Attachment 145225 Details for Bug 111481 – Merge last adg5f code

[patch] Merge last adg5f code

merge_last_amdgpu-for-5.3-rc6.patch (text/plain), 22.82 MB, created by Mathieu Belanger on 2019-08-31 22:15:36 UTC

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Creator: Mathieu Belanger

Created: 2019-08-31 22:15:36 UTC

Size: 22.82 MB

patch

obsolete

>diff -Naur linux-5.3-rc6/arch/x86/kernel/early-quirks.c linux-5.3-rc6-agd5fed/arch/x86/kernel/early-quirks.c
>--- linux-5.3-rc6/arch/x86/kernel/early-quirks.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/arch/x86/kernel/early-quirks.c	2019-08-31 15:01:11.825736165 -0500
>@@ -549,6 +549,7 @@
> 	INTEL_CNL_IDS(&gen9_early_ops),
> 	INTEL_ICL_11_IDS(&gen11_early_ops),
> 	INTEL_EHL_IDS(&gen11_early_ops),
>+	INTEL_TGL_12_IDS(&gen11_early_ops),
> };
> 
> struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
>diff -Naur linux-5.3-rc6/.clang-format linux-5.3-rc6-agd5fed/.clang-format
>--- linux-5.3-rc6/.clang-format	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/.clang-format	1969-12-31 18:00:00.000000000 -0600
>@@ -1,493 +0,0 @@
>-# SPDX-License-Identifier: GPL-2.0
>-#
>-# clang-format configuration file. Intended for clang-format >= 4.
>-#
>-# For more information, see:
>-#
>-#   Documentation/process/clang-format.rst
>-#   https://clang.llvm.org/docs/ClangFormat.html
>-#   https://clang.llvm.org/docs/ClangFormatStyleOptions.html
>-#
>----
>-AccessModifierOffset: -4
>-AlignAfterOpenBracket: Align
>-AlignConsecutiveAssignments: false
>-AlignConsecutiveDeclarations: false
>-#AlignEscapedNewlines: Left # Unknown to clang-format-4.0
>-AlignOperands: true
>-AlignTrailingComments: false
>-AllowAllParametersOfDeclarationOnNextLine: false
>-AllowShortBlocksOnASingleLine: false
>-AllowShortCaseLabelsOnASingleLine: false
>-AllowShortFunctionsOnASingleLine: None
>-AllowShortIfStatementsOnASingleLine: false
>-AllowShortLoopsOnASingleLine: false
>-AlwaysBreakAfterDefinitionReturnType: None
>-AlwaysBreakAfterReturnType: None
>-AlwaysBreakBeforeMultilineStrings: false
>-AlwaysBreakTemplateDeclarations: false
>-BinPackArguments: true
>-BinPackParameters: true
>-BraceWrapping:
>-  AfterClass: false
>-  AfterControlStatement: false
>-  AfterEnum: false
>-  AfterFunction: true
>-  AfterNamespace: true
>-  AfterObjCDeclaration: false
>-  AfterStruct: false
>-  AfterUnion: false
>-  #AfterExternBlock: false # Unknown to clang-format-5.0
>-  BeforeCatch: false
>-  BeforeElse: false
>-  IndentBraces: false
>-  #SplitEmptyFunction: true # Unknown to clang-format-4.0
>-  #SplitEmptyRecord: true # Unknown to clang-format-4.0
>-  #SplitEmptyNamespace: true # Unknown to clang-format-4.0
>-BreakBeforeBinaryOperators: None
>-BreakBeforeBraces: Custom
>-#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0
>-BreakBeforeTernaryOperators: false
>-BreakConstructorInitializersBeforeComma: false
>-#BreakConstructorInitializers: BeforeComma # Unknown to clang-format-4.0
>-BreakAfterJavaFieldAnnotations: false
>-BreakStringLiterals: false
>-ColumnLimit: 80
>-CommentPragmas: '^ IWYU pragma:'
>-#CompactNamespaces: false # Unknown to clang-format-4.0
>-ConstructorInitializerAllOnOneLineOrOnePerLine: false
>-ConstructorInitializerIndentWidth: 8
>-ContinuationIndentWidth: 8
>-Cpp11BracedListStyle: false
>-DerivePointerAlignment: false
>-DisableFormat: false
>-ExperimentalAutoDetectBinPacking: false
>-#FixNamespaceComments: false # Unknown to clang-format-4.0
>-
>-# Taken from:
>-#   git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ \
>-#   | sed "s,^#define $[^[:space:]]*for_each[^[:space:]]*$(.*$,  - '\1'," \
>-#   | sort | uniq
>-ForEachMacros:
>-  - 'apei_estatus_for_each_section'
>-  - 'ata_for_each_dev'
>-  - 'ata_for_each_link'
>-  - '__ata_qc_for_each'
>-  - 'ata_qc_for_each'
>-  - 'ata_qc_for_each_raw'
>-  - 'ata_qc_for_each_with_internal'
>-  - 'ax25_for_each'
>-  - 'ax25_uid_for_each'
>-  - '__bio_for_each_bvec'
>-  - 'bio_for_each_bvec'
>-  - 'bio_for_each_integrity_vec'
>-  - '__bio_for_each_segment'
>-  - 'bio_for_each_segment'
>-  - 'bio_for_each_segment_all'
>-  - 'bio_list_for_each'
>-  - 'bip_for_each_vec'
>-  - 'blkg_for_each_descendant_post'
>-  - 'blkg_for_each_descendant_pre'
>-  - 'blk_queue_for_each_rl'
>-  - 'bond_for_each_slave'
>-  - 'bond_for_each_slave_rcu'
>-  - 'bpf_for_each_spilled_reg'
>-  - 'btree_for_each_safe128'
>-  - 'btree_for_each_safe32'
>-  - 'btree_for_each_safe64'
>-  - 'btree_for_each_safel'
>-  - 'card_for_each_dev'
>-  - 'cgroup_taskset_for_each'
>-  - 'cgroup_taskset_for_each_leader'
>-  - 'cpufreq_for_each_entry'
>-  - 'cpufreq_for_each_entry_idx'
>-  - 'cpufreq_for_each_valid_entry'
>-  - 'cpufreq_for_each_valid_entry_idx'
>-  - 'css_for_each_child'
>-  - 'css_for_each_descendant_post'
>-  - 'css_for_each_descendant_pre'
>-  - 'device_for_each_child_node'
>-  - 'drm_atomic_crtc_for_each_plane'
>-  - 'drm_atomic_crtc_state_for_each_plane'
>-  - 'drm_atomic_crtc_state_for_each_plane_state'
>-  - 'drm_atomic_for_each_plane_damage'
>-  - 'drm_connector_for_each_possible_encoder'
>-  - 'drm_for_each_connector_iter'
>-  - 'drm_for_each_crtc'
>-  - 'drm_for_each_encoder'
>-  - 'drm_for_each_encoder_mask'
>-  - 'drm_for_each_fb'
>-  - 'drm_for_each_legacy_plane'
>-  - 'drm_for_each_plane'
>-  - 'drm_for_each_plane_mask'
>-  - 'drm_for_each_privobj'
>-  - 'drm_mm_for_each_hole'
>-  - 'drm_mm_for_each_node'
>-  - 'drm_mm_for_each_node_in_range'
>-  - 'drm_mm_for_each_node_safe'
>-  - 'flow_action_for_each'
>-  - 'for_each_active_drhd_unit'
>-  - 'for_each_active_iommu'
>-  - 'for_each_available_child_of_node'
>-  - 'for_each_bio'
>-  - 'for_each_board_func_rsrc'
>-  - 'for_each_bvec'
>-  - 'for_each_card_components'
>-  - 'for_each_card_links'
>-  - 'for_each_card_links_safe'
>-  - 'for_each_card_prelinks'
>-  - 'for_each_card_rtds'
>-  - 'for_each_card_rtds_safe'
>-  - 'for_each_cgroup_storage_type'
>-  - 'for_each_child_of_node'
>-  - 'for_each_clear_bit'
>-  - 'for_each_clear_bit_from'
>-  - 'for_each_cmsghdr'
>-  - 'for_each_compatible_node'
>-  - 'for_each_component_dais'
>-  - 'for_each_component_dais_safe'
>-  - 'for_each_comp_order'
>-  - 'for_each_console'
>-  - 'for_each_cpu'
>-  - 'for_each_cpu_and'
>-  - 'for_each_cpu_not'
>-  - 'for_each_cpu_wrap'
>-  - 'for_each_dev_addr'
>-  - 'for_each_dma_cap_mask'
>-  - 'for_each_dpcm_be'
>-  - 'for_each_dpcm_be_rollback'
>-  - 'for_each_dpcm_be_safe'
>-  - 'for_each_dpcm_fe'
>-  - 'for_each_drhd_unit'
>-  - 'for_each_dss_dev'
>-  - 'for_each_efi_memory_desc'
>-  - 'for_each_efi_memory_desc_in_map'
>-  - 'for_each_element'
>-  - 'for_each_element_extid'
>-  - 'for_each_element_id'
>-  - 'for_each_endpoint_of_node'
>-  - 'for_each_evictable_lru'
>-  - 'for_each_fib6_node_rt_rcu'
>-  - 'for_each_fib6_walker_rt'
>-  - 'for_each_free_mem_range'
>-  - 'for_each_free_mem_range_reverse'
>-  - 'for_each_func_rsrc'
>-  - 'for_each_hstate'
>-  - 'for_each_if'
>-  - 'for_each_iommu'
>-  - 'for_each_ip_tunnel_rcu'
>-  - 'for_each_irq_nr'
>-  - 'for_each_link_codecs'
>-  - 'for_each_lru'
>-  - 'for_each_matching_node'
>-  - 'for_each_matching_node_and_match'
>-  - 'for_each_memblock'
>-  - 'for_each_memblock_type'
>-  - 'for_each_memcg_cache_index'
>-  - 'for_each_mem_pfn_range'
>-  - 'for_each_mem_range'
>-  - 'for_each_mem_range_rev'
>-  - 'for_each_migratetype_order'
>-  - 'for_each_msi_entry'
>-  - 'for_each_msi_entry_safe'
>-  - 'for_each_net'
>-  - 'for_each_netdev'
>-  - 'for_each_netdev_continue'
>-  - 'for_each_netdev_continue_rcu'
>-  - 'for_each_netdev_feature'
>-  - 'for_each_netdev_in_bond_rcu'
>-  - 'for_each_netdev_rcu'
>-  - 'for_each_netdev_reverse'
>-  - 'for_each_netdev_safe'
>-  - 'for_each_net_rcu'
>-  - 'for_each_new_connector_in_state'
>-  - 'for_each_new_crtc_in_state'
>-  - 'for_each_new_mst_mgr_in_state'
>-  - 'for_each_new_plane_in_state'
>-  - 'for_each_new_private_obj_in_state'
>-  - 'for_each_node'
>-  - 'for_each_node_by_name'
>-  - 'for_each_node_by_type'
>-  - 'for_each_node_mask'
>-  - 'for_each_node_state'
>-  - 'for_each_node_with_cpus'
>-  - 'for_each_node_with_property'
>-  - 'for_each_of_allnodes'
>-  - 'for_each_of_allnodes_from'
>-  - 'for_each_of_cpu_node'
>-  - 'for_each_of_pci_range'
>-  - 'for_each_old_connector_in_state'
>-  - 'for_each_old_crtc_in_state'
>-  - 'for_each_old_mst_mgr_in_state'
>-  - 'for_each_oldnew_connector_in_state'
>-  - 'for_each_oldnew_crtc_in_state'
>-  - 'for_each_oldnew_mst_mgr_in_state'
>-  - 'for_each_oldnew_plane_in_state'
>-  - 'for_each_oldnew_plane_in_state_reverse'
>-  - 'for_each_oldnew_private_obj_in_state'
>-  - 'for_each_old_plane_in_state'
>-  - 'for_each_old_private_obj_in_state'
>-  - 'for_each_online_cpu'
>-  - 'for_each_online_node'
>-  - 'for_each_online_pgdat'
>-  - 'for_each_pci_bridge'
>-  - 'for_each_pci_dev'
>-  - 'for_each_pci_msi_entry'
>-  - 'for_each_populated_zone'
>-  - 'for_each_possible_cpu'
>-  - 'for_each_present_cpu'
>-  - 'for_each_prime_number'
>-  - 'for_each_prime_number_from'
>-  - 'for_each_process'
>-  - 'for_each_process_thread'
>-  - 'for_each_property_of_node'
>-  - 'for_each_registered_fb'
>-  - 'for_each_reserved_mem_region'
>-  - 'for_each_rtd_codec_dai'
>-  - 'for_each_rtd_codec_dai_rollback'
>-  - 'for_each_rtdcom'
>-  - 'for_each_rtdcom_safe'
>-  - 'for_each_set_bit'
>-  - 'for_each_set_bit_from'
>-  - 'for_each_sg'
>-  - 'for_each_sg_dma_page'
>-  - 'for_each_sg_page'
>-  - 'for_each_sibling_event'
>-  - 'for_each_subelement'
>-  - 'for_each_subelement_extid'
>-  - 'for_each_subelement_id'
>-  - '__for_each_thread'
>-  - 'for_each_thread'
>-  - 'for_each_zone'
>-  - 'for_each_zone_zonelist'
>-  - 'for_each_zone_zonelist_nodemask'
>-  - 'fwnode_for_each_available_child_node'
>-  - 'fwnode_for_each_child_node'
>-  - 'fwnode_graph_for_each_endpoint'
>-  - 'gadget_for_each_ep'
>-  - 'genradix_for_each'
>-  - 'genradix_for_each_from'
>-  - 'hash_for_each'
>-  - 'hash_for_each_possible'
>-  - 'hash_for_each_possible_rcu'
>-  - 'hash_for_each_possible_rcu_notrace'
>-  - 'hash_for_each_possible_safe'
>-  - 'hash_for_each_rcu'
>-  - 'hash_for_each_safe'
>-  - 'hctx_for_each_ctx'
>-  - 'hlist_bl_for_each_entry'
>-  - 'hlist_bl_for_each_entry_rcu'
>-  - 'hlist_bl_for_each_entry_safe'
>-  - 'hlist_for_each'
>-  - 'hlist_for_each_entry'
>-  - 'hlist_for_each_entry_continue'
>-  - 'hlist_for_each_entry_continue_rcu'
>-  - 'hlist_for_each_entry_continue_rcu_bh'
>-  - 'hlist_for_each_entry_from'
>-  - 'hlist_for_each_entry_from_rcu'
>-  - 'hlist_for_each_entry_rcu'
>-  - 'hlist_for_each_entry_rcu_bh'
>-  - 'hlist_for_each_entry_rcu_notrace'
>-  - 'hlist_for_each_entry_safe'
>-  - '__hlist_for_each_rcu'
>-  - 'hlist_for_each_safe'
>-  - 'hlist_nulls_for_each_entry'
>-  - 'hlist_nulls_for_each_entry_from'
>-  - 'hlist_nulls_for_each_entry_rcu'
>-  - 'hlist_nulls_for_each_entry_safe'
>-  - 'i3c_bus_for_each_i2cdev'
>-  - 'i3c_bus_for_each_i3cdev'
>-  - 'ide_host_for_each_port'
>-  - 'ide_port_for_each_dev'
>-  - 'ide_port_for_each_present_dev'
>-  - 'idr_for_each_entry'
>-  - 'idr_for_each_entry_continue'
>-  - 'idr_for_each_entry_ul'
>-  - 'inet_bind_bucket_for_each'
>-  - 'inet_lhash2_for_each_icsk_rcu'
>-  - 'key_for_each'
>-  - 'key_for_each_safe'
>-  - 'klp_for_each_func'
>-  - 'klp_for_each_func_safe'
>-  - 'klp_for_each_func_static'
>-  - 'klp_for_each_object'
>-  - 'klp_for_each_object_safe'
>-  - 'klp_for_each_object_static'
>-  - 'kvm_for_each_memslot'
>-  - 'kvm_for_each_vcpu'
>-  - 'list_for_each'
>-  - 'list_for_each_codec'
>-  - 'list_for_each_codec_safe'
>-  - 'list_for_each_entry'
>-  - 'list_for_each_entry_continue'
>-  - 'list_for_each_entry_continue_rcu'
>-  - 'list_for_each_entry_continue_reverse'
>-  - 'list_for_each_entry_from'
>-  - 'list_for_each_entry_from_rcu'
>-  - 'list_for_each_entry_from_reverse'
>-  - 'list_for_each_entry_lockless'
>-  - 'list_for_each_entry_rcu'
>-  - 'list_for_each_entry_reverse'
>-  - 'list_for_each_entry_safe'
>-  - 'list_for_each_entry_safe_continue'
>-  - 'list_for_each_entry_safe_from'
>-  - 'list_for_each_entry_safe_reverse'
>-  - 'list_for_each_prev'
>-  - 'list_for_each_prev_safe'
>-  - 'list_for_each_safe'
>-  - 'llist_for_each'
>-  - 'llist_for_each_entry'
>-  - 'llist_for_each_entry_safe'
>-  - 'llist_for_each_safe'
>-  - 'media_device_for_each_entity'
>-  - 'media_device_for_each_intf'
>-  - 'media_device_for_each_link'
>-  - 'media_device_for_each_pad'
>-  - 'mp_bvec_for_each_page'
>-  - 'mp_bvec_for_each_segment'
>-  - 'nanddev_io_for_each_page'
>-  - 'netdev_for_each_lower_dev'
>-  - 'netdev_for_each_lower_private'
>-  - 'netdev_for_each_lower_private_rcu'
>-  - 'netdev_for_each_mc_addr'
>-  - 'netdev_for_each_uc_addr'
>-  - 'netdev_for_each_upper_dev_rcu'
>-  - 'netdev_hw_addr_list_for_each'
>-  - 'nft_rule_for_each_expr'
>-  - 'nla_for_each_attr'
>-  - 'nla_for_each_nested'
>-  - 'nlmsg_for_each_attr'
>-  - 'nlmsg_for_each_msg'
>-  - 'nr_neigh_for_each'
>-  - 'nr_neigh_for_each_safe'
>-  - 'nr_node_for_each'
>-  - 'nr_node_for_each_safe'
>-  - 'of_for_each_phandle'
>-  - 'of_property_for_each_string'
>-  - 'of_property_for_each_u32'
>-  - 'pci_bus_for_each_resource'
>-  - 'ping_portaddr_for_each_entry'
>-  - 'plist_for_each'
>-  - 'plist_for_each_continue'
>-  - 'plist_for_each_entry'
>-  - 'plist_for_each_entry_continue'
>-  - 'plist_for_each_entry_safe'
>-  - 'plist_for_each_safe'
>-  - 'pnp_for_each_card'
>-  - 'pnp_for_each_dev'
>-  - 'protocol_for_each_card'
>-  - 'protocol_for_each_dev'
>-  - 'queue_for_each_hw_ctx'
>-  - 'radix_tree_for_each_slot'
>-  - 'radix_tree_for_each_tagged'
>-  - 'rbtree_postorder_for_each_entry_safe'
>-  - 'rdma_for_each_port'
>-  - 'resource_list_for_each_entry'
>-  - 'resource_list_for_each_entry_safe'
>-  - 'rhl_for_each_entry_rcu'
>-  - 'rhl_for_each_rcu'
>-  - 'rht_for_each'
>-  - 'rht_for_each_from'
>-  - 'rht_for_each_entry'
>-  - 'rht_for_each_entry_from'
>-  - 'rht_for_each_entry_rcu'
>-  - 'rht_for_each_entry_rcu_from'
>-  - 'rht_for_each_entry_safe'
>-  - 'rht_for_each_rcu'
>-  - 'rht_for_each_rcu_from'
>-  - '__rq_for_each_bio'
>-  - 'rq_for_each_bvec'
>-  - 'rq_for_each_segment'
>-  - 'scsi_for_each_prot_sg'
>-  - 'scsi_for_each_sg'
>-  - 'sctp_for_each_hentry'
>-  - 'sctp_skb_for_each'
>-  - 'shdma_for_each_chan'
>-  - '__shost_for_each_device'
>-  - 'shost_for_each_device'
>-  - 'sk_for_each'
>-  - 'sk_for_each_bound'
>-  - 'sk_for_each_entry_offset_rcu'
>-  - 'sk_for_each_from'
>-  - 'sk_for_each_rcu'
>-  - 'sk_for_each_safe'
>-  - 'sk_nulls_for_each'
>-  - 'sk_nulls_for_each_from'
>-  - 'sk_nulls_for_each_rcu'
>-  - 'snd_array_for_each'
>-  - 'snd_pcm_group_for_each_entry'
>-  - 'snd_soc_dapm_widget_for_each_path'
>-  - 'snd_soc_dapm_widget_for_each_path_safe'
>-  - 'snd_soc_dapm_widget_for_each_sink_path'
>-  - 'snd_soc_dapm_widget_for_each_source_path'
>-  - 'tb_property_for_each'
>-  - 'tcf_exts_for_each_action'
>-  - 'udp_portaddr_for_each_entry'
>-  - 'udp_portaddr_for_each_entry_rcu'
>-  - 'usb_hub_for_each_child'
>-  - 'v4l2_device_for_each_subdev'
>-  - 'v4l2_m2m_for_each_dst_buf'
>-  - 'v4l2_m2m_for_each_dst_buf_safe'
>-  - 'v4l2_m2m_for_each_src_buf'
>-  - 'v4l2_m2m_for_each_src_buf_safe'
>-  - 'virtio_device_for_each_vq'
>-  - 'xa_for_each'
>-  - 'xa_for_each_marked'
>-  - 'xa_for_each_start'
>-  - 'xas_for_each'
>-  - 'xas_for_each_conflict'
>-  - 'xas_for_each_marked'
>-  - 'zorro_for_each_dev'
>-
>-#IncludeBlocks: Preserve # Unknown to clang-format-5.0
>-IncludeCategories:
>-  - Regex: '.*'
>-    Priority: 1
>-IncludeIsMainRegex: '(Test)?$'
>-IndentCaseLabels: false
>-#IndentPPDirectives: None # Unknown to clang-format-5.0
>-IndentWidth: 8
>-IndentWrappedFunctionNames: false
>-JavaScriptQuotes: Leave
>-JavaScriptWrapImports: true
>-KeepEmptyLinesAtTheStartOfBlocks: false
>-MacroBlockBegin: ''
>-MacroBlockEnd: ''
>-MaxEmptyLinesToKeep: 1
>-NamespaceIndentation: Inner
>-#ObjCBinPackProtocolList: Auto # Unknown to clang-format-5.0
>-ObjCBlockIndentWidth: 8
>-ObjCSpaceAfterProperty: true
>-ObjCSpaceBeforeProtocolList: true
>-
>-# Taken from git's rules
>-#PenaltyBreakAssignment: 10 # Unknown to clang-format-4.0
>-PenaltyBreakBeforeFirstCallParameter: 30
>-PenaltyBreakComment: 10
>-PenaltyBreakFirstLessLess: 0
>-PenaltyBreakString: 10
>-PenaltyExcessCharacter: 100
>-PenaltyReturnTypeOnItsOwnLine: 60
>-
>-PointerAlignment: Right
>-ReflowComments: false
>-SortIncludes: false
>-#SortUsingDeclarations: false # Unknown to clang-format-4.0
>-SpaceAfterCStyleCast: false
>-SpaceAfterTemplateKeyword: true
>-SpaceBeforeAssignmentOperators: true
>-#SpaceBeforeCtorInitializerColon: true # Unknown to clang-format-5.0
>-#SpaceBeforeInheritanceColon: true # Unknown to clang-format-5.0
>-SpaceBeforeParens: ControlStatements
>-#SpaceBeforeRangeBasedForLoopColon: true # Unknown to clang-format-5.0
>-SpaceInEmptyParentheses: false
>-SpacesBeforeTrailingComments: 1
>-SpacesInAngles: false
>-SpacesInContainerLiterals: false
>-SpacesInCStyleCastParentheses: false
>-SpacesInParentheses: false
>-SpacesInSquareBrackets: false
>-Standard: Cpp03
>-TabWidth: 8
>-UseTab: Always
>-...
>diff -Naur linux-5.3-rc6/.cocciconfig linux-5.3-rc6-agd5fed/.cocciconfig
>--- linux-5.3-rc6/.cocciconfig	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/.cocciconfig	1969-12-31 18:00:00.000000000 -0600
>@@ -1,3 +0,0 @@
>-[spatch]
>-	options = --timeout 200
>-	options = --use-gitgrep
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/arm,pl11x.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/arm,pl11x.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/arm,pl11x.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/arm,pl11x.txt	2019-08-31 15:01:11.823736165 -0500
>@@ -39,9 +39,11 @@
> 
> - port: describes LCD panel signals, following the common binding
> 	for video transmitter interfaces; see
>-	Documentation/devicetree/bindings/media/video-interfaces.txt;
>-	when it is a TFT panel, the port's endpoint must define the
>-	following property:
>+	Documentation/devicetree/bindings/media/video-interfaces.txt
>+
>+Deprecated properties:
>+	The port's endbpoint subnode had this, now deprecated property
>+	in the past. Drivers should be able to survive without it:
> 
> 	- arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values,
> 		defining the way CLD pads are wired up; first value
>@@ -80,7 +82,6 @@
> 		port {
> 			clcd_pads: endpoint {
> 				remote-endpoint = <&clcd_panel>;
>-				arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
> 			};
> 		};
> 
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/bridge/sii902x.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/bridge/sii902x.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/bridge/sii902x.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/bridge/sii902x.txt	2019-08-31 15:01:11.823736165 -0500
>@@ -26,9 +26,8 @@
> 	- clocks: phandle and clock specifier for each clock listed in
>            the clock-names property
> 	- clock-names: "mclk"
>-	   Describes SII902x MCLK input. MCLK is used to produce
>-	   HDMI audio CTS values. This property is required if
>-	   "#sound-dai-cells"-property is present. This property follows
>+	   Describes SII902x MCLK input. MCLK can be used to produce
>+	   HDMI audio CTS values. This property follows
> 	   Documentation/devicetree/bindings/clock/clock-bindings.txt
> 	   consumer binding.
> 
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,26 +0,0 @@
>-Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel
>-
>-This binding is compatible with the simple-panel binding, which is specified
>-in simple-panel.txt in this directory.
>-
>-Required properties:
>-- compatible: should be "ampire,am-480272h3tmqw-t01h"
>-
>-Optional properties:
>-- power-supply: regulator to provide the supply voltage
>-- enable-gpios: GPIO pin to enable or disable the panel
>-- backlight: phandle of the backlight device attached to the panel
>-
>-Optional nodes:
>-- Video port for RGB input.
>-
>-Example:
>-	panel_rgb: panel-rgb {
>-		compatible = "ampire,am-480272h3tmqw-t01h";
>-		enable-gpios = <&gpioa 8 1>;
>-		port {
>-			panel_in_rgb: endpoint {
>-				remote-endpoint = <&controller_out_rgb>;
>-			};
>-		};
>-	};
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml	2019-08-31 15:01:11.823736165 -0500
>@@ -0,0 +1,42 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/ampire,am-480272h3tmqw-t01h.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel
>+
>+maintainers:
>+  - Yannick Fertre <yannick.fertre@st.com>
>+  - Thierry Reding <treding@nvidia.com>
>+
>+allOf:
>+  - $ref: panel-common.yaml#
>+
>+properties:
>+  compatible:
>+    const: ampire,am-480272h3tmqw-t01h
>+
>+  power-supply: true
>+  enable-gpios: true
>+  backlight: true
>+  port: true
>+
>+required:
>+  - compatible
>+
>+additionalProperties: false
>+
>+examples:
>+  - |
>+    panel_rgb: panel {
>+      compatible = "ampire,am-480272h3tmqw-t01h";
>+      enable-gpios = <&gpioa 8 1>;
>+      port {
>+        panel_in_rgb: endpoint {
>+          remote-endpoint = <&controller_out_rgb>;
>+        };
>+      };
>+    };
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,9 +0,0 @@
>-Armadeus ST0700 Adapt. A Santek ST0700I5Y-RBSLW 7.0" WVGA (800x480) TFT with
>-an adapter board.
>-
>-Required properties:
>-- compatible: "armadeus,st0700-adapt"
>-- power-supply: see panel-common.txt
>-
>-Optional properties:
>-- backlight: see panel-common.txt
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/armadeus,st0700-adapt.yaml	2019-08-31 15:01:11.823736165 -0500
>@@ -0,0 +1,33 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/armadeus,st0700-adapt.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: Armadeus ST0700 Adapter
>+
>+description:
>+  A Santek ST0700I5Y-RBSLW 7.0" WVGA (800x480) TFT with an adapter board.
>+
>+maintainers:
>+  - '"SÃ©bastien Szymanski" <sebastien.szymanski@armadeus.com>'
>+  - Thierry Reding <thierry.reding@gmail.com>
>+
>+allOf:
>+  - $ref: panel-common.yaml#
>+
>+properties:
>+  compatible:
>+    const: armadeus,st0700-adapt
>+
>+  power-supply: true
>+  backlight: true
>+  port: true
>+
>+additionalProperties: false
>+
>+required:
>+  - compatible
>+  - power-supply
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/arm,versatile-tft-panel.txt	2019-08-31 15:01:11.823736165 -0500
>@@ -10,7 +10,7 @@
> - compatible: should be "arm,versatile-tft-panel"
> 
> Required subnodes:
>-- port: see display/panel/panel-common.txt, graph.txt
>+- port: see display/panel/panel-common.yaml, graph.txt
> 
> 
> Example:
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,12 +0,0 @@
>-Banana Pi 7" (S070WV20-CT16) TFT LCD Panel
>-
>-Required properties:
>-- compatible: should be "bananapi,s070wv20-ct16"
>-- power-supply: see ./panel-common.txt
>-
>-Optional properties:
>-- enable-gpios: see ./simple-panel.txt
>-- backlight: see ./simple-panel.txt
>-
>-This binding is compatible with the simple-panel binding, which is specified
>-in ./simple-panel.txt.
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.yaml	2019-08-31 15:01:11.823736165 -0500
>@@ -0,0 +1,31 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/bananapi,s070wv20-ct16.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: Banana Pi 7" (S070WV20-CT16) TFT LCD Panel
>+
>+maintainers:
>+  - Chen-Yu Tsai <wens@csie.org>
>+  - Thierry Reding <thierry.reding@gmail.com>
>+
>+allOf:
>+  - $ref: panel-common.yaml#
>+
>+properties:
>+  compatible:
>+    const: bananapi,s070wv20-ct16
>+
>+  power-supply: true
>+  backlight: true
>+  enable-gpios: true
>+  port: true
>+
>+additionalProperties: false
>+
>+required:
>+  - compatible
>+  - power-supply
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/boe,himax8279d.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/boe,himax8279d.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/boe,himax8279d.txt	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/boe,himax8279d.txt	2019-08-31 15:01:11.823736165 -0500
>@@ -0,0 +1,24 @@
>+Boe Himax8279d 1200x1920 TFT LCD panel
>+
>+Required properties:
>+- compatible: should be "boe,himax8279d8p" and one of: "boe,himax8279d10p"
>+- reg: DSI virtual channel of the peripheral
>+- enable-gpios: panel enable gpio
>+- pp33-gpios: a GPIO phandle for the 3.3v pin that provides the supply voltage
>+- pp18-gpios: a GPIO phandle for the 1.8v pin that provides the supply voltage
>+
>+Optional properties:
>+- backlight: phandle of the backlight device attached to the panel
>+
>+Example:
>+
>+	&mipi_dsi {
>+		panel {
>+			compatible = "boe,himax8279d8p", "boe,himax8279d10p";
>+			reg = <0>;
>+			backlight = <&backlight>;
>+			enable-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;
>+			pp33-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
>+			pp18-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
>+		};
>+	};
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,13 +0,0 @@
>-DLC Display Co. DLC0700YZG-1 7.0" WSVGA TFT LCD panel
>-
>-Required properties:
>-- compatible: should be "dlc,dlc0700yzg-1"
>-- power-supply: See simple-panel.txt
>-
>-Optional properties:
>-- reset-gpios: See panel-common.txt
>-- enable-gpios: See simple-panel.txt
>-- backlight: See simple-panel.txt
>-
>-This binding is compatible with the simple-panel binding, which is specified
>-in simple-panel.txt in this directory.
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.yaml	2019-08-31 15:01:11.823736165 -0500
>@@ -0,0 +1,31 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/dlc,dlc0700yzg-1.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: DLC Display Co. DLC0700YZG-1 7.0" WSVGA TFT LCD panel
>+
>+maintainers:
>+  - Philipp Zabel <p.zabel@pengutronix.de>
>+  - Thierry Reding <thierry.reding@gmail.com>
>+
>+allOf:
>+  - $ref: panel-common.yaml#
>+
>+properties:
>+  compatible:
>+    const: dlc,dlc0700yzg-1
>+
>+  reset-gpios: true
>+  enable-gpios: true
>+  backlight: true
>+  port: true
>+
>+additionalProperties: false
>+
>+required:
>+  - compatible
>+  - power-supply
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/edt,et-series.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/edt,et-series.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/edt,et-series.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/edt,et-series.txt	2019-08-31 15:01:11.823736165 -0500
>@@ -40,7 +40,7 @@
> | Identifier      | compatbile          | description                         |
> +=================+=====================+=====================================+
> | ETM0700G0DH6    | edt,etm070080dh6    | WVGA TFT Display with capacitive    |
>-|                 |                     | Touchscreen                         |
>+|                 | edt,etm0700g0dh6    | Touchscreen                         |
> +-----------------+---------------------+-------------------------------------+
> | ETM0700G0BDH6   | edt,etm070080bdh6   | Same as ETM0700G0DH6 but with       |
> |                 |                     | inverted pixel clock.               |
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt	2019-08-31 15:01:11.823736165 -0500
>@@ -0,0 +1,12 @@
>+GiantPlus 3.0" (320x240 pixels) 24-bit TFT LCD panel
>+
>+Required properties:
>+- compatible: should be "giantplus,gpm940b0"
>+- power-supply: as specified in the base binding
>+
>+Optional properties:
>+- backlight: as specified in the base binding
>+- enable-gpios: as specified in the base binding
>+
>+This binding is compatible with the simple-panel binding, which is specified
>+in simple-panel.txt in this directory.
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,7 +0,0 @@
>-Innolux Corporation 10.1" EE101IA-01D WXGA (1280x800) LVDS panel
>-
>-Required properties:
>-- compatible: should be "innolux,ee101ia-01d"
>-
>-This binding is compatible with the lvds-panel binding, which is specified
>-in panel-lvds.txt in this directory.
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.yaml	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,31 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/innolux,ee101ia-01d.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: Innolux Corporation 10.1" EE101IA-01D WXGA (1280x800) LVDS panel
>+
>+maintainers:
>+  - Heiko Stuebner <heiko.stuebner@bq.com>
>+  - Thierry Reding <thierry.reding@gmail.com>
>+
>+allOf:
>+  - $ref: lvds.yaml#
>+
>+properties:
>+  compatible:
>+    items:
>+      - const: innolux,ee101ia-01d
>+      - {} # panel-lvds, but not listed here to avoid false select
>+
>+  backlight: true
>+  enable-gpios: true
>+  power-supply: true
>+  width-mm: true
>+  height-mm: true
>+  panel-timing: true
>+  port: true
>+
>+additionalProperties: false
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/kingdisplay,kd035g6-54nt.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/kingdisplay,kd035g6-54nt.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/kingdisplay,kd035g6-54nt.txt	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/kingdisplay,kd035g6-54nt.txt	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,42 @@
>+King Display KD035G6-54NT 3.5" (320x240 pixels) 24-bit TFT LCD panel
>+
>+Required properties:
>+- compatible: should be "kingdisplay,kd035g6-54nt"
>+- power-supply: See panel-common.txt
>+- reset-gpios: See panel-common.txt
>+
>+Optional properties:
>+- backlight: see panel-common.txt
>+
>+The generic bindings for the SPI slaves documented in [1] also apply.
>+
>+The device node can contain one 'port' child node with one child
>+'endpoint' node, according to the bindings defined in [2]. This
>+node should describe panel's video bus.
>+
>+[1]: Documentation/devicetree/bindings/spi/spi-bus.txt
>+[2]: Documentation/devicetree/bindings/graph.txt
>+
>+Example:
>+
>+&spi {
>+	panel@0 {
>+		compatible = "kingdisplay,kd035g6-54nt";
>+		reg = <0>;
>+
>+		spi-max-frequency = <3125000>;
>+		spi-3wire;
>+		spi-cs-high;
>+
>+		reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>;
>+
>+		backlight = <&backlight>;
>+		power-supply = <&ldo6>;
>+
>+		port {
>+			panel_input: endpoint {
>+				remote-endpoint = <&panel_output>;
>+			};
>+		};
>+	};
>+};
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/lvds.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/lvds.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/lvds.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/lvds.yaml	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,107 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/lvds.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: LVDS Display Panel
>+
>+maintainers:
>+  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>+  - Thierry Reding <thierry.reding@gmail.com>
>+
>+description: |+
>+  LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
>+  incompatible data link layers have been used over time to transmit image data
>+  to LVDS panels. This bindings supports display panels compatible with the
>+  following specifications.
>+
>+  [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
>+  1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
>+  [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
>+  Semiconductor
>+  [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
>+  Electronics Standards Association (VESA)
>+
>+  Device compatible with those specifications have been marketed under the
>+  FPD-Link and FlatLink brands.
>+
>+allOf:
>+  - $ref: panel-common.yaml#
>+
>+properties:
>+  compatible:
>+    contains:
>+      const: panel-lvds
>+    description:
>+      Shall contain "panel-lvds" in addition to a mandatory panel-specific
>+      compatible string defined in individual panel bindings. The "panel-lvds"
>+      value shall never be used on its own.
>+
>+  data-mapping:
>+    enum:
>+      - jeida-18
>+      - jeida-24
>+      - vesa-24
>+    description: |
>+      The color signals mapping order.
>+
>+      LVDS data mappings are defined as follows.
>+
>+      - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
>+        [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
>+
>+      Slot	    0       1       2       3       4       5       6
>+            ________________                         _________________
>+      Clock	                \_______________________/
>+              ______  ______  ______  ______  ______  ______  ______
>+      DATA0	><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
>+      DATA1	><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
>+      DATA2	><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
>+
>+      - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
>+        specifications. Data are transferred as follows on 4 LVDS lanes.
>+
>+      Slot	    0       1       2       3       4       5       6
>+            ________________                         _________________
>+      Clock	                \_______________________/
>+              ______  ______  ______  ______  ______  ______  ______
>+      DATA0	><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
>+      DATA1	><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
>+      DATA2	><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
>+      DATA3	><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
>+
>+      - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
>+        Data are transferred as follows on 4 LVDS lanes.
>+
>+      Slot	    0       1       2       3       4       5       6
>+            ________________                         _________________
>+      Clock	                \_______________________/
>+              ______  ______  ______  ______  ______  ______  ______
>+      DATA0	><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
>+      DATA1	><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
>+      DATA2	><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
>+      DATA3	><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
>+
>+      Control signals are mapped as follows.
>+
>+      CTL0: HSync
>+      CTL1: VSync
>+      CTL2: Data Enable
>+      CTL3: 0
>+
>+  data-mirror:
>+    type: boolean
>+    description:
>+      If set, reverse the bit order described in the data mappings below on all
>+      data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.
>+
>+required:
>+  - compatible
>+  - data-mapping
>+  - width-mm
>+  - height-mm
>+  - panel-timing
>+  - port
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,47 +0,0 @@
>-Mitsubishi AA204XD12 LVDS Display Panel
>-=======================================
>-
>-The AA104XD12 is a 10.4" XGA TFT-LCD display panel.
>-
>-These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt
>-with the following device-specific properties.
>-
>-
>-Required properties:
>-
>-- compatible: Shall contain "mitsubishi,aa121td01" and "panel-lvds", in that
>-  order.
>-- vcc-supply: Reference to the regulator powering the panel VCC pins.
>-
>-
>-Example
>--------
>-
>-panel {
>-	compatible = "mitsubishi,aa104xd12", "panel-lvds";
>-	vcc-supply = <&vcc_3v3>;
>-
>-	width-mm = <210>;
>-	height-mm = <158>;
>-
>-	data-mapping = "jeida-24";
>-
>-	panel-timing {
>-		/* 1024x768 @65Hz */
>-		clock-frequency = <65000000>;
>-		hactive = <1024>;
>-		vactive = <768>;
>-		hsync-len = <136>;
>-		hfront-porch = <20>;
>-		hback-porch = <160>;
>-		vfront-porch = <3>;
>-		vback-porch = <29>;
>-		vsync-len = <6>;
>-	};
>-
>-	port {
>-		panel_in: endpoint {
>-			remote-endpoint = <&lvds_encoder>;
>-		};
>-	};
>-};
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,75 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/mitsubishi,aa104xd12.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: Mitsubishi AA104XD12 10.4" XGA LVDS Display Panel
>+
>+maintainers:
>+  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>+  - Thierry Reding <thierry.reding@gmail.com>
>+
>+allOf:
>+  - $ref: lvds.yaml#
>+
>+properties:
>+  compatible:
>+    items:
>+      - const: mitsubishi,aa104xd12
>+      - {} # panel-lvds, but not listed here to avoid false select
>+
>+  vcc-supply:
>+    description: Reference to the regulator powering the panel VCC pins.
>+
>+  data-mapping:
>+    const: jeida-24
>+
>+  width-mm:
>+    const: 210
>+
>+  height-mm:
>+    const: 158
>+
>+  panel-timing: true
>+  port: true
>+
>+additionalProperties: false
>+
>+required:
>+  - compatible
>+  - vcc-supply
>+
>+examples:
>+  - |+
>+
>+    panel {
>+      compatible = "mitsubishi,aa104xd12", "panel-lvds";
>+      vcc-supply = <&vcc_3v3>;
>+
>+      width-mm = <210>;
>+      height-mm = <158>;
>+
>+      data-mapping = "jeida-24";
>+
>+      panel-timing {
>+        /* 1024x768 @65Hz */
>+        clock-frequency = <65000000>;
>+        hactive = <1024>;
>+        vactive = <768>;
>+        hsync-len = <136>;
>+        hfront-porch = <20>;
>+        hback-porch = <160>;
>+        vfront-porch = <3>;
>+        vback-porch = <29>;
>+        vsync-len = <6>;
>+      };
>+
>+      port {
>+        panel_in: endpoint {
>+          remote-endpoint = <&lvds_encoder>;
>+        };
>+      };
>+    };
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,47 +0,0 @@
>-Mitsubishi AA121TD01 LVDS Display Panel
>-=======================================
>-
>-The AA121TD01 is a 12.1" WXGA TFT-LCD display panel.
>-
>-These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt
>-with the following device-specific properties.
>-
>-
>-Required properties:
>-
>-- compatible: Shall contain "mitsubishi,aa121td01" and "panel-lvds", in that
>-  order.
>-- vcc-supply: Reference to the regulator powering the panel VCC pins.
>-
>-
>-Example
>--------
>-
>-panel {
>-	compatible = "mitsubishi,aa121td01", "panel-lvds";
>-	vcc-supply = <&vcc_3v3>;
>-
>-	width-mm = <261>;
>-	height-mm = <163>;
>-
>-	data-mapping = "jeida-24";
>-
>-	panel-timing {
>-		/* 1280x800 @60Hz */
>-		clock-frequency = <71000000>;
>-		hactive = <1280>;
>-		vactive = <800>;
>-		hsync-len = <70>;
>-		hfront-porch = <20>;
>-		hback-porch = <70>;
>-		vsync-len = <5>;
>-		vfront-porch = <3>;
>-		vback-porch = <15>;
>-	};
>-
>-	port {
>-		panel_in: endpoint {
>-			remote-endpoint = <&lvds_encoder>;
>-		};
>-	};
>-};
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.yaml	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,74 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/mitsubishi,aa121td01.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: Mitsubishi AA121TD01 12.1" WXGA LVDS Display Panel
>+
>+maintainers:
>+  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>+  - Thierry Reding <thierry.reding@gmail.com>
>+
>+allOf:
>+  - $ref: lvds.yaml#
>+
>+properties:
>+  compatible:
>+    items:
>+      - const: mitsubishi,aa121td01
>+      - {} # panel-lvds, but not listed here to avoid false select
>+
>+  vcc-supply:
>+    description: Reference to the regulator powering the panel VCC pins.
>+
>+  data-mapping:
>+    const: jeida-24
>+
>+  width-mm:
>+    const: 261
>+
>+  height-mm:
>+    const: 163
>+
>+  panel-timing: true
>+  port: true
>+
>+additionalProperties: false
>+
>+required:
>+  - compatible
>+  - vcc-supply
>+
>+examples:
>+  - |+
>+    panel {
>+      compatible = "mitsubishi,aa121td01", "panel-lvds";
>+      vcc-supply = <&vcc_3v3>;
>+
>+      width-mm = <261>;
>+      height-mm = <163>;
>+
>+      data-mapping = "jeida-24";
>+
>+      panel-timing {
>+        /* 1280x800 @60Hz */
>+        clock-frequency = <71000000>;
>+        hactive = <1280>;
>+        vactive = <800>;
>+        hsync-len = <70>;
>+        hfront-porch = <20>;
>+        hback-porch = <70>;
>+        vsync-len = <5>;
>+        vfront-porch = <3>;
>+        vback-porch = <15>;
>+      };
>+
>+      port {
>+        panel_in: endpoint {
>+          remote-endpoint = <&lvds_encoder>;
>+        };
>+      };
>+    };
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m05dtc.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m05dtc.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m05dtc.txt	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m05dtc.txt	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,12 @@
>+OrtusTech COM37H3M05DTC Blanview 3.7" VGA portrait TFT-LCD panel
>+
>+Required properties:
>+- compatible: should be "ortustech,com37h3m05dtc"
>+
>+Optional properties:
>+- enable-gpios: GPIO pin to enable or disable the panel
>+- backlight: phandle of the backlight device attached to the panel
>+- power-supply: phandle of the regulator that provides the supply voltage
>+
>+This binding is compatible with the simple-panel binding, which is specified
>+in simple-panel.txt in this directory.
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m99dtc.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m99dtc.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m99dtc.txt	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/ortustech,com37h3m99dtc.txt	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,12 @@
>+OrtusTech COM37H3M99DTC Blanview 3.7" VGA portrait TFT-LCD panel
>+
>+Required properties:
>+- compatible: should be "ortustech,com37h3m99dtc"
>+
>+Optional properties:
>+- enable-gpios: GPIO pin to enable or disable the panel
>+- backlight: phandle of the backlight device attached to the panel
>+- power-supply: phandle of the regulator that provides the supply voltage
>+
>+This binding is compatible with the simple-panel binding, which is specified
>+in simple-panel.txt in this directory.
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel-common.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel-common.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel-common.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel-common.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,101 +0,0 @@
>-Common Properties for Display Panel
>-===================================
>-
>-This document defines device tree properties common to several classes of
>-display panels. It doesn't constitue a device tree binding specification by
>-itself but is meant to be referenced by device tree bindings.
>-
>-When referenced from panel device tree bindings the properties defined in this
>-document are defined as follows. The panel device tree bindings are
>-responsible for defining whether each property is required or optional.
>-
>-
>-Descriptive Properties
>-----------------------
>-
>-- width-mm,
>-- height-mm: The width-mm and height-mm specify the width and height of the
>-  physical area where images are displayed. These properties are expressed in
>-  millimeters and rounded to the closest unit.
>-
>-- label: The label property specifies a symbolic name for the panel as a
>-  string suitable for use by humans. It typically contains a name inscribed on
>-  the system (e.g. as an affixed label) or specified in the system's
>-  documentation (e.g. in the user's manual).
>-
>-  If no such name exists, and unless the property is mandatory according to
>-  device tree bindings, it shall rather be omitted than constructed of
>-  non-descriptive information. For instance an LCD panel in a system that
>-  contains a single panel shall not be labelled "LCD" if that name is not
>-  inscribed on the system or used in a descriptive fashion in system
>-  documentation.
>-
>-
>-Display Timings
>----------------
>-
>-- panel-timing: Most display panels are restricted to a single resolution and
>-  require specific display timings. The panel-timing subnode expresses those
>-  timings as specified in the timing subnode section of the display timing
>-  bindings defined in
>-  Documentation/devicetree/bindings/display/panel/display-timing.txt.
>-
>-
>-Connectivity
>-------------
>-
>-- ports: Panels receive video data through one or multiple connections. While
>-  the nature of those connections is specific to the panel type, the
>-  connectivity is expressed in a standard fashion using ports as specified in
>-  the device graph bindings defined in
>-  Documentation/devicetree/bindings/graph.txt.
>-
>-- ddc-i2c-bus: Some panels expose EDID information through an I2C-compatible
>-  bus such as DDC2 or E-DDC. For such panels the ddc-i2c-bus contains a
>-  phandle to the system I2C controller connected to that bus.
>-
>-
>-Control I/Os
>-------------
>-
>-Many display panels can be controlled through pins driven by GPIOs. The nature
>-and timing of those control signals are device-specific and left for panel
>-device tree bindings to specify. The following GPIO specifiers can however be
>-used for panels that implement compatible control signals.
>-
>-- enable-gpios: Specifier for a GPIO connected to the panel enable control
>-  signal. The enable signal is active high and enables operation of the panel.
>-  This property can also be used for panels implementing an active low power
>-  down signal, which is a negated version of the enable signal. Active low
>-  enable signals (or active high power down signals) can be supported by
>-  inverting the GPIO specifier polarity flag.
>-
>-  Note that the enable signal control panel operation only and must not be
>-  confused with a backlight enable signal.
>-
>-- reset-gpios: Specifier for a GPIO coonnected to the panel reset control
>-  signal. The reset signal is active low and resets the panel internal logic
>-  while active. Active high reset signals can be supported by inverting the
>-  GPIO specifier polarity flag.
>-
>-Power
>------
>-
>-- power-supply: display panels require power to be supplied. While several
>-  panels need more than one power supply with panel-specific constraints
>-  governing the order and timings of the power supplies, in many cases a single
>-  power supply is sufficient, either because the panel has a single power rail,
>-  or because all its power rails can be driven by the same supply. In that case
>-  the power-supply property specifies the supply powering the panel as a phandle
>-  to a regulator.
>-
>-Backlight
>----------
>-
>-Most display panels include a backlight. Some of them also include a backlight
>-controller exposed through a control bus such as I2C or DSI. Others expose
>-backlight control through GPIO, PWM or other signals connected to an external
>-backlight controller.
>-
>-- backlight: For panels whose backlight is controlled by an external backlight
>-  controller, this property contains a phandle that references the controller.
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel-common.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel-common.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel-common.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel-common.yaml	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,149 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: Common Properties for Display Panels
>+
>+maintainers:
>+  - Thierry Reding <thierry.reding@gmail.com>
>+  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>+
>+description: |
>+  This document defines device tree properties common to several classes of
>+  display panels. It doesn't constitue a device tree binding specification by
>+  itself but is meant to be referenced by device tree bindings.
>+
>+  When referenced from panel device tree bindings the properties defined in this
>+  document are defined as follows. The panel device tree bindings are
>+  responsible for defining whether each property is required or optional.
>+
>+properties:
>+  # Descriptive Properties
>+  width-mm:
>+    description:
>+      Specifies the width of the physical area where images are displayed. This
>+      property is expressed in millimeters and rounded to the closest unit.
>+
>+  height-mm:
>+    description:
>+      Specifies the height of the physical area where images are displayed. This
>+      property is expressed in millimeters and rounded to the closest unit.
>+
>+  label:
>+    description: |
>+      The label property specifies a symbolic name for the panel as a
>+      string suitable for use by humans. It typically contains a name inscribed
>+      on the system (e.g. as an affixed label) or specified in the system's
>+      documentation (e.g. in the user's manual).
>+
>+      If no such name exists, and unless the property is mandatory according to
>+      device tree bindings, it shall rather be omitted than constructed of
>+      non-descriptive information. For instance an LCD panel in a system that
>+      contains a single panel shall not be labelled "LCD" if that name is not
>+      inscribed on the system or used in a descriptive fashion in system
>+      documentation.
>+
>+  rotation:
>+    description:
>+      Display rotation in degrees counter clockwise (0,90,180,270)
>+    allOf:
>+      - $ref: /schemas/types.yaml#/definitions/uint32
>+      - enum: [ 0, 90, 180, 270 ]
>+
>+  # Display Timings
>+  panel-timing:
>+    type: object
>+    description:
>+      Most display panels are restricted to a single resolution and
>+      require specific display timings. The panel-timing subnode expresses those
>+      timings as specified in the timing subnode section of the display timing
>+      bindings defined in
>+      Documentation/devicetree/bindings/display/panel/display-timing.txt.
>+
>+  # Connectivity
>+  port:
>+    type: object
>+
>+  ports:
>+    type: object
>+    description:
>+      Panels receive video data through one or multiple connections. While
>+      the nature of those connections is specific to the panel type, the
>+      connectivity is expressed in a standard fashion using ports as specified
>+      in the device graph bindings defined in
>+      Documentation/devicetree/bindings/graph.txt.
>+
>+  ddc-i2c-bus:
>+    $ref: /schemas/types.yaml#/definitions/phandle
>+    description:
>+      Some panels expose EDID information through an I2C-compatible
>+      bus such as DDC2 or E-DDC. For such panels the ddc-i2c-bus contains a
>+      phandle to the system I2C controller connected to that bus.
>+
>+  no-hpd:
>+    type: boolean
>+    description:
>+      This panel is supposed to communicate that it's ready via HPD
>+      (hot plug detect) signal, but the signal isn't hooked up so we should
>+      hardcode the max delay from the panel spec when powering up the panel.
>+
>+  # Control I/Os
>+
>+  # Many display panels can be controlled through pins driven by GPIOs. The nature
>+  # and timing of those control signals are device-specific and left for panel
>+  # device tree bindings to specify. The following GPIO specifiers can however be
>+  # used for panels that implement compatible control signals.
>+
>+  enable-gpios:
>+    maxItems: 1
>+    description: |
>+      Specifier for a GPIO connected to the panel enable control signal. The
>+      enable signal is active high and enables operation of the panel. This
>+      property can also be used for panels implementing an active low power down
>+      signal, which is a negated version of the enable signal. Active low enable
>+      signals (or active high power down signals) can be supported by inverting
>+      the GPIO specifier polarity flag.
>+
>+      Note that the enable signal control panel operation only and must not be
>+      confused with a backlight enable signal.
>+
>+  reset-gpios:
>+    maxItems: 1
>+    description:
>+      Specifier for a GPIO connected to the panel reset control signal.
>+      The reset signal is active low and resets the panel internal logic
>+      while active. Active high reset signals can be supported by inverting the
>+      GPIO specifier polarity flag.
>+
>+  # Power
>+  power-supply:
>+    description:
>+      Display panels require power to be supplied. While several panels need
>+      more than one power supply with panel-specific constraints governing the
>+      order and timings of the power supplies, in many cases a single power
>+      supply is sufficient, either because the panel has a single power rail, or
>+      because all its power rails can be driven by the same supply. In that case
>+      the power-supply property specifies the supply powering the panel as a
>+      phandle to a regulator.
>+
>+  # Backlight
>+
>+  # Most display panels include a backlight. Some of them also include a backlight
>+  # controller exposed through a control bus such as I2C or DSI. Others expose
>+  # backlight control through GPIO, PWM or other signals connected to an external
>+  # backlight controller.
>+
>+  backlight:
>+    $ref: /schemas/types.yaml#/definitions/phandle
>+    description:
>+      For panels whose backlight is controlled by an external backlight
>+      controller, this property contains a phandle that references the
>+      controller.
>+
>+dependencies:
>+  width-mm: [ height-mm ]
>+  height-mm: [ width-mm ]
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel-lvds.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel-lvds.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel-lvds.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel-lvds.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,121 +0,0 @@
>-LVDS Display Panel
>-==================
>-
>-LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
>-incompatible data link layers have been used over time to transmit image data
>-to LVDS panels. This bindings supports display panels compatible with the
>-following specifications.
>-
>-[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
>-1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
>-[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
>-Semiconductor
>-[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
>-Electronics Standards Association (VESA)
>-
>-Device compatible with those specifications have been marketed under the
>-FPD-Link and FlatLink brands.
>-
>-
>-Required properties:
>-
>-- compatible: Shall contain "panel-lvds" in addition to a mandatory
>-  panel-specific compatible string defined in individual panel bindings. The
>-  "panel-lvds" value shall never be used on its own.
>-- width-mm: See panel-common.txt.
>-- height-mm: See panel-common.txt.
>-- data-mapping: The color signals mapping order, "jeida-18", "jeida-24"
>-  or "vesa-24".
>-
>-Optional properties:
>-
>-- label: See panel-common.txt.
>-- gpios: See panel-common.txt.
>-- backlight: See panel-common.txt.
>-- power-supply: See panel-common.txt.
>-- data-mirror: If set, reverse the bit order described in the data mappings
>-  below on all data lanes, transmitting bits for slots 6 to 0 instead of
>-  0 to 6.
>-
>-Required nodes:
>-
>-- panel-timing: See panel-common.txt.
>-- ports: See panel-common.txt. These bindings require a single port subnode
>-  corresponding to the panel LVDS input.
>-
>-
>-LVDS data mappings are defined as follows.
>-
>-- "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
>-  [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
>-
>-Slot	    0       1       2       3       4       5       6
>-	________________                         _________________
>-Clock	                \_______________________/
>-	  ______  ______  ______  ______  ______  ______  ______
>-DATA0	><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
>-DATA1	><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
>-DATA2	><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
>-
>-- "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
>-  specifications. Data are transferred as follows on 4 LVDS lanes.
>-
>-Slot	    0       1       2       3       4       5       6
>-	________________                         _________________
>-Clock	                \_______________________/
>-	  ______  ______  ______  ______  ______  ______  ______
>-DATA0	><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
>-DATA1	><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
>-DATA2	><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
>-DATA3	><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
>-
>-- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
>-  Data are transferred as follows on 4 LVDS lanes.
>-
>-Slot	    0       1       2       3       4       5       6
>-	________________                         _________________
>-Clock	                \_______________________/
>-	  ______  ______  ______  ______  ______  ______  ______
>-DATA0	><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
>-DATA1	><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
>-DATA2	><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
>-DATA3	><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
>-
>-Control signals are mapped as follows.
>-
>-CTL0: HSync
>-CTL1: VSync
>-CTL2: Data Enable
>-CTL3: 0
>-
>-
>-Example
>--------
>-
>-panel {
>-	compatible = "mitsubishi,aa121td01", "panel-lvds";
>-
>-	width-mm = <261>;
>-	height-mm = <163>;
>-
>-	data-mapping = "jeida-24";
>-
>-	panel-timing {
>-		/* 1280x800 @60Hz */
>-		clock-frequency = <71000000>;
>-		hactive = <1280>;
>-		vactive = <800>;
>-		hsync-len = <70>;
>-		hfront-porch = <20>;
>-		hback-porch = <70>;
>-		vsync-len = <5>;
>-		vfront-porch = <3>;
>-		vback-porch = <15>;
>-	};
>-
>-	port {
>-		panel_in: endpoint {
>-			remote-endpoint = <&lvds_encoder>;
>-		};
>-	};
>-};
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/panel.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/panel.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,4 +0,0 @@
>-Common display properties
>--------------------------
>-
>-- rotation:	Display rotation in degrees counter clockwise (0,90,180,270)
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,14 +0,0 @@
>-PDA 91-00156-A0 5.0" WVGA TFT LCD panel
>-
>-Required properties:
>-- compatible: should be "pda,91-00156-a0"
>-- power-supply: this panel requires a single power supply. A phandle to a
>-regulator needs to be specified here. Compatible with panel-common binding which
>-is specified in the panel-common.txt in this directory.
>-- backlight: this panel's backlight is controlled by an external backlight
>-controller. A phandle to this controller needs to be specified here.
>-Compatible with panel-common binding which is specified in the panel-common.txt
>-in this directory.
>-
>-This binding is compatible with the simple-panel binding, which is specified
>-in simple-panel.txt in this directory.
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/pda,91-00156-a0.yaml	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,31 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/pda,91-00156-a0.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: PDA 91-00156-A0 5.0" WVGA TFT LCD panel
>+
>+maintainers:
>+  - Cristian Birsan <cristian.birsan@microchip.com>
>+  - Thierry Reding <thierry.reding@gmail.com>
>+
>+allOf:
>+  - $ref: panel-common.yaml#
>+
>+properties:
>+  compatible:
>+    const: pda,91-00156-a0
>+
>+  power-supply: true
>+  backlight: true
>+  port: true
>+
>+additionalProperties: false
>+
>+required:
>+  - compatible
>+  - power-supply
>+  - backlight
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,49 +0,0 @@
>-This binding covers the official 7" (800x480) Raspberry Pi touchscreen
>-panel.
>-
>-This DSI panel contains:
>-
>-- TC358762 DSI->DPI bridge
>-- Atmel microcontroller on I2C for power sequencing the DSI bridge and
>-  controlling backlight
>-- Touchscreen controller on I2C for touch input
>-
>-and this binding covers the DSI display parts but not its touch input.
>-
>-Required properties:
>-- compatible:	Must be "raspberrypi,7inch-touchscreen-panel"
>-- reg:		Must be "45"
>-- port:		See panel-common.txt
>-
>-Example:
>-
>-dsi1: dsi@7e700000 {
>-	#address-cells = <1>;
>-	#size-cells = <0>;
>-	<...>
>-
>-	port {
>-		dsi_out_port: endpoint {
>-			remote-endpoint = <&panel_dsi_port>;
>-		};
>-	};
>-};
>-
>-i2c_dsi: i2c {
>-	compatible = "i2c-gpio";
>-	#address-cells = <1>;
>-	#size-cells = <0>;
>-	gpios = <&gpio 28 0
>-		 &gpio 29 0>;
>-
>-	lcd@45 {
>-		compatible = "raspberrypi,7inch-touchscreen-panel";
>-		reg = <0x45>;
>-
>-		port {
>-			panel_dsi_port: endpoint {
>-				remote-endpoint = <&dsi_out_port>;
>-			};
>-		};
>-	};
>-};
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/raspberrypi,7inch-touchscreen.yaml	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,71 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/raspberrypi,7inch-touchscreen.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: The official 7" (800x480) Raspberry Pi touchscreen
>+
>+maintainers:
>+  - Eric Anholt <eric@anholt.net>
>+  - Thierry Reding <thierry.reding@gmail.com>
>+
>+description: |+
>+  This DSI panel contains:
>+
>+  - TC358762 DSI->DPI bridge
>+  - Atmel microcontroller on I2C for power sequencing the DSI bridge and
>+    controlling backlight
>+  - Touchscreen controller on I2C for touch input
>+
>+  and this binding covers the DSI display parts but not its touch input.
>+
>+properties:
>+  compatible:
>+    const: raspberrypi,7inch-touchscreen-panel
>+
>+  reg:
>+    const: 0x45
>+
>+  port: true
>+
>+required:
>+  - compatible
>+  - reg
>+  - port
>+
>+additionalProperties: false
>+
>+examples:
>+  - |+
>+    dsi1: dsi {
>+      #address-cells = <1>;
>+      #size-cells = <0>;
>+
>+      port {
>+        dsi_out_port: endpoint {
>+          remote-endpoint = <&panel_dsi_port>;
>+        };
>+      };
>+    };
>+
>+    i2c_dsi: i2c {
>+      compatible = "i2c-gpio";
>+      #address-cells = <1>;
>+      #size-cells = <0>;
>+      scl-gpios = <&gpio 28 0>;
>+      sda-gpios = <&gpio 29 0>;
>+
>+      lcd@45 {
>+        compatible = "raspberrypi,7inch-touchscreen-panel";
>+        reg = <0x45>;
>+
>+        port {
>+          panel_dsi_port: endpoint {
>+            remote-endpoint = <&dsi_out_port>;
>+          };
>+        };
>+      };
>+    };
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,41 @@
>+Raydium RM67171 OLED LCD panel with MIPI-DSI protocol
>+
>+Required properties:
>+- compatible: 		"raydium,rm67191"
>+- reg:			virtual channel for MIPI-DSI protocol
>+			must be <0>
>+- dsi-lanes:		number of DSI lanes to be used
>+			must be <3> or <4>
>+- port: 		input port node with endpoint definition as
>+			defined in Documentation/devicetree/bindings/graph.txt;
>+			the input port should be connected to a MIPI-DSI device
>+			driver
>+
>+Optional properties:
>+- reset-gpios:		a GPIO spec for the RST_B GPIO pin
>+- v3p3-supply:		phandle to 3.3V regulator that powers the VDD_3V3 pin
>+- v1p8-supply:		phandle to 1.8V regulator that powers the VDD_1V8 pin
>+- width-mm:		see panel-common.txt
>+- height-mm:		see panel-common.txt
>+- video-mode:		0 - burst-mode
>+			1 - non-burst with sync event
>+			2 - non-burst with sync pulse
>+
>+Example:
>+
>+	panel@0 {
>+		compatible = "raydium,rm67191";
>+		reg = <0>;
>+		pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>;
>+		pinctrl-names = "default";
>+		reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
>+		dsi-lanes = <4>;
>+		width-mm = <68>;
>+		height-mm = <121>;
>+
>+		port {
>+			panel_in: endpoint {
>+				remote-endpoint = <&mipi_out>;
>+			};
>+		};
>+	};
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.txt	2019-08-31 15:01:11.824736165 -0500
>@@ -5,6 +5,9 @@
> - reg: DSI virtual channel of the peripheral
> - reset-gpios: panel reset gpio
> - backlight: phandle of the backlight device attached to the panel
>+- vcc-supply: phandle of the regulator that provides the vcc supply voltage.
>+- iovcc-supply: phandle of the regulator that provides the iovcc supply
>+  voltage.
> 
> Example:
> 
>@@ -14,5 +17,7 @@
> 			reg = <0>;
> 			backlight = <&backlight>;
> 			reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
>+			vcc-supply = <&reg_2v8_p>;
>+			iovcc-supply = <&reg_1v8_p>;
> 		};
> 	};
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,41 +0,0 @@
>-Solomon Goldentek Display GKTW70SDAE4SE LVDS Display Panel
>-==========================================================
>-
>-The GKTW70SDAE4SE is a 7" WVGA TFT-LCD display panel.
>-
>-These DT bindings follow the LVDS panel bindings defined in panel-lvds.txt
>-with the following device-specific properties.
>-
>-Required properties:
>-
>-- compatible: Shall contain "sgd,gktw70sdae4se" and "panel-lvds", in that order.
>-
>-Example
>--------
>-
>-panel {
>-	compatible = "sgd,gktw70sdae4se", "panel-lvds";
>-
>-	width-mm = <153>;
>-	height-mm = <86>;
>-
>-	data-mapping = "jeida-18";
>-
>-	panel-timing {
>-		clock-frequency = <32000000>;
>-		hactive = <800>;
>-		vactive = <480>;
>-		hback-porch = <39>;
>-		hfront-porch = <39>;
>-		vback-porch = <29>;
>-		vfront-porch = <13>;
>-		hsync-len = <47>;
>-		vsync-len = <2>;
>-	};
>-
>-	port {
>-		panel_in: endpoint {
>-			remote-endpoint = <&lvds_encoder>;
>-		};
>-	};
>-};
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.yaml	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,68 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/sgd,gktw70sdae4se.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: Solomon Goldentek Display GKTW70SDAE4SE 7" WVGA LVDS Display Panel
>+
>+maintainers:
>+  - Neil Armstrong <narmstrong@baylibre.com>
>+  - Thierry Reding <thierry.reding@gmail.com>
>+
>+allOf:
>+  - $ref: lvds.yaml#
>+
>+properties:
>+  compatible:
>+    items:
>+      - const: sgd,gktw70sdae4se
>+      - {} # panel-lvds, but not listed here to avoid false select
>+
>+  data-mapping:
>+    const: jeida-18
>+
>+  width-mm:
>+    const: 153
>+
>+  height-mm:
>+    const: 86
>+
>+  panel-timing: true
>+  port: true
>+
>+additionalProperties: false
>+
>+required:
>+  - compatible
>+
>+examples:
>+  - |+
>+    panel {
>+      compatible = "sgd,gktw70sdae4se", "panel-lvds";
>+
>+      width-mm = <153>;
>+      height-mm = <86>;
>+
>+      data-mapping = "jeida-18";
>+
>+      panel-timing {
>+        clock-frequency = <32000000>;
>+        hactive = <800>;
>+        vactive = <480>;
>+        hback-porch = <39>;
>+        hfront-porch = <39>;
>+        vback-porch = <29>;
>+        vfront-porch = <13>;
>+        hsync-len = <47>;
>+        vsync-len = <2>;
>+      };
>+
>+      port {
>+        panel_in: endpoint {
>+          remote-endpoint = <&lvds_encoder>;
>+        };
>+      };
>+    };
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sharp,ld-d5116z01b.txt	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,26 @@
>+Sharp LD-D5116Z01B 12.3" WUXGA+ eDP panel
>+
>+Required properties:
>+- compatible: should be "sharp,ld-d5116z01b"
>+- power-supply: regulator to provide the VCC supply voltage (3.3 volts)
>+
>+This binding is compatible with the simple-panel binding.
>+
>+The device node can contain one 'port' child node with one child
>+'endpoint' node, according to the bindings defined in [1]. This
>+node should describe panel's video bus.
>+
>+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
>+
>+Example:
>+
>+	panel: panel {
>+		compatible = "sharp,ld-d5116z01b";
>+		power-supply = <&vlcd_3v3>;
>+
>+		port {
>+			panel_ep: endpoint {
>+				remote-endpoint = <&bridge_out_ep>;
>+			};
>+		};
>+	};
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sharp,lq070y3dg3b.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sharp,lq070y3dg3b.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sharp,lq070y3dg3b.txt	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sharp,lq070y3dg3b.txt	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,12 @@
>+Sharp LQ070Y3DG3B 7.0" WVGA landscape TFT LCD panel
>+
>+Required properties:
>+- compatible: should be "sharp,lq070y3dg3b"
>+
>+Optional properties:
>+- enable-gpios: GPIO pin to enable or disable the panel
>+- backlight: phandle of the backlight device attached to the panel
>+- power-supply: phandle of the regulator that provides the supply voltage
>+
>+This binding is compatible with the simple-panel binding, which is specified
>+in simple-panel.txt in this directory.
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,12 @@
>+Sharp 2.0" (240x160 pixels) 16-bit TFT LCD panel
>+
>+Required properties:
>+- compatible: should be "sharp,ls020b1dd01d"
>+- power-supply: as specified in the base binding
>+
>+Optional properties:
>+- backlight: as specified in the base binding
>+- enable-gpios: as specified in the base binding
>+
>+This binding is compatible with the simple-panel binding, which is specified
>+in simple-panel.txt in this directory.
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/simple-panel.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/simple-panel.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/simple-panel.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/simple-panel.txt	2019-08-31 15:01:11.824736165 -0500
>@@ -1,28 +1 @@
>-Simple display panel
>-====================
>-
>-panel node
>-----------
>-
>-Required properties:
>-- power-supply: See panel-common.txt
>-
>-Optional properties:
>-- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
>-- enable-gpios: GPIO pin to enable or disable the panel
>-- backlight: phandle of the backlight device attached to the panel
>-- no-hpd: This panel is supposed to communicate that it's ready via HPD
>-  (hot plug detect) signal, but the signal isn't hooked up so we should
>-  hardcode the max delay from the panel spec when powering up the panel.
>-
>-Example:
>-
>-	panel: panel {
>-		compatible = "cptt,claa101wb01";
>-		ddc-i2c-bus = <&panelddc>;
>-
>-		power-supply = <&vdd_pnl_reg>;
>-		enable-gpios = <&gpio 90 0>;
>-
>-		backlight = <&backlight>;
>-	};
>+See panel-common.yaml in this directory.
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-TFC S9700RTWV43TR-01B 7" Three Five Corp 800x480 LCD panel with
>-resistive touch
>-
>-The panel is found on TI AM335x-evm.
>-
>-Required properties:
>-- compatible: should be "tfc,s9700rtwv43tr-01b"
>-- power-supply: See panel-common.txt
>-
>-Optional properties:
>-- enable-gpios: GPIO pin to enable or disable the panel, if there is one
>-- backlight: phandle of the backlight device attached to the panel
>-
>-This binding is compatible with the simple-panel binding, which is specified
>-in simple-panel.txt in this directory.
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tfc,s9700rtwv43tr-01b.yaml	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,33 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/tfc,s9700rtwv43tr-01b.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: TFC S9700RTWV43TR-01B 7" Three Five Corp 800x480 LCD panel with resistive touch
>+
>+maintainers:
>+  - Jyri Sarha <jsarha@ti.com>
>+  - Thierry Reding <thierry.reding@gmail.com>
>+
>+description: |+
>+  The panel is found on TI AM335x-evm.
>+
>+allOf:
>+  - $ref: panel-common.yaml#
>+
>+properties:
>+  compatible:
>+    const: tfc,s9700rtwv43tr-01b
>+
>+  enable-gpios: true
>+  backlight: true
>+  port: true
>+
>+additionalProperties: false
>+
>+required:
>+  - compatible
>+  - power-supply
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt	1969-12-31 18:00:00.000000000 -0600
>@@ -1,70 +0,0 @@
>-TPO TPG110 Panel
>-================
>-
>-This panel driver is a component that acts as an intermediary
>-between an RGB output and a variety of panels. The panel
>-driver is strapped up in electronics to the desired resolution
>-and other properties, and has a control interface over 3WIRE
>-SPI. By talking to the TPG110 over SPI, the strapped properties
>-can be discovered and the hardware is therefore mostly
>-self-describing.
>-
>-       +--------+
>-SPI -> |  TPO   | -> physical display
>-RGB -> | TPG110 |
>-       +--------+
>-
>-If some electrical strap or alternate resolution is desired,
>-this can be set up by taking software control of the display
>-over the SPI interface. The interface can also adjust
>-for properties of the display such as gamma correction and
>-certain electrical driving levels.
>-
>-The TPG110 does not know the physical dimensions of the panel
>-connected, so this needs to be specified in the device tree.
>-
>-It requires a GPIO line for control of its reset line.
>-
>-The serial protocol has line names that resemble I2C but the
>-protocol is not I2C but 3WIRE SPI.
>-
>-Required properties:
>-- compatible : one of:
>-  "ste,nomadik-nhk15-display", "tpo,tpg110"
>-  "tpo,tpg110"
>-- grestb-gpios : panel reset GPIO
>-- width-mm : see display/panel/panel-common.txt
>-- height-mm : see display/panel/panel-common.txt
>-
>-The device needs to be a child of an SPI bus, see
>-spi/spi-bus.txt. The SPI child must set the following
>-properties:
>-- spi-3wire
>-- spi-max-frequency = <3000000>;
>-as these are characteristics of this device.
>-
>-The device node can contain one 'port' child node with one child
>-'endpoint' node, according to the bindings defined in
>-media/video-interfaces.txt. This node should describe panel's video bus.
>-
>-Example
>--------
>-
>-panel: display@0 {
>-	compatible = "tpo,tpg110";
>-	reg = <0>;
>-	spi-3wire;
>-	/* 320 ns min period ~= 3 MHz */
>-	spi-max-frequency = <3000000>;
>-	/* Width and height from data sheet */
>-	width-mm = <116>;
>-	height-mm = <87>;
>-	grestb-gpios = <&foo_gpio 5 GPIO_ACTIVE_LOW>;
>-	backlight = <&bl>;
>-
>-	port {
>-		nomadik_clcd_panel: endpoint {
>-			remote-endpoint = <&foo>;
>-		};
>-	};
>-};
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml	2019-08-31 15:01:11.824736165 -0500
>@@ -0,0 +1,101 @@
>+# SPDX-License-Identifier: GPL-2.0
>+%YAML 1.2
>+---
>+$id: http://devicetree.org/schemas/display/panel/tpo,tpg110.yaml#
>+$schema: http://devicetree.org/meta-schemas/core.yaml#
>+
>+title: TPO TPG110 Panel
>+
>+maintainers:
>+  - Linus Walleij <linus.walleij@linaro.org>
>+  - Thierry Reding <thierry.reding@gmail.com>
>+
>+description: |+
>+  This panel driver is a component that acts as an intermediary
>+  between an RGB output and a variety of panels. The panel
>+  driver is strapped up in electronics to the desired resolution
>+  and other properties, and has a control interface over 3WIRE
>+  SPI. By talking to the TPG110 over SPI, the strapped properties
>+  can be discovered and the hardware is therefore mostly
>+  self-describing.
>+
>+         +--------+
>+  SPI -> |  TPO   | -> physical display
>+  RGB -> | TPG110 |
>+         +--------+
>+
>+  If some electrical strap or alternate resolution is desired,
>+  this can be set up by taking software control of the display
>+  over the SPI interface. The interface can also adjust
>+  for properties of the display such as gamma correction and
>+  certain electrical driving levels.
>+
>+  The TPG110 does not know the physical dimensions of the panel
>+  connected, so this needs to be specified in the device tree.
>+
>+  It requires a GPIO line for control of its reset line.
>+
>+  The serial protocol has line names that resemble I2C but the
>+  protocol is not I2C but 3WIRE SPI.
>+
>+
>+allOf:
>+  - $ref: panel-common.yaml#
>+
>+properties:
>+  compatible:
>+    oneOf:
>+      - items:
>+          - enum:
>+              - ste,nomadik-nhk15-display
>+          - const: tpo,tpg110
>+      - const: tpo,tpg110
>+
>+  reg: true
>+
>+  grestb-gpios:
>+    maxItems: 1
>+    description: panel reset GPIO
>+
>+  spi-3wire: true
>+
>+  spi-max-frequency:
>+    const: 3000000
>+
>+required:
>+  - compatible
>+  - reg
>+  - grestb-gpios
>+  - width-mm
>+  - height-mm
>+  - spi-3wire
>+  - spi-max-frequency
>+  - port
>+
>+examples:
>+  - |+
>+    spi {
>+      #address-cells = <1>;
>+      #size-cells = <0>;
>+
>+      panel: display@0 {
>+        compatible = "tpo,tpg110";
>+        reg = <0>;
>+        spi-3wire;
>+        /* 320 ns min period ~= 3 MHz */
>+        spi-max-frequency = <3000000>;
>+        /* Width and height from data sheet */
>+        width-mm = <116>;
>+        height-mm = <87>;
>+        grestb-gpios = <&foo_gpio 5 1>;
>+        backlight = <&bl>;
>+
>+        port {
>+          nomadik_clcd_panel: endpoint {
>+            remote-endpoint = <&foo>;
>+          };
>+        };
>+      };
>+    };
>+
>+...
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt	2019-08-31 15:01:11.824736165 -0500
>@@ -32,17 +32,6 @@
> - video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
> - video port 1 for either a panel or subsequent encoder
> 
>-the lvds panel described by
>-	Documentation/devicetree/bindings/display/panel/simple-panel.txt
>-
>-Panel required properties:
>-- ports for remote LVDS output
>-
>-Panel optional properties:
>-- data-mapping: should be "vesa-24","jeida-24" or "jeida-18".
>-This describes decribed by:
>-	Documentation/devicetree/bindings/display/panel/panel-lvds.txt
>-
> Example:
> 
> lvds_panel: lvds-panel {
>diff -Naur linux-5.3-rc6/Documentation/devicetree/bindings/display/ssd1307fb.txt linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/ssd1307fb.txt
>--- linux-5.3-rc6/Documentation/devicetree/bindings/display/ssd1307fb.txt	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/devicetree/bindings/display/ssd1307fb.txt	2019-08-31 15:01:11.824736165 -0500
>@@ -27,6 +27,15 @@
>   - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles.
>                          This needs to be the higher, the higher the capacitance
>                          of the OLED's pixels is
>+  - solomon,dclk-div: Clock divisor 1 to 16
>+  - solomon,dclk-frq: Clock frequency 0 to 15, higher value means higher
>+                      frequency
>+  - solomon,lookup-table: 8 bit value array of current drive pulse widths for
>+                          BANK0, and colors A, B, and C. Each value in range
>+                          of 31 to 63 for pulse widths of 32 to 64. Color D
>+                          is always width 64.
>+  - solomon,area-color-enable: Display uses color mode
>+  - solomon,low-power. Display runs in low power mode
> 
> [0]: Documentation/devicetree/bindings/pwm/pwm.txt
> 
>@@ -46,4 +55,5 @@
>         solomon,com-lrremap;
>         solomon,com-invdir;
>         solomon,com-offset = <32>;
>+        solomon,lookup-table = /bits/ 8 <0x3f 0x3f 0x3f 0x3f>;
> };
>diff -Naur linux-5.3-rc6/Documentation/gpu/drivers.rst linux-5.3-rc6-agd5fed/Documentation/gpu/drivers.rst
>--- linux-5.3-rc6/Documentation/gpu/drivers.rst	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/gpu/drivers.rst	2019-08-31 15:01:11.824736165 -0500
>@@ -11,7 +11,6 @@
>    meson
>    pl111
>    tegra
>-   tinydrm
>    tve200
>    v3d
>    vc4
>diff -Naur linux-5.3-rc6/Documentation/gpu/drm-kms-helpers.rst linux-5.3-rc6-agd5fed/Documentation/gpu/drm-kms-helpers.rst
>--- linux-5.3-rc6/Documentation/gpu/drm-kms-helpers.rst	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/gpu/drm-kms-helpers.rst	2019-08-31 15:01:11.824736165 -0500
>@@ -263,6 +263,18 @@
>                drm_dp_mst_topology_put_port
>                drm_dp_mst_get_mstb_malloc drm_dp_mst_put_mstb_malloc
> 
>+MIPI DBI Helper Functions Reference
>+===================================
>+
>+.. kernel-doc:: drivers/gpu/drm/drm_mipi_dbi.c
>+   :doc: overview
>+
>+.. kernel-doc:: include/drm/drm_mipi_dbi.h
>+   :internal:
>+
>+.. kernel-doc:: drivers/gpu/drm/drm_mipi_dbi.c
>+   :export:
>+
> MIPI DSI Helper Functions Reference
> ===================================
> 
>diff -Naur linux-5.3-rc6/Documentation/gpu/drm-mm.rst linux-5.3-rc6-agd5fed/Documentation/gpu/drm-mm.rst
>--- linux-5.3-rc6/Documentation/gpu/drm-mm.rst	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/gpu/drm-mm.rst	2019-08-31 15:01:11.825736165 -0500
>@@ -433,43 +433,11 @@
> created for the OPTIMUS range of multi-gpu platforms. To userspace PRIME
> buffers are dma-buf based file descriptors.
> 
>-Overview and Driver Interface
>------------------------------
>+Overview and Lifetime Rules
>+---------------------------
> 
>-Similar to GEM global names, PRIME file descriptors are also used to
>-share buffer objects across processes. They offer additional security:
>-as file descriptors must be explicitly sent over UNIX domain sockets to
>-be shared between applications, they can't be guessed like the globally
>-unique GEM names.
>-
>-Drivers that support the PRIME API must set the DRIVER_PRIME bit in the
>-struct :c:type:`struct drm_driver <drm_driver>`
>-driver_features field, and implement the prime_handle_to_fd and
>-prime_fd_to_handle operations.
>-
>-int (\*prime_handle_to_fd)(struct drm_device \*dev, struct drm_file
>-\*file_priv, uint32_t handle, uint32_t flags, int \*prime_fd); int
>-(\*prime_fd_to_handle)(struct drm_device \*dev, struct drm_file
>-\*file_priv, int prime_fd, uint32_t \*handle); Those two operations
>-convert a handle to a PRIME file descriptor and vice versa. Drivers must
>-use the kernel dma-buf buffer sharing framework to manage the PRIME file
>-descriptors. Similar to the mode setting API PRIME is agnostic to the
>-underlying buffer object manager, as long as handles are 32bit unsigned
>-integers.
>-
>-While non-GEM drivers must implement the operations themselves, GEM
>-drivers must use the :c:func:`drm_gem_prime_handle_to_fd()` and
>-:c:func:`drm_gem_prime_fd_to_handle()` helper functions. Those
>-helpers rely on the driver gem_prime_export and gem_prime_import
>-operations to create a dma-buf instance from a GEM object (dma-buf
>-exporter role) and to create a GEM object from a dma-buf instance
>-(dma-buf importer role).
>-
>-struct dma_buf \* (\*gem_prime_export)(struct drm_device \*dev,
>-struct drm_gem_object \*obj, int flags); struct drm_gem_object \*
>-(\*gem_prime_import)(struct drm_device \*dev, struct dma_buf
>-\*dma_buf); These two operations are mandatory for GEM drivers that
>-support PRIME.
>+.. kernel-doc:: drivers/gpu/drm/drm_prime.c
>+   :doc: overview and lifetime rules
> 
> PRIME Helper Functions
> ----------------------
>diff -Naur linux-5.3-rc6/Documentation/gpu/i915.rst linux-5.3-rc6-agd5fed/Documentation/gpu/i915.rst
>--- linux-5.3-rc6/Documentation/gpu/i915.rst	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/gpu/i915.rst	2019-08-31 15:01:11.825736165 -0500
>@@ -430,31 +430,31 @@
> GuC
> ===
> 
>+Firmware Layout
>+-------------------
>+
>+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
>+   :doc: Firmware Layout
>+
> GuC-specific firmware loader
> ----------------------------
> 
>-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c
>+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>    :internal:
> 
> GuC-based command submission
> ----------------------------
> 
>-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_submission.c
>+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>    :doc: GuC-based command submission
> 
>-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_submission.c
>+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>    :internal:
> 
>-GuC Firmware Layout
>--------------------
>-
>-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h
>-   :doc: GuC Firmware Layout
>-
> GuC Address Space
> -----------------
> 
>-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc.c
>+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
>    :doc: GuC Address Space
> 
> Tracing
>diff -Naur linux-5.3-rc6/Documentation/gpu/introduction.rst linux-5.3-rc6-agd5fed/Documentation/gpu/introduction.rst
>--- linux-5.3-rc6/Documentation/gpu/introduction.rst	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/gpu/introduction.rst	2019-08-31 15:01:11.825736165 -0500
>@@ -51,6 +51,22 @@
> 
> Also read the :ref:`guidelines for the kernel documentation at large <doc_guide>`.
> 
>+Documentation Requirements for kAPI
>+-----------------------------------
>+
>+All kernel APIs exported to other modules must be documented, including their
>+datastructures and at least a short introductory section explaining the overall
>+concepts. Documentation should be put into the code itself as kerneldoc comments
>+as much as reasonable.
>+
>+Do not blindly document everything, but document only what's relevant for driver
>+authors: Internal functions of drm.ko and definitely static functions should not
>+have formal kerneldoc comments. Use normal C comments if you feel like a comment
>+is warranted. You may use kerneldoc syntax in the comment, but it shall not
>+start with a /** kerneldoc marker. Similar for data structures, annotate
>+anything entirely private with ``/* private: */`` comments as per the
>+documentation guide.
>+
> Getting Started
> ===============
> 
>diff -Naur linux-5.3-rc6/Documentation/gpu/tinydrm.rst linux-5.3-rc6-agd5fed/Documentation/gpu/tinydrm.rst
>--- linux-5.3-rc6/Documentation/gpu/tinydrm.rst	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/gpu/tinydrm.rst	1969-12-31 18:00:00.000000000 -0600
>@@ -1,30 +0,0 @@
>-============================
>-drm/tinydrm Tiny DRM drivers
>-============================
>-
>-tinydrm is a collection of DRM drivers that are so small they can fit in a
>-single source file.
>-
>-Helpers
>-=======
>-
>-.. kernel-doc:: include/drm/tinydrm/tinydrm-helpers.h
>-   :internal:
>-
>-.. kernel-doc:: drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c
>-   :export:
>-
>-.. kernel-doc:: drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c
>-   :export:
>-
>-MIPI DBI Compatible Controllers
>-===============================
>-
>-.. kernel-doc:: drivers/gpu/drm/tinydrm/mipi-dbi.c
>-   :doc: overview
>-
>-.. kernel-doc:: include/drm/tinydrm/mipi-dbi.h
>-   :internal:
>-
>-.. kernel-doc:: drivers/gpu/drm/tinydrm/mipi-dbi.c
>-   :export:
>diff -Naur linux-5.3-rc6/Documentation/gpu/todo.rst linux-5.3-rc6-agd5fed/Documentation/gpu/todo.rst
>--- linux-5.3-rc6/Documentation/gpu/todo.rst	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/gpu/todo.rst	2019-08-31 15:01:11.825736165 -0500
>@@ -162,7 +162,7 @@
> 
> A lot of drivers forward gem mmap calls to dma-buf mmap for imported buffers.
> And also a lot of them forward dma-buf mmap to the gem mmap implementations.
>-Would be great to refactor this all into a set of small common helpers.
>+There's drm_gem_prime_mmap() for this now, but still needs to be rolled out.
> 
> Contact: Daniel Vetter
> 
>@@ -196,15 +196,6 @@
> 
> Contact: Daniel Vetter, Noralf Tronnes
> 
>-Remove the ->gem_prime_res_obj callback
>---------------------------------------------
>-
>-The ->gem_prime_res_obj callback can be removed from drivers by using the
>-reservation_object in the drm_gem_object. It may also be possible to use the
>-generic drm_gem_reservation_object_wait helper for waiting for a bo.
>-
>-Contact: Daniel Vetter
>-
> idr_init_base()
> ---------------
> 
>@@ -215,22 +206,13 @@
> 
> Contact: Daniel Vetter
> 
>-Defaults for .gem_prime_import and export
>------------------------------------------
>-
>-Most drivers don't need to set drm_driver->gem_prime_import and
>-->gem_prime_export now that drm_gem_prime_import() and drm_gem_prime_export()
>-are the default.
>-
> struct drm_gem_object_funcs
> ---------------------------
> 
> GEM objects can now have a function table instead of having the callbacks on the
> DRM driver struct. This is now the preferred way and drivers can be moved over.
> 
>-DRM_GEM_CMA_VMAP_DRIVER_OPS, DRM_GEM_SHMEM_DRIVER_OPS already support this, but
>-DRM_GEM_VRAM_DRIVER_PRIME does not yet and needs to be aligned with the previous
>-two. We also need a 2nd version of the CMA define that doesn't require the
>+We also need a 2nd version of the CMA define that doesn't require the
> vmapping to be present (different hook for prime importing). Plus this needs to
> be rolled out to all drivers using their own implementations, too.
> 
>@@ -317,19 +299,6 @@
> 
> Contact: Daniel Vetter
> 
>-Add missing kerneldoc for exported functions
>---------------------------------------------
>-
>-The DRM reference documentation is still lacking kerneldoc in a few areas. The
>-task would be to clean up interfaces like moving functions around between
>-files to better group them and improving the interfaces like dropping return
>-values for functions that never fail. Then write kerneldoc for all exported
>-functions and an overview section and integrate it all into the drm book.
>-
>-See https://dri.freedesktop.org/docs/drm/ for what's there already.
>-
>-Contact: Daniel Vetter
>-
> Make panic handling work
> ------------------------
> 
>@@ -393,6 +362,9 @@
>   this (together with the drm_minor->drm_device move) would allow us to remove
>   debugfs_init.
> 
>+- Drop the return code and error checking from all debugfs functions. Greg KH is
>+  working on this already.
>+
> Contact: Daniel Vetter
> 
> KMS cleanups
>@@ -440,38 +412,21 @@
> 
> Contact: Daniel Vetter
> 
>-Driver Specific
>-===============
>+Backlight Refactoring
>+---------------------
> 
>-tinydrm
>--------
>+Backlight drivers have a triple enable/disable state, which is a bit overkill.
>+Plan to fix this:
> 
>-Tinydrm is the helper driver for really simple fb drivers. The goal is to make
>-those drivers as simple as possible, so lots of room for refactoring:
>+1. Roll out backlight_enable() and backlight_disable() helpers everywhere. This
>+   has started already.
>+2. In all, only look at one of the three status bits set by the above helpers.
>+3. Remove the other two status bits.
> 
>-- backlight helpers, probably best to put them into a new drm_backlight.c.
>-  This is because drivers/video is de-facto unmaintained. We could also
>-  move drivers/video/backlight to drivers/gpu/backlight and take it all
>-  over within drm-misc, but that's more work. Backlight helpers require a fair
>-  bit of reworking and refactoring. A simple example is the enabling of a backlight.
>-  Tinydrm has helpers for this. It would be good if other drivers can also use the
>-  helper. However, there are various cases we need to consider i.e different
>-  drivers seem to have different ways of enabling/disabling a backlight.
>-  We also need to consider the backlight drivers (like gpio_backlight). The situation
>-  is further complicated by the fact that the backlight is tied to fbdev
>-  via fb_notifier_callback() which has complicated logic. For further details, refer
>-  to the following discussion thread:
>-  https://groups.google.com/forum/#!topic/outreachy-kernel/8rBe30lwtdA
>-
>-- spi helpers, probably best put into spi core/helper code. Thierry said
>-  the spi maintainer is fast&reactive, so shouldn't be a big issue.
>-
>-- extract the mipi-dbi helper (well, the non-tinydrm specific parts at
>-  least) into a separate helper, like we have for mipi-dsi already. Or follow
>-  one of the ideas for having a shared dsi/dbi helper, abstracting away the
>-  transport details more.
>+Contact: Daniel Vetter
> 
>-Contact: Noralf TrÃ¸nnes, Daniel Vetter
>+Driver Specific
>+===============
> 
> AMD DC Display Driver
> ---------------------
>diff -Naur linux-5.3-rc6/Documentation/media/uapi/v4l/subdev-formats.rst linux-5.3-rc6-agd5fed/Documentation/media/uapi/v4l/subdev-formats.rst
>--- linux-5.3-rc6/Documentation/media/uapi/v4l/subdev-formats.rst	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/Documentation/media/uapi/v4l/subdev-formats.rst	2019-08-31 15:01:11.825736165 -0500
>@@ -1305,6 +1305,113 @@
>       - g\ :sub:`6`
>       - g\ :sub:`5`
>       - g\ :sub:`4`
>+    * .. _MEDIA-BUS-FMT-RGB888-3X8:
>+
>+      - MEDIA_BUS_FMT_RGB888_3X8
>+      - 0x101c
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      - r\ :sub:`7`
>+      - r\ :sub:`6`
>+      - r\ :sub:`5`
>+      - r\ :sub:`4`
>+      - r\ :sub:`3`
>+      - r\ :sub:`2`
>+      - r\ :sub:`1`
>+      - r\ :sub:`0`
>+    * -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      - g\ :sub:`7`
>+      - g\ :sub:`6`
>+      - g\ :sub:`5`
>+      - g\ :sub:`4`
>+      - g\ :sub:`3`
>+      - g\ :sub:`2`
>+      - g\ :sub:`1`
>+      - g\ :sub:`0`
>+    * -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      -
>+      - b\ :sub:`7`
>+      - b\ :sub:`6`
>+      - b\ :sub:`5`
>+      - b\ :sub:`4`
>+      - b\ :sub:`3`
>+      - b\ :sub:`2`
>+      - b\ :sub:`1`
>+      - b\ :sub:`0`
>     * .. _MEDIA-BUS-FMT-ARGB888-1X32:
> 
>       - MEDIA_BUS_FMT_ARGB888_1X32
>diff -Naur linux-5.3-rc6/drivers/dma-buf/dma-fence-chain.c linux-5.3-rc6-agd5fed/drivers/dma-buf/dma-fence-chain.c
>--- linux-5.3-rc6/drivers/dma-buf/dma-fence-chain.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/dma-buf/dma-fence-chain.c	2019-08-31 15:01:11.833736166 -0500
>@@ -178,8 +178,30 @@
> static void dma_fence_chain_release(struct dma_fence *fence)
> {
> 	struct dma_fence_chain *chain = to_dma_fence_chain(fence);
>+	struct dma_fence *prev;
>+
>+	/* Manually unlink the chain as much as possible to avoid recursion
>+	 * and potential stack overflow.
>+	 */
>+	while ((prev = rcu_dereference_protected(chain->prev, true))) {
>+		struct dma_fence_chain *prev_chain;
>+
>+		if (kref_read(&prev->refcount) > 1)
>+		       break;
>+
>+		prev_chain = to_dma_fence_chain(prev);
>+		if (!prev_chain)
>+			break;
>+
>+		/* No need for atomic operations since we hold the last
>+		 * reference to prev_chain.
>+		 */
>+		chain->prev = prev_chain->prev;
>+		RCU_INIT_POINTER(prev_chain->prev, NULL);
>+		dma_fence_put(prev);
>+	}
>+	dma_fence_put(prev);
> 
>-	dma_fence_put(rcu_dereference_protected(chain->prev, true));
> 	dma_fence_put(chain->fence);
> 	dma_fence_free(fence);
> }
>diff -Naur linux-5.3-rc6/drivers/dma-buf/reservation.c linux-5.3-rc6-agd5fed/drivers/dma-buf/reservation.c
>--- linux-5.3-rc6/drivers/dma-buf/reservation.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/dma-buf/reservation.c	2019-08-31 15:01:11.838736166 -0500
>@@ -56,6 +56,85 @@
> EXPORT_SYMBOL(reservation_seqcount_string);
> 
> /**
>+ * reservation_object_list_alloc - allocate fence list
>+ * @shared_max: number of fences we need space for
>+ *
>+ * Allocate a new reservation_object_list and make sure to correctly initialize
>+ * shared_max.
>+ */
>+static struct reservation_object_list *
>+reservation_object_list_alloc(unsigned int shared_max)
>+{
>+	struct reservation_object_list *list;
>+
>+	list = kmalloc(offsetof(typeof(*list), shared[shared_max]), GFP_KERNEL);
>+	if (!list)
>+		return NULL;
>+
>+	list->shared_max = (ksize(list) - offsetof(typeof(*list), shared)) /
>+		sizeof(*list->shared);
>+
>+	return list;
>+}
>+
>+/**
>+ * reservation_object_list_free - free fence list
>+ * @list: list to free
>+ *
>+ * Free a reservation_object_list and make sure to drop all references.
>+ */
>+static void reservation_object_list_free(struct reservation_object_list *list)
>+{
>+	unsigned int i;
>+
>+	if (!list)
>+		return;
>+
>+	for (i = 0; i < list->shared_count; ++i)
>+		dma_fence_put(rcu_dereference_protected(list->shared[i], true));
>+
>+	kfree_rcu(list, rcu);
>+}
>+
>+/**
>+ * reservation_object_init - initialize a reservation object
>+ * @obj: the reservation object
>+ */
>+void reservation_object_init(struct reservation_object *obj)
>+{
>+	ww_mutex_init(&obj->lock, &reservation_ww_class);
>+
>+	__seqcount_init(&obj->seq, reservation_seqcount_string,
>+			&reservation_seqcount_class);
>+	RCU_INIT_POINTER(obj->fence, NULL);
>+	RCU_INIT_POINTER(obj->fence_excl, NULL);
>+}
>+EXPORT_SYMBOL(reservation_object_init);
>+
>+/**
>+ * reservation_object_fini - destroys a reservation object
>+ * @obj: the reservation object
>+ */
>+void reservation_object_fini(struct reservation_object *obj)
>+{
>+	struct reservation_object_list *fobj;
>+	struct dma_fence *excl;
>+
>+	/*
>+	 * This object should be dead and all references must have
>+	 * been released to it, so no need to be protected with rcu.
>+	 */
>+	excl = rcu_dereference_protected(obj->fence_excl, 1);
>+	if (excl)
>+		dma_fence_put(excl);
>+
>+	fobj = rcu_dereference_protected(obj->fence, 1);
>+	reservation_object_list_free(fobj);
>+	ww_mutex_destroy(&obj->lock);
>+}
>+EXPORT_SYMBOL(reservation_object_fini);
>+
>+/**
>  * reservation_object_reserve_shared - Reserve space to add shared fences to
>  * a reservation_object.
>  * @obj: reservation object
>@@ -87,7 +166,7 @@
> 		max = 4;
> 	}
> 
>-	new = kmalloc(offsetof(typeof(*new), shared[max]), GFP_KERNEL);
>+	new = reservation_object_list_alloc(max);
> 	if (!new)
> 		return -ENOMEM;
> 
>@@ -108,23 +187,22 @@
> 			RCU_INIT_POINTER(new->shared[j++], fence);
> 	}
> 	new->shared_count = j;
>-	new->shared_max = max;
> 
>-	preempt_disable();
>-	write_seqcount_begin(&obj->seq);
> 	/*
>-	 * RCU_INIT_POINTER can be used here,
>-	 * seqcount provides the necessary barriers
>+	 * We are not changing the effective set of fences here so can
>+	 * merely update the pointer to the new array; both existing
>+	 * readers and new readers will see exactly the same set of
>+	 * active (unsignaled) shared fences. Individual fences and the
>+	 * old array are protected by RCU and so will not vanish under
>+	 * the gaze of the rcu_read_lock() readers.
> 	 */
>-	RCU_INIT_POINTER(obj->fence, new);
>-	write_seqcount_end(&obj->seq);
>-	preempt_enable();
>+	rcu_assign_pointer(obj->fence, new);
> 
> 	if (!old)
> 		return 0;
> 
> 	/* Drop the references to the signaled fences */
>-	for (i = k; i < new->shared_max; ++i) {
>+	for (i = k; i < max; ++i) {
> 		struct dma_fence *fence;
> 
> 		fence = rcu_dereference_protected(new->shared[i],
>@@ -149,6 +227,7 @@
> 					 struct dma_fence *fence)
> {
> 	struct reservation_object_list *fobj;
>+	struct dma_fence *old;
> 	unsigned int i, count;
> 
> 	dma_fence_get(fence);
>@@ -162,18 +241,16 @@
> 	write_seqcount_begin(&obj->seq);
> 
> 	for (i = 0; i < count; ++i) {
>-		struct dma_fence *old_fence;
> 
>-		old_fence = rcu_dereference_protected(fobj->shared[i],
>-						      reservation_object_held(obj));
>-		if (old_fence->context == fence->context ||
>-		    dma_fence_is_signaled(old_fence)) {
>-			dma_fence_put(old_fence);
>+		old = rcu_dereference_protected(fobj->shared[i],
>+						reservation_object_held(obj));
>+		if (old->context == fence->context ||
>+		    dma_fence_is_signaled(old))
> 			goto replace;
>-		}
> 	}
> 
> 	BUG_ON(fobj->shared_count >= fobj->shared_max);
>+	old = NULL;
> 	count++;
> 
> replace:
>@@ -183,6 +260,7 @@
> 
> 	write_seqcount_end(&obj->seq);
> 	preempt_enable();
>+	dma_fence_put(old);
> }
> EXPORT_SYMBOL(reservation_object_add_shared_fence);
> 
>@@ -239,7 +317,6 @@
> {
> 	struct reservation_object_list *src_list, *dst_list;
> 	struct dma_fence *old, *new;
>-	size_t size;
> 	unsigned i;
> 
> 	reservation_object_assert_held(dst);
>@@ -251,10 +328,9 @@
> 	if (src_list) {
> 		unsigned shared_count = src_list->shared_count;
> 
>-		size = offsetof(typeof(*src_list), shared[shared_count]);
> 		rcu_read_unlock();
> 
>-		dst_list = kmalloc(size, GFP_KERNEL);
>+		dst_list = reservation_object_list_alloc(shared_count);
> 		if (!dst_list)
> 			return -ENOMEM;
> 
>@@ -266,7 +342,6 @@
> 		}
> 
> 		dst_list->shared_count = 0;
>-		dst_list->shared_max = shared_count;
> 		for (i = 0; i < src_list->shared_count; ++i) {
> 			struct dma_fence *fence;
> 
>@@ -276,7 +351,7 @@
> 				continue;
> 
> 			if (!dma_fence_get_rcu(fence)) {
>-				kfree(dst_list);
>+				reservation_object_list_free(dst_list);
> 				src_list = rcu_dereference(src->fence);
> 				goto retry;
> 			}
>@@ -306,8 +381,7 @@
> 	write_seqcount_end(&dst->seq);
> 	preempt_enable();
> 
>-	if (src_list)
>-		kfree_rcu(src_list, rcu);
>+	reservation_object_list_free(src_list);
> 	dma_fence_put(old);
> 
> 	return 0;
>@@ -385,13 +459,6 @@
> 				if (!dma_fence_get_rcu(shared[i]))
> 					break;
> 			}
>-
>-			if (!pfence_excl && fence_excl) {
>-				shared[i] = fence_excl;
>-				fence_excl = NULL;
>-				++i;
>-				++shared_count;
>-			}
> 		}
> 
> 		if (i != shared_count || read_seqcount_retry(&obj->seq, seq)) {
>@@ -406,6 +473,11 @@
> 		rcu_read_unlock();
> 	} while (ret);
> 
>+	if (pfence_excl)
>+		*pfence_excl = fence_excl;
>+	else if (fence_excl)
>+		shared[++shared_count] = fence_excl;
>+
> 	if (!shared_count) {
> 		kfree(shared);
> 		shared = NULL;
>@@ -413,9 +485,6 @@
> 
> 	*pshared_count = shared_count;
> 	*pshared = shared;
>-	if (pfence_excl)
>-		*pfence_excl = fence_excl;
>-
> 	return ret;
> }
> EXPORT_SYMBOL_GPL(reservation_object_get_fences_rcu);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c	2019-08-31 15:01:11.839736167 -0500
>@@ -0,0 +1,323 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+
>+#undef pr_fmt
>+#define pr_fmt(fmt) "kfd2kgd: " fmt
>+
>+#include <linux/module.h>
>+#include <linux/fdtable.h>
>+#include <linux/uaccess.h>
>+#include <linux/mmu_context.h>
>+#include <linux/firmware.h>
>+#include "amdgpu.h"
>+#include "amdgpu_amdkfd.h"
>+#include "sdma0/sdma0_4_2_2_offset.h"
>+#include "sdma0/sdma0_4_2_2_sh_mask.h"
>+#include "sdma1/sdma1_4_2_2_offset.h"
>+#include "sdma1/sdma1_4_2_2_sh_mask.h"
>+#include "sdma2/sdma2_4_2_2_offset.h"
>+#include "sdma2/sdma2_4_2_2_sh_mask.h"
>+#include "sdma3/sdma3_4_2_2_offset.h"
>+#include "sdma3/sdma3_4_2_2_sh_mask.h"
>+#include "sdma4/sdma4_4_2_2_offset.h"
>+#include "sdma4/sdma4_4_2_2_sh_mask.h"
>+#include "sdma5/sdma5_4_2_2_offset.h"
>+#include "sdma5/sdma5_4_2_2_sh_mask.h"
>+#include "sdma6/sdma6_4_2_2_offset.h"
>+#include "sdma6/sdma6_4_2_2_sh_mask.h"
>+#include "sdma7/sdma7_4_2_2_offset.h"
>+#include "sdma7/sdma7_4_2_2_sh_mask.h"
>+#include "v9_structs.h"
>+#include "soc15.h"
>+#include "soc15d.h"
>+#include "amdgpu_amdkfd_gfx_v9.h"
>+
>+#define HQD_N_REGS 56
>+#define DUMP_REG(addr) do {				\
>+		if (WARN_ON_ONCE(i >= HQD_N_REGS))	\
>+			break;				\
>+		(*dump)[i][0] = (addr) << 2;		\
>+		(*dump)[i++][1] = RREG32(addr);		\
>+	} while (0)
>+
>+static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
>+{
>+	return (struct amdgpu_device *)kgd;
>+}
>+
>+static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd)
>+{
>+	return (struct v9_sdma_mqd *)mqd;
>+}
>+
>+static uint32_t get_sdma_base_addr(struct amdgpu_device *adev,
>+				unsigned int engine_id,
>+				unsigned int queue_id)
>+{
>+	uint32_t base[8] = {
>+		SOC15_REG_OFFSET(SDMA0, 0,
>+				 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
>+		SOC15_REG_OFFSET(SDMA1, 0,
>+				 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL,
>+		SOC15_REG_OFFSET(SDMA2, 0,
>+				 mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL,
>+		SOC15_REG_OFFSET(SDMA3, 0,
>+				 mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL,
>+		SOC15_REG_OFFSET(SDMA4, 0,
>+				 mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL,
>+		SOC15_REG_OFFSET(SDMA5, 0,
>+				 mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL,
>+		SOC15_REG_OFFSET(SDMA6, 0,
>+				 mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL,
>+		SOC15_REG_OFFSET(SDMA7, 0,
>+				 mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL
>+	};
>+	uint32_t retval;
>+
>+	retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL -
>+					       mmSDMA0_RLC0_RB_CNTL);
>+
>+	pr_debug("sdma base address: 0x%x\n", retval);
>+
>+	return retval;
>+}
>+
>+static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
>+		u32 instance, u32 offset)
>+{
>+	switch (instance) {
>+	case 0:
>+		return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
>+	case 1:
>+		return (adev->reg_offset[SDMA1_HWIP][0][1] + offset);
>+	case 2:
>+		return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
>+	case 3:
>+		return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
>+	case 4:
>+		return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
>+	case 5:
>+		return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
>+	case 6:
>+		return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
>+	case 7:
>+		return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
>+	default:
>+		break;
>+	}
>+	return 0;
>+}
>+
>+static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
>+			     uint32_t __user *wptr, struct mm_struct *mm)
>+{
>+	struct amdgpu_device *adev = get_amdgpu_device(kgd);
>+	struct v9_sdma_mqd *m;
>+	uint32_t sdma_base_addr, sdmax_gfx_context_cntl;
>+	unsigned long end_jiffies;
>+	uint32_t data;
>+	uint64_t data64;
>+	uint64_t __user *wptr64 = (uint64_t __user *)wptr;
>+
>+	m = get_sdma_mqd(mqd);
>+	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
>+					    m->sdma_queue_id);
>+	sdmax_gfx_context_cntl = sdma_v4_0_get_reg_offset(adev,
>+			m->sdma_engine_id, mmSDMA0_GFX_CONTEXT_CNTL);
>+
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
>+		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
>+
>+	end_jiffies = msecs_to_jiffies(2000) + jiffies;
>+	while (true) {
>+		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
>+		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
>+			break;
>+		if (time_after(jiffies, end_jiffies))
>+			return -ETIME;
>+		usleep_range(500, 1000);
>+	}
>+	data = RREG32(sdmax_gfx_context_cntl);
>+	data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
>+			     RESUME_CTX, 0);
>+	WREG32(sdmax_gfx_context_cntl, data);
>+
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,
>+	       m->sdmax_rlcx_doorbell_offset);
>+
>+	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
>+			     ENABLE, 1);
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,
>+				m->sdmax_rlcx_rb_rptr_hi);
>+
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
>+	if (read_user_wptr(mm, wptr64, data64)) {
>+		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
>+		       lower_32_bits(data64));
>+		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
>+		       upper_32_bits(data64));
>+	} else {
>+		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
>+		       m->sdmax_rlcx_rb_rptr);
>+		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,
>+		       m->sdmax_rlcx_rb_rptr_hi);
>+	}
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
>+
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
>+			m->sdmax_rlcx_rb_base_hi);
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
>+			m->sdmax_rlcx_rb_rptr_addr_lo);
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
>+			m->sdmax_rlcx_rb_rptr_addr_hi);
>+
>+	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
>+			     RB_ENABLE, 1);
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
>+
>+	return 0;
>+}
>+
>+static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
>+			     uint32_t engine_id, uint32_t queue_id,
>+			     uint32_t (**dump)[2], uint32_t *n_regs)
>+{
>+	struct amdgpu_device *adev = get_amdgpu_device(kgd);
>+	uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id);
>+	uint32_t i = 0, reg;
>+#undef HQD_N_REGS
>+#define HQD_N_REGS (19+6+7+10)
>+
>+	*dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL);
>+	if (*dump == NULL)
>+		return -ENOMEM;
>+
>+	for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
>+		DUMP_REG(sdma_base_addr + reg);
>+	for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
>+		DUMP_REG(sdma_base_addr + reg);
>+	for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
>+	     reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
>+		DUMP_REG(sdma_base_addr + reg);
>+	for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
>+	     reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
>+		DUMP_REG(sdma_base_addr + reg);
>+
>+	WARN_ON_ONCE(i != HQD_N_REGS);
>+	*n_regs = i;
>+
>+	return 0;
>+}
>+
>+static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
>+{
>+	struct amdgpu_device *adev = get_amdgpu_device(kgd);
>+	struct v9_sdma_mqd *m;
>+	uint32_t sdma_base_addr;
>+	uint32_t sdma_rlc_rb_cntl;
>+
>+	m = get_sdma_mqd(mqd);
>+	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
>+					    m->sdma_queue_id);
>+
>+	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
>+
>+	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
>+		return true;
>+
>+	return false;
>+}
>+
>+static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
>+				unsigned int utimeout)
>+{
>+	struct amdgpu_device *adev = get_amdgpu_device(kgd);
>+	struct v9_sdma_mqd *m;
>+	uint32_t sdma_base_addr;
>+	uint32_t temp;
>+	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
>+
>+	m = get_sdma_mqd(mqd);
>+	sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id,
>+					    m->sdma_queue_id);
>+
>+	temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
>+	temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
>+
>+	while (true) {
>+		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
>+		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
>+			break;
>+		if (time_after(jiffies, end_jiffies))
>+			return -ETIME;
>+		usleep_range(500, 1000);
>+	}
>+
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
>+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
>+		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
>+		SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
>+
>+	m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
>+	m->sdmax_rlcx_rb_rptr_hi =
>+		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
>+
>+	return 0;
>+}
>+
>+static const struct kfd2kgd_calls kfd2kgd = {
>+	.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
>+	.set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
>+	.init_interrupts = kgd_gfx_v9_init_interrupts,
>+	.hqd_load = kgd_gfx_v9_hqd_load,
>+	.hqd_sdma_load = kgd_hqd_sdma_load,
>+	.hqd_dump = kgd_gfx_v9_hqd_dump,
>+	.hqd_sdma_dump = kgd_hqd_sdma_dump,
>+	.hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied,
>+	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
>+	.hqd_destroy = kgd_gfx_v9_hqd_destroy,
>+	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
>+	.address_watch_disable = kgd_gfx_v9_address_watch_disable,
>+	.address_watch_execute = kgd_gfx_v9_address_watch_execute,
>+	.wave_control_execute = kgd_gfx_v9_wave_control_execute,
>+	.address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
>+	.get_atc_vmid_pasid_mapping_pasid =
>+			kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid,
>+	.get_atc_vmid_pasid_mapping_valid =
>+			kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid,
>+	.set_scratch_backing_va = kgd_gfx_v9_set_scratch_backing_va,
>+	.get_tile_config = kgd_gfx_v9_get_tile_config,
>+	.set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
>+	.invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
>+	.invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid,
>+	.get_hive_id = amdgpu_amdkfd_get_hive_id,
>+};
>+
>+struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void)
>+{
>+	return (struct kfd2kgd_calls *)&kfd2kgd;
>+}
>+
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c	2019-08-31 15:01:11.839736167 -0500
>@@ -87,7 +87,12 @@
> 	case CHIP_RAVEN:
> 		kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
> 		break;
>+	case CHIP_ARCTURUS:
>+		kfd2kgd = amdgpu_amdkfd_arcturus_get_functions();
>+		break;
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions();
> 		break;
> 	default:
>@@ -651,8 +656,12 @@
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
> 
>-	if (adev->powerplay.pp_funcs &&
>-	    adev->powerplay.pp_funcs->switch_power_profile)
>+	if (is_support_sw_smu(adev))
>+		smu_switch_power_profile(&adev->smu,
>+					 PP_SMC_POWER_PROFILE_COMPUTE,
>+					 !idle);
>+	else if (adev->powerplay.pp_funcs &&
>+		 adev->powerplay.pp_funcs->switch_power_profile)
> 		amdgpu_dpm_switch_power_profile(adev,
> 						PP_SMC_POWER_PROFILE_COMPUTE,
> 						!idle);
>@@ -714,6 +723,11 @@
> {
> 	return NULL;
> }
>+
>+struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void)
>+{
>+	return NULL;
>+}
> 
> struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void)
> {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c	2019-08-31 15:01:11.839736167 -0500
>@@ -27,7 +27,6 @@
> #include <linux/uaccess.h>
> #include <linux/firmware.h>
> #include <linux/mmu_context.h>
>-#include <drm/drmP.h>
> #include "amdgpu.h"
> #include "amdgpu_amdkfd.h"
> #include "amdgpu_ucode.h"
>@@ -802,42 +801,6 @@
> 	return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
> }
> 
>-static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
>-{
>-	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
>-	uint32_t req = (1 << vmid) |
>-		(0 << GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT) |/* legacy */
>-		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK |
>-		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK |
>-		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK |
>-		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK |
>-		GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK;
>-
>-	mutex_lock(&adev->srbm_mutex);
>-
>-	/* Use light weight invalidation.
>-	 *
>-	 * TODO 1: agree on the right set of invalidation registers for
>-	 * KFD use. Use the last one for now. Invalidate only GCHUB as
>-	 * SDMA is now moved to GCHUB
>-	 *
>-	 * TODO 2: support range-based invalidation, requires kfg2kgd
>-	 * interface change
>-	 */
>-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32),
>-				0xffffffff);
>-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32),
>-				0x0000001f);
>-
>-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ), req);
>-
>-	while (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK)) &
>-					(1 << vmid)))
>-		cpu_relax();
>-
>-	mutex_unlock(&adev->srbm_mutex);
>-}
>-
> static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid)
> {
> 	signed long r;
>@@ -878,7 +841,8 @@
> 		if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
> 			if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
> 				== pasid) {
>-				write_vmid_invalidate_request(kgd, vmid);
>+				amdgpu_gmc_flush_gpu_tlb(adev, vmid,
>+						AMDGPU_GFXHUB_0, 0);
> 				break;
> 			}
> 		}
>@@ -896,7 +860,7 @@
> 		return 0;
> 	}
> 
>-	write_vmid_invalidate_request(kgd, vmid);
>+	amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
> 	return 0;
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c	2019-08-31 15:01:11.839736167 -0500
>@@ -47,6 +47,7 @@
> #include "soc15d.h"
> #include "mmhub_v1_0.h"
> #include "gfxhub_v1_0.h"
>+#include "gmc_v9_0.h"
> 
> 
> #define V9_PIPE_PER_MEC		(4)
>@@ -58,66 +59,11 @@
> 	RESET_WAVES
> };
> 
>-/*
>- * Register access functions
>- */
>-
>-static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
>-		uint32_t sh_mem_config,
>-		uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
>-		uint32_t sh_mem_bases);
>-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
>-		unsigned int vmid);
>-static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
>-static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>-			uint32_t queue_id, uint32_t __user *wptr,
>-			uint32_t wptr_shift, uint32_t wptr_mask,
>-			struct mm_struct *mm);
>-static int kgd_hqd_dump(struct kgd_dev *kgd,
>-			uint32_t pipe_id, uint32_t queue_id,
>-			uint32_t (**dump)[2], uint32_t *n_regs);
>-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
>-			     uint32_t __user *wptr, struct mm_struct *mm);
>-static int kgd_hqd_sdma_dump(struct kgd_dev *kgd,
>-			     uint32_t engine_id, uint32_t queue_id,
>-			     uint32_t (**dump)[2], uint32_t *n_regs);
>-static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
>-		uint32_t pipe_id, uint32_t queue_id);
>-static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
>-static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
>-				enum kfd_preempt_type reset_type,
>-				unsigned int utimeout, uint32_t pipe_id,
>-				uint32_t queue_id);
>-static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
>-				unsigned int utimeout);
>-static int kgd_address_watch_disable(struct kgd_dev *kgd);
>-static int kgd_address_watch_execute(struct kgd_dev *kgd,
>-					unsigned int watch_point_id,
>-					uint32_t cntl_val,
>-					uint32_t addr_hi,
>-					uint32_t addr_lo);
>-static int kgd_wave_control_execute(struct kgd_dev *kgd,
>-					uint32_t gfx_index_val,
>-					uint32_t sq_cmd);
>-static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
>-					unsigned int watch_point_id,
>-					unsigned int reg_offset);
>-
>-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
>-		uint8_t vmid);
>-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
>-		uint8_t vmid);
>-static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
>-		uint64_t page_table_base);
>-static void set_scratch_backing_va(struct kgd_dev *kgd,
>-					uint64_t va, uint32_t vmid);
>-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
>-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
> 
> /* Because of REG_GET_FIELD() being used, we put this function in the
>  * asic specific file.
>  */
>-static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
>+int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
> 		struct tile_config *config)
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
>@@ -135,39 +81,6 @@
> 	return 0;
> }
> 
>-static const struct kfd2kgd_calls kfd2kgd = {
>-	.program_sh_mem_settings = kgd_program_sh_mem_settings,
>-	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
>-	.init_interrupts = kgd_init_interrupts,
>-	.hqd_load = kgd_hqd_load,
>-	.hqd_sdma_load = kgd_hqd_sdma_load,
>-	.hqd_dump = kgd_hqd_dump,
>-	.hqd_sdma_dump = kgd_hqd_sdma_dump,
>-	.hqd_is_occupied = kgd_hqd_is_occupied,
>-	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
>-	.hqd_destroy = kgd_hqd_destroy,
>-	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
>-	.address_watch_disable = kgd_address_watch_disable,
>-	.address_watch_execute = kgd_address_watch_execute,
>-	.wave_control_execute = kgd_wave_control_execute,
>-	.address_watch_get_offset = kgd_address_watch_get_offset,
>-	.get_atc_vmid_pasid_mapping_pasid =
>-			get_atc_vmid_pasid_mapping_pasid,
>-	.get_atc_vmid_pasid_mapping_valid =
>-			get_atc_vmid_pasid_mapping_valid,
>-	.set_scratch_backing_va = set_scratch_backing_va,
>-	.get_tile_config = amdgpu_amdkfd_get_tile_config,
>-	.set_vm_context_page_table_base = set_vm_context_page_table_base,
>-	.invalidate_tlbs = invalidate_tlbs,
>-	.invalidate_tlbs_vmid = invalidate_tlbs_vmid,
>-	.get_hive_id = amdgpu_amdkfd_get_hive_id,
>-};
>-
>-struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
>-{
>-	return (struct kfd2kgd_calls *)&kfd2kgd;
>-}
>-
> static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
> {
> 	return (struct amdgpu_device *)kgd;
>@@ -215,7 +128,7 @@
> 	unlock_srbm(kgd);
> }
> 
>-static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
>+void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
> 					uint32_t sh_mem_config,
> 					uint32_t sh_mem_ape1_base,
> 					uint32_t sh_mem_ape1_limit,
>@@ -232,7 +145,7 @@
> 	unlock_srbm(kgd);
> }
> 
>-static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
>+int kgd_gfx_v9_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
> 					unsigned int vmid)
> {
> 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
>@@ -293,7 +206,7 @@
>  * but still works
>  */
> 
>-static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
>+int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
> {
> 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
> 	uint32_t mec;
>@@ -343,7 +256,7 @@
> 	return (struct v9_sdma_mqd *)mqd;
> }
> 
>-static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>+int kgd_gfx_v9_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
> 			uint32_t queue_id, uint32_t __user *wptr,
> 			uint32_t wptr_shift, uint32_t wptr_mask,
> 			struct mm_struct *mm)
>@@ -438,7 +351,7 @@
> 	return 0;
> }
> 
>-static int kgd_hqd_dump(struct kgd_dev *kgd,
>+int kgd_gfx_v9_hqd_dump(struct kgd_dev *kgd,
> 			uint32_t pipe_id, uint32_t queue_id,
> 			uint32_t (**dump)[2], uint32_t *n_regs)
> {
>@@ -575,7 +488,7 @@
> 	return 0;
> }
> 
>-static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
>+bool kgd_gfx_v9_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
> 				uint32_t pipe_id, uint32_t queue_id)
> {
> 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
>@@ -616,7 +529,7 @@
> 	return false;
> }
> 
>-static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
>+int kgd_gfx_v9_hqd_destroy(struct kgd_dev *kgd, void *mqd,
> 				enum kfd_preempt_type reset_type,
> 				unsigned int utimeout, uint32_t pipe_id,
> 				uint32_t queue_id)
>@@ -704,7 +617,7 @@
> 	return 0;
> }
> 
>-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
>+bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
> 							uint8_t vmid)
> {
> 	uint32_t reg;
>@@ -715,7 +628,7 @@
> 	return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
> }
> 
>-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
>+uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
> 								uint8_t vmid)
> {
> 	uint32_t reg;
>@@ -754,10 +667,10 @@
> 	return 0;
> }
> 
>-static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
>+int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
>-	int vmid;
>+	int vmid, i;
> 	struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
> 	uint32_t flush_type = 0;
> 
>@@ -773,11 +686,12 @@
> 	for (vmid = 0; vmid < 16; vmid++) {
> 		if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
> 			continue;
>-		if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
>-			if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
>+		if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
>+			if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
> 				== pasid) {
>-				amdgpu_gmc_flush_gpu_tlb(adev, vmid,
>-							 flush_type);
>+				for (i = 0; i < adev->num_vmhubs; i++)
>+					amdgpu_gmc_flush_gpu_tlb(adev, vmid,
>+								i, flush_type);
> 				break;
> 			}
> 		}
>@@ -786,9 +700,10 @@
> 	return 0;
> }
> 
>-static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
>+int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
>+	int i;
> 
> 	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
> 		pr_err("non kfd vmid %d\n", vmid);
>@@ -810,16 +725,18 @@
> 	 * TODO 2: support range-based invalidation, requires kfg2kgd
> 	 * interface change
> 	 */
>-	amdgpu_gmc_flush_gpu_tlb(adev, vmid, 0);
>+	for (i = 0; i < adev->num_vmhubs; i++)
>+		amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
>+
> 	return 0;
> }
> 
>-static int kgd_address_watch_disable(struct kgd_dev *kgd)
>+int kgd_gfx_v9_address_watch_disable(struct kgd_dev *kgd)
> {
> 	return 0;
> }
> 
>-static int kgd_address_watch_execute(struct kgd_dev *kgd,
>+int kgd_gfx_v9_address_watch_execute(struct kgd_dev *kgd,
> 					unsigned int watch_point_id,
> 					uint32_t cntl_val,
> 					uint32_t addr_hi,
>@@ -828,7 +745,7 @@
> 	return 0;
> }
> 
>-static int kgd_wave_control_execute(struct kgd_dev *kgd,
>+int kgd_gfx_v9_wave_control_execute(struct kgd_dev *kgd,
> 					uint32_t gfx_index_val,
> 					uint32_t sq_cmd)
> {
>@@ -853,14 +770,14 @@
> 	return 0;
> }
> 
>-static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
>+uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd,
> 					unsigned int watch_point_id,
> 					unsigned int reg_offset)
> {
> 	return 0;
> }
> 
>-static void set_scratch_backing_va(struct kgd_dev *kgd,
>+void kgd_gfx_v9_set_scratch_backing_va(struct kgd_dev *kgd,
> 					uint64_t va, uint32_t vmid)
> {
> 	/* No longer needed on GFXv9. The scratch base address is
>@@ -869,7 +786,7 @@
> 	 */
> }
> 
>-static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
>+void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
> 		uint64_t page_table_base)
> {
> 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
>@@ -884,7 +801,45 @@
> 	 * now, all processes share the same address space size, like
> 	 * on GFX8 and older.
> 	 */
>-	mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
>+	if (adev->asic_type == CHIP_ARCTURUS) {
>+		/* Two MMHUBs */
>+		mmhub_v9_4_setup_vm_pt_regs(adev, 0, vmid, page_table_base);
>+		mmhub_v9_4_setup_vm_pt_regs(adev, 1, vmid, page_table_base);
>+	} else
>+		mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
> 
> 	gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);
> }
>+
>+static const struct kfd2kgd_calls kfd2kgd = {
>+	.program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
>+	.set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
>+	.init_interrupts = kgd_gfx_v9_init_interrupts,
>+	.hqd_load = kgd_gfx_v9_hqd_load,
>+	.hqd_sdma_load = kgd_hqd_sdma_load,
>+	.hqd_dump = kgd_gfx_v9_hqd_dump,
>+	.hqd_sdma_dump = kgd_hqd_sdma_dump,
>+	.hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied,
>+	.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
>+	.hqd_destroy = kgd_gfx_v9_hqd_destroy,
>+	.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
>+	.address_watch_disable = kgd_gfx_v9_address_watch_disable,
>+	.address_watch_execute = kgd_gfx_v9_address_watch_execute,
>+	.wave_control_execute = kgd_gfx_v9_wave_control_execute,
>+	.address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
>+	.get_atc_vmid_pasid_mapping_pasid =
>+			kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid,
>+	.get_atc_vmid_pasid_mapping_valid =
>+			kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid,
>+	.set_scratch_backing_va = kgd_gfx_v9_set_scratch_backing_va,
>+	.get_tile_config = kgd_gfx_v9_get_tile_config,
>+	.set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
>+	.invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
>+	.invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid,
>+	.get_hive_id = amdgpu_amdkfd_get_hive_id,
>+};
>+
>+struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
>+{
>+	return (struct kfd2kgd_calls *)&kfd2kgd;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h	2019-08-31 15:01:11.839736167 -0500
>@@ -0,0 +1,69 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+
>+
>+
>+void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
>+		uint32_t sh_mem_config,
>+		uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
>+		uint32_t sh_mem_bases);
>+int kgd_gfx_v9_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
>+		unsigned int vmid);
>+int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
>+int kgd_gfx_v9_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>+			uint32_t queue_id, uint32_t __user *wptr,
>+			uint32_t wptr_shift, uint32_t wptr_mask,
>+			struct mm_struct *mm);
>+int kgd_gfx_v9_hqd_dump(struct kgd_dev *kgd,
>+			uint32_t pipe_id, uint32_t queue_id,
>+			uint32_t (**dump)[2], uint32_t *n_regs);
>+bool kgd_gfx_v9_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
>+		uint32_t pipe_id, uint32_t queue_id);
>+int kgd_gfx_v9_hqd_destroy(struct kgd_dev *kgd, void *mqd,
>+				enum kfd_preempt_type reset_type,
>+				unsigned int utimeout, uint32_t pipe_id,
>+				uint32_t queue_id);
>+int kgd_gfx_v9_address_watch_disable(struct kgd_dev *kgd);
>+int kgd_gfx_v9_address_watch_execute(struct kgd_dev *kgd,
>+					unsigned int watch_point_id,
>+					uint32_t cntl_val,
>+					uint32_t addr_hi,
>+					uint32_t addr_lo);
>+int kgd_gfx_v9_wave_control_execute(struct kgd_dev *kgd,
>+					uint32_t gfx_index_val,
>+					uint32_t sq_cmd);
>+uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd,
>+					unsigned int watch_point_id,
>+					unsigned int reg_offset);
>+
>+bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
>+		uint8_t vmid);
>+uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
>+		uint8_t vmid);
>+void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
>+		uint64_t page_table_base);
>+void kgd_gfx_v9_set_scratch_backing_va(struct kgd_dev *kgd,
>+					uint64_t va, uint32_t vmid);
>+int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
>+int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid);
>+int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
>+		struct tile_config *config);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c	2019-08-31 15:01:11.840736167 -0500
>@@ -218,7 +218,7 @@
> static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
> 					struct amdgpu_amdkfd_fence *ef)
> {
>-	struct reservation_object *resv = bo->tbo.resv;
>+	struct reservation_object *resv = bo->tbo.base.resv;
> 	struct reservation_object_list *old, *new;
> 	unsigned int i, j, k;
> 
>@@ -812,7 +812,7 @@
> 		struct amdgpu_bo *pd = peer_vm->root.base.bo;
> 
> 		ret = amdgpu_sync_resv(NULL,
>-					sync, pd->tbo.resv,
>+					sync, pd->tbo.base.resv,
> 					AMDGPU_FENCE_OWNER_KFD, false);
> 		if (ret)
> 			return ret;
>@@ -887,7 +887,7 @@
> 				  AMDGPU_FENCE_OWNER_KFD, false);
> 	if (ret)
> 		goto wait_pd_fail;
>-	ret = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv, 1);
>+	ret = reservation_object_reserve_shared(vm->root.base.bo->tbo.base.resv, 1);
> 	if (ret)
> 		goto reserve_shared_fail;
> 	amdgpu_bo_fence(vm->root.base.bo,
>@@ -1090,7 +1090,7 @@
> 	 */
> 	if (flags & ALLOC_MEM_FLAGS_VRAM) {
> 		domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
>-		alloc_flags = AMDGPU_GEM_CREATE_VRAM_CLEARED;
>+		alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
> 		alloc_flags |= (flags & ALLOC_MEM_FLAGS_PUBLIC) ?
> 			AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED :
> 			AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
>@@ -2133,7 +2133,7 @@
> 	 * Add process eviction fence to bo so they can
> 	 * evict each other.
> 	 */
>-	ret = reservation_object_reserve_shared(gws_bo->tbo.resv, 1);
>+	ret = reservation_object_reserve_shared(gws_bo->tbo.base.resv, 1);
> 	if (ret)
> 		goto reserve_shared_fail;
> 	amdgpu_bo_fence(gws_bo, &process_info->eviction_fence->base, true);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h	2019-08-31 15:01:11.839736167 -0500
>@@ -140,6 +140,7 @@
> struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void);
> struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void);
> struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void);
>+struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void);
> struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void);
> 
> bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c	2019-08-31 15:01:11.840736167 -0500
>@@ -574,6 +574,7 @@
> 	{ 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
> 	{ 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
> 	{ 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
>+	{ 0x1002, 0x699f, 0x1028, 0x0814, AMDGPU_PX_QUIRK_FORCE_ATPX },
> 	{ 0x1002, 0x6900, 0x1025, 0x125A, AMDGPU_PX_QUIRK_FORCE_ATPX },
> 	{ 0x1002, 0x6900, 0x17AA, 0x3806, AMDGPU_PX_QUIRK_FORCE_ATPX },
> 	{ 0, 0, 0, 0, 0 },
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c	2019-08-31 15:01:11.840736167 -0500
>@@ -1505,6 +1505,7 @@
> 	struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
> 	struct drm_encoder *encoder;
> 	struct amdgpu_encoder *amdgpu_encoder;
>+	struct i2c_adapter *ddc = NULL;
> 	uint32_t subpixel_order = SubPixelNone;
> 	bool shared_ddc = false;
> 	bool is_dp_bridge = false;
>@@ -1574,17 +1575,21 @@
> 		amdgpu_connector->con_priv = amdgpu_dig_connector;
> 		if (i2c_bus->valid) {
> 			amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
>-			if (amdgpu_connector->ddc_bus)
>+			if (amdgpu_connector->ddc_bus) {
> 				has_aux = true;
>-			else
>+				ddc = &amdgpu_connector->ddc_bus->adapter;
>+			} else {
> 				DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
>+			}
> 		}
> 		switch (connector_type) {
> 		case DRM_MODE_CONNECTOR_VGA:
> 		case DRM_MODE_CONNECTOR_DVIA:
> 		default:
>-			drm_connector_init(dev, &amdgpu_connector->base,
>-					   &amdgpu_connector_dp_funcs, connector_type);
>+			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
>+						    &amdgpu_connector_dp_funcs,
>+						    connector_type,
>+						    ddc);
> 			drm_connector_helper_add(&amdgpu_connector->base,
> 						 &amdgpu_connector_dp_helper_funcs);
> 			connector->interlace_allowed = true;
>@@ -1602,8 +1607,10 @@
> 		case DRM_MODE_CONNECTOR_HDMIA:
> 		case DRM_MODE_CONNECTOR_HDMIB:
> 		case DRM_MODE_CONNECTOR_DisplayPort:
>-			drm_connector_init(dev, &amdgpu_connector->base,
>-					   &amdgpu_connector_dp_funcs, connector_type);
>+			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
>+						    &amdgpu_connector_dp_funcs,
>+						    connector_type,
>+						    ddc);
> 			drm_connector_helper_add(&amdgpu_connector->base,
> 						 &amdgpu_connector_dp_helper_funcs);
> 			drm_object_attach_property(&amdgpu_connector->base.base,
>@@ -1644,8 +1651,10 @@
> 			break;
> 		case DRM_MODE_CONNECTOR_LVDS:
> 		case DRM_MODE_CONNECTOR_eDP:
>-			drm_connector_init(dev, &amdgpu_connector->base,
>-					   &amdgpu_connector_edp_funcs, connector_type);
>+			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
>+						    &amdgpu_connector_edp_funcs,
>+						    connector_type,
>+						    ddc);
> 			drm_connector_helper_add(&amdgpu_connector->base,
> 						 &amdgpu_connector_dp_helper_funcs);
> 			drm_object_attach_property(&amdgpu_connector->base.base,
>@@ -1659,13 +1668,18 @@
> 	} else {
> 		switch (connector_type) {
> 		case DRM_MODE_CONNECTOR_VGA:
>-			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
>-			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
> 			if (i2c_bus->valid) {
> 				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
> 				if (!amdgpu_connector->ddc_bus)
> 					DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
>+				else
>+					ddc = &amdgpu_connector->ddc_bus->adapter;
> 			}
>+			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
>+						    &amdgpu_connector_vga_funcs,
>+						    connector_type,
>+						    ddc);
>+			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
> 			amdgpu_connector->dac_load_detect = true;
> 			drm_object_attach_property(&amdgpu_connector->base.base,
> 						      adev->mode_info.load_detect_property,
>@@ -1679,13 +1693,18 @@
> 			connector->doublescan_allowed = true;
> 			break;
> 		case DRM_MODE_CONNECTOR_DVIA:
>-			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
>-			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
> 			if (i2c_bus->valid) {
> 				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
> 				if (!amdgpu_connector->ddc_bus)
> 					DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
>+				else
>+					ddc = &amdgpu_connector->ddc_bus->adapter;
> 			}
>+			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
>+						    &amdgpu_connector_vga_funcs,
>+						    connector_type,
>+						    ddc);
>+			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
> 			amdgpu_connector->dac_load_detect = true;
> 			drm_object_attach_property(&amdgpu_connector->base.base,
> 						      adev->mode_info.load_detect_property,
>@@ -1704,13 +1723,18 @@
> 			if (!amdgpu_dig_connector)
> 				goto failed;
> 			amdgpu_connector->con_priv = amdgpu_dig_connector;
>-			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
>-			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
> 			if (i2c_bus->valid) {
> 				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
> 				if (!amdgpu_connector->ddc_bus)
> 					DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
>+				else
>+					ddc = &amdgpu_connector->ddc_bus->adapter;
> 			}
>+			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
>+						    &amdgpu_connector_dvi_funcs,
>+						    connector_type,
>+						    ddc);
>+			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
> 			subpixel_order = SubPixelHorizontalRGB;
> 			drm_object_attach_property(&amdgpu_connector->base.base,
> 						      adev->mode_info.coherent_mode_property,
>@@ -1754,13 +1778,18 @@
> 			if (!amdgpu_dig_connector)
> 				goto failed;
> 			amdgpu_connector->con_priv = amdgpu_dig_connector;
>-			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
>-			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
> 			if (i2c_bus->valid) {
> 				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
> 				if (!amdgpu_connector->ddc_bus)
> 					DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
>+				else
>+					ddc = &amdgpu_connector->ddc_bus->adapter;
> 			}
>+			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
>+						    &amdgpu_connector_dvi_funcs,
>+						    connector_type,
>+						    ddc);
>+			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
> 			drm_object_attach_property(&amdgpu_connector->base.base,
> 						      adev->mode_info.coherent_mode_property,
> 						      1);
>@@ -1796,15 +1825,20 @@
> 			if (!amdgpu_dig_connector)
> 				goto failed;
> 			amdgpu_connector->con_priv = amdgpu_dig_connector;
>-			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
>-			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
> 			if (i2c_bus->valid) {
> 				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
>-				if (amdgpu_connector->ddc_bus)
>+				if (amdgpu_connector->ddc_bus) {
> 					has_aux = true;
>-				else
>+					ddc = &amdgpu_connector->ddc_bus->adapter;
>+				} else {
> 					DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
>+				}
> 			}
>+			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
>+						    &amdgpu_connector_dp_funcs,
>+						    connector_type,
>+						    ddc);
>+			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
> 			subpixel_order = SubPixelHorizontalRGB;
> 			drm_object_attach_property(&amdgpu_connector->base.base,
> 						      adev->mode_info.coherent_mode_property,
>@@ -1838,15 +1872,20 @@
> 			if (!amdgpu_dig_connector)
> 				goto failed;
> 			amdgpu_connector->con_priv = amdgpu_dig_connector;
>-			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
>-			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
> 			if (i2c_bus->valid) {
> 				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
>-				if (amdgpu_connector->ddc_bus)
>+				if (amdgpu_connector->ddc_bus) {
> 					has_aux = true;
>-				else
>+					ddc = &amdgpu_connector->ddc_bus->adapter;
>+				} else {
> 					DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
>+				}
> 			}
>+			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
>+						    &amdgpu_connector_edp_funcs,
>+						    connector_type,
>+						    ddc);
>+			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
> 			drm_object_attach_property(&amdgpu_connector->base.base,
> 						      dev->mode_config.scaling_mode_property,
> 						      DRM_MODE_SCALE_FULLSCREEN);
>@@ -1859,13 +1898,18 @@
> 			if (!amdgpu_dig_connector)
> 				goto failed;
> 			amdgpu_connector->con_priv = amdgpu_dig_connector;
>-			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
>-			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
> 			if (i2c_bus->valid) {
> 				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
> 				if (!amdgpu_connector->ddc_bus)
> 					DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
>+				else
>+					ddc = &amdgpu_connector->ddc_bus->adapter;
> 			}
>+			drm_connector_init_with_ddc(dev, &amdgpu_connector->base,
>+						    &amdgpu_connector_lvds_funcs,
>+						    connector_type,
>+						    ddc);
>+			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
> 			drm_object_attach_property(&amdgpu_connector->base.base,
> 						      dev->mode_config.scaling_mode_property,
> 						      DRM_MODE_SCALE_FULLSCREEN);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c	2019-08-31 15:01:12.278736205 -0500
>@@ -402,7 +402,7 @@
> 	struct ttm_operation_ctx ctx = {
> 		.interruptible = true,
> 		.no_wait_gpu = false,
>-		.resv = bo->tbo.resv,
>+		.resv = bo->tbo.base.resv,
> 		.flags = 0
> 	};
> 	uint32_t domain;
>@@ -730,7 +730,7 @@
> 
> 	list_for_each_entry(e, &p->validated, tv.head) {
> 		struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
>-		struct reservation_object *resv = bo->tbo.resv;
>+		struct reservation_object *resv = bo->tbo.base.resv;
> 
> 		r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
> 				     amdgpu_bo_explicit_sync(bo));
>@@ -1732,7 +1732,7 @@
> 	*map = mapping;
> 
> 	/* Double check that the BO is reserved by this CS */
>-	if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
>+	if (reservation_object_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
> 		return -EINVAL;
> 
> 	if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c	2019-08-31 15:01:11.840736167 -0500
>@@ -42,7 +42,7 @@
> 	[AMDGPU_HW_IP_VCN_JPEG]	=	1,
> };
> 
>-static int amdgput_ctx_total_num_entities(void)
>+static int amdgpu_ctx_total_num_entities(void)
> {
> 	unsigned i, num_entities = 0;
> 
>@@ -73,8 +73,8 @@
> 			   struct drm_file *filp,
> 			   struct amdgpu_ctx *ctx)
> {
>-	unsigned num_entities = amdgput_ctx_total_num_entities();
>-	unsigned i, j;
>+	unsigned num_entities = amdgpu_ctx_total_num_entities();
>+	unsigned i, j, k;
> 	int r;
> 
> 	if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
>@@ -123,7 +123,7 @@
> 	for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
> 		struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
> 		struct drm_sched_rq *rqs[AMDGPU_MAX_RINGS];
>-		unsigned num_rings;
>+		unsigned num_rings = 0;
> 		unsigned num_rqs = 0;
> 
> 		switch (i) {
>@@ -154,16 +154,26 @@
> 			num_rings = 1;
> 			break;
> 		case AMDGPU_HW_IP_VCN_DEC:
>-			rings[0] = &adev->vcn.ring_dec;
>-			num_rings = 1;
>+			for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
>+				if (adev->vcn.harvest_config & (1 << j))
>+					continue;
>+				rings[num_rings++] = &adev->vcn.inst[j].ring_dec;
>+			}
> 			break;
> 		case AMDGPU_HW_IP_VCN_ENC:
>-			rings[0] = &adev->vcn.ring_enc[0];
>-			num_rings = 1;
>+			for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
>+				if (adev->vcn.harvest_config & (1 << j))
>+					continue;
>+				for (k = 0; k < adev->vcn.num_enc_rings; ++k)
>+					rings[num_rings++] = &adev->vcn.inst[j].ring_enc[k];
>+			}
> 			break;
> 		case AMDGPU_HW_IP_VCN_JPEG:
>-			rings[0] = &adev->vcn.ring_jpeg;
>-			num_rings = 1;
>+			for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
>+				if (adev->vcn.harvest_config & (1 << j))
>+					continue;
>+				rings[num_rings++] = &adev->vcn.inst[j].ring_jpeg;
>+			}
> 			break;
> 		}
> 
>@@ -197,7 +207,7 @@
> static void amdgpu_ctx_fini(struct kref *ref)
> {
> 	struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount);
>-	unsigned num_entities = amdgput_ctx_total_num_entities();
>+	unsigned num_entities = amdgpu_ctx_total_num_entities();
> 	struct amdgpu_device *adev = ctx->adev;
> 	unsigned i, j;
> 
>@@ -279,10 +289,7 @@
> 
> 	ctx = container_of(ref, struct amdgpu_ctx, refcount);
> 
>-	num_entities = 0;
>-	for (i = 0; i < AMDGPU_HW_IP_NUM; i++)
>-		num_entities += amdgpu_ctx_num_entities[i];
>-
>+	num_entities = amdgpu_ctx_total_num_entities();
> 	for (i = 0; i < num_entities; i++)
> 		drm_sched_entity_destroy(&ctx->entities[0][i].entity);
> 
>@@ -344,7 +351,7 @@
> {
> 	struct amdgpu_ctx *ctx;
> 	struct amdgpu_ctx_mgr *mgr;
>-	uint32_t ras_counter;
>+	unsigned long ras_counter;
> 
> 	if (!fpriv)
> 		return -EINVAL;
>@@ -514,7 +521,7 @@
> void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
> 				  enum drm_sched_priority priority)
> {
>-	unsigned num_entities = amdgput_ctx_total_num_entities();
>+	unsigned num_entities = amdgpu_ctx_total_num_entities();
> 	enum drm_sched_priority ctx_prio;
> 	unsigned i;
> 
>@@ -534,21 +541,24 @@
> 			       struct drm_sched_entity *entity)
> {
> 	struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity);
>-	unsigned idx = centity->sequence & (amdgpu_sched_jobs - 1);
>-	struct dma_fence *other = centity->fences[idx];
>+	struct dma_fence *other;
>+	unsigned idx;
>+	long r;
> 
>-	if (other) {
>-		signed long r;
>-		r = dma_fence_wait(other, true);
>-		if (r < 0) {
>-			if (r != -ERESTARTSYS)
>-				DRM_ERROR("Error (%ld) waiting for fence!\n", r);
>+	spin_lock(&ctx->ring_lock);
>+	idx = centity->sequence & (amdgpu_sched_jobs - 1);
>+	other = dma_fence_get(centity->fences[idx]);
>+	spin_unlock(&ctx->ring_lock);
> 
>-			return r;
>-		}
>-	}
>+	if (!other)
>+		return 0;
> 
>-	return 0;
>+	r = dma_fence_wait(other, true);
>+	if (r < 0 && r != -ERESTARTSYS)
>+		DRM_ERROR("Error (%ld) waiting for fence!\n", r);
>+
>+	dma_fence_put(other);
>+	return r;
> }
> 
> void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr)
>@@ -559,7 +569,7 @@
> 
> long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout)
> {
>-	unsigned num_entities = amdgput_ctx_total_num_entities();
>+	unsigned num_entities = amdgpu_ctx_total_num_entities();
> 	struct amdgpu_ctx *ctx;
> 	struct idr *idp;
> 	uint32_t id, i;
>@@ -581,7 +591,7 @@
> 
> void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr)
> {
>-	unsigned num_entities = amdgput_ctx_total_num_entities();
>+	unsigned num_entities = amdgpu_ctx_total_num_entities();
> 	struct amdgpu_ctx *ctx;
> 	struct idr *idp;
> 	uint32_t id, i;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h	2019-08-31 15:01:11.840736167 -0500
>@@ -49,8 +49,8 @@
> 	enum drm_sched_priority		override_priority;
> 	struct mutex			lock;
> 	atomic_t			guilty;
>-	uint32_t			ras_counter_ce;
>-	uint32_t			ras_counter_ue;
>+	unsigned long			ras_counter_ce;
>+	unsigned long			ras_counter_ue;
> };
> 
> struct amdgpu_ctx_mgr {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c	2019-08-31 15:01:11.841736167 -0500
>@@ -70,7 +70,11 @@
> MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
> MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
> MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
>+MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
>+MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
> MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
>+MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
>+MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
> 
> #define AMDGPU_RESUME_MS		2000
> 
>@@ -98,7 +102,11 @@
> 	"VEGA12",
> 	"VEGA20",
> 	"RAVEN",
>+	"ARCTURUS",
>+	"RENOIR",
> 	"NAVI10",
>+	"NAVI14",
>+	"NAVI12",
> 	"LAST",
> };
> 
>@@ -413,6 +421,40 @@
> }
> 
> /**
>+ * amdgpu_invalid_rreg64 - dummy 64 bit reg read function
>+ *
>+ * @adev: amdgpu device pointer
>+ * @reg: offset of register
>+ *
>+ * Dummy register read function.  Used for register blocks
>+ * that certain asics don't have (all asics).
>+ * Returns the value in the register.
>+ */
>+static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
>+{
>+	DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
>+	BUG();
>+	return 0;
>+}
>+
>+/**
>+ * amdgpu_invalid_wreg64 - dummy reg write function
>+ *
>+ * @adev: amdgpu device pointer
>+ * @reg: offset of register
>+ * @v: value to write to the register
>+ *
>+ * Dummy register read function.  Used for register blocks
>+ * that certain asics don't have (all asics).
>+ */
>+static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
>+{
>+	DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n",
>+		  reg, v);
>+	BUG();
>+}
>+
>+/**
>  * amdgpu_block_invalid_rreg - dummy reg read function
>  *
>  * @adev: amdgpu device pointer
>@@ -1384,9 +1426,21 @@
> 		else
> 			chip_name = "raven";
> 		break;
>+	case CHIP_ARCTURUS:
>+		chip_name = "arcturus";
>+		break;
>+	case CHIP_RENOIR:
>+		chip_name = "renoir";
>+		break;
> 	case CHIP_NAVI10:
> 		chip_name = "navi10";
> 		break;
>+	case CHIP_NAVI14:
>+		chip_name = "navi14";
>+		break;
>+	case CHIP_NAVI12:
>+		chip_name = "navi12";
>+		break;
> 	}
> 
> 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
>@@ -1529,7 +1583,10 @@
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
> 	case CHIP_RAVEN:
>-		if (adev->asic_type == CHIP_RAVEN)
>+	case CHIP_ARCTURUS:
>+	case CHIP_RENOIR:
>+		if (adev->asic_type == CHIP_RAVEN ||
>+		    adev->asic_type == CHIP_RENOIR)
> 			adev->family = AMDGPU_FAMILY_RV;
> 		else
> 			adev->family = AMDGPU_FAMILY_AI;
>@@ -1539,6 +1596,8 @@
> 			return r;
> 		break;
> 	case  CHIP_NAVI10:
>+	case  CHIP_NAVI14:
>+	case  CHIP_NAVI12:
> 		adev->family = AMDGPU_FAMILY_NV;
> 
> 		r = nv_set_ip_blocks(adev);
>@@ -1560,9 +1619,6 @@
> 		r = amdgpu_virt_request_full_gpu(adev, true);
> 		if (r)
> 			return -EAGAIN;
>-
>-		/* query the reg access mode at the very beginning */
>-		amdgpu_virt_init_reg_access_mode(adev);
> 	}
> 
> 	adev->pm.pp_feature = amdgpu_pp_feature_mask;
>@@ -1665,28 +1721,34 @@
> 
> 	if (adev->asic_type >= CHIP_VEGA10) {
> 		for (i = 0; i < adev->num_ip_blocks; i++) {
>-			if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
>-				if (adev->in_gpu_reset || adev->in_suspend) {
>-					if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset)
>-						break; /* sriov gpu reset, psp need to do hw_init before IH because of hw limit */
>-					r = adev->ip_blocks[i].version->funcs->resume(adev);
>-					if (r) {
>-						DRM_ERROR("resume of IP block <%s> failed %d\n",
>+			if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP)
>+				continue;
>+
>+			/* no need to do the fw loading again if already done*/
>+			if (adev->ip_blocks[i].status.hw == true)
>+				break;
>+
>+			if (adev->in_gpu_reset || adev->in_suspend) {
>+				r = adev->ip_blocks[i].version->funcs->resume(adev);
>+				if (r) {
>+					DRM_ERROR("resume of IP block <%s> failed %d\n",
> 							  adev->ip_blocks[i].version->funcs->name, r);
>-						return r;
>-					}
>-				} else {
>-					r = adev->ip_blocks[i].version->funcs->hw_init(adev);
>-					if (r) {
>-						DRM_ERROR("hw_init of IP block <%s> failed %d\n",
>-						  adev->ip_blocks[i].version->funcs->name, r);
>-						return r;
>-					}
>+					return r;
>+				}
>+			} else {
>+				r = adev->ip_blocks[i].version->funcs->hw_init(adev);
>+				if (r) {
>+					DRM_ERROR("hw_init of IP block <%s> failed %d\n",
>+							  adev->ip_blocks[i].version->funcs->name, r);
>+					return r;
> 				}
>-				adev->ip_blocks[i].status.hw = true;
> 			}
>+
>+			adev->ip_blocks[i].status.hw = true;
>+			break;
> 		}
> 	}
>+
> 	r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
> 
> 	return r;
>@@ -2128,7 +2190,9 @@
> 			if (r) {
> 				DRM_ERROR("suspend of IP block <%s> failed %d\n",
> 					  adev->ip_blocks[i].version->funcs->name, r);
>+				return r;
> 			}
>+			adev->ip_blocks[i].status.hw = false;
> 		}
> 	}
> 
>@@ -2163,6 +2227,25 @@
> 			DRM_ERROR("suspend of IP block <%s> failed %d\n",
> 				  adev->ip_blocks[i].version->funcs->name, r);
> 		}
>+		adev->ip_blocks[i].status.hw = false;
>+		/* handle putting the SMC in the appropriate state */
>+		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
>+			if (is_support_sw_smu(adev)) {
>+				/* todo */
>+			} else if (adev->powerplay.pp_funcs &&
>+					   adev->powerplay.pp_funcs->set_mp1_state) {
>+				r = adev->powerplay.pp_funcs->set_mp1_state(
>+					adev->powerplay.pp_handle,
>+					adev->mp1_state);
>+				if (r) {
>+					DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
>+						  adev->mp1_state, r);
>+					return r;
>+				}
>+			}
>+		}
>+
>+		adev->ip_blocks[i].status.hw = false;
> 	}
> 
> 	return 0;
>@@ -2215,6 +2298,7 @@
> 		for (j = 0; j < adev->num_ip_blocks; j++) {
> 			block = &adev->ip_blocks[j];
> 
>+			block->status.hw = false;
> 			if (block->version->type != ip_order[i] ||
> 				!block->status.valid)
> 				continue;
>@@ -2223,6 +2307,7 @@
> 			DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
> 			if (r)
> 				return r;
>+			block->status.hw = true;
> 		}
> 	}
> 
>@@ -2250,13 +2335,15 @@
> 			block = &adev->ip_blocks[j];
> 
> 			if (block->version->type != ip_order[i] ||
>-				!block->status.valid)
>+				!block->status.valid ||
>+				block->status.hw)
> 				continue;
> 
> 			r = block->version->funcs->hw_init(adev);
> 			DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded");
> 			if (r)
> 				return r;
>+			block->status.hw = true;
> 		}
> 	}
> 
>@@ -2280,17 +2367,19 @@
> 	int i, r;
> 
> 	for (i = 0; i < adev->num_ip_blocks; i++) {
>-		if (!adev->ip_blocks[i].status.valid)
>+		if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
> 			continue;
> 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
> 		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
> 		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
>+
> 			r = adev->ip_blocks[i].version->funcs->resume(adev);
> 			if (r) {
> 				DRM_ERROR("resume of IP block <%s> failed %d\n",
> 					  adev->ip_blocks[i].version->funcs->name, r);
> 				return r;
> 			}
>+			adev->ip_blocks[i].status.hw = true;
> 		}
> 	}
> 
>@@ -2315,7 +2404,7 @@
> 	int i, r;
> 
> 	for (i = 0; i < adev->num_ip_blocks; i++) {
>-		if (!adev->ip_blocks[i].status.valid)
>+		if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw)
> 			continue;
> 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
> 		    adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
>@@ -2328,6 +2417,7 @@
> 				  adev->ip_blocks[i].version->funcs->name, r);
> 			return r;
> 		}
>+		adev->ip_blocks[i].status.hw = true;
> 	}
> 
> 	return 0;
>@@ -2426,6 +2516,11 @@
> #endif
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
>+#endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	case CHIP_RENOIR:
> #endif
> 		return amdgpu_dc != 0;
> #endif
>@@ -2509,6 +2604,8 @@
> 	adev->pcie_wreg = &amdgpu_invalid_wreg;
> 	adev->pciep_rreg = &amdgpu_invalid_rreg;
> 	adev->pciep_wreg = &amdgpu_invalid_wreg;
>+	adev->pcie_rreg64 = &amdgpu_invalid_rreg64;
>+	adev->pcie_wreg64 = &amdgpu_invalid_wreg64;
> 	adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
> 	adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
> 	adev->didt_rreg = &amdgpu_invalid_rreg;
>@@ -3389,7 +3486,7 @@
> 	amdgpu_virt_init_data_exchange(adev);
> 	amdgpu_virt_release_full_gpu(adev, true);
> 	if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
>-		atomic_inc(&adev->vram_lost_counter);
>+		amdgpu_inc_vram_lost(adev);
> 		r = amdgpu_device_recover_vram(adev);
> 	}
> 
>@@ -3431,6 +3528,7 @@
> 		case CHIP_VEGA20:
> 		case CHIP_VEGA10:
> 		case CHIP_VEGA12:
>+		case CHIP_RAVEN:
> 			break;
> 		default:
> 			goto disabled;
>@@ -3554,7 +3652,7 @@
> 				vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
> 				if (vram_lost) {
> 					DRM_INFO("VRAM is lost due to GPU reset!\n");
>-					atomic_inc(&tmp_adev->vram_lost_counter);
>+					amdgpu_inc_vram_lost(tmp_adev);
> 				}
> 
> 				r = amdgpu_gtt_mgr_recover(
>@@ -3627,6 +3725,17 @@
> 
> 	atomic_inc(&adev->gpu_reset_counter);
> 	adev->in_gpu_reset = 1;
>+	switch (amdgpu_asic_reset_method(adev)) {
>+	case AMD_RESET_METHOD_MODE1:
>+		adev->mp1_state = PP_MP1_STATE_SHUTDOWN;
>+		break;
>+	case AMD_RESET_METHOD_MODE2:
>+		adev->mp1_state = PP_MP1_STATE_RESET;
>+		break;
>+	default:
>+		adev->mp1_state = PP_MP1_STATE_NONE;
>+		break;
>+	}
> 	/* Block kfd: SRIOV would do it separately */
> 	if (!amdgpu_sriov_vf(adev))
>                 amdgpu_amdkfd_pre_reset(adev);
>@@ -3640,6 +3749,7 @@
> 	if (!amdgpu_sriov_vf(adev))
>                 amdgpu_amdkfd_post_reset(adev);
> 	amdgpu_vf_error_trans_all(adev);
>+	adev->mp1_state = PP_MP1_STATE_NONE;
> 	adev->in_gpu_reset = 0;
> 	mutex_unlock(&adev->lock_reset);
> }
>@@ -3684,14 +3794,14 @@
> 
> 	if (hive && !mutex_trylock(&hive->reset_lock)) {
> 		DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
>-			 job->base.id, hive->hive_id);
>+			  job ? job->base.id : -1, hive->hive_id);
> 		return 0;
> 	}
> 
> 	/* Start with adev pre asic reset first for soft reset check.*/
> 	if (!amdgpu_device_lock_adev(adev, !hive)) {
> 		DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
>-					 job->base.id);
>+			  job ? job->base.id : -1);
> 		return 0;
> 	}
> 
>@@ -3732,7 +3842,7 @@
> 			if (!ring || !ring->sched.thread)
> 				continue;
> 
>-			drm_sched_stop(&ring->sched, &job->base);
>+			drm_sched_stop(&ring->sched, job ? &job->base : NULL);
> 		}
> 	}
> 
>@@ -3757,9 +3867,7 @@
> 
> 
> 	/* Guilty job will be freed after this*/
>-	r = amdgpu_device_pre_asic_reset(adev,
>-					 job,
>-					 &need_full_reset);
>+	r = amdgpu_device_pre_asic_reset(adev, job, &need_full_reset);
> 	if (r) {
> 		/*TODO Should we stop ?*/
> 		DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c	2019-08-31 15:01:11.841736167 -0500
>@@ -191,7 +191,8 @@
> 	}
> 
> 	if (!adev->enable_virtual_display) {
>-		r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
>+		r = amdgpu_bo_pin(new_abo,
>+				  amdgpu_display_supported_domains(adev, new_abo->flags));
> 		if (unlikely(r != 0)) {
> 			DRM_ERROR("failed to pin new abo buffer before flip\n");
> 			goto unreserve;
>@@ -204,7 +205,7 @@
> 		goto unpin;
> 	}
> 
>-	r = reservation_object_get_fences_rcu(new_abo->tbo.resv, &work->excl,
>+	r = reservation_object_get_fences_rcu(new_abo->tbo.base.resv, &work->excl,
> 					      &work->shared_count,
> 					      &work->shared);
> 	if (unlikely(r != 0)) {
>@@ -495,13 +496,25 @@
> 	.create_handle = drm_gem_fb_create_handle,
> };
> 
>-uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
>+uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
>+					  uint64_t bo_flags)
> {
> 	uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
> 
> #if defined(CONFIG_DRM_AMD_DC)
>-	if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
>-	    adev->flags & AMD_IS_APU &&
>+	/*
>+	 * if amdgpu_bo_support_uswc returns false it means that USWC mappings
>+	 * is not supported for this board. But this mapping is required
>+	 * to avoid hang caused by placement of scanout BO in GTT on certain
>+	 * APUs. So force the BO placement to VRAM in case this architecture
>+	 * will not allow USWC mappings.
>+	 * Also, don't allow GTT domain if the BO doens't have USWC falg set.
>+	 */
>+	if (adev->asic_type >= CHIP_CARRIZO &&
>+	    adev->asic_type <= CHIP_RAVEN &&
>+	    (adev->flags & AMD_IS_APU) &&
>+	    (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
>+	    amdgpu_bo_support_uswc(bo_flags) &&
> 	    amdgpu_device_asic_has_dc_support(adev->asic_type))
> 		domain |= AMDGPU_GEM_DOMAIN_GTT;
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h	2019-08-31 15:01:11.841736167 -0500
>@@ -38,7 +38,8 @@
> int amdgpu_display_freesync_ioctl(struct drm_device *dev, void *data,
> 				  struct drm_file *filp);
> void amdgpu_display_update_priority(struct amdgpu_device *adev);
>-uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev);
>+uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
>+					  uint64_t bo_flags);
> struct drm_framebuffer *
> amdgpu_display_user_framebuffer_create(struct drm_device *dev,
> 				       struct drm_file *file_priv,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c	2019-08-31 15:01:11.841736167 -0500
>@@ -216,7 +216,7 @@
> 		 * fences on the reservation object into a single exclusive
> 		 * fence.
> 		 */
>-		r = __reservation_object_make_exclusive(bo->tbo.resv);
>+		r = __reservation_object_make_exclusive(bo->tbo.base.resv);
> 		if (r)
> 			goto error_unreserve;
> 	}
>@@ -268,20 +268,6 @@
> }
> 
> /**
>- * amdgpu_gem_prime_res_obj - &drm_driver.gem_prime_res_obj implementation
>- * @obj: GEM BO
>- *
>- * Returns:
>- * The BO's reservation object.
>- */
>-struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj)
>-{
>-	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
>-
>-	return bo->tbo.resv;
>-}
>-
>-/**
>  * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
>  * @dma_buf: Shared DMA buffer
>  * @direction: Direction of DMA transfer
>@@ -299,7 +285,7 @@
> 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
> 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> 	struct ttm_operation_ctx ctx = { true, false };
>-	u32 domain = amdgpu_display_supported_domains(adev);
>+	u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
> 	int ret;
> 	bool reads = (direction == DMA_BIDIRECTIONAL ||
> 		      direction == DMA_FROM_DEVICE);
>@@ -339,14 +325,12 @@
>  * @gobj: GEM BO
>  * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
>  *
>- * The main work is done by the &drm_gem_prime_export helper, which in turn
>- * uses &amdgpu_gem_prime_res_obj.
>+ * The main work is done by the &drm_gem_prime_export helper.
>  *
>  * Returns:
>  * Shared DMA buffer representing the GEM BO from the given device.
>  */
>-struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
>-					struct drm_gem_object *gobj,
>+struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
> 					int flags)
> {
> 	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
>@@ -356,9 +340,9 @@
> 	    bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
> 		return ERR_PTR(-EPERM);
> 
>-	buf = drm_gem_prime_export(dev, gobj, flags);
>+	buf = drm_gem_prime_export(gobj, flags);
> 	if (!IS_ERR(buf)) {
>-		buf->file->f_mapping = dev->anon_inode->i_mapping;
>+		buf->file->f_mapping = gobj->dev->anon_inode->i_mapping;
> 		buf->ops = &amdgpu_dmabuf_ops;
> 	}
> 
>@@ -396,7 +380,7 @@
> 	bp.flags = 0;
> 	bp.type = ttm_bo_type_sg;
> 	bp.resv = resv;
>-	ww_mutex_lock(&resv->lock, NULL);
>+	reservation_object_lock(resv, NULL);
> 	ret = amdgpu_bo_create(adev, &bp, &bo);
> 	if (ret)
> 		goto error;
>@@ -408,11 +392,11 @@
> 	if (attach->dmabuf->ops != &amdgpu_dmabuf_ops)
> 		bo->prime_shared_count = 1;
> 
>-	ww_mutex_unlock(&resv->lock);
>-	return &bo->gem_base;
>+	reservation_object_unlock(resv);
>+	return &bo->tbo.base;
> 
> error:
>-	ww_mutex_unlock(&resv->lock);
>+	reservation_object_unlock(resv);
> 	return ERR_PTR(ret);
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h	2019-08-31 15:01:11.841736167 -0500
>@@ -30,12 +30,10 @@
> amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
> 				 struct dma_buf_attachment *attach,
> 				 struct sg_table *sg);
>-struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
>-					struct drm_gem_object *gobj,
>+struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
> 					int flags);
> struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
> 					    struct dma_buf *dma_buf);
>-struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
> void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
> void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
> int amdgpu_gem_prime_mmap(struct drm_gem_object *obj,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h	2019-08-31 15:01:11.841736167 -0500
>@@ -130,13 +130,18 @@
> 	AMDGPU_VEGA20_DOORBELL_IH                      = 0x178,
> 	/* MMSCH: 392~407
> 	 * overlap the doorbell assignment with VCN as they are  mutually exclusive
>-	 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
>+	 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD
> 	 */
>-	AMDGPU_VEGA20_DOORBELL64_VCN0_1                  = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
>+	AMDGPU_VEGA20_DOORBELL64_VCN0_1                  = 0x188, /* VNC0 */
> 	AMDGPU_VEGA20_DOORBELL64_VCN2_3                  = 0x189,
> 	AMDGPU_VEGA20_DOORBELL64_VCN4_5                  = 0x18A,
> 	AMDGPU_VEGA20_DOORBELL64_VCN6_7                  = 0x18B,
> 
>+	AMDGPU_VEGA20_DOORBELL64_VCN8_9                  = 0x18C, /* VNC1 */
>+	AMDGPU_VEGA20_DOORBELL64_VCNa_b                  = 0x18D,
>+	AMDGPU_VEGA20_DOORBELL64_VCNc_d                  = 0x18E,
>+	AMDGPU_VEGA20_DOORBELL64_VCNe_f                  = 0x18F,
>+
> 	AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1             = 0x188,
> 	AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3             = 0x189,
> 	AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5             = 0x18A,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c	2019-08-31 15:01:11.841736167 -0500
>@@ -79,9 +79,10 @@
>  * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
>  * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
>  * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
>+ * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
>  */
> #define KMS_DRIVER_MAJOR	3
>-#define KMS_DRIVER_MINOR	33
>+#define KMS_DRIVER_MINOR	34
> #define KMS_DRIVER_PATCHLEVEL	0
> 
> #define AMDGPU_MAX_TIMEOUT_PARAM_LENTH	256
>@@ -142,7 +143,7 @@
> int amdgpu_mcbp = 0;
> int amdgpu_discovery = -1;
> int amdgpu_mes = 0;
>-int amdgpu_noretry;
>+int amdgpu_noretry = 1;
> 
> struct amdgpu_mgpu_info mgpu_info = {
> 	.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
>@@ -610,7 +611,7 @@
> module_param_named(mes, amdgpu_mes, int, 0444);
> 
> MODULE_PARM_DESC(noretry,
>-	"Disable retry faults (0 = retry enabled (default), 1 = retry disabled)");
>+	"Disable retry faults (0 = retry enabled, 1 = retry disabled (default))");
> module_param_named(noretry, amdgpu_noretry, int, 0644);
> 
> #ifdef CONFIG_HSA_AMD
>@@ -996,6 +997,11 @@
> 	/* Raven */
> 	{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
> 	{0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
>+	/* Arcturus */
>+	{0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
>+	{0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
>+	{0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
>+	{0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
> 	/* Navi10 */
> 	{0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
> 	{0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
>@@ -1004,6 +1010,11 @@
> 	{0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
> 	{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
> 	{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
>+	/* Navi14 */
>+	{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
>+
>+	/* Renoir */
>+	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},
> 
> 	{0, 0, 0}
> };
>@@ -1092,21 +1103,21 @@
> 	 * unfortunately we can't detect certain
> 	 * hypervisors so just do this all the time.
> 	 */
>+	adev->mp1_state = PP_MP1_STATE_UNLOAD;
> 	amdgpu_device_ip_suspend(adev);
>+	adev->mp1_state = PP_MP1_STATE_NONE;
> }
> 
> static int amdgpu_pmops_suspend(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
> 	return amdgpu_device_suspend(drm_dev, true, true);
> }
> 
> static int amdgpu_pmops_resume(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 
> 	/* GPU comes up enabled by the bios on resume */
> 	if (amdgpu_device_is_px(drm_dev)) {
>@@ -1120,33 +1131,29 @@
> 
> static int amdgpu_pmops_freeze(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
> 	return amdgpu_device_suspend(drm_dev, false, true);
> }
> 
> static int amdgpu_pmops_thaw(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
> 	return amdgpu_device_resume(drm_dev, false, true);
> }
> 
> static int amdgpu_pmops_poweroff(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
> 	return amdgpu_device_suspend(drm_dev, true, true);
> }
> 
> static int amdgpu_pmops_restore(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
> 	return amdgpu_device_resume(drm_dev, false, true);
> }
> 
>@@ -1205,8 +1212,7 @@
> 
> static int amdgpu_pmops_runtime_idle(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 	struct drm_crtc *crtc;
> 
> 	if (!amdgpu_device_is_px(drm_dev)) {
>@@ -1373,7 +1379,7 @@
> 	.driver_features =
> 	    DRIVER_USE_AGP | DRIVER_ATOMIC |
> 	    DRIVER_GEM |
>-	    DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
>+	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ,
> 	.load = amdgpu_driver_load_kms,
> 	.open = amdgpu_driver_open_kms,
> 	.postclose = amdgpu_driver_postclose_kms,
>@@ -1397,7 +1403,6 @@
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> 	.gem_prime_export = amdgpu_gem_prime_export,
> 	.gem_prime_import = amdgpu_gem_prime_import,
>-	.gem_prime_res_obj = amdgpu_gem_prime_res_obj,
> 	.gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
> 	.gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
> 	.gem_prime_vmap = amdgpu_gem_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c	2019-08-31 15:01:11.841736167 -0500
>@@ -131,6 +131,10 @@
> 	int aligned_size, size;
> 	int height = mode_cmd->height;
> 	u32 cpp;
>+	u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
>+			       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS     |
>+			       AMDGPU_GEM_CREATE_VRAM_CLEARED 	     |
>+			       AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> 
> 	info = drm_get_format_info(adev->ddev, mode_cmd);
> 	cpp = info->cpp[0];
>@@ -138,15 +142,11 @@
> 	/* need to align pitch with crtc limits */
> 	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
> 						  fb_tiled);
>-	domain = amdgpu_display_supported_domains(adev);
>-
>+	domain = amdgpu_display_supported_domains(adev, flags);
> 	height = ALIGN(mode_cmd->height, 8);
> 	size = mode_cmd->pitches[0] * height;
> 	aligned_size = ALIGN(size, PAGE_SIZE);
>-	ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
>-				       AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
>-				       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
>-				       AMDGPU_GEM_CREATE_VRAM_CLEARED,
>+	ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags,
> 				       ttm_bo_type_kernel, NULL, &gobj);
> 	if (ret) {
> 		pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
>@@ -168,7 +168,6 @@
> 			dev_err(adev->dev, "FB failed to set tiling flags\n");
> 	}
> 
>-
> 	ret = amdgpu_bo_pin(abo, domain);
> 	if (ret) {
> 		amdgpu_bo_unreserve(abo);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c	2019-08-31 15:01:11.841736167 -0500
>@@ -251,7 +251,9 @@
> 	}
> 	mb();
> 	amdgpu_asic_flush_hdp(adev, NULL);
>-	amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);
>+	for (i = 0; i < adev->num_vmhubs; i++)
>+		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
>+
> 	return 0;
> }
> 
>@@ -310,9 +312,9 @@
> 		     uint64_t flags)
> {
> #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
>-	unsigned i,t,p;
>+	unsigned t,p;
> #endif
>-	int r;
>+	int r, i;
> 
> 	if (!adev->gart.ready) {
> 		WARN(1, "trying to bind memory to uninitialized GART !\n");
>@@ -336,7 +338,8 @@
> 
> 	mb();
> 	amdgpu_asic_flush_hdp(adev, NULL);
>-	amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);
>+	for (i = 0; i < adev->num_vmhubs; i++)
>+		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
> 	return 0;
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c	2019-08-31 15:01:11.841736167 -0500
>@@ -85,7 +85,7 @@
> 		}
> 		return r;
> 	}
>-	*obj = &bo->gem_base;
>+	*obj = &bo->tbo.base;
> 
> 	return 0;
> }
>@@ -134,7 +134,7 @@
> 		return -EPERM;
> 
> 	if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
>-	    abo->tbo.resv != vm->root.base.bo->tbo.resv)
>+	    abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
> 		return -EPERM;
> 
> 	r = amdgpu_bo_reserve(abo, false);
>@@ -252,7 +252,7 @@
> 		if (r)
> 			return r;
> 
>-		resv = vm->root.base.bo->tbo.resv;
>+		resv = vm->root.base.bo->tbo.base.resv;
> 	}
> 
> 	r = amdgpu_gem_object_create(adev, size, args->in.alignment,
>@@ -433,7 +433,7 @@
> 		return -ENOENT;
> 	}
> 	robj = gem_to_amdgpu_bo(gobj);
>-	ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
>+	ret = reservation_object_wait_timeout_rcu(robj->tbo.base.resv, true, true,
> 						  timeout);
> 
> 	/* ret == 0 means not signaled,
>@@ -689,7 +689,7 @@
> 		struct drm_amdgpu_gem_create_in info;
> 		void __user *out = u64_to_user_ptr(args->value);
> 
>-		info.bo_size = robj->gem_base.size;
>+		info.bo_size = robj->tbo.base.size;
> 		info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
> 		info.domains = robj->preferred_domains;
> 		info.domain_flags = robj->flags;
>@@ -747,7 +747,8 @@
> 	struct amdgpu_device *adev = dev->dev_private;
> 	struct drm_gem_object *gobj;
> 	uint32_t handle;
>-	u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
>+	u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
>+		    AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> 	u32 domain;
> 	int r;
> 
>@@ -764,7 +765,7 @@
> 	args->size = (u64)args->pitch * args->height;
> 	args->size = ALIGN(args->size, PAGE_SIZE);
> 	domain = amdgpu_bo_get_preferred_pin_domain(adev,
>-				amdgpu_display_supported_domains(adev));
>+				amdgpu_display_supported_domains(adev, flags));
> 	r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
> 				     ttm_bo_type_device, NULL, &gobj);
> 	if (r)
>@@ -819,8 +820,8 @@
> 	if (pin_count)
> 		seq_printf(m, " pin count %d", pin_count);
> 
>-	dma_buf = READ_ONCE(bo->gem_base.dma_buf);
>-	attachment = READ_ONCE(bo->gem_base.import_attach);
>+	dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
>+	attachment = READ_ONCE(bo->tbo.base.import_attach);
> 
> 	if (attachment)
> 		seq_printf(m, " imported from %p", dma_buf);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h	2019-08-31 15:01:11.841736167 -0500
>@@ -31,7 +31,7 @@
>  */
> 
> #define AMDGPU_GEM_DOMAIN_MAX		0x3
>-#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
>+#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, tbo.base)
> 
> void amdgpu_gem_object_free(struct drm_gem_object *obj);
> int amdgpu_gem_object_open(struct drm_gem_object *obj,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c	2019-08-31 15:01:11.842736167 -0500
>@@ -389,7 +389,7 @@
> 				dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
> 	}
> 
>-	if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring) {
>+	if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
> 		/* create MQD for each KGQ */
> 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> 			ring = &adev->gfx.gfx_ring[i];
>@@ -437,7 +437,7 @@
> 	struct amdgpu_ring *ring = NULL;
> 	int i;
> 
>-	if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring) {
>+	if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
> 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> 			ring = &adev->gfx.gfx_ring[i];
> 			kfree(adev->gfx.me.mqd_backup[i]);
>@@ -456,7 +456,7 @@
> 	}
> 
> 	ring = &adev->gfx.kiq.ring;
>-	if (adev->asic_type == CHIP_NAVI10 && amdgpu_async_gfx_ring)
>+	if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring)
> 		kfree(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]);
> 	kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]);
> 	amdgpu_bo_free_kernel(&ring->mqd_obj,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h	2019-08-31 15:01:11.842736167 -0500
>@@ -196,6 +196,8 @@
> 				uint32_t *dst);
> 	void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
> 				 u32 queue, u32 vmid);
>+	int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
>+	int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
> };
> 
> struct amdgpu_ngg_buf {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c	2019-08-31 15:01:11.842736167 -0500
>@@ -220,6 +220,14 @@
> 	const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1);
> 	u64 size_af, size_bf;
> 
>+	if (amdgpu_sriov_vf(adev)) {
>+		mc->agp_start = 0xffffffff;
>+		mc->agp_end = 0x0;
>+		mc->agp_size = 0;
>+
>+		return;
>+	}
>+
> 	if (mc->fb_start > mc->gart_start) {
> 		size_bf = (mc->fb_start & sixteen_gb_mask) -
> 			ALIGN(mc->gart_end + 1, sixteen_gb);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h	2019-08-31 15:01:11.842736167 -0500
>@@ -89,8 +89,8 @@
>  */
> struct amdgpu_gmc_funcs {
> 	/* flush the vm tlb via mmio */
>-	void (*flush_gpu_tlb)(struct amdgpu_device *adev,
>-			      uint32_t vmid, uint32_t flush_type);
>+	void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
>+				uint32_t vmhub, uint32_t flush_type);
> 	/* flush the vm tlb via ring */
> 	uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
> 				       uint64_t pd_addr);
>@@ -177,10 +177,11 @@
> 
> 	struct amdgpu_xgmi xgmi;
> 	struct amdgpu_irq_src	ecc_irq;
>-	struct ras_common_if    *ras_if;
>+	struct ras_common_if    *umc_ras_if;
>+	struct ras_common_if    *mmhub_ras_if;
> };
> 
>-#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, type) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (type))
>+#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
> #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
> #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
> #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu.h	2019-08-31 15:01:11.839736167 -0500
>@@ -86,6 +86,8 @@
> #include "amdgpu_smu.h"
> #include "amdgpu_discovery.h"
> #include "amdgpu_mes.h"
>+#include "amdgpu_umc.h"
>+#include "amdgpu_mmhub.h"
> 
> #define MAX_GPU_INSTANCE		16
> 
>@@ -532,6 +534,14 @@
> 	bool grbm_indexed;
> };
> 
>+enum amd_reset_method {
>+	AMD_RESET_METHOD_LEGACY = 0,
>+	AMD_RESET_METHOD_MODE0,
>+	AMD_RESET_METHOD_MODE1,
>+	AMD_RESET_METHOD_MODE2,
>+	AMD_RESET_METHOD_BACO
>+};
>+
> /*
>  * ASIC specific functions.
>  */
>@@ -543,6 +553,7 @@
> 			     u32 sh_num, u32 reg_offset, u32 *value);
> 	void (*set_vga_state)(struct amdgpu_device *adev, bool state);
> 	int (*reset)(struct amdgpu_device *adev);
>+	enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
> 	/* get the reference clock */
> 	u32 (*get_xclk)(struct amdgpu_device *adev);
> 	/* MM block clocks */
>@@ -627,6 +638,9 @@
> typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
> typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
> 
>+typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
>+typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
>+
> typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
> typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
> 
>@@ -648,6 +662,12 @@
> 	u32 ref_and_mask_cp9;
> 	u32 ref_and_mask_sdma0;
> 	u32 ref_and_mask_sdma1;
>+	u32 ref_and_mask_sdma2;
>+	u32 ref_and_mask_sdma3;
>+	u32 ref_and_mask_sdma4;
>+	u32 ref_and_mask_sdma5;
>+	u32 ref_and_mask_sdma6;
>+	u32 ref_and_mask_sdma7;
> };
> 
> struct amdgpu_mmio_remap {
>@@ -668,7 +688,7 @@
> 	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
> 			bool use_doorbell, int doorbell_index, int doorbell_size);
> 	void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
>-			int doorbell_index);
>+				   int doorbell_index, int instance);
> 	void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
> 					 bool enable);
> 	void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
>@@ -705,6 +725,9 @@
> 					 int is_disable);
> 	void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
> 					 uint64_t *count);
>+	uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
>+	void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
>+			 uint32_t ficadl_val, uint32_t ficadh_val);
> };
> /* Define the HW IP blocks will be used in driver , add more if necessary */
> enum amd_hw_ip_block_type {
>@@ -712,6 +735,12 @@
> 	HDP_HWIP,
> 	SDMA0_HWIP,
> 	SDMA1_HWIP,
>+	SDMA2_HWIP,
>+	SDMA3_HWIP,
>+	SDMA4_HWIP,
>+	SDMA5_HWIP,
>+	SDMA6_HWIP,
>+	SDMA7_HWIP,
> 	MMHUB_HWIP,
> 	ATHUB_HWIP,
> 	NBIO_HWIP,
>@@ -728,10 +757,12 @@
> 	NBIF_HWIP,
> 	THM_HWIP,
> 	CLK_HWIP,
>+	UMC_HWIP,
>+	RSMU_HWIP,
> 	MAX_HWIP
> };
> 
>-#define HWIP_MAX_INSTANCE	6
>+#define HWIP_MAX_INSTANCE	8
> 
> struct amd_powerplay {
> 	void *pp_handle;
>@@ -758,7 +789,6 @@
> 	int				usec_timeout;
> 	const struct amdgpu_asic_funcs	*asic_funcs;
> 	bool				shutdown;
>-	bool				need_dma32;
> 	bool				need_swiotlb;
> 	bool				accel_working;
> 	struct notifier_block		acpi_nb;
>@@ -803,6 +833,8 @@
> 	amdgpu_wreg_t			pcie_wreg;
> 	amdgpu_rreg_t			pciep_rreg;
> 	amdgpu_wreg_t			pciep_wreg;
>+	amdgpu_rreg64_t			pcie_rreg64;
>+	amdgpu_wreg64_t			pcie_wreg64;
> 	/* protects concurrent UVD register access */
> 	spinlock_t uvd_ctx_idx_lock;
> 	amdgpu_rreg_t			uvd_ctx_rreg;
>@@ -836,6 +868,7 @@
> 	dma_addr_t			dummy_page_addr;
> 	struct amdgpu_vm_manager	vm_manager;
> 	struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];
>+	unsigned			num_vmhubs;
> 
> 	/* memory management */
> 	struct amdgpu_mman		mman;
>@@ -915,6 +948,9 @@
> 	/* KFD */
> 	struct amdgpu_kfd_dev		kfd;
> 
>+	/* UMC */
>+	struct amdgpu_umc		umc;
>+
> 	/* display related functionality */
> 	struct amdgpu_display_manager dm;
> 
>@@ -940,6 +976,7 @@
> 
> 	const struct amdgpu_nbio_funcs	*nbio_funcs;
> 	const struct amdgpu_df_funcs	*df_funcs;
>+	const struct amdgpu_mmhub_funcs	*mmhub_funcs;
> 
> 	/* delayed work_func for deferring clockgating during resume */
> 	struct delayed_work     delayed_init_work;
>@@ -965,6 +1002,7 @@
> 	/* record last mm index being written through WREG32*/
> 	unsigned long last_mm_index;
> 	bool                            in_gpu_reset;
>+	enum pp_mp1_state               mp1_state;
> 	struct mutex  lock_reset;
> 	struct amdgpu_doorbell_index doorbell_index;
> 
>@@ -1033,6 +1071,8 @@
> #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
> #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
> #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
>+#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
>+#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
> #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
> #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
> #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
>@@ -1093,6 +1133,7 @@
>  */
> #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
> #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
>+#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
> #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
> #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
> #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
>@@ -1110,6 +1151,7 @@
> #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
> #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
> #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
>+#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
> 
> /* Common functions */
> bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c	2019-08-31 15:01:11.842736167 -0500
>@@ -368,7 +368,8 @@
> 		 * are broken on Navi10 and Navi14.
> 		 */
> 		if (needs_flush && (adev->asic_type < CHIP_VEGA10 ||
>-				    adev->asic_type == CHIP_NAVI10))
>+				    adev->asic_type == CHIP_NAVI10 ||
>+				    adev->asic_type == CHIP_NAVI14))
> 			continue;
> 
> 		/* Good, we can use this VMID. Remember this submission as
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c	2019-08-31 15:01:11.842736167 -0500
>@@ -408,23 +408,38 @@
> 		break;
> 	case AMDGPU_HW_IP_VCN_DEC:
> 		type = AMD_IP_BLOCK_TYPE_VCN;
>-		if (adev->vcn.ring_dec.sched.ready)
>-			++num_rings;
>+		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>+			if (adev->uvd.harvest_config & (1 << i))
>+				continue;
>+
>+			if (adev->vcn.inst[i].ring_dec.sched.ready)
>+				++num_rings;
>+		}
> 		ib_start_alignment = 16;
> 		ib_size_alignment = 16;
> 		break;
> 	case AMDGPU_HW_IP_VCN_ENC:
> 		type = AMD_IP_BLOCK_TYPE_VCN;
>-		for (i = 0; i < adev->vcn.num_enc_rings; i++)
>-			if (adev->vcn.ring_enc[i].sched.ready)
>-				++num_rings;
>+		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>+			if (adev->uvd.harvest_config & (1 << i))
>+				continue;
>+
>+			for (j = 0; j < adev->vcn.num_enc_rings; j++)
>+				if (adev->vcn.inst[i].ring_enc[j].sched.ready)
>+					++num_rings;
>+		}
> 		ib_start_alignment = 64;
> 		ib_size_alignment = 1;
> 		break;
> 	case AMDGPU_HW_IP_VCN_JPEG:
> 		type = AMD_IP_BLOCK_TYPE_VCN;
>-		if (adev->vcn.ring_jpeg.sched.ready)
>-			++num_rings;
>+		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>+			if (adev->uvd.harvest_config & (1 << i))
>+				continue;
>+
>+			if (adev->vcn.inst[i].ring_jpeg.sched.ready)
>+				++num_rings;
>+		}
> 		ib_start_alignment = 16;
> 		ib_size_alignment = 16;
> 		break;
>@@ -1088,7 +1103,7 @@
> 	amdgpu_vm_fini(adev, &fpriv->vm);
> 
> 	if (pasid)
>-		amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
>+		amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
> 	amdgpu_bo_unref(&pd);
> 
> 	idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h	2019-08-31 15:01:11.842736167 -0500
>@@ -0,0 +1,31 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef __AMDGPU_MMHUB_H__
>+#define __AMDGPU_MMHUB_H__
>+
>+struct amdgpu_mmhub_funcs {
>+	void (*ras_init)(struct amdgpu_device *adev);
>+	void (*query_ras_error_count)(struct amdgpu_device *adev,
>+					void *ras_error_status);
>+};
>+
>+#endif
>+
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c	2019-08-31 15:01:11.842736167 -0500
>@@ -179,7 +179,7 @@
> 		if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end))
> 			continue;
> 
>-		r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
>+		r = reservation_object_wait_timeout_rcu(bo->tbo.base.resv,
> 			true, false, MAX_SCHEDULE_TIMEOUT);
> 		if (r <= 0)
> 			DRM_ERROR("(%ld) failed to wait for user bo\n", r);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c	2019-08-31 15:01:11.842736167 -0500
>@@ -80,14 +80,11 @@
> 	if (bo->pin_count > 0)
> 		amdgpu_bo_subtract_pin_size(bo);
> 
>-	if (bo->kfd_bo)
>-		amdgpu_amdkfd_unreserve_memory_limit(bo);
>-
> 	amdgpu_bo_kunmap(bo);
> 
>-	if (bo->gem_base.import_attach)
>-		drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
>-	drm_gem_object_release(&bo->gem_base);
>+	if (bo->tbo.base.import_attach)
>+		drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
>+	drm_gem_object_release(&bo->tbo.base);
> 	/* in case amdgpu_device_recover_vram got NULL of bo->parent */
> 	if (!list_empty(&bo->shadow_list)) {
> 		mutex_lock(&adev->shadow_list_lock);
>@@ -249,8 +246,9 @@
> 	bp.size = size;
> 	bp.byte_align = align;
> 	bp.domain = domain;
>-	bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
>-		AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
>+	bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
>+		: AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
>+	bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> 	bp.type = ttm_bo_type_kernel;
> 	bp.resv = NULL;
> 
>@@ -413,6 +411,40 @@
> 	return false;
> }
> 
>+bool amdgpu_bo_support_uswc(u64 bo_flags)
>+{
>+
>+#ifdef CONFIG_X86_32
>+	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
>+	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
>+	 */
>+	return false;
>+#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
>+	/* Don't try to enable write-combining when it can't work, or things
>+	 * may be slow
>+	 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
>+	 */
>+
>+#ifndef CONFIG_COMPILE_TEST
>+#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
>+	 thanks to write-combining
>+#endif
>+
>+	if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
>+		DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
>+			      "better performance thanks to write-combining\n");
>+	return false;
>+#else
>+	/* For architectures that don't support WC memory,
>+	 * mask out the WC flag from the BO
>+	 */
>+	if (!drm_arch_can_wc_memory())
>+		return false;
>+
>+	return true;
>+#endif
>+}
>+
> static int amdgpu_bo_do_create(struct amdgpu_device *adev,
> 			       struct amdgpu_bo_param *bp,
> 			       struct amdgpu_bo **bo_ptr)
>@@ -454,7 +486,7 @@
> 	bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
> 	if (bo == NULL)
> 		return -ENOMEM;
>-	drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
>+	drm_gem_private_object_init(adev->ddev, &bo->tbo.base, size);
> 	INIT_LIST_HEAD(&bo->shadow_list);
> 	bo->vm_bo = NULL;
> 	bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
>@@ -466,33 +498,8 @@
> 
> 	bo->flags = bp->flags;
> 
>-#ifdef CONFIG_X86_32
>-	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
>-	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
>-	 */
>-	bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>-#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
>-	/* Don't try to enable write-combining when it can't work, or things
>-	 * may be slow
>-	 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
>-	 */
>-
>-#ifndef CONFIG_COMPILE_TEST
>-#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
>-	 thanks to write-combining
>-#endif
>-
>-	if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
>-		DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
>-			      "better performance thanks to write-combining\n");
>-	bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>-#else
>-	/* For architectures that don't support WC memory,
>-	 * mask out the WC flag from the BO
>-	 */
>-	if (!drm_arch_can_wc_memory())
>+	if (!amdgpu_bo_support_uswc(bo->flags))
> 		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>-#endif
> 
> 	bo->tbo.bdev = &adev->mman.bdev;
> 	if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
>@@ -521,7 +528,7 @@
> 	    bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
> 		struct dma_fence *fence;
> 
>-		r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
>+		r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);
> 		if (unlikely(r))
> 			goto fail_unreserve;
> 
>@@ -544,7 +551,7 @@
> 
> fail_unreserve:
> 	if (!bp->resv)
>-		ww_mutex_unlock(&bo->tbo.resv->lock);
>+		reservation_object_unlock(bo->tbo.base.resv);
> 	amdgpu_bo_unref(&bo);
> 	return r;
> }
>@@ -565,7 +572,7 @@
> 	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC |
> 		AMDGPU_GEM_CREATE_SHADOW;
> 	bp.type = ttm_bo_type_kernel;
>-	bp.resv = bo->tbo.resv;
>+	bp.resv = bo->tbo.base.resv;
> 
> 	r = amdgpu_bo_do_create(adev, &bp, &bo->shadow);
> 	if (!r) {
>@@ -606,13 +613,13 @@
> 
> 	if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) {
> 		if (!bp->resv)
>-			WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
>+			WARN_ON(reservation_object_lock((*bo_ptr)->tbo.base.resv,
> 							NULL));
> 
> 		r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr);
> 
> 		if (!bp->resv)
>-			reservation_object_unlock((*bo_ptr)->tbo.resv);
>+			reservation_object_unlock((*bo_ptr)->tbo.base.resv);
> 
> 		if (r)
> 			amdgpu_bo_unref(bo_ptr);
>@@ -709,7 +716,7 @@
> 		return 0;
> 	}
> 
>-	r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
>+	r = reservation_object_wait_timeout_rcu(bo->tbo.base.resv, false, false,
> 						MAX_SCHEDULE_TIMEOUT);
> 	if (r < 0)
> 		return r;
>@@ -1087,7 +1094,7 @@
>  */
> void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
> {
>-	lockdep_assert_held(&bo->tbo.resv->lock.base);
>+	reservation_object_assert_held(bo->tbo.base.resv);
> 
> 	if (tiling_flags)
> 		*tiling_flags = bo->tiling_flags;
>@@ -1212,6 +1219,42 @@
> }
> 
> /**
>+ * amdgpu_bo_move_notify - notification about a BO being released
>+ * @bo: pointer to a buffer object
>+ *
>+ * Wipes VRAM buffers whose contents should not be leaked before the
>+ * memory is released.
>+ */
>+void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
>+{
>+	struct dma_fence *fence = NULL;
>+	struct amdgpu_bo *abo;
>+	int r;
>+
>+	if (!amdgpu_bo_is_amdgpu_bo(bo))
>+		return;
>+
>+	abo = ttm_to_amdgpu_bo(bo);
>+
>+	if (abo->kfd_bo)
>+		amdgpu_amdkfd_unreserve_memory_limit(abo);
>+
>+	if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node ||
>+	    !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE))
>+		return;
>+
>+	reservation_object_lock(bo->base.resv, NULL);
>+
>+	r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence);
>+	if (!WARN_ON(r)) {
>+		amdgpu_bo_fence(abo, fence, false);
>+		dma_fence_put(fence);
>+	}
>+
>+	reservation_object_unlock(bo->base.resv);
>+}
>+
>+/**
>  * amdgpu_bo_fault_reserve_notify - notification about a memory fault
>  * @bo: pointer to a buffer object
>  *
>@@ -1283,7 +1326,7 @@
> void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
> 		     bool shared)
> {
>-	struct reservation_object *resv = bo->tbo.resv;
>+	struct reservation_object *resv = bo->tbo.base.resv;
> 
> 	if (shared)
> 		reservation_object_add_shared_fence(resv, fence);
>@@ -1308,7 +1351,7 @@
> 	int r;
> 
> 	amdgpu_sync_create(&sync);
>-	amdgpu_sync_resv(adev, &sync, bo->tbo.resv, owner, false);
>+	amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, owner, false);
> 	r = amdgpu_sync_wait(&sync, intr);
> 	amdgpu_sync_free(&sync);
> 
>@@ -1328,7 +1371,7 @@
> u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
> {
> 	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
>-	WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
>+	WARN_ON_ONCE(!reservation_object_is_locked(bo->tbo.base.resv) &&
> 		     !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel);
> 	WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
> 	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h	2019-08-31 15:01:11.842736167 -0500
>@@ -94,7 +94,6 @@
> 	/* per VM structure for page tables and with virtual addresses */
> 	struct amdgpu_vm_bo_base	*vm_bo;
> 	/* Constant after initialization */
>-	struct drm_gem_object		gem_base;
> 	struct amdgpu_bo		*parent;
> 	struct amdgpu_bo		*shadow;
> 
>@@ -192,7 +191,7 @@
>  */
> static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
> {
>-	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
>+	return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
> }
> 
> /**
>@@ -265,6 +264,7 @@
> void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
> 			   bool evict,
> 			   struct ttm_mem_reg *new_mem);
>+void amdgpu_bo_release_notify(struct ttm_buffer_object *bo);
> int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
> void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
> 		     bool shared);
>@@ -308,5 +308,7 @@
> 					 struct seq_file *m);
> #endif
> 
>+bool amdgpu_bo_support_uswc(u64 bo_flags);
>+
> 
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c	2019-08-31 15:01:11.843736167 -0500
>@@ -325,13 +325,6 @@
> 	     (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
> 		return -EINVAL;
> 
>-	if (!amdgpu_sriov_vf(adev)) {
>-		if (is_support_sw_smu(adev))
>-			current_level = smu_get_performance_level(&adev->smu);
>-		else if (adev->powerplay.pp_funcs->get_performance_level)
>-			current_level = amdgpu_dpm_get_performance_level(adev);
>-	}
>-
> 	if (strncmp("low", buf, strlen("low")) == 0) {
> 		level = AMD_DPM_FORCED_LEVEL_LOW;
> 	} else if (strncmp("high", buf, strlen("high")) == 0) {
>@@ -355,17 +348,23 @@
> 		goto fail;
> 	}
> 
>-        if (amdgpu_sriov_vf(adev)) {
>-                if (amdgim_is_hwperf(adev) &&
>-                    adev->virt.ops->force_dpm_level) {
>-                        mutex_lock(&adev->pm.mutex);
>-                        adev->virt.ops->force_dpm_level(adev, level);
>-                        mutex_unlock(&adev->pm.mutex);
>-                        return count;
>-                } else {
>-                        return -EINVAL;
>+	/* handle sriov case here */
>+	if (amdgpu_sriov_vf(adev)) {
>+		if (amdgim_is_hwperf(adev) &&
>+		    adev->virt.ops->force_dpm_level) {
>+			mutex_lock(&adev->pm.mutex);
>+			adev->virt.ops->force_dpm_level(adev, level);
>+			mutex_unlock(&adev->pm.mutex);
>+			return count;
>+		} else {
>+			return -EINVAL;
> 		}
>-        }
>+	}
>+
>+	if (is_support_sw_smu(adev))
>+		current_level = smu_get_performance_level(&adev->smu);
>+	else if (adev->powerplay.pp_funcs->get_performance_level)
>+		current_level = amdgpu_dpm_get_performance_level(adev);
> 
> 	if (current_level == level)
> 		return count;
>@@ -746,10 +745,10 @@
> }
> 
> /**
>- * DOC: ppfeatures
>+ * DOC: pp_features
>  *
>  * The amdgpu driver provides a sysfs API for adjusting what powerplay
>- * features to be enabled. The file ppfeatures is used for this. And
>+ * features to be enabled. The file pp_features is used for this. And
>  * this is only available for Vega10 and later dGPUs.
>  *
>  * Reading back the file will show you the followings:
>@@ -761,7 +760,7 @@
>  * the corresponding bit from original ppfeature masks and input the
>  * new ppfeature masks.
>  */
>-static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
>+static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
> 		struct device_attribute *attr,
> 		const char *buf,
> 		size_t count)
>@@ -778,7 +777,7 @@
> 	pr_debug("featuremask = 0x%llx\n", featuremask);
> 
> 	if (is_support_sw_smu(adev)) {
>-		ret = smu_set_ppfeature_status(&adev->smu, featuremask);
>+		ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
> 		if (ret)
> 			return -EINVAL;
> 	} else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
>@@ -790,7 +789,7 @@
> 	return count;
> }
> 
>-static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
>+static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
> 		struct device_attribute *attr,
> 		char *buf)
> {
>@@ -798,7 +797,7 @@
> 	struct amdgpu_device *adev = ddev->dev_private;
> 
> 	if (is_support_sw_smu(adev)) {
>-		return smu_get_ppfeature_status(&adev->smu, buf);
>+		return smu_sys_get_pp_feature_mask(&adev->smu, buf);
> 	} else if (adev->powerplay.pp_funcs->get_ppfeature_status)
> 		return amdgpu_dpm_get_ppfeature_status(adev, buf);
> 
>@@ -1458,9 +1457,9 @@
> static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
> 		amdgpu_get_memory_busy_percent, NULL);
> static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
>-static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
>-		amdgpu_get_ppfeature_status,
>-		amdgpu_set_ppfeature_status);
>+static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
>+		amdgpu_get_pp_feature_status,
>+		amdgpu_set_pp_feature_status);
> static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
> 
> static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
>@@ -1625,20 +1624,16 @@
> 	     (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
> 		return -EINVAL;
> 
>-	if (is_support_sw_smu(adev)) {
>-		err = kstrtoint(buf, 10, &value);
>-		if (err)
>-			return err;
>+	err = kstrtoint(buf, 10, &value);
>+	if (err)
>+		return err;
> 
>+	if (is_support_sw_smu(adev)) {
> 		smu_set_fan_control_mode(&adev->smu, value);
> 	} else {
> 		if (!adev->powerplay.pp_funcs->set_fan_control_mode)
> 			return -EINVAL;
> 
>-		err = kstrtoint(buf, 10, &value);
>-		if (err)
>-			return err;
>-
> 		amdgpu_dpm_set_fan_control_mode(adev, value);
> 	}
> 
>@@ -2058,16 +2053,18 @@
> 		return err;
> 
> 	value = value / 1000000; /* convert to Watt */
>+
> 	if (is_support_sw_smu(adev)) {
>-		adev->smu.funcs->set_power_limit(&adev->smu, value);
>+		err = smu_set_power_limit(&adev->smu, value);
> 	} else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
> 		err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
>-		if (err)
>-			return err;
> 	} else {
>-		return -EINVAL;
>+		err = -EINVAL;
> 	}
> 
>+	if (err)
>+		return err;
>+
> 	return count;
> }
> 
>@@ -2352,7 +2349,9 @@
> 			effective_mode &= ~S_IWUSR;
> 	}
> 
>-	if ((adev->flags & AMD_IS_APU) &&
>+	if (((adev->flags & AMD_IS_APU) ||
>+	     adev->family == AMDGPU_FAMILY_SI ||	/* not implemented yet */
>+	     adev->family == AMDGPU_FAMILY_KV) &&	/* not implemented yet */
> 	    (attr == &sensor_dev_attr_power1_average.dev_attr.attr ||
> 	     attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
> 	     attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
>@@ -2376,6 +2375,12 @@
> 			return 0;
> 	}
> 
>+	if ((adev->family == AMDGPU_FAMILY_SI ||	/* not implemented yet */
>+	     adev->family == AMDGPU_FAMILY_KV) &&	/* not implemented yet */
>+	    (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
>+	     attr == &sensor_dev_attr_in0_label.dev_attr.attr))
>+		return 0;
>+
> 	/* only APUs have vddnb */
> 	if (!(adev->flags & AMD_IS_APU) &&
> 	    (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
>@@ -2831,10 +2836,12 @@
> 			DRM_ERROR("failed to create device file pp_dpm_socclk\n");
> 			return ret;
> 		}
>-		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
>-		if (ret) {
>-			DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
>-			return ret;
>+		if (adev->asic_type != CHIP_ARCTURUS) {
>+			ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
>+			if (ret) {
>+				DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
>+				return ret;
>+			}
> 		}
> 	}
> 	if (adev->asic_type >= CHIP_VEGA20) {
>@@ -2844,10 +2851,12 @@
> 			return ret;
> 		}
> 	}
>-	ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
>-	if (ret) {
>-		DRM_ERROR("failed to create device file pp_dpm_pcie\n");
>-		return ret;
>+	if (adev->asic_type != CHIP_ARCTURUS) {
>+		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
>+		if (ret) {
>+			DRM_ERROR("failed to create device file pp_dpm_pcie\n");
>+			return ret;
>+		}
> 	}
> 	ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
> 	if (ret) {
>@@ -2917,10 +2926,10 @@
> 	if ((adev->asic_type >= CHIP_VEGA10) &&
> 	    !(adev->flags & AMD_IS_APU)) {
> 		ret = device_create_file(adev->dev,
>-				&dev_attr_ppfeatures);
>+				&dev_attr_pp_features);
> 		if (ret) {
> 			DRM_ERROR("failed to create device file	"
>-					"ppfeatures\n");
>+					"pp_features\n");
> 			return ret;
> 		}
> 	}
>@@ -2951,9 +2960,11 @@
> 	device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
> 	if (adev->asic_type >= CHIP_VEGA10) {
> 		device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
>-		device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
>+		if (adev->asic_type != CHIP_ARCTURUS)
>+			device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
> 	}
>-	device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
>+	if (adev->asic_type != CHIP_ARCTURUS)
>+		device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
> 	if (adev->asic_type >= CHIP_VEGA20)
> 		device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
> 	device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
>@@ -2974,7 +2985,7 @@
> 		device_remove_file(adev->dev, &dev_attr_unique_id);
> 	if ((adev->asic_type >= CHIP_VEGA10) &&
> 	    !(adev->flags & AMD_IS_APU))
>-		device_remove_file(adev->dev, &dev_attr_ppfeatures);
>+		device_remove_file(adev->dev, &dev_attr_pp_features);
> }
> 
> void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c	2019-08-31 15:01:11.843736167 -0500
>@@ -32,6 +32,7 @@
> #include "psp_v3_1.h"
> #include "psp_v10_0.h"
> #include "psp_v11_0.h"
>+#include "psp_v12_0.h"
> 
> static void psp_set_funcs(struct amdgpu_device *adev);
> 
>@@ -53,13 +54,19 @@
> 		psp->autoload_supported = false;
> 		break;
> 	case CHIP_VEGA20:
>+	case CHIP_ARCTURUS:
> 		psp_v11_0_set_psp_funcs(psp);
> 		psp->autoload_supported = false;
> 		break;
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		psp_v11_0_set_psp_funcs(psp);
> 		psp->autoload_supported = true;
> 		break;
>+	case CHIP_RENOIR:
>+		psp_v12_0_set_psp_funcs(psp);
>+		break;
> 	default:
> 		return -EINVAL;
> 	}
>@@ -137,8 +144,7 @@
> 	memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
> 
> 	index = atomic_inc_return(&psp->fence_value);
>-	ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
>-			     fence_mc_addr, index);
>+	ret = psp_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
> 	if (ret) {
> 		atomic_dec(&psp->fence_value);
> 		mutex_unlock(&psp->mutex);
>@@ -162,8 +168,8 @@
> 		if (ucode)
> 			DRM_WARN("failed to load ucode id (%d) ",
> 				  ucode->ucode_id);
>-		DRM_WARN("psp command failed and response status is (%d)\n",
>-			  psp->cmd_buf_mem->resp.status);
>+		DRM_WARN("psp command failed and response status is (0x%X)\n",
>+			  psp->cmd_buf_mem->resp.status & GFX_CMD_STATUS_MASK);
> 		if (!timeout) {
> 			mutex_unlock(&psp->mutex);
> 			return -EINVAL;
>@@ -233,6 +239,8 @@
> {
> 	int ret;
> 	int tmr_size;
>+	void *tmr_buf;
>+	void **pptr;
> 
> 	/*
> 	 * According to HW engineer, they prefer the TMR address be "naturally
>@@ -255,9 +263,10 @@
> 		}
> 	}
> 
>+	pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
> 	ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
> 				      AMDGPU_GEM_DOMAIN_VRAM,
>-				      &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
>+				      &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
> 
> 	return ret;
> }
>@@ -831,7 +840,6 @@
> 				"XGMI: Failed to initialize XGMI session\n");
> 	}
> 
>-
> 	if (psp->adev->psp.ta_fw) {
> 		ret = psp_ras_initialize(psp);
> 		if (ret)
>@@ -852,6 +860,24 @@
> 	case AMDGPU_UCODE_ID_SDMA1:
> 		*type = GFX_FW_TYPE_SDMA1;
> 		break;
>+	case AMDGPU_UCODE_ID_SDMA2:
>+		*type = GFX_FW_TYPE_SDMA2;
>+		break;
>+	case AMDGPU_UCODE_ID_SDMA3:
>+		*type = GFX_FW_TYPE_SDMA3;
>+		break;
>+	case AMDGPU_UCODE_ID_SDMA4:
>+		*type = GFX_FW_TYPE_SDMA4;
>+		break;
>+	case AMDGPU_UCODE_ID_SDMA5:
>+		*type = GFX_FW_TYPE_SDMA5;
>+		break;
>+	case AMDGPU_UCODE_ID_SDMA6:
>+		*type = GFX_FW_TYPE_SDMA6;
>+		break;
>+	case AMDGPU_UCODE_ID_SDMA7:
>+		*type = GFX_FW_TYPE_SDMA7;
>+		break;
> 	case AMDGPU_UCODE_ID_CP_CE:
> 		*type = GFX_FW_TYPE_CP_CE;
> 		break;
>@@ -920,6 +946,60 @@
> 	return 0;
> }
> 
>+static void psp_print_fw_hdr(struct psp_context *psp,
>+			     struct amdgpu_firmware_info *ucode)
>+{
>+	struct amdgpu_device *adev = psp->adev;
>+	const struct sdma_firmware_header_v1_0 *sdma_hdr =
>+		(const struct sdma_firmware_header_v1_0 *)
>+		adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
>+	const struct gfx_firmware_header_v1_0 *ce_hdr =
>+		(const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
>+	const struct gfx_firmware_header_v1_0 *pfp_hdr =
>+		(const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
>+	const struct gfx_firmware_header_v1_0 *me_hdr =
>+		(const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
>+	const struct gfx_firmware_header_v1_0 *mec_hdr =
>+		(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
>+	const struct rlc_firmware_header_v2_0 *rlc_hdr =
>+		(const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
>+	const struct smc_firmware_header_v1_0 *smc_hdr =
>+		(const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
>+
>+	switch (ucode->ucode_id) {
>+	case AMDGPU_UCODE_ID_SDMA0:
>+	case AMDGPU_UCODE_ID_SDMA1:
>+	case AMDGPU_UCODE_ID_SDMA2:
>+	case AMDGPU_UCODE_ID_SDMA3:
>+	case AMDGPU_UCODE_ID_SDMA4:
>+	case AMDGPU_UCODE_ID_SDMA5:
>+	case AMDGPU_UCODE_ID_SDMA6:
>+	case AMDGPU_UCODE_ID_SDMA7:
>+		amdgpu_ucode_print_sdma_hdr(&sdma_hdr->header);
>+		break;
>+	case AMDGPU_UCODE_ID_CP_CE:
>+		amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
>+		break;
>+	case AMDGPU_UCODE_ID_CP_PFP:
>+		amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
>+		break;
>+	case AMDGPU_UCODE_ID_CP_ME:
>+		amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
>+		break;
>+	case AMDGPU_UCODE_ID_CP_MEC1:
>+		amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
>+		break;
>+	case AMDGPU_UCODE_ID_RLC_G:
>+		amdgpu_ucode_print_rlc_hdr(&rlc_hdr->header);
>+		break;
>+	case AMDGPU_UCODE_ID_SMC:
>+		amdgpu_ucode_print_smc_hdr(&smc_hdr->header);
>+		break;
>+	default:
>+		break;
>+	}
>+}
>+
> static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
> 				       struct psp_gfx_cmd_resp *cmd)
> {
>@@ -980,17 +1060,31 @@
> 		if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
> 		    (psp_smu_reload_quirk(psp) || psp->autoload_supported))
> 			continue;
>+
> 		if (amdgpu_sriov_vf(adev) &&
> 		   (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
> 		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
>+		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
>+		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
>+		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
>+		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
>+		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
>+		    || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
> 		    || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
> 			/*skip ucode loading in SRIOV VF */
> 			continue;
>+
> 		if (psp->autoload_supported &&
> 		    (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
> 		     ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
> 			/* skip mec JT when autoload is enabled */
> 			continue;
>+		/* Renoir only needs to load mec jump table one time */
>+		if (adev->asic_type == CHIP_RENOIR &&
>+		    ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)
>+			continue;
>+
>+		psp_print_fw_hdr(psp, ucode);
> 
> 		ret = psp_execute_np_fw_load(psp, ucode);
> 		if (ret)
>@@ -1115,6 +1209,8 @@
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 	struct psp_context *psp = &adev->psp;
>+	void *tmr_buf;
>+	void **pptr;
> 
> 	if (adev->gmc.xgmi.num_physical_nodes > 1 &&
> 	    psp->xgmi_context.initialized == 1)
>@@ -1125,7 +1221,8 @@
> 
> 	psp_ring_destroy(psp, PSP_RING_TYPE__KM);
> 
>-	amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
>+	pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
>+	amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
> 	amdgpu_bo_free_kernel(&psp->fw_pri_bo,
> 			      &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
> 	amdgpu_bo_free_kernel(&psp->fence_buf_bo,
>@@ -1328,4 +1425,13 @@
> 	.minor = 0,
> 	.rev = 0,
> 	.funcs = &psp_ip_funcs,
>+};
>+
>+const struct amdgpu_ip_block_version psp_v12_0_ip_block =
>+{
>+	.type = AMD_IP_BLOCK_TYPE_PSP,
>+	.major = 12,
>+	.minor = 0,
>+	.rev = 0,
>+	.funcs = &psp_ip_funcs,
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h	2019-08-31 15:01:11.843736167 -0500
>@@ -90,7 +90,6 @@
> 	int (*ring_destroy)(struct psp_context *psp,
> 			    enum psp_ring_type ring_type);
> 	int (*cmd_submit)(struct psp_context *psp,
>-			  struct amdgpu_firmware_info *ucode,
> 			  uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
> 			  int index);
> 	bool (*compare_sram_data)(struct psp_context *psp,
>@@ -172,7 +171,6 @@
> 	/* tmr buffer */
> 	struct amdgpu_bo		*tmr_bo;
> 	uint64_t			tmr_mc_addr;
>-	void				*tmr_buf;
> 
> 	/* asd firmware and buffer */
> 	const struct firmware		*asd_fw;
>@@ -223,8 +221,8 @@
> #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
> #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
> #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
>-#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
>-		(psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
>+#define psp_cmd_submit(psp, cmd_mc, fence_mc, index) \
>+		(psp)->funcs->cmd_submit((psp), (cmd_mc), (fence_mc), (index))
> #define psp_compare_sram_data(psp, ucode, type) \
> 		(psp)->funcs->compare_sram_data((psp), (ucode), (type))
> #define psp_init_microcode(psp) \
>@@ -270,6 +268,7 @@
> 			uint32_t field_val, uint32_t mask, bool check_changed);
> 
> extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
>+extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
> 
> int psp_gpu_reset(struct amdgpu_device *adev);
> int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c	2019-08-31 15:01:11.843736167 -0500
>@@ -30,74 +30,6 @@
> #include "amdgpu_ras.h"
> #include "amdgpu_atomfirmware.h"
> 
>-struct ras_ih_data {
>-	/* interrupt bottom half */
>-	struct work_struct ih_work;
>-	int inuse;
>-	/* IP callback */
>-	ras_ih_cb cb;
>-	/* full of entries */
>-	unsigned char *ring;
>-	unsigned int ring_size;
>-	unsigned int element_size;
>-	unsigned int aligned_element_size;
>-	unsigned int rptr;
>-	unsigned int wptr;
>-};
>-
>-struct ras_fs_data {
>-	char sysfs_name[32];
>-	char debugfs_name[32];
>-};
>-
>-struct ras_err_data {
>-	unsigned long ue_count;
>-	unsigned long ce_count;
>-};
>-
>-struct ras_err_handler_data {
>-	/* point to bad pages array */
>-	struct {
>-		unsigned long bp;
>-		struct amdgpu_bo *bo;
>-	} *bps;
>-	/* the count of entries */
>-	int count;
>-	/* the space can place new entries */
>-	int space_left;
>-	/* last reserved entry's index + 1 */
>-	int last_reserved;
>-};
>-
>-struct ras_manager {
>-	struct ras_common_if head;
>-	/* reference count */
>-	int use;
>-	/* ras block link */
>-	struct list_head node;
>-	/* the device */
>-	struct amdgpu_device *adev;
>-	/* debugfs */
>-	struct dentry *ent;
>-	/* sysfs */
>-	struct device_attribute sysfs_attr;
>-	int attr_inuse;
>-
>-	/* fs node name */
>-	struct ras_fs_data fs_data;
>-
>-	/* IH data */
>-	struct ras_ih_data ih_data;
>-
>-	struct ras_err_data err_data;
>-};
>-
>-struct ras_badpage {
>-	unsigned int bp;
>-	unsigned int size;
>-	unsigned int flags;
>-};
>-
> const char *ras_error_string[] = {
> 	"none",
> 	"parity",
>@@ -130,6 +62,9 @@
> #define AMDGPU_RAS_FLAG_INIT_NEED_RESET		2
> #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
> 
>+/* inject address is 52 bits */
>+#define	RAS_UMC_INJECT_ADDR_LIMIT	(0x1ULL << 52)
>+
> static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
> 		uint64_t offset, uint64_t size,
> 		struct amdgpu_bo **bo_ptr);
>@@ -196,6 +131,7 @@
> 	char err[9] = "ue";
> 	int op = -1;
> 	int block_id;
>+	uint32_t sub_block;
> 	u64 address, value;
> 
> 	if (*pos)
>@@ -223,17 +159,23 @@
> 			return -EINVAL;
> 
> 		data->head.block = block_id;
>-		data->head.type = memcmp("ue", err, 2) == 0 ?
>-			AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE :
>-			AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
>+		/* only ue and ce errors are supported */
>+		if (!memcmp("ue", err, 2))
>+			data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
>+		else if (!memcmp("ce", err, 2))
>+			data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
>+		else
>+			return -EINVAL;
>+
> 		data->op = op;
> 
> 		if (op == 2) {
>-			if (sscanf(str, "%*s %*s %*s %llu %llu",
>-						&address, &value) != 2)
>-				if (sscanf(str, "%*s %*s %*s 0x%llx 0x%llx",
>-							&address, &value) != 2)
>+			if (sscanf(str, "%*s %*s %*s %u %llu %llu",
>+						&sub_block, &address, &value) != 3)
>+				if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
>+							&sub_block, &address, &value) != 3)
> 					return -EINVAL;
>+			data->head.sub_block_index = sub_block;
> 			data->inject.address = address;
> 			data->inject.value = value;
> 		}
>@@ -278,7 +220,7 @@
>  * write the struct to the control node.
>  *
>  * bash:
>- * echo op block [error [address value]] > .../ras/ras_ctrl
>+ * echo op block [error [sub_blcok address value]] > .../ras/ras_ctrl
>  *	op: disable, enable, inject
>  *		disable: only block is needed
>  *		enable: block and error are needed
>@@ -288,10 +230,11 @@
>  *	error: ue, ce
>  *		ue: multi_uncorrectable
>  *		ce: single_correctable
>+ *	sub_block: sub block index, pass 0 if there is no sub block
>  *
>  * here are some examples for bash commands,
>- *	echo inject umc ue 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
>- *	echo inject umc ce 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
>+ *	echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
>+ *	echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
>  *	echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
>  *
>  * How to check the result?
>@@ -310,7 +253,6 @@
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
> 	struct ras_debug_if data;
>-	struct amdgpu_bo *bo;
> 	int ret = 0;
> 
> 	ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
>@@ -328,17 +270,14 @@
> 		ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
> 		break;
> 	case 2:
>-		ret = amdgpu_ras_reserve_vram(adev,
>-				data.inject.address, PAGE_SIZE, &bo);
>-		if (ret) {
>-			/* address was offset, now it is absolute.*/
>-			data.inject.address += adev->gmc.vram_start;
>-			if (data.inject.address > adev->gmc.vram_end)
>-				break;
>-		} else
>-			data.inject.address = amdgpu_bo_gpu_offset(bo);
>+		if ((data.inject.address >= adev->gmc.mc_vram_size) ||
>+		    (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
>+			ret = -EINVAL;
>+			break;
>+		}
>+
>+		/* data.inject.address is offset instead of absolute gpu address */
> 		ret = amdgpu_ras_error_inject(adev, &data.inject);
>-		amdgpu_ras_release_vram(adev, &bo);
> 		break;
> 	default:
> 		ret = -EINVAL;
>@@ -656,14 +595,46 @@
> 		struct ras_query_if *info)
> {
> 	struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
>+	struct ras_err_data err_data = {0, 0, 0, NULL};
> 
> 	if (!obj)
> 		return -EINVAL;
>-	/* TODO might read the register to read the count */
>+
>+	switch (info->head.block) {
>+	case AMDGPU_RAS_BLOCK__UMC:
>+		if (adev->umc.funcs->query_ras_error_count)
>+			adev->umc.funcs->query_ras_error_count(adev, &err_data);
>+		/* umc query_ras_error_address is also responsible for clearing
>+		 * error status
>+		 */
>+		if (adev->umc.funcs->query_ras_error_address)
>+			adev->umc.funcs->query_ras_error_address(adev, &err_data);
>+		break;
>+	case AMDGPU_RAS_BLOCK__GFX:
>+		if (adev->gfx.funcs->query_ras_error_count)
>+			adev->gfx.funcs->query_ras_error_count(adev, &err_data);
>+		break;
>+	case AMDGPU_RAS_BLOCK__MMHUB:
>+		if (adev->mmhub_funcs->query_ras_error_count)
>+			adev->mmhub_funcs->query_ras_error_count(adev, &err_data);
>+		break;
>+	default:
>+		break;
>+	}
>+
>+	obj->err_data.ue_count += err_data.ue_count;
>+	obj->err_data.ce_count += err_data.ce_count;
> 
> 	info->ue_count = obj->err_data.ue_count;
> 	info->ce_count = obj->err_data.ce_count;
> 
>+	if (err_data.ce_count)
>+		dev_info(adev->dev, "%ld correctable errors detected in %s block\n",
>+			 obj->err_data.ce_count, ras_block_str(info->head.block));
>+	if (err_data.ue_count)
>+		dev_info(adev->dev, "%ld uncorrectable errors detected in %s block\n",
>+			 obj->err_data.ue_count, ras_block_str(info->head.block));
>+
> 	return 0;
> }
> 
>@@ -684,13 +655,23 @@
> 	if (!obj)
> 		return -EINVAL;
> 
>-	if (block_info.block_id != TA_RAS_BLOCK__UMC) {
>+	switch (info->head.block) {
>+	case AMDGPU_RAS_BLOCK__GFX:
>+		if (adev->gfx.funcs->ras_error_inject)
>+			ret = adev->gfx.funcs->ras_error_inject(adev, info);
>+		else
>+			ret = -EINVAL;
>+		break;
>+	case AMDGPU_RAS_BLOCK__UMC:
>+	case AMDGPU_RAS_BLOCK__MMHUB:
>+		ret = psp_ras_trigger_error(&adev->psp, &block_info);
>+		break;
>+	default:
> 		DRM_INFO("%s error injection is not supported yet\n",
> 			 ras_block_str(info->head.block));
>-		return -EINVAL;
>+		ret = -EINVAL;
> 	}
> 
>-	ret = psp_ras_trigger_error(&adev->psp, &block_info);
> 	if (ret)
> 		DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n",
> 				ras_block_str(info->head.block),
>@@ -707,7 +688,7 @@
> }
> 
> /* get the total error counts on all IPs */
>-int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
>+unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
> 		bool is_ce)
> {
> 	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
>@@ -715,7 +696,7 @@
> 	struct ras_err_data data = {0, 0};
> 
> 	if (!con)
>-		return -EINVAL;
>+		return 0;
> 
> 	list_for_each_entry(obj, &con->head, node) {
> 		struct ras_query_if info = {
>@@ -723,7 +704,7 @@
> 		};
> 
> 		if (amdgpu_ras_error_query(adev, &info))
>-			return -EINVAL;
>+			return 0;
> 
> 		data.ce_count += info.ce_count;
> 		data.ue_count += info.ue_count;
>@@ -812,32 +793,8 @@
> {
> 	struct amdgpu_ras *con =
> 		container_of(attr, struct amdgpu_ras, features_attr);
>-	struct drm_device *ddev = dev_get_drvdata(dev);
>-	struct amdgpu_device *adev = ddev->dev_private;
>-	struct ras_common_if head;
>-	int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
>-	int i;
>-	ssize_t s;
>-	struct ras_manager *obj;
>-
>-	s = scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
> 
>-	for (i = 0; i < ras_block_count; i++) {
>-		head.block = i;
>-
>-		if (amdgpu_ras_is_feature_enabled(adev, &head)) {
>-			obj = amdgpu_ras_find_obj(adev, &head);
>-			s += scnprintf(&buf[s], PAGE_SIZE - s,
>-					"%s: %s\n",
>-					ras_block_str(i),
>-					ras_err_str(obj->head.type));
>-		} else
>-			s += scnprintf(&buf[s], PAGE_SIZE - s,
>-					"%s: disabled\n",
>-					ras_block_str(i));
>-	}
>-
>-	return s;
>+	return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
> }
> 
> static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev)
>@@ -1054,6 +1011,7 @@
> 	struct ras_ih_data *data = &obj->ih_data;
> 	struct amdgpu_iv_entry entry;
> 	int ret;
>+	struct ras_err_data err_data = {0, 0, 0, NULL};
> 
> 	while (data->rptr != data->wptr) {
> 		rmb();
>@@ -1068,19 +1026,19 @@
> 		 * from the callback to udpate the error type/count, etc
> 		 */
> 		if (data->cb) {
>-			ret = data->cb(obj->adev, &entry);
>+			ret = data->cb(obj->adev, &err_data, &entry);
> 			/* ue will trigger an interrupt, and in that case
> 			 * we need do a reset to recovery the whole system.
> 			 * But leave IP do that recovery, here we just dispatch
> 			 * the error.
> 			 */
>-			if (ret == AMDGPU_RAS_UE) {
>-				obj->err_data.ue_count++;
>+			if (ret == AMDGPU_RAS_SUCCESS) {
>+				/* these counts could be left as 0 if
>+				 * some blocks do not count error number
>+				 */
>+				obj->err_data.ue_count += err_data.ue_count;
>+				obj->err_data.ce_count += err_data.ce_count;
> 			}
>-			/* Might need get ce count by register, but not all IP
>-			 * saves ce count, some IP just use one bit or two bits
>-			 * to indicate ce happened.
>-			 */
> 		}
> 	}
> }
>@@ -1577,6 +1535,10 @@
> 	if (amdgpu_ras_fs_init(adev))
> 		goto fs_out;
> 
>+	/* ras init for each ras block */
>+	if (adev->umc.funcs->ras_init)
>+		adev->umc.funcs->ras_init(adev);
>+
> 	DRM_INFO("RAS INFO: ras initialized successfully, "
> 			"hardware ability[%x] ras_mask[%x]\n",
> 			con->hw_supported, con->supported);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c	2019-08-31 15:01:11.843736167 -0500
>@@ -0,0 +1,493 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include "amdgpu_ras_eeprom.h"
>+#include "amdgpu.h"
>+#include "amdgpu_ras.h"
>+#include <linux/bits.h>
>+#include "smu_v11_0_i2c.h"
>+
>+#define EEPROM_I2C_TARGET_ADDR 0xA0
>+
>+/*
>+ * The 2 macros bellow represent the actual size in bytes that
>+ * those entities occupy in the EEPROM memory.
>+ * EEPROM_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
>+ * uses uint64 to store 6b fields such as retired_page.
>+ */
>+#define EEPROM_TABLE_HEADER_SIZE 20
>+#define EEPROM_TABLE_RECORD_SIZE 24
>+
>+#define EEPROM_ADDRESS_SIZE 0x2
>+
>+/* Table hdr is 'AMDR' */
>+#define EEPROM_TABLE_HDR_VAL 0x414d4452
>+#define EEPROM_TABLE_VER 0x00010000
>+
>+/* Assume 2 Mbit size */
>+#define EEPROM_SIZE_BYTES 256000
>+#define EEPROM_PAGE__SIZE_BYTES 256
>+#define EEPROM_HDR_START 0
>+#define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE)
>+#define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES - EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE)
>+#define EEPROM_ADDR_MSB_MASK GENMASK(17, 8)
>+
>+#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev
>+
>+static void __encode_table_header_to_buff(struct amdgpu_ras_eeprom_table_header *hdr,
>+					  unsigned char *buff)
>+{
>+	uint32_t *pp = (uint32_t *) buff;
>+
>+	pp[0] = cpu_to_le32(hdr->header);
>+	pp[1] = cpu_to_le32(hdr->version);
>+	pp[2] = cpu_to_le32(hdr->first_rec_offset);
>+	pp[3] = cpu_to_le32(hdr->tbl_size);
>+	pp[4] = cpu_to_le32(hdr->checksum);
>+}
>+
>+static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_header *hdr,
>+					  unsigned char *buff)
>+{
>+	uint32_t *pp = (uint32_t *)buff;
>+
>+	hdr->header 	      = le32_to_cpu(pp[0]);
>+	hdr->version 	      = le32_to_cpu(pp[1]);
>+	hdr->first_rec_offset = le32_to_cpu(pp[2]);
>+	hdr->tbl_size 	      = le32_to_cpu(pp[3]);
>+	hdr->checksum 	      = le32_to_cpu(pp[4]);
>+}
>+
>+static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
>+				 unsigned char *buff)
>+{
>+	int ret = 0;
>+	struct i2c_msg msg = {
>+			.addr	= EEPROM_I2C_TARGET_ADDR,
>+			.flags	= 0,
>+			.len	= EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
>+			.buf	= buff,
>+	};
>+
>+
>+	*(uint16_t *)buff = EEPROM_HDR_START;
>+	__encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);
>+
>+	ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
>+	if (ret < 1)
>+		DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret);
>+
>+	return ret;
>+}
>+
>+static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control);
>+
>+int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
>+{
>+	int ret = 0;
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+	unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
>+	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
>+	struct i2c_msg msg = {
>+			.addr	= EEPROM_I2C_TARGET_ADDR,
>+			.flags	= I2C_M_RD,
>+			.len	= EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
>+			.buf	= buff,
>+	};
>+
>+	mutex_init(&control->tbl_mutex);
>+
>+	switch (adev->asic_type) {
>+	case CHIP_VEGA20:
>+		ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);
>+		break;
>+
>+	default:
>+		return 0;
>+	}
>+
>+	if (ret) {
>+		DRM_ERROR("Failed to init I2C controller, ret:%d", ret);
>+		return ret;
>+	}
>+
>+	/* Read/Create table header from EEPROM address 0 */
>+	ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
>+	if (ret < 1) {
>+		DRM_ERROR("Failed to read EEPROM table header, ret:%d", ret);
>+		return ret;
>+	}
>+
>+	__decode_table_header_from_buff(hdr, &buff[2]);
>+
>+	if (hdr->header == EEPROM_TABLE_HDR_VAL) {
>+		control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /
>+				    EEPROM_TABLE_RECORD_SIZE;
>+		DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
>+				 control->num_recs);
>+
>+	} else {
>+		DRM_INFO("Creating new EEPROM table");
>+
>+		hdr->header = EEPROM_TABLE_HDR_VAL;
>+		hdr->version = EEPROM_TABLE_VER;
>+		hdr->first_rec_offset = EEPROM_RECORD_START;
>+		hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE;
>+
>+		adev->psp.ras.ras->eeprom_control.tbl_byte_sum =
>+				__calc_hdr_byte_sum(&adev->psp.ras.ras->eeprom_control);
>+		ret = __update_table_header(control, buff);
>+	}
>+
>+	/* Start inserting records from here */
>+	adev->psp.ras.ras->eeprom_control.next_addr = EEPROM_RECORD_START;
>+
>+	return ret == 1 ? 0 : -EIO;
>+}
>+
>+void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+
>+	switch (adev->asic_type) {
>+	case CHIP_VEGA20:
>+		smu_v11_0_i2c_eeprom_control_fini(&control->eeprom_accessor);
>+		break;
>+
>+	default:
>+		return;
>+	}
>+}
>+
>+static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control *control,
>+					  struct eeprom_table_record *record,
>+					  unsigned char *buff)
>+{
>+	__le64 tmp = 0;
>+	int i = 0;
>+
>+	/* Next are all record fields according to EEPROM page spec in LE foramt */
>+	buff[i++] = record->err_type;
>+
>+	buff[i++] = record->bank;
>+
>+	tmp = cpu_to_le64(record->ts);
>+	memcpy(buff + i, &tmp, 8);
>+	i += 8;
>+
>+	tmp = cpu_to_le64((record->offset & 0xffffffffffff));
>+	memcpy(buff + i, &tmp, 6);
>+	i += 6;
>+
>+	buff[i++] = record->mem_channel;
>+	buff[i++] = record->mcumc_id;
>+
>+	tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
>+	memcpy(buff + i, &tmp, 6);
>+}
>+
>+static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *control,
>+					    struct eeprom_table_record *record,
>+					    unsigned char *buff)
>+{
>+	__le64 tmp = 0;
>+	int i =  0;
>+
>+	/* Next are all record fields according to EEPROM page spec in LE foramt */
>+	record->err_type = buff[i++];
>+
>+	record->bank = buff[i++];
>+
>+	memcpy(&tmp, buff + i, 8);
>+	record->ts = le64_to_cpu(tmp);
>+	i += 8;
>+
>+	memcpy(&tmp, buff + i, 6);
>+	record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
>+	i += 6;
>+
>+	buff[i++] = record->mem_channel;
>+	buff[i++] = record->mcumc_id;
>+
>+	memcpy(&tmp, buff + i,  6);
>+	record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
>+}
>+
>+/*
>+ * When reaching end of EEPROM memory jump back to 0 record address
>+ * When next record access will go beyond EEPROM page boundary modify bits A17/A8
>+ * in I2C selector to go to next page
>+ */
>+static uint32_t __correct_eeprom_dest_address(uint32_t curr_address)
>+{
>+	uint32_t next_address = curr_address + EEPROM_TABLE_RECORD_SIZE;
>+
>+	/* When all EEPROM memory used jump back to 0 address */
>+	if (next_address > EEPROM_SIZE_BYTES) {
>+		DRM_INFO("Reached end of EEPROM memory, jumping to 0 "
>+			 "and overriding old record");
>+		return EEPROM_RECORD_START;
>+	}
>+
>+	/*
>+	 * To check if we overflow page boundary  compare next address with
>+	 * current and see if bits 17/8 of the EEPROM address will change
>+	 * If they do start from the next 256b page
>+	 *
>+	 * https://www.st.com/resource/en/datasheet/m24m02-dr.pdf sec. 5.1.2
>+	 */
>+	if ((curr_address & EEPROM_ADDR_MSB_MASK) != (next_address & EEPROM_ADDR_MSB_MASK)) {
>+		DRM_DEBUG_DRIVER("Reached end of EEPROM memory page, jumping to next: %lx",
>+				(next_address & EEPROM_ADDR_MSB_MASK));
>+
>+		return  (next_address & EEPROM_ADDR_MSB_MASK);
>+	}
>+
>+	return curr_address;
>+}
>+
>+
>+static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)
>+{
>+	int i;
>+	uint32_t tbl_sum = 0;
>+
>+	/* Header checksum, skip checksum field in the calculation */
>+	for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)
>+		tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);
>+
>+	return tbl_sum;
>+}
>+
>+static uint32_t  __calc_recs_byte_sum(struct eeprom_table_record *records,
>+				      int num)
>+{
>+	int i, j;
>+	uint32_t tbl_sum = 0;
>+
>+	/* Records checksum */
>+	for (i = 0; i < num; i++) {
>+		struct eeprom_table_record *record = &records[i];
>+
>+		for (j = 0; j < sizeof(*record); j++) {
>+			tbl_sum += *(((unsigned char *)record) + j);
>+		}
>+	}
>+
>+	return tbl_sum;
>+}
>+
>+static inline uint32_t  __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,
>+				  struct eeprom_table_record *records, int num)
>+{
>+	return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);
>+}
>+
>+/* Checksum = 256 -((sum of all table entries) mod 256)Â */
>+static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
>+				  struct eeprom_table_record *records, int num,
>+				  uint32_t old_hdr_byte_sum)
>+{
>+	/*
>+	 * This will update the table sum with new records.
>+	 *
>+	 * TODO: What happens when the EEPROM table is to be wrapped around
>+	 * and old records from start will get overridden.
>+	 */
>+
>+	/* need to recalculate updated header byte sum */
>+	control->tbl_byte_sum -= old_hdr_byte_sum;
>+	control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);
>+
>+	control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);
>+}
>+
>+/* table sum mod 256 + checksum must equals 256 */
>+static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
>+			    struct eeprom_table_record *records, int num)
>+{
>+	control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);
>+
>+	if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {
>+		DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);
>+		return false;
>+	}
>+
>+	return true;
>+}
>+
>+int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
>+					    struct eeprom_table_record *records,
>+					    bool write,
>+					    int num)
>+{
>+	int i, ret = 0;
>+	struct i2c_msg *msgs;
>+	unsigned char *buffs;
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+
>+	if (adev->asic_type != CHIP_VEGA20)
>+		return 0;
>+
>+	buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE,
>+			 GFP_KERNEL);
>+	if (!buffs)
>+		return -ENOMEM;
>+
>+	mutex_lock(&control->tbl_mutex);
>+
>+	msgs = kcalloc(num, sizeof(*msgs), GFP_KERNEL);
>+	if (!msgs) {
>+		ret = -ENOMEM;
>+		goto free_buff;
>+	}
>+
>+	/* In case of overflow just start from beginning to not lose newest records */
>+	if (write && (control->next_addr + EEPROM_TABLE_RECORD_SIZE * num > EEPROM_SIZE_BYTES))
>+		control->next_addr = EEPROM_RECORD_START;
>+
>+
>+	/*
>+	 * TODO Currently makes EEPROM writes for each record, this creates
>+	 * internal fragmentation. Optimized the code to do full page write of
>+	 * 256b
>+	 */
>+	for (i = 0; i < num; i++) {
>+		unsigned char *buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
>+		struct eeprom_table_record *record = &records[i];
>+		struct i2c_msg *msg = &msgs[i];
>+
>+		control->next_addr = __correct_eeprom_dest_address(control->next_addr);
>+
>+		/*
>+		 * Update bits 16,17 of EEPROM address in I2C address by setting them
>+		 * to bits 1,2 of Device address byte
>+		 */
>+		msg->addr = EEPROM_I2C_TARGET_ADDR |
>+			       ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
>+		msg->flags	= write ? 0 : I2C_M_RD;
>+		msg->len	= EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE;
>+		msg->buf	= buff;
>+
>+		/* Insert the EEPROM dest addess, bits 0-15 */
>+		buff[0] = ((control->next_addr >> 8) & 0xff);
>+		buff[1] = (control->next_addr & 0xff);
>+
>+		/* EEPROM table content is stored in LE format */
>+		if (write)
>+			__encode_table_record_to_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
>+
>+		/*
>+		 * The destination EEPROM address might need to be corrected to account
>+		 * for page or entire memory wrapping
>+		 */
>+		control->next_addr += EEPROM_TABLE_RECORD_SIZE;
>+	}
>+
>+	ret = i2c_transfer(&control->eeprom_accessor, msgs, num);
>+	if (ret < 1) {
>+		DRM_ERROR("Failed to process EEPROM table records, ret:%d", ret);
>+
>+		/* TODO Restore prev next EEPROM address ? */
>+		goto free_msgs;
>+	}
>+
>+
>+	if (!write) {
>+		for (i = 0; i < num; i++) {
>+			unsigned char *buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
>+			struct eeprom_table_record *record = &records[i];
>+
>+			__decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
>+		}
>+	}
>+
>+	if (write) {
>+		uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control);
>+
>+		/*
>+		 * Update table header with size and CRC and account for table
>+		 * wrap around where the assumption is that we treat it as empty
>+		 * table
>+		 *
>+		 * TODO - Check the assumption is correct
>+		 */
>+		control->num_recs += num;
>+		control->num_recs %= EEPROM_MAX_RECORD_NUM;
>+		control->tbl_hdr.tbl_size += EEPROM_TABLE_RECORD_SIZE * num;
>+		if (control->tbl_hdr.tbl_size > EEPROM_SIZE_BYTES)
>+			control->tbl_hdr.tbl_size = EEPROM_TABLE_HEADER_SIZE +
>+			control->num_recs * EEPROM_TABLE_RECORD_SIZE;
>+
>+		__update_tbl_checksum(control, records, num, old_hdr_byte_sum);
>+
>+		__update_table_header(control, buffs);
>+	} else if (!__validate_tbl_checksum(control, records, num)) {
>+		DRM_WARN("EEPROM Table checksum mismatch!");
>+		/* TODO Uncomment when EEPROM read/write is relliable */
>+		/* ret = -EIO; */
>+	}
>+
>+free_msgs:
>+	kfree(msgs);
>+
>+free_buff:
>+	kfree(buffs);
>+
>+	mutex_unlock(&control->tbl_mutex);
>+
>+	return ret == num ? 0 : -EIO;
>+}
>+
>+/* Used for testing if bugs encountered */
>+#if 0
>+void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control)
>+{
>+	int i;
>+	struct eeprom_table_record *recs = kcalloc(1, sizeof(*recs), GFP_KERNEL);
>+
>+	if (!recs)
>+		return;
>+
>+	for (i = 0; i < 1 ; i++) {
>+		recs[i].address = 0xdeadbeef;
>+		recs[i].retired_page = i;
>+	}
>+
>+	if (!amdgpu_ras_eeprom_process_recods(control, recs, true, 1)) {
>+
>+		memset(recs, 0, sizeof(*recs) * 1);
>+
>+		control->next_addr = EEPROM_RECORD_START;
>+
>+		if (!amdgpu_ras_eeprom_process_recods(control, recs, false, 1)) {
>+			for (i = 0; i < 1; i++)
>+				DRM_INFO("rec.address :0x%llx, rec.retired_page :%llu",
>+					 recs[i].address, recs[i].retired_page);
>+		} else
>+			DRM_ERROR("Failed in reading from table");
>+
>+	} else
>+		DRM_ERROR("Failed in writing to table");
>+}
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h	2019-08-31 15:01:11.843736167 -0500
>@@ -0,0 +1,90 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef _AMDGPU_RAS_EEPROM_H
>+#define _AMDGPU_RAS_EEPROM_H
>+
>+#include <linux/i2c.h>
>+
>+struct amdgpu_device;
>+
>+enum amdgpu_ras_eeprom_err_type{
>+	AMDGPU_RAS_EEPROM_ERR_PLACE_HOLDER,
>+	AMDGPU_RAS_EEPROM_ERR_RECOVERABLE,
>+	AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE
>+};
>+
>+struct amdgpu_ras_eeprom_table_header {
>+	uint32_t header;
>+	uint32_t version;
>+	uint32_t first_rec_offset;
>+	uint32_t tbl_size;
>+	uint32_t checksum;
>+}__attribute__((__packed__));
>+
>+struct amdgpu_ras_eeprom_control {
>+	struct amdgpu_ras_eeprom_table_header tbl_hdr;
>+	struct i2c_adapter eeprom_accessor;
>+	uint32_t next_addr;
>+	unsigned int num_recs;
>+	struct mutex tbl_mutex;
>+	bool bus_locked;
>+	uint32_t tbl_byte_sum;
>+};
>+
>+/*
>+ * Represents single table record. Packed to be easily serialized into byte
>+ * stream.
>+ */
>+struct eeprom_table_record {
>+
>+	union {
>+		uint64_t address;
>+		uint64_t offset;
>+	};
>+
>+	uint64_t retired_page;
>+	uint64_t ts;
>+
>+	enum amdgpu_ras_eeprom_err_type err_type;
>+
>+	union {
>+		unsigned char bank;
>+		unsigned char cu;
>+	};
>+
>+	unsigned char mem_channel;
>+	unsigned char mcumc_id;
>+}__attribute__((__packed__));
>+
>+int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control);
>+void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control);
>+
>+int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
>+					    struct eeprom_table_record *records,
>+					    bool write,
>+					    int num);
>+
>+void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control);
>+
>+#endif // _AMDGPU_RAS_EEPROM_H
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h	2019-08-31 15:01:11.843736167 -0500
>@@ -29,6 +29,7 @@
> #include "amdgpu.h"
> #include "amdgpu_psp.h"
> #include "ta_ras_if.h"
>+#include "amdgpu_ras_eeprom.h"
> 
> enum amdgpu_ras_block {
> 	AMDGPU_RAS_BLOCK__UMC = 0,
>@@ -52,6 +53,236 @@
> #define AMDGPU_RAS_BLOCK_COUNT	AMDGPU_RAS_BLOCK__LAST
> #define AMDGPU_RAS_BLOCK_MASK	((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
> 
>+enum amdgpu_ras_gfx_subblock {
>+	/* CPC */
>+	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
>+	AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
>+		AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
>+	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
>+	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
>+	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
>+	AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
>+	AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
>+	AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
>+	AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
>+		AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
>+	/* CPF */
>+	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
>+		AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
>+	AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
>+	AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
>+	/* CPG */
>+	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
>+		AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
>+	AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
>+	AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
>+	/* GDS */
>+	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
>+	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
>+	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
>+	AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
>+	AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
>+		AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
>+	/* SPI */
>+	AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
>+	/* SQ */
>+	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
>+	AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
>+	AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
>+	AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
>+	/* SQC (3 ranges) */
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
>+	/* SQC range 0 */
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
>+		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
>+		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
>+		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
>+	/* SQC range 1 */
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
>+		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
>+		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
>+	/* SQC range 2 */
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
>+		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
>+		AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
>+		AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
>+	/* TA */
>+	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
>+		AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
>+	AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
>+	AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
>+	AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
>+	AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
>+	/* TCA */
>+	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
>+		AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
>+		AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
>+	/* TCC (5 sub-ranges) */
>+	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
>+	/* TCC range 0 */
>+	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
>+		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
>+		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
>+		AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
>+	/* TCC range 1 */
>+	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
>+		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
>+		AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
>+	/* TCC range 2 */
>+	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
>+		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
>+		AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
>+	/* TCC range 3 */
>+	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
>+		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
>+		AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
>+	/* TCC range 4 */
>+	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
>+		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
>+		AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
>+	AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
>+		AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
>+	/* TCI */
>+	AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
>+	/* TCP */
>+	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
>+		AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
>+	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
>+	AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
>+	AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
>+		AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
>+	/* TD */
>+	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
>+		AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
>+	AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
>+	AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
>+	/* EA (3 sub-ranges) */
>+	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
>+	/* EA range 0 */
>+	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
>+		AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
>+	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
>+		AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
>+	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
>+		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
>+	/* EA range 1 */
>+	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
>+	AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
>+		AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
>+	AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
>+		AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
>+	/* EA range 2 */
>+	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
>+	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
>+		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
>+	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
>+		AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
>+	AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
>+		AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
>+	/* UTC VM L2 bank */
>+	AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
>+	/* UTC VM walker */
>+	AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
>+	/* UTC ATC L2 2MB cache */
>+	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
>+	/* UTC ATC L2 4KB cache */
>+	AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
>+	AMDGPU_RAS_BLOCK__GFX_MAX
>+};
>+
> enum amdgpu_ras_error_type {
> 	AMDGPU_RAS_ERROR__NONE							= 0,
> 	AMDGPU_RAS_ERROR__PARITY						= 1,
>@@ -76,9 +307,6 @@
> 	char name[32];
> };
> 
>-typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
>-		struct amdgpu_iv_entry *entry);
>-
> struct amdgpu_ras {
> 	/* ras infrastructure */
> 	/* for ras itself. */
>@@ -106,10 +334,85 @@
> 	struct mutex recovery_lock;
> 
> 	uint32_t flags;
>+
>+	struct amdgpu_ras_eeprom_control eeprom_control;
> };
> 
>-/* interfaces for IP */
>+struct ras_fs_data {
>+	char sysfs_name[32];
>+	char debugfs_name[32];
>+};
>+
>+struct ras_err_data {
>+	unsigned long ue_count;
>+	unsigned long ce_count;
>+	unsigned long err_addr_cnt;
>+	uint64_t *err_addr;
>+};
> 
>+struct ras_err_handler_data {
>+	/* point to bad pages array */
>+	struct {
>+		unsigned long bp;
>+		struct amdgpu_bo *bo;
>+	} *bps;
>+	/* the count of entries */
>+	int count;
>+	/* the space can place new entries */
>+	int space_left;
>+	/* last reserved entry's index + 1 */
>+	int last_reserved;
>+};
>+
>+typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
>+		struct ras_err_data *err_data,
>+		struct amdgpu_iv_entry *entry);
>+
>+struct ras_ih_data {
>+	/* interrupt bottom half */
>+	struct work_struct ih_work;
>+	int inuse;
>+	/* IP callback */
>+	ras_ih_cb cb;
>+	/* full of entries */
>+	unsigned char *ring;
>+	unsigned int ring_size;
>+	unsigned int element_size;
>+	unsigned int aligned_element_size;
>+	unsigned int rptr;
>+	unsigned int wptr;
>+};
>+
>+struct ras_manager {
>+	struct ras_common_if head;
>+	/* reference count */
>+	int use;
>+	/* ras block link */
>+	struct list_head node;
>+	/* the device */
>+	struct amdgpu_device *adev;
>+	/* debugfs */
>+	struct dentry *ent;
>+	/* sysfs */
>+	struct device_attribute sysfs_attr;
>+	int attr_inuse;
>+
>+	/* fs node name */
>+	struct ras_fs_data fs_data;
>+
>+	/* IH data */
>+	struct ras_ih_data ih_data;
>+
>+	struct ras_err_data err_data;
>+};
>+
>+struct ras_badpage {
>+	unsigned int bp;
>+	unsigned int size;
>+	unsigned int flags;
>+};
>+
>+/* interfaces for IP */
> struct ras_fs_if {
> 	struct ras_common_if head;
> 	char sysfs_name[32];
>@@ -184,7 +487,7 @@
> void amdgpu_ras_resume(struct amdgpu_device *adev);
> void amdgpu_ras_suspend(struct amdgpu_device *adev);
> 
>-int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
>+unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
> 		bool is_ce);
> 
> /* error handling functions */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h	2019-08-31 15:01:11.843736167 -0500
>@@ -29,7 +29,7 @@
> #include <drm/drm_print.h>
> 
> /* max number of rings */
>-#define AMDGPU_MAX_RINGS		24
>+#define AMDGPU_MAX_RINGS		28
> #define AMDGPU_MAX_GFX_RINGS		2
> #define AMDGPU_MAX_COMPUTE_RINGS	8
> #define AMDGPU_MAX_VCE_RINGS		3
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h	2019-08-31 15:01:11.843736167 -0500
>@@ -25,11 +25,17 @@
> #define __AMDGPU_SDMA_H__
> 
> /* max number of IP instances */
>-#define AMDGPU_MAX_SDMA_INSTANCES		2
>+#define AMDGPU_MAX_SDMA_INSTANCES		8
> 
> enum amdgpu_sdma_irq {
> 	AMDGPU_SDMA_IRQ_INSTANCE0  = 0,
> 	AMDGPU_SDMA_IRQ_INSTANCE1,
>+	AMDGPU_SDMA_IRQ_INSTANCE2,
>+	AMDGPU_SDMA_IRQ_INSTANCE3,
>+	AMDGPU_SDMA_IRQ_INSTANCE4,
>+	AMDGPU_SDMA_IRQ_INSTANCE5,
>+	AMDGPU_SDMA_IRQ_INSTANCE6,
>+	AMDGPU_SDMA_IRQ_INSTANCE7,
> 	AMDGPU_SDMA_IRQ_LAST
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c	2019-08-31 15:01:11.844736167 -0500
>@@ -227,7 +227,7 @@
> 
> 	if (amdgpu_ttm_tt_get_usermm(bo->ttm))
> 		return -EPERM;
>-	return drm_vma_node_verify_access(&abo->gem_base.vma_node,
>+	return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
> 					  filp->private_data);
> }
> 
>@@ -440,10 +440,26 @@
> 
> 	r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
> 				       new_mem->num_pages << PAGE_SHIFT,
>-				       bo->resv, &fence);
>+				       bo->base.resv, &fence);
> 	if (r)
> 		goto error;
> 
>+	/* clear the space being freed */
>+	if (old_mem->mem_type == TTM_PL_VRAM &&
>+	    (ttm_to_amdgpu_bo(bo)->flags &
>+	     AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
>+		struct dma_fence *wipe_fence = NULL;
>+
>+		r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
>+				       NULL, &wipe_fence);
>+		if (r) {
>+			goto error;
>+		} else if (wipe_fence) {
>+			dma_fence_put(fence);
>+			fence = wipe_fence;
>+		}
>+	}
>+
> 	/* Always block for VM page tables before committing the new location */
> 	if (bo->type == ttm_bo_type_kernel)
> 		r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
>@@ -1478,18 +1494,18 @@
> 	 * cleanly handle page faults.
> 	 */
> 	if (bo->type == ttm_bo_type_kernel &&
>-	    !reservation_object_test_signaled_rcu(bo->resv, true))
>+	    !reservation_object_test_signaled_rcu(bo->base.resv, true))
> 		return false;
> 
> 	/* If bo is a KFD BO, check if the bo belongs to the current process.
> 	 * If true, then return false as any KFD process needs all its BOs to
> 	 * be resident to run successfully
> 	 */
>-	flist = reservation_object_get_list(bo->resv);
>+	flist = reservation_object_get_list(bo->base.resv);
> 	if (flist) {
> 		for (i = 0; i < flist->shared_count; ++i) {
> 			f = rcu_dereference_protected(flist->shared[i],
>-				reservation_object_held(bo->resv));
>+				reservation_object_held(bo->base.resv));
> 			if (amdkfd_fence_check_mm(f, current->mm))
> 				return false;
> 		}
>@@ -1599,6 +1615,7 @@
> 	.move = &amdgpu_bo_move,
> 	.verify_access = &amdgpu_verify_access,
> 	.move_notify = &amdgpu_bo_move_notify,
>+	.release_notify = &amdgpu_bo_release_notify,
> 	.fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
> 	.io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
> 	.io_mem_free = &amdgpu_ttm_io_mem_free,
>@@ -1721,6 +1738,7 @@
> 	uint64_t gtt_size;
> 	int r;
> 	u64 vis_vram_limit;
>+	void *stolen_vga_buf;
> 
> 	mutex_init(&adev->mman.gtt_window_lock);
> 
>@@ -1728,7 +1746,7 @@
> 	r = ttm_bo_device_init(&adev->mman.bdev,
> 			       &amdgpu_bo_driver,
> 			       adev->ddev->anon_inode->i_mapping,
>-			       adev->need_dma32);
>+			       dma_addressing_limited(adev->dev));
> 	if (r) {
> 		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
> 		return r;
>@@ -1775,7 +1793,7 @@
> 	r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
> 				    AMDGPU_GEM_DOMAIN_VRAM,
> 				    &adev->stolen_vga_memory,
>-				    NULL, NULL);
>+				    NULL, &stolen_vga_buf);
> 	if (r)
> 		return r;
> 	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
>@@ -1839,8 +1857,9 @@
>  */
> void amdgpu_ttm_late_init(struct amdgpu_device *adev)
> {
>+	void *stolen_vga_buf;
> 	/* return the VGA stolen memory (if any) back to VRAM */
>-	amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
>+	amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
> }
> 
> /**
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h	2019-08-31 15:01:11.844736167 -0500
>@@ -38,6 +38,8 @@
> #define AMDGPU_GTT_MAX_TRANSFER_SIZE	512
> #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS	2
> 
>+#define AMDGPU_POISON	0xd0bed0be
>+
> struct amdgpu_mman {
> 	struct ttm_bo_device		bdev;
> 	bool				mem_global_referenced;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c	2019-08-31 15:01:11.844736167 -0500
>@@ -83,8 +83,8 @@
> 		const struct smc_firmware_header_v2_0 *v2_hdr =
> 			container_of(v1_hdr, struct smc_firmware_header_v2_0, v1_0);
> 
>-		DRM_INFO("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes));
>-		DRM_INFO("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes));
>+		DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes));
>+		DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes));
> 	} else {
> 		DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
> 	}
>@@ -269,6 +269,16 @@
> 			DRM_DEBUG("kdb_size_bytes: %u\n",
> 				  le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes));
> 		}
>+		if (version_minor == 2) {
>+			const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
>+				container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
>+			DRM_DEBUG("kdb_header_version: %u\n",
>+				  le32_to_cpu(psp_hdr_v1_2->kdb_header_version));
>+			DRM_DEBUG("kdb_offset_bytes: %u\n",
>+				  le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes));
>+			DRM_DEBUG("kdb_size_bytes: %u\n",
>+				  le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes));
>+		}
> 	} else {
> 		DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
> 			  version_major, version_minor);
>@@ -350,11 +360,17 @@
> 	case CHIP_RAVEN:
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
>+	case CHIP_RENOIR:
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		if (!load_type)
> 			return AMDGPU_FW_LOAD_DIRECT;
> 		else
> 			return AMDGPU_FW_LOAD_PSP;
>+	case CHIP_ARCTURUS:
>+		return AMDGPU_FW_LOAD_DIRECT;
>+
> 	default:
> 		DRM_ERROR("Unknown firmware load type\n");
> 	}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h	2019-08-31 15:01:11.844736167 -0500
>@@ -90,6 +90,15 @@
> 	uint32_t kdb_size_bytes;
> };
> 
>+/* version_major=1, version_minor=2 */
>+struct psp_firmware_header_v1_2 {
>+	struct psp_firmware_header_v1_0 v1_0;
>+	uint32_t reserve[3];
>+	uint32_t kdb_header_version;
>+	uint32_t kdb_offset_bytes;
>+	uint32_t kdb_size_bytes;
>+};
>+
> /* version_major=1, version_minor=0 */
> struct ta_firmware_header_v1_0 {
> 	struct common_firmware_header header;
>@@ -262,6 +271,12 @@
> enum AMDGPU_UCODE_ID {
> 	AMDGPU_UCODE_ID_SDMA0 = 0,
> 	AMDGPU_UCODE_ID_SDMA1,
>+	AMDGPU_UCODE_ID_SDMA2,
>+	AMDGPU_UCODE_ID_SDMA3,
>+	AMDGPU_UCODE_ID_SDMA4,
>+	AMDGPU_UCODE_ID_SDMA5,
>+	AMDGPU_UCODE_ID_SDMA6,
>+	AMDGPU_UCODE_ID_SDMA7,
> 	AMDGPU_UCODE_ID_CP_CE,
> 	AMDGPU_UCODE_ID_CP_PFP,
> 	AMDGPU_UCODE_ID_CP_ME,
>@@ -281,6 +296,7 @@
> 	AMDGPU_UCODE_ID_UVD1,
> 	AMDGPU_UCODE_ID_VCE,
> 	AMDGPU_UCODE_ID_VCN,
>+	AMDGPU_UCODE_ID_VCN1,
> 	AMDGPU_UCODE_ID_DMCU_ERAM,
> 	AMDGPU_UCODE_ID_DMCU_INTV,
> 	AMDGPU_UCODE_ID_VCN0_RAM,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h	2019-08-31 15:01:11.844736167 -0500
>@@ -0,0 +1,82 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef __AMDGPU_UMC_H__
>+#define __AMDGPU_UMC_H__
>+
>+/* implement 64 bits REG operations via 32 bits interface */
>+#define RREG64_UMC(reg)	(RREG32(reg) | \
>+				((uint64_t)RREG32((reg) + 1) << 32))
>+#define WREG64_UMC(reg, v)	\
>+	do {	\
>+		WREG32((reg), lower_32_bits(v));	\
>+		WREG32((reg) + 1, upper_32_bits(v));	\
>+	} while (0)
>+
>+/*
>+ * void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data,
>+ *				uint32_t umc_reg_offset, uint32_t channel_index)
>+ */
>+#define amdgpu_umc_for_each_channel(func)	\
>+	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;	\
>+	uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index;	\
>+	for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; umc_inst++) {	\
>+		/* enable the index mode to query eror count per channel */	\
>+		adev->umc.funcs->enable_umc_index_mode(adev, umc_inst);	\
>+		for (channel_inst = 0;	\
>+			channel_inst < adev->umc.channel_inst_num;	\
>+			channel_inst++) {	\
>+			/* calc the register offset according to channel instance */	\
>+			umc_reg_offset = adev->umc.channel_offs * channel_inst;	\
>+			/* get channel index of interleaved memory */	\
>+			channel_index = adev->umc.channel_idx_tbl[	\
>+				umc_inst * adev->umc.channel_inst_num + channel_inst];	\
>+			(func)(adev, err_data, umc_reg_offset, channel_index);	\
>+		}	\
>+	}	\
>+	adev->umc.funcs->disable_umc_index_mode(adev);
>+
>+struct amdgpu_umc_funcs {
>+	void (*ras_init)(struct amdgpu_device *adev);
>+	void (*query_ras_error_count)(struct amdgpu_device *adev,
>+					void *ras_error_status);
>+	void (*query_ras_error_address)(struct amdgpu_device *adev,
>+					void *ras_error_status);
>+	void (*enable_umc_index_mode)(struct amdgpu_device *adev,
>+					uint32_t umc_instance);
>+	void (*disable_umc_index_mode)(struct amdgpu_device *adev);
>+};
>+
>+struct amdgpu_umc {
>+	/* max error count in one ras query call */
>+	uint32_t max_ras_err_cnt_per_query;
>+	/* number of umc channel instance with memory map register access */
>+	uint32_t channel_inst_num;
>+	/* number of umc instance with memory map register access */
>+	uint32_t umc_inst_num;
>+	/* UMC regiser per channel offset */
>+	uint32_t channel_offs;
>+	/* channel index table of interleaved memory */
>+	const uint32_t *channel_idx_tbl;
>+
>+	const struct amdgpu_umc_funcs *funcs;
>+};
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c	2019-08-31 15:01:11.844736167 -0500
>@@ -1073,7 +1073,7 @@
> 	ib->length_dw = 16;
> 
> 	if (direct) {
>-		r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
>+		r = reservation_object_wait_timeout_rcu(bo->tbo.base.resv,
> 							true, false,
> 							msecs_to_jiffies(10));
> 		if (r == 0)
>@@ -1085,7 +1085,7 @@
> 		if (r)
> 			goto err_free;
> 	} else {
>-		r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
>+		r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv,
> 				     AMDGPU_FENCE_OWNER_UNDEFINED, false);
> 		if (r)
> 			goto err_free;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c	2019-08-31 15:01:11.844736167 -0500
>@@ -46,12 +46,20 @@
> #define FIRMWARE_RAVEN		"amdgpu/raven_vcn.bin"
> #define FIRMWARE_PICASSO	"amdgpu/picasso_vcn.bin"
> #define FIRMWARE_RAVEN2		"amdgpu/raven2_vcn.bin"
>+#define FIRMWARE_ARCTURUS 	"amdgpu/arcturus_vcn.bin"
>+#define FIRMWARE_RENOIR 	"amdgpu/renoir_vcn.bin"
> #define FIRMWARE_NAVI10 	"amdgpu/navi10_vcn.bin"
>+#define FIRMWARE_NAVI14 	"amdgpu/navi14_vcn.bin"
>+#define FIRMWARE_NAVI12 	"amdgpu/navi12_vcn.bin"
> 
> MODULE_FIRMWARE(FIRMWARE_RAVEN);
> MODULE_FIRMWARE(FIRMWARE_PICASSO);
> MODULE_FIRMWARE(FIRMWARE_RAVEN2);
>+MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
>+MODULE_FIRMWARE(FIRMWARE_RENOIR);
> MODULE_FIRMWARE(FIRMWARE_NAVI10);
>+MODULE_FIRMWARE(FIRMWARE_NAVI14);
>+MODULE_FIRMWARE(FIRMWARE_NAVI12);
> 
> static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
> 
>@@ -61,7 +69,7 @@
> 	const char *fw_name;
> 	const struct common_firmware_header *hdr;
> 	unsigned char fw_check;
>-	int r;
>+	int i, r;
> 
> 	INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
> 
>@@ -74,12 +82,33 @@
> 		else
> 			fw_name = FIRMWARE_RAVEN;
> 		break;
>+	case CHIP_ARCTURUS:
>+		fw_name = FIRMWARE_ARCTURUS;
>+		break;
>+	case CHIP_RENOIR:
>+		fw_name = FIRMWARE_RENOIR;
>+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
>+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
>+			adev->vcn.indirect_sram = true;
>+		break;
> 	case CHIP_NAVI10:
> 		fw_name = FIRMWARE_NAVI10;
> 		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
> 		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
> 			adev->vcn.indirect_sram = true;
> 		break;
>+	case CHIP_NAVI14:
>+		fw_name = FIRMWARE_NAVI14;
>+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
>+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
>+			adev->vcn.indirect_sram = true;
>+		break;
>+	case CHIP_NAVI12:
>+		fw_name = FIRMWARE_NAVI12;
>+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
>+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
>+			adev->vcn.indirect_sram = true;
>+		break;
> 	default:
> 		return -EINVAL;
> 	}
>@@ -133,12 +162,18 @@
> 	bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
> 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> 		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>-	r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
>-				    AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
>-				    &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
>-	if (r) {
>-		dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
>-		return r;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+
>+		r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
>+						AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
>+						&adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
>+		if (r) {
>+			dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
>+			return r;
>+		}
> 	}
> 
> 	if (adev->vcn.indirect_sram) {
>@@ -156,26 +191,30 @@
> 
> int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
> {
>-	int i;
>-
>-	kvfree(adev->vcn.saved_bo);
>+	int i, j;
> 
> 	if (adev->vcn.indirect_sram) {
> 		amdgpu_bo_free_kernel(&adev->vcn.dpg_sram_bo,
>-			      &adev->vcn.dpg_sram_gpu_addr,
>-			      (void **)&adev->vcn.dpg_sram_cpu_addr);
>+				      &adev->vcn.dpg_sram_gpu_addr,
>+				      (void **)&adev->vcn.dpg_sram_cpu_addr);
> 	}
> 
>-	amdgpu_bo_free_kernel(&adev->vcn.vcpu_bo,
>-			      &adev->vcn.gpu_addr,
>-			      (void **)&adev->vcn.cpu_addr);
>+	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
>+		if (adev->vcn.harvest_config & (1 << j))
>+			continue;
>+		kvfree(adev->vcn.inst[j].saved_bo);
> 
>-	amdgpu_ring_fini(&adev->vcn.ring_dec);
>+		amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
>+					  &adev->vcn.inst[j].gpu_addr,
>+					  (void **)&adev->vcn.inst[j].cpu_addr);
> 
>-	for (i = 0; i < adev->vcn.num_enc_rings; ++i)
>-		amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
>+		amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
> 
>-	amdgpu_ring_fini(&adev->vcn.ring_jpeg);
>+		for (i = 0; i < adev->vcn.num_enc_rings; ++i)
>+			amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
>+
>+		amdgpu_ring_fini(&adev->vcn.inst[j].ring_jpeg);
>+	}
> 
> 	release_firmware(adev->vcn.fw);
> 
>@@ -186,21 +225,25 @@
> {
> 	unsigned size;
> 	void *ptr;
>+	int i;
> 
> 	cancel_delayed_work_sync(&adev->vcn.idle_work);
> 
>-	if (adev->vcn.vcpu_bo == NULL)
>-		return 0;
>-
>-	size = amdgpu_bo_size(adev->vcn.vcpu_bo);
>-	ptr = adev->vcn.cpu_addr;
>-
>-	adev->vcn.saved_bo = kvmalloc(size, GFP_KERNEL);
>-	if (!adev->vcn.saved_bo)
>-		return -ENOMEM;
>-
>-	memcpy_fromio(adev->vcn.saved_bo, ptr, size);
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		if (adev->vcn.inst[i].vcpu_bo == NULL)
>+			return 0;
>+
>+		size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
>+		ptr = adev->vcn.inst[i].cpu_addr;
>+
>+		adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
>+		if (!adev->vcn.inst[i].saved_bo)
>+			return -ENOMEM;
> 
>+		memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
>+	}
> 	return 0;
> }
> 
>@@ -208,32 +251,36 @@
> {
> 	unsigned size;
> 	void *ptr;
>+	int i;
> 
>-	if (adev->vcn.vcpu_bo == NULL)
>-		return -EINVAL;
>-
>-	size = amdgpu_bo_size(adev->vcn.vcpu_bo);
>-	ptr = adev->vcn.cpu_addr;
>-
>-	if (adev->vcn.saved_bo != NULL) {
>-		memcpy_toio(ptr, adev->vcn.saved_bo, size);
>-		kvfree(adev->vcn.saved_bo);
>-		adev->vcn.saved_bo = NULL;
>-	} else {
>-		const struct common_firmware_header *hdr;
>-		unsigned offset;
>-
>-		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
>-		if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
>-			offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
>-			memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset,
>-				    le32_to_cpu(hdr->ucode_size_bytes));
>-			size -= le32_to_cpu(hdr->ucode_size_bytes);
>-			ptr += le32_to_cpu(hdr->ucode_size_bytes);
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		if (adev->vcn.inst[i].vcpu_bo == NULL)
>+			return -EINVAL;
>+
>+		size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
>+		ptr = adev->vcn.inst[i].cpu_addr;
>+
>+		if (adev->vcn.inst[i].saved_bo != NULL) {
>+			memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
>+			kvfree(adev->vcn.inst[i].saved_bo);
>+			adev->vcn.inst[i].saved_bo = NULL;
>+		} else {
>+			const struct common_firmware_header *hdr;
>+			unsigned offset;
>+
>+			hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
>+			if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
>+				offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
>+				memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
>+					    le32_to_cpu(hdr->ucode_size_bytes));
>+				size -= le32_to_cpu(hdr->ucode_size_bytes);
>+				ptr += le32_to_cpu(hdr->ucode_size_bytes);
>+			}
>+			memset_io(ptr, 0, size);
> 		}
>-		memset_io(ptr, 0, size);
> 	}
>-
> 	return 0;
> }
> 
>@@ -241,35 +288,40 @@
> {
> 	struct amdgpu_device *adev =
> 		container_of(work, struct amdgpu_device, vcn.idle_work.work);
>-	unsigned int fences = 0;
>-	unsigned int i;
>+	unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
>+	unsigned int i, j;
> 
>-	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>-		fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
>-	}
>+	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
>+		if (adev->vcn.harvest_config & (1 << j))
>+			continue;
>+		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>+			fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
>+		}
> 
>-	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)	{
>-		struct dpg_pause_state new_state;
>+		if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)	{
>+			struct dpg_pause_state new_state;
> 
>-		if (fences)
>-			new_state.fw_based = VCN_DPG_STATE__PAUSE;
>-		else
>-			new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
>+			if (fence[j])
>+				new_state.fw_based = VCN_DPG_STATE__PAUSE;
>+			else
>+				new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
>+
>+			if (amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg))
>+				new_state.jpeg = VCN_DPG_STATE__PAUSE;
>+			else
>+				new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
> 
>-		if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg))
>-			new_state.jpeg = VCN_DPG_STATE__PAUSE;
>-		else
>-			new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
>+			adev->vcn.pause_dpg_mode(adev, &new_state);
>+		}
> 
>-		adev->vcn.pause_dpg_mode(adev, &new_state);
>+		fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_jpeg);
>+		fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
>+		fences += fence[j];
> 	}
> 
>-	fences += amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg);
>-	fences += amdgpu_fence_count_emitted(&adev->vcn.ring_dec);
>-
> 	if (fences == 0) {
> 		amdgpu_gfx_off_ctrl(adev, true);
>-		if (adev->asic_type < CHIP_NAVI10 && adev->pm.dpm_enabled)
>+		if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled)
> 			amdgpu_dpm_enable_uvd(adev, false);
> 		else
> 			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
>@@ -286,7 +338,7 @@
> 
> 	if (set_clocks) {
> 		amdgpu_gfx_off_ctrl(adev, false);
>-		if (adev->asic_type < CHIP_NAVI10 && adev->pm.dpm_enabled)
>+		if (adev->asic_type < CHIP_ARCTURUS && adev->pm.dpm_enabled)
> 			amdgpu_dpm_enable_uvd(adev, true);
> 		else
> 			amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
>@@ -299,14 +351,14 @@
> 		unsigned int i;
> 
> 		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>-			fences += amdgpu_fence_count_emitted(&adev->vcn.ring_enc[i]);
>+			fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
> 		}
> 		if (fences)
> 			new_state.fw_based = VCN_DPG_STATE__PAUSE;
> 		else
> 			new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
> 
>-		if (amdgpu_fence_count_emitted(&adev->vcn.ring_jpeg))
>+		if (amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_jpeg))
> 			new_state.jpeg = VCN_DPG_STATE__PAUSE;
> 		else
> 			new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
>@@ -332,7 +384,7 @@
> 	unsigned i;
> 	int r;
> 
>-	WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD);
>+	WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
> 	r = amdgpu_ring_alloc(ring, 3);
> 	if (r)
> 		return r;
>@@ -340,7 +392,7 @@
> 	amdgpu_ring_write(ring, 0xDEADBEEF);
> 	amdgpu_ring_commit(ring);
> 	for (i = 0; i < adev->usec_timeout; i++) {
>-		tmp = RREG32(adev->vcn.external.scratch9);
>+		tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
> 		if (tmp == 0xDEADBEEF)
> 			break;
> 		udelay(1);
>@@ -651,7 +703,7 @@
> 	unsigned i;
> 	int r;
> 
>-	WREG32(adev->vcn.external.jpeg_pitch, 0xCAFEDEAD);
>+	WREG32(adev->vcn.inst[ring->me].external.jpeg_pitch, 0xCAFEDEAD);
> 	r = amdgpu_ring_alloc(ring, 3);
> 	if (r)
> 		return r;
>@@ -661,7 +713,7 @@
> 	amdgpu_ring_commit(ring);
> 
> 	for (i = 0; i < adev->usec_timeout; i++) {
>-		tmp = RREG32(adev->vcn.external.jpeg_pitch);
>+		tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
> 		if (tmp == 0xDEADBEEF)
> 			break;
> 		udelay(1);
>@@ -735,7 +787,7 @@
> 	}
> 
> 	for (i = 0; i < adev->usec_timeout; i++) {
>-		tmp = RREG32(adev->vcn.external.jpeg_pitch);
>+		tmp = RREG32(adev->vcn.inst[ring->me].external.jpeg_pitch);
> 		if (tmp == 0xDEADBEEF)
> 			break;
> 		udelay(1);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h	2019-08-31 15:09:42.578781293 -0500
>@@ -30,6 +30,11 @@
> #define AMDGPU_VCN_FIRMWARE_OFFSET	256
> #define AMDGPU_VCN_MAX_ENC_RINGS	3
> 
>+#define AMDGPU_MAX_VCN_INSTANCES	2
>+
>+#define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
>+#define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
>+
> #define VCN_DEC_KMD_CMD 		0x80000000
> #define VCN_DEC_CMD_FENCE		0x00000000
> #define VCN_DEC_CMD_TRAP		0x00000001
>@@ -146,34 +151,49 @@
> 	unsigned	data1;
> 	unsigned	cmd;
> 	unsigned	nop;
>+	unsigned	context_id;
>+	unsigned	ib_vmid;
>+	unsigned	ib_bar_low;
>+	unsigned	ib_bar_high;
>+	unsigned	ib_size;
>+	unsigned	gp_scratch8;
> 	unsigned	scratch9;
> 	unsigned	jpeg_pitch;
> };
> 
>-struct amdgpu_vcn {
>+struct amdgpu_vcn_inst {
> 	struct amdgpu_bo	*vcpu_bo;
> 	void			*cpu_addr;
> 	uint64_t		gpu_addr;
>-	unsigned		fw_version;
> 	void			*saved_bo;
>-	struct delayed_work	idle_work;
>-	const struct firmware	*fw;	/* VCN firmware */
> 	struct amdgpu_ring	ring_dec;
> 	struct amdgpu_ring	ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
> 	struct amdgpu_ring	ring_jpeg;
> 	struct amdgpu_irq_src	irq;
>+	struct amdgpu_vcn_reg	external;
>+};
>+
>+struct amdgpu_vcn {
>+	unsigned		fw_version;
>+	struct delayed_work	idle_work;
>+	const struct firmware	*fw;	/* VCN firmware */
> 	unsigned		num_enc_rings;
> 	enum amd_powergating_state cur_state;
> 	struct dpg_pause_state pause_state;
>-	struct amdgpu_vcn_reg	internal, external;
>-	int (*pause_dpg_mode)(struct amdgpu_device *adev,
>-		struct dpg_pause_state *new_state);
> 
> 	bool			indirect_sram;
> 	struct amdgpu_bo	*dpg_sram_bo;
> 	void			*dpg_sram_cpu_addr;
> 	uint64_t		dpg_sram_gpu_addr;
> 	uint32_t		*dpg_sram_curr_addr;
>+
>+	uint8_t	num_vcn_inst;
>+	struct amdgpu_vcn_inst	inst[AMDGPU_MAX_VCN_INSTANCES];
>+	struct amdgpu_vcn_reg	internal;
>+
>+	unsigned	harvest_config;
>+	int (*pause_dpg_mode)(struct amdgpu_device *adev,
>+		struct dpg_pause_state *new_state);
> };
> 
> int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c	2019-08-31 15:01:11.844736167 -0500
>@@ -430,48 +430,3 @@
> 
> 	return clk;
> }
>-
>-void amdgpu_virt_init_reg_access_mode(struct amdgpu_device *adev)
>-{
>-	struct amdgpu_virt *virt = &adev->virt;
>-
>-	if (virt->ops && virt->ops->init_reg_access_mode)
>-		virt->ops->init_reg_access_mode(adev);
>-}
>-
>-bool amdgpu_virt_support_psp_prg_ih_reg(struct amdgpu_device *adev)
>-{
>-	bool ret = false;
>-	struct amdgpu_virt *virt = &adev->virt;
>-
>-	if (amdgpu_sriov_vf(adev)
>-		&& (virt->reg_access_mode & AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH))
>-		ret = true;
>-
>-	return ret;
>-}
>-
>-bool amdgpu_virt_support_rlc_prg_reg(struct amdgpu_device *adev)
>-{
>-	bool ret = false;
>-	struct amdgpu_virt *virt = &adev->virt;
>-
>-	if (amdgpu_sriov_vf(adev)
>-		&& (virt->reg_access_mode & AMDGPU_VIRT_REG_ACCESS_RLC)
>-		&& !(amdgpu_sriov_runtime(adev)))
>-		ret = true;
>-
>-	return ret;
>-}
>-
>-bool amdgpu_virt_support_skip_setting(struct amdgpu_device *adev)
>-{
>-	bool ret = false;
>-	struct amdgpu_virt *virt = &adev->virt;
>-
>-	if (amdgpu_sriov_vf(adev)
>-		&& (virt->reg_access_mode & AMDGPU_VIRT_REG_SKIP_SEETING))
>-		ret = true;
>-
>-	return ret;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h	2019-08-31 15:01:11.844736167 -0500
>@@ -48,12 +48,6 @@
> 	uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
> };
> 
>-/* According to the fw feature, some new reg access modes are supported */
>-#define AMDGPU_VIRT_REG_ACCESS_LEGACY          (1 << 0) /* directly mmio */
>-#define AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH      (1 << 1) /* by PSP */
>-#define AMDGPU_VIRT_REG_ACCESS_RLC             (1 << 2) /* by RLC */
>-#define AMDGPU_VIRT_REG_SKIP_SEETING           (1 << 3) /* Skip setting reg */
>-
> /**
>  * struct amdgpu_virt_ops - amdgpu device virt operations
>  */
>@@ -65,7 +59,6 @@
> 	void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
> 	int (*get_pp_clk)(struct amdgpu_device *adev, u32 type, char *buf);
> 	int (*force_dpm_level)(struct amdgpu_device *adev, u32 level);
>-	void (*init_reg_access_mode)(struct amdgpu_device *adev);
> };
> 
> /*
>@@ -315,10 +308,4 @@
> void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
> uint32_t amdgpu_virt_get_sclk(struct amdgpu_device *adev, bool lowest);
> uint32_t amdgpu_virt_get_mclk(struct amdgpu_device *adev, bool lowest);
>-
>-void amdgpu_virt_init_reg_access_mode(struct amdgpu_device *adev);
>-bool amdgpu_virt_support_psp_prg_ih_reg(struct amdgpu_device *adev);
>-bool amdgpu_virt_support_rlc_prg_reg(struct amdgpu_device *adev);
>-bool amdgpu_virt_support_skip_setting(struct amdgpu_device *adev);
>-
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c	2019-08-31 15:01:11.845736167 -0500
>@@ -302,7 +302,7 @@
> 	base->next = bo->vm_bo;
> 	bo->vm_bo = base;
> 
>-	if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
>+	if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
> 		return;
> 
> 	vm->bulk_moveable = false;
>@@ -583,7 +583,7 @@
> 	for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
> 		struct amdgpu_vm *vm = bo_base->vm;
> 
>-		if (abo->tbo.resv == vm->root.base.bo->tbo.resv)
>+		if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
> 			vm->bulk_moveable = false;
> 	}
> 
>@@ -834,7 +834,7 @@
> 		bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
> 	bp->type = ttm_bo_type_kernel;
> 	if (vm->root.base.bo)
>-		bp->resv = vm->root.base.bo->tbo.resv;
>+		bp->resv = vm->root.base.bo->tbo.base.resv;
> }
> 
> /**
>@@ -1574,7 +1574,7 @@
> 	flags &= ~AMDGPU_PTE_EXECUTABLE;
> 	flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
> 
>-	if (adev->asic_type == CHIP_NAVI10) {
>+	if (adev->asic_type >= CHIP_NAVI10) {
> 		flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
> 		flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
> 	} else {
>@@ -1702,7 +1702,7 @@
> 			ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
> 			pages_addr = ttm->dma_address;
> 		}
>-		exclusive = reservation_object_get_excl(bo->tbo.resv);
>+		exclusive = reservation_object_get_excl(bo->tbo.base.resv);
> 	}
> 
> 	if (bo) {
>@@ -1712,7 +1712,7 @@
> 		flags = 0x0;
> 	}
> 
>-	if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
>+	if (clear || (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv))
> 		last_update = &vm->last_update;
> 	else
> 		last_update = &bo_va->last_pt_update;
>@@ -1743,7 +1743,7 @@
> 	 * the evicted list so that it gets validated again on the
> 	 * next command submission.
> 	 */
>-	if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
>+	if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
> 		uint32_t mem_type = bo->tbo.mem.mem_type;
> 
> 		if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
>@@ -1879,7 +1879,7 @@
>  */
> static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
> {
>-	struct reservation_object *resv = vm->root.base.bo->tbo.resv;
>+	struct reservation_object *resv = vm->root.base.bo->tbo.base.resv;
> 	struct dma_fence *excl, **shared;
> 	unsigned i, shared_count;
> 	int r;
>@@ -1993,7 +1993,7 @@
> 	while (!list_empty(&vm->invalidated)) {
> 		bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
> 					 base.vm_status);
>-		resv = bo_va->base.bo->tbo.resv;
>+		resv = bo_va->base.bo->tbo.base.resv;
> 		spin_unlock(&vm->invalidated_lock);
> 
> 		/* Try to reserve the BO to avoid clearing its ptes */
>@@ -2084,7 +2084,7 @@
> 	if (mapping->flags & AMDGPU_PTE_PRT)
> 		amdgpu_vm_prt_get(adev);
> 
>-	if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
>+	if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv &&
> 	    !bo_va->base.moved) {
> 		list_move(&bo_va->base.vm_status, &vm->moved);
> 	}
>@@ -2416,7 +2416,8 @@
> 			struct amdgpu_bo *bo;
> 
> 			bo = mapping->bo_va->base.bo;
>-			if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket)
>+			if (reservation_object_locking_ctx(bo->tbo.base.resv) !=
>+			    ticket)
> 				continue;
> 		}
> 
>@@ -2443,7 +2444,7 @@
> 	struct amdgpu_vm_bo_base **base;
> 
> 	if (bo) {
>-		if (bo->tbo.resv == vm->root.base.bo->tbo.resv)
>+		if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
> 			vm->bulk_moveable = false;
> 
> 		for (base = &bo_va->base.bo->vm_bo; *base;
>@@ -2507,7 +2508,7 @@
> 	for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
> 		struct amdgpu_vm *vm = bo_base->vm;
> 
>-		if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
>+		if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
> 			amdgpu_vm_bo_evicted(bo_base);
> 			continue;
> 		}
>@@ -2518,7 +2519,7 @@
> 
> 		if (bo->tbo.type == ttm_bo_type_kernel)
> 			amdgpu_vm_bo_relocated(bo_base);
>-		else if (bo->tbo.resv == vm->root.base.bo->tbo.resv)
>+		else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
> 			amdgpu_vm_bo_moved(bo_base);
> 		else
> 			amdgpu_vm_bo_invalidated(bo_base);
>@@ -2648,7 +2649,7 @@
>  */
> long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
> {
>-	return reservation_object_wait_timeout_rcu(vm->root.base.bo->tbo.resv,
>+	return reservation_object_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv,
> 						   true, true, timeout);
> }
> 
>@@ -2723,7 +2724,7 @@
> 	if (r)
> 		goto error_free_root;
> 
>-	r = reservation_object_reserve_shared(root->tbo.resv, 1);
>+	r = reservation_object_reserve_shared(root->tbo.base.resv, 1);
> 	if (r)
> 		goto error_unreserve;
> 
>@@ -2862,6 +2863,13 @@
> 	WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
> 		  "CPU update of VM recommended only for large BAR system\n");
> 
>+	if (vm->use_cpu_for_update)
>+		vm->update_funcs = &amdgpu_vm_cpu_funcs;
>+	else
>+		vm->update_funcs = &amdgpu_vm_sdma_funcs;
>+	dma_fence_put(vm->last_update);
>+	vm->last_update = NULL;
>+
> 	if (vm->pasid) {
> 		unsigned long flags;
> 
>@@ -3060,12 +3068,12 @@
> 	switch (args->in.op) {
> 	case AMDGPU_VM_OP_RESERVE_VMID:
> 		/* current, we only have requirement to reserve vmid from gfxhub */
>-		r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
>+		r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
> 		if (r)
> 			return r;
> 		break;
> 	case AMDGPU_VM_OP_UNRESERVE_VMID:
>-		amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
>+		amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
> 		break;
> 	default:
> 		return -EINVAL;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h	2019-08-31 15:01:11.845736167 -0500
>@@ -90,7 +90,7 @@
>                                 | AMDGPU_PTE_WRITEABLE  \
>                                 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
> 
>-/* NAVI10 only */
>+/* gfx10 */
> #define AMDGPU_PTE_MTYPE_NV10(a)       ((uint64_t)(a) << 48)
> #define AMDGPU_PTE_MTYPE_NV10_MASK     AMDGPU_PTE_MTYPE_NV10(7ULL)
> 
>@@ -100,9 +100,10 @@
> #define AMDGPU_VM_FAULT_STOP_ALWAYS	2
> 
> /* max number of VMHUB */
>-#define AMDGPU_MAX_VMHUBS			2
>-#define AMDGPU_GFXHUB				0
>-#define AMDGPU_MMHUB				1
>+#define AMDGPU_MAX_VMHUBS			3
>+#define AMDGPU_GFXHUB_0				0
>+#define AMDGPU_MMHUB_0				1
>+#define AMDGPU_MMHUB_1				2
> 
> /* hardcode that limit for now */
> #define AMDGPU_VA_RESERVED_SIZE			(1ULL << 20)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c	2019-08-31 15:01:11.845736167 -0500
>@@ -72,7 +72,7 @@
> 	if (r)
> 		return r;
> 
>-	r = amdgpu_sync_resv(p->adev, &p->job->sync, root->tbo.resv,
>+	r = amdgpu_sync_resv(p->adev, &p->job->sync, root->tbo.base.resv,
> 			     owner, false);
> 	if (r)
> 		return r;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c	2019-08-31 15:01:11.845736167 -0500
>@@ -25,7 +25,7 @@
> #include "amdgpu.h"
> #include "amdgpu_xgmi.h"
> #include "amdgpu_smu.h"
>-
>+#include "df/df_3_6_offset.h"
> 
> static DEFINE_MUTEX(xgmi_mutex);
> 
>@@ -131,9 +131,37 @@
> 
> }
> 
>+#define AMDGPU_XGMI_SET_FICAA(o)	((o) | 0x456801)
>+static ssize_t amdgpu_xgmi_show_error(struct device *dev,
>+				      struct device_attribute *attr,
>+				      char *buf)
>+{
>+	struct drm_device *ddev = dev_get_drvdata(dev);
>+	struct amdgpu_device *adev = ddev->dev_private;
>+	uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
>+	uint64_t fica_out;
>+	unsigned int error_count = 0;
>+
>+	ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
>+	ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
> 
>-static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
>+	fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_ctl_in);
>+	if (fica_out != 0x1f)
>+		pr_err("xGMI error counters not enabled!\n");
>+
>+	fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_status_in);
>+
>+	if ((fica_out & 0xffff) == 2)
>+		error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
> 
>+	adev->df_funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
>+
>+	return snprintf(buf, PAGE_SIZE, "%d\n", error_count);
>+}
>+
>+
>+static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
>+static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
> 
> static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
> 					 struct amdgpu_hive_info *hive)
>@@ -148,6 +176,12 @@
> 		return ret;
> 	}
> 
>+	/* Create xgmi error file */
>+	ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
>+	if (ret)
>+		pr_err("failed to create xgmi_error\n");
>+
>+
> 	/* Create sysfs link to hive info folder on the first device */
> 	if (adev != hive->adev) {
> 		ret = sysfs_create_link(&adev->dev->kobj, hive->kobj,
>@@ -248,7 +282,7 @@
> 
> 	dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate);
> 
>-	if (is_support_sw_smu(adev))
>+	if (is_support_sw_smu_xgmi(adev))
> 		ret = smu_set_xgmi_pstate(&adev->smu, pstate);
> 	if (ret)
> 		dev_err(adev->dev,
>@@ -296,23 +330,28 @@
> 	struct amdgpu_xgmi	*entry;
> 	struct amdgpu_device *tmp_adev = NULL;
> 
>-	int count = 0, ret = -EINVAL;
>+	int count = 0, ret = 0;
> 
> 	if (!adev->gmc.xgmi.supported)
> 		return 0;
> 
>-	ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
>-	if (ret) {
>-		dev_err(adev->dev,
>-			"XGMI: Failed to get node id\n");
>-		return ret;
>-	}
>+	if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
>+		ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
>+		if (ret) {
>+			dev_err(adev->dev,
>+				"XGMI: Failed to get hive id\n");
>+			return ret;
>+		}
> 
>-	ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
>-	if (ret) {
>-		dev_err(adev->dev,
>-			"XGMI: Failed to get hive id\n");
>-		return ret;
>+		ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
>+		if (ret) {
>+			dev_err(adev->dev,
>+				"XGMI: Failed to get node id\n");
>+			return ret;
>+		}
>+	} else {
>+		adev->gmc.xgmi.hive_id = 16;
>+		adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16;
> 	}
> 
> 	hive = amdgpu_get_xgmi_hive(adev, 1);
>@@ -332,29 +371,32 @@
> 	top_info->num_nodes = count;
> 	hive->number_devices = count;
> 
>-	list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
>-		/* update node list for other device in the hive */
>-		if (tmp_adev != adev) {
>-			top_info = &tmp_adev->psp.xgmi_context.top_info;
>-			top_info->nodes[count - 1].node_id = adev->gmc.xgmi.node_id;
>-			top_info->num_nodes = count;
>+	if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
>+		list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
>+			/* update node list for other device in the hive */
>+			if (tmp_adev != adev) {
>+				top_info = &tmp_adev->psp.xgmi_context.top_info;
>+				top_info->nodes[count - 1].node_id =
>+					adev->gmc.xgmi.node_id;
>+				top_info->num_nodes = count;
>+			}
>+			ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
>+			if (ret)
>+				goto exit;
> 		}
>-		ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
>-		if (ret)
>-			goto exit;
>-	}
> 
>-	/* get latest topology info for each device from psp */
>-	list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
>-		ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
>-				&tmp_adev->psp.xgmi_context.top_info);
>-		if (ret) {
>-			dev_err(tmp_adev->dev,
>-				"XGMI: Get topology failure on device %llx, hive %llx, ret %d",
>-				tmp_adev->gmc.xgmi.node_id,
>-				tmp_adev->gmc.xgmi.hive_id, ret);
>-			/* To do : continue with some node failed or disable the whole hive */
>-			goto exit;
>+		/* get latest topology info for each device from psp */
>+		list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
>+			ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
>+					&tmp_adev->psp.xgmi_context.top_info);
>+			if (ret) {
>+				dev_err(tmp_adev->dev,
>+					"XGMI: Get topology failure on device %llx, hive %llx, ret %d",
>+					tmp_adev->gmc.xgmi.node_id,
>+					tmp_adev->gmc.xgmi.hive_id, ret);
>+				/* To do : continue with some node failed or disable the whole hive */
>+				goto exit;
>+			}
> 		}
> 	}
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c	2019-08-31 15:01:11.845736167 -0500
>@@ -0,0 +1,59 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#include "amdgpu.h"
>+#include "soc15.h"
>+
>+#include "soc15_common.h"
>+#include "soc15_hw_ip.h"
>+#include "arct_ip_offset.h"
>+
>+int arct_reg_base_init(struct amdgpu_device *adev)
>+{
>+	/* HW has more IP blocks,  only initialized the block needed by our driver  */
>+	uint32_t i;
>+	for (i = 0 ; i < MAX_INSTANCE ; ++i) {
>+		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
>+		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
>+		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
>+		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
>+		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
>+		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
>+		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
>+		adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
>+		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
>+		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
>+		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
>+		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));
>+		adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i]));
>+		adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i]));
>+		adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i]));
>+		adev->reg_offset[SDMA5_HWIP][i] = (uint32_t *)(&(SDMA5_BASE.instance[i]));
>+		adev->reg_offset[SDMA6_HWIP][i] = (uint32_t *)(&(SDMA6_BASE.instance[i]));
>+		adev->reg_offset[SDMA7_HWIP][i] = (uint32_t *)(&(SDMA7_BASE.instance[i]));
>+		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
>+		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
>+	}
>+	return 0;
>+}
>+
>+
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/athub_v1_0.c	2019-08-31 15:01:11.845736167 -0500
>@@ -0,0 +1,103 @@
>+/*
>+ * Copyright 2016 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#include "amdgpu.h"
>+#include "athub_v1_0.h"
>+
>+#include "athub/athub_1_0_offset.h"
>+#include "athub/athub_1_0_sh_mask.h"
>+#include "vega10_enum.h"
>+
>+#include "soc15_common.h"
>+
>+static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
>+						   bool enable)
>+{
>+	uint32_t def, data;
>+
>+	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
>+
>+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
>+		data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
>+	else
>+		data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
>+
>+	if (def != data)
>+		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
>+}
>+
>+static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
>+						  bool enable)
>+{
>+	uint32_t def, data;
>+
>+	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
>+
>+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
>+	    (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
>+		data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
>+	else
>+		data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
>+
>+	if(def != data)
>+		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
>+}
>+
>+int athub_v1_0_set_clockgating(struct amdgpu_device *adev,
>+			       enum amd_clockgating_state state)
>+{
>+	if (amdgpu_sriov_vf(adev))
>+		return 0;
>+
>+	switch (adev->asic_type) {
>+	case CHIP_VEGA10:
>+	case CHIP_VEGA12:
>+	case CHIP_VEGA20:
>+	case CHIP_RAVEN:
>+		athub_update_medium_grain_clock_gating(adev,
>+				state == AMD_CG_STATE_GATE ? true : false);
>+		athub_update_medium_grain_light_sleep(adev,
>+				state == AMD_CG_STATE_GATE ? true : false);
>+		break;
>+	default:
>+		break;
>+	}
>+
>+	return 0;
>+}
>+
>+void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
>+{
>+	int data;
>+
>+	if (amdgpu_sriov_vf(adev))
>+		*flags = 0;
>+
>+	/* AMD_CG_SUPPORT_ATHUB_MGCG */
>+	data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
>+	if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
>+		*flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
>+
>+	/* AMD_CG_SUPPORT_ATHUB_LS */
>+	if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
>+		*flags |= AMD_CG_SUPPORT_ATHUB_LS;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/athub_v1_0.h	2019-08-31 15:01:11.845736167 -0500
>@@ -0,0 +1,30 @@
>+/*
>+ * Copyright 2016 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#ifndef __ATHUB_V1_0_H__
>+#define __ATHUB_V1_0_H__
>+
>+int athub_v1_0_set_clockgating(struct amdgpu_device *adev,
>+			       enum amd_clockgating_state state);
>+void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c	2019-08-31 15:01:11.845736167 -0500
>@@ -74,6 +74,8 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		athub_v2_0_update_medium_grain_clock_gating(adev,
> 				state == AMD_CG_STATE_GATE ? true : false);
> 		athub_v2_0_update_medium_grain_light_sleep(adev,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/cik.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/cik.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/cik.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/cik.c	2019-08-31 15:01:11.845736167 -0500
>@@ -1291,6 +1291,12 @@
> 	return r;
> }
> 
>+static enum amd_reset_method
>+cik_asic_reset_method(struct amdgpu_device *adev)
>+{
>+	return AMD_RESET_METHOD_LEGACY;
>+}
>+
> static u32 cik_get_config_memsize(struct amdgpu_device *adev)
> {
> 	return RREG32(mmCONFIG_MEMSIZE);
>@@ -1823,6 +1829,7 @@
> 	.read_bios_from_rom = &cik_read_bios_from_rom,
> 	.read_register = &cik_read_register,
> 	.reset = &cik_asic_reset,
>+	.reset_method = &cik_asic_reset_method,
> 	.set_vga_state = &cik_vga_set_state,
> 	.get_xclk = &cik_get_xclk,
> 	.set_uvd_clocks = &cik_set_uvd_clocks,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c	2019-08-31 15:01:11.846736167 -0500
>@@ -236,6 +236,7 @@
> 				int crtc_id, u64 crtc_base, bool async)
> {
> 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
>+	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
> 	u32 tmp;
> 
> 	/* flip at hsync for async, default is vsync */
>@@ -243,6 +244,9 @@
> 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
> 			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
> 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
>+	/* update pitch */
>+	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
>+	       fb->pitches[0] / fb->format->cpp[0]);
> 	/* update the primary scanout address */
> 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
> 	       upper_32_bits(crtc_base));
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c	2019-08-31 15:01:11.846736167 -0500
>@@ -254,6 +254,7 @@
> 				int crtc_id, u64 crtc_base, bool async)
> {
> 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
>+	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
> 	u32 tmp;
> 
> 	/* flip immediate for async, default is vsync */
>@@ -261,6 +262,9 @@
> 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
> 			    GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
> 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
>+	/* update pitch */
>+	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
>+	       fb->pitches[0] / fb->format->cpp[0]);
> 	/* update the scanout addresses */
> 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
> 	       upper_32_bits(crtc_base));
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c	2019-08-31 15:01:11.846736167 -0500
>@@ -191,10 +191,14 @@
> 			       int crtc_id, u64 crtc_base, bool async)
> {
> 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
>+	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
> 
> 	/* flip at hsync for async, default is vsync */
> 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
> 	       GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
>+	/* update pitch */
>+	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
>+	       fb->pitches[0] / fb->format->cpp[0]);
> 	/* update the scanout addresses */
> 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
> 	       upper_32_bits(crtc_base));
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c	2019-08-31 15:01:11.846736167 -0500
>@@ -184,10 +184,14 @@
> 			       int crtc_id, u64 crtc_base, bool async)
> {
> 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
>+	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
> 
> 	/* flip at hsync for async, default is vsync */
> 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
> 	       GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
>+	/* update pitch */
>+	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
>+	       fb->pitches[0] / fb->format->cpp[0]);
> 	/* update the primary scanout addresses */
> 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
> 	       upper_32_bits(crtc_base));
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_virtual.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/dce_virtual.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/dce_virtual.c	2019-08-31 15:01:11.846736167 -0500
>@@ -454,13 +454,8 @@
> #endif
> 		/* no DCE */
> 		break;
>-	case CHIP_VEGA10:
>-	case CHIP_VEGA12:
>-	case CHIP_VEGA20:
>-	case CHIP_NAVI10:
>-		break;
> 	default:
>-		DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
>+		break;
> 	}
> 	return 0;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/df_v3_6.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/df_v3_6.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/df_v3_6.c	2019-08-31 15:01:11.846736167 -0500
>@@ -93,6 +93,96 @@
> 		NULL
> };
> 
>+static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
>+				 uint32_t ficaa_val)
>+{
>+	unsigned long flags, address, data;
>+	uint32_t ficadl_val, ficadh_val;
>+
>+	address = adev->nbio_funcs->get_pcie_index_offset(adev);
>+	data = adev->nbio_funcs->get_pcie_data_offset(adev);
>+
>+	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
>+	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
>+	WREG32(data, ficaa_val);
>+
>+	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
>+	ficadl_val = RREG32(data);
>+
>+	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
>+	ficadh_val = RREG32(data);
>+
>+	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
>+
>+	return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val);
>+}
>+
>+static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
>+			     uint32_t ficadl_val, uint32_t ficadh_val)
>+{
>+	unsigned long flags, address, data;
>+
>+	address = adev->nbio_funcs->get_pcie_index_offset(adev);
>+	data = adev->nbio_funcs->get_pcie_data_offset(adev);
>+
>+	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
>+	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
>+	WREG32(data, ficaa_val);
>+
>+	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
>+	WREG32(data, ficadl_val);
>+
>+	WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
>+	WREG32(data, ficadh_val);
>+
>+	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
>+}
>+
>+/*
>+ * df_v3_6_perfmon_rreg - read perfmon lo and hi
>+ *
>+ * required to be atomic.  no mmio method provided so subsequent reads for lo
>+ * and hi require to preserve df finite state machine
>+ */
>+static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
>+			    uint32_t lo_addr, uint32_t *lo_val,
>+			    uint32_t hi_addr, uint32_t *hi_val)
>+{
>+	unsigned long flags, address, data;
>+
>+	address = adev->nbio_funcs->get_pcie_index_offset(adev);
>+	data = adev->nbio_funcs->get_pcie_data_offset(adev);
>+
>+	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
>+	WREG32(address, lo_addr);
>+	*lo_val = RREG32(data);
>+	WREG32(address, hi_addr);
>+	*hi_val = RREG32(data);
>+	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
>+}
>+
>+/*
>+ * df_v3_6_perfmon_wreg - write to perfmon lo and hi
>+ *
>+ * required to be atomic.  no mmio method provided so subsequent reads after
>+ * data writes cannot occur to preserve data fabrics finite state machine.
>+ */
>+static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
>+			    uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val)
>+{
>+	unsigned long flags, address, data;
>+
>+	address = adev->nbio_funcs->get_pcie_index_offset(adev);
>+	data = adev->nbio_funcs->get_pcie_data_offset(adev);
>+
>+	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
>+	WREG32(address, lo_addr);
>+	WREG32(data, lo_val);
>+	WREG32(address, hi_addr);
>+	WREG32(data, hi_val);
>+	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
>+}
>+
> /* get the number of df counters available */
> static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev,
> 		struct device_attribute *attr,
>@@ -268,6 +358,10 @@
> 					  uint32_t *lo_val,
> 					  uint32_t *hi_val)
> {
>+
>+	uint32_t eventsel, instance, unitmask;
>+	uint32_t instance_10, instance_5432, instance_76;
>+
> 	df_v3_6_pmc_get_addr(adev, config, 1, lo_base_addr, hi_base_addr);
> 
> 	if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) {
>@@ -276,40 +370,33 @@
> 		return -ENXIO;
> 	}
> 
>-	if (lo_val && hi_val) {
>-		uint32_t eventsel, instance, unitmask;
>-		uint32_t instance_10, instance_5432, instance_76;
>-
>-		eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;
>-		unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;
>-		instance = DF_V3_6_GET_INSTANCE(config);
>-
>-		instance_10 = instance & 0x3;
>-		instance_5432 = (instance >> 2) & 0xf;
>-		instance_76 = (instance >> 6) & 0x3;
>+	eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;
>+	unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;
>+	instance = DF_V3_6_GET_INSTANCE(config);
>+
>+	instance_10 = instance & 0x3;
>+	instance_5432 = (instance >> 2) & 0xf;
>+	instance_76 = (instance >> 6) & 0x3;
> 
>-		*lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel;
>-		*hi_val = (instance_76 << 29) | instance_5432;
>-	}
>+	*lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel | (1 << 22);
>+	*hi_val = (instance_76 << 29) | instance_5432;
>+
>+	DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
>+		config, *lo_base_addr, *hi_base_addr, *lo_val, *hi_val);
> 
> 	return 0;
> }
> 
>-/* assign df performance counters for read */
>-static int df_v3_6_pmc_assign_cntr(struct amdgpu_device *adev,
>-				   uint64_t config,
>-				   int *is_assigned)
>+/* add df performance counters for read */
>+static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev,
>+				   uint64_t config)
> {
> 	int i, target_cntr;
> 
>-	*is_assigned = 0;
>-
> 	target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
> 
>-	if (target_cntr >= 0) {
>-		*is_assigned = 1;
>+	if (target_cntr >= 0)
> 		return 0;
>-	}
> 
> 	for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
> 		if (adev->df_perfmon_config_assign_mask[i] == 0U) {
>@@ -344,45 +431,13 @@
> 	if ((lo_base_addr == 0) || (hi_base_addr == 0))
> 		return;
> 
>-	WREG32_PCIE(lo_base_addr, 0UL);
>-	WREG32_PCIE(hi_base_addr, 0UL);
>-}
>-
>-
>-static int df_v3_6_add_perfmon_cntr(struct amdgpu_device *adev,
>-				      uint64_t config)
>-{
>-	uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
>-	int ret, is_assigned;
>-
>-	ret = df_v3_6_pmc_assign_cntr(adev, config, &is_assigned);
>-
>-	if (ret || is_assigned)
>-		return ret;
>-
>-	ret = df_v3_6_pmc_get_ctrl_settings(adev,
>-			config,
>-			&lo_base_addr,
>-			&hi_base_addr,
>-			&lo_val,
>-			&hi_val);
>-
>-	if (ret)
>-		return ret;
>-
>-	DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
>-			config, lo_base_addr, hi_base_addr, lo_val, hi_val);
>-
>-	WREG32_PCIE(lo_base_addr, lo_val);
>-	WREG32_PCIE(hi_base_addr, hi_val);
>-
>-	return ret;
>+	df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0);
> }
> 
> static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
> 			     int is_enable)
> {
>-	uint32_t lo_base_addr, hi_base_addr, lo_val;
>+	uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
> 	int ret = 0;
> 
> 	switch (adev->asic_type) {
>@@ -391,24 +446,20 @@
> 		df_v3_6_reset_perfmon_cntr(adev, config);
> 
> 		if (is_enable) {
>-			ret = df_v3_6_add_perfmon_cntr(adev, config);
>+			ret = df_v3_6_pmc_add_cntr(adev, config);
> 		} else {
> 			ret = df_v3_6_pmc_get_ctrl_settings(adev,
> 					config,
> 					&lo_base_addr,
> 					&hi_base_addr,
>-					NULL,
>-					NULL);
>+					&lo_val,
>+					&hi_val);
> 
> 			if (ret)
> 				return ret;
> 
>-			lo_val = RREG32_PCIE(lo_base_addr);
>-
>-			DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x",
>-				config, lo_base_addr, hi_base_addr, lo_val);
>-
>-			WREG32_PCIE(lo_base_addr, lo_val | (1ULL << 22));
>+			df_v3_6_perfmon_wreg(adev, lo_base_addr, lo_val,
>+					hi_base_addr, hi_val);
> 		}
> 
> 		break;
>@@ -422,7 +473,7 @@
> static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
> 			    int is_disable)
> {
>-	uint32_t lo_base_addr, hi_base_addr, lo_val;
>+	uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
> 	int ret = 0;
> 
> 	switch (adev->asic_type) {
>@@ -431,18 +482,13 @@
> 			config,
> 			&lo_base_addr,
> 			&hi_base_addr,
>-			NULL,
>-			NULL);
>+			&lo_val,
>+			&hi_val);
> 
> 		if (ret)
> 			return ret;
> 
>-		lo_val = RREG32_PCIE(lo_base_addr);
>-
>-		DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x",
>-				config, lo_base_addr, hi_base_addr, lo_val);
>-
>-		WREG32_PCIE(lo_base_addr, lo_val & ~(1ULL << 22));
>+		df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0);
> 
> 		if (is_disable)
> 			df_v3_6_pmc_release_cntr(adev, config);
>@@ -471,8 +517,8 @@
> 		if ((lo_base_addr == 0) || (hi_base_addr == 0))
> 			return;
> 
>-		lo_val = RREG32_PCIE(lo_base_addr);
>-		hi_val = RREG32_PCIE(hi_base_addr);
>+		df_v3_6_perfmon_rreg(adev, lo_base_addr, &lo_val,
>+				hi_base_addr, &hi_val);
> 
> 		*count  = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL);
> 
>@@ -480,7 +526,7 @@
> 			*count = 0;
> 
> 		DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
>-			config, lo_base_addr, hi_base_addr, lo_val, hi_val);
>+			 config, lo_base_addr, hi_base_addr, lo_val, hi_val);
> 
> 		break;
> 
>@@ -499,5 +545,7 @@
> 	.get_clockgating_state = df_v3_6_get_clockgating_state,
> 	.pmc_start = df_v3_6_pmc_start,
> 	.pmc_stop = df_v3_6_pmc_stop,
>-	.pmc_get_count = df_v3_6_pmc_get_count
>+	.pmc_get_count = df_v3_6_pmc_get_count,
>+	.get_fica = df_v3_6_get_fica,
>+	.set_fica = df_v3_6_set_fica
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c	2019-08-31 15:01:11.847736167 -0500
>@@ -357,7 +357,7 @@
> 
> void gfxhub_v1_0_init(struct amdgpu_device *adev)
> {
>-	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
>+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
> 
> 	hub->ctx0_ptb_addr_lo32 =
> 		SOC15_REG_OFFSET(GC, 0,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c	2019-08-31 15:01:11.847736167 -0500
>@@ -140,7 +140,7 @@
> 	/* XXX for emulation, Refer to closed source code.*/
> 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
> 			    L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
>-	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
>+	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> 	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
> 	WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
>@@ -333,7 +333,7 @@
> 
> void gfxhub_v2_0_init(struct amdgpu_device *adev)
> {
>-	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
>+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
> 
> 	hub->ctx0_ptb_addr_lo32 =
> 		SOC15_REG_OFFSET(GC, 0,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c	2019-08-31 15:01:12.277736205 -0500
>@@ -20,8 +20,12 @@
>  * OTHER DEALINGS IN THE SOFTWARE.
>  *
>  */
>+
>+#include <linux/delay.h>
>+#include <linux/kernel.h>
> #include <linux/firmware.h>
>-#include <drm/drmP.h>
>+#include <linux/module.h>
>+#include <linux/pci.h>
> #include "amdgpu.h"
> #include "amdgpu_gfx.h"
> #include "amdgpu_psp.h"
>@@ -56,6 +60,9 @@
> #define F32_CE_PROGRAM_RAM_SIZE		65536
> #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
> 
>+#define mmCGTT_GS_NGG_CLK_CTRL	0x5087
>+#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX	1
>+
> MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
> MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
> MODULE_FIRMWARE("amdgpu/navi10_me.bin");
>@@ -63,6 +70,20 @@
> MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
> MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
> 
>+MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
>+MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
>+MODULE_FIRMWARE("amdgpu/navi14_me.bin");
>+MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
>+MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
>+MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
>+
>+MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
>+MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
>+MODULE_FIRMWARE("amdgpu/navi12_me.bin");
>+MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
>+MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
>+MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
>+
> static const struct soc15_reg_golden golden_settings_gc_10_1[] =
> {
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
>@@ -109,6 +130,99 @@
> 	/* Pending on emulation bring up */
> };
> 
>+static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
>+{
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000),
>+};
>+
>+static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
>+{
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0xc0000100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
>+};
>+
>+static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
>+{
>+	/* Pending on emulation bring up */
>+};
>+
>+static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
>+{
>+	/* Pending on emulation bring up */
>+};
>+
> #define DEFAULT_SH_MEM_CONFIG \
> 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
> 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
>@@ -250,6 +364,22 @@
> 						golden_settings_gc_10_0_nv10,
> 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
> 		break;
>+	case CHIP_NAVI14:
>+		soc15_program_register_sequence(adev,
>+						golden_settings_gc_10_1_1,
>+						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
>+		soc15_program_register_sequence(adev,
>+						golden_settings_gc_10_1_nv14,
>+						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
>+		break;
>+	case CHIP_NAVI12:
>+		soc15_program_register_sequence(adev,
>+						golden_settings_gc_10_1_2,
>+						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
>+		soc15_program_register_sequence(adev,
>+						golden_settings_gc_10_1_2_nv12,
>+						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
>+		break;
> 	default:
> 		break;
> 	}
>@@ -331,7 +461,7 @@
> 		if (amdgpu_emu_mode == 1)
> 			msleep(1);
> 		else
>-			DRM_UDELAY(1);
>+			udelay(1);
> 	}
> 	if (i < adev->usec_timeout) {
> 		if (amdgpu_emu_mode == 1)
>@@ -481,6 +611,12 @@
> 	case CHIP_NAVI10:
> 		chip_name = "navi10";
> 		break;
>+	case CHIP_NAVI14:
>+		chip_name = "navi14";
>+		break;
>+	case CHIP_NAVI12:
>+		chip_name = "navi12";
>+		break;
> 	default:
> 		BUG();
> 	}
>@@ -1026,6 +1162,8 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		adev->gfx.config.max_hw_contexts = 8;
> 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
> 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
>@@ -1133,6 +1271,8 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		adev->gfx.me.num_me = 1;
> 		adev->gfx.me.num_pipe_per_me = 2;
> 		adev->gfx.me.num_queue_per_pipe = 1;
>@@ -1452,6 +1592,25 @@
> 	}
> }
> 
>+static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
>+{
>+	int vmid;
>+
>+	/*
>+	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
>+	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
>+	 * the driver can enable them for graphics. VMID0 should maintain
>+	 * access so that HWS firmware can save/restore entries.
>+	 */
>+	for (vmid = 1; vmid < 16; vmid++) {
>+		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
>+		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
>+		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
>+		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
>+	}
>+}
>+
>+
> static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
> {
> 	int i, j, k;
>@@ -1461,7 +1620,8 @@
> 	u32 utcl_invreq_disable = 0;
> 	/*
> 	 * GCRD_TARGETS_DISABLE field contains
>-	 * for Navi10: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
>+	 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
>+	 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
> 	 */
> 	u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
> 		2 * max_wgp_per_sh + /* TCP */
>@@ -1469,7 +1629,8 @@
> 		4); /* GL1C */
> 	/*
> 	 * UTCL1_UTCL0_INVREQ_DISABLE field contains
>-	 * for Navi10: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
>+	 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
>+	 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
> 	 */
> 	u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
> 		2 * max_wgp_per_sh + /* TCP */
>@@ -1477,7 +1638,9 @@
> 		4 + /* RMI */
> 		1); /* SQG */
> 
>-	if (adev->asic_type == CHIP_NAVI10) {
>+	if (adev->asic_type == CHIP_NAVI10 ||
>+	    adev->asic_type == CHIP_NAVI14 ||
>+	    adev->asic_type == CHIP_NAVI12) {
> 		mutex_lock(&adev->grbm_idx_mutex);
> 		for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
> 			for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
>@@ -1535,7 +1698,7 @@
> 	/* XXX SH_MEM regs */
> 	/* where to put LDS, scratch, GPUVM in FSA64 space */
> 	mutex_lock(&adev->srbm_mutex);
>-	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
>+	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
> 		nv_grbm_select(adev, 0, 0, 0, i);
> 		/* CP and shaders */
> 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
>@@ -1552,6 +1715,7 @@
> 	mutex_unlock(&adev->srbm_mutex);
> 
> 	gfx_v10_0_init_compute_vmid(adev);
>+	gfx_v10_0_init_gds_vmid(adev);
> 
> }
> 
>@@ -1584,9 +1748,12 @@
> 
> static void gfx_v10_0_init_pg(struct amdgpu_device *adev)
> {
>+	int i;
>+
> 	gfx_v10_0_init_csb(adev);
> 
>-	amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);
>+	for (i = 0; i < adev->num_vmhubs; i++)
>+		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
> 
> 	/* TODO: init power gating */
> 	return;
>@@ -1624,9 +1791,9 @@
> 		 * hence no handshake between SMU & RLC
> 		 * GFXOFF will be disabled
> 		 */
>-		rlc_pg_cntl |= 0x80000;
>+		rlc_pg_cntl |= 0x800000;
> 	} else
>-		rlc_pg_cntl &= ~0x80000;
>+		rlc_pg_cntl &= ~0x800000;
> 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
> }
> 
>@@ -3614,20 +3781,12 @@
> 
> static int gfx_v10_0_suspend(void *handle)
> {
>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>-
>-	adev->in_suspend = true;
>-	return gfx_v10_0_hw_fini(adev);
>+	return gfx_v10_0_hw_fini(handle);
> }
> 
> static int gfx_v10_0_resume(void *handle)
> {
>-	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>-	int r;
>-
>-	r = gfx_v10_0_hw_init(adev);
>-	adev->in_suspend = false;
>-	return r;
>+	return gfx_v10_0_hw_init(handle);
> }
> 
> static bool gfx_v10_0_is_idle(void *handle)
>@@ -4037,6 +4196,7 @@
> 	bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
> 		if (!enable) {
> 			amdgpu_gfx_off_ctrl(adev, false);
> 			cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
>@@ -4056,6 +4216,8 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		gfx_v10_0_update_gfx_clock_gating(adev,
> 						 state == AMD_CG_STATE_GATE ? true : false);
> 		break;
>@@ -4453,7 +4615,7 @@
> 		if (ring->trail_seq ==
> 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
> 			break;
>-		DRM_UDELAY(1);
>+		udelay(1);
> 	}
> 
> 	if (i >= adev->usec_timeout) {
>@@ -4927,7 +5089,7 @@
> 	.align_mask = 0xff,
> 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
> 	.support_64bit_ptrs = true,
>-	.vmhub = AMDGPU_GFXHUB,
>+	.vmhub = AMDGPU_GFXHUB_0,
> 	.get_rptr = gfx_v10_0_ring_get_rptr_gfx,
> 	.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
> 	.set_wptr = gfx_v10_0_ring_set_wptr_gfx,
>@@ -4978,7 +5140,7 @@
> 	.align_mask = 0xff,
> 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
> 	.support_64bit_ptrs = true,
>-	.vmhub = AMDGPU_GFXHUB,
>+	.vmhub = AMDGPU_GFXHUB_0,
> 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
> 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
> 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
>@@ -5011,7 +5173,7 @@
> 	.align_mask = 0xff,
> 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
> 	.support_64bit_ptrs = true,
>-	.vmhub = AMDGPU_GFXHUB,
>+	.vmhub = AMDGPU_GFXHUB_0,
> 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
> 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
> 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
>@@ -5088,6 +5250,8 @@
> {
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
> 		break;
> 	default:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c	2019-08-31 15:01:11.847736167 -0500
>@@ -1890,6 +1890,24 @@
> 	}
> }
> 
>+static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
>+{
>+	int vmid;
>+
>+	/*
>+	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
>+	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
>+	 * the driver can enable them for graphics. VMID0 should maintain
>+	 * access so that HWS firmware can save/restore entries.
>+	 */
>+	for (vmid = 1; vmid < 16; vmid++) {
>+		WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
>+		WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
>+		WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
>+		WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
>+	}
>+}
>+
> static void gfx_v7_0_config_init(struct amdgpu_device *adev)
> {
> 	adev->gfx.config.double_offchip_lds_buf = 1;
>@@ -1968,6 +1986,7 @@
> 	mutex_unlock(&adev->srbm_mutex);
> 
> 	gfx_v7_0_init_compute_vmid(adev);
>+	gfx_v7_0_init_gds_vmid(adev);
> 
> 	WREG32(mmSX_DEBUG_1, 0x20);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c	2019-08-31 15:01:12.274736205 -0500
>@@ -3750,6 +3750,24 @@
> 	}
> }
> 
>+static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
>+{
>+	int vmid;
>+
>+	/*
>+	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
>+	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
>+	 * the driver can enable them for graphics. VMID0 should maintain
>+	 * access so that HWS firmware can save/restore entries.
>+	 */
>+	for (vmid = 1; vmid < 16; vmid++) {
>+		WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
>+		WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
>+		WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
>+		WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
>+	}
>+}
>+
> static void gfx_v8_0_config_init(struct amdgpu_device *adev)
> {
> 	switch (adev->asic_type) {
>@@ -3816,6 +3834,7 @@
> 	mutex_unlock(&adev->srbm_mutex);
> 
> 	gfx_v8_0_init_compute_vmid(adev);
>+	gfx_v8_0_init_gds_vmid(adev);
> 
> 	mutex_lock(&adev->grbm_idx_mutex);
> 	/*
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c	2019-08-31 15:09:16.619778999 -0500
>@@ -36,10 +36,10 @@
> 
> #include "gc/gc_9_0_offset.h"
> #include "gc/gc_9_0_sh_mask.h"
>+
> #include "vega10_enum.h"
> #include "hdp/hdp_4_0_offset.h"
> 
>-#include "soc15.h"
> #include "soc15_common.h"
> #include "clearstate_gfx9.h"
> #include "v9_structs.h"
>@@ -60,6 +60,9 @@
> #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK		0x00000001L
> #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK		0x00000006L
> 
>+#define mmGCEA_PROBE_MAP                        0x070c
>+#define mmGCEA_PROBE_MAP_BASE_IDX               0
>+
> MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
> MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
> MODULE_FIRMWARE("amdgpu/vega10_me.bin");
>@@ -104,6 +107,397 @@
> MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
> MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
> 
>+MODULE_FIRMWARE("amdgpu/arcturus_mec.bin");
>+MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin");
>+MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin");
>+
>+MODULE_FIRMWARE("amdgpu/renoir_ce.bin");
>+MODULE_FIRMWARE("amdgpu/renoir_pfp.bin");
>+MODULE_FIRMWARE("amdgpu/renoir_me.bin");
>+MODULE_FIRMWARE("amdgpu/renoir_mec.bin");
>+MODULE_FIRMWARE("amdgpu/renoir_mec2.bin");
>+MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
>+
>+#define mmTCP_CHAN_STEER_0_ARCT								0x0b03
>+#define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX							0
>+#define mmTCP_CHAN_STEER_1_ARCT								0x0b04
>+#define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX							0
>+#define mmTCP_CHAN_STEER_2_ARCT								0x0b09
>+#define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX							0
>+#define mmTCP_CHAN_STEER_3_ARCT								0x0b0a
>+#define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX							0
>+#define mmTCP_CHAN_STEER_4_ARCT								0x0b0b
>+#define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX							0
>+#define mmTCP_CHAN_STEER_5_ARCT								0x0b0c
>+#define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX							0
>+
>+enum ta_ras_gfx_subblock {
>+	/*CPC*/
>+	TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
>+	TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START,
>+	TA_RAS_BLOCK__GFX_CPC_UCODE,
>+	TA_RAS_BLOCK__GFX_DC_STATE_ME1,
>+	TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
>+	TA_RAS_BLOCK__GFX_DC_RESTORE_ME1,
>+	TA_RAS_BLOCK__GFX_DC_STATE_ME2,
>+	TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
>+	TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
>+	TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2,
>+	/* CPF*/
>+	TA_RAS_BLOCK__GFX_CPF_INDEX_START,
>+	TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START,
>+	TA_RAS_BLOCK__GFX_CPF_ROQ_ME1,
>+	TA_RAS_BLOCK__GFX_CPF_TAG,
>+	TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG,
>+	/* CPG*/
>+	TA_RAS_BLOCK__GFX_CPG_INDEX_START,
>+	TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START,
>+	TA_RAS_BLOCK__GFX_CPG_DMA_TAG,
>+	TA_RAS_BLOCK__GFX_CPG_TAG,
>+	TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG,
>+	/* GDS*/
>+	TA_RAS_BLOCK__GFX_GDS_INDEX_START,
>+	TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START,
>+	TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
>+	TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
>+	TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
>+	TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
>+	TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
>+	/* SPI*/
>+	TA_RAS_BLOCK__GFX_SPI_SR_MEM,
>+	/* SQ*/
>+	TA_RAS_BLOCK__GFX_SQ_INDEX_START,
>+	TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START,
>+	TA_RAS_BLOCK__GFX_SQ_LDS_D,
>+	TA_RAS_BLOCK__GFX_SQ_LDS_I,
>+	TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/
>+	TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR,
>+	/* SQC (3 ranges)*/
>+	TA_RAS_BLOCK__GFX_SQC_INDEX_START,
>+	/* SQC range 0*/
>+	TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START,
>+	TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
>+		TA_RAS_BLOCK__GFX_SQC_INDEX0_START,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
>+	TA_RAS_BLOCK__GFX_SQC_INDEX0_END =
>+		TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
>+	/* SQC range 1*/
>+	TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
>+	TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
>+		TA_RAS_BLOCK__GFX_SQC_INDEX1_START,
>+	TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
>+	TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
>+	TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
>+	TA_RAS_BLOCK__GFX_SQC_INDEX1_END =
>+		TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
>+	/* SQC range 2*/
>+	TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
>+	TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
>+		TA_RAS_BLOCK__GFX_SQC_INDEX2_START,
>+	TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
>+	TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
>+	TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
>+	TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
>+	TA_RAS_BLOCK__GFX_SQC_INDEX2_END =
>+		TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
>+	TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END,
>+	/* TA*/
>+	TA_RAS_BLOCK__GFX_TA_INDEX_START,
>+	TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START,
>+	TA_RAS_BLOCK__GFX_TA_FS_AFIFO,
>+	TA_RAS_BLOCK__GFX_TA_FL_LFIFO,
>+	TA_RAS_BLOCK__GFX_TA_FX_LFIFO,
>+	TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
>+	TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO,
>+	/* TCA*/
>+	TA_RAS_BLOCK__GFX_TCA_INDEX_START,
>+	TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START,
>+	TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
>+	TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO,
>+	/* TCC (5 sub-ranges)*/
>+	TA_RAS_BLOCK__GFX_TCC_INDEX_START,
>+	/* TCC range 0*/
>+	TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START,
>+	TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START,
>+	TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
>+	TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
>+	TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
>+	TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
>+	TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
>+	TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
>+	TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
>+	TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
>+	/* TCC range 1*/
>+	TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
>+	TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START,
>+	TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
>+	TA_RAS_BLOCK__GFX_TCC_INDEX1_END =
>+		TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
>+	/* TCC range 2*/
>+	TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
>+	TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START,
>+	TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
>+	TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
>+	TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
>+	TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
>+	TA_RAS_BLOCK__GFX_TCC_SRC_FIFO,
>+	TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
>+	TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
>+	TA_RAS_BLOCK__GFX_TCC_INDEX2_END =
>+		TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
>+	/* TCC range 3*/
>+	TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
>+	TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START,
>+	TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
>+	TA_RAS_BLOCK__GFX_TCC_INDEX3_END =
>+		TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
>+	/* TCC range 4*/
>+	TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
>+	TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
>+		TA_RAS_BLOCK__GFX_TCC_INDEX4_START,
>+	TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
>+	TA_RAS_BLOCK__GFX_TCC_INDEX4_END =
>+		TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
>+	TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END,
>+	/* TCI*/
>+	TA_RAS_BLOCK__GFX_TCI_WRITE_RAM,
>+	/* TCP*/
>+	TA_RAS_BLOCK__GFX_TCP_INDEX_START,
>+	TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START,
>+	TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
>+	TA_RAS_BLOCK__GFX_TCP_CMD_FIFO,
>+	TA_RAS_BLOCK__GFX_TCP_VM_FIFO,
>+	TA_RAS_BLOCK__GFX_TCP_DB_RAM,
>+	TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
>+	TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
>+	TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
>+	/* TD*/
>+	TA_RAS_BLOCK__GFX_TD_INDEX_START,
>+	TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START,
>+	TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
>+	TA_RAS_BLOCK__GFX_TD_CS_FIFO,
>+	TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO,
>+	/* EA (3 sub-ranges)*/
>+	TA_RAS_BLOCK__GFX_EA_INDEX_START,
>+	/* EA range 0*/
>+	TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START,
>+	TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START,
>+	TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
>+	TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
>+	TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
>+	TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
>+	TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
>+	TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
>+	TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
>+	TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
>+	/* EA range 1*/
>+	TA_RAS_BLOCK__GFX_EA_INDEX1_START,
>+	TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START,
>+	TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
>+	TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
>+	TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
>+	TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
>+	TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
>+	TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
>+	TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
>+	/* EA range 2*/
>+	TA_RAS_BLOCK__GFX_EA_INDEX2_START,
>+	TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START,
>+	TA_RAS_BLOCK__GFX_EA_MAM_D1MEM,
>+	TA_RAS_BLOCK__GFX_EA_MAM_D2MEM,
>+	TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
>+	TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM,
>+	TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END,
>+	/* UTC VM L2 bank*/
>+	TA_RAS_BLOCK__UTC_VML2_BANK_CACHE,
>+	/* UTC VM walker*/
>+	TA_RAS_BLOCK__UTC_VML2_WALKER,
>+	/* UTC ATC L2 2MB cache*/
>+	TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
>+	/* UTC ATC L2 4KB cache*/
>+	TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
>+	TA_RAS_BLOCK__GFX_MAX
>+};
>+
>+struct ras_gfx_subblock {
>+	unsigned char *name;
>+	int ta_subblock;
>+	int hw_supported_error_type;
>+	int sw_supported_error_type;
>+};
>+
>+#define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h)                             \
>+	[AMDGPU_RAS_BLOCK__##subblock] = {                                     \
>+		#subblock,                                                     \
>+		TA_RAS_BLOCK__##subblock,                                      \
>+		((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)),                  \
>+		(((e) << 1) | ((f) << 3) | (g) | ((h) << 2)),                  \
>+	}
>+
>+static const struct ras_gfx_subblock ras_gfx_subblocks[] = {
>+	AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
>+			     0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
>+			     0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
>+			     0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
>+			     1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
>+			     0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
>+			     0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
>+			     0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
>+			     0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0,
>+			     1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0,
>+			     1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0,
>+			     1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0,
>+			     0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0,
>+			     0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0),
>+	AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0),
>+};
>+
> static const struct soc15_reg_golden golden_settings_gc_9_0[] =
> {
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
>@@ -227,6 +621,22 @@
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
> };
> 
>+static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] =
>+{
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc),
>+};
>+
> static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
> {
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff),
>@@ -271,6 +681,18 @@
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00000000, 0x00008000)
> };
> 
>+static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
>+{
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
>+};
>+
> static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
> {
> 	mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
>@@ -310,19 +732,21 @@
> static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
> static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
> static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
>+static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
>+					  void *ras_error_status);
>+static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
>+				     void *inject_if);
> 
> static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
> {
> 	switch (adev->asic_type) {
> 	case CHIP_VEGA10:
>-		if (!amdgpu_virt_support_skip_setting(adev)) {
>-			soc15_program_register_sequence(adev,
>-							 golden_settings_gc_9_0,
>-							 ARRAY_SIZE(golden_settings_gc_9_0));
>-			soc15_program_register_sequence(adev,
>-							 golden_settings_gc_9_0_vg10,
>-							 ARRAY_SIZE(golden_settings_gc_9_0_vg10));
>-		}
>+		soc15_program_register_sequence(adev,
>+						golden_settings_gc_9_0,
>+						ARRAY_SIZE(golden_settings_gc_9_0));
>+		soc15_program_register_sequence(adev,
>+						golden_settings_gc_9_0_vg10,
>+						ARRAY_SIZE(golden_settings_gc_9_0_vg10));
> 		break;
> 	case CHIP_VEGA12:
> 		soc15_program_register_sequence(adev,
>@@ -340,6 +764,11 @@
> 						golden_settings_gc_9_0_vg20,
> 						ARRAY_SIZE(golden_settings_gc_9_0_vg20));
> 		break;
>+	case CHIP_ARCTURUS:
>+		soc15_program_register_sequence(adev,
>+						golden_settings_gc_9_4_1_arct,
>+						ARRAY_SIZE(golden_settings_gc_9_4_1_arct));
>+		break;
> 	case CHIP_RAVEN:
> 		soc15_program_register_sequence(adev, golden_settings_gc_9_1,
> 						ARRAY_SIZE(golden_settings_gc_9_1));
>@@ -352,12 +781,18 @@
> 							golden_settings_gc_9_1_rv1,
> 							ARRAY_SIZE(golden_settings_gc_9_1_rv1));
> 		break;
>+	 case CHIP_RENOIR:
>+		soc15_program_register_sequence(adev,
>+						golden_settings_gc_9_1_rn,
>+						ARRAY_SIZE(golden_settings_gc_9_1_rn));
>+		return; /* for renoir, don't need common goldensetting */
> 	default:
> 		break;
> 	}
> 
>-	soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
>-					(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
>+	if (adev->asic_type != CHIP_ARCTURUS)
>+		soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
>+						(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
> }
> 
> static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
>@@ -596,14 +1031,14 @@
> 	case CHIP_VEGA20:
> 		break;
> 	case CHIP_RAVEN:
>-		if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
>-			break;
>-		if ((adev->gfx.rlc_fw_version != 106 &&
>-		     adev->gfx.rlc_fw_version < 531) ||
>-		    (adev->gfx.rlc_fw_version == 53815) ||
>-		    (adev->gfx.rlc_feature_version < 1) ||
>-		    !adev->gfx.rlc.is_rlc_v2_1)
>+		if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
>+			&&((adev->gfx.rlc_fw_version != 106 &&
>+			     adev->gfx.rlc_fw_version < 531) ||
>+			    (adev->gfx.rlc_fw_version == 53815) ||
>+			    (adev->gfx.rlc_feature_version < 1) ||
>+			    !adev->gfx.rlc.is_rlc_v2_1))
> 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>+
> 		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
> 			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
> 				AMD_PG_SUPPORT_CP |
>@@ -614,44 +1049,14 @@
> 	}
> }
> 
>-static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
>+static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev,
>+					  const char *chip_name)
> {
>-	const char *chip_name;
> 	char fw_name[30];
> 	int err;
> 	struct amdgpu_firmware_info *info = NULL;
> 	const struct common_firmware_header *header = NULL;
> 	const struct gfx_firmware_header_v1_0 *cp_hdr;
>-	const struct rlc_firmware_header_v2_0 *rlc_hdr;
>-	unsigned int *tmp = NULL;
>-	unsigned int i = 0;
>-	uint16_t version_major;
>-	uint16_t version_minor;
>-	uint32_t smu_version;
>-
>-	DRM_DEBUG("\n");
>-
>-	switch (adev->asic_type) {
>-	case CHIP_VEGA10:
>-		chip_name = "vega10";
>-		break;
>-	case CHIP_VEGA12:
>-		chip_name = "vega12";
>-		break;
>-	case CHIP_VEGA20:
>-		chip_name = "vega20";
>-		break;
>-	case CHIP_RAVEN:
>-		if (adev->rev_id >= 8)
>-			chip_name = "raven2";
>-		else if (adev->pdev->device == 0x15d8)
>-			chip_name = "picasso";
>-		else
>-			chip_name = "raven";
>-		break;
>-	default:
>-		BUG();
>-	}
> 
> 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
> 	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
>@@ -686,6 +1091,58 @@
> 	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
> 	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
> 
>+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>+		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
>+		info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
>+		info->fw = adev->gfx.pfp_fw;
>+		header = (const struct common_firmware_header *)info->fw->data;
>+		adev->firmware.fw_size +=
>+			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
>+
>+		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
>+		info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
>+		info->fw = adev->gfx.me_fw;
>+		header = (const struct common_firmware_header *)info->fw->data;
>+		adev->firmware.fw_size +=
>+			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
>+
>+		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
>+		info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
>+		info->fw = adev->gfx.ce_fw;
>+		header = (const struct common_firmware_header *)info->fw->data;
>+		adev->firmware.fw_size +=
>+			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
>+	}
>+
>+out:
>+	if (err) {
>+		dev_err(adev->dev,
>+			"gfx9: Failed to load firmware \"%s\"\n",
>+			fw_name);
>+		release_firmware(adev->gfx.pfp_fw);
>+		adev->gfx.pfp_fw = NULL;
>+		release_firmware(adev->gfx.me_fw);
>+		adev->gfx.me_fw = NULL;
>+		release_firmware(adev->gfx.ce_fw);
>+		adev->gfx.ce_fw = NULL;
>+	}
>+	return err;
>+}
>+
>+static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
>+					  const char *chip_name)
>+{
>+	char fw_name[30];
>+	int err;
>+	struct amdgpu_firmware_info *info = NULL;
>+	const struct common_firmware_header *header = NULL;
>+	const struct rlc_firmware_header_v2_0 *rlc_hdr;
>+	unsigned int *tmp = NULL;
>+	unsigned int i = 0;
>+	uint16_t version_major;
>+	uint16_t version_minor;
>+	uint32_t smu_version;
>+
> 	/*
> 	 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
> 	 * instead of picasso_rlc.bin.
>@@ -760,57 +1217,7 @@
> 	if (adev->gfx.rlc.is_rlc_v2_1)
> 		gfx_v9_0_init_rlc_ext_microcode(adev);
> 
>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
>-	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
>-	if (err)
>-		goto out;
>-	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
>-	if (err)
>-		goto out;
>-	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
>-	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
>-	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
>-
>-
>-	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
>-	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
>-	if (!err) {
>-		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
>-		if (err)
>-			goto out;
>-		cp_hdr = (const struct gfx_firmware_header_v1_0 *)
>-		adev->gfx.mec2_fw->data;
>-		adev->gfx.mec2_fw_version =
>-		le32_to_cpu(cp_hdr->header.ucode_version);
>-		adev->gfx.mec2_feature_version =
>-		le32_to_cpu(cp_hdr->ucode_feature_version);
>-	} else {
>-		err = 0;
>-		adev->gfx.mec2_fw = NULL;
>-	}
>-
> 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>-		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
>-		info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
>-		info->fw = adev->gfx.pfp_fw;
>-		header = (const struct common_firmware_header *)info->fw->data;
>-		adev->firmware.fw_size +=
>-			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
>-
>-		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
>-		info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
>-		info->fw = adev->gfx.me_fw;
>-		header = (const struct common_firmware_header *)info->fw->data;
>-		adev->firmware.fw_size +=
>-			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
>-
>-		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
>-		info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
>-		info->fw = adev->gfx.ce_fw;
>-		header = (const struct common_firmware_header *)info->fw->data;
>-		adev->firmware.fw_size +=
>-			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
>-
> 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
> 		info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
> 		info->fw = adev->gfx.rlc_fw;
>@@ -840,7 +1247,58 @@
> 			adev->firmware.fw_size +=
> 				ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
> 		}
>+	}
> 
>+out:
>+	if (err) {
>+		dev_err(adev->dev,
>+			"gfx9: Failed to load firmware \"%s\"\n",
>+			fw_name);
>+		release_firmware(adev->gfx.rlc_fw);
>+		adev->gfx.rlc_fw = NULL;
>+	}
>+	return err;
>+}
>+
>+static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
>+					  const char *chip_name)
>+{
>+	char fw_name[30];
>+	int err;
>+	struct amdgpu_firmware_info *info = NULL;
>+	const struct common_firmware_header *header = NULL;
>+	const struct gfx_firmware_header_v1_0 *cp_hdr;
>+
>+	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
>+	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
>+	if (err)
>+		goto out;
>+	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
>+	if (err)
>+		goto out;
>+	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
>+	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
>+	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
>+
>+
>+	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
>+	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
>+	if (!err) {
>+		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
>+		if (err)
>+			goto out;
>+		cp_hdr = (const struct gfx_firmware_header_v1_0 *)
>+		adev->gfx.mec2_fw->data;
>+		adev->gfx.mec2_fw_version =
>+		le32_to_cpu(cp_hdr->header.ucode_version);
>+		adev->gfx.mec2_feature_version =
>+		le32_to_cpu(cp_hdr->ucode_feature_version);
>+	} else {
>+		err = 0;
>+		adev->gfx.mec2_fw = NULL;
>+	}
>+
>+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
> 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
> 		info->fw = adev->gfx.mec_fw;
>@@ -863,13 +1321,18 @@
> 			cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
> 			adev->firmware.fw_size +=
> 				ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
>-			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
>-			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
>-			info->fw = adev->gfx.mec2_fw;
>-			adev->firmware.fw_size +=
>-				ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
>-		}
> 
>+			/* TODO: Determine if MEC2 JT FW loading can be removed
>+				 for all GFX V9 asic and above */
>+			if (adev->asic_type != CHIP_ARCTURUS) {
>+				info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
>+				info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
>+				info->fw = adev->gfx.mec2_fw;
>+				adev->firmware.fw_size +=
>+					ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
>+					PAGE_SIZE);
>+			}
>+		}
> 	}
> 
> out:
>@@ -879,14 +1342,6 @@
> 		dev_err(adev->dev,
> 			"gfx9: Failed to load firmware \"%s\"\n",
> 			fw_name);
>-		release_firmware(adev->gfx.pfp_fw);
>-		adev->gfx.pfp_fw = NULL;
>-		release_firmware(adev->gfx.me_fw);
>-		adev->gfx.me_fw = NULL;
>-		release_firmware(adev->gfx.ce_fw);
>-		adev->gfx.ce_fw = NULL;
>-		release_firmware(adev->gfx.rlc_fw);
>-		adev->gfx.rlc_fw = NULL;
> 		release_firmware(adev->gfx.mec_fw);
> 		adev->gfx.mec_fw = NULL;
> 		release_firmware(adev->gfx.mec2_fw);
>@@ -895,6 +1350,59 @@
> 	return err;
> }
> 
>+static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
>+{
>+	const char *chip_name;
>+	int r;
>+
>+	DRM_DEBUG("\n");
>+
>+	switch (adev->asic_type) {
>+	case CHIP_VEGA10:
>+		chip_name = "vega10";
>+		break;
>+	case CHIP_VEGA12:
>+		chip_name = "vega12";
>+		break;
>+	case CHIP_VEGA20:
>+		chip_name = "vega20";
>+		break;
>+	case CHIP_RAVEN:
>+		if (adev->rev_id >= 8)
>+			chip_name = "raven2";
>+		else if (adev->pdev->device == 0x15d8)
>+			chip_name = "picasso";
>+		else
>+			chip_name = "raven";
>+		break;
>+	case CHIP_ARCTURUS:
>+		chip_name = "arcturus";
>+		break;
>+	case CHIP_RENOIR:
>+		chip_name = "renoir";
>+		break;
>+	default:
>+		BUG();
>+	}
>+
>+	/* No CPG in Arcturus */
>+	if (adev->asic_type != CHIP_ARCTURUS) {
>+		r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name);
>+		if (r)
>+			return r;
>+	}
>+
>+	r = gfx_v9_0_init_rlc_microcode(adev, chip_name);
>+	if (r)
>+		return r;
>+
>+	r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name);
>+	if (r)
>+		return r;
>+
>+	return r;
>+}
>+
> static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
> {
> 	u32 count = 0;
>@@ -1132,7 +1640,7 @@
> 			return r;
> 	}
> 
>-	if (adev->asic_type == CHIP_RAVEN) {
>+	if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) {
> 		/* TODO: double check the cp_table_size for RV */
> 		adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
> 		r = amdgpu_gfx_rlc_init_cpt(adev);
>@@ -1142,6 +1650,7 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_RAVEN:
>+	case CHIP_RENOIR:
> 		gfx_v9_0_init_lbpw(adev);
> 		break;
> 	case CHIP_VEGA20:
>@@ -1328,7 +1837,9 @@
> 	.read_wave_data = &gfx_v9_0_read_wave_data,
> 	.read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
> 	.read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
>-	.select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
>+	.select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
>+	.ras_error_inject = &gfx_v9_0_ras_error_inject,
>+	.query_ras_error_count = &gfx_v9_0_query_ras_error_count
> };
> 
> static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
>@@ -1381,6 +1892,26 @@
> 		else
> 			gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
> 		break;
>+	case CHIP_ARCTURUS:
>+		adev->gfx.config.max_hw_contexts = 8;
>+		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
>+		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
>+		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
>+		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
>+		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
>+		gb_addr_config &= ~0xf3e777ff;
>+		gb_addr_config |= 0x22014042;
>+		break;
>+	case CHIP_RENOIR:
>+		adev->gfx.config.max_hw_contexts = 8;
>+		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
>+		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
>+		adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
>+		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
>+		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
>+		gb_addr_config &= ~0xf3e777ff;
>+		gb_addr_config |= 0x22010042;
>+		break;
> 	default:
> 		BUG();
> 		break;
>@@ -1657,6 +2188,8 @@
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
> 	case CHIP_RAVEN:
>+	case CHIP_ARCTURUS:
>+	case CHIP_RENOIR:
> 		adev->gfx.mec.num_mec = 2;
> 		break;
> 	default:
>@@ -1814,7 +2347,7 @@
> 	gfx_v9_0_mec_fini(adev);
> 	gfx_v9_0_ngg_fini(adev);
> 	amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
>-	if (adev->asic_type == CHIP_RAVEN) {
>+	if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) {
> 		amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
> 				&adev->gfx.rlc.cp_table_gpu_addr,
> 				(void **)&adev->gfx.rlc.cp_table_ptr);
>@@ -1933,6 +2466,24 @@
> 	}
> }
> 
>+static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
>+{
>+	int vmid;
>+
>+	/*
>+	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
>+	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
>+	 * the driver can enable them for graphics. VMID0 should maintain
>+	 * access so that HWS firmware can save/restore entries.
>+	 */
>+	for (vmid = 1; vmid < 16; vmid++) {
>+		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
>+		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
>+		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
>+		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
>+	}
>+}
>+
> static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
> {
> 	u32 tmp;
>@@ -1949,7 +2500,7 @@
> 	/* XXX SH_MEM regs */
> 	/* where to put LDS, scratch, GPUVM in FSA64 space */
> 	mutex_lock(&adev->srbm_mutex);
>-	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
>+	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
> 		soc15_grbm_select(adev, 0, 0, 0, i);
> 		/* CP and shaders */
> 		if (i == 0) {
>@@ -1977,6 +2528,7 @@
> 	mutex_unlock(&adev->srbm_mutex);
> 
> 	gfx_v9_0_init_compute_vmid(adev);
>+	gfx_v9_0_init_gds_vmid(adev);
> }
> 
> static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
>@@ -2474,6 +3026,7 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_RAVEN:
>+	case CHIP_RENOIR:
> 		if (amdgpu_lbpw == 0)
> 			gfx_v9_0_enable_lbpw(adev, false);
> 		else
>@@ -2853,6 +3406,10 @@
> 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
> 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
> 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
>+	mqd->compute_static_thread_mgmt_se4 = 0xffffffff;
>+	mqd->compute_static_thread_mgmt_se5 = 0xffffffff;
>+	mqd->compute_static_thread_mgmt_se6 = 0xffffffff;
>+	mqd->compute_static_thread_mgmt_se7 = 0xffffffff;
> 	mqd->compute_misc_reserved = 0x00000003;
> 
> 	mqd->dynamic_cu_mask_addr_lo =
>@@ -3256,10 +3813,12 @@
> 		gfx_v9_0_enable_gui_idle_interrupt(adev, false);
> 
> 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
>-		/* legacy firmware loading */
>-		r = gfx_v9_0_cp_gfx_load_microcode(adev);
>-		if (r)
>-			return r;
>+		if (adev->asic_type != CHIP_ARCTURUS) {
>+			/* legacy firmware loading */
>+			r = gfx_v9_0_cp_gfx_load_microcode(adev);
>+			if (r)
>+				return r;
>+		}
> 
> 		r = gfx_v9_0_cp_compute_load_microcode(adev);
> 		if (r)
>@@ -3270,18 +3829,22 @@
> 	if (r)
> 		return r;
> 
>-	r = gfx_v9_0_cp_gfx_resume(adev);
>-	if (r)
>-		return r;
>+	if (adev->asic_type != CHIP_ARCTURUS) {
>+		r = gfx_v9_0_cp_gfx_resume(adev);
>+		if (r)
>+			return r;
>+	}
> 
> 	r = gfx_v9_0_kcq_resume(adev);
> 	if (r)
> 		return r;
> 
>-	ring = &adev->gfx.gfx_ring[0];
>-	r = amdgpu_ring_test_helper(ring);
>-	if (r)
>-		return r;
>+	if (adev->asic_type != CHIP_ARCTURUS) {
>+		ring = &adev->gfx.gfx_ring[0];
>+		r = amdgpu_ring_test_helper(ring);
>+		if (r)
>+			return r;
>+	}
> 
> 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> 		ring = &adev->gfx.compute_ring[i];
>@@ -3295,7 +3858,8 @@
> 
> static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
> {
>-	gfx_v9_0_cp_gfx_enable(adev, enable);
>+	if (adev->asic_type != CHIP_ARCTURUS)
>+		gfx_v9_0_cp_gfx_enable(adev, enable);
> 	gfx_v9_0_cp_compute_enable(adev, enable);
> }
> 
>@@ -3304,7 +3868,8 @@
> 	int r;
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
>-	gfx_v9_0_init_golden_registers(adev);
>+	if (!amdgpu_sriov_vf(adev))
>+		gfx_v9_0_init_golden_registers(adev);
> 
> 	gfx_v9_0_constants_init(adev);
> 
>@@ -3320,9 +3885,11 @@
> 	if (r)
> 		return r;
> 
>-	r = gfx_v9_0_ngg_en(adev);
>-	if (r)
>-		return r;
>+	if (adev->asic_type != CHIP_ARCTURUS) {
>+		r = gfx_v9_0_ngg_en(adev);
>+		if (r)
>+			return r;
>+	}
> 
> 	return r;
> }
>@@ -3470,8 +4037,9 @@
> 		/* stop the rlc */
> 		adev->gfx.rlc.funcs->stop(adev);
> 
>-		/* Disable GFX parsing/prefetching */
>-		gfx_v9_0_cp_gfx_enable(adev, false);
>+		if (adev->asic_type != CHIP_ARCTURUS)
>+			/* Disable GFX parsing/prefetching */
>+			gfx_v9_0_cp_gfx_enable(adev, false);
> 
> 		/* Disable MEC parsing/prefetching */
> 		gfx_v9_0_cp_compute_enable(adev, false);
>@@ -3814,7 +4382,10 @@
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
>-	adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
>+	if (adev->asic_type == CHIP_ARCTURUS)
>+		adev->gfx.num_gfx_rings = 0;
>+	else
>+		adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
> 	adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
> 	gfx_v9_0_set_ring_funcs(adev);
> 	gfx_v9_0_set_irq_funcs(adev);
>@@ -3825,6 +4396,7 @@
> }
> 
> static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
>+		struct ras_err_data *err_data,
> 		struct amdgpu_iv_entry *entry);
> 
> static int gfx_v9_0_ecc_late_init(void *handle)
>@@ -3990,6 +4562,9 @@
> {
> 	amdgpu_gfx_rlc_enter_safe_mode(adev);
> 
>+	if (is_support_sw_smu(adev) && !enable)
>+		smu_set_gfx_cgpg(&adev->smu, enable);
>+
> 	if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
> 		gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
> 		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
>@@ -4101,6 +4676,9 @@
> {
> 	uint32_t data, def;
> 
>+	if (adev->asic_type == CHIP_ARCTURUS)
>+		return;
>+
> 	amdgpu_gfx_rlc_enter_safe_mode(adev);
> 
> 	/* Enable 3D CGCG/CGLS */
>@@ -4166,8 +4744,12 @@
> 		/* enable cgcg FSM(0x0000363F) */
> 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
> 
>-		data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>-			RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
>+		if (adev->asic_type == CHIP_ARCTURUS)
>+			data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>+				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
>+		else
>+			data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>+				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
> 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
> 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
> 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
>@@ -4239,6 +4821,7 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_RAVEN:
>+	case CHIP_RENOIR:
> 		if (!enable) {
> 			amdgpu_gfx_off_ctrl(adev, false);
> 			cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
>@@ -4257,6 +4840,8 @@
> 			gfx_v9_0_enable_cp_power_gating(adev, false);
> 
> 		/* update gfx cgpg state */
>+		if (is_support_sw_smu(adev) && enable)
>+			smu_set_gfx_cgpg(&adev->smu, enable);
> 		gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
> 
> 		/* update mgcg state */
>@@ -4293,6 +4878,8 @@
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
> 	case CHIP_RAVEN:
>+	case CHIP_ARCTURUS:
>+	case CHIP_RENOIR:
> 		gfx_v9_0_update_gfx_clock_gating(adev,
> 						 state == AMD_CG_STATE_GATE ? true : false);
> 		break;
>@@ -4334,14 +4921,16 @@
> 	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
> 		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
> 
>-	/* AMD_CG_SUPPORT_GFX_3D_CGCG */
>-	data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
>-	if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
>-		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
>-
>-	/* AMD_CG_SUPPORT_GFX_3D_CGLS */
>-	if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
>-		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
>+	if (adev->asic_type != CHIP_ARCTURUS) {
>+		/* AMD_CG_SUPPORT_GFX_3D_CGCG */
>+		data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
>+		if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
>+			*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
>+
>+		/* AMD_CG_SUPPORT_GFX_3D_CGLS */
>+		if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
>+			*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
>+	}
> }
> 
> static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
>@@ -5137,12 +5726,423 @@
> }
> 
> static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
>+		struct ras_err_data *err_data,
> 		struct amdgpu_iv_entry *entry)
> {
> 	/* TODO ue will trigger an interrupt. */
> 	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
>+	if (adev->gfx.funcs->query_ras_error_count)
>+		adev->gfx.funcs->query_ras_error_count(adev, err_data);
> 	amdgpu_ras_reset_gpu(adev, 0);
>-	return AMDGPU_RAS_UE;
>+	return AMDGPU_RAS_SUCCESS;
>+}
>+
>+static const struct {
>+	const char *name;
>+	uint32_t ip;
>+	uint32_t inst;
>+	uint32_t seg;
>+	uint32_t reg_offset;
>+	uint32_t per_se_instance;
>+	int32_t num_instance;
>+	uint32_t sec_count_mask;
>+	uint32_t ded_count_mask;
>+} gfx_ras_edc_regs[] = {
>+	{ "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1,
>+	  REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
>+	  REG_FIELD_MASK(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
>+	{ "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1,
>+	  REG_FIELD_MASK(CPC_EDC_UCODE_CNT, SEC_COUNT),
>+	  REG_FIELD_MASK(CPC_EDC_UCODE_CNT, DED_COUNT) },
>+	{ "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1,
>+	  REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME1), 0 },
>+	{ "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1,
>+	  REG_FIELD_MASK(CPF_EDC_ROQ_CNT, COUNT_ME2), 0 },
>+	{ "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1,
>+	  REG_FIELD_MASK(CPF_EDC_TAG_CNT, SEC_COUNT),
>+	  REG_FIELD_MASK(CPF_EDC_TAG_CNT, DED_COUNT) },
>+	{ "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1,
>+	  REG_FIELD_MASK(CPG_EDC_DMA_CNT, ROQ_COUNT), 0 },
>+	{ "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1,
>+	  REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_SEC_COUNT),
>+	  REG_FIELD_MASK(CPG_EDC_DMA_CNT, TAG_DED_COUNT) },
>+	{ "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1,
>+	  REG_FIELD_MASK(CPG_EDC_TAG_CNT, SEC_COUNT),
>+	  REG_FIELD_MASK(CPG_EDC_TAG_CNT, DED_COUNT) },
>+	{ "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1,
>+	  REG_FIELD_MASK(DC_EDC_CSINVOC_CNT, COUNT_ME1), 0 },
>+	{ "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1,
>+	  REG_FIELD_MASK(DC_EDC_RESTORE_CNT, COUNT_ME1), 0 },
>+	{ "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1,
>+	  REG_FIELD_MASK(DC_EDC_STATE_CNT, COUNT_ME1), 0 },
>+	{ "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1,
>+	  REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_SEC),
>+	  REG_FIELD_MASK(GDS_EDC_CNT, GDS_MEM_DED) },
>+	{ "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1,
>+	  REG_FIELD_MASK(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 0 },
>+	{ "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
>+	  0, 1, REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
>+	  REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) },
>+	{ "GDS_OA_PHY_PHY_CMD_RAM_MEM",
>+	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1,
>+	  REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
>+	  REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) },
>+	{ "GDS_OA_PHY_PHY_DATA_RAM_MEM",
>+	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1,
>+	  REG_FIELD_MASK(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 0 },
>+	{ "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM",
>+	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
>+	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
>+	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) },
>+	{ "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM",
>+	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
>+	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
>+	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) },
>+	{ "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM",
>+	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
>+	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
>+	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) },
>+	{ "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM",
>+	  SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1,
>+	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
>+	  REG_FIELD_MASK(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) },
>+	{ "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 1, 1,
>+	  REG_FIELD_MASK(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 0 },
>+	{ "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
>+	  REG_FIELD_MASK(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) },
>+	{ "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 0 },
>+	{ "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 0 },
>+	{ "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 0 },
>+	{ "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 0 },
>+	{ "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2,
>+	  REG_FIELD_MASK(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 0 },
>+	{ "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 2,
>+	  REG_FIELD_MASK(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 0 },
>+	{ "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
>+	  REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) },
>+	{ "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
>+	  REG_FIELD_MASK(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) },
>+	{ "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
>+	  REG_FIELD_MASK(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) },
>+	{ "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
>+	  REG_FIELD_MASK(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) },
>+	{ "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
>+	  REG_FIELD_MASK(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) },
>+	{ "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 0 },
>+	{ "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 0 },
>+	{ "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 0 },
>+	{ "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 0 },
>+	{ "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 0 },
>+	{ "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 0 },
>+	{ "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 0 },
>+	{ "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 16,
>+	  REG_FIELD_MASK(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 0 },
>+	{ "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
>+	  16, REG_FIELD_MASK(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 0 },
>+	{ "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
>+	  0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT),
>+	  0 },
>+	{ "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
>+	  16, REG_FIELD_MASK(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 0 },
>+	{ "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
>+	  0, 16, REG_FIELD_MASK(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT),
>+	  0 },
>+	{ "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0,
>+	  16, REG_FIELD_MASK(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 0 },
>+	{ "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 72,
>+	  REG_FIELD_MASK(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 0 },
>+	{ "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
>+	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
>+	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) },
>+	{ "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
>+	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
>+	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) },
>+	{ "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
>+	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 0 },
>+	{ "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
>+	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 0 },
>+	{ "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
>+	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 0 },
>+	{ "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
>+	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
>+	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) },
>+	{ "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 1, 16,
>+	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
>+	  REG_FIELD_MASK(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) },
>+	{ "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
>+	  REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) },
>+	{ "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
>+	  REG_FIELD_MASK(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) },
>+	{ "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(TD_EDC_CNT, CS_FIFO_SED_COUNT), 0 },
>+	{ "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_SEC_COUNT),
>+	  REG_FIELD_MASK(SQ_EDC_CNT, LDS_D_DED_COUNT) },
>+	{ "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_SEC_COUNT),
>+	  REG_FIELD_MASK(SQ_EDC_CNT, LDS_I_DED_COUNT) },
>+	{ "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(SQ_EDC_CNT, SGPR_SEC_COUNT),
>+	  REG_FIELD_MASK(SQ_EDC_CNT, SGPR_DED_COUNT) },
>+	{ "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_SEC_COUNT),
>+	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR0_DED_COUNT) },
>+	{ "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_SEC_COUNT),
>+	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR1_DED_COUNT) },
>+	{ "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_SEC_COUNT),
>+	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR2_DED_COUNT) },
>+	{ "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 1, 16,
>+	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_SEC_COUNT),
>+	  REG_FIELD_MASK(SQ_EDC_CNT, VGPR3_DED_COUNT) },
>+	{ "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
>+	  1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) },
>+	{ "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) },
>+	{ "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
>+	  1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) },
>+	{ "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) },
>+	{ "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
>+	  1, 6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) },
>+	{ "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) },
>+	{ "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) },
>+	{ "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) },
>+	{ "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) },
>+	{ "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) },
>+	{ "SQC_INST_BANKA_UTCL1_MISS_FIFO",
>+	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
>+	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT),
>+	  0 },
>+	{ "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 0 },
>+	{ "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 0 },
>+	{ "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 0 },
>+	{ "SQC_DATA_BANKA_DIRTY_BIT_RAM",
>+	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
>+	  REG_FIELD_MASK(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 0 },
>+	{ "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 1, 6,
>+	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) },
>+	{ "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) },
>+	{ "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) },
>+	{ "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) },
>+	{ "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
>+	  REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) },
>+	{ "SQC_INST_BANKB_UTCL1_MISS_FIFO",
>+	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6,
>+	  REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT),
>+	  0 },
>+	{ "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 0 },
>+	{ "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 0 },
>+	{ "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1,
>+	  6, REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 0 },
>+	{ "SQC_DATA_BANKB_DIRTY_BIT_RAM",
>+	  SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 1, 6,
>+	  REG_FIELD_MASK(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 0 },
>+	{ "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) },
>+	{ "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) },
>+	{ "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) },
>+	{ "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) },
>+	{ "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) },
>+	{ "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0 },
>+	{ "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0 },
>+	{ "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0 },
>+	{ "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0 },
>+	{ "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 0 },
>+	{ "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
>+	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) },
>+	{ "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
>+	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) },
>+	{ "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
>+	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) },
>+	{ "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0 },
>+	{ "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0 },
>+	{ "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 0 },
>+	{ "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 0 },
>+	{ "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 0 },
>+	{ "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 32,
>+	  REG_FIELD_MASK(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 0 },
>+};
>+
>+static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
>+				     void *inject_if)
>+{
>+	struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
>+	int ret;
>+	struct ta_ras_trigger_error_input block_info = { 0 };
>+
>+	if (adev->asic_type != CHIP_VEGA20)
>+		return -EINVAL;
>+
>+	if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks))
>+		return -EINVAL;
>+
>+	if (!ras_gfx_subblocks[info->head.sub_block_index].name)
>+		return -EPERM;
>+
>+	if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type &
>+	      info->head.type)) {
>+		DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n",
>+			ras_gfx_subblocks[info->head.sub_block_index].name,
>+			info->head.type);
>+		return -EPERM;
>+	}
>+
>+	if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type &
>+	      info->head.type)) {
>+		DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n",
>+			ras_gfx_subblocks[info->head.sub_block_index].name,
>+			info->head.type);
>+		return -EPERM;
>+	}
>+
>+	block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
>+	block_info.sub_block_index =
>+		ras_gfx_subblocks[info->head.sub_block_index].ta_subblock;
>+	block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
>+	block_info.address = info->address;
>+	block_info.value = info->value;
>+
>+	mutex_lock(&adev->grbm_idx_mutex);
>+	ret = psp_ras_trigger_error(&adev->psp, &block_info);
>+	mutex_unlock(&adev->grbm_idx_mutex);
>+
>+	return ret;
>+}
>+
>+static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
>+					  void *ras_error_status)
>+{
>+	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
>+	uint32_t sec_count, ded_count;
>+	uint32_t i;
>+	uint32_t reg_value;
>+	uint32_t se_id, instance_id;
>+
>+	if (adev->asic_type != CHIP_VEGA20)
>+		return -EINVAL;
>+
>+	err_data->ue_count = 0;
>+	err_data->ce_count = 0;
>+
>+	mutex_lock(&adev->grbm_idx_mutex);
>+	for (se_id = 0; se_id < adev->gfx.config.max_shader_engines; se_id++) {
>+		for (instance_id = 0; instance_id < 256; instance_id++) {
>+			for (i = 0;
>+			     i < sizeof(gfx_ras_edc_regs) / sizeof(gfx_ras_edc_regs[0]);
>+			     i++) {
>+				if (se_id != 0 &&
>+				    !gfx_ras_edc_regs[i].per_se_instance)
>+					continue;
>+				if (instance_id >= gfx_ras_edc_regs[i].num_instance)
>+					continue;
>+
>+				gfx_v9_0_select_se_sh(adev, se_id, 0,
>+						      instance_id);
>+
>+				reg_value = RREG32(
>+					adev->reg_offset[gfx_ras_edc_regs[i].ip]
>+							[gfx_ras_edc_regs[i].inst]
>+							[gfx_ras_edc_regs[i].seg] +
>+					gfx_ras_edc_regs[i].reg_offset);
>+				sec_count = reg_value &
>+					    gfx_ras_edc_regs[i].sec_count_mask;
>+				ded_count = reg_value &
>+					    gfx_ras_edc_regs[i].ded_count_mask;
>+				if (sec_count) {
>+					DRM_INFO(
>+						"Instance[%d][%d]: SubBlock %s, SEC %d\n",
>+						se_id, instance_id,
>+						gfx_ras_edc_regs[i].name,
>+						sec_count);
>+					err_data->ce_count++;
>+				}
>+
>+				if (ded_count) {
>+					DRM_INFO(
>+						"Instance[%d][%d]: SubBlock %s, DED %d\n",
>+						se_id, instance_id,
>+						gfx_ras_edc_regs[i].name,
>+						ded_count);
>+					err_data->ue_count++;
>+				}
>+			}
>+		}
>+	}
>+	gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
>+	mutex_unlock(&adev->grbm_idx_mutex);
>+
>+	return 0;
> }
> 
> static int gfx_v9_0_cp_ecc_error_irq(struct amdgpu_device *adev,
>@@ -5187,7 +6187,7 @@
> 	.align_mask = 0xff,
> 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
> 	.support_64bit_ptrs = true,
>-	.vmhub = AMDGPU_GFXHUB,
>+	.vmhub = AMDGPU_GFXHUB_0,
> 	.get_rptr = gfx_v9_0_ring_get_rptr_gfx,
> 	.get_wptr = gfx_v9_0_ring_get_wptr_gfx,
> 	.set_wptr = gfx_v9_0_ring_set_wptr_gfx,
>@@ -5238,7 +6238,7 @@
> 	.align_mask = 0xff,
> 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
> 	.support_64bit_ptrs = true,
>-	.vmhub = AMDGPU_GFXHUB,
>+	.vmhub = AMDGPU_GFXHUB_0,
> 	.get_rptr = gfx_v9_0_ring_get_rptr_compute,
> 	.get_wptr = gfx_v9_0_ring_get_wptr_compute,
> 	.set_wptr = gfx_v9_0_ring_set_wptr_compute,
>@@ -5273,7 +6273,7 @@
> 	.align_mask = 0xff,
> 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
> 	.support_64bit_ptrs = true,
>-	.vmhub = AMDGPU_GFXHUB,
>+	.vmhub = AMDGPU_GFXHUB_0,
> 	.get_rptr = gfx_v9_0_ring_get_rptr_compute,
> 	.get_wptr = gfx_v9_0_ring_get_wptr_compute,
> 	.set_wptr = gfx_v9_0_ring_set_wptr_compute,
>@@ -5353,6 +6353,8 @@
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
> 	case CHIP_RAVEN:
>+	case CHIP_ARCTURUS:
>+	case CHIP_RENOIR:
> 		adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
> 		break;
> 	default:
>@@ -5370,6 +6372,7 @@
> 		adev->gds.gds_size = 0x10000;
> 		break;
> 	case CHIP_RAVEN:
>+	case CHIP_ARCTURUS:
> 		adev->gds.gds_size = 0x1000;
> 		break;
> 	default:
>@@ -5391,6 +6394,9 @@
> 		else
> 			adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */
> 		break;
>+	case CHIP_ARCTURUS:
>+		adev->gds.gds_compute_max_wave_id = 0xfff;
>+		break;
> 	default:
> 		/* this really depends on the chip */
> 		adev->gds.gds_compute_max_wave_id = 0x7ff;
>@@ -5435,12 +6441,21 @@
> {
> 	int i, j, k, counter, active_cu_number = 0;
> 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
>-	unsigned disable_masks[4 * 2];
>+	unsigned disable_masks[4 * 4];
> 
> 	if (!adev || !cu_info)
> 		return -EINVAL;
> 
>-	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
>+	/*
>+	 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
>+	 */
>+	if (adev->gfx.config.max_shader_engines *
>+		adev->gfx.config.max_sh_per_se > 16)
>+		return -EINVAL;
>+
>+	amdgpu_gfx_parse_disable_cu(disable_masks,
>+				    adev->gfx.config.max_shader_engines,
>+				    adev->gfx.config.max_sh_per_se);
> 
> 	mutex_lock(&adev->grbm_idx_mutex);
> 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
>@@ -5449,11 +6464,23 @@
> 			ao_bitmap = 0;
> 			counter = 0;
> 			gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
>-			if (i < 4 && j < 2)
>-				gfx_v9_0_set_user_cu_inactive_bitmap(
>-					adev, disable_masks[i * 2 + j]);
>+			gfx_v9_0_set_user_cu_inactive_bitmap(
>+				adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
> 			bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
>-			cu_info->bitmap[i][j] = bitmap;
>+
>+			/*
>+			 * The bitmap(and ao_cu_bitmap) in cu_info structure is
>+			 * 4x4 size array, and it's usually suitable for Vega
>+			 * ASICs which has 4*2 SE/SH layout.
>+			 * But for Arcturus, SE/SH layout is changed to 8*1.
>+			 * To mostly reduce the impact, we make it compatible
>+			 * with current bitmap array as below:
>+			 *    SE4,SH0 --> bitmap[0][1]
>+			 *    SE5,SH0 --> bitmap[1][1]
>+			 *    SE6,SH0 --> bitmap[2][1]
>+			 *    SE7,SH0 --> bitmap[3][1]
>+			 */
>+			cu_info->bitmap[i % 4][j + i / 4] = bitmap;
> 
> 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
> 				if (bitmap & mask) {
>@@ -5466,7 +6493,7 @@
> 			active_cu_number += counter;
> 			if (i < 2 && j < 2)
> 				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
>-			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
>+			cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap;
> 		}
> 	}
> 	gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c	2019-08-31 15:01:11.848736167 -0500
>@@ -62,7 +62,7 @@
> 	struct amdgpu_vmhub *hub;
> 	u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i;
> 
>-	bits[AMDGPU_GFXHUB] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>+	bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> 		GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> 		GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> 		GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>@@ -70,7 +70,7 @@
> 		GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> 		GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
> 
>-	bits[AMDGPU_MMHUB] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>+	bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> 		MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> 		MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
> 		MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
>@@ -81,39 +81,39 @@
> 	switch (state) {
> 	case AMDGPU_IRQ_STATE_DISABLE:
> 		/* MM HUB */
>-		hub = &adev->vmhub[AMDGPU_MMHUB];
>+		hub = &adev->vmhub[AMDGPU_MMHUB_0];
> 		for (i = 0; i < 16; i++) {
> 			reg = hub->vm_context0_cntl + i;
> 			tmp = RREG32(reg);
>-			tmp &= ~bits[AMDGPU_MMHUB];
>+			tmp &= ~bits[AMDGPU_MMHUB_0];
> 			WREG32(reg, tmp);
> 		}
> 
> 		/* GFX HUB */
>-		hub = &adev->vmhub[AMDGPU_GFXHUB];
>+		hub = &adev->vmhub[AMDGPU_GFXHUB_0];
> 		for (i = 0; i < 16; i++) {
> 			reg = hub->vm_context0_cntl + i;
> 			tmp = RREG32(reg);
>-			tmp &= ~bits[AMDGPU_GFXHUB];
>+			tmp &= ~bits[AMDGPU_GFXHUB_0];
> 			WREG32(reg, tmp);
> 		}
> 		break;
> 	case AMDGPU_IRQ_STATE_ENABLE:
> 		/* MM HUB */
>-		hub = &adev->vmhub[AMDGPU_MMHUB];
>+		hub = &adev->vmhub[AMDGPU_MMHUB_0];
> 		for (i = 0; i < 16; i++) {
> 			reg = hub->vm_context0_cntl + i;
> 			tmp = RREG32(reg);
>-			tmp |= bits[AMDGPU_MMHUB];
>+			tmp |= bits[AMDGPU_MMHUB_0];
> 			WREG32(reg, tmp);
> 		}
> 
> 		/* GFX HUB */
>-		hub = &adev->vmhub[AMDGPU_GFXHUB];
>+		hub = &adev->vmhub[AMDGPU_GFXHUB_0];
> 		for (i = 0; i < 16; i++) {
> 			reg = hub->vm_context0_cntl + i;
> 			tmp = RREG32(reg);
>-			tmp |= bits[AMDGPU_GFXHUB];
>+			tmp |= bits[AMDGPU_GFXHUB_0];
> 			WREG32(reg, tmp);
> 		}
> 		break;
>@@ -136,22 +136,53 @@
> 	addr |= ((u64)entry->src_data[1] & 0xf) << 44;
> 
> 	if (!amdgpu_sriov_vf(adev)) {
>+		/*
>+		 * Issue a dummy read to wait for the status register to
>+		 * be updated to avoid reading an incorrect value due to
>+		 * the new fast GRBM interface.
>+		 */
>+		if (entry->vmid_src == AMDGPU_GFXHUB_0)
>+			RREG32(hub->vm_l2_pro_fault_status);
>+
> 		status = RREG32(hub->vm_l2_pro_fault_status);
> 		WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
> 	}
> 
> 	if (printk_ratelimit()) {
>+		struct amdgpu_task_info task_info;
>+
>+		memset(&task_info, 0, sizeof(struct amdgpu_task_info));
>+		amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
>+
> 		dev_err(adev->dev,
>-			"[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n",
>+			"[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
>+			"for process %s pid %d thread %s pid %d)\n",
> 			entry->vmid_src ? "mmhub" : "gfxhub",
> 			entry->src_id, entry->ring_id, entry->vmid,
>-			entry->pasid);
>-		dev_err(adev->dev, "  at page 0x%016llx from %d\n",
>+			entry->pasid, task_info.process_name, task_info.tgid,
>+			task_info.task_name, task_info.pid);
>+		dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
> 			addr, entry->client_id);
>-		if (!amdgpu_sriov_vf(adev))
>+		if (!amdgpu_sriov_vf(adev)) {
> 			dev_err(adev->dev,
>-				"VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
>+				"GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> 				status);
>+			dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
>+				REG_GET_FIELD(status,
>+				GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
>+			dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
>+				REG_GET_FIELD(status,
>+				GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
>+			dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
>+				REG_GET_FIELD(status,
>+				GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
>+			dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
>+				REG_GET_FIELD(status,
>+				GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
>+			dev_err(adev->dev, "\t RW: 0x%lx\n",
>+				REG_GET_FIELD(status,
>+				GCVM_L2_PROTECTION_FAULT_STATUS, RW));
>+		}
> 	}
> 
> 	return 0;
>@@ -206,6 +237,13 @@
> 
> 	WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
> 
>+	/*
>+	 * Issue a dummy read to wait for the ACK register to be cleared
>+	 * to avoid a false ACK due to the new fast GRBM interface.
>+	 */
>+	if (vmhub == AMDGPU_GFXHUB_0)
>+		RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
>+
> 	/* Wait for ACK with a delay.*/
> 	for (i = 0; i < adev->usec_timeout; i++) {
> 		tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
>@@ -230,8 +268,8 @@
>  *
>  * Flush the TLB for the requested page table.
>  */
>-static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev,
>-				    uint32_t vmid, uint32_t flush_type)
>+static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
>+					uint32_t vmhub, uint32_t flush_type)
> {
> 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
> 	struct dma_fence *fence;
>@@ -244,11 +282,18 @@
> 
> 	mutex_lock(&adev->mman.gtt_window_lock);
> 
>-	gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB, 0);
>+	if (vmhub == AMDGPU_MMHUB_0) {
>+		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
>+		mutex_unlock(&adev->mman.gtt_window_lock);
>+		return;
>+	}
>+
>+	BUG_ON(vmhub != AMDGPU_GFXHUB_0);
>+
> 	if (!adev->mman.buffer_funcs_enabled ||
> 	    !adev->ib_pool_ready ||
> 	    adev->in_gpu_reset) {
>-		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB, 0);
>+		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
> 		mutex_unlock(&adev->mman.gtt_window_lock);
> 		return;
> 	}
>@@ -313,7 +358,7 @@
> 	struct amdgpu_device *adev = ring->adev;
> 	uint32_t reg;
> 
>-	if (ring->funcs->vmhub == AMDGPU_GFXHUB)
>+	if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
> 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
> 	else
> 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
>@@ -524,6 +569,8 @@
> 	if (amdgpu_gart_size == -1) {
> 		switch (adev->asic_type) {
> 		case CHIP_NAVI10:
>+		case CHIP_NAVI14:
>+		case CHIP_NAVI12:
> 		default:
> 			adev->gmc.gart_size = 512ULL << 20;
> 			break;
>@@ -590,7 +637,6 @@
> static int gmc_v10_0_sw_init(void *handle)
> {
> 	int r;
>-	int dma_bits;
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
> 	gfxhub_v2_0_init(adev);
>@@ -601,9 +647,12 @@
> 	adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
>+		adev->num_vmhubs = 2;
> 		/*
> 		 * To fulfill 4-level page support,
>-		 * vm size is 256TB (48bit), maximum size of Navi10,
>+		 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
> 		 * block size 512 (9bit)
> 		 */
> 		amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
>@@ -637,26 +686,10 @@
> 	else
> 		adev->gmc.stolen_size = 9 * 1024 *1024;
> 
>-	/*
>-	 * Set DMA mask + need_dma32 flags.
>-	 * PCIE - can handle 44-bits.
>-	 * IGP - can handle 44-bits
>-	 * PCI - dma32 for legacy pci gart, 44 bits on navi10
>-	 */
>-	adev->need_dma32 = false;
>-	dma_bits = adev->need_dma32 ? 32 : 44;
>-
>-	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
>+	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
> 	if (r) {
>-		adev->need_dma32 = true;
>-		dma_bits = 32;
> 		printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
>-	}
>-
>-	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
>-	if (r) {
>-		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
>-		printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
>+		return r;
> 	}
> 
> 	r = gmc_v10_0_mc_init(adev);
>@@ -680,8 +713,8 @@
> 	 * amdgpu graphics/compute will use VMIDs 1-7
> 	 * amdkfd will use VMIDs 8-15
> 	 */
>-	adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
>-	adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
>+	adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
>+	adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
> 
> 	amdgpu_vm_manager_init(adev);
> 
>@@ -717,6 +750,8 @@
> {
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		break;
> 	default:
> 		break;
>@@ -766,7 +801,8 @@
> 
> 	gfxhub_v2_0_set_fault_enable_default(adev, value);
> 	mmhub_v2_0_set_fault_enable_default(adev, value);
>-	gmc_v10_0_flush_gpu_tlb(adev, 0, 0);
>+	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
>+	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
> 
> 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
> 		 (unsigned)(adev->gmc.gart_size >> 20),
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c	2019-08-31 15:01:11.848736167 -0500
>@@ -362,8 +362,8 @@
> 	return 0;
> }
> 
>-static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev,
>-				uint32_t vmid, uint32_t flush_type)
>+static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
>+					uint32_t vmhub, uint32_t flush_type)
> {
> 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
> }
>@@ -571,7 +571,7 @@
> 	else
> 		gmc_v6_0_set_fault_enable_default(adev, true);
> 
>-	gmc_v6_0_flush_gpu_tlb(adev, 0, 0);
>+	gmc_v6_0_flush_gpu_tlb(adev, 0, 0, 0);
> 	dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
> 		 (unsigned)(adev->gmc.gart_size >> 20),
> 		 (unsigned long long)table_addr);
>@@ -839,9 +839,10 @@
> static int gmc_v6_0_sw_init(void *handle)
> {
> 	int r;
>-	int dma_bits;
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
>+	adev->num_vmhubs = 1;
>+
> 	if (adev->flags & AMD_IS_APU) {
> 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
> 	} else {
>@@ -862,20 +863,12 @@
> 
> 	adev->gmc.mc_mask = 0xffffffffffULL;
> 
>-	adev->need_dma32 = false;
>-	dma_bits = adev->need_dma32 ? 32 : 40;
>-	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
>+	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
> 	if (r) {
>-		adev->need_dma32 = true;
>-		dma_bits = 32;
> 		dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
>+		return r;
> 	}
>-	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
>-	if (r) {
>-		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
>-		dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
>-	}
>-	adev->need_swiotlb = drm_need_swiotlb(dma_bits);
>+	adev->need_swiotlb = drm_need_swiotlb(44);
> 
> 	r = gmc_v6_0_init_microcode(adev);
> 	if (r) {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c	2019-08-31 15:01:11.848736167 -0500
>@@ -433,8 +433,8 @@
>  *
>  * Flush the TLB for the requested page table (CIK).
>  */
>-static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev,
>-				uint32_t vmid, uint32_t flush_type)
>+static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
>+					uint32_t vmhub, uint32_t flush_type)
> {
> 	/* bits 0-15 are the VM contexts0-15 */
> 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
>@@ -677,7 +677,7 @@
> 		WREG32(mmCHUB_CONTROL, tmp);
> 	}
> 
>-	gmc_v7_0_flush_gpu_tlb(adev, 0, 0);
>+	gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0);
> 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
> 		 (unsigned)(adev->gmc.gart_size >> 20),
> 		 (unsigned long long)table_addr);
>@@ -959,9 +959,10 @@
> static int gmc_v7_0_sw_init(void *handle)
> {
> 	int r;
>-	int dma_bits;
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
>+	adev->num_vmhubs = 1;
>+
> 	if (adev->flags & AMD_IS_APU) {
> 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
> 	} else {
>@@ -990,25 +991,12 @@
> 	 */
> 	adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
> 
>-	/* set DMA mask + need_dma32 flags.
>-	 * PCIE - can handle 40-bits.
>-	 * IGP - can handle 40-bits
>-	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
>-	 */
>-	adev->need_dma32 = false;
>-	dma_bits = adev->need_dma32 ? 32 : 40;
>-	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
>+	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
> 	if (r) {
>-		adev->need_dma32 = true;
>-		dma_bits = 32;
> 		pr_warn("amdgpu: No suitable DMA available\n");
>+		return r;
> 	}
>-	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
>-	if (r) {
>-		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
>-		pr_warn("amdgpu: No coherent DMA available\n");
>-	}
>-	adev->need_swiotlb = drm_need_swiotlb(dma_bits);
>+	adev->need_swiotlb = drm_need_swiotlb(40);
> 
> 	r = gmc_v7_0_init_microcode(adev);
> 	if (r) {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c	2019-08-31 15:01:11.848736167 -0500
>@@ -635,8 +635,8 @@
>  *
>  * Flush the TLB for the requested page table (VI).
>  */
>-static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev,
>-				uint32_t vmid, uint32_t flush_type)
>+static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
>+					uint32_t vmhub, uint32_t flush_type)
> {
> 	/* bits 0-15 are the VM contexts0-15 */
> 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
>@@ -921,7 +921,7 @@
> 	else
> 		gmc_v8_0_set_fault_enable_default(adev, true);
> 
>-	gmc_v8_0_flush_gpu_tlb(adev, 0, 0);
>+	gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0);
> 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
> 		 (unsigned)(adev->gmc.gart_size >> 20),
> 		 (unsigned long long)table_addr);
>@@ -1079,9 +1079,10 @@
> static int gmc_v8_0_sw_init(void *handle)
> {
> 	int r;
>-	int dma_bits;
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
>+	adev->num_vmhubs = 1;
>+
> 	if (adev->flags & AMD_IS_APU) {
> 		adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
> 	} else {
>@@ -1116,25 +1117,12 @@
> 	 */
> 	adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
> 
>-	/* set DMA mask + need_dma32 flags.
>-	 * PCIE - can handle 40-bits.
>-	 * IGP - can handle 40-bits
>-	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
>-	 */
>-	adev->need_dma32 = false;
>-	dma_bits = adev->need_dma32 ? 32 : 40;
>-	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
>+	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
> 	if (r) {
>-		adev->need_dma32 = true;
>-		dma_bits = 32;
> 		pr_warn("amdgpu: No suitable DMA available\n");
>+		return r;
> 	}
>-	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
>-	if (r) {
>-		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
>-		pr_warn("amdgpu: No coherent DMA available\n");
>-	}
>-	adev->need_swiotlb = drm_need_swiotlb(dma_bits);
>+	adev->need_swiotlb = drm_need_swiotlb(40);
> 
> 	r = gmc_v8_0_init_microcode(adev);
> 	if (r) {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c	2019-08-31 15:01:11.848736167 -0500
>@@ -47,7 +47,10 @@
> 
> #include "gfxhub_v1_0.h"
> #include "mmhub_v1_0.h"
>+#include "athub_v1_0.h"
> #include "gfxhub_v1_1.h"
>+#include "mmhub_v9_4.h"
>+#include "umc_v6_1.h"
> 
> #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
> 
>@@ -241,18 +244,30 @@
> }
> 
> static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
>+		struct ras_err_data *err_data,
> 		struct amdgpu_iv_entry *entry)
> {
> 	kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
>-	amdgpu_ras_reset_gpu(adev, 0);
>-	return AMDGPU_RAS_UE;
>+	if (adev->umc.funcs->query_ras_error_count)
>+		adev->umc.funcs->query_ras_error_count(adev, err_data);
>+	/* umc query_ras_error_address is also responsible for clearing
>+	 * error status
>+	 */
>+	if (adev->umc.funcs->query_ras_error_address)
>+		adev->umc.funcs->query_ras_error_address(adev, err_data);
>+
>+	/* only uncorrectable error needs gpu reset */
>+	if (err_data->ue_count)
>+		amdgpu_ras_reset_gpu(adev, 0);
>+
>+	return AMDGPU_RAS_SUCCESS;
> }
> 
> static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev,
> 		struct amdgpu_irq_src *source,
> 		struct amdgpu_iv_entry *entry)
> {
>-	struct ras_common_if *ras_if = adev->gmc.ras_if;
>+	struct ras_common_if *ras_if = adev->gmc.umc_ras_if;
> 	struct ras_dispatch_if ih_data = {
> 		.entry = entry,
> 	};
>@@ -284,7 +299,7 @@
> 
> 	switch (state) {
> 	case AMDGPU_IRQ_STATE_DISABLE:
>-		for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
>+		for (j = 0; j < adev->num_vmhubs; j++) {
> 			hub = &adev->vmhub[j];
> 			for (i = 0; i < 16; i++) {
> 				reg = hub->vm_context0_cntl + i;
>@@ -295,7 +310,7 @@
> 		}
> 		break;
> 	case AMDGPU_IRQ_STATE_ENABLE:
>-		for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
>+		for (j = 0; j < adev->num_vmhubs; j++) {
> 			hub = &adev->vmhub[j];
> 			for (i = 0; i < 16; i++) {
> 				reg = hub->vm_context0_cntl + i;
>@@ -315,10 +330,11 @@
> 				struct amdgpu_irq_src *source,
> 				struct amdgpu_iv_entry *entry)
> {
>-	struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
>+	struct amdgpu_vmhub *hub;
> 	bool retry_fault = !!(entry->src_data[1] & 0x80);
> 	uint32_t status = 0;
> 	u64 addr;
>+	char hub_name[10];
> 
> 	addr = (u64)entry->src_data[0] << 12;
> 	addr |= ((u64)entry->src_data[1] & 0xf) << 44;
>@@ -327,8 +343,27 @@
> 						    entry->timestamp))
> 		return 1; /* This also prevents sending it to KFD */
> 
>+	if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
>+		snprintf(hub_name, sizeof(hub_name), "mmhub0");
>+		hub = &adev->vmhub[AMDGPU_MMHUB_0];
>+	} else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
>+		snprintf(hub_name, sizeof(hub_name), "mmhub1");
>+		hub = &adev->vmhub[AMDGPU_MMHUB_1];
>+	} else {
>+		snprintf(hub_name, sizeof(hub_name), "gfxhub0");
>+		hub = &adev->vmhub[AMDGPU_GFXHUB_0];
>+	}
>+
> 	/* If it's the first fault for this address, process it normally */
> 	if (!amdgpu_sriov_vf(adev)) {
>+		/*
>+		 * Issue a dummy read to wait for the status register to
>+		 * be updated to avoid reading an incorrect value due to
>+		 * the new fast GRBM interface.
>+		 */
>+		if (entry->vmid_src == AMDGPU_GFXHUB_0)
>+			RREG32(hub->vm_l2_pro_fault_status);
>+
> 		status = RREG32(hub->vm_l2_pro_fault_status);
> 		WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
> 	}
>@@ -342,17 +377,33 @@
> 		dev_err(adev->dev,
> 			"[%s] %s page fault (src_id:%u ring:%u vmid:%u "
> 			"pasid:%u, for process %s pid %d thread %s pid %d)\n",
>-			entry->vmid_src ? "mmhub" : "gfxhub",
>-			retry_fault ? "retry" : "no-retry",
>+			hub_name, retry_fault ? "retry" : "no-retry",
> 			entry->src_id, entry->ring_id, entry->vmid,
> 			entry->pasid, task_info.process_name, task_info.tgid,
> 			task_info.task_name, task_info.pid);
>-		dev_err(adev->dev, "  in page starting at address 0x%016llx from %d\n",
>+		dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
> 			addr, entry->client_id);
>-		if (!amdgpu_sriov_vf(adev))
>+		if (!amdgpu_sriov_vf(adev)) {
> 			dev_err(adev->dev,
> 				"VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
> 				status);
>+			dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
>+				REG_GET_FIELD(status,
>+				VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
>+			dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
>+				REG_GET_FIELD(status,
>+				VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
>+			dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
>+				REG_GET_FIELD(status,
>+				VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
>+			dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
>+				REG_GET_FIELD(status,
>+				VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
>+			dev_err(adev->dev, "\t RW: 0x%lx\n",
>+				REG_GET_FIELD(status,
>+				VM_L2_PROTECTION_FAULT_STATUS, RW));
>+
>+		}
> 	}
> 
> 	return 0;
>@@ -413,44 +464,53 @@
>  *
>  * Flush the TLB for the requested page table using certain type.
>  */
>-static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
>-				uint32_t vmid, uint32_t flush_type)
>+static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
>+					uint32_t vmhub, uint32_t flush_type)
> {
> 	const unsigned eng = 17;
>-	unsigned i, j;
>+	u32 j, tmp;
>+	struct amdgpu_vmhub *hub;
> 
>-	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
>-		struct amdgpu_vmhub *hub = &adev->vmhub[i];
>-		u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
>+	BUG_ON(vmhub >= adev->num_vmhubs);
> 
>-		/* This is necessary for a HW workaround under SRIOV as well
>-		 * as GFXOFF under bare metal
>-		 */
>-		if (adev->gfx.kiq.ring.sched.ready &&
>-		    (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
>-		    !adev->in_gpu_reset) {
>-			uint32_t req = hub->vm_inv_eng0_req + eng;
>-			uint32_t ack = hub->vm_inv_eng0_ack + eng;
>-
>-			amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
>-							   1 << vmid);
>-			continue;
>-		}
>+	hub = &adev->vmhub[vmhub];
>+	tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type);
> 
>-		spin_lock(&adev->gmc.invalidate_lock);
>-		WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
>-		for (j = 0; j < adev->usec_timeout; j++) {
>-			tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
>-			if (tmp & (1 << vmid))
>-				break;
>-			udelay(1);
>-		}
>-		spin_unlock(&adev->gmc.invalidate_lock);
>-		if (j < adev->usec_timeout)
>-			continue;
>+	/* This is necessary for a HW workaround under SRIOV as well
>+	 * as GFXOFF under bare metal
>+	 */
>+	if (adev->gfx.kiq.ring.sched.ready &&
>+			(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
>+			!adev->in_gpu_reset) {
>+		uint32_t req = hub->vm_inv_eng0_req + eng;
>+		uint32_t ack = hub->vm_inv_eng0_ack + eng;
> 
>-		DRM_ERROR("Timeout waiting for VM flush ACK!\n");
>+		amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp,
>+				1 << vmid);
>+		return;
> 	}
>+
>+	spin_lock(&adev->gmc.invalidate_lock);
>+	WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
>+
>+	/*
>+	 * Issue a dummy read to wait for the ACK register to be cleared
>+	 * to avoid a false ACK due to the new fast GRBM interface.
>+	 */
>+	if (vmhub == AMDGPU_GFXHUB_0)
>+		RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
>+
>+	for (j = 0; j < adev->usec_timeout; j++) {
>+		tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
>+		if (tmp & (1 << vmid))
>+			break;
>+		udelay(1);
>+	}
>+	spin_unlock(&adev->gmc.invalidate_lock);
>+	if (j < adev->usec_timeout)
>+		return;
>+
>+	DRM_ERROR("Timeout waiting for VM flush ACK!\n");
> }
> 
> static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>@@ -480,7 +540,11 @@
> 	struct amdgpu_device *adev = ring->adev;
> 	uint32_t reg;
> 
>-	if (ring->funcs->vmhub == AMDGPU_GFXHUB)
>+	/* Do nothing because there's no lut register for mmhub1. */
>+	if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
>+		return;
>+
>+	if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
> 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
> 	else
> 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
>@@ -597,12 +661,41 @@
> 	adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
> }
> 
>+static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
>+{
>+	switch (adev->asic_type) {
>+	case CHIP_VEGA20:
>+		adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
>+		adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
>+		adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
>+		adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET;
>+		adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
>+		adev->umc.funcs = &umc_v6_1_funcs;
>+		break;
>+	default:
>+		break;
>+	}
>+}
>+
>+static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
>+{
>+	switch (adev->asic_type) {
>+	case CHIP_VEGA20:
>+		adev->mmhub_funcs = &mmhub_v1_0_funcs;
>+		break;
>+	default:
>+		break;
>+	}
>+}
>+
> static int gmc_v9_0_early_init(void *handle)
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
> 	gmc_v9_0_set_gmc_funcs(adev);
> 	gmc_v9_0_set_irq_funcs(adev);
>+	gmc_v9_0_set_umc_funcs(adev);
>+	gmc_v9_0_set_mmhub_funcs(adev);
> 
> 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
> 	adev->gmc.shared_aperture_end =
>@@ -629,6 +722,8 @@
> 	switch (adev->asic_type) {
> 	case CHIP_VEGA10:
> 	case CHIP_RAVEN:
>+	case CHIP_ARCTURUS:
>+	case CHIP_RENOIR:
> 		return true;
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
>@@ -641,7 +736,8 @@
> {
> 	struct amdgpu_ring *ring;
> 	unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
>-		{GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP};
>+		{GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP,
>+		GFXHUB_FREE_VM_INV_ENGS_BITMAP};
> 	unsigned i;
> 	unsigned vmhub, inv_eng;
> 
>@@ -666,29 +762,28 @@
> 	return 0;
> }
> 
>-static int gmc_v9_0_ecc_late_init(void *handle)
>+static int gmc_v9_0_ecc_ras_block_late_init(void *handle,
>+			struct ras_fs_if *fs_info, struct ras_common_if *ras_block)
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>-	struct ras_common_if **ras_if = &adev->gmc.ras_if;
>+	struct ras_common_if **ras_if = NULL;
> 	struct ras_ih_if ih_info = {
> 		.cb = gmc_v9_0_process_ras_data_cb,
> 	};
>-	struct ras_fs_if fs_info = {
>-		.sysfs_name = "umc_err_count",
>-		.debugfs_name = "umc_err_inject",
>-	};
>-	struct ras_common_if ras_block = {
>-		.block = AMDGPU_RAS_BLOCK__UMC,
>-		.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
>-		.sub_block_index = 0,
>-		.name = "umc",
>-	};
> 	int r;
> 
>-	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) {
>-		amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
>+	if (ras_block->block == AMDGPU_RAS_BLOCK__UMC)
>+		ras_if = &adev->gmc.umc_ras_if;
>+	else if (ras_block->block == AMDGPU_RAS_BLOCK__MMHUB)
>+		ras_if = &adev->gmc.mmhub_ras_if;
>+	else
>+		BUG();
>+
>+	if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
>+		amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
> 		return 0;
> 	}
>+
> 	/* handle resume path. */
> 	if (*ras_if) {
> 		/* resend ras TA enable cmd during resume.
>@@ -700,7 +795,7 @@
> 			if (r == -EAGAIN) {
> 				/* request a gpu reset. will run again. */
> 				amdgpu_ras_request_reset_on_boot(adev,
>-						AMDGPU_RAS_BLOCK__UMC);
>+						ras_block->block);
> 				return 0;
> 			}
> 			/* fail to enable ras, cleanup all. */
>@@ -714,41 +809,46 @@
> 	if (!*ras_if)
> 		return -ENOMEM;
> 
>-	**ras_if = ras_block;
>+	**ras_if = *ras_block;
> 
> 	r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
> 	if (r) {
> 		if (r == -EAGAIN) {
> 			amdgpu_ras_request_reset_on_boot(adev,
>-					AMDGPU_RAS_BLOCK__UMC);
>+					ras_block->block);
> 			r = 0;
> 		}
> 		goto feature;
> 	}
> 
> 	ih_info.head = **ras_if;
>-	fs_info.head = **ras_if;
>+	fs_info->head = **ras_if;
> 
>-	r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
>-	if (r)
>-		goto interrupt;
>+	if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) {
>+		r = amdgpu_ras_interrupt_add_handler(adev, &ih_info);
>+		if (r)
>+			goto interrupt;
>+	}
> 
>-	amdgpu_ras_debugfs_create(adev, &fs_info);
>+	amdgpu_ras_debugfs_create(adev, fs_info);
> 
>-	r = amdgpu_ras_sysfs_create(adev, &fs_info);
>+	r = amdgpu_ras_sysfs_create(adev, fs_info);
> 	if (r)
> 		goto sysfs;
> resume:
>-	r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
>-	if (r)
>-		goto irq;
>+	if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) {
>+		r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
>+		if (r)
>+			goto irq;
>+	}
> 
> 	return 0;
> irq:
> 	amdgpu_ras_sysfs_remove(adev, *ras_if);
> sysfs:
> 	amdgpu_ras_debugfs_remove(adev, *ras_if);
>-	amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
>+	if (ras_block->block == AMDGPU_RAS_BLOCK__UMC)
>+		amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
> interrupt:
> 	amdgpu_ras_feature_enable(adev, *ras_if, 0);
> feature:
>@@ -757,6 +857,40 @@
> 	return r;
> }
> 
>+static int gmc_v9_0_ecc_late_init(void *handle)
>+{
>+	int r;
>+
>+	struct ras_fs_if umc_fs_info = {
>+		.sysfs_name = "umc_err_count",
>+		.debugfs_name = "umc_err_inject",
>+	};
>+	struct ras_common_if umc_ras_block = {
>+		.block = AMDGPU_RAS_BLOCK__UMC,
>+		.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
>+		.sub_block_index = 0,
>+		.name = "umc",
>+	};
>+	struct ras_fs_if mmhub_fs_info = {
>+		.sysfs_name = "mmhub_err_count",
>+		.debugfs_name = "mmhub_err_inject",
>+	};
>+	struct ras_common_if mmhub_ras_block = {
>+		.block = AMDGPU_RAS_BLOCK__MMHUB,
>+		.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
>+		.sub_block_index = 0,
>+		.name = "mmhub",
>+	};
>+
>+	r = gmc_v9_0_ecc_ras_block_late_init(handle,
>+			&umc_fs_info, &umc_ras_block);
>+	if (r)
>+		return r;
>+
>+	r = gmc_v9_0_ecc_ras_block_late_init(handle,
>+			&mmhub_fs_info, &mmhub_ras_block);
>+	return r;
>+}
> 
> static int gmc_v9_0_late_init(void *handle)
> {
>@@ -806,14 +940,17 @@
> 					struct amdgpu_gmc *mc)
> {
> 	u64 base = 0;
>-	if (!amdgpu_sriov_vf(adev))
>+
>+	if (adev->asic_type == CHIP_ARCTURUS)
>+		base = mmhub_v9_4_get_fb_location(adev);
>+	else if (!amdgpu_sriov_vf(adev))
> 		base = mmhub_v1_0_get_fb_location(adev);
>+
> 	/* add the xgmi offset of the physical node */
> 	base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
> 	amdgpu_gmc_vram_location(adev, mc, base);
> 	amdgpu_gmc_gart_location(adev, mc);
>-	if (!amdgpu_sriov_vf(adev))
>-		amdgpu_gmc_agp_location(adev, mc);
>+	amdgpu_gmc_agp_location(adev, mc);
> 	/* base offset of vram pages */
> 	adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
> 
>@@ -887,10 +1024,12 @@
> 		case CHIP_VEGA10:  /* all engines support GPUVM */
> 		case CHIP_VEGA12:  /* all engines support GPUVM */
> 		case CHIP_VEGA20:
>+		case CHIP_ARCTURUS:
> 		default:
> 			adev->gmc.gart_size = 512ULL << 20;
> 			break;
> 		case CHIP_RAVEN:   /* DCE SG support */
>+		case CHIP_RENOIR:
> 			adev->gmc.gart_size = 1024ULL << 20;
> 			break;
> 		}
>@@ -923,7 +1062,7 @@
> 
> static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
> {
>-	u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
>+	u32 d1vga_control;
> 	unsigned size;
> 
> 	/*
>@@ -933,6 +1072,7 @@
> 	if (gmc_v9_0_keep_stolen_memory(adev))
> 		return 9 * 1024 * 1024;
> 
>+	d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
> 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
> 		size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
> 	} else {
>@@ -940,6 +1080,7 @@
> 
> 		switch (adev->asic_type) {
> 		case CHIP_RAVEN:
>+		case CHIP_RENOIR:
> 			viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
> 			size = (REG_GET_FIELD(viewport,
> 					      HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
>@@ -968,17 +1109,21 @@
> static int gmc_v9_0_sw_init(void *handle)
> {
> 	int r;
>-	int dma_bits;
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
> 	gfxhub_v1_0_init(adev);
>-	mmhub_v1_0_init(adev);
>+	if (adev->asic_type == CHIP_ARCTURUS)
>+		mmhub_v9_4_init(adev);
>+	else
>+		mmhub_v1_0_init(adev);
> 
> 	spin_lock_init(&adev->gmc.invalidate_lock);
> 
> 	adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
> 	switch (adev->asic_type) {
> 	case CHIP_RAVEN:
>+		adev->num_vmhubs = 2;
>+
> 		if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
> 			amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
> 		} else {
>@@ -991,6 +1136,10 @@
> 	case CHIP_VEGA10:
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
>+	case CHIP_RENOIR:
>+		adev->num_vmhubs = 2;
>+
>+
> 		/*
> 		 * To fulfill 4-level page support,
> 		 * vm size is 256TB (48bit), maximum size of Vega10,
>@@ -1002,6 +1151,12 @@
> 		else
> 			amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
> 		break;
>+	case CHIP_ARCTURUS:
>+		adev->num_vmhubs = 3;
>+
>+		/* Keep the vm size same with Vega20 */
>+		amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
>+		break;
> 	default:
> 		break;
> 	}
>@@ -1012,6 +1167,13 @@
> 	if (r)
> 		return r;
> 
>+	if (adev->asic_type == CHIP_ARCTURUS) {
>+		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
>+					&adev->gmc.vm_fault);
>+		if (r)
>+			return r;
>+	}
>+
> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
> 				&adev->gmc.vm_fault);
> 
>@@ -1030,25 +1192,12 @@
> 	 */
> 	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
> 
>-	/* set DMA mask + need_dma32 flags.
>-	 * PCIE - can handle 44-bits.
>-	 * IGP - can handle 44-bits
>-	 * PCI - dma32 for legacy pci gart, 44 bits on vega10
>-	 */
>-	adev->need_dma32 = false;
>-	dma_bits = adev->need_dma32 ? 32 : 44;
>-	r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
>+	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
> 	if (r) {
>-		adev->need_dma32 = true;
>-		dma_bits = 32;
> 		printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
>+		return r;
> 	}
>-	r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
>-	if (r) {
>-		pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
>-		printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
>-	}
>-	adev->need_swiotlb = drm_need_swiotlb(dma_bits);
>+	adev->need_swiotlb = drm_need_swiotlb(44);
> 
> 	if (adev->gmc.xgmi.supported) {
> 		r = gfxhub_v1_1_get_xgmi_info(adev);
>@@ -1077,8 +1226,9 @@
> 	 * amdgpu graphics/compute will use VMIDs 1-7
> 	 * amdkfd will use VMIDs 8-15
> 	 */
>-	adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
>-	adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
>+	adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
>+	adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
>+	adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS;
> 
> 	amdgpu_vm_manager_init(adev);
> 
>@@ -1088,28 +1238,40 @@
> static int gmc_v9_0_sw_fini(void *handle)
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+	void *stolen_vga_buf;
> 
> 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
>-			adev->gmc.ras_if) {
>-		struct ras_common_if *ras_if = adev->gmc.ras_if;
>+			adev->gmc.umc_ras_if) {
>+		struct ras_common_if *ras_if = adev->gmc.umc_ras_if;
> 		struct ras_ih_if ih_info = {
> 			.head = *ras_if,
> 		};
> 
>-		/*remove fs first*/
>+		/* remove fs first */
> 		amdgpu_ras_debugfs_remove(adev, ras_if);
> 		amdgpu_ras_sysfs_remove(adev, ras_if);
>-		/*remove the IH*/
>+		/* remove the IH */
> 		amdgpu_ras_interrupt_remove_handler(adev, &ih_info);
> 		amdgpu_ras_feature_enable(adev, ras_if, 0);
> 		kfree(ras_if);
> 	}
> 
>+	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
>+			adev->gmc.mmhub_ras_if) {
>+		struct ras_common_if *ras_if = adev->gmc.mmhub_ras_if;
>+
>+		/* remove fs and disable ras feature */
>+		amdgpu_ras_debugfs_remove(adev, ras_if);
>+		amdgpu_ras_sysfs_remove(adev, ras_if);
>+		amdgpu_ras_feature_enable(adev, ras_if, 0);
>+		kfree(ras_if);
>+	}
>+
> 	amdgpu_gem_force_release(adev);
> 	amdgpu_vm_manager_fini(adev);
> 
> 	if (gmc_v9_0_keep_stolen_memory(adev))
>-		amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
>+		amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
> 
> 	amdgpu_gart_table_vram_free(adev);
> 	amdgpu_bo_fini(adev);
>@@ -1123,7 +1285,7 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_VEGA10:
>-		if (amdgpu_virt_support_skip_setting(adev))
>+		if (amdgpu_sriov_vf(adev))
> 			break;
> 		/* fall through */
> 	case CHIP_VEGA20:
>@@ -1137,6 +1299,7 @@
> 	case CHIP_VEGA12:
> 		break;
> 	case CHIP_RAVEN:
>+		/* TODO for renoir */
> 		soc15_program_register_sequence(adev,
> 						golden_settings_athub_1_0_0,
> 						ARRAY_SIZE(golden_settings_athub_1_0_0));
>@@ -1153,7 +1316,7 @@
>  */
> static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
> {
>-	int r;
>+	int r, i;
> 	bool value;
> 	u32 tmp;
> 
>@@ -1171,6 +1334,7 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_RAVEN:
>+		/* TODO for renoir */
> 		mmhub_v1_0_update_power_gating(adev, true);
> 		break;
> 	default:
>@@ -1181,7 +1345,10 @@
> 	if (r)
> 		return r;
> 
>-	r = mmhub_v1_0_gart_enable(adev);
>+	if (adev->asic_type == CHIP_ARCTURUS)
>+		r = mmhub_v9_4_gart_enable(adev);
>+	else
>+		r = mmhub_v1_0_gart_enable(adev);
> 	if (r)
> 		return r;
> 
>@@ -1202,8 +1369,13 @@
> 		value = true;
> 
> 	gfxhub_v1_0_set_fault_enable_default(adev, value);
>-	mmhub_v1_0_set_fault_enable_default(adev, value);
>-	gmc_v9_0_flush_gpu_tlb(adev, 0, 0);
>+	if (adev->asic_type == CHIP_ARCTURUS)
>+		mmhub_v9_4_set_fault_enable_default(adev, value);
>+	else
>+		mmhub_v1_0_set_fault_enable_default(adev, value);
>+
>+	for (i = 0; i < adev->num_vmhubs; ++i)
>+		gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
> 
> 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
> 		 (unsigned)(adev->gmc.gart_size >> 20),
>@@ -1243,7 +1415,10 @@
> static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
> {
> 	gfxhub_v1_0_gart_disable(adev);
>-	mmhub_v1_0_gart_disable(adev);
>+	if (adev->asic_type == CHIP_ARCTURUS)
>+		mmhub_v9_4_gart_disable(adev);
>+	else
>+		mmhub_v1_0_gart_disable(adev);
> 	amdgpu_gart_table_vram_unpin(adev);
> }
> 
>@@ -1308,14 +1483,26 @@
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
>-	return mmhub_v1_0_set_clockgating(adev, state);
>+	if (adev->asic_type == CHIP_ARCTURUS)
>+		mmhub_v9_4_set_clockgating(adev, state);
>+	else
>+		mmhub_v1_0_set_clockgating(adev, state);
>+
>+	athub_v1_0_set_clockgating(adev, state);
>+
>+	return 0;
> }
> 
> static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
>-	mmhub_v1_0_get_clockgating(adev, flags);
>+	if (adev->asic_type == CHIP_ARCTURUS)
>+		mmhub_v9_4_get_clockgating(adev, flags);
>+	else
>+		mmhub_v1_0_get_clockgating(adev, flags);
>+
>+	athub_v1_0_get_clockgating(adev, flags);
> }
> 
> static int gmc_v9_0_set_powergating_state(void *handle,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h	2019-08-31 15:01:11.848736167 -0500
>@@ -37,4 +37,11 @@
> extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
> extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
> 
>+/* amdgpu_amdkfd*.c */
>+void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
>+				uint64_t value);
>+void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
>+				uint64_t value);
>+void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,
>+				uint32_t vmid, uint64_t value);
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/Makefile	2019-08-31 15:01:11.838736166 -0500
>@@ -54,7 +54,7 @@
> 	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
> 	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
> 	amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
>-	amdgpu_vm_sdma.o amdgpu_discovery.o
>+	amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o amdgpu_ras_eeprom.o smu_v11_0_i2c.o
> 
> amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
> 
>@@ -66,7 +66,8 @@
> 
> amdgpu-y += \
> 	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \
>-	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o
>+	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
>+	arct_reg_init.o navi12_reg_init.o
> 
> # add DF block
> amdgpu-y += \
>@@ -77,9 +78,13 @@
> amdgpu-y += \
> 	gmc_v7_0.o \
> 	gmc_v8_0.o \
>-	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o \
>+	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \
> 	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o
> 
>+# add UMC block
>+amdgpu-y += \
>+	umc_v6_1.o
>+
> # add IH block
> amdgpu-y += \
> 	amdgpu_irq.o \
>@@ -95,7 +100,8 @@
> 	amdgpu_psp.o \
> 	psp_v3_1.o \
> 	psp_v10_0.o \
>-	psp_v11_0.o
>+	psp_v11_0.o \
>+	psp_v12_0.o
> 
> # add SMC block
> amdgpu-y += \
>@@ -144,10 +150,12 @@
> amdgpu-y += \
> 	amdgpu_vcn.o \
> 	vcn_v1_0.o \
>-	vcn_v2_0.o
>+	vcn_v2_0.o \
>+	vcn_v2_5.o
> 
> # add ATHUB block
> amdgpu-y += \
>+	athub_v1_0.o \
> 	athub_v2_0.o
> 
> # add amdkfd interfaces
>@@ -162,6 +170,7 @@
> 	 amdgpu_amdkfd_gpuvm.o \
> 	 amdgpu_amdkfd_gfx_v8.o \
> 	 amdgpu_amdkfd_gfx_v9.o \
>+	 amdgpu_amdkfd_arcturus.o \
> 	 amdgpu_amdkfd_gfx_v10.o
> 
> ifneq ($(CONFIG_DRM_AMDGPU_CIK),)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c	2019-08-31 15:01:11.848736167 -0500
>@@ -21,13 +21,13 @@
>  *
>  */
> #include "amdgpu.h"
>+#include "amdgpu_ras.h"
> #include "mmhub_v1_0.h"
> 
> #include "mmhub/mmhub_1_0_offset.h"
> #include "mmhub/mmhub_1_0_sh_mask.h"
> #include "mmhub/mmhub_1_0_default.h"
>-#include "athub/athub_1_0_offset.h"
>-#include "athub/athub_1_0_sh_mask.h"
>+#include "mmhub/mmhub_9_4_0_offset.h"
> #include "vega10_enum.h"
> 
> #include "soc15_common.h"
>@@ -35,6 +35,9 @@
> #define mmDAGB0_CNTL_MISC2_RV 0x008f
> #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
> 
>+#define EA_EDC_CNT_MASK 0x3
>+#define EA_EDC_CNT_SHIFT 0x2
>+
> u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
> {
> 	u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
>@@ -111,7 +114,7 @@
> 		WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
> 			     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
> 
>-	if (amdgpu_virt_support_skip_setting(adev))
>+	if (amdgpu_sriov_vf(adev))
> 		return;
> 
> 	/* Set default page address. */
>@@ -159,7 +162,7 @@
> {
> 	uint32_t tmp;
> 
>-	if (amdgpu_virt_support_skip_setting(adev))
>+	if (amdgpu_sriov_vf(adev))
> 		return;
> 
> 	/* Setup L2 cache */
>@@ -208,7 +211,7 @@
> 
> static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
> {
>-	if (amdgpu_virt_support_skip_setting(adev))
>+	if (amdgpu_sriov_vf(adev))
> 		return;
> 
> 	WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
>@@ -348,7 +351,7 @@
> 				0);
> 	WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
> 
>-	if (!amdgpu_virt_support_skip_setting(adev)) {
>+	if (!amdgpu_sriov_vf(adev)) {
> 		/* Setup L2 cache */
> 		tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
> 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
>@@ -367,7 +370,7 @@
> {
> 	u32 tmp;
> 
>-	if (amdgpu_virt_support_skip_setting(adev))
>+	if (amdgpu_sriov_vf(adev))
> 		return;
> 
> 	tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
>@@ -407,7 +410,7 @@
> 
> void mmhub_v1_0_init(struct amdgpu_device *adev)
> {
>-	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
>+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
> 
> 	hub->ctx0_ptb_addr_lo32 =
> 		SOC15_REG_OFFSET(MMHUB, 0,
>@@ -491,22 +494,6 @@
> 		WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
> }
> 
>-static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
>-						   bool enable)
>-{
>-	uint32_t def, data;
>-
>-	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
>-
>-	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
>-		data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
>-	else
>-		data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
>-
>-	if (def != data)
>-		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
>-}
>-
> static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
> 						       bool enable)
> {
>@@ -523,23 +510,6 @@
> 		WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
> }
> 
>-static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
>-						  bool enable)
>-{
>-	uint32_t def, data;
>-
>-	def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
>-
>-	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
>-	    (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
>-		data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
>-	else
>-		data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
>-
>-	if(def != data)
>-		WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
>-}
>-
> int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
> 			       enum amd_clockgating_state state)
> {
>@@ -551,14 +521,11 @@
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
> 	case CHIP_RAVEN:
>+	case CHIP_RENOIR:
> 		mmhub_v1_0_update_medium_grain_clock_gating(adev,
> 				state == AMD_CG_STATE_GATE ? true : false);
>-		athub_update_medium_grain_clock_gating(adev,
>-				state == AMD_CG_STATE_GATE ? true : false);
> 		mmhub_v1_0_update_medium_grain_light_sleep(adev,
> 				state == AMD_CG_STATE_GATE ? true : false);
>-		athub_update_medium_grain_light_sleep(adev,
>-				state == AMD_CG_STATE_GATE ? true : false);
> 		break;
> 	default:
> 		break;
>@@ -569,18 +536,85 @@
> 
> void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
> {
>-	int data;
>+	int data, data1;
> 
> 	if (amdgpu_sriov_vf(adev))
> 		*flags = 0;
> 
>+	data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
>+
>+	data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
>+
> 	/* AMD_CG_SUPPORT_MC_MGCG */
>-	data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
>-	if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
>+	if ((data & ATC_L2_MISC_CG__ENABLE_MASK) &&
>+	    !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
>+		       DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
>+		       DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
>+		       DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
>+		       DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
>+		       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
> 		*flags |= AMD_CG_SUPPORT_MC_MGCG;
> 
> 	/* AMD_CG_SUPPORT_MC_LS */
>-	data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
> 	if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
> 		*flags |= AMD_CG_SUPPORT_MC_LS;
> }
>+
>+static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
>+					   void *ras_error_status)
>+{
>+	int i;
>+	uint32_t ea0_edc_cnt, ea0_edc_cnt2;
>+	uint32_t ea1_edc_cnt, ea1_edc_cnt2;
>+	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
>+
>+	/* EDC CNT will be cleared automatically after read */
>+	ea0_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT_VG20);
>+	ea0_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20);
>+	ea1_edc_cnt = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT_VG20);
>+	ea1_edc_cnt2 = RREG32_SOC15(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20);
>+
>+	/* error count of each error type is recorded by 2 bits,
>+	 * ce and ue count in EDC_CNT
>+	 */
>+	for (i = 0; i < 5; i++) {
>+		err_data->ce_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
>+		err_data->ce_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
>+		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
>+		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
>+		err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
>+		err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
>+		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
>+		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
>+	}
>+	/* successive ue count in EDC_CNT */
>+	for (i = 0; i < 5; i++) {
>+		err_data->ue_count += (ea0_edc_cnt & EA_EDC_CNT_MASK);
>+		err_data->ue_count += (ea1_edc_cnt & EA_EDC_CNT_MASK);
>+		ea0_edc_cnt >>= EA_EDC_CNT_SHIFT;
>+		ea1_edc_cnt >>= EA_EDC_CNT_SHIFT;
>+	}
>+
>+	/* ce and ue count in EDC_CNT2 */
>+	for (i = 0; i < 3; i++) {
>+		err_data->ce_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
>+		err_data->ce_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
>+		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
>+		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
>+		err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
>+		err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
>+		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
>+		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
>+	}
>+	/* successive ue count in EDC_CNT2 */
>+	for (i = 0; i < 6; i++) {
>+		err_data->ue_count += (ea0_edc_cnt2 & EA_EDC_CNT_MASK);
>+		err_data->ue_count += (ea1_edc_cnt2 & EA_EDC_CNT_MASK);
>+		ea0_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
>+		ea1_edc_cnt2 >>= EA_EDC_CNT_SHIFT;
>+	}
>+}
>+
>+const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
>+	.query_ras_error_count = mmhub_v1_0_query_ras_error_count,
>+};
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h	2019-08-31 15:01:11.849736167 -0500
>@@ -23,6 +23,8 @@
> #ifndef __MMHUB_V1_0_H__
> #define __MMHUB_V1_0_H__
> 
>+extern const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs;
>+
> u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev);
> int mmhub_v1_0_gart_enable(struct amdgpu_device *adev);
> void mmhub_v1_0_gart_disable(struct amdgpu_device *adev);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c	2019-08-31 15:01:11.849736167 -0500
>@@ -126,7 +126,7 @@
> 	/* XXX for emulation, Refer to closed source code.*/
> 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
> 			    0);
>-	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
>+	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
> 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
> 	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
> 	WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
>@@ -324,7 +324,7 @@
> 
> void mmhub_v2_0_init(struct amdgpu_device *adev)
> {
>-	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
>+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
> 
> 	hub->ctx0_ptb_addr_lo32 =
> 		SOC15_REG_OFFSET(MMHUB, 0,
>@@ -406,6 +406,8 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		mmhub_v2_0_update_medium_grain_clock_gating(adev,
> 				state == AMD_CG_STATE_GATE ? true : false);
> 		mmhub_v2_0_update_medium_grain_light_sleep(adev,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c	2019-08-31 15:01:11.849736167 -0500
>@@ -0,0 +1,642 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#include "amdgpu.h"
>+#include "mmhub_v9_4.h"
>+
>+#include "mmhub/mmhub_9_4_1_offset.h"
>+#include "mmhub/mmhub_9_4_1_sh_mask.h"
>+#include "mmhub/mmhub_9_4_1_default.h"
>+#include "athub/athub_1_0_offset.h"
>+#include "athub/athub_1_0_sh_mask.h"
>+#include "vega10_enum.h"
>+
>+#include "soc15_common.h"
>+
>+#define MMHUB_NUM_INSTANCES			2
>+#define MMHUB_INSTANCE_REGISTER_OFFSET		0x3000
>+
>+u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
>+{
>+	/* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */
>+	u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);
>+	u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP);
>+
>+	base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
>+	base <<= 24;
>+
>+	top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
>+	top <<= 24;
>+
>+	adev->gmc.fb_start = base;
>+	adev->gmc.fb_end = top;
>+
>+	return base;
>+}
>+
>+void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,
>+				uint32_t vmid, uint64_t value)
>+{
>+	/* two registers distance between mmVML2VC0_VM_CONTEXT0_* to
>+	 * mmVML2VC0_VM_CONTEXT1_*
>+	 */
>+	int dist = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
>+			- mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
>+
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
>+			    dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    lower_32_bits(value));
>+
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
>+			    dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    upper_32_bits(value));
>+
>+}
>+
>+static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
>+					       int hubid)
>+{
>+	uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
>+
>+	mmhub_v9_4_setup_vm_pt_regs(adev, hubid, 0, pt_base);
>+
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    (u32)(adev->gmc.gart_start >> 12));
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    (u32)(adev->gmc.gart_start >> 44));
>+
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    (u32)(adev->gmc.gart_end >> 12));
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    (u32)(adev->gmc.gart_end >> 44));
>+}
>+
>+static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
>+					         int hubid)
>+{
>+	uint64_t value;
>+	uint32_t tmp;
>+
>+	/* Program the AGP BAR */
>+	WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    0);
>+	WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    adev->gmc.agp_end >> 24);
>+	WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    adev->gmc.agp_start >> 24);
>+
>+	/* Program the system aperture low logical page number. */
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+			    mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+			    mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
>+
>+	/* Set default page address. */
>+	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
>+		adev->vm_manager.vram_base_offset;
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+			mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
>+			hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			(u32)(value >> 12));
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+			mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
>+			hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			(u32)(value >> 44));
>+
>+	/* Program "protection fault". */
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+			    mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    (u32)(adev->dummy_page_addr >> 12));
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+			    mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
>+			    (u32)((u64)adev->dummy_page_addr >> 44));
>+
>+	tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
>+				  mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
>+				  hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
>+	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
>+			    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
>+	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
>+}
>+
>+static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid)
>+{
>+	uint32_t tmp;
>+
>+	/* Setup TLB control */
>+	tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
>+			   mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+			   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
>+
>+	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+			    ENABLE_L1_TLB, 1);
>+	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+			    SYSTEM_ACCESS_MODE, 3);
>+	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+			    ENABLE_ADVANCED_DRIVER_MODEL, 1);
>+	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+			    SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
>+	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+			    ECO_BITS, 0);
>+	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+			    MTYPE, MTYPE_UC);/* XXX for emulation. */
>+	tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+			    ATC_EN, 1);
>+
>+	WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
>+}
>+
>+static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
>+{
>+	uint32_t tmp;
>+
>+	/* Setup L2 cache */
>+	tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
>+				  hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
>+	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
>+			    ENABLE_L2_CACHE, 1);
>+	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
>+			    ENABLE_L2_FRAGMENT_PROCESSING, 1);
>+	/* XXX for emulation, Refer to closed source code.*/
>+	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
>+			    L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
>+	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
>+			    PDE_FAULT_CLASSIFICATION, 0);
>+	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
>+			    CONTEXT1_IDENTITY_ACCESS_MODE, 1);
>+	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
>+			    IDENTITY_MODE_FRAGMENT_SIZE, 0);
>+	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
>+		     hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
>+
>+	tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
>+				  hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
>+	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
>+			    INVALIDATE_ALL_L1_TLBS, 1);
>+	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
>+			    INVALIDATE_L2_CACHE, 1);
>+	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
>+
>+	tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
>+	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
>+
>+	tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT;
>+	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
>+			    VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
>+	tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
>+			    VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
>+	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
>+}
>+
>+static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev,
>+					    int hubid)
>+{
>+	uint32_t tmp;
>+
>+	tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
>+				  hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
>+	tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
>+	tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
>+	WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
>+}
>+
>+static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
>+						 int hubid)
>+{
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+		    mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
>+		    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF);
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+		    mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
>+		    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F);
>+
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+		    mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
>+		    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+		    mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
>+		    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
>+
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+		    mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
>+		    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
>+	WREG32_SOC15_OFFSET(MMHUB, 0,
>+		    mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
>+		    hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
>+}
>+
>+static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
>+{
>+	uint32_t tmp;
>+	int i;
>+
>+	for (i = 0; i <= 14; i++) {
>+		tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
>+				hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
>+		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
>+				    ENABLE_CONTEXT, 1);
>+		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
>+				    PAGE_TABLE_DEPTH,
>+				    adev->vm_manager.num_level);
>+		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
>+				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
>+		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
>+				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
>+				    1);
>+		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
>+				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
>+		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
>+				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
>+		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
>+				    READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
>+		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
>+				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
>+		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
>+				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
>+		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
>+				    PAGE_TABLE_BLOCK_SIZE,
>+				    adev->vm_manager.block_size - 9);
>+		/* Send no-retry XNACK on fault to suppress VM fault storm. */
>+		tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
>+				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
>+		WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
>+				    hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i,
>+				    tmp);
>+		WREG32_SOC15_OFFSET(MMHUB, 0,
>+			    mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0);
>+		WREG32_SOC15_OFFSET(MMHUB, 0,
>+			    mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
>+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0);
>+		WREG32_SOC15_OFFSET(MMHUB, 0,
>+				mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
>+				hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2,
>+				lower_32_bits(adev->vm_manager.max_pfn - 1));
>+		WREG32_SOC15_OFFSET(MMHUB, 0,
>+				mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
>+				hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2,
>+				upper_32_bits(adev->vm_manager.max_pfn - 1));
>+	}
>+}
>+
>+static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev,
>+					    int hubid)
>+{
>+	unsigned i;
>+
>+	for (i = 0; i < 18; ++i) {
>+		WREG32_SOC15_OFFSET(MMHUB, 0,
>+				mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
>+				hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i,
>+				0xffffffff);
>+		WREG32_SOC15_OFFSET(MMHUB, 0,
>+				mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
>+				hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i,
>+				0x1f);
>+	}
>+}
>+
>+int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)
>+{
>+	int i;
>+
>+	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
>+		if (amdgpu_sriov_vf(adev)) {
>+			/*
>+			 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase
>+			 * they are VF copy registers so vbios post doesn't
>+			 * program them, for SRIOV driver need to program them
>+			 */
>+			WREG32_SOC15_OFFSET(MMHUB, 0,
>+				     mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE,
>+				     i * MMHUB_INSTANCE_REGISTER_OFFSET,
>+				     adev->gmc.vram_start >> 24);
>+			WREG32_SOC15_OFFSET(MMHUB, 0,
>+				     mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP,
>+				     i * MMHUB_INSTANCE_REGISTER_OFFSET,
>+				     adev->gmc.vram_end >> 24);
>+		}
>+
>+		/* GART Enable. */
>+		mmhub_v9_4_init_gart_aperture_regs(adev, i);
>+		mmhub_v9_4_init_system_aperture_regs(adev, i);
>+		mmhub_v9_4_init_tlb_regs(adev, i);
>+		mmhub_v9_4_init_cache_regs(adev, i);
>+
>+		mmhub_v9_4_enable_system_domain(adev, i);
>+		mmhub_v9_4_disable_identity_aperture(adev, i);
>+		mmhub_v9_4_setup_vmid_config(adev, i);
>+		mmhub_v9_4_program_invalidation(adev, i);
>+	}
>+
>+	return 0;
>+}
>+
>+void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
>+{
>+	u32 tmp;
>+	u32 i, j;
>+
>+	for (j = 0; j < MMHUB_NUM_INSTANCES; j++) {
>+		/* Disable all tables */
>+		for (i = 0; i < 16; i++)
>+			WREG32_SOC15_OFFSET(MMHUB, 0,
>+					    mmVML2VC0_VM_CONTEXT0_CNTL,
>+					    j * MMHUB_INSTANCE_REGISTER_OFFSET +
>+					    i, 0);
>+
>+		/* Setup TLB control */
>+		tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
>+				   mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+				   j * MMHUB_INSTANCE_REGISTER_OFFSET);
>+		tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+				    ENABLE_L1_TLB, 0);
>+		tmp = REG_SET_FIELD(tmp,
>+				    VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+				    ENABLE_ADVANCED_DRIVER_MODEL, 0);
>+		WREG32_SOC15_OFFSET(MMHUB, 0,
>+				    mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
>+				    j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
>+
>+		/* Setup L2 cache */
>+		tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
>+					  j * MMHUB_INSTANCE_REGISTER_OFFSET);
>+		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
>+				    ENABLE_L2_CACHE, 0);
>+		WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
>+				    j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
>+		WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
>+				    j * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
>+	}
>+}
>+
>+/**
>+ * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
>+ *
>+ * @adev: amdgpu_device pointer
>+ * @value: true redirects VM faults to the default page
>+ */
>+void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value)
>+{
>+	u32 tmp;
>+	int i;
>+
>+	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
>+		tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
>+					  mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+					  i * MMHUB_INSTANCE_REGISTER_OFFSET);
>+		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+				    RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,
>+				    value);
>+		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+				    PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,
>+				    value);
>+		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+				    PDE1_PROTECTION_FAULT_ENABLE_DEFAULT,
>+				    value);
>+		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+				    PDE2_PROTECTION_FAULT_ENABLE_DEFAULT,
>+				    value);
>+		tmp = REG_SET_FIELD(tmp,
>+			    VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+			    TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
>+			    value);
>+		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+				    NACK_PROTECTION_FAULT_ENABLE_DEFAULT,
>+				    value);
>+		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+				    DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
>+				    value);
>+		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+				    VALID_PROTECTION_FAULT_ENABLE_DEFAULT,
>+				    value);
>+		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+				    READ_PROTECTION_FAULT_ENABLE_DEFAULT,
>+				    value);
>+		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+				    WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,
>+				    value);
>+		tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+				    EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT,
>+				    value);
>+		if (!value) {
>+			tmp = REG_SET_FIELD(tmp,
>+					    VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+					    CRASH_ON_NO_RETRY_FAULT, 1);
>+			tmp = REG_SET_FIELD(tmp,
>+					    VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+					    CRASH_ON_RETRY_FAULT, 1);
>+		}
>+
>+		WREG32_SOC15_OFFSET(MMHUB, 0,
>+				    mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
>+				    i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
>+	}
>+}
>+
>+void mmhub_v9_4_init(struct amdgpu_device *adev)
>+{
>+	struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] =
>+		{&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]};
>+	int i;
>+
>+	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
>+		hub[i]->ctx0_ptb_addr_lo32 =
>+			SOC15_REG_OFFSET(MMHUB, 0,
>+			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) +
>+			    i * MMHUB_INSTANCE_REGISTER_OFFSET;
>+		hub[i]->ctx0_ptb_addr_hi32 =
>+			SOC15_REG_OFFSET(MMHUB, 0,
>+			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) +
>+			    i * MMHUB_INSTANCE_REGISTER_OFFSET;
>+		hub[i]->vm_inv_eng0_req =
>+			SOC15_REG_OFFSET(MMHUB, 0,
>+					 mmVML2VC0_VM_INVALIDATE_ENG0_REQ) +
>+					 i * MMHUB_INSTANCE_REGISTER_OFFSET;
>+		hub[i]->vm_inv_eng0_ack =
>+			SOC15_REG_OFFSET(MMHUB, 0,
>+					 mmVML2VC0_VM_INVALIDATE_ENG0_ACK) +
>+					 i * MMHUB_INSTANCE_REGISTER_OFFSET;
>+		hub[i]->vm_context0_cntl =
>+			SOC15_REG_OFFSET(MMHUB, 0,
>+					 mmVML2VC0_VM_CONTEXT0_CNTL) +
>+					 i * MMHUB_INSTANCE_REGISTER_OFFSET;
>+		hub[i]->vm_l2_pro_fault_status =
>+			SOC15_REG_OFFSET(MMHUB, 0,
>+				    mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) +
>+				    i * MMHUB_INSTANCE_REGISTER_OFFSET;
>+		hub[i]->vm_l2_pro_fault_cntl =
>+			SOC15_REG_OFFSET(MMHUB, 0,
>+				    mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) +
>+				    i * MMHUB_INSTANCE_REGISTER_OFFSET;
>+	}
>+}
>+
>+static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
>+							bool enable)
>+{
>+	uint32_t def, data, def1, data1;
>+	int i, j;
>+	int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2;
>+
>+	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
>+		def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
>+					mmATCL2_0_ATC_L2_MISC_CG,
>+					i * MMHUB_INSTANCE_REGISTER_OFFSET);
>+
>+		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
>+			data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
>+		else
>+			data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
>+
>+		if (def != data)
>+			WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
>+				i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
>+
>+		for (j = 0; j < 5; j++) {
>+			def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
>+					mmDAGB0_CNTL_MISC2,
>+					i * MMHUB_INSTANCE_REGISTER_OFFSET +
>+					j * dist);
>+			if (enable &&
>+			    (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
>+				data1 &=
>+				    ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
>+				    DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
>+				    DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
>+				    DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
>+				    DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
>+				    DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
>+			} else {
>+				data1 |=
>+				    (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
>+				    DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
>+				    DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
>+				    DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
>+				    DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
>+				    DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
>+			}
>+
>+			if (def1 != data1)
>+				WREG32_SOC15_OFFSET(MMHUB, 0,
>+					mmDAGB0_CNTL_MISC2,
>+					i * MMHUB_INSTANCE_REGISTER_OFFSET +
>+					j * dist, data1);
>+
>+			if (i == 1 && j == 3)
>+				break;
>+		}
>+	}
>+}
>+
>+static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
>+						       bool enable)
>+{
>+	uint32_t def, data;
>+	int i;
>+
>+	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
>+		def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
>+					mmATCL2_0_ATC_L2_MISC_CG,
>+					i * MMHUB_INSTANCE_REGISTER_OFFSET);
>+
>+		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
>+			data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
>+		else
>+			data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
>+
>+		if (def != data)
>+			WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
>+				i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
>+	}
>+}
>+
>+int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
>+			       enum amd_clockgating_state state)
>+{
>+	if (amdgpu_sriov_vf(adev))
>+		return 0;
>+
>+	switch (adev->asic_type) {
>+	case CHIP_ARCTURUS:
>+		mmhub_v9_4_update_medium_grain_clock_gating(adev,
>+				state == AMD_CG_STATE_GATE ? true : false);
>+		mmhub_v9_4_update_medium_grain_light_sleep(adev,
>+				state == AMD_CG_STATE_GATE ? true : false);
>+		break;
>+	default:
>+		break;
>+	}
>+
>+	return 0;
>+}
>+
>+void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
>+{
>+	int data, data1;
>+
>+	if (amdgpu_sriov_vf(adev))
>+		*flags = 0;
>+
>+	/* AMD_CG_SUPPORT_MC_MGCG */
>+	data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
>+
>+	data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
>+
>+	if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) &&
>+	    !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
>+		       DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
>+		       DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
>+		       DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
>+		       DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
>+		       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
>+		*flags |= AMD_CG_SUPPORT_MC_MGCG;
>+
>+	/* AMD_CG_SUPPORT_MC_LS */
>+	if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
>+		*flags |= AMD_CG_SUPPORT_MC_LS;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h	2019-08-31 15:01:11.849736167 -0500
>@@ -0,0 +1,36 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#ifndef __MMHUB_V9_4_H__
>+#define __MMHUB_V9_4_H__
>+
>+u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev);
>+int mmhub_v9_4_gart_enable(struct amdgpu_device *adev);
>+void mmhub_v9_4_gart_disable(struct amdgpu_device *adev);
>+void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev,
>+					 bool value);
>+void mmhub_v9_4_init(struct amdgpu_device *adev);
>+int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
>+			       enum amd_clockgating_state state);
>+void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c	2019-08-31 15:01:11.849736167 -0500
>@@ -449,20 +449,6 @@
> 	amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
> }
> 
>-static void xgpu_ai_init_reg_access_mode(struct amdgpu_device *adev)
>-{
>-	adev->virt.reg_access_mode = AMDGPU_VIRT_REG_ACCESS_LEGACY;
>-
>-	/* Enable L1 security reg access mode by defaul,  as non-security VF
>-	 * will no longer be supported.
>-	 */
>-	adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC;
>-
>-	adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH;
>-
>-	adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING;
>-}
>-
> const struct amdgpu_virt_ops xgpu_ai_virt_ops = {
> 	.req_full_gpu	= xgpu_ai_request_full_gpu_access,
> 	.rel_full_gpu	= xgpu_ai_release_full_gpu_access,
>@@ -471,5 +457,4 @@
> 	.trans_msg = xgpu_ai_mailbox_trans_msg,
> 	.get_pp_clk = xgpu_ai_get_pp_clk,
> 	.force_dpm_level = xgpu_ai_force_dpm_level,
>-	.init_reg_access_mode = xgpu_ai_init_reg_access_mode,
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi10_ih.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi10_ih.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi10_ih.c	2019-08-31 15:01:11.849736167 -0500
>@@ -21,7 +21,8 @@
>  *
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/pci.h>
>+
> #include "amdgpu.h"
> #include "amdgpu_ih.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c	2019-08-31 15:01:11.849736167 -0500
>@@ -29,20 +29,8 @@
> 
> int navi10_reg_base_init(struct amdgpu_device *adev)
> {
>-	int r, i;
>+	int i;
> 
>-	if (amdgpu_discovery) {
>-		r = amdgpu_discovery_reg_base_init(adev);
>-		if (r) {
>-			DRM_WARN("failed to init reg base from ip discovery table, "
>-					"fallback to legacy init method\n");
>-			goto legacy_init;
>-		}
>-
>-		return 0;
>-	}
>-
>-legacy_init:
> 	for (i = 0 ; i < MAX_INSTANCE ; ++i) {
> 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
> 		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c	2019-08-31 15:01:11.849736167 -0500
>@@ -0,0 +1,53 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#include "amdgpu.h"
>+#include "nv.h"
>+
>+#include "soc15_common.h"
>+#include "soc15_hw_ip.h"
>+#include "navi12_ip_offset.h"
>+
>+int navi12_reg_base_init(struct amdgpu_device *adev)
>+{
>+	/* HW has more IP blocks,  only initialized the blocks needed by driver */
>+	uint32_t i;
>+	for (i = 0 ; i < MAX_INSTANCE ; ++i) {
>+		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
>+		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
>+		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
>+		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
>+		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
>+		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
>+		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
>+		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
>+		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
>+		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
>+		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
>+		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
>+		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
>+		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
>+		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
>+		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
>+	}
>+	return 0;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c	2019-08-31 15:01:11.849736167 -0500
>@@ -0,0 +1,54 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#include "amdgpu.h"
>+#include "nv.h"
>+
>+#include "soc15_common.h"
>+#include "soc15_hw_ip.h"
>+#include "navi14_ip_offset.h"
>+
>+int navi14_reg_base_init(struct amdgpu_device *adev)
>+{
>+	int i;
>+
>+	for (i = 0 ; i < MAX_INSTANCE ; ++i) {
>+		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
>+		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
>+		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
>+		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
>+		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i]));
>+		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
>+		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
>+		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(UVD0_BASE.instance[i]));
>+		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
>+		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DMU_BASE.instance[i]));
>+		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
>+		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
>+		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
>+		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
>+		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
>+		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
>+	}
>+
>+	return 0;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c	2019-08-31 15:01:11.849736167 -0500
>@@ -92,7 +92,7 @@
> }
> 
> static void nbio_v2_3_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
>-					 int doorbell_index)
>+					 int doorbell_index, int instance)
> {
> 	u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c	2019-08-31 15:01:11.849736167 -0500
>@@ -91,6 +91,26 @@
> 	WREG32(reg, doorbell_range);
> }
> 
>+static void nbio_v7_0_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
>+					 int doorbell_index, int instance)
>+{
>+	u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
>+
>+	u32 doorbell_range = RREG32(reg);
>+
>+	if (use_doorbell) {
>+		doorbell_range = REG_SET_FIELD(doorbell_range,
>+					       BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
>+					       doorbell_index);
>+		doorbell_range = REG_SET_FIELD(doorbell_range,
>+					       BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
>+	} else
>+		doorbell_range = REG_SET_FIELD(doorbell_range,
>+					       BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
>+
>+	WREG32(reg, doorbell_range);
>+}
>+
> static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
> 					       bool enable)
> {
>@@ -282,6 +302,7 @@
> 	.hdp_flush = nbio_v7_0_hdp_flush,
> 	.get_memsize = nbio_v7_0_get_memsize,
> 	.sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
>+	.vcn_doorbell_range = nbio_v7_0_vcn_doorbell_range,
> 	.enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
> 	.enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
> 	.ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c	2019-08-31 15:01:11.849736167 -0500
>@@ -31,6 +31,25 @@
> 
> #define smnNBIF_MGCG_CTRL_LCLK	0x1013a21c
> 
>+/*
>+ * These are nbio v7_4_1 registers mask. Temporarily define these here since
>+ * nbio v7_4_1 header is incomplete.
>+ */
>+#define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK	0x00001000L
>+#define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK	0x00002000L
>+#define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK	0x00004000L
>+#define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK	0x00008000L
>+#define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK	0x00010000L
>+#define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK	0x00020000L
>+
>+#define mmBIF_MMSCH1_DOORBELL_RANGE                     0x01dc
>+#define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX            2
>+//BIF_MMSCH1_DOORBELL_RANGE
>+#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT        0x2
>+#define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT          0x10
>+#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK          0x00000FFCL
>+#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK            0x001F0000L
>+
> static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
> {
> 	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
>@@ -75,10 +94,24 @@
> static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
> 			bool use_doorbell, int doorbell_index, int doorbell_size)
> {
>-	u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
>-			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
>+	u32 reg, doorbell_range;
>+
>+	if (instance < 2)
>+		reg = instance +
>+			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
>+	else
>+		/*
>+		 * These registers address of SDMA2~7 is not consecutive
>+		 * from SDMA0~1. Need plus 4 dwords offset.
>+		 *
>+		 *   BIF_SDMA0_DOORBELL_RANGE:  0x3bc0
>+		 *   BIF_SDMA1_DOORBELL_RANGE:  0x3bc4
>+		 *   BIF_SDMA2_DOORBELL_RANGE:  0x3bd8
>+		 */
>+		reg = instance + 0x4 +
>+			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
> 
>-	u32 doorbell_range = RREG32(reg);
>+	doorbell_range = RREG32(reg);
> 
> 	if (use_doorbell) {
> 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
>@@ -89,6 +122,32 @@
> 	WREG32(reg, doorbell_range);
> }
> 
>+static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
>+					 int doorbell_index, int instance)
>+{
>+	u32 reg;
>+	u32 doorbell_range;
>+
>+	if (instance)
>+		reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
>+	else
>+		reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
>+
>+	doorbell_range = RREG32(reg);
>+
>+	if (use_doorbell) {
>+		doorbell_range = REG_SET_FIELD(doorbell_range,
>+					       BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
>+					       doorbell_index);
>+		doorbell_range = REG_SET_FIELD(doorbell_range,
>+					       BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
>+	} else
>+		doorbell_range = REG_SET_FIELD(doorbell_range,
>+					       BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
>+
>+	WREG32(reg, doorbell_range);
>+}
>+
> static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
> 					       bool enable)
> {
>@@ -220,6 +279,12 @@
> 	.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
> 	.ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
> 	.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
>+	.ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
>+	.ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
>+	.ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
>+	.ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
>+	.ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
>+	.ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
> };
> 
> static void nbio_v7_4_detect_hw_virt(struct amdgpu_device *adev)
>@@ -261,6 +326,7 @@
> 	.hdp_flush = nbio_v7_4_hdp_flush,
> 	.get_memsize = nbio_v7_4_get_memsize,
> 	.sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
>+	.vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range,
> 	.enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
> 	.enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
> 	.ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nv.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nv.c	2019-08-31 15:01:12.265736204 -0500
>@@ -23,7 +23,8 @@
> #include <linux/firmware.h>
> #include <linux/slab.h>
> #include <linux/module.h>
>-#include <drm/drmP.h>
>+#include <linux/pci.h>
>+
> #include "amdgpu.h"
> #include "amdgpu_atombios.h"
> #include "amdgpu_ih.h"
>@@ -289,6 +290,18 @@
> 
> 	return ret;
> }
>+
>+static enum amd_reset_method
>+nv_asic_reset_method(struct amdgpu_device *adev)
>+{
>+	struct smu_context *smu = &adev->smu;
>+
>+	if (smu_baco_is_support(smu))
>+		return AMD_RESET_METHOD_BACO;
>+	else
>+		return AMD_RESET_METHOD_MODE1;
>+}
>+
> static int nv_asic_reset(struct amdgpu_device *adev)
> {
> 
>@@ -303,10 +316,13 @@
> 	int ret = 0;
> 	struct smu_context *smu = &adev->smu;
> 
>-	if (smu_baco_is_support(smu))
>+	if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
>+		amdgpu_inc_vram_lost(adev);
> 		ret = smu_baco_reset(smu);
>-	else
>+	} else {
>+		amdgpu_inc_vram_lost(adev);
> 		ret = nv_asic_mode1_reset(adev);
>+	}
> 
> 	return ret;
> }
>@@ -363,23 +379,55 @@
> 	.funcs = &nv_common_ip_funcs,
> };
> 
>-int nv_set_ip_blocks(struct amdgpu_device *adev)
>+static int nv_reg_base_init(struct amdgpu_device *adev)
> {
>-	/* Set IP register base before any HW register access */
>+	int r;
>+
>+	if (amdgpu_discovery) {
>+		r = amdgpu_discovery_reg_base_init(adev);
>+		if (r) {
>+			DRM_WARN("failed to init reg base from ip discovery table, "
>+					"fallback to legacy init method\n");
>+			goto legacy_init;
>+		}
>+
>+		return 0;
>+	}
>+
>+legacy_init:
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
> 		navi10_reg_base_init(adev);
> 		break;
>+	case CHIP_NAVI14:
>+		navi14_reg_base_init(adev);
>+		break;
>+	case CHIP_NAVI12:
>+		navi12_reg_base_init(adev);
>+		break;
> 	default:
> 		return -EINVAL;
> 	}
> 
>+	return 0;
>+}
>+
>+int nv_set_ip_blocks(struct amdgpu_device *adev)
>+{
>+	int r;
>+
>+	/* Set IP register base before any HW register access */
>+	r = nv_reg_base_init(adev);
>+	if (r)
>+		return r;
>+
> 	adev->nbio_funcs = &nbio_v2_3_funcs;
> 
> 	adev->nbio_funcs->detect_hw_virt(adev);
> 
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
> 		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> 		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> 		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
>@@ -402,6 +450,27 @@
> 		if (adev->enable_mes)
> 			amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
> 		break;
>+	case CHIP_NAVI12:
>+		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
>+		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
>+		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
>+		amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
>+		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
>+		    is_support_sw_smu(adev))
>+			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
>+		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
>+			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
>+#if defined(CONFIG_DRM_AMD_DC)
>+		else if (amdgpu_device_has_dc_support(adev))
>+			amdgpu_device_ip_block_add(adev, &dm_ip_block);
>+#endif
>+		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
>+		amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
>+		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
>+		    is_support_sw_smu(adev))
>+			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
>+		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
>+		break;
> 	default:
> 		return -EINVAL;
> 	}
>@@ -496,6 +565,7 @@
> 	.read_bios_from_rom = &nv_read_bios_from_rom,
> 	.read_register = &nv_read_register,
> 	.reset = &nv_asic_reset,
>+	.reset_method = &nv_asic_reset_method,
> 	.set_vga_state = &nv_vga_set_state,
> 	.get_xclk = &nv_get_xclk,
> 	.set_uvd_clocks = &nv_set_uvd_clocks,
>@@ -511,7 +581,6 @@
> 
> static int nv_common_early_init(void *handle)
> {
>-	bool psp_enabled = false;
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
> 	adev->smc_rreg = NULL;
>@@ -528,10 +597,6 @@
> 
> 	adev->asic_funcs = &nv_asic_funcs;
> 
>-	if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
>-	    (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
>-		psp_enabled = true;
>-
> 	adev->rev_id = nv_get_rev_id(adev);
> 	adev->external_rev_id = 0xff;
> 	switch (adev->asic_type) {
>@@ -555,6 +620,46 @@
> 			AMD_PG_SUPPORT_ATHUB;
> 		adev->external_rev_id = adev->rev_id + 0x1;
> 		break;
>+	case CHIP_NAVI14:
>+		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
>+			AMD_CG_SUPPORT_GFX_CGCG |
>+			AMD_CG_SUPPORT_IH_CG |
>+			AMD_CG_SUPPORT_HDP_MGCG |
>+			AMD_CG_SUPPORT_HDP_LS |
>+			AMD_CG_SUPPORT_SDMA_MGCG |
>+			AMD_CG_SUPPORT_SDMA_LS |
>+			AMD_CG_SUPPORT_MC_MGCG |
>+			AMD_CG_SUPPORT_MC_LS |
>+			AMD_CG_SUPPORT_ATHUB_MGCG |
>+			AMD_CG_SUPPORT_ATHUB_LS |
>+			AMD_CG_SUPPORT_VCN_MGCG |
>+			AMD_CG_SUPPORT_BIF_MGCG |
>+			AMD_CG_SUPPORT_BIF_LS;
>+		adev->pg_flags = AMD_PG_SUPPORT_VCN |
>+			AMD_PG_SUPPORT_VCN_DPG;
>+		adev->external_rev_id = adev->rev_id + 20;
>+		break;
>+	case CHIP_NAVI12:
>+		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
>+			AMD_CG_SUPPORT_GFX_MGLS |
>+			AMD_CG_SUPPORT_GFX_CGCG |
>+			AMD_CG_SUPPORT_GFX_CP_LS |
>+			AMD_CG_SUPPORT_GFX_RLC_LS |
>+			AMD_CG_SUPPORT_IH_CG |
>+			AMD_CG_SUPPORT_HDP_MGCG |
>+			AMD_CG_SUPPORT_HDP_LS |
>+			AMD_CG_SUPPORT_SDMA_MGCG |
>+			AMD_CG_SUPPORT_SDMA_LS |
>+			AMD_CG_SUPPORT_MC_MGCG |
>+			AMD_CG_SUPPORT_MC_LS |
>+			AMD_CG_SUPPORT_ATHUB_MGCG |
>+			AMD_CG_SUPPORT_ATHUB_LS |
>+			AMD_CG_SUPPORT_VCN_MGCG;
>+		adev->pg_flags = AMD_PG_SUPPORT_VCN |
>+			AMD_PG_SUPPORT_VCN_DPG |
>+			AMD_PG_SUPPORT_ATHUB;
>+		adev->external_rev_id = adev->rev_id + 0xa;
>+		break;
> 	default:
> 		/* FIXME: not supported yet */
> 		return -EINVAL;
>@@ -747,6 +852,8 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		adev->nbio_funcs->update_medium_grain_clock_gating(adev,
> 				state == AMD_CG_STATE_GATE ? true : false);
> 		adev->nbio_funcs->update_medium_grain_light_sleep(adev,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nv.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/nv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/nv.h	2019-08-31 15:01:11.849736167 -0500
>@@ -30,4 +30,6 @@
> 		    u32 me, u32 pipe, u32 queue, u32 vmid);
> int nv_set_ip_blocks(struct amdgpu_device *adev);
> int navi10_reg_base_init(struct amdgpu_device *adev);
>+int navi14_reg_base_init(struct amdgpu_device *adev);
>+int navi12_reg_base_init(struct amdgpu_device *adev);
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h	2019-08-31 15:01:11.849736167 -0500
>@@ -233,8 +233,15 @@
> 	GFX_FW_TYPE_RLCP_CAM                        = 46,   /* RLCP CAM                 NV      */
> 	GFX_FW_TYPE_RLC_SPP_CAM_EXT                 = 47,   /* RLC SPP CAM EXT          NV      */
> 	GFX_FW_TYPE_RLX6_DRAM_BOOT                  = 48,   /* RLX6 DRAM BOOT           NV      */
>-	GFX_FW_TYPE_VCN0_RAM                        = 49,   /* VCN_RAM  NV */
>-	GFX_FW_TYPE_VCN1_RAM                        = 50,   /* VCN_RAM  NV */
>+	GFX_FW_TYPE_VCN0_RAM                        = 49,   /* VCN_RAM                  NV + RN */
>+	GFX_FW_TYPE_VCN1_RAM                        = 50,   /* VCN_RAM                  NV + RN */
>+	GFX_FW_TYPE_DMUB                            = 51,   /* DMUB                          RN */
>+	GFX_FW_TYPE_SDMA2                           = 52,   /* SDMA2                    MI      */
>+	GFX_FW_TYPE_SDMA3                           = 53,   /* SDMA3                    MI      */
>+	GFX_FW_TYPE_SDMA4                           = 54,   /* SDMA4                    MI      */
>+	GFX_FW_TYPE_SDMA5                           = 55,   /* SDMA5                    MI      */
>+	GFX_FW_TYPE_SDMA6                           = 56,   /* SDMA6                    MI      */
>+	GFX_FW_TYPE_SDMA7                           = 57,   /* SDMA7                    MI      */
> 	GFX_FW_TYPE_MAX
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c	2019-08-31 15:01:11.850736167 -0500
>@@ -190,7 +190,6 @@
> }
> 
> static int psp_v10_0_cmd_submit(struct psp_context *psp,
>-				struct amdgpu_firmware_info *ucode,
> 				uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
> 				int index)
> {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c	2019-08-31 15:01:11.850736167 -0500
>@@ -43,6 +43,12 @@
> MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
> MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
> MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
>+MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
>+MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
>+MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
>+MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
>+MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
>+MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
> 
> /* address block */
> #define smnMP1_FIRMWARE_FLAGS		0x3010024
>@@ -60,6 +66,7 @@
> 	int err = 0;
> 	const struct psp_firmware_header_v1_0 *sos_hdr;
> 	const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
>+	const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
> 	const struct psp_firmware_header_v1_0 *asd_hdr;
> 	const struct ta_firmware_header_v1_0 *ta_hdr;
> 
>@@ -72,6 +79,15 @@
> 	case CHIP_NAVI10:
> 		chip_name = "navi10";
> 		break;
>+	case CHIP_NAVI14:
>+		chip_name = "navi14";
>+		break;
>+	case CHIP_NAVI12:
>+		chip_name = "navi12";
>+		break;
>+	case CHIP_ARCTURUS:
>+		chip_name = "arcturus";
>+		break;
> 	default:
> 		BUG();
> 	}
>@@ -107,6 +123,12 @@
> 			adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
> 					le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
> 		}
>+		if (sos_hdr->header.header_version_minor == 2) {
>+			sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
>+			adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
>+			adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
>+						    le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
>+		}
> 		break;
> 	default:
> 		dev_err(adev->dev,
>@@ -158,6 +180,9 @@
> 		}
> 		break;
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
>+	case CHIP_ARCTURUS:
> 		break;
> 	default:
> 		BUG();
>@@ -473,7 +498,6 @@
> }
> 
> static int psp_v11_0_cmd_submit(struct psp_context *psp,
>-			       struct amdgpu_firmware_info *ucode,
> 			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
> 			       int index)
> {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c	2019-08-31 15:01:11.850736167 -0500
>@@ -0,0 +1,565 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+
>+#include <linux/firmware.h>
>+#include <linux/module.h>
>+#include "amdgpu.h"
>+#include "amdgpu_psp.h"
>+#include "amdgpu_ucode.h"
>+#include "soc15_common.h"
>+#include "psp_v12_0.h"
>+
>+#include "mp/mp_12_0_0_offset.h"
>+#include "mp/mp_12_0_0_sh_mask.h"
>+#include "gc/gc_9_0_offset.h"
>+#include "sdma0/sdma0_4_0_offset.h"
>+#include "nbio/nbio_7_4_offset.h"
>+
>+#include "oss/osssys_4_0_offset.h"
>+#include "oss/osssys_4_0_sh_mask.h"
>+
>+MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
>+/* address block */
>+#define smnMP1_FIRMWARE_FLAGS		0x3010024
>+
>+static int psp_v12_0_init_microcode(struct psp_context *psp)
>+{
>+	struct amdgpu_device *adev = psp->adev;
>+	const char *chip_name;
>+	char fw_name[30];
>+	int err = 0;
>+	const struct psp_firmware_header_v1_0 *asd_hdr;
>+
>+	DRM_DEBUG("\n");
>+
>+	switch (adev->asic_type) {
>+	case CHIP_RENOIR:
>+		chip_name = "renoir";
>+		break;
>+	default:
>+		BUG();
>+	}
>+
>+	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
>+	err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
>+	if (err)
>+		goto out1;
>+
>+	err = amdgpu_ucode_validate(adev->psp.asd_fw);
>+	if (err)
>+		goto out1;
>+
>+	asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
>+	adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
>+	adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
>+	adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
>+	adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
>+				le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
>+
>+	return 0;
>+
>+out1:
>+	release_firmware(adev->psp.asd_fw);
>+	adev->psp.asd_fw = NULL;
>+
>+	return err;
>+}
>+
>+static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
>+{
>+	int ret;
>+	uint32_t psp_gfxdrv_command_reg = 0;
>+	struct amdgpu_device *adev = psp->adev;
>+	uint32_t sol_reg;
>+
>+	/* Check sOS sign of life register to confirm sys driver and sOS
>+	 * are already been loaded.
>+	 */
>+	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
>+	if (sol_reg) {
>+		psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
>+		printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
>+		return 0;
>+	}
>+
>+	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
>+	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
>+			   0x80000000, 0x80000000, false);
>+	if (ret)
>+		return ret;
>+
>+	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
>+
>+	/* Copy PSP System Driver binary to memory */
>+	memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
>+
>+	/* Provide the sys driver to bootloader */
>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
>+	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
>+	psp_gfxdrv_command_reg = 1 << 16;
>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
>+	       psp_gfxdrv_command_reg);
>+
>+	/* there might be handshake issue with hardware which needs delay */
>+	mdelay(20);
>+
>+	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
>+			   0x80000000, 0x80000000, false);
>+
>+	return ret;
>+}
>+
>+static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
>+{
>+	int ret;
>+	unsigned int psp_gfxdrv_command_reg = 0;
>+	struct amdgpu_device *adev = psp->adev;
>+	uint32_t sol_reg;
>+
>+	/* Check sOS sign of life register to confirm sys driver and sOS
>+	 * are already been loaded.
>+	 */
>+	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
>+	if (sol_reg)
>+		return 0;
>+
>+	/* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
>+	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
>+			   0x80000000, 0x80000000, false);
>+	if (ret)
>+		return ret;
>+
>+	memset(psp->fw_pri_buf, 0, PSP_1_MEG);
>+
>+	/* Copy Secure OS binary to PSP memory */
>+	memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
>+
>+	/* Provide the PSP secure OS to bootloader */
>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
>+	       (uint32_t)(psp->fw_pri_mc_addr >> 20));
>+	psp_gfxdrv_command_reg = 2 << 16;
>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
>+	       psp_gfxdrv_command_reg);
>+
>+	/* there might be handshake issue with hardware which needs delay */
>+	mdelay(20);
>+	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
>+			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
>+			   0, true);
>+
>+	return ret;
>+}
>+
>+static void psp_v12_0_reroute_ih(struct psp_context *psp)
>+{
>+	struct amdgpu_device *adev = psp->adev;
>+	uint32_t tmp;
>+
>+	/* Change IH ring for VMC */
>+	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
>+	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
>+	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
>+
>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
>+
>+	mdelay(20);
>+	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
>+		     0x80000000, 0x8000FFFF, false);
>+
>+	/* Change IH ring for UMC */
>+	tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
>+	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
>+
>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
>+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
>+
>+	mdelay(20);
>+	psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
>+		     0x80000000, 0x8000FFFF, false);
>+}
>+
>+static int psp_v12_0_ring_init(struct psp_context *psp,
>+			      enum psp_ring_type ring_type)
>+{
>+	int ret = 0;
>+	struct psp_ring *ring;
>+	struct amdgpu_device *adev = psp->adev;
>+
>+	psp_v12_0_reroute_ih(psp);
>+
>+	ring = &psp->km_ring;
>+
>+	ring->ring_type = ring_type;
>+
>+	/* allocate 4k Page of Local Frame Buffer memory for ring */
>+	ring->ring_size = 0x1000;
>+	ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
>+				      AMDGPU_GEM_DOMAIN_VRAM,
>+				      &adev->firmware.rbuf,
>+				      &ring->ring_mem_mc_addr,
>+				      (void **)&ring->ring_mem);
>+	if (ret) {
>+		ring->ring_size = 0;
>+		return ret;
>+	}
>+
>+	return 0;
>+}
>+
>+static bool psp_v12_0_support_vmr_ring(struct psp_context *psp)
>+{
>+	if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
>+		return true;
>+	return false;
>+}
>+
>+static int psp_v12_0_ring_create(struct psp_context *psp,
>+				enum psp_ring_type ring_type)
>+{
>+	int ret = 0;
>+	unsigned int psp_ring_reg = 0;
>+	struct psp_ring *ring = &psp->km_ring;
>+	struct amdgpu_device *adev = psp->adev;
>+
>+	if (psp_v12_0_support_vmr_ring(psp)) {
>+		/* Write low address of the ring to C2PMSG_102 */
>+		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
>+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
>+		/* Write high address of the ring to C2PMSG_103 */
>+		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
>+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
>+
>+		/* Write the ring initialization command to C2PMSG_101 */
>+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
>+					     GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
>+
>+		/* there might be handshake issue with hardware which needs delay */
>+		mdelay(20);
>+
>+		/* Wait for response flag (bit 31) in C2PMSG_101 */
>+		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
>+				   0x80000000, 0x8000FFFF, false);
>+
>+	} else {
>+		/* Write low address of the ring to C2PMSG_69 */
>+		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
>+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
>+		/* Write high address of the ring to C2PMSG_70 */
>+		psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
>+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
>+		/* Write size of ring to C2PMSG_71 */
>+		psp_ring_reg = ring->ring_size;
>+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
>+		/* Write the ring initialization command to C2PMSG_64 */
>+		psp_ring_reg = ring_type;
>+		psp_ring_reg = psp_ring_reg << 16;
>+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
>+
>+		/* there might be handshake issue with hardware which needs delay */
>+		mdelay(20);
>+
>+		/* Wait for response flag (bit 31) in C2PMSG_64 */
>+		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
>+				   0x80000000, 0x8000FFFF, false);
>+	}
>+
>+	return ret;
>+}
>+
>+static int psp_v12_0_ring_stop(struct psp_context *psp,
>+			      enum psp_ring_type ring_type)
>+{
>+	int ret = 0;
>+	struct amdgpu_device *adev = psp->adev;
>+
>+	/* Write the ring destroy command*/
>+	if (psp_v12_0_support_vmr_ring(psp))
>+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
>+				     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
>+	else
>+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
>+				     GFX_CTRL_CMD_ID_DESTROY_RINGS);
>+
>+	/* there might be handshake issue with hardware which needs delay */
>+	mdelay(20);
>+
>+	/* Wait for response flag (bit 31) */
>+	if (psp_v12_0_support_vmr_ring(psp))
>+		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
>+				   0x80000000, 0x80000000, false);
>+	else
>+		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
>+				   0x80000000, 0x80000000, false);
>+
>+	return ret;
>+}
>+
>+static int psp_v12_0_ring_destroy(struct psp_context *psp,
>+				 enum psp_ring_type ring_type)
>+{
>+	int ret = 0;
>+	struct psp_ring *ring = &psp->km_ring;
>+	struct amdgpu_device *adev = psp->adev;
>+
>+	ret = psp_v12_0_ring_stop(psp, ring_type);
>+	if (ret)
>+		DRM_ERROR("Fail to stop psp ring\n");
>+
>+	amdgpu_bo_free_kernel(&adev->firmware.rbuf,
>+			      &ring->ring_mem_mc_addr,
>+			      (void **)&ring->ring_mem);
>+
>+	return ret;
>+}
>+
>+static int psp_v12_0_cmd_submit(struct psp_context *psp,
>+			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
>+			       int index)
>+{
>+	unsigned int psp_write_ptr_reg = 0;
>+	struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
>+	struct psp_ring *ring = &psp->km_ring;
>+	struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
>+	struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
>+		ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
>+	struct amdgpu_device *adev = psp->adev;
>+	uint32_t ring_size_dw = ring->ring_size / 4;
>+	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
>+
>+	/* KM (GPCOM) prepare write pointer */
>+	if (psp_v12_0_support_vmr_ring(psp))
>+		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
>+	else
>+		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
>+
>+	/* Update KM RB frame pointer to new frame */
>+	/* write_frame ptr increments by size of rb_frame in bytes */
>+	/* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
>+	if ((psp_write_ptr_reg % ring_size_dw) == 0)
>+		write_frame = ring_buffer_start;
>+	else
>+		write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
>+	/* Check invalid write_frame ptr address */
>+	if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
>+		DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
>+			  ring_buffer_start, ring_buffer_end, write_frame);
>+		DRM_ERROR("write_frame is pointing to address out of bounds\n");
>+		return -EINVAL;
>+	}
>+
>+	/* Initialize KM RB frame */
>+	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
>+
>+	/* Update KM RB frame */
>+	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
>+	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
>+	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
>+	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
>+	write_frame->fence_value = index;
>+
>+	/* Update the write Pointer in DWORDs */
>+	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
>+	if (psp_v12_0_support_vmr_ring(psp)) {
>+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
>+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
>+	} else
>+		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
>+
>+	return 0;
>+}
>+
>+static int
>+psp_v12_0_sram_map(struct amdgpu_device *adev,
>+		  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
>+		  unsigned int *sram_data_reg_offset,
>+		  enum AMDGPU_UCODE_ID ucode_id)
>+{
>+	int ret = 0;
>+
>+	switch (ucode_id) {
>+/* TODO: needs to confirm */
>+#if 0
>+	case AMDGPU_UCODE_ID_SMC:
>+		*sram_offset = 0;
>+		*sram_addr_reg_offset = 0;
>+		*sram_data_reg_offset = 0;
>+		break;
>+#endif
>+
>+	case AMDGPU_UCODE_ID_CP_CE:
>+		*sram_offset = 0x0;
>+		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
>+		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
>+		break;
>+
>+	case AMDGPU_UCODE_ID_CP_PFP:
>+		*sram_offset = 0x0;
>+		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
>+		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
>+		break;
>+
>+	case AMDGPU_UCODE_ID_CP_ME:
>+		*sram_offset = 0x0;
>+		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
>+		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
>+		break;
>+
>+	case AMDGPU_UCODE_ID_CP_MEC1:
>+		*sram_offset = 0x10000;
>+		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
>+		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
>+		break;
>+
>+	case AMDGPU_UCODE_ID_CP_MEC2:
>+		*sram_offset = 0x10000;
>+		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
>+		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
>+		break;
>+
>+	case AMDGPU_UCODE_ID_RLC_G:
>+		*sram_offset = 0x2000;
>+		*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
>+		*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
>+		break;
>+
>+	case AMDGPU_UCODE_ID_SDMA0:
>+		*sram_offset = 0x0;
>+		*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
>+		*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
>+		break;
>+
>+/* TODO: needs to confirm */
>+#if 0
>+	case AMDGPU_UCODE_ID_SDMA1:
>+		*sram_offset = ;
>+		*sram_addr_reg_offset = ;
>+		break;
>+
>+	case AMDGPU_UCODE_ID_UVD:
>+		*sram_offset = ;
>+		*sram_addr_reg_offset = ;
>+		break;
>+
>+	case AMDGPU_UCODE_ID_VCE:
>+		*sram_offset = ;
>+		*sram_addr_reg_offset = ;
>+		break;
>+#endif
>+
>+	case AMDGPU_UCODE_ID_MAXIMUM:
>+	default:
>+		ret = -EINVAL;
>+		break;
>+	}
>+
>+	return ret;
>+}
>+
>+static bool psp_v12_0_compare_sram_data(struct psp_context *psp,
>+				       struct amdgpu_firmware_info *ucode,
>+				       enum AMDGPU_UCODE_ID ucode_type)
>+{
>+	int err = 0;
>+	unsigned int fw_sram_reg_val = 0;
>+	unsigned int fw_sram_addr_reg_offset = 0;
>+	unsigned int fw_sram_data_reg_offset = 0;
>+	unsigned int ucode_size;
>+	uint32_t *ucode_mem = NULL;
>+	struct amdgpu_device *adev = psp->adev;
>+
>+	err = psp_v12_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
>+				&fw_sram_data_reg_offset, ucode_type);
>+	if (err)
>+		return false;
>+
>+	WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
>+
>+	ucode_size = ucode->ucode_size;
>+	ucode_mem = (uint32_t *)ucode->kaddr;
>+	while (ucode_size) {
>+		fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
>+
>+		if (*ucode_mem != fw_sram_reg_val)
>+			return false;
>+
>+		ucode_mem++;
>+		/* 4 bytes */
>+		ucode_size -= 4;
>+	}
>+
>+	return true;
>+}
>+
>+static int psp_v12_0_mode1_reset(struct psp_context *psp)
>+{
>+	int ret;
>+	uint32_t offset;
>+	struct amdgpu_device *adev = psp->adev;
>+
>+	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
>+
>+	ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
>+
>+	if (ret) {
>+		DRM_INFO("psp is not working correctly before mode1 reset!\n");
>+		return -EINVAL;
>+	}
>+
>+	/*send the mode 1 reset command*/
>+	WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
>+
>+	msleep(500);
>+
>+	offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
>+
>+	ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
>+
>+	if (ret) {
>+		DRM_INFO("psp mode 1 reset failed!\n");
>+		return -EINVAL;
>+	}
>+
>+	DRM_INFO("psp mode1 reset succeed \n");
>+
>+	return 0;
>+}
>+
>+static const struct psp_funcs psp_v12_0_funcs = {
>+	.init_microcode = psp_v12_0_init_microcode,
>+	.bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
>+	.bootloader_load_sos = psp_v12_0_bootloader_load_sos,
>+	.ring_init = psp_v12_0_ring_init,
>+	.ring_create = psp_v12_0_ring_create,
>+	.ring_stop = psp_v12_0_ring_stop,
>+	.ring_destroy = psp_v12_0_ring_destroy,
>+	.cmd_submit = psp_v12_0_cmd_submit,
>+	.compare_sram_data = psp_v12_0_compare_sram_data,
>+	.mode1_reset = psp_v12_0_mode1_reset,
>+};
>+
>+void psp_v12_0_set_psp_funcs(struct psp_context *psp)
>+{
>+	psp->funcs = &psp_v12_0_funcs;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v12_0.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v12_0.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v12_0.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v12_0.h	2019-08-31 15:01:12.265736204 -0500
>@@ -0,0 +1,30 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#ifndef __PSP_V12_0_H__
>+#define __PSP_V12_0_H__
>+
>+#include "amdgpu_psp.h"
>+
>+void psp_v12_0_set_psp_funcs(struct psp_context *psp);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c	2019-08-31 15:01:11.850736167 -0500
>@@ -411,7 +411,6 @@
> }
> 
> static int psp_v3_1_cmd_submit(struct psp_context *psp,
>-			       struct amdgpu_firmware_info *ucode,
> 			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
> 			       int index)
> {
>@@ -636,7 +635,7 @@
> 
> static bool psp_v3_1_support_vmr_ring(struct psp_context *psp)
> {
>-	if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version >= 0x80455)
>+	if (amdgpu_sriov_vf(psp->adev))
> 		return true;
> 
> 	return false;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c	2019-08-31 15:01:11.850736167 -0500
>@@ -34,6 +34,18 @@
> #include "sdma0/sdma0_4_2_sh_mask.h"
> #include "sdma1/sdma1_4_2_offset.h"
> #include "sdma1/sdma1_4_2_sh_mask.h"
>+#include "sdma2/sdma2_4_2_2_offset.h"
>+#include "sdma2/sdma2_4_2_2_sh_mask.h"
>+#include "sdma3/sdma3_4_2_2_offset.h"
>+#include "sdma3/sdma3_4_2_2_sh_mask.h"
>+#include "sdma4/sdma4_4_2_2_offset.h"
>+#include "sdma4/sdma4_4_2_2_sh_mask.h"
>+#include "sdma5/sdma5_4_2_2_offset.h"
>+#include "sdma5/sdma5_4_2_2_sh_mask.h"
>+#include "sdma6/sdma6_4_2_2_offset.h"
>+#include "sdma6/sdma6_4_2_2_sh_mask.h"
>+#include "sdma7/sdma7_4_2_2_offset.h"
>+#include "sdma7/sdma7_4_2_2_sh_mask.h"
> #include "hdp/hdp_4_0_offset.h"
> #include "sdma0/sdma0_4_1_default.h"
> 
>@@ -55,6 +67,8 @@
> MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
> MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
> MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
>+MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
>+MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
> 
> #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
> #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
>@@ -202,25 +216,132 @@
> 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
> };
> 
>+static const struct soc15_reg_golden golden_settings_sdma_arct[] =
>+{
>+	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
>+	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
>+	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
>+	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
>+	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
>+	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
>+	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
>+	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
>+	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002)
>+};
>+
>+static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
>+	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
>+	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
>+	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
>+	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
>+	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
>+	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
>+	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
>+	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
>+};
>+
> static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
> 		u32 instance, u32 offset)
> {
>-	return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) :
>-			(adev->reg_offset[SDMA1_HWIP][0][0] + offset));
>+	switch (instance) {
>+	case 0:
>+		return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
>+	case 1:
>+		return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
>+	case 2:
>+		return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
>+	case 3:
>+		return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
>+	case 4:
>+		return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
>+	case 5:
>+		return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
>+	case 6:
>+		return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
>+	case 7:
>+		return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
>+	default:
>+		break;
>+	}
>+	return 0;
>+}
>+
>+static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
>+{
>+	switch (seq_num) {
>+	case 0:
>+		return SOC15_IH_CLIENTID_SDMA0;
>+	case 1:
>+		return SOC15_IH_CLIENTID_SDMA1;
>+	case 2:
>+		return SOC15_IH_CLIENTID_SDMA2;
>+	case 3:
>+		return SOC15_IH_CLIENTID_SDMA3;
>+	case 4:
>+		return SOC15_IH_CLIENTID_SDMA4;
>+	case 5:
>+		return SOC15_IH_CLIENTID_SDMA5;
>+	case 6:
>+		return SOC15_IH_CLIENTID_SDMA6;
>+	case 7:
>+		return SOC15_IH_CLIENTID_SDMA7;
>+	default:
>+		break;
>+	}
>+	return -EINVAL;
>+}
>+
>+static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
>+{
>+	switch (client_id) {
>+	case SOC15_IH_CLIENTID_SDMA0:
>+		return 0;
>+	case SOC15_IH_CLIENTID_SDMA1:
>+		return 1;
>+	case SOC15_IH_CLIENTID_SDMA2:
>+		return 2;
>+	case SOC15_IH_CLIENTID_SDMA3:
>+		return 3;
>+	case SOC15_IH_CLIENTID_SDMA4:
>+		return 4;
>+	case SOC15_IH_CLIENTID_SDMA5:
>+		return 5;
>+	case SOC15_IH_CLIENTID_SDMA6:
>+		return 6;
>+	case SOC15_IH_CLIENTID_SDMA7:
>+		return 7;
>+	default:
>+		break;
>+	}
>+	return -EINVAL;
> }
> 
> static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
> {
> 	switch (adev->asic_type) {
> 	case CHIP_VEGA10:
>-		if (!amdgpu_virt_support_skip_setting(adev)) {
>-			soc15_program_register_sequence(adev,
>-							 golden_settings_sdma_4,
>-							 ARRAY_SIZE(golden_settings_sdma_4));
>-			soc15_program_register_sequence(adev,
>-							 golden_settings_sdma_vg10,
>-							 ARRAY_SIZE(golden_settings_sdma_vg10));
>-		}
>+		soc15_program_register_sequence(adev,
>+						golden_settings_sdma_4,
>+						ARRAY_SIZE(golden_settings_sdma_4));
>+		soc15_program_register_sequence(adev,
>+						golden_settings_sdma_vg10,
>+						ARRAY_SIZE(golden_settings_sdma_vg10));
> 		break;
> 	case CHIP_VEGA12:
> 		soc15_program_register_sequence(adev,
>@@ -241,6 +362,11 @@
> 						golden_settings_sdma1_4_2,
> 						ARRAY_SIZE(golden_settings_sdma1_4_2));
> 		break;
>+	case CHIP_ARCTURUS:
>+		soc15_program_register_sequence(adev,
>+						golden_settings_sdma_arct,
>+						ARRAY_SIZE(golden_settings_sdma_arct));
>+		break;
> 	case CHIP_RAVEN:
> 		soc15_program_register_sequence(adev,
> 						golden_settings_sdma_4_1,
>@@ -254,11 +380,53 @@
> 							golden_settings_sdma_rv1,
> 							ARRAY_SIZE(golden_settings_sdma_rv1));
> 		break;
>+	case CHIP_RENOIR:
>+		soc15_program_register_sequence(adev,
>+						golden_settings_sdma_4_3,
>+						ARRAY_SIZE(golden_settings_sdma_4_3));
>+		break;
> 	default:
> 		break;
> 	}
> }
> 
>+static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
>+{
>+	int err = 0;
>+	const struct sdma_firmware_header_v1_0 *hdr;
>+
>+	err = amdgpu_ucode_validate(sdma_inst->fw);
>+	if (err)
>+		return err;
>+
>+	hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
>+	sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
>+	sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
>+
>+	if (sdma_inst->feature_version >= 20)
>+		sdma_inst->burst_nop = true;
>+
>+	return 0;
>+}
>+
>+static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
>+{
>+	int i;
>+
>+	for (i = 0; i < adev->sdma.num_instances; i++) {
>+		if (adev->sdma.instance[i].fw != NULL)
>+			release_firmware(adev->sdma.instance[i].fw);
>+
>+		/* arcturus shares the same FW memory across
>+		   all SDMA isntances */
>+		if (adev->asic_type == CHIP_ARCTURUS)
>+			break;
>+	}
>+
>+	memset((void*)adev->sdma.instance, 0,
>+		sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
>+}
>+
> /**
>  * sdma_v4_0_init_microcode - load ucode images from disk
>  *
>@@ -278,7 +446,6 @@
> 	int err = 0, i;
> 	struct amdgpu_firmware_info *info = NULL;
> 	const struct common_firmware_header *header = NULL;
>-	const struct sdma_firmware_header_v1_0 *hdr;
> 
> 	DRM_DEBUG("\n");
> 
>@@ -300,30 +467,52 @@
> 		else
> 			chip_name = "raven";
> 		break;
>+	case CHIP_ARCTURUS:
>+		chip_name = "arcturus";
>+		break;
>+	case CHIP_RENOIR:
>+		chip_name = "renoir";
>+		break;
> 	default:
> 		BUG();
> 	}
> 
>-	for (i = 0; i < adev->sdma.num_instances; i++) {
>-		if (i == 0)
>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
>-		else
>-			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
>-		err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
>-		if (err)
>-			goto out;
>-		err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
>-		if (err)
>-			goto out;
>-		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
>-		adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
>-		adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
>-		if (adev->sdma.instance[i].feature_version >= 20)
>-			adev->sdma.instance[i].burst_nop = true;
>-		DRM_DEBUG("psp_load == '%s'\n",
>-				adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
>+	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
>+
>+	err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
>+	if (err)
>+		goto out;
>+
>+	err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
>+	if (err)
>+		goto out;
>+
>+	for (i = 1; i < adev->sdma.num_instances; i++) {
>+		if (adev->asic_type == CHIP_ARCTURUS) {
>+			/* Acturus will leverage the same FW memory
>+			   for every SDMA instance */
>+			memcpy((void*)&adev->sdma.instance[i],
>+			       (void*)&adev->sdma.instance[0],
>+			       sizeof(struct amdgpu_sdma_instance));
>+		}
>+		else {
>+			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
>+
>+			err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
>+			if (err)
>+				goto out;
>+
>+			err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
>+			if (err)
>+				goto out;
>+		}
>+	}
> 
>-		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>+	DRM_DEBUG("psp_load == '%s'\n",
>+		adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
>+
>+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>+		for (i = 0; i < adev->sdma.num_instances; i++) {
> 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
> 			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
> 			info->fw = adev->sdma.instance[i].fw;
>@@ -332,13 +521,11 @@
> 				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
> 		}
> 	}
>+
> out:
> 	if (err) {
> 		DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
>-		for (i = 0; i < adev->sdma.num_instances; i++) {
>-			release_firmware(adev->sdma.instance[i].fw);
>-			adev->sdma.instance[i].fw = NULL;
>-		}
>+		sdma_v4_0_destroy_inst_ctx(adev);
> 	}
> 	return err;
> }
>@@ -561,10 +748,7 @@
> 	u32 ref_and_mask = 0;
> 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
> 
>-	if (ring->me == 0)
>-		ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
>-	else
>-		ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
>+	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
> 
> 	sdma_v4_0_wait_reg_mem(ring, 0, 1,
> 			       adev->nbio_funcs->get_hdp_flush_done_offset(adev),
>@@ -620,26 +804,27 @@
>  */
> static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
> {
>-	struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
>-	struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
>+	struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
> 	u32 rb_cntl, ib_cntl;
>-	int i;
>+	int i, unset = 0;
>+
>+	for (i = 0; i < adev->sdma.num_instances; i++) {
>+		sdma[i] = &adev->sdma.instance[i].ring;
> 
>-	if ((adev->mman.buffer_funcs_ring == sdma0) ||
>-	    (adev->mman.buffer_funcs_ring == sdma1))
>+		if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
> 			amdgpu_ttm_set_buffer_funcs_status(adev, false);
>+			unset = 1;
>+		}
> 
>-	for (i = 0; i < adev->sdma.num_instances; i++) {
> 		rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
> 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
> 		WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
> 		ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
> 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
> 		WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
>-	}
> 
>-	sdma0->sched.ready = false;
>-	sdma1->sched.ready = false;
>+		sdma[i]->sched.ready = false;
>+	}
> }
> 
> /**
>@@ -663,16 +848,20 @@
>  */
> static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
> {
>-	struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].page;
>-	struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].page;
>+	struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
> 	u32 rb_cntl, ib_cntl;
> 	int i;
>-
>-	if ((adev->mman.buffer_funcs_ring == sdma0) ||
>-	    (adev->mman.buffer_funcs_ring == sdma1))
>-		amdgpu_ttm_set_buffer_funcs_status(adev, false);
>+	bool unset = false;
> 
> 	for (i = 0; i < adev->sdma.num_instances; i++) {
>+		sdma[i] = &adev->sdma.instance[i].page;
>+
>+		if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
>+			(unset == false)) {
>+			amdgpu_ttm_set_buffer_funcs_status(adev, false);
>+			unset = true;
>+		}
>+
> 		rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
> 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
> 					RB_ENABLE, 0);
>@@ -681,10 +870,9 @@
> 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
> 					IB_ENABLE, 0);
> 		WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
>-	}
> 
>-	sdma0->sched.ready = false;
>-	sdma1->sched.ready = false;
>+		sdma[i]->sched.ready = false;
>+	}
> }
> 
> /**
>@@ -1018,6 +1206,7 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_RAVEN:
>+	case CHIP_RENOIR:
> 		sdma_v4_1_init_power_gating(adev);
> 		sdma_v4_1_update_power_gating(adev, true);
> 		break;
>@@ -1473,8 +1662,10 @@
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 	int r;
> 
>-	if (adev->asic_type == CHIP_RAVEN)
>+	if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR)
> 		adev->sdma.num_instances = 1;
>+	else if (adev->asic_type == CHIP_ARCTURUS)
>+		adev->sdma.num_instances = 8;
> 	else
> 		adev->sdma.num_instances = 2;
> 
>@@ -1499,6 +1690,7 @@
> }
> 
> static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
>+		struct ras_err_data *err_data,
> 		struct amdgpu_iv_entry *entry);
> 
> static int sdma_v4_0_late_init(void *handle)
>@@ -1518,7 +1710,7 @@
> 		.sub_block_index = 0,
> 		.name = "sdma",
> 	};
>-	int r;
>+	int r, i;
> 
> 	if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
> 		amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
>@@ -1575,14 +1767,11 @@
> 	if (r)
> 		goto sysfs;
> resume:
>-	r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0);
>-	if (r)
>-		goto irq;
>-
>-	r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE1);
>-	if (r) {
>-		amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0);
>-		goto irq;
>+	for (i = 0; i < adev->sdma.num_instances; i++) {
>+		r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
>+				   AMDGPU_SDMA_IRQ_INSTANCE0 + i);
>+		if (r)
>+			goto irq;
> 	}
> 
> 	return 0;
>@@ -1606,28 +1795,22 @@
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
> 	/* SDMA trap event */
>-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP,
>-			      &adev->sdma.trap_irq);
>-	if (r)
>-		return r;
>-
>-	/* SDMA trap event */
>-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP,
>-			      &adev->sdma.trap_irq);
>-	if (r)
>-		return r;
>-
>-	/* SDMA SRAM ECC event */
>-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
>-			&adev->sdma.ecc_irq);
>-	if (r)
>-		return r;
>+	for (i = 0; i < adev->sdma.num_instances; i++) {
>+		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
>+				      SDMA0_4_0__SRCID__SDMA_TRAP,
>+				      &adev->sdma.trap_irq);
>+		if (r)
>+			return r;
>+	}
> 
> 	/* SDMA SRAM ECC event */
>-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_SRAM_ECC,
>-			&adev->sdma.ecc_irq);
>-	if (r)
>-		return r;
>+	for (i = 0; i < adev->sdma.num_instances; i++) {
>+		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
>+				      SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
>+				      &adev->sdma.ecc_irq);
>+		if (r)
>+			return r;
>+	}
> 
> 	for (i = 0; i < adev->sdma.num_instances; i++) {
> 		ring = &adev->sdma.instance[i].ring;
>@@ -1641,11 +1824,8 @@
> 		ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
> 
> 		sprintf(ring->name, "sdma%d", i);
>-		r = amdgpu_ring_init(adev, ring, 1024,
>-				     &adev->sdma.trap_irq,
>-				     (i == 0) ?
>-				     AMDGPU_SDMA_IRQ_INSTANCE0 :
>-				     AMDGPU_SDMA_IRQ_INSTANCE1);
>+		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
>+				     AMDGPU_SDMA_IRQ_INSTANCE0 + i);
> 		if (r)
> 			return r;
> 
>@@ -1663,9 +1843,7 @@
> 			sprintf(ring->name, "page%d", i);
> 			r = amdgpu_ring_init(adev, ring, 1024,
> 					     &adev->sdma.trap_irq,
>-					     (i == 0) ?
>-					     AMDGPU_SDMA_IRQ_INSTANCE0 :
>-					     AMDGPU_SDMA_IRQ_INSTANCE1);
>+					     AMDGPU_SDMA_IRQ_INSTANCE0 + i);
> 			if (r)
> 				return r;
> 		}
>@@ -1701,10 +1879,7 @@
> 			amdgpu_ring_fini(&adev->sdma.instance[i].page);
> 	}
> 
>-	for (i = 0; i < adev->sdma.num_instances; i++) {
>-		release_firmware(adev->sdma.instance[i].fw);
>-		adev->sdma.instance[i].fw = NULL;
>-	}
>+	sdma_v4_0_destroy_inst_ctx(adev);
> 
> 	return 0;
> }
>@@ -1718,7 +1893,8 @@
> 			adev->powerplay.pp_funcs->set_powergating_by_smu)
> 		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
> 
>-	sdma_v4_0_init_golden_registers(adev);
>+	if (!amdgpu_sriov_vf(adev))
>+		sdma_v4_0_init_golden_registers(adev);
> 
> 	r = sdma_v4_0_start(adev);
> 
>@@ -1728,12 +1904,15 @@
> static int sdma_v4_0_hw_fini(void *handle)
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+	int i;
> 
> 	if (amdgpu_sriov_vf(adev))
> 		return 0;
> 
>-	amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE0);
>-	amdgpu_irq_put(adev, &adev->sdma.ecc_irq, AMDGPU_SDMA_IRQ_INSTANCE1);
>+	for (i = 0; i < adev->sdma.num_instances; i++) {
>+		amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
>+			       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
>+	}
> 
> 	sdma_v4_0_ctx_switch_enable(adev, false);
> 	sdma_v4_0_enable(adev, false);
>@@ -1776,15 +1955,17 @@
> 
> static int sdma_v4_0_wait_for_idle(void *handle)
> {
>-	unsigned i;
>-	u32 sdma0, sdma1;
>+	unsigned i, j;
>+	u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
> 	for (i = 0; i < adev->usec_timeout; i++) {
>-		sdma0 = RREG32_SDMA(0, mmSDMA0_STATUS_REG);
>-		sdma1 = RREG32_SDMA(1, mmSDMA0_STATUS_REG);
>-
>-		if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
>+		for (j = 0; j < adev->sdma.num_instances; j++) {
>+			sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
>+			if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
>+				break;
>+		}
>+		if (j == adev->sdma.num_instances)
> 			return 0;
> 		udelay(1);
> 	}
>@@ -1820,17 +2001,7 @@
> 	uint32_t instance;
> 
> 	DRM_DEBUG("IH: SDMA trap\n");
>-	switch (entry->client_id) {
>-	case SOC15_IH_CLIENTID_SDMA0:
>-		instance = 0;
>-		break;
>-	case SOC15_IH_CLIENTID_SDMA1:
>-		instance = 1;
>-		break;
>-	default:
>-		return 0;
>-	}
>-
>+	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
> 	switch (entry->ring_id) {
> 	case 0:
> 		amdgpu_fence_process(&adev->sdma.instance[instance].ring);
>@@ -1851,20 +2022,15 @@
> }
> 
> static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
>+		struct ras_err_data *err_data,
> 		struct amdgpu_iv_entry *entry)
> {
>-	uint32_t instance, err_source;
>+	uint32_t err_source;
>+	int instance;
> 
>-	switch (entry->client_id) {
>-	case SOC15_IH_CLIENTID_SDMA0:
>-		instance = 0;
>-		break;
>-	case SOC15_IH_CLIENTID_SDMA1:
>-		instance = 1;
>-		break;
>-	default:
>+	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
>+	if (instance < 0)
> 		return 0;
>-	}
> 
> 	switch (entry->src_id) {
> 	case SDMA0_4_0__SRCID__SDMA_SRAM_ECC:
>@@ -1881,7 +2047,7 @@
> 
> 	amdgpu_ras_reset_gpu(adev, 0);
> 
>-	return AMDGPU_RAS_UE;
>+	return AMDGPU_RAS_SUCCESS;
> }
> 
> static int sdma_v4_0_process_ecc_irq(struct amdgpu_device *adev,
>@@ -1910,16 +2076,9 @@
> 
> 	DRM_ERROR("Illegal instruction in SDMA command stream\n");
> 
>-	switch (entry->client_id) {
>-	case SOC15_IH_CLIENTID_SDMA0:
>-		instance = 0;
>-		break;
>-	case SOC15_IH_CLIENTID_SDMA1:
>-		instance = 1;
>-		break;
>-	default:
>+	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
>+	if (instance < 0)
> 		return 0;
>-	}
> 
> 	switch (entry->ring_id) {
> 	case 0:
>@@ -1936,14 +2095,10 @@
> {
> 	u32 sdma_edc_config;
> 
>-	u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
>-		sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_EDC_CONFIG) :
>-		sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_EDC_CONFIG);
>-
>-	sdma_edc_config = RREG32(reg_offset);
>+	sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
> 	sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
> 		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
>-	WREG32(reg_offset, sdma_edc_config);
>+	WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
> 
> 	return 0;
> }
>@@ -1953,61 +2108,35 @@
> 		bool enable)
> {
> 	uint32_t data, def;
>+	int i;
> 
> 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
>-		/* enable sdma0 clock gating */
>-		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
>-		data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
>-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
>-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
>-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
>-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
>-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
>-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
>-			  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
>-		if (def != data)
>-			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
>-
>-		if (adev->sdma.num_instances > 1) {
>-			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
>-			data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
>-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
>-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
>-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
>-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
>-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
>-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
>-				  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
>+		for (i = 0; i < adev->sdma.num_instances; i++) {
>+			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
>+			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
>+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
>+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
>+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
>+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
>+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
>+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
>+				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
> 			if (def != data)
>-				WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
>+				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
> 		}
> 	} else {
>-		/* disable sdma0 clock gating */
>-		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
>-		data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
>-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
>-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
>-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
>-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
>-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
>-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
>-			 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
>-
>-		if (def != data)
>-			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
>-
>-		if (adev->sdma.num_instances > 1) {
>-			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
>-			data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
>-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
>-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
>-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
>-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
>-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
>-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
>-				 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
>+		for (i = 0; i < adev->sdma.num_instances; i++) {
>+			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
>+			data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
>+				 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
>+				 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
>+				 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
>+				 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
>+				 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
>+				 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
>+				 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
> 			if (def != data)
>-				WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
>+				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
> 		}
> 	}
> }
>@@ -2018,34 +2147,23 @@
> 		bool enable)
> {
> 	uint32_t data, def;
>+	int i;
> 
> 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
>-		/* 1-not override: enable sdma0 mem light sleep */
>-		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
>-		data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
>-		if (def != data)
>-			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
>-
>-		/* 1-not override: enable sdma1 mem light sleep */
>-		if (adev->sdma.num_instances > 1) {
>-			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
>-			data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
>+		for (i = 0; i < adev->sdma.num_instances; i++) {
>+			/* 1-not override: enable sdma mem light sleep */
>+			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
>+			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
> 			if (def != data)
>-				WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
>+				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
> 		}
> 	} else {
>-		/* 0-override:disable sdma0 mem light sleep */
>-		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
>-		data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
>-		if (def != data)
>-			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
>-
>-		/* 0-override:disable sdma1 mem light sleep */
>-		if (adev->sdma.num_instances > 1) {
>-			def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
>-			data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
>+		for (i = 0; i < adev->sdma.num_instances; i++) {
>+		/* 0-override:disable sdma mem light sleep */
>+			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
>+			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
> 			if (def != data)
>-				WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
>+				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
> 		}
> 	}
> }
>@@ -2063,6 +2181,8 @@
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
> 	case CHIP_RAVEN:
>+	case CHIP_ARCTURUS:
>+	case CHIP_RENOIR:
> 		sdma_v4_0_update_medium_grain_clock_gating(adev,
> 				state == AMD_CG_STATE_GATE ? true : false);
> 		sdma_v4_0_update_medium_grain_light_sleep(adev,
>@@ -2133,7 +2253,43 @@
> 	.align_mask = 0xf,
> 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
> 	.support_64bit_ptrs = true,
>-	.vmhub = AMDGPU_MMHUB,
>+	.vmhub = AMDGPU_MMHUB_0,
>+	.get_rptr = sdma_v4_0_ring_get_rptr,
>+	.get_wptr = sdma_v4_0_ring_get_wptr,
>+	.set_wptr = sdma_v4_0_ring_set_wptr,
>+	.emit_frame_size =
>+		6 + /* sdma_v4_0_ring_emit_hdp_flush */
>+		3 + /* hdp invalidate */
>+		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
>+		/* sdma_v4_0_ring_emit_vm_flush */
>+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
>+		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
>+		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
>+	.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
>+	.emit_ib = sdma_v4_0_ring_emit_ib,
>+	.emit_fence = sdma_v4_0_ring_emit_fence,
>+	.emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
>+	.emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
>+	.emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
>+	.test_ring = sdma_v4_0_ring_test_ring,
>+	.test_ib = sdma_v4_0_ring_test_ib,
>+	.insert_nop = sdma_v4_0_ring_insert_nop,
>+	.pad_ib = sdma_v4_0_ring_pad_ib,
>+	.emit_wreg = sdma_v4_0_ring_emit_wreg,
>+	.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
>+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
>+};
>+
>+/*
>+ * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
>+ * So create a individual constant ring_funcs for those instances.
>+ */
>+static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
>+	.type = AMDGPU_RING_TYPE_SDMA,
>+	.align_mask = 0xf,
>+	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
>+	.support_64bit_ptrs = true,
>+	.vmhub = AMDGPU_MMHUB_1,
> 	.get_rptr = sdma_v4_0_ring_get_rptr,
> 	.get_wptr = sdma_v4_0_ring_get_wptr,
> 	.set_wptr = sdma_v4_0_ring_set_wptr,
>@@ -2165,7 +2321,39 @@
> 	.align_mask = 0xf,
> 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
> 	.support_64bit_ptrs = true,
>-	.vmhub = AMDGPU_MMHUB,
>+	.vmhub = AMDGPU_MMHUB_0,
>+	.get_rptr = sdma_v4_0_ring_get_rptr,
>+	.get_wptr = sdma_v4_0_page_ring_get_wptr,
>+	.set_wptr = sdma_v4_0_page_ring_set_wptr,
>+	.emit_frame_size =
>+		6 + /* sdma_v4_0_ring_emit_hdp_flush */
>+		3 + /* hdp invalidate */
>+		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
>+		/* sdma_v4_0_ring_emit_vm_flush */
>+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
>+		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
>+		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
>+	.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
>+	.emit_ib = sdma_v4_0_ring_emit_ib,
>+	.emit_fence = sdma_v4_0_ring_emit_fence,
>+	.emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
>+	.emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
>+	.emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
>+	.test_ring = sdma_v4_0_ring_test_ring,
>+	.test_ib = sdma_v4_0_ring_test_ib,
>+	.insert_nop = sdma_v4_0_ring_insert_nop,
>+	.pad_ib = sdma_v4_0_ring_pad_ib,
>+	.emit_wreg = sdma_v4_0_ring_emit_wreg,
>+	.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
>+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
>+};
>+
>+static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
>+	.type = AMDGPU_RING_TYPE_SDMA,
>+	.align_mask = 0xf,
>+	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
>+	.support_64bit_ptrs = true,
>+	.vmhub = AMDGPU_MMHUB_1,
> 	.get_rptr = sdma_v4_0_ring_get_rptr,
> 	.get_wptr = sdma_v4_0_page_ring_get_wptr,
> 	.set_wptr = sdma_v4_0_page_ring_set_wptr,
>@@ -2197,10 +2385,20 @@
> 	int i;
> 
> 	for (i = 0; i < adev->sdma.num_instances; i++) {
>-		adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
>+		if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
>+			adev->sdma.instance[i].ring.funcs =
>+					&sdma_v4_0_ring_funcs_2nd_mmhub;
>+		else
>+			adev->sdma.instance[i].ring.funcs =
>+					&sdma_v4_0_ring_funcs;
> 		adev->sdma.instance[i].ring.me = i;
> 		if (adev->sdma.has_page_queue) {
>-			adev->sdma.instance[i].page.funcs = &sdma_v4_0_page_ring_funcs;
>+			if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
>+				adev->sdma.instance[i].page.funcs =
>+					&sdma_v4_0_page_ring_funcs_2nd_mmhub;
>+			else
>+				adev->sdma.instance[i].page.funcs =
>+					&sdma_v4_0_page_ring_funcs;
> 			adev->sdma.instance[i].page.me = i;
> 		}
> 	}
>@@ -2224,10 +2422,23 @@
> 
> static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
> {
>-	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
>+	switch (adev->sdma.num_instances) {
>+	case 1:
>+		adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
>+		adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
>+		break;
>+	case 8:
>+		adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
>+		adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
>+		break;
>+	case 2:
>+	default:
>+		adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
>+		adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
>+		break;
>+	}
> 	adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
> 	adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
>-	adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
> 	adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
> }
> 
>@@ -2293,8 +2504,8 @@
> static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
> {
> 	adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
>-	if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1)
>-		adev->mman.buffer_funcs_ring = &adev->sdma.instance[1].page;
>+	if (adev->sdma.has_page_queue)
>+		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
> 	else
> 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
> }
>@@ -2313,22 +2524,15 @@
> 	unsigned i;
> 
> 	adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
>-	if (adev->sdma.has_page_queue && adev->sdma.num_instances > 1) {
>-		for (i = 1; i < adev->sdma.num_instances; i++) {
>+	for (i = 0; i < adev->sdma.num_instances; i++) {
>+		if (adev->sdma.has_page_queue)
> 			sched = &adev->sdma.instance[i].page.sched;
>-			adev->vm_manager.vm_pte_rqs[i - 1] =
>-				&sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
>-		}
>-		adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances - 1;
>-		adev->vm_manager.page_fault = &adev->sdma.instance[0].page;
>-	} else {
>-		for (i = 0; i < adev->sdma.num_instances; i++) {
>+		else
> 			sched = &adev->sdma.instance[i].ring.sched;
>-			adev->vm_manager.vm_pte_rqs[i] =
>-				&sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
>-		}
>-		adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
>+		adev->vm_manager.vm_pte_rqs[i] =
>+			&sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
> 	}
>+	adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
> }
> 
> const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c	2019-08-31 15:01:11.850736167 -0500
>@@ -21,8 +21,11 @@
>  *
>  */
> 
>+#include <linux/delay.h>
> #include <linux/firmware.h>
>-#include <drm/drmP.h>
>+#include <linux/module.h>
>+#include <linux/pci.h>
>+
> #include "amdgpu.h"
> #include "amdgpu_ucode.h"
> #include "amdgpu_trace.h"
>@@ -42,6 +45,12 @@
> MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
> MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
> 
>+MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
>+MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
>+
>+MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
>+MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
>+
> #define SDMA1_REG_OFFSET 0x600
> #define SDMA0_HYP_DEC_REG_START 0x5880
> #define SDMA0_HYP_DEC_REG_END 0x5893
>@@ -59,7 +68,7 @@
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
>-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
>@@ -71,7 +80,7 @@
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
>-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
> 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
>@@ -80,6 +89,18 @@
> };
> 
> static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
>+};
>+
>+static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
>+};
>+
>+static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
>+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
> };
> 
> static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
>@@ -111,6 +132,22 @@
> 						golden_settings_sdma_nv10,
> 						(const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
> 		break;
>+	case CHIP_NAVI14:
>+		soc15_program_register_sequence(adev,
>+						golden_settings_sdma_5,
>+						(const u32)ARRAY_SIZE(golden_settings_sdma_5));
>+		soc15_program_register_sequence(adev,
>+						golden_settings_sdma_nv14,
>+						(const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
>+		break;
>+	case CHIP_NAVI12:
>+		soc15_program_register_sequence(adev,
>+						golden_settings_sdma_5,
>+						(const u32)ARRAY_SIZE(golden_settings_sdma_5));
>+		soc15_program_register_sequence(adev,
>+						golden_settings_sdma_nv12,
>+						(const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
>+		break;
> 	default:
> 		break;
> 	}
>@@ -143,6 +180,12 @@
> 	case CHIP_NAVI10:
> 		chip_name = "navi10";
> 		break;
>+	case CHIP_NAVI14:
>+		chip_name = "navi14";
>+		break;
>+	case CHIP_NAVI12:
>+		chip_name = "navi12";
>+		break;
> 	default:
> 		BUG();
> 	}
>@@ -861,7 +904,7 @@
> 		if (amdgpu_emu_mode == 1)
> 			msleep(1);
> 		else
>-			DRM_UDELAY(1);
>+			udelay(1);
> 	}
> 
> 	if (i < adev->usec_timeout) {
>@@ -1316,7 +1359,7 @@
> 		if (ring->trail_seq ==
> 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
> 			break;
>-		DRM_UDELAY(1);
>+		udelay(1);
> 	}
> 
> 	if (i >= adev->usec_timeout) {
>@@ -1472,6 +1515,8 @@
> 
> 	switch (adev->asic_type) {
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		sdma_v5_0_update_medium_grain_clock_gating(adev,
> 				state == AMD_CG_STATE_GATE ? true : false);
> 		sdma_v5_0_update_medium_grain_light_sleep(adev,
>@@ -1532,7 +1577,7 @@
> 	.align_mask = 0xf,
> 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
> 	.support_64bit_ptrs = true,
>-	.vmhub = AMDGPU_GFXHUB,
>+	.vmhub = AMDGPU_GFXHUB_0,
> 	.get_rptr = sdma_v5_0_ring_get_rptr,
> 	.get_wptr = sdma_v5_0_ring_get_wptr,
> 	.set_wptr = sdma_v5_0_ring_set_wptr,
>@@ -1583,7 +1628,8 @@
> 
> static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
> {
>-	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
>+	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
>+					adev->sdma.num_instances;
> 	adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
> 	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/si.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/si.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/si.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/si.c	2019-08-31 15:01:11.850736167 -0500
>@@ -1186,6 +1186,12 @@
> 	return 0;
> }
> 
>+static enum amd_reset_method
>+si_asic_reset_method(struct amdgpu_device *adev)
>+{
>+	return AMD_RESET_METHOD_LEGACY;
>+}
>+
> static u32 si_get_config_memsize(struct amdgpu_device *adev)
> {
> 	return RREG32(mmCONFIG_MEMSIZE);
>@@ -1394,6 +1400,7 @@
> 	.read_bios_from_rom = &si_read_bios_from_rom,
> 	.read_register = &si_read_register,
> 	.reset = &si_asic_reset,
>+	.reset_method = &si_asic_reset_method,
> 	.set_vga_state = &si_vga_set_state,
> 	.get_xclk = &si_get_xclk,
> 	.set_uvd_clocks = &si_set_uvd_clocks,
>@@ -1881,7 +1888,7 @@
> 			if (orig != data)
> 				si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
> 
>-			if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
>+			if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) {
> 				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
> 				data &= ~PLL_RAMP_UP_TIME_0_MASK;
> 				if (orig != data)
>@@ -1930,14 +1937,14 @@
> 
> 			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
> 			data &= ~LS2_EXIT_TIME_MASK;
>-			if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
>+			if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN))
> 				data |= LS2_EXIT_TIME(5);
> 			if (orig != data)
> 				si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
> 
> 			orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
> 			data &= ~LS2_EXIT_TIME_MASK;
>-			if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
>+			if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN))
> 				data |= LS2_EXIT_TIME(5);
> 			if (orig != data)
> 				si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c	2019-08-31 15:01:11.850736167 -0500
>@@ -0,0 +1,724 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include "smuio/smuio_11_0_0_offset.h"
>+#include "smuio/smuio_11_0_0_sh_mask.h"
>+
>+#include "smu_v11_0_i2c.h"
>+#include "amdgpu.h"
>+#include "soc15_common.h"
>+#include <drm/drm_fixed.h>
>+#include <drm/drm_drv.h>
>+#include "amdgpu_amdkfd.h"
>+#include <linux/i2c.h>
>+#include <linux/pci.h>
>+#include "amdgpu_ras.h"
>+
>+/* error codes */
>+#define I2C_OK                0
>+#define I2C_NAK_7B_ADDR_NOACK 1
>+#define I2C_NAK_TXDATA_NOACK  2
>+#define I2C_TIMEOUT           4
>+#define I2C_SW_TIMEOUT        8
>+#define I2C_ABORT             0x10
>+
>+/* I2C transaction flags */
>+#define I2C_NO_STOP	1
>+#define I2C_RESTART	2
>+
>+#define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control.eeprom_accessor))->adev
>+#define to_eeprom_control(x) container_of(x, struct amdgpu_ras_eeprom_control, eeprom_accessor)
>+
>+static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+	uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);
>+
>+	reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);
>+	WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg);
>+}
>+
>+
>+static void smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+
>+	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0);
>+}
>+
>+static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+	/* do */
>+	{
>+		RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR);
>+
>+	} /* while (reg_CKSVII2C_ic_clr_intr == 0) */
>+}
>+
>+static void smu_v11_0_i2c_configure(struct i2c_adapter *control)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+	uint32_t reg = 0;
>+
>+	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);
>+	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1);
>+	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0);
>+	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0);
>+	/* Standard mode */
>+	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE, 2);
>+	reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1);
>+
>+	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg);
>+}
>+
>+static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+
>+	/*
>+	 * Standard mode speed, These values are taken from SMUIO MAS,
>+	 * but are different from what is given is
>+	 * Synopsys spec. The values here are based on assumption
>+	 * that refclock is 100MHz
>+	 *
>+	 * Configuration for standard mode; Speed = 100kbps
>+	 * Scale linearly, for now only support standard speed clock
>+	 * This will work only with 100M ref clock
>+	 *
>+	 * TBD:Change the calculation to take into account ref clock values also.
>+	 */
>+
>+	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2);
>+	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120);
>+	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130);
>+	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20);
>+}
>+
>+static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, uint8_t address)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+
>+	/* Convert fromr 8-bit to 7-bit address */
>+	address >>= 1;
>+	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, (address & 0xFF));
>+}
>+
>+static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+	uint32_t ret = I2C_OK;
>+	uint32_t reg, reg_c_tx_abrt_source;
>+
>+	/*Check if transmission is completed */
>+	unsigned long  timeout_counter = jiffies + msecs_to_jiffies(20);
>+
>+	do {
>+		if (time_after(jiffies, timeout_counter)) {
>+			ret |= I2C_SW_TIMEOUT;
>+			break;
>+		}
>+
>+		reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
>+
>+	} while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0);
>+
>+	if (ret != I2C_OK)
>+		return ret;
>+
>+	/* This only checks if NAK is received and transaction got aborted */
>+	reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT);
>+
>+	if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) {
>+		reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
>+		DRM_INFO("TX was terminated, IC_TX_ABRT_SOURCE val is:%x", reg_c_tx_abrt_source);
>+
>+		/* Check for stop due to NACK */
>+		if (REG_GET_FIELD(reg_c_tx_abrt_source,
>+				  CKSVII2C_IC_TX_ABRT_SOURCE,
>+				  ABRT_TXDATA_NOACK) == 1) {
>+
>+			ret |= I2C_NAK_TXDATA_NOACK;
>+
>+		} else if (REG_GET_FIELD(reg_c_tx_abrt_source,
>+					 CKSVII2C_IC_TX_ABRT_SOURCE,
>+					 ABRT_7B_ADDR_NOACK) == 1) {
>+
>+			ret |= I2C_NAK_7B_ADDR_NOACK;
>+		} else {
>+			ret |= I2C_ABORT;
>+		}
>+
>+		smu_v11_0_i2c_clear_status(control);
>+	}
>+
>+	return ret;
>+}
>+
>+static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+	uint32_t ret = I2C_OK;
>+	uint32_t reg_ic_status, reg_c_tx_abrt_source;
>+
>+	reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE);
>+
>+	/* If slave is not present */
>+	if (REG_GET_FIELD(reg_c_tx_abrt_source,
>+			  CKSVII2C_IC_TX_ABRT_SOURCE,
>+			  ABRT_7B_ADDR_NOACK) == 1) {
>+		ret |= I2C_NAK_7B_ADDR_NOACK;
>+
>+		smu_v11_0_i2c_clear_status(control);
>+	} else {  /* wait till some data is there in RXFIFO */
>+		/* Poll for some byte in RXFIFO */
>+		unsigned long  timeout_counter = jiffies + msecs_to_jiffies(20);
>+
>+		do {
>+			if (time_after(jiffies, timeout_counter)) {
>+				ret |= I2C_SW_TIMEOUT;
>+				break;
>+			}
>+
>+			reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
>+
>+		} while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0);
>+	}
>+
>+	return ret;
>+}
>+
>+
>+
>+
>+/**
>+ * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device.
>+ *
>+ * @address: The I2C address of the slave device.
>+ * @data: The data to transmit over the bus.
>+ * @numbytes: The amount of data to transmit.
>+ * @i2c_flag: Flags for transmission
>+ *
>+ * Returns 0 on success or error.
>+ */
>+static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control,
>+				  uint8_t address, uint8_t *data,
>+				  uint32_t numbytes, uint32_t i2c_flag)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+	uint32_t bytes_sent, reg, ret = 0;
>+	unsigned long  timeout_counter;
>+
>+	bytes_sent = 0;
>+
>+	DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ",
>+		 (uint16_t)address, numbytes);
>+
>+	if (drm_debug & DRM_UT_DRIVER) {
>+		print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
>+			       16, 1, data, numbytes, false);
>+	}
>+
>+	/* Set the I2C slave address */
>+	smu_v11_0_i2c_set_address(control, address);
>+	/* Enable I2C */
>+	smu_v11_0_i2c_enable(control, true);
>+
>+	/* Clear status bits */
>+	smu_v11_0_i2c_clear_status(control);
>+
>+
>+	timeout_counter = jiffies + msecs_to_jiffies(20);
>+
>+	while (numbytes > 0) {
>+		reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
>+		if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) {
>+			do {
>+				reg = 0;
>+				/*
>+				 * Prepare transaction, no need to set RESTART. I2C engine will send
>+				 * START as soon as it sees data in TXFIFO
>+				 */
>+				if (bytes_sent == 0)
>+					reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART,
>+							    (i2c_flag & I2C_RESTART) ? 1 : 0);
>+				reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]);
>+
>+				/* determine if we need to send STOP bit or not */
>+				if (numbytes == 1)
>+					/* Final transaction, so send stop unless I2C_NO_STOP */
>+					reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP,
>+							    (i2c_flag & I2C_NO_STOP) ? 0 : 1);
>+				/* Write */
>+				reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0);
>+				WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
>+
>+				/* Record that the bytes were transmitted */
>+				bytes_sent++;
>+				numbytes--;
>+
>+				reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS);
>+
>+			} while (numbytes &&  REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF));
>+		}
>+
>+		/*
>+		 * We waited too long for the transmission FIFO to become not-full.
>+		 * Exit the loop with error.
>+		 */
>+		if (time_after(jiffies, timeout_counter)) {
>+			ret |= I2C_SW_TIMEOUT;
>+			goto Err;
>+		}
>+	}
>+
>+	ret = smu_v11_0_i2c_poll_tx_status(control);
>+
>+Err:
>+	/* Any error, no point in proceeding */
>+	if (ret != I2C_OK) {
>+		if (ret & I2C_SW_TIMEOUT)
>+			DRM_ERROR("TIMEOUT ERROR !!!");
>+
>+		if (ret & I2C_NAK_7B_ADDR_NOACK)
>+			DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
>+
>+
>+		if (ret & I2C_NAK_TXDATA_NOACK)
>+			DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
>+	}
>+
>+	return ret;
>+}
>+
>+
>+/**
>+ * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device.
>+ *
>+ * @address: The I2C address of the slave device.
>+ * @numbytes: The amount of data to transmit.
>+ * @i2c_flag: Flags for transmission
>+ *
>+ * Returns 0 on success or error.
>+ */
>+static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control,
>+				 uint8_t address, uint8_t *data,
>+				 uint32_t numbytes, uint8_t i2c_flag)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+	uint32_t bytes_received, ret = I2C_OK;
>+
>+	bytes_received = 0;
>+
>+	/* Set the I2C slave address */
>+	smu_v11_0_i2c_set_address(control, address);
>+
>+	/* Enable I2C */
>+	smu_v11_0_i2c_enable(control, true);
>+
>+	while (numbytes > 0) {
>+		uint32_t reg = 0;
>+
>+		smu_v11_0_i2c_clear_status(control);
>+
>+
>+		/* Prepare transaction */
>+
>+		/* Each time we disable I2C, so this is not a restart */
>+		if (bytes_received == 0)
>+			reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART,
>+					    (i2c_flag & I2C_RESTART) ? 1 : 0);
>+
>+		reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0);
>+		/* Read */
>+		reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1);
>+
>+		/* Transmitting last byte */
>+		if (numbytes == 1)
>+			/* Final transaction, so send stop if requested */
>+			reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP,
>+					    (i2c_flag & I2C_NO_STOP) ? 0 : 1);
>+
>+		WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg);
>+
>+		ret = smu_v11_0_i2c_poll_rx_status(control);
>+
>+		/* Any error, no point in proceeding */
>+		if (ret != I2C_OK) {
>+			if (ret & I2C_SW_TIMEOUT)
>+				DRM_ERROR("TIMEOUT ERROR !!!");
>+
>+			if (ret & I2C_NAK_7B_ADDR_NOACK)
>+				DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!");
>+
>+			if (ret & I2C_NAK_TXDATA_NOACK)
>+				DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!");
>+
>+			break;
>+		}
>+
>+		reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD);
>+		data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT);
>+
>+		/* Record that the bytes were received */
>+		bytes_received++;
>+		numbytes--;
>+	}
>+
>+	DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :",
>+		  (uint16_t)address, bytes_received);
>+
>+	if (drm_debug & DRM_UT_DRIVER) {
>+		print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE,
>+			       16, 1, data, bytes_received, false);
>+	}
>+
>+	return ret;
>+}
>+
>+static void smu_v11_0_i2c_abort(struct i2c_adapter *control)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+	uint32_t reg = 0;
>+
>+	/* Enable I2C engine; */
>+	reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);
>+	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
>+
>+	/* Abort previous transaction */
>+	reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1);
>+	WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg);
>+
>+	DRM_DEBUG_DRIVER("I2C_Abort() Done.");
>+}
>+
>+
>+static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+
>+	const uint32_t IDLE_TIMEOUT = 1024;
>+	uint32_t timeout_count = 0;
>+	uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity;
>+
>+	reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
>+	reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
>+
>+
>+	if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
>+	    (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
>+		/*
>+		 * Nobody is using I2C engine, but engine remains active because
>+		 * someone missed to send STOP
>+		 */
>+		smu_v11_0_i2c_abort(control);
>+	} else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) {
>+		/* Nobody is using I2C engine */
>+		return true;
>+	}
>+
>+	/* Keep reading activity bit until it's cleared */
>+	do {
>+		reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY);
>+
>+		if (REG_GET_FIELD(reg_ic_clr_activity,
>+		    CKSVII2C_IC_CLR_ACTIVITY, CLR_ACTIVITY) == 0)
>+			return true;
>+
>+		++timeout_count;
>+
>+	} while (timeout_count < IDLE_TIMEOUT);
>+
>+	return false;
>+}
>+
>+static void smu_v11_0_i2c_init(struct i2c_adapter *control)
>+{
>+	/* Disable clock gating */
>+	smu_v11_0_i2c_set_clock_gating(control, false);
>+
>+	if (!smu_v11_0_i2c_activity_done(control))
>+		DRM_WARN("I2C busy !");
>+
>+	/* Disable I2C */
>+	smu_v11_0_i2c_enable(control, false);
>+
>+	/* Configure I2C to operate as master and in standard mode */
>+	smu_v11_0_i2c_configure(control);
>+
>+	/* Initialize the clock to 50 kHz default */
>+	smu_v11_0_i2c_set_clock(control);
>+
>+}
>+
>+static void smu_v11_0_i2c_fini(struct i2c_adapter *control)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+	uint32_t reg_ic_enable_status, reg_ic_enable;
>+
>+	smu_v11_0_i2c_enable(control, false);
>+
>+	/* Double check if disabled, else force abort */
>+	reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS);
>+	reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE);
>+
>+	if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&
>+	    (REG_GET_FIELD(reg_ic_enable_status,
>+			   CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) {
>+		/*
>+		 * Nobody is using I2C engine, but engine remains active because
>+		 * someone missed to send STOP
>+		 */
>+		smu_v11_0_i2c_abort(control);
>+	}
>+
>+	/* Restore clock gating */
>+	smu_v11_0_i2c_set_clock_gating(control, true);
>+
>+}
>+
>+static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+
>+	/* Send  PPSMC_MSG_RequestI2CBus */
>+	if (!adev->powerplay.pp_funcs->smu_i2c_bus_access)
>+		goto Fail;
>+
>+
>+	if (!adev->powerplay.pp_funcs->smu_i2c_bus_access(adev->powerplay.pp_handle, true))
>+		return true;
>+
>+Fail:
>+	return false;
>+}
>+
>+static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+
>+	/* Send  PPSMC_MSG_RequestI2CBus */
>+	if (!adev->powerplay.pp_funcs->smu_i2c_bus_access)
>+		goto Fail;
>+
>+	/* Send  PPSMC_MSG_ReleaseI2CBus */
>+	if (!adev->powerplay.pp_funcs->smu_i2c_bus_access(adev->powerplay.pp_handle,
>+							     false))
>+		return true;
>+
>+Fail:
>+	return false;
>+}
>+
>+/***************************** EEPROM I2C GLUE ****************************/
>+
>+static uint32_t smu_v11_0_i2c_eeprom_read_data(struct i2c_adapter *control,
>+					       uint8_t address,
>+					       uint8_t *data,
>+					       uint32_t numbytes)
>+{
>+	uint32_t  ret = 0;
>+
>+	/* First 2 bytes are dummy write to set EEPROM address */
>+	ret = smu_v11_0_i2c_transmit(control, address, data, 2, I2C_NO_STOP);
>+	if (ret != I2C_OK)
>+		goto Fail;
>+
>+	/* Now read data starting with that address */
>+	ret = smu_v11_0_i2c_receive(control, address, data + 2, numbytes - 2,
>+				    I2C_RESTART);
>+
>+Fail:
>+	if (ret != I2C_OK)
>+		DRM_ERROR("ReadData() - I2C error occurred :%x", ret);
>+
>+	return ret;
>+}
>+
>+static uint32_t smu_v11_0_i2c_eeprom_write_data(struct i2c_adapter *control,
>+						uint8_t address,
>+						uint8_t *data,
>+						uint32_t numbytes)
>+{
>+	uint32_t  ret;
>+
>+	ret = smu_v11_0_i2c_transmit(control, address, data, numbytes, 0);
>+
>+	if (ret != I2C_OK)
>+		DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret);
>+	else
>+		/*
>+		 * According to EEPROM spec there is a MAX of 10 ms required for
>+		 * EEPROM to flush internal RX buffer after STOP was issued at the
>+		 * end of write transaction. During this time the EEPROM will not be
>+		 * responsive to any more commands - so wait a bit more.
>+		 *
>+		 * TODO Improve to wait for first ACK for slave address after
>+		 * internal write cycle done.
>+		 */
>+		msleep(10);
>+
>+	return ret;
>+
>+}
>+
>+static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
>+{
>+	struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c);
>+
>+	if (!smu_v11_0_i2c_bus_lock(i2c)) {
>+		DRM_ERROR("Failed to lock the bus from SMU");
>+		return;
>+	}
>+
>+	control->bus_locked = true;
>+}
>+
>+static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
>+{
>+	WARN_ONCE(1, "This operation not supposed to run in atomic context!");
>+	return false;
>+}
>+
>+static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
>+{
>+	struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c);
>+
>+	if (!smu_v11_0_i2c_bus_unlock(i2c)) {
>+		DRM_ERROR("Failed to unlock the bus from SMU");
>+		return;
>+	}
>+
>+	control->bus_locked = false;
>+}
>+
>+static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = {
>+	.lock_bus = lock_bus,
>+	.trylock_bus = trylock_bus,
>+	.unlock_bus = unlock_bus,
>+};
>+
>+static int smu_v11_0_i2c_eeprom_i2c_xfer(struct i2c_adapter *i2c_adap,
>+			      struct i2c_msg *msgs, int num)
>+{
>+	int i, ret;
>+	struct amdgpu_ras_eeprom_control *control = to_eeprom_control(i2c_adap);
>+
>+	if (!control->bus_locked) {
>+		DRM_ERROR("I2C bus unlocked, stopping transaction!");
>+		return -EIO;
>+	}
>+
>+	smu_v11_0_i2c_init(i2c_adap);
>+
>+	for (i = 0; i < num; i++) {
>+		if (msgs[i].flags & I2C_M_RD)
>+			ret = smu_v11_0_i2c_eeprom_read_data(i2c_adap,
>+							(uint8_t)msgs[i].addr,
>+							msgs[i].buf, msgs[i].len);
>+		else
>+			ret = smu_v11_0_i2c_eeprom_write_data(i2c_adap,
>+							 (uint8_t)msgs[i].addr,
>+							 msgs[i].buf, msgs[i].len);
>+
>+		if (ret != I2C_OK) {
>+			num = -EIO;
>+			break;
>+		}
>+	}
>+
>+	smu_v11_0_i2c_fini(i2c_adap);
>+	return num;
>+}
>+
>+static u32 smu_v11_0_i2c_eeprom_i2c_func(struct i2c_adapter *adap)
>+{
>+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
>+}
>+
>+
>+static const struct i2c_algorithm smu_v11_0_i2c_eeprom_i2c_algo = {
>+	.master_xfer = smu_v11_0_i2c_eeprom_i2c_xfer,
>+	.functionality = smu_v11_0_i2c_eeprom_i2c_func,
>+};
>+
>+int smu_v11_0_i2c_eeprom_control_init(struct i2c_adapter *control)
>+{
>+	struct amdgpu_device *adev = to_amdgpu_device(control);
>+	int res;
>+
>+	control->owner = THIS_MODULE;
>+	control->class = I2C_CLASS_SPD;
>+	control->dev.parent = &adev->pdev->dev;
>+	control->algo = &smu_v11_0_i2c_eeprom_i2c_algo;
>+	snprintf(control->name, sizeof(control->name), "RAS EEPROM");
>+	control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops;
>+
>+	res = i2c_add_adapter(control);
>+	if (res)
>+		DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
>+
>+	return res;
>+}
>+
>+void smu_v11_0_i2c_eeprom_control_fini(struct i2c_adapter *control)
>+{
>+	i2c_del_adapter(control);
>+}
>+
>+/*
>+ * Keep this for future unit test if bugs arise
>+ */
>+#if 0
>+#define I2C_TARGET_ADDR 0xA0
>+
>+bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control)
>+{
>+
>+	uint32_t ret = I2C_OK;
>+	uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef};
>+
>+
>+	DRM_INFO("Begin");
>+
>+	if (!smu_v11_0_i2c_bus_lock(control)) {
>+		DRM_ERROR("Failed to lock the bus!.");
>+		return false;
>+	}
>+
>+	smu_v11_0_i2c_init(control);
>+
>+	/* Write 0xde to address 0x0000 on the EEPROM */
>+	ret = smu_v11_0_i2c_eeprom_write_data(control, I2C_TARGET_ADDR, data, 6);
>+
>+	ret = smu_v11_0_i2c_eeprom_read_data(control, I2C_TARGET_ADDR, data, 6);
>+
>+	smu_v11_0_i2c_fini(control);
>+
>+	smu_v11_0_i2c_bus_unlock(control);
>+
>+
>+	DRM_INFO("End");
>+	return true;
>+}
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h	2019-08-31 15:01:11.851736168 -0500
>@@ -0,0 +1,34 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef SMU_V11_I2C_CONTROL_H
>+#define SMU_V11_I2C_CONTROL_H
>+
>+#include <linux/types.h>
>+
>+struct i2c_adapter;
>+
>+int smu_v11_0_i2c_eeprom_control_init(struct i2c_adapter *control);
>+void smu_v11_0_i2c_eeprom_control_fini(struct i2c_adapter *control);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/soc15.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/soc15.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/soc15.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/soc15.c	2019-08-31 15:08:53.346776943 -0500
>@@ -63,6 +63,8 @@
> #include "uvd_v7_0.h"
> #include "vce_v4_0.h"
> #include "vcn_v1_0.h"
>+#include "vcn_v2_0.h"
>+#include "vcn_v2_5.h"
> #include "dce_virtual.h"
> #include "mxgpu_ai.h"
> #include "amdgpu_smu.h"
>@@ -115,6 +117,49 @@
> 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
> }
> 
>+static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
>+{
>+	unsigned long flags, address, data;
>+	u64 r;
>+	address = adev->nbio_funcs->get_pcie_index_offset(adev);
>+	data = adev->nbio_funcs->get_pcie_data_offset(adev);
>+
>+	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
>+	/* read low 32 bit */
>+	WREG32(address, reg);
>+	(void)RREG32(address);
>+	r = RREG32(data);
>+
>+	/* read high 32 bit*/
>+	WREG32(address, reg + 4);
>+	(void)RREG32(address);
>+	r |= ((u64)RREG32(data) << 32);
>+	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
>+	return r;
>+}
>+
>+static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
>+{
>+	unsigned long flags, address, data;
>+
>+	address = adev->nbio_funcs->get_pcie_index_offset(adev);
>+	data = adev->nbio_funcs->get_pcie_data_offset(adev);
>+
>+	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
>+	/* write low 32 bit */
>+	WREG32(address, reg);
>+	(void)RREG32(address);
>+	WREG32(data, (u32)(v & 0xffffffffULL));
>+	(void)RREG32(data);
>+
>+	/* write high 32 bit */
>+	WREG32(address, reg + 4);
>+	(void)RREG32(address);
>+	WREG32(data, (u32)(v >> 32));
>+	(void)RREG32(data);
>+	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
>+}
>+
> static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
> {
> 	unsigned long flags, address, data;
>@@ -464,12 +509,23 @@
> 	return 0;
> }
> 
>-static int soc15_asic_reset(struct amdgpu_device *adev)
>+static int soc15_mode2_reset(struct amdgpu_device *adev)
>+{
>+	if (!adev->powerplay.pp_funcs ||
>+	    !adev->powerplay.pp_funcs->asic_reset_mode_2)
>+		return -ENOENT;
>+
>+	return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle);
>+}
>+
>+static enum amd_reset_method
>+soc15_asic_reset_method(struct amdgpu_device *adev)
> {
>-	int ret;
> 	bool baco_reset;
> 
> 	switch (adev->asic_type) {
>+	case CHIP_RAVEN:
>+		return AMD_RESET_METHOD_MODE2;
> 	case CHIP_VEGA10:
> 	case CHIP_VEGA12:
> 		soc15_asic_get_baco_capability(adev, &baco_reset);
>@@ -493,11 +549,23 @@
> 	}
> 
> 	if (baco_reset)
>-		ret = soc15_asic_baco_reset(adev);
>+		return AMD_RESET_METHOD_BACO;
> 	else
>-		ret = soc15_asic_mode1_reset(adev);
>+		return AMD_RESET_METHOD_MODE1;
>+}
> 
>-	return ret;
>+static int soc15_asic_reset(struct amdgpu_device *adev)
>+{
>+	switch (soc15_asic_reset_method(adev)) {
>+		case AMD_RESET_METHOD_BACO:
>+			amdgpu_inc_vram_lost(adev);
>+			return soc15_asic_baco_reset(adev);
>+		case AMD_RESET_METHOD_MODE2:
>+			return soc15_mode2_reset(adev);
>+		default:
>+			amdgpu_inc_vram_lost(adev);
>+			return soc15_asic_mode1_reset(adev);
>+	}
> }
> 
> /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
>@@ -581,26 +649,31 @@
> 	case CHIP_VEGA10:
> 	case CHIP_VEGA12:
> 	case CHIP_RAVEN:
>+	case CHIP_RENOIR:
> 		vega10_reg_base_init(adev);
> 		break;
> 	case CHIP_VEGA20:
> 		vega20_reg_base_init(adev);
> 		break;
>+	case CHIP_ARCTURUS:
>+		arct_reg_base_init(adev);
>+		break;
> 	default:
> 		return -EINVAL;
> 	}
> 
>-	if (adev->asic_type == CHIP_VEGA20)
>+	if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
> 		adev->gmc.xgmi.supported = true;
> 
> 	if (adev->flags & AMD_IS_APU)
> 		adev->nbio_funcs = &nbio_v7_0_funcs;
>-	else if (adev->asic_type == CHIP_VEGA20)
>+	else if (adev->asic_type == CHIP_VEGA20 ||
>+		adev->asic_type == CHIP_ARCTURUS)
> 		adev->nbio_funcs = &nbio_v7_4_funcs;
> 	else
> 		adev->nbio_funcs = &nbio_v6_1_funcs;
> 
>-	if (adev->asic_type == CHIP_VEGA20)
>+	if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
> 		adev->df_funcs = &df_v3_6_funcs;
> 	else
> 		adev->df_funcs = &df_v1_7_funcs;
>@@ -672,6 +745,37 @@
> #endif
> 		amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
> 		break;
>+	case CHIP_ARCTURUS:
>+		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
>+		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
>+		amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
>+		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
>+			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
>+		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
>+		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
>+		amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
>+		amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
>+		break;
>+	case CHIP_RENOIR:
>+		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
>+		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
>+		amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
>+		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
>+			amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
>+		if (is_support_sw_smu(adev))
>+			amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
>+		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
>+		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
>+		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
>+			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
>+#if defined(CONFIG_DRM_AMD_DC)
>+                else if (amdgpu_device_has_dc_support(adev))
>+                        amdgpu_device_ip_block_add(adev, &dm_ip_block);
>+#else
>+#       warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
>+#endif
>+		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
>+		break;
> 	default:
> 		return -EINVAL;
> 	}
>@@ -688,7 +792,7 @@
> 				 struct amdgpu_ring *ring)
> {
> 	if (!ring || !ring->funcs->emit_wreg)
>-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
>+		WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
> 	else
> 		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
> 			HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
>@@ -714,14 +818,9 @@
> 
> 	/* Set the 2 events that we wish to watch, defined above */
> 	/* Reg 40 is # received msgs */
>+	/* Reg 104 is # of posted requests sent */
> 	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
>-	/* Pre-VG20, Reg 104 is # of posted requests sent. On VG20 it's 108 */
>-	if (adev->asic_type == CHIP_VEGA20)
>-		perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
>-					EVENT1_SEL, 108);
>-	else
>-		perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK,
>-					EVENT1_SEL, 104);
>+	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
> 
> 	/* Write to enable desired perf counters */
> 	WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
>@@ -751,6 +850,55 @@
> 	*count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
> }
> 
>+static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
>+				 uint64_t *count1)
>+{
>+	uint32_t perfctr = 0;
>+	uint64_t cnt0_of, cnt1_of;
>+	int tmp;
>+
>+	/* This reports 0 on APUs, so return to avoid writing/reading registers
>+	 * that may or may not be different from their GPU counterparts
>+	 */
>+	if (adev->flags & AMD_IS_APU)
>+		return;
>+
>+	/* Set the 2 events that we wish to watch, defined above */
>+	/* Reg 40 is # received msgs */
>+	/* Reg 108 is # of posted requests sent on VG20 */
>+	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
>+				EVENT0_SEL, 40);
>+	perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
>+				EVENT1_SEL, 108);
>+
>+	/* Write to enable desired perf counters */
>+	WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
>+	/* Zero out and enable the perf counters
>+	 * Write 0x5:
>+	 * Bit 0 = Start all counters(1)
>+	 * Bit 2 = Global counter reset enable(1)
>+	 */
>+	WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
>+
>+	msleep(1000);
>+
>+	/* Load the shadow and disable the perf counters
>+	 * Write 0x2:
>+	 * Bit 0 = Stop counters(0)
>+	 * Bit 1 = Load the shadow counters(1)
>+	 */
>+	WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
>+
>+	/* Read register values to get any >32bit overflow */
>+	tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
>+	cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
>+	cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
>+
>+	/* Get the values and add the overflow */
>+	*count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
>+	*count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
>+}
>+
> static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
> {
> 	u32 sol_reg;
>@@ -792,6 +940,7 @@
> 	.read_bios_from_rom = &soc15_read_bios_from_rom,
> 	.read_register = &soc15_read_register,
> 	.reset = &soc15_asic_reset,
>+	.reset_method = &soc15_asic_reset_method,
> 	.set_vga_state = &soc15_vga_set_state,
> 	.get_xclk = &soc15_get_xclk,
> 	.set_uvd_clocks = &soc15_set_uvd_clocks,
>@@ -821,9 +970,10 @@
> 	.invalidate_hdp = &soc15_invalidate_hdp,
> 	.need_full_reset = &soc15_need_full_reset,
> 	.init_doorbell_index = &vega20_doorbell_index_init,
>-	.get_pcie_usage = &soc15_get_pcie_usage,
>+	.get_pcie_usage = &vega20_get_pcie_usage,
> 	.need_reset_on_init = &soc15_need_reset_on_init,
> 	.get_pcie_replay_count = &soc15_get_pcie_replay_count,
>+	.reset_method = &soc15_asic_reset_method
> };
> 
> static int soc15_common_early_init(void *handle)
>@@ -837,6 +987,8 @@
> 	adev->smc_wreg = NULL;
> 	adev->pcie_rreg = &soc15_pcie_rreg;
> 	adev->pcie_wreg = &soc15_pcie_wreg;
>+	adev->pcie_rreg64 = &soc15_pcie_rreg64;
>+	adev->pcie_wreg64 = &soc15_pcie_wreg64;
> 	adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
> 	adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
> 	adev->didt_rreg = &soc15_didt_rreg;
>@@ -993,6 +1145,53 @@
> 			adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
> 		}
> 		break;
>+	case CHIP_ARCTURUS:
>+		adev->asic_funcs = &vega20_asic_funcs;
>+		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
>+			AMD_CG_SUPPORT_GFX_MGLS |
>+			AMD_CG_SUPPORT_GFX_CGCG |
>+			AMD_CG_SUPPORT_GFX_CGLS |
>+			AMD_CG_SUPPORT_GFX_CP_LS |
>+			AMD_CG_SUPPORT_HDP_MGCG |
>+			AMD_CG_SUPPORT_HDP_LS |
>+			AMD_CG_SUPPORT_SDMA_MGCG |
>+			AMD_CG_SUPPORT_SDMA_LS |
>+			AMD_CG_SUPPORT_MC_MGCG |
>+			AMD_CG_SUPPORT_MC_LS;
>+		adev->pg_flags = 0;
>+		adev->external_rev_id = adev->rev_id + 0x32;
>+		break;
>+	case CHIP_RENOIR:
>+		adev->asic_funcs = &soc15_asic_funcs;
>+		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
>+				 AMD_CG_SUPPORT_GFX_MGLS |
>+				 AMD_CG_SUPPORT_GFX_3D_CGCG |
>+				 AMD_CG_SUPPORT_GFX_3D_CGLS |
>+				 AMD_CG_SUPPORT_GFX_CGCG |
>+				 AMD_CG_SUPPORT_GFX_CGLS |
>+				 AMD_CG_SUPPORT_GFX_CP_LS |
>+				 AMD_CG_SUPPORT_MC_MGCG |
>+				 AMD_CG_SUPPORT_MC_LS |
>+				 AMD_CG_SUPPORT_SDMA_MGCG |
>+				 AMD_CG_SUPPORT_SDMA_LS |
>+				 AMD_CG_SUPPORT_BIF_LS |
>+				 AMD_CG_SUPPORT_HDP_LS |
>+				 AMD_CG_SUPPORT_ROM_MGCG |
>+				 AMD_CG_SUPPORT_VCN_MGCG |
>+				 AMD_CG_SUPPORT_IH_CG |
>+				 AMD_CG_SUPPORT_ATHUB_LS |
>+				 AMD_CG_SUPPORT_ATHUB_MGCG |
>+				 AMD_CG_SUPPORT_DF_MGCG;
>+		adev->pg_flags = AMD_PG_SUPPORT_SDMA |
>+				 AMD_PG_SUPPORT_VCN |
>+				 AMD_PG_SUPPORT_VCN_DPG;
>+		adev->external_rev_id = adev->rev_id + 0x91;
>+
>+		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
>+			adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
>+				AMD_PG_SUPPORT_CP |
>+				AMD_PG_SUPPORT_RLC_SMU_HS;
>+		break;
> 	default:
> 		/* FIXME: not supported yet */
> 		return -EINVAL;
>@@ -1038,21 +1237,18 @@
> 	int i;
> 	struct amdgpu_ring *ring;
> 
>-	/*  Two reasons to skip
>-	*		1, Host driver already programmed them
>-	*		2, To avoid registers program violations in SR-IOV
>-	*/
>-	if (!amdgpu_virt_support_skip_setting(adev)) {
>+	/* sdma/ih doorbell range are programed by hypervisor */
>+	if (!amdgpu_sriov_vf(adev)) {
> 		for (i = 0; i < adev->sdma.num_instances; i++) {
> 			ring = &adev->sdma.instance[i].ring;
> 			adev->nbio_funcs->sdma_doorbell_range(adev, i,
> 				ring->use_doorbell, ring->doorbell_index,
> 				adev->doorbell_index.sdma_doorbell_range);
> 		}
>-	}
> 
>-	adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
>+		adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
> 						adev->irq.ih.doorbell_index);
>+	}
> }
> 
> static int soc15_common_hw_init(void *handle)
>@@ -1129,7 +1325,8 @@
> {
> 	uint32_t def, data;
> 
>-	if (adev->asic_type == CHIP_VEGA20) {
>+	if (adev->asic_type == CHIP_VEGA20 ||
>+		adev->asic_type == CHIP_ARCTURUS) {
> 		def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
> 
> 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
>@@ -1248,6 +1445,7 @@
> 				state == AMD_CG_STATE_GATE ? true : false);
> 		break;
> 	case CHIP_RAVEN:
>+	case CHIP_RENOIR:
> 		adev->nbio_funcs->update_medium_grain_clock_gating(adev,
> 				state == AMD_CG_STATE_GATE ? true : false);
> 		adev->nbio_funcs->update_medium_grain_light_sleep(adev,
>@@ -1261,6 +1459,10 @@
> 		soc15_update_rom_medium_grain_clock_gating(adev,
> 				state == AMD_CG_STATE_GATE ? true : false);
> 		break;
>+	case CHIP_ARCTURUS:
>+		soc15_update_hdp_light_sleep(adev,
>+				state == AMD_CG_STATE_GATE ? true : false);
>+		break;
> 	default:
> 		break;
> 	}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/soc15_common.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/soc15_common.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/soc15_common.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/soc15_common.h	2019-08-31 15:01:11.851736168 -0500
>@@ -69,9 +69,10 @@
> 		}						\
> 	} while (0)
> 
>+#define AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(a) (amdgpu_sriov_vf((a)) && !amdgpu_sriov_runtime((a)))
> #define WREG32_RLC(reg, value) \
> 	do {							\
>-		if (amdgpu_virt_support_rlc_prg_reg(adev)) {    \
>+		if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) {    \
> 			uint32_t i = 0;	\
> 			uint32_t retries = 50000;	\
> 			uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0;	\
>@@ -96,7 +97,7 @@
> #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
> 	do {							\
> 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
>-		if (amdgpu_virt_support_rlc_prg_reg(adev)) {    \
>+		if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) {    \
> 			uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2;	\
> 			uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3;	\
> 			uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;   \
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/soc15.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/soc15.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/soc15.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/soc15.h	2019-08-31 15:01:11.851736168 -0500
>@@ -77,6 +77,7 @@
> 
> int vega10_reg_base_init(struct amdgpu_device *adev);
> int vega20_reg_base_init(struct amdgpu_device *adev);
>+int arct_reg_base_init(struct amdgpu_device *adev);
> 
> void vega10_doorbell_index_init(struct amdgpu_device *adev);
> void vega20_doorbell_index_init(struct amdgpu_device *adev);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c	2019-08-31 15:01:11.851736168 -0500
>@@ -0,0 +1,255 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#include "umc_v6_1.h"
>+#include "amdgpu_ras.h"
>+#include "amdgpu.h"
>+
>+#include "rsmu/rsmu_0_0_2_offset.h"
>+#include "rsmu/rsmu_0_0_2_sh_mask.h"
>+#include "umc/umc_6_1_1_offset.h"
>+#include "umc/umc_6_1_1_sh_mask.h"
>+
>+#define smnMCA_UMC0_MCUMC_ADDRT0	0x50f10
>+
>+/*
>+ * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
>+ * is the index of 8KB block
>+ */
>+#define ADDR_OF_8KB_BLOCK(addr)		(((addr) & ~0xffULL) << 5)
>+/* channel index is the index of 256B block */
>+#define ADDR_OF_256B_BLOCK(channel_index)	((channel_index) << 8)
>+/* offset in 256B block */
>+#define OFFSET_IN_256B_BLOCK(addr)		((addr) & 0xffULL)
>+
>+const uint32_t
>+	umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = {
>+		{2, 18, 11, 27},	{4, 20, 13, 29},
>+		{1, 17, 8, 24},		{7, 23, 14, 30},
>+		{10, 26, 3, 19},	{12, 28, 5, 21},
>+		{9, 25, 0, 16},		{15, 31, 6, 22}
>+};
>+
>+static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev,
>+					   uint32_t umc_instance)
>+{
>+	uint32_t rsmu_umc_index;
>+
>+	rsmu_umc_index = RREG32_SOC15(RSMU, 0,
>+			mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU);
>+	rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
>+			RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
>+			RSMU_UMC_INDEX_MODE_EN, 1);
>+	rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
>+			RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
>+			RSMU_UMC_INDEX_INSTANCE, umc_instance);
>+	rsmu_umc_index = REG_SET_FIELD(rsmu_umc_index,
>+			RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
>+			RSMU_UMC_INDEX_WREN, 1 << umc_instance);
>+	WREG32_SOC15(RSMU, 0, mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
>+				rsmu_umc_index);
>+}
>+
>+static void umc_v6_1_disable_umc_index_mode(struct amdgpu_device *adev)
>+{
>+	WREG32_FIELD15(RSMU, 0, RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
>+			RSMU_UMC_INDEX_MODE_EN, 0);
>+}
>+
>+static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev,
>+						   uint32_t umc_reg_offset,
>+						   unsigned long *error_count)
>+{
>+	uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
>+	uint32_t ecc_err_cnt, ecc_err_cnt_addr;
>+	uint64_t mc_umc_status;
>+	uint32_t mc_umc_status_addr;
>+
>+	ecc_err_cnt_sel_addr =
>+		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
>+	ecc_err_cnt_addr =
>+		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
>+	mc_umc_status_addr =
>+		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
>+
>+	/* select the lower chip and check the error count */
>+	ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
>+	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
>+					EccErrCntCsSel, 0);
>+	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
>+	ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
>+	*error_count +=
>+		(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
>+		 UMC_V6_1_CE_CNT_INIT);
>+	/* clear the lower chip err count */
>+	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
>+
>+	/* select the higher chip and check the err counter */
>+	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
>+					EccErrCntCsSel, 1);
>+	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
>+	ecc_err_cnt = RREG32(ecc_err_cnt_addr + umc_reg_offset);
>+	*error_count +=
>+		(REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) -
>+		 UMC_V6_1_CE_CNT_INIT);
>+	/* clear the higher chip err count */
>+	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
>+
>+	/* check for SRAM correctable error
>+	  MCUMC_STATUS is a 64 bit register */
>+	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
>+	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&
>+	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
>+	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
>+		*error_count += 1;
>+}
>+
>+static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev,
>+						      uint32_t umc_reg_offset,
>+						      unsigned long *error_count)
>+{
>+	uint64_t mc_umc_status;
>+	uint32_t mc_umc_status_addr;
>+
>+	mc_umc_status_addr =
>+                SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
>+
>+	/* check the MCUMC_STATUS */
>+	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
>+	if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
>+	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
>+	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
>+	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
>+	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
>+	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
>+		*error_count += 1;
>+}
>+
>+static void umc_v6_1_query_error_count(struct amdgpu_device *adev,
>+					   struct ras_err_data *err_data, uint32_t umc_reg_offset,
>+					   uint32_t channel_index)
>+{
>+	umc_v6_1_query_correctable_error_count(adev, umc_reg_offset,
>+						   &(err_data->ce_count));
>+	umc_v6_1_querry_uncorrectable_error_count(adev, umc_reg_offset,
>+						  &(err_data->ue_count));
>+}
>+
>+static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev,
>+					   void *ras_error_status)
>+{
>+	amdgpu_umc_for_each_channel(umc_v6_1_query_error_count);
>+}
>+
>+static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
>+					 struct ras_err_data *err_data,
>+					 uint32_t umc_reg_offset, uint32_t channel_index)
>+{
>+	uint32_t lsb, mc_umc_status_addr;
>+	uint64_t mc_umc_status, err_addr;
>+
>+	mc_umc_status_addr =
>+		SOC15_REG_OFFSET(UMC, 0, mmMCA_UMC_UMC0_MCUMC_STATUST0);
>+
>+	/* skip error address process if -ENOMEM */
>+	if (!err_data->err_addr) {
>+		/* clear umc status */
>+		WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
>+		return;
>+	}
>+
>+	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);
>+
>+	/* calculate error address if ue/ce error is detected */
>+	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
>+	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
>+	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
>+		err_addr = RREG64_PCIE(smnMCA_UMC0_MCUMC_ADDRT0 + umc_reg_offset * 4);
>+
>+		/* the lowest lsb bits should be ignored */
>+		lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB);
>+		err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
>+		err_addr &= ~((0x1ULL << lsb) - 1);
>+
>+		/* translate umc channel address to soc pa, 3 parts are included */
>+		err_data->err_addr[err_data->err_addr_cnt] =
>+						ADDR_OF_8KB_BLOCK(err_addr) |
>+						ADDR_OF_256B_BLOCK(channel_index) |
>+						OFFSET_IN_256B_BLOCK(err_addr);
>+
>+		err_data->err_addr_cnt++;
>+	}
>+
>+	/* clear umc status */
>+	WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);
>+}
>+
>+static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
>+					     void *ras_error_status)
>+{
>+	amdgpu_umc_for_each_channel(umc_v6_1_query_error_address);
>+}
>+
>+static void umc_v6_1_ras_init_per_channel(struct amdgpu_device *adev,
>+					 struct ras_err_data *err_data,
>+					 uint32_t umc_reg_offset, uint32_t channel_index)
>+{
>+	uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
>+	uint32_t ecc_err_cnt_addr;
>+
>+	ecc_err_cnt_sel_addr =
>+		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel);
>+	ecc_err_cnt_addr =
>+		SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt);
>+
>+	/* select the lower chip and check the error count */
>+	ecc_err_cnt_sel = RREG32(ecc_err_cnt_sel_addr + umc_reg_offset);
>+	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
>+					EccErrCntCsSel, 0);
>+	/* set ce error interrupt type to APIC based interrupt */
>+	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
>+					EccErrInt, 0x1);
>+	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
>+	/* set error count to initial value */
>+	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
>+
>+	/* select the higher chip and check the err counter */
>+	ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_EccErrCntSel,
>+					EccErrCntCsSel, 1);
>+	WREG32(ecc_err_cnt_sel_addr + umc_reg_offset, ecc_err_cnt_sel);
>+	WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
>+}
>+
>+static void umc_v6_1_ras_init(struct amdgpu_device *adev)
>+{
>+	void *ras_error_status = NULL;
>+
>+	amdgpu_umc_for_each_channel(umc_v6_1_ras_init_per_channel);
>+}
>+
>+const struct amdgpu_umc_funcs umc_v6_1_funcs = {
>+	.ras_init = umc_v6_1_ras_init,
>+	.query_ras_error_count = umc_v6_1_query_ras_error_count,
>+	.query_ras_error_address = umc_v6_1_query_ras_error_address,
>+	.enable_umc_index_mode = umc_v6_1_enable_umc_index_mode,
>+	.disable_umc_index_mode = umc_v6_1_disable_umc_index_mode,
>+};
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h	2019-08-31 15:01:11.851736168 -0500
>@@ -0,0 +1,51 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#ifndef __UMC_V6_1_H__
>+#define __UMC_V6_1_H__
>+
>+#include "soc15_common.h"
>+#include "amdgpu.h"
>+
>+/* HBM  Memory Channel Width */
>+#define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH	128
>+/* number of umc channel instance with memory map register access */
>+#define UMC_V6_1_CHANNEL_INSTANCE_NUM		4
>+/* number of umc instance with memory map register access */
>+#define UMC_V6_1_UMC_INSTANCE_NUM		8
>+/* total channel instances in one umc block */
>+#define UMC_V6_1_TOTAL_CHANNEL_NUM	(UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)
>+/* UMC regiser per channel offset */
>+#define UMC_V6_1_PER_CHANNEL_OFFSET		0x800
>+
>+/* EccErrCnt max value */
>+#define UMC_V6_1_CE_CNT_MAX		0xffff
>+/* umc ce interrupt threshold */
>+#define UMC_V6_1_CE_INT_THRESHOLD	0xffff
>+/* umc ce count initial value */
>+#define UMC_V6_1_CE_CNT_INIT	(UMC_V6_1_CE_CNT_MAX - UMC_V6_1_CE_INT_THRESHOLD)
>+
>+extern const struct amdgpu_umc_funcs umc_v6_1_funcs;
>+extern const uint32_t
>+	umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM];
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c	2019-08-31 15:01:11.851736168 -0500
>@@ -1763,7 +1763,7 @@
> 	.align_mask = 0xf,
> 	.support_64bit_ptrs = false,
> 	.no_user_fence = true,
>-	.vmhub = AMDGPU_MMHUB,
>+	.vmhub = AMDGPU_MMHUB_0,
> 	.get_rptr = uvd_v7_0_ring_get_rptr,
> 	.get_wptr = uvd_v7_0_ring_get_wptr,
> 	.set_wptr = uvd_v7_0_ring_set_wptr,
>@@ -1796,7 +1796,7 @@
> 	.nop = HEVC_ENC_CMD_NO_OP,
> 	.support_64bit_ptrs = false,
> 	.no_user_fence = true,
>-	.vmhub = AMDGPU_MMHUB,
>+	.vmhub = AMDGPU_MMHUB_0,
> 	.get_rptr = uvd_v7_0_enc_ring_get_rptr,
> 	.get_wptr = uvd_v7_0_enc_ring_get_wptr,
> 	.set_wptr = uvd_v7_0_enc_ring_set_wptr,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c	2019-08-31 15:01:11.851736168 -0500
>@@ -1070,7 +1070,7 @@
> 	.nop = VCE_CMD_NO_OP,
> 	.support_64bit_ptrs = false,
> 	.no_user_fence = true,
>-	.vmhub = AMDGPU_MMHUB,
>+	.vmhub = AMDGPU_MMHUB_0,
> 	.get_rptr = vce_v4_0_ring_get_rptr,
> 	.get_wptr = vce_v4_0_ring_get_wptr,
> 	.set_wptr = vce_v4_0_ring_set_wptr,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c	2019-08-31 15:01:11.851736168 -0500
>@@ -63,6 +63,7 @@
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
>+	adev->vcn.num_vcn_inst = 1;
> 	adev->vcn.num_enc_rings = 2;
> 
> 	vcn_v1_0_set_dec_ring_funcs(adev);
>@@ -87,20 +88,21 @@
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
> 	/* VCN DEC TRAP */
>-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq);
>+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
>+			VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
> 	if (r)
> 		return r;
> 
> 	/* VCN ENC TRAP */
> 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
>-					&adev->vcn.irq);
>+					&adev->vcn.inst->irq);
> 		if (r)
> 			return r;
> 	}
> 
> 	/* VCN JPEG TRAP */
>-	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq);
>+	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.inst->irq);
> 	if (r)
> 		return r;
> 
>@@ -122,39 +124,39 @@
> 	if (r)
> 		return r;
> 
>-	ring = &adev->vcn.ring_dec;
>+	ring = &adev->vcn.inst->ring_dec;
> 	sprintf(ring->name, "vcn_dec");
>-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
>+	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
> 	if (r)
> 		return r;
> 
>-	adev->vcn.internal.scratch9 = adev->vcn.external.scratch9 =
>+	adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 =
> 		SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
>-	adev->vcn.internal.data0 = adev->vcn.external.data0 =
>+	adev->vcn.internal.data0 = adev->vcn.inst->external.data0 =
> 		SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
>-	adev->vcn.internal.data1 = adev->vcn.external.data1 =
>+	adev->vcn.internal.data1 = adev->vcn.inst->external.data1 =
> 		SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
>-	adev->vcn.internal.cmd = adev->vcn.external.cmd =
>+	adev->vcn.internal.cmd = adev->vcn.inst->external.cmd =
> 		SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
>-	adev->vcn.internal.nop = adev->vcn.external.nop =
>+	adev->vcn.internal.nop = adev->vcn.inst->external.nop =
> 		SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
> 
> 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>-		ring = &adev->vcn.ring_enc[i];
>+		ring = &adev->vcn.inst->ring_enc[i];
> 		sprintf(ring->name, "vcn_enc%d", i);
>-		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
>+		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
> 		if (r)
> 			return r;
> 	}
> 
>-	ring = &adev->vcn.ring_jpeg;
>+	ring = &adev->vcn.inst->ring_jpeg;
> 	sprintf(ring->name, "vcn_jpeg");
>-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
>+	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
> 	if (r)
> 		return r;
> 
> 	adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
>-	adev->vcn.internal.jpeg_pitch = adev->vcn.external.jpeg_pitch =
>+	adev->vcn.internal.jpeg_pitch = adev->vcn.inst->external.jpeg_pitch =
> 		SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
> 
> 	return 0;
>@@ -191,7 +193,7 @@
> static int vcn_v1_0_hw_init(void *handle)
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
>+	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
> 	int i, r;
> 
> 	r = amdgpu_ring_test_helper(ring);
>@@ -199,14 +201,14 @@
> 		goto done;
> 
> 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>-		ring = &adev->vcn.ring_enc[i];
>+		ring = &adev->vcn.inst->ring_enc[i];
> 		ring->sched.ready = true;
> 		r = amdgpu_ring_test_helper(ring);
> 		if (r)
> 			goto done;
> 	}
> 
>-	ring = &adev->vcn.ring_jpeg;
>+	ring = &adev->vcn.inst->ring_jpeg;
> 	r = amdgpu_ring_test_helper(ring);
> 	if (r)
> 		goto done;
>@@ -229,7 +231,7 @@
> static int vcn_v1_0_hw_fini(void *handle)
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
>+	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
> 
> 	if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> 		RREG32_SOC15(VCN, 0, mmUVD_STATUS))
>@@ -304,9 +306,9 @@
> 		offset = 0;
> 	} else {
> 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
>-			lower_32_bits(adev->vcn.gpu_addr));
>+			lower_32_bits(adev->vcn.inst->gpu_addr));
> 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
>-			upper_32_bits(adev->vcn.gpu_addr));
>+			upper_32_bits(adev->vcn.inst->gpu_addr));
> 		offset = size;
> 		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
> 			     AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
>@@ -316,17 +318,17 @@
> 
> 	/* cache window 1: stack */
> 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
>-		     lower_32_bits(adev->vcn.gpu_addr + offset));
>+		     lower_32_bits(adev->vcn.inst->gpu_addr + offset));
> 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
>-		     upper_32_bits(adev->vcn.gpu_addr + offset));
>+		     upper_32_bits(adev->vcn.inst->gpu_addr + offset));
> 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
> 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
> 
> 	/* cache window 2: context */
> 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
>-		     lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
>+		     lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
> 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
>-		     upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
>+		     upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
> 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
> 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
> 
>@@ -374,9 +376,9 @@
> 		offset = 0;
> 	} else {
> 		WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
>-			lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
>+			lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
> 		WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
>-			upper_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);
>+			upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
> 		offset = size;
> 		WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
> 			     AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
>@@ -386,9 +388,9 @@
> 
> 	/* cache window 1: stack */
> 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
>-		     lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
>+		     lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
> 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
>-		     upper_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);
>+		     upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
> 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
> 			     0xFFFFFFFF, 0);
> 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
>@@ -396,10 +398,10 @@
> 
> 	/* cache window 2: context */
> 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
>-		     lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
>+		     lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
> 			     0xFFFFFFFF, 0);
> 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
>-		     upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
>+		     upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
> 			     0xFFFFFFFF, 0);
> 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
> 	WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
>@@ -779,7 +781,7 @@
>  */
> static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
> {
>-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
>+	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
> 	uint32_t rb_bufsz, tmp;
> 	uint32_t lmi_swap_cntl;
> 	int i, j, r;
>@@ -932,21 +934,21 @@
> 	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
> 			~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
> 
>-	ring = &adev->vcn.ring_enc[0];
>+	ring = &adev->vcn.inst->ring_enc[0];
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
> 
>-	ring = &adev->vcn.ring_enc[1];
>+	ring = &adev->vcn.inst->ring_enc[1];
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
> 
>-	ring = &adev->vcn.ring_jpeg;
>+	ring = &adev->vcn.inst->ring_jpeg;
> 	WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
> 	WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
> 			UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
>@@ -968,7 +970,7 @@
> 
> static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
> {
>-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
>+	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
> 	uint32_t rb_bufsz, tmp;
> 	uint32_t lmi_swap_cntl;
> 
>@@ -1106,7 +1108,7 @@
> 			~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
> 
> 	/* initialize JPEG wptr */
>-	ring = &adev->vcn.ring_jpeg;
>+	ring = &adev->vcn.inst->ring_jpeg;
> 	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
> 
> 	/* copy patch commands to the jpeg ring */
>@@ -1255,21 +1257,21 @@
> 						   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
> 
> 				/* Restore */
>-				ring = &adev->vcn.ring_enc[0];
>+				ring = &adev->vcn.inst->ring_enc[0];
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
> 
>-				ring = &adev->vcn.ring_enc[1];
>+				ring = &adev->vcn.inst->ring_enc[1];
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
> 
>-				ring = &adev->vcn.ring_dec;
>+				ring = &adev->vcn.inst->ring_dec;
> 				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
> 						   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
> 				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
>@@ -1315,7 +1317,7 @@
> 							UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code);
> 
> 				/* Restore */
>-				ring = &adev->vcn.ring_jpeg;
>+				ring = &adev->vcn.inst->ring_jpeg;
> 				WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
> 				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
> 							UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
>@@ -1329,7 +1331,7 @@
> 				WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
> 							UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
> 
>-				ring = &adev->vcn.ring_dec;
>+				ring = &adev->vcn.inst->ring_dec;
> 				WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
> 						   RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
> 				SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
>@@ -1596,7 +1598,7 @@
> {
> 	struct amdgpu_device *adev = ring->adev;
> 
>-	if (ring == &adev->vcn.ring_enc[0])
>+	if (ring == &adev->vcn.inst->ring_enc[0])
> 		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
> 	else
> 		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
>@@ -1613,7 +1615,7 @@
> {
> 	struct amdgpu_device *adev = ring->adev;
> 
>-	if (ring == &adev->vcn.ring_enc[0])
>+	if (ring == &adev->vcn.inst->ring_enc[0])
> 		return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
> 	else
> 		return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
>@@ -1630,7 +1632,7 @@
> {
> 	struct amdgpu_device *adev = ring->adev;
> 
>-	if (ring == &adev->vcn.ring_enc[0])
>+	if (ring == &adev->vcn.inst->ring_enc[0])
> 		WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
> 			lower_32_bits(ring->wptr));
> 	else
>@@ -2114,16 +2116,16 @@
> 
> 	switch (entry->src_id) {
> 	case 124:
>-		amdgpu_fence_process(&adev->vcn.ring_dec);
>+		amdgpu_fence_process(&adev->vcn.inst->ring_dec);
> 		break;
> 	case 119:
>-		amdgpu_fence_process(&adev->vcn.ring_enc[0]);
>+		amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
> 		break;
> 	case 120:
>-		amdgpu_fence_process(&adev->vcn.ring_enc[1]);
>+		amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
> 		break;
> 	case 126:
>-		amdgpu_fence_process(&adev->vcn.ring_jpeg);
>+		amdgpu_fence_process(&adev->vcn.inst->ring_jpeg);
> 		break;
> 	default:
> 		DRM_ERROR("Unhandled interrupt: %d %d\n",
>@@ -2198,7 +2200,7 @@
> 	.align_mask = 0xf,
> 	.support_64bit_ptrs = false,
> 	.no_user_fence = true,
>-	.vmhub = AMDGPU_MMHUB,
>+	.vmhub = AMDGPU_MMHUB_0,
> 	.get_rptr = vcn_v1_0_dec_ring_get_rptr,
> 	.get_wptr = vcn_v1_0_dec_ring_get_wptr,
> 	.set_wptr = vcn_v1_0_dec_ring_set_wptr,
>@@ -2232,7 +2234,7 @@
> 	.nop = VCN_ENC_CMD_NO_OP,
> 	.support_64bit_ptrs = false,
> 	.no_user_fence = true,
>-	.vmhub = AMDGPU_MMHUB,
>+	.vmhub = AMDGPU_MMHUB_0,
> 	.get_rptr = vcn_v1_0_enc_ring_get_rptr,
> 	.get_wptr = vcn_v1_0_enc_ring_get_wptr,
> 	.set_wptr = vcn_v1_0_enc_ring_set_wptr,
>@@ -2264,7 +2266,7 @@
> 	.nop = PACKET0(0x81ff, 0),
> 	.support_64bit_ptrs = false,
> 	.no_user_fence = true,
>-	.vmhub = AMDGPU_MMHUB,
>+	.vmhub = AMDGPU_MMHUB_0,
> 	.extra_dw = 64,
> 	.get_rptr = vcn_v1_0_jpeg_ring_get_rptr,
> 	.get_wptr = vcn_v1_0_jpeg_ring_get_wptr,
>@@ -2295,7 +2297,7 @@
> 
> static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
> {
>-	adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
>+	adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
> 	DRM_INFO("VCN decode is enabled in VM mode\n");
> }
> 
>@@ -2304,14 +2306,14 @@
> 	int i;
> 
> 	for (i = 0; i < adev->vcn.num_enc_rings; ++i)
>-		adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
>+		adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
> 
> 	DRM_INFO("VCN encode is enabled in VM mode\n");
> }
> 
> static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
> {
>-	adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
>+	adev->vcn.inst->ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
> 	DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
> }
> 
>@@ -2322,8 +2324,8 @@
> 
> static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
> {
>-	adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
>-	adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
>+	adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
>+	adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
> }
> 
> const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c	2019-08-31 15:08:26.826774600 -0500
>@@ -22,7 +22,7 @@
>  */
> 
> #include <linux/firmware.h>
>-#include <drm/drmP.h>
>+
> #include "amdgpu.h"
> #include "amdgpu_vcn.h"
> #include "soc15.h"
>@@ -92,6 +92,7 @@
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 
>+	adev->vcn.num_vcn_inst = 1;
> 	adev->vcn.num_enc_rings = 2;
> 
> 	vcn_v2_0_set_dec_ring_funcs(adev);
>@@ -118,7 +119,7 @@
> 	/* VCN DEC TRAP */
> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
> 			      VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
>-			      &adev->vcn.irq);
>+			      &adev->vcn.inst->irq);
> 	if (r)
> 		return r;
> 
>@@ -126,15 +127,14 @@
> 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
> 		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
> 				      i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
>-				      &adev->vcn.irq);
>+				      &adev->vcn.inst->irq);
> 		if (r)
> 			return r;
> 	}
> 
> 	/* VCN JPEG TRAP */
> 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
>-			      VCN_2_0__SRCID__JPEG_DECODE,
>-			      &adev->vcn.irq);
>+			      VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst->irq);
> 	if (r)
> 		return r;
> 
>@@ -156,49 +156,56 @@
> 	if (r)
> 		return r;
> 
>-	ring = &adev->vcn.ring_dec;
>+	ring = &adev->vcn.inst->ring_dec;
> 
> 	ring->use_doorbell = true;
> 	ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
> 
> 	sprintf(ring->name, "vcn_dec");
>-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
>+	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
> 	if (r)
> 		return r;
> 
>+	adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
>+	adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
>+	adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
>+	adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
>+	adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
>+	adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
>+
> 	adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
>-	adev->vcn.external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
>+	adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
> 	adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
>-	adev->vcn.external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
>+	adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
> 	adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
>-	adev->vcn.external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
>+	adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
> 	adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
>-	adev->vcn.external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
>+	adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
> 	adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
>-	adev->vcn.external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
>+	adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
> 
> 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>-		ring = &adev->vcn.ring_enc[i];
>+		ring = &adev->vcn.inst->ring_enc[i];
> 		ring->use_doorbell = true;
> 		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
> 		sprintf(ring->name, "vcn_enc%d", i);
>-		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
>+		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
> 		if (r)
> 			return r;
> 	}
> 
>-	ring = &adev->vcn.ring_jpeg;
>+	ring = &adev->vcn.inst->ring_jpeg;
> 	ring->use_doorbell = true;
> 	ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
> 	sprintf(ring->name, "vcn_jpeg");
>-	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
>+	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0);
> 	if (r)
> 		return r;
> 
> 	adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
> 
> 	adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
>-	adev->vcn.external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
>+	adev->vcn.inst->external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_PITCH);
> 
> 	return 0;
> }
>@@ -234,11 +241,11 @@
> static int vcn_v2_0_hw_init(void *handle)
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
>+	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
> 	int i, r;
> 
> 	adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
>-		ring->doorbell_index);
>+					     ring->doorbell_index, 0);
> 
> 	ring->sched.ready = true;
> 	r = amdgpu_ring_test_ring(ring);
>@@ -248,7 +255,7 @@
> 	}
> 
> 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>-		ring = &adev->vcn.ring_enc[i];
>+		ring = &adev->vcn.inst->ring_enc[i];
> 		ring->sched.ready = true;
> 		r = amdgpu_ring_test_ring(ring);
> 		if (r) {
>@@ -257,7 +264,7 @@
> 		}
> 	}
> 
>-	ring = &adev->vcn.ring_jpeg;
>+	ring = &adev->vcn.inst->ring_jpeg;
> 	ring->sched.ready = true;
> 	r = amdgpu_ring_test_ring(ring);
> 	if (r) {
>@@ -283,7 +290,7 @@
> static int vcn_v2_0_hw_fini(void *handle)
> {
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
>+	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
> 	int i;
> 
> 	if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>@@ -294,11 +301,11 @@
> 	ring->sched.ready = false;
> 
> 	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>-		ring = &adev->vcn.ring_enc[i];
>+		ring = &adev->vcn.inst->ring_enc[i];
> 		ring->sched.ready = false;
> 	}
> 
>-	ring = &adev->vcn.ring_jpeg;
>+	ring = &adev->vcn.inst->ring_jpeg;
> 	ring->sched.ready = false;
> 
> 	return 0;
>@@ -368,9 +375,9 @@
> 		offset = 0;
> 	} else {
> 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
>-			lower_32_bits(adev->vcn.gpu_addr));
>+			lower_32_bits(adev->vcn.inst->gpu_addr));
> 		WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
>-			upper_32_bits(adev->vcn.gpu_addr));
>+			upper_32_bits(adev->vcn.inst->gpu_addr));
> 		offset = size;
> 		WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
> 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
>@@ -380,17 +387,17 @@
> 
> 	/* cache window 1: stack */
> 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
>-		lower_32_bits(adev->vcn.gpu_addr + offset));
>+		lower_32_bits(adev->vcn.inst->gpu_addr + offset));
> 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
>-		upper_32_bits(adev->vcn.gpu_addr + offset));
>+		upper_32_bits(adev->vcn.inst->gpu_addr + offset));
> 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
> 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
> 
> 	/* cache window 2: context */
> 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
>-		lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
>+		lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
> 	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
>-		upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
>+		upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
> 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
> 	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
> 
>@@ -426,10 +433,10 @@
> 	} else {
> 		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
> 			UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>-			lower_32_bits(adev->vcn.gpu_addr), 0, indirect);
>+			lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
> 		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
> 			UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>-			upper_32_bits(adev->vcn.gpu_addr), 0, indirect);
>+			upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
> 		offset = size;
> 		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
> 			UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
>@@ -447,10 +454,10 @@
> 	if (!indirect) {
> 		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
> 			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>-			lower_32_bits(adev->vcn.gpu_addr + offset), 0, indirect);
>+			lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
> 		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
> 			UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>-			upper_32_bits(adev->vcn.gpu_addr + offset), 0, indirect);
>+			upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
> 		WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
> 			UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> 	} else {
>@@ -467,10 +474,10 @@
> 	/* cache window 2: context */
> 	WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
> 		UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>-		lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
>+		lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
> 	WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
> 		UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>-		upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
>+		upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
> 	WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
> 		UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
> 	WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
>@@ -658,7 +665,7 @@
>  */
> static int jpeg_v2_0_start(struct amdgpu_device *adev)
> {
>-	struct amdgpu_ring *ring = &adev->vcn.ring_jpeg;
>+	struct amdgpu_ring *ring = &adev->vcn.inst->ring_jpeg;
> 	uint32_t tmp;
> 	int r = 0;
> 
>@@ -920,7 +927,7 @@
> 
> static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
> {
>-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
>+	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
> 	uint32_t rb_bufsz, tmp;
> 
> 	vcn_v2_0_enable_static_power_gating(adev);
>@@ -1046,7 +1053,7 @@
> 
> static int vcn_v2_0_start(struct amdgpu_device *adev)
> {
>-	struct amdgpu_ring *ring = &adev->vcn.ring_dec;
>+	struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
> 	uint32_t rb_bufsz, tmp;
> 	uint32_t lmi_swap_cntl;
> 	int i, j, r;
>@@ -1197,14 +1204,14 @@
> 	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
> 			lower_32_bits(ring->wptr));
> 
>-	ring = &adev->vcn.ring_enc[0];
>+	ring = &adev->vcn.inst->ring_enc[0];
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
> 
>-	ring = &adev->vcn.ring_enc[1];
>+	ring = &adev->vcn.inst->ring_enc[1];
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
> 	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
>@@ -1351,14 +1358,14 @@
> 					   UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
> 
> 				/* Restore */
>-				ring = &adev->vcn.ring_enc[0];
>+				ring = &adev->vcn.inst->ring_enc[0];
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
> 
>-				ring = &adev->vcn.ring_enc[1];
>+				ring = &adev->vcn.inst->ring_enc[1];
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
> 				WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
>@@ -1480,11 +1487,13 @@
>  *
>  * Write a start command to the ring.
>  */
>-static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
>+void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
> {
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
> 	amdgpu_ring_write(ring, 0);
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
> }
> 
>@@ -1495,9 +1504,11 @@
>  *
>  * Write a end command to the ring.
>  */
>-static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
>+void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
> {
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
> }
> 
>@@ -1508,14 +1519,15 @@
>  *
>  * Write a nop command to the ring.
>  */
>-static void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
>+void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
> {
>+	struct amdgpu_device *adev = ring->adev;
> 	int i;
> 
> 	WARN_ON(ring->wptr % 2 || count % 2);
> 
> 	for (i = 0; i < count / 2; i++) {
>-		amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP_INTERNAL_OFFSET, 0));
>+		amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
> 		amdgpu_ring_write(ring, 0);
> 	}
> }
>@@ -1528,30 +1540,31 @@
>  *
>  * Write a fence and a trap command to the ring.
>  */
>-static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
>-				     unsigned flags)
>+void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
>+				unsigned flags)
> {
>-	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
>+	struct amdgpu_device *adev = ring->adev;
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID_INTERNAL_OFFSET, 0));
>+	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
> 	amdgpu_ring_write(ring, seq);
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
> 	amdgpu_ring_write(ring, addr & 0xffffffff);
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
> 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
> 	amdgpu_ring_write(ring, 0);
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
> 	amdgpu_ring_write(ring, 0);
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
> 
> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
> }
>@@ -1564,44 +1577,46 @@
>  *
>  * Write ring commands to execute the indirect buffer
>  */
>-static void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
>-				      struct amdgpu_job *job,
>-				      struct amdgpu_ib *ib,
>-				      uint32_t flags)
>+void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
>+			       struct amdgpu_job *job,
>+			       struct amdgpu_ib *ib,
>+			       uint32_t flags)
> {
>+	struct amdgpu_device *adev = ring->adev;
> 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));
> 	amdgpu_ring_write(ring, vmid);
> 
>-	amdgpu_ring_write(ring,	PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring,	PACKET0(adev->vcn.internal.ib_bar_low, 0));
> 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
>-	amdgpu_ring_write(ring,	PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring,	PACKET0(adev->vcn.internal.ib_bar_high, 0));
> 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
>-	amdgpu_ring_write(ring,	PACKET0(mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring,	PACKET0(adev->vcn.internal.ib_size, 0));
> 	amdgpu_ring_write(ring, ib->length_dw);
> }
> 
>-static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
>-					    uint32_t reg, uint32_t val,
>-					    uint32_t mask)
>+void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
>+				uint32_t val, uint32_t mask)
> {
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
> 	amdgpu_ring_write(ring, reg << 2);
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
> 	amdgpu_ring_write(ring, val);
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));
> 	amdgpu_ring_write(ring, mask);
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
> 
> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
> }
> 
>-static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
>-					    unsigned vmid, uint64_t pd_addr)
>+void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
>+				unsigned vmid, uint64_t pd_addr)
> {
> 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
> 	uint32_t data0, data1, mask;
>@@ -1615,16 +1630,18 @@
> 	vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
> }
> 
>-static void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
>-					uint32_t reg, uint32_t val)
>+void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
>+				uint32_t reg, uint32_t val)
> {
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0));
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
> 	amdgpu_ring_write(ring, reg << 2);
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
> 	amdgpu_ring_write(ring, val);
> 
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
> 
> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
> }
>@@ -1640,7 +1657,7 @@
> {
> 	struct amdgpu_device *adev = ring->adev;
> 
>-	if (ring == &adev->vcn.ring_enc[0])
>+	if (ring == &adev->vcn.inst->ring_enc[0])
> 		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
> 	else
> 		return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
>@@ -1657,7 +1674,7 @@
> {
> 	struct amdgpu_device *adev = ring->adev;
> 
>-	if (ring == &adev->vcn.ring_enc[0]) {
>+	if (ring == &adev->vcn.inst->ring_enc[0]) {
> 		if (ring->use_doorbell)
> 			return adev->wb.wb[ring->wptr_offs];
> 		else
>@@ -1681,7 +1698,7 @@
> {
> 	struct amdgpu_device *adev = ring->adev;
> 
>-	if (ring == &adev->vcn.ring_enc[0]) {
>+	if (ring == &adev->vcn.inst->ring_enc[0]) {
> 		if (ring->use_doorbell) {
> 			adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
> 			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
>@@ -1706,8 +1723,8 @@
>  *
>  * Write enc a fence and a trap command to the ring.
>  */
>-static void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
>-			u64 seq, unsigned flags)
>+void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
>+				u64 seq, unsigned flags)
> {
> 	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
> 
>@@ -1718,7 +1735,7 @@
> 	amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
> }
> 
>-static void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
>+void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
> {
> 	amdgpu_ring_write(ring, VCN_ENC_CMD_END);
> }
>@@ -1731,10 +1748,10 @@
>  *
>  * Write enc ring commands to execute the indirect buffer
>  */
>-static void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
>-				      struct amdgpu_job *job,
>-				      struct amdgpu_ib *ib,
>-				      uint32_t flags)
>+void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
>+			       struct amdgpu_job *job,
>+			       struct amdgpu_ib *ib,
>+			       uint32_t flags)
> {
> 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
> 
>@@ -1745,9 +1762,8 @@
> 	amdgpu_ring_write(ring, ib->length_dw);
> }
> 
>-static void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
>-					    uint32_t reg, uint32_t val,
>-					    uint32_t mask)
>+void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
>+				uint32_t val, uint32_t mask)
> {
> 	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
> 	amdgpu_ring_write(ring, reg << 2);
>@@ -1755,8 +1771,8 @@
> 	amdgpu_ring_write(ring, val);
> }
> 
>-static void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
>-					    unsigned int vmid, uint64_t pd_addr)
>+void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
>+				unsigned int vmid, uint64_t pd_addr)
> {
> 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
> 
>@@ -1767,8 +1783,7 @@
> 					lower_32_bits(pd_addr), 0xffffffff);
> }
> 
>-static void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
>-					uint32_t reg, uint32_t val)
>+void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
> {
> 	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
> 	amdgpu_ring_write(ring,	reg << 2);
>@@ -1832,7 +1847,7 @@
>  *
>  * Write a start command to the ring.
>  */
>-static void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
>+void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
> {
> 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
> 		0, 0, PACKETJ_TYPE0));
>@@ -1850,7 +1865,7 @@
>  *
>  * Write a end command to the ring.
>  */
>-static void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
>+void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
> {
> 	amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
> 		0, 0, PACKETJ_TYPE0));
>@@ -1869,8 +1884,8 @@
>  *
>  * Write a fence and a trap command to the ring.
>  */
>-static void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
>-				     unsigned flags)
>+void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
>+				unsigned flags)
> {
> 	WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
> 
>@@ -1918,10 +1933,10 @@
>  *
>  * Write ring commands to execute the indirect buffer.
>  */
>-static void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
>-				       struct amdgpu_job *job,
>-				       struct amdgpu_ib *ib,
>-				       uint32_t flags)
>+void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
>+				struct amdgpu_job *job,
>+				struct amdgpu_ib *ib,
>+				uint32_t flags)
> {
> 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
> 
>@@ -1969,9 +1984,8 @@
> 	amdgpu_ring_write(ring, 0x2);
> }
> 
>-static void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
>-					    uint32_t reg, uint32_t val,
>-					    uint32_t mask)
>+void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
>+				uint32_t val, uint32_t mask)
> {
> 	uint32_t reg_offset = (reg << 2);
> 
>@@ -1997,8 +2011,8 @@
> 	amdgpu_ring_write(ring, mask);
> }
> 
>-static void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
>-		unsigned vmid, uint64_t pd_addr)
>+void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
>+				unsigned vmid, uint64_t pd_addr)
> {
> 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
> 	uint32_t data0, data1, mask;
>@@ -2012,8 +2026,7 @@
> 	vcn_v2_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
> }
> 
>-static void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
>-					uint32_t reg, uint32_t val)
>+void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
> {
> 	uint32_t reg_offset = (reg << 2);
> 
>@@ -2031,7 +2044,7 @@
> 	amdgpu_ring_write(ring, val);
> }
> 
>-static void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
>+void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
> {
> 	int i;
> 
>@@ -2059,16 +2072,16 @@
> 
> 	switch (entry->src_id) {
> 	case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
>-		amdgpu_fence_process(&adev->vcn.ring_dec);
>+		amdgpu_fence_process(&adev->vcn.inst->ring_dec);
> 		break;
> 	case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
>-		amdgpu_fence_process(&adev->vcn.ring_enc[0]);
>+		amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
> 		break;
> 	case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
>-		amdgpu_fence_process(&adev->vcn.ring_enc[1]);
>+		amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
> 		break;
> 	case VCN_2_0__SRCID__JPEG_DECODE:
>-		amdgpu_fence_process(&adev->vcn.ring_jpeg);
>+		amdgpu_fence_process(&adev->vcn.inst->ring_jpeg);
> 		break;
> 	default:
> 		DRM_ERROR("Unhandled interrupt: %d %d\n",
>@@ -2086,20 +2099,20 @@
> 	unsigned i;
> 	int r;
> 
>-	WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD);
>+	WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
> 	r = amdgpu_ring_alloc(ring, 4);
> 	if (r)
> 		return r;
>-	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0));
>+	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
> 	amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
> 	amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
> 	amdgpu_ring_write(ring, 0xDEADBEEF);
> 	amdgpu_ring_commit(ring);
> 	for (i = 0; i < adev->usec_timeout; i++) {
>-		tmp = RREG32(adev->vcn.external.scratch9);
>+		tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
> 		if (tmp == 0xDEADBEEF)
> 			break;
>-		DRM_UDELAY(1);
>+		udelay(1);
> 	}
> 
> 	if (i >= adev->usec_timeout)
>@@ -2158,7 +2171,7 @@
> static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
> 	.type = AMDGPU_RING_TYPE_VCN_DEC,
> 	.align_mask = 0xf,
>-	.vmhub = AMDGPU_MMHUB,
>+	.vmhub = AMDGPU_MMHUB_0,
> 	.get_rptr = vcn_v2_0_dec_ring_get_rptr,
> 	.get_wptr = vcn_v2_0_dec_ring_get_wptr,
> 	.set_wptr = vcn_v2_0_dec_ring_set_wptr,
>@@ -2189,7 +2202,7 @@
> 	.type = AMDGPU_RING_TYPE_VCN_ENC,
> 	.align_mask = 0x3f,
> 	.nop = VCN_ENC_CMD_NO_OP,
>-	.vmhub = AMDGPU_MMHUB,
>+	.vmhub = AMDGPU_MMHUB_0,
> 	.get_rptr = vcn_v2_0_enc_ring_get_rptr,
> 	.get_wptr = vcn_v2_0_enc_ring_get_wptr,
> 	.set_wptr = vcn_v2_0_enc_ring_set_wptr,
>@@ -2218,7 +2231,7 @@
> static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_ring_vm_funcs = {
> 	.type = AMDGPU_RING_TYPE_VCN_JPEG,
> 	.align_mask = 0xf,
>-	.vmhub = AMDGPU_MMHUB,
>+	.vmhub = AMDGPU_MMHUB_0,
> 	.get_rptr = vcn_v2_0_jpeg_ring_get_rptr,
> 	.get_wptr = vcn_v2_0_jpeg_ring_get_wptr,
> 	.set_wptr = vcn_v2_0_jpeg_ring_set_wptr,
>@@ -2247,7 +2260,7 @@
> 
> static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
> {
>-	adev->vcn.ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
>+	adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
> 	DRM_INFO("VCN decode is enabled in VM mode\n");
> }
> 
>@@ -2256,14 +2269,14 @@
> 	int i;
> 
> 	for (i = 0; i < adev->vcn.num_enc_rings; ++i)
>-		adev->vcn.ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
>+		adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
> 
> 	DRM_INFO("VCN encode is enabled in VM mode\n");
> }
> 
> static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
> {
>-	adev->vcn.ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs;
>+	adev->vcn.inst->ring_jpeg.funcs = &vcn_v2_0_jpeg_ring_vm_funcs;
> 	DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
> }
> 
>@@ -2274,8 +2287,8 @@
> 
> static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
> {
>-	adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
>-	adev->vcn.irq.funcs = &vcn_v2_0_irq_funcs;
>+	adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
>+	adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
> }
> 
> const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h	2019-08-31 15:01:11.851736168 -0500
>@@ -24,6 +24,44 @@
> #ifndef __VCN_V2_0_H__
> #define __VCN_V2_0_H__
> 
>+extern void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
>+extern void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
>+extern void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
>+extern void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
>+				unsigned flags);
>+extern void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
>+				struct amdgpu_ib *ib, uint32_t flags);
>+extern void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
>+				uint32_t val, uint32_t mask);
>+extern void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
>+				unsigned vmid, uint64_t pd_addr);
>+extern void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
>+				uint32_t reg, uint32_t val);
>+
>+extern void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring);
>+extern void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
>+				u64 seq, unsigned flags);
>+extern void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
>+				struct amdgpu_ib *ib, uint32_t flags);
>+extern void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
>+				uint32_t val, uint32_t mask);
>+extern void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
>+				unsigned int vmid, uint64_t pd_addr);
>+extern void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
>+
>+extern void vcn_v2_0_jpeg_ring_insert_start(struct amdgpu_ring *ring);
>+extern void vcn_v2_0_jpeg_ring_insert_end(struct amdgpu_ring *ring);
>+extern void vcn_v2_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
>+				unsigned flags);
>+extern void vcn_v2_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
>+				struct amdgpu_ib *ib, uint32_t flags);
>+extern void vcn_v2_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
>+				uint32_t val, uint32_t mask);
>+extern void vcn_v2_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
>+				unsigned vmid, uint64_t pd_addr);
>+extern void vcn_v2_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
>+extern void vcn_v2_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count);
>+
> extern const struct amdgpu_ip_block_version vcn_v2_0_ip_block;
> 
> #endif /* __VCN_V2_0_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c	2019-08-31 15:01:11.852736168 -0500
>@@ -0,0 +1,1414 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include <linux/firmware.h>
>+
>+#include "amdgpu.h"
>+#include "amdgpu_vcn.h"
>+#include "soc15.h"
>+#include "soc15d.h"
>+#include "vcn_v2_0.h"
>+
>+#include "vcn/vcn_2_5_offset.h"
>+#include "vcn/vcn_2_5_sh_mask.h"
>+#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
>+
>+#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET			0x27
>+#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET			0x0f
>+#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET			0x10
>+#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET			0x11
>+#define mmUVD_NO_OP_INTERNAL_OFFSET				0x29
>+#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET			0x66
>+#define mmUVD_SCRATCH9_INTERNAL_OFFSET				0xc01d
>+
>+#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET			0x431
>+#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET		0x3b4
>+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 	0x3b5
>+#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET			0x25c
>+
>+#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET			0x401f
>+
>+#define VCN25_MAX_HW_INSTANCES_ARCTURUS				2
>+
>+static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
>+static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
>+static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev);
>+static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
>+static int vcn_v2_5_set_powergating_state(void *handle,
>+				enum amd_powergating_state state);
>+
>+static int amdgpu_ih_clientid_vcns[] = {
>+	SOC15_IH_CLIENTID_VCN,
>+	SOC15_IH_CLIENTID_VCN1
>+};
>+
>+/**
>+ * vcn_v2_5_early_init - set function pointers
>+ *
>+ * @handle: amdgpu_device pointer
>+ *
>+ * Set ring and irq function pointers
>+ */
>+static int vcn_v2_5_early_init(void *handle)
>+{
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+	if (adev->asic_type == CHIP_ARCTURUS) {
>+		u32 harvest;
>+		int i;
>+
>+		adev->vcn.num_vcn_inst = VCN25_MAX_HW_INSTANCES_ARCTURUS;
>+		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>+			harvest = RREG32_SOC15(UVD, i, mmCC_UVD_HARVESTING);
>+			if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
>+				adev->vcn.harvest_config |= 1 << i;
>+		}
>+
>+		if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
>+						 AMDGPU_VCN_HARVEST_VCN1))
>+			/* both instances are harvested, disable the block */
>+			return -ENOENT;
>+	} else
>+		adev->vcn.num_vcn_inst = 1;
>+
>+	adev->vcn.num_enc_rings = 2;
>+
>+	vcn_v2_5_set_dec_ring_funcs(adev);
>+	vcn_v2_5_set_enc_ring_funcs(adev);
>+	vcn_v2_5_set_jpeg_ring_funcs(adev);
>+	vcn_v2_5_set_irq_funcs(adev);
>+
>+	return 0;
>+}
>+
>+/**
>+ * vcn_v2_5_sw_init - sw init for VCN block
>+ *
>+ * @handle: amdgpu_device pointer
>+ *
>+ * Load firmware and sw initialization
>+ */
>+static int vcn_v2_5_sw_init(void *handle)
>+{
>+	struct amdgpu_ring *ring;
>+	int i, j, r;
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+
>+	for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
>+		if (adev->vcn.harvest_config & (1 << j))
>+			continue;
>+		/* VCN DEC TRAP */
>+		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
>+				VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);
>+		if (r)
>+			return r;
>+
>+		/* VCN ENC TRAP */
>+		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>+			r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
>+				i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);
>+			if (r)
>+				return r;
>+		}
>+
>+		/* VCN JPEG TRAP */
>+		r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
>+				VCN_2_0__SRCID__JPEG_DECODE, &adev->vcn.inst[j].irq);
>+		if (r)
>+			return r;
>+	}
>+
>+	r = amdgpu_vcn_sw_init(adev);
>+	if (r)
>+		return r;
>+
>+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>+		const struct common_firmware_header *hdr;
>+		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
>+		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
>+		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
>+		adev->firmware.fw_size +=
>+			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
>+
>+		if (adev->vcn.num_vcn_inst == VCN25_MAX_HW_INSTANCES_ARCTURUS) {
>+			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
>+			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
>+			adev->firmware.fw_size +=
>+				ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
>+		}
>+		DRM_INFO("PSP loading VCN firmware\n");
>+	}
>+
>+	r = amdgpu_vcn_resume(adev);
>+	if (r)
>+		return r;
>+
>+	for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
>+		if (adev->vcn.harvest_config & (1 << j))
>+			continue;
>+		adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
>+		adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
>+		adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
>+		adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
>+		adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
>+		adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
>+
>+		adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
>+		adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(UVD, j, mmUVD_SCRATCH9);
>+		adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
>+		adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA0);
>+		adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
>+		adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA1);
>+		adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
>+		adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_CMD);
>+		adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
>+		adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(UVD, j, mmUVD_NO_OP);
>+
>+		adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
>+		adev->vcn.inst[j].external.jpeg_pitch = SOC15_REG_OFFSET(UVD, j, mmUVD_JPEG_PITCH);
>+
>+		ring = &adev->vcn.inst[j].ring_dec;
>+		ring->use_doorbell = true;
>+		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8*j;
>+		sprintf(ring->name, "vcn_dec_%d", j);
>+		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
>+		if (r)
>+			return r;
>+
>+		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>+			ring = &adev->vcn.inst[j].ring_enc[i];
>+			ring->use_doorbell = true;
>+			ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i + 8*j;
>+			sprintf(ring->name, "vcn_enc_%d.%d", j, i);
>+			r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
>+			if (r)
>+				return r;
>+		}
>+
>+		ring = &adev->vcn.inst[j].ring_jpeg;
>+		ring->use_doorbell = true;
>+		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8*j;
>+		sprintf(ring->name, "vcn_jpeg_%d", j);
>+		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 0);
>+		if (r)
>+			return r;
>+	}
>+
>+	return 0;
>+}
>+
>+/**
>+ * vcn_v2_5_sw_fini - sw fini for VCN block
>+ *
>+ * @handle: amdgpu_device pointer
>+ *
>+ * VCN suspend and free up sw allocation
>+ */
>+static int vcn_v2_5_sw_fini(void *handle)
>+{
>+	int r;
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+
>+	r = amdgpu_vcn_suspend(adev);
>+	if (r)
>+		return r;
>+
>+	r = amdgpu_vcn_sw_fini(adev);
>+
>+	return r;
>+}
>+
>+/**
>+ * vcn_v2_5_hw_init - start and test VCN block
>+ *
>+ * @handle: amdgpu_device pointer
>+ *
>+ * Initialize the hardware, boot up the VCPU and do some testing
>+ */
>+static int vcn_v2_5_hw_init(void *handle)
>+{
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+	struct amdgpu_ring *ring;
>+	int i, j, r;
>+
>+	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
>+		if (adev->vcn.harvest_config & (1 << j))
>+			continue;
>+		ring = &adev->vcn.inst[j].ring_dec;
>+
>+		adev->nbio_funcs->vcn_doorbell_range(adev, ring->use_doorbell,
>+						     ring->doorbell_index, j);
>+
>+		r = amdgpu_ring_test_ring(ring);
>+		if (r) {
>+			ring->sched.ready = false;
>+			goto done;
>+		}
>+
>+		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>+			ring = &adev->vcn.inst[j].ring_enc[i];
>+			ring->sched.ready = false;
>+			continue;
>+			r = amdgpu_ring_test_ring(ring);
>+			if (r) {
>+				ring->sched.ready = false;
>+				goto done;
>+			}
>+		}
>+
>+		ring = &adev->vcn.inst[j].ring_jpeg;
>+		r = amdgpu_ring_test_ring(ring);
>+		if (r) {
>+			ring->sched.ready = false;
>+			goto done;
>+		}
>+	}
>+done:
>+	if (!r)
>+		DRM_INFO("VCN decode and encode initialized successfully.\n");
>+
>+	return r;
>+}
>+
>+/**
>+ * vcn_v2_5_hw_fini - stop the hardware block
>+ *
>+ * @handle: amdgpu_device pointer
>+ *
>+ * Stop the VCN block, mark ring as not ready any more
>+ */
>+static int vcn_v2_5_hw_fini(void *handle)
>+{
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+	struct amdgpu_ring *ring;
>+	int i;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		ring = &adev->vcn.inst[i].ring_dec;
>+
>+		if (RREG32_SOC15(VCN, i, mmUVD_STATUS))
>+			vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
>+
>+		ring->sched.ready = false;
>+
>+		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>+			ring = &adev->vcn.inst[i].ring_enc[i];
>+			ring->sched.ready = false;
>+		}
>+
>+		ring = &adev->vcn.inst[i].ring_jpeg;
>+		ring->sched.ready = false;
>+	}
>+
>+	return 0;
>+}
>+
>+/**
>+ * vcn_v2_5_suspend - suspend VCN block
>+ *
>+ * @handle: amdgpu_device pointer
>+ *
>+ * HW fini and suspend VCN block
>+ */
>+static int vcn_v2_5_suspend(void *handle)
>+{
>+	int r;
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+
>+	r = vcn_v2_5_hw_fini(adev);
>+	if (r)
>+		return r;
>+
>+	r = amdgpu_vcn_suspend(adev);
>+
>+	return r;
>+}
>+
>+/**
>+ * vcn_v2_5_resume - resume VCN block
>+ *
>+ * @handle: amdgpu_device pointer
>+ *
>+ * Resume firmware and hw init VCN block
>+ */
>+static int vcn_v2_5_resume(void *handle)
>+{
>+	int r;
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+
>+	r = amdgpu_vcn_resume(adev);
>+	if (r)
>+		return r;
>+
>+	r = vcn_v2_5_hw_init(adev);
>+
>+	return r;
>+}
>+
>+/**
>+ * vcn_v2_5_mc_resume - memory controller programming
>+ *
>+ * @adev: amdgpu_device pointer
>+ *
>+ * Let the VCN memory controller know it's offsets
>+ */
>+static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
>+{
>+	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
>+	uint32_t offset;
>+	int i;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		/* cache window 0: fw */
>+		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>+			WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
>+				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
>+			WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
>+				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
>+			WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
>+			offset = 0;
>+		} else {
>+			WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
>+				lower_32_bits(adev->vcn.inst[i].gpu_addr));
>+			WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
>+				upper_32_bits(adev->vcn.inst[i].gpu_addr));
>+			offset = size;
>+			WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
>+				AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
>+		}
>+		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
>+
>+		/* cache window 1: stack */
>+		WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
>+			lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
>+		WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
>+			upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
>+		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, 0);
>+		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
>+
>+		/* cache window 2: context */
>+		WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
>+			lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
>+		WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
>+			upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
>+		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, 0);
>+		WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
>+	}
>+}
>+
>+/**
>+ * vcn_v2_5_disable_clock_gating - disable VCN clock gating
>+ *
>+ * @adev: amdgpu_device pointer
>+ * @sw: enable SW clock gating
>+ *
>+ * Disable clock gating for VCN block
>+ */
>+static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
>+{
>+	uint32_t data;
>+	int ret = 0;
>+	int i;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		/* UVD disable CGC */
>+		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
>+		if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
>+			data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
>+		else
>+			data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
>+		data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
>+		data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
>+		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
>+
>+		data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
>+		data &= ~(UVD_CGC_GATE__SYS_MASK
>+			| UVD_CGC_GATE__UDEC_MASK
>+			| UVD_CGC_GATE__MPEG2_MASK
>+			| UVD_CGC_GATE__REGS_MASK
>+			| UVD_CGC_GATE__RBC_MASK
>+			| UVD_CGC_GATE__LMI_MC_MASK
>+			| UVD_CGC_GATE__LMI_UMC_MASK
>+			| UVD_CGC_GATE__IDCT_MASK
>+			| UVD_CGC_GATE__MPRD_MASK
>+			| UVD_CGC_GATE__MPC_MASK
>+			| UVD_CGC_GATE__LBSI_MASK
>+			| UVD_CGC_GATE__LRBBM_MASK
>+			| UVD_CGC_GATE__UDEC_RE_MASK
>+			| UVD_CGC_GATE__UDEC_CM_MASK
>+			| UVD_CGC_GATE__UDEC_IT_MASK
>+			| UVD_CGC_GATE__UDEC_DB_MASK
>+			| UVD_CGC_GATE__UDEC_MP_MASK
>+			| UVD_CGC_GATE__WCB_MASK
>+			| UVD_CGC_GATE__VCPU_MASK
>+			| UVD_CGC_GATE__MMSCH_MASK);
>+
>+		WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
>+
>+		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0,  0xFFFFFFFF, ret);
>+
>+		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
>+		data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
>+			| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
>+			| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
>+			| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
>+			| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
>+			| UVD_CGC_CTRL__SYS_MODE_MASK
>+			| UVD_CGC_CTRL__UDEC_MODE_MASK
>+			| UVD_CGC_CTRL__MPEG2_MODE_MASK
>+			| UVD_CGC_CTRL__REGS_MODE_MASK
>+			| UVD_CGC_CTRL__RBC_MODE_MASK
>+			| UVD_CGC_CTRL__LMI_MC_MODE_MASK
>+			| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
>+			| UVD_CGC_CTRL__IDCT_MODE_MASK
>+			| UVD_CGC_CTRL__MPRD_MODE_MASK
>+			| UVD_CGC_CTRL__MPC_MODE_MASK
>+			| UVD_CGC_CTRL__LBSI_MODE_MASK
>+			| UVD_CGC_CTRL__LRBBM_MODE_MASK
>+			| UVD_CGC_CTRL__WCB_MODE_MASK
>+			| UVD_CGC_CTRL__VCPU_MODE_MASK
>+			| UVD_CGC_CTRL__MMSCH_MODE_MASK);
>+		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
>+
>+		/* turn on */
>+		data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);
>+		data |= (UVD_SUVD_CGC_GATE__SRE_MASK
>+			| UVD_SUVD_CGC_GATE__SIT_MASK
>+			| UVD_SUVD_CGC_GATE__SMP_MASK
>+			| UVD_SUVD_CGC_GATE__SCM_MASK
>+			| UVD_SUVD_CGC_GATE__SDB_MASK
>+			| UVD_SUVD_CGC_GATE__SRE_H264_MASK
>+			| UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
>+			| UVD_SUVD_CGC_GATE__SIT_H264_MASK
>+			| UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
>+			| UVD_SUVD_CGC_GATE__SCM_H264_MASK
>+			| UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
>+			| UVD_SUVD_CGC_GATE__SDB_H264_MASK
>+			| UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
>+			| UVD_SUVD_CGC_GATE__SCLR_MASK
>+			| UVD_SUVD_CGC_GATE__UVD_SC_MASK
>+			| UVD_SUVD_CGC_GATE__ENT_MASK
>+			| UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
>+			| UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
>+			| UVD_SUVD_CGC_GATE__SITE_MASK
>+			| UVD_SUVD_CGC_GATE__SRE_VP9_MASK
>+			| UVD_SUVD_CGC_GATE__SCM_VP9_MASK
>+			| UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
>+			| UVD_SUVD_CGC_GATE__SDB_VP9_MASK
>+			| UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
>+		WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data);
>+
>+		data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
>+		data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
>+		WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
>+	}
>+}
>+
>+/**
>+ * vcn_v2_5_enable_clock_gating - enable VCN clock gating
>+ *
>+ * @adev: amdgpu_device pointer
>+ * @sw: enable SW clock gating
>+ *
>+ * Enable clock gating for VCN block
>+ */
>+static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
>+{
>+	uint32_t data = 0;
>+	int i;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		/* enable UVD CGC */
>+		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
>+		if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
>+			data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
>+		else
>+			data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
>+		data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
>+		data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
>+		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
>+
>+		data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
>+		data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
>+			| UVD_CGC_CTRL__UDEC_CM_MODE_MASK
>+			| UVD_CGC_CTRL__UDEC_IT_MODE_MASK
>+			| UVD_CGC_CTRL__UDEC_DB_MODE_MASK
>+			| UVD_CGC_CTRL__UDEC_MP_MODE_MASK
>+			| UVD_CGC_CTRL__SYS_MODE_MASK
>+			| UVD_CGC_CTRL__UDEC_MODE_MASK
>+			| UVD_CGC_CTRL__MPEG2_MODE_MASK
>+			| UVD_CGC_CTRL__REGS_MODE_MASK
>+			| UVD_CGC_CTRL__RBC_MODE_MASK
>+			| UVD_CGC_CTRL__LMI_MC_MODE_MASK
>+			| UVD_CGC_CTRL__LMI_UMC_MODE_MASK
>+			| UVD_CGC_CTRL__IDCT_MODE_MASK
>+			| UVD_CGC_CTRL__MPRD_MODE_MASK
>+			| UVD_CGC_CTRL__MPC_MODE_MASK
>+			| UVD_CGC_CTRL__LBSI_MODE_MASK
>+			| UVD_CGC_CTRL__LRBBM_MODE_MASK
>+			| UVD_CGC_CTRL__WCB_MODE_MASK
>+			| UVD_CGC_CTRL__VCPU_MODE_MASK);
>+		WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
>+
>+		data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL);
>+		data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__IME_MODE_MASK
>+			| UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
>+		WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data);
>+	}
>+}
>+
>+/**
>+ * jpeg_v2_5_start - start JPEG block
>+ *
>+ * @adev: amdgpu_device pointer
>+ *
>+ * Setup and start the JPEG block
>+ */
>+static int jpeg_v2_5_start(struct amdgpu_device *adev)
>+{
>+	struct amdgpu_ring *ring;
>+	uint32_t tmp;
>+	int i;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		ring = &adev->vcn.inst[i].ring_jpeg;
>+		/* disable anti hang mechanism */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS), 0,
>+			~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
>+
>+		/* JPEG disable CGC */
>+		tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL);
>+		tmp |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
>+		tmp |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
>+		tmp |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
>+		WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp);
>+
>+		tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE);
>+		tmp &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
>+			| JPEG_CGC_GATE__JPEG2_DEC_MASK
>+			| JPEG_CGC_GATE__JMCIF_MASK
>+			| JPEG_CGC_GATE__JRBBM_MASK);
>+		WREG32_SOC15(VCN, i, mmJPEG_CGC_GATE, tmp);
>+
>+		tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL);
>+		tmp &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
>+			| JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
>+			| JPEG_CGC_CTRL__JMCIF_MODE_MASK
>+			| JPEG_CGC_CTRL__JRBBM_MODE_MASK);
>+		WREG32_SOC15(VCN, i, mmJPEG_CGC_CTRL, tmp);
>+
>+		/* MJPEG global tiling registers */
>+		WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
>+			adev->gfx.config.gb_addr_config);
>+		WREG32_SOC15(UVD, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
>+			adev->gfx.config.gb_addr_config);
>+
>+		/* enable JMI channel */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL), 0,
>+			~UVD_JMI_CNTL__SOFT_RESET_MASK);
>+
>+		/* enable System Interrupt for JRBC */
>+		WREG32_P(SOC15_REG_OFFSET(VCN, i, mmJPEG_SYS_INT_EN),
>+			JPEG_SYS_INT_EN__DJRBC_MASK,
>+			~JPEG_SYS_INT_EN__DJRBC_MASK);
>+
>+		WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_VMID, 0);
>+		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
>+		WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
>+			lower_32_bits(ring->gpu_addr));
>+		WREG32_SOC15(UVD, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
>+			upper_32_bits(ring->gpu_addr));
>+		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_RPTR, 0);
>+		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR, 0);
>+		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
>+		WREG32_SOC15(UVD, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
>+		ring->wptr = RREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR);
>+	}
>+
>+	return 0;
>+}
>+
>+/**
>+ * jpeg_v2_5_stop - stop JPEG block
>+ *
>+ * @adev: amdgpu_device pointer
>+ *
>+ * stop the JPEG block
>+ */
>+static int jpeg_v2_5_stop(struct amdgpu_device *adev)
>+{
>+	uint32_t tmp;
>+	int i;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		/* reset JMI */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JMI_CNTL),
>+			UVD_JMI_CNTL__SOFT_RESET_MASK,
>+			~UVD_JMI_CNTL__SOFT_RESET_MASK);
>+
>+		tmp = RREG32_SOC15(VCN, i, mmJPEG_CGC_GATE);
>+		tmp |= (JPEG_CGC_GATE__JPEG_DEC_MASK
>+			|JPEG_CGC_GATE__JPEG2_DEC_MASK
>+			|JPEG_CGC_GATE__JMCIF_MASK
>+			|JPEG_CGC_GATE__JRBBM_MASK);
>+		WREG32_SOC15(VCN, i, mmJPEG_CGC_GATE, tmp);
>+
>+		/* enable anti hang mechanism */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_JPEG_POWER_STATUS),
>+			UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
>+			~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
>+	}
>+
>+	return 0;
>+}
>+
>+static int vcn_v2_5_start(struct amdgpu_device *adev)
>+{
>+	struct amdgpu_ring *ring;
>+	uint32_t rb_bufsz, tmp;
>+	int i, j, k, r;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		/* disable register anti-hang mechanism */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
>+			~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
>+
>+		/* set uvd status busy */
>+		tmp = RREG32_SOC15(UVD, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
>+		WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp);
>+	}
>+
>+	/*SW clock gating */
>+	vcn_v2_5_disable_clock_gating(adev);
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		/* enable VCPU clock */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
>+			UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
>+
>+		/* disable master interrupt */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 0,
>+			~UVD_MASTINT_EN__VCPU_EN_MASK);
>+
>+		/* setup mmUVD_LMI_CTRL */
>+		tmp = RREG32_SOC15(UVD, i, mmUVD_LMI_CTRL);
>+		tmp &= ~0xff;
>+		WREG32_SOC15(UVD, i, mmUVD_LMI_CTRL, tmp | 0x8|
>+			UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK	|
>+			UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
>+			UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
>+			UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
>+
>+		/* setup mmUVD_MPC_CNTL */
>+		tmp = RREG32_SOC15(UVD, i, mmUVD_MPC_CNTL);
>+		tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
>+		tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
>+		WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
>+
>+		/* setup UVD_MPC_SET_MUXA0 */
>+		WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXA0,
>+			((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
>+			(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
>+			(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
>+			(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
>+
>+		/* setup UVD_MPC_SET_MUXB0 */
>+		WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUXB0,
>+			((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
>+			(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
>+			(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
>+			(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
>+
>+		/* setup mmUVD_MPC_SET_MUX */
>+		WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUX,
>+			((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
>+			(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>+			(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
>+	}
>+
>+	vcn_v2_5_mc_resume(adev);
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		/* VCN global tiling registers */
>+		WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG,
>+			adev->gfx.config.gb_addr_config);
>+		WREG32_SOC15(UVD, i, mmUVD_GFX8_ADDR_CONFIG,
>+			adev->gfx.config.gb_addr_config);
>+
>+		/* enable LMI MC and UMC channels */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
>+			~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
>+
>+		/* unblock VCPU register access */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL), 0,
>+			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
>+
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
>+			~UVD_VCPU_CNTL__BLK_RST_MASK);
>+
>+		for (k = 0; k < 10; ++k) {
>+			uint32_t status;
>+
>+			for (j = 0; j < 100; ++j) {
>+				status = RREG32_SOC15(UVD, i, mmUVD_STATUS);
>+				if (status & 2)
>+					break;
>+				if (amdgpu_emu_mode == 1)
>+					msleep(500);
>+				else
>+					mdelay(10);
>+			}
>+			r = 0;
>+			if (status & 2)
>+				break;
>+
>+			DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
>+			WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
>+				UVD_VCPU_CNTL__BLK_RST_MASK,
>+				~UVD_VCPU_CNTL__BLK_RST_MASK);
>+			mdelay(10);
>+			WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
>+				~UVD_VCPU_CNTL__BLK_RST_MASK);
>+
>+			mdelay(10);
>+			r = -1;
>+		}
>+
>+		if (r) {
>+			DRM_ERROR("VCN decode not responding, giving up!!!\n");
>+			return r;
>+		}
>+
>+		/* enable master interrupt */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
>+			UVD_MASTINT_EN__VCPU_EN_MASK,
>+			~UVD_MASTINT_EN__VCPU_EN_MASK);
>+
>+		/* clear the busy bit of VCN_STATUS */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0,
>+			~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
>+
>+		WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_VMID, 0);
>+
>+		ring = &adev->vcn.inst[i].ring_dec;
>+		/* force RBC into idle state */
>+		rb_bufsz = order_base_2(ring->ring_size);
>+		tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
>+		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
>+		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
>+		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
>+		tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
>+		WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, tmp);
>+
>+		/* programm the RB_BASE for ring buffer */
>+		WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
>+			lower_32_bits(ring->gpu_addr));
>+		WREG32_SOC15(UVD, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
>+			upper_32_bits(ring->gpu_addr));
>+
>+		/* Initialize the ring buffer's read and write pointers */
>+		WREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR, 0);
>+
>+		ring->wptr = RREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR);
>+		WREG32_SOC15(UVD, i, mmUVD_RBC_RB_WPTR,
>+				lower_32_bits(ring->wptr));
>+		ring = &adev->vcn.inst[i].ring_enc[0];
>+		WREG32_SOC15(UVD, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
>+		WREG32_SOC15(UVD, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
>+		WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
>+		WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
>+		WREG32_SOC15(UVD, i, mmUVD_RB_SIZE, ring->ring_size / 4);
>+
>+		ring = &adev->vcn.inst[i].ring_enc[1];
>+		WREG32_SOC15(UVD, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
>+		WREG32_SOC15(UVD, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
>+		WREG32_SOC15(UVD, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
>+		WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
>+		WREG32_SOC15(UVD, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
>+	}
>+	r = jpeg_v2_5_start(adev);
>+
>+	return r;
>+}
>+
>+static int vcn_v2_5_stop(struct amdgpu_device *adev)
>+{
>+	uint32_t tmp;
>+	int i, r;
>+
>+	r = jpeg_v2_5_stop(adev);
>+	if (r)
>+		return r;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		/* wait for vcn idle */
>+		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
>+		if (r)
>+			return r;
>+
>+		tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
>+			UVD_LMI_STATUS__READ_CLEAN_MASK |
>+			UVD_LMI_STATUS__WRITE_CLEAN_MASK |
>+			UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
>+		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
>+		if (r)
>+			return r;
>+
>+		/* block LMI UMC channel */
>+		tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
>+		tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
>+		WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
>+
>+		tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
>+			UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
>+		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp, r);
>+		if (r)
>+			return r;
>+
>+		/* block VCPU register access */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_ARB_CTRL),
>+			UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
>+			~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
>+
>+		/* reset VCPU */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
>+			UVD_VCPU_CNTL__BLK_RST_MASK,
>+			~UVD_VCPU_CNTL__BLK_RST_MASK);
>+
>+		/* disable VCPU clock */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 0,
>+			~(UVD_VCPU_CNTL__CLK_EN_MASK));
>+
>+		/* clear status */
>+		WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
>+
>+		vcn_v2_5_enable_clock_gating(adev);
>+
>+		/* enable register anti-hang mechanism */
>+		WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS),
>+			UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
>+			~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
>+	}
>+
>+	return 0;
>+}
>+
>+/**
>+ * vcn_v2_5_dec_ring_get_rptr - get read pointer
>+ *
>+ * @ring: amdgpu_ring pointer
>+ *
>+ * Returns the current hardware read pointer
>+ */
>+static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
>+{
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
>+}
>+
>+/**
>+ * vcn_v2_5_dec_ring_get_wptr - get write pointer
>+ *
>+ * @ring: amdgpu_ring pointer
>+ *
>+ * Returns the current hardware write pointer
>+ */
>+static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
>+{
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	if (ring->use_doorbell)
>+		return adev->wb.wb[ring->wptr_offs];
>+	else
>+		return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
>+}
>+
>+/**
>+ * vcn_v2_5_dec_ring_set_wptr - set write pointer
>+ *
>+ * @ring: amdgpu_ring pointer
>+ *
>+ * Commits the write pointer to the hardware
>+ */
>+static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
>+{
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	if (ring->use_doorbell) {
>+		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
>+		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
>+	} else {
>+		WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
>+	}
>+}
>+
>+static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
>+	.type = AMDGPU_RING_TYPE_VCN_DEC,
>+	.align_mask = 0xf,
>+	.vmhub = AMDGPU_MMHUB_1,
>+	.get_rptr = vcn_v2_5_dec_ring_get_rptr,
>+	.get_wptr = vcn_v2_5_dec_ring_get_wptr,
>+	.set_wptr = vcn_v2_5_dec_ring_set_wptr,
>+	.emit_frame_size =
>+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
>+		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
>+		8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
>+		14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
>+		6,
>+	.emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
>+	.emit_ib = vcn_v2_0_dec_ring_emit_ib,
>+	.emit_fence = vcn_v2_0_dec_ring_emit_fence,
>+	.emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
>+	.test_ring = amdgpu_vcn_dec_ring_test_ring,
>+	.test_ib = amdgpu_vcn_dec_ring_test_ib,
>+	.insert_nop = vcn_v2_0_dec_ring_insert_nop,
>+	.insert_start = vcn_v2_0_dec_ring_insert_start,
>+	.insert_end = vcn_v2_0_dec_ring_insert_end,
>+	.pad_ib = amdgpu_ring_generic_pad_ib,
>+	.begin_use = amdgpu_vcn_ring_begin_use,
>+	.end_use = amdgpu_vcn_ring_end_use,
>+	.emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
>+	.emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
>+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
>+};
>+
>+/**
>+ * vcn_v2_5_enc_ring_get_rptr - get enc read pointer
>+ *
>+ * @ring: amdgpu_ring pointer
>+ *
>+ * Returns the current hardware enc read pointer
>+ */
>+static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
>+{
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
>+		return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
>+	else
>+		return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
>+}
>+
>+/**
>+ * vcn_v2_5_enc_ring_get_wptr - get enc write pointer
>+ *
>+ * @ring: amdgpu_ring pointer
>+ *
>+ * Returns the current hardware enc write pointer
>+ */
>+static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
>+{
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
>+		if (ring->use_doorbell)
>+			return adev->wb.wb[ring->wptr_offs];
>+		else
>+			return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
>+	} else {
>+		if (ring->use_doorbell)
>+			return adev->wb.wb[ring->wptr_offs];
>+		else
>+			return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
>+	}
>+}
>+
>+/**
>+ * vcn_v2_5_enc_ring_set_wptr - set enc write pointer
>+ *
>+ * @ring: amdgpu_ring pointer
>+ *
>+ * Commits the enc write pointer to the hardware
>+ */
>+static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
>+{
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
>+		if (ring->use_doorbell) {
>+			adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
>+			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
>+		} else {
>+			WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
>+		}
>+	} else {
>+		if (ring->use_doorbell) {
>+			adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
>+			WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
>+		} else {
>+			WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
>+		}
>+	}
>+}
>+
>+static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
>+	.type = AMDGPU_RING_TYPE_VCN_ENC,
>+	.align_mask = 0x3f,
>+	.nop = VCN_ENC_CMD_NO_OP,
>+	.vmhub = AMDGPU_MMHUB_1,
>+	.get_rptr = vcn_v2_5_enc_ring_get_rptr,
>+	.get_wptr = vcn_v2_5_enc_ring_get_wptr,
>+	.set_wptr = vcn_v2_5_enc_ring_set_wptr,
>+	.emit_frame_size =
>+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
>+		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
>+		4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
>+		5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
>+		1, /* vcn_v2_0_enc_ring_insert_end */
>+	.emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
>+	.emit_ib = vcn_v2_0_enc_ring_emit_ib,
>+	.emit_fence = vcn_v2_0_enc_ring_emit_fence,
>+	.emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
>+	.test_ring = amdgpu_vcn_enc_ring_test_ring,
>+	.test_ib = amdgpu_vcn_enc_ring_test_ib,
>+	.insert_nop = amdgpu_ring_insert_nop,
>+	.insert_end = vcn_v2_0_enc_ring_insert_end,
>+	.pad_ib = amdgpu_ring_generic_pad_ib,
>+	.begin_use = amdgpu_vcn_ring_begin_use,
>+	.end_use = amdgpu_vcn_ring_end_use,
>+	.emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
>+	.emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
>+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
>+};
>+
>+/**
>+ * vcn_v2_5_jpeg_ring_get_rptr - get read pointer
>+ *
>+ * @ring: amdgpu_ring pointer
>+ *
>+ * Returns the current hardware read pointer
>+ */
>+static uint64_t vcn_v2_5_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
>+{
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_RPTR);
>+}
>+
>+/**
>+ * vcn_v2_5_jpeg_ring_get_wptr - get write pointer
>+ *
>+ * @ring: amdgpu_ring pointer
>+ *
>+ * Returns the current hardware write pointer
>+ */
>+static uint64_t vcn_v2_5_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
>+{
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	if (ring->use_doorbell)
>+		return adev->wb.wb[ring->wptr_offs];
>+	else
>+		return RREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR);
>+}
>+
>+/**
>+ * vcn_v2_5_jpeg_ring_set_wptr - set write pointer
>+ *
>+ * @ring: amdgpu_ring pointer
>+ *
>+ * Commits the write pointer to the hardware
>+ */
>+static void vcn_v2_5_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
>+{
>+	struct amdgpu_device *adev = ring->adev;
>+
>+	if (ring->use_doorbell) {
>+		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
>+		WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
>+	} else {
>+		WREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
>+	}
>+}
>+
>+static const struct amdgpu_ring_funcs vcn_v2_5_jpeg_ring_vm_funcs = {
>+	.type = AMDGPU_RING_TYPE_VCN_JPEG,
>+	.align_mask = 0xf,
>+	.vmhub = AMDGPU_MMHUB_1,
>+	.get_rptr = vcn_v2_5_jpeg_ring_get_rptr,
>+	.get_wptr = vcn_v2_5_jpeg_ring_get_wptr,
>+	.set_wptr = vcn_v2_5_jpeg_ring_set_wptr,
>+	.emit_frame_size =
>+		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
>+		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
>+		8 + /* vcn_v2_0_jpeg_ring_emit_vm_flush */
>+		18 + 18 + /* vcn_v2_0_jpeg_ring_emit_fence x2 vm fence */
>+		8 + 16,
>+	.emit_ib_size = 22, /* vcn_v2_0_jpeg_ring_emit_ib */
>+	.emit_ib = vcn_v2_0_jpeg_ring_emit_ib,
>+	.emit_fence = vcn_v2_0_jpeg_ring_emit_fence,
>+	.emit_vm_flush = vcn_v2_0_jpeg_ring_emit_vm_flush,
>+	.test_ring = amdgpu_vcn_jpeg_ring_test_ring,
>+	.test_ib = amdgpu_vcn_jpeg_ring_test_ib,
>+	.insert_nop = vcn_v2_0_jpeg_ring_nop,
>+	.insert_start = vcn_v2_0_jpeg_ring_insert_start,
>+	.insert_end = vcn_v2_0_jpeg_ring_insert_end,
>+	.pad_ib = amdgpu_ring_generic_pad_ib,
>+	.begin_use = amdgpu_vcn_ring_begin_use,
>+	.end_use = amdgpu_vcn_ring_end_use,
>+	.emit_wreg = vcn_v2_0_jpeg_ring_emit_wreg,
>+	.emit_reg_wait = vcn_v2_0_jpeg_ring_emit_reg_wait,
>+	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
>+};
>+
>+static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
>+{
>+	int i;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
>+		adev->vcn.inst[i].ring_dec.me = i;
>+		DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i);
>+	}
>+}
>+
>+static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
>+{
>+	int i, j;
>+
>+	for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
>+		if (adev->vcn.harvest_config & (1 << j))
>+			continue;
>+		for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
>+			adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
>+			adev->vcn.inst[j].ring_enc[i].me = j;
>+		}
>+		DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j);
>+	}
>+}
>+
>+static void vcn_v2_5_set_jpeg_ring_funcs(struct amdgpu_device *adev)
>+{
>+	int i;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		adev->vcn.inst[i].ring_jpeg.funcs = &vcn_v2_5_jpeg_ring_vm_funcs;
>+		adev->vcn.inst[i].ring_jpeg.me = i;
>+		DRM_INFO("VCN(%d) jpeg decode is enabled in VM mode\n", i);
>+	}
>+}
>+
>+static bool vcn_v2_5_is_idle(void *handle)
>+{
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+	int i, ret = 1;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
>+	}
>+
>+	return ret;
>+}
>+
>+static int vcn_v2_5_wait_for_idle(void *handle)
>+{
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+	int i, ret = 0;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
>+			UVD_STATUS__IDLE, ret);
>+		if (ret)
>+			return ret;
>+	}
>+
>+	return ret;
>+}
>+
>+static int vcn_v2_5_set_clockgating_state(void *handle,
>+					  enum amd_clockgating_state state)
>+{
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
>+
>+	if (enable) {
>+		if (vcn_v2_5_is_idle(handle))
>+			return -EBUSY;
>+		vcn_v2_5_enable_clock_gating(adev);
>+	} else {
>+		vcn_v2_5_disable_clock_gating(adev);
>+	}
>+
>+	return 0;
>+}
>+
>+static int vcn_v2_5_set_powergating_state(void *handle,
>+					  enum amd_powergating_state state)
>+{
>+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+	int ret;
>+
>+	if(state == adev->vcn.cur_state)
>+		return 0;
>+
>+	if (state == AMD_PG_STATE_GATE)
>+		ret = vcn_v2_5_stop(adev);
>+	else
>+		ret = vcn_v2_5_start(adev);
>+
>+	if(!ret)
>+		adev->vcn.cur_state = state;
>+
>+	return ret;
>+}
>+
>+static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
>+					struct amdgpu_irq_src *source,
>+					unsigned type,
>+					enum amdgpu_interrupt_state state)
>+{
>+	return 0;
>+}
>+
>+static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
>+				      struct amdgpu_irq_src *source,
>+				      struct amdgpu_iv_entry *entry)
>+{
>+	uint32_t ip_instance;
>+
>+	switch (entry->client_id) {
>+	case SOC15_IH_CLIENTID_VCN:
>+		ip_instance = 0;
>+		break;
>+	case SOC15_IH_CLIENTID_VCN1:
>+		ip_instance = 1;
>+		break;
>+	default:
>+		DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
>+		return 0;
>+	}
>+
>+	DRM_DEBUG("IH: VCN TRAP\n");
>+
>+	switch (entry->src_id) {
>+	case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
>+		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
>+		break;
>+	case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
>+		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
>+		break;
>+	case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
>+		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
>+		break;
>+	case VCN_2_0__SRCID__JPEG_DECODE:
>+		amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_jpeg);
>+		break;
>+	default:
>+		DRM_ERROR("Unhandled interrupt: %d %d\n",
>+			  entry->src_id, entry->src_data[0]);
>+		break;
>+	}
>+
>+	return 0;
>+}
>+
>+static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
>+	.set = vcn_v2_5_set_interrupt_state,
>+	.process = vcn_v2_5_process_interrupt,
>+};
>+
>+static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
>+{
>+	int i;
>+
>+	for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>+		if (adev->vcn.harvest_config & (1 << i))
>+			continue;
>+		adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 2;
>+		adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
>+	}
>+}
>+
>+static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
>+	.name = "vcn_v2_5",
>+	.early_init = vcn_v2_5_early_init,
>+	.late_init = NULL,
>+	.sw_init = vcn_v2_5_sw_init,
>+	.sw_fini = vcn_v2_5_sw_fini,
>+	.hw_init = vcn_v2_5_hw_init,
>+	.hw_fini = vcn_v2_5_hw_fini,
>+	.suspend = vcn_v2_5_suspend,
>+	.resume = vcn_v2_5_resume,
>+	.is_idle = vcn_v2_5_is_idle,
>+	.wait_for_idle = vcn_v2_5_wait_for_idle,
>+	.check_soft_reset = NULL,
>+	.pre_soft_reset = NULL,
>+	.soft_reset = NULL,
>+	.post_soft_reset = NULL,
>+	.set_clockgating_state = vcn_v2_5_set_clockgating_state,
>+	.set_powergating_state = vcn_v2_5_set_powergating_state,
>+};
>+
>+const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
>+{
>+		.type = AMD_IP_BLOCK_TYPE_VCN,
>+		.major = 2,
>+		.minor = 5,
>+		.rev = 0,
>+		.funcs = &vcn_v2_5_ip_funcs,
>+};
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.h	2019-08-31 15:01:11.852736168 -0500
>@@ -0,0 +1,29 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef __VCN_V2_5_H__
>+#define __VCN_V2_5_H__
>+
>+extern const struct amdgpu_ip_block_version vcn_v2_5_ip_block;
>+
>+#endif /* __VCN_V2_5_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vega10_ih.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vega10_ih.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vega10_ih.c	2019-08-31 15:01:11.852736168 -0500
>@@ -50,7 +50,7 @@
> 
> 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
> 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);
>-	if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
>+	if (amdgpu_sriov_vf(adev)) {
> 		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
> 			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> 			return;
>@@ -64,7 +64,7 @@
> 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
> 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> 					   RB_ENABLE, 1);
>-		if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
>+		if (amdgpu_sriov_vf(adev)) {
> 			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
> 						ih_rb_cntl)) {
> 				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
>@@ -80,7 +80,7 @@
> 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> 					   RB_ENABLE, 1);
>-		if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
>+		if (amdgpu_sriov_vf(adev)) {
> 			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
> 						ih_rb_cntl)) {
> 				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
>@@ -106,7 +106,7 @@
> 
> 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
> 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);
>-	if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
>+	if (amdgpu_sriov_vf(adev)) {
> 		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
> 			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> 			return;
>@@ -125,7 +125,7 @@
> 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);
> 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
> 					   RB_ENABLE, 0);
>-		if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
>+		if (amdgpu_sriov_vf(adev)) {
> 			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
> 						ih_rb_cntl)) {
> 				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
>@@ -145,7 +145,7 @@
> 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
> 					   RB_ENABLE, 0);
>-		if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
>+		if (amdgpu_sriov_vf(adev)) {
> 			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
> 						ih_rb_cntl)) {
> 				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
>@@ -219,7 +219,7 @@
> static int vega10_ih_irq_init(struct amdgpu_device *adev)
> {
> 	struct amdgpu_ih_ring *ih;
>-	u32 ih_rb_cntl;
>+	u32 ih_rb_cntl, ih_chicken;
> 	int ret = 0;
> 	u32 tmp;
> 
>@@ -234,11 +234,17 @@
> 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);
> 
> 	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL);
>+	ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
> 	ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
>+	if (adev->irq.ih.use_bus_addr) {
>+		ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
>+	} else {
>+		ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_FBPA_ENABLE, 1);
>+	}
> 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,
> 				   !!adev->irq.msi_enabled);
> 
>-	if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
>+	if (amdgpu_sriov_vf(adev)) {
> 		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {
> 			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> 			return -ETIMEDOUT;
>@@ -247,6 +253,11 @@
> 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
> 	}
> 
>+	if ((adev->asic_type == CHIP_ARCTURUS
>+		&& adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)
>+		|| adev->asic_type == CHIP_RENOIR)
>+		WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
>+
> 	/* set the writeback address whether it's enabled or not */
> 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,
> 		     lower_32_bits(ih->wptr_addr));
>@@ -272,7 +283,7 @@
> 					   WPTR_OVERFLOW_ENABLE, 0);
> 		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
> 					   RB_FULL_DRAIN_ENABLE, 1);
>-		if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
>+		if (amdgpu_sriov_vf(adev)) {
> 			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,
> 						ih_rb_cntl)) {
> 				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");
>@@ -299,7 +310,7 @@
> 		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
> 		ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);
> 
>-		if (amdgpu_virt_support_psp_prg_ih_reg(adev)) {
>+		if (amdgpu_sriov_vf(adev)) {
> 			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,
> 						ih_rb_cntl)) {
> 				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c	2019-08-31 15:01:11.852736168 -0500
>@@ -81,6 +81,10 @@
> 	adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_DOORBELL64_VCE_RING2_3;
> 	adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_DOORBELL64_VCE_RING4_5;
> 	adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
>+	adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_DOORBELL64_VCN0_1;
>+	adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_DOORBELL64_VCN2_3;
>+	adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_DOORBELL64_VCN4_5;
>+	adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_DOORBELL64_VCN6_7;
> 
> 	adev->doorbell_index.first_non_cp = AMDGPU_DOORBELL64_FIRST_NON_CP;
> 	adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL64_LAST_NON_CP;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c	2019-08-31 15:01:11.852736168 -0500
>@@ -50,6 +50,8 @@
> 		adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
> 		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
> 		adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
>+		adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));
>+		adev->reg_offset[RSMU_HWIP][i] = (uint32_t *)(&(RSMU_BASE.instance[i]));
> 	}
> 	return 0;
> }
>@@ -85,6 +87,10 @@
> 	adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3;
> 	adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5;
> 	adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7;
>+	adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_VEGA20_DOORBELL64_VCN0_1;
>+	adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_VEGA20_DOORBELL64_VCN2_3;
>+	adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_VEGA20_DOORBELL64_VCN4_5;
>+	adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_VEGA20_DOORBELL64_VCN6_7;
> 
> 	adev->doorbell_index.first_non_cp = AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP;
> 	adev->doorbell_index.last_non_cp = AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vi.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdgpu/vi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdgpu/vi.c	2019-08-31 15:01:11.852736168 -0500
>@@ -711,6 +711,12 @@
> 	return r;
> }
> 
>+static enum amd_reset_method
>+vi_asic_reset_method(struct amdgpu_device *adev)
>+{
>+	return AMD_RESET_METHOD_LEGACY;
>+}
>+
> static u32 vi_get_config_memsize(struct amdgpu_device *adev)
> {
> 	return RREG32(mmCONFIG_MEMSIZE);
>@@ -1023,6 +1029,7 @@
> 	.read_bios_from_rom = &vi_read_bios_from_rom,
> 	.read_register = &vi_read_register,
> 	.reset = &vi_asic_reset,
>+	.reset_method = &vi_asic_reset_method,
> 	.set_vga_state = &vi_vga_set_state,
> 	.get_xclk = &vi_get_xclk,
> 	.set_uvd_clocks = &vi_set_uvd_clocks,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm	2019-08-31 15:01:11.853736168 -0500
>@@ -20,1105 +20,947 @@
>  * OTHER DEALINGS IN THE SOFTWARE.
>  */
> 
>+var SQ_WAVE_STATUS_INST_ATC_SHIFT		= 23
>+var SQ_WAVE_STATUS_INST_ATC_MASK		= 0x00800000
>+var SQ_WAVE_STATUS_SPI_PRIO_MASK		= 0x00000006
>+var SQ_WAVE_STATUS_HALT_MASK			= 0x2000
> 
>-shader main
>-
>-asic(DEFAULT)
>-
>-type(CS)
>+var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT		= 12
>+var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE		= 9
>+var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT		= 8
>+var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE		= 6
>+var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT		= 24
>+var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE		= 4
>+var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT	= 24
>+var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE	= 4
>+var SQ_WAVE_IB_STS2_WAVE64_SHIFT		= 11
>+var SQ_WAVE_IB_STS2_WAVE64_SIZE			= 1
>+
>+var SQ_WAVE_TRAPSTS_SAVECTX_MASK		= 0x400
>+var SQ_WAVE_TRAPSTS_EXCE_MASK			= 0x1FF
>+var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT		= 10
>+var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK		= 0x100
>+var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT		= 8
>+var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK		= 0x3FF
>+var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT		= 0x0
>+var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE		= 10
>+var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK		= 0xFFFFF800
>+var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT		= 11
>+var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE		= 21
>+var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK		= 0x800
>+
>+var SQ_WAVE_IB_STS_RCNT_SHIFT			= 16
>+var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT		= 15
>+var SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT		= 25
>+var SQ_WAVE_IB_STS_REPLAY_W64H_SIZE		= 1
>+var SQ_WAVE_IB_STS_REPLAY_W64H_MASK		= 0x02000000
>+var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE		= 1
>+var SQ_WAVE_IB_STS_RCNT_SIZE			= 6
>+var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK	= 0x003F8000
>+var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG	= 0x00007FFF
>+
>+var SQ_BUF_RSRC_WORD1_ATC_SHIFT			= 24
>+var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT		= 27
>+
>+// bits [31:24] unused by SPI debug data
>+var TTMP11_SAVE_REPLAY_W64H_SHIFT		= 31
>+var TTMP11_SAVE_REPLAY_W64H_MASK		= 0x80000000
>+var TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT		= 24
>+var TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK		= 0x7F000000
>+
>+// SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14]
>+// when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE
>+var S_SAVE_BUF_RSRC_WORD1_STRIDE		= 0x00040000
>+var S_SAVE_BUF_RSRC_WORD3_MISC			= 0x10807FAC
>+
>+var S_SAVE_SPI_INIT_ATC_MASK			= 0x08000000
>+var S_SAVE_SPI_INIT_ATC_SHIFT			= 27
>+var S_SAVE_SPI_INIT_MTYPE_MASK			= 0x70000000
>+var S_SAVE_SPI_INIT_MTYPE_SHIFT			= 28
>+var S_SAVE_SPI_INIT_FIRST_WAVE_MASK		= 0x04000000
>+var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT		= 26
>+
>+var S_SAVE_PC_HI_RCNT_SHIFT			= 26
>+var S_SAVE_PC_HI_RCNT_MASK			= 0xFC000000
>+var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT		= 25
>+var S_SAVE_PC_HI_FIRST_REPLAY_MASK		= 0x02000000
>+var S_SAVE_PC_HI_REPLAY_W64H_SHIFT		= 24
>+var S_SAVE_PC_HI_REPLAY_W64H_MASK		= 0x01000000
>+
>+var s_sgpr_save_num				= 108
>+
>+var s_save_spi_init_lo				= exec_lo
>+var s_save_spi_init_hi				= exec_hi
>+var s_save_pc_lo				= ttmp0
>+var s_save_pc_hi				= ttmp1
>+var s_save_exec_lo				= ttmp2
>+var s_save_exec_hi				= ttmp3
>+var s_save_status				= ttmp12
>+var s_save_trapsts				= ttmp5
>+var s_save_xnack_mask				= ttmp6
>+var s_wave_size					= ttmp7
>+var s_save_buf_rsrc0				= ttmp8
>+var s_save_buf_rsrc1				= ttmp9
>+var s_save_buf_rsrc2				= ttmp10
>+var s_save_buf_rsrc3				= ttmp11
>+var s_save_mem_offset				= ttmp14
>+var s_save_alloc_size				= s_save_trapsts
>+var s_save_tmp					= s_save_buf_rsrc2
>+var s_save_m0					= ttmp15
>+
>+var S_RESTORE_BUF_RSRC_WORD1_STRIDE		= S_SAVE_BUF_RSRC_WORD1_STRIDE
>+var S_RESTORE_BUF_RSRC_WORD3_MISC		= S_SAVE_BUF_RSRC_WORD3_MISC
>+
>+var S_RESTORE_SPI_INIT_ATC_MASK			= 0x08000000
>+var S_RESTORE_SPI_INIT_ATC_SHIFT		= 27
>+var S_RESTORE_SPI_INIT_MTYPE_MASK		= 0x70000000
>+var S_RESTORE_SPI_INIT_MTYPE_SHIFT		= 28
>+var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK		= 0x04000000
>+var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT		= 26
>+var S_WAVE_SIZE					= 25
>+
>+var S_RESTORE_PC_HI_RCNT_SHIFT			= S_SAVE_PC_HI_RCNT_SHIFT
>+var S_RESTORE_PC_HI_RCNT_MASK			= S_SAVE_PC_HI_RCNT_MASK
>+var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT		= S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
>+var S_RESTORE_PC_HI_FIRST_REPLAY_MASK		= S_SAVE_PC_HI_FIRST_REPLAY_MASK
>+
>+var s_restore_spi_init_lo			= exec_lo
>+var s_restore_spi_init_hi			= exec_hi
>+var s_restore_mem_offset			= ttmp12
>+var s_restore_alloc_size			= ttmp3
>+var s_restore_tmp				= ttmp6
>+var s_restore_mem_offset_save			= s_restore_tmp
>+var s_restore_m0				= s_restore_alloc_size
>+var s_restore_mode				= ttmp7
>+var s_restore_flat_scratch			= ttmp2
>+var s_restore_pc_lo				= ttmp0
>+var s_restore_pc_hi				= ttmp1
>+var s_restore_exec_lo				= ttmp14
>+var s_restore_exec_hi				= ttmp15
>+var s_restore_status				= ttmp4
>+var s_restore_trapsts				= ttmp5
>+var s_restore_xnack_mask			= ttmp13
>+var s_restore_buf_rsrc0				= ttmp8
>+var s_restore_buf_rsrc1				= ttmp9
>+var s_restore_buf_rsrc2				= ttmp10
>+var s_restore_buf_rsrc3				= ttmp11
>+var s_restore_size				= ttmp7
> 
>-wave_size(32)
>-/*************************************************************************/
>-/*					control on how to run the shader					 */
>-/*************************************************************************/
>-//any hack that needs to be made to run this code in EMU (either becasue various EMU code are not ready or no compute save & restore in EMU run)
>-var EMU_RUN_HACK					=	0
>-var EMU_RUN_HACK_RESTORE_NORMAL		=	0
>-var EMU_RUN_HACK_SAVE_NORMAL_EXIT	=	0
>-var	EMU_RUN_HACK_SAVE_SINGLE_WAVE	=	0
>-var EMU_RUN_HACK_SAVE_FIRST_TIME	= 	0					//for interrupted restore in which the first save is through EMU_RUN_HACK
>-var SAVE_LDS						= 	0
>-var WG_BASE_ADDR_LO					=   0x9000a000
>-var WG_BASE_ADDR_HI					=	0x0
>-var WAVE_SPACE						=	0x9000				//memory size that each wave occupies in workgroup state mem, increase from 5000 to 9000 for more SGPR need to be saved
>-var CTX_SAVE_CONTROL				=	0x0
>-var CTX_RESTORE_CONTROL				=	CTX_SAVE_CONTROL
>-var SIM_RUN_HACK					=	0					//any hack that needs to be made to run this code in SIM (either becasue various RTL code are not ready or no compute save & restore in RTL run)
>-var	SGPR_SAVE_USE_SQC				=	0					//use SQC D$ to do the write
>-var USE_MTBUF_INSTEAD_OF_MUBUF		=	0					//need to change BUF_DATA_FORMAT in S_SAVE_BUF_RSRC_WORD3_MISC from 0 to BUF_DATA_FORMAT_32 if set to 1 (i.e. 0x00827FAC)
>-var SWIZZLE_EN						=	0					//whether we use swizzled buffer addressing
>-var SAVE_RESTORE_HWID_DDID          =   0
>-var RESTORE_DDID_IN_SGPR18          =   0
>-/**************************************************************************/
>-/*                     	variables							              */
>-/**************************************************************************/
>-var SQ_WAVE_STATUS_INST_ATC_SHIFT  = 23
>-var SQ_WAVE_STATUS_INST_ATC_MASK   = 0x00800000
>-var SQ_WAVE_STATUS_SPI_PRIO_MASK   = 0x00000006
>+shader main
>+	asic(DEFAULT)
>+	type(CS)
>+	wave_size(32)
> 
>-var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT	= 12
>-var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE		= 9
>-var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT	= 8
>-var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE	= 6
>-var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT	= 24
>-var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE	= 4						//FIXME	 sq.blk still has 4 bits at this time while SQ programming guide has 3 bits
>-var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT    = 24
>-var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE     = 4
>-var SQ_WAVE_IB_STS2_WAVE64_SHIFT        = 11
>-var SQ_WAVE_IB_STS2_WAVE64_SIZE         = 1
>-
>-var	SQ_WAVE_TRAPSTS_SAVECTX_MASK	=	0x400
>-var SQ_WAVE_TRAPSTS_EXCE_MASK       =   0x1FF          			// Exception mask
>-var	SQ_WAVE_TRAPSTS_SAVECTX_SHIFT	=	10					
>-var	SQ_WAVE_TRAPSTS_MEM_VIOL_MASK	=	0x100					
>-var	SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT	=	8		
>-var	SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK 	=	0x3FF
>-var	SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT 	=	0x0
>-var	SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE 	=	10
>-var	SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK 	=	0xFFFFF800	
>-var	SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT 	=	11
>-var	SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE 	=	21	
>-
>-var SQ_WAVE_IB_STS_RCNT_SHIFT			=	16					//FIXME
>-var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT	=	15					//FIXME
>-var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE    =   1                   //FIXME
>-var SQ_WAVE_IB_STS_RCNT_SIZE            =   6                   //FIXME
>-var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG	= 0x00007FFF	//FIXME
>- 
>-var	SQ_BUF_RSRC_WORD1_ATC_SHIFT		=	24
>-var	SQ_BUF_RSRC_WORD3_MTYPE_SHIFT	=	27
>-
>-
>-/*      Save        */
>-var	S_SAVE_BUF_RSRC_WORD1_STRIDE		=	0x00040000  		//stride is 4 bytes 
>-var	S_SAVE_BUF_RSRC_WORD3_MISC			= 	0x00807FAC			//SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE			
>-
>-var	S_SAVE_SPI_INIT_ATC_MASK			=	0x08000000			//bit[27]: ATC bit
>-var	S_SAVE_SPI_INIT_ATC_SHIFT			=	27
>-var	S_SAVE_SPI_INIT_MTYPE_MASK			=	0x70000000			//bit[30:28]: Mtype
>-var	S_SAVE_SPI_INIT_MTYPE_SHIFT			=	28
>-var	S_SAVE_SPI_INIT_FIRST_WAVE_MASK		=	0x04000000			//bit[26]: FirstWaveInTG
>-var	S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT	=	26
>-
>-var S_SAVE_PC_HI_RCNT_SHIFT				=	28					//FIXME	 check with Brian to ensure all fields other than PC[47:0] can be used
>-var S_SAVE_PC_HI_RCNT_MASK				=   0xF0000000			//FIXME
>-var S_SAVE_PC_HI_FIRST_REPLAY_SHIFT		=	27					//FIXME
>-var S_SAVE_PC_HI_FIRST_REPLAY_MASK		=	0x08000000			//FIXME
>-
>-var	s_save_spi_init_lo				=	exec_lo
>-var s_save_spi_init_hi				=	exec_hi
>-
>-var	s_save_pc_lo			=	ttmp0			//{TTMP1, TTMP0} = {3¡¯h0,pc_rewind[3:0], HT[0],trapID[7:0], PC[47:0]}
>-var	s_save_pc_hi			=	ttmp1			
>-var s_save_exec_lo			=	ttmp2
>-var s_save_exec_hi			= 	ttmp3			
>-var	s_save_status			=	ttmp4			
>-var	s_save_trapsts			=	ttmp5			//not really used until the end of the SAVE routine
>-var s_wave_size         	=	ttmp6           //ttmp6 is not needed now, since it's only 32bit xnack mask, now use it to determine wave32 or wave64 in EMU_HACK
>-var s_save_xnack_mask	    =	ttmp7
>-var	s_save_buf_rsrc0		=	ttmp8
>-var	s_save_buf_rsrc1		=	ttmp9
>-var	s_save_buf_rsrc2		=	ttmp10
>-var	s_save_buf_rsrc3		=	ttmp11
>-
>-var s_save_mem_offset		= 	ttmp14
>-var s_sgpr_save_num         =   106                     //in gfx10, all sgpr must be saved
>-var s_save_alloc_size		=	s_save_trapsts			//conflict
>-var s_save_tmp              =   s_save_buf_rsrc2       	//shared with s_save_buf_rsrc2  (conflict: should not use mem access with s_save_tmp at the same time)
>-var s_save_m0				=	ttmp15					
>-
>-/*      Restore     */
>-var	S_RESTORE_BUF_RSRC_WORD1_STRIDE			=	S_SAVE_BUF_RSRC_WORD1_STRIDE 
>-var	S_RESTORE_BUF_RSRC_WORD3_MISC			= 	S_SAVE_BUF_RSRC_WORD3_MISC		 
>-
>-var	S_RESTORE_SPI_INIT_ATC_MASK			    =	0x08000000			//bit[27]: ATC bit
>-var	S_RESTORE_SPI_INIT_ATC_SHIFT			=	27
>-var	S_RESTORE_SPI_INIT_MTYPE_MASK			=	0x70000000			//bit[30:28]: Mtype
>-var	S_RESTORE_SPI_INIT_MTYPE_SHIFT			=	28
>-var	S_RESTORE_SPI_INIT_FIRST_WAVE_MASK		=	0x04000000			//bit[26]: FirstWaveInTG
>-var	S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT	    =	26
>-
>-var S_RESTORE_PC_HI_RCNT_SHIFT				=	S_SAVE_PC_HI_RCNT_SHIFT
>-var S_RESTORE_PC_HI_RCNT_MASK				=   S_SAVE_PC_HI_RCNT_MASK
>-var S_RESTORE_PC_HI_FIRST_REPLAY_SHIFT		=	S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
>-var S_RESTORE_PC_HI_FIRST_REPLAY_MASK		=	S_SAVE_PC_HI_FIRST_REPLAY_MASK
>-
>-var s_restore_spi_init_lo                   =   exec_lo
>-var s_restore_spi_init_hi                   =   exec_hi
>-
>-var s_restore_mem_offset		= 	ttmp12
>-var s_restore_alloc_size		=	ttmp3
>-var s_restore_tmp           	=   ttmp6
>-var s_restore_mem_offset_save	= 	s_restore_tmp 		//no conflict
>-
>-var s_restore_m0			=	s_restore_alloc_size	//no conflict			
>-
>-var s_restore_mode			=  	ttmp13
>-var s_restore_hwid1         =  ttmp2
>-var s_restore_ddid          =  s_restore_hwid1
>-var	s_restore_pc_lo		    =	ttmp0			
>-var	s_restore_pc_hi		    =	ttmp1
>-var s_restore_exec_lo		=	ttmp14
>-var s_restore_exec_hi		= 	ttmp15
>-var	s_restore_status	    =	ttmp4			
>-var	s_restore_trapsts	    =	ttmp5
>-//var s_restore_xnack_mask_lo	=	xnack_mask_lo
>-//var s_restore_xnack_mask_hi	=	xnack_mask_hi
>-var s_restore_xnack_mask    =   ttmp7
>-var	s_restore_buf_rsrc0		=	ttmp8
>-var	s_restore_buf_rsrc1		=	ttmp9
>-var	s_restore_buf_rsrc2		=	ttmp10
>-var	s_restore_buf_rsrc3		=	ttmp11
>-var s_restore_size         	=	ttmp13                  //ttmp13 has no conflict
>-
>-/**************************************************************************/
>-/*                     	trap handler entry points			              */
>-/**************************************************************************/
>-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL)) 					//hack to use trap_id for determining save/restore
>-		//FIXME VCCZ un-init assertion s_getreg_b32  	s_save_status, hwreg(HW_REG_STATUS)			//save STATUS since we will change SCC
>-		s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000 				//change SCC
>-    	s_cmp_eq_u32 s_save_tmp, 0x007e0000  						//Save: trap_id = 0x7e. Restore: trap_id = 0x7f.  
>-    	s_cbranch_scc0 L_JUMP_TO_RESTORE							//do not need to recover STATUS here  since we are going to RESTORE
>-		//FIXME  s_setreg_b32 	hwreg(HW_REG_STATUS), 	s_save_status		//need to recover STATUS since we are going to SAVE	
>-		s_branch L_SKIP_RESTORE 									//NOT restore, SAVE actually
>-	else	
>-		s_branch L_SKIP_RESTORE 									//NOT restore. might be a regular trap or save
>-    end
>+	s_branch	L_SKIP_RESTORE						//NOT restore. might be a regular trap or save
> 
> L_JUMP_TO_RESTORE:
>-    s_branch L_RESTORE												//restore
>+	s_branch	L_RESTORE
> 
> L_SKIP_RESTORE:
>-	
>-	s_getreg_b32  	s_save_status, hwreg(HW_REG_STATUS)								//save STATUS since we will change SCC
>-    s_andn2_b32		s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK      //check whether this is for save
>-	s_getreg_b32  	s_save_trapsts, hwreg(HW_REG_TRAPSTS)    		 				
>-	s_and_b32		s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK	//check whether this is for save  
>-	s_cbranch_scc1	L_SAVE															//this is the operation for save
>-
>-    // *********    Handle non-CWSR traps       *******************
>-    if (!EMU_RUN_HACK)
>-		s_getreg_b32     s_save_trapsts, hwreg(HW_REG_TRAPSTS)
>-		s_and_b32        s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK // Check whether it is an exception
>-		s_cbranch_scc1  L_EXCP_CASE   // Exception, jump back to the shader program directly.
>-		s_add_u32    ttmp0, ttmp0, 4   // S_TRAP case, add 4 to ttmp0 
>-		
>-		L_EXCP_CASE:
>-		s_and_b32    ttmp1, ttmp1, 0xFFFF
>-		s_rfe_b64    [ttmp0, ttmp1]
>-	end
>-    // *********        End handling of non-CWSR traps   *******************
>-
>-/**************************************************************************/
>-/*                     	save routine						              */
>-/**************************************************************************/
>+	s_getreg_b32	s_save_status, hwreg(HW_REG_STATUS)			//save STATUS since we will change SCC
>+	s_andn2_b32	s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK
>+	s_getreg_b32	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
>+	s_and_b32	ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK	//check whether this is for save
>+	s_cbranch_scc1	L_SAVE
>+
>+	// If STATUS.MEM_VIOL is asserted then halt the wave to prevent
>+	// the exception raising again and blocking context save.
>+	s_and_b32	ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK
>+	s_cbranch_scc0	L_FETCH_2ND_TRAP
>+	s_or_b32	s_save_status, s_save_status, SQ_WAVE_STATUS_HALT_MASK
>+
>+L_FETCH_2ND_TRAP:
>+	// Preserve and clear scalar XNACK state before issuing scalar loads.
>+	// Save IB_STS.REPLAY_W64H[25], RCNT[21:16], FIRST_REPLAY[15] into
>+	// unused space ttmp11[31:24].
>+	s_andn2_b32	ttmp11, ttmp11, (TTMP11_SAVE_REPLAY_W64H_MASK | TTMP11_SAVE_RCNT_FIRST_REPLAY_MASK)
>+	s_getreg_b32	ttmp2, hwreg(HW_REG_IB_STS)
>+	s_and_b32	ttmp3, ttmp2, SQ_WAVE_IB_STS_REPLAY_W64H_MASK
>+	s_lshl_b32	ttmp3, ttmp3, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT)
>+	s_or_b32	ttmp11, ttmp11, ttmp3
>+	s_and_b32	ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK
>+	s_lshl_b32	ttmp3, ttmp3, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT)
>+	s_or_b32	ttmp11, ttmp11, ttmp3
>+	s_andn2_b32	ttmp2, ttmp2, (SQ_WAVE_IB_STS_REPLAY_W64H_MASK | SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK)
>+	s_setreg_b32	hwreg(HW_REG_IB_STS), ttmp2
>+
>+	// Read second-level TBA/TMA from first-level TMA and jump if available.
>+	// ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data)
>+	// ttmp12 holds SQ_WAVE_STATUS
>+	s_getreg_b32	ttmp4, hwreg(HW_REG_SHADER_TMA_LO)
>+	s_getreg_b32	ttmp5, hwreg(HW_REG_SHADER_TMA_HI)
>+	s_lshl_b64	[ttmp4, ttmp5], [ttmp4, ttmp5], 0x8
>+	s_load_dwordx2	[ttmp2, ttmp3], [ttmp4, ttmp5], 0x0 glc:1		// second-level TBA
>+	s_waitcnt	lgkmcnt(0)
>+	s_load_dwordx2	[ttmp4, ttmp5], [ttmp4, ttmp5], 0x8 glc:1		// second-level TMA
>+	s_waitcnt	lgkmcnt(0)
>+	s_and_b64	[ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3]
>+	s_cbranch_scc0	L_NO_NEXT_TRAP						// second-level trap handler not been set
>+	s_setpc_b64	[ttmp2, ttmp3]						// jump to second-level trap handler
>+
>+L_NO_NEXT_TRAP:
>+	s_getreg_b32	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
>+	s_and_b32	s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_EXCE_MASK
>+	s_cbranch_scc1	L_EXCP_CASE						// Exception, jump back to the shader program directly.
>+	s_add_u32	ttmp0, ttmp0, 4						// S_TRAP case, add 4 to ttmp0
>+	s_addc_u32	ttmp1, ttmp1, 0
>+L_EXCP_CASE:
>+	s_and_b32	ttmp1, ttmp1, 0xFFFF
>+
>+	// Restore SQ_WAVE_IB_STS.
>+	s_lshr_b32	ttmp2, ttmp11, (TTMP11_SAVE_RCNT_FIRST_REPLAY_SHIFT - SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT)
>+	s_and_b32	ttmp3, ttmp2, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK
>+	s_lshr_b32	ttmp2, ttmp11, (TTMP11_SAVE_REPLAY_W64H_SHIFT - SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT)
>+	s_and_b32	ttmp2, ttmp2, SQ_WAVE_IB_STS_REPLAY_W64H_MASK
>+	s_or_b32	ttmp2, ttmp2, ttmp3
>+	s_setreg_b32	hwreg(HW_REG_IB_STS), ttmp2
>+
>+	// Restore SQ_WAVE_STATUS.
>+	s_and_b64	exec, exec, exec					// Restore STATUS.EXECZ, not writable by s_setreg_b32
>+	s_and_b64	vcc, vcc, vcc						// Restore STATUS.VCCZ, not writable by s_setreg_b32
>+	s_setreg_b32	hwreg(HW_REG_STATUS), s_save_status
> 
>-L_SAVE:	
>-	
>+	s_rfe_b64	[ttmp0, ttmp1]
>+
>+L_SAVE:
> 	//check whether there is mem_viol
>-	s_getreg_b32  	s_save_trapsts, hwreg(HW_REG_TRAPSTS)    		 				
>-	s_and_b32		s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK			
>+	s_getreg_b32	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
>+	s_and_b32	s_save_trapsts, s_save_trapsts, SQ_WAVE_TRAPSTS_MEM_VIOL_MASK
> 	s_cbranch_scc0	L_NO_PC_REWIND
>-    
>+
> 	//if so, need rewind PC assuming GDS operation gets NACKed
>-	s_mov_b32       s_save_tmp, 0															//clear mem_viol bit
>-	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT, 1), s_save_tmp	//clear mem_viol bit 
>-	s_and_b32 		s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
>-	s_sub_u32 		s_save_pc_lo, s_save_pc_lo, 8             //pc[31:0]-8
>-	s_subb_u32 		s_save_pc_hi, s_save_pc_hi, 0x0			  // -scc
>+	s_mov_b32	s_save_tmp, 0
>+	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT, 1), s_save_tmp	//clear mem_viol bit
>+	s_and_b32	s_save_pc_hi, s_save_pc_hi, 0x0000ffff			//pc[47:32]
>+	s_sub_u32	s_save_pc_lo, s_save_pc_lo, 8				//pc[31:0]-8
>+	s_subb_u32	s_save_pc_hi, s_save_pc_hi, 0x0
> 
> L_NO_PC_REWIND:
>-    s_mov_b32       s_save_tmp, 0															//clear saveCtx bit
>-	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp		//clear saveCtx bit   
>+	s_mov_b32	s_save_tmp, 0
>+	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp	//clear saveCtx bit
> 
>-	//s_mov_b32		s_save_xnack_mask_lo,	xnack_mask_lo									//save XNACK_MASK  
>-	//s_mov_b32		s_save_xnack_mask_hi,	xnack_mask_hi
>-    s_getreg_b32	s_save_xnack_mask,  hwreg(HW_REG_SHADER_XNACK_MASK)  
>-	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE)					//save RCNT
>-	s_lshl_b32		s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT
>-	s_or_b32		s_save_pc_hi, s_save_pc_hi, s_save_tmp
>-	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE)	//save FIRST_REPLAY
>-	s_lshl_b32		s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
>-	s_or_b32		s_save_pc_hi, s_save_pc_hi, s_save_tmp
>-	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS)										//clear RCNT and FIRST_REPLAY in IB_STS
>-	s_and_b32		s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG
>+	s_getreg_b32	s_save_xnack_mask, hwreg(HW_REG_SHADER_XNACK_MASK)
>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_RCNT_SHIFT, SQ_WAVE_IB_STS_RCNT_SIZE)
>+	s_lshl_b32	s_save_tmp, s_save_tmp, S_SAVE_PC_HI_RCNT_SHIFT
>+	s_or_b32	s_save_pc_hi, s_save_pc_hi, s_save_tmp
>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT, SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE)
>+	s_lshl_b32	s_save_tmp, s_save_tmp, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
>+	s_or_b32	s_save_pc_hi, s_save_pc_hi, s_save_tmp
>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS, SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT, SQ_WAVE_IB_STS_REPLAY_W64H_SIZE)
>+	s_lshl_b32	s_save_tmp, s_save_tmp, S_SAVE_PC_HI_REPLAY_W64H_SHIFT
>+	s_or_b32	s_save_pc_hi, s_save_pc_hi, s_save_tmp
>+	s_getreg_b32	s_save_tmp, hwreg(HW_REG_IB_STS)			//clear RCNT and FIRST_REPLAY and REPLAY_W64H in IB_STS
>+	s_and_b32	s_save_tmp, s_save_tmp, SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG
> 
> 	s_setreg_b32	hwreg(HW_REG_IB_STS), s_save_tmp
>-    
>-	/*		inform SPI the readiness and wait for SPI's go signal */
>-	s_mov_b32		s_save_exec_lo,	exec_lo													//save EXEC and use EXEC for the go signal from SPI
>-	s_mov_b32		s_save_exec_hi,	exec_hi
>-	s_mov_b64		exec, 	0x0																//clear EXEC to get ready to receive
>-	if (EMU_RUN_HACK)
>-	
>-	else
>-		s_sendmsg	sendmsg(MSG_SAVEWAVE)													//send SPI a message and wait for SPI's write to EXEC  
>-	end
>-
>-  L_SLEEP:		
>-	s_sleep 0x2
>-	
>-	if (EMU_RUN_HACK)
>-																							
>-	else
>-		s_cbranch_execz	L_SLEEP                                                         
>-	end
>-
>-
>-	/*      setup Resource Contants    */
>-	if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE))	
>-		//calculate wd_addr using absolute thread id 
>-		v_readlane_b32 s_save_tmp, v9, 0
>-        //determine it is wave32 or wave64
>-        s_getreg_b32 	s_wave_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE)
>-        s_cmp_eq_u32    s_wave_size, 0
>-        s_cbranch_scc1  L_SAVE_WAVE32
>-        s_lshr_b32 s_save_tmp, s_save_tmp, 6 //SAVE WAVE64
>-        s_branch    L_SAVE_CON
>-    L_SAVE_WAVE32:
>-        s_lshr_b32 s_save_tmp, s_save_tmp, 5 //SAVE WAVE32
>-    L_SAVE_CON:
>-		s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE
>-		s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
>-		s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
>-		s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL		
>-	else
>-	end
>-	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE))
>-		s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
>-		s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
>-		s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL		
>-	else
>-	end
>-	
>-	
>-	s_mov_b32		s_save_buf_rsrc0, 	s_save_spi_init_lo														//base_addr_lo
>-	s_and_b32		s_save_buf_rsrc1, 	s_save_spi_init_hi, 0x0000FFFF											//base_addr_hi
>-	s_or_b32		s_save_buf_rsrc1, 	s_save_buf_rsrc1,  S_SAVE_BUF_RSRC_WORD1_STRIDE
>-    s_mov_b32       s_save_buf_rsrc2,   0                                               						//NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited
>-	s_mov_b32		s_save_buf_rsrc3, 	S_SAVE_BUF_RSRC_WORD3_MISC
>-	s_and_b32		s_save_tmp,         s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK		
>-	s_lshr_b32		s_save_tmp,  		s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)			//get ATC bit into position
>-	s_or_b32		s_save_buf_rsrc3, 	s_save_buf_rsrc3,  s_save_tmp											//or ATC
>-	s_and_b32		s_save_tmp,         s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK		
>-	s_lshr_b32		s_save_tmp,  		s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)		//get MTYPE bits into position
>-	s_or_b32		s_save_buf_rsrc3, 	s_save_buf_rsrc3,  s_save_tmp											//or MTYPE	
>-	
>-	s_mov_b32		s_save_m0,			m0																	//save M0
>-	
>-	/* 		global mem offset			*/
>-	s_mov_b32		s_save_mem_offset, 	0x0																		//mem offset initial value = 0
>-    s_getreg_b32 	s_wave_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) //get wave_save_size
>-    s_or_b32        s_wave_size, s_save_spi_init_hi,    s_wave_size                                             //share s_wave_size with exec_hi
>-
>-    /*      	save VGPRs	    */
>-	//////////////////////////////
>-  L_SAVE_VGPR:
>-  
>- 	s_mov_b32		exec_lo, 0xFFFFFFFF 											//need every thread from now on
>-    s_and_b32       m0, s_wave_size, 1
>-    s_cmp_eq_u32    m0, 1  
>-    s_cbranch_scc1  L_ENABLE_SAVE_VGPR_EXEC_HI   
>-    s_mov_b32		exec_hi, 0x00000000
>-    s_branch        L_SAVE_VGPR_NORMAL
>-  L_ENABLE_SAVE_VGPR_EXEC_HI:
>-	s_mov_b32		exec_hi, 0xFFFFFFFF
>-  L_SAVE_VGPR_NORMAL:	
>-	s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 					//vpgr_size
>-	//for wave32 and wave64, the num of vgpr function is the same?
>-    s_add_u32 		s_save_alloc_size, s_save_alloc_size, 1
>-	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 2 						//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)   //FIXME for GFX, zero is possible
>-    //determine it is wave32 or wave64
>-    s_and_b32       m0, s_wave_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_cbranch_scc1  L_SAVE_VGPR_WAVE64
>-
>-    //zhenxu added it for save vgpr for wave32
>-	s_lshl_b32		s_save_buf_rsrc2,  s_save_alloc_size, 7							//NUM_RECORDS in bytes (32 threads*4)
>-	if (SWIZZLE_EN)
>-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
>-	else
>-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
>-	end
>-	
>-    s_mov_b32 		m0, 0x0 														//VGPR initial index value =0
>-	//s_set_gpr_idx_on  m0, 0x1														//M0[7:0] = M0[7:0] and M0[15:12] = 0x1
>-    //s_add_u32		s_save_alloc_size, s_save_alloc_size, 0x1000					//add 0x1000 since we compare m0 against it later, doesn't need this in gfx10
>-
>-  L_SAVE_VGPR_WAVE32_LOOP: 										
>-	v_movrels_b32 		v0, v0															//v0 = v[0+m0]	
>-	    
>-    if(USE_MTBUF_INSTEAD_OF_MUBUF)       
>-		tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-    else
>-		buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>-	end
>-
>-    s_add_u32		m0, m0, 1														//next vgpr index
>-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 128						//every buffer_store_dword does 128 bytes
>-	s_cmp_lt_u32 	m0,	s_save_alloc_size 											//scc = (m0 < s_save_alloc_size) ? 1 : 0
>-	s_cbranch_scc1 	L_SAVE_VGPR_WAVE32_LOOP												//VGPR save is complete?
>-    s_branch    L_SAVE_LDS
>-    //save vgpr for wave32 ends
>-
>-  L_SAVE_VGPR_WAVE64:
>-	s_lshl_b32		s_save_buf_rsrc2,  s_save_alloc_size, 8							//NUM_RECORDS in bytes (64 threads*4)
>-	if (SWIZZLE_EN)
>-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
>-	else
>-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
>-	end
>-	
>-    s_mov_b32 		m0, 0x0 														//VGPR initial index value =0
>-	//s_set_gpr_idx_on  m0, 0x1														//M0[7:0] = M0[7:0] and M0[15:12] = 0x1
>-    //s_add_u32		s_save_alloc_size, s_save_alloc_size, 0x1000					//add 0x1000 since we compare m0 against it later, doesn't need this in gfx10
>-
>-  L_SAVE_VGPR_WAVE64_LOOP: 										
>-	v_movrels_b32 		v0, v0															//v0 = v[0+m0]	
>-	    
>-    if(USE_MTBUF_INSTEAD_OF_MUBUF)       
>-		tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-    else
>-		buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>-	end
>-
>-    s_add_u32		m0, m0, 1														//next vgpr index
>-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 256						//every buffer_store_dword does 256 bytes
>-	s_cmp_lt_u32 	m0,	s_save_alloc_size 											//scc = (m0 < s_save_alloc_size) ? 1 : 0
>-	s_cbranch_scc1 	L_SAVE_VGPR_WAVE64_LOOP												//VGPR save is complete?
>-	//s_set_gpr_idx_off
>-    //
>-    //Below part will be the save shared vgpr part (new for gfx10)
>-    s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) 			//shared_vgpr_size
>-    s_and_b32		s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF				//shared_vgpr_size is zero?
>-    s_cbranch_scc0	L_SAVE_LDS													    //no shared_vgpr used? jump to L_SAVE_LDS
>-    s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 3 						//Number of SHARED_VGPRs = shared_vgpr_size * 8    (non-zero value)
>-    //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count.
>-    //save shared_vgpr will start from the index of m0
>-    s_add_u32       s_save_alloc_size, s_save_alloc_size, m0
>-    s_mov_b32		exec_lo, 0xFFFFFFFF
>-    s_mov_b32		exec_hi, 0x00000000
>-    L_SAVE_SHARED_VGPR_WAVE64_LOOP: 										
>-	v_movrels_b32 		v0, v0															//v0 = v[0+m0]	
>-	buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>-    s_add_u32		m0, m0, 1														//next vgpr index
>-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 128						//every buffer_store_dword does 256 bytes
>-	s_cmp_lt_u32 	m0,	s_save_alloc_size 											//scc = (m0 < s_save_alloc_size) ? 1 : 0
>-	s_cbranch_scc1 	L_SAVE_SHARED_VGPR_WAVE64_LOOP									//SHARED_VGPR save is complete?
>-    
>-	/*      	save LDS	    */
>-	//////////////////////////////
>-  L_SAVE_LDS:
>-
>-    //Only check the first wave need LDS
>-	/*      the first wave in the threadgroup    */
>-	s_barrier																		//FIXME  not performance-optimal "LDS is used? wait for other waves in the same TG" 
>-	s_and_b32		s_save_tmp, s_wave_size, S_SAVE_SPI_INIT_FIRST_WAVE_MASK								//exec is still used here
>-	s_cbranch_scc0	L_SAVE_SGPR
>-	
>-	s_mov_b32		exec_lo, 0xFFFFFFFF 											//need every thread from now on
>-    s_and_b32       m0, s_wave_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_cbranch_scc1  L_ENABLE_SAVE_LDS_EXEC_HI   
>-    s_mov_b32		exec_hi, 0x00000000
>-    s_branch        L_SAVE_LDS_NORMAL
>-  L_ENABLE_SAVE_LDS_EXEC_HI:
>-	s_mov_b32		exec_hi, 0xFFFFFFFF
>-  L_SAVE_LDS_NORMAL:	
>-	s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 			//lds_size
>-	s_and_b32		s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF				//lds_size is zero?
>-	s_cbranch_scc0	L_SAVE_SGPR														//no lds used? jump to L_SAVE_VGPR
>-	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 6 						//LDS size in dwords = lds_size * 64dw
>-	s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 2 						//LDS size in bytes
>-	s_mov_b32		s_save_buf_rsrc2,  s_save_alloc_size  							//NUM_RECORDS in bytes
>-	if (SWIZZLE_EN)
>-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
>-	else
>-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
>-	end
>-
>-    //load 0~63*4(byte address) to vgpr v15
>-    v_mbcnt_lo_u32_b32 v0, -1, 0
>-    v_mbcnt_hi_u32_b32 v0, -1, v0
>-    v_mul_u32_u24 v0, 4, v0
>-
>-    s_and_b32       m0, s_wave_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_mov_b32 		m0, 0x0
>-    s_cbranch_scc1  L_SAVE_LDS_LOOP_W64
>-
>-  L_SAVE_LDS_LOOP_W32:									
>-	if (SAVE_LDS)
>-    ds_read_b32 v1, v0
>-    s_waitcnt 0														    //ensure data ready
>-    buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>-	//buffer_store_lds_dword	s_save_buf_rsrc0, s_save_mem_offset lds:1               //save lds to memory doesn't exist in 10
>-	end
>-	s_add_u32		m0, m0, 128															//every buffer_store_lds does 128 bytes
>-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 128							//mem offset increased by 128 bytes
>-    v_add_nc_u32    v0, v0, 128
>-	s_cmp_lt_u32	m0, s_save_alloc_size												//scc=(m0 < s_save_alloc_size) ? 1 : 0
>-	s_cbranch_scc1  L_SAVE_LDS_LOOP_W32													//LDS save is complete?
>-    s_branch        L_SAVE_SGPR
>-
>-  L_SAVE_LDS_LOOP_W64:									
>-	if (SAVE_LDS)
>-    ds_read_b32 v1, v0
>-    s_waitcnt 0														    //ensure data ready
>-    buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>-	//buffer_store_lds_dword	s_save_buf_rsrc0, s_save_mem_offset lds:1               //save lds to memory doesn't exist in 10
>-	end
>-	s_add_u32		m0, m0, 256															//every buffer_store_lds does 256 bytes
>-	s_add_u32		s_save_mem_offset, s_save_mem_offset, 256							//mem offset increased by 256 bytes
>-    v_add_nc_u32    v0, v0, 256
>-	s_cmp_lt_u32	m0, s_save_alloc_size												//scc=(m0 < s_save_alloc_size) ? 1 : 0
>-	s_cbranch_scc1  L_SAVE_LDS_LOOP_W64													//LDS save is complete?
>-   
>-	
>-	/*      	save SGPRs	    */
>-	//////////////////////////////
>-	//s_getreg_b32 	s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) 				//spgr_size
>-	//s_add_u32 		s_save_alloc_size, s_save_alloc_size, 1
>-	//s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 4 						//Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value) 
>-	//s_lshl_b32 		s_save_alloc_size, s_save_alloc_size, 3 						//In gfx10, Number of SGPRs = (sgpr_size + 1) * 8   (non-zero value) 
>-  L_SAVE_SGPR:
>-    //need to look at it is wave32 or wave64
>-    s_and_b32       m0, s_wave_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_cbranch_scc1  L_SAVE_SGPR_VMEM_WAVE64
>-    if (SGPR_SAVE_USE_SQC)
>-		s_lshl_b32		s_save_buf_rsrc2,	s_sgpr_save_num, 2					//NUM_RECORDS in bytes
>-    else
>-        s_lshl_b32		s_save_buf_rsrc2,	s_sgpr_save_num, 7					//NUM_RECORDS in bytes (32 threads)
>-    end
>-    s_branch    L_SAVE_SGPR_CONT    
>-  L_SAVE_SGPR_VMEM_WAVE64:
>-	if (SGPR_SAVE_USE_SQC)
>-		s_lshl_b32		s_save_buf_rsrc2,	s_sgpr_save_num, 2					//NUM_RECORDS in bytes 
>-	else
>-		s_lshl_b32		s_save_buf_rsrc2,	s_sgpr_save_num, 8					//NUM_RECORDS in bytes (64 threads)
>-	end
>-  L_SAVE_SGPR_CONT:
>-	if (SWIZZLE_EN)
>-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
>-	else
>-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
>-	end
>-	
>-	//s_mov_b32 		m0, 0x0 														//SGPR initial index value =0		
>-    //s_nop           0x0                                                             //Manually inserted wait states
>-	
>-    s_and_b32       m0, s_wave_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    
>-    s_mov_b32 		m0, 0x0 														//SGPR initial index value =0		
>-    s_nop           0x0                                                             //Manually inserted wait states
>-
>-    s_cbranch_scc1  L_SAVE_SGPR_LOOP_WAVE64
>-
>-  L_SAVE_SGPR_LOOP_WAVE32: 										
>-	s_movrels_b32 	s0, s0 															//s0 = s[0+m0]
>-    //zhenxu, adding one more argument to save sgpr function, this is only for vmem, using sqc is not change    
>-	write_sgpr_to_mem_wave32(s0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)							//PV: the best performance should be using s_buffer_store_dwordx4
>-	s_add_u32		m0, m0, 1														//next sgpr index
>-	s_cmp_lt_u32 	m0, s_sgpr_save_num 											//scc = (m0 < s_sgpr_save_num) ? 1 : 0
>-	s_cbranch_scc1 	L_SAVE_SGPR_LOOP_WAVE32												//SGPR save is complete?
>-    s_branch    L_SAVE_HWREG
>-
>-  L_SAVE_SGPR_LOOP_WAVE64: 										
>-	s_movrels_b32 	s0, s0 															//s0 = s[0+m0]
>-    //zhenxu, adding one more argument to save sgpr function, this is only for vmem, using sqc is not change    
>-	write_sgpr_to_mem_wave64(s0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)							//PV: the best performance should be using s_buffer_store_dwordx4
>-	s_add_u32		m0, m0, 1														//next sgpr index
>-	s_cmp_lt_u32 	m0, s_sgpr_save_num 											//scc = (m0 < s_sgpr_save_num) ? 1 : 0
>-	s_cbranch_scc1 	L_SAVE_SGPR_LOOP_WAVE64												//SGPR save is complete?
>-
>-	
>-	/* 		save HW registers	*/
>-	//////////////////////////////
>-  L_SAVE_HWREG:
>-    s_mov_b32		s_save_buf_rsrc2, 0x4								//NUM_RECORDS	in bytes
>-	if (SWIZZLE_EN)
>-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
>-	else
>-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
>-	end
>-
>-    s_and_b32       m0, s_wave_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_cbranch_scc1  L_SAVE_HWREG_WAVE64
>-	
>-	write_sgpr_to_mem_wave32(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)					//M0
>-
>-	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME))      
>-		s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
>-		s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0			//carry bit over
>-	end
>-
>-	write_sgpr_to_mem_wave32(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)					//PC
>-	write_sgpr_to_mem_wave32(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
>-	write_sgpr_to_mem_wave32(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//EXEC
>-	write_sgpr_to_mem_wave32(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
>-	write_sgpr_to_mem_wave32(s_save_status, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//STATUS 
>-	
>-	//s_save_trapsts conflicts with s_save_alloc_size
>-	s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
>-	write_sgpr_to_mem_wave32(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//TRAPSTS
>-	
>-	//write_sgpr_to_mem_wave32(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)			//XNACK_MASK_LO
>-	write_sgpr_to_mem_wave32(s_save_xnack_mask, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)			//XNACK_MASK_HI
>-	
>-	//use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2
>-	s_getreg_b32 	s_save_m0, hwreg(HW_REG_MODE)																						//MODE
>-	write_sgpr_to_mem_wave32(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
>-    if(SAVE_RESTORE_HWID_DDID)
>-    s_getreg_b32 	s_save_m0, hwreg(HW_REG_HW_ID1)																						//HW_ID1, handler records the SE/SA/WGP/SIMD/wave of the original wave
>-    write_sgpr_to_mem_wave32(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
>-    end
>-    s_branch   L_S_PGM_END_SAVED
>-
>-  L_SAVE_HWREG_WAVE64:
>-    write_sgpr_to_mem_wave64(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)					//M0
>-
>-	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME))      
>-		s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
>-		s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0			//carry bit over
>-	end
>-
>-	write_sgpr_to_mem_wave64(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)					//PC
>-	write_sgpr_to_mem_wave64(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
>-	write_sgpr_to_mem_wave64(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//EXEC
>-	write_sgpr_to_mem_wave64(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
>-	write_sgpr_to_mem_wave64(s_save_status, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//STATUS 
>-	
>-	//s_save_trapsts conflicts with s_save_alloc_size
>-	s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
>-	write_sgpr_to_mem_wave64(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)				//TRAPSTS
>-	
>-	//write_sgpr_to_mem_wave64(s_save_xnack_mask_lo, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)			//XNACK_MASK_LO
>-	write_sgpr_to_mem_wave64(s_save_xnack_mask, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)			//XNACK_MASK_HI
>-	
>-	//use s_save_tmp would introduce conflict here between s_save_tmp and s_save_buf_rsrc2
>-	s_getreg_b32 	s_save_m0, hwreg(HW_REG_MODE)																						//MODE
>-	write_sgpr_to_mem_wave64(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
>-
>-
>-    if(SAVE_RESTORE_HWID_DDID)
>-    s_getreg_b32 	s_save_m0, hwreg(HW_REG_HW_ID1)																						//HW_ID1, handler records the SE/SA/WGP/SIMD/wave of the original wave
>-    write_sgpr_to_mem_wave64(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF)
>-
>-	/* 		save DDID	*/
>-	//////////////////////////////
>-  L_SAVE_DDID:
>-    //EXEC has been saved, no vector inst following
>-    s_mov_b32	exec_lo, 0x80000000    //Set MSB to 1. Cleared when draw index is returned
>-    s_sendmsg sendmsg(MSG_GET_DDID)
>-
>-  L_WAIT_DDID_LOOP:    
>-    s_nop		7			// sleep a bit
>-    s_bitcmp0_b32 exec_lo, 31	// test to see if MSB is cleared, meaning done
>-    s_cbranch_scc0	L_WAIT_DDID_LOOP
>-
>-    s_mov_b32	s_save_m0, exec_lo
>-
>-
>-    s_mov_b32		s_save_buf_rsrc2, 0x4								//NUM_RECORDS	in bytes
>-	if (SWIZZLE_EN)
>-		s_add_u32		s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
>-	else
>-		s_mov_b32		s_save_buf_rsrc2,  0x1000000								//NUM_RECORDS in bytes
>-	end
>-    s_and_b32       m0, s_wave_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_cbranch_scc1  L_SAVE_DDID_WAVE64
>-
>-    write_sgpr_to_mem_wave32(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) 
>-
>-  L_SAVE_DDID_WAVE64:
>-    write_sgpr_to_mem_wave64(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset, SGPR_SAVE_USE_SQC, USE_MTBUF_INSTEAD_OF_MUBUF) 
>-
>-    end
>-   
>-  L_S_PGM_END_SAVED:
>-	/*     S_PGM_END_SAVED  */    							//FIXME  graphics ONLY
>-	if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT))	
>-		s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
>-		s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
>-		s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0			//carry bit over
>-		s_rfe_b64 s_save_pc_lo                              //Return to the main shader program
>-	else
>-	end
>-
>-	
>-    s_branch	L_END_PGM
>-	
>-
>-				
>-/**************************************************************************/
>-/*                     	restore routine						              */
>-/**************************************************************************/
>+
>+	/* inform SPI the readiness and wait for SPI's go signal */
>+	s_mov_b32	s_save_exec_lo, exec_lo					//save EXEC and use EXEC for the go signal from SPI
>+	s_mov_b32	s_save_exec_hi, exec_hi
>+	s_mov_b64	exec, 0x0						//clear EXEC to get ready to receive
>+
>+	s_sendmsg	sendmsg(MSG_SAVEWAVE)					//send SPI a message and wait for SPI's write to EXEC
>+
>+L_SLEEP:
>+	// sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause
>+	// SQ hang, since the 7,8th wave could not get arbit to exec inst, while
>+	// other waves are stuck into the sleep-loop and waiting for wrexec!=0
>+	s_sleep		0x2
>+	s_cbranch_execz	L_SLEEP
>+
>+	/* setup Resource Contants */
>+	s_mov_b32	s_save_buf_rsrc0, s_save_spi_init_lo			//base_addr_lo
>+	s_and_b32	s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF	//base_addr_hi
>+	s_or_b32	s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE
>+	s_mov_b32	s_save_buf_rsrc2, 0					//NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited
>+	s_mov_b32	s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC
>+	s_and_b32	s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_ATC_MASK
>+	s_lshr_b32	s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)
>+	s_or_b32	s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp		//or ATC
>+	s_and_b32	s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_MTYPE_MASK
>+	s_lshr_b32	s_save_tmp, s_save_tmp, (S_SAVE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)
>+	s_or_b32	s_save_buf_rsrc3, s_save_buf_rsrc3, s_save_tmp		//or MTYPE
>+
>+	s_mov_b32	s_save_m0, m0
>+
>+	/* global mem offset */
>+	s_mov_b32	s_save_mem_offset, 0x0
>+	s_getreg_b32	s_wave_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE)
>+	s_lshl_b32	s_wave_size, s_wave_size, S_WAVE_SIZE
>+	s_or_b32	s_wave_size, s_save_spi_init_hi, s_wave_size		//share s_wave_size with exec_hi, it's at bit25
>+
>+	/* save HW registers */
>+
>+L_SAVE_HWREG:
>+	// HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)
>+	get_vgpr_size_bytes(s_save_mem_offset, s_wave_size)
>+	get_svgpr_size_bytes(s_save_tmp)
>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, s_save_tmp
>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes()
>+
>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
>+
>+	write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
>+	write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset)
>+	write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset)
>+	write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset)
>+	write_hwreg_to_mem(s_save_exec_hi, s_save_buf_rsrc0, s_save_mem_offset)
>+	write_hwreg_to_mem(s_save_status, s_save_buf_rsrc0, s_save_mem_offset)
>+
>+	s_getreg_b32	s_save_trapsts, hwreg(HW_REG_TRAPSTS)
>+	write_hwreg_to_mem(s_save_trapsts, s_save_buf_rsrc0, s_save_mem_offset)
>+	write_hwreg_to_mem(s_save_xnack_mask, s_save_buf_rsrc0, s_save_mem_offset)
>+
>+	s_getreg_b32	s_save_m0, hwreg(HW_REG_MODE)
>+	write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
>+
>+	s_getreg_b32	s_save_m0, hwreg(HW_REG_SHADER_FLAT_SCRATCH_LO)
>+	write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
>+
>+	s_getreg_b32	s_save_m0, hwreg(HW_REG_SHADER_FLAT_SCRATCH_HI)
>+	write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)
>+
>+	/* the first wave in the threadgroup */
>+	s_and_b32	s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK
>+	s_mov_b32	s_save_exec_hi, 0x0
>+	s_or_b32	s_save_exec_hi, s_save_tmp, s_save_exec_hi		// save first wave bit to s_save_exec_hi.bits[26]
>+
>+	/* save SGPRs */
>+	// Save SGPR before LDS save, then the s0 to s4 can be used during LDS save...
>+
>+	// SGPR SR memory offset : size(VGPR)+size(SVGPR)
>+	get_vgpr_size_bytes(s_save_mem_offset, s_wave_size)
>+	get_svgpr_size_bytes(s_save_tmp)
>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, s_save_tmp
>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
>+
>+	// backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0
>+	s_mov_b32	s_save_xnack_mask, s_save_buf_rsrc0
>+	s_add_u32	s_save_buf_rsrc0, s_save_buf_rsrc0, s_save_mem_offset
>+	s_addc_u32	s_save_buf_rsrc1, s_save_buf_rsrc1, 0
>+
>+	s_mov_b32	m0, 0x0							//SGPR initial index value =0
>+	s_nop		0x0							//Manually inserted wait states
>+L_SAVE_SGPR_LOOP:
>+	// SGPR is allocated in 16 SGPR granularity
>+	s_movrels_b64	s0, s0							//s0 = s[0+m0], s1 = s[1+m0]
>+	s_movrels_b64	s2, s2							//s2 = s[2+m0], s3 = s[3+m0]
>+	s_movrels_b64	s4, s4							//s4 = s[4+m0], s5 = s[5+m0]
>+	s_movrels_b64	s6, s6							//s6 = s[6+m0], s7 = s[7+m0]
>+	s_movrels_b64	s8, s8							//s8 = s[8+m0], s9 = s[9+m0]
>+	s_movrels_b64	s10, s10						//s10 = s[10+m0], s11 = s[11+m0]
>+	s_movrels_b64	s12, s12						//s12 = s[12+m0], s13 = s[13+m0]
>+	s_movrels_b64	s14, s14						//s14 = s[14+m0], s15 = s[15+m0]
>+
>+	write_16sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset)
>+	s_add_u32	m0, m0, 16						//next sgpr index
>+	s_cmp_lt_u32	m0, 96							//scc = (m0 < first 96 SGPR) ? 1 : 0
>+	s_cbranch_scc1	L_SAVE_SGPR_LOOP					//first 96 SGPR save is complete?
>+
>+	//save the rest 12 SGPR
>+	s_movrels_b64	s0, s0							//s0 = s[0+m0], s1 = s[1+m0]
>+	s_movrels_b64	s2, s2							//s2 = s[2+m0], s3 = s[3+m0]
>+	s_movrels_b64	s4, s4							//s4 = s[4+m0], s5 = s[5+m0]
>+	s_movrels_b64	s6, s6							//s6 = s[6+m0], s7 = s[7+m0]
>+	s_movrels_b64	s8, s8							//s8 = s[8+m0], s9 = s[9+m0]
>+	s_movrels_b64	s10, s10						//s10 = s[10+m0], s11 = s[11+m0]
>+	write_12sgpr_to_mem(s0, s_save_buf_rsrc0, s_save_mem_offset)
>+
>+	// restore s_save_buf_rsrc0,1
>+	s_mov_b32	s_save_buf_rsrc0, s_save_xnack_mask
>+
>+	/* save first 4 VGPR, then LDS save could use   */
>+	// each wave will alloc 4 vgprs at least...
>+
>+	s_mov_b32	s_save_mem_offset, 0
>+ 	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on
>+	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE
>+	s_and_b32	m0, m0, 1
>+	s_cmp_eq_u32	m0, 1
>+	s_cbranch_scc1	L_ENABLE_SAVE_4VGPR_EXEC_HI
>+	s_mov_b32	exec_hi, 0x00000000
>+	s_branch	L_SAVE_4VGPR_WAVE32
>+L_ENABLE_SAVE_4VGPR_EXEC_HI:
>+	s_mov_b32	exec_hi, 0xFFFFFFFF
>+	s_branch	L_SAVE_4VGPR_WAVE64
>+L_SAVE_4VGPR_WAVE32:
>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
>+
>+	// VGPR Allocated in 4-GPR granularity
>+
>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128
>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2
>+	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3
>+	s_branch	L_SAVE_LDS
>+
>+L_SAVE_4VGPR_WAVE64:
>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
>+
>+	// VGPR Allocated in 4-GPR granularity
>+
>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
>+	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
>+
>+	/* save LDS */
>+
>+L_SAVE_LDS:
>+	// Change EXEC to all threads...
>+	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on
>+	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE
>+	s_and_b32	m0, m0, 1
>+	s_cmp_eq_u32	m0, 1
>+	s_cbranch_scc1	L_ENABLE_SAVE_LDS_EXEC_HI
>+	s_mov_b32	exec_hi, 0x00000000
>+	s_branch	L_SAVE_LDS_NORMAL
>+L_ENABLE_SAVE_LDS_EXEC_HI:
>+	s_mov_b32	exec_hi, 0xFFFFFFFF
>+L_SAVE_LDS_NORMAL:
>+	s_getreg_b32	s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)
>+	s_and_b32	s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF	//lds_size is zero?
>+	s_cbranch_scc0	L_SAVE_LDS_DONE						//no lds used? jump to L_SAVE_DONE
>+
>+	s_barrier								//LDS is used? wait for other waves in the same TG
>+	s_and_b32	s_save_tmp, s_save_exec_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK
>+	s_cbranch_scc0	L_SAVE_LDS_DONE
>+
>+	// first wave do LDS save;
>+
>+	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, 6			//LDS size in dwords = lds_size * 64dw
>+	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, 2			//LDS size in bytes
>+	s_mov_b32	s_save_buf_rsrc2, s_save_alloc_size			//NUM_RECORDS in bytes
>+
>+	// LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG)
>+	//
>+	get_vgpr_size_bytes(s_save_mem_offset, s_wave_size)
>+	get_svgpr_size_bytes(s_save_tmp)
>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, s_save_tmp
>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes()
>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes()
>+
>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
>+
>+	//load 0~63*4(byte address) to vgpr v0
>+	v_mbcnt_lo_u32_b32	v0, -1, 0
>+	v_mbcnt_hi_u32_b32	v0, -1, v0
>+	v_mul_u32_u24	v0, 4, v0
>+
>+	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE
>+	s_and_b32	m0, m0, 1
>+	s_cmp_eq_u32	m0, 1
>+	s_mov_b32	m0, 0x0
>+	s_cbranch_scc1	L_SAVE_LDS_W64
>+
>+L_SAVE_LDS_W32:
>+	s_mov_b32	s3, 128
>+	s_nop		0
>+	s_nop		0
>+	s_nop		0
>+L_SAVE_LDS_LOOP_W32:
>+	ds_read_b32	v1, v0
>+	s_waitcnt	0
>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>+
>+	s_add_u32	m0, m0, s3						//every buffer_store_lds does 256 bytes
>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, s3
>+	v_add_nc_u32	v0, v0, 128						//mem offset increased by 128 bytes
>+	s_cmp_lt_u32	m0, s_save_alloc_size					//scc=(m0 < s_save_alloc_size) ? 1 : 0
>+	s_cbranch_scc1	L_SAVE_LDS_LOOP_W32					//LDS save is complete?
>+
>+	s_branch	L_SAVE_LDS_DONE
>+
>+L_SAVE_LDS_W64:
>+	s_mov_b32	s3, 256
>+	s_nop		0
>+	s_nop		0
>+	s_nop		0
>+L_SAVE_LDS_LOOP_W64:
>+	ds_read_b32	v1, v0
>+	s_waitcnt	0
>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>+
>+	s_add_u32	m0, m0, s3						//every buffer_store_lds does 256 bytes
>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, s3
>+	v_add_nc_u32	v0, v0, 256						//mem offset increased by 256 bytes
>+	s_cmp_lt_u32	m0, s_save_alloc_size					//scc=(m0 < s_save_alloc_size) ? 1 : 0
>+	s_cbranch_scc1	L_SAVE_LDS_LOOP_W64					//LDS save is complete?
>+
>+L_SAVE_LDS_DONE:
>+	/* save VGPRs  - set the Rest VGPRs */
>+L_SAVE_VGPR:
>+	// VGPR SR memory offset: 0
>+	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on
>+	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE
>+	s_and_b32	m0, m0, 1
>+	s_cmp_eq_u32	m0, 1
>+	s_cbranch_scc1	L_ENABLE_SAVE_VGPR_EXEC_HI
>+	s_mov_b32	s_save_mem_offset, (0+128*4)				// for the rest VGPRs
>+	s_mov_b32	exec_hi, 0x00000000
>+	s_branch	L_SAVE_VGPR_NORMAL
>+L_ENABLE_SAVE_VGPR_EXEC_HI:
>+	s_mov_b32	s_save_mem_offset, (0+256*4)				// for the rest VGPRs
>+	s_mov_b32	exec_hi, 0xFFFFFFFF
>+L_SAVE_VGPR_NORMAL:
>+	s_getreg_b32	s_save_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)
>+	s_add_u32	s_save_alloc_size, s_save_alloc_size, 1
>+	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, 2			//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
>+	//determine it is wave32 or wave64
>+	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE
>+	s_and_b32	m0, m0, 1
>+	s_cmp_eq_u32	m0, 1
>+	s_cbranch_scc1	L_SAVE_VGPR_WAVE64
>+
>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
>+
>+	// VGPR Allocated in 4-GPR granularity
>+
>+	// VGPR store using dw burst
>+	s_mov_b32	m0, 0x4							//VGPR initial index value =4
>+	s_cmp_lt_u32	m0, s_save_alloc_size
>+	s_cbranch_scc0	L_SAVE_VGPR_END
>+
>+L_SAVE_VGPR_W32_LOOP:
>+	v_movrels_b32	v0, v0							//v0 = v[0+m0]
>+	v_movrels_b32	v1, v1							//v1 = v[1+m0]
>+	v_movrels_b32	v2, v2							//v2 = v[2+m0]
>+	v_movrels_b32	v3, v3							//v3 = v[3+m0]
>+
>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128
>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2
>+	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3
>+
>+	s_add_u32	m0, m0, 4						//next vgpr index
>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, 128*4		//every buffer_store_dword does 128 bytes
>+	s_cmp_lt_u32	m0, s_save_alloc_size					//scc = (m0 < s_save_alloc_size) ? 1 : 0
>+	s_cbranch_scc1	L_SAVE_VGPR_W32_LOOP					//VGPR save is complete?
>+
>+	s_branch	L_SAVE_VGPR_END
>+
>+L_SAVE_VGPR_WAVE64:
>+	s_mov_b32	s_save_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
>+
>+	// VGPR store using dw burst
>+	s_mov_b32	m0, 0x4							//VGPR initial index value =4
>+	s_cmp_lt_u32	m0, s_save_alloc_size
>+	s_cbranch_scc0	L_SAVE_VGPR_END
>+
>+L_SAVE_VGPR_W64_LOOP:
>+	v_movrels_b32	v0, v0							//v0 = v[0+m0]
>+	v_movrels_b32	v1, v1							//v1 = v[1+m0]
>+	v_movrels_b32	v2, v2							//v2 = v[2+m0]
>+	v_movrels_b32	v3, v3							//v3 = v[3+m0]
>+
>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>+	buffer_store_dword	v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
>+	buffer_store_dword	v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
>+	buffer_store_dword	v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
>+
>+	s_add_u32	m0, m0, 4						//next vgpr index
>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, 256*4		//every buffer_store_dword does 256 bytes
>+	s_cmp_lt_u32	m0, s_save_alloc_size					//scc = (m0 < s_save_alloc_size) ? 1 : 0
>+	s_cbranch_scc1	L_SAVE_VGPR_W64_LOOP					//VGPR save is complete?
>+
>+	//Below part will be the save shared vgpr part (new for gfx10)
>+	s_getreg_b32	s_save_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE)
>+	s_and_b32	s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF	//shared_vgpr_size is zero?
>+	s_cbranch_scc0	L_SAVE_VGPR_END						//no shared_vgpr used? jump to L_SAVE_LDS
>+	s_lshl_b32	s_save_alloc_size, s_save_alloc_size, 3			//Number of SHARED_VGPRs = shared_vgpr_size * 8    (non-zero value)
>+	//m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count.
>+	//save shared_vgpr will start from the index of m0
>+	s_add_u32	s_save_alloc_size, s_save_alloc_size, m0
>+	s_mov_b32	exec_lo, 0xFFFFFFFF
>+	s_mov_b32	exec_hi, 0x00000000
>+L_SAVE_SHARED_VGPR_WAVE64_LOOP:
>+	v_movrels_b32	v0, v0							//v0 = v[0+m0]
>+	buffer_store_dword	v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>+	s_add_u32	m0, m0, 1						//next vgpr index
>+	s_add_u32	s_save_mem_offset, s_save_mem_offset, 128
>+	s_cmp_lt_u32	m0, s_save_alloc_size					//scc = (m0 < s_save_alloc_size) ? 1 : 0
>+	s_cbranch_scc1	L_SAVE_SHARED_VGPR_WAVE64_LOOP				//SHARED_VGPR save is complete?
>+
>+L_SAVE_VGPR_END:
>+	s_branch	L_END_PGM
> 
> L_RESTORE:
>-    /*      Setup Resource Contants    */
>-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
>-		//calculate wd_addr using absolute thread id
>-		v_readlane_b32 s_restore_tmp, v9, 0
>-        //determine it is wave32 or wave64
>-        s_getreg_b32 	s_restore_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE) //change to ttmp13
>-        s_cmp_eq_u32    s_restore_size, 0
>-        s_cbranch_scc1  L_RESTORE_WAVE32
>-        s_lshr_b32 s_restore_tmp, s_restore_tmp, 6 //SAVE WAVE64
>-        s_branch    L_RESTORE_CON
>-    L_RESTORE_WAVE32:
>-        s_lshr_b32 s_restore_tmp, s_restore_tmp, 5 //SAVE WAVE32
>-    L_RESTORE_CON:
>-		s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE
>-		s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO
>-		s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI
>-		s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL	
>-	else
>-	end
>-	
>-    s_mov_b32		s_restore_buf_rsrc0, 	s_restore_spi_init_lo															//base_addr_lo
>-	s_and_b32		s_restore_buf_rsrc1, 	s_restore_spi_init_hi, 0x0000FFFF												//base_addr_hi
>-	s_or_b32		s_restore_buf_rsrc1, 	s_restore_buf_rsrc1,  S_RESTORE_BUF_RSRC_WORD1_STRIDE
>-    s_mov_b32       s_restore_buf_rsrc2,   	0                                               								//NUM_RECORDS initial value = 0 (in bytes)
>-	s_mov_b32		s_restore_buf_rsrc3, 	S_RESTORE_BUF_RSRC_WORD3_MISC
>-	s_and_b32		s_restore_tmp,         	s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK		
>-	s_lshr_b32		s_restore_tmp,  		s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)		//get ATC bit into position
>-	s_or_b32		s_restore_buf_rsrc3, 	s_restore_buf_rsrc3,  s_restore_tmp												//or ATC
>-	s_and_b32		s_restore_tmp,         	s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK		
>-	s_lshr_b32		s_restore_tmp,  		s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)	//get MTYPE bits into position
>-	s_or_b32		s_restore_buf_rsrc3, 	s_restore_buf_rsrc3,  s_restore_tmp												//or MTYPE
>-    //determine it is wave32 or wave64
>-    s_getreg_b32 	s_restore_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE)
>-    s_or_b32        s_restore_size, s_restore_spi_init_hi,    s_restore_size                                             //share s_wave_size with exec_hi
>-	
>-	/* 		global mem offset			*/
>-	s_mov_b32		s_restore_mem_offset, 0x0								//mem offset initial value = 0
>-
>-        /*      	restore VGPRs	    */
>-	//////////////////////////////
>-  L_RESTORE_VGPR:
>-  
>- 	s_mov_b32		exec_lo, 0xFFFFFFFF 													//need every thread from now on   //be consistent with SAVE although can be moved ahead
>-    s_and_b32       m0, s_restore_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_cbranch_scc1  L_ENABLE_RESTORE_VGPR_EXEC_HI   
>-    s_mov_b32		exec_hi, 0x00000000
>-    s_branch        L_RESTORE_VGPR_NORMAL
>-  L_ENABLE_RESTORE_VGPR_EXEC_HI:
>-	s_mov_b32		exec_hi, 0xFFFFFFFF
>-  L_RESTORE_VGPR_NORMAL:	
>-	s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE) 	//vpgr_size
>-	s_add_u32 		s_restore_alloc_size, s_restore_alloc_size, 1
>-	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 2 							//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
>-    //determine it is wave32 or wave64
>-    s_and_b32       m0, s_restore_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_cbranch_scc1  L_RESTORE_VGPR_WAVE64
>-
>-    s_lshl_b32		s_restore_buf_rsrc2,  s_restore_alloc_size, 7						    //NUM_RECORDS in bytes (32 threads*4)
>-	if (SWIZZLE_EN)
>-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
>-	else
>-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
>-	end	
>-
>-	s_mov_b32		s_restore_mem_offset_save, s_restore_mem_offset							// restore start with v1, v0 will be the last
>-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 128
>-    s_mov_b32 		m0, 1 																	//VGPR initial index value = 1
>-	//s_set_gpr_idx_on  m0, 0x8																//M0[7:0] = M0[7:0] and M0[15:12] = 0x8
>-    //s_add_u32		s_restore_alloc_size, s_restore_alloc_size, 0x8000						//add 0x8000 since we compare m0 against it later, might not need this in gfx10	
>-
>-  L_RESTORE_VGPR_WAVE32_LOOP: 										
>-    if(USE_MTBUF_INSTEAD_OF_MUBUF)       
>-		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-    else
>-		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset	slc:1 glc:1	
>-	end
>-	s_waitcnt		vmcnt(0)																//ensure data ready
>-	v_movreld_b32		v0, v0																	//v[0+m0] = v0
>-    s_add_u32		m0, m0, 1																//next vgpr index
>-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 128							//every buffer_load_dword does 128 bytes
>-	s_cmp_lt_u32 	m0,	s_restore_alloc_size 												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
>-	s_cbranch_scc1 	L_RESTORE_VGPR_WAVE32_LOOP														//VGPR restore (except v0) is complete?
>-	//s_set_gpr_idx_off
>-																							/* VGPR restore on v0 */
>-    if(USE_MTBUF_INSTEAD_OF_MUBUF)       
>-		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-    else
>-		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save	slc:1 glc:1	
>-	end
>-
>-    s_branch    L_RESTORE_LDS
>-
>-  L_RESTORE_VGPR_WAVE64:
>-    s_lshl_b32		s_restore_buf_rsrc2,  s_restore_alloc_size, 8						    //NUM_RECORDS in bytes (64 threads*4)
>-	if (SWIZZLE_EN)
>-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
>-	else
>-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
>-	end	
>-
>-	s_mov_b32		s_restore_mem_offset_save, s_restore_mem_offset							// restore start with v1, v0 will be the last
>-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256
>-    s_mov_b32 		m0, 1 																	//VGPR initial index value = 1
>-  L_RESTORE_VGPR_WAVE64_LOOP: 										
>-    if(USE_MTBUF_INSTEAD_OF_MUBUF)       
>-		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-    else
>-		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset	slc:1 glc:1	
>-	end
>-	s_waitcnt		vmcnt(0)																//ensure data ready
>-	v_movreld_b32		v0, v0																	//v[0+m0] = v0
>-    s_add_u32		m0, m0, 1																//next vgpr index
>-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256							//every buffer_load_dword does 256 bytes
>-	s_cmp_lt_u32 	m0,	s_restore_alloc_size 												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
>-	s_cbranch_scc1 	L_RESTORE_VGPR_WAVE64_LOOP														//VGPR restore (except v0) is complete?
>-	//s_set_gpr_idx_off
>-    //
>-    //Below part will be the restore shared vgpr part (new for gfx10)
>-    s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) 			//shared_vgpr_size
>-    s_and_b32		s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF				//shared_vgpr_size is zero?
>-    s_cbranch_scc0	L_RESTORE_V0													    //no shared_vgpr used? jump to L_SAVE_LDS
>-    s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 3 						//Number of SHARED_VGPRs = shared_vgpr_size * 8    (non-zero value)
>-    //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count.
>-    //restore shared_vgpr will start from the index of m0
>-    s_add_u32       s_restore_alloc_size, s_restore_alloc_size, m0
>-    s_mov_b32		exec_lo, 0xFFFFFFFF
>-    s_mov_b32		exec_hi, 0x00000000
>-    L_RESTORE_SHARED_VGPR_WAVE64_LOOP: 
>-    buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset	slc:1 glc:1
>-    s_waitcnt		vmcnt(0)																//ensure data ready
>-	v_movreld_b32		v0, v0																	//v[0+m0] = v0
>-    s_add_u32		m0, m0, 1																//next vgpr index
>-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 128							//every buffer_load_dword does 256 bytes
>-	s_cmp_lt_u32 	m0,	s_restore_alloc_size 												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
>-	s_cbranch_scc1 	L_RESTORE_SHARED_VGPR_WAVE64_LOOP														//VGPR restore (except v0) is complete?
>-
>-    s_mov_b32 exec_hi, 0xFFFFFFFF                                                           //restore back exec_hi before restoring V0!!
>-	
>-    /* VGPR restore on v0 */
>-  L_RESTORE_V0:
>-    if(USE_MTBUF_INSTEAD_OF_MUBUF)       
>-		tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-    else
>-		buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save	slc:1 glc:1	
>-	end
>-
>-
>-    /*      	restore LDS	    */
>-	//////////////////////////////
>-  L_RESTORE_LDS:
>-
>-    //Only need to check the first wave    
>-	/*      the first wave in the threadgroup    */
>-	s_and_b32		s_restore_tmp, s_restore_size, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK			
>-	s_cbranch_scc0	L_RESTORE_SGPR
>-	
>-    s_mov_b32		exec_lo, 0xFFFFFFFF 													//need every thread from now on   //be consistent with SAVE although can be moved ahead
>-    s_and_b32       m0, s_restore_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_cbranch_scc1  L_ENABLE_RESTORE_LDS_EXEC_HI   
>-    s_mov_b32		exec_hi, 0x00000000
>-    s_branch        L_RESTORE_LDS_NORMAL
>-  L_ENABLE_RESTORE_LDS_EXEC_HI:
>-	s_mov_b32		exec_hi, 0xFFFFFFFF
>-  L_RESTORE_LDS_NORMAL:	
>-	s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE) 				//lds_size
>-	s_and_b32		s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF					//lds_size is zero?
>-	s_cbranch_scc0	L_RESTORE_SGPR															//no lds used? jump to L_RESTORE_VGPR
>-	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 6 							//LDS size in dwords = lds_size * 64dw
>-	s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 2 							//LDS size in bytes
>-	s_mov_b32		s_restore_buf_rsrc2,	s_restore_alloc_size							//NUM_RECORDS in bytes
>-	if (SWIZZLE_EN)
>-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
>-	else
>-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
>-	end
>-
>-    s_and_b32       m0, s_wave_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_mov_b32 		m0, 0x0
>-    s_cbranch_scc1  L_RESTORE_LDS_LOOP_W64
>-
>-  L_RESTORE_LDS_LOOP_W32:									
>-	if (SAVE_LDS)
>-	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1
>-    s_waitcnt 0
>-	end
>-    s_add_u32		m0, m0, 128																//every buffer_load_dword does 256 bytes
>-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 128						//mem offset increased by 256 bytes
>-	s_cmp_lt_u32	m0, s_restore_alloc_size												//scc=(m0 < s_restore_alloc_size) ? 1 : 0
>-	s_cbranch_scc1  L_RESTORE_LDS_LOOP_W32														//LDS restore is complete?
>-    s_branch        L_RESTORE_SGPR
>-
>-  L_RESTORE_LDS_LOOP_W64:									
>-	if (SAVE_LDS)
>-	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1
>-    s_waitcnt 0
>-	end
>-    s_add_u32		m0, m0, 256																//every buffer_load_dword does 256 bytes
>-	s_add_u32		s_restore_mem_offset, s_restore_mem_offset, 256							//mem offset increased by 256 bytes
>-	s_cmp_lt_u32	m0, s_restore_alloc_size												//scc=(m0 < s_restore_alloc_size) ? 1 : 0
>-	s_cbranch_scc1  L_RESTORE_LDS_LOOP_W64														//LDS restore is complete?
>-
>-	
>-    /*      	restore SGPRs	    */
>-	//////////////////////////////
>-	//s_getreg_b32 	s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE) 				//spgr_size
>-	//s_add_u32 		s_restore_alloc_size, s_restore_alloc_size, 1
>-	//s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 4 							//Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
>-	//s_lshl_b32 		s_restore_alloc_size, s_restore_alloc_size, 3 							//Number of SGPRs = (sgpr_size + 1) * 8   (non-zero value)
>-  L_RESTORE_SGPR:
>-    //need to look at it is wave32 or wave64
>-    s_and_b32       m0, s_restore_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_cbranch_scc1  L_RESTORE_SGPR_VMEM_WAVE64
>-	if (SGPR_SAVE_USE_SQC)
>-		s_lshl_b32		s_restore_buf_rsrc2,	s_sgpr_save_num, 2						//NUM_RECORDS in bytes 
>-	else
>-        s_lshl_b32		s_restore_buf_rsrc2,	s_sgpr_save_num, 7						//NUM_RECORDS in bytes (32 threads)
>-    end
>-    s_branch        L_RESTORE_SGPR_CONT
>-  L_RESTORE_SGPR_VMEM_WAVE64:
>-    if (SGPR_SAVE_USE_SQC)
>-		s_lshl_b32		s_restore_buf_rsrc2,	s_sgpr_save_num, 2						//NUM_RECORDS in bytes 
>-	else
>-		s_lshl_b32		s_restore_buf_rsrc2,	s_sgpr_save_num, 8						//NUM_RECORDS in bytes (64 threads)
>-	end
>-
>-  L_RESTORE_SGPR_CONT:
>-	if (SWIZZLE_EN)
>-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
>-	else
>-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
>-	end
>-
>-    s_and_b32       m0, s_restore_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_cbranch_scc1  L_RESTORE_SGPR_WAVE64
>-
>-    read_sgpr_from_mem_wave32(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)		//save s0 to s_restore_tmp
>-	s_mov_b32 		m0, 0x1
>-
>-  L_RESTORE_SGPR_LOOP_WAVE32:
>-    read_sgpr_from_mem_wave32(s0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)															//PV: further performance improvement can be made
>-	s_waitcnt		lgkmcnt(0)																//ensure data ready
>-	s_movreld_b32 	s0, s0                                                                  //s[0+m0] = s0
>-    s_nop 0                                                                                 // hazard SALU M0=> S_MOVREL
>-	s_add_u32		m0, m0, 1																//next sgpr index
>-	s_cmp_lt_u32 	m0, s_sgpr_save_num												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
>-	s_cbranch_scc1 	L_RESTORE_SGPR_LOOP_WAVE32														//SGPR restore (except s0) is complete?
>-	s_mov_b32		s0, s_restore_tmp															/* SGPR restore on s0 */
>-    s_branch        L_RESTORE_HWREG
>-  
>-  L_RESTORE_SGPR_WAVE64:
>-	read_sgpr_from_mem_wave64(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)		//save s0 to s_restore_tmp
>-	s_mov_b32 		m0, 0x1																				//SGPR initial index value =1	//go on with with s1
>-	
>-  L_RESTORE_SGPR_LOOP_WAVE64: 																					
>-	read_sgpr_from_mem_wave64(s0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)															//PV: further performance improvement can be made
>-	s_waitcnt		lgkmcnt(0)																//ensure data ready
>-	s_movreld_b32 	s0, s0                                                                  //s[0+m0] = s0
>-    s_nop 0                                                                                 // hazard SALU M0=> S_MOVREL
>-	s_add_u32		m0, m0, 1																//next sgpr index
>-	s_cmp_lt_u32 	m0, s_sgpr_save_num												//scc = (m0 < s_restore_alloc_size) ? 1 : 0
>-	s_cbranch_scc1 	L_RESTORE_SGPR_LOOP_WAVE64														//SGPR restore (except s0) is complete?
>-	s_mov_b32		s0, s_restore_tmp															/* SGPR restore on s0 */
>-
>-	
>-    /* 		restore HW registers	*/
>-	//////////////////////////////
>-  L_RESTORE_HWREG:
>-    s_mov_b32		s_restore_buf_rsrc2, 0x4												//NUM_RECORDS	in bytes
>-	if (SWIZZLE_EN)
>-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
>-	else
>-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
>-	end
>-
>-    s_and_b32       m0, s_restore_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_cbranch_scc1  L_RESTORE_HWREG_WAVE64
>-
>-    read_sgpr_from_mem_wave32(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//M0
>-	read_sgpr_from_mem_wave32(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//PC
>-	read_sgpr_from_mem_wave32(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)
>-	read_sgpr_from_mem_wave32(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//EXEC
>-	read_sgpr_from_mem_wave32(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)
>-	read_sgpr_from_mem_wave32(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//STATUS
>-	read_sgpr_from_mem_wave32(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//TRAPSTS
>-    //read_sgpr_from_mem_wave32(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK_LO
>-	//read_sgpr_from_mem_wave32(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK_HI
>-    read_sgpr_from_mem_wave32(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK
>-	read_sgpr_from_mem_wave32(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//MODE
>-    if(SAVE_RESTORE_HWID_DDID)
>-    read_sgpr_from_mem_wave32(s_restore_hwid1, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//HW_ID1
>-    end
>-    s_branch        L_RESTORE_HWREG_FINISH
>-
>-  L_RESTORE_HWREG_WAVE64:
>-	read_sgpr_from_mem_wave64(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//M0
>-	read_sgpr_from_mem_wave64(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//PC
>-	read_sgpr_from_mem_wave64(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)
>-	read_sgpr_from_mem_wave64(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//EXEC
>-	read_sgpr_from_mem_wave64(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)
>-	read_sgpr_from_mem_wave64(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//STATUS
>-	read_sgpr_from_mem_wave64(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//TRAPSTS
>-    //read_sgpr_from_mem_wave64(xnack_mask_lo, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK_LO
>-	//read_sgpr_from_mem_wave64(xnack_mask_hi, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK_HI
>-    read_sgpr_from_mem_wave64(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)					//XNACK_MASK
>-	read_sgpr_from_mem_wave64(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//MODE
>-    if(SAVE_RESTORE_HWID_DDID)
>-    read_sgpr_from_mem_wave64(s_restore_hwid1, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)				//HW_ID1
>-    end
>-  L_RESTORE_HWREG_FINISH:
>-	s_waitcnt		lgkmcnt(0)																						//from now on, it is safe to restore STATUS and IB_STS
>-  
>-
>-
>-    if(SAVE_RESTORE_HWID_DDID)
>-  L_RESTORE_DDID:
>-    s_mov_b32      m0, s_restore_hwid1                                                      //virture ttrace support: The save-context handler records the SE/SA/WGP/SIMD/wave of the original wave
>-    s_ttracedata                                                                            //and then can output it as SHADER_DATA to ttrace on restore to provide a correlation across the save-restore
>-                                    
>-    s_mov_b32		s_restore_buf_rsrc2, 0x4												//NUM_RECORDS	in bytes
>-	if (SWIZZLE_EN)
>-		s_add_u32		s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0						//FIXME need to use swizzle to enable bounds checking?
>-	else
>-		s_mov_b32		s_restore_buf_rsrc2,  0x1000000										//NUM_RECORDS in bytes
>-	end
>-
>-    s_and_b32       m0, s_restore_size, 1
>-    s_cmp_eq_u32    m0, 1
>-    s_cbranch_scc1  L_RESTORE_DDID_WAVE64
>-
>-    read_sgpr_from_mem_wave32(s_restore_ddid, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)	
>-    s_branch        L_RESTORE_DDID_FINISH
>-  L_RESTORE_DDID_WAVE64:
>-    read_sgpr_from_mem_wave64(s_restore_ddid, s_restore_buf_rsrc0, s_restore_mem_offset, SGPR_SAVE_USE_SQC)	
>-
>-  L_RESTORE_DDID_FINISH:
>-    s_waitcnt		lgkmcnt(0)
>-    //s_mov_b32      m0, s_restore_ddid
>-    //s_ttracedata   
>-    if (RESTORE_DDID_IN_SGPR18)
>-        s_mov_b32   s18, s_restore_ddid
>-	end	
>-    
>-    end   
>-
>-	s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff    	//pc[47:32]        //Do it here in order not to affect STATUS
>-
>-	//for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise:
>-	if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
>-		s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8            //pc[31:0]+8	  //two back-to-back s_trap are used (first for save and second for restore)
>-		s_addc_u32	s_restore_pc_hi, s_restore_pc_hi, 0x0		 //carry bit over
>-	end	
>-	if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL))	      
>-		s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4            //pc[31:0]+4     // save is hack through s_trap but restore is normal
>-		s_addc_u32	s_restore_pc_hi, s_restore_pc_hi, 0x0		 //carry bit over
>-	end
>-	
>-	s_mov_b32 		m0, 		s_restore_m0
>-	s_mov_b32 		exec_lo, 	s_restore_exec_lo
>-	s_mov_b32 		exec_hi, 	s_restore_exec_hi
>-	
>-	s_and_b32		s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts
>+	/* Setup Resource Contants */
>+	s_mov_b32	s_restore_buf_rsrc0, s_restore_spi_init_lo		//base_addr_lo
>+	s_and_b32	s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF	//base_addr_hi
>+	s_or_b32	s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE
>+	s_mov_b32	s_restore_buf_rsrc2, 0					//NUM_RECORDS initial value = 0 (in bytes)
>+	s_mov_b32	s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC
>+	s_and_b32	s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_ATC_MASK
>+	s_lshr_b32	s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_ATC_SHIFT-SQ_BUF_RSRC_WORD1_ATC_SHIFT)
>+	s_or_b32	s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp	//or ATC
>+	s_and_b32	s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_MTYPE_MASK
>+	s_lshr_b32	s_restore_tmp, s_restore_tmp, (S_RESTORE_SPI_INIT_MTYPE_SHIFT-SQ_BUF_RSRC_WORD3_MTYPE_SHIFT)
>+	s_or_b32	s_restore_buf_rsrc3, s_restore_buf_rsrc3, s_restore_tmp	//or MTYPE
>+	//determine it is wave32 or wave64
>+	s_getreg_b32	s_restore_size, hwreg(HW_REG_IB_STS2,SQ_WAVE_IB_STS2_WAVE64_SHIFT,SQ_WAVE_IB_STS2_WAVE64_SIZE)
>+	s_lshl_b32	s_restore_size, s_restore_size, S_WAVE_SIZE
>+	s_or_b32	s_restore_size, s_restore_spi_init_hi, s_restore_size
>+
>+	s_and_b32	s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK
>+	s_cbranch_scc0	L_RESTORE_VGPR
>+
>+	/* restore LDS */
>+L_RESTORE_LDS:
>+	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on
>+	s_lshr_b32	m0, s_restore_size, S_WAVE_SIZE
>+	s_and_b32	m0, m0, 1
>+	s_cmp_eq_u32	m0, 1
>+	s_cbranch_scc1	L_ENABLE_RESTORE_LDS_EXEC_HI
>+	s_mov_b32	exec_hi, 0x00000000
>+	s_branch	L_RESTORE_LDS_NORMAL
>+L_ENABLE_RESTORE_LDS_EXEC_HI:
>+	s_mov_b32	exec_hi, 0xFFFFFFFF
>+L_RESTORE_LDS_NORMAL:
>+	s_getreg_b32	s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)
>+	s_and_b32	s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF	//lds_size is zero?
>+	s_cbranch_scc0	L_RESTORE_VGPR						//no lds used? jump to L_RESTORE_VGPR
>+	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, 6		//LDS size in dwords = lds_size * 64dw
>+	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, 2		//LDS size in bytes
>+	s_mov_b32	s_restore_buf_rsrc2, s_restore_alloc_size		//NUM_RECORDS in bytes
>+
>+	// LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG)
>+	//
>+	get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size)
>+	get_svgpr_size_bytes(s_restore_tmp)
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes()
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes()
>+
>+	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
>+
>+	s_lshr_b32	m0, s_wave_size, S_WAVE_SIZE
>+	s_and_b32	m0, m0, 1
>+	s_cmp_eq_u32	m0, 1
>+	s_mov_b32	m0, 0x0
>+	s_cbranch_scc1	L_RESTORE_LDS_LOOP_W64
>+
>+L_RESTORE_LDS_LOOP_W32:
>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1	// first 64DW
>+	s_add_u32	m0, m0, 128						// 128 DW
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128		//mem offset increased by 128DW
>+	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc=(m0 < s_restore_alloc_size) ? 1 : 0
>+	s_cbranch_scc1	L_RESTORE_LDS_LOOP_W32					//LDS restore is complete?
>+	s_branch	L_RESTORE_VGPR
>+
>+L_RESTORE_LDS_LOOP_W64:
>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1	// first 64DW
>+	s_add_u32	m0, m0, 256						// 256 DW
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 256		//mem offset increased by 256DW
>+	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc=(m0 < s_restore_alloc_size) ? 1 : 0
>+	s_cbranch_scc1	L_RESTORE_LDS_LOOP_W64					//LDS restore is complete?
>+
>+	/* restore VGPRs */
>+L_RESTORE_VGPR:
>+	// VGPR SR memory offset : 0
>+	s_mov_b32	s_restore_mem_offset, 0x0
>+ 	s_mov_b32	exec_lo, 0xFFFFFFFF					//need every thread from now on
>+	s_lshr_b32	m0, s_restore_size, S_WAVE_SIZE
>+	s_and_b32	m0, m0, 1
>+	s_cmp_eq_u32	m0, 1
>+	s_cbranch_scc1	L_ENABLE_RESTORE_VGPR_EXEC_HI
>+	s_mov_b32	exec_hi, 0x00000000
>+	s_branch	L_RESTORE_VGPR_NORMAL
>+L_ENABLE_RESTORE_VGPR_EXEC_HI:
>+	s_mov_b32	exec_hi, 0xFFFFFFFF
>+L_RESTORE_VGPR_NORMAL:
>+	s_getreg_b32	s_restore_alloc_size, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)
>+	s_add_u32	s_restore_alloc_size, s_restore_alloc_size, 1
>+	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, 2		//Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
>+	//determine it is wave32 or wave64
>+	s_lshr_b32	m0, s_restore_size, S_WAVE_SIZE
>+	s_and_b32	m0, m0, 1
>+	s_cmp_eq_u32	m0, 1
>+	s_cbranch_scc1	L_RESTORE_VGPR_WAVE64
>+
>+	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
>+
>+	// VGPR load using dw burst
>+	s_mov_b32	s_restore_mem_offset_save, s_restore_mem_offset		// restore start with v1, v0 will be the last
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128*4
>+	s_mov_b32	m0, 4							//VGPR initial index value = 4
>+
>+L_RESTORE_VGPR_WAVE32_LOOP:
>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
>+	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128
>+	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*2
>+	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*3
>+	s_waitcnt	vmcnt(0)
>+	v_movreld_b32	v0, v0							//v[0+m0] = v0
>+	v_movreld_b32	v1, v1
>+	v_movreld_b32	v2, v2
>+	v_movreld_b32	v3, v3
>+	s_add_u32	m0, m0, 4						//next vgpr index
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128*4	//every buffer_load_dword does 128 bytes
>+	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc = (m0 < s_restore_alloc_size) ? 1 : 0
>+	s_cbranch_scc1	L_RESTORE_VGPR_WAVE32_LOOP				//VGPR restore (except v0) is complete?
>+
>+	/* VGPR restore on v0 */
>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1
>+	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128
>+	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*2
>+	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*3
>+
>+	s_branch	L_RESTORE_SGPR
>+
>+L_RESTORE_VGPR_WAVE64:
>+	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
>+
>+	// VGPR load using dw burst
>+	s_mov_b32	s_restore_mem_offset_save, s_restore_mem_offset		// restore start with v4, v0 will be the last
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 256*4
>+	s_mov_b32	m0, 4							//VGPR initial index value = 4
>+
>+L_RESTORE_VGPR_WAVE64_LOOP:
>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
>+	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256
>+	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2
>+	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3
>+	s_waitcnt	vmcnt(0)
>+	v_movreld_b32	v0, v0							//v[0+m0] = v0
>+	v_movreld_b32	v1, v1
>+	v_movreld_b32	v2, v2
>+	v_movreld_b32	v3, v3
>+	s_add_u32	m0, m0, 4						//next vgpr index
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 256*4	//every buffer_load_dword does 256 bytes
>+	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc = (m0 < s_restore_alloc_size) ? 1 : 0
>+	s_cbranch_scc1	L_RESTORE_VGPR_WAVE64_LOOP				//VGPR restore (except v0) is complete?
>+
>+	//Below part will be the restore shared vgpr part (new for gfx10)
>+	s_getreg_b32	s_restore_alloc_size, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE)	//shared_vgpr_size
>+	s_and_b32	s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF	//shared_vgpr_size is zero?
>+	s_cbranch_scc0	L_RESTORE_V0						//no shared_vgpr used?
>+	s_lshl_b32	s_restore_alloc_size, s_restore_alloc_size, 3		//Number of SHARED_VGPRs = shared_vgpr_size * 8    (non-zero value)
>+	//m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count.
>+	//restore shared_vgpr will start from the index of m0
>+	s_add_u32	s_restore_alloc_size, s_restore_alloc_size, m0
>+	s_mov_b32	exec_lo, 0xFFFFFFFF
>+	s_mov_b32	exec_hi, 0x00000000
>+L_RESTORE_SHARED_VGPR_WAVE64_LOOP:
>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
>+	s_waitcnt	vmcnt(0)
>+	v_movreld_b32	v0, v0							//v[0+m0] = v0
>+	s_add_u32	m0, m0, 1						//next vgpr index
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, 128
>+	s_cmp_lt_u32	m0, s_restore_alloc_size				//scc = (m0 < s_restore_alloc_size) ? 1 : 0
>+	s_cbranch_scc1	L_RESTORE_SHARED_VGPR_WAVE64_LOOP			//VGPR restore (except v0) is complete?
>+
>+	s_mov_b32	exec_hi, 0xFFFFFFFF					//restore back exec_hi before restoring V0!!
>+
>+	/* VGPR restore on v0 */
>+L_RESTORE_V0:
>+	buffer_load_dword	v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1
>+	buffer_load_dword	v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256
>+	buffer_load_dword	v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*2
>+	buffer_load_dword	v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256*3
>+
>+	/* restore SGPRs */
>+	//will be 2+8+16*6
>+	// SGPR SR memory offset : size(VGPR)+size(SVGPR)
>+L_RESTORE_SGPR:
>+	get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size)
>+	get_svgpr_size_bytes(s_restore_tmp)
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes()
>+	s_sub_u32	s_restore_mem_offset, s_restore_mem_offset, 20*4	//s108~s127 is not saved
>+
>+	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
>+
>+	s_mov_b32	m0, s_sgpr_save_num
>+
>+	read_4sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	s_waitcnt	lgkmcnt(0)
>+
>+	s_sub_u32	m0, m0, 4						// Restore from S[0] to S[104]
>+	s_nop		0							// hazard SALU M0=> S_MOVREL
>+
>+	s_movreld_b64	s0, s0							//s[0+m0] = s0
>+	s_movreld_b64	s2, s2
>+
>+	read_8sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	s_waitcnt	lgkmcnt(0)
>+
>+	s_sub_u32	m0, m0, 8						// Restore from S[0] to S[96]
>+	s_nop		0							// hazard SALU M0=> S_MOVREL
>+
>+	s_movreld_b64	s0, s0							//s[0+m0] = s0
>+	s_movreld_b64	s2, s2
>+	s_movreld_b64	s4, s4
>+	s_movreld_b64	s6, s6
>+
>+ L_RESTORE_SGPR_LOOP:
>+	read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	s_waitcnt	lgkmcnt(0)
>+
>+	s_sub_u32	m0, m0, 16						// Restore from S[n] to S[0]
>+	s_nop		0							// hazard SALU M0=> S_MOVREL
>+
>+	s_movreld_b64	s0, s0							//s[0+m0] = s0
>+	s_movreld_b64	s2, s2
>+	s_movreld_b64	s4, s4
>+	s_movreld_b64	s6, s6
>+	s_movreld_b64	s8, s8
>+	s_movreld_b64	s10, s10
>+	s_movreld_b64	s12, s12
>+	s_movreld_b64	s14, s14
>+
>+	s_cmp_eq_u32	m0, 0							//scc = (m0 < s_sgpr_save_num) ? 1 : 0
>+	s_cbranch_scc0	L_RESTORE_SGPR_LOOP
>+
>+	/* restore HW registers */
>+L_RESTORE_HWREG:
>+	// HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)
>+	get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size)
>+	get_svgpr_size_bytes(s_restore_tmp)
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp
>+	s_add_u32	s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes()
>+
>+	s_mov_b32	s_restore_buf_rsrc2, 0x1000000				//NUM_RECORDS in bytes
>+
>+	read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	read_hwreg_from_mem(s_restore_status, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	read_hwreg_from_mem(s_restore_trapsts, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	read_hwreg_from_mem(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	s_waitcnt	lgkmcnt(0)
>+
>+	s_setreg_b32	hwreg(HW_REG_SHADER_FLAT_SCRATCH_LO), s_restore_flat_scratch
>+
>+	read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset)
>+	s_waitcnt	lgkmcnt(0)						//from now on, it is safe to restore STATUS and IB_STS
>+
>+	s_setreg_b32	hwreg(HW_REG_SHADER_FLAT_SCRATCH_HI), s_restore_flat_scratch
>+
>+	s_mov_b32	s_restore_tmp, s_restore_pc_hi
>+	s_and_b32	s_restore_pc_hi, s_restore_tmp, 0x0000ffff		//pc[47:32] //Do it here in order not to affect STATUS
>+
>+	s_mov_b32	m0, s_restore_m0
>+	s_mov_b32	exec_lo, s_restore_exec_lo
>+	s_mov_b32	exec_hi, s_restore_exec_hi
>+
>+	s_and_b32	s_restore_m0, SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK, s_restore_trapsts
> 	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE), s_restore_m0
>-    s_setreg_b32    hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask         //restore xnack_mask
>-	s_and_b32		s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts
>-	s_lshr_b32		s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT
>+	s_setreg_b32	hwreg(HW_REG_SHADER_XNACK_MASK), s_restore_xnack_mask
>+	s_and_b32	s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK, s_restore_trapsts
>+	s_lshr_b32	s_restore_m0, s_restore_m0, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT
> 	s_setreg_b32	hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT, SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE), s_restore_m0
>-	//s_setreg_b32 	hwreg(HW_REG_TRAPSTS), 	s_restore_trapsts      //don't overwrite SAVECTX bit as it may be set through external SAVECTX during restore
>-	s_setreg_b32 	hwreg(HW_REG_MODE), 	s_restore_mode
>-	//reuse s_restore_m0 as a temp register
>-	s_and_b32		s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_RCNT_MASK
>-	s_lshr_b32		s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT
>-	s_lshl_b32		s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT
>-	s_mov_b32		s_restore_tmp, 0x0																				//IB_STS is zero
>-	s_or_b32		s_restore_tmp, s_restore_tmp, s_restore_m0
>-	s_and_b32		s_restore_m0, s_restore_pc_hi, S_SAVE_PC_HI_FIRST_REPLAY_MASK
>-	s_lshr_b32		s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
>-	s_lshl_b32		s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT
>-	s_or_b32		s_restore_tmp, s_restore_tmp, s_restore_m0
>-    s_and_b32       s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK 
>-    s_lshr_b32		s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT
>-	s_setreg_b32 	hwreg(HW_REG_IB_STS), 	s_restore_tmp
>-	s_setreg_b32 	hwreg(HW_REG_STATUS), 	s_restore_status
>-
>-	s_barrier													//barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG //FIXME not performance-optimal at this time
>-	
>-	
>-//	s_rfe_b64 s_restore_pc_lo                              		//Return to the main shader program and resume execution
>-    s_rfe_b64  s_restore_pc_lo            // s_restore_m0[0] is used to set STATUS.inst_atc 
>-
>-
>-/**************************************************************************/
>-/*                     	the END								              */
>-/**************************************************************************/	
>-L_END_PGM:	
>+	s_setreg_b32	hwreg(HW_REG_MODE), s_restore_mode
>+	s_and_b32	s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_RCNT_MASK
>+	s_lshr_b32	s_restore_m0, s_restore_m0, S_SAVE_PC_HI_RCNT_SHIFT
>+	s_lshl_b32	s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_RCNT_SHIFT
>+	s_mov_b32	s_restore_mode, 0x0
>+	s_or_b32	s_restore_mode, s_restore_mode, s_restore_m0
>+	s_and_b32	s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_FIRST_REPLAY_MASK
>+	s_lshr_b32	s_restore_m0, s_restore_m0, S_SAVE_PC_HI_FIRST_REPLAY_SHIFT
>+	s_lshl_b32	s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT
>+	s_or_b32	s_restore_mode, s_restore_mode, s_restore_m0
>+	s_and_b32	s_restore_m0, s_restore_tmp, S_SAVE_PC_HI_REPLAY_W64H_MASK
>+	s_lshr_b32	s_restore_m0, s_restore_m0, S_SAVE_PC_HI_REPLAY_W64H_SHIFT
>+	s_lshl_b32	s_restore_m0, s_restore_m0, SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT
>+	s_or_b32	s_restore_mode, s_restore_mode, s_restore_m0
>+
>+	s_and_b32	s_restore_m0, s_restore_status, SQ_WAVE_STATUS_INST_ATC_MASK
>+	s_lshr_b32	s_restore_m0, s_restore_m0, SQ_WAVE_STATUS_INST_ATC_SHIFT
>+	s_setreg_b32 	hwreg(HW_REG_IB_STS), s_restore_mode
>+
>+	s_and_b64	exec, exec, exec					// Restore STATUS.EXECZ, not writable by s_setreg_b32
>+	s_and_b64	vcc, vcc, vcc						// Restore STATUS.VCCZ, not writable by s_setreg_b32
>+	s_setreg_b32	hwreg(HW_REG_STATUS), s_restore_status			// SCC is included, which is changed by previous salu
>+
>+	s_barrier								//barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG
>+
>+	s_rfe_b64	s_restore_pc_lo						//Return to the main shader program and resume execution
>+
>+L_END_PGM:
> 	s_endpgm
>-	
>-end	
>+end
>+
>+function write_hwreg_to_mem(s, s_rsrc, s_mem_offset)
>+	s_mov_b32	exec_lo, m0
>+	s_mov_b32	m0, s_mem_offset
>+	s_buffer_store_dword	s, s_rsrc, m0 glc:1
>+	s_add_u32	s_mem_offset, s_mem_offset, 4
>+	s_mov_b32	m0, exec_lo
>+end
>+
>+
>+function write_16sgpr_to_mem(s, s_rsrc, s_mem_offset)
>+	s_buffer_store_dwordx4	s[0], s_rsrc, 0 glc:1
>+	s_buffer_store_dwordx4	s[4], s_rsrc, 16 glc:1
>+	s_buffer_store_dwordx4	s[8], s_rsrc, 32 glc:1
>+	s_buffer_store_dwordx4	s[12], s_rsrc, 48 glc:1
>+	s_add_u32	s_rsrc[0], s_rsrc[0], 4*16
>+	s_addc_u32	s_rsrc[1], s_rsrc[1], 0x0
>+end
>+
>+function write_12sgpr_to_mem(s, s_rsrc, s_mem_offset)
>+	s_buffer_store_dwordx4	s[0], s_rsrc, 0 glc:1
>+	s_buffer_store_dwordx4	s[4], s_rsrc, 16 glc:1
>+	s_buffer_store_dwordx4	s[8], s_rsrc, 32 glc:1
>+	s_add_u32	s_rsrc[0], s_rsrc[0], 4*12
>+	s_addc_u32	s_rsrc[1], s_rsrc[1], 0x0
>+end
>+
>+
>+function read_hwreg_from_mem(s, s_rsrc, s_mem_offset)
>+	s_buffer_load_dword	s, s_rsrc, s_mem_offset glc:1
>+	s_add_u32	s_mem_offset, s_mem_offset, 4
>+end
>+
>+function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset)
>+	s_sub_u32	s_mem_offset, s_mem_offset, 4*16
>+	s_buffer_load_dwordx16	s, s_rsrc, s_mem_offset glc:1
>+end
>+
>+function read_8sgpr_from_mem(s, s_rsrc, s_mem_offset)
>+	s_sub_u32	s_mem_offset, s_mem_offset, 4*8
>+	s_buffer_load_dwordx8	s, s_rsrc, s_mem_offset glc:1
>+end
>+
>+function read_4sgpr_from_mem(s, s_rsrc, s_mem_offset)
>+	s_sub_u32	s_mem_offset, s_mem_offset, 4*4
>+	s_buffer_load_dwordx4	s, s_rsrc, s_mem_offset glc:1
>+end
> 
> 
>-/**************************************************************************/
>-/*                     	the helper functions							  */
>-/**************************************************************************/
>-function write_sgpr_to_mem_wave32(s, s_rsrc, s_mem_offset, use_sqc, use_mtbuf)
>-	if (use_sqc)
>-		s_mov_b32 exec_lo, m0					//assuming exec_lo is not needed anymore from this point on
>-		s_mov_b32 m0, s_mem_offset
>-		s_buffer_store_dword s, s_rsrc, m0		glc:1	
>-		s_add_u32		s_mem_offset, s_mem_offset, 4
>-		s_mov_b32	m0, exec_lo
>-    elsif (use_mtbuf)
>-        v_mov_b32	v0,	s
>-        tbuffer_store_format_x v0, v0, s_rsrc, s_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-		s_add_u32		s_mem_offset, s_mem_offset, 128
>-    else 
>-        v_mov_b32	v0,	s
>-		buffer_store_dword	v0, v0, s_rsrc, s_mem_offset	slc:1 glc:1
>-        s_add_u32		s_mem_offset, s_mem_offset, 128
>-	end
>+function get_lds_size_bytes(s_lds_size_byte)
>+	s_getreg_b32	s_lds_size_byte, hwreg(HW_REG_LDS_ALLOC, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT, SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE)
>+	s_lshl_b32	s_lds_size_byte, s_lds_size_byte, 8			//LDS size in dwords = lds_size * 64 *4Bytes // granularity 64DW
> end
> 
>-function write_sgpr_to_mem_wave64(s, s_rsrc, s_mem_offset, use_sqc, use_mtbuf)
>-	if (use_sqc)
>-		s_mov_b32 exec_lo, m0					//assuming exec_lo is not needed anymore from this point on
>-		s_mov_b32 m0, s_mem_offset
>-		s_buffer_store_dword s, s_rsrc, m0		glc:1	
>-		s_add_u32		s_mem_offset, s_mem_offset, 4
>-		s_mov_b32	m0, exec_lo
>-    elsif (use_mtbuf)
>-        v_mov_b32	v0,	s
>-        tbuffer_store_format_x v0, v0, s_rsrc, s_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-		s_add_u32		s_mem_offset, s_mem_offset, 256
>-    else 
>-        v_mov_b32	v0,	s
>-		buffer_store_dword	v0, v0, s_rsrc, s_mem_offset	slc:1 glc:1
>-        s_add_u32		s_mem_offset, s_mem_offset, 256
>-	end
>+function get_vgpr_size_bytes(s_vgpr_size_byte, s_size)
>+	s_getreg_b32	s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)
>+	s_add_u32	s_vgpr_size_byte, s_vgpr_size_byte, 1
>+	s_lshr_b32	m0, s_size, S_WAVE_SIZE
>+	s_and_b32	m0, m0, 1
>+	s_cmp_eq_u32	m0, 1
>+	s_cbranch_scc1	L_ENABLE_SHIFT_W64
>+	s_lshl_b32	s_vgpr_size_byte, s_vgpr_size_byte, (2+7)		//Number of VGPRs = (vgpr_size + 1) * 4 * 32 * 4   (non-zero value)
>+	s_branch	L_SHIFT_DONE
>+L_ENABLE_SHIFT_W64:
>+	s_lshl_b32	s_vgpr_size_byte, s_vgpr_size_byte, (2+8)		//Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4   (non-zero value)
>+L_SHIFT_DONE:
> end
> 
>-function read_sgpr_from_mem_wave32(s, s_rsrc, s_mem_offset, use_sqc)
>-	s_buffer_load_dword s, s_rsrc, s_mem_offset		glc:1
>-	if (use_sqc)
>-		s_add_u32		s_mem_offset, s_mem_offset, 4
>-	else
>-        s_add_u32		s_mem_offset, s_mem_offset, 128
>-	end
>+function get_svgpr_size_bytes(s_svgpr_size_byte)
>+	s_getreg_b32	s_svgpr_size_byte, hwreg(HW_REG_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE)
>+	s_lshl_b32	s_svgpr_size_byte, s_svgpr_size_byte, (3+7)
> end
> 
>-function read_sgpr_from_mem_wave64(s, s_rsrc, s_mem_offset, use_sqc)
>-	s_buffer_load_dword s, s_rsrc, s_mem_offset		glc:1
>-	if (use_sqc)
>-		s_add_u32		s_mem_offset, s_mem_offset, 4
>-	else
>-        s_add_u32		s_mem_offset, s_mem_offset, 256
>-	end
>+function get_sgpr_size_bytes
>+	return 512
> end
> 
>+function get_hwreg_size_bytes
>+	return 128
>+end
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx8.asm	2019-08-31 15:01:11.853736168 -0500
>@@ -24,78 +24,6 @@
>  * PROJECT=vi ./sp3 cwsr_trap_handler_gfx8.asm -hex tmp.hex
>  */
> 
>-/* HW (VI) source code for CWSR trap handler */
>-/* Version 18 + multiple trap handler */
>-
>-// this performance-optimal version was originally from Seven Xu at SRDC
>-
>-// Revison #18   --...
>-/* Rev History
>-** #1. Branch from gc dv.   //gfxip/gfx8/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV)
>-** #4. SR Memory Layout:
>-**             1. VGPR-SGPR-HWREG-{LDS}
>-**             2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern..
>-** #5. Update: 1. Accurate g8sr_ts_save_d timestamp
>-** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation)
>-** #7. Update: 1. don't barrier if noLDS
>-** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version
>-**             2. Fix SQ issue by s_sleep 2
>-** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last
>-**             2. optimize s_buffer save by burst 16sgprs...
>-** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs.
>-** #11. Update 1. Add 2 more timestamp for debug version
>-** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance
>-** #13. Integ  1. Always use MUBUF for PV trap shader...
>-** #14. Update 1. s_buffer_store soft clause...
>-** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot.
>-** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree
>-** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part]
>-**             2. PERF - Save LDS before save VGPR to cover LDS save long latency...
>-** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32
>-**             2. FUNC - Handle non-CWSR traps
>-*/
>-
>-var G8SR_WDMEM_HWREG_OFFSET = 0
>-var G8SR_WDMEM_SGPR_OFFSET  = 128  // in bytes
>-
>-// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore.
>-
>-var G8SR_DEBUG_TIMESTAMP = 0
>-var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4  // ts_save_d timestamp offset relative to SGPR_SR_memory_offset
>-var s_g8sr_ts_save_s    = s[34:35]   // save start
>-var s_g8sr_ts_sq_save_msg  = s[36:37]   // The save shader send SAVEWAVE msg to spi
>-var s_g8sr_ts_spi_wrexec   = s[38:39]   // the SPI write the sr address to SQ
>-var s_g8sr_ts_save_d    = s[40:41]   // save end
>-var s_g8sr_ts_restore_s = s[42:43]   // restore start
>-var s_g8sr_ts_restore_d = s[44:45]   // restore end
>-
>-var G8SR_VGPR_SR_IN_DWX4 = 0
>-var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000    // DWx4 stride is 4*4Bytes
>-var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4  = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4
>-
>-
>-/*************************************************************************/
>-/*                  control on how to run the shader                     */
>-/*************************************************************************/
>-//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run)
>-var EMU_RUN_HACK                    =   0
>-var EMU_RUN_HACK_RESTORE_NORMAL     =   0
>-var EMU_RUN_HACK_SAVE_NORMAL_EXIT   =   0
>-var EMU_RUN_HACK_SAVE_SINGLE_WAVE   =   0
>-var EMU_RUN_HACK_SAVE_FIRST_TIME    =   0                   //for interrupted restore in which the first save is through EMU_RUN_HACK
>-var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO =   0                   //for interrupted restore in which the first save is through EMU_RUN_HACK
>-var EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI =   0                   //for interrupted restore in which the first save is through EMU_RUN_HACK
>-var SAVE_LDS                        =   1
>-var WG_BASE_ADDR_LO                 =   0x9000a000
>-var WG_BASE_ADDR_HI                 =   0x0
>-var WAVE_SPACE                      =   0x5000              //memory size that each wave occupies in workgroup state mem
>-var CTX_SAVE_CONTROL                =   0x0
>-var CTX_RESTORE_CONTROL             =   CTX_SAVE_CONTROL
>-var SIM_RUN_HACK                    =   0                   //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run)
>-var SGPR_SAVE_USE_SQC               =   1                   //use SQC D$ to do the write
>-var USE_MTBUF_INSTEAD_OF_MUBUF      =   0                   //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes
>-var SWIZZLE_EN                      =   0                   //whether we use swizzled buffer addressing
>-
> /**************************************************************************/
> /*                      variables                                         */
> /**************************************************************************/
>@@ -226,16 +154,7 @@
>   type(CS)
> 
> 
>-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))                   //hack to use trap_id for determining save/restore
>-        //FIXME VCCZ un-init assertion s_getreg_b32     s_save_status, hwreg(HW_REG_STATUS)         //save STATUS since we will change SCC
>-        s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000              //change SCC
>-        s_cmp_eq_u32 s_save_tmp, 0x007e0000                         //Save: trap_id = 0x7e. Restore: trap_id = 0x7f.
>-        s_cbranch_scc0 L_JUMP_TO_RESTORE                            //do not need to recover STATUS here  since we are going to RESTORE
>-        //FIXME  s_setreg_b32   hwreg(HW_REG_STATUS),   s_save_status       //need to recover STATUS since we are going to SAVE
>-        s_branch L_SKIP_RESTORE                                     //NOT restore, SAVE actually
>-    else
>         s_branch L_SKIP_RESTORE                                     //NOT restore. might be a regular trap or save
>-    end
> 
> L_JUMP_TO_RESTORE:
>     s_branch L_RESTORE                                              //restore
>@@ -249,7 +168,7 @@
>     s_cbranch_scc1  L_SAVE                                      //this is the operation for save
> 
>     // *********    Handle non-CWSR traps       *******************
>-if (!EMU_RUN_HACK)
>+
>     /* read tba and tma for next level trap handler, ttmp4 is used as s_save_status */
>     s_load_dwordx4  [ttmp8,ttmp9,ttmp10, ttmp11], [tma_lo,tma_hi], 0
>     s_waitcnt lgkmcnt(0)
>@@ -268,7 +187,7 @@
>     s_and_b32   ttmp1, ttmp1, 0xFFFF
>     set_status_without_spi_prio(s_save_status, ttmp2) //restore HW status(SCC)
>     s_rfe_b64       [ttmp0, ttmp1]
>-end
>+
>     // *********        End handling of non-CWSR traps   *******************
> 
> /**************************************************************************/
>@@ -276,12 +195,6 @@
> /**************************************************************************/
> 
> L_SAVE:
>-
>-if G8SR_DEBUG_TIMESTAMP
>-        s_memrealtime   s_g8sr_ts_save_s
>-        s_waitcnt lgkmcnt(0)         //FIXME, will cause xnack??
>-end
>-
>     s_mov_b32       s_save_tmp, 0                                                           //clear saveCtx bit
>     s_setreg_b32    hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT, 1), s_save_tmp     //clear saveCtx bit
> 
>@@ -303,16 +216,7 @@
>     s_mov_b32       s_save_exec_hi, exec_hi
>     s_mov_b64       exec,   0x0                                                             //clear EXEC to get ready to receive
> 
>-if G8SR_DEBUG_TIMESTAMP
>-        s_memrealtime  s_g8sr_ts_sq_save_msg
>-        s_waitcnt lgkmcnt(0)
>-end
>-
>-    if (EMU_RUN_HACK)
>-
>-    else
>         s_sendmsg   sendmsg(MSG_SAVEWAVE)  //send SPI a message and wait for SPI's write to EXEC
>-    end
> 
>     // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for.
>     s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT)
>@@ -321,36 +225,9 @@
>   L_SLEEP:
>     s_sleep 0x2                // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0
> 
>-    if (EMU_RUN_HACK)
>-
>-    else
>         s_cbranch_execz L_SLEEP
>-    end
>-
>-if G8SR_DEBUG_TIMESTAMP
>-        s_memrealtime  s_g8sr_ts_spi_wrexec
>-        s_waitcnt lgkmcnt(0)
>-end
> 
>     /*      setup Resource Contants    */
>-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE))
>-        //calculate wd_addr using absolute thread id
>-        v_readlane_b32 s_save_tmp, v9, 0
>-        s_lshr_b32 s_save_tmp, s_save_tmp, 6
>-        s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE
>-        s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
>-        s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
>-        s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
>-    else
>-    end
>-    if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE))
>-        s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
>-        s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
>-        s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
>-    else
>-    end
>-
>-
>     s_mov_b32       s_save_buf_rsrc0,   s_save_spi_init_lo                                                      //base_addr_lo
>     s_and_b32       s_save_buf_rsrc1,   s_save_spi_init_hi, 0x0000FFFF                                          //base_addr_hi
>     s_or_b32        s_save_buf_rsrc1,   s_save_buf_rsrc1,  S_SAVE_BUF_RSRC_WORD1_STRIDE
>@@ -383,22 +260,10 @@
> 
> 
>     s_mov_b32       s_save_buf_rsrc2, 0x4                               //NUM_RECORDS   in bytes
>-    if (SWIZZLE_EN)
>-        s_add_u32       s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0                     //FIXME need to use swizzle to enable bounds checking?
>-    else
>         s_mov_b32       s_save_buf_rsrc2,  0x1000000                                //NUM_RECORDS in bytes
>-    end
> 
> 
>     write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)                  //M0
>-
>-    if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME))
>-        s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
>-        s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0          //carry bit over
>-        s_mov_b32   tba_lo, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_LO
>-        s_mov_b32   tba_hi, EMU_RUN_HACK_SAVE_FIRST_TIME_TBA_HI
>-    end
>-
>     write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset)                   //PC
>     write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset)
>     write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset)             //EXEC
>@@ -440,18 +305,8 @@
>     s_add_u32       s_save_alloc_size, s_save_alloc_size, 1
>     s_lshl_b32      s_save_alloc_size, s_save_alloc_size, 4                         //Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
> 
>-    if (SGPR_SAVE_USE_SQC)
>         s_lshl_b32      s_save_buf_rsrc2,   s_save_alloc_size, 2                    //NUM_RECORDS in bytes
>-    else
>-        s_lshl_b32      s_save_buf_rsrc2,   s_save_alloc_size, 8                    //NUM_RECORDS in bytes (64 threads)
>-    end
>-
>-    if (SWIZZLE_EN)
>-        s_add_u32       s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0                     //FIXME need to use swizzle to enable bounds checking?
>-    else
>         s_mov_b32       s_save_buf_rsrc2,  0x1000000                                //NUM_RECORDS in bytes
>-    end
>-
> 
>     // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0
>     //s_mov_b64 s_save_pc_lo, s_save_buf_rsrc0
>@@ -490,30 +345,14 @@
>     s_mov_b32       exec_lo, 0xFFFFFFFF                                             //need every thread from now on
>     s_mov_b32       exec_hi, 0xFFFFFFFF
> 
>-    if (SWIZZLE_EN)
>-        s_add_u32       s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0                     //FIXME need to use swizzle to enable bounds checking?
>-    else
>         s_mov_b32       s_save_buf_rsrc2,  0x1000000                                //NUM_RECORDS in bytes
>-    end
>-
> 
>     // VGPR Allocated in 4-GPR granularity
> 
>-if G8SR_VGPR_SR_IN_DWX4
>-        // the const stride for DWx4 is 4*4 bytes
>-        s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
>-        s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4  // const stride to 4*4 bytes
>-
>-        buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>-
>-        s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
>-        s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE  // reset const stride to 4 bytes
>-else
>         buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>         buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256
>         buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*2
>         buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*3
>-end
> 
> 
> 
>@@ -549,64 +388,10 @@
>     s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes()
> 
> 
>-    if (SWIZZLE_EN)
>-        s_add_u32       s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0       //FIXME need to use swizzle to enable bounds checking?
>-    else
>         s_mov_b32       s_save_buf_rsrc2,  0x1000000                  //NUM_RECORDS in bytes
>-    end
>-
>     s_mov_b32       m0, 0x0                                               //lds_offset initial value = 0
> 
> 
>-var LDS_DMA_ENABLE = 0
>-var UNROLL = 0
>-if UNROLL==0 && LDS_DMA_ENABLE==1
>-        s_mov_b32  s3, 256*2
>-        s_nop 0
>-        s_nop 0
>-        s_nop 0
>-  L_SAVE_LDS_LOOP:
>-        //TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.???
>-    if (SAVE_LDS)     //SPI always alloc LDS space in 128DW granularity
>-            buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1            // first 64DW
>-            buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW
>-    end
>-
>-    s_add_u32       m0, m0, s3                                          //every buffer_store_lds does 256 bytes
>-    s_add_u32       s_save_mem_offset, s_save_mem_offset, s3                            //mem offset increased by 256 bytes
>-    s_cmp_lt_u32    m0, s_save_alloc_size                                               //scc=(m0 < s_save_alloc_size) ? 1 : 0
>-    s_cbranch_scc1  L_SAVE_LDS_LOOP                                                     //LDS save is complete?
>-
>-elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL  , has ichace miss
>-      // store from higest LDS address to lowest
>-      s_mov_b32  s3, 256*2
>-      s_sub_u32  m0, s_save_alloc_size, s3
>-      s_add_u32 s_save_mem_offset, s_save_mem_offset, m0
>-      s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9   // how many 128 trunks...
>-      s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size   // store from higheset addr to lowest
>-      s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4   // PC offset increment,  each LDS save block cost 6*4 Bytes instruction
>-      s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4   //2is the below 2 inst...//s_addc and s_setpc
>-      s_nop 0
>-      s_nop 0
>-      s_nop 0   //pad 3 dw to let LDS_DMA align with 64Bytes
>-      s_getpc_b64 s[0:1]                              // reuse s[0:1], since s[0:1] already saved
>-      s_add_u32   s0, s0,s_save_alloc_size
>-      s_addc_u32  s1, s1, 0
>-      s_setpc_b64 s[0:1]
>-
>-
>-       for var i =0; i< 128; i++
>-            // be careful to make here a 64Byte aligned address, which could improve performance...
>-            buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0           // first 64DW
>-            buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256           // second 64DW
>-
>-        if i!=127
>-        s_sub_u32  m0, m0, s3      // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e.  pack more LDS_DMA inst to one Cacheline
>-            s_sub_u32  s_save_mem_offset, s_save_mem_offset,  s3
>-            end
>-       end
>-
>-else   // BUFFER_STORE
>       v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0
>       v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2     // tid
>       v_mul_i32_i24 v2, v3, 8   // tid*8
>@@ -628,8 +413,6 @@
>       // restore rsrc3
>       s_mov_b32 s_save_buf_rsrc3, s0
> 
>-end
>-
> L_SAVE_LDS_DONE:
> 
> 
>@@ -647,44 +430,8 @@
>     s_add_u32       s_save_alloc_size, s_save_alloc_size, 1
>     s_lshl_b32      s_save_alloc_size, s_save_alloc_size, 2                         //Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)   //FIXME for GFX, zero is possible
>     s_lshl_b32      s_save_buf_rsrc2,  s_save_alloc_size, 8                         //NUM_RECORDS in bytes (64 threads*4)
>-    if (SWIZZLE_EN)
>-        s_add_u32       s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0                     //FIXME need to use swizzle to enable bounds checking?
>-    else
>         s_mov_b32       s_save_buf_rsrc2,  0x1000000                                //NUM_RECORDS in bytes
>-    end
>-
>-
>-    // VGPR Allocated in 4-GPR granularity
> 
>-if G8SR_VGPR_SR_IN_DWX4
>-        // the const stride for DWx4 is 4*4 bytes
>-        s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
>-        s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4  // const stride to 4*4 bytes
>-
>-        s_mov_b32         m0, 4     // skip first 4 VGPRs
>-        s_cmp_lt_u32      m0, s_save_alloc_size
>-        s_cbranch_scc0    L_SAVE_VGPR_LOOP_END      // no more vgprs
>-
>-        s_set_gpr_idx_on  m0, 0x1   // This will change M0
>-        s_add_u32         s_save_alloc_size, s_save_alloc_size, 0x1000  // because above inst change m0
>-L_SAVE_VGPR_LOOP:
>-        v_mov_b32         v0, v0   // v0 = v[0+m0]
>-        v_mov_b32         v1, v1
>-        v_mov_b32         v2, v2
>-        v_mov_b32         v3, v3
>-
>-
>-        buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>-        s_add_u32         m0, m0, 4
>-        s_add_u32         s_save_mem_offset, s_save_mem_offset, 256*4
>-        s_cmp_lt_u32      m0, s_save_alloc_size
>-    s_cbranch_scc1  L_SAVE_VGPR_LOOP                                                //VGPR save is complete?
>-    s_set_gpr_idx_off
>-L_SAVE_VGPR_LOOP_END:
>-
>-        s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
>-        s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE  // reset const stride to 4 bytes
>-else
>     // VGPR store using dw burst
>     s_mov_b32         m0, 0x4   //VGPR initial index value =0
>     s_cmp_lt_u32      m0, s_save_alloc_size
>@@ -700,52 +447,18 @@
>     v_mov_b32       v2, v2              //v0 = v[0+m0]
>     v_mov_b32       v3, v3              //v0 = v[0+m0]
> 
>-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
>-        tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-    else
>         buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>         buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256
>         buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*2
>         buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*3
>-    end
> 
>     s_add_u32       m0, m0, 4                                                       //next vgpr index
>     s_add_u32       s_save_mem_offset, s_save_mem_offset, 256*4                     //every buffer_store_dword does 256 bytes
>     s_cmp_lt_u32    m0, s_save_alloc_size                                           //scc = (m0 < s_save_alloc_size) ? 1 : 0
>     s_cbranch_scc1  L_SAVE_VGPR_LOOP                                                //VGPR save is complete?
>     s_set_gpr_idx_off
>-end
> 
> L_SAVE_VGPR_END:
>-
>-
>-
>-
>-
>-
>-    /*     S_PGM_END_SAVED  */                              //FIXME  graphics ONLY
>-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT))
>-        s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
>-        s_add_u32 s_save_pc_lo, s_save_pc_lo, 4             //pc[31:0]+4
>-        s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0          //carry bit over
>-        s_rfe_b64 s_save_pc_lo                              //Return to the main shader program
>-    else
>-    end
>-
>-// Save Done timestamp
>-if G8SR_DEBUG_TIMESTAMP
>-        s_memrealtime   s_g8sr_ts_save_d
>-        // SGPR SR memory offset : size(VGPR)
>-        get_vgpr_size_bytes(s_save_mem_offset)
>-        s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET
>-        s_waitcnt lgkmcnt(0)         //FIXME, will cause xnack??
>-        // Need reset rsrc2??
>-        s_mov_b32 m0, s_save_mem_offset
>-        s_mov_b32 s_save_buf_rsrc2,  0x1000000                                  //NUM_RECORDS in bytes
>-        s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0       glc:1
>-end
>-
>-
>     s_branch    L_END_PGM
> 
> 
>@@ -756,27 +469,6 @@
> 
> L_RESTORE:
>     /*      Setup Resource Contants    */
>-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
>-        //calculate wd_addr using absolute thread id
>-        v_readlane_b32 s_restore_tmp, v9, 0
>-        s_lshr_b32 s_restore_tmp, s_restore_tmp, 6
>-        s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE
>-        s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO
>-        s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI
>-        s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL
>-    else
>-    end
>-
>-if G8SR_DEBUG_TIMESTAMP
>-        s_memrealtime   s_g8sr_ts_restore_s
>-        s_waitcnt lgkmcnt(0)         //FIXME, will cause xnack??
>-        // tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case...
>-        s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0]
>-        s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1]   //backup ts to ttmp0/1, sicne exec will be finally restored..
>-end
>-
>-
>-
>     s_mov_b32       s_restore_buf_rsrc0,    s_restore_spi_init_lo                                                           //base_addr_lo
>     s_and_b32       s_restore_buf_rsrc1,    s_restore_spi_init_hi, 0x0000FFFF                                               //base_addr_hi
>     s_or_b32        s_restore_buf_rsrc1,    s_restore_buf_rsrc1,  S_RESTORE_BUF_RSRC_WORD1_STRIDE
>@@ -818,18 +510,12 @@
>     s_add_u32  s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes()            //FIXME, Check if offset overflow???
> 
> 
>-    if (SWIZZLE_EN)
>-        s_add_u32       s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0                       //FIXME need to use swizzle to enable bounds checking?
>-    else
>         s_mov_b32       s_restore_buf_rsrc2,  0x1000000                                     //NUM_RECORDS in bytes
>-    end
>     s_mov_b32       m0, 0x0                                                                 //lds_offset initial value = 0
> 
>   L_RESTORE_LDS_LOOP:
>-    if (SAVE_LDS)
>         buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1                    // first 64DW
>         buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256         // second 64DW
>-    end
>     s_add_u32       m0, m0, 256*2                                               // 128 DW
>     s_add_u32       s_restore_mem_offset, s_restore_mem_offset, 256*2           //mem offset increased by 128DW
>     s_cmp_lt_u32    m0, s_restore_alloc_size                                    //scc=(m0 < s_restore_alloc_size) ? 1 : 0
>@@ -848,40 +534,8 @@
>     s_add_u32       s_restore_alloc_size, s_restore_alloc_size, 1
>     s_lshl_b32      s_restore_alloc_size, s_restore_alloc_size, 2                           //Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
>     s_lshl_b32      s_restore_buf_rsrc2,  s_restore_alloc_size, 8                           //NUM_RECORDS in bytes (64 threads*4)
>-    if (SWIZZLE_EN)
>-        s_add_u32       s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0                       //FIXME need to use swizzle to enable bounds checking?
>-    else
>         s_mov_b32       s_restore_buf_rsrc2,  0x1000000                                     //NUM_RECORDS in bytes
>-    end
> 
>-if G8SR_VGPR_SR_IN_DWX4
>-     get_vgpr_size_bytes(s_restore_mem_offset)
>-     s_sub_u32         s_restore_mem_offset, s_restore_mem_offset, 256*4
>-
>-     // the const stride for DWx4 is 4*4 bytes
>-     s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
>-     s_or_b32  s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4  // const stride to 4*4 bytes
>-
>-     s_mov_b32         m0, s_restore_alloc_size
>-     s_set_gpr_idx_on  m0, 0x8    // Note.. This will change m0
>-
>-L_RESTORE_VGPR_LOOP:
>-     buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
>-     s_waitcnt vmcnt(0)
>-     s_sub_u32         m0, m0, 4
>-     v_mov_b32         v0, v0   // v[0+m0] = v0
>-     v_mov_b32         v1, v1
>-     v_mov_b32         v2, v2
>-     v_mov_b32         v3, v3
>-     s_sub_u32         s_restore_mem_offset, s_restore_mem_offset, 256*4
>-     s_cmp_eq_u32      m0, 0x8000
>-     s_cbranch_scc0    L_RESTORE_VGPR_LOOP
>-     s_set_gpr_idx_off
>-
>-     s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
>-     s_or_b32  s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE  // const stride to 4*4 bytes
>-
>-else
>     // VGPR load using dw burst
>     s_mov_b32       s_restore_mem_offset_save, s_restore_mem_offset     // restore start with v1, v0 will be the last
>     s_add_u32       s_restore_mem_offset, s_restore_mem_offset, 256*4
>@@ -890,14 +544,10 @@
>     s_add_u32       s_restore_alloc_size, s_restore_alloc_size, 0x8000                      //add 0x8000 since we compare m0 against it later
> 
>   L_RESTORE_VGPR_LOOP:
>-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
>-        tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-    else
>         buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
>         buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256
>         buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2
>         buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3
>-    end
>     s_waitcnt       vmcnt(0)                                                                //ensure data ready
>     v_mov_b32       v0, v0                                                                  //v[0+m0] = v0
>     v_mov_b32       v1, v1
>@@ -909,16 +559,10 @@
>     s_cbranch_scc1  L_RESTORE_VGPR_LOOP                                                     //VGPR restore (except v0) is complete?
>     s_set_gpr_idx_off
>                                                                                             /* VGPR restore on v0 */
>-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
>-        tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-    else
>         buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1
>         buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256
>         buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256*2
>         buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256*3
>-    end
>-
>-end
> 
>     /*          restore SGPRs       */
>     //////////////////////////////
>@@ -934,16 +578,8 @@
>     s_add_u32       s_restore_alloc_size, s_restore_alloc_size, 1
>     s_lshl_b32      s_restore_alloc_size, s_restore_alloc_size, 4                           //Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
> 
>-    if (SGPR_SAVE_USE_SQC)
>         s_lshl_b32      s_restore_buf_rsrc2,    s_restore_alloc_size, 2                     //NUM_RECORDS in bytes
>-    else
>-        s_lshl_b32      s_restore_buf_rsrc2,    s_restore_alloc_size, 8                     //NUM_RECORDS in bytes (64 threads)
>-    end
>-    if (SWIZZLE_EN)
>-        s_add_u32       s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0                       //FIXME need to use swizzle to enable bounds checking?
>-    else
>         s_mov_b32       s_restore_buf_rsrc2,  0x1000000                                     //NUM_RECORDS in bytes
>-    end
> 
>     /* If 112 SGPRs ar allocated, 4 sgprs are not used TBA(108,109),TMA(110,111),
>        However, we are safe to restore these 4 SGPRs anyway, since TBA,TMA will later be restored by HWREG
>@@ -972,12 +608,6 @@
>     //////////////////////////////
>   L_RESTORE_HWREG:
> 
>-
>-if G8SR_DEBUG_TIMESTAMP
>-      s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo
>-      s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi
>-end
>-
>     // HWREG SR memory offset : size(VGPR)+size(SGPR)
>     get_vgpr_size_bytes(s_restore_mem_offset)
>     get_sgpr_size_bytes(s_restore_tmp)
>@@ -985,11 +615,7 @@
> 
> 
>     s_mov_b32       s_restore_buf_rsrc2, 0x4                                                //NUM_RECORDS   in bytes
>-    if (SWIZZLE_EN)
>-        s_add_u32       s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0                       //FIXME need to use swizzle to enable bounds checking?
>-    else
>         s_mov_b32       s_restore_buf_rsrc2,  0x1000000                                     //NUM_RECORDS in bytes
>-    end
> 
>     read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset)                    //M0
>     read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset)             //PC
>@@ -1006,16 +632,6 @@
> 
>     s_waitcnt       lgkmcnt(0)                                                                                      //from now on, it is safe to restore STATUS and IB_STS
> 
>-    //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise:
>-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
>-        s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8            //pc[31:0]+8     //two back-to-back s_trap are used (first for save and second for restore)
>-        s_addc_u32  s_restore_pc_hi, s_restore_pc_hi, 0x0        //carry bit over
>-    end
>-    if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL))
>-        s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4            //pc[31:0]+4     // save is hack through s_trap but restore is normal
>-        s_addc_u32  s_restore_pc_hi, s_restore_pc_hi, 0x0        //carry bit over
>-    end
>-
>     s_mov_b32       m0,         s_restore_m0
>     s_mov_b32       exec_lo,    s_restore_exec_lo
>     s_mov_b32       exec_hi,    s_restore_exec_hi
>@@ -1048,11 +664,6 @@
> 
>     s_barrier                                                   //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time
> 
>-if G8SR_DEBUG_TIMESTAMP
>-    s_memrealtime s_g8sr_ts_restore_d
>-    s_waitcnt lgkmcnt(0)
>-end
>-
> //  s_rfe_b64 s_restore_pc_lo                                   //Return to the main shader program and resume execution
>     s_rfe_restore_b64  s_restore_pc_lo, s_restore_m0            // s_restore_m0[0] is used to set STATUS.inst_atc
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm	2019-08-31 15:01:11.853736168 -0500
>@@ -24,76 +24,9 @@
>  * PROJECT=greenland ./sp3 cwsr_trap_handler_gfx9.asm -hex tmp.hex
>  */
> 
>-/* HW (GFX9) source code for CWSR trap handler */
>-/* Version 18 + multiple trap handler */
>-
>-// this performance-optimal version was originally from Seven Xu at SRDC
>-
>-// Revison #18	 --...
>-/* Rev History
>-** #1. Branch from gc dv.   //gfxip/gfx9/main/src/test/suites/block/cs/sr/cs_trap_handler.sp3#1,#50, #51, #52-53(Skip, Already Fixed by PV), #54-56(merged),#57-58(mergerd, skiped-already fixed by PV)
>-** #4. SR Memory Layout:
>-**			 1. VGPR-SGPR-HWREG-{LDS}
>-**			 2. tba_hi.bits.26 - reconfigured as the first wave in tg bits, for defer Save LDS for a threadgroup.. performance concern..
>-** #5. Update: 1. Accurate g8sr_ts_save_d timestamp
>-** #6. Update: 1. Fix s_barrier usage; 2. VGPR s/r using swizzle buffer?(NoNeed, already matched the swizzle pattern, more investigation)
>-** #7. Update: 1. don't barrier if noLDS
>-** #8. Branch: 1. Branch to ver#0, which is very similar to gc dv version
>-**	       2. Fix SQ issue by s_sleep 2
>-** #9. Update: 1. Fix scc restore failed issue, restore wave_status at last
>-**	       2. optimize s_buffer save by burst 16sgprs...
>-** #10. Update 1. Optimize restore sgpr by busrt 16 sgprs.
>-** #11. Update 1. Add 2 more timestamp for debug version
>-** #12. Update 1. Add VGPR SR using DWx4, some case improve and some case drop performance
>-** #13. Integ  1. Always use MUBUF for PV trap shader...
>-** #14. Update 1. s_buffer_store soft clause...
>-** #15. Update 1. PERF - sclar write with glc:0/mtype0 to allow L2 combine. perf improvement a lot.
>-** #16. Update 1. PRRF - UNROLL LDS_DMA got 2500cycle save in IP tree
>-** #17. Update 1. FUNC - LDS_DMA has issues while ATC, replace with ds_read/buffer_store for save part[TODO restore part]
>-**	       2. PERF - Save LDS before save VGPR to cover LDS save long latency...
>-** #18. Update 1. FUNC - Implicitly estore STATUS.VCCZ, which is not writable by s_setreg_b32
>-**	       2. FUNC - Handle non-CWSR traps
>-*/
>-
>-var G8SR_WDMEM_HWREG_OFFSET = 0
>-var G8SR_WDMEM_SGPR_OFFSET  = 128  // in bytes
>-
>-// Keep definition same as the app shader, These 2 time stamps are part of the app shader... Should before any Save and after restore.
>-
>-var G8SR_DEBUG_TIMESTAMP = 0
>-var G8SR_DEBUG_TS_SAVE_D_OFFSET = 40*4	// ts_save_d timestamp offset relative to SGPR_SR_memory_offset
>-var s_g8sr_ts_save_s	= s[34:35]   // save start
>-var s_g8sr_ts_sq_save_msg  = s[36:37]	// The save shader send SAVEWAVE msg to spi
>-var s_g8sr_ts_spi_wrexec   = s[38:39]	// the SPI write the sr address to SQ
>-var s_g8sr_ts_save_d	= s[40:41]   // save end
>-var s_g8sr_ts_restore_s = s[42:43]   // restore start
>-var s_g8sr_ts_restore_d = s[44:45]   // restore end
>-
>-var G8SR_VGPR_SR_IN_DWX4 = 0
>-var G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4 = 0x00100000	 // DWx4 stride is 4*4Bytes
>-var G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4  = G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4
>-
>-
>-/*************************************************************************/
>-/*		    control on how to run the shader			 */
>-/*************************************************************************/
>-//any hack that needs to be made to run this code in EMU (either because various EMU code are not ready or no compute save & restore in EMU run)
>-var EMU_RUN_HACK		    =	0
>-var EMU_RUN_HACK_RESTORE_NORMAL	    =	0
>-var EMU_RUN_HACK_SAVE_NORMAL_EXIT   =	0
>-var EMU_RUN_HACK_SAVE_SINGLE_WAVE   =	0
>-var EMU_RUN_HACK_SAVE_FIRST_TIME    =	0		    //for interrupted restore in which the first save is through EMU_RUN_HACK
>-var SAVE_LDS			    =	1
>-var WG_BASE_ADDR_LO		    =	0x9000a000
>-var WG_BASE_ADDR_HI		    =	0x0
>-var WAVE_SPACE			    =	0x5000		    //memory size that each wave occupies in workgroup state mem
>-var CTX_SAVE_CONTROL		    =	0x0
>-var CTX_RESTORE_CONTROL		    =	CTX_SAVE_CONTROL
>-var SIM_RUN_HACK		    =	0		    //any hack that needs to be made to run this code in SIM (either because various RTL code are not ready or no compute save & restore in RTL run)
>-var SGPR_SAVE_USE_SQC		    =	1		    //use SQC D$ to do the write
>-var USE_MTBUF_INSTEAD_OF_MUBUF	    =	0		    //because TC EMU currently asserts on 0 of // overload DFMT field to carry 4 more bits of stride for MUBUF opcodes
>-var SWIZZLE_EN			    =	0		    //whether we use swizzled buffer addressing
> var ACK_SQC_STORE		    =	1		    //workaround for suspected SQC store bug causing incorrect stores under concurrency
>+var SAVE_AFTER_XNACK_ERROR	    =	1		    //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger
>+var SINGLE_STEP_MISSED_WORKAROUND   =	1		    //workaround for lost MODE.DEBUG_EN exception when SAVECTX raised
> 
> /**************************************************************************/
> /*			variables					  */
>@@ -107,6 +40,7 @@
> var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE    = 1
> var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT  = 3
> var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE   = 29
>+var SQ_WAVE_STATUS_ALLOW_REPLAY_MASK    = 0x400000
> 
> var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT	= 12
> var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE	= 9
>@@ -127,12 +61,15 @@
> var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT	=   11
> var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE	=   21
> var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK	=   0x800
>+var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK	=   0x10000000
> 
> var SQ_WAVE_IB_STS_RCNT_SHIFT		=   16			//FIXME
> var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT	=   15			//FIXME
> var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK	= 0x1F8000
> var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK_NEG	= 0x00007FFF	//FIXME
> 
>+var SQ_WAVE_MODE_DEBUG_EN_MASK		=   0x800
>+
> var SQ_BUF_RSRC_WORD1_ATC_SHIFT	    =	24
> var SQ_BUF_RSRC_WORD3_MTYPE_SHIFT   =	27
> 
>@@ -197,13 +134,15 @@
> var s_restore_spi_init_hi		    =	exec_hi
> 
> var s_restore_mem_offset	=   ttmp12
>+var s_restore_accvgpr_offset	=   ttmp13
> var s_restore_alloc_size	=   ttmp3
> var s_restore_tmp		=   ttmp2
> var s_restore_mem_offset_save	=   s_restore_tmp	//no conflict
>+var s_restore_accvgpr_offset_save = ttmp7
> 
> var s_restore_m0	    =	s_restore_alloc_size	//no conflict
> 
>-var s_restore_mode	    =	ttmp7
>+var s_restore_mode	    =	s_restore_accvgpr_offset_save
> 
> var s_restore_pc_lo	    =	ttmp0
> var s_restore_pc_hi	    =	ttmp1
>@@ -226,20 +165,11 @@
> /* Shader Main*/
> 
> shader main
>-  asic(GFX9)
>+  asic(DEFAULT)
>   type(CS)
> 
> 
>-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))		    //hack to use trap_id for determining save/restore
>-	//FIXME VCCZ un-init assertion s_getreg_b32	s_save_status, hwreg(HW_REG_STATUS)	    //save STATUS since we will change SCC
>-	s_and_b32 s_save_tmp, s_save_pc_hi, 0xffff0000		    //change SCC
>-	s_cmp_eq_u32 s_save_tmp, 0x007e0000			    //Save: trap_id = 0x7e. Restore: trap_id = 0x7f.
>-	s_cbranch_scc0 L_JUMP_TO_RESTORE			    //do not need to recover STATUS here  since we are going to RESTORE
>-	//FIXME	 s_setreg_b32	hwreg(HW_REG_STATUS),	s_save_status	    //need to recover STATUS since we are going to SAVE
>-	s_branch L_SKIP_RESTORE					    //NOT restore, SAVE actually
>-    else
> 	s_branch L_SKIP_RESTORE					    //NOT restore. might be a regular trap or save
>-    end
> 
> L_JUMP_TO_RESTORE:
>     s_branch L_RESTORE						    //restore
>@@ -248,12 +178,29 @@
> 
>     s_getreg_b32    s_save_status, hwreg(HW_REG_STATUS)				    //save STATUS since we will change SCC
>     s_andn2_b32	    s_save_status, s_save_status, SQ_WAVE_STATUS_SPI_PRIO_MASK	    //check whether this is for save
>+
>+if SINGLE_STEP_MISSED_WORKAROUND
>+    // No single step exceptions if MODE.DEBUG_EN=0.
>+    s_getreg_b32    ttmp2, hwreg(HW_REG_MODE)
>+    s_and_b32       ttmp2, ttmp2, SQ_WAVE_MODE_DEBUG_EN_MASK
>+    s_cbranch_scc0  L_NO_SINGLE_STEP_WORKAROUND
>+
>+    // Second-level trap already handled exception if STATUS.HALT=1.
>+    s_and_b32       ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK
>+
>+    // Prioritize single step exception over context save.
>+    // Second-level trap will halt wave and RFE, re-entering for SAVECTX.
>+    s_cbranch_scc0  L_FETCH_2ND_TRAP
>+
>+L_NO_SINGLE_STEP_WORKAROUND:
>+end
>+
>     s_getreg_b32    s_save_trapsts, hwreg(HW_REG_TRAPSTS)
>     s_and_b32       ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK    //check whether this is for save
>     s_cbranch_scc1  L_SAVE					//this is the operation for save
> 
>     // *********    Handle non-CWSR traps	*******************
>-if (!EMU_RUN_HACK)
>+
>     // Illegal instruction is a non-maskable exception which blocks context save.
>     // Halt the wavefront and return from the trap.
>     s_and_b32       ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK
>@@ -330,7 +277,7 @@
>     set_status_without_spi_prio(s_save_status, ttmp2)
> 
>     s_rfe_b64       [ttmp0, ttmp1]
>-end
>+
>     // *********	End handling of non-CWSR traps	 *******************
> 
> /**************************************************************************/
>@@ -338,12 +285,6 @@
> /**************************************************************************/
> 
> L_SAVE:
>-
>-if G8SR_DEBUG_TIMESTAMP
>-	s_memrealtime	s_g8sr_ts_save_s
>-	s_waitcnt lgkmcnt(0)	     //FIXME, will cause xnack??
>-end
>-
>     s_and_b32	    s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
> 
>     s_mov_b32	    s_save_tmp, 0							    //clear saveCtx bit
>@@ -365,16 +306,7 @@
>     s_mov_b32	    s_save_exec_hi, exec_hi
>     s_mov_b64	    exec,   0x0								    //clear EXEC to get ready to receive
> 
>-if G8SR_DEBUG_TIMESTAMP
>-	s_memrealtime  s_g8sr_ts_sq_save_msg
>-	s_waitcnt lgkmcnt(0)
>-end
>-
>-    if (EMU_RUN_HACK)
>-
>-    else
> 	s_sendmsg   sendmsg(MSG_SAVEWAVE)  //send SPI a message and wait for SPI's write to EXEC
>-    end
> 
>     // Set SPI_PRIO=2 to avoid starving instruction fetch in the waves we're waiting for.
>     s_or_b32 s_save_tmp, s_save_status, (2 << SQ_WAVE_STATUS_SPI_PRIO_SHIFT)
>@@ -383,33 +315,7 @@
>   L_SLEEP:
>     s_sleep 0x2		       // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0
> 
>-    if (EMU_RUN_HACK)
>-
>-    else
> 	s_cbranch_execz L_SLEEP
>-    end
>-
>-if G8SR_DEBUG_TIMESTAMP
>-	s_memrealtime  s_g8sr_ts_spi_wrexec
>-	s_waitcnt lgkmcnt(0)
>-end
>-
>-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_SINGLE_WAVE))
>-	//calculate wd_addr using absolute thread id
>-	v_readlane_b32 s_save_tmp, v9, 0
>-	s_lshr_b32 s_save_tmp, s_save_tmp, 6
>-	s_mul_i32 s_save_tmp, s_save_tmp, WAVE_SPACE
>-	s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
>-	s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
>-	s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
>-    else
>-    end
>-    if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_SINGLE_WAVE))
>-	s_add_i32 s_save_spi_init_lo, s_save_tmp, WG_BASE_ADDR_LO
>-	s_mov_b32 s_save_spi_init_hi, WG_BASE_ADDR_HI
>-	s_and_b32 s_save_spi_init_hi, s_save_spi_init_hi, CTX_SAVE_CONTROL
>-    else
>-    end
> 
>     // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic
>     // ttmp SR memory offset : size(VGPR)+size(SGPR)+0x40
>@@ -459,20 +365,10 @@
> 
> 
>     s_mov_b32	    s_save_buf_rsrc2, 0x4				//NUM_RECORDS	in bytes
>-    if (SWIZZLE_EN)
>-	s_add_u32	s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
>-    else
> 	s_mov_b32	s_save_buf_rsrc2,  0x1000000				    //NUM_RECORDS in bytes
>-    end
> 
> 
>     write_hwreg_to_mem(s_save_m0, s_save_buf_rsrc0, s_save_mem_offset)			//M0
>-
>-    if ((EMU_RUN_HACK) && (EMU_RUN_HACK_SAVE_FIRST_TIME))
>-	s_add_u32 s_save_pc_lo, s_save_pc_lo, 4		    //pc[31:0]+4
>-	s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0	    //carry bit over
>-    end
>-
>     write_hwreg_to_mem(s_save_pc_lo, s_save_buf_rsrc0, s_save_mem_offset)		    //PC
>     write_hwreg_to_mem(s_save_pc_hi, s_save_buf_rsrc0, s_save_mem_offset)
>     write_hwreg_to_mem(s_save_exec_lo, s_save_buf_rsrc0, s_save_mem_offset)		//EXEC
>@@ -510,17 +406,9 @@
>     s_add_u32	    s_save_alloc_size, s_save_alloc_size, 1
>     s_lshl_b32	    s_save_alloc_size, s_save_alloc_size, 4			    //Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
> 
>-    if (SGPR_SAVE_USE_SQC)
> 	s_lshl_b32	s_save_buf_rsrc2,   s_save_alloc_size, 2		    //NUM_RECORDS in bytes
>-    else
>-	s_lshl_b32	s_save_buf_rsrc2,   s_save_alloc_size, 8		    //NUM_RECORDS in bytes (64 threads)
>-    end
> 
>-    if (SWIZZLE_EN)
>-	s_add_u32	s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
>-    else
> 	s_mov_b32	s_save_buf_rsrc2,  0x1000000				    //NUM_RECORDS in bytes
>-    end
> 
> 
>     // backup s_save_buf_rsrc0,1 to s_save_pc_lo/hi, since write_16sgpr_to_mem function will change the rsrc0
>@@ -563,30 +451,25 @@
>     s_mov_b32	    xnack_mask_lo, 0x0
>     s_mov_b32	    xnack_mask_hi, 0x0
> 
>-    if (SWIZZLE_EN)
>-	s_add_u32	s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
>-    else
> 	s_mov_b32	s_save_buf_rsrc2,  0x1000000				    //NUM_RECORDS in bytes
>-    end
> 
> 
>     // VGPR Allocated in 4-GPR granularity
> 
>-if G8SR_VGPR_SR_IN_DWX4
>-	// the const stride for DWx4 is 4*4 bytes
>-	s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
>-	s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4  // const stride to 4*4 bytes
>-
>-	buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>-
>-	s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
>-	s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE  // reset const stride to 4 bytes
>-else
>+if SAVE_AFTER_XNACK_ERROR
>+	check_if_tcp_store_ok()
>+	s_cbranch_scc1 L_SAVE_FIRST_VGPRS_WITH_TCP
>+
>+	write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
>+	s_branch L_SAVE_LDS
>+
>+L_SAVE_FIRST_VGPRS_WITH_TCP:
>+end
>+
> 	buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
> 	buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256
> 	buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*2
> 	buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*3
>-end
> 
> 
> 
>@@ -621,66 +504,34 @@
>     s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes()
> 
> 
>-    if (SWIZZLE_EN)
>-	s_add_u32	s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0	      //FIXME need to use swizzle to enable bounds checking?
>-    else
> 	s_mov_b32	s_save_buf_rsrc2,  0x1000000		      //NUM_RECORDS in bytes
>-    end
> 
>     s_mov_b32	    m0, 0x0						  //lds_offset initial value = 0
> 
> 
>-var LDS_DMA_ENABLE = 0
>-var UNROLL = 0
>-if UNROLL==0 && LDS_DMA_ENABLE==1
>-	s_mov_b32  s3, 256*2
>-	s_nop 0
>-	s_nop 0
>-	s_nop 0
>-  L_SAVE_LDS_LOOP:
>-	//TODO: looks the 2 buffer_store/load clause for s/r will hurt performance.???
>-    if (SAVE_LDS)     //SPI always alloc LDS space in 128DW granularity
>-	    buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1		// first 64DW
>-	    buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256 // second 64DW
>-    end
>-
>-    s_add_u32	    m0, m0, s3						//every buffer_store_lds does 256 bytes
>-    s_add_u32	    s_save_mem_offset, s_save_mem_offset, s3				//mem offset increased by 256 bytes
>-    s_cmp_lt_u32    m0, s_save_alloc_size						//scc=(m0 < s_save_alloc_size) ? 1 : 0
>-    s_cbranch_scc1  L_SAVE_LDS_LOOP							//LDS save is complete?
>-
>-elsif LDS_DMA_ENABLE==1 && UNROLL==1 // UNROOL	, has ichace miss
>-      // store from higest LDS address to lowest
>-      s_mov_b32	 s3, 256*2
>-      s_sub_u32	 m0, s_save_alloc_size, s3
>-      s_add_u32 s_save_mem_offset, s_save_mem_offset, m0
>-      s_lshr_b32 s_save_alloc_size, s_save_alloc_size, 9   // how many 128 trunks...
>-      s_sub_u32 s_save_alloc_size, 128, s_save_alloc_size   // store from higheset addr to lowest
>-      s_mul_i32 s_save_alloc_size, s_save_alloc_size, 6*4   // PC offset increment,  each LDS save block cost 6*4 Bytes instruction
>-      s_add_u32 s_save_alloc_size, s_save_alloc_size, 3*4   //2is the below 2 inst...//s_addc and s_setpc
>-      s_nop 0
>-      s_nop 0
>-      s_nop 0	//pad 3 dw to let LDS_DMA align with 64Bytes
>-      s_getpc_b64 s[0:1]			      // reuse s[0:1], since s[0:1] already saved
>-      s_add_u32	  s0, s0,s_save_alloc_size
>-      s_addc_u32  s1, s1, 0
>-      s_setpc_b64 s[0:1]
>-
>-
>-       for var i =0; i< 128; i++
>-	    // be careful to make here a 64Byte aligned address, which could improve performance...
>-	    buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:0		// first 64DW
>-	    buffer_store_lds_dword s_save_buf_rsrc0, s_save_mem_offset lds:1 offset:256		  // second 64DW
>-
>-	if i!=127
>-	s_sub_u32  m0, m0, s3	   // use a sgpr to shrink 2DW-inst to 1DW inst to improve performance , i.e.  pack more LDS_DMA inst to one Cacheline
>-	    s_sub_u32  s_save_mem_offset, s_save_mem_offset,  s3
>-	    end
>-       end
>-
>-else   // BUFFER_STORE
>       v_mbcnt_lo_u32_b32 v2, 0xffffffff, 0x0
>       v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2	// tid
>+
>+if SAVE_AFTER_XNACK_ERROR
>+	check_if_tcp_store_ok()
>+	s_cbranch_scc1 L_SAVE_LDS_WITH_TCP
>+
>+	v_lshlrev_b32 v2, 2, v3
>+L_SAVE_LDS_LOOP_SQC:
>+	ds_read2_b32 v[0:1], v2 offset0:0 offset1:0x40
>+	s_waitcnt lgkmcnt(0)
>+
>+	write_vgprs_to_mem_with_sqc(v0, 2, s_save_buf_rsrc0, s_save_mem_offset)
>+
>+	v_add_u32 v2, 0x200, v2
>+	v_cmp_lt_u32 vcc[0:1], v2, s_save_alloc_size
>+	s_cbranch_vccnz L_SAVE_LDS_LOOP_SQC
>+
>+	s_branch L_SAVE_LDS_DONE
>+
>+L_SAVE_LDS_WITH_TCP:
>+end
>+
>       v_mul_i32_i24 v2, v3, 8	// tid*8
>       v_mov_b32 v3, 256*2
>       s_mov_b32 m0, 0x10000
>@@ -701,8 +552,6 @@
>       // restore rsrc3
>       s_mov_b32 s_save_buf_rsrc3, s0
> 
>-end
>-
> L_SAVE_LDS_DONE:
> 
> 
>@@ -720,44 +569,9 @@
>     s_add_u32	    s_save_alloc_size, s_save_alloc_size, 1
>     s_lshl_b32	    s_save_alloc_size, s_save_alloc_size, 2			    //Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)	  //FIXME for GFX, zero is possible
>     s_lshl_b32	    s_save_buf_rsrc2,  s_save_alloc_size, 8			    //NUM_RECORDS in bytes (64 threads*4)
>-    if (SWIZZLE_EN)
>-	s_add_u32	s_save_buf_rsrc2, s_save_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
>-    else
> 	s_mov_b32	s_save_buf_rsrc2,  0x1000000				    //NUM_RECORDS in bytes
>-    end
>-
>-
>-    // VGPR Allocated in 4-GPR granularity
> 
>-if G8SR_VGPR_SR_IN_DWX4
>-	// the const stride for DWx4 is 4*4 bytes
>-	s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
>-	s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, G8SR_SAVE_BUF_RSRC_WORD1_STRIDE_DWx4  // const stride to 4*4 bytes
>-
>-	s_mov_b32	  m0, 4	    // skip first 4 VGPRs
>-	s_cmp_lt_u32	  m0, s_save_alloc_size
>-	s_cbranch_scc0	  L_SAVE_VGPR_LOOP_END	    // no more vgprs
>-
>-	s_set_gpr_idx_on  m0, 0x1   // This will change M0
>-	s_add_u32	  s_save_alloc_size, s_save_alloc_size, 0x1000	// because above inst change m0
>-L_SAVE_VGPR_LOOP:
>-	v_mov_b32	  v0, v0   // v0 = v[0+m0]
>-	v_mov_b32	  v1, v1
>-	v_mov_b32	  v2, v2
>-	v_mov_b32	  v3, v3
>-
>-
>-	buffer_store_dwordx4 v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>-	s_add_u32	  m0, m0, 4
>-	s_add_u32	  s_save_mem_offset, s_save_mem_offset, 256*4
>-	s_cmp_lt_u32	  m0, s_save_alloc_size
>-    s_cbranch_scc1  L_SAVE_VGPR_LOOP						    //VGPR save is complete?
>-    s_set_gpr_idx_off
>-L_SAVE_VGPR_LOOP_END:
> 
>-	s_and_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
>-	s_or_b32  s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE  // reset const stride to 4 bytes
>-else
>     // VGPR store using dw burst
>     s_mov_b32	      m0, 0x4	//VGPR initial index value =0
>     s_cmp_lt_u32      m0, s_save_alloc_size
>@@ -767,57 +581,82 @@
>     s_set_gpr_idx_on	m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1
>     s_add_u32	    s_save_alloc_size, s_save_alloc_size, 0x1000		    //add 0x1000 since we compare m0 against it later
> 
>+if SAVE_AFTER_XNACK_ERROR
>+	check_if_tcp_store_ok()
>+	s_cbranch_scc1 L_SAVE_VGPR_LOOP
>+
>+L_SAVE_VGPR_LOOP_SQC:
>+	write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
>+
>+	s_add_u32 m0, m0, 4
>+	s_cmp_lt_u32 m0, s_save_alloc_size
>+	s_cbranch_scc1 L_SAVE_VGPR_LOOP_SQC
>+
>+	s_set_gpr_idx_off
>+	s_branch L_SAVE_VGPR_END
>+end
>+
>   L_SAVE_VGPR_LOOP:
>     v_mov_b32	    v0, v0		//v0 = v[0+m0]
>     v_mov_b32	    v1, v1		//v0 = v[0+m0]
>     v_mov_b32	    v2, v2		//v0 = v[0+m0]
>     v_mov_b32	    v3, v3		//v0 = v[0+m0]
> 
>-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
>-	tbuffer_store_format_x v0, v0, s_save_buf_rsrc0, s_save_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-    else
> 	buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
> 	buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256
> 	buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*2
> 	buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1  offset:256*3
>-    end
> 
>     s_add_u32	    m0, m0, 4							    //next vgpr index
>     s_add_u32	    s_save_mem_offset, s_save_mem_offset, 256*4			    //every buffer_store_dword does 256 bytes
>     s_cmp_lt_u32    m0, s_save_alloc_size					    //scc = (m0 < s_save_alloc_size) ? 1 : 0
>     s_cbranch_scc1  L_SAVE_VGPR_LOOP						    //VGPR save is complete?
>     s_set_gpr_idx_off
>-end
> 
> L_SAVE_VGPR_END:
> 
>+if ASIC_TARGET_ARCTURUS
>+    // Save ACC VGPRs
>+    s_mov_b32 m0, 0x0 //VGPR initial index value =0
>+    s_set_gpr_idx_on m0, 0x1 //M0[7:0] = M0[7:0] and M0[15:12] = 0x1
> 
>+if SAVE_AFTER_XNACK_ERROR
>+    check_if_tcp_store_ok()
>+    s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP
> 
>+L_SAVE_ACCVGPR_LOOP_SQC:
>+    for var vgpr = 0; vgpr < 4; ++ vgpr
>+        v_accvgpr_read v[vgpr], acc[vgpr]  // v[N] = acc[N+m0]
>+    end
>+
>+    write_vgprs_to_mem_with_sqc(v0, 4, s_save_buf_rsrc0, s_save_mem_offset)
> 
>+    s_add_u32 m0, m0, 4
>+    s_cmp_lt_u32 m0, s_save_alloc_size
>+    s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP_SQC
> 
>+    s_set_gpr_idx_off
>+    s_branch L_SAVE_ACCVGPR_END
>+end
> 
>-    /*	   S_PGM_END_SAVED  */				    //FIXME  graphics ONLY
>-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_SAVE_NORMAL_EXIT))
>-	s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff    //pc[47:32]
>-	s_add_u32 s_save_pc_lo, s_save_pc_lo, 4		    //pc[31:0]+4
>-	s_addc_u32 s_save_pc_hi, s_save_pc_hi, 0x0	    //carry bit over
>-	s_rfe_b64 s_save_pc_lo				    //Return to the main shader program
>-    else
>+L_SAVE_ACCVGPR_LOOP:
>+    for var vgpr = 0; vgpr < 4; ++ vgpr
>+        v_accvgpr_read v[vgpr], acc[vgpr]  // v[N] = acc[N+m0]
>     end
> 
>-// Save Done timestamp
>-if G8SR_DEBUG_TIMESTAMP
>-	s_memrealtime	s_g8sr_ts_save_d
>-	// SGPR SR memory offset : size(VGPR)
>-	get_vgpr_size_bytes(s_save_mem_offset)
>-	s_add_u32 s_save_mem_offset, s_save_mem_offset, G8SR_DEBUG_TS_SAVE_D_OFFSET
>-	s_waitcnt lgkmcnt(0)	     //FIXME, will cause xnack??
>-	// Need reset rsrc2??
>-	s_mov_b32 m0, s_save_mem_offset
>-	s_mov_b32 s_save_buf_rsrc2,  0x1000000					//NUM_RECORDS in bytes
>-	s_buffer_store_dwordx2 s_g8sr_ts_save_d, s_save_buf_rsrc0, m0	    glc:1
>-end
>+    buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
>+    buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
>+    buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
>+    buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
>+
>+    s_add_u32 m0, m0, 4
>+    s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4
>+    s_cmp_lt_u32 m0, s_save_alloc_size
>+    s_cbranch_scc1 L_SAVE_ACCVGPR_LOOP
>+    s_set_gpr_idx_off
> 
>+L_SAVE_ACCVGPR_END:
>+end
> 
>     s_branch	L_END_PGM
> 
>@@ -829,27 +668,6 @@
> 
> L_RESTORE:
>     /*	    Setup Resource Contants    */
>-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
>-	//calculate wd_addr using absolute thread id
>-	v_readlane_b32 s_restore_tmp, v9, 0
>-	s_lshr_b32 s_restore_tmp, s_restore_tmp, 6
>-	s_mul_i32 s_restore_tmp, s_restore_tmp, WAVE_SPACE
>-	s_add_i32 s_restore_spi_init_lo, s_restore_tmp, WG_BASE_ADDR_LO
>-	s_mov_b32 s_restore_spi_init_hi, WG_BASE_ADDR_HI
>-	s_and_b32 s_restore_spi_init_hi, s_restore_spi_init_hi, CTX_RESTORE_CONTROL
>-    else
>-    end
>-
>-if G8SR_DEBUG_TIMESTAMP
>-	s_memrealtime	s_g8sr_ts_restore_s
>-	s_waitcnt lgkmcnt(0)	     //FIXME, will cause xnack??
>-	// tma_lo/hi are sgpr 110, 111, which will not used for 112 SGPR allocated case...
>-	s_mov_b32 s_restore_pc_lo, s_g8sr_ts_restore_s[0]
>-	s_mov_b32 s_restore_pc_hi, s_g8sr_ts_restore_s[1]   //backup ts to ttmp0/1, sicne exec will be finally restored..
>-end
>-
>-
>-
>     s_mov_b32	    s_restore_buf_rsrc0,    s_restore_spi_init_lo							    //base_addr_lo
>     s_and_b32	    s_restore_buf_rsrc1,    s_restore_spi_init_hi, 0x0000FFFF						    //base_addr_hi
>     s_or_b32	    s_restore_buf_rsrc1,    s_restore_buf_rsrc1,  S_RESTORE_BUF_RSRC_WORD1_STRIDE
>@@ -891,18 +709,12 @@
>     s_add_u32  s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes()	     //FIXME, Check if offset overflow???
> 
> 
>-    if (SWIZZLE_EN)
>-	s_add_u32	s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
>-    else
> 	s_mov_b32	s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
>-    end
>     s_mov_b32	    m0, 0x0								    //lds_offset initial value = 0
> 
>   L_RESTORE_LDS_LOOP:
>-    if (SAVE_LDS)
> 	buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1		       // first 64DW
> 	buffer_load_dword   v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset lds:1 offset:256	       // second 64DW
>-    end
>     s_add_u32	    m0, m0, 256*2						// 128 DW
>     s_add_u32	    s_restore_mem_offset, s_restore_mem_offset, 256*2		//mem offset increased by 128DW
>     s_cmp_lt_u32    m0, s_restore_alloc_size					//scc=(m0 < s_restore_alloc_size) ? 1 : 0
>@@ -921,56 +733,43 @@
>     s_add_u32	    s_restore_alloc_size, s_restore_alloc_size, 1
>     s_lshl_b32	    s_restore_alloc_size, s_restore_alloc_size, 2			    //Number of VGPRs = (vgpr_size + 1) * 4    (non-zero value)
>     s_lshl_b32	    s_restore_buf_rsrc2,  s_restore_alloc_size, 8			    //NUM_RECORDS in bytes (64 threads*4)
>-    if (SWIZZLE_EN)
>-	s_add_u32	s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
>-    else
>-	s_mov_b32	s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
>-    end
> 
>-if G8SR_VGPR_SR_IN_DWX4
>-     get_vgpr_size_bytes(s_restore_mem_offset)
>-     s_sub_u32	       s_restore_mem_offset, s_restore_mem_offset, 256*4
>-
>-     // the const stride for DWx4 is 4*4 bytes
>-     s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
>-     s_or_b32  s_restore_buf_rsrc1, s_restore_buf_rsrc1, G8SR_RESTORE_BUF_RSRC_WORD1_STRIDE_DWx4  // const stride to 4*4 bytes
>-
>-     s_mov_b32	       m0, s_restore_alloc_size
>-     s_set_gpr_idx_on  m0, 0x8	  // Note.. This will change m0
>-
>-L_RESTORE_VGPR_LOOP:
>-     buffer_load_dwordx4 v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
>-     s_waitcnt vmcnt(0)
>-     s_sub_u32	       m0, m0, 4
>-     v_mov_b32	       v0, v0	// v[0+m0] = v0
>-     v_mov_b32	       v1, v1
>-     v_mov_b32	       v2, v2
>-     v_mov_b32	       v3, v3
>-     s_sub_u32	       s_restore_mem_offset, s_restore_mem_offset, 256*4
>-     s_cmp_eq_u32      m0, 0x8000
>-     s_cbranch_scc0    L_RESTORE_VGPR_LOOP
>-     s_set_gpr_idx_off
>+if ASIC_TARGET_ARCTURUS
>+    s_mov_b32	    s_restore_accvgpr_offset, s_restore_buf_rsrc2                           //ACC VGPRs at end of VGPRs
>+end
> 
>-     s_and_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, 0x0000FFFF   // reset const stride to 0
>-     s_or_b32  s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE  // const stride to 4*4 bytes
>+	s_mov_b32	s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
> 
>-else
>     // VGPR load using dw burst
>     s_mov_b32	    s_restore_mem_offset_save, s_restore_mem_offset	// restore start with v1, v0 will be the last
>     s_add_u32	    s_restore_mem_offset, s_restore_mem_offset, 256*4
>+if ASIC_TARGET_ARCTURUS
>+    s_mov_b32	    s_restore_accvgpr_offset_save, s_restore_accvgpr_offset
>+    s_add_u32	    s_restore_accvgpr_offset, s_restore_accvgpr_offset, 256*4
>+end
>     s_mov_b32	    m0, 4				//VGPR initial index value = 1
>     s_set_gpr_idx_on  m0, 0x8			    //M0[7:0] = M0[7:0] and M0[15:12] = 0x8
>     s_add_u32	    s_restore_alloc_size, s_restore_alloc_size, 0x8000			    //add 0x8000 since we compare m0 against it later
> 
>   L_RESTORE_VGPR_LOOP:
>-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
>-	tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-    else
>+
>+if ASIC_TARGET_ARCTURUS
>+	buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1
>+	buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256
>+	buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256*2
>+	buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset slc:1 glc:1 offset:256*3
>+	s_add_u32 s_restore_accvgpr_offset, s_restore_accvgpr_offset, 256*4
>+	s_waitcnt vmcnt(0)
>+
>+	for var vgpr = 0; vgpr < 4; ++ vgpr
>+		v_accvgpr_write acc[vgpr], v[vgpr]
>+	end
>+end
>+
> 	buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
> 	buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256
> 	buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*2
> 	buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3
>-    end
>     s_waitcnt	    vmcnt(0)								    //ensure data ready
>     v_mov_b32	    v0, v0								    //v[0+m0] = v0
>     v_mov_b32	    v1, v1
>@@ -982,16 +781,22 @@
>     s_cbranch_scc1  L_RESTORE_VGPR_LOOP							    //VGPR restore (except v0) is complete?
>     s_set_gpr_idx_off
> 											    /* VGPR restore on v0 */
>-    if(USE_MTBUF_INSTEAD_OF_MUBUF)
>-	tbuffer_load_format_x v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save format:BUF_NUM_FORMAT_FLOAT format: BUF_DATA_FORMAT_32 slc:1 glc:1
>-    else
>+if ASIC_TARGET_ARCTURUS
>+	buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1
>+	buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256
>+	buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256*2
>+	buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_accvgpr_offset_save slc:1 glc:1 offset:256*3
>+	s_waitcnt vmcnt(0)
>+
>+	for var vgpr = 0; vgpr < 4; ++ vgpr
>+		v_accvgpr_write acc[vgpr], v[vgpr]
>+	end
>+end
>+
> 	buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1
> 	buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256
> 	buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256*2
> 	buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save    slc:1 glc:1 offset:256*3
>-    end
>-
>-end
> 
>     /*		restore SGPRs	    */
>     //////////////////////////////
>@@ -1007,16 +812,8 @@
>     s_add_u32	    s_restore_alloc_size, s_restore_alloc_size, 1
>     s_lshl_b32	    s_restore_alloc_size, s_restore_alloc_size, 4			    //Number of SGPRs = (sgpr_size + 1) * 16   (non-zero value)
> 
>-    if (SGPR_SAVE_USE_SQC)
> 	s_lshl_b32	s_restore_buf_rsrc2,	s_restore_alloc_size, 2			    //NUM_RECORDS in bytes
>-    else
>-	s_lshl_b32	s_restore_buf_rsrc2,	s_restore_alloc_size, 8			    //NUM_RECORDS in bytes (64 threads)
>-    end
>-    if (SWIZZLE_EN)
>-	s_add_u32	s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
>-    else
> 	s_mov_b32	s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
>-    end
> 
>     s_mov_b32 m0, s_restore_alloc_size
> 
>@@ -1044,11 +841,6 @@
>   L_RESTORE_HWREG:
> 
> 
>-if G8SR_DEBUG_TIMESTAMP
>-      s_mov_b32 s_g8sr_ts_restore_s[0], s_restore_pc_lo
>-      s_mov_b32 s_g8sr_ts_restore_s[1], s_restore_pc_hi
>-end
>-
>     // HWREG SR memory offset : size(VGPR)+size(SGPR)
>     get_vgpr_size_bytes(s_restore_mem_offset)
>     get_sgpr_size_bytes(s_restore_tmp)
>@@ -1056,11 +848,7 @@
> 
> 
>     s_mov_b32	    s_restore_buf_rsrc2, 0x4						    //NUM_RECORDS   in bytes
>-    if (SWIZZLE_EN)
>-	s_add_u32	s_restore_buf_rsrc2, s_restore_buf_rsrc2, 0x0			    //FIXME need to use swizzle to enable bounds checking?
>-    else
> 	s_mov_b32	s_restore_buf_rsrc2,  0x1000000					    //NUM_RECORDS in bytes
>-    end
> 
>     read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset)		    //M0
>     read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset)		//PC
>@@ -1075,16 +863,6 @@
> 
>     s_waitcnt	    lgkmcnt(0)											    //from now on, it is safe to restore STATUS and IB_STS
> 
>-    //for normal save & restore, the saved PC points to the next inst to execute, no adjustment needs to be made, otherwise:
>-    if ((EMU_RUN_HACK) && (!EMU_RUN_HACK_RESTORE_NORMAL))
>-	s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 8		 //pc[31:0]+8	  //two back-to-back s_trap are used (first for save and second for restore)
>-	s_addc_u32  s_restore_pc_hi, s_restore_pc_hi, 0x0	 //carry bit over
>-    end
>-    if ((EMU_RUN_HACK) && (EMU_RUN_HACK_RESTORE_NORMAL))
>-	s_add_u32 s_restore_pc_lo, s_restore_pc_lo, 4		 //pc[31:0]+4	  // save is hack through s_trap but restore is normal
>-	s_addc_u32  s_restore_pc_hi, s_restore_pc_hi, 0x0	 //carry bit over
>-    end
>-
>     s_mov_b32	    m0,		s_restore_m0
>     s_mov_b32	    exec_lo,	s_restore_exec_lo
>     s_mov_b32	    exec_hi,	s_restore_exec_hi
>@@ -1131,11 +909,6 @@
> 
>     s_barrier							//barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time
> 
>-if G8SR_DEBUG_TIMESTAMP
>-    s_memrealtime s_g8sr_ts_restore_d
>-    s_waitcnt lgkmcnt(0)
>-end
>-
> //  s_rfe_b64 s_restore_pc_lo					//Return to the main shader program and resume execution
>     s_rfe_restore_b64  s_restore_pc_lo, s_restore_m0		// s_restore_m0[0] is used to set STATUS.inst_atc
> 
>@@ -1190,7 +963,39 @@
>     s_sub_u32	    s_mem_offset, s_mem_offset, 4*16
> end
> 
>+function check_if_tcp_store_ok
>+	// If STATUS.ALLOW_REPLAY=0 and TRAPSTS.XNACK_ERROR=1 then TCP stores will fail.
>+	s_and_b32 s_save_tmp, s_save_status, SQ_WAVE_STATUS_ALLOW_REPLAY_MASK
>+	s_cbranch_scc1 L_TCP_STORE_CHECK_DONE
>+
>+	s_getreg_b32 s_save_tmp, hwreg(HW_REG_TRAPSTS)
>+	s_andn2_b32 s_save_tmp, SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK, s_save_tmp
>+
>+L_TCP_STORE_CHECK_DONE:
>+end
>+
>+function write_vgpr_to_mem_with_sqc(v, s_rsrc, s_mem_offset)
>+	s_mov_b32 s4, 0
> 
>+L_WRITE_VGPR_LANE_LOOP:
>+	for var lane = 0; lane < 4; ++ lane
>+		v_readlane_b32 s[lane], v, s4
>+		s_add_u32 s4, s4, 1
>+	end
>+
>+	s_buffer_store_dwordx4 s[0:3], s_rsrc, s_mem_offset glc:1
>+	ack_sqc_store_workaround()
>+
>+	s_add_u32 s_mem_offset, s_mem_offset, 0x10
>+	s_cmp_eq_u32 s4, 0x40
>+	s_cbranch_scc0 L_WRITE_VGPR_LANE_LOOP
>+end
>+
>+function write_vgprs_to_mem_with_sqc(v, n_vgprs, s_rsrc, s_mem_offset)
>+	for var vgpr = 0; vgpr < n_vgprs; ++ vgpr
>+		write_vgpr_to_mem_with_sqc(v[vgpr], s_rsrc, s_mem_offset)
>+	end
>+end
> 
> function get_lds_size_bytes(s_lds_size_byte)
>     // SQ LDS granularity is 64DW, while PGM_RSRC2.lds_size is in granularity 128DW
>@@ -1202,6 +1007,10 @@
>     s_getreg_b32   s_vgpr_size_byte, hwreg(HW_REG_GPR_ALLOC,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT,SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE)	 //vpgr_size
>     s_add_u32	   s_vgpr_size_byte, s_vgpr_size_byte, 1
>     s_lshl_b32	   s_vgpr_size_byte, s_vgpr_size_byte, (2+8) //Number of VGPRs = (vgpr_size + 1) * 4 * 64 * 4	(non-zero value)   //FIXME for GFX, zero is possible
>+
>+if ASIC_TARGET_ARCTURUS
>+    s_lshl_b32     s_vgpr_size_byte, s_vgpr_size_byte, 1  // Double size for ACC VGPRs
>+end
> end
> 
> function get_sgpr_size_bytes(s_sgpr_size_byte)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h	2019-08-31 15:01:11.852736168 -0500
>@@ -274,154 +274,227 @@
> 
> 
> static const uint32_t cwsr_trap_gfx9_hex[] = {
>-	0xbf820001, 0xbf82015e,
>+	0xbf820001, 0xbf820248,
> 	0xb8f8f802, 0x89788678,
>-	0xb8fbf803, 0x866eff7b,
>-	0x00000400, 0xbf85003b,
>-	0x866eff7b, 0x00000800,
>-	0xbf850003, 0x866eff7b,
>-	0x00000100, 0xbf84000c,
>+	0xb8eef801, 0x866eff6e,
>+	0x00000800, 0xbf840003,
> 	0x866eff78, 0x00002000,
>-	0xbf840005, 0xbf8e0010,
>-	0xb8eef803, 0x866eff6e,
>-	0x00000400, 0xbf84fffb,
>-	0x8778ff78, 0x00002000,
>-	0x80ec886c, 0x82ed806d,
>-	0xb8eef807, 0x866fff6e,
>-	0x001f8000, 0x8e6f8b6f,
>-	0x8977ff77, 0xfc000000,
>-	0x87776f77, 0x896eff6e,
>-	0x001f8000, 0xb96ef807,
>-	0xb8faf812, 0xb8fbf813,
>-	0x8efa887a, 0xc0071bbd,
>-	0x00000000, 0xbf8cc07f,
>-	0xc0071ebd, 0x00000008,
>-	0xbf8cc07f, 0x86ee6e6e,
>-	0xbf840001, 0xbe801d6e,
>-	0xb8fbf803, 0x867bff7b,
>-	0x000001ff, 0xbf850002,
>-	0x806c846c, 0x826d806d,
>+	0xbf840016, 0xb8fbf803,
>+	0x866eff7b, 0x00000400,
>+	0xbf85003b, 0x866eff7b,
>+	0x00000800, 0xbf850003,
>+	0x866eff7b, 0x00000100,
>+	0xbf84000c, 0x866eff78,
>+	0x00002000, 0xbf840005,
>+	0xbf8e0010, 0xb8eef803,
>+	0x866eff6e, 0x00000400,
>+	0xbf84fffb, 0x8778ff78,
>+	0x00002000, 0x80ec886c,
>+	0x82ed806d, 0xb8eef807,
>+	0x866fff6e, 0x001f8000,
>+	0x8e6f8b6f, 0x8977ff77,
>+	0xfc000000, 0x87776f77,
>+	0x896eff6e, 0x001f8000,
>+	0xb96ef807, 0xb8faf812,
>+	0xb8fbf813, 0x8efa887a,
>+	0xc0071bbd, 0x00000000,
>+	0xbf8cc07f, 0xc0071ebd,
>+	0x00000008, 0xbf8cc07f,
>+	0x86ee6e6e, 0xbf840001,
>+	0xbe801d6e, 0xb8fbf803,
>+	0x867bff7b, 0x000001ff,
>+	0xbf850002, 0x806c846c,
>+	0x826d806d, 0x866dff6d,
>+	0x0000ffff, 0x8f6e8b77,
>+	0x866eff6e, 0x001f8000,
>+	0xb96ef807, 0x86fe7e7e,
>+	0x86ea6a6a, 0x8f6e8378,
>+	0xb96ee0c2, 0xbf800002,
>+	0xb9780002, 0xbe801f6c,
> 	0x866dff6d, 0x0000ffff,
>-	0x8f6e8b77, 0x866eff6e,
>-	0x001f8000, 0xb96ef807,
>-	0x86fe7e7e, 0x86ea6a6a,
>-	0x8f6e8378, 0xb96ee0c2,
>-	0xbf800002, 0xb9780002,
>-	0xbe801f6c, 0x866dff6d,
>-	0x0000ffff, 0xbefa0080,
>-	0xb97a0283, 0xb8fa2407,
>-	0x8e7a9b7a, 0x876d7a6d,
>-	0xb8fa03c7, 0x8e7a9a7a,
>-	0x876d7a6d, 0xb8faf807,
>-	0x867aff7a, 0x00007fff,
>-	0xb97af807, 0xbeee007e,
>-	0xbeef007f, 0xbefe0180,
>-	0xbf900004, 0x877a8478,
>-	0xb97af802, 0xbf8e0002,
>-	0xbf88fffe, 0xb8fa2a05,
>-	0x807a817a, 0x8e7a8a7a,
>-	0xb8fb1605, 0x807b817b,
>-	0x8e7b867b, 0x807a7b7a,
>-	0x807a7e7a, 0x827b807f,
>-	0x867bff7b, 0x0000ffff,
>-	0xc04b1c3d, 0x00000050,
>-	0xbf8cc07f, 0xc04b1d3d,
>-	0x00000060, 0xbf8cc07f,
>-	0xc0431e7d, 0x00000074,
>-	0xbf8cc07f, 0xbef4007e,
>-	0x8675ff7f, 0x0000ffff,
>-	0x8775ff75, 0x00040000,
>-	0xbef60080, 0xbef700ff,
>-	0x00807fac, 0x867aff7f,
>-	0x08000000, 0x8f7a837a,
>-	0x87777a77, 0x867aff7f,
>-	0x70000000, 0x8f7a817a,
>-	0x87777a77, 0xbef1007c,
>-	0xbef00080, 0xb8f02a05,
>-	0x80708170, 0x8e708a70,
>-	0xb8fa1605, 0x807a817a,
>-	0x8e7a867a, 0x80707a70,
>-	0xbef60084, 0xbef600ff,
>-	0x01000000, 0xbefe007c,
>-	0xbefc0070, 0xc0611c7a,
>-	0x0000007c, 0xbf8cc07f,
>-	0x80708470, 0xbefc007e,
>+	0xbefa0080, 0xb97a0283,
>+	0xb8fa2407, 0x8e7a9b7a,
>+	0x876d7a6d, 0xb8fa03c7,
>+	0x8e7a9a7a, 0x876d7a6d,
>+	0xb8faf807, 0x867aff7a,
>+	0x00007fff, 0xb97af807,
>+	0xbeee007e, 0xbeef007f,
>+	0xbefe0180, 0xbf900004,
>+	0x877a8478, 0xb97af802,
>+	0xbf8e0002, 0xbf88fffe,
>+	0xb8fa2a05, 0x807a817a,
>+	0x8e7a8a7a, 0xb8fb1605,
>+	0x807b817b, 0x8e7b867b,
>+	0x807a7b7a, 0x807a7e7a,
>+	0x827b807f, 0x867bff7b,
>+	0x0000ffff, 0xc04b1c3d,
>+	0x00000050, 0xbf8cc07f,
>+	0xc04b1d3d, 0x00000060,
>+	0xbf8cc07f, 0xc0431e7d,
>+	0x00000074, 0xbf8cc07f,
>+	0xbef4007e, 0x8675ff7f,
>+	0x0000ffff, 0x8775ff75,
>+	0x00040000, 0xbef60080,
>+	0xbef700ff, 0x00807fac,
>+	0x867aff7f, 0x08000000,
>+	0x8f7a837a, 0x87777a77,
>+	0x867aff7f, 0x70000000,
>+	0x8f7a817a, 0x87777a77,
>+	0xbef1007c, 0xbef00080,
>+	0xb8f02a05, 0x80708170,
>+	0x8e708a70, 0xb8fa1605,
>+	0x807a817a, 0x8e7a867a,
>+	0x80707a70, 0xbef60084,
>+	0xbef600ff, 0x01000000,
> 	0xbefe007c, 0xbefc0070,
>-	0xc0611b3a, 0x0000007c,
>+	0xc0611c7a, 0x0000007c,
> 	0xbf8cc07f, 0x80708470,
> 	0xbefc007e, 0xbefe007c,
>-	0xbefc0070, 0xc0611b7a,
>+	0xbefc0070, 0xc0611b3a,
> 	0x0000007c, 0xbf8cc07f,
> 	0x80708470, 0xbefc007e,
> 	0xbefe007c, 0xbefc0070,
>-	0xc0611bba, 0x0000007c,
>+	0xc0611b7a, 0x0000007c,
> 	0xbf8cc07f, 0x80708470,
> 	0xbefc007e, 0xbefe007c,
>-	0xbefc0070, 0xc0611bfa,
>+	0xbefc0070, 0xc0611bba,
> 	0x0000007c, 0xbf8cc07f,
> 	0x80708470, 0xbefc007e,
> 	0xbefe007c, 0xbefc0070,
>-	0xc0611e3a, 0x0000007c,
>-	0xbf8cc07f, 0x80708470,
>-	0xbefc007e, 0xb8fbf803,
>-	0xbefe007c, 0xbefc0070,
>-	0xc0611efa, 0x0000007c,
>+	0xc0611bfa, 0x0000007c,
> 	0xbf8cc07f, 0x80708470,
> 	0xbefc007e, 0xbefe007c,
>-	0xbefc0070, 0xc0611a3a,
>+	0xbefc0070, 0xc0611e3a,
>+	0x0000007c, 0xbf8cc07f,
>+	0x80708470, 0xbefc007e,
>+	0xb8fbf803, 0xbefe007c,
>+	0xbefc0070, 0xc0611efa,
> 	0x0000007c, 0xbf8cc07f,
> 	0x80708470, 0xbefc007e,
> 	0xbefe007c, 0xbefc0070,
>-	0xc0611a7a, 0x0000007c,
>-	0xbf8cc07f, 0x80708470,
>-	0xbefc007e, 0xb8f1f801,
>-	0xbefe007c, 0xbefc0070,
>-	0xc0611c7a, 0x0000007c,
>+	0xc0611a3a, 0x0000007c,
> 	0xbf8cc07f, 0x80708470,
>-	0xbefc007e, 0x867aff7f,
>-	0x04000000, 0xbeef0080,
>-	0x876f6f7a, 0xb8f02a05,
>+	0xbefc007e, 0xbefe007c,
>+	0xbefc0070, 0xc0611a7a,
>+	0x0000007c, 0xbf8cc07f,
>+	0x80708470, 0xbefc007e,
>+	0xb8f1f801, 0xbefe007c,
>+	0xbefc0070, 0xc0611c7a,
>+	0x0000007c, 0xbf8cc07f,
>+	0x80708470, 0xbefc007e,
>+	0x867aff7f, 0x04000000,
>+	0xbeef0080, 0x876f6f7a,
>+	0xb8f02a05, 0x80708170,
>+	0x8e708a70, 0xb8fb1605,
>+	0x807b817b, 0x8e7b847b,
>+	0x8e76827b, 0xbef600ff,
>+	0x01000000, 0xbef20174,
>+	0x80747074, 0x82758075,
>+	0xbefc0080, 0xbf800000,
>+	0xbe802b00, 0xbe822b02,
>+	0xbe842b04, 0xbe862b06,
>+	0xbe882b08, 0xbe8a2b0a,
>+	0xbe8c2b0c, 0xbe8e2b0e,
>+	0xc06b003a, 0x00000000,
>+	0xbf8cc07f, 0xc06b013a,
>+	0x00000010, 0xbf8cc07f,
>+	0xc06b023a, 0x00000020,
>+	0xbf8cc07f, 0xc06b033a,
>+	0x00000030, 0xbf8cc07f,
>+	0x8074c074, 0x82758075,
>+	0x807c907c, 0xbf0a7b7c,
>+	0xbf85ffe7, 0xbef40172,
>+	0xbef00080, 0xbefe00c1,
>+	0xbeff00c1, 0xbee80080,
>+	0xbee90080, 0xbef600ff,
>+	0x01000000, 0x867aff78,
>+	0x00400000, 0xbf850003,
>+	0xb8faf803, 0x897a7aff,
>+	0x10000000, 0xbf85004d,
>+	0xbe840080, 0xd2890000,
>+	0x00000900, 0x80048104,
>+	0xd2890001, 0x00000900,
>+	0x80048104, 0xd2890002,
>+	0x00000900, 0x80048104,
>+	0xd2890003, 0x00000900,
>+	0x80048104, 0xc069003a,
>+	0x00000070, 0xbf8cc07f,
>+	0x80709070, 0xbf06c004,
>+	0xbf84ffee, 0xbe840080,
>+	0xd2890000, 0x00000901,
>+	0x80048104, 0xd2890001,
>+	0x00000901, 0x80048104,
>+	0xd2890002, 0x00000901,
>+	0x80048104, 0xd2890003,
>+	0x00000901, 0x80048104,
>+	0xc069003a, 0x00000070,
>+	0xbf8cc07f, 0x80709070,
>+	0xbf06c004, 0xbf84ffee,
>+	0xbe840080, 0xd2890000,
>+	0x00000902, 0x80048104,
>+	0xd2890001, 0x00000902,
>+	0x80048104, 0xd2890002,
>+	0x00000902, 0x80048104,
>+	0xd2890003, 0x00000902,
>+	0x80048104, 0xc069003a,
>+	0x00000070, 0xbf8cc07f,
>+	0x80709070, 0xbf06c004,
>+	0xbf84ffee, 0xbe840080,
>+	0xd2890000, 0x00000903,
>+	0x80048104, 0xd2890001,
>+	0x00000903, 0x80048104,
>+	0xd2890002, 0x00000903,
>+	0x80048104, 0xd2890003,
>+	0x00000903, 0x80048104,
>+	0xc069003a, 0x00000070,
>+	0xbf8cc07f, 0x80709070,
>+	0xbf06c004, 0xbf84ffee,
>+	0xbf820008, 0xe0724000,
>+	0x701d0000, 0xe0724100,
>+	0x701d0100, 0xe0724200,
>+	0x701d0200, 0xe0724300,
>+	0x701d0300, 0xbefe00c1,
>+	0xbeff00c1, 0xb8fb4306,
>+	0x867bc17b, 0xbf840063,
>+	0xbf8a0000, 0x867aff6f,
>+	0x04000000, 0xbf84005f,
>+	0x8e7b867b, 0x8e7b827b,
>+	0xbef6007b, 0xb8f02a05,
> 	0x80708170, 0x8e708a70,
>-	0xb8fb1605, 0x807b817b,
>-	0x8e7b847b, 0x8e76827b,
>-	0xbef600ff, 0x01000000,
>-	0xbef20174, 0x80747074,
>-	0x82758075, 0xbefc0080,
>-	0xbf800000, 0xbe802b00,
>-	0xbe822b02, 0xbe842b04,
>-	0xbe862b06, 0xbe882b08,
>-	0xbe8a2b0a, 0xbe8c2b0c,
>-	0xbe8e2b0e, 0xc06b003a,
>-	0x00000000, 0xbf8cc07f,
>-	0xc06b013a, 0x00000010,
>-	0xbf8cc07f, 0xc06b023a,
>-	0x00000020, 0xbf8cc07f,
>-	0xc06b033a, 0x00000030,
>-	0xbf8cc07f, 0x8074c074,
>-	0x82758075, 0x807c907c,
>-	0xbf0a7b7c, 0xbf85ffe7,
>-	0xbef40172, 0xbef00080,
>-	0xbefe00c1, 0xbeff00c1,
>-	0xbee80080, 0xbee90080,
>+	0xb8fa1605, 0x807a817a,
>+	0x8e7a867a, 0x80707a70,
>+	0x8070ff70, 0x00000080,
> 	0xbef600ff, 0x01000000,
>-	0xe0724000, 0x701d0000,
>-	0xe0724100, 0x701d0100,
>-	0xe0724200, 0x701d0200,
>-	0xe0724300, 0x701d0300,
>-	0xbefe00c1, 0xbeff00c1,
>-	0xb8fb4306, 0x867bc17b,
>-	0xbf84002c, 0xbf8a0000,
>-	0x867aff6f, 0x04000000,
>-	0xbf840028, 0x8e7b867b,
>-	0x8e7b827b, 0xbef6007b,
>-	0xb8f02a05, 0x80708170,
>-	0x8e708a70, 0xb8fa1605,
>-	0x807a817a, 0x8e7a867a,
>-	0x80707a70, 0x8070ff70,
>-	0x00000080, 0xbef600ff,
>-	0x01000000, 0xbefc0080,
>-	0xd28c0002, 0x000100c1,
>-	0xd28d0003, 0x000204c1,
>+	0xbefc0080, 0xd28c0002,
>+	0x000100c1, 0xd28d0003,
>+	0x000204c1, 0x867aff78,
>+	0x00400000, 0xbf850003,
>+	0xb8faf803, 0x897a7aff,
>+	0x10000000, 0xbf850030,
>+	0x24040682, 0xd86e4000,
>+	0x00000002, 0xbf8cc07f,
>+	0xbe840080, 0xd2890000,
>+	0x00000900, 0x80048104,
>+	0xd2890001, 0x00000900,
>+	0x80048104, 0xd2890002,
>+	0x00000900, 0x80048104,
>+	0xd2890003, 0x00000900,
>+	0x80048104, 0xc069003a,
>+	0x00000070, 0xbf8cc07f,
>+	0x80709070, 0xbf06c004,
>+	0xbf84ffee, 0xbe840080,
>+	0xd2890000, 0x00000901,
>+	0x80048104, 0xd2890001,
>+	0x00000901, 0x80048104,
>+	0xd2890002, 0x00000901,
>+	0x80048104, 0xd2890003,
>+	0x00000901, 0x80048104,
>+	0xc069003a, 0x00000070,
>+	0xbf8cc07f, 0x80709070,
>+	0xbf06c004, 0xbf84ffee,
>+	0x680404ff, 0x00000200,
>+	0xd0c9006a, 0x0000f702,
>+	0xbf87ffd2, 0xbf820015,
> 	0xd1060002, 0x00011103,
> 	0x7e0602ff, 0x00000200,
> 	0xbefc00ff, 0x00010000,
>@@ -438,9 +511,53 @@
> 	0x807b817b, 0x8e7b827b,
> 	0x8e76887b, 0xbef600ff,
> 	0x01000000, 0xbefc0084,
>-	0xbf0a7b7c, 0xbf840015,
>+	0xbf0a7b7c, 0xbf84006d,
> 	0xbf11017c, 0x807bff7b,
>-	0x00001000, 0x7e000300,
>+	0x00001000, 0x867aff78,
>+	0x00400000, 0xbf850003,
>+	0xb8faf803, 0x897a7aff,
>+	0x10000000, 0xbf850051,
>+	0xbe840080, 0xd2890000,
>+	0x00000900, 0x80048104,
>+	0xd2890001, 0x00000900,
>+	0x80048104, 0xd2890002,
>+	0x00000900, 0x80048104,
>+	0xd2890003, 0x00000900,
>+	0x80048104, 0xc069003a,
>+	0x00000070, 0xbf8cc07f,
>+	0x80709070, 0xbf06c004,
>+	0xbf84ffee, 0xbe840080,
>+	0xd2890000, 0x00000901,
>+	0x80048104, 0xd2890001,
>+	0x00000901, 0x80048104,
>+	0xd2890002, 0x00000901,
>+	0x80048104, 0xd2890003,
>+	0x00000901, 0x80048104,
>+	0xc069003a, 0x00000070,
>+	0xbf8cc07f, 0x80709070,
>+	0xbf06c004, 0xbf84ffee,
>+	0xbe840080, 0xd2890000,
>+	0x00000902, 0x80048104,
>+	0xd2890001, 0x00000902,
>+	0x80048104, 0xd2890002,
>+	0x00000902, 0x80048104,
>+	0xd2890003, 0x00000902,
>+	0x80048104, 0xc069003a,
>+	0x00000070, 0xbf8cc07f,
>+	0x80709070, 0xbf06c004,
>+	0xbf84ffee, 0xbe840080,
>+	0xd2890000, 0x00000903,
>+	0x80048104, 0xd2890001,
>+	0x00000903, 0x80048104,
>+	0xd2890002, 0x00000903,
>+	0x80048104, 0xd2890003,
>+	0x00000903, 0x80048104,
>+	0xc069003a, 0x00000070,
>+	0xbf8cc07f, 0x80709070,
>+	0xbf06c004, 0xbf84ffee,
>+	0x807c847c, 0xbf0a7b7c,
>+	0xbf85ffb1, 0xbf9c0000,
>+	0xbf820012, 0x7e000300,
> 	0x7e020301, 0x7e040302,
> 	0x7e060303, 0xe0724000,
> 	0x701d0000, 0xe0724100,
>@@ -563,24 +680,47 @@
> };
> 
> static const uint32_t cwsr_trap_gfx10_hex[] = {
>-	0xbf820001, 0xbf82012e,
>-	0xb0804004, 0xb970f802,
>-	0x8a708670, 0xb971f803,
>-	0x8771ff71, 0x00000400,
>-	0xbf850008, 0xb971f803,
>-	0x8771ff71, 0x000001ff,
>-	0xbf850001, 0x806c846c,
>+	0xbf820001, 0xbf8201c1,
>+	0xb0804004, 0xb978f802,
>+	0x8a788678, 0xb971f803,
>+	0x876eff71, 0x00000400,
>+	0xbf850033, 0x876eff71,
>+	0x00000100, 0xbf840002,
>+	0x8878ff78, 0x00002000,
>+	0x8a77ff77, 0xff000000,
>+	0xb96ef807, 0x876fff6e,
>+	0x02000000, 0x8f6f866f,
>+	0x88776f77, 0x876fff6e,
>+	0x003f8000, 0x8f6f896f,
>+	0x88776f77, 0x8a6eff6e,
>+	0x023f8000, 0xb9eef807,
>+	0xb970f812, 0xb971f813,
>+	0x8ff08870, 0xf4051bb8,
>+	0xfa000000, 0xbf8cc07f,
>+	0xf4051c38, 0xfa000008,
>+	0xbf8cc07f, 0x87ee6e6e,
>+	0xbf840001, 0xbe80206e,
>+	0xb971f803, 0x8771ff71,
>+	0x000001ff, 0xbf850002,
>+	0x806c846c, 0x826d806d,
>+	0x876dff6d, 0x0000ffff,
>+	0x906e8977, 0x876fff6e,
>+	0x003f8000, 0x906e8677,
>+	0x876eff6e, 0x02000000,
>+	0x886e6f6e, 0xb9eef807,
>+	0x87fe7e7e, 0x87ea6a6a,
>+	0xb9f8f802, 0xbe80226c,
>+	0xb971f803, 0x8771ff71,
>+	0x00000100, 0xbf840006,
>+	0xbef60380, 0xb9f60203,
> 	0x876dff6d, 0x0000ffff,
>-	0xbe80226c, 0xb971f803,
>-	0x8771ff71, 0x00000100,
>-	0xbf840006, 0xbef60380,
>-	0xb9f60203, 0x876dff6d,
>-	0x0000ffff, 0x80ec886c,
>-	0x82ed806d, 0xbef60380,
>-	0xb9f60283, 0xb973f816,
>-	0xb9762c07, 0x8f769c76,
>-	0x886d766d, 0xb97603c7,
>-	0x8f769b76, 0x886d766d,
>+	0x80ec886c, 0x82ed806d,
>+	0xbef60380, 0xb9f60283,
>+	0xb972f816, 0xb9762c07,
>+	0x8f769a76, 0x886d766d,
>+	0xb97603c7, 0x8f769976,
>+	0x886d766d, 0xb9760647,
>+	0x8f769876, 0x886d766d,
> 	0xb976f807, 0x8776ff76,
> 	0x00007fff, 0xb9f6f807,
> 	0xbeee037e, 0xbeef037f,
>@@ -589,274 +729,833 @@
> 	0xbef4037e, 0x8775ff7f,
> 	0x0000ffff, 0x8875ff75,
> 	0x00040000, 0xbef60380,
>-	0xbef703ff, 0x00807fac,
>+	0xbef703ff, 0x10807fac,
> 	0x8776ff7f, 0x08000000,
> 	0x90768376, 0x88777677,
> 	0x8776ff7f, 0x70000000,
> 	0x90768176, 0x88777677,
> 	0xbefb037c, 0xbefa0380,
>-	0xb97202dc, 0x8872727f,
>-	0xbefe03c1, 0x877c8172,
>-	0xbf06817c, 0xbf850002,
>-	0xbeff0380, 0xbf820001,
>-	0xbeff03c1, 0xb9712a05,
>-	0x80718171, 0x8f718271,
>-	0x877c8172, 0xbf06817c,
>-	0xbf85000d, 0x8f768771,
>+	0xb97302dc, 0x8f739973,
>+	0x8873737f, 0xb97a2a05,
>+	0x807a817a, 0x907c9973,
>+	0x877c817c, 0xbf06817c,
>+	0xbf850002, 0x8f7a897a,
>+	0xbf820001, 0x8f7a8a7a,
>+	0xb9761e06, 0x8f768a76,
>+	0x807a767a, 0x807aff7a,
>+	0x00000200, 0xbef603ff,
>+	0x01000000, 0xbefe037c,
>+	0xbefc037a, 0xf4611efa,
>+	0xf8000000, 0x807a847a,
>+	0xbefc037e, 0xbefe037c,
>+	0xbefc037a, 0xf4611b3a,
>+	0xf8000000, 0x807a847a,
>+	0xbefc037e, 0xbefe037c,
>+	0xbefc037a, 0xf4611b7a,
>+	0xf8000000, 0x807a847a,
>+	0xbefc037e, 0xbefe037c,
>+	0xbefc037a, 0xf4611bba,
>+	0xf8000000, 0x807a847a,
>+	0xbefc037e, 0xbefe037c,
>+	0xbefc037a, 0xf4611bfa,
>+	0xf8000000, 0x807a847a,
>+	0xbefc037e, 0xbefe037c,
>+	0xbefc037a, 0xf4611e3a,
>+	0xf8000000, 0x807a847a,
>+	0xbefc037e, 0xb971f803,
>+	0xbefe037c, 0xbefc037a,
>+	0xf4611c7a, 0xf8000000,
>+	0x807a847a, 0xbefc037e,
>+	0xbefe037c, 0xbefc037a,
>+	0xf4611cba, 0xf8000000,
>+	0x807a847a, 0xbefc037e,
>+	0xb97bf801, 0xbefe037c,
>+	0xbefc037a, 0xf4611efa,
>+	0xf8000000, 0x807a847a,
>+	0xbefc037e, 0xb97bf814,
>+	0xbefe037c, 0xbefc037a,
>+	0xf4611efa, 0xf8000000,
>+	0x807a847a, 0xbefc037e,
>+	0xb97bf815, 0xbefe037c,
>+	0xbefc037a, 0xf4611efa,
>+	0xf8000000, 0x807a847a,
>+	0xbefc037e, 0x8776ff7f,
>+	0x04000000, 0xbeef0380,
>+	0x886f6f76, 0xb97a2a05,
>+	0x807a817a, 0x907c9973,
>+	0x877c817c, 0xbf06817c,
>+	0xbf850002, 0x8f7a897a,
>+	0xbf820001, 0x8f7a8a7a,
>+	0xb9761e06, 0x8f768a76,
>+	0x807a767a, 0xbef603ff,
>+	0x01000000, 0xbef20374,
>+	0x80747a74, 0x82758075,
>+	0xbefc0380, 0xbf800000,
>+	0xbe802f00, 0xbe822f02,
>+	0xbe842f04, 0xbe862f06,
>+	0xbe882f08, 0xbe8a2f0a,
>+	0xbe8c2f0c, 0xbe8e2f0e,
>+	0xf469003a, 0xfa000000,
>+	0xf469013a, 0xfa000010,
>+	0xf469023a, 0xfa000020,
>+	0xf469033a, 0xfa000030,
>+	0x8074c074, 0x82758075,
>+	0x807c907c, 0xbf0aff7c,
>+	0x00000060, 0xbf85ffea,
>+	0xbe802f00, 0xbe822f02,
>+	0xbe842f04, 0xbe862f06,
>+	0xbe882f08, 0xbe8a2f0a,
>+	0xf469003a, 0xfa000000,
>+	0xf469013a, 0xfa000010,
>+	0xf469023a, 0xfa000020,
>+	0x8074b074, 0x82758075,
>+	0xbef40372, 0xbefa0380,
>+	0xbefe03c1, 0x907c9973,
>+	0x877c817c, 0xbf06817c,
>+	0xbf850002, 0xbeff0380,
>+	0xbf820002, 0xbeff03c1,
>+	0xbf82000b, 0xbef603ff,
>+	0x01000000, 0xe0704000,
>+	0x7a5d0000, 0xe0704080,
>+	0x7a5d0100, 0xe0704100,
>+	0x7a5d0200, 0xe0704180,
>+	0x7a5d0300, 0xbf82000a,
> 	0xbef603ff, 0x01000000,
>-	0xbefc0380, 0x7e008700,
> 	0xe0704000, 0x7a5d0000,
>-	0x807c817c, 0x807aff7a,
>-	0x00000080, 0xbf0a717c,
>-	0xbf85fff8, 0xbf82001b,
>-	0x8f768871, 0xbef603ff,
>-	0x01000000, 0xbefc0380,
>-	0x7e008700, 0xe0704000,
>-	0x7a5d0000, 0x807c817c,
>-	0x807aff7a, 0x00000100,
>-	0xbf0a717c, 0xbf85fff8,
>-	0xb9711e06, 0x8771c171,
>-	0xbf84000c, 0x8f718371,
>-	0x80717c71, 0xbefe03c1,
>-	0xbeff0380, 0x7e008700,
>-	0xe0704000, 0x7a5d0000,
>-	0x807c817c, 0x807aff7a,
>-	0x00000080, 0xbf0a717c,
>-	0xbf85fff8, 0xbf8a0000,
>-	0x8776ff72, 0x04000000,
>-	0xbf84002b, 0xbefe03c1,
>-	0x877c8172, 0xbf06817c,
>+	0xe0704100, 0x7a5d0100,
>+	0xe0704200, 0x7a5d0200,
>+	0xe0704300, 0x7a5d0300,
>+	0xbefe03c1, 0x907c9973,
>+	0x877c817c, 0xbf06817c,
> 	0xbf850002, 0xbeff0380,
> 	0xbf820001, 0xbeff03c1,
> 	0xb9714306, 0x8771c171,
>-	0xbf840021, 0x8f718671,
>+	0xbf840046, 0xbf8a0000,
>+	0x8776ff6f, 0x04000000,
>+	0xbf840042, 0x8f718671,
> 	0x8f718271, 0xbef60371,
>+	0xb97a2a05, 0x807a817a,
>+	0x907c9973, 0x877c817c,
>+	0xbf06817c, 0xbf850002,
>+	0x8f7a897a, 0xbf820001,
>+	0x8f7a8a7a, 0xb9761e06,
>+	0x8f768a76, 0x807a767a,
>+	0x807aff7a, 0x00000200,
>+	0x807aff7a, 0x00000080,
> 	0xbef603ff, 0x01000000,
> 	0xd7650000, 0x000100c1,
> 	0xd7660000, 0x000200c1,
>-	0x16000084, 0x877c8172,
>-	0xbf06817c, 0xbefc0380,
>-	0xbf85000a, 0x807cff7c,
>-	0x00000080, 0x807aff7a,
>-	0x00000080, 0xd5250000,
>-	0x0001ff00, 0x00000080,
>-	0xbf0a717c, 0xbf85fff7,
>-	0xbf820009, 0x807cff7c,
>-	0x00000100, 0x807aff7a,
>-	0x00000100, 0xd5250000,
>-	0x0001ff00, 0x00000100,
>-	0xbf0a717c, 0xbf85fff7,
>-	0x877c8172, 0xbf06817c,
>-	0xbf850003, 0x8f7687ff,
>-	0x0000006a, 0xbf820002,
>-	0x8f7688ff, 0x0000006a,
>+	0x16000084, 0x907c9973,
>+	0x877c817c, 0xbf06817c,
>+	0xbefc0380, 0xbf850012,
>+	0xbe8303ff, 0x00000080,
>+	0xbf800000, 0xbf800000,
>+	0xbf800000, 0xd8d80000,
>+	0x01000000, 0xbf8c0000,
>+	0xe0704000, 0x7a5d0100,
>+	0x807c037c, 0x807a037a,
>+	0xd5250000, 0x0001ff00,
>+	0x00000080, 0xbf0a717c,
>+	0xbf85fff4, 0xbf820011,
>+	0xbe8303ff, 0x00000100,
>+	0xbf800000, 0xbf800000,
>+	0xbf800000, 0xd8d80000,
>+	0x01000000, 0xbf8c0000,
>+	0xe0704000, 0x7a5d0100,
>+	0x807c037c, 0x807a037a,
>+	0xd5250000, 0x0001ff00,
>+	0x00000100, 0xbf0a717c,
>+	0xbf85fff4, 0xbefe03c1,
>+	0x907c9973, 0x877c817c,
>+	0xbf06817c, 0xbf850004,
>+	0xbefa03ff, 0x00000200,
>+	0xbeff0380, 0xbf820003,
>+	0xbefa03ff, 0x00000400,
>+	0xbeff03c1, 0xb9712a05,
>+	0x80718171, 0x8f718271,
>+	0x907c9973, 0x877c817c,
>+	0xbf06817c, 0xbf850017,
> 	0xbef603ff, 0x01000000,
>-	0x877c8172, 0xbf06817c,
>-	0xbefc0380, 0xbf800000,
>-	0xbf85000b, 0xbe802e00,
>-	0x7e000200, 0xe0704000,
>-	0x7a5d0000, 0x807aff7a,
>-	0x00000080, 0x807c817c,
>-	0xbf0aff7c, 0x0000006a,
>-	0xbf85fff6, 0xbf82000a,
>-	0xbe802e00, 0x7e000200,
>-	0xe0704000, 0x7a5d0000,
>-	0x807aff7a, 0x00000100,
>-	0x807c817c, 0xbf0aff7c,
>-	0x0000006a, 0xbf85fff6,
>-	0xbef60384, 0xbef603ff,
>-	0x01000000, 0x877c8172,
>-	0xbf06817c, 0xbf850030,
>-	0x7e00027b, 0xe0704000,
>-	0x7a5d0000, 0x807aff7a,
>-	0x00000080, 0x7e00026c,
>-	0xe0704000, 0x7a5d0000,
>-	0x807aff7a, 0x00000080,
>-	0x7e00026d, 0xe0704000,
>-	0x7a5d0000, 0x807aff7a,
>-	0x00000080, 0x7e00026e,
>-	0xe0704000, 0x7a5d0000,
>-	0x807aff7a, 0x00000080,
>-	0x7e00026f, 0xe0704000,
>-	0x7a5d0000, 0x807aff7a,
>-	0x00000080, 0x7e000270,
>-	0xe0704000, 0x7a5d0000,
>-	0x807aff7a, 0x00000080,
>-	0xb971f803, 0x7e000271,
>+	0xbefc0384, 0xbf0a717c,
>+	0xbf840037, 0x7e008700,
>+	0x7e028701, 0x7e048702,
>+	0x7e068703, 0xe0704000,
>+	0x7a5d0000, 0xe0704080,
>+	0x7a5d0100, 0xe0704100,
>+	0x7a5d0200, 0xe0704180,
>+	0x7a5d0300, 0x807c847c,
>+	0x807aff7a, 0x00000200,
>+	0xbf0a717c, 0xbf85ffef,
>+	0xbf820025, 0xbef603ff,
>+	0x01000000, 0xbefc0384,
>+	0xbf0a717c, 0xbf840020,
>+	0x7e008700, 0x7e028701,
>+	0x7e048702, 0x7e068703,
> 	0xe0704000, 0x7a5d0000,
>+	0xe0704100, 0x7a5d0100,
>+	0xe0704200, 0x7a5d0200,
>+	0xe0704300, 0x7a5d0300,
>+	0x807c847c, 0x807aff7a,
>+	0x00000400, 0xbf0a717c,
>+	0xbf85ffef, 0xb9711e06,
>+	0x8771c171, 0xbf84000c,
>+	0x8f718371, 0x80717c71,
>+	0xbefe03c1, 0xbeff0380,
>+	0x7e008700, 0xe0704000,
>+	0x7a5d0000, 0x807c817c,
> 	0x807aff7a, 0x00000080,
>-	0x7e000273, 0xe0704000,
>-	0x7a5d0000, 0x807aff7a,
>-	0x00000080, 0xb97bf801,
>-	0x7e00027b, 0xe0704000,
>-	0x7a5d0000, 0x807aff7a,
>-	0x00000080, 0xbf82002f,
>-	0x7e00027b, 0xe0704000,
>-	0x7a5d0000, 0x807aff7a,
>-	0x00000100, 0x7e00026c,
>-	0xe0704000, 0x7a5d0000,
>-	0x807aff7a, 0x00000100,
>-	0x7e00026d, 0xe0704000,
>-	0x7a5d0000, 0x807aff7a,
>-	0x00000100, 0x7e00026e,
>-	0xe0704000, 0x7a5d0000,
>-	0x807aff7a, 0x00000100,
>-	0x7e00026f, 0xe0704000,
>-	0x7a5d0000, 0x807aff7a,
>-	0x00000100, 0x7e000270,
>-	0xe0704000, 0x7a5d0000,
>-	0x807aff7a, 0x00000100,
>-	0xb971f803, 0x7e000271,
>-	0xe0704000, 0x7a5d0000,
>-	0x807aff7a, 0x00000100,
>-	0x7e000273, 0xe0704000,
>-	0x7a5d0000, 0x807aff7a,
>-	0x00000100, 0xb97bf801,
>-	0x7e00027b, 0xe0704000,
>-	0x7a5d0000, 0x807aff7a,
>-	0x00000100, 0xbf820119,
>-	0xbef4037e, 0x8775ff7f,
>-	0x0000ffff, 0x8875ff75,
>-	0x00040000, 0xbef60380,
>-	0xbef703ff, 0x00807fac,
>-	0x8772ff7f, 0x08000000,
>-	0x90728372, 0x88777277,
>-	0x8772ff7f, 0x70000000,
>-	0x90728172, 0x88777277,
>-	0xb97902dc, 0x8879797f,
>-	0xbef80380, 0xbefe03c1,
>-	0x877c8179, 0xbf06817c,
>+	0xbf0a717c, 0xbf85fff8,
>+	0xbf820141, 0xbef4037e,
>+	0x8775ff7f, 0x0000ffff,
>+	0x8875ff75, 0x00040000,
>+	0xbef60380, 0xbef703ff,
>+	0x10807fac, 0x8772ff7f,
>+	0x08000000, 0x90728372,
>+	0x88777277, 0x8772ff7f,
>+	0x70000000, 0x90728172,
>+	0x88777277, 0xb97302dc,
>+	0x8f739973, 0x8873737f,
>+	0x8772ff7f, 0x04000000,
>+	0xbf840036, 0xbefe03c1,
>+	0x907c9973, 0x877c817c,
>+	0xbf06817c, 0xbf850002,
>+	0xbeff0380, 0xbf820001,
>+	0xbeff03c1, 0xb96f4306,
>+	0x876fc16f, 0xbf84002b,
>+	0x8f6f866f, 0x8f6f826f,
>+	0xbef6036f, 0xb9782a05,
>+	0x80788178, 0x907c9973,
>+	0x877c817c, 0xbf06817c,
>+	0xbf850002, 0x8f788978,
>+	0xbf820001, 0x8f788a78,
>+	0xb9721e06, 0x8f728a72,
>+	0x80787278, 0x8078ff78,
>+	0x00000200, 0x8078ff78,
>+	0x00000080, 0xbef603ff,
>+	0x01000000, 0x907c9973,
>+	0x877c817c, 0xbf06817c,
>+	0xbefc0380, 0xbf850009,
>+	0xe0310000, 0x781d0000,
>+	0x807cff7c, 0x00000080,
>+	0x8078ff78, 0x00000080,
>+	0xbf0a6f7c, 0xbf85fff8,
>+	0xbf820008, 0xe0310000,
>+	0x781d0000, 0x807cff7c,
>+	0x00000100, 0x8078ff78,
>+	0x00000100, 0xbf0a6f7c,
>+	0xbf85fff8, 0xbef80380,
>+	0xbefe03c1, 0x907c9973,
>+	0x877c817c, 0xbf06817c,
> 	0xbf850002, 0xbeff0380,
> 	0xbf820001, 0xbeff03c1,
> 	0xb96f2a05, 0x806f816f,
>-	0x8f6f826f, 0x877c8179,
>-	0xbf06817c, 0xbf850013,
>-	0x8f76876f, 0xbef603ff,
>+	0x8f6f826f, 0x907c9973,
>+	0x877c817c, 0xbf06817c,
>+	0xbf850021, 0xbef603ff,
> 	0x01000000, 0xbef20378,
>-	0x8078ff78, 0x00000080,
>-	0xbefc0381, 0xe0304000,
>-	0x785d0000, 0xbf8c3f70,
>-	0x7e008500, 0x807c817c,
>-	0x8078ff78, 0x00000080,
>-	0xbf0a6f7c, 0xbf85fff7,
>-	0xe0304000, 0x725d0000,
>-	0xbf820023, 0x8f76886f,
>+	0x8078ff78, 0x00000200,
>+	0xbefc0384, 0xe0304000,
>+	0x785d0000, 0xe0304080,
>+	0x785d0100, 0xe0304100,
>+	0x785d0200, 0xe0304180,
>+	0x785d0300, 0xbf8c3f70,
>+	0x7e008500, 0x7e028501,
>+	0x7e048502, 0x7e068503,
>+	0x807c847c, 0x8078ff78,
>+	0x00000200, 0xbf0a6f7c,
>+	0xbf85ffee, 0xe0304000,
>+	0x725d0000, 0xe0304080,
>+	0x725d0100, 0xe0304100,
>+	0x725d0200, 0xe0304180,
>+	0x725d0300, 0xbf820031,
> 	0xbef603ff, 0x01000000,
> 	0xbef20378, 0x8078ff78,
>-	0x00000100, 0xbefc0381,
>+	0x00000400, 0xbefc0384,
> 	0xe0304000, 0x785d0000,
>+	0xe0304100, 0x785d0100,
>+	0xe0304200, 0x785d0200,
>+	0xe0304300, 0x785d0300,
> 	0xbf8c3f70, 0x7e008500,
>-	0x807c817c, 0x8078ff78,
>-	0x00000100, 0xbf0a6f7c,
>-	0xbf85fff7, 0xb96f1e06,
>-	0x876fc16f, 0xbf84000e,
>-	0x8f6f836f, 0x806f7c6f,
>-	0xbefe03c1, 0xbeff0380,
>-	0xe0304000, 0x785d0000,
>-	0xbf8c3f70, 0x7e008500,
>-	0x807c817c, 0x8078ff78,
>-	0x00000080, 0xbf0a6f7c,
>-	0xbf85fff7, 0xbeff03c1,
>-	0xe0304000, 0x725d0000,
>-	0x8772ff79, 0x04000000,
>-	0xbf840020, 0xbefe03c1,
>-	0x877c8179, 0xbf06817c,
>-	0xbf850002, 0xbeff0380,
>-	0xbf820001, 0xbeff03c1,
>-	0xb96f4306, 0x876fc16f,
>-	0xbf840016, 0x8f6f866f,
>-	0x8f6f826f, 0xbef6036f,
>-	0xbef603ff, 0x01000000,
>-	0x877c8172, 0xbf06817c,
>-	0xbefc0380, 0xbf850007,
>-	0x807cff7c, 0x00000080,
>-	0x8078ff78, 0x00000080,
>-	0xbf0a6f7c, 0xbf85fffa,
>-	0xbf820006, 0x807cff7c,
>-	0x00000100, 0x8078ff78,
>-	0x00000100, 0xbf0a6f7c,
>-	0xbf85fffa, 0x877c8179,
>-	0xbf06817c, 0xbf850003,
>-	0x8f7687ff, 0x0000006a,
>-	0xbf820002, 0x8f7688ff,
>-	0x0000006a, 0xbef603ff,
>-	0x01000000, 0x877c8179,
>-	0xbf06817c, 0xbf850012,
>-	0xf4211cba, 0xf0000000,
>+	0x7e028501, 0x7e048502,
>+	0x7e068503, 0x807c847c,
>+	0x8078ff78, 0x00000400,
>+	0xbf0a6f7c, 0xbf85ffee,
>+	0xb96f1e06, 0x876fc16f,
>+	0xbf84000e, 0x8f6f836f,
>+	0x806f7c6f, 0xbefe03c1,
>+	0xbeff0380, 0xe0304000,
>+	0x785d0000, 0xbf8c3f70,
>+	0x7e008500, 0x807c817c,
> 	0x8078ff78, 0x00000080,
>-	0xbefc0381, 0xf421003a,
>-	0xf0000000, 0x8078ff78,
>-	0x00000080, 0xbf8cc07f,
>-	0xbe803000, 0xbf800000,
>-	0x807c817c, 0xbf0aff7c,
>-	0x0000006a, 0xbf85fff5,
>-	0xbe800372, 0xbf820011,
>-	0xf4211cba, 0xf0000000,
>-	0x8078ff78, 0x00000100,
>-	0xbefc0381, 0xf421003a,
>-	0xf0000000, 0x8078ff78,
>-	0x00000100, 0xbf8cc07f,
>-	0xbe803000, 0xbf800000,
>-	0x807c817c, 0xbf0aff7c,
>-	0x0000006a, 0xbf85fff5,
>-	0xbe800372, 0xbef60384,
>-	0xbef603ff, 0x01000000,
>-	0x877c8179, 0xbf06817c,
>-	0xbf850025, 0xf4211bfa,
>-	0xf0000000, 0x8078ff78,
>-	0x00000080, 0xf4211b3a,
>-	0xf0000000, 0x8078ff78,
>-	0x00000080, 0xf4211b7a,
>-	0xf0000000, 0x8078ff78,
>-	0x00000080, 0xf4211eba,
>-	0xf0000000, 0x8078ff78,
>-	0x00000080, 0xf4211efa,
>-	0xf0000000, 0x8078ff78,
>-	0x00000080, 0xf4211c3a,
>-	0xf0000000, 0x8078ff78,
>-	0x00000080, 0xf4211c7a,
>-	0xf0000000, 0x8078ff78,
>-	0x00000080, 0xf4211cfa,
>-	0xf0000000, 0x8078ff78,
>-	0x00000080, 0xf4211e7a,
>-	0xf0000000, 0x8078ff78,
>-	0x00000080, 0xbf820024,
>-	0xf4211bfa, 0xf0000000,
>-	0x8078ff78, 0x00000100,
>+	0xbf0a6f7c, 0xbf85fff7,
>+	0xbeff03c1, 0xe0304000,
>+	0x725d0000, 0xe0304100,
>+	0x725d0100, 0xe0304200,
>+	0x725d0200, 0xe0304300,
>+	0x725d0300, 0xb9782a05,
>+	0x80788178, 0x907c9973,
>+	0x877c817c, 0xbf06817c,
>+	0xbf850002, 0x8f788978,
>+	0xbf820001, 0x8f788a78,
>+	0xb9721e06, 0x8f728a72,
>+	0x80787278, 0x8078ff78,
>+	0x00000200, 0x80f8ff78,
>+	0x00000050, 0xbef603ff,
>+	0x01000000, 0xbefc03ff,
>+	0x0000006c, 0x80f89078,
>+	0xf429003a, 0xf0000000,
>+	0xbf8cc07f, 0x80fc847c,
>+	0xbf800000, 0xbe803100,
>+	0xbe823102, 0x80f8a078,
>+	0xf42d003a, 0xf0000000,
>+	0xbf8cc07f, 0x80fc887c,
>+	0xbf800000, 0xbe803100,
>+	0xbe823102, 0xbe843104,
>+	0xbe863106, 0x80f8c078,
>+	0xf431003a, 0xf0000000,
>+	0xbf8cc07f, 0x80fc907c,
>+	0xbf800000, 0xbe803100,
>+	0xbe823102, 0xbe843104,
>+	0xbe863106, 0xbe883108,
>+	0xbe8a310a, 0xbe8c310c,
>+	0xbe8e310e, 0xbf06807c,
>+	0xbf84fff0, 0xb9782a05,
>+	0x80788178, 0x907c9973,
>+	0x877c817c, 0xbf06817c,
>+	0xbf850002, 0x8f788978,
>+	0xbf820001, 0x8f788a78,
>+	0xb9721e06, 0x8f728a72,
>+	0x80787278, 0x8078ff78,
>+	0x00000200, 0xbef603ff,
>+	0x01000000, 0xf4211bfa,
>+	0xf0000000, 0x80788478,
> 	0xf4211b3a, 0xf0000000,
>-	0x8078ff78, 0x00000100,
>-	0xf4211b7a, 0xf0000000,
>-	0x8078ff78, 0x00000100,
>+	0x80788478, 0xf4211b7a,
>+	0xf0000000, 0x80788478,
> 	0xf4211eba, 0xf0000000,
>-	0x8078ff78, 0x00000100,
>-	0xf4211efa, 0xf0000000,
>-	0x8078ff78, 0x00000100,
>+	0x80788478, 0xf4211efa,
>+	0xf0000000, 0x80788478,
> 	0xf4211c3a, 0xf0000000,
>-	0x8078ff78, 0x00000100,
>-	0xf4211c7a, 0xf0000000,
>-	0x8078ff78, 0x00000100,
>-	0xf4211cfa, 0xf0000000,
>-	0x8078ff78, 0x00000100,
>+	0x80788478, 0xf4211c7a,
>+	0xf0000000, 0x80788478,
> 	0xf4211e7a, 0xf0000000,
>-	0x8078ff78, 0x00000100,
>-	0xbf8cc07f, 0x876dff6d,
>+	0x80788478, 0xf4211cfa,
>+	0xf0000000, 0x80788478,
>+	0xf4211bba, 0xf0000000,
>+	0x80788478, 0xbf8cc07f,
>+	0xb9eef814, 0xf4211bba,
>+	0xf0000000, 0x80788478,
>+	0xbf8cc07f, 0xb9eef815,
>+	0xbef2036d, 0x876dff72,
> 	0x0000ffff, 0xbefc036f,
> 	0xbefe037a, 0xbeff037b,
> 	0x876f71ff, 0x000003ff,
>-	0xb9ef4803, 0xb9f3f816,
>+	0xb9ef4803, 0xb9f9f816,
> 	0x876f71ff, 0xfffff800,
> 	0x906f8b6f, 0xb9efa2c3,
>-	0xb9f9f801, 0x876fff6d,
>-	0xf0000000, 0x906f9c6f,
>-	0x8f6f906f, 0xbef20380,
>-	0x88726f72, 0x876fff6d,
>-	0x08000000, 0x906f9b6f,
>-	0x8f6f8f6f, 0x88726f72,
>-	0x876fff70, 0x00800000,
>-	0x906f976f, 0xb9f2f807,
>-	0xb9f0f802, 0xbf8a0000,
>-	0xbe80226c, 0xbf810000,
>+	0xb9f3f801, 0x876fff72,
>+	0xfc000000, 0x906f9a6f,
>+	0x8f6f906f, 0xbef30380,
>+	0x88736f73, 0x876fff72,
>+	0x02000000, 0x906f996f,
>+	0x8f6f8f6f, 0x88736f73,
>+	0x876fff72, 0x01000000,
>+	0x906f986f, 0x8f6f996f,
>+	0x88736f73, 0x876fff70,
>+	0x00800000, 0x906f976f,
>+	0xb9f3f807, 0x87fe7e7e,
>+	0x87ea6a6a, 0xb9f0f802,
>+	0xbf8a0000, 0xbe80226c,
>+	0xbf810000, 0xbf9f0000,
> 	0xbf9f0000, 0xbf9f0000,
> 	0xbf9f0000, 0xbf9f0000,
>-	0xbf9f0000, 0x00000000,
>+};
>+static const uint32_t cwsr_trap_arcturus_hex[] = {
>+	0xbf820001, 0xbf8202c4,
>+	0xb8f8f802, 0x89788678,
>+	0xb8eef801, 0x866eff6e,
>+	0x00000800, 0xbf840003,
>+	0x866eff78, 0x00002000,
>+	0xbf840016, 0xb8fbf803,
>+	0x866eff7b, 0x00000400,
>+	0xbf85003b, 0x866eff7b,
>+	0x00000800, 0xbf850003,
>+	0x866eff7b, 0x00000100,
>+	0xbf84000c, 0x866eff78,
>+	0x00002000, 0xbf840005,
>+	0xbf8e0010, 0xb8eef803,
>+	0x866eff6e, 0x00000400,
>+	0xbf84fffb, 0x8778ff78,
>+	0x00002000, 0x80ec886c,
>+	0x82ed806d, 0xb8eef807,
>+	0x866fff6e, 0x001f8000,
>+	0x8e6f8b6f, 0x8977ff77,
>+	0xfc000000, 0x87776f77,
>+	0x896eff6e, 0x001f8000,
>+	0xb96ef807, 0xb8faf812,
>+	0xb8fbf813, 0x8efa887a,
>+	0xc0071bbd, 0x00000000,
>+	0xbf8cc07f, 0xc0071ebd,
>+	0x00000008, 0xbf8cc07f,
>+	0x86ee6e6e, 0xbf840001,
>+	0xbe801d6e, 0xb8fbf803,
>+	0x867bff7b, 0x000001ff,
>+	0xbf850002, 0x806c846c,
>+	0x826d806d, 0x866dff6d,
>+	0x0000ffff, 0x8f6e8b77,
>+	0x866eff6e, 0x001f8000,
>+	0xb96ef807, 0x86fe7e7e,
>+	0x86ea6a6a, 0x8f6e8378,
>+	0xb96ee0c2, 0xbf800002,
>+	0xb9780002, 0xbe801f6c,
>+	0x866dff6d, 0x0000ffff,
>+	0xbefa0080, 0xb97a0283,
>+	0xb8fa2407, 0x8e7a9b7a,
>+	0x876d7a6d, 0xb8fa03c7,
>+	0x8e7a9a7a, 0x876d7a6d,
>+	0xb8faf807, 0x867aff7a,
>+	0x00007fff, 0xb97af807,
>+	0xbeee007e, 0xbeef007f,
>+	0xbefe0180, 0xbf900004,
>+	0x877a8478, 0xb97af802,
>+	0xbf8e0002, 0xbf88fffe,
>+	0xb8fa2a05, 0x807a817a,
>+	0x8e7a8a7a, 0x8e7a817a,
>+	0xb8fb1605, 0x807b817b,
>+	0x8e7b867b, 0x807a7b7a,
>+	0x807a7e7a, 0x827b807f,
>+	0x867bff7b, 0x0000ffff,
>+	0xc04b1c3d, 0x00000050,
>+	0xbf8cc07f, 0xc04b1d3d,
>+	0x00000060, 0xbf8cc07f,
>+	0xc0431e7d, 0x00000074,
>+	0xbf8cc07f, 0xbef4007e,
>+	0x8675ff7f, 0x0000ffff,
>+	0x8775ff75, 0x00040000,
>+	0xbef60080, 0xbef700ff,
>+	0x00807fac, 0x867aff7f,
>+	0x08000000, 0x8f7a837a,
>+	0x87777a77, 0x867aff7f,
>+	0x70000000, 0x8f7a817a,
>+	0x87777a77, 0xbef1007c,
>+	0xbef00080, 0xb8f02a05,
>+	0x80708170, 0x8e708a70,
>+	0x8e708170, 0xb8fa1605,
>+	0x807a817a, 0x8e7a867a,
>+	0x80707a70, 0xbef60084,
>+	0xbef600ff, 0x01000000,
>+	0xbefe007c, 0xbefc0070,
>+	0xc0611c7a, 0x0000007c,
>+	0xbf8cc07f, 0x80708470,
>+	0xbefc007e, 0xbefe007c,
>+	0xbefc0070, 0xc0611b3a,
>+	0x0000007c, 0xbf8cc07f,
>+	0x80708470, 0xbefc007e,
>+	0xbefe007c, 0xbefc0070,
>+	0xc0611b7a, 0x0000007c,
>+	0xbf8cc07f, 0x80708470,
>+	0xbefc007e, 0xbefe007c,
>+	0xbefc0070, 0xc0611bba,
>+	0x0000007c, 0xbf8cc07f,
>+	0x80708470, 0xbefc007e,
>+	0xbefe007c, 0xbefc0070,
>+	0xc0611bfa, 0x0000007c,
>+	0xbf8cc07f, 0x80708470,
>+	0xbefc007e, 0xbefe007c,
>+	0xbefc0070, 0xc0611e3a,
>+	0x0000007c, 0xbf8cc07f,
>+	0x80708470, 0xbefc007e,
>+	0xb8fbf803, 0xbefe007c,
>+	0xbefc0070, 0xc0611efa,
>+	0x0000007c, 0xbf8cc07f,
>+	0x80708470, 0xbefc007e,
>+	0xbefe007c, 0xbefc0070,
>+	0xc0611a3a, 0x0000007c,
>+	0xbf8cc07f, 0x80708470,
>+	0xbefc007e, 0xbefe007c,
>+	0xbefc0070, 0xc0611a7a,
>+	0x0000007c, 0xbf8cc07f,
>+	0x80708470, 0xbefc007e,
>+	0xb8f1f801, 0xbefe007c,
>+	0xbefc0070, 0xc0611c7a,
>+	0x0000007c, 0xbf8cc07f,
>+	0x80708470, 0xbefc007e,
>+	0x867aff7f, 0x04000000,
>+	0xbeef0080, 0x876f6f7a,
>+	0xb8f02a05, 0x80708170,
>+	0x8e708a70, 0x8e708170,
>+	0xb8fb1605, 0x807b817b,
>+	0x8e7b847b, 0x8e76827b,
>+	0xbef600ff, 0x01000000,
>+	0xbef20174, 0x80747074,
>+	0x82758075, 0xbefc0080,
>+	0xbf800000, 0xbe802b00,
>+	0xbe822b02, 0xbe842b04,
>+	0xbe862b06, 0xbe882b08,
>+	0xbe8a2b0a, 0xbe8c2b0c,
>+	0xbe8e2b0e, 0xc06b003a,
>+	0x00000000, 0xbf8cc07f,
>+	0xc06b013a, 0x00000010,
>+	0xbf8cc07f, 0xc06b023a,
>+	0x00000020, 0xbf8cc07f,
>+	0xc06b033a, 0x00000030,
>+	0xbf8cc07f, 0x8074c074,
>+	0x82758075, 0x807c907c,
>+	0xbf0a7b7c, 0xbf85ffe7,
>+	0xbef40172, 0xbef00080,
>+	0xbefe00c1, 0xbeff00c1,
>+	0xbee80080, 0xbee90080,
>+	0xbef600ff, 0x01000000,
>+	0x867aff78, 0x00400000,
>+	0xbf850003, 0xb8faf803,
>+	0x897a7aff, 0x10000000,
>+	0xbf85004d, 0xbe840080,
>+	0xd2890000, 0x00000900,
>+	0x80048104, 0xd2890001,
>+	0x00000900, 0x80048104,
>+	0xd2890002, 0x00000900,
>+	0x80048104, 0xd2890003,
>+	0x00000900, 0x80048104,
>+	0xc069003a, 0x00000070,
>+	0xbf8cc07f, 0x80709070,
>+	0xbf06c004, 0xbf84ffee,
>+	0xbe840080, 0xd2890000,
>+	0x00000901, 0x80048104,
>+	0xd2890001, 0x00000901,
>+	0x80048104, 0xd2890002,
>+	0x00000901, 0x80048104,
>+	0xd2890003, 0x00000901,
>+	0x80048104, 0xc069003a,
>+	0x00000070, 0xbf8cc07f,
>+	0x80709070, 0xbf06c004,
>+	0xbf84ffee, 0xbe840080,
>+	0xd2890000, 0x00000902,
>+	0x80048104, 0xd2890001,
>+	0x00000902, 0x80048104,
>+	0xd2890002, 0x00000902,
>+	0x80048104, 0xd2890003,
>+	0x00000902, 0x80048104,
>+	0xc069003a, 0x00000070,
>+	0xbf8cc07f, 0x80709070,
>+	0xbf06c004, 0xbf84ffee,
>+	0xbe840080, 0xd2890000,
>+	0x00000903, 0x80048104,
>+	0xd2890001, 0x00000903,
>+	0x80048104, 0xd2890002,
>+	0x00000903, 0x80048104,
>+	0xd2890003, 0x00000903,
>+	0x80048104, 0xc069003a,
>+	0x00000070, 0xbf8cc07f,
>+	0x80709070, 0xbf06c004,
>+	0xbf84ffee, 0xbf820008,
>+	0xe0724000, 0x701d0000,
>+	0xe0724100, 0x701d0100,
>+	0xe0724200, 0x701d0200,
>+	0xe0724300, 0x701d0300,
>+	0xbefe00c1, 0xbeff00c1,
>+	0xb8fb4306, 0x867bc17b,
>+	0xbf840064, 0xbf8a0000,
>+	0x867aff6f, 0x04000000,
>+	0xbf840060, 0x8e7b867b,
>+	0x8e7b827b, 0xbef6007b,
>+	0xb8f02a05, 0x80708170,
>+	0x8e708a70, 0x8e708170,
>+	0xb8fa1605, 0x807a817a,
>+	0x8e7a867a, 0x80707a70,
>+	0x8070ff70, 0x00000080,
>+	0xbef600ff, 0x01000000,
>+	0xbefc0080, 0xd28c0002,
>+	0x000100c1, 0xd28d0003,
>+	0x000204c1, 0x867aff78,
>+	0x00400000, 0xbf850003,
>+	0xb8faf803, 0x897a7aff,
>+	0x10000000, 0xbf850030,
>+	0x24040682, 0xd86e4000,
>+	0x00000002, 0xbf8cc07f,
>+	0xbe840080, 0xd2890000,
>+	0x00000900, 0x80048104,
>+	0xd2890001, 0x00000900,
>+	0x80048104, 0xd2890002,
>+	0x00000900, 0x80048104,
>+	0xd2890003, 0x00000900,
>+	0x80048104, 0xc069003a,
>+	0x00000070, 0xbf8cc07f,
>+	0x80709070, 0xbf06c004,
>+	0xbf84ffee, 0xbe840080,
>+	0xd2890000, 0x00000901,
>+	0x80048104, 0xd2890001,
>+	0x00000901, 0x80048104,
>+	0xd2890002, 0x00000901,
>+	0x80048104, 0xd2890003,
>+	0x00000901, 0x80048104,
>+	0xc069003a, 0x00000070,
>+	0xbf8cc07f, 0x80709070,
>+	0xbf06c004, 0xbf84ffee,
>+	0x680404ff, 0x00000200,
>+	0xd0c9006a, 0x0000f702,
>+	0xbf87ffd2, 0xbf820015,
>+	0xd1060002, 0x00011103,
>+	0x7e0602ff, 0x00000200,
>+	0xbefc00ff, 0x00010000,
>+	0xbe800077, 0x8677ff77,
>+	0xff7fffff, 0x8777ff77,
>+	0x00058000, 0xd8ec0000,
>+	0x00000002, 0xbf8cc07f,
>+	0xe0765000, 0x701d0002,
>+	0x68040702, 0xd0c9006a,
>+	0x0000f702, 0xbf87fff7,
>+	0xbef70000, 0xbef000ff,
>+	0x00000400, 0xbefe00c1,
>+	0xbeff00c1, 0xb8fb2a05,
>+	0x807b817b, 0x8e7b827b,
>+	0x8e76887b, 0xbef600ff,
>+	0x01000000, 0xbefc0084,
>+	0xbf0a7b7c, 0xbf84006d,
>+	0xbf11017c, 0x807bff7b,
>+	0x00001000, 0x867aff78,
>+	0x00400000, 0xbf850003,
>+	0xb8faf803, 0x897a7aff,
>+	0x10000000, 0xbf850051,
>+	0xbe840080, 0xd2890000,
>+	0x00000900, 0x80048104,
>+	0xd2890001, 0x00000900,
>+	0x80048104, 0xd2890002,
>+	0x00000900, 0x80048104,
>+	0xd2890003, 0x00000900,
>+	0x80048104, 0xc069003a,
>+	0x00000070, 0xbf8cc07f,
>+	0x80709070, 0xbf06c004,
>+	0xbf84ffee, 0xbe840080,
>+	0xd2890000, 0x00000901,
>+	0x80048104, 0xd2890001,
>+	0x00000901, 0x80048104,
>+	0xd2890002, 0x00000901,
>+	0x80048104, 0xd2890003,
>+	0x00000901, 0x80048104,
>+	0xc069003a, 0x00000070,
>+	0xbf8cc07f, 0x80709070,
>+	0xbf06c004, 0xbf84ffee,
>+	0xbe840080, 0xd2890000,
>+	0x00000902, 0x80048104,
>+	0xd2890001, 0x00000902,
>+	0x80048104, 0xd2890002,
>+	0x00000902, 0x80048104,
>+	0xd2890003, 0x00000902,
>+	0x80048104, 0xc069003a,
>+	0x00000070, 0xbf8cc07f,
>+	0x80709070, 0xbf06c004,
>+	0xbf84ffee, 0xbe840080,
>+	0xd2890000, 0x00000903,
>+	0x80048104, 0xd2890001,
>+	0x00000903, 0x80048104,
>+	0xd2890002, 0x00000903,
>+	0x80048104, 0xd2890003,
>+	0x00000903, 0x80048104,
>+	0xc069003a, 0x00000070,
>+	0xbf8cc07f, 0x80709070,
>+	0xbf06c004, 0xbf84ffee,
>+	0x807c847c, 0xbf0a7b7c,
>+	0xbf85ffb1, 0xbf9c0000,
>+	0xbf820012, 0x7e000300,
>+	0x7e020301, 0x7e040302,
>+	0x7e060303, 0xe0724000,
>+	0x701d0000, 0xe0724100,
>+	0x701d0100, 0xe0724200,
>+	0x701d0200, 0xe0724300,
>+	0x701d0300, 0x807c847c,
>+	0x8070ff70, 0x00000400,
>+	0xbf0a7b7c, 0xbf85ffef,
>+	0xbf9c0000, 0xbefc0080,
>+	0xbf11017c, 0x867aff78,
>+	0x00400000, 0xbf850003,
>+	0xb8faf803, 0x897a7aff,
>+	0x10000000, 0xbf850059,
>+	0xd3d84000, 0x18000100,
>+	0xd3d84001, 0x18000101,
>+	0xd3d84002, 0x18000102,
>+	0xd3d84003, 0x18000103,
>+	0xbe840080, 0xd2890000,
>+	0x00000900, 0x80048104,
>+	0xd2890001, 0x00000900,
>+	0x80048104, 0xd2890002,
>+	0x00000900, 0x80048104,
>+	0xd2890003, 0x00000900,
>+	0x80048104, 0xc069003a,
>+	0x00000070, 0xbf8cc07f,
>+	0x80709070, 0xbf06c004,
>+	0xbf84ffee, 0xbe840080,
>+	0xd2890000, 0x00000901,
>+	0x80048104, 0xd2890001,
>+	0x00000901, 0x80048104,
>+	0xd2890002, 0x00000901,
>+	0x80048104, 0xd2890003,
>+	0x00000901, 0x80048104,
>+	0xc069003a, 0x00000070,
>+	0xbf8cc07f, 0x80709070,
>+	0xbf06c004, 0xbf84ffee,
>+	0xbe840080, 0xd2890000,
>+	0x00000902, 0x80048104,
>+	0xd2890001, 0x00000902,
>+	0x80048104, 0xd2890002,
>+	0x00000902, 0x80048104,
>+	0xd2890003, 0x00000902,
>+	0x80048104, 0xc069003a,
>+	0x00000070, 0xbf8cc07f,
>+	0x80709070, 0xbf06c004,
>+	0xbf84ffee, 0xbe840080,
>+	0xd2890000, 0x00000903,
>+	0x80048104, 0xd2890001,
>+	0x00000903, 0x80048104,
>+	0xd2890002, 0x00000903,
>+	0x80048104, 0xd2890003,
>+	0x00000903, 0x80048104,
>+	0xc069003a, 0x00000070,
>+	0xbf8cc07f, 0x80709070,
>+	0xbf06c004, 0xbf84ffee,
>+	0x807c847c, 0xbf0a7b7c,
>+	0xbf85ffa9, 0xbf9c0000,
>+	0xbf820016, 0xd3d84000,
>+	0x18000100, 0xd3d84001,
>+	0x18000101, 0xd3d84002,
>+	0x18000102, 0xd3d84003,
>+	0x18000103, 0xe0724000,
>+	0x701d0000, 0xe0724100,
>+	0x701d0100, 0xe0724200,
>+	0x701d0200, 0xe0724300,
>+	0x701d0300, 0x807c847c,
>+	0x8070ff70, 0x00000400,
>+	0xbf0a7b7c, 0xbf85ffeb,
>+	0xbf9c0000, 0xbf820106,
>+	0xbef4007e, 0x8675ff7f,
>+	0x0000ffff, 0x8775ff75,
>+	0x00040000, 0xbef60080,
>+	0xbef700ff, 0x00807fac,
>+	0x866eff7f, 0x08000000,
>+	0x8f6e836e, 0x87776e77,
>+	0x866eff7f, 0x70000000,
>+	0x8f6e816e, 0x87776e77,
>+	0x866eff7f, 0x04000000,
>+	0xbf84001f, 0xbefe00c1,
>+	0xbeff00c1, 0xb8ef4306,
>+	0x866fc16f, 0xbf84001a,
>+	0x8e6f866f, 0x8e6f826f,
>+	0xbef6006f, 0xb8f82a05,
>+	0x80788178, 0x8e788a78,
>+	0x8e788178, 0xb8ee1605,
>+	0x806e816e, 0x8e6e866e,
>+	0x80786e78, 0x8078ff78,
>+	0x00000080, 0xbef600ff,
>+	0x01000000, 0xbefc0080,
>+	0xe0510000, 0x781d0000,
>+	0xe0510100, 0x781d0000,
>+	0x807cff7c, 0x00000200,
>+	0x8078ff78, 0x00000200,
>+	0xbf0a6f7c, 0xbf85fff6,
>+	0xbef80080, 0xbefe00c1,
>+	0xbeff00c1, 0xb8ef2a05,
>+	0x806f816f, 0x8e6f826f,
>+	0x8e76886f, 0xbef90076,
>+	0xbef600ff, 0x01000000,
>+	0xbeee0078, 0x8078ff78,
>+	0x00000400, 0xbef30079,
>+	0x8079ff79, 0x00000400,
>+	0xbefc0084, 0xbf11087c,
>+	0x806fff6f, 0x00008000,
>+	0xe0524000, 0x791d0000,
>+	0xe0524100, 0x791d0100,
>+	0xe0524200, 0x791d0200,
>+	0xe0524300, 0x791d0300,
>+	0x8079ff79, 0x00000400,
>+	0xbf8c0f70, 0xd3d94000,
>+	0x18000100, 0xd3d94001,
>+	0x18000101, 0xd3d94002,
>+	0x18000102, 0xd3d94003,
>+	0x18000103, 0xe0524000,
>+	0x781d0000, 0xe0524100,
>+	0x781d0100, 0xe0524200,
>+	0x781d0200, 0xe0524300,
>+	0x781d0300, 0xbf8c0f70,
>+	0x7e000300, 0x7e020301,
>+	0x7e040302, 0x7e060303,
>+	0x807c847c, 0x8078ff78,
>+	0x00000400, 0xbf0a6f7c,
>+	0xbf85ffdb, 0xbf9c0000,
>+	0xe0524000, 0x731d0000,
>+	0xe0524100, 0x731d0100,
>+	0xe0524200, 0x731d0200,
>+	0xe0524300, 0x731d0300,
>+	0xbf8c0f70, 0xd3d94000,
>+	0x18000100, 0xd3d94001,
>+	0x18000101, 0xd3d94002,
>+	0x18000102, 0xd3d94003,
>+	0x18000103, 0xe0524000,
>+	0x6e1d0000, 0xe0524100,
>+	0x6e1d0100, 0xe0524200,
>+	0x6e1d0200, 0xe0524300,
>+	0x6e1d0300, 0xb8f82a05,
>+	0x80788178, 0x8e788a78,
>+	0x8e788178, 0xb8ee1605,
>+	0x806e816e, 0x8e6e866e,
>+	0x80786e78, 0x80f8c078,
>+	0xb8ef1605, 0x806f816f,
>+	0x8e6f846f, 0x8e76826f,
>+	0xbef600ff, 0x01000000,
>+	0xbefc006f, 0xc031003a,
>+	0x00000078, 0x80f8c078,
>+	0xbf8cc07f, 0x80fc907c,
>+	0xbf800000, 0xbe802d00,
>+	0xbe822d02, 0xbe842d04,
>+	0xbe862d06, 0xbe882d08,
>+	0xbe8a2d0a, 0xbe8c2d0c,
>+	0xbe8e2d0e, 0xbf06807c,
>+	0xbf84fff0, 0xb8f82a05,
>+	0x80788178, 0x8e788a78,
>+	0x8e788178, 0xb8ee1605,
>+	0x806e816e, 0x8e6e866e,
>+	0x80786e78, 0xbef60084,
>+	0xbef600ff, 0x01000000,
>+	0xc0211bfa, 0x00000078,
>+	0x80788478, 0xc0211b3a,
>+	0x00000078, 0x80788478,
>+	0xc0211b7a, 0x00000078,
>+	0x80788478, 0xc0211c3a,
>+	0x00000078, 0x80788478,
>+	0xc0211c7a, 0x00000078,
>+	0x80788478, 0xc0211eba,
>+	0x00000078, 0x80788478,
>+	0xc0211efa, 0x00000078,
>+	0x80788478, 0xc0211a3a,
>+	0x00000078, 0x80788478,
>+	0xc0211a7a, 0x00000078,
>+	0x80788478, 0xc0211cfa,
>+	0x00000078, 0x80788478,
>+	0xbf8cc07f, 0xbefc006f,
>+	0xbefe0070, 0xbeff0071,
>+	0x866f7bff, 0x000003ff,
>+	0xb96f4803, 0x866f7bff,
>+	0xfffff800, 0x8f6f8b6f,
>+	0xb96fa2c3, 0xb973f801,
>+	0xb8ee2a05, 0x806e816e,
>+	0x8e6e8a6e, 0x8e6e816e,
>+	0xb8ef1605, 0x806f816f,
>+	0x8e6f866f, 0x806e6f6e,
>+	0x806e746e, 0x826f8075,
>+	0x866fff6f, 0x0000ffff,
>+	0xc00b1c37, 0x00000050,
>+	0xc00b1d37, 0x00000060,
>+	0xc0031e77, 0x00000074,
>+	0xbf8cc07f, 0x866fff6d,
>+	0xf8000000, 0x8f6f9b6f,
>+	0x8e6f906f, 0xbeee0080,
>+	0x876e6f6e, 0x866fff6d,
>+	0x04000000, 0x8f6f9a6f,
>+	0x8e6f8f6f, 0x876e6f6e,
>+	0x866fff7a, 0x00800000,
>+	0x8f6f976f, 0xb96ef807,
>+	0x866dff6d, 0x0000ffff,
>+	0x86fe7e7e, 0x86ea6a6a,
>+	0x8f6e837a, 0xb96ee0c2,
>+	0xbf800002, 0xb97a0002,
>+	0xbf8a0000, 0x95806f6c,
>+	0xbf810000, 0x00000000,
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_crat.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_crat.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_crat.c	2019-08-31 15:01:11.853736168 -0500
>@@ -662,6 +662,7 @@
> 	case CHIP_VEGA10:
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
>+	case CHIP_ARCTURUS:
> 		pcache_info = vega10_cache_info;
> 		num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
> 		break;
>@@ -788,7 +789,7 @@
>  * is put in the code to ensure we don't overwrite.
>  */
> #define VCRAT_SIZE_FOR_CPU	(2 * PAGE_SIZE)
>-#define VCRAT_SIZE_FOR_GPU	(3 * PAGE_SIZE)
>+#define VCRAT_SIZE_FOR_GPU	(4 * PAGE_SIZE)
> 
> /* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node
>  *
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_device.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_device.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_device.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_device.c	2019-08-31 15:01:11.853736168 -0500
>@@ -42,6 +42,7 @@
> #ifdef KFD_SUPPORT_IOMMU_V2
> static const struct kfd_device_info kaveri_device_info = {
> 	.asic_family = CHIP_KAVERI,
>+	.asic_name = "kaveri",
> 	.max_pasid_bits = 16,
> 	/* max num of queues for KV.TODO should be a dynamic value */
> 	.max_no_of_hqd	= 24,
>@@ -60,6 +61,7 @@
> 
> static const struct kfd_device_info carrizo_device_info = {
> 	.asic_family = CHIP_CARRIZO,
>+	.asic_name = "carrizo",
> 	.max_pasid_bits = 16,
> 	/* max num of queues for CZ.TODO should be a dynamic value */
> 	.max_no_of_hqd	= 24,
>@@ -78,6 +80,7 @@
> 
> static const struct kfd_device_info raven_device_info = {
> 	.asic_family = CHIP_RAVEN,
>+	.asic_name = "raven",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 8,
>@@ -96,6 +99,7 @@
> 
> static const struct kfd_device_info hawaii_device_info = {
> 	.asic_family = CHIP_HAWAII,
>+	.asic_name = "hawaii",
> 	.max_pasid_bits = 16,
> 	/* max num of queues for KV.TODO should be a dynamic value */
> 	.max_no_of_hqd	= 24,
>@@ -114,6 +118,7 @@
> 
> static const struct kfd_device_info tonga_device_info = {
> 	.asic_family = CHIP_TONGA,
>+	.asic_name = "tonga",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 4,
>@@ -131,6 +136,7 @@
> 
> static const struct kfd_device_info fiji_device_info = {
> 	.asic_family = CHIP_FIJI,
>+	.asic_name = "fiji",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 4,
>@@ -148,6 +154,7 @@
> 
> static const struct kfd_device_info fiji_vf_device_info = {
> 	.asic_family = CHIP_FIJI,
>+	.asic_name = "fiji",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 4,
>@@ -166,6 +173,7 @@
> 
> static const struct kfd_device_info polaris10_device_info = {
> 	.asic_family = CHIP_POLARIS10,
>+	.asic_name = "polaris10",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 4,
>@@ -183,6 +191,7 @@
> 
> static const struct kfd_device_info polaris10_vf_device_info = {
> 	.asic_family = CHIP_POLARIS10,
>+	.asic_name = "polaris10",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 4,
>@@ -200,6 +209,7 @@
> 
> static const struct kfd_device_info polaris11_device_info = {
> 	.asic_family = CHIP_POLARIS11,
>+	.asic_name = "polaris11",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 4,
>@@ -217,6 +227,7 @@
> 
> static const struct kfd_device_info polaris12_device_info = {
> 	.asic_family = CHIP_POLARIS12,
>+	.asic_name = "polaris12",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 4,
>@@ -234,6 +245,7 @@
> 
> static const struct kfd_device_info vegam_device_info = {
> 	.asic_family = CHIP_VEGAM,
>+	.asic_name = "vegam",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 4,
>@@ -251,6 +263,7 @@
> 
> static const struct kfd_device_info vega10_device_info = {
> 	.asic_family = CHIP_VEGA10,
>+	.asic_name = "vega10",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 8,
>@@ -268,6 +281,7 @@
> 
> static const struct kfd_device_info vega10_vf_device_info = {
> 	.asic_family = CHIP_VEGA10,
>+	.asic_name = "vega10",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 8,
>@@ -285,6 +299,7 @@
> 
> static const struct kfd_device_info vega12_device_info = {
> 	.asic_family = CHIP_VEGA12,
>+	.asic_name = "vega12",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 8,
>@@ -302,6 +317,7 @@
> 
> static const struct kfd_device_info vega20_device_info = {
> 	.asic_family = CHIP_VEGA20,
>+	.asic_name = "vega20",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd	= 24,
> 	.doorbell_size	= 8,
>@@ -317,8 +333,27 @@
> 	.num_sdma_queues_per_engine = 8,
> };
> 
>+static const struct kfd_device_info arcturus_device_info = {
>+	.asic_family = CHIP_ARCTURUS,
>+	.asic_name = "arcturus",
>+	.max_pasid_bits = 16,
>+	.max_no_of_hqd	= 24,
>+	.doorbell_size	= 8,
>+	.ih_ring_entry_size = 8 * sizeof(uint32_t),
>+	.event_interrupt_class = &event_interrupt_class_v9,
>+	.num_of_watch_points = 4,
>+	.mqd_size_aligned = MQD_SIZE_ALIGNED,
>+	.supports_cwsr = true,
>+	.needs_iommu_device = false,
>+	.needs_pci_atomics = false,
>+	.num_sdma_engines = 2,
>+	.num_xgmi_sdma_engines = 6,
>+	.num_sdma_queues_per_engine = 8,
>+};
>+
> static const struct kfd_device_info navi10_device_info = {
> 	.asic_family = CHIP_NAVI10,
>+	.asic_name = "navi10",
> 	.max_pasid_bits = 16,
> 	.max_no_of_hqd  = 24,
> 	.doorbell_size  = 8,
>@@ -452,7 +487,10 @@
> 	{ 0x66a4, &vega20_device_info },	/* Vega20 */
> 	{ 0x66a7, &vega20_device_info },	/* Vega20 */
> 	{ 0x66af, &vega20_device_info },	/* Vega20 */
>-	/* Navi10 */
>+	{ 0x738C, &arcturus_device_info },	/* Arcturus */
>+	{ 0x7388, &arcturus_device_info },	/* Arcturus */
>+	{ 0x738E, &arcturus_device_info },	/* Arcturus */
>+	{ 0x7390, &arcturus_device_info },	/* Arcturus vf */
> 	{ 0x7310, &navi10_device_info },	/* Navi10 */
> 	{ 0x7312, &navi10_device_info },	/* Navi10 */
> 	{ 0x7318, &navi10_device_info },	/* Navi10 */
>@@ -536,6 +574,10 @@
> 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
> 			kfd->cwsr_isa = cwsr_trap_gfx8_hex;
> 			kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
>+		} else if (kfd->device_info->asic_family == CHIP_ARCTURUS) {
>+			BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
>+			kfd->cwsr_isa = cwsr_trap_arcturus_hex;
>+			kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
> 		} else if (kfd->device_info->asic_family < CHIP_NAVI10) {
> 			BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
> 			kfd->cwsr_isa = cwsr_trap_gfx9_hex;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c	2019-08-31 15:01:11.853736168 -0500
>@@ -880,8 +880,8 @@
> 	}
> 
> 	dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
>-	dqm->sdma_bitmap = (1ULL << get_num_sdma_queues(dqm)) - 1;
>-	dqm->xgmi_sdma_bitmap = (1ULL << get_num_xgmi_sdma_queues(dqm)) - 1;
>+	dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
>+	dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
> 
> 	return 0;
> }
>@@ -1019,8 +1019,8 @@
> 	dqm->sdma_queue_count = 0;
> 	dqm->xgmi_sdma_queue_count = 0;
> 	dqm->active_runlist = false;
>-	dqm->sdma_bitmap = (1ULL << get_num_sdma_queues(dqm)) - 1;
>-	dqm->xgmi_sdma_bitmap = (1ULL << get_num_xgmi_sdma_queues(dqm)) - 1;
>+	dqm->sdma_bitmap = ~0ULL >> (64 - get_num_sdma_queues(dqm));
>+	dqm->xgmi_sdma_bitmap = ~0ULL >> (64 - get_num_xgmi_sdma_queues(dqm));
> 
> 	INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
> 
>@@ -1786,6 +1786,7 @@
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
> 	case CHIP_RAVEN:
>+	case CHIP_ARCTURUS:
> 		device_queue_manager_init_v9(&dqm->asic_ops);
> 		break;
> 	case CHIP_NAVI10:
>@@ -1813,7 +1814,8 @@
> 	return NULL;
> }
> 
>-void deallocate_hiq_sdma_mqd(struct kfd_dev *dev, struct kfd_mem_obj *mqd)
>+static void deallocate_hiq_sdma_mqd(struct kfd_dev *dev,
>+				    struct kfd_mem_obj *mqd)
> {
> 	WARN(!mqd, "No hiq sdma mqd trunk to free");
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c	2019-08-31 15:01:11.853736168 -0500
>@@ -405,6 +405,7 @@
> 			case CHIP_VEGA12:
> 			case CHIP_VEGA20:
> 			case CHIP_RAVEN:
>+			case CHIP_ARCTURUS:
> 			case CHIP_NAVI10:
> 				kfd_init_apertures_v9(pdd, id);
> 				break;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c	2019-08-31 15:01:11.853736168 -0500
>@@ -80,6 +80,7 @@
> 		source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG ||
> 		source_id == SOC15_INTSRC_CP_BAD_OPCODE ||
> 		client_id == SOC15_IH_CLIENTID_VMC ||
>+		client_id == SOC15_IH_CLIENTID_VMC1 ||
> 		client_id == SOC15_IH_CLIENTID_UTCL2;
> }
> 
>@@ -104,6 +105,7 @@
> 	else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE)
> 		kfd_signal_hw_exception_event(pasid);
> 	else if (client_id == SOC15_IH_CLIENTID_VMC ||
>+		client_id == SOC15_IH_CLIENTID_VMC1 ||
> 		 client_id == SOC15_IH_CLIENTID_UTCL2) {
> 		struct kfd_vm_fault_info info = {0};
> 		uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c	2019-08-31 15:01:11.853736168 -0500
>@@ -330,6 +330,7 @@
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
> 	case CHIP_RAVEN:
>+	case CHIP_ARCTURUS:
> 		kernel_queue_init_v9(&kq->ops_asic_specific);
> 		break;
> 	case CHIP_NAVI10:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_v9.c	2019-08-31 15:01:11.853736168 -0500
>@@ -81,7 +81,8 @@
> 	packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
> 	packet->bitfields2.process_quantum = 1;
> 	packet->bitfields2.pasid = qpd->pqm->process->pasid;
>-	packet->bitfields14.gds_size = qpd->gds_size;
>+	packet->bitfields14.gds_size = qpd->gds_size & 0x3F;
>+	packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF;
> 	packet->bitfields14.num_gws = qpd->num_gws;
> 	packet->bitfields14.num_oac = qpd->num_oac;
> 	packet->bitfields14.sdma_enable = 1;
>@@ -143,6 +144,34 @@
> 	return 0;
> }
> 
>+static int pm_set_resources_v9(struct packet_manager *pm, uint32_t *buffer,
>+				struct scheduling_resources *res)
>+{
>+	struct pm4_mes_set_resources *packet;
>+
>+	packet = (struct pm4_mes_set_resources *)buffer;
>+	memset(buffer, 0, sizeof(struct pm4_mes_set_resources));
>+
>+	packet->header.u32All = pm_build_pm4_header(IT_SET_RESOURCES,
>+					sizeof(struct pm4_mes_set_resources));
>+
>+	packet->bitfields2.queue_type =
>+			queue_type__mes_set_resources__hsa_interface_queue_hiq;
>+	packet->bitfields2.vmid_mask = res->vmid_mask;
>+	packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100;
>+	packet->bitfields7.oac_mask = res->oac_mask;
>+	packet->bitfields8.gds_heap_base = res->gds_heap_base;
>+	packet->bitfields8.gds_heap_size = res->gds_heap_size;
>+
>+	packet->gws_mask_lo = lower_32_bits(res->gws_mask);
>+	packet->gws_mask_hi = upper_32_bits(res->gws_mask);
>+
>+	packet->queue_mask_lo = lower_32_bits(res->queue_mask);
>+	packet->queue_mask_hi = upper_32_bits(res->queue_mask);
>+
>+	return 0;
>+}
>+
> static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer,
> 		struct queue *q, bool is_static)
> {
>@@ -161,6 +190,8 @@
> 	packet->bitfields2.engine_sel =
> 		engine_sel__mes_map_queues__compute_vi;
> 	packet->bitfields2.gws_control_queue = q->gws ? 1 : 0;
>+	packet->bitfields2.extended_engine_sel =
>+		extended_engine_sel__mes_map_queues__legacy_engine_sel;
> 	packet->bitfields2.queue_type =
> 		queue_type__mes_map_queues__normal_compute_vi;
> 
>@@ -176,9 +207,15 @@
> 		break;
> 	case KFD_QUEUE_TYPE_SDMA:
> 	case KFD_QUEUE_TYPE_SDMA_XGMI:
>-		packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
>-				engine_sel__mes_map_queues__sdma0_vi;
> 		use_static = false; /* no static queues under SDMA */
>+		if (q->properties.sdma_engine_id < 2)
>+			packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
>+				engine_sel__mes_map_queues__sdma0_vi;
>+		else {
>+			packet->bitfields2.extended_engine_sel =
>+				extended_engine_sel__mes_map_queues__sdma0_to_7_sel;
>+			packet->bitfields2.engine_sel = q->properties.sdma_engine_id;
>+		}
> 		break;
> 	default:
> 		WARN(1, "queue type %d", q->properties.type);
>@@ -218,13 +255,23 @@
> 	switch (type) {
> 	case KFD_QUEUE_TYPE_COMPUTE:
> 	case KFD_QUEUE_TYPE_DIQ:
>+		packet->bitfields2.extended_engine_sel =
>+			extended_engine_sel__mes_unmap_queues__legacy_engine_sel;
> 		packet->bitfields2.engine_sel =
> 			engine_sel__mes_unmap_queues__compute;
> 		break;
> 	case KFD_QUEUE_TYPE_SDMA:
> 	case KFD_QUEUE_TYPE_SDMA_XGMI:
>-		packet->bitfields2.engine_sel =
>-			engine_sel__mes_unmap_queues__sdma0 + sdma_engine;
>+		if (sdma_engine < 2) {
>+			packet->bitfields2.extended_engine_sel =
>+				extended_engine_sel__mes_unmap_queues__legacy_engine_sel;
>+			packet->bitfields2.engine_sel =
>+				engine_sel__mes_unmap_queues__sdma0 + sdma_engine;
>+		} else {
>+			packet->bitfields2.extended_engine_sel =
>+				extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel;
>+			packet->bitfields2.engine_sel = sdma_engine;
>+		}
> 		break;
> 	default:
> 		WARN(1, "queue type %d", type);
>@@ -326,7 +373,7 @@
> const struct packet_manager_funcs kfd_v9_pm_funcs = {
> 	.map_process		= pm_map_process_v9,
> 	.runlist		= pm_runlist_v9,
>-	.set_resources		= pm_set_resources_vi,
>+	.set_resources		= pm_set_resources_v9,
> 	.map_queues		= pm_map_queues_v9,
> 	.unmap_queues		= pm_unmap_queues_v9,
> 	.query_status		= pm_query_status_v9,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c	2019-08-31 15:01:11.853736168 -0500
>@@ -98,8 +98,8 @@
> 		uint32_t *se_mask)
> {
> 	struct kfd_cu_info cu_info;
>-	uint32_t cu_per_sh[4] = {0};
>-	int i, se, cu = 0;
>+	uint32_t cu_per_se[KFD_MAX_NUM_SE] = {0};
>+	int i, se, sh, cu = 0;
> 
> 	amdgpu_amdkfd_get_cu_info(mm->dev->kgd, &cu_info);
> 
>@@ -107,8 +107,8 @@
> 		cu_mask_count = cu_info.cu_active_number;
> 
> 	for (se = 0; se < cu_info.num_shader_engines; se++)
>-		for (i = 0; i < 4; i++)
>-			cu_per_sh[se] += hweight32(cu_info.cu_bitmap[se][i]);
>+		for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++)
>+			cu_per_se[se] += hweight32(cu_info.cu_bitmap[se % 4][sh + (se / 4)]);
> 
> 	/* Symmetrically map cu_mask to all SEs:
> 	 * cu_mask[0] bit0 -> se_mask[0] bit0;
>@@ -128,6 +128,6 @@
> 				se = 0;
> 				cu++;
> 			}
>-		} while (cu >= cu_per_sh[se] && cu < 32);
>+		} while (cu >= cu_per_se[se] && cu < 32);
> 	}
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h	2019-08-31 15:01:11.853736168 -0500
>@@ -26,6 +26,8 @@
> 
> #include "kfd_priv.h"
> 
>+#define KFD_MAX_NUM_SE 8
>+
> /**
>  * struct mqd_manager
>  *
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c	2019-08-31 15:01:11.854736168 -0500
>@@ -46,7 +46,7 @@
> 			struct queue_properties *q)
> {
> 	struct v9_mqd *m;
>-	uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
>+	uint32_t se_mask[KFD_MAX_NUM_SE] = {0};
> 
> 	if (q->cu_mask_count == 0)
> 		return;
>@@ -59,12 +59,20 @@
> 	m->compute_static_thread_mgmt_se1 = se_mask[1];
> 	m->compute_static_thread_mgmt_se2 = se_mask[2];
> 	m->compute_static_thread_mgmt_se3 = se_mask[3];
>+	m->compute_static_thread_mgmt_se4 = se_mask[4];
>+	m->compute_static_thread_mgmt_se5 = se_mask[5];
>+	m->compute_static_thread_mgmt_se6 = se_mask[6];
>+	m->compute_static_thread_mgmt_se7 = se_mask[7];
> 
>-	pr_debug("update cu mask to %#x %#x %#x %#x\n",
>+	pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n",
> 		m->compute_static_thread_mgmt_se0,
> 		m->compute_static_thread_mgmt_se1,
> 		m->compute_static_thread_mgmt_se2,
>-		m->compute_static_thread_mgmt_se3);
>+		m->compute_static_thread_mgmt_se3,
>+		m->compute_static_thread_mgmt_se4,
>+		m->compute_static_thread_mgmt_se5,
>+		m->compute_static_thread_mgmt_se6,
>+		m->compute_static_thread_mgmt_se7);
> }
> 
> static void set_priority(struct v9_mqd *m, struct queue_properties *q)
>@@ -125,6 +133,10 @@
> 	m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
> 	m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
> 	m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
>+	m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF;
>+	m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF;
>+	m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF;
>+	m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF;
> 
> 	m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
> 			0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c	2019-08-31 15:01:11.854736168 -0500
>@@ -239,6 +239,7 @@
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
> 	case CHIP_RAVEN:
>+	case CHIP_ARCTURUS:
> 		pm->pmf = &kfd_v9_pm_funcs;
> 		break;
> 	case CHIP_NAVI10:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h	2019-08-31 15:01:11.854736168 -0500
>@@ -83,10 +83,10 @@
> 
> 	union {
> 		struct {
>-		uint32_t gds_heap_base:6;
>-		uint32_t reserved3:5;
>-		uint32_t gds_heap_size:6;
>-		uint32_t reserved4:15;
>+		uint32_t gds_heap_base:10;
>+		uint32_t reserved3:1;
>+		uint32_t gds_heap_size:10;
>+		uint32_t reserved4:11;
> 		} bitfields8;
> 		uint32_t ordinal8;
> 	};
>@@ -179,7 +179,7 @@
> 			uint32_t num_gws:7;
> 			uint32_t sdma_enable:1;
> 			uint32_t num_oac:4;
>-			uint32_t reserved8:4;
>+			uint32_t gds_size_hi:4;
> 			uint32_t gds_size:6;
> 			uint32_t num_queues:10;
> 		} bitfields14;
>@@ -260,6 +260,10 @@
> 	engine_sel__mes_map_queues__sdma1_vi = 3
> };
> 
>+enum mes_map_queues_extended_engine_sel_enum {
>+	extended_engine_sel__mes_map_queues__legacy_engine_sel = 0,
>+	extended_engine_sel__mes_map_queues__sdma0_to_7_sel = 1
>+};
> 
> struct pm4_mes_map_queues {
> 	union {
>@@ -269,7 +273,8 @@
> 
> 	union {
> 		struct {
>-			uint32_t reserved1:4;
>+			uint32_t reserved1:2;
>+			enum mes_map_queues_extended_engine_sel_enum extended_engine_sel:2;
> 			enum mes_map_queues_queue_sel_enum queue_sel:2;
> 			uint32_t reserved5:6;
> 			uint32_t gws_control_queue:1;
>@@ -382,6 +387,11 @@
> 	engine_sel__mes_unmap_queues__sdmal = 3
> };
> 
>+enum mes_unmap_queues_extended_engine_sel_enum {
>+	extended_engine_sel__mes_unmap_queues__legacy_engine_sel = 0,
>+	extended_engine_sel__mes_unmap_queues__sdma0_to_7_sel = 1
>+};
>+
> struct pm4_mes_unmap_queues {
> 	union {
> 		union PM4_MES_TYPE_3_HEADER   header;            /* header */
>@@ -391,7 +401,7 @@
> 	union {
> 		struct {
> 			enum mes_unmap_queues_action_enum action:2;
>-			uint32_t reserved1:2;
>+			enum mes_unmap_queues_extended_engine_sel_enum extended_engine_sel:2;
> 			enum mes_unmap_queues_queue_sel_enum queue_sel:2;
> 			uint32_t reserved2:20;
> 			enum mes_unmap_queues_engine_sel_enum engine_sel:3;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_priv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_priv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_priv.h	2019-08-31 15:01:11.854736168 -0500
>@@ -195,6 +195,7 @@
> 
> struct kfd_device_info {
> 	enum amd_asic_type asic_family;
>+	const char *asic_name;
> 	const struct kfd_event_interrupt_class *event_interrupt_class;
> 	unsigned int max_pasid_bits;
> 	unsigned int max_no_of_hqd;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_process.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_process.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_process.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_process.c	2019-08-31 15:01:11.854736168 -0500
>@@ -801,6 +801,8 @@
> 		return ret;
> 	}
> 
>+	amdgpu_vm_set_task_info(pdd->vm);
>+
> 	ret = kfd_process_device_reserve_ib_mem(pdd);
> 	if (ret)
> 		goto err_reserve_ib_mem;
>@@ -1042,7 +1044,6 @@
> {
> 	struct delayed_work *dwork;
> 	struct kfd_process *p;
>-	struct kfd_process_device *pdd;
> 	int ret = 0;
> 
> 	dwork = to_delayed_work(work);
>@@ -1051,16 +1052,6 @@
> 	 * lifetime of this thread, kfd_process p will be valid
> 	 */
> 	p = container_of(dwork, struct kfd_process, restore_work);
>-
>-	/* Call restore_process_bos on the first KGD device. This function
>-	 * takes care of restoring the whole process including other devices.
>-	 * Restore can fail if enough memory is not available. If so,
>-	 * reschedule again.
>-	 */
>-	pdd = list_first_entry(&p->per_device_data,
>-			       struct kfd_process_device,
>-			       per_device_list);
>-
> 	pr_debug("Started restoring pasid %d\n", p->pasid);
> 
> 	/* Setting last_restore_timestamp before successful restoration.
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_topology.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_topology.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_topology.c	2019-08-31 15:01:11.854736168 -0500
>@@ -406,8 +406,6 @@
> 		char *buffer)
> {
> 	struct kfd_topology_device *dev;
>-	char public_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
>-	uint32_t i;
> 	uint32_t log_max_watch_addr;
> 
> 	/* Making sure that the buffer is an empty string */
>@@ -422,14 +420,8 @@
> 	if (strcmp(attr->name, "name") == 0) {
> 		dev = container_of(attr, struct kfd_topology_device,
> 				attr_name);
>-		for (i = 0; i < KFD_TOPOLOGY_PUBLIC_NAME_SIZE; i++) {
>-			public_name[i] =
>-					(char)dev->node_props.marketing_name[i];
>-			if (dev->node_props.marketing_name[i] == 0)
>-				break;
>-		}
>-		public_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE-1] = 0x0;
>-		return sysfs_show_str_val(buffer, public_name);
>+
>+		return sysfs_show_str_val(buffer, dev->node_props.name);
> 	}
> 
> 	dev = container_of(attr, struct kfd_topology_device,
>@@ -1274,6 +1266,10 @@
> 	 */
> 
> 	amdgpu_amdkfd_get_cu_info(dev->gpu->kgd, &cu_info);
>+
>+	strncpy(dev->node_props.name, gpu->device_info->asic_name,
>+			KFD_TOPOLOGY_PUBLIC_NAME_SIZE);
>+
> 	dev->node_props.simd_arrays_per_engine =
> 		cu_info.num_shader_arrays_per_engine;
> 
>@@ -1321,6 +1317,7 @@
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
> 	case CHIP_RAVEN:
>+	case CHIP_ARCTURUS:
> 	case CHIP_NAVI10:
> 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
> 			HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_topology.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/amdkfd/kfd_topology.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/amdkfd/kfd_topology.h	2019-08-31 15:01:11.854736168 -0500
>@@ -27,7 +27,7 @@
> #include <linux/list.h>
> #include "kfd_crat.h"
> 
>-#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 128
>+#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32
> 
> #define HSA_CAP_HOT_PLUGGABLE			0x00000001
> #define HSA_CAP_ATS_PRESENT			0x00000002
>@@ -81,7 +81,7 @@
> 	int32_t  drm_render_minor;
> 	uint32_t num_sdma_engines;
> 	uint32_t num_sdma_xgmi_engines;
>-	uint16_t marketing_name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
>+	char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE];
> };
> 
> #define HSA_MEM_HEAP_TYPE_SYSTEM	0
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c	2019-08-31 15:01:12.261736204 -0500
>@@ -688,12 +688,15 @@
> 	 */
> 	if (adev->flags & AMD_IS_APU &&
> 	    adev->asic_type >= CHIP_CARRIZO &&
>-	    adev->asic_type < CHIP_RAVEN)
>+	    adev->asic_type <= CHIP_RAVEN)
> 		init_data.flags.gpu_vm_support = true;
> 
> 	if (amdgpu_dc_feature_mask & DC_FBC_MASK)
> 		init_data.flags.fbc_support = true;
> 
>+	if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
>+		init_data.flags.multi_mon_pp_mclk_switch = true;
>+
> 	init_data.flags.power_down_display_on_boot = true;
> 
> #ifdef CONFIG_DRM_AMD_DC_DCN2_0
>@@ -809,6 +812,9 @@
> 	case CHIP_VEGA12:
> 	case CHIP_VEGA20:
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
>+	case CHIP_RENOIR:
> 		return 0;
> 	case CHIP_RAVEN:
> 		if (ASICREV_IS_PICASSO(adev->external_rev_id))
>@@ -2358,7 +2364,12 @@
> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> 	case CHIP_RAVEN:
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>+	case CHIP_NAVI12:
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+#endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	case CHIP_RENOIR:
> #endif
> 		if (dcn10_register_irq_handlers(dm->adev)) {
> 			DRM_ERROR("DM: Failed to initialize IRQ\n");
>@@ -2428,8 +2439,7 @@
> {
> 	int ret;
> 	int s3_state;
>-	struct pci_dev *pdev = to_pci_dev(device);
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
>+	struct drm_device *drm_dev = dev_get_drvdata(device);
> 	struct amdgpu_device *adev = drm_dev->dev_private;
> 
> 	ret = kstrtoint(buf, 0, &s3_state);
>@@ -2515,10 +2525,23 @@
> #endif
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI12:
> 		adev->mode_info.num_crtc = 6;
> 		adev->mode_info.num_hpd = 6;
> 		adev->mode_info.num_dig = 6;
> 		break;
>+	case CHIP_NAVI14:
>+		adev->mode_info.num_crtc = 5;
>+		adev->mode_info.num_hpd = 5;
>+		adev->mode_info.num_dig = 5;
>+		break;
>+#endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	case CHIP_RENOIR:
>+		adev->mode_info.num_crtc = 4;
>+		adev->mode_info.num_hpd = 4;
>+		adev->mode_info.num_dig = 4;
>+		break;
> #endif
> 	default:
> 		DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
>@@ -2665,7 +2688,7 @@
> 			  const struct amdgpu_framebuffer *afb,
> 			  const enum surface_pixel_format format,
> 			  const enum dc_rotation_angle rotation,
>-			  const union plane_size *plane_size,
>+			  const struct plane_size *plane_size,
> 			  const union dc_tiling_info *tiling_info,
> 			  const uint64_t info,
> 			  struct dc_plane_dcc_param *dcc,
>@@ -2691,8 +2714,8 @@
> 		return -EINVAL;
> 
> 	input.format = format;
>-	input.surface_size.width = plane_size->grph.surface_size.width;
>-	input.surface_size.height = plane_size->grph.surface_size.height;
>+	input.surface_size.width = plane_size->surface_size.width;
>+	input.surface_size.height = plane_size->surface_size.height;
> 	input.swizzle_mode = tiling_info->gfx9.swizzle;
> 
> 	if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
>@@ -2710,9 +2733,9 @@
> 		return -EINVAL;
> 
> 	dcc->enable = 1;
>-	dcc->grph.meta_pitch =
>+	dcc->meta_pitch =
> 		AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
>-	dcc->grph.independent_64b_blks = i64b;
>+	dcc->independent_64b_blks = i64b;
> 
> 	dcc_address = get_dcc_address(afb->address, info);
> 	address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
>@@ -2728,7 +2751,7 @@
> 			     const enum dc_rotation_angle rotation,
> 			     const uint64_t tiling_flags,
> 			     union dc_tiling_info *tiling_info,
>-			     union plane_size *plane_size,
>+			     struct plane_size *plane_size,
> 			     struct dc_plane_dcc_param *dcc,
> 			     struct dc_plane_address *address)
> {
>@@ -2741,11 +2764,11 @@
> 	memset(address, 0, sizeof(*address));
> 
> 	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
>-		plane_size->grph.surface_size.x = 0;
>-		plane_size->grph.surface_size.y = 0;
>-		plane_size->grph.surface_size.width = fb->width;
>-		plane_size->grph.surface_size.height = fb->height;
>-		plane_size->grph.surface_pitch =
>+		plane_size->surface_size.x = 0;
>+		plane_size->surface_size.y = 0;
>+		plane_size->surface_size.width = fb->width;
>+		plane_size->surface_size.height = fb->height;
>+		plane_size->surface_pitch =
> 			fb->pitches[0] / fb->format->cpp[0];
> 
> 		address->type = PLN_ADDR_TYPE_GRAPHICS;
>@@ -2754,20 +2777,20 @@
> 	} else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
> 		uint64_t chroma_addr = afb->address + fb->offsets[1];
> 
>-		plane_size->video.luma_size.x = 0;
>-		plane_size->video.luma_size.y = 0;
>-		plane_size->video.luma_size.width = fb->width;
>-		plane_size->video.luma_size.height = fb->height;
>-		plane_size->video.luma_pitch =
>+		plane_size->surface_size.x = 0;
>+		plane_size->surface_size.y = 0;
>+		plane_size->surface_size.width = fb->width;
>+		plane_size->surface_size.height = fb->height;
>+		plane_size->surface_pitch =
> 			fb->pitches[0] / fb->format->cpp[0];
> 
>-		plane_size->video.chroma_size.x = 0;
>-		plane_size->video.chroma_size.y = 0;
>+		plane_size->chroma_size.x = 0;
>+		plane_size->chroma_size.y = 0;
> 		/* TODO: set these based on surface format */
>-		plane_size->video.chroma_size.width = fb->width / 2;
>-		plane_size->video.chroma_size.height = fb->height / 2;
>+		plane_size->chroma_size.width = fb->width / 2;
>+		plane_size->chroma_size.height = fb->height / 2;
> 
>-		plane_size->video.chroma_pitch =
>+		plane_size->chroma_pitch =
> 			fb->pitches[1] / fb->format->cpp[1];
> 
> 		address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
>@@ -2814,6 +2837,11 @@
> 	    adev->asic_type == CHIP_VEGA20 ||
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> 	    adev->asic_type == CHIP_NAVI10 ||
>+	    adev->asic_type == CHIP_NAVI14 ||
>+	    adev->asic_type == CHIP_NAVI12 ||
>+#endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	    adev->asic_type == CHIP_RENOIR ||
> #endif
> 	    adev->asic_type == CHIP_RAVEN) {
> 		/* Fill GFX9 params */
>@@ -2995,6 +3023,8 @@
> 	plane_info->visible = true;
> 	plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
> 
>+	plane_info->layer_index = 0;
>+
> 	ret = fill_plane_color_attributes(plane_state, plane_info->format,
> 					  &plane_info->color_space);
> 	if (ret)
>@@ -3060,6 +3090,7 @@
> 	dc_plane_state->global_alpha = plane_info.global_alpha;
> 	dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
> 	dc_plane_state->dcc = plane_info.dcc;
>+	dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
> 
> 	/*
> 	 * Always set input transfer function, since plane state is refreshed
>@@ -3503,6 +3534,10 @@
> 	bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
> 	int mode_refresh;
> 	int preferred_refresh = 0;
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	struct dsc_dec_dpcd_caps dsc_caps;
>+	uint32_t link_bandwidth_kbps;
>+#endif
> 
> 	struct dc_sink *sink = NULL;
> 	if (aconnector == NULL) {
>@@ -3575,17 +3610,23 @@
> 			&mode, &aconnector->base, con_state, old_stream);
> 
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>-	/* stream->timing.flags.DSC = 0; */
>-        /*  */
>-	/* if (aconnector->dc_link && */
>-	/* 		aconnector->dc_link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */
>-	/* 		aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) */
>-	/* 	if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */
>-	/* 			&aconnector->dc_link->dpcd_caps.dsc_caps, */
>-	/* 			dc_link_bandwidth_kbps(aconnector->dc_link, dc_link_get_link_cap(aconnector->dc_link)), */
>-	/* 			&stream->timing, */
>-	/* 			&stream->timing.dsc_cfg)) */
>-	/* 		stream->timing.flags.DSC = 1; */
>+	stream->timing.flags.DSC = 0;
>+
>+	if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
>+		dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
>+				      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
>+				      &dsc_caps);
>+		link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
>+							     dc_link_get_link_cap(aconnector->dc_link));
>+
>+		if (dsc_caps.is_dsc_supported)
>+			if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc,
>+						  &dsc_caps,
>+						  link_bandwidth_kbps,
>+						  &stream->timing,
>+						  &stream->timing.dsc_cfg))
>+				stream->timing.flags.DSC = 1;
>+	}
> #endif
> 
> 	update_stream_scaling_settings(&mode, dm_state, stream);
>@@ -3669,7 +3710,7 @@
> 	state->abm_level = cur->abm_level;
> 	state->vrr_supported = cur->vrr_supported;
> 	state->freesync_config = cur->freesync_config;
>-	state->crc_enabled = cur->crc_enabled;
>+	state->crc_src = cur->crc_src;
> 	state->cm_has_degamma = cur->cm_has_degamma;
> 	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
> 
>@@ -3739,6 +3780,7 @@
> 	.atomic_destroy_state = dm_crtc_destroy_state,
> 	.set_crc_source = amdgpu_dm_crtc_set_crc_source,
> 	.verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
>+	.get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
> 	.enable_vblank = dm_enable_vblank,
> 	.disable_vblank = dm_disable_vblank,
> };
>@@ -4458,7 +4500,7 @@
> 	}
> 
> 	if (plane->type != DRM_PLANE_TYPE_CURSOR)
>-		domain = amdgpu_display_supported_domains(adev);
>+		domain = amdgpu_display_supported_domains(adev, rbo->flags);
> 	else
> 		domain = AMDGPU_GEM_DOMAIN_VRAM;
> 
>@@ -4548,20 +4590,10 @@
> static int dm_plane_atomic_async_check(struct drm_plane *plane,
> 				       struct drm_plane_state *new_plane_state)
> {
>-	struct drm_plane_state *old_plane_state =
>-		drm_atomic_get_old_plane_state(new_plane_state->state, plane);
>-
> 	/* Only support async updates on cursor planes. */
> 	if (plane->type != DRM_PLANE_TYPE_CURSOR)
> 		return -EINVAL;
> 
>-	/*
>-	 * DRM calls prepare_fb and cleanup_fb on new_plane_state for
>-	 * async commits so don't allow fb changes.
>-	 */
>-	if (old_plane_state->fb != new_plane_state->fb)
>-		return -EINVAL;
>-
> 	return 0;
> }
> 
>@@ -5705,11 +5737,11 @@
> 		 * deadlock during GPU reset when this fence will not signal
> 		 * but we hold reservation lock for the BO.
> 		 */
>-		r = reservation_object_wait_timeout_rcu(abo->tbo.resv, true,
>+		r = reservation_object_wait_timeout_rcu(abo->tbo.base.resv, true,
> 							false,
> 							msecs_to_jiffies(5000));
> 		if (unlikely(r <= 0))
>-			DRM_ERROR("Waiting for fences timed out or interrupted!");
>+			DRM_ERROR("Waiting for fences timed out!");
> 
> 		/*
> 		 * TODO This might fail and hence better not used, wait
>@@ -5733,8 +5765,14 @@
> 		bundle->surface_updates[planes_count].plane_info =
> 			&bundle->plane_infos[planes_count];
> 
>+		/*
>+		 * Only allow immediate flips for fast updates that don't
>+		 * change FB pitch, DCC state, rotation or mirroing.
>+		 */
> 		bundle->flip_addrs[planes_count].flip_immediate =
>-				(crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
>+			(crtc->state->pageflip_flags &
>+			 DRM_MODE_PAGE_FLIP_ASYNC) != 0 &&
>+			acrtc_state->update_type == UPDATE_TYPE_FAST;
> 
> 		timestamp_ns = ktime_get_ns();
> 		bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
>@@ -5979,6 +6017,7 @@
> 	struct drm_crtc *crtc;
> 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
> 	int i;
>+	enum amdgpu_dm_pipe_crc_source source;
> 
> 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
> 				      new_crtc_state, i) {
>@@ -6004,9 +6043,11 @@
> 
> #ifdef CONFIG_DEBUG_FS
> 		/* The stream has changed so CRC capture needs to re-enabled. */
>-		if (dm_new_crtc_state->crc_enabled) {
>-			dm_new_crtc_state->crc_enabled = false;
>-			amdgpu_dm_crtc_set_crc_source(crtc, "auto");
>+		source = dm_new_crtc_state->crc_src;
>+		if (amdgpu_dm_is_valid_crc_source(source)) {
>+			amdgpu_dm_crtc_configure_crc_source(
>+				crtc, dm_new_crtc_state,
>+				dm_new_crtc_state->crc_src);
> 		}
> #endif
> 	}
>@@ -6057,23 +6098,8 @@
> 
> 		if (dm_old_crtc_state->interrupts_enabled &&
> 		    (!dm_new_crtc_state->interrupts_enabled ||
>-		     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
>-			/*
>-			 * Drop the extra vblank reference added by CRC
>-			 * capture if applicable.
>-			 */
>-			if (dm_new_crtc_state->crc_enabled)
>-				drm_crtc_vblank_put(crtc);
>-
>-			/*
>-			 * Only keep CRC capture enabled if there's
>-			 * still a stream for the CRTC.
>-			 */
>-			if (!dm_new_crtc_state->stream)
>-				dm_new_crtc_state->crc_enabled = false;
>-
>+		     drm_atomic_crtc_needs_modeset(new_crtc_state)))
> 			manage_dm_interrupts(adev, acrtc, false);
>-		}
> 	}
> 	/*
> 	 * Add check here for SoC's that support hardware cursor plane, to
>@@ -7045,6 +7071,12 @@
> 			continue;
> 
> 		for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
>+			const struct amdgpu_framebuffer *amdgpu_fb =
>+				to_amdgpu_framebuffer(new_plane_state->fb);
>+			struct dc_plane_info plane_info;
>+			struct dc_flip_addrs flip_addr;
>+			uint64_t tiling_flags;
>+
> 			new_plane_crtc = new_plane_state->crtc;
> 			old_plane_crtc = old_plane_state->crtc;
> 			new_dm_plane_state = to_dm_plane_state(new_plane_state);
>@@ -7088,6 +7120,24 @@
> 
> 			updates[num_plane].scaling_info = &scaling_info;
> 
>+			if (amdgpu_fb) {
>+				ret = get_fb_info(amdgpu_fb, &tiling_flags);
>+				if (ret)
>+					goto cleanup;
>+
>+				memset(&flip_addr, 0, sizeof(flip_addr));
>+
>+				ret = fill_dc_plane_info_and_addr(
>+					dm->adev, new_plane_state, tiling_flags,
>+					&plane_info,
>+					&flip_addr.address);
>+				if (ret)
>+					goto cleanup;
>+
>+				updates[num_plane].plane_info = &plane_info;
>+				updates[num_plane].flip_addr = &flip_addr;
>+			}
>+
> 			num_plane++;
> 		}
> 
>@@ -7284,6 +7334,26 @@
> 	if (ret)
> 		goto fail;
> 
>+	if (state->legacy_cursor_update) {
>+		/*
>+		 * This is a fast cursor update coming from the plane update
>+		 * helper, check if it can be done asynchronously for better
>+		 * performance.
>+		 */
>+		state->async_update =
>+			!drm_atomic_helper_async_check(dev, state);
>+
>+		/*
>+		 * Skip the remaining global validation if this is an async
>+		 * update. Cursor updates can be done without affecting
>+		 * state or bandwidth calcs and this avoids the performance
>+		 * penalty of locking the private state object and
>+		 * allocating a new dc_state.
>+		 */
>+		if (state->async_update)
>+			return 0;
>+	}
>+
> 	/* Check scaling and underscan changes*/
> 	/* TODO Removed scaling changes validation due to inability to commit
> 	 * new stream into context w\o causing full reset. Need to
>@@ -7336,13 +7406,37 @@
> 			ret = -EINVAL;
> 			goto fail;
> 		}
>-	} else if (state->legacy_cursor_update) {
>+	} else {
> 		/*
>-		 * This is a fast cursor update coming from the plane update
>-		 * helper, check if it can be done asynchronously for better
>-		 * performance.
>+		 * The commit is a fast update. Fast updates shouldn't change
>+		 * the DC context, affect global validation, and can have their
>+		 * commit work done in parallel with other commits not touching
>+		 * the same resource. If we have a new DC context as part of
>+		 * the DM atomic state from validation we need to free it and
>+		 * retain the existing one instead.
> 		 */
>-		state->async_update = !drm_atomic_helper_async_check(dev, state);
>+		struct dm_atomic_state *new_dm_state, *old_dm_state;
>+
>+		new_dm_state = dm_atomic_get_new_state(state);
>+		old_dm_state = dm_atomic_get_old_state(state);
>+
>+		if (new_dm_state && old_dm_state) {
>+			if (new_dm_state->context)
>+				dc_release_state(new_dm_state->context);
>+
>+			new_dm_state->context = old_dm_state->context;
>+
>+			if (old_dm_state->context)
>+				dc_retain_state(old_dm_state->context);
>+		}
>+	}
>+
>+	/* Store the overall update type for use later in atomic check. */
>+	for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
>+		struct dm_crtc_state *dm_new_crtc_state =
>+			to_dm_crtc_state(new_crtc_state);
>+
>+		dm_new_crtc_state->update_type = (int)overall_update_type;
> 	}
> 
> 	/* Must be success */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c	2019-08-31 15:01:11.854736168 -0500
>@@ -30,23 +30,57 @@
> #include "amdgpu_dm.h"
> #include "dc.h"
> 
>-enum amdgpu_dm_pipe_crc_source {
>-	AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
>-	AMDGPU_DM_PIPE_CRC_SOURCE_AUTO,
>-	AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
>-	AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
>+static const char *const pipe_crc_sources[] = {
>+	"none",
>+	"crtc",
>+	"crtc dither",
>+	"dprx",
>+	"dprx dither",
>+	"auto",
> };
> 
> static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
> {
> 	if (!source || !strcmp(source, "none"))
> 		return AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
>-	if (!strcmp(source, "auto"))
>-		return AMDGPU_DM_PIPE_CRC_SOURCE_AUTO;
>+	if (!strcmp(source, "auto") || !strcmp(source, "crtc"))
>+		return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC;
>+	if (!strcmp(source, "dprx"))
>+		return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX;
>+	if (!strcmp(source, "crtc dither"))
>+		return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER;
>+	if (!strcmp(source, "dprx dither"))
>+		return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER;
> 
> 	return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
> }
> 
>+static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src)
>+{
>+	return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) ||
>+	       (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER);
>+}
>+
>+static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src)
>+{
>+	return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) ||
>+	       (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER);
>+}
>+
>+static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src)
>+{
>+	return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) ||
>+	       (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) ||
>+	       (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE);
>+}
>+
>+const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
>+						  size_t *count)
>+{
>+	*count = ARRAY_SIZE(pipe_crc_sources);
>+	return pipe_crc_sources;
>+}
>+
> int
> amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
> 				 size_t *values_cnt)
>@@ -63,14 +97,52 @@
> 	return 0;
> }
> 
>-int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
>+int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
>+					struct dm_crtc_state *dm_crtc_state,
>+					enum amdgpu_dm_pipe_crc_source source)
> {
> 	struct amdgpu_device *adev = crtc->dev->dev_private;
>-	struct dm_crtc_state *crtc_state = to_dm_crtc_state(crtc->state);
>-	struct dc_stream_state *stream_state = crtc_state->stream;
>-	bool enable;
>+	struct dc_stream_state *stream_state = dm_crtc_state->stream;
>+	bool enable = amdgpu_dm_is_valid_crc_source(source);
>+	int ret = 0;
>+
>+	/* Configuration will be deferred to stream enable. */
>+	if (!stream_state)
>+		return 0;
>+
>+	mutex_lock(&adev->dm.dc_lock);
>+
>+	/* Enable CRTC CRC generation if necessary. */
>+	if (dm_is_crc_source_crtc(source)) {
>+		if (!dc_stream_configure_crc(stream_state->ctx->dc,
>+					     stream_state, enable, enable)) {
>+			ret = -EINVAL;
>+			goto unlock;
>+		}
>+	}
>+
>+	/* Configure dithering */
>+	if (!dm_need_crc_dither(source))
>+		dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8);
>+	else
>+		dc_stream_set_dither_option(stream_state,
>+					    DITHER_OPTION_DEFAULT);
> 
>+unlock:
>+	mutex_unlock(&adev->dm.dc_lock);
>+
>+	return ret;
>+}
>+
>+int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
>+{
> 	enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
>+	struct drm_crtc_commit *commit;
>+	struct dm_crtc_state *crtc_state;
>+	struct drm_dp_aux *aux = NULL;
>+	bool enable = false;
>+	bool enabled = false;
>+	int ret = 0;
> 
> 	if (source < 0) {
> 		DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
>@@ -78,41 +150,124 @@
> 		return -EINVAL;
> 	}
> 
>-	if (!stream_state) {
>-		DRM_ERROR("No stream state for CRTC%d\n", crtc->index);
>-		return -EINVAL;
>+	ret = drm_modeset_lock(&crtc->mutex, NULL);
>+	if (ret)
>+		return ret;
>+
>+	spin_lock(&crtc->commit_lock);
>+	commit = list_first_entry_or_null(&crtc->commit_list,
>+					  struct drm_crtc_commit, commit_entry);
>+	if (commit)
>+		drm_crtc_commit_get(commit);
>+	spin_unlock(&crtc->commit_lock);
>+
>+	if (commit) {
>+		/*
>+		 * Need to wait for all outstanding programming to complete
>+		 * in commit tail since it can modify CRC related fields and
>+		 * hardware state. Since we're holding the CRTC lock we're
>+		 * guaranteed that no other commit work can be queued off
>+		 * before we modify the state below.
>+		 */
>+		ret = wait_for_completion_interruptible_timeout(
>+			&commit->hw_done, 10 * HZ);
>+		if (ret)
>+			goto cleanup;
> 	}
> 
>-	enable = (source == AMDGPU_DM_PIPE_CRC_SOURCE_AUTO);
>+	enable = amdgpu_dm_is_valid_crc_source(source);
>+	crtc_state = to_dm_crtc_state(crtc->state);
> 
>-	mutex_lock(&adev->dm.dc_lock);
>-	if (!dc_stream_configure_crc(stream_state->ctx->dc, stream_state,
>-				     enable, enable)) {
>-		mutex_unlock(&adev->dm.dc_lock);
>-		return -EINVAL;
>+	/*
>+	 * USER REQ SRC | CURRENT SRC | BEHAVIOR
>+	 * -----------------------------
>+	 * None         | None        | Do nothing
>+	 * None         | CRTC        | Disable CRTC CRC, set default to dither
>+	 * None         | DPRX        | Disable DPRX CRC, need 'aux', set default to dither
>+	 * None         | CRTC DITHER | Disable CRTC CRC
>+	 * None         | DPRX DITHER | Disable DPRX CRC, need 'aux'
>+	 * CRTC         | XXXX        | Enable CRTC CRC, no dither
>+	 * DPRX         | XXXX        | Enable DPRX CRC, need 'aux', no dither
>+	 * CRTC DITHER  | XXXX        | Enable CRTC CRC, set dither
>+	 * DPRX DITHER  | XXXX        | Enable DPRX CRC, need 'aux', set dither
>+	 */
>+	if (dm_is_crc_source_dprx(source) ||
>+	    (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE &&
>+	     dm_is_crc_source_dprx(crtc_state->crc_src))) {
>+		struct amdgpu_dm_connector *aconn = NULL;
>+		struct drm_connector *connector;
>+		struct drm_connector_list_iter conn_iter;
>+
>+		drm_connector_list_iter_begin(crtc->dev, &conn_iter);
>+		drm_for_each_connector_iter(connector, &conn_iter) {
>+			if (!connector->state || connector->state->crtc != crtc)
>+				continue;
>+
>+			aconn = to_amdgpu_dm_connector(connector);
>+			break;
>+		}
>+		drm_connector_list_iter_end(&conn_iter);
>+
>+		if (!aconn) {
>+			DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
>+			ret = -EINVAL;
>+			goto cleanup;
>+		}
>+
>+		aux = &aconn->dm_dp_aux.aux;
>+
>+		if (!aux) {
>+			DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
>+			ret = -EINVAL;
>+			goto cleanup;
>+		}
> 	}
> 
>-	/* When enabling CRC, we should also disable dithering. */
>-	dc_stream_set_dither_option(stream_state,
>-				    enable ? DITHER_OPTION_TRUN8
>-					   : DITHER_OPTION_DEFAULT);
>-
>-	mutex_unlock(&adev->dm.dc_lock);
>+	if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) {
>+		ret = -EINVAL;
>+		goto cleanup;
>+	}
> 
> 	/*
> 	 * Reading the CRC requires the vblank interrupt handler to be
> 	 * enabled. Keep a reference until CRC capture stops.
> 	 */
>-	if (!crtc_state->crc_enabled && enable)
>-		drm_crtc_vblank_get(crtc);
>-	else if (crtc_state->crc_enabled && !enable)
>+	enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src);
>+	if (!enabled && enable) {
>+		ret = drm_crtc_vblank_get(crtc);
>+		if (ret)
>+			goto cleanup;
>+
>+		if (dm_is_crc_source_dprx(source)) {
>+			if (drm_dp_start_crc(aux, crtc)) {
>+				DRM_DEBUG_DRIVER("dp start crc failed\n");
>+				ret = -EINVAL;
>+				goto cleanup;
>+			}
>+		}
>+	} else if (enabled && !enable) {
> 		drm_crtc_vblank_put(crtc);
>+		if (dm_is_crc_source_dprx(source)) {
>+			if (drm_dp_stop_crc(aux)) {
>+				DRM_DEBUG_DRIVER("dp stop crc failed\n");
>+				ret = -EINVAL;
>+				goto cleanup;
>+			}
>+		}
>+	}
> 
>-	crtc_state->crc_enabled = enable;
>+	crtc_state->crc_src = source;
> 
> 	/* Reset crc_skipped on dm state */
> 	crtc_state->crc_skip_count = 0;
>-	return 0;
>+
>+cleanup:
>+	if (commit)
>+		drm_crtc_commit_put(commit);
>+
>+	drm_modeset_unlock(&crtc->mutex);
>+
>+	return ret;
> }
> 
> /**
>@@ -135,7 +290,7 @@
> 	stream_state = crtc_state->stream;
> 
> 	/* Early return if CRC capture is not enabled. */
>-	if (!crtc_state->crc_enabled)
>+	if (!amdgpu_dm_is_valid_crc_source(crtc_state->crc_src))
> 		return;
> 
> 	/*
>@@ -149,10 +304,12 @@
> 		return;
> 	}
> 
>-	if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
>-			       &crcs[0], &crcs[1], &crcs[2]))
>-		return;
>+	if (dm_is_crc_source_crtc(crtc_state->crc_src)) {
>+		if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
>+				       &crcs[0], &crcs[1], &crcs[2]))
>+			return;
> 
>-	drm_crtc_add_crc_entry(crtc, true,
>-			       drm_crtc_accurate_vblank_count(crtc), crcs);
>+		drm_crtc_add_crc_entry(crtc, true,
>+				       drm_crtc_accurate_vblank_count(crtc), crcs);
>+	}
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h	2019-08-31 15:01:11.854736168 -0500
>@@ -0,0 +1,67 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifndef AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
>+#define AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_
>+
>+struct drm_crtc;
>+struct dm_crtc_state;
>+
>+enum amdgpu_dm_pipe_crc_source {
>+	AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0,
>+	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC,
>+	AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER,
>+	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX,
>+	AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER,
>+	AMDGPU_DM_PIPE_CRC_SOURCE_MAX,
>+	AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1,
>+};
>+
>+static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
>+{
>+	return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&
>+	       (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);
>+}
>+
>+/* amdgpu_dm_crc.c */
>+#ifdef CONFIG_DEBUG_FS
>+int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
>+					struct dm_crtc_state *dm_crtc_state,
>+					enum amdgpu_dm_pipe_crc_source source);
>+int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
>+int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
>+				     const char *src_name,
>+				     size_t *values_cnt);
>+const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
>+						  size_t *count);
>+void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
>+#else
>+#define amdgpu_dm_crtc_set_crc_source NULL
>+#define amdgpu_dm_crtc_verify_crc_source NULL
>+#define amdgpu_dm_crtc_get_crc_sources NULL
>+#define amdgpu_dm_crtc_handle_crc_irq(x)
>+#endif
>+
>+#endif /* AMD_DAL_DEV_AMDGPU_DM_AMDGPU_DM_CRC_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c	2019-08-31 15:01:11.855736168 -0500
>@@ -1053,9 +1053,33 @@
> 	return 0;
> }
> 
>+static int mst_topo(struct seq_file *m, void *unused)
>+{
>+	struct drm_info_node *node = (struct drm_info_node *)m->private;
>+	struct drm_device *dev = node->minor->dev;
>+	struct drm_connector *connector;
>+	struct drm_connector_list_iter conn_iter;
>+	struct amdgpu_dm_connector *aconnector;
>+
>+	drm_connector_list_iter_begin(dev, &conn_iter);
>+	drm_for_each_connector_iter(connector, &conn_iter) {
>+		if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
>+			continue;
>+
>+		aconnector = to_amdgpu_dm_connector(connector);
>+
>+		seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
>+		drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
>+	}
>+	drm_connector_list_iter_end(&conn_iter);
>+
>+	return 0;
>+}
>+
> static const struct drm_info_list amdgpu_dm_debugfs_list[] = {
> 	{"amdgpu_current_backlight_pwm", &current_backlight_read},
> 	{"amdgpu_target_backlight_pwm", &target_backlight_read},
>+	{"amdgpu_mst_topology", &mst_topo},
> };
> 
> /*
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h	2019-08-31 15:01:11.854736168 -0500
>@@ -50,6 +50,7 @@
> 
> #include "irq_types.h"
> #include "signal_types.h"
>+#include "amdgpu_dm_crc.h"
> 
> /* Forward declarations */
> struct amdgpu_device;
>@@ -309,11 +310,12 @@
> 	bool cm_has_degamma;
> 	bool cm_is_degamma_srgb;
> 
>+	int update_type;
> 	int active_planes;
> 	bool interrupts_enabled;
> 
> 	int crc_skip_count;
>-	bool crc_enabled;
>+	enum amdgpu_dm_pipe_crc_source crc_src;
> 
> 	bool freesync_timing_changed;
> 	bool freesync_vrr_info_changed;
>@@ -380,19 +382,6 @@
> void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
> 					struct edid *edid);
> 
>-/* amdgpu_dm_crc.c */
>-#ifdef CONFIG_DEBUG_FS
>-int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
>-int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
>-				     const char *src_name,
>-				     size_t *values_cnt);
>-void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
>-#else
>-#define amdgpu_dm_crtc_set_crc_source NULL
>-#define amdgpu_dm_crtc_verify_crc_source NULL
>-#define amdgpu_dm_crtc_handle_crc_irq(x)
>-#endif
>-
> #define MAX_COLOR_LUT_ENTRIES 4096
> /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
> #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c	2019-08-31 15:01:11.855736168 -0500
>@@ -548,7 +548,9 @@
> 		bool enable
> )
> {
>-	return false;
>+	uint8_t enable_dsc = enable ? 1 : 0;
>+
>+	return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);
> }
> #endif
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c	2019-08-31 15:01:11.855736168 -0500
>@@ -156,6 +156,26 @@
> 	kfree(amdgpu_dm_connector);
> }
> 
>+static int
>+amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
>+{
>+	struct amdgpu_dm_connector *amdgpu_dm_connector =
>+		to_amdgpu_dm_connector(connector);
>+	struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
>+
>+	return drm_dp_mst_connector_late_register(connector, port);
>+}
>+
>+static void
>+amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
>+{
>+	struct amdgpu_dm_connector *amdgpu_dm_connector =
>+		to_amdgpu_dm_connector(connector);
>+	struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
>+
>+	drm_dp_mst_connector_early_unregister(connector, port);
>+}
>+
> static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
> 	.detect = dm_dp_mst_detect,
> 	.fill_modes = drm_helper_probe_single_connector_modes,
>@@ -164,7 +184,9 @@
> 	.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
> 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> 	.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
>-	.atomic_get_property = amdgpu_dm_connector_atomic_get_property
>+	.atomic_get_property = amdgpu_dm_connector_atomic_get_property,
>+	.late_register = amdgpu_dm_mst_connector_late_register,
>+	.early_unregister = amdgpu_dm_mst_connector_early_unregister,
> };
> 
> static int dm_dp_mst_get_modes(struct drm_connector *connector)
>@@ -388,7 +410,7 @@
> 				       struct amdgpu_dm_connector *aconnector)
> {
> 	aconnector->dm_dp_aux.aux.name = "dmdc";
>-	aconnector->dm_dp_aux.aux.dev = dm->adev->dev;
>+	aconnector->dm_dp_aux.aux.dev = aconnector->base.kdev;
> 	aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
> 	aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c	2019-08-31 15:01:11.855736168 -0500
>@@ -151,18 +151,31 @@
> static enum smu_clk_type dc_to_smu_clock_type(
> 		enum dm_pp_clock_type dm_pp_clk_type)
> {
>-#define DCCLK_MAP_SMUCLK(dcclk, smuclk) \
>-	[dcclk] = smuclk
>+	enum smu_clk_type smu_clk_type = SMU_CLK_COUNT;
> 
>-	static int dc_clk_type_map[] = {
>-		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DISPLAY_CLK,	SMU_DISPCLK),
>-		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_ENGINE_CLK,	SMU_GFXCLK),
>-		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_MEMORY_CLK,	SMU_MCLK),
>-		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_DCEFCLK,	SMU_DCEFCLK),
>-		DCCLK_MAP_SMUCLK(DM_PP_CLOCK_TYPE_SOCCLK,	SMU_SOCCLK),
>-	};
>+	switch (dm_pp_clk_type) {
>+	case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
>+		smu_clk_type = SMU_DISPCLK;
>+		break;
>+	case DM_PP_CLOCK_TYPE_ENGINE_CLK:
>+		smu_clk_type = SMU_GFXCLK;
>+		break;
>+	case DM_PP_CLOCK_TYPE_MEMORY_CLK:
>+		smu_clk_type = SMU_MCLK;
>+		break;
>+	case DM_PP_CLOCK_TYPE_DCEFCLK:
>+		smu_clk_type = SMU_DCEFCLK;
>+		break;
>+	case DM_PP_CLOCK_TYPE_SOCCLK:
>+		smu_clk_type = SMU_SOCCLK;
>+		break;
>+	default:
>+		DRM_ERROR("DM_PPLIB: invalid clock type: %d!\n",
>+			  dm_pp_clk_type);
>+		break;
>+	}
> 
>-	return dc_clk_type_map[dm_pp_clk_type];
>+	return smu_clk_type;
> }
> 
> static enum amd_pp_clock_type dc_to_pp_clock_type(
>@@ -334,7 +347,7 @@
> 		}
> 	} else if (adev->smu.funcs && adev->smu.funcs->get_clock_by_type) {
> 		if (smu_get_clock_by_type(&adev->smu,
>-					  dc_to_smu_clock_type(clk_type),
>+					  dc_to_pp_clock_type(clk_type),
> 					  &pp_clks)) {
> 			get_default_clock_levels(clk_type, dc_clks);
> 			return true;
>@@ -419,7 +432,7 @@
> 			return false;
> 	} else if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->get_clock_by_type_with_latency) {
> 		if (smu_get_clock_by_type_with_latency(&adev->smu,
>-						       dc_to_pp_clock_type(clk_type),
>+						       dc_to_smu_clock_type(clk_type),
> 						       &pp_clks))
> 			return false;
> 	}
>@@ -801,6 +814,19 @@
> 	return PP_SMU_RESULT_OK;
> }
> 
>+enum pp_smu_status pp_nv_set_pstate_handshake_support(
>+	struct pp_smu *pp, BOOLEAN pstate_handshake_supported)
>+{
>+	const struct dc_context *ctx = pp->dm;
>+	struct amdgpu_device *adev = ctx->driver_context;
>+	struct smu_context *smu = &adev->smu;
>+
>+	if (smu_display_disable_memory_clock_switch(smu, !pstate_handshake_supported))
>+		return PP_SMU_RESULT_FAIL;
>+
>+	return PP_SMU_RESULT_OK;
>+}
>+
> enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
> 		enum pp_smu_nv_clock_id clock_id, int mhz)
> {
>@@ -916,6 +942,7 @@
> 		funcs->nv_funcs.get_maximum_sustainable_clocks = pp_nv_get_maximum_sustainable_clocks;
> 		/*todo  compare data with window driver */
> 		funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
>+		funcs->nv_funcs.set_pstate_handshake_support = pp_nv_set_pstate_handshake_support;
> 		break;
> #endif
> 	default:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c	2019-08-31 15:01:11.855736168 -0500
>@@ -1881,8 +1881,6 @@
> 
> 	.get_device_tag = bios_parser_get_device_tag,
> 
>-	.get_firmware_info = bios_parser_get_firmware_info,
>-
> 	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
> 
> 	.get_ss_entry_number = bios_parser_get_ss_entry_number,
>@@ -1998,6 +1996,7 @@
> 	dal_bios_parser_init_cmd_tbl_helper2(&bp->cmd_helper, dce_version);
> 
> 	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
>+	bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
> 
> 	return true;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c	2019-08-31 15:01:11.855736168 -0500
>@@ -2796,8 +2796,6 @@
> 
> 	.get_device_tag = bios_parser_get_device_tag,
> 
>-	.get_firmware_info = bios_parser_get_firmware_info,
>-
> 	.get_spread_spectrum_info = bios_parser_get_spread_spectrum_info,
> 
> 	.get_ss_entry_number = bios_parser_get_ss_entry_number,
>@@ -2922,6 +2920,7 @@
> 	dal_bios_parser_init_cmd_tbl_helper(&bp->cmd_helper, dce_version);
> 
> 	bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base);
>+	bp->base.fw_info_valid = bios_parser_get_firmware_info(&bp->base, &bp->base.fw_info) == BP_RESULT_OK;
> 
> 	return true;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c	2019-08-31 15:01:11.856736168 -0500
>@@ -67,6 +67,11 @@
> 		*h = dal_cmd_tbl_helper_dce112_get_table2();
> 		return true;
> #endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	case DCN_VERSION_2_1:
>+		*h = dal_cmd_tbl_helper_dce112_get_table2();
>+		return true;
>+#endif
> 	case DCE_VERSION_12_0:
> 	case DCE_VERSION_12_1:
> 		*h = dal_cmd_tbl_helper_dce112_get_table2();
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/dce110/command_table_helper_dce110.c	2019-08-31 15:01:11.856736168 -0500
>@@ -153,38 +153,10 @@
> 
> static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
> {
>-	uint8_t atom_dig_encoder_sel = 0;
>-
>-	switch (id) {
>-	case ENGINE_ID_DIGA:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
>-		break;
>-	case ENGINE_ID_DIGB:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGB_SEL;
>-		break;
>-	case ENGINE_ID_DIGC:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGC_SEL;
>-		break;
>-	case ENGINE_ID_DIGD:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGD_SEL;
>-		break;
>-	case ENGINE_ID_DIGE:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGE_SEL;
>-		break;
>-	case ENGINE_ID_DIGF:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGF_SEL;
>-		break;
>-	case ENGINE_ID_DIGG:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGG_SEL;
>-		break;
>-	case ENGINE_ID_UNKNOWN:
>-		 /* No DIG_FRONT is associated to DIG_BACKEND */
>-		atom_dig_encoder_sel = 0;
>-		break;
>-	default:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V5__DIGA_SEL;
>-		break;
>-	}
>+	/* On any ASIC after DCE80, we manually program the DIG_FE
>+	 * selection (see connect_dig_be_to_fe function of the link
>+	 * encoder), so translation should always return 0 (no FE).
>+	 */
> 
> 	return 0;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c	2019-08-31 15:01:11.856736168 -0500
>@@ -150,38 +150,10 @@
> 
> static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
> {
>-	uint8_t atom_dig_encoder_sel = 0;
>-
>-	switch (id) {
>-	case ENGINE_ID_DIGA:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
>-		break;
>-	case ENGINE_ID_DIGB:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
>-		break;
>-	case ENGINE_ID_DIGC:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
>-		break;
>-	case ENGINE_ID_DIGD:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
>-		break;
>-	case ENGINE_ID_DIGE:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
>-		break;
>-	case ENGINE_ID_DIGF:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
>-		break;
>-	case ENGINE_ID_DIGG:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
>-		break;
>-	case ENGINE_ID_UNKNOWN:
>-		/* No DIG_FRONT is associated to DIG_BACKEND */
>-		atom_dig_encoder_sel = 0;
>-		break;
>-	default:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
>-		break;
>-	}
>+	/* On any ASIC after DCE80, we manually program the DIG_FE
>+	 * selection (see connect_dig_be_to_fe function of the link
>+	 * encoder), so translation should always return 0 (no FE).
>+	 */
> 
> 	return 0;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper_dce112.c	2019-08-31 15:01:11.856736168 -0500
>@@ -150,38 +150,10 @@
> 
> static uint8_t dig_encoder_sel_to_atom(enum engine_id id)
> {
>-	uint8_t atom_dig_encoder_sel = 0;
>-
>-	switch (id) {
>-	case ENGINE_ID_DIGA:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
>-		break;
>-	case ENGINE_ID_DIGB:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGB_SEL;
>-		break;
>-	case ENGINE_ID_DIGC:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGC_SEL;
>-		break;
>-	case ENGINE_ID_DIGD:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGD_SEL;
>-		break;
>-	case ENGINE_ID_DIGE:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGE_SEL;
>-		break;
>-	case ENGINE_ID_DIGF:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGF_SEL;
>-		break;
>-	case ENGINE_ID_DIGG:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGG_SEL;
>-		break;
>-	case ENGINE_ID_UNKNOWN:
>-		/* No DIG_FRONT is associated to DIG_BACKEND */
>-		atom_dig_encoder_sel = 0;
>-		break;
>-	default:
>-		atom_dig_encoder_sel = ATOM_TRANMSITTER_V6__DIGA_SEL;
>-		break;
>-	}
>+	/* On any ASIC after DCE80, we manually program the DIG_FE
>+	 * selection (see connect_dig_be_to_fe function of the link
>+	 * encoder), so translation should always return 0 (no FE).
>+	 */
> 
> 	return 0;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c	2019-08-31 15:01:11.856736168 -0500
>@@ -25,6 +25,7 @@
> 
> #include <linux/slab.h>
> 
>+#include "resource.h"
> #include "dm_services.h"
> #include "dce_calcs.h"
> #include "dc.h"
>@@ -2852,7 +2853,7 @@
> 			data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);
> 			data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);
> 			data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed(
>-					pipe[i].bottom_pipe->plane_state->plane_size.grph.surface_pitch);
>+					pipe[i].bottom_pipe->plane_state->plane_size.surface_pitch);
> 			data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);
> 			data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps);
> 			data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
>@@ -2977,6 +2978,32 @@
> 	data->number_of_displays = num_displays;
> }
> 
>+static bool all_displays_in_sync(const struct pipe_ctx pipe[],
>+				 int pipe_count)
>+{
>+	const struct pipe_ctx *active_pipes[MAX_PIPES];
>+	int i, num_active_pipes = 0;
>+
>+	for (i = 0; i < pipe_count; i++) {
>+		if (!pipe[i].stream || pipe[i].top_pipe)
>+			continue;
>+
>+		active_pipes[num_active_pipes++] = &pipe[i];
>+	}
>+
>+	if (!num_active_pipes)
>+		return false;
>+
>+	for (i = 1; i < num_active_pipes; ++i) {
>+		if (!resource_are_streams_timing_synchronizable(
>+			    active_pipes[0]->stream, active_pipes[i]->stream)) {
>+			return false;
>+		}
>+	}
>+
>+	return true;
>+}
>+
> /**
>  * Return:
>  *	true -	Display(s) configuration supported.
>@@ -2998,8 +3025,10 @@
> 
> 	populate_initial_data(pipe, pipe_count, data);
> 
>-	/*TODO: this should be taken out calcs output and assigned during timing sync for pplib use*/
>-	calcs_output->all_displays_in_sync = false;
>+	if (ctx->dc->config.multi_mon_pp_mclk_switch)
>+		calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count);
>+	else
>+		calcs_output->all_displays_in_sync = false;
> 
> 	if (data->number_of_displays != 0) {
> 		uint8_t yclk_lvl, sclk_lvl;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c	2019-08-31 15:01:11.857736168 -0500
>@@ -329,7 +329,7 @@
> 			dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
> 	}
> 	input->src.dcc_rate            = 1;
>-	input->src.meta_pitch          = pipe->plane_state->dcc.grph.meta_pitch;
>+	input->src.meta_pitch          = pipe->plane_state->dcc.meta_pitch;
> 	input->src.source_scan         = dm_horz;
> 	input->src.sw_mode             = pipe->plane_state->tiling_info.gfx9.swizzle;
> 
>@@ -705,6 +705,13 @@
> 		hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
> }
> 
>+
>+unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev)
>+{
>+	/* we are ok with all levels */
>+	return 4;
>+}
>+
> bool dcn_validate_bandwidth(
> 		struct dc *dc,
> 		struct dc_state *context,
>@@ -732,6 +739,7 @@
> 
> 	memset(v, 0, sizeof(*v));
> 	kernel_fpu_begin();
>+
> 	v->sr_exit_time = dc->dcn_soc->sr_exit_time;
> 	v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
> 	v->urgent_latency = dc->dcn_soc->urgent_latency;
>@@ -1268,7 +1276,7 @@
> 	PERFORMANCE_TRACE_END();
> 	BW_VAL_TRACE_FINISH();
> 
>-	if (bw_limit_pass && v->voltage_level != 5)
>+	if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->ctx->asic_id.hw_internal_rev))
> 		return true;
> 	else
> 		return false;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/calcs/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/calcs/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/calcs/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/calcs/Makefile	2019-08-31 15:01:11.856736168 -0500
>@@ -32,6 +32,10 @@
> 
> calcs_ccflags := -mhard-float -msse $(cc_stack_align)
> 
>+ifdef CONFIG_CC_IS_CLANG
>+calcs_ccflags += -msse2
>+endif
>+
> CFLAGS_dcn_calcs.o := $(calcs_ccflags)
> CFLAGS_dcn_calc_auto.o := $(calcs_ccflags)
> CFLAGS_dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c	2019-08-31 15:01:11.857736168 -0500
>@@ -37,6 +37,9 @@
> #include "dcn10/rv1_clk_mgr.h"
> #include "dcn10/rv2_clk_mgr.h"
> #include "dcn20/dcn20_clk_mgr.h"
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+#include "dcn21/rn_clk_mgr.h"
>+#endif
> 
> 
> int clk_mgr_helper_get_active_display_cnt(
>@@ -108,6 +111,12 @@
> 
> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
> 	case FAMILY_RV:
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+		if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
>+			rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
>+			break;
>+		}
>+#endif	/* DCN2_1 */
> 		if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) {
> 			rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
> 			break;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c	2019-08-31 15:01:11.857736168 -0500
>@@ -273,18 +273,12 @@
> {
> 	struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug;
> 	struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
>-	struct integrated_info info = { { { 0 } } };
>-	struct dc_firmware_info fw_info = { { 0 } };
> 	int i;
> 
> 	if (bp->integrated_info)
>-		info = *bp->integrated_info;
>-
>-	clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq;
>+		clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
> 	if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
>-		bp->funcs->get_firmware_info(bp, &fw_info);
>-		clk_mgr_dce->dentist_vco_freq_khz =
>-			fw_info.smu_gpu_pll_output_freq;
>+		clk_mgr_dce->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
> 		if (clk_mgr_dce->dentist_vco_freq_khz == 0)
> 			clk_mgr_dce->dentist_vco_freq_khz = 3600000;
> 	}
>@@ -317,9 +311,10 @@
> 
> 		/*Do not allow bad VBIOS/SBIOS to override with invalid values,
> 		 * check for > 100MHz*/
>-		if (info.disp_clk_voltage[i].max_supported_clk >= 100000)
>-			clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
>-				info.disp_clk_voltage[i].max_supported_clk;
>+		if (bp->integrated_info)
>+			if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000)
>+				clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz =
>+					bp->integrated_info->disp_clk_voltage[i].max_supported_clk;
> 	}
> 
> 	if (!debug->disable_dfs_bypass && bp->integrated_info)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c	2019-08-31 15:01:11.857736168 -0500
>@@ -34,6 +34,11 @@
> #include "rv1_clk_mgr_vbios_smu.h"
> #include "rv1_clk_mgr_clk.h"
> 
>+void rv1_init_clocks(struct clk_mgr *clk_mgr)
>+{
>+	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
>+}
>+
> static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
> {
> 	bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
>@@ -232,6 +237,7 @@
> }
> 
> static struct clk_mgr_funcs rv1_clk_funcs = {
>+	.init_clocks = rv1_init_clocks,
> 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
> 	.update_clocks = rv1_update_clocks,
> 	.enable_pme_wa = rv1_enable_pme_wa,
>@@ -246,7 +252,6 @@
> {
> 	struct dc_debug_options *debug = &ctx->dc->debug;
> 	struct dc_bios *bp = ctx->dc_bios;
>-	struct dc_firmware_info fw_info = { { 0 } };
> 
> 	clk_mgr->base.ctx = ctx;
> 	clk_mgr->pp_smu = pp_smu;
>@@ -262,9 +267,8 @@
> 
> 	if (bp->integrated_info)
> 		clk_mgr->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
>-	if (clk_mgr->dentist_vco_freq_khz == 0) {
>-		bp->funcs->get_firmware_info(bp, &fw_info);
>-		clk_mgr->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq;
>+	if (bp->fw_info_valid && clk_mgr->dentist_vco_freq_khz == 0) {
>+		clk_mgr->dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
> 		if (clk_mgr->dentist_vco_freq_khz == 0)
> 			clk_mgr->dentist_vco_freq_khz = 3600000;
> 	}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c	2019-08-31 15:01:11.857736168 -0500
>@@ -26,8 +26,6 @@
> #include "dccg.h"
> #include "clk_mgr_internal.h"
> 
>-
>-#include "dcn20/dcn20_clk_mgr.h"
> #include "dce100/dce_clk_mgr.h"
> #include "reg_helper.h"
> #include "core_types.h"
>@@ -106,7 +104,6 @@
> {
> 	int i;
> 
>-	clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
> 	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
> 		int dpp_inst, dppclk_khz;
> 
>@@ -116,28 +113,75 @@
> 		dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
> 		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
> 		clk_mgr->dccg->funcs->update_dpp_dto(
>-				clk_mgr->dccg, dpp_inst, dppclk_khz);
>+				clk_mgr->dccg, dpp_inst, dppclk_khz, false);
> 	}
> }
> 
>-void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)
>+static void update_global_dpp_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz)
> {
> 	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
>-			* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
>-	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
>-			* clk_mgr->dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
>+			* clk_mgr->dentist_vco_freq_khz / khz;
> 
> 	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
>-	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
> 
> 	REG_UPDATE(DENTIST_DISPCLK_CNTL,
>-			DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
>-//	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 5, 100);
>-	REG_UPDATE(DENTIST_DISPCLK_CNTL,
> 			DENTIST_DPPCLK_WDIVIDER, dppclk_wdivider);
> 	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, 1, 5, 100);
> }
> 
>+static void update_display_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz)
>+{
>+	int disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
>+			* clk_mgr->dentist_vco_freq_khz / khz;
>+
>+	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
>+
>+	REG_UPDATE(DENTIST_DISPCLK_CNTL,
>+			DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
>+}
>+
>+static void request_voltage_and_program_disp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz)
>+{
>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
>+	struct dc *dc = clk_mgr_base->ctx->dc;
>+	struct pp_smu_funcs_nv *pp_smu = NULL;
>+	bool going_up = clk_mgr->base.clks.dispclk_khz < khz;
>+
>+	if (dc->res_pool->pp_smu)
>+		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
>+
>+	clk_mgr->base.clks.dispclk_khz = khz;
>+
>+	if (going_up && pp_smu && pp_smu->set_voltage_by_freq)
>+		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
>+
>+	update_display_clk(clk_mgr, khz);
>+
>+	if (!going_up && pp_smu && pp_smu->set_voltage_by_freq)
>+		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
>+}
>+
>+static void request_voltage_and_program_global_dpp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz)
>+{
>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
>+	struct dc *dc = clk_mgr_base->ctx->dc;
>+	struct pp_smu_funcs_nv *pp_smu = NULL;
>+	bool going_up = clk_mgr->base.clks.dppclk_khz < khz;
>+
>+	if (dc->res_pool->pp_smu)
>+		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
>+
>+	clk_mgr->base.clks.dppclk_khz = khz;
>+	clk_mgr->dccg->ref_dppclk = khz;
>+
>+	if (going_up && pp_smu && pp_smu->set_voltage_by_freq)
>+		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
>+
>+	update_global_dpp_clk(clk_mgr, khz);
>+
>+	if (!going_up && pp_smu && pp_smu->set_voltage_by_freq)
>+		pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
>+}
> 
> void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
> 			struct dc_state *context,
>@@ -148,12 +192,21 @@
> 	struct dc *dc = clk_mgr_base->ctx->dc;
> 	struct pp_smu_funcs_nv *pp_smu = NULL;
> 	int display_count;
>-	bool update_dppclk = false;
> 	bool update_dispclk = false;
> 	bool enter_display_off = false;
>-	bool dpp_clock_lowered = false;
> 	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
>+	bool force_reset = false;
>+	int i;
>+
>+	if (dc->work_arounds.skip_clock_update)
>+		return;
> 
>+	if (clk_mgr_base->clks.dispclk_khz == 0 ||
>+		dc->debug.force_clock_mode & 0x1) {
>+		//this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3.
>+		force_reset = true;
>+		//force_clock_mode 0x1:  force reset the clock even it is the same clock as long as it is in Passive level.
>+	}
> 	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
> 	if (dc->res_pool->pp_smu)
> 		pp_smu = &dc->res_pool->pp_smu->nv_funcs;
>@@ -172,6 +225,7 @@
> 			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 1000);
> 	}
> 
>+
> 	if (dc->debug.force_min_dcfclk_mhz > 0)
> 		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
> 				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
>@@ -196,10 +250,13 @@
> 	}
> 
> 	if (should_update_pstate_support(safe_to_lower, new_clocks->p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
>+		clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
>+
> 		clk_mgr_base->clks.p_state_change_support = new_clocks->p_state_change_support;
> 		if (pp_smu && pp_smu->set_pstate_handshake_support)
> 			pp_smu->set_pstate_handshake_support(&pp_smu->pp_smu, clk_mgr_base->clks.p_state_change_support);
> 	}
>+	clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
> 
> 	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
> 		clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
>@@ -207,35 +264,48 @@
> 			pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
> 	}
> 
>-	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
>-		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
>-			dpp_clock_lowered = true;
>-		clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
>+	if (dc->config.forced_clocks == false) {
>+		// First update display clock
>+		if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz))
>+			request_voltage_and_program_disp_clk(clk_mgr_base, new_clocks->dispclk_khz);
>+
>+		// Updating DPP clock requires some more logic
>+		if (!safe_to_lower) {
>+			// For pre-programming, we need to make sure any DPP clock that will go up has to go up
>+
>+			// First raise the global reference if needed
>+			if (new_clocks->dppclk_khz > clk_mgr_base->clks.dppclk_khz)
>+				request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
>+
>+			// Then raise any dividers that need raising
>+			for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
>+				int dpp_inst, dppclk_khz;
> 
>-		if (pp_smu && pp_smu->set_voltage_by_freq)
>-			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000);
>+				if (!context->res_ctx.pipe_ctx[i].plane_state)
>+					continue;
> 
>-		update_dppclk = true;
>-	}
>+				dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
>+				dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
> 
>-	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
>-		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
>-		if (pp_smu && pp_smu->set_voltage_by_freq)
>-			pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000);
>-
>-		update_dispclk = true;
>-	}
>-	if (dc->config.forced_clocks == false) {
>-		if (dpp_clock_lowered) {
>-			// if clock is being lowered, increase DTO before lowering refclk
>-			dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
>-			dcn20_update_clocks_update_dentist(clk_mgr);
>+				clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, true);
>+			}
> 		} else {
>-			// if clock is being raised, increase refclk before lowering DTO
>-			if (update_dppclk || update_dispclk)
>-				dcn20_update_clocks_update_dentist(clk_mgr);
>-			if (update_dppclk)
>-				dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
>+			// For post-programming, we can lower ref clk if needed, and unconditionally set all the DTOs
>+
>+			if (new_clocks->dppclk_khz < clk_mgr_base->clks.dppclk_khz)
>+				request_voltage_and_program_global_dpp_clk(clk_mgr_base, new_clocks->dppclk_khz);
>+
>+			for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
>+				int dpp_inst, dppclk_khz;
>+
>+				if (!context->res_ctx.pipe_ctx[i].plane_state)
>+					continue;
>+
>+				dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
>+				dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
>+
>+				clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, dpp_inst, dppclk_khz, false);
>+			}
> 		}
> 	}
> 	if (update_dispclk &&
>@@ -303,6 +373,7 @@
> 	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
> 	// Assumption is that boot state always supports pstate
> 	clk_mgr->clks.p_state_change_support = true;
>+	clk_mgr->clks.prev_p_state_change_support = true;
> }
> 
> void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base)
>@@ -318,11 +389,32 @@
> 	}
> }
> 
>+void dcn2_get_clock(struct clk_mgr *clk_mgr,
>+		struct dc_state *context,
>+			enum dc_clock_type clock_type,
>+			struct dc_clock_config *clock_cfg)
>+{
>+
>+	if (clock_type == DC_CLOCK_TYPE_DISPCLK) {
>+		clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
>+		clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz;
>+		clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz;
>+		clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
>+	}
>+	if (clock_type == DC_CLOCK_TYPE_DPPCLK) {
>+		clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
>+		clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz;
>+		clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz;
>+		clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
>+	}
>+}
>+
> static struct clk_mgr_funcs dcn2_funcs = {
> 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
> 	.update_clocks = dcn2_update_clocks,
> 	.init_clocks = dcn2_init_clocks,
>-	.enable_pme_wa = dcn2_enable_pme_wa
>+	.enable_pme_wa = dcn2_enable_pme_wa,
>+	.get_clock = dcn2_get_clock,
> };
> 
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h	2019-08-31 15:01:11.857736168 -0500
>@@ -45,4 +45,9 @@
> 
> uint32_t dentist_get_did_from_divider(int divider);
> 
>+void dcn2_get_clock(struct clk_mgr *clk_mgr,
>+		struct dc_state *context,
>+			enum dc_clock_type clock_type,
>+			struct dc_clock_config *clock_cfg);
>+
> #endif //__DCN20_CLK_MGR_H__
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c	2019-08-31 15:01:11.857736168 -0500
>@@ -0,0 +1,590 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#include "dccg.h"
>+#include "clk_mgr_internal.h"
>+
>+
>+#include "dcn20/dcn20_clk_mgr.h"
>+#include "rn_clk_mgr.h"
>+
>+
>+#include "dce100/dce_clk_mgr.h"
>+#include "rn_clk_mgr_vbios_smu.h"
>+#include "reg_helper.h"
>+#include "core_types.h"
>+#include "dm_helpers.h"
>+
>+#include "atomfirmware.h"
>+#include "clk/clk_10_0_2_offset.h"
>+#include "clk/clk_10_0_2_sh_mask.h"
>+#include "renoir_ip_offset.h"
>+
>+
>+/* Constants */
>+
>+#define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
>+
>+/* Macros */
>+
>+#define REG(reg_name) \
>+	(CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
>+
>+void rn_update_clocks(struct clk_mgr *clk_mgr_base,
>+			struct dc_state *context,
>+			bool safe_to_lower)
>+{
>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
>+	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
>+	struct dc *dc = clk_mgr_base->ctx->dc;
>+	int display_count;
>+	bool update_dppclk = false;
>+	bool update_dispclk = false;
>+	bool enter_display_off = false;
>+	bool dpp_clock_lowered = false;
>+	struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
>+
>+	display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
>+
>+	if (display_count == 0)
>+		enter_display_off = true;
>+
>+	if (enter_display_off == safe_to_lower) {
>+		rn_vbios_smu_set_display_count(clk_mgr, display_count);
>+	}
>+
>+	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
>+		clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
>+		rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
>+	}
>+
>+	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
>+		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
>+		rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
>+	}
>+
>+	if (should_set_clock(safe_to_lower,
>+			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
>+		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
>+		rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
>+	}
>+
>+	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
>+		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
>+			dpp_clock_lowered = true;
>+		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
>+		update_dppclk = true;
>+	}
>+
>+	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
>+		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
>+		rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
>+
>+		update_dispclk = true;
>+	}
>+
>+	if (dpp_clock_lowered) {
>+		// if clock is being lowered, increase DTO before lowering refclk
>+		dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
>+		rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
>+	} else {
>+		// if clock is being raised, increase refclk before lowering DTO
>+		if (update_dppclk || update_dispclk)
>+			rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
>+		if (update_dppclk)
>+			dcn20_update_clocks_update_dpp_dto(clk_mgr, context);
>+	}
>+
>+	if (update_dispclk &&
>+			dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
>+		/*update dmcu for wait_loop count*/
>+		dmcu->funcs->set_psr_wait_loop(dmcu,
>+			clk_mgr_base->clks.dispclk_khz / 1000 / 7);
>+	}
>+}
>+
>+
>+static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
>+{
>+	/* get FbMult value */
>+	struct fixed31_32 pll_req;
>+	unsigned int fbmult_frac_val = 0;
>+	unsigned int fbmult_int_val = 0;
>+
>+
>+	/*
>+	 * Register value of fbmult is in 8.16 format, we are converting to 31.32
>+	 * to leverage the fix point operations available in driver
>+	 */
>+
>+	REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
>+	REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
>+
>+	pll_req = dc_fixpt_from_int(fbmult_int_val);
>+
>+	/*
>+	 * since fractional part is only 16 bit in register definition but is 32 bit
>+	 * in our fix point definiton, need to shift left by 16 to obtain correct value
>+	 */
>+	pll_req.value |= fbmult_frac_val << 16;
>+
>+	/* multiply by REFCLK period */
>+	pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
>+
>+	/* integer part is now VCO frequency in kHz */
>+	return dc_fixpt_floor(pll_req);
>+}
>+
>+static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base)
>+{
>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
>+
>+	internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
>+	internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
>+
>+	internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);	//dcf deep sleep divider
>+	internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
>+
>+	internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
>+	internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
>+
>+	internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
>+	internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
>+
>+	internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
>+	internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
>+}
>+
>+/* This function collect raw clk register values */
>+static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
>+		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
>+{
>+	struct rn_clk_internal internal = {0};
>+	char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
>+	unsigned int chars_printed = 0;
>+	unsigned int remaining_buffer = log_info->bufSize;
>+
>+	rn_dump_clk_registers_internal(&internal, clk_mgr_base);
>+
>+	regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
>+	regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
>+	regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
>+	regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
>+	regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
>+	regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
>+
>+	regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
>+	if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
>+		regs_and_bypass->dppclk_bypass = 0;
>+	regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
>+	if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
>+		regs_and_bypass->dcfclk_bypass = 0;
>+	regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
>+	if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
>+		regs_and_bypass->dispclk_bypass = 0;
>+	regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
>+	if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
>+		regs_and_bypass->dprefclk_bypass = 0;
>+
>+	if (log_info->enabled) {
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
>+			regs_and_bypass->dcfclk,
>+			regs_and_bypass->dcf_deep_sleep_divider,
>+			regs_and_bypass->dcf_deep_sleep_allow,
>+			bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
>+			regs_and_bypass->dprefclk,
>+			bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
>+			regs_and_bypass->dispclk,
>+			bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		//split
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		// REGISTER VALUES
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
>+				internal.CLK1_CLK3_CURRENT_CNT);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
>+					internal.CLK1_CLK3_DS_CNTL);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
>+					internal.CLK1_CLK3_ALLOW_DS);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
>+					internal.CLK1_CLK2_CURRENT_CNT);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
>+					internal.CLK1_CLK0_CURRENT_CNT);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
>+					internal.CLK1_CLK1_CURRENT_CNT);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
>+					internal.CLK1_CLK3_BYPASS_CNTL);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
>+					internal.CLK1_CLK2_BYPASS_CNTL);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
>+					internal.CLK1_CLK0_BYPASS_CNTL);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+
>+		chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
>+					internal.CLK1_CLK1_BYPASS_CNTL);
>+		remaining_buffer -= chars_printed;
>+		*log_info->sum_chars_printed += chars_printed;
>+		log_info->pBuf += chars_printed;
>+	}
>+}
>+
>+/* This function produce translated logical clk state values*/
>+void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
>+{
>+	struct clk_state_registers_and_bypass sb = { 0 };
>+	struct clk_log_info log_info = { 0 };
>+
>+	rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
>+
>+	s->dprefclk_khz = sb.dprefclk;
>+}
>+
>+void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
>+{
>+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
>+
>+	rn_vbios_smu_enable_pme_wa(clk_mgr);
>+}
>+
>+static struct clk_mgr_funcs dcn21_funcs = {
>+	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
>+	.update_clocks = rn_update_clocks,
>+	.init_clocks = dcn2_init_clocks,
>+	.enable_pme_wa = rn_enable_pme_wa,
>+	/* .dump_clk_registers = rn_dump_clk_registers */
>+};
>+
>+struct clk_bw_params rn_bw_params = {
>+	.vram_type = Ddr4MemType,
>+	.num_channels = 1,
>+	.clk_table = {
>+		.entries = {
>+			{
>+				.voltage = 0,
>+				.dcfclk_mhz = 400,
>+				.fclk_mhz = 400,
>+				.memclk_mhz = 800,
>+				.socclk_mhz = 0,
>+			},
>+			{
>+				.voltage = 0,
>+				.dcfclk_mhz = 483,
>+				.fclk_mhz = 800,
>+				.memclk_mhz = 1600,
>+				.socclk_mhz = 0,
>+			},
>+			{
>+				.voltage = 0,
>+				.dcfclk_mhz = 602,
>+				.fclk_mhz = 1067,
>+				.memclk_mhz = 1067,
>+				.socclk_mhz = 0,
>+			},
>+			{
>+				.voltage = 0,
>+				.dcfclk_mhz = 738,
>+				.fclk_mhz = 1333,
>+				.memclk_mhz = 1600,
>+				.socclk_mhz = 0,
>+			},
>+		},
>+
>+		.num_entries = 4,
>+	},
>+
>+	.wm_table = {
>+		.entries = {
>+			{
>+				.wm_inst = WM_A,
>+				.wm_type = WM_TYPE_PSTATE_CHG,
>+				.pstate_latency_us = 23.84,
>+				.valid = true,
>+			},
>+			{
>+				.wm_inst = WM_B,
>+				.wm_type = WM_TYPE_PSTATE_CHG,
>+				.pstate_latency_us = 23.84,
>+				.valid = true,
>+			},
>+			{
>+				.wm_inst = WM_C,
>+				.wm_type = WM_TYPE_PSTATE_CHG,
>+				.pstate_latency_us = 23.84,
>+				.valid = true,
>+			},
>+			{
>+				.wm_inst = WM_D,
>+				.wm_type = WM_TYPE_PSTATE_CHG,
>+				.pstate_latency_us = 23.84,
>+				.valid = true,
>+			},
>+		},
>+	}
>+};
>+
>+void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
>+{
>+	int i, num_valid_sets;
>+
>+	num_valid_sets = 0;
>+
>+	for (i = 0; i < WM_SET_COUNT; i++) {
>+		/* skip empty entries, the smu array has no holes*/
>+		if (!bw_params->wm_table.entries[i].valid)
>+			continue;
>+
>+		ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
>+		ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;;
>+		/* We will not select WM based on dcfclk, so leave it as unconstrained */
>+		ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
>+		ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
>+		/* fclk wil be used to select WM*/
>+
>+		if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
>+			if (i == 0)
>+				ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0;
>+			else {
>+				/* add 1 to make it non-overlapping with next lvl */
>+				ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = bw_params->clk_table.entries[i - 1].fclk_mhz + 1;
>+			}
>+			ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
>+
>+		} else {
>+			/* unconstrained for memory retraining */
>+			ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
>+			ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
>+
>+			/* Modify previous watermark range to cover up to max */
>+			ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
>+		}
>+		num_valid_sets++;
>+	}
>+
>+	ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
>+	ranges->num_reader_wm_sets = num_valid_sets;
>+
>+	/* modify the min and max to make sure we cover the whole range*/
>+	ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
>+	ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
>+	ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
>+	ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
>+
>+	/* This is for writeback only, does not matter currently as no writeback support*/
>+	ranges->num_writer_wm_sets = 1;
>+	ranges->writer_wm_sets[0].wm_inst = WM_A;
>+	ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
>+	ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
>+	ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
>+	ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
>+
>+}
>+
>+void clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct hw_asic_id *asic_id)
>+{
>+	int i;
>+
>+	ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
>+
>+	for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
>+		if (clock_table->FClocks[i].Freq == 0)
>+			break;
>+
>+		bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i].Freq;
>+		bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[i].Freq;
>+		bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[i].Freq;
>+		bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i].Freq;
>+		bw_params->clk_table.entries[i].voltage = clock_table->FClocks[i].Vol;
>+	}
>+	bw_params->clk_table.num_entries = i;
>+
>+	bw_params->vram_type = asic_id->vram_type;
>+	bw_params->num_channels = asic_id->vram_width / DDR4_DRAM_WIDTH;
>+
>+	for (i = 0; i < WM_SET_COUNT; i++) {
>+		bw_params->wm_table.entries[i].wm_inst = i;
>+
>+		if (clock_table->FClocks[i].Freq == 0) {
>+			bw_params->wm_table.entries[i].valid = false;
>+			continue;
>+		}
>+
>+		bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
>+		bw_params->wm_table.entries[i].valid = true;
>+	}
>+
>+	if (bw_params->vram_type == LpDdr4MemType) {
>+		/*
>+		 * WM set D will be re-purposed for memory retraining
>+		 */
>+		bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
>+		bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
>+		bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
>+		bw_params->wm_table.entries[WM_D].valid = true;
>+	}
>+
>+}
>+
>+void rn_clk_mgr_construct(
>+		struct dc_context *ctx,
>+		struct clk_mgr_internal *clk_mgr,
>+		struct pp_smu_funcs *pp_smu,
>+		struct dccg *dccg)
>+{
>+	struct dc_debug_options *debug = &ctx->dc->debug;
>+	struct dpm_clocks clock_table = { 0 };
>+	struct clk_state_registers_and_bypass s = { 0 };
>+
>+	clk_mgr->base.ctx = ctx;
>+	clk_mgr->base.funcs = &dcn21_funcs;
>+
>+	clk_mgr->pp_smu = pp_smu;
>+
>+	clk_mgr->dccg = dccg;
>+	clk_mgr->dfs_bypass_disp_clk = 0;
>+
>+	clk_mgr->dprefclk_ss_percentage = 0;
>+	clk_mgr->dprefclk_ss_divider = 1000;
>+	clk_mgr->ss_on_dprefclk = false;
>+	clk_mgr->dfs_ref_freq_khz = 48000;
>+
>+	clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
>+
>+	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
>+		dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
>+		clk_mgr->dentist_vco_freq_khz = 3600000;
>+		clk_mgr->base.dprefclk_khz = 600000;
>+	} else {
>+		struct clk_log_info log_info = {0};
>+
>+		/* TODO: Check we get what we expect during bringup */
>+		clk_mgr->dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
>+
>+		/* in case we don't get a value from the register, use default */
>+		if (clk_mgr->dentist_vco_freq_khz == 0)
>+			clk_mgr->dentist_vco_freq_khz = 3600000;
>+
>+		rn_dump_clk_registers(&s, &clk_mgr->base, &log_info);
>+		clk_mgr->base.dprefclk_khz = s.dprefclk;
>+
>+		if (clk_mgr->base.dprefclk_khz != 600000) {
>+			clk_mgr->base.dprefclk_khz = 600000;
>+			ASSERT(1); //TODO: Renoir follow up.
>+		}
>+
>+		/* in case we don't get a value from the register, use default */
>+		if (clk_mgr->base.dprefclk_khz == 0)
>+			clk_mgr->base.dprefclk_khz = 600000;
>+	}
>+
>+	dce_clock_read_ss_info(clk_mgr);
>+
>+	clk_mgr->base.bw_params = &rn_bw_params;
>+
>+	if (pp_smu) {
>+		pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
>+		clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, &clock_table, &ctx->asic_id);
>+	}
>+
>+	/*
>+	 * Notify SMU which set of WM should be selected for different ranges of fclk
>+	 * On Renoir there is a maximumum of 4 DF pstates supported, could be less
>+	 * depending on DDR speed and fused maximum fclk.
>+	 */
>+	if (!debug->disable_pplib_wm_range) {
>+		struct pp_smu_wm_range_sets ranges = {0};
>+
>+		build_watermark_ranges(clk_mgr->base.bw_params, &ranges);
>+
>+		/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
>+		if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
>+			pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
>+	}
>+
>+	/* enable powerfeatures when displaycount goes to 0 */
>+	if (!debug->disable_48mhz_pwrdwn)
>+		rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr);
>+}
>+
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.h	2019-08-31 15:01:11.857736168 -0500
>@@ -0,0 +1,39 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifndef __RN_CLK_MGR_H__
>+#define __RN_CLK_MGR_H__
>+
>+struct rn_clk_registers {
>+	uint32_t CLK1_CLK0_CURRENT_CNT; /* DPREFCLK */
>+};
>+
>+
>+void rn_clk_mgr_construct(struct dc_context *ctx,
>+		struct clk_mgr_internal *clk_mgr,
>+		struct pp_smu_funcs *pp_smu,
>+		struct dccg *dccg);
>+
>+#endif //__RN_CLK_MGR_H__
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c	2019-08-31 15:01:11.857736168 -0500
>@@ -0,0 +1,200 @@
>+/*
>+ * Copyright 2012-16 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#include "core_types.h"
>+#include "clk_mgr_internal.h"
>+#include "reg_helper.h"
>+
>+#include "renoir_ip_offset.h"
>+
>+#include "mp/mp_12_0_0_offset.h"
>+#include "mp/mp_12_0_0_sh_mask.h"
>+
>+#define REG(reg_name) \
>+	(MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
>+
>+#define FN(reg_name, field) \
>+	FD(reg_name##__##field)
>+
>+#define VBIOSSMC_MSG_TestMessage                  0x1
>+#define VBIOSSMC_MSG_GetSmuVersion                0x2
>+#define VBIOSSMC_MSG_PowerUpGfx                   0x3
>+#define VBIOSSMC_MSG_SetDispclkFreq               0x4
>+#define VBIOSSMC_MSG_SetDprefclkFreq              0x5
>+#define VBIOSSMC_MSG_PowerDownGfx                 0x6
>+#define VBIOSSMC_MSG_SetDppclkFreq                0x7
>+#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq       0x8
>+#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk        0x9
>+#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq       0xA
>+#define VBIOSSMC_MSG_GetFclkFrequency             0xB
>+#define VBIOSSMC_MSG_SetDisplayCount              0xC
>+#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD
>+#define VBIOSSMC_MSG_UpdatePmeRestore			  0xE
>+
>+int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
>+{
>+	/* First clear response register */
>+	REG_WRITE(MP1_SMN_C2PMSG_91, 0);
>+
>+	/* Set the parameter register for the SMU message, unit is Mhz */
>+	REG_WRITE(MP1_SMN_C2PMSG_83, param);
>+
>+	/* Trigger the message transaction by writing the message ID */
>+	REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
>+
>+	REG_WAIT(MP1_SMN_C2PMSG_91, CONTENT, 1, 10, 200000);
>+
>+	/* Actual dispclk set is returned in the parameter register */
>+	return REG_READ(MP1_SMN_C2PMSG_83);
>+}
>+
>+int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
>+{
>+	return rn_vbios_smu_send_msg_with_param(
>+			clk_mgr,
>+			VBIOSSMC_MSG_GetSmuVersion,
>+			0);
>+}
>+
>+
>+int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
>+{
>+	int actual_dispclk_set_mhz = -1;
>+	struct dc *core_dc = clk_mgr->base.ctx->dc;
>+	struct dmcu *dmcu = core_dc->res_pool->dmcu;
>+	uint32_t clk = requested_dispclk_khz / 1000;
>+
>+	if (clk <= 100)
>+		clk = 101;
>+
>+	/*  Unit of SMU msg parameter is Mhz */
>+	actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param(
>+			clk_mgr,
>+			VBIOSSMC_MSG_SetDispclkFreq,
>+			clk);
>+
>+	if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
>+		if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
>+			if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
>+				dmcu->funcs->set_psr_wait_loop(dmcu,
>+						actual_dispclk_set_mhz / 7);
>+		}
>+	}
>+
>+	return actual_dispclk_set_mhz * 1000;
>+}
>+
>+int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
>+{
>+	int actual_dprefclk_set_mhz = -1;
>+
>+	actual_dprefclk_set_mhz = rn_vbios_smu_send_msg_with_param(
>+			clk_mgr,
>+			VBIOSSMC_MSG_SetDprefclkFreq,
>+			clk_mgr->base.dprefclk_khz / 1000);
>+
>+	/* TODO: add code for programing DP DTO, currently this is down by command table */
>+
>+	return actual_dprefclk_set_mhz * 1000;
>+}
>+
>+int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
>+{
>+	int actual_dcfclk_set_mhz = -1;
>+
>+	if (clk_mgr->smu_ver < 0xFFFFFFFF)
>+		return actual_dcfclk_set_mhz;
>+
>+	actual_dcfclk_set_mhz = rn_vbios_smu_send_msg_with_param(
>+			clk_mgr,
>+			VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
>+			requested_dcfclk_khz / 1000);
>+
>+	return actual_dcfclk_set_mhz * 1000;
>+}
>+
>+int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
>+{
>+	int actual_min_ds_dcfclk_mhz = -1;
>+
>+	if (clk_mgr->smu_ver < 0xFFFFFFFF)
>+		return actual_min_ds_dcfclk_mhz;
>+
>+	actual_min_ds_dcfclk_mhz = rn_vbios_smu_send_msg_with_param(
>+			clk_mgr,
>+			VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
>+			requested_min_ds_dcfclk_khz / 1000);
>+
>+	return actual_min_ds_dcfclk_mhz * 1000;
>+}
>+
>+void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz)
>+{
>+	rn_vbios_smu_send_msg_with_param(
>+			clk_mgr,
>+			VBIOSSMC_MSG_SetPhyclkVoltageByFreq,
>+			requested_phyclk_khz / 1000);
>+}
>+
>+int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
>+{
>+	int actual_dppclk_set_mhz = -1;
>+
>+	uint32_t clk = requested_dpp_khz / 1000;
>+
>+	if (clk <= 100)
>+		clk = 101;
>+
>+	actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(
>+			clk_mgr,
>+			VBIOSSMC_MSG_SetDppclkFreq,
>+			clk);
>+
>+	return actual_dppclk_set_mhz * 1000;
>+}
>+
>+void rn_vbios_smu_set_display_count(struct clk_mgr_internal *clk_mgr, int display_count)
>+{
>+	rn_vbios_smu_send_msg_with_param(
>+			clk_mgr,
>+			VBIOSSMC_MSG_SetDisplayCount,
>+			display_count);
>+}
>+
>+void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr)
>+{
>+	rn_vbios_smu_send_msg_with_param(
>+			clk_mgr,
>+			VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown,
>+			0);
>+}
>+
>+void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
>+{
>+	rn_vbios_smu_send_msg_with_param(
>+			clk_mgr,
>+			VBIOSSMC_MSG_UpdatePmeRestore,
>+			0);
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h	2019-08-31 15:01:11.857736168 -0500
>@@ -0,0 +1,40 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifndef DAL_DC_RN_CLK_MGR_VBIOS_SMU_H_
>+#define DAL_DC_RN_CLK_MGR_VBIOS_SMU_H_
>+
>+int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
>+int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
>+int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
>+int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
>+int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
>+void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
>+int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
>+void rn_vbios_smu_set_display_count(struct clk_mgr_internal *clk_mgr, int display_count);
>+void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr);
>+void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
>+
>+#endif /* DAL_DC_DCN10_RV1_CLK_MGR_VBIOS_SMU_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile	2019-08-31 15:01:11.857736168 -0500
>@@ -85,3 +85,13 @@
> AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN20)
> endif
> 
>+ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+###############################################################################
>+# DCN21
>+###############################################################################
>+CLK_MGR_DCN21 = rn_clk_mgr.o rn_clk_mgr_vbios_smu.o
>+
>+AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21))
>+
>+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)
>+endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc.c	2019-08-31 15:01:12.256736203 -0500
>@@ -181,13 +181,25 @@
> 		link = link_create(&link_init_params);
> 
> 		if (link) {
>-			if (dc->config.edp_not_connected &&
>-					link->connector_signal == SIGNAL_TYPE_EDP) {
>-				link_destroy(&link);
>-			} else {
>+			bool should_destory_link = false;
>+
>+			if (link->connector_signal == SIGNAL_TYPE_EDP) {
>+				if (dc->config.edp_not_connected)
>+					should_destory_link = true;
>+				else if (dc->debug.remove_disconnect_edp) {
>+					enum dc_connection_type type;
>+					dc_link_detect_sink(link, &type);
>+					if (type == dc_connection_none)
>+						should_destory_link = true;
>+				}
>+			}
>+
>+			if (!should_destory_link) {
> 				dc->links[dc->link_count] = link;
> 				link->dc = dc;
> 				++dc->link_count;
>+			} else {
>+				link_destroy(&link);
> 			}
> 		}
> 	}
>@@ -279,7 +291,9 @@
> 			dc->hwss.set_drr(&pipe,
> 					1,
> 					adjust->v_total_min,
>-					adjust->v_total_max);
>+					adjust->v_total_max,
>+					adjust->v_total_mid,
>+					adjust->v_total_mid_frame_num);
> 
> 			ret = true;
> 		}
>@@ -675,6 +689,11 @@
> 	if (!dc->clk_mgr)
> 		goto fail;
> 
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+	if (dc->res_pool->funcs->update_bw_bounding_box)
>+		dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
>+#endif
>+
> 	/* Creation of current_state must occur after dc->dml
> 	 * is initialized in dc_create_resource_pool because
> 	 * on creation it copies the contents of dc->dml
>@@ -948,7 +967,7 @@
> {
> 	struct timing_generator *tg;
> 	struct dc_link *link = sink->link;
>-	unsigned int inst;
>+	unsigned int enc_inst, tg_inst;
> 
> 	/* Check for enabled DIG to identify enabled display */
> 	if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
>@@ -960,13 +979,22 @@
> 	 * current implementation always map 1-to-1, so this code makes
> 	 * the same assumption and doesn't check OTG source.
> 	 */
>-	inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
>+	enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
> 
> 	/* Instance should be within the range of the pool */
>-	if (inst >= dc->res_pool->pipe_count)
>+	if (enc_inst >= dc->res_pool->pipe_count)
>+		return false;
>+
>+	if (enc_inst >= dc->res_pool->stream_enc_count)
> 		return false;
> 
>-	tg = dc->res_pool->timing_generators[inst];
>+	tg_inst = dc->res_pool->stream_enc[enc_inst]->funcs->dig_source_otg(
>+		dc->res_pool->stream_enc[enc_inst]);
>+
>+	if (tg_inst >= dc->res_pool->timing_generator_count)
>+		return false;
>+
>+	tg = dc->res_pool->timing_generators[tg_inst];
> 
> 	if (!tg->funcs->is_matching_timing)
> 		return false;
>@@ -979,10 +1007,11 @@
> 
> 		dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
> 			dc->res_pool->dp_clock_source,
>-			inst, &pix_clk_100hz);
>+			tg_inst, &pix_clk_100hz);
> 
> 		if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
> 			return false;
>+
> 	}
> 
> 	return true;
>@@ -1065,7 +1094,7 @@
> 	if (result != DC_OK)
> 		return result;
> 
>-	if (context->stream_count > 1) {
>+	if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
> 		enable_timing_multisync(dc, context);
> 		program_timing_sync(dc, context);
> 	}
>@@ -1208,6 +1237,12 @@
> 			if (cur_pipe->bottom_pipe)
> 				cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
> 
>+			if (cur_pipe->prev_odm_pipe)
>+				cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
>+
>+			if (cur_pipe->next_odm_pipe)
>+				cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
>+
> 	}
> 
> 	for (i = 0; i < new_ctx->stream_count; i++) {
>@@ -1239,6 +1274,55 @@
> 	kref_put(&context->refcount, dc_state_free);
> }
> 
>+bool dc_set_generic_gpio_for_stereo(bool enable,
>+		struct gpio_service *gpio_service)
>+{
>+	enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
>+	struct gpio_pin_info pin_info;
>+	struct gpio *generic;
>+	struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
>+			   GFP_KERNEL);
>+
>+	if (!config)
>+		return false;
>+	pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
>+
>+	if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
>+		kfree(config);
>+		return false;
>+	} else {
>+		generic = dal_gpio_service_create_generic_mux(
>+			gpio_service,
>+			pin_info.offset,
>+			pin_info.mask);
>+	}
>+
>+	if (!generic) {
>+		kfree(config);
>+		return false;
>+	}
>+
>+	gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
>+
>+	config->enable_output_from_mux = enable;
>+	config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
>+
>+	if (gpio_result == GPIO_RESULT_OK)
>+		gpio_result = dal_mux_setup_config(generic, config);
>+
>+	if (gpio_result == GPIO_RESULT_OK) {
>+		dal_gpio_close(generic);
>+		dal_gpio_destroy_generic_mux(&generic);
>+		kfree(config);
>+		return true;
>+	} else {
>+		dal_gpio_close(generic);
>+		dal_gpio_destroy_generic_mux(&generic);
>+		kfree(config);
>+		return false;
>+	}
>+}
>+
> static bool is_surface_in_context(
> 		const struct dc_state *context,
> 		const struct dc_plane_state *plane_state)
>@@ -1305,8 +1389,8 @@
> 	}
> 
> 	if (u->plane_info->dcc.enable != u->surface->dcc.enable
>-			|| u->plane_info->dcc.grph.independent_64b_blks != u->surface->dcc.grph.independent_64b_blks
>-			|| u->plane_info->dcc.grph.meta_pitch != u->surface->dcc.grph.meta_pitch) {
>+			|| u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
>+			|| u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
> 		update_flags->bits.dcc_change = 1;
> 		elevate_update_type(&update_type, UPDATE_TYPE_MED);
> 	}
>@@ -1320,9 +1404,9 @@
> 		elevate_update_type(&update_type, UPDATE_TYPE_FULL);
> 	}
> 
>-	if (u->plane_info->plane_size.grph.surface_pitch != u->surface->plane_size.grph.surface_pitch
>-			|| u->plane_info->plane_size.video.luma_pitch != u->surface->plane_size.video.luma_pitch
>-			|| u->plane_info->plane_size.video.chroma_pitch != u->surface->plane_size.video.chroma_pitch) {
>+	if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
>+			|| u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
>+			|| u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
> 		update_flags->bits.plane_size_change = 1;
> 		elevate_update_type(&update_type, UPDATE_TYPE_MED);
> 	}
>@@ -1542,6 +1626,9 @@
> 		for (i = 0; i < surface_count; i++)
> 			updates[i].surface->update_flags.raw = 0xFFFFFFFF;
> 
>+	if (type == UPDATE_TYPE_FAST && memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0)
>+		dc->optimized_required = true;
>+
> 	return type;
> }
> 
>@@ -1618,6 +1705,8 @@
> 				srf_update->plane_info->dcc;
> 		surface->sdr_white_level =
> 				srf_update->plane_info->sdr_white_level;
>+		surface->layer_index =
>+				srf_update->plane_info->layer_index;
> 	}
> 
> 	if (srf_update->gamma &&
>@@ -1784,9 +1873,7 @@
> 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
> 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
> 
>-		if (!pipe_ctx->top_pipe &&
>-			pipe_ctx->stream &&
>-			pipe_ctx->stream == stream) {
>+		if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
> 
> 			if (stream_update->periodic_interrupt0 &&
> 					dc->hwss.setup_periodic_interrupt)
>@@ -1812,7 +1899,7 @@
> 
> 			if (stream_update->dither_option) {
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>-				struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
>+				struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
> #endif
> 				resource_build_bit_depth_reduction_params(pipe_ctx->stream,
> 									&pipe_ctx->stream->bit_depth_params);
>@@ -1820,10 +1907,12 @@
> 						&stream->bit_depth_params,
> 						&stream->clamping);
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>-				if (odm_pipe)
>+				while (odm_pipe) {
> 					odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
> 							&stream->bit_depth_params,
> 							&stream->clamping);
>+					odm_pipe = odm_pipe->next_odm_pipe;
>+				}
> #endif
> 			}
> 
>@@ -1840,13 +1929,21 @@
> 
> 			if (stream_update->dpms_off) {
> 				dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
>+
> 				if (*stream_update->dpms_off) {
>-					core_link_disable_stream(pipe_ctx, KEEP_ACQUIRED_RESOURCE);
>+					core_link_disable_stream(pipe_ctx);
>+					/* for dpms, keep acquired resources*/
>+					if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
>+						pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
>+
> 					dc->hwss.optimize_bandwidth(dc, dc->current_state);
> 				} else {
>-					dc->hwss.prepare_bandwidth(dc, dc->current_state);
>+					if (!dc->optimize_seamless_boot)
>+						dc->hwss.prepare_bandwidth(dc, dc->current_state);
>+
> 					core_link_enable_stream(dc->current_state, pipe_ctx);
> 				}
>+
> 				dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
> 			}
> 
>@@ -1936,6 +2033,7 @@
> 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
> 
> 		if (!pipe_ctx->top_pipe &&
>+			!pipe_ctx->prev_odm_pipe &&
> 			pipe_ctx->stream &&
> 			pipe_ctx->stream == stream) {
> 			struct dc_stream_status *stream_status = NULL;
>@@ -2050,7 +2148,7 @@
> 	enum surface_update_type update_type;
> 	struct dc_state *context;
> 	struct dc_context *dc_ctx = dc->ctx;
>-	int i, j;
>+	int i;
> 
> 	stream_status = dc_stream_get_status(stream);
> 	context = dc->current_state;
>@@ -2088,16 +2186,6 @@
> 
> 		copy_surface_update_to_plane(surface, &srf_updates[i]);
> 
>-		if (update_type >= UPDATE_TYPE_MED) {
>-			for (j = 0; j < dc->res_pool->pipe_count; j++) {
>-				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
>-
>-				if (pipe_ctx->plane_state != surface)
>-					continue;
>-
>-				resource_build_scaling_params(pipe_ctx);
>-			}
>-		}
> 	}
> 
> 	copy_stream_update_to_stream(dc, context, stream, stream_update);
>@@ -2187,6 +2275,14 @@
> 		dc_resource_state_construct(dc, dc->current_state);
> 
> 		dc->hwss.init_hw(dc);
>+
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
>+		if (dc->hwss.init_sys_ctx != NULL &&
>+			dc->vm_pa_config.valid) {
>+			dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
>+		}
>+#endif
>+
> 		break;
> 	default:
> 		ASSERT(dc->current_state->stream_count == 0);
>@@ -2387,3 +2483,14 @@
> 	info->fClock					= (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
> 	info->phyClock					= (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
> }
>+enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
>+{
>+	if (dc->hwss.set_clock)
>+		return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
>+	return DC_ERROR_UNEXPECTED;
>+}
>+void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
>+{
>+	if (dc->hwss.get_clock)
>+		dc->hwss.get_clock(dc, clock_type, clock_cfg);
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_debug.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_debug.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_debug.c	2019-08-31 15:01:11.857736168 -0500
>@@ -115,16 +115,16 @@
> 				plane_state->clip_rect.height);
> 
> 		SURFACE_TRACE(
>-				"plane_state->plane_size.grph.surface_size.x = %d;\n"
>-				"plane_state->plane_size.grph.surface_size.y = %d;\n"
>-				"plane_state->plane_size.grph.surface_size.width = %d;\n"
>-				"plane_state->plane_size.grph.surface_size.height = %d;\n"
>-				"plane_state->plane_size.grph.surface_pitch = %d;\n",
>-				plane_state->plane_size.grph.surface_size.x,
>-				plane_state->plane_size.grph.surface_size.y,
>-				plane_state->plane_size.grph.surface_size.width,
>-				plane_state->plane_size.grph.surface_size.height,
>-				plane_state->plane_size.grph.surface_pitch);
>+				"plane_state->plane_size.surface_size.x = %d;\n"
>+				"plane_state->plane_size.surface_size.y = %d;\n"
>+				"plane_state->plane_size.surface_size.width = %d;\n"
>+				"plane_state->plane_size.surface_size.height = %d;\n"
>+				"plane_state->plane_size.surface_pitch = %d;\n",
>+				plane_state->plane_size.surface_size.x,
>+				plane_state->plane_size.surface_size.y,
>+				plane_state->plane_size.surface_size.width,
>+				plane_state->plane_size.surface_size.height,
>+				plane_state->plane_size.surface_pitch);
> 
> 
> 		SURFACE_TRACE(
>@@ -202,20 +202,20 @@
> 			SURFACE_TRACE(
> 					"plane_info->color_space = %d;\n"
> 					"plane_info->format = %d;\n"
>-					"plane_info->plane_size.grph.surface_pitch = %d;\n"
>-					"plane_info->plane_size.grph.surface_size.height = %d;\n"
>-					"plane_info->plane_size.grph.surface_size.width = %d;\n"
>-					"plane_info->plane_size.grph.surface_size.x = %d;\n"
>-					"plane_info->plane_size.grph.surface_size.y = %d;\n"
>+					"plane_info->plane_size.surface_pitch = %d;\n"
>+					"plane_info->plane_size.surface_size.height = %d;\n"
>+					"plane_info->plane_size.surface_size.width = %d;\n"
>+					"plane_info->plane_size.surface_size.x = %d;\n"
>+					"plane_info->plane_size.surface_size.y = %d;\n"
> 					"plane_info->rotation = %d;\n"
> 					"plane_info->stereo_format = %d;\n",
> 					update->plane_info->color_space,
> 					update->plane_info->format,
>-					update->plane_info->plane_size.grph.surface_pitch,
>-					update->plane_info->plane_size.grph.surface_size.height,
>-					update->plane_info->plane_size.grph.surface_size.width,
>-					update->plane_info->plane_size.grph.surface_size.x,
>-					update->plane_info->plane_size.grph.surface_size.y,
>+					update->plane_info->plane_size.surface_pitch,
>+					update->plane_info->plane_size.surface_size.height,
>+					update->plane_info->plane_size.surface_size.width,
>+					update->plane_info->plane_size.surface_size.x,
>+					update->plane_info->plane_size.surface_size.y,
> 					update->plane_info->rotation,
> 					update->plane_info->stereo_format);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link.c	2019-08-31 15:01:11.858736168 -0500
>@@ -45,10 +45,6 @@
> #include "dpcd_defs.h"
> #include "dmcu.h"
> #include "hw/clk_mgr.h"
>-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>-#include "resource.h"
>-#endif
>-#include "hw/clk_mgr.h"
> 
> #define DC_LOGGER_INIT(logger)
> 
>@@ -684,6 +680,56 @@
> 	return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
> }
> 
>+bool wait_for_alt_mode(struct dc_link *link)
>+{
>+
>+	/**
>+	 * something is terribly wrong if time out is > 200ms. (5Hz)
>+	 * 500 microseconds * 400 tries us 200 ms
>+	 **/
>+	unsigned int sleep_time_in_microseconds = 500;
>+	unsigned int tries_allowed = 400;
>+	bool is_in_alt_mode;
>+	unsigned long long enter_timestamp;
>+	unsigned long long finish_timestamp;
>+	unsigned long long time_taken_in_ns;
>+	int tries_taken;
>+
>+	DC_LOGGER_INIT(link->ctx->logger);
>+
>+	if (link->link_enc->funcs->is_in_alt_mode == NULL)
>+		return true;
>+
>+	is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
>+	DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
>+
>+	if (is_in_alt_mode)
>+		return true;
>+
>+	enter_timestamp = dm_get_timestamp(link->ctx);
>+
>+	for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
>+		udelay(sleep_time_in_microseconds);
>+		/* ask the link if alt mode is enabled, if so return ok */
>+		if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
>+
>+			finish_timestamp = dm_get_timestamp(link->ctx);
>+			time_taken_in_ns = dm_get_elapse_time_in_ns(
>+				link->ctx, finish_timestamp, enter_timestamp);
>+			DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
>+				       div_u64(time_taken_in_ns, 1000000));
>+			return true;
>+		}
>+
>+	}
>+	finish_timestamp = dm_get_timestamp(link->ctx);
>+	time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
>+						    enter_timestamp);
>+	DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
>+			div_u64(time_taken_in_ns, 1000000));
>+	return false;
>+}
>+
> /**
>  * dc_link_detect() - Detect if a sink is attached to a given link
>  *
>@@ -772,6 +818,15 @@
> 		}
> 
> 		case SIGNAL_TYPE_DISPLAY_PORT: {
>+			/* wa HPD high coming too early*/
>+			if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
>+
>+				/* if alt mode times out, return false */
>+				if (wait_for_alt_mode(link) == false) {
>+					return false;
>+				}
>+			}
>+
> 			if (!detect_dp(
> 				link,
> 				&sink_caps,
>@@ -795,16 +850,9 @@
> 					dc_sink_release(prev_sink);
> 				} else {
> 					/* Empty dongle plug in */
>-					for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
>-						int fail_count = 0;
>-
>-						dp_verify_link_cap(link,
>-								  &link->reported_link_cap,
>-								  &fail_count);
>-
>-						if (fail_count == 0)
>-							break;
>-					}
>+					dp_verify_link_cap_with_retries(link,
>+							&link->reported_link_cap,
>+							LINK_TRAINING_MAX_VERIFY_RETRY);
> 				}
> 				return true;
> 			}
>@@ -908,17 +956,9 @@
> 			 */
> 
> 			/* deal with non-mst cases */
>-			for (i = 0; i < LINK_TRAINING_MAX_VERIFY_RETRY; i++) {
>-				int fail_count = 0;
>-
>-				dp_verify_link_cap(link,
>-						  &link->reported_link_cap,
>-						  &fail_count);
>-
>-				if (fail_count == 0)
>-					break;
>-			}
>-
>+			dp_verify_link_cap_with_retries(link,
>+					&link->reported_link_cap,
>+					LINK_TRAINING_MAX_VERIFY_RETRY);
> 		} else {
> 			// If edid is the same, then discard new sink and revert back to original sink
> 			if (same_edid) {
>@@ -1188,6 +1228,9 @@
> 	link->ctx = dc_ctx;
> 	link->link_index = init_params->link_index;
> 
>+	memset(&link->preferred_training_settings, 0, sizeof(struct dc_link_training_overrides));
>+	memset(&link->preferred_link_setting, 0, sizeof(struct dc_link_settings));
>+
> 	link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
> 
> 	if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
>@@ -1384,57 +1427,6 @@
> 	*link = NULL;
> }
> 
>-static void dpcd_configure_panel_mode(
>-	struct dc_link *link,
>-	enum dp_panel_mode panel_mode)
>-{
>-	union dpcd_edp_config edp_config_set;
>-	bool panel_mode_edp = false;
>-	DC_LOGGER_INIT(link->ctx->logger);
>-
>-	memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
>-
>-	if (DP_PANEL_MODE_DEFAULT != panel_mode) {
>-
>-		switch (panel_mode) {
>-		case DP_PANEL_MODE_EDP:
>-		case DP_PANEL_MODE_SPECIAL:
>-			panel_mode_edp = true;
>-			break;
>-
>-		default:
>-			break;
>-		}
>-
>-		/*set edp panel mode in receiver*/
>-		core_link_read_dpcd(
>-			link,
>-			DP_EDP_CONFIGURATION_SET,
>-			&edp_config_set.raw,
>-			sizeof(edp_config_set.raw));
>-
>-		if (edp_config_set.bits.PANEL_MODE_EDP
>-			!= panel_mode_edp) {
>-			enum ddc_result result = DDC_RESULT_UNKNOWN;
>-
>-			edp_config_set.bits.PANEL_MODE_EDP =
>-			panel_mode_edp;
>-			result = core_link_write_dpcd(
>-				link,
>-				DP_EDP_CONFIGURATION_SET,
>-				&edp_config_set.raw,
>-				sizeof(edp_config_set.raw));
>-
>-			ASSERT(result == DDC_RESULT_SUCESSFULL);
>-		}
>-	}
>-	DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
>-			"eDP panel mode enabled: %d \n",
>-			link->link_index,
>-			link->dpcd_caps.panel_mode_edp,
>-			panel_mode_edp);
>-}
>-
> static void enable_stream_features(struct pipe_ctx *pipe_ctx)
> {
> 	struct dc_stream_state *stream = pipe_ctx->stream;
>@@ -1466,6 +1458,19 @@
> 	struct dc_link *link = stream->link;
> 	struct dc_link_settings link_settings = {0};
> 	enum dp_panel_mode panel_mode;
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	bool fec_enable;
>+#endif
>+	int i;
>+	bool apply_seamless_boot_optimization = false;
>+
>+	// check for seamless boot
>+	for (i = 0; i < state->stream_count; i++) {
>+		if (state->streams[i]->apply_seamless_boot_optimization) {
>+			apply_seamless_boot_optimization = true;
>+			break;
>+		}
>+	}
> 
> 	/* get link settings for video mode timing */
> 	decide_link_settings(stream, &link_settings);
>@@ -1487,7 +1492,8 @@
> 
> 	pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
> 			link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
>-	state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
>+	if (!apply_seamless_boot_optimization)
>+		state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false);
> 
> 	dp_enable_link_phy(
> 		link,
>@@ -1502,18 +1508,19 @@
> 	}
> 
> 	panel_mode = dp_get_panel_mode(link);
>-	dpcd_configure_panel_mode(link, panel_mode);
>+	dp_set_panel_mode(link, panel_mode);
> 
> 	skip_video_pattern = true;
> 
> 	if (link_settings.link_rate == LINK_RATE_LOW)
> 			skip_video_pattern = false;
> 
>-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>-	dp_set_fec_ready(link, true);
>-#endif
>+	if (link->aux_access_disabled) {
>+		dc_link_dp_perform_link_training_skip_aux(link, &link_settings);
> 
>-	if (perform_link_training_with_retries(
>+		link->cur_link_settings = link_settings;
>+		status = DC_OK;
>+	} else if (perform_link_training_with_retries(
> 			link,
> 			&link_settings,
> 			skip_video_pattern,
>@@ -1525,7 +1532,12 @@
> 		status = DC_FAIL_DP_LINK_TRAINING;
> 
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>-	dp_set_fec_enable(link, true);
>+	if (link->preferred_training_settings.fec_enable != NULL)
>+		fec_enable = *link->preferred_training_settings.fec_enable;
>+	else
>+		fec_enable = true;
>+
>+	dp_set_fec_enable(link, fec_enable);
> #endif
> 	return status;
> }
>@@ -2755,21 +2767,27 @@
> 					CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
> 					COLOR_DEPTH_UNDEFINED);
> 
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+		if (pipe_ctx->stream->timing.flags.DSC) {
>+			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
>+					dc_is_virtual_signal(pipe_ctx->stream->signal))
>+				dp_set_dsc_enable(pipe_ctx, true);
>+		}
>+#endif
> 		core_dc->hwss.enable_stream(pipe_ctx);
> 
>-		if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
>-			allocate_mst_payload(pipe_ctx);
>-
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>-		if (pipe_ctx->stream->timing.flags.DSC &&
>-				(dc_is_dp_signal(pipe_ctx->stream->signal) ||
>-				dc_is_virtual_signal(pipe_ctx->stream->signal))) {
>-			dp_set_dsc_enable(pipe_ctx, true);
>-			pipe_ctx->stream_res.tg->funcs->wait_for_state(
>-					pipe_ctx->stream_res.tg,
>-					CRTC_STATE_VBLANK);
>+		/* Set DPS PPS SDP (AKA "info frames") */
>+		if (pipe_ctx->stream->timing.flags.DSC) {
>+			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
>+					dc_is_virtual_signal(pipe_ctx->stream->signal))
>+				dp_set_dsc_pps_sdp(pipe_ctx, true);
> 		}
> #endif
>+
>+		if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
>+			allocate_mst_payload(pipe_ctx);
>+
> 		core_dc->hwss.unblank_stream(pipe_ctx,
> 			&pipe_ctx->stream->link->cur_link_settings);
> 
>@@ -2786,7 +2804,7 @@
> #endif
> }
> 
>-void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
>+void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
> {
> 	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
> 	struct dc_stream_state *stream = pipe_ctx->stream;
>@@ -2821,13 +2839,13 @@
> 			write_i2c_redriver_setting(pipe_ctx, false);
> 		}
> 	}
>-	core_dc->hwss.disable_stream(pipe_ctx, option);
>+	core_dc->hwss.disable_stream(pipe_ctx);
> 
> 	disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>-	if (pipe_ctx->stream->timing.flags.DSC &&
>-			dc_is_dp_signal(pipe_ctx->stream->signal)) {
>-		dp_set_dsc_enable(pipe_ctx, false);
>+	if (pipe_ctx->stream->timing.flags.DSC) {
>+		if (dc_is_dp_signal(pipe_ctx->stream->signal))
>+			dp_set_dsc_enable(pipe_ctx, false);
> 	}
> #endif
> }
>@@ -2836,7 +2854,7 @@
> {
> 	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;
> 
>-	if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
>+	if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
> 		return;
> 
> 	core_dc->hwss.set_avmute(pipe_ctx, enable);
>@@ -2999,8 +3017,10 @@
> 	for (i = 0; i < MAX_PIPES; i++) {
> 		pipe = &dc->current_state->res_ctx.pipe_ctx[i];
> 		if (pipe->stream && pipe->stream->link) {
>-			if (pipe->stream->link == link)
>+			if (pipe->stream->link == link) {
>+				link_stream = pipe->stream;
> 				break;
>+			}
> 		}
> 	}
> 
>@@ -3008,20 +3028,40 @@
> 	if (i == MAX_PIPES)
> 		return;
> 
>-	link_stream = link->dc->current_state->res_ctx.pipe_ctx[i].stream;
>-
> 	/* Cannot retrain link if backend is off */
> 	if (link_stream->dpms_off)
> 		return;
> 
>-	if (link_stream)
>-		decide_link_settings(link_stream, &store_settings);
>+	decide_link_settings(link_stream, &store_settings);
> 
> 	if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
> 		(store_settings.link_rate != LINK_RATE_UNKNOWN))
> 		dp_retrain_link_dp_test(link, &store_settings, false);
> }
> 
>+void dc_link_set_preferred_training_settings(struct dc *dc,
>+						 struct dc_link_settings *link_setting,
>+						 struct dc_link_training_overrides *lt_overrides,
>+						 struct dc_link *link,
>+						 bool skip_immediate_retrain)
>+{
>+	if (lt_overrides != NULL)
>+		link->preferred_training_settings = *lt_overrides;
>+	else
>+		memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
>+
>+	if (link_setting != NULL) {
>+		link->preferred_link_setting = *link_setting;
>+	} else {
>+		link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
>+		link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
>+	}
>+
>+	/* Retrain now, or wait until next stream update to apply */
>+	if (skip_immediate_retrain == false)
>+		dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
>+}
>+
> void dc_link_enable_hpd(const struct dc_link *link)
> {
> 	dc_link_dp_enable_hpd(link);
>@@ -3032,7 +3072,6 @@
> 	dc_link_dp_disable_hpd(link);
> }
> 
>-
> void dc_link_set_test_pattern(struct dc_link *link,
> 			      enum dp_test_pattern test_pattern,
> 			      const struct link_training_settings *p_link_settings,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c	2019-08-31 15:01:11.858736168 -0500
>@@ -294,7 +294,7 @@
> {
> 	struct dc_link *link = ddc->link;
> 
>-	if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_4 &&
>+	if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
> 		!memcmp(link->dpcd_caps.branch_dev_name,
> 			DP_DVI_CONVERTER_ID_4,
> 			sizeof(link->dpcd_caps.branch_dev_name)))
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c	2019-08-31 15:01:11.858736168 -0500
>@@ -49,7 +49,7 @@
> 		struct dc_link_settings link_setting_a,
> 		struct dc_link_settings link_setting_b);
> 
>-static void wait_for_training_aux_rd_interval(
>+static uint32_t get_training_aux_rd_interval(
> 	struct dc_link *link,
> 	uint32_t default_wait_in_micro_secs)
> {
>@@ -68,15 +68,21 @@
> 			sizeof(training_rd_interval));
> 
> 		if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
>-			default_wait_in_micro_secs =
>-				training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
>+			default_wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
> 	}
> 
>-	udelay(default_wait_in_micro_secs);
>+	return default_wait_in_micro_secs;
>+}
>+
>+static void wait_for_training_aux_rd_interval(
>+	struct dc_link *link,
>+	uint32_t wait_in_micro_secs)
>+{
>+	udelay(wait_in_micro_secs);
> 
> 	DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
> 		__func__,
>-		default_wait_in_micro_secs);
>+		wait_in_micro_secs);
> }
> 
> static void dpcd_set_training_pattern(
>@@ -95,27 +101,27 @@
> 		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
> }
> 
>-static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
>+static enum dc_dp_training_pattern get_supported_tp(struct dc_link *link)
> {
>-	enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
>+	enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
> 	struct encoder_feature_support *features = &link->link_enc->features;
> 	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
> 
> 	if (features->flags.bits.IS_TPS3_CAPABLE)
>-		highest_tp = HW_DP_TRAINING_PATTERN_3;
>+		highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
> 
> 	if (features->flags.bits.IS_TPS4_CAPABLE)
>-		highest_tp = HW_DP_TRAINING_PATTERN_4;
>+		highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
> 
> 	if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
>-		highest_tp >= HW_DP_TRAINING_PATTERN_4)
>-		return HW_DP_TRAINING_PATTERN_4;
>+		highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
>+		return DP_TRAINING_PATTERN_SEQUENCE_4;
> 
> 	if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
>-		highest_tp >= HW_DP_TRAINING_PATTERN_3)
>-		return HW_DP_TRAINING_PATTERN_3;
>+		highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
>+		return DP_TRAINING_PATTERN_SEQUENCE_3;
> 
>-	return HW_DP_TRAINING_PATTERN_2;
>+	return DP_TRAINING_PATTERN_SEQUENCE_2;
> }
> 
> static void dpcd_set_link_settings(
>@@ -126,7 +132,7 @@
> 
> 	union down_spread_ctrl downspread = { {0} };
> 	union lane_count_set lane_count_set = { {0} };
>-	enum hw_dp_training_pattern hw_tr_pattern;
>+	enum dc_dp_training_pattern dp_tr_pattern;
> 
> 	downspread.raw = (uint8_t)
> 	(lt_settings->link_settings.link_spread);
>@@ -134,21 +140,21 @@
> 	lane_count_set.bits.LANE_COUNT_SET =
> 	lt_settings->link_settings.lane_count;
> 
>-	lane_count_set.bits.ENHANCED_FRAMING = 1;
>-
>+	lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
> 	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
> 
>-	hw_tr_pattern = get_supported_tp(link);
>-	if (hw_tr_pattern != HW_DP_TRAINING_PATTERN_4) {
>+	dp_tr_pattern = get_supported_tp(link);
>+
>+	if (dp_tr_pattern != DP_TRAINING_PATTERN_SEQUENCE_4) {
> 		lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
> 				link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
> 	}
> 
> 	core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
>-	&downspread.raw, sizeof(downspread));
>+		&downspread.raw, sizeof(downspread));
> 
> 	core_link_write_dpcd(link, DP_LANE_COUNT_SET,
>-	&lane_count_set.raw, 1);
>+		&lane_count_set.raw, 1);
> 
> 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
> 			lt_settings->link_settings.use_link_rate_set == true) {
>@@ -162,46 +168,47 @@
> 	}
> 
> 	if (rate) {
>-		DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n",
>+		DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
> 			__func__,
> 			DP_LINK_BW_SET,
> 			lt_settings->link_settings.link_rate,
> 			DP_LANE_COUNT_SET,
> 			lt_settings->link_settings.lane_count,
>+			lt_settings->enhanced_framing,
> 			DP_DOWNSPREAD_CTRL,
> 			lt_settings->link_settings.link_spread);
> 	} else {
>-		DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x\n %x spread = %x\n",
>+		DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
> 			__func__,
> 			DP_LINK_RATE_SET,
> 			lt_settings->link_settings.link_rate_set,
> 			DP_LANE_COUNT_SET,
> 			lt_settings->link_settings.lane_count,
>+			lt_settings->enhanced_framing,
> 			DP_DOWNSPREAD_CTRL,
> 			lt_settings->link_settings.link_spread);
> 	}
>-
> }
> 
> static enum dpcd_training_patterns
>-	hw_training_pattern_to_dpcd_training_pattern(
>+	dc_dp_training_pattern_to_dpcd_training_pattern(
> 	struct dc_link *link,
>-	enum hw_dp_training_pattern pattern)
>+	enum dc_dp_training_pattern pattern)
> {
> 	enum dpcd_training_patterns dpcd_tr_pattern =
> 	DPCD_TRAINING_PATTERN_VIDEOIDLE;
> 
> 	switch (pattern) {
>-	case HW_DP_TRAINING_PATTERN_1:
>+	case DP_TRAINING_PATTERN_SEQUENCE_1:
> 		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
> 		break;
>-	case HW_DP_TRAINING_PATTERN_2:
>+	case DP_TRAINING_PATTERN_SEQUENCE_2:
> 		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
> 		break;
>-	case HW_DP_TRAINING_PATTERN_3:
>+	case DP_TRAINING_PATTERN_SEQUENCE_3:
> 		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
> 		break;
>-	case HW_DP_TRAINING_PATTERN_4:
>+	case DP_TRAINING_PATTERN_SEQUENCE_4:
> 		dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
> 		break;
> 	default:
>@@ -212,13 +219,12 @@
> 	}
> 
> 	return dpcd_tr_pattern;
>-
> }
> 
> static void dpcd_set_lt_pattern_and_lane_settings(
> 	struct dc_link *link,
> 	const struct link_training_settings *lt_settings,
>-	enum hw_dp_training_pattern pattern)
>+	enum dc_dp_training_pattern pattern)
> {
> 	union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
> 	const uint32_t dpcd_base_lt_offset =
>@@ -233,7 +239,7 @@
> 	* DpcdAddress_TrainingPatternSet
> 	*****************************************************************/
> 	dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
>-		hw_training_pattern_to_dpcd_training_pattern(link, pattern);
>+		dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
> 
> 	dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - dpcd_base_lt_offset]
> 		= dpcd_pattern.raw;
>@@ -346,12 +352,20 @@
> {
> 	uint32_t lane;
> 	for (lane = 0; lane < src.link_settings.lane_count; lane++) {
>-		dest->lane_settings[lane].VOLTAGE_SWING =
>-			src.lane_settings[lane].VOLTAGE_SWING;
>-		dest->lane_settings[lane].PRE_EMPHASIS =
>-			src.lane_settings[lane].PRE_EMPHASIS;
>-		dest->lane_settings[lane].POST_CURSOR2 =
>-			src.lane_settings[lane].POST_CURSOR2;
>+		if (dest->voltage_swing == NULL)
>+			dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
>+		else
>+			dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
>+
>+		if (dest->pre_emphasis == NULL)
>+			dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
>+		else
>+			dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
>+
>+		if (dest->post_cursor2 == NULL)
>+			dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
>+		else
>+			dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
> 	}
> }
> 
>@@ -754,15 +768,15 @@
> 	struct link_training_settings *lt_settings)
> {
> 	struct link_training_settings req_settings;
>-	enum hw_dp_training_pattern hw_tr_pattern;
>+	enum dc_dp_training_pattern tr_pattern;
> 	uint32_t retries_ch_eq;
> 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
> 	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
> 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
> 
>-	hw_tr_pattern = get_supported_tp(link);
>+	tr_pattern = lt_settings->pattern_for_eq;
> 
>-	dp_set_hw_training_pattern(link, hw_tr_pattern);
>+	dp_set_hw_training_pattern(link, tr_pattern);
> 
> 	for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
> 		retries_ch_eq++) {
>@@ -776,12 +790,12 @@
> 			dpcd_set_lt_pattern_and_lane_settings(
> 				link,
> 				lt_settings,
>-				hw_tr_pattern);
>+				tr_pattern);
> 		else
> 			dpcd_set_lane_settings(link, lt_settings);
> 
> 		/* 3. wait for receiver to lock-on*/
>-		wait_for_training_aux_rd_interval(link, 400);
>+		wait_for_training_aux_rd_interval(link, lt_settings->eq_pattern_time);
> 
> 		/* 4. Read lane status and requested
> 		 * drive settings as set by the sink*/
>@@ -817,27 +831,16 @@
> {
> 	uint32_t retries_cr;
> 	uint32_t retry_count;
>-	uint32_t lane;
> 	struct link_training_settings req_settings;
>-	enum dc_lane_count lane_count =
>-	lt_settings->link_settings.lane_count;
>-	enum hw_dp_training_pattern hw_tr_pattern = HW_DP_TRAINING_PATTERN_1;
>+	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
>+	enum dc_dp_training_pattern tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_1;
> 	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
> 	union lane_align_status_updated dpcd_lane_status_updated;
> 
> 	retries_cr = 0;
> 	retry_count = 0;
>-	/* initial drive setting (VS/PE/PC2)*/
>-	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
>-		lt_settings->lane_settings[lane].VOLTAGE_SWING =
>-		VOLTAGE_SWING_LEVEL0;
>-		lt_settings->lane_settings[lane].PRE_EMPHASIS =
>-		PRE_EMPHASIS_DISABLED;
>-		lt_settings->lane_settings[lane].POST_CURSOR2 =
>-		POST_CURSOR2_DISABLED;
>-	}
> 
>-	dp_set_hw_training_pattern(link, hw_tr_pattern);
>+	dp_set_hw_training_pattern(link, tr_pattern);
> 
> 	/* najeeb - The synaptics MST hub can put the LT in
> 	* infinite loop by switching the VS
>@@ -845,7 +848,7 @@
> 	/* between level 0 and level 1 continuously, here
> 	* we try for CR lock for LinkTrainingMaxCRRetry count*/
> 	while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
>-	(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
>+		(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
> 
> 		memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
> 		memset(&dpcd_lane_status_updated, '\0',
>@@ -863,7 +866,7 @@
> 			dpcd_set_lt_pattern_and_lane_settings(
> 					link,
> 					lt_settings,
>-					hw_tr_pattern);
>+					tr_pattern);
> 		else
> 			dpcd_set_lane_settings(
> 					link,
>@@ -872,7 +875,7 @@
> 		/* 3. wait receiver to lock-on*/
> 		wait_for_training_aux_rd_interval(
> 				link,
>-				100);
>+				lt_settings->cr_pattern_time);
> 
> 		/* 4. Read lane status and requested drive
> 		* settings as set by the sink
>@@ -939,7 +942,7 @@
> 	 * TPS4 must be used instead of POST_LT_ADJ_REQ.
> 	 */
> 	if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
>-			get_supported_tp(link) == HW_DP_TRAINING_PATTERN_4)
>+			get_supported_tp(link) == DP_TRAINING_PATTERN_SEQUENCE_4)
> 		return status;
> 
> 	if (status == LINK_TRAINING_SUCCESS &&
>@@ -947,7 +950,7 @@
> 		status = LINK_TRAINING_LQA_FAIL;
> 
> 	lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
>-	lane_count_set.bits.ENHANCED_FRAMING = 1;
>+	lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
> 	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
> 
> 	core_link_write_dpcd(
>@@ -959,24 +962,29 @@
> 	return status;
> }
> 
>-enum link_training_result dc_link_dp_perform_link_training(
>-	struct dc_link *link,
>+static void initialize_training_settings(
>+	 struct dc_link *link,
> 	const struct dc_link_settings *link_setting,
>-	bool skip_video_pattern)
>+	const struct dc_link_training_overrides *overrides,
>+	struct link_training_settings *lt_settings)
> {
>-	enum link_training_result status = LINK_TRAINING_SUCCESS;
>+	uint32_t lane;
> 
>-	char *link_rate = "Unknown";
>-	char *lt_result = "Unknown";
>+	memset(lt_settings, '\0', sizeof(struct link_training_settings));
> 
>-	struct link_training_settings lt_settings;
>+	/* Initialize link settings */
>+	lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
>+	lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
> 
>-	memset(&lt_settings, '\0', sizeof(lt_settings));
>+	if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
>+		lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
>+	else
>+		lt_settings->link_settings.link_rate = link_setting->link_rate;
> 
>-	lt_settings.link_settings.link_rate = link_setting->link_rate;
>-	lt_settings.link_settings.lane_count = link_setting->lane_count;
>-	lt_settings.link_settings.use_link_rate_set = link_setting->use_link_rate_set;
>-	lt_settings.link_settings.link_rate_set = link_setting->link_rate_set;
>+	if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
>+		lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
>+	else
>+		lt_settings->link_settings.lane_count = link_setting->lane_count;
> 
> 	/*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
> 
>@@ -987,31 +995,75 @@
> 	 * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
> 	 * LINK_SPREAD_DISABLED;
> 	 */
>+	/* Initialize link spread */
> 	if (link->dp_ss_off)
>-		lt_settings.link_settings.link_spread = LINK_SPREAD_DISABLED;
>+		lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
>+	else if (overrides->downspread != NULL)
>+		lt_settings->link_settings.link_spread
>+			= *overrides->downspread
>+			? LINK_SPREAD_05_DOWNSPREAD_30KHZ
>+			: LINK_SPREAD_DISABLED;
> 	else
>-		lt_settings.link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
>+		lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
> 
>-	/* 1. set link rate, lane count and spread*/
>-	dpcd_set_link_settings(link, &lt_settings);
>+	/* Initialize lane settings overrides */
>+	if (overrides->voltage_swing != NULL)
>+		lt_settings->voltage_swing = overrides->voltage_swing;
> 
>-	/* 2. perform link training (set link training done
>-	 *  to false is done as well)*/
>-	status = perform_clock_recovery_sequence(link, &lt_settings);
>-	if (status == LINK_TRAINING_SUCCESS) {
>-		status = perform_channel_equalization_sequence(link,
>-				&lt_settings);
>-	}
>+	if (overrides->pre_emphasis != NULL)
>+		lt_settings->pre_emphasis = overrides->pre_emphasis;
> 
>-	if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
>-		status = perform_link_training_int(link,
>-				&lt_settings,
>-				status);
>+	if (overrides->post_cursor2 != NULL)
>+		lt_settings->post_cursor2 = overrides->post_cursor2;
>+
>+	/* Initialize lane settings (VS/PE/PC2) */
>+	for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
>+		lt_settings->lane_settings[lane].VOLTAGE_SWING =
>+			lt_settings->voltage_swing != NULL ?
>+			*lt_settings->voltage_swing :
>+			VOLTAGE_SWING_LEVEL0;
>+		lt_settings->lane_settings[lane].PRE_EMPHASIS =
>+			lt_settings->pre_emphasis != NULL ?
>+			*lt_settings->pre_emphasis
>+			: PRE_EMPHASIS_DISABLED;
>+		lt_settings->lane_settings[lane].POST_CURSOR2 =
>+			lt_settings->post_cursor2 != NULL ?
>+			*lt_settings->post_cursor2
>+			: POST_CURSOR2_DISABLED;
> 	}
> 
>-	/* 6. print status message*/
>-	switch (lt_settings.link_settings.link_rate) {
>+	/* Initialize training timings */
>+	if (overrides->cr_pattern_time != NULL)
>+		lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
>+	else
>+		lt_settings->cr_pattern_time = get_training_aux_rd_interval(link, 100);
>+
>+	if (overrides->eq_pattern_time != NULL)
>+		lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
>+	else
>+		lt_settings->eq_pattern_time = get_training_aux_rd_interval(link, 400);
>+
>+	if (overrides->pattern_for_eq != NULL)
>+		lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
>+	else
>+		lt_settings->pattern_for_eq = get_supported_tp(link);
>+
>+	if (overrides->enhanced_framing != NULL)
>+		lt_settings->enhanced_framing = *overrides->enhanced_framing;
>+	else
>+		lt_settings->enhanced_framing = 1;
>+}
> 
>+static void print_status_message(
>+	struct dc_link *link,
>+	const struct link_training_settings *lt_settings,
>+	enum link_training_result status)
>+{
>+	char *link_rate = "Unknown";
>+	char *lt_result = "Unknown";
>+	char *lt_spread = "Disabled";
>+
>+	switch (lt_settings->link_settings.link_rate) {
> 	case LINK_RATE_LOW:
> 		link_rate = "RBR";
> 		break;
>@@ -1057,13 +1109,122 @@
> 		break;
> 	}
> 
>+	switch (lt_settings->link_settings.link_spread) {
>+	case LINK_SPREAD_DISABLED:
>+		lt_spread = "Disabled";
>+		break;
>+	case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
>+		lt_spread = "0.5% 30KHz";
>+		break;
>+	case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
>+		lt_spread = "0.5% 33KHz";
>+		break;
>+	default:
>+		break;
>+	}
>+
> 	/* Connectivity log: link training */
>-	CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d",
>-			link_rate,
>-			lt_settings.link_settings.lane_count,
>-			lt_result,
>-			lt_settings.lane_settings[0].VOLTAGE_SWING,
>-			lt_settings.lane_settings[0].PRE_EMPHASIS);
>+	CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
>+				link_rate,
>+				lt_settings->link_settings.lane_count,
>+				lt_result,
>+				lt_settings->lane_settings[0].VOLTAGE_SWING,
>+				lt_settings->lane_settings[0].PRE_EMPHASIS,
>+				lt_spread);
>+}
>+
>+bool dc_link_dp_perform_link_training_skip_aux(
>+	struct dc_link *link,
>+	const struct dc_link_settings *link_setting)
>+{
>+	struct link_training_settings lt_settings;
>+	enum dc_dp_training_pattern pattern_for_cr = DP_TRAINING_PATTERN_SEQUENCE_1;
>+
>+	initialize_training_settings(
>+			link,
>+			link_setting,
>+			&link->preferred_training_settings,
>+			&lt_settings);
>+
>+	/* 1. Perform_clock_recovery_sequence. */
>+
>+	/* transmit training pattern for clock recovery */
>+	dp_set_hw_training_pattern(link, pattern_for_cr);
>+
>+	/* call HWSS to set lane settings*/
>+	dp_set_hw_lane_settings(link, &lt_settings);
>+
>+	/* wait receiver to lock-on*/
>+	wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
>+
>+	/* 2. Perform_channel_equalization_sequence. */
>+
>+	/* transmit training pattern for channel equalization. */
>+	dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq);
>+
>+	/* call HWSS to set lane settings*/
>+	dp_set_hw_lane_settings(link, &lt_settings);
>+
>+	/* wait receiver to lock-on. */
>+	wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
>+
>+	/* 3. Perform_link_training_int. */
>+
>+	/* Mainlink output idle pattern. */
>+	dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
>+
>+	print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
>+
>+	return true;
>+}
>+
>+enum link_training_result dc_link_dp_perform_link_training(
>+	struct dc_link *link,
>+	const struct dc_link_settings *link_setting,
>+	bool skip_video_pattern)
>+{
>+	enum link_training_result status = LINK_TRAINING_SUCCESS;
>+	struct link_training_settings lt_settings;
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	bool fec_enable;
>+#endif
>+
>+	initialize_training_settings(
>+			link,
>+			link_setting,
>+			&link->preferred_training_settings,
>+			&lt_settings);
>+
>+	/* 1. set link rate, lane count and spread. */
>+	dpcd_set_link_settings(link, &lt_settings);
>+
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	if (link->preferred_training_settings.fec_enable != NULL)
>+		fec_enable = *link->preferred_training_settings.fec_enable;
>+	else
>+		fec_enable = true;
>+
>+	dp_set_fec_ready(link, fec_enable);
>+#endif
>+
>+
>+	/* 2. perform link training (set link training done
>+	 *  to false is done as well)
>+	 */
>+	status = perform_clock_recovery_sequence(link, &lt_settings);
>+	if (status == LINK_TRAINING_SUCCESS) {
>+		status = perform_channel_equalization_sequence(link,
>+				&lt_settings);
>+	}
>+
>+	if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
>+		status = perform_link_training_int(link,
>+				&lt_settings,
>+				status);
>+	}
>+
>+	/* 6. print status message*/
>+	print_status_message(link, &lt_settings, status);
> 
> 	if (status != LINK_TRAINING_SUCCESS)
> 		link->ctx->dc->debug_data.ltFailCount++;
>@@ -1071,7 +1232,6 @@
> 	return status;
> }
> 
>-
> bool perform_link_training_with_retries(
> 	struct dc_link *link,
> 	const struct dc_link_settings *link_setting,
>@@ -1096,6 +1256,146 @@
> 	return false;
> }
> 
>+static enum clock_source_id get_clock_source_id(struct dc_link *link)
>+{
>+	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
>+	struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
>+
>+	if (dp_cs != NULL) {
>+		dp_cs_id = dp_cs->id;
>+	} else {
>+		/*
>+		 * dp clock source is not initialized for some reason.
>+		 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
>+		 */
>+		ASSERT(dp_cs);
>+	}
>+
>+	return dp_cs_id;
>+}
>+
>+static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
>+{
>+	if (mst_enable == false &&
>+		link->type == dc_connection_mst_branch) {
>+		/* Disable MST on link. Use only local sink. */
>+		dp_disable_link_phy_mst(link, link->connector_signal);
>+
>+		link->type = dc_connection_single;
>+		link->local_sink = link->remote_sinks[0];
>+		link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
>+	} else if (mst_enable == true &&
>+			link->type == dc_connection_single &&
>+			link->remote_sinks[0] != NULL) {
>+		/* Re-enable MST on link. */
>+		dp_disable_link_phy(link, link->connector_signal);
>+		dp_enable_mst_on_sink(link, true);
>+
>+		link->type = dc_connection_mst_branch;
>+		link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
>+	}
>+}
>+
>+bool dc_link_dp_sync_lt_begin(struct dc_link *link)
>+{
>+	/* Begin Sync LT. During this time,
>+	 * DPCD:600h must not be powered down.
>+	 */
>+	link->sync_lt_in_progress = true;
>+
>+	/*Clear any existing preferred settings.*/
>+	memset(&link->preferred_training_settings, 0,
>+		sizeof(struct dc_link_training_overrides));
>+	memset(&link->preferred_link_setting, 0,
>+		sizeof(struct dc_link_settings));
>+
>+	return true;
>+}
>+
>+enum link_training_result dc_link_dp_sync_lt_attempt(
>+    struct dc_link *link,
>+    struct dc_link_settings *link_settings,
>+    struct dc_link_training_overrides *lt_overrides)
>+{
>+	struct link_training_settings lt_settings;
>+	enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
>+	enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
>+	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	bool fec_enable = false;
>+#endif
>+
>+	initialize_training_settings(
>+		link,
>+		link_settings,
>+		lt_overrides,
>+		&lt_settings);
>+
>+	/* Setup MST Mode */
>+	if (lt_overrides->mst_enable)
>+		set_dp_mst_mode(link, *lt_overrides->mst_enable);
>+
>+	/* Disable link */
>+	dp_disable_link_phy(link, link->connector_signal);
>+
>+	/* Enable link */
>+	dp_cs_id = get_clock_source_id(link);
>+	dp_enable_link_phy(link, link->connector_signal,
>+		dp_cs_id, link_settings);
>+
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	/* Set FEC enable */
>+	fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
>+	dp_set_fec_ready(link, fec_enable);
>+#endif
>+
>+	if (lt_overrides->alternate_scrambler_reset) {
>+		if (*lt_overrides->alternate_scrambler_reset)
>+			panel_mode = DP_PANEL_MODE_EDP;
>+		else
>+			panel_mode = DP_PANEL_MODE_DEFAULT;
>+	} else
>+		panel_mode = dp_get_panel_mode(link);
>+
>+	dp_set_panel_mode(link, panel_mode);
>+
>+	/* Attempt to train with given link training settings */
>+
>+	/* Set link rate, lane count and spread. */
>+	dpcd_set_link_settings(link, &lt_settings);
>+
>+	/* 2. perform link training (set link training done
>+	 *  to false is done as well)
>+	 */
>+	lt_status = perform_clock_recovery_sequence(link, &lt_settings);
>+	if (lt_status == LINK_TRAINING_SUCCESS) {
>+		lt_status = perform_channel_equalization_sequence(link,
>+						&lt_settings);
>+	}
>+
>+	/* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
>+	/* 4. print status message*/
>+	print_status_message(link, &lt_settings, lt_status);
>+
>+	return lt_status;
>+}
>+
>+bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
>+{
>+	/* If input parameter is set, shut down phy.
>+	 * Still shouldn't turn off dp_receiver (DPCD:600h)
>+	 */
>+	if (link_down == true) {
>+		dp_disable_link_phy(link, link->connector_signal);
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+		dp_set_fec_ready(link, false);
>+#endif
>+	}
>+
>+	link->sync_lt_in_progress = false;
>+	return true;
>+}
>+
> static struct dc_link_settings get_max_link_cap(struct dc_link *link)
> {
> 	/* Set Default link settings */
>@@ -1250,7 +1550,6 @@
> 	bool success;
> 	bool skip_link_training;
> 	bool skip_video_pattern;
>-	struct clock_source *dp_cs;
> 	enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
> 	enum link_training_result status;
> 	union hpd_irq_data irq_data;
>@@ -1274,17 +1573,7 @@
> 	/* disable PHY done possible by BIOS, will be done by driver itself */
> 	dp_disable_link_phy(link, link->connector_signal);
> 
>-	dp_cs = link->dc->res_pool->dp_clock_source;
>-
>-	if (dp_cs)
>-		dp_cs_id = dp_cs->id;
>-	else {
>-		/*
>-		 * dp clock source is not initialized for some reason.
>-		 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
>-		 */
>-		ASSERT(dp_cs);
>-	}
>+	dp_cs_id = get_clock_source_id(link);
> 
> 	/* link training starts with the maximum common settings
> 	 * supported by both sink and ASIC.
>@@ -1354,6 +1643,33 @@
> 	return success;
> }
> 
>+bool dp_verify_link_cap_with_retries(
>+	struct dc_link *link,
>+	struct dc_link_settings *known_limit_link_setting,
>+	int attempts)
>+{
>+	uint8_t i = 0;
>+	bool success = false;
>+
>+	for (i = 0; i < attempts; i++) {
>+		int fail_count = 0;
>+		enum dc_connection_type type;
>+
>+		memset(&link->verified_link_cap, 0,
>+				sizeof(struct dc_link_settings));
>+		if (!dc_link_detect_sink(link, &type)) {
>+			break;
>+		} else if (dp_verify_link_cap(link,
>+				&link->reported_link_cap,
>+				&fail_count) && fail_count == 0) {
>+			success = true;
>+			break;
>+		}
>+		msleep(10);
>+	}
>+	return success;
>+}
>+
> static struct dc_link_settings get_common_supported_link_settings(
> 		struct dc_link_settings link_setting_a,
> 		struct dc_link_settings link_setting_b)
>@@ -2156,6 +2472,11 @@
> 	union dpcd_rev rev;
> 	union mstm_cap cap;
> 
>+	if (link->preferred_training_settings.mst_enable &&
>+		*link->preferred_training_settings.mst_enable == false) {
>+		return false;
>+	}
>+
> 	rev.raw  = 0;
> 	cap.raw  = 0;
> 
>@@ -2363,13 +2684,13 @@
> 
> 	if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
> 		switch (link->dpcd_caps.branch_dev_id) {
>-		/* Some active dongles (DP-VGA, DP-DLDVI converters) power down
>+		/* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
> 		 * all internal circuits including AUX communication preventing
> 		 * reading DPCD table and EDID (spec violation).
> 		 * Encoder will skip DP RX power down on disable_output to
> 		 * keep receiver powered all the time.*/
>-		case DP_BRANCH_DEVICE_ID_1:
>-		case DP_BRANCH_DEVICE_ID_4:
>+		case DP_BRANCH_DEVICE_ID_0010FA:
>+		case DP_BRANCH_DEVICE_ID_0080E1:
> 			link->wa_flags.dp_keep_receiver_powered = true;
> 			break;
> 
>@@ -2774,14 +3095,19 @@
> 				controller_test_pattern, color_depth);
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> 		else if (opp->funcs->opp_set_disp_pattern_generator) {
>-			struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
>+			struct pipe_ctx *odm_pipe;
>+			int opp_cnt = 1;
> 
>-			if (bot_odm_pipe) {
>-				struct output_pixel_processor *bot_opp = bot_odm_pipe->stream_res.opp;
>+			for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
>+				opp_cnt++;
> 
>-				bot_opp->funcs->opp_program_bit_depth_reduction(bot_opp, &params);
>-				width /= 2;
>-				bot_opp->funcs->opp_set_disp_pattern_generator(bot_opp,
>+			width /= opp_cnt;
>+
>+			for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
>+				struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
>+
>+				odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
>+				odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
> 					controller_test_pattern,
> 					color_depth,
> 					NULL,
>@@ -2810,14 +3136,18 @@
> 				color_depth);
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> 		else if (opp->funcs->opp_set_disp_pattern_generator) {
>-			struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
>+			struct pipe_ctx *odm_pipe;
>+			int opp_cnt = 1;
> 
>-			if (bot_odm_pipe) {
>-				struct output_pixel_processor *bot_opp = bot_odm_pipe->stream_res.opp;
>+			for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
>+				opp_cnt++;
> 
>-				bot_opp->funcs->opp_program_bit_depth_reduction(bot_opp, &params);
>-				width /= 2;
>-				bot_opp->funcs->opp_set_disp_pattern_generator(bot_opp,
>+			width /= opp_cnt;
>+			for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
>+				struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
>+
>+				odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
>+				odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
> 					CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
> 					color_depth,
> 					NULL,
>@@ -2858,7 +3188,7 @@
> 	memset(&training_pattern, 0, sizeof(training_pattern));
> 
> 	for (i = 0; i < MAX_PIPES; i++) {
>-		if (pipes[i].stream->link == link) {
>+		if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
> 			pipe_ctx = &pipes[i];
> 			break;
> 		}
>@@ -3007,6 +3337,105 @@
> 	core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
> }
> 
>+void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
>+{
>+	union dpcd_edp_config edp_config_set;
>+	bool panel_mode_edp = false;
>+
>+	memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
>+
>+	if (panel_mode != DP_PANEL_MODE_DEFAULT) {
>+
>+		switch (panel_mode) {
>+		case DP_PANEL_MODE_EDP:
>+		case DP_PANEL_MODE_SPECIAL:
>+			panel_mode_edp = true;
>+			break;
>+
>+		default:
>+				break;
>+		}
>+
>+		/*set edp panel mode in receiver*/
>+		core_link_read_dpcd(
>+			link,
>+			DP_EDP_CONFIGURATION_SET,
>+			&edp_config_set.raw,
>+			sizeof(edp_config_set.raw));
>+
>+		if (edp_config_set.bits.PANEL_MODE_EDP
>+			!= panel_mode_edp) {
>+			enum ddc_result result = DDC_RESULT_UNKNOWN;
>+
>+			edp_config_set.bits.PANEL_MODE_EDP =
>+			panel_mode_edp;
>+			result = core_link_write_dpcd(
>+				link,
>+				DP_EDP_CONFIGURATION_SET,
>+				&edp_config_set.raw,
>+				sizeof(edp_config_set.raw));
>+
>+			ASSERT(result == DDC_RESULT_SUCESSFULL);
>+		}
>+	}
>+	DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
>+		 "eDP panel mode enabled: %d \n",
>+		 link->link_index,
>+		 link->dpcd_caps.panel_mode_edp,
>+		 panel_mode_edp);
>+}
>+
>+enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
>+{
>+	/* We need to explicitly check that connector
>+	 * is not DP. Some Travis_VGA get reported
>+	 * by video bios as DP.
>+	 */
>+	if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
>+
>+		switch (link->dpcd_caps.branch_dev_id) {
>+		case DP_BRANCH_DEVICE_ID_0022B9:
>+			/* alternate scrambler reset is required for Travis
>+			 * for the case when external chip does not
>+			 * provide sink device id, alternate scrambler
>+			 * scheme will  be overriden later by querying
>+			 * Encoder features
>+			 */
>+			if (strncmp(
>+				link->dpcd_caps.branch_dev_name,
>+				DP_VGA_LVDS_CONVERTER_ID_2,
>+				sizeof(
>+				link->dpcd_caps.
>+				branch_dev_name)) == 0) {
>+					return DP_PANEL_MODE_SPECIAL;
>+			}
>+			break;
>+		case DP_BRANCH_DEVICE_ID_00001A:
>+			/* alternate scrambler reset is required for Travis
>+			 * for the case when external chip does not provide
>+			 * sink device id, alternate scrambler scheme will
>+			 * be overriden later by querying Encoder feature
>+			 */
>+			if (strncmp(link->dpcd_caps.branch_dev_name,
>+				DP_VGA_LVDS_CONVERTER_ID_3,
>+				sizeof(
>+				link->dpcd_caps.
>+				branch_dev_name)) == 0) {
>+					return DP_PANEL_MODE_SPECIAL;
>+			}
>+			break;
>+		default:
>+			break;
>+		}
>+	}
>+
>+	if (link->dpcd_caps.panel_mode_edp) {
>+		return DP_PANEL_MODE_EDP;
>+	}
>+
>+	return DP_PANEL_MODE_DEFAULT;
>+}
>+
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> void dp_set_fec_ready(struct dc_link *link, bool ready)
> {
>@@ -3024,7 +3453,7 @@
> 
> 	if (link_enc->funcs->fec_set_ready &&
> 			link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
>-		if (link->fec_state == dc_link_fec_not_ready && ready) {
>+		if (ready) {
> 			fec_config = 1;
> 			if (core_link_write_dpcd(link,
> 					DP_FEC_CONFIGURATION,
>@@ -3033,9 +3462,11 @@
> 				link_enc->funcs->fec_set_ready(link_enc, true);
> 				link->fec_state = dc_link_fec_ready;
> 			} else {
>+				link->link_enc->funcs->fec_set_ready(link->link_enc, false);
>+				link->fec_state = dc_link_fec_not_ready;
> 				dm_error("dpcd write failed to set fec_ready");
> 			}
>-		} else if (link->fec_state == dc_link_fec_ready && !ready) {
>+		} else if (link->fec_state == dc_link_fec_ready) {
> 			fec_config = 0;
> 			core_link_write_dpcd(link,
> 					DP_FEC_CONFIGURATION,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c	2019-08-31 15:01:11.858736168 -0500
>@@ -25,10 +25,11 @@
> 	uint8_t *data,
> 	uint32_t size)
> {
>-	if (!dm_helpers_dp_read_dpcd(link->ctx,
>-			link,
>-			address, data, size))
>-			return DC_ERROR_UNEXPECTED;
>+	if (!link->aux_access_disabled &&
>+			!dm_helpers_dp_read_dpcd(link->ctx,
>+			link, address, data, size)) {
>+		return DC_ERROR_UNEXPECTED;
>+	}
> 
> 	return DC_OK;
> }
>@@ -39,10 +40,11 @@
> 	const uint8_t *data,
> 	uint32_t size)
> {
>-	if (!dm_helpers_dp_write_dpcd(link->ctx,
>-			link,
>-			address, data, size))
>-				return DC_ERROR_UNEXPECTED;
>+	if (!link->aux_access_disabled &&
>+			!dm_helpers_dp_write_dpcd(link->ctx,
>+			link, address, data, size)) {
>+		return DC_ERROR_UNEXPECTED;
>+	}
> 
> 	return DC_OK;
> }
>@@ -53,6 +55,9 @@
> 
> 	state = on ? DP_POWER_STATE_D0 : DP_POWER_STATE_D3;
> 
>+	if (link->sync_lt_in_progress)
>+		return;
>+
> 	core_link_write_dpcd(link, DP_SET_POWER, &state,
> 			sizeof(state));
> }
>@@ -160,6 +165,10 @@
> 			break;
> 		udelay(25); //MAx T7 is 50ms
> 	} while (++tries < 300);
>+
>+	if (link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0)
>+		udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 1000);
>+
> 	return result;
> }
> 
>@@ -203,21 +212,21 @@
> 
> bool dp_set_hw_training_pattern(
> 	struct dc_link *link,
>-	enum hw_dp_training_pattern pattern)
>+	enum dc_dp_training_pattern pattern)
> {
> 	enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
> 
> 	switch (pattern) {
>-	case HW_DP_TRAINING_PATTERN_1:
>+	case DP_TRAINING_PATTERN_SEQUENCE_1:
> 		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1;
> 		break;
>-	case HW_DP_TRAINING_PATTERN_2:
>+	case DP_TRAINING_PATTERN_SEQUENCE_2:
> 		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2;
> 		break;
>-	case HW_DP_TRAINING_PATTERN_3:
>+	case DP_TRAINING_PATTERN_SEQUENCE_3:
> 		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
> 		break;
>-	case HW_DP_TRAINING_PATTERN_4:
>+	case DP_TRAINING_PATTERN_SEQUENCE_4:
> 		test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
> 		break;
> 	default:
>@@ -239,46 +248,6 @@
> 	encoder->funcs->dp_set_lane_settings(encoder, link_settings);
> }
> 
>-enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
>-{
>-	/* We need to explicitly check that connector
>-	 * is not DP. Some Travis_VGA get reported
>-	 * by video bios as DP.
>-	 */
>-	if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
>-
>-		switch (link->dpcd_caps.branch_dev_id) {
>-		case DP_BRANCH_DEVICE_ID_2:
>-			if (strncmp(
>-				link->dpcd_caps.branch_dev_name,
>-				DP_VGA_LVDS_CONVERTER_ID_2,
>-				sizeof(
>-				link->dpcd_caps.
>-				branch_dev_name)) == 0) {
>-				return DP_PANEL_MODE_SPECIAL;
>-			}
>-			break;
>-		case DP_BRANCH_DEVICE_ID_3:
>-			if (strncmp(link->dpcd_caps.branch_dev_name,
>-				DP_VGA_LVDS_CONVERTER_ID_3,
>-				sizeof(
>-				link->dpcd_caps.
>-				branch_dev_name)) == 0) {
>-				return DP_PANEL_MODE_SPECIAL;
>-			}
>-			break;
>-		default:
>-			break;
>-		}
>-	}
>-
>-	if (link->dpcd_caps.panel_mode_edp) {
>-		return DP_PANEL_MODE_EDP;
>-	}
>-
>-	return DP_PANEL_MODE_DEFAULT;
>-}
>-
> void dp_set_hw_test_pattern(
> 	struct dc_link *link,
> 	enum dp_test_pattern test_pattern,
>@@ -306,7 +275,7 @@
> 
> 	for (i = 0; i < MAX_PIPES; i++) {
> 		if (pipes[i].stream != NULL &&
>-			!pipes[i].top_pipe &&
>+			!pipes[i].top_pipe && !pipes[i].prev_odm_pipe &&
> 			pipes[i].stream->link != NULL &&
> 			pipes[i].stream_res.stream_enc != NULL) {
> 			udelay(100);
>@@ -320,7 +289,9 @@
> 
> 			dp_receiver_power_ctrl(link, false);
> 
>-			link->dc->hwss.disable_stream(&pipes[i], KEEP_ACQUIRED_RESOURCE);
>+			link->dc->hwss.disable_stream(&pipes[i]);
>+			if ((&pipes[i])->stream_res.audio && !link->dc->debug.az_endpoint_mute_only)
>+				(&pipes[i])->stream_res.audio->funcs->az_disable((&pipes[i])->stream_res.audio);
> 
> 			link->link_enc->funcs->disable_output(
> 					link->link_enc,
>@@ -373,10 +344,22 @@
> static void dsc_optc_config_log(struct display_stream_compressor *dsc,
> 		struct dsc_optc_config *config)
> {
>-	DC_LOG_DSC("Setting optc DSC config at DSC inst %d", dsc->inst);
>-	DC_LOG_DSC("\n\tbytes_per_pixel %d\n\tis_pixel_format_444 %d\n\tslice_width %d",
>-			config->bytes_per_pixel,
>-			config->is_pixel_format_444, config->slice_width);
>+	uint32_t precision = 1 << 28;
>+	uint32_t bytes_per_pixel_int = config->bytes_per_pixel / precision;
>+	uint32_t bytes_per_pixel_mod = config->bytes_per_pixel % precision;
>+	uint64_t ll_bytes_per_pix_fraq = bytes_per_pixel_mod;
>+
>+	/* 7 fractional digits decimal precision for bytes per pixel is enough because DSC
>+	 * bits per pixel precision is 1/16th of a pixel, which means bytes per pixel precision is
>+	 * 1/16/8 = 1/128 of a byte, or 0.0078125 decimal
>+	 */
>+	ll_bytes_per_pix_fraq *= 10000000;
>+	ll_bytes_per_pix_fraq /= precision;
>+
>+	DC_LOG_DSC("\tbytes_per_pixel 0x%08x (%d.%07d)",
>+			config->bytes_per_pixel, bytes_per_pixel_int, (uint32_t)ll_bytes_per_pix_fraq);
>+	DC_LOG_DSC("\tis_pixel_format_444 %d", config->is_pixel_format_444);
>+	DC_LOG_DSC("\tslice_width %d", config->slice_width);
> }
> 
> static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)
>@@ -392,55 +375,62 @@
> 	return result;
> }
> 
>-/* This has to be done after DSC was enabled on RX first, i.e. after dp_enable_dsc_on_rx() had been called
>+/* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,
>+ * i.e. after dp_enable_dsc_on_rx() had been called
>  */
>-static void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
>+void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
> {
> 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
> 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
> 	struct dc_stream_state *stream = pipe_ctx->stream;
>-	struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
>+	struct pipe_ctx *odm_pipe;
>+	int opp_cnt = 1;
>+
>+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
>+		opp_cnt++;
> 
> 	if (enable) {
>-		/* TODO proper function */
> 		struct dsc_config dsc_cfg;
> 		struct dsc_optc_config dsc_optc_cfg;
> 		enum optc_dsc_mode optc_dsc_mode;
>-		uint8_t dsc_packed_pps[128];
> 
> 		/* Enable DSC hw block */
>-		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
>+		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
> 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
> 		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
> 		dsc_cfg.color_depth = stream->timing.display_color_depth;
> 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
>+		ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
>+		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
> 
>-		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg, &dsc_packed_pps[0]);
>-		if (odm_pipe) {
>-			struct display_stream_compressor *bot_dsc = odm_pipe->stream_res.dsc;
>-			uint8_t dsc_packed_pps_odm[128];
>-
>-			dsc_cfg.pic_width /= 2;
>-			ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % 2 == 0);
>-			dsc_cfg.dc_dsc_cfg.num_slices_h /= 2;
>-			dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg, &dsc_packed_pps_odm[0]);
>-			bot_dsc->funcs->dsc_set_config(bot_dsc, &dsc_cfg, &dsc_optc_cfg, &dsc_packed_pps_odm[0]);
>-			bot_dsc->funcs->dsc_enable(bot_dsc, odm_pipe->stream_res.opp->inst);
>-		}
>+		dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
> 		dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
>+		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
>+			struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc;
>+
>+			odm_dsc->funcs->dsc_set_config(odm_dsc, &dsc_cfg, &dsc_optc_cfg);
>+			odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst);
>+		}
>+		dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
>+		dsc_cfg.pic_width *= opp_cnt;
> 
> 		optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
> 
>-		dsc_optc_config_log(dsc, &dsc_optc_cfg);
> 		/* Enable DSC in encoder */
>-		if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) && pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config)
>+		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
>+			DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id);
>+			dsc_optc_config_log(dsc, &dsc_optc_cfg);
> 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc,
> 									optc_dsc_mode,
> 									dsc_optc_cfg.bytes_per_pixel,
>-									dsc_optc_cfg.slice_width,
>-									&dsc_packed_pps[0]);
>+									dsc_optc_cfg.slice_width);
>+
>+			/* PPS SDP is set elsewhere because it has to be done after DIG FE is connected to DIG BE */
>+		}
> 
> 		/* Enable DSC in OPTC */
>+		DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst);
>+		dsc_optc_config_log(dsc, &dsc_optc_cfg);
> 		pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg,
> 							optc_dsc_mode,
> 							dsc_optc_cfg.bytes_per_pixel,
>@@ -452,15 +442,18 @@
> 				OPTC_DSC_DISABLED, 0, 0);
> 
> 		/* disable DSC in stream encoder */
>-		if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
>+		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
> 			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(
> 					pipe_ctx->stream_res.stream_enc,
>-					OPTC_DSC_DISABLED, 0, 0, NULL);
>+					OPTC_DSC_DISABLED, 0, 0);
>+
>+			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
>+					pipe_ctx->stream_res.stream_enc, false, NULL);
> 		}
> 
> 		/* disable DSC block */
> 		pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
>-		if (odm_pipe)
>+		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
> 			odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc);
> 	}
> }
>@@ -489,6 +482,47 @@
> 	return result;
> }
> 
>+bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable)
>+{
>+	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
>+	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
>+	struct dc_stream_state *stream = pipe_ctx->stream;
>+
>+	if (!pipe_ctx->stream->timing.flags.DSC || !dsc)
>+		return false;
>+
>+	if (enable) {
>+		struct dsc_config dsc_cfg;
>+		uint8_t dsc_packed_pps[128];
>+
>+		/* Enable DSC hw block */
>+		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
>+		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
>+		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
>+		dsc_cfg.color_depth = stream->timing.display_color_depth;
>+		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
>+
>+		DC_LOG_DSC(" ");
>+		dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
>+		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
>+			DC_LOG_DSC("Setting stream encoder DSC PPS SDP for engine %d\n", (int)pipe_ctx->stream_res.stream_enc->id);
>+			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
>+									pipe_ctx->stream_res.stream_enc,
>+									true,
>+									&dsc_packed_pps[0]);
>+		}
>+	} else {
>+		/* disable DSC PPS in stream encoder */
>+		if (dc_is_dp_signal(stream->signal) && !IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
>+			pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_pps_info_packet(
>+						pipe_ctx->stream_res.stream_enc, false, NULL);
>+		}
>+	}
>+
>+	return true;
>+}
>+
>+
> bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx)
> {
> 	struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc;
>@@ -499,8 +533,8 @@
> 		return false;
> 
> 	dp_set_dsc_on_stream(pipe_ctx, true);
>+	dp_set_dsc_pps_sdp(pipe_ctx, true);
> 	return true;
> }
>-
> #endif
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_resource.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_resource.c	2019-08-31 15:01:11.859736168 -0500
>@@ -52,6 +52,9 @@
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> #include "dcn20/dcn20_resource.h"
> #endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+#include "dcn21/dcn21_resource.h"
>+#endif
> #include "dce120/dce120_resource.h"
> 
> #define DC_LOGGER_INIT(logger)
>@@ -101,6 +104,10 @@
> 		dc_version = DCN_VERSION_1_0;
> 		if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
> 			dc_version = DCN_VERSION_1_01;
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+		if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
>+			dc_version = DCN_VERSION_2_1;
>+#endif
> 		break;
> #endif
> 
>@@ -168,17 +175,20 @@
> 		res_pool = dcn20_create_resource_pool(init_data, dc);
> 		break;
> #endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	case DCN_VERSION_2_1:
>+		res_pool = dcn21_create_resource_pool(init_data, dc);
>+		break;
>+#endif
> 
> 	default:
> 		break;
> 	}
>-	if (res_pool != NULL) {
>-		struct dc_firmware_info fw_info = { { 0 } };
> 
>-		if (dc->ctx->dc_bios->funcs->get_firmware_info(dc->ctx->dc_bios,
>-				&fw_info) == BP_RESULT_OK) {
>+	if (res_pool != NULL) {
>+		if (dc->ctx->dc_bios->fw_info_valid) {
> 			res_pool->ref_clocks.xtalin_clock_inKhz =
>-				fw_info.pll_info.crystal_frequency;
>+				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
> 			/* initialize with firmware data first, no all
> 			 * ASIC have DCCG SW component. FPGA or
> 			 * simulation need initialization of
>@@ -265,12 +275,10 @@
> 				DC_ERR("DC: failed to create audio!\n");
> 				return false;
> 			}
>-
> 			if (!aud->funcs->endpoint_valid(aud)) {
> 				aud->funcs->destroy(&aud);
> 				break;
> 			}
>-
> 			pool->audios[i] = aud;
> 			pool->audio_count++;
> 		}
>@@ -940,7 +948,14 @@
> 	data->inits.v_c_bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
> 
> }
>+static bool are_rect_integer_multiples(struct rect src, struct rect dest)
>+{
>+	if (dest.width  >= src.width  && dest.width  % src.width  == 0 &&
>+		dest.height >= src.height && dest.height % src.height == 0)
>+		return true;
> 
>+	return false;
>+}
> bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
> {
> 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
>@@ -983,6 +998,15 @@
> 	if (pipe_ctx->plane_res.dpp != NULL)
> 		res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
> 				pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
>+
>+	if (res &&
>+	    plane_state->scaling_quality.integer_scaling &&
>+	    are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport,
>+				       pipe_ctx->plane_res.scl_data.recout)) {
>+		pipe_ctx->plane_res.scl_data.taps.v_taps = 1;
>+		pipe_ctx->plane_res.scl_data.taps.h_taps = 1;
>+	}
>+
> 	if (!res) {
> 		/* Try 24 bpp linebuffer */
> 		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
>@@ -1103,25 +1127,21 @@
> 		struct dc_stream_state *stream)
> {
> 	int i;
>+
> 	for (i = 0; i < MAX_PIPES; i++) {
>-		if (res_ctx->pipe_ctx[i].stream == stream &&
>-				!res_ctx->pipe_ctx[i].top_pipe) {
>+		if (res_ctx->pipe_ctx[i].stream == stream
>+				&& !res_ctx->pipe_ctx[i].top_pipe
>+				&& !res_ctx->pipe_ctx[i].prev_odm_pipe)
> 			return &res_ctx->pipe_ctx[i];
>-			break;
>-		}
> 	}
> 	return NULL;
> }
> 
>-static struct pipe_ctx *resource_get_tail_pipe_for_stream(
>+static struct pipe_ctx *resource_get_tail_pipe(
> 		struct resource_context *res_ctx,
>-		struct dc_stream_state *stream)
>+		struct pipe_ctx *head_pipe)
> {
>-	struct pipe_ctx *head_pipe, *tail_pipe;
>-	head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
>-
>-	if (!head_pipe)
>-		return NULL;
>+	struct pipe_ctx *tail_pipe;
> 
> 	tail_pipe = head_pipe->bottom_pipe;
> 
>@@ -1137,31 +1157,20 @@
>  * A free_pipe for a stream is defined here as a pipe
>  * that has no surface attached yet
>  */
>-static struct pipe_ctx *acquire_free_pipe_for_stream(
>+static struct pipe_ctx *acquire_free_pipe_for_head(
> 		struct dc_state *context,
> 		const struct resource_pool *pool,
>-		struct dc_stream_state *stream)
>+		struct pipe_ctx *head_pipe)
> {
> 	int i;
> 	struct resource_context *res_ctx = &context->res_ctx;
> 
>-	struct pipe_ctx *head_pipe = NULL;
>-
>-	/* Find head pipe, which has the back end set up*/
>-
>-	head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
>-
>-	if (!head_pipe) {
>-		ASSERT(0);
>-		return NULL;
>-	}
>-
> 	if (!head_pipe->plane_state)
> 		return head_pipe;
> 
> 	/* Re-use pipe already acquired for this stream if available*/
> 	for (i = pool->pipe_count - 1; i >= 0; i--) {
>-		if (res_ctx->pipe_ctx[i].stream == stream &&
>+		if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
> 				!res_ctx->pipe_ctx[i].plane_state) {
> 			return &res_ctx->pipe_ctx[i];
> 		}
>@@ -1175,8 +1184,7 @@
> 	if (!pool->funcs->acquire_idle_pipe_for_layer)
> 		return NULL;
> 
>-	return pool->funcs->acquire_idle_pipe_for_layer(context, pool, stream);
>-
>+	return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
> }
> 
> #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>@@ -1190,7 +1198,7 @@
> 	for (i = 0; i < pool->pipe_count; i++) {
> 		struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
> 
>-		if (split_pipe->top_pipe && !dc_res_is_odm_head_pipe(split_pipe) &&
>+		if (split_pipe->top_pipe &&
> 				split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
> 			split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
> 			if (split_pipe->bottom_pipe)
>@@ -1251,39 +1259,41 @@
> 		return false;
> 	}
> 
>-	tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream);
>-	ASSERT(tail_pipe);
>-
>-	free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
>+	/* retain new surface, but only once per stream */
>+	dc_plane_state_retain(plane_state);
> 
>-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>-	if (!free_pipe) {
>-		int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
>-		if (pipe_idx >= 0)
>-			free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
>-	}
>-#endif
>-	if (!free_pipe)
>-		return false;
>+	while (head_pipe) {
>+		tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
>+		ASSERT(tail_pipe);
>+
>+		free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
>+
>+	#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
>+		if (!free_pipe) {
>+			int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
>+			if (pipe_idx >= 0)
>+				free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
>+		}
>+	#endif
>+		if (!free_pipe) {
>+			dc_plane_state_release(plane_state);
>+			return false;
>+		}
> 
>-	/* retain new surfaces */
>-	dc_plane_state_retain(plane_state);
>-	free_pipe->plane_state = plane_state;
>+		free_pipe->plane_state = plane_state;
> 
>-	if (head_pipe != free_pipe) {
>-		free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
>-		free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
>-		free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
>-		free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
>-		free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
>-		free_pipe->clock_source = tail_pipe->clock_source;
>-		free_pipe->top_pipe = tail_pipe;
>-		tail_pipe->bottom_pipe = free_pipe;
>-	} else if (free_pipe->bottom_pipe && free_pipe->bottom_pipe->plane_state == NULL) {
>-		ASSERT(free_pipe->bottom_pipe->stream_res.opp != free_pipe->stream_res.opp);
>-		free_pipe->bottom_pipe->plane_state = plane_state;
>+		if (head_pipe != free_pipe) {
>+			free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
>+			free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
>+			free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
>+			free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
>+			free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
>+			free_pipe->clock_source = tail_pipe->clock_source;
>+			free_pipe->top_pipe = tail_pipe;
>+			tail_pipe->bottom_pipe = free_pipe;
>+		}
>+		head_pipe = head_pipe->next_odm_pipe;
> 	}
>-
> 	/* assign new surfaces*/
> 	stream_status->plane_states[stream_status->plane_count] = plane_state;
> 
>@@ -1292,35 +1302,6 @@
> 	return true;
> }
> 
>-struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx)
>-{
>-	struct pipe_ctx *bottom_pipe = pipe_ctx->bottom_pipe;
>-
>-	/* ODM should only be updated once per otg */
>-	if (pipe_ctx->top_pipe)
>-		return NULL;
>-
>-	while (bottom_pipe) {
>-		if (bottom_pipe->stream_res.opp != pipe_ctx->stream_res.opp)
>-			break;
>-		bottom_pipe = bottom_pipe->bottom_pipe;
>-	}
>-
>-	return bottom_pipe;
>-}
>-
>-bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx)
>-{
>-	struct pipe_ctx *top_pipe = pipe_ctx->top_pipe;
>-
>-	if (!top_pipe)
>-		return false;
>-	if (top_pipe && top_pipe->stream_res.opp == pipe_ctx->stream_res.opp)
>-		return false;
>-
>-	return true;
>-}
>-
> bool dc_remove_plane_from_context(
> 		const struct dc *dc,
> 		struct dc_stream_state *stream,
>@@ -1347,12 +1328,6 @@
> 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
> 
> 		if (pipe_ctx->plane_state == plane_state) {
>-			if (dc_res_is_odm_head_pipe(pipe_ctx)) {
>-				pipe_ctx->plane_state = NULL;
>-				pipe_ctx->bottom_pipe = NULL;
>-				continue;
>-			}
>-
> 			if (pipe_ctx->top_pipe)
> 				pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
> 
>@@ -1367,13 +1342,10 @@
> 			 * For head pipe detach surfaces from pipe for tail
> 			 * pipe just zero it out
> 			 */
>-			if (!pipe_ctx->top_pipe) {
>+			if (!pipe_ctx->top_pipe)
> 				pipe_ctx->plane_state = NULL;
>-				if (!dc_res_get_odm_bottom_pipe(pipe_ctx))
>-					pipe_ctx->bottom_pipe = NULL;
>-			} else {
>+			else
> 				memset(pipe_ctx, 0, sizeof(*pipe_ctx));
>-			}
> 		}
> 	}
> 
>@@ -1659,24 +1631,25 @@
> 		const struct resource_pool *pool,
> 		enum engine_id id)
> {
>-	int i;
>-	for (i = 0; i < pool->audio_count; i++) {
>+	int i, available_audio_count;
>+
>+	available_audio_count = pool->audio_count;
>+
>+	for (i = 0; i < available_audio_count; i++) {
> 		if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
> 			/*we have enough audio endpoint, find the matching inst*/
> 			if (id != i)
> 				continue;
>-
> 			return pool->audios[i];
> 		}
> 	}
> 
>-    /* use engine id to find free audio */
>-	if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
>+	/* use engine id to find free audio */
>+	if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
> 		return pool->audios[id];
> 	}
>-
> 	/*not found the matching one, first come first serve*/
>-	for (i = 0; i < pool->audio_count; i++) {
>+	for (i = 0; i < available_audio_count; i++) {
> 		if (res_ctx->is_audio_acquired[i] == false) {
> 			return pool->audios[i];
> 		}
>@@ -1736,51 +1709,46 @@
> {
> 	int i;
> 	struct dc_context *dc_ctx = dc->ctx;
>-	struct pipe_ctx *del_pipe = NULL;
>-
>-	/* Release primary pipe */
>-	for (i = 0; i < MAX_PIPES; i++) {
>-		if (new_ctx->res_ctx.pipe_ctx[i].stream == stream &&
>-				!new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
>-			struct pipe_ctx *odm_pipe =
>-					dc_res_get_odm_bottom_pipe(&new_ctx->res_ctx.pipe_ctx[i]);
>-
>-			del_pipe = &new_ctx->res_ctx.pipe_ctx[i];
>-
>-			ASSERT(del_pipe->stream_res.stream_enc);
>-			update_stream_engine_usage(
>-					&new_ctx->res_ctx,
>-						dc->res_pool,
>-					del_pipe->stream_res.stream_enc,
>-					false);
>-
>-			if (del_pipe->stream_res.audio)
>-				update_audio_usage(
>-					&new_ctx->res_ctx,
>-					dc->res_pool,
>-					del_pipe->stream_res.audio,
>-					false);
>-
>-			resource_unreference_clock_source(&new_ctx->res_ctx,
>-							  dc->res_pool,
>-							  del_pipe->clock_source);
>-
>-			if (dc->res_pool->funcs->remove_stream_from_ctx)
>-				dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
>-
>-			memset(del_pipe, 0, sizeof(*del_pipe));
>-			if (odm_pipe)
>-				memset(odm_pipe, 0, sizeof(*odm_pipe));
>-
>-			break;
>-		}
>-	}
>+	struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
>+	struct pipe_ctx *odm_pipe;
> 
> 	if (!del_pipe) {
> 		DC_ERROR("Pipe not found for stream %p !\n", stream);
> 		return DC_ERROR_UNEXPECTED;
> 	}
> 
>+	odm_pipe = del_pipe->next_odm_pipe;
>+
>+	/* Release primary pipe */
>+	ASSERT(del_pipe->stream_res.stream_enc);
>+	update_stream_engine_usage(
>+			&new_ctx->res_ctx,
>+				dc->res_pool,
>+			del_pipe->stream_res.stream_enc,
>+			false);
>+
>+	if (del_pipe->stream_res.audio)
>+		update_audio_usage(
>+			&new_ctx->res_ctx,
>+			dc->res_pool,
>+			del_pipe->stream_res.audio,
>+			false);
>+
>+	resource_unreference_clock_source(&new_ctx->res_ctx,
>+					  dc->res_pool,
>+					  del_pipe->clock_source);
>+
>+	if (dc->res_pool->funcs->remove_stream_from_ctx)
>+		dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
>+
>+	while (odm_pipe) {
>+		struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
>+
>+		memset(odm_pipe, 0, sizeof(*odm_pipe));
>+		odm_pipe = next_odm_pipe;
>+	}
>+	memset(del_pipe, 0, sizeof(*del_pipe));
>+
> 	for (i = 0; i < new_ctx->stream_count; i++)
> 		if (new_ctx->streams[i] == stream)
> 			break;
>@@ -1880,7 +1848,7 @@
> 		struct dc_stream_state *stream)
> {
> 	struct dc_link *link = stream->link;
>-	unsigned int inst;
>+	unsigned int inst, tg_inst;
> 
> 	/* Check for enabled DIG to identify enabled display */
> 	if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
>@@ -1892,28 +1860,37 @@
> 	 * current implementation always map 1-to-1, so this code makes
> 	 * the same assumption and doesn't check OTG source.
> 	 */
>-	inst = link->link_enc->funcs->get_dig_frontend(link->link_enc) - 1;
>+	inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
> 
> 	/* Instance should be within the range of the pool */
> 	if (inst >= pool->pipe_count)
> 		return -1;
> 
>-	if (!res_ctx->pipe_ctx[inst].stream) {
>-		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[inst];
>+	if (inst >= pool->stream_enc_count)
>+		return -1;
>+
>+	tg_inst = pool->stream_enc[inst]->funcs->dig_source_otg(pool->stream_enc[inst]);
> 
>-		pipe_ctx->stream_res.tg = pool->timing_generators[inst];
>-		pipe_ctx->plane_res.mi = pool->mis[inst];
>-		pipe_ctx->plane_res.hubp = pool->hubps[inst];
>-		pipe_ctx->plane_res.ipp = pool->ipps[inst];
>-		pipe_ctx->plane_res.xfm = pool->transforms[inst];
>-		pipe_ctx->plane_res.dpp = pool->dpps[inst];
>-		pipe_ctx->stream_res.opp = pool->opps[inst];
>-		if (pool->dpps[inst])
>-			pipe_ctx->plane_res.mpcc_inst = pool->dpps[inst]->inst;
>-		pipe_ctx->pipe_idx = inst;
>+	if (tg_inst >= pool->timing_generator_count)
>+		return false;
>+
>+	if (!res_ctx->pipe_ctx[tg_inst].stream) {
>+		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
>+
>+		pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
>+		pipe_ctx->plane_res.mi = pool->mis[tg_inst];
>+		pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
>+		pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
>+		pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
>+		pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
>+		pipe_ctx->stream_res.opp = pool->opps[tg_inst];
>+
>+		if (pool->dpps[tg_inst])
>+			pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
>+		pipe_ctx->pipe_idx = tg_inst;
> 
> 		pipe_ctx->stream = stream;
>-		return inst;
>+		return tg_inst;
> 	}
> 
> 	return -1;
>@@ -2475,6 +2452,12 @@
> 
> 		if (cur_pipe->bottom_pipe)
> 			cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
>+
>+		if (cur_pipe->next_odm_pipe)
>+			cur_pipe->next_odm_pipe =  &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
>+
>+		if (cur_pipe->prev_odm_pipe)
>+			cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
> 	}
> 
> 	for (i = 0; i < dst_ctx->stream_count; i++) {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_stream.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_stream.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_stream.c	2019-08-31 15:01:11.859736168 -0500
>@@ -566,6 +566,7 @@
> 
> 	return ret;
> }
>+
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream)
> {
>@@ -597,6 +598,14 @@
> 	struct hubp *hubp;
> 	int i;
> 
>+	/* Dynamic metadata is only supported on HDMI or DP */
>+	if (!dc_is_hdmi_signal(stream->signal) && !dc_is_dp_signal(stream->signal))
>+		return false;
>+
>+	/* Check hardware support */
>+	if (!dc->hwss.program_dmdata_engine)
>+		return false;
>+
> 	for (i = 0; i < MAX_PIPES; i++) {
> 		pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
> 		if (pipe_ctx->stream == stream)
>@@ -612,23 +621,7 @@
> 
> 	pipe_ctx->stream->dmdata_address = attr->address;
> 
>-	if (pipe_ctx->stream_res.stream_enc &&
>-			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL) {
>-		if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
>-			/* if using dynamic meta, don't set up generic infopackets */
>-			pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
>-			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(
>-					pipe_ctx->stream_res.stream_enc,
>-					true, pipe_ctx->plane_res.hubp->inst,
>-					dc_is_dp_signal(pipe_ctx->stream->signal) ?
>-							dmdata_dp : dmdata_hdmi);
>-		} else
>-			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(
>-					pipe_ctx->stream_res.stream_enc,
>-					false, pipe_ctx->plane_res.hubp->inst,
>-					dc_is_dp_signal(pipe_ctx->stream->signal) ?
>-							dmdata_dp : dmdata_hdmi);
>-	}
>+	dc->hwss.program_dmdata_engine(pipe_ctx);
> 
> 	if (hubp->funcs->dmdata_set_attributes != NULL &&
> 			pipe_ctx->stream->dmdata_address.quad_part != 0) {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_surface.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/core/dc_surface.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/core/dc_surface.c	2019-08-31 15:01:11.859736168 -0500
>@@ -60,7 +60,6 @@
> 	plane_state->lut3d_func = dc_create_3dlut_func();
> 	if (plane_state->lut3d_func != NULL) {
> 		plane_state->lut3d_func->ctx = ctx;
>-		plane_state->lut3d_func->initialized = false;
> 	}
> 	plane_state->blend_tf = dc_create_transfer_func();
> 	if (plane_state->blend_tf != NULL) {
>@@ -279,7 +278,7 @@
> 		goto alloc_fail;
> 
> 	kref_init(&lut->refcount);
>-	lut->initialized = false;
>+	lut->state.raw = 0;
> 
> 	return lut;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_bios_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_bios_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_bios_types.h	2019-08-31 15:01:11.859736168 -0500
>@@ -61,9 +61,6 @@
> 		struct graphics_object_id connector_object_id,
> 		uint32_t device_tag_index,
> 		struct connector_device_tag_info *info);
>-	enum bp_result (*get_firmware_info)(
>-		struct dc_bios *bios,
>-		struct dc_firmware_info *info);
> 	enum bp_result (*get_spread_spectrum_info)(
> 		struct dc_bios *bios,
> 		enum as_signal_type signal,
>@@ -152,6 +149,8 @@
> 	struct dc_context *ctx;
> 	const struct bios_registers *regs;
> 	struct integrated_info *integrated_info;
>+	struct dc_firmware_info fw_info;
>+	bool fw_info_valid;
> };
> 
> #endif /* DC_BIOS_TYPES_H */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_dp_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_dp_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_dp_types.h	2019-08-31 15:01:11.859736168 -0500
>@@ -90,6 +90,13 @@
> 	POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
> };
> 
>+enum dc_dp_training_pattern {
>+	DP_TRAINING_PATTERN_SEQUENCE_1 = 0,
>+	DP_TRAINING_PATTERN_SEQUENCE_2,
>+	DP_TRAINING_PATTERN_SEQUENCE_3,
>+	DP_TRAINING_PATTERN_SEQUENCE_4,
>+};
>+
> struct dc_link_settings {
> 	enum dc_lane_count lane_count;
> 	enum dc_link_rate link_rate;
>@@ -109,6 +116,23 @@
> 	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
> };
> 
>+struct dc_link_training_overrides {
>+	enum dc_voltage_swing *voltage_swing;
>+	enum dc_pre_emphasis *pre_emphasis;
>+	enum dc_post_cursor2 *post_cursor2;
>+
>+	uint16_t *cr_pattern_time;
>+	uint16_t *eq_pattern_time;
>+	enum dc_dp_training_pattern *pattern_for_eq;
>+
>+	enum dc_link_spread *downspread;
>+	bool *alternate_scrambler_reset;
>+	bool *enhanced_framing;
>+	bool *mst_enable;
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	bool *fec_enable;
>+#endif
>+};
> 
> union dpcd_rev {
> 	struct {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c	2019-08-31 15:01:11.859736168 -0500
>@@ -145,20 +145,20 @@
> 	if (channel_count > 2) {
> 
> 		/* Based on HDMI spec 1.3 Table 7.5 */
>-		if ((crtc_info->requested_pixel_clock <= 27000) &&
>+		if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
> 		(crtc_info->v_active <= 576) &&
> 		!(crtc_info->interlaced) &&
> 		!(crtc_info->pixel_repetition == 2 ||
> 		crtc_info->pixel_repetition == 4)) {
> 			limit_freq_to_48_khz = true;
> 
>-		} else if ((crtc_info->requested_pixel_clock <= 27000) &&
>+		} else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
> 				(crtc_info->v_active <= 576) &&
> 				(crtc_info->interlaced) &&
> 				(crtc_info->pixel_repetition == 2)) {
> 			limit_freq_to_88_2_khz = true;
> 
>-		} else if ((crtc_info->requested_pixel_clock <= 54000) &&
>+		} else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) &&
> 				(crtc_info->v_active <= 576) &&
> 				!(crtc_info->interlaced)) {
> 			limit_freq_to_174_4_khz = true;
>@@ -613,6 +613,8 @@
> 
> 	AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
> 		value);
>+	DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n",
>+		audio->inst, value, audio_info->display_name);
> 
> 	/*
> 	*write the port ID:
>@@ -737,8 +739,8 @@
> 
> /* search pixel clock value for Azalia HDMI Audio */
> static void get_azalia_clock_info_hdmi(
>-	uint32_t crtc_pixel_clock_in_khz,
>-	uint32_t actual_pixel_clock_in_khz,
>+	uint32_t crtc_pixel_clock_100hz,
>+	uint32_t actual_pixel_clock_100Hz,
> 	struct azalia_clock_info *azalia_clock_info)
> {
> 	/* audio_dto_phase= 24 * 10,000;
>@@ -749,11 +751,11 @@
> 	/* audio_dto_module = PCLKFrequency * 10,000;
> 	 *  [khz] -> [100Hz] */
> 	azalia_clock_info->audio_dto_module =
>-			actual_pixel_clock_in_khz * 10;
>+			actual_pixel_clock_100Hz;
> }
> 
> static void get_azalia_clock_info_dp(
>-	uint32_t requested_pixel_clock_in_khz,
>+	uint32_t requested_pixel_clock_100Hz,
> 	const struct audio_pll_info *pll_info,
> 	struct azalia_clock_info *azalia_clock_info)
> {
>@@ -792,15 +794,15 @@
> 
> 		/* calculate DTO settings */
> 		get_azalia_clock_info_hdmi(
>-			crtc_info->requested_pixel_clock,
>-			crtc_info->calculated_pixel_clock,
>+			crtc_info->requested_pixel_clock_100Hz,
>+			crtc_info->calculated_pixel_clock_100Hz,
> 			&clock_info);
> 
>-		DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock = %d"\
>-				"calculated_pixel_clock =%d\n"\
>+		DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
>+				"calculated_pixel_clock_100Hz =%d\n"\
> 				"audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
>-				crtc_info->requested_pixel_clock,\
>-				crtc_info->calculated_pixel_clock,\
>+				crtc_info->requested_pixel_clock_100Hz,\
>+				crtc_info->calculated_pixel_clock_100Hz,\
> 				clock_info.audio_dto_module,\
> 				clock_info.audio_dto_phase);
> 
>@@ -833,7 +835,7 @@
> 
> 		calculate DTO settings */
> 		get_azalia_clock_info_dp(
>-			crtc_info->requested_pixel_clock,
>+			crtc_info->requested_pixel_clock_100Hz,
> 			pll_info,
> 			&clock_info);
> 
>@@ -922,7 +924,6 @@
> 	.az_configure = dce_aud_az_configure,
> 	.destroy = dce_aud_destroy,
> };
>-
> void dce_aud_destroy(struct audio **audio)
> {
> 	struct dce_audio *aud = DCE_AUD(*audio);
>@@ -936,7 +937,7 @@
> 		unsigned int inst,
> 		const struct dce_audio_registers *reg,
> 		const struct dce_audio_shift *shifts,
>-		const struct dce_aduio_mask *masks
>+		const struct dce_audio_mask *masks
> 		)
> {
> 	struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
>@@ -953,7 +954,6 @@
> 	audio->regs = reg;
> 	audio->shifts = shifts;
> 	audio->masks = masks;
>-
> 	return &audio->base;
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h	2019-08-31 15:01:11.859736168 -0500
>@@ -101,7 +101,7 @@
> 	uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;
> };
> 
>-struct dce_aduio_mask {
>+struct dce_audio_mask {
> 	uint32_t AZALIA_ENDPOINT_REG_INDEX;
> 	uint32_t AZALIA_ENDPOINT_REG_DATA;
> 
>@@ -125,7 +125,7 @@
> 	struct audio base;
> 	const struct dce_audio_registers *regs;
> 	const struct dce_audio_shift *shifts;
>-	const struct dce_aduio_mask *masks;
>+	const struct dce_audio_mask *masks;
> };
> 
> struct audio *dce_audio_create(
>@@ -133,7 +133,7 @@
> 		unsigned int inst,
> 		const struct dce_audio_registers *reg,
> 		const struct dce_audio_shift *shifts,
>-		const struct dce_aduio_mask *masks);
>+		const struct dce_audio_mask *masks);
> 
> void dce_aud_destroy(struct audio **audio);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c	2019-08-31 15:01:11.860736168 -0500
>@@ -30,6 +30,7 @@
> #include "core_types.h"
> #include "dce_aux.h"
> #include "dce/dce_11_0_sh_mask.h"
>+#include "dm_event_log.h"
> 
> #define CTX \
> 	aux110->base.ctx
>@@ -252,6 +253,8 @@
> 	}
> 
> 	REG_UPDATE(AUX_SW_CONTROL, AUX_SW_GO, 1);
>+	EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE,
>+					request->action, request->address, request->length, request->data);
> }
> 
> static int read_channel_reply(struct dce_aux *engine, uint32_t size,
>@@ -480,9 +483,13 @@
> 	*operation_result = get_channel_status(aux_engine, &returned_bytes);
> 
> 	if (*operation_result == AUX_CHANNEL_OPERATION_SUCCEEDED) {
>-		read_channel_reply(aux_engine, payload->length,
>+		int bytes_replied = 0;
>+		bytes_replied = read_channel_reply(aux_engine, payload->length,
> 					 payload->data, payload->reply,
> 					 &status);
>+		EVENT_LOG_AUX_REP(aux_engine->ddc->pin_data->en,
>+					EVENT_LOG_AUX_ORIGIN_NATIVE, *payload->reply,
>+					bytes_replied, payload->data);
> 		res = returned_bytes;
> 	} else {
> 		res = -1;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c	2019-08-31 15:01:11.860736168 -0500
>@@ -1061,7 +1061,8 @@
> static const struct clock_source_funcs dcn20_clk_src_funcs = {
> 	.cs_power_down = dce110_clock_source_power_down,
> 	.program_pix_clk = dcn20_program_pix_clk,
>-	.get_pix_clk_dividers = dce112_get_pix_clk_dividers
>+	.get_pix_clk_dividers = dce112_get_pix_clk_dividers,
>+	.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
> };
> #endif
> 
>@@ -1234,37 +1235,36 @@
> 			struct calc_pll_clock_source_init_data *init_data)
> {
> 	uint32_t i;
>-	struct dc_firmware_info fw_info = { { 0 } };
>+	struct dc_firmware_info *fw_info;
> 	if (calc_pll_cs == NULL ||
> 			init_data == NULL ||
> 			init_data->bp == NULL)
> 		return false;
> 
>-	if (init_data->bp->funcs->get_firmware_info(
>-				init_data->bp,
>-				&fw_info) != BP_RESULT_OK)
>+	if (!init_data->bp->fw_info_valid)
> 		return false;
> 
>+	fw_info = &init_data->bp->fw_info;
> 	calc_pll_cs->ctx = init_data->ctx;
>-	calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency;
>+	calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;
> 	calc_pll_cs->min_vco_khz =
>-			fw_info.pll_info.min_output_pxl_clk_pll_frequency;
>+			fw_info->pll_info.min_output_pxl_clk_pll_frequency;
> 	calc_pll_cs->max_vco_khz =
>-			fw_info.pll_info.max_output_pxl_clk_pll_frequency;
>+			fw_info->pll_info.max_output_pxl_clk_pll_frequency;
> 
> 	if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
> 		calc_pll_cs->max_pll_input_freq_khz =
> 			init_data->max_override_input_pxl_clk_pll_freq_khz;
> 	else
> 		calc_pll_cs->max_pll_input_freq_khz =
>-			fw_info.pll_info.max_input_pxl_clk_pll_frequency;
>+			fw_info->pll_info.max_input_pxl_clk_pll_frequency;
> 
> 	if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
> 		calc_pll_cs->min_pll_input_freq_khz =
> 			init_data->min_override_input_pxl_clk_pll_freq_khz;
> 	else
> 		calc_pll_cs->min_pll_input_freq_khz =
>-			fw_info.pll_info.min_input_pxl_clk_pll_frequency;
>+			fw_info->pll_info.min_input_pxl_clk_pll_frequency;
> 
> 	calc_pll_cs->min_pix_clock_pll_post_divider =
> 			init_data->min_pix_clk_pll_post_divider;
>@@ -1316,7 +1316,6 @@
> 	const struct dce110_clk_src_shift *cs_shift,
> 	const struct dce110_clk_src_mask *cs_mask)
> {
>-	struct dc_firmware_info fw_info = { { 0 } };
> 	struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
> 	struct calc_pll_clock_source_init_data calc_pll_cs_init_data;
> 
>@@ -1329,14 +1328,12 @@
> 	clk_src->cs_shift = cs_shift;
> 	clk_src->cs_mask = cs_mask;
> 
>-	if (clk_src->bios->funcs->get_firmware_info(
>-			clk_src->bios, &fw_info) != BP_RESULT_OK) {
>+	if (!clk_src->bios->fw_info_valid) {
> 		ASSERT_CRITICAL(false);
> 		goto unexpected_failure;
> 	}
> 
>-	clk_src->ext_clk_khz =
>-			fw_info.external_clock_source_frequency_for_dp;
>+	clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
> 
> 	/* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
> 	calc_pll_cs_init_data.bp = bios;
>@@ -1376,7 +1373,7 @@
> 			FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
> 	calc_pll_cs_init_data_hdmi.ctx = ctx;
> 
>-	clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
>+	clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency;
> 
> 	if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
> 		return true;
>@@ -1419,8 +1416,6 @@
> 	const struct dce110_clk_src_shift *cs_shift,
> 	const struct dce110_clk_src_mask *cs_mask)
> {
>-	struct dc_firmware_info fw_info = { { 0 } };
>-
> 	clk_src->base.ctx = ctx;
> 	clk_src->bios = bios;
> 	clk_src->base.id = id;
>@@ -1430,13 +1425,12 @@
> 	clk_src->cs_shift = cs_shift;
> 	clk_src->cs_mask = cs_mask;
> 
>-	if (clk_src->bios->funcs->get_firmware_info(
>-			clk_src->bios, &fw_info) != BP_RESULT_OK) {
>+	if (!clk_src->bios->fw_info_valid) {
> 		ASSERT_CRITICAL(false);
> 		return false;
> 	}
> 
>-	clk_src->ext_clk_khz = fw_info.external_clock_source_frequency_for_dp;
>+	clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
> 
> 	return true;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h	2019-08-31 15:01:11.860736168 -0500
>@@ -78,6 +78,23 @@
> 		SRII(PIXEL_RATE_CNTL, OTG, 5)
> #endif
> 
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+#define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
>+		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
>+		SRII(PHASE, DP_DTO, 0),\
>+		SRII(PHASE, DP_DTO, 1),\
>+		SRII(PHASE, DP_DTO, 2),\
>+		SRII(PHASE, DP_DTO, 3),\
>+		SRII(MODULO, DP_DTO, 0),\
>+		SRII(MODULO, DP_DTO, 1),\
>+		SRII(MODULO, DP_DTO, 2),\
>+		SRII(MODULO, DP_DTO, 3),\
>+		SRII(PIXEL_RATE_CNTL, OTG, 0),\
>+		SRII(PIXEL_RATE_CNTL, OTG, 1),\
>+		SRII(PIXEL_RATE_CNTL, OTG, 2),\
>+		SRII(PIXEL_RATE_CNTL, OTG, 3)
>+#endif
>+
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
> 	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h	2019-08-31 15:01:11.860736168 -0500
>@@ -62,6 +62,10 @@
> 	SRII(BLND_CONTROL, BLND, 4), \
> 	SRII(BLND_CONTROL, BLND, 5)
> 
>+#define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \
>+	SRII(PIXEL_RATE_CNTL, blk, inst), \
>+	SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst)
>+
> #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \
> 	SRII(PIXEL_RATE_CNTL, blk, 0), \
> 	SRII(PIXEL_RATE_CNTL, blk, 1), \
>@@ -151,7 +155,10 @@
> 	SR(DCCG_GATE_DISABLE_CNTL2), \
> 	SR(DCFCLK_CNTL),\
> 	SR(DCFCLK_CNTL), \
>-	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
>+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
>+
>+
>+#define MMHUB_DCN_REG_LIST()\
> 	/* todo:  get these from GVM instead of reading registers ourselves */\
> 	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\
> 	MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\
>@@ -166,10 +173,14 @@
> 	MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\
> 	MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR)
> 
>+
> #define HWSEQ_DCN1_REG_LIST()\
> 	HWSEQ_DCN_REG_LIST(), \
>-	HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
>-	HWSEQ_PHYPLL_REG_LIST(OTG), \
>+	MMHUB_DCN_REG_LIST(), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
> 	SR(DCHUBBUB_SDPIF_FB_BASE),\
> 	SR(DCHUBBUB_SDPIF_FB_OFFSET),\
> 	SR(DCHUBBUB_SDPIF_AGP_BASE),\
>@@ -202,8 +213,12 @@
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> #define HWSEQ_DCN2_REG_LIST()\
> 	HWSEQ_DCN_REG_LIST(), \
>-	HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
>-	HWSEQ_PHYPLL_REG_LIST(OTG), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \
> 	SR(MICROSECOND_TIME_BASE_DIV), \
> 	SR(MILLISECOND_TIME_BASE_DIV), \
> 	SR(DISPCLK_FREQ_CHANGE_CNTL), \
>@@ -227,8 +242,8 @@
> 	SR(DOMAIN7_PG_CONFIG), \
> 	SR(DOMAIN8_PG_CONFIG), \
> 	SR(DOMAIN9_PG_CONFIG), \
>-	SR(DOMAIN10_PG_CONFIG), \
>-	SR(DOMAIN11_PG_CONFIG), \
>+/*	SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\
>+/*	SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\
> 	SR(DOMAIN16_PG_CONFIG), \
> 	SR(DOMAIN17_PG_CONFIG), \
> 	SR(DOMAIN18_PG_CONFIG), \
>@@ -263,6 +278,59 @@
> 	BL_REG_LIST()
> #endif
> 
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+#define HWSEQ_DCN21_REG_LIST()\
>+	HWSEQ_DCN_REG_LIST(), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
>+	HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
>+	MMHUB_DCN_REG_LIST(), \
>+	SR(MICROSECOND_TIME_BASE_DIV), \
>+	SR(MILLISECOND_TIME_BASE_DIV), \
>+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
>+	SR(RBBMIF_TIMEOUT_DIS), \
>+	SR(RBBMIF_TIMEOUT_DIS_2), \
>+	SR(DCHUBBUB_CRC_CTRL), \
>+	SR(DPP_TOP0_DPP_CRC_CTRL), \
>+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
>+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
>+	SR(MPC_CRC_CTRL), \
>+	SR(MPC_CRC_RESULT_GB), \
>+	SR(MPC_CRC_RESULT_C), \
>+	SR(MPC_CRC_RESULT_AR), \
>+	SR(DOMAIN0_PG_CONFIG), \
>+	SR(DOMAIN1_PG_CONFIG), \
>+	SR(DOMAIN2_PG_CONFIG), \
>+	SR(DOMAIN3_PG_CONFIG), \
>+	SR(DOMAIN4_PG_CONFIG), \
>+	SR(DOMAIN5_PG_CONFIG), \
>+	SR(DOMAIN6_PG_CONFIG), \
>+	SR(DOMAIN7_PG_CONFIG), \
>+	SR(DOMAIN16_PG_CONFIG), \
>+	SR(DOMAIN17_PG_CONFIG), \
>+	SR(DOMAIN18_PG_CONFIG), \
>+	SR(DOMAIN0_PG_STATUS), \
>+	SR(DOMAIN1_PG_STATUS), \
>+	SR(DOMAIN2_PG_STATUS), \
>+	SR(DOMAIN3_PG_STATUS), \
>+	SR(DOMAIN4_PG_STATUS), \
>+	SR(DOMAIN5_PG_STATUS), \
>+	SR(DOMAIN6_PG_STATUS), \
>+	SR(DOMAIN7_PG_STATUS), \
>+	SR(DOMAIN16_PG_STATUS), \
>+	SR(DOMAIN17_PG_STATUS), \
>+	SR(DOMAIN18_PG_STATUS), \
>+	SR(D1VGA_CONTROL), \
>+	SR(D2VGA_CONTROL), \
>+	SR(D3VGA_CONTROL), \
>+	SR(D4VGA_CONTROL), \
>+	SR(D5VGA_CONTROL), \
>+	SR(D6VGA_CONTROL), \
>+	SR(DC_IP_REQUEST_CNTL), \
>+	BL_REG_LIST()
>+#endif
>+
> struct dce_hwseq_registers {
> 
> 		/* Backlight registers */
>@@ -401,36 +469,34 @@
> 	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
> 	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
> 
>+#define HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)\
>+	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
>+	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
>+	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
>+	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
>+
> #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\
> 	.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \
> 	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
> 	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\
> 	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\
> 	HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\
>-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
>-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
>-	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
>+	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
>+	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
> 
> #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\
> 	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\
> 	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\
>-	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \
>-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
>-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
>+	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
>+	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
> 
> #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\
> 	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
> 	SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\
>-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
>-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
>-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
>-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
> 	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)
> 
> #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\
> 	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
>-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
>-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\
> 	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_)
> 
> #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\
>@@ -438,18 +504,15 @@
> 	SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\
> 	SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\
> 	SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\
>-	SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \
>-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
>-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
>+	SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)
> 
> #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\
> 	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\
> 	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\
> 	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\
> 	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\
>-	HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \
>-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
>-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
>+	HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh),\
>+	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
> 
> #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\
> 	HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\
>@@ -512,10 +575,7 @@
> 	HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\
> 	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
> 	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
>-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
>-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \
>-	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \
>-	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
>+	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
> 
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
>@@ -576,6 +636,49 @@
> 	HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \
> 	HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \
> 	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
>+	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
>+#endif
>+
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+#define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\
>+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
>+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
>+	HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
>+	HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
>+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
>+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
>+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
>+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
>+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
>+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
>+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
>+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
>+	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
>+	HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
>+	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
>+	HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
>+	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
>+	HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
>+	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
>+	HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
>+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
>+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
>+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
>+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
>+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
>+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
>+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
>+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
>+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
>+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
>+	HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
>+	HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
>+	HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
>+	HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
>+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
>+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
>+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
>+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
> 	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
> 	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
> #endif
>@@ -612,9 +715,9 @@
> 	type ENABLE_L1_TLB;\
> 	type SYSTEM_ACCESS_MODE;\
> 	type LVTMA_BLON;\
>-	type LVTMA_PWRSEQ_TARGET_STATE_R;\
> 	type LVTMA_DIGON;\
>-	type LVTMA_DIGON_OVRD;
>+	type LVTMA_DIGON_OVRD;\
>+	type LVTMA_PWRSEQ_TARGET_STATE_R;
> 
> #define HWSEQ_DCN_REG_FIELD_LIST(type) \
> 	type HUBP_VTG_SEL; \
>@@ -696,7 +799,8 @@
> 	type D2VGA_MODE_ENABLE; \
> 	type D3VGA_MODE_ENABLE; \
> 	type D4VGA_MODE_ENABLE; \
>-	type AZALIA_AUDIO_DTO_MODULE;
>+	type AZALIA_AUDIO_DTO_MODULE;\
>+	type HPO_HDMISTREAMCLK_GATE_DIS;
> 
> struct dce_hwseq_shift {
> 	HWSEQ_REG_FIELD_LIST(uint8_t)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c	2019-08-31 15:01:11.860736168 -0500
>@@ -25,6 +25,7 @@
> 
> #include <linux/delay.h>
> 
>+#include "resource.h"
> #include "dce_i2c.h"
> #include "dce_i2c_hw.h"
> #include "reg_helper.h"
>@@ -99,17 +100,6 @@
> 			dce_i2c_hw->buffer_used_bytes;
> }
> 
>-uint32_t get_reference_clock(
>-		struct dc_bios *bios)
>-{
>-	struct dc_firmware_info info = { { 0 } };
>-
>-	if (bios->funcs->get_firmware_info(bios, &info) != BP_RESULT_OK)
>-		return 0;
>-
>-	return info.pll_info.crystal_frequency;
>-}
>-
> static uint32_t get_speed(
> 	const struct dce_i2c_hw *dce_i2c_hw)
> {
>@@ -401,7 +391,7 @@
> 	if (ddc->hw_info.hw_supported) {
> 		enum gpio_ddc_line line = dal_ddc_get_line(ddc);
> 
>-		if (line < pool->pipe_count)
>+		if (line < pool->res_cap->num_ddc)
> 			dce_i2c_hw = pool->hw_i2cs[line];
> 	}
> 
>@@ -632,7 +622,7 @@
> {
> 	dce_i2c_hw->ctx = ctx;
> 	dce_i2c_hw->engine_id = engine_id;
>-	dce_i2c_hw->reference_frequency = get_reference_clock(ctx->dc_bios) >> 1;
>+	dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1;
> 	dce_i2c_hw->regs = regs;
> 	dce_i2c_hw->shifts = shifts;
> 	dce_i2c_hw->masks = masks;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c	2019-08-31 15:01:11.860736168 -0500
>@@ -391,10 +391,10 @@
> static void program_size_and_rotation(
> 	struct dce_mem_input *dce_mi,
> 	enum dc_rotation_angle rotation,
>-	const union plane_size *plane_size)
>+	const struct plane_size *plane_size)
> {
>-	const struct rect *in_rect = &plane_size->grph.surface_size;
>-	struct rect hw_rect = plane_size->grph.surface_size;
>+	const struct rect *in_rect = &plane_size->surface_size;
>+	struct rect hw_rect = plane_size->surface_size;
> 	const uint32_t rotation_angles[ROTATION_ANGLE_COUNT] = {
> 			[ROTATION_ANGLE_0] = 0,
> 			[ROTATION_ANGLE_90] = 1,
>@@ -423,7 +423,7 @@
> 			GRPH_Y_END, hw_rect.height);
> 
> 	REG_SET(GRPH_PITCH, 0,
>-			GRPH_PITCH, plane_size->grph.surface_pitch);
>+			GRPH_PITCH, plane_size->surface_pitch);
> 
> 	REG_SET(HW_ROTATION, 0,
> 			GRPH_ROTATION_ANGLE, rotation_angles[rotation]);
>@@ -505,7 +505,7 @@
> 	struct mem_input *mi,
> 	enum surface_pixel_format format,
> 	union dc_tiling_info *tiling_info,
>-	union plane_size *plane_size,
>+	struct plane_size *plane_size,
> 	enum dc_rotation_angle rotation,
> 	struct dc_plane_dcc_param *dcc,
> 	bool horizontal_mirror)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c	2019-08-31 15:01:11.860736168 -0500
>@@ -1038,6 +1038,24 @@
> }
> 
> 
>+static void dce110_reset_hdmi_stream_attribute(
>+	struct stream_encoder *enc)
>+{
>+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
>+	if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
>+		REG_UPDATE_5(HDMI_CONTROL,
>+			HDMI_PACKET_GEN_VERSION, 1,
>+			HDMI_KEEPOUT_MODE, 1,
>+			HDMI_DEEP_COLOR_ENABLE, 0,
>+			HDMI_DATA_SCRAMBLE_EN, 0,
>+			HDMI_CLOCK_CHANNEL_RATE, 0);
>+	else
>+		REG_UPDATE_3(HDMI_CONTROL,
>+			HDMI_PACKET_GEN_VERSION, 1,
>+			HDMI_KEEPOUT_MODE, 1,
>+			HDMI_DEEP_COLOR_ENABLE, 0);
>+}
>+
> #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
> #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
> 
>@@ -1251,13 +1269,13 @@
> 
> static void get_audio_clock_info(
> 	enum dc_color_depth color_depth,
>-	uint32_t crtc_pixel_clock_in_khz,
>-	uint32_t actual_pixel_clock_in_khz,
>+	uint32_t crtc_pixel_clock_100Hz,
>+	uint32_t actual_pixel_clock_100Hz,
> 	struct audio_clock_info *audio_clock_info)
> {
> 	const struct audio_clock_info *clock_info;
> 	uint32_t index;
>-	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
>+	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
> 	uint32_t audio_array_size;
> 
> 	switch (color_depth) {
>@@ -1294,16 +1312,16 @@
> 	}
> 
> 	/* not found */
>-	if (actual_pixel_clock_in_khz == 0)
>-		actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
>+	if (actual_pixel_clock_100Hz == 0)
>+		actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
> 
> 	/* See HDMI spec  the table entry under
> 	 *  pixel clock of "Other". */
> 	audio_clock_info->pixel_clock_in_10khz =
>-			actual_pixel_clock_in_khz / 10;
>-	audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
>-	audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
>-	audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
>+			actual_pixel_clock_100Hz / 100;
>+	audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
>+	audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
>+	audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
> 
> 	audio_clock_info->n_32khz = 4096;
> 	audio_clock_info->n_44khz = 6272;
>@@ -1369,14 +1387,14 @@
> 
> 	/* Program audio clock sample/regeneration parameters */
> 	get_audio_clock_info(crtc_info->color_depth,
>-			     crtc_info->requested_pixel_clock,
>-			     crtc_info->calculated_pixel_clock,
>+			     crtc_info->requested_pixel_clock_100Hz,
>+			     crtc_info->calculated_pixel_clock_100Hz,
> 			     &audio_clock_info);
> 	DC_LOG_HW_AUDIO(
>-			"\n%s:Input::requested_pixel_clock = %d"	\
>-			"calculated_pixel_clock = %d \n", __func__,	\
>-			crtc_info->requested_pixel_clock,		\
>-			crtc_info->calculated_pixel_clock);
>+			"\n%s:Input::requested_pixel_clock_100Hz = %d"	\
>+			"calculated_pixel_clock_100Hz = %d \n", __func__,	\
>+			crtc_info->requested_pixel_clock_100Hz,		\
>+			crtc_info->calculated_pixel_clock_100Hz);
> 
> 	/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
> 	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
>@@ -1584,6 +1602,17 @@
> 	REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
> }
> 
>+static unsigned int dig_source_otg(
>+	struct stream_encoder *enc)
>+{
>+	uint32_t tg_inst = 0;
>+	struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
>+
>+	REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
>+
>+	return tg_inst;
>+}
>+
> static const struct stream_encoder_funcs dce110_str_enc_funcs = {
> 	.dp_set_stream_attribute =
> 		dce110_stream_encoder_dp_set_stream_attribute,
>@@ -1618,6 +1647,8 @@
> 	.setup_stereo_sync  = setup_stereo_sync,
> 	.set_avmute = dce110_stream_encoder_set_avmute,
> 	.dig_connect_to_otg  = dig_connect_to_otg,
>+	.hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute,
>+	.dig_source_otg = dig_source_otg,
> };
> 
> void dce110_stream_encoder_construct(
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c	2019-08-31 15:01:11.861736168 -0500
>@@ -304,7 +304,7 @@
> 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
> };
> 
>-static const struct dce_aduio_mask audio_mask = {
>+static const struct dce_audio_mask audio_mask = {
> 		AUD_COMMON_MASK_SH_LIST(_MASK)
> };
> 
>@@ -910,7 +910,6 @@
> {
> 	unsigned int i;
> 	struct dc_context *ctx = dc->ctx;
>-	struct dc_firmware_info info;
> 	struct dc_bios *bp;
> 
> 	ctx->dc_bios->regs = &bios_regs;
>@@ -921,8 +920,7 @@
> 
> 	bp = ctx->dc_bios;
> 
>-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
>-		info.external_clock_source_frequency_for_dp != 0) {
>+	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
> 		pool->base.dp_clock_source =
> 				dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c	2019-08-31 15:01:11.861736168 -0500
>@@ -667,29 +667,7 @@
> 	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
> 						    pipe_ctx->stream_res.stream_enc->id, true);
> 
>-	/* update AVI info frame (HDMI, DP)*/
>-	/* TODO: FPGA may change to hwss.update_info_frame */
>-
>-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>-	if (pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL &&
>-			pipe_ctx->plane_res.hubp != NULL) {
>-		if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
>-			/* if using dynamic meta, don't set up generic infopackets */
>-			pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
>-			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(
>-					pipe_ctx->stream_res.stream_enc,
>-					true, pipe_ctx->plane_res.hubp->inst,
>-					dc_is_dp_signal(pipe_ctx->stream->signal) ?
>-							dmdata_dp : dmdata_hdmi);
>-		} else
>-			pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(
>-					pipe_ctx->stream_res.stream_enc,
>-					false, pipe_ctx->plane_res.hubp->inst,
>-					dc_is_dp_signal(pipe_ctx->stream->signal) ?
>-							dmdata_dp : dmdata_hdmi);
>-	}
>-#endif
>-	dce110_update_info_frame(pipe_ctx);
>+	link->dc->hwss.update_info_frame(pipe_ctx);
> 
> 	/* enable early control to avoid corruption on DP monitor*/
> 	active_total_with_borders =
>@@ -753,7 +731,7 @@
>  * @brief
>  * eDP only.
>  */
>-void hwss_edp_wait_for_hpd_ready(
>+void dce110_edp_wait_for_hpd_ready(
> 		struct dc_link *link,
> 		bool power_up)
> {
>@@ -821,7 +799,7 @@
> 	}
> }
> 
>-void hwss_edp_power_control(
>+void dce110_edp_power_control(
> 		struct dc_link *link,
> 		bool power_up)
> {
>@@ -903,7 +881,7 @@
>  * @brief
>  * eDP only. Control the backlight of the eDP panel
>  */
>-void hwss_edp_backlight_control(
>+void dce110_edp_backlight_control(
> 		struct dc_link *link,
> 		bool enable)
> {
>@@ -1003,7 +981,7 @@
> 	}
> }
> 
>-void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
>+void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
> {
> 	struct dc *dc;
> 	struct pp_smu_funcs *pp_smu = NULL;
>@@ -1026,24 +1004,13 @@
> 		if (dc->res_pool->pp_smu)
> 			pp_smu = dc->res_pool->pp_smu;
> 
>-		if (option != KEEP_ACQUIRED_RESOURCE ||
>-				!dc->debug.az_endpoint_mute_only)
>-			/*only disalbe az_endpoint if power down or free*/
>-			pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
>-
> 		if (dc_is_dp_signal(pipe_ctx->stream->signal))
> 			pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
> 					pipe_ctx->stream_res.stream_enc);
> 		else
> 			pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
> 					pipe_ctx->stream_res.stream_enc);
>-		/*don't free audio if it is from retrain or internal disable stream*/
>-		if (option == FREE_ACQUIRED_RESOURCE && dc->caps.dynamic_audio == true) {
>-			/*we have to dynamic arbitrate the audio endpoints*/
>-			/*we free the resource, need reset is_audio_acquired*/
>-			update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
>-			pipe_ctx->stream_res.audio = NULL;
>-		}
>+
> 		if (clk_mgr->funcs->enable_pme_wa)
> 			/*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
> 			clk_mgr->funcs->enable_pme_wa(clk_mgr);
>@@ -1056,21 +1023,24 @@
> 	}
> }
> 
>-void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option)
>+void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
> {
> 	struct dc_stream_state *stream = pipe_ctx->stream;
> 	struct dc_link *link = stream->link;
> 	struct dc *dc = pipe_ctx->stream->ctx->dc;
> 
>-	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
>+	if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
> 		pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
> 			pipe_ctx->stream_res.stream_enc);
>+		pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
>+			pipe_ctx->stream_res.stream_enc);
>+	}
> 
> 	if (dc_is_dp_signal(pipe_ctx->stream->signal))
> 		pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
> 			pipe_ctx->stream_res.stream_enc);
> 
>-	dc->hwss.disable_audio_stream(pipe_ctx, option);
>+	dc->hwss.disable_audio_stream(pipe_ctx);
> 
> 	link->link_enc->funcs->connect_dig_be_to_fe(
> 			link->link_enc,
>@@ -1174,27 +1144,27 @@
> 			stream->timing.flags.INTERLACE;
> 
> 	audio_output->crtc_info.refresh_rate =
>-		(stream->timing.pix_clk_100hz*10000)/
>+		(stream->timing.pix_clk_100hz*100)/
> 		(stream->timing.h_total*stream->timing.v_total);
> 
> 	audio_output->crtc_info.color_depth =
> 		stream->timing.display_color_depth;
> 
>-	audio_output->crtc_info.requested_pixel_clock =
>-			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
>+	audio_output->crtc_info.requested_pixel_clock_100Hz =
>+			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
> 
>-	audio_output->crtc_info.calculated_pixel_clock =
>-			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
>+	audio_output->crtc_info.calculated_pixel_clock_100Hz =
>+			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
> 
> /*for HDMI, audio ACR is with deep color ratio factor*/
> 	if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
>-		audio_output->crtc_info.requested_pixel_clock ==
>-				(stream->timing.pix_clk_100hz / 10)) {
>+		audio_output->crtc_info.requested_pixel_clock_100Hz ==
>+				(stream->timing.pix_clk_100hz)) {
> 		if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
>-			audio_output->crtc_info.requested_pixel_clock =
>-					audio_output->crtc_info.requested_pixel_clock/2;
>-			audio_output->crtc_info.calculated_pixel_clock =
>-					pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/20;
>+			audio_output->crtc_info.requested_pixel_clock_100Hz =
>+					audio_output->crtc_info.requested_pixel_clock_100Hz/2;
>+			audio_output->crtc_info.calculated_pixel_clock_100Hz =
>+					pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
> 
> 		}
> 	}
>@@ -1360,7 +1330,7 @@
> 	struct drr_params params = {0};
> 	unsigned int event_triggers = 0;
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>-	struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
>+	struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
> #endif
> 
> 	if (dc->hwss.disable_stream_gating) {
>@@ -1428,7 +1398,7 @@
> 		&stream->bit_depth_params,
> 		&stream->clamping);
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>-	if (odm_pipe) {
>+	while (odm_pipe) {
> 		odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
> 				odm_pipe->stream_res.opp,
> 				COLOR_SPACE_YCBCR601,
>@@ -1439,6 +1409,7 @@
> 				odm_pipe->stream_res.opp,
> 				&stream->bit_depth_params,
> 				&stream->clamping);
>+		odm_pipe = odm_pipe->next_odm_pipe;
> 	}
> #endif
> 
>@@ -1748,7 +1719,8 @@
>  ******************************************************************************/
> 
> static void set_drr(struct pipe_ctx **pipe_ctx,
>-		int num_pipes, int vmin, int vmax)
>+		int num_pipes, unsigned int vmin, unsigned int vmax,
>+		unsigned int vmid, unsigned int vmid_frame_number)
> {
> 	int i = 0;
> 	struct drr_params params = {0};
>@@ -1932,8 +1904,25 @@
> 			/* Disable if new stream is null. O/w, if stream is
> 			 * disabled already, no need to disable again.
> 			 */
>-			if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off)
>-				core_link_disable_stream(pipe_ctx_old, FREE_ACQUIRED_RESOURCE);
>+			if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
>+				core_link_disable_stream(pipe_ctx_old);
>+
>+				/* free acquired resources*/
>+				if (pipe_ctx_old->stream_res.audio) {
>+					/*disable az_endpoint*/
>+					pipe_ctx_old->stream_res.audio->funcs->
>+							az_disable(pipe_ctx_old->stream_res.audio);
>+
>+					/*free audio*/
>+					if (dc->caps.dynamic_audio == true) {
>+						/*we have to dynamic arbitrate the audio endpoints*/
>+						/*we free the resource, need reset is_audio_acquired*/
>+						update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
>+								pipe_ctx_old->stream_res.audio, false);
>+						pipe_ctx_old->stream_res.audio = NULL;
>+					}
>+				}
>+			}
> 
> 			pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
> 			if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
>@@ -2098,7 +2087,7 @@
> 		if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
> 			continue;
> 
>-		if (pipe_ctx->top_pipe)
>+		if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
> 			continue;
> 
> 		status = apply_single_controller_ctx_to_hw(
>@@ -2777,9 +2766,9 @@
> 	.setup_stereo = NULL,
> 	.set_avmute = dce110_set_avmute,
> 	.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
>-	.edp_backlight_control = hwss_edp_backlight_control,
>-	.edp_power_control = hwss_edp_power_control,
>-	.edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
>+	.edp_backlight_control = dce110_edp_backlight_control,
>+	.edp_power_control = dce110_edp_power_control,
>+	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
> 	.set_cursor_position = dce110_set_cursor_position,
> 	.set_cursor_attribute = dce110_set_cursor_attribute
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h	2019-08-31 15:01:11.861736168 -0500
>@@ -42,7 +42,7 @@
> 
> void dce110_enable_stream(struct pipe_ctx *pipe_ctx);
> 
>-void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option);
>+void dce110_disable_stream(struct pipe_ctx *pipe_ctx);
> 
> void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
> 		struct dc_link_settings *link_settings);
>@@ -50,7 +50,7 @@
> void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
> 
> void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
>-void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option);
>+void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
> 
> void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
> 
>@@ -73,15 +73,15 @@
> 
> void dp_receiver_power_ctrl(struct dc_link *link, bool on);
> 
>-void hwss_edp_power_control(
>+void dce110_edp_power_control(
> 		struct dc_link *link,
> 		bool power_up);
> 
>-void hwss_edp_backlight_control(
>+void dce110_edp_backlight_control(
> 	struct dc_link *link,
> 	bool enable);
> 
>-void hwss_edp_wait_for_hpd_ready(
>+void dce110_edp_wait_for_hpd_ready(
> 		struct dc_link *link,
> 		bool power_up);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c	2019-08-31 15:01:11.861736168 -0500
>@@ -229,26 +229,26 @@
> static void program_size_and_rotation(
> 	struct dce_mem_input *mem_input110,
> 	enum dc_rotation_angle rotation,
>-	const union plane_size *plane_size)
>+	const struct plane_size *plane_size)
> {
> 	uint32_t value = 0;
>-	union plane_size local_size = *plane_size;
>+	struct plane_size local_size = *plane_size;
> 
> 	if (rotation == ROTATION_ANGLE_90 ||
> 		rotation == ROTATION_ANGLE_270) {
> 
>-		swap(local_size.video.luma_size.x,
>-		     local_size.video.luma_size.y);
>-		swap(local_size.video.luma_size.width,
>-		     local_size.video.luma_size.height);
>-		swap(local_size.video.chroma_size.x,
>-		     local_size.video.chroma_size.y);
>-		swap(local_size.video.chroma_size.width,
>-		     local_size.video.chroma_size.height);
>+		swap(local_size.surface_size.x,
>+		     local_size.surface_size.y);
>+		swap(local_size.surface_size.width,
>+		     local_size.surface_size.height);
>+		swap(local_size.chroma_size.x,
>+		     local_size.chroma_size.y);
>+		swap(local_size.chroma_size.width,
>+		     local_size.chroma_size.height);
> 	}
> 
> 	value = 0;
>-	set_reg_field_value(value, local_size.video.luma_pitch,
>+	set_reg_field_value(value, local_size.surface_pitch,
> 			UNP_GRPH_PITCH_L, GRPH_PITCH_L);
> 
> 	dm_write_reg(
>@@ -257,7 +257,7 @@
> 		value);
> 
> 	value = 0;
>-	set_reg_field_value(value, local_size.video.chroma_pitch,
>+	set_reg_field_value(value, local_size.chroma_pitch,
> 			UNP_GRPH_PITCH_C, GRPH_PITCH_C);
> 	dm_write_reg(
> 		mem_input110->base.ctx,
>@@ -297,8 +297,8 @@
> 		value);
> 
> 	value = 0;
>-	set_reg_field_value(value, local_size.video.luma_size.x +
>-			local_size.video.luma_size.width,
>+	set_reg_field_value(value, local_size.surface_size.x +
>+			local_size.surface_size.width,
> 			UNP_GRPH_X_END_L, GRPH_X_END_L);
> 	dm_write_reg(
> 		mem_input110->base.ctx,
>@@ -306,8 +306,8 @@
> 		value);
> 
> 	value = 0;
>-	set_reg_field_value(value, local_size.video.chroma_size.x +
>-			local_size.video.chroma_size.width,
>+	set_reg_field_value(value, local_size.chroma_size.x +
>+			local_size.chroma_size.width,
> 			UNP_GRPH_X_END_C, GRPH_X_END_C);
> 	dm_write_reg(
> 		mem_input110->base.ctx,
>@@ -315,8 +315,8 @@
> 		value);
> 
> 	value = 0;
>-	set_reg_field_value(value, local_size.video.luma_size.y +
>-			local_size.video.luma_size.height,
>+	set_reg_field_value(value, local_size.surface_size.y +
>+			local_size.surface_size.height,
> 			UNP_GRPH_Y_END_L, GRPH_Y_END_L);
> 	dm_write_reg(
> 		mem_input110->base.ctx,
>@@ -324,8 +324,8 @@
> 		value);
> 
> 	value = 0;
>-	set_reg_field_value(value, local_size.video.chroma_size.y +
>-			local_size.video.chroma_size.height,
>+	set_reg_field_value(value, local_size.chroma_size.y +
>+			local_size.chroma_size.height,
> 			UNP_GRPH_Y_END_C, GRPH_Y_END_C);
> 	dm_write_reg(
> 		mem_input110->base.ctx,
>@@ -637,7 +637,7 @@
> 	struct mem_input *mem_input,
> 	enum surface_pixel_format format,
> 	union dc_tiling_info *tiling_info,
>-	union plane_size *plane_size,
>+	struct plane_size *plane_size,
> 	enum dc_rotation_angle rotation,
> 	struct dc_plane_dcc_param *dcc,
> 	bool horizotal_mirror)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c	2019-08-31 15:01:11.861736168 -0500
>@@ -331,7 +331,7 @@
> 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
> };
> 
>-static const struct dce_aduio_mask audio_mask = {
>+static const struct dce_audio_mask audio_mask = {
> 		AUD_COMMON_MASK_SH_LIST(_MASK)
> };
> 
>@@ -1274,7 +1274,6 @@
> {
> 	unsigned int i;
> 	struct dc_context *ctx = dc->ctx;
>-	struct dc_firmware_info info;
> 	struct dc_bios *bp;
> 
> 	ctx->dc_bios->regs = &bios_regs;
>@@ -1300,8 +1299,7 @@
> 
> 	bp = ctx->dc_bios;
> 
>-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
>-		info.external_clock_source_frequency_for_dp != 0) {
>+	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
> 		pool->base.dp_clock_source =
> 				dce110_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c	2019-08-31 15:01:11.861736168 -0500
>@@ -337,7 +337,7 @@
> 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
> };
> 
>-static const struct dce_aduio_mask audio_mask = {
>+static const struct dce_audio_mask audio_mask = {
> 		AUD_COMMON_MASK_SH_LIST(_MASK)
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c	2019-08-31 15:01:11.861736168 -0500
>@@ -352,7 +352,7 @@
> 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
> };
> 
>-static const struct dce_aduio_mask audio_mask = {
>+static const struct dce_audio_mask audio_mask = {
> 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c	2019-08-31 15:01:11.861736168 -0500
>@@ -322,7 +322,7 @@
> 		AUD_COMMON_MASK_SH_LIST(__SHIFT)
> };
> 
>-static const struct dce_aduio_mask audio_mask = {
>+static const struct dce_audio_mask audio_mask = {
> 		AUD_COMMON_MASK_SH_LIST(_MASK)
> };
> 
>@@ -876,7 +876,6 @@
> {
> 	unsigned int i;
> 	struct dc_context *ctx = dc->ctx;
>-	struct dc_firmware_info info;
> 	struct dc_bios *bp;
> 
> 	ctx->dc_bios->regs = &bios_regs;
>@@ -902,8 +901,7 @@
> 
> 	bp = ctx->dc_bios;
> 
>-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
>-		info.external_clock_source_frequency_for_dp != 0) {
>+	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
> 		pool->base.dp_clock_source =
> 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> 
>@@ -1075,7 +1073,6 @@
> {
> 	unsigned int i;
> 	struct dc_context *ctx = dc->ctx;
>-	struct dc_firmware_info info;
> 	struct dc_bios *bp;
> 
> 	ctx->dc_bios->regs = &bios_regs;
>@@ -1101,8 +1098,7 @@
> 
> 	bp = ctx->dc_bios;
> 
>-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
>-		info.external_clock_source_frequency_for_dp != 0) {
>+	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
> 		pool->base.dp_clock_source =
> 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> 
>@@ -1274,7 +1270,6 @@
> {
> 	unsigned int i;
> 	struct dc_context *ctx = dc->ctx;
>-	struct dc_firmware_info info;
> 	struct dc_bios *bp;
> 
> 	ctx->dc_bios->regs = &bios_regs;
>@@ -1300,8 +1295,7 @@
> 
> 	bp = ctx->dc_bios;
> 
>-	if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
>-		info.external_clock_source_frequency_for_dp != 0) {
>+	if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
> 		pool->base.dp_clock_source =
> 				dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc.h	2019-08-31 15:01:11.859736168 -0500
>@@ -39,7 +39,7 @@
> #include "inc/hw/dmcu.h"
> #include "dml/display_mode_lib.h"
> 
>-#define DC_VER "3.2.35"
>+#define DC_VER "3.2.48"
> 
> #define MAX_SURFACES 3
> #define MAX_PLANES 6
>@@ -121,6 +121,7 @@
> struct dc_bug_wa {
> 	bool no_connect_phy_config;
> 	bool dedcn20_305_wa;
>+	bool skip_clock_update;
> };
> #endif
> 
>@@ -219,7 +220,7 @@
> 	bool power_down_display_on_boot;
> 	bool edp_not_connected;
> 	bool forced_clocks;
>-
>+	bool multi_mon_pp_mclk_switch;
> };
> 
> enum visual_confirm {
>@@ -252,7 +253,10 @@
> struct dc_clocks {
> 	int dispclk_khz;
> 	int max_supported_dppclk_khz;
>+	int max_supported_dispclk_khz;
> 	int dppclk_khz;
>+	int bw_dppclk_khz; /*a copy of dppclk_khz*/
>+	int bw_dispclk_khz;
> 	int dcfclk_khz;
> 	int socclk_khz;
> 	int dcfclk_deep_sleep_khz;
>@@ -260,6 +264,12 @@
> 	int phyclk_khz;
> 	int dramclk_khz;
> 	bool p_state_change_support;
>+
>+	/*
>+	 * Elements below are not compared for the purposes of
>+	 * optimization required
>+	 */
>+	bool prev_p_state_change_support;
> };
> 
> struct dc_bw_validation_profile {
>@@ -341,6 +351,7 @@
> 	bool disable_pplib_wm_range;
> 	enum wm_report_mode pplib_wm_report_mode;
> 	unsigned int min_disp_clk_khz;
>+	unsigned int min_dpp_clk_khz;
> 	int sr_exit_time_dpm0_ns;
> 	int sr_enter_plus_exit_time_dpm0_ns;
> 	int sr_exit_time_ns;
>@@ -367,6 +378,7 @@
> 	bool scl_reset_length10;
> 	bool hdmi20_disable;
> 	bool skip_detection_link_training;
>+	bool remove_disconnect_edp;
> 	unsigned int force_odm_combine; //bit vector based on otg inst
> 	unsigned int force_fclk_khz;
> 	bool disable_tri_buf;
>@@ -374,10 +386,18 @@
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> 	bool disable_fec;
> #endif
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+	bool disable_48mhz_pwrdwn;
>+#endif
> 	/* This forces a hard min on the DCFCLK requested to SMU/PP
> 	 * watermarks are not affected.
> 	 */
> 	unsigned int force_min_dcfclk_mhz;
>+	bool disable_timing_sync;
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>+	bool cm_in_bypass;
>+#endif
>+	int force_clock_mode;/*every mode change.*/
> };
> 
> struct dc_debug_data {
>@@ -406,6 +426,7 @@
> 	} gart_config;
> 
> 	bool valid;
>+	uint64_t page_table_default_page_addr;
> };
> 
> struct dc_virtual_addr_space_config {
>@@ -597,9 +618,12 @@
> 	TRANSFER_FUNCTION_UNITY,
> 	TRANSFER_FUNCTION_HLG,
> 	TRANSFER_FUNCTION_HLG12,
>-	TRANSFER_FUNCTION_GAMMA22
>+	TRANSFER_FUNCTION_GAMMA22,
>+	TRANSFER_FUNCTION_GAMMA24,
>+	TRANSFER_FUNCTION_GAMMA26
> };
> 
>+
> struct dc_transfer_func {
> 	struct kref refcount;
> 	enum dc_transfer_func_type type;
>@@ -615,12 +639,26 @@
> 
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> 
>+union dc_3dlut_state {
>+	struct {
>+		uint32_t initialized:1;		/*if 3dlut is went through color module for initialization */
>+		uint32_t rmu_idx_valid:1;	/*if mux settings are valid*/
>+		uint32_t rmu_mux_num:3;		/*index of mux to use*/
>+		uint32_t mpc_rmu0_mux:4;	/*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
>+		uint32_t mpc_rmu1_mux:4;
>+		uint32_t mpc_rmu2_mux:4;
>+		uint32_t reserved:15;
>+	} bits;
>+	uint32_t raw;
>+};
>+
> 
> struct dc_3dlut {
> 	struct kref refcount;
> 	struct tetrahedral_params lut_3d;
> 	uint32_t hdr_multiplier;
>-	bool initialized;
>+	bool initialized; /*remove after diag fix*/
>+	union dc_3dlut_state state;
> 	struct dc_context *ctx;
> };
> #endif
>@@ -682,7 +720,7 @@
> 	struct rect dst_rect;
> 	struct rect clip_rect;
> 
>-	union plane_size plane_size;
>+	struct plane_size plane_size;
> 	union dc_tiling_info tiling_info;
> 
> 	struct dc_plane_dcc_param dcc;
>@@ -716,6 +754,7 @@
> 	bool visible;
> 	bool flip_immediate;
> 	bool horizontal_mirror;
>+	int layer_index;
> 
> 	union surface_update_flags update_flags;
> 	/* private to DC core */
>@@ -731,7 +770,7 @@
> };
> 
> struct dc_plane_info {
>-	union plane_size plane_size;
>+	struct plane_size plane_size;
> 	union dc_tiling_info tiling_info;
> 	struct dc_plane_dcc_param dcc;
> 	enum surface_pixel_format format;
>@@ -745,6 +784,7 @@
> 	bool global_alpha;
> 	int  global_alpha_value;
> 	bool input_csc_enabled;
>+	int layer_index;
> };
> 
> struct dc_scaling_info {
>@@ -834,6 +874,9 @@
> 
> void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
> 
>+bool dc_set_generic_gpio_for_stereo(bool enable,
>+		struct gpio_service *gpio_service);
>+
> /*
>  * fast_validate: we return after determining if we can support the new state,
>  * but before we populate the programming info
>@@ -1020,6 +1063,8 @@
> 
> bool dc_is_dmcu_initialized(struct dc *dc);
> 
>+enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
>+void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
> #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
> /*******************************************************************************
>  * DSC Interfaces
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_hw_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_hw_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_hw_types.h	2019-08-31 15:01:11.859736168 -0500
>@@ -115,42 +115,40 @@
> 	int height;
> };
> 
>-union plane_size {
>-	/* Grph or Video will be selected
>-	 * based on format above:
>-	 * Use Video structure if
>-	 * format >= DalPixelFormat_VideoBegin
>-	 * else use Grph structure
>+struct plane_size {
>+	/* Graphic surface pitch in pixels.
>+	 * In LINEAR_GENERAL mode, pitch
>+	 * is 32 pixel aligned.
> 	 */
>-	struct {
>-		struct rect surface_size;
>-		/* Graphic surface pitch in pixels.
>-		 * In LINEAR_GENERAL mode, pitch
>-		 * is 32 pixel aligned.
>-		 */
>-		int surface_pitch;
>-	} grph;
>+	int surface_pitch;
>+	int chroma_pitch;
>+	struct rect surface_size;
>+	struct rect chroma_size;
> 
>-	struct {
>-		struct rect luma_size;
>-		/* Graphic surface pitch in pixels.
>-		 * In LINEAR_GENERAL mode, pitch is
>-		 * 32 pixel aligned.
>-		 */
>-		int luma_pitch;
>+	union {
>+		struct {
>+			struct rect surface_size;
>+			int surface_pitch;
>+		} grph;
> 
>-		struct rect chroma_size;
>-		/* Graphic surface pitch in pixels.
>-		 * In LINEAR_GENERAL mode, pitch is
>-		 * 32 pixel aligned.
>-		 */
>-		int chroma_pitch;
>-	} video;
>+		struct {
>+			struct rect luma_size;
>+			int luma_pitch;
>+			struct rect chroma_size;
>+			int chroma_pitch;
>+		} video;
>+	};
> };
> 
> struct dc_plane_dcc_param {
> 	bool enable;
> 
>+	int meta_pitch;
>+	bool independent_64b_blks;
>+
>+	int meta_pitch_c;
>+	bool independent_64b_blks_c;
>+
> 	union {
> 		struct {
> 			int meta_pitch;
>@@ -482,7 +480,6 @@
> 	 * is_logical_identity indicates the given gamma ramp regardless of type is identity.
> 	 */
> 	bool is_identity;
>-	bool is_logical_identity;
> };
> 
> /* Used by both ipp amd opp functions*/
>@@ -519,7 +516,8 @@
> 		uint32_t INVERT_PIXEL_DATA:1;
> 		uint32_t ZERO_EXPANSION:1;
> 		uint32_t MIN_MAX_INVERT:1;
>-		uint32_t RESERVED:25;
>+		uint32_t ENABLE_CURSOR_DEGAMMA:1;
>+		uint32_t RESERVED:24;
> 	} bits;
> 	uint32_t value;
> };
>@@ -615,6 +613,7 @@
> 	uint32_t h_taps;
> 	uint32_t v_taps_c;
> 	uint32_t h_taps_c;
>+	bool integer_scaling;
> };
> 
> enum dc_timing_standard {
>@@ -758,6 +757,8 @@
> struct dc_crtc_timing_adjust {
> 	uint32_t v_total_min;
> 	uint32_t v_total_max;
>+	uint32_t v_total_mid;
>+	uint32_t v_total_mid_frame_num;
> };
> 
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_link.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_link.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_link.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_link.h	2019-08-31 15:01:11.859736168 -0500
>@@ -83,6 +83,8 @@
> 	bool is_hpd_filter_disabled;
> 	bool dp_ss_off;
> 	bool link_state_valid;
>+	bool aux_access_disabled;
>+	bool sync_lt_in_progress;
> 
> 	/* caps is the same as reported_link_cap. link_traing use
> 	 * reported_link_cap. Will clean up.  TODO
>@@ -92,6 +94,7 @@
> 	struct dc_link_settings cur_link_settings;
> 	struct dc_lane_settings cur_lane_setting;
> 	struct dc_link_settings preferred_link_setting;
>+	struct dc_link_training_overrides preferred_training_settings;
> 
> 	uint8_t ddc_hw_inst;
> 
>@@ -217,11 +220,24 @@
> 	struct dc_link *link,
> 	struct link_training_settings *lt_settings);
> 
>+bool dc_link_dp_perform_link_training_skip_aux(
>+	struct dc_link *link,
>+	const struct dc_link_settings *link_setting);
>+
> enum link_training_result dc_link_dp_perform_link_training(
> 	struct dc_link *link,
> 	const struct dc_link_settings *link_setting,
> 	bool skip_video_pattern);
> 
>+bool dc_link_dp_sync_lt_begin(struct dc_link *link);
>+
>+enum link_training_result dc_link_dp_sync_lt_attempt(
>+	struct dc_link *link,
>+	struct dc_link_settings *link_setting,
>+	struct dc_link_training_overrides *lt_settings);
>+
>+bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down);
>+
> void dc_link_dp_enable_hpd(const struct dc_link *link);
> 
> void dc_link_dp_disable_hpd(const struct dc_link *link);
>@@ -251,6 +267,11 @@
> void dc_link_set_preferred_link_settings(struct dc *dc,
> 					 struct dc_link_settings *link_setting,
> 					 struct dc_link *link);
>+void dc_link_set_preferred_training_settings(struct dc *dc,
>+					struct dc_link_settings *link_setting,
>+					struct dc_link_training_overrides *lt_overrides,
>+					struct dc_link *link,
>+					bool skip_immediate_retrain);
> void dc_link_enable_hpd(const struct dc_link *link);
> void dc_link_disable_hpd(const struct dc_link *link);
> void dc_link_set_test_pattern(struct dc_link *link,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c	2019-08-31 15:01:11.861736168 -0500
>@@ -343,8 +343,8 @@
> 		region_start = -MAX_LOW_POINT;
> 		region_end   = NUMBER_REGIONS - MAX_LOW_POINT;
> 	} else {
>-		/* 10 segments
>-		 * segment is from 2^-10 to 2^0
>+		/* 11 segments
>+		 * segment is from 2^-10 to 2^1
> 		 * There are less than 256 points, for optimization
> 		 */
> 		seg_distr[0] = 3;
>@@ -357,9 +357,10 @@
> 		seg_distr[7] = 4;
> 		seg_distr[8] = 4;
> 		seg_distr[9] = 4;
>+		seg_distr[10] = 1;
> 
> 		region_start = -10;
>-		region_end = 0;
>+		region_end = 1;
> 	}
> 
> 	for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c	2019-08-31 15:01:11.862736169 -0500
>@@ -426,8 +426,9 @@
> 
> void dpp1_set_cursor_attributes(
> 		struct dpp *dpp_base,
>-		enum dc_cursor_color_format color_format)
>+		struct dc_cursor_attributes *cursor_attributes)
> {
>+	enum dc_cursor_color_format color_format = cursor_attributes->color_format;
> 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
> 
> 	REG_UPDATE_2(CURSOR0_CONTROL,
>@@ -456,6 +457,19 @@
> 	int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
> 	uint32_t cur_en = pos->enable ? 1 : 0;
> 
>+	// Cursor width/height and hotspots need to be rotated for offset calculation
>+	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
>+		swap(width, height);
>+		if (param->rotation == ROTATION_ANGLE_90) {
>+			src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
>+			src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
>+		}
>+	} else if (param->rotation == ROTATION_ANGLE_180) {
>+		src_x_offset = pos->x - param->viewport.x;
>+		src_y_offset = pos->y - param->viewport.y;
>+	}
>+
>+
> 	if (src_x_offset >= (int)param->viewport.width)
> 		cur_en = 0;  /* not visible beyond right edge*/
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h	2019-08-31 15:01:11.862736169 -0500
>@@ -1368,7 +1368,7 @@
> 
> void dpp1_set_cursor_attributes(
> 		struct dpp *dpp_base,
>-		enum dc_cursor_color_format color_format);
>+		struct dc_cursor_attributes *cursor_attributes);
> 
> void dpp1_set_cursor_position(
> 		struct dpp *dpp_base,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c	2019-08-31 15:01:11.862736169 -0500
>@@ -104,7 +104,7 @@
> 			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow);
> }
> 
>-bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
>+bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
> {
> 	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
> 	uint32_t enable = 0;
>@@ -945,6 +945,8 @@
> 	.get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,
> 	.wm_read_state = hubbub1_wm_read_state,
> 	.program_watermarks = hubbub1_program_watermarks,
>+	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
>+	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
> };
> 
> void hubbub1_construct(struct hubbub *hubbub,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h	2019-08-31 15:01:11.862736169 -0500
>@@ -119,6 +119,28 @@
> 	uint32_t DCN_VM_AGP_BOT;
> 	uint32_t DCN_VM_AGP_TOP;
> 	uint32_t DCN_VM_AGP_BASE;
>+	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;
>+	uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB;
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;
>+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;
>+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;
>+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;
>+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;
>+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;
>+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;
>+	uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;
>+	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;
>+	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;
>+	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;
>+	uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;
>+	uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
>+	uint32_t DCHVM_CTRL0;
>+	uint32_t DCHVM_MEM_CTRL;
>+	uint32_t DCHVM_CLK_CTRL;
>+	uint32_t DCHVM_RIOMMU_CTRL0;
>+	uint32_t DCHVM_RIOMMU_STAT0;
>+#endif
> };
> 
> /* set field name */
>@@ -196,7 +218,9 @@
> 		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
> 		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
> 		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
>-		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
>+		type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
>+		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\
>+		type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB
> 
> #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \
> 		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\
>@@ -208,15 +232,68 @@
> 		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\
> 		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
> 
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+#define HUBBUB_HVM_REG_FIELD_LIST(type) \
>+		type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\
>+		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\
>+		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B;\
>+		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C;\
>+		type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D;\
>+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A;\
>+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B;\
>+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C;\
>+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D;\
>+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A;\
>+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B;\
>+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C;\
>+		type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D;\
>+		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\
>+		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\
>+		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\
>+		type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\
>+		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;\
>+		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;\
>+		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;\
>+		type DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;\
>+		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;\
>+		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;\
>+		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;\
>+		type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;\
>+		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;\
>+		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;\
>+		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;\
>+		type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;\
>+		type DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD;\
>+		type HOSTVM_INIT_REQ; \
>+		type HVM_GPUVMRET_PWR_REQ_DIS; \
>+		type HVM_GPUVMRET_FORCE_REQ; \
>+		type HVM_GPUVMRET_POWER_STATUS; \
>+		type HVM_DISPCLK_R_GATE_DIS; \
>+		type HVM_DISPCLK_G_GATE_DIS; \
>+		type HVM_DCFCLK_R_GATE_DIS; \
>+		type HVM_DCFCLK_G_GATE_DIS; \
>+		type TR_REQ_REQCLKREQ_MODE; \
>+		type TW_RSP_COMPCLKREQ_MODE; \
>+		type HOSTVM_PREFETCH_REQ; \
>+		type HOSTVM_POWERSTATUS; \
>+		type RIOMMU_ACTIVE; \
>+		type HOSTVM_PREFETCH_DONE
>+#endif
> 
> struct dcn_hubbub_shift {
> 	DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
> 	HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
>+#endif
> };
> 
> struct dcn_hubbub_mask {
> 	DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
> 	HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
>+#endif
> };
> 
> struct dc;
>@@ -247,7 +324,7 @@
> 
> void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow);
> 
>-bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubub);
>+bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub);
> 
> void hubbub1_toggle_watermark_change_req(
> 		struct hubbub *hubbub);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c	2019-08-31 15:01:11.862736169 -0500
>@@ -163,7 +163,7 @@
> void hubp1_program_size(
> 	struct hubp *hubp,
> 	enum surface_pixel_format format,
>-	const union plane_size *plane_size,
>+	const struct plane_size *plane_size,
> 	struct dc_plane_dcc_param *dcc)
> {
> 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
>@@ -173,16 +173,16 @@
> 	 * 444 or 420 luma
> 	 */
> 	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) {
>-		ASSERT(plane_size->video.chroma_pitch != 0);
>+		ASSERT(plane_size->chroma_pitch != 0);
> 		/* Chroma pitch zero can cause system hang! */
> 
>-		pitch = plane_size->video.luma_pitch - 1;
>-		meta_pitch = dcc->video.meta_pitch_l - 1;
>-		pitch_c = plane_size->video.chroma_pitch - 1;
>-		meta_pitch_c = dcc->video.meta_pitch_c - 1;
>+		pitch = plane_size->surface_pitch - 1;
>+		meta_pitch = dcc->meta_pitch - 1;
>+		pitch_c = plane_size->chroma_pitch - 1;
>+		meta_pitch_c = dcc->meta_pitch_c - 1;
> 	} else {
>-		pitch = plane_size->grph.surface_pitch - 1;
>-		meta_pitch = dcc->grph.meta_pitch - 1;
>+		pitch = plane_size->surface_pitch - 1;
>+		meta_pitch = dcc->meta_pitch - 1;
> 		pitch_c = 0;
> 		meta_pitch_c = 0;
> 	}
>@@ -509,7 +509,7 @@
> }
> 
> void hubp1_dcc_control(struct hubp *hubp, bool enable,
>-		bool independent_64b_blks)
>+		enum hubp_ind_block_size independent_64b_blks)
> {
> 	uint32_t dcc_en = enable ? 1 : 0;
> 	uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
>@@ -526,13 +526,13 @@
> 	struct hubp *hubp,
> 	enum surface_pixel_format format,
> 	union dc_tiling_info *tiling_info,
>-	union plane_size *plane_size,
>+	struct plane_size *plane_size,
> 	enum dc_rotation_angle rotation,
> 	struct dc_plane_dcc_param *dcc,
> 	bool horizontal_mirror,
> 	unsigned int compat_level)
> {
>-	hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
>+	hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
> 	hubp1_program_tiling(hubp, tiling_info, format);
> 	hubp1_program_size(hubp, format, plane_size, dcc);
> 	hubp1_program_rotation(hubp, rotation, horizontal_mirror);
>@@ -843,7 +843,7 @@
> 		  PRI_VIEWPORT_Y_START_C, viewport_c->y);
> }
> 
>-void hubp1_read_state(struct hubp *hubp)
>+void hubp1_read_state_common(struct hubp *hubp)
> {
> 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
> 	struct dcn_hubp_state *s = &hubp1->state;
>@@ -859,24 +859,6 @@
> 			PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
> 			MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
> 			CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
>-	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
>-		CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
>-		MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
>-		META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
>-		MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
>-		DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
>-		MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
>-		SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
>-		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
>-	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
>-		CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
>-		MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
>-		META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
>-		MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
>-		DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
>-		MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
>-		SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
>-		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
> 
> 	/* DLG - Per hubp */
> 	REG_GET_2(BLANK_OFFSET_0,
>@@ -1030,8 +1012,38 @@
> 	REG_GET_2(DCN_TTU_QOS_WM,
> 			QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
> 			QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
>+
> }
> 
>+void hubp1_read_state(struct hubp *hubp)
>+{
>+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
>+	struct dcn_hubp_state *s = &hubp1->state;
>+	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
>+
>+	hubp1_read_state_common(hubp);
>+
>+	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
>+		CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
>+		MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
>+		META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
>+		MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
>+		DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
>+		MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
>+		SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
>+		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
>+
>+	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
>+		CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
>+		MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
>+		META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
>+		MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
>+		DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
>+		MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
>+		SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
>+		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
>+
>+}
> enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch)
> {
> 	enum cursor_pitch hw_pitch;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h	2019-08-31 15:01:11.862736169 -0500
>@@ -125,8 +125,6 @@
> 	SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, HUBPREQ, id),\
> 	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, HUBPREQ, id),\
> 	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, HUBPREQ, id),\
>-	SR(DCHUBBUB_SDPIF_FB_BASE),\
>-	SR(DCHUBBUB_SDPIF_FB_OFFSET),\
> 	SRI(CURSOR_SETTINS, HUBPREQ, id), \
> 	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
> 	SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
>@@ -226,14 +224,6 @@
> 	uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB; \
> 	uint32_t DCN_VM_SYSTEM_APERTURE_LOW_ADDR; \
> 	uint32_t DCN_VM_SYSTEM_APERTURE_HIGH_ADDR; \
>-	uint32_t DCHUBBUB_SDPIF_FB_BASE; \
>-	uint32_t DCHUBBUB_SDPIF_FB_OFFSET; \
>-	uint32_t DCN_VM_FB_LOCATION_TOP; \
>-	uint32_t DCN_VM_FB_LOCATION_BASE; \
>-	uint32_t DCN_VM_FB_OFFSET; \
>-	uint32_t DCN_VM_AGP_BASE; \
>-	uint32_t DCN_VM_AGP_BOT; \
>-	uint32_t DCN_VM_AGP_TOP; \
> 	uint32_t CURSOR_SETTINS; \
> 	uint32_t CURSOR_SETTINGS; \
> 	uint32_t CURSOR_SURFACE_ADDRESS_HIGH; \
>@@ -249,7 +239,8 @@
> 	.field_name = reg_name ## __ ## field_name ## post_fix
> 
> /* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */
>-#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\
>+/*1.x, 2.x, and 3.x*/
>+#define HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh)\
> 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
> 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
> 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
>@@ -265,7 +256,6 @@
> 	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
> 	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
> 	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
>-	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
> 	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
> 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
> 	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
>@@ -372,12 +362,17 @@
> 	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
> 	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
> 	HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
>-
>-#define HUBP_MASK_SH_LIST_DCN(mask_sh)\
>-	HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh),\
>+/*2.x and 1.x only*/
>+#define HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)\
>+	HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
>+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
> 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
> 	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
> 
>+/*2.x and 1.x only*/
>+#define HUBP_MASK_SH_LIST_DCN(mask_sh)\
>+	HUBP_MASK_SH_LIST_DCN_COMMON(mask_sh)
>+
> /* Mask/shift struct generation macro for ASICs with VM */
> #define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\
> 	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
>@@ -412,8 +407,6 @@
> 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mask_sh),\
> 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mask_sh),\
> 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mask_sh),\
>-	HUBP_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh),\
>-	HUBP_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh),\
> 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
> 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
> 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh),\
>@@ -434,7 +427,7 @@
> 	HUBP_SF(CURSOR0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
> 	HUBP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
> 
>-#define DCN_HUBP_REG_FIELD_LIST(type) \
>+#define DCN_HUBP_REG_FIELD_BASE_LIST(type) \
> 	type HUBP_BLANK_EN;\
> 	type HUBP_DISABLE;\
> 	type HUBP_TTU_DISABLE;\
>@@ -459,7 +452,6 @@
> 	type ROTATION_ANGLE;\
> 	type H_MIRROR_EN;\
> 	type SURFACE_PIXEL_FORMAT;\
>-	type ALPHA_PLANE_EN;\
> 	type SURFACE_FLIP_TYPE;\
> 	type SURFACE_FLIP_MODE_FOR_STEREOSYNC;\
> 	type SURFACE_FLIP_IN_STEREOSYNC;\
>@@ -589,18 +581,6 @@
> 	type MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB;\
> 	type MC_VM_SYSTEM_APERTURE_LOW_ADDR;\
> 	type MC_VM_SYSTEM_APERTURE_HIGH_ADDR;\
>-	type SDPIF_FB_TOP;\
>-	type SDPIF_FB_BASE;\
>-	type SDPIF_FB_OFFSET;\
>-	type SDPIF_AGP_BASE;\
>-	type SDPIF_AGP_BOT;\
>-	type SDPIF_AGP_TOP;\
>-	type FB_TOP;\
>-	type FB_BASE;\
>-	type FB_OFFSET;\
>-	type AGP_BASE;\
>-	type AGP_BOT;\
>-	type AGP_TOP;\
> 	type DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\
> 	type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\
> 	type DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\
>@@ -632,6 +612,10 @@
> 	type CURSOR_DST_X_OFFSET; \
> 	type OUTPUT_FP
> 
>+#define DCN_HUBP_REG_FIELD_LIST(type) \
>+	DCN_HUBP_REG_FIELD_BASE_LIST(type);\
>+	type ALPHA_PLANE_EN
>+
> struct dcn_mi_registers {
> 	HUBP_COMMON_REG_VARIABLE_LIST;
> };
>@@ -677,7 +661,7 @@
> 	struct hubp *hubp,
> 	enum surface_pixel_format format,
> 	union dc_tiling_info *tiling_info,
>-	union plane_size *plane_size,
>+	struct plane_size *plane_size,
> 	enum dc_rotation_angle rotation,
> 	struct dc_plane_dcc_param *dcc,
> 	bool horizontal_mirror,
>@@ -699,7 +683,7 @@
> void hubp1_program_size(
> 	struct hubp *hubp,
> 	enum surface_pixel_format format,
>-	const union plane_size *plane_size,
>+	const struct plane_size *plane_size,
> 	struct dc_plane_dcc_param *dcc);
> 
> void hubp1_program_rotation(
>@@ -714,7 +698,7 @@
> 
> void hubp1_dcc_control(struct hubp *hubp,
> 		bool enable,
>-		bool independent_64b_blks);
>+		enum hubp_ind_block_size independent_64b_blks);
> 
> #ifdef CONFIG_DRM_AMD_DC_DCN2_0
> bool hubp1_program_surface_flip_and_addr(
>@@ -760,5 +744,6 @@
> 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
> 
> void hubp1_init(struct hubp *hubp);
>+void hubp1_read_state_common(struct hubp *hubp);
> 
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c	2019-08-31 15:01:11.863736169 -0500
>@@ -438,7 +438,7 @@
> 	return false;
> }
> 
>-static void enable_power_gating_plane(
>+static void dcn10_enable_power_gating_plane(
> 	struct dce_hwseq *hws,
> 	bool enable)
> {
>@@ -460,7 +460,7 @@
> 	REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
> }
> 
>-static void disable_vga(
>+static void dcn10_disable_vga(
> 	struct dce_hwseq *hws)
> {
> 	unsigned int in_vga1_mode = 0;
>@@ -493,7 +493,7 @@
> 	REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
> }
> 
>-static void dpp_pg_control(
>+static void dcn10_dpp_pg_control(
> 		struct dce_hwseq *hws,
> 		unsigned int dpp_inst,
> 		bool power_on)
>@@ -545,7 +545,7 @@
> 	}
> }
> 
>-static void hubp_pg_control(
>+static void dcn10_hubp_pg_control(
> 		struct dce_hwseq *hws,
> 		unsigned int hubp_inst,
> 		bool power_on)
>@@ -605,8 +605,8 @@
> 	if (REG(DC_IP_REQUEST_CNTL)) {
> 		REG_SET(DC_IP_REQUEST_CNTL, 0,
> 				IP_REQUEST_EN, 1);
>-		dpp_pg_control(hws, plane_id, true);
>-		hubp_pg_control(hws, plane_id, true);
>+		hws->ctx->dc->hwss.dpp_pg_control(hws, plane_id, true);
>+		hws->ctx->dc->hwss.hubp_pg_control(hws, plane_id, true);
> 		REG_SET(DC_IP_REQUEST_CNTL, 0,
> 				IP_REQUEST_EN, 0);
> 		DC_LOG_DEBUG(
>@@ -627,7 +627,7 @@
> 	REG_SET(DC_IP_REQUEST_CNTL, 0,
> 			IP_REQUEST_EN, 1);
> 
>-	hubp_pg_control(hws, 0, false);
>+	dc->hwss.hubp_pg_control(hws, 0, false);
> 	REG_SET(DC_IP_REQUEST_CNTL, 0,
> 			IP_REQUEST_EN, 0);
> 
>@@ -656,7 +656,7 @@
> 	REG_SET(DC_IP_REQUEST_CNTL, 0,
> 			IP_REQUEST_EN, 1);
> 
>-	hubp_pg_control(hws, 0, true);
>+	dc->hwss.hubp_pg_control(hws, 0, true);
> 	REG_SET(DC_IP_REQUEST_CNTL, 0,
> 			IP_REQUEST_EN, 0);
> 
>@@ -664,10 +664,23 @@
> 	hws->wa_state.DEGVIDCN10_253_applied = true;
> }
> 
>-static void bios_golden_init(struct dc *dc)
>+static void dcn10_bios_golden_init(struct dc *dc)
> {
> 	struct dc_bios *bp = dc->ctx->dc_bios;
> 	int i;
>+	bool allow_self_fresh_force_enable = true;
>+
>+	if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
>+		allow_self_fresh_force_enable =
>+				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
>+
>+
>+	/* WA for making DF sleep when idle after resume from S0i3.
>+	 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
>+	 * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
>+	 * before calling command table and it changed to 1 after,
>+	 * it should be set back to 0.
>+	 */
> 
> 	/* initialize dcn global */
> 	bp->funcs->enable_disp_power_gating(bp,
>@@ -678,6 +691,12 @@
> 		bp->funcs->enable_disp_power_gating(bp,
> 				CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
> 	}
>+
>+	if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
>+		if (allow_self_fresh_force_enable == false &&
>+				dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub))
>+			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, true);
>+
> }
> 
> static void false_optc_underflow_wa(
>@@ -702,7 +721,8 @@
> 		dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
> 	}
> 
>-	tg->funcs->set_blank_data_double_buffer(tg, true);
>+	if (tg->funcs->set_blank_data_double_buffer)
>+		tg->funcs->set_blank_data_double_buffer(tg, true);
> 
> 	if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
> 		tg->funcs->clear_optc_underflow(tg);
>@@ -808,11 +828,23 @@
> 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
> 		/* DPMS may already disable */
> 		if (!pipe_ctx->stream->dpms_off)
>-			core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
>-		else if (pipe_ctx->stream_res.audio) {
>-			dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
>+			core_link_disable_stream(pipe_ctx);
>+		else if (pipe_ctx->stream_res.audio)
>+			dc->hwss.disable_audio_stream(pipe_ctx);
>+
>+		if (pipe_ctx->stream_res.audio) {
>+			/*disable az_endpoint*/
>+			pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
>+
>+			/*free audio*/
>+			if (dc->caps.dynamic_audio == true) {
>+				/*we have to dynamic arbitrate the audio endpoints*/
>+				/*we free the resource, need reset is_audio_acquired*/
>+				update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
>+						pipe_ctx->stream_res.audio, false);
>+				pipe_ctx->stream_res.audio = NULL;
>+			}
> 		}
>-
> 	}
> 
> 	/* by upper caller loop, parent pipe: pipe0, will be reset last.
>@@ -823,6 +855,9 @@
> 		pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
> 
> 		pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
>+		if (pipe_ctx->stream_res.tg->funcs->set_drr)
>+			pipe_ctx->stream_res.tg->funcs->set_drr(
>+					pipe_ctx->stream_res.tg, NULL);
> 	}
> 
> 	for (i = 0; i < dc->res_pool->pipe_count; i++)
>@@ -968,7 +1003,7 @@
> 		dcn10_verify_allow_pstate_change_high(dc);
> }
> 
>-static void plane_atomic_power_down(struct dc *dc,
>+static void dcn10_plane_atomic_power_down(struct dc *dc,
> 		struct dpp *dpp,
> 		struct hubp *hubp)
> {
>@@ -978,8 +1013,8 @@
> 	if (REG(DC_IP_REQUEST_CNTL)) {
> 		REG_SET(DC_IP_REQUEST_CNTL, 0,
> 				IP_REQUEST_EN, 1);
>-		dpp_pg_control(hws, dpp->inst, false);
>-		hubp_pg_control(hws, hubp->inst, false);
>+		dc->hwss.dpp_pg_control(hws, dpp->inst, false);
>+		dc->hwss.hubp_pg_control(hws, hubp->inst, false);
> 		dpp->funcs->dpp_reset(dpp);
> 		REG_SET(DC_IP_REQUEST_CNTL, 0,
> 				IP_REQUEST_EN, 0);
>@@ -991,7 +1026,7 @@
> /* disable HW used by plane.
>  * note:  cannot disable until disconnect is complete
>  */
>-static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
>+static void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
> {
> 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
> 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
>@@ -1011,7 +1046,7 @@
> 	hubp->power_gated = true;
> 	dc->optimized_required = false; /* We're powering off, no need to optimize */
> 
>-	plane_atomic_power_down(dc,
>+	dc->hwss.plane_atomic_power_down(dc,
> 			pipe_ctx->plane_res.dpp,
> 			pipe_ctx->plane_res.hubp);
> 
>@@ -1030,7 +1065,7 @@
> 	if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
> 		return;
> 
>-	plane_atomic_disable(dc, pipe_ctx);
>+	dc->hwss.plane_atomic_disable(dc, pipe_ctx);
> 
> 	apply_DEGVIDCN10_253_wa(dc);
> 
>@@ -1065,15 +1100,27 @@
> 		 * command table.
> 		 */
> 		if (tg->funcs->is_tg_enabled(tg)) {
>-			tg->funcs->lock(tg);
>-			tg->funcs->set_blank(tg, true);
>-			hwss_wait_for_blank_complete(tg);
>+			if (dc->hwss.init_blank != NULL) {
>+				dc->hwss.init_blank(dc, tg);
>+				tg->funcs->lock(tg);
>+			} else {
>+				tg->funcs->lock(tg);
>+				tg->funcs->set_blank(tg, true);
>+				hwss_wait_for_blank_complete(tg);
>+			}
> 		}
> 	}
> 
>-	/* Cannot reset the MPC mux if seamless boot */
>-	if (!can_apply_seamless_boot)
>-		dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
>+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
>+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
>+
>+		/* Cannot reset the MPC mux if seamless boot */
>+		if (pipe_ctx->stream != NULL && can_apply_seamless_boot)
>+			continue;
>+
>+		dc->res_pool->mpc->funcs->mpc_init_single_inst(
>+				dc->res_pool->mpc, i);
>+	}
> 
> 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
> 		struct timing_generator *tg = dc->res_pool->timing_generators[i];
>@@ -1111,12 +1158,12 @@
> 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
> 		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
> 
>-		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
>+		dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
> 
> 		if (tg->funcs->is_tg_enabled(tg))
> 			tg->funcs->unlock(tg);
> 
>-		dcn10_disable_plane(dc, pipe_ctx);
>+		dc->hwss.disable_plane(dc, pipe_ctx);
> 
> 		pipe_ctx->stream_res.tg = NULL;
> 		pipe_ctx->plane_res.hubp = NULL;
>@@ -1132,8 +1179,17 @@
> 	struct dmcu *dmcu = dc->res_pool->dmcu;
> 	struct dce_hwseq *hws = dc->hwseq;
> 	struct dc_bios *dcb = dc->ctx->dc_bios;
>+	struct resource_pool *res_pool = dc->res_pool;
>+
>+	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
>+		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
>+
>+	// Initialize the dccg
>+	if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
>+		dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);
> 
> 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
>+
> 		REG_WRITE(REFCLK_CNTL, 0);
> 		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
> 		REG_WRITE(DIO_MEM_PWR_CTRL, 0);
>@@ -1147,31 +1203,40 @@
> 			REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
> 		}
> 
>-		enable_power_gating_plane(dc->hwseq, true);
>+		//Enable ability to power gate / don't force power on permanently
>+		dc->hwss.enable_power_gating_plane(hws, true);
> 
>-		/* end of FPGA. Below if real ASIC */
> 		return;
> 	}
> 
>-	if (!dcb->funcs->is_accelerated_mode(dcb)) {
>-		bool allow_self_fresh_force_enable =
>-			hububu1_is_allow_self_refresh_enabled(
>-						dc->res_pool->hubbub);
>+	if (!dcb->funcs->is_accelerated_mode(dcb))
>+		dc->hwss.disable_vga(dc->hwseq);
> 
>-		bios_golden_init(dc);
>+	dc->hwss.bios_golden_init(dc);
>+	if (dc->ctx->dc_bios->fw_info_valid) {
>+		res_pool->ref_clocks.xtalin_clock_inKhz =
>+				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
> 
>-		/* WA for making DF sleep when idle after resume from S0i3.
>-		 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
>-		 * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
>-		 * before calling command table and it changed to 1 after,
>-		 * it should be set back to 0.
>-		 */
>-		if (allow_self_fresh_force_enable == false &&
>-				hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
>-			hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, true);
>+		if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
>+			if (res_pool->dccg && res_pool->hubbub) {
> 
>-		disable_vga(dc->hwseq);
>-	}
>+				(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
>+						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
>+						&res_pool->ref_clocks.dccg_ref_clock_inKhz);
>+
>+				(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
>+						res_pool->ref_clocks.dccg_ref_clock_inKhz,
>+						&res_pool->ref_clocks.dchub_ref_clock_inKhz);
>+			} else {
>+				// Not all ASICs have DCCG sw component
>+				res_pool->ref_clocks.dccg_ref_clock_inKhz =
>+						res_pool->ref_clocks.xtalin_clock_inKhz;
>+				res_pool->ref_clocks.dchub_ref_clock_inKhz =
>+						res_pool->ref_clocks.xtalin_clock_inKhz;
>+			}
>+		}
>+	} else
>+		ASSERT_CRITICAL(false);
> 
> 	for (i = 0; i < dc->link_count; i++) {
> 		/* Power up AND update implementation according to the
>@@ -1188,6 +1253,13 @@
> 			link->link_status.link_active = true;
> 	}
> 
>+	/* Power gate DSCs */
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
>+		if (dc->hwss.dsc_pg_control != NULL)
>+			dc->hwss.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
>+#endif
>+
> 	/* If taking control over from VBIOS, we may want to optimize our first
> 	 * mode set, so we need to skip powering down pipes until we know which
> 	 * pipes we want to use.
>@@ -1198,8 +1270,8 @@
> 		dc->hwss.init_pipes(dc, dc->current_state);
> 	}
> 
>-	for (i = 0; i < dc->res_pool->audio_count; i++) {
>-		struct audio *audio = dc->res_pool->audios[i];
>+	for (i = 0; i < res_pool->audio_count; i++) {
>+		struct audio *audio = res_pool->audios[i];
> 
> 		audio->funcs->hw_init(audio);
> 	}
>@@ -1227,9 +1299,7 @@
> 		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
> 	}
> 
>-	enable_power_gating_plane(dc->hwseq, true);
>-
>-	memset(&dc->clk_mgr->clks, 0, sizeof(dc->clk_mgr->clks));
>+	dc->hwss.enable_power_gating_plane(dc->hwseq, true);
> }
> 
> static void dcn10_reset_hw_ctx_wrap(
>@@ -1366,6 +1436,34 @@
> 	return result;
> }
> 
>+#define MAX_NUM_HW_POINTS 0x200
>+
>+static void log_tf(struct dc_context *ctx,
>+				struct dc_transfer_func *tf, uint32_t hw_points_num)
>+{
>+	// DC_LOG_GAMMA is default logging of all hw points
>+	// DC_LOG_ALL_GAMMA logs all points, not only hw points
>+	// DC_LOG_ALL_TF_POINTS logs all channels of the tf
>+	int i = 0;
>+
>+	DC_LOGGER_INIT(ctx->logger);
>+	DC_LOG_GAMMA("Gamma Correction TF");
>+	DC_LOG_ALL_GAMMA("Logging all tf points...");
>+	DC_LOG_ALL_TF_CHANNELS("Logging all channels...");
>+
>+	for (i = 0; i < hw_points_num; i++) {
>+		DC_LOG_GAMMA("R\t%d\t%llu\n", i, tf->tf_pts.red[i].value);
>+		DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu\n", i, tf->tf_pts.green[i].value);
>+		DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu\n", i, tf->tf_pts.blue[i].value);
>+	}
>+
>+	for (i = hw_points_num; i < MAX_NUM_HW_POINTS; i++) {
>+		DC_LOG_ALL_GAMMA("R\t%d\t%llu\n", i, tf->tf_pts.red[i].value);
>+		DC_LOG_ALL_TF_CHANNELS("G\t%d\t%llu\n", i, tf->tf_pts.green[i].value);
>+		DC_LOG_ALL_TF_CHANNELS("B\t%d\t%llu\n", i, tf->tf_pts.blue[i].value);
>+	}
>+}
>+
> static bool
> dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
> 			       const struct dc_stream_state *stream)
>@@ -1394,6 +1492,13 @@
> 	} else
> 		dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
> 
>+	if (stream != NULL && stream->ctx != NULL &&
>+			stream->out_transfer_func != NULL) {
>+		log_tf(stream->ctx,
>+				stream->out_transfer_func,
>+				dpp->regamma_params.hw_points_num);
>+	}
>+
> 	return true;
> }
> 
>@@ -1786,7 +1891,7 @@
> 	}
> }
> 
>-static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
>+static void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
> {
> 	int i = 0;
> 	struct dpp_grph_csc_adjustment adjust;
>@@ -1804,6 +1909,36 @@
> 	pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
> }
> 
>+
>+static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace)
>+{
>+	if (pipe_ctx->plane_state && pipe_ctx->plane_state->layer_index > 0 && is_rgb_cspace(colorspace)) {
>+		if (pipe_ctx->top_pipe) {
>+			struct pipe_ctx *top = pipe_ctx->top_pipe;
>+
>+			while (top->top_pipe)
>+				top = top->top_pipe; // Traverse to top pipe_ctx
>+			if (top->plane_state && top->plane_state->layer_index == 0)
>+				return true; // Front MPO plane not hidden
>+		}
>+	}
>+	return false;
>+}
>+
>+static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint16_t *matrix)
>+{
>+	// Override rear plane RGB bias to fix MPO brightness
>+	uint16_t rgb_bias = matrix[3];
>+
>+	matrix[3] = 0;
>+	matrix[7] = 0;
>+	matrix[11] = 0;
>+	pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
>+	matrix[3] = rgb_bias;
>+	matrix[7] = rgb_bias;
>+	matrix[11] = rgb_bias;
>+}
>+
> static void dcn10_program_output_csc(struct dc *dc,
> 		struct pipe_ctx *pipe_ctx,
> 		enum dc_color_space colorspace,
>@@ -1811,8 +1946,25 @@
> 		int opp_id)
> {
> 	if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
>-		if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
>-			pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
>+		if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {
>+
>+			/* MPO is broken with RGB colorspaces when OCSC matrix
>+			 * brightness offset >= 0 on DCN1 due to OCSC before MPC
>+			 * Blending adds offsets from front + rear to rear plane
>+			 *
>+			 * Fix is to set RGB bias to 0 on rear plane, top plane
>+			 * black value pixels add offset instead of rear + front
>+			 */
>+
>+			int16_t rgb_bias = matrix[3];
>+			// matrix[3/7/11] are all the same offset value
>+
>+			if (rgb_bias > 0 && dcn10_is_rear_mpo_fix_required(pipe_ctx, colorspace)) {
>+				dcn10_set_csc_adjustment_rgb_mpo_fix(pipe_ctx, matrix);
>+			} else {
>+				pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
>+			}
>+		}
> 	} else {
> 		if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
> 			pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
>@@ -2132,7 +2284,7 @@
> 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
> 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
> 	struct dc_plane_state *plane_state = pipe_ctx->plane_state;
>-	union plane_size size = plane_state->plane_size;
>+	struct plane_size size = plane_state->plane_size;
> 	unsigned int compat_level = 0;
> 
> 	/* depends on DML calculation, DPP clock value may change dynamically */
>@@ -2152,7 +2304,8 @@
> 			dc->res_pool->dccg->funcs->update_dpp_dto(
> 					dc->res_pool->dccg,
> 					dpp->inst,
>-					pipe_ctx->plane_res.bw.dppclk_khz);
>+					pipe_ctx->plane_res.bw.dppclk_khz,
>+					false);
> 		else
> 			dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
> 						dc->clk_mgr->clks.dispclk_khz / 2 :
>@@ -2178,7 +2331,7 @@
> 			&pipe_ctx->ttu_regs);
> 	}
> 
>-	size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
>+	size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
> 
> 	if (plane_state->update_flags.bits.full_update ||
> 		plane_state->update_flags.bits.bpp_change)
>@@ -2216,7 +2369,7 @@
> 
> 	if (plane_state->update_flags.bits.full_update) {
> 		/*gamut remap*/
>-		program_gamut_remap(pipe_ctx);
>+		dc->hwss.program_gamut_remap(pipe_ctx);
> 
> 		dc->hwss.program_output_csc(dc,
> 				pipe_ctx,
>@@ -2388,7 +2541,7 @@
> 		if (pipe_ctx->stream != stream)
> 			continue;
> 
>-		if (!pipe_ctx->top_pipe)
>+		if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
> 			return pipe_ctx;
> 	}
> 	return NULL;
>@@ -2453,7 +2606,7 @@
> 			if (old_pipe_ctx->stream_res.tg == tg &&
> 			    old_pipe_ctx->plane_res.hubp &&
> 			    old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
>-				dcn10_disable_plane(dc, old_pipe_ctx);
>+				dc->hwss.disable_plane(dc, old_pipe_ctx);
> 		}
> 
> 		if ((!pipe_ctx->plane_state ||
>@@ -2501,7 +2654,7 @@
> 
> 	for (i = 0; i < dc->res_pool->pipe_count; i++)
> 		if (removed_pipe[i])
>-			dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
>+			dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
> 
> 	for (i = 0; i < dc->res_pool->pipe_count; i++)
> 		if (removed_pipe[i]) {
>@@ -2593,8 +2746,9 @@
> 		dcn10_verify_allow_pstate_change_high(dc);
> }
> 
>-static void set_drr(struct pipe_ctx **pipe_ctx,
>-		int num_pipes, int vmin, int vmax)
>+static void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
>+		int num_pipes, unsigned int vmin, unsigned int vmax,
>+		unsigned int vmid, unsigned int vmid_frame_number)
> {
> 	int i = 0;
> 	struct drr_params params = {0};
>@@ -2603,6 +2757,8 @@
> 
> 	params.vertical_total_max = vmax;
> 	params.vertical_total_min = vmin;
>+	params.vertical_total_mid = vmid;
>+	params.vertical_total_mid_frame_num = vmid_frame_number;
> 
> 	/* TODO: If multiple pipes are to be supported, you need
> 	 * some GSL stuff. Static screen triggers may be programmed differently
>@@ -2618,7 +2774,7 @@
> 	}
> }
> 
>-static void get_position(struct pipe_ctx **pipe_ctx,
>+static void dcn10_get_position(struct pipe_ctx **pipe_ctx,
> 		int num_pipes,
> 		struct crtc_position *position)
> {
>@@ -2630,7 +2786,7 @@
> 		pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
> }
> 
>-static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
>+static void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
> 		int num_pipes, const struct dc_static_screen_events *events)
> {
> 	unsigned int i;
>@@ -2692,6 +2848,13 @@
> 
> 	dcn10_config_stereo_parameters(stream, &flags);
> 
>+	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
>+		if (!dc_set_generic_gpio_for_stereo(true, dc->ctx->gpio_service))
>+			dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
>+	} else {
>+		dc_set_generic_gpio_for_stereo(false, dc->ctx->gpio_service);
>+	}
>+
> 	pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
> 		pipe_ctx->stream_res.opp,
> 		flags.PROGRAM_STEREO == 1 ? true:false,
>@@ -2782,14 +2945,10 @@
> 
> static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
> {
>-	if (hws->ctx->dc->res_pool->hubbub != NULL) {
>-		struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];
>+	struct hubbub *hubbub = hws->ctx->dc->res_pool->hubbub;
> 
>-		if (hubp->funcs->hubp_update_dchub)
>-			hubp->funcs->hubp_update_dchub(hubp, dh_data);
>-		else
>-			hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
>-	}
>+	/* In DCN, this programming sequence is owned by the hubbub */
>+	hubbub->funcs->update_dchub(hubbub, dh_data);
> }
> 
> static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
>@@ -2820,6 +2979,40 @@
> 			== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
> 		pos_cpy.enable = false;
> 
>+	// Swap axis and mirror horizontally
>+	if (param.rotation == ROTATION_ANGLE_90) {
>+		uint32_t temp_x = pos_cpy.x;
>+		pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -
>+				(pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x;
>+		pos_cpy.y = temp_x;
>+	}
>+	// Swap axis and mirror vertically
>+	else if (param.rotation == ROTATION_ANGLE_270) {
>+		uint32_t temp_y = pos_cpy.y;
>+		if (pos_cpy.x >  pipe_ctx->plane_res.scl_data.viewport.height) {
>+			pos_cpy.x = pos_cpy.x - pipe_ctx->plane_res.scl_data.viewport.height;
>+			pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
>+		} else {
>+			pos_cpy.y = 2 * pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
>+		}
>+		pos_cpy.x = temp_y;
>+	}
>+	// Mirror horizontally and vertically
>+	else if (param.rotation == ROTATION_ANGLE_180) {
>+		if (pos_cpy.x >= pipe_ctx->plane_res.scl_data.viewport.width + pipe_ctx->plane_res.scl_data.viewport.x) {
>+			pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.width
>+					- pos_cpy.x + 2 * pipe_ctx->plane_res.scl_data.viewport.x;
>+		} else {
>+			uint32_t temp_x = pos_cpy.x;
>+			pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.x - pos_cpy.x;
>+			if (temp_x >= pipe_ctx->plane_res.scl_data.viewport.x + (int)hubp->curs_attr.width
>+					|| pos_cpy.x <= (int)hubp->curs_attr.width + pipe_ctx->plane_state->src_rect.x) {
>+				pos_cpy.x = temp_x + pipe_ctx->plane_res.scl_data.viewport.width;
>+			}
>+		}
>+		pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
>+	}
>+
> 	hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
> 	dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
> }
>@@ -2831,7 +3024,7 @@
> 	pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
> 			pipe_ctx->plane_res.hubp, attributes);
> 	pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
>-		pipe_ctx->plane_res.dpp, attributes->color_format);
>+		pipe_ctx->plane_res.dpp, attributes);
> }
> 
> static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
>@@ -3062,9 +3255,59 @@
> 				sdp_message_size);
> 	}
> }
>+static enum dc_status dcn10_set_clock(struct dc *dc,
>+			enum dc_clock_type clock_type,
>+			uint32_t clk_khz,
>+			uint32_t stepping)
>+{
>+	struct dc_state *context = dc->current_state;
>+	struct dc_clock_config clock_cfg = {0};
>+	struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;
>+
>+	if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
>+				dc->clk_mgr->funcs->get_clock(dc->clk_mgr,
>+						context, clock_type, &clock_cfg);
>+
>+	if (!dc->clk_mgr->funcs->get_clock)
>+		return DC_FAIL_UNSUPPORTED_1;
>+
>+	if (clk_khz > clock_cfg.max_clock_khz)
>+		return DC_FAIL_CLK_EXCEED_MAX;
>+
>+	if (clk_khz < clock_cfg.min_clock_khz)
>+		return DC_FAIL_CLK_BELOW_MIN;
>+
>+	if (clk_khz < clock_cfg.bw_requirequired_clock_khz)
>+		return DC_FAIL_CLK_BELOW_CFG_REQUIRED;
>+
>+	/*update internal request clock for update clock use*/
>+	if (clock_type == DC_CLOCK_TYPE_DISPCLK)
>+		current_clocks->dispclk_khz = clk_khz;
>+	else if (clock_type == DC_CLOCK_TYPE_DPPCLK)
>+		current_clocks->dppclk_khz = clk_khz;
>+	else
>+		return DC_ERROR_UNEXPECTED;
>+
>+	if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks)
>+				dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,
>+				context, true);
>+	return DC_OK;
>+
>+}
>+
>+static void dcn10_get_clock(struct dc *dc,
>+			enum dc_clock_type clock_type,
>+			struct dc_clock_config *clock_cfg)
>+{
>+	struct dc_state *context = dc->current_state;
>+
>+	if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
>+				dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg);
>+
>+}
> 
> static const struct hw_sequencer_funcs dcn10_funcs = {
>-	.program_gamut_remap = program_gamut_remap,
>+	.program_gamut_remap = dcn10_program_gamut_remap,
> 	.init_hw = dcn10_init_hw,
> 	.init_pipes = dcn10_init_pipes,
> 	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
>@@ -3097,18 +3340,18 @@
> 	.optimize_bandwidth = dcn10_optimize_bandwidth,
> 	.reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
> 	.enable_stream_timing = dcn10_enable_stream_timing,
>-	.set_drr = set_drr,
>-	.get_position = get_position,
>-	.set_static_screen_control = set_static_screen_control,
>+	.set_drr = dcn10_set_drr,
>+	.get_position = dcn10_get_position,
>+	.set_static_screen_control = dcn10_set_static_screen_control,
> 	.setup_stereo = dcn10_setup_stereo,
> 	.set_avmute = dce110_set_avmute,
> 	.log_hw_state = dcn10_log_hw_state,
> 	.get_hw_state = dcn10_get_hw_state,
> 	.clear_status_bits = dcn10_clear_status_bits,
> 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
>-	.edp_backlight_control = hwss_edp_backlight_control,
>-	.edp_power_control = hwss_edp_power_control,
>-	.edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
>+	.edp_backlight_control = dce110_edp_backlight_control,
>+	.edp_power_control = dce110_edp_power_control,
>+	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
> 	.set_cursor_position = dcn10_set_cursor_position,
> 	.set_cursor_attribute = dcn10_set_cursor_attribute,
> 	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
>@@ -3116,7 +3359,18 @@
> 	.enable_stream_gating = NULL,
> 	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
> 	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
>-	.did_underflow_occur = dcn10_did_underflow_occur
>+	.set_clock = dcn10_set_clock,
>+	.get_clock = dcn10_get_clock,
>+	.did_underflow_occur = dcn10_did_underflow_occur,
>+	.init_blank = NULL,
>+	.disable_vga = dcn10_disable_vga,
>+	.bios_golden_init = dcn10_bios_golden_init,
>+	.plane_atomic_disable = dcn10_plane_atomic_disable,
>+	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
>+	.enable_power_gating_plane = dcn10_enable_power_gating_plane,
>+	.dpp_pg_control = dcn10_dpp_pg_control,
>+	.hubp_pg_control = dcn10_hubp_pg_control,
>+	.dsc_pg_control = NULL,
> };
> 
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c	2019-08-31 15:01:11.863736169 -0500
>@@ -45,7 +45,7 @@
> #include "dcn10_cm_common.h"
> #include "clk_mgr.h"
> 
>-static unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...)
>+unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...)
> {
> 	unsigned int ret_vsnprintf;
> 	unsigned int chars_printed;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c	2019-08-31 15:01:11.863736169 -0500
>@@ -89,6 +89,7 @@
> 	.disable_hpd = dcn10_link_encoder_disable_hpd,
> 	.is_dig_enabled = dcn10_is_dig_enabled,
> 	.get_dig_frontend = dcn10_get_dig_frontend,
>+	.get_dig_mode = dcn10_get_dig_mode,
> 	.destroy = dcn10_link_encoder_destroy
> };
> 
>@@ -446,6 +447,46 @@
> 	}
> }
> 
>+unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
>+{
>+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
>+	int32_t value;
>+	enum engine_id result;
>+
>+	REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
>+
>+	switch (value) {
>+	case DCN10_DIG_FE_SOURCE_SELECT_DIGA:
>+		result = ENGINE_ID_DIGA;
>+		break;
>+	case DCN10_DIG_FE_SOURCE_SELECT_DIGB:
>+		result = ENGINE_ID_DIGB;
>+		break;
>+	case DCN10_DIG_FE_SOURCE_SELECT_DIGC:
>+		result = ENGINE_ID_DIGC;
>+		break;
>+	case DCN10_DIG_FE_SOURCE_SELECT_DIGD:
>+		result = ENGINE_ID_DIGD;
>+		break;
>+	case DCN10_DIG_FE_SOURCE_SELECT_DIGE:
>+		result = ENGINE_ID_DIGE;
>+		break;
>+	case DCN10_DIG_FE_SOURCE_SELECT_DIGF:
>+		result = ENGINE_ID_DIGF;
>+		break;
>+	case DCN10_DIG_FE_SOURCE_SELECT_DIGG:
>+		result = ENGINE_ID_DIGG;
>+		break;
>+	default:
>+		// invalid source select DIG
>+		ASSERT(false);
>+		result = ENGINE_ID_UNKNOWN;
>+	}
>+
>+	return result;
>+
>+}
>+
> void enc1_configure_encoder(
> 	struct dcn10_link_encoder *enc10,
> 	const struct dc_link_settings *link_settings)
>@@ -501,15 +542,6 @@
> 	return value;
> }
> 
>-unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
>-{
>-	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
>-	uint32_t value;
>-
>-	REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
>-	return value;
>-}
>-
> static void link_encoder_disable(struct dcn10_link_encoder *enc10)
> {
> 	/* reset training pattern */
>@@ -1366,3 +1398,25 @@
> 	AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
> 			AUX_RX_RECEIVE_WINDOW, 0);
> }
>+
>+enum signal_type dcn10_get_dig_mode(
>+	struct link_encoder *enc)
>+{
>+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
>+	uint32_t value;
>+	REG_GET(DIG_BE_CNTL, DIG_MODE, &value);
>+	switch (value) {
>+	case 1:
>+		return SIGNAL_TYPE_DISPLAY_PORT;
>+	case 2:
>+		return SIGNAL_TYPE_DVI_SINGLE_LINK;
>+	case 3:
>+		return SIGNAL_TYPE_HDMI_TYPE_A;
>+	case 5:
>+		return SIGNAL_TYPE_DISPLAY_PORT_MST;
>+	default:
>+		return SIGNAL_TYPE_NONE;
>+	}
>+	return SIGNAL_TYPE_NONE;
>+}
>+
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h	2019-08-31 15:01:11.863736169 -0500
>@@ -337,6 +337,7 @@
> 		type RDPCS_TX_FIFO_ERROR_MASK;\
> 		type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
> 		type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
>+		type RDPCS_PHY_DPALT_DISABLE;\
> 		type RDPCS_PHY_DPALT_DISABLE_ACK;\
> 		type RDPCS_PHY_DP_MPLLB_V2I;\
> 		type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
>@@ -514,4 +515,6 @@
> 
> void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
> 
>+enum signal_type dcn10_get_dig_mode(
>+	struct link_encoder *enc);
> #endif /* __DC_LINK_ENCODER__DCN10_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c	2019-08-31 15:01:11.863736169 -0500
>@@ -211,7 +211,7 @@
> 	} else {
> 		new_mpcc->mpcc_bot = NULL;
> 		REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
>-		REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH);
>+		REG_UPDATE(MPCC_CONTROL[mpcc_id], MPCC_MODE, MPCC_BLEND_MODE_TOP_LAYER_ONLY);
> 	}
> 	REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
> 	REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
>@@ -364,6 +364,24 @@
> 	}
> }
> 
>+void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id)
>+{
>+	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
>+	int opp_id;
>+
>+	REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);
>+
>+	REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, 0xf);
>+	REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
>+	REG_SET(MPCC_OPP_ID[mpcc_id],  0, MPCC_OPP_ID,  0xf);
>+
>+	mpc1_init_mpcc(&(mpc->mpcc_array[mpcc_id]), mpcc_id);
>+
>+	if (opp_id < MAX_OPP && REG(MUX[opp_id]))
>+		REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
>+}
>+
>+
> void mpc1_init_mpcc_list_from_hw(
> 	struct mpc *mpc,
> 	struct mpc_tree *tree)
>@@ -433,6 +451,7 @@
> 	.insert_plane = mpc1_insert_plane,
> 	.remove_mpcc = mpc1_remove_mpcc,
> 	.mpc_init = mpc1_mpc_init,
>+	.mpc_init_single_inst = mpc1_mpc_init_single_inst,
> 	.get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp,
> 	.wait_for_idle = mpc1_assert_idle_mpcc,
> 	.assert_mpcc_idle_before_connect = mpc1_assert_mpcc_idle_before_connect,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h	2019-08-31 15:01:11.863736169 -0500
>@@ -149,6 +149,10 @@
> void mpc1_mpc_init(
> 	struct mpc *mpc);
> 
>+void mpc1_mpc_init_single_inst(
>+	struct mpc *mpc,
>+	unsigned int mpcc_id);
>+
> void mpc1_assert_idle_mpcc(
> 	struct mpc *mpc,
> 	int id);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c	2019-08-31 15:01:11.863736169 -0500
>@@ -154,7 +154,7 @@
> 	uint32_t h_sync_polarity, v_sync_polarity;
> 	uint32_t start_point = 0;
> 	uint32_t field_num = 0;
>-	uint32_t h_div_2;
>+	enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
> 
> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
> 
>@@ -285,10 +285,11 @@
> 	 * of stereo handled in explicit call
> 	 */
> 
>-	h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing);
>-	REG_UPDATE(OTG_H_TIMING_CNTL,
>-			OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->comb_opp_id != 0xf);
>+	if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
>+		h_div = H_TIMING_DIV_BY2;
> 
>+	REG_UPDATE(OTG_H_TIMING_CNTL,
>+		OTG_H_TIMING_DIV_BY2, h_div);
> }
> 
> void optc1_set_vtg_params(struct timing_generator *optc,
>@@ -824,6 +825,9 @@
> 
> 	REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
> 			MANUAL_FLOW_CONTROL, 1);
>+
>+	REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
>+			MANUAL_FLOW_CONTROL, 0);
> }
> 
> 
>@@ -846,6 +850,18 @@
> 		params->vertical_total_max > 0 &&
> 		params->vertical_total_min > 0) {
> 
>+		if (params->vertical_total_mid != 0) {
>+
>+			REG_SET(OTG_V_TOTAL_MID, 0,
>+				OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
>+
>+			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
>+					OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
>+					OTG_VTOTAL_MID_FRAME_NUM,
>+					(uint8_t)params->vertical_total_mid_frame_num);
>+
>+		}
>+
> 		REG_SET(OTG_V_TOTAL_MAX, 0,
> 			OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
> 
>@@ -1513,7 +1529,6 @@
> 	optc1->min_v_blank_interlace = 5;
> 	optc1->min_h_sync_width = 8;
> 	optc1->min_v_sync_width = 1;
>-	optc1->comb_opp_id = 0xf;
> }
> 
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h	2019-08-31 15:01:11.863736169 -0500
>@@ -54,6 +54,7 @@
> 	SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
> 	SRI(OTG_STEREO_STATUS, OTG, inst),\
> 	SRI(OTG_V_TOTAL_MAX, OTG, inst),\
>+	SRI(OTG_V_TOTAL_MID, OTG, inst),\
> 	SRI(OTG_V_TOTAL_MIN, OTG, inst),\
> 	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
> 	SRI(OTG_TRIGA_CNTL, OTG, inst),\
>@@ -125,6 +126,7 @@
> 	uint32_t OTG_3D_STRUCTURE_CONTROL;
> 	uint32_t OTG_STEREO_STATUS;
> 	uint32_t OTG_V_TOTAL_MAX;
>+	uint32_t OTG_V_TOTAL_MID;
> 	uint32_t OTG_V_TOTAL_MIN;
> 	uint32_t OTG_V_TOTAL_CONTROL;
> 	uint32_t OTG_TRIGA_CNTL;
>@@ -214,12 +216,15 @@
> 	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
> 	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
> 	SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
>+	SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\
> 	SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
> 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
> 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
> 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
> 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\
> 	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
>+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
>+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\
> 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
> 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
> 	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
>@@ -348,9 +353,12 @@
> 	type OTG_3D_STRUCTURE_V_UPDATE_MODE;\
> 	type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\
> 	type OTG_V_TOTAL_MAX;\
>+	type OTG_V_TOTAL_MID;\
> 	type OTG_V_TOTAL_MIN;\
> 	type OTG_V_TOTAL_MIN_SEL;\
> 	type OTG_V_TOTAL_MAX_SEL;\
>+	type OTG_VTOTAL_MID_REPLACING_MAX_EN;\
>+	type OTG_VTOTAL_MID_FRAME_NUM;\
> 	type OTG_FORCE_LOCK_ON_EVENT;\
> 	type OTG_SET_V_TOTAL_MIN_MASK_EN;\
> 	type OTG_SET_V_TOTAL_MIN_MASK;\
>@@ -494,7 +502,7 @@
> 	const struct dcn_optc_shift *tg_shift;
> 	const struct dcn_optc_mask *tg_mask;
> 
>-	int comb_opp_id;
>+	int opp_count;
> 
> 	uint32_t max_h_total;
> 	uint32_t max_v_total;
>@@ -539,6 +547,10 @@
> void optc1_read_otg_state(struct optc *optc1,
> 		struct dcn_otg_state *s);
> 
>+bool optc1_is_matching_timing(
>+	struct timing_generator *tg,
>+	const struct dc_crtc_timing *otg_timing);
>+
> bool optc1_validate_timing(
> 	struct timing_generator *optc,
> 	const struct dc_crtc_timing *timing);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c	2019-08-31 15:01:11.864736169 -0500
>@@ -270,7 +270,7 @@
> 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
> };
> 
>-static const struct dce_aduio_mask audio_mask = {
>+static const struct dce_audio_mask audio_mask = {
> 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
> };
> 
>@@ -1416,6 +1416,14 @@
> 
> 	pool->base.pp_smu = dcn10_pp_smu_create(ctx);
> 
>+	/*
>+	 * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification *
>+	 * implemented. So AZ D3 should work.For issue 197007.                   *
>+	 */
>+	if (pool->base.pp_smu != NULL
>+			&& pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
>+		dc->debug.az_endpoint_mute_only = false;
>+
> 	if (!dc->debug.disable_pplib_clock_request)
> 		dcn_bw_update_from_pplib(dc);
> 	dcn_bw_sync_calcs_and_dml(dc);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c	2019-08-31 15:01:11.864736169 -0500
>@@ -512,11 +512,12 @@
> 	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
> 
> 	/* setup HDMI engine */
>-	REG_UPDATE_5(HDMI_CONTROL,
>+	REG_UPDATE_6(HDMI_CONTROL,
> 		HDMI_PACKET_GEN_VERSION, 1,
> 		HDMI_KEEPOUT_MODE, 1,
> 		HDMI_DEEP_COLOR_ENABLE, 0,
> 		HDMI_DATA_SCRAMBLE_EN, 0,
>+		HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
> 		HDMI_CLOCK_CHANNEL_RATE, 0);
> 
> 
>@@ -1003,6 +1004,19 @@
> 	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
> }
> 
>+void enc1_reset_hdmi_stream_attribute(
>+	struct stream_encoder *enc)
>+{
>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
>+
>+	REG_UPDATE_5(HDMI_CONTROL,
>+		HDMI_PACKET_GEN_VERSION, 1,
>+		HDMI_KEEPOUT_MODE, 1,
>+		HDMI_DEEP_COLOR_ENABLE, 0,
>+		HDMI_DATA_SCRAMBLE_EN, 0,
>+		HDMI_CLOCK_CHANNEL_RATE, 0);
>+}
>+
> 
> #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
> #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
>@@ -1196,13 +1210,13 @@
> 
> void get_audio_clock_info(
> 	enum dc_color_depth color_depth,
>-	uint32_t crtc_pixel_clock_in_khz,
>-	uint32_t actual_pixel_clock_in_khz,
>+	uint32_t crtc_pixel_clock_100Hz,
>+	uint32_t actual_pixel_clock_100Hz,
> 	struct audio_clock_info *audio_clock_info)
> {
> 	const struct audio_clock_info *clock_info;
> 	uint32_t index;
>-	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
>+	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
> 	uint32_t audio_array_size;
> 
> 	switch (color_depth) {
>@@ -1239,16 +1253,16 @@
> 	}
> 
> 	/* not found */
>-	if (actual_pixel_clock_in_khz == 0)
>-		actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
>+	if (actual_pixel_clock_100Hz == 0)
>+		actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
> 
> 	/* See HDMI spec  the table entry under
> 	 *  pixel clock of "Other". */
> 	audio_clock_info->pixel_clock_in_10khz =
>-			actual_pixel_clock_in_khz / 10;
>-	audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
>-	audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
>-	audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
>+			actual_pixel_clock_100Hz / 100;
>+	audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
>+	audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
>+	audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
> 
> 	audio_clock_info->n_32khz = 4096;
> 	audio_clock_info->n_44khz = 6272;
>@@ -1308,14 +1322,14 @@
> 
> 	/* Program audio clock sample/regeneration parameters */
> 	get_audio_clock_info(crtc_info->color_depth,
>-			     crtc_info->requested_pixel_clock,
>-			     crtc_info->calculated_pixel_clock,
>+			     crtc_info->requested_pixel_clock_100Hz,
>+			     crtc_info->calculated_pixel_clock_100Hz,
> 			     &audio_clock_info);
> 	DC_LOG_HW_AUDIO(
>-			"\n%s:Input::requested_pixel_clock = %d"	\
>-			"calculated_pixel_clock = %d \n", __func__,	\
>-			crtc_info->requested_pixel_clock,		\
>-			crtc_info->calculated_pixel_clock);
>+			"\n%s:Input::requested_pixel_clock_100Hz = %d"	\
>+			"calculated_pixel_clock_100Hz = %d \n", __func__,	\
>+			crtc_info->requested_pixel_clock_100Hz,		\
>+			crtc_info->calculated_pixel_clock_100Hz);
> 
> 	/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
> 	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
>@@ -1528,6 +1542,17 @@
> 	REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
> }
> 
>+unsigned int enc1_dig_source_otg(
>+	struct stream_encoder *enc)
>+{
>+	uint32_t tg_inst = 0;
>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
>+
>+	REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
>+
>+	return tg_inst;
>+}
>+
> static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
> 	.dp_set_stream_attribute =
> 		enc1_stream_encoder_dp_set_stream_attribute,
>@@ -1562,6 +1587,8 @@
> 	.setup_stereo_sync  = enc1_setup_stereo_sync,
> 	.set_avmute = enc1_stream_encoder_set_avmute,
> 	.dig_connect_to_otg  = enc1_dig_connect_to_otg,
>+	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
>+	.dig_source_otg = enc1_dig_source_otg,
> };
> 
> void dcn10_stream_encoder_construct(
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h	2019-08-31 15:01:11.864736169 -0500
>@@ -89,7 +89,8 @@
> 	SRI(DP_VID_STREAM_CNTL, DP, id), \
> 	SRI(DP_VID_TIMING, DP, id), \
> 	SRI(DP_SEC_AUD_N, DP, id), \
>-	SRI(DP_SEC_TIMESTAMP, DP, id)
>+	SRI(DP_SEC_TIMESTAMP, DP, id), \
>+	SRI(DIG_CLOCK_PATTERN, DIG, id)
> 
> #define SE_DCN_REG_LIST(id)\
> 	SE_COMMON_DCN_REG_LIST(id)
>@@ -170,6 +171,7 @@
> 	uint32_t HDMI_METADATA_PACKET_CONTROL;
> 	uint32_t DP_SEC_FRAMING4;
> #endif
>+	uint32_t DIG_CLOCK_PATTERN;
> };
> 
> 
>@@ -189,6 +191,7 @@
> 	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
> 	SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
> 	SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
>+	SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\
> 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
> 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
> 	SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
>@@ -297,7 +300,8 @@
> 	SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
> 	SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
> 	SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
>-	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh)
>+	SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\
>+	SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh)
> 
> #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
> 	SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
>@@ -374,6 +378,7 @@
> 	type HDMI_GC_SEND;\
> 	type HDMI_NULL_SEND;\
> 	type HDMI_DATA_SCRAMBLE_EN;\
>+	type HDMI_NO_EXTRA_NULL_PACKET_FILLED;\
> 	type HDMI_AUDIO_INFO_SEND;\
> 	type AFMT_AUDIO_INFO_UPDATE;\
> 	type HDMI_AUDIO_INFO_LINE;\
>@@ -458,7 +463,8 @@
> 	type HDMI_DB_DISABLE;\
> 	type DP_VID_N_MUL;\
> 	type DP_VID_M_DOUBLE_VALUE_EN;\
>-	type DIG_SOURCE_SELECT
>+	type DIG_SOURCE_SELECT;\
>+	type DIG_CLOCK_PATTERN
> 
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> #define SE_REG_FIELD_LIST_DCN2_0(type) \
>@@ -592,6 +598,9 @@
> 	struct stream_encoder *enc,
> 	int tg_inst);
> 
>+unsigned int enc1_dig_source_otg(
>+	struct stream_encoder *enc);
>+
> void enc1_stream_encoder_set_stream_attribute_helper(
> 	struct dcn10_stream_encoder *enc1,
> 	struct dc_crtc_timing *crtc_timing);
>@@ -605,8 +614,11 @@
> 
> void get_audio_clock_info(
> 	enum dc_color_depth color_depth,
>-	uint32_t crtc_pixel_clock_in_khz,
>-	uint32_t actual_pixel_clock_in_khz,
>+	uint32_t crtc_pixel_clock_100Hz,
>+	uint32_t actual_pixel_clock_100Hz,
> 	struct audio_clock_info *audio_clock_info);
> 
>+void enc1_reset_hdmi_stream_attribute(
>+	struct stream_encoder *enc);
>+
> #endif /* __DC_STREAM_ENCODER_DCN10_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c	2019-08-31 15:01:11.864736169 -0500
>@@ -44,12 +44,16 @@
> #define DC_LOGGER \
> 	dccg->ctx->logger
> 
>-void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
>+void dccg2_update_dpp_dto(struct dccg *dccg,
>+		int dpp_inst,
>+		int req_dppclk,
>+		bool reduce_divider_only)
> {
> 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
> 
> 	if (dccg->ref_dppclk && req_dppclk) {
> 		int ref_dppclk = dccg->ref_dppclk;
>+		int current_phase, current_modulo;
> 
> 		ASSERT(req_dppclk <= ref_dppclk);
> 		/* need to clamp to 8 bits */
>@@ -61,9 +65,28 @@
> 			if (req_dppclk > ref_dppclk)
> 				req_dppclk = ref_dppclk;
> 		}
>-		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
>-				DPPCLK0_DTO_PHASE, req_dppclk,
>-				DPPCLK0_DTO_MODULO, ref_dppclk);
>+
>+		REG_GET_2(DPPCLK_DTO_PARAM[dpp_inst],
>+				DPPCLK0_DTO_PHASE, &current_phase,
>+				DPPCLK0_DTO_MODULO, &current_modulo);
>+
>+		if (reduce_divider_only) {
>+			// requested phase/modulo greater than current
>+			if (req_dppclk * current_modulo >= current_phase * ref_dppclk) {
>+				REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
>+						DPPCLK0_DTO_PHASE, req_dppclk,
>+						DPPCLK0_DTO_MODULO, ref_dppclk);
>+			} else {
>+				REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
>+						DPPCLK0_DTO_PHASE, current_phase,
>+						DPPCLK0_DTO_MODULO, current_modulo);
>+			}
>+		} else {
>+			REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
>+					DPPCLK0_DTO_PHASE, req_dppclk,
>+					DPPCLK0_DTO_MODULO, ref_dppclk);
>+		}
>+
> 		REG_UPDATE(DPPCLK_DTO_CTRL,
> 				DPPCLK_DTO_ENABLE[dpp_inst], 1);
> 	} else {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h	2019-08-31 15:01:11.864736169 -0500
>@@ -97,7 +97,7 @@
> 	const struct dccg_mask *dccg_mask;
> };
> 
>-void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
>+void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk, bool raise_divider_only);
> 
> void dccg2_get_dccg_ref_freq(struct dccg *dccg,
> 		unsigned int xtalin_freq_inKhz,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c	2019-08-31 15:01:11.864736169 -0500
>@@ -72,6 +72,21 @@
> 	}
> }
> 
>+void dpp2_power_on_obuf(
>+		struct dpp *dpp_base,
>+	bool power_on)
>+{
>+	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
>+
>+	REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0);
>+
>+	REG_UPDATE(OBUF_MEM_PWR_CTRL,
>+			OBUF_MEM_PWR_FORCE, power_on == true ? 0:1);
>+
>+	REG_UPDATE(DSCL_MEM_PWR_CTRL,
>+			LUT_MEM_PWR_FORCE, power_on == true ? 0:1);
>+}
>+
> void dpp2_dummy_program_input_lut(
> 		struct dpp *dpp_base,
> 		const struct dc_gamma *gamma)
>@@ -227,6 +242,7 @@
> 				CUR0_ENABLE, 0);
> 
> 	}
>+	dpp2_power_on_obuf(dpp_base, true);
> 
> }
> 
>@@ -326,14 +342,18 @@
> 
> void dpp2_set_cursor_attributes(
> 		struct dpp *dpp_base,
>-		enum dc_cursor_color_format color_format)
>+		struct dc_cursor_attributes *cursor_attributes)
> {
>+	enum dc_cursor_color_format color_format = cursor_attributes->color_format;
> 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
> 	int cur_rom_en = 0;
> 
> 	if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
>-		color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA)
>-		cur_rom_en = 1;
>+		color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
>+		if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) {
>+			cur_rom_en = 1;
>+		}
>+	}
> 
> 	REG_UPDATE_3(CURSOR0_CONTROL,
> 			CUR0_MODE, color_format,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c	2019-08-31 15:01:11.865736169 -0500
>@@ -52,7 +52,12 @@
> {
> 	struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);
> 
>-	REG_UPDATE(CM_CONTROL, CM_BYPASS, 0);
>+	unsigned int cm_bypass_mode = 0;
>+	//Temp, put CM in bypass mode
>+	if (dpp_base->ctx->dc->debug.cm_in_bypass)
>+		cm_bypass_mode = 1;
>+
>+	REG_UPDATE(CM_CONTROL, CM_BYPASS, cm_bypass_mode);
> }
> 
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h	2019-08-31 15:01:11.864736169 -0500
>@@ -162,7 +162,9 @@
> 	SRI(COLOR_KEYER_GREEN, CNVC_CFG, id), \
> 	SRI(COLOR_KEYER_BLUE, CNVC_CFG, id), \
> 	SRI(CM_SHAPER_LUT_DATA, CM, id), \
>-	SRI(CURSOR_CONTROL, CURSOR0_, id)
>+	SRI(CURSOR_CONTROL, CURSOR0_, id),\
>+	SRI(OBUF_MEM_PWR_CTRL, DSCL, id),\
>+	SRI(DSCL_MEM_PWR_CTRL, DSCL, id)
> 
> #define TF_REG_LIST_SH_MASK_DCN20(mask_sh)\
> 	TF_REG_LIST_SH_MASK_DCN(mask_sh), \
>@@ -554,7 +556,9 @@
> 	TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \
> 	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \
> 	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \
>-	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh)
>+	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\
>+	TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\
>+	TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh)
> 
> #define TF_REG_FIELD_LIST_DCN2_0(type) \
> 	TF_REG_FIELD_LIST(type) \
>@@ -585,7 +589,9 @@
> 	type COLOR_KEYER_BLUE_HIGH; \
> 	type CUR0_PIX_INV_MODE; \
> 	type CUR0_PIXEL_ALPHA_MOD_EN; \
>-	type CUR0_ROM_EN
>+	type CUR0_ROM_EN;\
>+	type OBUF_MEM_PWR_FORCE;\
>+	type LUT_MEM_PWR_FORCE
> 
> struct dcn2_dpp_shift {
> 	TF_REG_FIELD_LIST_DCN2_0(uint8_t);
>@@ -609,7 +615,9 @@
> 	uint32_t COLOR_KEYER_ALPHA; \
> 	uint32_t COLOR_KEYER_RED; \
> 	uint32_t COLOR_KEYER_GREEN; \
>-	uint32_t COLOR_KEYER_BLUE
>+	uint32_t COLOR_KEYER_BLUE; \
>+	uint32_t OBUF_MEM_PWR_CTRL;\
>+	uint32_t DSCL_MEM_PWR_CTRL
> 
> struct dcn2_dpp_registers {
> 	DPP_DCN2_REG_VARIABLE_LIST;
>@@ -668,7 +676,7 @@
> 
> void dpp2_set_cursor_attributes(
> 		struct dpp *dpp_base,
>-		enum dc_cursor_color_format color_format);
>+		struct dc_cursor_attributes *cursor_attributes);
> 
> void dpp2_dummy_program_input_lut(
> 			struct dpp *dpp_base,
>@@ -695,4 +703,7 @@
> 	const struct dcn2_dpp_shift *tf_shift,
> 	const struct dcn2_dpp_mask *tf_mask);
> 
>+void dpp2_power_on_obuf(
>+		struct dpp *dpp_base,
>+	bool power_on);
> #endif /* __DC_HWSS_DCN20_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c	2019-08-31 15:01:11.865736169 -0500
>@@ -29,7 +29,7 @@
> #include "dsc/dscc_types.h"
> 
> static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps);
>-static bool dsc_prepare_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
>+static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
> 			struct dsc_optc_config *dsc_optc_cfg);
> static void dsc_init_reg_values(struct dsc_reg_values *reg_vals);
> static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params);
>@@ -42,7 +42,8 @@
> static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
> static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
> static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
>-		struct dsc_optc_config *dsc_optc_cfg, uint8_t *dsc_packed_pps);
>+		struct dsc_optc_config *dsc_optc_cfg);
>+static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps);
> static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);
> static void dsc2_disable(struct display_stream_compressor *dsc);
> 
>@@ -51,6 +52,7 @@
> 	.dsc_read_state = dsc2_read_state,
> 	.dsc_validate_stream = dsc2_validate_stream,
> 	.dsc_set_config = dsc2_set_config,
>+	.dsc_get_packed_pps = dsc2_get_packed_pps,
> 	.dsc_enable = dsc2_enable,
> 	.dsc_disable = dsc2_disable,
> };
>@@ -116,8 +118,8 @@
> 
> 	dsc_enc_caps->color_formats.bits.RGB = 1;
> 	dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
>-	dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
>-	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;
>+	dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 0;
>+	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
> 	dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
> 
> 	dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
>@@ -162,40 +164,61 @@
> static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
> {
> 	struct dsc_optc_config dsc_optc_cfg;
>+	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
> 
>-	if (dsc_cfg->pic_width > TO_DCN20_DSC(dsc)->max_image_width)
>+	if (dsc_cfg->pic_width > dsc20->max_image_width)
> 		return false;
> 
>-	return dsc_prepare_config(dsc, dsc_cfg, &dsc_optc_cfg);
>+	return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);
> }
> 
> 
>-static void dsc_config_log(struct display_stream_compressor *dsc,
>-		const struct dsc_config *config)
>+static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)
> {
>-	DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
>-	DC_LOG_DSC("\n\tnum_slices_h %d\n\tnum_slices_v %d\n\tbits_per_pixel %d\n\tcolor_depth %d",
>-		config->dc_dsc_cfg.num_slices_h,
>-		config->dc_dsc_cfg.num_slices_v,
>+	DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);
>+	DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);
>+	DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)",
> 		config->dc_dsc_cfg.bits_per_pixel,
>-		config->color_depth);
>+		config->dc_dsc_cfg.bits_per_pixel / 16,
>+		((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16);
>+	DC_LOG_DSC("\tcolor_depth %d", config->color_depth);
> }
> 
> static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
>-		struct dsc_optc_config *dsc_optc_cfg, uint8_t *dsc_packed_pps)
>+		struct dsc_optc_config *dsc_optc_cfg)
> {
> 	bool is_config_ok;
> 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
> 
>+	DC_LOG_DSC(" ");
>+	DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
> 	dsc_config_log(dsc, dsc_cfg);
>-	is_config_ok = dsc_prepare_config(dsc, dsc_cfg, dsc_optc_cfg);
>+	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
> 	ASSERT(is_config_ok);
>-	drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc20->reg_vals.pps);
>+	DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
> 	dsc_log_pps(dsc, &dsc20->reg_vals.pps);
> 	dsc_write_to_registers(dsc, &dsc20->reg_vals);
> }
> 
> 
>+static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)
>+{
>+	bool is_config_ok;
>+	struct dsc_reg_values dsc_reg_vals;
>+	struct dsc_optc_config dsc_optc_cfg;
>+
>+	DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
>+	dsc_config_log(dsc, dsc_cfg);
>+	DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
>+	is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg);
>+	ASSERT(is_config_ok);
>+	drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);
>+	dsc_log_pps(dsc, &dsc_reg_vals.pps);
>+
>+	return is_config_ok;
>+}
>+
>+
> static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
> {
> 	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
>@@ -232,7 +255,6 @@
> 	int i;
> 	int bits_per_pixel = pps->bits_per_pixel;
> 
>-	DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
> 	DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);
> 	DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);
> 	DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);
>@@ -282,13 +304,11 @@
> 	}
> }
> 
>-static bool dsc_prepare_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
>+static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
> 			struct dsc_optc_config *dsc_optc_cfg)
> {
> 	struct dsc_parameters dsc_params;
> 
>-	struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
>-
> 	/* Validate input parameters */
> 	ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h);
> 	ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v);
>@@ -302,7 +322,7 @@
> 		    dsc_cfg->dc_dsc_cfg.linebuf_depth == 0)));
> 	ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375
> 
>-	if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_v ||
>+	if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h ||
> 		!(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) ||
> 		!dsc_cfg->pic_width || !dsc_cfg->pic_height ||
> 		!((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range:
>@@ -315,54 +335,54 @@
> 		return false;
> 	}
> 
>-	dsc_init_reg_values(&dsc20->reg_vals);
>+	dsc_init_reg_values(dsc_reg_vals);
> 
> 	/* Copy input config */
>-	dsc20->reg_vals.pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
>-	dsc20->reg_vals.num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
>-	dsc20->reg_vals.num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
>-	dsc20->reg_vals.pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
>-	dsc20->reg_vals.pps.pic_width = dsc_cfg->pic_width;
>-	dsc20->reg_vals.pps.pic_height = dsc_cfg->pic_height;
>-	dsc20->reg_vals.pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
>-	dsc20->reg_vals.pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
>-	dsc20->reg_vals.pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
>-	dsc20->reg_vals.alternate_ich_encoding_en = dsc20->reg_vals.pps.dsc_version_minor == 1 ? 0 : 1;
>+	dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
>+	dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
>+	dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
>+	dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
>+	dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
>+	dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
>+	dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
>+	dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
>+	dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
>+	dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;
> 
> 	// TODO: in addition to validating slice height (pic height must be divisible by slice height),
> 	// see what happens when the same condition doesn't apply for slice_width/pic_width.
>-	dsc20->reg_vals.pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
>-	dsc20->reg_vals.pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
>+	dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
>+	dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
> 
>-	ASSERT(dsc20->reg_vals.pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
>-	if (!(dsc20->reg_vals.pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
>+	ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
>+	if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
> 		dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v);
> 		return false;
> 	}
> 
>-	dsc20->reg_vals.bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
>-	if (dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
>-		dsc20->reg_vals.pps.bits_per_pixel = dsc20->reg_vals.bpp_x32;
>+	dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
>+	if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
>+		dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;
> 	else
>-		dsc20->reg_vals.pps.bits_per_pixel = dsc20->reg_vals.bpp_x32 >> 1;
>+		dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;
> 
>-	dsc20->reg_vals.pps.convert_rgb = dsc20->reg_vals.pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
>-	dsc20->reg_vals.pps.native_422 = (dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
>-	dsc20->reg_vals.pps.native_420 = (dsc20->reg_vals.pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);
>-	dsc20->reg_vals.pps.simple_422 = (dsc20->reg_vals.pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);
>+	dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
>+	dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
>+	dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);
>+	dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);
> 
>-	if (dscc_compute_dsc_parameters(&dsc20->reg_vals.pps, &dsc_params)) {
>+	if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) {
> 		dm_output_to_console("%s: DSC config failed\n", __func__);
> 		return false;
> 	}
> 
>-	dsc_update_from_dsc_parameters(&dsc20->reg_vals, &dsc_params);
>+	dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params);
> 
> 	dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel;
>-	dsc_optc_cfg->slice_width = dsc20->reg_vals.pps.slice_width;
>-	dsc_optc_cfg->is_pixel_format_444 = dsc20->reg_vals.pixel_format == DSC_PIXFMT_RGB ||
>-					dsc20->reg_vals.pixel_format == DSC_PIXFMT_YCBCR444 ||
>-					dsc20->reg_vals.pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;
>+	dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;
>+	dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ||
>+					dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 ||
>+					dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;
> 
> 	return true;
> }
>@@ -427,6 +447,8 @@
> {
> 	int i;
> 
>+	memset(reg_vals, 0, sizeof(struct dsc_reg_values));
>+
> 	/* Non-PPS values */
> 	reg_vals->dsc_clock_enable            = 1;
> 	reg_vals->dsc_clock_gating_disable    = 0;
>@@ -436,7 +458,7 @@
> 	reg_vals->ich_reset_at_eol            = 0;
> 	reg_vals->alternate_ich_encoding_en   = 0;
> 	reg_vals->rc_buffer_model_size        = 0;
>-	reg_vals->disable_ich                 = 0;
>+	/*reg_vals->disable_ich                 = 0;*/
> 	reg_vals->dsc_dbg_en                  = 0;
> 
> 	for (i = 0; i < 4; i++)
>@@ -518,9 +540,11 @@
> 		ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
> 		NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
> 
>-	REG_SET_2(DSCC_CONFIG1, 0,
>+	REG_SET(DSCC_CONFIG1, 0,
>+			DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);
>+	/*REG_SET_2(DSCC_CONFIG1, 0,
> 		DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,
>-		DSCC_DISABLE_ICH, reg_vals->disable_ich);
>+		DSCC_DISABLE_ICH, reg_vals->disable_ich);*/
> 
> 	REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,
> 		DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0],
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h	2019-08-31 15:01:11.865736169 -0500
>@@ -103,7 +103,7 @@
> 	DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \
> 	DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \
> 	DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \
>-	DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh), \
>+	/*DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh),*/ \
> 	DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
> 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \
> 	DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \
>@@ -278,7 +278,7 @@
> 	type ALTERNATE_ICH_ENCODING_EN; \
> 	type NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION; \
> 	type DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE; \
>-	type DSCC_DISABLE_ICH; \
>+	/*type DSCC_DISABLE_ICH;*/ \
> 	type DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING; \
> 	type DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED; \
> 	type DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED; \
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c	2019-08-31 15:01:11.865736169 -0500
>@@ -26,6 +26,7 @@
> 
> #include "dcn20_hubbub.h"
> #include "reg_helper.h"
>+#include "clk_mgr.h"
> 
> #define REG(reg)\
> 	hubbub1->regs->reg
>@@ -379,6 +380,11 @@
> 	REG_SET(DCN_VM_AGP_BASE, 0,
> 			AGP_BASE, pa_config->system_aperture.agp_base >> 24);
> 
>+	REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
>+			DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF);
>+	REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
>+			DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, (pa_config->page_table_default_page_addr >> 12) & 0xFFFFFFFF);
>+
> 	if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
> 		phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
> 		phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;
>@@ -397,54 +403,67 @@
> {
> 	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
> 
>-	if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {
>-		ASSERT(false);
>-		/*should not come here*/
>+	if (REG(DCN_VM_FB_LOCATION_TOP) == 0)
> 		return;
>-	}
>-	/* TODO: port code from dal2 */
>+
> 	switch (dh_data->fb_mode) {
> 	case FRAME_BUFFER_MODE_ZFB_ONLY:
> 		/*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
>-		REG_UPDATE(DCHUBBUB_SDPIF_FB_TOP,
>-				SDPIF_FB_TOP, 0);
>+		REG_UPDATE(DCN_VM_FB_LOCATION_TOP,
>+				FB_TOP, 0);
> 
>-		REG_UPDATE(DCHUBBUB_SDPIF_FB_BASE,
>-				SDPIF_FB_BASE, 0x0FFFF);
>+		REG_UPDATE(DCN_VM_FB_LOCATION_BASE,
>+				FB_BASE, 0xFFFFFF);
> 
>-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
>-				SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
>-
>-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
>-				SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
>-
>-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
>-				SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
>-						dh_data->zfb_size_in_byte - 1) >> 22);
>+		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
>+		REG_UPDATE(DCN_VM_AGP_BASE,
>+				AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
>+
>+		/*This field defines the bottom range of the AGP aperture and represents the 24*/
>+		/*MSBs, bits [47:24] of the 48 address bits*/
>+		REG_UPDATE(DCN_VM_AGP_BOT,
>+				AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
>+
>+		/*This field defines the top range of the AGP aperture and represents the 24*/
>+		/*MSBs, bits [47:24] of the 48 address bits*/
>+		REG_UPDATE(DCN_VM_AGP_TOP,
>+				AGP_TOP, (dh_data->zfb_mc_base_addr +
>+						dh_data->zfb_size_in_byte - 1) >> 24);
> 		break;
> 	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
> 		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
> 
>-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
>-				SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
>-
>-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
>-				SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
>-
>-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
>-				SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
>-						dh_data->zfb_size_in_byte - 1) >> 22);
>+		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
>+		REG_UPDATE(DCN_VM_AGP_BASE,
>+				AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
>+
>+		/*This field defines the bottom range of the AGP aperture and represents the 24*/
>+		/*MSBs, bits [47:24] of the 48 address bits*/
>+		REG_UPDATE(DCN_VM_AGP_BOT,
>+				AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
>+
>+		/*This field defines the top range of the AGP aperture and represents the 24*/
>+		/*MSBs, bits [47:24] of the 48 address bits*/
>+		REG_UPDATE(DCN_VM_AGP_TOP,
>+				AGP_TOP, (dh_data->zfb_mc_base_addr +
>+						dh_data->zfb_size_in_byte - 1) >> 24);
> 		break;
> 	case FRAME_BUFFER_MODE_LOCAL_ONLY:
>-		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
>-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
>-				SDPIF_AGP_BASE, 0);
>+		/*Should not touch FB LOCATION (should be done by VBIOS)*/
> 
>-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
>-				SDPIF_AGP_BOT, 0X03FFFF);
>-
>-		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
>-				SDPIF_AGP_TOP, 0);
>+		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
>+		REG_UPDATE(DCN_VM_AGP_BASE,
>+				AGP_BASE, 0);
>+
>+		/*This field defines the bottom range of the AGP aperture and represents the 24*/
>+		/*MSBs, bits [47:24] of the 48 address bits*/
>+		REG_UPDATE(DCN_VM_AGP_BOT,
>+				AGP_BOT, 0xFFFFFF);
>+
>+		/*This field defines the top range of the AGP aperture and represents the 24*/
>+		/*MSBs, bits [47:24] of the 48 address bits*/
>+		REG_UPDATE(DCN_VM_AGP_TOP,
>+				AGP_TOP, 0);
> 		break;
> 	default:
> 		break;
>@@ -553,6 +572,16 @@
> 	 */
> 	hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
> 	hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
>+
>+	/*
>+	 * There's a special case when going from p-state support to p-state unsupported
>+	 * here we are going to LOWER watermarks to go to dummy p-state only, but this has
>+	 * to be done prepare_bandwidth, not optimize
>+	 */
>+	if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true &&
>+		hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false)
>+		safe_to_lower = true;
>+
> 	hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
> 
> 	REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
>@@ -571,7 +600,7 @@
> 	.get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
> 	.wm_read_state = hubbub2_wm_read_state,
> 	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
>-	.program_watermarks = hubbub2_program_watermarks,
>+	.program_watermarks = hubbub2_program_watermarks
> };
> 
> void hubbub2_construct(struct dcn20_hubbub *hubbub,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h	2019-08-31 15:01:11.865736169 -0500
>@@ -29,13 +29,21 @@
> #include "dcn10/dcn10_hubbub.h"
> #include "dcn20_vmid.h"
> 
>+#define HUBBUB_REG_LIST_DCN20_COMMON()\
>+	HUBBUB_REG_LIST_DCN_COMMON(), \
>+	SR(DCHUBBUB_CRC_CTRL), \
>+	SR(DCN_VM_FB_LOCATION_BASE),\
>+	SR(DCN_VM_FB_LOCATION_TOP),\
>+	SR(DCN_VM_FB_OFFSET),\
>+	SR(DCN_VM_AGP_BOT),\
>+	SR(DCN_VM_AGP_TOP),\
>+	SR(DCN_VM_AGP_BASE)
>+
> #define TO_DCN20_HUBBUB(hubbub)\
> 	container_of(hubbub, struct dcn20_hubbub, base)
> 
>-#define HUBBUB_REG_LIST_DCN20(id)\
>+#define HUBBUB_REG_LIST_DCN20_COMMON()\
> 	HUBBUB_REG_LIST_DCN_COMMON(), \
>-	HUBBUB_VM_REG_LIST(), \
>-	HUBBUB_SR_WATERMARK_REG_LIST(), \
> 	SR(DCHUBBUB_CRC_CTRL), \
> 	SR(DCN_VM_FB_LOCATION_BASE),\
> 	SR(DCN_VM_FB_LOCATION_TOP),\
>@@ -44,6 +52,14 @@
> 	SR(DCN_VM_AGP_TOP),\
> 	SR(DCN_VM_AGP_BASE)
> 
>+#define HUBBUB_REG_LIST_DCN20(id)\
>+	HUBBUB_REG_LIST_DCN20_COMMON(), \
>+	HUBBUB_SR_WATERMARK_REG_LIST(), \
>+	HUBBUB_VM_REG_LIST(),\
>+	SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB),\
>+	SR(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB)
>+
>+
> #define HUBBUB_MASK_SH_LIST_DCN20(mask_sh)\
> 	HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
> 	HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
>@@ -53,7 +69,9 @@
> 	HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
> 	HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
> 	HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
>-	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh)
>+	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
>+	HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, mask_sh), \
>+	HUBBUB_SF(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, mask_sh)
> 
> struct dcn20_hubbub {
> 	struct hubbub base;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c	2019-08-31 15:01:11.865736169 -0500
>@@ -40,81 +40,6 @@
> #define FN(reg_name, field_name) \
> 	hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
> 
>-void hubp2_update_dchub(
>-	struct hubp *hubp,
>-	struct dchub_init_data *dh_data)
>-{
>-	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>-	if (REG(DCN_VM_FB_LOCATION_TOP) == 0)
>-		return;
>-
>-	switch (dh_data->fb_mode) {
>-	case FRAME_BUFFER_MODE_ZFB_ONLY:
>-		/*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
>-		REG_UPDATE(DCN_VM_FB_LOCATION_TOP,
>-				FB_TOP, 0);
>-
>-		REG_UPDATE(DCN_VM_FB_LOCATION_BASE,
>-				FB_BASE, 0xFFFFFF);
>-
>-		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
>-		REG_UPDATE(DCN_VM_AGP_BASE,
>-				AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
>-
>-		/*This field defines the bottom range of the AGP aperture and represents the 24*/
>-		/*MSBs, bits [47:24] of the 48 address bits*/
>-		REG_UPDATE(DCN_VM_AGP_BOT,
>-				AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
>-
>-		/*This field defines the top range of the AGP aperture and represents the 24*/
>-		/*MSBs, bits [47:24] of the 48 address bits*/
>-		REG_UPDATE(DCN_VM_AGP_TOP,
>-				AGP_TOP, (dh_data->zfb_mc_base_addr +
>-						dh_data->zfb_size_in_byte - 1) >> 24);
>-		break;
>-	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
>-		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
>-
>-		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
>-		REG_UPDATE(DCN_VM_AGP_BASE,
>-				AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
>-
>-		/*This field defines the bottom range of the AGP aperture and represents the 24*/
>-		/*MSBs, bits [47:24] of the 48 address bits*/
>-		REG_UPDATE(DCN_VM_AGP_BOT,
>-				AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
>-
>-		/*This field defines the top range of the AGP aperture and represents the 24*/
>-		/*MSBs, bits [47:24] of the 48 address bits*/
>-		REG_UPDATE(DCN_VM_AGP_TOP,
>-				AGP_TOP, (dh_data->zfb_mc_base_addr +
>-						dh_data->zfb_size_in_byte - 1) >> 24);
>-		break;
>-	case FRAME_BUFFER_MODE_LOCAL_ONLY:
>-		/*Should not touch FB LOCATION (should be done by VBIOS)*/
>-
>-		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
>-		REG_UPDATE(DCN_VM_AGP_BASE,
>-				AGP_BASE, 0);
>-
>-		/*This field defines the bottom range of the AGP aperture and represents the 24*/
>-		/*MSBs, bits [47:24] of the 48 address bits*/
>-		REG_UPDATE(DCN_VM_AGP_BOT,
>-				AGP_BOT, 0xFFFFFF);
>-
>-		/*This field defines the top range of the AGP aperture and represents the 24*/
>-		/*MSBs, bits [47:24] of the 48 address bits*/
>-		REG_UPDATE(DCN_VM_AGP_TOP,
>-				AGP_TOP, 0);
>-		break;
>-	default:
>-		break;
>-	}
>-
>-	dh_data->dchub_initialzied = true;
>-	dh_data->dchub_info_valid = false;
>-}
>-
> void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
> 		struct vm_system_aperture_param *apt)
> {
>@@ -156,7 +81,85 @@
> {
> 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
> 
>-	hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
>+	/* DLG - Per hubp */
>+	REG_SET_2(BLANK_OFFSET_0, 0,
>+		REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
>+		DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
>+
>+	REG_SET(BLANK_OFFSET_1, 0,
>+		MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
>+
>+	REG_SET(DST_DIMENSIONS, 0,
>+		REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
>+
>+	REG_SET_2(DST_AFTER_SCALER, 0,
>+		REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
>+		DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
>+
>+	REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
>+		REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
>+
>+	/* DLG - Per luma/chroma */
>+	REG_SET(VBLANK_PARAMETERS_1, 0,
>+		REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
>+
>+	if (REG(NOM_PARAMETERS_0))
>+		REG_SET(NOM_PARAMETERS_0, 0,
>+			DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
>+
>+	if (REG(NOM_PARAMETERS_1))
>+		REG_SET(NOM_PARAMETERS_1, 0,
>+			REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
>+
>+	REG_SET(NOM_PARAMETERS_4, 0,
>+		DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
>+
>+	REG_SET(NOM_PARAMETERS_5, 0,
>+		REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
>+
>+	REG_SET_2(PER_LINE_DELIVERY, 0,
>+		REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
>+		REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
>+
>+	REG_SET(VBLANK_PARAMETERS_2, 0,
>+		REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
>+
>+	if (REG(NOM_PARAMETERS_2))
>+		REG_SET(NOM_PARAMETERS_2, 0,
>+			DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
>+
>+	if (REG(NOM_PARAMETERS_3))
>+		REG_SET(NOM_PARAMETERS_3, 0,
>+			REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
>+
>+	REG_SET(NOM_PARAMETERS_6, 0,
>+		DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
>+
>+	REG_SET(NOM_PARAMETERS_7, 0,
>+		REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
>+
>+	/* TTU - per hubp */
>+	REG_SET_2(DCN_TTU_QOS_WM, 0,
>+		QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
>+		QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
>+
>+	/* TTU - per luma/chroma */
>+	/* Assumed surf0 is luma and 1 is chroma */
>+
>+	REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
>+		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
>+		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
>+		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
>+
>+	REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
>+		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
>+		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
>+		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
>+
>+	REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
>+		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
>+		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
>+		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
> 
> 	REG_SET(FLIP_PARAMETERS_1, 0,
> 		REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l);
>@@ -184,6 +187,39 @@
> 	REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);
> }
> 
>+void hubp2_program_requestor(
>+		struct hubp *hubp,
>+		struct _vcs_dpi_display_rq_regs_st *rq_regs)
>+{
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+
>+	REG_UPDATE(HUBPRET_CONTROL,
>+			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
>+	REG_SET_4(DCN_EXPANSION_MODE, 0,
>+			DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
>+			PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
>+			MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
>+			CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
>+	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
>+		CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
>+		MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
>+		META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
>+		MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
>+		DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
>+		MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
>+		SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
>+		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
>+	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
>+		CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
>+		MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
>+		META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
>+		MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
>+		DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
>+		MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
>+		SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
>+		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
>+}
>+
> static void hubp2_setup(
> 		struct hubp *hubp,
> 		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
>@@ -196,7 +232,7 @@
> 	 */
> 
> 	hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
>-	hubp1_program_requestor(hubp, rq_regs);
>+	hubp2_program_requestor(hubp, rq_regs);
> 	hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
> 
> }
>@@ -283,11 +319,205 @@
> 			PIPE_ALIGNED, 0);
> }
> 
>+void hubp2_program_size(
>+	struct hubp *hubp,
>+	enum surface_pixel_format format,
>+	const struct plane_size *plane_size,
>+	struct dc_plane_dcc_param *dcc)
>+{
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+	uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
>+	bool use_pitch_c = false;
>+
>+	/* Program data and meta surface pitch (calculation from addrlib)
>+	 * 444 or 420 luma
>+	 */
>+	use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
>+		&& format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
>+	if (use_pitch_c) {
>+		ASSERT(plane_size->chroma_pitch != 0);
>+		/* Chroma pitch zero can cause system hang! */
>+
>+		pitch = plane_size->surface_pitch - 1;
>+		meta_pitch = dcc->meta_pitch - 1;
>+		pitch_c = plane_size->chroma_pitch - 1;
>+		meta_pitch_c = dcc->meta_pitch_c - 1;
>+	} else {
>+		pitch = plane_size->surface_pitch - 1;
>+		meta_pitch = dcc->meta_pitch - 1;
>+		pitch_c = 0;
>+		meta_pitch_c = 0;
>+	}
>+
>+	if (!dcc->enable) {
>+		meta_pitch = 0;
>+		meta_pitch_c = 0;
>+	}
>+
>+	REG_UPDATE_2(DCSURF_SURFACE_PITCH,
>+			PITCH, pitch, META_PITCH, meta_pitch);
>+
>+	use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN;
>+	if (use_pitch_c)
>+		REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
>+			PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
>+}
>+
>+void hubp2_program_rotation(
>+	struct hubp *hubp,
>+	enum dc_rotation_angle rotation,
>+	bool horizontal_mirror)
>+{
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+	uint32_t mirror;
>+
>+
>+	if (horizontal_mirror)
>+		mirror = 1;
>+	else
>+		mirror = 0;
>+
>+	/* Program rotation angle and horz mirror - no mirror */
>+	if (rotation == ROTATION_ANGLE_0)
>+		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
>+				ROTATION_ANGLE, 0,
>+				H_MIRROR_EN, mirror);
>+	else if (rotation == ROTATION_ANGLE_90)
>+		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
>+				ROTATION_ANGLE, 1,
>+				H_MIRROR_EN, mirror);
>+	else if (rotation == ROTATION_ANGLE_180)
>+		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
>+				ROTATION_ANGLE, 2,
>+				H_MIRROR_EN, mirror);
>+	else if (rotation == ROTATION_ANGLE_270)
>+		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
>+				ROTATION_ANGLE, 3,
>+				H_MIRROR_EN, mirror);
>+}
>+
>+void hubp2_dcc_control(struct hubp *hubp, bool enable,
>+		enum hubp_ind_block_size independent_64b_blks)
>+{
>+	uint32_t dcc_en = enable ? 1 : 0;
>+	uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+
>+	REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
>+			PRIMARY_SURFACE_DCC_EN, dcc_en,
>+			PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
>+			SECONDARY_SURFACE_DCC_EN, dcc_en,
>+			SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
>+}
>+
>+void hubp2_program_pixel_format(
>+	struct hubp *hubp,
>+	enum surface_pixel_format format)
>+{
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+	uint32_t red_bar = 3;
>+	uint32_t blue_bar = 2;
>+
>+	/* swap for ABGR format */
>+	if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
>+			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
>+			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
>+			|| format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
>+		red_bar = 2;
>+		blue_bar = 3;
>+	}
>+
>+	REG_UPDATE_2(HUBPRET_CONTROL,
>+			CROSSBAR_SRC_CB_B, blue_bar,
>+			CROSSBAR_SRC_CR_R, red_bar);
>+
>+	/* Mapping is same as ipp programming (cnvc) */
>+
>+	switch (format)	{
>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 1);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 3);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 8);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 10);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 22);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
>+	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 24);
>+		break;
>+
>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 65);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 64);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 67);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 66);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 12);
>+		break;
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>+	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 112);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 113);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 114);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 118);
>+		break;
>+	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
>+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
>+				SURFACE_PIXEL_FORMAT, 119);
>+		break;
>+#endif
>+	default:
>+		BREAK_TO_DEBUGGER();
>+		break;
>+	}
>+
>+	/* don't see the need of program the xbar in DCN 1.0 */
>+}
>+
> void hubp2_program_surface_config(
> 	struct hubp *hubp,
> 	enum surface_pixel_format format,
> 	union dc_tiling_info *tiling_info,
>-	union plane_size *plane_size,
>+	struct plane_size *plane_size,
> 	enum dc_rotation_angle rotation,
> 	struct dc_plane_dcc_param *dcc,
> 	bool horizontal_mirror,
>@@ -295,11 +525,11 @@
> {
> 	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
> 
>-	hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
>+	hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
> 	hubp2_program_tiling(hubp2, tiling_info, format);
>-	hubp1_program_size(hubp, format, plane_size, dcc);
>-	hubp1_program_rotation(hubp, rotation, horizontal_mirror);
>-	hubp1_program_pixel_format(hubp, format);
>+	hubp2_program_size(hubp, format, plane_size, dcc);
>+	hubp2_program_rotation(hubp, rotation, horizontal_mirror);
>+	hubp2_program_pixel_format(hubp, format);
> }
> 
> enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(
>@@ -652,28 +882,388 @@
> 	REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0);
> }
> 
>+bool hubp2_is_flip_pending(struct hubp *hubp)
>+{
>+	uint32_t flip_pending = 0;
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+	struct dc_plane_address earliest_inuse_address;
>+
>+	REG_GET(DCSURF_FLIP_CONTROL,
>+			SURFACE_FLIP_PENDING, &flip_pending);
>+
>+	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
>+			SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
>+
>+	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
>+			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
>+
>+	if (flip_pending)
>+		return true;
>+
>+	if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
>+		return true;
>+
>+	return false;
>+}
>+
>+void hubp2_set_blank(struct hubp *hubp, bool blank)
>+{
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+	uint32_t blank_en = blank ? 1 : 0;
>+
>+	REG_UPDATE_2(DCHUBP_CNTL,
>+			HUBP_BLANK_EN, blank_en,
>+			HUBP_TTU_DISABLE, blank_en);
>+
>+	if (blank) {
>+		uint32_t reg_val = REG_READ(DCHUBP_CNTL);
>+
>+		if (reg_val) {
>+			/* init sequence workaround: in case HUBP is
>+			 * power gated, this wait would timeout.
>+			 *
>+			 * we just wrote reg_val to non-0, if it stay 0
>+			 * it means HUBP is gated
>+			 */
>+			REG_WAIT(DCHUBP_CNTL,
>+					HUBP_NO_OUTSTANDING_REQ, 1,
>+					1, 200);
>+		}
>+
>+		hubp->mpcc_id = 0xf;
>+		hubp->opp_id = OPP_ID_INVALID;
>+	}
>+}
>+
>+void hubp2_cursor_set_position(
>+		struct hubp *hubp,
>+		const struct dc_cursor_position *pos,
>+		const struct dc_cursor_mi_param *param)
>+{
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+	int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
>+	int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
>+	int x_hotspot = pos->x_hotspot;
>+	int y_hotspot = pos->y_hotspot;
>+	int cursor_height = (int)hubp->curs_attr.height;
>+	int cursor_width = (int)hubp->curs_attr.width;
>+	uint32_t dst_x_offset;
>+	uint32_t cur_en = pos->enable ? 1 : 0;
>+
>+	/*
>+	 * Guard aganst cursor_set_position() from being called with invalid
>+	 * attributes
>+	 *
>+	 * TODO: Look at combining cursor_set_position() and
>+	 * cursor_set_attributes() into cursor_update()
>+	 */
>+	if (hubp->curs_attr.address.quad_part == 0)
>+		return;
>+
>+	// Rotated cursor width/height and hotspots tweaks for offset calculation
>+	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
>+		swap(cursor_height, cursor_width);
>+		if (param->rotation == ROTATION_ANGLE_90) {
>+			src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
>+			src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
>+		}
>+	} else if (param->rotation == ROTATION_ANGLE_180) {
>+		src_x_offset = pos->x - param->viewport.x;
>+		src_y_offset = pos->y - param->viewport.y;
>+	}
>+
>+	if (param->mirror) {
>+		x_hotspot = param->viewport.width - x_hotspot;
>+		src_x_offset = param->viewport.x + param->viewport.width - src_x_offset;
>+	}
>+
>+	dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
>+	dst_x_offset *= param->ref_clk_khz;
>+	dst_x_offset /= param->pixel_clk_khz;
>+
>+	ASSERT(param->h_scale_ratio.value);
>+
>+	if (param->h_scale_ratio.value)
>+		dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
>+				dc_fixpt_from_int(dst_x_offset),
>+				param->h_scale_ratio));
>+
>+	if (src_x_offset >= (int)param->viewport.width)
>+		cur_en = 0;  /* not visible beyond right edge*/
>+
>+	if (src_x_offset + cursor_width <= 0)
>+		cur_en = 0;  /* not visible beyond left edge*/
>+
>+	if (src_y_offset >= (int)param->viewport.height)
>+		cur_en = 0;  /* not visible beyond bottom edge*/
>+
>+	if (src_y_offset + cursor_height <= 0)
>+		cur_en = 0;  /* not visible beyond top edge*/
>+
>+	if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
>+		hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
>+
>+	REG_UPDATE(CURSOR_CONTROL,
>+			CURSOR_ENABLE, cur_en);
>+
>+	REG_SET_2(CURSOR_POSITION, 0,
>+			CURSOR_X_POSITION, pos->x,
>+			CURSOR_Y_POSITION, pos->y);
>+
>+	REG_SET_2(CURSOR_HOT_SPOT, 0,
>+			CURSOR_HOT_SPOT_X, x_hotspot,
>+			CURSOR_HOT_SPOT_Y, y_hotspot);
>+
>+	REG_SET(CURSOR_DST_OFFSET, 0,
>+			CURSOR_DST_X_OFFSET, dst_x_offset);
>+	/* TODO Handle surface pixel formats other than 4:4:4 */
>+}
>+
>+void hubp2_clk_cntl(struct hubp *hubp, bool enable)
>+{
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+	uint32_t clk_enable = enable ? 1 : 0;
>+
>+	REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
>+}
>+
>+void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
>+{
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+
>+	REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
>+}
>+
>+void hubp2_clear_underflow(struct hubp *hubp)
>+{
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+
>+	REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
>+}
>+
>+void hubp2_read_state_common(struct hubp *hubp)
>+{
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+	struct dcn_hubp_state *s = &hubp2->state;
>+	struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
>+	struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
>+	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
>+
>+	/* Requester */
>+	REG_GET(HUBPRET_CONTROL,
>+			DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
>+	REG_GET_4(DCN_EXPANSION_MODE,
>+			DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
>+			PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
>+			MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
>+			CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
>+
>+	/* DLG - Per hubp */
>+	REG_GET_2(BLANK_OFFSET_0,
>+		REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
>+		DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
>+
>+	REG_GET(BLANK_OFFSET_1,
>+		MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
>+
>+	REG_GET(DST_DIMENSIONS,
>+		REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
>+
>+	REG_GET_2(DST_AFTER_SCALER,
>+		REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
>+		DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
>+
>+	if (REG(PREFETCH_SETTINS))
>+		REG_GET_2(PREFETCH_SETTINS,
>+			DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
>+			VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
>+	else
>+		REG_GET_2(PREFETCH_SETTINGS,
>+			DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
>+			VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
>+
>+	REG_GET_2(VBLANK_PARAMETERS_0,
>+		DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
>+		DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
>+
>+	REG_GET(REF_FREQ_TO_PIX_FREQ,
>+		REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
>+
>+	/* DLG - Per luma/chroma */
>+	REG_GET(VBLANK_PARAMETERS_1,
>+		REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
>+
>+	REG_GET(VBLANK_PARAMETERS_3,
>+		REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
>+
>+	if (REG(NOM_PARAMETERS_0))
>+		REG_GET(NOM_PARAMETERS_0,
>+			DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
>+
>+	if (REG(NOM_PARAMETERS_1))
>+		REG_GET(NOM_PARAMETERS_1,
>+			REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
>+
>+	REG_GET(NOM_PARAMETERS_4,
>+		DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
>+
>+	REG_GET(NOM_PARAMETERS_5,
>+		REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
>+
>+	REG_GET_2(PER_LINE_DELIVERY_PRE,
>+		REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
>+		REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
>+
>+	REG_GET_2(PER_LINE_DELIVERY,
>+		REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
>+		REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
>+
>+	if (REG(PREFETCH_SETTINS_C))
>+		REG_GET(PREFETCH_SETTINS_C,
>+			VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
>+	else
>+		REG_GET(PREFETCH_SETTINGS_C,
>+			VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
>+
>+	REG_GET(VBLANK_PARAMETERS_2,
>+		REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
>+
>+	REG_GET(VBLANK_PARAMETERS_4,
>+		REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
>+
>+	if (REG(NOM_PARAMETERS_2))
>+		REG_GET(NOM_PARAMETERS_2,
>+			DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
>+
>+	if (REG(NOM_PARAMETERS_3))
>+		REG_GET(NOM_PARAMETERS_3,
>+			REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
>+
>+	REG_GET(NOM_PARAMETERS_6,
>+		DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
>+
>+	REG_GET(NOM_PARAMETERS_7,
>+		REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
>+
>+	/* TTU - per hubp */
>+	REG_GET_2(DCN_TTU_QOS_WM,
>+		QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
>+		QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
>+
>+	REG_GET_2(DCN_GLOBAL_TTU_CNTL,
>+		MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
>+		QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
>+
>+	/* TTU - per luma/chroma */
>+	/* Assumed surf0 is luma and 1 is chroma */
>+
>+	REG_GET_3(DCN_SURF0_TTU_CNTL0,
>+		REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
>+		QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
>+		QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
>+
>+	REG_GET(DCN_SURF0_TTU_CNTL1,
>+		REFCYC_PER_REQ_DELIVERY_PRE,
>+		&ttu_attr->refcyc_per_req_delivery_pre_l);
>+
>+	REG_GET_3(DCN_SURF1_TTU_CNTL0,
>+		REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
>+		QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
>+		QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
>+
>+	REG_GET(DCN_SURF1_TTU_CNTL1,
>+		REFCYC_PER_REQ_DELIVERY_PRE,
>+		&ttu_attr->refcyc_per_req_delivery_pre_c);
>+
>+	/* Rest of hubp */
>+	REG_GET(DCSURF_SURFACE_CONFIG,
>+			SURFACE_PIXEL_FORMAT, &s->pixel_format);
>+
>+	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
>+			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
>+
>+	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
>+			SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
>+
>+	REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
>+			PRI_VIEWPORT_WIDTH, &s->viewport_width,
>+			PRI_VIEWPORT_HEIGHT, &s->viewport_height);
>+
>+	REG_GET_2(DCSURF_SURFACE_CONFIG,
>+			ROTATION_ANGLE, &s->rotation_angle,
>+			H_MIRROR_EN, &s->h_mirror_en);
>+
>+	REG_GET(DCSURF_TILING_CONFIG,
>+			SW_MODE, &s->sw_mode);
>+
>+	REG_GET(DCSURF_SURFACE_CONTROL,
>+			PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
>+
>+	REG_GET_3(DCHUBP_CNTL,
>+			HUBP_BLANK_EN, &s->blank_en,
>+			HUBP_TTU_DISABLE, &s->ttu_disable,
>+			HUBP_UNDERFLOW_STATUS, &s->underflow_status);
>+
>+	REG_GET(DCN_GLOBAL_TTU_CNTL,
>+			MIN_TTU_VBLANK, &s->min_ttu_vblank);
>+
>+	REG_GET_2(DCN_TTU_QOS_WM,
>+			QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
>+			QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
>+
>+}
>+
>+void hubp2_read_state(struct hubp *hubp)
>+{
>+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
>+	struct dcn_hubp_state *s = &hubp2->state;
>+	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
>+
>+	hubp2_read_state_common(hubp);
>+
>+	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
>+		CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
>+		MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
>+		META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
>+		MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
>+		DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
>+		MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
>+		SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
>+		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
>+
>+	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
>+		CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
>+		MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
>+		META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
>+		MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
>+		DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
>+		MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
>+		SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
>+		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
>+
>+}
>+
> static struct hubp_funcs dcn20_hubp_funcs = {
> 	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
> 	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
> 	.hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
> 	.hubp_program_surface_config = hubp2_program_surface_config,
>-	.hubp_is_flip_pending = hubp1_is_flip_pending,
>+	.hubp_is_flip_pending = hubp2_is_flip_pending,
> 	.hubp_setup = hubp2_setup,
> 	.hubp_setup_interdependent = hubp2_setup_interdependent,
> 	.hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings,
>-	.set_blank = hubp1_set_blank,
>-	.dcc_control = hubp1_dcc_control,
>-	.hubp_update_dchub = hubp2_update_dchub,
>+	.set_blank = hubp2_set_blank,
>+	.dcc_control = hubp2_dcc_control,
> 	.mem_program_viewport = min_set_viewport,
> 	.set_cursor_attributes	= hubp2_cursor_set_attributes,
>-	.set_cursor_position	= hubp1_cursor_set_position,
>-	.hubp_clk_cntl = hubp1_clk_cntl,
>-	.hubp_vtg_sel = hubp1_vtg_sel,
>+	.set_cursor_position	= hubp2_cursor_set_position,
>+	.hubp_clk_cntl = hubp2_clk_cntl,
>+	.hubp_vtg_sel = hubp2_vtg_sel,
> 	.dmdata_set_attributes = hubp2_dmdata_set_attributes,
> 	.dmdata_load = hubp2_dmdata_load,
> 	.dmdata_status_done = hubp2_dmdata_status_done,
>-	.hubp_read_state = hubp1_read_state,
>-	.hubp_clear_underflow = hubp1_clear_underflow,
>+	.hubp_read_state = hubp2_read_state,
>+	.hubp_clear_underflow = hubp2_clear_underflow,
> 	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
> 	.hubp_init = hubp1_init,
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h	2019-08-31 15:01:11.865736169 -0500
>@@ -38,12 +38,6 @@
> 	SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\
> 	SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\
> 	SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\
>-	SR(DCN_VM_FB_LOCATION_TOP),\
>-	SR(DCN_VM_FB_LOCATION_BASE),\
>-	SR(DCN_VM_FB_OFFSET),\
>-	SR(DCN_VM_AGP_BASE),\
>-	SR(DCN_VM_AGP_BOT),\
>-	SR(DCN_VM_AGP_TOP),\
> 	SRI(CURSOR_SETTINGS, HUBPREQ, id), \
> 	SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
> 	SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
>@@ -72,8 +66,8 @@
> 	SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\
> 	SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)
> 
>-#define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\
>-	HUBP_MASK_SH_LIST_DCN(mask_sh),\
>+#define HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh)\
>+	HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
> 	HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
> 	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
> 	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
>@@ -82,12 +76,6 @@
> 	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
> 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
> 	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
>-	HUBP_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh),\
>-	HUBP_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh),\
>-	HUBP_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh),\
>-	HUBP_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh),\
>-	HUBP_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh),\
>-	HUBP_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh),\
> 	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
> 	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
> 	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
>@@ -127,13 +115,21 @@
> 	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
> 	HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh)
> 
>+/*DCN2.x and DCN1.x*/
>+#define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\
>+	HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh),\
>+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\
>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\
>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh)
>+
>+/*DCN2.0 specific*/
> #define HUBP_MASK_SH_LIST_DCN20(mask_sh)\
> 	HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\
> 	HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\
> 	HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\
> 	HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh)
> 
>-
>+/*DCN2.x */
> #define DCN2_HUBP_REG_COMMON_VARIABLE_LIST \
> 	HUBP_COMMON_REG_VARIABLE_LIST; \
> 	uint32_t DMDATA_ADDRESS_HIGH; \
>@@ -149,14 +145,22 @@
> 	uint32_t FLIP_PARAMETERS_2;\
> 	uint32_t DCN_CUR1_TTU_CNTL0;\
> 	uint32_t DCN_CUR1_TTU_CNTL1;\
>-	uint32_t VMID_SETTINGS_0;\
>+	uint32_t VMID_SETTINGS_0
>+
>+
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+#define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \
>+	DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \
> 	uint32_t FLIP_PARAMETERS_3;\
> 	uint32_t FLIP_PARAMETERS_4;\
>+	uint32_t FLIP_PARAMETERS_5;\
>+	uint32_t FLIP_PARAMETERS_6;\
> 	uint32_t VBLANK_PARAMETERS_5;\
> 	uint32_t VBLANK_PARAMETERS_6
>+#endif
> 
> #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \
>-	DCN_HUBP_REG_FIELD_LIST(type); \
>+	DCN_HUBP_REG_FIELD_BASE_LIST(type); \
> 	type DMDATA_ADDRESS_HIGH;\
> 	type DMDATA_MODE;\
> 	type DMDATA_UPDATED;\
>@@ -180,17 +184,41 @@
> 	type SURFACE_TRIPLE_BUFFER_ENABLE;\
> 	type VMID
> 
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+#define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \
>+	DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\
>+	type REFCYC_PER_VM_GROUP_FLIP;\
>+	type REFCYC_PER_VM_REQ_FLIP;\
>+	type REFCYC_PER_VM_GROUP_VBLANK;\
>+	type REFCYC_PER_VM_REQ_VBLANK;\
>+	type REFCYC_PER_PTE_GROUP_FLIP_C; \
>+	type REFCYC_PER_META_CHUNK_FLIP_C; \
>+	type VM_GROUP_SIZE
>+#endif
>+
> 
> struct dcn_hubp2_registers {
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	DCN21_HUBP_REG_COMMON_VARIABLE_LIST;
>+#else
> 	DCN2_HUBP_REG_COMMON_VARIABLE_LIST;
>+#endif
> };
> 
> struct dcn_hubp2_shift {
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
>+#else
> 	DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
>+#endif
> };
> 
> struct dcn_hubp2_mask {
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	DCN21_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
>+#else
> 	DCN2_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
>+#endif
> };
> 
> struct dcn20_hubp {
>@@ -217,10 +245,6 @@
> void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
> 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
> 
>-void hubp2_update_dchub(
>-		struct hubp *hubp,
>-		struct dchub_init_data *dh_data);
>-
> void hubp2_cursor_set_attributes(
> 		struct hubp *hubp,
> 		const struct dc_cursor_attributes *attr);
>@@ -262,16 +286,53 @@
> 	const struct dc_plane_address *address,
> 	bool flip_immediate);
> 
>+void hubp2_dcc_control(struct hubp *hubp, bool enable,
>+		enum hubp_ind_block_size independent_64b_blks);
>+
>+void hubp2_program_size(
>+	struct hubp *hubp,
>+	enum surface_pixel_format format,
>+	const struct plane_size *plane_size,
>+	struct dc_plane_dcc_param *dcc);
>+
>+void hubp2_program_rotation(
>+	struct hubp *hubp,
>+	enum dc_rotation_angle rotation,
>+	bool horizontal_mirror);
>+
>+void hubp2_program_pixel_format(
>+	struct hubp *hubp,
>+	enum surface_pixel_format format);
>+
> void hubp2_program_surface_config(
> 	struct hubp *hubp,
> 	enum surface_pixel_format format,
> 	union dc_tiling_info *tiling_info,
>-	union plane_size *plane_size,
>+	struct plane_size *plane_size,
> 	enum dc_rotation_angle rotation,
> 	struct dc_plane_dcc_param *dcc,
> 	bool horizontal_mirror,
> 	unsigned int compat_level);
> 
>+bool hubp2_is_flip_pending(struct hubp *hubp);
>+
>+void hubp2_set_blank(struct hubp *hubp, bool blank);
>+
>+void hubp2_cursor_set_position(
>+		struct hubp *hubp,
>+		const struct dc_cursor_position *pos,
>+		const struct dc_cursor_mi_param *param);
>+
>+void hubp2_clk_cntl(struct hubp *hubp, bool enable);
>+
>+void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst);
>+
>+void hubp2_clear_underflow(struct hubp *hubp);
>+
>+void hubp2_read_state_common(struct hubp *hubp);
>+
>+void hubp2_read_state(struct hubp *hubp);
>+
> #endif /* __DC_MEM_INPUT_DCN20_H__ */
> 
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c	2019-08-31 15:01:11.865736169 -0500
>@@ -64,23 +64,7 @@
> #define FN(reg_name, field_name) \
> 	hws->shifts->field_name, hws->masks->field_name
> 
>-static void bios_golden_init(struct dc *dc)
>-{
>-	struct dc_bios *bp = dc->ctx->dc_bios;
>-	int i;
>-
>-	/* initialize dcn global */
>-	bp->funcs->enable_disp_power_gating(bp,
>-			CONTROLLER_ID_D0, ASIC_PIPE_INIT);
>-
>-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
>-		/* initialize dcn per pipe */
>-		bp->funcs->enable_disp_power_gating(bp,
>-				CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
>-	}
>-}
>-
>-static void enable_power_gating_plane(
>+static void dcn20_enable_power_gating_plane(
> 	struct dce_hwseq *hws,
> 	bool enable)
> {
>@@ -94,28 +78,34 @@
> 	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
> 	REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
> 	REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
>-	REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
>-	/*Do not power gate DCHUB5, should be left at HW default, power on permanently*/
>-	/*REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, force_on);*/
>+	if (REG(DOMAIN8_PG_CONFIG))
>+		REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
>+	if (REG(DOMAIN10_PG_CONFIG))
>+		REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
> 
> 	/* DPP0/1/2/3/4/5 */
> 	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
> 	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
> 	REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
> 	REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
>-	REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
>-	/*Do not power gate DPP5, should be left at HW default, power on permanently*/
>-	/*REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, force_on);*/
>+	if (REG(DOMAIN9_PG_CONFIG))
>+		REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
>+	if (REG(DOMAIN11_PG_CONFIG))
>+		REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
> 
>+	/* DCS0/1/2/3/4/5 */
> 	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
> 	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
> 	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
>-	REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
>-	REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
>-	REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
>+	if (REG(DOMAIN19_PG_CONFIG))
>+		REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
>+	if (REG(DOMAIN20_PG_CONFIG))
>+		REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
>+	if (REG(DOMAIN21_PG_CONFIG))
>+		REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
> }
> 
>-static void dcn20_dccg_init(struct dce_hwseq *hws)
>+void dcn20_dccg_init(struct dce_hwseq *hws)
> {
> 	/*
> 	 * set MICROSECOND_TIME_BASE_DIV
>@@ -138,8 +128,46 @@
> 	/* This value is dependent on the hardware pipeline delay so set once per SOC */
> 	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
> }
>+void dcn20_display_init(struct dc *dc)
>+{
>+	struct dce_hwseq *hws = dc->hwseq;
>+
>+	/* RBBMIF
>+	 * disable RBBMIF timeout detection for all clients
>+	 * Ensure RBBMIF does not drop register accesses due to the per-client timeout
>+	 */
>+	REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
>+	REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
> 
>-static void disable_vga(
>+	/* DCCG */
>+	dcn20_dccg_init(hws);
>+
>+	REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 0);
>+
>+	/* DCHUB/MMHUBBUB
>+	 * set global timer refclk divider
>+	 * 100Mhz refclk -> 2
>+	 * 27Mhz refclk ->  1
>+	 * 48Mhz refclk ->  1
>+	 */
>+	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
>+	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
>+	REG_WRITE(REFCLK_CNTL, 0);
>+
>+	/* OPTC
>+	 * OTG_CONTROL.OTG_DISABLE_POINT_CNTL = 0x3; will be set during optc2_enable_crtc
>+	 */
>+
>+	/* AZ
>+	 * default value is 0x64 for 100Mhz ref clock, if the ref clock is 100Mhz, no need to program this regiser,
>+	 * if not, it should be programmed according to the ref clock
>+	 */
>+	REG_UPDATE(AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, 0x64);
>+	/* Enable controller clock gating */
>+	REG_WRITE(AZALIA_CONTROLLER_CLOCK_GATING, 0x1);
>+}
>+
>+void dcn20_disable_vga(
> 	struct dce_hwseq *hws)
> {
> 	REG_WRITE(D1VGA_CONTROL, 0);
>@@ -163,7 +191,7 @@
> }
> 
> /* Blank pixel data during initialization */
>-static void dcn20_init_blank(
>+void dcn20_init_blank(
> 		struct dc *dc,
> 		struct timing_generator *tg)
> {
>@@ -442,29 +470,6 @@
> }
> 
> 
>-
>-static void dcn20_plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
>-{
>-	struct dce_hwseq *hws = dc->hwseq;
>-	struct dpp *dpp = pipe_ctx->plane_res.dpp;
>-
>-	DC_LOGGER_INIT(dc->ctx->logger);
>-
>-	if (REG(DC_IP_REQUEST_CNTL)) {
>-		REG_SET(DC_IP_REQUEST_CNTL, 0,
>-				IP_REQUEST_EN, 1);
>-		dcn20_dpp_pg_control(hws, dpp->inst, false);
>-		dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, false);
>-		dpp->funcs->dpp_reset(dpp);
>-		REG_SET(DC_IP_REQUEST_CNTL, 0,
>-				IP_REQUEST_EN, 0);
>-		DC_LOG_DEBUG(
>-				"Power gated front end %d\n", pipe_ctx->pipe_idx);
>-	}
>-}
>-
>-
>-
> /* disable HW used by plane.
>  * note:  cannot disable until disconnect is complete
>  */
>@@ -490,7 +495,9 @@
> 	hubp->power_gated = true;
> 	dc->optimized_required = false; /* We're powering off, no need to optimize */
> 
>-	dcn20_plane_atomic_power_down(dc, pipe_ctx);
>+	dc->hwss.plane_atomic_power_down(dc,
>+			pipe_ctx->plane_res.dpp,
>+			pipe_ctx->plane_res.hubp);
> 
> 	pipe_ctx->stream = NULL;
> 	memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
>@@ -514,199 +521,6 @@
> 					pipe_ctx->pipe_idx);
> }
> 
>-static void dcn20_init_hw(struct dc *dc)
>-{
>-	int i, j;
>-	struct abm *abm = dc->res_pool->abm;
>-	struct dmcu *dmcu = dc->res_pool->dmcu;
>-	struct dce_hwseq *hws = dc->hwseq;
>-	struct dc_bios *dcb = dc->ctx->dc_bios;
>-	struct resource_pool *res_pool = dc->res_pool;
>-	struct dc_state  *context = dc->current_state;
>-	struct dc_firmware_info fw_info = { { 0 } };
>-
>-	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
>-		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
>-
>-	// Initialize the dccg
>-	if (res_pool->dccg->funcs->dccg_init)
>-		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
>-
>-	//Enable ability to power gate / don't force power on permanently
>-	enable_power_gating_plane(dc->hwseq, true);
>-
>-	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
>-		REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
>-		REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
>-
>-		dcn20_dccg_init(hws);
>-
>-		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
>-		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
>-		REG_WRITE(REFCLK_CNTL, 0);
>-	} else {
>-		if (!dcb->funcs->is_accelerated_mode(dcb)) {
>-			bios_golden_init(dc);
>-			if (dc->ctx->dc_bios->funcs->get_firmware_info(
>-					dc->ctx->dc_bios, &fw_info) == BP_RESULT_OK) {
>-				res_pool->ref_clocks.xtalin_clock_inKhz = fw_info.pll_info.crystal_frequency;
>-
>-				if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
>-					if (res_pool->dccg && res_pool->hubbub) {
>-
>-						(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
>-								fw_info.pll_info.crystal_frequency,
>-								&res_pool->ref_clocks.dccg_ref_clock_inKhz);
>-
>-						(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
>-								res_pool->ref_clocks.dccg_ref_clock_inKhz,
>-								&res_pool->ref_clocks.dchub_ref_clock_inKhz);
>-					} else {
>-						// Not all ASICs have DCCG sw component
>-						res_pool->ref_clocks.dccg_ref_clock_inKhz =
>-								res_pool->ref_clocks.xtalin_clock_inKhz;
>-						res_pool->ref_clocks.dchub_ref_clock_inKhz =
>-								res_pool->ref_clocks.xtalin_clock_inKhz;
>-					}
>-				}
>-			} else
>-				ASSERT_CRITICAL(false);
>-			disable_vga(dc->hwseq);
>-		}
>-
>-		for (i = 0; i < dc->link_count; i++) {
>-			/* Power up AND update implementation according to the
>-			 * required signal (which may be different from the
>-			 * default signal on connector).
>-			 */
>-			struct dc_link *link = dc->links[i];
>-
>-			link->link_enc->funcs->hw_init(link->link_enc);
>-		}
>-	}
>-
>-	/* Blank pixel data with OPP DPG */
>-	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
>-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
>-
>-		if (tg->funcs->is_tg_enabled(tg)) {
>-			dcn20_init_blank(dc, tg);
>-		}
>-	}
>-
>-	for (i = 0; i < res_pool->timing_generator_count; i++) {
>-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
>-
>-		if (tg->funcs->is_tg_enabled(tg))
>-			tg->funcs->lock(tg);
>-	}
>-
>-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
>-		struct dpp *dpp = res_pool->dpps[i];
>-
>-		dpp->funcs->dpp_reset(dpp);
>-	}
>-
>-	/* Reset all MPCC muxes */
>-	res_pool->mpc->funcs->mpc_init(res_pool->mpc);
>-
>-	/* initialize OPP mpc_tree parameter */
>-	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
>-		res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
>-		res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
>-		for (j = 0; j < MAX_PIPES; j++)
>-			res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
>-	}
>-
>-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
>-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
>-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
>-		struct hubp *hubp = dc->res_pool->hubps[i];
>-		struct dpp *dpp = dc->res_pool->dpps[i];
>-
>-		pipe_ctx->stream_res.tg = tg;
>-		pipe_ctx->pipe_idx = i;
>-
>-		pipe_ctx->plane_res.hubp = hubp;
>-		pipe_ctx->plane_res.dpp = dpp;
>-		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
>-		hubp->mpcc_id = dpp->inst;
>-		hubp->opp_id = OPP_ID_INVALID;
>-		hubp->power_gated = false;
>-		pipe_ctx->stream_res.opp = NULL;
>-
>-		hubp->funcs->hubp_init(hubp);
>-
>-		//dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
>-		//dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
>-		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
>-		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
>-		/*to do*/
>-		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
>-	}
>-
>-	/* initialize DWB pointer to MCIF_WB */
>-	for (i = 0; i < res_pool->res_cap->num_dwb; i++)
>-		res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
>-
>-	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
>-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
>-
>-		if (tg->funcs->is_tg_enabled(tg))
>-			tg->funcs->unlock(tg);
>-	}
>-
>-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
>-		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
>-
>-		dc->hwss.disable_plane(dc, pipe_ctx);
>-
>-		pipe_ctx->stream_res.tg = NULL;
>-		pipe_ctx->plane_res.hubp = NULL;
>-	}
>-
>-	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
>-		struct timing_generator *tg = dc->res_pool->timing_generators[i];
>-
>-		tg->funcs->tg_init(tg);
>-	}
>-
>-	/* end of FPGA. Below if real ASIC */
>-	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
>-		return;
>-
>-
>-	for (i = 0; i < res_pool->audio_count; i++) {
>-		struct audio *audio = res_pool->audios[i];
>-
>-		audio->funcs->hw_init(audio);
>-	}
>-
>-	if (abm != NULL) {
>-		abm->funcs->init_backlight(abm);
>-		abm->funcs->abm_init(abm);
>-	}
>-
>-	if (dmcu != NULL)
>-		dmcu->funcs->dmcu_init(dmcu);
>-
>-	if (abm != NULL && dmcu != NULL)
>-		abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
>-
>-	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
>-	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
>-
>-	if (!dc->debug.disable_clock_gate) {
>-		/* enable all DCN clock gating */
>-		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
>-
>-		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
>-
>-		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
>-	}
>-
>-}
>-
> enum dc_status dcn20_enable_stream_timing(
> 		struct pipe_ctx *pipe_ctx,
> 		struct dc_state *context,
>@@ -715,11 +529,9 @@
> 	struct dc_stream_state *stream = pipe_ctx->stream;
> 	struct drr_params params = {0};
> 	unsigned int event_triggers = 0;
>-
>-
>-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>-	struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
>-#endif
>+	struct pipe_ctx *odm_pipe;
>+	int opp_cnt = 1;
>+	int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
> 
> 	/* by upper caller loop, pipe0 is parent pipe and be called first.
> 	 * back end is set up by for pipe0. Other children pipe share back end
>@@ -730,12 +542,17 @@
> 
> 	/* TODO check if timing_changed, disable stream if timing changed */
> 
>-	if (odm_pipe)
>+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
>+		opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
>+		opp_cnt++;
>+	}
>+
>+	if (opp_cnt > 1)
> 		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
> 				pipe_ctx->stream_res.tg,
>-				odm_pipe->stream_res.opp->inst,
>-				pipe_ctx->stream->timing.h_addressable/2,
>-				pipe_ctx->stream->timing.pixel_encoding);
>+				opp_inst, opp_cnt,
>+				&pipe_ctx->stream->timing);
>+
> 	/* HW program guide assume display already disable
> 	 * by unplug sequence. OTG assume stop.
> 	 */
>@@ -759,11 +576,7 @@
> 			pipe_ctx->stream->signal,
> 			true);
> 
>-	if (pipe_ctx->stream_res.tg->funcs->setup_global_lock)
>-		pipe_ctx->stream_res.tg->funcs->setup_global_lock(
>-				pipe_ctx->stream_res.tg);
>-
>-	if (odm_pipe)
>+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
> 		odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
> 				odm_pipe->stream_res.opp,
> 				true);
>@@ -784,6 +597,8 @@
> 
> 	params.vertical_total_min = stream->adjust.v_total_min;
> 	params.vertical_total_max = stream->adjust.v_total_max;
>+	params.vertical_total_mid = stream->adjust.v_total_mid;
>+	params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
> 	if (pipe_ctx->stream_res.tg->funcs->set_drr)
> 		pipe_ctx->stream_res.tg->funcs->set_drr(
> 			pipe_ctx->stream_res.tg, &params);
>@@ -814,6 +629,10 @@
> {
> 	struct mpc *mpc = dc->res_pool->mpc;
> 	enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
>+	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
>+
>+	if (mpc->funcs->power_on_mpc_mem_pwr)
>+		mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
> 
> 	if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
> 		if (mpc->funcs->set_output_csc != NULL)
>@@ -843,7 +662,9 @@
> 	 * if programming for all pipes is required then remove condition
> 	 * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
> 	 */
>-	if ((pipe_ctx->top_pipe == NULL || dc_res_is_odm_head_pipe(pipe_ctx))
>+	if (mpc->funcs->power_on_mpc_mem_pwr)
>+		mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
>+	if (pipe_ctx->top_pipe == NULL
> 			&& mpc->funcs->set_output_gamma && stream->out_transfer_func) {
> 		if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
> 			params = &stream->out_transfer_func->pwl;
>@@ -909,14 +730,14 @@
> 
> 	result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
> 	if (plane_state->lut3d_func &&
>-		plane_state->lut3d_func->initialized == true)
>+		plane_state->lut3d_func->state.bits.initialized == 1)
> 		result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
> 								&plane_state->lut3d_func->lut_3d);
> 	else
> 		result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
> 
> 	if (plane_state->lut3d_func &&
>-		plane_state->lut3d_func->initialized == true &&
>+		plane_state->lut3d_func->state.bits.initialized == 1 &&
> 		plane_state->lut3d_func->hdr_multiplier != 0)
> 		dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base,
> 				plane_state->lut3d_func->hdr_multiplier);
>@@ -1005,14 +826,20 @@
> 
> static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
> {
>-	struct pipe_ctx *combine_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
>+	struct pipe_ctx *odm_pipe;
>+	int opp_cnt = 1;
>+	int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
> 
>-	if (combine_pipe)
>+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
>+		opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
>+		opp_cnt++;
>+	}
>+
>+	if (opp_cnt > 1)
> 		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
> 				pipe_ctx->stream_res.tg,
>-				combine_pipe->stream_res.opp->inst,
>-				pipe_ctx->plane_res.scl_data.h_active,
>-				pipe_ctx->stream->timing.pixel_encoding);
>+				opp_inst, opp_cnt,
>+				&pipe_ctx->stream->timing);
> 	else
> 		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
> 				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
>@@ -1028,7 +855,8 @@
> 	struct dc_stream_state *stream = pipe_ctx->stream;
> 	enum dc_color_space color_space = stream->output_color_space;
> 	enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
>-	struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
>+	struct pipe_ctx *odm_pipe;
>+	int odm_cnt = 1;
> 
> 	int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
> 	int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
>@@ -1036,8 +864,10 @@
> 	/* get opp dpg blank color */
> 	color_space_to_black_color(dc, color_space, &black_color);
> 
>-	if (bot_odm_pipe)
>-		width = width / 2;
>+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
>+		odm_cnt++;
>+
>+	width = width / odm_cnt;
> 
> 	if (blank) {
> 		if (stream_res->abm)
>@@ -1057,10 +887,10 @@
> 			width,
> 			height);
> 
>-	if (bot_odm_pipe) {
>-		bot_odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
>-				bot_odm_pipe->stream_res.opp,
>-				dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE ?
>+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
>+		odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
>+				odm_pipe->stream_res.opp,
>+				dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
> 						CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
> 				stream->timing.display_color_depth,
> 				&black_color,
>@@ -1106,6 +936,9 @@
> 	/* enable DCFCLK current DCHUB */
> 	pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
> 
>+	/* initialize HUBP on power up */
>+	pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
>+
> 	/* make sure OPP_PIPE_CLOCK_EN = 1 */
> 	pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
> 			pipe_ctx->stream_res.opp,
>@@ -1201,7 +1034,7 @@
> 		struct pipe_ctx *pipe_ctx,
> 		struct dc_state *context)
> {
>-	if (pipe_ctx->top_pipe == NULL) {
>+	if (pipe_ctx->top_pipe == NULL && !pipe_ctx->prev_odm_pipe) {
> 		bool blank = !is_pipe_tree_visible(pipe_ctx);
> 
> 		pipe_ctx->stream_res.tg->funcs->program_global_sync(
>@@ -1223,8 +1056,13 @@
> 	if (pipe_ctx->plane_state != NULL)
> 		dcn20_program_pipe(dc, pipe_ctx, context);
> 
>-	if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
>+	if (pipe_ctx->bottom_pipe != NULL) {
>+		ASSERT(pipe_ctx->bottom_pipe != pipe_ctx);
> 		dcn20_program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
>+	} else if (pipe_ctx->next_odm_pipe != NULL) {
>+		ASSERT(pipe_ctx->next_odm_pipe != pipe_ctx);
>+		dcn20_program_all_pipe_in_tree(dc, pipe_ctx->next_odm_pipe, context);
>+	}
> }
> 
> void dcn20_pipe_control_lock_global(
>@@ -1265,17 +1103,6 @@
> 	if (pipe->plane_state != NULL)
> 		flip_immediate = pipe->plane_state->flip_immediate;
> 
>-	if (flip_immediate && lock) {
>-		while (pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))	{
>-			udelay(1);
>-		}
>-
>-		if (pipe->bottom_pipe != NULL)
>-			while (pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))	{
>-				udelay(1);
>-			}
>-	}
>-
> 	/* In flip immediate and pipe splitting case, we need to use GSL
> 	 * for synchronization. Only do setup on locking and on flip type change.
> 	 */
>@@ -1303,18 +1130,32 @@
> 		int num_planes,
> 		struct dc_state *context)
> {
>-
>+	const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
> 	int i;
> 	struct timing_generator *tg;
> 	bool removed_pipe[6] = { false };
> 	bool interdependent_update = false;
> 	struct pipe_ctx *top_pipe_to_program =
> 			find_top_pipe_for_stream(dc, context, stream);
>+	struct pipe_ctx *prev_top_pipe_to_program =
>+			find_top_pipe_for_stream(dc, dc->current_state, stream);
> 	DC_LOGGER_INIT(dc->ctx->logger);
> 
> 	if (!top_pipe_to_program)
> 		return;
> 
>+	/* Carry over GSL groups in case the context is changing. */
>+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
>+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
>+		struct pipe_ctx *old_pipe_ctx =
>+			&dc->current_state->res_ctx.pipe_ctx[i];
>+
>+		if (pipe_ctx->stream == stream &&
>+		    pipe_ctx->stream == old_pipe_ctx->stream)
>+			pipe_ctx->stream_res.gsl_group =
>+				old_pipe_ctx->stream_res.gsl_group;
>+	}
>+
> 	tg = top_pipe_to_program->stream_res.tg;
> 
> 	interdependent_update = top_pipe_to_program->plane_state &&
>@@ -1345,7 +1186,7 @@
> 			if (old_pipe_ctx->stream_res.tg == tg &&
> 			    old_pipe_ctx->plane_res.hubp &&
> 			    old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
>-				dcn20_disable_plane(dc, old_pipe_ctx);
>+				dc->hwss.disable_plane(dc, old_pipe_ctx);
> 		}
> 
> 		if ((!pipe_ctx->plane_state ||
>@@ -1391,6 +1232,22 @@
> 	for (i = 0; i < dc->res_pool->pipe_count; i++)
> 		if (removed_pipe[i])
> 			dcn20_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
>+
>+	/*
>+	 * If we are enabling a pipe, we need to wait for pending clear as this is a critical
>+	 * part of the enable operation otherwise, DM may request an immediate flip which
>+	 * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
>+	 * is unsupported on DCN.
>+	 */
>+	i = 0;
>+	if (num_planes > 0 && top_pipe_to_program &&
>+			(prev_top_pipe_to_program == NULL || prev_top_pipe_to_program->plane_state == NULL)) {
>+		while (i < TIMEOUT_FOR_PIPE_ENABLE_MS &&
>+				top_pipe_to_program->plane_res.hubp->funcs->hubp_is_flip_pending(top_pipe_to_program->plane_res.hubp)) {
>+			i += 1;
>+			msleep(1);
>+		}
>+	}
> }
> 
> 
>@@ -1400,16 +1257,16 @@
> {
> 	struct hubbub *hubbub = dc->res_pool->hubbub;
> 
>+	dc->clk_mgr->funcs->update_clocks(
>+			dc->clk_mgr,
>+			context,
>+			false);
>+
> 	/* program dchubbub watermarks */
> 	hubbub->funcs->program_watermarks(hubbub,
> 					&context->bw_ctx.bw.dcn.watermarks,
> 					dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
> 					false);
>-
>-	dc->clk_mgr->funcs->update_clocks(
>-			dc->clk_mgr,
>-			context,
>-			false);
> }
> 
> void dcn20_optimize_bandwidth(
>@@ -1462,8 +1319,8 @@
> 
> 			pipe_ctx->stream_res.tg->funcs->set_vtg_params(
> 					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
>-
>-			dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
>+			if (pipe_ctx->prev_odm_pipe == NULL)
>+				dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
> 		}
> 
> 		pipe_ctx->plane_res.hubp->funcs->hubp_setup(
>@@ -1553,12 +1410,15 @@
> {
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> 	struct dce_hwseq *hws = dc->hwseq;
>-	struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
> 
> 	if (pipe_ctx->stream_res.dsc) {
>+		struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
>+
> 		dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
>-		if (bot_odm_pipe)
>-			dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, true);
>+		while (odm_pipe) {
>+			dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
>+			odm_pipe = odm_pipe->next_odm_pipe;
>+		}
> 	}
> #endif
> }
>@@ -1567,12 +1427,15 @@
> {
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> 	struct dce_hwseq *hws = dc->hwseq;
>-	struct pipe_ctx *bot_odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
> 
> 	if (pipe_ctx->stream_res.dsc) {
>+		struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
>+
> 		dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
>-		if (bot_odm_pipe)
>-			dcn20_dsc_pg_control(hws, bot_odm_pipe->stream_res.dsc->inst, false);
>+		while (odm_pipe) {
>+			dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
>+			odm_pipe = odm_pipe->next_odm_pipe;
>+		}
> 	}
> #endif
> }
>@@ -1597,9 +1460,9 @@
> 	hubp->funcs->dmdata_set_attributes(hubp, &attr);
> }
> 
>-void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option)
>+void dcn20_disable_stream(struct pipe_ctx *pipe_ctx)
> {
>-	dce110_disable_stream(pipe_ctx, option);
>+	dce110_disable_stream(pipe_ctx);
> }
> 
> static void dcn20_init_vm_ctx(
>@@ -1637,6 +1500,7 @@
> 	config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
> 	config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
> 	config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
>+	config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
> 
> 	return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
> }
>@@ -1702,18 +1566,22 @@
> 	struct encoder_unblank_param params = { { 0 } };
> 	struct dc_stream_state *stream = pipe_ctx->stream;
> 	struct dc_link *link = stream->link;
>-	params.odm = dc_res_get_odm_bottom_pipe(pipe_ctx);
>+	struct pipe_ctx *odm_pipe;
> 
>+	params.opp_cnt = 1;
>+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
>+		params.opp_cnt++;
>+	}
> 	/* only 3 items below are used by unblank */
> 	params.timing = pipe_ctx->stream->timing;
> 
> 	params.link_settings.link_rate = link_settings->link_rate;
> 
> 	if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
>-		if (optc1_is_two_pixels_per_containter(&stream->timing) || params.odm)
>+		if (optc1_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
> 			params.timing.pix_clk_100hz /= 2;
> 		pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
>-				pipe_ctx->stream_res.stream_enc, params.odm);
>+				pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
> 		pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
> 	}
> 
>@@ -1749,14 +1617,29 @@
> 	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
> 		/* DPMS may already disable */
> 		if (!pipe_ctx->stream->dpms_off)
>-			core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
>-		else if (pipe_ctx->stream_res.audio) {
>-			dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
>+			core_link_disable_stream(pipe_ctx);
>+		else if (pipe_ctx->stream_res.audio)
>+			dc->hwss.disable_audio_stream(pipe_ctx);
>+
>+		/* free acquired resources */
>+		if (pipe_ctx->stream_res.audio) {
>+			/*disable az_endpoint*/
>+			pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
>+
>+			/*free audio*/
>+			if (dc->caps.dynamic_audio == true) {
>+				/*we have to dynamic arbitrate the audio endpoints*/
>+				/*we free the resource, need reset is_audio_acquired*/
>+				update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
>+						pipe_ctx->stream_res.audio, false);
>+				pipe_ctx->stream_res.audio = NULL;
>+			}
> 		}
> 	}
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>-	else if (pipe_ctx->stream_res.dsc)
>+	else if (pipe_ctx->stream_res.dsc) {
> 		dp_set_dsc_enable(pipe_ctx, false);
>+	}
> #endif
> 
> 	/* by upper caller loop, parent pipe: pipe0, will be reset last.
>@@ -1770,6 +1653,10 @@
> 		if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
> 			pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
> 					pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
>+
>+		if (pipe_ctx->stream_res.tg->funcs->set_drr)
>+			pipe_ctx->stream_res.tg->funcs->set_drr(
>+					pipe_ctx->stream_res.tg, NULL);
> 	}
> 
> 	for (i = 0; i < dc->res_pool->pipe_count; i++)
>@@ -1799,7 +1686,7 @@
> 		if (!pipe_ctx_old->stream)
> 			continue;
> 
>-		if (pipe_ctx_old->top_pipe)
>+		if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
> 			continue;
> 
> 		if (!pipe_ctx->stream ||
>@@ -1819,7 +1706,7 @@
> {
> 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
> 	struct mpcc_blnd_cfg blnd_cfg = { {0} };
>-	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
>+	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
> 	int mpcc_id;
> 	struct mpcc *new_mpcc;
> 	struct mpc *mpc = dc->res_pool->mpc;
>@@ -2012,14 +1899,198 @@
> 
> }
> 
>+static void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
>+{
>+	enum dc_lane_count lane_count =
>+		pipe_ctx->stream->link->cur_link_settings.lane_count;
>+
>+	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
>+	struct dc_link *link = pipe_ctx->stream->link;
>+
>+	uint32_t active_total_with_borders;
>+	uint32_t early_control = 0;
>+	struct timing_generator *tg = pipe_ctx->stream_res.tg;
>+
>+	/* For MST, there are multiply stream go to only one link.
>+	 * connect DIG back_end to front_end while enable_stream and
>+	 * disconnect them during disable_stream
>+	 * BY this, it is logic clean to separate stream and link
>+	 */
>+	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
>+						    pipe_ctx->stream_res.stream_enc->id, true);
>+
>+	if (link->dc->hwss.program_dmdata_engine)
>+		link->dc->hwss.program_dmdata_engine(pipe_ctx);
>+
>+	link->dc->hwss.update_info_frame(pipe_ctx);
>+
>+	/* enable early control to avoid corruption on DP monitor*/
>+	active_total_with_borders =
>+			timing->h_addressable
>+				+ timing->h_border_left
>+				+ timing->h_border_right;
>+
>+	if (lane_count != 0)
>+		early_control = active_total_with_borders % lane_count;
>+
>+	if (early_control == 0)
>+		early_control = lane_count;
>+
>+	tg->funcs->set_early_control(tg, early_control);
>+
>+	/* enable audio only within mode set */
>+	if (pipe_ctx->stream_res.audio != NULL) {
>+		if (dc_is_dp_signal(pipe_ctx->stream->signal))
>+			pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
>+	}
>+}
>+
>+static void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
>+{
>+	struct dc_stream_state    *stream     = pipe_ctx->stream;
>+	struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
>+	bool                       enable     = false;
>+	struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
>+	enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
>+							? dmdata_dp
>+							: dmdata_hdmi;
>+
>+	/* if using dynamic meta, don't set up generic infopackets */
>+	if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
>+		pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
>+		enable = true;
>+	}
>+
>+	if (!hubp)
>+		return;
>+
>+	if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
>+		return;
>+
>+	stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
>+						hubp->inst, mode);
>+}
>+
>+static void dcn20_fpga_init_hw(struct dc *dc)
>+{
>+	int i, j;
>+	struct dce_hwseq *hws = dc->hwseq;
>+	struct resource_pool *res_pool = dc->res_pool;
>+	struct dc_state  *context = dc->current_state;
>+
>+	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
>+		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
>+
>+	// Initialize the dccg
>+	if (res_pool->dccg->funcs->dccg_init)
>+		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
>+
>+	//Enable ability to power gate / don't force power on permanently
>+	dc->hwss.enable_power_gating_plane(hws, true);
>+
>+	// Specific to FPGA dccg and registers
>+	REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
>+	REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
>+
>+	dcn20_dccg_init(hws);
>+
>+	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
>+	REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
>+	REG_WRITE(REFCLK_CNTL, 0);
>+	//
>+
>+
>+	/* Blank pixel data with OPP DPG */
>+	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
>+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
>+
>+		if (tg->funcs->is_tg_enabled(tg))
>+			dcn20_init_blank(dc, tg);
>+	}
>+
>+	for (i = 0; i < res_pool->timing_generator_count; i++) {
>+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
>+
>+		if (tg->funcs->is_tg_enabled(tg))
>+			tg->funcs->lock(tg);
>+	}
>+
>+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
>+		struct dpp *dpp = res_pool->dpps[i];
>+
>+		dpp->funcs->dpp_reset(dpp);
>+	}
>+
>+	/* Reset all MPCC muxes */
>+	res_pool->mpc->funcs->mpc_init(res_pool->mpc);
>+
>+	/* initialize OPP mpc_tree parameter */
>+	for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
>+		res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
>+		res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
>+		for (j = 0; j < MAX_PIPES; j++)
>+			res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
>+	}
>+
>+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
>+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
>+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
>+		struct hubp *hubp = dc->res_pool->hubps[i];
>+		struct dpp *dpp = dc->res_pool->dpps[i];
>+
>+		pipe_ctx->stream_res.tg = tg;
>+		pipe_ctx->pipe_idx = i;
>+
>+		pipe_ctx->plane_res.hubp = hubp;
>+		pipe_ctx->plane_res.dpp = dpp;
>+		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
>+		hubp->mpcc_id = dpp->inst;
>+		hubp->opp_id = OPP_ID_INVALID;
>+		hubp->power_gated = false;
>+		pipe_ctx->stream_res.opp = NULL;
>+
>+		hubp->funcs->hubp_init(hubp);
>+
>+		//dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
>+		//dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
>+		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
>+		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
>+		/*to do*/
>+		hwss1_plane_atomic_disconnect(dc, pipe_ctx);
>+	}
>+
>+	/* initialize DWB pointer to MCIF_WB */
>+	for (i = 0; i < res_pool->res_cap->num_dwb; i++)
>+		res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
>+
>+	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
>+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
>+
>+		if (tg->funcs->is_tg_enabled(tg))
>+			tg->funcs->unlock(tg);
>+	}
>+
>+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
>+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
>+
>+		dc->hwss.disable_plane(dc, pipe_ctx);
>+
>+		pipe_ctx->stream_res.tg = NULL;
>+		pipe_ctx->plane_res.hubp = NULL;
>+	}
>+
>+	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
>+		struct timing_generator *tg = dc->res_pool->timing_generators[i];
>+
>+		tg->funcs->tg_init(tg);
>+	}
>+}
>+
> void dcn20_hw_sequencer_construct(struct dc *dc)
> {
> 	dcn10_hw_sequencer_construct(dc);
>-	dc->hwss.init_hw = dcn20_init_hw;
>-	dc->hwss.init_pipes = NULL;
> 	dc->hwss.unblank_stream = dcn20_unblank_stream;
> 	dc->hwss.update_plane_addr = dcn20_update_plane_addr;
>-	dc->hwss.disable_plane = dcn20_disable_plane,
> 	dc->hwss.enable_stream_timing = dcn20_enable_stream_timing;
> 	dc->hwss.program_triplebuffer = dcn20_program_tripleBuffer;
> 	dc->hwss.set_input_transfer_func = dcn20_set_input_transfer_func;
>@@ -2036,6 +2107,8 @@
> 	dc->hwss.update_odm = dcn20_update_odm;
> 	dc->hwss.blank_pixel_data = dcn20_blank_pixel_data;
> 	dc->hwss.dmdata_status_done = dcn20_dmdata_status_done;
>+	dc->hwss.program_dmdata_engine = dcn20_program_dmdata_engine;
>+	dc->hwss.enable_stream = dcn20_enable_stream;
> 	dc->hwss.disable_stream = dcn20_disable_stream;
> 	dc->hwss.init_sys_ctx = dcn20_init_sys_ctx;
> 	dc->hwss.init_vm_ctx = dcn20_init_vm_ctx;
>@@ -2045,5 +2118,23 @@
> 	dc->hwss.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap;
> 	dc->hwss.update_mpcc = dcn20_update_mpcc;
> 	dc->hwss.set_flip_control_gsl = dcn20_set_flip_control_gsl;
>-	dc->hwss.did_underflow_occur = dcn10_did_underflow_occur;
>+	dc->hwss.init_blank = dcn20_init_blank;
>+	dc->hwss.disable_plane = dcn20_disable_plane;
>+	dc->hwss.plane_atomic_disable = dcn20_plane_atomic_disable;
>+	dc->hwss.enable_power_gating_plane = dcn20_enable_power_gating_plane;
>+	dc->hwss.dpp_pg_control = dcn20_dpp_pg_control;
>+	dc->hwss.hubp_pg_control = dcn20_hubp_pg_control;
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	dc->hwss.dsc_pg_control = dcn20_dsc_pg_control;
>+#else
>+	dc->hwss.dsc_pg_control = NULL;
>+#endif
>+	dc->hwss.disable_vga = dcn20_disable_vga;
>+
>+	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
>+		dc->hwss.init_hw = dcn20_fpga_init_hw;
>+		dc->hwss.init_pipes = NULL;
>+	}
>+
>+
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h	2019-08-31 15:01:11.865736169 -0500
>@@ -75,7 +75,7 @@
> 
> void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
> 
>-void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option);
>+void dcn20_disable_stream(struct pipe_ctx *pipe_ctx);
> 
> void dcn20_program_tripleBuffer(
> 		const struct dc *dc,
>@@ -91,13 +91,9 @@
> void dcn20_setup_gsl_group_as_lock(const struct dc *dc,
> 				struct pipe_ctx *pipe_ctx,
> 				bool enable);
>-void dcn20_pipe_control_lock(
>-	struct dc *dc,
>-	struct pipe_ctx *pipe,
>-	bool lock);
>-void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
>-void dcn20_enable_plane(
>-	struct dc *dc,
>-	struct pipe_ctx *pipe_ctx,
>-	struct dc_state *context);
>+void dcn20_dccg_init(struct dce_hwseq *hws);
>+void dcn20_init_blank(
>+	   struct dc *dc,
>+	   struct timing_generator *tg);
>+void dcn20_display_init(struct dc *dc);
> #endif /* __DC_HWSS_DCN20_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c	2019-08-31 15:01:11.866736169 -0500
>@@ -341,6 +341,7 @@
> 	.fec_set_enable = enc2_fec_set_enable,
> 	.fec_set_ready = enc2_fec_set_ready,
> 	.fec_is_active = enc2_fec_is_active,
>+	.get_dig_mode = dcn10_get_dig_mode,
> 	.get_dig_frontend = dcn10_get_dig_frontend,
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c	2019-08-31 15:01:11.866736169 -0500
>@@ -233,14 +233,14 @@
> 	reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
> }
> 
>-static void mpc20_power_on_ogam_lut(
>+void mpc20_power_on_ogam_lut(
> 		struct mpc *mpc, int mpcc_id,
> 		bool power_on)
> {
> 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
> 
> 	REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
>-			MPCC_OGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
>+			MPCC_OGAM_MEM_PWR_DIS, power_on == true ? 1:0);
> 
> }
> 
>@@ -368,6 +368,11 @@
> {
> 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
> 
>+	if (mpc->ctx->dc->debug.cm_in_bypass) {
>+		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
>+		return;
>+	}
>+
> 	if (mpc->ctx->dc->work_arounds.dedcn20_305_wa == false) {
> 		/*hw fixed in new review*/
> 		return;
>@@ -390,10 +395,16 @@
> 	enum dc_lut_mode next_mode;
> 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
> 
>+	if (mpc->ctx->dc->debug.cm_in_bypass) {
>+		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
>+		return;
>+	}
>+
> 	if (params == NULL) {
> 		REG_SET(MPCC_OGAM_MODE[mpcc_id], 0, MPCC_OGAM_MODE, 0);
> 		return;
> 	}
>+
> 	current_mode = mpc20_get_ogam_current(mpc, mpcc_id);
> 	if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
> 		next_mode = LUT_RAM_B;
>@@ -435,23 +446,22 @@
> {
> 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
> 	unsigned int top_sel, mpc_busy, mpc_idle, mpc_disabled;
>-	REG_GET(MPCC_STATUS[mpcc_id], MPCC_DISABLED, &mpc_disabled);
>-
>-	if (mpc_disabled) {
>-		ASSERT(0);
>-		return;
>-	}
> 
> 	REG_GET(MPCC_TOP_SEL[mpcc_id],
> 			MPCC_TOP_SEL, &top_sel);
> 
>-	if (top_sel == 0xf) {
>-		REG_GET_2(MPCC_STATUS[mpcc_id],
>-				MPCC_BUSY, &mpc_busy,
>-				MPCC_IDLE, &mpc_idle);
>+	REG_GET_3(MPCC_STATUS[mpcc_id],
>+			MPCC_BUSY, &mpc_busy,
>+			MPCC_IDLE, &mpc_idle,
>+			MPCC_DISABLED, &mpc_disabled);
> 
>-		ASSERT(mpc_busy == 0);
>-		ASSERT(mpc_idle == 1);
>+	if (top_sel == 0xf) {
>+		ASSERT(!mpc_busy);
>+		ASSERT(mpc_idle);
>+		ASSERT(mpc_disabled);
>+	} else {
>+		ASSERT(!mpc_disabled);
>+		ASSERT(!mpc_idle);
> 	}
> }
> 
>@@ -488,6 +498,7 @@
> 	.insert_plane = mpc1_insert_plane,
> 	.remove_mpcc = mpc1_remove_mpcc,
> 	.mpc_init = mpc1_mpc_init,
>+	.mpc_init_single_inst = mpc1_mpc_init_single_inst,
> 	.update_blending = mpc2_update_blending,
> 	.get_mpcc_for_dpp = mpc2_get_mpcc_for_dpp,
> 	.wait_for_idle = mpc2_assert_idle_mpcc,
>@@ -498,6 +509,7 @@
> 	.set_output_csc = mpc2_set_output_csc,
> 	.set_ocsc_default = mpc2_set_ocsc_default,
> 	.set_output_gamma = mpc2_set_output_gamma,
>+	.power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
> };
> 
> void dcn20_mpc_construct(struct dcn20_mpc *mpc20,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h	2019-08-31 15:01:11.866736169 -0500
>@@ -159,6 +159,7 @@
> 	SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\
> 	SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\
> 	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
>+	SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
> 	SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
> 	SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\
> 	SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\
>@@ -173,6 +174,7 @@
> 	SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
> 	SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh)
> 
>+
> #define MPC_REG_FIELD_LIST_DCN2_0(type) \
> 	MPC_REG_FIELD_LIST(type)\
> 	type MPCC_BG_BPC;\
>@@ -217,7 +219,8 @@
> 	type MPC_OUT_DENORM_CLAMP_MIN_G_Y;\
> 	type MPC_OUT_DENORM_CLAMP_MAX_B_CB;\
> 	type MPC_OUT_DENORM_CLAMP_MIN_B_CB;\
>-	type MPCC_DISABLED;
>+	type MPCC_DISABLED;\
>+	type MPCC_OGAM_MEM_PWR_DIS;
> 
> struct dcn20_mpc_registers {
> 	MPC_REG_VARIABLE_LIST_DCN2_0
>@@ -282,4 +285,5 @@
> 
> void mpc2_assert_idle_mpcc(struct mpc *mpc, int id);
> void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
>+void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c	2019-08-31 15:01:11.866736169 -0500
>@@ -332,7 +332,6 @@
> 		.opp_set_disp_pattern_generator = opp2_set_disp_pattern_generator,
> 		.dpg_is_blanked = opp2_dpg_is_blanked,
> 		.opp_dpg_set_blank_color = opp2_dpg_set_blank_color,
>-		.opp_convert_pti = NULL,
> 		.opp_destroy = opp1_destroy,
> 		.opp_program_left_edge_extra_pixel = opp2_program_left_edge_extra_pixel,
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c	2019-08-31 15:01:11.866736169 -0500
>@@ -191,15 +191,6 @@
> 					uint32_t dsc_slice_width)
> {
> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
>-	uint32_t data_format = 0;
>-	/* skip if dsc mode is not changed */
>-	data_format = dm_read_reg(CTX, REG(OPTC_DATA_FORMAT_CONTROL));
>-
>-	data_format = data_format & 0x30; /* bit5:4 */
>-	data_format = data_format >> 4;
>-
>-	if (data_format == dsc_mode)
>-		return;
> 
> 	REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
> 		OPTC_DSC_MODE, dsc_mode);
>@@ -224,7 +215,6 @@
> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
> 	uint32_t h_div_2 = 0;
> 
>-	optc1->comb_opp_id = 0xf;
> 	REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
> 			OPTC_NUM_OF_INPUT_SEGMENT, 0,
> 			OPTC_SEG0_SRC_SEL, optc->inst,
>@@ -236,13 +226,16 @@
> 			OTG_H_TIMING_DIV_BY2, h_div_2);
> 	REG_SET(OPTC_MEMORY_CONFIG, 0,
> 			OPTC_MEM_SEL, 0);
>+	optc1->opp_count = 1;
> }
> 
>-void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
>-		int mpcc_hactive, enum dc_pixel_encoding pixel_encoding)
>+void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
>+		struct dc_crtc_timing *timing)
> {
> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
> 	/* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192 */
>+	int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
>+			/ opp_cnt;
> 	int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf;
> 	uint32_t data_fmt = 0;
> 
>@@ -257,23 +250,24 @@
> 		REG_SET(OPTC_MEMORY_CONFIG, 0,
> 			OPTC_MEM_SEL, memory_mask << (optc->inst * 4));
> 
>-	if (pixel_encoding == PIXEL_ENCODING_YCBCR422)
>+	if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
> 		data_fmt = 1;
>-	else if (pixel_encoding == PIXEL_ENCODING_YCBCR420)
>+	else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
> 		data_fmt = 2;
> 
> 	REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
> 
>+	ASSERT(opp_cnt == 2);
> 	REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
> 			OPTC_NUM_OF_INPUT_SEGMENT, 1,
>-			OPTC_SEG0_SRC_SEL, optc->inst,
>-			OPTC_SEG1_SRC_SEL, combine_opp_id);
>+			OPTC_SEG0_SRC_SEL, opp_id[0],
>+			OPTC_SEG1_SRC_SEL, opp_id[1]);
> 
> 	REG_UPDATE(OPTC_WIDTH_CONTROL,
> 			OPTC_SEGMENT_WIDTH, mpcc_hactive);
> 
> 	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
>-	optc1->comb_opp_id = combine_opp_id;
>+	optc1->opp_count = opp_cnt;
> }
> 
> void optc2_get_optc_source(struct timing_generator *optc,
>@@ -339,65 +333,6 @@
> 
> }
> 
>-
>-void optc2_setup_global_lock(struct timing_generator *optc)
>-{
>-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
>-	uint32_t v_blank_start = 0;
>-	uint32_t h_blank_start = 0, h_total = 0;
>-
>-	REG_SET(OTG_GLOBAL_CONTROL1, 0, MASTER_UPDATE_LOCK_DB_EN, 1);
>-
>-	REG_SET(OTG_GLOBAL_CONTROL2, 0, DIG_UPDATE_LOCATION, 20);
>-
>-	REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, &v_blank_start);
>-
>-	REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, &h_blank_start);
>-
>-	REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &h_total);
>-	REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
>-			MASTER_UPDATE_LOCK_DB_X,
>-			h_blank_start - 200 - 1,
>-			MASTER_UPDATE_LOCK_DB_Y,
>-			v_blank_start - 1);
>-}
>-
>-void optc2_lock_global(struct timing_generator *optc)
>-{
>-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
>-
>-	REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
>-
>-	REG_SET(OTG_GLOBAL_CONTROL0, 0,
>-			OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
>-	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
>-			OTG_MASTER_UPDATE_LOCK, 1);
>-
>-	/* Should be fast, status does not update on maximus */
>-	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
>-		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
>-				UPDATE_LOCK_STATUS, 1,
>-				1, 10);
>-}
>-
>-void optc2_lock(struct timing_generator *optc)
>-{
>-	struct optc *optc1 = DCN10TG_FROM_TG(optc);
>-
>-	REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
>-
>-	REG_SET(OTG_GLOBAL_CONTROL0, 0,
>-			OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
>-	REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
>-			OTG_MASTER_UPDATE_LOCK, 1);
>-
>-	/* Should be fast, status does not update on maximus */
>-	if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
>-		REG_WAIT(OTG_MASTER_UPDATE_LOCK,
>-				UPDATE_LOCK_STATUS, 1,
>-				1, 10);
>-}
>-
> void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
> {
> 	struct optc *optc1 = DCN10TG_FROM_TG(optc);
>@@ -492,10 +427,8 @@
> 		.triplebuffer_lock = optc2_triplebuffer_lock,
> 		.triplebuffer_unlock = optc2_triplebuffer_unlock,
> 		.disable_reset_trigger = optc1_disable_reset_trigger,
>-		.lock = optc2_lock,
>+		.lock = optc1_lock,
> 		.unlock = optc1_unlock,
>-		.lock_global = optc2_lock_global,
>-		.setup_global_lock = optc2_setup_global_lock,
> 		.lock_doublebuffer_enable = optc2_lock_doublebuffer_enable,
> 		.lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
> 		.enable_optc_clock = optc1_enable_optc_clock,
>@@ -522,7 +455,8 @@
> 		.set_gsl_source_select = optc2_set_gsl_source_select,
> 		.set_vtg_params = optc1_set_vtg_params,
> 		.program_manual_trigger = optc2_program_manual_trigger,
>-		.setup_manual_trigger = optc2_setup_manual_trigger
>+		.setup_manual_trigger = optc2_setup_manual_trigger,
>+		.is_matching_timing = optc1_is_matching_timing
> };
> 
> void dcn20_timing_generator_init(struct optc *optc1)
>@@ -537,6 +471,5 @@
> 	optc1->min_v_blank_interlace = 5;
> 	optc1->min_h_sync_width = 4;//	Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
> 	optc1->min_v_sync_width = 1;
>-	optc1->comb_opp_id = 0xf;
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h	2019-08-31 15:01:11.866736169 -0500
>@@ -96,8 +96,8 @@
> void optc2_set_odm_bypass(struct timing_generator *optc,
> 		const struct dc_crtc_timing *dc_crtc_timing);
> 
>-void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
>-		int mpcc_hactive, enum dc_pixel_encoding pixel_encoding);
>+void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
>+		struct dc_crtc_timing *timing);
> 
> void optc2_get_optc_source(struct timing_generator *optc,
> 		uint32_t *num_of_src_opp,
>@@ -106,9 +106,6 @@
> 
> void optc2_triplebuffer_lock(struct timing_generator *optc);
> void optc2_triplebuffer_unlock(struct timing_generator *optc);
>-void optc2_lock(struct timing_generator *optc);
>-void optc2_lock_global(struct timing_generator *optc);
>-void optc2_setup_global_lock(struct timing_generator *optc);
> void optc2_lock_doublebuffer_disable(struct timing_generator *optc);
> void optc2_lock_doublebuffer_enable(struct timing_generator *optc);
> void optc2_program_manual_trigger(struct timing_generator *optc);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c	2019-08-31 15:01:11.866736169 -0500
>@@ -82,6 +82,7 @@
> 
> #include "amdgpu_socbb.h"
> 
>+/* NV12 SOC BB is currently in FW, mark SW bounding box invalid. */
> #define SOC_BOUNDING_BOX_VALID false
> #define DC_LOGGER_INIT(logger)
> 
>@@ -156,8 +157,119 @@
> 	.xfc_fill_constant_bytes = 0,
> };
> 
>-struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = { 0 };
>+struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
>+	/* Defaults that get patched on driver load from firmware. */
>+	.clock_limits = {
>+			{
>+				.state = 0,
>+				.dcfclk_mhz = 560.0,
>+				.fabricclk_mhz = 560.0,
>+				.dispclk_mhz = 513.0,
>+				.dppclk_mhz = 513.0,
>+				.phyclk_mhz = 540.0,
>+				.socclk_mhz = 560.0,
>+				.dscclk_mhz = 171.0,
>+				.dram_speed_mts = 8960.0,
>+			},
>+			{
>+				.state = 1,
>+				.dcfclk_mhz = 694.0,
>+				.fabricclk_mhz = 694.0,
>+				.dispclk_mhz = 642.0,
>+				.dppclk_mhz = 642.0,
>+				.phyclk_mhz = 600.0,
>+				.socclk_mhz = 694.0,
>+				.dscclk_mhz = 214.0,
>+				.dram_speed_mts = 11104.0,
>+			},
>+			{
>+				.state = 2,
>+				.dcfclk_mhz = 875.0,
>+				.fabricclk_mhz = 875.0,
>+				.dispclk_mhz = 734.0,
>+				.dppclk_mhz = 734.0,
>+				.phyclk_mhz = 810.0,
>+				.socclk_mhz = 875.0,
>+				.dscclk_mhz = 245.0,
>+				.dram_speed_mts = 14000.0,
>+			},
>+			{
>+				.state = 3,
>+				.dcfclk_mhz = 1000.0,
>+				.fabricclk_mhz = 1000.0,
>+				.dispclk_mhz = 1100.0,
>+				.dppclk_mhz = 1100.0,
>+				.phyclk_mhz = 810.0,
>+				.socclk_mhz = 1000.0,
>+				.dscclk_mhz = 367.0,
>+				.dram_speed_mts = 16000.0,
>+			},
>+			{
>+				.state = 4,
>+				.dcfclk_mhz = 1200.0,
>+				.fabricclk_mhz = 1200.0,
>+				.dispclk_mhz = 1284.0,
>+				.dppclk_mhz = 1284.0,
>+				.phyclk_mhz = 810.0,
>+				.socclk_mhz = 1200.0,
>+				.dscclk_mhz = 428.0,
>+				.dram_speed_mts = 16000.0,
>+			},
>+			/*Extra state, no dispclk ramping*/
>+			{
>+				.state = 5,
>+				.dcfclk_mhz = 1200.0,
>+				.fabricclk_mhz = 1200.0,
>+				.dispclk_mhz = 1284.0,
>+				.dppclk_mhz = 1284.0,
>+				.phyclk_mhz = 810.0,
>+				.socclk_mhz = 1200.0,
>+				.dscclk_mhz = 428.0,
>+				.dram_speed_mts = 16000.0,
>+			},
>+		},
>+	.num_states = 5,
>+	.sr_exit_time_us = 8.6,
>+	.sr_enter_plus_exit_time_us = 10.9,
>+	.urgent_latency_us = 4.0,
>+	.urgent_latency_pixel_data_only_us = 4.0,
>+	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
>+	.urgent_latency_vm_data_only_us = 4.0,
>+	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
>+	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
>+	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
>+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
>+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
>+	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
>+	.max_avg_sdp_bw_use_normal_percent = 40.0,
>+	.max_avg_dram_bw_use_normal_percent = 40.0,
>+	.writeback_latency_us = 12.0,
>+	.ideal_dram_bw_after_urgent_percent = 40.0,
>+	.max_request_size_bytes = 256,
>+	.dram_channel_width_bytes = 2,
>+	.fabric_datapath_to_dcn_data_return_bytes = 64,
>+	.dcn_downspread_percent = 0.5,
>+	.downspread_percent = 0.38,
>+	.dram_page_open_time_ns = 50.0,
>+	.dram_rw_turnaround_time_ns = 17.5,
>+	.dram_return_buffer_per_channel_bytes = 8192,
>+	.round_trip_ping_latency_dcfclk_cycles = 131,
>+	.urgent_out_of_order_return_per_channel_bytes = 256,
>+	.channel_interleave_bytes = 256,
>+	.num_banks = 8,
>+	.num_chans = 16,
>+	.vmm_page_size_bytes = 4096,
>+	.dram_clock_change_latency_us = 404.0,
>+	.dummy_pstate_latency_us = 5.0,
>+	.writeback_dram_clock_change_latency_us = 23.0,
>+	.return_bus_width_bytes = 64,
>+	.dispclk_dppclk_vco_speed_mhz = 3850,
>+	.xfc_bus_transport_time_us = 20,
>+	.xfc_xbuf_latency_tolerance_us = 4,
>+	.use_urgent_burst_bw = 0
>+};
> 
>+struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
> 
> #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
> 	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f
>@@ -314,7 +426,7 @@
> 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
> };
> 
>-static const struct dce_aduio_mask audio_mask = {
>+static const struct dce_audio_mask audio_mask = {
> 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
> };
> 
>@@ -695,6 +807,16 @@
> 			.fp16 = 1
> 	}
> };
>+static const struct resource_caps res_cap_nv14 = {
>+		.num_timing_generator = 5,
>+		.num_opp = 5,
>+		.num_video_plane = 5,
>+		.num_audio = 6,
>+		.num_stream_encoder = 5,
>+		.num_pll = 5,
>+		.num_dwb = 0,
>+		.num_ddc = 5,
>+};
> 
> static const struct dc_debug_options debug_defaults_drv = {
> 		.disable_dmcu = true,
>@@ -1197,7 +1319,11 @@
> 	struct pixel_clk_params *pixel_clk_params)
> {
> 	const struct dc_stream_state *stream = pipe_ctx->stream;
>-	bool odm_combine = dc_res_get_odm_bottom_pipe(pipe_ctx) != NULL;
>+	struct pipe_ctx *odm_pipe;
>+	int opp_cnt = 1;
>+
>+	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
>+		opp_cnt++;
> 
> 	pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
> 	pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
>@@ -1215,7 +1341,9 @@
> 	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
> 		pixel_clk_params->color_depth = COLOR_DEPTH_888;
> 
>-	if (optc1_is_two_pixels_per_containter(&stream->timing) || odm_combine)
>+	if (opp_cnt == 4)
>+		pixel_clk_params->requested_pix_clk_100hz /= 4;
>+	else if (optc1_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
> 		pixel_clk_params->requested_pix_clk_100hz /= 2;
> 
> 	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
>@@ -1359,22 +1487,16 @@
> 	for (i = 0; i < MAX_PIPES; i++) {
> 		if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
> 			pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
>-			break;
>+
>+			if (pipe_ctx->stream_res.dsc)
>+				release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
> 		}
> 	}
> 
> 	if (!pipe_ctx)
> 		return DC_ERROR_UNEXPECTED;
>-
>-	if (pipe_ctx->stream_res.dsc) {
>-		struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
>-
>-		release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
>-		if (odm_pipe)
>-			release_dsc(&new_ctx->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
>-	}
>-
>-	return DC_OK;
>+	else
>+		return DC_OK;
> }
> #endif
> 
>@@ -1473,17 +1595,92 @@
> 	}
> }
> 
>-static bool dcn20_split_stream_for_combine(
>+static bool dcn20_split_stream_for_odm(
>+		struct resource_context *res_ctx,
>+		const struct resource_pool *pool,
>+		struct pipe_ctx *prev_odm_pipe,
>+		struct pipe_ctx *next_odm_pipe)
>+{
>+	int pipe_idx = next_odm_pipe->pipe_idx;
>+
>+	*next_odm_pipe = *prev_odm_pipe;
>+
>+	next_odm_pipe->pipe_idx = pipe_idx;
>+	next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
>+	next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
>+	next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
>+	next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
>+	next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
>+	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	next_odm_pipe->stream_res.dsc = NULL;
>+#endif
>+	if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
>+		ASSERT(!next_odm_pipe->next_odm_pipe);
>+		next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
>+		next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
>+	}
>+	prev_odm_pipe->next_odm_pipe = next_odm_pipe;
>+	next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
>+	ASSERT(next_odm_pipe->top_pipe == NULL);
>+
>+	if (prev_odm_pipe->plane_state) {
>+		struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
>+		int new_width;
>+
>+		/* HACTIVE halved for odm combine */
>+		sd->h_active /= 2;
>+		/* Calculate new vp and recout for left pipe */
>+		/* Need at least 16 pixels width per side */
>+		if (sd->recout.x + 16 >= sd->h_active)
>+			return false;
>+		new_width = sd->h_active - sd->recout.x;
>+		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
>+				sd->ratios.horz, sd->recout.width - new_width));
>+		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
>+				sd->ratios.horz_c, sd->recout.width - new_width));
>+		sd->recout.width = new_width;
>+
>+		/* Calculate new vp and recout for right pipe */
>+		sd = &next_odm_pipe->plane_res.scl_data;
>+		/* HACTIVE halved for odm combine */
>+		sd->h_active /= 2;
>+		/* Need at least 16 pixels width per side */
>+		if (new_width <= 16)
>+			return false;
>+		new_width = sd->recout.width + sd->recout.x - sd->h_active;
>+		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
>+				sd->ratios.horz, sd->recout.width - new_width));
>+		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
>+				sd->ratios.horz_c, sd->recout.width - new_width));
>+		sd->recout.width = new_width;
>+		sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
>+				sd->ratios.horz, sd->h_active - sd->recout.x));
>+		sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
>+				sd->ratios.horz_c, sd->h_active - sd->recout.x));
>+		sd->recout.x = 0;
>+	}
>+	next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	if (next_odm_pipe->stream->timing.flags.DSC == 1) {
>+		acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc);
>+		ASSERT(next_odm_pipe->stream_res.dsc);
>+		if (next_odm_pipe->stream_res.dsc == NULL)
>+			return false;
>+	}
>+#endif
>+
>+	return true;
>+}
>+
>+static void dcn20_split_stream_for_mpc(
> 		struct resource_context *res_ctx,
> 		const struct resource_pool *pool,
> 		struct pipe_ctx *primary_pipe,
>-		struct pipe_ctx *secondary_pipe,
>-		bool is_odm_combine)
>+		struct pipe_ctx *secondary_pipe)
> {
> 	int pipe_idx = secondary_pipe->pipe_idx;
>-	struct scaler_data *sd = &primary_pipe->plane_res.scl_data;
> 	struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
>-	int new_width;
> 
> 	*secondary_pipe = *primary_pipe;
> 	secondary_pipe->bottom_pipe = sec_bot_pipe;
>@@ -1506,57 +1703,9 @@
> 	primary_pipe->bottom_pipe = secondary_pipe;
> 	secondary_pipe->top_pipe = primary_pipe;
> 
>-	if (is_odm_combine) {
>-		if (primary_pipe->plane_state) {
>-			/* HACTIVE halved for odm combine */
>-			sd->h_active /= 2;
>-			/* Copy scl_data to secondary pipe */
>-			secondary_pipe->plane_res.scl_data = *sd;
>-
>-			/* Calculate new vp and recout for left pipe */
>-			/* Need at least 16 pixels width per side */
>-			if (sd->recout.x + 16 >= sd->h_active)
>-				return false;
>-			new_width = sd->h_active - sd->recout.x;
>-			sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
>-					sd->ratios.horz, sd->recout.width - new_width));
>-			sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
>-					sd->ratios.horz_c, sd->recout.width - new_width));
>-			sd->recout.width = new_width;
>-
>-			/* Calculate new vp and recout for right pipe */
>-			sd = &secondary_pipe->plane_res.scl_data;
>-			new_width = sd->recout.width + sd->recout.x - sd->h_active;
>-			/* Need at least 16 pixels width per side */
>-			if (new_width <= 16)
>-				return false;
>-			sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
>-					sd->ratios.horz, sd->recout.width - new_width));
>-			sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
>-					sd->ratios.horz_c, sd->recout.width - new_width));
>-			sd->recout.width = new_width;
>-			sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
>-					sd->ratios.horz, sd->h_active - sd->recout.x));
>-			sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
>-					sd->ratios.horz_c, sd->h_active - sd->recout.x));
>-			sd->recout.x = 0;
>-		}
>-		secondary_pipe->stream_res.opp = pool->opps[secondary_pipe->pipe_idx];
>-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>-		if (secondary_pipe->stream->timing.flags.DSC == 1) {
>-			acquire_dsc(res_ctx, pool, &secondary_pipe->stream_res.dsc);
>-			ASSERT(secondary_pipe->stream_res.dsc);
>-			if (secondary_pipe->stream_res.dsc == NULL)
>-				return false;
>-		}
>-#endif
>-	} else {
>-		ASSERT(primary_pipe->plane_state);
>-		resource_build_scaling_params(primary_pipe);
>-		resource_build_scaling_params(secondary_pipe);
>-	}
>-
>-	return true;
>+	ASSERT(primary_pipe->plane_state);
>+	resource_build_scaling_params(primary_pipe);
>+	resource_build_scaling_params(secondary_pipe);
> }
> 
> void dcn20_populate_dml_writeback_from_context(
>@@ -1669,6 +1818,19 @@
> 		pipes[pipe_cnt].dout.dp_lanes = 4;
> 		pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
> 		pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
>+		pipes[pipe_cnt].pipe.dest.odm_combine = res_ctx->pipe_ctx[i].prev_odm_pipe
>+							|| res_ctx->pipe_ctx[i].next_odm_pipe;
>+		pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
>+		if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
>+				== res_ctx->pipe_ctx[i].plane_state)
>+			pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
>+		else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
>+			struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
>+
>+			while (first_pipe->prev_odm_pipe)
>+				first_pipe = first_pipe->prev_odm_pipe;
>+			pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
>+		}
> 
> 		switch (res_ctx->pipe_ctx[i].stream->signal) {
> 		case SIGNAL_TYPE_DISPLAY_PORT_MST:
>@@ -1721,7 +1883,6 @@
> 			break;
> 		}
> 
>-
> 		switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
> 		case PIXEL_ENCODING_RGB:
> 		case PIXEL_ENCODING_YCBCR444:
>@@ -1743,10 +1904,6 @@
> 			pipes[pipe_cnt].dout.output_format = dm_444;
> 			pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
> 		}
>-		pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
>-		if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
>-				== res_ctx->pipe_ctx[i].plane_state)
>-			pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
> 
> 		/* todo: default max for now, until there is logic reflecting this in dc*/
> 		pipes[pipe_cnt].dout.output_bpc = 12;
>@@ -1795,14 +1952,6 @@
> 					&& res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
> 					|| (res_ctx->pipe_ctx[i].top_pipe
> 					&& res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
>-			pipes[pipe_cnt].pipe.dest.odm_combine = (res_ctx->pipe_ctx[i].bottom_pipe
>-					&& res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln
>-					&& res_ctx->pipe_ctx[i].bottom_pipe->stream_res.opp
>-						!= res_ctx->pipe_ctx[i].stream_res.opp)
>-				|| (res_ctx->pipe_ctx[i].top_pipe
>-					&& res_ctx->pipe_ctx[i].top_pipe->plane_state == pln
>-					&& res_ctx->pipe_ctx[i].top_pipe->stream_res.opp
>-						!= res_ctx->pipe_ctx[i].stream_res.opp);
> 			pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
> 					|| pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
> 			pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
>@@ -1812,13 +1961,13 @@
> 			pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
> 			pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
> 			if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
>-				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.video.luma_pitch;
>-				pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.video.chroma_pitch;
>-				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.video.meta_pitch_l;
>-				pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.video.meta_pitch_c;
>+				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
>+				pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
>+				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
>+				pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
> 			} else {
>-				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.grph.surface_pitch;
>-				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.grph.meta_pitch;
>+				pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
>+				pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
> 			}
> 			pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
> 			pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
>@@ -1986,20 +2135,24 @@
> 		struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
> 		struct dc_stream_state *stream = pipe_ctx->stream;
> 		struct dsc_config dsc_cfg;
>+		struct pipe_ctx *odm_pipe;
>+		int opp_cnt = 1;
>+
>+		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
>+			opp_cnt++;
> 
> 		/* Only need to validate top pipe */
>-		if (pipe_ctx->top_pipe || !stream || !stream->timing.flags.DSC)
>+		if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
> 			continue;
> 
>-		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left
>-				+ stream->timing.h_border_right;
>+		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
>+				+ stream->timing.h_border_right) / opp_cnt;
> 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
> 				+ stream->timing.v_border_bottom;
>-		if (dc_res_get_odm_bottom_pipe(pipe_ctx))
>-			dsc_cfg.pic_width /= 2;
> 		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
> 		dsc_cfg.color_depth = stream->timing.display_color_depth;
> 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
>+		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
> 
> 		if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
> 			return false;
>@@ -2008,15 +2161,93 @@
> }
> #endif
> 
>-bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
>-		bool fast_validate)
>+static struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
>+		struct resource_context *res_ctx,
>+		const struct resource_pool *pool,
>+		const struct pipe_ctx *primary_pipe)
> {
>-	bool out = false;
>+	struct pipe_ctx *secondary_pipe = NULL;
> 
>-	BW_VAL_TRACE_SETUP();
>+	if (dc && primary_pipe) {
>+		int j;
>+		int preferred_pipe_idx = 0;
>+
>+		/* first check the prev dc state:
>+		 * if this primary pipe has a bottom pipe in prev. state
>+		 * and if the bottom pipe is still available (which it should be),
>+		 * pick that pipe as secondary
>+		 * Same logic applies for ODM pipes. Since mpo is not allowed with odm
>+		 * check in else case.
>+		 */
>+		if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
>+			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
>+			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
>+				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
>+				secondary_pipe->pipe_idx = preferred_pipe_idx;
>+			}
>+		} else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
>+			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
>+			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
>+				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
>+				secondary_pipe->pipe_idx = preferred_pipe_idx;
>+			}
>+		}
>+
>+		/*
>+		 * if this primary pipe does not have a bottom pipe in prev. state
>+		 * start backward and find a pipe that did not used to be a bottom pipe in
>+		 * prev. dc state. This way we make sure we keep the same assignment as
>+		 * last state and will not have to reprogram every pipe
>+		 */
>+		if (secondary_pipe == NULL) {
>+			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
>+				if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL) {
>+					preferred_pipe_idx = j;
>+
>+					if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
>+						secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
>+						secondary_pipe->pipe_idx = preferred_pipe_idx;
>+						break;
>+					}
>+				}
>+			}
>+		}
>+		/*
>+		 * We should never hit this assert unless assignments are shuffled around
>+		 * if this happens we will prob. hit a vsync tdr
>+		 */
>+		ASSERT(secondary_pipe);
>+		/*
>+		 * search backwards for the second pipe to keep pipe
>+		 * assignment more consistent
>+		 */
>+		if (secondary_pipe == NULL) {
>+			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
>+				preferred_pipe_idx = j;
>+
>+				if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
>+					secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
>+					secondary_pipe->pipe_idx = preferred_pipe_idx;
>+					break;
>+				}
>+			}
>+		}
>+	}
>+
>+	return secondary_pipe;
>+}
>+
>+bool dcn20_fast_validate_bw(
>+		struct dc *dc,
>+		struct dc_state *context,
>+		display_e2e_pipe_params_st *pipes,
>+		int *pipe_cnt_out,
>+		int *pipe_split_from,
>+		int *vlevel_out)
>+{
>+	bool out = false;
> 
> 	int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
>-	int pipe_split_from[MAX_PIPES];
> 	bool odm_capable = context->bw_ctx.dml.ip.odm_capable;
> 	bool force_split = false;
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>@@ -2024,15 +2255,44 @@
> #endif
> 	int split_threshold = dc->res_pool->pipe_count / 2;
> 	bool avoid_split = dc->debug.pipe_split_policy != MPC_SPLIT_DYNAMIC;
>-	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
>-	DC_LOGGER_INIT(dc->ctx->logger);
> 
>-	BW_VAL_TRACE_COUNT();
> 
> 	ASSERT(pipes);
> 	if (!pipes)
> 		return false;
> 
>+	/* merge previously split odm pipes since mode support needs to make the decision */
>+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
>+		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
>+		struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
>+
>+		if (pipe->prev_odm_pipe)
>+			continue;
>+
>+		pipe->next_odm_pipe = NULL;
>+		while (odm_pipe) {
>+			struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
>+
>+			odm_pipe->plane_state = NULL;
>+			odm_pipe->stream = NULL;
>+			odm_pipe->top_pipe = NULL;
>+			odm_pipe->bottom_pipe = NULL;
>+			odm_pipe->prev_odm_pipe = NULL;
>+			odm_pipe->next_odm_pipe = NULL;
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+			if (odm_pipe->stream_res.dsc)
>+				release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
>+#endif
>+			/* Clear plane_res and stream_res */
>+			memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
>+			memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
>+			odm_pipe = next_odm_pipe;
>+		}
>+		if (pipe->plane_state)
>+			resource_build_scaling_params(pipe);
>+	}
>+
>+	/* merge previously mpc split pipes since mode support needs to make the decision */
> 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
> 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
> 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
>@@ -2040,7 +2300,6 @@
> 		if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
> 			continue;
> 
>-		/* merge previously split pipe since mode support needs to make the decision */
> 		pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
> 		if (hsplit_pipe->bottom_pipe)
> 			hsplit_pipe->bottom_pipe->top_pipe = pipe;
>@@ -2048,10 +2307,7 @@
> 		hsplit_pipe->stream = NULL;
> 		hsplit_pipe->top_pipe = NULL;
> 		hsplit_pipe->bottom_pipe = NULL;
>-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>-		if (hsplit_pipe->stream_res.dsc && hsplit_pipe->stream_res.dsc != pipe->stream_res.dsc)
>-			release_dsc(&context->res_ctx, dc->res_pool, &hsplit_pipe->stream_res.dsc);
>-#endif
>+
> 		/* Clear plane_res and stream_res */
> 		memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
> 		memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
>@@ -2066,8 +2322,9 @@
> 		pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
> 			&context->res_ctx, pipes);
> 
>+	*pipe_cnt_out = pipe_cnt;
>+
> 	if (!pipe_cnt) {
>-		BW_VAL_TRACE_SKIP(pass);
> 		out = true;
> 		goto validate_out;
> 	}
>@@ -2160,17 +2417,12 @@
> 		}
> 		if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
> 			context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
>-		if (dc->config.forced_clocks == true) {
>-			context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] =
>-					context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
>-		}
> 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
>-			hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
>+			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
> 			ASSERT(hsplit_pipe);
>-			if (!dcn20_split_stream_for_combine(
>+			if (!dcn20_split_stream_for_odm(
> 					&context->res_ctx, dc->res_pool,
>-					pipe, hsplit_pipe,
>-					true))
>+					pipe, hsplit_pipe))
> 				goto validate_fail;
> 			pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
> 			dcn20_build_mapped_resource(dc, context, pipe->stream);
>@@ -2206,16 +2458,20 @@
> 		if (need_split3d || need_split || force_split) {
> 			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
> 				/* pipe not split previously needs split */
>-				hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, dc->res_pool, pipe);
>+				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
> 				ASSERT(hsplit_pipe || force_split);
> 				if (!hsplit_pipe)
> 					continue;
> 
>-				if (!dcn20_split_stream_for_combine(
>+				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
>+					if (!dcn20_split_stream_for_odm(
>+							&context->res_ctx, dc->res_pool,
>+							pipe, hsplit_pipe))
>+						goto validate_fail;
>+				} else
>+					dcn20_split_stream_for_mpc(
> 						&context->res_ctx, dc->res_pool,
>-						pipe, hsplit_pipe,
>-						context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]))
>-					goto validate_fail;
>+						pipe, hsplit_pipe);
> 				pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
> 			}
> 		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
>@@ -2232,13 +2488,26 @@
> 	}
> #endif
> 
>-	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
>+	*vlevel_out = vlevel;
> 
>-	if (fast_validate) {
>-		BW_VAL_TRACE_SKIP(fast);
>-		out = true;
>-		goto validate_out;
>-	}
>+	out = true;
>+	goto validate_out;
>+
>+validate_fail:
>+	out = false;
>+
>+validate_out:
>+	return out;
>+}
>+
>+void dcn20_calculate_wm(
>+		struct dc *dc, struct dc_state *context,
>+		display_e2e_pipe_params_st *pipes,
>+		int *out_pipe_cnt,
>+		int *pipe_split_from,
>+		int vlevel)
>+{
>+	int pipe_cnt, i, pipe_idx;
> 
> 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
> 		if (!context->res_ctx.pipe_ctx[i].stream)
>@@ -2265,10 +2534,16 @@
> 			else
> 				pipes[pipe_cnt].pipe.dest.odm_combine = 0;
> 		}
>+
> 		if (dc->config.forced_clocks) {
> 			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
> 			pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
> 		}
>+		if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
>+			pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
>+		if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
>+			pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
>+
> 		pipe_cnt++;
> 	}
> 
>@@ -2281,6 +2556,8 @@
> 				&context->res_ctx, pipes);
> 	}
> 
>+	*out_pipe_cnt = pipe_cnt;
>+
> 	pipes[0].clks_cfg.voltage = vlevel;
> 	pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
> 	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
>@@ -2327,6 +2604,17 @@
> 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
> 	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
> 	context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
>+}
>+
>+void dcn20_calculate_dlg_params(
>+		struct dc *dc, struct dc_state *context,
>+		display_e2e_pipe_params_st *pipes,
>+		int pipe_cnt,
>+		int vlevel)
>+{
>+	int i, j, pipe_idx, pipe_idx_unsplit;
>+	bool visited[MAX_PIPES] = { 0 };
>+
> 	/* Writeback MCIF_WB arbitration parameters */
> 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
> 
>@@ -2335,32 +2623,69 @@
> 	context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
> 	context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
> 	context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
>-	context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
>+	context->bw_ctx.bw.dcn.clk.fclk_khz = 0;
> 	context->bw_ctx.bw.dcn.clk.p_state_change_support =
> 		context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
> 							!= dm_dram_clock_change_unsupported;
> 	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
> 
>-	BW_VAL_TRACE_END_WATERMARKS();
>+	/*
>+	 * An artifact of dml pipe split/odm is that pipes get merged back together for
>+	 * calculation. Therefore we need to only extract for first pipe in ascending index order
>+	 * and copy into the other split half.
>+	 */
>+	for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
>+		if (!context->res_ctx.pipe_ctx[i].stream)
>+			continue;
>+
>+		if (!visited[pipe_idx]) {
>+			display_pipe_source_params_st *src = &pipes[pipe_idx_unsplit].pipe.src;
>+			display_pipe_dest_params_st *dst = &pipes[pipe_idx_unsplit].pipe.dest;
>+
>+			dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
>+			dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
>+			dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
>+			dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
>+			/*
>+			 * j iterates inside pipes array, unlike i which iterates inside
>+			 * pipe_ctx array
>+			 */
>+			if (src->is_hsplit)
>+				for (j = pipe_idx + 1; j < pipe_cnt; j++) {
>+					display_pipe_source_params_st *src_j = &pipes[j].pipe.src;
>+					display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;
>+
>+					if (src_j->is_hsplit && !visited[j]
>+							&& src->hsplit_grp == src_j->hsplit_grp) {
>+						dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
>+						dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
>+						dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
>+						dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
>+						visited[j] = true;
>+					}
>+				}
>+			visited[pipe_idx] = true;
>+			pipe_idx_unsplit++;
>+		}
>+		pipe_idx++;
>+	}
> 
> 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
> 		if (!context->res_ctx.pipe_ctx[i].stream)
> 			continue;
>-		pipes[pipe_idx].pipe.dest.vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx];
>-		pipes[pipe_idx].pipe.dest.vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx];
>-		pipes[pipe_idx].pipe.dest.vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx];
>-		pipes[pipe_idx].pipe.dest.vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx];
> 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
> 			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
> 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
> 						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
>-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>-		context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz =
>-				context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000;
>-#endif
>+		ASSERT(visited[pipe_idx]);
> 		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
> 		pipe_idx++;
> 	}
>+	/*save a original dppclock copy*/
>+	context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
>+	context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
>+	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
>+	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
> 
> 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
> 		bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
>@@ -2383,8 +2708,43 @@
> 				pipes[pipe_idx].pipe);
> 		pipe_idx++;
> 	}
>+}
>+
>+static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
>+		bool fast_validate)
>+{
>+	bool out = false;
>+
>+	BW_VAL_TRACE_SETUP();
>+
>+	int vlevel = 0;
>+	int pipe_split_from[MAX_PIPES];
>+	int pipe_cnt = 0;
>+	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
>+	DC_LOGGER_INIT(dc->ctx->logger);
>+
>+	BW_VAL_TRACE_COUNT();
>+
>+	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
>+
>+	if (pipe_cnt == 0)
>+		goto validate_out;
>+
>+	if (!out)
>+		goto validate_fail;
>+
>+	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
>+
>+	if (fast_validate) {
>+		BW_VAL_TRACE_SKIP(fast);
>+		goto validate_out;
>+	}
>+
>+	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
>+	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
>+
>+	BW_VAL_TRACE_END_WATERMARKS();
> 
>-	out = true;
> 	goto validate_out;
> 
> validate_fail:
>@@ -2402,6 +2762,50 @@
> 	return out;
> }
> 
>+
>+bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
>+		bool fast_validate)
>+{
>+	bool voltage_supported = false;
>+	bool full_pstate_supported = false;
>+	bool dummy_pstate_supported = false;
>+	double p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
>+
>+	if (fast_validate)
>+		return dcn20_validate_bandwidth_internal(dc, context, true);
>+
>+
>+	// Best case, we support full UCLK switch latency
>+	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
>+	full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
>+
>+	if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
>+		(voltage_supported && full_pstate_supported)) {
>+		context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
>+		goto restore_dml_state;
>+	}
>+
>+	// Fallback: Try to only support G6 temperature read latency
>+	context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
>+
>+	voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
>+	dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
>+
>+	if (voltage_supported && dummy_pstate_supported) {
>+		context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
>+		goto restore_dml_state;
>+	}
>+
>+	// ERROR: fallback is supposed to always work.
>+	ASSERT(false);
>+
>+restore_dml_state:
>+	memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
>+	context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
>+
>+	return voltage_supported;
>+}
>+
> struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
> 		struct dc_state *state,
> 		const struct resource_pool *pool,
>@@ -2576,9 +2980,6 @@
> 						&& max_clocks.uClockInKhz != 0)
> 			bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
> 
>-		// HACK: Force every uclk to max for now to "disable" uclk switching.
>-		bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
>-
> 		if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
> 						&& max_clocks.fabricClockInKhz != 0)
> 			bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
>@@ -2674,6 +3075,10 @@
> 		num_calculated_states++;
> 	}
> 
>+	calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
>+	calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
>+	calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
>+
> 	memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
> 	bb->num_states = num_calculated_states;
> 
>@@ -2711,6 +3116,27 @@
> 	kernel_fpu_end();
> }
> 
>+static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
>+	uint32_t hw_internal_rev)
>+{
>+	if (ASICREV_IS_NAVI12_P(hw_internal_rev))
>+		return &dcn2_0_nv12_soc;
>+
>+	return &dcn2_0_soc;
>+}
>+
>+static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
>+	uint32_t hw_internal_rev)
>+{
>+	/* NV12 and NV10 */
>+	return &dcn2_0_ip;
>+}
>+
>+static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
>+{
>+	return DML_PROJECT_NAVI10v2;
>+}
>+
> #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
> #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
> 
>@@ -2718,6 +3144,11 @@
> 				  struct dcn20_resource_pool *pool)
> {
> 	const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
>+	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
>+			get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
>+	struct _vcs_dpi_ip_params_st *loaded_ip =
>+			get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
>+
> 	DC_LOGGER_INIT(dc->ctx->logger);
> 
> 	if (!bb && !SOC_BOUNDING_BOX_VALID) {
>@@ -2728,103 +3159,103 @@
> 	if (bb && !SOC_BOUNDING_BOX_VALID) {
> 		int i;
> 
>-		dcn2_0_soc.sr_exit_time_us =
>+		dcn2_0_nv12_soc.sr_exit_time_us =
> 				fixed16_to_double_to_cpu(bb->sr_exit_time_us);
>-		dcn2_0_soc.sr_enter_plus_exit_time_us =
>+		dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
> 				fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
>-		dcn2_0_soc.urgent_latency_us =
>+		dcn2_0_nv12_soc.urgent_latency_us =
> 				fixed16_to_double_to_cpu(bb->urgent_latency_us);
>-		dcn2_0_soc.urgent_latency_pixel_data_only_us =
>+		dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
> 				fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
>-		dcn2_0_soc.urgent_latency_pixel_mixed_with_vm_data_us =
>+		dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
> 				fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
>-		dcn2_0_soc.urgent_latency_vm_data_only_us =
>+		dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
> 				fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
>-		dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
>+		dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
> 				le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
>-		dcn2_0_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
>+		dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
> 				le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
>-		dcn2_0_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
>+		dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
> 				le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
>-		dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
>+		dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
> 				fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
>-		dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
>+		dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
> 				fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
>-		dcn2_0_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
>+		dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
> 				fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
>-		dcn2_0_soc.max_avg_sdp_bw_use_normal_percent =
>+		dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
> 				fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
>-		dcn2_0_soc.max_avg_dram_bw_use_normal_percent =
>+		dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
> 				fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
>-		dcn2_0_soc.writeback_latency_us =
>+		dcn2_0_nv12_soc.writeback_latency_us =
> 				fixed16_to_double_to_cpu(bb->writeback_latency_us);
>-		dcn2_0_soc.ideal_dram_bw_after_urgent_percent =
>+		dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
> 				fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
>-		dcn2_0_soc.max_request_size_bytes =
>+		dcn2_0_nv12_soc.max_request_size_bytes =
> 				le32_to_cpu(bb->max_request_size_bytes);
>-		dcn2_0_soc.dram_channel_width_bytes =
>+		dcn2_0_nv12_soc.dram_channel_width_bytes =
> 				le32_to_cpu(bb->dram_channel_width_bytes);
>-		dcn2_0_soc.fabric_datapath_to_dcn_data_return_bytes =
>+		dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
> 				le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
>-		dcn2_0_soc.dcn_downspread_percent =
>+		dcn2_0_nv12_soc.dcn_downspread_percent =
> 				fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
>-		dcn2_0_soc.downspread_percent =
>+		dcn2_0_nv12_soc.downspread_percent =
> 				fixed16_to_double_to_cpu(bb->downspread_percent);
>-		dcn2_0_soc.dram_page_open_time_ns =
>+		dcn2_0_nv12_soc.dram_page_open_time_ns =
> 				fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
>-		dcn2_0_soc.dram_rw_turnaround_time_ns =
>+		dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
> 				fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
>-		dcn2_0_soc.dram_return_buffer_per_channel_bytes =
>+		dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
> 				le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
>-		dcn2_0_soc.round_trip_ping_latency_dcfclk_cycles =
>+		dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
> 				le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
>-		dcn2_0_soc.urgent_out_of_order_return_per_channel_bytes =
>+		dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
> 				le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
>-		dcn2_0_soc.channel_interleave_bytes =
>+		dcn2_0_nv12_soc.channel_interleave_bytes =
> 				le32_to_cpu(bb->channel_interleave_bytes);
>-		dcn2_0_soc.num_banks =
>+		dcn2_0_nv12_soc.num_banks =
> 				le32_to_cpu(bb->num_banks);
>-		dcn2_0_soc.num_chans =
>+		dcn2_0_nv12_soc.num_chans =
> 				le32_to_cpu(bb->num_chans);
>-		dcn2_0_soc.vmm_page_size_bytes =
>+		dcn2_0_nv12_soc.vmm_page_size_bytes =
> 				le32_to_cpu(bb->vmm_page_size_bytes);
>-		dcn2_0_soc.dram_clock_change_latency_us =
>+		dcn2_0_nv12_soc.dram_clock_change_latency_us =
> 				fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
> 		// HACK!! Lower uclock latency switch time so we don't switch
>-		dcn2_0_soc.dram_clock_change_latency_us = 10;
>-		dcn2_0_soc.writeback_dram_clock_change_latency_us =
>+		dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
>+		dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
> 				fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
>-		dcn2_0_soc.return_bus_width_bytes =
>+		dcn2_0_nv12_soc.return_bus_width_bytes =
> 				le32_to_cpu(bb->return_bus_width_bytes);
>-		dcn2_0_soc.dispclk_dppclk_vco_speed_mhz =
>+		dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
> 				le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
>-		dcn2_0_soc.xfc_bus_transport_time_us =
>+		dcn2_0_nv12_soc.xfc_bus_transport_time_us =
> 				le32_to_cpu(bb->xfc_bus_transport_time_us);
>-		dcn2_0_soc.xfc_xbuf_latency_tolerance_us =
>+		dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
> 				le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
>-		dcn2_0_soc.use_urgent_burst_bw =
>+		dcn2_0_nv12_soc.use_urgent_burst_bw =
> 				le32_to_cpu(bb->use_urgent_burst_bw);
>-		dcn2_0_soc.num_states =
>+		dcn2_0_nv12_soc.num_states =
> 				le32_to_cpu(bb->num_states);
> 
>-		for (i = 0; i < dcn2_0_soc.num_states; i++) {
>-			dcn2_0_soc.clock_limits[i].state =
>+		for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
>+			dcn2_0_nv12_soc.clock_limits[i].state =
> 					le32_to_cpu(bb->clock_limits[i].state);
>-			dcn2_0_soc.clock_limits[i].dcfclk_mhz =
>+			dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
> 					fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
>-			dcn2_0_soc.clock_limits[i].fabricclk_mhz =
>+			dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
> 					fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
>-			dcn2_0_soc.clock_limits[i].dispclk_mhz =
>+			dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
> 					fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
>-			dcn2_0_soc.clock_limits[i].dppclk_mhz =
>+			dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
> 					fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
>-			dcn2_0_soc.clock_limits[i].phyclk_mhz =
>+			dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
> 					fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
>-			dcn2_0_soc.clock_limits[i].socclk_mhz =
>+			dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
> 					fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
>-			dcn2_0_soc.clock_limits[i].dscclk_mhz =
>+			dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
> 					fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
>-			dcn2_0_soc.clock_limits[i].dram_speed_mts =
>+			dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
> 					fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
> 		}
> 	}
>@@ -2833,7 +3264,6 @@
> 		struct pp_smu_nv_clock_table max_clocks = {0};
> 		unsigned int uclk_states[8] = {0};
> 		unsigned int num_states = 0;
>-		int i;
> 		enum pp_smu_status status;
> 		bool clock_limits_available = false;
> 		bool uclk_states_available = false;
>@@ -2855,19 +3285,15 @@
> 			clock_limits_available = (status == PP_SMU_RESULT_OK);
> 		}
> 
>-		// HACK: Use the max uclk_states value for all elements.
>-		for (i = 0; i < num_states; i++)
>-			uclk_states[i] = uclk_states[num_states - 1];
>-
> 		if (clock_limits_available && uclk_states_available && num_states)
>-			update_bounding_box(dc, &dcn2_0_soc, &max_clocks, uclk_states, num_states);
>+			update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
> 		else if (clock_limits_available)
>-			cap_soc_clocks(&dcn2_0_soc, max_clocks);
>+			cap_soc_clocks(loaded_bb, max_clocks);
> 	}
> 
>-	dcn2_0_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
>-	dcn2_0_ip.max_num_dpp = pool->base.pipe_count;
>-	patch_bounding_box(dc, &dcn2_0_soc);
>+	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
>+	loaded_ip->max_num_dpp = pool->base.pipe_count;
>+	patch_bounding_box(dc, loaded_bb);
> 
> 	return true;
> }
>@@ -2880,19 +3306,30 @@
> 	int i;
> 	struct dc_context *ctx = dc->ctx;
> 	struct irq_service_init_data init_data;
>+	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
>+			get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
>+	struct _vcs_dpi_ip_params_st *loaded_ip =
>+			get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
>+	enum dml_project dml_project_version =
>+			get_dml_project_version(ctx->asic_id.hw_internal_rev);
> 
> 	ctx->dc_bios->regs = &bios_regs;
>-
>-	pool->base.res_cap = &res_cap_nv10;
> 	pool->base.funcs = &dcn20_res_pool_funcs;
> 
>+	if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
>+		pool->base.res_cap = &res_cap_nv14;
>+		pool->base.pipe_count = 5;
>+		pool->base.mpcc_count = 5;
>+	} else {
>+		pool->base.res_cap = &res_cap_nv10;
>+		pool->base.pipe_count = 6;
>+		pool->base.mpcc_count = 6;
>+	}
> 	/*************************************************
> 	 *  Resource + asic cap harcoding                *
> 	 *************************************************/
> 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
> 
>-	pool->base.pipe_count = 6;
>-	pool->base.mpcc_count = 6;
> 	dc->caps.max_downscale_ratio = 200;
> 	dc->caps.i2c_speed_in_khz = 100;
> 	dc->caps.max_cursor_size = 256;
>@@ -2998,7 +3435,7 @@
> 		goto create_fail;
> 	}
> 
>-	dml_init_instance(&dc->dml, &dcn2_0_soc, &dcn2_0_ip, DML_PROJECT_NAVI10);
>+	dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
> 
> 	if (!dc->debug.disable_pplib_wm_range) {
> 		struct pp_smu_wm_range_sets ranges = {0};
>@@ -3006,7 +3443,7 @@
> 
> 		ranges.num_reader_wm_sets = 0;
> 
>-		if (dcn2_0_soc.num_states == 1) {
>+		if (loaded_bb->num_states == 1) {
> 			ranges.reader_wm_sets[0].wm_inst = i;
> 			ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
> 			ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
>@@ -3014,13 +3451,13 @@
> 			ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
> 
> 			ranges.num_reader_wm_sets = 1;
>-		} else if (dcn2_0_soc.num_states > 1) {
>-			for (i = 0; i < 4 && i < dcn2_0_soc.num_states; i++) {
>+		} else if (loaded_bb->num_states > 1) {
>+			for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
> 				ranges.reader_wm_sets[i].wm_inst = i;
> 				ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
> 				ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
>-				ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (dcn2_0_soc.clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
>-				ranges.reader_wm_sets[i].max_fill_clk_mhz = dcn2_0_soc.clock_limits[i].dram_speed_mts / 16;
>+				ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
>+				ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
> 
> 				ranges.num_reader_wm_sets = i + 1;
> 			}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h	2019-08-31 15:01:11.866736169 -0500
>@@ -116,6 +116,18 @@
> 		display_e2e_pipe_params_st *pipes,
> 		int pipe_cnt);
> bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate);
>+bool dcn20_fast_validate_bw(
>+		struct dc *dc,
>+		struct dc_state *context,
>+		display_e2e_pipe_params_st *pipes,
>+		int *pipe_cnt_out,
>+		int *pipe_split_from,
>+		int *vlevel_out);
>+void dcn20_calculate_dlg_params(
>+		struct dc *dc, struct dc_state *context,
>+		display_e2e_pipe_params_st *pipes,
>+		int pipe_cnt,
>+		int vlevel);
> 
> enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
> enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c	2019-08-31 15:01:11.866736169 -0500
>@@ -207,9 +207,8 @@
> 
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> 
>-
> /* Update GSP7 SDP 128 byte long */
>-static void enc2_send_gsp7_128_info_packet(
>+static void enc2_update_gsp7_128_info_packet(
> 	struct dcn10_stream_encoder *enc1,
> 	const struct dc_info_packet_128 *info_packet)
> {
>@@ -277,18 +276,9 @@
> static void enc2_dp_set_dsc_config(struct stream_encoder *enc,
> 					enum optc_dsc_mode dsc_mode,
> 					uint32_t dsc_bytes_per_pixel,
>-					uint32_t dsc_slice_width,
>-					uint8_t *dsc_packed_pps)
>+					uint32_t dsc_slice_width)
> {
> 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
>-	uint32_t dsc_value = 0;
>-
>-	dsc_value = REG_READ(DP_DSC_CNTL);
>-
>-	/* dsc disable skip */
>-	if ((dsc_value & 0x3) == 0x0)
>-		return;
>-
> 
> 	REG_UPDATE_2(DP_DSC_CNTL,
> 			DP_DSC_MODE, dsc_mode,
>@@ -296,8 +286,16 @@
> 
> 	REG_SET(DP_DSC_BYTES_PER_PIXEL, 0,
> 		DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
>+}
>+
> 
>-	if (dsc_mode != OPTC_DSC_DISABLED) {
>+static void enc2_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
>+					bool enable,
>+					uint8_t *dsc_packed_pps)
>+{
>+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
>+
>+	if (enable) {
> 		struct dc_info_packet_128 pps_sdp;
> 
> 		ASSERT(dsc_packed_pps);
>@@ -309,7 +307,7 @@
> 		pps_sdp.hb2 = 127;
> 		pps_sdp.hb3 = 0;
> 		memcpy(&pps_sdp.sb[0], dsc_packed_pps, sizeof(pps_sdp.sb));
>-		enc2_send_gsp7_128_info_packet(enc1, &pps_sdp);
>+		enc2_update_gsp7_128_info_packet(enc1, &pps_sdp);
> 
> 		/* Enable Generic Stream Packet 7 (GSP) transmission */
> 		//REG_UPDATE(DP_SEC_CNTL,
>@@ -340,9 +338,8 @@
> 		REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 0);
> 	}
> }
>-#endif
> 
>-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+
> /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
>  * into a dcn_dsc_state struct.
>  */
>@@ -373,7 +370,7 @@
>  *
>  *   Ensure the OTG master update lock is set when changing DME configuration.
>  */
>-static void enc2_set_dynamic_metadata(struct stream_encoder *enc,
>+void enc2_set_dynamic_metadata(struct stream_encoder *enc,
> 		bool enable_dme,
> 		uint32_t hubp_requestor_id,
> 		enum dynamic_metadata_mode dmdata_mode)
>@@ -463,7 +460,7 @@
> 		uint64_t m_vid_l = n_vid;
> 
> 		/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
>-		if (is_two_pixels_per_containter(&param->timing) || param->odm) {
>+		if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) {
> 			/*this logic should be the same in get_pixel_clock_parameters() */
> 			n_multiply = 1;
> 		}
>@@ -580,14 +577,14 @@
> 	.setup_stereo_sync  = enc1_setup_stereo_sync,
> 	.set_avmute = enc1_stream_encoder_set_avmute,
> 	.dig_connect_to_otg  = enc1_dig_connect_to_otg,
>+	.dig_source_otg = enc1_dig_source_otg,
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> 	.enc_read_state = enc2_read_state,
>-#endif
>-
>-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> 	.dp_set_dsc_config = enc2_dp_set_dsc_config,
>+	.dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet,
> #endif
> 	.set_dynamic_metadata = enc2_set_dynamic_metadata,
>+	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
> };
> 
> void dcn20_stream_encoder_construct(
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h	2019-08-31 15:01:11.866736169 -0500
>@@ -104,4 +104,9 @@
> 	struct stream_encoder *enc,
> 	const struct encoder_unblank_param *param);
> 
>+void enc2_set_dynamic_metadata(struct stream_encoder *enc,
>+		bool enable_dme,
>+		uint32_t hubp_requestor_id,
>+		enum dynamic_metadata_mode dmdata_mode);
>+
> #endif /* __DC_STREAM_ENCODER_DCN20_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn20/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn20/Makefile	2019-08-31 15:01:11.864736169 -0500
>@@ -18,6 +18,10 @@
> 
> CFLAGS_dcn20_resource.o := -mhard-float -msse $(cc_stack_align)
> 
>+ifdef CONFIG_CC_IS_CLANG
>+CFLAGS_dcn20_resource.o += -msse2
>+endif
>+
> AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
> 
> AMD_DISPLAY_FILES += $(AMD_DAL_DCN20)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c	2019-08-31 15:01:11.866736169 -0500
>@@ -0,0 +1,595 @@
>+/*
>+* Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+#include "dm_services.h"
>+#include "dcn20/dcn20_hubbub.h"
>+#include "dcn21_hubbub.h"
>+#include "reg_helper.h"
>+
>+#define REG(reg)\
>+	hubbub1->regs->reg
>+#define DC_LOGGER \
>+	hubbub1->base.ctx->logger
>+#define CTX \
>+	hubbub1->base.ctx
>+
>+#undef FN
>+#define FN(reg_name, field_name) \
>+	hubbub1->shifts->field_name, hubbub1->masks->field_name
>+
>+#define REG(reg)\
>+	hubbub1->regs->reg
>+
>+#define CTX \
>+	hubbub1->base.ctx
>+
>+#undef FN
>+#define FN(reg_name, field_name) \
>+	hubbub1->shifts->field_name, hubbub1->masks->field_name
>+
>+#ifdef NUM_VMID
>+#undef NUM_VMID
>+#endif
>+#define NUM_VMID 1
>+
>+static uint32_t convert_and_clamp(
>+	uint32_t wm_ns,
>+	uint32_t refclk_mhz,
>+	uint32_t clamp_value)
>+{
>+	uint32_t ret_val = 0;
>+	ret_val = wm_ns * refclk_mhz;
>+	ret_val /= 1000;
>+
>+	if (ret_val > clamp_value)
>+		ret_val = clamp_value;
>+
>+	return ret_val;
>+}
>+
>+void dcn21_dchvm_init(struct hubbub *hubbub)
>+{
>+	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
>+
>+	//Init DCHVM block
>+	REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);
>+
>+	//Poll until RIOMMU_ACTIVE = 1
>+	//TODO: Figure out interval us and retry count
>+	REG_WAIT(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, 1, 5, 100);
>+
>+	//Reflect the power status of DCHUBBUB
>+	REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);
>+
>+	//Start rIOMMU prefetching
>+	REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);
>+
>+	// Enable dynamic clock gating
>+	REG_UPDATE_4(DCHVM_CLK_CTRL,
>+					HVM_DISPCLK_R_GATE_DIS, 0,
>+					HVM_DISPCLK_G_GATE_DIS, 0,
>+					HVM_DCFCLK_R_GATE_DIS, 0,
>+					HVM_DCFCLK_G_GATE_DIS, 0);
>+
>+	//Poll until HOSTVM_PREFETCH_DONE = 1
>+	//TODO: Figure out interval us and retry count
>+	REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
>+}
>+
>+static int hubbub21_init_dchub(struct hubbub *hubbub,
>+		struct dcn_hubbub_phys_addr_config *pa_config)
>+{
>+	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
>+
>+	REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
>+		FB_BASE, pa_config->system_aperture.fb_base);
>+	REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
>+			FB_TOP, pa_config->system_aperture.fb_top);
>+	REG_SET(DCN_VM_FB_OFFSET, 0,
>+			FB_OFFSET, pa_config->system_aperture.fb_offset);
>+	REG_SET(DCN_VM_AGP_BOT, 0,
>+			AGP_BOT, pa_config->system_aperture.agp_bot);
>+	REG_SET(DCN_VM_AGP_TOP, 0,
>+			AGP_TOP, pa_config->system_aperture.agp_top);
>+	REG_SET(DCN_VM_AGP_BASE, 0,
>+			AGP_BASE, pa_config->system_aperture.agp_base);
>+
>+	dcn21_dchvm_init(hubbub);
>+
>+	return NUM_VMID;
>+}
>+
>+static void hubbub21_program_urgent_watermarks(
>+		struct hubbub *hubbub,
>+		struct dcn_watermark_set *watermarks,
>+		unsigned int refclk_mhz,
>+		bool safe_to_lower)
>+{
>+	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
>+	uint32_t prog_wm_value;
>+
>+	/* Repeat for water mark set A, B, C and D. */
>+	/* clock state A */
>+	if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) {
>+		hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
>+		prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
>+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, prog_wm_value);
>+
>+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n"
>+			"HW register value = 0x%x\n",
>+			watermarks->a.urgent_ns, prog_wm_value);
>+	}
>+
>+	/* determine the transfer time for a quantity of data for a particular requestor.*/
>+	if (safe_to_lower || watermarks->a.frac_urg_bw_flip
>+			> hubbub1->watermarks.a.frac_urg_bw_flip) {
>+		hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;
>+
>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,
>+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip);
>+	}
>+
>+	if (safe_to_lower || watermarks->a.frac_urg_bw_nom
>+			> hubbub1->watermarks.a.frac_urg_bw_nom) {
>+		hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;
>+
>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,
>+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom);
>+	}
>+
>+	/* clock state B */
>+	if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) {
>+		hubbub1->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
>+		prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
>+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, prog_wm_value);
>+
>+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n"
>+			"HW register value = 0x%x\n",
>+			watermarks->b.urgent_ns, prog_wm_value);
>+	}
>+
>+	/* determine the transfer time for a quantity of data for a particular requestor.*/
>+	if (safe_to_lower || watermarks->a.frac_urg_bw_flip
>+			> hubbub1->watermarks.a.frac_urg_bw_flip) {
>+		hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;
>+
>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,
>+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->a.frac_urg_bw_flip);
>+	}
>+
>+	if (safe_to_lower || watermarks->a.frac_urg_bw_nom
>+			> hubbub1->watermarks.a.frac_urg_bw_nom) {
>+		hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;
>+
>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,
>+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->a.frac_urg_bw_nom);
>+	}
>+
>+	/* clock state C */
>+	if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) {
>+		hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
>+		prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
>+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, prog_wm_value);
>+
>+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n"
>+			"HW register value = 0x%x\n",
>+			watermarks->c.urgent_ns, prog_wm_value);
>+	}
>+
>+	/* determine the transfer time for a quantity of data for a particular requestor.*/
>+	if (safe_to_lower || watermarks->a.frac_urg_bw_flip
>+			> hubbub1->watermarks.a.frac_urg_bw_flip) {
>+		hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;
>+
>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0,
>+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->a.frac_urg_bw_flip);
>+	}
>+
>+	if (safe_to_lower || watermarks->a.frac_urg_bw_nom
>+			> hubbub1->watermarks.a.frac_urg_bw_nom) {
>+		hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;
>+
>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0,
>+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->a.frac_urg_bw_nom);
>+	}
>+
>+	/* clock state D */
>+	if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) {
>+		hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
>+		prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,
>+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, prog_wm_value);
>+
>+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n"
>+			"HW register value = 0x%x\n",
>+			watermarks->d.urgent_ns, prog_wm_value);
>+	}
>+
>+	/* determine the transfer time for a quantity of data for a particular requestor.*/
>+	if (safe_to_lower || watermarks->a.frac_urg_bw_flip
>+			> hubbub1->watermarks.a.frac_urg_bw_flip) {
>+		hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;
>+
>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0,
>+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->a.frac_urg_bw_flip);
>+	}
>+
>+	if (safe_to_lower || watermarks->a.frac_urg_bw_nom
>+			> hubbub1->watermarks.a.frac_urg_bw_nom) {
>+		hubbub1->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;
>+
>+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,
>+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->a.frac_urg_bw_nom);
>+	}
>+}
>+
>+static void hubbub21_program_stutter_watermarks(
>+		struct hubbub *hubbub,
>+		struct dcn_watermark_set *watermarks,
>+		unsigned int refclk_mhz,
>+		bool safe_to_lower)
>+{
>+	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
>+	uint32_t prog_wm_value;
>+
>+	/* clock state A */
>+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
>+			> hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {
>+		hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
>+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;
>+		prog_wm_value = convert_and_clamp(
>+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,
>+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
>+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
>+			"HW register value = 0x%x\n",
>+			watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
>+	}
>+
>+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns
>+			> hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns) {
>+		hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns =
>+				watermarks->a.cstate_pstate.cstate_exit_ns;
>+		prog_wm_value = convert_and_clamp(
>+				watermarks->a.cstate_pstate.cstate_exit_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,
>+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
>+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"
>+			"HW register value = 0x%x\n",
>+			watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
>+	}
>+
>+	/* clock state B */
>+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
>+			> hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {
>+		hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
>+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;
>+		prog_wm_value = convert_and_clamp(
>+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,
>+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
>+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"
>+			"HW register value = 0x%x\n",
>+			watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
>+	}
>+
>+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns
>+			> hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns) {
>+		hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns =
>+				watermarks->b.cstate_pstate.cstate_exit_ns;
>+		prog_wm_value = convert_and_clamp(
>+				watermarks->b.cstate_pstate.cstate_exit_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,
>+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
>+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"
>+			"HW register value = 0x%x\n",
>+			watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
>+	}
>+
>+	/* clock state C */
>+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
>+			> hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {
>+		hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
>+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;
>+		prog_wm_value = convert_and_clamp(
>+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,
>+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
>+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n"
>+			"HW register value = 0x%x\n",
>+			watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
>+	}
>+
>+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns
>+			> hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns) {
>+		hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns =
>+				watermarks->c.cstate_pstate.cstate_exit_ns;
>+		prog_wm_value = convert_and_clamp(
>+				watermarks->c.cstate_pstate.cstate_exit_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,
>+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
>+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"
>+			"HW register value = 0x%x\n",
>+			watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
>+	}
>+
>+	/* clock state D */
>+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
>+			> hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {
>+		hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
>+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;
>+		prog_wm_value = convert_and_clamp(
>+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,
>+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
>+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n"
>+			"HW register value = 0x%x\n",
>+			watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
>+	}
>+
>+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns
>+			> hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns) {
>+		hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns =
>+				watermarks->d.cstate_pstate.cstate_exit_ns;
>+		prog_wm_value = convert_and_clamp(
>+				watermarks->d.cstate_pstate.cstate_exit_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,
>+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
>+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"
>+			"HW register value = 0x%x\n",
>+			watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
>+	}
>+}
>+
>+static void hubbub21_program_pstate_watermarks(
>+		struct hubbub *hubbub,
>+		struct dcn_watermark_set *watermarks,
>+		unsigned int refclk_mhz,
>+		bool safe_to_lower)
>+{
>+	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
>+	uint32_t prog_wm_value;
>+
>+	/* clock state A */
>+	if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns
>+			> hubbub1->watermarks.a.cstate_pstate.pstate_change_ns) {
>+		hubbub1->watermarks.a.cstate_pstate.pstate_change_ns =
>+				watermarks->a.cstate_pstate.pstate_change_ns;
>+		prog_wm_value = convert_and_clamp(
>+				watermarks->a.cstate_pstate.pstate_change_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0,
>+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
>+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
>+			"HW register value = 0x%x\n\n",
>+			watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
>+	}
>+
>+	/* clock state B */
>+	if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns
>+			> hubbub1->watermarks.b.cstate_pstate.pstate_change_ns) {
>+		hubbub1->watermarks.b.cstate_pstate.pstate_change_ns =
>+				watermarks->b.cstate_pstate.pstate_change_ns;
>+		prog_wm_value = convert_and_clamp(
>+				watermarks->b.cstate_pstate.pstate_change_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0,
>+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
>+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n"
>+			"HW register value = 0x%x\n\n",
>+			watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
>+	}
>+
>+	/* clock state C */
>+	if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns
>+			> hubbub1->watermarks.c.cstate_pstate.pstate_change_ns) {
>+		hubbub1->watermarks.c.cstate_pstate.pstate_change_ns =
>+				watermarks->c.cstate_pstate.pstate_change_ns;
>+		prog_wm_value = convert_and_clamp(
>+				watermarks->c.cstate_pstate.pstate_change_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0,
>+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
>+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n"
>+			"HW register value = 0x%x\n\n",
>+			watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
>+	}
>+
>+	/* clock state D */
>+	if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns
>+			> hubbub1->watermarks.d.cstate_pstate.pstate_change_ns) {
>+		hubbub1->watermarks.d.cstate_pstate.pstate_change_ns =
>+				watermarks->d.cstate_pstate.pstate_change_ns;
>+		prog_wm_value = convert_and_clamp(
>+				watermarks->d.cstate_pstate.pstate_change_ns,
>+				refclk_mhz, 0x1fffff);
>+		REG_SET_2(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0,
>+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value,
>+				DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
>+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
>+			"HW register value = 0x%x\n\n",
>+			watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
>+	}
>+}
>+
>+void hubbub21_program_watermarks(
>+		struct hubbub *hubbub,
>+		struct dcn_watermark_set *watermarks,
>+		unsigned int refclk_mhz,
>+		bool safe_to_lower)
>+{
>+	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
>+
>+	hubbub21_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
>+	hubbub21_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
>+	hubbub21_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
>+
>+	/*
>+	 * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric.
>+	 * If the memory controller is fully utilized and the DCHub requestors are
>+	 * well ahead of their amortized schedule, then it is safe to prevent the next winner
>+	 * from being committed and sent to the fabric.
>+	 * The utilization of the memory controller is approximated by ensuring that
>+	 * the number of outstanding requests is greater than a threshold specified
>+	 * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule,
>+	 * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles.
>+	 *
>+	 * TODO: Revisit request limit after figure out right number. request limit for Renoir isn't decided yet, set maximum value (0x1FF)
>+	 * to turn off it for now.
>+	 */
>+	REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
>+			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
>+	REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
>+			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF,
>+			DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA);
>+	REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL,
>+			DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF);
>+
>+	hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
>+}
>+
>+void hubbub21_wm_read_state(struct hubbub *hubbub,
>+		struct dcn_hubbub_wm *wm)
>+{
>+	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
>+	struct dcn_hubbub_wm_set *s;
>+
>+	memset(wm, 0, sizeof(struct dcn_hubbub_wm));
>+
>+	s = &wm->sets[0];
>+	s->wm_set = 0;
>+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A,
>+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, &s->data_urgent);
>+
>+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A,
>+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, &s->sr_enter);
>+
>+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A,
>+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, &s->sr_exit);
>+
>+	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A,
>+			 DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, &s->dram_clk_chanage);
>+
>+	s = &wm->sets[1];
>+	s->wm_set = 1;
>+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B,
>+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, &s->data_urgent);
>+
>+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B,
>+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, &s->sr_enter);
>+
>+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B,
>+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, &s->sr_exit);
>+
>+	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B,
>+			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, &s->dram_clk_chanage);
>+
>+	s = &wm->sets[2];
>+	s->wm_set = 2;
>+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C,
>+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, &s->data_urgent);
>+
>+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C,
>+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, &s->sr_enter);
>+
>+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C,
>+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, &s->sr_exit);
>+
>+	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C,
>+			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, &s->dram_clk_chanage);
>+
>+	s = &wm->sets[3];
>+	s->wm_set = 3;
>+	REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D,
>+			DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, &s->data_urgent);
>+
>+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D,
>+			DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, &s->sr_enter);
>+
>+	REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D,
>+			DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, &s->sr_exit);
>+
>+	REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D,
>+			DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, &s->dram_clk_chanage);
>+}
>+
>+
>+static const struct hubbub_funcs hubbub21_funcs = {
>+	.update_dchub = hubbub2_update_dchub,
>+	.init_dchub_sys_ctx = hubbub21_init_dchub,
>+	.init_vm_ctx = NULL,
>+	.dcc_support_swizzle = hubbub2_dcc_support_swizzle,
>+	.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
>+	.get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
>+	.wm_read_state = hubbub21_wm_read_state,
>+	.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
>+	.program_watermarks = hubbub21_program_watermarks,
>+};
>+
>+void hubbub21_construct(struct dcn20_hubbub *hubbub,
>+	struct dc_context *ctx,
>+	const struct dcn_hubbub_registers *hubbub_regs,
>+	const struct dcn_hubbub_shift *hubbub_shift,
>+	const struct dcn_hubbub_mask *hubbub_mask)
>+{
>+	hubbub->base.ctx = ctx;
>+
>+	hubbub->base.funcs = &hubbub21_funcs;
>+
>+	hubbub->regs = hubbub_regs;
>+	hubbub->shifts = hubbub_shift;
>+	hubbub->masks = hubbub_mask;
>+
>+	hubbub->debug_test_index_pstate = 0xB;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h	2019-08-31 15:01:11.866736169 -0500
>@@ -0,0 +1,132 @@
>+/*
>+* Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+#ifndef DAL_DC_DCN21_DCN21_HUBBUB_H_
>+#define DAL_DC_DCN21_DCN21_HUBBUB_H_
>+
>+#include "dcn20/dcn20_hubbub.h"
>+
>+#define HUBBUB_HVM_REG_LIST() \
>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\
>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\
>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\
>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\
>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\
>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
>+	SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
>+	SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
>+	SR(DCHVM_CTRL0), \
>+	SR(DCHVM_MEM_CTRL), \
>+	SR(DCHVM_CLK_CTRL), \
>+	SR(DCHVM_RIOMMU_CTRL0), \
>+	SR(DCHVM_RIOMMU_STAT0)
>+
>+#define HUBBUB_REG_LIST_DCN21()\
>+	HUBBUB_REG_LIST_DCN_COMMON(), \
>+	HUBBUB_SR_WATERMARK_REG_LIST(), \
>+	HUBBUB_HVM_REG_LIST(), \
>+	SR(DCHUBBUB_CRC_CTRL), \
>+	SR(DCN_VM_FB_LOCATION_BASE),\
>+	SR(DCN_VM_FB_LOCATION_TOP),\
>+	SR(DCN_VM_FB_OFFSET),\
>+	SR(DCN_VM_AGP_BOT),\
>+	SR(DCN_VM_AGP_TOP),\
>+	SR(DCN_VM_AGP_BASE)
>+
>+#define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \
>+	HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh), \
>+	HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh), \
>+	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh), \
>+	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh), \
>+	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh), \
>+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh), \
>+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh), \
>+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh), \
>+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh), \
>+	HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh), \
>+	HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh), \
>+	HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh), \
>+	HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh), \
>+	HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh), \
>+	HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh)
>+
>+#define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\
>+	HUBBUB_MASK_SH_LIST_HVM(mask_sh),\
>+	HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
>+	HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
>+	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
>+	HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \
>+	HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
>+	HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
>+	HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
>+	HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
>+	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh)
>+
>+void dcn21_dchvm_init(struct hubbub *hubbub);
>+void hubbub21_program_watermarks(
>+		struct hubbub *hubbub,
>+		struct dcn_watermark_set *watermarks,
>+		unsigned int refclk_mhz,
>+		bool safe_to_lower);
>+
>+void hubbub21_wm_read_state(struct hubbub *hubbub,
>+		struct dcn_hubbub_wm *wm);
>+
>+void hubbub21_construct(struct dcn20_hubbub *hubbub,
>+	struct dc_context *ctx,
>+	const struct dcn_hubbub_registers *hubbub_regs,
>+	const struct dcn_hubbub_shift *hubbub_shift,
>+	const struct dcn_hubbub_mask *hubbub_mask);
>+
>+#endif /* DAL_DC_DCN21_DCN21_HUBBUB_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c	2019-08-31 15:01:11.866736169 -0500
>@@ -0,0 +1,244 @@
>+/*
>+* Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+#include "dcn21_hubp.h"
>+
>+#include "dm_services.h"
>+#include "reg_helper.h"
>+
>+#define REG(reg)\
>+	hubp21->hubp_regs->reg
>+
>+#define CTX \
>+	hubp21->base.ctx
>+
>+#undef FN
>+#define FN(reg_name, field_name) \
>+	hubp21->hubp_shift->field_name, hubp21->hubp_mask->field_name
>+
>+/*
>+ * In DCN2.1, the non-double buffered version of the following 4 DLG registers are used in RTL.
>+ * As a result, if S/W updates any of these registers during a mode change,
>+ * the current frame before the mode change will use the new value right away
>+ * and can lead to generating incorrect request deadlines and incorrect TTU/QoS behavior.
>+ *
>+ * REFCYC_PER_VM_GROUP_FLIP[22:0]
>+ * REFCYC_PER_VM_GROUP_VBLANK[22:0]
>+ * REFCYC_PER_VM_REQ_FLIP[22:0]
>+ * REFCYC_PER_VM_REQ_VBLANK[22:0]
>+ *
>+ * REFCYC_PER_VM_*_FLIP affects the deadline of the VM requests generated
>+ * when flipping to a new surface
>+ *
>+ * REFCYC_PER_VM_*_VBLANK affects the deadline of the VM requests generated
>+ * during prefetch  period of a frame. The prefetch starts at a pre-determined
>+ * number of lines before the display active per frame
>+ *
>+ * DCN may underflow due to incorrectly programming these registers
>+ * during VM stage of prefetch/iflip. First lines of display active
>+ * or a sub-region of active using a new surface will be corrupted
>+ * until the VM data returns at flip/mode change transitions
>+ *
>+ * Work around:
>+ * workaround is always opt to use the more aggressive settings.
>+ * On any mode switch, if the new reg values are smaller than the current values,
>+ * then update the regs with the new values.
>+ *
>+ * Link to the ticket: http://ontrack-internal.amd.com/browse/DEDCN21-142
>+ *
>+ */
>+void apply_DEDCN21_142_wa_for_hostvm_deadline(
>+		struct hubp *hubp,
>+		struct _vcs_dpi_display_dlg_regs_st *dlg_attr)
>+{
>+	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
>+	uint32_t cur_value;
>+
>+	REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value);
>+	if (cur_value > dlg_attr->refcyc_per_vm_group_vblank)
>+		REG_SET(VBLANK_PARAMETERS_5, 0,
>+				REFCYC_PER_VM_GROUP_VBLANK, dlg_attr->refcyc_per_vm_group_vblank);
>+
>+	REG_GET(VBLANK_PARAMETERS_6,
>+			REFCYC_PER_VM_REQ_VBLANK,
>+			&cur_value);
>+	if (cur_value > dlg_attr->refcyc_per_vm_req_vblank)
>+		REG_SET(VBLANK_PARAMETERS_6, 0,
>+				REFCYC_PER_VM_REQ_VBLANK, dlg_attr->refcyc_per_vm_req_vblank);
>+
>+	REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value);
>+	if (cur_value > dlg_attr->refcyc_per_vm_group_flip)
>+		REG_SET(FLIP_PARAMETERS_3, 0,
>+				REFCYC_PER_VM_GROUP_FLIP, dlg_attr->refcyc_per_vm_group_flip);
>+
>+	REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value);
>+	if (cur_value > dlg_attr->refcyc_per_vm_req_flip)
>+		REG_SET(FLIP_PARAMETERS_4, 0,
>+					REFCYC_PER_VM_REQ_FLIP, dlg_attr->refcyc_per_vm_req_flip);
>+
>+	REG_SET(FLIP_PARAMETERS_5, 0,
>+			REFCYC_PER_PTE_GROUP_FLIP_C, dlg_attr->refcyc_per_pte_group_flip_c);
>+	REG_SET(FLIP_PARAMETERS_6, 0,
>+			REFCYC_PER_META_CHUNK_FLIP_C, dlg_attr->refcyc_per_meta_chunk_flip_c);
>+}
>+
>+void hubp21_program_deadline(
>+		struct hubp *hubp,
>+		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
>+		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
>+{
>+	hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
>+
>+	apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr);
>+}
>+
>+void hubp21_program_requestor(
>+		struct hubp *hubp,
>+		struct _vcs_dpi_display_rq_regs_st *rq_regs)
>+{
>+	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
>+
>+	REG_UPDATE(HUBPRET_CONTROL,
>+			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
>+	REG_SET_4(DCN_EXPANSION_MODE, 0,
>+			DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
>+			PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
>+			MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
>+			CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
>+	REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
>+		CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
>+		MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
>+		META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
>+		MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
>+		DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
>+		VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
>+		SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
>+		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
>+	REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0,
>+		CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
>+		MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
>+		META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
>+		MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
>+		DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
>+		SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
>+		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
>+}
>+
>+static void hubp21_setup(
>+		struct hubp *hubp,
>+		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
>+		struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
>+		struct _vcs_dpi_display_rq_regs_st *rq_regs,
>+		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
>+{
>+	/* otg is locked when this func is called. Register are double buffered.
>+	 * disable the requestors is not needed
>+	 */
>+
>+	hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
>+	hubp21_program_requestor(hubp, rq_regs);
>+	hubp21_program_deadline(hubp, dlg_attr, ttu_attr);
>+
>+}
>+
>+void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
>+		struct vm_system_aperture_param *apt)
>+{
>+	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
>+
>+	PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
>+	PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
>+	PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
>+
>+	// The format of default addr is 48:12 of the 48 bit addr
>+	mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
>+
>+	// The format of high/low are 48:18 of the 48 bit addr
>+	mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
>+	mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
>+
>+	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
>+			MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
>+
>+	REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
>+			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
>+
>+	REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
>+			ENABLE_L1_TLB, 1,
>+			SYSTEM_ACCESS_MODE, 0x3);
>+}
>+
>+void hubp21_init(struct hubp *hubp)
>+{
>+	// DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
>+	// This is a chicken bit to enable the ECO fix.
>+
>+	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);
>+	//hubp[i].HUBPREQ_DEBUG.HUBPREQ_DEBUG[26] = 1;
>+	REG_WRITE(HUBPREQ_DEBUG, 1 << 26);
>+}
>+static struct hubp_funcs dcn21_hubp_funcs = {
>+	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
>+	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
>+	.hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
>+	.hubp_program_surface_config = hubp2_program_surface_config,
>+	.hubp_is_flip_pending = hubp1_is_flip_pending,
>+	.hubp_setup = hubp21_setup,
>+	.hubp_setup_interdependent = hubp2_setup_interdependent,
>+	.hubp_set_vm_system_aperture_settings = hubp21_set_vm_system_aperture_settings,
>+	.set_blank = hubp1_set_blank,
>+	.dcc_control = hubp1_dcc_control,
>+	.mem_program_viewport = min_set_viewport,
>+	.set_cursor_attributes	= hubp2_cursor_set_attributes,
>+	.set_cursor_position	= hubp1_cursor_set_position,
>+	.hubp_clk_cntl = hubp1_clk_cntl,
>+	.hubp_vtg_sel = hubp1_vtg_sel,
>+	.dmdata_set_attributes = hubp2_dmdata_set_attributes,
>+	.dmdata_load = hubp2_dmdata_load,
>+	.dmdata_status_done = hubp2_dmdata_status_done,
>+	.hubp_read_state = hubp1_read_state,
>+	.hubp_clear_underflow = hubp1_clear_underflow,
>+	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
>+	.hubp_init = hubp21_init,
>+};
>+
>+bool hubp21_construct(
>+	struct dcn21_hubp *hubp21,
>+	struct dc_context *ctx,
>+	uint32_t inst,
>+	const struct dcn_hubp2_registers *hubp_regs,
>+	const struct dcn_hubp2_shift *hubp_shift,
>+	const struct dcn_hubp2_mask *hubp_mask)
>+{
>+	hubp21->base.funcs = &dcn21_hubp_funcs;
>+	hubp21->base.ctx = ctx;
>+	hubp21->hubp_regs = hubp_regs;
>+	hubp21->hubp_shift = hubp_shift;
>+	hubp21->hubp_mask = hubp_mask;
>+	hubp21->base.inst = inst;
>+	hubp21->base.opp_id = OPP_ID_INVALID;
>+	hubp21->base.mpcc_id = 0xf;
>+
>+	return true;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h	2019-08-31 15:01:11.866736169 -0500
>@@ -0,0 +1,133 @@
>+/*
>+* Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifndef DAL_DC_DCN21_DCN21_HUBP_H_
>+#define DAL_DC_DCN21_DCN21_HUBP_H_
>+
>+#include "../dcn20/dcn20_hubp.h"
>+#include "../dcn10/dcn10_hubp.h"
>+
>+#define TO_DCN21_HUBP(hubp)\
>+	container_of(hubp, struct dcn21_hubp, base)
>+
>+#define HUBP_REG_LIST_DCN21(id)\
>+	HUBP_REG_LIST_DCN2_COMMON(id),\
>+	SRI(FLIP_PARAMETERS_3, HUBPREQ, id),\
>+	SRI(FLIP_PARAMETERS_4, HUBPREQ, id),\
>+	SRI(FLIP_PARAMETERS_5, HUBPREQ, id),\
>+	SRI(FLIP_PARAMETERS_6, HUBPREQ, id),\
>+	SRI(VBLANK_PARAMETERS_5, HUBPREQ, id),\
>+	SRI(VBLANK_PARAMETERS_6, HUBPREQ, id)
>+
>+#define HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh)\
>+	HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\
>+	HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
>+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
>+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
>+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
>+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
>+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
>+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
>+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
>+	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
>+	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
>+	HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
>+	HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
>+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
>+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
>+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
>+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
>+	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
>+	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
>+	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
>+	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
>+	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
>+	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
>+	HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
>+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
>+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
>+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
>+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
>+	HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\
>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\
>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\
>+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
>+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
>+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
>+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)
>+
>+#define HUBP_MASK_SH_LIST_DCN21(mask_sh)\
>+	HUBP_MASK_SH_LIST_DCN21_COMMON(mask_sh),\
>+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh)
>+
>+
>+struct dcn21_hubp {
>+	struct hubp base;
>+	struct dcn_hubp_state state;
>+	const struct dcn_hubp2_registers *hubp_regs;
>+	const struct dcn_hubp2_shift *hubp_shift;
>+	const struct dcn_hubp2_mask *hubp_mask;
>+};
>+
>+bool hubp21_construct(
>+	struct dcn21_hubp *hubp21,
>+	struct dc_context *ctx,
>+	uint32_t inst,
>+	const struct dcn_hubp2_registers *hubp_regs,
>+	const struct dcn_hubp2_shift *hubp_shift,
>+	const struct dcn_hubp2_mask *hubp_mask);
>+
>+void apply_DEDCN21_142_wa_for_hostvm_deadline(
>+		struct hubp *hubp,
>+		struct _vcs_dpi_display_dlg_regs_st *dlg_attr);
>+
>+void hubp21_program_deadline(
>+		struct hubp *hubp,
>+		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
>+		struct _vcs_dpi_display_ttu_regs_st *ttu_attr);
>+
>+void hubp21_program_requestor(
>+		struct hubp *hubp,
>+		struct _vcs_dpi_display_rq_regs_st *rq_regs);
>+#endif /* DAL_DC_DCN21_DCN21_HUBP_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c	2019-08-31 15:01:11.866736169 -0500
>@@ -0,0 +1,1680 @@
>+/*
>+* Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#include "dm_services.h"
>+#include "dc.h"
>+
>+#include "resource.h"
>+#include "include/irq_service_interface.h"
>+#include "dcn20/dcn20_resource.h"
>+
>+#include "clk_mgr.h"
>+#include "dcn10/dcn10_hubp.h"
>+#include "dcn10/dcn10_ipp.h"
>+#include "dcn20/dcn20_hubbub.h"
>+#include "dcn20/dcn20_mpc.h"
>+#include "dcn20/dcn20_hubp.h"
>+#include "dcn21_hubp.h"
>+#include "irq/dcn21/irq_service_dcn21.h"
>+#include "dcn20/dcn20_dpp.h"
>+#include "dcn20/dcn20_optc.h"
>+#include "dcn20/dcn20_hwseq.h"
>+#include "dce110/dce110_hw_sequencer.h"
>+#include "dcn20/dcn20_opp.h"
>+#include "dcn20/dcn20_dsc.h"
>+#include "dcn20/dcn20_link_encoder.h"
>+#include "dcn20/dcn20_stream_encoder.h"
>+#include "dce/dce_clock_source.h"
>+#include "dce/dce_audio.h"
>+#include "dce/dce_hwseq.h"
>+#include "virtual/virtual_stream_encoder.h"
>+#include "dce110/dce110_resource.h"
>+#include "dml/display_mode_vba.h"
>+#include "dcn20/dcn20_dccg.h"
>+#include "dcn21_hubbub.h"
>+#include "dcn10/dcn10_resource.h"
>+
>+#include "dcn20/dcn20_dwb.h"
>+#include "dcn20/dcn20_mmhubbub.h"
>+
>+#include "renoir_ip_offset.h"
>+#include "dcn/dcn_2_1_0_offset.h"
>+#include "dcn/dcn_2_1_0_sh_mask.h"
>+
>+#include "nbio/nbio_7_0_offset.h"
>+
>+#include "mmhub/mmhub_2_0_0_offset.h"
>+#include "mmhub/mmhub_2_0_0_sh_mask.h"
>+
>+#include "reg_helper.h"
>+#include "dce/dce_abm.h"
>+#include "dce/dce_dmcu.h"
>+#include "dce/dce_aux.h"
>+#include "dce/dce_i2c.h"
>+#include "dcn21_resource.h"
>+#include "vm_helper.h"
>+#include "dcn20/dcn20_vmid.h"
>+
>+#define SOC_BOUNDING_BOX_VALID false
>+#define DC_LOGGER_INIT(logger)
>+
>+
>+struct _vcs_dpi_ip_params_st dcn2_1_ip = {
>+	.gpuvm_enable = 0,
>+	.hostvm_enable = 0,
>+	.gpuvm_max_page_table_levels = 1,
>+	.hostvm_max_page_table_levels = 4,
>+	.hostvm_cached_page_table_levels = 2,
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	.num_dsc = 3,
>+#else
>+	.num_dsc = 0,
>+#endif
>+	.rob_buffer_size_kbytes = 168,
>+	.det_buffer_size_kbytes = 164,
>+	.dpte_buffer_size_in_pte_reqs_luma = 44,
>+	.dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
>+	.dpp_output_buffer_pixels = 2560,
>+	.opp_output_buffer_lines = 1,
>+	.pixel_chunk_size_kbytes = 8,
>+	.pte_enable = 1,
>+	.max_page_table_levels = 4,
>+	.pte_chunk_size_kbytes = 2,
>+	.meta_chunk_size_kbytes = 2,
>+	.writeback_chunk_size_kbytes = 2,
>+	.line_buffer_size_bits = 789504,
>+	.is_line_buffer_bpp_fixed = 0,
>+	.line_buffer_fixed_bpp = 0,
>+	.dcc_supported = true,
>+	.max_line_buffer_lines = 12,
>+	.writeback_luma_buffer_size_kbytes = 12,
>+	.writeback_chroma_buffer_size_kbytes = 8,
>+	.writeback_chroma_line_buffer_width_pixels = 4,
>+	.writeback_max_hscl_ratio = 1,
>+	.writeback_max_vscl_ratio = 1,
>+	.writeback_min_hscl_ratio = 1,
>+	.writeback_min_vscl_ratio = 1,
>+	.writeback_max_hscl_taps = 12,
>+	.writeback_max_vscl_taps = 12,
>+	.writeback_line_buffer_luma_buffer_size = 0,
>+	.writeback_line_buffer_chroma_buffer_size = 14643,
>+	.cursor_buffer_size = 8,
>+	.cursor_chunk_size = 2,
>+	.max_num_otg = 4,
>+	.max_num_dpp = 4,
>+	.max_num_wb = 1,
>+	.max_dchub_pscl_bw_pix_per_clk = 4,
>+	.max_pscl_lb_bw_pix_per_clk = 2,
>+	.max_lb_vscl_bw_pix_per_clk = 4,
>+	.max_vscl_hscl_bw_pix_per_clk = 4,
>+	.max_hscl_ratio = 4,
>+	.max_vscl_ratio = 4,
>+	.hscl_mults = 4,
>+	.vscl_mults = 4,
>+	.max_hscl_taps = 8,
>+	.max_vscl_taps = 8,
>+	.dispclk_ramp_margin_percent = 1,
>+	.underscan_factor = 1.10,
>+	.min_vblank_lines = 32, //
>+	.dppclk_delay_subtotal = 77, //
>+	.dppclk_delay_scl_lb_only = 16,
>+	.dppclk_delay_scl = 50,
>+	.dppclk_delay_cnvc_formatter = 8,
>+	.dppclk_delay_cnvc_cursor = 6,
>+	.dispclk_delay_subtotal = 87, //
>+	.dcfclk_cstate_latency = 10, // SRExitTime
>+	.max_inter_dcn_tile_repeaters = 8,
>+
>+	.xfc_supported = false,
>+	.xfc_fill_bw_overhead_percent = 10.0,
>+	.xfc_fill_constant_bytes = 0,
>+	.ptoi_supported = 0
>+};
>+
>+struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
>+	.clock_limits = {
>+			{
>+				.state = 0,
>+				.dcfclk_mhz = 304.0,
>+				.fabricclk_mhz = 600.0,
>+				.dispclk_mhz = 618.0,
>+				.dppclk_mhz = 440.0,
>+				.phyclk_mhz = 600.0,
>+				.socclk_mhz = 278.0,
>+				.dscclk_mhz = 205.67,
>+				.dram_speed_mts = 1600.0,
>+			},
>+			{
>+				.state = 1,
>+				.dcfclk_mhz = 304.0,
>+				.fabricclk_mhz = 600.0,
>+				.dispclk_mhz = 618.0,
>+				.dppclk_mhz = 618.0,
>+				.phyclk_mhz = 600.0,
>+				.socclk_mhz = 278.0,
>+				.dscclk_mhz = 205.67,
>+				.dram_speed_mts = 1600.0,
>+			},
>+			{
>+				.state = 2,
>+				.dcfclk_mhz = 608.0,
>+				.fabricclk_mhz = 1066.0,
>+				.dispclk_mhz = 888.0,
>+				.dppclk_mhz = 888.0,
>+				.phyclk_mhz = 810.0,
>+				.socclk_mhz = 278.0,
>+				.dscclk_mhz = 287.67,
>+				.dram_speed_mts = 2133.0,
>+			},
>+			{
>+				.state = 3,
>+				.dcfclk_mhz = 676.0,
>+				.fabricclk_mhz = 1600.0,
>+				.dispclk_mhz = 1015.0,
>+				.dppclk_mhz = 1015.0,
>+				.phyclk_mhz = 810.0,
>+				.socclk_mhz = 715.0,
>+				.dscclk_mhz = 318.334,
>+				.dram_speed_mts = 4266.0,
>+			},
>+			{
>+				.state = 4,
>+				.dcfclk_mhz = 810.0,
>+				.fabricclk_mhz = 1600.0,
>+				.dispclk_mhz = 1015.0,
>+				.dppclk_mhz = 1015.0,
>+				.phyclk_mhz = 810.0,
>+				.socclk_mhz = 953.0,
>+				.dscclk_mhz = 318.334,
>+				.dram_speed_mts = 4266.0,
>+			},
>+			/*Extra state, no dispclk ramping*/
>+			{
>+				.state = 5,
>+				.dcfclk_mhz = 810.0,
>+				.fabricclk_mhz = 1600.0,
>+				.dispclk_mhz = 1015.0,
>+				.dppclk_mhz = 1015.0,
>+				.phyclk_mhz = 810.0,
>+				.socclk_mhz = 953.0,
>+				.dscclk_mhz = 318.334,
>+				.dram_speed_mts = 4266.0,
>+			},
>+
>+		},
>+
>+	.sr_exit_time_us = 9.0,
>+	.sr_enter_plus_exit_time_us = 11.0,
>+	.urgent_latency_us = 4.0,
>+	.urgent_latency_pixel_data_only_us = 4.0,
>+	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
>+	.urgent_latency_vm_data_only_us = 4.0,
>+	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
>+	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
>+	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
>+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
>+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
>+	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
>+	.max_avg_sdp_bw_use_normal_percent = 60.0,
>+	.max_avg_dram_bw_use_normal_percent = 100.0,
>+	.writeback_latency_us = 12.0,
>+	.max_request_size_bytes = 256,
>+	.dram_channel_width_bytes = 4,
>+	.fabric_datapath_to_dcn_data_return_bytes = 32,
>+	.dcn_downspread_percent = 0.5,
>+	.downspread_percent = 0.5,
>+	.dram_page_open_time_ns = 50.0,
>+	.dram_rw_turnaround_time_ns = 17.5,
>+	.dram_return_buffer_per_channel_bytes = 8192,
>+	.round_trip_ping_latency_dcfclk_cycles = 128,
>+	.urgent_out_of_order_return_per_channel_bytes = 4096,
>+	.channel_interleave_bytes = 256,
>+	.num_banks = 8,
>+	.num_chans = 4,
>+	.vmm_page_size_bytes = 4096,
>+	.dram_clock_change_latency_us = 23.84,
>+	.return_bus_width_bytes = 64,
>+	.dispclk_dppclk_vco_speed_mhz = 3550,
>+	.xfc_bus_transport_time_us = 4,
>+	.xfc_xbuf_latency_tolerance_us = 4,
>+	.use_urgent_burst_bw = 1,
>+	.num_states = 5
>+};
>+
>+#ifndef MAX
>+#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
>+#endif
>+#ifndef MIN
>+#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
>+#endif
>+
>+/* begin *********************
>+ * macros to expend register list macro defined in HW object header file */
>+
>+/* DCN */
>+/* TODO awful hack. fixup dcn20_dwb.h */
>+#undef BASE_INNER
>+#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
>+
>+#define BASE(seg) BASE_INNER(seg)
>+
>+#define SR(reg_name)\
>+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
>+					mm ## reg_name
>+
>+#define SRI(reg_name, block, id)\
>+	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
>+					mm ## block ## id ## _ ## reg_name
>+
>+#define SRIR(var_name, reg_name, block, id)\
>+	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
>+					mm ## block ## id ## _ ## reg_name
>+
>+#define SRII(reg_name, block, id)\
>+	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
>+					mm ## block ## id ## _ ## reg_name
>+
>+#define DCCG_SRII(reg_name, block, id)\
>+	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
>+					mm ## block ## id ## _ ## reg_name
>+
>+/* NBIO */
>+#define NBIO_BASE_INNER(seg) \
>+	NBIF0_BASE__INST0_SEG ## seg
>+
>+#define NBIO_BASE(seg) \
>+	NBIO_BASE_INNER(seg)
>+
>+#define NBIO_SR(reg_name)\
>+		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
>+					mm ## reg_name
>+
>+/* MMHUB */
>+#define MMHUB_BASE_INNER(seg) \
>+	MMHUB_BASE__INST0_SEG ## seg
>+
>+#define MMHUB_BASE(seg) \
>+	MMHUB_BASE_INNER(seg)
>+
>+#define MMHUB_SR(reg_name)\
>+		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
>+					mmMM ## reg_name
>+
>+#define clk_src_regs(index, pllid)\
>+[index] = {\
>+	CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
>+}
>+
>+static const struct dce110_clk_src_regs clk_src_regs[] = {
>+	clk_src_regs(0, A),
>+	clk_src_regs(1, B),
>+	clk_src_regs(2, C),
>+	clk_src_regs(3, D),
>+	clk_src_regs(4, E),
>+};
>+
>+static const struct dce110_clk_src_shift cs_shift = {
>+		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
>+};
>+
>+static const struct dce110_clk_src_mask cs_mask = {
>+		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
>+};
>+
>+static const struct bios_registers bios_regs = {
>+		NBIO_SR(BIOS_SCRATCH_3),
>+		NBIO_SR(BIOS_SCRATCH_6)
>+};
>+
>+#ifdef CONFIG_DRM_AMD_DC_DMUB
>+static const struct dcn21_dmcub_registers dmcub_regs = {
>+		DMCUB_REG_LIST_DCN()
>+};
>+
>+static const struct dcn21_dmcub_shift dmcub_shift = {
>+		DMCUB_COMMON_MASK_SH_LIST_BASE(__SHIFT)
>+};
>+
>+static const struct dcn21_dmcub_mask dmcub_mask = {
>+		DMCUB_COMMON_MASK_SH_LIST_BASE(_MASK)
>+};
>+#endif
>+
>+#define audio_regs(id)\
>+[id] = {\
>+		AUD_COMMON_REG_LIST(id)\
>+}
>+
>+static const struct dce_audio_registers audio_regs[] = {
>+	audio_regs(0),
>+	audio_regs(1),
>+	audio_regs(2),
>+	audio_regs(3),
>+	audio_regs(4),
>+	audio_regs(5),
>+};
>+
>+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
>+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
>+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
>+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
>+
>+static const struct dce_audio_shift audio_shift = {
>+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
>+};
>+
>+static const struct dce_audio_mask audio_mask = {
>+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
>+};
>+
>+static const struct dccg_registers dccg_regs = {
>+		DCCG_COMMON_REG_LIST_DCN_BASE()
>+};
>+
>+static const struct dccg_shift dccg_shift = {
>+		DCCG_MASK_SH_LIST_DCN2(__SHIFT)
>+};
>+
>+static const struct dccg_mask dccg_mask = {
>+		DCCG_MASK_SH_LIST_DCN2(_MASK)
>+};
>+
>+#define opp_regs(id)\
>+[id] = {\
>+	OPP_REG_LIST_DCN20(id),\
>+}
>+
>+static const struct dcn20_opp_registers opp_regs[] = {
>+	opp_regs(0),
>+	opp_regs(1),
>+	opp_regs(2),
>+	opp_regs(3),
>+	opp_regs(4),
>+	opp_regs(5),
>+};
>+
>+static const struct dcn20_opp_shift opp_shift = {
>+		OPP_MASK_SH_LIST_DCN20(__SHIFT)
>+};
>+
>+static const struct dcn20_opp_mask opp_mask = {
>+		OPP_MASK_SH_LIST_DCN20(_MASK)
>+};
>+
>+#define tg_regs(id)\
>+[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
>+
>+static const struct dcn_optc_registers tg_regs[] = {
>+	tg_regs(0),
>+	tg_regs(1),
>+	tg_regs(2),
>+	tg_regs(3)
>+};
>+
>+static const struct dcn_optc_shift tg_shift = {
>+	TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
>+};
>+
>+static const struct dcn_optc_mask tg_mask = {
>+	TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
>+};
>+
>+static const struct dcn20_mpc_registers mpc_regs = {
>+		MPC_REG_LIST_DCN2_0(0),
>+		MPC_REG_LIST_DCN2_0(1),
>+		MPC_REG_LIST_DCN2_0(2),
>+		MPC_REG_LIST_DCN2_0(3),
>+		MPC_REG_LIST_DCN2_0(4),
>+		MPC_REG_LIST_DCN2_0(5),
>+		MPC_OUT_MUX_REG_LIST_DCN2_0(0),
>+		MPC_OUT_MUX_REG_LIST_DCN2_0(1),
>+		MPC_OUT_MUX_REG_LIST_DCN2_0(2),
>+		MPC_OUT_MUX_REG_LIST_DCN2_0(3)
>+};
>+
>+static const struct dcn20_mpc_shift mpc_shift = {
>+	MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
>+};
>+
>+static const struct dcn20_mpc_mask mpc_mask = {
>+	MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
>+};
>+
>+#define hubp_regs(id)\
>+[id] = {\
>+	HUBP_REG_LIST_DCN21(id)\
>+}
>+
>+static const struct dcn_hubp2_registers hubp_regs[] = {
>+		hubp_regs(0),
>+		hubp_regs(1),
>+		hubp_regs(2),
>+		hubp_regs(3)
>+};
>+
>+static const struct dcn_hubp2_shift hubp_shift = {
>+		HUBP_MASK_SH_LIST_DCN21(__SHIFT)
>+};
>+
>+static const struct dcn_hubp2_mask hubp_mask = {
>+		HUBP_MASK_SH_LIST_DCN21(_MASK)
>+};
>+
>+static const struct dcn_hubbub_registers hubbub_reg = {
>+		HUBBUB_REG_LIST_DCN21()
>+};
>+
>+static const struct dcn_hubbub_shift hubbub_shift = {
>+		HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
>+};
>+
>+static const struct dcn_hubbub_mask hubbub_mask = {
>+		HUBBUB_MASK_SH_LIST_DCN21(_MASK)
>+};
>+
>+
>+#define vmid_regs(id)\
>+[id] = {\
>+		DCN20_VMID_REG_LIST(id)\
>+}
>+
>+static const struct dcn_vmid_registers vmid_regs[] = {
>+	vmid_regs(0),
>+	vmid_regs(1),
>+	vmid_regs(2),
>+	vmid_regs(3),
>+	vmid_regs(4),
>+	vmid_regs(5),
>+	vmid_regs(6),
>+	vmid_regs(7),
>+	vmid_regs(8),
>+	vmid_regs(9),
>+	vmid_regs(10),
>+	vmid_regs(11),
>+	vmid_regs(12),
>+	vmid_regs(13),
>+	vmid_regs(14),
>+	vmid_regs(15)
>+};
>+
>+static const struct dcn20_vmid_shift vmid_shifts = {
>+		DCN20_VMID_MASK_SH_LIST(__SHIFT)
>+};
>+
>+static const struct dcn20_vmid_mask vmid_masks = {
>+		DCN20_VMID_MASK_SH_LIST(_MASK)
>+};
>+
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+#define dsc_regsDCN20(id)\
>+[id] = {\
>+	DSC_REG_LIST_DCN20(id)\
>+}
>+
>+static const struct dcn20_dsc_registers dsc_regs[] = {
>+	dsc_regsDCN20(0),
>+	dsc_regsDCN20(1),
>+	dsc_regsDCN20(2),
>+	dsc_regsDCN20(3),
>+	dsc_regsDCN20(4),
>+	dsc_regsDCN20(5)
>+};
>+
>+static const struct dcn20_dsc_shift dsc_shift = {
>+	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
>+};
>+
>+static const struct dcn20_dsc_mask dsc_mask = {
>+	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
>+};
>+#endif
>+
>+#define ipp_regs(id)\
>+[id] = {\
>+	IPP_REG_LIST_DCN20(id),\
>+}
>+
>+static const struct dcn10_ipp_registers ipp_regs[] = {
>+	ipp_regs(0),
>+	ipp_regs(1),
>+	ipp_regs(2),
>+	ipp_regs(3),
>+};
>+
>+static const struct dcn10_ipp_shift ipp_shift = {
>+		IPP_MASK_SH_LIST_DCN20(__SHIFT)
>+};
>+
>+static const struct dcn10_ipp_mask ipp_mask = {
>+		IPP_MASK_SH_LIST_DCN20(_MASK),
>+};
>+
>+#define opp_regs(id)\
>+[id] = {\
>+	OPP_REG_LIST_DCN20(id),\
>+}
>+
>+
>+#define aux_engine_regs(id)\
>+[id] = {\
>+	AUX_COMMON_REG_LIST0(id), \
>+	.AUXN_IMPCAL = 0, \
>+	.AUXP_IMPCAL = 0, \
>+	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
>+}
>+
>+static const struct dce110_aux_registers aux_engine_regs[] = {
>+		aux_engine_regs(0),
>+		aux_engine_regs(1),
>+		aux_engine_regs(2),
>+		aux_engine_regs(3),
>+		aux_engine_regs(4),
>+};
>+
>+#define tf_regs(id)\
>+[id] = {\
>+	TF_REG_LIST_DCN20(id),\
>+}
>+
>+static const struct dcn2_dpp_registers tf_regs[] = {
>+	tf_regs(0),
>+	tf_regs(1),
>+	tf_regs(2),
>+	tf_regs(3),
>+};
>+
>+static const struct dcn2_dpp_shift tf_shift = {
>+		TF_REG_LIST_SH_MASK_DCN20(__SHIFT)
>+};
>+
>+static const struct dcn2_dpp_mask tf_mask = {
>+		TF_REG_LIST_SH_MASK_DCN20(_MASK)
>+};
>+
>+#define stream_enc_regs(id)\
>+[id] = {\
>+	SE_DCN2_REG_LIST(id)\
>+}
>+
>+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
>+	stream_enc_regs(0),
>+	stream_enc_regs(1),
>+	stream_enc_regs(2),
>+	stream_enc_regs(3),
>+	stream_enc_regs(4),
>+};
>+
>+static const struct dcn10_stream_encoder_shift se_shift = {
>+		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
>+};
>+
>+static const struct dcn10_stream_encoder_mask se_mask = {
>+		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
>+};
>+
>+static struct input_pixel_processor *dcn21_ipp_create(
>+	struct dc_context *ctx, uint32_t inst)
>+{
>+	struct dcn10_ipp *ipp =
>+		kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
>+
>+	if (!ipp) {
>+		BREAK_TO_DEBUGGER();
>+		return NULL;
>+	}
>+
>+	dcn20_ipp_construct(ipp, ctx, inst,
>+			&ipp_regs[inst], &ipp_shift, &ipp_mask);
>+	return &ipp->base;
>+}
>+
>+static struct dpp *dcn21_dpp_create(
>+	struct dc_context *ctx,
>+	uint32_t inst)
>+{
>+	struct dcn20_dpp *dpp =
>+		kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
>+
>+	if (!dpp)
>+		return NULL;
>+
>+	if (dpp2_construct(dpp, ctx, inst,
>+			&tf_regs[inst], &tf_shift, &tf_mask))
>+		return &dpp->base;
>+
>+	BREAK_TO_DEBUGGER();
>+	kfree(dpp);
>+	return NULL;
>+}
>+
>+static struct dce_aux *dcn21_aux_engine_create(
>+	struct dc_context *ctx,
>+	uint32_t inst)
>+{
>+	struct aux_engine_dce110 *aux_engine =
>+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
>+
>+	if (!aux_engine)
>+		return NULL;
>+
>+	dce110_aux_engine_construct(aux_engine, ctx, inst,
>+				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
>+				    &aux_engine_regs[inst]);
>+
>+	return &aux_engine->base;
>+}
>+
>+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
>+
>+static const struct dce_i2c_registers i2c_hw_regs[] = {
>+		i2c_inst_regs(1),
>+		i2c_inst_regs(2),
>+		i2c_inst_regs(3),
>+		i2c_inst_regs(4),
>+		i2c_inst_regs(5),
>+};
>+
>+static const struct dce_i2c_shift i2c_shifts = {
>+		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
>+};
>+
>+static const struct dce_i2c_mask i2c_masks = {
>+		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
>+};
>+
>+struct dce_i2c_hw *dcn21_i2c_hw_create(
>+	struct dc_context *ctx,
>+	uint32_t inst)
>+{
>+	struct dce_i2c_hw *dce_i2c_hw =
>+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
>+
>+	if (!dce_i2c_hw)
>+		return NULL;
>+
>+	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
>+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
>+
>+	return dce_i2c_hw;
>+}
>+
>+static const struct resource_caps res_cap_rn = {
>+		.num_timing_generator = 4,
>+		.num_opp = 4,
>+		.num_video_plane = 4,
>+		.num_audio = 6, // 6 audio endpoints.  4 audio streams
>+		.num_stream_encoder = 5,
>+		.num_pll = 5,  // maybe 3 because the last two used for USB-c
>+		.num_dwb = 1,
>+		.num_ddc = 5,
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+		.num_dsc = 3,
>+#endif
>+};
>+
>+#ifdef DIAGS_BUILD
>+static const struct resource_caps res_cap_rn_FPGA_4pipe = {
>+		.num_timing_generator = 4,
>+		.num_opp = 4,
>+		.num_video_plane = 4,
>+		.num_audio = 7,
>+		.num_stream_encoder = 4,
>+		.num_pll = 4,
>+		.num_dwb = 1,
>+		.num_ddc = 4,
>+		.num_dsc = 0,
>+};
>+
>+static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
>+		.num_timing_generator = 2,
>+		.num_opp = 2,
>+		.num_video_plane = 2,
>+		.num_audio = 7,
>+		.num_stream_encoder = 2,
>+		.num_pll = 4,
>+		.num_dwb = 1,
>+		.num_ddc = 4,
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+		.num_dsc = 2,
>+#endif
>+};
>+#endif
>+
>+static const struct dc_plane_cap plane_cap = {
>+	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
>+	.blends_with_above = true,
>+	.blends_with_below = true,
>+	.per_pixel_alpha = true,
>+
>+	.pixel_format_support = {
>+			.argb8888 = true,
>+			.nv12 = true,
>+			.fp16 = true
>+	},
>+
>+	.max_upscale_factor = {
>+			.argb8888 = 16000,
>+			.nv12 = 16000,
>+			.fp16 = 16000
>+	},
>+
>+	.max_downscale_factor = {
>+			.argb8888 = 250,
>+			.nv12 = 250,
>+			.fp16 = 250
>+	}
>+};
>+
>+static const struct dc_debug_options debug_defaults_drv = {
>+		.disable_dmcu = true,
>+		.force_abm_enable = false,
>+		.timing_trace = false,
>+		.clock_trace = true,
>+		.disable_pplib_clock_request = true,
>+		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
>+		.force_single_disp_pipe_split = true,
>+		.disable_dcc = DCC_ENABLE,
>+		.vsr_support = true,
>+		.performance_trace = false,
>+		.max_downscale_src_width = 5120,/*upto 5K*/
>+		.disable_pplib_wm_range = false,
>+		.scl_reset_length10 = true,
>+		.sanity_checks = true,
>+		.disable_48mhz_pwrdwn = true,
>+};
>+
>+static const struct dc_debug_options debug_defaults_diags = {
>+		.disable_dmcu = true,
>+		.force_abm_enable = false,
>+		.timing_trace = true,
>+		.clock_trace = true,
>+		.disable_dpp_power_gate = true,
>+		.disable_hubp_power_gate = true,
>+		.disable_clock_gate = true,
>+		.disable_pplib_clock_request = true,
>+		.disable_pplib_wm_range = true,
>+		.disable_stutter = true,
>+		.disable_48mhz_pwrdwn = true,
>+};
>+
>+enum dcn20_clk_src_array_id {
>+	DCN20_CLK_SRC_PLL0,
>+	DCN20_CLK_SRC_PLL1,
>+	DCN20_CLK_SRC_TOTAL_DCN21
>+};
>+
>+static void destruct(struct dcn21_resource_pool *pool)
>+{
>+	unsigned int i;
>+
>+	for (i = 0; i < pool->base.stream_enc_count; i++) {
>+		if (pool->base.stream_enc[i] != NULL) {
>+			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
>+			pool->base.stream_enc[i] = NULL;
>+		}
>+	}
>+
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
>+		if (pool->base.dscs[i] != NULL)
>+			dcn20_dsc_destroy(&pool->base.dscs[i]);
>+	}
>+#endif
>+
>+	if (pool->base.mpc != NULL) {
>+		kfree(TO_DCN20_MPC(pool->base.mpc));
>+		pool->base.mpc = NULL;
>+	}
>+	if (pool->base.hubbub != NULL) {
>+		kfree(pool->base.hubbub);
>+		pool->base.hubbub = NULL;
>+	}
>+	for (i = 0; i < pool->base.pipe_count; i++) {
>+		if (pool->base.dpps[i] != NULL)
>+			dcn20_dpp_destroy(&pool->base.dpps[i]);
>+
>+		if (pool->base.ipps[i] != NULL)
>+			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
>+
>+		if (pool->base.hubps[i] != NULL) {
>+			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
>+			pool->base.hubps[i] = NULL;
>+		}
>+
>+		if (pool->base.irqs != NULL) {
>+			dal_irq_service_destroy(&pool->base.irqs);
>+		}
>+	}
>+
>+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
>+		if (pool->base.engines[i] != NULL)
>+			dce110_engine_destroy(&pool->base.engines[i]);
>+		if (pool->base.hw_i2cs[i] != NULL) {
>+			kfree(pool->base.hw_i2cs[i]);
>+			pool->base.hw_i2cs[i] = NULL;
>+		}
>+		if (pool->base.sw_i2cs[i] != NULL) {
>+			kfree(pool->base.sw_i2cs[i]);
>+			pool->base.sw_i2cs[i] = NULL;
>+		}
>+	}
>+
>+	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
>+		if (pool->base.opps[i] != NULL)
>+			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
>+	}
>+
>+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
>+		if (pool->base.timing_generators[i] != NULL)	{
>+			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
>+			pool->base.timing_generators[i] = NULL;
>+		}
>+	}
>+
>+	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
>+		if (pool->base.dwbc[i] != NULL) {
>+			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
>+			pool->base.dwbc[i] = NULL;
>+		}
>+		if (pool->base.mcif_wb[i] != NULL) {
>+			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
>+			pool->base.mcif_wb[i] = NULL;
>+		}
>+	}
>+
>+	for (i = 0; i < pool->base.audio_count; i++) {
>+		if (pool->base.audios[i])
>+			dce_aud_destroy(&pool->base.audios[i]);
>+	}
>+
>+	for (i = 0; i < pool->base.clk_src_count; i++) {
>+		if (pool->base.clock_sources[i] != NULL) {
>+			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
>+			pool->base.clock_sources[i] = NULL;
>+		}
>+	}
>+
>+	if (pool->base.dp_clock_source != NULL) {
>+		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
>+		pool->base.dp_clock_source = NULL;
>+	}
>+
>+
>+	if (pool->base.abm != NULL)
>+		dce_abm_destroy(&pool->base.abm);
>+
>+	if (pool->base.dmcu != NULL)
>+		dce_dmcu_destroy(&pool->base.dmcu);
>+
>+#ifdef CONFIG_DRM_AMD_DC_DMUB
>+	if (pool->base.dmcub != NULL)
>+		dcn21_dmcub_destroy(&pool->base.dmcub);
>+#endif
>+
>+	if (pool->base.dccg != NULL)
>+		dcn_dccg_destroy(&pool->base.dccg);
>+
>+	if (pool->base.pp_smu != NULL)
>+		dcn20_pp_smu_destroy(&pool->base.pp_smu);
>+}
>+
>+
>+static void calculate_wm_set_for_vlevel(
>+		int vlevel,
>+		struct wm_range_table_entry *table_entry,
>+		struct dcn_watermarks *wm_set,
>+		struct display_mode_lib *dml,
>+		display_e2e_pipe_params_st *pipes,
>+		int pipe_cnt)
>+{
>+	double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
>+
>+	ASSERT(vlevel < dml->soc.num_states);
>+	/* only pipe 0 is read for voltage and dcf/soc clocks */
>+	pipes[0].clks_cfg.voltage = vlevel;
>+	pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
>+	pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
>+
>+	dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
>+
>+	wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
>+	wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
>+	wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
>+	wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
>+	wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
>+	wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
>+#endif
>+	dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
>+
>+}
>+
>+void dcn21_calculate_wm(
>+		struct dc *dc, struct dc_state *context,
>+		display_e2e_pipe_params_st *pipes,
>+		int *out_pipe_cnt,
>+		int *pipe_split_from,
>+		int vlevel_req)
>+{
>+	int pipe_cnt, i, pipe_idx;
>+	int vlevel, vlevel_max;
>+	struct wm_range_table_entry *table_entry;
>+	struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
>+
>+	ASSERT(bw_params);
>+
>+	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
>+			if (!context->res_ctx.pipe_ctx[i].stream)
>+				continue;
>+
>+			pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
>+			pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
>+
>+			if (pipe_split_from[i] < 0) {
>+				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
>+						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
>+				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
>+					pipes[pipe_cnt].pipe.dest.odm_combine =
>+							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
>+				else
>+					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
>+				pipe_idx++;
>+			} else {
>+				pipes[pipe_cnt].clks_cfg.dppclk_mhz =
>+						context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
>+				if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
>+					pipes[pipe_cnt].pipe.dest.odm_combine =
>+							context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
>+				else
>+					pipes[pipe_cnt].pipe.dest.odm_combine = 0;
>+			}
>+			pipe_cnt++;
>+	}
>+
>+	if (pipe_cnt != pipe_idx) {
>+		if (dc->res_pool->funcs->populate_dml_pipes)
>+			pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
>+				&context->res_ctx, pipes);
>+		else
>+			pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
>+				&context->res_ctx, pipes);
>+	}
>+
>+	*out_pipe_cnt = pipe_cnt;
>+
>+	vlevel_max = bw_params->clk_table.num_entries - 1;
>+
>+
>+	/* WM Set D */
>+	table_entry = &bw_params->wm_table.entries[WM_D];
>+	if (table_entry->wm_type == WM_TYPE_RETRAINING)
>+		vlevel = 0;
>+	else
>+		vlevel = vlevel_max;
>+	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
>+						&context->bw_ctx.dml, pipes, pipe_cnt);
>+	/* WM Set C */
>+	table_entry = &bw_params->wm_table.entries[WM_C];
>+	vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
>+	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
>+						&context->bw_ctx.dml, pipes, pipe_cnt);
>+	/* WM Set B */
>+	table_entry = &bw_params->wm_table.entries[WM_B];
>+	vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
>+	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
>+						&context->bw_ctx.dml, pipes, pipe_cnt);
>+
>+	/* WM Set A */
>+	table_entry = &bw_params->wm_table.entries[WM_A];
>+	vlevel = MIN(vlevel_req, vlevel_max);
>+	calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
>+						&context->bw_ctx.dml, pipes, pipe_cnt);
>+}
>+
>+
>+bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
>+		bool fast_validate)
>+{
>+	bool out = false;
>+
>+	BW_VAL_TRACE_SETUP();
>+
>+	int vlevel = 0;
>+	int pipe_split_from[MAX_PIPES];
>+	int pipe_cnt = 0;
>+	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
>+	DC_LOGGER_INIT(dc->ctx->logger);
>+
>+	BW_VAL_TRACE_COUNT();
>+
>+	out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
>+
>+	if (pipe_cnt == 0)
>+		goto validate_out;
>+
>+	if (!out)
>+		goto validate_fail;
>+
>+	BW_VAL_TRACE_END_VOLTAGE_LEVEL();
>+
>+	if (fast_validate) {
>+		BW_VAL_TRACE_SKIP(fast);
>+		goto validate_out;
>+	}
>+
>+	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
>+	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
>+
>+	BW_VAL_TRACE_END_WATERMARKS();
>+
>+	goto validate_out;
>+
>+validate_fail:
>+	DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
>+		dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
>+
>+	BW_VAL_TRACE_SKIP(fail);
>+	out = false;
>+
>+validate_out:
>+	kfree(pipes);
>+
>+	BW_VAL_TRACE_FINISH();
>+
>+	return out;
>+}
>+static void dcn21_destroy_resource_pool(struct resource_pool **pool)
>+{
>+	struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
>+
>+	destruct(dcn21_pool);
>+	kfree(dcn21_pool);
>+	*pool = NULL;
>+}
>+
>+static struct clock_source *dcn21_clock_source_create(
>+		struct dc_context *ctx,
>+		struct dc_bios *bios,
>+		enum clock_source_id id,
>+		const struct dce110_clk_src_regs *regs,
>+		bool dp_clk_src)
>+{
>+	struct dce110_clk_src *clk_src =
>+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
>+
>+	if (!clk_src)
>+		return NULL;
>+
>+	if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
>+			regs, &cs_shift, &cs_mask)) {
>+		clk_src->base.dp_clk_src = dp_clk_src;
>+		return &clk_src->base;
>+	}
>+
>+	BREAK_TO_DEBUGGER();
>+	return NULL;
>+}
>+
>+static struct hubp *dcn21_hubp_create(
>+	struct dc_context *ctx,
>+	uint32_t inst)
>+{
>+	struct dcn21_hubp *hubp21 =
>+		kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
>+
>+	if (!hubp21)
>+		return NULL;
>+
>+	if (hubp21_construct(hubp21, ctx, inst,
>+			&hubp_regs[inst], &hubp_shift, &hubp_mask))
>+		return &hubp21->base;
>+
>+	BREAK_TO_DEBUGGER();
>+	kfree(hubp21);
>+	return NULL;
>+}
>+
>+static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
>+{
>+	int i;
>+
>+	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
>+					  GFP_KERNEL);
>+
>+	if (!hubbub)
>+		return NULL;
>+
>+	hubbub21_construct(hubbub, ctx,
>+			&hubbub_reg,
>+			&hubbub_shift,
>+			&hubbub_mask);
>+
>+	for (i = 0; i < res_cap_rn.num_vmid; i++) {
>+		struct dcn20_vmid *vmid = &hubbub->vmid[i];
>+
>+		vmid->ctx = ctx;
>+
>+		vmid->regs = &vmid_regs[i];
>+		vmid->shifts = &vmid_shifts;
>+		vmid->masks = &vmid_masks;
>+	}
>+
>+	return &hubbub->base;
>+}
>+
>+struct output_pixel_processor *dcn21_opp_create(
>+	struct dc_context *ctx, uint32_t inst)
>+{
>+	struct dcn20_opp *opp =
>+		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
>+
>+	if (!opp) {
>+		BREAK_TO_DEBUGGER();
>+		return NULL;
>+	}
>+
>+	dcn20_opp_construct(opp, ctx, inst,
>+			&opp_regs[inst], &opp_shift, &opp_mask);
>+	return &opp->base;
>+}
>+
>+struct timing_generator *dcn21_timing_generator_create(
>+		struct dc_context *ctx,
>+		uint32_t instance)
>+{
>+	struct optc *tgn10 =
>+		kzalloc(sizeof(struct optc), GFP_KERNEL);
>+
>+	if (!tgn10)
>+		return NULL;
>+
>+	tgn10->base.inst = instance;
>+	tgn10->base.ctx = ctx;
>+
>+	tgn10->tg_regs = &tg_regs[instance];
>+	tgn10->tg_shift = &tg_shift;
>+	tgn10->tg_mask = &tg_mask;
>+
>+	dcn20_timing_generator_init(tgn10);
>+
>+	return &tgn10->base;
>+}
>+
>+struct mpc *dcn21_mpc_create(struct dc_context *ctx)
>+{
>+	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
>+					  GFP_KERNEL);
>+
>+	if (!mpc20)
>+		return NULL;
>+
>+	dcn20_mpc_construct(mpc20, ctx,
>+			&mpc_regs,
>+			&mpc_shift,
>+			&mpc_mask,
>+			6);
>+
>+	return &mpc20->base;
>+}
>+
>+static void read_dce_straps(
>+	struct dc_context *ctx,
>+	struct resource_straps *straps)
>+{
>+	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
>+		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
>+
>+}
>+
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+
>+struct display_stream_compressor *dcn21_dsc_create(
>+	struct dc_context *ctx, uint32_t inst)
>+{
>+	struct dcn20_dsc *dsc =
>+		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
>+
>+	if (!dsc) {
>+		BREAK_TO_DEBUGGER();
>+		return NULL;
>+	}
>+
>+	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
>+	return &dsc->base;
>+}
>+#endif
>+
>+static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
>+{
>+	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
>+	struct clk_limit_table *clk_table = &bw_params->clk_table;
>+	int i;
>+
>+	dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
>+	dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
>+	dcn2_1_soc.num_chans = bw_params->num_channels;
>+	dcn2_1_soc.num_states = 0;
>+
>+	for (i = 0; i < clk_table->num_entries; i++) {
>+
>+		dcn2_1_soc.clock_limits[i].state = i;
>+		dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
>+		dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
>+		dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
>+		/* This is probably wrong, TODO: find correct calculation */
>+		dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000;
>+		dcn2_1_soc.num_states++;
>+	}
>+}
>+
>+/* Temporary Place holder until we can get them from fuse */
>+static struct dpm_clocks dummy_clocks = {
>+		.DcfClocks = {
>+				{.Freq = 400, .Vol = 1},
>+				{.Freq = 483, .Vol = 1},
>+				{.Freq = 602, .Vol = 1},
>+				{.Freq = 738, .Vol = 1} },
>+		.SocClocks = {
>+				{.Freq = 300, .Vol = 1},
>+				{.Freq = 400, .Vol = 1},
>+				{.Freq = 400, .Vol = 1},
>+				{.Freq = 400, .Vol = 1} },
>+		.FClocks = {
>+				{.Freq = 400, .Vol = 1},
>+				{.Freq = 800, .Vol = 1},
>+				{.Freq = 1067, .Vol = 1},
>+				{.Freq = 1600, .Vol = 1} },
>+		.MemClocks = {
>+				{.Freq = 800, .Vol = 1},
>+				{.Freq = 1600, .Vol = 1},
>+				{.Freq = 1067, .Vol = 1},
>+				{.Freq = 1600, .Vol = 1} },
>+
>+};
>+
>+enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
>+		struct pp_smu_wm_range_sets *ranges)
>+{
>+	return PP_SMU_RESULT_OK;
>+}
>+
>+enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
>+		struct dpm_clocks *clock_table)
>+{
>+	*clock_table = dummy_clocks;
>+	return PP_SMU_RESULT_OK;
>+}
>+
>+struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
>+{
>+	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
>+
>+	pp_smu->ctx.ver = PP_SMU_VER_RN;
>+
>+	pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
>+	pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
>+
>+	return pp_smu;
>+}
>+
>+void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
>+{
>+	if (pp_smu && *pp_smu) {
>+		kfree(*pp_smu);
>+		*pp_smu = NULL;
>+	}
>+}
>+
>+static struct audio *dcn21_create_audio(
>+		struct dc_context *ctx, unsigned int inst)
>+{
>+	return dce_audio_create(ctx, inst,
>+			&audio_regs[inst], &audio_shift, &audio_mask);
>+}
>+
>+static struct dc_cap_funcs cap_funcs = {
>+	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
>+};
>+
>+struct stream_encoder *dcn21_stream_encoder_create(
>+	enum engine_id eng_id,
>+	struct dc_context *ctx)
>+{
>+	struct dcn10_stream_encoder *enc1 =
>+		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
>+
>+	if (!enc1)
>+		return NULL;
>+
>+	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
>+					&stream_enc_regs[eng_id],
>+					&se_shift, &se_mask);
>+
>+	return &enc1->base;
>+}
>+
>+static const struct dce_hwseq_registers hwseq_reg = {
>+		HWSEQ_DCN21_REG_LIST()
>+};
>+
>+static const struct dce_hwseq_shift hwseq_shift = {
>+		HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
>+};
>+
>+static const struct dce_hwseq_mask hwseq_mask = {
>+		HWSEQ_DCN21_MASK_SH_LIST(_MASK)
>+};
>+
>+static struct dce_hwseq *dcn21_hwseq_create(
>+	struct dc_context *ctx)
>+{
>+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
>+
>+	if (hws) {
>+		hws->ctx = ctx;
>+		hws->regs = &hwseq_reg;
>+		hws->shifts = &hwseq_shift;
>+		hws->masks = &hwseq_mask;
>+	}
>+	return hws;
>+}
>+
>+static const struct resource_create_funcs res_create_funcs = {
>+	.read_dce_straps = read_dce_straps,
>+	.create_audio = dcn21_create_audio,
>+	.create_stream_encoder = dcn21_stream_encoder_create,
>+	.create_hwseq = dcn21_hwseq_create,
>+};
>+
>+static const struct resource_create_funcs res_create_maximus_funcs = {
>+	.read_dce_straps = NULL,
>+	.create_audio = NULL,
>+	.create_stream_encoder = NULL,
>+	.create_hwseq = dcn21_hwseq_create,
>+};
>+
>+static struct resource_funcs dcn21_res_pool_funcs = {
>+	.destroy = dcn21_destroy_resource_pool,
>+	.link_enc_create = dcn20_link_encoder_create,
>+	.validate_bandwidth = dcn21_validate_bandwidth,
>+	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
>+	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
>+	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
>+	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
>+	.get_default_swizzle_mode = dcn20_get_default_swizzle_mode,
>+	.set_mcif_arb_params = dcn20_set_mcif_arb_params,
>+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
>+	.update_bw_bounding_box = update_bw_bounding_box
>+};
>+
>+static bool construct(
>+	uint8_t num_virtual_links,
>+	struct dc *dc,
>+	struct dcn21_resource_pool *pool)
>+{
>+	int i;
>+	struct dc_context *ctx = dc->ctx;
>+	struct irq_service_init_data init_data;
>+
>+	ctx->dc_bios->regs = &bios_regs;
>+
>+	pool->base.res_cap = &res_cap_rn;
>+#ifdef DIAGS_BUILD
>+	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
>+		//pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
>+		pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
>+#endif
>+
>+	pool->base.funcs = &dcn21_res_pool_funcs;
>+
>+	/*************************************************
>+	 *  Resource + asic cap harcoding                *
>+	 *************************************************/
>+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
>+
>+	pool->base.pipe_count = 4;
>+	dc->caps.max_downscale_ratio = 200;
>+	dc->caps.i2c_speed_in_khz = 100;
>+	dc->caps.max_cursor_size = 256;
>+	dc->caps.dmdata_alloc_size = 2048;
>+	dc->caps.hw_3d_lut = true;
>+
>+	dc->caps.max_slave_planes = 1;
>+	dc->caps.post_blend_color_processing = true;
>+	dc->caps.force_dp_tps4_for_cp2520 = true;
>+
>+	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
>+		dc->debug = debug_defaults_drv;
>+	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
>+		pool->base.pipe_count = 4;
>+		dc->debug = debug_defaults_diags;
>+	} else
>+		dc->debug = debug_defaults_diags;
>+
>+	// Init the vm_helper
>+	if (dc->vm_helper)
>+		vm_helper_init(dc->vm_helper, 16);
>+
>+	/*************************************************
>+	 *  Create resources                             *
>+	 *************************************************/
>+
>+	pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
>+			dcn21_clock_source_create(ctx, ctx->dc_bios,
>+				CLOCK_SOURCE_COMBO_PHY_PLL0,
>+				&clk_src_regs[0], false);
>+	pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
>+			dcn21_clock_source_create(ctx, ctx->dc_bios,
>+				CLOCK_SOURCE_COMBO_PHY_PLL1,
>+				&clk_src_regs[1], false);
>+
>+	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
>+
>+	/* todo: not reuse phy_pll registers */
>+	pool->base.dp_clock_source =
>+			dcn21_clock_source_create(ctx, ctx->dc_bios,
>+				CLOCK_SOURCE_ID_DP_DTO,
>+				&clk_src_regs[0], true);
>+
>+	for (i = 0; i < pool->base.clk_src_count; i++) {
>+		if (pool->base.clock_sources[i] == NULL) {
>+			dm_error("DC: failed to create clock sources!\n");
>+			BREAK_TO_DEBUGGER();
>+			goto create_fail;
>+		}
>+	}
>+
>+	pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
>+	if (pool->base.dccg == NULL) {
>+		dm_error("DC: failed to create dccg!\n");
>+		BREAK_TO_DEBUGGER();
>+		goto create_fail;
>+	}
>+
>+#ifdef CONFIG_DRM_AMD_DC_DMUB
>+	pool->base.dmcub = dcn21_dmcub_create(ctx,
>+			&dmcub_regs,
>+			&dmcub_shift,
>+			&dmcub_mask);
>+	if (pool->base.dmcub == NULL) {
>+		dm_error("DC: failed to create dmcub!\n");
>+		BREAK_TO_DEBUGGER();
>+		goto create_fail;
>+	}
>+#endif
>+
>+	pool->base.pp_smu = dcn21_pp_smu_create(ctx);
>+
>+	dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
>+
>+	init_data.ctx = dc->ctx;
>+	pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
>+	if (!pool->base.irqs)
>+		goto create_fail;
>+
>+	/* mem input -> ipp -> dpp -> opp -> TG */
>+	for (i = 0; i < pool->base.pipe_count; i++) {
>+		pool->base.hubps[i] = dcn21_hubp_create(ctx, i);
>+		if (pool->base.hubps[i] == NULL) {
>+			BREAK_TO_DEBUGGER();
>+			dm_error(
>+				"DC: failed to create memory input!\n");
>+			goto create_fail;
>+		}
>+
>+		pool->base.ipps[i] = dcn21_ipp_create(ctx, i);
>+		if (pool->base.ipps[i] == NULL) {
>+			BREAK_TO_DEBUGGER();
>+			dm_error(
>+				"DC: failed to create input pixel processor!\n");
>+			goto create_fail;
>+		}
>+
>+		pool->base.dpps[i] = dcn21_dpp_create(ctx, i);
>+		if (pool->base.dpps[i] == NULL) {
>+			BREAK_TO_DEBUGGER();
>+			dm_error(
>+				"DC: failed to create dpps!\n");
>+			goto create_fail;
>+		}
>+	}
>+
>+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
>+		pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
>+		if (pool->base.engines[i] == NULL) {
>+			BREAK_TO_DEBUGGER();
>+			dm_error(
>+				"DC:failed to create aux engine!!\n");
>+			goto create_fail;
>+		}
>+		pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
>+		if (pool->base.hw_i2cs[i] == NULL) {
>+			BREAK_TO_DEBUGGER();
>+			dm_error(
>+				"DC:failed to create hw i2c!!\n");
>+			goto create_fail;
>+		}
>+		pool->base.sw_i2cs[i] = NULL;
>+	}
>+
>+	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
>+		pool->base.opps[i] = dcn21_opp_create(ctx, i);
>+		if (pool->base.opps[i] == NULL) {
>+			BREAK_TO_DEBUGGER();
>+			dm_error(
>+				"DC: failed to create output pixel processor!\n");
>+			goto create_fail;
>+		}
>+	}
>+
>+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
>+		pool->base.timing_generators[i] = dcn21_timing_generator_create(
>+				ctx, i);
>+		if (pool->base.timing_generators[i] == NULL) {
>+			BREAK_TO_DEBUGGER();
>+			dm_error("DC: failed to create tg!\n");
>+			goto create_fail;
>+		}
>+	}
>+
>+	pool->base.timing_generator_count = i;
>+
>+	pool->base.mpc = dcn21_mpc_create(ctx);
>+	if (pool->base.mpc == NULL) {
>+		BREAK_TO_DEBUGGER();
>+		dm_error("DC: failed to create mpc!\n");
>+		goto create_fail;
>+	}
>+
>+	pool->base.hubbub = dcn21_hubbub_create(ctx);
>+	if (pool->base.hubbub == NULL) {
>+		BREAK_TO_DEBUGGER();
>+		dm_error("DC: failed to create hubbub!\n");
>+		goto create_fail;
>+	}
>+
>+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
>+		pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
>+		if (pool->base.dscs[i] == NULL) {
>+			BREAK_TO_DEBUGGER();
>+			dm_error("DC: failed to create display stream compressor %d!\n", i);
>+			goto create_fail;
>+		}
>+	}
>+#endif
>+
>+	if (!dcn20_dwbc_create(ctx, &pool->base)) {
>+		BREAK_TO_DEBUGGER();
>+		dm_error("DC: failed to create dwbc!\n");
>+		goto create_fail;
>+	}
>+	if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
>+		BREAK_TO_DEBUGGER();
>+		dm_error("DC: failed to create mcif_wb!\n");
>+		goto create_fail;
>+	}
>+
>+	if (!resource_construct(num_virtual_links, dc, &pool->base,
>+			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
>+			&res_create_funcs : &res_create_maximus_funcs)))
>+			goto create_fail;
>+
>+	dcn20_hw_sequencer_construct(dc);
>+
>+	dc->caps.max_planes =  pool->base.pipe_count;
>+
>+	for (i = 0; i < dc->caps.max_planes; ++i)
>+		dc->caps.planes[i] = plane_cap;
>+
>+	dc->cap_funcs = cap_funcs;
>+
>+	return true;
>+
>+create_fail:
>+
>+	destruct(pool);
>+
>+	return false;
>+}
>+
>+struct resource_pool *dcn21_create_resource_pool(
>+		const struct dc_init_data *init_data,
>+		struct dc *dc)
>+{
>+	struct dcn21_resource_pool *pool =
>+		kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
>+
>+	if (!pool)
>+		return NULL;
>+
>+	if (construct(init_data->num_virtual_links, dc, pool))
>+		return &pool->base;
>+
>+	BREAK_TO_DEBUGGER();
>+	kfree(pool);
>+	return NULL;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.h	2019-08-31 15:01:11.867736169 -0500
>@@ -0,0 +1,45 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifndef _DCN21_RESOURCE_H_
>+#define _DCN21_RESOURCE_H_
>+
>+#include "core_types.h"
>+
>+#define TO_DCN21_RES_POOL(pool)\
>+	container_of(pool, struct dcn21_resource_pool, base)
>+
>+struct dc;
>+struct resource_pool;
>+struct _vcs_dpi_display_pipe_params_st;
>+
>+struct dcn21_resource_pool {
>+	struct resource_pool base;
>+};
>+struct resource_pool *dcn21_create_resource_pool(
>+		const struct dc_init_data *init_data,
>+		struct dc *dc);
>+
>+#endif /* _DCN21_RESOURCE_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dcn21/Makefile	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dcn21/Makefile	2019-08-31 15:01:11.866736169 -0500
>@@ -0,0 +1,10 @@
>+#
>+# Makefile for DCN21.
>+
>+DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o
>+
>+CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
>+
>+AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
>+
>+AMD_DISPLAY_FILES += $(AMD_DAL_DCN21)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dc_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dc_types.h	2019-08-31 15:01:11.859736168 -0500
>@@ -202,6 +202,7 @@
> 	unsigned int dppowerup_delay;
> 	unsigned int extra_t12_ms;
> 	unsigned int extra_delay_backlight_off;
>+	unsigned int extra_t7_ms;
> };
> 
> struct dc_edid_caps {
>@@ -725,6 +726,19 @@
> 	unsigned int phyClock;
> };
> 
>+
>+enum dc_clock_type {
>+	DC_CLOCK_TYPE_DISPCLK = 0,
>+	DC_CLOCK_TYPE_DPPCLK        = 1,
>+};
>+
>+struct dc_clock_config {
>+	uint32_t max_clock_khz;
>+	uint32_t min_clock_khz;
>+	uint32_t bw_requirequired_clock_khz;
>+	uint32_t current_clock_khz;/*current clock in use*/
>+};
>+
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> /* DSC DPCD capabilities */
> union dsc_slice_caps1 {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c	2019-08-31 15:01:11.867736169 -0500
>@@ -0,0 +1,5136 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#include "../display_mode_lib.h"
>+#include "display_mode_vba_20v2.h"
>+#include "../dml_inline_defs.h"
>+
>+/*
>+ * NOTE:
>+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
>+ *
>+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
>+ * ways. Unless there is something clearly wrong with it the code should
>+ * remain as-is as it provides us with a guarantee from HW that it is correct.
>+ */
>+
>+#define BPP_INVALID 0
>+#define BPP_BLENDED_PIPE 0xffffffff
>+
>+static double adjust_ReturnBW(
>+		struct display_mode_lib *mode_lib,
>+		double ReturnBW,
>+		bool DCCEnabledAnyPlane,
>+		double ReturnBandwidthToDCN);
>+static unsigned int dscceComputeDelay(
>+		unsigned int bpc,
>+		double bpp,
>+		unsigned int sliceWidth,
>+		unsigned int numSlices,
>+		enum output_format_class pixelFormat);
>+static unsigned int dscComputeDelay(enum output_format_class pixelFormat);
>+static bool CalculateDelayAfterScaler(
>+		struct display_mode_lib *mode_lib,
>+		double ReturnBW,
>+		double ReadBandwidthPlaneLuma,
>+		double ReadBandwidthPlaneChroma,
>+		double TotalDataReadBandwidth,
>+		double DisplayPipeLineDeliveryTimeLuma,
>+		double DisplayPipeLineDeliveryTimeChroma,
>+		double DPPCLK,
>+		double DISPCLK,
>+		double PixelClock,
>+		unsigned int DSCDelay,
>+		unsigned int DPPPerPlane,
>+		bool ScalerEnabled,
>+		unsigned int NumberOfCursors,
>+		double DPPCLKDelaySubtotal,
>+		double DPPCLKDelaySCL,
>+		double DPPCLKDelaySCLLBOnly,
>+		double DPPCLKDelayCNVCFormater,
>+		double DPPCLKDelayCNVCCursor,
>+		double DISPCLKDelaySubtotal,
>+		unsigned int ScalerRecoutWidth,
>+		enum output_format_class OutputFormat,
>+		unsigned int HTotal,
>+		unsigned int SwathWidthSingleDPPY,
>+		double BytePerPixelDETY,
>+		double BytePerPixelDETC,
>+		unsigned int SwathHeightY,
>+		unsigned int SwathHeightC,
>+		bool Interlace,
>+		bool ProgressiveToInterlaceUnitInOPP,
>+		double *DSTXAfterScaler,
>+		double *DSTYAfterScaler
>+		);
>+// Super monster function with some 45 argument
>+static bool CalculatePrefetchSchedule(
>+		struct display_mode_lib *mode_lib,
>+		double DPPCLK,
>+		double DISPCLK,
>+		double PixelClock,
>+		double DCFCLKDeepSleep,
>+		unsigned int DPPPerPlane,
>+		unsigned int NumberOfCursors,
>+		unsigned int VBlank,
>+		unsigned int HTotal,
>+		unsigned int MaxInterDCNTileRepeaters,
>+		unsigned int VStartup,
>+		unsigned int PageTableLevels,
>+		bool GPUVMEnable,
>+		bool DynamicMetadataEnable,
>+		unsigned int DynamicMetadataLinesBeforeActiveRequired,
>+		unsigned int DynamicMetadataTransmittedBytes,
>+		bool DCCEnable,
>+		double UrgentLatencyPixelDataOnly,
>+		double UrgentExtraLatency,
>+		double TCalc,
>+		unsigned int PDEAndMetaPTEBytesFrame,
>+		unsigned int MetaRowByte,
>+		unsigned int PixelPTEBytesPerRow,
>+		double PrefetchSourceLinesY,
>+		unsigned int SwathWidthY,
>+		double BytePerPixelDETY,
>+		double VInitPreFillY,
>+		unsigned int MaxNumSwathY,
>+		double PrefetchSourceLinesC,
>+		double BytePerPixelDETC,
>+		double VInitPreFillC,
>+		unsigned int MaxNumSwathC,
>+		unsigned int SwathHeightY,
>+		unsigned int SwathHeightC,
>+		double TWait,
>+		bool XFCEnabled,
>+		double XFCRemoteSurfaceFlipDelay,
>+		bool InterlaceEnable,
>+		bool ProgressiveToInterlaceUnitInOPP,
>+		double DSTXAfterScaler,
>+		double DSTYAfterScaler,
>+		double *DestinationLinesForPrefetch,
>+		double *PrefetchBandwidth,
>+		double *DestinationLinesToRequestVMInVBlank,
>+		double *DestinationLinesToRequestRowInVBlank,
>+		double *VRatioPrefetchY,
>+		double *VRatioPrefetchC,
>+		double *RequiredPrefetchPixDataBW,
>+		double *Tno_bw,
>+		unsigned int *VUpdateOffsetPix,
>+		double *VUpdateWidthPix,
>+		double *VReadyOffsetPix);
>+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
>+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed);
>+static double CalculatePrefetchSourceLines(
>+		struct display_mode_lib *mode_lib,
>+		double VRatio,
>+		double vtaps,
>+		bool Interlace,
>+		bool ProgressiveToInterlaceUnitInOPP,
>+		unsigned int SwathHeight,
>+		unsigned int ViewportYStart,
>+		double *VInitPreFill,
>+		unsigned int *MaxNumSwath);
>+static unsigned int CalculateVMAndRowBytes(
>+		struct display_mode_lib *mode_lib,
>+		bool DCCEnable,
>+		unsigned int BlockHeight256Bytes,
>+		unsigned int BlockWidth256Bytes,
>+		enum source_format_class SourcePixelFormat,
>+		unsigned int SurfaceTiling,
>+		unsigned int BytePerPixel,
>+		enum scan_direction_class ScanDirection,
>+		unsigned int ViewportWidth,
>+		unsigned int ViewportHeight,
>+		unsigned int SwathWidthY,
>+		bool GPUVMEnable,
>+		unsigned int VMMPageSize,
>+		unsigned int PTEBufferSizeInRequestsLuma,
>+		unsigned int PDEProcessingBufIn64KBReqs,
>+		unsigned int Pitch,
>+		unsigned int DCCMetaPitch,
>+		unsigned int *MacroTileWidth,
>+		unsigned int *MetaRowByte,
>+		unsigned int *PixelPTEBytesPerRow,
>+		bool *PTEBufferSizeNotExceeded,
>+		unsigned int *dpte_row_height,
>+		unsigned int *meta_row_height);
>+static double CalculateTWait(
>+		unsigned int PrefetchMode,
>+		double DRAMClockChangeLatency,
>+		double UrgentLatencyPixelDataOnly,
>+		double SREnterPlusExitTime);
>+static double CalculateRemoteSurfaceFlipDelay(
>+		struct display_mode_lib *mode_lib,
>+		double VRatio,
>+		double SwathWidth,
>+		double Bpp,
>+		double LineTime,
>+		double XFCTSlvVupdateOffset,
>+		double XFCTSlvVupdateWidth,
>+		double XFCTSlvVreadyOffset,
>+		double XFCXBUFLatencyTolerance,
>+		double XFCFillBWOverhead,
>+		double XFCSlvChunkSize,
>+		double XFCBusTransportTime,
>+		double TCalc,
>+		double TWait,
>+		double *SrcActiveDrainRate,
>+		double *TInitXFill,
>+		double *TslvChk);
>+static void CalculateActiveRowBandwidth(
>+		bool GPUVMEnable,
>+		enum source_format_class SourcePixelFormat,
>+		double VRatio,
>+		bool DCCEnable,
>+		double LineTime,
>+		unsigned int MetaRowByteLuma,
>+		unsigned int MetaRowByteChroma,
>+		unsigned int meta_row_height_luma,
>+		unsigned int meta_row_height_chroma,
>+		unsigned int PixelPTEBytesPerRowLuma,
>+		unsigned int PixelPTEBytesPerRowChroma,
>+		unsigned int dpte_row_height_luma,
>+		unsigned int dpte_row_height_chroma,
>+		double *meta_row_bw,
>+		double *dpte_row_bw,
>+		double *qual_row_bw);
>+static void CalculateFlipSchedule(
>+		struct display_mode_lib *mode_lib,
>+		double UrgentExtraLatency,
>+		double UrgentLatencyPixelDataOnly,
>+		unsigned int GPUVMMaxPageTableLevels,
>+		bool GPUVMEnable,
>+		double BandwidthAvailableForImmediateFlip,
>+		unsigned int TotImmediateFlipBytes,
>+		enum source_format_class SourcePixelFormat,
>+		unsigned int ImmediateFlipBytes,
>+		double LineTime,
>+		double VRatio,
>+		double Tno_bw,
>+		double PDEAndMetaPTEBytesFrame,
>+		unsigned int MetaRowByte,
>+		unsigned int PixelPTEBytesPerRow,
>+		bool DCCEnable,
>+		unsigned int dpte_row_height,
>+		unsigned int meta_row_height,
>+		double qual_row_bw,
>+		double *DestinationLinesToRequestVMInImmediateFlip,
>+		double *DestinationLinesToRequestRowInImmediateFlip,
>+		double *final_flip_bw,
>+		bool *ImmediateFlipSupportedForPipe);
>+static double CalculateWriteBackDelay(
>+		enum source_format_class WritebackPixelFormat,
>+		double WritebackHRatio,
>+		double WritebackVRatio,
>+		unsigned int WritebackLumaHTaps,
>+		unsigned int WritebackLumaVTaps,
>+		unsigned int WritebackChromaHTaps,
>+		unsigned int WritebackChromaVTaps,
>+		unsigned int WritebackDestinationWidth);
>+
>+static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
>+static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
>+		struct display_mode_lib *mode_lib);
>+
>+void dml20v2_recalculate(struct display_mode_lib *mode_lib)
>+{
>+	ModeSupportAndSystemConfiguration(mode_lib);
>+	mode_lib->vba.FabricAndDRAMBandwidth = dml_min(
>+		mode_lib->vba.DRAMSpeed * mode_lib->vba.NumberOfChannels * mode_lib->vba.DRAMChannelWidth,
>+		mode_lib->vba.FabricClock * mode_lib->vba.FabricDatapathToDCNDataReturn) / 1000.0;
>+	PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
>+	dml20v2_DisplayPipeConfiguration(mode_lib);
>+	dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib);
>+}
>+
>+static double adjust_ReturnBW(
>+		struct display_mode_lib *mode_lib,
>+		double ReturnBW,
>+		bool DCCEnabledAnyPlane,
>+		double ReturnBandwidthToDCN)
>+{
>+	double CriticalCompression;
>+
>+	if (DCCEnabledAnyPlane
>+			&& ReturnBandwidthToDCN
>+					> mode_lib->vba.DCFCLK * mode_lib->vba.ReturnBusWidth / 4.0)
>+		ReturnBW =
>+				dml_min(
>+						ReturnBW,
>+						ReturnBandwidthToDCN * 4
>+								* (1.0
>+										- mode_lib->vba.UrgentLatencyPixelDataOnly
>+												/ ((mode_lib->vba.ROBBufferSizeInKByte
>+														- mode_lib->vba.PixelChunkSizeInKByte)
>+														* 1024
>+														/ ReturnBandwidthToDCN
>+														- mode_lib->vba.DCFCLK
>+																* mode_lib->vba.ReturnBusWidth
>+																/ 4)
>+										+ mode_lib->vba.UrgentLatencyPixelDataOnly));
>+
>+	CriticalCompression = 2.0 * mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK
>+			* mode_lib->vba.UrgentLatencyPixelDataOnly
>+			/ (ReturnBandwidthToDCN * mode_lib->vba.UrgentLatencyPixelDataOnly
>+					+ (mode_lib->vba.ROBBufferSizeInKByte
>+							- mode_lib->vba.PixelChunkSizeInKByte)
>+							* 1024);
>+
>+	if (DCCEnabledAnyPlane && CriticalCompression > 1.0 && CriticalCompression < 4.0)
>+		ReturnBW =
>+				dml_min(
>+						ReturnBW,
>+						4.0 * ReturnBandwidthToDCN
>+								* (mode_lib->vba.ROBBufferSizeInKByte
>+										- mode_lib->vba.PixelChunkSizeInKByte)
>+								* 1024
>+								* mode_lib->vba.ReturnBusWidth
>+								* mode_lib->vba.DCFCLK
>+								* mode_lib->vba.UrgentLatencyPixelDataOnly
>+								/ dml_pow(
>+										(ReturnBandwidthToDCN
>+												* mode_lib->vba.UrgentLatencyPixelDataOnly
>+												+ (mode_lib->vba.ROBBufferSizeInKByte
>+														- mode_lib->vba.PixelChunkSizeInKByte)
>+														* 1024),
>+										2));
>+
>+	return ReturnBW;
>+}
>+
>+static unsigned int dscceComputeDelay(
>+		unsigned int bpc,
>+		double bpp,
>+		unsigned int sliceWidth,
>+		unsigned int numSlices,
>+		enum output_format_class pixelFormat)
>+{
>+	// valid bpc         = source bits per component in the set of {8, 10, 12}
>+	// valid bpp         = increments of 1/16 of a bit
>+	//                    min = 6/7/8 in N420/N422/444, respectively
>+	//                    max = such that compression is 1:1
>+	//valid sliceWidth  = number of pixels per slice line, must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode)
>+	//valid numSlices   = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4}
>+	//valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420}
>+
>+	// fixed value
>+	unsigned int rcModelSize = 8192;
>+
>+	// N422/N420 operate at 2 pixels per clock
>+	unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, s, ix, wx, p, l0, a, ax, l,
>+			Delay, pixels;
>+
>+	if (pixelFormat == dm_n422 || pixelFormat == dm_420)
>+		pixelsPerClock = 2;
>+	// #all other modes operate at 1 pixel per clock
>+	else
>+		pixelsPerClock = 1;
>+
>+	//initial transmit delay as per PPS
>+	initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock);
>+
>+	//compute ssm delay
>+	if (bpc == 8)
>+		D = 81;
>+	else if (bpc == 10)
>+		D = 89;
>+	else
>+		D = 113;
>+
>+	//divide by pixel per cycle to compute slice width as seen by DSC
>+	w = sliceWidth / pixelsPerClock;
>+
>+	//422 mode has an additional cycle of delay
>+	if (pixelFormat == dm_s422)
>+		s = 1;
>+	else
>+		s = 0;
>+
>+	//main calculation for the dscce
>+	ix = initalXmitDelay + 45;
>+	wx = (w + 2) / 3;
>+	p = 3 * wx - w;
>+	l0 = ix / w;
>+	a = ix + p * l0;
>+	ax = (a + 2) / 3 + D + 6 + 1;
>+	l = (ax + wx - 1) / wx;
>+	if ((ix % w) == 0 && p != 0)
>+		lstall = 1;
>+	else
>+		lstall = 0;
>+	Delay = l * wx * (numSlices - 1) + ax + s + lstall + 22;
>+
>+	//dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels
>+	pixels = Delay * 3 * pixelsPerClock;
>+	return pixels;
>+}
>+
>+static unsigned int dscComputeDelay(enum output_format_class pixelFormat)
>+{
>+	unsigned int Delay = 0;
>+
>+	if (pixelFormat == dm_420) {
>+		//   sfr
>+		Delay = Delay + 2;
>+		//   dsccif
>+		Delay = Delay + 0;
>+		//   dscc - input deserializer
>+		Delay = Delay + 3;
>+		//   dscc gets pixels every other cycle
>+		Delay = Delay + 2;
>+		//   dscc - input cdc fifo
>+		Delay = Delay + 12;
>+		//   dscc gets pixels every other cycle
>+		Delay = Delay + 13;
>+		//   dscc - cdc uncertainty
>+		Delay = Delay + 2;
>+		//   dscc - output cdc fifo
>+		Delay = Delay + 7;
>+		//   dscc gets pixels every other cycle
>+		Delay = Delay + 3;
>+		//   dscc - cdc uncertainty
>+		Delay = Delay + 2;
>+		//   dscc - output serializer
>+		Delay = Delay + 1;
>+		//   sft
>+		Delay = Delay + 1;
>+	} else if (pixelFormat == dm_n422) {
>+		//   sfr
>+		Delay = Delay + 2;
>+		//   dsccif
>+		Delay = Delay + 1;
>+		//   dscc - input deserializer
>+		Delay = Delay + 5;
>+		//  dscc - input cdc fifo
>+		Delay = Delay + 25;
>+		//   dscc - cdc uncertainty
>+		Delay = Delay + 2;
>+		//   dscc - output cdc fifo
>+		Delay = Delay + 10;
>+		//   dscc - cdc uncertainty
>+		Delay = Delay + 2;
>+		//   dscc - output serializer
>+		Delay = Delay + 1;
>+		//   sft
>+		Delay = Delay + 1;
>+	} else {
>+		//   sfr
>+		Delay = Delay + 2;
>+		//   dsccif
>+		Delay = Delay + 0;
>+		//   dscc - input deserializer
>+		Delay = Delay + 3;
>+		//   dscc - input cdc fifo
>+		Delay = Delay + 12;
>+		//   dscc - cdc uncertainty
>+		Delay = Delay + 2;
>+		//   dscc - output cdc fifo
>+		Delay = Delay + 7;
>+		//   dscc - output serializer
>+		Delay = Delay + 1;
>+		//   dscc - cdc uncertainty
>+		Delay = Delay + 2;
>+		//   sft
>+		Delay = Delay + 1;
>+	}
>+
>+	return Delay;
>+}
>+
>+static bool CalculateDelayAfterScaler(
>+		struct display_mode_lib *mode_lib,
>+		double ReturnBW,
>+		double ReadBandwidthPlaneLuma,
>+		double ReadBandwidthPlaneChroma,
>+		double TotalDataReadBandwidth,
>+		double DisplayPipeLineDeliveryTimeLuma,
>+		double DisplayPipeLineDeliveryTimeChroma,
>+		double DPPCLK,
>+		double DISPCLK,
>+		double PixelClock,
>+		unsigned int DSCDelay,
>+		unsigned int DPPPerPlane,
>+		bool ScalerEnabled,
>+		unsigned int NumberOfCursors,
>+		double DPPCLKDelaySubtotal,
>+		double DPPCLKDelaySCL,
>+		double DPPCLKDelaySCLLBOnly,
>+		double DPPCLKDelayCNVCFormater,
>+		double DPPCLKDelayCNVCCursor,
>+		double DISPCLKDelaySubtotal,
>+		unsigned int ScalerRecoutWidth,
>+		enum output_format_class OutputFormat,
>+		unsigned int HTotal,
>+		unsigned int SwathWidthSingleDPPY,
>+		double BytePerPixelDETY,
>+		double BytePerPixelDETC,
>+		unsigned int SwathHeightY,
>+		unsigned int SwathHeightC,
>+		bool Interlace,
>+		bool ProgressiveToInterlaceUnitInOPP,
>+		double *DSTXAfterScaler,
>+		double *DSTYAfterScaler
>+		)
>+{
>+	unsigned int DPPCycles, DISPCLKCycles;
>+	double DataFabricLineDeliveryTimeLuma;
>+	double DataFabricLineDeliveryTimeChroma;
>+	double DSTTotalPixelsAfterScaler;
>+
>+	DataFabricLineDeliveryTimeLuma = SwathWidthSingleDPPY * SwathHeightY * dml_ceil(BytePerPixelDETY, 1) / (mode_lib->vba.ReturnBW * ReadBandwidthPlaneLuma / TotalDataReadBandwidth);
>+	mode_lib->vba.LastPixelOfLineExtraWatermark = dml_max(mode_lib->vba.LastPixelOfLineExtraWatermark, DataFabricLineDeliveryTimeLuma - DisplayPipeLineDeliveryTimeLuma);
>+
>+	if (BytePerPixelDETC != 0) {
>+		DataFabricLineDeliveryTimeChroma = SwathWidthSingleDPPY / 2 * SwathHeightC * dml_ceil(BytePerPixelDETC, 2) / (mode_lib->vba.ReturnBW * ReadBandwidthPlaneChroma / TotalDataReadBandwidth);
>+		mode_lib->vba.LastPixelOfLineExtraWatermark = dml_max(mode_lib->vba.LastPixelOfLineExtraWatermark, DataFabricLineDeliveryTimeChroma - DisplayPipeLineDeliveryTimeChroma);
>+	}
>+
>+	if (ScalerEnabled)
>+		DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL;
>+	else
>+		DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly;
>+
>+	DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + NumberOfCursors * DPPCLKDelayCNVCCursor;
>+
>+	DISPCLKCycles = DISPCLKDelaySubtotal;
>+
>+	if (DPPCLK == 0.0 || DISPCLK == 0.0)
>+		return true;
>+
>+	*DSTXAfterScaler = DPPCycles * PixelClock / DPPCLK + DISPCLKCycles * PixelClock / DISPCLK
>+			+ DSCDelay;
>+
>+	if (DPPPerPlane > 1)
>+		*DSTXAfterScaler = *DSTXAfterScaler + ScalerRecoutWidth;
>+
>+	if (OutputFormat == dm_420 || (Interlace && ProgressiveToInterlaceUnitInOPP))
>+		*DSTYAfterScaler = 1;
>+	else
>+		*DSTYAfterScaler = 0;
>+
>+	DSTTotalPixelsAfterScaler = ((double) (*DSTYAfterScaler * HTotal)) + *DSTXAfterScaler;
>+	*DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / HTotal, 1);
>+	*DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * HTotal));
>+
>+	return true;
>+}
>+
>+static bool CalculatePrefetchSchedule(
>+		struct display_mode_lib *mode_lib,
>+		double DPPCLK,
>+		double DISPCLK,
>+		double PixelClock,
>+		double DCFCLKDeepSleep,
>+		unsigned int DPPPerPlane,
>+		unsigned int NumberOfCursors,
>+		unsigned int VBlank,
>+		unsigned int HTotal,
>+		unsigned int MaxInterDCNTileRepeaters,
>+		unsigned int VStartup,
>+		unsigned int PageTableLevels,
>+		bool GPUVMEnable,
>+		bool DynamicMetadataEnable,
>+		unsigned int DynamicMetadataLinesBeforeActiveRequired,
>+		unsigned int DynamicMetadataTransmittedBytes,
>+		bool DCCEnable,
>+		double UrgentLatencyPixelDataOnly,
>+		double UrgentExtraLatency,
>+		double TCalc,
>+		unsigned int PDEAndMetaPTEBytesFrame,
>+		unsigned int MetaRowByte,
>+		unsigned int PixelPTEBytesPerRow,
>+		double PrefetchSourceLinesY,
>+		unsigned int SwathWidthY,
>+		double BytePerPixelDETY,
>+		double VInitPreFillY,
>+		unsigned int MaxNumSwathY,
>+		double PrefetchSourceLinesC,
>+		double BytePerPixelDETC,
>+		double VInitPreFillC,
>+		unsigned int MaxNumSwathC,
>+		unsigned int SwathHeightY,
>+		unsigned int SwathHeightC,
>+		double TWait,
>+		bool XFCEnabled,
>+		double XFCRemoteSurfaceFlipDelay,
>+		bool InterlaceEnable,
>+		bool ProgressiveToInterlaceUnitInOPP,
>+		double DSTXAfterScaler,
>+		double DSTYAfterScaler,
>+		double *DestinationLinesForPrefetch,
>+		double *PrefetchBandwidth,
>+		double *DestinationLinesToRequestVMInVBlank,
>+		double *DestinationLinesToRequestRowInVBlank,
>+		double *VRatioPrefetchY,
>+		double *VRatioPrefetchC,
>+		double *RequiredPrefetchPixDataBW,
>+		double *Tno_bw,
>+		unsigned int *VUpdateOffsetPix,
>+		double *VUpdateWidthPix,
>+		double *VReadyOffsetPix)
>+{
>+	bool MyError = false;
>+	double TotalRepeaterDelayTime;
>+	double Tdm, LineTime, Tsetup;
>+	double dst_y_prefetch_equ;
>+	double Tsw_oto;
>+	double prefetch_bw_oto;
>+	double Tvm_oto;
>+	double Tr0_oto;
>+	double Tpre_oto;
>+	double dst_y_prefetch_oto;
>+	double TimeForFetchingMetaPTE = 0;
>+	double TimeForFetchingRowInVBlank = 0;
>+	double LinesToRequestPrefetchPixelData = 0;
>+
>+	*VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1);
>+	TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK);
>+	*VUpdateWidthPix = (14.0 / DCFCLKDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime)
>+			* PixelClock;
>+
>+	*VReadyOffsetPix = dml_max(
>+			150.0 / DPPCLK,
>+			TotalRepeaterDelayTime + 20.0 / DCFCLKDeepSleep + 10.0 / DPPCLK)
>+			* PixelClock;
>+
>+	Tsetup = (double) (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock;
>+
>+	LineTime = (double) HTotal / PixelClock;
>+
>+	if (DynamicMetadataEnable) {
>+		double Tdmbf, Tdmec, Tdmsks;
>+
>+		Tdm = dml_max(0.0, UrgentExtraLatency - TCalc);
>+		Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK;
>+		Tdmec = LineTime;
>+		if (DynamicMetadataLinesBeforeActiveRequired == 0)
>+			Tdmsks = VBlank * LineTime / 2.0;
>+		else
>+			Tdmsks = DynamicMetadataLinesBeforeActiveRequired * LineTime;
>+		if (InterlaceEnable && !ProgressiveToInterlaceUnitInOPP)
>+			Tdmsks = Tdmsks / 2;
>+		if (VStartup * LineTime
>+				< Tsetup + TWait + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) {
>+			MyError = true;
>+		}
>+	} else
>+		Tdm = 0;
>+
>+	if (GPUVMEnable) {
>+		if (PageTableLevels == 4)
>+			*Tno_bw = UrgentExtraLatency + UrgentLatencyPixelDataOnly;
>+		else if (PageTableLevels == 3)
>+			*Tno_bw = UrgentExtraLatency;
>+		else
>+			*Tno_bw = 0;
>+	} else if (DCCEnable)
>+		*Tno_bw = LineTime;
>+	else
>+		*Tno_bw = LineTime / 4;
>+
>+	dst_y_prefetch_equ = VStartup - dml_max(TCalc + TWait, XFCRemoteSurfaceFlipDelay) / LineTime
>+			- (Tsetup + Tdm) / LineTime
>+			- (DSTYAfterScaler + DSTXAfterScaler / HTotal);
>+
>+	Tsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
>+
>+	prefetch_bw_oto = (MetaRowByte + PixelPTEBytesPerRow
>+			+ PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
>+			+ PrefetchSourceLinesC * SwathWidthY / 2 * dml_ceil(BytePerPixelDETC, 2))
>+			/ Tsw_oto;
>+
>+	if (GPUVMEnable == true) {
>+		Tvm_oto =
>+				dml_max(
>+						*Tno_bw + PDEAndMetaPTEBytesFrame / prefetch_bw_oto,
>+						dml_max(
>+								UrgentExtraLatency
>+										+ UrgentLatencyPixelDataOnly
>+												* (PageTableLevels
>+														- 1),
>+								LineTime / 4.0));
>+	} else
>+		Tvm_oto = LineTime / 4.0;
>+
>+	if ((GPUVMEnable == true || DCCEnable == true)) {
>+		Tr0_oto = dml_max(
>+				(MetaRowByte + PixelPTEBytesPerRow) / prefetch_bw_oto,
>+				dml_max(UrgentLatencyPixelDataOnly, dml_max(LineTime - Tvm_oto, LineTime / 4)));
>+	} else
>+		Tr0_oto = LineTime - Tvm_oto;
>+
>+	Tpre_oto = Tvm_oto + Tr0_oto + Tsw_oto;
>+
>+	dst_y_prefetch_oto = Tpre_oto / LineTime;
>+
>+	if (dst_y_prefetch_oto < dst_y_prefetch_equ)
>+		*DestinationLinesForPrefetch = dst_y_prefetch_oto;
>+	else
>+		*DestinationLinesForPrefetch = dst_y_prefetch_equ;
>+
>+	*DestinationLinesForPrefetch = dml_floor(4.0 * (*DestinationLinesForPrefetch + 0.125), 1)
>+			/ 4;
>+
>+	dml_print("DML: VStartup: %d\n", VStartup);
>+	dml_print("DML: TCalc: %f\n", TCalc);
>+	dml_print("DML: TWait: %f\n", TWait);
>+	dml_print("DML: XFCRemoteSurfaceFlipDelay: %f\n", XFCRemoteSurfaceFlipDelay);
>+	dml_print("DML: LineTime: %f\n", LineTime);
>+	dml_print("DML: Tsetup: %f\n", Tsetup);
>+	dml_print("DML: Tdm: %f\n", Tdm);
>+	dml_print("DML: DSTYAfterScaler: %f\n", DSTYAfterScaler);
>+	dml_print("DML: DSTXAfterScaler: %f\n", DSTXAfterScaler);
>+	dml_print("DML: HTotal: %d\n", HTotal);
>+
>+	*PrefetchBandwidth = 0;
>+	*DestinationLinesToRequestVMInVBlank = 0;
>+	*DestinationLinesToRequestRowInVBlank = 0;
>+	*VRatioPrefetchY = 0;
>+	*VRatioPrefetchC = 0;
>+	*RequiredPrefetchPixDataBW = 0;
>+	if (*DestinationLinesForPrefetch > 1) {
>+		*PrefetchBandwidth = (PDEAndMetaPTEBytesFrame + 2 * MetaRowByte
>+				+ 2 * PixelPTEBytesPerRow
>+				+ PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1)
>+				+ PrefetchSourceLinesC * SwathWidthY / 2
>+						* dml_ceil(BytePerPixelDETC, 2))
>+				/ (*DestinationLinesForPrefetch * LineTime - *Tno_bw);
>+		if (GPUVMEnable) {
>+			TimeForFetchingMetaPTE =
>+					dml_max(
>+							*Tno_bw
>+									+ (double) PDEAndMetaPTEBytesFrame
>+											/ *PrefetchBandwidth,
>+							dml_max(
>+									UrgentExtraLatency
>+											+ UrgentLatencyPixelDataOnly
>+													* (PageTableLevels
>+															- 1),
>+									LineTime / 4));
>+		} else {
>+			if (NumberOfCursors > 0 || XFCEnabled)
>+				TimeForFetchingMetaPTE = LineTime / 4;
>+			else
>+				TimeForFetchingMetaPTE = 0.0;
>+		}
>+
>+		if ((GPUVMEnable == true || DCCEnable == true)) {
>+			TimeForFetchingRowInVBlank =
>+					dml_max(
>+							(MetaRowByte + PixelPTEBytesPerRow)
>+									/ *PrefetchBandwidth,
>+							dml_max(
>+									UrgentLatencyPixelDataOnly,
>+									dml_max(
>+											LineTime
>+													- TimeForFetchingMetaPTE,
>+											LineTime
>+													/ 4.0)));
>+		} else {
>+			if (NumberOfCursors > 0 || XFCEnabled)
>+				TimeForFetchingRowInVBlank = LineTime - TimeForFetchingMetaPTE;
>+			else
>+				TimeForFetchingRowInVBlank = 0.0;
>+		}
>+
>+		*DestinationLinesToRequestVMInVBlank = dml_floor(
>+				4.0 * (TimeForFetchingMetaPTE / LineTime + 0.125),
>+				1) / 4.0;
>+
>+		*DestinationLinesToRequestRowInVBlank = dml_floor(
>+				4.0 * (TimeForFetchingRowInVBlank / LineTime + 0.125),
>+				1) / 4.0;
>+
>+		LinesToRequestPrefetchPixelData =
>+				*DestinationLinesForPrefetch
>+						- ((NumberOfCursors > 0 || GPUVMEnable
>+								|| DCCEnable) ?
>+								(*DestinationLinesToRequestVMInVBlank
>+										+ *DestinationLinesToRequestRowInVBlank) :
>+								0.0);
>+
>+		if (LinesToRequestPrefetchPixelData > 0) {
>+
>+			*VRatioPrefetchY = (double) PrefetchSourceLinesY
>+					/ LinesToRequestPrefetchPixelData;
>+			*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
>+			if ((SwathHeightY > 4) && (VInitPreFillY > 3)) {
>+				if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) {
>+					*VRatioPrefetchY =
>+							dml_max(
>+									(double) PrefetchSourceLinesY
>+											/ LinesToRequestPrefetchPixelData,
>+									(double) MaxNumSwathY
>+											* SwathHeightY
>+											/ (LinesToRequestPrefetchPixelData
>+													- (VInitPreFillY
>+															- 3.0)
>+															/ 2.0));
>+					*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
>+				} else {
>+					MyError = true;
>+					*VRatioPrefetchY = 0;
>+				}
>+			}
>+
>+			*VRatioPrefetchC = (double) PrefetchSourceLinesC
>+					/ LinesToRequestPrefetchPixelData;
>+			*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
>+
>+			if ((SwathHeightC > 4)) {
>+				if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) {
>+					*VRatioPrefetchC =
>+							dml_max(
>+									*VRatioPrefetchC,
>+									(double) MaxNumSwathC
>+											* SwathHeightC
>+											/ (LinesToRequestPrefetchPixelData
>+													- (VInitPreFillC
>+															- 3.0)
>+															/ 2.0));
>+					*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
>+				} else {
>+					MyError = true;
>+					*VRatioPrefetchC = 0;
>+				}
>+			}
>+
>+			*RequiredPrefetchPixDataBW =
>+					DPPPerPlane
>+							* ((double) PrefetchSourceLinesY
>+									/ LinesToRequestPrefetchPixelData
>+									* dml_ceil(
>+											BytePerPixelDETY,
>+											1)
>+									+ (double) PrefetchSourceLinesC
>+											/ LinesToRequestPrefetchPixelData
>+											* dml_ceil(
>+													BytePerPixelDETC,
>+													2)
>+											/ 2)
>+							* SwathWidthY / LineTime;
>+		} else {
>+			MyError = true;
>+			*VRatioPrefetchY = 0;
>+			*VRatioPrefetchC = 0;
>+			*RequiredPrefetchPixDataBW = 0;
>+		}
>+
>+	} else {
>+		MyError = true;
>+	}
>+
>+	if (MyError) {
>+		*PrefetchBandwidth = 0;
>+		TimeForFetchingMetaPTE = 0;
>+		TimeForFetchingRowInVBlank = 0;
>+		*DestinationLinesToRequestVMInVBlank = 0;
>+		*DestinationLinesToRequestRowInVBlank = 0;
>+		*DestinationLinesForPrefetch = 0;
>+		LinesToRequestPrefetchPixelData = 0;
>+		*VRatioPrefetchY = 0;
>+		*VRatioPrefetchC = 0;
>+		*RequiredPrefetchPixDataBW = 0;
>+	}
>+
>+	return MyError;
>+}
>+
>+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed)
>+{
>+	return VCOSpeed * 4 / dml_floor(VCOSpeed * 4 / Clock, 1);
>+}
>+
>+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed)
>+{
>+	return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1);
>+}
>+
>+static double CalculatePrefetchSourceLines(
>+		struct display_mode_lib *mode_lib,
>+		double VRatio,
>+		double vtaps,
>+		bool Interlace,
>+		bool ProgressiveToInterlaceUnitInOPP,
>+		unsigned int SwathHeight,
>+		unsigned int ViewportYStart,
>+		double *VInitPreFill,
>+		unsigned int *MaxNumSwath)
>+{
>+	unsigned int MaxPartialSwath;
>+
>+	if (ProgressiveToInterlaceUnitInOPP)
>+		*VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1);
>+	else
>+		*VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
>+
>+	if (!mode_lib->vba.IgnoreViewportPositioning) {
>+
>+		*MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0;
>+
>+		if (*VInitPreFill > 1.0)
>+			MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight;
>+		else
>+			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2)
>+					% SwathHeight;
>+		MaxPartialSwath = dml_max(1U, MaxPartialSwath);
>+
>+	} else {
>+
>+		if (ViewportYStart != 0)
>+			dml_print(
>+					"WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n");
>+
>+		*MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1);
>+
>+		if (*VInitPreFill > 1.0)
>+			MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight;
>+		else
>+			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1)
>+					% SwathHeight;
>+	}
>+
>+	return *MaxNumSwath * SwathHeight + MaxPartialSwath;
>+}
>+
>+static unsigned int CalculateVMAndRowBytes(
>+		struct display_mode_lib *mode_lib,
>+		bool DCCEnable,
>+		unsigned int BlockHeight256Bytes,
>+		unsigned int BlockWidth256Bytes,
>+		enum source_format_class SourcePixelFormat,
>+		unsigned int SurfaceTiling,
>+		unsigned int BytePerPixel,
>+		enum scan_direction_class ScanDirection,
>+		unsigned int ViewportWidth,
>+		unsigned int ViewportHeight,
>+		unsigned int SwathWidth,
>+		bool GPUVMEnable,
>+		unsigned int VMMPageSize,
>+		unsigned int PTEBufferSizeInRequestsLuma,
>+		unsigned int PDEProcessingBufIn64KBReqs,
>+		unsigned int Pitch,
>+		unsigned int DCCMetaPitch,
>+		unsigned int *MacroTileWidth,
>+		unsigned int *MetaRowByte,
>+		unsigned int *PixelPTEBytesPerRow,
>+		bool *PTEBufferSizeNotExceeded,
>+		unsigned int *dpte_row_height,
>+		unsigned int *meta_row_height)
>+{
>+	unsigned int MetaRequestHeight;
>+	unsigned int MetaRequestWidth;
>+	unsigned int MetaSurfWidth;
>+	unsigned int MetaSurfHeight;
>+	unsigned int MPDEBytesFrame;
>+	unsigned int MetaPTEBytesFrame;
>+	unsigned int DCCMetaSurfaceBytes;
>+
>+	unsigned int MacroTileSizeBytes;
>+	unsigned int MacroTileHeight;
>+	unsigned int DPDE0BytesFrame;
>+	unsigned int ExtraDPDEBytesFrame;
>+	unsigned int PDEAndMetaPTEBytesFrame;
>+
>+	if (DCCEnable == true) {
>+		MetaRequestHeight = 8 * BlockHeight256Bytes;
>+		MetaRequestWidth = 8 * BlockWidth256Bytes;
>+		if (ScanDirection == dm_horz) {
>+			*meta_row_height = MetaRequestHeight;
>+			MetaSurfWidth = dml_ceil((double) SwathWidth - 1, MetaRequestWidth)
>+					+ MetaRequestWidth;
>+			*MetaRowByte = MetaSurfWidth * MetaRequestHeight * BytePerPixel / 256.0;
>+		} else {
>+			*meta_row_height = MetaRequestWidth;
>+			MetaSurfHeight = dml_ceil((double) SwathWidth - 1, MetaRequestHeight)
>+					+ MetaRequestHeight;
>+			*MetaRowByte = MetaSurfHeight * MetaRequestWidth * BytePerPixel / 256.0;
>+		}
>+		if (ScanDirection == dm_horz) {
>+			DCCMetaSurfaceBytes = DCCMetaPitch
>+					* (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes)
>+							+ 64 * BlockHeight256Bytes) * BytePerPixel
>+					/ 256;
>+		} else {
>+			DCCMetaSurfaceBytes = DCCMetaPitch
>+					* (dml_ceil(
>+							(double) ViewportHeight - 1,
>+							64 * BlockHeight256Bytes)
>+							+ 64 * BlockHeight256Bytes) * BytePerPixel
>+					/ 256;
>+		}
>+		if (GPUVMEnable == true) {
>+			MetaPTEBytesFrame = (dml_ceil(
>+					(double) (DCCMetaSurfaceBytes - VMMPageSize)
>+							/ (8 * VMMPageSize),
>+					1) + 1) * 64;
>+			MPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 1);
>+		} else {
>+			MetaPTEBytesFrame = 0;
>+			MPDEBytesFrame = 0;
>+		}
>+	} else {
>+		MetaPTEBytesFrame = 0;
>+		MPDEBytesFrame = 0;
>+		*MetaRowByte = 0;
>+	}
>+
>+	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_lvp) {
>+		MacroTileSizeBytes = 256;
>+		MacroTileHeight = BlockHeight256Bytes;
>+	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
>+			|| SurfaceTiling == dm_sw_4kb_d || SurfaceTiling == dm_sw_4kb_d_x) {
>+		MacroTileSizeBytes = 4096;
>+		MacroTileHeight = 4 * BlockHeight256Bytes;
>+	} else if (SurfaceTiling == dm_sw_64kb_s || SurfaceTiling == dm_sw_64kb_s_t
>+			|| SurfaceTiling == dm_sw_64kb_s_x || SurfaceTiling == dm_sw_64kb_d
>+			|| SurfaceTiling == dm_sw_64kb_d_t || SurfaceTiling == dm_sw_64kb_d_x
>+			|| SurfaceTiling == dm_sw_64kb_r_x) {
>+		MacroTileSizeBytes = 65536;
>+		MacroTileHeight = 16 * BlockHeight256Bytes;
>+	} else {
>+		MacroTileSizeBytes = 262144;
>+		MacroTileHeight = 32 * BlockHeight256Bytes;
>+	}
>+	*MacroTileWidth = MacroTileSizeBytes / BytePerPixel / MacroTileHeight;
>+
>+	if (GPUVMEnable == true && mode_lib->vba.GPUVMMaxPageTableLevels > 1) {
>+		if (ScanDirection == dm_horz) {
>+			DPDE0BytesFrame =
>+					64
>+							* (dml_ceil(
>+									((Pitch
>+											* (dml_ceil(
>+													ViewportHeight
>+															- 1,
>+													MacroTileHeight)
>+													+ MacroTileHeight)
>+											* BytePerPixel)
>+											- MacroTileSizeBytes)
>+											/ (8
>+													* 2097152),
>+									1) + 1);
>+		} else {
>+			DPDE0BytesFrame =
>+					64
>+							* (dml_ceil(
>+									((Pitch
>+											* (dml_ceil(
>+													(double) SwathWidth
>+															- 1,
>+													MacroTileHeight)
>+													+ MacroTileHeight)
>+											* BytePerPixel)
>+											- MacroTileSizeBytes)
>+											/ (8
>+													* 2097152),
>+									1) + 1);
>+		}
>+		ExtraDPDEBytesFrame = 128 * (mode_lib->vba.GPUVMMaxPageTableLevels - 2);
>+	} else {
>+		DPDE0BytesFrame = 0;
>+		ExtraDPDEBytesFrame = 0;
>+	}
>+
>+	PDEAndMetaPTEBytesFrame = MetaPTEBytesFrame + MPDEBytesFrame + DPDE0BytesFrame
>+			+ ExtraDPDEBytesFrame;
>+
>+	if (GPUVMEnable == true) {
>+		unsigned int PTERequestSize;
>+		unsigned int PixelPTEReqHeight;
>+		unsigned int PixelPTEReqWidth;
>+		double FractionOfPTEReturnDrop;
>+		unsigned int EffectivePDEProcessingBufIn64KBReqs;
>+
>+		if (SurfaceTiling == dm_sw_linear) {
>+			PixelPTEReqHeight = 1;
>+			PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel;
>+			PTERequestSize = 64;
>+			FractionOfPTEReturnDrop = 0;
>+		} else if (MacroTileSizeBytes == 4096) {
>+			PixelPTEReqHeight = MacroTileHeight;
>+			PixelPTEReqWidth = 8 * *MacroTileWidth;
>+			PTERequestSize = 64;
>+			if (ScanDirection == dm_horz)
>+				FractionOfPTEReturnDrop = 0;
>+			else
>+				FractionOfPTEReturnDrop = 7 / 8;
>+		} else if (VMMPageSize == 4096 && MacroTileSizeBytes > 4096) {
>+			PixelPTEReqHeight = 16 * BlockHeight256Bytes;
>+			PixelPTEReqWidth = 16 * BlockWidth256Bytes;
>+			PTERequestSize = 128;
>+			FractionOfPTEReturnDrop = 0;
>+		} else {
>+			PixelPTEReqHeight = MacroTileHeight;
>+			PixelPTEReqWidth = 8 * *MacroTileWidth;
>+			PTERequestSize = 64;
>+			FractionOfPTEReturnDrop = 0;
>+		}
>+
>+		if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10)
>+			EffectivePDEProcessingBufIn64KBReqs = PDEProcessingBufIn64KBReqs / 2;
>+		else
>+			EffectivePDEProcessingBufIn64KBReqs = PDEProcessingBufIn64KBReqs;
>+
>+		if (SurfaceTiling == dm_sw_linear) {
>+			*dpte_row_height =
>+					dml_min(
>+							128,
>+							1
>+									<< (unsigned int) dml_floor(
>+											dml_log2(
>+													dml_min(
>+															(double) PTEBufferSizeInRequestsLuma
>+																	* PixelPTEReqWidth,
>+															EffectivePDEProcessingBufIn64KBReqs
>+																	* 65536.0
>+																	/ BytePerPixel)
>+															/ Pitch),
>+											1));
>+			*PixelPTEBytesPerRow = PTERequestSize
>+					* (dml_ceil(
>+							(double) (Pitch * *dpte_row_height - 1)
>+									/ PixelPTEReqWidth,
>+							1) + 1);
>+		} else if (ScanDirection == dm_horz) {
>+			*dpte_row_height = PixelPTEReqHeight;
>+			*PixelPTEBytesPerRow = PTERequestSize
>+					* (dml_ceil(((double) SwathWidth - 1) / PixelPTEReqWidth, 1)
>+							+ 1);
>+		} else {
>+			*dpte_row_height = dml_min(PixelPTEReqWidth, *MacroTileWidth);
>+			*PixelPTEBytesPerRow = PTERequestSize
>+					* (dml_ceil(
>+							((double) SwathWidth - 1)
>+									/ PixelPTEReqHeight,
>+							1) + 1);
>+		}
>+		if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop)
>+				<= 64 * PTEBufferSizeInRequestsLuma) {
>+			*PTEBufferSizeNotExceeded = true;
>+		} else {
>+			*PTEBufferSizeNotExceeded = false;
>+		}
>+	} else {
>+		*PixelPTEBytesPerRow = 0;
>+		*PTEBufferSizeNotExceeded = true;
>+	}
>+
>+	return PDEAndMetaPTEBytesFrame;
>+}
>+
>+static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
>+		struct display_mode_lib *mode_lib)
>+{
>+	unsigned int j, k;
>+
>+	mode_lib->vba.WritebackDISPCLK = 0.0;
>+	mode_lib->vba.DISPCLKWithRamping = 0;
>+	mode_lib->vba.DISPCLKWithoutRamping = 0;
>+	mode_lib->vba.GlobalDPPCLK = 0.0;
>+
>+	// dml_ml->vba.DISPCLK and dml_ml->vba.DPPCLK Calculation
>+	//
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.WritebackEnable[k]) {
>+			mode_lib->vba.WritebackDISPCLK =
>+					dml_max(
>+							mode_lib->vba.WritebackDISPCLK,
>+							CalculateWriteBackDISPCLK(
>+									mode_lib->vba.WritebackPixelFormat[k],
>+									mode_lib->vba.PixelClock[k],
>+									mode_lib->vba.WritebackHRatio[k],
>+									mode_lib->vba.WritebackVRatio[k],
>+									mode_lib->vba.WritebackLumaHTaps[k],
>+									mode_lib->vba.WritebackLumaVTaps[k],
>+									mode_lib->vba.WritebackChromaHTaps[k],
>+									mode_lib->vba.WritebackChromaVTaps[k],
>+									mode_lib->vba.WritebackDestinationWidth[k],
>+									mode_lib->vba.HTotal[k],
>+									mode_lib->vba.WritebackChromaLineBufferWidth));
>+		}
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.HRatio[k] > 1) {
>+			mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
>+					mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+					mode_lib->vba.MaxPSCLToLBThroughput
>+							* mode_lib->vba.HRatio[k]
>+							/ dml_ceil(
>+									mode_lib->vba.htaps[k]
>+											/ 6.0,
>+									1));
>+		} else {
>+			mode_lib->vba.PSCL_THROUGHPUT_LUMA[k] = dml_min(
>+					mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+					mode_lib->vba.MaxPSCLToLBThroughput);
>+		}
>+
>+		mode_lib->vba.DPPCLKUsingSingleDPPLuma =
>+				mode_lib->vba.PixelClock[k]
>+						* dml_max(
>+								mode_lib->vba.vtaps[k] / 6.0
>+										* dml_min(
>+												1.0,
>+												mode_lib->vba.HRatio[k]),
>+								dml_max(
>+										mode_lib->vba.HRatio[k]
>+												* mode_lib->vba.VRatio[k]
>+												/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k],
>+										1.0));
>+
>+		if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
>+				&& mode_lib->vba.DPPCLKUsingSingleDPPLuma
>+						< 2 * mode_lib->vba.PixelClock[k]) {
>+			mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k];
>+		}
>+
>+		if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
>+			mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = 0.0;
>+			mode_lib->vba.DPPCLKUsingSingleDPP[k] =
>+					mode_lib->vba.DPPCLKUsingSingleDPPLuma;
>+		} else {
>+			if (mode_lib->vba.HRatio[k] > 1) {
>+				mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] =
>+						dml_min(
>+								mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+								mode_lib->vba.MaxPSCLToLBThroughput
>+										* mode_lib->vba.HRatio[k]
>+										/ 2
>+										/ dml_ceil(
>+												mode_lib->vba.HTAPsChroma[k]
>+														/ 6.0,
>+												1.0));
>+			} else {
>+				mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k] = dml_min(
>+						mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+						mode_lib->vba.MaxPSCLToLBThroughput);
>+			}
>+			mode_lib->vba.DPPCLKUsingSingleDPPChroma =
>+					mode_lib->vba.PixelClock[k]
>+							* dml_max(
>+									mode_lib->vba.VTAPsChroma[k]
>+											/ 6.0
>+											* dml_min(
>+													1.0,
>+													mode_lib->vba.HRatio[k]
>+															/ 2),
>+									dml_max(
>+											mode_lib->vba.HRatio[k]
>+													* mode_lib->vba.VRatio[k]
>+													/ 4
>+													/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k],
>+											1.0));
>+
>+			if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6)
>+					&& mode_lib->vba.DPPCLKUsingSingleDPPChroma
>+							< 2 * mode_lib->vba.PixelClock[k]) {
>+				mode_lib->vba.DPPCLKUsingSingleDPPChroma = 2
>+						* mode_lib->vba.PixelClock[k];
>+			}
>+
>+			mode_lib->vba.DPPCLKUsingSingleDPP[k] = dml_max(
>+					mode_lib->vba.DPPCLKUsingSingleDPPLuma,
>+					mode_lib->vba.DPPCLKUsingSingleDPPChroma);
>+		}
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.BlendingAndTiming[k] != k)
>+			continue;
>+		if (mode_lib->vba.ODMCombineEnabled[k]) {
>+			mode_lib->vba.DISPCLKWithRamping =
>+					dml_max(
>+							mode_lib->vba.DISPCLKWithRamping,
>+							mode_lib->vba.PixelClock[k] / 2
>+									* (1
>+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+													/ 100)
>+									* (1
>+											+ mode_lib->vba.DISPCLKRampingMargin
>+													/ 100));
>+			mode_lib->vba.DISPCLKWithoutRamping =
>+					dml_max(
>+							mode_lib->vba.DISPCLKWithoutRamping,
>+							mode_lib->vba.PixelClock[k] / 2
>+									* (1
>+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+													/ 100));
>+		} else if (!mode_lib->vba.ODMCombineEnabled[k]) {
>+			mode_lib->vba.DISPCLKWithRamping =
>+					dml_max(
>+							mode_lib->vba.DISPCLKWithRamping,
>+							mode_lib->vba.PixelClock[k]
>+									* (1
>+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+													/ 100)
>+									* (1
>+											+ mode_lib->vba.DISPCLKRampingMargin
>+													/ 100));
>+			mode_lib->vba.DISPCLKWithoutRamping =
>+					dml_max(
>+							mode_lib->vba.DISPCLKWithoutRamping,
>+							mode_lib->vba.PixelClock[k]
>+									* (1
>+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+													/ 100));
>+		}
>+	}
>+
>+	mode_lib->vba.DISPCLKWithRamping = dml_max(
>+			mode_lib->vba.DISPCLKWithRamping,
>+			mode_lib->vba.WritebackDISPCLK);
>+	mode_lib->vba.DISPCLKWithoutRamping = dml_max(
>+			mode_lib->vba.DISPCLKWithoutRamping,
>+			mode_lib->vba.WritebackDISPCLK);
>+
>+	ASSERT(mode_lib->vba.DISPCLKDPPCLKVCOSpeed != 0);
>+	mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(
>+			mode_lib->vba.DISPCLKWithRamping,
>+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
>+	mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(
>+			mode_lib->vba.DISPCLKWithoutRamping,
>+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
>+	mode_lib->vba.MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
>+			mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz,
>+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
>+	if (mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity
>+			> mode_lib->vba.MaxDispclkRoundedToDFSGranularity) {
>+		mode_lib->vba.DISPCLK_calculated =
>+				mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity;
>+	} else if (mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity
>+			> mode_lib->vba.MaxDispclkRoundedToDFSGranularity) {
>+		mode_lib->vba.DISPCLK_calculated = mode_lib->vba.MaxDispclkRoundedToDFSGranularity;
>+	} else {
>+		mode_lib->vba.DISPCLK_calculated =
>+				mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity;
>+	}
>+	DTRACE("   dispclk_mhz (calculated) = %f", mode_lib->vba.DISPCLK_calculated);
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.DPPPerPlane[k] == 0) {
>+			mode_lib->vba.DPPCLK_calculated[k] = 0;
>+		} else {
>+			mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.DPPCLKUsingSingleDPP[k]
>+					/ mode_lib->vba.DPPPerPlane[k]
>+					* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
>+		}
>+		mode_lib->vba.GlobalDPPCLK = dml_max(
>+				mode_lib->vba.GlobalDPPCLK,
>+				mode_lib->vba.DPPCLK_calculated[k]);
>+	}
>+	mode_lib->vba.GlobalDPPCLK = RoundToDFSGranularityUp(
>+			mode_lib->vba.GlobalDPPCLK,
>+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255
>+				* dml_ceil(
>+						mode_lib->vba.DPPCLK_calculated[k] * 255
>+								/ mode_lib->vba.GlobalDPPCLK,
>+						1);
>+		DTRACE("   dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]);
>+	}
>+
>+	// Urgent Watermark
>+	mode_lib->vba.DCCEnabledAnyPlane = false;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
>+		if (mode_lib->vba.DCCEnable[k])
>+			mode_lib->vba.DCCEnabledAnyPlane = true;
>+
>+	mode_lib->vba.ReturnBandwidthToDCN = dml_min(
>+			mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK,
>+			mode_lib->vba.FabricAndDRAMBandwidth * 1000)
>+			* mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly / 100;
>+
>+	mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBandwidthToDCN;
>+	mode_lib->vba.ReturnBW = adjust_ReturnBW(
>+			mode_lib,
>+			mode_lib->vba.ReturnBW,
>+			mode_lib->vba.DCCEnabledAnyPlane,
>+			mode_lib->vba.ReturnBandwidthToDCN);
>+
>+	// Let's do this calculation again??
>+	mode_lib->vba.ReturnBandwidthToDCN = dml_min(
>+			mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLK,
>+			mode_lib->vba.FabricAndDRAMBandwidth * 1000);
>+	mode_lib->vba.ReturnBW = adjust_ReturnBW(
>+			mode_lib,
>+			mode_lib->vba.ReturnBW,
>+			mode_lib->vba.DCCEnabledAnyPlane,
>+			mode_lib->vba.ReturnBandwidthToDCN);
>+
>+	DTRACE("   dcfclk_mhz         = %f", mode_lib->vba.DCFCLK);
>+	DTRACE("   return_bw_to_dcn   = %f", mode_lib->vba.ReturnBandwidthToDCN);
>+	DTRACE("   return_bus_bw      = %f", mode_lib->vba.ReturnBW);
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		bool MainPlaneDoesODMCombine = false;
>+
>+		if (mode_lib->vba.SourceScan[k] == dm_horz)
>+			mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k];
>+		else
>+			mode_lib->vba.SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k];
>+
>+		if (mode_lib->vba.ODMCombineEnabled[k] == true)
>+			MainPlaneDoesODMCombine = true;
>+		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j)
>+			if (mode_lib->vba.BlendingAndTiming[k] == j
>+					&& mode_lib->vba.ODMCombineEnabled[j] == true)
>+				MainPlaneDoesODMCombine = true;
>+
>+		if (MainPlaneDoesODMCombine == true)
>+			mode_lib->vba.SwathWidthY[k] = dml_min(
>+					(double) mode_lib->vba.SwathWidthSingleDPPY[k],
>+					dml_round(
>+							mode_lib->vba.HActive[k] / 2.0
>+									* mode_lib->vba.HRatio[k]));
>+		else {
>+			if (mode_lib->vba.DPPPerPlane[k] == 0) {
>+				mode_lib->vba.SwathWidthY[k] = 0;
>+			} else {
>+				mode_lib->vba.SwathWidthY[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
>+						/ mode_lib->vba.DPPPerPlane[k];
>+			}
>+		}
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
>+			mode_lib->vba.BytePerPixelDETY[k] = 8;
>+			mode_lib->vba.BytePerPixelDETC[k] = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
>+			mode_lib->vba.BytePerPixelDETY[k] = 4;
>+			mode_lib->vba.BytePerPixelDETC[k] = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
>+			mode_lib->vba.BytePerPixelDETY[k] = 2;
>+			mode_lib->vba.BytePerPixelDETC[k] = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
>+			mode_lib->vba.BytePerPixelDETY[k] = 1;
>+			mode_lib->vba.BytePerPixelDETC[k] = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
>+			mode_lib->vba.BytePerPixelDETY[k] = 1;
>+			mode_lib->vba.BytePerPixelDETC[k] = 2;
>+		} else { // dm_420_10
>+			mode_lib->vba.BytePerPixelDETY[k] = 4.0 / 3.0;
>+			mode_lib->vba.BytePerPixelDETC[k] = 8.0 / 3.0;
>+		}
>+	}
>+
>+	mode_lib->vba.TotalDataReadBandwidth = 0.0;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.ReadBandwidthPlaneLuma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
>+				* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1)
>+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
>+				* mode_lib->vba.VRatio[k];
>+		mode_lib->vba.ReadBandwidthPlaneChroma[k] = mode_lib->vba.SwathWidthSingleDPPY[k]
>+				/ 2 * dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2)
>+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
>+				* mode_lib->vba.VRatio[k] / 2;
>+		DTRACE(
>+				"   read_bw[%i] = %fBps",
>+				k,
>+				mode_lib->vba.ReadBandwidthPlaneLuma[k]
>+						+ mode_lib->vba.ReadBandwidthPlaneChroma[k]);
>+		mode_lib->vba.TotalDataReadBandwidth += mode_lib->vba.ReadBandwidthPlaneLuma[k]
>+				+ mode_lib->vba.ReadBandwidthPlaneChroma[k];
>+	}
>+
>+	mode_lib->vba.TotalDCCActiveDPP = 0;
>+	mode_lib->vba.TotalActiveDPP = 0;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP
>+				+ mode_lib->vba.DPPPerPlane[k];
>+		if (mode_lib->vba.DCCEnable[k])
>+			mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP
>+					+ mode_lib->vba.DPPPerPlane[k];
>+	}
>+
>+	mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency =
>+			(mode_lib->vba.RoundTripPingLatencyCycles + 32) / mode_lib->vba.DCFCLK
>+					+ mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly
>+							* mode_lib->vba.NumberOfChannels
>+							/ mode_lib->vba.ReturnBW;
>+
>+	mode_lib->vba.LastPixelOfLineExtraWatermark = 0;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+			if (mode_lib->vba.VRatio[k] <= 1.0)
>+				mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
>+						(double) mode_lib->vba.SwathWidthY[k]
>+								* mode_lib->vba.DPPPerPlane[k]
>+								/ mode_lib->vba.HRatio[k]
>+								/ mode_lib->vba.PixelClock[k];
>+			else
>+				mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k] =
>+						(double) mode_lib->vba.SwathWidthY[k]
>+								/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
>+								/ mode_lib->vba.DPPCLK[k];
>+
>+			if (mode_lib->vba.BytePerPixelDETC[k] == 0)
>+				mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] = 0.0;
>+			else if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0)
>+				mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
>+						mode_lib->vba.SwathWidthY[k] / 2.0
>+								* mode_lib->vba.DPPPerPlane[k]
>+								/ (mode_lib->vba.HRatio[k] / 2.0)
>+								/ mode_lib->vba.PixelClock[k];
>+			else
>+				mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k] =
>+						mode_lib->vba.SwathWidthY[k] / 2.0
>+								/ mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
>+								/ mode_lib->vba.DPPCLK[k];
>+		}
>+
>+	mode_lib->vba.UrgentExtraLatency = mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency
>+			+ (mode_lib->vba.TotalActiveDPP * mode_lib->vba.PixelChunkSizeInKByte
>+					+ mode_lib->vba.TotalDCCActiveDPP
>+							* mode_lib->vba.MetaChunkSize) * 1024.0
>+					/ mode_lib->vba.ReturnBW;
>+
>+	if (mode_lib->vba.GPUVMEnable)
>+		mode_lib->vba.UrgentExtraLatency += mode_lib->vba.TotalActiveDPP
>+				* mode_lib->vba.PTEGroupSize / mode_lib->vba.ReturnBW;
>+
>+	mode_lib->vba.UrgentWatermark = mode_lib->vba.UrgentLatencyPixelDataOnly
>+			+ mode_lib->vba.LastPixelOfLineExtraWatermark
>+			+ mode_lib->vba.UrgentExtraLatency;
>+
>+	DTRACE("   urgent_extra_latency = %fus", mode_lib->vba.UrgentExtraLatency);
>+	DTRACE("   wm_urgent = %fus", mode_lib->vba.UrgentWatermark);
>+
>+	mode_lib->vba.UrgentLatency = mode_lib->vba.UrgentLatencyPixelDataOnly;
>+
>+	mode_lib->vba.TotalActiveWriteback = 0;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.WritebackEnable[k])
>+			mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + mode_lib->vba.ActiveWritebacksPerPlane[k];
>+	}
>+
>+	if (mode_lib->vba.TotalActiveWriteback <= 1)
>+		mode_lib->vba.WritebackUrgentWatermark = mode_lib->vba.WritebackLatency;
>+	else
>+		mode_lib->vba.WritebackUrgentWatermark = mode_lib->vba.WritebackLatency
>+				+ mode_lib->vba.WritebackChunkSize * 1024.0 / 32
>+						/ mode_lib->vba.SOCCLK;
>+
>+	DTRACE("   wm_wb_urgent = %fus", mode_lib->vba.WritebackUrgentWatermark);
>+
>+	// NB P-State/DRAM Clock Change Watermark
>+	mode_lib->vba.DRAMClockChangeWatermark = mode_lib->vba.DRAMClockChangeLatency
>+			+ mode_lib->vba.UrgentWatermark;
>+
>+	DTRACE("   wm_pstate_change = %fus", mode_lib->vba.DRAMClockChangeWatermark);
>+
>+	DTRACE("   calculating wb pstate watermark");
>+	DTRACE("      total wb outputs %d", mode_lib->vba.TotalActiveWriteback);
>+	DTRACE("      socclk frequency %f Mhz", mode_lib->vba.SOCCLK);
>+
>+	if (mode_lib->vba.TotalActiveWriteback <= 1)
>+		mode_lib->vba.WritebackDRAMClockChangeWatermark =
>+				mode_lib->vba.DRAMClockChangeLatency
>+						+ mode_lib->vba.WritebackLatency;
>+	else
>+		mode_lib->vba.WritebackDRAMClockChangeWatermark =
>+				mode_lib->vba.DRAMClockChangeLatency
>+						+ mode_lib->vba.WritebackLatency
>+						+ mode_lib->vba.WritebackChunkSize * 1024.0 / 32
>+								/ mode_lib->vba.SOCCLK;
>+
>+	DTRACE("   wm_wb_pstate %fus", mode_lib->vba.WritebackDRAMClockChangeWatermark);
>+
>+	// Stutter Efficiency
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.LinesInDETY[k] = mode_lib->vba.DETBufferSizeY[k]
>+				/ mode_lib->vba.BytePerPixelDETY[k] / mode_lib->vba.SwathWidthY[k];
>+		mode_lib->vba.LinesInDETYRoundedDownToSwath[k] = dml_floor(
>+				mode_lib->vba.LinesInDETY[k],
>+				mode_lib->vba.SwathHeightY[k]);
>+		mode_lib->vba.FullDETBufferingTimeY[k] =
>+				mode_lib->vba.LinesInDETYRoundedDownToSwath[k]
>+						* (mode_lib->vba.HTotal[k]
>+								/ mode_lib->vba.PixelClock[k])
>+						/ mode_lib->vba.VRatio[k];
>+		if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
>+			mode_lib->vba.LinesInDETC[k] = mode_lib->vba.DETBufferSizeC[k]
>+					/ mode_lib->vba.BytePerPixelDETC[k]
>+					/ (mode_lib->vba.SwathWidthY[k] / 2);
>+			mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = dml_floor(
>+					mode_lib->vba.LinesInDETC[k],
>+					mode_lib->vba.SwathHeightC[k]);
>+			mode_lib->vba.FullDETBufferingTimeC[k] =
>+					mode_lib->vba.LinesInDETCRoundedDownToSwath[k]
>+							* (mode_lib->vba.HTotal[k]
>+									/ mode_lib->vba.PixelClock[k])
>+							/ (mode_lib->vba.VRatio[k] / 2);
>+		} else {
>+			mode_lib->vba.LinesInDETC[k] = 0;
>+			mode_lib->vba.LinesInDETCRoundedDownToSwath[k] = 0;
>+			mode_lib->vba.FullDETBufferingTimeC[k] = 999999;
>+		}
>+	}
>+
>+	mode_lib->vba.MinFullDETBufferingTime = 999999.0;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.FullDETBufferingTimeY[k]
>+				< mode_lib->vba.MinFullDETBufferingTime) {
>+			mode_lib->vba.MinFullDETBufferingTime =
>+					mode_lib->vba.FullDETBufferingTimeY[k];
>+			mode_lib->vba.FrameTimeForMinFullDETBufferingTime =
>+					(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
>+							/ mode_lib->vba.PixelClock[k];
>+		}
>+		if (mode_lib->vba.FullDETBufferingTimeC[k]
>+				< mode_lib->vba.MinFullDETBufferingTime) {
>+			mode_lib->vba.MinFullDETBufferingTime =
>+					mode_lib->vba.FullDETBufferingTimeC[k];
>+			mode_lib->vba.FrameTimeForMinFullDETBufferingTime =
>+					(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
>+							/ mode_lib->vba.PixelClock[k];
>+		}
>+	}
>+
>+	mode_lib->vba.AverageReadBandwidthGBytePerSecond = 0.0;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.DCCEnable[k]) {
>+			mode_lib->vba.AverageReadBandwidthGBytePerSecond =
>+					mode_lib->vba.AverageReadBandwidthGBytePerSecond
>+							+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
>+									/ mode_lib->vba.DCCRate[k]
>+									/ 1000
>+							+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
>+									/ mode_lib->vba.DCCRate[k]
>+									/ 1000;
>+		} else {
>+			mode_lib->vba.AverageReadBandwidthGBytePerSecond =
>+					mode_lib->vba.AverageReadBandwidthGBytePerSecond
>+							+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
>+									/ 1000
>+							+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
>+									/ 1000;
>+		}
>+		if (mode_lib->vba.DCCEnable[k]) {
>+			mode_lib->vba.AverageReadBandwidthGBytePerSecond =
>+					mode_lib->vba.AverageReadBandwidthGBytePerSecond
>+							+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
>+									/ 1000 / 256
>+							+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
>+									/ 1000 / 256;
>+		}
>+		if (mode_lib->vba.GPUVMEnable) {
>+			mode_lib->vba.AverageReadBandwidthGBytePerSecond =
>+					mode_lib->vba.AverageReadBandwidthGBytePerSecond
>+							+ mode_lib->vba.ReadBandwidthPlaneLuma[k]
>+									/ 1000 / 512
>+							+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
>+									/ 1000 / 512;
>+		}
>+	}
>+
>+	mode_lib->vba.PartOfBurstThatFitsInROB =
>+			dml_min(
>+					mode_lib->vba.MinFullDETBufferingTime
>+							* mode_lib->vba.TotalDataReadBandwidth,
>+					mode_lib->vba.ROBBufferSizeInKByte * 1024
>+							* mode_lib->vba.TotalDataReadBandwidth
>+							/ (mode_lib->vba.AverageReadBandwidthGBytePerSecond
>+									* 1000));
>+	mode_lib->vba.StutterBurstTime = mode_lib->vba.PartOfBurstThatFitsInROB
>+			* (mode_lib->vba.AverageReadBandwidthGBytePerSecond * 1000)
>+			/ mode_lib->vba.TotalDataReadBandwidth / mode_lib->vba.ReturnBW
>+			+ (mode_lib->vba.MinFullDETBufferingTime
>+					* mode_lib->vba.TotalDataReadBandwidth
>+					- mode_lib->vba.PartOfBurstThatFitsInROB)
>+					/ (mode_lib->vba.DCFCLK * 64);
>+	if (mode_lib->vba.TotalActiveWriteback == 0) {
>+		mode_lib->vba.StutterEfficiencyNotIncludingVBlank = (1
>+				- (mode_lib->vba.SRExitTime + mode_lib->vba.StutterBurstTime)
>+						/ mode_lib->vba.MinFullDETBufferingTime) * 100;
>+	} else {
>+		mode_lib->vba.StutterEfficiencyNotIncludingVBlank = 0;
>+	}
>+
>+	mode_lib->vba.SmallestVBlank = 999999;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
>+			mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k]
>+					- mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k]
>+					/ mode_lib->vba.PixelClock[k];
>+		} else {
>+			mode_lib->vba.VBlankTime = 0;
>+		}
>+		mode_lib->vba.SmallestVBlank = dml_min(
>+				mode_lib->vba.SmallestVBlank,
>+				mode_lib->vba.VBlankTime);
>+	}
>+
>+	mode_lib->vba.StutterEfficiency = (mode_lib->vba.StutterEfficiencyNotIncludingVBlank / 100
>+			* (mode_lib->vba.FrameTimeForMinFullDETBufferingTime
>+					- mode_lib->vba.SmallestVBlank)
>+			+ mode_lib->vba.SmallestVBlank)
>+			/ mode_lib->vba.FrameTimeForMinFullDETBufferingTime * 100;
>+
>+	// dml_ml->vba.DCFCLK Deep Sleep
>+	mode_lib->vba.DCFCLKDeepSleep = 8.0;
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; k++) {
>+		if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
>+			mode_lib->vba.DCFCLKDeepSleepPerPlane[k] =
>+					dml_max(
>+							1.1 * mode_lib->vba.SwathWidthY[k]
>+									* dml_ceil(
>+											mode_lib->vba.BytePerPixelDETY[k],
>+											1) / 32
>+									/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k],
>+							1.1 * mode_lib->vba.SwathWidthY[k] / 2.0
>+									* dml_ceil(
>+											mode_lib->vba.BytePerPixelDETC[k],
>+											2) / 32
>+									/ mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k]);
>+		} else
>+			mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * mode_lib->vba.SwathWidthY[k]
>+					* dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1) / 64.0
>+					/ mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k];
>+		mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
>+				mode_lib->vba.DCFCLKDeepSleepPerPlane[k],
>+				mode_lib->vba.PixelClock[k] / 16.0);
>+		mode_lib->vba.DCFCLKDeepSleep = dml_max(
>+				mode_lib->vba.DCFCLKDeepSleep,
>+				mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
>+
>+		DTRACE(
>+				"   dcfclk_deepsleep_per_plane[%i] = %fMHz",
>+				k,
>+				mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
>+	}
>+
>+	DTRACE("   dcfclk_deepsleep_mhz = %fMHz", mode_lib->vba.DCFCLKDeepSleep);
>+
>+	// Stutter Watermark
>+	mode_lib->vba.StutterExitWatermark = mode_lib->vba.SRExitTime
>+			+ mode_lib->vba.LastPixelOfLineExtraWatermark
>+			+ mode_lib->vba.UrgentExtraLatency + 10 / mode_lib->vba.DCFCLKDeepSleep;
>+	mode_lib->vba.StutterEnterPlusExitWatermark = mode_lib->vba.SREnterPlusExitTime
>+			+ mode_lib->vba.LastPixelOfLineExtraWatermark
>+			+ mode_lib->vba.UrgentExtraLatency;
>+
>+	DTRACE("   wm_cstate_exit       = %fus", mode_lib->vba.StutterExitWatermark);
>+	DTRACE("   wm_cstate_enter_exit = %fus", mode_lib->vba.StutterEnterPlusExitWatermark);
>+
>+	// Urgent Latency Supported
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.EffectiveDETPlusLBLinesLuma =
>+				dml_floor(
>+						mode_lib->vba.LinesInDETY[k]
>+								+ dml_min(
>+										mode_lib->vba.LinesInDETY[k]
>+												* mode_lib->vba.DPPCLK[k]
>+												* mode_lib->vba.BytePerPixelDETY[k]
>+												* mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
>+												/ (mode_lib->vba.ReturnBW
>+														/ mode_lib->vba.DPPPerPlane[k]),
>+										(double) mode_lib->vba.EffectiveLBLatencyHidingSourceLinesLuma),
>+						mode_lib->vba.SwathHeightY[k]);
>+
>+		mode_lib->vba.UrgentLatencySupportUsLuma = mode_lib->vba.EffectiveDETPlusLBLinesLuma
>+				* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
>+				/ mode_lib->vba.VRatio[k]
>+				- mode_lib->vba.EffectiveDETPlusLBLinesLuma
>+						* mode_lib->vba.SwathWidthY[k]
>+						* mode_lib->vba.BytePerPixelDETY[k]
>+						/ (mode_lib->vba.ReturnBW
>+								/ mode_lib->vba.DPPPerPlane[k]);
>+
>+		if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
>+			mode_lib->vba.EffectiveDETPlusLBLinesChroma =
>+					dml_floor(
>+							mode_lib->vba.LinesInDETC[k]
>+									+ dml_min(
>+											mode_lib->vba.LinesInDETC[k]
>+													* mode_lib->vba.DPPCLK[k]
>+													* mode_lib->vba.BytePerPixelDETC[k]
>+													* mode_lib->vba.PSCL_THROUGHPUT_CHROMA[k]
>+													/ (mode_lib->vba.ReturnBW
>+															/ mode_lib->vba.DPPPerPlane[k]),
>+											(double) mode_lib->vba.EffectiveLBLatencyHidingSourceLinesChroma),
>+							mode_lib->vba.SwathHeightC[k]);
>+			mode_lib->vba.UrgentLatencySupportUsChroma =
>+					mode_lib->vba.EffectiveDETPlusLBLinesChroma
>+							* (mode_lib->vba.HTotal[k]
>+									/ mode_lib->vba.PixelClock[k])
>+							/ (mode_lib->vba.VRatio[k] / 2)
>+							- mode_lib->vba.EffectiveDETPlusLBLinesChroma
>+									* (mode_lib->vba.SwathWidthY[k]
>+											/ 2)
>+									* mode_lib->vba.BytePerPixelDETC[k]
>+									/ (mode_lib->vba.ReturnBW
>+											/ mode_lib->vba.DPPPerPlane[k]);
>+			mode_lib->vba.UrgentLatencySupportUs[k] = dml_min(
>+					mode_lib->vba.UrgentLatencySupportUsLuma,
>+					mode_lib->vba.UrgentLatencySupportUsChroma);
>+		} else {
>+			mode_lib->vba.UrgentLatencySupportUs[k] =
>+					mode_lib->vba.UrgentLatencySupportUsLuma;
>+		}
>+	}
>+
>+	mode_lib->vba.MinUrgentLatencySupportUs = 999999;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.MinUrgentLatencySupportUs = dml_min(
>+				mode_lib->vba.MinUrgentLatencySupportUs,
>+				mode_lib->vba.UrgentLatencySupportUs[k]);
>+	}
>+
>+	// Non-Urgent Latency Tolerance
>+	mode_lib->vba.NonUrgentLatencyTolerance = mode_lib->vba.MinUrgentLatencySupportUs
>+			- mode_lib->vba.UrgentWatermark;
>+
>+	// DSCCLK
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
>+			mode_lib->vba.DSCCLK_calculated[k] = 0.0;
>+		} else {
>+			if (mode_lib->vba.OutputFormat[k] == dm_420
>+					|| mode_lib->vba.OutputFormat[k] == dm_n422)
>+				mode_lib->vba.DSCFormatFactor = 2;
>+			else
>+				mode_lib->vba.DSCFormatFactor = 1;
>+			if (mode_lib->vba.ODMCombineEnabled[k])
>+				mode_lib->vba.DSCCLK_calculated[k] =
>+						mode_lib->vba.PixelClockBackEnd[k] / 6
>+								/ mode_lib->vba.DSCFormatFactor
>+								/ (1
>+										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+												/ 100);
>+			else
>+				mode_lib->vba.DSCCLK_calculated[k] =
>+						mode_lib->vba.PixelClockBackEnd[k] / 3
>+								/ mode_lib->vba.DSCFormatFactor
>+								/ (1
>+										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+												/ 100);
>+		}
>+	}
>+
>+	// DSC Delay
>+	// TODO
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		double bpp = mode_lib->vba.OutputBpp[k];
>+		unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k];
>+
>+		if (mode_lib->vba.DSCEnabled[k] && bpp != 0) {
>+			if (!mode_lib->vba.ODMCombineEnabled[k]) {
>+				mode_lib->vba.DSCDelay[k] =
>+						dscceComputeDelay(
>+								mode_lib->vba.DSCInputBitPerComponent[k],
>+								bpp,
>+								dml_ceil(
>+										(double) mode_lib->vba.HActive[k]
>+												/ mode_lib->vba.NumberOfDSCSlices[k],
>+										1),
>+								slices,
>+								mode_lib->vba.OutputFormat[k])
>+								+ dscComputeDelay(
>+										mode_lib->vba.OutputFormat[k]);
>+			} else {
>+				mode_lib->vba.DSCDelay[k] =
>+						2
>+								* (dscceComputeDelay(
>+										mode_lib->vba.DSCInputBitPerComponent[k],
>+										bpp,
>+										dml_ceil(
>+												(double) mode_lib->vba.HActive[k]
>+														/ mode_lib->vba.NumberOfDSCSlices[k],
>+												1),
>+										slices / 2.0,
>+										mode_lib->vba.OutputFormat[k])
>+										+ dscComputeDelay(
>+												mode_lib->vba.OutputFormat[k]));
>+			}
>+			mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[k]
>+					* mode_lib->vba.PixelClock[k]
>+					/ mode_lib->vba.PixelClockBackEnd[k];
>+		} else {
>+			mode_lib->vba.DSCDelay[k] = 0;
>+		}
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
>+		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) // NumberOfPlanes
>+			if (j != k && mode_lib->vba.BlendingAndTiming[k] == j
>+					&& mode_lib->vba.DSCEnabled[j])
>+				mode_lib->vba.DSCDelay[k] = mode_lib->vba.DSCDelay[j];
>+
>+	// Prefetch
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		unsigned int PDEAndMetaPTEBytesFrameY;
>+		unsigned int PixelPTEBytesPerRowY;
>+		unsigned int MetaRowByteY;
>+		unsigned int MetaRowByteC;
>+		unsigned int PDEAndMetaPTEBytesFrameC;
>+		unsigned int PixelPTEBytesPerRowC;
>+
>+		Calculate256BBlockSizes(
>+				mode_lib->vba.SourcePixelFormat[k],
>+				mode_lib->vba.SurfaceTiling[k],
>+				dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
>+				dml_ceil(mode_lib->vba.BytePerPixelDETC[k], 2),
>+				&mode_lib->vba.BlockHeight256BytesY[k],
>+				&mode_lib->vba.BlockHeight256BytesC[k],
>+				&mode_lib->vba.BlockWidth256BytesY[k],
>+				&mode_lib->vba.BlockWidth256BytesC[k]);
>+		PDEAndMetaPTEBytesFrameY = CalculateVMAndRowBytes(
>+				mode_lib,
>+				mode_lib->vba.DCCEnable[k],
>+				mode_lib->vba.BlockHeight256BytesY[k],
>+				mode_lib->vba.BlockWidth256BytesY[k],
>+				mode_lib->vba.SourcePixelFormat[k],
>+				mode_lib->vba.SurfaceTiling[k],
>+				dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
>+				mode_lib->vba.SourceScan[k],
>+				mode_lib->vba.ViewportWidth[k],
>+				mode_lib->vba.ViewportHeight[k],
>+				mode_lib->vba.SwathWidthY[k],
>+				mode_lib->vba.GPUVMEnable,
>+				mode_lib->vba.VMMPageSize,
>+				mode_lib->vba.PTEBufferSizeInRequestsLuma,
>+				mode_lib->vba.PDEProcessingBufIn64KBReqs,
>+				mode_lib->vba.PitchY[k],
>+				mode_lib->vba.DCCMetaPitchY[k],
>+				&mode_lib->vba.MacroTileWidthY[k],
>+				&MetaRowByteY,
>+				&PixelPTEBytesPerRowY,
>+				&mode_lib->vba.PTEBufferSizeNotExceeded[mode_lib->vba.VoltageLevel][0],
>+				&mode_lib->vba.dpte_row_height[k],
>+				&mode_lib->vba.meta_row_height[k]);
>+		mode_lib->vba.PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
>+				mode_lib,
>+				mode_lib->vba.VRatio[k],
>+				mode_lib->vba.vtaps[k],
>+				mode_lib->vba.Interlace[k],
>+				mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+				mode_lib->vba.SwathHeightY[k],
>+				mode_lib->vba.ViewportYStartY[k],
>+				&mode_lib->vba.VInitPreFillY[k],
>+				&mode_lib->vba.MaxNumSwathY[k]);
>+
>+		if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) {
>+			PDEAndMetaPTEBytesFrameC =
>+					CalculateVMAndRowBytes(
>+							mode_lib,
>+							mode_lib->vba.DCCEnable[k],
>+							mode_lib->vba.BlockHeight256BytesC[k],
>+							mode_lib->vba.BlockWidth256BytesC[k],
>+							mode_lib->vba.SourcePixelFormat[k],
>+							mode_lib->vba.SurfaceTiling[k],
>+							dml_ceil(
>+									mode_lib->vba.BytePerPixelDETC[k],
>+									2),
>+							mode_lib->vba.SourceScan[k],
>+							mode_lib->vba.ViewportWidth[k] / 2,
>+							mode_lib->vba.ViewportHeight[k] / 2,
>+							mode_lib->vba.SwathWidthY[k] / 2,
>+							mode_lib->vba.GPUVMEnable,
>+							mode_lib->vba.VMMPageSize,
>+							mode_lib->vba.PTEBufferSizeInRequestsLuma,
>+							mode_lib->vba.PDEProcessingBufIn64KBReqs,
>+							mode_lib->vba.PitchC[k],
>+							0,
>+							&mode_lib->vba.MacroTileWidthC[k],
>+							&MetaRowByteC,
>+							&PixelPTEBytesPerRowC,
>+							&mode_lib->vba.PTEBufferSizeNotExceeded[mode_lib->vba.VoltageLevel][0],
>+							&mode_lib->vba.dpte_row_height_chroma[k],
>+							&mode_lib->vba.meta_row_height_chroma[k]);
>+			mode_lib->vba.PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
>+					mode_lib,
>+					mode_lib->vba.VRatio[k] / 2,
>+					mode_lib->vba.VTAPsChroma[k],
>+					mode_lib->vba.Interlace[k],
>+					mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+					mode_lib->vba.SwathHeightC[k],
>+					mode_lib->vba.ViewportYStartC[k],
>+					&mode_lib->vba.VInitPreFillC[k],
>+					&mode_lib->vba.MaxNumSwathC[k]);
>+		} else {
>+			PixelPTEBytesPerRowC = 0;
>+			PDEAndMetaPTEBytesFrameC = 0;
>+			MetaRowByteC = 0;
>+			mode_lib->vba.MaxNumSwathC[k] = 0;
>+			mode_lib->vba.PrefetchSourceLinesC[k] = 0;
>+		}
>+
>+		mode_lib->vba.PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
>+		mode_lib->vba.PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
>+				+ PDEAndMetaPTEBytesFrameC;
>+		mode_lib->vba.MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
>+
>+		CalculateActiveRowBandwidth(
>+				mode_lib->vba.GPUVMEnable,
>+				mode_lib->vba.SourcePixelFormat[k],
>+				mode_lib->vba.VRatio[k],
>+				mode_lib->vba.DCCEnable[k],
>+				mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
>+				MetaRowByteY,
>+				MetaRowByteC,
>+				mode_lib->vba.meta_row_height[k],
>+				mode_lib->vba.meta_row_height_chroma[k],
>+				PixelPTEBytesPerRowY,
>+				PixelPTEBytesPerRowC,
>+				mode_lib->vba.dpte_row_height[k],
>+				mode_lib->vba.dpte_row_height_chroma[k],
>+				&mode_lib->vba.meta_row_bw[k],
>+				&mode_lib->vba.dpte_row_bw[k],
>+				&mode_lib->vba.qual_row_bw[k]);
>+	}
>+
>+	mode_lib->vba.TCalc = 24.0 / mode_lib->vba.DCFCLKDeepSleep;
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+			if (mode_lib->vba.WritebackEnable[k] == true) {
>+				mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
>+						mode_lib->vba.WritebackLatency
>+								+ CalculateWriteBackDelay(
>+										mode_lib->vba.WritebackPixelFormat[k],
>+										mode_lib->vba.WritebackHRatio[k],
>+										mode_lib->vba.WritebackVRatio[k],
>+										mode_lib->vba.WritebackLumaHTaps[k],
>+										mode_lib->vba.WritebackLumaVTaps[k],
>+										mode_lib->vba.WritebackChromaHTaps[k],
>+										mode_lib->vba.WritebackChromaVTaps[k],
>+										mode_lib->vba.WritebackDestinationWidth[k])
>+										/ mode_lib->vba.DISPCLK;
>+			} else
>+				mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
>+			for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {
>+				if (mode_lib->vba.BlendingAndTiming[j] == k
>+						&& mode_lib->vba.WritebackEnable[j] == true) {
>+					mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
>+							dml_max(
>+									mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k],
>+									mode_lib->vba.WritebackLatency
>+											+ CalculateWriteBackDelay(
>+													mode_lib->vba.WritebackPixelFormat[j],
>+													mode_lib->vba.WritebackHRatio[j],
>+													mode_lib->vba.WritebackVRatio[j],
>+													mode_lib->vba.WritebackLumaHTaps[j],
>+													mode_lib->vba.WritebackLumaVTaps[j],
>+													mode_lib->vba.WritebackChromaHTaps[j],
>+													mode_lib->vba.WritebackChromaVTaps[j],
>+													mode_lib->vba.WritebackDestinationWidth[j])
>+													/ mode_lib->vba.DISPCLK);
>+				}
>+			}
>+		}
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
>+		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j)
>+			if (mode_lib->vba.BlendingAndTiming[k] == j)
>+				mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k] =
>+						mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][j];
>+
>+	mode_lib->vba.VStartupLines = 13;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.MaxVStartupLines[k] =
>+				mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
>+						- dml_max(
>+								1.0,
>+								dml_ceil(
>+										mode_lib->vba.WritebackDelay[mode_lib->vba.VoltageLevel][k]
>+												/ (mode_lib->vba.HTotal[k]
>+														/ mode_lib->vba.PixelClock[k]),
>+										1));
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
>+		mode_lib->vba.MaximumMaxVStartupLines = dml_max(
>+				mode_lib->vba.MaximumMaxVStartupLines,
>+				mode_lib->vba.MaxVStartupLines[k]);
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.cursor_bw[k] = 0.0;
>+		for (j = 0; j < mode_lib->vba.NumberOfCursors[k]; ++j)
>+			mode_lib->vba.cursor_bw[k] += mode_lib->vba.CursorWidth[k][j]
>+					* mode_lib->vba.CursorBPP[k][j] / 8.0
>+					/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
>+					* mode_lib->vba.VRatio[k];
>+	}
>+
>+	do {
>+		double MaxTotalRDBandwidth = 0;
>+		bool DestinationLineTimesForPrefetchLessThan2 = false;
>+		bool VRatioPrefetchMoreThan4 = false;
>+		bool prefetch_vm_bw_valid = true;
>+		bool prefetch_row_bw_valid = true;
>+		double TWait = CalculateTWait(
>+				mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
>+				mode_lib->vba.DRAMClockChangeLatency,
>+				mode_lib->vba.UrgentLatencyPixelDataOnly,
>+				mode_lib->vba.SREnterPlusExitTime);
>+
>+		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+			if (mode_lib->vba.XFCEnabled[k] == true) {
>+				mode_lib->vba.XFCRemoteSurfaceFlipDelay =
>+						CalculateRemoteSurfaceFlipDelay(
>+								mode_lib,
>+								mode_lib->vba.VRatio[k],
>+								mode_lib->vba.SwathWidthY[k],
>+								dml_ceil(
>+										mode_lib->vba.BytePerPixelDETY[k],
>+										1),
>+								mode_lib->vba.HTotal[k]
>+										/ mode_lib->vba.PixelClock[k],
>+								mode_lib->vba.XFCTSlvVupdateOffset,
>+								mode_lib->vba.XFCTSlvVupdateWidth,
>+								mode_lib->vba.XFCTSlvVreadyOffset,
>+								mode_lib->vba.XFCXBUFLatencyTolerance,
>+								mode_lib->vba.XFCFillBWOverhead,
>+								mode_lib->vba.XFCSlvChunkSize,
>+								mode_lib->vba.XFCBusTransportTime,
>+								mode_lib->vba.TCalc,
>+								TWait,
>+								&mode_lib->vba.SrcActiveDrainRate,
>+								&mode_lib->vba.TInitXFill,
>+								&mode_lib->vba.TslvChk);
>+			} else {
>+				mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0;
>+			}
>+
>+			CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBW, mode_lib->vba.ReadBandwidthPlaneLuma[k], mode_lib->vba.ReadBandwidthPlaneChroma[k], mode_lib->vba.TotalDataReadBandwidth,
>+					mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k],
>+					mode_lib->vba.DPPCLK[k], mode_lib->vba.DISPCLK, mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelay[k], mode_lib->vba.DPPPerPlane[k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k],
>+					mode_lib->vba.DPPCLKDelaySubtotal, mode_lib->vba.DPPCLKDelaySCL, mode_lib->vba.DPPCLKDelaySCLLBOnly, mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal,
>+					mode_lib->vba.SwathWidthY[k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k],
>+					mode_lib->vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPixelDETC[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], mode_lib->vba.Interlace[k],
>+					mode_lib->vba.ProgressiveToInterlaceUnitInOPP, &mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]);
>+
>+			mode_lib->vba.ErrorResult[k] =
>+					CalculatePrefetchSchedule(
>+							mode_lib,
>+							mode_lib->vba.DPPCLK[k],
>+							mode_lib->vba.DISPCLK,
>+							mode_lib->vba.PixelClock[k],
>+							mode_lib->vba.DCFCLKDeepSleep,
>+							mode_lib->vba.DPPPerPlane[k],
>+							mode_lib->vba.NumberOfCursors[k],
>+							mode_lib->vba.VTotal[k]
>+									- mode_lib->vba.VActive[k],
>+							mode_lib->vba.HTotal[k],
>+							mode_lib->vba.MaxInterDCNTileRepeaters,
>+							dml_min(
>+									mode_lib->vba.VStartupLines,
>+									mode_lib->vba.MaxVStartupLines[k]),
>+							mode_lib->vba.GPUVMMaxPageTableLevels,
>+							mode_lib->vba.GPUVMEnable,
>+							mode_lib->vba.DynamicMetadataEnable[k],
>+							mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
>+							mode_lib->vba.DynamicMetadataTransmittedBytes[k],
>+							mode_lib->vba.DCCEnable[k],
>+							mode_lib->vba.UrgentLatencyPixelDataOnly,
>+							mode_lib->vba.UrgentExtraLatency,
>+							mode_lib->vba.TCalc,
>+							mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
>+							mode_lib->vba.MetaRowByte[k],
>+							mode_lib->vba.PixelPTEBytesPerRow[k],
>+							mode_lib->vba.PrefetchSourceLinesY[k],
>+							mode_lib->vba.SwathWidthY[k],
>+							mode_lib->vba.BytePerPixelDETY[k],
>+							mode_lib->vba.VInitPreFillY[k],
>+							mode_lib->vba.MaxNumSwathY[k],
>+							mode_lib->vba.PrefetchSourceLinesC[k],
>+							mode_lib->vba.BytePerPixelDETC[k],
>+							mode_lib->vba.VInitPreFillC[k],
>+							mode_lib->vba.MaxNumSwathC[k],
>+							mode_lib->vba.SwathHeightY[k],
>+							mode_lib->vba.SwathHeightC[k],
>+							TWait,
>+							mode_lib->vba.XFCEnabled[k],
>+							mode_lib->vba.XFCRemoteSurfaceFlipDelay,
>+							mode_lib->vba.Interlace[k],
>+							mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+							mode_lib->vba.DSTXAfterScaler[k],
>+							mode_lib->vba.DSTYAfterScaler[k],
>+							&mode_lib->vba.DestinationLinesForPrefetch[k],
>+							&mode_lib->vba.PrefetchBandwidth[k],
>+							&mode_lib->vba.DestinationLinesToRequestVMInVBlank[k],
>+							&mode_lib->vba.DestinationLinesToRequestRowInVBlank[k],
>+							&mode_lib->vba.VRatioPrefetchY[k],
>+							&mode_lib->vba.VRatioPrefetchC[k],
>+							&mode_lib->vba.RequiredPrefetchPixDataBWLuma[k],
>+							&mode_lib->vba.Tno_bw[k],
>+							&mode_lib->vba.VUpdateOffsetPix[k],
>+							&mode_lib->vba.VUpdateWidthPix[k],
>+							&mode_lib->vba.VReadyOffsetPix[k]);
>+
>+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+				mode_lib->vba.VStartup[k] = dml_min(
>+						mode_lib->vba.VStartupLines,
>+						mode_lib->vba.MaxVStartupLines[k]);
>+				if (mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata
>+						!= 0) {
>+					mode_lib->vba.VStartup[k] =
>+							mode_lib->vba.VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
>+				}
>+			} else {
>+				mode_lib->vba.VStartup[k] =
>+						dml_min(
>+								mode_lib->vba.VStartupLines,
>+								mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]);
>+			}
>+		}
>+
>+		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+
>+			if (mode_lib->vba.PDEAndMetaPTEBytesFrame[k] == 0)
>+				mode_lib->vba.prefetch_vm_bw[k] = 0;
>+			else if (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k] > 0) {
>+				mode_lib->vba.prefetch_vm_bw[k] =
>+						(double) mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
>+								/ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
>+										* mode_lib->vba.HTotal[k]
>+										/ mode_lib->vba.PixelClock[k]);
>+			} else {
>+				mode_lib->vba.prefetch_vm_bw[k] = 0;
>+				prefetch_vm_bw_valid = false;
>+			}
>+			if (mode_lib->vba.MetaRowByte[k] + mode_lib->vba.PixelPTEBytesPerRow[k]
>+					== 0)
>+				mode_lib->vba.prefetch_row_bw[k] = 0;
>+			else if (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k] > 0) {
>+				mode_lib->vba.prefetch_row_bw[k] =
>+						(double) (mode_lib->vba.MetaRowByte[k]
>+								+ mode_lib->vba.PixelPTEBytesPerRow[k])
>+								/ (mode_lib->vba.DestinationLinesToRequestRowInVBlank[k]
>+										* mode_lib->vba.HTotal[k]
>+										/ mode_lib->vba.PixelClock[k]);
>+			} else {
>+				mode_lib->vba.prefetch_row_bw[k] = 0;
>+				prefetch_row_bw_valid = false;
>+			}
>+
>+			MaxTotalRDBandwidth =
>+					MaxTotalRDBandwidth + mode_lib->vba.cursor_bw[k]
>+							+ dml_max(
>+									mode_lib->vba.prefetch_vm_bw[k],
>+									dml_max(
>+											mode_lib->vba.prefetch_row_bw[k],
>+											dml_max(
>+													mode_lib->vba.ReadBandwidthPlaneLuma[k]
>+															+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
>+													mode_lib->vba.RequiredPrefetchPixDataBWLuma[k])
>+													+ mode_lib->vba.meta_row_bw[k]
>+													+ mode_lib->vba.dpte_row_bw[k]));
>+
>+			if (mode_lib->vba.DestinationLinesForPrefetch[k] < 2)
>+				DestinationLineTimesForPrefetchLessThan2 = true;
>+			if (mode_lib->vba.VRatioPrefetchY[k] > 4
>+					|| mode_lib->vba.VRatioPrefetchC[k] > 4)
>+				VRatioPrefetchMoreThan4 = true;
>+		}
>+
>+		if (MaxTotalRDBandwidth <= mode_lib->vba.ReturnBW && prefetch_vm_bw_valid
>+				&& prefetch_row_bw_valid && !VRatioPrefetchMoreThan4
>+				&& !DestinationLineTimesForPrefetchLessThan2)
>+			mode_lib->vba.PrefetchModeSupported = true;
>+		else {
>+			mode_lib->vba.PrefetchModeSupported = false;
>+			dml_print(
>+					"DML: CalculatePrefetchSchedule ***failed***. Bandwidth violation. Results are NOT valid\n");
>+		}
>+
>+		if (mode_lib->vba.PrefetchModeSupported == true) {
>+			double final_flip_bw[DC__NUM_DPP__MAX];
>+			unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
>+			double total_dcn_read_bw_with_flip = 0;
>+
>+			mode_lib->vba.BandwidthAvailableForImmediateFlip = mode_lib->vba.ReturnBW;
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				mode_lib->vba.BandwidthAvailableForImmediateFlip =
>+						mode_lib->vba.BandwidthAvailableForImmediateFlip
>+								- mode_lib->vba.cursor_bw[k]
>+								- dml_max(
>+										mode_lib->vba.ReadBandwidthPlaneLuma[k]
>+												+ mode_lib->vba.ReadBandwidthPlaneChroma[k]
>+												+ mode_lib->vba.qual_row_bw[k],
>+										mode_lib->vba.PrefetchBandwidth[k]);
>+			}
>+
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				ImmediateFlipBytes[k] = 0;
>+				if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
>+					ImmediateFlipBytes[k] =
>+							mode_lib->vba.PDEAndMetaPTEBytesFrame[k]
>+									+ mode_lib->vba.MetaRowByte[k]
>+									+ mode_lib->vba.PixelPTEBytesPerRow[k];
>+				}
>+			}
>+			mode_lib->vba.TotImmediateFlipBytes = 0;
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
>+					mode_lib->vba.TotImmediateFlipBytes =
>+							mode_lib->vba.TotImmediateFlipBytes
>+									+ ImmediateFlipBytes[k];
>+				}
>+			}
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				CalculateFlipSchedule(
>+						mode_lib,
>+						mode_lib->vba.UrgentExtraLatency,
>+						mode_lib->vba.UrgentLatencyPixelDataOnly,
>+						mode_lib->vba.GPUVMMaxPageTableLevels,
>+						mode_lib->vba.GPUVMEnable,
>+						mode_lib->vba.BandwidthAvailableForImmediateFlip,
>+						mode_lib->vba.TotImmediateFlipBytes,
>+						mode_lib->vba.SourcePixelFormat[k],
>+						ImmediateFlipBytes[k],
>+						mode_lib->vba.HTotal[k]
>+								/ mode_lib->vba.PixelClock[k],
>+						mode_lib->vba.VRatio[k],
>+						mode_lib->vba.Tno_bw[k],
>+						mode_lib->vba.PDEAndMetaPTEBytesFrame[k],
>+						mode_lib->vba.MetaRowByte[k],
>+						mode_lib->vba.PixelPTEBytesPerRow[k],
>+						mode_lib->vba.DCCEnable[k],
>+						mode_lib->vba.dpte_row_height[k],
>+						mode_lib->vba.meta_row_height[k],
>+						mode_lib->vba.qual_row_bw[k],
>+						&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
>+						&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
>+						&final_flip_bw[k],
>+						&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
>+			}
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				total_dcn_read_bw_with_flip =
>+						total_dcn_read_bw_with_flip
>+								+ mode_lib->vba.cursor_bw[k]
>+								+ dml_max(
>+										mode_lib->vba.prefetch_vm_bw[k],
>+										dml_max(
>+												mode_lib->vba.prefetch_row_bw[k],
>+												final_flip_bw[k]
>+														+ dml_max(
>+																mode_lib->vba.ReadBandwidthPlaneLuma[k]
>+																		+ mode_lib->vba.ReadBandwidthPlaneChroma[k],
>+																mode_lib->vba.RequiredPrefetchPixDataBWLuma[k])));
>+			}
>+			mode_lib->vba.ImmediateFlipSupported = true;
>+			if (total_dcn_read_bw_with_flip > mode_lib->vba.ReturnBW) {
>+				mode_lib->vba.ImmediateFlipSupported = false;
>+			}
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
>+					mode_lib->vba.ImmediateFlipSupported = false;
>+				}
>+			}
>+		} else {
>+			mode_lib->vba.ImmediateFlipSupported = false;
>+		}
>+
>+		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+			if (mode_lib->vba.ErrorResult[k]) {
>+				mode_lib->vba.PrefetchModeSupported = false;
>+				dml_print(
>+						"DML: CalculatePrefetchSchedule ***failed***. Prefetch schedule violation. Results are NOT valid\n");
>+			}
>+		}
>+
>+		mode_lib->vba.VStartupLines = mode_lib->vba.VStartupLines + 1;
>+	} while (!((mode_lib->vba.PrefetchModeSupported
>+			&& (!mode_lib->vba.ImmediateFlipSupport
>+					|| mode_lib->vba.ImmediateFlipSupported))
>+			|| mode_lib->vba.MaximumMaxVStartupLines < mode_lib->vba.VStartupLines));
>+
>+	//Display Pipeline Delivery Time in Prefetch
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.VRatioPrefetchY[k] <= 1) {
>+			mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
>+					mode_lib->vba.SwathWidthY[k] * mode_lib->vba.DPPPerPlane[k]
>+							/ mode_lib->vba.HRatio[k]
>+							/ mode_lib->vba.PixelClock[k];
>+		} else {
>+			mode_lib->vba.DisplayPipeLineDeliveryTimeLumaPrefetch[k] =
>+					mode_lib->vba.SwathWidthY[k]
>+							/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
>+							/ mode_lib->vba.DPPCLK[k];
>+		}
>+		if (mode_lib->vba.BytePerPixelDETC[k] == 0) {
>+			mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
>+		} else {
>+			if (mode_lib->vba.VRatioPrefetchC[k] <= 1) {
>+				mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
>+						mode_lib->vba.SwathWidthY[k]
>+								* mode_lib->vba.DPPPerPlane[k]
>+								/ mode_lib->vba.HRatio[k]
>+								/ mode_lib->vba.PixelClock[k];
>+			} else {
>+				mode_lib->vba.DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
>+						mode_lib->vba.SwathWidthY[k]
>+								/ mode_lib->vba.PSCL_THROUGHPUT_LUMA[k]
>+								/ mode_lib->vba.DPPCLK[k];
>+			}
>+		}
>+	}
>+
>+	// Min TTUVBlank
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
>+			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true;
>+			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
>+			mode_lib->vba.MinTTUVBlank[k] = dml_max(
>+					mode_lib->vba.DRAMClockChangeWatermark,
>+					dml_max(
>+							mode_lib->vba.StutterEnterPlusExitWatermark,
>+							mode_lib->vba.UrgentWatermark));
>+		} else if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 1) {
>+			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
>+			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
>+			mode_lib->vba.MinTTUVBlank[k] = dml_max(
>+					mode_lib->vba.StutterEnterPlusExitWatermark,
>+					mode_lib->vba.UrgentWatermark);
>+		} else {
>+			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
>+			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false;
>+			mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
>+		}
>+		if (!mode_lib->vba.DynamicMetadataEnable[k])
>+			mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.TCalc
>+					+ mode_lib->vba.MinTTUVBlank[k];
>+	}
>+
>+	// DCC Configuration
>+	mode_lib->vba.ActiveDPPs = 0;
>+	// NB P-State/DRAM Clock Change Support
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.ActiveDPPs = mode_lib->vba.ActiveDPPs + mode_lib->vba.DPPPerPlane[k];
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		double EffectiveLBLatencyHidingY;
>+		double EffectiveLBLatencyHidingC;
>+		double DPPOutputBufferLinesY;
>+		double DPPOutputBufferLinesC;
>+		double DPPOPPBufferingY;
>+		double MaxDETBufferingTimeY;
>+		double ActiveDRAMClockChangeLatencyMarginY;
>+
>+		mode_lib->vba.LBLatencyHidingSourceLinesY =
>+				dml_min(
>+						mode_lib->vba.MaxLineBufferLines,
>+						(unsigned int) dml_floor(
>+								(double) mode_lib->vba.LineBufferSize
>+										/ mode_lib->vba.LBBitPerPixel[k]
>+										/ (mode_lib->vba.SwathWidthY[k]
>+												/ dml_max(
>+														mode_lib->vba.HRatio[k],
>+														1.0)),
>+								1)) - (mode_lib->vba.vtaps[k] - 1);
>+
>+		mode_lib->vba.LBLatencyHidingSourceLinesC =
>+				dml_min(
>+						mode_lib->vba.MaxLineBufferLines,
>+						(unsigned int) dml_floor(
>+								(double) mode_lib->vba.LineBufferSize
>+										/ mode_lib->vba.LBBitPerPixel[k]
>+										/ (mode_lib->vba.SwathWidthY[k]
>+												/ 2.0
>+												/ dml_max(
>+														mode_lib->vba.HRatio[k]
>+																/ 2,
>+														1.0)),
>+								1))
>+						- (mode_lib->vba.VTAPsChroma[k] - 1);
>+
>+		EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY
>+				/ mode_lib->vba.VRatio[k]
>+				* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
>+
>+		EffectiveLBLatencyHidingC = mode_lib->vba.LBLatencyHidingSourceLinesC
>+				/ (mode_lib->vba.VRatio[k] / 2)
>+				* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]);
>+
>+		if (mode_lib->vba.SwathWidthY[k] > 2 * mode_lib->vba.DPPOutputBufferPixels) {
>+			DPPOutputBufferLinesY = mode_lib->vba.DPPOutputBufferPixels
>+					/ mode_lib->vba.SwathWidthY[k];
>+		} else if (mode_lib->vba.SwathWidthY[k] > mode_lib->vba.DPPOutputBufferPixels) {
>+			DPPOutputBufferLinesY = 0.5;
>+		} else {
>+			DPPOutputBufferLinesY = 1;
>+		}
>+
>+		if (mode_lib->vba.SwathWidthY[k] / 2 > 2 * mode_lib->vba.DPPOutputBufferPixels) {
>+			DPPOutputBufferLinesC = mode_lib->vba.DPPOutputBufferPixels
>+					/ (mode_lib->vba.SwathWidthY[k] / 2);
>+		} else if (mode_lib->vba.SwathWidthY[k] / 2 > mode_lib->vba.DPPOutputBufferPixels) {
>+			DPPOutputBufferLinesC = 0.5;
>+		} else {
>+			DPPOutputBufferLinesC = 1;
>+		}
>+
>+		DPPOPPBufferingY = (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
>+				* (DPPOutputBufferLinesY + mode_lib->vba.OPPOutputBufferLines);
>+		MaxDETBufferingTimeY = mode_lib->vba.FullDETBufferingTimeY[k]
>+				+ (mode_lib->vba.LinesInDETY[k]
>+						- mode_lib->vba.LinesInDETYRoundedDownToSwath[k])
>+						/ mode_lib->vba.SwathHeightY[k]
>+						* (mode_lib->vba.HTotal[k]
>+								/ mode_lib->vba.PixelClock[k]);
>+
>+		ActiveDRAMClockChangeLatencyMarginY = DPPOPPBufferingY + EffectiveLBLatencyHidingY
>+				+ MaxDETBufferingTimeY - mode_lib->vba.DRAMClockChangeWatermark;
>+
>+		if (mode_lib->vba.ActiveDPPs > 1) {
>+			ActiveDRAMClockChangeLatencyMarginY =
>+					ActiveDRAMClockChangeLatencyMarginY
>+							- (1 - 1 / (mode_lib->vba.ActiveDPPs - 1))
>+									* mode_lib->vba.SwathHeightY[k]
>+									* (mode_lib->vba.HTotal[k]
>+											/ mode_lib->vba.PixelClock[k]);
>+		}
>+
>+		if (mode_lib->vba.BytePerPixelDETC[k] > 0) {
>+			double DPPOPPBufferingC = (mode_lib->vba.HTotal[k]
>+					/ mode_lib->vba.PixelClock[k])
>+					* (DPPOutputBufferLinesC
>+							+ mode_lib->vba.OPPOutputBufferLines);
>+			double MaxDETBufferingTimeC =
>+					mode_lib->vba.FullDETBufferingTimeC[k]
>+							+ (mode_lib->vba.LinesInDETC[k]
>+									- mode_lib->vba.LinesInDETCRoundedDownToSwath[k])
>+									/ mode_lib->vba.SwathHeightC[k]
>+									* (mode_lib->vba.HTotal[k]
>+											/ mode_lib->vba.PixelClock[k]);
>+			double ActiveDRAMClockChangeLatencyMarginC = DPPOPPBufferingC
>+					+ EffectiveLBLatencyHidingC + MaxDETBufferingTimeC
>+					- mode_lib->vba.DRAMClockChangeWatermark;
>+
>+			if (mode_lib->vba.ActiveDPPs > 1) {
>+				ActiveDRAMClockChangeLatencyMarginC =
>+						ActiveDRAMClockChangeLatencyMarginC
>+								- (1
>+										- 1
>+												/ (mode_lib->vba.ActiveDPPs
>+														- 1))
>+										* mode_lib->vba.SwathHeightC[k]
>+										* (mode_lib->vba.HTotal[k]
>+												/ mode_lib->vba.PixelClock[k]);
>+			}
>+			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
>+					ActiveDRAMClockChangeLatencyMarginY,
>+					ActiveDRAMClockChangeLatencyMarginC);
>+		} else {
>+			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] =
>+					ActiveDRAMClockChangeLatencyMarginY;
>+		}
>+
>+		if (mode_lib->vba.WritebackEnable[k]) {
>+			double WritebackDRAMClockChangeLatencyMargin;
>+
>+			if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
>+				WritebackDRAMClockChangeLatencyMargin =
>+						(double) (mode_lib->vba.WritebackInterfaceLumaBufferSize
>+								+ mode_lib->vba.WritebackInterfaceChromaBufferSize)
>+								/ (mode_lib->vba.WritebackDestinationWidth[k]
>+										* mode_lib->vba.WritebackDestinationHeight[k]
>+										/ (mode_lib->vba.WritebackSourceHeight[k]
>+												* mode_lib->vba.HTotal[k]
>+												/ mode_lib->vba.PixelClock[k])
>+										* 4)
>+								- mode_lib->vba.WritebackDRAMClockChangeWatermark;
>+			} else if (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
>+				WritebackDRAMClockChangeLatencyMargin =
>+						dml_min(
>+								(double) mode_lib->vba.WritebackInterfaceLumaBufferSize
>+										* 8.0 / 10,
>+								2.0
>+										* mode_lib->vba.WritebackInterfaceChromaBufferSize
>+										* 8 / 10)
>+								/ (mode_lib->vba.WritebackDestinationWidth[k]
>+										* mode_lib->vba.WritebackDestinationHeight[k]
>+										/ (mode_lib->vba.WritebackSourceHeight[k]
>+												* mode_lib->vba.HTotal[k]
>+												/ mode_lib->vba.PixelClock[k]))
>+								- mode_lib->vba.WritebackDRAMClockChangeWatermark;
>+			} else {
>+				WritebackDRAMClockChangeLatencyMargin =
>+						dml_min(
>+								(double) mode_lib->vba.WritebackInterfaceLumaBufferSize,
>+								2.0
>+										* mode_lib->vba.WritebackInterfaceChromaBufferSize)
>+								/ (mode_lib->vba.WritebackDestinationWidth[k]
>+										* mode_lib->vba.WritebackDestinationHeight[k]
>+										/ (mode_lib->vba.WritebackSourceHeight[k]
>+												* mode_lib->vba.HTotal[k]
>+												/ mode_lib->vba.PixelClock[k]))
>+								- mode_lib->vba.WritebackDRAMClockChangeWatermark;
>+			}
>+			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
>+					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k],
>+					WritebackDRAMClockChangeLatencyMargin);
>+		}
>+	}
>+
>+	mode_lib->vba.MinActiveDRAMClockChangeMargin = 999999;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
>+				< mode_lib->vba.MinActiveDRAMClockChangeMargin) {
>+			mode_lib->vba.MinActiveDRAMClockChangeMargin =
>+					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
>+		}
>+	}
>+
>+	mode_lib->vba.MinActiveDRAMClockChangeLatencySupported =
>+			mode_lib->vba.MinActiveDRAMClockChangeMargin
>+					+ mode_lib->vba.DRAMClockChangeLatency;
>+
>+	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
>+		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;
>+	} else {
>+		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
>+			mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vblank;
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				if (!mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k]) {
>+					mode_lib->vba.DRAMClockChangeSupport[0][0] =
>+							dm_dram_clock_change_unsupported;
>+				}
>+			}
>+		} else {
>+			mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_unsupported;
>+		}
>+	}
>+	for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
>+		for (j = 0; j < 2; j++)
>+			mode_lib->vba.DRAMClockChangeSupport[k][j] = mode_lib->vba.DRAMClockChangeSupport[0][0];
>+
>+	//XFC Parameters:
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.XFCEnabled[k] == true) {
>+			double TWait;
>+
>+			mode_lib->vba.XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
>+			mode_lib->vba.XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
>+			mode_lib->vba.XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
>+			TWait = CalculateTWait(
>+					mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
>+					mode_lib->vba.DRAMClockChangeLatency,
>+					mode_lib->vba.UrgentLatencyPixelDataOnly,
>+					mode_lib->vba.SREnterPlusExitTime);
>+			mode_lib->vba.XFCRemoteSurfaceFlipDelay = CalculateRemoteSurfaceFlipDelay(
>+					mode_lib,
>+					mode_lib->vba.VRatio[k],
>+					mode_lib->vba.SwathWidthY[k],
>+					dml_ceil(mode_lib->vba.BytePerPixelDETY[k], 1),
>+					mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
>+					mode_lib->vba.XFCTSlvVupdateOffset,
>+					mode_lib->vba.XFCTSlvVupdateWidth,
>+					mode_lib->vba.XFCTSlvVreadyOffset,
>+					mode_lib->vba.XFCXBUFLatencyTolerance,
>+					mode_lib->vba.XFCFillBWOverhead,
>+					mode_lib->vba.XFCSlvChunkSize,
>+					mode_lib->vba.XFCBusTransportTime,
>+					mode_lib->vba.TCalc,
>+					TWait,
>+					&mode_lib->vba.SrcActiveDrainRate,
>+					&mode_lib->vba.TInitXFill,
>+					&mode_lib->vba.TslvChk);
>+			mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =
>+					dml_floor(
>+							mode_lib->vba.XFCRemoteSurfaceFlipDelay
>+									/ (mode_lib->vba.HTotal[k]
>+											/ mode_lib->vba.PixelClock[k]),
>+							1);
>+			mode_lib->vba.XFCTransferDelay[k] =
>+					dml_ceil(
>+							mode_lib->vba.XFCBusTransportTime
>+									/ (mode_lib->vba.HTotal[k]
>+											/ mode_lib->vba.PixelClock[k]),
>+							1);
>+			mode_lib->vba.XFCPrechargeDelay[k] =
>+					dml_ceil(
>+							(mode_lib->vba.XFCBusTransportTime
>+									+ mode_lib->vba.TInitXFill
>+									+ mode_lib->vba.TslvChk)
>+									/ (mode_lib->vba.HTotal[k]
>+											/ mode_lib->vba.PixelClock[k]),
>+							1);
>+			mode_lib->vba.InitFillLevel = mode_lib->vba.XFCXBUFLatencyTolerance
>+					* mode_lib->vba.SrcActiveDrainRate;
>+			mode_lib->vba.FinalFillMargin =
>+					(mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
>+							+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
>+							* mode_lib->vba.HTotal[k]
>+							/ mode_lib->vba.PixelClock[k]
>+							* mode_lib->vba.SrcActiveDrainRate
>+							+ mode_lib->vba.XFCFillConstant;
>+			mode_lib->vba.FinalFillLevel = mode_lib->vba.XFCRemoteSurfaceFlipDelay
>+					* mode_lib->vba.SrcActiveDrainRate
>+					+ mode_lib->vba.FinalFillMargin;
>+			mode_lib->vba.RemainingFillLevel = dml_max(
>+					0.0,
>+					mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel);
>+			mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel
>+					/ (mode_lib->vba.SrcActiveDrainRate
>+							* mode_lib->vba.XFCFillBWOverhead / 100);
>+			mode_lib->vba.XFCPrefetchMargin[k] =
>+					mode_lib->vba.XFCRemoteSurfaceFlipDelay
>+							+ mode_lib->vba.TFinalxFill
>+							+ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
>+									+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
>+									* mode_lib->vba.HTotal[k]
>+									/ mode_lib->vba.PixelClock[k];
>+		} else {
>+			mode_lib->vba.XFCSlaveVUpdateOffset[k] = 0;
>+			mode_lib->vba.XFCSlaveVupdateWidth[k] = 0;
>+			mode_lib->vba.XFCSlaveVReadyOffset[k] = 0;
>+			mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = 0;
>+			mode_lib->vba.XFCPrechargeDelay[k] = 0;
>+			mode_lib->vba.XFCTransferDelay[k] = 0;
>+			mode_lib->vba.XFCPrefetchMargin[k] = 0;
>+		}
>+	}
>+	{
>+		unsigned int VStartupMargin = 0;
>+		bool FirstMainPlane = true;
>+
>+		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+				unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k])
>+						* mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k];
>+
>+				if (FirstMainPlane) {
>+					VStartupMargin = Margin;
>+					FirstMainPlane = false;
>+				} else
>+					VStartupMargin = dml_min(VStartupMargin, Margin);
>+		}
>+
>+		if (mode_lib->vba.UseMaximumVStartup) {
>+			if (mode_lib->vba.VTotal_Max[k] == mode_lib->vba.VTotal[k]) {
>+				//only use max vstart if it is not drr or lateflip.
>+				mode_lib->vba.VStartup[k] = mode_lib->vba.MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]];
>+			}
>+		}
>+	}
>+}
>+}
>+
>+static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
>+{
>+	double BytePerPixDETY;
>+	double BytePerPixDETC;
>+	double Read256BytesBlockHeightY;
>+	double Read256BytesBlockHeightC;
>+	double Read256BytesBlockWidthY;
>+	double Read256BytesBlockWidthC;
>+	double MaximumSwathHeightY;
>+	double MaximumSwathHeightC;
>+	double MinimumSwathHeightY;
>+	double MinimumSwathHeightC;
>+	double SwathWidth;
>+	double SwathWidthGranularityY;
>+	double SwathWidthGranularityC;
>+	double RoundedUpMaxSwathSizeBytesY;
>+	double RoundedUpMaxSwathSizeBytesC;
>+	unsigned int j, k;
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		bool MainPlaneDoesODMCombine = false;
>+
>+		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
>+			BytePerPixDETY = 8;
>+			BytePerPixDETC = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
>+			BytePerPixDETY = 4;
>+			BytePerPixDETC = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
>+			BytePerPixDETY = 2;
>+			BytePerPixDETC = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
>+			BytePerPixDETY = 1;
>+			BytePerPixDETC = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
>+			BytePerPixDETY = 1;
>+			BytePerPixDETC = 2;
>+		} else {
>+			BytePerPixDETY = 4.0 / 3.0;
>+			BytePerPixDETC = 8.0 / 3.0;
>+		}
>+
>+		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
>+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
>+				Read256BytesBlockHeightY = 1;
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
>+				Read256BytesBlockHeightY = 4;
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32
>+					|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
>+				Read256BytesBlockHeightY = 8;
>+			} else {
>+				Read256BytesBlockHeightY = 16;
>+			}
>+			Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1)
>+					/ Read256BytesBlockHeightY;
>+			Read256BytesBlockHeightC = 0;
>+			Read256BytesBlockWidthC = 0;
>+		} else {
>+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
>+				Read256BytesBlockHeightY = 1;
>+				Read256BytesBlockHeightC = 1;
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
>+				Read256BytesBlockHeightY = 16;
>+				Read256BytesBlockHeightC = 8;
>+			} else {
>+				Read256BytesBlockHeightY = 8;
>+				Read256BytesBlockHeightC = 8;
>+			}
>+			Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1)
>+					/ Read256BytesBlockHeightY;
>+			Read256BytesBlockWidthC = 256 / dml_ceil(BytePerPixDETC, 2)
>+					/ Read256BytesBlockHeightC;
>+		}
>+
>+		if (mode_lib->vba.SourceScan[k] == dm_horz) {
>+			MaximumSwathHeightY = Read256BytesBlockHeightY;
>+			MaximumSwathHeightC = Read256BytesBlockHeightC;
>+		} else {
>+			MaximumSwathHeightY = Read256BytesBlockWidthY;
>+			MaximumSwathHeightC = Read256BytesBlockWidthC;
>+		}
>+
>+		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
>+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>+					|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
>+							&& (mode_lib->vba.SurfaceTiling[k]
>+									== dm_sw_4kb_s
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_4kb_s_x
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_64kb_s
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_64kb_s_t
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_64kb_s_x
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_var_s
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_var_s_x)
>+							&& mode_lib->vba.SourceScan[k] == dm_horz)) {
>+				MinimumSwathHeightY = MaximumSwathHeightY;
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8
>+					&& mode_lib->vba.SourceScan[k] != dm_horz) {
>+				MinimumSwathHeightY = MaximumSwathHeightY;
>+			} else {
>+				MinimumSwathHeightY = MaximumSwathHeightY / 2.0;
>+			}
>+			MinimumSwathHeightC = MaximumSwathHeightC;
>+		} else {
>+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
>+				MinimumSwathHeightY = MaximumSwathHeightY;
>+				MinimumSwathHeightC = MaximumSwathHeightC;
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
>+					&& mode_lib->vba.SourceScan[k] == dm_horz) {
>+				MinimumSwathHeightY = MaximumSwathHeightY / 2.0;
>+				MinimumSwathHeightC = MaximumSwathHeightC;
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
>+					&& mode_lib->vba.SourceScan[k] == dm_horz) {
>+				MinimumSwathHeightC = MaximumSwathHeightC / 2.0;
>+				MinimumSwathHeightY = MaximumSwathHeightY;
>+			} else {
>+				MinimumSwathHeightY = MaximumSwathHeightY;
>+				MinimumSwathHeightC = MaximumSwathHeightC;
>+			}
>+		}
>+
>+		if (mode_lib->vba.SourceScan[k] == dm_horz) {
>+			SwathWidth = mode_lib->vba.ViewportWidth[k];
>+		} else {
>+			SwathWidth = mode_lib->vba.ViewportHeight[k];
>+		}
>+
>+		if (mode_lib->vba.ODMCombineEnabled[k] == true) {
>+			MainPlaneDoesODMCombine = true;
>+		}
>+		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {
>+			if (mode_lib->vba.BlendingAndTiming[k] == j
>+					&& mode_lib->vba.ODMCombineEnabled[j] == true) {
>+				MainPlaneDoesODMCombine = true;
>+			}
>+		}
>+
>+		if (MainPlaneDoesODMCombine == true) {
>+			SwathWidth = dml_min(
>+					SwathWidth,
>+					mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]);
>+		} else {
>+			if (mode_lib->vba.DPPPerPlane[k] == 0)
>+				SwathWidth = 0;
>+			else
>+				SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k];
>+		}
>+
>+		SwathWidthGranularityY = 256 / dml_ceil(BytePerPixDETY, 1) / MaximumSwathHeightY;
>+		RoundedUpMaxSwathSizeBytesY = (dml_ceil(
>+				(double) (SwathWidth - 1),
>+				SwathWidthGranularityY) + SwathWidthGranularityY) * BytePerPixDETY
>+				* MaximumSwathHeightY;
>+		if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
>+			RoundedUpMaxSwathSizeBytesY = dml_ceil(RoundedUpMaxSwathSizeBytesY, 256)
>+					+ 256;
>+		}
>+		if (MaximumSwathHeightC > 0) {
>+			SwathWidthGranularityC = 256.0 / dml_ceil(BytePerPixDETC, 2)
>+					/ MaximumSwathHeightC;
>+			RoundedUpMaxSwathSizeBytesC = (dml_ceil(
>+					(double) (SwathWidth / 2.0 - 1),
>+					SwathWidthGranularityC) + SwathWidthGranularityC)
>+					* BytePerPixDETC * MaximumSwathHeightC;
>+			if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
>+				RoundedUpMaxSwathSizeBytesC = dml_ceil(
>+						RoundedUpMaxSwathSizeBytesC,
>+						256) + 256;
>+			}
>+		} else
>+			RoundedUpMaxSwathSizeBytesC = 0.0;
>+
>+		if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC
>+				<= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) {
>+			mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
>+			mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
>+		} else {
>+			mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY;
>+			mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC;
>+		}
>+
>+		if (mode_lib->vba.SwathHeightC[k] == 0) {
>+			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte * 1024;
>+			mode_lib->vba.DETBufferSizeC[k] = 0;
>+		} else if (mode_lib->vba.SwathHeightY[k] <= mode_lib->vba.SwathHeightC[k]) {
>+			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte
>+					* 1024.0 / 2;
>+			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte
>+					* 1024.0 / 2;
>+		} else {
>+			mode_lib->vba.DETBufferSizeY[k] = mode_lib->vba.DETBufferSizeInKByte
>+					* 1024.0 * 2 / 3;
>+			mode_lib->vba.DETBufferSizeC[k] = mode_lib->vba.DETBufferSizeInKByte
>+					* 1024.0 / 3;
>+		}
>+	}
>+}
>+
>+static double CalculateTWait(
>+		unsigned int PrefetchMode,
>+		double DRAMClockChangeLatency,
>+		double UrgentLatencyPixelDataOnly,
>+		double SREnterPlusExitTime)
>+{
>+	if (PrefetchMode == 0) {
>+		return dml_max(
>+				DRAMClockChangeLatency + UrgentLatencyPixelDataOnly,
>+				dml_max(SREnterPlusExitTime, UrgentLatencyPixelDataOnly));
>+	} else if (PrefetchMode == 1) {
>+		return dml_max(SREnterPlusExitTime, UrgentLatencyPixelDataOnly);
>+	} else {
>+		return UrgentLatencyPixelDataOnly;
>+	}
>+}
>+
>+static double CalculateRemoteSurfaceFlipDelay(
>+		struct display_mode_lib *mode_lib,
>+		double VRatio,
>+		double SwathWidth,
>+		double Bpp,
>+		double LineTime,
>+		double XFCTSlvVupdateOffset,
>+		double XFCTSlvVupdateWidth,
>+		double XFCTSlvVreadyOffset,
>+		double XFCXBUFLatencyTolerance,
>+		double XFCFillBWOverhead,
>+		double XFCSlvChunkSize,
>+		double XFCBusTransportTime,
>+		double TCalc,
>+		double TWait,
>+		double *SrcActiveDrainRate,
>+		double *TInitXFill,
>+		double *TslvChk)
>+{
>+	double TSlvSetup, AvgfillRate, result;
>+
>+	*SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime;
>+	TSlvSetup = XFCTSlvVupdateOffset + XFCTSlvVupdateWidth + XFCTSlvVreadyOffset;
>+	*TInitXFill = XFCXBUFLatencyTolerance / (1 + XFCFillBWOverhead / 100);
>+	AvgfillRate = *SrcActiveDrainRate * (1 + XFCFillBWOverhead / 100);
>+	*TslvChk = XFCSlvChunkSize / AvgfillRate;
>+	dml_print(
>+			"DML::CalculateRemoteSurfaceFlipDelay: SrcActiveDrainRate: %f\n",
>+			*SrcActiveDrainRate);
>+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TSlvSetup: %f\n", TSlvSetup);
>+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TInitXFill: %f\n", *TInitXFill);
>+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: AvgfillRate: %f\n", AvgfillRate);
>+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TslvChk: %f\n", *TslvChk);
>+	result = 2 * XFCBusTransportTime + TSlvSetup + TCalc + TWait + *TslvChk + *TInitXFill; // TODO: This doesn't seem to match programming guide
>+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: RemoteSurfaceFlipDelay: %f\n", result);
>+	return result;
>+}
>+
>+static double CalculateWriteBackDelay(
>+		enum source_format_class WritebackPixelFormat,
>+		double WritebackHRatio,
>+		double WritebackVRatio,
>+		unsigned int WritebackLumaHTaps,
>+		unsigned int WritebackLumaVTaps,
>+		unsigned int WritebackChromaHTaps,
>+		unsigned int WritebackChromaVTaps,
>+		unsigned int WritebackDestinationWidth)
>+{
>+	double CalculateWriteBackDelay =
>+			dml_max(
>+					dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio,
>+					WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1)
>+							* dml_ceil(
>+									WritebackDestinationWidth
>+											/ 4.0,
>+									1)
>+							+ dml_ceil(1.0 / WritebackVRatio, 1)
>+									* (dml_ceil(
>+											WritebackLumaVTaps
>+													/ 4.0,
>+											1) + 4));
>+
>+	if (WritebackPixelFormat != dm_444_32) {
>+		CalculateWriteBackDelay =
>+				dml_max(
>+						CalculateWriteBackDelay,
>+						dml_max(
>+								dml_ceil(
>+										WritebackChromaHTaps
>+												/ 2.0,
>+										1)
>+										/ (2
>+												* WritebackHRatio),
>+								WritebackChromaVTaps
>+										* dml_ceil(
>+												1
>+														/ (2
>+																* WritebackVRatio),
>+												1)
>+										* dml_ceil(
>+												WritebackDestinationWidth
>+														/ 2.0
>+														/ 2.0,
>+												1)
>+										+ dml_ceil(
>+												1
>+														/ (2
>+																* WritebackVRatio),
>+												1)
>+												* (dml_ceil(
>+														WritebackChromaVTaps
>+																/ 4.0,
>+														1)
>+														+ 4)));
>+	}
>+	return CalculateWriteBackDelay;
>+}
>+
>+static void CalculateActiveRowBandwidth(
>+		bool GPUVMEnable,
>+		enum source_format_class SourcePixelFormat,
>+		double VRatio,
>+		bool DCCEnable,
>+		double LineTime,
>+		unsigned int MetaRowByteLuma,
>+		unsigned int MetaRowByteChroma,
>+		unsigned int meta_row_height_luma,
>+		unsigned int meta_row_height_chroma,
>+		unsigned int PixelPTEBytesPerRowLuma,
>+		unsigned int PixelPTEBytesPerRowChroma,
>+		unsigned int dpte_row_height_luma,
>+		unsigned int dpte_row_height_chroma,
>+		double *meta_row_bw,
>+		double *dpte_row_bw,
>+		double *qual_row_bw)
>+{
>+	if (DCCEnable != true) {
>+		*meta_row_bw = 0;
>+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
>+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime)
>+				+ VRatio / 2 * MetaRowByteChroma
>+						/ (meta_row_height_chroma * LineTime);
>+	} else {
>+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime);
>+	}
>+
>+	if (GPUVMEnable != true) {
>+		*dpte_row_bw = 0;
>+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
>+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime)
>+				+ VRatio / 2 * PixelPTEBytesPerRowChroma
>+						/ (dpte_row_height_chroma * LineTime);
>+	} else {
>+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime);
>+	}
>+
>+	if ((SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10)) {
>+		*qual_row_bw = *meta_row_bw + *dpte_row_bw;
>+	} else {
>+		*qual_row_bw = 0;
>+	}
>+}
>+
>+static void CalculateFlipSchedule(
>+		struct display_mode_lib *mode_lib,
>+		double UrgentExtraLatency,
>+		double UrgentLatencyPixelDataOnly,
>+		unsigned int GPUVMMaxPageTableLevels,
>+		bool GPUVMEnable,
>+		double BandwidthAvailableForImmediateFlip,
>+		unsigned int TotImmediateFlipBytes,
>+		enum source_format_class SourcePixelFormat,
>+		unsigned int ImmediateFlipBytes,
>+		double LineTime,
>+		double VRatio,
>+		double Tno_bw,
>+		double PDEAndMetaPTEBytesFrame,
>+		unsigned int MetaRowByte,
>+		unsigned int PixelPTEBytesPerRow,
>+		bool DCCEnable,
>+		unsigned int dpte_row_height,
>+		unsigned int meta_row_height,
>+		double qual_row_bw,
>+		double *DestinationLinesToRequestVMInImmediateFlip,
>+		double *DestinationLinesToRequestRowInImmediateFlip,
>+		double *final_flip_bw,
>+		bool *ImmediateFlipSupportedForPipe)
>+{
>+	double min_row_time = 0.0;
>+
>+	if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
>+		*DestinationLinesToRequestVMInImmediateFlip = 0.0;
>+		*DestinationLinesToRequestRowInImmediateFlip = 0.0;
>+		*final_flip_bw = qual_row_bw;
>+		*ImmediateFlipSupportedForPipe = true;
>+	} else {
>+		double TimeForFetchingMetaPTEImmediateFlip;
>+		double TimeForFetchingRowInVBlankImmediateFlip;
>+
>+		if (GPUVMEnable == true) {
>+			mode_lib->vba.ImmediateFlipBW[0] = BandwidthAvailableForImmediateFlip
>+					* ImmediateFlipBytes / TotImmediateFlipBytes;
>+			TimeForFetchingMetaPTEImmediateFlip =
>+					dml_max(
>+							Tno_bw
>+									+ PDEAndMetaPTEBytesFrame
>+											/ mode_lib->vba.ImmediateFlipBW[0],
>+							dml_max(
>+									UrgentExtraLatency
>+											+ UrgentLatencyPixelDataOnly
>+													* (GPUVMMaxPageTableLevels
>+															- 1),
>+									LineTime / 4.0));
>+		} else {
>+			TimeForFetchingMetaPTEImmediateFlip = 0;
>+		}
>+
>+		*DestinationLinesToRequestVMInImmediateFlip = dml_floor(
>+				4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime + 0.125),
>+				1) / 4.0;
>+
>+		if ((GPUVMEnable == true || DCCEnable == true)) {
>+			mode_lib->vba.ImmediateFlipBW[0] = BandwidthAvailableForImmediateFlip
>+					* ImmediateFlipBytes / TotImmediateFlipBytes;
>+			TimeForFetchingRowInVBlankImmediateFlip = dml_max(
>+					(MetaRowByte + PixelPTEBytesPerRow)
>+							/ mode_lib->vba.ImmediateFlipBW[0],
>+					dml_max(UrgentLatencyPixelDataOnly, LineTime / 4.0));
>+		} else {
>+			TimeForFetchingRowInVBlankImmediateFlip = 0;
>+		}
>+
>+		*DestinationLinesToRequestRowInImmediateFlip = dml_floor(
>+				4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime + 0.125),
>+				1) / 4.0;
>+
>+		if (GPUVMEnable == true) {
>+			*final_flip_bw =
>+					dml_max(
>+							PDEAndMetaPTEBytesFrame
>+									/ (*DestinationLinesToRequestVMInImmediateFlip
>+											* LineTime),
>+							(MetaRowByte + PixelPTEBytesPerRow)
>+									/ (TimeForFetchingRowInVBlankImmediateFlip
>+											* LineTime));
>+		} else if (MetaRowByte + PixelPTEBytesPerRow > 0) {
>+			*final_flip_bw = (MetaRowByte + PixelPTEBytesPerRow)
>+					/ (TimeForFetchingRowInVBlankImmediateFlip * LineTime);
>+		} else {
>+			*final_flip_bw = 0;
>+		}
>+
>+		if (GPUVMEnable && !DCCEnable)
>+			min_row_time = dpte_row_height * LineTime / VRatio;
>+		else if (!GPUVMEnable && DCCEnable)
>+			min_row_time = meta_row_height * LineTime / VRatio;
>+		else
>+			min_row_time = dml_min(dpte_row_height, meta_row_height) * LineTime
>+					/ VRatio;
>+
>+		if (*DestinationLinesToRequestVMInImmediateFlip >= 8
>+				|| *DestinationLinesToRequestRowInImmediateFlip >= 16
>+				|| TimeForFetchingMetaPTEImmediateFlip
>+						+ 2 * TimeForFetchingRowInVBlankImmediateFlip
>+						> min_row_time)
>+			*ImmediateFlipSupportedForPipe = false;
>+		else
>+			*ImmediateFlipSupportedForPipe = true;
>+	}
>+}
>+
>+static unsigned int TruncToValidBPP(
>+		double DecimalBPP,
>+		bool DSCEnabled,
>+		enum output_encoder_class Output,
>+		enum output_format_class Format,
>+		unsigned int DSCInputBitPerComponent)
>+{
>+	if (Output == dm_hdmi) {
>+		if (Format == dm_420) {
>+			if (DecimalBPP >= 18)
>+				return 18;
>+			else if (DecimalBPP >= 15)
>+				return 15;
>+			else if (DecimalBPP >= 12)
>+				return 12;
>+			else
>+				return BPP_INVALID;
>+		} else if (Format == dm_444) {
>+			if (DecimalBPP >= 36)
>+				return 36;
>+			else if (DecimalBPP >= 30)
>+				return 30;
>+			else if (DecimalBPP >= 24)
>+				return 24;
>+			else if (DecimalBPP >= 18)
>+				return 18;
>+			else
>+				return BPP_INVALID;
>+		} else {
>+			if (DecimalBPP / 1.5 >= 24)
>+				return 24;
>+			else if (DecimalBPP / 1.5 >= 20)
>+				return 20;
>+			else if (DecimalBPP / 1.5 >= 16)
>+				return 16;
>+			else
>+				return BPP_INVALID;
>+		}
>+	} else {
>+		if (DSCEnabled) {
>+			if (Format == dm_420) {
>+				if (DecimalBPP < 6)
>+					return BPP_INVALID;
>+				else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1 / 16)
>+					return 1.5 * DSCInputBitPerComponent - 1 / 16;
>+				else
>+					return dml_floor(16 * DecimalBPP, 1) / 16;
>+			} else if (Format == dm_n422) {
>+				if (DecimalBPP < 7)
>+					return BPP_INVALID;
>+				else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1 / 16)
>+					return 2 * DSCInputBitPerComponent - 1 / 16;
>+				else
>+					return dml_floor(16 * DecimalBPP, 1) / 16;
>+			} else {
>+				if (DecimalBPP < 8)
>+					return BPP_INVALID;
>+				else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1 / 16)
>+					return 3 * DSCInputBitPerComponent - 1 / 16;
>+				else
>+					return dml_floor(16 * DecimalBPP, 1) / 16;
>+			}
>+		} else if (Format == dm_420) {
>+			if (DecimalBPP >= 18)
>+				return 18;
>+			else if (DecimalBPP >= 15)
>+				return 15;
>+			else if (DecimalBPP >= 12)
>+				return 12;
>+			else
>+				return BPP_INVALID;
>+		} else if (Format == dm_s422 || Format == dm_n422) {
>+			if (DecimalBPP >= 24)
>+				return 24;
>+			else if (DecimalBPP >= 20)
>+				return 20;
>+			else if (DecimalBPP >= 16)
>+				return 16;
>+			else
>+				return BPP_INVALID;
>+		} else {
>+			if (DecimalBPP >= 36)
>+				return 36;
>+			else if (DecimalBPP >= 30)
>+				return 30;
>+			else if (DecimalBPP >= 24)
>+				return 24;
>+			else if (DecimalBPP >= 18)
>+				return 18;
>+			else
>+				return BPP_INVALID;
>+		}
>+	}
>+}
>+
>+void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
>+{
>+	struct vba_vars_st *locals = &mode_lib->vba;
>+
>+	int i;
>+	unsigned int j, k, m;
>+
>+	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
>+
>+	/*Scale Ratio, taps Support Check*/
>+
>+	mode_lib->vba.ScaleRatioAndTapsSupport = true;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.ScalerEnabled[k] == false
>+				&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)
>+						|| mode_lib->vba.HRatio[k] != 1.0
>+						|| mode_lib->vba.htaps[k] != 1.0
>+						|| mode_lib->vba.VRatio[k] != 1.0
>+						|| mode_lib->vba.vtaps[k] != 1.0)) {
>+			mode_lib->vba.ScaleRatioAndTapsSupport = false;
>+		} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0
>+				|| mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0
>+				|| (mode_lib->vba.htaps[k] > 1.0
>+						&& (mode_lib->vba.htaps[k] % 2) == 1)
>+				|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
>+				|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
>+				|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
>+				|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
>+				|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
>+						&& (mode_lib->vba.HRatio[k] / 2.0
>+								> mode_lib->vba.HTAPsChroma[k]
>+								|| mode_lib->vba.VRatio[k] / 2.0
>+										> mode_lib->vba.VTAPsChroma[k]))) {
>+			mode_lib->vba.ScaleRatioAndTapsSupport = false;
>+		}
>+	}
>+	/*Source Format, Pixel Format and Scan Support Check*/
>+
>+	mode_lib->vba.SourceFormatPixelAndScanSupport = true;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>+				&& mode_lib->vba.SourceScan[k] != dm_horz)
>+				|| ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d
>+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x
>+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d
>+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t
>+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x
>+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d
>+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x)
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_64)
>+				|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x
>+						&& (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8
>+								|| mode_lib->vba.SourcePixelFormat[k]
>+										== dm_420_8
>+								|| mode_lib->vba.SourcePixelFormat[k]
>+										== dm_420_10))
>+				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
>+						|| mode_lib->vba.SurfaceTiling[k]
>+								== dm_sw_gfx7_2d_thin_lvp)
>+						&& !((mode_lib->vba.SourcePixelFormat[k]
>+								== dm_444_64
>+								|| mode_lib->vba.SourcePixelFormat[k]
>+										== dm_444_32)
>+								&& mode_lib->vba.SourceScan[k]
>+										== dm_horz
>+								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
>+										== true
>+								&& mode_lib->vba.DCCEnable[k]
>+										== false))
>+						|| (mode_lib->vba.DCCEnable[k] == true
>+								&& (mode_lib->vba.SurfaceTiling[k]
>+										== dm_sw_linear
>+										|| mode_lib->vba.SourcePixelFormat[k]
>+												== dm_420_8
>+										|| mode_lib->vba.SourcePixelFormat[k]
>+												== dm_420_10)))) {
>+			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>+		}
>+	}
>+	/*Bandwidth Support Check*/
>+
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
>+			locals->BytePerPixelInDETY[k] = 8.0;
>+			locals->BytePerPixelInDETC[k] = 0.0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
>+			locals->BytePerPixelInDETY[k] = 4.0;
>+			locals->BytePerPixelInDETC[k] = 0.0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
>+			locals->BytePerPixelInDETY[k] = 2.0;
>+			locals->BytePerPixelInDETC[k] = 0.0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
>+			locals->BytePerPixelInDETY[k] = 1.0;
>+			locals->BytePerPixelInDETC[k] = 0.0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
>+			locals->BytePerPixelInDETY[k] = 1.0;
>+			locals->BytePerPixelInDETC[k] = 2.0;
>+		} else {
>+			locals->BytePerPixelInDETY[k] = 4.0 / 3;
>+			locals->BytePerPixelInDETC[k] = 8.0 / 3;
>+		}
>+		if (mode_lib->vba.SourceScan[k] == dm_horz) {
>+			locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
>+		} else {
>+			locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
>+		}
>+	}
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
>+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
>+		locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0)
>+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0;
>+		locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k];
>+	}
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.WritebackEnable[k] == true
>+				&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
>+			locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
>+					* mode_lib->vba.WritebackDestinationHeight[k]
>+					/ (mode_lib->vba.WritebackSourceHeight[k]
>+							* mode_lib->vba.HTotal[k]
>+							/ mode_lib->vba.PixelClock[k]) * 4.0;
>+		} else if (mode_lib->vba.WritebackEnable[k] == true
>+				&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
>+			locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
>+					* mode_lib->vba.WritebackDestinationHeight[k]
>+					/ (mode_lib->vba.WritebackSourceHeight[k]
>+							* mode_lib->vba.HTotal[k]
>+							/ mode_lib->vba.PixelClock[k]) * 3.0;
>+		} else if (mode_lib->vba.WritebackEnable[k] == true) {
>+			locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
>+					* mode_lib->vba.WritebackDestinationHeight[k]
>+					/ (mode_lib->vba.WritebackSourceHeight[k]
>+							* mode_lib->vba.HTotal[k]
>+							/ mode_lib->vba.PixelClock[k]) * 1.5;
>+		} else {
>+			locals->WriteBandwidth[k] = 0.0;
>+		}
>+	}
>+	mode_lib->vba.DCCEnabledInAnyPlane = false;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.DCCEnable[k] == true) {
>+			mode_lib->vba.DCCEnabledInAnyPlane = true;
>+		}
>+	}
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		locals->FabricAndDRAMBandwidthPerState[i] = dml_min(
>+				mode_lib->vba.DRAMSpeedPerState[i] * mode_lib->vba.NumberOfChannels
>+						* mode_lib->vba.DRAMChannelWidth,
>+				mode_lib->vba.FabricClockPerState[i]
>+						* mode_lib->vba.FabricDatapathToDCNDataReturn) / 1000;
>+		locals->ReturnBWToDCNPerState = dml_min(locals->ReturnBusWidth * locals->DCFCLKPerState[i],
>+				locals->FabricAndDRAMBandwidthPerState[i] * 1000)
>+				* locals->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly / 100;
>+
>+		locals->ReturnBWPerState[i] = locals->ReturnBWToDCNPerState;
>+
>+		if (locals->DCCEnabledInAnyPlane == true && locals->ReturnBWToDCNPerState > locals->DCFCLKPerState[i] * locals->ReturnBusWidth / 4) {
>+			locals->ReturnBWPerState[i] = dml_min(locals->ReturnBWPerState[i],
>+					locals->ReturnBWToDCNPerState * 4 * (1 - locals->UrgentLatency /
>+					((locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024
>+					/ (locals->ReturnBWToDCNPerState - locals->DCFCLKPerState[i]
>+					* locals->ReturnBusWidth / 4) + locals->UrgentLatency)));
>+		}
>+		locals->CriticalPoint = 2 * locals->ReturnBusWidth * locals->DCFCLKPerState[i] *
>+				locals->UrgentLatency / (locals->ReturnBWToDCNPerState * locals->UrgentLatency
>+				+ (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024);
>+
>+		if (locals->DCCEnabledInAnyPlane && locals->CriticalPoint > 1 && locals->CriticalPoint < 4) {
>+			locals->ReturnBWPerState[i] = dml_min(locals->ReturnBWPerState[i],
>+				4 * locals->ReturnBWToDCNPerState *
>+				(locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024
>+				* locals->ReturnBusWidth * locals->DCFCLKPerState[i] * locals->UrgentLatency /
>+				dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency
>+				+ (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024), 2));
>+		}
>+
>+		locals->ReturnBWToDCNPerState = dml_min(locals->ReturnBusWidth *
>+				locals->DCFCLKPerState[i], locals->FabricAndDRAMBandwidthPerState[i] * 1000);
>+
>+		if (locals->DCCEnabledInAnyPlane == true && locals->ReturnBWToDCNPerState > locals->DCFCLKPerState[i] * locals->ReturnBusWidth / 4) {
>+			locals->ReturnBWPerState[i] = dml_min(locals->ReturnBWPerState[i],
>+					locals->ReturnBWToDCNPerState * 4 * (1 - locals->UrgentLatency /
>+					((locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024
>+					/ (locals->ReturnBWToDCNPerState - locals->DCFCLKPerState[i]
>+					* locals->ReturnBusWidth / 4) + locals->UrgentLatency)));
>+		}
>+		locals->CriticalPoint = 2 * locals->ReturnBusWidth * locals->DCFCLKPerState[i] *
>+				locals->UrgentLatency / (locals->ReturnBWToDCNPerState * locals->UrgentLatency
>+				+ (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024);
>+
>+		if (locals->DCCEnabledInAnyPlane && locals->CriticalPoint > 1 && locals->CriticalPoint < 4) {
>+			locals->ReturnBWPerState[i] = dml_min(locals->ReturnBWPerState[i],
>+				4 * locals->ReturnBWToDCNPerState *
>+				(locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024
>+				* locals->ReturnBusWidth * locals->DCFCLKPerState[i] * locals->UrgentLatency /
>+				dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency
>+				+ (locals->ROBBufferSizeInKByte - locals->PixelChunkSizeInKByte) * 1024), 2));
>+		}
>+	}
>+	/*Writeback Latency support check*/
>+
>+	mode_lib->vba.WritebackLatencySupport = true;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.WritebackEnable[k] == true) {
>+			if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
>+				if (locals->WriteBandwidth[k]
>+						> (mode_lib->vba.WritebackInterfaceLumaBufferSize
>+								+ mode_lib->vba.WritebackInterfaceChromaBufferSize)
>+								/ mode_lib->vba.WritebackLatency) {
>+					mode_lib->vba.WritebackLatencySupport = false;
>+				}
>+			} else {
>+				if (locals->WriteBandwidth[k]
>+						> 1.5
>+								* dml_min(
>+										mode_lib->vba.WritebackInterfaceLumaBufferSize,
>+										2.0
>+												* mode_lib->vba.WritebackInterfaceChromaBufferSize)
>+								/ mode_lib->vba.WritebackLatency) {
>+					mode_lib->vba.WritebackLatencySupport = false;
>+				}
>+			}
>+		}
>+	}
>+	/*Re-ordering Buffer Support Check*/
>+
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i] =
>+				(mode_lib->vba.RoundTripPingLatencyCycles + 32.0) / mode_lib->vba.DCFCLKPerState[i]
>+				+ locals->UrgentOutOfOrderReturnPerChannel * mode_lib->vba.NumberOfChannels / locals->ReturnBWPerState[i];
>+		if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024.0 / locals->ReturnBWPerState[i]
>+				> locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i]) {
>+			locals->ROBSupport[i] = true;
>+		} else {
>+			locals->ROBSupport[i] = false;
>+		}
>+	}
>+	/*Writeback Mode Support Check*/
>+
>+	mode_lib->vba.TotalNumberOfActiveWriteback = 0;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.WritebackEnable[k] == true) {
>+			if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0)
>+				mode_lib->vba.ActiveWritebacksPerPlane[k] = 1;
>+			mode_lib->vba.TotalNumberOfActiveWriteback =
>+					mode_lib->vba.TotalNumberOfActiveWriteback
>+							+ mode_lib->vba.ActiveWritebacksPerPlane[k];
>+		}
>+	}
>+	mode_lib->vba.WritebackModeSupport = true;
>+	if (mode_lib->vba.TotalNumberOfActiveWriteback > mode_lib->vba.MaxNumWriteback) {
>+		mode_lib->vba.WritebackModeSupport = false;
>+	}
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.WritebackEnable[k] == true
>+				&& mode_lib->vba.Writeback10bpc420Supported != true
>+				&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
>+			mode_lib->vba.WritebackModeSupport = false;
>+		}
>+	}
>+	/*Writeback Scale Ratio and Taps Support Check*/
>+
>+	mode_lib->vba.WritebackScaleRatioAndTapsSupport = true;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.WritebackEnable[k] == true) {
>+			if (mode_lib->vba.WritebackLumaAndChromaScalingSupported == false
>+					&& (mode_lib->vba.WritebackHRatio[k] != 1.0
>+							|| mode_lib->vba.WritebackVRatio[k] != 1.0)) {
>+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
>+			}
>+			if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
>+					|| mode_lib->vba.WritebackVRatio[k]
>+							> mode_lib->vba.WritebackMaxVSCLRatio
>+					|| mode_lib->vba.WritebackHRatio[k]
>+							< mode_lib->vba.WritebackMinHSCLRatio
>+					|| mode_lib->vba.WritebackVRatio[k]
>+							< mode_lib->vba.WritebackMinVSCLRatio
>+					|| mode_lib->vba.WritebackLumaHTaps[k]
>+							> mode_lib->vba.WritebackMaxHSCLTaps
>+					|| mode_lib->vba.WritebackLumaVTaps[k]
>+							> mode_lib->vba.WritebackMaxVSCLTaps
>+					|| mode_lib->vba.WritebackHRatio[k]
>+							> mode_lib->vba.WritebackLumaHTaps[k]
>+					|| mode_lib->vba.WritebackVRatio[k]
>+							> mode_lib->vba.WritebackLumaVTaps[k]
>+					|| (mode_lib->vba.WritebackLumaHTaps[k] > 2.0
>+							&& ((mode_lib->vba.WritebackLumaHTaps[k] % 2)
>+									== 1))
>+					|| (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32
>+							&& (mode_lib->vba.WritebackChromaHTaps[k]
>+									> mode_lib->vba.WritebackMaxHSCLTaps
>+									|| mode_lib->vba.WritebackChromaVTaps[k]
>+											> mode_lib->vba.WritebackMaxVSCLTaps
>+									|| 2.0
>+											* mode_lib->vba.WritebackHRatio[k]
>+											> mode_lib->vba.WritebackChromaHTaps[k]
>+									|| 2.0
>+											* mode_lib->vba.WritebackVRatio[k]
>+											> mode_lib->vba.WritebackChromaVTaps[k]
>+									|| (mode_lib->vba.WritebackChromaHTaps[k] > 2.0
>+										&& ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) {
>+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
>+			}
>+			if (mode_lib->vba.WritebackVRatio[k] < 1.0) {
>+				mode_lib->vba.WritebackLumaVExtra =
>+						dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
>+			} else {
>+				mode_lib->vba.WritebackLumaVExtra = -1;
>+			}
>+			if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32
>+					&& mode_lib->vba.WritebackLumaVTaps[k]
>+							> (mode_lib->vba.WritebackLineBufferLumaBufferSize
>+									+ mode_lib->vba.WritebackLineBufferChromaBufferSize)
>+									/ 3.0
>+									/ mode_lib->vba.WritebackDestinationWidth[k]
>+									- mode_lib->vba.WritebackLumaVExtra)
>+					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
>+							&& mode_lib->vba.WritebackLumaVTaps[k]
>+									> mode_lib->vba.WritebackLineBufferLumaBufferSize
>+											* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
>+											- mode_lib->vba.WritebackLumaVExtra)
>+					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
>+							&& mode_lib->vba.WritebackLumaVTaps[k]
>+									> mode_lib->vba.WritebackLineBufferLumaBufferSize
>+											* 8.0 / 10.0
>+											/ mode_lib->vba.WritebackDestinationWidth[k]
>+											- mode_lib->vba.WritebackLumaVExtra)) {
>+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
>+			}
>+			if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) {
>+				mode_lib->vba.WritebackChromaVExtra = 0.0;
>+			} else {
>+				mode_lib->vba.WritebackChromaVExtra = -1;
>+			}
>+			if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
>+					&& mode_lib->vba.WritebackChromaVTaps[k]
>+							> mode_lib->vba.WritebackLineBufferChromaBufferSize
>+									* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
>+									- mode_lib->vba.WritebackChromaVExtra)
>+					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
>+							&& mode_lib->vba.WritebackChromaVTaps[k]
>+									> mode_lib->vba.WritebackLineBufferChromaBufferSize
>+											* 8.0 / 10.0
>+											/ mode_lib->vba.WritebackDestinationWidth[k]
>+											- mode_lib->vba.WritebackChromaVExtra)) {
>+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
>+			}
>+		}
>+	}
>+	/*Maximum DISPCLK/DPPCLK Support check*/
>+
>+	mode_lib->vba.WritebackRequiredDISPCLK = 0.0;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.WritebackEnable[k] == true) {
>+			mode_lib->vba.WritebackRequiredDISPCLK =
>+					dml_max(
>+							mode_lib->vba.WritebackRequiredDISPCLK,
>+							CalculateWriteBackDISPCLK(
>+									mode_lib->vba.WritebackPixelFormat[k],
>+									mode_lib->vba.PixelClock[k],
>+									mode_lib->vba.WritebackHRatio[k],
>+									mode_lib->vba.WritebackVRatio[k],
>+									mode_lib->vba.WritebackLumaHTaps[k],
>+									mode_lib->vba.WritebackLumaVTaps[k],
>+									mode_lib->vba.WritebackChromaHTaps[k],
>+									mode_lib->vba.WritebackChromaVTaps[k],
>+									mode_lib->vba.WritebackDestinationWidth[k],
>+									mode_lib->vba.HTotal[k],
>+									mode_lib->vba.WritebackChromaLineBufferWidth));
>+		}
>+	}
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.HRatio[k] > 1.0) {
>+			locals->PSCL_FACTOR[k] = dml_min(
>+					mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+					mode_lib->vba.MaxPSCLToLBThroughput
>+							* mode_lib->vba.HRatio[k]
>+							/ dml_ceil(
>+									mode_lib->vba.htaps[k]
>+											/ 6.0,
>+									1.0));
>+		} else {
>+			locals->PSCL_FACTOR[k] = dml_min(
>+					mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+					mode_lib->vba.MaxPSCLToLBThroughput);
>+		}
>+		if (locals->BytePerPixelInDETC[k] == 0.0) {
>+			locals->PSCL_FACTOR_CHROMA[k] = 0.0;
>+			locals->MinDPPCLKUsingSingleDPP[k] =
>+					mode_lib->vba.PixelClock[k]
>+							* dml_max3(
>+									mode_lib->vba.vtaps[k] / 6.0
>+											* dml_min(
>+													1.0,
>+													mode_lib->vba.HRatio[k]),
>+									mode_lib->vba.HRatio[k]
>+											* mode_lib->vba.VRatio[k]
>+											/ locals->PSCL_FACTOR[k],
>+									1.0);
>+			if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0)
>+					&& locals->MinDPPCLKUsingSingleDPP[k]
>+							< 2.0 * mode_lib->vba.PixelClock[k]) {
>+				locals->MinDPPCLKUsingSingleDPP[k] = 2.0
>+						* mode_lib->vba.PixelClock[k];
>+			}
>+		} else {
>+			if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) {
>+				locals->PSCL_FACTOR_CHROMA[k] =
>+						dml_min(
>+								mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+								mode_lib->vba.MaxPSCLToLBThroughput
>+										* mode_lib->vba.HRatio[k]
>+										/ 2.0
>+										/ dml_ceil(
>+												mode_lib->vba.HTAPsChroma[k]
>+														/ 6.0,
>+												1.0));
>+			} else {
>+				locals->PSCL_FACTOR_CHROMA[k] = dml_min(
>+						mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+						mode_lib->vba.MaxPSCLToLBThroughput);
>+			}
>+			locals->MinDPPCLKUsingSingleDPP[k] =
>+					mode_lib->vba.PixelClock[k]
>+							* dml_max5(
>+									mode_lib->vba.vtaps[k] / 6.0
>+											* dml_min(
>+													1.0,
>+													mode_lib->vba.HRatio[k]),
>+									mode_lib->vba.HRatio[k]
>+											* mode_lib->vba.VRatio[k]
>+											/ locals->PSCL_FACTOR[k],
>+									mode_lib->vba.VTAPsChroma[k]
>+											/ 6.0
>+											* dml_min(
>+													1.0,
>+													mode_lib->vba.HRatio[k]
>+															/ 2.0),
>+									mode_lib->vba.HRatio[k]
>+											* mode_lib->vba.VRatio[k]
>+											/ 4.0
>+											/ locals->PSCL_FACTOR_CHROMA[k],
>+									1.0);
>+			if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0
>+					|| mode_lib->vba.HTAPsChroma[k] > 6.0
>+					|| mode_lib->vba.VTAPsChroma[k] > 6.0)
>+					&& locals->MinDPPCLKUsingSingleDPP[k]
>+							< 2.0 * mode_lib->vba.PixelClock[k]) {
>+				locals->MinDPPCLKUsingSingleDPP[k] = 2.0
>+						* mode_lib->vba.PixelClock[k];
>+			}
>+		}
>+	}
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		Calculate256BBlockSizes(
>+				mode_lib->vba.SourcePixelFormat[k],
>+				mode_lib->vba.SurfaceTiling[k],
>+				dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
>+				dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
>+				&locals->Read256BlockHeightY[k],
>+				&locals->Read256BlockHeightC[k],
>+				&locals->Read256BlockWidthY[k],
>+				&locals->Read256BlockWidthC[k]);
>+		if (mode_lib->vba.SourceScan[k] == dm_horz) {
>+			locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k];
>+			locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k];
>+		} else {
>+			locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k];
>+			locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k];
>+		}
>+		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) {
>+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>+					|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
>+							&& (mode_lib->vba.SurfaceTiling[k]
>+									== dm_sw_4kb_s
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_4kb_s_x
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_64kb_s
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_64kb_s_t
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_64kb_s_x
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_var_s
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_var_s_x)
>+							&& mode_lib->vba.SourceScan[k] == dm_horz)) {
>+				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
>+			} else {
>+				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
>+						/ 2.0;
>+			}
>+			locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
>+		} else {
>+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
>+				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
>+				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
>+					&& mode_lib->vba.SourceScan[k] == dm_horz) {
>+				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
>+						/ 2.0;
>+				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
>+					&& mode_lib->vba.SourceScan[k] == dm_horz) {
>+				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]
>+						/ 2.0;
>+				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
>+			} else {
>+				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
>+				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
>+			}
>+		}
>+		if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
>+			mode_lib->vba.MaximumSwathWidthSupport = 8192.0;
>+		} else {
>+			mode_lib->vba.MaximumSwathWidthSupport = 5120.0;
>+		}
>+		mode_lib->vba.MaximumSwathWidthInDETBuffer =
>+				dml_min(
>+						mode_lib->vba.MaximumSwathWidthSupport,
>+						mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0
>+								/ (locals->BytePerPixelInDETY[k]
>+										* locals->MinSwathHeightY[k]
>+										+ locals->BytePerPixelInDETC[k]
>+												/ 2.0
>+												* locals->MinSwathHeightC[k]));
>+		if (locals->BytePerPixelInDETC[k] == 0.0) {
>+			mode_lib->vba.MaximumSwathWidthInLineBuffer =
>+					mode_lib->vba.LineBufferSize
>+							* dml_max(mode_lib->vba.HRatio[k], 1.0)
>+							/ mode_lib->vba.LBBitPerPixel[k]
>+							/ (mode_lib->vba.vtaps[k]
>+									+ dml_max(
>+											dml_ceil(
>+													mode_lib->vba.VRatio[k],
>+													1.0)
>+													- 2,
>+											0.0));
>+		} else {
>+			mode_lib->vba.MaximumSwathWidthInLineBuffer =
>+					dml_min(
>+							mode_lib->vba.LineBufferSize
>+									* dml_max(
>+											mode_lib->vba.HRatio[k],
>+											1.0)
>+									/ mode_lib->vba.LBBitPerPixel[k]
>+									/ (mode_lib->vba.vtaps[k]
>+											+ dml_max(
>+													dml_ceil(
>+															mode_lib->vba.VRatio[k],
>+															1.0)
>+															- 2,
>+													0.0)),
>+							2.0 * mode_lib->vba.LineBufferSize
>+									* dml_max(
>+											mode_lib->vba.HRatio[k]
>+													/ 2.0,
>+											1.0)
>+									/ mode_lib->vba.LBBitPerPixel[k]
>+									/ (mode_lib->vba.VTAPsChroma[k]
>+											+ dml_max(
>+													dml_ceil(
>+															mode_lib->vba.VRatio[k]
>+																	/ 2.0,
>+															1.0)
>+															- 2,
>+													0.0)));
>+		}
>+		locals->MaximumSwathWidth[k] = dml_min(
>+				mode_lib->vba.MaximumSwathWidthInDETBuffer,
>+				mode_lib->vba.MaximumSwathWidthInLineBuffer);
>+	}
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (j = 0; j < 2; j++) {
>+			mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
>+				mode_lib->vba.MaxDispclk[i],
>+				mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
>+			mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
>+				mode_lib->vba.MaxDppclk[i],
>+				mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
>+			locals->RequiredDISPCLK[i][j] = 0.0;
>+			locals->DISPCLK_DPPCLK_Support[i][j] = true;
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine =
>+						mode_lib->vba.PixelClock[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
>+								* (1.0 + mode_lib->vba.DISPCLKRampingMargin / 100.0);
>+				if (mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine >= mode_lib->vba.MaxDispclk[i]
>+						&& i == mode_lib->vba.soc.num_states)
>+					mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k]
>+							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>+
>+				mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
>+					* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * (1 + mode_lib->vba.DISPCLKRampingMargin / 100.0);
>+				if (mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine >= mode_lib->vba.MaxDispclk[i]
>+						&& i == mode_lib->vba.soc.num_states)
>+					mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
>+							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>+				if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
>+					locals->ODMCombineEnablePerState[i][k] = false;
>+					mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
>+				} else {
>+					locals->ODMCombineEnablePerState[i][k] = true;
>+					mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
>+				}
>+				if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
>+						&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
>+						&& locals->ODMCombineEnablePerState[i][k] == false) {
>+					locals->NoOfDPP[i][j][k] = 1;
>+					locals->RequiredDPPCLK[i][j][k] =
>+						locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>+				} else {
>+					locals->NoOfDPP[i][j][k] = 2;
>+					locals->RequiredDPPCLK[i][j][k] =
>+						locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
>+				}
>+				locals->RequiredDISPCLK[i][j] = dml_max(
>+						locals->RequiredDISPCLK[i][j],
>+						mode_lib->vba.PlaneRequiredDISPCLK);
>+				if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
>+						> mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity)
>+						|| (mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)) {
>+					locals->DISPCLK_DPPCLK_Support[i][j] = false;
>+				}
>+			}
>+			locals->TotalNumberOfActiveDPP[i][j] = 0.0;
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
>+				locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
>+			if (j == 1) {
>+				while (locals->TotalNumberOfActiveDPP[i][j] < mode_lib->vba.MaxNumDPP
>+						&& locals->TotalNumberOfActiveDPP[i][j] < 2 * mode_lib->vba.NumberOfActivePlanes) {
>+					double BWOfNonSplitPlaneOfMaximumBandwidth;
>+					unsigned int NumberOfNonSplitPlaneOfMaximumBandwidth;
>+
>+					BWOfNonSplitPlaneOfMaximumBandwidth = 0;
>+					NumberOfNonSplitPlaneOfMaximumBandwidth = 0;
>+					for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+						if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) {
>+							BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k];
>+							NumberOfNonSplitPlaneOfMaximumBandwidth = k;
>+						}
>+					}
>+					locals->NoOfDPP[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = 2;
>+					locals->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] =
>+						locals->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth]
>+							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2;
>+					locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + 1;
>+				}
>+			}
>+			if (locals->TotalNumberOfActiveDPP[i][j] > mode_lib->vba.MaxNumDPP) {
>+				locals->RequiredDISPCLK[i][j] = 0.0;
>+				locals->DISPCLK_DPPCLK_Support[i][j] = true;
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					locals->ODMCombineEnablePerState[i][k] = false;
>+					if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
>+						locals->NoOfDPP[i][j][k] = 1;
>+						locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
>+							* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>+					} else {
>+						locals->NoOfDPP[i][j][k] = 2;
>+						locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
>+										* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
>+					}
>+					if (i != mode_lib->vba.soc.num_states) {
>+						mode_lib->vba.PlaneRequiredDISPCLK =
>+								mode_lib->vba.PixelClock[k]
>+										* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
>+										* (1.0 + mode_lib->vba.DISPCLKRampingMargin / 100.0);
>+					} else {
>+						mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k]
>+							* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>+					}
>+					locals->RequiredDISPCLK[i][j] = dml_max(
>+							locals->RequiredDISPCLK[i][j],
>+							mode_lib->vba.PlaneRequiredDISPCLK);
>+					if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
>+							> mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
>+							|| mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)
>+						locals->DISPCLK_DPPCLK_Support[i][j] = false;
>+				}
>+				locals->TotalNumberOfActiveDPP[i][j] = 0.0;
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
>+					locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
>+			}
>+			locals->RequiredDISPCLK[i][j] = dml_max(
>+					locals->RequiredDISPCLK[i][j],
>+					mode_lib->vba.WritebackRequiredDISPCLK);
>+			if (mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity
>+					< mode_lib->vba.WritebackRequiredDISPCLK) {
>+				locals->DISPCLK_DPPCLK_Support[i][j] = false;
>+			}
>+		}
>+	}
>+	/*Viewport Size Check*/
>+
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		locals->ViewportSizeSupport[i] = true;
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			if (locals->ODMCombineEnablePerState[i][k] == true) {
>+				if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
>+						> locals->MaximumSwathWidth[k]) {
>+					locals->ViewportSizeSupport[i] = false;
>+				}
>+			} else {
>+				if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) {
>+					locals->ViewportSizeSupport[i] = false;
>+				}
>+			}
>+		}
>+	}
>+	/*Total Available Pipes Support Check*/
>+
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (j = 0; j < 2; j++) {
>+			if (locals->TotalNumberOfActiveDPP[i][j] <= mode_lib->vba.MaxNumDPP)
>+				locals->TotalAvailablePipesSupport[i][j] = true;
>+			else
>+				locals->TotalAvailablePipesSupport[i][j] = false;
>+		}
>+	}
>+	/*Total Available OTG Support Check*/
>+
>+	mode_lib->vba.TotalNumberOfActiveOTG = 0.0;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+			mode_lib->vba.TotalNumberOfActiveOTG = mode_lib->vba.TotalNumberOfActiveOTG
>+					+ 1.0;
>+		}
>+	}
>+	if (mode_lib->vba.TotalNumberOfActiveOTG <= mode_lib->vba.MaxNumOTG) {
>+		mode_lib->vba.NumberOfOTGSupport = true;
>+	} else {
>+		mode_lib->vba.NumberOfOTGSupport = false;
>+	}
>+	/*Display IO and DSC Support Check*/
>+
>+	mode_lib->vba.NonsupportedDSCInputBPC = false;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
>+				|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
>+				|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) {
>+			mode_lib->vba.NonsupportedDSCInputBPC = true;
>+		}
>+	}
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			locals->RequiresDSC[i][k] = 0;
>+			locals->RequiresFEC[i][k] = 0;
>+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+				if (mode_lib->vba.Output[k] == dm_hdmi) {
>+					locals->RequiresDSC[i][k] = 0;
>+					locals->RequiresFEC[i][k] = 0;
>+					locals->OutputBppPerState[i][k] = TruncToValidBPP(
>+							dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
>+							false,
>+							mode_lib->vba.Output[k],
>+							mode_lib->vba.OutputFormat[k],
>+							mode_lib->vba.DSCInputBitPerComponent[k]);
>+				} else if (mode_lib->vba.Output[k] == dm_dp
>+						|| mode_lib->vba.Output[k] == dm_edp) {
>+					if (mode_lib->vba.Output[k] == dm_edp) {
>+						mode_lib->vba.EffectiveFECOverhead = 0.0;
>+					} else {
>+						mode_lib->vba.EffectiveFECOverhead =
>+								mode_lib->vba.FECOverhead;
>+					}
>+					if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) {
>+						mode_lib->vba.Outbpp = TruncToValidBPP(
>+								(1.0 - mode_lib->vba.Downspreading / 100.0) * 270.0
>+								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
>+								false,
>+								mode_lib->vba.Output[k],
>+								mode_lib->vba.OutputFormat[k],
>+								mode_lib->vba.DSCInputBitPerComponent[k]);
>+						mode_lib->vba.OutbppDSC = TruncToValidBPP(
>+								(1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 270.0
>+								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
>+								true,
>+								mode_lib->vba.Output[k],
>+								mode_lib->vba.OutputFormat[k],
>+								mode_lib->vba.DSCInputBitPerComponent[k]);
>+						if (mode_lib->vba.DSCEnabled[k] == true) {
>+							locals->RequiresDSC[i][k] = true;
>+							if (mode_lib->vba.Output[k] == dm_dp) {
>+								locals->RequiresFEC[i][k] = true;
>+							} else {
>+								locals->RequiresFEC[i][k] = false;
>+							}
>+							mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC;
>+						} else {
>+							locals->RequiresDSC[i][k] = false;
>+							locals->RequiresFEC[i][k] = false;
>+						}
>+						locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
>+					}
>+					if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) {
>+						mode_lib->vba.Outbpp = TruncToValidBPP(
>+								(1.0 - mode_lib->vba.Downspreading / 100.0) * 540.0
>+								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
>+									false,
>+									mode_lib->vba.Output[k],
>+									mode_lib->vba.OutputFormat[k],
>+									mode_lib->vba.DSCInputBitPerComponent[k]);
>+						mode_lib->vba.OutbppDSC = TruncToValidBPP(
>+								(1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 540.0
>+								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
>+								true,
>+								mode_lib->vba.Output[k],
>+								mode_lib->vba.OutputFormat[k],
>+								mode_lib->vba.DSCInputBitPerComponent[k]);
>+						if (mode_lib->vba.DSCEnabled[k] == true) {
>+							locals->RequiresDSC[i][k] = true;
>+							if (mode_lib->vba.Output[k] == dm_dp) {
>+								locals->RequiresFEC[i][k] = true;
>+							} else {
>+								locals->RequiresFEC[i][k] = false;
>+							}
>+							mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC;
>+						} else {
>+							locals->RequiresDSC[i][k] = false;
>+							locals->RequiresFEC[i][k] = false;
>+						}
>+						locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
>+					}
>+					if (mode_lib->vba.Outbpp == BPP_INVALID
>+							&& mode_lib->vba.PHYCLKPerState[i]
>+									>= 810.0) {
>+						mode_lib->vba.Outbpp = TruncToValidBPP(
>+								(1.0 - mode_lib->vba.Downspreading / 100.0) * 810.0
>+								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
>+								false,
>+								mode_lib->vba.Output[k],
>+								mode_lib->vba.OutputFormat[k],
>+								mode_lib->vba.DSCInputBitPerComponent[k]);
>+						mode_lib->vba.OutbppDSC = TruncToValidBPP(
>+								(1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 810.0
>+								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
>+								true,
>+								mode_lib->vba.Output[k],
>+								mode_lib->vba.OutputFormat[k],
>+								mode_lib->vba.DSCInputBitPerComponent[k]);
>+						if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {
>+							locals->RequiresDSC[i][k] = true;
>+							if (mode_lib->vba.Output[k] == dm_dp) {
>+								locals->RequiresFEC[i][k] = true;
>+							} else {
>+								locals->RequiresFEC[i][k] = false;
>+							}
>+							mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC;
>+						} else {
>+							locals->RequiresDSC[i][k] = false;
>+							locals->RequiresFEC[i][k] = false;
>+						}
>+						locals->OutputBppPerState[i][k] =
>+								mode_lib->vba.Outbpp;
>+					}
>+				}
>+			} else {
>+				locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE;
>+			}
>+		}
>+	}
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		locals->DIOSupport[i] = true;
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			if (locals->OutputBppPerState[i][k] == BPP_INVALID
>+					|| (mode_lib->vba.OutputFormat[k] == dm_420
>+							&& mode_lib->vba.Interlace[k] == true
>+							&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) {
>+				locals->DIOSupport[i] = false;
>+			}
>+		}
>+	}
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			locals->DSCCLKRequiredMoreThanSupported[i] = false;
>+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+				if ((mode_lib->vba.Output[k] == dm_dp
>+						|| mode_lib->vba.Output[k] == dm_edp)) {
>+					if (mode_lib->vba.OutputFormat[k] == dm_420
>+							|| mode_lib->vba.OutputFormat[k]
>+									== dm_n422) {
>+						mode_lib->vba.DSCFormatFactor = 2;
>+					} else {
>+						mode_lib->vba.DSCFormatFactor = 1;
>+					}
>+					if (locals->RequiresDSC[i][k] == true) {
>+						if (locals->ODMCombineEnablePerState[i][k]
>+								== true) {
>+							if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor
>+									> (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) {
>+								locals->DSCCLKRequiredMoreThanSupported[i] =
>+										true;
>+							}
>+						} else {
>+							if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor
>+									> (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) {
>+								locals->DSCCLKRequiredMoreThanSupported[i] =
>+										true;
>+							}
>+						}
>+					}
>+				}
>+			}
>+		}
>+	}
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		locals->NotEnoughDSCUnits[i] = false;
>+		mode_lib->vba.TotalDSCUnitsRequired = 0.0;
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			if (locals->RequiresDSC[i][k] == true) {
>+				if (locals->ODMCombineEnablePerState[i][k] == true) {
>+					mode_lib->vba.TotalDSCUnitsRequired =
>+							mode_lib->vba.TotalDSCUnitsRequired + 2.0;
>+				} else {
>+					mode_lib->vba.TotalDSCUnitsRequired =
>+							mode_lib->vba.TotalDSCUnitsRequired + 1.0;
>+				}
>+			}
>+		}
>+		if (mode_lib->vba.TotalDSCUnitsRequired > mode_lib->vba.NumberOfDSC) {
>+			locals->NotEnoughDSCUnits[i] = true;
>+		}
>+	}
>+	/*DSC Delay per state*/
>+
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			if (mode_lib->vba.BlendingAndTiming[k] != k) {
>+				mode_lib->vba.slices = 0;
>+			} else if (locals->RequiresDSC[i][k] == 0
>+					|| locals->RequiresDSC[i][k] == false) {
>+				mode_lib->vba.slices = 0;
>+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) {
>+				mode_lib->vba.slices = dml_ceil(
>+						mode_lib->vba.PixelClockBackEnd[k] / 400.0,
>+						4.0);
>+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) {
>+				mode_lib->vba.slices = 8.0;
>+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) {
>+				mode_lib->vba.slices = 4.0;
>+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) {
>+				mode_lib->vba.slices = 2.0;
>+			} else {
>+				mode_lib->vba.slices = 1.0;
>+			}
>+			if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE
>+					|| locals->OutputBppPerState[i][k] == BPP_INVALID) {
>+				mode_lib->vba.bpp = 0.0;
>+			} else {
>+				mode_lib->vba.bpp = locals->OutputBppPerState[i][k];
>+			}
>+			if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {
>+				if (locals->ODMCombineEnablePerState[i][k] == false) {
>+					locals->DSCDelayPerState[i][k] =
>+							dscceComputeDelay(
>+									mode_lib->vba.DSCInputBitPerComponent[k],
>+									mode_lib->vba.bpp,
>+									dml_ceil(
>+											mode_lib->vba.HActive[k]
>+													/ mode_lib->vba.slices,
>+											1.0),
>+									mode_lib->vba.slices,
>+									mode_lib->vba.OutputFormat[k])
>+									+ dscComputeDelay(
>+											mode_lib->vba.OutputFormat[k]);
>+				} else {
>+					locals->DSCDelayPerState[i][k] =
>+							2.0 * (dscceComputeDelay(
>+											mode_lib->vba.DSCInputBitPerComponent[k],
>+											mode_lib->vba.bpp,
>+											dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0),
>+											mode_lib->vba.slices / 2,
>+											mode_lib->vba.OutputFormat[k])
>+									+ dscComputeDelay(mode_lib->vba.OutputFormat[k]));
>+				}
>+				locals->DSCDelayPerState[i][k] =
>+						locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k];
>+			} else {
>+				locals->DSCDelayPerState[i][k] = 0.0;
>+			}
>+		}
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) {
>+				for (j = 0; j <= mode_lib->vba.NumberOfActivePlanes - 1; j++) {
>+					if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)
>+						locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m];
>+				}
>+			}
>+		}
>+	}
>+
>+	//Prefetch Check
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (j = 0; j < 2; j++) {
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				if (locals->ODMCombineEnablePerState[i][k] == true)
>+					locals->SwathWidthYPerState[i][j][k] = dml_min(locals->SwathWidthYSingleDPP[k], dml_round(locals->HActive[k] / 2 * locals->HRatio[k]));
>+				else
>+					locals->SwathWidthYPerState[i][j][k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k];
>+				locals->SwathWidthGranularityY = 256  / dml_ceil(locals->BytePerPixelInDETY[k], 1) / locals->MaxSwathHeightY[k];
>+				locals->RoundedUpMaxSwathSizeBytesY = (dml_ceil(locals->SwathWidthYPerState[i][j][k] - 1, locals->SwathWidthGranularityY)
>+						+ locals->SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k];
>+				if (locals->SourcePixelFormat[k] == dm_420_10) {
>+					locals->RoundedUpMaxSwathSizeBytesY = dml_ceil(locals->RoundedUpMaxSwathSizeBytesY, 256) + 256;
>+				}
>+				if (locals->MaxSwathHeightC[k] > 0) {
>+					locals->SwathWidthGranularityC = 256 / dml_ceil(locals->BytePerPixelInDETC[k], 2) / locals->MaxSwathHeightC[k];
>+
>+					locals->RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYPerState[i][j][k] / 2 - 1, locals->SwathWidthGranularityC)
>+					+ locals->SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k];
>+				}
>+				if (locals->SourcePixelFormat[k] == dm_420_10) {
>+					locals->RoundedUpMaxSwathSizeBytesC = dml_ceil(locals->RoundedUpMaxSwathSizeBytesC, 256)  + 256;
>+				} else {
>+					locals->RoundedUpMaxSwathSizeBytesC = 0;
>+				}
>+
>+				if (locals->RoundedUpMaxSwathSizeBytesY + locals->RoundedUpMaxSwathSizeBytesC <= locals->DETBufferSizeInKByte * 1024 / 2) {
>+					locals->SwathHeightYPerState[i][j][k] = locals->MaxSwathHeightY[k];
>+					locals->SwathHeightCPerState[i][j][k] = locals->MaxSwathHeightC[k];
>+				} else {
>+					locals->SwathHeightYPerState[i][j][k] = locals->MinSwathHeightY[k];
>+					locals->SwathHeightCPerState[i][j][k] = locals->MinSwathHeightC[k];
>+				}
>+
>+				if (locals->BytePerPixelInDETC[k] == 0) {
>+					locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
>+					locals->LinesInDETChroma = 0;
>+				} else if (locals->SwathHeightYPerState[i][j][k] <= locals->SwathHeightCPerState[i][j][k]) {
>+					locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETY[k] /
>+							locals->SwathWidthYPerState[i][j][k];
>+					locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 2 / locals->BytePerPixelInDETC[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
>+				} else {
>+					locals->LinesInDETLuma = locals->DETBufferSizeInKByte * 1024 * 2 / 3 / locals->BytePerPixelInDETY[k] / locals->SwathWidthYPerState[i][j][k];
>+					locals->LinesInDETChroma = locals->DETBufferSizeInKByte * 1024 / 3 / locals->BytePerPixelInDETY[k] / (locals->SwathWidthYPerState[i][j][k] / 2);
>+				}
>+
>+				locals->EffectiveLBLatencyHidingSourceLinesLuma = dml_min(locals->MaxLineBufferLines,
>+					dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k] / (locals->SwathWidthYPerState[i][j][k]
>+					/ dml_max(locals->HRatio[k], 1)), 1)) - (locals->vtaps[k] - 1);
>+
>+				locals->EffectiveLBLatencyHidingSourceLinesChroma =  dml_min(locals->MaxLineBufferLines,
>+						dml_floor(locals->LineBufferSize / locals->LBBitPerPixel[k]
>+						/ (locals->SwathWidthYPerState[i][j][k] / 2
>+						/ dml_max(locals->HRatio[k] / 2, 1)), 1)) - (locals->VTAPsChroma[k] - 1);
>+
>+				locals->EffectiveDETLBLinesLuma = dml_floor(locals->LinesInDETLuma +  dml_min(
>+						locals->LinesInDETLuma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETY[k] *
>+						locals->PSCL_FACTOR[k] / locals->ReturnBWPerState[i],
>+						locals->EffectiveLBLatencyHidingSourceLinesLuma),
>+						locals->SwathHeightYPerState[i][j][k]);
>+
>+				locals->EffectiveDETLBLinesChroma = dml_floor(locals->LinesInDETChroma + dml_min(
>+						locals->LinesInDETChroma * locals->RequiredDISPCLK[i][j] * locals->BytePerPixelInDETC[k] *
>+						locals->PSCL_FACTOR_CHROMA[k] / locals->ReturnBWPerState[i],
>+						locals->EffectiveLBLatencyHidingSourceLinesChroma),
>+						locals->SwathHeightCPerState[i][j][k]);
>+
>+				if (locals->BytePerPixelInDETC[k] == 0) {
>+					locals->UrgentLatencySupportUsPerState[i][j][k] = locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k])
>+							/ locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] *
>+								dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k]);
>+				} else {
>+					locals->UrgentLatencySupportUsPerState[i][j][k] = dml_min(
>+						locals->EffectiveDETLBLinesLuma * (locals->HTotal[k] / locals->PixelClock[k])
>+						/ locals->VRatio[k] - locals->EffectiveDETLBLinesLuma * locals->SwathWidthYPerState[i][j][k] *
>+						dml_ceil(locals->BytePerPixelInDETY[k], 1) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k]),
>+							locals->EffectiveDETLBLinesChroma * (locals->HTotal[k] / locals->PixelClock[k]) / (locals->VRatio[k] / 2) -
>+							locals->EffectiveDETLBLinesChroma * locals->SwathWidthYPerState[i][j][k] / 2 *
>+							dml_ceil(locals->BytePerPixelInDETC[k], 2) / (locals->ReturnBWPerState[i] / locals->NoOfDPP[i][j][k]));
>+				}
>+			}
>+		}
>+	}
>+
>+	for (i = 0; i <= locals->soc.num_states; i++) {
>+		for (j = 0; j < 2; j++) {
>+			locals->UrgentLatencySupport[i][j] = true;
>+			for (k = 0; k < locals->NumberOfActivePlanes; k++) {
>+				if (locals->UrgentLatencySupportUsPerState[i][j][k] < locals->UrgentLatency)
>+					locals->UrgentLatencySupport[i][j] = false;
>+			}
>+		}
>+	}
>+
>+
>+	/*Prefetch Check*/
>+	for (i = 0; i <= locals->soc.num_states; i++) {
>+		for (j = 0; j < 2; j++) {
>+			locals->TotalNumberOfDCCActiveDPP[i][j] = 0;
>+			for (k = 0; k < locals->NumberOfActivePlanes; k++) {
>+				if (locals->DCCEnable[k] == true) {
>+					locals->TotalNumberOfDCCActiveDPP[i][j] =
>+						locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
>+				}
>+			}
>+		}
>+	}
>+
>+	CalculateMinAndMaxPrefetchMode(locals->AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, &locals->MinPrefetchMode, &locals->MaxPrefetchMode);
>+
>+	locals->MaxTotalVActiveRDBandwidth = 0;
>+	for (k = 0; k < locals->NumberOfActivePlanes; k++) {
>+		locals->MaxTotalVActiveRDBandwidth = locals->MaxTotalVActiveRDBandwidth + locals->ReadBandwidth[k];
>+	}
>+
>+	for (i = 0; i <= locals->soc.num_states; i++) {
>+		for (j = 0; j < 2; j++) {
>+			for (k = 0; k < locals->NumberOfActivePlanes; k++) {
>+				locals->NoOfDPPThisState[k] = locals->NoOfDPP[i][j][k];
>+				locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
>+				locals->SwathHeightYThisState[k] = locals->SwathHeightYPerState[i][j][k];
>+				locals->SwathHeightCThisState[k] = locals->SwathHeightCPerState[i][j][k];
>+				locals->SwathWidthYThisState[k] = locals->SwathWidthYPerState[i][j][k];
>+				mode_lib->vba.ProjectedDCFCLKDeepSleep = dml_max(
>+						mode_lib->vba.ProjectedDCFCLKDeepSleep,
>+						mode_lib->vba.PixelClock[k] / 16.0);
>+				if (mode_lib->vba.BytePerPixelInDETC[k] == 0.0) {
>+					if (mode_lib->vba.VRatio[k] <= 1.0) {
>+						mode_lib->vba.ProjectedDCFCLKDeepSleep =
>+								dml_max(
>+										mode_lib->vba.ProjectedDCFCLKDeepSleep,
>+										1.1
>+												* dml_ceil(
>+														mode_lib->vba.BytePerPixelInDETY[k],
>+														1.0)
>+												/ 64.0
>+												* mode_lib->vba.HRatio[k]
>+												* mode_lib->vba.PixelClock[k]
>+												/ mode_lib->vba.NoOfDPP[i][j][k]);
>+					} else {
>+						mode_lib->vba.ProjectedDCFCLKDeepSleep =
>+								dml_max(
>+										mode_lib->vba.ProjectedDCFCLKDeepSleep,
>+										1.1
>+												* dml_ceil(
>+														mode_lib->vba.BytePerPixelInDETY[k],
>+														1.0)
>+												/ 64.0
>+												* mode_lib->vba.PSCL_FACTOR[k]
>+												* mode_lib->vba.RequiredDPPCLK[i][j][k]);
>+					}
>+				} else {
>+					if (mode_lib->vba.VRatio[k] <= 1.0) {
>+						mode_lib->vba.ProjectedDCFCLKDeepSleep =
>+								dml_max(
>+										mode_lib->vba.ProjectedDCFCLKDeepSleep,
>+										1.1
>+												* dml_ceil(
>+														mode_lib->vba.BytePerPixelInDETY[k],
>+														1.0)
>+												/ 32.0
>+												* mode_lib->vba.HRatio[k]
>+												* mode_lib->vba.PixelClock[k]
>+												/ mode_lib->vba.NoOfDPP[i][j][k]);
>+					} else {
>+						mode_lib->vba.ProjectedDCFCLKDeepSleep =
>+								dml_max(
>+										mode_lib->vba.ProjectedDCFCLKDeepSleep,
>+										1.1
>+												* dml_ceil(
>+														mode_lib->vba.BytePerPixelInDETY[k],
>+														1.0)
>+												/ 32.0
>+												* mode_lib->vba.PSCL_FACTOR[k]
>+												* mode_lib->vba.RequiredDPPCLK[i][j][k]);
>+					}
>+					if (mode_lib->vba.VRatio[k] / 2.0 <= 1.0) {
>+						mode_lib->vba.ProjectedDCFCLKDeepSleep =
>+								dml_max(
>+										mode_lib->vba.ProjectedDCFCLKDeepSleep,
>+										1.1
>+												* dml_ceil(
>+														mode_lib->vba.BytePerPixelInDETC[k],
>+														2.0)
>+												/ 32.0
>+												* mode_lib->vba.HRatio[k]
>+												/ 2.0
>+												* mode_lib->vba.PixelClock[k]
>+												/ mode_lib->vba.NoOfDPP[i][j][k]);
>+					} else {
>+						mode_lib->vba.ProjectedDCFCLKDeepSleep =
>+								dml_max(
>+										mode_lib->vba.ProjectedDCFCLKDeepSleep,
>+										1.1
>+												* dml_ceil(
>+														mode_lib->vba.BytePerPixelInDETC[k],
>+														2.0)
>+												/ 32.0
>+												* mode_lib->vba.PSCL_FACTOR_CHROMA[k]
>+												* mode_lib->vba.RequiredDPPCLK[i][j][k]);
>+					}
>+				}
>+			}
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				mode_lib->vba.PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes(
>+						mode_lib,
>+						mode_lib->vba.DCCEnable[k],
>+						mode_lib->vba.Read256BlockHeightY[k],
>+						mode_lib->vba.Read256BlockWidthY[k],
>+						mode_lib->vba.SourcePixelFormat[k],
>+						mode_lib->vba.SurfaceTiling[k],
>+						dml_ceil(mode_lib->vba.BytePerPixelInDETY[k], 1.0),
>+						mode_lib->vba.SourceScan[k],
>+						mode_lib->vba.ViewportWidth[k],
>+						mode_lib->vba.ViewportHeight[k],
>+						mode_lib->vba.SwathWidthYPerState[i][j][k],
>+						mode_lib->vba.GPUVMEnable,
>+						mode_lib->vba.VMMPageSize,
>+						mode_lib->vba.PTEBufferSizeInRequestsLuma,
>+						mode_lib->vba.PDEProcessingBufIn64KBReqs,
>+						mode_lib->vba.PitchY[k],
>+						mode_lib->vba.DCCMetaPitchY[k],
>+						&mode_lib->vba.MacroTileWidthY[k],
>+						&mode_lib->vba.MetaRowBytesY,
>+						&mode_lib->vba.DPTEBytesPerRowY,
>+						&mode_lib->vba.PTEBufferSizeNotExceededY[i][j][k],
>+						&mode_lib->vba.dpte_row_height[k],
>+						&mode_lib->vba.meta_row_height[k]);
>+				mode_lib->vba.PrefetchLinesY[k] = CalculatePrefetchSourceLines(
>+						mode_lib,
>+						mode_lib->vba.VRatio[k],
>+						mode_lib->vba.vtaps[k],
>+						mode_lib->vba.Interlace[k],
>+						mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+						mode_lib->vba.SwathHeightYPerState[i][j][k],
>+						mode_lib->vba.ViewportYStartY[k],
>+						&mode_lib->vba.PrefillY[k],
>+						&mode_lib->vba.MaxNumSwY[k]);
>+				if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) {
>+					mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes(
>+							mode_lib,
>+							mode_lib->vba.DCCEnable[k],
>+							mode_lib->vba.Read256BlockHeightY[k],
>+							mode_lib->vba.Read256BlockWidthY[k],
>+							mode_lib->vba.SourcePixelFormat[k],
>+							mode_lib->vba.SurfaceTiling[k],
>+							dml_ceil(mode_lib->vba.BytePerPixelInDETC[k], 2.0),
>+							mode_lib->vba.SourceScan[k],
>+							mode_lib->vba.ViewportWidth[k] / 2.0,
>+							mode_lib->vba.ViewportHeight[k] / 2.0,
>+							mode_lib->vba.SwathWidthYPerState[i][j][k] / 2.0,
>+							mode_lib->vba.GPUVMEnable,
>+							mode_lib->vba.VMMPageSize,
>+							mode_lib->vba.PTEBufferSizeInRequestsLuma,
>+							mode_lib->vba.PDEProcessingBufIn64KBReqs,
>+							mode_lib->vba.PitchC[k],
>+							0.0,
>+							&mode_lib->vba.MacroTileWidthC[k],
>+							&mode_lib->vba.MetaRowBytesC,
>+							&mode_lib->vba.DPTEBytesPerRowC,
>+							&mode_lib->vba.PTEBufferSizeNotExceededC[i][j][k],
>+							&mode_lib->vba.dpte_row_height_chroma[k],
>+							&mode_lib->vba.meta_row_height_chroma[k]);
>+					mode_lib->vba.PrefetchLinesC[k] = CalculatePrefetchSourceLines(
>+							mode_lib,
>+							mode_lib->vba.VRatio[k] / 2.0,
>+							mode_lib->vba.VTAPsChroma[k],
>+							mode_lib->vba.Interlace[k],
>+							mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+							mode_lib->vba.SwathHeightCPerState[i][j][k],
>+							mode_lib->vba.ViewportYStartC[k],
>+							&mode_lib->vba.PrefillC[k],
>+							&mode_lib->vba.MaxNumSwC[k]);
>+				} else {
>+					mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0;
>+					mode_lib->vba.MetaRowBytesC = 0.0;
>+					mode_lib->vba.DPTEBytesPerRowC = 0.0;
>+					locals->PrefetchLinesC[k] = 0.0;
>+					locals->PTEBufferSizeNotExceededC[i][j][k] = true;
>+					locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma;
>+				}
>+				locals->PDEAndMetaPTEBytesPerFrame[k] =
>+						mode_lib->vba.PDEAndMetaPTEBytesPerFrameY + mode_lib->vba.PDEAndMetaPTEBytesPerFrameC;
>+				locals->MetaRowBytes[k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC;
>+				locals->DPTEBytesPerRow[k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC;
>+
>+				CalculateActiveRowBandwidth(
>+						mode_lib->vba.GPUVMEnable,
>+						mode_lib->vba.SourcePixelFormat[k],
>+						mode_lib->vba.VRatio[k],
>+						mode_lib->vba.DCCEnable[k],
>+						mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
>+						mode_lib->vba.MetaRowBytesY,
>+						mode_lib->vba.MetaRowBytesC,
>+						mode_lib->vba.meta_row_height[k],
>+						mode_lib->vba.meta_row_height_chroma[k],
>+						mode_lib->vba.DPTEBytesPerRowY,
>+						mode_lib->vba.DPTEBytesPerRowC,
>+						mode_lib->vba.dpte_row_height[k],
>+						mode_lib->vba.dpte_row_height_chroma[k],
>+						&mode_lib->vba.meta_row_bw[k],
>+						&mode_lib->vba.dpte_row_bw[k],
>+						&mode_lib->vba.qual_row_bw[k]);
>+			}
>+			mode_lib->vba.ExtraLatency =
>+					mode_lib->vba.UrgentRoundTripAndOutOfOrderLatencyPerState[i]
>+							+ (mode_lib->vba.TotalNumberOfActiveDPP[i][j]
>+									* mode_lib->vba.PixelChunkSizeInKByte
>+									+ mode_lib->vba.TotalNumberOfDCCActiveDPP[i][j]
>+											* mode_lib->vba.MetaChunkSize)
>+									* 1024.0
>+									/ mode_lib->vba.ReturnBWPerState[i];
>+			if (mode_lib->vba.GPUVMEnable == true) {
>+				mode_lib->vba.ExtraLatency = mode_lib->vba.ExtraLatency
>+						+ mode_lib->vba.TotalNumberOfActiveDPP[i][j]
>+								* mode_lib->vba.PTEGroupSize
>+								/ mode_lib->vba.ReturnBWPerState[i];
>+			}
>+			mode_lib->vba.TimeCalc = 24.0 / mode_lib->vba.ProjectedDCFCLKDeepSleep;
>+
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+					if (mode_lib->vba.WritebackEnable[k] == true) {
>+						locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency
>+								+ CalculateWriteBackDelay(
>+										mode_lib->vba.WritebackPixelFormat[k],
>+										mode_lib->vba.WritebackHRatio[k],
>+										mode_lib->vba.WritebackVRatio[k],
>+										mode_lib->vba.WritebackLumaHTaps[k],
>+										mode_lib->vba.WritebackLumaVTaps[k],
>+										mode_lib->vba.WritebackChromaHTaps[k],
>+										mode_lib->vba.WritebackChromaVTaps[k],
>+										mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j];
>+					} else {
>+						locals->WritebackDelay[i][k] = 0.0;
>+					}
>+					for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) {
>+						if (mode_lib->vba.BlendingAndTiming[m] == k
>+								&& mode_lib->vba.WritebackEnable[m]
>+										== true) {
>+							locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
>+											mode_lib->vba.WritebackLatency + CalculateWriteBackDelay(
>+													mode_lib->vba.WritebackPixelFormat[m],
>+													mode_lib->vba.WritebackHRatio[m],
>+													mode_lib->vba.WritebackVRatio[m],
>+													mode_lib->vba.WritebackLumaHTaps[m],
>+													mode_lib->vba.WritebackLumaVTaps[m],
>+													mode_lib->vba.WritebackChromaHTaps[m],
>+													mode_lib->vba.WritebackChromaVTaps[m],
>+													mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]);
>+						}
>+					}
>+				}
>+			}
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) {
>+					if (mode_lib->vba.BlendingAndTiming[k] == m) {
>+						locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m];
>+					}
>+				}
>+			}
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				for (m = 0; m < locals->NumberOfCursors[k]; m++)
>+					locals->cursor_bw[k] = locals->NumberOfCursors[k] * locals->CursorWidth[k][m] * locals->CursorBPP[k][m]
>+						/ 8 / (locals->HTotal[k] / locals->PixelClock[k]) * locals->VRatio[k];
>+			}
>+
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				locals->MaximumVStartup[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
>+					- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
>+			}
>+
>+			mode_lib->vba.NextPrefetchMode = mode_lib->vba.MinPrefetchMode;
>+			do {
>+				mode_lib->vba.PrefetchMode[i][j] = mode_lib->vba.NextPrefetchMode;
>+				mode_lib->vba.NextPrefetchMode = mode_lib->vba.NextPrefetchMode + 1;
>+
>+				mode_lib->vba.TWait = CalculateTWait(
>+						mode_lib->vba.PrefetchMode[i][j],
>+						mode_lib->vba.DRAMClockChangeLatency,
>+						mode_lib->vba.UrgentLatency,
>+						mode_lib->vba.SREnterPlusExitTime);
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+
>+					if (mode_lib->vba.XFCEnabled[k] == true) {
>+						mode_lib->vba.XFCRemoteSurfaceFlipDelay =
>+								CalculateRemoteSurfaceFlipDelay(
>+										mode_lib,
>+										mode_lib->vba.VRatio[k],
>+										locals->SwathWidthYPerState[i][j][k],
>+										dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
>+										mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
>+										mode_lib->vba.XFCTSlvVupdateOffset,
>+										mode_lib->vba.XFCTSlvVupdateWidth,
>+										mode_lib->vba.XFCTSlvVreadyOffset,
>+										mode_lib->vba.XFCXBUFLatencyTolerance,
>+										mode_lib->vba.XFCFillBWOverhead,
>+										mode_lib->vba.XFCSlvChunkSize,
>+										mode_lib->vba.XFCBusTransportTime,
>+										mode_lib->vba.TimeCalc,
>+										mode_lib->vba.TWait,
>+										&mode_lib->vba.SrcActiveDrainRate,
>+										&mode_lib->vba.TInitXFill,
>+										&mode_lib->vba.TslvChk);
>+					} else {
>+						mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0.0;
>+					}
>+
>+					CalculateDelayAfterScaler(mode_lib, mode_lib->vba.ReturnBWPerState[i], mode_lib->vba.ReadBandwidthLuma[k], mode_lib->vba.ReadBandwidthChroma[k], mode_lib->vba.MaxTotalVActiveRDBandwidth,
>+						mode_lib->vba.DisplayPipeLineDeliveryTimeLuma[k], mode_lib->vba.DisplayPipeLineDeliveryTimeChroma[k],
>+						mode_lib->vba.RequiredDPPCLK[i][j][k], mode_lib->vba.RequiredDISPCLK[i][j], mode_lib->vba.PixelClock[k], mode_lib->vba.DSCDelayPerState[i][k], mode_lib->vba.NoOfDPP[i][j][k], mode_lib->vba.ScalerEnabled[k], mode_lib->vba.NumberOfCursors[k],
>+						mode_lib->vba.DPPCLKDelaySubtotal, mode_lib->vba.DPPCLKDelaySCL, mode_lib->vba.DPPCLKDelaySCLLBOnly, mode_lib->vba.DPPCLKDelayCNVCFormater, mode_lib->vba.DPPCLKDelayCNVCCursor, mode_lib->vba.DISPCLKDelaySubtotal,
>+						mode_lib->vba.SwathWidthYPerState[i][j][k] / mode_lib->vba.HRatio[k], mode_lib->vba.OutputFormat[k], mode_lib->vba.HTotal[k],
>+						mode_lib->vba.SwathWidthYSingleDPP[k], mode_lib->vba.BytePerPixelInDETY[k], mode_lib->vba.BytePerPixelInDETC[k], mode_lib->vba.SwathHeightYThisState[k], mode_lib->vba.SwathHeightCThisState[k], mode_lib->vba.Interlace[k], mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+						&mode_lib->vba.DSTXAfterScaler[k], &mode_lib->vba.DSTYAfterScaler[k]);
>+
>+					mode_lib->vba.IsErrorResult[i][j][k] =
>+							CalculatePrefetchSchedule(
>+									mode_lib,
>+									mode_lib->vba.RequiredDPPCLK[i][j][k],
>+									mode_lib->vba.RequiredDISPCLK[i][j],
>+									mode_lib->vba.PixelClock[k],
>+									mode_lib->vba.ProjectedDCFCLKDeepSleep,
>+									mode_lib->vba.NoOfDPP[i][j][k],
>+									mode_lib->vba.NumberOfCursors[k],
>+									mode_lib->vba.VTotal[k]
>+											- mode_lib->vba.VActive[k],
>+									mode_lib->vba.HTotal[k],
>+									mode_lib->vba.MaxInterDCNTileRepeaters,
>+									mode_lib->vba.MaximumVStartup[k],
>+									mode_lib->vba.GPUVMMaxPageTableLevels,
>+									mode_lib->vba.GPUVMEnable,
>+									mode_lib->vba.DynamicMetadataEnable[k],
>+									mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
>+									mode_lib->vba.DynamicMetadataTransmittedBytes[k],
>+									mode_lib->vba.DCCEnable[k],
>+									mode_lib->vba.UrgentLatencyPixelDataOnly,
>+									mode_lib->vba.ExtraLatency,
>+									mode_lib->vba.TimeCalc,
>+									mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k],
>+									mode_lib->vba.MetaRowBytes[k],
>+									mode_lib->vba.DPTEBytesPerRow[k],
>+									mode_lib->vba.PrefetchLinesY[k],
>+									mode_lib->vba.SwathWidthYPerState[i][j][k],
>+									mode_lib->vba.BytePerPixelInDETY[k],
>+									mode_lib->vba.PrefillY[k],
>+									mode_lib->vba.MaxNumSwY[k],
>+									mode_lib->vba.PrefetchLinesC[k],
>+									mode_lib->vba.BytePerPixelInDETC[k],
>+									mode_lib->vba.PrefillC[k],
>+									mode_lib->vba.MaxNumSwC[k],
>+									mode_lib->vba.SwathHeightYPerState[i][j][k],
>+									mode_lib->vba.SwathHeightCPerState[i][j][k],
>+									mode_lib->vba.TWait,
>+									mode_lib->vba.XFCEnabled[k],
>+									mode_lib->vba.XFCRemoteSurfaceFlipDelay,
>+									mode_lib->vba.Interlace[k],
>+									mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+									mode_lib->vba.DSTXAfterScaler[k],
>+									mode_lib->vba.DSTYAfterScaler[k],
>+									&mode_lib->vba.LineTimesForPrefetch[k],
>+									&mode_lib->vba.PrefetchBW[k],
>+									&mode_lib->vba.LinesForMetaPTE[k],
>+									&mode_lib->vba.LinesForMetaAndDPTERow[k],
>+									&mode_lib->vba.VRatioPreY[i][j][k],
>+									&mode_lib->vba.VRatioPreC[i][j][k],
>+									&mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k],
>+									&mode_lib->vba.Tno_bw[k],
>+									&mode_lib->vba.VUpdateOffsetPix[k],
>+									&mode_lib->vba.VUpdateWidthPix[k],
>+									&mode_lib->vba.VReadyOffsetPix[k]);
>+				}
>+				mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = 0.0;
>+				mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0;
>+				locals->prefetch_vm_bw_valid = true;
>+				locals->prefetch_row_bw_valid = true;
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					if (locals->PDEAndMetaPTEBytesPerFrame[k] == 0)
>+						locals->prefetch_vm_bw[k] = 0;
>+					else if (locals->LinesForMetaPTE[k] > 0)
>+						locals->prefetch_vm_bw[k] = locals->PDEAndMetaPTEBytesPerFrame[k]
>+							/ (locals->LinesForMetaPTE[k] * locals->HTotal[k] / locals->PixelClock[k]);
>+					else {
>+						locals->prefetch_vm_bw[k] = 0;
>+						locals->prefetch_vm_bw_valid = false;
>+					}
>+					if (locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k] == 0)
>+						locals->prefetch_row_bw[k] = 0;
>+					else if (locals->LinesForMetaAndDPTERow[k] > 0)
>+						locals->prefetch_row_bw[k] = (locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k])
>+							/ (locals->LinesForMetaAndDPTERow[k] * locals->HTotal[k] / locals->PixelClock[k]);
>+					else {
>+						locals->prefetch_row_bw[k] = 0;
>+						locals->prefetch_row_bw_valid = false;
>+					}
>+
>+					mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = mode_lib->vba.MaximumReadBandwidthWithPrefetch
>+							+ mode_lib->vba.cursor_bw[k] + mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k];
>+					mode_lib->vba.MaximumReadBandwidthWithPrefetch =
>+							mode_lib->vba.MaximumReadBandwidthWithPrefetch
>+									+ mode_lib->vba.cursor_bw[k]
>+									+ dml_max3(
>+											mode_lib->vba.prefetch_vm_bw[k],
>+											mode_lib->vba.prefetch_row_bw[k],
>+											dml_max(mode_lib->vba.ReadBandwidth[k],
>+											mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k])
>+											+ mode_lib->vba.meta_row_bw[k] + mode_lib->vba.dpte_row_bw[k]);
>+				}
>+				locals->BandwidthWithoutPrefetchSupported[i] = true;
>+				if (mode_lib->vba.MaximumReadBandwidthWithoutPrefetch > locals->ReturnBWPerState[i]) {
>+					locals->BandwidthWithoutPrefetchSupported[i] = false;
>+				}
>+
>+				locals->PrefetchSupported[i][j] = true;
>+				if (mode_lib->vba.MaximumReadBandwidthWithPrefetch > locals->ReturnBWPerState[i]) {
>+					locals->PrefetchSupported[i][j] = false;
>+				}
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					if (locals->LineTimesForPrefetch[k] < 2.0
>+							|| locals->LinesForMetaPTE[k] >= 8.0
>+							|| locals->LinesForMetaAndDPTERow[k] >= 16.0
>+							|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
>+						locals->PrefetchSupported[i][j] = false;
>+					}
>+				}
>+				locals->VRatioInPrefetchSupported[i][j] = true;
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					if (locals->VRatioPreY[i][j][k] > 4.0
>+							|| locals->VRatioPreC[i][j][k] > 4.0
>+							|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
>+						locals->VRatioInPrefetchSupported[i][j] = false;
>+					}
>+				}
>+			} while ((locals->PrefetchSupported[i][j] != true || locals->VRatioInPrefetchSupported[i][j] != true)
>+					&& mode_lib->vba.NextPrefetchMode < mode_lib->vba.MaxPrefetchMode);
>+
>+			if (mode_lib->vba.PrefetchSupported[i][j] == true
>+					&& mode_lib->vba.VRatioInPrefetchSupported[i][j] == true) {
>+				mode_lib->vba.BandwidthAvailableForImmediateFlip =
>+						mode_lib->vba.ReturnBWPerState[i];
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					mode_lib->vba.BandwidthAvailableForImmediateFlip =
>+							mode_lib->vba.BandwidthAvailableForImmediateFlip
>+									- mode_lib->vba.cursor_bw[k]
>+									- dml_max(
>+											mode_lib->vba.ReadBandwidth[k] + mode_lib->vba.qual_row_bw[k],
>+											mode_lib->vba.PrefetchBW[k]);
>+				}
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					mode_lib->vba.ImmediateFlipBytes[k] = 0.0;
>+					if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
>+							&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
>+						mode_lib->vba.ImmediateFlipBytes[k] =
>+								mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k]
>+										+ mode_lib->vba.MetaRowBytes[k]
>+										+ mode_lib->vba.DPTEBytesPerRow[k];
>+					}
>+				}
>+				mode_lib->vba.TotImmediateFlipBytes = 0.0;
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
>+							&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
>+						mode_lib->vba.TotImmediateFlipBytes =
>+								mode_lib->vba.TotImmediateFlipBytes
>+										+ mode_lib->vba.ImmediateFlipBytes[k];
>+					}
>+				}
>+
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					CalculateFlipSchedule(
>+							mode_lib,
>+							mode_lib->vba.ExtraLatency,
>+							mode_lib->vba.UrgentLatencyPixelDataOnly,
>+							mode_lib->vba.GPUVMMaxPageTableLevels,
>+							mode_lib->vba.GPUVMEnable,
>+							mode_lib->vba.BandwidthAvailableForImmediateFlip,
>+							mode_lib->vba.TotImmediateFlipBytes,
>+							mode_lib->vba.SourcePixelFormat[k],
>+							mode_lib->vba.ImmediateFlipBytes[k],
>+							mode_lib->vba.HTotal[k]
>+									/ mode_lib->vba.PixelClock[k],
>+							mode_lib->vba.VRatio[k],
>+							mode_lib->vba.Tno_bw[k],
>+							mode_lib->vba.PDEAndMetaPTEBytesPerFrame[k],
>+							mode_lib->vba.MetaRowBytes[k],
>+							mode_lib->vba.DPTEBytesPerRow[k],
>+							mode_lib->vba.DCCEnable[k],
>+							mode_lib->vba.dpte_row_height[k],
>+							mode_lib->vba.meta_row_height[k],
>+							mode_lib->vba.qual_row_bw[k],
>+							&mode_lib->vba.DestinationLinesToRequestVMInImmediateFlip[k],
>+							&mode_lib->vba.DestinationLinesToRequestRowInImmediateFlip[k],
>+							&mode_lib->vba.final_flip_bw[k],
>+							&mode_lib->vba.ImmediateFlipSupportedForPipe[k]);
>+				}
>+				mode_lib->vba.total_dcn_read_bw_with_flip = 0.0;
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					mode_lib->vba.total_dcn_read_bw_with_flip =
>+							mode_lib->vba.total_dcn_read_bw_with_flip
>+									+ mode_lib->vba.cursor_bw[k]
>+									+ dml_max3(
>+											mode_lib->vba.prefetch_vm_bw[k],
>+											mode_lib->vba.prefetch_row_bw[k],
>+											mode_lib->vba.final_flip_bw[k]
>+													+ dml_max(
>+															mode_lib->vba.ReadBandwidth[k],
>+															mode_lib->vba.RequiredPrefetchPixelDataBWLuma[i][j][k]));
>+				}
>+				mode_lib->vba.ImmediateFlipSupportedForState[i][j] = true;
>+				if (mode_lib->vba.total_dcn_read_bw_with_flip
>+						> mode_lib->vba.ReturnBWPerState[i]) {
>+					mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
>+				}
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					if (mode_lib->vba.ImmediateFlipSupportedForPipe[k] == false) {
>+						mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
>+					}
>+				}
>+			} else {
>+				mode_lib->vba.ImmediateFlipSupportedForState[i][j] = false;
>+			}
>+		}
>+	}
>+
>+	/*Vertical Active BW support*/
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i] = dml_min(mode_lib->vba.ReturnBusWidth *
>+				mode_lib->vba.DCFCLKPerState[i], mode_lib->vba.FabricAndDRAMBandwidthPerState[i] * 1000) *
>+				mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation / 100;
>+		if (mode_lib->vba.MaxTotalVActiveRDBandwidth <= mode_lib->vba.MaxTotalVerticalActiveAvailableBandwidth[i])
>+			mode_lib->vba.TotalVerticalActiveBandwidthSupport[i] = true;
>+		else
>+			mode_lib->vba.TotalVerticalActiveBandwidthSupport[i] = false;
>+	}
>+
>+	/*PTE Buffer Size Check*/
>+
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (j = 0; j < 2; j++) {
>+			locals->PTEBufferSizeNotExceeded[i][j] = true;
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
>+						|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
>+					locals->PTEBufferSizeNotExceeded[i][j] = false;
>+				}
>+			}
>+		}
>+	}
>+	/*Cursor Support Check*/
>+	mode_lib->vba.CursorSupport = true;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		for (j = 0; j < 2; j++) {
>+			if (mode_lib->vba.CursorWidth[k][j] > 0.0) {
>+				if (dml_floor(
>+						dml_floor(
>+								mode_lib->vba.CursorBufferSize
>+										- mode_lib->vba.CursorChunkSize,
>+								mode_lib->vba.CursorChunkSize) * 1024.0
>+								/ (mode_lib->vba.CursorWidth[k][j]
>+										* mode_lib->vba.CursorBPP[k][j]
>+										/ 8.0),
>+						1.0)
>+						* (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
>+						/ mode_lib->vba.VRatio[k] < mode_lib->vba.UrgentLatencyPixelDataOnly
>+						|| (mode_lib->vba.CursorBPP[k][j] == 64.0
>+								&& mode_lib->vba.Cursor64BppSupport == false)) {
>+					mode_lib->vba.CursorSupport = false;
>+				}
>+			}
>+		}
>+	}
>+	/*Valid Pitch Check*/
>+
>+	mode_lib->vba.PitchSupport = true;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		locals->AlignedYPitch[k] = dml_ceil(
>+				dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
>+				locals->MacroTileWidthY[k]);
>+		if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) {
>+			mode_lib->vba.PitchSupport = false;
>+		}
>+		if (mode_lib->vba.DCCEnable[k] == true) {
>+			locals->AlignedDCCMetaPitch[k] = dml_ceil(
>+					dml_max(
>+							mode_lib->vba.DCCMetaPitchY[k],
>+							mode_lib->vba.ViewportWidth[k]),
>+					64.0 * locals->Read256BlockWidthY[k]);
>+		} else {
>+			locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k];
>+		}
>+		if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) {
>+			mode_lib->vba.PitchSupport = false;
>+		}
>+		if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
>+			locals->AlignedCPitch[k] = dml_ceil(
>+					dml_max(
>+							mode_lib->vba.PitchC[k],
>+							mode_lib->vba.ViewportWidth[k] / 2.0),
>+					locals->MacroTileWidthC[k]);
>+		} else {
>+			locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k];
>+		}
>+		if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) {
>+			mode_lib->vba.PitchSupport = false;
>+		}
>+	}
>+	/*Mode Support, Voltage State and SOC Configuration*/
>+
>+	for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
>+		for (j = 0; j < 2; j++) {
>+			enum dm_validation_status status = DML_VALIDATION_OK;
>+
>+			if (mode_lib->vba.ScaleRatioAndTapsSupport != true) {
>+				status = DML_FAIL_SCALE_RATIO_TAP;
>+			} else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) {
>+				status = DML_FAIL_SOURCE_PIXEL_FORMAT;
>+			} else if (locals->ViewportSizeSupport[i] != true) {
>+				status = DML_FAIL_VIEWPORT_SIZE;
>+			} else if (locals->DIOSupport[i] != true) {
>+				status = DML_FAIL_DIO_SUPPORT;
>+			} else if (locals->NotEnoughDSCUnits[i] != false) {
>+				status = DML_FAIL_NOT_ENOUGH_DSC;
>+			} else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) {
>+				status = DML_FAIL_DSC_CLK_REQUIRED;
>+			} else if (locals->UrgentLatencySupport[i][j] != true) {
>+				status = DML_FAIL_URGENT_LATENCY;
>+			} else if (locals->ROBSupport[i] != true) {
>+				status = DML_FAIL_REORDERING_BUFFER;
>+			} else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) {
>+				status = DML_FAIL_DISPCLK_DPPCLK;
>+			} else if (locals->TotalAvailablePipesSupport[i][j] != true) {
>+				status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
>+			} else if (mode_lib->vba.NumberOfOTGSupport != true) {
>+				status = DML_FAIL_NUM_OTG;
>+			} else if (mode_lib->vba.WritebackModeSupport != true) {
>+				status = DML_FAIL_WRITEBACK_MODE;
>+			} else if (mode_lib->vba.WritebackLatencySupport != true) {
>+				status = DML_FAIL_WRITEBACK_LATENCY;
>+			} else if (mode_lib->vba.WritebackScaleRatioAndTapsSupport != true) {
>+				status = DML_FAIL_WRITEBACK_SCALE_RATIO_TAP;
>+			} else if (mode_lib->vba.CursorSupport != true) {
>+				status = DML_FAIL_CURSOR_SUPPORT;
>+			} else if (mode_lib->vba.PitchSupport != true) {
>+				status = DML_FAIL_PITCH_SUPPORT;
>+			} else if (locals->PrefetchSupported[i][j] != true) {
>+				status = DML_FAIL_PREFETCH_SUPPORT;
>+			} else if (locals->TotalVerticalActiveBandwidthSupport[i] != true) {
>+				status = DML_FAIL_TOTAL_V_ACTIVE_BW;
>+			} else if (locals->VRatioInPrefetchSupported[i][j] != true) {
>+				status = DML_FAIL_V_RATIO_PREFETCH;
>+			} else if (locals->PTEBufferSizeNotExceeded[i][j] != true) {
>+				status = DML_FAIL_PTE_BUFFER_SIZE;
>+			} else if (mode_lib->vba.NonsupportedDSCInputBPC != false) {
>+				status = DML_FAIL_DSC_INPUT_BPC;
>+			}
>+
>+			if (status == DML_VALIDATION_OK) {
>+				locals->ModeSupport[i][j] = true;
>+			} else {
>+				locals->ModeSupport[i][j] = false;
>+			}
>+			locals->ValidationStatus[i] = status;
>+		}
>+	}
>+	{
>+		unsigned int MaximumMPCCombine = 0;
>+		mode_lib->vba.VoltageLevel = mode_lib->vba.soc.num_states + 1;
>+		for (i = mode_lib->vba.VoltageOverrideLevel; i <= mode_lib->vba.soc.num_states; i++) {
>+			if (locals->ModeSupport[i][0] == true || locals->ModeSupport[i][1] == true) {
>+				mode_lib->vba.VoltageLevel = i;
>+				if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false
>+						|| mode_lib->vba.WhenToDoMPCCombine == dm_mpc_always_when_possible)) {
>+					MaximumMPCCombine = 1;
>+				} else {
>+					MaximumMPCCombine = 0;
>+				}
>+				break;
>+			}
>+		}
>+		mode_lib->vba.ImmediateFlipSupport =
>+			locals->ImmediateFlipSupportedForState[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
>+			locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
>+		}
>+		mode_lib->vba.DISPCLK = locals->RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
>+		mode_lib->vba.maxMpcComb = MaximumMPCCombine;
>+	}
>+	mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel];
>+	mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel];
>+	mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel];
>+	mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel];
>+	mode_lib->vba.ReturnBW = locals->ReturnBWPerState[mode_lib->vba.VoltageLevel];
>+	mode_lib->vba.FabricAndDRAMBandwidth = locals->FabricAndDRAMBandwidthPerState[mode_lib->vba.VoltageLevel];
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+			mode_lib->vba.ODMCombineEnabled[k] =
>+					locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
>+		} else {
>+			mode_lib->vba.ODMCombineEnabled[k] = 0;
>+		}
>+		mode_lib->vba.DSCEnabled[k] =
>+				locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
>+		mode_lib->vba.OutputBpp[k] =
>+				locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k];
>+	}
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.h	2019-08-31 15:01:11.867736169 -0500
>@@ -0,0 +1,32 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifndef _DCN20V2_DISPLAY_MODE_VBA_H_
>+#define _DCN20V2_DISPLAY_MODE_VBA_H_
>+
>+void dml20v2_recalculate(struct display_mode_lib *mode_lib);
>+void dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c	2019-08-31 15:01:11.867736169 -0500
>@@ -0,0 +1,1701 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#include "../display_mode_lib.h"
>+#include "../display_mode_vba.h"
>+#include "display_rq_dlg_calc_20v2.h"
>+
>+// Function: dml20v2_rq_dlg_get_rq_params
>+//  Calculate requestor related parameters that register definition agnostic
>+//  (i.e. this layer does try to separate real values from register definition)
>+// Input:
>+//  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
>+// Output:
>+//  rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
>+//
>+static void dml20v2_rq_dlg_get_rq_params(
>+		struct display_mode_lib *mode_lib,
>+		display_rq_params_st * rq_param,
>+		const display_pipe_source_params_st pipe_src_param);
>+
>+// Function: dml20v2_rq_dlg_get_dlg_params
>+//  Calculate deadline related parameters
>+//
>+static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
>+		const display_e2e_pipe_params_st *e2e_pipe_param,
>+		const unsigned int num_pipes,
>+		const unsigned int pipe_idx,
>+		display_dlg_regs_st *disp_dlg_regs,
>+		display_ttu_regs_st *disp_ttu_regs,
>+		const display_rq_dlg_params_st rq_dlg_param,
>+		const display_dlg_sys_params_st dlg_sys_param,
>+		const bool cstate_en,
>+		const bool pstate_en);
>+/*
>+ * NOTE:
>+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
>+ *
>+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
>+ * ways. Unless there is something clearly wrong with it the code should
>+ * remain as-is as it provides us with a guarantee from HW that it is correct.
>+ */
>+
>+static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
>+		double *refcyc_per_req_delivery_pre_cur,
>+		double *refcyc_per_req_delivery_cur,
>+		double refclk_freq_in_mhz,
>+		double ref_freq_to_pix_freq,
>+		double hscale_pixel_rate_l,
>+		double hscl_ratio,
>+		double vratio_pre_l,
>+		double vratio_l,
>+		unsigned int cur_width,
>+		enum cursor_bpp cur_bpp);
>+
>+#include "../dml_inline_defs.h"
>+
>+static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
>+{
>+	unsigned int ret_val = 0;
>+
>+	if (source_format == dm_444_16) {
>+		if (!is_chroma)
>+			ret_val = 2;
>+	} else if (source_format == dm_444_32) {
>+		if (!is_chroma)
>+			ret_val = 4;
>+	} else if (source_format == dm_444_64) {
>+		if (!is_chroma)
>+			ret_val = 8;
>+	} else if (source_format == dm_420_8) {
>+		if (is_chroma)
>+			ret_val = 2;
>+		else
>+			ret_val = 1;
>+	} else if (source_format == dm_420_10) {
>+		if (is_chroma)
>+			ret_val = 4;
>+		else
>+			ret_val = 2;
>+	} else if (source_format == dm_444_8) {
>+		ret_val = 1;
>+	}
>+	return ret_val;
>+}
>+
>+static bool is_dual_plane(enum source_format_class source_format)
>+{
>+	bool ret_val = 0;
>+
>+	if ((source_format == dm_420_8) || (source_format == dm_420_10))
>+		ret_val = 1;
>+
>+	return ret_val;
>+}
>+
>+static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib,
>+		double refclk_freq_in_mhz,
>+		double pclk_freq_in_mhz,
>+		bool odm_combine,
>+		unsigned int recout_width,
>+		unsigned int hactive,
>+		double vratio,
>+		double hscale_pixel_rate,
>+		unsigned int delivery_width,
>+		unsigned int req_per_swath_ub)
>+{
>+	double refcyc_per_delivery = 0.0;
>+
>+	if (vratio <= 1.0) {
>+		if (odm_combine)
>+			refcyc_per_delivery = (double) refclk_freq_in_mhz
>+					* dml_min((double) recout_width, (double) hactive / 2.0)
>+					/ pclk_freq_in_mhz / (double) req_per_swath_ub;
>+		else
>+			refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width
>+					/ pclk_freq_in_mhz / (double) req_per_swath_ub;
>+	} else {
>+		refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width
>+				/ (double) hscale_pixel_rate / (double) req_per_swath_ub;
>+	}
>+
>+	dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
>+	dml_print("DML_DLG: %s: pclk_freq_in_mhz   = %3.2f\n", __func__, pclk_freq_in_mhz);
>+	dml_print("DML_DLG: %s: recout_width       = %d\n", __func__, recout_width);
>+	dml_print("DML_DLG: %s: vratio             = %3.2f\n", __func__, vratio);
>+	dml_print("DML_DLG: %s: req_per_swath_ub   = %d\n", __func__, req_per_swath_ub);
>+	dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
>+
>+	return refcyc_per_delivery;
>+
>+}
>+
>+static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
>+{
>+	if (tile_size == dm_256k_tile)
>+		return (256 * 1024);
>+	else if (tile_size == dm_64k_tile)
>+		return (64 * 1024);
>+	else
>+		return (4 * 1024);
>+}
>+
>+static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib,
>+		display_data_rq_regs_st *rq_regs,
>+		const display_data_rq_sizing_params_st rq_sizing)
>+{
>+	dml_print("DML_DLG: %s: rq_sizing param\n", __func__);
>+	print__data_rq_sizing_params_st(mode_lib, rq_sizing);
>+
>+	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
>+
>+	if (rq_sizing.min_chunk_bytes == 0)
>+		rq_regs->min_chunk_size = 0;
>+	else
>+		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
>+
>+	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
>+	if (rq_sizing.min_meta_chunk_bytes == 0)
>+		rq_regs->min_meta_chunk_size = 0;
>+	else
>+		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
>+
>+	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
>+	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
>+}
>+
>+static void extract_rq_regs(struct display_mode_lib *mode_lib,
>+		display_rq_regs_st *rq_regs,
>+		const display_rq_params_st rq_param)
>+{
>+	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
>+	unsigned int detile_buf_plane1_addr = 0;
>+
>+	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
>+
>+	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
>+			1) - 3;
>+
>+	if (rq_param.yuv420) {
>+		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
>+		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
>+				1) - 3;
>+	}
>+
>+	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
>+	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
>+
>+	// FIXME: take the max between luma, chroma chunk size?
>+	// okay for now, as we are setting chunk_bytes to 8kb anyways
>+	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb
>+		rq_regs->drq_expansion_mode = 0;
>+	} else {
>+		rq_regs->drq_expansion_mode = 2;
>+	}
>+	rq_regs->prq_expansion_mode = 1;
>+	rq_regs->mrq_expansion_mode = 1;
>+	rq_regs->crq_expansion_mode = 1;
>+
>+	if (rq_param.yuv420) {
>+		if ((double) rq_param.misc.rq_l.stored_swath_bytes
>+				/ (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
>+			detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma
>+		} else {
>+			detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
>+					256,
>+					0) / 64.0; // 2/3 to chroma
>+		}
>+	}
>+	rq_regs->plane1_base_address = detile_buf_plane1_addr;
>+}
>+
>+static void handle_det_buf_split(struct display_mode_lib *mode_lib,
>+		display_rq_params_st *rq_param,
>+		const display_pipe_source_params_st pipe_src_param)
>+{
>+	unsigned int total_swath_bytes = 0;
>+	unsigned int swath_bytes_l = 0;
>+	unsigned int swath_bytes_c = 0;
>+	unsigned int full_swath_bytes_packed_l = 0;
>+	unsigned int full_swath_bytes_packed_c = 0;
>+	bool req128_l = 0;
>+	bool req128_c = 0;
>+	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
>+	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
>+	unsigned int log2_swath_height_l = 0;
>+	unsigned int log2_swath_height_c = 0;
>+	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
>+
>+	full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
>+	full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
>+
>+	if (rq_param->yuv420_10bpc) {
>+		full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2 / 3,
>+				256,
>+				1) + 256;
>+		full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2 / 3,
>+				256,
>+				1) + 256;
>+	}
>+
>+	if (rq_param->yuv420) {
>+		total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
>+
>+		if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
>+			req128_l = 0;
>+			req128_c = 0;
>+			swath_bytes_l = full_swath_bytes_packed_l;
>+			swath_bytes_c = full_swath_bytes_packed_c;
>+		} else { //128b request (for luma only for yuv420 8bpc)
>+			req128_l = 1;
>+			req128_c = 0;
>+			swath_bytes_l = full_swath_bytes_packed_l / 2;
>+			swath_bytes_c = full_swath_bytes_packed_c;
>+		}
>+		// Note: assumption, the config that pass in will fit into
>+		//       the detiled buffer.
>+	} else {
>+		total_swath_bytes = 2 * full_swath_bytes_packed_l;
>+
>+		if (total_swath_bytes <= detile_buf_size_in_bytes)
>+			req128_l = 0;
>+		else
>+			req128_l = 1;
>+
>+		swath_bytes_l = total_swath_bytes;
>+		swath_bytes_c = 0;
>+	}
>+	rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
>+	rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
>+
>+	if (surf_linear) {
>+		log2_swath_height_l = 0;
>+		log2_swath_height_c = 0;
>+	} else if (!surf_vert) {
>+		log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
>+		log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
>+	} else {
>+		log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
>+		log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
>+	}
>+	rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
>+	rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
>+
>+	dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
>+	dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
>+	dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",
>+			__func__,
>+			full_swath_bytes_packed_l);
>+	dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",
>+			__func__,
>+			full_swath_bytes_packed_c);
>+}
>+
>+static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,
>+		display_data_rq_dlg_params_st *rq_dlg_param,
>+		display_data_rq_misc_params_st *rq_misc_param,
>+		display_data_rq_sizing_params_st *rq_sizing_param,
>+		unsigned int vp_width,
>+		unsigned int vp_height,
>+		unsigned int data_pitch,
>+		unsigned int meta_pitch,
>+		unsigned int source_format,
>+		unsigned int tiling,
>+		unsigned int macro_tile_size,
>+		unsigned int source_scan,
>+		unsigned int is_chroma)
>+{
>+	bool surf_linear = (tiling == dm_sw_linear);
>+	bool surf_vert = (source_scan == dm_vert);
>+
>+	unsigned int bytes_per_element;
>+	unsigned int bytes_per_element_y = get_bytes_per_element((enum source_format_class)(source_format),
>+			false);
>+	unsigned int bytes_per_element_c = get_bytes_per_element((enum source_format_class)(source_format),
>+			true);
>+
>+	unsigned int blk256_width = 0;
>+	unsigned int blk256_height = 0;
>+
>+	unsigned int blk256_width_y = 0;
>+	unsigned int blk256_height_y = 0;
>+	unsigned int blk256_width_c = 0;
>+	unsigned int blk256_height_c = 0;
>+	unsigned int log2_bytes_per_element;
>+	unsigned int log2_blk256_width;
>+	unsigned int log2_blk256_height;
>+	unsigned int blk_bytes;
>+	unsigned int log2_blk_bytes;
>+	unsigned int log2_blk_height;
>+	unsigned int log2_blk_width;
>+	unsigned int log2_meta_req_bytes;
>+	unsigned int log2_meta_req_height;
>+	unsigned int log2_meta_req_width;
>+	unsigned int meta_req_width;
>+	unsigned int meta_req_height;
>+	unsigned int log2_meta_row_height;
>+	unsigned int meta_row_width_ub;
>+	unsigned int log2_meta_chunk_bytes;
>+	unsigned int log2_meta_chunk_height;
>+
>+	//full sized meta chunk width in unit of data elements
>+	unsigned int log2_meta_chunk_width;
>+	unsigned int log2_min_meta_chunk_bytes;
>+	unsigned int min_meta_chunk_width;
>+	unsigned int meta_chunk_width;
>+	unsigned int meta_chunk_per_row_int;
>+	unsigned int meta_row_remainder;
>+	unsigned int meta_chunk_threshold;
>+	unsigned int meta_blk_bytes;
>+	unsigned int meta_blk_height;
>+	unsigned int meta_blk_width;
>+	unsigned int meta_surface_bytes;
>+	unsigned int vmpg_bytes;
>+	unsigned int meta_pte_req_per_frame_ub;
>+	unsigned int meta_pte_bytes_per_frame_ub;
>+	const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
>+	const unsigned int dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma;
>+	const unsigned int pde_proc_buffer_size_64k_reqs =
>+			mode_lib->ip.pde_proc_buffer_size_64k_reqs;
>+
>+	unsigned int log2_vmpg_height = 0;
>+	unsigned int log2_vmpg_width = 0;
>+	unsigned int log2_dpte_req_height_ptes = 0;
>+	unsigned int log2_dpte_req_height = 0;
>+	unsigned int log2_dpte_req_width = 0;
>+	unsigned int log2_dpte_row_height_linear = 0;
>+	unsigned int log2_dpte_row_height = 0;
>+	unsigned int log2_dpte_group_width = 0;
>+	unsigned int dpte_row_width_ub = 0;
>+	unsigned int dpte_req_height = 0;
>+	unsigned int dpte_req_width = 0;
>+	unsigned int dpte_group_width = 0;
>+	unsigned int log2_dpte_group_bytes = 0;
>+	unsigned int log2_dpte_group_length = 0;
>+	unsigned int pde_buf_entries;
>+	bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10);
>+
>+	Calculate256BBlockSizes((enum source_format_class)(source_format),
>+			(enum dm_swizzle_mode)(tiling),
>+			bytes_per_element_y,
>+			bytes_per_element_c,
>+			&blk256_height_y,
>+			&blk256_height_c,
>+			&blk256_width_y,
>+			&blk256_width_c);
>+
>+	if (!is_chroma) {
>+		blk256_width = blk256_width_y;
>+		blk256_height = blk256_height_y;
>+		bytes_per_element = bytes_per_element_y;
>+	} else {
>+		blk256_width = blk256_width_c;
>+		blk256_height = blk256_height_c;
>+		bytes_per_element = bytes_per_element_c;
>+	}
>+
>+	log2_bytes_per_element = dml_log2(bytes_per_element);
>+
>+	dml_print("DML_DLG: %s: surf_linear        = %d\n", __func__, surf_linear);
>+	dml_print("DML_DLG: %s: surf_vert          = %d\n", __func__, surf_vert);
>+	dml_print("DML_DLG: %s: blk256_width       = %d\n", __func__, blk256_width);
>+	dml_print("DML_DLG: %s: blk256_height      = %d\n", __func__, blk256_height);
>+
>+	log2_blk256_width = dml_log2((double) blk256_width);
>+	log2_blk256_height = dml_log2((double) blk256_height);
>+	blk_bytes = surf_linear ?
>+			256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
>+	log2_blk_bytes = dml_log2((double) blk_bytes);
>+	log2_blk_height = 0;
>+	log2_blk_width = 0;
>+
>+	// remember log rule
>+	// "+" in log is multiply
>+	// "-" in log is divide
>+	// "/2" is like square root
>+	// blk is vertical biased
>+	if (tiling != dm_sw_linear)
>+		log2_blk_height = log2_blk256_height
>+				+ dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
>+	else
>+		log2_blk_height = 0;  // blk height of 1
>+
>+	log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
>+
>+	if (!surf_vert) {
>+		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
>+				+ blk256_width;
>+		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
>+	} else {
>+		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1)
>+				+ blk256_height;
>+		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
>+	}
>+
>+	if (!surf_vert)
>+		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
>+				* bytes_per_element;
>+	else
>+		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
>+				* bytes_per_element;
>+
>+	rq_misc_param->blk256_height = blk256_height;
>+	rq_misc_param->blk256_width = blk256_width;
>+
>+	// -------
>+	// meta
>+	// -------
>+	log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element
>+
>+	// each 64b meta request for dcn is 8x8 meta elements and
>+	// a meta element covers one 256b block of the the data surface.
>+	log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256
>+	log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
>+			- log2_meta_req_height;
>+	meta_req_width = 1 << log2_meta_req_width;
>+	meta_req_height = 1 << log2_meta_req_height;
>+	log2_meta_row_height = 0;
>+	meta_row_width_ub = 0;
>+
>+	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.
>+	// calculate upper bound of the meta_row_width
>+	if (!surf_vert) {
>+		log2_meta_row_height = log2_meta_req_height;
>+		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
>+				+ meta_req_width;
>+		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
>+	} else {
>+		log2_meta_row_height = log2_meta_req_width;
>+		meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1)
>+				+ meta_req_height;
>+		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
>+	}
>+	rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
>+
>+	rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
>+
>+	log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
>+	log2_meta_chunk_height = log2_meta_row_height;
>+
>+	//full sized meta chunk width in unit of data elements
>+	log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element
>+			- log2_meta_chunk_height;
>+	log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
>+	min_meta_chunk_width = 1
>+			<< (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element
>+					- log2_meta_chunk_height);
>+	meta_chunk_width = 1 << log2_meta_chunk_width;
>+	meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
>+	meta_row_remainder = meta_row_width_ub % meta_chunk_width;
>+	meta_chunk_threshold = 0;
>+	meta_blk_bytes = 4096;
>+	meta_blk_height = blk256_height * 64;
>+	meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height;
>+	meta_surface_bytes = meta_pitch
>+			* (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height)
>+			* bytes_per_element / 256;
>+	vmpg_bytes = mode_lib->soc.vmm_page_size_bytes;
>+	meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes,
>+			8 * vmpg_bytes,
>+			1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
>+	meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request
>+	rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
>+
>+	dml_print("DML_DLG: %s: meta_blk_height             = %d\n", __func__, meta_blk_height);
>+	dml_print("DML_DLG: %s: meta_blk_width              = %d\n", __func__, meta_blk_width);
>+	dml_print("DML_DLG: %s: meta_surface_bytes          = %d\n", __func__, meta_surface_bytes);
>+	dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub   = %d\n",
>+			__func__,
>+			meta_pte_req_per_frame_ub);
>+	dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",
>+			__func__,
>+			meta_pte_bytes_per_frame_ub);
>+
>+	if (!surf_vert)
>+		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
>+	else
>+		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
>+
>+	if (meta_row_remainder <= meta_chunk_threshold)
>+		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
>+	else
>+		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
>+
>+	// ------
>+	// dpte
>+	// ------
>+	if (surf_linear) {
>+		log2_vmpg_height = 0;   // one line high
>+	} else {
>+		log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
>+	}
>+	log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
>+
>+	// only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
>+	if (surf_linear) { //one 64B PTE request returns 8 PTEs
>+		log2_dpte_req_height_ptes = 0;
>+		log2_dpte_req_width = log2_vmpg_width + 3;
>+		log2_dpte_req_height = 0;
>+	} else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
>+		//one 64B req gives 8x1 PTEs for 4KB tile
>+		log2_dpte_req_height_ptes = 0;
>+		log2_dpte_req_width = log2_blk_width + 3;
>+		log2_dpte_req_height = log2_blk_height + 0;
>+	} else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
>+		//two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
>+		log2_dpte_req_height_ptes = 4;
>+		log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width
>+		log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height
>+	} else { //64KB page size and must 64KB tile block
>+		 //one 64B req gives 8x1 PTEs for 64KB tile
>+		log2_dpte_req_height_ptes = 0;
>+		log2_dpte_req_width = log2_blk_width + 3;
>+		log2_dpte_req_height = log2_blk_height + 0;
>+	}
>+
>+	// The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
>+	// log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
>+	// That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
>+	//log2_dpte_req_height    = log2_vmpg_height + log2_dpte_req_height_ptes;
>+	//log2_dpte_req_width     = log2_vmpg_width + log2_dpte_req_width_ptes;
>+	dpte_req_height = 1 << log2_dpte_req_height;
>+	dpte_req_width = 1 << log2_dpte_req_width;
>+
>+	// calculate pitch dpte row buffer can hold
>+	// round the result down to a power of two.
>+	pde_buf_entries = yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs;
>+	if (surf_linear) {
>+		unsigned int dpte_row_height;
>+
>+		log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries
>+										/ bytes_per_element,
>+								dpte_buf_in_pte_reqs
>+										* dpte_req_width)
>+								/ data_pitch),
>+				1);
>+
>+		ASSERT(log2_dpte_row_height_linear >= 3);
>+
>+		if (log2_dpte_row_height_linear > 7)
>+			log2_dpte_row_height_linear = 7;
>+
>+		log2_dpte_row_height = log2_dpte_row_height_linear;
>+		// For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
>+		// the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
>+		dpte_row_height = 1 << log2_dpte_row_height;
>+		dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
>+				dpte_req_width,
>+				1) + dpte_req_width;
>+		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
>+	} else {
>+		// the upper bound of the dpte_row_width without dependency on viewport position follows.
>+		// for tiled mode, row height is the same as req height and row store up to vp size upper bound
>+		if (!surf_vert) {
>+			log2_dpte_row_height = log2_dpte_req_height;
>+			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
>+					+ dpte_req_width;
>+			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
>+		} else {
>+			log2_dpte_row_height =
>+					(log2_blk_width < log2_dpte_req_width) ?
>+							log2_blk_width : log2_dpte_req_width;
>+			dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
>+					+ dpte_req_height;
>+			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
>+		}
>+	}
>+	if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
>+		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
>+	else
>+		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
>+
>+	rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
>+
>+	// the dpte_group_bytes is reduced for the specific case of vertical
>+	// access of a tile surface that has dpte request of 8x1 ptes.
>+	if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
>+		rq_sizing_param->dpte_group_bytes = 512;
>+	else
>+		//full size
>+		rq_sizing_param->dpte_group_bytes = 2048;
>+
>+	//since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
>+	log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
>+	log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
>+
>+	// full sized data pte group width in elements
>+	if (!surf_vert)
>+		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
>+	else
>+		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
>+
>+	//But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
>+	if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
>+		log2_dpte_group_width = log2_dpte_group_width - 1;
>+
>+	dpte_group_width = 1 << log2_dpte_group_width;
>+
>+	// since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
>+	// the upper bound for the dpte groups per row is as follows.
>+	rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
>+			1);
>+}
>+
>+static void get_surf_rq_param(struct display_mode_lib *mode_lib,
>+		display_data_rq_sizing_params_st *rq_sizing_param,
>+		display_data_rq_dlg_params_st *rq_dlg_param,
>+		display_data_rq_misc_params_st *rq_misc_param,
>+		const display_pipe_source_params_st pipe_src_param,
>+		bool is_chroma)
>+{
>+	bool mode_422 = 0;
>+	unsigned int vp_width = 0;
>+	unsigned int vp_height = 0;
>+	unsigned int data_pitch = 0;
>+	unsigned int meta_pitch = 0;
>+	unsigned int ppe = mode_422 ? 2 : 1;
>+
>+	// FIXME check if ppe apply for both luma and chroma in 422 case
>+	if (is_chroma) {
>+		vp_width = pipe_src_param.viewport_width_c / ppe;
>+		vp_height = pipe_src_param.viewport_height_c;
>+		data_pitch = pipe_src_param.data_pitch_c;
>+		meta_pitch = pipe_src_param.meta_pitch_c;
>+	} else {
>+		vp_width = pipe_src_param.viewport_width / ppe;
>+		vp_height = pipe_src_param.viewport_height;
>+		data_pitch = pipe_src_param.data_pitch;
>+		meta_pitch = pipe_src_param.meta_pitch;
>+	}
>+
>+	rq_sizing_param->chunk_bytes = 8192;
>+
>+	if (rq_sizing_param->chunk_bytes == 64 * 1024)
>+		rq_sizing_param->min_chunk_bytes = 0;
>+	else
>+		rq_sizing_param->min_chunk_bytes = 1024;
>+
>+	rq_sizing_param->meta_chunk_bytes = 2048;
>+	rq_sizing_param->min_meta_chunk_bytes = 256;
>+
>+	rq_sizing_param->mpte_group_bytes = 2048;
>+
>+	get_meta_and_pte_attr(mode_lib,
>+			rq_dlg_param,
>+			rq_misc_param,
>+			rq_sizing_param,
>+			vp_width,
>+			vp_height,
>+			data_pitch,
>+			meta_pitch,
>+			pipe_src_param.source_format,
>+			pipe_src_param.sw_mode,
>+			pipe_src_param.macro_tile_size,
>+			pipe_src_param.source_scan,
>+			is_chroma);
>+}
>+
>+static void dml20v2_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,
>+		display_rq_params_st *rq_param,
>+		const display_pipe_source_params_st pipe_src_param)
>+{
>+	// get param for luma surface
>+	rq_param->yuv420 = pipe_src_param.source_format == dm_420_8
>+			|| pipe_src_param.source_format == dm_420_10;
>+	rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;
>+
>+	get_surf_rq_param(mode_lib,
>+			&(rq_param->sizing.rq_l),
>+			&(rq_param->dlg.rq_l),
>+			&(rq_param->misc.rq_l),
>+			pipe_src_param,
>+			0);
>+
>+	if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) {
>+		// get param for chroma surface
>+		get_surf_rq_param(mode_lib,
>+				&(rq_param->sizing.rq_c),
>+				&(rq_param->dlg.rq_c),
>+				&(rq_param->misc.rq_c),
>+				pipe_src_param,
>+				1);
>+	}
>+
>+	// calculate how to split the det buffer space between luma and chroma
>+	handle_det_buf_split(mode_lib, rq_param, pipe_src_param);
>+	print__rq_params_st(mode_lib, *rq_param);
>+}
>+
>+void dml20v2_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
>+		display_rq_regs_st *rq_regs,
>+		const display_pipe_params_st pipe_param)
>+{
>+	display_rq_params_st rq_param = {0};
>+
>+	memset(rq_regs, 0, sizeof(*rq_regs));
>+	dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param.src);
>+	extract_rq_regs(mode_lib, rq_regs, rq_param);
>+
>+	print__rq_regs_st(mode_lib, *rq_regs);
>+}
>+
>+// Note: currently taken in as is.
>+// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
>+static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
>+		const display_e2e_pipe_params_st *e2e_pipe_param,
>+		const unsigned int num_pipes,
>+		const unsigned int pipe_idx,
>+		display_dlg_regs_st *disp_dlg_regs,
>+		display_ttu_regs_st *disp_ttu_regs,
>+		const display_rq_dlg_params_st rq_dlg_param,
>+		const display_dlg_sys_params_st dlg_sys_param,
>+		const bool cstate_en,
>+		const bool pstate_en)
>+{
>+	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
>+	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
>+	const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
>+	const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
>+	const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
>+	const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
>+
>+	// -------------------------
>+	// Section 1.15.2.1: OTG dependent Params
>+	// -------------------------
>+	// Timing
>+	unsigned int htotal = dst->htotal;
>+//    unsigned int hblank_start = dst.hblank_start; // TODO: Remove
>+	unsigned int hblank_end = dst->hblank_end;
>+	unsigned int vblank_start = dst->vblank_start;
>+	unsigned int vblank_end = dst->vblank_end;
>+	unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
>+
>+	double dppclk_freq_in_mhz = clks->dppclk_mhz;
>+	double dispclk_freq_in_mhz = clks->dispclk_mhz;
>+	double refclk_freq_in_mhz = clks->refclk_mhz;
>+	double pclk_freq_in_mhz = dst->pixel_rate_mhz;
>+	bool interlaced = dst->interlaced;
>+
>+	double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
>+
>+	double min_dcfclk_mhz;
>+	double t_calc_us;
>+	double min_ttu_vblank;
>+
>+	double min_dst_y_ttu_vblank;
>+	unsigned int dlg_vblank_start;
>+	bool dual_plane;
>+	bool mode_422;
>+	unsigned int access_dir;
>+	unsigned int vp_height_l;
>+	unsigned int vp_width_l;
>+	unsigned int vp_height_c;
>+	unsigned int vp_width_c;
>+
>+	// Scaling
>+	unsigned int htaps_l;
>+	unsigned int htaps_c;
>+	double hratio_l;
>+	double hratio_c;
>+	double vratio_l;
>+	double vratio_c;
>+	bool scl_enable;
>+
>+	double line_time_in_us;
>+	//    double vinit_l;
>+	//    double vinit_c;
>+	//    double vinit_bot_l;
>+	//    double vinit_bot_c;
>+
>+	//    unsigned int swath_height_l;
>+	unsigned int swath_width_ub_l;
>+	//    unsigned int dpte_bytes_per_row_ub_l;
>+	unsigned int dpte_groups_per_row_ub_l;
>+	//    unsigned int meta_pte_bytes_per_frame_ub_l;
>+	//    unsigned int meta_bytes_per_row_ub_l;
>+
>+	//    unsigned int swath_height_c;
>+	unsigned int swath_width_ub_c;
>+	//   unsigned int dpte_bytes_per_row_ub_c;
>+	unsigned int dpte_groups_per_row_ub_c;
>+
>+	unsigned int meta_chunks_per_row_ub_l;
>+	unsigned int meta_chunks_per_row_ub_c;
>+	unsigned int vupdate_offset;
>+	unsigned int vupdate_width;
>+	unsigned int vready_offset;
>+
>+	unsigned int dppclk_delay_subtotal;
>+	unsigned int dispclk_delay_subtotal;
>+	unsigned int pixel_rate_delay_subtotal;
>+
>+	unsigned int vstartup_start;
>+	unsigned int dst_x_after_scaler;
>+	unsigned int dst_y_after_scaler;
>+	double line_wait;
>+	double dst_y_prefetch;
>+	double dst_y_per_vm_vblank;
>+	double dst_y_per_row_vblank;
>+	double dst_y_per_vm_flip;
>+	double dst_y_per_row_flip;
>+	double min_dst_y_per_vm_vblank;
>+	double min_dst_y_per_row_vblank;
>+	double lsw;
>+	double vratio_pre_l;
>+	double vratio_pre_c;
>+	unsigned int req_per_swath_ub_l;
>+	unsigned int req_per_swath_ub_c;
>+	unsigned int meta_row_height_l;
>+	unsigned int meta_row_height_c;
>+	unsigned int swath_width_pixels_ub_l;
>+	unsigned int swath_width_pixels_ub_c;
>+	unsigned int scaler_rec_in_width_l;
>+	unsigned int scaler_rec_in_width_c;
>+	unsigned int dpte_row_height_l;
>+	unsigned int dpte_row_height_c;
>+	double hscale_pixel_rate_l;
>+	double hscale_pixel_rate_c;
>+	double min_hratio_fact_l;
>+	double min_hratio_fact_c;
>+	double refcyc_per_line_delivery_pre_l;
>+	double refcyc_per_line_delivery_pre_c;
>+	double refcyc_per_line_delivery_l;
>+	double refcyc_per_line_delivery_c;
>+
>+	double refcyc_per_req_delivery_pre_l;
>+	double refcyc_per_req_delivery_pre_c;
>+	double refcyc_per_req_delivery_l;
>+	double refcyc_per_req_delivery_c;
>+
>+	unsigned int full_recout_width;
>+	double xfc_transfer_delay;
>+	double xfc_precharge_delay;
>+	double xfc_remote_surface_flip_latency;
>+	double xfc_dst_y_delta_drq_limit;
>+	double xfc_prefetch_margin;
>+	double refcyc_per_req_delivery_pre_cur0;
>+	double refcyc_per_req_delivery_cur0;
>+	double refcyc_per_req_delivery_pre_cur1;
>+	double refcyc_per_req_delivery_cur1;
>+
>+	memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
>+	memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
>+
>+	dml_print("DML_DLG: %s:  cstate_en = %d\n", __func__, cstate_en);
>+	dml_print("DML_DLG: %s:  pstate_en = %d\n", __func__, pstate_en);
>+
>+	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
>+	dml_print("DML_DLG: %s: dispclk_freq_in_mhz    = %3.2f\n", __func__, dispclk_freq_in_mhz);
>+	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
>+	dml_print("DML_DLG: %s: pclk_freq_in_mhz       = %3.2f\n", __func__, pclk_freq_in_mhz);
>+	dml_print("DML_DLG: %s: interlaced             = %d\n", __func__, interlaced);
>+	ASSERT(ref_freq_to_pix_freq < 4.0);
>+
>+	disp_dlg_regs->ref_freq_to_pix_freq =
>+			(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
>+	disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
>+			* dml_pow(2, 8));
>+	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
>+	disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end
>+			* (double) ref_freq_to_pix_freq);
>+	ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
>+
>+	min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
>+	t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes);
>+	min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+
>+	min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
>+	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
>+
>+	disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
>+			+ min_dst_y_ttu_vblank) * dml_pow(2, 2));
>+	ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
>+
>+	dml_print("DML_DLG: %s: min_dcfclk_mhz                         = %3.2f\n",
>+			__func__,
>+			min_dcfclk_mhz);
>+	dml_print("DML_DLG: %s: min_ttu_vblank                         = %3.2f\n",
>+			__func__,
>+			min_ttu_vblank);
>+	dml_print("DML_DLG: %s: min_dst_y_ttu_vblank                   = %3.2f\n",
>+			__func__,
>+			min_dst_y_ttu_vblank);
>+	dml_print("DML_DLG: %s: t_calc_us                              = %3.2f\n",
>+			__func__,
>+			t_calc_us);
>+	dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start    = 0x%0x\n",
>+			__func__,
>+			disp_dlg_regs->min_dst_y_next_start);
>+	dml_print("DML_DLG: %s: ref_freq_to_pix_freq                   = %3.2f\n",
>+			__func__,
>+			ref_freq_to_pix_freq);
>+
>+	// -------------------------
>+	// Section 1.15.2.2: Prefetch, Active and TTU
>+	// -------------------------
>+	// Prefetch Calc
>+	// Source
>+//             dcc_en              = src.dcc;
>+	dual_plane = is_dual_plane((enum source_format_class)(src->source_format));
>+	mode_422 = 0; // FIXME
>+	access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
>+//      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);
>+//      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);
>+	vp_height_l = src->viewport_height;
>+	vp_width_l = src->viewport_width;
>+	vp_height_c = src->viewport_height_c;
>+	vp_width_c = src->viewport_width_c;
>+
>+	// Scaling
>+	htaps_l = taps->htaps;
>+	htaps_c = taps->htaps_c;
>+	hratio_l = scl->hscl_ratio;
>+	hratio_c = scl->hscl_ratio_c;
>+	vratio_l = scl->vscl_ratio;
>+	vratio_c = scl->vscl_ratio_c;
>+	scl_enable = scl->scl_enable;
>+
>+	line_time_in_us = (htotal / pclk_freq_in_mhz);
>+//     vinit_l         = scl.vinit;
>+//     vinit_c         = scl.vinit_c;
>+//     vinit_bot_l     = scl.vinit_bot;
>+//     vinit_bot_c     = scl.vinit_bot_c;
>+
>+//    unsigned int swath_height_l                 = rq_dlg_param.rq_l.swath_height;
>+	swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
>+//    unsigned int dpte_bytes_per_row_ub_l        = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;
>+	dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
>+//    unsigned int meta_pte_bytes_per_frame_ub_l  = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;
>+//    unsigned int meta_bytes_per_row_ub_l        = rq_dlg_param.rq_l.meta_bytes_per_row_ub;
>+
>+//    unsigned int swath_height_c                 = rq_dlg_param.rq_c.swath_height;
>+	swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
>+	//   dpte_bytes_per_row_ub_c        = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;
>+	dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
>+
>+	meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
>+	meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;
>+	vupdate_offset = dst->vupdate_offset;
>+	vupdate_width = dst->vupdate_width;
>+	vready_offset = dst->vready_offset;
>+
>+	dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
>+	dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
>+
>+	if (scl_enable)
>+		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
>+	else
>+		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
>+
>+	dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter
>+			+ src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
>+
>+	if (dout->dsc_enable) {
>+		double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+
>+		dispclk_delay_subtotal += dsc_delay;
>+	}
>+
>+	pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz
>+			+ dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
>+
>+	vstartup_start = dst->vstartup_start;
>+	if (interlaced) {
>+		if (vstartup_start / 2.0
>+				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
>+				<= vblank_end / 2.0)
>+			disp_dlg_regs->vready_after_vcount0 = 1;
>+		else
>+			disp_dlg_regs->vready_after_vcount0 = 0;
>+	} else {
>+		if (vstartup_start
>+				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
>+				<= vblank_end)
>+			disp_dlg_regs->vready_after_vcount0 = 1;
>+		else
>+			disp_dlg_regs->vready_after_vcount0 = 0;
>+	}
>+
>+	// TODO: Where is this coming from?
>+	if (interlaced)
>+		vstartup_start = vstartup_start / 2;
>+
>+	// TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp?
>+	if (vstartup_start >= min_vblank) {
>+		dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
>+				__func__,
>+				vblank_start,
>+				vblank_end);
>+		dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
>+				__func__,
>+				vstartup_start,
>+				min_vblank);
>+		min_vblank = vstartup_start + 1;
>+		dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
>+				__func__,
>+				vstartup_start,
>+				min_vblank);
>+	}
>+
>+	dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+	dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+
>+	dml_print("DML_DLG: %s: htotal                                 = %d\n", __func__, htotal);
>+	dml_print("DML_DLG: %s: pixel_rate_delay_subtotal              = %d\n",
>+			__func__,
>+			pixel_rate_delay_subtotal);
>+	dml_print("DML_DLG: %s: dst_x_after_scaler                     = %d\n",
>+			__func__,
>+			dst_x_after_scaler);
>+	dml_print("DML_DLG: %s: dst_y_after_scaler                     = %d\n",
>+			__func__,
>+			dst_y_after_scaler);
>+
>+	// Lwait
>+	line_wait = mode_lib->soc.urgent_latency_us;
>+	if (cstate_en)
>+		line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
>+	if (pstate_en)
>+		line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us
>+						+ mode_lib->soc.urgent_latency_us,
>+				line_wait);
>+	line_wait = line_wait / line_time_in_us;
>+
>+	dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+	dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
>+
>+	dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib,
>+			e2e_pipe_param,
>+			num_pipes,
>+			pipe_idx);
>+	dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib,
>+			e2e_pipe_param,
>+			num_pipes,
>+			pipe_idx);
>+	dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+	dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+
>+	min_dst_y_per_vm_vblank = 8.0;
>+	min_dst_y_per_row_vblank = 16.0;
>+
>+	// magic!
>+	if (htotal <= 75) {
>+		min_vblank = 300;
>+		min_dst_y_per_vm_vblank = 100.0;
>+		min_dst_y_per_row_vblank = 100.0;
>+	}
>+
>+	dml_print("DML_DLG: %s: dst_y_per_vm_vblank    = %3.2f\n", __func__, dst_y_per_vm_vblank);
>+	dml_print("DML_DLG: %s: dst_y_per_row_vblank   = %3.2f\n", __func__, dst_y_per_row_vblank);
>+
>+	ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);
>+	ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);
>+
>+	ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
>+	lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank);
>+
>+	dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw);
>+
>+	vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+	vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+
>+	dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l);
>+	dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c);
>+
>+	// Active
>+	req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
>+	req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
>+	meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
>+	meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;
>+	swath_width_pixels_ub_l = 0;
>+	swath_width_pixels_ub_c = 0;
>+	scaler_rec_in_width_l = 0;
>+	scaler_rec_in_width_c = 0;
>+	dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
>+	dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
>+
>+	if (mode_422) {
>+		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element
>+		swath_width_pixels_ub_c = swath_width_ub_c * 2;
>+	} else {
>+		swath_width_pixels_ub_l = swath_width_ub_l * 1;
>+		swath_width_pixels_ub_c = swath_width_ub_c * 1;
>+	}
>+
>+	hscale_pixel_rate_l = 0.;
>+	hscale_pixel_rate_c = 0.;
>+	min_hratio_fact_l = 1.0;
>+	min_hratio_fact_c = 1.0;
>+
>+	if (htaps_l <= 1)
>+		min_hratio_fact_l = 2.0;
>+	else if (htaps_l <= 6) {
>+		if ((hratio_l * 2.0) > 4.0)
>+			min_hratio_fact_l = 4.0;
>+		else
>+			min_hratio_fact_l = hratio_l * 2.0;
>+	} else {
>+		if (hratio_l > 4.0)
>+			min_hratio_fact_l = 4.0;
>+		else
>+			min_hratio_fact_l = hratio_l;
>+	}
>+
>+	hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
>+
>+	if (htaps_c <= 1)
>+		min_hratio_fact_c = 2.0;
>+	else if (htaps_c <= 6) {
>+		if ((hratio_c * 2.0) > 4.0)
>+			min_hratio_fact_c = 4.0;
>+		else
>+			min_hratio_fact_c = hratio_c * 2.0;
>+	} else {
>+		if (hratio_c > 4.0)
>+			min_hratio_fact_c = 4.0;
>+		else
>+			min_hratio_fact_c = hratio_c;
>+	}
>+
>+	hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
>+
>+	refcyc_per_line_delivery_pre_l = 0.;
>+	refcyc_per_line_delivery_pre_c = 0.;
>+	refcyc_per_line_delivery_l = 0.;
>+	refcyc_per_line_delivery_c = 0.;
>+
>+	refcyc_per_req_delivery_pre_l = 0.;
>+	refcyc_per_req_delivery_pre_c = 0.;
>+	refcyc_per_req_delivery_l = 0.;
>+	refcyc_per_req_delivery_c = 0.;
>+
>+	full_recout_width = 0;
>+	// In ODM
>+	if (src->is_hsplit) {
>+		// This "hack"  is only allowed (and valid) for MPC combine. In ODM
>+		// combine, you MUST specify the full_recout_width...according to Oswin
>+		if (dst->full_recout_width == 0 && !dst->odm_combine) {
>+			dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",
>+					__func__);
>+			full_recout_width = dst->recout_width * 2; // assume half split for dcn1
>+		} else
>+			full_recout_width = dst->full_recout_width;
>+	} else
>+		full_recout_width = dst->recout_width;
>+
>+	// As of DCN2, mpc_combine and odm_combine are mutually exclusive
>+	refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib,
>+			refclk_freq_in_mhz,
>+			pclk_freq_in_mhz,
>+			dst->odm_combine,
>+			full_recout_width,
>+			dst->hactive,
>+			vratio_pre_l,
>+			hscale_pixel_rate_l,
>+			swath_width_pixels_ub_l,
>+			1); // per line
>+
>+	refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib,
>+			refclk_freq_in_mhz,
>+			pclk_freq_in_mhz,
>+			dst->odm_combine,
>+			full_recout_width,
>+			dst->hactive,
>+			vratio_l,
>+			hscale_pixel_rate_l,
>+			swath_width_pixels_ub_l,
>+			1); // per line
>+
>+	dml_print("DML_DLG: %s: full_recout_width              = %d\n",
>+			__func__,
>+			full_recout_width);
>+	dml_print("DML_DLG: %s: hscale_pixel_rate_l            = %3.2f\n",
>+			__func__,
>+			hscale_pixel_rate_l);
>+	dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",
>+			__func__,
>+			refcyc_per_line_delivery_pre_l);
>+	dml_print("DML_DLG: %s: refcyc_per_line_delivery_l     = %3.2f\n",
>+			__func__,
>+			refcyc_per_line_delivery_l);
>+
>+	if (dual_plane) {
>+		refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib,
>+				refclk_freq_in_mhz,
>+				pclk_freq_in_mhz,
>+				dst->odm_combine,
>+				full_recout_width,
>+				dst->hactive,
>+				vratio_pre_c,
>+				hscale_pixel_rate_c,
>+				swath_width_pixels_ub_c,
>+				1); // per line
>+
>+		refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib,
>+				refclk_freq_in_mhz,
>+				pclk_freq_in_mhz,
>+				dst->odm_combine,
>+				full_recout_width,
>+				dst->hactive,
>+				vratio_c,
>+				hscale_pixel_rate_c,
>+				swath_width_pixels_ub_c,
>+				1);  // per line
>+
>+		dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",
>+				__func__,
>+				refcyc_per_line_delivery_pre_c);
>+		dml_print("DML_DLG: %s: refcyc_per_line_delivery_c     = %3.2f\n",
>+				__func__,
>+				refcyc_per_line_delivery_c);
>+	}
>+
>+	// TTU - Luma / Chroma
>+	if (access_dir) {  // vertical access
>+		scaler_rec_in_width_l = vp_height_l;
>+		scaler_rec_in_width_c = vp_height_c;
>+	} else {
>+		scaler_rec_in_width_l = vp_width_l;
>+		scaler_rec_in_width_c = vp_width_c;
>+	}
>+
>+	refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib,
>+			refclk_freq_in_mhz,
>+			pclk_freq_in_mhz,
>+			dst->odm_combine,
>+			full_recout_width,
>+			dst->hactive,
>+			vratio_pre_l,
>+			hscale_pixel_rate_l,
>+			scaler_rec_in_width_l,
>+			req_per_swath_ub_l);  // per req
>+	refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib,
>+			refclk_freq_in_mhz,
>+			pclk_freq_in_mhz,
>+			dst->odm_combine,
>+			full_recout_width,
>+			dst->hactive,
>+			vratio_l,
>+			hscale_pixel_rate_l,
>+			scaler_rec_in_width_l,
>+			req_per_swath_ub_l);  // per req
>+
>+	dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",
>+			__func__,
>+			refcyc_per_req_delivery_pre_l);
>+	dml_print("DML_DLG: %s: refcyc_per_req_delivery_l     = %3.2f\n",
>+			__func__,
>+			refcyc_per_req_delivery_l);
>+
>+	ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
>+	ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
>+
>+	if (dual_plane) {
>+		refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib,
>+				refclk_freq_in_mhz,
>+				pclk_freq_in_mhz,
>+				dst->odm_combine,
>+				full_recout_width,
>+				dst->hactive,
>+				vratio_pre_c,
>+				hscale_pixel_rate_c,
>+				scaler_rec_in_width_c,
>+				req_per_swath_ub_c);  // per req
>+		refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib,
>+				refclk_freq_in_mhz,
>+				pclk_freq_in_mhz,
>+				dst->odm_combine,
>+				full_recout_width,
>+				dst->hactive,
>+				vratio_c,
>+				hscale_pixel_rate_c,
>+				scaler_rec_in_width_c,
>+				req_per_swath_ub_c);  // per req
>+
>+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",
>+				__func__,
>+				refcyc_per_req_delivery_pre_c);
>+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_c     = %3.2f\n",
>+				__func__,
>+				refcyc_per_req_delivery_c);
>+
>+		ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
>+		ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
>+	}
>+
>+	// XFC
>+	xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+	xfc_precharge_delay = get_xfc_precharge_delay(mode_lib,
>+			e2e_pipe_param,
>+			num_pipes,
>+			pipe_idx);
>+	xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(mode_lib,
>+			e2e_pipe_param,
>+			num_pipes,
>+			pipe_idx);
>+	xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;
>+	xfc_prefetch_margin = get_xfc_prefetch_margin(mode_lib,
>+			e2e_pipe_param,
>+			num_pipes,
>+			pipe_idx);
>+
>+	// TTU - Cursor
>+	refcyc_per_req_delivery_pre_cur0 = 0.0;
>+	refcyc_per_req_delivery_cur0 = 0.0;
>+	if (src->num_cursors > 0) {
>+		calculate_ttu_cursor(mode_lib,
>+				&refcyc_per_req_delivery_pre_cur0,
>+				&refcyc_per_req_delivery_cur0,
>+				refclk_freq_in_mhz,
>+				ref_freq_to_pix_freq,
>+				hscale_pixel_rate_l,
>+				scl->hscl_ratio,
>+				vratio_pre_l,
>+				vratio_l,
>+				src->cur0_src_width,
>+				(enum cursor_bpp)(src->cur0_bpp));
>+	}
>+
>+	refcyc_per_req_delivery_pre_cur1 = 0.0;
>+	refcyc_per_req_delivery_cur1 = 0.0;
>+	if (src->num_cursors > 1) {
>+		calculate_ttu_cursor(mode_lib,
>+				&refcyc_per_req_delivery_pre_cur1,
>+				&refcyc_per_req_delivery_cur1,
>+				refclk_freq_in_mhz,
>+				ref_freq_to_pix_freq,
>+				hscale_pixel_rate_l,
>+				scl->hscl_ratio,
>+				vratio_pre_l,
>+				vratio_l,
>+				src->cur1_src_width,
>+				(enum cursor_bpp)(src->cur1_bpp));
>+	}
>+
>+	// TTU - Misc
>+	// all hard-coded
>+
>+	// Assignment to register structures
>+	disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
>+	disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
>+	ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));
>+	disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
>+	disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
>+	disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
>+	disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
>+	disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
>+
>+	disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
>+	disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
>+
>+	disp_dlg_regs->refcyc_per_pte_group_vblank_l =
>+			(unsigned int) (dst_y_per_row_vblank * (double) htotal
>+					* ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
>+	ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));
>+
>+	if (dual_plane) {
>+		disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank
>+				* (double) htotal * ref_freq_to_pix_freq
>+				/ (double) dpte_groups_per_row_ub_c);
>+		ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
>+						< (unsigned int) dml_pow(2, 13));
>+	}
>+
>+	disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
>+			(unsigned int) (dst_y_per_row_vblank * (double) htotal
>+					* ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
>+	ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
>+
>+	disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
>+			disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
>+
>+	disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
>+			* ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
>+	disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
>+			* ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
>+
>+	if (dual_plane) {
>+		disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip
>+				* htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
>+		disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip
>+				* htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
>+	}
>+
>+	disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l
>+			/ (double) vratio_l * dml_pow(2, 2));
>+	ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));
>+
>+	if (dual_plane) {
>+		disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c
>+				/ (double) vratio_c * dml_pow(2, 2));
>+		if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
>+			dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
>+					__func__,
>+					disp_dlg_regs->dst_y_per_pte_row_nom_c,
>+					(unsigned int) dml_pow(2, 17) - 1);
>+		}
>+	}
>+
>+	disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
>+			/ (double) vratio_l * dml_pow(2, 2));
>+	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
>+
>+	disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
>+
>+	disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l
>+			/ (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
>+			/ (double) dpte_groups_per_row_ub_l);
>+	if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
>+		disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
>+	disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l
>+			/ (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
>+			/ (double) meta_chunks_per_row_ub_l);
>+	if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
>+		disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
>+
>+	if (dual_plane) {
>+		disp_dlg_regs->refcyc_per_pte_group_nom_c =
>+				(unsigned int) ((double) dpte_row_height_c / (double) vratio_c
>+						* (double) htotal * ref_freq_to_pix_freq
>+						/ (double) dpte_groups_per_row_ub_c);
>+		if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
>+			disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
>+
>+		// TODO: Is this the right calculation? Does htotal need to be halved?
>+		disp_dlg_regs->refcyc_per_meta_chunk_nom_c =
>+				(unsigned int) ((double) meta_row_height_c / (double) vratio_c
>+						* (double) htotal * ref_freq_to_pix_freq
>+						/ (double) meta_chunks_per_row_ub_c);
>+		if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
>+			disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
>+	}
>+
>+	disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l,
>+			1);
>+	disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l,
>+			1);
>+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
>+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));
>+
>+	disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c,
>+			1);
>+	disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c,
>+			1);
>+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));
>+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));
>+
>+	disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
>+	disp_dlg_regs->dst_y_offset_cur0 = 0;
>+	disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
>+	disp_dlg_regs->dst_y_offset_cur1 = 0;
>+
>+	disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay;
>+	disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay;
>+	disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency;
>+	disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz,
>+			1);
>+
>+	// slave has to have this value also set to off
>+	if (src->xfc_enable && !src->xfc_slave)
>+		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
>+	else
>+		disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
>+
>+	disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
>+			* dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
>+			* dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c
>+			* dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
>+			* dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
>+			(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0
>+			* dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 =
>+			(unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1
>+			* dml_pow(2, 10));
>+	disp_ttu_regs->qos_level_low_wm = 0;
>+	ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
>+	disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
>+			* ref_freq_to_pix_freq);
>+	/*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/
>+
>+	disp_ttu_regs->qos_level_flip = 14;
>+	disp_ttu_regs->qos_level_fixed_l = 8;
>+	disp_ttu_regs->qos_level_fixed_c = 8;
>+	disp_ttu_regs->qos_level_fixed_cur0 = 8;
>+	disp_ttu_regs->qos_ramp_disable_l = 0;
>+	disp_ttu_regs->qos_ramp_disable_c = 0;
>+	disp_ttu_regs->qos_ramp_disable_cur0 = 0;
>+
>+	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
>+	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
>+
>+	print__ttu_regs_st(mode_lib, *disp_ttu_regs);
>+	print__dlg_regs_st(mode_lib, *disp_dlg_regs);
>+}
>+
>+void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
>+		display_dlg_regs_st *dlg_regs,
>+		display_ttu_regs_st *ttu_regs,
>+		display_e2e_pipe_params_st *e2e_pipe_param,
>+		const unsigned int num_pipes,
>+		const unsigned int pipe_idx,
>+		const bool cstate_en,
>+		const bool pstate_en,
>+		const bool vm_en,
>+		const bool ignore_viewport_pos,
>+		const bool immediate_flip_support)
>+{
>+	display_rq_params_st rq_param = {0};
>+	display_dlg_sys_params_st dlg_sys_param = {0};
>+
>+	// Get watermark and Tex.
>+	dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
>+	dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib,
>+			e2e_pipe_param,
>+			num_pipes);
>+	dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
>+	dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
>+	dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
>+	dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
>+	dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib,
>+			e2e_pipe_param,
>+			num_pipes);
>+	dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib,
>+			e2e_pipe_param,
>+			num_pipes);
>+	dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
>+			/ dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
>+
>+	print__dlg_sys_params_st(mode_lib, dlg_sys_param);
>+
>+	// system parameter calculation done
>+
>+	dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
>+	dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src);
>+	dml20v2_rq_dlg_get_dlg_params(mode_lib,
>+			e2e_pipe_param,
>+			num_pipes,
>+			pipe_idx,
>+			dlg_regs,
>+			ttu_regs,
>+			rq_param.dlg,
>+			dlg_sys_param,
>+			cstate_en,
>+			pstate_en);
>+	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
>+}
>+
>+static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
>+		double *refcyc_per_req_delivery_pre_cur,
>+		double *refcyc_per_req_delivery_cur,
>+		double refclk_freq_in_mhz,
>+		double ref_freq_to_pix_freq,
>+		double hscale_pixel_rate_l,
>+		double hscl_ratio,
>+		double vratio_pre_l,
>+		double vratio_l,
>+		unsigned int cur_width,
>+		enum cursor_bpp cur_bpp)
>+{
>+	unsigned int cur_src_width = cur_width;
>+	unsigned int cur_req_size = 0;
>+	unsigned int cur_req_width = 0;
>+	double cur_width_ub = 0.0;
>+	double cur_req_per_width = 0.0;
>+	double hactive_cur = 0.0;
>+
>+	ASSERT(cur_src_width <= 256);
>+
>+	*refcyc_per_req_delivery_pre_cur = 0.0;
>+	*refcyc_per_req_delivery_cur = 0.0;
>+	if (cur_src_width > 0) {
>+		unsigned int cur_bit_per_pixel = 0;
>+
>+		if (cur_bpp == dm_cur_2bit) {
>+			cur_req_size = 64; // byte
>+			cur_bit_per_pixel = 2;
>+		} else { // 32bit
>+			cur_bit_per_pixel = 32;
>+			if (cur_src_width >= 1 && cur_src_width <= 16)
>+				cur_req_size = 64;
>+			else if (cur_src_width >= 17 && cur_src_width <= 31)
>+				cur_req_size = 128;
>+			else
>+				cur_req_size = 256;
>+		}
>+
>+		cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
>+		cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
>+				* (double) cur_req_width;
>+		cur_req_per_width = cur_width_ub / (double) cur_req_width;
>+		hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
>+
>+		if (vratio_pre_l <= 1.0) {
>+			*refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq
>+					/ (double) cur_req_per_width;
>+		} else {
>+			*refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz
>+					* (double) cur_src_width / hscale_pixel_rate_l
>+					/ (double) cur_req_per_width;
>+		}
>+
>+		ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
>+
>+		if (vratio_l <= 1.0) {
>+			*refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq
>+					/ (double) cur_req_per_width;
>+		} else {
>+			*refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz
>+					* (double) cur_src_width / hscale_pixel_rate_l
>+					/ (double) cur_req_per_width;
>+		}
>+
>+		dml_print("DML_DLG: %s: cur_req_width                     = %d\n",
>+				__func__,
>+				cur_req_width);
>+		dml_print("DML_DLG: %s: cur_width_ub                      = %3.2f\n",
>+				__func__,
>+				cur_width_ub);
>+		dml_print("DML_DLG: %s: cur_req_per_width                 = %3.2f\n",
>+				__func__,
>+				cur_req_per_width);
>+		dml_print("DML_DLG: %s: hactive_cur                       = %3.2f\n",
>+				__func__,
>+				hactive_cur);
>+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur   = %3.2f\n",
>+				__func__,
>+				*refcyc_per_req_delivery_pre_cur);
>+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur       = %3.2f\n",
>+				__func__,
>+				*refcyc_per_req_delivery_cur);
>+
>+		ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
>+	}
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h	2019-08-31 15:01:11.867736169 -0500
>@@ -0,0 +1,74 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifndef __DML20V2_DISPLAY_RQ_DLG_CALC_H__
>+#define __DML20V2_DISPLAY_RQ_DLG_CALC_H__
>+
>+#include "../dml_common_defs.h"
>+#include "../display_rq_dlg_helpers.h"
>+
>+struct display_mode_lib;
>+
>+
>+// Function: dml_rq_dlg_get_rq_reg
>+//  Main entry point for test to get the register values out of this DML class.
>+//  This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
>+//  and then populate the rq_regs struct
>+// Input:
>+//  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
>+// Output:
>+//  rq_regs - struct that holds all the RQ registers field value.
>+//            See also: <display_rq_regs_st>
>+void dml20v2_rq_dlg_get_rq_reg(
>+		struct display_mode_lib *mode_lib,
>+		display_rq_regs_st *rq_regs,
>+		const display_pipe_params_st pipe_param);
>+
>+
>+// Function: dml_rq_dlg_get_dlg_reg
>+//   Calculate and return DLG and TTU register struct given the system setting
>+// Output:
>+//  dlg_regs - output DLG register struct
>+//  ttu_regs - output DLG TTU register struct
>+// Input:
>+//  e2e_pipe_param - "compacted" array of e2e pipe param struct
>+//  num_pipes - num of active "pipe" or "route"
>+//  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
>+//  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
>+//           Added for legacy or unrealistic timing tests.
>+void dml20v2_rq_dlg_get_dlg_reg(
>+		struct display_mode_lib *mode_lib,
>+		display_dlg_regs_st *dlg_regs,
>+		display_ttu_regs_st *ttu_regs,
>+		display_e2e_pipe_params_st *e2e_pipe_param,
>+		const unsigned int num_pipes,
>+		const unsigned int pipe_idx,
>+		const bool cstate_en,
>+		const bool pstate_en,
>+		const bool vm_en,
>+		const bool ignore_viewport_pos,
>+		const bool immediate_flip_support);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c	2019-08-31 15:01:11.868736169 -0500
>@@ -0,0 +1,6123 @@
>+/*
>+ * Copyright 2017 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
>+
>+#include "../display_mode_lib.h"
>+#include "../dml_inline_defs.h"
>+#include "../display_mode_vba.h"
>+#include "display_mode_vba_21.h"
>+
>+
>+/*
>+ * NOTE:
>+ *   This file is gcc-parsable HW gospel, coming straight from HW engineers.
>+ *
>+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
>+ * ways. Unless there is something clearly wrong with it the code should
>+ * remain as-is as it provides us with a guarantee from HW that it is correct.
>+ */
>+
>+typedef unsigned int uint;
>+
>+typedef struct {
>+	double DPPCLK;
>+	double DISPCLK;
>+	double PixelClock;
>+	double DCFCLKDeepSleep;
>+	unsigned int DPPPerPlane;
>+	bool ScalerEnabled;
>+	enum scan_direction_class SourceScan;
>+	unsigned int BlockWidth256BytesY;
>+	unsigned int BlockHeight256BytesY;
>+	unsigned int BlockWidth256BytesC;
>+	unsigned int BlockHeight256BytesC;
>+	unsigned int InterlaceEnable;
>+	unsigned int NumberOfCursors;
>+	unsigned int VBlank;
>+	unsigned int HTotal;
>+} Pipe;
>+
>+typedef struct {
>+	bool Enable;
>+	unsigned int MaxPageTableLevels;
>+	unsigned int CachedPageTableLevels;
>+} HostVM;
>+
>+#define BPP_INVALID 0
>+#define BPP_BLENDED_PIPE 0xffffffff
>+
>+static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
>+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
>+		struct display_mode_lib *mode_lib);
>+static unsigned int dscceComputeDelay(
>+		unsigned int bpc,
>+		double bpp,
>+		unsigned int sliceWidth,
>+		unsigned int numSlices,
>+		enum output_format_class pixelFormat);
>+static unsigned int dscComputeDelay(enum output_format_class pixelFormat);
>+// Super monster function with some 45 argument
>+static bool CalculatePrefetchSchedule(
>+		struct display_mode_lib *mode_lib,
>+		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
>+		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
>+		Pipe *myPipe,
>+		unsigned int DSCDelay,
>+		double DPPCLKDelaySubtotal,
>+		double DPPCLKDelaySCL,
>+		double DPPCLKDelaySCLLBOnly,
>+		double DPPCLKDelayCNVCFormater,
>+		double DPPCLKDelayCNVCCursor,
>+		double DISPCLKDelaySubtotal,
>+		unsigned int ScalerRecoutWidth,
>+		enum output_format_class OutputFormat,
>+		unsigned int MaxInterDCNTileRepeaters,
>+		unsigned int VStartup,
>+		unsigned int MaxVStartup,
>+		unsigned int GPUVMPageTableLevels,
>+		bool GPUVMEnable,
>+		HostVM *myHostVM,
>+		bool DynamicMetadataEnable,
>+		int DynamicMetadataLinesBeforeActiveRequired,
>+		unsigned int DynamicMetadataTransmittedBytes,
>+		bool DCCEnable,
>+		double UrgentLatency,
>+		double UrgentExtraLatency,
>+		double TCalc,
>+		unsigned int PDEAndMetaPTEBytesFrame,
>+		unsigned int MetaRowByte,
>+		unsigned int PixelPTEBytesPerRow,
>+		double PrefetchSourceLinesY,
>+		unsigned int SwathWidthY,
>+		double BytePerPixelDETY,
>+		double VInitPreFillY,
>+		unsigned int MaxNumSwathY,
>+		double PrefetchSourceLinesC,
>+		double BytePerPixelDETC,
>+		double VInitPreFillC,
>+		unsigned int MaxNumSwathC,
>+		unsigned int SwathHeightY,
>+		unsigned int SwathHeightC,
>+		double TWait,
>+		bool XFCEnabled,
>+		double XFCRemoteSurfaceFlipDelay,
>+		bool ProgressiveToInterlaceUnitInOPP,
>+		double *DSTXAfterScaler,
>+		double *DSTYAfterScaler,
>+		double *DestinationLinesForPrefetch,
>+		double *PrefetchBandwidth,
>+		double *DestinationLinesToRequestVMInVBlank,
>+		double *DestinationLinesToRequestRowInVBlank,
>+		double *VRatioPrefetchY,
>+		double *VRatioPrefetchC,
>+		double *RequiredPrefetchPixDataBWLuma,
>+		double *RequiredPrefetchPixDataBWChroma,
>+		unsigned int *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata,
>+		double *Tno_bw,
>+		double *prefetch_vmrow_bw,
>+		unsigned int *swath_width_luma_ub,
>+		unsigned int *swath_width_chroma_ub,
>+		unsigned int *VUpdateOffsetPix,
>+		double *VUpdateWidthPix,
>+		double *VReadyOffsetPix);
>+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
>+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed);
>+static double CalculateDCCConfiguration(
>+		bool                 DCCEnabled,
>+		bool                 DCCProgrammingAssumesScanDirectionUnknown,
>+		unsigned int         ViewportWidth,
>+		unsigned int         ViewportHeight,
>+		double               DETBufferSize,
>+		unsigned int         RequestHeight256Byte,
>+		unsigned int         SwathHeight,
>+		enum dm_swizzle_mode TilingFormat,
>+		unsigned int         BytePerPixel,
>+		enum scan_direction_class ScanOrientation,
>+		unsigned int        *MaxUncompressedBlock,
>+		unsigned int        *MaxCompressedBlock,
>+		unsigned int        *Independent64ByteBlock);
>+static double CalculatePrefetchSourceLines(
>+		struct display_mode_lib *mode_lib,
>+		double VRatio,
>+		double vtaps,
>+		bool Interlace,
>+		bool ProgressiveToInterlaceUnitInOPP,
>+		unsigned int SwathHeight,
>+		unsigned int ViewportYStart,
>+		double *VInitPreFill,
>+		unsigned int *MaxNumSwath);
>+static unsigned int CalculateVMAndRowBytes(
>+		struct display_mode_lib *mode_lib,
>+		bool DCCEnable,
>+		unsigned int BlockHeight256Bytes,
>+		unsigned int BlockWidth256Bytes,
>+		enum source_format_class SourcePixelFormat,
>+		unsigned int SurfaceTiling,
>+		unsigned int BytePerPixel,
>+		enum scan_direction_class ScanDirection,
>+		unsigned int ViewportWidth,
>+		unsigned int ViewportHeight,
>+		unsigned int SwathWidthY,
>+		bool GPUVMEnable,
>+		bool HostVMEnable,
>+		unsigned int HostVMMaxPageTableLevels,
>+		unsigned int HostVMCachedPageTableLevels,
>+		unsigned int VMMPageSize,
>+		unsigned int PTEBufferSizeInRequests,
>+		unsigned int Pitch,
>+		unsigned int DCCMetaPitch,
>+		unsigned int *MacroTileWidth,
>+		unsigned int *MetaRowByte,
>+		unsigned int *PixelPTEBytesPerRow,
>+		bool *PTEBufferSizeNotExceeded,
>+		unsigned int *dpte_row_width_ub,
>+		unsigned int *dpte_row_height,
>+		unsigned int *MetaRequestWidth,
>+		unsigned int *MetaRequestHeight,
>+		unsigned int *meta_row_width,
>+		unsigned int *meta_row_height,
>+		unsigned int *vm_group_bytes,
>+		long         *dpte_group_bytes,
>+		unsigned int *PixelPTEReqWidth,
>+		unsigned int *PixelPTEReqHeight,
>+		unsigned int *PTERequestSize,
>+		unsigned int *DPDE0BytesFrame,
>+		unsigned int *MetaPTEBytesFrame);
>+
>+static double CalculateTWait(
>+		unsigned int PrefetchMode,
>+		double DRAMClockChangeLatency,
>+		double UrgentLatency,
>+		double SREnterPlusExitTime);
>+static double CalculateRemoteSurfaceFlipDelay(
>+		struct display_mode_lib *mode_lib,
>+		double VRatio,
>+		double SwathWidth,
>+		double Bpp,
>+		double LineTime,
>+		double XFCTSlvVupdateOffset,
>+		double XFCTSlvVupdateWidth,
>+		double XFCTSlvVreadyOffset,
>+		double XFCXBUFLatencyTolerance,
>+		double XFCFillBWOverhead,
>+		double XFCSlvChunkSize,
>+		double XFCBusTransportTime,
>+		double TCalc,
>+		double TWait,
>+		double *SrcActiveDrainRate,
>+		double *TInitXFill,
>+		double *TslvChk);
>+static void CalculateActiveRowBandwidth(
>+		bool GPUVMEnable,
>+		enum source_format_class SourcePixelFormat,
>+		double VRatio,
>+		bool DCCEnable,
>+		double LineTime,
>+		unsigned int MetaRowByteLuma,
>+		unsigned int MetaRowByteChroma,
>+		unsigned int meta_row_height_luma,
>+		unsigned int meta_row_height_chroma,
>+		unsigned int PixelPTEBytesPerRowLuma,
>+		unsigned int PixelPTEBytesPerRowChroma,
>+		unsigned int dpte_row_height_luma,
>+		unsigned int dpte_row_height_chroma,
>+		double *meta_row_bw,
>+		double *dpte_row_bw);
>+static void CalculateFlipSchedule(
>+		struct display_mode_lib *mode_lib,
>+		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
>+		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
>+		double UrgentExtraLatency,
>+		double UrgentLatency,
>+		unsigned int GPUVMMaxPageTableLevels,
>+		bool HostVMEnable,
>+		unsigned int HostVMMaxPageTableLevels,
>+		unsigned int HostVMCachedPageTableLevels,
>+		bool GPUVMEnable,
>+		double PDEAndMetaPTEBytesPerFrame,
>+		double MetaRowBytes,
>+		double DPTEBytesPerRow,
>+		double BandwidthAvailableForImmediateFlip,
>+		unsigned int TotImmediateFlipBytes,
>+		enum source_format_class SourcePixelFormat,
>+		double LineTime,
>+		double VRatio,
>+		double Tno_bw,
>+		bool DCCEnable,
>+		unsigned int dpte_row_height,
>+		unsigned int meta_row_height,
>+		unsigned int dpte_row_height_chroma,
>+		unsigned int meta_row_height_chroma,
>+		double *DestinationLinesToRequestVMInImmediateFlip,
>+		double *DestinationLinesToRequestRowInImmediateFlip,
>+		double *final_flip_bw,
>+		bool *ImmediateFlipSupportedForPipe);
>+static double CalculateWriteBackDelay(
>+		enum source_format_class WritebackPixelFormat,
>+		double WritebackHRatio,
>+		double WritebackVRatio,
>+		unsigned int WritebackLumaHTaps,
>+		unsigned int WritebackLumaVTaps,
>+		unsigned int WritebackChromaHTaps,
>+		unsigned int WritebackChromaVTaps,
>+		unsigned int WritebackDestinationWidth);
>+static void CalculateWatermarksAndDRAMSpeedChangeSupport(
>+		struct display_mode_lib *mode_lib,
>+		unsigned int PrefetchMode,
>+		unsigned int NumberOfActivePlanes,
>+		unsigned int MaxLineBufferLines,
>+		unsigned int LineBufferSize,
>+		unsigned int DPPOutputBufferPixels,
>+		double DETBufferSizeInKByte,
>+		unsigned int WritebackInterfaceLumaBufferSize,
>+		unsigned int WritebackInterfaceChromaBufferSize,
>+		double DCFCLK,
>+		double UrgentOutOfOrderReturn,
>+		double ReturnBW,
>+		bool GPUVMEnable,
>+		long dpte_group_bytes[],
>+		unsigned int MetaChunkSize,
>+		double UrgentLatency,
>+		double ExtraLatency,
>+		double WritebackLatency,
>+		double WritebackChunkSize,
>+		double SOCCLK,
>+		double DRAMClockChangeLatency,
>+		double SRExitTime,
>+		double SREnterPlusExitTime,
>+		double DCFCLKDeepSleep,
>+		int DPPPerPlane[],
>+		bool DCCEnable[],
>+		double DPPCLK[],
>+		unsigned int SwathWidthSingleDPPY[],
>+		unsigned int SwathHeightY[],
>+		double ReadBandwidthPlaneLuma[],
>+		unsigned int SwathHeightC[],
>+		double ReadBandwidthPlaneChroma[],
>+		unsigned int LBBitPerPixel[],
>+		unsigned int SwathWidthY[],
>+		double HRatio[],
>+		unsigned int vtaps[],
>+		unsigned int VTAPsChroma[],
>+		double VRatio[],
>+		unsigned int HTotal[],
>+		double PixelClock[],
>+		unsigned int BlendingAndTiming[],
>+		double BytePerPixelDETY[],
>+		double BytePerPixelDETC[],
>+		bool WritebackEnable[],
>+		enum source_format_class WritebackPixelFormat[],
>+		double WritebackDestinationWidth[],
>+		double WritebackDestinationHeight[],
>+		double WritebackSourceHeight[],
>+		enum clock_change_support *DRAMClockChangeSupport,
>+		double *UrgentWatermark,
>+		double *WritebackUrgentWatermark,
>+		double *DRAMClockChangeWatermark,
>+		double *WritebackDRAMClockChangeWatermark,
>+		double *StutterExitWatermark,
>+		double *StutterEnterPlusExitWatermark,
>+		double *MinActiveDRAMClockChangeLatencySupported);
>+static void CalculateDCFCLKDeepSleep(
>+		struct display_mode_lib *mode_lib,
>+		unsigned int NumberOfActivePlanes,
>+		double BytePerPixelDETY[],
>+		double BytePerPixelDETC[],
>+		double VRatio[],
>+		unsigned int SwathWidthY[],
>+		int DPPPerPlane[],
>+		double HRatio[],
>+		double PixelClock[],
>+		double PSCL_THROUGHPUT[],
>+		double PSCL_THROUGHPUT_CHROMA[],
>+		double DPPCLK[],
>+		double *DCFCLKDeepSleep);
>+static void CalculateDETBufferSize(
>+		double DETBufferSizeInKByte,
>+		unsigned int SwathHeightY,
>+		unsigned int SwathHeightC,
>+		double *DETBufferSizeY,
>+		double *DETBufferSizeC);
>+static void CalculateUrgentBurstFactor(
>+		unsigned int DETBufferSizeInKByte,
>+		unsigned int SwathHeightY,
>+		unsigned int SwathHeightC,
>+		unsigned int SwathWidthY,
>+		double LineTime,
>+		double UrgentLatency,
>+		double CursorBufferSize,
>+		unsigned int CursorWidth,
>+		unsigned int CursorBPP,
>+		double VRatio,
>+		double VRatioPreY,
>+		double VRatioPreC,
>+		double BytePerPixelInDETY,
>+		double BytePerPixelInDETC,
>+		double *UrgentBurstFactorCursor,
>+		double *UrgentBurstFactorCursorPre,
>+		double *UrgentBurstFactorLuma,
>+		double *UrgentBurstFactorLumaPre,
>+		double *UrgentBurstFactorChroma,
>+		double *UrgentBurstFactorChromaPre,
>+		unsigned int *NotEnoughUrgentLatencyHiding,
>+		unsigned int *NotEnoughUrgentLatencyHidingPre);
>+
>+static void CalculatePixelDeliveryTimes(
>+		unsigned int           NumberOfActivePlanes,
>+		double                 VRatio[],
>+		double                 VRatioPrefetchY[],
>+		double                 VRatioPrefetchC[],
>+		unsigned int           swath_width_luma_ub[],
>+		unsigned int           swath_width_chroma_ub[],
>+		int                    DPPPerPlane[],
>+		double                 HRatio[],
>+		double                 PixelClock[],
>+		double                 PSCL_THROUGHPUT[],
>+		double                 PSCL_THROUGHPUT_CHROMA[],
>+		double                 DPPCLK[],
>+		double                 BytePerPixelDETC[],
>+		enum scan_direction_class SourceScan[],
>+		unsigned int           BlockWidth256BytesY[],
>+		unsigned int           BlockHeight256BytesY[],
>+		unsigned int           BlockWidth256BytesC[],
>+		unsigned int           BlockHeight256BytesC[],
>+		double                 DisplayPipeLineDeliveryTimeLuma[],
>+		double                 DisplayPipeLineDeliveryTimeChroma[],
>+		double                 DisplayPipeLineDeliveryTimeLumaPrefetch[],
>+		double                 DisplayPipeLineDeliveryTimeChromaPrefetch[],
>+		double                 DisplayPipeRequestDeliveryTimeLuma[],
>+		double                 DisplayPipeRequestDeliveryTimeChroma[],
>+		double                 DisplayPipeRequestDeliveryTimeLumaPrefetch[],
>+		double                 DisplayPipeRequestDeliveryTimeChromaPrefetch[]);
>+
>+static void CalculateMetaAndPTETimes(
>+		unsigned int           NumberOfActivePlanes,
>+		bool                   GPUVMEnable,
>+		unsigned int           MetaChunkSize,
>+		unsigned int           MinMetaChunkSizeBytes,
>+		unsigned int           GPUVMMaxPageTableLevels,
>+		unsigned int           HTotal[],
>+		double                 VRatio[],
>+		double                 VRatioPrefetchY[],
>+		double                 VRatioPrefetchC[],
>+		double                 DestinationLinesToRequestRowInVBlank[],
>+		double                 DestinationLinesToRequestRowInImmediateFlip[],
>+		double                 DestinationLinesToRequestVMInVBlank[],
>+		double                 DestinationLinesToRequestVMInImmediateFlip[],
>+		bool                   DCCEnable[],
>+		double                 PixelClock[],
>+		double                 BytePerPixelDETY[],
>+		double                 BytePerPixelDETC[],
>+		enum scan_direction_class SourceScan[],
>+		unsigned int           dpte_row_height[],
>+		unsigned int           dpte_row_height_chroma[],
>+		unsigned int           meta_row_width[],
>+		unsigned int           meta_row_height[],
>+		unsigned int           meta_req_width[],
>+		unsigned int           meta_req_height[],
>+		long                   dpte_group_bytes[],
>+		unsigned int           PTERequestSizeY[],
>+		unsigned int           PTERequestSizeC[],
>+		unsigned int           PixelPTEReqWidthY[],
>+		unsigned int           PixelPTEReqHeightY[],
>+		unsigned int           PixelPTEReqWidthC[],
>+		unsigned int           PixelPTEReqHeightC[],
>+		unsigned int           dpte_row_width_luma_ub[],
>+		unsigned int           dpte_row_width_chroma_ub[],
>+		unsigned int           vm_group_bytes[],
>+		unsigned int           dpde0_bytes_per_frame_ub_l[],
>+		unsigned int           dpde0_bytes_per_frame_ub_c[],
>+		unsigned int           meta_pte_bytes_per_frame_ub_l[],
>+		unsigned int           meta_pte_bytes_per_frame_ub_c[],
>+		double                 DST_Y_PER_PTE_ROW_NOM_L[],
>+		double                 DST_Y_PER_PTE_ROW_NOM_C[],
>+		double                 DST_Y_PER_META_ROW_NOM_L[],
>+		double                 TimePerMetaChunkNominal[],
>+		double                 TimePerMetaChunkVBlank[],
>+		double                 TimePerMetaChunkFlip[],
>+		double                 time_per_pte_group_nom_luma[],
>+		double                 time_per_pte_group_vblank_luma[],
>+		double                 time_per_pte_group_flip_luma[],
>+		double                 time_per_pte_group_nom_chroma[],
>+		double                 time_per_pte_group_vblank_chroma[],
>+		double                 time_per_pte_group_flip_chroma[],
>+		double                 TimePerVMGroupVBlank[],
>+		double                 TimePerVMGroupFlip[],
>+		double                 TimePerVMRequestVBlank[],
>+		double                 TimePerVMRequestFlip[]);
>+
>+static double CalculateExtraLatency(
>+		double UrgentRoundTripAndOutOfOrderLatency,
>+		int TotalNumberOfActiveDPP,
>+		int PixelChunkSizeInKByte,
>+		int TotalNumberOfDCCActiveDPP,
>+		int MetaChunkSize,
>+		double ReturnBW,
>+		bool GPUVMEnable,
>+		bool HostVMEnable,
>+		int NumberOfActivePlanes,
>+		int NumberOfDPP[],
>+		long dpte_group_bytes[],
>+		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
>+		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
>+		int HostVMMaxPageTableLevels,
>+		int HostVMCachedPageTableLevels);
>+
>+void dml21_recalculate(struct display_mode_lib *mode_lib)
>+{
>+	ModeSupportAndSystemConfiguration(mode_lib);
>+	PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
>+	DisplayPipeConfiguration(mode_lib);
>+	DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib);
>+}
>+
>+static unsigned int dscceComputeDelay(
>+		unsigned int bpc,
>+		double bpp,
>+		unsigned int sliceWidth,
>+		unsigned int numSlices,
>+		enum output_format_class pixelFormat)
>+{
>+	// valid bpc         = source bits per component in the set of {8, 10, 12}
>+	// valid bpp         = increments of 1/16 of a bit
>+	//                    min = 6/7/8 in N420/N422/444, respectively
>+	//                    max = such that compression is 1:1
>+	//valid sliceWidth  = number of pixels per slice line, must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode)
>+	//valid numSlices   = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4}
>+	//valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420}
>+
>+	// fixed value
>+	unsigned int rcModelSize = 8192;
>+
>+	// N422/N420 operate at 2 pixels per clock
>+	unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, S, ix, wx, p, l0, a, ax, l,
>+			Delay, pixels;
>+
>+	if (pixelFormat == dm_n422 || pixelFormat == dm_420)
>+		pixelsPerClock = 2;
>+	// #all other modes operate at 1 pixel per clock
>+	else
>+		pixelsPerClock = 1;
>+
>+	//initial transmit delay as per PPS
>+	initalXmitDelay = dml_round(rcModelSize / 2.0 / bpp / pixelsPerClock);
>+
>+	//compute ssm delay
>+	if (bpc == 8)
>+		D = 81;
>+	else if (bpc == 10)
>+		D = 89;
>+	else
>+		D = 113;
>+
>+	//divide by pixel per cycle to compute slice width as seen by DSC
>+	w = sliceWidth / pixelsPerClock;
>+
>+	//422 mode has an additional cycle of delay
>+	if (pixelFormat == dm_s422)
>+		S = 1;
>+	else
>+		S = 0;
>+
>+	//main calculation for the dscce
>+	ix = initalXmitDelay + 45;
>+	wx = (w + 2) / 3;
>+	p = 3 * wx - w;
>+	l0 = ix / w;
>+	a = ix + p * l0;
>+	ax = (a + 2) / 3 + D + 6 + 1;
>+	l = (ax + wx - 1) / wx;
>+	if ((ix % w) == 0 && p != 0)
>+		lstall = 1;
>+	else
>+		lstall = 0;
>+	Delay = l * wx * (numSlices - 1) + ax + S + lstall + 22;
>+
>+	//dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels
>+	pixels = Delay * 3 * pixelsPerClock;
>+	return pixels;
>+}
>+
>+static unsigned int dscComputeDelay(enum output_format_class pixelFormat)
>+{
>+	unsigned int Delay = 0;
>+
>+	if (pixelFormat == dm_420) {
>+		//   sfr
>+		Delay = Delay + 2;
>+		//   dsccif
>+		Delay = Delay + 0;
>+		//   dscc - input deserializer
>+		Delay = Delay + 3;
>+		//   dscc gets pixels every other cycle
>+		Delay = Delay + 2;
>+		//   dscc - input cdc fifo
>+		Delay = Delay + 12;
>+		//   dscc gets pixels every other cycle
>+		Delay = Delay + 13;
>+		//   dscc - cdc uncertainty
>+		Delay = Delay + 2;
>+		//   dscc - output cdc fifo
>+		Delay = Delay + 7;
>+		//   dscc gets pixels every other cycle
>+		Delay = Delay + 3;
>+		//   dscc - cdc uncertainty
>+		Delay = Delay + 2;
>+		//   dscc - output serializer
>+		Delay = Delay + 1;
>+		//   sft
>+		Delay = Delay + 1;
>+	} else if (pixelFormat == dm_n422) {
>+		//   sfr
>+		Delay = Delay + 2;
>+		//   dsccif
>+		Delay = Delay + 1;
>+		//   dscc - input deserializer
>+		Delay = Delay + 5;
>+		//  dscc - input cdc fifo
>+		Delay = Delay + 25;
>+		//   dscc - cdc uncertainty
>+		Delay = Delay + 2;
>+		//   dscc - output cdc fifo
>+		Delay = Delay + 10;
>+		//   dscc - cdc uncertainty
>+		Delay = Delay + 2;
>+		//   dscc - output serializer
>+		Delay = Delay + 1;
>+		//   sft
>+		Delay = Delay + 1;
>+	} else {
>+		//   sfr
>+		Delay = Delay + 2;
>+		//   dsccif
>+		Delay = Delay + 0;
>+		//   dscc - input deserializer
>+		Delay = Delay + 3;
>+		//   dscc - input cdc fifo
>+		Delay = Delay + 12;
>+		//   dscc - cdc uncertainty
>+		Delay = Delay + 2;
>+		//   dscc - output cdc fifo
>+		Delay = Delay + 7;
>+		//   dscc - output serializer
>+		Delay = Delay + 1;
>+		//   dscc - cdc uncertainty
>+		Delay = Delay + 2;
>+		//   sft
>+		Delay = Delay + 1;
>+	}
>+
>+	return Delay;
>+}
>+
>+static bool CalculatePrefetchSchedule(
>+		struct display_mode_lib *mode_lib,
>+		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
>+		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
>+		Pipe *myPipe,
>+		unsigned int DSCDelay,
>+		double DPPCLKDelaySubtotal,
>+		double DPPCLKDelaySCL,
>+		double DPPCLKDelaySCLLBOnly,
>+		double DPPCLKDelayCNVCFormater,
>+		double DPPCLKDelayCNVCCursor,
>+		double DISPCLKDelaySubtotal,
>+		unsigned int ScalerRecoutWidth,
>+		enum output_format_class OutputFormat,
>+		unsigned int MaxInterDCNTileRepeaters,
>+		unsigned int VStartup,
>+		unsigned int MaxVStartup,
>+		unsigned int GPUVMPageTableLevels,
>+		bool GPUVMEnable,
>+		HostVM *myHostVM,
>+		bool DynamicMetadataEnable,
>+		int DynamicMetadataLinesBeforeActiveRequired,
>+		unsigned int DynamicMetadataTransmittedBytes,
>+		bool DCCEnable,
>+		double UrgentLatency,
>+		double UrgentExtraLatency,
>+		double TCalc,
>+		unsigned int PDEAndMetaPTEBytesFrame,
>+		unsigned int MetaRowByte,
>+		unsigned int PixelPTEBytesPerRow,
>+		double PrefetchSourceLinesY,
>+		unsigned int SwathWidthY,
>+		double BytePerPixelDETY,
>+		double VInitPreFillY,
>+		unsigned int MaxNumSwathY,
>+		double PrefetchSourceLinesC,
>+		double BytePerPixelDETC,
>+		double VInitPreFillC,
>+		unsigned int MaxNumSwathC,
>+		unsigned int SwathHeightY,
>+		unsigned int SwathHeightC,
>+		double TWait,
>+		bool XFCEnabled,
>+		double XFCRemoteSurfaceFlipDelay,
>+		bool ProgressiveToInterlaceUnitInOPP,
>+		double *DSTXAfterScaler,
>+		double *DSTYAfterScaler,
>+		double *DestinationLinesForPrefetch,
>+		double *PrefetchBandwidth,
>+		double *DestinationLinesToRequestVMInVBlank,
>+		double *DestinationLinesToRequestRowInVBlank,
>+		double *VRatioPrefetchY,
>+		double *VRatioPrefetchC,
>+		double *RequiredPrefetchPixDataBWLuma,
>+		double *RequiredPrefetchPixDataBWChroma,
>+		unsigned int *VStartupRequiredWhenNotEnoughTimeForDynamicMetadata,
>+		double *Tno_bw,
>+		double *prefetch_vmrow_bw,
>+		unsigned int *swath_width_luma_ub,
>+		unsigned int *swath_width_chroma_ub,
>+		unsigned int *VUpdateOffsetPix,
>+		double *VUpdateWidthPix,
>+		double *VReadyOffsetPix)
>+{
>+	bool MyError = false;
>+	unsigned int DPPCycles, DISPCLKCycles;
>+	double DSTTotalPixelsAfterScaler, TotalRepeaterDelayTime;
>+	double Tdm, LineTime, Tsetup;
>+	double dst_y_prefetch_equ;
>+	double Tsw_oto;
>+	double prefetch_bw_oto;
>+	double Tvm_oto;
>+	double Tr0_oto;
>+	double Tvm_oto_lines;
>+	double Tr0_oto_lines;
>+	double Tsw_oto_lines;
>+	double dst_y_prefetch_oto;
>+	double TimeForFetchingMetaPTE = 0;
>+	double TimeForFetchingRowInVBlank = 0;
>+	double LinesToRequestPrefetchPixelData = 0;
>+	double HostVMInefficiencyFactor;
>+	unsigned int HostVMDynamicLevels;
>+
>+	if (GPUVMEnable == true && myHostVM->Enable == true) {
>+		HostVMInefficiencyFactor =
>+				PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData
>+						/ PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly;
>+		HostVMDynamicLevels = myHostVM->MaxPageTableLevels
>+				- myHostVM->CachedPageTableLevels;
>+	} else {
>+		HostVMInefficiencyFactor = 1;
>+		HostVMDynamicLevels = 0;
>+	}
>+
>+	if (myPipe->ScalerEnabled)
>+		DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCL;
>+	else
>+		DPPCycles = DPPCLKDelaySubtotal + DPPCLKDelaySCLLBOnly;
>+
>+	DPPCycles = DPPCycles + DPPCLKDelayCNVCFormater + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor;
>+
>+	DISPCLKCycles = DISPCLKDelaySubtotal;
>+
>+	if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
>+		return true;
>+
>+	*DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK
>+			+ DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay;
>+
>+	if (myPipe->DPPPerPlane > 1)
>+		*DSTXAfterScaler = *DSTXAfterScaler + ScalerRecoutWidth;
>+
>+	if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && ProgressiveToInterlaceUnitInOPP))
>+		*DSTYAfterScaler = 1;
>+	else
>+		*DSTYAfterScaler = 0;
>+
>+	DSTTotalPixelsAfterScaler = ((double) (*DSTYAfterScaler * myPipe->HTotal)) + *DSTXAfterScaler;
>+	*DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1);
>+	*DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal));
>+
>+	*VUpdateOffsetPix = dml_ceil(myPipe->HTotal / 4.0, 1);
>+	TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / myPipe->DPPCLK + 3.0 / myPipe->DISPCLK);
>+	*VUpdateWidthPix = (14.0 / myPipe->DCFCLKDeepSleep + 12.0 / myPipe->DPPCLK + TotalRepeaterDelayTime)
>+			* myPipe->PixelClock;
>+
>+	*VReadyOffsetPix = dml_max(
>+			150.0 / myPipe->DPPCLK,
>+			TotalRepeaterDelayTime + 20.0 / myPipe->DCFCLKDeepSleep + 10.0 / myPipe->DPPCLK)
>+			* myPipe->PixelClock;
>+
>+	Tsetup = (double) (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / myPipe->PixelClock;
>+
>+	LineTime = (double) myPipe->HTotal / myPipe->PixelClock;
>+
>+	if (DynamicMetadataEnable) {
>+		double Tdmbf, Tdmec, Tdmsks;
>+
>+		Tdm = dml_max(0.0, UrgentExtraLatency - TCalc);
>+		Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / myPipe->DISPCLK;
>+		Tdmec = LineTime;
>+		if (DynamicMetadataLinesBeforeActiveRequired == -1)
>+			Tdmsks = myPipe->VBlank * LineTime / 2.0;
>+		else
>+			Tdmsks = DynamicMetadataLinesBeforeActiveRequired * LineTime;
>+		if (myPipe->InterlaceEnable && !ProgressiveToInterlaceUnitInOPP)
>+			Tdmsks = Tdmsks / 2;
>+		if (VStartup * LineTime
>+				< Tsetup + TWait + UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) {
>+			MyError = true;
>+			*VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = (Tsetup + TWait
>+					+ UrgentExtraLatency + Tdmbf + Tdmec + Tdmsks) / LineTime;
>+		} else
>+			*VStartupRequiredWhenNotEnoughTimeForDynamicMetadata = 0.0;
>+	} else
>+		Tdm = 0;
>+
>+	if (GPUVMEnable) {
>+		if (GPUVMPageTableLevels >= 3)
>+			*Tno_bw = UrgentExtraLatency + UrgentLatency * ((GPUVMPageTableLevels - 2) * (myHostVM->MaxPageTableLevels + 1) - 1);
>+		else
>+			*Tno_bw = 0;
>+	} else if (!DCCEnable)
>+		*Tno_bw = LineTime;
>+	else
>+		*Tno_bw = LineTime / 4;
>+
>+	dst_y_prefetch_equ = VStartup - dml_max(TCalc + TWait, XFCRemoteSurfaceFlipDelay) / LineTime
>+			- (Tsetup + Tdm) / LineTime
>+			- (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal);
>+
>+	Tsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime;
>+
>+	if (myPipe->SourceScan == dm_horz) {
>+		*swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockWidth256BytesY) + myPipe->BlockWidth256BytesY;
>+		*swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockWidth256BytesC) + myPipe->BlockWidth256BytesC;
>+	} else {
>+		*swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockHeight256BytesY) + myPipe->BlockHeight256BytesY;
>+		*swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockHeight256BytesC) + myPipe->BlockHeight256BytesC;
>+	}
>+
>+	prefetch_bw_oto = (PrefetchSourceLinesY * *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) + PrefetchSourceLinesC * *swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2)) / Tsw_oto;
>+
>+
>+	if (GPUVMEnable == true) {
>+		Tvm_oto = dml_max(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
>+				dml_max(UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1),
>+					LineTime / 4.0));
>+	} else
>+		Tvm_oto = LineTime / 4.0;
>+
>+	if ((GPUVMEnable == true || DCCEnable == true)) {
>+		Tr0_oto = dml_max(
>+				(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto,
>+				dml_max(UrgentLatency * (HostVMDynamicLevels + 1), dml_max(LineTime - Tvm_oto, LineTime / 4)));
>+	} else
>+		Tr0_oto = (LineTime - Tvm_oto) / 2.0;
>+
>+	Tvm_oto_lines = dml_ceil(4 * Tvm_oto / LineTime, 1) / 4.0;
>+	Tr0_oto_lines = dml_ceil(4 * Tr0_oto / LineTime, 1) / 4.0;
>+	Tsw_oto_lines = dml_ceil(4 * Tsw_oto / LineTime, 1) / 4.0;
>+	dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Tsw_oto_lines + 0.75;
>+
>+	dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0;
>+
>+	if (dst_y_prefetch_oto < dst_y_prefetch_equ)
>+		*DestinationLinesForPrefetch = dst_y_prefetch_oto;
>+	else
>+		*DestinationLinesForPrefetch = dst_y_prefetch_equ;
>+
>+	dml_print("DML: VStartup: %d\n", VStartup);
>+	dml_print("DML: TCalc: %f\n", TCalc);
>+	dml_print("DML: TWait: %f\n", TWait);
>+	dml_print("DML: XFCRemoteSurfaceFlipDelay: %f\n", XFCRemoteSurfaceFlipDelay);
>+	dml_print("DML: LineTime: %f\n", LineTime);
>+	dml_print("DML: Tsetup: %f\n", Tsetup);
>+	dml_print("DML: Tdm: %f\n", Tdm);
>+	dml_print("DML: DSTYAfterScaler: %f\n", *DSTYAfterScaler);
>+	dml_print("DML: DSTXAfterScaler: %f\n", *DSTXAfterScaler);
>+	dml_print("DML: HTotal: %d\n", myPipe->HTotal);
>+
>+	*PrefetchBandwidth = 0;
>+	*DestinationLinesToRequestVMInVBlank = 0;
>+	*DestinationLinesToRequestRowInVBlank = 0;
>+	*VRatioPrefetchY = 0;
>+	*VRatioPrefetchC = 0;
>+	*RequiredPrefetchPixDataBWLuma = 0;
>+	if (*DestinationLinesForPrefetch > 1) {
>+		double PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte
>+				+ 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor
>+				+ PrefetchSourceLinesY * *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1)
>+				+ PrefetchSourceLinesC * *swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2))
>+				/ (*DestinationLinesForPrefetch * LineTime - *Tno_bw);
>+
>+		double PrefetchBandwidth2 = (PDEAndMetaPTEBytesFrame *
>+				HostVMInefficiencyFactor + PrefetchSourceLinesY *
>+				*swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) +
>+				PrefetchSourceLinesC * *swath_width_chroma_ub *
>+				dml_ceil(BytePerPixelDETC, 2)) /
>+				(*DestinationLinesForPrefetch * LineTime - *Tno_bw - 2 *
>+				UrgentLatency * (1 + HostVMDynamicLevels));
>+
>+		double PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow
>+				* HostVMInefficiencyFactor + PrefetchSourceLinesY *
>+				*swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) +
>+				PrefetchSourceLinesC * *swath_width_chroma_ub *
>+				dml_ceil(BytePerPixelDETC, 2)) /
>+				(*DestinationLinesForPrefetch * LineTime -
>+				UrgentExtraLatency - UrgentLatency * (GPUVMPageTableLevels
>+				* (HostVMDynamicLevels + 1) - 1));
>+
>+		double PrefetchBandwidth4 = (PrefetchSourceLinesY * *swath_width_luma_ub *
>+				dml_ceil(BytePerPixelDETY, 1) + PrefetchSourceLinesC *
>+				*swath_width_chroma_ub * dml_ceil(BytePerPixelDETC, 2)) /
>+				(*DestinationLinesForPrefetch * LineTime -
>+				UrgentExtraLatency - UrgentLatency * (GPUVMPageTableLevels
>+				* (HostVMDynamicLevels + 1) - 1) - 2 * UrgentLatency *
>+				(1 + HostVMDynamicLevels));
>+
>+		if (VStartup == MaxVStartup && (PrefetchBandwidth1 > 4 * prefetch_bw_oto) && (*DestinationLinesForPrefetch - dml_ceil(Tsw_oto_lines, 1) / 4.0 - 0.75) * LineTime - *Tno_bw > 0) {
>+			PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) / ((*DestinationLinesForPrefetch - dml_ceil(Tsw_oto_lines, 1) / 4.0 - 0.75) * LineTime - *Tno_bw);
>+		}
>+		if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1 >= UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1) && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth1 >= UrgentLatency * (1 + HostVMDynamicLevels)) {
>+			*PrefetchBandwidth = PrefetchBandwidth1;
>+		} else if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2 >= UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1) && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth2 < UrgentLatency * (1 + HostVMDynamicLevels)) {
>+			*PrefetchBandwidth = PrefetchBandwidth2;
>+		} else if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3 < UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1) && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth3 >= UrgentLatency * (1 + HostVMDynamicLevels)) {
>+			*PrefetchBandwidth = PrefetchBandwidth3;
>+		} else {
>+			*PrefetchBandwidth = PrefetchBandwidth4;
>+		}
>+
>+		if (GPUVMEnable) {
>+			TimeForFetchingMetaPTE = dml_max(*Tno_bw + (double) PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / *PrefetchBandwidth,
>+					dml_max(UrgentExtraLatency + UrgentLatency * (GPUVMPageTableLevels * (HostVMDynamicLevels + 1) - 1), LineTime / 4));
>+		} else {
>+// 5/30/2018 - This was an optimization requested from Sy but now NumberOfCursors is no longer a factor
>+//             so if this needs to be reinstated, then it should be officially done in the VBA code as well.
>+//			if (mode_lib->NumberOfCursors > 0 || XFCEnabled)
>+				TimeForFetchingMetaPTE = LineTime / 4;
>+//			else
>+//				TimeForFetchingMetaPTE = 0.0;
>+		}
>+
>+		if ((GPUVMEnable == true || DCCEnable == true)) {
>+			TimeForFetchingRowInVBlank =
>+					dml_max(
>+							(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor)
>+									/ *PrefetchBandwidth,
>+							dml_max(
>+									UrgentLatency * (1 + HostVMDynamicLevels),
>+									dml_max(
>+											(LineTime
>+													- TimeForFetchingMetaPTE) / 2.0,
>+											LineTime
>+													/ 4.0)));
>+		} else {
>+// See note above dated 5/30/2018
>+//			if (NumberOfCursors > 0 || XFCEnabled)
>+				TimeForFetchingRowInVBlank = (LineTime - TimeForFetchingMetaPTE) / 2.0;
>+//			else // TODO: Did someone else add this??
>+//				TimeForFetchingRowInVBlank = 0.0;
>+		}
>+
>+		*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
>+
>+		*DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0;
>+
>+		LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch
>+// See note above dated 5/30/2018
>+//						- ((NumberOfCursors > 0 || GPUVMEnable || DCCEnable) ?
>+						- ((GPUVMEnable || DCCEnable) ?
>+								(*DestinationLinesToRequestVMInVBlank + 2 * *DestinationLinesToRequestRowInVBlank) :
>+								0.0); // TODO: Did someone else add this??
>+
>+		if (LinesToRequestPrefetchPixelData > 0) {
>+
>+			*VRatioPrefetchY = (double) PrefetchSourceLinesY
>+					/ LinesToRequestPrefetchPixelData;
>+			*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
>+			if ((SwathHeightY > 4) && (VInitPreFillY > 3)) {
>+				if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) {
>+					*VRatioPrefetchY =
>+							dml_max(
>+									(double) PrefetchSourceLinesY
>+											/ LinesToRequestPrefetchPixelData,
>+									(double) MaxNumSwathY
>+											* SwathHeightY
>+											/ (LinesToRequestPrefetchPixelData
>+													- (VInitPreFillY
>+															- 3.0)
>+															/ 2.0));
>+					*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
>+				} else {
>+					MyError = true;
>+					*VRatioPrefetchY = 0;
>+				}
>+			}
>+
>+			*VRatioPrefetchC = (double) PrefetchSourceLinesC
>+					/ LinesToRequestPrefetchPixelData;
>+			*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
>+
>+			if ((SwathHeightC > 4)) {
>+				if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) {
>+					*VRatioPrefetchC =
>+							dml_max(
>+									*VRatioPrefetchC,
>+									(double) MaxNumSwathC
>+											* SwathHeightC
>+											/ (LinesToRequestPrefetchPixelData
>+													- (VInitPreFillC
>+															- 3.0)
>+															/ 2.0));
>+					*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
>+				} else {
>+					MyError = true;
>+					*VRatioPrefetchC = 0;
>+				}
>+			}
>+
>+			*RequiredPrefetchPixDataBWLuma = myPipe->DPPPerPlane
>+					* (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData
>+					* dml_ceil(BytePerPixelDETY, 1)
>+					* *swath_width_luma_ub / LineTime;
>+			*RequiredPrefetchPixDataBWChroma = myPipe->DPPPerPlane
>+					* (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData
>+					* dml_ceil(BytePerPixelDETC, 2)
>+					* *swath_width_chroma_ub / LineTime;
>+		} else {
>+			MyError = true;
>+			*VRatioPrefetchY = 0;
>+			*VRatioPrefetchC = 0;
>+			*RequiredPrefetchPixDataBWLuma = 0;
>+			*RequiredPrefetchPixDataBWChroma = 0;
>+		}
>+
>+		dml_print("DML: Tvm: %fus\n", TimeForFetchingMetaPTE);
>+		dml_print("DML: Tr0: %fus\n", TimeForFetchingRowInVBlank);
>+		dml_print("DML: Tsw: %fus\n", (double)(*DestinationLinesForPrefetch) * LineTime - TimeForFetchingMetaPTE - TimeForFetchingRowInVBlank);
>+		dml_print("DML: Tpre: %fus\n", (double)(*DestinationLinesForPrefetch) * LineTime);
>+		dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d\n", PixelPTEBytesPerRow);
>+
>+	} else {
>+		MyError = true;
>+	}
>+
>+	{
>+		double prefetch_vm_bw;
>+		double prefetch_row_bw;
>+
>+		if (PDEAndMetaPTEBytesFrame == 0) {
>+			prefetch_vm_bw = 0;
>+		} else if (*DestinationLinesToRequestVMInVBlank > 0) {
>+			prefetch_vm_bw = PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInVBlank * LineTime);
>+		} else {
>+			prefetch_vm_bw = 0;
>+			MyError = true;
>+		}
>+		if (MetaRowByte + PixelPTEBytesPerRow == 0) {
>+			prefetch_row_bw = 0;
>+		} else if (*DestinationLinesToRequestRowInVBlank > 0) {
>+			prefetch_row_bw = (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInVBlank * LineTime);
>+		} else {
>+			prefetch_row_bw = 0;
>+			MyError = true;
>+		}
>+
>+		*prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw);
>+	}
>+
>+	if (MyError) {
>+		*PrefetchBandwidth = 0;
>+		TimeForFetchingMetaPTE = 0;
>+		TimeForFetchingRowInVBlank = 0;
>+		*DestinationLinesToRequestVMInVBlank = 0;
>+		*DestinationLinesToRequestRowInVBlank = 0;
>+		*DestinationLinesForPrefetch = 0;
>+		LinesToRequestPrefetchPixelData = 0;
>+		*VRatioPrefetchY = 0;
>+		*VRatioPrefetchC = 0;
>+		*RequiredPrefetchPixDataBWLuma = 0;
>+		*RequiredPrefetchPixDataBWChroma = 0;
>+	}
>+
>+	return MyError;
>+}
>+
>+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed)
>+{
>+	return VCOSpeed * 4 / dml_floor(VCOSpeed * 4 / Clock, 1);
>+}
>+
>+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed)
>+{
>+	return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1);
>+}
>+
>+static double CalculateDCCConfiguration(
>+		bool DCCEnabled,
>+		bool DCCProgrammingAssumesScanDirectionUnknown,
>+		unsigned int ViewportWidth,
>+		unsigned int ViewportHeight,
>+		double DETBufferSize,
>+		unsigned int RequestHeight256Byte,
>+		unsigned int SwathHeight,
>+		enum dm_swizzle_mode TilingFormat,
>+		unsigned int BytePerPixel,
>+		enum scan_direction_class ScanOrientation,
>+		unsigned int *MaxUncompressedBlock,
>+		unsigned int *MaxCompressedBlock,
>+		unsigned int *Independent64ByteBlock)
>+{
>+	double MaximumDCCCompressionSurface = 0.0;
>+	enum {
>+		REQ_256Bytes,
>+		REQ_128BytesNonContiguous,
>+		REQ_128BytesContiguous,
>+		REQ_NA
>+	} Request = REQ_NA;
>+
>+	if (DCCEnabled == true) {
>+		if (DCCProgrammingAssumesScanDirectionUnknown == true) {
>+			if (DETBufferSize >= RequestHeight256Byte * ViewportWidth * BytePerPixel
>+					&& DETBufferSize
>+							>= 256 / RequestHeight256Byte
>+									* ViewportHeight) {
>+				Request = REQ_256Bytes;
>+			} else if ((DETBufferSize
>+					< RequestHeight256Byte * ViewportWidth * BytePerPixel
>+					&& (BytePerPixel == 2 || BytePerPixel == 4))
>+					|| (DETBufferSize
>+							< 256 / RequestHeight256Byte
>+									* ViewportHeight
>+							&& BytePerPixel == 8
>+							&& (TilingFormat == dm_sw_4kb_d
>+									|| TilingFormat
>+											== dm_sw_4kb_d_x
>+									|| TilingFormat
>+											== dm_sw_var_d
>+									|| TilingFormat
>+											== dm_sw_var_d_x
>+									|| TilingFormat
>+											== dm_sw_64kb_d
>+									|| TilingFormat
>+											== dm_sw_64kb_d_x
>+									|| TilingFormat
>+											== dm_sw_64kb_d_t
>+									|| TilingFormat
>+											== dm_sw_64kb_r_x))) {
>+				Request = REQ_128BytesNonContiguous;
>+			} else {
>+				Request = REQ_128BytesContiguous;
>+			}
>+		} else {
>+			if (BytePerPixel == 1) {
>+				if (ScanOrientation == dm_vert || SwathHeight == 16) {
>+					Request = REQ_256Bytes;
>+				} else {
>+					Request = REQ_128BytesContiguous;
>+				}
>+			} else if (BytePerPixel == 2) {
>+				if ((ScanOrientation == dm_vert && SwathHeight == 16) || (ScanOrientation != dm_vert && SwathHeight == 8)) {
>+					Request = REQ_256Bytes;
>+				} else if (ScanOrientation == dm_vert) {
>+					Request = REQ_128BytesContiguous;
>+				} else {
>+					Request = REQ_128BytesNonContiguous;
>+				}
>+			} else if (BytePerPixel == 4) {
>+				if (SwathHeight == 8) {
>+					Request = REQ_256Bytes;
>+				} else if (ScanOrientation == dm_vert) {
>+					Request = REQ_128BytesContiguous;
>+				} else {
>+					Request = REQ_128BytesNonContiguous;
>+				}
>+			} else if (BytePerPixel == 8) {
>+				if (TilingFormat == dm_sw_4kb_d || TilingFormat == dm_sw_4kb_d_x
>+						|| TilingFormat == dm_sw_var_d
>+						|| TilingFormat == dm_sw_var_d_x
>+						|| TilingFormat == dm_sw_64kb_d
>+						|| TilingFormat == dm_sw_64kb_d_x
>+						|| TilingFormat == dm_sw_64kb_d_t
>+						|| TilingFormat == dm_sw_64kb_r_x) {
>+					if ((ScanOrientation == dm_vert && SwathHeight == 8)
>+							|| (ScanOrientation != dm_vert
>+									&& SwathHeight == 4)) {
>+						Request = REQ_256Bytes;
>+					} else if (ScanOrientation != dm_vert) {
>+						Request = REQ_128BytesContiguous;
>+					} else {
>+						Request = REQ_128BytesNonContiguous;
>+					}
>+				} else {
>+					if (ScanOrientation != dm_vert || SwathHeight == 8) {
>+						Request = REQ_256Bytes;
>+					} else {
>+						Request = REQ_128BytesContiguous;
>+					}
>+				}
>+			}
>+		}
>+	} else {
>+		Request = REQ_NA;
>+	}
>+
>+	if (Request == REQ_256Bytes) {
>+		*MaxUncompressedBlock = 256;
>+		*MaxCompressedBlock = 256;
>+		*Independent64ByteBlock = false;
>+		MaximumDCCCompressionSurface = 4.0;
>+	} else if (Request == REQ_128BytesContiguous) {
>+		*MaxUncompressedBlock = 128;
>+		*MaxCompressedBlock = 128;
>+		*Independent64ByteBlock = false;
>+		MaximumDCCCompressionSurface = 2.0;
>+	} else if (Request == REQ_128BytesNonContiguous) {
>+		*MaxUncompressedBlock = 256;
>+		*MaxCompressedBlock = 64;
>+		*Independent64ByteBlock = true;
>+		MaximumDCCCompressionSurface = 4.0;
>+	} else {
>+		*MaxUncompressedBlock = 0;
>+		*MaxCompressedBlock = 0;
>+		*Independent64ByteBlock = 0;
>+		MaximumDCCCompressionSurface = 0.0;
>+	}
>+
>+	return MaximumDCCCompressionSurface;
>+}
>+
>+static double CalculatePrefetchSourceLines(
>+		struct display_mode_lib *mode_lib,
>+		double VRatio,
>+		double vtaps,
>+		bool Interlace,
>+		bool ProgressiveToInterlaceUnitInOPP,
>+		unsigned int SwathHeight,
>+		unsigned int ViewportYStart,
>+		double *VInitPreFill,
>+		unsigned int *MaxNumSwath)
>+{
>+	unsigned int MaxPartialSwath;
>+
>+	if (ProgressiveToInterlaceUnitInOPP)
>+		*VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1);
>+	else
>+		*VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
>+
>+	if (!mode_lib->vba.IgnoreViewportPositioning) {
>+
>+		*MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0;
>+
>+		if (*VInitPreFill > 1.0)
>+			MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight;
>+		else
>+			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2)
>+					% SwathHeight;
>+		MaxPartialSwath = dml_max(1U, MaxPartialSwath);
>+
>+	} else {
>+
>+		if (ViewportYStart != 0)
>+			dml_print(
>+					"WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n");
>+
>+		*MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1);
>+
>+		if (*VInitPreFill > 1.0)
>+			MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight;
>+		else
>+			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1)
>+					% SwathHeight;
>+	}
>+
>+	return *MaxNumSwath * SwathHeight + MaxPartialSwath;
>+}
>+
>+static unsigned int CalculateVMAndRowBytes(
>+		struct display_mode_lib *mode_lib,
>+		bool DCCEnable,
>+		unsigned int BlockHeight256Bytes,
>+		unsigned int BlockWidth256Bytes,
>+		enum source_format_class SourcePixelFormat,
>+		unsigned int SurfaceTiling,
>+		unsigned int BytePerPixel,
>+		enum scan_direction_class ScanDirection,
>+		unsigned int ViewportWidth,
>+		unsigned int ViewportHeight,
>+		unsigned int SwathWidth,
>+		bool GPUVMEnable,
>+		bool HostVMEnable,
>+		unsigned int HostVMMaxPageTableLevels,
>+		unsigned int HostVMCachedPageTableLevels,
>+		unsigned int VMMPageSize,
>+		unsigned int PTEBufferSizeInRequests,
>+		unsigned int Pitch,
>+		unsigned int DCCMetaPitch,
>+		unsigned int *MacroTileWidth,
>+		unsigned int *MetaRowByte,
>+		unsigned int *PixelPTEBytesPerRow,
>+		bool *PTEBufferSizeNotExceeded,
>+		unsigned int *dpte_row_width_ub,
>+		unsigned int *dpte_row_height,
>+		unsigned int *MetaRequestWidth,
>+		unsigned int *MetaRequestHeight,
>+		unsigned int *meta_row_width,
>+		unsigned int *meta_row_height,
>+		unsigned int *vm_group_bytes,
>+		long         *dpte_group_bytes,
>+		unsigned int *PixelPTEReqWidth,
>+		unsigned int *PixelPTEReqHeight,
>+		unsigned int *PTERequestSize,
>+		unsigned int *DPDE0BytesFrame,
>+		unsigned int *MetaPTEBytesFrame)
>+{
>+	unsigned int MPDEBytesFrame;
>+	unsigned int DCCMetaSurfaceBytes;
>+	unsigned int MacroTileSizeBytes;
>+	unsigned int MacroTileHeight;
>+	unsigned int ExtraDPDEBytesFrame;
>+	unsigned int PDEAndMetaPTEBytesFrame;
>+	unsigned int PixelPTEReqHeightPTEs;
>+
>+	if (DCCEnable == true) {
>+		*MetaRequestHeight = 8 * BlockHeight256Bytes;
>+		*MetaRequestWidth = 8 * BlockWidth256Bytes;
>+		if (ScanDirection == dm_horz) {
>+			*meta_row_height = *MetaRequestHeight;
>+			*meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth)
>+					+ *MetaRequestWidth;
>+			*MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0;
>+		} else {
>+			*meta_row_height = *MetaRequestWidth;
>+			*meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight)
>+					+ *MetaRequestHeight;
>+			*MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0;
>+		}
>+		if (ScanDirection == dm_horz) {
>+			DCCMetaSurfaceBytes = DCCMetaPitch
>+					* (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes)
>+							+ 64 * BlockHeight256Bytes) * BytePerPixel
>+					/ 256;
>+		} else {
>+			DCCMetaSurfaceBytes = DCCMetaPitch
>+					* (dml_ceil(
>+							(double) ViewportHeight - 1,
>+							64 * BlockHeight256Bytes)
>+							+ 64 * BlockHeight256Bytes) * BytePerPixel
>+					/ 256;
>+		}
>+		if (GPUVMEnable == true) {
>+			*MetaPTEBytesFrame = (dml_ceil(
>+					(double) (DCCMetaSurfaceBytes - VMMPageSize)
>+							/ (8 * VMMPageSize),
>+					1) + 1) * 64;
>+			MPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) - 2);
>+		} else {
>+			*MetaPTEBytesFrame = 0;
>+			MPDEBytesFrame = 0;
>+		}
>+	} else {
>+		*MetaPTEBytesFrame = 0;
>+		MPDEBytesFrame = 0;
>+		*MetaRowByte = 0;
>+	}
>+
>+	if (SurfaceTiling == dm_sw_linear || SurfaceTiling == dm_sw_gfx7_2d_thin_gl || SurfaceTiling == dm_sw_gfx7_2d_thin_lvp) {
>+		MacroTileSizeBytes = 256;
>+		MacroTileHeight = BlockHeight256Bytes;
>+	} else if (SurfaceTiling == dm_sw_4kb_s || SurfaceTiling == dm_sw_4kb_s_x
>+			|| SurfaceTiling == dm_sw_4kb_d || SurfaceTiling == dm_sw_4kb_d_x) {
>+		MacroTileSizeBytes = 4096;
>+		MacroTileHeight = 4 * BlockHeight256Bytes;
>+	} else if (SurfaceTiling == dm_sw_64kb_s || SurfaceTiling == dm_sw_64kb_s_t
>+			|| SurfaceTiling == dm_sw_64kb_s_x || SurfaceTiling == dm_sw_64kb_d
>+			|| SurfaceTiling == dm_sw_64kb_d_t || SurfaceTiling == dm_sw_64kb_d_x
>+			|| SurfaceTiling == dm_sw_64kb_r_x) {
>+		MacroTileSizeBytes = 65536;
>+		MacroTileHeight = 16 * BlockHeight256Bytes;
>+	} else {
>+		MacroTileSizeBytes = 262144;
>+		MacroTileHeight = 32 * BlockHeight256Bytes;
>+	}
>+	*MacroTileWidth = MacroTileSizeBytes / BytePerPixel / MacroTileHeight;
>+
>+	if (GPUVMEnable == true && (mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) > 2) {
>+		if (ScanDirection == dm_horz) {
>+			*DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1);
>+		} else {
>+			*DPDE0BytesFrame = 64 * (dml_ceil(((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes) / (8 * 2097152), 1) + 1);
>+		}
>+		ExtraDPDEBytesFrame = 128 * ((mode_lib->vba.GPUVMMaxPageTableLevels + 1) * (mode_lib->vba.HostVMMaxPageTableLevels + 1) - 3);
>+	} else {
>+		*DPDE0BytesFrame = 0;
>+		ExtraDPDEBytesFrame = 0;
>+	}
>+
>+	PDEAndMetaPTEBytesFrame = *MetaPTEBytesFrame + MPDEBytesFrame + *DPDE0BytesFrame
>+			+ ExtraDPDEBytesFrame;
>+
>+	if (HostVMEnable == true) {
>+		PDEAndMetaPTEBytesFrame = PDEAndMetaPTEBytesFrame * (1 + 8 * (HostVMMaxPageTableLevels - HostVMCachedPageTableLevels));
>+	}
>+
>+	if (GPUVMEnable == true) {
>+		double FractionOfPTEReturnDrop;
>+
>+		if (SurfaceTiling == dm_sw_linear) {
>+			PixelPTEReqHeightPTEs = 1;
>+			*PixelPTEReqHeight = 1;
>+			*PixelPTEReqWidth = 8.0 * VMMPageSize / BytePerPixel;
>+			*PTERequestSize = 64;
>+			FractionOfPTEReturnDrop = 0;
>+		} else if (MacroTileSizeBytes == 4096) {
>+			PixelPTEReqHeightPTEs = 1;
>+			*PixelPTEReqHeight = MacroTileHeight;
>+			*PixelPTEReqWidth = 8 * *MacroTileWidth;
>+			*PTERequestSize = 64;
>+			if (ScanDirection == dm_horz)
>+				FractionOfPTEReturnDrop = 0;
>+			else
>+				FractionOfPTEReturnDrop = 7 / 8;
>+		} else if (VMMPageSize == 4096 && MacroTileSizeBytes > 4096) {
>+			PixelPTEReqHeightPTEs = 16;
>+			*PixelPTEReqHeight = 16 * BlockHeight256Bytes;
>+			*PixelPTEReqWidth = 16 * BlockWidth256Bytes;
>+			*PTERequestSize = 128;
>+			FractionOfPTEReturnDrop = 0;
>+		} else {
>+			PixelPTEReqHeightPTEs = 1;
>+			*PixelPTEReqHeight = MacroTileHeight;
>+			*PixelPTEReqWidth = 8 * *MacroTileWidth;
>+			*PTERequestSize = 64;
>+			FractionOfPTEReturnDrop = 0;
>+		}
>+
>+		if (SurfaceTiling == dm_sw_linear) {
>+			*dpte_row_height = dml_min(128,
>+					1 << (unsigned int) dml_floor(
>+						dml_log2(
>+							(double) PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch),
>+						1));
>+			*dpte_row_width_ub = (dml_ceil((double) (Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
>+			*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
>+		} else if (ScanDirection == dm_horz) {
>+			*dpte_row_height = *PixelPTEReqHeight;
>+			*dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
>+			*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
>+		} else {
>+			*dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
>+			*dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight;
>+			*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize;
>+		}
>+		if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop)
>+				<= 64 * PTEBufferSizeInRequests) {
>+			*PTEBufferSizeNotExceeded = true;
>+		} else {
>+			*PTEBufferSizeNotExceeded = false;
>+		}
>+	} else {
>+		*PixelPTEBytesPerRow = 0;
>+		*PTEBufferSizeNotExceeded = true;
>+	}
>+	dml_print("DML: vm_bytes = meta_pte_bytes_per_frame (per_pipe) = MetaPTEBytesFrame = : %d\n", *MetaPTEBytesFrame);
>+
>+	if (HostVMEnable == true) {
>+		*PixelPTEBytesPerRow = *PixelPTEBytesPerRow * (1 + 8 * (HostVMMaxPageTableLevels - HostVMCachedPageTableLevels));
>+	}
>+
>+	if (HostVMEnable == true) {
>+		*vm_group_bytes = 512;
>+		*dpte_group_bytes = 512;
>+	} else if (GPUVMEnable == true) {
>+		*vm_group_bytes = 2048;
>+		if (SurfaceTiling != dm_sw_linear && PixelPTEReqHeightPTEs == 1 && ScanDirection != dm_horz) {
>+			*dpte_group_bytes = 512;
>+		} else {
>+			*dpte_group_bytes = 2048;
>+		}
>+	} else {
>+		*vm_group_bytes = 0;
>+		*dpte_group_bytes = 0;
>+	}
>+
>+	return PDEAndMetaPTEBytesFrame;
>+}
>+
>+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
>+		struct display_mode_lib *mode_lib)
>+{
>+	struct vba_vars_st *locals = &mode_lib->vba;
>+	unsigned int j, k;
>+
>+	mode_lib->vba.WritebackDISPCLK = 0.0;
>+	mode_lib->vba.DISPCLKWithRamping = 0;
>+	mode_lib->vba.DISPCLKWithoutRamping = 0;
>+	mode_lib->vba.GlobalDPPCLK = 0.0;
>+
>+	// DISPCLK and DPPCLK Calculation
>+	//
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.WritebackEnable[k]) {
>+			mode_lib->vba.WritebackDISPCLK =
>+					dml_max(
>+							mode_lib->vba.WritebackDISPCLK,
>+							CalculateWriteBackDISPCLK(
>+									mode_lib->vba.WritebackPixelFormat[k],
>+									mode_lib->vba.PixelClock[k],
>+									mode_lib->vba.WritebackHRatio[k],
>+									mode_lib->vba.WritebackVRatio[k],
>+									mode_lib->vba.WritebackLumaHTaps[k],
>+									mode_lib->vba.WritebackLumaVTaps[k],
>+									mode_lib->vba.WritebackChromaHTaps[k],
>+									mode_lib->vba.WritebackChromaVTaps[k],
>+									mode_lib->vba.WritebackDestinationWidth[k],
>+									mode_lib->vba.HTotal[k],
>+									mode_lib->vba.WritebackChromaLineBufferWidth));
>+		}
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.HRatio[k] > 1) {
>+			locals->PSCL_THROUGHPUT_LUMA[k] = dml_min(
>+					mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+					mode_lib->vba.MaxPSCLToLBThroughput
>+							* mode_lib->vba.HRatio[k]
>+							/ dml_ceil(
>+									mode_lib->vba.htaps[k]
>+											/ 6.0,
>+									1));
>+		} else {
>+			locals->PSCL_THROUGHPUT_LUMA[k] = dml_min(
>+					mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+					mode_lib->vba.MaxPSCLToLBThroughput);
>+		}
>+
>+		mode_lib->vba.DPPCLKUsingSingleDPPLuma =
>+				mode_lib->vba.PixelClock[k]
>+						* dml_max(
>+								mode_lib->vba.vtaps[k] / 6.0
>+										* dml_min(
>+												1.0,
>+												mode_lib->vba.HRatio[k]),
>+								dml_max(
>+										mode_lib->vba.HRatio[k]
>+												* mode_lib->vba.VRatio[k]
>+												/ locals->PSCL_THROUGHPUT_LUMA[k],
>+										1.0));
>+
>+		if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6)
>+				&& mode_lib->vba.DPPCLKUsingSingleDPPLuma
>+						< 2 * mode_lib->vba.PixelClock[k]) {
>+			mode_lib->vba.DPPCLKUsingSingleDPPLuma = 2 * mode_lib->vba.PixelClock[k];
>+		}
>+
>+		if ((mode_lib->vba.SourcePixelFormat[k] != dm_420_8
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_420_10)) {
>+			locals->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
>+			locals->DPPCLKUsingSingleDPP[k] =
>+					mode_lib->vba.DPPCLKUsingSingleDPPLuma;
>+		} else {
>+			if (mode_lib->vba.HRatio[k] > 1) {
>+				locals->PSCL_THROUGHPUT_CHROMA[k] =
>+						dml_min(
>+								mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+								mode_lib->vba.MaxPSCLToLBThroughput
>+										* mode_lib->vba.HRatio[k]
>+										/ 2
>+										/ dml_ceil(
>+												mode_lib->vba.HTAPsChroma[k]
>+														/ 6.0,
>+												1.0));
>+			} else {
>+				locals->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
>+						mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+						mode_lib->vba.MaxPSCLToLBThroughput);
>+			}
>+			mode_lib->vba.DPPCLKUsingSingleDPPChroma =
>+					mode_lib->vba.PixelClock[k]
>+							* dml_max(
>+									mode_lib->vba.VTAPsChroma[k]
>+											/ 6.0
>+											* dml_min(
>+													1.0,
>+													mode_lib->vba.HRatio[k]
>+															/ 2),
>+									dml_max(
>+											mode_lib->vba.HRatio[k]
>+													* mode_lib->vba.VRatio[k]
>+													/ 4
>+													/ locals->PSCL_THROUGHPUT_CHROMA[k],
>+											1.0));
>+
>+			if ((mode_lib->vba.HTAPsChroma[k] > 6 || mode_lib->vba.VTAPsChroma[k] > 6)
>+					&& mode_lib->vba.DPPCLKUsingSingleDPPChroma
>+							< 2 * mode_lib->vba.PixelClock[k]) {
>+				mode_lib->vba.DPPCLKUsingSingleDPPChroma = 2
>+						* mode_lib->vba.PixelClock[k];
>+			}
>+
>+			locals->DPPCLKUsingSingleDPP[k] = dml_max(
>+					mode_lib->vba.DPPCLKUsingSingleDPPLuma,
>+					mode_lib->vba.DPPCLKUsingSingleDPPChroma);
>+		}
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.BlendingAndTiming[k] != k)
>+			continue;
>+		if (mode_lib->vba.ODMCombineEnabled[k]) {
>+			mode_lib->vba.DISPCLKWithRamping =
>+					dml_max(
>+							mode_lib->vba.DISPCLKWithRamping,
>+							mode_lib->vba.PixelClock[k] / 2
>+									* (1
>+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+													/ 100)
>+									* (1
>+											+ mode_lib->vba.DISPCLKRampingMargin
>+													/ 100));
>+			mode_lib->vba.DISPCLKWithoutRamping =
>+					dml_max(
>+							mode_lib->vba.DISPCLKWithoutRamping,
>+							mode_lib->vba.PixelClock[k] / 2
>+									* (1
>+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+													/ 100));
>+		} else if (!mode_lib->vba.ODMCombineEnabled[k]) {
>+			mode_lib->vba.DISPCLKWithRamping =
>+					dml_max(
>+							mode_lib->vba.DISPCLKWithRamping,
>+							mode_lib->vba.PixelClock[k]
>+									* (1
>+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+													/ 100)
>+									* (1
>+											+ mode_lib->vba.DISPCLKRampingMargin
>+													/ 100));
>+			mode_lib->vba.DISPCLKWithoutRamping =
>+					dml_max(
>+							mode_lib->vba.DISPCLKWithoutRamping,
>+							mode_lib->vba.PixelClock[k]
>+									* (1
>+											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+													/ 100));
>+		}
>+	}
>+
>+	mode_lib->vba.DISPCLKWithRamping = dml_max(
>+			mode_lib->vba.DISPCLKWithRamping,
>+			mode_lib->vba.WritebackDISPCLK);
>+	mode_lib->vba.DISPCLKWithoutRamping = dml_max(
>+			mode_lib->vba.DISPCLKWithoutRamping,
>+			mode_lib->vba.WritebackDISPCLK);
>+
>+	ASSERT(mode_lib->vba.DISPCLKDPPCLKVCOSpeed != 0);
>+	mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(
>+			mode_lib->vba.DISPCLKWithRamping,
>+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
>+	mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(
>+			mode_lib->vba.DISPCLKWithoutRamping,
>+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
>+	mode_lib->vba.MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
>+			mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz,
>+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
>+	if (mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity
>+			> mode_lib->vba.MaxDispclkRoundedToDFSGranularity) {
>+		mode_lib->vba.DISPCLK_calculated =
>+				mode_lib->vba.DISPCLKWithoutRampingRoundedToDFSGranularity;
>+	} else if (mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity
>+			> mode_lib->vba.MaxDispclkRoundedToDFSGranularity) {
>+		mode_lib->vba.DISPCLK_calculated = mode_lib->vba.MaxDispclkRoundedToDFSGranularity;
>+	} else {
>+		mode_lib->vba.DISPCLK_calculated =
>+				mode_lib->vba.DISPCLKWithRampingRoundedToDFSGranularity;
>+	}
>+	DTRACE("   dispclk_mhz (calculated) = %f", mode_lib->vba.DISPCLK_calculated);
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.DPPCLK_calculated[k] = locals->DPPCLKUsingSingleDPP[k]
>+				/ mode_lib->vba.DPPPerPlane[k]
>+				* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
>+		mode_lib->vba.GlobalDPPCLK = dml_max(
>+				mode_lib->vba.GlobalDPPCLK,
>+				mode_lib->vba.DPPCLK_calculated[k]);
>+	}
>+	mode_lib->vba.GlobalDPPCLK = RoundToDFSGranularityUp(
>+			mode_lib->vba.GlobalDPPCLK,
>+			mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.DPPCLK_calculated[k] = mode_lib->vba.GlobalDPPCLK / 255
>+				* dml_ceil(
>+						mode_lib->vba.DPPCLK_calculated[k] * 255
>+								/ mode_lib->vba.GlobalDPPCLK,
>+						1);
>+		DTRACE("   dppclk_mhz[%i] (calculated) = %f", k, mode_lib->vba.DPPCLK_calculated[k]);
>+	}
>+
>+	// Urgent and B P-State/DRAM Clock Change Watermark
>+	DTRACE("   dcfclk_mhz         = %f", mode_lib->vba.DCFCLK);
>+	DTRACE("   return_bw_to_dcn   = %f", mode_lib->vba.ReturnBandwidthToDCN);
>+	DTRACE("   return_bus_bw      = %f", mode_lib->vba.ReturnBW);
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		bool MainPlaneDoesODMCombine = false;
>+
>+		if (mode_lib->vba.SourceScan[k] == dm_horz)
>+			locals->SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportWidth[k];
>+		else
>+			locals->SwathWidthSingleDPPY[k] = mode_lib->vba.ViewportHeight[k];
>+
>+		if (mode_lib->vba.ODMCombineEnabled[k] == true)
>+			MainPlaneDoesODMCombine = true;
>+		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j)
>+			if (mode_lib->vba.BlendingAndTiming[k] == j
>+					&& mode_lib->vba.ODMCombineEnabled[j] == true)
>+				MainPlaneDoesODMCombine = true;
>+
>+		if (MainPlaneDoesODMCombine == true)
>+			locals->SwathWidthY[k] = dml_min(
>+					(double) locals->SwathWidthSingleDPPY[k],
>+					dml_round(
>+							mode_lib->vba.HActive[k] / 2.0
>+									* mode_lib->vba.HRatio[k]));
>+		else
>+			locals->SwathWidthY[k] = locals->SwathWidthSingleDPPY[k]
>+					/ mode_lib->vba.DPPPerPlane[k];
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
>+			locals->BytePerPixelDETY[k] = 8;
>+			locals->BytePerPixelDETC[k] = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
>+			locals->BytePerPixelDETY[k] = 4;
>+			locals->BytePerPixelDETC[k] = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16 || mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
>+			locals->BytePerPixelDETY[k] = 2;
>+			locals->BytePerPixelDETC[k] = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8 || mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
>+			locals->BytePerPixelDETY[k] = 1;
>+			locals->BytePerPixelDETC[k] = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
>+			locals->BytePerPixelDETY[k] = 1;
>+			locals->BytePerPixelDETC[k] = 2;
>+		} else { // dm_420_10
>+			locals->BytePerPixelDETY[k] = 4.0 / 3.0;
>+			locals->BytePerPixelDETC[k] = 8.0 / 3.0;
>+		}
>+	}
>+
>+	mode_lib->vba.TotalDataReadBandwidth = 0.0;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		locals->ReadBandwidthPlaneLuma[k] = locals->SwathWidthSingleDPPY[k]
>+				* dml_ceil(locals->BytePerPixelDETY[k], 1)
>+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
>+				* mode_lib->vba.VRatio[k];
>+		locals->ReadBandwidthPlaneChroma[k] = locals->SwathWidthSingleDPPY[k]
>+				/ 2 * dml_ceil(locals->BytePerPixelDETC[k], 2)
>+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k])
>+				* mode_lib->vba.VRatio[k] / 2;
>+		DTRACE(
>+				"   read_bw[%i] = %fBps",
>+				k,
>+				locals->ReadBandwidthPlaneLuma[k]
>+						+ locals->ReadBandwidthPlaneChroma[k]);
>+		mode_lib->vba.TotalDataReadBandwidth += locals->ReadBandwidthPlaneLuma[k]
>+				+ locals->ReadBandwidthPlaneChroma[k];
>+	}
>+
>+	// DCFCLK Deep Sleep
>+	CalculateDCFCLKDeepSleep(
>+		mode_lib,
>+		mode_lib->vba.NumberOfActivePlanes,
>+		locals->BytePerPixelDETY,
>+		locals->BytePerPixelDETC,
>+		mode_lib->vba.VRatio,
>+		locals->SwathWidthY,
>+		mode_lib->vba.DPPPerPlane,
>+		mode_lib->vba.HRatio,
>+		mode_lib->vba.PixelClock,
>+		locals->PSCL_THROUGHPUT_LUMA,
>+		locals->PSCL_THROUGHPUT_CHROMA,
>+		locals->DPPCLK,
>+		&mode_lib->vba.DCFCLKDeepSleep);
>+
>+	// DSCCLK
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
>+			locals->DSCCLK_calculated[k] = 0.0;
>+		} else {
>+			if (mode_lib->vba.OutputFormat[k] == dm_420
>+					|| mode_lib->vba.OutputFormat[k] == dm_n422)
>+				mode_lib->vba.DSCFormatFactor = 2;
>+			else
>+				mode_lib->vba.DSCFormatFactor = 1;
>+			if (mode_lib->vba.ODMCombineEnabled[k])
>+				locals->DSCCLK_calculated[k] =
>+						mode_lib->vba.PixelClockBackEnd[k] / 6
>+								/ mode_lib->vba.DSCFormatFactor
>+								/ (1
>+										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+												/ 100);
>+			else
>+				locals->DSCCLK_calculated[k] =
>+						mode_lib->vba.PixelClockBackEnd[k] / 3
>+								/ mode_lib->vba.DSCFormatFactor
>+								/ (1
>+										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+												/ 100);
>+		}
>+	}
>+
>+	// DSC Delay
>+	// TODO
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		double bpp = mode_lib->vba.OutputBpp[k];
>+		unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k];
>+
>+		if (mode_lib->vba.DSCEnabled[k] && bpp != 0) {
>+			if (!mode_lib->vba.ODMCombineEnabled[k]) {
>+				locals->DSCDelay[k] =
>+						dscceComputeDelay(
>+								mode_lib->vba.DSCInputBitPerComponent[k],
>+								bpp,
>+								dml_ceil(
>+										(double) mode_lib->vba.HActive[k]
>+												/ mode_lib->vba.NumberOfDSCSlices[k],
>+										1),
>+								slices,
>+								mode_lib->vba.OutputFormat[k])
>+								+ dscComputeDelay(
>+										mode_lib->vba.OutputFormat[k]);
>+			} else {
>+				locals->DSCDelay[k] =
>+						2
>+								* (dscceComputeDelay(
>+										mode_lib->vba.DSCInputBitPerComponent[k],
>+										bpp,
>+										dml_ceil(
>+												(double) mode_lib->vba.HActive[k]
>+														/ mode_lib->vba.NumberOfDSCSlices[k],
>+												1),
>+										slices / 2.0,
>+										mode_lib->vba.OutputFormat[k])
>+										+ dscComputeDelay(
>+												mode_lib->vba.OutputFormat[k]));
>+			}
>+			locals->DSCDelay[k] = locals->DSCDelay[k]
>+					* mode_lib->vba.PixelClock[k]
>+					/ mode_lib->vba.PixelClockBackEnd[k];
>+		} else {
>+			locals->DSCDelay[k] = 0;
>+		}
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
>+		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) // NumberOfPlanes
>+			if (j != k && mode_lib->vba.BlendingAndTiming[k] == j
>+					&& mode_lib->vba.DSCEnabled[j])
>+				locals->DSCDelay[k] = locals->DSCDelay[j];
>+
>+	// Prefetch
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		unsigned int PDEAndMetaPTEBytesFrameY;
>+		unsigned int PixelPTEBytesPerRowY;
>+		unsigned int MetaRowByteY;
>+		unsigned int MetaRowByteC;
>+		unsigned int PDEAndMetaPTEBytesFrameC;
>+		unsigned int PixelPTEBytesPerRowC;
>+		bool         PTEBufferSizeNotExceededY;
>+		bool         PTEBufferSizeNotExceededC;
>+
>+		Calculate256BBlockSizes(
>+				mode_lib->vba.SourcePixelFormat[k],
>+				mode_lib->vba.SurfaceTiling[k],
>+				dml_ceil(locals->BytePerPixelDETY[k], 1),
>+				dml_ceil(locals->BytePerPixelDETC[k], 2),
>+				&locals->BlockHeight256BytesY[k],
>+				&locals->BlockHeight256BytesC[k],
>+				&locals->BlockWidth256BytesY[k],
>+				&locals->BlockWidth256BytesC[k]);
>+
>+		locals->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
>+				mode_lib,
>+				mode_lib->vba.VRatio[k],
>+				mode_lib->vba.vtaps[k],
>+				mode_lib->vba.Interlace[k],
>+				mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+				mode_lib->vba.SwathHeightY[k],
>+				mode_lib->vba.ViewportYStartY[k],
>+				&locals->VInitPreFillY[k],
>+				&locals->MaxNumSwathY[k]);
>+
>+		if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_8)) {
>+			PDEAndMetaPTEBytesFrameC =
>+					CalculateVMAndRowBytes(
>+							mode_lib,
>+							mode_lib->vba.DCCEnable[k],
>+							locals->BlockHeight256BytesC[k],
>+							locals->BlockWidth256BytesC[k],
>+							mode_lib->vba.SourcePixelFormat[k],
>+							mode_lib->vba.SurfaceTiling[k],
>+							dml_ceil(
>+									locals->BytePerPixelDETC[k],
>+									2),
>+							mode_lib->vba.SourceScan[k],
>+							mode_lib->vba.ViewportWidth[k] / 2,
>+							mode_lib->vba.ViewportHeight[k] / 2,
>+							locals->SwathWidthY[k] / 2,
>+							mode_lib->vba.GPUVMEnable,
>+							mode_lib->vba.HostVMEnable,
>+							mode_lib->vba.HostVMMaxPageTableLevels,
>+							mode_lib->vba.HostVMCachedPageTableLevels,
>+							mode_lib->vba.VMMPageSize,
>+							mode_lib->vba.PTEBufferSizeInRequestsChroma,
>+							mode_lib->vba.PitchC[k],
>+							mode_lib->vba.DCCMetaPitchC[k],
>+							&locals->MacroTileWidthC[k],
>+							&MetaRowByteC,
>+							&PixelPTEBytesPerRowC,
>+							&PTEBufferSizeNotExceededC,
>+							&locals->dpte_row_width_chroma_ub[k],
>+							&locals->dpte_row_height_chroma[k],
>+							&locals->meta_req_width_chroma[k],
>+							&locals->meta_req_height_chroma[k],
>+							&locals->meta_row_width_chroma[k],
>+							&locals->meta_row_height_chroma[k],
>+							&locals->vm_group_bytes_chroma,
>+							&locals->dpte_group_bytes_chroma,
>+							&locals->PixelPTEReqWidthC[k],
>+							&locals->PixelPTEReqHeightC[k],
>+							&locals->PTERequestSizeC[k],
>+							&locals->dpde0_bytes_per_frame_ub_c[k],
>+							&locals->meta_pte_bytes_per_frame_ub_c[k]);
>+
>+			locals->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
>+					mode_lib,
>+					mode_lib->vba.VRatio[k] / 2,
>+					mode_lib->vba.VTAPsChroma[k],
>+					mode_lib->vba.Interlace[k],
>+					mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+					mode_lib->vba.SwathHeightC[k],
>+					mode_lib->vba.ViewportYStartC[k],
>+					&locals->VInitPreFillC[k],
>+					&locals->MaxNumSwathC[k]);
>+		} else {
>+			PixelPTEBytesPerRowC = 0;
>+			PDEAndMetaPTEBytesFrameC = 0;
>+			MetaRowByteC = 0;
>+			locals->MaxNumSwathC[k] = 0;
>+			locals->PrefetchSourceLinesC[k] = 0;
>+			locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma;
>+		}
>+
>+		PDEAndMetaPTEBytesFrameY = CalculateVMAndRowBytes(
>+				mode_lib,
>+				mode_lib->vba.DCCEnable[k],
>+				locals->BlockHeight256BytesY[k],
>+				locals->BlockWidth256BytesY[k],
>+				mode_lib->vba.SourcePixelFormat[k],
>+				mode_lib->vba.SurfaceTiling[k],
>+				dml_ceil(locals->BytePerPixelDETY[k], 1),
>+				mode_lib->vba.SourceScan[k],
>+				mode_lib->vba.ViewportWidth[k],
>+				mode_lib->vba.ViewportHeight[k],
>+				locals->SwathWidthY[k],
>+				mode_lib->vba.GPUVMEnable,
>+				mode_lib->vba.HostVMEnable,
>+				mode_lib->vba.HostVMMaxPageTableLevels,
>+				mode_lib->vba.HostVMCachedPageTableLevels,
>+				mode_lib->vba.VMMPageSize,
>+				locals->PTEBufferSizeInRequestsForLuma,
>+				mode_lib->vba.PitchY[k],
>+				mode_lib->vba.DCCMetaPitchY[k],
>+				&locals->MacroTileWidthY[k],
>+				&MetaRowByteY,
>+				&PixelPTEBytesPerRowY,
>+				&PTEBufferSizeNotExceededY,
>+				&locals->dpte_row_width_luma_ub[k],
>+				&locals->dpte_row_height[k],
>+				&locals->meta_req_width[k],
>+				&locals->meta_req_height[k],
>+				&locals->meta_row_width[k],
>+				&locals->meta_row_height[k],
>+				&locals->vm_group_bytes[k],
>+				&locals->dpte_group_bytes[k],
>+				&locals->PixelPTEReqWidthY[k],
>+				&locals->PixelPTEReqHeightY[k],
>+				&locals->PTERequestSizeY[k],
>+				&locals->dpde0_bytes_per_frame_ub_l[k],
>+				&locals->meta_pte_bytes_per_frame_ub_l[k]);
>+
>+		locals->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
>+		locals->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY
>+				+ PDEAndMetaPTEBytesFrameC;
>+		locals->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
>+
>+		CalculateActiveRowBandwidth(
>+				mode_lib->vba.GPUVMEnable,
>+				mode_lib->vba.SourcePixelFormat[k],
>+				mode_lib->vba.VRatio[k],
>+				mode_lib->vba.DCCEnable[k],
>+				mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
>+				MetaRowByteY,
>+				MetaRowByteC,
>+				locals->meta_row_height[k],
>+				locals->meta_row_height_chroma[k],
>+				PixelPTEBytesPerRowY,
>+				PixelPTEBytesPerRowC,
>+				locals->dpte_row_height[k],
>+				locals->dpte_row_height_chroma[k],
>+				&locals->meta_row_bw[k],
>+				&locals->dpte_row_bw[k]);
>+	}
>+
>+	mode_lib->vba.TotalDCCActiveDPP = 0;
>+	mode_lib->vba.TotalActiveDPP = 0;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP
>+				+ mode_lib->vba.DPPPerPlane[k];
>+		if (mode_lib->vba.DCCEnable[k])
>+			mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP
>+					+ mode_lib->vba.DPPPerPlane[k];
>+	}
>+
>+	mode_lib->vba.UrgentOutOfOrderReturnPerChannel = dml_max3(
>+			mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
>+			mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
>+			mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly);
>+
>+	mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency =
>+			(mode_lib->vba.RoundTripPingLatencyCycles + 32) / mode_lib->vba.DCFCLK
>+					+ mode_lib->vba.UrgentOutOfOrderReturnPerChannel
>+							* mode_lib->vba.NumberOfChannels
>+							/ mode_lib->vba.ReturnBW;
>+
>+	mode_lib->vba.UrgentExtraLatency = CalculateExtraLatency(
>+			mode_lib->vba.UrgentRoundTripAndOutOfOrderLatency,
>+			mode_lib->vba.TotalActiveDPP,
>+			mode_lib->vba.PixelChunkSizeInKByte,
>+			mode_lib->vba.TotalDCCActiveDPP,
>+			mode_lib->vba.MetaChunkSize,
>+			mode_lib->vba.ReturnBW,
>+			mode_lib->vba.GPUVMEnable,
>+			mode_lib->vba.HostVMEnable,
>+			mode_lib->vba.NumberOfActivePlanes,
>+			mode_lib->vba.DPPPerPlane,
>+			locals->dpte_group_bytes,
>+			mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
>+			mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
>+			mode_lib->vba.HostVMMaxPageTableLevels,
>+			mode_lib->vba.HostVMCachedPageTableLevels);
>+
>+
>+	mode_lib->vba.TCalc = 24.0 / mode_lib->vba.DCFCLKDeepSleep;
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+			if (mode_lib->vba.WritebackEnable[k] == true) {
>+				locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
>+						mode_lib->vba.WritebackLatency
>+								+ CalculateWriteBackDelay(
>+										mode_lib->vba.WritebackPixelFormat[k],
>+										mode_lib->vba.WritebackHRatio[k],
>+										mode_lib->vba.WritebackVRatio[k],
>+										mode_lib->vba.WritebackLumaHTaps[k],
>+										mode_lib->vba.WritebackLumaVTaps[k],
>+										mode_lib->vba.WritebackChromaHTaps[k],
>+										mode_lib->vba.WritebackChromaVTaps[k],
>+										mode_lib->vba.WritebackDestinationWidth[k])
>+										/ mode_lib->vba.DISPCLK;
>+			} else
>+				locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] = 0;
>+			for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {
>+				if (mode_lib->vba.BlendingAndTiming[j] == k
>+						&& mode_lib->vba.WritebackEnable[j] == true) {
>+					locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
>+							dml_max(
>+									locals->WritebackDelay[mode_lib->vba.VoltageLevel][k],
>+									mode_lib->vba.WritebackLatency
>+											+ CalculateWriteBackDelay(
>+													mode_lib->vba.WritebackPixelFormat[j],
>+													mode_lib->vba.WritebackHRatio[j],
>+													mode_lib->vba.WritebackVRatio[j],
>+													mode_lib->vba.WritebackLumaHTaps[j],
>+													mode_lib->vba.WritebackLumaVTaps[j],
>+													mode_lib->vba.WritebackChromaHTaps[j],
>+													mode_lib->vba.WritebackChromaVTaps[j],
>+													mode_lib->vba.WritebackDestinationWidth[j])
>+													/ mode_lib->vba.DISPCLK);
>+				}
>+			}
>+		}
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
>+		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j)
>+			if (mode_lib->vba.BlendingAndTiming[k] == j)
>+				locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] =
>+						locals->WritebackDelay[mode_lib->vba.VoltageLevel][j];
>+
>+	mode_lib->vba.VStartupLines = 13;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		locals->MaxVStartupLines[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k] - dml_max(1.0, dml_ceil(locals->WritebackDelay[mode_lib->vba.VoltageLevel][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1));
>+	}
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k)
>+		locals->MaximumMaxVStartupLines = dml_max(locals->MaximumMaxVStartupLines, locals->MaxVStartupLines[k]);
>+
>+	// We don't really care to iterate between the various prefetch modes
>+	//mode_lib->vba.PrefetchERROR = CalculateMinAndMaxPrefetchMode(mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, &mode_lib->vba.MinPrefetchMode, &mode_lib->vba.MaxPrefetchMode);
>+	mode_lib->vba.UrgentLatency = dml_max3(mode_lib->vba.UrgentLatencyPixelDataOnly, mode_lib->vba.UrgentLatencyPixelMixedWithVMData, mode_lib->vba.UrgentLatencyVMDataOnly);
>+
>+	do {
>+		double MaxTotalRDBandwidth = 0;
>+		double MaxTotalRDBandwidthNoUrgentBurst = 0;
>+		bool DestinationLineTimesForPrefetchLessThan2 = false;
>+		bool VRatioPrefetchMoreThan4 = false;
>+		double TWait = CalculateTWait(
>+				mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
>+				mode_lib->vba.DRAMClockChangeLatency,
>+				mode_lib->vba.UrgentLatency,
>+				mode_lib->vba.SREnterPlusExitTime);
>+
>+		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+			Pipe   myPipe;
>+			HostVM myHostVM;
>+
>+			if (mode_lib->vba.XFCEnabled[k] == true) {
>+				mode_lib->vba.XFCRemoteSurfaceFlipDelay =
>+						CalculateRemoteSurfaceFlipDelay(
>+								mode_lib,
>+								mode_lib->vba.VRatio[k],
>+								locals->SwathWidthY[k],
>+								dml_ceil(
>+										locals->BytePerPixelDETY[k],
>+										1),
>+								mode_lib->vba.HTotal[k]
>+										/ mode_lib->vba.PixelClock[k],
>+								mode_lib->vba.XFCTSlvVupdateOffset,
>+								mode_lib->vba.XFCTSlvVupdateWidth,
>+								mode_lib->vba.XFCTSlvVreadyOffset,
>+								mode_lib->vba.XFCXBUFLatencyTolerance,
>+								mode_lib->vba.XFCFillBWOverhead,
>+								mode_lib->vba.XFCSlvChunkSize,
>+								mode_lib->vba.XFCBusTransportTime,
>+								mode_lib->vba.TCalc,
>+								TWait,
>+								&mode_lib->vba.SrcActiveDrainRate,
>+								&mode_lib->vba.TInitXFill,
>+								&mode_lib->vba.TslvChk);
>+			} else {
>+				mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0;
>+			}
>+
>+			myPipe.DPPCLK = locals->DPPCLK[k];
>+			myPipe.DISPCLK = mode_lib->vba.DISPCLK;
>+			myPipe.PixelClock = mode_lib->vba.PixelClock[k];
>+			myPipe.DCFCLKDeepSleep = mode_lib->vba.DCFCLKDeepSleep;
>+			myPipe.DPPPerPlane = mode_lib->vba.DPPPerPlane[k];
>+			myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
>+			myPipe.SourceScan = mode_lib->vba.SourceScan[k];
>+			myPipe.BlockWidth256BytesY = locals->BlockWidth256BytesY[k];
>+			myPipe.BlockHeight256BytesY = locals->BlockHeight256BytesY[k];
>+			myPipe.BlockWidth256BytesC = locals->BlockWidth256BytesC[k];
>+			myPipe.BlockHeight256BytesC = locals->BlockHeight256BytesC[k];
>+			myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
>+			myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
>+			myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
>+			myPipe.HTotal = mode_lib->vba.HTotal[k];
>+
>+
>+			myHostVM.Enable = mode_lib->vba.HostVMEnable;
>+			myHostVM.MaxPageTableLevels = mode_lib->vba.HostVMMaxPageTableLevels;
>+			myHostVM.CachedPageTableLevels = mode_lib->vba.HostVMCachedPageTableLevels;
>+
>+			mode_lib->vba.ErrorResult[k] =
>+					CalculatePrefetchSchedule(
>+							mode_lib,
>+							mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
>+							mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
>+							&myPipe,
>+							locals->DSCDelay[k],
>+							mode_lib->vba.DPPCLKDelaySubtotal,
>+							mode_lib->vba.DPPCLKDelaySCL,
>+							mode_lib->vba.DPPCLKDelaySCLLBOnly,
>+							mode_lib->vba.DPPCLKDelayCNVCFormater,
>+							mode_lib->vba.DPPCLKDelayCNVCCursor,
>+							mode_lib->vba.DISPCLKDelaySubtotal,
>+							(unsigned int) (locals->SwathWidthY[k]
>+									/ mode_lib->vba.HRatio[k]),
>+							mode_lib->vba.OutputFormat[k],
>+							mode_lib->vba.MaxInterDCNTileRepeaters,
>+							dml_min(mode_lib->vba.VStartupLines, locals->MaxVStartupLines[k]),
>+							locals->MaxVStartupLines[k],
>+							mode_lib->vba.GPUVMMaxPageTableLevels,
>+							mode_lib->vba.GPUVMEnable,
>+							&myHostVM,
>+							mode_lib->vba.DynamicMetadataEnable[k],
>+							mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
>+							mode_lib->vba.DynamicMetadataTransmittedBytes[k],
>+							mode_lib->vba.DCCEnable[k],
>+							mode_lib->vba.UrgentLatency,
>+							mode_lib->vba.UrgentExtraLatency,
>+							mode_lib->vba.TCalc,
>+							locals->PDEAndMetaPTEBytesFrame[k],
>+							locals->MetaRowByte[k],
>+							locals->PixelPTEBytesPerRow[k],
>+							locals->PrefetchSourceLinesY[k],
>+							locals->SwathWidthY[k],
>+							locals->BytePerPixelDETY[k],
>+							locals->VInitPreFillY[k],
>+							locals->MaxNumSwathY[k],
>+							locals->PrefetchSourceLinesC[k],
>+							locals->BytePerPixelDETC[k],
>+							locals->VInitPreFillC[k],
>+							locals->MaxNumSwathC[k],
>+							mode_lib->vba.SwathHeightY[k],
>+							mode_lib->vba.SwathHeightC[k],
>+							TWait,
>+							mode_lib->vba.XFCEnabled[k],
>+							mode_lib->vba.XFCRemoteSurfaceFlipDelay,
>+							mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+							&locals->DSTXAfterScaler[k],
>+							&locals->DSTYAfterScaler[k],
>+							&locals->DestinationLinesForPrefetch[k],
>+							&locals->PrefetchBandwidth[k],
>+							&locals->DestinationLinesToRequestVMInVBlank[k],
>+							&locals->DestinationLinesToRequestRowInVBlank[k],
>+							&locals->VRatioPrefetchY[k],
>+							&locals->VRatioPrefetchC[k],
>+							&locals->RequiredPrefetchPixDataBWLuma[k],
>+							&locals->RequiredPrefetchPixDataBWChroma[k],
>+							&locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata,
>+							&locals->Tno_bw[k],
>+							&locals->prefetch_vmrow_bw[k],
>+							&locals->swath_width_luma_ub[k],
>+							&locals->swath_width_chroma_ub[k],
>+							&mode_lib->vba.VUpdateOffsetPix[k],
>+							&mode_lib->vba.VUpdateWidthPix[k],
>+							&mode_lib->vba.VReadyOffsetPix[k]);
>+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+				locals->VStartup[k] = dml_min(
>+						mode_lib->vba.VStartupLines,
>+						locals->MaxVStartupLines[k]);
>+				if (locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata
>+						!= 0) {
>+					locals->VStartup[k] =
>+							locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
>+				}
>+			} else {
>+				locals->VStartup[k] =
>+						dml_min(
>+								mode_lib->vba.VStartupLines,
>+								locals->MaxVStartupLines[mode_lib->vba.BlendingAndTiming[k]]);
>+			}
>+		}
>+
>+		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+			unsigned int m;
>+
>+			locals->cursor_bw[k] = 0;
>+			locals->cursor_bw_pre[k] = 0;
>+			for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
>+				locals->cursor_bw[k] += mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
>+				locals->cursor_bw_pre[k] += mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPrefetchY[k];
>+			}
>+
>+			CalculateUrgentBurstFactor(
>+					mode_lib->vba.DETBufferSizeInKByte,
>+					mode_lib->vba.SwathHeightY[k],
>+					mode_lib->vba.SwathHeightC[k],
>+					locals->SwathWidthY[k],
>+					mode_lib->vba.HTotal[k] /
>+					mode_lib->vba.PixelClock[k],
>+					mode_lib->vba.UrgentLatency,
>+					mode_lib->vba.CursorBufferSize,
>+					mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1],
>+					dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]),
>+					mode_lib->vba.VRatio[k],
>+					locals->VRatioPrefetchY[k],
>+					locals->VRatioPrefetchC[k],
>+					locals->BytePerPixelDETY[k],
>+					locals->BytePerPixelDETC[k],
>+					&locals->UrgentBurstFactorCursor[k],
>+					&locals->UrgentBurstFactorCursorPre[k],
>+					&locals->UrgentBurstFactorLuma[k],
>+					&locals->UrgentBurstFactorLumaPre[k],
>+					&locals->UrgentBurstFactorChroma[k],
>+					&locals->UrgentBurstFactorChromaPre[k],
>+					&locals->NotEnoughUrgentLatencyHiding,
>+					&locals->NotEnoughUrgentLatencyHidingPre);
>+
>+			if (mode_lib->vba.UseUrgentBurstBandwidth == false) {
>+				locals->UrgentBurstFactorLuma[k] = 1;
>+				locals->UrgentBurstFactorChroma[k] = 1;
>+				locals->UrgentBurstFactorCursor[k] = 1;
>+				locals->UrgentBurstFactorLumaPre[k] = 1;
>+				locals->UrgentBurstFactorChromaPre[k] = 1;
>+				locals->UrgentBurstFactorCursorPre[k] = 1;
>+			}
>+
>+			MaxTotalRDBandwidth = MaxTotalRDBandwidth +
>+				dml_max3(locals->prefetch_vmrow_bw[k],
>+					locals->ReadBandwidthPlaneLuma[k] * locals->UrgentBurstFactorLuma[k]
>+					+ locals->ReadBandwidthPlaneChroma[k] * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k]
>+					* locals->UrgentBurstFactorCursor[k] + locals->meta_row_bw[k] + locals->dpte_row_bw[k],
>+					locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] + locals->RequiredPrefetchPixDataBWChroma[k]
>+					* locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
>+
>+			MaxTotalRDBandwidthNoUrgentBurst = MaxTotalRDBandwidthNoUrgentBurst +
>+				dml_max3(locals->prefetch_vmrow_bw[k],
>+					locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k] + locals->cursor_bw[k]
>+					+ locals->meta_row_bw[k] + locals->dpte_row_bw[k],
>+					locals->RequiredPrefetchPixDataBWLuma[k] + locals->RequiredPrefetchPixDataBWChroma[k] + locals->cursor_bw_pre[k]);
>+
>+			if (locals->DestinationLinesForPrefetch[k] < 2)
>+				DestinationLineTimesForPrefetchLessThan2 = true;
>+			if (locals->VRatioPrefetchY[k] > 4 || locals->VRatioPrefetchC[k] > 4)
>+				VRatioPrefetchMoreThan4 = true;
>+		}
>+		mode_lib->vba.FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / mode_lib->vba.ReturnBW;
>+
>+		if (MaxTotalRDBandwidth <= mode_lib->vba.ReturnBW && locals->NotEnoughUrgentLatencyHiding == 0 && locals->NotEnoughUrgentLatencyHidingPre == 0 && !VRatioPrefetchMoreThan4
>+				&& !DestinationLineTimesForPrefetchLessThan2)
>+			mode_lib->vba.PrefetchModeSupported = true;
>+		else {
>+			mode_lib->vba.PrefetchModeSupported = false;
>+			dml_print(
>+					"DML: CalculatePrefetchSchedule ***failed***. Bandwidth violation. Results are NOT valid\n");
>+		}
>+
>+		if (mode_lib->vba.PrefetchModeSupported == true) {
>+			mode_lib->vba.BandwidthAvailableForImmediateFlip = mode_lib->vba.ReturnBW;
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				mode_lib->vba.BandwidthAvailableForImmediateFlip =
>+						mode_lib->vba.BandwidthAvailableForImmediateFlip
>+							- dml_max(
>+								locals->ReadBandwidthPlaneLuma[k] * locals->UrgentBurstFactorLuma[k]
>+								+ locals->ReadBandwidthPlaneChroma[k] * locals->UrgentBurstFactorChroma[k]
>+								+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
>+								locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k] +
>+								locals->RequiredPrefetchPixDataBWChroma[k] * locals->UrgentBurstFactorChromaPre[k] +
>+								locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
>+			}
>+
>+			mode_lib->vba.TotImmediateFlipBytes = 0;
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes + locals->PDEAndMetaPTEBytesFrame[k] + locals->MetaRowByte[k] + locals->PixelPTEBytesPerRow[k];
>+			}
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				CalculateFlipSchedule(
>+						mode_lib,
>+						mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
>+						mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
>+						mode_lib->vba.UrgentExtraLatency,
>+						mode_lib->vba.UrgentLatency,
>+						mode_lib->vba.GPUVMMaxPageTableLevels,
>+						mode_lib->vba.HostVMEnable,
>+						mode_lib->vba.HostVMMaxPageTableLevels,
>+						mode_lib->vba.HostVMCachedPageTableLevels,
>+						mode_lib->vba.GPUVMEnable,
>+						locals->PDEAndMetaPTEBytesFrame[k],
>+						locals->MetaRowByte[k],
>+						locals->PixelPTEBytesPerRow[k],
>+						mode_lib->vba.BandwidthAvailableForImmediateFlip,
>+						mode_lib->vba.TotImmediateFlipBytes,
>+						mode_lib->vba.SourcePixelFormat[k],
>+						mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
>+						mode_lib->vba.VRatio[k],
>+						locals->Tno_bw[k],
>+						mode_lib->vba.DCCEnable[k],
>+						locals->dpte_row_height[k],
>+						locals->meta_row_height[k],
>+						locals->dpte_row_height_chroma[k],
>+						locals->meta_row_height_chroma[k],
>+						&locals->DestinationLinesToRequestVMInImmediateFlip[k],
>+						&locals->DestinationLinesToRequestRowInImmediateFlip[k],
>+						&locals->final_flip_bw[k],
>+						&locals->ImmediateFlipSupportedForPipe[k]);
>+			}
>+			mode_lib->vba.total_dcn_read_bw_with_flip = 0.0;
>+			mode_lib->vba.total_dcn_read_bw_with_flip_no_urgent_burst = 0.0;
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				mode_lib->vba.total_dcn_read_bw_with_flip =
>+						mode_lib->vba.total_dcn_read_bw_with_flip + dml_max3(
>+							locals->prefetch_vmrow_bw[k],
>+							locals->final_flip_bw[k] + locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
>+							+ locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
>+							locals->final_flip_bw[k] + locals->RequiredPrefetchPixDataBWLuma[k] * locals->UrgentBurstFactorLumaPre[k]
>+							+ locals->RequiredPrefetchPixDataBWChroma[k] * locals->UrgentBurstFactorChromaPre[k]
>+							+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
>+				mode_lib->vba.total_dcn_read_bw_with_flip_no_urgent_burst =
>+				mode_lib->vba.total_dcn_read_bw_with_flip_no_urgent_burst +
>+					dml_max3(locals->prefetch_vmrow_bw[k],
>+						locals->final_flip_bw[k] + locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k] + locals->cursor_bw[k],
>+						locals->final_flip_bw[k] + locals->RequiredPrefetchPixDataBWLuma[k] + locals->RequiredPrefetchPixDataBWChroma[k] + locals->cursor_bw_pre[k]);
>+
>+			}
>+			mode_lib->vba.FractionOfUrgentBandwidthImmediateFlip = mode_lib->vba.total_dcn_read_bw_with_flip_no_urgent_burst / mode_lib->vba.ReturnBW;
>+
>+			mode_lib->vba.ImmediateFlipSupported = true;
>+			if (mode_lib->vba.total_dcn_read_bw_with_flip > mode_lib->vba.ReturnBW) {
>+				mode_lib->vba.ImmediateFlipSupported = false;
>+			}
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				if (locals->ImmediateFlipSupportedForPipe[k] == false) {
>+					mode_lib->vba.ImmediateFlipSupported = false;
>+				}
>+			}
>+		} else {
>+			mode_lib->vba.ImmediateFlipSupported = false;
>+		}
>+
>+		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+			if (mode_lib->vba.ErrorResult[k]) {
>+				mode_lib->vba.PrefetchModeSupported = false;
>+				dml_print(
>+						"DML: CalculatePrefetchSchedule ***failed***. Prefetch schedule violation. Results are NOT valid\n");
>+			}
>+		}
>+
>+		mode_lib->vba.VStartupLines = mode_lib->vba.VStartupLines + 1;
>+	} while (!((mode_lib->vba.PrefetchModeSupported
>+			&& ((!mode_lib->vba.ImmediateFlipSupport && !mode_lib->vba.HostVMEnable)
>+					|| mode_lib->vba.ImmediateFlipSupported))
>+			|| locals->MaximumMaxVStartupLines < mode_lib->vba.VStartupLines));
>+
>+	//Watermarks and NB P-State/DRAM Clock Change Support
>+	{
>+		enum clock_change_support DRAMClockChangeSupport; // dummy
>+		CalculateWatermarksAndDRAMSpeedChangeSupport(
>+				mode_lib,
>+				mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
>+				mode_lib->vba.NumberOfActivePlanes,
>+				mode_lib->vba.MaxLineBufferLines,
>+				mode_lib->vba.LineBufferSize,
>+				mode_lib->vba.DPPOutputBufferPixels,
>+				mode_lib->vba.DETBufferSizeInKByte,
>+				mode_lib->vba.WritebackInterfaceLumaBufferSize,
>+				mode_lib->vba.WritebackInterfaceChromaBufferSize,
>+				mode_lib->vba.DCFCLK,
>+				mode_lib->vba.UrgentOutOfOrderReturnPerChannel * mode_lib->vba.NumberOfChannels,
>+				mode_lib->vba.ReturnBW,
>+				mode_lib->vba.GPUVMEnable,
>+				locals->dpte_group_bytes,
>+				mode_lib->vba.MetaChunkSize,
>+				mode_lib->vba.UrgentLatency,
>+				mode_lib->vba.UrgentExtraLatency,
>+				mode_lib->vba.WritebackLatency,
>+				mode_lib->vba.WritebackChunkSize,
>+				mode_lib->vba.SOCCLK,
>+				mode_lib->vba.DRAMClockChangeLatency,
>+				mode_lib->vba.SRExitTime,
>+				mode_lib->vba.SREnterPlusExitTime,
>+				mode_lib->vba.DCFCLKDeepSleep,
>+				mode_lib->vba.DPPPerPlane,
>+				mode_lib->vba.DCCEnable,
>+				locals->DPPCLK,
>+				locals->SwathWidthSingleDPPY,
>+				mode_lib->vba.SwathHeightY,
>+				locals->ReadBandwidthPlaneLuma,
>+				mode_lib->vba.SwathHeightC,
>+				locals->ReadBandwidthPlaneChroma,
>+				mode_lib->vba.LBBitPerPixel,
>+				locals->SwathWidthY,
>+				mode_lib->vba.HRatio,
>+				mode_lib->vba.vtaps,
>+				mode_lib->vba.VTAPsChroma,
>+				mode_lib->vba.VRatio,
>+				mode_lib->vba.HTotal,
>+				mode_lib->vba.PixelClock,
>+				mode_lib->vba.BlendingAndTiming,
>+				locals->BytePerPixelDETY,
>+				locals->BytePerPixelDETC,
>+				mode_lib->vba.WritebackEnable,
>+				mode_lib->vba.WritebackPixelFormat,
>+				mode_lib->vba.WritebackDestinationWidth,
>+				mode_lib->vba.WritebackDestinationHeight,
>+				mode_lib->vba.WritebackSourceHeight,
>+				&DRAMClockChangeSupport,
>+				&mode_lib->vba.UrgentWatermark,
>+				&mode_lib->vba.WritebackUrgentWatermark,
>+				&mode_lib->vba.DRAMClockChangeWatermark,
>+				&mode_lib->vba.WritebackDRAMClockChangeWatermark,
>+				&mode_lib->vba.StutterExitWatermark,
>+				&mode_lib->vba.StutterEnterPlusExitWatermark,
>+				&mode_lib->vba.MinActiveDRAMClockChangeLatencySupported);
>+	}
>+
>+
>+	//Display Pipeline Delivery Time in Prefetch, Groups
>+	CalculatePixelDeliveryTimes(
>+		mode_lib->vba.NumberOfActivePlanes,
>+		mode_lib->vba.VRatio,
>+		locals->VRatioPrefetchY,
>+		locals->VRatioPrefetchC,
>+		locals->swath_width_luma_ub,
>+		locals->swath_width_chroma_ub,
>+		mode_lib->vba.DPPPerPlane,
>+		mode_lib->vba.HRatio,
>+		mode_lib->vba.PixelClock,
>+		locals->PSCL_THROUGHPUT_LUMA,
>+		locals->PSCL_THROUGHPUT_CHROMA,
>+		locals->DPPCLK,
>+		locals->BytePerPixelDETC,
>+		mode_lib->vba.SourceScan,
>+		locals->BlockWidth256BytesY,
>+		locals->BlockHeight256BytesY,
>+		locals->BlockWidth256BytesC,
>+		locals->BlockHeight256BytesC,
>+		locals->DisplayPipeLineDeliveryTimeLuma,
>+		locals->DisplayPipeLineDeliveryTimeChroma,
>+		locals->DisplayPipeLineDeliveryTimeLumaPrefetch,
>+		locals->DisplayPipeLineDeliveryTimeChromaPrefetch,
>+		locals->DisplayPipeRequestDeliveryTimeLuma,
>+		locals->DisplayPipeRequestDeliveryTimeChroma,
>+		locals->DisplayPipeRequestDeliveryTimeLumaPrefetch,
>+		locals->DisplayPipeRequestDeliveryTimeChromaPrefetch);
>+
>+	CalculateMetaAndPTETimes(
>+		mode_lib->vba.NumberOfActivePlanes,
>+		mode_lib->vba.GPUVMEnable,
>+		mode_lib->vba.MetaChunkSize,
>+		mode_lib->vba.MinMetaChunkSizeBytes,
>+		mode_lib->vba.GPUVMMaxPageTableLevels,
>+		mode_lib->vba.HTotal,
>+		mode_lib->vba.VRatio,
>+		locals->VRatioPrefetchY,
>+		locals->VRatioPrefetchC,
>+		locals->DestinationLinesToRequestRowInVBlank,
>+		locals->DestinationLinesToRequestRowInImmediateFlip,
>+		locals->DestinationLinesToRequestVMInVBlank,
>+		locals->DestinationLinesToRequestVMInImmediateFlip,
>+		mode_lib->vba.DCCEnable,
>+		mode_lib->vba.PixelClock,
>+		locals->BytePerPixelDETY,
>+		locals->BytePerPixelDETC,
>+		mode_lib->vba.SourceScan,
>+		locals->dpte_row_height,
>+		locals->dpte_row_height_chroma,
>+		locals->meta_row_width,
>+		locals->meta_row_height,
>+		locals->meta_req_width,
>+		locals->meta_req_height,
>+		locals->dpte_group_bytes,
>+		locals->PTERequestSizeY,
>+		locals->PTERequestSizeC,
>+		locals->PixelPTEReqWidthY,
>+		locals->PixelPTEReqHeightY,
>+		locals->PixelPTEReqWidthC,
>+		locals->PixelPTEReqHeightC,
>+		locals->dpte_row_width_luma_ub,
>+		locals->dpte_row_width_chroma_ub,
>+		locals->vm_group_bytes,
>+		locals->dpde0_bytes_per_frame_ub_l,
>+		locals->dpde0_bytes_per_frame_ub_c,
>+		locals->meta_pte_bytes_per_frame_ub_l,
>+		locals->meta_pte_bytes_per_frame_ub_c,
>+		locals->DST_Y_PER_PTE_ROW_NOM_L,
>+		locals->DST_Y_PER_PTE_ROW_NOM_C,
>+		locals->DST_Y_PER_META_ROW_NOM_L,
>+		locals->TimePerMetaChunkNominal,
>+		locals->TimePerMetaChunkVBlank,
>+		locals->TimePerMetaChunkFlip,
>+		locals->time_per_pte_group_nom_luma,
>+		locals->time_per_pte_group_vblank_luma,
>+		locals->time_per_pte_group_flip_luma,
>+		locals->time_per_pte_group_nom_chroma,
>+		locals->time_per_pte_group_vblank_chroma,
>+		locals->time_per_pte_group_flip_chroma,
>+		locals->TimePerVMGroupVBlank,
>+		locals->TimePerVMGroupFlip,
>+		locals->TimePerVMRequestVBlank,
>+		locals->TimePerVMRequestFlip);
>+
>+
>+	// Min TTUVBlank
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
>+			locals->AllowDRAMClockChangeDuringVBlank[k] = true;
>+			locals->AllowDRAMSelfRefreshDuringVBlank[k] = true;
>+			locals->MinTTUVBlank[k] = dml_max(
>+					mode_lib->vba.DRAMClockChangeWatermark,
>+					dml_max(
>+							mode_lib->vba.StutterEnterPlusExitWatermark,
>+							mode_lib->vba.UrgentWatermark));
>+		} else if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 1) {
>+			locals->AllowDRAMClockChangeDuringVBlank[k] = false;
>+			locals->AllowDRAMSelfRefreshDuringVBlank[k] = true;
>+			locals->MinTTUVBlank[k] = dml_max(
>+					mode_lib->vba.StutterEnterPlusExitWatermark,
>+					mode_lib->vba.UrgentWatermark);
>+		} else {
>+			locals->AllowDRAMClockChangeDuringVBlank[k] = false;
>+			locals->AllowDRAMSelfRefreshDuringVBlank[k] = false;
>+			locals->MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
>+		}
>+		if (!mode_lib->vba.DynamicMetadataEnable[k])
>+			locals->MinTTUVBlank[k] = mode_lib->vba.TCalc
>+					+ locals->MinTTUVBlank[k];
>+	}
>+
>+	// DCC Configuration
>+	mode_lib->vba.ActiveDPPs = 0;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		locals->MaximumDCCCompressionYSurface[k] = CalculateDCCConfiguration(
>+			mode_lib->vba.DCCEnable[k],
>+			false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
>+			mode_lib->vba.ViewportWidth[k],
>+			mode_lib->vba.ViewportHeight[k],
>+			mode_lib->vba.DETBufferSizeInKByte * 1024,
>+			locals->BlockHeight256BytesY[k],
>+			mode_lib->vba.SwathHeightY[k],
>+			mode_lib->vba.SurfaceTiling[k],
>+			locals->BytePerPixelDETY[k],
>+			mode_lib->vba.SourceScan[k],
>+			&locals->DCCYMaxUncompressedBlock[k],
>+			&locals->DCCYMaxCompressedBlock[k],
>+			&locals->DCCYIndependent64ByteBlock[k]);
>+	}
>+
>+	//XFC Parameters:
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.XFCEnabled[k] == true) {
>+			double TWait;
>+
>+			locals->XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
>+			locals->XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
>+			locals->XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
>+			TWait = CalculateTWait(
>+					mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
>+					mode_lib->vba.DRAMClockChangeLatency,
>+					mode_lib->vba.UrgentLatency,
>+					mode_lib->vba.SREnterPlusExitTime);
>+			mode_lib->vba.XFCRemoteSurfaceFlipDelay = CalculateRemoteSurfaceFlipDelay(
>+					mode_lib,
>+					mode_lib->vba.VRatio[k],
>+					locals->SwathWidthY[k],
>+					dml_ceil(locals->BytePerPixelDETY[k], 1),
>+					mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
>+					mode_lib->vba.XFCTSlvVupdateOffset,
>+					mode_lib->vba.XFCTSlvVupdateWidth,
>+					mode_lib->vba.XFCTSlvVreadyOffset,
>+					mode_lib->vba.XFCXBUFLatencyTolerance,
>+					mode_lib->vba.XFCFillBWOverhead,
>+					mode_lib->vba.XFCSlvChunkSize,
>+					mode_lib->vba.XFCBusTransportTime,
>+					mode_lib->vba.TCalc,
>+					TWait,
>+					&mode_lib->vba.SrcActiveDrainRate,
>+					&mode_lib->vba.TInitXFill,
>+					&mode_lib->vba.TslvChk);
>+					locals->XFCRemoteSurfaceFlipLatency[k] =
>+					dml_floor(
>+							mode_lib->vba.XFCRemoteSurfaceFlipDelay
>+									/ (mode_lib->vba.HTotal[k]
>+											/ mode_lib->vba.PixelClock[k]),
>+							1);
>+			locals->XFCTransferDelay[k] =
>+					dml_ceil(
>+							mode_lib->vba.XFCBusTransportTime
>+									/ (mode_lib->vba.HTotal[k]
>+											/ mode_lib->vba.PixelClock[k]),
>+							1);
>+			locals->XFCPrechargeDelay[k] =
>+					dml_ceil(
>+							(mode_lib->vba.XFCBusTransportTime
>+									+ mode_lib->vba.TInitXFill
>+									+ mode_lib->vba.TslvChk)
>+									/ (mode_lib->vba.HTotal[k]
>+											/ mode_lib->vba.PixelClock[k]),
>+							1);
>+			mode_lib->vba.InitFillLevel = mode_lib->vba.XFCXBUFLatencyTolerance
>+					* mode_lib->vba.SrcActiveDrainRate;
>+			mode_lib->vba.FinalFillMargin =
>+					(locals->DestinationLinesToRequestVMInVBlank[k]
>+							+ locals->DestinationLinesToRequestRowInVBlank[k])
>+							* mode_lib->vba.HTotal[k]
>+							/ mode_lib->vba.PixelClock[k]
>+							* mode_lib->vba.SrcActiveDrainRate
>+							+ mode_lib->vba.XFCFillConstant;
>+			mode_lib->vba.FinalFillLevel = mode_lib->vba.XFCRemoteSurfaceFlipDelay
>+					* mode_lib->vba.SrcActiveDrainRate
>+					+ mode_lib->vba.FinalFillMargin;
>+			mode_lib->vba.RemainingFillLevel = dml_max(
>+					0.0,
>+					mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel);
>+			mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel
>+					/ (mode_lib->vba.SrcActiveDrainRate
>+							* mode_lib->vba.XFCFillBWOverhead / 100);
>+			locals->XFCPrefetchMargin[k] =
>+					mode_lib->vba.XFCRemoteSurfaceFlipDelay
>+							+ mode_lib->vba.TFinalxFill
>+							+ (locals->DestinationLinesToRequestVMInVBlank[k]
>+									+ locals->DestinationLinesToRequestRowInVBlank[k])
>+									* mode_lib->vba.HTotal[k]
>+									/ mode_lib->vba.PixelClock[k];
>+		} else {
>+			locals->XFCSlaveVUpdateOffset[k] = 0;
>+			locals->XFCSlaveVupdateWidth[k] = 0;
>+			locals->XFCSlaveVReadyOffset[k] = 0;
>+			locals->XFCRemoteSurfaceFlipLatency[k] = 0;
>+			locals->XFCPrechargeDelay[k] = 0;
>+			locals->XFCTransferDelay[k] = 0;
>+			locals->XFCPrefetchMargin[k] = 0;
>+		}
>+	}
>+
>+	// Stutter Efficiency
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		CalculateDETBufferSize(
>+			mode_lib->vba.DETBufferSizeInKByte,
>+			mode_lib->vba.SwathHeightY[k],
>+			mode_lib->vba.SwathHeightC[k],
>+			&locals->DETBufferSizeY[k],
>+			&locals->DETBufferSizeC[k]);
>+
>+		locals->LinesInDETY[k] = locals->DETBufferSizeY[k]
>+				/ locals->BytePerPixelDETY[k] / locals->SwathWidthY[k];
>+		locals->LinesInDETYRoundedDownToSwath[k] = dml_floor(
>+				locals->LinesInDETY[k],
>+				mode_lib->vba.SwathHeightY[k]);
>+		locals->FullDETBufferingTimeY[k] =
>+				locals->LinesInDETYRoundedDownToSwath[k]
>+						* (mode_lib->vba.HTotal[k]
>+								/ mode_lib->vba.PixelClock[k])
>+						/ mode_lib->vba.VRatio[k];
>+	}
>+
>+	mode_lib->vba.StutterPeriod = 999999.0;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (locals->FullDETBufferingTimeY[k] < mode_lib->vba.StutterPeriod) {
>+			mode_lib->vba.StutterPeriod = locals->FullDETBufferingTimeY[k];
>+			mode_lib->vba.FrameTimeForMinFullDETBufferingTime =
>+				(double) mode_lib->vba.VTotal[k] * mode_lib->vba.HTotal[k]
>+				/ mode_lib->vba.PixelClock[k];
>+			locals->BytePerPixelYCriticalPlane = dml_ceil(locals->BytePerPixelDETY[k], 1);
>+			locals->SwathWidthYCriticalPlane = locals->SwathWidthY[k];
>+			locals->LinesToFinishSwathTransferStutterCriticalPlane =
>+				mode_lib->vba.SwathHeightY[k] - (locals->LinesInDETY[k] - locals->LinesInDETYRoundedDownToSwath[k]);
>+		}
>+	}
>+
>+	mode_lib->vba.AverageReadBandwidth = 0.0;
>+	mode_lib->vba.TotalRowReadBandwidth = 0.0;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		unsigned int DCCRateLimit;
>+
>+		if (mode_lib->vba.DCCEnable[k]) {
>+			if (locals->DCCYMaxCompressedBlock[k] == 256)
>+				DCCRateLimit = 4;
>+			else
>+				DCCRateLimit = 2;
>+
>+			mode_lib->vba.AverageReadBandwidth =
>+					mode_lib->vba.AverageReadBandwidth
>+							+ (locals->ReadBandwidthPlaneLuma[k] + locals->ReadBandwidthPlaneChroma[k]) /
>+								dml_min(mode_lib->vba.DCCRate[k], DCCRateLimit);
>+		} else {
>+			mode_lib->vba.AverageReadBandwidth =
>+					mode_lib->vba.AverageReadBandwidth
>+							+ locals->ReadBandwidthPlaneLuma[k]
>+							+ locals->ReadBandwidthPlaneChroma[k];
>+		}
>+		mode_lib->vba.TotalRowReadBandwidth = mode_lib->vba.TotalRowReadBandwidth +
>+		locals->meta_row_bw[k] + locals->dpte_row_bw[k];
>+	}
>+
>+	mode_lib->vba.AverageDCCCompressionRate = mode_lib->vba.TotalDataReadBandwidth / mode_lib->vba.AverageReadBandwidth;
>+
>+	mode_lib->vba.PartOfBurstThatFitsInROB =
>+			dml_min(
>+					mode_lib->vba.StutterPeriod
>+							* mode_lib->vba.TotalDataReadBandwidth,
>+					mode_lib->vba.ROBBufferSizeInKByte * 1024
>+							* mode_lib->vba.AverageDCCCompressionRate);
>+	mode_lib->vba.StutterBurstTime = mode_lib->vba.PartOfBurstThatFitsInROB
>+			/ mode_lib->vba.AverageDCCCompressionRate / mode_lib->vba.ReturnBW
>+			+ (mode_lib->vba.StutterPeriod * mode_lib->vba.TotalDataReadBandwidth
>+					- mode_lib->vba.PartOfBurstThatFitsInROB)
>+					/ (mode_lib->vba.DCFCLK * 64)
>+					+ mode_lib->vba.StutterPeriod * mode_lib->vba.TotalRowReadBandwidth / mode_lib->vba.ReturnBW;
>+	mode_lib->vba.StutterBurstTime = dml_max(
>+		mode_lib->vba.StutterBurstTime,
>+		(locals->LinesToFinishSwathTransferStutterCriticalPlane * locals->BytePerPixelYCriticalPlane *
>+		locals->SwathWidthYCriticalPlane / mode_lib->vba.ReturnBW)
>+	);
>+
>+	mode_lib->vba.TotalActiveWriteback = 0;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.WritebackEnable[k] == true) {
>+			mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + 1;
>+		}
>+	}
>+
>+	if (mode_lib->vba.TotalActiveWriteback == 0) {
>+		mode_lib->vba.StutterEfficiencyNotIncludingVBlank = (1
>+				- (mode_lib->vba.SRExitTime + mode_lib->vba.StutterBurstTime)
>+						/ mode_lib->vba.StutterPeriod) * 100;
>+	} else {
>+		mode_lib->vba.StutterEfficiencyNotIncludingVBlank = 0;
>+	}
>+
>+	mode_lib->vba.SmallestVBlank = 999999;
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.SynchronizedVBlank || mode_lib->vba.NumberOfActivePlanes == 1) {
>+			mode_lib->vba.VBlankTime = (double) (mode_lib->vba.VTotal[k]
>+					- mode_lib->vba.VActive[k]) * mode_lib->vba.HTotal[k]
>+					/ mode_lib->vba.PixelClock[k];
>+		} else {
>+			mode_lib->vba.VBlankTime = 0;
>+		}
>+		mode_lib->vba.SmallestVBlank = dml_min(
>+				mode_lib->vba.SmallestVBlank,
>+				mode_lib->vba.VBlankTime);
>+	}
>+
>+	mode_lib->vba.StutterEfficiency = (mode_lib->vba.StutterEfficiencyNotIncludingVBlank / 100
>+			* (mode_lib->vba.FrameTimeForMinFullDETBufferingTime
>+					- mode_lib->vba.SmallestVBlank)
>+			+ mode_lib->vba.SmallestVBlank)
>+			/ mode_lib->vba.FrameTimeForMinFullDETBufferingTime * 100;
>+}
>+
>+static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
>+{
>+	// Display Pipe Configuration
>+	double BytePerPixDETY;
>+	double BytePerPixDETC;
>+	double Read256BytesBlockHeightY;
>+	double Read256BytesBlockHeightC;
>+	double Read256BytesBlockWidthY;
>+	double Read256BytesBlockWidthC;
>+	double MaximumSwathHeightY;
>+	double MaximumSwathHeightC;
>+	double MinimumSwathHeightY;
>+	double MinimumSwathHeightC;
>+	double SwathWidth;
>+	double SwathWidthGranularityY;
>+	double SwathWidthGranularityC;
>+	double RoundedUpMaxSwathSizeBytesY;
>+	double RoundedUpMaxSwathSizeBytesC;
>+	unsigned int j, k;
>+
>+	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+		bool MainPlaneDoesODMCombine = false;
>+
>+		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
>+			BytePerPixDETY = 8;
>+			BytePerPixDETC = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
>+			BytePerPixDETY = 4;
>+			BytePerPixDETC = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
>+			BytePerPixDETY = 2;
>+			BytePerPixDETC = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8) {
>+			BytePerPixDETY = 1;
>+			BytePerPixDETC = 0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
>+			BytePerPixDETY = 1;
>+			BytePerPixDETC = 2;
>+		} else {
>+			BytePerPixDETY = 4.0 / 3.0;
>+			BytePerPixDETC = 8.0 / 3.0;
>+		}
>+
>+		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
>+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
>+				Read256BytesBlockHeightY = 1;
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
>+				Read256BytesBlockHeightY = 4;
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32
>+					|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16) {
>+				Read256BytesBlockHeightY = 8;
>+			} else {
>+				Read256BytesBlockHeightY = 16;
>+			}
>+			Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1)
>+					/ Read256BytesBlockHeightY;
>+			Read256BytesBlockHeightC = 0;
>+			Read256BytesBlockWidthC = 0;
>+		} else {
>+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
>+				Read256BytesBlockHeightY = 1;
>+				Read256BytesBlockHeightC = 1;
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
>+				Read256BytesBlockHeightY = 16;
>+				Read256BytesBlockHeightC = 8;
>+			} else {
>+				Read256BytesBlockHeightY = 8;
>+				Read256BytesBlockHeightC = 8;
>+			}
>+			Read256BytesBlockWidthY = 256 / dml_ceil(BytePerPixDETY, 1)
>+					/ Read256BytesBlockHeightY;
>+			Read256BytesBlockWidthC = 256 / dml_ceil(BytePerPixDETC, 2)
>+					/ Read256BytesBlockHeightC;
>+		}
>+
>+		if (mode_lib->vba.SourceScan[k] == dm_horz) {
>+			MaximumSwathHeightY = Read256BytesBlockHeightY;
>+			MaximumSwathHeightC = Read256BytesBlockHeightC;
>+		} else {
>+			MaximumSwathHeightY = Read256BytesBlockWidthY;
>+			MaximumSwathHeightC = Read256BytesBlockWidthC;
>+		}
>+
>+		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_8)) {
>+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>+					|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
>+							&& (mode_lib->vba.SurfaceTiling[k]
>+									== dm_sw_4kb_s
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_4kb_s_x
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_64kb_s
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_64kb_s_t
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_64kb_s_x
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_var_s
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_var_s_x)
>+							&& mode_lib->vba.SourceScan[k] == dm_horz)) {
>+				MinimumSwathHeightY = MaximumSwathHeightY;
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_8
>+					&& mode_lib->vba.SourceScan[k] != dm_horz) {
>+				MinimumSwathHeightY = MaximumSwathHeightY;
>+			} else {
>+				MinimumSwathHeightY = MaximumSwathHeightY / 2.0;
>+			}
>+			MinimumSwathHeightC = MaximumSwathHeightC;
>+		} else {
>+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
>+				MinimumSwathHeightY = MaximumSwathHeightY;
>+				MinimumSwathHeightC = MaximumSwathHeightC;
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
>+					&& mode_lib->vba.SourceScan[k] == dm_horz) {
>+				MinimumSwathHeightY = MaximumSwathHeightY / 2.0;
>+				MinimumSwathHeightC = MaximumSwathHeightC;
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
>+					&& mode_lib->vba.SourceScan[k] == dm_horz) {
>+				MinimumSwathHeightC = MaximumSwathHeightC / 2.0;
>+				MinimumSwathHeightY = MaximumSwathHeightY;
>+			} else {
>+				MinimumSwathHeightY = MaximumSwathHeightY;
>+				MinimumSwathHeightC = MaximumSwathHeightC;
>+			}
>+		}
>+
>+		if (mode_lib->vba.SourceScan[k] == dm_horz) {
>+			SwathWidth = mode_lib->vba.ViewportWidth[k];
>+		} else {
>+			SwathWidth = mode_lib->vba.ViewportHeight[k];
>+		}
>+
>+		if (mode_lib->vba.ODMCombineEnabled[k] == true) {
>+			MainPlaneDoesODMCombine = true;
>+		}
>+		for (j = 0; j < mode_lib->vba.NumberOfActivePlanes; ++j) {
>+			if (mode_lib->vba.BlendingAndTiming[k] == j
>+					&& mode_lib->vba.ODMCombineEnabled[j] == true) {
>+				MainPlaneDoesODMCombine = true;
>+			}
>+		}
>+
>+		if (MainPlaneDoesODMCombine == true) {
>+			SwathWidth = dml_min(
>+					SwathWidth,
>+					mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]);
>+		} else {
>+			SwathWidth = SwathWidth / mode_lib->vba.DPPPerPlane[k];
>+		}
>+
>+		SwathWidthGranularityY = 256 / dml_ceil(BytePerPixDETY, 1) / MaximumSwathHeightY;
>+		RoundedUpMaxSwathSizeBytesY = (dml_ceil(
>+				(double) (SwathWidth - 1),
>+				SwathWidthGranularityY) + SwathWidthGranularityY) * BytePerPixDETY
>+				* MaximumSwathHeightY;
>+		if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
>+			RoundedUpMaxSwathSizeBytesY = dml_ceil(RoundedUpMaxSwathSizeBytesY, 256)
>+					+ 256;
>+		}
>+		if (MaximumSwathHeightC > 0) {
>+			SwathWidthGranularityC = 256.0 / dml_ceil(BytePerPixDETC, 2)
>+					/ MaximumSwathHeightC;
>+			RoundedUpMaxSwathSizeBytesC = (dml_ceil(
>+					(double) (SwathWidth / 2.0 - 1),
>+					SwathWidthGranularityC) + SwathWidthGranularityC)
>+					* BytePerPixDETC * MaximumSwathHeightC;
>+			if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
>+				RoundedUpMaxSwathSizeBytesC = dml_ceil(
>+						RoundedUpMaxSwathSizeBytesC,
>+						256) + 256;
>+			}
>+		} else
>+			RoundedUpMaxSwathSizeBytesC = 0.0;
>+
>+		if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC
>+				<= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) {
>+			mode_lib->vba.SwathHeightY[k] = MaximumSwathHeightY;
>+			mode_lib->vba.SwathHeightC[k] = MaximumSwathHeightC;
>+		} else {
>+			mode_lib->vba.SwathHeightY[k] = MinimumSwathHeightY;
>+			mode_lib->vba.SwathHeightC[k] = MinimumSwathHeightC;
>+		}
>+
>+		CalculateDETBufferSize(
>+				mode_lib->vba.DETBufferSizeInKByte,
>+				mode_lib->vba.SwathHeightY[k],
>+				mode_lib->vba.SwathHeightC[k],
>+				&mode_lib->vba.DETBufferSizeY[k],
>+				&mode_lib->vba.DETBufferSizeC[k]);
>+	}
>+}
>+
>+static double CalculateTWait(
>+		unsigned int PrefetchMode,
>+		double DRAMClockChangeLatency,
>+		double UrgentLatency,
>+		double SREnterPlusExitTime)
>+{
>+	if (PrefetchMode == 0) {
>+		return dml_max(
>+				DRAMClockChangeLatency + UrgentLatency,
>+				dml_max(SREnterPlusExitTime, UrgentLatency));
>+	} else if (PrefetchMode == 1) {
>+		return dml_max(SREnterPlusExitTime, UrgentLatency);
>+	} else {
>+		return UrgentLatency;
>+	}
>+}
>+
>+static double CalculateRemoteSurfaceFlipDelay(
>+		struct display_mode_lib *mode_lib,
>+		double VRatio,
>+		double SwathWidth,
>+		double Bpp,
>+		double LineTime,
>+		double XFCTSlvVupdateOffset,
>+		double XFCTSlvVupdateWidth,
>+		double XFCTSlvVreadyOffset,
>+		double XFCXBUFLatencyTolerance,
>+		double XFCFillBWOverhead,
>+		double XFCSlvChunkSize,
>+		double XFCBusTransportTime,
>+		double TCalc,
>+		double TWait,
>+		double *SrcActiveDrainRate,
>+		double *TInitXFill,
>+		double *TslvChk)
>+{
>+	double TSlvSetup, AvgfillRate, result;
>+
>+	*SrcActiveDrainRate = VRatio * SwathWidth * Bpp / LineTime;
>+	TSlvSetup = XFCTSlvVupdateOffset + XFCTSlvVupdateWidth + XFCTSlvVreadyOffset;
>+	*TInitXFill = XFCXBUFLatencyTolerance / (1 + XFCFillBWOverhead / 100);
>+	AvgfillRate = *SrcActiveDrainRate * (1 + XFCFillBWOverhead / 100);
>+	*TslvChk = XFCSlvChunkSize / AvgfillRate;
>+	dml_print(
>+			"DML::CalculateRemoteSurfaceFlipDelay: SrcActiveDrainRate: %f\n",
>+			*SrcActiveDrainRate);
>+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TSlvSetup: %f\n", TSlvSetup);
>+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TInitXFill: %f\n", *TInitXFill);
>+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: AvgfillRate: %f\n", AvgfillRate);
>+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: TslvChk: %f\n", *TslvChk);
>+	result = 2 * XFCBusTransportTime + TSlvSetup + TCalc + TWait + *TslvChk + *TInitXFill; // TODO: This doesn't seem to match programming guide
>+	dml_print("DML::CalculateRemoteSurfaceFlipDelay: RemoteSurfaceFlipDelay: %f\n", result);
>+	return result;
>+}
>+
>+static double CalculateWriteBackDelay(
>+		enum source_format_class WritebackPixelFormat,
>+		double WritebackHRatio,
>+		double WritebackVRatio,
>+		unsigned int WritebackLumaHTaps,
>+		unsigned int WritebackLumaVTaps,
>+		unsigned int WritebackChromaHTaps,
>+		unsigned int WritebackChromaVTaps,
>+		unsigned int WritebackDestinationWidth)
>+{
>+	double CalculateWriteBackDelay =
>+			dml_max(
>+					dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio,
>+					WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1)
>+							* dml_ceil(
>+									WritebackDestinationWidth
>+											/ 4.0,
>+									1)
>+							+ dml_ceil(1.0 / WritebackVRatio, 1)
>+									* (dml_ceil(
>+											WritebackLumaVTaps
>+													/ 4.0,
>+											1) + 4));
>+
>+	if (WritebackPixelFormat != dm_444_32) {
>+		CalculateWriteBackDelay =
>+				dml_max(
>+						CalculateWriteBackDelay,
>+						dml_max(
>+								dml_ceil(
>+										WritebackChromaHTaps
>+												/ 2.0,
>+										1)
>+										/ (2
>+												* WritebackHRatio),
>+								WritebackChromaVTaps
>+										* dml_ceil(
>+												1
>+														/ (2
>+																* WritebackVRatio),
>+												1)
>+										* dml_ceil(
>+												WritebackDestinationWidth
>+														/ 2.0
>+														/ 2.0,
>+												1)
>+										+ dml_ceil(
>+												1
>+														/ (2
>+																* WritebackVRatio),
>+												1)
>+												* (dml_ceil(
>+														WritebackChromaVTaps
>+																/ 4.0,
>+														1)
>+														+ 4)));
>+	}
>+	return CalculateWriteBackDelay;
>+}
>+
>+static void CalculateActiveRowBandwidth(
>+		bool GPUVMEnable,
>+		enum source_format_class SourcePixelFormat,
>+		double VRatio,
>+		bool DCCEnable,
>+		double LineTime,
>+		unsigned int MetaRowByteLuma,
>+		unsigned int MetaRowByteChroma,
>+		unsigned int meta_row_height_luma,
>+		unsigned int meta_row_height_chroma,
>+		unsigned int PixelPTEBytesPerRowLuma,
>+		unsigned int PixelPTEBytesPerRowChroma,
>+		unsigned int dpte_row_height_luma,
>+		unsigned int dpte_row_height_chroma,
>+		double *meta_row_bw,
>+		double *dpte_row_bw)
>+{
>+	if (DCCEnable != true) {
>+		*meta_row_bw = 0;
>+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
>+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime)
>+				+ VRatio / 2 * MetaRowByteChroma
>+						/ (meta_row_height_chroma * LineTime);
>+	} else {
>+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime);
>+	}
>+
>+	if (GPUVMEnable != true) {
>+		*dpte_row_bw = 0;
>+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
>+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime)
>+				+ VRatio / 2 * PixelPTEBytesPerRowChroma
>+						/ (dpte_row_height_chroma * LineTime);
>+	} else {
>+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime);
>+	}
>+}
>+
>+static void CalculateFlipSchedule(
>+		struct display_mode_lib *mode_lib,
>+		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
>+		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
>+		double UrgentExtraLatency,
>+		double UrgentLatency,
>+		unsigned int GPUVMMaxPageTableLevels,
>+		bool HostVMEnable,
>+		unsigned int HostVMMaxPageTableLevels,
>+		unsigned int HostVMCachedPageTableLevels,
>+		bool GPUVMEnable,
>+		double PDEAndMetaPTEBytesPerFrame,
>+		double MetaRowBytes,
>+		double DPTEBytesPerRow,
>+		double BandwidthAvailableForImmediateFlip,
>+		unsigned int TotImmediateFlipBytes,
>+		enum source_format_class SourcePixelFormat,
>+		double LineTime,
>+		double VRatio,
>+		double Tno_bw,
>+		bool DCCEnable,
>+		unsigned int dpte_row_height,
>+		unsigned int meta_row_height,
>+		unsigned int dpte_row_height_chroma,
>+		unsigned int meta_row_height_chroma,
>+		double *DestinationLinesToRequestVMInImmediateFlip,
>+		double *DestinationLinesToRequestRowInImmediateFlip,
>+		double *final_flip_bw,
>+		bool *ImmediateFlipSupportedForPipe)
>+{
>+	double min_row_time = 0.0;
>+	unsigned int HostVMDynamicLevels;
>+	double TimeForFetchingMetaPTEImmediateFlip;
>+	double TimeForFetchingRowInVBlankImmediateFlip;
>+	double ImmediateFlipBW;
>+	double HostVMInefficiencyFactor;
>+
>+	if (GPUVMEnable == true && HostVMEnable == true) {
>+		HostVMInefficiencyFactor =
>+				PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData
>+						/ PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly;
>+		HostVMDynamicLevels = HostVMMaxPageTableLevels - HostVMCachedPageTableLevels;
>+	} else {
>+		HostVMInefficiencyFactor = 1;
>+		HostVMDynamicLevels = 0;
>+	}
>+
>+	ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow)
>+			* BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes;
>+
>+	if (GPUVMEnable == true) {
>+		TimeForFetchingMetaPTEImmediateFlip = dml_max3(
>+			Tno_bw + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
>+			UrgentExtraLatency + UrgentLatency * (GPUVMMaxPageTableLevels * (HostVMDynamicLevels + 1) - 1),
>+			LineTime / 4.0);
>+	} else {
>+		TimeForFetchingMetaPTEImmediateFlip = 0;
>+	}
>+
>+	*DestinationLinesToRequestVMInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0;
>+	if ((GPUVMEnable == true || DCCEnable == true)) {
>+		TimeForFetchingRowInVBlankImmediateFlip = dml_max3((MetaRowBytes + DPTEBytesPerRow) * HostVMInefficiencyFactor / ImmediateFlipBW, UrgentLatency * (HostVMDynamicLevels + 1), LineTime / 4);
>+	} else {
>+		TimeForFetchingRowInVBlankImmediateFlip = 0;
>+	}
>+
>+	*DestinationLinesToRequestRowInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0;
>+	*final_flip_bw = dml_max(PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInImmediateFlip * LineTime), (MetaRowBytes + DPTEBytesPerRow) * HostVMInefficiencyFactor / (*DestinationLinesToRequestRowInImmediateFlip * LineTime));
>+	if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10) {
>+		if (GPUVMEnable == true && DCCEnable != true) {
>+			min_row_time = dml_min(
>+					dpte_row_height * LineTime / VRatio,
>+					dpte_row_height_chroma * LineTime / (VRatio / 2));
>+		} else if (GPUVMEnable != true && DCCEnable == true) {
>+			min_row_time = dml_min(
>+					meta_row_height * LineTime / VRatio,
>+					meta_row_height_chroma * LineTime / (VRatio / 2));
>+		} else {
>+			min_row_time = dml_min4(
>+					dpte_row_height * LineTime / VRatio,
>+					meta_row_height * LineTime / VRatio,
>+					dpte_row_height_chroma * LineTime / (VRatio / 2),
>+					meta_row_height_chroma * LineTime / (VRatio / 2));
>+		}
>+	} else {
>+		if (GPUVMEnable == true && DCCEnable != true) {
>+			min_row_time = dpte_row_height * LineTime / VRatio;
>+		} else if (GPUVMEnable != true && DCCEnable == true) {
>+			min_row_time = meta_row_height * LineTime / VRatio;
>+		} else {
>+			min_row_time = dml_min(
>+					dpte_row_height * LineTime / VRatio,
>+					meta_row_height * LineTime / VRatio);
>+		}
>+	}
>+
>+	if (*DestinationLinesToRequestVMInImmediateFlip >= 32
>+			|| *DestinationLinesToRequestRowInImmediateFlip >= 16
>+			|| TimeForFetchingMetaPTEImmediateFlip + 2 * TimeForFetchingRowInVBlankImmediateFlip > min_row_time) {
>+		*ImmediateFlipSupportedForPipe = false;
>+	} else {
>+		*ImmediateFlipSupportedForPipe = true;
>+	}
>+}
>+
>+static unsigned int TruncToValidBPP(
>+		double DecimalBPP,
>+		double DesiredBPP,
>+		bool DSCEnabled,
>+		enum output_encoder_class Output,
>+		enum output_format_class Format,
>+		unsigned int DSCInputBitPerComponent)
>+{
>+	if (Output == dm_hdmi) {
>+		if (Format == dm_420) {
>+			if (DecimalBPP >= 18 && (DesiredBPP == 0 || DesiredBPP == 18))
>+				return 18;
>+			else if (DecimalBPP >= 15 && (DesiredBPP == 0 || DesiredBPP == 15))
>+				return 15;
>+			else if (DecimalBPP >= 12 && (DesiredBPP == 0 || DesiredBPP == 12))
>+				return 12;
>+			else
>+				return BPP_INVALID;
>+		} else if (Format == dm_444) {
>+			if (DecimalBPP >= 36 && (DesiredBPP == 0 || DesiredBPP == 36))
>+				return 36;
>+			else if (DecimalBPP >= 30 && (DesiredBPP == 0 || DesiredBPP == 30))
>+				return 30;
>+			else if (DecimalBPP >= 24 && (DesiredBPP == 0 || DesiredBPP == 24))
>+				return 24;
>+			else if (DecimalBPP >= 18 && (DesiredBPP == 0 || DesiredBPP == 18))
>+				return 18;
>+			else
>+				return BPP_INVALID;
>+		} else {
>+			if (DecimalBPP / 1.5 >= 24 && (DesiredBPP == 0 || DesiredBPP == 24))
>+				return 24;
>+			else if (DecimalBPP / 1.5 >= 20 && (DesiredBPP == 0 || DesiredBPP == 20))
>+				return 20;
>+			else if (DecimalBPP / 1.5 >= 16 && (DesiredBPP == 0 || DesiredBPP == 16))
>+				return 16;
>+			else
>+				return BPP_INVALID;
>+		}
>+	} else {
>+		if (DSCEnabled) {
>+			if (Format == dm_420) {
>+				if (DesiredBPP == 0) {
>+					if (DecimalBPP < 6)
>+						return BPP_INVALID;
>+					else if (DecimalBPP >= 1.5 * DSCInputBitPerComponent - 1.0 / 16.0)
>+						return 1.5 * DSCInputBitPerComponent - 1.0 / 16.0;
>+					else
>+						return dml_floor(16 * DecimalBPP, 1) / 16.0;
>+				} else {
>+					if (DecimalBPP < 6
>+							|| DesiredBPP < 6
>+							|| DesiredBPP > 1.5 * DSCInputBitPerComponent - 1.0 / 16.0
>+							|| DecimalBPP < DesiredBPP) {
>+						return BPP_INVALID;
>+					} else {
>+						return DesiredBPP;
>+					}
>+				}
>+			} else if (Format == dm_n422) {
>+				if (DesiredBPP == 0) {
>+					if (DecimalBPP < 7)
>+						return BPP_INVALID;
>+					else if (DecimalBPP >= 2 * DSCInputBitPerComponent - 1.0 / 16.0)
>+						return 2 * DSCInputBitPerComponent - 1.0 / 16.0;
>+					else
>+						return dml_floor(16 * DecimalBPP, 1) / 16.0;
>+				} else {
>+					if (DecimalBPP < 7
>+							|| DesiredBPP < 7
>+							|| DesiredBPP > 2 * DSCInputBitPerComponent - 1.0 / 16.0
>+							|| DecimalBPP < DesiredBPP) {
>+						return BPP_INVALID;
>+					} else {
>+						return DesiredBPP;
>+					}
>+				}
>+			} else {
>+				if (DesiredBPP == 0) {
>+					if (DecimalBPP < 8)
>+						return BPP_INVALID;
>+					else if (DecimalBPP >= 3 * DSCInputBitPerComponent - 1.0 / 16.0)
>+						return 3 * DSCInputBitPerComponent - 1.0 / 16.0;
>+					else
>+						return dml_floor(16 * DecimalBPP, 1) / 16.0;
>+				} else {
>+					if (DecimalBPP < 8
>+							|| DesiredBPP < 8
>+							|| DesiredBPP > 3 * DSCInputBitPerComponent - 1.0 / 16.0
>+							|| DecimalBPP < DesiredBPP) {
>+						return BPP_INVALID;
>+					} else {
>+						return DesiredBPP;
>+					}
>+				}
>+			}
>+		} else if (Format == dm_420) {
>+			if (DecimalBPP >= 18 && (DesiredBPP == 0 || DesiredBPP == 18))
>+				return 18;
>+			else if (DecimalBPP >= 15 && (DesiredBPP == 0 || DesiredBPP == 15))
>+				return 15;
>+			else if (DecimalBPP >= 12 && (DesiredBPP == 0 || DesiredBPP == 12))
>+				return 12;
>+			else
>+				return BPP_INVALID;
>+		} else if (Format == dm_s422 || Format == dm_n422) {
>+			if (DecimalBPP >= 24 && (DesiredBPP == 0 || DesiredBPP == 24))
>+				return 24;
>+			else if (DecimalBPP >= 20 && (DesiredBPP == 0 || DesiredBPP == 20))
>+				return 20;
>+			else if (DecimalBPP >= 16 && (DesiredBPP == 0 || DesiredBPP == 16))
>+				return 16;
>+			else
>+				return BPP_INVALID;
>+		} else {
>+			if (DecimalBPP >= 36 && (DesiredBPP == 0 || DesiredBPP == 36))
>+				return 36;
>+			else if (DecimalBPP >= 30 && (DesiredBPP == 0 || DesiredBPP == 30))
>+				return 30;
>+			else if (DecimalBPP >= 24 && (DesiredBPP == 0 || DesiredBPP == 24))
>+				return 24;
>+			else
>+				return BPP_INVALID;
>+		}
>+	}
>+}
>+
>+void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
>+{
>+	struct vba_vars_st *locals = &mode_lib->vba;
>+
>+	int i;
>+	unsigned int j, k, m;
>+
>+	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
>+
>+	/*Scale Ratio, taps Support Check*/
>+
>+	mode_lib->vba.ScaleRatioAndTapsSupport = true;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.ScalerEnabled[k] == false
>+				&& ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)
>+						|| mode_lib->vba.HRatio[k] != 1.0
>+						|| mode_lib->vba.htaps[k] != 1.0
>+						|| mode_lib->vba.VRatio[k] != 1.0
>+						|| mode_lib->vba.vtaps[k] != 1.0)) {
>+			mode_lib->vba.ScaleRatioAndTapsSupport = false;
>+		} else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0
>+				|| mode_lib->vba.htaps[k] < 1.0 || mode_lib->vba.htaps[k] > 8.0
>+				|| (mode_lib->vba.htaps[k] > 1.0
>+						&& (mode_lib->vba.htaps[k] % 2) == 1)
>+				|| mode_lib->vba.HRatio[k] > mode_lib->vba.MaxHSCLRatio
>+				|| mode_lib->vba.VRatio[k] > mode_lib->vba.MaxVSCLRatio
>+				|| mode_lib->vba.HRatio[k] > mode_lib->vba.htaps[k]
>+				|| mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k]
>+				|| (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8
>+						&& (mode_lib->vba.HRatio[k] / 2.0
>+								> mode_lib->vba.HTAPsChroma[k]
>+								|| mode_lib->vba.VRatio[k] / 2.0
>+										> mode_lib->vba.VTAPsChroma[k]))) {
>+			mode_lib->vba.ScaleRatioAndTapsSupport = false;
>+		}
>+	}
>+	/*Source Format, Pixel Format and Scan Support Check*/
>+
>+	mode_lib->vba.SourceFormatPixelAndScanSupport = true;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if ((mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>+				&& mode_lib->vba.SourceScan[k] != dm_horz)
>+				|| ((mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d
>+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_4kb_d_x
>+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d
>+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_t
>+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_d_x
>+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d
>+						|| mode_lib->vba.SurfaceTiling[k] == dm_sw_var_d_x)
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_64)
>+				|| (mode_lib->vba.SurfaceTiling[k] == dm_sw_64kb_r_x
>+						&& (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8
>+								|| mode_lib->vba.SourcePixelFormat[k]
>+										== dm_420_8
>+								|| mode_lib->vba.SourcePixelFormat[k]
>+										== dm_420_10))
>+				|| (((mode_lib->vba.SurfaceTiling[k] == dm_sw_gfx7_2d_thin_gl
>+						|| mode_lib->vba.SurfaceTiling[k]
>+								== dm_sw_gfx7_2d_thin_lvp)
>+						&& !((mode_lib->vba.SourcePixelFormat[k]
>+								== dm_444_64
>+								|| mode_lib->vba.SourcePixelFormat[k]
>+										== dm_444_32)
>+								&& mode_lib->vba.SourceScan[k]
>+										== dm_horz
>+								&& mode_lib->vba.SupportGFX7CompatibleTilingIn32bppAnd64bpp
>+										== true
>+								&& mode_lib->vba.DCCEnable[k]
>+										== false))
>+						|| (mode_lib->vba.DCCEnable[k] == true
>+								&& (mode_lib->vba.SurfaceTiling[k]
>+										== dm_sw_linear
>+										|| mode_lib->vba.SourcePixelFormat[k]
>+												== dm_420_8
>+										|| mode_lib->vba.SourcePixelFormat[k]
>+												== dm_420_10)))) {
>+			mode_lib->vba.SourceFormatPixelAndScanSupport = false;
>+		}
>+	}
>+	/*Bandwidth Support Check*/
>+
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.SourcePixelFormat[k] == dm_444_64) {
>+			locals->BytePerPixelInDETY[k] = 8.0;
>+			locals->BytePerPixelInDETC[k] = 0.0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_32) {
>+			locals->BytePerPixelInDETY[k] = 4.0;
>+			locals->BytePerPixelInDETC[k] = 0.0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_444_16
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16) {
>+			locals->BytePerPixelInDETY[k] = 2.0;
>+			locals->BytePerPixelInDETC[k] = 0.0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_mono_8) {
>+			locals->BytePerPixelInDETY[k] = 1.0;
>+			locals->BytePerPixelInDETC[k] = 0.0;
>+		} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8) {
>+			locals->BytePerPixelInDETY[k] = 1.0;
>+			locals->BytePerPixelInDETC[k] = 2.0;
>+		} else {
>+			locals->BytePerPixelInDETY[k] = 4.0 / 3;
>+			locals->BytePerPixelInDETC[k] = 8.0 / 3;
>+		}
>+		if (mode_lib->vba.SourceScan[k] == dm_horz) {
>+			locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
>+		} else {
>+			locals->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
>+		}
>+	}
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		locals->ReadBandwidthLuma[k] = locals->SwathWidthYSingleDPP[k] * dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
>+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
>+		locals->ReadBandwidthChroma[k] = locals->SwathWidthYSingleDPP[k] / 2 * dml_ceil(locals->BytePerPixelInDETC[k], 2.0)
>+				/ (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k] / 2.0;
>+		locals->ReadBandwidth[k] = locals->ReadBandwidthLuma[k] + locals->ReadBandwidthChroma[k];
>+	}
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.WritebackEnable[k] == true
>+				&& mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
>+			locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
>+					* mode_lib->vba.WritebackDestinationHeight[k]
>+					/ (mode_lib->vba.WritebackSourceHeight[k]
>+							* mode_lib->vba.HTotal[k]
>+							/ mode_lib->vba.PixelClock[k]) * 4.0;
>+		} else if (mode_lib->vba.WritebackEnable[k] == true
>+				&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
>+			locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
>+					* mode_lib->vba.WritebackDestinationHeight[k]
>+					/ (mode_lib->vba.WritebackSourceHeight[k]
>+							* mode_lib->vba.HTotal[k]
>+							/ mode_lib->vba.PixelClock[k]) * 3.0;
>+		} else if (mode_lib->vba.WritebackEnable[k] == true) {
>+			locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k]
>+					* mode_lib->vba.WritebackDestinationHeight[k]
>+					/ (mode_lib->vba.WritebackSourceHeight[k]
>+							* mode_lib->vba.HTotal[k]
>+							/ mode_lib->vba.PixelClock[k]) * 1.5;
>+		} else {
>+			locals->WriteBandwidth[k] = 0.0;
>+		}
>+	}
>+	mode_lib->vba.DCCEnabledInAnyPlane = false;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.DCCEnable[k] == true) {
>+			mode_lib->vba.DCCEnabledInAnyPlane = true;
>+		}
>+	}
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		locals->IdealSDPPortBandwidthPerState[i] = dml_min3(
>+				mode_lib->vba.ReturnBusWidth * mode_lib->vba.DCFCLKPerState[i],
>+				mode_lib->vba.DRAMSpeedPerState[i] * mode_lib->vba.NumberOfChannels
>+						* mode_lib->vba.DRAMChannelWidth,
>+				mode_lib->vba.FabricClockPerState[i]
>+						* mode_lib->vba.FabricDatapathToDCNDataReturn);
>+		if (mode_lib->vba.HostVMEnable == false) {
>+			locals->ReturnBWPerState[i] = locals->IdealSDPPortBandwidthPerState[i]
>+					* mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly / 100.0;
>+		} else {
>+			locals->ReturnBWPerState[i] = locals->IdealSDPPortBandwidthPerState[i]
>+					* mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0;
>+		}
>+	}
>+	/*Writeback Latency support check*/
>+
>+	mode_lib->vba.WritebackLatencySupport = true;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.WritebackEnable[k] == true) {
>+			if (mode_lib->vba.WritebackPixelFormat[k] == dm_444_32) {
>+				if (locals->WriteBandwidth[k]
>+						> (mode_lib->vba.WritebackInterfaceLumaBufferSize
>+								+ mode_lib->vba.WritebackInterfaceChromaBufferSize)
>+								/ mode_lib->vba.WritebackLatency) {
>+					mode_lib->vba.WritebackLatencySupport = false;
>+				}
>+			} else {
>+				if (locals->WriteBandwidth[k]
>+						> 1.5
>+								* dml_min(
>+										mode_lib->vba.WritebackInterfaceLumaBufferSize,
>+										2.0
>+												* mode_lib->vba.WritebackInterfaceChromaBufferSize)
>+								/ mode_lib->vba.WritebackLatency) {
>+					mode_lib->vba.WritebackLatencySupport = false;
>+				}
>+			}
>+		}
>+	}
>+	/*Re-ordering Buffer Support Check*/
>+
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i] =
>+				(mode_lib->vba.RoundTripPingLatencyCycles + 32.0) / mode_lib->vba.DCFCLKPerState[i]
>+				+ dml_max3(mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
>+						mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
>+						mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly)
>+					* mode_lib->vba.NumberOfChannels / locals->ReturnBWPerState[i];
>+		if ((mode_lib->vba.ROBBufferSizeInKByte - mode_lib->vba.PixelChunkSizeInKByte) * 1024.0 / locals->ReturnBWPerState[i]
>+				> locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i]) {
>+			locals->ROBSupport[i] = true;
>+		} else {
>+			locals->ROBSupport[i] = false;
>+		}
>+	}
>+	/*Writeback Mode Support Check*/
>+
>+	mode_lib->vba.TotalNumberOfActiveWriteback = 0;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.WritebackEnable[k] == true) {
>+			if (mode_lib->vba.ActiveWritebacksPerPlane[k] == 0)
>+				mode_lib->vba.ActiveWritebacksPerPlane[k] = 1;
>+			mode_lib->vba.TotalNumberOfActiveWriteback =
>+					mode_lib->vba.TotalNumberOfActiveWriteback
>+							+ mode_lib->vba.ActiveWritebacksPerPlane[k];
>+		}
>+	}
>+	mode_lib->vba.WritebackModeSupport = true;
>+	if (mode_lib->vba.TotalNumberOfActiveWriteback > mode_lib->vba.MaxNumWriteback) {
>+		mode_lib->vba.WritebackModeSupport = false;
>+	}
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.WritebackEnable[k] == true
>+				&& mode_lib->vba.Writeback10bpc420Supported != true
>+				&& mode_lib->vba.WritebackPixelFormat[k] == dm_420_10) {
>+			mode_lib->vba.WritebackModeSupport = false;
>+		}
>+	}
>+	/*Writeback Scale Ratio and Taps Support Check*/
>+
>+	mode_lib->vba.WritebackScaleRatioAndTapsSupport = true;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.WritebackEnable[k] == true) {
>+			if (mode_lib->vba.WritebackLumaAndChromaScalingSupported == false
>+					&& (mode_lib->vba.WritebackHRatio[k] != 1.0
>+							|| mode_lib->vba.WritebackVRatio[k] != 1.0)) {
>+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
>+			}
>+			if (mode_lib->vba.WritebackHRatio[k] > mode_lib->vba.WritebackMaxHSCLRatio
>+					|| mode_lib->vba.WritebackVRatio[k]
>+							> mode_lib->vba.WritebackMaxVSCLRatio
>+					|| mode_lib->vba.WritebackHRatio[k]
>+							< mode_lib->vba.WritebackMinHSCLRatio
>+					|| mode_lib->vba.WritebackVRatio[k]
>+							< mode_lib->vba.WritebackMinVSCLRatio
>+					|| mode_lib->vba.WritebackLumaHTaps[k]
>+							> mode_lib->vba.WritebackMaxHSCLTaps
>+					|| mode_lib->vba.WritebackLumaVTaps[k]
>+							> mode_lib->vba.WritebackMaxVSCLTaps
>+					|| mode_lib->vba.WritebackHRatio[k]
>+							> mode_lib->vba.WritebackLumaHTaps[k]
>+					|| mode_lib->vba.WritebackVRatio[k]
>+							> mode_lib->vba.WritebackLumaVTaps[k]
>+					|| (mode_lib->vba.WritebackLumaHTaps[k] > 2.0
>+							&& ((mode_lib->vba.WritebackLumaHTaps[k] % 2)
>+									== 1))
>+					|| (mode_lib->vba.WritebackPixelFormat[k] != dm_444_32
>+							&& (mode_lib->vba.WritebackChromaHTaps[k]
>+									> mode_lib->vba.WritebackMaxHSCLTaps
>+									|| mode_lib->vba.WritebackChromaVTaps[k]
>+											> mode_lib->vba.WritebackMaxVSCLTaps
>+									|| 2.0
>+											* mode_lib->vba.WritebackHRatio[k]
>+											> mode_lib->vba.WritebackChromaHTaps[k]
>+									|| 2.0
>+											* mode_lib->vba.WritebackVRatio[k]
>+											> mode_lib->vba.WritebackChromaVTaps[k]
>+									|| (mode_lib->vba.WritebackChromaHTaps[k] > 2.0
>+										&& ((mode_lib->vba.WritebackChromaHTaps[k] % 2) == 1))))) {
>+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
>+			}
>+			if (mode_lib->vba.WritebackVRatio[k] < 1.0) {
>+				mode_lib->vba.WritebackLumaVExtra =
>+						dml_max(1.0 - 2.0 / dml_ceil(1.0 / mode_lib->vba.WritebackVRatio[k], 1.0), 0.0);
>+			} else {
>+				mode_lib->vba.WritebackLumaVExtra = -1;
>+			}
>+			if ((mode_lib->vba.WritebackPixelFormat[k] == dm_444_32
>+					&& mode_lib->vba.WritebackLumaVTaps[k]
>+							> (mode_lib->vba.WritebackLineBufferLumaBufferSize
>+									+ mode_lib->vba.WritebackLineBufferChromaBufferSize)
>+									/ 3.0
>+									/ mode_lib->vba.WritebackDestinationWidth[k]
>+									- mode_lib->vba.WritebackLumaVExtra)
>+					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
>+							&& mode_lib->vba.WritebackLumaVTaps[k]
>+									> mode_lib->vba.WritebackLineBufferLumaBufferSize
>+											* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
>+											- mode_lib->vba.WritebackLumaVExtra)
>+					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
>+							&& mode_lib->vba.WritebackLumaVTaps[k]
>+									> mode_lib->vba.WritebackLineBufferLumaBufferSize
>+											* 8.0 / 10.0
>+											/ mode_lib->vba.WritebackDestinationWidth[k]
>+											- mode_lib->vba.WritebackLumaVExtra)) {
>+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
>+			}
>+			if (2.0 * mode_lib->vba.WritebackVRatio[k] < 1) {
>+				mode_lib->vba.WritebackChromaVExtra = 0.0;
>+			} else {
>+				mode_lib->vba.WritebackChromaVExtra = -1;
>+			}
>+			if ((mode_lib->vba.WritebackPixelFormat[k] == dm_420_8
>+					&& mode_lib->vba.WritebackChromaVTaps[k]
>+							> mode_lib->vba.WritebackLineBufferChromaBufferSize
>+									* 8.0 / 10.0 / mode_lib->vba.WritebackDestinationWidth[k]
>+									- mode_lib->vba.WritebackChromaVExtra)
>+					|| (mode_lib->vba.WritebackPixelFormat[k] == dm_420_10
>+							&& mode_lib->vba.WritebackChromaVTaps[k]
>+									> mode_lib->vba.WritebackLineBufferChromaBufferSize
>+											* 8.0 / 10.0
>+											/ mode_lib->vba.WritebackDestinationWidth[k]
>+											- mode_lib->vba.WritebackChromaVExtra)) {
>+				mode_lib->vba.WritebackScaleRatioAndTapsSupport = false;
>+			}
>+		}
>+	}
>+	/*Maximum DISPCLK/DPPCLK Support check*/
>+
>+	mode_lib->vba.WritebackRequiredDISPCLK = 0.0;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.WritebackEnable[k] == true) {
>+			mode_lib->vba.WritebackRequiredDISPCLK =
>+					dml_max(
>+							mode_lib->vba.WritebackRequiredDISPCLK,
>+							CalculateWriteBackDISPCLK(
>+									mode_lib->vba.WritebackPixelFormat[k],
>+									mode_lib->vba.PixelClock[k],
>+									mode_lib->vba.WritebackHRatio[k],
>+									mode_lib->vba.WritebackVRatio[k],
>+									mode_lib->vba.WritebackLumaHTaps[k],
>+									mode_lib->vba.WritebackLumaVTaps[k],
>+									mode_lib->vba.WritebackChromaHTaps[k],
>+									mode_lib->vba.WritebackChromaVTaps[k],
>+									mode_lib->vba.WritebackDestinationWidth[k],
>+									mode_lib->vba.HTotal[k],
>+									mode_lib->vba.WritebackChromaLineBufferWidth));
>+		}
>+	}
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.HRatio[k] > 1.0) {
>+			locals->PSCL_FACTOR[k] = dml_min(
>+					mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+					mode_lib->vba.MaxPSCLToLBThroughput
>+							* mode_lib->vba.HRatio[k]
>+							/ dml_ceil(
>+									mode_lib->vba.htaps[k]
>+											/ 6.0,
>+									1.0));
>+		} else {
>+			locals->PSCL_FACTOR[k] = dml_min(
>+					mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+					mode_lib->vba.MaxPSCLToLBThroughput);
>+		}
>+		if (locals->BytePerPixelInDETC[k] == 0.0) {
>+			locals->PSCL_FACTOR_CHROMA[k] = 0.0;
>+			locals->MinDPPCLKUsingSingleDPP[k] =
>+					mode_lib->vba.PixelClock[k]
>+							* dml_max3(
>+									mode_lib->vba.vtaps[k] / 6.0
>+											* dml_min(
>+													1.0,
>+													mode_lib->vba.HRatio[k]),
>+									mode_lib->vba.HRatio[k]
>+											* mode_lib->vba.VRatio[k]
>+											/ locals->PSCL_FACTOR[k],
>+									1.0);
>+			if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0)
>+					&& locals->MinDPPCLKUsingSingleDPP[k]
>+							< 2.0 * mode_lib->vba.PixelClock[k]) {
>+				locals->MinDPPCLKUsingSingleDPP[k] = 2.0
>+						* mode_lib->vba.PixelClock[k];
>+			}
>+		} else {
>+			if (mode_lib->vba.HRatio[k] / 2.0 > 1.0) {
>+				locals->PSCL_FACTOR_CHROMA[k] =
>+						dml_min(
>+								mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+								mode_lib->vba.MaxPSCLToLBThroughput
>+										* mode_lib->vba.HRatio[k]
>+										/ 2.0
>+										/ dml_ceil(
>+												mode_lib->vba.HTAPsChroma[k]
>+														/ 6.0,
>+												1.0));
>+			} else {
>+				locals->PSCL_FACTOR_CHROMA[k] = dml_min(
>+						mode_lib->vba.MaxDCHUBToPSCLThroughput,
>+						mode_lib->vba.MaxPSCLToLBThroughput);
>+			}
>+			locals->MinDPPCLKUsingSingleDPP[k] =
>+					mode_lib->vba.PixelClock[k]
>+							* dml_max5(
>+									mode_lib->vba.vtaps[k] / 6.0
>+											* dml_min(
>+													1.0,
>+													mode_lib->vba.HRatio[k]),
>+									mode_lib->vba.HRatio[k]
>+											* mode_lib->vba.VRatio[k]
>+											/ locals->PSCL_FACTOR[k],
>+									mode_lib->vba.VTAPsChroma[k]
>+											/ 6.0
>+											* dml_min(
>+													1.0,
>+													mode_lib->vba.HRatio[k]
>+															/ 2.0),
>+									mode_lib->vba.HRatio[k]
>+											* mode_lib->vba.VRatio[k]
>+											/ 4.0
>+											/ locals->PSCL_FACTOR_CHROMA[k],
>+									1.0);
>+			if ((mode_lib->vba.htaps[k] > 6.0 || mode_lib->vba.vtaps[k] > 6.0
>+					|| mode_lib->vba.HTAPsChroma[k] > 6.0
>+					|| mode_lib->vba.VTAPsChroma[k] > 6.0)
>+					&& locals->MinDPPCLKUsingSingleDPP[k]
>+							< 2.0 * mode_lib->vba.PixelClock[k]) {
>+				locals->MinDPPCLKUsingSingleDPP[k] = 2.0
>+						* mode_lib->vba.PixelClock[k];
>+			}
>+		}
>+	}
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		Calculate256BBlockSizes(
>+				mode_lib->vba.SourcePixelFormat[k],
>+				mode_lib->vba.SurfaceTiling[k],
>+				dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
>+				dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
>+				&locals->Read256BlockHeightY[k],
>+				&locals->Read256BlockHeightC[k],
>+				&locals->Read256BlockWidthY[k],
>+				&locals->Read256BlockWidthC[k]);
>+		if (mode_lib->vba.SourceScan[k] == dm_horz) {
>+			locals->MaxSwathHeightY[k] = locals->Read256BlockHeightY[k];
>+			locals->MaxSwathHeightC[k] = locals->Read256BlockHeightC[k];
>+		} else {
>+			locals->MaxSwathHeightY[k] = locals->Read256BlockWidthY[k];
>+			locals->MaxSwathHeightC[k] = locals->Read256BlockWidthC[k];
>+		}
>+		if ((mode_lib->vba.SourcePixelFormat[k] == dm_444_64
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_32
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_444_16
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_16
>+				|| mode_lib->vba.SourcePixelFormat[k] == dm_mono_8)) {
>+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear
>+					|| (mode_lib->vba.SourcePixelFormat[k] == dm_444_64
>+							&& (mode_lib->vba.SurfaceTiling[k]
>+									== dm_sw_4kb_s
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_4kb_s_x
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_64kb_s
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_64kb_s_t
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_64kb_s_x
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_var_s
>+									|| mode_lib->vba.SurfaceTiling[k]
>+											== dm_sw_var_s_x)
>+							&& mode_lib->vba.SourceScan[k] == dm_horz)) {
>+				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
>+			} else {
>+				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
>+						/ 2.0;
>+			}
>+			locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
>+		} else {
>+			if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
>+				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
>+				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_8
>+					&& mode_lib->vba.SourceScan[k] == dm_horz) {
>+				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k]
>+						/ 2.0;
>+				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
>+			} else if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10
>+					&& mode_lib->vba.SourceScan[k] == dm_horz) {
>+				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k]
>+						/ 2.0;
>+				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
>+			} else {
>+				locals->MinSwathHeightY[k] = locals->MaxSwathHeightY[k];
>+				locals->MinSwathHeightC[k] = locals->MaxSwathHeightC[k];
>+			}
>+		}
>+		if (mode_lib->vba.SurfaceTiling[k] == dm_sw_linear) {
>+			mode_lib->vba.MaximumSwathWidthSupport = 8192.0;
>+		} else {
>+			mode_lib->vba.MaximumSwathWidthSupport = 5120.0;
>+		}
>+		mode_lib->vba.MaximumSwathWidthInDETBuffer =
>+				dml_min(
>+						mode_lib->vba.MaximumSwathWidthSupport,
>+						mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0
>+								/ (locals->BytePerPixelInDETY[k]
>+										* locals->MinSwathHeightY[k]
>+										+ locals->BytePerPixelInDETC[k]
>+												/ 2.0
>+												* locals->MinSwathHeightC[k]));
>+		if (locals->BytePerPixelInDETC[k] == 0.0) {
>+			mode_lib->vba.MaximumSwathWidthInLineBuffer =
>+					mode_lib->vba.LineBufferSize
>+							* dml_max(mode_lib->vba.HRatio[k], 1.0)
>+							/ mode_lib->vba.LBBitPerPixel[k]
>+							/ (mode_lib->vba.vtaps[k]
>+									+ dml_max(
>+											dml_ceil(
>+													mode_lib->vba.VRatio[k],
>+													1.0)
>+													- 2,
>+											0.0));
>+		} else {
>+			mode_lib->vba.MaximumSwathWidthInLineBuffer =
>+					dml_min(
>+							mode_lib->vba.LineBufferSize
>+									* dml_max(
>+											mode_lib->vba.HRatio[k],
>+											1.0)
>+									/ mode_lib->vba.LBBitPerPixel[k]
>+									/ (mode_lib->vba.vtaps[k]
>+											+ dml_max(
>+													dml_ceil(
>+															mode_lib->vba.VRatio[k],
>+															1.0)
>+															- 2,
>+													0.0)),
>+							2.0 * mode_lib->vba.LineBufferSize
>+									* dml_max(
>+											mode_lib->vba.HRatio[k]
>+													/ 2.0,
>+											1.0)
>+									/ mode_lib->vba.LBBitPerPixel[k]
>+									/ (mode_lib->vba.VTAPsChroma[k]
>+											+ dml_max(
>+													dml_ceil(
>+															mode_lib->vba.VRatio[k]
>+																	/ 2.0,
>+															1.0)
>+															- 2,
>+													0.0)));
>+		}
>+		locals->MaximumSwathWidth[k] = dml_min(
>+				mode_lib->vba.MaximumSwathWidthInDETBuffer,
>+				mode_lib->vba.MaximumSwathWidthInLineBuffer);
>+	}
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (j = 0; j < 2; j++) {
>+			mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
>+				mode_lib->vba.MaxDispclk[i],
>+				mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
>+			mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(
>+				mode_lib->vba.MaxDppclk[i],
>+				mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
>+			locals->RequiredDISPCLK[i][j] = 0.0;
>+			locals->DISPCLK_DPPCLK_Support[i][j] = true;
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine =
>+						mode_lib->vba.PixelClock[k]
>+								* (1.0
>+										+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
>+												/ 100.0)
>+								* (1.0
>+										+ mode_lib->vba.DISPCLKRampingMargin
>+												/ 100.0);
>+				if (mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine >= mode_lib->vba.MaxDispclk[i]
>+						&& i == mode_lib->vba.soc.num_states)
>+					mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine = mode_lib->vba.PixelClock[k]
>+							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>+
>+				mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
>+					* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * (1 + mode_lib->vba.DISPCLKRampingMargin / 100.0);
>+				if (mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine >= mode_lib->vba.MaxDispclk[i]
>+						&& i == mode_lib->vba.soc.num_states)
>+					mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] / 2
>+							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>+				if (mode_lib->vba.ODMCapability == false || mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
>+					locals->ODMCombineEnablePerState[i][k] = false;
>+					mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
>+				} else {
>+					locals->ODMCombineEnablePerState[i][k] = true;
>+					mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
>+				}
>+				if (locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) <= mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
>+						&& locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]
>+						&& locals->ODMCombineEnablePerState[i][k] == false) {
>+					locals->NoOfDPP[i][j][k] = 1;
>+					locals->RequiredDPPCLK[i][j][k] =
>+						locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>+				} else {
>+					locals->NoOfDPP[i][j][k] = 2;
>+					locals->RequiredDPPCLK[i][j][k] =
>+						locals->MinDPPCLKUsingSingleDPP[k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
>+				}
>+				locals->RequiredDISPCLK[i][j] = dml_max(
>+						locals->RequiredDISPCLK[i][j],
>+						mode_lib->vba.PlaneRequiredDISPCLK);
>+				if ((locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
>+						> mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity)
>+						|| (mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)) {
>+					locals->DISPCLK_DPPCLK_Support[i][j] = false;
>+				}
>+			}
>+			locals->TotalNumberOfActiveDPP[i][j] = 0.0;
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
>+				locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
>+			if (j == 1) {
>+				while (locals->TotalNumberOfActiveDPP[i][j] < mode_lib->vba.MaxNumDPP
>+						&& locals->TotalNumberOfActiveDPP[i][j] < 2 * mode_lib->vba.NumberOfActivePlanes) {
>+					double BWOfNonSplitPlaneOfMaximumBandwidth;
>+					unsigned int NumberOfNonSplitPlaneOfMaximumBandwidth;
>+
>+					BWOfNonSplitPlaneOfMaximumBandwidth = 0;
>+					NumberOfNonSplitPlaneOfMaximumBandwidth = 0;
>+					for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+						if (locals->ReadBandwidth[k] > BWOfNonSplitPlaneOfMaximumBandwidth && locals->NoOfDPP[i][j][k] == 1) {
>+							BWOfNonSplitPlaneOfMaximumBandwidth = locals->ReadBandwidth[k];
>+							NumberOfNonSplitPlaneOfMaximumBandwidth = k;
>+						}
>+					}
>+					locals->NoOfDPP[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = 2;
>+					locals->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] =
>+						locals->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth]
>+							* (1 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2;
>+					locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + 1;
>+				}
>+			}
>+			if (locals->TotalNumberOfActiveDPP[i][j] > mode_lib->vba.MaxNumDPP) {
>+				locals->RequiredDISPCLK[i][j] = 0.0;
>+				locals->DISPCLK_DPPCLK_Support[i][j] = true;
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					locals->ODMCombineEnablePerState[i][k] = false;
>+					if (locals->SwathWidthYSingleDPP[k] <= locals->MaximumSwathWidth[k]) {
>+						locals->NoOfDPP[i][j][k] = 1;
>+						locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
>+							* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>+					} else {
>+						locals->NoOfDPP[i][j][k] = 2;
>+						locals->RequiredDPPCLK[i][j][k] = locals->MinDPPCLKUsingSingleDPP[k]
>+										* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
>+					}
>+					if (i != mode_lib->vba.soc.num_states) {
>+						mode_lib->vba.PlaneRequiredDISPCLK =
>+								mode_lib->vba.PixelClock[k]
>+										* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
>+										* (1.0 + mode_lib->vba.DISPCLKRampingMargin / 100.0);
>+					} else {
>+						mode_lib->vba.PlaneRequiredDISPCLK = mode_lib->vba.PixelClock[k]
>+							* (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>+					}
>+					locals->RequiredDISPCLK[i][j] = dml_max(
>+							locals->RequiredDISPCLK[i][j],
>+							mode_lib->vba.PlaneRequiredDISPCLK);
>+					if (locals->MinDPPCLKUsingSingleDPP[k] / locals->NoOfDPP[i][j][k] * (1.0 + mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
>+							> mode_lib->vba.MaxDppclkRoundedDownToDFSGranularity
>+							|| mode_lib->vba.PlaneRequiredDISPCLK > mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity)
>+						locals->DISPCLK_DPPCLK_Support[i][j] = false;
>+				}
>+				locals->TotalNumberOfActiveDPP[i][j] = 0.0;
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++)
>+					locals->TotalNumberOfActiveDPP[i][j] = locals->TotalNumberOfActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
>+			}
>+			locals->RequiredDISPCLK[i][j] = dml_max(
>+					locals->RequiredDISPCLK[i][j],
>+					mode_lib->vba.WritebackRequiredDISPCLK);
>+			if (mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity
>+					< mode_lib->vba.WritebackRequiredDISPCLK) {
>+				locals->DISPCLK_DPPCLK_Support[i][j] = false;
>+			}
>+		}
>+	}
>+	/*Viewport Size Check*/
>+
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		locals->ViewportSizeSupport[i] = true;
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			if (locals->ODMCombineEnablePerState[i][k] == true) {
>+				if (dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]))
>+						> locals->MaximumSwathWidth[k]) {
>+					locals->ViewportSizeSupport[i] = false;
>+				}
>+			} else {
>+				if (locals->SwathWidthYSingleDPP[k] / 2.0 > locals->MaximumSwathWidth[k]) {
>+					locals->ViewportSizeSupport[i] = false;
>+				}
>+			}
>+		}
>+	}
>+	/*Total Available Pipes Support Check*/
>+
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (j = 0; j < 2; j++) {
>+			if (locals->TotalNumberOfActiveDPP[i][j] <= mode_lib->vba.MaxNumDPP)
>+				locals->TotalAvailablePipesSupport[i][j] = true;
>+			else
>+				locals->TotalAvailablePipesSupport[i][j] = false;
>+		}
>+	}
>+	/*Total Available OTG Support Check*/
>+
>+	mode_lib->vba.TotalNumberOfActiveOTG = 0.0;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+			mode_lib->vba.TotalNumberOfActiveOTG = mode_lib->vba.TotalNumberOfActiveOTG
>+					+ 1.0;
>+		}
>+	}
>+	if (mode_lib->vba.TotalNumberOfActiveOTG <= mode_lib->vba.MaxNumOTG) {
>+		mode_lib->vba.NumberOfOTGSupport = true;
>+	} else {
>+		mode_lib->vba.NumberOfOTGSupport = false;
>+	}
>+	/*Display IO and DSC Support Check*/
>+
>+	mode_lib->vba.NonsupportedDSCInputBPC = false;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (!(mode_lib->vba.DSCInputBitPerComponent[k] == 12.0
>+				|| mode_lib->vba.DSCInputBitPerComponent[k] == 10.0
>+				|| mode_lib->vba.DSCInputBitPerComponent[k] == 8.0)) {
>+			mode_lib->vba.NonsupportedDSCInputBPC = true;
>+		}
>+	}
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			locals->RequiresDSC[i][k] = 0;
>+			locals->RequiresFEC[i][k] = 0;
>+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+				if (mode_lib->vba.Output[k] == dm_hdmi) {
>+					locals->RequiresDSC[i][k] = 0;
>+					locals->RequiresFEC[i][k] = 0;
>+					locals->OutputBppPerState[i][k] = TruncToValidBPP(
>+							dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24,
>+							mode_lib->vba.ForcedOutputLinkBPP[k],
>+							false,
>+							mode_lib->vba.Output[k],
>+							mode_lib->vba.OutputFormat[k],
>+							mode_lib->vba.DSCInputBitPerComponent[k]);
>+				} else if (mode_lib->vba.Output[k] == dm_dp
>+						|| mode_lib->vba.Output[k] == dm_edp) {
>+					if (mode_lib->vba.Output[k] == dm_edp) {
>+						mode_lib->vba.EffectiveFECOverhead = 0.0;
>+					} else {
>+						mode_lib->vba.EffectiveFECOverhead =
>+								mode_lib->vba.FECOverhead;
>+					}
>+					if (mode_lib->vba.PHYCLKPerState[i] >= 270.0) {
>+						mode_lib->vba.Outbpp = TruncToValidBPP(
>+								(1.0 - mode_lib->vba.Downspreading / 100.0) * 270.0
>+								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
>+								mode_lib->vba.ForcedOutputLinkBPP[k],
>+								false,
>+								mode_lib->vba.Output[k],
>+								mode_lib->vba.OutputFormat[k],
>+								mode_lib->vba.DSCInputBitPerComponent[k]);
>+						mode_lib->vba.OutbppDSC = TruncToValidBPP(
>+								(1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 270.0
>+								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
>+								mode_lib->vba.ForcedOutputLinkBPP[k],
>+								true,
>+								mode_lib->vba.Output[k],
>+								mode_lib->vba.OutputFormat[k],
>+								mode_lib->vba.DSCInputBitPerComponent[k]);
>+						if (mode_lib->vba.DSCEnabled[k] == true) {
>+							locals->RequiresDSC[i][k] = true;
>+							if (mode_lib->vba.Output[k] == dm_dp) {
>+								locals->RequiresFEC[i][k] = true;
>+							} else {
>+								locals->RequiresFEC[i][k] = false;
>+							}
>+							mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC;
>+						} else {
>+							locals->RequiresDSC[i][k] = false;
>+							locals->RequiresFEC[i][k] = false;
>+						}
>+						locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
>+					}
>+					if (mode_lib->vba.Outbpp == BPP_INVALID && mode_lib->vba.PHYCLKPerState[i] >= 540.0) {
>+						mode_lib->vba.Outbpp = TruncToValidBPP(
>+								(1.0 - mode_lib->vba.Downspreading / 100.0) * 540.0
>+								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
>+								mode_lib->vba.ForcedOutputLinkBPP[k],
>+									false,
>+									mode_lib->vba.Output[k],
>+									mode_lib->vba.OutputFormat[k],
>+									mode_lib->vba.DSCInputBitPerComponent[k]);
>+						mode_lib->vba.OutbppDSC = TruncToValidBPP(
>+								(1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 540.0
>+								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
>+								mode_lib->vba.ForcedOutputLinkBPP[k],
>+								true,
>+								mode_lib->vba.Output[k],
>+								mode_lib->vba.OutputFormat[k],
>+								mode_lib->vba.DSCInputBitPerComponent[k]);
>+						if (mode_lib->vba.DSCEnabled[k] == true) {
>+							locals->RequiresDSC[i][k] = true;
>+							if (mode_lib->vba.Output[k] == dm_dp) {
>+								locals->RequiresFEC[i][k] = true;
>+							} else {
>+								locals->RequiresFEC[i][k] = false;
>+							}
>+							mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC;
>+						} else {
>+							locals->RequiresDSC[i][k] = false;
>+							locals->RequiresFEC[i][k] = false;
>+						}
>+						locals->OutputBppPerState[i][k] = mode_lib->vba.Outbpp;
>+					}
>+					if (mode_lib->vba.Outbpp == BPP_INVALID
>+							&& mode_lib->vba.PHYCLKPerState[i]
>+									>= 810.0) {
>+						mode_lib->vba.Outbpp = TruncToValidBPP(
>+								(1.0 - mode_lib->vba.Downspreading / 100.0) * 810.0
>+								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
>+								mode_lib->vba.ForcedOutputLinkBPP[k],
>+								false,
>+								mode_lib->vba.Output[k],
>+								mode_lib->vba.OutputFormat[k],
>+								mode_lib->vba.DSCInputBitPerComponent[k]);
>+						mode_lib->vba.OutbppDSC = TruncToValidBPP(
>+								(1.0 - mode_lib->vba.Downspreading / 100.0) * (1.0 - mode_lib->vba.EffectiveFECOverhead / 100.0) * 810.0
>+								* mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0,
>+								mode_lib->vba.ForcedOutputLinkBPP[k],
>+								true,
>+								mode_lib->vba.Output[k],
>+								mode_lib->vba.OutputFormat[k],
>+								mode_lib->vba.DSCInputBitPerComponent[k]);
>+						if (mode_lib->vba.DSCEnabled[k] == true || mode_lib->vba.Outbpp == BPP_INVALID) {
>+							locals->RequiresDSC[i][k] = true;
>+							if (mode_lib->vba.Output[k] == dm_dp) {
>+								locals->RequiresFEC[i][k] = true;
>+							} else {
>+								locals->RequiresFEC[i][k] = false;
>+							}
>+							mode_lib->vba.Outbpp = mode_lib->vba.OutbppDSC;
>+						} else {
>+							locals->RequiresDSC[i][k] = false;
>+							locals->RequiresFEC[i][k] = false;
>+						}
>+						locals->OutputBppPerState[i][k] =
>+								mode_lib->vba.Outbpp;
>+					}
>+				}
>+			} else {
>+				locals->OutputBppPerState[i][k] = BPP_BLENDED_PIPE;
>+			}
>+		}
>+	}
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		locals->DIOSupport[i] = true;
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			if (locals->OutputBppPerState[i][k] == BPP_INVALID
>+					|| (mode_lib->vba.OutputFormat[k] == dm_420
>+							&& mode_lib->vba.Interlace[k] == true
>+							&& mode_lib->vba.ProgressiveToInterlaceUnitInOPP == true)) {
>+				locals->DIOSupport[i] = false;
>+			}
>+		}
>+	}
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			locals->DSCCLKRequiredMoreThanSupported[i] = false;
>+			if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+				if ((mode_lib->vba.Output[k] == dm_dp
>+						|| mode_lib->vba.Output[k] == dm_edp)) {
>+					if (mode_lib->vba.OutputFormat[k] == dm_420
>+							|| mode_lib->vba.OutputFormat[k]
>+									== dm_n422) {
>+						mode_lib->vba.DSCFormatFactor = 2;
>+					} else {
>+						mode_lib->vba.DSCFormatFactor = 1;
>+					}
>+					if (locals->RequiresDSC[i][k] == true) {
>+						if (locals->ODMCombineEnablePerState[i][k]
>+								== true) {
>+							if (mode_lib->vba.PixelClockBackEnd[k] / 6.0 / mode_lib->vba.DSCFormatFactor
>+									> (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) {
>+								locals->DSCCLKRequiredMoreThanSupported[i] =
>+										true;
>+							}
>+						} else {
>+							if (mode_lib->vba.PixelClockBackEnd[k] / 3.0 / mode_lib->vba.DSCFormatFactor
>+									> (1.0 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * mode_lib->vba.MaxDSCCLK[i]) {
>+								locals->DSCCLKRequiredMoreThanSupported[i] =
>+										true;
>+							}
>+						}
>+					}
>+				}
>+			}
>+		}
>+	}
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		locals->NotEnoughDSCUnits[i] = false;
>+		mode_lib->vba.TotalDSCUnitsRequired = 0.0;
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			if (locals->RequiresDSC[i][k] == true) {
>+				if (locals->ODMCombineEnablePerState[i][k] == true) {
>+					mode_lib->vba.TotalDSCUnitsRequired =
>+							mode_lib->vba.TotalDSCUnitsRequired + 2.0;
>+				} else {
>+					mode_lib->vba.TotalDSCUnitsRequired =
>+							mode_lib->vba.TotalDSCUnitsRequired + 1.0;
>+				}
>+			}
>+		}
>+		if (mode_lib->vba.TotalDSCUnitsRequired > mode_lib->vba.NumberOfDSC) {
>+			locals->NotEnoughDSCUnits[i] = true;
>+		}
>+	}
>+	/*DSC Delay per state*/
>+
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			if (mode_lib->vba.BlendingAndTiming[k] != k) {
>+				mode_lib->vba.slices = 0;
>+			} else if (locals->RequiresDSC[i][k] == 0
>+					|| locals->RequiresDSC[i][k] == false) {
>+				mode_lib->vba.slices = 0;
>+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 3200.0) {
>+				mode_lib->vba.slices = dml_ceil(
>+						mode_lib->vba.PixelClockBackEnd[k] / 400.0,
>+						4.0);
>+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 1360.0) {
>+				mode_lib->vba.slices = 8.0;
>+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 680.0) {
>+				mode_lib->vba.slices = 4.0;
>+			} else if (mode_lib->vba.PixelClockBackEnd[k] > 340.0) {
>+				mode_lib->vba.slices = 2.0;
>+			} else {
>+				mode_lib->vba.slices = 1.0;
>+			}
>+			if (locals->OutputBppPerState[i][k] == BPP_BLENDED_PIPE
>+					|| locals->OutputBppPerState[i][k] == BPP_INVALID) {
>+				mode_lib->vba.bpp = 0.0;
>+			} else {
>+				mode_lib->vba.bpp = locals->OutputBppPerState[i][k];
>+			}
>+			if (locals->RequiresDSC[i][k] == true && mode_lib->vba.bpp != 0.0) {
>+				if (locals->ODMCombineEnablePerState[i][k] == false) {
>+					locals->DSCDelayPerState[i][k] =
>+							dscceComputeDelay(
>+									mode_lib->vba.DSCInputBitPerComponent[k],
>+									mode_lib->vba.bpp,
>+									dml_ceil(
>+											mode_lib->vba.HActive[k]
>+													/ mode_lib->vba.slices,
>+											1.0),
>+									mode_lib->vba.slices,
>+									mode_lib->vba.OutputFormat[k])
>+									+ dscComputeDelay(
>+											mode_lib->vba.OutputFormat[k]);
>+				} else {
>+					locals->DSCDelayPerState[i][k] =
>+							2.0 * (dscceComputeDelay(
>+											mode_lib->vba.DSCInputBitPerComponent[k],
>+											mode_lib->vba.bpp,
>+											dml_ceil(mode_lib->vba.HActive[k] / mode_lib->vba.slices, 1.0),
>+											mode_lib->vba.slices / 2,
>+											mode_lib->vba.OutputFormat[k])
>+									+ dscComputeDelay(mode_lib->vba.OutputFormat[k]));
>+				}
>+				locals->DSCDelayPerState[i][k] =
>+						locals->DSCDelayPerState[i][k] * mode_lib->vba.PixelClock[k] / mode_lib->vba.PixelClockBackEnd[k];
>+			} else {
>+				locals->DSCDelayPerState[i][k] = 0.0;
>+			}
>+		}
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) {
>+				for (j = 0; j <= mode_lib->vba.NumberOfActivePlanes - 1; j++) {
>+					if (mode_lib->vba.BlendingAndTiming[k] == m && locals->RequiresDSC[i][m] == true)
>+						locals->DSCDelayPerState[i][k] = locals->DSCDelayPerState[i][m];
>+				}
>+			}
>+		}
>+	}
>+
>+	//Prefetch Check
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; ++i) {
>+		for (j = 0; j <= 1; ++j) {
>+			locals->TotalNumberOfDCCActiveDPP[i][j] = 0;
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				if (mode_lib->vba.DCCEnable[k] == true)
>+					locals->TotalNumberOfDCCActiveDPP[i][j] = locals->TotalNumberOfDCCActiveDPP[i][j] + locals->NoOfDPP[i][j][k];
>+			}
>+		}
>+	}
>+
>+	mode_lib->vba.UrgentLatency = dml_max3(
>+			mode_lib->vba.UrgentLatencyPixelDataOnly,
>+			mode_lib->vba.UrgentLatencyPixelMixedWithVMData,
>+			mode_lib->vba.UrgentLatencyVMDataOnly);
>+	mode_lib->vba.PrefetchERROR = CalculateMinAndMaxPrefetchMode(
>+			mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
>+			&mode_lib->vba.MinPrefetchMode,
>+			&mode_lib->vba.MaxPrefetchMode);
>+
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (j = 0; j < 2; j++) {
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				locals->RequiredDPPCLKThisState[k] = locals->RequiredDPPCLK[i][j][k];
>+				locals->NoOfDPPThisState[k]        = locals->NoOfDPP[i][j][k];
>+				if (locals->ODMCombineEnablePerState[i][k] == true) {
>+					locals->SwathWidthYThisState[k] =
>+						dml_min(locals->SwathWidthYSingleDPP[k], dml_round(mode_lib->vba.HActive[k] / 2.0 * mode_lib->vba.HRatio[k]));
>+				} else {
>+					locals->SwathWidthYThisState[k] = locals->SwathWidthYSingleDPP[k] / locals->NoOfDPP[i][j][k];
>+				}
>+				mode_lib->vba.SwathWidthGranularityY = 256.0
>+					/ dml_ceil(locals->BytePerPixelInDETY[k], 1.0)
>+					/ locals->MaxSwathHeightY[k];
>+				mode_lib->vba.RoundedUpMaxSwathSizeBytesY =
>+					(dml_ceil(locals->SwathWidthYThisState[k] - 1.0, mode_lib->vba.SwathWidthGranularityY)
>+					+ mode_lib->vba.SwathWidthGranularityY) * locals->BytePerPixelInDETY[k] * locals->MaxSwathHeightY[k];
>+				if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
>+					mode_lib->vba.RoundedUpMaxSwathSizeBytesY = dml_ceil(
>+							mode_lib->vba.RoundedUpMaxSwathSizeBytesY,
>+							256.0) + 256;
>+				}
>+				if (locals->MaxSwathHeightC[k] > 0.0) {
>+					mode_lib->vba.SwathWidthGranularityC = 256.0 / dml_ceil(locals->BytePerPixelInDETC[k], 2.0) / locals->MaxSwathHeightC[k];
>+					mode_lib->vba.RoundedUpMaxSwathSizeBytesC = (dml_ceil(locals->SwathWidthYThisState[k] / 2.0 - 1.0, mode_lib->vba.SwathWidthGranularityC)
>+							+ mode_lib->vba.SwathWidthGranularityC) * locals->BytePerPixelInDETC[k] * locals->MaxSwathHeightC[k];
>+					if (mode_lib->vba.SourcePixelFormat[k] == dm_420_10) {
>+						mode_lib->vba.RoundedUpMaxSwathSizeBytesC = dml_ceil(mode_lib->vba.RoundedUpMaxSwathSizeBytesC, 256.0) + 256;
>+					}
>+				} else {
>+					mode_lib->vba.RoundedUpMaxSwathSizeBytesC = 0.0;
>+				}
>+				if (mode_lib->vba.RoundedUpMaxSwathSizeBytesY + mode_lib->vba.RoundedUpMaxSwathSizeBytesC
>+						<= mode_lib->vba.DETBufferSizeInKByte * 1024.0 / 2.0) {
>+					locals->SwathHeightYThisState[k] = locals->MaxSwathHeightY[k];
>+					locals->SwathHeightCThisState[k] = locals->MaxSwathHeightC[k];
>+				} else {
>+					locals->SwathHeightYThisState[k] =
>+							locals->MinSwathHeightY[k];
>+					locals->SwathHeightCThisState[k] =
>+							locals->MinSwathHeightC[k];
>+				}
>+			}
>+
>+			CalculateDCFCLKDeepSleep(
>+					mode_lib,
>+					mode_lib->vba.NumberOfActivePlanes,
>+					locals->BytePerPixelInDETY,
>+					locals->BytePerPixelInDETC,
>+					mode_lib->vba.VRatio,
>+					locals->SwathWidthYThisState,
>+					locals->NoOfDPPThisState,
>+					mode_lib->vba.HRatio,
>+					mode_lib->vba.PixelClock,
>+					locals->PSCL_FACTOR,
>+					locals->PSCL_FACTOR_CHROMA,
>+					locals->RequiredDPPCLKThisState,
>+					&mode_lib->vba.ProjectedDCFCLKDeepSleep);
>+
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				if ((mode_lib->vba.SourcePixelFormat[k] != dm_444_64
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
>+						&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8)) {
>+					mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes(
>+							mode_lib,
>+							mode_lib->vba.DCCEnable[k],
>+							locals->Read256BlockHeightC[k],
>+							locals->Read256BlockWidthC[k],
>+							mode_lib->vba.SourcePixelFormat[k],
>+							mode_lib->vba.SurfaceTiling[k],
>+							dml_ceil(locals->BytePerPixelInDETC[k], 2.0),
>+							mode_lib->vba.SourceScan[k],
>+							mode_lib->vba.ViewportWidth[k] / 2.0,
>+							mode_lib->vba.ViewportHeight[k] / 2.0,
>+							locals->SwathWidthYThisState[k] / 2.0,
>+							mode_lib->vba.GPUVMEnable,
>+							mode_lib->vba.HostVMEnable,
>+							mode_lib->vba.HostVMMaxPageTableLevels,
>+							mode_lib->vba.HostVMCachedPageTableLevels,
>+							mode_lib->vba.VMMPageSize,
>+							mode_lib->vba.PTEBufferSizeInRequestsChroma,
>+							mode_lib->vba.PitchC[k],
>+							0.0,
>+							&locals->MacroTileWidthC[k],
>+							&mode_lib->vba.MetaRowBytesC,
>+							&mode_lib->vba.DPTEBytesPerRowC,
>+							&locals->PTEBufferSizeNotExceededC[i][j][k],
>+							locals->dpte_row_width_chroma_ub,
>+							&locals->dpte_row_height_chroma[k],
>+							&locals->meta_req_width_chroma[k],
>+							&locals->meta_req_height_chroma[k],
>+							&locals->meta_row_width_chroma[k],
>+							&locals->meta_row_height_chroma[k],
>+							&locals->vm_group_bytes_chroma,
>+							&locals->dpte_group_bytes_chroma,
>+							locals->PixelPTEReqWidthC,
>+							locals->PixelPTEReqHeightC,
>+							locals->PTERequestSizeC,
>+							locals->dpde0_bytes_per_frame_ub_c,
>+							locals->meta_pte_bytes_per_frame_ub_c);
>+					locals->PrefetchLinesC[k] = CalculatePrefetchSourceLines(
>+							mode_lib,
>+							mode_lib->vba.VRatio[k]/2,
>+							mode_lib->vba.VTAPsChroma[k],
>+							mode_lib->vba.Interlace[k],
>+							mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+							locals->SwathHeightCThisState[k],
>+							mode_lib->vba.ViewportYStartC[k],
>+							&locals->PrefillC[k],
>+							&locals->MaxNumSwC[k]);
>+					locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma;
>+				} else {
>+					mode_lib->vba.PDEAndMetaPTEBytesPerFrameC = 0.0;
>+					mode_lib->vba.MetaRowBytesC = 0.0;
>+					mode_lib->vba.DPTEBytesPerRowC = 0.0;
>+					locals->PrefetchLinesC[k] = 0.0;
>+					locals->PTEBufferSizeNotExceededC[i][j][k] = true;
>+					locals->PTEBufferSizeInRequestsForLuma = mode_lib->vba.PTEBufferSizeInRequestsLuma + mode_lib->vba.PTEBufferSizeInRequestsChroma;
>+				}
>+				mode_lib->vba.PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes(
>+						mode_lib,
>+						mode_lib->vba.DCCEnable[k],
>+						locals->Read256BlockHeightY[k],
>+						locals->Read256BlockWidthY[k],
>+						mode_lib->vba.SourcePixelFormat[k],
>+						mode_lib->vba.SurfaceTiling[k],
>+						dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
>+						mode_lib->vba.SourceScan[k],
>+						mode_lib->vba.ViewportWidth[k],
>+						mode_lib->vba.ViewportHeight[k],
>+						locals->SwathWidthYThisState[k],
>+						mode_lib->vba.GPUVMEnable,
>+						mode_lib->vba.HostVMEnable,
>+						mode_lib->vba.HostVMMaxPageTableLevels,
>+						mode_lib->vba.HostVMCachedPageTableLevels,
>+						mode_lib->vba.VMMPageSize,
>+						locals->PTEBufferSizeInRequestsForLuma,
>+						mode_lib->vba.PitchY[k],
>+						mode_lib->vba.DCCMetaPitchY[k],
>+						&locals->MacroTileWidthY[k],
>+						&mode_lib->vba.MetaRowBytesY,
>+						&mode_lib->vba.DPTEBytesPerRowY,
>+						&locals->PTEBufferSizeNotExceededY[i][j][k],
>+						locals->dpte_row_width_luma_ub,
>+						&locals->dpte_row_height[k],
>+						&locals->meta_req_width[k],
>+						&locals->meta_req_height[k],
>+						&locals->meta_row_width[k],
>+						&locals->meta_row_height[k],
>+						&locals->vm_group_bytes[k],
>+						&locals->dpte_group_bytes[k],
>+						locals->PixelPTEReqWidthY,
>+						locals->PixelPTEReqHeightY,
>+						locals->PTERequestSizeY,
>+						locals->dpde0_bytes_per_frame_ub_l,
>+						locals->meta_pte_bytes_per_frame_ub_l);
>+				locals->PrefetchLinesY[k] = CalculatePrefetchSourceLines(
>+						mode_lib,
>+						mode_lib->vba.VRatio[k],
>+						mode_lib->vba.vtaps[k],
>+						mode_lib->vba.Interlace[k],
>+						mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+						locals->SwathHeightYThisState[k],
>+						mode_lib->vba.ViewportYStartY[k],
>+						&locals->PrefillY[k],
>+						&locals->MaxNumSwY[k]);
>+				locals->PDEAndMetaPTEBytesPerFrame[k] =
>+						mode_lib->vba.PDEAndMetaPTEBytesPerFrameY + mode_lib->vba.PDEAndMetaPTEBytesPerFrameC;
>+				locals->MetaRowBytes[k] = mode_lib->vba.MetaRowBytesY + mode_lib->vba.MetaRowBytesC;
>+				locals->DPTEBytesPerRow[k] = mode_lib->vba.DPTEBytesPerRowY + mode_lib->vba.DPTEBytesPerRowC;
>+
>+				CalculateActiveRowBandwidth(
>+						mode_lib->vba.GPUVMEnable,
>+						mode_lib->vba.SourcePixelFormat[k],
>+						mode_lib->vba.VRatio[k],
>+						mode_lib->vba.DCCEnable[k],
>+						mode_lib->vba.HTotal[k] /
>+						mode_lib->vba.PixelClock[k],
>+						mode_lib->vba.MetaRowBytesY,
>+						mode_lib->vba.MetaRowBytesC,
>+						locals->meta_row_height[k],
>+						locals->meta_row_height_chroma[k],
>+						mode_lib->vba.DPTEBytesPerRowY,
>+						mode_lib->vba.DPTEBytesPerRowC,
>+						locals->dpte_row_height[k],
>+						locals->dpte_row_height_chroma[k],
>+						&locals->meta_row_bw[k],
>+						&locals->dpte_row_bw[k]);
>+			}
>+			mode_lib->vba.ExtraLatency = CalculateExtraLatency(
>+					locals->UrgentRoundTripAndOutOfOrderLatencyPerState[i],
>+					locals->TotalNumberOfActiveDPP[i][j],
>+					mode_lib->vba.PixelChunkSizeInKByte,
>+					locals->TotalNumberOfDCCActiveDPP[i][j],
>+					mode_lib->vba.MetaChunkSize,
>+					locals->ReturnBWPerState[i],
>+					mode_lib->vba.GPUVMEnable,
>+					mode_lib->vba.HostVMEnable,
>+					mode_lib->vba.NumberOfActivePlanes,
>+					locals->NoOfDPPThisState,
>+					locals->dpte_group_bytes,
>+					mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
>+					mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
>+					mode_lib->vba.HostVMMaxPageTableLevels,
>+					mode_lib->vba.HostVMCachedPageTableLevels);
>+
>+			mode_lib->vba.TimeCalc = 24.0 / mode_lib->vba.ProjectedDCFCLKDeepSleep;
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+					if (mode_lib->vba.WritebackEnable[k] == true) {
>+						locals->WritebackDelay[i][k] = mode_lib->vba.WritebackLatency
>+								+ CalculateWriteBackDelay(
>+										mode_lib->vba.WritebackPixelFormat[k],
>+										mode_lib->vba.WritebackHRatio[k],
>+										mode_lib->vba.WritebackVRatio[k],
>+										mode_lib->vba.WritebackLumaHTaps[k],
>+										mode_lib->vba.WritebackLumaVTaps[k],
>+										mode_lib->vba.WritebackChromaHTaps[k],
>+										mode_lib->vba.WritebackChromaVTaps[k],
>+										mode_lib->vba.WritebackDestinationWidth[k]) / locals->RequiredDISPCLK[i][j];
>+					} else {
>+						locals->WritebackDelay[i][k] = 0.0;
>+					}
>+					for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) {
>+						if (mode_lib->vba.BlendingAndTiming[m] == k
>+								&& mode_lib->vba.WritebackEnable[m]
>+										== true) {
>+							locals->WritebackDelay[i][k] = dml_max(locals->WritebackDelay[i][k],
>+											mode_lib->vba.WritebackLatency + CalculateWriteBackDelay(
>+													mode_lib->vba.WritebackPixelFormat[m],
>+													mode_lib->vba.WritebackHRatio[m],
>+													mode_lib->vba.WritebackVRatio[m],
>+													mode_lib->vba.WritebackLumaHTaps[m],
>+													mode_lib->vba.WritebackLumaVTaps[m],
>+													mode_lib->vba.WritebackChromaHTaps[m],
>+													mode_lib->vba.WritebackChromaVTaps[m],
>+													mode_lib->vba.WritebackDestinationWidth[m]) / locals->RequiredDISPCLK[i][j]);
>+						}
>+					}
>+				}
>+			}
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				for (m = 0; m <= mode_lib->vba.NumberOfActivePlanes - 1; m++) {
>+					if (mode_lib->vba.BlendingAndTiming[k] == m) {
>+						locals->WritebackDelay[i][k] = locals->WritebackDelay[i][m];
>+					}
>+				}
>+			}
>+			mode_lib->vba.MaxMaxVStartup = 0;
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				locals->MaximumVStartup[k] = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k]
>+					- dml_max(1.0, dml_ceil(locals->WritebackDelay[i][k] / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1.0));
>+				mode_lib->vba.MaxMaxVStartup = dml_max(mode_lib->vba.MaxMaxVStartup, locals->MaximumVStartup[k]);
>+			}
>+
>+			mode_lib->vba.NextPrefetchMode = mode_lib->vba.MinPrefetchMode;
>+			mode_lib->vba.NextMaxVStartup = mode_lib->vba.MaxMaxVStartup;
>+			do {
>+				mode_lib->vba.PrefetchMode[i][j] = mode_lib->vba.NextPrefetchMode;
>+				mode_lib->vba.MaxVStartup = mode_lib->vba.NextMaxVStartup;
>+
>+				mode_lib->vba.TWait = CalculateTWait(
>+						mode_lib->vba.PrefetchMode[i][j],
>+						mode_lib->vba.DRAMClockChangeLatency,
>+						mode_lib->vba.UrgentLatency,
>+						mode_lib->vba.SREnterPlusExitTime);
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					Pipe myPipe;
>+					HostVM myHostVM;
>+
>+					if (mode_lib->vba.XFCEnabled[k] == true) {
>+						mode_lib->vba.XFCRemoteSurfaceFlipDelay =
>+								CalculateRemoteSurfaceFlipDelay(
>+										mode_lib,
>+										mode_lib->vba.VRatio[k],
>+										locals->SwathWidthYThisState[k],
>+										dml_ceil(locals->BytePerPixelInDETY[k], 1.0),
>+										mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
>+										mode_lib->vba.XFCTSlvVupdateOffset,
>+										mode_lib->vba.XFCTSlvVupdateWidth,
>+										mode_lib->vba.XFCTSlvVreadyOffset,
>+										mode_lib->vba.XFCXBUFLatencyTolerance,
>+										mode_lib->vba.XFCFillBWOverhead,
>+										mode_lib->vba.XFCSlvChunkSize,
>+										mode_lib->vba.XFCBusTransportTime,
>+										mode_lib->vba.TimeCalc,
>+										mode_lib->vba.TWait,
>+										&mode_lib->vba.SrcActiveDrainRate,
>+										&mode_lib->vba.TInitXFill,
>+										&mode_lib->vba.TslvChk);
>+					} else {
>+						mode_lib->vba.XFCRemoteSurfaceFlipDelay = 0.0;
>+					}
>+
>+					myPipe.DPPCLK = locals->RequiredDPPCLK[i][j][k];
>+					myPipe.DISPCLK = locals->RequiredDISPCLK[i][j];
>+					myPipe.PixelClock = mode_lib->vba.PixelClock[k];
>+					myPipe.DCFCLKDeepSleep = mode_lib->vba.ProjectedDCFCLKDeepSleep;
>+					myPipe.DPPPerPlane = locals->NoOfDPP[i][j][k];
>+					myPipe.ScalerEnabled = mode_lib->vba.ScalerEnabled[k];
>+					myPipe.SourceScan = mode_lib->vba.SourceScan[k];
>+					myPipe.BlockWidth256BytesY = locals->Read256BlockWidthY[k];
>+					myPipe.BlockHeight256BytesY = locals->Read256BlockHeightY[k];
>+					myPipe.BlockWidth256BytesC = locals->Read256BlockWidthC[k];
>+					myPipe.BlockHeight256BytesC = locals->Read256BlockHeightC[k];
>+					myPipe.InterlaceEnable = mode_lib->vba.Interlace[k];
>+					myPipe.NumberOfCursors = mode_lib->vba.NumberOfCursors[k];
>+					myPipe.VBlank = mode_lib->vba.VTotal[k] - mode_lib->vba.VActive[k];
>+					myPipe.HTotal = mode_lib->vba.HTotal[k];
>+
>+
>+					myHostVM.Enable = mode_lib->vba.HostVMEnable;
>+					myHostVM.MaxPageTableLevels = mode_lib->vba.HostVMMaxPageTableLevels;
>+					myHostVM.CachedPageTableLevels = mode_lib->vba.HostVMCachedPageTableLevels;
>+
>+
>+					mode_lib->vba.IsErrorResult[i][j][k] = CalculatePrefetchSchedule(
>+							mode_lib,
>+							mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
>+							mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
>+							&myPipe,
>+							locals->DSCDelayPerState[i][k],
>+							mode_lib->vba.DPPCLKDelaySubtotal,
>+							mode_lib->vba.DPPCLKDelaySCL,
>+							mode_lib->vba.DPPCLKDelaySCLLBOnly,
>+							mode_lib->vba.DPPCLKDelayCNVCFormater,
>+							mode_lib->vba.DPPCLKDelayCNVCCursor,
>+							mode_lib->vba.DISPCLKDelaySubtotal,
>+							locals->SwathWidthYThisState[k] / mode_lib->vba.HRatio[k],
>+							mode_lib->vba.OutputFormat[k],
>+							mode_lib->vba.MaxInterDCNTileRepeaters,
>+							dml_min(mode_lib->vba.MaxVStartup, locals->MaximumVStartup[k]),
>+							locals->MaximumVStartup[k],
>+							mode_lib->vba.GPUVMMaxPageTableLevels,
>+							mode_lib->vba.GPUVMEnable,
>+							&myHostVM,
>+							mode_lib->vba.DynamicMetadataEnable[k],
>+							mode_lib->vba.DynamicMetadataLinesBeforeActiveRequired[k],
>+							mode_lib->vba.DynamicMetadataTransmittedBytes[k],
>+							mode_lib->vba.DCCEnable[k],
>+							mode_lib->vba.UrgentLatency,
>+							mode_lib->vba.ExtraLatency,
>+							mode_lib->vba.TimeCalc,
>+							locals->PDEAndMetaPTEBytesPerFrame[k],
>+							locals->MetaRowBytes[k],
>+							locals->DPTEBytesPerRow[k],
>+							locals->PrefetchLinesY[k],
>+							locals->SwathWidthYThisState[k],
>+							locals->BytePerPixelInDETY[k],
>+							locals->PrefillY[k],
>+							locals->MaxNumSwY[k],
>+							locals->PrefetchLinesC[k],
>+							locals->BytePerPixelInDETC[k],
>+							locals->PrefillC[k],
>+							locals->MaxNumSwC[k],
>+							locals->SwathHeightYThisState[k],
>+							locals->SwathHeightCThisState[k],
>+							mode_lib->vba.TWait,
>+							mode_lib->vba.XFCEnabled[k],
>+							mode_lib->vba.XFCRemoteSurfaceFlipDelay,
>+							mode_lib->vba.ProgressiveToInterlaceUnitInOPP,
>+							&locals->dst_x_after_scaler,
>+							&locals->dst_y_after_scaler,
>+							&locals->LineTimesForPrefetch[k],
>+							&locals->PrefetchBW[k],
>+							&locals->LinesForMetaPTE[k],
>+							&locals->LinesForMetaAndDPTERow[k],
>+							&locals->VRatioPreY[i][j][k],
>+							&locals->VRatioPreC[i][j][k],
>+							&locals->RequiredPrefetchPixelDataBWLuma[i][j][k],
>+							&locals->RequiredPrefetchPixelDataBWChroma[i][j][k],
>+							&locals->VStartupRequiredWhenNotEnoughTimeForDynamicMetadata,
>+							&locals->Tno_bw[k],
>+							&locals->prefetch_vmrow_bw[k],
>+							locals->swath_width_luma_ub,
>+							locals->swath_width_chroma_ub,
>+							&mode_lib->vba.VUpdateOffsetPix[k],
>+							&mode_lib->vba.VUpdateWidthPix[k],
>+							&mode_lib->vba.VReadyOffsetPix[k]);
>+				}
>+				mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = 0.0;
>+				mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0;
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					uint m;
>+
>+					locals->cursor_bw[k] = 0;
>+					locals->cursor_bw_pre[k] = 0;
>+					for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
>+						locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m]
>+							/ 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k];
>+						locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m]
>+							/ 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPreY[i][j][k];
>+					}
>+
>+					CalculateUrgentBurstFactor(
>+							mode_lib->vba.DETBufferSizeInKByte,
>+							locals->SwathHeightYThisState[k],
>+							locals->SwathHeightCThisState[k],
>+							locals->SwathWidthYThisState[k],
>+							mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
>+							mode_lib->vba.UrgentLatency,
>+							mode_lib->vba.CursorBufferSize,
>+							mode_lib->vba.CursorWidth[k][0] + mode_lib->vba.CursorWidth[k][1],
>+							dml_max(mode_lib->vba.CursorBPP[k][0], mode_lib->vba.CursorBPP[k][1]),
>+							mode_lib->vba.VRatio[k],
>+							locals->VRatioPreY[i][j][k],
>+							locals->VRatioPreC[i][j][k],
>+							locals->BytePerPixelInDETY[k],
>+							locals->BytePerPixelInDETC[k],
>+							&locals->UrgentBurstFactorCursor[k],
>+							&locals->UrgentBurstFactorCursorPre[k],
>+							&locals->UrgentBurstFactorLuma[k],
>+							&locals->UrgentBurstFactorLumaPre[k],
>+							&locals->UrgentBurstFactorChroma[k],
>+							&locals->UrgentBurstFactorChromaPre[k],
>+							&locals->NotEnoughUrgentLatencyHiding,
>+							&locals->NotEnoughUrgentLatencyHidingPre);
>+
>+					if (mode_lib->vba.UseUrgentBurstBandwidth == false) {
>+						locals->UrgentBurstFactorCursor[k] = 1;
>+						locals->UrgentBurstFactorCursorPre[k] = 1;
>+						locals->UrgentBurstFactorLuma[k] = 1;
>+						locals->UrgentBurstFactorLumaPre[k] = 1;
>+						locals->UrgentBurstFactorChroma[k] = 1;
>+						locals->UrgentBurstFactorChromaPre[k] = 1;
>+					}
>+
>+					mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = mode_lib->vba.MaximumReadBandwidthWithoutPrefetch
>+						+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k] + locals->ReadBandwidthLuma[k]
>+						* locals->UrgentBurstFactorLuma[k] + locals->ReadBandwidthChroma[k]
>+						* locals->UrgentBurstFactorChroma[k] + locals->meta_row_bw[k] + locals->dpte_row_bw[k];
>+					mode_lib->vba.MaximumReadBandwidthWithPrefetch = mode_lib->vba.MaximumReadBandwidthWithPrefetch
>+						+ dml_max3(locals->prefetch_vmrow_bw[k],
>+						locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k] + locals->ReadBandwidthChroma[k]
>+						* locals->UrgentBurstFactorChroma[k] + locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k]
>+						+ locals->meta_row_bw[k] + locals->dpte_row_bw[k],
>+						locals->RequiredPrefetchPixelDataBWLuma[i][j][k] * locals->UrgentBurstFactorLumaPre[k]
>+						+ locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k]
>+						+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
>+				}
>+				locals->BandwidthWithoutPrefetchSupported[i] = true;
>+				if (mode_lib->vba.MaximumReadBandwidthWithoutPrefetch > locals->ReturnBWPerState[i]
>+						|| locals->NotEnoughUrgentLatencyHiding == 1) {
>+					locals->BandwidthWithoutPrefetchSupported[i] = false;
>+				}
>+
>+				locals->PrefetchSupported[i][j] = true;
>+				if (mode_lib->vba.MaximumReadBandwidthWithPrefetch > locals->ReturnBWPerState[i]
>+						|| locals->NotEnoughUrgentLatencyHiding == 1
>+						|| locals->NotEnoughUrgentLatencyHidingPre == 1) {
>+					locals->PrefetchSupported[i][j] = false;
>+				}
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					if (locals->LineTimesForPrefetch[k] < 2.0
>+							|| locals->LinesForMetaPTE[k] >= 32.0
>+							|| locals->LinesForMetaAndDPTERow[k] >= 16.0
>+							|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
>+						locals->PrefetchSupported[i][j] = false;
>+					}
>+				}
>+				locals->VRatioInPrefetchSupported[i][j] = true;
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					if (locals->VRatioPreY[i][j][k] > 4.0
>+							|| locals->VRatioPreC[i][j][k] > 4.0
>+							|| mode_lib->vba.IsErrorResult[i][j][k] == true) {
>+						locals->VRatioInPrefetchSupported[i][j] = false;
>+					}
>+				}
>+				mode_lib->vba.AnyLinesForVMOrRowTooLarge = false;
>+				for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+					if (locals->LinesForMetaAndDPTERow[k] >= 16 || locals->LinesForMetaPTE[k] >= 32) {
>+						mode_lib->vba.AnyLinesForVMOrRowTooLarge = true;
>+					}
>+				}
>+
>+				if (mode_lib->vba.MaxVStartup <= 13 || mode_lib->vba.AnyLinesForVMOrRowTooLarge == false) {
>+					mode_lib->vba.NextMaxVStartup = mode_lib->vba.MaxMaxVStartup;
>+					mode_lib->vba.NextPrefetchMode = mode_lib->vba.NextPrefetchMode + 1;
>+				} else {
>+					mode_lib->vba.NextMaxVStartup = mode_lib->vba.NextMaxVStartup - 1;
>+				}
>+			} while ((locals->PrefetchSupported[i][j] != true || locals->VRatioInPrefetchSupported[i][j] != true)
>+					&& (mode_lib->vba.NextMaxVStartup != mode_lib->vba.MaxMaxVStartup
>+						|| mode_lib->vba.NextPrefetchMode < mode_lib->vba.MaxPrefetchMode));
>+
>+			if (locals->PrefetchSupported[i][j] == true && locals->VRatioInPrefetchSupported[i][j] == true) {
>+				mode_lib->vba.BandwidthAvailableForImmediateFlip = locals->ReturnBWPerState[i];
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					mode_lib->vba.BandwidthAvailableForImmediateFlip = mode_lib->vba.BandwidthAvailableForImmediateFlip
>+						- dml_max(locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
>+							+ locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k]
>+							+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
>+							locals->RequiredPrefetchPixelDataBWLuma[i][j][k] * locals->UrgentBurstFactorLumaPre[k]
>+							+ locals->RequiredPrefetchPixelDataBWChroma[i][j][k] * locals->UrgentBurstFactorChromaPre[k]
>+							+ locals->cursor_bw_pre[k] * locals->UrgentBurstFactorCursorPre[k]);
>+				}
>+				mode_lib->vba.TotImmediateFlipBytes = 0.0;
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					mode_lib->vba.TotImmediateFlipBytes = mode_lib->vba.TotImmediateFlipBytes
>+						+ locals->PDEAndMetaPTEBytesPerFrame[k] + locals->MetaRowBytes[k] + locals->DPTEBytesPerRow[k];
>+				}
>+
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					CalculateFlipSchedule(
>+							mode_lib,
>+							mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
>+							mode_lib->vba.PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
>+							mode_lib->vba.ExtraLatency,
>+							mode_lib->vba.UrgentLatency,
>+							mode_lib->vba.GPUVMMaxPageTableLevels,
>+							mode_lib->vba.HostVMEnable,
>+							mode_lib->vba.HostVMMaxPageTableLevels,
>+							mode_lib->vba.HostVMCachedPageTableLevels,
>+							mode_lib->vba.GPUVMEnable,
>+							locals->PDEAndMetaPTEBytesPerFrame[k],
>+							locals->MetaRowBytes[k],
>+							locals->DPTEBytesPerRow[k],
>+							mode_lib->vba.BandwidthAvailableForImmediateFlip,
>+							mode_lib->vba.TotImmediateFlipBytes,
>+							mode_lib->vba.SourcePixelFormat[k],
>+							mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k],
>+							mode_lib->vba.VRatio[k],
>+							locals->Tno_bw[k],
>+							mode_lib->vba.DCCEnable[k],
>+							locals->dpte_row_height[k],
>+							locals->meta_row_height[k],
>+							locals->dpte_row_height_chroma[k],
>+							locals->meta_row_height_chroma[k],
>+							&locals->DestinationLinesToRequestVMInImmediateFlip[k],
>+							&locals->DestinationLinesToRequestRowInImmediateFlip[k],
>+							&locals->final_flip_bw[k],
>+							&locals->ImmediateFlipSupportedForPipe[k]);
>+				}
>+				mode_lib->vba.total_dcn_read_bw_with_flip = 0.0;
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					mode_lib->vba.total_dcn_read_bw_with_flip = mode_lib->vba.total_dcn_read_bw_with_flip + dml_max3(
>+						locals->prefetch_vmrow_bw[k],
>+						locals->final_flip_bw[k] +  locals->ReadBandwidthLuma[k] * locals->UrgentBurstFactorLuma[k]
>+						+ locals->ReadBandwidthChroma[k] * locals->UrgentBurstFactorChroma[k]
>+						+ locals->cursor_bw[k] * locals->UrgentBurstFactorCursor[k],
>+						locals->final_flip_bw[k] + locals->RequiredPrefetchPixelDataBWLuma[i][j][k]
>+						* locals->UrgentBurstFactorLumaPre[k] + locals->RequiredPrefetchPixelDataBWChroma[i][j][k]
>+						* locals->UrgentBurstFactorChromaPre[k] + locals->cursor_bw_pre[k]
>+						* locals->UrgentBurstFactorCursorPre[k]);
>+				}
>+				locals->ImmediateFlipSupportedForState[i][j] = true;
>+				if (mode_lib->vba.total_dcn_read_bw_with_flip
>+						> locals->ReturnBWPerState[i]) {
>+					locals->ImmediateFlipSupportedForState[i][j] = false;
>+				}
>+				for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+					if (locals->ImmediateFlipSupportedForPipe[k] == false) {
>+						locals->ImmediateFlipSupportedForState[i][j] = false;
>+					}
>+				}
>+			} else {
>+				locals->ImmediateFlipSupportedForState[i][j] = false;
>+			}
>+			mode_lib->vba.UrgentOutOfOrderReturnPerChannel = dml_max3(
>+					mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelDataOnly,
>+					mode_lib->vba.UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
>+					mode_lib->vba.UrgentOutOfOrderReturnPerChannelVMDataOnly);
>+			CalculateWatermarksAndDRAMSpeedChangeSupport(
>+					mode_lib,
>+					mode_lib->vba.PrefetchMode[i][j],
>+					mode_lib->vba.NumberOfActivePlanes,
>+					mode_lib->vba.MaxLineBufferLines,
>+					mode_lib->vba.LineBufferSize,
>+					mode_lib->vba.DPPOutputBufferPixels,
>+					mode_lib->vba.DETBufferSizeInKByte,
>+					mode_lib->vba.WritebackInterfaceLumaBufferSize,
>+					mode_lib->vba.WritebackInterfaceChromaBufferSize,
>+					mode_lib->vba.DCFCLKPerState[i],
>+					mode_lib->vba.UrgentOutOfOrderReturnPerChannel * mode_lib->vba.NumberOfChannels,
>+					locals->ReturnBWPerState[i],
>+					mode_lib->vba.GPUVMEnable,
>+					locals->dpte_group_bytes,
>+					mode_lib->vba.MetaChunkSize,
>+					mode_lib->vba.UrgentLatency,
>+					mode_lib->vba.ExtraLatency,
>+					mode_lib->vba.WritebackLatency,
>+					mode_lib->vba.WritebackChunkSize,
>+					mode_lib->vba.SOCCLKPerState[i],
>+					mode_lib->vba.DRAMClockChangeLatency,
>+					mode_lib->vba.SRExitTime,
>+					mode_lib->vba.SREnterPlusExitTime,
>+					mode_lib->vba.ProjectedDCFCLKDeepSleep,
>+					locals->NoOfDPPThisState,
>+					mode_lib->vba.DCCEnable,
>+					locals->RequiredDPPCLKThisState,
>+					locals->SwathWidthYSingleDPP,
>+					locals->SwathHeightYThisState,
>+					locals->ReadBandwidthLuma,
>+					locals->SwathHeightCThisState,
>+					locals->ReadBandwidthChroma,
>+					mode_lib->vba.LBBitPerPixel,
>+					locals->SwathWidthYThisState,
>+					mode_lib->vba.HRatio,
>+					mode_lib->vba.vtaps,
>+					mode_lib->vba.VTAPsChroma,
>+					mode_lib->vba.VRatio,
>+					mode_lib->vba.HTotal,
>+					mode_lib->vba.PixelClock,
>+					mode_lib->vba.BlendingAndTiming,
>+					locals->BytePerPixelInDETY,
>+					locals->BytePerPixelInDETC,
>+					mode_lib->vba.WritebackEnable,
>+					mode_lib->vba.WritebackPixelFormat,
>+					mode_lib->vba.WritebackDestinationWidth,
>+					mode_lib->vba.WritebackDestinationHeight,
>+					mode_lib->vba.WritebackSourceHeight,
>+					&locals->DRAMClockChangeSupport[i][j],
>+					&mode_lib->vba.UrgentWatermark,
>+					&mode_lib->vba.WritebackUrgentWatermark,
>+					&mode_lib->vba.DRAMClockChangeWatermark,
>+					&mode_lib->vba.WritebackDRAMClockChangeWatermark,
>+					&mode_lib->vba.StutterExitWatermark,
>+					&mode_lib->vba.StutterEnterPlusExitWatermark,
>+					&mode_lib->vba.MinActiveDRAMClockChangeLatencySupported);
>+			}
>+		}
>+
>+		/*Vertical Active BW support*/
>+		{
>+			double MaxTotalVActiveRDBandwidth = 0.0;
>+			for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
>+				MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + locals->ReadBandwidth[k];
>+		}
>+		for (i = 0; i <= mode_lib->vba.soc.num_states; ++i) {
>+			locals->MaxTotalVerticalActiveAvailableBandwidth[i] = dml_min(
>+				locals->IdealSDPPortBandwidthPerState[i] *
>+				mode_lib->vba.MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation
>+				/ 100.0, mode_lib->vba.DRAMSpeedPerState[i] *
>+				mode_lib->vba.NumberOfChannels *
>+				mode_lib->vba.DRAMChannelWidth *
>+				mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation
>+				/ 100.0);
>+
>+			if (MaxTotalVActiveRDBandwidth <= locals->MaxTotalVerticalActiveAvailableBandwidth[i]) {
>+				locals->TotalVerticalActiveBandwidthSupport[i] = true;
>+			} else {
>+				locals->TotalVerticalActiveBandwidthSupport[i] = false;
>+			}
>+		}
>+	}
>+
>+	/*PTE Buffer Size Check*/
>+
>+	for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
>+		for (j = 0; j < 2; j++) {
>+			locals->PTEBufferSizeNotExceeded[i][j] = true;
>+			for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+				if (locals->PTEBufferSizeNotExceededY[i][j][k] == false
>+						|| locals->PTEBufferSizeNotExceededC[i][j][k] == false) {
>+					locals->PTEBufferSizeNotExceeded[i][j] = false;
>+				}
>+			}
>+		}
>+	}
>+	/*Cursor Support Check*/
>+
>+	mode_lib->vba.CursorSupport = true;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.CursorWidth[k][0] > 0.0) {
>+			for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) {
>+				if (mode_lib->vba.CursorBPP[k][m] == 64 && mode_lib->vba.Cursor64BppSupport == false) {
>+					mode_lib->vba.CursorSupport = false;
>+				}
>+			}
>+		}
>+	}
>+	/*Valid Pitch Check*/
>+
>+	mode_lib->vba.PitchSupport = true;
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		locals->AlignedYPitch[k] = dml_ceil(
>+				dml_max(mode_lib->vba.PitchY[k], mode_lib->vba.ViewportWidth[k]),
>+				locals->MacroTileWidthY[k]);
>+		if (locals->AlignedYPitch[k] > mode_lib->vba.PitchY[k]) {
>+			mode_lib->vba.PitchSupport = false;
>+		}
>+		if (mode_lib->vba.DCCEnable[k] == true) {
>+			locals->AlignedDCCMetaPitch[k] = dml_ceil(
>+					dml_max(
>+							mode_lib->vba.DCCMetaPitchY[k],
>+							mode_lib->vba.ViewportWidth[k]),
>+					64.0 * locals->Read256BlockWidthY[k]);
>+		} else {
>+			locals->AlignedDCCMetaPitch[k] = mode_lib->vba.DCCMetaPitchY[k];
>+		}
>+		if (locals->AlignedDCCMetaPitch[k] > mode_lib->vba.DCCMetaPitchY[k]) {
>+			mode_lib->vba.PitchSupport = false;
>+		}
>+		if (mode_lib->vba.SourcePixelFormat[k] != dm_444_64
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_32
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_444_16
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_16
>+				&& mode_lib->vba.SourcePixelFormat[k] != dm_mono_8) {
>+			locals->AlignedCPitch[k] = dml_ceil(
>+					dml_max(
>+							mode_lib->vba.PitchC[k],
>+							mode_lib->vba.ViewportWidth[k] / 2.0),
>+					locals->MacroTileWidthC[k]);
>+		} else {
>+			locals->AlignedCPitch[k] = mode_lib->vba.PitchC[k];
>+		}
>+		if (locals->AlignedCPitch[k] > mode_lib->vba.PitchC[k]) {
>+			mode_lib->vba.PitchSupport = false;
>+		}
>+	}
>+	/*Mode Support, Voltage State and SOC Configuration*/
>+
>+	for (i = mode_lib->vba.soc.num_states; i >= 0; i--) {
>+		for (j = 0; j < 2; j++) {
>+			enum dm_validation_status status = DML_VALIDATION_OK;
>+
>+			if (mode_lib->vba.ScaleRatioAndTapsSupport != true) {
>+				status = DML_FAIL_SCALE_RATIO_TAP;
>+			} else if (mode_lib->vba.SourceFormatPixelAndScanSupport != true) {
>+				status = DML_FAIL_SOURCE_PIXEL_FORMAT;
>+			} else if (locals->ViewportSizeSupport[i] != true) {
>+				status = DML_FAIL_VIEWPORT_SIZE;
>+			} else if (locals->DIOSupport[i] != true) {
>+				status = DML_FAIL_DIO_SUPPORT;
>+			} else if (locals->NotEnoughDSCUnits[i] != false) {
>+				status = DML_FAIL_NOT_ENOUGH_DSC;
>+			} else if (locals->DSCCLKRequiredMoreThanSupported[i] != false) {
>+				status = DML_FAIL_DSC_CLK_REQUIRED;
>+			} else if (locals->ROBSupport[i] != true) {
>+				status = DML_FAIL_REORDERING_BUFFER;
>+			} else if (locals->DISPCLK_DPPCLK_Support[i][j] != true) {
>+				status = DML_FAIL_DISPCLK_DPPCLK;
>+			} else if (locals->TotalAvailablePipesSupport[i][j] != true) {
>+				status = DML_FAIL_TOTAL_AVAILABLE_PIPES;
>+			} else if (mode_lib->vba.NumberOfOTGSupport != true) {
>+				status = DML_FAIL_NUM_OTG;
>+			} else if (mode_lib->vba.WritebackModeSupport != true) {
>+				status = DML_FAIL_WRITEBACK_MODE;
>+			} else if (mode_lib->vba.WritebackLatencySupport != true) {
>+				status = DML_FAIL_WRITEBACK_LATENCY;
>+			} else if (mode_lib->vba.WritebackScaleRatioAndTapsSupport != true) {
>+				status = DML_FAIL_WRITEBACK_SCALE_RATIO_TAP;
>+			} else if (mode_lib->vba.CursorSupport != true) {
>+				status = DML_FAIL_CURSOR_SUPPORT;
>+			} else if (mode_lib->vba.PitchSupport != true) {
>+				status = DML_FAIL_PITCH_SUPPORT;
>+			} else if (locals->TotalVerticalActiveBandwidthSupport[i] != true) {
>+				status = DML_FAIL_TOTAL_V_ACTIVE_BW;
>+			} else if (locals->PTEBufferSizeNotExceeded[i][j] != true) {
>+				status = DML_FAIL_PTE_BUFFER_SIZE;
>+			} else if (mode_lib->vba.NonsupportedDSCInputBPC != false) {
>+				status = DML_FAIL_DSC_INPUT_BPC;
>+			} else if ((mode_lib->vba.HostVMEnable != false
>+					&& locals->ImmediateFlipSupportedForState[i][j] != true)) {
>+				status = DML_FAIL_HOST_VM_IMMEDIATE_FLIP;
>+			} else if (locals->PrefetchSupported[i][j] != true) {
>+				status = DML_FAIL_PREFETCH_SUPPORT;
>+			} else if (locals->VRatioInPrefetchSupported[i][j] != true) {
>+				status = DML_FAIL_V_RATIO_PREFETCH;
>+			}
>+
>+			if (status == DML_VALIDATION_OK) {
>+				locals->ModeSupport[i][j] = true;
>+			} else {
>+				locals->ModeSupport[i][j] = false;
>+			}
>+			locals->ValidationStatus[i] = status;
>+		}
>+	}
>+	{
>+		unsigned int MaximumMPCCombine = 0;
>+		mode_lib->vba.VoltageLevel = mode_lib->vba.soc.num_states + 1;
>+		for (i = mode_lib->vba.VoltageOverrideLevel; i <= mode_lib->vba.soc.num_states; i++) {
>+			if (locals->ModeSupport[i][0] == true || locals->ModeSupport[i][1] == true) {
>+				mode_lib->vba.VoltageLevel = i;
>+				if (locals->ModeSupport[i][1] == true && (locals->ModeSupport[i][0] == false
>+						|| mode_lib->vba.WhenToDoMPCCombine == dm_mpc_always_when_possible
>+						|| (mode_lib->vba.WhenToDoMPCCombine == dm_mpc_reduce_voltage_and_clocks
>+							&& ((locals->DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vactive
>+								&& locals->DRAMClockChangeSupport[i][0] != dm_dram_clock_change_vactive)
>+							|| (locals->DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vblank
>+								&& locals->DRAMClockChangeSupport[i][0] == dm_dram_clock_change_unsupported))))) {
>+					MaximumMPCCombine = 1;
>+				} else {
>+					MaximumMPCCombine = 0;
>+				}
>+				break;
>+			}
>+		}
>+		mode_lib->vba.ImmediateFlipSupport =
>+			locals->ImmediateFlipSupportedForState[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
>+		for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+			mode_lib->vba.DPPPerPlane[k] = locals->NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
>+			locals->DPPCLK[k] = locals->RequiredDPPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
>+		}
>+		mode_lib->vba.DISPCLK = locals->RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine];
>+		mode_lib->vba.maxMpcComb = MaximumMPCCombine;
>+	}
>+	mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKPerState[mode_lib->vba.VoltageLevel];
>+	mode_lib->vba.DRAMSpeed = mode_lib->vba.DRAMSpeedPerState[mode_lib->vba.VoltageLevel];
>+	mode_lib->vba.FabricClock = mode_lib->vba.FabricClockPerState[mode_lib->vba.VoltageLevel];
>+	mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel];
>+	mode_lib->vba.ReturnBW = locals->ReturnBWPerState[mode_lib->vba.VoltageLevel];
>+	for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) {
>+		if (mode_lib->vba.BlendingAndTiming[k] == k) {
>+			mode_lib->vba.ODMCombineEnabled[k] =
>+					locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
>+		} else {
>+			mode_lib->vba.ODMCombineEnabled[k] = 0;
>+		}
>+		mode_lib->vba.DSCEnabled[k] =
>+				locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
>+		mode_lib->vba.OutputBpp[k] =
>+				locals->OutputBppPerState[mode_lib->vba.VoltageLevel][k];
>+	}
>+}
>+
>+static void CalculateWatermarksAndDRAMSpeedChangeSupport(
>+		struct display_mode_lib *mode_lib,
>+		unsigned int PrefetchMode,
>+		unsigned int NumberOfActivePlanes,
>+		unsigned int MaxLineBufferLines,
>+		unsigned int LineBufferSize,
>+		unsigned int DPPOutputBufferPixels,
>+		double DETBufferSizeInKByte,
>+		unsigned int WritebackInterfaceLumaBufferSize,
>+		unsigned int WritebackInterfaceChromaBufferSize,
>+		double DCFCLK,
>+		double UrgentOutOfOrderReturn,
>+		double ReturnBW,
>+		bool GPUVMEnable,
>+		long dpte_group_bytes[],
>+		unsigned int MetaChunkSize,
>+		double UrgentLatency,
>+		double ExtraLatency,
>+		double WritebackLatency,
>+		double WritebackChunkSize,
>+		double SOCCLK,
>+		double DRAMClockChangeLatency,
>+		double SRExitTime,
>+		double SREnterPlusExitTime,
>+		double DCFCLKDeepSleep,
>+		int DPPPerPlane[],
>+		bool DCCEnable[],
>+		double DPPCLK[],
>+		unsigned int SwathWidthSingleDPPY[],
>+		unsigned int SwathHeightY[],
>+		double ReadBandwidthPlaneLuma[],
>+		unsigned int SwathHeightC[],
>+		double ReadBandwidthPlaneChroma[],
>+		unsigned int LBBitPerPixel[],
>+		unsigned int SwathWidthY[],
>+		double HRatio[],
>+		unsigned int vtaps[],
>+		unsigned int VTAPsChroma[],
>+		double VRatio[],
>+		unsigned int HTotal[],
>+		double PixelClock[],
>+		unsigned int BlendingAndTiming[],
>+		double BytePerPixelDETY[],
>+		double BytePerPixelDETC[],
>+		bool WritebackEnable[],
>+		enum source_format_class WritebackPixelFormat[],
>+		double WritebackDestinationWidth[],
>+		double WritebackDestinationHeight[],
>+		double WritebackSourceHeight[],
>+		enum clock_change_support *DRAMClockChangeSupport,
>+		double *UrgentWatermark,
>+		double *WritebackUrgentWatermark,
>+		double *DRAMClockChangeWatermark,
>+		double *WritebackDRAMClockChangeWatermark,
>+		double *StutterExitWatermark,
>+		double *StutterEnterPlusExitWatermark,
>+		double *MinActiveDRAMClockChangeLatencySupported)
>+{
>+	double EffectiveLBLatencyHidingY;
>+	double EffectiveLBLatencyHidingC;
>+	double DPPOutputBufferLinesY;
>+	double DPPOutputBufferLinesC;
>+	double DETBufferSizeY;
>+	double DETBufferSizeC;
>+	double LinesInDETY[DC__NUM_DPP__MAX];
>+	double LinesInDETC;
>+	unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
>+	unsigned int LinesInDETCRoundedDownToSwath;
>+	double FullDETBufferingTimeY[DC__NUM_DPP__MAX];
>+	double FullDETBufferingTimeC;
>+	double ActiveDRAMClockChangeLatencyMarginY;
>+	double ActiveDRAMClockChangeLatencyMarginC;
>+	double WritebackDRAMClockChangeLatencyMargin;
>+	double PlaneWithMinActiveDRAMClockChangeMargin;
>+	double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank;
>+	double FullDETBufferingTimeYStutterCriticalPlane = 0;
>+	double TimeToFinishSwathTransferStutterCriticalPlane = 0;
>+	uint k, j;
>+
>+	mode_lib->vba.TotalActiveDPP = 0;
>+	mode_lib->vba.TotalDCCActiveDPP = 0;
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + DPPPerPlane[k];
>+		if (DCCEnable[k] == true) {
>+			mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP + DPPPerPlane[k];
>+		}
>+	}
>+
>+	mode_lib->vba.TotalDataReadBandwidth = 0;
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		mode_lib->vba.TotalDataReadBandwidth = mode_lib->vba.TotalDataReadBandwidth
>+				+ ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k];
>+	}
>+
>+	*UrgentWatermark = UrgentLatency + ExtraLatency;
>+
>+	*DRAMClockChangeWatermark = DRAMClockChangeLatency + *UrgentWatermark;
>+
>+	mode_lib->vba.TotalActiveWriteback = 0;
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		if (WritebackEnable[k] == true) {
>+			mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + 1;
>+		}
>+	}
>+
>+	if (mode_lib->vba.TotalActiveWriteback <= 1) {
>+		*WritebackUrgentWatermark = WritebackLatency;
>+	} else {
>+		*WritebackUrgentWatermark = WritebackLatency
>+				+ WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
>+	}
>+
>+	if (mode_lib->vba.TotalActiveWriteback <= 1) {
>+		*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency;
>+	} else {
>+		*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency
>+				+ WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
>+	}
>+
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+
>+		mode_lib->vba.LBLatencyHidingSourceLinesY = dml_min((double) MaxLineBufferLines,
>+			dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1))
>+				- (vtaps[k] - 1);
>+
>+		mode_lib->vba.LBLatencyHidingSourceLinesC = dml_min((double) MaxLineBufferLines,
>+			dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / 2 / dml_max(HRatio[k] / 2, 1.0)), 1))
>+				- (VTAPsChroma[k] - 1);
>+
>+		EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / VRatio[k]
>+				* (HTotal[k] / PixelClock[k]);
>+
>+		EffectiveLBLatencyHidingC = mode_lib->vba.LBLatencyHidingSourceLinesC
>+				/ (VRatio[k] / 2) * (HTotal[k] / PixelClock[k]);
>+
>+		if (SwathWidthY[k] > 2 * DPPOutputBufferPixels) {
>+			DPPOutputBufferLinesY = (double) DPPOutputBufferPixels / SwathWidthY[k];
>+		} else if (SwathWidthY[k] > DPPOutputBufferPixels) {
>+			DPPOutputBufferLinesY = 0.5;
>+		} else {
>+			DPPOutputBufferLinesY = 1;
>+		}
>+
>+		if (SwathWidthY[k] / 2.0 > 2 * DPPOutputBufferPixels) {
>+			DPPOutputBufferLinesC = (double) DPPOutputBufferPixels
>+					/ (SwathWidthY[k] / 2.0);
>+		} else if (SwathWidthY[k] / 2.0 > DPPOutputBufferPixels) {
>+			DPPOutputBufferLinesC = 0.5;
>+		} else {
>+			DPPOutputBufferLinesC = 1;
>+		}
>+
>+		CalculateDETBufferSize(
>+				DETBufferSizeInKByte,
>+				SwathHeightY[k],
>+				SwathHeightC[k],
>+				&DETBufferSizeY,
>+				&DETBufferSizeC);
>+
>+		LinesInDETY[k] = DETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
>+		LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
>+		FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k]
>+				* (HTotal[k] / PixelClock[k]) / VRatio[k];
>+		if (BytePerPixelDETC[k] > 0) {
>+			LinesInDETC = DETBufferSizeC / BytePerPixelDETC[k] / (SwathWidthY[k] / 2.0);
>+			LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
>+			FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath
>+					* (HTotal[k] / PixelClock[k]) / (VRatio[k] / 2);
>+		} else {
>+			LinesInDETC = 0;
>+			FullDETBufferingTimeC = 999999;
>+		}
>+
>+		ActiveDRAMClockChangeLatencyMarginY = HTotal[k] / PixelClock[k]
>+				* DPPOutputBufferLinesY + EffectiveLBLatencyHidingY
>+				+ FullDETBufferingTimeY[k] - *DRAMClockChangeWatermark;
>+
>+		if (NumberOfActivePlanes > 1) {
>+			ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY
>+				- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k];
>+		}
>+
>+		if (BytePerPixelDETC[k] > 0) {
>+			ActiveDRAMClockChangeLatencyMarginC = HTotal[k] / PixelClock[k]
>+					* DPPOutputBufferLinesC + EffectiveLBLatencyHidingC
>+					+ FullDETBufferingTimeC - *DRAMClockChangeWatermark;
>+			if (NumberOfActivePlanes > 1) {
>+				ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC
>+					- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / (VRatio[k] / 2);
>+			}
>+			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
>+					ActiveDRAMClockChangeLatencyMarginY,
>+					ActiveDRAMClockChangeLatencyMarginC);
>+		} else {
>+			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
>+		}
>+
>+		if (WritebackEnable[k] == true) {
>+			if (WritebackPixelFormat[k] == dm_444_32) {
>+				WritebackDRAMClockChangeLatencyMargin = (WritebackInterfaceLumaBufferSize
>+					+ WritebackInterfaceChromaBufferSize) / (WritebackDestinationWidth[k]
>+					* WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k]
>+					/ PixelClock[k]) * 4) - *WritebackDRAMClockChangeWatermark;
>+			} else {
>+				WritebackDRAMClockChangeLatencyMargin = dml_min(
>+						WritebackInterfaceLumaBufferSize * 8.0 / 10,
>+						2 * WritebackInterfaceChromaBufferSize * 8.0 / 10) / (WritebackDestinationWidth[k]
>+							* WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]))
>+						- *WritebackDRAMClockChangeWatermark;
>+			}
>+			mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(
>+					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k],
>+					WritebackDRAMClockChangeLatencyMargin);
>+		}
>+	}
>+
>+	mode_lib->vba.MinActiveDRAMClockChangeMargin = 999999;
>+	PlaneWithMinActiveDRAMClockChangeMargin = 0;
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
>+				< mode_lib->vba.MinActiveDRAMClockChangeMargin) {
>+			mode_lib->vba.MinActiveDRAMClockChangeMargin =
>+					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
>+			if (BlendingAndTiming[k] == k) {
>+				PlaneWithMinActiveDRAMClockChangeMargin = k;
>+			} else {
>+				for (j = 0; j < NumberOfActivePlanes; ++j) {
>+					if (BlendingAndTiming[k] == j) {
>+						PlaneWithMinActiveDRAMClockChangeMargin = j;
>+					}
>+				}
>+			}
>+		}
>+	}
>+
>+	*MinActiveDRAMClockChangeLatencySupported = mode_lib->vba.MinActiveDRAMClockChangeMargin + DRAMClockChangeLatency;
>+
>+	SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999;
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k))
>+				&& !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
>+				&& mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]
>+						< SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
>+			SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank =
>+					mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k];
>+		}
>+	}
>+
>+	mode_lib->vba.TotalNumberOfActiveOTG = 0;
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		if (BlendingAndTiming[k] == k) {
>+			mode_lib->vba.TotalNumberOfActiveOTG = mode_lib->vba.TotalNumberOfActiveOTG + 1;
>+		}
>+	}
>+
>+	if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) {
>+		*DRAMClockChangeSupport = dm_dram_clock_change_vactive;
>+	} else if (((mode_lib->vba.SynchronizedVBlank == true
>+			|| mode_lib->vba.TotalNumberOfActiveOTG == 1
>+			|| SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0)
>+			&& PrefetchMode == 0)) {
>+		*DRAMClockChangeSupport = dm_dram_clock_change_vblank;
>+	} else {
>+		*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
>+	}
>+
>+	FullDETBufferingTimeYStutterCriticalPlane = FullDETBufferingTimeY[0];
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		if (FullDETBufferingTimeY[k] <= FullDETBufferingTimeYStutterCriticalPlane) {
>+			TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k]
>+					- (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k]))
>+					* (HTotal[k] / PixelClock[k]) / VRatio[k];
>+		}
>+	}
>+
>+	*StutterExitWatermark = SRExitTime + mode_lib->vba.LastPixelOfLineExtraWatermark
>+			+ ExtraLatency + 10 / DCFCLKDeepSleep;
>+	*StutterEnterPlusExitWatermark = dml_max(
>+			SREnterPlusExitTime + mode_lib->vba.LastPixelOfLineExtraWatermark
>+					+ ExtraLatency + 10 / DCFCLKDeepSleep,
>+			TimeToFinishSwathTransferStutterCriticalPlane);
>+
>+}
>+
>+static void CalculateDCFCLKDeepSleep(
>+		struct display_mode_lib *mode_lib,
>+		unsigned int NumberOfActivePlanes,
>+		double BytePerPixelDETY[],
>+		double BytePerPixelDETC[],
>+		double VRatio[],
>+		unsigned int SwathWidthY[],
>+		int DPPPerPlane[],
>+		double HRatio[],
>+		double PixelClock[],
>+		double PSCL_THROUGHPUT[],
>+		double PSCL_THROUGHPUT_CHROMA[],
>+		double DPPCLK[],
>+		double *DCFCLKDeepSleep)
>+{
>+	uint k;
>+	double DisplayPipeLineDeliveryTimeLuma;
>+	double DisplayPipeLineDeliveryTimeChroma;
>+	//double   DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
>+
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		if (VRatio[k] <= 1) {
>+			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k]
>+					/ HRatio[k] / PixelClock[k];
>+		} else {
>+			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k]
>+					/ DPPCLK[k];
>+		}
>+		if (BytePerPixelDETC[k] == 0) {
>+			DisplayPipeLineDeliveryTimeChroma = 0;
>+		} else {
>+			if (VRatio[k] / 2 <= 1) {
>+				DisplayPipeLineDeliveryTimeChroma = SwathWidthY[k] / 2.0
>+						* DPPPerPlane[k] / (HRatio[k] / 2) / PixelClock[k];
>+			} else {
>+				DisplayPipeLineDeliveryTimeChroma = SwathWidthY[k] / 2.0
>+						/ PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
>+			}
>+		}
>+
>+		if (BytePerPixelDETC[k] > 0) {
>+			mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
>+					1.1 * SwathWidthY[k] * dml_ceil(BytePerPixelDETY[k], 1)
>+							/ 32.0 / DisplayPipeLineDeliveryTimeLuma,
>+					1.1 * SwathWidthY[k] / 2.0
>+							* dml_ceil(BytePerPixelDETC[k], 2) / 32.0
>+							/ DisplayPipeLineDeliveryTimeChroma);
>+		} else {
>+			mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = 1.1 * SwathWidthY[k]
>+					* dml_ceil(BytePerPixelDETY[k], 1) / 64.0
>+					/ DisplayPipeLineDeliveryTimeLuma;
>+		}
>+		mode_lib->vba.DCFCLKDeepSleepPerPlane[k] = dml_max(
>+				mode_lib->vba.DCFCLKDeepSleepPerPlane[k],
>+				PixelClock[k] / 16);
>+
>+	}
>+
>+	*DCFCLKDeepSleep = 8;
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		*DCFCLKDeepSleep = dml_max(
>+				*DCFCLKDeepSleep,
>+				mode_lib->vba.DCFCLKDeepSleepPerPlane[k]);
>+	}
>+}
>+
>+static void CalculateDETBufferSize(
>+		double DETBufferSizeInKByte,
>+		unsigned int SwathHeightY,
>+		unsigned int SwathHeightC,
>+		double *DETBufferSizeY,
>+		double *DETBufferSizeC)
>+{
>+	if (SwathHeightC == 0) {
>+		*DETBufferSizeY = DETBufferSizeInKByte * 1024;
>+		*DETBufferSizeC = 0;
>+	} else if (SwathHeightY <= SwathHeightC) {
>+		*DETBufferSizeY = DETBufferSizeInKByte * 1024 / 2;
>+		*DETBufferSizeC = DETBufferSizeInKByte * 1024 / 2;
>+	} else {
>+		*DETBufferSizeY = DETBufferSizeInKByte * 1024 * 2 / 3;
>+		*DETBufferSizeC = DETBufferSizeInKByte * 1024 / 3;
>+	}
>+}
>+
>+static void CalculateUrgentBurstFactor(
>+		unsigned int DETBufferSizeInKByte,
>+		unsigned int SwathHeightY,
>+		unsigned int SwathHeightC,
>+		unsigned int SwathWidthY,
>+		double LineTime,
>+		double UrgentLatency,
>+		double CursorBufferSize,
>+		unsigned int CursorWidth,
>+		unsigned int CursorBPP,
>+		double VRatio,
>+		double VRatioPreY,
>+		double VRatioPreC,
>+		double BytePerPixelInDETY,
>+		double BytePerPixelInDETC,
>+		double *UrgentBurstFactorCursor,
>+		double *UrgentBurstFactorCursorPre,
>+		double *UrgentBurstFactorLuma,
>+		double *UrgentBurstFactorLumaPre,
>+		double *UrgentBurstFactorChroma,
>+		double *UrgentBurstFactorChromaPre,
>+		unsigned int *NotEnoughUrgentLatencyHiding,
>+		unsigned int *NotEnoughUrgentLatencyHidingPre)
>+{
>+	double LinesInDETLuma;
>+	double LinesInDETChroma;
>+	unsigned int LinesInCursorBuffer;
>+	double CursorBufferSizeInTime;
>+	double CursorBufferSizeInTimePre;
>+	double DETBufferSizeInTimeLuma;
>+	double DETBufferSizeInTimeLumaPre;
>+	double DETBufferSizeInTimeChroma;
>+	double DETBufferSizeInTimeChromaPre;
>+	double DETBufferSizeY;
>+	double DETBufferSizeC;
>+
>+	*NotEnoughUrgentLatencyHiding = 0;
>+	*NotEnoughUrgentLatencyHidingPre = 0;
>+
>+	if (CursorWidth > 0) {
>+		LinesInCursorBuffer = 1 << (unsigned int) dml_floor(
>+			dml_log2(CursorBufferSize * 1024.0 / (CursorWidth * CursorBPP / 8.0)), 1.0);
>+		CursorBufferSizeInTime = LinesInCursorBuffer * LineTime / VRatio;
>+		if (CursorBufferSizeInTime - UrgentLatency <= 0) {
>+			*NotEnoughUrgentLatencyHiding = 1;
>+			*UrgentBurstFactorCursor = 0;
>+		} else {
>+			*UrgentBurstFactorCursor = CursorBufferSizeInTime
>+					/ (CursorBufferSizeInTime - UrgentLatency);
>+		}
>+		if (VRatioPreY > 0) {
>+			CursorBufferSizeInTimePre = LinesInCursorBuffer * LineTime / VRatioPreY;
>+			if (CursorBufferSizeInTimePre - UrgentLatency <= 0) {
>+				*NotEnoughUrgentLatencyHidingPre = 1;
>+				*UrgentBurstFactorCursorPre = 0;
>+			} else {
>+				*UrgentBurstFactorCursorPre = CursorBufferSizeInTimePre
>+						/ (CursorBufferSizeInTimePre - UrgentLatency);
>+			}
>+		} else {
>+			*UrgentBurstFactorCursorPre = 1;
>+		}
>+	}
>+
>+	CalculateDETBufferSize(
>+			DETBufferSizeInKByte,
>+			SwathHeightY,
>+			SwathHeightC,
>+			&DETBufferSizeY,
>+			&DETBufferSizeC);
>+
>+	LinesInDETLuma = DETBufferSizeY / BytePerPixelInDETY / SwathWidthY;
>+	DETBufferSizeInTimeLuma = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime / VRatio;
>+	if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) {
>+		*NotEnoughUrgentLatencyHiding = 1;
>+		*UrgentBurstFactorLuma = 0;
>+	} else {
>+		*UrgentBurstFactorLuma = DETBufferSizeInTimeLuma
>+				/ (DETBufferSizeInTimeLuma - UrgentLatency);
>+	}
>+	if (VRatioPreY > 0) {
>+		DETBufferSizeInTimeLumaPre = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime
>+				/ VRatioPreY;
>+		if (DETBufferSizeInTimeLumaPre - UrgentLatency <= 0) {
>+			*NotEnoughUrgentLatencyHidingPre = 1;
>+			*UrgentBurstFactorLumaPre = 0;
>+		} else {
>+			*UrgentBurstFactorLumaPre = DETBufferSizeInTimeLumaPre
>+					/ (DETBufferSizeInTimeLumaPre - UrgentLatency);
>+		}
>+	} else {
>+		*UrgentBurstFactorLumaPre = 1;
>+	}
>+
>+	if (BytePerPixelInDETC > 0) {
>+		LinesInDETChroma = DETBufferSizeC / BytePerPixelInDETC / (SwathWidthY / 2);
>+		DETBufferSizeInTimeChroma = dml_floor(LinesInDETChroma, SwathHeightC) * LineTime
>+				/ (VRatio / 2);
>+		if (DETBufferSizeInTimeChroma - UrgentLatency <= 0) {
>+			*NotEnoughUrgentLatencyHiding = 1;
>+			*UrgentBurstFactorChroma = 0;
>+		} else {
>+			*UrgentBurstFactorChroma = DETBufferSizeInTimeChroma
>+					/ (DETBufferSizeInTimeChroma - UrgentLatency);
>+		}
>+		if (VRatioPreC > 0) {
>+			DETBufferSizeInTimeChromaPre = dml_floor(LinesInDETChroma, SwathHeightC)
>+					* LineTime / VRatioPreC;
>+			if (DETBufferSizeInTimeChromaPre - UrgentLatency <= 0) {
>+				*NotEnoughUrgentLatencyHidingPre = 1;
>+				*UrgentBurstFactorChromaPre = 0;
>+			} else {
>+				*UrgentBurstFactorChromaPre = DETBufferSizeInTimeChromaPre
>+						/ (DETBufferSizeInTimeChromaPre - UrgentLatency);
>+			}
>+		} else {
>+			*UrgentBurstFactorChromaPre = 1;
>+		}
>+	}
>+}
>+
>+static void CalculatePixelDeliveryTimes(
>+		unsigned int NumberOfActivePlanes,
>+		double VRatio[],
>+		double VRatioPrefetchY[],
>+		double VRatioPrefetchC[],
>+		unsigned int swath_width_luma_ub[],
>+		unsigned int swath_width_chroma_ub[],
>+		int DPPPerPlane[],
>+		double HRatio[],
>+		double PixelClock[],
>+		double PSCL_THROUGHPUT[],
>+		double PSCL_THROUGHPUT_CHROMA[],
>+		double DPPCLK[],
>+		double BytePerPixelDETC[],
>+		enum scan_direction_class SourceScan[],
>+		unsigned int BlockWidth256BytesY[],
>+		unsigned int BlockHeight256BytesY[],
>+		unsigned int BlockWidth256BytesC[],
>+		unsigned int BlockHeight256BytesC[],
>+		double DisplayPipeLineDeliveryTimeLuma[],
>+		double DisplayPipeLineDeliveryTimeChroma[],
>+		double DisplayPipeLineDeliveryTimeLumaPrefetch[],
>+		double DisplayPipeLineDeliveryTimeChromaPrefetch[],
>+		double DisplayPipeRequestDeliveryTimeLuma[],
>+		double DisplayPipeRequestDeliveryTimeChroma[],
>+		double DisplayPipeRequestDeliveryTimeLumaPrefetch[],
>+		double DisplayPipeRequestDeliveryTimeChromaPrefetch[])
>+{
>+	double req_per_swath_ub;
>+	uint k;
>+
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		if (VRatio[k] <= 1) {
>+			DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k]
>+					/ HRatio[k] / PixelClock[k];
>+		} else {
>+			DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k]
>+					/ PSCL_THROUGHPUT[k] / DPPCLK[k];
>+		}
>+
>+		if (BytePerPixelDETC[k] == 0) {
>+			DisplayPipeLineDeliveryTimeChroma[k] = 0;
>+		} else {
>+			if (VRatio[k] / 2 <= 1) {
>+				DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k]
>+						* DPPPerPlane[k] / (HRatio[k] / 2) / PixelClock[k];
>+			} else {
>+				DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k]
>+						/ PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
>+			}
>+		}
>+
>+		if (VRatioPrefetchY[k] <= 1) {
>+			DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k]
>+					* DPPPerPlane[k] / HRatio[k] / PixelClock[k];
>+		} else {
>+			DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k]
>+					/ PSCL_THROUGHPUT[k] / DPPCLK[k];
>+		}
>+
>+		if (BytePerPixelDETC[k] == 0) {
>+			DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
>+		} else {
>+			if (VRatioPrefetchC[k] <= 1) {
>+				DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
>+						swath_width_chroma_ub[k] * DPPPerPlane[k]
>+								/ (HRatio[k] / 2) / PixelClock[k];
>+			} else {
>+				DisplayPipeLineDeliveryTimeChromaPrefetch[k] =
>+						swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
>+			}
>+		}
>+	}
>+
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		if (SourceScan[k] == dm_horz) {
>+			req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
>+		} else {
>+			req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
>+		}
>+		DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k]
>+				/ req_per_swath_ub;
>+		DisplayPipeRequestDeliveryTimeLumaPrefetch[k] =
>+				DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
>+		if (BytePerPixelDETC[k] == 0) {
>+			DisplayPipeRequestDeliveryTimeChroma[k] = 0;
>+			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
>+		} else {
>+			if (SourceScan[k] == dm_horz) {
>+				req_per_swath_ub = swath_width_chroma_ub[k]
>+						/ BlockWidth256BytesC[k];
>+			} else {
>+				req_per_swath_ub = swath_width_chroma_ub[k]
>+						/ BlockHeight256BytesC[k];
>+			}
>+			DisplayPipeRequestDeliveryTimeChroma[k] =
>+					DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
>+			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] =
>+					DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
>+		}
>+	}
>+}
>+
>+static void CalculateMetaAndPTETimes(
>+		unsigned int NumberOfActivePlanes,
>+		bool GPUVMEnable,
>+		unsigned int MetaChunkSize,
>+		unsigned int MinMetaChunkSizeBytes,
>+		unsigned int GPUVMMaxPageTableLevels,
>+		unsigned int HTotal[],
>+		double VRatio[],
>+		double VRatioPrefetchY[],
>+		double VRatioPrefetchC[],
>+		double DestinationLinesToRequestRowInVBlank[],
>+		double DestinationLinesToRequestRowInImmediateFlip[],
>+		double DestinationLinesToRequestVMInVBlank[],
>+		double DestinationLinesToRequestVMInImmediateFlip[],
>+		bool DCCEnable[],
>+		double PixelClock[],
>+		double BytePerPixelDETY[],
>+		double BytePerPixelDETC[],
>+		enum scan_direction_class SourceScan[],
>+		unsigned int dpte_row_height[],
>+		unsigned int dpte_row_height_chroma[],
>+		unsigned int meta_row_width[],
>+		unsigned int meta_row_height[],
>+		unsigned int meta_req_width[],
>+		unsigned int meta_req_height[],
>+		long dpte_group_bytes[],
>+		unsigned int PTERequestSizeY[],
>+		unsigned int PTERequestSizeC[],
>+		unsigned int PixelPTEReqWidthY[],
>+		unsigned int PixelPTEReqHeightY[],
>+		unsigned int PixelPTEReqWidthC[],
>+		unsigned int PixelPTEReqHeightC[],
>+		unsigned int dpte_row_width_luma_ub[],
>+		unsigned int dpte_row_width_chroma_ub[],
>+		unsigned int vm_group_bytes[],
>+		unsigned int dpde0_bytes_per_frame_ub_l[],
>+		unsigned int dpde0_bytes_per_frame_ub_c[],
>+		unsigned int meta_pte_bytes_per_frame_ub_l[],
>+		unsigned int meta_pte_bytes_per_frame_ub_c[],
>+		double DST_Y_PER_PTE_ROW_NOM_L[],
>+		double DST_Y_PER_PTE_ROW_NOM_C[],
>+		double DST_Y_PER_META_ROW_NOM_L[],
>+		double TimePerMetaChunkNominal[],
>+		double TimePerMetaChunkVBlank[],
>+		double TimePerMetaChunkFlip[],
>+		double time_per_pte_group_nom_luma[],
>+		double time_per_pte_group_vblank_luma[],
>+		double time_per_pte_group_flip_luma[],
>+		double time_per_pte_group_nom_chroma[],
>+		double time_per_pte_group_vblank_chroma[],
>+		double time_per_pte_group_flip_chroma[],
>+		double TimePerVMGroupVBlank[],
>+		double TimePerVMGroupFlip[],
>+		double TimePerVMRequestVBlank[],
>+		double TimePerVMRequestFlip[])
>+{
>+	unsigned int meta_chunk_width;
>+	unsigned int min_meta_chunk_width;
>+	unsigned int meta_chunk_per_row_int;
>+	unsigned int meta_row_remainder;
>+	unsigned int meta_chunk_threshold;
>+	unsigned int meta_chunks_per_row_ub;
>+	unsigned int dpte_group_width_luma;
>+	unsigned int dpte_group_width_chroma;
>+	unsigned int dpte_groups_per_row_luma_ub;
>+	unsigned int dpte_groups_per_row_chroma_ub;
>+	unsigned int num_group_per_lower_vm_stage;
>+	unsigned int num_req_per_lower_vm_stage;
>+	uint k;
>+
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		if (GPUVMEnable == true) {
>+			DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
>+			if (BytePerPixelDETC[k] == 0) {
>+				DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
>+			} else {
>+				DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / (VRatio[k] / 2);
>+			}
>+		} else {
>+			DST_Y_PER_PTE_ROW_NOM_L[k] = 0;
>+			DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
>+		}
>+		if (DCCEnable[k] == true) {
>+			DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
>+		} else {
>+			DST_Y_PER_META_ROW_NOM_L[k] = 0;
>+		}
>+	}
>+
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		if (DCCEnable[k] == true) {
>+			meta_chunk_width = MetaChunkSize * 1024 * 256
>+					/ dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k];
>+			min_meta_chunk_width = MinMetaChunkSizeBytes * 256
>+					/ dml_ceil(BytePerPixelDETY[k], 1) / meta_row_height[k];
>+			meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
>+			meta_row_remainder = meta_row_width[k] % meta_chunk_width;
>+			if (SourceScan[k] == dm_horz) {
>+				meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
>+			} else {
>+				meta_chunk_threshold = 2 * min_meta_chunk_width
>+						- meta_req_height[k];
>+			}
>+			if (meta_row_remainder <= meta_chunk_threshold) {
>+				meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
>+			} else {
>+				meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
>+			}
>+			TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k]
>+					/ PixelClock[k] / meta_chunks_per_row_ub;
>+			TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k]
>+					* HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
>+			TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k]
>+					* HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
>+		} else {
>+			TimePerMetaChunkNominal[k] = 0;
>+			TimePerMetaChunkVBlank[k] = 0;
>+			TimePerMetaChunkFlip[k] = 0;
>+		}
>+	}
>+
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		if (GPUVMEnable == true) {
>+			if (SourceScan[k] == dm_horz) {
>+				dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k]
>+						* PixelPTEReqWidthY[k];
>+			} else {
>+				dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k]
>+						* PixelPTEReqHeightY[k];
>+			}
>+			dpte_groups_per_row_luma_ub = dml_ceil(
>+					dpte_row_width_luma_ub[k] / dpte_group_width_luma,
>+					1);
>+			time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k]
>+					/ PixelClock[k] / dpte_groups_per_row_luma_ub;
>+			time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k]
>+					* HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
>+			time_per_pte_group_flip_luma[k] =
>+					DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k]
>+							/ PixelClock[k]
>+							/ dpte_groups_per_row_luma_ub;
>+			if (BytePerPixelDETC[k] == 0) {
>+				time_per_pte_group_nom_chroma[k] = 0;
>+				time_per_pte_group_vblank_chroma[k] = 0;
>+				time_per_pte_group_flip_chroma[k] = 0;
>+			} else {
>+				if (SourceScan[k] == dm_horz) {
>+					dpte_group_width_chroma = dpte_group_bytes[k]
>+							/ PTERequestSizeC[k] * PixelPTEReqWidthC[k];
>+				} else {
>+					dpte_group_width_chroma = dpte_group_bytes[k]
>+							/ PTERequestSizeC[k]
>+							* PixelPTEReqHeightC[k];
>+				}
>+				dpte_groups_per_row_chroma_ub = dml_ceil(
>+						dpte_row_width_chroma_ub[k]
>+								/ dpte_group_width_chroma,
>+						1);
>+				time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k]
>+						* HTotal[k] / PixelClock[k]
>+						/ dpte_groups_per_row_chroma_ub;
>+				time_per_pte_group_vblank_chroma[k] =
>+						DestinationLinesToRequestRowInVBlank[k] * HTotal[k]
>+								/ PixelClock[k]
>+								/ dpte_groups_per_row_chroma_ub;
>+				time_per_pte_group_flip_chroma[k] =
>+						DestinationLinesToRequestRowInImmediateFlip[k]
>+								* HTotal[k] / PixelClock[k]
>+								/ dpte_groups_per_row_chroma_ub;
>+			}
>+		} else {
>+			time_per_pte_group_nom_luma[k] = 0;
>+			time_per_pte_group_vblank_luma[k] = 0;
>+			time_per_pte_group_flip_luma[k] = 0;
>+			time_per_pte_group_nom_chroma[k] = 0;
>+			time_per_pte_group_vblank_chroma[k] = 0;
>+			time_per_pte_group_flip_chroma[k] = 0;
>+		}
>+	}
>+
>+	for (k = 0; k < NumberOfActivePlanes; ++k) {
>+		if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
>+			if (DCCEnable[k] == false) {
>+				if (BytePerPixelDETC[k] > 0) {
>+					num_group_per_lower_vm_stage =
>+						dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
>+						+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
>+				} else {
>+					num_group_per_lower_vm_stage =
>+							dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
>+				}
>+			} else {
>+				if (GPUVMMaxPageTableLevels == 1) {
>+					if (BytePerPixelDETC[k] > 0) {
>+						num_group_per_lower_vm_stage =
>+							dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
>+							+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
>+					} else {
>+						num_group_per_lower_vm_stage =
>+							dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
>+					}
>+				} else {
>+					if (BytePerPixelDETC[k] > 0) {
>+						num_group_per_lower_vm_stage =
>+							dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
>+							+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)
>+							+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
>+							+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
>+					} else {
>+						num_group_per_lower_vm_stage =
>+							dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
>+							+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
>+					}
>+				}
>+			}
>+
>+			if (DCCEnable[k] == false) {
>+				if (BytePerPixelDETC[k] > 0) {
>+					num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k]
>+							/ 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
>+				} else {
>+					num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k]
>+							/ 64;
>+				}
>+			} else {
>+				if (GPUVMMaxPageTableLevels == 1) {
>+					if (BytePerPixelDETC[k] > 0) {
>+						num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64
>+							+ meta_pte_bytes_per_frame_ub_c[k] / 64;
>+					} else {
>+						num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
>+					}
>+				} else {
>+					if (BytePerPixelDETC[k] > 0) {
>+						num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64
>+							+ dpde0_bytes_per_frame_ub_c[k] / 64
>+							+ meta_pte_bytes_per_frame_ub_l[k] / 64
>+							+ meta_pte_bytes_per_frame_ub_c[k] / 64;
>+					} else {
>+						num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64
>+							+ meta_pte_bytes_per_frame_ub_l[k] / 64;
>+					}
>+				}
>+			}
>+
>+			TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k]
>+					/ PixelClock[k] / num_group_per_lower_vm_stage;
>+			TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k]
>+					* HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
>+			TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k]
>+					* HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
>+			TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k]
>+					* HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
>+
>+			if (GPUVMMaxPageTableLevels > 2) {
>+				TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
>+				TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
>+				TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
>+				TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
>+			}
>+
>+		} else {
>+			TimePerVMGroupVBlank[k] = 0;
>+			TimePerVMGroupFlip[k] = 0;
>+			TimePerVMRequestVBlank[k] = 0;
>+			TimePerVMRequestFlip[k] = 0;
>+		}
>+	}
>+}
>+
>+static double CalculateExtraLatency(
>+		double UrgentRoundTripAndOutOfOrderLatency,
>+		int TotalNumberOfActiveDPP,
>+		int PixelChunkSizeInKByte,
>+		int TotalNumberOfDCCActiveDPP,
>+		int MetaChunkSize,
>+		double ReturnBW,
>+		bool GPUVMEnable,
>+		bool HostVMEnable,
>+		int NumberOfActivePlanes,
>+		int NumberOfDPP[],
>+		long dpte_group_bytes[],
>+		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData,
>+		double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
>+		int HostVMMaxPageTableLevels,
>+		int HostVMCachedPageTableLevels)
>+{
>+	double CalculateExtraLatency;
>+	double HostVMInefficiencyFactor;
>+	int HostVMDynamicLevels;
>+
>+	if (GPUVMEnable && HostVMEnable) {
>+		HostVMInefficiencyFactor =
>+				PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData
>+						/ PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly;
>+		HostVMDynamicLevels = HostVMMaxPageTableLevels - HostVMCachedPageTableLevels;
>+	} else {
>+		HostVMInefficiencyFactor = 1;
>+		HostVMDynamicLevels = 0;
>+	}
>+
>+	CalculateExtraLatency = UrgentRoundTripAndOutOfOrderLatency
>+			+ (TotalNumberOfActiveDPP * PixelChunkSizeInKByte
>+					+ TotalNumberOfDCCActiveDPP * MetaChunkSize) * 1024.0
>+					/ ReturnBW;
>+
>+	if (GPUVMEnable) {
>+		int k;
>+
>+		for (k = 0; k < NumberOfActivePlanes; k++) {
>+			CalculateExtraLatency = CalculateExtraLatency
>+					+ NumberOfDPP[k] * dpte_group_bytes[k]
>+							* (1 + 8 * HostVMDynamicLevels)
>+							* HostVMInefficiencyFactor / ReturnBW;
>+		}
>+	}
>+	return CalculateExtraLatency;
>+}
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.h	2019-08-31 15:01:11.868736169 -0500
>@@ -0,0 +1,32 @@
>+/*
>+ * Copyright 2017 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifndef __DML21_DISPLAY_MODE_VBA_H__
>+#define __DML21_DISPLAY_MODE_VBA_H__
>+
>+void dml21_recalculate(struct display_mode_lib *mode_lib);
>+void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
>+
>+#endif /* _DML21_DISPLAY_MODE_VBA_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c	2019-08-31 15:01:11.868736169 -0500
>@@ -0,0 +1,1823 @@
>+/*
>+ * Copyright 2017 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
>+
>+#include "../display_mode_lib.h"
>+#include "../display_mode_vba.h"
>+#include "../dml_inline_defs.h"
>+#include "display_rq_dlg_calc_21.h"
>+
>+/*
>+ * NOTE:
>+ *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
>+ *
>+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
>+ * ways. Unless there is something clearly wrong with it the code should
>+ * remain as-is as it provides us with a guarantee from HW that it is correct.
>+ */
>+
>+static void calculate_ttu_cursor(
>+		struct display_mode_lib *mode_lib,
>+		double *refcyc_per_req_delivery_pre_cur,
>+		double *refcyc_per_req_delivery_cur,
>+		double refclk_freq_in_mhz,
>+		double ref_freq_to_pix_freq,
>+		double hscale_pixel_rate_l,
>+		double hscl_ratio,
>+		double vratio_pre_l,
>+		double vratio_l,
>+		unsigned int cur_width,
>+		enum cursor_bpp cur_bpp);
>+
>+static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
>+{
>+	unsigned int ret_val = 0;
>+
>+	if (source_format == dm_444_16) {
>+		if (!is_chroma)
>+			ret_val = 2;
>+	} else if (source_format == dm_444_32) {
>+		if (!is_chroma)
>+			ret_val = 4;
>+	} else if (source_format == dm_444_64) {
>+		if (!is_chroma)
>+			ret_val = 8;
>+	} else if (source_format == dm_420_8) {
>+		if (is_chroma)
>+			ret_val = 2;
>+		else
>+			ret_val = 1;
>+	} else if (source_format == dm_420_10) {
>+		if (is_chroma)
>+			ret_val = 4;
>+		else
>+			ret_val = 2;
>+	} else if (source_format == dm_444_8) {
>+		ret_val = 1;
>+	}
>+	return ret_val;
>+}
>+
>+static bool is_dual_plane(enum source_format_class source_format)
>+{
>+	bool ret_val = 0;
>+
>+	if ((source_format == dm_420_8) || (source_format == dm_420_10))
>+		ret_val = 1;
>+
>+	return ret_val;
>+}
>+
>+static double get_refcyc_per_delivery(
>+		struct display_mode_lib *mode_lib,
>+		double refclk_freq_in_mhz,
>+		double pclk_freq_in_mhz,
>+		bool odm_combine,
>+		unsigned int recout_width,
>+		unsigned int hactive,
>+		double vratio,
>+		double hscale_pixel_rate,
>+		unsigned int delivery_width,
>+		unsigned int req_per_swath_ub)
>+{
>+	double refcyc_per_delivery = 0.0;
>+
>+	if (vratio <= 1.0) {
>+		if (odm_combine)
>+			refcyc_per_delivery = (double) refclk_freq_in_mhz
>+					* dml_min((double) recout_width, (double) hactive / 2.0)
>+					/ pclk_freq_in_mhz / (double) req_per_swath_ub;
>+		else
>+			refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width
>+					/ pclk_freq_in_mhz / (double) req_per_swath_ub;
>+	} else {
>+		refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width
>+				/ (double) hscale_pixel_rate / (double) req_per_swath_ub;
>+	}
>+
>+	dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
>+	dml_print("DML_DLG: %s: pclk_freq_in_mhz   = %3.2f\n", __func__, pclk_freq_in_mhz);
>+	dml_print("DML_DLG: %s: recout_width       = %d\n", __func__, recout_width);
>+	dml_print("DML_DLG: %s: vratio             = %3.2f\n", __func__, vratio);
>+	dml_print("DML_DLG: %s: req_per_swath_ub   = %d\n", __func__, req_per_swath_ub);
>+	dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
>+
>+	return refcyc_per_delivery;
>+
>+}
>+
>+static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
>+{
>+	if (tile_size == dm_256k_tile)
>+		return (256 * 1024);
>+	else if (tile_size == dm_64k_tile)
>+		return (64 * 1024);
>+	else
>+		return (4 * 1024);
>+}
>+
>+static void extract_rq_sizing_regs(
>+		struct display_mode_lib *mode_lib,
>+		display_data_rq_regs_st *rq_regs,
>+		const display_data_rq_sizing_params_st rq_sizing)
>+{
>+	dml_print("DML_DLG: %s: rq_sizing param\n", __func__);
>+	print__data_rq_sizing_params_st(mode_lib, rq_sizing);
>+
>+	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
>+
>+	if (rq_sizing.min_chunk_bytes == 0)
>+		rq_regs->min_chunk_size = 0;
>+	else
>+		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
>+
>+	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
>+	if (rq_sizing.min_meta_chunk_bytes == 0)
>+		rq_regs->min_meta_chunk_size = 0;
>+	else
>+		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
>+
>+	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
>+	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
>+}
>+
>+static void extract_rq_regs(
>+		struct display_mode_lib *mode_lib,
>+		display_rq_regs_st *rq_regs,
>+		const display_rq_params_st rq_param)
>+{
>+	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
>+	unsigned int detile_buf_plane1_addr = 0;
>+
>+	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
>+
>+	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(
>+			dml_log2(rq_param.dlg.rq_l.dpte_row_height),
>+			1) - 3;
>+
>+	if (rq_param.yuv420) {
>+		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
>+		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(
>+				dml_log2(rq_param.dlg.rq_c.dpte_row_height),
>+				1) - 3;
>+	}
>+
>+	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
>+	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
>+
>+	// FIXME: take the max between luma, chroma chunk size?
>+	// okay for now, as we are setting chunk_bytes to 8kb anyways
>+	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb
>+		rq_regs->drq_expansion_mode = 0;
>+	} else {
>+		rq_regs->drq_expansion_mode = 2;
>+	}
>+	rq_regs->prq_expansion_mode = 1;
>+	rq_regs->mrq_expansion_mode = 1;
>+	rq_regs->crq_expansion_mode = 1;
>+
>+	if (rq_param.yuv420) {
>+		if ((double) rq_param.misc.rq_l.stored_swath_bytes
>+				/ (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
>+			detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma
>+		} else {
>+			detile_buf_plane1_addr = dml_round_to_multiple(
>+					(unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
>+					256,
>+					0) / 64.0; // 2/3 to chroma
>+		}
>+	}
>+	rq_regs->plane1_base_address = detile_buf_plane1_addr;
>+}
>+
>+static void handle_det_buf_split(
>+		struct display_mode_lib *mode_lib,
>+		display_rq_params_st *rq_param,
>+		const display_pipe_source_params_st pipe_src_param)
>+{
>+	unsigned int total_swath_bytes = 0;
>+	unsigned int swath_bytes_l = 0;
>+	unsigned int swath_bytes_c = 0;
>+	unsigned int full_swath_bytes_packed_l = 0;
>+	unsigned int full_swath_bytes_packed_c = 0;
>+	bool req128_l = 0;
>+	bool req128_c = 0;
>+	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
>+	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
>+	unsigned int log2_swath_height_l = 0;
>+	unsigned int log2_swath_height_c = 0;
>+	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
>+
>+	full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
>+	full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
>+
>+	if (rq_param->yuv420_10bpc) {
>+		full_swath_bytes_packed_l = dml_round_to_multiple(
>+				rq_param->misc.rq_l.full_swath_bytes * 2 / 3,
>+				256,
>+				1) + 256;
>+		full_swath_bytes_packed_c = dml_round_to_multiple(
>+				rq_param->misc.rq_c.full_swath_bytes * 2 / 3,
>+				256,
>+				1) + 256;
>+	}
>+
>+	if (rq_param->yuv420) {
>+		total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
>+
>+		if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
>+			req128_l = 0;
>+			req128_c = 0;
>+			swath_bytes_l = full_swath_bytes_packed_l;
>+			swath_bytes_c = full_swath_bytes_packed_c;
>+		} else { //128b request (for luma only for yuv420 8bpc)
>+			req128_l = 1;
>+			req128_c = 0;
>+			swath_bytes_l = full_swath_bytes_packed_l / 2;
>+			swath_bytes_c = full_swath_bytes_packed_c;
>+		}
>+		// Note: assumption, the config that pass in will fit into
>+		//       the detiled buffer.
>+	} else {
>+		total_swath_bytes = 2 * full_swath_bytes_packed_l;
>+
>+		if (total_swath_bytes <= detile_buf_size_in_bytes)
>+			req128_l = 0;
>+		else
>+			req128_l = 1;
>+
>+		swath_bytes_l = total_swath_bytes;
>+		swath_bytes_c = 0;
>+	}
>+	rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
>+	rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
>+
>+	if (surf_linear) {
>+		log2_swath_height_l = 0;
>+		log2_swath_height_c = 0;
>+	} else if (!surf_vert) {
>+		log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
>+		log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
>+	} else {
>+		log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
>+		log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
>+	}
>+	rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
>+	rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
>+
>+	dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
>+	dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
>+	dml_print(
>+			"DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",
>+			__func__,
>+			full_swath_bytes_packed_l);
>+	dml_print(
>+			"DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",
>+			__func__,
>+			full_swath_bytes_packed_c);
>+}
>+
>+static void get_meta_and_pte_attr(
>+		struct display_mode_lib *mode_lib,
>+		display_data_rq_dlg_params_st *rq_dlg_param,
>+		display_data_rq_misc_params_st *rq_misc_param,
>+		display_data_rq_sizing_params_st *rq_sizing_param,
>+		unsigned int vp_width,
>+		unsigned int vp_height,
>+		unsigned int data_pitch,
>+		unsigned int meta_pitch,
>+		unsigned int source_format,
>+		unsigned int tiling,
>+		unsigned int macro_tile_size,
>+		unsigned int source_scan,
>+		unsigned int hostvm_enable,
>+		unsigned int is_chroma)
>+{
>+	bool surf_linear = (tiling == dm_sw_linear);
>+	bool surf_vert = (source_scan == dm_vert);
>+
>+	unsigned int bytes_per_element;
>+	unsigned int bytes_per_element_y = get_bytes_per_element(
>+			(enum source_format_class) (source_format),
>+			false);
>+	unsigned int bytes_per_element_c = get_bytes_per_element(
>+			(enum source_format_class) (source_format),
>+			true);
>+
>+	unsigned int blk256_width = 0;
>+	unsigned int blk256_height = 0;
>+
>+	unsigned int blk256_width_y = 0;
>+	unsigned int blk256_height_y = 0;
>+	unsigned int blk256_width_c = 0;
>+	unsigned int blk256_height_c = 0;
>+	unsigned int log2_bytes_per_element;
>+	unsigned int log2_blk256_width;
>+	unsigned int log2_blk256_height;
>+	unsigned int blk_bytes;
>+	unsigned int log2_blk_bytes;
>+	unsigned int log2_blk_height;
>+	unsigned int log2_blk_width;
>+	unsigned int log2_meta_req_bytes;
>+	unsigned int log2_meta_req_height;
>+	unsigned int log2_meta_req_width;
>+	unsigned int meta_req_width;
>+	unsigned int meta_req_height;
>+	unsigned int log2_meta_row_height;
>+	unsigned int meta_row_width_ub;
>+	unsigned int log2_meta_chunk_bytes;
>+	unsigned int log2_meta_chunk_height;
>+
>+	//full sized meta chunk width in unit of data elements
>+	unsigned int log2_meta_chunk_width;
>+	unsigned int log2_min_meta_chunk_bytes;
>+	unsigned int min_meta_chunk_width;
>+	unsigned int meta_chunk_width;
>+	unsigned int meta_chunk_per_row_int;
>+	unsigned int meta_row_remainder;
>+	unsigned int meta_chunk_threshold;
>+	unsigned int meta_blk_bytes;
>+	unsigned int meta_blk_height;
>+	unsigned int meta_blk_width;
>+	unsigned int meta_surface_bytes;
>+	unsigned int vmpg_bytes;
>+	unsigned int meta_pte_req_per_frame_ub;
>+	unsigned int meta_pte_bytes_per_frame_ub;
>+	const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
>+	const unsigned int dpte_buf_in_pte_reqs =
>+		mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma;
>+	const unsigned int pde_proc_buffer_size_64k_reqs =
>+			mode_lib->ip.pde_proc_buffer_size_64k_reqs;
>+
>+	unsigned int log2_vmpg_height = 0;
>+	unsigned int log2_vmpg_width = 0;
>+	unsigned int log2_dpte_req_height_ptes = 0;
>+	unsigned int log2_dpte_req_height = 0;
>+	unsigned int log2_dpte_req_width = 0;
>+	unsigned int log2_dpte_row_height_linear = 0;
>+	unsigned int log2_dpte_row_height = 0;
>+	unsigned int log2_dpte_group_width = 0;
>+	unsigned int dpte_row_width_ub = 0;
>+	unsigned int dpte_req_height = 0;
>+	unsigned int dpte_req_width = 0;
>+	unsigned int dpte_group_width = 0;
>+	unsigned int log2_dpte_group_bytes = 0;
>+	unsigned int log2_dpte_group_length = 0;
>+	unsigned int pde_buf_entries;
>+	bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10);
>+
>+	Calculate256BBlockSizes(
>+			(enum source_format_class) (source_format),
>+			(enum dm_swizzle_mode) (tiling),
>+			bytes_per_element_y,
>+			bytes_per_element_c,
>+			&blk256_height_y,
>+			&blk256_height_c,
>+			&blk256_width_y,
>+			&blk256_width_c);
>+
>+	if (!is_chroma) {
>+		blk256_width = blk256_width_y;
>+		blk256_height = blk256_height_y;
>+		bytes_per_element = bytes_per_element_y;
>+	} else {
>+		blk256_width = blk256_width_c;
>+		blk256_height = blk256_height_c;
>+		bytes_per_element = bytes_per_element_c;
>+	}
>+
>+	log2_bytes_per_element = dml_log2(bytes_per_element);
>+
>+	dml_print("DML_DLG: %s: surf_linear        = %d\n", __func__, surf_linear);
>+	dml_print("DML_DLG: %s: surf_vert          = %d\n", __func__, surf_vert);
>+	dml_print("DML_DLG: %s: blk256_width       = %d\n", __func__, blk256_width);
>+	dml_print("DML_DLG: %s: blk256_height      = %d\n", __func__, blk256_height);
>+
>+	log2_blk256_width = dml_log2((double) blk256_width);
>+	log2_blk256_height = dml_log2((double) blk256_height);
>+	blk_bytes = surf_linear ?
>+			256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
>+	log2_blk_bytes = dml_log2((double) blk_bytes);
>+	log2_blk_height = 0;
>+	log2_blk_width = 0;
>+
>+	// remember log rule
>+	// "+" in log is multiply
>+	// "-" in log is divide
>+	// "/2" is like square root
>+	// blk is vertical biased
>+	if (tiling != dm_sw_linear)
>+		log2_blk_height = log2_blk256_height
>+				+ dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
>+	else
>+		log2_blk_height = 0;  // blk height of 1
>+
>+	log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
>+
>+	if (!surf_vert) {
>+		rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
>+				+ blk256_width;
>+		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
>+	} else {
>+		rq_dlg_param->swath_width_ub = dml_round_to_multiple(
>+				vp_height - 1,
>+				blk256_height,
>+				1) + blk256_height;
>+		rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
>+	}
>+
>+	if (!surf_vert)
>+		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
>+				* bytes_per_element;
>+	else
>+		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
>+				* bytes_per_element;
>+
>+	rq_misc_param->blk256_height = blk256_height;
>+	rq_misc_param->blk256_width = blk256_width;
>+
>+	// -------
>+	// meta
>+	// -------
>+	log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element
>+
>+	// each 64b meta request for dcn is 8x8 meta elements and
>+	// a meta element covers one 256b block of the the data surface.
>+	log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256
>+	log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
>+			- log2_meta_req_height;
>+	meta_req_width = 1 << log2_meta_req_width;
>+	meta_req_height = 1 << log2_meta_req_height;
>+	log2_meta_row_height = 0;
>+	meta_row_width_ub = 0;
>+
>+	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.
>+	// calculate upper bound of the meta_row_width
>+	if (!surf_vert) {
>+		log2_meta_row_height = log2_meta_req_height;
>+		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
>+				+ meta_req_width;
>+		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
>+	} else {
>+		log2_meta_row_height = log2_meta_req_width;
>+		meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1)
>+				+ meta_req_height;
>+		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
>+	}
>+	rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
>+
>+	rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
>+
>+	log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
>+	log2_meta_chunk_height = log2_meta_row_height;
>+
>+	//full sized meta chunk width in unit of data elements
>+	log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element
>+			- log2_meta_chunk_height;
>+	log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
>+	min_meta_chunk_width = 1
>+			<< (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element
>+					- log2_meta_chunk_height);
>+	meta_chunk_width = 1 << log2_meta_chunk_width;
>+	meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
>+	meta_row_remainder = meta_row_width_ub % meta_chunk_width;
>+	meta_chunk_threshold = 0;
>+	meta_blk_bytes = 4096;
>+	meta_blk_height = blk256_height * 64;
>+	meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height;
>+	meta_surface_bytes = meta_pitch
>+			* (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1)
>+					+ meta_blk_height) * bytes_per_element / 256;
>+	vmpg_bytes = mode_lib->soc.vmm_page_size_bytes;
>+	meta_pte_req_per_frame_ub = (dml_round_to_multiple(
>+			meta_surface_bytes - vmpg_bytes,
>+			8 * vmpg_bytes,
>+			1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
>+	meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request
>+	rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
>+
>+	dml_print("DML_DLG: %s: meta_blk_height             = %d\n", __func__, meta_blk_height);
>+	dml_print("DML_DLG: %s: meta_blk_width              = %d\n", __func__, meta_blk_width);
>+	dml_print("DML_DLG: %s: meta_surface_bytes          = %d\n", __func__, meta_surface_bytes);
>+	dml_print(
>+			"DML_DLG: %s: meta_pte_req_per_frame_ub   = %d\n",
>+			__func__,
>+			meta_pte_req_per_frame_ub);
>+	dml_print(
>+			"DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",
>+			__func__,
>+			meta_pte_bytes_per_frame_ub);
>+
>+	if (!surf_vert)
>+		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
>+	else
>+		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
>+
>+	if (meta_row_remainder <= meta_chunk_threshold)
>+		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
>+	else
>+		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
>+
>+	// ------
>+	// dpte
>+	// ------
>+	if (surf_linear) {
>+		log2_vmpg_height = 0;   // one line high
>+	} else {
>+		log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
>+	}
>+	log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
>+
>+	// only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
>+	if (surf_linear) { //one 64B PTE request returns 8 PTEs
>+		log2_dpte_req_height_ptes = 0;
>+		log2_dpte_req_width = log2_vmpg_width + 3;
>+		log2_dpte_req_height = 0;
>+	} else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
>+					   //one 64B req gives 8x1 PTEs for 4KB tile
>+		log2_dpte_req_height_ptes = 0;
>+		log2_dpte_req_width = log2_blk_width + 3;
>+		log2_dpte_req_height = log2_blk_height + 0;
>+	} else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
>+									//two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
>+		log2_dpte_req_height_ptes = 4;
>+		log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width
>+		log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height
>+	} else { //64KB page size and must 64KB tile block
>+		 //one 64B req gives 8x1 PTEs for 64KB tile
>+		log2_dpte_req_height_ptes = 0;
>+		log2_dpte_req_width = log2_blk_width + 3;
>+		log2_dpte_req_height = log2_blk_height + 0;
>+	}
>+
>+	// The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
>+	// log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
>+	// That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
>+	//log2_dpte_req_height    = log2_vmpg_height + log2_dpte_req_height_ptes;
>+	//log2_dpte_req_width     = log2_vmpg_width + log2_dpte_req_width_ptes;
>+	dpte_req_height = 1 << log2_dpte_req_height;
>+	dpte_req_width = 1 << log2_dpte_req_width;
>+
>+	// calculate pitch dpte row buffer can hold
>+	// round the result down to a power of two.
>+	pde_buf_entries =
>+			yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs;
>+	if (surf_linear) {
>+		unsigned int dpte_row_height;
>+
>+		log2_dpte_row_height_linear = dml_floor(
>+				dml_log2(
>+						dml_min(
>+								64 * 1024 * pde_buf_entries
>+										/ bytes_per_element,
>+								dpte_buf_in_pte_reqs
>+										* dpte_req_width)
>+								/ data_pitch),
>+				1);
>+
>+		ASSERT(log2_dpte_row_height_linear >= 3);
>+
>+		if (log2_dpte_row_height_linear > 7)
>+			log2_dpte_row_height_linear = 7;
>+
>+		log2_dpte_row_height = log2_dpte_row_height_linear;
>+		// For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
>+		// the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
>+		dpte_row_height = 1 << log2_dpte_row_height;
>+		dpte_row_width_ub = dml_round_to_multiple(
>+				data_pitch * dpte_row_height - 1,
>+				dpte_req_width,
>+				1) + dpte_req_width;
>+		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
>+	} else {
>+		// the upper bound of the dpte_row_width without dependency on viewport position follows.
>+		// for tiled mode, row height is the same as req height and row store up to vp size upper bound
>+		if (!surf_vert) {
>+			log2_dpte_row_height = log2_dpte_req_height;
>+			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
>+					+ dpte_req_width;
>+			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
>+		} else {
>+			log2_dpte_row_height =
>+					(log2_blk_width < log2_dpte_req_width) ?
>+							log2_blk_width : log2_dpte_req_width;
>+			dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
>+					+ dpte_req_height;
>+			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
>+		}
>+	}
>+	if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
>+		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
>+	else
>+		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
>+
>+	rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
>+
>+	// the dpte_group_bytes is reduced for the specific case of vertical
>+	// access of a tile surface that has dpte request of 8x1 ptes.
>+
>+	if (hostvm_enable)
>+		rq_sizing_param->dpte_group_bytes = 512;
>+	else {
>+		if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
>+			rq_sizing_param->dpte_group_bytes = 512;
>+		else
>+			//full size
>+			rq_sizing_param->dpte_group_bytes = 2048;
>+	}
>+
>+	//since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
>+	log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
>+	log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
>+
>+	// full sized data pte group width in elements
>+	if (!surf_vert)
>+		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
>+	else
>+		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
>+
>+	//But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
>+	if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
>+		log2_dpte_group_width = log2_dpte_group_width - 1;
>+
>+	dpte_group_width = 1 << log2_dpte_group_width;
>+
>+	// since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
>+	// the upper bound for the dpte groups per row is as follows.
>+	rq_dlg_param->dpte_groups_per_row_ub = dml_ceil(
>+			(double) dpte_row_width_ub / dpte_group_width,
>+			1);
>+}
>+
>+static void get_surf_rq_param(
>+		struct display_mode_lib *mode_lib,
>+		display_data_rq_sizing_params_st *rq_sizing_param,
>+		display_data_rq_dlg_params_st *rq_dlg_param,
>+		display_data_rq_misc_params_st *rq_misc_param,
>+		const display_pipe_params_st pipe_param,
>+		bool is_chroma)
>+{
>+	bool mode_422 = 0;
>+	unsigned int vp_width = 0;
>+	unsigned int vp_height = 0;
>+	unsigned int data_pitch = 0;
>+	unsigned int meta_pitch = 0;
>+	unsigned int ppe = mode_422 ? 2 : 1;
>+
>+	// FIXME check if ppe apply for both luma and chroma in 422 case
>+	if (is_chroma) {
>+		vp_width = pipe_param.src.viewport_width_c / ppe;
>+		vp_height = pipe_param.src.viewport_height_c;
>+		data_pitch = pipe_param.src.data_pitch_c;
>+		meta_pitch = pipe_param.src.meta_pitch_c;
>+	} else {
>+		vp_width = pipe_param.src.viewport_width / ppe;
>+		vp_height = pipe_param.src.viewport_height;
>+		data_pitch = pipe_param.src.data_pitch;
>+		meta_pitch = pipe_param.src.meta_pitch;
>+	}
>+
>+	if (pipe_param.dest.odm_combine) {
>+		unsigned int access_dir;
>+		unsigned int full_src_vp_width;
>+		unsigned int hactive_half;
>+		unsigned int src_hactive_half;
>+		access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
>+		hactive_half  = pipe_param.dest.hactive / 2;
>+		if (is_chroma) {
>+			full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width;
>+			src_hactive_half  = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_half;
>+		} else {
>+			full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width;
>+			src_hactive_half  = pipe_param.scale_ratio_depth.hscl_ratio * hactive_half;
>+		}
>+
>+		if (access_dir == 0) {
>+			vp_width = dml_min(full_src_vp_width, src_hactive_half);
>+			dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width);
>+		} else {
>+			vp_height = dml_min(full_src_vp_width, src_hactive_half);
>+			dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height);
>+
>+		}
>+		dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width);
>+		dml_print("DML_DLG: %s: hactive_half = %d\n", __func__, hactive_half);
>+		dml_print("DML_DLG: %s: src_hactive_half = %d\n", __func__, src_hactive_half);
>+	}
>+	rq_sizing_param->chunk_bytes = 8192;
>+
>+	if (rq_sizing_param->chunk_bytes == 64 * 1024)
>+		rq_sizing_param->min_chunk_bytes = 0;
>+	else
>+		rq_sizing_param->min_chunk_bytes = 1024;
>+
>+	rq_sizing_param->meta_chunk_bytes = 2048;
>+	rq_sizing_param->min_meta_chunk_bytes = 256;
>+
>+	if (pipe_param.src.hostvm)
>+		rq_sizing_param->mpte_group_bytes = 512;
>+	else
>+		rq_sizing_param->mpte_group_bytes = 2048;
>+
>+	get_meta_and_pte_attr(
>+			mode_lib,
>+			rq_dlg_param,
>+			rq_misc_param,
>+			rq_sizing_param,
>+			vp_width,
>+			vp_height,
>+			data_pitch,
>+			meta_pitch,
>+			pipe_param.src.source_format,
>+			pipe_param.src.sw_mode,
>+			pipe_param.src.macro_tile_size,
>+			pipe_param.src.source_scan,
>+			pipe_param.src.hostvm,
>+			is_chroma);
>+}
>+
>+static void dml_rq_dlg_get_rq_params(
>+		struct display_mode_lib *mode_lib,
>+		display_rq_params_st *rq_param,
>+		const display_pipe_params_st pipe_param)
>+{
>+	// get param for luma surface
>+	rq_param->yuv420 = pipe_param.src.source_format == dm_420_8
>+			|| pipe_param.src.source_format == dm_420_10;
>+	rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10;
>+
>+	get_surf_rq_param(
>+			mode_lib,
>+			&(rq_param->sizing.rq_l),
>+			&(rq_param->dlg.rq_l),
>+			&(rq_param->misc.rq_l),
>+			pipe_param,
>+			0);
>+
>+	if (is_dual_plane((enum source_format_class) (pipe_param.src.source_format))) {
>+		// get param for chroma surface
>+		get_surf_rq_param(
>+				mode_lib,
>+				&(rq_param->sizing.rq_c),
>+				&(rq_param->dlg.rq_c),
>+				&(rq_param->misc.rq_c),
>+				pipe_param,
>+				1);
>+	}
>+
>+	// calculate how to split the det buffer space between luma and chroma
>+	handle_det_buf_split(mode_lib, rq_param, pipe_param.src);
>+	print__rq_params_st(mode_lib, *rq_param);
>+}
>+
>+void dml21_rq_dlg_get_rq_reg(
>+		struct display_mode_lib *mode_lib,
>+		display_rq_regs_st *rq_regs,
>+		const display_pipe_params_st pipe_param)
>+{
>+	display_rq_params_st rq_param = {0};
>+
>+	memset(rq_regs, 0, sizeof(*rq_regs));
>+	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param);
>+	extract_rq_regs(mode_lib, rq_regs, rq_param);
>+
>+	print__rq_regs_st(mode_lib, *rq_regs);
>+}
>+
>+// Note: currently taken in as is.
>+// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
>+static void dml_rq_dlg_get_dlg_params(
>+		struct display_mode_lib *mode_lib,
>+		const display_e2e_pipe_params_st *e2e_pipe_param,
>+		const unsigned int num_pipes,
>+		const unsigned int pipe_idx,
>+		display_dlg_regs_st *disp_dlg_regs,
>+		display_ttu_regs_st *disp_ttu_regs,
>+		const display_rq_dlg_params_st rq_dlg_param,
>+		const display_dlg_sys_params_st dlg_sys_param,
>+		const bool cstate_en,
>+		const bool pstate_en)
>+{
>+	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
>+	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
>+	const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
>+	const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
>+	const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
>+	const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
>+
>+	// -------------------------
>+	// Section 1.15.2.1: OTG dependent Params
>+	// -------------------------
>+	// Timing
>+	unsigned int htotal = dst->htotal;
>+	//    unsigned int hblank_start = dst.hblank_start; // TODO: Remove
>+	unsigned int hblank_end = dst->hblank_end;
>+	unsigned int vblank_start = dst->vblank_start;
>+	unsigned int vblank_end = dst->vblank_end;
>+	unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
>+
>+	double dppclk_freq_in_mhz = clks->dppclk_mhz;
>+	double dispclk_freq_in_mhz = clks->dispclk_mhz;
>+	double refclk_freq_in_mhz = clks->refclk_mhz;
>+	double pclk_freq_in_mhz = dst->pixel_rate_mhz;
>+	bool interlaced = dst->interlaced;
>+
>+	double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
>+
>+	double min_dcfclk_mhz;
>+	double t_calc_us;
>+	double min_ttu_vblank;
>+
>+	double min_dst_y_ttu_vblank;
>+	unsigned int dlg_vblank_start;
>+	bool dual_plane;
>+	bool mode_422;
>+	unsigned int access_dir;
>+	unsigned int vp_height_l;
>+	unsigned int vp_width_l;
>+	unsigned int vp_height_c;
>+	unsigned int vp_width_c;
>+
>+	// Scaling
>+	unsigned int htaps_l;
>+	unsigned int htaps_c;
>+	double hratio_l;
>+	double hratio_c;
>+	double vratio_l;
>+	double vratio_c;
>+	bool scl_enable;
>+
>+	double line_time_in_us;
>+	//    double vinit_l;
>+	//    double vinit_c;
>+	//    double vinit_bot_l;
>+	//    double vinit_bot_c;
>+
>+	//    unsigned int swath_height_l;
>+	unsigned int swath_width_ub_l;
>+	//    unsigned int dpte_bytes_per_row_ub_l;
>+	unsigned int dpte_groups_per_row_ub_l;
>+	//    unsigned int meta_pte_bytes_per_frame_ub_l;
>+	//    unsigned int meta_bytes_per_row_ub_l;
>+
>+	//    unsigned int swath_height_c;
>+	unsigned int swath_width_ub_c;
>+	//   unsigned int dpte_bytes_per_row_ub_c;
>+	unsigned int dpte_groups_per_row_ub_c;
>+
>+	unsigned int meta_chunks_per_row_ub_l;
>+	unsigned int meta_chunks_per_row_ub_c;
>+	unsigned int vupdate_offset;
>+	unsigned int vupdate_width;
>+	unsigned int vready_offset;
>+
>+	unsigned int dppclk_delay_subtotal;
>+	unsigned int dispclk_delay_subtotal;
>+	unsigned int pixel_rate_delay_subtotal;
>+
>+	unsigned int vstartup_start;
>+	unsigned int dst_x_after_scaler;
>+	unsigned int dst_y_after_scaler;
>+	double line_wait;
>+	double dst_y_prefetch;
>+	double dst_y_per_vm_vblank;
>+	double dst_y_per_row_vblank;
>+	double dst_y_per_vm_flip;
>+	double dst_y_per_row_flip;
>+	double max_dst_y_per_vm_vblank;
>+	double max_dst_y_per_row_vblank;
>+	double lsw;
>+	double vratio_pre_l;
>+	double vratio_pre_c;
>+	unsigned int req_per_swath_ub_l;
>+	unsigned int req_per_swath_ub_c;
>+	unsigned int meta_row_height_l;
>+	unsigned int meta_row_height_c;
>+	unsigned int swath_width_pixels_ub_l;
>+	unsigned int swath_width_pixels_ub_c;
>+	unsigned int scaler_rec_in_width_l;
>+	unsigned int scaler_rec_in_width_c;
>+	unsigned int dpte_row_height_l;
>+	unsigned int dpte_row_height_c;
>+	double hscale_pixel_rate_l;
>+	double hscale_pixel_rate_c;
>+	double min_hratio_fact_l;
>+	double min_hratio_fact_c;
>+	double refcyc_per_line_delivery_pre_l;
>+	double refcyc_per_line_delivery_pre_c;
>+	double refcyc_per_line_delivery_l;
>+	double refcyc_per_line_delivery_c;
>+
>+	double refcyc_per_req_delivery_pre_l;
>+	double refcyc_per_req_delivery_pre_c;
>+	double refcyc_per_req_delivery_l;
>+	double refcyc_per_req_delivery_c;
>+
>+	unsigned int full_recout_width;
>+	double xfc_transfer_delay;
>+	double xfc_precharge_delay;
>+	double xfc_remote_surface_flip_latency;
>+	double xfc_dst_y_delta_drq_limit;
>+	double xfc_prefetch_margin;
>+	double refcyc_per_req_delivery_pre_cur0;
>+	double refcyc_per_req_delivery_cur0;
>+	double refcyc_per_req_delivery_pre_cur1;
>+	double refcyc_per_req_delivery_cur1;
>+
>+	memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
>+	memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
>+
>+	dml_print("DML_DLG: %s:  cstate_en = %d\n", __func__, cstate_en);
>+	dml_print("DML_DLG: %s:  pstate_en = %d\n", __func__, pstate_en);
>+
>+	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
>+	dml_print("DML_DLG: %s: dispclk_freq_in_mhz    = %3.2f\n", __func__, dispclk_freq_in_mhz);
>+	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
>+	dml_print("DML_DLG: %s: pclk_freq_in_mhz       = %3.2f\n", __func__, pclk_freq_in_mhz);
>+	dml_print("DML_DLG: %s: interlaced             = %d\n", __func__, interlaced);
>+	ASSERT(ref_freq_to_pix_freq < 4.0);
>+
>+	disp_dlg_regs->ref_freq_to_pix_freq =
>+			(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
>+	disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
>+			* dml_pow(2, 8));
>+	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
>+	disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end
>+			* (double) ref_freq_to_pix_freq);
>+	ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
>+
>+	min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
>+	t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes);
>+	min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+
>+	min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
>+	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
>+
>+	disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
>+	ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
>+
>+	dml_print(
>+			"DML_DLG: %s: min_dcfclk_mhz                         = %3.2f\n",
>+			__func__,
>+			min_dcfclk_mhz);
>+	dml_print(
>+			"DML_DLG: %s: min_ttu_vblank                         = %3.2f\n",
>+			__func__,
>+			min_ttu_vblank);
>+	dml_print(
>+			"DML_DLG: %s: min_dst_y_ttu_vblank                   = %3.2f\n",
>+			__func__,
>+			min_dst_y_ttu_vblank);
>+	dml_print(
>+			"DML_DLG: %s: t_calc_us                              = %3.2f\n",
>+			__func__,
>+			t_calc_us);
>+	dml_print(
>+			"DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start    = 0x%0x\n",
>+			__func__,
>+			disp_dlg_regs->min_dst_y_next_start);
>+	dml_print(
>+			"DML_DLG: %s: ref_freq_to_pix_freq                   = %3.2f\n",
>+			__func__,
>+			ref_freq_to_pix_freq);
>+
>+	// -------------------------
>+	// Section 1.15.2.2: Prefetch, Active and TTU
>+	// -------------------------
>+	// Prefetch Calc
>+	// Source
>+	//             dcc_en              = src.dcc;
>+	dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
>+	mode_422 = 0; // FIXME
>+	access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
>+						    //      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);
>+						    //      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);
>+	vp_height_l = src->viewport_height;
>+	vp_width_l = src->viewport_width;
>+	vp_height_c = src->viewport_height_c;
>+	vp_width_c = src->viewport_width_c;
>+
>+	// Scaling
>+	htaps_l = taps->htaps;
>+	htaps_c = taps->htaps_c;
>+	hratio_l = scl->hscl_ratio;
>+	hratio_c = scl->hscl_ratio_c;
>+	vratio_l = scl->vscl_ratio;
>+	vratio_c = scl->vscl_ratio_c;
>+	scl_enable = scl->scl_enable;
>+
>+	line_time_in_us = (htotal / pclk_freq_in_mhz);
>+	swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
>+	dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
>+	swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
>+	dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
>+
>+	meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
>+	meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;
>+	vupdate_offset = dst->vupdate_offset;
>+	vupdate_width = dst->vupdate_width;
>+	vready_offset = dst->vready_offset;
>+
>+	dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
>+	dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
>+
>+	if (scl_enable)
>+		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
>+	else
>+		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
>+
>+	dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter
>+			+ src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
>+
>+	if (dout->dsc_enable) {
>+		double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+
>+		dispclk_delay_subtotal += dsc_delay;
>+	}
>+
>+	pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz
>+			+ dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
>+
>+	vstartup_start = dst->vstartup_start;
>+	if (interlaced) {
>+		if (vstartup_start / 2.0
>+				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
>+				<= vblank_end / 2.0)
>+			disp_dlg_regs->vready_after_vcount0 = 1;
>+		else
>+			disp_dlg_regs->vready_after_vcount0 = 0;
>+	} else {
>+		if (vstartup_start
>+				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
>+				<= vblank_end)
>+			disp_dlg_regs->vready_after_vcount0 = 1;
>+		else
>+			disp_dlg_regs->vready_after_vcount0 = 0;
>+	}
>+
>+	// TODO: Where is this coming from?
>+	if (interlaced)
>+		vstartup_start = vstartup_start / 2;
>+
>+	// TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp?
>+	if (vstartup_start >= min_vblank) {
>+		dml_print(
>+				"WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
>+				__func__,
>+				vblank_start,
>+				vblank_end);
>+		dml_print(
>+				"WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
>+				__func__,
>+				vstartup_start,
>+				min_vblank);
>+		min_vblank = vstartup_start + 1;
>+		dml_print(
>+				"WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
>+				__func__,
>+				vstartup_start,
>+				min_vblank);
>+	}
>+
>+	dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+	dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+
>+	dml_print("DML_DLG: %s: htotal                                 = %d\n", __func__, htotal);
>+	dml_print(
>+			"DML_DLG: %s: pixel_rate_delay_subtotal              = %d\n",
>+			__func__,
>+			pixel_rate_delay_subtotal);
>+	dml_print(
>+			"DML_DLG: %s: dst_x_after_scaler                     = %d\n",
>+			__func__,
>+			dst_x_after_scaler);
>+	dml_print(
>+			"DML_DLG: %s: dst_y_after_scaler                     = %d\n",
>+			__func__,
>+			dst_y_after_scaler);
>+
>+	// Lwait
>+	// TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us?
>+	line_wait = mode_lib->soc.urgent_latency_pixel_data_only_us;
>+	if (cstate_en)
>+		line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
>+	if (pstate_en)
>+		line_wait = dml_max(
>+				mode_lib->soc.dram_clock_change_latency_us
>+						+ mode_lib->soc.urgent_latency_pixel_data_only_us, // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us?
>+				line_wait);
>+	line_wait = line_wait / line_time_in_us;
>+
>+	dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+	dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
>+
>+	dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(
>+			mode_lib,
>+			e2e_pipe_param,
>+			num_pipes,
>+			pipe_idx);
>+	dst_y_per_row_vblank = get_dst_y_per_row_vblank(
>+			mode_lib,
>+			e2e_pipe_param,
>+			num_pipes,
>+			pipe_idx);
>+	dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+	dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+
>+	max_dst_y_per_vm_vblank = 32.0;
>+	max_dst_y_per_row_vblank = 16.0;
>+
>+	// magic!
>+	if (htotal <= 75) {
>+		min_vblank = 300;
>+		max_dst_y_per_vm_vblank = 100.0;
>+		max_dst_y_per_row_vblank = 100.0;
>+	}
>+
>+	dml_print("DML_DLG: %s: dst_y_per_vm_flip    = %3.2f\n", __func__, dst_y_per_vm_flip);
>+	dml_print("DML_DLG: %s: dst_y_per_row_flip   = %3.2f\n", __func__, dst_y_per_row_flip);
>+	dml_print("DML_DLG: %s: dst_y_per_vm_vblank  = %3.2f\n", __func__, dst_y_per_vm_vblank);
>+	dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank);
>+
>+	ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank);
>+	ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
>+
>+	ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
>+	lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank);
>+
>+	dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw);
>+
>+	vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+	vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+
>+	dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l);
>+	dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c);
>+
>+	// Active
>+	req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
>+	req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
>+	meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
>+	meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;
>+	swath_width_pixels_ub_l = 0;
>+	swath_width_pixels_ub_c = 0;
>+	scaler_rec_in_width_l = 0;
>+	scaler_rec_in_width_c = 0;
>+	dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
>+	dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
>+
>+	if (mode_422) {
>+		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element
>+		swath_width_pixels_ub_c = swath_width_ub_c * 2;
>+	} else {
>+		swath_width_pixels_ub_l = swath_width_ub_l * 1;
>+		swath_width_pixels_ub_c = swath_width_ub_c * 1;
>+	}
>+
>+	hscale_pixel_rate_l = 0.;
>+	hscale_pixel_rate_c = 0.;
>+	min_hratio_fact_l = 1.0;
>+	min_hratio_fact_c = 1.0;
>+
>+	if (htaps_l <= 1)
>+		min_hratio_fact_l = 2.0;
>+	else if (htaps_l <= 6) {
>+		if ((hratio_l * 2.0) > 4.0)
>+			min_hratio_fact_l = 4.0;
>+		else
>+			min_hratio_fact_l = hratio_l * 2.0;
>+	} else {
>+		if (hratio_l > 4.0)
>+			min_hratio_fact_l = 4.0;
>+		else
>+			min_hratio_fact_l = hratio_l;
>+	}
>+
>+	hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
>+
>+	if (htaps_c <= 1)
>+		min_hratio_fact_c = 2.0;
>+	else if (htaps_c <= 6) {
>+		if ((hratio_c * 2.0) > 4.0)
>+			min_hratio_fact_c = 4.0;
>+		else
>+			min_hratio_fact_c = hratio_c * 2.0;
>+	} else {
>+		if (hratio_c > 4.0)
>+			min_hratio_fact_c = 4.0;
>+		else
>+			min_hratio_fact_c = hratio_c;
>+	}
>+
>+	hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
>+
>+	refcyc_per_line_delivery_pre_l = 0.;
>+	refcyc_per_line_delivery_pre_c = 0.;
>+	refcyc_per_line_delivery_l = 0.;
>+	refcyc_per_line_delivery_c = 0.;
>+
>+	refcyc_per_req_delivery_pre_l = 0.;
>+	refcyc_per_req_delivery_pre_c = 0.;
>+	refcyc_per_req_delivery_l = 0.;
>+	refcyc_per_req_delivery_c = 0.;
>+
>+	full_recout_width = 0;
>+	// In ODM
>+	if (src->is_hsplit) {
>+		// This "hack"  is only allowed (and valid) for MPC combine. In ODM
>+		// combine, you MUST specify the full_recout_width...according to Oswin
>+		if (dst->full_recout_width == 0 && !dst->odm_combine) {
>+			dml_print(
>+					"DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",
>+					__func__);
>+			full_recout_width = dst->recout_width * 2; // assume half split for dcn1
>+		} else
>+			full_recout_width = dst->full_recout_width;
>+	} else
>+		full_recout_width = dst->recout_width;
>+
>+	// As of DCN2, mpc_combine and odm_combine are mutually exclusive
>+	refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(
>+			mode_lib,
>+			refclk_freq_in_mhz,
>+			pclk_freq_in_mhz,
>+			dst->odm_combine,
>+			full_recout_width,
>+			dst->hactive,
>+			vratio_pre_l,
>+			hscale_pixel_rate_l,
>+			swath_width_pixels_ub_l,
>+			1); // per line
>+
>+	refcyc_per_line_delivery_l = get_refcyc_per_delivery(
>+			mode_lib,
>+			refclk_freq_in_mhz,
>+			pclk_freq_in_mhz,
>+			dst->odm_combine,
>+			full_recout_width,
>+			dst->hactive,
>+			vratio_l,
>+			hscale_pixel_rate_l,
>+			swath_width_pixels_ub_l,
>+			1); // per line
>+
>+	dml_print("DML_DLG: %s: full_recout_width              = %d\n", __func__, full_recout_width);
>+	dml_print(
>+			"DML_DLG: %s: hscale_pixel_rate_l            = %3.2f\n",
>+			__func__,
>+			hscale_pixel_rate_l);
>+	dml_print(
>+			"DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",
>+			__func__,
>+			refcyc_per_line_delivery_pre_l);
>+	dml_print(
>+			"DML_DLG: %s: refcyc_per_line_delivery_l     = %3.2f\n",
>+			__func__,
>+			refcyc_per_line_delivery_l);
>+
>+	if (dual_plane) {
>+		refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(
>+				mode_lib,
>+				refclk_freq_in_mhz,
>+				pclk_freq_in_mhz,
>+				dst->odm_combine,
>+				full_recout_width,
>+				dst->hactive,
>+				vratio_pre_c,
>+				hscale_pixel_rate_c,
>+				swath_width_pixels_ub_c,
>+				1); // per line
>+
>+		refcyc_per_line_delivery_c = get_refcyc_per_delivery(
>+				mode_lib,
>+				refclk_freq_in_mhz,
>+				pclk_freq_in_mhz,
>+				dst->odm_combine,
>+				full_recout_width,
>+				dst->hactive,
>+				vratio_c,
>+				hscale_pixel_rate_c,
>+				swath_width_pixels_ub_c,
>+				1);  // per line
>+
>+		dml_print(
>+				"DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",
>+				__func__,
>+				refcyc_per_line_delivery_pre_c);
>+		dml_print(
>+				"DML_DLG: %s: refcyc_per_line_delivery_c     = %3.2f\n",
>+				__func__,
>+				refcyc_per_line_delivery_c);
>+	}
>+
>+	// TTU - Luma / Chroma
>+	if (access_dir) {  // vertical access
>+		scaler_rec_in_width_l = vp_height_l;
>+		scaler_rec_in_width_c = vp_height_c;
>+	} else {
>+		scaler_rec_in_width_l = vp_width_l;
>+		scaler_rec_in_width_c = vp_width_c;
>+	}
>+
>+	refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(
>+			mode_lib,
>+			refclk_freq_in_mhz,
>+			pclk_freq_in_mhz,
>+			dst->odm_combine,
>+			full_recout_width,
>+			dst->hactive,
>+			vratio_pre_l,
>+			hscale_pixel_rate_l,
>+			scaler_rec_in_width_l,
>+			req_per_swath_ub_l);  // per req
>+	refcyc_per_req_delivery_l = get_refcyc_per_delivery(
>+			mode_lib,
>+			refclk_freq_in_mhz,
>+			pclk_freq_in_mhz,
>+			dst->odm_combine,
>+			full_recout_width,
>+			dst->hactive,
>+			vratio_l,
>+			hscale_pixel_rate_l,
>+			scaler_rec_in_width_l,
>+			req_per_swath_ub_l);  // per req
>+
>+	dml_print(
>+			"DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",
>+			__func__,
>+			refcyc_per_req_delivery_pre_l);
>+	dml_print(
>+			"DML_DLG: %s: refcyc_per_req_delivery_l     = %3.2f\n",
>+			__func__,
>+			refcyc_per_req_delivery_l);
>+
>+	ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
>+	ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
>+
>+	if (dual_plane) {
>+		refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(
>+				mode_lib,
>+				refclk_freq_in_mhz,
>+				pclk_freq_in_mhz,
>+				dst->odm_combine,
>+				full_recout_width,
>+				dst->hactive,
>+				vratio_pre_c,
>+				hscale_pixel_rate_c,
>+				scaler_rec_in_width_c,
>+				req_per_swath_ub_c);  // per req
>+		refcyc_per_req_delivery_c = get_refcyc_per_delivery(
>+				mode_lib,
>+				refclk_freq_in_mhz,
>+				pclk_freq_in_mhz,
>+				dst->odm_combine,
>+				full_recout_width,
>+				dst->hactive,
>+				vratio_c,
>+				hscale_pixel_rate_c,
>+				scaler_rec_in_width_c,
>+				req_per_swath_ub_c);  // per req
>+
>+		dml_print(
>+				"DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",
>+				__func__,
>+				refcyc_per_req_delivery_pre_c);
>+		dml_print(
>+				"DML_DLG: %s: refcyc_per_req_delivery_c     = %3.2f\n",
>+				__func__,
>+				refcyc_per_req_delivery_c);
>+
>+		ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
>+		ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
>+	}
>+
>+	// XFC
>+	xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
>+	xfc_precharge_delay = get_xfc_precharge_delay(
>+			mode_lib,
>+			e2e_pipe_param,
>+			num_pipes,
>+			pipe_idx);
>+	xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(
>+			mode_lib,
>+			e2e_pipe_param,
>+			num_pipes,
>+			pipe_idx);
>+	xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;
>+	xfc_prefetch_margin = get_xfc_prefetch_margin(
>+			mode_lib,
>+			e2e_pipe_param,
>+			num_pipes,
>+			pipe_idx);
>+
>+	// TTU - Cursor
>+	refcyc_per_req_delivery_pre_cur0 = 0.0;
>+	refcyc_per_req_delivery_cur0 = 0.0;
>+	if (src->num_cursors > 0) {
>+		calculate_ttu_cursor(
>+				mode_lib,
>+				&refcyc_per_req_delivery_pre_cur0,
>+				&refcyc_per_req_delivery_cur0,
>+				refclk_freq_in_mhz,
>+				ref_freq_to_pix_freq,
>+				hscale_pixel_rate_l,
>+				scl->hscl_ratio,
>+				vratio_pre_l,
>+				vratio_l,
>+				src->cur0_src_width,
>+				(enum cursor_bpp) (src->cur0_bpp));
>+	}
>+
>+	refcyc_per_req_delivery_pre_cur1 = 0.0;
>+	refcyc_per_req_delivery_cur1 = 0.0;
>+	if (src->num_cursors > 1) {
>+		calculate_ttu_cursor(
>+				mode_lib,
>+				&refcyc_per_req_delivery_pre_cur1,
>+				&refcyc_per_req_delivery_cur1,
>+				refclk_freq_in_mhz,
>+				ref_freq_to_pix_freq,
>+				hscale_pixel_rate_l,
>+				scl->hscl_ratio,
>+				vratio_pre_l,
>+				vratio_l,
>+				src->cur1_src_width,
>+				(enum cursor_bpp) (src->cur1_bpp));
>+	}
>+
>+	// TTU - Misc
>+	// all hard-coded
>+
>+	// Assignment to register structures
>+	disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
>+	disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
>+	ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
>+	disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
>+	disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
>+	disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
>+	disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
>+	disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
>+
>+	disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
>+	disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
>+
>+	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank  = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank);
>+	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank);
>+	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip    = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip);
>+	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip   = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip);
>+
>+	disp_dlg_regs->refcyc_per_pte_group_vblank_l =
>+			(unsigned int) (dst_y_per_row_vblank * (double) htotal
>+					* ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
>+	ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
>+
>+	if (dual_plane) {
>+		disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank
>+				* (double) htotal * ref_freq_to_pix_freq
>+				/ (double) dpte_groups_per_row_ub_c);
>+		ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
>+				< (unsigned int)dml_pow(2, 13));
>+	}
>+
>+	disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
>+			(unsigned int) (dst_y_per_row_vblank * (double) htotal
>+					* ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
>+	ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
>+
>+	disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
>+			disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
>+
>+	disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
>+			* ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
>+	disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
>+			* ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
>+
>+	if (dual_plane) {
>+		disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip
>+				* htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
>+		disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip
>+				* htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
>+	}
>+
>+	disp_dlg_regs->refcyc_per_vm_group_vblank   = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
>+	disp_dlg_regs->refcyc_per_vm_group_flip     = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;
>+	disp_dlg_regs->refcyc_per_vm_req_vblank     = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;;
>+	disp_dlg_regs->refcyc_per_vm_req_flip       = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;;
>+
>+	// Clamp to max for now
>+	if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23))
>+		disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;
>+
>+	if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23))
>+		disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;
>+
>+	if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23))
>+		disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;
>+
>+	if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23))
>+		disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;
>+	disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l
>+			/ (double) vratio_l * dml_pow(2, 2));
>+	ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
>+
>+	if (dual_plane) {
>+		disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c
>+				/ (double) vratio_c * dml_pow(2, 2));
>+		if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
>+			dml_print(
>+					"DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
>+					__func__,
>+					disp_dlg_regs->dst_y_per_pte_row_nom_c,
>+					(unsigned int)dml_pow(2, 17) - 1);
>+		}
>+	}
>+
>+	disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
>+			/ (double) vratio_l * dml_pow(2, 2));
>+	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
>+
>+	disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
>+
>+	dml_print(
>+			"DML: Trow: %fus\n",
>+			line_time_in_us * (double)dpte_row_height_l / (double)vratio_l);
>+
>+	disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l
>+			/ (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
>+			/ (double) dpte_groups_per_row_ub_l);
>+	if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
>+		disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
>+	disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l
>+			/ (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
>+			/ (double) meta_chunks_per_row_ub_l);
>+	if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
>+		disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
>+
>+	if (dual_plane) {
>+		disp_dlg_regs->refcyc_per_pte_group_nom_c =
>+				(unsigned int) ((double) dpte_row_height_c / (double) vratio_c
>+						* (double) htotal * ref_freq_to_pix_freq
>+						/ (double) dpte_groups_per_row_ub_c);
>+		if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
>+			disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
>+
>+		// TODO: Is this the right calculation? Does htotal need to be halved?
>+		disp_dlg_regs->refcyc_per_meta_chunk_nom_c =
>+				(unsigned int) ((double) meta_row_height_c / (double) vratio_c
>+						* (double) htotal * ref_freq_to_pix_freq
>+						/ (double) meta_chunks_per_row_ub_c);
>+		if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
>+			disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
>+	}
>+
>+	disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(
>+			refcyc_per_line_delivery_pre_l, 1);
>+	disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(
>+			refcyc_per_line_delivery_l, 1);
>+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));
>+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
>+
>+	disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(
>+			refcyc_per_line_delivery_pre_c, 1);
>+	disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(
>+			refcyc_per_line_delivery_c, 1);
>+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));
>+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
>+
>+	disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
>+	disp_dlg_regs->dst_y_offset_cur0 = 0;
>+	disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
>+	disp_dlg_regs->dst_y_offset_cur1 = 0;
>+
>+	disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay;
>+	disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay;
>+	disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency;
>+	disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(
>+			xfc_prefetch_margin * refclk_freq_in_mhz, 1);
>+
>+	// slave has to have this value also set to off
>+	if (src->xfc_enable && !src->xfc_slave)
>+		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
>+	else
>+		disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
>+
>+	disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
>+			* dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
>+			* dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c
>+			* dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
>+			* dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
>+			(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0
>+			* dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 =
>+			(unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
>+	disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1
>+			* dml_pow(2, 10));
>+	disp_ttu_regs->qos_level_low_wm = 0;
>+	ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
>+	disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
>+			* ref_freq_to_pix_freq);
>+	ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
>+
>+	disp_ttu_regs->qos_level_flip = 14;
>+	disp_ttu_regs->qos_level_fixed_l = 8;
>+	disp_ttu_regs->qos_level_fixed_c = 8;
>+	disp_ttu_regs->qos_level_fixed_cur0 = 8;
>+	disp_ttu_regs->qos_ramp_disable_l = 0;
>+	disp_ttu_regs->qos_ramp_disable_c = 0;
>+	disp_ttu_regs->qos_ramp_disable_cur0 = 0;
>+
>+	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
>+	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
>+
>+	print__ttu_regs_st(mode_lib, *disp_ttu_regs);
>+	print__dlg_regs_st(mode_lib, *disp_dlg_regs);
>+}
>+
>+void dml21_rq_dlg_get_dlg_reg(
>+		struct display_mode_lib *mode_lib,
>+		display_dlg_regs_st *dlg_regs,
>+		display_ttu_regs_st *ttu_regs,
>+		display_e2e_pipe_params_st *e2e_pipe_param,
>+		const unsigned int num_pipes,
>+		const unsigned int pipe_idx,
>+		const bool cstate_en,
>+		const bool pstate_en,
>+		const bool vm_en,
>+		const bool ignore_viewport_pos,
>+		const bool immediate_flip_support)
>+{
>+	display_rq_params_st rq_param = {0};
>+	display_dlg_sys_params_st dlg_sys_param = {0};
>+
>+	// Get watermark and Tex.
>+	dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
>+	dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(
>+			mode_lib,
>+			e2e_pipe_param,
>+			num_pipes);
>+	dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
>+	dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
>+	dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
>+	dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
>+	dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(
>+			mode_lib,
>+			e2e_pipe_param,
>+			num_pipes);
>+	dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(
>+			mode_lib,
>+			e2e_pipe_param,
>+			num_pipes);
>+	dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
>+			/ dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
>+
>+	print__dlg_sys_params_st(mode_lib, dlg_sys_param);
>+
>+	// system parameter calculation done
>+
>+	dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
>+	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe);
>+	dml_rq_dlg_get_dlg_params(
>+			mode_lib,
>+			e2e_pipe_param,
>+			num_pipes,
>+			pipe_idx,
>+			dlg_regs,
>+			ttu_regs,
>+			rq_param.dlg,
>+			dlg_sys_param,
>+			cstate_en,
>+			pstate_en);
>+	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
>+}
>+
>+void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param)
>+{
>+	memset(arb_param, 0, sizeof(*arb_param));
>+	arb_param->max_req_outstanding = 256;
>+	arb_param->min_req_outstanding = 68;
>+	arb_param->sat_level_us = 60;
>+}
>+
>+static void calculate_ttu_cursor(
>+		struct display_mode_lib *mode_lib,
>+		double *refcyc_per_req_delivery_pre_cur,
>+		double *refcyc_per_req_delivery_cur,
>+		double refclk_freq_in_mhz,
>+		double ref_freq_to_pix_freq,
>+		double hscale_pixel_rate_l,
>+		double hscl_ratio,
>+		double vratio_pre_l,
>+		double vratio_l,
>+		unsigned int cur_width,
>+		enum cursor_bpp cur_bpp)
>+{
>+	unsigned int cur_src_width = cur_width;
>+	unsigned int cur_req_size = 0;
>+	unsigned int cur_req_width = 0;
>+	double cur_width_ub = 0.0;
>+	double cur_req_per_width = 0.0;
>+	double hactive_cur = 0.0;
>+
>+	ASSERT(cur_src_width <= 256);
>+
>+	*refcyc_per_req_delivery_pre_cur = 0.0;
>+	*refcyc_per_req_delivery_cur = 0.0;
>+	if (cur_src_width > 0) {
>+		unsigned int cur_bit_per_pixel = 0;
>+
>+		if (cur_bpp == dm_cur_2bit) {
>+			cur_req_size = 64; // byte
>+			cur_bit_per_pixel = 2;
>+		} else { // 32bit
>+			cur_bit_per_pixel = 32;
>+			if (cur_src_width >= 1 && cur_src_width <= 16)
>+				cur_req_size = 64;
>+			else if (cur_src_width >= 17 && cur_src_width <= 31)
>+				cur_req_size = 128;
>+			else
>+				cur_req_size = 256;
>+		}
>+
>+		cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
>+		cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
>+				* (double) cur_req_width;
>+		cur_req_per_width = cur_width_ub / (double) cur_req_width;
>+		hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
>+
>+		if (vratio_pre_l <= 1.0) {
>+			*refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq
>+					/ (double) cur_req_per_width;
>+		} else {
>+			*refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz
>+					* (double) cur_src_width / hscale_pixel_rate_l
>+					/ (double) cur_req_per_width;
>+		}
>+
>+		ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
>+
>+		if (vratio_l <= 1.0) {
>+			*refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq
>+					/ (double) cur_req_per_width;
>+		} else {
>+			*refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz
>+					* (double) cur_src_width / hscale_pixel_rate_l
>+					/ (double) cur_req_per_width;
>+		}
>+
>+		dml_print(
>+				"DML_DLG: %s: cur_req_width                     = %d\n",
>+				__func__,
>+				cur_req_width);
>+		dml_print(
>+				"DML_DLG: %s: cur_width_ub                      = %3.2f\n",
>+				__func__,
>+				cur_width_ub);
>+		dml_print(
>+				"DML_DLG: %s: cur_req_per_width                 = %3.2f\n",
>+				__func__,
>+				cur_req_per_width);
>+		dml_print(
>+				"DML_DLG: %s: hactive_cur                       = %3.2f\n",
>+				__func__,
>+				hactive_cur);
>+		dml_print(
>+				"DML_DLG: %s: refcyc_per_req_delivery_pre_cur   = %3.2f\n",
>+				__func__,
>+				*refcyc_per_req_delivery_pre_cur);
>+		dml_print(
>+				"DML_DLG: %s: refcyc_per_req_delivery_cur       = %3.2f\n",
>+				__func__,
>+				*refcyc_per_req_delivery_cur);
>+
>+		ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
>+	}
>+}
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h	2019-08-31 15:01:11.868736169 -0500
>@@ -0,0 +1,73 @@
>+/*
>+ * Copyright 2017 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifndef __DML21_DISPLAY_RQ_DLG_CALC_H__
>+#define __DML21_DISPLAY_RQ_DLG_CALC_H__
>+
>+#include "../dml_common_defs.h"
>+#include "../display_rq_dlg_helpers.h"
>+
>+struct display_mode_lib;
>+
>+
>+// Function: dml_rq_dlg_get_rq_reg
>+//  Main entry point for test to get the register values out of this DML class.
>+//  This function calls <get_rq_param> and <extract_rq_regs> functions to calculate
>+//  and then populate the rq_regs struct
>+// Input:
>+//  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
>+// Output:
>+//  rq_regs - struct that holds all the RQ registers field value.
>+//            See also: <display_rq_regs_st>
>+void dml21_rq_dlg_get_rq_reg(
>+		struct display_mode_lib *mode_lib,
>+		display_rq_regs_st *rq_regs,
>+		const display_pipe_params_st pipe_param);
>+
>+// Function: dml_rq_dlg_get_dlg_reg
>+//   Calculate and return DLG and TTU register struct given the system setting
>+// Output:
>+//  dlg_regs - output DLG register struct
>+//  ttu_regs - output DLG TTU register struct
>+// Input:
>+//  e2e_pipe_param - "compacted" array of e2e pipe param struct
>+//  num_pipes - num of active "pipe" or "route"
>+//  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
>+//  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
>+//           Added for legacy or unrealistic timing tests.
>+void dml21_rq_dlg_get_dlg_reg(
>+		struct display_mode_lib *mode_lib,
>+		display_dlg_regs_st *dlg_regs,
>+		display_ttu_regs_st *ttu_regs,
>+		display_e2e_pipe_params_st *e2e_pipe_param,
>+		const unsigned int num_pipes,
>+		const unsigned int pipe_idx,
>+		const bool cstate_en,
>+		const bool pstate_en,
>+		const bool vm_en,
>+		const bool ignore_viewport_pos,
>+		const bool immediate_flip_support);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h	2019-08-31 15:01:11.868736169 -0500
>@@ -37,11 +37,14 @@
> 	dm_444_64 = 2,
> 	dm_420_8 = 3,
> 	dm_420_10 = 4,
>-	dm_422_8 = 5,
>-	dm_422_10 = 6,
>-	dm_444_8 = 7,
>+	dm_420_12 = 5,
>+	dm_422_8 = 6,
>+	dm_422_10 = 7,
>+	dm_444_8 = 8,
> 	dm_mono_8 = dm_444_8,
>-	dm_mono_16 = dm_444_16
>+	dm_mono_16 = dm_444_16,
>+	dm_rgbe = 9,
>+	dm_rgbe_alpha = 10,
> };
> enum output_bpc_class {
> 	dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
>@@ -83,7 +86,7 @@
> 	dm_sw_var_d_x = 30,
> 	dm_sw_64kb_r_x,
> 	dm_sw_gfx7_2d_thin_lvp,
>-	dm_sw_gfx7_2d_thin_gl
>+	dm_sw_gfx7_2d_thin_gl,
> };
> enum lb_depth {
> 	dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
>@@ -112,7 +115,8 @@
> enum mpc_combine_affinity {
> 	dm_mpc_always_when_possible,
> 	dm_mpc_reduce_voltage,
>-	dm_mpc_reduce_voltage_and_clocks
>+	dm_mpc_reduce_voltage_and_clocks,
>+	dm_mpc_never
> };
> 
> enum self_refresh_affinity {
>@@ -157,4 +161,10 @@
> 	dm_whole_buffer_for_single_stream_interleave,
> };
> 
>+enum odm_combine_mode {
>+	dm_odm_combine_mode_disabled,
>+	dm_odm_combine_mode_2to1,
>+	dm_odm_combine_mode_4to1,
>+};
>+
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c	2019-08-31 15:01:11.868736169 -0500
>@@ -28,6 +28,12 @@
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> #include "dcn20/display_mode_vba_20.h"
> #include "dcn20/display_rq_dlg_calc_20.h"
>+#include "dcn20/display_mode_vba_20v2.h"
>+#include "dcn20/display_rq_dlg_calc_20v2.h"
>+#endif
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+#include "dcn21/display_mode_vba_21.h"
>+#include "dcn21/display_rq_dlg_calc_21.h"
> #endif
> 
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>@@ -37,6 +43,22 @@
> 	.rq_dlg_get_dlg_reg = dml20_rq_dlg_get_dlg_reg,
> 	.rq_dlg_get_rq_reg = dml20_rq_dlg_get_rq_reg
> };
>+
>+const struct dml_funcs dml20v2_funcs = {
>+	.validate = dml20v2_ModeSupportAndSystemConfigurationFull,
>+	.recalculate = dml20v2_recalculate,
>+	.rq_dlg_get_dlg_reg = dml20v2_rq_dlg_get_dlg_reg,
>+	.rq_dlg_get_rq_reg = dml20v2_rq_dlg_get_rq_reg
>+};
>+#endif
>+
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+const struct dml_funcs dml21_funcs = {
>+        .validate = dml21_ModeSupportAndSystemConfigurationFull,
>+        .recalculate = dml21_recalculate,
>+        .rq_dlg_get_dlg_reg = dml21_rq_dlg_get_dlg_reg,
>+        .rq_dlg_get_rq_reg = dml21_rq_dlg_get_rq_reg
>+};
> #endif
> 
> void dml_init_instance(struct display_mode_lib *lib,
>@@ -52,7 +74,16 @@
> 	case DML_PROJECT_NAVI10:
> 		lib->funcs = dml20_funcs;
> 		break;
>+	case DML_PROJECT_NAVI10v2:
>+		lib->funcs = dml20v2_funcs;
>+		break;
> #endif
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+        case DML_PROJECT_DCN21:
>+                lib->funcs = dml21_funcs;
>+                break;
>+#endif
>+
> 	default:
> 		break;
> 	}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h	2019-08-31 15:01:11.868736169 -0500
>@@ -36,6 +36,10 @@
> 	DML_PROJECT_RAVEN1,
> #ifdef CONFIG_DRM_AMD_DC_DCN2_0
> 	DML_PROJECT_NAVI10,
>+	DML_PROJECT_NAVI10v2,
>+#endif
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+	DML_PROJECT_DCN21,
> #endif
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h	2019-08-31 15:01:11.868736169 -0500
>@@ -100,6 +100,7 @@
> 	unsigned int vmm_page_size_bytes;
> 	unsigned int hostvm_min_page_size_bytes;
> 	double dram_clock_change_latency_us;
>+	double dummy_pstate_latency_us;
> 	double writeback_dram_clock_change_latency_us;
> 	unsigned int return_bus_width_bytes;
> 	unsigned int voltage_override;
>@@ -108,6 +109,9 @@
> 	int use_urgent_burst_bw;
> 	unsigned int num_states;
> 	struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES];
>+	bool do_urgent_latency_adjustment;
>+	double urgent_latency_adjustment_fabric_clock_component_us;
>+	double urgent_latency_adjustment_fabric_clock_reference_mhz;
> };
> 
> struct _vcs_dpi_ip_params_st {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c	2019-08-31 15:01:11.868736169 -0500
>@@ -262,6 +262,13 @@
> 		//mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mhz;
> 		mode_lib->vba.MaxDispclk[i] = soc->clock_limits[i].dispclk_mhz;
> 	}
>+
>+	mode_lib->vba.DoUrgentLatencyAdjustment =
>+		soc->do_urgent_latency_adjustment;
>+	mode_lib->vba.UrgentLatencyAdjustmentFabricClockComponent =
>+		soc->urgent_latency_adjustment_fabric_clock_component_us;
>+	mode_lib->vba.UrgentLatencyAdjustmentFabricClockReference =
>+		soc->urgent_latency_adjustment_fabric_clock_reference_mhz;
> }
> 
> static void fetch_ip_params(struct display_mode_lib *mode_lib)
>@@ -385,8 +392,10 @@
> 				src->viewport_y_c;
> 		mode_lib->vba.PitchY[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch;
> 		mode_lib->vba.SurfaceHeightY[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height;
>+		mode_lib->vba.SurfaceWidthY[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width;
> 		mode_lib->vba.PitchC[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch_c;
> 		mode_lib->vba.SurfaceHeightC[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height_c;
>+		mode_lib->vba.SurfaceWidthC[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width_c;
> 		mode_lib->vba.DCCMetaPitchY[mode_lib->vba.NumberOfActivePlanes] = src->meta_pitch;
> 		mode_lib->vba.DCCMetaPitchC[mode_lib->vba.NumberOfActivePlanes] = src->meta_pitch_c;
> 		mode_lib->vba.HRatio[mode_lib->vba.NumberOfActivePlanes] = scl->hscl_ratio;
>@@ -457,6 +466,10 @@
> 				dout->wb.wb_dst_width;
> 		mode_lib->vba.WritebackDestinationHeight[mode_lib->vba.NumberOfActivePlanes] =
> 				dout->wb.wb_dst_height;
>+		mode_lib->vba.WritebackHRatio[mode_lib->vba.NumberOfActivePlanes] =
>+				dout->wb.wb_hratio;
>+		mode_lib->vba.WritebackVRatio[mode_lib->vba.NumberOfActivePlanes] =
>+				dout->wb.wb_vratio;
> 		mode_lib->vba.WritebackPixelFormat[mode_lib->vba.NumberOfActivePlanes] =
> 				(enum source_format_class) (dout->wb.wb_pixel_format);
> 		mode_lib->vba.WritebackHTaps[mode_lib->vba.NumberOfActivePlanes] =
>@@ -568,6 +581,7 @@
> 		if (src->is_hsplit) {
> 			for (k = j + 1; k < mode_lib->vba.cache_num_pipes; ++k) {
> 				display_pipe_source_params_st *src_k = &pipes[k].pipe.src;
>+				display_pipe_dest_params_st *dst_k = &pipes[k].pipe.dest;
> 
> 				if (src_k->is_hsplit && !visited[k]
> 						&& src->hsplit_grp == src_k->hsplit_grp) {
>@@ -575,12 +589,15 @@
> 							mode_lib->vba.NumberOfActivePlanes;
> 					mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes]++;
> 					if (mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes]
>-							== dm_horz)
>+							== dm_horz) {
> 						mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] +=
> 								src_k->viewport_width;
>-					else
>+						mode_lib->vba.ScalerRecoutWidth[mode_lib->vba.NumberOfActivePlanes] +=
>+								dst_k->recout_width;
>+					} else {
> 						mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] +=
> 								src_k->viewport_height;
>+					}
> 
> 					visited[k] = true;
> 				}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h	2019-08-31 15:01:11.869736169 -0500
>@@ -290,6 +290,7 @@
> 	double PixelClock[DC__NUM_DPP__MAX];
> 	double PixelClockBackEnd[DC__NUM_DPP__MAX];
> 	bool DCCEnable[DC__NUM_DPP__MAX];
>+	bool FECEnable[DC__NUM_DPP__MAX];
> 	unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
> 	unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
> 	enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
>@@ -317,6 +318,7 @@
> 	double DCCRate[DC__NUM_DPP__MAX];
> 	double AverageDCCCompressionRate;
> 	bool ODMCombineEnabled[DC__NUM_DPP__MAX];
>+	enum odm_combine_mode ODMCombineTypeEnabled[DC__NUM_DPP__MAX];
> 	double OutputBpp[DC__NUM_DPP__MAX];
> 	bool DSCEnabled[DC__NUM_DPP__MAX];
> 	unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
>@@ -395,6 +397,7 @@
> 	double FabricClockPerState[DC__VOLTAGE_STATES + 1];
> 	double SOCCLKPerState[DC__VOLTAGE_STATES + 1];
> 	double PHYCLKPerState[DC__VOLTAGE_STATES + 1];
>+	double DTBCLKPerState[DC__VOLTAGE_STATES + 1];
> 	double MaxDppclk[DC__VOLTAGE_STATES + 1];
> 	double MaxDSCCLK[DC__VOLTAGE_STATES + 1];
> 	double DRAMSpeedPerState[DC__VOLTAGE_STATES + 1];
>@@ -488,6 +491,7 @@
> 	unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
> 	int NoOfDPPThisState[DC__NUM_DPP__MAX];
> 	bool ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
>+	enum odm_combine_mode ODMCombineTypeEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
> 	unsigned int SwathWidthYThisState[DC__NUM_DPP__MAX];
> 	unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
> 	unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
>@@ -513,6 +517,7 @@
> 	bool DIOSupport[DC__VOLTAGE_STATES + 1];
> 	bool NotEnoughDSCUnits[DC__VOLTAGE_STATES + 1];
> 	bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
>+	bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
> 	double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES + 1];
> 	bool ROBSupport[DC__VOLTAGE_STATES + 1];
> 	bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES + 1][2];
>@@ -605,6 +610,7 @@
> 	double         MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
> 	double         MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
> 	bool odm_combine_dummy[DC__NUM_DPP__MAX];
>+	enum odm_combine_mode odm_combine_mode_dummy[DC__NUM_DPP__MAX];
> 	double         dummy1[DC__NUM_DPP__MAX];
> 	double         dummy2[DC__NUM_DPP__MAX];
> 	double         dummy3[DC__NUM_DPP__MAX];
>@@ -625,6 +631,11 @@
> 	unsigned int        dummyinteger10;
> 	unsigned int        dummyinteger11;
> 	unsigned int        dummyinteger12;
>+	unsigned int        dummyintegerarr1[DC__NUM_DPP__MAX];
>+	unsigned int        dummyintegerarr2[DC__NUM_DPP__MAX];
>+	unsigned int        dummyintegerarr3[DC__NUM_DPP__MAX];
>+	unsigned int        dummyintegerarr4[DC__NUM_DPP__MAX];
>+	long                dummylongarr1[DC__NUM_DPP__MAX];
> 	bool           dummysinglestring;
> 	bool           SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
> 	double         PlaneRequiredDISPCLKWithODMCombine2To1;
>@@ -633,6 +644,7 @@
> 	bool           LinkDSCEnable;
> 	bool           ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES + 1];
> 	bool ODMCombineEnableThisState[DC__NUM_DPP__MAX];
>+	enum odm_combine_mode ODMCombineEnableTypeThisState[DC__NUM_DPP__MAX];
> 	unsigned int   SwathWidthCThisState[DC__NUM_DPP__MAX];
> 	bool           ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
> 	double         AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
>@@ -641,6 +653,7 @@
> 	unsigned int NotEnoughUrgentLatencyHiding;
> 	unsigned int NotEnoughUrgentLatencyHidingPre;
> 	long PTEBufferSizeInRequestsForLuma;
>+	long PTEBufferSizeInRequestsForChroma;
> 
> 	// Missing from VBA
> 	long dpte_group_bytes_chroma;
>@@ -787,6 +800,9 @@
> 	unsigned int PDEProcessingBufIn64KBReqs;
> 
> 	double MaxTotalVActiveRDBandwidth;
>+	bool DoUrgentLatencyAdjustment;
>+	double UrgentLatencyAdjustmentFabricClockComponent;
>+	double UrgentLatencyAdjustmentFabricClockReference;
> 	double MinUrgentLatencySupportUs;
> 	double MinFullDETBufferingTime;
> 	double AverageReadBandwidthGBytePerSecond;
>@@ -801,6 +817,8 @@
> 	bool ModeIsSupported;
> 	bool ODMCombine4To1Supported;
> 
>+	unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
>+	unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
> 	unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
> 	unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
> 	unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dml/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dml/Makefile	2019-08-31 15:01:11.867736169 -0500
>@@ -32,12 +32,22 @@
> 
> dml_ccflags := -mhard-float -msse $(cc_stack_align)
> 
>+ifdef CONFIG_CC_IS_CLANG
>+dml_ccflags += -msse2
>+endif
>+
> CFLAGS_display_mode_lib.o := $(dml_ccflags)
> 
> ifdef CONFIG_DRM_AMD_DC_DCN2_0
> CFLAGS_display_mode_vba.o := $(dml_ccflags)
> CFLAGS_display_mode_vba_20.o := $(dml_ccflags)
> CFLAGS_display_rq_dlg_calc_20.o := $(dml_ccflags)
>+CFLAGS_display_mode_vba_20v2.o := $(dml_ccflags)
>+CFLAGS_display_rq_dlg_calc_20v2.o := $(dml_ccflags)
>+endif
>+ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+CFLAGS_display_mode_vba_21.o := $(dml_ccflags)
>+CFLAGS_display_rq_dlg_calc_21.o := $(dml_ccflags)
> endif
> ifdef CONFIG_DRM_AMD_DCN3AG
> CFLAGS_display_mode_vba_3ag.o := $(dml_ccflags)
>@@ -51,7 +61,12 @@
> 
> ifdef CONFIG_DRM_AMD_DC_DCN2_0
> DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o
>+DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
> endif
>+ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
>+endif
>+
> 
> AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h	2019-08-31 15:01:11.867736169 -0500
>@@ -44,6 +44,9 @@
> #ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0
> 	PP_SMU_VER_NV,
> #endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	PP_SMU_VER_RN,
>+#endif
> 
> 	PP_SMU_VER_MAX
> };
>@@ -246,6 +249,47 @@
> };
> #endif
> 
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+
>+#define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8
>+#define PP_SMU_NUM_DCFCLK_DPM_LEVELS  4
>+#define PP_SMU_NUM_FCLK_DPM_LEVELS    4
>+#define PP_SMU_NUM_MEMCLK_DPM_LEVELS  4
>+
>+struct dpm_clock {
>+  uint32_t  Freq;    // In MHz
>+  uint32_t  Vol;     // Millivolts with 2 fractional bits
>+};
>+
>+
>+/* this is a copy of the structure defined in smuxx_driver_if.h*/
>+struct dpm_clocks {
>+	struct dpm_clock DcfClocks[PP_SMU_NUM_DCFCLK_DPM_LEVELS];
>+	struct dpm_clock SocClocks[PP_SMU_NUM_SOCCLK_DPM_LEVELS];
>+	struct dpm_clock FClocks[PP_SMU_NUM_FCLK_DPM_LEVELS];
>+	struct dpm_clock MemClocks[PP_SMU_NUM_MEMCLK_DPM_LEVELS];
>+};
>+
>+
>+struct pp_smu_funcs_rn {
>+	struct pp_smu pp_smu;
>+
>+	/*
>+	 * reader and writer WM's are sent together as part of one table
>+	 *
>+	 * PPSMC_MSG_SetDriverDramAddrHigh
>+	 * PPSMC_MSG_SetDriverDramAddrLow
>+	 * PPSMC_MSG_TransferTableDram2Smu
>+	 *
>+	 */
>+	enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
>+			struct pp_smu_wm_range_sets *ranges);
>+
>+	enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,
>+			struct dpm_clocks *clock_table);
>+};
>+#endif
>+
> struct pp_smu_funcs {
> 	struct pp_smu ctx;
> 	union {
>@@ -253,6 +297,9 @@
> #ifndef CONFIG_TRIM_DRM_AMD_DC_DCN2_0
> 		struct pp_smu_funcs_nv nv_funcs;
> #endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+		struct pp_smu_funcs_rn rn_funcs;
>+#endif
> 
> 	};
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dm_services.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dm_services.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dm_services.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dm_services.h	2019-08-31 15:01:11.867736169 -0500
>@@ -151,6 +151,7 @@
> 	unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
> 	const char *func_name, int line);
> 
>+unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...);
> 
> /* These macros need to be used with soc15 registers in order to retrieve
>  * the actual offset.
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c	2019-08-31 15:01:11.869736169 -0500
>@@ -28,6 +28,23 @@
> #include "dsc.h"
> #include <drm/drm_dp_helper.h>
> 
>+struct dc_dsc_policy {
>+	bool use_min_slices_h;
>+	int max_slices_h; // Maximum available if 0
>+	int min_sice_height; // Must not be less than 8
>+	int max_target_bpp;
>+	int min_target_bpp; // Minimum target bits per pixel
>+};
>+
>+const struct dc_dsc_policy dsc_policy = {
>+	.use_min_slices_h = true, // DSC Policy: Use minimum number of slices that fits the pixel clock
>+	.max_slices_h = 0, // DSC Policy: Use max available slices (in our case 4 for or 8, depending on the mode)
>+	.min_sice_height = 108, // DSC Policy: Use slice height recommended by VESA DSC Spreadsheet user guide
>+	.max_target_bpp = 16,
>+	.min_target_bpp = 8,
>+};
>+
>+
> /* This module's internal functions */
> 
> static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_block_size)
>@@ -241,14 +258,6 @@
> 	return true;
> }
> 
>-struct dc_dsc_policy {
>-	bool use_min_slices_h;
>-	int max_slices_h; // Maximum available if 0
>-	int num_slices_v;
>-	int max_target_bpp;
>-	int min_target_bpp; // Minimum target bits per pixel
>-};
>-
> static inline uint32_t dsc_div_by_10_round_up(uint32_t value)
> {
> 	return (value + 9) / 10;
>@@ -270,19 +279,6 @@
> 	return dsc_target_bpp_x16;
> }
> 
>-const struct dc_dsc_policy dsc_policy = {
>-	.use_min_slices_h = true, // DSC Policy: Use minimum number of slices that fits the pixel clock
>-	.max_slices_h = 0, // DSC Policy: Use max available slices (in our case 4 for or 8, depending on the mode)
>-	/* DSC Policy: Number of vertical slices set to 2 for no particular reason.
>-	 * Seems small enough to not affect the quality too much, while still providing some error
>-	 * propagation control (which may also help debugging).
>-	 */
>-	.num_slices_v = 16,
>-	.max_target_bpp = 16,
>-	.min_target_bpp = 8,
>-};
>-
>-
> /* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, and timing's pixel clock
>  * and uncompressed bandwidth.
>  */
>@@ -528,8 +524,8 @@
> 	int sink_per_slice_throughput_mps;
> 	int branch_max_throughput_mps = 0;
> 	bool is_dsc_possible = false;
>-	int num_slices_v;
> 	int pic_height;
>+	int slice_height;
> 
> 	memset(dsc_cfg, 0, sizeof(struct dc_dsc_config));
> 
>@@ -615,7 +611,7 @@
> 	if (!is_dsc_possible)
> 		goto done;
> 
>-	// DSC slicing
>+	// Slice width (i.e. number of slices per line)
> 	max_slices_h = get_max_dsc_slices(dsc_common_caps.slice_caps);
> 
> 	while (max_slices_h > 0) {
>@@ -678,29 +674,26 @@
> 	dsc_cfg->num_slices_h = num_slices_h;
> 	slice_width = pic_width / num_slices_h;
> 
>-	// Vertical number of slices: start from policy and pick the first one that height is divisible by.
>+	is_dsc_possible = slice_width <= dsc_common_caps.max_slice_width;
>+	if (!is_dsc_possible)
>+		goto done;
>+
>+	// Slice height (i.e. number of slices per column): start with policy and pick the first one that height is divisible by.
> 	// For 4:2:0 make sure the slice height is divisible by 2 as well.
>-	num_slices_v = dsc_policy.num_slices_v;
>-	if (num_slices_v < 1)
>-		num_slices_v = 1;
>-
>-	while (num_slices_v >= 1) {
>-		if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
>-			int slice_height = pic_height / num_slices_v;
>-			if (pic_height % num_slices_v == 0 && slice_height % 2 == 0)
>-				break;
>-		} else if (pic_height % num_slices_v == 0)
>-			break;
>+	slice_height = min(dsc_policy.min_sice_height, pic_height);
> 
>-		num_slices_v--;
>-	}
>+	while (slice_height < pic_height && (pic_height % slice_height != 0 ||
>+		(timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && slice_height % 2 != 0)))
>+		slice_height++;
> 
>-	dsc_cfg->num_slices_v = num_slices_v;
>+	if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) // For the case when pic_height < dsc_policy.min_sice_height
>+		is_dsc_possible = (slice_height % 2 == 0);
> 
>-	is_dsc_possible = slice_width <= dsc_common_caps.max_slice_width;
> 	if (!is_dsc_possible)
> 		goto done;
> 
>+	dsc_cfg->num_slices_v = pic_height/slice_height;
>+
> 	// Final decission: can we do DSC or not?
> 	if (is_dsc_possible) {
> 		// Fill out the rest of DSC settings
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dsc/drm_dsc_dc.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,388 +0,0 @@
>-// SPDX-License-Identifier: MIT
>-/*
>- * Copyright Â© 2018 Intel Corp
>- *
>- * Author:
>- * Manasi Navare <manasi.d.navare@intel.com>
>- */
>-
>-/* DC versions of linux includes */
>-#include <include/drm_dsc_dc.h>
>-
>-#define EXPORT_SYMBOL(symbol)	/* nothing */
>-#define BUILD_BUG_ON(cond)	/* nothing */
>-#define DIV_ROUND_UP(a, b)	(((b) + (a) - 1) / (b))
>-#define ERANGE			-1
>-#define DRM_DEBUG_KMS(msg)	/* nothing */
>-#define cpu_to_be16(__x) little_to_big(__x)
>-
>-static unsigned short little_to_big(int data)
>-{
>-	/* Swap lower and upper byte. DMCU uses big endian format. */
>-	return (0xff & (data >> 8)) + ((data & 0xff) << 8);
>-}
>-
>-/*
>- * Everything below this comment was copied directly from drm_dsc.c.
>- * Only the functions needed in DC are included.
>- * Please keep this file synced with upstream.
>- */
>-
>-/**
>- * DOC: dsc helpers
>- *
>- * These functions contain some common logic and helpers to deal with VESA
>- * Display Stream Compression standard required for DSC on Display Port/eDP or
>- * MIPI display interfaces.
>- */
>-
>-/**
>- * drm_dsc_pps_payload_pack() - Populates the DSC PPS
>- *
>- * @pps_payload:
>- * Bitwise struct for DSC Picture Parameter Set. This is defined
>- * by &struct drm_dsc_picture_parameter_set
>- * @dsc_cfg:
>- * DSC Configuration data filled by driver as defined by
>- * &struct drm_dsc_config
>- *
>- * DSC source device sends a picture parameter set (PPS) containing the
>- * information required by the sink to decode the compressed frame. Driver
>- * populates the DSC PPS struct using the DSC configuration parameters in
>- * the order expected by the DSC Display Sink device. For the DSC, the sink
>- * device expects the PPS payload in big endian format for fields
>- * that span more than 1 byte.
>- */
>-void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
>-				const struct drm_dsc_config *dsc_cfg)
>-{
>-	int i;
>-
>-	/* Protect against someone accidently changing struct size */
>-	BUILD_BUG_ON(sizeof(*pps_payload) !=
>-		     DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1);
>-
>-	memset(pps_payload, 0, sizeof(*pps_payload));
>-
>-	/* PPS 0 */
>-	pps_payload->dsc_version =
>-		dsc_cfg->dsc_version_minor |
>-		dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT;
>-
>-	/* PPS 1, 2 is 0 */
>-
>-	/* PPS 3 */
>-	pps_payload->pps_3 =
>-		dsc_cfg->line_buf_depth |
>-		dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT;
>-
>-	/* PPS 4 */
>-	pps_payload->pps_4 =
>-		((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >>
>-		 DSC_PPS_MSB_SHIFT) |
>-		dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT |
>-		dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT |
>-		dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT |
>-		dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT;
>-
>-	/* PPS 5 */
>-	pps_payload->bits_per_pixel_low =
>-		(dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK);
>-
>-	/*
>-	 * The DSC panel expects the PPS packet to have big endian format
>-	 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert
>-	 * to big endian format. If format is little endian, it will swap
>-	 * bytes to convert to Big endian else keep it unchanged.
>-	 */
>-
>-	/* PPS 6, 7 */
>-	pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
>-
>-	/* PPS 8, 9 */
>-	pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
>-
>-	/* PPS 10, 11 */
>-	pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
>-
>-	/* PPS 12, 13 */
>-	pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
>-
>-	/* PPS 14, 15 */
>-	pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
>-
>-	/* PPS 16 */
>-	pps_payload->initial_xmit_delay_high =
>-		((dsc_cfg->initial_xmit_delay &
>-		  DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >>
>-		 DSC_PPS_MSB_SHIFT);
>-
>-	/* PPS 17 */
>-	pps_payload->initial_xmit_delay_low =
>-		(dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK);
>-
>-	/* PPS 18, 19 */
>-	pps_payload->initial_dec_delay =
>-		cpu_to_be16(dsc_cfg->initial_dec_delay);
>-
>-	/* PPS 20 is 0 */
>-
>-	/* PPS 21 */
>-	pps_payload->initial_scale_value =
>-		dsc_cfg->initial_scale_value;
>-
>-	/* PPS 22, 23 */
>-	pps_payload->scale_increment_interval =
>-		cpu_to_be16(dsc_cfg->scale_increment_interval);
>-
>-	/* PPS 24 */
>-	pps_payload->scale_decrement_interval_high =
>-		((dsc_cfg->scale_decrement_interval &
>-		  DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >>
>-		 DSC_PPS_MSB_SHIFT);
>-
>-	/* PPS 25 */
>-	pps_payload->scale_decrement_interval_low =
>-		(dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK);
>-
>-	/* PPS 26[7:0], PPS 27[7:5] RESERVED */
>-
>-	/* PPS 27 */
>-	pps_payload->first_line_bpg_offset =
>-		dsc_cfg->first_line_bpg_offset;
>-
>-	/* PPS 28, 29 */
>-	pps_payload->nfl_bpg_offset =
>-		cpu_to_be16(dsc_cfg->nfl_bpg_offset);
>-
>-	/* PPS 30, 31 */
>-	pps_payload->slice_bpg_offset =
>-		cpu_to_be16(dsc_cfg->slice_bpg_offset);
>-
>-	/* PPS 32, 33 */
>-	pps_payload->initial_offset =
>-		cpu_to_be16(dsc_cfg->initial_offset);
>-
>-	/* PPS 34, 35 */
>-	pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
>-
>-	/* PPS 36 */
>-	pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
>-
>-	/* PPS 37 */
>-	pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
>-
>-	/* PPS 38, 39 */
>-	pps_payload->rc_model_size =
>-		cpu_to_be16(DSC_RC_MODEL_SIZE_CONST);
>-
>-	/* PPS 40 */
>-	pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
>-
>-	/* PPS 41 */
>-	pps_payload->rc_quant_incr_limit0 =
>-		dsc_cfg->rc_quant_incr_limit0;
>-
>-	/* PPS 42 */
>-	pps_payload->rc_quant_incr_limit1 =
>-		dsc_cfg->rc_quant_incr_limit1;
>-
>-	/* PPS 43 */
>-	pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
>-		DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT;
>-
>-	/* PPS 44 - 57 */
>-	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
>-		pps_payload->rc_buf_thresh[i] =
>-			dsc_cfg->rc_buf_thresh[i];
>-
>-	/* PPS 58 - 87 */
>-	/*
>-	 * For DSC sink programming the RC Range parameter fields
>-	 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0]
>-	 */
>-	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
>-		pps_payload->rc_range_parameters[i] =
>-			((dsc_cfg->rc_range_params[i].range_min_qp <<
>-			  DSC_PPS_RC_RANGE_MINQP_SHIFT) |
>-			 (dsc_cfg->rc_range_params[i].range_max_qp <<
>-			  DSC_PPS_RC_RANGE_MAXQP_SHIFT) |
>-			 (dsc_cfg->rc_range_params[i].range_bpg_offset));
>-		pps_payload->rc_range_parameters[i] =
>-			cpu_to_be16(pps_payload->rc_range_parameters[i]);
>-	}
>-
>-	/* PPS 88 */
>-	pps_payload->native_422_420 = dsc_cfg->native_422 |
>-		dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT;
>-
>-	/* PPS 89 */
>-	pps_payload->second_line_bpg_offset =
>-		dsc_cfg->second_line_bpg_offset;
>-
>-	/* PPS 90, 91 */
>-	pps_payload->nsl_bpg_offset =
>-		cpu_to_be16(dsc_cfg->nsl_bpg_offset);
>-
>-	/* PPS 92, 93 */
>-	pps_payload->second_line_offset_adj =
>-		cpu_to_be16(dsc_cfg->second_line_offset_adj);
>-
>-	/* PPS 94 - 127 are O */
>-}
>-EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
>-
>-/**
>- * drm_dsc_compute_rc_parameters() - Write rate control
>- * parameters to the dsc configuration defined in
>- * &struct drm_dsc_config in accordance with the DSC 1.2
>- * specification. Some configuration fields must be present
>- * beforehand.
>- *
>- * @vdsc_cfg:
>- * DSC Configuration data partially filled by driver
>- */
>-int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
>-{
>-	unsigned long groups_per_line = 0;
>-	unsigned long groups_total = 0;
>-	unsigned long num_extra_mux_bits = 0;
>-	unsigned long slice_bits = 0;
>-	unsigned long hrd_delay = 0;
>-	unsigned long final_scale = 0;
>-	unsigned long rbs_min = 0;
>-
>-	if (vdsc_cfg->native_420 || vdsc_cfg->native_422) {
>-		/* Number of groups used to code each line of a slice */
>-		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2,
>-					       DSC_RC_PIXELS_PER_GROUP);
>-
>-		/* chunksize in Bytes */
>-		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
>-							  vdsc_cfg->bits_per_pixel,
>-							  (8 * 16));
>-	} else {
>-		/* Number of groups used to code each line of a slice */
>-		groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
>-					       DSC_RC_PIXELS_PER_GROUP);
>-
>-		/* chunksize in Bytes */
>-		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
>-							  vdsc_cfg->bits_per_pixel,
>-							  (8 * 16));
>-	}
>-
>-	if (vdsc_cfg->convert_rgb)
>-		num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
>-					  (4 * vdsc_cfg->bits_per_component + 4)
>-					  - 2);
>-	else if (vdsc_cfg->native_422)
>-		num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size +
>-			(4 * vdsc_cfg->bits_per_component + 4) +
>-			3 * (4 * vdsc_cfg->bits_per_component) - 2;
>-	else
>-		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
>-			(4 * vdsc_cfg->bits_per_component + 4) +
>-			2 * (4 * vdsc_cfg->bits_per_component) - 2;
>-	/* Number of bits in one Slice */
>-	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
>-
>-	while ((num_extra_mux_bits > 0) &&
>-	       ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
>-		num_extra_mux_bits--;
>-
>-	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
>-		vdsc_cfg->initial_scale_value = groups_per_line + 8;
>-
>-	/* scale_decrement_interval calculation according to DSC spec 1.11 */
>-	if (vdsc_cfg->initial_scale_value > 8)
>-		vdsc_cfg->scale_decrement_interval = groups_per_line /
>-			(vdsc_cfg->initial_scale_value - 8);
>-	else
>-		vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
>-
>-	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
>-		(vdsc_cfg->initial_xmit_delay *
>-		 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
>-
>-	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
>-		DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
>-		return -ERANGE;
>-	}
>-
>-	final_scale = (vdsc_cfg->rc_model_size * 8) /
>-		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
>-	if (vdsc_cfg->slice_height > 1)
>-		/*
>-		 * NflBpgOffset is 16 bit value with 11 fractional bits
>-		 * hence we multiply by 2^11 for preserving the
>-		 * fractional part
>-		 */
>-		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
>-							(vdsc_cfg->slice_height - 1));
>-	else
>-		vdsc_cfg->nfl_bpg_offset = 0;
>-
>-	/* 2^16 - 1 */
>-	if (vdsc_cfg->nfl_bpg_offset > 65535) {
>-		DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
>-		return -ERANGE;
>-	}
>-
>-	/* Number of groups used to code the entire slice */
>-	groups_total = groups_per_line * vdsc_cfg->slice_height;
>-
>-	/* slice_bpg_offset is 16 bit value with 11 fractional bits */
>-	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
>-						    vdsc_cfg->initial_offset +
>-						    num_extra_mux_bits) << 11),
>-						  groups_total);
>-
>-	if (final_scale > 9) {
>-		/*
>-		 * ScaleIncrementInterval =
>-		 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
>-		 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
>-		 * we need divide by 2^11 from pstDscCfg values
>-		 */
>-		vdsc_cfg->scale_increment_interval =
>-				(vdsc_cfg->final_offset * (1 << 11)) /
>-				((vdsc_cfg->nfl_bpg_offset +
>-				vdsc_cfg->slice_bpg_offset) *
>-				(final_scale - 9));
>-	} else {
>-		/*
>-		 * If finalScaleValue is less than or equal to 9, a value of 0 should
>-		 * be used to disable the scale increment at the end of the slice
>-		 */
>-		vdsc_cfg->scale_increment_interval = 0;
>-	}
>-
>-	if (vdsc_cfg->scale_increment_interval > 65535) {
>-		DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
>-		return -ERANGE;
>-	}
>-
>-	/*
>-	 * DSC spec mentions that bits_per_pixel specifies the target
>-	 * bits/pixel (bpp) rate that is used by the encoder,
>-	 * in steps of 1/16 of a bit per pixel
>-	 */
>-	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
>-		DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
>-			     vdsc_cfg->bits_per_pixel, 16) +
>-		groups_per_line * vdsc_cfg->first_line_bpg_offset;
>-
>-	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
>-	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
>-	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
>-
>-	/* As per DSC spec v1.2a recommendation: */
>-	if (vdsc_cfg->native_420)
>-		vdsc_cfg->second_line_offset_adj = 512;
>-	else
>-		vdsc_cfg->second_line_offset_adj = 0;
>-
>-	return 0;
>-}
>-EXPORT_SYMBOL(drm_dsc_compute_rc_parameters);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dsc/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dsc/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/dsc/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/dsc/Makefile	2019-08-31 15:01:11.869736169 -0500
>@@ -9,6 +9,10 @@
> 
> dsc_ccflags := -mhard-float -msse $(cc_stack_align)
> 
>+ifdef CONFIG_CC_IS_CLANG
>+dsc_ccflags += -msse2
>+endif
>+
> CFLAGS_rc_calc.o := $(dsc_ccflags)
> CFLAGS_rc_calc_dpi.o := $(dsc_ccflags)
> CFLAGS_codec_main_amd.o := $(dsc_ccflags)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c	2019-08-31 15:01:11.869736169 -0500
>@@ -24,9 +24,15 @@
>  */
> 
> #include "dm_services.h"
>+
> #include "include/gpio_types.h"
> #include "../hw_factory.h"
> 
>+#include "../hw_gpio.h"
>+#include "../hw_ddc.h"
>+#include "../hw_hpd.h"
>+#include "../hw_generic.h"
>+
> #include "hw_factory_dce110.h"
> 
> #include "dce/dce_11_0_d.h"
>@@ -143,12 +149,12 @@
> }
> 
> static const struct hw_factory_funcs funcs = {
>-	.create_ddc_data = dal_hw_ddc_create,
>-	.create_ddc_clock = dal_hw_ddc_create,
>-	.create_generic = NULL,
>-	.create_hpd = dal_hw_hpd_create,
>-	.create_sync = NULL,
>-	.create_gsl = NULL,
>+	.init_ddc_data = dal_hw_ddc_init,
>+	.init_generic = NULL,
>+	.init_hpd = dal_hw_hpd_init,
>+	.get_ddc_pin = dal_hw_ddc_get_pin,
>+	.get_hpd_pin = dal_hw_hpd_get_pin,
>+	.get_generic_pin = NULL,
> 	.define_hpd_registers = define_hpd_registers,
> 	.define_ddc_registers = define_ddc_registers
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c	2019-08-31 15:01:11.869736169 -0500
>@@ -27,10 +27,10 @@
> #include "include/gpio_types.h"
> #include "../hw_factory.h"
> 
>-
> #include "../hw_gpio.h"
> #include "../hw_ddc.h"
> #include "../hw_hpd.h"
>+#include "../hw_generic.h"
> 
> #include "hw_factory_dce120.h"
> 
>@@ -164,12 +164,12 @@
> 
> /* fucntion table */
> static const struct hw_factory_funcs funcs = {
>-	.create_ddc_data = dal_hw_ddc_create,
>-	.create_ddc_clock = dal_hw_ddc_create,
>-	.create_generic = NULL,
>-	.create_hpd = dal_hw_hpd_create,
>-	.create_sync = NULL,
>-	.create_gsl = NULL,
>+	.init_ddc_data = dal_hw_ddc_init,
>+	.init_generic = NULL,
>+	.init_hpd = dal_hw_hpd_init,
>+	.get_ddc_pin = dal_hw_ddc_get_pin,
>+	.get_hpd_pin = dal_hw_hpd_get_pin,
>+	.get_generic_pin = NULL,
> 	.define_hpd_registers = define_hpd_registers,
> 	.define_ddc_registers = define_ddc_registers
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c	2019-08-31 15:01:11.869736169 -0500
>@@ -32,10 +32,12 @@
> #include "../hw_gpio.h"
> #include "../hw_ddc.h"
> #include "../hw_hpd.h"
>+#include "../hw_generic.h"
> 
> #include "dce/dce_8_0_d.h"
> #include "dce/dce_8_0_sh_mask.h"
> 
>+
> #define REG(reg_name)\
> 		mm ## reg_name
> 
>@@ -147,12 +149,12 @@
> }
> 
> static const struct hw_factory_funcs funcs = {
>-	.create_ddc_data = dal_hw_ddc_create,
>-	.create_ddc_clock = dal_hw_ddc_create,
>-	.create_generic = NULL,
>-	.create_hpd = dal_hw_hpd_create,
>-	.create_sync = NULL,
>-	.create_gsl = NULL,
>+	.init_ddc_data = dal_hw_ddc_init,
>+	.init_generic = NULL,
>+	.init_hpd = dal_hw_hpd_init,
>+	.get_ddc_pin = dal_hw_ddc_get_pin,
>+	.get_hpd_pin = dal_hw_hpd_get_pin,
>+	.get_generic_pin = NULL,
> 	.define_hpd_registers = define_hpd_registers,
> 	.define_ddc_registers = define_ddc_registers
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c	2019-08-31 15:01:11.869736169 -0500
>@@ -31,6 +31,7 @@
> #include "../hw_gpio.h"
> #include "../hw_ddc.h"
> #include "../hw_hpd.h"
>+#include "../hw_generic.h"
> 
> #include "hw_factory_dcn10.h"
> 
>@@ -121,6 +122,42 @@
> 		DDC_MASK_SH_LIST(_MASK)
> };
> 
>+#include "../generic_regs.h"
>+
>+/* set field name */
>+#define SF_GENERIC(reg_name, field_name, post_fix)\
>+	.field_name = reg_name ## __ ## field_name ## post_fix
>+
>+#define generic_regs(id) \
>+{\
>+	GENERIC_REG_LIST(id)\
>+}
>+
>+static const struct generic_registers generic_regs[] = {
>+	generic_regs(A),
>+	generic_regs(B),
>+};
>+
>+static const struct generic_sh_mask generic_shift[] = {
>+	GENERIC_MASK_SH_LIST(__SHIFT, A),
>+	GENERIC_MASK_SH_LIST(__SHIFT, B),
>+};
>+
>+static const struct generic_sh_mask generic_mask[] = {
>+	GENERIC_MASK_SH_LIST(_MASK, A),
>+	GENERIC_MASK_SH_LIST(_MASK, B),
>+};
>+
>+static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
>+{
>+	struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
>+
>+	generic->regs = &generic_regs[en];
>+	generic->shifts = &generic_shift[en];
>+	generic->masks = &generic_mask[en];
>+	generic->base.regs = &generic_regs[en].gpio;
>+}
>+
> static void define_ddc_registers(
> 		struct hw_gpio_pin *pin,
> 		uint32_t en)
>@@ -159,14 +196,15 @@
> 
> /* fucntion table */
> static const struct hw_factory_funcs funcs = {
>-	.create_ddc_data = dal_hw_ddc_create,
>-	.create_ddc_clock = dal_hw_ddc_create,
>-	.create_generic = NULL,
>-	.create_hpd = dal_hw_hpd_create,
>-	.create_sync = NULL,
>-	.create_gsl = NULL,
>+	.init_ddc_data = dal_hw_ddc_init,
>+	.init_generic = dal_hw_generic_init,
>+	.init_hpd = dal_hw_hpd_init,
>+	.get_ddc_pin = dal_hw_ddc_get_pin,
>+	.get_hpd_pin = dal_hw_hpd_get_pin,
>+	.get_generic_pin = dal_hw_generic_get_pin,
> 	.define_hpd_registers = define_hpd_registers,
>-	.define_ddc_registers = define_ddc_registers
>+	.define_ddc_registers = define_ddc_registers,
>+	.define_generic_registers = define_generic_registers
> };
> /*
>  * dal_hw_factory_dcn10_init
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c	2019-08-31 15:01:11.869736169 -0500
>@@ -31,6 +31,7 @@
> #include "../hw_gpio.h"
> #include "../hw_ddc.h"
> #include "../hw_hpd.h"
>+#include "../hw_generic.h"
> 
> #include "hw_factory_dcn20.h"
> 
>@@ -138,6 +139,32 @@
> 	DDC_MASK_SH_LIST_DCN2(_MASK, 6)
> };
> 
>+#include "../generic_regs.h"
>+
>+/* set field name */
>+#define SF_GENERIC(reg_name, field_name, post_fix)\
>+	.field_name = reg_name ## __ ## field_name ## post_fix
>+
>+#define generic_regs(id) \
>+{\
>+	GENERIC_REG_LIST(id)\
>+}
>+
>+static const struct generic_registers generic_regs[] = {
>+	generic_regs(A),
>+	generic_regs(B),
>+};
>+
>+static const struct generic_sh_mask generic_shift[] = {
>+	GENERIC_MASK_SH_LIST(__SHIFT, A),
>+	GENERIC_MASK_SH_LIST(__SHIFT, B),
>+};
>+
>+static const struct generic_sh_mask generic_mask[] = {
>+	GENERIC_MASK_SH_LIST(_MASK, A),
>+	GENERIC_MASK_SH_LIST(_MASK, B),
>+};
>+
> static void define_ddc_registers(
> 		struct hw_gpio_pin *pin,
> 		uint32_t en)
>@@ -173,17 +200,27 @@
> 	hpd->base.regs = &hpd_regs[en].gpio;
> }
> 
>+static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
>+{
>+	struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
>+
>+	generic->regs = &generic_regs[en];
>+	generic->shifts = &generic_shift[en];
>+	generic->masks = &generic_mask[en];
>+	generic->base.regs = &generic_regs[en].gpio;
>+}
> 
> /* fucntion table */
> static const struct hw_factory_funcs funcs = {
>-	.create_ddc_data = dal_hw_ddc_create,
>-	.create_ddc_clock = dal_hw_ddc_create,
>-	.create_generic = NULL,
>-	.create_hpd = dal_hw_hpd_create,
>-	.create_sync = NULL,
>-	.create_gsl = NULL,
>+	.init_ddc_data = dal_hw_ddc_init,
>+	.init_generic = dal_hw_generic_init,
>+	.init_hpd = dal_hw_hpd_init,
>+	.get_ddc_pin = dal_hw_ddc_get_pin,
>+	.get_hpd_pin = dal_hw_hpd_get_pin,
>+	.get_generic_pin = dal_hw_generic_get_pin,
> 	.define_hpd_registers = define_hpd_registers,
>-	.define_ddc_registers = define_ddc_registers
>+	.define_ddc_registers = define_ddc_registers,
>+	.define_generic_registers = define_generic_registers,
> };
> /*
>  * dal_hw_factory_dcn10_init
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c	2019-08-31 15:01:11.869736169 -0500
>@@ -71,7 +71,7 @@
> {
> 	switch (offset) {
> 	/* GENERIC */
>-	case REG(DC_GENERICA):
>+	case REG(DC_GPIO_GENERIC_A):
> 		*id = GPIO_ID_GENERIC;
> 		switch (mask) {
> 		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c	2019-08-31 15:01:11.869736169 -0500
>@@ -0,0 +1,210 @@
>+/*
>+ * Copyright 2013-15 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>+#include "dm_services.h"
>+#include "include/gpio_types.h"
>+#include "../hw_factory.h"
>+
>+
>+#include "../hw_gpio.h"
>+#include "../hw_ddc.h"
>+#include "../hw_hpd.h"
>+#include "../hw_generic.h"
>+
>+#include "hw_factory_dcn21.h"
>+
>+
>+#include "dcn/dcn_2_1_0_offset.h"
>+#include "dcn/dcn_2_1_0_sh_mask.h"
>+#include "renoir_ip_offset.h"
>+
>+
>+#include "reg_helper.h"
>+#include "../hpd_regs.h"
>+/* begin *********************
>+ * macros to expend register list macro defined in HW object header file */
>+
>+/* DCN */
>+#define block HPD
>+#define reg_num 0
>+
>+#undef BASE_INNER
>+#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
>+
>+#define BASE(seg) BASE_INNER(seg)
>+
>+
>+
>+#define REG(reg_name)\
>+		BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
>+
>+#define SF_HPD(reg_name, field_name, post_fix)\
>+	.field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
>+
>+#define REGI(reg_name, block, id)\
>+	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
>+				mm ## block ## id ## _ ## reg_name
>+
>+#define SF(reg_name, field_name, post_fix)\
>+	.field_name = reg_name ## __ ## field_name ## post_fix
>+
>+/* macros to expend register list macro defined in HW object header file
>+ * end *********************/
>+
>+
>+
>+#define hpd_regs(id) \
>+{\
>+	HPD_REG_LIST(id)\
>+}
>+
>+static const struct hpd_registers hpd_regs[] = {
>+	hpd_regs(0),
>+	hpd_regs(1),
>+	hpd_regs(2),
>+	hpd_regs(3),
>+	hpd_regs(4),
>+};
>+
>+static const struct hpd_sh_mask hpd_shift = {
>+		HPD_MASK_SH_LIST(__SHIFT)
>+};
>+
>+static const struct hpd_sh_mask hpd_mask = {
>+		HPD_MASK_SH_LIST(_MASK)
>+};
>+
>+#include "../ddc_regs.h"
>+
>+ /* set field name */
>+#define SF_DDC(reg_name, field_name, post_fix)\
>+	.field_name = reg_name ## __ ## field_name ## post_fix
>+
>+static const struct ddc_registers ddc_data_regs_dcn[] = {
>+	ddc_data_regs_dcn2(1),
>+	ddc_data_regs_dcn2(2),
>+	ddc_data_regs_dcn2(3),
>+	ddc_data_regs_dcn2(4),
>+	ddc_data_regs_dcn2(5),
>+};
>+
>+static const struct ddc_registers ddc_clk_regs_dcn[] = {
>+	ddc_clk_regs_dcn2(1),
>+	ddc_clk_regs_dcn2(2),
>+	ddc_clk_regs_dcn2(3),
>+	ddc_clk_regs_dcn2(4),
>+	ddc_clk_regs_dcn2(5),
>+};
>+
>+static const struct ddc_sh_mask ddc_shift[] = {
>+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
>+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
>+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
>+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
>+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
>+	DDC_MASK_SH_LIST_DCN2(__SHIFT, 6)
>+};
>+
>+static const struct ddc_sh_mask ddc_mask[] = {
>+	DDC_MASK_SH_LIST_DCN2(_MASK, 1),
>+	DDC_MASK_SH_LIST_DCN2(_MASK, 2),
>+	DDC_MASK_SH_LIST_DCN2(_MASK, 3),
>+	DDC_MASK_SH_LIST_DCN2(_MASK, 4),
>+	DDC_MASK_SH_LIST_DCN2(_MASK, 5),
>+	DDC_MASK_SH_LIST_DCN2(_MASK, 6)
>+};
>+
>+static void define_ddc_registers(
>+		struct hw_gpio_pin *pin,
>+		uint32_t en)
>+{
>+	struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
>+
>+	switch (pin->id) {
>+	case GPIO_ID_DDC_DATA:
>+		ddc->regs = &ddc_data_regs_dcn[en];
>+		ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
>+		break;
>+	case GPIO_ID_DDC_CLOCK:
>+		ddc->regs = &ddc_clk_regs_dcn[en];
>+		ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
>+		break;
>+	default:
>+		ASSERT_CRITICAL(false);
>+		return;
>+	}
>+
>+	ddc->shifts = &ddc_shift[en];
>+	ddc->masks = &ddc_mask[en];
>+
>+}
>+
>+static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
>+{
>+	struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
>+
>+	hpd->regs = &hpd_regs[en];
>+	hpd->shifts = &hpd_shift;
>+	hpd->masks = &hpd_mask;
>+	hpd->base.regs = &hpd_regs[en].gpio;
>+}
>+
>+
>+/* fucntion table */
>+static const struct hw_factory_funcs funcs = {
>+	.init_ddc_data = dal_hw_ddc_init,
>+	.init_generic = dal_hw_generic_init,
>+	.init_hpd = dal_hw_hpd_init,
>+	.get_ddc_pin = dal_hw_ddc_get_pin,
>+	.get_hpd_pin = dal_hw_hpd_get_pin,
>+	.get_generic_pin = dal_hw_generic_get_pin,
>+	.define_hpd_registers = define_hpd_registers,
>+	.define_ddc_registers = define_ddc_registers
>+};
>+/*
>+ * dal_hw_factory_dcn10_init
>+ *
>+ * @brief
>+ * Initialize HW factory function pointers and pin info
>+ *
>+ * @param
>+ * struct hw_factory *factory - [out] struct of function pointers
>+ */
>+void dal_hw_factory_dcn21_init(struct hw_factory *factory)
>+{
>+	/*TODO check ASIC CAPs*/
>+	factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
>+	factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
>+	factory->number_of_pins[GPIO_ID_GENERIC] = 4;
>+	factory->number_of_pins[GPIO_ID_HPD] = 6;
>+	factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
>+	factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
>+	factory->number_of_pins[GPIO_ID_SYNC] = 0;
>+	factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
>+
>+	factory->funcs = &funcs;
>+}
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.h	2019-08-31 15:01:11.869736169 -0500
>@@ -0,0 +1,33 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+#ifndef __DAL_HW_FACTORY_DCN21_H__
>+#define __DAL_HW_FACTORY_DCN21_H__
>+
>+/* Initialize HW factory function pointers and pin info */
>+void dal_hw_factory_dcn21_init(struct hw_factory *factory);
>+
>+#endif /* __DAL_HW_FACTORY_DCN20_H__ */
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c	2019-08-31 15:01:11.869736169 -0500
>@@ -0,0 +1,386 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+/*
>+ * Pre-requisites: headers required by header of this unit
>+ */
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>+#include "hw_translate_dcn21.h"
>+
>+#include "dm_services.h"
>+#include "include/gpio_types.h"
>+#include "../hw_translate.h"
>+
>+#include "dcn/dcn_2_1_0_offset.h"
>+#include "dcn/dcn_2_1_0_sh_mask.h"
>+#include "renoir_ip_offset.h"
>+
>+
>+
>+
>+/* begin *********************
>+ * macros to expend register list macro defined in HW object header file */
>+
>+/* DCN */
>+#define block HPD
>+#define reg_num 0
>+
>+#undef BASE_INNER
>+#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
>+
>+#define BASE(seg) BASE_INNER(seg)
>+
>+#undef REG
>+#define REG(reg_name)\
>+		BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
>+#define SF_HPD(reg_name, field_name, post_fix)\
>+	.field_name = reg_name ## __ ## field_name ## post_fix
>+
>+
>+/* macros to expend register list macro defined in HW object header file
>+ * end *********************/
>+
>+
>+static bool offset_to_id(
>+	uint32_t offset,
>+	uint32_t mask,
>+	enum gpio_id *id,
>+	uint32_t *en)
>+{
>+	switch (offset) {
>+	/* GENERIC */
>+	case REG(DC_GENERICA):
>+		*id = GPIO_ID_GENERIC;
>+		switch (mask) {
>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK:
>+			*en = GPIO_GENERIC_A;
>+			return true;
>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK:
>+			*en = GPIO_GENERIC_B;
>+			return true;
>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK:
>+			*en = GPIO_GENERIC_C;
>+			return true;
>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK:
>+			*en = GPIO_GENERIC_D;
>+			return true;
>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK:
>+			*en = GPIO_GENERIC_E;
>+			return true;
>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK:
>+			*en = GPIO_GENERIC_F;
>+			return true;
>+		case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK:
>+			*en = GPIO_GENERIC_G;
>+			return true;
>+		default:
>+			ASSERT_CRITICAL(false);
>+#ifdef PALLADIUM_SUPPORTED
>+		*en = GPIO_DDC_LINE_DDC1;
>+		return true;
>+#endif
>+			return false;
>+		}
>+	break;
>+	/* HPD */
>+	case REG(DC_GPIO_HPD_A):
>+		*id = GPIO_ID_HPD;
>+		switch (mask) {
>+		case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK:
>+			*en = GPIO_HPD_1;
>+			return true;
>+		case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK:
>+			*en = GPIO_HPD_2;
>+			return true;
>+		case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK:
>+			*en = GPIO_HPD_3;
>+			return true;
>+		case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK:
>+			*en = GPIO_HPD_4;
>+			return true;
>+		case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK:
>+			*en = GPIO_HPD_5;
>+			return true;
>+		case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK:
>+			*en = GPIO_HPD_6;
>+			return true;
>+		default:
>+			ASSERT_CRITICAL(false);
>+			return false;
>+		}
>+	break;
>+	/* REG(DC_GPIO_GENLK_MASK */
>+	case REG(DC_GPIO_GENLK_A):
>+		*id = GPIO_ID_GSL;
>+		switch (mask) {
>+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK:
>+			*en = GPIO_GSL_GENLOCK_CLOCK;
>+			return true;
>+		case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK:
>+			*en = GPIO_GSL_GENLOCK_VSYNC;
>+			return true;
>+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK:
>+			*en = GPIO_GSL_SWAPLOCK_A;
>+			return true;
>+		case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK:
>+			*en = GPIO_GSL_SWAPLOCK_B;
>+			return true;
>+		default:
>+			ASSERT_CRITICAL(false);
>+			return false;
>+		}
>+	break;
>+	/* DDC */
>+	/* we don't care about the GPIO_ID for DDC
>+	 * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
>+	 * directly in the create method */
>+	case REG(DC_GPIO_DDC1_A):
>+		*en = GPIO_DDC_LINE_DDC1;
>+		return true;
>+	case REG(DC_GPIO_DDC2_A):
>+		*en = GPIO_DDC_LINE_DDC2;
>+		return true;
>+	case REG(DC_GPIO_DDC3_A):
>+		*en = GPIO_DDC_LINE_DDC3;
>+		return true;
>+	case REG(DC_GPIO_DDC4_A):
>+		*en = GPIO_DDC_LINE_DDC4;
>+		return true;
>+	case REG(DC_GPIO_DDC5_A):
>+		*en = GPIO_DDC_LINE_DDC5;
>+		return true;
>+	case REG(DC_GPIO_DDCVGA_A):
>+		*en = GPIO_DDC_LINE_DDC_VGA;
>+		return true;
>+
>+//	case REG(DC_GPIO_I2CPAD_A): not exit
>+//	case REG(DC_GPIO_PWRSEQ_A):
>+//	case REG(DC_GPIO_PAD_STRENGTH_1):
>+//	case REG(DC_GPIO_PAD_STRENGTH_2):
>+//	case REG(DC_GPIO_DEBUG):
>+	/* UNEXPECTED */
>+	default:
>+//	case REG(DC_GPIO_SYNCA_A): not exist
>+#ifdef PALLADIUM_SUPPORTED
>+		*id = GPIO_ID_HPD;
>+		*en = GPIO_DDC_LINE_DDC1;
>+		return true;
>+#endif
>+		ASSERT_CRITICAL(false);
>+		return false;
>+	}
>+}
>+
>+static bool id_to_offset(
>+	enum gpio_id id,
>+	uint32_t en,
>+	struct gpio_pin_info *info)
>+{
>+	bool result = true;
>+
>+	switch (id) {
>+	case GPIO_ID_DDC_DATA:
>+		info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK;
>+		switch (en) {
>+		case GPIO_DDC_LINE_DDC1:
>+			info->offset = REG(DC_GPIO_DDC1_A);
>+		break;
>+		case GPIO_DDC_LINE_DDC2:
>+			info->offset = REG(DC_GPIO_DDC2_A);
>+		break;
>+		case GPIO_DDC_LINE_DDC3:
>+			info->offset = REG(DC_GPIO_DDC3_A);
>+		break;
>+		case GPIO_DDC_LINE_DDC4:
>+			info->offset = REG(DC_GPIO_DDC4_A);
>+		break;
>+		case GPIO_DDC_LINE_DDC5:
>+			info->offset = REG(DC_GPIO_DDC5_A);
>+		break;
>+		case GPIO_DDC_LINE_DDC_VGA:
>+			info->offset = REG(DC_GPIO_DDCVGA_A);
>+		break;
>+		case GPIO_DDC_LINE_I2C_PAD:
>+		default:
>+			ASSERT_CRITICAL(false);
>+			result = false;
>+		}
>+	break;
>+	case GPIO_ID_DDC_CLOCK:
>+		info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK;
>+		switch (en) {
>+		case GPIO_DDC_LINE_DDC1:
>+			info->offset = REG(DC_GPIO_DDC1_A);
>+		break;
>+		case GPIO_DDC_LINE_DDC2:
>+			info->offset = REG(DC_GPIO_DDC2_A);
>+		break;
>+		case GPIO_DDC_LINE_DDC3:
>+			info->offset = REG(DC_GPIO_DDC3_A);
>+		break;
>+		case GPIO_DDC_LINE_DDC4:
>+			info->offset = REG(DC_GPIO_DDC4_A);
>+		break;
>+		case GPIO_DDC_LINE_DDC5:
>+			info->offset = REG(DC_GPIO_DDC5_A);
>+		break;
>+		case GPIO_DDC_LINE_DDC_VGA:
>+			info->offset = REG(DC_GPIO_DDCVGA_A);
>+		break;
>+		case GPIO_DDC_LINE_I2C_PAD:
>+		default:
>+			ASSERT_CRITICAL(false);
>+			result = false;
>+		}
>+	break;
>+	case GPIO_ID_GENERIC:
>+		info->offset = REG(DC_GPIO_GENERIC_A);
>+		switch (en) {
>+		case GPIO_GENERIC_A:
>+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK;
>+		break;
>+		case GPIO_GENERIC_B:
>+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK;
>+		break;
>+		case GPIO_GENERIC_C:
>+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK;
>+		break;
>+		case GPIO_GENERIC_D:
>+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK;
>+		break;
>+		case GPIO_GENERIC_E:
>+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK;
>+		break;
>+		case GPIO_GENERIC_F:
>+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK;
>+		break;
>+		case GPIO_GENERIC_G:
>+			info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK;
>+		break;
>+		default:
>+			ASSERT_CRITICAL(false);
>+			result = false;
>+		}
>+	break;
>+	case GPIO_ID_HPD:
>+		info->offset = REG(DC_GPIO_HPD_A);
>+		switch (en) {
>+		case GPIO_HPD_1:
>+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
>+		break;
>+		case GPIO_HPD_2:
>+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK;
>+		break;
>+		case GPIO_HPD_3:
>+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK;
>+		break;
>+		case GPIO_HPD_4:
>+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK;
>+		break;
>+		case GPIO_HPD_5:
>+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK;
>+		break;
>+		case GPIO_HPD_6:
>+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK;
>+		break;
>+		default:
>+			ASSERT_CRITICAL(false);
>+#ifdef PALLADIUM_SUPPORTED
>+			info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK;
>+			result = true;
>+#endif
>+			result = false;
>+		}
>+	break;
>+	case GPIO_ID_GSL:
>+		switch (en) {
>+		case GPIO_GSL_GENLOCK_CLOCK:
>+				/*not implmented*/
>+			ASSERT_CRITICAL(false);
>+			result = false;
>+		break;
>+		case GPIO_GSL_GENLOCK_VSYNC:
>+			/*not implmented*/
>+			ASSERT_CRITICAL(false);
>+			result = false;
>+		break;
>+		case GPIO_GSL_SWAPLOCK_A:
>+			/*not implmented*/
>+			ASSERT_CRITICAL(false);
>+			result = false;
>+		break;
>+		case GPIO_GSL_SWAPLOCK_B:
>+			/*not implmented*/
>+			ASSERT_CRITICAL(false);
>+			result = false;
>+
>+		break;
>+		default:
>+			ASSERT_CRITICAL(false);
>+			result = false;
>+		}
>+	break;
>+	case GPIO_ID_SYNC:
>+	case GPIO_ID_VIP_PAD:
>+	default:
>+		ASSERT_CRITICAL(false);
>+		result = false;
>+	}
>+
>+	if (result) {
>+		info->offset_y = info->offset + 2;
>+		info->offset_en = info->offset + 1;
>+		info->offset_mask = info->offset - 1;
>+
>+		info->mask_y = info->mask;
>+		info->mask_en = info->mask;
>+		info->mask_mask = info->mask;
>+	}
>+
>+	return result;
>+}
>+
>+/* function table */
>+static const struct hw_translate_funcs funcs = {
>+	.offset_to_id = offset_to_id,
>+	.id_to_offset = id_to_offset,
>+};
>+
>+/*
>+ * dal_hw_translate_dcn10_init
>+ *
>+ * @brief
>+ * Initialize Hw translate function pointers.
>+ *
>+ * @param
>+ * struct hw_translate *tr - [out] struct of function pointers
>+ *
>+ */
>+void dal_hw_translate_dcn21_init(struct hw_translate *tr)
>+{
>+	tr->funcs = &funcs;
>+}
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.h	2019-08-31 15:01:11.869736169 -0500
>@@ -0,0 +1,35 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+#ifndef __DAL_HW_TRANSLATE_DCN21_H__
>+#define __DAL_HW_TRANSLATE_DCN21_H__
>+
>+struct hw_translate;
>+
>+/* Initialize Hw translate function pointers */
>+void dal_hw_translate_dcn21_init(struct hw_translate *tr);
>+
>+#endif /* __DAL_HW_TRANSLATE_DCN21_H__ */
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/diagnostics/hw_factory_diag.c	2019-08-31 15:01:11.869736169 -0500
>@@ -38,15 +38,13 @@
> #include "../hw_gpio.h"
> #include "../hw_ddc.h"
> #include "../hw_hpd.h"
>+#include "../hw_generic.h"
> 
> /* function table */
> static const struct hw_factory_funcs funcs = {
>-	.create_ddc_data = NULL,
>-	.create_ddc_clock = NULL,
>-	.create_generic = NULL,
>-	.create_hpd = NULL,
>-	.create_sync = NULL,
>-	.create_gsl = NULL,
>+	.init_ddc_data = NULL,
>+	.init_generic = NULL,
>+	.init_hpd = NULL,
> };
> 
> void dal_hw_factory_diag_fpga_init(struct hw_factory *factory)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h	2019-08-31 15:01:11.869736169 -0500
>@@ -0,0 +1,66 @@
>+/*
>+ * Copyright 2012-16 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GENERIC_REGS_H_
>+#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GENERIC_REGS_H_
>+
>+#include "gpio_regs.h"
>+
>+#define GENERIC_GPIO_REG_LIST_ENTRY(type, cd, id) \
>+	.type ## _reg =  REG(DC_GPIO_GENERIC_## type),\
>+	.type ## _mask =  DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## _MASK,\
>+	.type ## _shift = DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## __SHIFT
>+
>+#define GENERIC_GPIO_REG_LIST(id) \
>+	{\
>+	GENERIC_GPIO_REG_LIST_ENTRY(MASK, cd, id),\
>+	GENERIC_GPIO_REG_LIST_ENTRY(A, cd, id),\
>+	GENERIC_GPIO_REG_LIST_ENTRY(EN, cd, id),\
>+	GENERIC_GPIO_REG_LIST_ENTRY(Y, cd, id)\
>+	}
>+
>+#define GENERIC_REG_LIST(id) \
>+	GENERIC_GPIO_REG_LIST(id), \
>+	.mux = REG(DC_GENERIC ## id),\
>+
>+#define GENERIC_MASK_SH_LIST(mask_sh, cd) \
>+	{(DC_GENERIC ## cd ##__GENERIC ## cd ##_EN## mask_sh),\
>+	(DC_GENERIC ## cd ##__GENERIC ## cd ##_SEL## mask_sh)}
>+
>+struct generic_registers {
>+	struct gpio_registers gpio;
>+	uint32_t mux;
>+};
>+
>+struct generic_sh_mask {
>+	/* enable */
>+	uint32_t GENERIC_EN;
>+	/* select */
>+	uint32_t GENERIC_SEL;
>+
>+};
>+
>+
>+#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_GENERIC_REGS_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c	2019-08-31 15:01:11.869736169 -0500
>@@ -67,10 +67,14 @@
> 		return GPIO_RESULT_ALREADY_OPENED;
> 	}
> 
>+	// No action if allocation failed during gpio construct
>+	if (!gpio->hw_container.ddc) {
>+		ASSERT_CRITICAL(false);
>+		return GPIO_RESULT_NON_SPECIFIC_ERROR;
>+	}
> 	gpio->mode = mode;
> 
>-	return dal_gpio_service_open(
>-		gpio->service, gpio->id, gpio->en, mode, &gpio->pin);
>+	return dal_gpio_service_open(gpio);
> }
> 
> enum gpio_result dal_gpio_get_value(
>@@ -231,6 +235,21 @@
> 	return gpio->output_state;
> }
> 
>+struct hw_ddc *dal_gpio_get_ddc(struct gpio *gpio)
>+{
>+	return gpio->hw_container.ddc;
>+}
>+
>+struct hw_hpd *dal_gpio_get_hpd(struct gpio *gpio)
>+{
>+	return gpio->hw_container.hpd;
>+}
>+
>+struct hw_generic *dal_gpio_get_generic(struct gpio *gpio)
>+{
>+	return gpio->hw_container.generic;
>+}
>+
> void dal_gpio_close(
> 	struct gpio *gpio)
> {
>@@ -267,6 +286,30 @@
> 	gpio->mode = GPIO_MODE_UNKNOWN;
> 	gpio->output_state = output_state;
> 
>+	//initialize hw_container union based on id
>+	switch (gpio->id) {
>+	case GPIO_ID_DDC_DATA:
>+		gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en);
>+		break;
>+	case GPIO_ID_DDC_CLOCK:
>+		gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en);
>+		break;
>+	case GPIO_ID_GENERIC:
>+		gpio->service->factory.funcs->init_generic(&gpio->hw_container.generic, service->ctx, id, en);
>+		break;
>+	case GPIO_ID_HPD:
>+		gpio->service->factory.funcs->init_hpd(&gpio->hw_container.hpd, service->ctx, id, en);
>+		break;
>+	// TODO: currently gpio for sync and gsl does not get created, might need it later
>+	case GPIO_ID_SYNC:
>+		break;
>+	case GPIO_ID_GSL:
>+		break;
>+	default:
>+		ASSERT_CRITICAL(false);
>+		gpio->pin = NULL;
>+	}
>+
> 	return gpio;
> }
> 
>@@ -280,6 +323,33 @@
> 
> 	dal_gpio_close(*gpio);
> 
>+	switch ((*gpio)->id) {
>+	case GPIO_ID_DDC_DATA:
>+		kfree((*gpio)->hw_container.ddc);
>+		(*gpio)->hw_container.ddc = NULL;
>+		break;
>+	case GPIO_ID_DDC_CLOCK:
>+		//TODO: might want to change it to init_ddc_clock
>+		kfree((*gpio)->hw_container.ddc);
>+		(*gpio)->hw_container.ddc = NULL;
>+		break;
>+	case GPIO_ID_GENERIC:
>+		kfree((*gpio)->hw_container.generic);
>+		(*gpio)->hw_container.generic = NULL;
>+		break;
>+	case GPIO_ID_HPD:
>+		kfree((*gpio)->hw_container.hpd);
>+		(*gpio)->hw_container.hpd = NULL;
>+		break;
>+	// TODO: currently gpio for sync and gsl does not get created, might need it later
>+	case GPIO_ID_SYNC:
>+		break;
>+	case GPIO_ID_GSL:
>+		break;
>+	default:
>+		break;
>+	}
>+
> 	kfree(*gpio);
> 
> 	*gpio = NULL;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c	2019-08-31 15:01:11.870736169 -0500
>@@ -141,6 +141,58 @@
> 	return dal_gpio_create_irq(service, id, en);
> }
> 
>+struct gpio *dal_gpio_service_create_generic_mux(
>+	struct gpio_service *service,
>+	uint32_t offset,
>+	uint32_t mask)
>+{
>+	enum gpio_id id;
>+	uint32_t en;
>+	struct gpio *generic;
>+
>+	if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) {
>+		ASSERT_CRITICAL(false);
>+		return NULL;
>+	}
>+
>+	generic = dal_gpio_create(
>+		service, id, en, GPIO_PIN_OUTPUT_STATE_DEFAULT);
>+
>+	return generic;
>+}
>+
>+void dal_gpio_destroy_generic_mux(
>+	struct gpio **mux)
>+{
>+	if (!mux || !*mux) {
>+		ASSERT_CRITICAL(false);
>+		return;
>+	}
>+
>+	dal_gpio_close(*mux);
>+	dal_gpio_destroy(mux);
>+	kfree(*mux);
>+
>+	*mux = NULL;
>+}
>+
>+struct gpio_pin_info dal_gpio_get_generic_pin_info(
>+	struct gpio_service *service,
>+	enum gpio_id id,
>+	uint32_t en)
>+{
>+	struct gpio_pin_info pin;
>+
>+	if (service->translate.funcs->id_to_offset) {
>+		service->translate.funcs->id_to_offset(id, en, &pin);
>+	} else {
>+		pin.mask = 0xFFFFFFFF;
>+		pin.offset = 0xFFFFFFFF;
>+	}
>+
>+	return pin;
>+}
>+
> void dal_gpio_service_destroy(
> 	struct gpio_service **ptr)
> {
>@@ -165,6 +217,21 @@
> 	*ptr = NULL;
> }
> 
>+enum gpio_result dal_mux_setup_config(
>+	struct gpio *mux,
>+	struct gpio_generic_mux_config *config)
>+{
>+	struct gpio_config_data config_data;
>+
>+	if (!config)
>+		return GPIO_RESULT_INVALID_DATA;
>+
>+	config_data.config.generic_mux = *config;
>+	config_data.type = GPIO_CONFIG_TYPE_GENERIC_MUX;
>+
>+	return dal_gpio_set_config(mux, &config_data);
>+}
>+
> /*
>  * @brief
>  * Private API.
>@@ -223,13 +290,15 @@
> }
> 
> enum gpio_result dal_gpio_service_open(
>-	struct gpio_service *service,
>-	enum gpio_id id,
>-	uint32_t en,
>-	enum gpio_mode mode,
>-	struct hw_gpio_pin **ptr)
>+	struct gpio *gpio)
> {
>-	struct hw_gpio_pin *pin;
>+	struct gpio_service *service = gpio->service;
>+	enum gpio_id id = gpio->id;
>+	uint32_t en = gpio->en;
>+	enum gpio_mode mode = gpio->mode;
>+
>+	struct hw_gpio_pin **pin = &gpio->pin;
>+
> 
> 	if (!service->busyness[id]) {
> 		ASSERT_CRITICAL(false);
>@@ -243,50 +312,43 @@
> 
> 	switch (id) {
> 	case GPIO_ID_DDC_DATA:
>-		pin = service->factory.funcs->create_ddc_data(
>-			service->ctx, id, en);
>-		service->factory.funcs->define_ddc_registers(pin, en);
>+		*pin = service->factory.funcs->get_ddc_pin(gpio);
>+		service->factory.funcs->define_ddc_registers(*pin, en);
> 	break;
> 	case GPIO_ID_DDC_CLOCK:
>-		pin = service->factory.funcs->create_ddc_clock(
>-			service->ctx, id, en);
>-		service->factory.funcs->define_ddc_registers(pin, en);
>+		*pin = service->factory.funcs->get_ddc_pin(gpio);
>+		service->factory.funcs->define_ddc_registers(*pin, en);
> 	break;
> 	case GPIO_ID_GENERIC:
>-		pin = service->factory.funcs->create_generic(
>-			service->ctx, id, en);
>+		*pin = service->factory.funcs->get_generic_pin(gpio);
>+		service->factory.funcs->define_generic_registers(*pin, en);
> 	break;
> 	case GPIO_ID_HPD:
>-		pin = service->factory.funcs->create_hpd(
>-			service->ctx, id, en);
>-		service->factory.funcs->define_hpd_registers(pin, en);
>+		*pin = service->factory.funcs->get_hpd_pin(gpio);
>+		service->factory.funcs->define_hpd_registers(*pin, en);
> 	break;
>+
>+	//TODO: gsl and sync support? create_sync and create_gsl are NULL
> 	case GPIO_ID_SYNC:
>-		pin = service->factory.funcs->create_sync(
>-			service->ctx, id, en);
>-	break;
> 	case GPIO_ID_GSL:
>-		pin = service->factory.funcs->create_gsl(
>-			service->ctx, id, en);
> 	break;
> 	default:
> 		ASSERT_CRITICAL(false);
> 		return GPIO_RESULT_NON_SPECIFIC_ERROR;
> 	}
> 
>-	if (!pin) {
>+	if (!*pin) {
> 		ASSERT_CRITICAL(false);
> 		return GPIO_RESULT_NON_SPECIFIC_ERROR;
> 	}
> 
>-	if (!pin->funcs->open(pin, mode)) {
>+	if (!(*pin)->funcs->open(*pin, mode)) {
> 		ASSERT_CRITICAL(false);
>-		dal_gpio_service_close(service, &pin);
>+		dal_gpio_service_close(service, pin);
> 		return GPIO_RESULT_OPEN_FAILED;
> 	}
> 
> 	set_pin_busy(service, id, en);
>-	*ptr = pin;
> 	return GPIO_RESULT_OK;
> }
> 
>@@ -308,11 +370,10 @@
> 
> 		pin->funcs->close(pin);
> 
>-		pin->funcs->destroy(ptr);
>+		*ptr = NULL;
> 	}
> }
> 
>-
> enum dc_irq_source dal_irq_get_source(
> 	const struct gpio *irq)
> {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.h	2019-08-31 15:01:11.870736169 -0500
>@@ -42,11 +42,7 @@
> };
> 
> enum gpio_result dal_gpio_service_open(
>-	struct gpio_service *service,
>-	enum gpio_id id,
>-	uint32_t en,
>-	enum gpio_mode mode,
>-	struct hw_gpio_pin **ptr);
>+	struct gpio *gpio);
> 
> void dal_gpio_service_close(
> 	struct gpio_service *service,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c	2019-08-31 15:01:11.870736169 -0500
>@@ -28,6 +28,7 @@
> 
> #include "dm_services.h"
> 
>+#include "include/gpio_interface.h"
> #include "include/gpio_types.h"
> #include "hw_gpio.h"
> #include "hw_ddc.h"
>@@ -45,6 +46,8 @@
> #define REG(reg)\
> 	(ddc->regs->reg)
> 
>+struct gpio;
>+
> static void destruct(
> 	struct hw_ddc *pin)
> {
>@@ -227,24 +230,29 @@
> 	ddc->base.base.funcs = &funcs;
> }
> 
>-struct hw_gpio_pin *dal_hw_ddc_create(
>+void dal_hw_ddc_init(
>+	struct hw_ddc **hw_ddc,
> 	struct dc_context *ctx,
> 	enum gpio_id id,
> 	uint32_t en)
> {
>-	struct hw_ddc *pin;
>-
> 	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
> 		ASSERT_CRITICAL(false);
>-		return NULL;
>+		*hw_ddc = NULL;
> 	}
> 
>-	pin = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL);
>-	if (!pin) {
>+	*hw_ddc = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL);
>+	if (!*hw_ddc) {
> 		ASSERT_CRITICAL(false);
>-		return NULL;
>+		return;
> 	}
> 
>-	construct(pin, id, en, ctx);
>-	return &pin->base.base;
>+	construct(*hw_ddc, id, en, ctx);
>+}
>+
>+struct hw_gpio_pin *dal_hw_ddc_get_pin(struct gpio *gpio)
>+{
>+	struct hw_ddc *hw_ddc = dal_gpio_get_ddc(gpio);
>+
>+	return &hw_ddc->base.base;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h	2019-08-31 15:01:11.870736169 -0500
>@@ -38,9 +38,12 @@
> #define HW_DDC_FROM_BASE(hw_gpio) \
> 	container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_ddc, base)
> 
>-struct hw_gpio_pin *dal_hw_ddc_create(
>+void dal_hw_ddc_init(
>+	struct hw_ddc **hw_ddc,
> 	struct dc_context *ctx,
> 	enum gpio_id id,
> 	uint32_t en);
> 
>+struct hw_gpio_pin *dal_hw_ddc_get_pin(struct gpio *gpio);
>+
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c	2019-08-31 15:01:11.870736169 -0500
>@@ -51,6 +51,9 @@
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> #include "dcn20/hw_factory_dcn20.h"
> #endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+#include "dcn21/hw_factory_dcn21.h"
>+#endif
> 
> #include "diagnostics/hw_factory_diag.h"
> 
>@@ -99,6 +102,11 @@
> 		dal_hw_factory_dcn20_init(factory);
> 		return true;
> #endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	case DCN_VERSION_2_1:
>+		dal_hw_factory_dcn21_init(factory);
>+		return true;
>+#endif
> 
> 	default:
> 		ASSERT_CRITICAL(false);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.h	2019-08-31 15:01:11.870736169 -0500
>@@ -28,41 +28,44 @@
> 
> struct hw_gpio_pin;
> struct hw_hpd;
>+struct hw_ddc;
>+struct hw_generic;
>+struct gpio;
> 
> struct hw_factory {
> 	uint32_t number_of_pins[GPIO_ID_COUNT];
> 
> 	const struct hw_factory_funcs {
>-		struct hw_gpio_pin *(*create_ddc_data)(
>-			struct dc_context *ctx,
>-			enum gpio_id id,
>-			uint32_t en);
>-		struct hw_gpio_pin *(*create_ddc_clock)(
>-			struct dc_context *ctx,
>-			enum gpio_id id,
>-			uint32_t en);
>-		struct hw_gpio_pin *(*create_generic)(
>-			struct dc_context *ctx,
>-			enum gpio_id id,
>-			uint32_t en);
>-		struct hw_gpio_pin *(*create_hpd)(
>-			struct dc_context *ctx,
>-			enum gpio_id id,
>-			uint32_t en);
>-		struct hw_gpio_pin *(*create_sync)(
>-			struct dc_context *ctx,
>-			enum gpio_id id,
>-			uint32_t en);
>-		struct hw_gpio_pin *(*create_gsl)(
>-			struct dc_context *ctx,
>-			enum gpio_id id,
>-			uint32_t en);
>+		void (*init_ddc_data)(
>+				struct hw_ddc **hw_ddc,
>+				struct dc_context *ctx,
>+				enum gpio_id id,
>+				uint32_t en);
>+		void (*init_generic)(
>+				struct hw_generic **hw_generic,
>+				struct dc_context *ctx,
>+				enum gpio_id id,
>+				uint32_t en);
>+		void (*init_hpd)(
>+				struct hw_hpd **hw_hpd,
>+				struct dc_context *ctx,
>+				enum gpio_id id,
>+				uint32_t en);
>+		struct hw_gpio_pin *(*get_hpd_pin)(
>+				struct gpio *gpio);
>+		struct hw_gpio_pin *(*get_ddc_pin)(
>+				struct gpio *gpio);
>+		struct hw_gpio_pin *(*get_generic_pin)(
>+				struct gpio *gpio);
> 		void (*define_hpd_registers)(
> 				struct hw_gpio_pin *pin,
> 				uint32_t en);
> 		void (*define_ddc_registers)(
> 				struct hw_gpio_pin *pin,
> 				uint32_t en);
>+		void (*define_generic_registers)(
>+				struct hw_gpio_pin *pin,
>+				uint32_t en);
> 	} *funcs;
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c	2019-08-31 15:01:11.870736169 -0500
>@@ -0,0 +1,138 @@
>+/*
>+ * Copyright 2012-15 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#include <linux/slab.h>
>+
>+#include "dm_services.h"
>+
>+#include "include/gpio_interface.h"
>+#include "include/gpio_types.h"
>+#include "hw_gpio.h"
>+#include "hw_generic.h"
>+
>+#include "reg_helper.h"
>+#include "generic_regs.h"
>+
>+#undef FN
>+#define FN(reg_name, field_name) \
>+	generic->shifts->field_name, generic->masks->field_name
>+
>+#define CTX \
>+	generic->base.base.ctx
>+#define REG(reg)\
>+	(generic->regs->reg)
>+
>+struct gpio;
>+
>+static void dal_hw_generic_construct(
>+	struct hw_generic *pin,
>+	enum gpio_id id,
>+	uint32_t en,
>+	struct dc_context *ctx)
>+{
>+	dal_hw_gpio_construct(&pin->base, id, en, ctx);
>+}
>+
>+static void dal_hw_generic_destruct(
>+	struct hw_generic *pin)
>+{
>+	dal_hw_gpio_destruct(&pin->base);
>+}
>+
>+static void destroy(
>+	struct hw_gpio_pin **ptr)
>+{
>+	struct hw_generic *generic = HW_GENERIC_FROM_BASE(*ptr);
>+
>+	dal_hw_generic_destruct(generic);
>+
>+	kfree(generic);
>+
>+	*ptr = NULL;
>+}
>+
>+static enum gpio_result set_config(
>+	struct hw_gpio_pin *ptr,
>+	const struct gpio_config_data *config_data)
>+{
>+	struct hw_generic *generic = HW_GENERIC_FROM_BASE(ptr);
>+
>+	if (!config_data)
>+		return GPIO_RESULT_INVALID_DATA;
>+
>+	REG_UPDATE_2(mux,
>+		GENERIC_EN, config_data->config.generic_mux.enable_output_from_mux,
>+		GENERIC_SEL, config_data->config.generic_mux.mux_select);
>+
>+	return GPIO_RESULT_OK;
>+}
>+
>+static const struct hw_gpio_pin_funcs funcs = {
>+	.destroy = destroy,
>+	.open = dal_hw_gpio_open,
>+	.get_value = dal_hw_gpio_get_value,
>+	.set_value = dal_hw_gpio_set_value,
>+	.set_config = set_config,
>+	.change_mode = dal_hw_gpio_change_mode,
>+	.close = dal_hw_gpio_close,
>+};
>+
>+static void construct(
>+	struct hw_generic *generic,
>+	enum gpio_id id,
>+	uint32_t en,
>+	struct dc_context *ctx)
>+{
>+	dal_hw_generic_construct(generic, id, en, ctx);
>+	generic->base.base.funcs = &funcs;
>+}
>+
>+void dal_hw_generic_init(
>+	struct hw_generic **hw_generic,
>+	struct dc_context *ctx,
>+	enum gpio_id id,
>+	uint32_t en)
>+{
>+	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
>+		ASSERT_CRITICAL(false);
>+		*hw_generic = NULL;
>+	}
>+
>+	*hw_generic = kzalloc(sizeof(struct hw_generic), GFP_KERNEL);
>+	if (!*hw_generic) {
>+		ASSERT_CRITICAL(false);
>+		return;
>+	}
>+
>+	construct(*hw_generic, id, en, ctx);
>+}
>+
>+
>+struct hw_gpio_pin *dal_hw_generic_get_pin(struct gpio *gpio)
>+{
>+	struct hw_generic *hw_generic = dal_gpio_get_generic(gpio);
>+
>+	return &hw_generic->base.base;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h	2019-08-31 15:01:11.870736169 -0500
>@@ -0,0 +1,50 @@
>+/*
>+ * Copyright 2012-15 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifndef __DAL_HW_generic_H__
>+#define __DAL_HW_generic_H__
>+
>+#include "generic_regs.h"
>+#include "hw_gpio.h"
>+
>+struct hw_generic {
>+	struct hw_gpio base;
>+	const struct generic_registers *regs;
>+	const struct generic_sh_mask *shifts;
>+	const struct generic_sh_mask *masks;
>+};
>+
>+#define HW_GENERIC_FROM_BASE(hw_gpio) \
>+	container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_generic, base)
>+
>+void dal_hw_generic_init(
>+	struct hw_generic **hw_generic,
>+	struct dc_context *ctx,
>+	enum gpio_id id,
>+	uint32_t en);
>+
>+struct hw_gpio_pin *dal_hw_generic_get_pin(struct gpio *gpio);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c	2019-08-31 15:01:11.870736169 -0500
>@@ -27,6 +27,7 @@
> 
> #include "dm_services.h"
> 
>+#include "include/gpio_interface.h"
> #include "include/gpio_types.h"
> #include "hw_gpio.h"
> #include "hw_hpd.h"
>@@ -43,6 +44,8 @@
> #define REG(reg)\
> 	(hpd->regs->reg)
> 
>+struct gpio;
>+
> static void dal_hw_hpd_construct(
> 	struct hw_hpd *pin,
> 	enum gpio_id id,
>@@ -136,29 +139,29 @@
> 	hpd->base.base.funcs = &funcs;
> }
> 
>-struct hw_gpio_pin *dal_hw_hpd_create(
>+void dal_hw_hpd_init(
>+	struct hw_hpd **hw_hpd,
> 	struct dc_context *ctx,
> 	enum gpio_id id,
> 	uint32_t en)
> {
>-	struct hw_hpd *hpd;
>-
>-	if (id != GPIO_ID_HPD) {
>+	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
> 		ASSERT_CRITICAL(false);
>-		return NULL;
>+		*hw_hpd = NULL;
> 	}
> 
>-	if ((en < GPIO_HPD_MIN) || (en > GPIO_HPD_MAX)) {
>+	*hw_hpd = kzalloc(sizeof(struct hw_hpd), GFP_KERNEL);
>+	if (!*hw_hpd) {
> 		ASSERT_CRITICAL(false);
>-		return NULL;
>+		return;
> 	}
> 
>-	hpd = kzalloc(sizeof(struct hw_hpd), GFP_KERNEL);
>-	if (!hpd) {
>-		ASSERT_CRITICAL(false);
>-		return NULL;
>-	}
>+	construct(*hw_hpd, id, en, ctx);
>+}
>+
>+struct hw_gpio_pin *dal_hw_hpd_get_pin(struct gpio *gpio)
>+{
>+	struct hw_hpd *hw_hpd = dal_gpio_get_hpd(gpio);
> 
>-	construct(hpd, id, en, ctx);
>-	return &hpd->base.base;
>+	return &hw_hpd->base.base;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h	2019-08-31 15:01:11.870736169 -0500
>@@ -38,9 +38,12 @@
> #define HW_HPD_FROM_BASE(hw_gpio) \
> 	container_of((HW_GPIO_FROM_BASE(hw_gpio)), struct hw_hpd, base)
> 
>-struct hw_gpio_pin *dal_hw_hpd_create(
>+void dal_hw_hpd_init(
>+	struct hw_hpd **hw_hpd,
> 	struct dc_context *ctx,
> 	enum gpio_id id,
> 	uint32_t en);
> 
>+struct hw_gpio_pin *dal_hw_hpd_get_pin(struct gpio *gpio);
>+
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c	2019-08-31 15:01:11.870736169 -0500
>@@ -49,6 +49,9 @@
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> #include "dcn20/hw_translate_dcn20.h"
> #endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+#include "dcn21/hw_translate_dcn21.h"
>+#endif
> 
> #include "diagnostics/hw_translate_diag.h"
> 
>@@ -94,6 +97,11 @@
> 		dal_hw_translate_dcn20_init(translate);
> 		return true;
> #endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	case DCN_VERSION_2_1:
>+		dal_hw_translate_dcn21_init(translate);
>+		return true;
>+#endif
> 
> 	default:
> 		BREAK_TO_DEBUGGER();
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/gpio/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/gpio/Makefile	2019-08-31 15:01:11.869736169 -0500
>@@ -24,7 +24,7 @@
> # It provides the control and status of HW GPIO pins.
> 
> GPIO = gpio_base.o gpio_service.o hw_factory.o \
>-       hw_gpio.o hw_hpd.o hw_ddc.o hw_translate.o
>+       hw_gpio.o hw_hpd.o hw_ddc.o hw_generic.o hw_translate.o
> 
> AMD_DAL_GPIO = $(addprefix $(AMDDALPATH)/dc/gpio/,$(GPIO))
> 
>@@ -80,6 +80,13 @@
> AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN20)
> endif
> 
>+ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+GPIO_DCN21 = hw_translate_dcn21.o hw_factory_dcn21.o
>+
>+AMD_DAL_GPIO_DCN21 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn21/,$(GPIO_DCN21))
>+
>+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN21)
>+endif
> ###############################################################################
> # Diagnostics on FPGA
> ###############################################################################
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/core_status.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/core_status.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/core_status.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/core_status.h	2019-08-31 15:01:11.870736169 -0500
>@@ -48,6 +48,9 @@
> 	DC_NO_DSC_RESOURCE = 17,
> #endif
> 	DC_FAIL_UNSUPPORTED_1 = 18,
>+	DC_FAIL_CLK_EXCEED_MAX = 21,
>+	DC_FAIL_CLK_BELOW_MIN = 22, /*THIS IS MIN PER IP*/
>+	DC_FAIL_CLK_BELOW_CFG_REQUIRED = 23, /*THIS IS hard_min in PPLIB*/
> 
> 	DC_ERROR_UNEXPECTED = -1
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/core_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/core_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/core_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/core_types.h	2019-08-31 15:01:11.870736169 -0500
>@@ -63,11 +63,6 @@
> 				TODO: remove it when DC is complete. */
> };
> 
>-enum {
>-	FREE_ACQUIRED_RESOURCE = 0,
>-	KEEP_ACQUIRED_RESOURCE = 1,
>-};
>-
> struct dc_link *link_create(const struct link_init_data *init_params);
> void link_destroy(struct dc_link **link);
> 
>@@ -82,7 +77,7 @@
> 		struct dc_state *state,
> 		struct pipe_ctx *pipe_ctx);
> 
>-void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option);
>+void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
> 
> void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
> /********** DAL Core*********************/
>@@ -92,6 +87,9 @@
> struct resource_pool;
> struct dc_state;
> struct resource_context;
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+struct clk_bw_params;
>+#endif
> 
> struct resource_funcs {
> 	void (*destroy)(struct resource_pool **pool);
>@@ -147,6 +145,11 @@
> 			display_e2e_pipe_params_st *pipes,
> 			int pipe_cnt);
> #endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	void (*update_bw_bounding_box)(
>+			struct dc *dc,
>+			struct clk_bw_params *bw_params);
>+#endif
> 
> };
> 
>@@ -228,14 +231,12 @@
> 
> struct dcn_fe_bandwidth {
> 	int dppclk_khz;
>-
> };
> 
> struct stream_resource {
> 	struct output_pixel_processor *opp;
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> 	struct display_stream_compressor *dsc;
>-	int dscclk_khz;
> #endif
> 	struct timing_generator *tg;
> 	struct stream_encoder *stream_enc;
>@@ -299,6 +300,8 @@
> 
> 	struct pipe_ctx *top_pipe;
> 	struct pipe_ctx *bottom_pipe;
>+	struct pipe_ctx *next_odm_pipe;
>+	struct pipe_ctx *prev_odm_pipe;
> 
> #ifdef CONFIG_DRM_AMD_DC_DCN1_0
> 	struct _vcs_dpi_display_dlg_regs_st dlg_regs;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h	2019-08-31 15:01:11.870736169 -0500
>@@ -38,6 +38,11 @@
> 	struct dc_link_settings *known_limit_link_setting,
> 	int *fail_count);
> 
>+bool dp_verify_link_cap_with_retries(
>+	struct dc_link *link,
>+	struct dc_link_settings *known_limit_link_setting,
>+	int attempts);
>+
> bool dp_validate_mode_timing(
> 	struct dc_link *link,
> 	const struct dc_crtc_timing *timing);
>@@ -62,10 +67,15 @@
> 
> void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
> 
>+enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
>+void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
>+
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> void dp_set_fec_ready(struct dc_link *link, bool ready);
> void dp_set_fec_enable(struct dc_link *link, bool enable);
> bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
>+bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
>+void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
> bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
> #endif
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h	2019-08-31 15:01:11.870736169 -0500
>@@ -28,6 +28,131 @@
> 
> #include "dc.h"
> 
>+#define DCN_MINIMUM_DISPCLK_Khz 100000
>+#define DCN_MINIMUM_DPPCLK_Khz 100000
>+
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+/* Constants */
>+#define DDR4_DRAM_WIDTH   64
>+#define WM_A 0
>+#define WM_B 1
>+#define WM_C 2
>+#define WM_D 3
>+#define WM_SET_COUNT 4
>+#endif
>+
>+#define DCN_MINIMUM_DISPCLK_Khz 100000
>+#define DCN_MINIMUM_DPPCLK_Khz 100000
>+
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+/* Will these bw structures be ASIC specific? */
>+
>+#define MAX_NUM_DPM_LVL		4
>+#define WM_SET_COUNT 		4
>+
>+
>+struct clk_limit_table_entry {
>+	unsigned int voltage; /* milivolts withh 2 fractional bits */
>+	unsigned int dcfclk_mhz;
>+	unsigned int fclk_mhz;
>+	unsigned int memclk_mhz;
>+	unsigned int socclk_mhz;
>+};
>+
>+/* This table is contiguous */
>+struct clk_limit_table {
>+	struct clk_limit_table_entry entries[MAX_NUM_DPM_LVL];
>+	unsigned int num_entries;
>+};
>+
>+struct wm_range_table_entry {
>+	unsigned int wm_inst;
>+	unsigned int wm_type;
>+	double pstate_latency_us;
>+	bool valid;
>+};
>+
>+
>+struct clk_log_info {
>+	bool enabled;
>+	char *pBuf;
>+	unsigned int bufSize;
>+	unsigned int *sum_chars_printed;
>+};
>+
>+struct clk_state_registers_and_bypass {
>+	uint32_t dcfclk;
>+	uint32_t dcf_deep_sleep_divider;
>+	uint32_t dcf_deep_sleep_allow;
>+	uint32_t dprefclk;
>+	uint32_t dispclk;
>+	uint32_t dppclk;
>+
>+	uint32_t dppclk_bypass;
>+	uint32_t dcfclk_bypass;
>+	uint32_t dprefclk_bypass;
>+	uint32_t dispclk_bypass;
>+};
>+
>+struct rv1_clk_internal {
>+	uint32_t CLK0_CLK8_CURRENT_CNT;  //dcfclk
>+	uint32_t CLK0_CLK8_DS_CNTL;		 //dcf_deep_sleep_divider
>+	uint32_t CLK0_CLK8_ALLOW_DS;	 //dcf_deep_sleep_allow
>+	uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
>+	uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
>+
>+	uint32_t CLK0_CLK8_BYPASS_CNTL;  //dcfclk bypass
>+	uint32_t CLK0_CLK10_BYPASS_CNTL; //dprefclk bypass
>+	uint32_t CLK0_CLK11_BYPASS_CNTL; //dispclk bypass
>+};
>+
>+struct rn_clk_internal {
>+	uint32_t CLK1_CLK0_CURRENT_CNT; //dispclk
>+	uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
>+	uint32_t CLK1_CLK2_CURRENT_CNT; //dprefclk
>+	uint32_t CLK1_CLK3_CURRENT_CNT; //dcfclk
>+	uint32_t CLK1_CLK3_DS_CNTL;		//dcf_deep_sleep_divider
>+	uint32_t CLK1_CLK3_ALLOW_DS;	//dcf_deep_sleep_allow
>+
>+	uint32_t CLK1_CLK0_BYPASS_CNTL; //dispclk bypass
>+	uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
>+	uint32_t CLK1_CLK2_BYPASS_CNTL; //dprefclk bypass
>+	uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass
>+
>+};
>+
>+/* For dtn logging and debugging */
>+struct clk_state_registers {
>+		uint32_t CLK0_CLK8_CURRENT_CNT;  //dcfclk
>+		uint32_t CLK0_CLK8_DS_CNTL;		 //dcf_deep_sleep_divider
>+		uint32_t CLK0_CLK8_ALLOW_DS;	 //dcf_deep_sleep_allow
>+		uint32_t CLK0_CLK10_CURRENT_CNT; //dprefclk
>+		uint32_t CLK0_CLK11_CURRENT_CNT; //dispclk
>+};
>+
>+/* TODO: combine this with the above */
>+struct clk_bypass {
>+	uint32_t dcfclk_bypass;
>+	uint32_t dispclk_pypass;
>+	uint32_t dprefclk_bypass;
>+};
>+/*
>+ * This table is not contiguous, can have holes, each
>+ * entry correspond to one set of WM. For example if
>+ * we have 2 DPM and LPDDR, we will WM set A, B and
>+ * D occupied, C will be emptry.
>+ */
>+struct wm_table {
>+	struct wm_range_table_entry entries[WM_SET_COUNT];
>+};
>+
>+struct clk_bw_params {
>+	unsigned int vram_type;
>+	unsigned int num_channels;
>+	struct clk_limit_table clk_table;
>+	struct wm_table wm_table;
>+};
>+#endif
> /* Public interfaces */
> 
> struct clk_states {
>@@ -51,6 +176,10 @@
> 	void (*init_clocks)(struct clk_mgr *clk_mgr);
> 
> 	void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
>+	void (*get_clock)(struct clk_mgr *clk_mgr,
>+			struct dc_state *context,
>+			enum dc_clock_type clock_type,
>+			struct dc_clock_config *clock_cfg);
> };
> 
> struct clk_mgr {
>@@ -58,6 +187,9 @@
> 	struct clk_mgr_funcs *funcs;
> 	struct dc_clocks clks;
> 	int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where this goes
>+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+	struct clk_bw_params *bw_params;
>+#endif
> };
> 
> /* forward declarations */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h	2019-08-31 15:01:11.870736169 -0500
>@@ -64,6 +64,8 @@
>  ***************************************************************************************
>  */
> 
>+/* Macros */
>+
> #define TO_CLK_MGR_INTERNAL(clk_mgr)\
> 	container_of(clk_mgr, struct clk_mgr_internal, base)
> 
>@@ -189,6 +191,7 @@
> 
> struct clk_mgr_internal {
> 	struct clk_mgr base;
>+	int smu_ver;
> 	struct pp_smu_funcs *pp_smu;
> 	struct clk_mgr_internal_funcs *funcs;
> 
>@@ -213,6 +216,8 @@
> 	bool dfs_bypass_enabled;
> 	/* True if the DFS-bypass feature is enabled and active. */
> 	bool dfs_bypass_active;
>+
>+	uint32_t dfs_ref_freq_khz;
> 	/*
> 	 * Cache the display clock returned by VBIOS if DFS-bypass is enabled.
> 	 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency
>@@ -276,8 +281,14 @@
> 
> static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
> {
>-	// Whenever we are transitioning pstate support, we always want to notify prior to committing state
>-	return (calc_support != cur_support) ? !safe_to_lower : false;
>+	if (cur_support != calc_support) {
>+		if (calc_support == true && safe_to_lower)
>+			return true;
>+		else if (calc_support == false && !safe_to_lower)
>+			return true;
>+	}
>+
>+	return false;
> }
> 
> int clk_mgr_helper_get_active_display_cnt(
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h	2019-08-31 15:01:11.870736169 -0500
>@@ -38,7 +38,8 @@
> struct dccg_funcs {
> 	void (*update_dpp_dto)(struct dccg *dccg,
> 			int dpp_inst,
>-			int req_dppclk);
>+			int req_dppclk,
>+			bool reduce_divider_only);
> 	void (*get_dccg_ref_freq)(struct dccg *dccg,
> 			unsigned int xtalin_freq_inKhz,
> 			unsigned int *dccg_ref_freq_inKhz);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h	2019-08-31 15:01:11.870736169 -0500
>@@ -80,6 +80,8 @@
> 		uint64_t page_table_end_addr;
> 		uint64_t page_table_base_addr;
> 	} gart_config;
>+
>+	uint64_t page_table_default_page_addr;
> };
> 
> struct dcn_hubbub_virt_addr_config {
>@@ -141,6 +143,10 @@
> 			struct dcn_watermark_set *watermarks,
> 			unsigned int refclk_mhz,
> 			bool safe_to_lower);
>+
>+	bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub);
>+	void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
>+
> };
> 
> struct hubbub {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h	2019-08-31 15:01:11.870736169 -0500
>@@ -42,6 +42,7 @@
> 
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> 	struct pwl_params shaper_params;
>+	bool cm_bypass_mode;
> #endif
> };
> 
>@@ -200,7 +201,7 @@
> 
> 	void (*set_cursor_attributes)(
> 			struct dpp *dpp_base,
>-			enum dc_cursor_color_format color_format);
>+			struct dc_cursor_attributes *cursor_attributes);
> 
> 	void (*set_cursor_position)(
> 			struct dpp *dpp_base,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h	2019-08-31 15:01:11.870736169 -0500
>@@ -92,7 +92,9 @@
> 	void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
> 	bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
> 	void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
>-			struct dsc_optc_config *dsc_optc_cfg, uint8_t *dsc_packed_pps);
>+			struct dsc_optc_config *dsc_optc_cfg);
>+	bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
>+			uint8_t *dsc_packed_pps);
> 	void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
> 	void (*dsc_disable)(struct display_stream_compressor *dsc);
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h	2019-08-31 15:01:11.870736169 -0500
>@@ -45,22 +45,10 @@
> 	dwb_src_scl = 0,	/* for DCE7x/9x, DCN won't support. */
> 	dwb_src_blnd,		/* for DCE7x/9x */
> 	dwb_src_fmt,		/* for DCE7x/9x */
>-#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> 	dwb_src_otg0 = 0x100,	/* for DCN1.x/DCN2.x, register: mmDWB_SOURCE_SELECT */
> 	dwb_src_otg1,		/* for DCN1.x/DCN2.x */
> 	dwb_src_otg2,		/* for DCN1.x/DCN2.x */
> 	dwb_src_otg3,		/* for DCN1.x/DCN2.x */
>-#else
>-	dwb_src_otg0 = 0x100,	/* for DCN1.x, register: mmDWB_SOURCE_SELECT */
>-	dwb_src_otg1,		/* for DCN1.x */
>-	dwb_src_otg2,		/* for DCN1.x */
>-	dwb_src_otg3,		/* for DCN1.x */
>-#endif
>-	dwb_src_mpc0 = 0x200,	/* for DCN2, register: mmMPC_DWB0_MUX, mmMPC_DWB1_MUX, mmMPC_DWB2_MUX */
>-	dwb_src_mpc1,		/* for DCN2 */
>-	dwb_src_mpc2,		/* for DCN2 */
>-	dwb_src_mpc3,		/* for DCN2 */
>-	dwb_src_mpc4,		/* for DCN2 */
> };
> 
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h	2019-08-31 15:01:11.870736169 -0500
>@@ -28,12 +28,22 @@
> 
> #include "gpio_types.h"
> 
>+
>+union gpio_hw_container {
>+	struct hw_ddc *ddc;
>+	struct hw_generic *generic;
>+	struct hw_hpd *hpd;
>+};
>+
> struct gpio {
> 	struct gpio_service *service;
> 	struct hw_gpio_pin *pin;
> 	enum gpio_id id;
> 	uint32_t en;
>+
>+	union gpio_hw_container hw_container;
> 	enum gpio_mode mode;
>+
> 	/* when GPIO comes from VBIOS, it has defined output state */
> 	enum gpio_pin_output_state output_state;
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h	2019-08-31 15:01:11.871736169 -0500
>@@ -47,6 +47,11 @@
> 	CURSOR_LINE_PER_CHUNK_16
> };
> 
>+enum hubp_ind_block_size {
>+	hubp_ind_block_unconstrained = 0,
>+	hubp_ind_block_64b,
>+};
>+
> struct hubp {
> 	const struct hubp_funcs *funcs;
> 	struct dc_context *ctx;
>@@ -74,7 +79,8 @@
> 			struct _vcs_dpi_display_ttu_regs_st *ttu_regs);
> 
> 	void (*dcc_control)(struct hubp *hubp, bool enable,
>-			bool independent_64b_blks);
>+			enum hubp_ind_block_size blk_size);
>+
> 	void (*mem_program_viewport)(
> 			struct hubp *hubp,
> 			const struct rect *viewport,
>@@ -103,7 +109,7 @@
> 		struct hubp *hubp,
> 		enum surface_pixel_format format,
> 		union dc_tiling_info *tiling_info,
>-		union plane_size *plane_size,
>+		struct plane_size *plane_size,
> 		enum dc_rotation_angle rotation,
> 		struct dc_plane_dcc_param *dcc,
> 		bool horizontal_mirror,
>@@ -111,9 +117,6 @@
> 
> 	bool (*hubp_is_flip_pending)(struct hubp *hubp);
> 
>-	void (*hubp_update_dchub)(struct hubp *hubp,
>-				struct dchub_init_data *dh_data);
>-
> 	void (*set_blank)(struct hubp *hubp, bool blank);
> 	void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h	2019-08-31 15:01:11.871736169 -0500
>@@ -183,6 +183,9 @@
> 
> 	bool (*fec_is_active)(struct link_encoder *enc);
> #endif
>+	bool (*is_in_alt_mode) (struct link_encoder *enc);
>+	enum signal_type (*get_dig_mode)(
>+		struct link_encoder *enc);
> };
> 
> #endif /* LINK_ENCODER_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h	2019-08-31 15:01:11.871736169 -0500
>@@ -40,6 +40,10 @@
> struct dcn_watermarks {
> 	uint32_t pte_meta_urgent_ns;
> 	uint32_t urgent_ns;
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	uint32_t frac_urg_bw_nom;
>+	uint32_t frac_urg_bw_flip;
>+#endif
> 	struct cstate_pstate_watermarks_st cstate_pstate;
> };
> 
>@@ -149,7 +153,7 @@
> 		struct mem_input *mem_input,
> 		enum surface_pixel_format format,
> 		union dc_tiling_info *tiling_info,
>-		union plane_size *plane_size,
>+		struct plane_size *plane_size,
> 		enum dc_rotation_angle rotation,
> 		struct dc_plane_dcc_param *dcc,
> 		bool horizontal_mirror);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h	2019-08-31 15:01:11.871736169 -0500
>@@ -128,6 +128,7 @@
> 	struct mpcc mpcc_array[MAX_MPCC];
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> 	struct pwl_params blender_params;
>+	bool cm_bypass_mode;
> #endif
> };
> 
>@@ -198,6 +199,9 @@
> 	 * Return:  void
> 	 */
> 	void (*mpc_init)(struct mpc *mpc);
>+	void (*mpc_init_single_inst)(
>+			struct mpc *mpc,
>+			unsigned int mpcc_id);
> 
> 	/*
> 	 * Update the blending configuration for a specified MPCC.
>@@ -250,6 +254,10 @@
> 			struct mpc *mpc,
> 			int mpcc_id,
> 			const struct pwl_params *params);
>+	void (*power_on_mpc_mem_pwr)(
>+			struct mpc *mpc,
>+			int mpcc_id,
>+			bool power_on);
> #endif
> 
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h	2019-08-31 15:01:11.871736169 -0500
>@@ -316,11 +316,6 @@
> 	bool (*dpg_is_blanked)(
> 			struct output_pixel_processor *opp);
> 
>-	void (*opp_convert_pti)(
>-		struct output_pixel_processor *opp,
>-		bool enable,
>-		bool polarity);
>-
> 	void (*opp_dpg_set_blank_color)(
> 			struct output_pixel_processor *opp,
> 			const struct tg_color *color);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h	2019-08-31 15:01:11.871736169 -0500
>@@ -91,7 +91,7 @@
> 	struct dc_link_settings link_settings;
> 	struct dc_crtc_timing timing;
> #ifdef CONFIG_DRM_AMD_DC_DCN2_0
>-	bool odm;
>+	int opp_cnt;
> #endif
> };
> 
>@@ -122,9 +122,6 @@
> #endif
> 
> struct stream_encoder_funcs {
>-	#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>-		void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s);
>-	#endif
> 	void (*dp_set_stream_attribute)(
> 		struct stream_encoder *enc,
> 		struct dc_crtc_timing *crtc_timing,
>@@ -211,14 +208,25 @@
> 		struct stream_encoder *enc,
> 		int tg_inst);
> 
>+	void (*hdmi_reset_stream_attribute)(
>+		struct stream_encoder *enc);
>+
>+	unsigned int (*dig_source_otg)(
>+		struct stream_encoder *enc);
>+
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>+	void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s);
>+
> 	void (*dp_set_dsc_config)(
> 			struct stream_encoder *enc,
> 			enum optc_dsc_mode dsc_mode,
> 			uint32_t dsc_bytes_per_pixel,
>-			uint32_t dsc_slice_width,
>-			uint8_t *dsc_packed_pps);
>+			uint32_t dsc_slice_width);
>+
>+	void (*dp_set_dsc_pps_info_packet)(struct stream_encoder *enc,
>+				bool enable,
>+				uint8_t *dsc_packed_pps);
> #endif
> 
> 	void (*set_dynamic_metadata)(struct stream_encoder *enc,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h	2019-08-31 15:01:11.871736169 -0500
>@@ -59,6 +59,8 @@
> struct drr_params {
> 	uint32_t vertical_total_min;
> 	uint32_t vertical_total_max;
>+	uint32_t vertical_total_mid;
>+	uint32_t vertical_total_mid_frame_num;
> 	bool immediate_flip;
> };
> 
>@@ -96,6 +98,11 @@
> 	INTERSECT_WINDOW_NOT_A_NOT_B,
> };
> 
>+enum h_timing_div_mode {
>+	H_TIMING_NO_DIV,
>+	H_TIMING_DIV_BY2,
>+};
>+
> struct crc_params {
> 	/* Regions used to calculate CRC*/
> 	uint16_t windowa_x_start;
>@@ -184,10 +191,8 @@
> 	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
> 	void (*setup_global_swap_lock)(struct timing_generator *tg,
> 							const struct dcp_gsl_params *gsl_params);
>-	void (*setup_global_lock)(struct timing_generator *tg);
> 	void (*unlock)(struct timing_generator *tg);
> 	void (*lock)(struct timing_generator *tg);
>-	void (*lock_global)(struct timing_generator *tg);
> 	void (*lock_doublebuffer_disable)(struct timing_generator *tg);
> 	void (*lock_doublebuffer_enable)(struct timing_generator *tg);
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
>@@ -267,9 +272,9 @@
> 			       uint32_t dsc_bytes_per_pixel,
> 			       uint32_t dsc_slice_width);
> #endif
>-	void (*set_odm_bypass)(struct timing_generator *tg, const struct dc_crtc_timing *dc_crtc_timing);
>-	void (*set_odm_combine)(struct timing_generator *tg, int combine_opp_id,
>-		int mpcc_hactive, enum dc_pixel_encoding pixel_encoding);
>+	void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
>+	void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
>+			struct dc_crtc_timing *timing);
> 	void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
> 	void (*set_gsl_source_select)(struct timing_generator *optc,
> 			int group_idx,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h	2019-08-31 15:01:11.871736169 -0500
>@@ -48,6 +48,7 @@
> 	bool DEGVIDCN10_253;
> 	bool false_optc_underflow;
> 	bool DEGVIDCN10_254;
>+	bool DEGVIDCN21;
> };
> 
> struct hwseq_wa_state {
>@@ -78,6 +79,8 @@
> struct dc_phy_addr_space_config;
> struct dc_virtual_addr_space_config;
> #endif
>+struct hubp;
>+struct dpp;
> 
> struct hw_sequencer_funcs {
> 
>@@ -194,8 +197,7 @@
> 
> 	void (*enable_stream)(struct pipe_ctx *pipe_ctx);
> 
>-	void (*disable_stream)(struct pipe_ctx *pipe_ctx,
>-			int option);
>+	void (*disable_stream)(struct pipe_ctx *pipe_ctx);
> 
> 	void (*unblank_stream)(struct pipe_ctx *pipe_ctx,
> 			struct dc_link_settings *link_settings);
>@@ -204,7 +206,7 @@
> 
> 	void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx);
> 
>-	void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx, int option);
>+	void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx);
> 
> 	void (*pipe_control_lock)(
> 				struct dc *dc,
>@@ -231,11 +233,13 @@
> 	bool (*update_bandwidth)(
> 			struct dc *dc,
> 			struct dc_state *context);
>+	void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx);
> 	bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
> #endif
> 
> 	void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
>-			int vmin, int vmax);
>+			unsigned int vmin, unsigned int vmax,
>+			unsigned int vmid, unsigned int vmid_frame_number);
> 
> 	void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
> 			struct crtc_position *position);
>@@ -279,6 +283,36 @@
> 	void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
> 	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
> 
>+	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
>+	void (*disable_vga)(struct dce_hwseq *hws);
>+	void (*bios_golden_init)(struct dc *dc);
>+	void (*plane_atomic_power_down)(struct dc *dc,
>+			struct dpp *dpp,
>+			struct hubp *hubp);
>+
>+	void (*plane_atomic_disable)(
>+			struct dc *dc, struct pipe_ctx *pipe_ctx);
>+
>+	void (*enable_power_gating_plane)(
>+		struct dce_hwseq *hws,
>+		bool enable);
>+
>+	void (*dpp_pg_control)(
>+			struct dce_hwseq *hws,
>+			unsigned int dpp_inst,
>+			bool power_on);
>+
>+	void (*hubp_pg_control)(
>+			struct dce_hwseq *hws,
>+			unsigned int hubp_inst,
>+			bool power_on);
>+
>+	void (*dsc_pg_control)(
>+			struct dce_hwseq *hws,
>+			unsigned int dsc_inst,
>+			bool power_on);
>+
>+
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> 	void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
> 	void (*program_all_writeback_pipes_in_tree)(
>@@ -294,6 +328,15 @@
> 	void (*disable_writeback)(struct dc *dc,
> 			unsigned int dwb_pipe_inst);
> #endif
>+	enum dc_status (*set_clock)(struct dc *dc,
>+			enum dc_clock_type clock_type,
>+			uint32_t clk_khz,
>+			uint32_t stepping);
>+
>+	void (*get_clock)(struct dc *dc,
>+			enum dc_clock_type clock_type,
>+			struct dc_clock_config *clock_cfg);
>+
> };
> 
> void color_space_to_black_color(
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h	2019-08-31 15:01:11.871736169 -0500
>@@ -60,7 +60,7 @@
> 
> bool dp_set_hw_training_pattern(
> 	struct dc_link *link,
>-	enum hw_dp_training_pattern pattern);
>+	enum dc_dp_training_pattern pattern);
> 
> void dp_set_hw_lane_settings(
> 	struct dc_link *link,
>@@ -72,8 +72,6 @@
> 	uint8_t *custom_pattern,
> 	uint32_t custom_pattern_size);
> 
>-enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
>-
> void dp_retrain_link_dp_test(struct dc_link *link,
> 		struct dc_link_settings *link_setting,
> 		bool skip_video_pattern);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/resource.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/resource.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/inc/resource.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/inc/resource.h	2019-08-31 15:01:11.871736169 -0500
>@@ -179,7 +179,4 @@
> 
> unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format);
> 
>-struct pipe_ctx *dc_res_get_odm_bottom_pipe(struct pipe_ctx *pipe_ctx);
>-bool dc_res_is_odm_head_pipe(struct pipe_ctx *pipe_ctx);
>-
> #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c	2019-08-31 15:01:11.871736169 -0500
>@@ -167,6 +167,11 @@
> 	.ack = NULL
> };
> 
>+static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
>+	.set = NULL,
>+	.ack = NULL
>+};
>+
> #undef BASE_INNER
> #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
> 
>@@ -221,12 +226,15 @@
> 		.funcs = &pflip_irq_info_funcs\
> 	}
> 
>-#define vupdate_int_entry(reg_num)\
>+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
>+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.
>+ */
>+#define vupdate_no_lock_int_entry(reg_num)\
> 	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
> 		IRQ_REG_ENTRY(OTG, reg_num,\
>-			OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
>-			OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
>-		.funcs = &vblank_irq_info_funcs\
>+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
>+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
>+		.funcs = &vupdate_no_lock_irq_info_funcs\
> 	}
> 
> #define vblank_int_entry(reg_num)\
>@@ -333,12 +341,12 @@
> 	dc_underflow_int_entry(6),
> 	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
> 	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
>-	vupdate_int_entry(0),
>-	vupdate_int_entry(1),
>-	vupdate_int_entry(2),
>-	vupdate_int_entry(3),
>-	vupdate_int_entry(4),
>-	vupdate_int_entry(5),
>+	vupdate_no_lock_int_entry(0),
>+	vupdate_no_lock_int_entry(1),
>+	vupdate_no_lock_int_entry(2),
>+	vupdate_no_lock_int_entry(3),
>+	vupdate_no_lock_int_entry(4),
>+	vupdate_no_lock_int_entry(5),
> 	vblank_int_entry(0),
> 	vblank_int_entry(1),
> 	vblank_int_entry(2),
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c	2019-08-31 15:01:11.871736169 -0500
>@@ -0,0 +1,374 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#include <linux/slab.h>
>+
>+#include "dm_services.h"
>+
>+#include "include/logger_interface.h"
>+
>+#include "../dce110/irq_service_dce110.h"
>+
>+#include "dcn/dcn_2_1_0_offset.h"
>+#include "dcn/dcn_2_1_0_sh_mask.h"
>+#include "renoir_ip_offset.h"
>+
>+
>+#include "irq_service_dcn21.h"
>+
>+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
>+
>+enum dc_irq_source to_dal_irq_source_dcn21(
>+		struct irq_service *irq_service,
>+		uint32_t src_id,
>+		uint32_t ext_id)
>+{
>+	switch (src_id) {
>+	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
>+		return DC_IRQ_SOURCE_VBLANK1;
>+	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
>+		return DC_IRQ_SOURCE_VBLANK2;
>+	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
>+		return DC_IRQ_SOURCE_VBLANK3;
>+	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
>+		return DC_IRQ_SOURCE_VBLANK4;
>+	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
>+		return DC_IRQ_SOURCE_VBLANK5;
>+	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
>+		return DC_IRQ_SOURCE_VBLANK6;
>+	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
>+		return DC_IRQ_SOURCE_PFLIP1;
>+	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
>+		return DC_IRQ_SOURCE_PFLIP2;
>+	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
>+		return DC_IRQ_SOURCE_PFLIP3;
>+	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
>+		return DC_IRQ_SOURCE_PFLIP4;
>+	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
>+		return DC_IRQ_SOURCE_PFLIP5;
>+	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
>+		return DC_IRQ_SOURCE_PFLIP6;
>+	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
>+		return DC_IRQ_SOURCE_VUPDATE1;
>+	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
>+		return DC_IRQ_SOURCE_VUPDATE2;
>+	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
>+		return DC_IRQ_SOURCE_VUPDATE3;
>+	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
>+		return DC_IRQ_SOURCE_VUPDATE4;
>+	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
>+		return DC_IRQ_SOURCE_VUPDATE5;
>+	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
>+		return DC_IRQ_SOURCE_VUPDATE6;
>+
>+	case DCN_1_0__SRCID__DC_HPD1_INT:
>+		/* generic src_id for all HPD and HPDRX interrupts */
>+		switch (ext_id) {
>+		case DCN_1_0__CTXID__DC_HPD1_INT:
>+			return DC_IRQ_SOURCE_HPD1;
>+		case DCN_1_0__CTXID__DC_HPD2_INT:
>+			return DC_IRQ_SOURCE_HPD2;
>+		case DCN_1_0__CTXID__DC_HPD3_INT:
>+			return DC_IRQ_SOURCE_HPD3;
>+		case DCN_1_0__CTXID__DC_HPD4_INT:
>+			return DC_IRQ_SOURCE_HPD4;
>+		case DCN_1_0__CTXID__DC_HPD5_INT:
>+			return DC_IRQ_SOURCE_HPD5;
>+		case DCN_1_0__CTXID__DC_HPD6_INT:
>+			return DC_IRQ_SOURCE_HPD6;
>+		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
>+			return DC_IRQ_SOURCE_HPD1RX;
>+		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
>+			return DC_IRQ_SOURCE_HPD2RX;
>+		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
>+			return DC_IRQ_SOURCE_HPD3RX;
>+		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
>+			return DC_IRQ_SOURCE_HPD4RX;
>+		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
>+			return DC_IRQ_SOURCE_HPD5RX;
>+		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
>+			return DC_IRQ_SOURCE_HPD6RX;
>+		default:
>+			return DC_IRQ_SOURCE_INVALID;
>+		}
>+		break;
>+
>+	default:
>+		break;
>+	}
>+	return DC_IRQ_SOURCE_INVALID;
>+}
>+
>+static bool hpd_ack(
>+	struct irq_service *irq_service,
>+	const struct irq_source_info *info)
>+{
>+	uint32_t addr = info->status_reg;
>+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
>+	uint32_t current_status =
>+		get_reg_field_value(
>+			value,
>+			HPD0_DC_HPD_INT_STATUS,
>+			DC_HPD_SENSE_DELAYED);
>+
>+	dal_irq_service_ack_generic(irq_service, info);
>+
>+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
>+
>+	set_reg_field_value(
>+		value,
>+		current_status ? 0 : 1,
>+		HPD0_DC_HPD_INT_CONTROL,
>+		DC_HPD_INT_POLARITY);
>+
>+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
>+
>+	return true;
>+}
>+
>+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
>+	.set = NULL,
>+	.ack = hpd_ack
>+};
>+
>+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
>+	.set = NULL,
>+	.ack = NULL
>+};
>+
>+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
>+	.set = NULL,
>+	.ack = NULL
>+};
>+
>+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
>+	.set = NULL,
>+	.ack = NULL
>+};
>+
>+#undef BASE_INNER
>+#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
>+
>+/* compile time expand base address. */
>+#define BASE(seg) \
>+	BASE_INNER(seg)
>+
>+
>+#define SRI(reg_name, block, id)\
>+	BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
>+			mm ## block ## id ## _ ## reg_name
>+
>+
>+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
>+	.enable_reg = SRI(reg1, block, reg_num),\
>+	.enable_mask = \
>+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
>+	.enable_value = {\
>+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
>+		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
>+	},\
>+	.ack_reg = SRI(reg2, block, reg_num),\
>+	.ack_mask = \
>+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
>+	.ack_value = \
>+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
>+
>+
>+
>+#define hpd_int_entry(reg_num)\
>+	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
>+		IRQ_REG_ENTRY(HPD, reg_num,\
>+			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
>+			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
>+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
>+		.funcs = &hpd_irq_info_funcs\
>+	}
>+
>+#define hpd_rx_int_entry(reg_num)\
>+	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
>+		IRQ_REG_ENTRY(HPD, reg_num,\
>+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
>+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
>+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
>+		.funcs = &hpd_rx_irq_info_funcs\
>+	}
>+#define pflip_int_entry(reg_num)\
>+	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
>+		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
>+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
>+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
>+		.funcs = &pflip_irq_info_funcs\
>+	}
>+
>+#define vupdate_int_entry(reg_num)\
>+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
>+		IRQ_REG_ENTRY(OTG, reg_num,\
>+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
>+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
>+		.funcs = &vblank_irq_info_funcs\
>+	}
>+
>+#define vblank_int_entry(reg_num)\
>+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
>+		IRQ_REG_ENTRY(OTG, reg_num,\
>+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
>+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
>+		.funcs = &vblank_irq_info_funcs\
>+	}
>+
>+#define dummy_irq_entry() \
>+	{\
>+		.funcs = &dummy_irq_info_funcs\
>+	}
>+
>+#define i2c_int_entry(reg_num) \
>+	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
>+
>+#define dp_sink_int_entry(reg_num) \
>+	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
>+
>+#define gpio_pad_int_entry(reg_num) \
>+	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
>+
>+#define dc_underflow_int_entry(reg_num) \
>+	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
>+
>+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
>+	.set = dal_irq_service_dummy_set,
>+	.ack = dal_irq_service_dummy_ack
>+};
>+
>+static const struct irq_source_info
>+irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
>+	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
>+	hpd_int_entry(0),
>+	hpd_int_entry(1),
>+	hpd_int_entry(2),
>+	hpd_int_entry(3),
>+	hpd_int_entry(4),
>+	hpd_rx_int_entry(0),
>+	hpd_rx_int_entry(1),
>+	hpd_rx_int_entry(2),
>+	hpd_rx_int_entry(3),
>+	hpd_rx_int_entry(4),
>+	i2c_int_entry(1),
>+	i2c_int_entry(2),
>+	i2c_int_entry(3),
>+	i2c_int_entry(4),
>+	i2c_int_entry(5),
>+	i2c_int_entry(6),
>+	dp_sink_int_entry(1),
>+	dp_sink_int_entry(2),
>+	dp_sink_int_entry(3),
>+	dp_sink_int_entry(4),
>+	dp_sink_int_entry(5),
>+	dp_sink_int_entry(6),
>+	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
>+	pflip_int_entry(0),
>+	pflip_int_entry(1),
>+	pflip_int_entry(2),
>+	pflip_int_entry(3),
>+	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
>+	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
>+	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
>+	gpio_pad_int_entry(0),
>+	gpio_pad_int_entry(1),
>+	gpio_pad_int_entry(2),
>+	gpio_pad_int_entry(3),
>+	gpio_pad_int_entry(4),
>+	gpio_pad_int_entry(5),
>+	gpio_pad_int_entry(6),
>+	gpio_pad_int_entry(7),
>+	gpio_pad_int_entry(8),
>+	gpio_pad_int_entry(9),
>+	gpio_pad_int_entry(10),
>+	gpio_pad_int_entry(11),
>+	gpio_pad_int_entry(12),
>+	gpio_pad_int_entry(13),
>+	gpio_pad_int_entry(14),
>+	gpio_pad_int_entry(15),
>+	gpio_pad_int_entry(16),
>+	gpio_pad_int_entry(17),
>+	gpio_pad_int_entry(18),
>+	gpio_pad_int_entry(19),
>+	gpio_pad_int_entry(20),
>+	gpio_pad_int_entry(21),
>+	gpio_pad_int_entry(22),
>+	gpio_pad_int_entry(23),
>+	gpio_pad_int_entry(24),
>+	gpio_pad_int_entry(25),
>+	gpio_pad_int_entry(26),
>+	gpio_pad_int_entry(27),
>+	gpio_pad_int_entry(28),
>+	gpio_pad_int_entry(29),
>+	gpio_pad_int_entry(30),
>+	dc_underflow_int_entry(1),
>+	dc_underflow_int_entry(2),
>+	dc_underflow_int_entry(3),
>+	dc_underflow_int_entry(4),
>+	dc_underflow_int_entry(5),
>+	dc_underflow_int_entry(6),
>+	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
>+	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
>+	vupdate_int_entry(0),
>+	vupdate_int_entry(1),
>+	vupdate_int_entry(2),
>+	vupdate_int_entry(3),
>+	vupdate_int_entry(4),
>+	vupdate_int_entry(5),
>+	vblank_int_entry(0),
>+	vblank_int_entry(1),
>+	vblank_int_entry(2),
>+	vblank_int_entry(3),
>+	vblank_int_entry(4),
>+	vblank_int_entry(5),
>+};
>+
>+static const struct irq_service_funcs irq_service_funcs_dcn21 = {
>+		.to_dal_irq_source = to_dal_irq_source_dcn21
>+};
>+
>+static void construct(
>+	struct irq_service *irq_service,
>+	struct irq_service_init_data *init_data)
>+{
>+	dal_irq_service_construct(irq_service, init_data);
>+
>+	irq_service->info = irq_source_info_dcn21;
>+	irq_service->funcs = &irq_service_funcs_dcn21;
>+}
>+
>+struct irq_service *dal_irq_service_dcn21_create(
>+	struct irq_service_init_data *init_data)
>+{
>+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
>+						  GFP_KERNEL);
>+
>+	if (!irq_service)
>+		return NULL;
>+
>+	construct(irq_service, init_data);
>+	return irq_service;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h	2019-08-31 15:01:11.871736169 -0500
>@@ -0,0 +1,34 @@
>+/*
>+ * Copyright 2018 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ * Authors: AMD
>+ *
>+ */
>+
>+#ifndef __DAL_IRQ_SERVICE_DCN21_H__
>+#define __DAL_IRQ_SERVICE_DCN21_H__
>+
>+#include "../irq_service.h"
>+
>+struct irq_service *dal_irq_service_dcn21_create(
>+	struct irq_service_init_data *init_data);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/irq/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/irq/Makefile	2019-08-31 15:01:11.871736169 -0500
>@@ -77,3 +77,13 @@
> 
> AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN2)
> endif
>+###############################################################################
>+# DCN 21
>+###############################################################################
>+ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+IRQ_DCN21 = irq_service_dcn21.o
>+
>+AMD_DAL_IRQ_DCN21= $(addprefix $(AMDDALPATH)/dc/irq/dcn21/,$(IRQ_DCN21))
>+
>+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN21)
>+endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/Makefile	2019-08-31 15:01:11.855736168 -0500
>@@ -37,6 +37,9 @@
> ifdef CONFIG_DRM_AMD_DC_DCN1_0
> DC_LIBS += dcn10 dml
> endif
>+ifdef CONFIG_DRM_AMD_DC_DCN2_1
>+DC_LIBS += dcn21
>+endif
> 
> DC_LIBS += dce120
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c	2019-08-31 15:01:11.871736169 -0500
>@@ -77,6 +77,10 @@
> 	struct stream_encoder *enc,
> 	bool mute) {}
> 
>+static void virtual_stream_encoder_reset_hdmi_stream_attribute(
>+		struct stream_encoder *enc)
>+{}
>+
> #ifdef CONFIG_DRM_AMD_DC_DCN2_0
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> static void virtual_enc_dp_set_odm_combine(
>@@ -116,6 +120,7 @@
> 
> 	.audio_mute_control = virtual_audio_mute_control,
> 	.set_avmute = virtual_stream_encoder_set_avmute,
>+	.hdmi_reset_stream_attribute = virtual_stream_encoder_reset_hdmi_stream_attribute,
> };
> 
> bool virtual_stream_encoder_construct(
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/audio_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/audio_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/audio_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/audio_types.h	2019-08-31 15:01:11.871736169 -0500
>@@ -38,8 +38,8 @@
> 	uint32_t h_active;
> 	uint32_t v_active;
> 	uint32_t pixel_repetition;
>-	uint32_t requested_pixel_clock; /* in KHz */
>-	uint32_t calculated_pixel_clock; /* in KHz */
>+	uint32_t requested_pixel_clock_100Hz; /* in 100Hz */
>+	uint32_t calculated_pixel_clock_100Hz; /* in 100Hz */
> 	uint32_t refresh_rate;
> 	enum dc_color_depth color_depth;
> 	bool interlaced;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/dal_asic_id.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/dal_asic_id.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/dal_asic_id.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/dal_asic_id.h	2019-08-31 15:01:11.871736169 -0500
>@@ -151,6 +151,21 @@
> 
> #define FAMILY_NV 143 /* DCN 2*/
> 
>+enum {
>+	NV_NAVI10_P_A0      = 1,
>+	NV_NAVI12_P_A0      = 10,
>+	NV_NAVI14_M_A0      = 20,
>+	NV_UNKNOWN          = 0xFF
>+};
>+
>+#define ASICREV_IS_NAVI10_P(eChipRev)        (eChipRev < NV_NAVI12_P_A0)
>+#define ASICREV_IS_NAVI12_P(eChipRev)        ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
>+#define ASICREV_IS_NAVI14_M(eChipRev)        ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
>+#endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+#define RENOIR_A0 0x91
>+#define DEVICE_ID_RENOIR_1636 0x1636   // Renoir
>+#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < 0xFF))
> #endif
> 
> /*
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/dal_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/dal_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/dal_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/dal_types.h	2019-08-31 15:01:11.871736169 -0500
>@@ -49,6 +49,9 @@
> #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
> 	DCN_VERSION_2_0,
> #endif
>+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
>+	DCN_VERSION_2_1,
>+#endif
> 	DCN_VERSION_MAX
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/ddc_service_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/ddc_service_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/ddc_service_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/ddc_service_types.h	2019-08-31 15:01:11.871736169 -0500
>@@ -25,10 +25,12 @@
> #ifndef __DAL_DDC_SERVICE_TYPES_H__
> #define __DAL_DDC_SERVICE_TYPES_H__
> 
>-#define DP_BRANCH_DEVICE_ID_1 0x0010FA
>-#define DP_BRANCH_DEVICE_ID_2 0x0022B9
>-#define DP_BRANCH_DEVICE_ID_3 0x00001A
>-#define DP_BRANCH_DEVICE_ID_4 0x0080e1
>+/* 0010FA dongles (ST Micro) external converter chip id */
>+#define DP_BRANCH_DEVICE_ID_0010FA 0x0010FA
>+/* 0022B9 external converter chip id */
>+#define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9
>+#define DP_BRANCH_DEVICE_ID_00001A 0x00001A
>+#define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1
> 
> enum ddc_result {
> 	DDC_RESULT_UNKNOWN = 0,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/gpio_interface.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/gpio_interface.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/gpio_interface.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/gpio_interface.h	2019-08-31 15:01:11.872736169 -0500
>@@ -93,8 +93,17 @@
> enum gpio_pin_output_state dal_gpio_get_output_state(
> 	const struct gpio *gpio);
> 
>+struct hw_ddc *dal_gpio_get_ddc(struct gpio *gpio);
>+
>+struct hw_hpd *dal_gpio_get_hpd(struct gpio *gpio);
>+
>+struct hw_generic *dal_gpio_get_generic(struct gpio *gpio);
>+
> /* Close the handle */
> void dal_gpio_close(
> 	struct gpio *gpio);
> 
>+
>+
>+
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/gpio_service_interface.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/gpio_service_interface.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/gpio_service_interface.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/gpio_service_interface.h	2019-08-31 15:01:11.872736169 -0500
>@@ -51,13 +51,29 @@
> 	uint32_t offset,
> 	uint32_t mask);
> 
>+struct gpio *dal_gpio_service_create_generic_mux(
>+	struct gpio_service *service,
>+	uint32_t offset,
>+	uint32_t mask);
>+
>+void dal_gpio_destroy_generic_mux(
>+	struct gpio **mux);
>+
>+enum gpio_result dal_mux_setup_config(
>+	struct gpio *mux,
>+	struct gpio_generic_mux_config *config);
>+
>+struct gpio_pin_info dal_gpio_get_generic_pin_info(
>+	struct gpio_service *service,
>+	enum gpio_id id,
>+	uint32_t en);
>+
> struct ddc *dal_gpio_create_ddc(
> 	struct gpio_service *service,
> 	uint32_t offset,
> 	uint32_t mask,
> 	struct gpio_ddc_hw_info *info);
> 
>-
> void dal_gpio_destroy_ddc(
> 	struct ddc **ddc);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/link_service_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/link_service_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/link_service_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/link_service_types.h	2019-08-31 15:01:11.872736169 -0500
>@@ -71,14 +71,17 @@
> struct link_training_settings {
> 	struct dc_link_settings link_settings;
> 	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
>-	bool allow_invalid_msa_timing_param;
>-};
> 
>-enum hw_dp_training_pattern {
>-	HW_DP_TRAINING_PATTERN_1 = 0,
>-	HW_DP_TRAINING_PATTERN_2,
>-	HW_DP_TRAINING_PATTERN_3,
>-	HW_DP_TRAINING_PATTERN_4
>+	enum dc_voltage_swing *voltage_swing;
>+	enum dc_pre_emphasis *pre_emphasis;
>+	enum dc_post_cursor2 *post_cursor2;
>+
>+	uint16_t cr_pattern_time;
>+	uint16_t eq_pattern_time;
>+	enum dc_dp_training_pattern pattern_for_eq;
>+
>+	bool enhanced_framing;
>+	bool allow_invalid_msa_timing_param;
> };
> 
> /*TODO: Move this enum test harness*/
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/logger_interface.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/logger_interface.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/logger_interface.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/logger_interface.h	2019-08-31 15:01:11.872736169 -0500
>@@ -155,4 +155,6 @@
> 
> #define DISPLAY_STATS_END(entry) (void)(entry)
> 
>+#define LOG_GAMMA_WRITE(msg, ...)
>+
> #endif /* __DAL_LOGGER_INTERFACE_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/include/logger_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/logger_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/include/logger_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/include/logger_types.h	2019-08-31 15:01:11.872736169 -0500
>@@ -63,6 +63,9 @@
> #define DC_LOG_IF_TRACE(...) pr_debug("[IF_TRACE]:"__VA_ARGS__)
> #define DC_LOG_PERF_TRACE(...) DRM_DEBUG_KMS(__VA_ARGS__)
> #define DC_LOG_RETIMER_REDRIVER(...) DRM_DEBUG_KMS(__VA_ARGS__)
>+#define DC_LOG_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__)
>+#define DC_LOG_ALL_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__)
>+#define DC_LOG_ALL_TF_CHANNELS(...) pr_debug("[GAMMA]:"__VA_ARGS__)
> #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> #define DC_LOG_DSC(...) DRM_DEBUG_KMS(__VA_ARGS__)
> #endif
>@@ -117,6 +120,10 @@
> 	LOG_DSC,
> #endif
> 	LOG_DWB,
>+	LOG_GAMMA_DEBUG,
>+	LOG_MAX_HW_POINTS,
>+	LOG_ALL_TF_CHANNELS,
>+	LOG_SAMPLE_1DLUT,
> 	LOG_SECTION_TOTAL_COUNT
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/Kconfig linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/Kconfig
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/Kconfig	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/Kconfig	2019-08-31 15:01:11.854736168 -0500
>@@ -26,6 +26,14 @@
> 	    Choose this option if you want to have
> 	    Navi support for display engine
> 
>+config DRM_AMD_DC_DCN2_1
>+        bool "DCN 2.1 family"
>+        depends on DRM_AMD_DC && X86
>+        depends on DRM_AMD_DC_DCN2_0
>+        help
>+            Choose this option if you want to have
>+            Renoir support for display engine
>+
> config DRM_AMD_DC_DSC_SUPPORT
> 	bool "DSC support"
> 	default y
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/color/color_gamma.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/color/color_gamma.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/color/color_gamma.c	2019-08-31 15:01:11.872736169 -0500
>@@ -30,7 +30,6 @@
> #include "opp.h"
> #include "color_gamma.h"
> 
>-
> #define NUM_PTS_IN_REGION 16
> #define NUM_REGIONS 32
> #define MAX_HW_POINTS (NUM_PTS_IN_REGION*NUM_REGIONS)
>@@ -40,6 +39,33 @@
> static struct fixed31_32 pq_table[MAX_HW_POINTS + 2];
> static struct fixed31_32 de_pq_table[MAX_HW_POINTS + 2];
> 
>+// these are helpers for calculations to reduce stack usage
>+// do not depend on these being preserved across calls
>+static struct fixed31_32 scratch_1;
>+static struct fixed31_32 scratch_2;
>+static struct translate_from_linear_space_args scratch_gamma_args;
>+
>+/* Helper to optimize gamma calculation, only use in translate_from_linear, in
>+ * particular the dc_fixpt_pow function which is very expensive
>+ * The idea is that our regions for X points are exponential and currently they all use
>+ * the same number of points (NUM_PTS_IN_REGION) and in each region every point
>+ * is exactly 2x the one at the same index in the previous region. In other words
>+ * X[i] = 2 * X[i-NUM_PTS_IN_REGION] for i>=16
>+ * The other fact is that (2x)^gamma = 2^gamma * x^gamma
>+ * So we compute and save x^gamma for the first 16 regions, and for every next region
>+ * just multiply with 2^gamma which can be computed once, and save the result so we
>+ * recursively compute all the values.
>+ */
>+static struct fixed31_32 pow_buffer[NUM_PTS_IN_REGION];
>+static struct fixed31_32 gamma_of_2; // 2^gamma
>+int pow_buffer_ptr = -1;
>+										/*sRGB	 709 2.2 2.4 P3*/
>+static const int32_t gamma_numerator01[] = { 31308,	180000,	0,	0,	0};
>+static const int32_t gamma_numerator02[] = { 12920,	4500,	0,	0,	0};
>+static const int32_t gamma_numerator03[] = { 55,	99,		0,	0,	0};
>+static const int32_t gamma_numerator04[] = { 55,	99,		0,	0,	0};
>+static const int32_t gamma_numerator05[] = { 2400,	2200,	2200, 2400, 2600};
>+
> static bool pq_initialized; /* = false; */
> static bool de_pq_initialized; /* = false; */
> 
>@@ -71,6 +97,18 @@
> 	}
> }
> 
>+void log_x_points_distribution(struct dal_logger *logger)
>+{
>+	int i = 0;
>+
>+	if (logger != NULL) {
>+		LOG_GAMMA_WRITE("Log X Distribution\n");
>+
>+		for (i = 0; i < MAX_HW_POINTS; i++)
>+			LOG_GAMMA_WRITE("%llu\n", coordinates_x[i].x.value);
>+	}
>+}
>+
> static void compute_pq(struct fixed31_32 in_x, struct fixed31_32 *out_y)
> {
> 	/* consts for PQ gamma formula. */
>@@ -135,59 +173,68 @@
> 
> }
> 
>+
> /*de gamma, none linear to linear*/
>-static void compute_hlg_oetf(struct fixed31_32 in_x, bool is_light0_12, struct fixed31_32 *out_y)
>+static void compute_hlg_eotf(struct fixed31_32 in_x,
>+		struct fixed31_32 *out_y,
>+		uint32_t sdr_white_level, uint32_t max_luminance_nits)
> {
> 	struct fixed31_32 a;
> 	struct fixed31_32 b;
> 	struct fixed31_32 c;
> 	struct fixed31_32 threshold;
>-	struct fixed31_32 reference_white_level;
>+	struct fixed31_32 x;
> 
>+	struct fixed31_32 scaling_factor =
>+			dc_fixpt_from_fraction(max_luminance_nits, sdr_white_level);
> 	a = dc_fixpt_from_fraction(17883277, 100000000);
>-	if (is_light0_12) {
>-		/*light 0-12*/
>-		b = dc_fixpt_from_fraction(28466892, 100000000);
>-		c = dc_fixpt_from_fraction(55991073, 100000000);
>-		threshold = dc_fixpt_one;
>-		reference_white_level = dc_fixpt_half;
>+	b = dc_fixpt_from_fraction(28466892, 100000000);
>+	c = dc_fixpt_from_fraction(55991073, 100000000);
>+	threshold = dc_fixpt_from_fraction(1, 2);
>+
>+	if (dc_fixpt_lt(in_x, threshold)) {
>+		x = dc_fixpt_mul(in_x, in_x);
>+		x = dc_fixpt_div_int(x, 3);
> 	} else {
>-		/*light 0-1*/
>-		b = dc_fixpt_from_fraction(2372241, 100000000);
>-		c = dc_fixpt_add(dc_fixpt_one, dc_fixpt_from_fraction(429347, 100000000));
>-		threshold = dc_fixpt_from_fraction(1, 12);
>-		reference_white_level = dc_fixpt_pow(dc_fixpt_from_fraction(3, 1), dc_fixpt_half);
>+		x = dc_fixpt_sub(in_x, c);
>+		x = dc_fixpt_div(x, a);
>+		x = dc_fixpt_exp(x);
>+		x = dc_fixpt_add(x, b);
>+		x = dc_fixpt_div_int(x, 12);
> 	}
>-	if (dc_fixpt_lt(threshold, in_x))
>-		*out_y = dc_fixpt_add(c, dc_fixpt_mul(a, dc_fixpt_log(dc_fixpt_sub(in_x, b))));
>-	else
>-		*out_y = dc_fixpt_mul(dc_fixpt_pow(in_x, dc_fixpt_half), reference_white_level);
>+	*out_y = dc_fixpt_mul(x, scaling_factor);
>+
> }
> 
> /*re gamma, linear to none linear*/
>-static void compute_hlg_eotf(struct fixed31_32 in_x, bool is_light0_12, struct fixed31_32 *out_y)
>+static void compute_hlg_oetf(struct fixed31_32 in_x, struct fixed31_32 *out_y,
>+		uint32_t sdr_white_level, uint32_t max_luminance_nits)
> {
> 	struct fixed31_32 a;
> 	struct fixed31_32 b;
> 	struct fixed31_32 c;
>-	struct fixed31_32 reference_white_level;
>+	struct fixed31_32 threshold;
>+	struct fixed31_32 x;
> 
>+	struct fixed31_32 scaling_factor =
>+			dc_fixpt_from_fraction(sdr_white_level, max_luminance_nits);
> 	a = dc_fixpt_from_fraction(17883277, 100000000);
>-	if (is_light0_12) {
>-		/*light 0-12*/
>-		b = dc_fixpt_from_fraction(28466892, 100000000);
>-		c = dc_fixpt_from_fraction(55991073, 100000000);
>-		reference_white_level = dc_fixpt_from_fraction(4, 1);
>+	b = dc_fixpt_from_fraction(28466892, 100000000);
>+	c = dc_fixpt_from_fraction(55991073, 100000000);
>+	threshold = dc_fixpt_from_fraction(1, 12);
>+	x = dc_fixpt_mul(in_x, scaling_factor);
>+
>+
>+	if (dc_fixpt_lt(x, threshold)) {
>+		x = dc_fixpt_mul(x, dc_fixpt_from_fraction(3, 1));
>+		*out_y = dc_fixpt_pow(x, dc_fixpt_half);
> 	} else {
>-		/*light 0-1*/
>-		b = dc_fixpt_from_fraction(2372241, 100000000);
>-		c = dc_fixpt_add(dc_fixpt_one, dc_fixpt_from_fraction(429347, 100000000));
>-		reference_white_level = dc_fixpt_from_fraction(1, 3);
>+		x = dc_fixpt_mul(x, dc_fixpt_from_fraction(12, 1));
>+		x = dc_fixpt_sub(x, b);
>+		x = dc_fixpt_log(x);
>+		x = dc_fixpt_mul(a, x);
>+		*out_y = dc_fixpt_add(x, c);
> 	}
>-	if (dc_fixpt_lt(dc_fixpt_half, in_x))
>-		*out_y = dc_fixpt_add(dc_fixpt_exp(dc_fixpt_div(dc_fixpt_sub(in_x, c), a)), b);
>-	else
>-		*out_y = dc_fixpt_mul(dc_fixpt_pow(in_x, dc_fixpt_from_fraction(2, 1)), reference_white_level);
> }
> 
> 
>@@ -243,93 +290,101 @@
> 	struct fixed31_32 divider3;
> };
> 
>-enum gamma_type_index {
>-	gamma_type_index_2_4,
>-	gamma_type_index_2_2,
>-	gamma_type_index_2_2_flat
>-};
> 
>-static void build_coefficients(struct gamma_coefficients *coefficients, enum gamma_type_index type)
>+static bool build_coefficients(struct gamma_coefficients *coefficients, enum dc_transfer_func_predefined type)
> {
>-	static const int32_t numerator01[] = { 31308,	180000,	0};
>-	static const int32_t numerator02[] = { 12920,	4500,	0};
>-	static const int32_t numerator03[] = { 55,		99,		0};
>-	static const int32_t numerator04[] = { 55,		99,		0};
>-	static const int32_t numerator05[] = { 2400,	2200, 2200};
> 
> 	uint32_t i = 0;
> 	uint32_t index = 0;
>+	bool ret = true;
> 
>-	if (type == gamma_type_index_2_2)
>+	if (type == TRANSFER_FUNCTION_SRGB)
>+		index = 0;
>+	else if (type == TRANSFER_FUNCTION_BT709)
> 		index = 1;
>-	else if (type == gamma_type_index_2_2_flat)
>+	else if (type == TRANSFER_FUNCTION_GAMMA22)
> 		index = 2;
>+	else if (type == TRANSFER_FUNCTION_GAMMA24)
>+		index = 3;
>+	else if (type == TRANSFER_FUNCTION_GAMMA26)
>+		index = 4;
>+	else {
>+		ret = false;
>+		goto release;
>+	}
> 
> 	do {
> 		coefficients->a0[i] = dc_fixpt_from_fraction(
>-			numerator01[index], 10000000);
>+			gamma_numerator01[index], 10000000);
> 		coefficients->a1[i] = dc_fixpt_from_fraction(
>-			numerator02[index], 1000);
>+			gamma_numerator02[index], 1000);
> 		coefficients->a2[i] = dc_fixpt_from_fraction(
>-			numerator03[index], 1000);
>+			gamma_numerator03[index], 1000);
> 		coefficients->a3[i] = dc_fixpt_from_fraction(
>-			numerator04[index], 1000);
>+			gamma_numerator04[index], 1000);
> 		coefficients->user_gamma[i] = dc_fixpt_from_fraction(
>-			numerator05[index], 1000);
>+			gamma_numerator05[index], 1000);
> 
> 		++i;
> 	} while (i != ARRAY_SIZE(coefficients->a0));
>+release:
>+	return ret;
> }
> 
> static struct fixed31_32 translate_from_linear_space(
>-	struct fixed31_32 arg,
>-	struct fixed31_32 a0,
>-	struct fixed31_32 a1,
>-	struct fixed31_32 a2,
>-	struct fixed31_32 a3,
>-	struct fixed31_32 gamma)
>+		struct translate_from_linear_space_args *args)
> {
> 	const struct fixed31_32 one = dc_fixpt_from_int(1);
> 
>-	if (dc_fixpt_lt(one, arg))
>+	if (dc_fixpt_le(one, args->arg))
> 		return one;
> 
>-	if (dc_fixpt_le(arg, dc_fixpt_neg(a0)))
>-		return dc_fixpt_sub(
>-			a2,
>-			dc_fixpt_mul(
>-				dc_fixpt_add(
>-					one,
>-					a3),
>-				dc_fixpt_pow(
>-					dc_fixpt_neg(arg),
>-					dc_fixpt_recip(gamma))));
>-	else if (dc_fixpt_le(a0, arg))
>-		return dc_fixpt_sub(
>-			dc_fixpt_mul(
>-				dc_fixpt_add(
>-					one,
>-					a3),
>-				dc_fixpt_pow(
>-					arg,
>-					dc_fixpt_recip(gamma))),
>-			a2);
>+	if (dc_fixpt_le(args->arg, dc_fixpt_neg(args->a0))) {
>+		scratch_1 = dc_fixpt_add(one, args->a3);
>+		scratch_2 = dc_fixpt_pow(
>+				dc_fixpt_neg(args->arg),
>+				dc_fixpt_recip(args->gamma));
>+		scratch_1 = dc_fixpt_mul(scratch_1, scratch_2);
>+		scratch_1 = dc_fixpt_sub(args->a2, scratch_1);
>+
>+		return scratch_1;
>+	} else if (dc_fixpt_le(args->a0, args->arg)) {
>+		if (pow_buffer_ptr == 0) {
>+			gamma_of_2 = dc_fixpt_pow(dc_fixpt_from_int(2),
>+					dc_fixpt_recip(args->gamma));
>+		}
>+		scratch_1 = dc_fixpt_add(one, args->a3);
>+		if (pow_buffer_ptr < 16)
>+			scratch_2 = dc_fixpt_pow(args->arg,
>+					dc_fixpt_recip(args->gamma));
>+		else
>+			scratch_2 = dc_fixpt_mul(gamma_of_2,
>+					pow_buffer[pow_buffer_ptr%16]);
>+
>+		pow_buffer[pow_buffer_ptr%16] = scratch_2;
>+		pow_buffer_ptr++;
>+
>+		scratch_1 = dc_fixpt_mul(scratch_1, scratch_2);
>+		scratch_1 = dc_fixpt_sub(scratch_1, args->a2);
>+
>+		return scratch_1;
>+	}
> 	else
>-		return dc_fixpt_mul(
>-			arg,
>-			a1);
>+		return dc_fixpt_mul(args->arg, args->a1);
> }
> 
> static struct fixed31_32 calculate_gamma22(struct fixed31_32 arg)
> {
> 	struct fixed31_32 gamma = dc_fixpt_from_fraction(22, 10);
> 
>-	return translate_from_linear_space(arg,
>-			dc_fixpt_zero,
>-			dc_fixpt_zero,
>-			dc_fixpt_zero,
>-			dc_fixpt_zero,
>-			gamma);
>+	scratch_gamma_args.arg = arg;
>+	scratch_gamma_args.a0 = dc_fixpt_zero;
>+	scratch_gamma_args.a1 = dc_fixpt_zero;
>+	scratch_gamma_args.a2 = dc_fixpt_zero;
>+	scratch_gamma_args.a3 = dc_fixpt_zero;
>+	scratch_gamma_args.gamma = gamma;
>+
>+	return translate_from_linear_space(&scratch_gamma_args);
> }
> 
> static struct fixed31_32 translate_to_linear_space(
>@@ -365,18 +420,19 @@
> 	return linear;
> }
> 
>-static inline struct fixed31_32 translate_from_linear_space_ex(
>+static struct fixed31_32 translate_from_linear_space_ex(
> 	struct fixed31_32 arg,
> 	struct gamma_coefficients *coeff,
> 	uint32_t color_index)
> {
>-	return translate_from_linear_space(
>-		arg,
>-		coeff->a0[color_index],
>-		coeff->a1[color_index],
>-		coeff->a2[color_index],
>-		coeff->a3[color_index],
>-		coeff->user_gamma[color_index]);
>+	scratch_gamma_args.arg = arg;
>+	scratch_gamma_args.a0 = coeff->a0[color_index];
>+	scratch_gamma_args.a1 = coeff->a1[color_index];
>+	scratch_gamma_args.a2 = coeff->a2[color_index];
>+	scratch_gamma_args.a3 = coeff->a3[color_index];
>+	scratch_gamma_args.gamma = coeff->user_gamma[color_index];
>+
>+	return translate_from_linear_space(&scratch_gamma_args);
> }
> 
> 
>@@ -709,30 +765,42 @@
> 	}
> }
> 
>-static void build_regamma(struct pwl_float_data_ex *rgb_regamma,
>+static bool build_regamma(struct pwl_float_data_ex *rgb_regamma,
> 		uint32_t hw_points_num,
>-		const struct hw_x_point *coordinate_x, enum gamma_type_index type)
>+		const struct hw_x_point *coordinate_x, enum dc_transfer_func_predefined type)
> {
> 	uint32_t i;
>+	bool ret = false;
> 
>-	struct gamma_coefficients coeff;
>+	struct gamma_coefficients *coeff;
> 	struct pwl_float_data_ex *rgb = rgb_regamma;
> 	const struct hw_x_point *coord_x = coordinate_x;
> 
>-	build_coefficients(&coeff, type);
>+	coeff = kvzalloc(sizeof(*coeff), GFP_KERNEL);
>+	if (!coeff)
>+		goto release;
> 
>-	i = 0;
>+	if (!build_coefficients(coeff, type))
>+		goto release;
> 
>-	while (i != hw_points_num + 1) {
>+	memset(pow_buffer, 0, NUM_PTS_IN_REGION * sizeof(struct fixed31_32));
>+	pow_buffer_ptr = 0; // see variable definition for more info
>+	i = 0;
>+	while (i <= hw_points_num) {
> 		/*TODO use y vs r,g,b*/
> 		rgb->r = translate_from_linear_space_ex(
>-			coord_x->x, &coeff, 0);
>+			coord_x->x, coeff, 0);
> 		rgb->g = rgb->r;
> 		rgb->b = rgb->r;
> 		++coord_x;
> 		++rgb;
> 		++i;
> 	}
>+	pow_buffer_ptr = -1; // reset back to no optimize
>+	ret = true;
>+release:
>+	kfree(coeff);
>+	return ret;
> }
> 
> static void hermite_spline_eetf(struct fixed31_32 input_x,
>@@ -862,6 +930,8 @@
> 	else
> 		max_content = max_display;
> 
>+	if (!use_eetf)
>+		pow_buffer_ptr = 0; // see var definition for more info
> 	rgb += 32; // first 32 points have problems with fixed point, too small
> 	coord_x += 32;
> 	for (i = 32; i <= hw_points_num; i++) {
>@@ -900,19 +970,23 @@
> 		++coord_x;
> 		++rgb;
> 	}
>+	pow_buffer_ptr = -1;
> 
> 	return true;
> }
> 
>-static void build_degamma(struct pwl_float_data_ex *curve,
>+static bool build_degamma(struct pwl_float_data_ex *curve,
> 		uint32_t hw_points_num,
>-		const struct hw_x_point *coordinate_x, enum gamma_type_index type)
>+		const struct hw_x_point *coordinate_x, enum dc_transfer_func_predefined type)
> {
> 	uint32_t i;
> 	struct gamma_coefficients coeff;
> 	uint32_t begin_index, end_index;
>+	bool ret = false;
>+
>+	if (!build_coefficients(&coeff, type))
>+		goto release;
> 
>-	build_coefficients(&coeff, type);
> 	i = 0;
> 
> 	/* X points is 2^-25 to 2^7
>@@ -941,11 +1015,19 @@
> 		curve[i].b = dc_fixpt_one;
> 		i++;
> 	}
>+	ret = true;
>+release:
>+	return ret;
> }
> 
>+
>+
>+
>+
> static void build_hlg_degamma(struct pwl_float_data_ex *degamma,
> 		uint32_t hw_points_num,
>-		const struct hw_x_point *coordinate_x, bool is_light0_12)
>+		const struct hw_x_point *coordinate_x,
>+		uint32_t sdr_white_level, uint32_t max_luminance_nits)
> {
> 	uint32_t i;
> 
>@@ -953,9 +1035,9 @@
> 	const struct hw_x_point *coord_x = coordinate_x;
> 
> 	i = 0;
>-
>+	//check when i == 434
> 	while (i != hw_points_num + 1) {
>-		compute_hlg_oetf(coord_x->x, is_light0_12, &rgb->r);
>+		compute_hlg_eotf(coord_x->x, &rgb->r, sdr_white_level, max_luminance_nits);
> 		rgb->g = rgb->r;
> 		rgb->b = rgb->r;
> 		++coord_x;
>@@ -964,9 +1046,11 @@
> 	}
> }
> 
>+
> static void build_hlg_regamma(struct pwl_float_data_ex *regamma,
> 		uint32_t hw_points_num,
>-		const struct hw_x_point *coordinate_x, bool is_light0_12)
>+		const struct hw_x_point *coordinate_x,
>+		uint32_t sdr_white_level, uint32_t max_luminance_nits)
> {
> 	uint32_t i;
> 
>@@ -975,8 +1059,9 @@
> 
> 	i = 0;
> 
>+	//when i == 471
> 	while (i != hw_points_num + 1) {
>-		compute_hlg_eotf(coord_x->x, is_light0_12, &rgb->r);
>+		compute_hlg_oetf(coord_x->x, &rgb->r, sdr_white_level, max_luminance_nits);
> 		rgb->g = rgb->r;
> 		rgb->b = rgb->r;
> 		++coord_x;
>@@ -1572,14 +1657,15 @@
> 			output_tf->tf == TRANSFER_FUNCTION_SRGB) {
> 		if (ramp == NULL)
> 			return true;
>-		if ((ramp->is_logical_identity) ||
>+		if ((ramp->is_identity && ramp->type != GAMMA_CS_TFM_1D) ||
> 				(!mapUserRamp && ramp->type == GAMMA_RGB_256))
> 			return true;
> 	}
> 
> 	output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
> 
>-	if (ramp && (mapUserRamp || ramp->type != GAMMA_RGB_256)) {
>+	if (ramp && ramp->type != GAMMA_CS_TFM_1D &&
>+			(mapUserRamp || ramp->type != GAMMA_RGB_256)) {
> 		rgb_user = kvcalloc(ramp->num_entries + _EXTRA_POINTS,
> 			    sizeof(*rgb_user),
> 			    GFP_KERNEL);
>@@ -1634,6 +1720,12 @@
> 				MAX_HW_POINTS,
> 				coordinates_x,
> 				fs_params);
>+	} else if (tf == TRANSFER_FUNCTION_HLG) {
>+		build_freesync_hdr(rgb_regamma,
>+				MAX_HW_POINTS,
>+				coordinates_x,
>+				fs_params);
>+
> 	} else {
> 		tf_pts->end_exponent = 0;
> 		tf_pts->x_point_at_y1_red = 1;
>@@ -1642,9 +1734,7 @@
> 
> 		build_regamma(rgb_regamma,
> 				MAX_HW_POINTS,
>-				coordinates_x, tf == TRANSFER_FUNCTION_SRGB ? gamma_type_index_2_4 :
>-					tf == TRANSFER_FUNCTION_GAMMA22 ?
>-					gamma_type_index_2_2_flat : gamma_type_index_2_2);
>+				coordinates_x, tf);
> 	}
> 	map_regamma_hw_to_x_user(ramp, coeff, rgb_user,
> 			coordinates_x, axis_x, rgb_regamma,
>@@ -1845,13 +1935,19 @@
> 				MAX_HW_POINTS,
> 				coordinates_x);
> 	else if (tf == TRANSFER_FUNCTION_SRGB ||
>-			tf == TRANSFER_FUNCTION_BT709)
>+		tf == TRANSFER_FUNCTION_BT709 ||
>+		tf == TRANSFER_FUNCTION_GAMMA22 ||
>+		tf == TRANSFER_FUNCTION_GAMMA24 ||
>+		tf == TRANSFER_FUNCTION_GAMMA26)
> 		build_degamma(curve,
> 				MAX_HW_POINTS,
> 				coordinates_x,
>-				tf == TRANSFER_FUNCTION_SRGB ?
>-				gamma_type_index_2_4 : tf == TRANSFER_FUNCTION_GAMMA22 ?
>-				gamma_type_index_2_2_flat : gamma_type_index_2_2);
>+				tf);
>+	else if (tf == TRANSFER_FUNCTION_HLG)
>+		build_hlg_degamma(curve,
>+				MAX_HW_POINTS,
>+				coordinates_x,
>+				80, 1000);
> 	else if (tf == TRANSFER_FUNCTION_LINEAR) {
> 		// just copy coordinates_x into curve
> 		i = 0;
>@@ -1938,7 +2034,10 @@
> 
> 		kvfree(rgb_regamma);
> 	} else if (trans == TRANSFER_FUNCTION_SRGB ||
>-			  trans == TRANSFER_FUNCTION_BT709) {
>+		trans == TRANSFER_FUNCTION_BT709 ||
>+		trans == TRANSFER_FUNCTION_GAMMA22 ||
>+		trans == TRANSFER_FUNCTION_GAMMA24 ||
>+		trans == TRANSFER_FUNCTION_GAMMA26) {
> 		rgb_regamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
> 				       sizeof(*rgb_regamma),
> 				       GFP_KERNEL);
>@@ -1952,9 +2051,7 @@
> 		build_regamma(rgb_regamma,
> 				MAX_HW_POINTS,
> 				coordinates_x,
>-				trans == TRANSFER_FUNCTION_SRGB ?
>-				gamma_type_index_2_4 : trans == TRANSFER_FUNCTION_GAMMA22 ?
>-				gamma_type_index_2_2_flat : gamma_type_index_2_2);
>+				trans);
> 		for (i = 0; i <= MAX_HW_POINTS ; i++) {
> 			points->red[i]    = rgb_regamma[i].r;
> 			points->green[i]  = rgb_regamma[i].g;
>@@ -1963,18 +2060,21 @@
> 		ret = true;
> 
> 		kvfree(rgb_regamma);
>-	} else if (trans == TRANSFER_FUNCTION_HLG ||
>-		trans == TRANSFER_FUNCTION_HLG12) {
>+	} else if (trans == TRANSFER_FUNCTION_HLG) {
> 		rgb_regamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
> 				       sizeof(*rgb_regamma),
> 				       GFP_KERNEL);
> 		if (!rgb_regamma)
> 			goto rgb_regamma_alloc_fail;
>+		points->end_exponent = 4;
>+		points->x_point_at_y1_red = 12;
>+		points->x_point_at_y1_green = 12;
>+		points->x_point_at_y1_blue = 12;
> 
> 		build_hlg_regamma(rgb_regamma,
> 				MAX_HW_POINTS,
> 				coordinates_x,
>-				trans == TRANSFER_FUNCTION_HLG12 ? true:false);
>+				80, 1000);
> 		for (i = 0; i <= MAX_HW_POINTS ; i++) {
> 			points->red[i]    = rgb_regamma[i].r;
> 			points->green[i]  = rgb_regamma[i].g;
>@@ -2024,8 +2124,10 @@
> 
> 		kvfree(rgb_degamma);
> 	} else if (trans == TRANSFER_FUNCTION_SRGB ||
>-			  trans == TRANSFER_FUNCTION_BT709 ||
>-			  trans == TRANSFER_FUNCTION_GAMMA22) {
>+		trans == TRANSFER_FUNCTION_BT709 ||
>+		trans == TRANSFER_FUNCTION_GAMMA22 ||
>+		trans == TRANSFER_FUNCTION_GAMMA24 ||
>+		trans == TRANSFER_FUNCTION_GAMMA26) {
> 		rgb_degamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
> 				       sizeof(*rgb_degamma),
> 				       GFP_KERNEL);
>@@ -2035,9 +2137,7 @@
> 		build_degamma(rgb_degamma,
> 				MAX_HW_POINTS,
> 				coordinates_x,
>-				trans == TRANSFER_FUNCTION_SRGB ?
>-				gamma_type_index_2_4 : trans == TRANSFER_FUNCTION_GAMMA22 ?
>-				gamma_type_index_2_2_flat : gamma_type_index_2_2);
>+				trans);
> 		for (i = 0; i <= MAX_HW_POINTS ; i++) {
> 			points->red[i]    = rgb_degamma[i].r;
> 			points->green[i]  = rgb_degamma[i].g;
>@@ -2046,8 +2146,7 @@
> 		ret = true;
> 
> 		kvfree(rgb_degamma);
>-	} else if (trans == TRANSFER_FUNCTION_HLG ||
>-		trans == TRANSFER_FUNCTION_HLG12) {
>+	} else if (trans == TRANSFER_FUNCTION_HLG) {
> 		rgb_degamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
> 				       sizeof(*rgb_degamma),
> 				       GFP_KERNEL);
>@@ -2057,7 +2156,7 @@
> 		build_hlg_degamma(rgb_degamma,
> 				MAX_HW_POINTS,
> 				coordinates_x,
>-				trans == TRANSFER_FUNCTION_HLG12 ? true:false);
>+				80, 1000);
> 		for (i = 0; i <= MAX_HW_POINTS ; i++) {
> 			points->red[i]    = rgb_degamma[i].r;
> 			points->green[i]  = rgb_degamma[i].g;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/color/color_gamma.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/color/color_gamma.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/color/color_gamma.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/color/color_gamma.h	2019-08-31 15:01:11.872736169 -0500
>@@ -82,7 +82,17 @@
> 	unsigned int skip_tm; // skip tm
> };
> 
>+struct translate_from_linear_space_args {
>+	struct fixed31_32 arg;
>+	struct fixed31_32 a0;
>+	struct fixed31_32 a1;
>+	struct fixed31_32 a2;
>+	struct fixed31_32 a3;
>+	struct fixed31_32 gamma;
>+};
>+
> void setup_x_points_distribution(void);
>+void log_x_points_distribution(struct dal_logger *logger);
> void precompute_pq(void);
> void precompute_de_pq(void);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/freesync/freesync.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/freesync/freesync.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/freesync/freesync.c	2019-08-31 15:01:11.872736169 -0500
>@@ -52,93 +52,6 @@
> 	struct dc *dc;
> };
> 
>-void setFieldWithMask(unsigned char *dest, unsigned int mask, unsigned int value)
>-{
>-	unsigned int shift = 0;
>-
>-	if (!mask || !dest)
>-		return;
>-
>-	while (!((mask >> shift) & 1))
>-		shift++;
>-
>-	//reset
>-	*dest = *dest & ~mask;
>-	//set
>-	//dont let value span past mask
>-	value = value & (mask >> shift);
>-	//insert value
>-	*dest = *dest | (value << shift);
>-}
>-
>-// VTEM Byte Offset
>-#define VRR_VTEM_PB0		0
>-#define VRR_VTEM_PB1		1
>-#define VRR_VTEM_PB2		2
>-#define VRR_VTEM_PB3		3
>-#define VRR_VTEM_PB4		4
>-#define VRR_VTEM_PB5		5
>-#define VRR_VTEM_PB6		6
>-
>-#define VRR_VTEM_MD0		7
>-#define VRR_VTEM_MD1		8
>-#define VRR_VTEM_MD2		9
>-#define VRR_VTEM_MD3		10
>-
>-
>-// VTEM Byte Masks
>-//PB0
>-#define MASK__VRR_VTEM_PB0__RESERVED0  0x01
>-#define MASK__VRR_VTEM_PB0__SYNC       0x02
>-#define MASK__VRR_VTEM_PB0__VFR        0x04
>-#define MASK__VRR_VTEM_PB0__AFR        0x08
>-#define MASK__VRR_VTEM_PB0__DS_TYPE    0x30
>-	//0: Periodic pseudo-static EM Data Set
>-	//1: Periodic dynamic EM Data Set
>-	//2: Unique EM Data Set
>-	//3: Reserved
>-#define MASK__VRR_VTEM_PB0__END        0x40
>-#define MASK__VRR_VTEM_PB0__NEW        0x80
>-
>-//PB1
>-#define MASK__VRR_VTEM_PB1__RESERVED1 0xFF
>-
>-//PB2
>-#define MASK__VRR_VTEM_PB2__ORGANIZATION_ID 0xFF
>-	//0: This is a Vendor Specific EM Data Set
>-	//1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean)
>-	//2: This EM Data Set is defined by CTA-861-G
>-	//3: This EM Data Set is defined by VESA
>-//PB3
>-#define MASK__VRR_VTEM_PB3__DATA_SET_TAG_MSB    0xFF
>-//PB4
>-#define MASK__VRR_VTEM_PB4__DATA_SET_TAG_LSB    0xFF
>-//PB5
>-#define MASK__VRR_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF
>-//PB6
>-#define MASK__VRR_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF
>-
>-
>-
>-//PB7-27 (20 bytes):
>-//PB7 = MD0
>-#define MASK__VRR_VTEM_MD0__VRR_EN         0x01
>-#define MASK__VRR_VTEM_MD0__M_CONST        0x02
>-#define MASK__VRR_VTEM_MD0__RESERVED2      0x0C
>-#define MASK__VRR_VTEM_MD0__FVA_FACTOR_M1  0xF0
>-
>-//MD1
>-#define MASK__VRR_VTEM_MD1__BASE_VFRONT    0xFF
>-
>-//MD2
>-#define MASK__VRR_VTEM_MD2__BASE_REFRESH_RATE_98  0x03
>-#define MASK__VRR_VTEM_MD2__RB                    0x04
>-#define MASK__VRR_VTEM_MD2__RESERVED3             0xF8
>-
>-//MD3
>-#define MASK__VRR_VTEM_MD3__BASE_REFRESH_RATE_07  0xFF
>-
>-
> #define MOD_FREESYNC_TO_CORE(mod_freesync)\
> 		container_of(mod_freesync, struct core_freesync, public)
> 
>@@ -435,6 +348,12 @@
> 		/* Either we've calculated the number of frames to insert,
> 		 * or we need to insert min duration frames
> 		 */
>+		if (last_render_time_in_us / frames_to_insert <
>+				in_out_vrr->min_duration_in_us){
>+			frames_to_insert -= (frames_to_insert > 1) ?
>+					1 : 0;
>+		}
>+
> 		if (frames_to_insert > 0)
> 			inserted_frame_duration_in_us = last_render_time_in_us /
> 							frames_to_insert;
>@@ -568,22 +487,64 @@
> 	return false;
> }
> 
>-static void build_vrr_infopacket_header_vtem(enum signal_type signal,
>+static void build_vrr_infopacket_data(const struct mod_vrr_params *vrr,
>+		struct dc_info_packet *infopacket)
>+{
>+	/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
>+	infopacket->sb[1] = 0x1A;
>+
>+	/* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
>+	infopacket->sb[2] = 0x00;
>+
>+	/* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
>+	infopacket->sb[3] = 0x00;
>+
>+	/* PB4 = Reserved */
>+
>+	/* PB5 = Reserved */
>+
>+	/* PB6 = [Bits 7:3 = Reserved] */
>+
>+	/* PB6 = [Bit 0 = FreeSync Supported] */
>+	if (vrr->state != VRR_STATE_UNSUPPORTED)
>+		infopacket->sb[6] |= 0x01;
>+
>+	/* PB6 = [Bit 1 = FreeSync Enabled] */
>+	if (vrr->state != VRR_STATE_DISABLED &&
>+			vrr->state != VRR_STATE_UNSUPPORTED)
>+		infopacket->sb[6] |= 0x02;
>+
>+	/* PB6 = [Bit 2 = FreeSync Active] */
>+	if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
>+			vrr->state == VRR_STATE_ACTIVE_FIXED)
>+		infopacket->sb[6] |= 0x04;
>+
>+	/* PB7 = FreeSync Minimum refresh rate (Hz) */
>+	infopacket->sb[7] = (unsigned char)(vrr->min_refresh_in_uhz / 1000000);
>+
>+	/* PB8 = FreeSync Maximum refresh rate (Hz)
>+	 * Note: We should never go above the field rate of the mode timing set.
>+	 */
>+	infopacket->sb[8] = (unsigned char)(vrr->max_refresh_in_uhz / 1000000);
>+
>+
>+	//FreeSync HDR
>+	infopacket->sb[9] = 0;
>+	infopacket->sb[10] = 0;
>+}
>+
>+static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
> 		struct dc_info_packet *infopacket)
> {
>-	// HEADER
>+	if (app_tf != TRANSFER_FUNC_UNKNOWN) {
>+		infopacket->valid = true;
> 
>-	// HB0, HB1, HB2 indicates PacketType VTEMPacket
>-	infopacket->hb0 = 0x7F;
>-	infopacket->hb1 = 0xC0;
>-	infopacket->hb2 = 0x00; //sequence_index
>-
>-	setFieldWithMask(&infopacket->sb[VRR_VTEM_PB0], MASK__VRR_VTEM_PB0__VFR, 1);
>-	setFieldWithMask(&infopacket->sb[VRR_VTEM_PB2], MASK__VRR_VTEM_PB2__ORGANIZATION_ID, 1);
>-	setFieldWithMask(&infopacket->sb[VRR_VTEM_PB3], MASK__VRR_VTEM_PB3__DATA_SET_TAG_MSB, 0);
>-	setFieldWithMask(&infopacket->sb[VRR_VTEM_PB4], MASK__VRR_VTEM_PB4__DATA_SET_TAG_LSB, 1);
>-	setFieldWithMask(&infopacket->sb[VRR_VTEM_PB5], MASK__VRR_VTEM_PB5__DATA_SET_LENGTH_MSB, 0);
>-	setFieldWithMask(&infopacket->sb[VRR_VTEM_PB6], MASK__VRR_VTEM_PB6__DATA_SET_LENGTH_LSB, 4);
>+		infopacket->sb[6] |= 0x08;  // PB6 = [Bit 3 = Native Color Active]
>+
>+		if (app_tf == TRANSFER_FUNC_GAMMA_22) {
>+			infopacket->sb[9] |= 0x04;  // PB6 = [Bit 2 = Gamma 2.2 EOTF Active]
>+		}
>+	}
> }
> 
> static void build_vrr_infopacket_header_v1(enum signal_type signal,
>@@ -684,105 +645,6 @@
> 	}
> }
> 
>-static void build_vrr_vtem_infopacket_data(const struct dc_stream_state *stream,
>-		const struct mod_vrr_params *vrr,
>-		struct dc_info_packet *infopacket)
>-{
>-	unsigned int fieldRateInHz;
>-
>-	if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
>-				vrr->state == VRR_STATE_ACTIVE_FIXED) {
>-		setFieldWithMask(&infopacket->sb[VRR_VTEM_MD0], MASK__VRR_VTEM_MD0__VRR_EN, 1);
>-	} else {
>-		setFieldWithMask(&infopacket->sb[VRR_VTEM_MD0], MASK__VRR_VTEM_MD0__VRR_EN, 0);
>-	}
>-
>-	if (!stream->timing.vic) {
>-		setFieldWithMask(&infopacket->sb[VRR_VTEM_MD1], MASK__VRR_VTEM_MD1__BASE_VFRONT,
>-				stream->timing.v_front_porch);
>-
>-
>-		/* TODO: In dal2, we check mode flags for a reduced blanking timing.
>-		 * Need a way to relay that information to this function.
>-		 * if("ReducedBlanking")
>-		 * {
>-		 *   setFieldWithMask(&infopacket->sb[VRR_VTEM_MD2], MASK__VRR_VTEM_MD2__RB, 1;
>-		 * }
>-		 */
>-
>-		//TODO: DAL2 does FixPoint and rounding. Here we might need to account for that
>-		fieldRateInHz = (stream->timing.pix_clk_100hz * 100)/
>-			(stream->timing.h_total * stream->timing.v_total);
>-
>-		setFieldWithMask(&infopacket->sb[VRR_VTEM_MD2],  MASK__VRR_VTEM_MD2__BASE_REFRESH_RATE_98,
>-				fieldRateInHz >> 8);
>-		setFieldWithMask(&infopacket->sb[VRR_VTEM_MD3], MASK__VRR_VTEM_MD3__BASE_REFRESH_RATE_07,
>-				fieldRateInHz);
>-
>-	}
>-	infopacket->valid = true;
>-}
>-
>-static void build_vrr_infopacket_data(const struct mod_vrr_params *vrr,
>-		struct dc_info_packet *infopacket)
>-{
>-	/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
>-	infopacket->sb[1] = 0x1A;
>-
>-	/* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
>-	infopacket->sb[2] = 0x00;
>-
>-	/* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
>-	infopacket->sb[3] = 0x00;
>-
>-	/* PB4 = Reserved */
>-
>-	/* PB5 = Reserved */
>-
>-	/* PB6 = [Bits 7:3 = Reserved] */
>-
>-	/* PB6 = [Bit 0 = FreeSync Supported] */
>-	if (vrr->state != VRR_STATE_UNSUPPORTED)
>-		infopacket->sb[6] |= 0x01;
>-
>-	/* PB6 = [Bit 1 = FreeSync Enabled] */
>-	if (vrr->state != VRR_STATE_DISABLED &&
>-			vrr->state != VRR_STATE_UNSUPPORTED)
>-		infopacket->sb[6] |= 0x02;
>-
>-	/* PB6 = [Bit 2 = FreeSync Active] */
>-	if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
>-			vrr->state == VRR_STATE_ACTIVE_FIXED)
>-		infopacket->sb[6] |= 0x04;
>-
>-	/* PB7 = FreeSync Minimum refresh rate (Hz) */
>-	infopacket->sb[7] = (unsigned char)(vrr->min_refresh_in_uhz / 1000000);
>-
>-	/* PB8 = FreeSync Maximum refresh rate (Hz)
>-	 * Note: We should never go above the field rate of the mode timing set.
>-	 */
>-	infopacket->sb[8] = (unsigned char)(vrr->max_refresh_in_uhz / 1000000);
>-
>-
>-	//FreeSync HDR
>-	infopacket->sb[9] = 0;
>-	infopacket->sb[10] = 0;
>-}
>-
>-static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
>-		struct dc_info_packet *infopacket)
>-{
>-	if (app_tf != TRANSFER_FUNC_UNKNOWN) {
>-		infopacket->valid = true;
>-
>-		infopacket->sb[6] |= 0x08;  // PB6 = [Bit 3 = Native Color Active]
>-
>-		if (app_tf == TRANSFER_FUNC_GAMMA_22) {
>-			infopacket->sb[9] |= 0x04;  // PB6 = [Bit 2 = Gamma 2.2 EOTF Active]
>-		}
>-	}
>-}
>-
> static void build_vrr_infopacket_checksum(unsigned int *payload_size,
> 		struct dc_info_packet *infopacket)
> {
>@@ -835,21 +697,6 @@
> 	infopacket->valid = true;
> }
> 
>-static void build_vrr_infopacket_vtem(const struct dc_stream_state *stream,
>-		const struct mod_vrr_params *vrr,
>-		struct dc_info_packet *infopacket)
>-{
>-	//VTEM info packet for HdmiVrr
>-
>-	memset(infopacket, 0, sizeof(struct dc_info_packet));
>-
>-	//VTEM Packet is structured differently
>-	build_vrr_infopacket_header_vtem(stream->signal, infopacket);
>-	build_vrr_vtem_infopacket_data(stream, vrr, infopacket);
>-
>-	infopacket->valid = true;
>-}
>-
> void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
> 		const struct dc_stream_state *stream,
> 		const struct mod_vrr_params *vrr,
>@@ -862,16 +709,13 @@
> 	 * Check if Freesync is supported. Return if false. If true,
> 	 * set the corresponding bit in the info packet
> 	 */
>-	if (!vrr->supported || (!vrr->send_info_frame && packet_type != PACKET_TYPE_VTEM))
>+	if (!vrr->supported || (!vrr->send_info_frame))
> 		return;
> 
> 	switch (packet_type) {
> 	case PACKET_TYPE_FS2:
> 		build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket);
> 		break;
>-	case PACKET_TYPE_VTEM:
>-		build_vrr_infopacket_vtem(stream, vrr, infopacket);
>-		break;
> 	case PACKET_TYPE_VRR:
> 	case PACKET_TYPE_FS1:
> 	default:
>@@ -887,8 +731,8 @@
> 	struct core_freesync *core_freesync = NULL;
> 	unsigned long long nominal_field_rate_in_uhz = 0;
> 	unsigned int refresh_range = 0;
>-	unsigned int min_refresh_in_uhz = 0;
>-	unsigned int max_refresh_in_uhz = 0;
>+	unsigned long long min_refresh_in_uhz = 0;
>+	unsigned long long max_refresh_in_uhz = 0;
> 
> 	if (mod_freesync == NULL)
> 		return;
>@@ -915,7 +759,7 @@
> 		min_refresh_in_uhz = nominal_field_rate_in_uhz;
> 
> 	if (!vrr_settings_require_update(core_freesync,
>-			in_config, min_refresh_in_uhz, max_refresh_in_uhz,
>+			in_config, (unsigned int)min_refresh_in_uhz, (unsigned int)max_refresh_in_uhz,
> 			in_out_vrr))
> 		return;
> 
>@@ -931,15 +775,15 @@
> 		return;
> 
> 	} else {
>-		in_out_vrr->min_refresh_in_uhz = min_refresh_in_uhz;
>+		in_out_vrr->min_refresh_in_uhz = (unsigned int)min_refresh_in_uhz;
> 		in_out_vrr->max_duration_in_us =
> 				calc_duration_in_us_from_refresh_in_uhz(
>-						min_refresh_in_uhz);
>+						(unsigned int)min_refresh_in_uhz);
> 
>-		in_out_vrr->max_refresh_in_uhz = max_refresh_in_uhz;
>+		in_out_vrr->max_refresh_in_uhz = (unsigned int)max_refresh_in_uhz;
> 		in_out_vrr->min_duration_in_us =
> 				calc_duration_in_us_from_refresh_in_uhz(
>-						max_refresh_in_uhz);
>+						(unsigned int)max_refresh_in_uhz);
> 
> 		refresh_range = in_out_vrr->max_refresh_in_uhz -
> 				in_out_vrr->min_refresh_in_uhz;
>@@ -950,17 +794,18 @@
> 	in_out_vrr->fixed.ramping_active = in_config->ramping;
> 
> 	in_out_vrr->btr.btr_enabled = in_config->btr;
>+
> 	if (in_out_vrr->max_refresh_in_uhz <
> 			2 * in_out_vrr->min_refresh_in_uhz)
> 		in_out_vrr->btr.btr_enabled = false;
>+
> 	in_out_vrr->btr.btr_active = false;
> 	in_out_vrr->btr.inserted_duration_in_us = 0;
> 	in_out_vrr->btr.frames_to_insert = 0;
> 	in_out_vrr->btr.frame_counter = 0;
> 	in_out_vrr->btr.mid_point_in_us =
>-			in_out_vrr->min_duration_in_us +
>-				(in_out_vrr->max_duration_in_us -
>-				in_out_vrr->min_duration_in_us) / 2;
>+				(in_out_vrr->min_duration_in_us +
>+				 in_out_vrr->max_duration_in_us) / 2;
> 
> 	if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {
> 		in_out_vrr->adjust.v_total_min = stream->timing.v_total;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h	2019-08-31 15:01:11.872736169 -0500
>@@ -173,4 +173,6 @@
> 		uint32_t min_refresh_request_in_uhz,
> 		uint32_t max_refresh_request_in_uhz);
> 
>+
>+
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h	2019-08-31 15:01:11.872736169 -0500
>@@ -27,10 +27,10 @@
> #define MOD_INFO_PACKET_H_
> 
> #include "mod_shared.h"
>-
> //Forward Declarations
> struct dc_stream_state;
> struct dc_info_packet;
>+struct mod_vrr_params;
> 
> void mod_build_vsc_infopacket(const struct dc_stream_state *stream,
> 		struct dc_info_packet *info_packet);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c	2019-08-31 15:01:11.872736169 -0500
>@@ -27,9 +27,78 @@
> #include "core_types.h"
> #include "dc_types.h"
> #include "mod_shared.h"
>+#include "mod_freesync.h"
>+#include "dc.h"
> 
> #define HDMI_INFOFRAME_TYPE_VENDOR 0x81
> 
>+// VTEM Byte Offset
>+#define VTEM_PB0		0
>+#define VTEM_PB1		1
>+#define VTEM_PB2		2
>+#define VTEM_PB3		3
>+#define VTEM_PB4		4
>+#define VTEM_PB5		5
>+#define VTEM_PB6		6
>+
>+#define VTEM_MD0		7
>+#define VTEM_MD1		8
>+#define VTEM_MD2		9
>+#define VTEM_MD3		10
>+
>+
>+// VTEM Byte Masks
>+//PB0
>+#define MASK_VTEM_PB0__RESERVED0  0x01
>+#define MASK_VTEM_PB0__SYNC       0x02
>+#define MASK_VTEM_PB0__VFR        0x04
>+#define MASK_VTEM_PB0__AFR        0x08
>+#define MASK_VTEM_PB0__DS_TYPE    0x30
>+	//0: Periodic pseudo-static EM Data Set
>+	//1: Periodic dynamic EM Data Set
>+	//2: Unique EM Data Set
>+	//3: Reserved
>+#define MASK_VTEM_PB0__END        0x40
>+#define MASK_VTEM_PB0__NEW        0x80
>+
>+//PB1
>+#define MASK_VTEM_PB1__RESERVED1 0xFF
>+
>+//PB2
>+#define MASK_VTEM_PB2__ORGANIZATION_ID 0xFF
>+	//0: This is a Vendor Specific EM Data Set
>+	//1: This EM Data Set is defined by This Specification (HDMI 2.1 r102.clean)
>+	//2: This EM Data Set is defined by CTA-861-G
>+	//3: This EM Data Set is defined by VESA
>+//PB3
>+#define MASK_VTEM_PB3__DATA_SET_TAG_MSB    0xFF
>+//PB4
>+#define MASK_VTEM_PB4__DATA_SET_TAG_LSB    0xFF
>+//PB5
>+#define MASK_VTEM_PB5__DATA_SET_LENGTH_MSB 0xFF
>+//PB6
>+#define MASK_VTEM_PB6__DATA_SET_LENGTH_LSB 0xFF
>+
>+
>+
>+//PB7-27 (20 bytes):
>+//PB7 = MD0
>+#define MASK_VTEM_MD0__VRR_EN         0x01
>+#define MASK_VTEM_MD0__M_CONST        0x02
>+#define MASK_VTEM_MD0__RESERVED2      0x0C
>+#define MASK_VTEM_MD0__FVA_FACTOR_M1  0xF0
>+
>+//MD1
>+#define MASK_VTEM_MD1__BASE_VFRONT    0xFF
>+
>+//MD2
>+#define MASK_VTEM_MD2__BASE_REFRESH_RATE_98  0x03
>+#define MASK_VTEM_MD2__RB                    0x04
>+#define MASK_VTEM_MD2__RESERVED3             0xF8
>+
>+//MD3
>+#define MASK_VTEM_MD3__BASE_REFRESH_RATE_07  0xFF
>+
> enum ColorimetryRGBDP {
> 	ColorimetryRGB_DP_sRGB               = 0,
> 	ColorimetryRGB_DP_AdobeRGB           = 3,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/power/power_helpers.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/display/modules/power/power_helpers.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/display/modules/power/power_helpers.c	2019-08-31 15:01:11.872736169 -0500
>@@ -66,6 +66,39 @@
> {       3,              6,              10,             12      },	/* Alt #3  - Super aggressiveness */
> };
> 
>+struct abm_parameters {
>+	unsigned char min_reduction;
>+	unsigned char max_reduction;
>+	unsigned char bright_pos_gain;
>+	unsigned char dark_pos_gain;
>+	unsigned char brightness_gain;
>+	unsigned char contrast_factor;
>+	unsigned char deviation_gain;
>+	unsigned char min_knee;
>+	unsigned char max_knee;
>+};
>+
>+static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = {
>+//  min_red  max_red  bright_pos  dark_pos  brightness_gain  contrast  deviation  min_knee  max_knee
>+	{0xff,   0xbf,    0x20,       0x00,     0xff,            0x99,     0xb3,      0x40,     0xE0},
>+	{0xff,   0x85,    0x20,       0x00,     0xff,            0x90,     0xa8,      0x40,     0xE0},
>+	{0xff,   0x40,    0x20,       0x00,     0xff,            0x90,     0x68,      0x40,     0xE0},
>+	{0x82,   0x4d,    0x20,       0x00,     0x00,            0x90,     0xb3,      0x70,     0x70},
>+};
>+
>+static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = {
>+//  min_red  max_red  bright_pos  dark_pos  brightness_gain  contrast  deviation  min_knee  max_knee
>+	{0xf0,   0xd9,    0x20,       0x00,     0x00,            0xa8,     0xb3,      0x70,     0x70},
>+	{0xcd,   0xa5,    0x20,       0x00,     0x00,            0xa8,     0xb3,      0x70,     0x70},
>+	{0x99,   0x65,    0x20,       0x00,     0x00,            0xa8,     0xb3,      0x70,     0x70},
>+	{0x82,   0x4d,    0x20,       0x00,     0x00,            0xa8,     0xb3,      0x70,     0x70},
>+};
>+
>+static const struct abm_parameters * const abm_settings[] = {
>+	abm_settings_config0,
>+	abm_settings_config1,
>+};
>+
> #define NUM_AMBI_LEVEL    5
> #define NUM_AGGR_LEVEL    4
> #define NUM_POWER_FN_SEGS 8
>@@ -131,11 +164,13 @@
> 	uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];		/* 0x16 U0.8 */
> 	uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];	/* 0x2a U2.6 */
> 	uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL];		/* 0x3e U2.6 */
>-	uint8_t hybridFactor[NUM_AGGR_LEVEL];						/* 0x52 U0.8 */
>-	uint8_t contrastFactor[NUM_AGGR_LEVEL];						/* 0x56 U0.8 */
>+	uint8_t hybrid_factor[NUM_AGGR_LEVEL];						/* 0x52 U0.8 */
>+	uint8_t contrast_factor[NUM_AGGR_LEVEL];					/* 0x56 U0.8 */
> 	uint8_t deviation_gain[NUM_AGGR_LEVEL];						/* 0x5a U0.8 */
> 	uint8_t iir_curve[NUM_AMBI_LEVEL];							/* 0x5e U0.8 */
>-	uint8_t pad[29];											/* 0x63 U0.8 */
>+	uint8_t min_knee[NUM_AGGR_LEVEL];							/* 0x63 U0.8 */
>+	uint8_t max_knee[NUM_AGGR_LEVEL];							/* 0x67 U0.8 */
>+	uint8_t pad[21];											/* 0x6b U0.8 */
> 
> 	/* parameters for crgb conversion */
> 	uint16_t crgb_thresh[NUM_POWER_FN_SEGS];					/* 0x80 U3.13 */
>@@ -501,15 +536,72 @@
> 	ram_table->dark_pos_gain[4][2] = 0x00;
> 	ram_table->dark_pos_gain[4][3] = 0x00;
> 
>-	ram_table->hybridFactor[0] = 0xff;
>-	ram_table->hybridFactor[1] = 0xff;
>-	ram_table->hybridFactor[2] = 0xff;
>-	ram_table->hybridFactor[3] = 0xc0;
>-
>-	ram_table->contrastFactor[0] = 0x99;
>-	ram_table->contrastFactor[1] = 0x99;
>-	ram_table->contrastFactor[2] = 0x90;
>-	ram_table->contrastFactor[3] = 0x80;
>+	ram_table->hybrid_factor[0] = 0xff;
>+	ram_table->hybrid_factor[1] = 0xff;
>+	ram_table->hybrid_factor[2] = 0xff;
>+	ram_table->hybrid_factor[3] = 0xc0;
>+
>+	ram_table->contrast_factor[0] = 0x99;
>+	ram_table->contrast_factor[1] = 0x99;
>+	ram_table->contrast_factor[2] = 0x90;
>+	ram_table->contrast_factor[3] = 0x80;
>+
>+	ram_table->iir_curve[0] = 0x65;
>+	ram_table->iir_curve[1] = 0x65;
>+	ram_table->iir_curve[2] = 0x65;
>+	ram_table->iir_curve[3] = 0x65;
>+	ram_table->iir_curve[4] = 0x65;
>+
>+	//Gamma 2.2
>+	ram_table->crgb_thresh[0] = cpu_to_be16(0x127c);
>+	ram_table->crgb_thresh[1] = cpu_to_be16(0x151b);
>+	ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5);
>+	ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56);
>+	ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83);
>+	ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72);
>+	ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0);
>+	ram_table->crgb_thresh[7] = cpu_to_be16(0x232b);
>+	ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
>+	ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
>+	ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
>+	ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
>+	ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
>+	ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
>+	ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
>+	ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
>+	ram_table->crgb_slope[0]  = cpu_to_be16(0x3609);
>+	ram_table->crgb_slope[1]  = cpu_to_be16(0x2dfa);
>+	ram_table->crgb_slope[2]  = cpu_to_be16(0x27ea);
>+	ram_table->crgb_slope[3]  = cpu_to_be16(0x235d);
>+	ram_table->crgb_slope[4]  = cpu_to_be16(0x2042);
>+	ram_table->crgb_slope[5]  = cpu_to_be16(0x1dc3);
>+	ram_table->crgb_slope[6]  = cpu_to_be16(0x1b1a);
>+	ram_table->crgb_slope[7]  = cpu_to_be16(0x1910);
>+
>+	fill_backlight_transform_table_v_2_2(
>+			params, ram_table);
>+}
>+
>+void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params)
>+{
>+	unsigned int i, j;
>+	unsigned int set = params.set;
>+
>+	ram_table->flags = 0x0;
>+	for (i = 0; i < NUM_AGGR_LEVEL; i++) {
>+		ram_table->hybrid_factor[i] = abm_settings[set][i].brightness_gain;
>+		ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor;
>+		ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain;
>+		ram_table->min_knee[i] = abm_settings[set][i].min_knee;
>+		ram_table->max_knee[i] = abm_settings[set][i].max_knee;
>+
>+		for (j = 0; j < NUM_AMBI_LEVEL; j++) {
>+			ram_table->min_reduction[j][i] = abm_settings[set][i].min_reduction;
>+			ram_table->max_reduction[j][i] = abm_settings[set][i].max_reduction;
>+			ram_table->bright_pos_gain[j][i] = abm_settings[set][i].bright_pos_gain;
>+			ram_table->dark_pos_gain[j][i] = abm_settings[set][i].dark_pos_gain;
>+		}
>+	}
> 
> 	ram_table->iir_curve[0] = 0x65;
> 	ram_table->iir_curve[1] = 0x65;
>@@ -561,7 +653,12 @@
> 
> 	memset(&ram_table, 0, sizeof(ram_table));
> 
>-	if (dmcu->dmcu_version.abm_version == 0x22) {
>+	if (dmcu->dmcu_version.abm_version == 0x23) {
>+		fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params);
>+
>+		result = dmcu->funcs->load_iram(
>+				dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);
>+	} else if (dmcu->dmcu_version.abm_version == 0x22) {
> 		fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params);
> 
> 		result = dmcu->funcs->load_iram(
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/amd_shared.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/amd_shared.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/amd_shared.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/amd_shared.h	2019-08-31 15:01:11.872736169 -0500
>@@ -142,6 +142,7 @@
> 
> enum DC_FEATURE_MASK {
> 	DC_FBC_MASK = 0x1,
>+	DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
> };
> 
> enum amd_dpm_forced_level;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/arct_ip_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/arct_ip_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/arct_ip_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/arct_ip_offset.h	2019-08-31 15:01:11.873736170 -0500
>@@ -0,0 +1,1650 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _arct_ip_offset_HEADER
>+#define _arct_ip_offset_HEADER
>+
>+#define MAX_INSTANCE                                       8
>+#define MAX_SEGMENT                                         6
>+
>+
>+struct IP_BASE_INSTANCE
>+{
>+    unsigned int segment[MAX_SEGMENT];
>+};
>+
>+struct IP_BASE
>+{
>+    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
>+};
>+
>+
>+static const struct IP_BASE ATHUB_BASE            ={ { { { 0x00000C20, 0x00012460, 0x00408C00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE CLK_BASE            ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } },
>+                                        { { 0x000120E0, 0x00016E00, 0x00401C00, 0, 0, 0 } },
>+                                        { { 0x00012100, 0x00017000, 0x00402000, 0, 0, 0 } },
>+                                        { { 0x00012120, 0x00017200, 0x00402400, 0, 0, 0 } },
>+                                        { { 0x000136C0, 0x0001B000, 0x0042D800, 0, 0, 0 } },
>+                                        { { 0x00013720, 0x0001B200, 0x0042E400, 0, 0, 0 } },
>+                                        { { 0x000125E0, 0x00017E00, 0x0040BC00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DF_BASE            ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE FUSE_BASE            ={ { { { 0x000120A0, 0x00017400, 0x00401400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE GC_BASE            ={ { { { 0x00002000, 0x0000A000, 0x00012160, 0x00402C00, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE HDP_BASE            ={ { { { 0x00000F20, 0x00012520, 0x0040A400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE MMHUB_BASE            ={ { { { 0x00012440, 0x0001A000, 0x00408800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE MP0_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE MP1_BASE            ={ { { { 0x00016000, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE NBIF0_BASE            ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x00012D80, 0x0041B000 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE OSSSYS_BASE            ={ { { { 0x000010A0, 0x00012500, 0x0040A000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE PCIE0_BASE            ={ { { { 0x000128C0, 0x00411800, 0x04440000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SDMA0_BASE            ={ { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SDMA1_BASE            ={ { { { 0x00001860, 0x00012560, 0x0040AC00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SDMA2_BASE            ={ { { { 0x00013760, 0x0001E000, 0x0042EC00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SDMA3_BASE            ={ { { { 0x00013780, 0x0001E400, 0x0042F000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SDMA4_BASE            ={ { { { 0x000137A0, 0x0001E800, 0x0042F400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SDMA5_BASE            ={ { { { 0x000137C0, 0x0001EC00, 0x0042F800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SDMA6_BASE            ={ { { { 0x000137E0, 0x0001F000, 0x0042FC00, 0, 0, 0 } },
>+                                       { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SDMA7_BASE            ={ { { { 0x00013800, 0x0001F400, 0x00430000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SMUIO_BASE            ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE THM_BASE            ={ { { { 0x00016600, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE UMC_BASE            ={ { { { 0x000132C0, 0x00014000, 0x00425800, 0, 0, 0 } },
>+                                        { { 0x000132E0, 0x00054000, 0x00425C00, 0, 0, 0 } },
>+                                        { { 0x00013300, 0x00094000, 0x00426000, 0, 0, 0 } },
>+                                        { { 0x00013320, 0x000D4000, 0x00426400, 0, 0, 0 } },
>+                                        { { 0x00013340, 0x00114000, 0x00426800, 0, 0, 0 } },
>+                                        { { 0x00013360, 0x00154000, 0x00426C00, 0, 0, 0 } },
>+                                        { { 0x00013380, 0x00194000, 0x00427000, 0, 0, 0 } },
>+                                        { { 0x000133A0, 0x001D4000, 0x00427400, 0, 0, 0 } } } };
>+static const struct IP_BASE UVD_BASE            ={ { { { 0x00007800, 0x00007E00, 0x00012180, 0x00403000, 0, 0 } },
>+                                        { { 0x00007A00, 0x00009000, 0x000136E0, 0x0042DC00, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DBGU_IO_BASE            ={ { { { 0x000001E0, 0x000125A0, 0x0040B400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE RSMU_BASE            ={ { { { 0x00012000, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0, 0 } } } };
>+
>+
>+
>+#define ATHUB_BASE__INST0_SEG0                     0x00000C20
>+#define ATHUB_BASE__INST0_SEG1                     0x00012460
>+#define ATHUB_BASE__INST0_SEG2                     0x00408C00
>+#define ATHUB_BASE__INST0_SEG3                     0
>+#define ATHUB_BASE__INST0_SEG4                     0
>+#define ATHUB_BASE__INST0_SEG5                     0
>+
>+#define ATHUB_BASE__INST1_SEG0                     0
>+#define ATHUB_BASE__INST1_SEG1                     0
>+#define ATHUB_BASE__INST1_SEG2                     0
>+#define ATHUB_BASE__INST1_SEG3                     0
>+#define ATHUB_BASE__INST1_SEG4                     0
>+#define ATHUB_BASE__INST1_SEG5                     0
>+
>+#define ATHUB_BASE__INST2_SEG0                     0
>+#define ATHUB_BASE__INST2_SEG1                     0
>+#define ATHUB_BASE__INST2_SEG2                     0
>+#define ATHUB_BASE__INST2_SEG3                     0
>+#define ATHUB_BASE__INST2_SEG4                     0
>+#define ATHUB_BASE__INST2_SEG5                     0
>+
>+#define ATHUB_BASE__INST3_SEG0                     0
>+#define ATHUB_BASE__INST3_SEG1                     0
>+#define ATHUB_BASE__INST3_SEG2                     0
>+#define ATHUB_BASE__INST3_SEG3                     0
>+#define ATHUB_BASE__INST3_SEG4                     0
>+#define ATHUB_BASE__INST3_SEG5                     0
>+
>+#define ATHUB_BASE__INST4_SEG0                     0
>+#define ATHUB_BASE__INST4_SEG1                     0
>+#define ATHUB_BASE__INST4_SEG2                     0
>+#define ATHUB_BASE__INST4_SEG3                     0
>+#define ATHUB_BASE__INST4_SEG4                     0
>+#define ATHUB_BASE__INST4_SEG5                     0
>+
>+#define ATHUB_BASE__INST5_SEG0                     0
>+#define ATHUB_BASE__INST5_SEG1                     0
>+#define ATHUB_BASE__INST5_SEG2                     0
>+#define ATHUB_BASE__INST5_SEG3                     0
>+#define ATHUB_BASE__INST5_SEG4                     0
>+#define ATHUB_BASE__INST5_SEG5                     0
>+
>+#define ATHUB_BASE__INST6_SEG0                     0
>+#define ATHUB_BASE__INST6_SEG1                     0
>+#define ATHUB_BASE__INST6_SEG2                     0
>+#define ATHUB_BASE__INST6_SEG3                     0
>+#define ATHUB_BASE__INST6_SEG4                     0
>+#define ATHUB_BASE__INST6_SEG5                     0
>+
>+#define ATHUB_BASE__INST7_SEG0                     0
>+#define ATHUB_BASE__INST7_SEG1                     0
>+#define ATHUB_BASE__INST7_SEG2                     0
>+#define ATHUB_BASE__INST7_SEG3                     0
>+#define ATHUB_BASE__INST7_SEG4                     0
>+#define ATHUB_BASE__INST7_SEG5                     0
>+
>+#define CLK_BASE__INST0_SEG0                       0x000120C0
>+#define CLK_BASE__INST0_SEG1                       0x00016C00
>+#define CLK_BASE__INST0_SEG2                       0x00401800
>+#define CLK_BASE__INST0_SEG3                       0
>+#define CLK_BASE__INST0_SEG4                       0
>+#define CLK_BASE__INST0_SEG5                       0
>+
>+#define CLK_BASE__INST1_SEG0                       0x000120E0
>+#define CLK_BASE__INST1_SEG1                       0x00016E00
>+#define CLK_BASE__INST1_SEG2                       0x00401C00
>+#define CLK_BASE__INST1_SEG3                       0
>+#define CLK_BASE__INST1_SEG4                       0
>+#define CLK_BASE__INST1_SEG5                       0
>+
>+#define CLK_BASE__INST2_SEG0                       0x00012100
>+#define CLK_BASE__INST2_SEG1                       0x00017000
>+#define CLK_BASE__INST2_SEG2                       0x00402000
>+#define CLK_BASE__INST2_SEG3                       0
>+#define CLK_BASE__INST2_SEG4                       0
>+#define CLK_BASE__INST2_SEG5                       0
>+
>+#define CLK_BASE__INST3_SEG0                       0x00012120
>+#define CLK_BASE__INST3_SEG1                       0x00017200
>+#define CLK_BASE__INST3_SEG2                       0x00402400
>+#define CLK_BASE__INST3_SEG3                       0
>+#define CLK_BASE__INST3_SEG4                       0
>+#define CLK_BASE__INST3_SEG5                       0
>+
>+#define CLK_BASE__INST4_SEG0                       0x000136C0
>+#define CLK_BASE__INST4_SEG1                       0x0001B000
>+#define CLK_BASE__INST4_SEG2                       0x0042D800
>+#define CLK_BASE__INST4_SEG3                       0
>+#define CLK_BASE__INST4_SEG4                       0
>+#define CLK_BASE__INST4_SEG5                       0
>+
>+#define CLK_BASE__INST5_SEG0                       0x00013720
>+#define CLK_BASE__INST5_SEG1                       0x0001B200
>+#define CLK_BASE__INST5_SEG2                       0x0042E400
>+#define CLK_BASE__INST5_SEG3                       0
>+#define CLK_BASE__INST5_SEG4                       0
>+#define CLK_BASE__INST5_SEG5                       0
>+
>+#define CLK_BASE__INST6_SEG0                       0x000125E0
>+#define CLK_BASE__INST6_SEG1                       0x00017E00
>+#define CLK_BASE__INST6_SEG2                       0x0040BC00
>+#define CLK_BASE__INST6_SEG3                       0
>+#define CLK_BASE__INST6_SEG4                       0
>+#define CLK_BASE__INST6_SEG5                       0
>+
>+#define CLK_BASE__INST7_SEG0                       0
>+#define CLK_BASE__INST7_SEG1                       0
>+#define CLK_BASE__INST7_SEG2                       0
>+#define CLK_BASE__INST7_SEG3                       0
>+#define CLK_BASE__INST7_SEG4                       0
>+#define CLK_BASE__INST7_SEG5                       0
>+
>+#define DF_BASE__INST0_SEG0                        0x00007000
>+#define DF_BASE__INST0_SEG1                        0x000125C0
>+#define DF_BASE__INST0_SEG2                        0x0040B800
>+#define DF_BASE__INST0_SEG3                        0
>+#define DF_BASE__INST0_SEG4                        0
>+#define DF_BASE__INST0_SEG5                        0
>+
>+#define DF_BASE__INST1_SEG0                        0
>+#define DF_BASE__INST1_SEG1                        0
>+#define DF_BASE__INST1_SEG2                        0
>+#define DF_BASE__INST1_SEG3                        0
>+#define DF_BASE__INST1_SEG4                        0
>+#define DF_BASE__INST1_SEG5                        0
>+
>+#define DF_BASE__INST2_SEG0                        0
>+#define DF_BASE__INST2_SEG1                        0
>+#define DF_BASE__INST2_SEG2                        0
>+#define DF_BASE__INST2_SEG3                        0
>+#define DF_BASE__INST2_SEG4                        0
>+#define DF_BASE__INST2_SEG5                        0
>+
>+#define DF_BASE__INST3_SEG0                        0
>+#define DF_BASE__INST3_SEG1                        0
>+#define DF_BASE__INST3_SEG2                        0
>+#define DF_BASE__INST3_SEG3                        0
>+#define DF_BASE__INST3_SEG4                        0
>+#define DF_BASE__INST3_SEG5                        0
>+
>+#define DF_BASE__INST4_SEG0                        0
>+#define DF_BASE__INST4_SEG1                        0
>+#define DF_BASE__INST4_SEG2                        0
>+#define DF_BASE__INST4_SEG3                        0
>+#define DF_BASE__INST4_SEG4                        0
>+#define DF_BASE__INST4_SEG5                        0
>+
>+#define DF_BASE__INST5_SEG0                        0
>+#define DF_BASE__INST5_SEG1                        0
>+#define DF_BASE__INST5_SEG2                        0
>+#define DF_BASE__INST5_SEG3                        0
>+#define DF_BASE__INST5_SEG4                        0
>+#define DF_BASE__INST5_SEG5                        0
>+
>+#define DF_BASE__INST6_SEG0                        0
>+#define DF_BASE__INST6_SEG1                        0
>+#define DF_BASE__INST6_SEG2                        0
>+#define DF_BASE__INST6_SEG3                        0
>+#define DF_BASE__INST6_SEG4                        0
>+#define DF_BASE__INST6_SEG5                        0
>+
>+#define DF_BASE__INST7_SEG0                        0
>+#define DF_BASE__INST7_SEG1                        0
>+#define DF_BASE__INST7_SEG2                        0
>+#define DF_BASE__INST7_SEG3                        0
>+#define DF_BASE__INST7_SEG4                        0
>+#define DF_BASE__INST7_SEG5                        0
>+
>+#define FUSE_BASE__INST0_SEG0                      0x000120A0
>+#define FUSE_BASE__INST0_SEG1                      0x00017400
>+#define FUSE_BASE__INST0_SEG2                      0x00401400
>+#define FUSE_BASE__INST0_SEG3                      0
>+#define FUSE_BASE__INST0_SEG4                      0
>+#define FUSE_BASE__INST0_SEG5                      0
>+
>+#define FUSE_BASE__INST1_SEG0                      0
>+#define FUSE_BASE__INST1_SEG1                      0
>+#define FUSE_BASE__INST1_SEG2                      0
>+#define FUSE_BASE__INST1_SEG3                      0
>+#define FUSE_BASE__INST1_SEG4                      0
>+#define FUSE_BASE__INST1_SEG5                      0
>+
>+#define FUSE_BASE__INST2_SEG0                      0
>+#define FUSE_BASE__INST2_SEG1                      0
>+#define FUSE_BASE__INST2_SEG2                      0
>+#define FUSE_BASE__INST2_SEG3                      0
>+#define FUSE_BASE__INST2_SEG4                      0
>+#define FUSE_BASE__INST2_SEG5                      0
>+
>+#define FUSE_BASE__INST3_SEG0                      0
>+#define FUSE_BASE__INST3_SEG1                      0
>+#define FUSE_BASE__INST3_SEG2                      0
>+#define FUSE_BASE__INST3_SEG3                      0
>+#define FUSE_BASE__INST3_SEG4                      0
>+#define FUSE_BASE__INST3_SEG5                      0
>+
>+#define FUSE_BASE__INST4_SEG0                      0
>+#define FUSE_BASE__INST4_SEG1                      0
>+#define FUSE_BASE__INST4_SEG2                      0
>+#define FUSE_BASE__INST4_SEG3                      0
>+#define FUSE_BASE__INST4_SEG4                      0
>+#define FUSE_BASE__INST4_SEG5                      0
>+
>+#define FUSE_BASE__INST5_SEG0                      0
>+#define FUSE_BASE__INST5_SEG1                      0
>+#define FUSE_BASE__INST5_SEG2                      0
>+#define FUSE_BASE__INST5_SEG3                      0
>+#define FUSE_BASE__INST5_SEG4                      0
>+#define FUSE_BASE__INST5_SEG5                      0
>+
>+#define FUSE_BASE__INST6_SEG0                      0
>+#define FUSE_BASE__INST6_SEG1                      0
>+#define FUSE_BASE__INST6_SEG2                      0
>+#define FUSE_BASE__INST6_SEG3                      0
>+#define FUSE_BASE__INST6_SEG4                      0
>+#define FUSE_BASE__INST6_SEG5                      0
>+
>+#define FUSE_BASE__INST7_SEG0                      0
>+#define FUSE_BASE__INST7_SEG1                      0
>+#define FUSE_BASE__INST7_SEG2                      0
>+#define FUSE_BASE__INST7_SEG3                      0
>+#define FUSE_BASE__INST7_SEG4                      0
>+#define FUSE_BASE__INST7_SEG5                      0
>+
>+#define GC_BASE__INST0_SEG0                        0x00002000
>+#define GC_BASE__INST0_SEG1                        0x0000A000
>+#define GC_BASE__INST0_SEG2                        0x00012160
>+#define GC_BASE__INST0_SEG3                        0x00402C00
>+#define GC_BASE__INST0_SEG4                        0
>+#define GC_BASE__INST0_SEG5                        0
>+
>+#define GC_BASE__INST1_SEG0                        0
>+#define GC_BASE__INST1_SEG1                        0
>+#define GC_BASE__INST1_SEG2                        0
>+#define GC_BASE__INST1_SEG3                        0
>+#define GC_BASE__INST1_SEG4                        0
>+#define GC_BASE__INST1_SEG5                        0
>+
>+#define GC_BASE__INST2_SEG0                        0
>+#define GC_BASE__INST2_SEG1                        0
>+#define GC_BASE__INST2_SEG2                        0
>+#define GC_BASE__INST2_SEG3                        0
>+#define GC_BASE__INST2_SEG4                        0
>+#define GC_BASE__INST2_SEG5                        0
>+
>+#define GC_BASE__INST3_SEG0                        0
>+#define GC_BASE__INST3_SEG1                        0
>+#define GC_BASE__INST3_SEG2                        0
>+#define GC_BASE__INST3_SEG3                        0
>+#define GC_BASE__INST3_SEG4                        0
>+#define GC_BASE__INST3_SEG5                        0
>+
>+#define GC_BASE__INST4_SEG0                        0
>+#define GC_BASE__INST4_SEG1                        0
>+#define GC_BASE__INST4_SEG2                        0
>+#define GC_BASE__INST4_SEG3                        0
>+#define GC_BASE__INST4_SEG4                        0
>+#define GC_BASE__INST4_SEG5                        0
>+
>+#define GC_BASE__INST5_SEG0                        0
>+#define GC_BASE__INST5_SEG1                        0
>+#define GC_BASE__INST5_SEG2                        0
>+#define GC_BASE__INST5_SEG3                        0
>+#define GC_BASE__INST5_SEG4                        0
>+#define GC_BASE__INST5_SEG5                        0
>+
>+#define GC_BASE__INST6_SEG0                        0
>+#define GC_BASE__INST6_SEG1                        0
>+#define GC_BASE__INST6_SEG2                        0
>+#define GC_BASE__INST6_SEG3                        0
>+#define GC_BASE__INST6_SEG4                        0
>+#define GC_BASE__INST6_SEG5                        0
>+
>+#define GC_BASE__INST7_SEG0                        0
>+#define GC_BASE__INST7_SEG1                        0
>+#define GC_BASE__INST7_SEG2                        0
>+#define GC_BASE__INST7_SEG3                        0
>+#define GC_BASE__INST7_SEG4                        0
>+#define GC_BASE__INST7_SEG5                        0
>+
>+#define HDP_BASE__INST0_SEG0                       0x00000F20
>+#define HDP_BASE__INST0_SEG1                       0x00012520
>+#define HDP_BASE__INST0_SEG2                       0x0040A400
>+#define HDP_BASE__INST0_SEG3                       0
>+#define HDP_BASE__INST0_SEG4                       0
>+#define HDP_BASE__INST0_SEG5                       0
>+
>+#define HDP_BASE__INST1_SEG0                       0
>+#define HDP_BASE__INST1_SEG1                       0
>+#define HDP_BASE__INST1_SEG2                       0
>+#define HDP_BASE__INST1_SEG3                       0
>+#define HDP_BASE__INST1_SEG4                       0
>+#define HDP_BASE__INST1_SEG5                       0
>+
>+#define HDP_BASE__INST2_SEG0                       0
>+#define HDP_BASE__INST2_SEG1                       0
>+#define HDP_BASE__INST2_SEG2                       0
>+#define HDP_BASE__INST2_SEG3                       0
>+#define HDP_BASE__INST2_SEG4                       0
>+#define HDP_BASE__INST2_SEG5                       0
>+
>+#define HDP_BASE__INST3_SEG0                       0
>+#define HDP_BASE__INST3_SEG1                       0
>+#define HDP_BASE__INST3_SEG2                       0
>+#define HDP_BASE__INST3_SEG3                       0
>+#define HDP_BASE__INST3_SEG4                       0
>+#define HDP_BASE__INST3_SEG5                       0
>+
>+#define HDP_BASE__INST4_SEG0                       0
>+#define HDP_BASE__INST4_SEG1                       0
>+#define HDP_BASE__INST4_SEG2                       0
>+#define HDP_BASE__INST4_SEG3                       0
>+#define HDP_BASE__INST4_SEG4                       0
>+#define HDP_BASE__INST4_SEG5                       0
>+
>+#define HDP_BASE__INST5_SEG0                       0
>+#define HDP_BASE__INST5_SEG1                       0
>+#define HDP_BASE__INST5_SEG2                       0
>+#define HDP_BASE__INST5_SEG3                       0
>+#define HDP_BASE__INST5_SEG4                       0
>+#define HDP_BASE__INST5_SEG5                       0
>+
>+#define HDP_BASE__INST6_SEG0                       0
>+#define HDP_BASE__INST6_SEG1                       0
>+#define HDP_BASE__INST6_SEG2                       0
>+#define HDP_BASE__INST6_SEG3                       0
>+#define HDP_BASE__INST6_SEG4                       0
>+#define HDP_BASE__INST6_SEG5                       0
>+
>+#define HDP_BASE__INST7_SEG0                       0
>+#define HDP_BASE__INST7_SEG1                       0
>+#define HDP_BASE__INST7_SEG2                       0
>+#define HDP_BASE__INST7_SEG3                       0
>+#define HDP_BASE__INST7_SEG4                       0
>+#define HDP_BASE__INST7_SEG5                       0
>+
>+#define MMHUB_BASE__INST0_SEG0                     0x00012440
>+#define MMHUB_BASE__INST0_SEG1                     0x0001A000
>+#define MMHUB_BASE__INST0_SEG2                     0x00408800
>+#define MMHUB_BASE__INST0_SEG3                     0
>+#define MMHUB_BASE__INST0_SEG4                     0
>+#define MMHUB_BASE__INST0_SEG5                     0
>+
>+#define MMHUB_BASE__INST1_SEG0                     0
>+#define MMHUB_BASE__INST1_SEG1                     0
>+#define MMHUB_BASE__INST1_SEG2                     0
>+#define MMHUB_BASE__INST1_SEG3                     0
>+#define MMHUB_BASE__INST1_SEG4                     0
>+#define MMHUB_BASE__INST1_SEG5                     0
>+
>+#define MMHUB_BASE__INST2_SEG0                     0
>+#define MMHUB_BASE__INST2_SEG1                     0
>+#define MMHUB_BASE__INST2_SEG2                     0
>+#define MMHUB_BASE__INST2_SEG3                     0
>+#define MMHUB_BASE__INST2_SEG4                     0
>+#define MMHUB_BASE__INST2_SEG5                     0
>+
>+#define MMHUB_BASE__INST3_SEG0                     0
>+#define MMHUB_BASE__INST3_SEG1                     0
>+#define MMHUB_BASE__INST3_SEG2                     0
>+#define MMHUB_BASE__INST3_SEG3                     0
>+#define MMHUB_BASE__INST3_SEG4                     0
>+#define MMHUB_BASE__INST3_SEG5                     0
>+
>+#define MMHUB_BASE__INST4_SEG0                     0
>+#define MMHUB_BASE__INST4_SEG1                     0
>+#define MMHUB_BASE__INST4_SEG2                     0
>+#define MMHUB_BASE__INST4_SEG3                     0
>+#define MMHUB_BASE__INST4_SEG4                     0
>+#define MMHUB_BASE__INST4_SEG5                     0
>+
>+#define MMHUB_BASE__INST5_SEG0                     0
>+#define MMHUB_BASE__INST5_SEG1                     0
>+#define MMHUB_BASE__INST5_SEG2                     0
>+#define MMHUB_BASE__INST5_SEG3                     0
>+#define MMHUB_BASE__INST5_SEG4                     0
>+#define MMHUB_BASE__INST5_SEG5                     0
>+
>+#define MMHUB_BASE__INST6_SEG0                     0
>+#define MMHUB_BASE__INST6_SEG1                     0
>+#define MMHUB_BASE__INST6_SEG2                     0
>+#define MMHUB_BASE__INST6_SEG3                     0
>+#define MMHUB_BASE__INST6_SEG4                     0
>+#define MMHUB_BASE__INST6_SEG5                     0
>+
>+#define MMHUB_BASE__INST7_SEG0                     0
>+#define MMHUB_BASE__INST7_SEG1                     0
>+#define MMHUB_BASE__INST7_SEG2                     0
>+#define MMHUB_BASE__INST7_SEG3                     0
>+#define MMHUB_BASE__INST7_SEG4                     0
>+#define MMHUB_BASE__INST7_SEG5                     0
>+
>+#define MP0_BASE__INST0_SEG0                       0x00013FE0
>+#define MP0_BASE__INST0_SEG1                       0x00016000
>+#define MP0_BASE__INST0_SEG2                       0x0043FC00
>+#define MP0_BASE__INST0_SEG3                       0x00DC0000
>+#define MP0_BASE__INST0_SEG4                       0x00E00000
>+#define MP0_BASE__INST0_SEG5                       0x00E40000
>+
>+#define MP0_BASE__INST1_SEG0                       0
>+#define MP0_BASE__INST1_SEG1                       0
>+#define MP0_BASE__INST1_SEG2                       0
>+#define MP0_BASE__INST1_SEG3                       0
>+#define MP0_BASE__INST1_SEG4                       0
>+#define MP0_BASE__INST1_SEG5                       0
>+
>+#define MP0_BASE__INST2_SEG0                       0
>+#define MP0_BASE__INST2_SEG1                       0
>+#define MP0_BASE__INST2_SEG2                       0
>+#define MP0_BASE__INST2_SEG3                       0
>+#define MP0_BASE__INST2_SEG4                       0
>+#define MP0_BASE__INST2_SEG5                       0
>+
>+#define MP0_BASE__INST3_SEG0                       0
>+#define MP0_BASE__INST3_SEG1                       0
>+#define MP0_BASE__INST3_SEG2                       0
>+#define MP0_BASE__INST3_SEG3                       0
>+#define MP0_BASE__INST3_SEG4                       0
>+#define MP0_BASE__INST3_SEG5                       0
>+
>+#define MP0_BASE__INST4_SEG0                       0
>+#define MP0_BASE__INST4_SEG1                       0
>+#define MP0_BASE__INST4_SEG2                       0
>+#define MP0_BASE__INST4_SEG3                       0
>+#define MP0_BASE__INST4_SEG4                       0
>+#define MP0_BASE__INST4_SEG5                       0
>+
>+#define MP0_BASE__INST5_SEG0                       0
>+#define MP0_BASE__INST5_SEG1                       0
>+#define MP0_BASE__INST5_SEG2                       0
>+#define MP0_BASE__INST5_SEG3                       0
>+#define MP0_BASE__INST5_SEG4                       0
>+#define MP0_BASE__INST5_SEG5                       0
>+
>+#define MP0_BASE__INST6_SEG0                       0
>+#define MP0_BASE__INST6_SEG1                       0
>+#define MP0_BASE__INST6_SEG2                       0
>+#define MP0_BASE__INST6_SEG3                       0
>+#define MP0_BASE__INST6_SEG4                       0
>+#define MP0_BASE__INST6_SEG5                       0
>+
>+#define MP0_BASE__INST7_SEG0                       0
>+#define MP0_BASE__INST7_SEG1                       0
>+#define MP0_BASE__INST7_SEG2                       0
>+#define MP0_BASE__INST7_SEG3                       0
>+#define MP0_BASE__INST7_SEG4                       0
>+#define MP0_BASE__INST7_SEG5                       0
>+
>+#define MP1_BASE__INST0_SEG0                       0x00012020
>+#define MP1_BASE__INST0_SEG1                       0x00016200
>+#define MP1_BASE__INST0_SEG2                       0x00400400
>+#define MP1_BASE__INST0_SEG3                       0x00E80000
>+#define MP1_BASE__INST0_SEG4                       0x00EC0000
>+#define MP1_BASE__INST0_SEG5                       0x00F00000
>+
>+#define MP1_BASE__INST1_SEG0                       0
>+#define MP1_BASE__INST1_SEG1                       0
>+#define MP1_BASE__INST1_SEG2                       0
>+#define MP1_BASE__INST1_SEG3                       0
>+#define MP1_BASE__INST1_SEG4                       0
>+#define MP1_BASE__INST1_SEG5                       0
>+
>+#define MP1_BASE__INST2_SEG0                       0
>+#define MP1_BASE__INST2_SEG1                       0
>+#define MP1_BASE__INST2_SEG2                       0
>+#define MP1_BASE__INST2_SEG3                       0
>+#define MP1_BASE__INST2_SEG4                       0
>+#define MP1_BASE__INST2_SEG5                       0
>+
>+#define MP1_BASE__INST3_SEG0                       0
>+#define MP1_BASE__INST3_SEG1                       0
>+#define MP1_BASE__INST3_SEG2                       0
>+#define MP1_BASE__INST3_SEG3                       0
>+#define MP1_BASE__INST3_SEG4                       0
>+#define MP1_BASE__INST3_SEG5                       0
>+
>+#define MP1_BASE__INST4_SEG0                       0
>+#define MP1_BASE__INST4_SEG1                       0
>+#define MP1_BASE__INST4_SEG2                       0
>+#define MP1_BASE__INST4_SEG3                       0
>+#define MP1_BASE__INST4_SEG4                       0
>+#define MP1_BASE__INST4_SEG5                       0
>+
>+#define MP1_BASE__INST5_SEG0                       0
>+#define MP1_BASE__INST5_SEG1                       0
>+#define MP1_BASE__INST5_SEG2                       0
>+#define MP1_BASE__INST5_SEG3                       0
>+#define MP1_BASE__INST5_SEG4                       0
>+#define MP1_BASE__INST5_SEG5                       0
>+
>+#define MP1_BASE__INST6_SEG0                       0
>+#define MP1_BASE__INST6_SEG1                       0
>+#define MP1_BASE__INST6_SEG2                       0
>+#define MP1_BASE__INST6_SEG3                       0
>+#define MP1_BASE__INST6_SEG4                       0
>+#define MP1_BASE__INST6_SEG5                       0
>+
>+#define MP1_BASE__INST7_SEG0                       0
>+#define MP1_BASE__INST7_SEG1                       0
>+#define MP1_BASE__INST7_SEG2                       0
>+#define MP1_BASE__INST7_SEG3                       0
>+#define MP1_BASE__INST7_SEG4                       0
>+#define MP1_BASE__INST7_SEG5                       0
>+
>+#define NBIF0_BASE__INST0_SEG0                     0x00000000
>+#define NBIF0_BASE__INST0_SEG1                     0x00000014
>+#define NBIF0_BASE__INST0_SEG2                     0x00000D20
>+#define NBIF0_BASE__INST0_SEG3                     0x00010400
>+#define NBIF0_BASE__INST0_SEG4                     0x00012D80
>+#define NBIF0_BASE__INST0_SEG5                     0x0041B000
>+
>+#define NBIF0_BASE__INST1_SEG0                     0
>+#define NBIF0_BASE__INST1_SEG1                     0
>+#define NBIF0_BASE__INST1_SEG2                     0
>+#define NBIF0_BASE__INST1_SEG3                     0
>+#define NBIF0_BASE__INST1_SEG4                     0
>+#define NBIF0_BASE__INST1_SEG5                     0
>+
>+#define NBIF0_BASE__INST2_SEG0                     0
>+#define NBIF0_BASE__INST2_SEG1                     0
>+#define NBIF0_BASE__INST2_SEG2                     0
>+#define NBIF0_BASE__INST2_SEG3                     0
>+#define NBIF0_BASE__INST2_SEG4                     0
>+#define NBIF0_BASE__INST2_SEG5                     0
>+
>+#define NBIF0_BASE__INST3_SEG0                     0
>+#define NBIF0_BASE__INST3_SEG1                     0
>+#define NBIF0_BASE__INST3_SEG2                     0
>+#define NBIF0_BASE__INST3_SEG3                     0
>+#define NBIF0_BASE__INST3_SEG4                     0
>+#define NBIF0_BASE__INST3_SEG5                     0
>+
>+#define NBIF0_BASE__INST4_SEG0                     0
>+#define NBIF0_BASE__INST4_SEG1                     0
>+#define NBIF0_BASE__INST4_SEG2                     0
>+#define NBIF0_BASE__INST4_SEG3                     0
>+#define NBIF0_BASE__INST4_SEG4                     0
>+#define NBIF0_BASE__INST4_SEG5                     0
>+
>+#define NBIF0_BASE__INST5_SEG0                     0
>+#define NBIF0_BASE__INST5_SEG1                     0
>+#define NBIF0_BASE__INST5_SEG2                     0
>+#define NBIF0_BASE__INST5_SEG3                     0
>+#define NBIF0_BASE__INST5_SEG4                     0
>+#define NBIF0_BASE__INST5_SEG5                     0
>+
>+#define NBIF0_BASE__INST6_SEG0                     0
>+#define NBIF0_BASE__INST6_SEG1                     0
>+#define NBIF0_BASE__INST6_SEG2                     0
>+#define NBIF0_BASE__INST6_SEG3                     0
>+#define NBIF0_BASE__INST6_SEG4                     0
>+#define NBIF0_BASE__INST6_SEG5                     0
>+
>+#define NBIF0_BASE__INST7_SEG0                     0
>+#define NBIF0_BASE__INST7_SEG1                     0
>+#define NBIF0_BASE__INST7_SEG2                     0
>+#define NBIF0_BASE__INST7_SEG3                     0
>+#define NBIF0_BASE__INST7_SEG4                     0
>+#define NBIF0_BASE__INST7_SEG5                     0
>+
>+#define OSSSYS_BASE__INST0_SEG0                    0x000010A0
>+#define OSSSYS_BASE__INST0_SEG1                    0x00012500
>+#define OSSSYS_BASE__INST0_SEG2                    0x0040A000
>+#define OSSSYS_BASE__INST0_SEG3                    0
>+#define OSSSYS_BASE__INST0_SEG4                    0
>+#define OSSSYS_BASE__INST0_SEG5                    0
>+
>+#define OSSSYS_BASE__INST1_SEG0                    0
>+#define OSSSYS_BASE__INST1_SEG1                    0
>+#define OSSSYS_BASE__INST1_SEG2                    0
>+#define OSSSYS_BASE__INST1_SEG3                    0
>+#define OSSSYS_BASE__INST1_SEG4                    0
>+#define OSSSYS_BASE__INST1_SEG5                    0
>+
>+#define OSSSYS_BASE__INST2_SEG0                    0
>+#define OSSSYS_BASE__INST2_SEG1                    0
>+#define OSSSYS_BASE__INST2_SEG2                    0
>+#define OSSSYS_BASE__INST2_SEG3                    0
>+#define OSSSYS_BASE__INST2_SEG4                    0
>+#define OSSSYS_BASE__INST2_SEG5                    0
>+
>+#define OSSSYS_BASE__INST3_SEG0                    0
>+#define OSSSYS_BASE__INST3_SEG1                    0
>+#define OSSSYS_BASE__INST3_SEG2                    0
>+#define OSSSYS_BASE__INST3_SEG3                    0
>+#define OSSSYS_BASE__INST3_SEG4                    0
>+#define OSSSYS_BASE__INST3_SEG5                    0
>+
>+#define OSSSYS_BASE__INST4_SEG0                    0
>+#define OSSSYS_BASE__INST4_SEG1                    0
>+#define OSSSYS_BASE__INST4_SEG2                    0
>+#define OSSSYS_BASE__INST4_SEG3                    0
>+#define OSSSYS_BASE__INST4_SEG4                    0
>+#define OSSSYS_BASE__INST4_SEG5                    0
>+
>+#define OSSSYS_BASE__INST5_SEG0                    0
>+#define OSSSYS_BASE__INST5_SEG1                    0
>+#define OSSSYS_BASE__INST5_SEG2                    0
>+#define OSSSYS_BASE__INST5_SEG3                    0
>+#define OSSSYS_BASE__INST5_SEG4                    0
>+#define OSSSYS_BASE__INST5_SEG5                    0
>+
>+#define OSSSYS_BASE__INST6_SEG0                    0
>+#define OSSSYS_BASE__INST6_SEG1                    0
>+#define OSSSYS_BASE__INST6_SEG2                    0
>+#define OSSSYS_BASE__INST6_SEG3                    0
>+#define OSSSYS_BASE__INST6_SEG4                    0
>+#define OSSSYS_BASE__INST6_SEG5                    0
>+
>+#define OSSSYS_BASE__INST7_SEG0                    0
>+#define OSSSYS_BASE__INST7_SEG1                    0
>+#define OSSSYS_BASE__INST7_SEG2                    0
>+#define OSSSYS_BASE__INST7_SEG3                    0
>+#define OSSSYS_BASE__INST7_SEG4                    0
>+#define OSSSYS_BASE__INST7_SEG5                    0
>+
>+#define PCIE0_BASE__INST0_SEG0                     0x000128C0
>+#define PCIE0_BASE__INST0_SEG1                     0x00411800
>+#define PCIE0_BASE__INST0_SEG2                     0x04440000
>+#define PCIE0_BASE__INST0_SEG3                     0
>+#define PCIE0_BASE__INST0_SEG4                     0
>+#define PCIE0_BASE__INST0_SEG5                     0
>+
>+#define PCIE0_BASE__INST1_SEG0                     0
>+#define PCIE0_BASE__INST1_SEG1                     0
>+#define PCIE0_BASE__INST1_SEG2                     0
>+#define PCIE0_BASE__INST1_SEG3                     0
>+#define PCIE0_BASE__INST1_SEG4                     0
>+#define PCIE0_BASE__INST1_SEG5                     0
>+
>+#define PCIE0_BASE__INST2_SEG0                     0
>+#define PCIE0_BASE__INST2_SEG1                     0
>+#define PCIE0_BASE__INST2_SEG2                     0
>+#define PCIE0_BASE__INST2_SEG3                     0
>+#define PCIE0_BASE__INST2_SEG4                     0
>+#define PCIE0_BASE__INST2_SEG5                     0
>+
>+#define PCIE0_BASE__INST3_SEG0                     0
>+#define PCIE0_BASE__INST3_SEG1                     0
>+#define PCIE0_BASE__INST3_SEG2                     0
>+#define PCIE0_BASE__INST3_SEG3                     0
>+#define PCIE0_BASE__INST3_SEG4                     0
>+#define PCIE0_BASE__INST3_SEG5                     0
>+
>+#define PCIE0_BASE__INST4_SEG0                     0
>+#define PCIE0_BASE__INST4_SEG1                     0
>+#define PCIE0_BASE__INST4_SEG2                     0
>+#define PCIE0_BASE__INST4_SEG3                     0
>+#define PCIE0_BASE__INST4_SEG4                     0
>+#define PCIE0_BASE__INST4_SEG5                     0
>+
>+#define PCIE0_BASE__INST5_SEG0                     0
>+#define PCIE0_BASE__INST5_SEG1                     0
>+#define PCIE0_BASE__INST5_SEG2                     0
>+#define PCIE0_BASE__INST5_SEG3                     0
>+#define PCIE0_BASE__INST5_SEG4                     0
>+#define PCIE0_BASE__INST5_SEG5                     0
>+
>+#define PCIE0_BASE__INST6_SEG0                     0
>+#define PCIE0_BASE__INST6_SEG1                     0
>+#define PCIE0_BASE__INST6_SEG2                     0
>+#define PCIE0_BASE__INST6_SEG3                     0
>+#define PCIE0_BASE__INST6_SEG4                     0
>+#define PCIE0_BASE__INST6_SEG5                     0
>+
>+#define PCIE0_BASE__INST7_SEG0                     0
>+#define PCIE0_BASE__INST7_SEG1                     0
>+#define PCIE0_BASE__INST7_SEG2                     0
>+#define PCIE0_BASE__INST7_SEG3                     0
>+#define PCIE0_BASE__INST7_SEG4                     0
>+#define PCIE0_BASE__INST7_SEG5                     0
>+
>+#define SDMA0_BASE__INST0_SEG0                     0x00001260
>+#define SDMA0_BASE__INST0_SEG1                     0x00012540
>+#define SDMA0_BASE__INST0_SEG2                     0x0040A800
>+#define SDMA0_BASE__INST0_SEG3                     0
>+#define SDMA0_BASE__INST0_SEG4                     0
>+#define SDMA0_BASE__INST0_SEG5                     0
>+
>+#define SDMA0_BASE__INST1_SEG0                     0
>+#define SDMA0_BASE__INST1_SEG1                     0
>+#define SDMA0_BASE__INST1_SEG2                     0
>+#define SDMA0_BASE__INST1_SEG3                     0
>+#define SDMA0_BASE__INST1_SEG4                     0
>+#define SDMA0_BASE__INST1_SEG5                     0
>+
>+#define SDMA0_BASE__INST2_SEG0                     0
>+#define SDMA0_BASE__INST2_SEG1                     0
>+#define SDMA0_BASE__INST2_SEG2                     0
>+#define SDMA0_BASE__INST2_SEG3                     0
>+#define SDMA0_BASE__INST2_SEG4                     0
>+#define SDMA0_BASE__INST2_SEG5                     0
>+
>+#define SDMA0_BASE__INST3_SEG0                     0
>+#define SDMA0_BASE__INST3_SEG1                     0
>+#define SDMA0_BASE__INST3_SEG2                     0
>+#define SDMA0_BASE__INST3_SEG3                     0
>+#define SDMA0_BASE__INST3_SEG4                     0
>+#define SDMA0_BASE__INST3_SEG5                     0
>+
>+#define SDMA0_BASE__INST4_SEG0                     0
>+#define SDMA0_BASE__INST4_SEG1                     0
>+#define SDMA0_BASE__INST4_SEG2                     0
>+#define SDMA0_BASE__INST4_SEG3                     0
>+#define SDMA0_BASE__INST4_SEG4                     0
>+#define SDMA0_BASE__INST4_SEG5                     0
>+
>+#define SDMA0_BASE__INST5_SEG0                     0
>+#define SDMA0_BASE__INST5_SEG1                     0
>+#define SDMA0_BASE__INST5_SEG2                     0
>+#define SDMA0_BASE__INST5_SEG3                     0
>+#define SDMA0_BASE__INST5_SEG4                     0
>+#define SDMA0_BASE__INST5_SEG5                     0
>+
>+#define SDMA0_BASE__INST6_SEG0                     0
>+#define SDMA0_BASE__INST6_SEG1                     0
>+#define SDMA0_BASE__INST6_SEG2                     0
>+#define SDMA0_BASE__INST6_SEG3                     0
>+#define SDMA0_BASE__INST6_SEG4                     0
>+#define SDMA0_BASE__INST6_SEG5                     0
>+
>+#define SDMA1_BASE__INST0_SEG0                     0x00001860
>+#define SDMA1_BASE__INST0_SEG1                     0x00012560
>+#define SDMA1_BASE__INST0_SEG2                     0x0040AC00
>+#define SDMA1_BASE__INST0_SEG3                     0
>+#define SDMA1_BASE__INST0_SEG4                     0
>+#define SDMA1_BASE__INST0_SEG5                     0
>+
>+#define SDMA1_BASE__INST1_SEG0                     0
>+#define SDMA1_BASE__INST1_SEG1                     0
>+#define SDMA1_BASE__INST1_SEG2                     0
>+#define SDMA1_BASE__INST1_SEG3                     0
>+#define SDMA1_BASE__INST1_SEG4                     0
>+#define SDMA1_BASE__INST1_SEG5                     0
>+
>+#define SDMA1_BASE__INST2_SEG0                     0
>+#define SDMA1_BASE__INST2_SEG1                     0
>+#define SDMA1_BASE__INST2_SEG2                     0
>+#define SDMA1_BASE__INST2_SEG3                     0
>+#define SDMA1_BASE__INST2_SEG4                     0
>+#define SDMA1_BASE__INST2_SEG5                     0
>+
>+#define SDMA1_BASE__INST3_SEG0                     0
>+#define SDMA1_BASE__INST3_SEG1                     0
>+#define SDMA1_BASE__INST3_SEG2                     0
>+#define SDMA1_BASE__INST3_SEG3                     0
>+#define SDMA1_BASE__INST3_SEG4                     0
>+#define SDMA1_BASE__INST3_SEG5                     0
>+
>+#define SDMA1_BASE__INST4_SEG0                     0
>+#define SDMA1_BASE__INST4_SEG1                     0
>+#define SDMA1_BASE__INST4_SEG2                     0
>+#define SDMA1_BASE__INST4_SEG3                     0
>+#define SDMA1_BASE__INST4_SEG4                     0
>+#define SDMA1_BASE__INST4_SEG5                     0
>+
>+#define SDMA1_BASE__INST5_SEG0                     0
>+#define SDMA1_BASE__INST5_SEG1                     0
>+#define SDMA1_BASE__INST5_SEG2                     0
>+#define SDMA1_BASE__INST5_SEG3                     0
>+#define SDMA1_BASE__INST5_SEG4                     0
>+#define SDMA1_BASE__INST5_SEG5                     0
>+
>+
>+#define SDMA1_BASE__INST6_SEG0                     0
>+#define SDMA1_BASE__INST6_SEG1                     0
>+#define SDMA1_BASE__INST6_SEG2                     0
>+#define SDMA1_BASE__INST6_SEG3                     0
>+#define SDMA1_BASE__INST6_SEG4                     0
>+#define SDMA1_BASE__INST6_SEG5                     0
>+
>+
>+#define SDMA2_BASE__INST0_SEG0                     0x00013760
>+#define SDMA2_BASE__INST0_SEG1                     0x0001E000
>+#define SDMA2_BASE__INST0_SEG2                     0x0042EC00
>+#define SDMA2_BASE__INST0_SEG3                     0
>+#define SDMA2_BASE__INST0_SEG4                     0
>+#define SDMA2_BASE__INST0_SEG5                     0
>+
>+
>+#define SDMA2_BASE__INST1_SEG0                     0
>+#define SDMA2_BASE__INST1_SEG1                     0
>+#define SDMA2_BASE__INST1_SEG2                     0
>+#define SDMA2_BASE__INST1_SEG3                     0
>+#define SDMA2_BASE__INST1_SEG4                     0
>+#define SDMA2_BASE__INST1_SEG5                     0
>+
>+#define SDMA2_BASE__INST2_SEG0                     0
>+#define SDMA2_BASE__INST2_SEG1                     0
>+#define SDMA2_BASE__INST2_SEG2                     0
>+#define SDMA2_BASE__INST2_SEG3                     0
>+#define SDMA2_BASE__INST2_SEG4                     0
>+#define SDMA2_BASE__INST2_SEG5                     0
>+
>+#define SDMA2_BASE__INST3_SEG0                     0
>+#define SDMA2_BASE__INST3_SEG1                     0
>+#define SDMA2_BASE__INST3_SEG2                     0
>+#define SDMA2_BASE__INST3_SEG3                     0
>+#define SDMA2_BASE__INST3_SEG4                     0
>+#define SDMA2_BASE__INST3_SEG5                     0
>+
>+#define SDMA2_BASE__INST4_SEG0                     0
>+#define SDMA2_BASE__INST4_SEG1                     0
>+#define SDMA2_BASE__INST4_SEG2                     0
>+#define SDMA2_BASE__INST4_SEG3                     0
>+#define SDMA2_BASE__INST4_SEG4                     0
>+#define SDMA2_BASE__INST4_SEG5                     0
>+
>+#define SDMA2_BASE__INST5_SEG0                     0
>+#define SDMA2_BASE__INST5_SEG1                     0
>+#define SDMA2_BASE__INST5_SEG2                     0
>+#define SDMA2_BASE__INST5_SEG3                     0
>+#define SDMA2_BASE__INST5_SEG4                     0
>+#define SDMA2_BASE__INST5_SEG5                     0
>+
>+#define SDMA2_BASE__INST6_SEG0                     0
>+#define SDMA2_BASE__INST6_SEG1                     0
>+#define SDMA2_BASE__INST6_SEG2                     0
>+#define SDMA2_BASE__INST6_SEG3                     0
>+#define SDMA2_BASE__INST6_SEG4                     0
>+#define SDMA2_BASE__INST6_SEG5                     0
>+
>+#define SDMA3_BASE__INST0_SEG0                     0x00013780
>+#define SDMA3_BASE__INST0_SEG1                     0x0001E400
>+#define SDMA3_BASE__INST0_SEG2                     0x0042F000
>+#define SDMA3_BASE__INST0_SEG3                     0
>+#define SDMA3_BASE__INST0_SEG4                     0
>+#define SDMA3_BASE__INST0_SEG5                     0
>+
>+#define SDMA3_BASE__INST1_SEG0                     0
>+#define SDMA3_BASE__INST1_SEG1                     0
>+#define SDMA3_BASE__INST1_SEG2                     0
>+#define SDMA3_BASE__INST1_SEG3                     0
>+#define SDMA3_BASE__INST1_SEG4                     0
>+#define SDMA3_BASE__INST1_SEG5                     0
>+
>+#define SDMA3_BASE__INST2_SEG0                     0
>+#define SDMA3_BASE__INST2_SEG1                     0
>+#define SDMA3_BASE__INST2_SEG2                     0
>+#define SDMA3_BASE__INST2_SEG3                     0
>+#define SDMA3_BASE__INST2_SEG4                     0
>+#define SDMA3_BASE__INST2_SEG5                     0
>+
>+#define SDMA3_BASE__INST3_SEG0                     0
>+#define SDMA3_BASE__INST3_SEG1                     0
>+#define SDMA3_BASE__INST3_SEG2                     0
>+#define SDMA3_BASE__INST3_SEG3                     0
>+#define SDMA3_BASE__INST3_SEG4                     0
>+#define SDMA3_BASE__INST3_SEG5                     0
>+
>+#define SDMA3_BASE__INST4_SEG0                     0
>+#define SDMA3_BASE__INST4_SEG1                     0
>+#define SDMA3_BASE__INST4_SEG2                     0
>+#define SDMA3_BASE__INST4_SEG3                     0
>+#define SDMA3_BASE__INST4_SEG4                     0
>+#define SDMA3_BASE__INST4_SEG5                     0
>+
>+#define SDMA3_BASE__INST5_SEG0                     0
>+#define SDMA3_BASE__INST5_SEG1                     0
>+#define SDMA3_BASE__INST5_SEG2                     0
>+#define SDMA3_BASE__INST5_SEG3                     0
>+#define SDMA3_BASE__INST5_SEG4                     0
>+#define SDMA3_BASE__INST5_SEG5                     0
>+
>+#define SDMA3_BASE__INST6_SEG0                     0
>+#define SDMA3_BASE__INST6_SEG1                     0
>+#define SDMA3_BASE__INST6_SEG2                     0
>+#define SDMA3_BASE__INST6_SEG3                     0
>+#define SDMA3_BASE__INST6_SEG4                     0
>+#define SDMA3_BASE__INST6_SEG5                     0
>+
>+#define SDMA4_BASE__INST0_SEG0                     0x000137A0
>+#define SDMA4_BASE__INST0_SEG1                     0x0001E800
>+#define SDMA4_BASE__INST0_SEG2                     0x0042F400
>+#define SDMA4_BASE__INST0_SEG3                     0
>+#define SDMA4_BASE__INST0_SEG4                     0
>+#define SDMA4_BASE__INST0_SEG5                     0
>+
>+#define SDMA4_BASE__INST1_SEG0                     0
>+#define SDMA4_BASE__INST1_SEG1                     0
>+#define SDMA4_BASE__INST1_SEG2                     0
>+#define SDMA4_BASE__INST1_SEG3                     0
>+#define SDMA4_BASE__INST1_SEG4                     0
>+#define SDMA4_BASE__INST1_SEG5                     0
>+
>+#define SDMA4_BASE__INST2_SEG0                     0
>+#define SDMA4_BASE__INST2_SEG1                     0
>+#define SDMA4_BASE__INST2_SEG2                     0
>+#define SDMA4_BASE__INST2_SEG3                     0
>+#define SDMA4_BASE__INST2_SEG4                     0
>+#define SDMA4_BASE__INST2_SEG5                     0
>+
>+#define SDMA4_BASE__INST3_SEG0                     0
>+#define SDMA4_BASE__INST3_SEG1                     0
>+#define SDMA4_BASE__INST3_SEG2                     0
>+#define SDMA4_BASE__INST3_SEG3                     0
>+#define SDMA4_BASE__INST3_SEG4                     0
>+#define SDMA4_BASE__INST3_SEG5                     0
>+
>+#define SDMA4_BASE__INST4_SEG0                     0
>+#define SDMA4_BASE__INST4_SEG1                     0
>+#define SDMA4_BASE__INST4_SEG2                     0
>+#define SDMA4_BASE__INST4_SEG3                     0
>+#define SDMA4_BASE__INST4_SEG4                     0
>+#define SDMA4_BASE__INST4_SEG5                     0
>+
>+#define SDMA4_BASE__INST5_SEG0                     0
>+#define SDMA4_BASE__INST5_SEG1                     0
>+#define SDMA4_BASE__INST5_SEG2                     0
>+#define SDMA4_BASE__INST5_SEG3                     0
>+#define SDMA4_BASE__INST5_SEG4                     0
>+#define SDMA4_BASE__INST5_SEG5                     0
>+
>+#define SDMA4_BASE__INST6_SEG0                     0
>+#define SDMA4_BASE__INST6_SEG1                     0
>+#define SDMA4_BASE__INST6_SEG2                     0
>+#define SDMA4_BASE__INST6_SEG3                     0
>+#define SDMA4_BASE__INST6_SEG4                     0
>+#define SDMA4_BASE__INST6_SEG5                     0
>+
>+#define SDMA5_BASE__INST0_SEG0                     0x000137C0
>+#define SDMA5_BASE__INST0_SEG1                     0x0001EC00
>+#define SDMA5_BASE__INST0_SEG2                     0x0042F800
>+#define SDMA5_BASE__INST0_SEG3                     0
>+#define SDMA5_BASE__INST0_SEG4                     0
>+#define SDMA5_BASE__INST0_SEG5                     0
>+
>+#define SDMA5_BASE__INST1_SEG0                     0
>+#define SDMA5_BASE__INST1_SEG1                     0
>+#define SDMA5_BASE__INST1_SEG2                     0
>+#define SDMA5_BASE__INST1_SEG3                     0
>+#define SDMA5_BASE__INST1_SEG4                     0
>+#define SDMA5_BASE__INST1_SEG5                     0
>+
>+#define SDMA5_BASE__INST2_SEG0                     0
>+#define SDMA5_BASE__INST2_SEG1                     0
>+#define SDMA5_BASE__INST2_SEG2                     0
>+#define SDMA5_BASE__INST2_SEG3                     0
>+#define SDMA5_BASE__INST2_SEG4                     0
>+#define SDMA5_BASE__INST2_SEG5                     0
>+
>+#define SDMA5_BASE__INST3_SEG0                     0
>+#define SDMA5_BASE__INST3_SEG1                     0
>+#define SDMA5_BASE__INST3_SEG2                     0
>+#define SDMA5_BASE__INST3_SEG3                     0
>+#define SDMA5_BASE__INST3_SEG4                     0
>+#define SDMA5_BASE__INST3_SEG5                     0
>+
>+#define SDMA5_BASE__INST4_SEG0                     0
>+#define SDMA5_BASE__INST4_SEG1                     0
>+#define SDMA5_BASE__INST4_SEG2                     0
>+#define SDMA5_BASE__INST4_SEG3                     0
>+#define SDMA5_BASE__INST4_SEG4                     0
>+#define SDMA5_BASE__INST4_SEG5                     0
>+
>+#define SDMA5_BASE__INST5_SEG0                     0
>+#define SDMA5_BASE__INST5_SEG1                     0
>+#define SDMA5_BASE__INST5_SEG2                     0
>+#define SDMA5_BASE__INST5_SEG3                     0
>+#define SDMA5_BASE__INST5_SEG4                     0
>+#define SDMA5_BASE__INST5_SEG5                     0
>+
>+#define SDMA5_BASE__INST6_SEG0                     0
>+#define SDMA5_BASE__INST6_SEG1                     0
>+#define SDMA5_BASE__INST6_SEG2                     0
>+#define SDMA5_BASE__INST6_SEG3                     0
>+#define SDMA5_BASE__INST6_SEG4                     0
>+#define SDMA5_BASE__INST6_SEG5                     0
>+
>+#define SDMA6_BASE__INST0_SEG0                     0x000137E0
>+#define SDMA6_BASE__INST0_SEG1                     0x0001F000
>+#define SDMA6_BASE__INST0_SEG2                     0x0042FC00
>+#define SDMA6_BASE__INST0_SEG3                     0
>+#define SDMA6_BASE__INST0_SEG4                     0
>+#define SDMA6_BASE__INST0_SEG5                     0
>+
>+#define SDMA6_BASE__INST1_SEG0                     0
>+#define SDMA6_BASE__INST1_SEG1                     0
>+#define SDMA6_BASE__INST1_SEG2                     0
>+#define SDMA6_BASE__INST1_SEG3                     0
>+#define SDMA6_BASE__INST1_SEG4                     0
>+#define SDMA6_BASE__INST1_SEG5                     0
>+
>+#define SDMA6_BASE__INST2_SEG0                     0
>+#define SDMA6_BASE__INST2_SEG1                     0
>+#define SDMA6_BASE__INST2_SEG2                     0
>+#define SDMA6_BASE__INST2_SEG3                     0
>+#define SDMA6_BASE__INST2_SEG4                     0
>+#define SDMA6_BASE__INST2_SEG5                     0
>+
>+#define SDMA6_BASE__INST3_SEG0                     0
>+#define SDMA6_BASE__INST3_SEG1                     0
>+#define SDMA6_BASE__INST3_SEG2                     0
>+#define SDMA6_BASE__INST3_SEG3                     0
>+#define SDMA6_BASE__INST3_SEG4                     0
>+#define SDMA6_BASE__INST3_SEG5                     0
>+
>+#define SDMA6_BASE__INST4_SEG0                     0
>+#define SDMA6_BASE__INST4_SEG1                     0
>+#define SDMA6_BASE__INST4_SEG2                     0
>+#define SDMA6_BASE__INST4_SEG3                     0
>+#define SDMA6_BASE__INST4_SEG4                     0
>+#define SDMA6_BASE__INST4_SEG5                     0
>+
>+#define SDMA6_BASE__INST5_SEG0                     0
>+#define SDMA6_BASE__INST5_SEG1                     0
>+#define SDMA6_BASE__INST5_SEG2                     0
>+#define SDMA6_BASE__INST5_SEG3                     0
>+#define SDMA6_BASE__INST5_SEG4                     0
>+#define SDMA6_BASE__INST5_SEG5                     0
>+
>+#define SDMA6_BASE__INST6_SEG0                     0
>+#define SDMA6_BASE__INST6_SEG1                     0
>+#define SDMA6_BASE__INST6_SEG2                     0
>+#define SDMA6_BASE__INST6_SEG3                     0
>+#define SDMA6_BASE__INST6_SEG4                     0
>+#define SDMA6_BASE__INST6_SEG5                     0
>+
>+#define SDMA7_BASE__INST0_SEG0                     0x00013800
>+#define SDMA7_BASE__INST0_SEG1                     0x0001F400
>+#define SDMA7_BASE__INST0_SEG2                     0x00430000
>+#define SDMA7_BASE__INST0_SEG3                     0
>+#define SDMA7_BASE__INST0_SEG4                     0
>+#define SDMA7_BASE__INST0_SEG5                     0
>+
>+#define SDMA7_BASE__INST1_SEG0                     0
>+#define SDMA7_BASE__INST1_SEG1                     0
>+#define SDMA7_BASE__INST1_SEG2                     0
>+#define SDMA7_BASE__INST1_SEG3                     0
>+#define SDMA7_BASE__INST1_SEG4                     0
>+#define SDMA7_BASE__INST1_SEG5                     0
>+
>+#define SDMA7_BASE__INST2_SEG0                     0
>+#define SDMA7_BASE__INST2_SEG1                     0
>+#define SDMA7_BASE__INST2_SEG2                     0
>+#define SDMA7_BASE__INST2_SEG3                     0
>+#define SDMA7_BASE__INST2_SEG4                     0
>+#define SDMA7_BASE__INST2_SEG5                     0
>+
>+#define SDMA7_BASE__INST3_SEG0                     0
>+#define SDMA7_BASE__INST3_SEG1                     0
>+#define SDMA7_BASE__INST3_SEG2                     0
>+#define SDMA7_BASE__INST3_SEG3                     0
>+#define SDMA7_BASE__INST3_SEG4                     0
>+#define SDMA7_BASE__INST3_SEG5                     0
>+
>+#define SDMA7_BASE__INST4_SEG0                     0
>+#define SDMA7_BASE__INST4_SEG1                     0
>+#define SDMA7_BASE__INST4_SEG2                     0
>+#define SDMA7_BASE__INST4_SEG3                     0
>+#define SDMA7_BASE__INST4_SEG4                     0
>+#define SDMA7_BASE__INST4_SEG5                     0
>+
>+#define SDMA7_BASE__INST5_SEG0                     0
>+#define SDMA7_BASE__INST5_SEG1                     0
>+#define SDMA7_BASE__INST5_SEG2                     0
>+#define SDMA7_BASE__INST5_SEG3                     0
>+#define SDMA7_BASE__INST5_SEG4                     0
>+#define SDMA7_BASE__INST5_SEG5                     0
>+
>+#define SDMA7_BASE__INST6_SEG0                     0
>+#define SDMA7_BASE__INST6_SEG1                     0
>+#define SDMA7_BASE__INST6_SEG2                     0
>+#define SDMA7_BASE__INST6_SEG3                     0
>+#define SDMA7_BASE__INST6_SEG4                     0
>+#define SDMA7_BASE__INST6_SEG5                     0
>+
>+#define SMUIO_BASE__INST0_SEG0                     0x00012080
>+#define SMUIO_BASE__INST0_SEG1                     0x00016800
>+#define SMUIO_BASE__INST0_SEG2                     0x00016A00
>+#define SMUIO_BASE__INST0_SEG3                     0x00401000
>+#define SMUIO_BASE__INST0_SEG4                     0x00440000
>+#define SMUIO_BASE__INST0_SEG5                     0
>+
>+#define SMUIO_BASE__INST1_SEG0                     0
>+#define SMUIO_BASE__INST1_SEG1                     0
>+#define SMUIO_BASE__INST1_SEG2                     0
>+#define SMUIO_BASE__INST1_SEG3                     0
>+#define SMUIO_BASE__INST1_SEG4                     0
>+#define SMUIO_BASE__INST1_SEG5                     0
>+
>+#define SMUIO_BASE__INST2_SEG0                     0
>+#define SMUIO_BASE__INST2_SEG1                     0
>+#define SMUIO_BASE__INST2_SEG2                     0
>+#define SMUIO_BASE__INST2_SEG3                     0
>+#define SMUIO_BASE__INST2_SEG4                     0
>+#define SMUIO_BASE__INST2_SEG5                     0
>+
>+#define SMUIO_BASE__INST3_SEG0                     0
>+#define SMUIO_BASE__INST3_SEG1                     0
>+#define SMUIO_BASE__INST3_SEG2                     0
>+#define SMUIO_BASE__INST3_SEG3                     0
>+#define SMUIO_BASE__INST3_SEG4                     0
>+#define SMUIO_BASE__INST3_SEG5                     0
>+
>+#define SMUIO_BASE__INST4_SEG0                     0
>+#define SMUIO_BASE__INST4_SEG1                     0
>+#define SMUIO_BASE__INST4_SEG2                     0
>+#define SMUIO_BASE__INST4_SEG3                     0
>+#define SMUIO_BASE__INST4_SEG4                     0
>+#define SMUIO_BASE__INST4_SEG5                     0
>+
>+#define SMUIO_BASE__INST5_SEG0                     0
>+#define SMUIO_BASE__INST5_SEG1                     0
>+#define SMUIO_BASE__INST5_SEG2                     0
>+#define SMUIO_BASE__INST5_SEG3                     0
>+#define SMUIO_BASE__INST5_SEG4                     0
>+#define SMUIO_BASE__INST5_SEG5                     0
>+
>+#define SMUIO_BASE__INST6_SEG0                     0
>+#define SMUIO_BASE__INST6_SEG1                     0
>+#define SMUIO_BASE__INST6_SEG2                     0
>+#define SMUIO_BASE__INST6_SEG3                     0
>+#define SMUIO_BASE__INST6_SEG4                     0
>+#define SMUIO_BASE__INST6_SEG5                     0
>+
>+#define SMUIO_BASE__INST7_SEG0                     0
>+#define SMUIO_BASE__INST7_SEG1                     0
>+#define SMUIO_BASE__INST7_SEG2                     0
>+#define SMUIO_BASE__INST7_SEG3                     0
>+#define SMUIO_BASE__INST7_SEG4                     0
>+#define SMUIO_BASE__INST7_SEG5                     0
>+
>+#define THM_BASE__INST0_SEG0                       0x00012060
>+#define THM_BASE__INST0_SEG1                       0x00016600
>+#define THM_BASE__INST0_SEG2                       0x00400C00
>+#define THM_BASE__INST0_SEG3                       0
>+#define THM_BASE__INST0_SEG4                       0
>+#define THM_BASE__INST0_SEG5                       0
>+
>+#define THM_BASE__INST1_SEG0                       0
>+#define THM_BASE__INST1_SEG1                       0
>+#define THM_BASE__INST1_SEG2                       0
>+#define THM_BASE__INST1_SEG3                       0
>+#define THM_BASE__INST1_SEG4                       0
>+#define THM_BASE__INST1_SEG5                       0
>+
>+#define THM_BASE__INST2_SEG0                       0
>+#define THM_BASE__INST2_SEG1                       0
>+#define THM_BASE__INST2_SEG2                       0
>+#define THM_BASE__INST2_SEG3                       0
>+#define THM_BASE__INST2_SEG4                       0
>+#define THM_BASE__INST2_SEG5                       0
>+
>+#define THM_BASE__INST3_SEG0                       0
>+#define THM_BASE__INST3_SEG1                       0
>+#define THM_BASE__INST3_SEG2                       0
>+#define THM_BASE__INST3_SEG3                       0
>+#define THM_BASE__INST3_SEG4                       0
>+#define THM_BASE__INST3_SEG5                       0
>+
>+#define THM_BASE__INST4_SEG0                       0
>+#define THM_BASE__INST4_SEG1                       0
>+#define THM_BASE__INST4_SEG2                       0
>+#define THM_BASE__INST4_SEG3                       0
>+#define THM_BASE__INST4_SEG4                       0
>+#define THM_BASE__INST4_SEG5                       0
>+
>+#define THM_BASE__INST5_SEG0                       0
>+#define THM_BASE__INST5_SEG1                       0
>+#define THM_BASE__INST5_SEG2                       0
>+#define THM_BASE__INST5_SEG3                       0
>+#define THM_BASE__INST5_SEG4                       0
>+#define THM_BASE__INST5_SEG5                       0
>+
>+#define THM_BASE__INST6_SEG0                       0
>+#define THM_BASE__INST6_SEG1                       0
>+#define THM_BASE__INST6_SEG2                       0
>+#define THM_BASE__INST6_SEG3                       0
>+#define THM_BASE__INST6_SEG4                       0
>+#define THM_BASE__INST6_SEG5                       0
>+
>+#define THM_BASE__INST7_SEG0                       0
>+#define THM_BASE__INST7_SEG1                       0
>+#define THM_BASE__INST7_SEG2                       0
>+#define THM_BASE__INST7_SEG3                       0
>+#define THM_BASE__INST7_SEG4                       0
>+#define THM_BASE__INST7_SEG5                       0
>+
>+#define UMC_BASE__INST0_SEG0                       0x000132C0
>+#define UMC_BASE__INST0_SEG1                       0x00014000
>+#define UMC_BASE__INST0_SEG2                       0x00425800
>+#define UMC_BASE__INST0_SEG3                       0
>+#define UMC_BASE__INST0_SEG4                       0
>+#define UMC_BASE__INST0_SEG5                       0
>+
>+#define UMC_BASE__INST1_SEG0                       0x000132E0
>+#define UMC_BASE__INST1_SEG1                       0x00054000
>+#define UMC_BASE__INST1_SEG2                       0x00425C00
>+#define UMC_BASE__INST1_SEG3                       0
>+#define UMC_BASE__INST1_SEG4                       0
>+#define UMC_BASE__INST1_SEG5                       0
>+
>+#define UMC_BASE__INST2_SEG0                       0x00013300
>+#define UMC_BASE__INST2_SEG1                       0x00094000
>+#define UMC_BASE__INST2_SEG2                       0x00426000
>+#define UMC_BASE__INST2_SEG3                       0
>+#define UMC_BASE__INST2_SEG4                       0
>+#define UMC_BASE__INST2_SEG5                       0
>+
>+#define UMC_BASE__INST3_SEG0                       0x00013320
>+#define UMC_BASE__INST3_SEG1                       0x000D4000
>+#define UMC_BASE__INST3_SEG2                       0x00426400
>+#define UMC_BASE__INST3_SEG3                       0
>+#define UMC_BASE__INST3_SEG4                       0
>+#define UMC_BASE__INST3_SEG5                       0
>+
>+#define UMC_BASE__INST4_SEG0                       0x00013340
>+#define UMC_BASE__INST4_SEG1                       0x00114000
>+#define UMC_BASE__INST4_SEG2                       0x00426800
>+#define UMC_BASE__INST4_SEG3                       0
>+#define UMC_BASE__INST4_SEG4                       0
>+#define UMC_BASE__INST4_SEG5                       0
>+
>+#define UMC_BASE__INST5_SEG0                       0x00013360
>+#define UMC_BASE__INST5_SEG1                       0x00154000
>+#define UMC_BASE__INST5_SEG2                       0x00426C00
>+#define UMC_BASE__INST5_SEG3                       0
>+#define UMC_BASE__INST5_SEG4                       0
>+#define UMC_BASE__INST5_SEG5                       0
>+
>+#define UMC_BASE__INST6_SEG0                       0x00013380
>+#define UMC_BASE__INST6_SEG1                       0x00194000
>+#define UMC_BASE__INST6_SEG2                       0x00427000
>+#define UMC_BASE__INST6_SEG3                       0
>+#define UMC_BASE__INST6_SEG4                       0
>+#define UMC_BASE__INST6_SEG5                       0
>+
>+#define UMC_BASE__INST7_SEG0                       0x000133A0
>+#define UMC_BASE__INST7_SEG1                       0x001D4000
>+#define UMC_BASE__INST7_SEG2                       0x00427400
>+#define UMC_BASE__INST7_SEG3                       0
>+#define UMC_BASE__INST7_SEG4                       0
>+#define UMC_BASE__INST7_SEG5                       0
>+
>+#define UVD_BASE__INST0_SEG0                       0x00007800
>+#define UVD_BASE__INST0_SEG1                       0x00007E00
>+#define UVD_BASE__INST0_SEG2                       0x00012180
>+#define UVD_BASE__INST0_SEG3                       0x00403000
>+#define UVD_BASE__INST0_SEG4                       0
>+#define UVD_BASE__INST0_SEG5                       0
>+
>+#define UVD_BASE__INST1_SEG0                       0x00007A00
>+#define UVD_BASE__INST1_SEG1                       0x00009000
>+#define UVD_BASE__INST1_SEG2                       0x000136E0
>+#define UVD_BASE__INST1_SEG3                       0x0042DC00
>+#define UVD_BASE__INST1_SEG4                       0
>+#define UVD_BASE__INST1_SEG5                       0
>+
>+#define UVD_BASE__INST2_SEG0                       0
>+#define UVD_BASE__INST2_SEG1                       0
>+#define UVD_BASE__INST2_SEG2                       0
>+#define UVD_BASE__INST2_SEG3                       0
>+#define UVD_BASE__INST2_SEG4                       0
>+#define UVD_BASE__INST2_SEG5                       0
>+
>+#define UVD_BASE__INST3_SEG0                       0
>+#define UVD_BASE__INST3_SEG1                       0
>+#define UVD_BASE__INST3_SEG2                       0
>+#define UVD_BASE__INST3_SEG3                       0
>+#define UVD_BASE__INST3_SEG4                       0
>+#define UVD_BASE__INST3_SEG5                       0
>+
>+#define UVD_BASE__INST4_SEG0                       0
>+#define UVD_BASE__INST4_SEG1                       0
>+#define UVD_BASE__INST4_SEG2                       0
>+#define UVD_BASE__INST4_SEG3                       0
>+#define UVD_BASE__INST4_SEG4                       0
>+#define UVD_BASE__INST4_SEG5                       0
>+
>+#define UVD_BASE__INST5_SEG0                       0
>+#define UVD_BASE__INST5_SEG1                       0
>+#define UVD_BASE__INST5_SEG2                       0
>+#define UVD_BASE__INST5_SEG3                       0
>+#define UVD_BASE__INST5_SEG4                       0
>+#define UVD_BASE__INST5_SEG5                       0
>+
>+#define UVD_BASE__INST6_SEG0                       0
>+#define UVD_BASE__INST6_SEG1                       0
>+#define UVD_BASE__INST6_SEG2                       0
>+#define UVD_BASE__INST6_SEG3                       0
>+#define UVD_BASE__INST6_SEG4                       0
>+#define UVD_BASE__INST6_SEG5                       0
>+
>+#define UVD_BASE__INST7_SEG0                       0
>+#define UVD_BASE__INST7_SEG1                       0
>+#define UVD_BASE__INST7_SEG2                       0
>+#define UVD_BASE__INST7_SEG3                       0
>+#define UVD_BASE__INST7_SEG4                       0
>+#define UVD_BASE__INST7_SEG5                       0
>+
>+#define DBGU_IO_BASE__INST0_SEG0                   0x000001E0
>+#define DBGU_IO_BASE__INST0_SEG1                   0x000125A0
>+#define DBGU_IO_BASE__INST0_SEG2                   0x0040B400
>+#define DBGU_IO_BASE__INST0_SEG3                   0
>+#define DBGU_IO_BASE__INST0_SEG4                   0
>+#define DBGU_IO_BASE__INST0_SEG5                   0
>+
>+#define DBGU_IO_BASE__INST1_SEG0                   0
>+#define DBGU_IO_BASE__INST1_SEG1                   0
>+#define DBGU_IO_BASE__INST1_SEG2                   0
>+#define DBGU_IO_BASE__INST1_SEG3                   0
>+#define DBGU_IO_BASE__INST1_SEG4                   0
>+#define DBGU_IO_BASE__INST1_SEG5                   0
>+
>+#define DBGU_IO_BASE__INST2_SEG0                   0
>+#define DBGU_IO_BASE__INST2_SEG1                   0
>+#define DBGU_IO_BASE__INST2_SEG2                   0
>+#define DBGU_IO_BASE__INST2_SEG3                   0
>+#define DBGU_IO_BASE__INST2_SEG4                   0
>+#define DBGU_IO_BASE__INST2_SEG5                   0
>+
>+#define DBGU_IO_BASE__INST3_SEG0                   0
>+#define DBGU_IO_BASE__INST3_SEG1                   0
>+#define DBGU_IO_BASE__INST3_SEG2                   0
>+#define DBGU_IO_BASE__INST3_SEG3                   0
>+#define DBGU_IO_BASE__INST3_SEG4                   0
>+#define DBGU_IO_BASE__INST3_SEG5                   0
>+
>+#define DBGU_IO_BASE__INST4_SEG0                   0
>+#define DBGU_IO_BASE__INST4_SEG1                   0
>+#define DBGU_IO_BASE__INST4_SEG2                   0
>+#define DBGU_IO_BASE__INST4_SEG3                   0
>+#define DBGU_IO_BASE__INST4_SEG4                   0
>+#define DBGU_IO_BASE__INST4_SEG5                   0
>+
>+#define DBGU_IO_BASE__INST5_SEG0                   0
>+#define DBGU_IO_BASE__INST5_SEG1                   0
>+#define DBGU_IO_BASE__INST5_SEG2                   0
>+#define DBGU_IO_BASE__INST5_SEG3                   0
>+#define DBGU_IO_BASE__INST5_SEG4                   0
>+#define DBGU_IO_BASE__INST5_SEG5                   0
>+
>+#define DBGU_IO_BASE__INST6_SEG0                   0
>+#define DBGU_IO_BASE__INST6_SEG1                   0
>+#define DBGU_IO_BASE__INST6_SEG2                   0
>+#define DBGU_IO_BASE__INST6_SEG3                   0
>+#define DBGU_IO_BASE__INST6_SEG4                   0
>+#define DBGU_IO_BASE__INST6_SEG5                   0
>+
>+#define DBGU_IO_BASE__INST7_SEG0                   0
>+#define DBGU_IO_BASE__INST7_SEG1                   0
>+#define DBGU_IO_BASE__INST7_SEG2                   0
>+#define DBGU_IO_BASE__INST7_SEG3                   0
>+#define DBGU_IO_BASE__INST7_SEG4                   0
>+#define DBGU_IO_BASE__INST7_SEG5                   0
>+
>+#define RSMU_BASE__INST0_SEG0                   0x00012000
>+#define RSMU_BASE__INST0_SEG1                   0
>+#define RSMU_BASE__INST0_SEG2                   0
>+#define RSMU_BASE__INST0_SEG3                   0
>+#define RSMU_BASE__INST0_SEG4                   0
>+#define RSMU_BASE__INST0_SEG5                   0
>+
>+#define RSMU_BASE__INST1_SEG0                   0
>+#define RSMU_BASE__INST1_SEG1                   0
>+#define RSMU_BASE__INST1_SEG2                   0
>+#define RSMU_BASE__INST1_SEG3                   0
>+#define RSMU_BASE__INST1_SEG4                   0
>+#define RSMU_BASE__INST1_SEG5                   0
>+
>+#define RSMU_BASE__INST2_SEG0                   0
>+#define RSMU_BASE__INST2_SEG1                   0
>+#define RSMU_BASE__INST2_SEG2                   0
>+#define RSMU_BASE__INST2_SEG3                   0
>+#define RSMU_BASE__INST2_SEG4                   0
>+#define RSMU_BASE__INST2_SEG5                   0
>+
>+#define RSMU_BASE__INST3_SEG0                   0
>+#define RSMU_BASE__INST3_SEG1                   0
>+#define RSMU_BASE__INST3_SEG2                   0
>+#define RSMU_BASE__INST3_SEG3                   0
>+#define RSMU_BASE__INST3_SEG4                   0
>+#define RSMU_BASE__INST3_SEG5                   0
>+
>+#define RSMU_BASE__INST4_SEG0                   0
>+#define RSMU_BASE__INST4_SEG1                   0
>+#define RSMU_BASE__INST4_SEG2                   0
>+#define RSMU_BASE__INST4_SEG3                   0
>+#define RSMU_BASE__INST4_SEG4                   0
>+#define RSMU_BASE__INST4_SEG5                   0
>+
>+#define RSMU_BASE__INST5_SEG0                   0
>+#define RSMU_BASE__INST5_SEG1                   0
>+#define RSMU_BASE__INST5_SEG2                   0
>+#define RSMU_BASE__INST5_SEG3                   0
>+#define RSMU_BASE__INST5_SEG4                   0
>+#define RSMU_BASE__INST5_SEG5                   0
>+
>+#define RSMU_BASE__INST6_SEG0                   0
>+#define RSMU_BASE__INST6_SEG1                   0
>+#define RSMU_BASE__INST6_SEG2                   0
>+#define RSMU_BASE__INST6_SEG3                   0
>+#define RSMU_BASE__INST6_SEG4                   0
>+#define RSMU_BASE__INST6_SEG5                   0
>+
>+#define RSMU_BASE__INST7_SEG0                   0
>+#define RSMU_BASE__INST7_SEG1                   0
>+#define RSMU_BASE__INST7_SEG2                   0
>+#define RSMU_BASE__INST7_SEG3                   0
>+#define RSMU_BASE__INST7_SEG4                   0
>+#define RSMU_BASE__INST7_SEG5                   0
>+
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h	2019-08-31 15:01:11.873736170 -0500
>@@ -0,0 +1,56 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _clk_10_0_2_OFFSET_HEADER
>+#define _clk_10_0_2_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: clk_clk1_0_SmuClkDec
>+// base address: 0x5b800
>+#define mmCLK1_CLK_PLL_REQ                                                                             0x000f
>+#define mmCLK1_CLK_PLL_REQ_BASE_IDX                                                                    1
>+#define mmCLK1_CLK0_BYPASS_CNTL                                                                        0x0049
>+#define mmCLK1_CLK0_BYPASS_CNTL_BASE_IDX                                                               1
>+#define mmCLK1_CLK1_BYPASS_CNTL                                                                        0x0053
>+#define mmCLK1_CLK1_BYPASS_CNTL_BASE_IDX                                                               1
>+#define mmCLK1_CLK2_BYPASS_CNTL                                                                        0x005d
>+#define mmCLK1_CLK2_BYPASS_CNTL_BASE_IDX                                                               1
>+#define mmCLK1_CLK2_STATUS                                                                             0x005e
>+#define mmCLK1_CLK2_STATUS_BASE_IDX                                                                    1
>+#define mmCLK1_CLK3_DFS_CNTL                                                                           0x005f
>+#define mmCLK1_CLK3_DFS_CNTL_BASE_IDX                                                                  1
>+#define mmCLK1_CLK3_DS_CNTL                                                                            0x0060
>+#define mmCLK1_CLK3_DS_CNTL_BASE_IDX                                                                   1
>+#define mmCLK1_CLK3_ALLOW_DS                                                                           0x0061
>+#define mmCLK1_CLK3_ALLOW_DS_BASE_IDX                                                                  1
>+#define mmCLK1_CLK3_BYPASS_CNTL                                                                        0x0067
>+#define mmCLK1_CLK3_BYPASS_CNTL_BASE_IDX                                                               1
>+#define mmCLK1_CLK0_CURRENT_CNT                                                                        0x008a
>+#define mmCLK1_CLK0_CURRENT_CNT_BASE_IDX                                                               1
>+#define mmCLK1_CLK1_CURRENT_CNT                                                                        0x008b
>+#define mmCLK1_CLK1_CURRENT_CNT_BASE_IDX                                                               1
>+#define mmCLK1_CLK2_CURRENT_CNT                                                                        0x008c
>+#define mmCLK1_CLK2_CURRENT_CNT_BASE_IDX                                                               1
>+#define mmCLK1_CLK3_CURRENT_CNT                                                                        0x008d
>+#define mmCLK1_CLK3_CURRENT_CNT_BASE_IDX                                                               1
>+
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h	2019-08-31 15:01:11.873736170 -0500
>@@ -0,0 +1,73 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _clk_10_0_2_SH_MASK_HEADER
>+#define _clk_10_0_2_SH_MASK_HEADER
>+
>+
>+// addressBlock: clk_clk1_0_SmuClkDec
>+//CLK1_CLK_PLL_REQ
>+#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                                   0x0
>+#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                                  0xc
>+#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                                  0x10
>+#define CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                                     0x000001FFL
>+#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK                                                                    0x0000F000L
>+#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                                    0xFFFF0000L
>+//CLK1_CLK0_BYPASS_CNTL
>+#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT                                                         0x0
>+#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT                                                         0x10
>+#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK                                                           0x00000007L
>+#define CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK                                                           0x000F0000L
>+//CLK1_CLK1_BYPASS_CNTL
>+#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT                                                         0x0
>+#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT                                                         0x10
>+#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK                                                           0x00000007L
>+#define CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK                                                           0x000F0000L
>+//CLK1_CLK2_BYPASS_CNTL
>+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT                                                         0x0
>+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT                                                         0x10
>+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK                                                           0x00000007L
>+#define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK                                                           0x000F0000L
>+//CLK1_CLK3_DS_CNTL
>+#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT                                                              0x0
>+#define CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK                                                                0x00000007L
>+//CLK1_CLK3_ALLOW_DS
>+#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT                                                              0x0
>+#define CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK                                                                0x00000001L
>+//CLK1_CLK3_BYPASS_CNTL
>+#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT                                                         0x0
>+#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT                                                         0x10
>+#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK                                                           0x00000007L
>+#define CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK                                                           0x000F0000L
>+//CLK1_CLK0_CURRENT_CNT
>+#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
>+#define CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
>+//CLK1_CLK1_CURRENT_CNT
>+#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
>+#define CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
>+//CLK1_CLK2_CURRENT_CNT
>+#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
>+#define CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
>+//CLK1_CLK3_CURRENT_CNT
>+#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                           0x0
>+#define CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK                                                             0xFFFFFFFFL
>+
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h	2019-08-31 15:01:11.876736170 -0500
>@@ -0,0 +1,13862 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _dcn_2_1_0_OFFSET_HEADER
>+#define _dcn_2_1_0_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
>+// base address: 0x48
>+#define mmVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
>+#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
>+#define mmVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
>+#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
>+
>+
>+// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
>+// base address: 0x3b4
>+#define mmCRTC8_IDX                                                                                    0x002d
>+#define mmCRTC8_IDX_BASE_IDX                                                                           1
>+#define mmCRTC8_DATA                                                                                   0x002d
>+#define mmCRTC8_DATA_BASE_IDX                                                                          1
>+#define mmGENFC_WT                                                                                     0x002e
>+#define mmGENFC_WT_BASE_IDX                                                                            1
>+#define mmGENS1                                                                                        0x002e
>+#define mmGENS1_BASE_IDX                                                                               1
>+#define mmATTRDW                                                                                       0x0030
>+#define mmATTRDW_BASE_IDX                                                                              1
>+#define mmATTRX                                                                                        0x0030
>+#define mmATTRX_BASE_IDX                                                                               1
>+#define mmATTRDR                                                                                       0x0030
>+#define mmATTRDR_BASE_IDX                                                                              1
>+#define mmGENMO_WT                                                                                     0x0030
>+#define mmGENMO_WT_BASE_IDX                                                                            1
>+#define mmGENS0                                                                                        0x0030
>+#define mmGENS0_BASE_IDX                                                                               1
>+#define mmGENENB                                                                                       0x0030
>+#define mmGENENB_BASE_IDX                                                                              1
>+#define mmSEQ8_IDX                                                                                     0x0031
>+#define mmSEQ8_IDX_BASE_IDX                                                                            1
>+#define mmSEQ8_DATA                                                                                    0x0031
>+#define mmSEQ8_DATA_BASE_IDX                                                                           1
>+#define mmDAC_MASK                                                                                     0x0031
>+#define mmDAC_MASK_BASE_IDX                                                                            1
>+#define mmDAC_R_INDEX                                                                                  0x0031
>+#define mmDAC_R_INDEX_BASE_IDX                                                                         1
>+#define mmDAC_W_INDEX                                                                                  0x0032
>+#define mmDAC_W_INDEX_BASE_IDX                                                                         1
>+#define mmDAC_DATA                                                                                     0x0032
>+#define mmDAC_DATA_BASE_IDX                                                                            1
>+#define mmGENFC_RD                                                                                     0x0032
>+#define mmGENFC_RD_BASE_IDX                                                                            1
>+#define mmGENMO_RD                                                                                     0x0033
>+#define mmGENMO_RD_BASE_IDX                                                                            1
>+#define mmGRPH8_IDX                                                                                    0x0033
>+#define mmGRPH8_IDX_BASE_IDX                                                                           1
>+#define mmGRPH8_DATA                                                                                   0x0033
>+#define mmGRPH8_DATA_BASE_IDX                                                                          1
>+#define mmCRTC8_IDX_1                                                                                  0x0035
>+#define mmCRTC8_IDX_1_BASE_IDX                                                                         1
>+#define mmCRTC8_DATA_1                                                                                 0x0035
>+#define mmCRTC8_DATA_1_BASE_IDX                                                                        1
>+#define mmGENFC_WT_1                                                                                   0x0036
>+#define mmGENFC_WT_1_BASE_IDX                                                                          1
>+#define mmGENS1_1                                                                                      0x0036
>+#define mmGENS1_1_BASE_IDX                                                                             1
>+
>+
>+// addressBlock: dce_dc_mmhubbub_vga_dispdec
>+// base address: 0x0
>+#define mmVGA_RENDER_CONTROL                                                                           0x0000
>+#define mmVGA_RENDER_CONTROL_BASE_IDX                                                                  1
>+#define mmVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
>+#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
>+#define mmVGA_MODE_CONTROL                                                                             0x0002
>+#define mmVGA_MODE_CONTROL_BASE_IDX                                                                    1
>+#define mmVGA_SURFACE_PITCH_SELECT                                                                     0x0003
>+#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
>+#define mmVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
>+#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
>+#define mmVGA_TEST_DEBUG_INDEX                                                                         0x0005
>+#define mmVGA_TEST_DEBUG_INDEX_BASE_IDX                                                                1
>+#define mmVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
>+#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
>+#define mmVGA_TEST_DEBUG_DATA                                                                          0x0007
>+#define mmVGA_TEST_DEBUG_DATA_BASE_IDX                                                                 1
>+#define mmVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
>+#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
>+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
>+#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
>+#define mmVGA_HDP_CONTROL                                                                              0x000a
>+#define mmVGA_HDP_CONTROL_BASE_IDX                                                                     1
>+#define mmVGA_CACHE_CONTROL                                                                            0x000b
>+#define mmVGA_CACHE_CONTROL_BASE_IDX                                                                   1
>+#define mmD1VGA_CONTROL                                                                                0x000c
>+#define mmD1VGA_CONTROL_BASE_IDX                                                                       1
>+#define mmVGA_SECURITY_LEVEL                                                                           0x000d
>+#define mmVGA_SECURITY_LEVEL_BASE_IDX                                                                  1
>+#define mmD2VGA_CONTROL                                                                                0x000e
>+#define mmD2VGA_CONTROL_BASE_IDX                                                                       1
>+#define mmVGA_HW_DEBUG                                                                                 0x000f
>+#define mmVGA_HW_DEBUG_BASE_IDX                                                                        1
>+#define mmVGA_STATUS                                                                                   0x0010
>+#define mmVGA_STATUS_BASE_IDX                                                                          1
>+#define mmVGA_INTERRUPT_CONTROL                                                                        0x0011
>+#define mmVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
>+#define mmVGA_STATUS_CLEAR                                                                             0x0012
>+#define mmVGA_STATUS_CLEAR_BASE_IDX                                                                    1
>+#define mmVGA_INTERRUPT_STATUS                                                                         0x0013
>+#define mmVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
>+#define mmVGA_MAIN_CONTROL                                                                             0x0014
>+#define mmVGA_MAIN_CONTROL_BASE_IDX                                                                    1
>+#define mmVGA_TEST_CONTROL                                                                             0x0015
>+#define mmVGA_TEST_CONTROL_BASE_IDX                                                                    1
>+#define mmVGA_DEBUG_READBACK_INDEX                                                                     0x0016
>+#define mmVGA_DEBUG_READBACK_INDEX_BASE_IDX                                                            1
>+#define mmVGA_DEBUG_READBACK_DATA                                                                      0x0017
>+#define mmVGA_DEBUG_READBACK_DATA_BASE_IDX                                                             1
>+#define mmVGA_QOS_CTRL                                                                                 0x0018
>+#define mmVGA_QOS_CTRL_BASE_IDX                                                                        1
>+#define mmD3VGA_CONTROL                                                                                0x0038
>+#define mmD3VGA_CONTROL_BASE_IDX                                                                       1
>+#define mmD4VGA_CONTROL                                                                                0x0039
>+#define mmD4VGA_CONTROL_BASE_IDX                                                                       1
>+#define mmD5VGA_CONTROL                                                                                0x003a
>+#define mmD5VGA_CONTROL_BASE_IDX                                                                       1
>+#define mmD6VGA_CONTROL                                                                                0x003b
>+#define mmD6VGA_CONTROL_BASE_IDX                                                                       1
>+#define mmVGA_SOURCE_SELECT                                                                            0x003c
>+#define mmVGA_SOURCE_SELECT_BASE_IDX                                                                   1
>+
>+
>+// addressBlock: dce_dc_dccg_dccg_dispdec
>+// base address: 0x0
>+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
>+#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
>+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
>+#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
>+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
>+#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
>+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
>+#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
>+#define mmDP_DTO_DBUF_EN                                                                               0x0044
>+#define mmDP_DTO_DBUF_EN_BASE_IDX                                                                      1
>+#define mmDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
>+#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
>+#define mmREFCLK_CNTL                                                                                  0x0049
>+#define mmREFCLK_CNTL_BASE_IDX                                                                         1
>+#define mmREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
>+#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
>+#define mmPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
>+#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
>+#define mmDCCG_PERFMON_CNTL2                                                                           0x004e
>+#define mmDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1
>+#define mmDCCG_DS_DTO_INCR                                                                             0x0053
>+#define mmDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
>+#define mmDCCG_DS_DTO_MODULO                                                                           0x0054
>+#define mmDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
>+#define mmDCCG_DS_CNTL                                                                                 0x0055
>+#define mmDCCG_DS_CNTL_BASE_IDX                                                                        1
>+#define mmDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
>+#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
>+#define mmDPREFCLK_CNTL                                                                                0x0058
>+#define mmDPREFCLK_CNTL_BASE_IDX                                                                       1
>+#define mmDCE_VERSION                                                                                  0x005e
>+#define mmDCE_VERSION_BASE_IDX                                                                         1
>+#define mmDCCG_GTC_CNTL                                                                                0x0060
>+#define mmDCCG_GTC_CNTL_BASE_IDX                                                                       1
>+#define mmDCCG_GTC_DTO_INCR                                                                            0x0061
>+#define mmDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
>+#define mmDCCG_GTC_DTO_MODULO                                                                          0x0062
>+#define mmDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
>+#define mmDCCG_GTC_CURRENT                                                                             0x0063
>+#define mmDCCG_GTC_CURRENT_BASE_IDX                                                                    1
>+#define mmDSCCLK0_DTO_PARAM                                                                            0x006c
>+#define mmDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
>+#define mmDSCCLK1_DTO_PARAM                                                                            0x006d
>+#define mmDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
>+#define mmDSCCLK2_DTO_PARAM                                                                            0x006e
>+#define mmDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
>+#define mmMILLISECOND_TIME_BASE_DIV                                                                    0x0070
>+#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
>+#define mmDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
>+#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
>+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
>+#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
>+#define mmDCCG_PERFMON_CNTL                                                                            0x0073
>+#define mmDCCG_PERFMON_CNTL_BASE_IDX                                                                   1
>+#define mmDCCG_GATE_DISABLE_CNTL                                                                       0x0074
>+#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
>+#define mmDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
>+#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
>+#define mmSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
>+#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
>+#define mmDCCG_CAC_STATUS                                                                              0x0077
>+#define mmDCCG_CAC_STATUS_BASE_IDX                                                                     1
>+#define mmMICROSECOND_TIME_BASE_DIV                                                                    0x007b
>+#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
>+#define mmDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
>+#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
>+#define mmSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
>+#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
>+#define mmDCCG_DISP_CNTL_REG                                                                           0x007f
>+#define mmDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
>+#define mmOTG0_PIXEL_RATE_CNTL                                                                         0x0080
>+#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
>+#define mmDP_DTO0_PHASE                                                                                0x0081
>+#define mmDP_DTO0_PHASE_BASE_IDX                                                                       1
>+#define mmDP_DTO0_MODULO                                                                               0x0082
>+#define mmDP_DTO0_MODULO_BASE_IDX                                                                      1
>+#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
>+#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
>+#define mmOTG1_PIXEL_RATE_CNTL                                                                         0x0084
>+#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
>+#define mmDP_DTO1_PHASE                                                                                0x0085
>+#define mmDP_DTO1_PHASE_BASE_IDX                                                                       1
>+#define mmDP_DTO1_MODULO                                                                               0x0086
>+#define mmDP_DTO1_MODULO_BASE_IDX                                                                      1
>+#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
>+#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
>+#define mmOTG2_PIXEL_RATE_CNTL                                                                         0x0088
>+#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
>+#define mmDP_DTO2_PHASE                                                                                0x0089
>+#define mmDP_DTO2_PHASE_BASE_IDX                                                                       1
>+#define mmDP_DTO2_MODULO                                                                               0x008a
>+#define mmDP_DTO2_MODULO_BASE_IDX                                                                      1
>+#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
>+#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
>+#define mmOTG3_PIXEL_RATE_CNTL                                                                         0x008c
>+#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
>+#define mmDP_DTO3_PHASE                                                                                0x008d
>+#define mmDP_DTO3_PHASE_BASE_IDX                                                                       1
>+#define mmDP_DTO3_MODULO                                                                               0x008e
>+#define mmDP_DTO3_MODULO_BASE_IDX                                                                      1
>+#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
>+#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
>+#define mmDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
>+#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
>+#define mmDPPCLK0_DTO_PARAM                                                                            0x0099
>+#define mmDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
>+#define mmDPPCLK1_DTO_PARAM                                                                            0x009a
>+#define mmDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
>+#define mmDPPCLK2_DTO_PARAM                                                                            0x009b
>+#define mmDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
>+#define mmDPPCLK3_DTO_PARAM                                                                            0x009c
>+#define mmDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
>+#define mmDCCG_CAC_STATUS2                                                                             0x009f
>+#define mmDCCG_CAC_STATUS2_BASE_IDX                                                                    1
>+#define mmSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
>+#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
>+#define mmSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
>+#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
>+#define mmSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
>+#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
>+#define mmSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
>+#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
>+#define mmSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
>+#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
>+#define mmDCCG_SOFT_RESET                                                                              0x00a6
>+#define mmDCCG_SOFT_RESET_BASE_IDX                                                                     1
>+#define mmDSCCLK_DTO_CTRL                                                                              0x00a7
>+#define mmDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
>+#define mmDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
>+#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
>+#define mmDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
>+#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
>+#define mmDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
>+#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
>+#define mmDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
>+#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
>+#define mmDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
>+#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
>+#define mmDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
>+#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
>+#define mmDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
>+#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
>+#define mmDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
>+#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
>+#define mmDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
>+#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
>+#define mmDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
>+#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
>+#define mmDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
>+#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
>+#define mmDPPCLK_DTO_CTRL                                                                              0x00b6
>+#define mmDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
>+#define mmDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
>+#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
>+#define mmDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
>+#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
>+#define mmFORCE_SYMCLK_DISABLE                                                                         0x00ba
>+#define mmFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
>+#define mmDCCG_TEST_CLK_SEL                                                                            0x00be
>+#define mmDCCG_TEST_CLK_SEL_BASE_IDX                                                                   1
>+
>+
>+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
>+// base address: 0x0
>+#define mmDENTIST_DISPCLK_CNTL                                                                         0x0064
>+#define mmDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
>+
>+
>+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
>+// base address: 0x0
>+#define mmDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0000
>+#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2
>+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0001
>+#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
>+#define mmDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0002
>+#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2
>+#define mmDC_PERFMON0_PERFMON_CNTL                                                                     0x0003
>+#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2
>+#define mmDC_PERFMON0_PERFMON_CNTL2                                                                    0x0004
>+#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2
>+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0005
>+#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
>+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0006
>+#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
>+#define mmDC_PERFMON0_PERFMON_HI                                                                       0x0007
>+#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2
>+#define mmDC_PERFMON0_PERFMON_LOW                                                                      0x0008
>+#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
>+// base address: 0x30
>+#define mmDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x000c
>+#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2
>+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x000d
>+#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
>+#define mmDC_PERFMON1_PERFCOUNTER_STATE                                                                0x000e
>+#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2
>+#define mmDC_PERFMON1_PERFMON_CNTL                                                                     0x000f
>+#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2
>+#define mmDC_PERFMON1_PERFMON_CNTL2                                                                    0x0010
>+#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2
>+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x0011
>+#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
>+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x0012
>+#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
>+#define mmDC_PERFMON1_PERFMON_HI                                                                       0x0013
>+#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2
>+#define mmDC_PERFMON1_PERFMON_LOW                                                                      0x0014
>+#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_dccg_dccg_pll_dispdec
>+// base address: 0x0
>+#define mmPLL_MACRO_CNTL_RESERVED0                                                                     0x0018
>+#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX                                                            2
>+#define mmPLL_MACRO_CNTL_RESERVED1                                                                     0x0019
>+#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX                                                            2
>+#define mmPLL_MACRO_CNTL_RESERVED2                                                                     0x001a
>+#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX                                                            2
>+#define mmPLL_MACRO_CNTL_RESERVED3                                                                     0x001b
>+#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX                                                            2
>+#define mmPLL_MACRO_CNTL_RESERVED4                                                                     0x001c
>+#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX                                                            2
>+#define mmPLL_MACRO_CNTL_RESERVED5                                                                     0x001d
>+#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX                                                            2
>+#define mmPLL_MACRO_CNTL_RESERVED6                                                                     0x001e
>+#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX                                                            2
>+#define mmPLL_MACRO_CNTL_RESERVED7                                                                     0x001f
>+#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX                                                            2
>+#define mmPLL_MACRO_CNTL_RESERVED8                                                                     0x0020
>+#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX                                                            2
>+#define mmPLL_MACRO_CNTL_RESERVED9                                                                     0x0021
>+#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX                                                            2
>+#define mmPLL_MACRO_CNTL_RESERVED10                                                                    0x0022
>+#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED11                                                                    0x0023
>+#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED12                                                                    0x0024
>+#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED13                                                                    0x0025
>+#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED14                                                                    0x0026
>+#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED15                                                                    0x0027
>+#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED16                                                                    0x0028
>+#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED17                                                                    0x0029
>+#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED18                                                                    0x002a
>+#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED19                                                                    0x002b
>+#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED20                                                                    0x002c
>+#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED21                                                                    0x002d
>+#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED22                                                                    0x002e
>+#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED23                                                                    0x002f
>+#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED24                                                                    0x0030
>+#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED25                                                                    0x0031
>+#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED26                                                                    0x0032
>+#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED27                                                                    0x0033
>+#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED28                                                                    0x0034
>+#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED29                                                                    0x0035
>+#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED30                                                                    0x0036
>+#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED31                                                                    0x0037
>+#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED32                                                                    0x0038
>+#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED33                                                                    0x0039
>+#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED34                                                                    0x003a
>+#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED35                                                                    0x003b
>+#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED36                                                                    0x003c
>+#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED37                                                                    0x003d
>+#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED38                                                                    0x003e
>+#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED39                                                                    0x003f
>+#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED40                                                                    0x0040
>+#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX                                                           2
>+#define mmPLL_MACRO_CNTL_RESERVED41                                                                    0x0041
>+#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX                                                           2
>+
>+
>+// addressBlock: dce_dc_dmu_rbbmif_dispdec
>+// base address: 0x0
>+#define mmRBBMIF_TIMEOUT                                                                               0x005b
>+#define mmRBBMIF_TIMEOUT_BASE_IDX                                                                      2
>+#define mmRBBMIF_STATUS                                                                                0x005c
>+#define mmRBBMIF_STATUS_BASE_IDX                                                                       2
>+#define mmRBBMIF_STATUS_2                                                                              0x005d
>+#define mmRBBMIF_STATUS_2_BASE_IDX                                                                     2
>+#define mmRBBMIF_INT_STATUS                                                                            0x005e
>+#define mmRBBMIF_INT_STATUS_BASE_IDX                                                                   2
>+#define mmRBBMIF_TIMEOUT_DIS                                                                           0x005f
>+#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
>+#define mmRBBMIF_TIMEOUT_DIS_2                                                                         0x0060
>+#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
>+#define mmRBBMIF_STATUS_FLAG                                                                           0x0061
>+#define mmRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
>+
>+
>+// addressBlock: dce_dc_dmu_dc_pg_dispdec
>+// base address: 0x0
>+#define mmDOMAIN0_PG_CONFIG                                                                            0x0080
>+#define mmDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
>+#define mmDOMAIN0_PG_STATUS                                                                            0x0081
>+#define mmDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
>+#define mmDOMAIN1_PG_CONFIG                                                                            0x0082
>+#define mmDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
>+#define mmDOMAIN1_PG_STATUS                                                                            0x0083
>+#define mmDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
>+#define mmDOMAIN2_PG_CONFIG                                                                            0x0084
>+#define mmDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
>+#define mmDOMAIN2_PG_STATUS                                                                            0x0085
>+#define mmDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
>+#define mmDOMAIN3_PG_CONFIG                                                                            0x0086
>+#define mmDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
>+#define mmDOMAIN3_PG_STATUS                                                                            0x0087
>+#define mmDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
>+#define mmDOMAIN4_PG_CONFIG                                                                            0x0088
>+#define mmDOMAIN4_PG_CONFIG_BASE_IDX                                                                   2
>+#define mmDOMAIN4_PG_STATUS                                                                            0x0089
>+#define mmDOMAIN4_PG_STATUS_BASE_IDX                                                                   2
>+#define mmDOMAIN5_PG_CONFIG                                                                            0x008a
>+#define mmDOMAIN5_PG_CONFIG_BASE_IDX                                                                   2
>+#define mmDOMAIN5_PG_STATUS                                                                            0x008b
>+#define mmDOMAIN5_PG_STATUS_BASE_IDX                                                                   2
>+#define mmDOMAIN6_PG_CONFIG                                                                            0x008c
>+#define mmDOMAIN6_PG_CONFIG_BASE_IDX                                                                   2
>+#define mmDOMAIN6_PG_STATUS                                                                            0x008d
>+#define mmDOMAIN6_PG_STATUS_BASE_IDX                                                                   2
>+#define mmDOMAIN7_PG_CONFIG                                                                            0x008e
>+#define mmDOMAIN7_PG_CONFIG_BASE_IDX                                                                   2
>+#define mmDOMAIN7_PG_STATUS                                                                            0x008f
>+#define mmDOMAIN7_PG_STATUS_BASE_IDX                                                                   2
>+#define mmDOMAIN16_PG_CONFIG                                                                           0x00a1
>+#define mmDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
>+#define mmDOMAIN16_PG_STATUS                                                                           0x00a2
>+#define mmDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
>+#define mmDOMAIN17_PG_CONFIG                                                                           0x00a3
>+#define mmDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
>+#define mmDOMAIN17_PG_STATUS                                                                           0x00a4
>+#define mmDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
>+#define mmDOMAIN18_PG_CONFIG                                                                           0x00a5
>+#define mmDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
>+#define mmDOMAIN18_PG_STATUS                                                                           0x00a6
>+#define mmDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
>+#define mmDCPG_INTERRUPT_STATUS                                                                        0x00ad
>+#define mmDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
>+#define mmDCPG_INTERRUPT_STATUS_2                                                                      0x00ae
>+#define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
>+#define mmDCPG_INTERRUPT_CONTROL_1                                                                     0x00af
>+#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
>+#define mmDCPG_INTERRUPT_CONTROL_2                                                                     0x00b0
>+#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX                                                            2
>+#define mmDCPG_INTERRUPT_CONTROL_3                                                                     0x00b1
>+#define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
>+#define mmDC_IP_REQUEST_CNTL                                                                           0x00b2
>+#define mmDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
>+
>+
>+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x2f8
>+#define mmDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x00be
>+#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2
>+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x00bf
>+#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
>+#define mmDC_PERFMON2_PERFCOUNTER_STATE                                                                0x00c0
>+#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2
>+#define mmDC_PERFMON2_PERFMON_CNTL                                                                     0x00c1
>+#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2
>+#define mmDC_PERFMON2_PERFMON_CNTL2                                                                    0x00c2
>+#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2
>+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x00c3
>+#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
>+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x00c4
>+#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
>+#define mmDC_PERFMON2_PERFMON_HI                                                                       0x00c5
>+#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2
>+#define mmDC_PERFMON2_PERFMON_LOW                                                                      0x00c6
>+#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
>+// base address: 0x0
>+#define mmCC_DC_PIPE_DIS                                                                               0x00ca
>+#define mmCC_DC_PIPE_DIS_BASE_IDX                                                                      2
>+#define mmDMU_CLK_CNTL                                                                                 0x00cb
>+#define mmDMU_CLK_CNTL_BASE_IDX                                                                        2
>+#define mmDMU_MEM_PWR_CNTL                                                                             0x00cc
>+#define mmDMU_MEM_PWR_CNTL_BASE_IDX                                                                    2
>+#define mmDMCU_SMU_INTERRUPT_CNTL                                                                      0x00cd
>+#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX                                                             2
>+#define mmSMU_INTERRUPT_CONTROL                                                                        0x00ce
>+#define mmSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
>+#define mmDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
>+#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_dmu_dmcu_dispdec
>+// base address: 0x0
>+#define mmDMCU_CTRL                                                                                    0x00da
>+#define mmDMCU_CTRL_BASE_IDX                                                                           2
>+#define mmDMCU_STATUS                                                                                  0x00db
>+#define mmDMCU_STATUS_BASE_IDX                                                                         2
>+#define mmDMCU_PC_START_ADDR                                                                           0x00dc
>+#define mmDMCU_PC_START_ADDR_BASE_IDX                                                                  2
>+#define mmDMCU_FW_START_ADDR                                                                           0x00dd
>+#define mmDMCU_FW_START_ADDR_BASE_IDX                                                                  2
>+#define mmDMCU_FW_END_ADDR                                                                             0x00de
>+#define mmDMCU_FW_END_ADDR_BASE_IDX                                                                    2
>+#define mmDMCU_FW_ISR_START_ADDR                                                                       0x00df
>+#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX                                                              2
>+#define mmDMCU_FW_CS_HI                                                                                0x00e0
>+#define mmDMCU_FW_CS_HI_BASE_IDX                                                                       2
>+#define mmDMCU_FW_CS_LO                                                                                0x00e1
>+#define mmDMCU_FW_CS_LO_BASE_IDX                                                                       2
>+#define mmDMCU_RAM_ACCESS_CTRL                                                                         0x00e2
>+#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX                                                                2
>+#define mmDMCU_ERAM_WR_CTRL                                                                            0x00e3
>+#define mmDMCU_ERAM_WR_CTRL_BASE_IDX                                                                   2
>+#define mmDMCU_ERAM_WR_DATA                                                                            0x00e4
>+#define mmDMCU_ERAM_WR_DATA_BASE_IDX                                                                   2
>+#define mmDMCU_ERAM_RD_CTRL                                                                            0x00e5
>+#define mmDMCU_ERAM_RD_CTRL_BASE_IDX                                                                   2
>+#define mmDMCU_ERAM_RD_DATA                                                                            0x00e6
>+#define mmDMCU_ERAM_RD_DATA_BASE_IDX                                                                   2
>+#define mmDMCU_IRAM_WR_CTRL                                                                            0x00e7
>+#define mmDMCU_IRAM_WR_CTRL_BASE_IDX                                                                   2
>+#define mmDMCU_IRAM_WR_DATA                                                                            0x00e8
>+#define mmDMCU_IRAM_WR_DATA_BASE_IDX                                                                   2
>+#define mmDMCU_IRAM_RD_CTRL                                                                            0x00e9
>+#define mmDMCU_IRAM_RD_CTRL_BASE_IDX                                                                   2
>+#define mmDMCU_IRAM_RD_DATA                                                                            0x00ea
>+#define mmDMCU_IRAM_RD_DATA_BASE_IDX                                                                   2
>+#define mmDMCU_EVENT_TRIGGER                                                                           0x00eb
>+#define mmDMCU_EVENT_TRIGGER_BASE_IDX                                                                  2
>+#define mmDMCU_UC_INTERNAL_INT_STATUS                                                                  0x00ec
>+#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX                                                         2
>+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS                                                                0x00ed
>+#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX                                                       2
>+#define mmDMCU_INTERRUPT_STATUS                                                                        0x00ee
>+#define mmDMCU_INTERRUPT_STATUS_BASE_IDX                                                               2
>+#define mmDMCU_INTERRUPT_STATUS_1                                                                      0x00ef
>+#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX                                                             2
>+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK                                                               0x00f0
>+#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX                                                      2
>+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK                                                                 0x00f1
>+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
>+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1                                                               0x00f2
>+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX                                                      2
>+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                                            0x00f3
>+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
>+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                                          0x00f4
>+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX                                                 2
>+#define mmDC_DMCU_SCRATCH                                                                              0x00f5
>+#define mmDC_DMCU_SCRATCH_BASE_IDX                                                                     2
>+#define mmDMCU_INT_CNT                                                                                 0x00f6
>+#define mmDMCU_INT_CNT_BASE_IDX                                                                        2
>+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                                               0x00f7
>+#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX                                                      2
>+#define mmDMCU_UC_CLK_GATING_CNTL                                                                      0x00f8
>+#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
>+#define mmMASTER_COMM_DATA_REG1                                                                        0x00f9
>+#define mmMASTER_COMM_DATA_REG1_BASE_IDX                                                               2
>+#define mmMASTER_COMM_DATA_REG2                                                                        0x00fa
>+#define mmMASTER_COMM_DATA_REG2_BASE_IDX                                                               2
>+#define mmMASTER_COMM_DATA_REG3                                                                        0x00fb
>+#define mmMASTER_COMM_DATA_REG3_BASE_IDX                                                               2
>+#define mmMASTER_COMM_CMD_REG                                                                          0x00fc
>+#define mmMASTER_COMM_CMD_REG_BASE_IDX                                                                 2
>+#define mmMASTER_COMM_CNTL_REG                                                                         0x00fd
>+#define mmMASTER_COMM_CNTL_REG_BASE_IDX                                                                2
>+#define mmSLAVE_COMM_DATA_REG1                                                                         0x00fe
>+#define mmSLAVE_COMM_DATA_REG1_BASE_IDX                                                                2
>+#define mmSLAVE_COMM_DATA_REG2                                                                         0x00ff
>+#define mmSLAVE_COMM_DATA_REG2_BASE_IDX                                                                2
>+#define mmSLAVE_COMM_DATA_REG3                                                                         0x0100
>+#define mmSLAVE_COMM_DATA_REG3_BASE_IDX                                                                2
>+#define mmSLAVE_COMM_CMD_REG                                                                           0x0101
>+#define mmSLAVE_COMM_CMD_REG_BASE_IDX                                                                  2
>+#define mmSLAVE_COMM_CNTL_REG                                                                          0x0102
>+#define mmSLAVE_COMM_CNTL_REG_BASE_IDX                                                                 2
>+#define mmDMCU_PERFMON_INTERRUPT_STATUS1                                                               0x0105
>+#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX                                                      2
>+#define mmDMCU_PERFMON_INTERRUPT_STATUS2                                                               0x0106
>+#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX                                                      2
>+#define mmDMCU_PERFMON_INTERRUPT_STATUS3                                                               0x0107
>+#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX                                                      2
>+#define mmDMCU_PERFMON_INTERRUPT_STATUS4                                                               0x0108
>+#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX                                                      2
>+#define mmDMCU_PERFMON_INTERRUPT_STATUS5                                                               0x0109
>+#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX                                                      2
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                                        0x010a
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                               2
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                                        0x010b
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX                                               2
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                                        0x010c
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX                                               2
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                                        0x010d
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX                                               2
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                                        0x010e
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX                                               2
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                   0x010f
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                          2
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                                                   0x0110
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX                                          2
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                                                   0x0111
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX                                          2
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                                                   0x0112
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX                                          2
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                                                   0x0113
>+#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX                                          2
>+#define mmDMCU_DPRX_INTERRUPT_STATUS1                                                                  0x0114
>+#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX                                                         2
>+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                                           0x0115
>+#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                                  2
>+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                      0x0116
>+#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                             2
>+#define mmDMCU_INTERRUPT_STATUS_CONTINUE                                                               0x0119
>+#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
>+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE                                                        0x011a
>+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX                                               2
>+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE                                                   0x011b
>+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX                                          2
>+#define mmDMCU_INT_CNT_CONTINUE                                                                        0x011c
>+#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX                                                               2
>+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2                                                      0x011d
>+#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX                                             2
>+#define mmDMCU_INTERRUPT_STATUS_2                                                                      0x011e
>+#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX                                                             2
>+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2                                                               0x011f
>+#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_dmu_ihc_dispdec
>+// base address: 0x0
>+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
>+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
>+#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
>+#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
>+#define mmDC_GPU_TIMER_READ                                                                            0x0128
>+#define mmDC_GPU_TIMER_READ_BASE_IDX                                                                   2
>+#define mmDC_GPU_TIMER_READ_CNTL                                                                       0x0129
>+#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
>+#define mmDISP_INTERRUPT_STATUS                                                                        0x012a
>+#define mmDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
>+#define mmDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
>+#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
>+#define mmDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
>+#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
>+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
>+#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
>+#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
>+#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
>+#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
>+#define mmDCCG_INTERRUPT_DEST                                                                          0x0147
>+#define mmDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
>+#define mmDMU_INTERRUPT_DEST                                                                           0x0148
>+#define mmDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
>+#define mmDCPG_INTERRUPT_DEST                                                                          0x0149
>+#define mmDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
>+#define mmDCPG_INTERRUPT_DEST2                                                                         0x014a
>+#define mmDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
>+#define mmMMHUBBUB_INTERRUPT_DEST                                                                      0x014b
>+#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
>+#define mmWB_INTERRUPT_DEST                                                                            0x014c
>+#define mmWB_INTERRUPT_DEST_BASE_IDX                                                                   2
>+#define mmDCHUB_INTERRUPT_DEST                                                                         0x014d
>+#define mmDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
>+#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x014e
>+#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
>+#define mmDCHUB_INTERRUPT_DEST2                                                                        0x014f
>+#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
>+#define mmDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0150
>+#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
>+#define mmMPC_INTERRUPT_DEST                                                                           0x0151
>+#define mmMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
>+#define mmOPP_INTERRUPT_DEST                                                                           0x0152
>+#define mmOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
>+#define mmOPTC_INTERRUPT_DEST                                                                          0x0153
>+#define mmOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
>+#define mmOTG0_INTERRUPT_DEST                                                                          0x0154
>+#define mmOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
>+#define mmOTG1_INTERRUPT_DEST                                                                          0x0155
>+#define mmOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
>+#define mmOTG2_INTERRUPT_DEST                                                                          0x0156
>+#define mmOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
>+#define mmOTG3_INTERRUPT_DEST                                                                          0x0157
>+#define mmOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
>+#define mmOTG4_INTERRUPT_DEST                                                                          0x0158
>+#define mmOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
>+#define mmOTG5_INTERRUPT_DEST                                                                          0x0159
>+#define mmOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
>+#define mmDIG_INTERRUPT_DEST                                                                           0x015a
>+#define mmDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
>+#define mmI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015b
>+#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
>+#define mmDIO_INTERRUPT_DEST                                                                           0x015d
>+#define mmDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
>+#define mmDCIO_INTERRUPT_DEST                                                                          0x015e
>+#define mmDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
>+#define mmHPD_INTERRUPT_DEST                                                                           0x015f
>+#define mmHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
>+#define mmAZ_INTERRUPT_DEST                                                                            0x0160
>+#define mmAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
>+#define mmAUX_INTERRUPT_DEST                                                                           0x0161
>+#define mmAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
>+#define mmDSC_INTERRUPT_DEST                                                                           0x0162
>+#define mmDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
>+
>+
>+// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec
>+// base address: 0x0
>+#define mmWB_ENABLE                                                                                    0x01da
>+#define mmWB_ENABLE_BASE_IDX                                                                           2
>+#define mmWB_EC_CONFIG                                                                                 0x01db
>+#define mmWB_EC_CONFIG_BASE_IDX                                                                        2
>+#define mmCNV_MODE                                                                                     0x01dc
>+#define mmCNV_MODE_BASE_IDX                                                                            2
>+#define mmCNV_WINDOW_START                                                                             0x01dd
>+#define mmCNV_WINDOW_START_BASE_IDX                                                                    2
>+#define mmCNV_WINDOW_SIZE                                                                              0x01de
>+#define mmCNV_WINDOW_SIZE_BASE_IDX                                                                     2
>+#define mmCNV_UPDATE                                                                                   0x01df
>+#define mmCNV_UPDATE_BASE_IDX                                                                          2
>+#define mmCNV_SOURCE_SIZE                                                                              0x01e0
>+#define mmCNV_SOURCE_SIZE_BASE_IDX                                                                     2
>+#define mmCNV_TEST_CNTL                                                                                0x01ee
>+#define mmCNV_TEST_CNTL_BASE_IDX                                                                       2
>+#define mmCNV_TEST_CRC_RED                                                                             0x01ef
>+#define mmCNV_TEST_CRC_RED_BASE_IDX                                                                    2
>+#define mmCNV_TEST_CRC_GREEN                                                                           0x01f0
>+#define mmCNV_TEST_CRC_GREEN_BASE_IDX                                                                  2
>+#define mmCNV_TEST_CRC_BLUE                                                                            0x01f1
>+#define mmCNV_TEST_CRC_BLUE_BASE_IDX                                                                   2
>+#define mmWB_DEBUG_CTRL                                                                                0x01f2
>+#define mmWB_DEBUG_CTRL_BASE_IDX                                                                       2
>+#define mmWB_DBG_MODE                                                                                  0x01f3
>+#define mmWB_DBG_MODE_BASE_IDX                                                                         2
>+#define mmWB_HW_DEBUG                                                                                  0x01f4
>+#define mmWB_HW_DEBUG_BASE_IDX                                                                         2
>+#define mmWB_SOFT_RESET                                                                                0x01f5
>+#define mmWB_SOFT_RESET_BASE_IDX                                                                       2
>+#define mmWB_WARM_UP_MODE_CTL1                                                                         0x01f6
>+#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX                                                                2
>+#define mmWB_WARM_UP_MODE_CTL2                                                                         0x01f7
>+#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX                                                                2
>+#define mmCNV_TEST_DEBUG_INDEX                                                                         0x01f8
>+#define mmCNV_TEST_DEBUG_INDEX_BASE_IDX                                                                2
>+#define mmCNV_TEST_DEBUG_DATA                                                                          0x01f9
>+#define mmCNV_TEST_DEBUG_DATA_BASE_IDX                                                                 2
>+
>+
>+// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec
>+// base address: 0x0
>+#define mmWBSCL_COEF_RAM_SELECT                                                                        0x020a
>+#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX                                                               2
>+#define mmWBSCL_COEF_RAM_TAP_DATA                                                                      0x020b
>+#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX                                                             2
>+#define mmWBSCL_MODE                                                                                   0x020c
>+#define mmWBSCL_MODE_BASE_IDX                                                                          2
>+#define mmWBSCL_TAP_CONTROL                                                                            0x020d
>+#define mmWBSCL_TAP_CONTROL_BASE_IDX                                                                   2
>+#define mmWBSCL_DEST_SIZE                                                                              0x020e
>+#define mmWBSCL_DEST_SIZE_BASE_IDX                                                                     2
>+#define mmWBSCL_HORZ_FILTER_SCALE_RATIO                                                                0x020f
>+#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                       2
>+#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB                                                                 0x0210
>+#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX                                                        2
>+#define mmWBSCL_HORZ_FILTER_INIT_CBCR                                                                  0x0211
>+#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX                                                         2
>+#define mmWBSCL_VERT_FILTER_SCALE_RATIO                                                                0x0212
>+#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                       2
>+#define mmWBSCL_VERT_FILTER_INIT_Y_RGB                                                                 0x0213
>+#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX                                                        2
>+#define mmWBSCL_VERT_FILTER_INIT_CBCR                                                                  0x0214
>+#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX                                                         2
>+#define mmWBSCL_ROUND_OFFSET                                                                           0x0215
>+#define mmWBSCL_ROUND_OFFSET_BASE_IDX                                                                  2
>+#define mmWBSCL_OVERFLOW_STATUS                                                                        0x0216
>+#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX                                                               2
>+#define mmWBSCL_COEF_RAM_CONFLICT_STATUS                                                               0x0217
>+#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX                                                      2
>+#define mmWBSCL_TEST_CNTL                                                                              0x0218
>+#define mmWBSCL_TEST_CNTL_BASE_IDX                                                                     2
>+#define mmWBSCL_TEST_CRC_RED                                                                           0x0219
>+#define mmWBSCL_TEST_CRC_RED_BASE_IDX                                                                  2
>+#define mmWBSCL_TEST_CRC_GREEN                                                                         0x021a
>+#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX                                                                2
>+#define mmWBSCL_TEST_CRC_BLUE                                                                          0x021b
>+#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX                                                                 2
>+#define mmWBSCL_BACKPRESSURE_CNT_EN                                                                    0x021c
>+#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX                                                           2
>+#define mmWB_MCIF_BACKPRESSURE_CNT                                                                     0x021d
>+#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX                                                            2
>+#define mmWBSCL_CLAMP_Y_RGB                                                                            0x021e
>+#define mmWBSCL_CLAMP_Y_RGB_BASE_IDX                                                                   2
>+#define mmWBSCL_CLAMP_CBCR                                                                             0x021f
>+#define mmWBSCL_CLAMP_CBCR_BASE_IDX                                                                    2
>+#define mmWBSCL_OUTSIDE_PIX_STRATEGY                                                                   0x0220
>+#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX                                                          2
>+#define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR                                                              0x0221
>+#define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR_BASE_IDX                                                     2
>+#define mmWBSCL_DEBUG                                                                                  0x0222
>+#define mmWBSCL_DEBUG_BASE_IDX                                                                         2
>+#define mmWBSCL_TEST_DEBUG_INDEX                                                                       0x0223
>+#define mmWBSCL_TEST_DEBUG_INDEX_BASE_IDX                                                              2
>+#define mmWBSCL_TEST_DEBUG_DATA                                                                        0x0224
>+#define mmWBSCL_TEST_DEBUG_DATA_BASE_IDX                                                               2
>+
>+
>+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x8e8
>+#define mmDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x023a
>+#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2
>+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x023b
>+#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
>+#define mmDC_PERFMON3_PERFCOUNTER_STATE                                                                0x023c
>+#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2
>+#define mmDC_PERFMON3_PERFMON_CNTL                                                                     0x023d
>+#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2
>+#define mmDC_PERFMON3_PERFMON_CNTL2                                                                    0x023e
>+#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2
>+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x023f
>+#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
>+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x0240
>+#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
>+#define mmDC_PERFMON3_PERFMON_HI                                                                       0x0241
>+#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2
>+#define mmDC_PERFMON3_PERFMON_LOW                                                                      0x0242
>+#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
>+// base address: 0x0
>+#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02b2
>+#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                  2
>+#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R                                                           0x02b3
>+#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX                                                  2
>+#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS                                                               0x02b4
>+#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX                                                      2
>+#define mmMCIF_WB0_MCIF_WB_BUF_PITCH                                                                   0x02b5
>+#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX                                                          2
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS                                                                0x02b6
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2                                                               0x02b7
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX                                                      2
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS                                                                0x02b8
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2                                                               0x02b9
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX                                                      2
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS                                                                0x02ba
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2                                                               0x02bb
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX                                                      2
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS                                                                0x02bc
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2                                                               0x02bd
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX                                                      2
>+#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL                                                         0x02be
>+#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                2
>+#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE                                                                 0x02bf
>+#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX                                                        2
>+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX                                                            0x02c0
>+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                   2
>+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA                                                             0x02c1
>+#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                    2
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y                                                                0x02c2
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                                         0x02c3
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C                                                                0x02c4
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET                                                         0x02c5
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y                                                                0x02c6
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                                         0x02c7
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C                                                                0x02c8
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET                                                         0x02c9
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y                                                                0x02ca
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                                         0x02cb
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C                                                                0x02cc
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET                                                         0x02cd
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y                                                                0x02ce
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                                         0x02cf
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C                                                                0x02d0
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET                                                         0x02d1
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL                                                          0x02d2
>+#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                 2
>+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                 0x02d3
>+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                        2
>+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL                                                           0x02d4
>+#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
>+#define mmMCIF_WB0_MCIF_WB_WATERMARK                                                                   0x02d5
>+#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX                                                          2
>+#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL                                                         0x02d6
>+#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                2
>+#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL                                                                0x02d7
>+#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL                                                        0x02d8
>+#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
>+#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL                                                                0x02d9
>+#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX                                                       2
>+#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL                                                              0x02da
>+#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL_BASE_IDX                                                     2
>+#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE                                                               0x02db
>+#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                      2
>+#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE                                                             0x02dc
>+#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                    2
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH                                                           0x02dd
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH                                                           0x02de
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH                                                           0x02df
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH                                                           0x02e0
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH                                                           0x02e1
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH                                                           0x02e2
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH                                                           0x02e3
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH                                                           0x02e4
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION                                                            0x02e5
>+#define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                   2
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION                                                            0x02e6
>+#define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                   2
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION                                                            0x02e7
>+#define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                   2
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION                                                            0x02e8
>+#define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                   2
>+
>+
>+// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec
>+// base address: 0x100
>+#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x02f2
>+#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                  2
>+#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R                                                           0x02f3
>+#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX                                                  2
>+#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS                                                               0x02f4
>+#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX                                                      2
>+#define mmMCIF_WB1_MCIF_WB_BUF_PITCH                                                                   0x02f5
>+#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX                                                          2
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS                                                                0x02f6
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2                                                               0x02f7
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX                                                      2
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS                                                                0x02f8
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2                                                               0x02f9
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX                                                      2
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS                                                                0x02fa
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2                                                               0x02fb
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX                                                      2
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS                                                                0x02fc
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2                                                               0x02fd
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX                                                      2
>+#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL                                                         0x02fe
>+#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                2
>+#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE                                                                 0x02ff
>+#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX                                                        2
>+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX                                                            0x0300
>+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                   2
>+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA                                                             0x0301
>+#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                    2
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y                                                                0x0302
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                                         0x0303
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C                                                                0x0304
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET                                                         0x0305
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y                                                                0x0306
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                                         0x0307
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C                                                                0x0308
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET                                                         0x0309
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y                                                                0x030a
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                                         0x030b
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C                                                                0x030c
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET                                                         0x030d
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y                                                                0x030e
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                                         0x030f
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C                                                                0x0310
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET                                                         0x0311
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL                                                          0x0312
>+#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                 2
>+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                 0x0313
>+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                        2
>+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL                                                           0x0314
>+#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
>+#define mmMCIF_WB1_MCIF_WB_WATERMARK                                                                   0x0315
>+#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX                                                          2
>+#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL                                                         0x0316
>+#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                2
>+#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL                                                                0x0317
>+#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL                                                        0x0318
>+#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
>+#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL                                                                0x0319
>+#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX                                                       2
>+#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE                                                               0x031b
>+#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                      2
>+#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE                                                             0x031c
>+#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                    2
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH                                                           0x031d
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH                                                           0x031e
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH                                                           0x031f
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH                                                           0x0320
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH                                                           0x0321
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH                                                           0x0322
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH                                                           0x0323
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH                                                           0x0324
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION                                                            0x0325
>+#define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                   2
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION                                                            0x0326
>+#define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                   2
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION                                                            0x0327
>+#define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                   2
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION                                                            0x0328
>+#define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                   2
>+
>+
>+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
>+// base address: 0x0
>+#define mmWBIF0_MISC_CTRL                                                                              0x0333
>+#define mmWBIF0_MISC_CTRL_BASE_IDX                                                                     2
>+#define mmWBIF0_SMU_WM_CONTROL                                                                         0x0334
>+#define mmWBIF0_SMU_WM_CONTROL_BASE_IDX                                                                2
>+#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0335
>+#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
>+#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0336
>+#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
>+#define mmVGA_SRC_SPLIT_CNTL                                                                           0x033f
>+#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
>+#define mmMMHUBBUB_MEM_PWR_STATUS                                                                      0x0340
>+#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
>+#define mmMMHUBBUB_MEM_PWR_CNTL                                                                        0x0341
>+#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
>+#define mmMMHUBBUB_CLOCK_CNTL                                                                          0x0342
>+#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
>+#define mmMMHUBBUB_SOFT_RESET                                                                          0x0343
>+#define mmMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
>+#define mmDMU_IF_ERR_STATUS                                                                            0x0347
>+#define mmDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
>+#define mmMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0348
>+#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
>+// base address: 0x0
>+#define mmMCIF_CONTROL                                                                                 0x034a
>+#define mmMCIF_CONTROL_BASE_IDX                                                                        2
>+#define mmMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
>+#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
>+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
>+#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
>+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
>+#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
>+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
>+#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
>+// base address: 0xd48
>+#define mmDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x0352
>+#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2
>+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x0353
>+#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
>+#define mmDC_PERFMON4_PERFCOUNTER_STATE                                                                0x0354
>+#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2
>+#define mmDC_PERFMON4_PERFMON_CNTL                                                                     0x0355
>+#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2
>+#define mmDC_PERFMON4_PERFMON_CNTL2                                                                    0x0356
>+#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2
>+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x0357
>+#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
>+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0358
>+#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
>+#define mmDC_PERFMON4_PERFMON_HI                                                                       0x0359
>+#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2
>+#define mmDC_PERFMON4_PERFMON_LOW                                                                      0x035a
>+#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream0_dispdec
>+// base address: 0x0
>+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
>+#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
>+#define mmAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
>+#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream1_dispdec
>+// base address: 0x8
>+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
>+#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
>+#define mmAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
>+#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream2_dispdec
>+// base address: 0x10
>+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
>+#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
>+#define mmAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
>+#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream3_dispdec
>+// base address: 0x18
>+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
>+#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
>+#define mmAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
>+#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream4_dispdec
>+// base address: 0x20
>+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
>+#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
>+#define mmAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
>+#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream5_dispdec
>+// base address: 0x28
>+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
>+#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
>+#define mmAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
>+#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream6_dispdec
>+// base address: 0x30
>+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
>+#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
>+#define mmAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
>+#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream7_dispdec
>+// base address: 0x38
>+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
>+#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
>+#define mmAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
>+#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_hda_az_misc_dispdec
>+// base address: 0x0
>+#define mmAZ_CLOCK_CNTL                                                                                0x0372
>+#define mmAZ_CLOCK_CNTL_BASE_IDX                                                                       2
>+
>+
>+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
>+// base address: 0xde8
>+#define mmDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x037a
>+#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2
>+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x037b
>+#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
>+#define mmDC_PERFMON5_PERFCOUNTER_STATE                                                                0x037c
>+#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2
>+#define mmDC_PERFMON5_PERFMON_CNTL                                                                     0x037d
>+#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2
>+#define mmDC_PERFMON5_PERFMON_CNTL2                                                                    0x037e
>+#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2
>+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x037f
>+#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
>+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x0380
>+#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
>+#define mmDC_PERFMON5_PERFMON_HI                                                                       0x0381
>+#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2
>+#define mmDC_PERFMON5_PERFMON_LOW                                                                      0x0382
>+#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
>+// base address: 0x0
>+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
>+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
>+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
>+#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
>+// base address: 0x18
>+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
>+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
>+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
>+#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
>+// base address: 0x30
>+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
>+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
>+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
>+#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
>+// base address: 0x48
>+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
>+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
>+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
>+#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
>+// base address: 0x60
>+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
>+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
>+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
>+#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
>+// base address: 0x78
>+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
>+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
>+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
>+#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
>+// base address: 0x90
>+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
>+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
>+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
>+#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
>+// base address: 0xa8
>+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
>+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
>+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
>+#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
>+
>+
>+// addressBlock: dce_dc_hda_azf0controller_dispdec
>+// base address: 0x0
>+#define mmAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
>+#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
>+#define mmAZALIA_AUDIO_DTO                                                                             0x03c3
>+#define mmAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
>+#define mmAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
>+#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
>+#define mmAZALIA_SOCCLK_CONTROL                                                                        0x03c5
>+#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
>+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
>+#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
>+#define mmAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
>+#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
>+#define mmAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
>+#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
>+#define mmAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
>+#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
>+#define mmAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
>+#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
>+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
>+#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
>+#define mmAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
>+#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
>+#define mmAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
>+#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
>+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
>+#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
>+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
>+#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
>+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
>+#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
>+#define mmAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
>+#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
>+#define mmAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
>+#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
>+#define mmAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
>+#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
>+#define mmAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
>+#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
>+#define mmAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
>+#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
>+#define mmAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
>+#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
>+#define mmAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
>+#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
>+#define mmAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
>+#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
>+#define mmAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
>+#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
>+#define mmAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
>+#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
>+#define mmAZALIA_CRC0_CONTROL0                                                                         0x03e3
>+#define mmAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
>+#define mmAZALIA_CRC0_CONTROL1                                                                         0x03e4
>+#define mmAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
>+#define mmAZALIA_CRC0_CONTROL2                                                                         0x03e5
>+#define mmAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
>+#define mmAZALIA_CRC0_CONTROL3                                                                         0x03e6
>+#define mmAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
>+#define mmAZALIA_CRC0_RESULT                                                                           0x03e7
>+#define mmAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
>+#define mmAZALIA_CRC1_CONTROL0                                                                         0x03e8
>+#define mmAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
>+#define mmAZALIA_CRC1_CONTROL1                                                                         0x03e9
>+#define mmAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
>+#define mmAZALIA_CRC1_CONTROL2                                                                         0x03ea
>+#define mmAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
>+#define mmAZALIA_CRC1_CONTROL3                                                                         0x03eb
>+#define mmAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
>+#define mmAZALIA_CRC1_RESULT                                                                           0x03ec
>+#define mmAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
>+#define mmAZALIA_MEM_PWR_CTRL                                                                          0x03ee
>+#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
>+#define mmAZALIA_MEM_PWR_STATUS                                                                        0x03ef
>+#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
>+
>+
>+// addressBlock: dce_dc_hda_azf0root_dispdec
>+// base address: 0x0
>+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
>+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
>+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
>+#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
>+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
>+#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
>+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
>+#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
>+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
>+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
>+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
>+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
>+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
>+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
>+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
>+#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
>+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
>+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
>+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
>+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
>+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
>+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
>+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
>+#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
>+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
>+#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
>+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
>+#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
>+#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
>+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
>+#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
>+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
>+#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream8_dispdec
>+// base address: 0x320
>+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
>+#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
>+#define mmAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
>+#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream9_dispdec
>+// base address: 0x328
>+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
>+#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
>+#define mmAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
>+#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream10_dispdec
>+// base address: 0x330
>+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
>+#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
>+#define mmAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
>+#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream11_dispdec
>+// base address: 0x338
>+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
>+#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
>+#define mmAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
>+#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream12_dispdec
>+// base address: 0x340
>+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
>+#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
>+#define mmAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
>+#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream13_dispdec
>+// base address: 0x348
>+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
>+#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
>+#define mmAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
>+#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream14_dispdec
>+// base address: 0x350
>+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
>+#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
>+#define mmAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
>+#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream15_dispdec
>+// base address: 0x358
>+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
>+#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
>+#define mmAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
>+#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
>+// base address: 0x0
>+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
>+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
>+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
>+#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
>+// base address: 0x10
>+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
>+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
>+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
>+#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
>+// base address: 0x20
>+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
>+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
>+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
>+#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
>+// base address: 0x30
>+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
>+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
>+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
>+#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
>+// base address: 0x40
>+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
>+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
>+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
>+#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
>+// base address: 0x50
>+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
>+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
>+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
>+#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
>+// base address: 0x60
>+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
>+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
>+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
>+#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
>+// base address: 0x70
>+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
>+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
>+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
>+#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
>+
>+
>+// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
>+// base address: 0x0
>+#define mmDCHUBBUB_SDPIF_CFG0                                                                          0x048f
>+#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
>+#define mmVM_REQUEST_PHYSICAL                                                                          0x0490
>+#define mmVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
>+#define mmDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0491
>+#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
>+#define mmDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0492
>+#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
>+#define mmDCN_VM_FB_LOCATION_BASE                                                                      0x0493
>+#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
>+#define mmDCN_VM_FB_LOCATION_TOP                                                                       0x0494
>+#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
>+#define mmDCN_VM_FB_OFFSET                                                                             0x0495
>+#define mmDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
>+#define mmDCN_VM_AGP_BOT                                                                               0x0496
>+#define mmDCN_VM_AGP_BOT_BASE_IDX                                                                      2
>+#define mmDCN_VM_AGP_TOP                                                                               0x0497
>+#define mmDCN_VM_AGP_TOP_BASE_IDX                                                                      2
>+#define mmDCN_VM_AGP_BASE                                                                              0x0498
>+#define mmDCN_VM_AGP_BASE_BASE_IDX                                                                     2
>+#define mmDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x0499
>+#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
>+#define mmDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x049a
>+#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
>+#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x049b
>+#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
>+#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL                                                                  0x04b8
>+#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX                                                         2
>+#define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL                                                           0x04b9
>+#define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX                                                  2
>+#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x04ba
>+#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
>+#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x04bb
>+#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
>+#define mmDCHUBBUB_SDPIF_CFG1                                                                          0x04bf
>+#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
>+#define mmDCHUBBUB_SDPIF_CFG2                                                                          0x04c0
>+#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
>+
>+
>+// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
>+// base address: 0x0
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG                                                                    0x04cf
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX                                                           2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0                                                                 0x04d0
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1                                                                 0x04d1
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0                                                                 0x04d2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1                                                                 0x04d3
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0                                                                 0x04d4
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1                                                                 0x04d5
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0                                                                 0x04d6
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1                                                                 0x04d7
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0                                                                 0x04d8
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1                                                                 0x04d9
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0                                                                 0x04da
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1                                                                 0x04db
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0                                                                 0x04dc
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1                                                                 0x04dd
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0                                                                 0x04de
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1                                                                 0x04df
>+#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX                                                        2
>+#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04ef
>+#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
>+#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04f0
>+#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
>+#define mmDCHUBBUB_CRC_CTRL                                                                            0x04f1
>+#define mmDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
>+#define mmDCHUBBUB_CRC0_VAL_R_G                                                                        0x04f2
>+#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
>+#define mmDCHUBBUB_CRC0_VAL_B_A                                                                        0x04f3
>+#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
>+#define mmDCHUBBUB_CRC1_VAL_R_G                                                                        0x04f4
>+#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
>+#define mmDCHUBBUB_CRC1_VAL_B_A                                                                        0x04f5
>+#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
>+
>+
>+// addressBlock: dce_dc_dchubbub_hubbub_dispdec
>+// base address: 0x0
>+#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x0505
>+#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
>+#define mmDCHUBBUB_ARB_SAT_LEVEL                                                                       0x0506
>+#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
>+#define mmDCHUBBUB_ARB_QOS_FORCE                                                                       0x0507
>+#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
>+#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x0508
>+#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
>+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x0509
>+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
>+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x050a
>+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
>+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x050b
>+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
>+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x050c
>+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
>+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A                                               0x050d
>+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX                                      2
>+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x050e
>+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
>+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x050f
>+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
>+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x0510
>+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
>+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x0511
>+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
>+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B                                               0x0512
>+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX                                      2
>+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x0513
>+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
>+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0514
>+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
>+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0515
>+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
>+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0516
>+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
>+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C                                               0x0517
>+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX                                      2
>+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0518
>+#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
>+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x0519
>+#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
>+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051a
>+#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
>+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051b
>+#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
>+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D                                               0x051c
>+#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX                                      2
>+#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x051d
>+#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
>+#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x051e
>+#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
>+#define mmDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x051f
>+#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
>+#define mmSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0520
>+#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
>+#define mmSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0521
>+#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
>+#define mmSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0522
>+#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
>+#define mmSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0523
>+#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
>+#define mmSURFACE_CHECK2_ADDRESS_LSB                                                                   0x0524
>+#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
>+#define mmSURFACE_CHECK2_ADDRESS_MSB                                                                   0x0525
>+#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
>+#define mmSURFACE_CHECK3_ADDRESS_LSB                                                                   0x0526
>+#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
>+#define mmSURFACE_CHECK3_ADDRESS_MSB                                                                   0x0527
>+#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
>+#define mmVTG0_CONTROL                                                                                 0x0528
>+#define mmVTG0_CONTROL_BASE_IDX                                                                        2
>+#define mmVTG1_CONTROL                                                                                 0x0529
>+#define mmVTG1_CONTROL_BASE_IDX                                                                        2
>+#define mmVTG2_CONTROL                                                                                 0x052a
>+#define mmVTG2_CONTROL_BASE_IDX                                                                        2
>+#define mmVTG3_CONTROL                                                                                 0x052b
>+#define mmVTG3_CONTROL_BASE_IDX                                                                        2
>+#define mmDCHUBBUB_SOFT_RESET                                                                          0x052e
>+#define mmDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
>+#define mmDCHUBBUB_CLOCK_CNTL                                                                          0x052f
>+#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
>+#define mmDCFCLK_CNTL                                                                                  0x0530
>+#define mmDCFCLK_CNTL_BASE_IDX                                                                         2
>+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0531
>+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
>+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0532
>+#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
>+#define mmDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0533
>+#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
>+#define mmDCHUBBUB_CTRL_STATUS                                                                         0x0534
>+#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
>+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053a
>+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
>+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053b
>+#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
>+#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x053c
>+#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
>+#define mmDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x053d
>+#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2
>+#define mmDCHUBBUB_TEST_DEBUG_DATA                                                                     0x053e
>+#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x053f
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0540
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x0541
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x0542
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0543
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0544
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x0545
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0546
>+#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
>+#define mmDCHUBBUB_ARB_HOSTVM_CNTL                                                                     0x0547
>+#define mmDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX                                                            2
>+#define mmFMON_CTRL                                                                                    0x0548
>+#define mmFMON_CTRL_BASE_IDX                                                                           2
>+
>+
>+// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x1534
>+#define mmDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x054d
>+#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2
>+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x054e
>+#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
>+#define mmDC_PERFMON6_PERFCOUNTER_STATE                                                                0x054f
>+#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2
>+#define mmDC_PERFMON6_PERFMON_CNTL                                                                     0x0550
>+#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2
>+#define mmDC_PERFMON6_PERFMON_CNTL2                                                                    0x0551
>+#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2
>+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x0552
>+#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
>+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x0553
>+#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
>+#define mmDC_PERFMON6_PERFMON_HI                                                                       0x0554
>+#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2
>+#define mmDC_PERFMON6_PERFMON_LOW                                                                      0x0555
>+#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
>+// base address: 0x0
>+#define mmDCN_VM_CONTEXT0_CNTL                                                                         0x0559
>+#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
>+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
>+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
>+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
>+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
>+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
>+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
>+#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT1_CNTL                                                                         0x0560
>+#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
>+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
>+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
>+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
>+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
>+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
>+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
>+#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT2_CNTL                                                                         0x0567
>+#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
>+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
>+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
>+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
>+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
>+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
>+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
>+#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT3_CNTL                                                                         0x056e
>+#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
>+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
>+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
>+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
>+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
>+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
>+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
>+#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT4_CNTL                                                                         0x0575
>+#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
>+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
>+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
>+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
>+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
>+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
>+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
>+#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT5_CNTL                                                                         0x057c
>+#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
>+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
>+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
>+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
>+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
>+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
>+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
>+#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT6_CNTL                                                                         0x0583
>+#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
>+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
>+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
>+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
>+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
>+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
>+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
>+#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT7_CNTL                                                                         0x058a
>+#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
>+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
>+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
>+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
>+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
>+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
>+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
>+#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT8_CNTL                                                                         0x0591
>+#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
>+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
>+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
>+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
>+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
>+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
>+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
>+#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT9_CNTL                                                                         0x0598
>+#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
>+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
>+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
>+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
>+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
>+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
>+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
>+#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
>+#define mmDCN_VM_CONTEXT10_CNTL                                                                        0x059f
>+#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
>+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
>+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
>+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
>+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
>+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
>+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
>+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
>+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
>+#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
>+#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
>+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
>+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
>+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
>+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
>+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
>+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
>+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
>+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
>+#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
>+#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
>+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
>+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
>+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
>+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
>+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
>+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
>+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
>+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
>+#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
>+#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
>+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
>+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
>+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
>+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
>+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
>+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
>+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
>+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
>+#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
>+#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
>+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
>+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
>+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
>+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
>+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
>+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
>+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
>+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
>+#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
>+#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
>+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
>+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
>+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
>+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
>+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
>+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
>+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
>+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
>+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
>+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
>+#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
>+#define mmDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
>+#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
>+#define mmDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
>+#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
>+#define mmDCN_VM_FAULT_CNTL                                                                            0x05cb
>+#define mmDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
>+#define mmDCN_VM_FAULT_STATUS                                                                          0x05cc
>+#define mmDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
>+#define mmDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
>+#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
>+#define mmDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
>+#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
>+
>+
>+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
>+// base address: 0x0
>+#define mmHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
>+#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
>+#define mmHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
>+#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
>+#define mmHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
>+#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
>+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
>+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
>+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
>+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
>+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
>+#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
>+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
>+#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
>+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
>+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
>+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
>+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
>+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
>+#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
>+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
>+#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
>+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
>+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
>+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
>+#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
>+#define mmHUBP0_DCHUBP_CNTL                                                                            0x05f3
>+#define mmHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
>+#define mmHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
>+#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
>+#define mmHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
>+#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
>+#define mmHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f6
>+#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
>+#define mmHUBP0_HUBPREQ_DEBUG                                                                          0x05f7
>+#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
>+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fb
>+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
>+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fc
>+#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
>+
>+
>+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
>+// base address: 0x0
>+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
>+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
>+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
>+#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
>+#define mmHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
>+#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
>+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
>+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
>+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
>+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
>+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
>+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
>+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
>+#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
>+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
>+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
>+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
>+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
>+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
>+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
>+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
>+#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
>+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
>+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
>+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
>+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
>+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
>+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
>+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
>+#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
>+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
>+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
>+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
>+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
>+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
>+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
>+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
>+#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
>+#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
>+#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
>+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
>+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
>+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
>+#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
>+#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x0620
>+#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
>+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0621
>+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
>+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0622
>+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
>+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0623
>+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
>+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0624
>+#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
>+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0625
>+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
>+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0626
>+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
>+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0627
>+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
>+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0628
>+#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
>+#define mmHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x062c
>+#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
>+#define mmHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x062d
>+#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
>+#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062e
>+#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
>+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062f
>+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
>+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x0630
>+#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
>+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x0631
>+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
>+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x0632
>+#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
>+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x0633
>+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
>+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0634
>+#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
>+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0635
>+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
>+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0636
>+#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
>+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0637
>+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
>+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0638
>+#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
>+#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0645
>+#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
>+#define mmHUBPREQ0_BLANK_OFFSET_0                                                                      0x0646
>+#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
>+#define mmHUBPREQ0_BLANK_OFFSET_1                                                                      0x0647
>+#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
>+#define mmHUBPREQ0_DST_DIMENSIONS                                                                      0x0648
>+#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
>+#define mmHUBPREQ0_DST_AFTER_SCALER                                                                    0x0649
>+#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
>+#define mmHUBPREQ0_PREFETCH_SETTINGS                                                                   0x064a
>+#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
>+#define mmHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x064b
>+#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x064c
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064d
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064e
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064f
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x0650
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
>+#define mmHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x0651
>+#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
>+#define mmHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x0652
>+#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
>+#define mmHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0653
>+#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
>+#define mmHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0654
>+#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
>+#define mmHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0655
>+#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
>+#define mmHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0656
>+#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
>+#define mmHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0657
>+#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
>+#define mmHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0658
>+#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
>+#define mmHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0659
>+#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
>+#define mmHUBPREQ0_NOM_PARAMETERS_6                                                                    0x065a
>+#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
>+#define mmHUBPREQ0_NOM_PARAMETERS_7                                                                    0x065b
>+#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
>+#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x065c
>+#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
>+#define mmHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065d
>+#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
>+#define mmHUBPREQ0_CURSOR_SETTINGS                                                                     0x065e
>+#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
>+#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065f
>+#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
>+#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x0660
>+#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
>+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x0661
>+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
>+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x0662
>+#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0665
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0666
>+#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
>+#define mmHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0667
>+#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
>+#define mmHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0668
>+#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
>+#define mmHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0669
>+#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
>+#define mmHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x066a
>+#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
>+// base address: 0x0
>+#define mmHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
>+#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
>+#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
>+#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
>+#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
>+#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
>+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
>+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
>+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
>+#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
>+#define mmHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
>+#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
>+#define mmHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
>+#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
>+#define mmHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
>+#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
>+#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
>+#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
>+#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
>+#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
>+
>+
>+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
>+// base address: 0x0
>+#define mmCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
>+#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
>+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
>+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
>+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
>+#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
>+#define mmCURSOR0_0_CURSOR_SIZE                                                                        0x067b
>+#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
>+#define mmCURSOR0_0_CURSOR_POSITION                                                                    0x067c
>+#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
>+#define mmCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
>+#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
>+#define mmCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
>+#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
>+#define mmCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
>+#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
>+#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
>+#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
>+#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
>+#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
>+#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
>+#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
>+#define mmCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
>+#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
>+#define mmCURSOR0_0_DMDATA_CNTL                                                                        0x0684
>+#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
>+#define mmCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
>+#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
>+#define mmCURSOR0_0_DMDATA_STATUS                                                                      0x0686
>+#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
>+#define mmCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
>+#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
>+#define mmCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
>+#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x1a74
>+#define mmDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x069d
>+#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2
>+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x069e
>+#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
>+#define mmDC_PERFMON7_PERFCOUNTER_STATE                                                                0x069f
>+#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2
>+#define mmDC_PERFMON7_PERFMON_CNTL                                                                     0x06a0
>+#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2
>+#define mmDC_PERFMON7_PERFMON_CNTL2                                                                    0x06a1
>+#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2
>+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x06a2
>+#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
>+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x06a3
>+#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
>+#define mmDC_PERFMON7_PERFMON_HI                                                                       0x06a4
>+#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2
>+#define mmDC_PERFMON7_PERFMON_LOW                                                                      0x06a5
>+#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
>+// base address: 0x370
>+#define mmHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
>+#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
>+#define mmHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
>+#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
>+#define mmHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
>+#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
>+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
>+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
>+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
>+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
>+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
>+#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
>+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
>+#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
>+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
>+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
>+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
>+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
>+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
>+#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
>+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
>+#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
>+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
>+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
>+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
>+#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
>+#define mmHUBP1_DCHUBP_CNTL                                                                            0x06cf
>+#define mmHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
>+#define mmHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
>+#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
>+#define mmHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
>+#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
>+#define mmHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d2
>+#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
>+#define mmHUBP1_HUBPREQ_DEBUG                                                                          0x06d3
>+#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
>+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d7
>+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
>+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06d8
>+#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
>+
>+
>+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
>+// base address: 0x370
>+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
>+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
>+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
>+#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
>+#define mmHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
>+#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
>+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
>+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
>+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
>+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
>+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
>+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
>+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
>+#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
>+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
>+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
>+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
>+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
>+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
>+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
>+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
>+#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
>+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
>+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
>+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
>+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
>+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
>+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
>+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
>+#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
>+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
>+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
>+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
>+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
>+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
>+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
>+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
>+#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
>+#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
>+#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
>+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
>+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
>+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
>+#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
>+#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fc
>+#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
>+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fd
>+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
>+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fe
>+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
>+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06ff
>+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
>+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0700
>+#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
>+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0701
>+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
>+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0702
>+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
>+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0703
>+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
>+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0704
>+#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
>+#define mmHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0708
>+#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
>+#define mmHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0709
>+#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
>+#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x070a
>+#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
>+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x070b
>+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
>+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x070c
>+#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
>+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x070d
>+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
>+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070e
>+#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
>+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070f
>+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
>+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x0710
>+#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
>+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x0711
>+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
>+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x0712
>+#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
>+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0713
>+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
>+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0714
>+#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
>+#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x0721
>+#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
>+#define mmHUBPREQ1_BLANK_OFFSET_0                                                                      0x0722
>+#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
>+#define mmHUBPREQ1_BLANK_OFFSET_1                                                                      0x0723
>+#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
>+#define mmHUBPREQ1_DST_DIMENSIONS                                                                      0x0724
>+#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
>+#define mmHUBPREQ1_DST_AFTER_SCALER                                                                    0x0725
>+#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
>+#define mmHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0726
>+#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
>+#define mmHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0727
>+#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0728
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0729
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x072a
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x072b
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x072c
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
>+#define mmHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072d
>+#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
>+#define mmHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072e
>+#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
>+#define mmHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072f
>+#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
>+#define mmHUBPREQ1_NOM_PARAMETERS_0                                                                    0x0730
>+#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
>+#define mmHUBPREQ1_NOM_PARAMETERS_1                                                                    0x0731
>+#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
>+#define mmHUBPREQ1_NOM_PARAMETERS_2                                                                    0x0732
>+#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
>+#define mmHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0733
>+#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
>+#define mmHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0734
>+#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
>+#define mmHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0735
>+#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
>+#define mmHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0736
>+#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
>+#define mmHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0737
>+#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
>+#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0738
>+#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
>+#define mmHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0739
>+#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
>+#define mmHUBPREQ1_CURSOR_SETTINGS                                                                     0x073a
>+#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
>+#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x073b
>+#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
>+#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x073c
>+#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
>+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073d
>+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
>+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073e
>+#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x0741
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x0742
>+#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
>+#define mmHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0743
>+#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
>+#define mmHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0744
>+#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
>+#define mmHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0745
>+#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
>+#define mmHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0746
>+#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
>+// base address: 0x370
>+#define mmHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
>+#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
>+#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
>+#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
>+#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
>+#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
>+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
>+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
>+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
>+#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
>+#define mmHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
>+#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
>+#define mmHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
>+#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
>+#define mmHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
>+#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
>+#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
>+#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
>+#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
>+#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
>+
>+
>+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
>+// base address: 0x370
>+#define mmCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
>+#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
>+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
>+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
>+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
>+#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
>+#define mmCURSOR0_1_CURSOR_SIZE                                                                        0x0757
>+#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
>+#define mmCURSOR0_1_CURSOR_POSITION                                                                    0x0758
>+#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
>+#define mmCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
>+#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
>+#define mmCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
>+#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
>+#define mmCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
>+#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
>+#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
>+#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
>+#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
>+#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
>+#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
>+#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
>+#define mmCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
>+#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
>+#define mmCURSOR0_1_DMDATA_CNTL                                                                        0x0760
>+#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
>+#define mmCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
>+#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
>+#define mmCURSOR0_1_DMDATA_STATUS                                                                      0x0762
>+#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
>+#define mmCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
>+#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
>+#define mmCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
>+#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x1de4
>+#define mmDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x0779
>+#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2
>+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x077a
>+#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
>+#define mmDC_PERFMON8_PERFCOUNTER_STATE                                                                0x077b
>+#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2
>+#define mmDC_PERFMON8_PERFMON_CNTL                                                                     0x077c
>+#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2
>+#define mmDC_PERFMON8_PERFMON_CNTL2                                                                    0x077d
>+#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2
>+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x077e
>+#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
>+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x077f
>+#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
>+#define mmDC_PERFMON8_PERFMON_HI                                                                       0x0780
>+#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2
>+#define mmDC_PERFMON8_PERFMON_LOW                                                                      0x0781
>+#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
>+// base address: 0x6e0
>+#define mmHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
>+#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
>+#define mmHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
>+#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
>+#define mmHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
>+#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
>+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
>+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
>+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
>+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
>+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
>+#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
>+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
>+#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
>+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
>+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
>+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
>+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
>+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
>+#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
>+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
>+#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
>+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
>+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
>+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
>+#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
>+#define mmHUBP2_DCHUBP_CNTL                                                                            0x07ab
>+#define mmHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
>+#define mmHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
>+#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
>+#define mmHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
>+#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
>+#define mmHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07ae
>+#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
>+#define mmHUBP2_HUBPREQ_DEBUG                                                                          0x07af
>+#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
>+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b3
>+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
>+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b4
>+#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
>+
>+
>+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
>+// base address: 0x6e0
>+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
>+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
>+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
>+#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
>+#define mmHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
>+#define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
>+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
>+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
>+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
>+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
>+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
>+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
>+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
>+#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
>+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
>+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
>+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
>+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
>+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
>+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
>+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
>+#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
>+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
>+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
>+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
>+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
>+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
>+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
>+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
>+#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
>+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
>+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
>+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
>+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
>+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
>+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
>+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
>+#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
>+#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
>+#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
>+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
>+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
>+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
>+#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
>+#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d8
>+#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
>+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d9
>+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
>+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07da
>+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
>+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07db
>+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
>+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07dc
>+#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
>+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dd
>+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
>+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07de
>+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
>+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07df
>+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
>+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07e0
>+#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
>+#define mmHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e4
>+#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
>+#define mmHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e5
>+#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
>+#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e6
>+#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
>+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e7
>+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
>+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e8
>+#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
>+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e9
>+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
>+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07ea
>+#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
>+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07eb
>+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
>+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07ec
>+#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
>+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07ed
>+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
>+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07ee
>+#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
>+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ef
>+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
>+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07f0
>+#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
>+#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fd
>+#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
>+#define mmHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fe
>+#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
>+#define mmHUBPREQ2_BLANK_OFFSET_1                                                                      0x07ff
>+#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
>+#define mmHUBPREQ2_DST_DIMENSIONS                                                                      0x0800
>+#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
>+#define mmHUBPREQ2_DST_AFTER_SCALER                                                                    0x0801
>+#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
>+#define mmHUBPREQ2_PREFETCH_SETTINGS                                                                   0x0802
>+#define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
>+#define mmHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0803
>+#define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0804
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0805
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0806
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0807
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0808
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
>+#define mmHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0809
>+#define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
>+#define mmHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x080a
>+#define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
>+#define mmHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x080b
>+#define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
>+#define mmHUBPREQ2_NOM_PARAMETERS_0                                                                    0x080c
>+#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
>+#define mmHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080d
>+#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
>+#define mmHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080e
>+#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
>+#define mmHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080f
>+#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
>+#define mmHUBPREQ2_NOM_PARAMETERS_4                                                                    0x0810
>+#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
>+#define mmHUBPREQ2_NOM_PARAMETERS_5                                                                    0x0811
>+#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
>+#define mmHUBPREQ2_NOM_PARAMETERS_6                                                                    0x0812
>+#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
>+#define mmHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0813
>+#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
>+#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0814
>+#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
>+#define mmHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0815
>+#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
>+#define mmHUBPREQ2_CURSOR_SETTINGS                                                                     0x0816
>+#define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
>+#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0817
>+#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
>+#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0818
>+#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
>+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0819
>+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
>+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x081a
>+#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081d
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081e
>+#define mmHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
>+#define mmHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081f
>+#define mmHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
>+#define mmHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x0820
>+#define mmHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
>+#define mmHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x0821
>+#define mmHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
>+#define mmHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x0822
>+#define mmHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
>+// base address: 0x6e0
>+#define mmHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
>+#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
>+#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
>+#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
>+#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
>+#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
>+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
>+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
>+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
>+#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
>+#define mmHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
>+#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
>+#define mmHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
>+#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
>+#define mmHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
>+#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
>+#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
>+#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
>+#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
>+#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
>+
>+
>+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
>+// base address: 0x6e0
>+#define mmCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
>+#define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
>+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
>+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
>+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
>+#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
>+#define mmCURSOR0_2_CURSOR_SIZE                                                                        0x0833
>+#define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
>+#define mmCURSOR0_2_CURSOR_POSITION                                                                    0x0834
>+#define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
>+#define mmCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
>+#define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
>+#define mmCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
>+#define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
>+#define mmCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
>+#define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
>+#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
>+#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
>+#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
>+#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
>+#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
>+#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
>+#define mmCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
>+#define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
>+#define mmCURSOR0_2_DMDATA_CNTL                                                                        0x083c
>+#define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
>+#define mmCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
>+#define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
>+#define mmCURSOR0_2_DMDATA_STATUS                                                                      0x083e
>+#define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
>+#define mmCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
>+#define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
>+#define mmCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
>+#define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x2154
>+#define mmDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x0855
>+#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2
>+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x0856
>+#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
>+#define mmDC_PERFMON9_PERFCOUNTER_STATE                                                                0x0857
>+#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2
>+#define mmDC_PERFMON9_PERFMON_CNTL                                                                     0x0858
>+#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2
>+#define mmDC_PERFMON9_PERFMON_CNTL2                                                                    0x0859
>+#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2
>+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x085a
>+#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
>+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x085b
>+#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
>+#define mmDC_PERFMON9_PERFMON_HI                                                                       0x085c
>+#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2
>+#define mmDC_PERFMON9_PERFMON_LOW                                                                      0x085d
>+#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
>+// base address: 0xa50
>+#define mmHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
>+#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
>+#define mmHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
>+#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
>+#define mmHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
>+#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
>+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
>+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
>+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
>+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
>+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
>+#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
>+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
>+#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
>+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
>+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
>+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
>+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
>+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
>+#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
>+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
>+#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
>+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
>+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
>+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
>+#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
>+#define mmHUBP3_DCHUBP_CNTL                                                                            0x0887
>+#define mmHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
>+#define mmHUBP3_HUBP_CLK_CNTL                                                                          0x0888
>+#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
>+#define mmHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
>+#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
>+#define mmHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088a
>+#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
>+#define mmHUBP3_HUBPREQ_DEBUG                                                                          0x088b
>+#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
>+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x088f
>+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
>+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0890
>+#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
>+
>+
>+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
>+// base address: 0xa50
>+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
>+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
>+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
>+#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
>+#define mmHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
>+#define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
>+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
>+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
>+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
>+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
>+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
>+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
>+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
>+#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
>+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
>+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
>+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
>+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
>+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
>+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
>+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
>+#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
>+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
>+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
>+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
>+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
>+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
>+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
>+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
>+#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
>+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
>+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
>+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
>+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
>+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
>+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
>+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
>+#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
>+#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
>+#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
>+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
>+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
>+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
>+#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
>+#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b4
>+#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
>+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b5
>+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
>+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b6
>+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
>+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b7
>+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
>+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b8
>+#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
>+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b9
>+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
>+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08ba
>+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
>+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08bb
>+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
>+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bc
>+#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
>+#define mmHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08c0
>+#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
>+#define mmHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08c1
>+#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
>+#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08c2
>+#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
>+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08c3
>+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
>+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c4
>+#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
>+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c5
>+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
>+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c6
>+#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
>+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c7
>+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
>+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c8
>+#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
>+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c9
>+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
>+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08ca
>+#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
>+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08cb
>+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
>+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08cc
>+#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
>+#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d9
>+#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
>+#define mmHUBPREQ3_BLANK_OFFSET_0                                                                      0x08da
>+#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
>+#define mmHUBPREQ3_BLANK_OFFSET_1                                                                      0x08db
>+#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
>+#define mmHUBPREQ3_DST_DIMENSIONS                                                                      0x08dc
>+#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
>+#define mmHUBPREQ3_DST_AFTER_SCALER                                                                    0x08dd
>+#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
>+#define mmHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08de
>+#define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
>+#define mmHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08df
>+#define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08e0
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08e1
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08e2
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e3
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e4
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
>+#define mmHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e5
>+#define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
>+#define mmHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e6
>+#define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
>+#define mmHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e7
>+#define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
>+#define mmHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e8
>+#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
>+#define mmHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e9
>+#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
>+#define mmHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08ea
>+#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
>+#define mmHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08eb
>+#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
>+#define mmHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08ec
>+#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
>+#define mmHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08ed
>+#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
>+#define mmHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08ee
>+#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
>+#define mmHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ef
>+#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
>+#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08f0
>+#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
>+#define mmHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08f1
>+#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
>+#define mmHUBPREQ3_CURSOR_SETTINGS                                                                     0x08f2
>+#define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
>+#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f3
>+#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
>+#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f4
>+#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
>+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f5
>+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
>+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f6
>+#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f9
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08fa
>+#define mmHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
>+#define mmHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08fb
>+#define mmHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
>+#define mmHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08fc
>+#define mmHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
>+#define mmHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fd
>+#define mmHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
>+#define mmHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fe
>+#define mmHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
>+// base address: 0xa50
>+#define mmHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
>+#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
>+#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
>+#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
>+#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
>+#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
>+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
>+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
>+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
>+#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
>+#define mmHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
>+#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
>+#define mmHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
>+#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
>+#define mmHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
>+#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
>+#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
>+#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
>+#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
>+#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
>+
>+
>+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
>+// base address: 0xa50
>+#define mmCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
>+#define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
>+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
>+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
>+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
>+#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
>+#define mmCURSOR0_3_CURSOR_SIZE                                                                        0x090f
>+#define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
>+#define mmCURSOR0_3_CURSOR_POSITION                                                                    0x0910
>+#define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
>+#define mmCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
>+#define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
>+#define mmCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
>+#define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
>+#define mmCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
>+#define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
>+#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
>+#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
>+#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
>+#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
>+#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
>+#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
>+#define mmCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
>+#define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
>+#define mmCURSOR0_3_DMDATA_CNTL                                                                        0x0918
>+#define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
>+#define mmCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
>+#define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
>+#define mmCURSOR0_3_DMDATA_STATUS                                                                      0x091a
>+#define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
>+#define mmCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
>+#define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
>+#define mmCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
>+#define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x24c4
>+#define mmDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x0931
>+#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x0932
>+#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON10_PERFCOUNTER_STATE                                                               0x0933
>+#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON10_PERFMON_CNTL                                                                    0x0934
>+#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON10_PERFMON_CNTL2                                                                   0x0935
>+#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x0936
>+#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x0937
>+#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON10_PERFMON_HI                                                                      0x0938
>+#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON10_PERFMON_LOW                                                                     0x0939
>+#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
>+// base address: 0x0
>+#define mmDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
>+#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
>+#define mmDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
>+#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
>+#define mmDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
>+#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
>+#define mmDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
>+#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
>+#define mmDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
>+#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
>+#define mmDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
>+#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
>+// base address: 0x0
>+#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
>+#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
>+#define mmCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
>+#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
>+#define mmCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
>+#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
>+#define mmCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
>+#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
>+#define mmCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
>+#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
>+#define mmCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
>+#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
>+#define mmCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
>+#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
>+#define mmCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
>+#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
>+#define mmCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
>+#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
>+#define mmCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
>+#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
>+#define mmCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
>+#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
>+#define mmCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
>+#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
>+#define mmCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
>+#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
>+#define mmCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
>+#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
>+// base address: 0x0
>+#define mmCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0ce0
>+#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
>+#define mmCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0ce1
>+#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
>+#define mmCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0ce2
>+#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
>+#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0ce3
>+#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
>+// base address: 0x0
>+#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cea
>+#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
>+#define mmDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0ceb
>+#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
>+#define mmDSCL0_SCL_MODE                                                                               0x0cec
>+#define mmDSCL0_SCL_MODE_BASE_IDX                                                                      2
>+#define mmDSCL0_SCL_TAP_CONTROL                                                                        0x0ced
>+#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
>+#define mmDSCL0_DSCL_CONTROL                                                                           0x0cee
>+#define mmDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
>+#define mmDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cef
>+#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
>+#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cf0
>+#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
>+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0cf1
>+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
>+#define mmDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0cf2
>+#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
>+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0cf3
>+#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
>+#define mmDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0cf4
>+#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
>+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0cf5
>+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
>+#define mmDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0cf6
>+#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
>+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0cf7
>+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
>+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0cf8
>+#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
>+#define mmDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0cf9
>+#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
>+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0cfa
>+#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
>+#define mmDSCL0_SCL_BLACK_OFFSET                                                                       0x0cfb
>+#define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX                                                              2
>+#define mmDSCL0_DSCL_UPDATE                                                                            0x0cfc
>+#define mmDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
>+#define mmDSCL0_DSCL_AUTOCAL                                                                           0x0cfd
>+#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
>+#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0cfe
>+#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
>+#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0cff
>+#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
>+#define mmDSCL0_OTG_H_BLANK                                                                            0x0d00
>+#define mmDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
>+#define mmDSCL0_OTG_V_BLANK                                                                            0x0d01
>+#define mmDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
>+#define mmDSCL0_RECOUT_START                                                                           0x0d02
>+#define mmDSCL0_RECOUT_START_BASE_IDX                                                                  2
>+#define mmDSCL0_RECOUT_SIZE                                                                            0x0d03
>+#define mmDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
>+#define mmDSCL0_MPC_SIZE                                                                               0x0d04
>+#define mmDSCL0_MPC_SIZE_BASE_IDX                                                                      2
>+#define mmDSCL0_LB_DATA_FORMAT                                                                         0x0d05
>+#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
>+#define mmDSCL0_LB_MEMORY_CTRL                                                                         0x0d06
>+#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
>+#define mmDSCL0_LB_V_COUNTER                                                                           0x0d07
>+#define mmDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
>+#define mmDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d08
>+#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
>+#define mmDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d09
>+#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
>+#define mmDSCL0_OBUF_CONTROL                                                                           0x0d0a
>+#define mmDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
>+#define mmDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d0b
>+#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
>+// base address: 0x0
>+#define mmCM0_CM_CONTROL                                                                               0x0d1a
>+#define mmCM0_CM_CONTROL_BASE_IDX                                                                      2
>+#define mmCM0_CM_ICSC_CONTROL                                                                          0x0d1b
>+#define mmCM0_CM_ICSC_CONTROL_BASE_IDX                                                                 2
>+#define mmCM0_CM_ICSC_C11_C12                                                                          0x0d1c
>+#define mmCM0_CM_ICSC_C11_C12_BASE_IDX                                                                 2
>+#define mmCM0_CM_ICSC_C13_C14                                                                          0x0d1d
>+#define mmCM0_CM_ICSC_C13_C14_BASE_IDX                                                                 2
>+#define mmCM0_CM_ICSC_C21_C22                                                                          0x0d1e
>+#define mmCM0_CM_ICSC_C21_C22_BASE_IDX                                                                 2
>+#define mmCM0_CM_ICSC_C23_C24                                                                          0x0d1f
>+#define mmCM0_CM_ICSC_C23_C24_BASE_IDX                                                                 2
>+#define mmCM0_CM_ICSC_C31_C32                                                                          0x0d20
>+#define mmCM0_CM_ICSC_C31_C32_BASE_IDX                                                                 2
>+#define mmCM0_CM_ICSC_C33_C34                                                                          0x0d21
>+#define mmCM0_CM_ICSC_C33_C34_BASE_IDX                                                                 2
>+#define mmCM0_CM_ICSC_B_C11_C12                                                                        0x0d22
>+#define mmCM0_CM_ICSC_B_C11_C12_BASE_IDX                                                               2
>+#define mmCM0_CM_ICSC_B_C13_C14                                                                        0x0d23
>+#define mmCM0_CM_ICSC_B_C13_C14_BASE_IDX                                                               2
>+#define mmCM0_CM_ICSC_B_C21_C22                                                                        0x0d24
>+#define mmCM0_CM_ICSC_B_C21_C22_BASE_IDX                                                               2
>+#define mmCM0_CM_ICSC_B_C23_C24                                                                        0x0d25
>+#define mmCM0_CM_ICSC_B_C23_C24_BASE_IDX                                                               2
>+#define mmCM0_CM_ICSC_B_C31_C32                                                                        0x0d26
>+#define mmCM0_CM_ICSC_B_C31_C32_BASE_IDX                                                               2
>+#define mmCM0_CM_ICSC_B_C33_C34                                                                        0x0d27
>+#define mmCM0_CM_ICSC_B_C33_C34_BASE_IDX                                                               2
>+#define mmCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d28
>+#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
>+#define mmCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d29
>+#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
>+#define mmCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d2a
>+#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
>+#define mmCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d2b
>+#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
>+#define mmCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d2c
>+#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
>+#define mmCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d2d
>+#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
>+#define mmCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d2e
>+#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
>+#define mmCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d2f
>+#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
>+#define mmCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d30
>+#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
>+#define mmCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d31
>+#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
>+#define mmCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d32
>+#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
>+#define mmCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d33
>+#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
>+#define mmCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d34
>+#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
>+#define mmCM0_CM_BIAS_CR_R                                                                             0x0d35
>+#define mmCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
>+#define mmCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d36
>+#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
>+#define mmCM0_CM_DGAM_CONTROL                                                                          0x0d37
>+#define mmCM0_CM_DGAM_CONTROL_BASE_IDX                                                                 2
>+#define mmCM0_CM_DGAM_LUT_INDEX                                                                        0x0d38
>+#define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX                                                               2
>+#define mmCM0_CM_DGAM_LUT_DATA                                                                         0x0d39
>+#define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX                                                                2
>+#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x0d3a
>+#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMA_START_CNTL_B                                                                0x0d3b
>+#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMA_START_CNTL_G                                                                0x0d3c
>+#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMA_START_CNTL_R                                                                0x0d3d
>+#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B                                                                0x0d3e
>+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G                                                                0x0d3f
>+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R                                                                0x0d40
>+#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0d41
>+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
>+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x0d42
>+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        2
>+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0d43
>+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
>+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x0d44
>+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        2
>+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0d45
>+#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
>+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x0d46
>+#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        2
>+#define mmCM0_CM_DGAM_RAMA_REGION_0_1                                                                  0x0d47
>+#define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX                                                         2
>+#define mmCM0_CM_DGAM_RAMA_REGION_2_3                                                                  0x0d48
>+#define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX                                                         2
>+#define mmCM0_CM_DGAM_RAMA_REGION_4_5                                                                  0x0d49
>+#define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX                                                         2
>+#define mmCM0_CM_DGAM_RAMA_REGION_6_7                                                                  0x0d4a
>+#define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX                                                         2
>+#define mmCM0_CM_DGAM_RAMA_REGION_8_9                                                                  0x0d4b
>+#define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX                                                         2
>+#define mmCM0_CM_DGAM_RAMA_REGION_10_11                                                                0x0d4c
>+#define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMA_REGION_12_13                                                                0x0d4d
>+#define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMA_REGION_14_15                                                                0x0d4e
>+#define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMB_START_CNTL_B                                                                0x0d4f
>+#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMB_START_CNTL_G                                                                0x0d50
>+#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMB_START_CNTL_R                                                                0x0d51
>+#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B                                                                0x0d52
>+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G                                                                0x0d53
>+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R                                                                0x0d54
>+#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B                                                                 0x0d55
>+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX                                                        2
>+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B                                                                 0x0d56
>+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX                                                        2
>+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G                                                                 0x0d57
>+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
>+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G                                                                 0x0d58
>+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX                                                        2
>+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R                                                                 0x0d59
>+#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX                                                        2
>+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R                                                                 0x0d5a
>+#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
>+#define mmCM0_CM_DGAM_RAMB_REGION_0_1                                                                  0x0d5b
>+#define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX                                                         2
>+#define mmCM0_CM_DGAM_RAMB_REGION_2_3                                                                  0x0d5c
>+#define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX                                                         2
>+#define mmCM0_CM_DGAM_RAMB_REGION_4_5                                                                  0x0d5d
>+#define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX                                                         2
>+#define mmCM0_CM_DGAM_RAMB_REGION_6_7                                                                  0x0d5e
>+#define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX                                                         2
>+#define mmCM0_CM_DGAM_RAMB_REGION_8_9                                                                  0x0d5f
>+#define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX                                                         2
>+#define mmCM0_CM_DGAM_RAMB_REGION_10_11                                                                0x0d60
>+#define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMB_REGION_12_13                                                                0x0d61
>+#define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX                                                       2
>+#define mmCM0_CM_DGAM_RAMB_REGION_14_15                                                                0x0d62
>+#define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX                                                       2
>+#define mmCM0_CM_BLNDGAM_CONTROL                                                                       0x0d63
>+#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
>+#define mmCM0_CM_BLNDGAM_LUT_INDEX                                                                     0x0d64
>+#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
>+#define mmCM0_CM_BLNDGAM_LUT_DATA                                                                      0x0d65
>+#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
>+#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK                                                             0x0d66
>+#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0d67
>+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0d68
>+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0d69
>+#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B                                                             0x0d6a
>+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G                                                             0x0d6b
>+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R                                                             0x0d6c
>+#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0d6d
>+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
>+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0d6e
>+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
>+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0d6f
>+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
>+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0d70
>+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
>+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0d71
>+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
>+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0d72
>+#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0d73
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0d74
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0d75
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0d76
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0d77
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0d78
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0d79
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0d7a
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0d7b
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0d7c
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0d7d
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0d7e
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0d7f
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0d80
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0d81
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0d82
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0d83
>+#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0d84
>+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0d85
>+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0d86
>+#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B                                                             0x0d87
>+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G                                                             0x0d88
>+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R                                                             0x0d89
>+#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0d8a
>+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
>+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0d8b
>+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
>+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0d8c
>+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
>+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0d8d
>+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
>+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0d8e
>+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
>+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0d8f
>+#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0d90
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0d91
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0d92
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0d93
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0d94
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0d95
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0d96
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0d97
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0d98
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0d99
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0d9a
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0d9b
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0d9c
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0d9d
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0d9e
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0d9f
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0da0
>+#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
>+#define mmCM0_CM_HDR_MULT_COEF                                                                         0x0da1
>+#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
>+#define mmCM0_CM_MEM_PWR_CTRL                                                                          0x0da2
>+#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
>+#define mmCM0_CM_MEM_PWR_STATUS                                                                        0x0da3
>+#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
>+#define mmCM0_CM_DEALPHA                                                                               0x0da5
>+#define mmCM0_CM_DEALPHA_BASE_IDX                                                                      2
>+#define mmCM0_CM_COEF_FORMAT                                                                           0x0da6
>+#define mmCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
>+#define mmCM0_CM_SHAPER_CONTROL                                                                        0x0da7
>+#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX                                                               2
>+#define mmCM0_CM_SHAPER_OFFSET_R                                                                       0x0da8
>+#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
>+#define mmCM0_CM_SHAPER_OFFSET_G                                                                       0x0da9
>+#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
>+#define mmCM0_CM_SHAPER_OFFSET_B                                                                       0x0daa
>+#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
>+#define mmCM0_CM_SHAPER_SCALE_R                                                                        0x0dab
>+#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
>+#define mmCM0_CM_SHAPER_SCALE_G_B                                                                      0x0dac
>+#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
>+#define mmCM0_CM_SHAPER_LUT_INDEX                                                                      0x0dad
>+#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
>+#define mmCM0_CM_SHAPER_LUT_DATA                                                                       0x0dae
>+#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
>+#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0daf
>+#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0db0
>+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0db1
>+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0db2
>+#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0db3
>+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0db4
>+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0db5
>+#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_0_1                                                                0x0db6
>+#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_2_3                                                                0x0db7
>+#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_4_5                                                                0x0db8
>+#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_6_7                                                                0x0db9
>+#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_8_9                                                                0x0dba
>+#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_10_11                                                              0x0dbb
>+#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_12_13                                                              0x0dbc
>+#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_14_15                                                              0x0dbd
>+#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_16_17                                                              0x0dbe
>+#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_18_19                                                              0x0dbf
>+#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_20_21                                                              0x0dc0
>+#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_22_23                                                              0x0dc1
>+#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_24_25                                                              0x0dc2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_26_27                                                              0x0dc3
>+#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_28_29                                                              0x0dc4
>+#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_30_31                                                              0x0dc5
>+#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMA_REGION_32_33                                                              0x0dc6
>+#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0dc7
>+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0dc8
>+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0dc9
>+#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0dca
>+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0dcb
>+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0dcc
>+#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_0_1                                                                0x0dcd
>+#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_2_3                                                                0x0dce
>+#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_4_5                                                                0x0dcf
>+#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_6_7                                                                0x0dd0
>+#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_8_9                                                                0x0dd1
>+#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_10_11                                                              0x0dd2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_12_13                                                              0x0dd3
>+#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_14_15                                                              0x0dd4
>+#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_16_17                                                              0x0dd5
>+#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_18_19                                                              0x0dd6
>+#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_20_21                                                              0x0dd7
>+#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_22_23                                                              0x0dd8
>+#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_24_25                                                              0x0dd9
>+#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_26_27                                                              0x0dda
>+#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_28_29                                                              0x0ddb
>+#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_30_31                                                              0x0ddc
>+#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
>+#define mmCM0_CM_SHAPER_RAMB_REGION_32_33                                                              0x0ddd
>+#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
>+#define mmCM0_CM_MEM_PWR_CTRL2                                                                         0x0dde
>+#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
>+#define mmCM0_CM_MEM_PWR_STATUS2                                                                       0x0ddf
>+#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
>+#define mmCM0_CM_3DLUT_MODE                                                                            0x0de0
>+#define mmCM0_CM_3DLUT_MODE_BASE_IDX                                                                   2
>+#define mmCM0_CM_3DLUT_INDEX                                                                           0x0de1
>+#define mmCM0_CM_3DLUT_INDEX_BASE_IDX                                                                  2
>+#define mmCM0_CM_3DLUT_DATA                                                                            0x0de2
>+#define mmCM0_CM_3DLUT_DATA_BASE_IDX                                                                   2
>+#define mmCM0_CM_3DLUT_DATA_30BIT                                                                      0x0de3
>+#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
>+#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0de4
>+#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
>+#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0de5
>+#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
>+#define mmCM0_CM_3DLUT_OUT_OFFSET_R                                                                    0x0de6
>+#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
>+#define mmCM0_CM_3DLUT_OUT_OFFSET_G                                                                    0x0de7
>+#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
>+#define mmCM0_CM_3DLUT_OUT_OFFSET_B                                                                    0x0de8
>+#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
>+#define mmCM0_CM_TEST_DEBUG_INDEX                                                                      0x0de9
>+#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
>+#define mmCM0_CM_TEST_DEBUG_DATA                                                                       0x0dea
>+#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x3890
>+#define mmDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x0e24
>+#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x0e25
>+#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON11_PERFCOUNTER_STATE                                                               0x0e26
>+#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON11_PERFMON_CNTL                                                                    0x0e27
>+#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON11_PERFMON_CNTL2                                                                   0x0e28
>+#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x0e29
>+#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x0e2a
>+#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON11_PERFMON_HI                                                                      0x0e2b
>+#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON11_PERFMON_LOW                                                                     0x0e2c
>+#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
>+// base address: 0x5ac
>+#define mmDPP_TOP1_DPP_CONTROL                                                                         0x0e30
>+#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
>+#define mmDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
>+#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
>+#define mmDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
>+#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
>+#define mmDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
>+#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
>+#define mmDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
>+#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
>+#define mmDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
>+#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
>+// base address: 0x5ac
>+#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
>+#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
>+#define mmCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
>+#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
>+#define mmCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
>+#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
>+#define mmCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
>+#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
>+#define mmCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
>+#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
>+#define mmCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
>+#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
>+#define mmCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
>+#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
>+#define mmCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
>+#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
>+#define mmCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
>+#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
>+#define mmCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
>+#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
>+#define mmCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
>+#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
>+#define mmCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
>+#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
>+#define mmCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
>+#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
>+#define mmCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
>+#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
>+// base address: 0x5ac
>+#define mmCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e4b
>+#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
>+#define mmCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e4c
>+#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
>+#define mmCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e4d
>+#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
>+#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e4e
>+#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
>+// base address: 0x5ac
>+#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e55
>+#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
>+#define mmDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e56
>+#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
>+#define mmDSCL1_SCL_MODE                                                                               0x0e57
>+#define mmDSCL1_SCL_MODE_BASE_IDX                                                                      2
>+#define mmDSCL1_SCL_TAP_CONTROL                                                                        0x0e58
>+#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
>+#define mmDSCL1_DSCL_CONTROL                                                                           0x0e59
>+#define mmDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
>+#define mmDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e5a
>+#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
>+#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e5b
>+#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
>+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e5c
>+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
>+#define mmDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e5d
>+#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
>+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e5e
>+#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
>+#define mmDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e5f
>+#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
>+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e60
>+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
>+#define mmDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e61
>+#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
>+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e62
>+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
>+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e63
>+#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
>+#define mmDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e64
>+#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
>+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e65
>+#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
>+#define mmDSCL1_SCL_BLACK_OFFSET                                                                       0x0e66
>+#define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX                                                              2
>+#define mmDSCL1_DSCL_UPDATE                                                                            0x0e67
>+#define mmDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
>+#define mmDSCL1_DSCL_AUTOCAL                                                                           0x0e68
>+#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
>+#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e69
>+#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
>+#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e6a
>+#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
>+#define mmDSCL1_OTG_H_BLANK                                                                            0x0e6b
>+#define mmDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
>+#define mmDSCL1_OTG_V_BLANK                                                                            0x0e6c
>+#define mmDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
>+#define mmDSCL1_RECOUT_START                                                                           0x0e6d
>+#define mmDSCL1_RECOUT_START_BASE_IDX                                                                  2
>+#define mmDSCL1_RECOUT_SIZE                                                                            0x0e6e
>+#define mmDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
>+#define mmDSCL1_MPC_SIZE                                                                               0x0e6f
>+#define mmDSCL1_MPC_SIZE_BASE_IDX                                                                      2
>+#define mmDSCL1_LB_DATA_FORMAT                                                                         0x0e70
>+#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
>+#define mmDSCL1_LB_MEMORY_CTRL                                                                         0x0e71
>+#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
>+#define mmDSCL1_LB_V_COUNTER                                                                           0x0e72
>+#define mmDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
>+#define mmDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e73
>+#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
>+#define mmDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e74
>+#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
>+#define mmDSCL1_OBUF_CONTROL                                                                           0x0e75
>+#define mmDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
>+#define mmDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e76
>+#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
>+// base address: 0x5ac
>+#define mmCM1_CM_CONTROL                                                                               0x0e85
>+#define mmCM1_CM_CONTROL_BASE_IDX                                                                      2
>+#define mmCM1_CM_ICSC_CONTROL                                                                          0x0e86
>+#define mmCM1_CM_ICSC_CONTROL_BASE_IDX                                                                 2
>+#define mmCM1_CM_ICSC_C11_C12                                                                          0x0e87
>+#define mmCM1_CM_ICSC_C11_C12_BASE_IDX                                                                 2
>+#define mmCM1_CM_ICSC_C13_C14                                                                          0x0e88
>+#define mmCM1_CM_ICSC_C13_C14_BASE_IDX                                                                 2
>+#define mmCM1_CM_ICSC_C21_C22                                                                          0x0e89
>+#define mmCM1_CM_ICSC_C21_C22_BASE_IDX                                                                 2
>+#define mmCM1_CM_ICSC_C23_C24                                                                          0x0e8a
>+#define mmCM1_CM_ICSC_C23_C24_BASE_IDX                                                                 2
>+#define mmCM1_CM_ICSC_C31_C32                                                                          0x0e8b
>+#define mmCM1_CM_ICSC_C31_C32_BASE_IDX                                                                 2
>+#define mmCM1_CM_ICSC_C33_C34                                                                          0x0e8c
>+#define mmCM1_CM_ICSC_C33_C34_BASE_IDX                                                                 2
>+#define mmCM1_CM_ICSC_B_C11_C12                                                                        0x0e8d
>+#define mmCM1_CM_ICSC_B_C11_C12_BASE_IDX                                                               2
>+#define mmCM1_CM_ICSC_B_C13_C14                                                                        0x0e8e
>+#define mmCM1_CM_ICSC_B_C13_C14_BASE_IDX                                                               2
>+#define mmCM1_CM_ICSC_B_C21_C22                                                                        0x0e8f
>+#define mmCM1_CM_ICSC_B_C21_C22_BASE_IDX                                                               2
>+#define mmCM1_CM_ICSC_B_C23_C24                                                                        0x0e90
>+#define mmCM1_CM_ICSC_B_C23_C24_BASE_IDX                                                               2
>+#define mmCM1_CM_ICSC_B_C31_C32                                                                        0x0e91
>+#define mmCM1_CM_ICSC_B_C31_C32_BASE_IDX                                                               2
>+#define mmCM1_CM_ICSC_B_C33_C34                                                                        0x0e92
>+#define mmCM1_CM_ICSC_B_C33_C34_BASE_IDX                                                               2
>+#define mmCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e93
>+#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
>+#define mmCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e94
>+#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
>+#define mmCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e95
>+#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
>+#define mmCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e96
>+#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
>+#define mmCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e97
>+#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
>+#define mmCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e98
>+#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
>+#define mmCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e99
>+#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
>+#define mmCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0e9a
>+#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
>+#define mmCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0e9b
>+#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
>+#define mmCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0e9c
>+#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
>+#define mmCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0e9d
>+#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
>+#define mmCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0e9e
>+#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
>+#define mmCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0e9f
>+#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
>+#define mmCM1_CM_BIAS_CR_R                                                                             0x0ea0
>+#define mmCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
>+#define mmCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea1
>+#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
>+#define mmCM1_CM_DGAM_CONTROL                                                                          0x0ea2
>+#define mmCM1_CM_DGAM_CONTROL_BASE_IDX                                                                 2
>+#define mmCM1_CM_DGAM_LUT_INDEX                                                                        0x0ea3
>+#define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX                                                               2
>+#define mmCM1_CM_DGAM_LUT_DATA                                                                         0x0ea4
>+#define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX                                                                2
>+#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x0ea5
>+#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMA_START_CNTL_B                                                                0x0ea6
>+#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMA_START_CNTL_G                                                                0x0ea7
>+#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMA_START_CNTL_R                                                                0x0ea8
>+#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B                                                                0x0ea9
>+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G                                                                0x0eaa
>+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R                                                                0x0eab
>+#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x0eac
>+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
>+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x0ead
>+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        2
>+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x0eae
>+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
>+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x0eaf
>+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        2
>+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x0eb0
>+#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
>+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x0eb1
>+#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        2
>+#define mmCM1_CM_DGAM_RAMA_REGION_0_1                                                                  0x0eb2
>+#define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX                                                         2
>+#define mmCM1_CM_DGAM_RAMA_REGION_2_3                                                                  0x0eb3
>+#define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX                                                         2
>+#define mmCM1_CM_DGAM_RAMA_REGION_4_5                                                                  0x0eb4
>+#define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX                                                         2
>+#define mmCM1_CM_DGAM_RAMA_REGION_6_7                                                                  0x0eb5
>+#define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX                                                         2
>+#define mmCM1_CM_DGAM_RAMA_REGION_8_9                                                                  0x0eb6
>+#define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX                                                         2
>+#define mmCM1_CM_DGAM_RAMA_REGION_10_11                                                                0x0eb7
>+#define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMA_REGION_12_13                                                                0x0eb8
>+#define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMA_REGION_14_15                                                                0x0eb9
>+#define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMB_START_CNTL_B                                                                0x0eba
>+#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMB_START_CNTL_G                                                                0x0ebb
>+#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMB_START_CNTL_R                                                                0x0ebc
>+#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B                                                                0x0ebd
>+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G                                                                0x0ebe
>+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R                                                                0x0ebf
>+#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B                                                                 0x0ec0
>+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX                                                        2
>+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B                                                                 0x0ec1
>+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX                                                        2
>+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G                                                                 0x0ec2
>+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
>+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G                                                                 0x0ec3
>+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX                                                        2
>+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R                                                                 0x0ec4
>+#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX                                                        2
>+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R                                                                 0x0ec5
>+#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
>+#define mmCM1_CM_DGAM_RAMB_REGION_0_1                                                                  0x0ec6
>+#define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX                                                         2
>+#define mmCM1_CM_DGAM_RAMB_REGION_2_3                                                                  0x0ec7
>+#define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX                                                         2
>+#define mmCM1_CM_DGAM_RAMB_REGION_4_5                                                                  0x0ec8
>+#define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX                                                         2
>+#define mmCM1_CM_DGAM_RAMB_REGION_6_7                                                                  0x0ec9
>+#define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX                                                         2
>+#define mmCM1_CM_DGAM_RAMB_REGION_8_9                                                                  0x0eca
>+#define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX                                                         2
>+#define mmCM1_CM_DGAM_RAMB_REGION_10_11                                                                0x0ecb
>+#define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMB_REGION_12_13                                                                0x0ecc
>+#define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX                                                       2
>+#define mmCM1_CM_DGAM_RAMB_REGION_14_15                                                                0x0ecd
>+#define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX                                                       2
>+#define mmCM1_CM_BLNDGAM_CONTROL                                                                       0x0ece
>+#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
>+#define mmCM1_CM_BLNDGAM_LUT_INDEX                                                                     0x0ecf
>+#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
>+#define mmCM1_CM_BLNDGAM_LUT_DATA                                                                      0x0ed0
>+#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
>+#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK                                                             0x0ed1
>+#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0ed2
>+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0ed3
>+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0ed4
>+#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B                                                             0x0ed5
>+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G                                                             0x0ed6
>+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R                                                             0x0ed7
>+#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0ed8
>+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
>+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0ed9
>+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
>+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0eda
>+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
>+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0edb
>+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
>+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0edc
>+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
>+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0edd
>+#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0ede
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0edf
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0ee0
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0ee1
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0ee2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0ee3
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0ee4
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0ee5
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0ee6
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0ee7
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0ee8
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0ee9
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0eea
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0eeb
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0eec
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0eed
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0eee
>+#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0eef
>+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0ef0
>+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0ef1
>+#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B                                                             0x0ef2
>+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G                                                             0x0ef3
>+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R                                                             0x0ef4
>+#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0ef5
>+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
>+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0ef6
>+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
>+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0ef7
>+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
>+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0ef8
>+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
>+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0ef9
>+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
>+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0efa
>+#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0efb
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0efc
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0efd
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0efe
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0eff
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0f00
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0f01
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0f02
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0f03
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0f04
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0f05
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0f06
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0f07
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0f08
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0f09
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0f0a
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0f0b
>+#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
>+#define mmCM1_CM_HDR_MULT_COEF                                                                         0x0f0c
>+#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
>+#define mmCM1_CM_MEM_PWR_CTRL                                                                          0x0f0d
>+#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
>+#define mmCM1_CM_MEM_PWR_STATUS                                                                        0x0f0e
>+#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
>+#define mmCM1_CM_DEALPHA                                                                               0x0f10
>+#define mmCM1_CM_DEALPHA_BASE_IDX                                                                      2
>+#define mmCM1_CM_COEF_FORMAT                                                                           0x0f11
>+#define mmCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
>+#define mmCM1_CM_SHAPER_CONTROL                                                                        0x0f12
>+#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX                                                               2
>+#define mmCM1_CM_SHAPER_OFFSET_R                                                                       0x0f13
>+#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
>+#define mmCM1_CM_SHAPER_OFFSET_G                                                                       0x0f14
>+#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
>+#define mmCM1_CM_SHAPER_OFFSET_B                                                                       0x0f15
>+#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
>+#define mmCM1_CM_SHAPER_SCALE_R                                                                        0x0f16
>+#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
>+#define mmCM1_CM_SHAPER_SCALE_G_B                                                                      0x0f17
>+#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
>+#define mmCM1_CM_SHAPER_LUT_INDEX                                                                      0x0f18
>+#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
>+#define mmCM1_CM_SHAPER_LUT_DATA                                                                       0x0f19
>+#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
>+#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0f1a
>+#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0f1b
>+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0f1c
>+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0f1d
>+#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0f1e
>+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0f1f
>+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0f20
>+#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_0_1                                                                0x0f21
>+#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_2_3                                                                0x0f22
>+#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_4_5                                                                0x0f23
>+#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_6_7                                                                0x0f24
>+#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_8_9                                                                0x0f25
>+#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_10_11                                                              0x0f26
>+#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_12_13                                                              0x0f27
>+#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_14_15                                                              0x0f28
>+#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_16_17                                                              0x0f29
>+#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_18_19                                                              0x0f2a
>+#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_20_21                                                              0x0f2b
>+#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_22_23                                                              0x0f2c
>+#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_24_25                                                              0x0f2d
>+#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_26_27                                                              0x0f2e
>+#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_28_29                                                              0x0f2f
>+#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_30_31                                                              0x0f30
>+#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMA_REGION_32_33                                                              0x0f31
>+#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0f32
>+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0f33
>+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0f34
>+#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0f35
>+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0f36
>+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0f37
>+#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_0_1                                                                0x0f38
>+#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_2_3                                                                0x0f39
>+#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_4_5                                                                0x0f3a
>+#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_6_7                                                                0x0f3b
>+#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_8_9                                                                0x0f3c
>+#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_10_11                                                              0x0f3d
>+#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_12_13                                                              0x0f3e
>+#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_14_15                                                              0x0f3f
>+#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_16_17                                                              0x0f40
>+#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_18_19                                                              0x0f41
>+#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_20_21                                                              0x0f42
>+#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_22_23                                                              0x0f43
>+#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_24_25                                                              0x0f44
>+#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_26_27                                                              0x0f45
>+#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_28_29                                                              0x0f46
>+#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_30_31                                                              0x0f47
>+#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
>+#define mmCM1_CM_SHAPER_RAMB_REGION_32_33                                                              0x0f48
>+#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
>+#define mmCM1_CM_MEM_PWR_CTRL2                                                                         0x0f49
>+#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
>+#define mmCM1_CM_MEM_PWR_STATUS2                                                                       0x0f4a
>+#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
>+#define mmCM1_CM_3DLUT_MODE                                                                            0x0f4b
>+#define mmCM1_CM_3DLUT_MODE_BASE_IDX                                                                   2
>+#define mmCM1_CM_3DLUT_INDEX                                                                           0x0f4c
>+#define mmCM1_CM_3DLUT_INDEX_BASE_IDX                                                                  2
>+#define mmCM1_CM_3DLUT_DATA                                                                            0x0f4d
>+#define mmCM1_CM_3DLUT_DATA_BASE_IDX                                                                   2
>+#define mmCM1_CM_3DLUT_DATA_30BIT                                                                      0x0f4e
>+#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
>+#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0f4f
>+#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
>+#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0f50
>+#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
>+#define mmCM1_CM_3DLUT_OUT_OFFSET_R                                                                    0x0f51
>+#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
>+#define mmCM1_CM_3DLUT_OUT_OFFSET_G                                                                    0x0f52
>+#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
>+#define mmCM1_CM_3DLUT_OUT_OFFSET_B                                                                    0x0f53
>+#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
>+#define mmCM1_CM_TEST_DEBUG_INDEX                                                                      0x0f54
>+#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
>+#define mmCM1_CM_TEST_DEBUG_DATA                                                                       0x0f55
>+#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x3e3c
>+#define mmDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x0f8f
>+#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x0f90
>+#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON12_PERFCOUNTER_STATE                                                               0x0f91
>+#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON12_PERFMON_CNTL                                                                    0x0f92
>+#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON12_PERFMON_CNTL2                                                                   0x0f93
>+#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x0f94
>+#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x0f95
>+#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON12_PERFMON_HI                                                                      0x0f96
>+#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON12_PERFMON_LOW                                                                     0x0f97
>+#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
>+// base address: 0xb58
>+#define mmDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
>+#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
>+#define mmDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
>+#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
>+#define mmDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
>+#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
>+#define mmDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
>+#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
>+#define mmDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
>+#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
>+#define mmDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
>+#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
>+// base address: 0xb58
>+#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
>+#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
>+#define mmCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
>+#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
>+#define mmCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
>+#define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
>+#define mmCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
>+#define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
>+#define mmCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
>+#define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
>+#define mmCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
>+#define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
>+#define mmCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
>+#define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
>+#define mmCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
>+#define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
>+#define mmCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
>+#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
>+#define mmCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
>+#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
>+#define mmCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
>+#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
>+#define mmCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
>+#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
>+#define mmCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
>+#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
>+#define mmCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
>+#define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
>+// base address: 0xb58
>+#define mmCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fb6
>+#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
>+#define mmCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fb7
>+#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
>+#define mmCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fb8
>+#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
>+#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fb9
>+#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
>+// base address: 0xb58
>+#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fc0
>+#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
>+#define mmDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fc1
>+#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
>+#define mmDSCL2_SCL_MODE                                                                               0x0fc2
>+#define mmDSCL2_SCL_MODE_BASE_IDX                                                                      2
>+#define mmDSCL2_SCL_TAP_CONTROL                                                                        0x0fc3
>+#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
>+#define mmDSCL2_DSCL_CONTROL                                                                           0x0fc4
>+#define mmDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
>+#define mmDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fc5
>+#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
>+#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fc6
>+#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
>+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fc7
>+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
>+#define mmDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fc8
>+#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
>+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fc9
>+#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
>+#define mmDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fca
>+#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
>+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fcb
>+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
>+#define mmDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fcc
>+#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
>+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fcd
>+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
>+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fce
>+#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
>+#define mmDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fcf
>+#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
>+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fd0
>+#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
>+#define mmDSCL2_SCL_BLACK_OFFSET                                                                       0x0fd1
>+#define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX                                                              2
>+#define mmDSCL2_DSCL_UPDATE                                                                            0x0fd2
>+#define mmDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
>+#define mmDSCL2_DSCL_AUTOCAL                                                                           0x0fd3
>+#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
>+#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fd4
>+#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
>+#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fd5
>+#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
>+#define mmDSCL2_OTG_H_BLANK                                                                            0x0fd6
>+#define mmDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
>+#define mmDSCL2_OTG_V_BLANK                                                                            0x0fd7
>+#define mmDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
>+#define mmDSCL2_RECOUT_START                                                                           0x0fd8
>+#define mmDSCL2_RECOUT_START_BASE_IDX                                                                  2
>+#define mmDSCL2_RECOUT_SIZE                                                                            0x0fd9
>+#define mmDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
>+#define mmDSCL2_MPC_SIZE                                                                               0x0fda
>+#define mmDSCL2_MPC_SIZE_BASE_IDX                                                                      2
>+#define mmDSCL2_LB_DATA_FORMAT                                                                         0x0fdb
>+#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
>+#define mmDSCL2_LB_MEMORY_CTRL                                                                         0x0fdc
>+#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
>+#define mmDSCL2_LB_V_COUNTER                                                                           0x0fdd
>+#define mmDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
>+#define mmDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fde
>+#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
>+#define mmDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fdf
>+#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
>+#define mmDSCL2_OBUF_CONTROL                                                                           0x0fe0
>+#define mmDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
>+#define mmDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0fe1
>+#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
>+// base address: 0xb58
>+#define mmCM2_CM_CONTROL                                                                               0x0ff0
>+#define mmCM2_CM_CONTROL_BASE_IDX                                                                      2
>+#define mmCM2_CM_ICSC_CONTROL                                                                          0x0ff1
>+#define mmCM2_CM_ICSC_CONTROL_BASE_IDX                                                                 2
>+#define mmCM2_CM_ICSC_C11_C12                                                                          0x0ff2
>+#define mmCM2_CM_ICSC_C11_C12_BASE_IDX                                                                 2
>+#define mmCM2_CM_ICSC_C13_C14                                                                          0x0ff3
>+#define mmCM2_CM_ICSC_C13_C14_BASE_IDX                                                                 2
>+#define mmCM2_CM_ICSC_C21_C22                                                                          0x0ff4
>+#define mmCM2_CM_ICSC_C21_C22_BASE_IDX                                                                 2
>+#define mmCM2_CM_ICSC_C23_C24                                                                          0x0ff5
>+#define mmCM2_CM_ICSC_C23_C24_BASE_IDX                                                                 2
>+#define mmCM2_CM_ICSC_C31_C32                                                                          0x0ff6
>+#define mmCM2_CM_ICSC_C31_C32_BASE_IDX                                                                 2
>+#define mmCM2_CM_ICSC_C33_C34                                                                          0x0ff7
>+#define mmCM2_CM_ICSC_C33_C34_BASE_IDX                                                                 2
>+#define mmCM2_CM_ICSC_B_C11_C12                                                                        0x0ff8
>+#define mmCM2_CM_ICSC_B_C11_C12_BASE_IDX                                                               2
>+#define mmCM2_CM_ICSC_B_C13_C14                                                                        0x0ff9
>+#define mmCM2_CM_ICSC_B_C13_C14_BASE_IDX                                                               2
>+#define mmCM2_CM_ICSC_B_C21_C22                                                                        0x0ffa
>+#define mmCM2_CM_ICSC_B_C21_C22_BASE_IDX                                                               2
>+#define mmCM2_CM_ICSC_B_C23_C24                                                                        0x0ffb
>+#define mmCM2_CM_ICSC_B_C23_C24_BASE_IDX                                                               2
>+#define mmCM2_CM_ICSC_B_C31_C32                                                                        0x0ffc
>+#define mmCM2_CM_ICSC_B_C31_C32_BASE_IDX                                                               2
>+#define mmCM2_CM_ICSC_B_C33_C34                                                                        0x0ffd
>+#define mmCM2_CM_ICSC_B_C33_C34_BASE_IDX                                                               2
>+#define mmCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x0ffe
>+#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
>+#define mmCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x0fff
>+#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
>+#define mmCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1000
>+#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
>+#define mmCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1001
>+#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
>+#define mmCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1002
>+#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
>+#define mmCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1003
>+#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
>+#define mmCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x1004
>+#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
>+#define mmCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1005
>+#define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
>+#define mmCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1006
>+#define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
>+#define mmCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1007
>+#define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
>+#define mmCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1008
>+#define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
>+#define mmCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x1009
>+#define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
>+#define mmCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x100a
>+#define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
>+#define mmCM2_CM_BIAS_CR_R                                                                             0x100b
>+#define mmCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
>+#define mmCM2_CM_BIAS_Y_G_CB_B                                                                         0x100c
>+#define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
>+#define mmCM2_CM_DGAM_CONTROL                                                                          0x100d
>+#define mmCM2_CM_DGAM_CONTROL_BASE_IDX                                                                 2
>+#define mmCM2_CM_DGAM_LUT_INDEX                                                                        0x100e
>+#define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX                                                               2
>+#define mmCM2_CM_DGAM_LUT_DATA                                                                         0x100f
>+#define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX                                                                2
>+#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x1010
>+#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMA_START_CNTL_B                                                                0x1011
>+#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMA_START_CNTL_G                                                                0x1012
>+#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMA_START_CNTL_R                                                                0x1013
>+#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B                                                                0x1014
>+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G                                                                0x1015
>+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R                                                                0x1016
>+#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x1017
>+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
>+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x1018
>+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        2
>+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x1019
>+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
>+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x101a
>+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        2
>+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x101b
>+#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
>+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x101c
>+#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        2
>+#define mmCM2_CM_DGAM_RAMA_REGION_0_1                                                                  0x101d
>+#define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX                                                         2
>+#define mmCM2_CM_DGAM_RAMA_REGION_2_3                                                                  0x101e
>+#define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX                                                         2
>+#define mmCM2_CM_DGAM_RAMA_REGION_4_5                                                                  0x101f
>+#define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX                                                         2
>+#define mmCM2_CM_DGAM_RAMA_REGION_6_7                                                                  0x1020
>+#define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX                                                         2
>+#define mmCM2_CM_DGAM_RAMA_REGION_8_9                                                                  0x1021
>+#define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX                                                         2
>+#define mmCM2_CM_DGAM_RAMA_REGION_10_11                                                                0x1022
>+#define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMA_REGION_12_13                                                                0x1023
>+#define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMA_REGION_14_15                                                                0x1024
>+#define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMB_START_CNTL_B                                                                0x1025
>+#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMB_START_CNTL_G                                                                0x1026
>+#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMB_START_CNTL_R                                                                0x1027
>+#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B                                                                0x1028
>+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G                                                                0x1029
>+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R                                                                0x102a
>+#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B                                                                 0x102b
>+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX                                                        2
>+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B                                                                 0x102c
>+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX                                                        2
>+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G                                                                 0x102d
>+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
>+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G                                                                 0x102e
>+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX                                                        2
>+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R                                                                 0x102f
>+#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX                                                        2
>+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R                                                                 0x1030
>+#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
>+#define mmCM2_CM_DGAM_RAMB_REGION_0_1                                                                  0x1031
>+#define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX                                                         2
>+#define mmCM2_CM_DGAM_RAMB_REGION_2_3                                                                  0x1032
>+#define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX                                                         2
>+#define mmCM2_CM_DGAM_RAMB_REGION_4_5                                                                  0x1033
>+#define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX                                                         2
>+#define mmCM2_CM_DGAM_RAMB_REGION_6_7                                                                  0x1034
>+#define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX                                                         2
>+#define mmCM2_CM_DGAM_RAMB_REGION_8_9                                                                  0x1035
>+#define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX                                                         2
>+#define mmCM2_CM_DGAM_RAMB_REGION_10_11                                                                0x1036
>+#define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMB_REGION_12_13                                                                0x1037
>+#define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX                                                       2
>+#define mmCM2_CM_DGAM_RAMB_REGION_14_15                                                                0x1038
>+#define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX                                                       2
>+#define mmCM2_CM_BLNDGAM_CONTROL                                                                       0x1039
>+#define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
>+#define mmCM2_CM_BLNDGAM_LUT_INDEX                                                                     0x103a
>+#define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
>+#define mmCM2_CM_BLNDGAM_LUT_DATA                                                                      0x103b
>+#define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
>+#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK                                                             0x103c
>+#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x103d
>+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x103e
>+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x103f
>+#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B                                                             0x1040
>+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G                                                             0x1041
>+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R                                                             0x1042
>+#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x1043
>+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
>+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x1044
>+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
>+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x1045
>+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
>+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x1046
>+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
>+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x1047
>+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
>+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x1048
>+#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x1049
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x104a
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x104b
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x104c
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x104d
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x104e
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x104f
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x1050
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x1051
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x1052
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x1053
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x1054
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x1055
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x1056
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x1057
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x1058
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x1059
>+#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x105a
>+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x105b
>+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x105c
>+#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B                                                             0x105d
>+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G                                                             0x105e
>+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R                                                             0x105f
>+#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x1060
>+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
>+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x1061
>+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
>+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x1062
>+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
>+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x1063
>+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
>+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x1064
>+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
>+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x1065
>+#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1066
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1067
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1068
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1069
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x106a
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x106b
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x106c
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x106d
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x106e
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x106f
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x1070
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x1071
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x1072
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x1073
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x1074
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x1075
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x1076
>+#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
>+#define mmCM2_CM_HDR_MULT_COEF                                                                         0x1077
>+#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
>+#define mmCM2_CM_MEM_PWR_CTRL                                                                          0x1078
>+#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
>+#define mmCM2_CM_MEM_PWR_STATUS                                                                        0x1079
>+#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
>+#define mmCM2_CM_DEALPHA                                                                               0x107b
>+#define mmCM2_CM_DEALPHA_BASE_IDX                                                                      2
>+#define mmCM2_CM_COEF_FORMAT                                                                           0x107c
>+#define mmCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
>+#define mmCM2_CM_SHAPER_CONTROL                                                                        0x107d
>+#define mmCM2_CM_SHAPER_CONTROL_BASE_IDX                                                               2
>+#define mmCM2_CM_SHAPER_OFFSET_R                                                                       0x107e
>+#define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
>+#define mmCM2_CM_SHAPER_OFFSET_G                                                                       0x107f
>+#define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
>+#define mmCM2_CM_SHAPER_OFFSET_B                                                                       0x1080
>+#define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
>+#define mmCM2_CM_SHAPER_SCALE_R                                                                        0x1081
>+#define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
>+#define mmCM2_CM_SHAPER_SCALE_G_B                                                                      0x1082
>+#define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
>+#define mmCM2_CM_SHAPER_LUT_INDEX                                                                      0x1083
>+#define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
>+#define mmCM2_CM_SHAPER_LUT_DATA                                                                       0x1084
>+#define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
>+#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x1085
>+#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B                                                              0x1086
>+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G                                                              0x1087
>+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R                                                              0x1088
>+#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B                                                                0x1089
>+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G                                                                0x108a
>+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R                                                                0x108b
>+#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_0_1                                                                0x108c
>+#define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_2_3                                                                0x108d
>+#define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_4_5                                                                0x108e
>+#define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_6_7                                                                0x108f
>+#define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_8_9                                                                0x1090
>+#define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_10_11                                                              0x1091
>+#define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_12_13                                                              0x1092
>+#define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_14_15                                                              0x1093
>+#define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_16_17                                                              0x1094
>+#define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_18_19                                                              0x1095
>+#define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_20_21                                                              0x1096
>+#define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_22_23                                                              0x1097
>+#define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_24_25                                                              0x1098
>+#define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_26_27                                                              0x1099
>+#define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_28_29                                                              0x109a
>+#define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_30_31                                                              0x109b
>+#define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMA_REGION_32_33                                                              0x109c
>+#define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B                                                              0x109d
>+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G                                                              0x109e
>+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R                                                              0x109f
>+#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B                                                                0x10a0
>+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G                                                                0x10a1
>+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R                                                                0x10a2
>+#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_0_1                                                                0x10a3
>+#define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_2_3                                                                0x10a4
>+#define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_4_5                                                                0x10a5
>+#define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_6_7                                                                0x10a6
>+#define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_8_9                                                                0x10a7
>+#define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_10_11                                                              0x10a8
>+#define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_12_13                                                              0x10a9
>+#define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_14_15                                                              0x10aa
>+#define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_16_17                                                              0x10ab
>+#define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_18_19                                                              0x10ac
>+#define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_20_21                                                              0x10ad
>+#define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_22_23                                                              0x10ae
>+#define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_24_25                                                              0x10af
>+#define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_26_27                                                              0x10b0
>+#define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_28_29                                                              0x10b1
>+#define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_30_31                                                              0x10b2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
>+#define mmCM2_CM_SHAPER_RAMB_REGION_32_33                                                              0x10b3
>+#define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
>+#define mmCM2_CM_MEM_PWR_CTRL2                                                                         0x10b4
>+#define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
>+#define mmCM2_CM_MEM_PWR_STATUS2                                                                       0x10b5
>+#define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
>+#define mmCM2_CM_3DLUT_MODE                                                                            0x10b6
>+#define mmCM2_CM_3DLUT_MODE_BASE_IDX                                                                   2
>+#define mmCM2_CM_3DLUT_INDEX                                                                           0x10b7
>+#define mmCM2_CM_3DLUT_INDEX_BASE_IDX                                                                  2
>+#define mmCM2_CM_3DLUT_DATA                                                                            0x10b8
>+#define mmCM2_CM_3DLUT_DATA_BASE_IDX                                                                   2
>+#define mmCM2_CM_3DLUT_DATA_30BIT                                                                      0x10b9
>+#define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
>+#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL                                                              0x10ba
>+#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
>+#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x10bb
>+#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
>+#define mmCM2_CM_3DLUT_OUT_OFFSET_R                                                                    0x10bc
>+#define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
>+#define mmCM2_CM_3DLUT_OUT_OFFSET_G                                                                    0x10bd
>+#define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
>+#define mmCM2_CM_3DLUT_OUT_OFFSET_B                                                                    0x10be
>+#define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
>+#define mmCM2_CM_TEST_DEBUG_INDEX                                                                      0x10bf
>+#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
>+#define mmCM2_CM_TEST_DEBUG_DATA                                                                       0x10c0
>+#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x43e8
>+#define mmDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x10fa
>+#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x10fb
>+#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON13_PERFCOUNTER_STATE                                                               0x10fc
>+#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON13_PERFMON_CNTL                                                                    0x10fd
>+#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON13_PERFMON_CNTL2                                                                   0x10fe
>+#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x10ff
>+#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x1100
>+#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON13_PERFMON_HI                                                                      0x1101
>+#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON13_PERFMON_LOW                                                                     0x1102
>+#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
>+// base address: 0x1104
>+#define mmDPP_TOP3_DPP_CONTROL                                                                         0x1106
>+#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
>+#define mmDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
>+#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
>+#define mmDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
>+#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
>+#define mmDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
>+#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
>+#define mmDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
>+#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
>+#define mmDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
>+#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
>+// base address: 0x1104
>+#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
>+#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
>+#define mmCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
>+#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
>+#define mmCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
>+#define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
>+#define mmCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
>+#define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
>+#define mmCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
>+#define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
>+#define mmCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
>+#define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
>+#define mmCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
>+#define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
>+#define mmCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
>+#define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
>+#define mmCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
>+#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
>+#define mmCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
>+#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
>+#define mmCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
>+#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
>+#define mmCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
>+#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
>+#define mmCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
>+#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
>+#define mmCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
>+#define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
>+// base address: 0x1104
>+#define mmCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1121
>+#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
>+#define mmCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1122
>+#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
>+#define mmCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1123
>+#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
>+#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1124
>+#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
>+// base address: 0x1104
>+#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x112b
>+#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
>+#define mmDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x112c
>+#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
>+#define mmDSCL3_SCL_MODE                                                                               0x112d
>+#define mmDSCL3_SCL_MODE_BASE_IDX                                                                      2
>+#define mmDSCL3_SCL_TAP_CONTROL                                                                        0x112e
>+#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
>+#define mmDSCL3_DSCL_CONTROL                                                                           0x112f
>+#define mmDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
>+#define mmDSCL3_DSCL_2TAP_CONTROL                                                                      0x1130
>+#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
>+#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1131
>+#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
>+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1132
>+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
>+#define mmDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1133
>+#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
>+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1134
>+#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
>+#define mmDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1135
>+#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
>+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1136
>+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
>+#define mmDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1137
>+#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
>+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1138
>+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
>+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1139
>+#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
>+#define mmDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x113a
>+#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
>+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x113b
>+#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
>+#define mmDSCL3_SCL_BLACK_OFFSET                                                                       0x113c
>+#define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX                                                              2
>+#define mmDSCL3_DSCL_UPDATE                                                                            0x113d
>+#define mmDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
>+#define mmDSCL3_DSCL_AUTOCAL                                                                           0x113e
>+#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
>+#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x113f
>+#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
>+#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x1140
>+#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
>+#define mmDSCL3_OTG_H_BLANK                                                                            0x1141
>+#define mmDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
>+#define mmDSCL3_OTG_V_BLANK                                                                            0x1142
>+#define mmDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
>+#define mmDSCL3_RECOUT_START                                                                           0x1143
>+#define mmDSCL3_RECOUT_START_BASE_IDX                                                                  2
>+#define mmDSCL3_RECOUT_SIZE                                                                            0x1144
>+#define mmDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
>+#define mmDSCL3_MPC_SIZE                                                                               0x1145
>+#define mmDSCL3_MPC_SIZE_BASE_IDX                                                                      2
>+#define mmDSCL3_LB_DATA_FORMAT                                                                         0x1146
>+#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
>+#define mmDSCL3_LB_MEMORY_CTRL                                                                         0x1147
>+#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
>+#define mmDSCL3_LB_V_COUNTER                                                                           0x1148
>+#define mmDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
>+#define mmDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1149
>+#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
>+#define mmDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x114a
>+#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
>+#define mmDSCL3_OBUF_CONTROL                                                                           0x114b
>+#define mmDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
>+#define mmDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x114c
>+#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
>+// base address: 0x1104
>+#define mmCM3_CM_CONTROL                                                                               0x115b
>+#define mmCM3_CM_CONTROL_BASE_IDX                                                                      2
>+#define mmCM3_CM_ICSC_CONTROL                                                                          0x115c
>+#define mmCM3_CM_ICSC_CONTROL_BASE_IDX                                                                 2
>+#define mmCM3_CM_ICSC_C11_C12                                                                          0x115d
>+#define mmCM3_CM_ICSC_C11_C12_BASE_IDX                                                                 2
>+#define mmCM3_CM_ICSC_C13_C14                                                                          0x115e
>+#define mmCM3_CM_ICSC_C13_C14_BASE_IDX                                                                 2
>+#define mmCM3_CM_ICSC_C21_C22                                                                          0x115f
>+#define mmCM3_CM_ICSC_C21_C22_BASE_IDX                                                                 2
>+#define mmCM3_CM_ICSC_C23_C24                                                                          0x1160
>+#define mmCM3_CM_ICSC_C23_C24_BASE_IDX                                                                 2
>+#define mmCM3_CM_ICSC_C31_C32                                                                          0x1161
>+#define mmCM3_CM_ICSC_C31_C32_BASE_IDX                                                                 2
>+#define mmCM3_CM_ICSC_C33_C34                                                                          0x1162
>+#define mmCM3_CM_ICSC_C33_C34_BASE_IDX                                                                 2
>+#define mmCM3_CM_ICSC_B_C11_C12                                                                        0x1163
>+#define mmCM3_CM_ICSC_B_C11_C12_BASE_IDX                                                               2
>+#define mmCM3_CM_ICSC_B_C13_C14                                                                        0x1164
>+#define mmCM3_CM_ICSC_B_C13_C14_BASE_IDX                                                               2
>+#define mmCM3_CM_ICSC_B_C21_C22                                                                        0x1165
>+#define mmCM3_CM_ICSC_B_C21_C22_BASE_IDX                                                               2
>+#define mmCM3_CM_ICSC_B_C23_C24                                                                        0x1166
>+#define mmCM3_CM_ICSC_B_C23_C24_BASE_IDX                                                               2
>+#define mmCM3_CM_ICSC_B_C31_C32                                                                        0x1167
>+#define mmCM3_CM_ICSC_B_C31_C32_BASE_IDX                                                               2
>+#define mmCM3_CM_ICSC_B_C33_C34                                                                        0x1168
>+#define mmCM3_CM_ICSC_B_C33_C34_BASE_IDX                                                               2
>+#define mmCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x1169
>+#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
>+#define mmCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x116a
>+#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
>+#define mmCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x116b
>+#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
>+#define mmCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x116c
>+#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
>+#define mmCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x116d
>+#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
>+#define mmCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x116e
>+#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
>+#define mmCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x116f
>+#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
>+#define mmCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1170
>+#define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
>+#define mmCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1171
>+#define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
>+#define mmCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1172
>+#define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
>+#define mmCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1173
>+#define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
>+#define mmCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x1174
>+#define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
>+#define mmCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1175
>+#define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
>+#define mmCM3_CM_BIAS_CR_R                                                                             0x1176
>+#define mmCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
>+#define mmCM3_CM_BIAS_Y_G_CB_B                                                                         0x1177
>+#define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
>+#define mmCM3_CM_DGAM_CONTROL                                                                          0x1178
>+#define mmCM3_CM_DGAM_CONTROL_BASE_IDX                                                                 2
>+#define mmCM3_CM_DGAM_LUT_INDEX                                                                        0x1179
>+#define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX                                                               2
>+#define mmCM3_CM_DGAM_LUT_DATA                                                                         0x117a
>+#define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX                                                                2
>+#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK                                                                0x117b
>+#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMA_START_CNTL_B                                                                0x117c
>+#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMA_START_CNTL_G                                                                0x117d
>+#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMA_START_CNTL_R                                                                0x117e
>+#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B                                                                0x117f
>+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G                                                                0x1180
>+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R                                                                0x1181
>+#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B                                                                 0x1182
>+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX                                                        2
>+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B                                                                 0x1183
>+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX                                                        2
>+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G                                                                 0x1184
>+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX                                                        2
>+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G                                                                 0x1185
>+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX                                                        2
>+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R                                                                 0x1186
>+#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX                                                        2
>+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R                                                                 0x1187
>+#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX                                                        2
>+#define mmCM3_CM_DGAM_RAMA_REGION_0_1                                                                  0x1188
>+#define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX                                                         2
>+#define mmCM3_CM_DGAM_RAMA_REGION_2_3                                                                  0x1189
>+#define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX                                                         2
>+#define mmCM3_CM_DGAM_RAMA_REGION_4_5                                                                  0x118a
>+#define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX                                                         2
>+#define mmCM3_CM_DGAM_RAMA_REGION_6_7                                                                  0x118b
>+#define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX                                                         2
>+#define mmCM3_CM_DGAM_RAMA_REGION_8_9                                                                  0x118c
>+#define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX                                                         2
>+#define mmCM3_CM_DGAM_RAMA_REGION_10_11                                                                0x118d
>+#define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMA_REGION_12_13                                                                0x118e
>+#define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMA_REGION_14_15                                                                0x118f
>+#define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMB_START_CNTL_B                                                                0x1190
>+#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMB_START_CNTL_G                                                                0x1191
>+#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMB_START_CNTL_R                                                                0x1192
>+#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B                                                                0x1193
>+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G                                                                0x1194
>+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R                                                                0x1195
>+#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B                                                                 0x1196
>+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX                                                        2
>+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B                                                                 0x1197
>+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX                                                        2
>+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G                                                                 0x1198
>+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX                                                        2
>+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G                                                                 0x1199
>+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX                                                        2
>+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R                                                                 0x119a
>+#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX                                                        2
>+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R                                                                 0x119b
>+#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX                                                        2
>+#define mmCM3_CM_DGAM_RAMB_REGION_0_1                                                                  0x119c
>+#define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX                                                         2
>+#define mmCM3_CM_DGAM_RAMB_REGION_2_3                                                                  0x119d
>+#define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX                                                         2
>+#define mmCM3_CM_DGAM_RAMB_REGION_4_5                                                                  0x119e
>+#define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX                                                         2
>+#define mmCM3_CM_DGAM_RAMB_REGION_6_7                                                                  0x119f
>+#define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX                                                         2
>+#define mmCM3_CM_DGAM_RAMB_REGION_8_9                                                                  0x11a0
>+#define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX                                                         2
>+#define mmCM3_CM_DGAM_RAMB_REGION_10_11                                                                0x11a1
>+#define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMB_REGION_12_13                                                                0x11a2
>+#define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX                                                       2
>+#define mmCM3_CM_DGAM_RAMB_REGION_14_15                                                                0x11a3
>+#define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX                                                       2
>+#define mmCM3_CM_BLNDGAM_CONTROL                                                                       0x11a4
>+#define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
>+#define mmCM3_CM_BLNDGAM_LUT_INDEX                                                                     0x11a5
>+#define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
>+#define mmCM3_CM_BLNDGAM_LUT_DATA                                                                      0x11a6
>+#define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
>+#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK                                                             0x11a7
>+#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x11a8
>+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x11a9
>+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x11aa
>+#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B                                                             0x11ab
>+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G                                                             0x11ac
>+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R                                                             0x11ad
>+#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x11ae
>+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
>+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x11af
>+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
>+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x11b0
>+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
>+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x11b1
>+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
>+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x11b2
>+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
>+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x11b3
>+#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x11b4
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x11b5
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x11b6
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x11b7
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x11b8
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x11b9
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x11ba
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x11bb
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x11bc
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x11bd
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x11be
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x11bf
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x11c0
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x11c1
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x11c2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x11c3
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x11c4
>+#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x11c5
>+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x11c6
>+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x11c7
>+#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B                                                             0x11c8
>+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G                                                             0x11c9
>+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R                                                             0x11ca
>+#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x11cb
>+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
>+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x11cc
>+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
>+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x11cd
>+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
>+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x11ce
>+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
>+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x11cf
>+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
>+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x11d0
>+#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x11d1
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x11d2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x11d3
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x11d4
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x11d5
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x11d6
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x11d7
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x11d8
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x11d9
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x11da
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x11db
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x11dc
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x11dd
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x11de
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x11df
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x11e0
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x11e1
>+#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
>+#define mmCM3_CM_HDR_MULT_COEF                                                                         0x11e2
>+#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
>+#define mmCM3_CM_MEM_PWR_CTRL                                                                          0x11e3
>+#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
>+#define mmCM3_CM_MEM_PWR_STATUS                                                                        0x11e4
>+#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
>+#define mmCM3_CM_DEALPHA                                                                               0x11e6
>+#define mmCM3_CM_DEALPHA_BASE_IDX                                                                      2
>+#define mmCM3_CM_COEF_FORMAT                                                                           0x11e7
>+#define mmCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
>+#define mmCM3_CM_SHAPER_CONTROL                                                                        0x11e8
>+#define mmCM3_CM_SHAPER_CONTROL_BASE_IDX                                                               2
>+#define mmCM3_CM_SHAPER_OFFSET_R                                                                       0x11e9
>+#define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
>+#define mmCM3_CM_SHAPER_OFFSET_G                                                                       0x11ea
>+#define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
>+#define mmCM3_CM_SHAPER_OFFSET_B                                                                       0x11eb
>+#define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
>+#define mmCM3_CM_SHAPER_SCALE_R                                                                        0x11ec
>+#define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
>+#define mmCM3_CM_SHAPER_SCALE_G_B                                                                      0x11ed
>+#define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
>+#define mmCM3_CM_SHAPER_LUT_INDEX                                                                      0x11ee
>+#define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
>+#define mmCM3_CM_SHAPER_LUT_DATA                                                                       0x11ef
>+#define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
>+#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x11f0
>+#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B                                                              0x11f1
>+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G                                                              0x11f2
>+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R                                                              0x11f3
>+#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B                                                                0x11f4
>+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G                                                                0x11f5
>+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R                                                                0x11f6
>+#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_0_1                                                                0x11f7
>+#define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_2_3                                                                0x11f8
>+#define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_4_5                                                                0x11f9
>+#define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_6_7                                                                0x11fa
>+#define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_8_9                                                                0x11fb
>+#define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_10_11                                                              0x11fc
>+#define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_12_13                                                              0x11fd
>+#define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_14_15                                                              0x11fe
>+#define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_16_17                                                              0x11ff
>+#define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_18_19                                                              0x1200
>+#define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_20_21                                                              0x1201
>+#define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_22_23                                                              0x1202
>+#define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_24_25                                                              0x1203
>+#define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_26_27                                                              0x1204
>+#define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_28_29                                                              0x1205
>+#define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_30_31                                                              0x1206
>+#define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMA_REGION_32_33                                                              0x1207
>+#define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B                                                              0x1208
>+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G                                                              0x1209
>+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R                                                              0x120a
>+#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B                                                                0x120b
>+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G                                                                0x120c
>+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R                                                                0x120d
>+#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_0_1                                                                0x120e
>+#define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_2_3                                                                0x120f
>+#define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_4_5                                                                0x1210
>+#define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_6_7                                                                0x1211
>+#define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_8_9                                                                0x1212
>+#define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_10_11                                                              0x1213
>+#define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_12_13                                                              0x1214
>+#define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_14_15                                                              0x1215
>+#define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_16_17                                                              0x1216
>+#define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_18_19                                                              0x1217
>+#define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_20_21                                                              0x1218
>+#define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_22_23                                                              0x1219
>+#define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_24_25                                                              0x121a
>+#define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_26_27                                                              0x121b
>+#define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_28_29                                                              0x121c
>+#define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_30_31                                                              0x121d
>+#define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
>+#define mmCM3_CM_SHAPER_RAMB_REGION_32_33                                                              0x121e
>+#define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
>+#define mmCM3_CM_MEM_PWR_CTRL2                                                                         0x121f
>+#define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
>+#define mmCM3_CM_MEM_PWR_STATUS2                                                                       0x1220
>+#define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
>+#define mmCM3_CM_3DLUT_MODE                                                                            0x1221
>+#define mmCM3_CM_3DLUT_MODE_BASE_IDX                                                                   2
>+#define mmCM3_CM_3DLUT_INDEX                                                                           0x1222
>+#define mmCM3_CM_3DLUT_INDEX_BASE_IDX                                                                  2
>+#define mmCM3_CM_3DLUT_DATA                                                                            0x1223
>+#define mmCM3_CM_3DLUT_DATA_BASE_IDX                                                                   2
>+#define mmCM3_CM_3DLUT_DATA_30BIT                                                                      0x1224
>+#define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
>+#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL                                                              0x1225
>+#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
>+#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x1226
>+#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
>+#define mmCM3_CM_3DLUT_OUT_OFFSET_R                                                                    0x1227
>+#define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
>+#define mmCM3_CM_3DLUT_OUT_OFFSET_G                                                                    0x1228
>+#define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
>+#define mmCM3_CM_3DLUT_OUT_OFFSET_B                                                                    0x1229
>+#define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
>+#define mmCM3_CM_TEST_DEBUG_INDEX                                                                      0x122a
>+#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
>+#define mmCM3_CM_TEST_DEBUG_DATA                                                                       0x122b
>+#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x4994
>+#define mmDC_PERFMON14_PERFCOUNTER_CNTL                                                                0x1265
>+#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON14_PERFCOUNTER_CNTL2                                                               0x1266
>+#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON14_PERFCOUNTER_STATE                                                               0x1267
>+#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON14_PERFMON_CNTL                                                                    0x1268
>+#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON14_PERFMON_CNTL2                                                                   0x1269
>+#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC                                                         0x126a
>+#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON14_PERFMON_CVALUE_LOW                                                              0x126b
>+#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON14_PERFMON_HI                                                                      0x126c
>+#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON14_PERFMON_LOW                                                                     0x126d
>+#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc0_dispdec
>+// base address: 0x0
>+#define mmMPCC0_MPCC_TOP_SEL                                                                           0x1271
>+#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  2
>+#define mmMPCC0_MPCC_BOT_SEL                                                                           0x1272
>+#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  2
>+#define mmMPCC0_MPCC_OPP_ID                                                                            0x1273
>+#define mmMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   2
>+#define mmMPCC0_MPCC_CONTROL                                                                           0x1274
>+#define mmMPCC0_MPCC_CONTROL_BASE_IDX                                                                  2
>+#define mmMPCC0_MPCC_SM_CONTROL                                                                        0x1275
>+#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               2
>+#define mmMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x1276
>+#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
>+#define mmMPCC0_MPCC_TOP_GAIN                                                                          0x1277
>+#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 2
>+#define mmMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x1278
>+#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
>+#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x1279
>+#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
>+#define mmMPCC0_MPCC_BG_R_CR                                                                           0x127a
>+#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  2
>+#define mmMPCC0_MPCC_BG_G_Y                                                                            0x127b
>+#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   2
>+#define mmMPCC0_MPCC_BG_B_CB                                                                           0x127c
>+#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  2
>+#define mmMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x127d
>+#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
>+#define mmMPCC0_MPCC_STALL_STATUS                                                                      0x127e
>+#define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX                                                             2
>+#define mmMPCC0_MPCC_STATUS                                                                            0x127f
>+#define mmMPCC0_MPCC_STATUS_BASE_IDX                                                                   2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc1_dispdec
>+// base address: 0x6c
>+#define mmMPCC1_MPCC_TOP_SEL                                                                           0x128c
>+#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  2
>+#define mmMPCC1_MPCC_BOT_SEL                                                                           0x128d
>+#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  2
>+#define mmMPCC1_MPCC_OPP_ID                                                                            0x128e
>+#define mmMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   2
>+#define mmMPCC1_MPCC_CONTROL                                                                           0x128f
>+#define mmMPCC1_MPCC_CONTROL_BASE_IDX                                                                  2
>+#define mmMPCC1_MPCC_SM_CONTROL                                                                        0x1290
>+#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               2
>+#define mmMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x1291
>+#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
>+#define mmMPCC1_MPCC_TOP_GAIN                                                                          0x1292
>+#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 2
>+#define mmMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x1293
>+#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
>+#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x1294
>+#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
>+#define mmMPCC1_MPCC_BG_R_CR                                                                           0x1295
>+#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  2
>+#define mmMPCC1_MPCC_BG_G_Y                                                                            0x1296
>+#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   2
>+#define mmMPCC1_MPCC_BG_B_CB                                                                           0x1297
>+#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  2
>+#define mmMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x1298
>+#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
>+#define mmMPCC1_MPCC_STALL_STATUS                                                                      0x1299
>+#define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX                                                             2
>+#define mmMPCC1_MPCC_STATUS                                                                            0x129a
>+#define mmMPCC1_MPCC_STATUS_BASE_IDX                                                                   2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc2_dispdec
>+// base address: 0xd8
>+#define mmMPCC2_MPCC_TOP_SEL                                                                           0x12a7
>+#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  2
>+#define mmMPCC2_MPCC_BOT_SEL                                                                           0x12a8
>+#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  2
>+#define mmMPCC2_MPCC_OPP_ID                                                                            0x12a9
>+#define mmMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   2
>+#define mmMPCC2_MPCC_CONTROL                                                                           0x12aa
>+#define mmMPCC2_MPCC_CONTROL_BASE_IDX                                                                  2
>+#define mmMPCC2_MPCC_SM_CONTROL                                                                        0x12ab
>+#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               2
>+#define mmMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x12ac
>+#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
>+#define mmMPCC2_MPCC_TOP_GAIN                                                                          0x12ad
>+#define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 2
>+#define mmMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x12ae
>+#define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
>+#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x12af
>+#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
>+#define mmMPCC2_MPCC_BG_R_CR                                                                           0x12b0
>+#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  2
>+#define mmMPCC2_MPCC_BG_G_Y                                                                            0x12b1
>+#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   2
>+#define mmMPCC2_MPCC_BG_B_CB                                                                           0x12b2
>+#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  2
>+#define mmMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x12b3
>+#define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
>+#define mmMPCC2_MPCC_STALL_STATUS                                                                      0x12b4
>+#define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX                                                             2
>+#define mmMPCC2_MPCC_STATUS                                                                            0x12b5
>+#define mmMPCC2_MPCC_STATUS_BASE_IDX                                                                   2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc3_dispdec
>+// base address: 0x144
>+#define mmMPCC3_MPCC_TOP_SEL                                                                           0x12c2
>+#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  2
>+#define mmMPCC3_MPCC_BOT_SEL                                                                           0x12c3
>+#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  2
>+#define mmMPCC3_MPCC_OPP_ID                                                                            0x12c4
>+#define mmMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   2
>+#define mmMPCC3_MPCC_CONTROL                                                                           0x12c5
>+#define mmMPCC3_MPCC_CONTROL_BASE_IDX                                                                  2
>+#define mmMPCC3_MPCC_SM_CONTROL                                                                        0x12c6
>+#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               2
>+#define mmMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x12c7
>+#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
>+#define mmMPCC3_MPCC_TOP_GAIN                                                                          0x12c8
>+#define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 2
>+#define mmMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x12c9
>+#define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
>+#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x12ca
>+#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
>+#define mmMPCC3_MPCC_BG_R_CR                                                                           0x12cb
>+#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  2
>+#define mmMPCC3_MPCC_BG_G_Y                                                                            0x12cc
>+#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   2
>+#define mmMPCC3_MPCC_BG_B_CB                                                                           0x12cd
>+#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  2
>+#define mmMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x12ce
>+#define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
>+#define mmMPCC3_MPCC_STALL_STATUS                                                                      0x12cf
>+#define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX                                                             2
>+#define mmMPCC3_MPCC_STATUS                                                                            0x12d0
>+#define mmMPCC3_MPCC_STATUS_BASE_IDX                                                                   2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc4_dispdec
>+// base address: 0x1b0
>+#define mmMPCC4_MPCC_TOP_SEL                                                                           0x12dd
>+#define mmMPCC4_MPCC_TOP_SEL_BASE_IDX                                                                  2
>+#define mmMPCC4_MPCC_BOT_SEL                                                                           0x12de
>+#define mmMPCC4_MPCC_BOT_SEL_BASE_IDX                                                                  2
>+#define mmMPCC4_MPCC_OPP_ID                                                                            0x12df
>+#define mmMPCC4_MPCC_OPP_ID_BASE_IDX                                                                   2
>+#define mmMPCC4_MPCC_CONTROL                                                                           0x12e0
>+#define mmMPCC4_MPCC_CONTROL_BASE_IDX                                                                  2
>+#define mmMPCC4_MPCC_SM_CONTROL                                                                        0x12e1
>+#define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX                                                               2
>+#define mmMPCC4_MPCC_UPDATE_LOCK_SEL                                                                   0x12e2
>+#define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
>+#define mmMPCC4_MPCC_TOP_GAIN                                                                          0x12e3
>+#define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX                                                                 2
>+#define mmMPCC4_MPCC_BOT_GAIN_INSIDE                                                                   0x12e4
>+#define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
>+#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE                                                                  0x12e5
>+#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
>+#define mmMPCC4_MPCC_BG_R_CR                                                                           0x12e6
>+#define mmMPCC4_MPCC_BG_R_CR_BASE_IDX                                                                  2
>+#define mmMPCC4_MPCC_BG_G_Y                                                                            0x12e7
>+#define mmMPCC4_MPCC_BG_G_Y_BASE_IDX                                                                   2
>+#define mmMPCC4_MPCC_BG_B_CB                                                                           0x12e8
>+#define mmMPCC4_MPCC_BG_B_CB_BASE_IDX                                                                  2
>+#define mmMPCC4_MPCC_MEM_PWR_CTRL                                                                      0x12e9
>+#define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
>+#define mmMPCC4_MPCC_STALL_STATUS                                                                      0x12ea
>+#define mmMPCC4_MPCC_STALL_STATUS_BASE_IDX                                                             2
>+#define mmMPCC4_MPCC_STATUS                                                                            0x12eb
>+#define mmMPCC4_MPCC_STATUS_BASE_IDX                                                                   2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc5_dispdec
>+// base address: 0x21c
>+#define mmMPCC5_MPCC_TOP_SEL                                                                           0x12f8
>+#define mmMPCC5_MPCC_TOP_SEL_BASE_IDX                                                                  2
>+#define mmMPCC5_MPCC_BOT_SEL                                                                           0x12f9
>+#define mmMPCC5_MPCC_BOT_SEL_BASE_IDX                                                                  2
>+#define mmMPCC5_MPCC_OPP_ID                                                                            0x12fa
>+#define mmMPCC5_MPCC_OPP_ID_BASE_IDX                                                                   2
>+#define mmMPCC5_MPCC_CONTROL                                                                           0x12fb
>+#define mmMPCC5_MPCC_CONTROL_BASE_IDX                                                                  2
>+#define mmMPCC5_MPCC_SM_CONTROL                                                                        0x12fc
>+#define mmMPCC5_MPCC_SM_CONTROL_BASE_IDX                                                               2
>+#define mmMPCC5_MPCC_UPDATE_LOCK_SEL                                                                   0x12fd
>+#define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
>+#define mmMPCC5_MPCC_TOP_GAIN                                                                          0x12fe
>+#define mmMPCC5_MPCC_TOP_GAIN_BASE_IDX                                                                 2
>+#define mmMPCC5_MPCC_BOT_GAIN_INSIDE                                                                   0x12ff
>+#define mmMPCC5_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
>+#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE                                                                  0x1300
>+#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
>+#define mmMPCC5_MPCC_BG_R_CR                                                                           0x1301
>+#define mmMPCC5_MPCC_BG_R_CR_BASE_IDX                                                                  2
>+#define mmMPCC5_MPCC_BG_G_Y                                                                            0x1302
>+#define mmMPCC5_MPCC_BG_G_Y_BASE_IDX                                                                   2
>+#define mmMPCC5_MPCC_BG_B_CB                                                                           0x1303
>+#define mmMPCC5_MPCC_BG_B_CB_BASE_IDX                                                                  2
>+#define mmMPCC5_MPCC_MEM_PWR_CTRL                                                                      0x1304
>+#define mmMPCC5_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
>+#define mmMPCC5_MPCC_STALL_STATUS                                                                      0x1305
>+#define mmMPCC5_MPCC_STALL_STATUS_BASE_IDX                                                             2
>+#define mmMPCC5_MPCC_STATUS                                                                            0x1306
>+#define mmMPCC5_MPCC_STATUS_BASE_IDX                                                                   2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc6_dispdec
>+// base address: 0x288
>+#define mmMPCC6_MPCC_TOP_SEL                                                                           0x1313
>+#define mmMPCC6_MPCC_TOP_SEL_BASE_IDX                                                                  2
>+#define mmMPCC6_MPCC_BOT_SEL                                                                           0x1314
>+#define mmMPCC6_MPCC_BOT_SEL_BASE_IDX                                                                  2
>+#define mmMPCC6_MPCC_OPP_ID                                                                            0x1315
>+#define mmMPCC6_MPCC_OPP_ID_BASE_IDX                                                                   2
>+#define mmMPCC6_MPCC_CONTROL                                                                           0x1316
>+#define mmMPCC6_MPCC_CONTROL_BASE_IDX                                                                  2
>+#define mmMPCC6_MPCC_SM_CONTROL                                                                        0x1317
>+#define mmMPCC6_MPCC_SM_CONTROL_BASE_IDX                                                               2
>+#define mmMPCC6_MPCC_UPDATE_LOCK_SEL                                                                   0x1318
>+#define mmMPCC6_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
>+#define mmMPCC6_MPCC_TOP_GAIN                                                                          0x1319
>+#define mmMPCC6_MPCC_TOP_GAIN_BASE_IDX                                                                 2
>+#define mmMPCC6_MPCC_BOT_GAIN_INSIDE                                                                   0x131a
>+#define mmMPCC6_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
>+#define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE                                                                  0x131b
>+#define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
>+#define mmMPCC6_MPCC_BG_R_CR                                                                           0x131c
>+#define mmMPCC6_MPCC_BG_R_CR_BASE_IDX                                                                  2
>+#define mmMPCC6_MPCC_BG_G_Y                                                                            0x131d
>+#define mmMPCC6_MPCC_BG_G_Y_BASE_IDX                                                                   2
>+#define mmMPCC6_MPCC_BG_B_CB                                                                           0x131e
>+#define mmMPCC6_MPCC_BG_B_CB_BASE_IDX                                                                  2
>+#define mmMPCC6_MPCC_MEM_PWR_CTRL                                                                      0x131f
>+#define mmMPCC6_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
>+#define mmMPCC6_MPCC_STALL_STATUS                                                                      0x1320
>+#define mmMPCC6_MPCC_STALL_STATUS_BASE_IDX                                                             2
>+#define mmMPCC6_MPCC_STATUS                                                                            0x1321
>+#define mmMPCC6_MPCC_STATUS_BASE_IDX                                                                   2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc7_dispdec
>+// base address: 0x2f4
>+#define mmMPCC7_MPCC_TOP_SEL                                                                           0x132e
>+#define mmMPCC7_MPCC_TOP_SEL_BASE_IDX                                                                  2
>+#define mmMPCC7_MPCC_BOT_SEL                                                                           0x132f
>+#define mmMPCC7_MPCC_BOT_SEL_BASE_IDX                                                                  2
>+#define mmMPCC7_MPCC_OPP_ID                                                                            0x1330
>+#define mmMPCC7_MPCC_OPP_ID_BASE_IDX                                                                   2
>+#define mmMPCC7_MPCC_CONTROL                                                                           0x1331
>+#define mmMPCC7_MPCC_CONTROL_BASE_IDX                                                                  2
>+#define mmMPCC7_MPCC_SM_CONTROL                                                                        0x1332
>+#define mmMPCC7_MPCC_SM_CONTROL_BASE_IDX                                                               2
>+#define mmMPCC7_MPCC_UPDATE_LOCK_SEL                                                                   0x1333
>+#define mmMPCC7_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          2
>+#define mmMPCC7_MPCC_TOP_GAIN                                                                          0x1334
>+#define mmMPCC7_MPCC_TOP_GAIN_BASE_IDX                                                                 2
>+#define mmMPCC7_MPCC_BOT_GAIN_INSIDE                                                                   0x1335
>+#define mmMPCC7_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          2
>+#define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE                                                                  0x1336
>+#define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         2
>+#define mmMPCC7_MPCC_BG_R_CR                                                                           0x1337
>+#define mmMPCC7_MPCC_BG_R_CR_BASE_IDX                                                                  2
>+#define mmMPCC7_MPCC_BG_G_Y                                                                            0x1338
>+#define mmMPCC7_MPCC_BG_G_Y_BASE_IDX                                                                   2
>+#define mmMPCC7_MPCC_BG_B_CB                                                                           0x1339
>+#define mmMPCC7_MPCC_BG_B_CB_BASE_IDX                                                                  2
>+#define mmMPCC7_MPCC_MEM_PWR_CTRL                                                                      0x133a
>+#define mmMPCC7_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             2
>+#define mmMPCC7_MPCC_STALL_STATUS                                                                      0x133b
>+#define mmMPCC7_MPCC_STALL_STATUS_BASE_IDX                                                             2
>+#define mmMPCC7_MPCC_STATUS                                                                            0x133c
>+#define mmMPCC7_MPCC_STATUS_BASE_IDX                                                                   2
>+
>+
>+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
>+// base address: 0x0
>+#define mmMPC_CLOCK_CONTROL                                                                            0x1349
>+#define mmMPC_CLOCK_CONTROL_BASE_IDX                                                                   2
>+#define mmMPC_SOFT_RESET                                                                               0x134a
>+#define mmMPC_SOFT_RESET_BASE_IDX                                                                      2
>+#define mmMPC_CRC_CTRL                                                                                 0x134b
>+#define mmMPC_CRC_CTRL_BASE_IDX                                                                        2
>+#define mmMPC_CRC_SEL_CONTROL                                                                          0x134c
>+#define mmMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 2
>+#define mmMPC_CRC_RESULT_AR                                                                            0x134d
>+#define mmMPC_CRC_RESULT_AR_BASE_IDX                                                                   2
>+#define mmMPC_CRC_RESULT_GB                                                                            0x134e
>+#define mmMPC_CRC_RESULT_GB_BASE_IDX                                                                   2
>+#define mmMPC_CRC_RESULT_C                                                                             0x134f
>+#define mmMPC_CRC_RESULT_C_BASE_IDX                                                                    2
>+#define mmMPC_PERFMON_EVENT_CTRL                                                                       0x1352
>+#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX                                                              2
>+#define mmMPC_BYPASS_BG_AR                                                                             0x1353
>+#define mmMPC_BYPASS_BG_AR_BASE_IDX                                                                    2
>+#define mmMPC_BYPASS_BG_GB                                                                             0x1354
>+#define mmMPC_BYPASS_BG_GB_BASE_IDX                                                                    2
>+#define mmMPC_STALL_GRACE_WINDOW                                                                       0x1355
>+#define mmMPC_STALL_GRACE_WINDOW_BASE_IDX                                                              2
>+#define mmMPC_HOST_READ_CONTROL                                                                        0x1356
>+#define mmMPC_HOST_READ_CONTROL_BASE_IDX                                                               2
>+#define mmMPC_PENDING_TAKEN_STATUS_REG1                                                                0x1357
>+#define mmMPC_PENDING_TAKEN_STATUS_REG1_BASE_IDX                                                       2
>+#define mmMPC_PENDING_TAKEN_STATUS_REG3                                                                0x1359
>+#define mmMPC_PENDING_TAKEN_STATUS_REG3_BASE_IDX                                                       2
>+#define mmMPC_UPDATE_ACK_REG5                                                                          0x135b
>+#define mmMPC_UPDATE_ACK_REG5_BASE_IDX                                                                 2
>+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x135d
>+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       2
>+#define mmADR_CFG_VUPDATE_LOCK_SET0                                                                    0x135e
>+#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           2
>+#define mmADR_VUPDATE_LOCK_SET0                                                                        0x135f
>+#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               2
>+#define mmCFG_VUPDATE_LOCK_SET0                                                                        0x1360
>+#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               2
>+#define mmCUR_VUPDATE_LOCK_SET0                                                                        0x1361
>+#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               2
>+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x1362
>+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       2
>+#define mmADR_CFG_VUPDATE_LOCK_SET1                                                                    0x1363
>+#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           2
>+#define mmADR_VUPDATE_LOCK_SET1                                                                        0x1364
>+#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               2
>+#define mmCFG_VUPDATE_LOCK_SET1                                                                        0x1365
>+#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               2
>+#define mmCUR_VUPDATE_LOCK_SET1                                                                        0x1366
>+#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               2
>+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x1367
>+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       2
>+#define mmADR_CFG_VUPDATE_LOCK_SET2                                                                    0x1368
>+#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           2
>+#define mmADR_VUPDATE_LOCK_SET2                                                                        0x1369
>+#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               2
>+#define mmCFG_VUPDATE_LOCK_SET2                                                                        0x136a
>+#define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               2
>+#define mmCUR_VUPDATE_LOCK_SET2                                                                        0x136b
>+#define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               2
>+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x136c
>+#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       2
>+#define mmADR_CFG_VUPDATE_LOCK_SET3                                                                    0x136d
>+#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           2
>+#define mmADR_VUPDATE_LOCK_SET3                                                                        0x136e
>+#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               2
>+#define mmCFG_VUPDATE_LOCK_SET3                                                                        0x136f
>+#define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               2
>+#define mmCUR_VUPDATE_LOCK_SET3                                                                        0x1370
>+#define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               2
>+#define mmMPC_OUT0_MUX                                                                                 0x1385
>+#define mmMPC_OUT0_MUX_BASE_IDX                                                                        2
>+#define mmMPC_OUT0_DENORM_CONTROL                                                                      0x1386
>+#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             2
>+#define mmMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x1387
>+#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           2
>+#define mmMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x1388
>+#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          2
>+#define mmMPC_OUT1_MUX                                                                                 0x1389
>+#define mmMPC_OUT1_MUX_BASE_IDX                                                                        2
>+#define mmMPC_OUT1_DENORM_CONTROL                                                                      0x138a
>+#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             2
>+#define mmMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x138b
>+#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           2
>+#define mmMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x138c
>+#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          2
>+#define mmMPC_OUT2_MUX                                                                                 0x138d
>+#define mmMPC_OUT2_MUX_BASE_IDX                                                                        2
>+#define mmMPC_OUT2_DENORM_CONTROL                                                                      0x138e
>+#define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             2
>+#define mmMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x138f
>+#define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           2
>+#define mmMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x1390
>+#define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          2
>+#define mmMPC_OUT3_MUX                                                                                 0x1391
>+#define mmMPC_OUT3_MUX_BASE_IDX                                                                        2
>+#define mmMPC_OUT3_DENORM_CONTROL                                                                      0x1392
>+#define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             2
>+#define mmMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x1393
>+#define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           2
>+#define mmMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x1394
>+#define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
>+// base address: 0x0
>+#define mmMPCC_OGAM0_MPCC_OGAM_MODE                                                                    0x13ae
>+#define mmMPCC_OGAM0_MPCC_OGAM_MODE_BASE_IDX                                                           2
>+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x13af
>+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
>+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x13b0
>+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
>+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x13b1
>+#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x13b2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x13b3
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x13b4
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x13b5
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x13b6
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x13b7
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x13b8
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x13b9
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x13ba
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x13bb
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x13bc
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x13bd
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x13be
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x13bf
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x13c0
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x13c1
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x13c2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x13c3
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x13c4
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x13c5
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x13c6
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x13c7
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x13c8
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x13c9
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x13ca
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x13cb
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x13cc
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x13cd
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x13ce
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x13cf
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x13d0
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x13d1
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x13d2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x13d3
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x13d4
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x13d5
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x13d6
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x13d7
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x13d8
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x13d9
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x13da
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x13db
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x13dc
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x13dd
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x13de
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x13df
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x13e0
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x13e1
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x13e2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x13e3
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x13e4
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x13e5
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x13e6
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x13e7
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x13e8
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x13e9
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x13ea
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x13eb
>+#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
>+// base address: 0x104
>+#define mmMPCC_OGAM1_MPCC_OGAM_MODE                                                                    0x13ef
>+#define mmMPCC_OGAM1_MPCC_OGAM_MODE_BASE_IDX                                                           2
>+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x13f0
>+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
>+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x13f1
>+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
>+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x13f2
>+#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x13f3
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x13f4
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x13f5
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x13f6
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x13f7
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x13f8
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x13f9
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x13fa
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x13fb
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x13fc
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x13fd
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x13fe
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x13ff
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1400
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1401
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1402
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1403
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1404
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x1405
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x1406
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x1407
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x1408
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x1409
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x140a
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x140b
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x140c
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x140d
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x140e
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x140f
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1410
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1411
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1412
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1413
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1414
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x1415
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x1416
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x1417
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x1418
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x1419
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x141a
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x141b
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x141c
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x141d
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x141e
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x141f
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x1420
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x1421
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x1422
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x1423
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x1424
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x1425
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x1426
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x1427
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x1428
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x1429
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x142a
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x142b
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x142c
>+#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
>+// base address: 0x208
>+#define mmMPCC_OGAM2_MPCC_OGAM_MODE                                                                    0x1430
>+#define mmMPCC_OGAM2_MPCC_OGAM_MODE_BASE_IDX                                                           2
>+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x1431
>+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
>+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x1432
>+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
>+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x1433
>+#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x1434
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x1435
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x1436
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x1437
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x1438
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x1439
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x143a
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x143b
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x143c
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x143d
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x143e
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x143f
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1440
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1441
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1442
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1443
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1444
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1445
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x1446
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x1447
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x1448
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x1449
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x144a
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x144b
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x144c
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x144d
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x144e
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x144f
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1450
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1451
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1452
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1453
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1454
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1455
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x1456
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x1457
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x1458
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x1459
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x145a
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x145b
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x145c
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x145d
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x145e
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x145f
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x1460
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x1461
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x1462
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x1463
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x1464
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x1465
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x1466
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x1467
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x1468
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x1469
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x146a
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x146b
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x146c
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x146d
>+#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
>+// base address: 0x30c
>+#define mmMPCC_OGAM3_MPCC_OGAM_MODE                                                                    0x1471
>+#define mmMPCC_OGAM3_MPCC_OGAM_MODE_BASE_IDX                                                           2
>+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x1472
>+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
>+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x1473
>+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
>+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x1474
>+#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x1475
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x1476
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x1477
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x1478
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x1479
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x147a
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x147b
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x147c
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x147d
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x147e
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x147f
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x1480
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1481
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1482
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1483
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1484
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1485
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1486
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x1487
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x1488
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x1489
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x148a
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x148b
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x148c
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x148d
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x148e
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x148f
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x1490
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1491
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1492
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1493
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1494
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1495
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1496
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x1497
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x1498
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x1499
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x149a
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x149b
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x149c
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x149d
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x149e
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x149f
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x14a0
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x14a1
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x14a2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x14a3
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x14a4
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x14a5
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x14a6
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x14a7
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x14a8
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x14a9
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x14aa
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x14ab
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x14ac
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x14ad
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x14ae
>+#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec
>+// base address: 0x410
>+#define mmMPCC_OGAM4_MPCC_OGAM_MODE                                                                    0x14b2
>+#define mmMPCC_OGAM4_MPCC_OGAM_MODE_BASE_IDX                                                           2
>+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX                                                               0x14b3
>+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
>+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA                                                                0x14b4
>+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
>+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x14b5
>+#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x14b6
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x14b7
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x14b8
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x14b9
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x14ba
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x14bb
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x14bc
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x14bd
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x14be
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x14bf
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x14c0
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x14c1
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1                                                         0x14c2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3                                                         0x14c3
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5                                                         0x14c4
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7                                                         0x14c5
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9                                                         0x14c6
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11                                                       0x14c7
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13                                                       0x14c8
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15                                                       0x14c9
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17                                                       0x14ca
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19                                                       0x14cb
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21                                                       0x14cc
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23                                                       0x14cd
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25                                                       0x14ce
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27                                                       0x14cf
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29                                                       0x14d0
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31                                                       0x14d1
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33                                                       0x14d2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x14d3
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x14d4
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x14d5
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x14d6
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x14d7
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x14d8
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x14d9
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x14da
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x14db
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x14dc
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x14dd
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x14de
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1                                                         0x14df
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3                                                         0x14e0
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5                                                         0x14e1
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7                                                         0x14e2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9                                                         0x14e3
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11                                                       0x14e4
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13                                                       0x14e5
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15                                                       0x14e6
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17                                                       0x14e7
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19                                                       0x14e8
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21                                                       0x14e9
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23                                                       0x14ea
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25                                                       0x14eb
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27                                                       0x14ec
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29                                                       0x14ed
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31                                                       0x14ee
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33                                                       0x14ef
>+#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec
>+// base address: 0x514
>+#define mmMPCC_OGAM5_MPCC_OGAM_MODE                                                                    0x14f3
>+#define mmMPCC_OGAM5_MPCC_OGAM_MODE_BASE_IDX                                                           2
>+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX                                                               0x14f4
>+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
>+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA                                                                0x14f5
>+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
>+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x14f6
>+#define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x14f7
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x14f8
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x14f9
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x14fa
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x14fb
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x14fc
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x14fd
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x14fe
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x14ff
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x1500
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x1501
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x1502
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1503
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1504
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1505
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1506
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1507
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1508
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13                                                       0x1509
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15                                                       0x150a
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17                                                       0x150b
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19                                                       0x150c
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21                                                       0x150d
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23                                                       0x150e
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25                                                       0x150f
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27                                                       0x1510
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29                                                       0x1511
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31                                                       0x1512
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1513
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1514
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1515
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1516
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1517
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1518
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x1519
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x151a
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x151b
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x151c
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x151d
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x151e
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x151f
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1                                                         0x1520
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3                                                         0x1521
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5                                                         0x1522
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7                                                         0x1523
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9                                                         0x1524
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11                                                       0x1525
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13                                                       0x1526
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15                                                       0x1527
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17                                                       0x1528
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19                                                       0x1529
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21                                                       0x152a
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23                                                       0x152b
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25                                                       0x152c
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27                                                       0x152d
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29                                                       0x152e
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31                                                       0x152f
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33                                                       0x1530
>+#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam6_dispdec
>+// base address: 0x618
>+#define mmMPCC_OGAM6_MPCC_OGAM_MODE                                                                    0x1534
>+#define mmMPCC_OGAM6_MPCC_OGAM_MODE_BASE_IDX                                                           2
>+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX                                                               0x1535
>+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
>+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA                                                                0x1536
>+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
>+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x1537
>+#define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x1538
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x1539
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x153a
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x153b
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x153c
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x153d
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x153e
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x153f
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x1540
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x1541
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x1542
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x1543
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1544
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1545
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1546
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1547
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1548
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11                                                       0x1549
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13                                                       0x154a
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15                                                       0x154b
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17                                                       0x154c
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19                                                       0x154d
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21                                                       0x154e
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23                                                       0x154f
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25                                                       0x1550
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27                                                       0x1551
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29                                                       0x1552
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31                                                       0x1553
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1554
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1555
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1556
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1557
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1558
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x1559
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x155a
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x155b
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x155c
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x155d
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x155e
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x155f
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x1560
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1                                                         0x1561
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3                                                         0x1562
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5                                                         0x1563
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7                                                         0x1564
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9                                                         0x1565
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11                                                       0x1566
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13                                                       0x1567
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15                                                       0x1568
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17                                                       0x1569
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19                                                       0x156a
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21                                                       0x156b
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23                                                       0x156c
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25                                                       0x156d
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27                                                       0x156e
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29                                                       0x156f
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31                                                       0x1570
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33                                                       0x1571
>+#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam7_dispdec
>+// base address: 0x71c
>+#define mmMPCC_OGAM7_MPCC_OGAM_MODE                                                                    0x1575
>+#define mmMPCC_OGAM7_MPCC_OGAM_MODE_BASE_IDX                                                           2
>+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX                                                               0x1576
>+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      2
>+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA                                                                0x1577
>+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       2
>+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL                                                         0x1578
>+#define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX                                                2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x1579
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x157a
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x157b
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B                                                       0x157c
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G                                                       0x157d
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R                                                       0x157e
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x157f
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x1580
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x1581
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x1582
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x1583
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x1584
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1                                                         0x1585
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3                                                         0x1586
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5                                                         0x1587
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7                                                         0x1588
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9                                                         0x1589
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11                                                       0x158a
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13                                                       0x158b
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15                                                       0x158c
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17                                                       0x158d
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19                                                       0x158e
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21                                                       0x158f
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23                                                       0x1590
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25                                                       0x1591
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27                                                       0x1592
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29                                                       0x1593
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31                                                       0x1594
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33                                                       0x1595
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x1596
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x1597
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x1598
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B                                                       0x1599
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G                                                       0x159a
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R                                                       0x159b
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x159c
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x159d
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x159e
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x159f
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x15a0
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x15a1
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1                                                         0x15a2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3                                                         0x15a3
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5                                                         0x15a4
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7                                                         0x15a5
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9                                                         0x15a6
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11                                                       0x15a7
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13                                                       0x15a8
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15                                                       0x15a9
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17                                                       0x15aa
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19                                                       0x15ab
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21                                                       0x15ac
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23                                                       0x15ad
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25                                                       0x15ae
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27                                                       0x15af
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29                                                       0x15b0
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31                                                       0x15b1
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33                                                       0x15b2
>+#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              2
>+
>+
>+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
>+// base address: 0x0
>+#define mmMPC_OUT_CSC_COEF_FORMAT                                                                      0x15b6
>+#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             2
>+#define mmMPC_OUT0_CSC_MODE                                                                            0x15b7
>+#define mmMPC_OUT0_CSC_MODE_BASE_IDX                                                                   2
>+#define mmMPC_OUT0_CSC_C11_C12_A                                                                       0x15b8
>+#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              2
>+#define mmMPC_OUT0_CSC_C13_C14_A                                                                       0x15b9
>+#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              2
>+#define mmMPC_OUT0_CSC_C21_C22_A                                                                       0x15ba
>+#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              2
>+#define mmMPC_OUT0_CSC_C23_C24_A                                                                       0x15bb
>+#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              2
>+#define mmMPC_OUT0_CSC_C31_C32_A                                                                       0x15bc
>+#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              2
>+#define mmMPC_OUT0_CSC_C33_C34_A                                                                       0x15bd
>+#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              2
>+#define mmMPC_OUT0_CSC_C11_C12_B                                                                       0x15be
>+#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              2
>+#define mmMPC_OUT0_CSC_C13_C14_B                                                                       0x15bf
>+#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              2
>+#define mmMPC_OUT0_CSC_C21_C22_B                                                                       0x15c0
>+#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              2
>+#define mmMPC_OUT0_CSC_C23_C24_B                                                                       0x15c1
>+#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              2
>+#define mmMPC_OUT0_CSC_C31_C32_B                                                                       0x15c2
>+#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              2
>+#define mmMPC_OUT0_CSC_C33_C34_B                                                                       0x15c3
>+#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              2
>+#define mmMPC_OUT1_CSC_MODE                                                                            0x15c4
>+#define mmMPC_OUT1_CSC_MODE_BASE_IDX                                                                   2
>+#define mmMPC_OUT1_CSC_C11_C12_A                                                                       0x15c5
>+#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              2
>+#define mmMPC_OUT1_CSC_C13_C14_A                                                                       0x15c6
>+#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              2
>+#define mmMPC_OUT1_CSC_C21_C22_A                                                                       0x15c7
>+#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              2
>+#define mmMPC_OUT1_CSC_C23_C24_A                                                                       0x15c8
>+#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              2
>+#define mmMPC_OUT1_CSC_C31_C32_A                                                                       0x15c9
>+#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              2
>+#define mmMPC_OUT1_CSC_C33_C34_A                                                                       0x15ca
>+#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              2
>+#define mmMPC_OUT1_CSC_C11_C12_B                                                                       0x15cb
>+#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              2
>+#define mmMPC_OUT1_CSC_C13_C14_B                                                                       0x15cc
>+#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              2
>+#define mmMPC_OUT1_CSC_C21_C22_B                                                                       0x15cd
>+#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              2
>+#define mmMPC_OUT1_CSC_C23_C24_B                                                                       0x15ce
>+#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              2
>+#define mmMPC_OUT1_CSC_C31_C32_B                                                                       0x15cf
>+#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              2
>+#define mmMPC_OUT1_CSC_C33_C34_B                                                                       0x15d0
>+#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              2
>+#define mmMPC_OUT2_CSC_MODE                                                                            0x15d1
>+#define mmMPC_OUT2_CSC_MODE_BASE_IDX                                                                   2
>+#define mmMPC_OUT2_CSC_C11_C12_A                                                                       0x15d2
>+#define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              2
>+#define mmMPC_OUT2_CSC_C13_C14_A                                                                       0x15d3
>+#define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              2
>+#define mmMPC_OUT2_CSC_C21_C22_A                                                                       0x15d4
>+#define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              2
>+#define mmMPC_OUT2_CSC_C23_C24_A                                                                       0x15d5
>+#define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              2
>+#define mmMPC_OUT2_CSC_C31_C32_A                                                                       0x15d6
>+#define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              2
>+#define mmMPC_OUT2_CSC_C33_C34_A                                                                       0x15d7
>+#define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              2
>+#define mmMPC_OUT2_CSC_C11_C12_B                                                                       0x15d8
>+#define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              2
>+#define mmMPC_OUT2_CSC_C13_C14_B                                                                       0x15d9
>+#define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              2
>+#define mmMPC_OUT2_CSC_C21_C22_B                                                                       0x15da
>+#define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              2
>+#define mmMPC_OUT2_CSC_C23_C24_B                                                                       0x15db
>+#define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              2
>+#define mmMPC_OUT2_CSC_C31_C32_B                                                                       0x15dc
>+#define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              2
>+#define mmMPC_OUT2_CSC_C33_C34_B                                                                       0x15dd
>+#define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              2
>+#define mmMPC_OUT3_CSC_MODE                                                                            0x15de
>+#define mmMPC_OUT3_CSC_MODE_BASE_IDX                                                                   2
>+#define mmMPC_OUT3_CSC_C11_C12_A                                                                       0x15df
>+#define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              2
>+#define mmMPC_OUT3_CSC_C13_C14_A                                                                       0x15e0
>+#define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              2
>+#define mmMPC_OUT3_CSC_C21_C22_A                                                                       0x15e1
>+#define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              2
>+#define mmMPC_OUT3_CSC_C23_C24_A                                                                       0x15e2
>+#define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              2
>+#define mmMPC_OUT3_CSC_C31_C32_A                                                                       0x15e3
>+#define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              2
>+#define mmMPC_OUT3_CSC_C33_C34_A                                                                       0x15e4
>+#define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              2
>+#define mmMPC_OUT3_CSC_C11_C12_B                                                                       0x15e5
>+#define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              2
>+#define mmMPC_OUT3_CSC_C13_C14_B                                                                       0x15e6
>+#define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              2
>+#define mmMPC_OUT3_CSC_C21_C22_B                                                                       0x15e7
>+#define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              2
>+#define mmMPC_OUT3_CSC_C23_C24_B                                                                       0x15e8
>+#define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              2
>+#define mmMPC_OUT3_CSC_C31_C32_B                                                                       0x15e9
>+#define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              2
>+#define mmMPC_OUT3_CSC_C33_C34_B                                                                       0x15ea
>+#define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x5964
>+#define mmDC_PERFMON15_PERFCOUNTER_CNTL                                                                0x1659
>+#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON15_PERFCOUNTER_CNTL2                                                               0x165a
>+#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON15_PERFCOUNTER_STATE                                                               0x165b
>+#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON15_PERFMON_CNTL                                                                    0x165c
>+#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON15_PERFMON_CNTL2                                                                   0x165d
>+#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC                                                         0x165e
>+#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON15_PERFMON_CVALUE_LOW                                                              0x165f
>+#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON15_PERFMON_HI                                                                      0x1660
>+#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON15_PERFMON_LOW                                                                     0x1661
>+#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_opp_abm0_dispdec
>+// base address: 0x0
>+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL                                                                  0x17b0
>+#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                         2
>+#define mmBL1_PWM_USER_LEVEL                                                                           0x17b1
>+#define mmBL1_PWM_USER_LEVEL_BASE_IDX                                                                  2
>+#define mmBL1_PWM_TARGET_ABM_LEVEL                                                                     0x17b2
>+#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                            2
>+#define mmBL1_PWM_CURRENT_ABM_LEVEL                                                                    0x17b3
>+#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                           2
>+#define mmBL1_PWM_FINAL_DUTY_CYCLE                                                                     0x17b4
>+#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                            2
>+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE                                                                   0x17b5
>+#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                          2
>+#define mmBL1_PWM_ABM_CNTL                                                                             0x17b6
>+#define mmBL1_PWM_ABM_CNTL_BASE_IDX                                                                    2
>+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE                                                                0x17b7
>+#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                       2
>+#define mmBL1_PWM_GRP2_REG_LOCK                                                                        0x17b8
>+#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                               2
>+#define mmDC_ABM1_CNTL                                                                                 0x17b9
>+#define mmDC_ABM1_CNTL_BASE_IDX                                                                        2
>+#define mmDC_ABM1_IPCSC_COEFF_SEL                                                                      0x17ba
>+#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                             2
>+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0                                                                   0x17bb
>+#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                          2
>+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1                                                                   0x17bc
>+#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                          2
>+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2                                                                   0x17bd
>+#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                          2
>+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3                                                                   0x17be
>+#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                          2
>+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4                                                                   0x17bf
>+#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                          2
>+#define mmDC_ABM1_ACE_THRES_12                                                                         0x17c0
>+#define mmDC_ABM1_ACE_THRES_12_BASE_IDX                                                                2
>+#define mmDC_ABM1_ACE_THRES_34                                                                         0x17c1
>+#define mmDC_ABM1_ACE_THRES_34_BASE_IDX                                                                2
>+#define mmDC_ABM1_ACE_CNTL_MISC                                                                        0x17c2
>+#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                               2
>+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS                                                               0x17c4
>+#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                      2
>+#define mmDC_ABM1_HG_MISC_CTRL                                                                         0x17c5
>+#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX                                                                2
>+#define mmDC_ABM1_LS_SUM_OF_LUMA                                                                       0x17c6
>+#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                              2
>+#define mmDC_ABM1_LS_MIN_MAX_LUMA                                                                      0x17c7
>+#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                             2
>+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                             0x17c8
>+#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                                    2
>+#define mmDC_ABM1_LS_PIXEL_COUNT                                                                       0x17c9
>+#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                              2
>+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                         0x17ca
>+#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                                2
>+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                             0x17cb
>+#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                                    2
>+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                             0x17cc
>+#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                                    2
>+#define mmDC_ABM1_HG_SAMPLE_RATE                                                                       0x17cd
>+#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                              2
>+#define mmDC_ABM1_LS_SAMPLE_RATE                                                                       0x17ce
>+#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                              2
>+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                               0x17cf
>+#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                      2
>+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                               0x17d0
>+#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                      2
>+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                              0x17d1
>+#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                     2
>+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                             0x17d2
>+#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                                    2
>+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                             0x17d3
>+#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                                    2
>+#define mmDC_ABM1_HG_RESULT_1                                                                          0x17d4
>+#define mmDC_ABM1_HG_RESULT_1_BASE_IDX                                                                 2
>+#define mmDC_ABM1_HG_RESULT_2                                                                          0x17d5
>+#define mmDC_ABM1_HG_RESULT_2_BASE_IDX                                                                 2
>+#define mmDC_ABM1_HG_RESULT_3                                                                          0x17d6
>+#define mmDC_ABM1_HG_RESULT_3_BASE_IDX                                                                 2
>+#define mmDC_ABM1_HG_RESULT_4                                                                          0x17d7
>+#define mmDC_ABM1_HG_RESULT_4_BASE_IDX                                                                 2
>+#define mmDC_ABM1_HG_RESULT_5                                                                          0x17d8
>+#define mmDC_ABM1_HG_RESULT_5_BASE_IDX                                                                 2
>+#define mmDC_ABM1_HG_RESULT_6                                                                          0x17d9
>+#define mmDC_ABM1_HG_RESULT_6_BASE_IDX                                                                 2
>+#define mmDC_ABM1_HG_RESULT_7                                                                          0x17da
>+#define mmDC_ABM1_HG_RESULT_7_BASE_IDX                                                                 2
>+#define mmDC_ABM1_HG_RESULT_8                                                                          0x17db
>+#define mmDC_ABM1_HG_RESULT_8_BASE_IDX                                                                 2
>+#define mmDC_ABM1_HG_RESULT_9                                                                          0x17dc
>+#define mmDC_ABM1_HG_RESULT_9_BASE_IDX                                                                 2
>+#define mmDC_ABM1_HG_RESULT_10                                                                         0x17dd
>+#define mmDC_ABM1_HG_RESULT_10_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_11                                                                         0x17de
>+#define mmDC_ABM1_HG_RESULT_11_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_12                                                                         0x17df
>+#define mmDC_ABM1_HG_RESULT_12_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_13                                                                         0x17e0
>+#define mmDC_ABM1_HG_RESULT_13_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_14                                                                         0x17e1
>+#define mmDC_ABM1_HG_RESULT_14_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_15                                                                         0x17e2
>+#define mmDC_ABM1_HG_RESULT_15_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_16                                                                         0x17e3
>+#define mmDC_ABM1_HG_RESULT_16_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_17                                                                         0x17e4
>+#define mmDC_ABM1_HG_RESULT_17_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_18                                                                         0x17e5
>+#define mmDC_ABM1_HG_RESULT_18_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_19                                                                         0x17e6
>+#define mmDC_ABM1_HG_RESULT_19_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_20                                                                         0x17e7
>+#define mmDC_ABM1_HG_RESULT_20_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_21                                                                         0x17e8
>+#define mmDC_ABM1_HG_RESULT_21_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_22                                                                         0x17e9
>+#define mmDC_ABM1_HG_RESULT_22_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_23                                                                         0x17ea
>+#define mmDC_ABM1_HG_RESULT_23_BASE_IDX                                                                2
>+#define mmDC_ABM1_HG_RESULT_24                                                                         0x17eb
>+#define mmDC_ABM1_HG_RESULT_24_BASE_IDX                                                                2
>+#define mmDC_ABM1_BL_MASTER_LOCK                                                                       0x17ec
>+#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_opp_fmt0_dispdec
>+// base address: 0x0
>+#define mmFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
>+#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
>+#define mmFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
>+#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
>+#define mmFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
>+#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
>+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
>+#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
>+#define mmFMT0_FMT_CONTROL                                                                             0x1840
>+#define mmFMT0_FMT_CONTROL_BASE_IDX                                                                    2
>+#define mmFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
>+#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
>+#define mmFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
>+#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
>+#define mmFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
>+#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
>+#define mmFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
>+#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
>+#define mmFMT0_FMT_CLAMP_CNTL                                                                          0x1845
>+#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
>+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
>+#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
>+#define mmFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
>+#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
>+#define mmFMT0_FMT_422_CONTROL                                                                         0x1849
>+#define mmFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
>+
>+
>+// addressBlock: dce_dc_opp_dpg0_dispdec
>+// base address: 0x0
>+#define mmDPG0_DPG_CONTROL                                                                             0x1854
>+#define mmDPG0_DPG_CONTROL_BASE_IDX                                                                    2
>+#define mmDPG0_DPG_RAMP_CONTROL                                                                        0x1855
>+#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
>+#define mmDPG0_DPG_DIMENSIONS                                                                          0x1856
>+#define mmDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
>+#define mmDPG0_DPG_COLOUR_R_CR                                                                         0x1857
>+#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
>+#define mmDPG0_DPG_COLOUR_G_Y                                                                          0x1858
>+#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
>+#define mmDPG0_DPG_COLOUR_B_CB                                                                         0x1859
>+#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
>+#define mmDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
>+#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
>+#define mmDPG0_DPG_STATUS                                                                              0x185b
>+#define mmDPG0_DPG_STATUS_BASE_IDX                                                                     2
>+
>+
>+// addressBlock: dce_dc_opp_oppbuf0_dispdec
>+// base address: 0x0
>+#define mmOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
>+#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
>+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
>+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
>+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
>+#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
>+#define mmOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
>+#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
>+// base address: 0x0
>+#define mmOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
>+#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
>+// base address: 0x0
>+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
>+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
>+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
>+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
>+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
>+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
>+#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
>+
>+
>+// addressBlock: dce_dc_opp_fmt1_dispdec
>+// base address: 0x168
>+#define mmFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
>+#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
>+#define mmFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
>+#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
>+#define mmFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
>+#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
>+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
>+#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
>+#define mmFMT1_FMT_CONTROL                                                                             0x189a
>+#define mmFMT1_FMT_CONTROL_BASE_IDX                                                                    2
>+#define mmFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
>+#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
>+#define mmFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
>+#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
>+#define mmFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
>+#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
>+#define mmFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
>+#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
>+#define mmFMT1_FMT_CLAMP_CNTL                                                                          0x189f
>+#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
>+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
>+#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
>+#define mmFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
>+#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
>+#define mmFMT1_FMT_422_CONTROL                                                                         0x18a3
>+#define mmFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
>+
>+
>+// addressBlock: dce_dc_opp_dpg1_dispdec
>+// base address: 0x168
>+#define mmDPG1_DPG_CONTROL                                                                             0x18ae
>+#define mmDPG1_DPG_CONTROL_BASE_IDX                                                                    2
>+#define mmDPG1_DPG_RAMP_CONTROL                                                                        0x18af
>+#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
>+#define mmDPG1_DPG_DIMENSIONS                                                                          0x18b0
>+#define mmDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
>+#define mmDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
>+#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
>+#define mmDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
>+#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
>+#define mmDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
>+#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
>+#define mmDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
>+#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
>+#define mmDPG1_DPG_STATUS                                                                              0x18b5
>+#define mmDPG1_DPG_STATUS_BASE_IDX                                                                     2
>+
>+
>+// addressBlock: dce_dc_opp_oppbuf1_dispdec
>+// base address: 0x168
>+#define mmOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
>+#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
>+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
>+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
>+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
>+#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
>+#define mmOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
>+#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
>+// base address: 0x168
>+#define mmOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
>+#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
>+// base address: 0x168
>+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
>+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
>+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
>+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
>+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
>+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
>+#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
>+
>+
>+// addressBlock: dce_dc_opp_fmt2_dispdec
>+// base address: 0x2d0
>+#define mmFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
>+#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
>+#define mmFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
>+#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
>+#define mmFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
>+#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
>+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
>+#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
>+#define mmFMT2_FMT_CONTROL                                                                             0x18f4
>+#define mmFMT2_FMT_CONTROL_BASE_IDX                                                                    2
>+#define mmFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
>+#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
>+#define mmFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
>+#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
>+#define mmFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
>+#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
>+#define mmFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
>+#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
>+#define mmFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
>+#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
>+#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
>+#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
>+#define mmFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
>+#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
>+#define mmFMT2_FMT_422_CONTROL                                                                         0x18fd
>+#define mmFMT2_FMT_422_CONTROL_BASE_IDX                                                                2
>+
>+
>+// addressBlock: dce_dc_opp_dpg2_dispdec
>+// base address: 0x2d0
>+#define mmDPG2_DPG_CONTROL                                                                             0x1908
>+#define mmDPG2_DPG_CONTROL_BASE_IDX                                                                    2
>+#define mmDPG2_DPG_RAMP_CONTROL                                                                        0x1909
>+#define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
>+#define mmDPG2_DPG_DIMENSIONS                                                                          0x190a
>+#define mmDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
>+#define mmDPG2_DPG_COLOUR_R_CR                                                                         0x190b
>+#define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
>+#define mmDPG2_DPG_COLOUR_G_Y                                                                          0x190c
>+#define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
>+#define mmDPG2_DPG_COLOUR_B_CB                                                                         0x190d
>+#define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
>+#define mmDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
>+#define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
>+#define mmDPG2_DPG_STATUS                                                                              0x190f
>+#define mmDPG2_DPG_STATUS_BASE_IDX                                                                     2
>+
>+
>+// addressBlock: dce_dc_opp_oppbuf2_dispdec
>+// base address: 0x2d0
>+#define mmOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
>+#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
>+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
>+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
>+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
>+#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
>+#define mmOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
>+#define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
>+// base address: 0x2d0
>+#define mmOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
>+#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
>+// base address: 0x2d0
>+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
>+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
>+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
>+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
>+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
>+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
>+#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
>+
>+
>+// addressBlock: dce_dc_opp_fmt3_dispdec
>+// base address: 0x438
>+#define mmFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
>+#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
>+#define mmFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
>+#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
>+#define mmFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
>+#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
>+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
>+#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
>+#define mmFMT3_FMT_CONTROL                                                                             0x194e
>+#define mmFMT3_FMT_CONTROL_BASE_IDX                                                                    2
>+#define mmFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
>+#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
>+#define mmFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
>+#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
>+#define mmFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
>+#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
>+#define mmFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
>+#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
>+#define mmFMT3_FMT_CLAMP_CNTL                                                                          0x1953
>+#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
>+#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
>+#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
>+#define mmFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
>+#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
>+#define mmFMT3_FMT_422_CONTROL                                                                         0x1957
>+#define mmFMT3_FMT_422_CONTROL_BASE_IDX                                                                2
>+
>+
>+// addressBlock: dce_dc_opp_dpg3_dispdec
>+// base address: 0x438
>+#define mmDPG3_DPG_CONTROL                                                                             0x1962
>+#define mmDPG3_DPG_CONTROL_BASE_IDX                                                                    2
>+#define mmDPG3_DPG_RAMP_CONTROL                                                                        0x1963
>+#define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
>+#define mmDPG3_DPG_DIMENSIONS                                                                          0x1964
>+#define mmDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
>+#define mmDPG3_DPG_COLOUR_R_CR                                                                         0x1965
>+#define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
>+#define mmDPG3_DPG_COLOUR_G_Y                                                                          0x1966
>+#define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
>+#define mmDPG3_DPG_COLOUR_B_CB                                                                         0x1967
>+#define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
>+#define mmDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
>+#define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
>+#define mmDPG3_DPG_STATUS                                                                              0x1969
>+#define mmDPG3_DPG_STATUS_BASE_IDX                                                                     2
>+
>+
>+// addressBlock: dce_dc_opp_oppbuf3_dispdec
>+// base address: 0x438
>+#define mmOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
>+#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
>+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
>+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
>+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
>+#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
>+#define mmOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
>+#define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
>+// base address: 0x438
>+#define mmOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
>+#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
>+// base address: 0x438
>+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
>+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
>+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
>+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
>+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
>+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
>+#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
>+
>+
>+// addressBlock: dce_dc_opp_fmt4_dispdec
>+// base address: 0x5a0
>+#define mmFMT4_FMT_CLAMP_COMPONENT_R                                                                   0x19a4
>+#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
>+#define mmFMT4_FMT_CLAMP_COMPONENT_G                                                                   0x19a5
>+#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
>+#define mmFMT4_FMT_CLAMP_COMPONENT_B                                                                   0x19a6
>+#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
>+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL                                                                    0x19a7
>+#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
>+#define mmFMT4_FMT_CONTROL                                                                             0x19a8
>+#define mmFMT4_FMT_CONTROL_BASE_IDX                                                                    2
>+#define mmFMT4_FMT_BIT_DEPTH_CONTROL                                                                   0x19a9
>+#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
>+#define mmFMT4_FMT_DITHER_RAND_R_SEED                                                                  0x19aa
>+#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
>+#define mmFMT4_FMT_DITHER_RAND_G_SEED                                                                  0x19ab
>+#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
>+#define mmFMT4_FMT_DITHER_RAND_B_SEED                                                                  0x19ac
>+#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
>+#define mmFMT4_FMT_CLAMP_CNTL                                                                          0x19ad
>+#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
>+#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x19ae
>+#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
>+#define mmFMT4_FMT_MAP420_MEMORY_CONTROL                                                               0x19af
>+#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
>+#define mmFMT4_FMT_422_CONTROL                                                                         0x19b1
>+#define mmFMT4_FMT_422_CONTROL_BASE_IDX                                                                2
>+
>+
>+// addressBlock: dce_dc_opp_dpg4_dispdec
>+// base address: 0x5a0
>+#define mmDPG4_DPG_CONTROL                                                                             0x19bc
>+#define mmDPG4_DPG_CONTROL_BASE_IDX                                                                    2
>+#define mmDPG4_DPG_RAMP_CONTROL                                                                        0x19bd
>+#define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX                                                               2
>+#define mmDPG4_DPG_DIMENSIONS                                                                          0x19be
>+#define mmDPG4_DPG_DIMENSIONS_BASE_IDX                                                                 2
>+#define mmDPG4_DPG_COLOUR_R_CR                                                                         0x19bf
>+#define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX                                                                2
>+#define mmDPG4_DPG_COLOUR_G_Y                                                                          0x19c0
>+#define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
>+#define mmDPG4_DPG_COLOUR_B_CB                                                                         0x19c1
>+#define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX                                                                2
>+#define mmDPG4_DPG_OFFSET_SEGMENT                                                                      0x19c2
>+#define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
>+#define mmDPG4_DPG_STATUS                                                                              0x19c3
>+#define mmDPG4_DPG_STATUS_BASE_IDX                                                                     2
>+
>+
>+// addressBlock: dce_dc_opp_oppbuf4_dispdec
>+// base address: 0x5a0
>+#define mmOPPBUF4_OPPBUF_CONTROL                                                                       0x19ec
>+#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX                                                              2
>+#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0                                                               0x19ed
>+#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
>+#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1                                                               0x19ee
>+#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
>+#define mmOPPBUF4_OPPBUF_CONTROL1                                                                      0x19f1
>+#define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe4_dispdec
>+// base address: 0x5a0
>+#define mmOPP_PIPE4_OPP_PIPE_CONTROL                                                                   0x19f4
>+#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
>+// base address: 0x5a0
>+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL                                                           0x19f9
>+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK                                                              0x19fa
>+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
>+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0                                                           0x19fb
>+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1                                                           0x19fc
>+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2                                                           0x19fd
>+#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
>+
>+
>+// addressBlock: dce_dc_opp_fmt5_dispdec
>+// base address: 0x708
>+#define mmFMT5_FMT_CLAMP_COMPONENT_R                                                                   0x19fe
>+#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
>+#define mmFMT5_FMT_CLAMP_COMPONENT_G                                                                   0x19ff
>+#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
>+#define mmFMT5_FMT_CLAMP_COMPONENT_B                                                                   0x1a00
>+#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
>+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL                                                                    0x1a01
>+#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
>+#define mmFMT5_FMT_CONTROL                                                                             0x1a02
>+#define mmFMT5_FMT_CONTROL_BASE_IDX                                                                    2
>+#define mmFMT5_FMT_BIT_DEPTH_CONTROL                                                                   0x1a03
>+#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
>+#define mmFMT5_FMT_DITHER_RAND_R_SEED                                                                  0x1a04
>+#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
>+#define mmFMT5_FMT_DITHER_RAND_G_SEED                                                                  0x1a05
>+#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
>+#define mmFMT5_FMT_DITHER_RAND_B_SEED                                                                  0x1a06
>+#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
>+#define mmFMT5_FMT_CLAMP_CNTL                                                                          0x1a07
>+#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
>+#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1a08
>+#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
>+#define mmFMT5_FMT_MAP420_MEMORY_CONTROL                                                               0x1a09
>+#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
>+#define mmFMT5_FMT_422_CONTROL                                                                         0x1a0b
>+#define mmFMT5_FMT_422_CONTROL_BASE_IDX                                                                2
>+
>+
>+// addressBlock: dce_dc_opp_dpg5_dispdec
>+// base address: 0x708
>+#define mmDPG5_DPG_CONTROL                                                                             0x1a16
>+#define mmDPG5_DPG_CONTROL_BASE_IDX                                                                    2
>+#define mmDPG5_DPG_RAMP_CONTROL                                                                        0x1a17
>+#define mmDPG5_DPG_RAMP_CONTROL_BASE_IDX                                                               2
>+#define mmDPG5_DPG_DIMENSIONS                                                                          0x1a18
>+#define mmDPG5_DPG_DIMENSIONS_BASE_IDX                                                                 2
>+#define mmDPG5_DPG_COLOUR_R_CR                                                                         0x1a19
>+#define mmDPG5_DPG_COLOUR_R_CR_BASE_IDX                                                                2
>+#define mmDPG5_DPG_COLOUR_G_Y                                                                          0x1a1a
>+#define mmDPG5_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
>+#define mmDPG5_DPG_COLOUR_B_CB                                                                         0x1a1b
>+#define mmDPG5_DPG_COLOUR_B_CB_BASE_IDX                                                                2
>+#define mmDPG5_DPG_OFFSET_SEGMENT                                                                      0x1a1c
>+#define mmDPG5_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
>+#define mmDPG5_DPG_STATUS                                                                              0x1a1d
>+#define mmDPG5_DPG_STATUS_BASE_IDX                                                                     2
>+
>+
>+// addressBlock: dce_dc_opp_oppbuf5_dispdec
>+// base address: 0x708
>+#define mmOPPBUF5_OPPBUF_CONTROL                                                                       0x1a46
>+#define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX                                                              2
>+#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0                                                               0x1a47
>+#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
>+#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1                                                               0x1a48
>+#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
>+#define mmOPPBUF5_OPPBUF_CONTROL1                                                                      0x1a4b
>+#define mmOPPBUF5_OPPBUF_CONTROL1_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe5_dispdec
>+// base address: 0x708
>+#define mmOPP_PIPE5_OPP_PIPE_CONTROL                                                                   0x1a4e
>+#define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
>+// base address: 0x708
>+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL                                                           0x1a53
>+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK                                                              0x1a54
>+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
>+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0                                                           0x1a55
>+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1                                                           0x1a56
>+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
>+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2                                                           0x1a57
>+#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
>+
>+
>+// addressBlock: dce_dc_opp_opp_top_dispdec
>+// base address: 0x0
>+#define mmOPP_TOP_CLK_CONTROL                                                                          0x1a5e
>+#define mmOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
>+
>+
>+// addressBlock: dce_dc_opp_dscrm0_dispdec
>+// base address: 0x0
>+#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
>+#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_opp_dscrm1_dispdec
>+// base address: 0x4
>+#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
>+#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_opp_dscrm2_dispdec
>+// base address: 0x8
>+#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
>+#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_opp_dscrm3_dispdec
>+// base address: 0xc
>+#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a67
>+#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_opp_dscrm4_dispdec
>+// base address: 0x10
>+#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a68
>+#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_opp_dscrm5_dispdec
>+// base address: 0x14
>+#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a69
>+#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
>+
>+
>+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x6af8
>+#define mmDC_PERFMON16_PERFCOUNTER_CNTL                                                                0x1abe
>+#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON16_PERFCOUNTER_CNTL2                                                               0x1abf
>+#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON16_PERFCOUNTER_STATE                                                               0x1ac0
>+#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON16_PERFMON_CNTL                                                                    0x1ac1
>+#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON16_PERFMON_CNTL2                                                                   0x1ac2
>+#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC                                                         0x1ac3
>+#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON16_PERFMON_CVALUE_LOW                                                              0x1ac4
>+#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON16_PERFMON_HI                                                                      0x1ac5
>+#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON16_PERFMON_LOW                                                                     0x1ac6
>+#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_optc_odm0_dispdec
>+// base address: 0x0
>+#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
>+#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
>+#define mmODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
>+#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
>+#define mmODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
>+#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
>+#define mmODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
>+#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
>+#define mmODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
>+#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
>+#define mmODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
>+#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
>+#define mmODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
>+#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
>+#define mmODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
>+#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_optc_odm1_dispdec
>+// base address: 0x40
>+#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
>+#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
>+#define mmODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
>+#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
>+#define mmODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
>+#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
>+#define mmODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
>+#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
>+#define mmODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
>+#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
>+#define mmODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
>+#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
>+#define mmODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
>+#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
>+#define mmODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
>+#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_optc_odm2_dispdec
>+// base address: 0x80
>+#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
>+#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
>+#define mmODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
>+#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
>+#define mmODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
>+#define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
>+#define mmODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
>+#define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
>+#define mmODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
>+#define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
>+#define mmODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
>+#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
>+#define mmODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
>+#define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
>+#define mmODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
>+#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_optc_odm3_dispdec
>+// base address: 0xc0
>+#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
>+#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
>+#define mmODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
>+#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
>+#define mmODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
>+#define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
>+#define mmODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
>+#define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
>+#define mmODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
>+#define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
>+#define mmODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
>+#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
>+#define mmODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
>+#define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
>+#define mmODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
>+#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_optc_odm4_dispdec
>+// base address: 0x100
>+#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1b0a
>+#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
>+#define mmODM4_OPTC_DATA_SOURCE_SELECT                                                                 0x1b0b
>+#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
>+#define mmODM4_OPTC_DATA_FORMAT_CONTROL                                                                0x1b0c
>+#define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
>+#define mmODM4_OPTC_BYTES_PER_PIXEL                                                                    0x1b0d
>+#define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
>+#define mmODM4_OPTC_WIDTH_CONTROL                                                                      0x1b0e
>+#define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
>+#define mmODM4_OPTC_INPUT_CLOCK_CONTROL                                                                0x1b0f
>+#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
>+#define mmODM4_OPTC_MEMORY_CONFIG                                                                      0x1b10
>+#define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
>+#define mmODM4_OPTC_INPUT_SPARE_REGISTER                                                               0x1b11
>+#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_optc_odm5_dispdec
>+// base address: 0x140
>+#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1b1a
>+#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
>+#define mmODM5_OPTC_DATA_SOURCE_SELECT                                                                 0x1b1b
>+#define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
>+#define mmODM5_OPTC_DATA_FORMAT_CONTROL                                                                0x1b1c
>+#define mmODM5_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
>+#define mmODM5_OPTC_BYTES_PER_PIXEL                                                                    0x1b1d
>+#define mmODM5_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
>+#define mmODM5_OPTC_WIDTH_CONTROL                                                                      0x1b1e
>+#define mmODM5_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
>+#define mmODM5_OPTC_INPUT_CLOCK_CONTROL                                                                0x1b1f
>+#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
>+#define mmODM5_OPTC_MEMORY_CONFIG                                                                      0x1b20
>+#define mmODM5_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
>+#define mmODM5_OPTC_INPUT_SPARE_REGISTER                                                               0x1b21
>+#define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dce_dc_optc_otg0_dispdec
>+// base address: 0x0
>+#define mmOTG0_OTG_H_TOTAL                                                                             0x1b2a
>+#define mmOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
>+#define mmOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
>+#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
>+#define mmOTG0_OTG_H_SYNC_A                                                                            0x1b2c
>+#define mmOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
>+#define mmOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
>+#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
>+#define mmOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
>+#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
>+#define mmOTG0_OTG_V_TOTAL                                                                             0x1b2f
>+#define mmOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
>+#define mmOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
>+#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
>+#define mmOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
>+#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
>+#define mmOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
>+#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
>+#define mmOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
>+#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
>+#define mmOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
>+#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
>+#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
>+#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
>+#define mmOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
>+#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
>+#define mmOTG0_OTG_V_SYNC_A                                                                            0x1b37
>+#define mmOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
>+#define mmOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
>+#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
>+#define mmOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
>+#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
>+#define mmOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
>+#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
>+#define mmOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
>+#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
>+#define mmOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
>+#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
>+#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
>+#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
>+#define mmOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
>+#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
>+#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
>+#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
>+#define mmOTG0_OTG_CONTROL                                                                             0x1b41
>+#define mmOTG0_OTG_CONTROL_BASE_IDX                                                                    2
>+#define mmOTG0_OTG_BLANK_CONTROL                                                                       0x1b42
>+#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX                                                              2
>+#define mmOTG0_OTG_PIPE_ABORT_CONTROL                                                                  0x1b43
>+#define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
>+#define mmOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
>+#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
>+#define mmOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
>+#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
>+#define mmOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
>+#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
>+#define mmOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
>+#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
>+#define mmOTG0_OTG_STATUS                                                                              0x1b49
>+#define mmOTG0_OTG_STATUS_BASE_IDX                                                                     2
>+#define mmOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
>+#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
>+#define mmOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
>+#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
>+#define mmOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
>+#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
>+#define mmOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
>+#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
>+#define mmOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
>+#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
>+#define mmOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
>+#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
>+#define mmOTG0_OTG_COUNT_RESET                                                                         0x1b50
>+#define mmOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
>+#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
>+#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
>+#define mmOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
>+#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
>+#define mmOTG0_OTG_STEREO_STATUS                                                                       0x1b53
>+#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
>+#define mmOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
>+#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
>+#define mmOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
>+#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
>+#define mmOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
>+#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
>+#define mmOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
>+#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
>+#define mmOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
>+#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
>+#define mmOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
>+#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
>+#define mmOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
>+#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
>+#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
>+#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
>+#define mmOTG0_OTG_MASTER_EN                                                                           0x1b5c
>+#define mmOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
>+#define mmOTG0_OTG_BLANK_DATA_COLOR                                                                    0x1b5e
>+#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
>+#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT                                                                0x1b5f
>+#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
>+#define mmOTG0_OTG_BLACK_COLOR                                                                         0x1b60
>+#define mmOTG0_OTG_BLACK_COLOR_BASE_IDX                                                                2
>+#define mmOTG0_OTG_BLACK_COLOR_EXT                                                                     0x1b61
>+#define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
>+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
>+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
>+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
>+#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
>+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
>+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
>+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
>+#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
>+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
>+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
>+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
>+#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
>+#define mmOTG0_OTG_CRC_CNTL                                                                            0x1b68
>+#define mmOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
>+#define mmOTG0_OTG_CRC_CNTL2                                                                           0x1b69
>+#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX                                                                  2
>+#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b6a
>+#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6b
>+#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6c
>+#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6d
>+#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6e
>+#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG0_OTG_CRC0_DATA_B                                                                         0x1b6f
>+#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
>+#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b70
>+#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b71
>+#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b72
>+#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b73
>+#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG0_OTG_CRC1_DATA_RG                                                                        0x1b74
>+#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG0_OTG_CRC1_DATA_B                                                                         0x1b75
>+#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
>+#define mmOTG0_OTG_CRC2_DATA_RG                                                                        0x1b76
>+#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG0_OTG_CRC2_DATA_B                                                                         0x1b77
>+#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
>+#define mmOTG0_OTG_CRC3_DATA_RG                                                                        0x1b78
>+#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG0_OTG_CRC3_DATA_B                                                                         0x1b79
>+#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
>+#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b7a
>+#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
>+#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7b
>+#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
>+#define mmOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b82
>+#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
>+#define mmOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b83
>+#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
>+#define mmOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b84
>+#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
>+#define mmOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b85
>+#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
>+#define mmOTG0_OTG_CLOCK_CONTROL                                                                       0x1b86
>+#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
>+#define mmOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b87
>+#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
>+#define mmOTG0_OTG_VUPDATE_PARAM                                                                       0x1b88
>+#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
>+#define mmOTG0_OTG_VREADY_PARAM                                                                        0x1b89
>+#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
>+#define mmOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b8a
>+#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
>+#define mmOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8b
>+#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
>+#define mmOTG0_OTG_GSL_CONTROL                                                                         0x1b8c
>+#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
>+#define mmOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8d
>+#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
>+#define mmOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8e
>+#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
>+#define mmOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8f
>+#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
>+#define mmOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b90
>+#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
>+#define mmOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b91
>+#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
>+#define mmOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b92
>+#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
>+#define mmOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b93
>+#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
>+#define mmOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b94
>+#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
>+#define mmOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b95
>+#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
>+#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS                                                             0x1b96
>+#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
>+#define mmOTG0_OTG_DRR_CONTROL                                                                         0x1b97
>+#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
>+#define mmOTG0_OTG_REQUEST_CONTROL                                                                     0x1b98
>+#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
>+#define mmOTG0_OTG_DSC_START_POSITION                                                                  0x1b99
>+#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
>+#define mmOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1b9a
>+#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
>+#define mmOTG0_OTG_SPARE_REGISTER                                                                      0x1b9c
>+#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_optc_otg1_dispdec
>+// base address: 0x200
>+#define mmOTG1_OTG_H_TOTAL                                                                             0x1baa
>+#define mmOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
>+#define mmOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
>+#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
>+#define mmOTG1_OTG_H_SYNC_A                                                                            0x1bac
>+#define mmOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
>+#define mmOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
>+#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
>+#define mmOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
>+#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
>+#define mmOTG1_OTG_V_TOTAL                                                                             0x1baf
>+#define mmOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
>+#define mmOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
>+#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
>+#define mmOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
>+#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
>+#define mmOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
>+#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
>+#define mmOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
>+#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
>+#define mmOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
>+#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
>+#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
>+#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
>+#define mmOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
>+#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
>+#define mmOTG1_OTG_V_SYNC_A                                                                            0x1bb7
>+#define mmOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
>+#define mmOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
>+#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
>+#define mmOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
>+#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
>+#define mmOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
>+#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
>+#define mmOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
>+#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
>+#define mmOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
>+#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
>+#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
>+#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
>+#define mmOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
>+#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
>+#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
>+#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
>+#define mmOTG1_OTG_CONTROL                                                                             0x1bc1
>+#define mmOTG1_OTG_CONTROL_BASE_IDX                                                                    2
>+#define mmOTG1_OTG_BLANK_CONTROL                                                                       0x1bc2
>+#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX                                                              2
>+#define mmOTG1_OTG_PIPE_ABORT_CONTROL                                                                  0x1bc3
>+#define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
>+#define mmOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
>+#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
>+#define mmOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
>+#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
>+#define mmOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
>+#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
>+#define mmOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
>+#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
>+#define mmOTG1_OTG_STATUS                                                                              0x1bc9
>+#define mmOTG1_OTG_STATUS_BASE_IDX                                                                     2
>+#define mmOTG1_OTG_STATUS_POSITION                                                                     0x1bca
>+#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
>+#define mmOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
>+#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
>+#define mmOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
>+#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
>+#define mmOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
>+#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
>+#define mmOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
>+#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
>+#define mmOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
>+#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
>+#define mmOTG1_OTG_COUNT_RESET                                                                         0x1bd0
>+#define mmOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
>+#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
>+#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
>+#define mmOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
>+#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
>+#define mmOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
>+#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
>+#define mmOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
>+#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
>+#define mmOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
>+#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
>+#define mmOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
>+#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
>+#define mmOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
>+#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
>+#define mmOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
>+#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
>+#define mmOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
>+#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
>+#define mmOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
>+#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
>+#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
>+#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
>+#define mmOTG1_OTG_MASTER_EN                                                                           0x1bdc
>+#define mmOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
>+#define mmOTG1_OTG_BLANK_DATA_COLOR                                                                    0x1bde
>+#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
>+#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT                                                                0x1bdf
>+#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
>+#define mmOTG1_OTG_BLACK_COLOR                                                                         0x1be0
>+#define mmOTG1_OTG_BLACK_COLOR_BASE_IDX                                                                2
>+#define mmOTG1_OTG_BLACK_COLOR_EXT                                                                     0x1be1
>+#define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
>+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
>+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
>+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
>+#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
>+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
>+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
>+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
>+#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
>+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
>+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
>+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
>+#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
>+#define mmOTG1_OTG_CRC_CNTL                                                                            0x1be8
>+#define mmOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
>+#define mmOTG1_OTG_CRC_CNTL2                                                                           0x1be9
>+#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX                                                                  2
>+#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1bea
>+#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1beb
>+#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1bec
>+#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bed
>+#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG1_OTG_CRC0_DATA_RG                                                                        0x1bee
>+#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG1_OTG_CRC0_DATA_B                                                                         0x1bef
>+#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
>+#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bf0
>+#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf1
>+#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf2
>+#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf3
>+#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf4
>+#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG1_OTG_CRC1_DATA_B                                                                         0x1bf5
>+#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
>+#define mmOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf6
>+#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG1_OTG_CRC2_DATA_B                                                                         0x1bf7
>+#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
>+#define mmOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf8
>+#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG1_OTG_CRC3_DATA_B                                                                         0x1bf9
>+#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
>+#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bfa
>+#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
>+#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfb
>+#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
>+#define mmOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c02
>+#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
>+#define mmOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c03
>+#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
>+#define mmOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c04
>+#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
>+#define mmOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c05
>+#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
>+#define mmOTG1_OTG_CLOCK_CONTROL                                                                       0x1c06
>+#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
>+#define mmOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c07
>+#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
>+#define mmOTG1_OTG_VUPDATE_PARAM                                                                       0x1c08
>+#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
>+#define mmOTG1_OTG_VREADY_PARAM                                                                        0x1c09
>+#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
>+#define mmOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c0a
>+#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
>+#define mmOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0b
>+#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
>+#define mmOTG1_OTG_GSL_CONTROL                                                                         0x1c0c
>+#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
>+#define mmOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0d
>+#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
>+#define mmOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0e
>+#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
>+#define mmOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0f
>+#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
>+#define mmOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c10
>+#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
>+#define mmOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c11
>+#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
>+#define mmOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c12
>+#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
>+#define mmOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c13
>+#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
>+#define mmOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c14
>+#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
>+#define mmOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c15
>+#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
>+#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS                                                             0x1c16
>+#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
>+#define mmOTG1_OTG_DRR_CONTROL                                                                         0x1c17
>+#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
>+#define mmOTG1_OTG_REQUEST_CONTROL                                                                     0x1c18
>+#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
>+#define mmOTG1_OTG_DSC_START_POSITION                                                                  0x1c19
>+#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
>+#define mmOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c1a
>+#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
>+#define mmOTG1_OTG_SPARE_REGISTER                                                                      0x1c1c
>+#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_optc_otg2_dispdec
>+// base address: 0x400
>+#define mmOTG2_OTG_H_TOTAL                                                                             0x1c2a
>+#define mmOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
>+#define mmOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
>+#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
>+#define mmOTG2_OTG_H_SYNC_A                                                                            0x1c2c
>+#define mmOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
>+#define mmOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
>+#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
>+#define mmOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
>+#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
>+#define mmOTG2_OTG_V_TOTAL                                                                             0x1c2f
>+#define mmOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
>+#define mmOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
>+#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
>+#define mmOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
>+#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
>+#define mmOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
>+#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
>+#define mmOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
>+#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
>+#define mmOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c34
>+#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
>+#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c35
>+#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
>+#define mmOTG2_OTG_V_BLANK_START_END                                                                   0x1c36
>+#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
>+#define mmOTG2_OTG_V_SYNC_A                                                                            0x1c37
>+#define mmOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
>+#define mmOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c38
>+#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
>+#define mmOTG2_OTG_TRIGA_CNTL                                                                          0x1c39
>+#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
>+#define mmOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3a
>+#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
>+#define mmOTG2_OTG_TRIGB_CNTL                                                                          0x1c3b
>+#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
>+#define mmOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3c
>+#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
>+#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3d
>+#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
>+#define mmOTG2_OTG_FLOW_CONTROL                                                                        0x1c3e
>+#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2
>+#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c3f
>+#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
>+#define mmOTG2_OTG_CONTROL                                                                             0x1c41
>+#define mmOTG2_OTG_CONTROL_BASE_IDX                                                                    2
>+#define mmOTG2_OTG_BLANK_CONTROL                                                                       0x1c42
>+#define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX                                                              2
>+#define mmOTG2_OTG_PIPE_ABORT_CONTROL                                                                  0x1c43
>+#define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
>+#define mmOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c44
>+#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
>+#define mmOTG2_OTG_INTERLACE_STATUS                                                                    0x1c45
>+#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
>+#define mmOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
>+#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
>+#define mmOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
>+#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
>+#define mmOTG2_OTG_STATUS                                                                              0x1c49
>+#define mmOTG2_OTG_STATUS_BASE_IDX                                                                     2
>+#define mmOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
>+#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
>+#define mmOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4b
>+#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
>+#define mmOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4c
>+#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
>+#define mmOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4d
>+#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
>+#define mmOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4e
>+#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
>+#define mmOTG2_OTG_COUNT_CONTROL                                                                       0x1c4f
>+#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
>+#define mmOTG2_OTG_COUNT_RESET                                                                         0x1c50
>+#define mmOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
>+#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c51
>+#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
>+#define mmOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c52
>+#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
>+#define mmOTG2_OTG_STEREO_STATUS                                                                       0x1c53
>+#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
>+#define mmOTG2_OTG_STEREO_CONTROL                                                                      0x1c54
>+#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
>+#define mmOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c55
>+#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
>+#define mmOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c56
>+#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
>+#define mmOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c57
>+#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
>+#define mmOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c58
>+#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
>+#define mmOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c59
>+#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
>+#define mmOTG2_OTG_UPDATE_LOCK                                                                         0x1c5a
>+#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
>+#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5b
>+#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
>+#define mmOTG2_OTG_MASTER_EN                                                                           0x1c5c
>+#define mmOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
>+#define mmOTG2_OTG_BLANK_DATA_COLOR                                                                    0x1c5e
>+#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
>+#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT                                                                0x1c5f
>+#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
>+#define mmOTG2_OTG_BLACK_COLOR                                                                         0x1c60
>+#define mmOTG2_OTG_BLACK_COLOR_BASE_IDX                                                                2
>+#define mmOTG2_OTG_BLACK_COLOR_EXT                                                                     0x1c61
>+#define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
>+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c62
>+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
>+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c63
>+#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
>+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c64
>+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
>+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c65
>+#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
>+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c66
>+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
>+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c67
>+#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
>+#define mmOTG2_OTG_CRC_CNTL                                                                            0x1c68
>+#define mmOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
>+#define mmOTG2_OTG_CRC_CNTL2                                                                           0x1c69
>+#define mmOTG2_OTG_CRC_CNTL2_BASE_IDX                                                                  2
>+#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c6a
>+#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c6b
>+#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c6c
>+#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c6d
>+#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6e
>+#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG2_OTG_CRC0_DATA_B                                                                         0x1c6f
>+#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
>+#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c70
>+#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c71
>+#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c72
>+#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c73
>+#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG2_OTG_CRC1_DATA_RG                                                                        0x1c74
>+#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG2_OTG_CRC1_DATA_B                                                                         0x1c75
>+#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
>+#define mmOTG2_OTG_CRC2_DATA_RG                                                                        0x1c76
>+#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG2_OTG_CRC2_DATA_B                                                                         0x1c77
>+#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
>+#define mmOTG2_OTG_CRC3_DATA_RG                                                                        0x1c78
>+#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG2_OTG_CRC3_DATA_B                                                                         0x1c79
>+#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
>+#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c7a
>+#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
>+#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c7b
>+#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
>+#define mmOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c82
>+#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
>+#define mmOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c83
>+#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
>+#define mmOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c84
>+#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
>+#define mmOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c85
>+#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
>+#define mmOTG2_OTG_CLOCK_CONTROL                                                                       0x1c86
>+#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
>+#define mmOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c87
>+#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
>+#define mmOTG2_OTG_VUPDATE_PARAM                                                                       0x1c88
>+#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
>+#define mmOTG2_OTG_VREADY_PARAM                                                                        0x1c89
>+#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
>+#define mmOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c8a
>+#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
>+#define mmOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c8b
>+#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
>+#define mmOTG2_OTG_GSL_CONTROL                                                                         0x1c8c
>+#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
>+#define mmOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8d
>+#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
>+#define mmOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8e
>+#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
>+#define mmOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8f
>+#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
>+#define mmOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c90
>+#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
>+#define mmOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c91
>+#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
>+#define mmOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c92
>+#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
>+#define mmOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c93
>+#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
>+#define mmOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c94
>+#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
>+#define mmOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c95
>+#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
>+#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS                                                             0x1c96
>+#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
>+#define mmOTG2_OTG_DRR_CONTROL                                                                         0x1c97
>+#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
>+#define mmOTG2_OTG_REQUEST_CONTROL                                                                     0x1c98
>+#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
>+#define mmOTG2_OTG_DSC_START_POSITION                                                                  0x1c99
>+#define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
>+#define mmOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1c9a
>+#define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
>+#define mmOTG2_OTG_SPARE_REGISTER                                                                      0x1c9c
>+#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_optc_otg3_dispdec
>+// base address: 0x600
>+#define mmOTG3_OTG_H_TOTAL                                                                             0x1caa
>+#define mmOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
>+#define mmOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
>+#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
>+#define mmOTG3_OTG_H_SYNC_A                                                                            0x1cac
>+#define mmOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
>+#define mmOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
>+#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
>+#define mmOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
>+#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
>+#define mmOTG3_OTG_V_TOTAL                                                                             0x1caf
>+#define mmOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
>+#define mmOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
>+#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
>+#define mmOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
>+#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
>+#define mmOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
>+#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
>+#define mmOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
>+#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
>+#define mmOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb4
>+#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
>+#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb5
>+#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
>+#define mmOTG3_OTG_V_BLANK_START_END                                                                   0x1cb6
>+#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
>+#define mmOTG3_OTG_V_SYNC_A                                                                            0x1cb7
>+#define mmOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
>+#define mmOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cb8
>+#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
>+#define mmOTG3_OTG_TRIGA_CNTL                                                                          0x1cb9
>+#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
>+#define mmOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cba
>+#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
>+#define mmOTG3_OTG_TRIGB_CNTL                                                                          0x1cbb
>+#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
>+#define mmOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbc
>+#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
>+#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbd
>+#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
>+#define mmOTG3_OTG_FLOW_CONTROL                                                                        0x1cbe
>+#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2
>+#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cbf
>+#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
>+#define mmOTG3_OTG_CONTROL                                                                             0x1cc1
>+#define mmOTG3_OTG_CONTROL_BASE_IDX                                                                    2
>+#define mmOTG3_OTG_BLANK_CONTROL                                                                       0x1cc2
>+#define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX                                                              2
>+#define mmOTG3_OTG_PIPE_ABORT_CONTROL                                                                  0x1cc3
>+#define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
>+#define mmOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc4
>+#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
>+#define mmOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc5
>+#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
>+#define mmOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
>+#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
>+#define mmOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
>+#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
>+#define mmOTG3_OTG_STATUS                                                                              0x1cc9
>+#define mmOTG3_OTG_STATUS_BASE_IDX                                                                     2
>+#define mmOTG3_OTG_STATUS_POSITION                                                                     0x1cca
>+#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
>+#define mmOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccb
>+#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
>+#define mmOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccc
>+#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
>+#define mmOTG3_OTG_STATUS_VF_COUNT                                                                     0x1ccd
>+#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
>+#define mmOTG3_OTG_STATUS_HV_COUNT                                                                     0x1cce
>+#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
>+#define mmOTG3_OTG_COUNT_CONTROL                                                                       0x1ccf
>+#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
>+#define mmOTG3_OTG_COUNT_RESET                                                                         0x1cd0
>+#define mmOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
>+#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd1
>+#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
>+#define mmOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd2
>+#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
>+#define mmOTG3_OTG_STEREO_STATUS                                                                       0x1cd3
>+#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
>+#define mmOTG3_OTG_STEREO_CONTROL                                                                      0x1cd4
>+#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
>+#define mmOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd5
>+#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
>+#define mmOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd6
>+#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
>+#define mmOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd7
>+#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
>+#define mmOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd8
>+#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
>+#define mmOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cd9
>+#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
>+#define mmOTG3_OTG_UPDATE_LOCK                                                                         0x1cda
>+#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
>+#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdb
>+#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
>+#define mmOTG3_OTG_MASTER_EN                                                                           0x1cdc
>+#define mmOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
>+#define mmOTG3_OTG_BLANK_DATA_COLOR                                                                    0x1cde
>+#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
>+#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT                                                                0x1cdf
>+#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
>+#define mmOTG3_OTG_BLACK_COLOR                                                                         0x1ce0
>+#define mmOTG3_OTG_BLACK_COLOR_BASE_IDX                                                                2
>+#define mmOTG3_OTG_BLACK_COLOR_EXT                                                                     0x1ce1
>+#define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
>+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1ce2
>+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
>+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce3
>+#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
>+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce4
>+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
>+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce5
>+#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
>+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce6
>+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
>+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce7
>+#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
>+#define mmOTG3_OTG_CRC_CNTL                                                                            0x1ce8
>+#define mmOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
>+#define mmOTG3_OTG_CRC_CNTL2                                                                           0x1ce9
>+#define mmOTG3_OTG_CRC_CNTL2_BASE_IDX                                                                  2
>+#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1cea
>+#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1ceb
>+#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1cec
>+#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ced
>+#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG3_OTG_CRC0_DATA_RG                                                                        0x1cee
>+#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG3_OTG_CRC0_DATA_B                                                                         0x1cef
>+#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
>+#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cf0
>+#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1cf1
>+#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cf2
>+#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cf3
>+#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf4
>+#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG3_OTG_CRC1_DATA_B                                                                         0x1cf5
>+#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
>+#define mmOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf6
>+#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG3_OTG_CRC2_DATA_B                                                                         0x1cf7
>+#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
>+#define mmOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf8
>+#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG3_OTG_CRC3_DATA_B                                                                         0x1cf9
>+#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
>+#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cfa
>+#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
>+#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cfb
>+#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
>+#define mmOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d02
>+#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
>+#define mmOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d03
>+#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
>+#define mmOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d04
>+#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
>+#define mmOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d05
>+#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
>+#define mmOTG3_OTG_CLOCK_CONTROL                                                                       0x1d06
>+#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
>+#define mmOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d07
>+#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
>+#define mmOTG3_OTG_VUPDATE_PARAM                                                                       0x1d08
>+#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
>+#define mmOTG3_OTG_VREADY_PARAM                                                                        0x1d09
>+#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
>+#define mmOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d0a
>+#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
>+#define mmOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d0b
>+#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
>+#define mmOTG3_OTG_GSL_CONTROL                                                                         0x1d0c
>+#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
>+#define mmOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0d
>+#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
>+#define mmOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0e
>+#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
>+#define mmOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0f
>+#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
>+#define mmOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d10
>+#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
>+#define mmOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d11
>+#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
>+#define mmOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d12
>+#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
>+#define mmOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d13
>+#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
>+#define mmOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d14
>+#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
>+#define mmOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d15
>+#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
>+#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS                                                             0x1d16
>+#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
>+#define mmOTG3_OTG_DRR_CONTROL                                                                         0x1d17
>+#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
>+#define mmOTG3_OTG_REQUEST_CONTROL                                                                     0x1d18
>+#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
>+#define mmOTG3_OTG_DSC_START_POSITION                                                                  0x1d19
>+#define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
>+#define mmOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d1a
>+#define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
>+#define mmOTG3_OTG_SPARE_REGISTER                                                                      0x1d1c
>+#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_optc_otg4_dispdec
>+// base address: 0x800
>+#define mmOTG4_OTG_H_TOTAL                                                                             0x1d2a
>+#define mmOTG4_OTG_H_TOTAL_BASE_IDX                                                                    2
>+#define mmOTG4_OTG_H_BLANK_START_END                                                                   0x1d2b
>+#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX                                                          2
>+#define mmOTG4_OTG_H_SYNC_A                                                                            0x1d2c
>+#define mmOTG4_OTG_H_SYNC_A_BASE_IDX                                                                   2
>+#define mmOTG4_OTG_H_SYNC_A_CNTL                                                                       0x1d2d
>+#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
>+#define mmOTG4_OTG_H_TIMING_CNTL                                                                       0x1d2e
>+#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
>+#define mmOTG4_OTG_V_TOTAL                                                                             0x1d2f
>+#define mmOTG4_OTG_V_TOTAL_BASE_IDX                                                                    2
>+#define mmOTG4_OTG_V_TOTAL_MIN                                                                         0x1d30
>+#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
>+#define mmOTG4_OTG_V_TOTAL_MAX                                                                         0x1d31
>+#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
>+#define mmOTG4_OTG_V_TOTAL_MID                                                                         0x1d32
>+#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX                                                                2
>+#define mmOTG4_OTG_V_TOTAL_CONTROL                                                                     0x1d33
>+#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
>+#define mmOTG4_OTG_V_TOTAL_INT_STATUS                                                                  0x1d34
>+#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
>+#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS                                                                0x1d35
>+#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
>+#define mmOTG4_OTG_V_BLANK_START_END                                                                   0x1d36
>+#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX                                                          2
>+#define mmOTG4_OTG_V_SYNC_A                                                                            0x1d37
>+#define mmOTG4_OTG_V_SYNC_A_BASE_IDX                                                                   2
>+#define mmOTG4_OTG_V_SYNC_A_CNTL                                                                       0x1d38
>+#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
>+#define mmOTG4_OTG_TRIGA_CNTL                                                                          0x1d39
>+#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
>+#define mmOTG4_OTG_TRIGA_MANUAL_TRIG                                                                   0x1d3a
>+#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
>+#define mmOTG4_OTG_TRIGB_CNTL                                                                          0x1d3b
>+#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
>+#define mmOTG4_OTG_TRIGB_MANUAL_TRIG                                                                   0x1d3c
>+#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
>+#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1d3d
>+#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
>+#define mmOTG4_OTG_FLOW_CONTROL                                                                        0x1d3e
>+#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX                                                               2
>+#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1d3f
>+#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
>+#define mmOTG4_OTG_CONTROL                                                                             0x1d41
>+#define mmOTG4_OTG_CONTROL_BASE_IDX                                                                    2
>+#define mmOTG4_OTG_BLANK_CONTROL                                                                       0x1d42
>+#define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX                                                              2
>+#define mmOTG4_OTG_PIPE_ABORT_CONTROL                                                                  0x1d43
>+#define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
>+#define mmOTG4_OTG_INTERLACE_CONTROL                                                                   0x1d44
>+#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
>+#define mmOTG4_OTG_INTERLACE_STATUS                                                                    0x1d45
>+#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
>+#define mmOTG4_OTG_PIXEL_DATA_READBACK0                                                                0x1d47
>+#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
>+#define mmOTG4_OTG_PIXEL_DATA_READBACK1                                                                0x1d48
>+#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
>+#define mmOTG4_OTG_STATUS                                                                              0x1d49
>+#define mmOTG4_OTG_STATUS_BASE_IDX                                                                     2
>+#define mmOTG4_OTG_STATUS_POSITION                                                                     0x1d4a
>+#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX                                                            2
>+#define mmOTG4_OTG_NOM_VERT_POSITION                                                                   0x1d4b
>+#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
>+#define mmOTG4_OTG_STATUS_FRAME_COUNT                                                                  0x1d4c
>+#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
>+#define mmOTG4_OTG_STATUS_VF_COUNT                                                                     0x1d4d
>+#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
>+#define mmOTG4_OTG_STATUS_HV_COUNT                                                                     0x1d4e
>+#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
>+#define mmOTG4_OTG_COUNT_CONTROL                                                                       0x1d4f
>+#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX                                                              2
>+#define mmOTG4_OTG_COUNT_RESET                                                                         0x1d50
>+#define mmOTG4_OTG_COUNT_RESET_BASE_IDX                                                                2
>+#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1d51
>+#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
>+#define mmOTG4_OTG_VERT_SYNC_CONTROL                                                                   0x1d52
>+#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
>+#define mmOTG4_OTG_STEREO_STATUS                                                                       0x1d53
>+#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX                                                              2
>+#define mmOTG4_OTG_STEREO_CONTROL                                                                      0x1d54
>+#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX                                                             2
>+#define mmOTG4_OTG_SNAPSHOT_STATUS                                                                     0x1d55
>+#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
>+#define mmOTG4_OTG_SNAPSHOT_CONTROL                                                                    0x1d56
>+#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
>+#define mmOTG4_OTG_SNAPSHOT_POSITION                                                                   0x1d57
>+#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
>+#define mmOTG4_OTG_SNAPSHOT_FRAME                                                                      0x1d58
>+#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
>+#define mmOTG4_OTG_INTERRUPT_CONTROL                                                                   0x1d59
>+#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
>+#define mmOTG4_OTG_UPDATE_LOCK                                                                         0x1d5a
>+#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX                                                                2
>+#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1d5b
>+#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
>+#define mmOTG4_OTG_MASTER_EN                                                                           0x1d5c
>+#define mmOTG4_OTG_MASTER_EN_BASE_IDX                                                                  2
>+#define mmOTG4_OTG_BLANK_DATA_COLOR                                                                    0x1d5e
>+#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
>+#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT                                                                0x1d5f
>+#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
>+#define mmOTG4_OTG_BLACK_COLOR                                                                         0x1d60
>+#define mmOTG4_OTG_BLACK_COLOR_BASE_IDX                                                                2
>+#define mmOTG4_OTG_BLACK_COLOR_EXT                                                                     0x1d61
>+#define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
>+#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1d62
>+#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
>+#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1d63
>+#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
>+#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1d64
>+#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
>+#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1d65
>+#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
>+#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1d66
>+#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
>+#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1d67
>+#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
>+#define mmOTG4_OTG_CRC_CNTL                                                                            0x1d68
>+#define mmOTG4_OTG_CRC_CNTL_BASE_IDX                                                                   2
>+#define mmOTG4_OTG_CRC_CNTL2                                                                           0x1d69
>+#define mmOTG4_OTG_CRC_CNTL2_BASE_IDX                                                                  2
>+#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1d6a
>+#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1d6b
>+#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1d6c
>+#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1d6d
>+#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG4_OTG_CRC0_DATA_RG                                                                        0x1d6e
>+#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG4_OTG_CRC0_DATA_B                                                                         0x1d6f
>+#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX                                                                2
>+#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1d70
>+#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1d71
>+#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1d72
>+#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1d73
>+#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG4_OTG_CRC1_DATA_RG                                                                        0x1d74
>+#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG4_OTG_CRC1_DATA_B                                                                         0x1d75
>+#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX                                                                2
>+#define mmOTG4_OTG_CRC2_DATA_RG                                                                        0x1d76
>+#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG4_OTG_CRC2_DATA_B                                                                         0x1d77
>+#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX                                                                2
>+#define mmOTG4_OTG_CRC3_DATA_RG                                                                        0x1d78
>+#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG4_OTG_CRC3_DATA_B                                                                         0x1d79
>+#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX                                                                2
>+#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1d7a
>+#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
>+#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1d7b
>+#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
>+#define mmOTG4_OTG_STATIC_SCREEN_CONTROL                                                               0x1d82
>+#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
>+#define mmOTG4_OTG_3D_STRUCTURE_CONTROL                                                                0x1d83
>+#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
>+#define mmOTG4_OTG_GSL_VSYNC_GAP                                                                       0x1d84
>+#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
>+#define mmOTG4_OTG_MASTER_UPDATE_MODE                                                                  0x1d85
>+#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
>+#define mmOTG4_OTG_CLOCK_CONTROL                                                                       0x1d86
>+#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
>+#define mmOTG4_OTG_VSTARTUP_PARAM                                                                      0x1d87
>+#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
>+#define mmOTG4_OTG_VUPDATE_PARAM                                                                       0x1d88
>+#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
>+#define mmOTG4_OTG_VREADY_PARAM                                                                        0x1d89
>+#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX                                                               2
>+#define mmOTG4_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d8a
>+#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
>+#define mmOTG4_OTG_MASTER_UPDATE_LOCK                                                                  0x1d8b
>+#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
>+#define mmOTG4_OTG_GSL_CONTROL                                                                         0x1d8c
>+#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX                                                                2
>+#define mmOTG4_OTG_GSL_WINDOW_X                                                                        0x1d8d
>+#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
>+#define mmOTG4_OTG_GSL_WINDOW_Y                                                                        0x1d8e
>+#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
>+#define mmOTG4_OTG_VUPDATE_KEEPOUT                                                                     0x1d8f
>+#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
>+#define mmOTG4_OTG_GLOBAL_CONTROL0                                                                     0x1d90
>+#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
>+#define mmOTG4_OTG_GLOBAL_CONTROL1                                                                     0x1d91
>+#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
>+#define mmOTG4_OTG_GLOBAL_CONTROL2                                                                     0x1d92
>+#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
>+#define mmOTG4_OTG_GLOBAL_CONTROL3                                                                     0x1d93
>+#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
>+#define mmOTG4_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d94
>+#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
>+#define mmOTG4_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d95
>+#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
>+#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS                                                             0x1d96
>+#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
>+#define mmOTG4_OTG_DRR_CONTROL                                                                         0x1d97
>+#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX                                                                2
>+#define mmOTG4_OTG_REQUEST_CONTROL                                                                     0x1d98
>+#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
>+#define mmOTG4_OTG_DSC_START_POSITION                                                                  0x1d99
>+#define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX                                                         2
>+#define mmOTG4_OTG_PIPE_UPDATE_STATUS                                                                  0x1d9a
>+#define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
>+#define mmOTG4_OTG_SPARE_REGISTER                                                                      0x1d9c
>+#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_optc_otg5_dispdec
>+// base address: 0xa00
>+#define mmOTG5_OTG_H_TOTAL                                                                             0x1daa
>+#define mmOTG5_OTG_H_TOTAL_BASE_IDX                                                                    2
>+#define mmOTG5_OTG_H_BLANK_START_END                                                                   0x1dab
>+#define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX                                                          2
>+#define mmOTG5_OTG_H_SYNC_A                                                                            0x1dac
>+#define mmOTG5_OTG_H_SYNC_A_BASE_IDX                                                                   2
>+#define mmOTG5_OTG_H_SYNC_A_CNTL                                                                       0x1dad
>+#define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
>+#define mmOTG5_OTG_H_TIMING_CNTL                                                                       0x1dae
>+#define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
>+#define mmOTG5_OTG_V_TOTAL                                                                             0x1daf
>+#define mmOTG5_OTG_V_TOTAL_BASE_IDX                                                                    2
>+#define mmOTG5_OTG_V_TOTAL_MIN                                                                         0x1db0
>+#define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
>+#define mmOTG5_OTG_V_TOTAL_MAX                                                                         0x1db1
>+#define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
>+#define mmOTG5_OTG_V_TOTAL_MID                                                                         0x1db2
>+#define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX                                                                2
>+#define mmOTG5_OTG_V_TOTAL_CONTROL                                                                     0x1db3
>+#define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
>+#define mmOTG5_OTG_V_TOTAL_INT_STATUS                                                                  0x1db4
>+#define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
>+#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS                                                                0x1db5
>+#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
>+#define mmOTG5_OTG_V_BLANK_START_END                                                                   0x1db6
>+#define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX                                                          2
>+#define mmOTG5_OTG_V_SYNC_A                                                                            0x1db7
>+#define mmOTG5_OTG_V_SYNC_A_BASE_IDX                                                                   2
>+#define mmOTG5_OTG_V_SYNC_A_CNTL                                                                       0x1db8
>+#define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
>+#define mmOTG5_OTG_TRIGA_CNTL                                                                          0x1db9
>+#define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
>+#define mmOTG5_OTG_TRIGA_MANUAL_TRIG                                                                   0x1dba
>+#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
>+#define mmOTG5_OTG_TRIGB_CNTL                                                                          0x1dbb
>+#define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
>+#define mmOTG5_OTG_TRIGB_MANUAL_TRIG                                                                   0x1dbc
>+#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
>+#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1dbd
>+#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
>+#define mmOTG5_OTG_FLOW_CONTROL                                                                        0x1dbe
>+#define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX                                                               2
>+#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1dbf
>+#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
>+#define mmOTG5_OTG_CONTROL                                                                             0x1dc1
>+#define mmOTG5_OTG_CONTROL_BASE_IDX                                                                    2
>+#define mmOTG5_OTG_BLANK_CONTROL                                                                       0x1dc2
>+#define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX                                                              2
>+#define mmOTG5_OTG_PIPE_ABORT_CONTROL                                                                  0x1dc3
>+#define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX                                                         2
>+#define mmOTG5_OTG_INTERLACE_CONTROL                                                                   0x1dc4
>+#define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
>+#define mmOTG5_OTG_INTERLACE_STATUS                                                                    0x1dc5
>+#define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
>+#define mmOTG5_OTG_PIXEL_DATA_READBACK0                                                                0x1dc7
>+#define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
>+#define mmOTG5_OTG_PIXEL_DATA_READBACK1                                                                0x1dc8
>+#define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
>+#define mmOTG5_OTG_STATUS                                                                              0x1dc9
>+#define mmOTG5_OTG_STATUS_BASE_IDX                                                                     2
>+#define mmOTG5_OTG_STATUS_POSITION                                                                     0x1dca
>+#define mmOTG5_OTG_STATUS_POSITION_BASE_IDX                                                            2
>+#define mmOTG5_OTG_NOM_VERT_POSITION                                                                   0x1dcb
>+#define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
>+#define mmOTG5_OTG_STATUS_FRAME_COUNT                                                                  0x1dcc
>+#define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
>+#define mmOTG5_OTG_STATUS_VF_COUNT                                                                     0x1dcd
>+#define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
>+#define mmOTG5_OTG_STATUS_HV_COUNT                                                                     0x1dce
>+#define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
>+#define mmOTG5_OTG_COUNT_CONTROL                                                                       0x1dcf
>+#define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX                                                              2
>+#define mmOTG5_OTG_COUNT_RESET                                                                         0x1dd0
>+#define mmOTG5_OTG_COUNT_RESET_BASE_IDX                                                                2
>+#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1dd1
>+#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
>+#define mmOTG5_OTG_VERT_SYNC_CONTROL                                                                   0x1dd2
>+#define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
>+#define mmOTG5_OTG_STEREO_STATUS                                                                       0x1dd3
>+#define mmOTG5_OTG_STEREO_STATUS_BASE_IDX                                                              2
>+#define mmOTG5_OTG_STEREO_CONTROL                                                                      0x1dd4
>+#define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX                                                             2
>+#define mmOTG5_OTG_SNAPSHOT_STATUS                                                                     0x1dd5
>+#define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
>+#define mmOTG5_OTG_SNAPSHOT_CONTROL                                                                    0x1dd6
>+#define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
>+#define mmOTG5_OTG_SNAPSHOT_POSITION                                                                   0x1dd7
>+#define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
>+#define mmOTG5_OTG_SNAPSHOT_FRAME                                                                      0x1dd8
>+#define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
>+#define mmOTG5_OTG_INTERRUPT_CONTROL                                                                   0x1dd9
>+#define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
>+#define mmOTG5_OTG_UPDATE_LOCK                                                                         0x1dda
>+#define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX                                                                2
>+#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1ddb
>+#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
>+#define mmOTG5_OTG_MASTER_EN                                                                           0x1ddc
>+#define mmOTG5_OTG_MASTER_EN_BASE_IDX                                                                  2
>+#define mmOTG5_OTG_BLANK_DATA_COLOR                                                                    0x1dde
>+#define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX                                                           2
>+#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT                                                                0x1ddf
>+#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX                                                       2
>+#define mmOTG5_OTG_BLACK_COLOR                                                                         0x1de0
>+#define mmOTG5_OTG_BLACK_COLOR_BASE_IDX                                                                2
>+#define mmOTG5_OTG_BLACK_COLOR_EXT                                                                     0x1de1
>+#define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX                                                            2
>+#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1de2
>+#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
>+#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1de3
>+#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
>+#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1de4
>+#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
>+#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1de5
>+#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
>+#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1de6
>+#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
>+#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1de7
>+#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
>+#define mmOTG5_OTG_CRC_CNTL                                                                            0x1de8
>+#define mmOTG5_OTG_CRC_CNTL_BASE_IDX                                                                   2
>+#define mmOTG5_OTG_CRC_CNTL2                                                                           0x1de9
>+#define mmOTG5_OTG_CRC_CNTL2_BASE_IDX                                                                  2
>+#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1dea
>+#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1deb
>+#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1dec
>+#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ded
>+#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG5_OTG_CRC0_DATA_RG                                                                        0x1dee
>+#define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG5_OTG_CRC0_DATA_B                                                                         0x1def
>+#define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX                                                                2
>+#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1df0
>+#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1df1
>+#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1df2
>+#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
>+#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1df3
>+#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
>+#define mmOTG5_OTG_CRC1_DATA_RG                                                                        0x1df4
>+#define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG5_OTG_CRC1_DATA_B                                                                         0x1df5
>+#define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX                                                                2
>+#define mmOTG5_OTG_CRC2_DATA_RG                                                                        0x1df6
>+#define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG5_OTG_CRC2_DATA_B                                                                         0x1df7
>+#define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX                                                                2
>+#define mmOTG5_OTG_CRC3_DATA_RG                                                                        0x1df8
>+#define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
>+#define mmOTG5_OTG_CRC3_DATA_B                                                                         0x1df9
>+#define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX                                                                2
>+#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1dfa
>+#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
>+#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1dfb
>+#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
>+#define mmOTG5_OTG_STATIC_SCREEN_CONTROL                                                               0x1e02
>+#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
>+#define mmOTG5_OTG_3D_STRUCTURE_CONTROL                                                                0x1e03
>+#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
>+#define mmOTG5_OTG_GSL_VSYNC_GAP                                                                       0x1e04
>+#define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
>+#define mmOTG5_OTG_MASTER_UPDATE_MODE                                                                  0x1e05
>+#define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
>+#define mmOTG5_OTG_CLOCK_CONTROL                                                                       0x1e06
>+#define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
>+#define mmOTG5_OTG_VSTARTUP_PARAM                                                                      0x1e07
>+#define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
>+#define mmOTG5_OTG_VUPDATE_PARAM                                                                       0x1e08
>+#define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
>+#define mmOTG5_OTG_VREADY_PARAM                                                                        0x1e09
>+#define mmOTG5_OTG_VREADY_PARAM_BASE_IDX                                                               2
>+#define mmOTG5_OTG_GLOBAL_SYNC_STATUS                                                                  0x1e0a
>+#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
>+#define mmOTG5_OTG_MASTER_UPDATE_LOCK                                                                  0x1e0b
>+#define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
>+#define mmOTG5_OTG_GSL_CONTROL                                                                         0x1e0c
>+#define mmOTG5_OTG_GSL_CONTROL_BASE_IDX                                                                2
>+#define mmOTG5_OTG_GSL_WINDOW_X                                                                        0x1e0d
>+#define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
>+#define mmOTG5_OTG_GSL_WINDOW_Y                                                                        0x1e0e
>+#define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
>+#define mmOTG5_OTG_VUPDATE_KEEPOUT                                                                     0x1e0f
>+#define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
>+#define mmOTG5_OTG_GLOBAL_CONTROL0                                                                     0x1e10
>+#define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
>+#define mmOTG5_OTG_GLOBAL_CONTROL1                                                                     0x1e11
>+#define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
>+#define mmOTG5_OTG_GLOBAL_CONTROL2                                                                     0x1e12
>+#define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
>+#define mmOTG5_OTG_GLOBAL_CONTROL3                                                                     0x1e13
>+#define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
>+#define mmOTG5_OTG_TRIG_MANUAL_CONTROL                                                                 0x1e14
>+#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
>+#define mmOTG5_OTG_MANUAL_FLOW_CONTROL                                                                 0x1e15
>+#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
>+#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS                                                             0x1e16
>+#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX                                                    2
>+#define mmOTG5_OTG_DRR_CONTROL                                                                         0x1e17
>+#define mmOTG5_OTG_DRR_CONTROL_BASE_IDX                                                                2
>+#define mmOTG5_OTG_REQUEST_CONTROL                                                                     0x1e18
>+#define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
>+#define mmOTG5_OTG_DSC_START_POSITION                                                                  0x1e19
>+#define mmOTG5_OTG_DSC_START_POSITION_BASE_IDX                                                         2
>+#define mmOTG5_OTG_PIPE_UPDATE_STATUS                                                                  0x1e1a
>+#define mmOTG5_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
>+#define mmOTG5_OTG_SPARE_REGISTER                                                                      0x1e1c
>+#define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX                                                             2
>+
>+
>+// addressBlock: dce_dc_optc_optc_misc_dispdec
>+// base address: 0x0
>+#define mmDWB_SOURCE_SELECT                                                                            0x1e2a
>+#define mmDWB_SOURCE_SELECT_BASE_IDX                                                                   2
>+#define mmGSL_SOURCE_SELECT                                                                            0x1e2b
>+#define mmGSL_SOURCE_SELECT_BASE_IDX                                                                   2
>+#define mmOPTC_CLOCK_CONTROL                                                                           0x1e2c
>+#define mmOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
>+#define mmODM_MEM_PWR_CTRL                                                                             0x1e2d
>+#define mmODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
>+#define mmODM_MEM_PWR_CTRL2                                                                            0x1e2e
>+#define mmODM_MEM_PWR_CTRL2_BASE_IDX                                                                   2
>+#define mmODM_MEM_PWR_CTRL3                                                                            0x1e2f
>+#define mmODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
>+#define mmODM_MEM_PWR_STATUS                                                                           0x1e30
>+#define mmODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
>+#define mmOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
>+#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x79a8
>+#define mmDC_PERFMON17_PERFCOUNTER_CNTL                                                                0x1e6a
>+#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON17_PERFCOUNTER_CNTL2                                                               0x1e6b
>+#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON17_PERFCOUNTER_STATE                                                               0x1e6c
>+#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON17_PERFMON_CNTL                                                                    0x1e6d
>+#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON17_PERFMON_CNTL2                                                                   0x1e6e
>+#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC                                                         0x1e6f
>+#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON17_PERFMON_CVALUE_LOW                                                              0x1e70
>+#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON17_PERFMON_HI                                                                      0x1e71
>+#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON17_PERFMON_LOW                                                                     0x1e72
>+#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dio_dout_i2c_dispdec
>+// base address: 0x0
>+#define mmDC_I2C_CONTROL                                                                               0x1e98
>+#define mmDC_I2C_CONTROL_BASE_IDX                                                                      2
>+#define mmDC_I2C_ARBITRATION                                                                           0x1e99
>+#define mmDC_I2C_ARBITRATION_BASE_IDX                                                                  2
>+#define mmDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
>+#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
>+#define mmDC_I2C_SW_STATUS                                                                             0x1e9b
>+#define mmDC_I2C_SW_STATUS_BASE_IDX                                                                    2
>+#define mmDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
>+#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
>+#define mmDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
>+#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
>+#define mmDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
>+#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
>+#define mmDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
>+#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
>+#define mmDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0
>+#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2
>+#define mmDC_I2C_DDC1_SPEED                                                                            0x1ea2
>+#define mmDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
>+#define mmDC_I2C_DDC1_SETUP                                                                            0x1ea3
>+#define mmDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
>+#define mmDC_I2C_DDC2_SPEED                                                                            0x1ea4
>+#define mmDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
>+#define mmDC_I2C_DDC2_SETUP                                                                            0x1ea5
>+#define mmDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
>+#define mmDC_I2C_DDC3_SPEED                                                                            0x1ea6
>+#define mmDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
>+#define mmDC_I2C_DDC3_SETUP                                                                            0x1ea7
>+#define mmDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
>+#define mmDC_I2C_DDC4_SPEED                                                                            0x1ea8
>+#define mmDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
>+#define mmDC_I2C_DDC4_SETUP                                                                            0x1ea9
>+#define mmDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
>+#define mmDC_I2C_DDC5_SPEED                                                                            0x1eaa
>+#define mmDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2
>+#define mmDC_I2C_DDC5_SETUP                                                                            0x1eab
>+#define mmDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2
>+#define mmDC_I2C_TRANSACTION0                                                                          0x1eae
>+#define mmDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
>+#define mmDC_I2C_TRANSACTION1                                                                          0x1eaf
>+#define mmDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
>+#define mmDC_I2C_TRANSACTION2                                                                          0x1eb0
>+#define mmDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
>+#define mmDC_I2C_TRANSACTION3                                                                          0x1eb1
>+#define mmDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
>+#define mmDC_I2C_DATA                                                                                  0x1eb2
>+#define mmDC_I2C_DATA_BASE_IDX                                                                         2
>+#define mmDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
>+#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
>+#define mmDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
>+#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
>+
>+
>+// addressBlock: dce_dc_dio_dio_misc_dispdec
>+// base address: 0x0
>+#define mmDIO_SCRATCH0                                                                                 0x1eca
>+#define mmDIO_SCRATCH0_BASE_IDX                                                                        2
>+#define mmDIO_SCRATCH1                                                                                 0x1ecb
>+#define mmDIO_SCRATCH1_BASE_IDX                                                                        2
>+#define mmDIO_SCRATCH2                                                                                 0x1ecc
>+#define mmDIO_SCRATCH2_BASE_IDX                                                                        2
>+#define mmDIO_SCRATCH3                                                                                 0x1ecd
>+#define mmDIO_SCRATCH3_BASE_IDX                                                                        2
>+#define mmDIO_SCRATCH4                                                                                 0x1ece
>+#define mmDIO_SCRATCH4_BASE_IDX                                                                        2
>+#define mmDIO_SCRATCH5                                                                                 0x1ecf
>+#define mmDIO_SCRATCH5_BASE_IDX                                                                        2
>+#define mmDIO_SCRATCH6                                                                                 0x1ed0
>+#define mmDIO_SCRATCH6_BASE_IDX                                                                        2
>+#define mmDIO_SCRATCH7                                                                                 0x1ed1
>+#define mmDIO_SCRATCH7_BASE_IDX                                                                        2
>+#define mmDCE_VCE_CONTROL                                                                              0x1ed2
>+#define mmDCE_VCE_CONTROL_BASE_IDX                                                                     2
>+#define mmDIO_MEM_PWR_STATUS                                                                           0x1edd
>+#define mmDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
>+#define mmDIO_MEM_PWR_CTRL                                                                             0x1ede
>+#define mmDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
>+#define mmDIO_MEM_PWR_CTRL2                                                                            0x1edf
>+#define mmDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
>+#define mmDIO_CLK_CNTL                                                                                 0x1ee0
>+#define mmDIO_CLK_CNTL_BASE_IDX                                                                        2
>+#define mmDIO_MEM_PWR_CTRL3                                                                            0x1ee1
>+#define mmDIO_MEM_PWR_CTRL3_BASE_IDX                                                                   2
>+#define mmDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
>+#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
>+#define mmDIG_SOFT_RESET                                                                               0x1eee
>+#define mmDIG_SOFT_RESET_BASE_IDX                                                                      2
>+#define mmDIO_MEM_PWR_STATUS1                                                                          0x1ef0
>+#define mmDIO_MEM_PWR_STATUS1_BASE_IDX                                                                 2
>+#define mmDIO_CLK_CNTL2                                                                                0x1ef2
>+#define mmDIO_CLK_CNTL2_BASE_IDX                                                                       2
>+#define mmDIO_CLK_CNTL3                                                                                0x1ef3
>+#define mmDIO_CLK_CNTL3_BASE_IDX                                                                       2
>+#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
>+#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
>+#define mmDIO_PSP_INTERRUPT_STATUS                                                                     0x1f00
>+#define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX                                                            2
>+#define mmDIO_PSP_INTERRUPT_CLEAR                                                                      0x1f01
>+#define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX                                                             2
>+#define mmDIO_GENERIC_INTERRUPT_MESSAGE                                                                0x1f02
>+#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX                                                       2
>+#define mmDIO_GENERIC_INTERRUPT_CLEAR                                                                  0x1f03
>+#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX                                                         2
>+
>+
>+// addressBlock: dce_dc_dio_hpd0_dispdec
>+// base address: 0x0
>+#define mmHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
>+#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
>+#define mmHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
>+#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
>+#define mmHPD0_DC_HPD_CONTROL                                                                          0x1f16
>+#define mmHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
>+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
>+#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
>+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
>+#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
>+
>+
>+// addressBlock: dce_dc_dio_hpd1_dispdec
>+// base address: 0x20
>+#define mmHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
>+#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
>+#define mmHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
>+#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
>+#define mmHPD1_DC_HPD_CONTROL                                                                          0x1f1e
>+#define mmHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
>+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
>+#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
>+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
>+#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
>+
>+
>+// addressBlock: dce_dc_dio_hpd2_dispdec
>+// base address: 0x40
>+#define mmHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
>+#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
>+#define mmHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
>+#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
>+#define mmHPD2_DC_HPD_CONTROL                                                                          0x1f26
>+#define mmHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
>+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
>+#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
>+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
>+#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
>+
>+
>+// addressBlock: dce_dc_dio_hpd3_dispdec
>+// base address: 0x60
>+#define mmHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
>+#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
>+#define mmHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
>+#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
>+#define mmHPD3_DC_HPD_CONTROL                                                                          0x1f2e
>+#define mmHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
>+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
>+#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
>+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
>+#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
>+
>+
>+// addressBlock: dce_dc_dio_hpd4_dispdec
>+// base address: 0x80
>+#define mmHPD4_DC_HPD_INT_STATUS                                                                       0x1f34
>+#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2
>+#define mmHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35
>+#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
>+#define mmHPD4_DC_HPD_CONTROL                                                                          0x1f36
>+#define mmHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2
>+#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37
>+#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
>+#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38
>+#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
>+
>+
>+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
>+// base address: 0x7d10
>+#define mmDC_PERFMON18_PERFCOUNTER_CNTL                                                                0x1f44
>+#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON18_PERFCOUNTER_CNTL2                                                               0x1f45
>+#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON18_PERFCOUNTER_STATE                                                               0x1f46
>+#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON18_PERFMON_CNTL                                                                    0x1f47
>+#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON18_PERFMON_CNTL2                                                                   0x1f48
>+#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC                                                         0x1f49
>+#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON18_PERFMON_CVALUE_LOW                                                              0x1f4a
>+#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON18_PERFMON_HI                                                                      0x1f4b
>+#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON18_PERFMON_LOW                                                                     0x1f4c
>+#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dio_dp_aux0_dispdec
>+// base address: 0x0
>+#define mmDP_AUX0_AUX_CONTROL                                                                          0x1f50
>+#define mmDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
>+#define mmDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
>+#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
>+#define mmDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
>+#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
>+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
>+#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
>+#define mmDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
>+#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
>+#define mmDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
>+#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
>+#define mmDP_AUX0_AUX_SW_DATA                                                                          0x1f56
>+#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
>+#define mmDP_AUX0_AUX_LS_DATA                                                                          0x1f57
>+#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
>+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
>+#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
>+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
>+#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
>+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
>+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
>+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
>+#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
>+#define mmDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
>+#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
>+#define mmDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
>+#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
>+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
>+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
>+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
>+#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
>+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
>+#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
>+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
>+#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
>+#define mmDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
>+#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
>+
>+
>+// addressBlock: dce_dc_dio_dp_aux1_dispdec
>+// base address: 0x70
>+#define mmDP_AUX1_AUX_CONTROL                                                                          0x1f6c
>+#define mmDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
>+#define mmDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
>+#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
>+#define mmDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
>+#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
>+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
>+#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
>+#define mmDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
>+#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
>+#define mmDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
>+#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
>+#define mmDP_AUX1_AUX_SW_DATA                                                                          0x1f72
>+#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
>+#define mmDP_AUX1_AUX_LS_DATA                                                                          0x1f73
>+#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
>+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
>+#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
>+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
>+#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
>+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
>+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
>+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
>+#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
>+#define mmDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
>+#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
>+#define mmDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
>+#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
>+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
>+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
>+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
>+#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
>+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
>+#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
>+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
>+#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
>+#define mmDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
>+#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
>+
>+
>+// addressBlock: dce_dc_dio_dp_aux2_dispdec
>+// base address: 0xe0
>+#define mmDP_AUX2_AUX_CONTROL                                                                          0x1f88
>+#define mmDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
>+#define mmDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
>+#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
>+#define mmDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
>+#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
>+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
>+#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
>+#define mmDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
>+#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
>+#define mmDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
>+#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
>+#define mmDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
>+#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
>+#define mmDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
>+#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
>+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
>+#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
>+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
>+#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
>+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
>+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
>+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
>+#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
>+#define mmDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
>+#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
>+#define mmDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
>+#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
>+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
>+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
>+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
>+#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
>+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
>+#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
>+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
>+#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
>+#define mmDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
>+#define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
>+
>+
>+// addressBlock: dce_dc_dio_dp_aux3_dispdec
>+// base address: 0x150
>+#define mmDP_AUX3_AUX_CONTROL                                                                          0x1fa4
>+#define mmDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
>+#define mmDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
>+#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
>+#define mmDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
>+#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
>+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
>+#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
>+#define mmDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
>+#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
>+#define mmDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
>+#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
>+#define mmDP_AUX3_AUX_SW_DATA                                                                          0x1faa
>+#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
>+#define mmDP_AUX3_AUX_LS_DATA                                                                          0x1fab
>+#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
>+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
>+#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
>+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
>+#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
>+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
>+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
>+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
>+#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
>+#define mmDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
>+#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
>+#define mmDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
>+#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
>+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
>+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
>+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
>+#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
>+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
>+#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
>+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
>+#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
>+#define mmDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
>+#define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
>+
>+
>+// addressBlock: dce_dc_dio_dp_aux4_dispdec
>+// base address: 0x1c0
>+#define mmDP_AUX4_AUX_CONTROL                                                                          0x1fc0
>+#define mmDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2
>+#define mmDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1
>+#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2
>+#define mmDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2
>+#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2
>+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3
>+#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
>+#define mmDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4
>+#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2
>+#define mmDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5
>+#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2
>+#define mmDP_AUX4_AUX_SW_DATA                                                                          0x1fc6
>+#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2
>+#define mmDP_AUX4_AUX_LS_DATA                                                                          0x1fc7
>+#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2
>+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8
>+#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
>+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9
>+#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
>+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca
>+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
>+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb
>+#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
>+#define mmDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc
>+#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
>+#define mmDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd
>+#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
>+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce
>+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
>+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf
>+#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
>+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0
>+#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
>+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1
>+#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
>+#define mmDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6
>+#define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
>+
>+
>+// addressBlock: dce_dc_dio_dig0_dispdec
>+// base address: 0x0
>+#define mmDIG0_DIG_FE_CNTL                                                                             0x2068
>+#define mmDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
>+#define mmDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x2069
>+#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
>+#define mmDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x206a
>+#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
>+#define mmDIG0_DIG_CLOCK_PATTERN                                                                       0x206b
>+#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
>+#define mmDIG0_DIG_TEST_PATTERN                                                                        0x206c
>+#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
>+#define mmDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x206d
>+#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
>+#define mmDIG0_DIG_FIFO_STATUS                                                                         0x206e
>+#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX                                                                2
>+#define mmDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x206f
>+#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
>+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2070
>+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
>+#define mmDIG0_HDMI_CONTROL                                                                            0x2071
>+#define mmDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
>+#define mmDIG0_HDMI_STATUS                                                                             0x2072
>+#define mmDIG0_HDMI_STATUS_BASE_IDX                                                                    2
>+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2073
>+#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
>+#define mmDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2074
>+#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2075
>+#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2076
>+#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
>+#define mmDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x2077
>+#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
>+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2078
>+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
>+#define mmDIG0_AFMT_INTERRUPT_STATUS                                                                   0x2079
>+#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
>+#define mmDIG0_HDMI_GC                                                                                 0x207b
>+#define mmDIG0_HDMI_GC_BASE_IDX                                                                        2
>+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2                                                              0x207c
>+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
>+#define mmDIG0_AFMT_ISRC1_0                                                                            0x207d
>+#define mmDIG0_AFMT_ISRC1_0_BASE_IDX                                                                   2
>+#define mmDIG0_AFMT_ISRC1_1                                                                            0x207e
>+#define mmDIG0_AFMT_ISRC1_1_BASE_IDX                                                                   2
>+#define mmDIG0_AFMT_ISRC1_2                                                                            0x207f
>+#define mmDIG0_AFMT_ISRC1_2_BASE_IDX                                                                   2
>+#define mmDIG0_AFMT_ISRC1_3                                                                            0x2080
>+#define mmDIG0_AFMT_ISRC1_3_BASE_IDX                                                                   2
>+#define mmDIG0_AFMT_ISRC1_4                                                                            0x2081
>+#define mmDIG0_AFMT_ISRC1_4_BASE_IDX                                                                   2
>+#define mmDIG0_AFMT_ISRC2_0                                                                            0x2082
>+#define mmDIG0_AFMT_ISRC2_0_BASE_IDX                                                                   2
>+#define mmDIG0_AFMT_ISRC2_1                                                                            0x2083
>+#define mmDIG0_AFMT_ISRC2_1_BASE_IDX                                                                   2
>+#define mmDIG0_AFMT_ISRC2_2                                                                            0x2084
>+#define mmDIG0_AFMT_ISRC2_2_BASE_IDX                                                                   2
>+#define mmDIG0_AFMT_ISRC2_3                                                                            0x2085
>+#define mmDIG0_AFMT_ISRC2_3_BASE_IDX                                                                   2
>+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2086
>+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
>+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2087
>+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
>+#define mmDIG0_HDMI_DB_CONTROL                                                                         0x2088
>+#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
>+#define mmDIG0_DME_CONTROL                                                                             0x2089
>+#define mmDIG0_DME_CONTROL_BASE_IDX                                                                    2
>+#define mmDIG0_AFMT_MPEG_INFO0                                                                         0x208a
>+#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX                                                                2
>+#define mmDIG0_AFMT_MPEG_INFO1                                                                         0x208b
>+#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX                                                                2
>+#define mmDIG0_AFMT_GENERIC_HDR                                                                        0x208c
>+#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX                                                               2
>+#define mmDIG0_AFMT_GENERIC_0                                                                          0x208d
>+#define mmDIG0_AFMT_GENERIC_0_BASE_IDX                                                                 2
>+#define mmDIG0_AFMT_GENERIC_1                                                                          0x208e
>+#define mmDIG0_AFMT_GENERIC_1_BASE_IDX                                                                 2
>+#define mmDIG0_AFMT_GENERIC_2                                                                          0x208f
>+#define mmDIG0_AFMT_GENERIC_2_BASE_IDX                                                                 2
>+#define mmDIG0_AFMT_GENERIC_3                                                                          0x2090
>+#define mmDIG0_AFMT_GENERIC_3_BASE_IDX                                                                 2
>+#define mmDIG0_AFMT_GENERIC_4                                                                          0x2091
>+#define mmDIG0_AFMT_GENERIC_4_BASE_IDX                                                                 2
>+#define mmDIG0_AFMT_GENERIC_5                                                                          0x2092
>+#define mmDIG0_AFMT_GENERIC_5_BASE_IDX                                                                 2
>+#define mmDIG0_AFMT_GENERIC_6                                                                          0x2093
>+#define mmDIG0_AFMT_GENERIC_6_BASE_IDX                                                                 2
>+#define mmDIG0_AFMT_GENERIC_7                                                                          0x2094
>+#define mmDIG0_AFMT_GENERIC_7_BASE_IDX                                                                 2
>+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2095
>+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
>+#define mmDIG0_HDMI_ACR_32_0                                                                           0x2096
>+#define mmDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
>+#define mmDIG0_HDMI_ACR_32_1                                                                           0x2097
>+#define mmDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
>+#define mmDIG0_HDMI_ACR_44_0                                                                           0x2098
>+#define mmDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
>+#define mmDIG0_HDMI_ACR_44_1                                                                           0x2099
>+#define mmDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
>+#define mmDIG0_HDMI_ACR_48_0                                                                           0x209a
>+#define mmDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
>+#define mmDIG0_HDMI_ACR_48_1                                                                           0x209b
>+#define mmDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
>+#define mmDIG0_HDMI_ACR_STATUS_0                                                                       0x209c
>+#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
>+#define mmDIG0_HDMI_ACR_STATUS_1                                                                       0x209d
>+#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
>+#define mmDIG0_AFMT_AUDIO_INFO0                                                                        0x209e
>+#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
>+#define mmDIG0_AFMT_AUDIO_INFO1                                                                        0x209f
>+#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
>+#define mmDIG0_AFMT_60958_0                                                                            0x20a0
>+#define mmDIG0_AFMT_60958_0_BASE_IDX                                                                   2
>+#define mmDIG0_AFMT_60958_1                                                                            0x20a1
>+#define mmDIG0_AFMT_60958_1_BASE_IDX                                                                   2
>+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL                                                                  0x20a2
>+#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
>+#define mmDIG0_AFMT_RAMP_CONTROL0                                                                      0x20a3
>+#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
>+#define mmDIG0_AFMT_RAMP_CONTROL1                                                                      0x20a4
>+#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
>+#define mmDIG0_AFMT_RAMP_CONTROL2                                                                      0x20a5
>+#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
>+#define mmDIG0_AFMT_RAMP_CONTROL3                                                                      0x20a6
>+#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
>+#define mmDIG0_AFMT_60958_2                                                                            0x20a7
>+#define mmDIG0_AFMT_60958_2_BASE_IDX                                                                   2
>+#define mmDIG0_AFMT_AUDIO_CRC_RESULT                                                                   0x20a8
>+#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
>+#define mmDIG0_AFMT_STATUS                                                                             0x20a9
>+#define mmDIG0_AFMT_STATUS_BASE_IDX                                                                    2
>+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL                                                               0x20aa
>+#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
>+#define mmDIG0_AFMT_VBI_PACKET_CONTROL                                                                 0x20ab
>+#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG0_AFMT_INFOFRAME_CONTROL0                                                                 0x20ac
>+#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
>+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL                                                                  0x20ad
>+#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
>+#define mmDIG0_DIG_BE_CNTL                                                                             0x20af
>+#define mmDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
>+#define mmDIG0_DIG_BE_EN_CNTL                                                                          0x20b0
>+#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
>+#define mmDIG0_TMDS_CNTL                                                                               0x20d3
>+#define mmDIG0_TMDS_CNTL_BASE_IDX                                                                      2
>+#define mmDIG0_TMDS_CONTROL_CHAR                                                                       0x20d4
>+#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
>+#define mmDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20d5
>+#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
>+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20d6
>+#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
>+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20d7
>+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
>+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20d8
>+#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
>+#define mmDIG0_TMDS_CTL_BITS                                                                           0x20da
>+#define mmDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
>+#define mmDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20db
>+#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
>+#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20dc
>+#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
>+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20dd
>+#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
>+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20de
>+#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
>+#define mmDIG0_DIG_VERSION                                                                             0x20e0
>+#define mmDIG0_DIG_VERSION_BASE_IDX                                                                    2
>+#define mmDIG0_DIG_LANE_ENABLE                                                                         0x20e1
>+#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX                                                                2
>+#define mmDIG0_AFMT_CNTL                                                                               0x20e6
>+#define mmDIG0_AFMT_CNTL_BASE_IDX                                                                      2
>+#define mmDIG0_AFMT_VBI_PACKET_CONTROL1                                                                0x20e7
>+#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
>+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x20f6
>+#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
>+#define mmDIG0_FORCE_DIG_DISABLE                                                                       0x20f7
>+#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dio_dp0_dispdec
>+// base address: 0x0
>+#define mmDP0_DP_LINK_CNTL                                                                             0x2108
>+#define mmDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
>+#define mmDP0_DP_PIXEL_FORMAT                                                                          0x2109
>+#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
>+#define mmDP0_DP_MSA_COLORIMETRY                                                                       0x210a
>+#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
>+#define mmDP0_DP_CONFIG                                                                                0x210b
>+#define mmDP0_DP_CONFIG_BASE_IDX                                                                       2
>+#define mmDP0_DP_VID_STREAM_CNTL                                                                       0x210c
>+#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
>+#define mmDP0_DP_STEER_FIFO                                                                            0x210d
>+#define mmDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
>+#define mmDP0_DP_MSA_MISC                                                                              0x210e
>+#define mmDP0_DP_MSA_MISC_BASE_IDX                                                                     2
>+#define mmDP0_DP_VID_TIMING                                                                            0x2110
>+#define mmDP0_DP_VID_TIMING_BASE_IDX                                                                   2
>+#define mmDP0_DP_VID_N                                                                                 0x2111
>+#define mmDP0_DP_VID_N_BASE_IDX                                                                        2
>+#define mmDP0_DP_VID_M                                                                                 0x2112
>+#define mmDP0_DP_VID_M_BASE_IDX                                                                        2
>+#define mmDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
>+#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
>+#define mmDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
>+#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
>+#define mmDP0_DP_VID_MSA_VBID                                                                          0x2115
>+#define mmDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
>+#define mmDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
>+#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
>+#define mmDP0_DP_DPHY_CNTL                                                                             0x2117
>+#define mmDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
>+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
>+#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
>+#define mmDP0_DP_DPHY_SYM0                                                                             0x2119
>+#define mmDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
>+#define mmDP0_DP_DPHY_SYM1                                                                             0x211a
>+#define mmDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
>+#define mmDP0_DP_DPHY_SYM2                                                                             0x211b
>+#define mmDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
>+#define mmDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
>+#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
>+#define mmDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
>+#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
>+#define mmDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
>+#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
>+#define mmDP0_DP_DPHY_CRC_EN                                                                           0x211f
>+#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
>+#define mmDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
>+#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
>+#define mmDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
>+#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
>+#define mmDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
>+#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
>+#define mmDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
>+#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
>+#define mmDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
>+#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
>+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
>+#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
>+#define mmDP0_DP_SEC_CNTL                                                                              0x212b
>+#define mmDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
>+#define mmDP0_DP_SEC_CNTL1                                                                             0x212c
>+#define mmDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
>+#define mmDP0_DP_SEC_FRAMING1                                                                          0x212d
>+#define mmDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
>+#define mmDP0_DP_SEC_FRAMING2                                                                          0x212e
>+#define mmDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
>+#define mmDP0_DP_SEC_FRAMING3                                                                          0x212f
>+#define mmDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
>+#define mmDP0_DP_SEC_FRAMING4                                                                          0x2130
>+#define mmDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
>+#define mmDP0_DP_SEC_AUD_N                                                                             0x2131
>+#define mmDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
>+#define mmDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
>+#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
>+#define mmDP0_DP_SEC_AUD_M                                                                             0x2133
>+#define mmDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
>+#define mmDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
>+#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
>+#define mmDP0_DP_SEC_TIMESTAMP                                                                         0x2135
>+#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
>+#define mmDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
>+#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
>+#define mmDP0_DP_MSE_RATE_CNTL                                                                         0x2137
>+#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
>+#define mmDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
>+#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
>+#define mmDP0_DP_MSE_SAT0                                                                              0x213a
>+#define mmDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
>+#define mmDP0_DP_MSE_SAT1                                                                              0x213b
>+#define mmDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
>+#define mmDP0_DP_MSE_SAT2                                                                              0x213c
>+#define mmDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
>+#define mmDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
>+#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
>+#define mmDP0_DP_MSE_LINK_TIMING                                                                       0x213e
>+#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
>+#define mmDP0_DP_MSE_MISC_CNTL                                                                         0x213f
>+#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
>+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
>+#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
>+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
>+#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
>+#define mmDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
>+#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
>+#define mmDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
>+#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
>+#define mmDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
>+#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
>+#define mmDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
>+#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
>+#define mmDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
>+#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
>+#define mmDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
>+#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
>+#define mmDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
>+#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
>+#define mmDP0_DP_MSO_CNTL                                                                              0x2150
>+#define mmDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
>+#define mmDP0_DP_MSO_CNTL1                                                                             0x2151
>+#define mmDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
>+#define mmDP0_DP_DSC_CNTL                                                                              0x2152
>+#define mmDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
>+#define mmDP0_DP_SEC_CNTL2                                                                             0x2153
>+#define mmDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
>+#define mmDP0_DP_SEC_CNTL3                                                                             0x2154
>+#define mmDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
>+#define mmDP0_DP_SEC_CNTL4                                                                             0x2155
>+#define mmDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
>+#define mmDP0_DP_SEC_CNTL5                                                                             0x2156
>+#define mmDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
>+#define mmDP0_DP_SEC_CNTL6                                                                             0x2157
>+#define mmDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
>+#define mmDP0_DP_SEC_CNTL7                                                                             0x2158
>+#define mmDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
>+#define mmDP0_DP_DB_CNTL                                                                               0x2159
>+#define mmDP0_DP_DB_CNTL_BASE_IDX                                                                      2
>+#define mmDP0_DP_MSA_VBID_MISC                                                                         0x215a
>+#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
>+#define mmDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
>+#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
>+#define mmDP0_DP_DSC_BYTES_PER_PIXEL                                                                   0x215c
>+#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
>+#define mmDP0_DP_ALPM_CNTL                                                                             0x215d
>+#define mmDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
>+
>+
>+// addressBlock: dce_dc_dio_dig1_dispdec
>+// base address: 0x400
>+#define mmDIG1_DIG_FE_CNTL                                                                             0x2168
>+#define mmDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
>+#define mmDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x2169
>+#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
>+#define mmDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x216a
>+#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
>+#define mmDIG1_DIG_CLOCK_PATTERN                                                                       0x216b
>+#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
>+#define mmDIG1_DIG_TEST_PATTERN                                                                        0x216c
>+#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
>+#define mmDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x216d
>+#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
>+#define mmDIG1_DIG_FIFO_STATUS                                                                         0x216e
>+#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX                                                                2
>+#define mmDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x216f
>+#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
>+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2170
>+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
>+#define mmDIG1_HDMI_CONTROL                                                                            0x2171
>+#define mmDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
>+#define mmDIG1_HDMI_STATUS                                                                             0x2172
>+#define mmDIG1_HDMI_STATUS_BASE_IDX                                                                    2
>+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2173
>+#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
>+#define mmDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2174
>+#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2175
>+#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2176
>+#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
>+#define mmDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x2177
>+#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
>+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2178
>+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
>+#define mmDIG1_AFMT_INTERRUPT_STATUS                                                                   0x2179
>+#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
>+#define mmDIG1_HDMI_GC                                                                                 0x217b
>+#define mmDIG1_HDMI_GC_BASE_IDX                                                                        2
>+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2                                                              0x217c
>+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
>+#define mmDIG1_AFMT_ISRC1_0                                                                            0x217d
>+#define mmDIG1_AFMT_ISRC1_0_BASE_IDX                                                                   2
>+#define mmDIG1_AFMT_ISRC1_1                                                                            0x217e
>+#define mmDIG1_AFMT_ISRC1_1_BASE_IDX                                                                   2
>+#define mmDIG1_AFMT_ISRC1_2                                                                            0x217f
>+#define mmDIG1_AFMT_ISRC1_2_BASE_IDX                                                                   2
>+#define mmDIG1_AFMT_ISRC1_3                                                                            0x2180
>+#define mmDIG1_AFMT_ISRC1_3_BASE_IDX                                                                   2
>+#define mmDIG1_AFMT_ISRC1_4                                                                            0x2181
>+#define mmDIG1_AFMT_ISRC1_4_BASE_IDX                                                                   2
>+#define mmDIG1_AFMT_ISRC2_0                                                                            0x2182
>+#define mmDIG1_AFMT_ISRC2_0_BASE_IDX                                                                   2
>+#define mmDIG1_AFMT_ISRC2_1                                                                            0x2183
>+#define mmDIG1_AFMT_ISRC2_1_BASE_IDX                                                                   2
>+#define mmDIG1_AFMT_ISRC2_2                                                                            0x2184
>+#define mmDIG1_AFMT_ISRC2_2_BASE_IDX                                                                   2
>+#define mmDIG1_AFMT_ISRC2_3                                                                            0x2185
>+#define mmDIG1_AFMT_ISRC2_3_BASE_IDX                                                                   2
>+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2186
>+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
>+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2187
>+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
>+#define mmDIG1_HDMI_DB_CONTROL                                                                         0x2188
>+#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
>+#define mmDIG1_DME_CONTROL                                                                             0x2189
>+#define mmDIG1_DME_CONTROL_BASE_IDX                                                                    2
>+#define mmDIG1_AFMT_MPEG_INFO0                                                                         0x218a
>+#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX                                                                2
>+#define mmDIG1_AFMT_MPEG_INFO1                                                                         0x218b
>+#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX                                                                2
>+#define mmDIG1_AFMT_GENERIC_HDR                                                                        0x218c
>+#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX                                                               2
>+#define mmDIG1_AFMT_GENERIC_0                                                                          0x218d
>+#define mmDIG1_AFMT_GENERIC_0_BASE_IDX                                                                 2
>+#define mmDIG1_AFMT_GENERIC_1                                                                          0x218e
>+#define mmDIG1_AFMT_GENERIC_1_BASE_IDX                                                                 2
>+#define mmDIG1_AFMT_GENERIC_2                                                                          0x218f
>+#define mmDIG1_AFMT_GENERIC_2_BASE_IDX                                                                 2
>+#define mmDIG1_AFMT_GENERIC_3                                                                          0x2190
>+#define mmDIG1_AFMT_GENERIC_3_BASE_IDX                                                                 2
>+#define mmDIG1_AFMT_GENERIC_4                                                                          0x2191
>+#define mmDIG1_AFMT_GENERIC_4_BASE_IDX                                                                 2
>+#define mmDIG1_AFMT_GENERIC_5                                                                          0x2192
>+#define mmDIG1_AFMT_GENERIC_5_BASE_IDX                                                                 2
>+#define mmDIG1_AFMT_GENERIC_6                                                                          0x2193
>+#define mmDIG1_AFMT_GENERIC_6_BASE_IDX                                                                 2
>+#define mmDIG1_AFMT_GENERIC_7                                                                          0x2194
>+#define mmDIG1_AFMT_GENERIC_7_BASE_IDX                                                                 2
>+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2195
>+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
>+#define mmDIG1_HDMI_ACR_32_0                                                                           0x2196
>+#define mmDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
>+#define mmDIG1_HDMI_ACR_32_1                                                                           0x2197
>+#define mmDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
>+#define mmDIG1_HDMI_ACR_44_0                                                                           0x2198
>+#define mmDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
>+#define mmDIG1_HDMI_ACR_44_1                                                                           0x2199
>+#define mmDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
>+#define mmDIG1_HDMI_ACR_48_0                                                                           0x219a
>+#define mmDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
>+#define mmDIG1_HDMI_ACR_48_1                                                                           0x219b
>+#define mmDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
>+#define mmDIG1_HDMI_ACR_STATUS_0                                                                       0x219c
>+#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
>+#define mmDIG1_HDMI_ACR_STATUS_1                                                                       0x219d
>+#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
>+#define mmDIG1_AFMT_AUDIO_INFO0                                                                        0x219e
>+#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
>+#define mmDIG1_AFMT_AUDIO_INFO1                                                                        0x219f
>+#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
>+#define mmDIG1_AFMT_60958_0                                                                            0x21a0
>+#define mmDIG1_AFMT_60958_0_BASE_IDX                                                                   2
>+#define mmDIG1_AFMT_60958_1                                                                            0x21a1
>+#define mmDIG1_AFMT_60958_1_BASE_IDX                                                                   2
>+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL                                                                  0x21a2
>+#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
>+#define mmDIG1_AFMT_RAMP_CONTROL0                                                                      0x21a3
>+#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
>+#define mmDIG1_AFMT_RAMP_CONTROL1                                                                      0x21a4
>+#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
>+#define mmDIG1_AFMT_RAMP_CONTROL2                                                                      0x21a5
>+#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
>+#define mmDIG1_AFMT_RAMP_CONTROL3                                                                      0x21a6
>+#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
>+#define mmDIG1_AFMT_60958_2                                                                            0x21a7
>+#define mmDIG1_AFMT_60958_2_BASE_IDX                                                                   2
>+#define mmDIG1_AFMT_AUDIO_CRC_RESULT                                                                   0x21a8
>+#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
>+#define mmDIG1_AFMT_STATUS                                                                             0x21a9
>+#define mmDIG1_AFMT_STATUS_BASE_IDX                                                                    2
>+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL                                                               0x21aa
>+#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
>+#define mmDIG1_AFMT_VBI_PACKET_CONTROL                                                                 0x21ab
>+#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG1_AFMT_INFOFRAME_CONTROL0                                                                 0x21ac
>+#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
>+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL                                                                  0x21ad
>+#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
>+#define mmDIG1_DIG_BE_CNTL                                                                             0x21af
>+#define mmDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
>+#define mmDIG1_DIG_BE_EN_CNTL                                                                          0x21b0
>+#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
>+#define mmDIG1_TMDS_CNTL                                                                               0x21d3
>+#define mmDIG1_TMDS_CNTL_BASE_IDX                                                                      2
>+#define mmDIG1_TMDS_CONTROL_CHAR                                                                       0x21d4
>+#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
>+#define mmDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21d5
>+#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
>+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21d6
>+#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
>+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21d7
>+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
>+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21d8
>+#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
>+#define mmDIG1_TMDS_CTL_BITS                                                                           0x21da
>+#define mmDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
>+#define mmDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21db
>+#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
>+#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21dc
>+#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
>+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x21dd
>+#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
>+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x21de
>+#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
>+#define mmDIG1_DIG_VERSION                                                                             0x21e0
>+#define mmDIG1_DIG_VERSION_BASE_IDX                                                                    2
>+#define mmDIG1_DIG_LANE_ENABLE                                                                         0x21e1
>+#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX                                                                2
>+#define mmDIG1_AFMT_CNTL                                                                               0x21e6
>+#define mmDIG1_AFMT_CNTL_BASE_IDX                                                                      2
>+#define mmDIG1_AFMT_VBI_PACKET_CONTROL1                                                                0x21e7
>+#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
>+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x21f6
>+#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
>+#define mmDIG1_FORCE_DIG_DISABLE                                                                       0x21f7
>+#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dio_dp1_dispdec
>+// base address: 0x400
>+#define mmDP1_DP_LINK_CNTL                                                                             0x2208
>+#define mmDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
>+#define mmDP1_DP_PIXEL_FORMAT                                                                          0x2209
>+#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
>+#define mmDP1_DP_MSA_COLORIMETRY                                                                       0x220a
>+#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
>+#define mmDP1_DP_CONFIG                                                                                0x220b
>+#define mmDP1_DP_CONFIG_BASE_IDX                                                                       2
>+#define mmDP1_DP_VID_STREAM_CNTL                                                                       0x220c
>+#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
>+#define mmDP1_DP_STEER_FIFO                                                                            0x220d
>+#define mmDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
>+#define mmDP1_DP_MSA_MISC                                                                              0x220e
>+#define mmDP1_DP_MSA_MISC_BASE_IDX                                                                     2
>+#define mmDP1_DP_VID_TIMING                                                                            0x2210
>+#define mmDP1_DP_VID_TIMING_BASE_IDX                                                                   2
>+#define mmDP1_DP_VID_N                                                                                 0x2211
>+#define mmDP1_DP_VID_N_BASE_IDX                                                                        2
>+#define mmDP1_DP_VID_M                                                                                 0x2212
>+#define mmDP1_DP_VID_M_BASE_IDX                                                                        2
>+#define mmDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
>+#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
>+#define mmDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
>+#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
>+#define mmDP1_DP_VID_MSA_VBID                                                                          0x2215
>+#define mmDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
>+#define mmDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
>+#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
>+#define mmDP1_DP_DPHY_CNTL                                                                             0x2217
>+#define mmDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
>+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
>+#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
>+#define mmDP1_DP_DPHY_SYM0                                                                             0x2219
>+#define mmDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
>+#define mmDP1_DP_DPHY_SYM1                                                                             0x221a
>+#define mmDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
>+#define mmDP1_DP_DPHY_SYM2                                                                             0x221b
>+#define mmDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
>+#define mmDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
>+#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
>+#define mmDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
>+#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
>+#define mmDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
>+#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
>+#define mmDP1_DP_DPHY_CRC_EN                                                                           0x221f
>+#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
>+#define mmDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
>+#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
>+#define mmDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
>+#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
>+#define mmDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
>+#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
>+#define mmDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
>+#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
>+#define mmDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
>+#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
>+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
>+#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
>+#define mmDP1_DP_SEC_CNTL                                                                              0x222b
>+#define mmDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
>+#define mmDP1_DP_SEC_CNTL1                                                                             0x222c
>+#define mmDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
>+#define mmDP1_DP_SEC_FRAMING1                                                                          0x222d
>+#define mmDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
>+#define mmDP1_DP_SEC_FRAMING2                                                                          0x222e
>+#define mmDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
>+#define mmDP1_DP_SEC_FRAMING3                                                                          0x222f
>+#define mmDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
>+#define mmDP1_DP_SEC_FRAMING4                                                                          0x2230
>+#define mmDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
>+#define mmDP1_DP_SEC_AUD_N                                                                             0x2231
>+#define mmDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
>+#define mmDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
>+#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
>+#define mmDP1_DP_SEC_AUD_M                                                                             0x2233
>+#define mmDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
>+#define mmDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
>+#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
>+#define mmDP1_DP_SEC_TIMESTAMP                                                                         0x2235
>+#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
>+#define mmDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
>+#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
>+#define mmDP1_DP_MSE_RATE_CNTL                                                                         0x2237
>+#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
>+#define mmDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
>+#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
>+#define mmDP1_DP_MSE_SAT0                                                                              0x223a
>+#define mmDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
>+#define mmDP1_DP_MSE_SAT1                                                                              0x223b
>+#define mmDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
>+#define mmDP1_DP_MSE_SAT2                                                                              0x223c
>+#define mmDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
>+#define mmDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
>+#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
>+#define mmDP1_DP_MSE_LINK_TIMING                                                                       0x223e
>+#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
>+#define mmDP1_DP_MSE_MISC_CNTL                                                                         0x223f
>+#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
>+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
>+#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
>+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
>+#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
>+#define mmDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
>+#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
>+#define mmDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
>+#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
>+#define mmDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
>+#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
>+#define mmDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
>+#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
>+#define mmDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
>+#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
>+#define mmDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
>+#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
>+#define mmDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
>+#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
>+#define mmDP1_DP_MSO_CNTL                                                                              0x2250
>+#define mmDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
>+#define mmDP1_DP_MSO_CNTL1                                                                             0x2251
>+#define mmDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
>+#define mmDP1_DP_DSC_CNTL                                                                              0x2252
>+#define mmDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
>+#define mmDP1_DP_SEC_CNTL2                                                                             0x2253
>+#define mmDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
>+#define mmDP1_DP_SEC_CNTL3                                                                             0x2254
>+#define mmDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
>+#define mmDP1_DP_SEC_CNTL4                                                                             0x2255
>+#define mmDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
>+#define mmDP1_DP_SEC_CNTL5                                                                             0x2256
>+#define mmDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
>+#define mmDP1_DP_SEC_CNTL6                                                                             0x2257
>+#define mmDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
>+#define mmDP1_DP_SEC_CNTL7                                                                             0x2258
>+#define mmDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
>+#define mmDP1_DP_DB_CNTL                                                                               0x2259
>+#define mmDP1_DP_DB_CNTL_BASE_IDX                                                                      2
>+#define mmDP1_DP_MSA_VBID_MISC                                                                         0x225a
>+#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
>+#define mmDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
>+#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
>+#define mmDP1_DP_DSC_BYTES_PER_PIXEL                                                                   0x225c
>+#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
>+#define mmDP1_DP_ALPM_CNTL                                                                             0x225d
>+#define mmDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
>+
>+
>+// addressBlock: dce_dc_dio_dig2_dispdec
>+// base address: 0x800
>+#define mmDIG2_DIG_FE_CNTL                                                                             0x2268
>+#define mmDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
>+#define mmDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x2269
>+#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
>+#define mmDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x226a
>+#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
>+#define mmDIG2_DIG_CLOCK_PATTERN                                                                       0x226b
>+#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
>+#define mmDIG2_DIG_TEST_PATTERN                                                                        0x226c
>+#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
>+#define mmDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x226d
>+#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
>+#define mmDIG2_DIG_FIFO_STATUS                                                                         0x226e
>+#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX                                                                2
>+#define mmDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x226f
>+#define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
>+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2270
>+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
>+#define mmDIG2_HDMI_CONTROL                                                                            0x2271
>+#define mmDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
>+#define mmDIG2_HDMI_STATUS                                                                             0x2272
>+#define mmDIG2_HDMI_STATUS_BASE_IDX                                                                    2
>+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x2273
>+#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
>+#define mmDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x2274
>+#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x2275
>+#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x2276
>+#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
>+#define mmDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x2277
>+#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
>+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2278
>+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
>+#define mmDIG2_AFMT_INTERRUPT_STATUS                                                                   0x2279
>+#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
>+#define mmDIG2_HDMI_GC                                                                                 0x227b
>+#define mmDIG2_HDMI_GC_BASE_IDX                                                                        2
>+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2                                                              0x227c
>+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
>+#define mmDIG2_AFMT_ISRC1_0                                                                            0x227d
>+#define mmDIG2_AFMT_ISRC1_0_BASE_IDX                                                                   2
>+#define mmDIG2_AFMT_ISRC1_1                                                                            0x227e
>+#define mmDIG2_AFMT_ISRC1_1_BASE_IDX                                                                   2
>+#define mmDIG2_AFMT_ISRC1_2                                                                            0x227f
>+#define mmDIG2_AFMT_ISRC1_2_BASE_IDX                                                                   2
>+#define mmDIG2_AFMT_ISRC1_3                                                                            0x2280
>+#define mmDIG2_AFMT_ISRC1_3_BASE_IDX                                                                   2
>+#define mmDIG2_AFMT_ISRC1_4                                                                            0x2281
>+#define mmDIG2_AFMT_ISRC1_4_BASE_IDX                                                                   2
>+#define mmDIG2_AFMT_ISRC2_0                                                                            0x2282
>+#define mmDIG2_AFMT_ISRC2_0_BASE_IDX                                                                   2
>+#define mmDIG2_AFMT_ISRC2_1                                                                            0x2283
>+#define mmDIG2_AFMT_ISRC2_1_BASE_IDX                                                                   2
>+#define mmDIG2_AFMT_ISRC2_2                                                                            0x2284
>+#define mmDIG2_AFMT_ISRC2_2_BASE_IDX                                                                   2
>+#define mmDIG2_AFMT_ISRC2_3                                                                            0x2285
>+#define mmDIG2_AFMT_ISRC2_3_BASE_IDX                                                                   2
>+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2286
>+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
>+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2287
>+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
>+#define mmDIG2_HDMI_DB_CONTROL                                                                         0x2288
>+#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
>+#define mmDIG2_DME_CONTROL                                                                             0x2289
>+#define mmDIG2_DME_CONTROL_BASE_IDX                                                                    2
>+#define mmDIG2_AFMT_MPEG_INFO0                                                                         0x228a
>+#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX                                                                2
>+#define mmDIG2_AFMT_MPEG_INFO1                                                                         0x228b
>+#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX                                                                2
>+#define mmDIG2_AFMT_GENERIC_HDR                                                                        0x228c
>+#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX                                                               2
>+#define mmDIG2_AFMT_GENERIC_0                                                                          0x228d
>+#define mmDIG2_AFMT_GENERIC_0_BASE_IDX                                                                 2
>+#define mmDIG2_AFMT_GENERIC_1                                                                          0x228e
>+#define mmDIG2_AFMT_GENERIC_1_BASE_IDX                                                                 2
>+#define mmDIG2_AFMT_GENERIC_2                                                                          0x228f
>+#define mmDIG2_AFMT_GENERIC_2_BASE_IDX                                                                 2
>+#define mmDIG2_AFMT_GENERIC_3                                                                          0x2290
>+#define mmDIG2_AFMT_GENERIC_3_BASE_IDX                                                                 2
>+#define mmDIG2_AFMT_GENERIC_4                                                                          0x2291
>+#define mmDIG2_AFMT_GENERIC_4_BASE_IDX                                                                 2
>+#define mmDIG2_AFMT_GENERIC_5                                                                          0x2292
>+#define mmDIG2_AFMT_GENERIC_5_BASE_IDX                                                                 2
>+#define mmDIG2_AFMT_GENERIC_6                                                                          0x2293
>+#define mmDIG2_AFMT_GENERIC_6_BASE_IDX                                                                 2
>+#define mmDIG2_AFMT_GENERIC_7                                                                          0x2294
>+#define mmDIG2_AFMT_GENERIC_7_BASE_IDX                                                                 2
>+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2295
>+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
>+#define mmDIG2_HDMI_ACR_32_0                                                                           0x2296
>+#define mmDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
>+#define mmDIG2_HDMI_ACR_32_1                                                                           0x2297
>+#define mmDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
>+#define mmDIG2_HDMI_ACR_44_0                                                                           0x2298
>+#define mmDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
>+#define mmDIG2_HDMI_ACR_44_1                                                                           0x2299
>+#define mmDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
>+#define mmDIG2_HDMI_ACR_48_0                                                                           0x229a
>+#define mmDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
>+#define mmDIG2_HDMI_ACR_48_1                                                                           0x229b
>+#define mmDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
>+#define mmDIG2_HDMI_ACR_STATUS_0                                                                       0x229c
>+#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
>+#define mmDIG2_HDMI_ACR_STATUS_1                                                                       0x229d
>+#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
>+#define mmDIG2_AFMT_AUDIO_INFO0                                                                        0x229e
>+#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
>+#define mmDIG2_AFMT_AUDIO_INFO1                                                                        0x229f
>+#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
>+#define mmDIG2_AFMT_60958_0                                                                            0x22a0
>+#define mmDIG2_AFMT_60958_0_BASE_IDX                                                                   2
>+#define mmDIG2_AFMT_60958_1                                                                            0x22a1
>+#define mmDIG2_AFMT_60958_1_BASE_IDX                                                                   2
>+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL                                                                  0x22a2
>+#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
>+#define mmDIG2_AFMT_RAMP_CONTROL0                                                                      0x22a3
>+#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
>+#define mmDIG2_AFMT_RAMP_CONTROL1                                                                      0x22a4
>+#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
>+#define mmDIG2_AFMT_RAMP_CONTROL2                                                                      0x22a5
>+#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
>+#define mmDIG2_AFMT_RAMP_CONTROL3                                                                      0x22a6
>+#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
>+#define mmDIG2_AFMT_60958_2                                                                            0x22a7
>+#define mmDIG2_AFMT_60958_2_BASE_IDX                                                                   2
>+#define mmDIG2_AFMT_AUDIO_CRC_RESULT                                                                   0x22a8
>+#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
>+#define mmDIG2_AFMT_STATUS                                                                             0x22a9
>+#define mmDIG2_AFMT_STATUS_BASE_IDX                                                                    2
>+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL                                                               0x22aa
>+#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
>+#define mmDIG2_AFMT_VBI_PACKET_CONTROL                                                                 0x22ab
>+#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG2_AFMT_INFOFRAME_CONTROL0                                                                 0x22ac
>+#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
>+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL                                                                  0x22ad
>+#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
>+#define mmDIG2_DIG_BE_CNTL                                                                             0x22af
>+#define mmDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
>+#define mmDIG2_DIG_BE_EN_CNTL                                                                          0x22b0
>+#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
>+#define mmDIG2_TMDS_CNTL                                                                               0x22d3
>+#define mmDIG2_TMDS_CNTL_BASE_IDX                                                                      2
>+#define mmDIG2_TMDS_CONTROL_CHAR                                                                       0x22d4
>+#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
>+#define mmDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x22d5
>+#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
>+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x22d6
>+#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
>+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x22d7
>+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
>+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x22d8
>+#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
>+#define mmDIG2_TMDS_CTL_BITS                                                                           0x22da
>+#define mmDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
>+#define mmDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x22db
>+#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
>+#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x22dc
>+#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
>+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x22dd
>+#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
>+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x22de
>+#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
>+#define mmDIG2_DIG_VERSION                                                                             0x22e0
>+#define mmDIG2_DIG_VERSION_BASE_IDX                                                                    2
>+#define mmDIG2_DIG_LANE_ENABLE                                                                         0x22e1
>+#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX                                                                2
>+#define mmDIG2_AFMT_CNTL                                                                               0x22e6
>+#define mmDIG2_AFMT_CNTL_BASE_IDX                                                                      2
>+#define mmDIG2_AFMT_VBI_PACKET_CONTROL1                                                                0x22e7
>+#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
>+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x22f6
>+#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
>+#define mmDIG2_FORCE_DIG_DISABLE                                                                       0x22f7
>+#define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dio_dp2_dispdec
>+// base address: 0x800
>+#define mmDP2_DP_LINK_CNTL                                                                             0x2308
>+#define mmDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
>+#define mmDP2_DP_PIXEL_FORMAT                                                                          0x2309
>+#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
>+#define mmDP2_DP_MSA_COLORIMETRY                                                                       0x230a
>+#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
>+#define mmDP2_DP_CONFIG                                                                                0x230b
>+#define mmDP2_DP_CONFIG_BASE_IDX                                                                       2
>+#define mmDP2_DP_VID_STREAM_CNTL                                                                       0x230c
>+#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
>+#define mmDP2_DP_STEER_FIFO                                                                            0x230d
>+#define mmDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
>+#define mmDP2_DP_MSA_MISC                                                                              0x230e
>+#define mmDP2_DP_MSA_MISC_BASE_IDX                                                                     2
>+#define mmDP2_DP_VID_TIMING                                                                            0x2310
>+#define mmDP2_DP_VID_TIMING_BASE_IDX                                                                   2
>+#define mmDP2_DP_VID_N                                                                                 0x2311
>+#define mmDP2_DP_VID_N_BASE_IDX                                                                        2
>+#define mmDP2_DP_VID_M                                                                                 0x2312
>+#define mmDP2_DP_VID_M_BASE_IDX                                                                        2
>+#define mmDP2_DP_LINK_FRAMING_CNTL                                                                     0x2313
>+#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
>+#define mmDP2_DP_HBR2_EYE_PATTERN                                                                      0x2314
>+#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
>+#define mmDP2_DP_VID_MSA_VBID                                                                          0x2315
>+#define mmDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
>+#define mmDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2316
>+#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
>+#define mmDP2_DP_DPHY_CNTL                                                                             0x2317
>+#define mmDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
>+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2318
>+#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
>+#define mmDP2_DP_DPHY_SYM0                                                                             0x2319
>+#define mmDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
>+#define mmDP2_DP_DPHY_SYM1                                                                             0x231a
>+#define mmDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
>+#define mmDP2_DP_DPHY_SYM2                                                                             0x231b
>+#define mmDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
>+#define mmDP2_DP_DPHY_8B10B_CNTL                                                                       0x231c
>+#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
>+#define mmDP2_DP_DPHY_PRBS_CNTL                                                                        0x231d
>+#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
>+#define mmDP2_DP_DPHY_SCRAM_CNTL                                                                       0x231e
>+#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
>+#define mmDP2_DP_DPHY_CRC_EN                                                                           0x231f
>+#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
>+#define mmDP2_DP_DPHY_CRC_CNTL                                                                         0x2320
>+#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
>+#define mmDP2_DP_DPHY_CRC_RESULT                                                                       0x2321
>+#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
>+#define mmDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2322
>+#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
>+#define mmDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2323
>+#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
>+#define mmDP2_DP_DPHY_FAST_TRAINING                                                                    0x2324
>+#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
>+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2325
>+#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
>+#define mmDP2_DP_SEC_CNTL                                                                              0x232b
>+#define mmDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
>+#define mmDP2_DP_SEC_CNTL1                                                                             0x232c
>+#define mmDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
>+#define mmDP2_DP_SEC_FRAMING1                                                                          0x232d
>+#define mmDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
>+#define mmDP2_DP_SEC_FRAMING2                                                                          0x232e
>+#define mmDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
>+#define mmDP2_DP_SEC_FRAMING3                                                                          0x232f
>+#define mmDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
>+#define mmDP2_DP_SEC_FRAMING4                                                                          0x2330
>+#define mmDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
>+#define mmDP2_DP_SEC_AUD_N                                                                             0x2331
>+#define mmDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
>+#define mmDP2_DP_SEC_AUD_N_READBACK                                                                    0x2332
>+#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
>+#define mmDP2_DP_SEC_AUD_M                                                                             0x2333
>+#define mmDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
>+#define mmDP2_DP_SEC_AUD_M_READBACK                                                                    0x2334
>+#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
>+#define mmDP2_DP_SEC_TIMESTAMP                                                                         0x2335
>+#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
>+#define mmDP2_DP_SEC_PACKET_CNTL                                                                       0x2336
>+#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
>+#define mmDP2_DP_MSE_RATE_CNTL                                                                         0x2337
>+#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
>+#define mmDP2_DP_MSE_RATE_UPDATE                                                                       0x2339
>+#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
>+#define mmDP2_DP_MSE_SAT0                                                                              0x233a
>+#define mmDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
>+#define mmDP2_DP_MSE_SAT1                                                                              0x233b
>+#define mmDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
>+#define mmDP2_DP_MSE_SAT2                                                                              0x233c
>+#define mmDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
>+#define mmDP2_DP_MSE_SAT_UPDATE                                                                        0x233d
>+#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
>+#define mmDP2_DP_MSE_LINK_TIMING                                                                       0x233e
>+#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
>+#define mmDP2_DP_MSE_MISC_CNTL                                                                         0x233f
>+#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
>+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2344
>+#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
>+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2345
>+#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
>+#define mmDP2_DP_MSE_SAT0_STATUS                                                                       0x2347
>+#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
>+#define mmDP2_DP_MSE_SAT1_STATUS                                                                       0x2348
>+#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
>+#define mmDP2_DP_MSE_SAT2_STATUS                                                                       0x2349
>+#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
>+#define mmDP2_DP_MSA_TIMING_PARAM1                                                                     0x234c
>+#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
>+#define mmDP2_DP_MSA_TIMING_PARAM2                                                                     0x234d
>+#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
>+#define mmDP2_DP_MSA_TIMING_PARAM3                                                                     0x234e
>+#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
>+#define mmDP2_DP_MSA_TIMING_PARAM4                                                                     0x234f
>+#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
>+#define mmDP2_DP_MSO_CNTL                                                                              0x2350
>+#define mmDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
>+#define mmDP2_DP_MSO_CNTL1                                                                             0x2351
>+#define mmDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
>+#define mmDP2_DP_DSC_CNTL                                                                              0x2352
>+#define mmDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
>+#define mmDP2_DP_SEC_CNTL2                                                                             0x2353
>+#define mmDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
>+#define mmDP2_DP_SEC_CNTL3                                                                             0x2354
>+#define mmDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
>+#define mmDP2_DP_SEC_CNTL4                                                                             0x2355
>+#define mmDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
>+#define mmDP2_DP_SEC_CNTL5                                                                             0x2356
>+#define mmDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
>+#define mmDP2_DP_SEC_CNTL6                                                                             0x2357
>+#define mmDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
>+#define mmDP2_DP_SEC_CNTL7                                                                             0x2358
>+#define mmDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
>+#define mmDP2_DP_DB_CNTL                                                                               0x2359
>+#define mmDP2_DP_DB_CNTL_BASE_IDX                                                                      2
>+#define mmDP2_DP_MSA_VBID_MISC                                                                         0x235a
>+#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
>+#define mmDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x235b
>+#define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
>+#define mmDP2_DP_DSC_BYTES_PER_PIXEL                                                                   0x235c
>+#define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
>+#define mmDP2_DP_ALPM_CNTL                                                                             0x235d
>+#define mmDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
>+
>+
>+// addressBlock: dce_dc_dio_dig3_dispdec
>+// base address: 0xc00
>+#define mmDIG3_DIG_FE_CNTL                                                                             0x2368
>+#define mmDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
>+#define mmDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x2369
>+#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
>+#define mmDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x236a
>+#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
>+#define mmDIG3_DIG_CLOCK_PATTERN                                                                       0x236b
>+#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
>+#define mmDIG3_DIG_TEST_PATTERN                                                                        0x236c
>+#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
>+#define mmDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x236d
>+#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
>+#define mmDIG3_DIG_FIFO_STATUS                                                                         0x236e
>+#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX                                                                2
>+#define mmDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x236f
>+#define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
>+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2370
>+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
>+#define mmDIG3_HDMI_CONTROL                                                                            0x2371
>+#define mmDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
>+#define mmDIG3_HDMI_STATUS                                                                             0x2372
>+#define mmDIG3_HDMI_STATUS_BASE_IDX                                                                    2
>+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x2373
>+#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
>+#define mmDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x2374
>+#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x2375
>+#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x2376
>+#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
>+#define mmDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x2377
>+#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
>+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2378
>+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
>+#define mmDIG3_AFMT_INTERRUPT_STATUS                                                                   0x2379
>+#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
>+#define mmDIG3_HDMI_GC                                                                                 0x237b
>+#define mmDIG3_HDMI_GC_BASE_IDX                                                                        2
>+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2                                                              0x237c
>+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
>+#define mmDIG3_AFMT_ISRC1_0                                                                            0x237d
>+#define mmDIG3_AFMT_ISRC1_0_BASE_IDX                                                                   2
>+#define mmDIG3_AFMT_ISRC1_1                                                                            0x237e
>+#define mmDIG3_AFMT_ISRC1_1_BASE_IDX                                                                   2
>+#define mmDIG3_AFMT_ISRC1_2                                                                            0x237f
>+#define mmDIG3_AFMT_ISRC1_2_BASE_IDX                                                                   2
>+#define mmDIG3_AFMT_ISRC1_3                                                                            0x2380
>+#define mmDIG3_AFMT_ISRC1_3_BASE_IDX                                                                   2
>+#define mmDIG3_AFMT_ISRC1_4                                                                            0x2381
>+#define mmDIG3_AFMT_ISRC1_4_BASE_IDX                                                                   2
>+#define mmDIG3_AFMT_ISRC2_0                                                                            0x2382
>+#define mmDIG3_AFMT_ISRC2_0_BASE_IDX                                                                   2
>+#define mmDIG3_AFMT_ISRC2_1                                                                            0x2383
>+#define mmDIG3_AFMT_ISRC2_1_BASE_IDX                                                                   2
>+#define mmDIG3_AFMT_ISRC2_2                                                                            0x2384
>+#define mmDIG3_AFMT_ISRC2_2_BASE_IDX                                                                   2
>+#define mmDIG3_AFMT_ISRC2_3                                                                            0x2385
>+#define mmDIG3_AFMT_ISRC2_3_BASE_IDX                                                                   2
>+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2386
>+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
>+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2387
>+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
>+#define mmDIG3_HDMI_DB_CONTROL                                                                         0x2388
>+#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
>+#define mmDIG3_DME_CONTROL                                                                             0x2389
>+#define mmDIG3_DME_CONTROL_BASE_IDX                                                                    2
>+#define mmDIG3_AFMT_MPEG_INFO0                                                                         0x238a
>+#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX                                                                2
>+#define mmDIG3_AFMT_MPEG_INFO1                                                                         0x238b
>+#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX                                                                2
>+#define mmDIG3_AFMT_GENERIC_HDR                                                                        0x238c
>+#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX                                                               2
>+#define mmDIG3_AFMT_GENERIC_0                                                                          0x238d
>+#define mmDIG3_AFMT_GENERIC_0_BASE_IDX                                                                 2
>+#define mmDIG3_AFMT_GENERIC_1                                                                          0x238e
>+#define mmDIG3_AFMT_GENERIC_1_BASE_IDX                                                                 2
>+#define mmDIG3_AFMT_GENERIC_2                                                                          0x238f
>+#define mmDIG3_AFMT_GENERIC_2_BASE_IDX                                                                 2
>+#define mmDIG3_AFMT_GENERIC_3                                                                          0x2390
>+#define mmDIG3_AFMT_GENERIC_3_BASE_IDX                                                                 2
>+#define mmDIG3_AFMT_GENERIC_4                                                                          0x2391
>+#define mmDIG3_AFMT_GENERIC_4_BASE_IDX                                                                 2
>+#define mmDIG3_AFMT_GENERIC_5                                                                          0x2392
>+#define mmDIG3_AFMT_GENERIC_5_BASE_IDX                                                                 2
>+#define mmDIG3_AFMT_GENERIC_6                                                                          0x2393
>+#define mmDIG3_AFMT_GENERIC_6_BASE_IDX                                                                 2
>+#define mmDIG3_AFMT_GENERIC_7                                                                          0x2394
>+#define mmDIG3_AFMT_GENERIC_7_BASE_IDX                                                                 2
>+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2395
>+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
>+#define mmDIG3_HDMI_ACR_32_0                                                                           0x2396
>+#define mmDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
>+#define mmDIG3_HDMI_ACR_32_1                                                                           0x2397
>+#define mmDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
>+#define mmDIG3_HDMI_ACR_44_0                                                                           0x2398
>+#define mmDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
>+#define mmDIG3_HDMI_ACR_44_1                                                                           0x2399
>+#define mmDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
>+#define mmDIG3_HDMI_ACR_48_0                                                                           0x239a
>+#define mmDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
>+#define mmDIG3_HDMI_ACR_48_1                                                                           0x239b
>+#define mmDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
>+#define mmDIG3_HDMI_ACR_STATUS_0                                                                       0x239c
>+#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
>+#define mmDIG3_HDMI_ACR_STATUS_1                                                                       0x239d
>+#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
>+#define mmDIG3_AFMT_AUDIO_INFO0                                                                        0x239e
>+#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
>+#define mmDIG3_AFMT_AUDIO_INFO1                                                                        0x239f
>+#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
>+#define mmDIG3_AFMT_60958_0                                                                            0x23a0
>+#define mmDIG3_AFMT_60958_0_BASE_IDX                                                                   2
>+#define mmDIG3_AFMT_60958_1                                                                            0x23a1
>+#define mmDIG3_AFMT_60958_1_BASE_IDX                                                                   2
>+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL                                                                  0x23a2
>+#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
>+#define mmDIG3_AFMT_RAMP_CONTROL0                                                                      0x23a3
>+#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
>+#define mmDIG3_AFMT_RAMP_CONTROL1                                                                      0x23a4
>+#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
>+#define mmDIG3_AFMT_RAMP_CONTROL2                                                                      0x23a5
>+#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
>+#define mmDIG3_AFMT_RAMP_CONTROL3                                                                      0x23a6
>+#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
>+#define mmDIG3_AFMT_60958_2                                                                            0x23a7
>+#define mmDIG3_AFMT_60958_2_BASE_IDX                                                                   2
>+#define mmDIG3_AFMT_AUDIO_CRC_RESULT                                                                   0x23a8
>+#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
>+#define mmDIG3_AFMT_STATUS                                                                             0x23a9
>+#define mmDIG3_AFMT_STATUS_BASE_IDX                                                                    2
>+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL                                                               0x23aa
>+#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
>+#define mmDIG3_AFMT_VBI_PACKET_CONTROL                                                                 0x23ab
>+#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG3_AFMT_INFOFRAME_CONTROL0                                                                 0x23ac
>+#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
>+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL                                                                  0x23ad
>+#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
>+#define mmDIG3_DIG_BE_CNTL                                                                             0x23af
>+#define mmDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
>+#define mmDIG3_DIG_BE_EN_CNTL                                                                          0x23b0
>+#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
>+#define mmDIG3_TMDS_CNTL                                                                               0x23d3
>+#define mmDIG3_TMDS_CNTL_BASE_IDX                                                                      2
>+#define mmDIG3_TMDS_CONTROL_CHAR                                                                       0x23d4
>+#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
>+#define mmDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x23d5
>+#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
>+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x23d6
>+#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
>+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x23d7
>+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
>+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x23d8
>+#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
>+#define mmDIG3_TMDS_CTL_BITS                                                                           0x23da
>+#define mmDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
>+#define mmDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x23db
>+#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
>+#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x23dc
>+#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
>+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x23dd
>+#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
>+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x23de
>+#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
>+#define mmDIG3_DIG_VERSION                                                                             0x23e0
>+#define mmDIG3_DIG_VERSION_BASE_IDX                                                                    2
>+#define mmDIG3_DIG_LANE_ENABLE                                                                         0x23e1
>+#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX                                                                2
>+#define mmDIG3_AFMT_CNTL                                                                               0x23e6
>+#define mmDIG3_AFMT_CNTL_BASE_IDX                                                                      2
>+#define mmDIG3_AFMT_VBI_PACKET_CONTROL1                                                                0x23e7
>+#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
>+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x23f6
>+#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
>+#define mmDIG3_FORCE_DIG_DISABLE                                                                       0x23f7
>+#define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dio_dp3_dispdec
>+// base address: 0xc00
>+#define mmDP3_DP_LINK_CNTL                                                                             0x2408
>+#define mmDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
>+#define mmDP3_DP_PIXEL_FORMAT                                                                          0x2409
>+#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
>+#define mmDP3_DP_MSA_COLORIMETRY                                                                       0x240a
>+#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
>+#define mmDP3_DP_CONFIG                                                                                0x240b
>+#define mmDP3_DP_CONFIG_BASE_IDX                                                                       2
>+#define mmDP3_DP_VID_STREAM_CNTL                                                                       0x240c
>+#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
>+#define mmDP3_DP_STEER_FIFO                                                                            0x240d
>+#define mmDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
>+#define mmDP3_DP_MSA_MISC                                                                              0x240e
>+#define mmDP3_DP_MSA_MISC_BASE_IDX                                                                     2
>+#define mmDP3_DP_VID_TIMING                                                                            0x2410
>+#define mmDP3_DP_VID_TIMING_BASE_IDX                                                                   2
>+#define mmDP3_DP_VID_N                                                                                 0x2411
>+#define mmDP3_DP_VID_N_BASE_IDX                                                                        2
>+#define mmDP3_DP_VID_M                                                                                 0x2412
>+#define mmDP3_DP_VID_M_BASE_IDX                                                                        2
>+#define mmDP3_DP_LINK_FRAMING_CNTL                                                                     0x2413
>+#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
>+#define mmDP3_DP_HBR2_EYE_PATTERN                                                                      0x2414
>+#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
>+#define mmDP3_DP_VID_MSA_VBID                                                                          0x2415
>+#define mmDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
>+#define mmDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2416
>+#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
>+#define mmDP3_DP_DPHY_CNTL                                                                             0x2417
>+#define mmDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
>+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2418
>+#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
>+#define mmDP3_DP_DPHY_SYM0                                                                             0x2419
>+#define mmDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
>+#define mmDP3_DP_DPHY_SYM1                                                                             0x241a
>+#define mmDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
>+#define mmDP3_DP_DPHY_SYM2                                                                             0x241b
>+#define mmDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
>+#define mmDP3_DP_DPHY_8B10B_CNTL                                                                       0x241c
>+#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
>+#define mmDP3_DP_DPHY_PRBS_CNTL                                                                        0x241d
>+#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
>+#define mmDP3_DP_DPHY_SCRAM_CNTL                                                                       0x241e
>+#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
>+#define mmDP3_DP_DPHY_CRC_EN                                                                           0x241f
>+#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
>+#define mmDP3_DP_DPHY_CRC_CNTL                                                                         0x2420
>+#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
>+#define mmDP3_DP_DPHY_CRC_RESULT                                                                       0x2421
>+#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
>+#define mmDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x2422
>+#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
>+#define mmDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x2423
>+#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
>+#define mmDP3_DP_DPHY_FAST_TRAINING                                                                    0x2424
>+#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
>+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2425
>+#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
>+#define mmDP3_DP_SEC_CNTL                                                                              0x242b
>+#define mmDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
>+#define mmDP3_DP_SEC_CNTL1                                                                             0x242c
>+#define mmDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
>+#define mmDP3_DP_SEC_FRAMING1                                                                          0x242d
>+#define mmDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
>+#define mmDP3_DP_SEC_FRAMING2                                                                          0x242e
>+#define mmDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
>+#define mmDP3_DP_SEC_FRAMING3                                                                          0x242f
>+#define mmDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
>+#define mmDP3_DP_SEC_FRAMING4                                                                          0x2430
>+#define mmDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
>+#define mmDP3_DP_SEC_AUD_N                                                                             0x2431
>+#define mmDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
>+#define mmDP3_DP_SEC_AUD_N_READBACK                                                                    0x2432
>+#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
>+#define mmDP3_DP_SEC_AUD_M                                                                             0x2433
>+#define mmDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
>+#define mmDP3_DP_SEC_AUD_M_READBACK                                                                    0x2434
>+#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
>+#define mmDP3_DP_SEC_TIMESTAMP                                                                         0x2435
>+#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
>+#define mmDP3_DP_SEC_PACKET_CNTL                                                                       0x2436
>+#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
>+#define mmDP3_DP_MSE_RATE_CNTL                                                                         0x2437
>+#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
>+#define mmDP3_DP_MSE_RATE_UPDATE                                                                       0x2439
>+#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
>+#define mmDP3_DP_MSE_SAT0                                                                              0x243a
>+#define mmDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
>+#define mmDP3_DP_MSE_SAT1                                                                              0x243b
>+#define mmDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
>+#define mmDP3_DP_MSE_SAT2                                                                              0x243c
>+#define mmDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
>+#define mmDP3_DP_MSE_SAT_UPDATE                                                                        0x243d
>+#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
>+#define mmDP3_DP_MSE_LINK_TIMING                                                                       0x243e
>+#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
>+#define mmDP3_DP_MSE_MISC_CNTL                                                                         0x243f
>+#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
>+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2444
>+#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
>+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2445
>+#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
>+#define mmDP3_DP_MSE_SAT0_STATUS                                                                       0x2447
>+#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
>+#define mmDP3_DP_MSE_SAT1_STATUS                                                                       0x2448
>+#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
>+#define mmDP3_DP_MSE_SAT2_STATUS                                                                       0x2449
>+#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
>+#define mmDP3_DP_MSA_TIMING_PARAM1                                                                     0x244c
>+#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
>+#define mmDP3_DP_MSA_TIMING_PARAM2                                                                     0x244d
>+#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
>+#define mmDP3_DP_MSA_TIMING_PARAM3                                                                     0x244e
>+#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
>+#define mmDP3_DP_MSA_TIMING_PARAM4                                                                     0x244f
>+#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
>+#define mmDP3_DP_MSO_CNTL                                                                              0x2450
>+#define mmDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
>+#define mmDP3_DP_MSO_CNTL1                                                                             0x2451
>+#define mmDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
>+#define mmDP3_DP_DSC_CNTL                                                                              0x2452
>+#define mmDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
>+#define mmDP3_DP_SEC_CNTL2                                                                             0x2453
>+#define mmDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
>+#define mmDP3_DP_SEC_CNTL3                                                                             0x2454
>+#define mmDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
>+#define mmDP3_DP_SEC_CNTL4                                                                             0x2455
>+#define mmDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
>+#define mmDP3_DP_SEC_CNTL5                                                                             0x2456
>+#define mmDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
>+#define mmDP3_DP_SEC_CNTL6                                                                             0x2457
>+#define mmDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
>+#define mmDP3_DP_SEC_CNTL7                                                                             0x2458
>+#define mmDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
>+#define mmDP3_DP_DB_CNTL                                                                               0x2459
>+#define mmDP3_DP_DB_CNTL_BASE_IDX                                                                      2
>+#define mmDP3_DP_MSA_VBID_MISC                                                                         0x245a
>+#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
>+#define mmDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x245b
>+#define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
>+#define mmDP3_DP_DSC_BYTES_PER_PIXEL                                                                   0x245c
>+#define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
>+#define mmDP3_DP_ALPM_CNTL                                                                             0x245d
>+#define mmDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
>+
>+
>+// addressBlock: dce_dc_dio_dig4_dispdec
>+// base address: 0x1000
>+#define mmDIG4_DIG_FE_CNTL                                                                             0x2468
>+#define mmDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2
>+#define mmDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x2469
>+#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
>+#define mmDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x246a
>+#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
>+#define mmDIG4_DIG_CLOCK_PATTERN                                                                       0x246b
>+#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
>+#define mmDIG4_DIG_TEST_PATTERN                                                                        0x246c
>+#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2
>+#define mmDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x246d
>+#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
>+#define mmDIG4_DIG_FIFO_STATUS                                                                         0x246e
>+#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX                                                                2
>+#define mmDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x246f
>+#define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
>+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x2470
>+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
>+#define mmDIG4_HDMI_CONTROL                                                                            0x2471
>+#define mmDIG4_HDMI_CONTROL_BASE_IDX                                                                   2
>+#define mmDIG4_HDMI_STATUS                                                                             0x2472
>+#define mmDIG4_HDMI_STATUS_BASE_IDX                                                                    2
>+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2473
>+#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
>+#define mmDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2474
>+#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2475
>+#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2476
>+#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
>+#define mmDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x2477
>+#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
>+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x2478
>+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
>+#define mmDIG4_AFMT_INTERRUPT_STATUS                                                                   0x2479
>+#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                          2
>+#define mmDIG4_HDMI_GC                                                                                 0x247b
>+#define mmDIG4_HDMI_GC_BASE_IDX                                                                        2
>+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2                                                              0x247c
>+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                     2
>+#define mmDIG4_AFMT_ISRC1_0                                                                            0x247d
>+#define mmDIG4_AFMT_ISRC1_0_BASE_IDX                                                                   2
>+#define mmDIG4_AFMT_ISRC1_1                                                                            0x247e
>+#define mmDIG4_AFMT_ISRC1_1_BASE_IDX                                                                   2
>+#define mmDIG4_AFMT_ISRC1_2                                                                            0x247f
>+#define mmDIG4_AFMT_ISRC1_2_BASE_IDX                                                                   2
>+#define mmDIG4_AFMT_ISRC1_3                                                                            0x2480
>+#define mmDIG4_AFMT_ISRC1_3_BASE_IDX                                                                   2
>+#define mmDIG4_AFMT_ISRC1_4                                                                            0x2481
>+#define mmDIG4_AFMT_ISRC1_4_BASE_IDX                                                                   2
>+#define mmDIG4_AFMT_ISRC2_0                                                                            0x2482
>+#define mmDIG4_AFMT_ISRC2_0_BASE_IDX                                                                   2
>+#define mmDIG4_AFMT_ISRC2_1                                                                            0x2483
>+#define mmDIG4_AFMT_ISRC2_1_BASE_IDX                                                                   2
>+#define mmDIG4_AFMT_ISRC2_2                                                                            0x2484
>+#define mmDIG4_AFMT_ISRC2_2_BASE_IDX                                                                   2
>+#define mmDIG4_AFMT_ISRC2_3                                                                            0x2485
>+#define mmDIG4_AFMT_ISRC2_3_BASE_IDX                                                                   2
>+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x2486
>+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
>+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x2487
>+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
>+#define mmDIG4_HDMI_DB_CONTROL                                                                         0x2488
>+#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2
>+#define mmDIG4_DME_CONTROL                                                                             0x2489
>+#define mmDIG4_DME_CONTROL_BASE_IDX                                                                    2
>+#define mmDIG4_AFMT_MPEG_INFO0                                                                         0x248a
>+#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX                                                                2
>+#define mmDIG4_AFMT_MPEG_INFO1                                                                         0x248b
>+#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX                                                                2
>+#define mmDIG4_AFMT_GENERIC_HDR                                                                        0x248c
>+#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX                                                               2
>+#define mmDIG4_AFMT_GENERIC_0                                                                          0x248d
>+#define mmDIG4_AFMT_GENERIC_0_BASE_IDX                                                                 2
>+#define mmDIG4_AFMT_GENERIC_1                                                                          0x248e
>+#define mmDIG4_AFMT_GENERIC_1_BASE_IDX                                                                 2
>+#define mmDIG4_AFMT_GENERIC_2                                                                          0x248f
>+#define mmDIG4_AFMT_GENERIC_2_BASE_IDX                                                                 2
>+#define mmDIG4_AFMT_GENERIC_3                                                                          0x2490
>+#define mmDIG4_AFMT_GENERIC_3_BASE_IDX                                                                 2
>+#define mmDIG4_AFMT_GENERIC_4                                                                          0x2491
>+#define mmDIG4_AFMT_GENERIC_4_BASE_IDX                                                                 2
>+#define mmDIG4_AFMT_GENERIC_5                                                                          0x2492
>+#define mmDIG4_AFMT_GENERIC_5_BASE_IDX                                                                 2
>+#define mmDIG4_AFMT_GENERIC_6                                                                          0x2493
>+#define mmDIG4_AFMT_GENERIC_6_BASE_IDX                                                                 2
>+#define mmDIG4_AFMT_GENERIC_7                                                                          0x2494
>+#define mmDIG4_AFMT_GENERIC_7_BASE_IDX                                                                 2
>+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x2495
>+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
>+#define mmDIG4_HDMI_ACR_32_0                                                                           0x2496
>+#define mmDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2
>+#define mmDIG4_HDMI_ACR_32_1                                                                           0x2497
>+#define mmDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2
>+#define mmDIG4_HDMI_ACR_44_0                                                                           0x2498
>+#define mmDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2
>+#define mmDIG4_HDMI_ACR_44_1                                                                           0x2499
>+#define mmDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2
>+#define mmDIG4_HDMI_ACR_48_0                                                                           0x249a
>+#define mmDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2
>+#define mmDIG4_HDMI_ACR_48_1                                                                           0x249b
>+#define mmDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2
>+#define mmDIG4_HDMI_ACR_STATUS_0                                                                       0x249c
>+#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
>+#define mmDIG4_HDMI_ACR_STATUS_1                                                                       0x249d
>+#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
>+#define mmDIG4_AFMT_AUDIO_INFO0                                                                        0x249e
>+#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX                                                               2
>+#define mmDIG4_AFMT_AUDIO_INFO1                                                                        0x249f
>+#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX                                                               2
>+#define mmDIG4_AFMT_60958_0                                                                            0x24a0
>+#define mmDIG4_AFMT_60958_0_BASE_IDX                                                                   2
>+#define mmDIG4_AFMT_60958_1                                                                            0x24a1
>+#define mmDIG4_AFMT_60958_1_BASE_IDX                                                                   2
>+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL                                                                  0x24a2
>+#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                         2
>+#define mmDIG4_AFMT_RAMP_CONTROL0                                                                      0x24a3
>+#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX                                                             2
>+#define mmDIG4_AFMT_RAMP_CONTROL1                                                                      0x24a4
>+#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX                                                             2
>+#define mmDIG4_AFMT_RAMP_CONTROL2                                                                      0x24a5
>+#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX                                                             2
>+#define mmDIG4_AFMT_RAMP_CONTROL3                                                                      0x24a6
>+#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX                                                             2
>+#define mmDIG4_AFMT_60958_2                                                                            0x24a7
>+#define mmDIG4_AFMT_60958_2_BASE_IDX                                                                   2
>+#define mmDIG4_AFMT_AUDIO_CRC_RESULT                                                                   0x24a8
>+#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                          2
>+#define mmDIG4_AFMT_STATUS                                                                             0x24a9
>+#define mmDIG4_AFMT_STATUS_BASE_IDX                                                                    2
>+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL                                                               0x24aa
>+#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
>+#define mmDIG4_AFMT_VBI_PACKET_CONTROL                                                                 0x24ab
>+#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                        2
>+#define mmDIG4_AFMT_INFOFRAME_CONTROL0                                                                 0x24ac
>+#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                        2
>+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL                                                                  0x24ad
>+#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                         2
>+#define mmDIG4_DIG_BE_CNTL                                                                             0x24af
>+#define mmDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2
>+#define mmDIG4_DIG_BE_EN_CNTL                                                                          0x24b0
>+#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
>+#define mmDIG4_TMDS_CNTL                                                                               0x24d3
>+#define mmDIG4_TMDS_CNTL_BASE_IDX                                                                      2
>+#define mmDIG4_TMDS_CONTROL_CHAR                                                                       0x24d4
>+#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
>+#define mmDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x24d5
>+#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
>+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x24d6
>+#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
>+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x24d7
>+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
>+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x24d8
>+#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
>+#define mmDIG4_TMDS_CTL_BITS                                                                           0x24da
>+#define mmDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2
>+#define mmDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x24db
>+#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
>+#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x24dc
>+#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
>+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x24dd
>+#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
>+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x24de
>+#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
>+#define mmDIG4_DIG_VERSION                                                                             0x24e0
>+#define mmDIG4_DIG_VERSION_BASE_IDX                                                                    2
>+#define mmDIG4_DIG_LANE_ENABLE                                                                         0x24e1
>+#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX                                                                2
>+#define mmDIG4_AFMT_CNTL                                                                               0x24e6
>+#define mmDIG4_AFMT_CNTL_BASE_IDX                                                                      2
>+#define mmDIG4_AFMT_VBI_PACKET_CONTROL1                                                                0x24e7
>+#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX                                                       2
>+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x24f6
>+#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
>+#define mmDIG4_FORCE_DIG_DISABLE                                                                       0x24f7
>+#define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dio_dp4_dispdec
>+// base address: 0x1000
>+#define mmDP4_DP_LINK_CNTL                                                                             0x2508
>+#define mmDP4_DP_LINK_CNTL_BASE_IDX                                                                    2
>+#define mmDP4_DP_PIXEL_FORMAT                                                                          0x2509
>+#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
>+#define mmDP4_DP_MSA_COLORIMETRY                                                                       0x250a
>+#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
>+#define mmDP4_DP_CONFIG                                                                                0x250b
>+#define mmDP4_DP_CONFIG_BASE_IDX                                                                       2
>+#define mmDP4_DP_VID_STREAM_CNTL                                                                       0x250c
>+#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
>+#define mmDP4_DP_STEER_FIFO                                                                            0x250d
>+#define mmDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
>+#define mmDP4_DP_MSA_MISC                                                                              0x250e
>+#define mmDP4_DP_MSA_MISC_BASE_IDX                                                                     2
>+#define mmDP4_DP_VID_TIMING                                                                            0x2510
>+#define mmDP4_DP_VID_TIMING_BASE_IDX                                                                   2
>+#define mmDP4_DP_VID_N                                                                                 0x2511
>+#define mmDP4_DP_VID_N_BASE_IDX                                                                        2
>+#define mmDP4_DP_VID_M                                                                                 0x2512
>+#define mmDP4_DP_VID_M_BASE_IDX                                                                        2
>+#define mmDP4_DP_LINK_FRAMING_CNTL                                                                     0x2513
>+#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
>+#define mmDP4_DP_HBR2_EYE_PATTERN                                                                      0x2514
>+#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
>+#define mmDP4_DP_VID_MSA_VBID                                                                          0x2515
>+#define mmDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2
>+#define mmDP4_DP_VID_INTERRUPT_CNTL                                                                    0x2516
>+#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
>+#define mmDP4_DP_DPHY_CNTL                                                                             0x2517
>+#define mmDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2
>+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2518
>+#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
>+#define mmDP4_DP_DPHY_SYM0                                                                             0x2519
>+#define mmDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2
>+#define mmDP4_DP_DPHY_SYM1                                                                             0x251a
>+#define mmDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2
>+#define mmDP4_DP_DPHY_SYM2                                                                             0x251b
>+#define mmDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2
>+#define mmDP4_DP_DPHY_8B10B_CNTL                                                                       0x251c
>+#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
>+#define mmDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d
>+#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
>+#define mmDP4_DP_DPHY_SCRAM_CNTL                                                                       0x251e
>+#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
>+#define mmDP4_DP_DPHY_CRC_EN                                                                           0x251f
>+#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
>+#define mmDP4_DP_DPHY_CRC_CNTL                                                                         0x2520
>+#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
>+#define mmDP4_DP_DPHY_CRC_RESULT                                                                       0x2521
>+#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
>+#define mmDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x2522
>+#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
>+#define mmDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x2523
>+#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
>+#define mmDP4_DP_DPHY_FAST_TRAINING                                                                    0x2524
>+#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
>+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2525
>+#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
>+#define mmDP4_DP_SEC_CNTL                                                                              0x252b
>+#define mmDP4_DP_SEC_CNTL_BASE_IDX                                                                     2
>+#define mmDP4_DP_SEC_CNTL1                                                                             0x252c
>+#define mmDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2
>+#define mmDP4_DP_SEC_FRAMING1                                                                          0x252d
>+#define mmDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2
>+#define mmDP4_DP_SEC_FRAMING2                                                                          0x252e
>+#define mmDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2
>+#define mmDP4_DP_SEC_FRAMING3                                                                          0x252f
>+#define mmDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2
>+#define mmDP4_DP_SEC_FRAMING4                                                                          0x2530
>+#define mmDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2
>+#define mmDP4_DP_SEC_AUD_N                                                                             0x2531
>+#define mmDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2
>+#define mmDP4_DP_SEC_AUD_N_READBACK                                                                    0x2532
>+#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
>+#define mmDP4_DP_SEC_AUD_M                                                                             0x2533
>+#define mmDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2
>+#define mmDP4_DP_SEC_AUD_M_READBACK                                                                    0x2534
>+#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
>+#define mmDP4_DP_SEC_TIMESTAMP                                                                         0x2535
>+#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
>+#define mmDP4_DP_SEC_PACKET_CNTL                                                                       0x2536
>+#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
>+#define mmDP4_DP_MSE_RATE_CNTL                                                                         0x2537
>+#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
>+#define mmDP4_DP_MSE_RATE_UPDATE                                                                       0x2539
>+#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
>+#define mmDP4_DP_MSE_SAT0                                                                              0x253a
>+#define mmDP4_DP_MSE_SAT0_BASE_IDX                                                                     2
>+#define mmDP4_DP_MSE_SAT1                                                                              0x253b
>+#define mmDP4_DP_MSE_SAT1_BASE_IDX                                                                     2
>+#define mmDP4_DP_MSE_SAT2                                                                              0x253c
>+#define mmDP4_DP_MSE_SAT2_BASE_IDX                                                                     2
>+#define mmDP4_DP_MSE_SAT_UPDATE                                                                        0x253d
>+#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
>+#define mmDP4_DP_MSE_LINK_TIMING                                                                       0x253e
>+#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
>+#define mmDP4_DP_MSE_MISC_CNTL                                                                         0x253f
>+#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
>+#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2544
>+#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
>+#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2545
>+#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
>+#define mmDP4_DP_MSE_SAT0_STATUS                                                                       0x2547
>+#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
>+#define mmDP4_DP_MSE_SAT1_STATUS                                                                       0x2548
>+#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
>+#define mmDP4_DP_MSE_SAT2_STATUS                                                                       0x2549
>+#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
>+#define mmDP4_DP_MSA_TIMING_PARAM1                                                                     0x254c
>+#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
>+#define mmDP4_DP_MSA_TIMING_PARAM2                                                                     0x254d
>+#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
>+#define mmDP4_DP_MSA_TIMING_PARAM3                                                                     0x254e
>+#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
>+#define mmDP4_DP_MSA_TIMING_PARAM4                                                                     0x254f
>+#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
>+#define mmDP4_DP_MSO_CNTL                                                                              0x2550
>+#define mmDP4_DP_MSO_CNTL_BASE_IDX                                                                     2
>+#define mmDP4_DP_MSO_CNTL1                                                                             0x2551
>+#define mmDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2
>+#define mmDP4_DP_DSC_CNTL                                                                              0x2552
>+#define mmDP4_DP_DSC_CNTL_BASE_IDX                                                                     2
>+#define mmDP4_DP_SEC_CNTL2                                                                             0x2553
>+#define mmDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2
>+#define mmDP4_DP_SEC_CNTL3                                                                             0x2554
>+#define mmDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2
>+#define mmDP4_DP_SEC_CNTL4                                                                             0x2555
>+#define mmDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2
>+#define mmDP4_DP_SEC_CNTL5                                                                             0x2556
>+#define mmDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2
>+#define mmDP4_DP_SEC_CNTL6                                                                             0x2557
>+#define mmDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2
>+#define mmDP4_DP_SEC_CNTL7                                                                             0x2558
>+#define mmDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2
>+#define mmDP4_DP_DB_CNTL                                                                               0x2559
>+#define mmDP4_DP_DB_CNTL_BASE_IDX                                                                      2
>+#define mmDP4_DP_MSA_VBID_MISC                                                                         0x255a
>+#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2
>+#define mmDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x255b
>+#define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
>+#define mmDP4_DP_DSC_BYTES_PER_PIXEL                                                                   0x255c
>+#define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
>+#define mmDP4_DP_ALPM_CNTL                                                                             0x255d
>+#define mmDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2
>+
>+
>+// addressBlock: dce_dc_dcio_dcio_dispdec
>+// base address: 0x0
>+#define mmDC_GENERICA                                                                                  0x2868
>+#define mmDC_GENERICA_BASE_IDX                                                                         2
>+#define mmDC_GENERICB                                                                                  0x2869
>+#define mmDC_GENERICB_BASE_IDX                                                                         2
>+#define mmDC_REF_CLK_CNTL                                                                              0x286b
>+#define mmDC_REF_CLK_CNTL_BASE_IDX                                                                     2
>+#define mmUNIPHYA_LINK_CNTL                                                                            0x286d
>+#define mmUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
>+#define mmUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
>+#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
>+#define mmUNIPHYB_LINK_CNTL                                                                            0x286f
>+#define mmUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
>+#define mmUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
>+#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
>+#define mmUNIPHYC_LINK_CNTL                                                                            0x2871
>+#define mmUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
>+#define mmUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
>+#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
>+#define mmUNIPHYD_LINK_CNTL                                                                            0x2873
>+#define mmUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
>+#define mmUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
>+#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
>+#define mmUNIPHYE_LINK_CNTL                                                                            0x2875
>+#define mmUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2
>+#define mmUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
>+#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
>+#define mmDCIO_WRCMD_DELAY                                                                             0x287e
>+#define mmDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
>+#define mmDC_PINSTRAPS                                                                                 0x2880
>+#define mmDC_PINSTRAPS_BASE_IDX                                                                        2
>+#define mmLVTMA_PWRSEQ_CNTL                                                                            0x2883
>+#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX                                                                   2
>+#define mmLVTMA_PWRSEQ_STATE                                                                           0x2884
>+#define mmLVTMA_PWRSEQ_STATE_BASE_IDX                                                                  2
>+#define mmLVTMA_PWRSEQ_REF_DIV                                                                         0x2885
>+#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX                                                                2
>+#define mmLVTMA_PWRSEQ_DELAY1                                                                          0x2886
>+#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX                                                                 2
>+#define mmLVTMA_PWRSEQ_DELAY2                                                                          0x2887
>+#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX                                                                 2
>+#define mmBL_PWM_CNTL                                                                                  0x2888
>+#define mmBL_PWM_CNTL_BASE_IDX                                                                         2
>+#define mmBL_PWM_CNTL2                                                                                 0x2889
>+#define mmBL_PWM_CNTL2_BASE_IDX                                                                        2
>+#define mmBL_PWM_PERIOD_CNTL                                                                           0x288a
>+#define mmBL_PWM_PERIOD_CNTL_BASE_IDX                                                                  2
>+#define mmBL_PWM_GRP1_REG_LOCK                                                                         0x288b
>+#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX                                                                2
>+#define mmDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
>+#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
>+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
>+#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
>+#define mmDCIO_CLOCK_CNTL                                                                              0x2895
>+#define mmDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
>+#define mmDCIO_SOFT_RESET                                                                              0x289e
>+#define mmDCIO_SOFT_RESET_BASE_IDX                                                                     2
>+
>+
>+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
>+// base address: 0x0
>+#define mmDC_GPIO_GENERIC_MASK                                                                         0x28c8
>+#define mmDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
>+#define mmDC_GPIO_GENERIC_A                                                                            0x28c9
>+#define mmDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
>+#define mmDC_GPIO_GENERIC_EN                                                                           0x28ca
>+#define mmDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
>+#define mmDC_GPIO_GENERIC_Y                                                                            0x28cb
>+#define mmDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
>+#define mmDC_GPIO_DDC1_MASK                                                                            0x28d0
>+#define mmDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
>+#define mmDC_GPIO_DDC1_A                                                                               0x28d1
>+#define mmDC_GPIO_DDC1_A_BASE_IDX                                                                      2
>+#define mmDC_GPIO_DDC1_EN                                                                              0x28d2
>+#define mmDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
>+#define mmDC_GPIO_DDC1_Y                                                                               0x28d3
>+#define mmDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
>+#define mmDC_GPIO_DDC2_MASK                                                                            0x28d4
>+#define mmDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
>+#define mmDC_GPIO_DDC2_A                                                                               0x28d5
>+#define mmDC_GPIO_DDC2_A_BASE_IDX                                                                      2
>+#define mmDC_GPIO_DDC2_EN                                                                              0x28d6
>+#define mmDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
>+#define mmDC_GPIO_DDC2_Y                                                                               0x28d7
>+#define mmDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
>+#define mmDC_GPIO_DDC3_MASK                                                                            0x28d8
>+#define mmDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
>+#define mmDC_GPIO_DDC3_A                                                                               0x28d9
>+#define mmDC_GPIO_DDC3_A_BASE_IDX                                                                      2
>+#define mmDC_GPIO_DDC3_EN                                                                              0x28da
>+#define mmDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
>+#define mmDC_GPIO_DDC3_Y                                                                               0x28db
>+#define mmDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
>+#define mmDC_GPIO_DDC4_MASK                                                                            0x28dc
>+#define mmDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
>+#define mmDC_GPIO_DDC4_A                                                                               0x28dd
>+#define mmDC_GPIO_DDC4_A_BASE_IDX                                                                      2
>+#define mmDC_GPIO_DDC4_EN                                                                              0x28de
>+#define mmDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
>+#define mmDC_GPIO_DDC4_Y                                                                               0x28df
>+#define mmDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
>+#define mmDC_GPIO_DDC5_MASK                                                                            0x28e0
>+#define mmDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
>+#define mmDC_GPIO_DDC5_A                                                                               0x28e1
>+#define mmDC_GPIO_DDC5_A_BASE_IDX                                                                      2
>+#define mmDC_GPIO_DDC5_EN                                                                              0x28e2
>+#define mmDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
>+#define mmDC_GPIO_DDC5_Y                                                                               0x28e3
>+#define mmDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
>+#define mmDC_GPIO_DDCVGA_MASK                                                                          0x28e8
>+#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
>+#define mmDC_GPIO_DDCVGA_A                                                                             0x28e9
>+#define mmDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
>+#define mmDC_GPIO_DDCVGA_EN                                                                            0x28ea
>+#define mmDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
>+#define mmDC_GPIO_DDCVGA_Y                                                                             0x28eb
>+#define mmDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
>+#define mmDC_GPIO_GENLK_MASK                                                                           0x28f0
>+#define mmDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
>+#define mmDC_GPIO_GENLK_A                                                                              0x28f1
>+#define mmDC_GPIO_GENLK_A_BASE_IDX                                                                     2
>+#define mmDC_GPIO_GENLK_EN                                                                             0x28f2
>+#define mmDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
>+#define mmDC_GPIO_GENLK_Y                                                                              0x28f3
>+#define mmDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
>+#define mmDC_GPIO_HPD_MASK                                                                             0x28f4
>+#define mmDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
>+#define mmDC_GPIO_HPD_A                                                                                0x28f5
>+#define mmDC_GPIO_HPD_A_BASE_IDX                                                                       2
>+#define mmDC_GPIO_HPD_EN                                                                               0x28f6
>+#define mmDC_GPIO_HPD_EN_BASE_IDX                                                                      2
>+#define mmDC_GPIO_HPD_Y                                                                                0x28f7
>+#define mmDC_GPIO_HPD_Y_BASE_IDX                                                                       2
>+#define mmDC_GPIO_PWRSEQ_MASK                                                                          0x28f8
>+#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX                                                                 2
>+#define mmDC_GPIO_PWRSEQ_A                                                                             0x28f9
>+#define mmDC_GPIO_PWRSEQ_A_BASE_IDX                                                                    2
>+#define mmDC_GPIO_PWRSEQ_EN                                                                            0x28fa
>+#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX                                                                   2
>+#define mmDC_GPIO_PWRSEQ_Y                                                                             0x28fb
>+#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX                                                                    2
>+#define mmDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
>+#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
>+#define mmDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
>+#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
>+#define mmPHY_AUX_CNTL                                                                                 0x28ff
>+#define mmPHY_AUX_CNTL_BASE_IDX                                                                        2
>+#define mmDC_GPIO_TX12_EN                                                                              0x2915
>+#define mmDC_GPIO_TX12_EN_BASE_IDX                                                                     2
>+#define mmDC_GPIO_AUX_CTRL_0                                                                           0x2916
>+#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
>+#define mmDC_GPIO_AUX_CTRL_1                                                                           0x2917
>+#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
>+#define mmDC_GPIO_AUX_CTRL_2                                                                           0x2918
>+#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
>+#define mmDC_GPIO_RXEN                                                                                 0x2919
>+#define mmDC_GPIO_RXEN_BASE_IDX                                                                        2
>+#define mmDC_GPIO_PULLUPEN                                                                             0x291a
>+#define mmDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
>+#define mmDC_GPIO_AUX_CTRL_3                                                                           0x291b
>+#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
>+#define mmDC_GPIO_AUX_CTRL_4                                                                           0x291c
>+#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
>+#define mmDC_GPIO_AUX_CTRL_5                                                                           0x291d
>+#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
>+#define mmAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
>+#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
>+
>+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
>+// base address: 0x0
>+#define mmDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
>+#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
>+#define mmDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
>+#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
>+// base address: 0x0
>+#define mmDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
>+#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
>+#define mmDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
>+#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
>+// base address: 0x0
>+#define mmDSCC0_DSCC_CONFIG0                                                                           0x300a
>+#define mmDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
>+#define mmDSCC0_DSCC_CONFIG1                                                                           0x300b
>+#define mmDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
>+#define mmDSCC0_DSCC_STATUS                                                                            0x300c
>+#define mmDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
>+#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
>+#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
>+#define mmDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
>+#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
>+#define mmDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
>+#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
>+#define mmDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
>+#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
>+#define mmDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
>+#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
>+#define mmDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
>+#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
>+#define mmDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
>+#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
>+#define mmDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
>+#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
>+#define mmDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
>+#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
>+#define mmDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
>+#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
>+#define mmDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
>+#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
>+#define mmDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
>+#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
>+#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
>+#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
>+#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
>+#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
>+#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
>+#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
>+#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
>+#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
>+#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
>+#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
>+#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
>+#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
>+#define mmDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
>+#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
>+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
>+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
>+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
>+#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
>+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
>+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
>+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
>+#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
>+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
>+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
>+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
>+#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
>+#define mmDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
>+#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
>+#define mmDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
>+#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
>+#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
>+#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
>+#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
>+#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
>+#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
>+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
>+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
>+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
>+#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a
>+#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
>+
>+
>+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
>+// base address: 0xc140
>+#define mmDC_PERFMON19_PERFCOUNTER_CNTL                                                                0x3050
>+#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON19_PERFCOUNTER_CNTL2                                                               0x3051
>+#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON19_PERFCOUNTER_STATE                                                               0x3052
>+#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON19_PERFMON_CNTL                                                                    0x3053
>+#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON19_PERFMON_CNTL2                                                                   0x3054
>+#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC                                                         0x3055
>+#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON19_PERFMON_CVALUE_LOW                                                              0x3056
>+#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON19_PERFMON_HI                                                                      0x3057
>+#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON19_PERFMON_LOW                                                                     0x3058
>+#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
>+// base address: 0x170
>+#define mmDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
>+#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
>+#define mmDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
>+#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
>+// base address: 0x170
>+#define mmDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
>+#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
>+#define mmDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
>+#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
>+// base address: 0x170
>+#define mmDSCC1_DSCC_CONFIG0                                                                           0x3066
>+#define mmDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
>+#define mmDSCC1_DSCC_CONFIG1                                                                           0x3067
>+#define mmDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
>+#define mmDSCC1_DSCC_STATUS                                                                            0x3068
>+#define mmDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
>+#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
>+#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
>+#define mmDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
>+#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
>+#define mmDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
>+#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
>+#define mmDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
>+#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
>+#define mmDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
>+#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
>+#define mmDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
>+#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
>+#define mmDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
>+#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
>+#define mmDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
>+#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
>+#define mmDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
>+#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
>+#define mmDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
>+#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
>+#define mmDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
>+#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
>+#define mmDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
>+#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
>+#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
>+#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
>+#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
>+#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
>+#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
>+#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
>+#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
>+#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
>+#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
>+#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
>+#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
>+#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
>+#define mmDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
>+#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
>+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
>+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
>+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
>+#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
>+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
>+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
>+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
>+#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
>+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
>+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
>+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
>+#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
>+#define mmDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
>+#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
>+#define mmDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
>+#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
>+#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
>+#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
>+#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
>+#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
>+#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
>+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
>+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
>+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
>+#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096
>+#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
>+
>+
>+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
>+// base address: 0xc2b0
>+#define mmDC_PERFMON20_PERFCOUNTER_CNTL                                                                0x30ac
>+#define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON20_PERFCOUNTER_CNTL2                                                               0x30ad
>+#define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON20_PERFCOUNTER_STATE                                                               0x30ae
>+#define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON20_PERFMON_CNTL                                                                    0x30af
>+#define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON20_PERFMON_CNTL2                                                                   0x30b0
>+#define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC                                                         0x30b1
>+#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON20_PERFMON_CVALUE_LOW                                                              0x30b2
>+#define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON20_PERFMON_HI                                                                      0x30b3
>+#define mmDC_PERFMON20_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON20_PERFMON_LOW                                                                     0x30b4
>+#define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
>+// base address: 0x2e0
>+#define mmDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
>+#define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
>+#define mmDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
>+#define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
>+// base address: 0x2e0
>+#define mmDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
>+#define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
>+#define mmDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
>+#define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
>+// base address: 0x2e0
>+#define mmDSCC2_DSCC_CONFIG0                                                                           0x30c2
>+#define mmDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
>+#define mmDSCC2_DSCC_CONFIG1                                                                           0x30c3
>+#define mmDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
>+#define mmDSCC2_DSCC_STATUS                                                                            0x30c4
>+#define mmDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
>+#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
>+#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
>+#define mmDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
>+#define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
>+#define mmDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
>+#define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
>+#define mmDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
>+#define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
>+#define mmDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
>+#define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
>+#define mmDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
>+#define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
>+#define mmDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
>+#define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
>+#define mmDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
>+#define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
>+#define mmDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
>+#define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
>+#define mmDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
>+#define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
>+#define mmDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
>+#define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
>+#define mmDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
>+#define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
>+#define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
>+#define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
>+#define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
>+#define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
>+#define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
>+#define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
>+#define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
>+#define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
>+#define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
>+#define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
>+#define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
>+#define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
>+#define mmDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
>+#define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
>+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
>+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
>+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
>+#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
>+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
>+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
>+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
>+#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
>+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
>+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
>+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
>+#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
>+#define mmDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
>+#define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
>+#define mmDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
>+#define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
>+#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
>+#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
>+#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
>+#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
>+#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
>+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
>+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
>+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
>+#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2
>+#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
>+
>+
>+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
>+// base address: 0xc420
>+#define mmDC_PERFMON21_PERFCOUNTER_CNTL                                                                0x3108
>+#define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON21_PERFCOUNTER_CNTL2                                                               0x3109
>+#define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON21_PERFCOUNTER_STATE                                                               0x310a
>+#define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON21_PERFMON_CNTL                                                                    0x310b
>+#define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON21_PERFMON_CNTL2                                                                   0x310c
>+#define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC                                                         0x310d
>+#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON21_PERFMON_CVALUE_LOW                                                              0x310e
>+#define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON21_PERFMON_HI                                                                      0x310f
>+#define mmDC_PERFMON21_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON21_PERFMON_LOW                                                                     0x3110
>+#define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
>+// base address: 0x450
>+#define mmDSC_TOP3_DSC_TOP_CONTROL                                                                     0x3114
>+#define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX                                                            2
>+#define mmDSC_TOP3_DSC_DEBUG_CONTROL                                                                   0x3115
>+#define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
>+// base address: 0x450
>+#define mmDSCCIF3_DSCCIF_CONFIG0                                                                       0x3119
>+#define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX                                                              2
>+#define mmDSCCIF3_DSCCIF_CONFIG1                                                                       0x311a
>+#define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
>+// base address: 0x450
>+#define mmDSCC3_DSCC_CONFIG0                                                                           0x311e
>+#define mmDSCC3_DSCC_CONFIG0_BASE_IDX                                                                  2
>+#define mmDSCC3_DSCC_CONFIG1                                                                           0x311f
>+#define mmDSCC3_DSCC_CONFIG1_BASE_IDX                                                                  2
>+#define mmDSCC3_DSCC_STATUS                                                                            0x3120
>+#define mmDSCC3_DSCC_STATUS_BASE_IDX                                                                   2
>+#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3121
>+#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
>+#define mmDSCC3_DSCC_PPS_CONFIG0                                                                       0x3122
>+#define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
>+#define mmDSCC3_DSCC_PPS_CONFIG1                                                                       0x3123
>+#define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
>+#define mmDSCC3_DSCC_PPS_CONFIG2                                                                       0x3124
>+#define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
>+#define mmDSCC3_DSCC_PPS_CONFIG3                                                                       0x3125
>+#define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
>+#define mmDSCC3_DSCC_PPS_CONFIG4                                                                       0x3126
>+#define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
>+#define mmDSCC3_DSCC_PPS_CONFIG5                                                                       0x3127
>+#define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
>+#define mmDSCC3_DSCC_PPS_CONFIG6                                                                       0x3128
>+#define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
>+#define mmDSCC3_DSCC_PPS_CONFIG7                                                                       0x3129
>+#define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
>+#define mmDSCC3_DSCC_PPS_CONFIG8                                                                       0x312a
>+#define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
>+#define mmDSCC3_DSCC_PPS_CONFIG9                                                                       0x312b
>+#define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
>+#define mmDSCC3_DSCC_PPS_CONFIG10                                                                      0x312c
>+#define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_PPS_CONFIG11                                                                      0x312d
>+#define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_PPS_CONFIG12                                                                      0x312e
>+#define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_PPS_CONFIG13                                                                      0x312f
>+#define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_PPS_CONFIG14                                                                      0x3130
>+#define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_PPS_CONFIG15                                                                      0x3131
>+#define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_PPS_CONFIG16                                                                      0x3132
>+#define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_PPS_CONFIG17                                                                      0x3133
>+#define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_PPS_CONFIG18                                                                      0x3134
>+#define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_PPS_CONFIG19                                                                      0x3135
>+#define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_PPS_CONFIG20                                                                      0x3136
>+#define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_PPS_CONFIG21                                                                      0x3137
>+#define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_PPS_CONFIG22                                                                      0x3138
>+#define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
>+#define mmDSCC3_DSCC_MEM_POWER_CONTROL                                                                 0x3139
>+#define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
>+#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x313a
>+#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
>+#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x313b
>+#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
>+#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x313c
>+#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
>+#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x313d
>+#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
>+#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x313e
>+#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
>+#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x313f
>+#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
>+#define mmDSCC3_DSCC_MAX_ABS_ERROR0                                                                    0x3140
>+#define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
>+#define mmDSCC3_DSCC_MAX_ABS_ERROR1                                                                    0x3141
>+#define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
>+#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x3142
>+#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x3143
>+#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3144
>+#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3145
>+#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3146
>+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3147
>+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3148
>+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149
>+#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x314e
>+#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
>+
>+// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
>+// base address: 0xc590
>+#define mmDC_PERFMON22_PERFCOUNTER_CNTL                                                                0x3164
>+#define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON22_PERFCOUNTER_CNTL2                                                               0x3165
>+#define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON22_PERFCOUNTER_STATE                                                               0x3166
>+#define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON22_PERFMON_CNTL                                                                    0x3167
>+#define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON22_PERFMON_CNTL2                                                                   0x3168
>+#define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC                                                         0x3169
>+#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON22_PERFMON_CVALUE_LOW                                                              0x316a
>+#define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON22_PERFMON_HI                                                                      0x316b
>+#define mmDC_PERFMON22_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON22_PERFMON_LOW                                                                     0x316c
>+#define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec
>+// base address: 0x5c0
>+#define mmDSC_TOP4_DSC_TOP_CONTROL                                                                     0x3170
>+#define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX                                                            2
>+#define mmDSC_TOP4_DSC_DEBUG_CONTROL                                                                   0x3171
>+#define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec
>+// base address: 0x5c0
>+#define mmDSCCIF4_DSCCIF_CONFIG0                                                                       0x3175
>+#define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX                                                              2
>+#define mmDSCCIF4_DSCCIF_CONFIG1                                                                       0x3176
>+#define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec
>+// base address: 0x5c0
>+#define mmDSCC4_DSCC_CONFIG0                                                                           0x317a
>+#define mmDSCC4_DSCC_CONFIG0_BASE_IDX                                                                  2
>+#define mmDSCC4_DSCC_CONFIG1                                                                           0x317b
>+#define mmDSCC4_DSCC_CONFIG1_BASE_IDX                                                                  2
>+#define mmDSCC4_DSCC_STATUS                                                                            0x317c
>+#define mmDSCC4_DSCC_STATUS_BASE_IDX                                                                   2
>+#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x317d
>+#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
>+#define mmDSCC4_DSCC_PPS_CONFIG0                                                                       0x317e
>+#define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
>+#define mmDSCC4_DSCC_PPS_CONFIG1                                                                       0x317f
>+#define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
>+#define mmDSCC4_DSCC_PPS_CONFIG2                                                                       0x3180
>+#define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
>+#define mmDSCC4_DSCC_PPS_CONFIG3                                                                       0x3181
>+#define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
>+#define mmDSCC4_DSCC_PPS_CONFIG4                                                                       0x3182
>+#define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
>+#define mmDSCC4_DSCC_PPS_CONFIG5                                                                       0x3183
>+#define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
>+#define mmDSCC4_DSCC_PPS_CONFIG6                                                                       0x3184
>+#define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
>+#define mmDSCC4_DSCC_PPS_CONFIG7                                                                       0x3185
>+#define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
>+#define mmDSCC4_DSCC_PPS_CONFIG8                                                                       0x3186
>+#define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
>+#define mmDSCC4_DSCC_PPS_CONFIG9                                                                       0x3187
>+#define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
>+#define mmDSCC4_DSCC_PPS_CONFIG10                                                                      0x3188
>+#define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_PPS_CONFIG11                                                                      0x3189
>+#define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_PPS_CONFIG12                                                                      0x318a
>+#define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_PPS_CONFIG13                                                                      0x318b
>+#define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_PPS_CONFIG14                                                                      0x318c
>+#define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_PPS_CONFIG15                                                                      0x318d
>+#define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_PPS_CONFIG16                                                                      0x318e
>+#define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_PPS_CONFIG17                                                                      0x318f
>+#define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_PPS_CONFIG18                                                                      0x3190
>+#define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_PPS_CONFIG19                                                                      0x3191
>+#define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_PPS_CONFIG20                                                                      0x3192
>+#define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_PPS_CONFIG21                                                                      0x3193
>+#define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_PPS_CONFIG22                                                                      0x3194
>+#define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
>+#define mmDSCC4_DSCC_MEM_POWER_CONTROL                                                                 0x3195
>+#define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
>+#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3196
>+#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
>+#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3197
>+#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
>+#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3198
>+#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
>+#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3199
>+#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
>+#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x319a
>+#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
>+#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x319b
>+#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
>+#define mmDSCC4_DSCC_MAX_ABS_ERROR0                                                                    0x319c
>+#define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
>+#define mmDSCC4_DSCC_MAX_ABS_ERROR1                                                                    0x319d
>+#define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
>+#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x319e
>+#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x319f
>+#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x31a0
>+#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x31a1
>+#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x31a2
>+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x31a3
>+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x31a4
>+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x31a5
>+#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x31aa
>+#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
>+
>+// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
>+// base address: 0xc700
>+#define mmDC_PERFMON23_PERFCOUNTER_CNTL                                                                0x31c0
>+#define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON23_PERFCOUNTER_CNTL2                                                               0x31c1
>+#define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON23_PERFCOUNTER_STATE                                                               0x31c2
>+#define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON23_PERFMON_CNTL                                                                    0x31c3
>+#define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON23_PERFMON_CNTL2                                                                   0x31c4
>+#define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC                                                         0x31c5
>+#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON23_PERFMON_CVALUE_LOW                                                              0x31c6
>+#define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON23_PERFMON_HI                                                                      0x31c7
>+#define mmDC_PERFMON23_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON23_PERFMON_LOW                                                                     0x31c8
>+#define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec
>+// base address: 0x730
>+#define mmDSC_TOP5_DSC_TOP_CONTROL                                                                     0x31cc
>+#define mmDSC_TOP5_DSC_TOP_CONTROL_BASE_IDX                                                            2
>+#define mmDSC_TOP5_DSC_DEBUG_CONTROL                                                                   0x31cd
>+#define mmDSC_TOP5_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
>+
>+
>+// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec
>+// base address: 0x730
>+#define mmDSCCIF5_DSCCIF_CONFIG0                                                                       0x31d1
>+#define mmDSCCIF5_DSCCIF_CONFIG0_BASE_IDX                                                              2
>+#define mmDSCCIF5_DSCCIF_CONFIG1                                                                       0x31d2
>+#define mmDSCCIF5_DSCCIF_CONFIG1_BASE_IDX                                                              2
>+
>+
>+// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec
>+// base address: 0x730
>+#define mmDSCC5_DSCC_CONFIG0                                                                           0x31d6
>+#define mmDSCC5_DSCC_CONFIG0_BASE_IDX                                                                  2
>+#define mmDSCC5_DSCC_CONFIG1                                                                           0x31d7
>+#define mmDSCC5_DSCC_CONFIG1_BASE_IDX                                                                  2
>+#define mmDSCC5_DSCC_STATUS                                                                            0x31d8
>+#define mmDSCC5_DSCC_STATUS_BASE_IDX                                                                   2
>+#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x31d9
>+#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
>+#define mmDSCC5_DSCC_PPS_CONFIG0                                                                       0x31da
>+#define mmDSCC5_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
>+#define mmDSCC5_DSCC_PPS_CONFIG1                                                                       0x31db
>+#define mmDSCC5_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
>+#define mmDSCC5_DSCC_PPS_CONFIG2                                                                       0x31dc
>+#define mmDSCC5_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
>+#define mmDSCC5_DSCC_PPS_CONFIG3                                                                       0x31dd
>+#define mmDSCC5_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
>+#define mmDSCC5_DSCC_PPS_CONFIG4                                                                       0x31de
>+#define mmDSCC5_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
>+#define mmDSCC5_DSCC_PPS_CONFIG5                                                                       0x31df
>+#define mmDSCC5_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
>+#define mmDSCC5_DSCC_PPS_CONFIG6                                                                       0x31e0
>+#define mmDSCC5_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
>+#define mmDSCC5_DSCC_PPS_CONFIG7                                                                       0x31e1
>+#define mmDSCC5_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
>+#define mmDSCC5_DSCC_PPS_CONFIG8                                                                       0x31e2
>+#define mmDSCC5_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
>+#define mmDSCC5_DSCC_PPS_CONFIG9                                                                       0x31e3
>+#define mmDSCC5_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
>+#define mmDSCC5_DSCC_PPS_CONFIG10                                                                      0x31e4
>+#define mmDSCC5_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_PPS_CONFIG11                                                                      0x31e5
>+#define mmDSCC5_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_PPS_CONFIG12                                                                      0x31e6
>+#define mmDSCC5_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_PPS_CONFIG13                                                                      0x31e7
>+#define mmDSCC5_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_PPS_CONFIG14                                                                      0x31e8
>+#define mmDSCC5_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_PPS_CONFIG15                                                                      0x31e9
>+#define mmDSCC5_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_PPS_CONFIG16                                                                      0x31ea
>+#define mmDSCC5_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_PPS_CONFIG17                                                                      0x31eb
>+#define mmDSCC5_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_PPS_CONFIG18                                                                      0x31ec
>+#define mmDSCC5_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_PPS_CONFIG19                                                                      0x31ed
>+#define mmDSCC5_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_PPS_CONFIG20                                                                      0x31ee
>+#define mmDSCC5_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_PPS_CONFIG21                                                                      0x31ef
>+#define mmDSCC5_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_PPS_CONFIG22                                                                      0x31f0
>+#define mmDSCC5_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
>+#define mmDSCC5_DSCC_MEM_POWER_CONTROL                                                                 0x31f1
>+#define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
>+#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x31f2
>+#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
>+#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x31f3
>+#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
>+#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x31f4
>+#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
>+#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x31f5
>+#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
>+#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x31f6
>+#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
>+#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x31f7
>+#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
>+#define mmDSCC5_DSCC_MAX_ABS_ERROR0                                                                    0x31f8
>+#define mmDSCC5_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
>+#define mmDSCC5_DSCC_MAX_ABS_ERROR1                                                                    0x31f9
>+#define mmDSCC5_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
>+#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x31fa
>+#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x31fb
>+#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x31fc
>+#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x31fd
>+#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
>+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x31fe
>+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x31ff
>+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3200
>+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3201
>+#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
>+#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3206
>+#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
>+
>+
>+// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
>+// base address: 0xc870
>+#define mmDC_PERFMON24_PERFCOUNTER_CNTL                                                                0x321c
>+#define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX                                                       2
>+#define mmDC_PERFMON24_PERFCOUNTER_CNTL2                                                               0x321d
>+#define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
>+#define mmDC_PERFMON24_PERFCOUNTER_STATE                                                               0x321e
>+#define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX                                                      2
>+#define mmDC_PERFMON24_PERFMON_CNTL                                                                    0x321f
>+#define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX                                                           2
>+#define mmDC_PERFMON24_PERFMON_CNTL2                                                                   0x3220
>+#define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX                                                          2
>+#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC                                                         0x3221
>+#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
>+#define mmDC_PERFMON24_PERFMON_CVALUE_LOW                                                              0x3222
>+#define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
>+#define mmDC_PERFMON24_PERFMON_HI                                                                      0x3223
>+#define mmDC_PERFMON24_PERFMON_HI_BASE_IDX                                                             2
>+#define mmDC_PERFMON24_PERFMON_LOW                                                                     0x3224
>+#define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX                                                            2
>+
>+
>+// addressBlock: dce_dc_dmu_dmcub_dispdec
>+// base address: 0x0
>+#define mmDMCUB_REGION0_OFFSET                                                                         0x3238
>+#define mmDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
>+#define mmDMCUB_REGION0_OFFSET_HIGH                                                                    0x3239
>+#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
>+#define mmDMCUB_REGION1_OFFSET                                                                         0x323a
>+#define mmDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
>+#define mmDMCUB_REGION1_OFFSET_HIGH                                                                    0x323b
>+#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
>+#define mmDMCUB_REGION2_OFFSET                                                                         0x323c
>+#define mmDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
>+#define mmDMCUB_REGION2_OFFSET_HIGH                                                                    0x323d
>+#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
>+#define mmDMCUB_REGION4_OFFSET                                                                         0x3240
>+#define mmDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
>+#define mmDMCUB_REGION4_OFFSET_HIGH                                                                    0x3241
>+#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
>+#define mmDMCUB_REGION5_OFFSET                                                                         0x3242
>+#define mmDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
>+#define mmDMCUB_REGION5_OFFSET_HIGH                                                                    0x3243
>+#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
>+#define mmDMCUB_REGION6_OFFSET                                                                         0x3244
>+#define mmDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
>+#define mmDMCUB_REGION6_OFFSET_HIGH                                                                    0x3245
>+#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
>+#define mmDMCUB_REGION7_OFFSET                                                                         0x3246
>+#define mmDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
>+#define mmDMCUB_REGION7_OFFSET_HIGH                                                                    0x3247
>+#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
>+#define mmDMCUB_REGION0_TOP_ADDRESS                                                                    0x3248
>+#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
>+#define mmDMCUB_REGION1_TOP_ADDRESS                                                                    0x3249
>+#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
>+#define mmDMCUB_REGION2_TOP_ADDRESS                                                                    0x324a
>+#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
>+#define mmDMCUB_REGION4_TOP_ADDRESS                                                                    0x324b
>+#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
>+#define mmDMCUB_REGION5_TOP_ADDRESS                                                                    0x324c
>+#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
>+#define mmDMCUB_REGION6_TOP_ADDRESS                                                                    0x324d
>+#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
>+#define mmDMCUB_REGION7_TOP_ADDRESS                                                                    0x324e
>+#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
>+#define mmDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x324f
>+#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
>+#define mmDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x3250
>+#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
>+#define mmDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x3251
>+#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
>+#define mmDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x3252
>+#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
>+#define mmDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x3253
>+#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
>+#define mmDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x3254
>+#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
>+#define mmDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x3255
>+#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
>+#define mmDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x3256
>+#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
>+#define mmDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x3257
>+#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x3258
>+#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x3259
>+#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x325a
>+#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x325b
>+#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x325c
>+#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x325d
>+#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x325e
>+#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW0_OFFSET                                                                     0x325f
>+#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
>+#define mmDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x3260
>+#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW1_OFFSET                                                                     0x3261
>+#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
>+#define mmDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x3262
>+#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW2_OFFSET                                                                     0x3263
>+#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
>+#define mmDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x3264
>+#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW3_OFFSET                                                                     0x3265
>+#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
>+#define mmDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x3266
>+#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW4_OFFSET                                                                     0x3267
>+#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
>+#define mmDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x3268
>+#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW5_OFFSET                                                                     0x3269
>+#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
>+#define mmDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x326a
>+#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW6_OFFSET                                                                     0x326b
>+#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
>+#define mmDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x326c
>+#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
>+#define mmDMCUB_REGION3_CW7_OFFSET                                                                     0x326d
>+#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
>+#define mmDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x326e
>+#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
>+#define mmDMCUB_INTERRUPT_ENABLE                                                                       0x326f
>+#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
>+#define mmDMCUB_INTERRUPT_ACK                                                                          0x3270
>+#define mmDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
>+#define mmDMCUB_INTERRUPT_STATUS                                                                       0x3271
>+#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
>+#define mmDMCUB_INTERRUPT_TYPE                                                                         0x3272
>+#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
>+#define mmDMCUB_EXT_INTERRUPT_STATUS                                                                   0x3273
>+#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
>+#define mmDMCUB_EXT_INTERRUPT_CTXID                                                                    0x3274
>+#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
>+#define mmDMCUB_EXT_INTERRUPT_ACK                                                                      0x3275
>+#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
>+#define mmDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x3276
>+#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
>+#define mmDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x3277
>+#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
>+#define mmDMCUB_SEC_CNTL                                                                               0x3278
>+#define mmDMCUB_SEC_CNTL_BASE_IDX                                                                      2
>+#define mmDMCUB_MEM_CNTL                                                                               0x3279
>+#define mmDMCUB_MEM_CNTL_BASE_IDX                                                                      2
>+#define mmDMCUB_INBOX0_BASE_ADDRESS                                                                    0x327a
>+#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
>+#define mmDMCUB_INBOX0_SIZE                                                                            0x327b
>+#define mmDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
>+#define mmDMCUB_INBOX0_WPTR                                                                            0x327c
>+#define mmDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
>+#define mmDMCUB_INBOX0_RPTR                                                                            0x327d
>+#define mmDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
>+#define mmDMCUB_INBOX1_BASE_ADDRESS                                                                    0x327e
>+#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
>+#define mmDMCUB_INBOX1_SIZE                                                                            0x327f
>+#define mmDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
>+#define mmDMCUB_INBOX1_WPTR                                                                            0x3280
>+#define mmDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
>+#define mmDMCUB_INBOX1_RPTR                                                                            0x3281
>+#define mmDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
>+#define mmDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x3282
>+#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
>+#define mmDMCUB_OUTBOX0_SIZE                                                                           0x3283
>+#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
>+#define mmDMCUB_OUTBOX0_WPTR                                                                           0x3284
>+#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
>+#define mmDMCUB_OUTBOX0_RPTR                                                                           0x3285
>+#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
>+#define mmDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x3286
>+#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
>+#define mmDMCUB_OUTBOX1_SIZE                                                                           0x3287
>+#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
>+#define mmDMCUB_OUTBOX1_WPTR                                                                           0x3288
>+#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
>+#define mmDMCUB_OUTBOX1_RPTR                                                                           0x3289
>+#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
>+#define mmDMCUB_TIMER_TRIGGER0                                                                         0x328a
>+#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
>+#define mmDMCUB_TIMER_TRIGGER1                                                                         0x328b
>+#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
>+#define mmDMCUB_TIMER_WINDOW                                                                           0x328c
>+#define mmDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
>+#define mmDMCUB_SCRATCH0                                                                               0x328d
>+#define mmDMCUB_SCRATCH0_BASE_IDX                                                                      2
>+#define mmDMCUB_SCRATCH1                                                                               0x328e
>+#define mmDMCUB_SCRATCH1_BASE_IDX                                                                      2
>+#define mmDMCUB_SCRATCH2                                                                               0x328f
>+#define mmDMCUB_SCRATCH2_BASE_IDX                                                                      2
>+#define mmDMCUB_SCRATCH3                                                                               0x3290
>+#define mmDMCUB_SCRATCH3_BASE_IDX                                                                      2
>+#define mmDMCUB_SCRATCH4                                                                               0x3291
>+#define mmDMCUB_SCRATCH4_BASE_IDX                                                                      2
>+#define mmDMCUB_SCRATCH5                                                                               0x3292
>+#define mmDMCUB_SCRATCH5_BASE_IDX                                                                      2
>+#define mmDMCUB_SCRATCH6                                                                               0x3293
>+#define mmDMCUB_SCRATCH6_BASE_IDX                                                                      2
>+#define mmDMCUB_SCRATCH7                                                                               0x3294
>+#define mmDMCUB_SCRATCH7_BASE_IDX                                                                      2
>+#define mmDMCUB_SCRATCH8                                                                               0x3295
>+#define mmDMCUB_SCRATCH8_BASE_IDX                                                                      2
>+#define mmDMCUB_SCRATCH9                                                                               0x3296
>+#define mmDMCUB_SCRATCH9_BASE_IDX                                                                      2
>+#define mmDMCUB_SCRATCH10                                                                              0x3297
>+#define mmDMCUB_SCRATCH10_BASE_IDX                                                                     2
>+#define mmDMCUB_SCRATCH11                                                                              0x3298
>+#define mmDMCUB_SCRATCH11_BASE_IDX                                                                     2
>+#define mmDMCUB_SCRATCH12                                                                              0x3299
>+#define mmDMCUB_SCRATCH12_BASE_IDX                                                                     2
>+#define mmDMCUB_SCRATCH13                                                                              0x329a
>+#define mmDMCUB_SCRATCH13_BASE_IDX                                                                     2
>+#define mmDMCUB_SCRATCH14                                                                              0x329b
>+#define mmDMCUB_SCRATCH14_BASE_IDX                                                                     2
>+#define mmDMCUB_SCRATCH15                                                                              0x329c
>+#define mmDMCUB_SCRATCH15_BASE_IDX                                                                     2
>+#define mmDMCUB_CNTL                                                                                   0x32a0
>+#define mmDMCUB_CNTL_BASE_IDX                                                                          2
>+#define mmDMCUB_GPINT_DATAIN0                                                                          0x32a1
>+#define mmDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
>+#define mmDMCUB_GPINT_DATAIN1                                                                          0x32a2
>+#define mmDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
>+#define mmDMCUB_GPINT_DATAOUT                                                                          0x32a3
>+#define mmDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
>+#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x32a4
>+#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
>+#define mmDMCUB_LS_WAKE_INT_ENABLE                                                                     0x32a5
>+#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
>+#define mmDMCUB_MEM_PWR_CNTL                                                                           0x32a6
>+#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
>+#define mmDMCUB_TIMER_CURRENT                                                                          0x32a7
>+#define mmDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
>+#define mmDMCUB_PROC_ID                                                                                0x32a9
>+#define mmDMCUB_PROC_ID_BASE_IDX                                                                       2
>+
>+
>+// addressBlock: dce_dc_mmhubbub_mcif_wb2_dispdec
>+// base address: 0xc6b8
>+#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL                                                           0x3460
>+#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                  2
>+#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R                                                           0x3461
>+#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX                                                  2
>+#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS                                                               0x3462
>+#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX                                                      2
>+#define mmMCIF_WB2_MCIF_WB_BUF_PITCH                                                                   0x3463
>+#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX                                                          2
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS                                                                0x3464
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2                                                               0x3465
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX                                                      2
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS                                                                0x3466
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2                                                               0x3467
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX                                                      2
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS                                                                0x3468
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2                                                               0x3469
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX                                                      2
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS                                                                0x346a
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2                                                               0x346b
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX                                                      2
>+#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL                                                         0x346c
>+#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                2
>+#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE                                                                 0x346d
>+#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX                                                        2
>+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX                                                            0x346e
>+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                   2
>+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA                                                             0x346f
>+#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                    2
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y                                                                0x3470
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET                                                         0x3471
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C                                                                0x3472
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET                                                         0x3473
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y                                                                0x3474
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET                                                         0x3475
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C                                                                0x3476
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET                                                         0x3477
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y                                                                0x3478
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET                                                         0x3479
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C                                                                0x347a
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET                                                         0x347b
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y                                                                0x347c
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET                                                         0x347d
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C                                                                0x347e
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET                                                         0x347f
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX                                                2
>+#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL                                                          0x3480
>+#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                 2
>+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                 0x3481
>+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                        2
>+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL                                                           0x3482
>+#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                  2
>+#define mmMCIF_WB2_MCIF_WB_WATERMARK                                                                   0x3483
>+#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX                                                          2
>+#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL                                                         0x3484
>+#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                2
>+#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL                                                                0x3485
>+#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL                                                        0x3486
>+#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                               2
>+#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL                                                                0x3487
>+#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX                                                       2
>+#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE                                                               0x3489
>+#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                      2
>+#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE                                                             0x348a
>+#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                    2
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH                                                           0x348b
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH                                                           0x348c
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH                                                           0x348d
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH                                                           0x348e
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH                                                           0x348f
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH                                                           0x3490
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH                                                           0x3491
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH                                                           0x3492
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                  2
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION                                                            0x3493
>+#define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                   2
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION                                                            0x3494
>+#define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                   2
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION                                                            0x3495
>+#define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                   2
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION                                                            0x3496
>+#define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                   2
>+
>+
>+// addressBlock: dce_dc_dchvm_hvm_dispdec
>+// base address: 0x0
>+#define mmDCHVM_CTRL0                                                                                  0x016b
>+#define mmDCHVM_CTRL0_BASE_IDX                                                                         3
>+#define mmDCHVM_CTRL1                                                                                  0x016c
>+#define mmDCHVM_CTRL1_BASE_IDX                                                                         3
>+#define mmDCHVM_CLK_CTRL                                                                               0x016d
>+#define mmDCHVM_CLK_CTRL_BASE_IDX                                                                      3
>+#define mmDCHVM_MEM_CTRL                                                                               0x016e
>+#define mmDCHVM_MEM_CTRL_BASE_IDX                                                                      3
>+#define mmDCHVM_RIOMMU_CTRL0                                                                           0x016f
>+#define mmDCHVM_RIOMMU_CTRL0_BASE_IDX                                                                  3
>+#define mmDCHVM_RIOMMU_STAT0                                                                           0x0170
>+#define mmDCHVM_RIOMMU_STAT0_BASE_IDX                                                                  3
>+
>+
>+// addressBlock: vga_vgaseqind
>+// base address: 0x0
>+#define ixSEQ00                                                                                        0x0000
>+#define ixSEQ01                                                                                        0x0001
>+#define ixSEQ02                                                                                        0x0002
>+#define ixSEQ03                                                                                        0x0003
>+#define ixSEQ04                                                                                        0x0004
>+
>+
>+// addressBlock: vga_vgacrtind
>+// base address: 0x0
>+#define ixCRT00                                                                                        0x0000
>+#define ixCRT01                                                                                        0x0001
>+#define ixCRT02                                                                                        0x0002
>+#define ixCRT03                                                                                        0x0003
>+#define ixCRT04                                                                                        0x0004
>+#define ixCRT05                                                                                        0x0005
>+#define ixCRT06                                                                                        0x0006
>+#define ixCRT07                                                                                        0x0007
>+#define ixCRT08                                                                                        0x0008
>+#define ixCRT09                                                                                        0x0009
>+#define ixCRT0A                                                                                        0x000a
>+#define ixCRT0B                                                                                        0x000b
>+#define ixCRT0C                                                                                        0x000c
>+#define ixCRT0D                                                                                        0x000d
>+#define ixCRT0E                                                                                        0x000e
>+#define ixCRT0F                                                                                        0x000f
>+#define ixCRT10                                                                                        0x0010
>+#define ixCRT11                                                                                        0x0011
>+#define ixCRT12                                                                                        0x0012
>+#define ixCRT13                                                                                        0x0013
>+#define ixCRT14                                                                                        0x0014
>+#define ixCRT15                                                                                        0x0015
>+#define ixCRT16                                                                                        0x0016
>+#define ixCRT17                                                                                        0x0017
>+#define ixCRT18                                                                                        0x0018
>+#define ixCRT1E                                                                                        0x001e
>+#define ixCRT1F                                                                                        0x001f
>+#define ixCRT22                                                                                        0x0022
>+
>+
>+// addressBlock: vga_vgagrphind
>+// base address: 0x0
>+#define ixGRA00                                                                                        0x0000
>+#define ixGRA01                                                                                        0x0001
>+#define ixGRA02                                                                                        0x0002
>+#define ixGRA03                                                                                        0x0003
>+#define ixGRA04                                                                                        0x0004
>+#define ixGRA05                                                                                        0x0005
>+#define ixGRA06                                                                                        0x0006
>+#define ixGRA07                                                                                        0x0007
>+#define ixGRA08                                                                                        0x0008
>+
>+
>+// addressBlock: vga_vgaattrind
>+// base address: 0x0
>+#define ixATTR00                                                                                       0x0000
>+#define ixATTR01                                                                                       0x0001
>+#define ixATTR02                                                                                       0x0002
>+#define ixATTR03                                                                                       0x0003
>+#define ixATTR04                                                                                       0x0004
>+#define ixATTR05                                                                                       0x0005
>+#define ixATTR06                                                                                       0x0006
>+#define ixATTR07                                                                                       0x0007
>+#define ixATTR08                                                                                       0x0008
>+#define ixATTR09                                                                                       0x0009
>+#define ixATTR0A                                                                                       0x000a
>+#define ixATTR0B                                                                                       0x000b
>+#define ixATTR0C                                                                                       0x000c
>+#define ixATTR0D                                                                                       0x000d
>+#define ixATTR0E                                                                                       0x000e
>+#define ixATTR0F                                                                                       0x000f
>+#define ixATTR10                                                                                       0x0010
>+#define ixATTR11                                                                                       0x0011
>+#define ixATTR12                                                                                       0x0012
>+#define ixATTR13                                                                                       0x0013
>+#define ixATTR14                                                                                       0x0014
>+
>+
>+// addressBlock: azendpoint_f2codecind
>+// base address: 0x0
>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
>+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
>+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
>+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
>+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
>+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
>+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
>+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
>+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
>+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
>+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
>+
>+
>+// addressBlock: azendpoint_descriptorind
>+// base address: 0x0
>+#define ixAUDIO_DESCRIPTOR0                                                                            0x0001
>+#define ixAUDIO_DESCRIPTOR1                                                                            0x0002
>+#define ixAUDIO_DESCRIPTOR2                                                                            0x0003
>+#define ixAUDIO_DESCRIPTOR3                                                                            0x0004
>+#define ixAUDIO_DESCRIPTOR4                                                                            0x0005
>+#define ixAUDIO_DESCRIPTOR5                                                                            0x0006
>+#define ixAUDIO_DESCRIPTOR6                                                                            0x0007
>+#define ixAUDIO_DESCRIPTOR7                                                                            0x0008
>+#define ixAUDIO_DESCRIPTOR8                                                                            0x0009
>+#define ixAUDIO_DESCRIPTOR9                                                                            0x000a
>+#define ixAUDIO_DESCRIPTOR10                                                                           0x000b
>+#define ixAUDIO_DESCRIPTOR11                                                                           0x000c
>+#define ixAUDIO_DESCRIPTOR12                                                                           0x000d
>+#define ixAUDIO_DESCRIPTOR13                                                                           0x000e
>+
>+
>+// addressBlock: azendpoint_sinkinfoind
>+// base address: 0x0
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
>+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
>+#define ixSINK_DESCRIPTION0                                                                            0x0005
>+#define ixSINK_DESCRIPTION1                                                                            0x0006
>+#define ixSINK_DESCRIPTION2                                                                            0x0007
>+#define ixSINK_DESCRIPTION3                                                                            0x0008
>+#define ixSINK_DESCRIPTION4                                                                            0x0009
>+#define ixSINK_DESCRIPTION5                                                                            0x000a
>+#define ixSINK_DESCRIPTION6                                                                            0x000b
>+#define ixSINK_DESCRIPTION7                                                                            0x000c
>+#define ixSINK_DESCRIPTION8                                                                            0x000d
>+#define ixSINK_DESCRIPTION9                                                                            0x000e
>+#define ixSINK_DESCRIPTION10                                                                           0x000f
>+#define ixSINK_DESCRIPTION11                                                                           0x0010
>+#define ixSINK_DESCRIPTION12                                                                           0x0011
>+#define ixSINK_DESCRIPTION13                                                                           0x0012
>+#define ixSINK_DESCRIPTION14                                                                           0x0013
>+#define ixSINK_DESCRIPTION15                                                                           0x0014
>+#define ixSINK_DESCRIPTION16                                                                           0x0015
>+#define ixSINK_DESCRIPTION17                                                                           0x0016
>+
>+
>+// addressBlock: azf0controller_azinputcrc0resultind
>+// base address: 0x0
>+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
>+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
>+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
>+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
>+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
>+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
>+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
>+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
>+
>+
>+// addressBlock: azf0controller_azinputcrc1resultind
>+// base address: 0x0
>+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
>+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
>+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
>+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
>+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
>+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
>+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
>+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
>+
>+
>+// addressBlock: azf0controller_azcrc0resultind
>+// base address: 0x0
>+#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
>+#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
>+#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
>+#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
>+#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
>+#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
>+#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
>+#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
>+
>+
>+// addressBlock: azf0controller_azcrc1resultind
>+// base address: 0x0
>+#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
>+#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
>+#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
>+#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
>+#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
>+#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
>+#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
>+#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
>+
>+
>+// addressBlock: azinputendpoint_f2codecind
>+// base address: 0x0
>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
>+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
>+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
>+
>+
>+// addressBlock: azroot_f2codecind
>+// base address: 0x0
>+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
>+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
>+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
>+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
>+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
>+
>+
>+// addressBlock: azf0stream0_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
>+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
>+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
>+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
>+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
>+
>+
>+// addressBlock: azf0stream1_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
>+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
>+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
>+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
>+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
>+
>+
>+// addressBlock: azf0stream2_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
>+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
>+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
>+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
>+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
>+
>+
>+// addressBlock: azf0stream3_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
>+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
>+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
>+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
>+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
>+
>+
>+// addressBlock: azf0stream4_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
>+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
>+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
>+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
>+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
>+
>+
>+// addressBlock: azf0stream5_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
>+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
>+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
>+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
>+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
>+
>+
>+// addressBlock: azf0stream6_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
>+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
>+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
>+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
>+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
>+
>+
>+// addressBlock: azf0stream7_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
>+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
>+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
>+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
>+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
>+
>+
>+// addressBlock: azf0stream8_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
>+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
>+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
>+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
>+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
>+
>+
>+// addressBlock: azf0stream9_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
>+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
>+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
>+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
>+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
>+
>+
>+// addressBlock: azf0stream10_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
>+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
>+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
>+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
>+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
>+
>+
>+// addressBlock: azf0stream11_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
>+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
>+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
>+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
>+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
>+
>+
>+// addressBlock: azf0stream12_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
>+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
>+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
>+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
>+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
>+
>+
>+// addressBlock: azf0stream13_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
>+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
>+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
>+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
>+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
>+
>+
>+// addressBlock: azf0stream14_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
>+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
>+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
>+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
>+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
>+
>+
>+// addressBlock: azf0stream15_streamind
>+// base address: 0x0
>+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
>+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
>+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
>+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
>+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
>+
>+
>+// addressBlock: azf0endpoint0_endpointind
>+// base address: 0x0
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
>+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
>+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
>+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
>+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
>+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
>+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
>+
>+
>+// addressBlock: azf0endpoint1_endpointind
>+// base address: 0x0
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
>+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
>+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
>+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
>+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
>+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
>+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
>+
>+
>+// addressBlock: azf0endpoint2_endpointind
>+// base address: 0x0
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
>+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
>+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
>+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
>+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
>+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
>+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
>+
>+
>+// addressBlock: azf0endpoint3_endpointind
>+// base address: 0x0
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
>+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
>+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
>+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
>+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
>+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
>+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
>+
>+
>+// addressBlock: azf0endpoint4_endpointind
>+// base address: 0x0
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
>+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
>+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
>+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
>+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
>+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
>+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
>+
>+
>+// addressBlock: azf0endpoint5_endpointind
>+// base address: 0x0
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
>+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
>+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
>+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
>+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
>+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
>+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
>+
>+
>+// addressBlock: azf0endpoint6_endpointind
>+// base address: 0x0
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
>+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
>+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
>+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
>+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
>+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
>+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
>+
>+
>+// addressBlock: azf0endpoint7_endpointind
>+// base address: 0x0
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
>+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
>+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
>+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
>+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
>+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
>+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
>+
>+
>+// addressBlock: azf0inputendpoint0_inputendpointind
>+// base address: 0x0
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
>+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
>+
>+
>+// addressBlock: azf0inputendpoint1_inputendpointind
>+// base address: 0x0
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
>+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
>+
>+
>+// addressBlock: azf0inputendpoint2_inputendpointind
>+// base address: 0x0
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
>+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
>+
>+
>+// addressBlock: azf0inputendpoint3_inputendpointind
>+// base address: 0x0
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
>+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
>+
>+
>+// addressBlock: azf0inputendpoint4_inputendpointind
>+// base address: 0x0
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
>+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
>+
>+
>+// addressBlock: azf0inputendpoint5_inputendpointind
>+// base address: 0x0
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
>+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
>+
>+
>+// addressBlock: azf0inputendpoint6_inputendpointind
>+// base address: 0x0
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
>+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
>+
>+
>+// addressBlock: azf0inputendpoint7_inputendpointind
>+// base address: 0x0
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
>+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
>+
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h	2019-08-31 15:01:11.885736171 -0500
>@@ -0,0 +1,56638 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _dcn_2_1_0_SH_MASK_HEADER
>+#define _dcn_2_1_0_SH_MASK_HEADER
>+
>+
>+// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
>+//VGA_MEM_WRITE_PAGE_ADDR
>+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT                                              0x0
>+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT                                              0x10
>+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK                                                0x000003FFL
>+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK                                                0x03FF0000L
>+//VGA_MEM_READ_PAGE_ADDR
>+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT                                                0x0
>+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT                                                0x10
>+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK                                                  0x000003FFL
>+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK                                                  0x03FF0000L
>+// addressBlock: dce_dc_mmhubbub_vga_dispdec
>+//VGA_RENDER_CONTROL
>+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT                                                             0x0
>+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT                                                             0x5
>+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT                                                    0x7
>+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT                                                 0x8
>+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT                                                           0x10
>+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT                                                              0x18
>+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT                                           0x19
>+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK                                                               0x0000001FL
>+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK                                                               0x00000060L
>+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK                                                      0x00000080L
>+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK                                                   0x00000100L
>+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK                                                             0x00030000L
>+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK                                                                0x01000000L
>+#define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK                                             0x02000000L
>+//VGA_SEQUENCER_RESET_CONTROL
>+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x0
>+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x1
>+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x2
>+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x3
>+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x4
>+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x5
>+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x8
>+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x9
>+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xa
>+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xb
>+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xc
>+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xd
>+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT                                      0x10
>+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT                             0x11
>+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT                                0x12
>+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000001L
>+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000002L
>+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000004L
>+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000008L
>+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000010L
>+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000020L
>+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000100L
>+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000200L
>+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000400L
>+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000800L
>+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00001000L
>+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00002000L
>+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK                                        0x00010000L
>+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK                               0x00020000L
>+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK                                  0x00FC0000L
>+//VGA_MODE_CONTROL
>+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT                                                               0x0
>+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT                                                  0x4
>+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT                                                     0x8
>+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT                                                      0x10
>+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT                                                    0x18
>+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK                                                                 0x00000001L
>+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK                                                    0x00000030L
>+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK                                                       0x00000100L
>+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK                                                        0x00010000L
>+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK                                                      0x01000000L
>+//VGA_SURFACE_PITCH_SELECT
>+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT                                             0x0
>+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT                                            0x8
>+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK                                               0x00000003L
>+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK                                              0x00000300L
>+//VGA_MEMORY_BASE_ADDRESS
>+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT                                               0x0
>+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
>+//VGA_DISPBUF1_SURFACE_ADDR
>+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT                                           0x0
>+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK                                             0x01FFFFFFL
>+//VGA_DISPBUF2_SURFACE_ADDR
>+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT                                           0x0
>+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK                                             0x01FFFFFFL
>+//VGA_MEMORY_BASE_ADDRESS_HIGH
>+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT                                     0x0
>+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK                                       0x0000FFFFL
>+//VGA_HDP_CONTROL
>+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT                                                        0x0
>+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT                                                            0x4
>+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT                                                         0x8
>+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT                                                                0x10
>+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18
>+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK                                                          0x00000001L
>+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK                                                              0x00000010L
>+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK                                                           0x00000100L
>+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK                                                                  0x00010000L
>+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK                                                          0x01000000L
>+//VGA_CACHE_CONTROL
>+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT                                                 0x0
>+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT                                                      0x8
>+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT                                                  0x10
>+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT                                                          0x14
>+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT                                                        0x18
>+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK                                                   0x00000001L
>+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK                                                        0x00000100L
>+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK                                                    0x00010000L
>+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK                                                            0x00100000L
>+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK                                                          0x3F000000L
>+//D1VGA_CONTROL
>+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT                                                               0x0
>+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT                                                             0x8
>+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
>+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
>+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT                                                                    0x18
>+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK                                                                 0x00000001L
>+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK                                                               0x00000100L
>+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
>+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
>+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK                                                                      0x03000000L
>+//D2VGA_CONTROL
>+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT                                                               0x0
>+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT                                                             0x8
>+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
>+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
>+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT                                                                    0x18
>+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK                                                                 0x00000001L
>+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK                                                               0x00000100L
>+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
>+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
>+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK                                                                      0x03000000L
>+//VGA_STATUS
>+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT                                                              0x0
>+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT                                                              0x1
>+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT                                                          0x2
>+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT                                                       0x3
>+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK                                                                0x00000001L
>+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK                                                                0x00000002L
>+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK                                                            0x00000004L
>+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK                                                         0x00000008L
>+//VGA_INTERRUPT_CONTROL
>+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT                                                 0x0
>+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT                                                 0x8
>+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT                                             0x10
>+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT                                          0x18
>+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK                                                   0x00000001L
>+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK                                                   0x00000100L
>+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK                                               0x00010000L
>+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK                                            0x01000000L
>+//VGA_STATUS_CLEAR
>+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT                                                     0x0
>+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT                                                     0x8
>+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT                                                 0x10
>+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT                                              0x18
>+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK                                                       0x00000001L
>+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK                                                       0x00000100L
>+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK                                                   0x00010000L
>+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK                                                0x01000000L
>+//VGA_INTERRUPT_STATUS
>+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT                                                0x0
>+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT                                                0x1
>+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT                                            0x2
>+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT                                         0x3
>+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK                                                  0x00000001L
>+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK                                                  0x00000002L
>+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK                                              0x00000004L
>+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK                                           0x00000008L
>+//VGA_MAIN_CONTROL
>+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT                                                             0x0
>+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT                                                     0x3
>+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT                                        0x5
>+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT                                       0x8
>+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT                                                0xc
>+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT                                        0x10
>+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT                                          0x18
>+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT                                             0x1a
>+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT                                                       0x1d
>+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT                                0x1f
>+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK                                                               0x00000003L
>+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK                                                       0x00000018L
>+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK                                          0x000000E0L
>+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK                                         0x00000300L
>+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK                                                  0x0000F000L
>+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK                                          0x00030000L
>+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK                                            0x03000000L
>+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK                                               0x04000000L
>+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK                                                         0x20000000L
>+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK                                  0x80000000L
>+//VGA_TEST_CONTROL
>+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT                                                              0x0
>+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT                                                        0x8
>+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT                                                         0x10
>+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT                                               0x18
>+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK                                                                0x00000001L
>+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK                                                          0x00000100L
>+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK                                                           0x00010000L
>+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK                                                 0x01000000L
>+//VGA_QOS_CTRL
>+#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT                                                                     0x0
>+#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT                                                                    0x4
>+#define VGA_QOS_CTRL__VGA_READ_QOS_MASK                                                                       0x0000000FL
>+#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK                                                                      0x000000F0L
>+//D3VGA_CONTROL
>+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT                                                               0x0
>+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT                                                             0x8
>+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
>+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
>+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT                                                                    0x18
>+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK                                                                 0x00000001L
>+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK                                                               0x00000100L
>+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
>+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
>+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK                                                                      0x03000000L
>+//D4VGA_CONTROL
>+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT                                                               0x0
>+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT                                                             0x8
>+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
>+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
>+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT                                                                    0x18
>+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK                                                                 0x00000001L
>+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK                                                               0x00000100L
>+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
>+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
>+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK                                                                      0x03000000L
>+//D5VGA_CONTROL
>+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT                                                               0x0
>+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT                                                             0x8
>+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
>+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
>+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT                                                                    0x18
>+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK                                                                 0x00000001L
>+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK                                                               0x00000100L
>+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
>+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
>+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK                                                                      0x03000000L
>+//D6VGA_CONTROL
>+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT                                                               0x0
>+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT                                                             0x8
>+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
>+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
>+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT                                                                    0x18
>+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK                                                                 0x00000001L
>+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK                                                               0x00000100L
>+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
>+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
>+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK                                                                      0x03000000L
>+//VGA_SOURCE_SELECT
>+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT                                                            0x0
>+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT                                                            0x8
>+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK                                                              0x00000007L
>+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK                                                              0x00000700L
>+
>+
>+// addressBlock: dce_dc_dccg_dccg_dispdec
>+//PHYPLLA_PIXCLK_RESYNC_CNTL
>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT                                              0x8
>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK                                                0x00000100L
>+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
>+//PHYPLLB_PIXCLK_RESYNC_CNTL
>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT                                              0x8
>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK                                                0x00000100L
>+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
>+//PHYPLLC_PIXCLK_RESYNC_CNTL
>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT                                              0x8
>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK                                                0x00000100L
>+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
>+//PHYPLLD_PIXCLK_RESYNC_CNTL
>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT                                              0x8
>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK                                                0x00000100L
>+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
>+//DP_DTO_DBUF_EN
>+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT                                                                0x0
>+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT                                                                0x1
>+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT                                                                0x2
>+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT                                                                0x3
>+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT                                                                0x4
>+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT                                                                0x5
>+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT                                                                0x6
>+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT                                                                0x7
>+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK                                                                  0x00000001L
>+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK                                                                  0x00000002L
>+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK                                                                  0x00000004L
>+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK                                                                  0x00000008L
>+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK                                                                  0x00000010L
>+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK                                                                  0x00000020L
>+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK                                                                  0x00000040L
>+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK                                                                  0x00000080L
>+//DPREFCLK_CGTT_BLK_CTRL_REG
>+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT                                             0x0
>+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT                                            0x4
>+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK                                               0x0000000FL
>+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK                                              0x00000FF0L
>+//REFCLK_CNTL
>+#define REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT                                                                   0x0
>+#define REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT                                                                    0x1
>+#define REFCLK_CNTL__REFCLK_CLOCK_EN_MASK                                                                     0x00000001L
>+#define REFCLK_CNTL__REFCLK_SRC_SEL_MASK                                                                      0x00000002L
>+//REFCLK_CGTT_BLK_CTRL_REG
>+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT                                                 0x0
>+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT                                                0x4
>+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
>+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
>+//PHYPLLE_PIXCLK_RESYNC_CNTL
>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT                                              0x8
>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK                                                0x00000100L
>+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
>+//DCCG_PERFMON_CNTL2
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT                                                    0x0
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT                                                    0x1
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT                                                   0x2
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT                                                   0x3
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT                                            0x4
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT                                            0x5
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT                                            0x6
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT                                            0x7
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT                                            0x8
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK                                                      0x00000001L
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK                                                      0x00000002L
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK                                                     0x00000004L
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK                                                     0x00000008L
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK                                              0x00000010L
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK                                              0x00000020L
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK                                              0x00000040L
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK                                              0x00000080L
>+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK                                              0x00000100L
>+//DCCG_DS_DTO_INCR
>+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0
>+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL
>+//DCCG_DS_DTO_MODULO
>+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT                                                         0x0
>+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK                                                           0xFFFFFFFFL
>+//DCCG_DS_CNTL
>+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT                                                                   0x0
>+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT                                                                  0x4
>+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT                                                            0x8
>+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT                                                           0x9
>+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10
>+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT                                                        0x18
>+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT                                                           0x19
>+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK                                                                     0x00000001L
>+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK                                                                    0x00000030L
>+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK                                                              0x00000100L
>+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK                                                             0x00000200L
>+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK                                                            0x00030000L
>+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK                                                          0x01000000L
>+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK                                                             0x02000000L
>+//DCCG_DS_HW_CAL_INTERVAL
>+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT                                               0x0
>+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK                                                 0xFFFFFFFFL
>+//DPREFCLK_CNTL
>+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT                                                                0x0
>+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK                                                                  0x00000007L
>+//DCE_VERSION
>+#define DCE_VERSION__MAJOR_VERSION__SHIFT                                                                     0x0
>+#define DCE_VERSION__MINOR_VERSION__SHIFT                                                                     0x8
>+#define DCE_VERSION__MAJOR_VERSION_MASK                                                                       0x000000FFL
>+#define DCE_VERSION__MINOR_VERSION_MASK                                                                       0x0000FF00L
>+//DCCG_GTC_CNTL
>+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT                                                                 0x0
>+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK                                                                   0x00000001L
>+//DCCG_GTC_DTO_INCR
>+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT                                                           0x0
>+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK                                                             0xFFFFFFFFL
>+//DCCG_GTC_DTO_MODULO
>+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT                                                       0x0
>+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK                                                         0xFFFFFFFFL
>+//DCCG_GTC_CURRENT
>+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT                                                             0x0
>+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK                                                               0xFFFFFFFFL
>+//DSCCLK0_DTO_PARAM
>+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT                                                           0x0
>+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT                                                          0x10
>+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK                                                             0x000000FFL
>+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
>+//DSCCLK1_DTO_PARAM
>+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT                                                           0x0
>+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT                                                          0x10
>+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK                                                             0x000000FFL
>+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
>+//DSCCLK2_DTO_PARAM
>+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT                                                           0x0
>+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT                                                          0x10
>+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK                                                             0x000000FFL
>+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
>+//MILLISECOND_TIME_BASE_DIV
>+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT                                           0x0
>+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
>+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK                                             0x0001FFFFL
>+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
>+//DISPCLK_FREQ_CHANGE_CNTL
>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT                                                   0x0
>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT                                                    0x10
>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT                                               0x14
>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT                                            0x19
>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT                                               0x1c
>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT                                               0x1d
>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT                                              0x1e
>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT                                         0x1f
>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK                                                     0x00003FFFL
>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK                                                      0x000F0000L
>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK                                                 0x00100000L
>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK                                              0x0E000000L
>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK                                                 0x10000000L
>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK                                                 0x20000000L
>+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK                                                0x40000000L
>+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK                                           0x80000000L
>+//DC_MEM_GLOBAL_PWR_REQ_CNTL
>+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0
>+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L
>+//DCCG_PERFMON_CNTL
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT                                                    0x0
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT                                                   0x1
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT                                             0x2
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT                                             0x3
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT                                                    0x4
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT                                                               0x5
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT                                                        0x6
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT                                                        0x7
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT                                                           0x8
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT                                                  0xb
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK                                                      0x00000001L
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK                                                     0x00000002L
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK                                               0x00000004L
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK                                               0x00000008L
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK                                                      0x00000010L
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK                                                                 0x00000020L
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK                                                          0x00000040L
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK                                                          0x00000080L
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK                                                             0x00000700L
>+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK                                                    0xFFFFF800L
>+//DCCG_GATE_DISABLE_CNTL
>+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT                                              0x0
>+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT                                            0x1
>+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT                                                    0x2
>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT                                                  0x3
>+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT                                                   0x4
>+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT                                                   0x6
>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT                                           0x8
>+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT                                                    0x9
>+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT                                             0xa
>+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT                                                    0xb
>+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT                                                  0xc
>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT                                                   0x11
>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT                                                   0x12
>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT                                                   0x13
>+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT                                            0x15
>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT                                              0x16
>+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT                                                    0x1a
>+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT                                              0x1b
>+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT                                                    0x1c
>+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT                                                   0x1d
>+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT                                                    0x1e
>+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK                                                0x00000001L
>+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK                                              0x00000002L
>+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK                                                      0x00000004L
>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK                                                    0x00000008L
>+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK                                                     0x00000010L
>+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK                                                     0x00000040L
>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK                                             0x00000100L
>+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK                                                      0x00000200L
>+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK                                               0x00000400L
>+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK                                                      0x00000800L
>+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK                                                    0x00001000L
>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK                                                     0x00020000L
>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK                                                     0x00040000L
>+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK                                                     0x00080000L
>+#define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK                                              0x00200000L
>+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK                                                0x00400000L
>+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK                                                      0x04000000L
>+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK                                                0x08000000L
>+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK                                                      0x10000000L
>+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK                                                     0x20000000L
>+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK                                                      0x40000000L
>+//DISPCLK_CGTT_BLK_CTRL_REG
>+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT                                               0x0
>+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT                                              0x4
>+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK                                                 0x0000000FL
>+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK                                                0x00000FF0L
>+//SOCCLK_CGTT_BLK_CTRL_REG
>+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT                                                 0x0
>+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT                                                0x4
>+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
>+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
>+//DCCG_CAC_STATUS
>+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT                                                             0x0
>+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK                                                               0xFFFFFFFFL
>+//MICROSECOND_TIME_BASE_DIV
>+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT                                           0x0
>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8
>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT                                                        0x10
>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT                                           0x11
>+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
>+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK                                             0x0000007FL
>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK                                                          0x00007F00L
>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK                                                          0x00010000L
>+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK                                             0x00020000L
>+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
>+//DCCG_GATE_DISABLE_CNTL2
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT                                               0x0
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT                                               0x1
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT                                               0x2
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT                                               0x3
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT                                               0x4
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT                                               0x5
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT                                               0x6
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT                                                  0x10
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT                                                  0x11
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT                                                  0x12
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT                                                  0x13
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT                                                  0x14
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT                                                  0x15
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT                                                  0x16
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK                                                 0x00000001L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK                                                 0x00000002L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK                                                 0x00000004L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK                                                 0x00000008L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK                                                 0x00000010L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK                                                 0x00000020L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK                                                 0x00000040L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK                                                    0x00010000L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK                                                    0x00020000L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK                                                    0x00040000L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK                                                    0x00080000L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK                                                    0x00100000L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK                                                    0x00200000L
>+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK                                                    0x00400000L
>+//SYMCLK_CGTT_BLK_CTRL_REG
>+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT                                                 0x0
>+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT                                                0x4
>+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
>+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
>+//DCCG_DISP_CNTL_REG
>+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8
>+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK                                                        0x00000100L
>+//OTG0_PIXEL_RATE_CNTL
>+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
>+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT                                                           0x4
>+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT                                                       0x5
>+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT                                                           0x8
>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT                                                          0x9
>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT                                                      0xe
>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT                                                     0x10
>+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
>+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK                                                             0x00000010L
>+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK                                                         0x00000020L
>+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK                                                             0x00000100L
>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK                                                            0x00000200L
>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
>+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
>+//DP_DTO0_PHASE
>+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT                                                                   0x0
>+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK                                                                     0xFFFFFFFFL
>+//DP_DTO0_MODULO
>+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT                                                                 0x0
>+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK                                                                   0xFFFFFFFFL
>+//OTG0_PHYPLL_PIXEL_RATE_CNTL
>+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
>+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
>+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
>+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
>+//OTG1_PIXEL_RATE_CNTL
>+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
>+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT                                                           0x4
>+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT                                                       0x5
>+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT                                                           0x8
>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT                                                          0x9
>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT                                                      0xe
>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT                                                     0x10
>+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
>+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK                                                             0x00000010L
>+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK                                                         0x00000020L
>+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK                                                             0x00000100L
>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK                                                            0x00000200L
>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
>+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
>+//DP_DTO1_PHASE
>+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT                                                                   0x0
>+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK                                                                     0xFFFFFFFFL
>+//DP_DTO1_MODULO
>+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT                                                                 0x0
>+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK                                                                   0xFFFFFFFFL
>+//OTG1_PHYPLL_PIXEL_RATE_CNTL
>+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
>+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
>+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
>+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
>+//OTG2_PIXEL_RATE_CNTL
>+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
>+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT                                                           0x4
>+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT                                                       0x5
>+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT                                                           0x8
>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT                                                          0x9
>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT                                                      0xe
>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT                                                     0x10
>+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
>+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK                                                             0x00000010L
>+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK                                                         0x00000020L
>+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK                                                             0x00000100L
>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK                                                            0x00000200L
>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
>+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
>+//DP_DTO2_PHASE
>+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT                                                                   0x0
>+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK                                                                     0xFFFFFFFFL
>+//DP_DTO2_MODULO
>+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT                                                                 0x0
>+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK                                                                   0xFFFFFFFFL
>+//OTG2_PHYPLL_PIXEL_RATE_CNTL
>+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
>+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
>+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
>+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
>+//OTG3_PIXEL_RATE_CNTL
>+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
>+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT                                                           0x4
>+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT                                                       0x5
>+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT                                                           0x8
>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT                                                          0x9
>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT                                                      0xe
>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT                                                     0x10
>+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
>+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK                                                             0x00000010L
>+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK                                                         0x00000020L
>+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK                                                             0x00000100L
>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK                                                            0x00000200L
>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
>+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
>+//DP_DTO3_PHASE
>+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT                                                                   0x0
>+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK                                                                     0xFFFFFFFFL
>+//DP_DTO3_MODULO
>+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT                                                                 0x0
>+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK                                                                   0xFFFFFFFFL
>+//OTG3_PHYPLL_PIXEL_RATE_CNTL
>+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
>+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
>+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
>+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
>+//DPPCLK_CGTT_BLK_CTRL_REG
>+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT                                                 0x0
>+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT                                                0x4
>+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
>+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
>+//DPPCLK0_DTO_PARAM
>+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT                                                           0x0
>+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT                                                          0x10
>+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK                                                             0x000000FFL
>+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
>+//DPPCLK1_DTO_PARAM
>+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT                                                           0x0
>+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT                                                          0x10
>+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK                                                             0x000000FFL
>+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
>+//DPPCLK2_DTO_PARAM
>+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT                                                           0x0
>+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT                                                          0x10
>+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK                                                             0x000000FFL
>+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
>+//DPPCLK3_DTO_PARAM
>+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT                                                           0x0
>+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT                                                          0x10
>+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK                                                             0x000000FFL
>+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK                                                            0x00FF0000L
>+//DCCG_CAC_STATUS2
>+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT                                                           0x0
>+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK                                                             0x0000007FL
>+//SYMCLKA_CLOCK_ENABLE
>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT                                                     0x0
>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT                                                      0x4
>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT                                                     0x8
>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK                                                       0x00000001L
>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK                                                        0x00000010L
>+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK                                                       0x00000700L
>+//SYMCLKB_CLOCK_ENABLE
>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT                                                     0x0
>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT                                                      0x4
>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT                                                     0x8
>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK                                                       0x00000001L
>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK                                                        0x00000010L
>+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK                                                       0x00000700L
>+//SYMCLKC_CLOCK_ENABLE
>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT                                                     0x0
>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT                                                      0x4
>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT                                                     0x8
>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK                                                       0x00000001L
>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK                                                        0x00000010L
>+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK                                                       0x00000700L
>+//SYMCLKD_CLOCK_ENABLE
>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT                                                     0x0
>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT                                                      0x4
>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT                                                     0x8
>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK                                                       0x00000001L
>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK                                                        0x00000010L
>+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK                                                       0x00000700L
>+//SYMCLKE_CLOCK_ENABLE
>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT                                                     0x0
>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT                                                      0x4
>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT                                                     0x8
>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK                                                       0x00000001L
>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK                                                        0x00000010L
>+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK                                                       0x00000700L
>+//DCCG_SOFT_RESET
>+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                             0x0
>+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET__SHIFT                                                        0x1
>+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT                                                                0x2
>+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT                                                                0x3
>+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT                                                     0x4
>+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT                                                           0x8
>+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT                                                             0xc
>+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT                                                             0xd
>+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xe
>+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xf
>+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x10
>+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x11
>+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x12
>+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x13
>+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x14
>+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x15
>+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                               0x00000001L
>+#define DCCG_SOFT_RESET__PCIE_REFCLK_SOFT_RESET_MASK                                                          0x00000002L
>+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK                                                                  0x00000004L
>+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK                                                                  0x00000008L
>+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK                                                       0x00000010L
>+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK                                                             0x00000100L
>+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK                                                               0x00001000L
>+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK                                                               0x00002000L
>+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00004000L
>+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00008000L
>+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00010000L
>+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00020000L
>+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00040000L
>+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00080000L
>+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00100000L
>+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00200000L
>+//DSCCLK_DTO_CTRL
>+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT                                                            0x0
>+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT                                                            0x1
>+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT                                                            0x2
>+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT                                                            0x3
>+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT                                                            0x4
>+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT                                                            0x5
>+#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_ENABLE__SHIFT                                                            0x6
>+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT                                                             0x8
>+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT                                                             0x9
>+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT                                                             0xa
>+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT                                                             0xb
>+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT                                                             0xc
>+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT                                                             0xd
>+#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_DB_EN__SHIFT                                                             0xe
>+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK                                                              0x00000001L
>+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK                                                              0x00000002L
>+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK                                                              0x00000004L
>+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK                                                              0x00000008L
>+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK                                                              0x00000010L
>+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK                                                              0x00000020L
>+#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_ENABLE_MASK                                                              0x00000040L
>+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK                                                               0x00000100L
>+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK                                                               0x00000200L
>+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK                                                               0x00000400L
>+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK                                                               0x00000800L
>+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK                                                               0x00001000L
>+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK                                                               0x00002000L
>+#define DSCCLK_DTO_CTRL__DSCCLK6_DTO_DB_EN_MASK                                                               0x00004000L
>+//DCCG_AUDIO_DTO_SOURCE
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT                                              0x0
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT                                                      0x4
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT                                              0xc
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT                                                0x10
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT                                          0x14
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT                                          0x18
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT                                          0x1c
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK                                                0x00000007L
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK                                                        0x00000030L
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK                                                0x00003000L
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK                                                  0x00010000L
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK                                            0x00100000L
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK                                            0x01000000L
>+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK                                            0x10000000L
>+//DCCG_AUDIO_DTO0_PHASE
>+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT                                                   0x0
>+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK                                                     0xFFFFFFFFL
>+//DCCG_AUDIO_DTO0_MODULE
>+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT                                                 0x0
>+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK                                                   0xFFFFFFFFL
>+//DCCG_AUDIO_DTO1_PHASE
>+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT                                                   0x0
>+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK                                                     0xFFFFFFFFL
>+//DCCG_AUDIO_DTO1_MODULE
>+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT                                                 0x0
>+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK                                                   0xFFFFFFFFL
>+//DCCG_VSYNC_OTG0_LATCH_VALUE
>+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT                                   0x0
>+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK                                     0xFFFFFFFFL
>+//DCCG_VSYNC_OTG1_LATCH_VALUE
>+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT                                   0x0
>+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK                                     0xFFFFFFFFL
>+//DCCG_VSYNC_OTG2_LATCH_VALUE
>+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT                                   0x0
>+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK                                     0xFFFFFFFFL
>+//DCCG_VSYNC_OTG3_LATCH_VALUE
>+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT                                   0x0
>+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK                                     0xFFFFFFFFL
>+//DCCG_VSYNC_OTG4_LATCH_VALUE
>+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT                                   0x0
>+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK                                     0xFFFFFFFFL
>+//DCCG_VSYNC_OTG5_LATCH_VALUE
>+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT                                   0x0
>+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK                                     0xFFFFFFFFL
>+//DPPCLK_DTO_CTRL
>+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT                                                            0x0
>+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT                                                             0x1
>+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT                                                            0x4
>+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT                                                             0x5
>+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT                                                            0x8
>+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT                                                             0x9
>+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT                                                            0xc
>+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT                                                             0xd
>+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT                                                            0x10
>+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT                                                             0x11
>+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT                                                            0x14
>+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT                                                             0x15
>+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK                                                              0x00000001L
>+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK                                                               0x00000002L
>+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK                                                              0x00000010L
>+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK                                                               0x00000020L
>+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK                                                              0x00000100L
>+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK                                                               0x00000200L
>+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK                                                              0x00001000L
>+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK                                                               0x00002000L
>+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK                                                              0x00010000L
>+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK                                                               0x00020000L
>+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK                                                              0x00100000L
>+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK                                                               0x00200000L
>+//DCCG_VSYNC_CNT_CTRL
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT                                                     0x0
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL__SHIFT                                                 0x1
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT                                                   0x2
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT                                                  0x3
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT                                               0x4
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT                                                  0x8
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT                                                  0x10
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT                                                  0x11
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT                                                  0x12
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT                                                  0x13
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT                                                  0x14
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT                                                  0x15
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT                                            0x18
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT                                            0x19
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT                                            0x1a
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT                                            0x1b
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT                                            0x1c
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT                                            0x1d
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK                                                       0x00000001L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_REFCLK_SEL_MASK                                                   0x00000002L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK                                                     0x00000004L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK                                                    0x00000008L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK                                                 0x000000F0L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK                                                    0x00000F00L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK                                                    0x00010000L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK                                                    0x00020000L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK                                                    0x00040000L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK                                                    0x00080000L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK                                                    0x00100000L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK                                                    0x00200000L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK                                              0x01000000L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK                                              0x02000000L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK                                              0x04000000L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK                                              0x08000000L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK                                              0x10000000L
>+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK                                              0x20000000L
>+//DCCG_VSYNC_CNT_INT_CTRL
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT                                   0x0
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT                             0x0
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT                                   0x1
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT                             0x1
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT                                   0x2
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT                             0x2
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT                                   0x3
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT                             0x3
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT                                   0x4
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT                             0x4
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT                                   0x5
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT                             0x5
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT                                        0x8
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT                                        0x9
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT                                        0xa
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT                                        0xb
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT                                        0xc
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT                                        0xd
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK                                     0x00000001L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK                               0x00000001L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK                                     0x00000002L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK                               0x00000002L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK                                     0x00000004L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK                               0x00000004L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK                                     0x00000008L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK                               0x00000008L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK                                     0x00000010L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK                               0x00000010L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK                                     0x00000020L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK                               0x00000020L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK                                          0x00000100L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK                                          0x00000200L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK                                          0x00000400L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK                                          0x00000800L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK                                          0x00001000L
>+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK                                          0x00002000L
>+//FORCE_SYMCLK_DISABLE
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT                                                    0x0
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT                                                    0x1
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT                                                    0x2
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT                                                    0x3
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT                                                    0x4
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT                                                    0x5
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT                                                    0x6
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK                                                      0x00000001L
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK                                                      0x00000002L
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK                                                      0x00000004L
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK                                                      0x00000008L
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK                                                      0x00000010L
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK                                                      0x00000020L
>+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK                                                      0x00000040L
>+//DCCG_TEST_CLK_SEL
>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT                                                  0x0
>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT                                                  0xc
>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT                                              0xe
>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT                                                  0x10
>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT                                                  0x1c
>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK                                                    0x000001FFL
>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK                                                    0x00001000L
>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK                                                0x0000C000L
>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK                                                    0x01FF0000L
>+#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK                                                    0x10000000L
>+
>+
>+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
>+//DENTIST_DISPCLK_CNTL
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT                                                 0x0
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT                                                 0x8
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT                                                 0xf
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT                                                   0x11
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT                                                  0x12
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT                                                 0x13
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT                                                  0x14
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT                                                    0x15
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT                                                   0x16
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT                                                  0x18
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK                                                   0x0000007FL
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK                                                   0x00007F00L
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK                                                   0x00018000L
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK                                                     0x00020000L
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK                                                    0x00040000L
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK                                                   0x00080000L
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK                                                    0x00100000L
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK                                                      0x00200000L
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK                                                     0x00400000L
>+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK                                                    0x7F000000L
>+
>+
>+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
>+//DC_PERFMON0_PERFCOUNTER_CNTL
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
>+//DC_PERFMON0_PERFCOUNTER_CNTL2
>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
>+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
>+//DC_PERFMON0_PERFCOUNTER_STATE
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
>+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
>+//DC_PERFMON0_PERFMON_CNTL
>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
>+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
>+//DC_PERFMON0_PERFMON_CNTL2
>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
>+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
>+//DC_PERFMON0_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
>+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
>+//DC_PERFMON0_PERFMON_CVALUE_LOW
>+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
>+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
>+//DC_PERFMON0_PERFMON_HI
>+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
>+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
>+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
>+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
>+//DC_PERFMON0_PERFMON_LOW
>+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
>+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
>+//DC_PERFMON1_PERFCOUNTER_CNTL
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
>+//DC_PERFMON1_PERFCOUNTER_CNTL2
>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
>+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
>+//DC_PERFMON1_PERFCOUNTER_STATE
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
>+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
>+//DC_PERFMON1_PERFMON_CNTL
>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
>+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
>+//DC_PERFMON1_PERFMON_CNTL2
>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
>+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
>+//DC_PERFMON1_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
>+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
>+//DC_PERFMON1_PERFMON_CVALUE_LOW
>+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
>+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
>+//DC_PERFMON1_PERFMON_HI
>+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
>+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
>+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
>+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
>+//DC_PERFMON1_PERFMON_LOW
>+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
>+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dccg_dccg_pll_dispdec
>+//PLL_MACRO_CNTL_RESERVED0
>+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
>+#define PLL_MACRO_CNTL_RESERVED0__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED1
>+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
>+#define PLL_MACRO_CNTL_RESERVED1__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED2
>+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
>+#define PLL_MACRO_CNTL_RESERVED2__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED3
>+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
>+#define PLL_MACRO_CNTL_RESERVED3__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED4
>+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
>+#define PLL_MACRO_CNTL_RESERVED4__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED5
>+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
>+#define PLL_MACRO_CNTL_RESERVED5__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED6
>+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
>+#define PLL_MACRO_CNTL_RESERVED6__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED7
>+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
>+#define PLL_MACRO_CNTL_RESERVED7__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED8
>+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
>+#define PLL_MACRO_CNTL_RESERVED8__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED9
>+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED__SHIFT                                              0x0
>+#define PLL_MACRO_CNTL_RESERVED9__PLL_MACRO_CNTL_RESERVED_MASK                                                0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED10
>+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED10__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED11
>+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED11__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED12
>+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED12__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED13
>+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED13__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED14
>+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED14__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED15
>+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED15__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED16
>+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED16__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED17
>+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED17__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED18
>+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED18__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED19
>+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED19__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED20
>+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED20__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED21
>+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED21__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED22
>+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED22__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED23
>+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED23__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED24
>+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED24__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED25
>+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED25__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED26
>+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED26__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED27
>+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED27__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED28
>+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED28__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED29
>+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED29__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED30
>+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED30__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED31
>+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED31__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED32
>+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED32__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED33
>+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED33__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED34
>+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED34__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED35
>+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED35__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED36
>+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED36__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED37
>+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED37__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED38
>+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED38__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED39
>+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED39__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED40
>+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED40__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+//PLL_MACRO_CNTL_RESERVED41
>+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED__SHIFT                                             0x0
>+#define PLL_MACRO_CNTL_RESERVED41__PLL_MACRO_CNTL_RESERVED_MASK                                               0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dmu_rbbmif_dispdec
>+//RBBMIF_TIMEOUT
>+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT                                                           0x0
>+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT                                                     0x14
>+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK                                                             0x000FFFFFL
>+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK                                                       0xFFF00000L
>+//RBBMIF_STATUS
>+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT                                                      0x0
>+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK                                                        0xFFFFFFFFL
>+//RBBMIF_STATUS_2
>+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT                                                  0x0
>+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK                                                    0x0000003FL
>+//RBBMIF_INT_STATUS
>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT                                                         0x2
>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT                                                           0x1c
>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT                                                  0x1d
>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT                                                          0x1e
>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT                                                         0x1f
>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK                                                           0x0003FFFCL
>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK                                                             0x10000000L
>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK                                                    0x20000000L
>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK                                                            0x40000000L
>+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK                                                           0x80000000L
>+//RBBMIF_TIMEOUT_DIS
>+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT                                                        0x0
>+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT                                                        0x1
>+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT                                                        0x2
>+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT                                                        0x3
>+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT                                                        0x4
>+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT                                                        0x5
>+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT                                                        0x6
>+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT                                                        0x7
>+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT                                                        0x8
>+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT                                                        0x9
>+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT                                                       0xa
>+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT                                                       0xb
>+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT                                                       0xc
>+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT                                                       0xd
>+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT                                                       0xe
>+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT                                                       0xf
>+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT                                                       0x10
>+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT                                                       0x11
>+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT                                                       0x12
>+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT                                                       0x13
>+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT                                                       0x14
>+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT                                                       0x15
>+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT                                                       0x16
>+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT                                                       0x17
>+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT                                                       0x18
>+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT                                                       0x19
>+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT                                                       0x1a
>+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT                                                       0x1b
>+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT                                                       0x1c
>+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT                                                       0x1d
>+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT                                                       0x1e
>+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT                                                       0x1f
>+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK                                                          0x00000001L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK                                                          0x00000002L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK                                                          0x00000004L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK                                                          0x00000008L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK                                                          0x00000010L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK                                                          0x00000020L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK                                                          0x00000040L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK                                                          0x00000080L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK                                                          0x00000100L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK                                                          0x00000200L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK                                                         0x00000400L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK                                                         0x00000800L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK                                                         0x00001000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK                                                         0x00002000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK                                                         0x00004000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK                                                         0x00008000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK                                                         0x00010000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK                                                         0x00020000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK                                                         0x00040000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK                                                         0x00080000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK                                                         0x00100000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK                                                         0x00200000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK                                                         0x00400000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK                                                         0x00800000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK                                                         0x01000000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK                                                         0x02000000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK                                                         0x04000000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK                                                         0x08000000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK                                                         0x10000000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK                                                         0x20000000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK                                                         0x40000000L
>+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK                                                         0x80000000L
>+//RBBMIF_TIMEOUT_DIS_2
>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT                                                     0x0
>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT                                                     0x1
>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT                                                     0x2
>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT                                                     0x3
>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT                                                     0x4
>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT                                                     0x5
>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK                                                       0x00000001L
>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK                                                       0x00000002L
>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK                                                       0x00000004L
>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK                                                       0x00000008L
>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK                                                       0x00000010L
>+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK                                                       0x00000020L
>+//RBBMIF_STATUS_FLAG
>+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT                                                               0x0
>+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT                                                        0x4
>+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT                                                          0x5
>+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT                                                           0x6
>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                                 0x8
>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                                 0x9
>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                                 0x10
>+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK                                                                 0x00000003L
>+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK                                                          0x00000010L
>+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK                                                            0x00000020L
>+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK                                                             0x00000040L
>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                   0x00000100L
>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                   0x00000E00L
>+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                   0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dmu_dc_pg_dispdec
>+//DOMAIN0_PG_CONFIG
>+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON__SHIFT                                                       0x0
>+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE__SHIFT                                                          0x8
>+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_FORCEON_MASK                                                         0x00000001L
>+#define DOMAIN0_PG_CONFIG__DOMAIN0_POWER_GATE_MASK                                                            0x00000100L
>+//DOMAIN0_PG_STATUS
>+#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE__SHIFT                                                   0x1c
>+#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
>+#define DOMAIN0_PG_STATUS__DOMAIN0_DESIRED_PWR_STATE_MASK                                                     0x10000000L
>+#define DOMAIN0_PG_STATUS__DOMAIN0_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
>+//DOMAIN1_PG_CONFIG
>+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON__SHIFT                                                       0x0
>+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE__SHIFT                                                          0x8
>+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_FORCEON_MASK                                                         0x00000001L
>+#define DOMAIN1_PG_CONFIG__DOMAIN1_POWER_GATE_MASK                                                            0x00000100L
>+//DOMAIN1_PG_STATUS
>+#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE__SHIFT                                                   0x1c
>+#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
>+#define DOMAIN1_PG_STATUS__DOMAIN1_DESIRED_PWR_STATE_MASK                                                     0x10000000L
>+#define DOMAIN1_PG_STATUS__DOMAIN1_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
>+//DOMAIN2_PG_CONFIG
>+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON__SHIFT                                                       0x0
>+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE__SHIFT                                                          0x8
>+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_FORCEON_MASK                                                         0x00000001L
>+#define DOMAIN2_PG_CONFIG__DOMAIN2_POWER_GATE_MASK                                                            0x00000100L
>+//DOMAIN2_PG_STATUS
>+#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE__SHIFT                                                   0x1c
>+#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
>+#define DOMAIN2_PG_STATUS__DOMAIN2_DESIRED_PWR_STATE_MASK                                                     0x10000000L
>+#define DOMAIN2_PG_STATUS__DOMAIN2_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
>+//DOMAIN3_PG_CONFIG
>+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON__SHIFT                                                       0x0
>+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE__SHIFT                                                          0x8
>+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_FORCEON_MASK                                                         0x00000001L
>+#define DOMAIN3_PG_CONFIG__DOMAIN3_POWER_GATE_MASK                                                            0x00000100L
>+//DOMAIN3_PG_STATUS
>+#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE__SHIFT                                                   0x1c
>+#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
>+#define DOMAIN3_PG_STATUS__DOMAIN3_DESIRED_PWR_STATE_MASK                                                     0x10000000L
>+#define DOMAIN3_PG_STATUS__DOMAIN3_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
>+//DOMAIN4_PG_CONFIG
>+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON__SHIFT                                                       0x0
>+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE__SHIFT                                                          0x8
>+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_FORCEON_MASK                                                         0x00000001L
>+#define DOMAIN4_PG_CONFIG__DOMAIN4_POWER_GATE_MASK                                                            0x00000100L
>+//DOMAIN4_PG_STATUS
>+#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE__SHIFT                                                   0x1c
>+#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
>+#define DOMAIN4_PG_STATUS__DOMAIN4_DESIRED_PWR_STATE_MASK                                                     0x10000000L
>+#define DOMAIN4_PG_STATUS__DOMAIN4_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
>+//DOMAIN5_PG_CONFIG
>+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON__SHIFT                                                       0x0
>+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE__SHIFT                                                          0x8
>+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_FORCEON_MASK                                                         0x00000001L
>+#define DOMAIN5_PG_CONFIG__DOMAIN5_POWER_GATE_MASK                                                            0x00000100L
>+//DOMAIN5_PG_STATUS
>+#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE__SHIFT                                                   0x1c
>+#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
>+#define DOMAIN5_PG_STATUS__DOMAIN5_DESIRED_PWR_STATE_MASK                                                     0x10000000L
>+#define DOMAIN5_PG_STATUS__DOMAIN5_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
>+//DOMAIN6_PG_CONFIG
>+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON__SHIFT                                                       0x0
>+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE__SHIFT                                                          0x8
>+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_FORCEON_MASK                                                         0x00000001L
>+#define DOMAIN6_PG_CONFIG__DOMAIN6_POWER_GATE_MASK                                                            0x00000100L
>+//DOMAIN6_PG_STATUS
>+#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE__SHIFT                                                   0x1c
>+#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
>+#define DOMAIN6_PG_STATUS__DOMAIN6_DESIRED_PWR_STATE_MASK                                                     0x10000000L
>+#define DOMAIN6_PG_STATUS__DOMAIN6_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
>+//DOMAIN7_PG_CONFIG
>+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON__SHIFT                                                       0x0
>+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE__SHIFT                                                          0x8
>+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_FORCEON_MASK                                                         0x00000001L
>+#define DOMAIN7_PG_CONFIG__DOMAIN7_POWER_GATE_MASK                                                            0x00000100L
>+//DOMAIN7_PG_STATUS
>+#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE__SHIFT                                                   0x1c
>+#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
>+#define DOMAIN7_PG_STATUS__DOMAIN7_DESIRED_PWR_STATE_MASK                                                     0x10000000L
>+#define DOMAIN7_PG_STATUS__DOMAIN7_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
>+//DOMAIN16_PG_CONFIG
>+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON__SHIFT                                                     0x0
>+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE__SHIFT                                                        0x8
>+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_FORCEON_MASK                                                       0x00000001L
>+#define DOMAIN16_PG_CONFIG__DOMAIN16_POWER_GATE_MASK                                                          0x00000100L
>+//DOMAIN16_PG_STATUS
>+#define DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE__SHIFT                                                 0x1c
>+#define DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS__SHIFT                                                  0x1e
>+#define DOMAIN16_PG_STATUS__DOMAIN16_DESIRED_PWR_STATE_MASK                                                   0x10000000L
>+#define DOMAIN16_PG_STATUS__DOMAIN16_PGFSM_PWR_STATUS_MASK                                                    0xC0000000L
>+//DOMAIN17_PG_CONFIG
>+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON__SHIFT                                                     0x0
>+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE__SHIFT                                                        0x8
>+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_FORCEON_MASK                                                       0x00000001L
>+#define DOMAIN17_PG_CONFIG__DOMAIN17_POWER_GATE_MASK                                                          0x00000100L
>+//DOMAIN17_PG_STATUS
>+#define DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE__SHIFT                                                 0x1c
>+#define DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS__SHIFT                                                  0x1e
>+#define DOMAIN17_PG_STATUS__DOMAIN17_DESIRED_PWR_STATE_MASK                                                   0x10000000L
>+#define DOMAIN17_PG_STATUS__DOMAIN17_PGFSM_PWR_STATUS_MASK                                                    0xC0000000L
>+//DOMAIN18_PG_CONFIG
>+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON__SHIFT                                                     0x0
>+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE__SHIFT                                                        0x8
>+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_FORCEON_MASK                                                       0x00000001L
>+#define DOMAIN18_PG_CONFIG__DOMAIN18_POWER_GATE_MASK                                                          0x00000100L
>+//DOMAIN18_PG_STATUS
>+#define DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE__SHIFT                                                 0x1c
>+#define DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS__SHIFT                                                  0x1e
>+#define DOMAIN18_PG_STATUS__DOMAIN18_DESIRED_PWR_STATE_MASK                                                   0x10000000L
>+#define DOMAIN18_PG_STATUS__DOMAIN18_PGFSM_PWR_STATUS_MASK                                                    0xC0000000L
>+//DCPG_INTERRUPT_STATUS
>+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                           0x0
>+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x1
>+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                           0x2
>+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x3
>+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                           0x4
>+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x5
>+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                           0x6
>+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x7
>+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT                                           0x8
>+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x9
>+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT                                           0xa
>+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT                                         0xb
>+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT                                           0xc
>+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT                                         0xd
>+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT                                           0xe
>+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT                                         0xf
>+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT                                           0x10
>+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x11
>+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT                                           0x12
>+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x13
>+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT                                          0x14
>+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x15
>+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT                                          0x16
>+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x17
>+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT                                          0x18
>+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x19
>+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT                                          0x1a
>+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x1b
>+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT                                          0x1c
>+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x1d
>+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT                                          0x1e
>+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT                                        0x1f
>+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                             0x00000001L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000002L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                             0x00000004L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000008L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                             0x00000010L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000020L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                             0x00000040L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000080L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_UP_INT_OCCURRED_MASK                                             0x00000100L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000200L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_UP_INT_OCCURRED_MASK                                             0x00000400L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000800L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_UP_INT_OCCURRED_MASK                                             0x00001000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK                                           0x00002000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_UP_INT_OCCURRED_MASK                                             0x00004000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK                                           0x00008000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_UP_INT_OCCURRED_MASK                                             0x00010000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK                                           0x00020000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_UP_INT_OCCURRED_MASK                                             0x00040000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK                                           0x00080000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_UP_INT_OCCURRED_MASK                                            0x00100000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK                                          0x00200000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_UP_INT_OCCURRED_MASK                                            0x00400000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK                                          0x00800000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_UP_INT_OCCURRED_MASK                                            0x01000000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK                                          0x02000000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_UP_INT_OCCURRED_MASK                                            0x04000000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK                                          0x08000000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_UP_INT_OCCURRED_MASK                                            0x10000000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK                                          0x20000000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_UP_INT_OCCURRED_MASK                                            0x40000000L
>+#define DCPG_INTERRUPT_STATUS__DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK                                          0x80000000L
>+//DCPG_INTERRUPT_STATUS_2
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                                        0x0
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                                        0x2
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                                        0x4
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                                        0x6
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x7
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT                                        0x8
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x9
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT                                        0xa
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT                                      0xb
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                          0x00000040L
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000080L
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_UP_INT_OCCURRED_MASK                                          0x00000100L
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000200L
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_UP_INT_OCCURRED_MASK                                          0x00000400L
>+#define DCPG_INTERRUPT_STATUS_2__DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000800L
>+//DCPG_INTERRUPT_CONTROL_1
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT                                            0x0
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                           0x1
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT                                          0x2
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT                                            0x4
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                           0x5
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT                                          0x6
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT                                            0x8
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                           0x9
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT                                          0xa
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                         0xb
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT                                            0xc
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                           0xd
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT                                          0xe
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                         0xf
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK__SHIFT                                            0x10
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR__SHIFT                                           0x11
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK__SHIFT                                          0x12
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT                                         0x13
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK__SHIFT                                            0x14
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR__SHIFT                                           0x15
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK__SHIFT                                          0x16
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT                                         0x17
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK__SHIFT                                            0x18
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR__SHIFT                                           0x19
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK__SHIFT                                          0x1a
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT                                         0x1b
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK__SHIFT                                            0x1c
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR__SHIFT                                           0x1d
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK__SHIFT                                          0x1e
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT                                         0x1f
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK                                              0x00000001L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK                                             0x00000002L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK                                            0x00000004L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK                                              0x00000010L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK                                             0x00000020L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK                                            0x00000040L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK                                              0x00000100L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK                                             0x00000200L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK                                            0x00000400L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                           0x00000800L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK                                              0x00001000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK                                             0x00002000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK                                            0x00004000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                           0x00008000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_MASK_MASK                                              0x00010000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_UP_INT_CLEAR_MASK                                             0x00020000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_MASK_MASK                                            0x00040000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN4_POWER_DOWN_INT_CLEAR_MASK                                           0x00080000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_MASK_MASK                                              0x00100000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_UP_INT_CLEAR_MASK                                             0x00200000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_MASK_MASK                                            0x00400000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN5_POWER_DOWN_INT_CLEAR_MASK                                           0x00800000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_MASK_MASK                                              0x01000000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_UP_INT_CLEAR_MASK                                             0x02000000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_MASK_MASK                                            0x04000000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN6_POWER_DOWN_INT_CLEAR_MASK                                           0x08000000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_MASK_MASK                                              0x10000000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_UP_INT_CLEAR_MASK                                             0x20000000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_MASK_MASK                                            0x40000000L
>+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN7_POWER_DOWN_INT_CLEAR_MASK                                           0x80000000L
>+//DCPG_INTERRUPT_CONTROL_2
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK__SHIFT                                            0x0
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR__SHIFT                                           0x1
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK__SHIFT                                          0x2
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK__SHIFT                                            0x4
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR__SHIFT                                           0x5
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK__SHIFT                                          0x6
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK__SHIFT                                           0x8
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR__SHIFT                                          0x9
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK__SHIFT                                         0xa
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK__SHIFT                                           0xc
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR__SHIFT                                          0xd
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK__SHIFT                                         0xe
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK__SHIFT                                           0x10
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR__SHIFT                                          0x11
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK__SHIFT                                         0x12
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT                                        0x13
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK__SHIFT                                           0x14
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR__SHIFT                                          0x15
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK__SHIFT                                         0x16
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT                                        0x17
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK__SHIFT                                           0x18
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR__SHIFT                                          0x19
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK__SHIFT                                         0x1a
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT                                        0x1b
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK__SHIFT                                           0x1c
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR__SHIFT                                          0x1d
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK__SHIFT                                         0x1e
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT                                        0x1f
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_MASK_MASK                                              0x00000001L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_UP_INT_CLEAR_MASK                                             0x00000002L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_MASK_MASK                                            0x00000004L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN8_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_MASK_MASK                                              0x00000010L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_UP_INT_CLEAR_MASK                                             0x00000020L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_MASK_MASK                                            0x00000040L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN9_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_MASK_MASK                                             0x00000100L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_UP_INT_CLEAR_MASK                                            0x00000200L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_MASK_MASK                                           0x00000400L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN10_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_MASK_MASK                                             0x00001000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_UP_INT_CLEAR_MASK                                            0x00002000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_MASK_MASK                                           0x00004000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN11_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_MASK_MASK                                             0x00010000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_UP_INT_CLEAR_MASK                                            0x00020000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_MASK_MASK                                           0x00040000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN12_POWER_DOWN_INT_CLEAR_MASK                                          0x00080000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_MASK_MASK                                             0x00100000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_UP_INT_CLEAR_MASK                                            0x00200000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_MASK_MASK                                           0x00400000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN13_POWER_DOWN_INT_CLEAR_MASK                                          0x00800000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_MASK_MASK                                             0x01000000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_UP_INT_CLEAR_MASK                                            0x02000000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_MASK_MASK                                           0x04000000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN14_POWER_DOWN_INT_CLEAR_MASK                                          0x08000000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_MASK_MASK                                             0x10000000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_UP_INT_CLEAR_MASK                                            0x20000000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_MASK_MASK                                           0x40000000L
>+#define DCPG_INTERRUPT_CONTROL_2__DOMAIN15_POWER_DOWN_INT_CLEAR_MASK                                          0x80000000L
>+//DCPG_INTERRUPT_CONTROL_3
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT                                           0x0
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                          0x1
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT                                         0x2
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT                                           0x4
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                          0x5
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT                                         0x6
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT                                           0x8
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                          0x9
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT                                         0xa
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK__SHIFT                                           0xc
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                          0xd
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT                                         0xe
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                        0xf
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK__SHIFT                                           0x10
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR__SHIFT                                          0x11
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK__SHIFT                                         0x12
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT                                        0x13
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK__SHIFT                                           0x14
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR__SHIFT                                          0x15
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK__SHIFT                                         0x16
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT                                        0x17
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK                                             0x00000001L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK                                            0x00000002L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK                                           0x00000004L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK                                             0x00000010L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK                                            0x00000020L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK                                           0x00000040L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK                                             0x00000100L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK                                            0x00000200L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK                                           0x00000400L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_MASK_MASK                                             0x00001000L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_UP_INT_CLEAR_MASK                                            0x00002000L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_MASK_MASK                                           0x00004000L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                          0x00008000L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_MASK_MASK                                             0x00010000L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_UP_INT_CLEAR_MASK                                            0x00020000L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_MASK_MASK                                           0x00040000L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN20_POWER_DOWN_INT_CLEAR_MASK                                          0x00080000L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_MASK_MASK                                             0x00100000L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_UP_INT_CLEAR_MASK                                            0x00200000L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_MASK_MASK                                           0x00400000L
>+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN21_POWER_DOWN_INT_CLEAR_MASK                                          0x00800000L
>+//DC_IP_REQUEST_CNTL
>+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT                                                              0x0
>+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK                                                                0x00000001L
>+
>+
>+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON2_PERFCOUNTER_CNTL
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
>+//DC_PERFMON2_PERFCOUNTER_CNTL2
>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
>+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
>+//DC_PERFMON2_PERFCOUNTER_STATE
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
>+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
>+//DC_PERFMON2_PERFMON_CNTL
>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
>+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
>+//DC_PERFMON2_PERFMON_CNTL2
>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
>+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
>+//DC_PERFMON2_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
>+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
>+//DC_PERFMON2_PERFMON_CVALUE_LOW
>+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
>+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
>+//DC_PERFMON2_PERFMON_HI
>+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
>+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
>+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
>+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
>+//DC_PERFMON2_PERFMON_LOW
>+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
>+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
>+//CC_DC_PIPE_DIS
>+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT                                                                    0x0
>+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT                                                                0x10
>+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK                                                                      0x000000FFL
>+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK                                                                  0x00010000L
>+//DMU_CLK_CNTL
>+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT                                                                 0x0
>+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT                                                           0x4
>+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT                                                          0x5
>+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT                                                        0x6
>+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT                                                               0x8
>+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON__SHIFT                                                          0x9
>+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT                                                        0xa
>+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK                                                                   0x0000000FL
>+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK                                                             0x00000010L
>+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK                                                            0x00000020L
>+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK                                                          0x00000040L
>+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK                                                                 0x00000100L
>+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON_MASK                                                            0x00000200L
>+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK                                                          0x00000400L
>+//DMU_MEM_PWR_CNTL
>+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT                                                   0x0
>+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT                                                      0x1
>+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT                                                        0x3
>+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT                                                      0x4
>+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT                                                      0x8
>+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT                                                        0x9
>+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT                                                      0xa
>+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK                                                     0x00000001L
>+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK                                                        0x00000006L
>+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK                                                          0x00000008L
>+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK                                                        0x00000030L
>+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK                                                        0x00000100L
>+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK                                                          0x00000200L
>+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK                                                        0x00000400L
>+//DMCU_SMU_INTERRUPT_CNTL
>+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT                                            0x0
>+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT                                         0x10
>+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK                                              0x00000001L
>+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK                                           0xFFFF0000L
>+//SMU_INTERRUPT_CONTROL
>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT                                                       0x0
>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT                                                       0x4
>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT                                                        0x10
>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK                                                         0x00000001L
>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK                                                         0x00000010L
>+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK                                                          0xFFFF0000L
>+//DMU_MISC_ALLOW_DS_FORCE
>+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT                                            0x0
>+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT                                         0x4
>+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK                                              0x00000001L
>+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK                                           0x00000010L
>+
>+
>+// addressBlock: dce_dc_dmu_dmcu_dispdec
>+//DMCU_CTRL
>+#define DMCU_CTRL__RESET_UC__SHIFT                                                                            0x0
>+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT                                                                       0x1
>+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT                                                                   0x2
>+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT                                                                  0x3
>+#define DMCU_CTRL__DMCU_ENABLE__SHIFT                                                                         0x4
>+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT                                                              0x8
>+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT                                                                   0x10
>+#define DMCU_CTRL__RESET_UC_MASK                                                                              0x00000001L
>+#define DMCU_CTRL__IGNORE_PWRMGT_MASK                                                                         0x00000002L
>+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK                                                                     0x00000004L
>+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK                                                                    0x00000008L
>+#define DMCU_CTRL__DMCU_ENABLE_MASK                                                                           0x00000010L
>+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK                                                                0x00000100L
>+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK                                                                     0xFFFF0000L
>+//DMCU_STATUS
>+#define DMCU_STATUS__UC_IN_RESET__SHIFT                                                                       0x0
>+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT                                                                   0x1
>+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT                                                                   0x2
>+#define DMCU_STATUS__UC_IN_RESET_MASK                                                                         0x00000001L
>+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK                                                                     0x00000002L
>+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK                                                                     0x00000004L
>+//DMCU_PC_START_ADDR
>+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT                                                          0x0
>+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT                                                          0x8
>+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK                                                            0x000000FFL
>+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK                                                            0x0000FF00L
>+//DMCU_FW_START_ADDR
>+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT                                                          0x0
>+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT                                                          0x8
>+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK                                                            0x000000FFL
>+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK                                                            0x0000FF00L
>+//DMCU_FW_END_ADDR
>+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT                                                              0x0
>+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT                                                              0x8
>+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK                                                                0x000000FFL
>+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK                                                                0x0000FF00L
>+//DMCU_FW_ISR_START_ADDR
>+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT                                                  0x0
>+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT                                                  0x8
>+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK                                                    0x000000FFL
>+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK                                                    0x0000FF00L
>+//DMCU_FW_CS_HI
>+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT                                                                  0x0
>+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK                                                                    0xFFFFFFFFL
>+//DMCU_FW_CS_LO
>+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT                                                                  0x0
>+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK                                                                    0xFFFFFFFFL
>+//DMCU_RAM_ACCESS_CTRL
>+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT                                                    0x0
>+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT                                                    0x1
>+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT                                                    0x2
>+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT                                                    0x3
>+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT                                                      0x4
>+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT                                                      0x5
>+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK                                                      0x00000001L
>+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK                                                      0x00000002L
>+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK                                                      0x00000004L
>+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK                                                      0x00000008L
>+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK                                                        0x00000010L
>+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK                                                        0x00000020L
>+//DMCU_ERAM_WR_CTRL
>+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT                                                                0x0
>+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT                                                                  0x10
>+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT                                                           0x14
>+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK                                                                  0x0000FFFFL
>+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK                                                                    0x000F0000L
>+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK                                                             0x00100000L
>+//DMCU_ERAM_WR_DATA
>+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT                                                                0x0
>+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK                                                                  0xFFFFFFFFL
>+//DMCU_ERAM_RD_CTRL
>+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT                                                                0x0
>+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT                                                                  0x10
>+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT                                                           0x14
>+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK                                                                  0x0000FFFFL
>+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK                                                                    0x000F0000L
>+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK                                                             0x00100000L
>+//DMCU_ERAM_RD_DATA
>+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT                                                                0x0
>+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK                                                                  0xFFFFFFFFL
>+//DMCU_IRAM_WR_CTRL
>+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT                                                                0x0
>+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK                                                                  0x000003FFL
>+//DMCU_IRAM_WR_DATA
>+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT                                                                0x0
>+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK                                                                  0x000000FFL
>+//DMCU_IRAM_RD_CTRL
>+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT                                                                0x0
>+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK                                                                  0x000003FFL
>+//DMCU_IRAM_RD_DATA
>+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT                                                                0x0
>+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK                                                                  0x000000FFL
>+//DMCU_EVENT_TRIGGER
>+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT                                                           0x0
>+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT                                                       0x10
>+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT                                                0x17
>+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK                                                             0x00000001L
>+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK                                                         0x007F0000L
>+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK                                                  0x00800000L
>+//DMCU_UC_INTERNAL_INT_STATUS
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT                                                  0x0
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT                                                 0x1
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT                                         0x2
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT                                        0x3
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT                                     0x4
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT                                     0x5
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT                                     0x6
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT                                     0x7
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT                                             0x8
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT                                        0x9
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT                     0xa
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT                                      0xb
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT                                      0xc
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT                                      0xd
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT                               0xe
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT                                 0xf
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK                                                    0x00000001L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK                                                   0x00000002L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK                                           0x00000004L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK                                          0x00000008L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK                                       0x00000010L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK                                       0x00000020L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK                                       0x00000040L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK                                       0x00000080L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK                                               0x00000100L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK                                          0x00000200L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK                       0x00000400L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK                                        0x00000800L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK                                        0x00001000L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK                                        0x00002000L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK                                 0x00004000L
>+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK                                   0x00008000L
>+//DMCU_SS_INTERRUPT_CNTL_STATUS
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT                                       0xd
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT                                     0xe
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT                                        0xe
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT                                       0xf
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT                                     0x10
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT                                        0x10
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT                                       0x11
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT                                     0x12
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT                                        0x12
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT                                       0x13
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT                                     0x14
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT                                        0x14
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT                                       0x15
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT                                     0x16
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT                                        0x16
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT                                       0x17
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT                                     0x18
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT                                        0x18
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK                                         0x00002000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK                                       0x00004000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK                                          0x00004000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK                                         0x00008000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK                                       0x00010000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK                                          0x00010000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK                                         0x00020000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK                                       0x00040000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK                                          0x00040000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK                                         0x00080000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK                                       0x00100000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK                                          0x00100000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK                                         0x00200000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK                                       0x00400000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK                                          0x00400000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK                                         0x00800000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK                                       0x01000000L
>+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK                                          0x01000000L
>+//DMCU_INTERRUPT_STATUS
>+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT                                              0x0
>+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT                                                 0x0
>+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT                                              0x1
>+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT                                                 0x1
>+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT                                             0x2
>+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT                                                0x2
>+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT                                                        0x3
>+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT                                                0x8
>+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT                                                   0x8
>+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT                                                        0x9
>+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT                                                0xa
>+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT                                                   0xa
>+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT                                          0xb
>+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT                                             0xb
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                  0xc
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                     0xc
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                  0xd
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                     0xd
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                  0xe
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                     0xe
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                  0xf
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                     0xf
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT                                  0x10
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR__SHIFT                                     0x10
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT                                  0x11
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR__SHIFT                                     0x11
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                0x12
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                   0x12
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                0x13
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                   0x13
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                0x14
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                   0x14
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                0x15
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                   0x15
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT                                0x16
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT                                   0x16
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT                                0x17
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT                                   0x17
>+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT                                                    0x18
>+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT                                                       0x18
>+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT                                                    0x19
>+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT                                                       0x19
>+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT                                                    0x1a
>+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT                                                       0x1a
>+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT                                                    0x1b
>+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT                                                       0x1b
>+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT                                                    0x1c
>+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT                                                       0x1c
>+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT                                                    0x1d
>+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT                                                       0x1d
>+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK                                                0x00000001L
>+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK                                                   0x00000001L
>+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK                                                0x00000002L
>+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK                                                   0x00000002L
>+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK                                               0x00000004L
>+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK                                                  0x00000004L
>+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK                                                          0x00000008L
>+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK                                                  0x00000100L
>+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK                                                     0x00000100L
>+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK                                                          0x00000200L
>+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK                                                  0x00000400L
>+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK                                                     0x00000400L
>+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK                                            0x00000800L
>+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK                                               0x00000800L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                    0x00001000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR_MASK                                       0x00001000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                    0x00002000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR_MASK                                       0x00002000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                    0x00004000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR_MASK                                       0x00004000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                    0x00008000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR_MASK                                       0x00008000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED_MASK                                    0x00010000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR_MASK                                       0x00010000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED_MASK                                    0x00020000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR_MASK                                       0x00020000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                  0x00040000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                     0x00040000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                  0x00080000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                     0x00080000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                  0x00100000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                     0x00100000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                  0x00200000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                     0x00200000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK                                  0x00400000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR_MASK                                     0x00400000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK                                  0x00800000L
>+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR_MASK                                     0x00800000L
>+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK                                                      0x01000000L
>+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK                                                         0x01000000L
>+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK                                                      0x02000000L
>+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK                                                         0x02000000L
>+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK                                                      0x04000000L
>+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK                                                         0x04000000L
>+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK                                                      0x08000000L
>+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK                                                         0x08000000L
>+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK                                                      0x10000000L
>+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK                                                         0x10000000L
>+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK                                                      0x20000000L
>+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK                                                         0x20000000L
>+//DMCU_INTERRUPT_STATUS_1
>+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x6
>+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x6
>+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x7
>+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x7
>+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x8
>+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x8
>+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x9
>+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x9
>+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0xa
>+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0xa
>+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0xb
>+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0xb
>+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT                                       0xd
>+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT                                          0xd
>+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000040L
>+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000040L
>+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000080L
>+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000080L
>+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000100L
>+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000100L
>+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000200L
>+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000200L
>+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000400L
>+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000400L
>+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000800L
>+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000800L
>+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK                                         0x00002000L
>+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK                                            0x00002000L
>+//DMCU_INTERRUPT_TO_HOST_EN_MASK
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT                                         0x0
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT                                         0x1
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT                                        0x2
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT                                         0x3
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT                                         0x4
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT                                        0x5
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT                                                   0x9
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT                                           0xa
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT                                     0xb
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK                                           0x00000001L
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK                                           0x00000002L
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK                                          0x00000004L
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK                                           0x00000008L
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK                                           0x00000010L
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK                                          0x00000020L
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK                                                     0x00000200L
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK                                             0x00000400L
>+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK                                       0x00000800L
>+//DMCU_INTERRUPT_TO_UC_EN_MASK
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT                                       0x0
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT                                       0x1
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT                                      0x2
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT                                                 0x3
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT                                      0x6
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT                                      0x7
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT                                         0x8
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT                                      0x9
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT                                      0xa
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT                                      0xb
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN__SHIFT                           0xc
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN__SHIFT                           0xd
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN__SHIFT                           0xe
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN__SHIFT                           0xf
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN__SHIFT                           0x10
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN__SHIFT                           0x11
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x12
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x13
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x14
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x15
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x16
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x17
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT                                             0x18
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT                                             0x19
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT                                             0x1a
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT                                             0x1b
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT                                             0x1c
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT                                             0x1d
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT                                      0x1e
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK                                         0x00000001L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK                                         0x00000002L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK                                        0x00000004L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK                                                   0x00000008L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK                                        0x00000040L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK                                        0x00000080L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK                                           0x00000100L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK                                        0x00000200L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK                                        0x00000400L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK                                        0x00000800L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN_MASK                             0x00001000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN_MASK                             0x00002000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN_MASK                             0x00004000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN_MASK                             0x00008000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN_MASK                             0x00010000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN_MASK                             0x00020000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00040000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00080000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00100000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00200000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00400000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00800000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK                                               0x01000000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK                                               0x02000000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK                                               0x04000000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK                                               0x08000000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK                                               0x10000000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK                                               0x20000000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK                                        0x40000000L
>+//DMCU_INTERRUPT_TO_UC_EN_MASK_1
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x6
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x7
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x8
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x9
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0xa
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0xb
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT                                      0xd
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000040L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000080L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000100L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000200L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000400L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000800L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK                                        0x00002000L
>+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                              0x0
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                              0x1
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                             0x2
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT                                        0x3
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT                             0x6
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT                             0x7
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT                                0x8
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT                             0x9
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT                             0xa
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT                             0xb
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xc
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xd
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xe
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xf
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0x10
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0x11
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x12
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x13
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x14
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x15
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x16
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x17
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT                                    0x18
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT                                    0x19
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1a
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1b
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1c
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1d
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT                             0x1e
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK                                0x00000001L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK                                0x00000002L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                               0x00000004L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK                                          0x00000008L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK                               0x00000040L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK                               0x00000080L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK                                  0x00000100L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK                               0x00000200L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK                               0x00000400L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK                               0x00000800L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00001000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00002000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00004000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00008000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00010000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00020000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00040000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00080000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00100000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00200000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00400000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00800000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK                                      0x01000000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK                                      0x02000000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK                                      0x04000000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK                                      0x08000000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK                                      0x10000000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK                                      0x20000000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK                               0x40000000L
>+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x6
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x7
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x8
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x9
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0xa
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0xb
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT                             0xd
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000040L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000080L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000100L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000200L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000400L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000800L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK                               0x00002000L
>+//DC_DMCU_SCRATCH
>+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT                                                                  0x0
>+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK                                                                    0xFFFFFFFFL
>+//DMCU_INT_CNT
>+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT                                                       0x0
>+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT                                                       0x8
>+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT                                                      0x10
>+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK                                                         0x000000FFL
>+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK                                                         0x0000FF00L
>+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK                                                        0x00FF0000L
>+//DMCU_FW_CHECKSUM_SMPL_BYTE_POS
>+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT                              0x0
>+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT                              0x2
>+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK                                0x00000003L
>+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK                                0x0000000CL
>+//DMCU_UC_CLK_GATING_CNTL
>+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT                                                      0x0
>+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT                                                      0x8
>+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT                                              0x10
>+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK                                                        0x00000007L
>+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK                                                        0x00000700L
>+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK                                                0x00010000L
>+//MASTER_COMM_DATA_REG1
>+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT                                             0x0
>+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT                                             0x8
>+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT                                             0x10
>+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT                                             0x18
>+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK                                               0x000000FFL
>+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK                                               0x0000FF00L
>+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK                                               0x00FF0000L
>+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK                                               0xFF000000L
>+//MASTER_COMM_DATA_REG2
>+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT                                             0x0
>+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT                                             0x8
>+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT                                             0x10
>+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT                                             0x18
>+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK                                               0x000000FFL
>+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK                                               0x0000FF00L
>+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK                                               0x00FF0000L
>+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK                                               0xFF000000L
>+//MASTER_COMM_DATA_REG3
>+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT                                             0x0
>+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT                                             0x8
>+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT                                             0x10
>+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT                                             0x18
>+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK                                               0x000000FFL
>+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK                                               0x0000FF00L
>+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK                                               0x00FF0000L
>+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK                                               0xFF000000L
>+//MASTER_COMM_CMD_REG
>+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT                                                 0x0
>+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT                                                 0x8
>+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT                                                 0x10
>+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT                                                 0x18
>+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK                                                   0x000000FFL
>+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK                                                   0x0000FF00L
>+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK                                                   0x00FF0000L
>+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK                                                   0xFF000000L
>+//MASTER_COMM_CNTL_REG
>+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT                                                    0x0
>+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK                                                      0x00000001L
>+//SLAVE_COMM_DATA_REG1
>+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT                                               0x0
>+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT                                               0x8
>+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT                                               0x10
>+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT                                               0x18
>+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK                                                 0x000000FFL
>+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK                                                 0x0000FF00L
>+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK                                                 0x00FF0000L
>+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK                                                 0xFF000000L
>+//SLAVE_COMM_DATA_REG2
>+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT                                               0x0
>+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT                                               0x8
>+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT                                               0x10
>+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT                                               0x18
>+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK                                                 0x000000FFL
>+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK                                                 0x0000FF00L
>+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK                                                 0x00FF0000L
>+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK                                                 0xFF000000L
>+//SLAVE_COMM_DATA_REG3
>+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT                                               0x0
>+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT                                               0x8
>+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT                                               0x10
>+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT                                               0x18
>+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK                                                 0x000000FFL
>+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK                                                 0x0000FF00L
>+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK                                                 0x00FF0000L
>+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK                                                 0xFF000000L
>+//SLAVE_COMM_CMD_REG
>+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT                                                   0x0
>+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT                                                   0x8
>+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT                                                   0x10
>+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT                                                   0x18
>+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK                                                     0x000000FFL
>+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK                                                     0x0000FF00L
>+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK                                                     0x00FF0000L
>+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK                                                     0xFF000000L
>+//SLAVE_COMM_CNTL_REG
>+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT                                                      0x0
>+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT                                         0x8
>+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK                                                        0x00000001L
>+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK                                           0x00000100L
>+//DMCU_PERFMON_INTERRUPT_STATUS1
>+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
>+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
>+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
>+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
>+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
>+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
>+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
>+//DMCU_PERFMON_INTERRUPT_STATUS2
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x0
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x0
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x1
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x1
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x2
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x2
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x3
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x3
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x4
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x4
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x5
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x5
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x6
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x6
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x7
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x7
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT                            0x8
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT                               0x8
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000020L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000020L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000040L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000040L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000080L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000080L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK                              0x00000100L
>+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK                                 0x00000100L
>+//DMCU_PERFMON_INTERRUPT_STATUS3
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x0
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x0
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x1
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x1
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x3
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x3
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x4
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x4
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x5
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x5
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x6
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x6
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x7
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x7
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000020L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000020L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000040L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000040L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000080L
>+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000080L
>+//DMCU_PERFMON_INTERRUPT_STATUS4
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT                             0x2
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT                                0x2
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT                          0x3
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT                             0x3
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x4
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x4
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK                               0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK                                  0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK                            0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK                               0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000010L
>+//DMCU_PERFMON_INTERRUPT_STATUS5
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x3
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x3
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x4
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x4
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x5
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x5
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x6
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x6
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x7
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x7
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x8
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x8
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x9
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x9
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000020L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000020L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000040L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000040L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000080L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000080L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000100L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000100L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000200L
>+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000200L
>+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
>+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x0
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x1
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x2
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x3
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x4
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x5
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x6
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x7
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                     0x8
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000020L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000040L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000080L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK                       0x00000100L
>+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x0
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x1
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x3
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x4
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x5
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x6
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x7
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000020L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000040L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000080L
>+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT                      0x2
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                   0x3
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x4
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK                        0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK                     0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000010L
>+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x3
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x4
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x5
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x6
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x7
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x8
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x9
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000020L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000040L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000080L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000100L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000200L
>+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x1
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x2
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000004L
>+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x0
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x1
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x2
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x3
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x4
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x5
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x6
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x7
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT            0x8
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000020L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000040L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000080L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK              0x00000100L
>+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x0
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x1
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x2
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x3
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x4
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x5
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x6
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x7
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000040L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000080L
>+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x1
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x2
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT          0x3
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x4
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK            0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000010L
>+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x1
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x2
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x3
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x4
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x5
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x6
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x7
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x8
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x9
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000002L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000004L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000008L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000040L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000080L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000100L
>+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000200L
>+//DMCU_DPRX_INTERRUPT_STATUS1
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT                              0x0
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT                                 0x0
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT            0x1
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT               0x1
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT                                 0x2
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT                                    0x2
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT                                 0x3
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT                                    0x3
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT                              0x4
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT                                 0x4
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT                              0x5
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT                                 0x5
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT            0x6
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT               0x6
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT                                 0x7
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT                                    0x7
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT                                 0x8
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT                                    0x8
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT                              0x9
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT                                 0x9
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT       0xa
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT          0xa
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT       0xb
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT          0xb
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT            0xc
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT               0xc
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT         0xd
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT            0xd
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT          0xe
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT             0xe
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT      0xf
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT         0xf
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT               0x10
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT                  0x10
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT                          0x11
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT                             0x11
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT                           0x12
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT                              0x12
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT                          0x13
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT                             0x13
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT                         0x14
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT                            0x14
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT                    0x15
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT                       0x15
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT                                      0x16
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT                                         0x16
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT                                      0x17
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT                                         0x17
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT                                      0x18
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT                                         0x18
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT                             0x19
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT                                0x19
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT                             0x1a
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT                                0x1a
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT                             0x1b
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT                                0x1b
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT                             0x1c
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT                                0x1c
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK                                0x00000001L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK                                   0x00000001L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK              0x00000002L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK                 0x00000002L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK                                   0x00000004L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK                                      0x00000004L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK                                   0x00000008L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK                                      0x00000008L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK                                0x00000010L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK                                   0x00000010L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK                                0x00000020L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK                                   0x00000020L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK              0x00000040L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK                 0x00000040L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK                                   0x00000080L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK                                      0x00000080L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK                                   0x00000100L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK                                      0x00000100L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK                                0x00000200L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK                                   0x00000200L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK         0x00000400L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK            0x00000400L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK         0x00000800L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK            0x00000800L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK              0x00001000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK                 0x00001000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK           0x00002000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK              0x00002000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK            0x00004000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK               0x00004000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK        0x00008000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK           0x00008000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK                 0x00010000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK                    0x00010000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK                            0x00020000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK                               0x00020000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK                             0x00040000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK                                0x00040000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK                            0x00080000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK                               0x00080000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK                           0x00100000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK                              0x00100000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK                      0x00200000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK                         0x00200000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK                                        0x00400000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK                                           0x00400000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK                                        0x00800000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK                                           0x00800000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK                                        0x01000000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK                                           0x01000000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK                               0x02000000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK                                  0x02000000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK                               0x04000000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK                                  0x04000000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK                               0x08000000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK                                  0x08000000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK                               0x10000000L
>+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK                                  0x10000000L
>+//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT                       0x0
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT     0x1
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT                          0x2
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT                          0x3
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT                       0x4
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT                       0x5
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT     0x6
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT                          0x7
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT                          0x8
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT                       0x9
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xa
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xb
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT     0xc
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xd
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT   0xe
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xf
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT        0x10
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT                   0x11
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT                    0x12
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT                   0x13
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT                  0x14
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT             0x15
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT                               0x16
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT                               0x17
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT                               0x18
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x19
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1a
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1b
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1c
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK                         0x00000001L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK       0x00000002L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK                            0x00000004L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK                            0x00000008L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK                         0x00000010L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK                         0x00000020L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK       0x00000040L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK                            0x00000080L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK                            0x00000100L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK                         0x00000200L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00000400L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00000800L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK       0x00001000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK    0x00002000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK     0x00004000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00008000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK          0x00010000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK                     0x00020000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK                      0x00040000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK                     0x00080000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK                    0x00100000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK               0x00200000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK                                 0x00400000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK                                 0x00800000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK                                 0x01000000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK                        0x02000000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK                        0x04000000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK                        0x08000000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK                        0x10000000L
>+//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x0
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT  0x1
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT                 0x2
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT                 0x3
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x4
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x5
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT  0x6
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT                 0x7
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT                 0x8
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x9
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xa
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xb
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xc
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xd
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xe
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xf
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0x10
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT          0x11
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT           0x12
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT          0x13
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT         0x14
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT    0x15
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT                      0x16
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT                      0x17
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT                      0x18
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x19
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1a
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1b
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1c
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000001L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK  0x00000002L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK                   0x00000004L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK                   0x00000008L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK  0x00000040L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK                   0x00000080L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK                   0x00000100L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000200L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00000400L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00000800L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00001000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00002000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00004000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00008000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00010000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK            0x00020000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK             0x00040000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK            0x00080000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK           0x00100000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK      0x00200000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK                        0x00400000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK                        0x00800000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK                        0x01000000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x02000000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x04000000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x08000000L
>+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x10000000L
>+//DMCU_INTERRUPT_STATUS_CONTINUE
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT                         0x0
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR__SHIFT                            0x0
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT                         0x1
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR__SHIFT                            0x1
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT                         0x2
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR__SHIFT                            0x2
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT                         0x3
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR__SHIFT                            0x3
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT                        0x4
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR__SHIFT                           0x4
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT                        0x5
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR__SHIFT                           0x5
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT                        0x6
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR__SHIFT                           0x6
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT                        0x7
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR__SHIFT                           0x7
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT                        0x8
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR__SHIFT                           0x8
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT                        0x9
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR__SHIFT                           0x9
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT                       0xa
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT                          0xa
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT                       0xb
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT                          0xb
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT                       0xc
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT                          0xc
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT                       0xd
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT                          0xd
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT                      0xe
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT                         0xe
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT                      0xf
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT                         0xf
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT                      0x10
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT                         0x10
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT                      0x11
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT                         0x11
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT                      0x12
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT                         0x12
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT                      0x13
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT                         0x13
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT                          0x14
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT                             0x14
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT                          0x15
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT                             0x15
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT                          0x16
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT                             0x16
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT                          0x17
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT                             0x17
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT                          0x18
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT                             0x18
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT                          0x19
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT                             0x19
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT                                     0x1a
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT                                        0x1a
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT                                     0x1b
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT                                        0x1b
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT                                    0x1c
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT                                       0x1c
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED_MASK                           0x00000001L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR_MASK                              0x00000001L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED_MASK                           0x00000002L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR_MASK                              0x00000002L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED_MASK                           0x00000004L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR_MASK                              0x00000004L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED_MASK                           0x00000008L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR_MASK                              0x00000008L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED_MASK                          0x00000010L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR_MASK                             0x00000010L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED_MASK                          0x00000020L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR_MASK                             0x00000020L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED_MASK                          0x00000040L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR_MASK                             0x00000040L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED_MASK                          0x00000080L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR_MASK                             0x00000080L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED_MASK                          0x00000100L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR_MASK                             0x00000100L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED_MASK                          0x00000200L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR_MASK                             0x00000200L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK                         0x00000400L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR_MASK                            0x00000400L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK                         0x00000800L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR_MASK                            0x00000800L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK                         0x00001000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR_MASK                            0x00001000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK                         0x00002000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR_MASK                            0x00002000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK                        0x00004000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR_MASK                           0x00004000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK                        0x00008000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR_MASK                           0x00008000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK                        0x00010000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR_MASK                           0x00010000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK                        0x00020000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR_MASK                           0x00020000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK                        0x00040000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR_MASK                           0x00040000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK                        0x00080000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR_MASK                           0x00080000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK                            0x00100000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK                               0x00100000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK                            0x00200000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK                               0x00200000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK                            0x00400000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK                               0x00400000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK                            0x00800000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK                               0x00800000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK                            0x01000000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK                               0x01000000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK                            0x02000000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK                               0x02000000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK                                       0x04000000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK                                          0x04000000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK                                       0x08000000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK                                          0x08000000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK                                      0x10000000L
>+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK                                         0x10000000L
>+//DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN__SHIFT                  0x0
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN__SHIFT                  0x1
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN__SHIFT                  0x2
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN__SHIFT                  0x3
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN__SHIFT                 0x4
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN__SHIFT                 0x5
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN__SHIFT                 0x6
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN__SHIFT                 0x7
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN__SHIFT                 0x8
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN__SHIFT                 0x9
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xa
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xb
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xc
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xd
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN__SHIFT               0xe
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN__SHIFT               0xf
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x10
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x11
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x12
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x13
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT                   0x14
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT                   0x15
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT                   0x16
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT                   0x17
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT                   0x18
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT                   0x19
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT                              0x1a
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT                              0x1b
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT                             0x1c
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN_MASK                    0x00000001L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN_MASK                    0x00000002L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN_MASK                    0x00000004L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN_MASK                    0x00000008L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN_MASK                   0x00000010L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN_MASK                   0x00000020L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN_MASK                   0x00000040L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN_MASK                   0x00000080L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN_MASK                   0x00000100L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN_MASK                   0x00000200L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00000400L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00000800L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00001000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00002000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00004000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00008000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00010000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00020000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00040000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00080000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK                     0x00100000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK                     0x00200000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK                     0x00400000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK                     0x00800000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK                     0x01000000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK                     0x02000000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK                                0x04000000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK                                0x08000000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK                               0x10000000L
>+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x0
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x1
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x2
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x3
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x4
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x5
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x6
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x7
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x8
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x9
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xa
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xb
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xc
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xd
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0xe
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0xf
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x10
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x11
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x12
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x13
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT          0x14
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT          0x15
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT          0x16
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT          0x17
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT          0x18
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT          0x19
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                     0x1a
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                     0x1b
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                    0x1c
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000001L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000002L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000004L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000008L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000010L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000020L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000040L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000080L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000100L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000200L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00000400L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00000800L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00001000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00002000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00004000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00008000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00010000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00020000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00040000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00080000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK            0x00100000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK            0x00200000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK            0x00400000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK            0x00800000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK            0x01000000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK            0x02000000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK                       0x04000000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK                       0x08000000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                      0x10000000L
>+//DMCU_INT_CNT_CONTINUE
>+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT                                              0x0
>+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT                                              0x8
>+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT                                             0x10
>+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK                                                0x000000FFL
>+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK                                                0x0000FF00L
>+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK                                               0x00FF0000L
>+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x0
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x1
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x2
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x3
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x4
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x5
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x6
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x7
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x8
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x9
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0xa
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0xb
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL__SHIFT                        0x10
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL__SHIFT                        0x11
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL__SHIFT                        0x12
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL__SHIFT                        0x13
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL__SHIFT                        0x14
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL__SHIFT                        0x15
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL__SHIFT                        0x16
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000001L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000002L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000004L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000008L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000010L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000020L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000040L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000080L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000100L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000200L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000400L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000800L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL_MASK                          0x00010000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL_MASK                          0x00020000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL_MASK                          0x00040000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL_MASK                          0x00080000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL_MASK                          0x00100000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL_MASK                          0x00200000L
>+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL_MASK                          0x00400000L
>+//DMCU_INTERRUPT_STATUS_2
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                               0x0
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                  0x0
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                               0x1
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                  0x1
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                               0x2
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                  0x2
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                               0x3
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                  0x3
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT                               0x4
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR__SHIFT                                  0x4
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT                               0x5
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR__SHIFT                                  0x5
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                             0x6
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                0x6
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                             0x7
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                0x7
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                             0x8
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                0x8
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                             0x9
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                0x9
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT                             0xa
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT                                0xa
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT                             0xb
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT                                0xb
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED__SHIFT                                            0x10
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR__SHIFT                                               0x10
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED__SHIFT                                            0x11
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR__SHIFT                                               0x11
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED__SHIFT                                            0x12
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR__SHIFT                                               0x12
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED__SHIFT                                            0x13
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR__SHIFT                                               0x13
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED__SHIFT                                            0x14
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR__SHIFT                                               0x14
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED__SHIFT                                            0x15
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR__SHIFT                                               0x15
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED__SHIFT                                            0x16
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR__SHIFT                                               0x16
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                 0x00000001L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR_MASK                                    0x00000001L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                 0x00000002L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR_MASK                                    0x00000002L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                 0x00000004L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR_MASK                                    0x00000004L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                 0x00000008L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR_MASK                                    0x00000008L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED_MASK                                 0x00000010L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR_MASK                                    0x00000010L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED_MASK                                 0x00000020L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR_MASK                                    0x00000020L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                               0x00000040L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                  0x00000040L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                               0x00000080L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                  0x00000080L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                               0x00000100L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                  0x00000100L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                               0x00000200L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                  0x00000200L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK                               0x00000400L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR_MASK                                  0x00000400L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK                               0x00000800L
>+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR_MASK                                  0x00000800L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED_MASK                                              0x00010000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR_MASK                                                 0x00010000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED_MASK                                              0x00020000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR_MASK                                                 0x00020000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED_MASK                                              0x00040000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR_MASK                                                 0x00040000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED_MASK                                              0x00080000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR_MASK                                                 0x00080000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED_MASK                                              0x00100000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR_MASK                                                 0x00100000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED_MASK                                              0x00200000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR_MASK                                                 0x00200000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED_MASK                                              0x00400000L
>+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR_MASK                                                 0x00400000L
>+//DMCU_INTERRUPT_TO_UC_EN_MASK_2
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN__SHIFT                        0x0
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN__SHIFT                        0x1
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN__SHIFT                        0x2
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN__SHIFT                        0x3
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN__SHIFT                        0x4
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN__SHIFT                        0x5
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x6
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x7
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x8
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x9
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0xa
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0xb
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN__SHIFT                                     0x10
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN__SHIFT                                     0x11
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN__SHIFT                                     0x12
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN__SHIFT                                     0x13
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN__SHIFT                                     0x14
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN__SHIFT                                     0x15
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN__SHIFT                                     0x16
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN_MASK                          0x00000001L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN_MASK                          0x00000002L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN_MASK                          0x00000004L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN_MASK                          0x00000008L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN_MASK                          0x00000010L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN_MASK                          0x00000020L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000040L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000080L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000100L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000200L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000400L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000800L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN_MASK                                       0x00010000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN_MASK                                       0x00020000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN_MASK                                       0x00040000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN_MASK                                       0x00080000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN_MASK                                       0x00100000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN_MASK                                       0x00200000L
>+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN_MASK                                       0x00400000L
>+
>+
>+// addressBlock: dce_dc_dmu_ihc_dispdec
>+//DC_GPU_TIMER_START_POSITION_V_UPDATE
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT                  0x0
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT                  0x4
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT                  0x8
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT                  0xc
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT                  0x10
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT                  0x14
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK                    0x00000007L
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK                    0x00000070L
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK                    0x00000700L
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK                    0x00007000L
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK                    0x00070000L
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK                    0x00700000L
>+//DC_GPU_TIMER_START_POSITION_VSTARTUP
>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT                  0x0
>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT                  0x4
>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT                  0x8
>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT                  0xc
>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT                  0x10
>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT                  0x14
>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK                    0x00000007L
>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK                    0x00000070L
>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK                    0x00000700L
>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK                    0x00007000L
>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK                    0x00070000L
>+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK                    0x00700000L
>+//DC_GPU_TIMER_READ
>+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT                                                           0x0
>+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK                                                             0xFFFFFFFFL
>+//DC_GPU_TIMER_READ_CNTL
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT                                               0x0
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT                               0x8
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT                               0xb
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT                               0xe
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT                               0x11
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT                               0x14
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT                               0x17
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK                                                 0x0000007FL
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK                                 0x00000700L
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK                                 0x00003800L
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK                                 0x0001C000L
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK                                 0x000E0000L
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK                                 0x00700000L
>+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK                                 0x03800000L
>+//DISP_INTERRUPT_STATUS
>+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT                                          0x1
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT                                             0x4
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                                0x5
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                                      0x6
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT                                                0x7
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT                                                0x8
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                            0x9
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                              0xa
>+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                                0xf
>+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                                    0x10
>+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT                                                       0x11
>+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT                                                    0x12
>+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT                                                  0x13
>+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT                                                  0x14
>+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT__SHIFT                                      0x16
>+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT                                            0x17
>+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT                                                0x18
>+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT                                                    0x1a
>+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT                                                            0x1b
>+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT                                                       0x1c
>+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT                                                       0x1d
>+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT                                                      0x1e
>+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT                                          0x1f
>+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK                                            0x00000002L
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK                                               0x00000010L
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                                  0x00000020L
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                                        0x00000040L
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK                                                  0x00000080L
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK                                                  0x00000100L
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK                                              0x00000200L
>+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                                0x00000400L
>+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                                  0x00008000L
>+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                                      0x00010000L
>+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK                                                         0x00020000L
>+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK                                                      0x00040000L
>+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK                                                    0x00080000L
>+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK                                                    0x00100000L
>+#define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_GENERITE_INTERRUPT_MASK                                        0x00400000L
>+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK                                              0x00800000L
>+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK                                                  0x01000000L
>+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK                                                      0x04000000L
>+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK                                                              0x08000000L
>+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK                                                         0x10000000L
>+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK                                                         0x20000000L
>+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK                                                        0x40000000L
>+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK                                            0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT                                 0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT                                    0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                       0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                             0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT                                       0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT                                       0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                   0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                     0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                       0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                           0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT                                              0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT                                           0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT                                         0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT                                         0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT                        0x19
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT                             0x1a
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT                      0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT                                   0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT                                   0x1d
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT                                   0x1e
>+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT                                0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK                                   0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK                                      0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                         0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                               0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK                                         0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK                                         0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK                                     0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                       0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                         0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                             0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK                                                0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK                                             0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK                                           0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK                                           0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK                          0x02000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK                               0x04000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK                        0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK                                     0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK                                     0x20000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK                                     0x40000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK                                  0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE2
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT                                             0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT                                          0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT                                        0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT                                        0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT                       0x19
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT                            0x1a
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT                     0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT                               0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK                                               0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK                                            0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK                                          0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK                                          0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK                         0x02000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK                              0x04000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK                       0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK                                 0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE3
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT                                             0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT                                          0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT                                        0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT                                        0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT__SHIFT                                0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x18
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT                       0x19
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT                            0x1a
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT                     0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT                               0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK                                               0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK                                            0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK                                          0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK                                          0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_HOST_CONFLICT_INTERRUPT_MASK                                  0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK                                  0x01000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK                         0x02000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK                              0x04000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK                       0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK                                 0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE4
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT                                             0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT                                          0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT                                        0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT                                        0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT                       0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT                            0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT                     0x18
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT                       0x19
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT                            0x1a
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT                     0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT                               0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK                                               0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK                                            0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK                                          0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK                                          0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK                         0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK                              0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK                       0x01000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK                         0x02000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK                              0x04000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK                       0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK                                 0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE5
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT                                             0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT                                          0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT                                        0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT                                        0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT                       0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT__SHIFT                            0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT                     0x18
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x19
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1a
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT                               0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK                                               0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK                                            0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK                                          0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK                                          0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK                         0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT_MASK                              0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK                       0x01000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK                                    0x02000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK                                    0x04000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK                                    0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK                                 0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE6
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT                                      0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT                                      0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT                                      0xb
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT                                      0xc
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT                                      0xd
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x15
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x18
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x19
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1a
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT                               0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK                                        0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK                                        0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK                                        0x00000800L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK                                        0x00001000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK                                        0x00002000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00200000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x01000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x02000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x04000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK                                 0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE7
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT                               0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK                                 0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE8
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT                               0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK                                 0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE9
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT__SHIFT                                0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_HOST_CONFLICT_INTERRUPT__SHIFT                                0x1d
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1e
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT                              0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_HOST_CONFLICT_INTERRUPT_MASK                                  0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK                                  0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_HOST_CONFLICT_INTERRUPT_MASK                                  0x20000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK                                  0x40000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK                                0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE10
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT                                0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT                                0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT                                0x2
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT                                0x3
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT                                0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT                                0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT                             0xc
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT                             0xd
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE__SHIFT                                 0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE__SHIFT                                 0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE__SHIFT                                 0x18
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE__SHIFT                                 0x19
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE__SHIFT                                 0x1a
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE__SHIFT                                 0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK                                  0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK                                  0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK                                  0x00000004L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK                                  0x00000008L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK                                  0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK                                  0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK                               0x00001000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK                               0x00002000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_RANGE_TIMING_UPDATE_MASK                                   0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_RANGE_TIMING_UPDATE_MASK                                   0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_RANGE_TIMING_UPDATE_MASK                                   0x01000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_RANGE_TIMING_UPDATE_MASK                                   0x02000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_RANGE_TIMING_UPDATE_MASK                                   0x04000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_RANGE_TIMING_UPDATE_MASK                                   0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE11
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT                                        0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT                                        0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT                                        0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT                                        0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT                                        0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT                                        0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT                                        0x15
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT                                        0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT                                    0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK                                          0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK                                          0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK                                          0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK                                          0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK                                          0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK                                          0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK                                          0x00200000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK                                          0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK                                      0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE12
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE13
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                            0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                            0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT                                0x2
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT                                 0x3
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT                          0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT                          0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT                          0xb
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT                          0xc
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT                          0xd
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT                          0xe
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT                          0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT                          0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                              0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                              0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK                                  0x00000004L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK                                   0x00000008L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK                            0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK                            0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK                            0x00000800L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK                            0x00001000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK                            0x00002000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK                            0x00004000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK                            0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK                            0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE14
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE15
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE16
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT                                   0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT                                    0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT                                   0xb
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT                                   0xc
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT                                    0xd
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT                                   0xe
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT                                   0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT                                    0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT                                   0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT                                   0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT                                    0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT                                   0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT                                   0x15
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT                                    0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT                                   0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x18
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x19
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1a
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK                                     0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK                                      0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK                                     0x00000800L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK                                     0x00001000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK                                      0x00002000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK                                     0x00004000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK                                     0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK                                      0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK                                     0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK                                     0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK                                      0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK                                     0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK                                     0x00200000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK                                      0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK                                     0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK                                    0x01000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK                                    0x02000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK                                    0x04000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK                                    0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK                                    0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE17
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT                                     0x2
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT                                     0x3
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT                                     0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT                                     0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT                                     0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT                                     0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT                                     0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT                                     0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                          0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                          0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x15
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x18
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x19
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1a
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK                                       0x00000004L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK                                       0x00000008L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK                                       0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK                                       0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK                                       0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK                                       0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK                                       0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK                                       0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                            0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                            0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00200000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x01000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x02000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x04000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE18
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_IHC_RXSENSE_INTERRUPT__SHIFT                                   0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT                            0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT                            0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT                            0xb
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT                            0xc
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT                            0xd
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT                            0xe
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT                            0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT                            0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT                        0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT                        0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT                        0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT                        0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT                        0x15
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT                        0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT                        0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT                        0x18
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_IHC_RXSENSE_INTERRUPT_MASK                                     0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK                              0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK                              0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK                              0x00000800L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK                              0x00001000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK                              0x00002000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK                              0x00004000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK                              0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK                              0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK                          0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK                          0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK                          0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK                          0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK                          0x00200000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK                          0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK                          0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK                          0x01000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE19
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x2
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x3
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT                           0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT                           0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT                           0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT                           0xb
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT                           0xc
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT                           0xd
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT                           0xe
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT                           0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT                          0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT                          0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT                          0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT                          0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT                          0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT                          0x15
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT                          0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT                          0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000004L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000008L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK                             0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK                             0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK                             0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK                             0x00000800L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK                             0x00001000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK                             0x00002000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK                             0x00004000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK                             0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK                            0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK                            0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK                            0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK                            0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK                            0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK                            0x00200000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK                            0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK                            0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE20
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x2
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x3
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xb
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xc
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xd
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xe
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x15
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT                                    0x18
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT                                    0x19
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT                                    0x1a
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT                                    0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT                                    0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT                                    0x1d
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000004L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000008L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000800L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00001000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00002000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00004000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00200000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK                                      0x01000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK                                      0x02000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK                                      0x04000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK                                      0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK                                      0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK                                      0x20000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE21
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT                          0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT                          0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT                          0x2
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT                          0x3
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT                          0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT                          0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT                        0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT                           0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT                           0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT                           0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT                           0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT                           0xb
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT                           0xc
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT                            0xd
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT__SHIFT                        0xe
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK                            0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK                            0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK                            0x00000004L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK                            0x00000008L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK                            0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK                            0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK                          0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK                             0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK                             0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK                             0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK                             0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK                             0x00000800L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK                             0x00001000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK                              0x00002000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__GENERIC_I2C_DDC_READ_REUEST_INTERRUPT_MASK                          0x00004000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE22
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT__SHIFT                          0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT__SHIFT                          0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT__SHIFT                         0x2
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT__SHIFT                         0x3
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT__SHIFT                         0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT__SHIFT                         0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT__SHIFT                         0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT__SHIFT                         0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT__SHIFT                        0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT__SHIFT                        0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT__SHIFT                       0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT__SHIFT                       0xb
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT__SHIFT                       0xc
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT__SHIFT                       0xd
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT__SHIFT                       0xe
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT__SHIFT                       0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT                                            0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT                                            0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT                                           0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x15
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x18
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_MASK                            0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_MASK                            0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_MASK                           0x00000004L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_MASK                           0x00000008L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_MASK                           0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_MASK                           0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_MASK                           0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_MASK                           0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_MASK                          0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_MASK                          0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_MASK                         0x00001000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_MASK                         0x00002000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_MASK                         0x00004000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_MASK                         0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK                                              0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK                                              0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK                                             0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00200000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x01000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK                               0x80000000L
>+//DC_GPU_TIMER_START_POSITION_VREADY
>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT                      0x0
>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT                      0x4
>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT                      0x8
>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT                      0xc
>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT                      0x10
>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT                      0x14
>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK                        0x00000007L
>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK                        0x00000070L
>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK                        0x00000700L
>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK                        0x00007000L
>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK                        0x00070000L
>+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK                        0x00700000L
>+//DC_GPU_TIMER_START_POSITION_FLIP
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT                          0x0
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT                          0x4
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT                          0x8
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT                          0xc
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT                          0x10
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT                          0x14
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT                          0x18
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT                          0x1c
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK                            0x00000007L
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK                            0x00000070L
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK                            0x00000700L
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK                            0x00007000L
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK                            0x00070000L
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK                            0x00700000L
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK                            0x07000000L
>+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK                            0x70000000L
>+//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT  0x0
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT  0x4
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT  0x8
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT  0xc
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT  0x10
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT  0x14
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK    0x00000007L
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK    0x00000070L
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK    0x00000700L
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK    0x00007000L
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK    0x00070000L
>+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK    0x00700000L
>+//DC_GPU_TIMER_START_POSITION_FLIP_AWAY
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT                0x0
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT                0x4
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT                0x8
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT                0xc
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT                0x10
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT                0x14
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT                0x18
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT                0x1c
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK                  0x00000007L
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK                  0x00000070L
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK                  0x00000700L
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK                  0x00007000L
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK                  0x00070000L
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK                  0x00700000L
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK                  0x07000000L
>+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK                  0x70000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE23
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT                         0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT                         0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT                         0x2
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT                         0x3
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT                         0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT                         0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT                       0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT                       0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT                       0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT                       0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT                       0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT                       0xb
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x15
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x18
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x19
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1a
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1b
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT                             0x1f
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK                           0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK                           0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK                           0x00000004L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK                           0x00000008L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK                           0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK                           0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK                         0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK                         0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK                         0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK                         0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00200000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x01000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x02000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x04000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x08000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK                               0x80000000L
>+//DISP_INTERRUPT_STATUS_CONTINUE24
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x0
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x1
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x2
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x3
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x4
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x5
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x6
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x7
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x8
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x9
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT                          0xc
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT                           0xd
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                    0xe
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                     0xf
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                     0x10
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                      0x11
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                   0x12
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                    0x13
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                    0x14
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                     0x15
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT                              0x16
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT                              0x17
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT                              0x18
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT                      0x19
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000001L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000002L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000004L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000008L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000010L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000020L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000040L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000080L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000100L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000200L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK                            0x00001000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK                             0x00002000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                      0x00004000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                       0x00008000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                       0x00010000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                        0x00020000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                     0x00040000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                      0x00080000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                      0x00100000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                       0x00200000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK                                0x00400000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK                                0x00800000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK                                0x01000000L
>+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK                        0x02000000L
>+//DCCG_INTERRUPT_DEST
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT                                        0x0
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT                                        0x1
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT                                        0x2
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT                                        0x3
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT                                        0x4
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT                                        0x5
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT                                 0xe
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT                                 0xf
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK                                          0x00000001L
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK                                          0x00000002L
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK                                          0x00000004L
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK                                          0x00000008L
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK                                          0x00000010L
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK                                          0x00000020L
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK                                   0x00004000L
>+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK                                   0x00008000L
>+//DMU_INTERRUPT_DEST
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT                                                  0x0
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT                                                  0x1
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT                                                  0x2
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT                                                  0x3
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT                                            0x4
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT                                             0x5
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT                                            0x6
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT                                             0x7
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT                                           0x8
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT                                            0x9
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT                                           0xa
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT                                            0xb
>+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
>+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST__SHIFT                                      0xe
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST__SHIFT                                      0xf
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST__SHIFT                                     0x10
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST__SHIFT                                      0x11
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST__SHIFT                                      0x12
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST__SHIFT                                     0x13
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT                                                  0x18
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT                                 0x19
>+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                          0x1a
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST__SHIFT                                      0x1b
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST__SHIFT                                                0x1c
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK                                                    0x00000001L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK                                                    0x00000002L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK                                                    0x00000004L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK                                                    0x00000008L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK                                              0x00000010L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK                                               0x00000020L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK                                              0x00000040L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK                                               0x00000080L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK                                             0x00000100L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK                                              0x00000200L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK                                             0x00000400L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK                                              0x00000800L
>+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
>+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST_MASK                                        0x00004000L
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST_MASK                                        0x00008000L
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST_MASK                                       0x00010000L
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST_MASK                                        0x00020000L
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST_MASK                                        0x00040000L
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST_MASK                                       0x00080000L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK                                                    0x01000000L
>+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK                                   0x02000000L
>+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                            0x04000000L
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST_MASK                                        0x08000000L
>+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST_MASK                                                  0x10000000L
>+//DCPG_INTERRUPT_DEST
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x0
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x1
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x2
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x3
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x4
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x5
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x6
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x7
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x8
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x9
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xa
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xb
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xc
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xd
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xe
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST__SHIFT                                 0xf
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x10
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x11
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x12
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x13
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x14
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x15
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x16
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x17
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x18
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x19
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1a
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1b
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1c
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1d
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1e
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST__SHIFT                               0x1f
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000001L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000002L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000004L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000008L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000010L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000020L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000040L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000080L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000100L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000200L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT_DEST_MASK                                   0x00000400L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT_DEST_MASK                                   0x00000800L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT_DEST_MASK                                   0x00001000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT_DEST_MASK                                   0x00002000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT_DEST_MASK                                   0x00004000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT_DEST_MASK                                   0x00008000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00010000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00020000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00040000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00080000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00100000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00200000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00400000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00800000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x01000000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x02000000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x04000000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x08000000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x10000000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x20000000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x40000000L
>+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT_DEST_MASK                                 0x80000000L
>+//DCPG_INTERRUPT_DEST2
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT                                0x0
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT                                0x1
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT                                0x2
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT                                0x3
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT                                0x4
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT                                0x5
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x6
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x7
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x8
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x9
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xa
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xb
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000001L
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000002L
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000004L
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000008L
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000010L
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000020L
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000040L
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000080L
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000100L
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000200L
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000400L
>+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000800L
>+//MMHUBBUB_INTERRUPT_DEST
>+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT                                        0x0
>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x1
>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x2
>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x3
>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x4
>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT                                       0x5
>+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                          0xc
>+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                          0xd
>+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK                                          0x00000001L
>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000002L
>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000004L
>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000008L
>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000010L
>+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK                                         0x00000020L
>+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                            0x00001000L
>+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                            0x00002000L
>+//WB_INTERRUPT_DEST
>+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT                                    0x0
>+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x1
>+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT                                    0x8
>+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x9
>+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_HOST_CONFLICT_INTERRUPT_DEST__SHIFT                                    0xa
>+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0xb
>+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xc
>+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xd
>+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xe
>+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xf
>+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0x10
>+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0x11
>+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK                                      0x00000001L
>+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000002L
>+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK                                      0x00000100L
>+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000200L
>+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_HOST_CONFLICT_INTERRUPT_DEST_MASK                                      0x00000400L
>+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000800L
>+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00001000L
>+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00002000L
>+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00004000L
>+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00008000L
>+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00010000L
>+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00020000L
>+//DCHUB_INTERRUPT_DEST
>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x0
>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1
>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x2
>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x3
>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x4
>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x5
>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x6
>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x7
>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x8
>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x9
>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xa
>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xb
>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0xc
>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0xd
>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xe
>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xf
>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x10
>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x11
>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x12
>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x13
>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x14
>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x15
>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x16
>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x17
>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x18
>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x19
>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1a
>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1b
>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x1c
>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1d
>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1e
>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1f
>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000001L
>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000002L
>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000004L
>+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000008L
>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000010L
>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000020L
>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000040L
>+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000080L
>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000100L
>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000200L
>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000400L
>+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000800L
>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00001000L
>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00002000L
>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00004000L
>+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00008000L
>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00010000L
>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00020000L
>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00040000L
>+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00080000L
>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00100000L
>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00200000L
>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00400000L
>+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00800000L
>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x01000000L
>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x02000000L
>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x04000000L
>+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x08000000L
>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x10000000L
>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x20000000L
>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x40000000L
>+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x80000000L
>+//DCHUB_PERFCOUNTER_INTERRUPT_DEST
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                   0xc
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                   0xd
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0xe
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0xf
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x10
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x11
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x12
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x13
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x14
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x15
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x16
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x17
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x18
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x19
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1a
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1b
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1c
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1d
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                     0x00001000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                     0x00002000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00004000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00008000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00010000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00020000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00040000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00080000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00100000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00200000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00400000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00800000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x01000000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x02000000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x04000000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x08000000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x10000000L
>+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x20000000L
>+//DCHUB_INTERRUPT_DEST2
>+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x0
>+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x1
>+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x2
>+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x3
>+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x4
>+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x5
>+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x6
>+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x7
>+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x8
>+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x9
>+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xa
>+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xb
>+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xc
>+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xd
>+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xe
>+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xf
>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT                                      0x18
>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                       0x19
>+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000001L
>+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000002L
>+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000004L
>+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000008L
>+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000010L
>+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000020L
>+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000040L
>+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000080L
>+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000100L
>+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000200L
>+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000400L
>+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000800L
>+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00001000L
>+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00002000L
>+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00004000L
>+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00008000L
>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK                                        0x01000000L
>+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                         0x02000000L
>+//DPP_PERFCOUNTER_INTERRUPT_DEST
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xc
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xd
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xe
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xf
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x10
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x11
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x12
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x13
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x14
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x15
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x16
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x17
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x18
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x19
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x1a
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x1b
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00001000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00002000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00004000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00008000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00010000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00020000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00040000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00080000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00100000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00200000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00400000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00800000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x01000000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x02000000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x04000000L
>+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x08000000L
>+//MPC_INTERRUPT_DEST
>+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT                                                 0x0
>+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT                                                 0x1
>+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT                                                 0x2
>+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT                                                 0x3
>+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT                                                 0x4
>+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT                                                 0x5
>+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT                                                 0x6
>+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT                                                 0x7
>+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
>+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
>+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK                                                   0x00000001L
>+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK                                                   0x00000002L
>+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK                                                   0x00000004L
>+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK                                                   0x00000008L
>+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK                                                   0x00000010L
>+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK                                                   0x00000020L
>+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK                                                   0x00000040L
>+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK                                                   0x00000080L
>+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
>+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
>+//OPP_INTERRUPT_DEST
>+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
>+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
>+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
>+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
>+//OPTC_INTERRUPT_DEST
>+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc
>+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd
>+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x18
>+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x19
>+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1a
>+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1b
>+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1c
>+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1d
>+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L
>+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L
>+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x01000000L
>+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x02000000L
>+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x04000000L
>+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x08000000L
>+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x10000000L
>+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x20000000L
>+//OTG0_INTERRUPT_DEST
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT                                      0x1
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT                          0xc
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT                               0xd
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT                        0xe
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK                                        0x00000002L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK                            0x00001000L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK                                 0x00002000L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK                          0x00004000L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
>+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
>+//OTG1_INTERRUPT_DEST
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT                                      0x1
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT                          0xc
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT                               0xd
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT                        0xe
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK                                        0x00000002L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK                            0x00001000L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK                                 0x00002000L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK                          0x00004000L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
>+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
>+//OTG2_INTERRUPT_DEST
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT                                      0x1
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT                          0xc
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT                               0xd
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT                        0xe
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK                                        0x00000002L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK                            0x00001000L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK                                 0x00002000L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK                          0x00004000L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
>+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
>+//OTG3_INTERRUPT_DEST
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT                                      0x1
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT                          0xc
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT                               0xd
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT                        0xe
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK                                        0x00000002L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK                            0x00001000L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK                                 0x00002000L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK                          0x00004000L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
>+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
>+//OTG4_INTERRUPT_DEST
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT                                      0x1
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT                          0xc
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT                               0xd
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT                        0xe
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK                                        0x00000002L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK                            0x00001000L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK                                 0x00002000L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK                          0x00004000L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
>+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
>+//OTG5_INTERRUPT_DEST
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_RANGE_TIMING_INTERRUPT_DEST__SHIFT                                      0x1
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST__SHIFT                          0xc
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST__SHIFT                               0xd
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST__SHIFT                        0xe
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_RANGE_TIMING_INTERRUPT_DEST_MASK                                        0x00000002L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_DEST_MASK                            0x00001000L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_INTERRUPT_DEST_MASK                                 0x00002000L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_DEST_MASK                          0x00004000L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
>+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
>+//DIG_INTERRUPT_DEST
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x0
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x1
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x2
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x3
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x4
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x5
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x6
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x7
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x8
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x9
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xa
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xb
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xc
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xd
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xe
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xf
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000001L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000002L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000004L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000008L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000010L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000020L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000040L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000080L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000100L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000200L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000400L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000800L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00001000L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00002000L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00004000L
>+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00008000L
>+//I2C_DDC_HPD_INTERRUPT_DEST
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT                                0x0
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT                           0x1
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT                           0x2
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT                           0x3
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT                           0x4
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT                           0x5
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT                           0x6
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT                         0x7
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x10
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x11
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x12
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x13
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x14
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x15
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT                          0x16
>+#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST__SHIFT                        0x17
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK                                  0x00000001L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK                             0x00000002L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK                             0x00000004L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK                             0x00000008L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK                             0x00000010L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK                             0x00000020L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK                             0x00000040L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK                           0x00000080L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00010000L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00020000L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00040000L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00080000L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00100000L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00200000L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK                            0x00400000L
>+#define I2C_DDC_HPD_INTERRUPT_DEST__GENERIC_I2C_DDC_READ_REQUEST_INTERRPUT_DEST_MASK                          0x00800000L
>+//DIO_INTERRUPT_DEST
>+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
>+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
>+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
>+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
>+//DCIO_INTERRUPT_DEST
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x0
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x1
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x2
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x3
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x4
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x5
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x6
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x10
>+#define DCIO_INTERRUPT_DEST__DCIO_IHC_RXSENSE_INTERRUPT_DEST__SHIFT                                           0x18
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000001L
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000002L
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000004L
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000008L
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000010L
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000020L
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000040L
>+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00010000L
>+#define DCIO_INTERRUPT_DEST__DCIO_IHC_RXSENSE_INTERRUPT_DEST_MASK                                             0x01000000L
>+//HPD_INTERRUPT_DEST
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT                                               0x0
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT                                               0x1
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT                                               0x2
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT                                               0x3
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT                                               0x4
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT                                               0x5
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT                                            0x8
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT                                            0x9
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT                                            0xa
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT                                            0xb
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT                                            0xc
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT                                            0xd
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_DACA_AUTODETECT_GENERATE_INTERRUPT_DEST__SHIFT                           0xe
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK                                                 0x00000001L
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK                                                 0x00000002L
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK                                                 0x00000004L
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK                                                 0x00000008L
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK                                                 0x00000010L
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK                                                 0x00000020L
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK                                              0x00000100L
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK                                              0x00000200L
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK                                              0x00000400L
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK                                              0x00000800L
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK                                              0x00001000L
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK                                              0x00002000L
>+#define HPD_INTERRUPT_DEST__DOUT_IHC_DACA_AUTODETECT_GENERATE_INTERRUPT_DEST_MASK                             0x00004000L
>+//AZ_INTERRUPT_DEST
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x0
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x1
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x2
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x3
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x4
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x5
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x6
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x7
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x8
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x9
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xa
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xb
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xc
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xd
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xe
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xf
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x10
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x11
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x12
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x13
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x14
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x15
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x16
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x17
>+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                      0x1e
>+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                      0x1f
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000001L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000002L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000004L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000008L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000010L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000020L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000040L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000080L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000100L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000200L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000400L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000800L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK                                       0x00001000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK                                       0x00002000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK                                       0x00004000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK                                       0x00008000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK                                      0x00010000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK                                      0x00020000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK                                      0x00040000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK                                      0x00080000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK                                      0x00100000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK                                      0x00200000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK                                      0x00400000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK                                      0x00800000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                        0x40000000L
>+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                        0x80000000L
>+//AUX_INTERRUPT_DEST
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x0
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x1
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x2
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x3
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x4
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x5
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x6
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x7
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x8
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x9
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT                                       0xa
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT                                       0xb
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x10
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x11
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x12
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x13
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x14
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x15
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x16
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x17
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x18
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x19
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x1a
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x1b
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000001L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000002L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000004L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000008L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000010L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000020L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000040L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000080L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000100L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000200L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000400L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000800L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00010000L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00020000L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00040000L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00080000L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00100000L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00200000L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00400000L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00800000L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x01000000L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x02000000L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x04000000L
>+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x08000000L
>+//DSC_INTERRUPT_DEST
>+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x0
>+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x1
>+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x2
>+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x3
>+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x4
>+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x5
>+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x6
>+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x7
>+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x8
>+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x9
>+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xa
>+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xb
>+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0xc
>+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0xd
>+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xe
>+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xf
>+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x10
>+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x11
>+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x12
>+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x13
>+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x14
>+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x15
>+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x16
>+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x17
>+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000001L
>+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000002L
>+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000004L
>+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000008L
>+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000010L
>+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000020L
>+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000040L
>+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000080L
>+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000100L
>+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000200L
>+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000400L
>+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000800L
>+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00001000L
>+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00002000L
>+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00004000L
>+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00008000L
>+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00010000L
>+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00020000L
>+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00040000L
>+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00080000L
>+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00100000L
>+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00200000L
>+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00400000L
>+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00800000L
>+
>+
>+// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec
>+//WB_ENABLE
>+#define WB_ENABLE__WB_ENABLE__SHIFT                                                                           0x0
>+#define WB_ENABLE__WB_ENABLE_MASK                                                                             0x00000001L
>+//WB_EC_CONFIG
>+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS__SHIFT                                                            0x0
>+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS__SHIFT                                                            0x1
>+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS__SHIFT                                                         0x2
>+#define WB_EC_CONFIG__WB_TEST_CLK_SEL__SHIFT                                                                  0x3
>+#define WB_EC_CONFIG__WB_LB_LS_DIS__SHIFT                                                                     0x7
>+#define WB_EC_CONFIG__WB_LB_SD_DIS__SHIFT                                                                     0x8
>+#define WB_EC_CONFIG__WB_LUT_LS_DIS__SHIFT                                                                    0x9
>+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL__SHIFT                                                        0xc
>+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS__SHIFT                                                             0xe
>+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE__SHIFT                                                           0xf
>+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE__SHIFT                                                           0x15
>+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE__SHIFT                                                              0x17
>+#define WB_EC_CONFIG__WBSCL_LUT_MEM_PWR_STATE__SHIFT                                                          0x18
>+#define WB_EC_CONFIG__DISPCLK_R_WB_GATE_DIS_MASK                                                              0x00000001L
>+#define WB_EC_CONFIG__DISPCLK_G_WB_GATE_DIS_MASK                                                              0x00000002L
>+#define WB_EC_CONFIG__DISPCLK_G_WBSCL_GATE_DIS_MASK                                                           0x00000004L
>+#define WB_EC_CONFIG__WB_TEST_CLK_SEL_MASK                                                                    0x00000078L
>+#define WB_EC_CONFIG__WB_LB_LS_DIS_MASK                                                                       0x00000080L
>+#define WB_EC_CONFIG__WB_LB_SD_DIS_MASK                                                                       0x00000100L
>+#define WB_EC_CONFIG__WB_LUT_LS_DIS_MASK                                                                      0x00000200L
>+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK                                                          0x00003000L
>+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_DIS_MASK                                                               0x00004000L
>+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_FORCE_MASK                                                             0x00018000L
>+#define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_STATE_MASK                                                             0x00600000L
>+#define WB_EC_CONFIG__WB_RAM_PW_SAVE_MODE_MASK                                                                0x00800000L
>+#define WB_EC_CONFIG__WBSCL_LUT_MEM_PWR_STATE_MASK                                                            0x03000000L
>+//CNV_MODE
>+#define CNV_MODE__CNV_OUT_BPC__SHIFT                                                                          0x4
>+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE__SHIFT                                                               0x8
>+#define CNV_MODE__CNV_WINDOW_CROP_EN__SHIFT                                                                   0xc
>+#define CNV_MODE__CNV_STEREO_TYPE__SHIFT                                                                      0xd
>+#define CNV_MODE__CNV_INTERLACED_MODE__SHIFT                                                                  0xf
>+#define CNV_MODE__CNV_EYE_SELECTION__SHIFT                                                                    0x10
>+#define CNV_MODE__CNV_STEREO_POLARITY__SHIFT                                                                  0x12
>+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER__SHIFT                                                           0x13
>+#define CNV_MODE__CNV_STEREO_SPLIT__SHIFT                                                                     0x14
>+#define CNV_MODE__CNV_NEW_CONTENT__SHIFT                                                                      0x18
>+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_CURRENT__SHIFT                                                         0x1e
>+#define CNV_MODE__CNV_FRAME_CAPTURE_EN__SHIFT                                                                 0x1f
>+#define CNV_MODE__CNV_OUT_BPC_MASK                                                                            0x00000010L
>+#define CNV_MODE__CNV_FRAME_CAPTURE_RATE_MASK                                                                 0x00000300L
>+#define CNV_MODE__CNV_WINDOW_CROP_EN_MASK                                                                     0x00001000L
>+#define CNV_MODE__CNV_STEREO_TYPE_MASK                                                                        0x00006000L
>+#define CNV_MODE__CNV_INTERLACED_MODE_MASK                                                                    0x00008000L
>+#define CNV_MODE__CNV_EYE_SELECTION_MASK                                                                      0x00030000L
>+#define CNV_MODE__CNV_STEREO_POLARITY_MASK                                                                    0x00040000L
>+#define CNV_MODE__CNV_INTERLACED_FIELD_ORDER_MASK                                                             0x00080000L
>+#define CNV_MODE__CNV_STEREO_SPLIT_MASK                                                                       0x00100000L
>+#define CNV_MODE__CNV_NEW_CONTENT_MASK                                                                        0x01000000L
>+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_CURRENT_MASK                                                           0x40000000L
>+#define CNV_MODE__CNV_FRAME_CAPTURE_EN_MASK                                                                   0x80000000L
>+//CNV_WINDOW_START
>+#define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT                                                           0x0
>+#define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT                                                           0x10
>+#define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK                                                             0x00000FFFL
>+#define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK                                                             0x0FFF0000L
>+//CNV_WINDOW_SIZE
>+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT                                                              0x0
>+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT                                                             0x10
>+#define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK                                                                0x00000FFFL
>+#define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK                                                               0x0FFF0000L
>+//CNV_UPDATE
>+#define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT                                                                 0x0
>+#define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT                                                                   0x8
>+#define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT                                                                    0x10
>+#define CNV_UPDATE__CNV_UPDATE_PENDING_MASK                                                                   0x00000001L
>+#define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK                                                                     0x00000100L
>+#define CNV_UPDATE__CNV_UPDATE_LOCK_MASK                                                                      0x00010000L
>+//CNV_SOURCE_SIZE
>+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT                                                              0x0
>+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT                                                             0x10
>+#define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK                                                                0x00007FFFL
>+#define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK                                                               0x7FFF0000L
>+//CNV_TEST_CNTL
>+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT                                                                 0x4
>+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT                                                            0x8
>+#define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK                                                                   0x00000010L
>+#define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK                                                              0x00000100L
>+//CNV_TEST_CRC_RED
>+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT                                                        0x4
>+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT                                                         0x10
>+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK                                                          0x0000FFF0L
>+#define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK                                                           0xFFFF0000L
>+//CNV_TEST_CRC_GREEN
>+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT                                                    0x4
>+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT                                                     0x10
>+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK                                                      0x0000FFF0L
>+#define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK                                                       0xFFFF0000L
>+//CNV_TEST_CRC_BLUE
>+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT                                                      0x4
>+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT                                                       0x10
>+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK                                                        0x0000FFF0L
>+#define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK                                                         0xFFFF0000L
>+//WB_DEBUG_CTRL
>+#define WB_DEBUG_CTRL__WB_DEBUG_EN__SHIFT                                                                     0x0
>+#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT                                                                    0x6
>+#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK                                                                       0x00000001L
>+#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK                                                                      0x000000C0L
>+//WB_DBG_MODE
>+#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT                                                                    0x0
>+#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT                                                                    0x1
>+#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT                                                                     0x2
>+#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT                                                                       0x3
>+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT                                                              0x8
>+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT                                                               0x10
>+#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK                                                                      0x00000001L
>+#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK                                                                      0x00000002L
>+#define WB_DBG_MODE__WB_DBG_36MODE_MASK                                                                       0x00000004L
>+#define WB_DBG_MODE__WB_DBG_CMAP_MASK                                                                         0x00000008L
>+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK                                                                0x00000100L
>+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK                                                                 0x7FFF0000L
>+//WB_HW_DEBUG
>+#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT                                                                       0x0
>+#define WB_HW_DEBUG__WB_HW_DEBUG_MASK                                                                         0xFFFFFFFFL
>+//WB_SOFT_RESET
>+#define WB_SOFT_RESET__WB_SOFT_RESET__SHIFT                                                                   0x0
>+#define WB_SOFT_RESET__WB_SOFT_RESET_MASK                                                                     0x00000001L
>+//WB_WARM_UP_MODE_CTL1
>+#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP__SHIFT                                                             0x0
>+#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP__SHIFT                                                            0x10
>+#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE__SHIFT                                                       0x1f
>+#define WB_WARM_UP_MODE_CTL1__WIDTH_WARMUP_MASK                                                               0x00007FFFL
>+#define WB_WARM_UP_MODE_CTL1__HEIGHT_WARMUP_MASK                                                              0x7FFF0000L
>+#define WB_WARM_UP_MODE_CTL1__GMC_WARM_UP_ENABLE_MASK                                                         0x80000000L
>+//WB_WARM_UP_MODE_CTL2
>+#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP__SHIFT                                                        0x0
>+#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP__SHIFT                                                              0x10
>+#define WB_WARM_UP_MODE_CTL2__DATA_DEPTH_WARMUP__SHIFT                                                        0x14
>+#define WB_WARM_UP_MODE_CTL2__DATA_VALUE_WARMUP_MASK                                                          0x000003FFL
>+#define WB_WARM_UP_MODE_CTL2__MODE_WARMUP_MASK                                                                0x00010000L
>+#define WB_WARM_UP_MODE_CTL2__DATA_DEPTH_WARMUP_MASK                                                          0x00100000L
>+//CNV_TEST_DEBUG_INDEX
>+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT                                                     0x0
>+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT                                                  0x8
>+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK                                                       0x000000FFL
>+#define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK                                                    0x00000100L
>+//CNV_TEST_DEBUG_DATA
>+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT                                                       0x0
>+#define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec
>+//WBSCL_COEF_RAM_SELECT
>+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                             0x0
>+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE__SHIFT                                                    0x8
>+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE__SHIFT                                              0x10
>+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_TAP_PAIR_IDX_MASK                                               0x00000007L
>+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_PHASE_MASK                                                      0x00000F00L
>+#define WBSCL_COEF_RAM_SELECT__WBSCL_COEF_RAM_FILTER_TYPE_MASK                                                0x00030000L
>+//WBSCL_COEF_RAM_TAP_DATA
>+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                          0x0
>+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                       0xf
>+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                           0x10
>+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                        0x1f
>+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_MASK                                            0x00003FFFL
>+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                         0x00008000L
>+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_MASK                                             0x3FFF0000L
>+#define WBSCL_COEF_RAM_TAP_DATA__WBSCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                          0x80000000L
>+//WBSCL_MODE
>+#define WBSCL_MODE__WBSCL_MODE__SHIFT                                                                         0x0
>+#define WBSCL_MODE__WBSCL_OUT_BIT_DEPTH__SHIFT                                                                0x4
>+#define WBSCL_MODE__WBSCL_MODE_MASK                                                                           0x00000003L
>+#define WBSCL_MODE__WBSCL_OUT_BIT_DEPTH_MASK                                                                  0x00000010L
>+//WBSCL_TAP_CONTROL
>+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB__SHIFT                                                   0x0
>+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR__SHIFT                                                    0x4
>+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB__SHIFT                                                   0x8
>+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR__SHIFT                                                    0xc
>+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_Y_RGB_MASK                                                     0x0000000FL
>+#define WBSCL_TAP_CONTROL__WBSCL_V_NUM_OF_TAPS_CBCR_MASK                                                      0x000000F0L
>+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_Y_RGB_MASK                                                     0x00000F00L
>+#define WBSCL_TAP_CONTROL__WBSCL_H_NUM_OF_TAPS_CBCR_MASK                                                      0x0000F000L
>+//WBSCL_DEST_SIZE
>+#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT__SHIFT                                                             0x0
>+#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH__SHIFT                                                              0x10
>+#define WBSCL_DEST_SIZE__WBSCL_DEST_HEIGHT_MASK                                                               0x00007FFFL
>+#define WBSCL_DEST_SIZE__WBSCL_DEST_WIDTH_MASK                                                                0x7FFF0000L
>+//WBSCL_HORZ_FILTER_SCALE_RATIO
>+#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO__SHIFT                                             0x0
>+#define WBSCL_HORZ_FILTER_SCALE_RATIO__WBSCL_H_SCALE_RATIO_MASK                                               0x07FFFFFFL
>+//WBSCL_HORZ_FILTER_INIT_Y_RGB
>+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB__SHIFT                                          0x0
>+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB__SHIFT                                           0x18
>+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_FRAC_Y_RGB_MASK                                            0x00FFFFFFL
>+#define WBSCL_HORZ_FILTER_INIT_Y_RGB__WBSCL_H_INIT_INT_Y_RGB_MASK                                             0x1F000000L
>+//WBSCL_HORZ_FILTER_INIT_CBCR
>+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR__SHIFT                                            0x0
>+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR__SHIFT                                             0x18
>+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_FRAC_CBCR_MASK                                              0x00FFFFFFL
>+#define WBSCL_HORZ_FILTER_INIT_CBCR__WBSCL_H_INIT_INT_CBCR_MASK                                               0x1F000000L
>+//WBSCL_VERT_FILTER_SCALE_RATIO
>+#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO__SHIFT                                             0x0
>+#define WBSCL_VERT_FILTER_SCALE_RATIO__WBSCL_V_SCALE_RATIO_MASK                                               0x07FFFFFFL
>+//WBSCL_VERT_FILTER_INIT_Y_RGB
>+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB__SHIFT                                          0x0
>+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB__SHIFT                                           0x18
>+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_FRAC_Y_RGB_MASK                                            0x00FFFFFFL
>+#define WBSCL_VERT_FILTER_INIT_Y_RGB__WBSCL_V_INIT_INT_Y_RGB_MASK                                             0x1F000000L
>+//WBSCL_VERT_FILTER_INIT_CBCR
>+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR__SHIFT                                            0x0
>+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR__SHIFT                                             0x18
>+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_FRAC_CBCR_MASK                                              0x00FFFFFFL
>+#define WBSCL_VERT_FILTER_INIT_CBCR__WBSCL_V_INIT_INT_CBCR_MASK                                               0x1F000000L
>+//WBSCL_ROUND_OFFSET
>+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB__SHIFT                                                   0x0
>+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR__SHIFT                                                    0x10
>+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_Y_RGB_MASK                                                     0x000003FFL
>+#define WBSCL_ROUND_OFFSET__WBSCL_ROUND_OFFSET_CBCR_MASK                                                      0x03FF0000L
>+//WBSCL_OVERFLOW_STATUS
>+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG__SHIFT                                                0x0
>+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK__SHIFT                                                 0x8
>+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK__SHIFT                                                0xc
>+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS__SHIFT                                          0x10
>+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE__SHIFT                                            0x14
>+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_FLAG_MASK                                                  0x00000001L
>+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_ACK_MASK                                                   0x00000100L
>+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_MASK_MASK                                                  0x00001000L
>+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_STATUS_MASK                                            0x00010000L
>+#define WBSCL_OVERFLOW_STATUS__WBSCL_DATA_OVERFLOW_INT_TYPE_MASK                                              0x00100000L
>+//WBSCL_COEF_RAM_CONFLICT_STATUS
>+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG__SHIFT                                       0x0
>+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK__SHIFT                                        0x8
>+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK__SHIFT                                       0xc
>+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS__SHIFT                                 0x10
>+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE__SHIFT                                   0x14
>+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_FLAG_MASK                                         0x00000001L
>+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_ACK_MASK                                          0x00000100L
>+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_MASK_MASK                                         0x00001000L
>+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_STATUS_MASK                                   0x00010000L
>+#define WBSCL_COEF_RAM_CONFLICT_STATUS__WBSCL_HOST_CONFLICT_INT_TYPE_MASK                                     0x00100000L
>+//WBSCL_TEST_CNTL
>+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN__SHIFT                                                             0x4
>+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN__SHIFT                                                        0x8
>+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_EN_MASK                                                               0x00000010L
>+#define WBSCL_TEST_CNTL__WBSCL_TEST_CRC_CONT_EN_MASK                                                          0x00000100L
>+//WBSCL_TEST_CRC_RED
>+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK__SHIFT                                                    0x0
>+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED__SHIFT                                                     0x10
>+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_RED_MASK_MASK                                                      0x000003FFL
>+#define WBSCL_TEST_CRC_RED__WBSCL_TEST_CRC_SIG_RED_MASK                                                       0xFFFF0000L
>+//WBSCL_TEST_CRC_GREEN
>+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK__SHIFT                                                0x0
>+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN__SHIFT                                                 0x10
>+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_GREEN_MASK_MASK                                                  0x0000FFFFL
>+#define WBSCL_TEST_CRC_GREEN__WBSCL_TEST_CRC_SIG_GREEN_MASK                                                   0xFFFF0000L
>+//WBSCL_TEST_CRC_BLUE
>+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK__SHIFT                                                  0x0
>+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE__SHIFT                                                   0x10
>+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_BLUE_MASK_MASK                                                    0x000003FFL
>+#define WBSCL_TEST_CRC_BLUE__WBSCL_TEST_CRC_SIG_BLUE_MASK                                                     0xFFFF0000L
>+//WBSCL_BACKPRESSURE_CNT_EN
>+#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN__SHIFT                                           0x0
>+#define WBSCL_BACKPRESSURE_CNT_EN__WBSCL_BACKPRESSURE_CNT_EN_MASK                                             0x00000001L
>+//WB_MCIF_BACKPRESSURE_CNT
>+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE__SHIFT                                           0x0
>+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE__SHIFT                                           0x10
>+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_Y_MAX_BACKPRESSURE_MASK                                             0x0000FFFFL
>+#define WB_MCIF_BACKPRESSURE_CNT__WB_MCIF_C_MAX_BACKPRESSURE_MASK                                             0xFFFF0000L
>+//WBSCL_CLAMP_Y_RGB
>+#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_UPPER_Y_RGB__SHIFT                                                     0x0
>+#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_LOWER_Y_RGB__SHIFT                                                     0x10
>+#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_UPPER_Y_RGB_MASK                                                       0x000003FFL
>+#define WBSCL_CLAMP_Y_RGB__WBSCL_CLAMP_LOWER_Y_RGB_MASK                                                       0x03FF0000L
>+//WBSCL_CLAMP_CBCR
>+#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_UPPER_CBCR__SHIFT                                                       0x0
>+#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_LOWER_CBCR__SHIFT                                                       0x10
>+#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_UPPER_CBCR_MASK                                                         0x000003FFL
>+#define WBSCL_CLAMP_CBCR__WBSCL_CLAMP_LOWER_CBCR_MASK                                                         0x03FF0000L
>+//WBSCL_OUTSIDE_PIX_STRATEGY
>+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY__SHIFT                                         0x0
>+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y__SHIFT                                              0x10
>+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_OUTSIDE_PIX_STRATEGY_MASK                                           0x00000001L
>+#define WBSCL_OUTSIDE_PIX_STRATEGY__WBSCL_BLACK_COLOR_G_Y_MASK                                                0x03FF0000L
>+//WBSCL_OUTSIDE_PIX_STRATEGY_CBCR
>+#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_B_CB__SHIFT                                        0x0
>+#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_R_CR__SHIFT                                        0x10
>+#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_B_CB_MASK                                          0x000003FFL
>+#define WBSCL_OUTSIDE_PIX_STRATEGY_CBCR__WBSCL_BLACK_COLOR_R_CR_MASK                                          0x03FF0000L
>+//WBSCL_DEBUG
>+#define WBSCL_DEBUG__WBSCL_DEBUG__SHIFT                                                                       0x0
>+#define WBSCL_DEBUG__WBSCL_DEBUG_MASK                                                                         0xFFFFFFFFL
>+//WBSCL_TEST_DEBUG_INDEX
>+#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_INDEX__SHIFT                                                 0x0
>+#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_WRITE_EN__SHIFT                                              0x8
>+#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_INDEX_MASK                                                   0x000000FFL
>+#define WBSCL_TEST_DEBUG_INDEX__WBSCL_TEST_DEBUG_WRITE_EN_MASK                                                0x00000100L
>+//WBSCL_TEST_DEBUG_DATA
>+#define WBSCL_TEST_DEBUG_DATA__WBSCL_TEST_DEBUG_DATA__SHIFT                                                   0x0
>+#define WBSCL_TEST_DEBUG_DATA__WBSCL_TEST_DEBUG_DATA_MASK                                                     0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON3_PERFCOUNTER_CNTL
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
>+//DC_PERFMON3_PERFCOUNTER_CNTL2
>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
>+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
>+//DC_PERFMON3_PERFCOUNTER_STATE
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
>+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
>+//DC_PERFMON3_PERFMON_CNTL
>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
>+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
>+//DC_PERFMON3_PERFMON_CNTL2
>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
>+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
>+//DC_PERFMON3_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
>+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
>+//DC_PERFMON3_PERFMON_CVALUE_LOW
>+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
>+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
>+//DC_PERFMON3_PERFMON_HI
>+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
>+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
>+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
>+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
>+//DC_PERFMON3_PERFMON_LOW
>+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
>+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
>+//MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                      0x0
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT                                   0x1
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                   0x4
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                  0x5
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                             0x6
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                           0x7
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                     0x8
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT                                             0x10
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                  0x18
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                        0x00000001L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK                                     0x00000002L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                     0x00000010L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                    0x00000020L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                               0x00000040L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                             0x00000080L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                       0x00000F00L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK                                               0x000F0000L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                    0x01000000L
>+//MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R
>+#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT                                  0x0
>+#define MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK                                    0x00001FFFL
>+//MCIF_WB0_MCIF_WB_BUFMGR_STATUS
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                  0x0
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                   0x1
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                           0x2
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                         0x4
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                    0x7
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                          0x8
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                      0xc
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                        0x1c
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                    0x00000001L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                     0x00000002L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                             0x00000004L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                           0x00000070L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                      0x00000080L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                            0x00000F00L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                        0x01FFF000L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                          0x70000000L
>+//MCIF_WB0_MCIF_WB_BUF_PITCH
>+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                             0x8
>+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                           0x18
>+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                               0x0000FF00L
>+#define MCIF_WB0_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                             0xFF000000L
>+//MCIF_WB0_MCIF_WB_BUF_1_STATUS
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                            0x0
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                         0x1
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                        0x2
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                          0x3
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                           0x4
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                              0x5
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                            0x8
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                           0xc
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT                                             0xf
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                        0x10
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT                                   0x1d
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT                                  0x1e
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT                                0x1f
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                              0x00000001L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                           0x00000002L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                          0x00000004L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                            0x00000008L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                             0x00000010L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                0x000000E0L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                              0x00000F00L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                             0x00007000L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK                                               0x00008000L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                          0x1FFF0000L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK                                     0x20000000L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK                                    0x40000000L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
>+//MCIF_WB0_MCIF_WB_BUF_1_STATUS2
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT                                       0x0
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                      0xd
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                      0xe
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                  0xf
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                              0x10
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                        0x11
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                        0x12
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                         0x13
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK                                         0x00001FFFL
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                        0x00002000L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                        0x00004000L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                0x00010000L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                          0x00020000L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                          0x00040000L
>+#define MCIF_WB0_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                           0x00080000L
>+//MCIF_WB0_MCIF_WB_BUF_2_STATUS
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                            0x0
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                         0x1
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                        0x2
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                          0x3
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                           0x4
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                              0x5
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                            0x8
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                           0xc
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT                                             0xf
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                        0x10
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT                                   0x1d
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT                                  0x1e
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT                                0x1f
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                              0x00000001L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                           0x00000002L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                          0x00000004L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                            0x00000008L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                             0x00000010L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                0x000000E0L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                              0x00000F00L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                             0x00007000L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK                                               0x00008000L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                          0x1FFF0000L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK                                     0x20000000L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK                                    0x40000000L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
>+//MCIF_WB0_MCIF_WB_BUF_2_STATUS2
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT                                       0x0
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                      0xd
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                      0xe
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                  0xf
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                              0x10
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                        0x11
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                        0x12
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                         0x13
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK                                         0x00001FFFL
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                        0x00002000L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                        0x00004000L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                0x00010000L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                          0x00020000L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                          0x00040000L
>+#define MCIF_WB0_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                           0x00080000L
>+//MCIF_WB0_MCIF_WB_BUF_3_STATUS
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                            0x0
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                         0x1
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                        0x2
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                          0x3
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                           0x4
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                              0x5
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                            0x8
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                           0xc
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT                                             0xf
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                        0x10
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT                                   0x1d
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT                                  0x1e
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT                                0x1f
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                              0x00000001L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                           0x00000002L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                          0x00000004L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                            0x00000008L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                             0x00000010L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                0x000000E0L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                              0x00000F00L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                             0x00007000L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK                                               0x00008000L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                          0x1FFF0000L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK                                     0x20000000L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK                                    0x40000000L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
>+//MCIF_WB0_MCIF_WB_BUF_3_STATUS2
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT                                       0x0
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                      0xd
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                      0xe
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                  0xf
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                              0x10
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                        0x11
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                        0x12
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                         0x13
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK                                         0x00001FFFL
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                        0x00002000L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                        0x00004000L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                0x00010000L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                          0x00020000L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                          0x00040000L
>+#define MCIF_WB0_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                           0x00080000L
>+//MCIF_WB0_MCIF_WB_BUF_4_STATUS
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                            0x0
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                         0x1
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                        0x2
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                          0x3
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                           0x4
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                              0x5
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                            0x8
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                           0xc
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT                                             0xf
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                        0x10
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT                                   0x1d
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT                                  0x1e
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT                                0x1f
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                              0x00000001L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                           0x00000002L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                          0x00000004L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                            0x00000008L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                             0x00000010L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                0x000000E0L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                              0x00000F00L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                             0x00007000L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK                                               0x00008000L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                          0x1FFF0000L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK                                     0x20000000L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK                                    0x40000000L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
>+//MCIF_WB0_MCIF_WB_BUF_4_STATUS2
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT                                       0x0
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                      0xd
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                      0xe
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                  0xf
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                              0x10
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                        0x11
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                        0x12
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                         0x13
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK                                         0x00001FFFL
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                        0x00002000L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                        0x00004000L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                0x00010000L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                          0x00020000L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                          0x00040000L
>+#define MCIF_WB0_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                           0x00080000L
>+//MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL
>+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                         0x0
>+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                   0x16
>+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                           0x00000003L
>+#define MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                     0xFFC00000L
>+//MCIF_WB0_MCIF_WB_SCLK_CHANGE
>+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                           0x0
>+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                       0x1
>+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                             0x00000001L
>+#define MCIF_WB0_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK                                         0x0000000EL
>+//MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX
>+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT                                    0x0
>+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT                                 0x8
>+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK                                      0x000000FFL
>+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK                                   0x00000100L
>+//MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA
>+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT                                      0x0
>+#define MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK                                        0xFFFFFFFFL
>+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y
>+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                            0x0
>+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                              0xFFFFFFFFL
>+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET
>+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT                              0x0
>+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C
>+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                            0x0
>+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                              0xFFFFFFFFL
>+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET
>+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT                              0x0
>+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y
>+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                            0x0
>+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                              0xFFFFFFFFL
>+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET
>+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT                              0x0
>+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C
>+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                            0x0
>+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                              0xFFFFFFFFL
>+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET
>+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT                              0x0
>+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y
>+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                            0x0
>+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                              0xFFFFFFFFL
>+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET
>+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT                              0x0
>+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C
>+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                            0x0
>+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                              0xFFFFFFFFL
>+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET
>+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT                              0x0
>+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y
>+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                            0x0
>+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                              0xFFFFFFFFL
>+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET
>+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT                              0x0
>+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C
>+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                            0x0
>+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                              0xFFFFFFFFL
>+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET
>+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT                              0x0
>+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL
>+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                            0x0
>+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                 0x4
>+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                0x5
>+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                           0x6
>+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                   0x8
>+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                 0x10
>+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                              0x00000001L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                   0x00000010L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                  0x00000020L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                             0x00000040L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                     0x00000F00L
>+#define MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                   0x1FFF0000L
>+//MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
>+#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT               0x0
>+#define MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                 0x0007FFFFL
>+//MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL
>+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT                     0x0
>+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                  0x1
>+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT                                 0x2
>+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                            0x4
>+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK                       0x00000001L
>+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                    0x00000002L
>+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK                                   0x00000004L
>+#define MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                              0x00000070L
>+//MCIF_WB0_MCIF_WB_WATERMARK
>+#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                              0x0
>+#define MCIF_WB0_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                0x0000FFFFL
>+//MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL
>+#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                         0x0
>+#define MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                           0x00000001L
>+//MCIF_WB0_MCIF_WB_WARM_UP_CNTL
>+#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT                                       0x8
>+#define MCIF_WB0_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK                                         0x0000FF00L
>+//MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL
>+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT                                0x0
>+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                   0x1
>+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK                                  0x00000001L
>+#define MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                     0x00000002L
>+//MCIF_WB0_MULTI_LEVEL_QOS_CTRL
>+#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                       0x0
>+#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                         0x003FFFFFL
>+//MCIF_WB0_MCIF_WB_SECURITY_LEVEL
>+#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT                                        0x0
>+#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK                                          0x00000007L
>+//MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE
>+#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                          0x0
>+#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                            0x000FFFFFL
>+//MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE
>+#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                      0x0
>+#define MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                        0x000FFFFFL
>+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH
>+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                  0x0
>+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH
>+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                  0x0
>+#define MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH
>+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                  0x0
>+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH
>+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                  0x0
>+#define MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH
>+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                  0x0
>+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH
>+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                  0x0
>+#define MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH
>+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                  0x0
>+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH
>+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                  0x0
>+#define MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION
>+#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                              0x0
>+#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                             0x10
>+#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                0x00001FFFL
>+#define MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
>+//MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION
>+#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                              0x0
>+#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                             0x10
>+#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                0x00001FFFL
>+#define MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
>+//MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION
>+#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                              0x0
>+#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                             0x10
>+#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                0x00001FFFL
>+#define MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
>+//MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION
>+#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                              0x0
>+#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                             0x10
>+#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                0x00001FFFL
>+#define MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
>+
>+
>+// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec
>+//MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                      0x0
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT                                   0x1
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                   0x4
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                  0x5
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                             0x6
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                           0x7
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                     0x8
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT                                             0x10
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                  0x18
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                        0x00000001L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK                                     0x00000002L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                     0x00000010L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                    0x00000020L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                               0x00000040L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                             0x00000080L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                       0x00000F00L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK                                               0x000F0000L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                    0x01000000L
>+//MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R
>+#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT                                  0x0
>+#define MCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK                                    0x00001FFFL
>+//MCIF_WB1_MCIF_WB_BUFMGR_STATUS
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                  0x0
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                   0x1
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                           0x2
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                         0x4
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                    0x7
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                          0x8
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                      0xc
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                        0x1c
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                    0x00000001L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                     0x00000002L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                             0x00000004L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                           0x00000070L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                      0x00000080L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                            0x00000F00L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                        0x01FFF000L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                          0x70000000L
>+//MCIF_WB1_MCIF_WB_BUF_PITCH
>+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                             0x8
>+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                           0x18
>+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                               0x0000FF00L
>+#define MCIF_WB1_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                             0xFF000000L
>+//MCIF_WB1_MCIF_WB_BUF_1_STATUS
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                            0x0
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                         0x1
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                        0x2
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                          0x3
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                           0x4
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                              0x5
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                            0x8
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                           0xc
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT                                             0xf
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                        0x10
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT                                   0x1d
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT                                  0x1e
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT                                0x1f
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                              0x00000001L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                           0x00000002L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                          0x00000004L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                            0x00000008L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                             0x00000010L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                0x000000E0L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                              0x00000F00L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                             0x00007000L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK                                               0x00008000L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                          0x1FFF0000L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK                                     0x20000000L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK                                    0x40000000L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
>+//MCIF_WB1_MCIF_WB_BUF_1_STATUS2
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT                                       0x0
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                      0xd
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                      0xe
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                  0xf
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                              0x10
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                        0x11
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                        0x12
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                         0x13
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK                                         0x00001FFFL
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                        0x00002000L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                        0x00004000L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                0x00010000L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                          0x00020000L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                          0x00040000L
>+#define MCIF_WB1_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                           0x00080000L
>+//MCIF_WB1_MCIF_WB_BUF_2_STATUS
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                            0x0
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                         0x1
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                        0x2
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                          0x3
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                           0x4
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                              0x5
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                            0x8
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                           0xc
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT                                             0xf
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                        0x10
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT                                   0x1d
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT                                  0x1e
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT                                0x1f
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                              0x00000001L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                           0x00000002L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                          0x00000004L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                            0x00000008L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                             0x00000010L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                0x000000E0L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                              0x00000F00L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                             0x00007000L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK                                               0x00008000L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                          0x1FFF0000L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK                                     0x20000000L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK                                    0x40000000L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
>+//MCIF_WB1_MCIF_WB_BUF_2_STATUS2
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT                                       0x0
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                      0xd
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                      0xe
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                  0xf
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                              0x10
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                        0x11
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                        0x12
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                         0x13
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK                                         0x00001FFFL
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                        0x00002000L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                        0x00004000L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                0x00010000L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                          0x00020000L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                          0x00040000L
>+#define MCIF_WB1_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                           0x00080000L
>+//MCIF_WB1_MCIF_WB_BUF_3_STATUS
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                            0x0
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                         0x1
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                        0x2
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                          0x3
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                           0x4
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                              0x5
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                            0x8
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                           0xc
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT                                             0xf
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                        0x10
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT                                   0x1d
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT                                  0x1e
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT                                0x1f
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                              0x00000001L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                           0x00000002L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                          0x00000004L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                            0x00000008L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                             0x00000010L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                0x000000E0L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                              0x00000F00L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                             0x00007000L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK                                               0x00008000L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                          0x1FFF0000L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK                                     0x20000000L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK                                    0x40000000L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
>+//MCIF_WB1_MCIF_WB_BUF_3_STATUS2
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT                                       0x0
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                      0xd
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                      0xe
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                  0xf
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                              0x10
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                        0x11
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                        0x12
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                         0x13
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK                                         0x00001FFFL
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                        0x00002000L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                        0x00004000L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                0x00010000L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                          0x00020000L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                          0x00040000L
>+#define MCIF_WB1_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                           0x00080000L
>+//MCIF_WB1_MCIF_WB_BUF_4_STATUS
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                            0x0
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                         0x1
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                        0x2
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                          0x3
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                           0x4
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                              0x5
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                            0x8
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                           0xc
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT                                             0xf
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                        0x10
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT                                   0x1d
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT                                  0x1e
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT                                0x1f
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                              0x00000001L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                           0x00000002L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                          0x00000004L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                            0x00000008L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                             0x00000010L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                0x000000E0L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                              0x00000F00L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                             0x00007000L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK                                               0x00008000L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                          0x1FFF0000L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK                                     0x20000000L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK                                    0x40000000L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
>+//MCIF_WB1_MCIF_WB_BUF_4_STATUS2
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT                                       0x0
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                      0xd
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                      0xe
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                  0xf
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                              0x10
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                        0x11
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                        0x12
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                         0x13
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK                                         0x00001FFFL
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                        0x00002000L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                        0x00004000L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                0x00010000L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                          0x00020000L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                          0x00040000L
>+#define MCIF_WB1_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                           0x00080000L
>+//MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL
>+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                         0x0
>+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                   0x16
>+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                           0x00000003L
>+#define MCIF_WB1_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                     0xFFC00000L
>+//MCIF_WB1_MCIF_WB_SCLK_CHANGE
>+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                           0x0
>+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                       0x1
>+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                             0x00000001L
>+#define MCIF_WB1_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK                                         0x0000000EL
>+//MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX
>+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT                                    0x0
>+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT                                 0x8
>+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK                                      0x000000FFL
>+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK                                   0x00000100L
>+//MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA
>+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT                                      0x0
>+#define MCIF_WB1_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK                                        0xFFFFFFFFL
>+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y
>+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                            0x0
>+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                              0xFFFFFFFFL
>+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET
>+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT                              0x0
>+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C
>+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                            0x0
>+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                              0xFFFFFFFFL
>+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET
>+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT                              0x0
>+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y
>+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                            0x0
>+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                              0xFFFFFFFFL
>+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET
>+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT                              0x0
>+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C
>+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                            0x0
>+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                              0xFFFFFFFFL
>+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET
>+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT                              0x0
>+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y
>+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                            0x0
>+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                              0xFFFFFFFFL
>+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET
>+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT                              0x0
>+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C
>+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                            0x0
>+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                              0xFFFFFFFFL
>+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET
>+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT                              0x0
>+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y
>+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                            0x0
>+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                              0xFFFFFFFFL
>+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET
>+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT                              0x0
>+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C
>+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                            0x0
>+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                              0xFFFFFFFFL
>+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET
>+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT                              0x0
>+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL
>+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                            0x0
>+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                 0x4
>+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                0x5
>+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                           0x6
>+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                   0x8
>+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                 0x10
>+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                              0x00000001L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                   0x00000010L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                  0x00000020L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                             0x00000040L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                     0x00000F00L
>+#define MCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                   0x1FFF0000L
>+//MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
>+#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT               0x0
>+#define MCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                 0x0007FFFFL
>+//MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL
>+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT                     0x0
>+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                  0x1
>+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT                                 0x2
>+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                            0x4
>+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK                       0x00000001L
>+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                    0x00000002L
>+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK                                   0x00000004L
>+#define MCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                              0x00000070L
>+//MCIF_WB1_MCIF_WB_WATERMARK
>+#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                              0x0
>+#define MCIF_WB1_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                0x0000FFFFL
>+//MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL
>+#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                         0x0
>+#define MCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                           0x00000001L
>+//MCIF_WB1_MCIF_WB_WARM_UP_CNTL
>+#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT                                       0x8
>+#define MCIF_WB1_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK                                         0x0000FF00L
>+//MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL
>+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT                                0x0
>+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                   0x1
>+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK                                  0x00000001L
>+#define MCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                     0x00000002L
>+//MCIF_WB1_MULTI_LEVEL_QOS_CTRL
>+#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                       0x0
>+#define MCIF_WB1_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                         0x003FFFFFL
>+//MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE
>+#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                          0x0
>+#define MCIF_WB1_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                            0x000FFFFFL
>+//MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE
>+#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                      0x0
>+#define MCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                        0x000FFFFFL
>+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH
>+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                  0x0
>+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH
>+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                  0x0
>+#define MCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH
>+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                  0x0
>+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH
>+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                  0x0
>+#define MCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH
>+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                  0x0
>+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH
>+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                  0x0
>+#define MCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH
>+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                  0x0
>+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH
>+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                  0x0
>+#define MCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION
>+#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                              0x0
>+#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                             0x10
>+#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                0x00001FFFL
>+#define MCIF_WB1_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
>+//MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION
>+#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                              0x0
>+#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                             0x10
>+#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                0x00001FFFL
>+#define MCIF_WB1_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
>+//MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION
>+#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                              0x0
>+#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                             0x10
>+#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                0x00001FFFL
>+#define MCIF_WB1_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
>+//MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION
>+#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                              0x0
>+#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                             0x10
>+#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                0x00001FFFL
>+#define MCIF_WB1_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
>+
>+
>+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
>+//WBIF0_MISC_CTRL
>+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT                                             0x0
>+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT                                                     0x10
>+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK                                               0x000003FFL
>+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK                                                       0x00010000L
>+//WBIF0_SMU_WM_CONTROL
>+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL__SHIFT                                                      0x14
>+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ__SHIFT                                                      0x16
>+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT                                              0x18
>+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT                                           0x19
>+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_SEL_MASK                                                        0x00300000L
>+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_REQ_MASK                                                        0x00400000L
>+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK                                                0x01000000L
>+#define WBIF0_SMU_WM_CONTROL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK                                             0x02000000L
>+//WBIF0_PHASE0_OUTSTANDING_COUNTER
>+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT                          0x0
>+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
>+//WBIF0_PHASE1_OUTSTANDING_COUNTER
>+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT                          0x0
>+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
>+//VGA_SRC_SPLIT_CNTL
>+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT                                                              0x0
>+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK                                                                0x00000003L
>+//MMHUBBUB_MEM_PWR_STATUS
>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT                                         0x0
>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT                                         0x2
>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT                                       0x4
>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT                                       0x6
>+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT                                                     0x1f
>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK                                           0x00000003L
>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK                                           0x0000000CL
>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK                                         0x00000030L
>+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK                                         0x000000C0L
>+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK                                                       0x80000000L
>+//MMHUBBUB_MEM_PWR_CNTL
>+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT                                                       0x0
>+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT                                                         0x1
>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT                                                 0x2
>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT                                                   0x4
>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT                                              0x5
>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT                                               0x7
>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT                                             0x8
>+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK                                                         0x00000001L
>+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK                                                           0x00000002L
>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK                                                   0x0000000CL
>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK                                                     0x00000010L
>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK                                                0x00000060L
>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK                                                 0x00000080L
>+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK                                               0x00000100L
>+//MMHUBBUB_CLOCK_CNTL
>+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT                                               0x5
>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT                                                  0x6
>+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT                                                   0x7
>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT                                                    0x8
>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT                                                  0x9
>+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT                                                   0xa
>+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK                                                 0x00000020L
>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK                                                    0x00000040L
>+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK                                                     0x00000080L
>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK                                                      0x00000100L
>+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK                                                    0x00000200L
>+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK                                                     0x00000400L
>+//MMHUBBUB_SOFT_RESET
>+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT                                                            0x0
>+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT                                                          0x1
>+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT                                                          0x2
>+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT                                                          0x8
>+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK                                                              0x00000001L
>+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK                                                            0x00000002L
>+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK                                                            0x00000004L
>+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK                                                            0x00000100L
>+//DMU_IF_ERR_STATUS
>+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT                                                      0x0
>+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT                                                  0x4
>+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK                                                        0x00000001L
>+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK                                                    0x00000010L
>+//MMHUBBUB_CLIENT_UNIT_ID
>+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT                                                           0x0
>+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT                                                         0x8
>+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK                                                             0x0000003FL
>+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK                                                           0x00003F00L
>+
>+
>+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
>+//MCIF_CONTROL
>+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT                                                   0x1e
>+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT                                              0x1f
>+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK                                                     0x40000000L
>+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK                                                0x80000000L
>+//MCIF_WRITE_COMBINE_CONTROL
>+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT                                         0x0
>+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK                                           0x000003FFL
>+//MCIF_PHASE0_OUTSTANDING_COUNTER
>+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT                               0x0
>+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
>+//MCIF_PHASE1_OUTSTANDING_COUNTER
>+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT                               0x0
>+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
>+//MCIF_PHASE2_OUTSTANDING_COUNTER
>+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT                               0x0
>+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
>+
>+
>+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON4_PERFCOUNTER_CNTL
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
>+//DC_PERFMON4_PERFCOUNTER_CNTL2
>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
>+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
>+//DC_PERFMON4_PERFCOUNTER_STATE
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
>+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
>+//DC_PERFMON4_PERFMON_CNTL
>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
>+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
>+//DC_PERFMON4_PERFMON_CNTL2
>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
>+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
>+//DC_PERFMON4_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
>+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
>+//DC_PERFMON4_PERFMON_CVALUE_LOW
>+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
>+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
>+//DC_PERFMON4_PERFMON_HI
>+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
>+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
>+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
>+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
>+//DC_PERFMON4_PERFMON_LOW
>+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
>+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream0_dispdec
>+//AZF0STREAM0_AZALIA_STREAM_INDEX
>+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
>+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
>+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
>+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
>+//AZF0STREAM0_AZALIA_STREAM_DATA
>+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
>+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream1_dispdec
>+//AZF0STREAM1_AZALIA_STREAM_INDEX
>+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
>+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
>+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
>+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
>+//AZF0STREAM1_AZALIA_STREAM_DATA
>+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
>+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream2_dispdec
>+//AZF0STREAM2_AZALIA_STREAM_INDEX
>+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
>+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
>+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
>+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
>+//AZF0STREAM2_AZALIA_STREAM_DATA
>+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
>+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream3_dispdec
>+//AZF0STREAM3_AZALIA_STREAM_INDEX
>+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
>+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
>+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
>+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
>+//AZF0STREAM3_AZALIA_STREAM_DATA
>+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
>+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream4_dispdec
>+//AZF0STREAM4_AZALIA_STREAM_INDEX
>+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
>+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
>+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
>+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
>+//AZF0STREAM4_AZALIA_STREAM_DATA
>+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
>+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream5_dispdec
>+//AZF0STREAM5_AZALIA_STREAM_INDEX
>+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
>+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
>+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
>+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
>+//AZF0STREAM5_AZALIA_STREAM_DATA
>+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
>+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream6_dispdec
>+//AZF0STREAM6_AZALIA_STREAM_INDEX
>+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
>+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
>+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
>+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
>+//AZF0STREAM6_AZALIA_STREAM_DATA
>+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
>+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream7_dispdec
>+//AZF0STREAM7_AZALIA_STREAM_INDEX
>+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
>+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
>+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
>+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
>+//AZF0STREAM7_AZALIA_STREAM_DATA
>+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
>+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_az_misc_dispdec
>+//AZ_CLOCK_CNTL
>+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT                                                       0x0
>+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT                                                              0x8
>+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT                                                         0x10
>+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT                                                              0x18
>+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK                                                         0x00000001L
>+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK                                                                0x00000100L
>+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK                                                           0x00010000L
>+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK                                                                0x1F000000L
>+
>+
>+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON5_PERFCOUNTER_CNTL
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
>+//DC_PERFMON5_PERFCOUNTER_CNTL2
>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
>+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
>+//DC_PERFMON5_PERFCOUNTER_STATE
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
>+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
>+//DC_PERFMON5_PERFMON_CNTL
>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
>+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
>+//DC_PERFMON5_PERFMON_CNTL2
>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
>+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
>+//DC_PERFMON5_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
>+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
>+//DC_PERFMON5_PERFMON_CVALUE_LOW
>+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
>+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
>+//DC_PERFMON5_PERFMON_HI
>+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
>+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
>+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
>+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
>+//DC_PERFMON5_PERFMON_LOW
>+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
>+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0controller_dispdec
>+//AZALIA_CONTROLLER_CLOCK_GATING
>+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT                                            0x0
>+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT                                                 0x4
>+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK                                              0x00000001L
>+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK                                                   0x00000010L
>+//AZALIA_AUDIO_DTO
>+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT                                                       0x0
>+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT                                                      0x10
>+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK                                                         0x0000FFFFL
>+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK                                                        0xFFFF0000L
>+//AZALIA_AUDIO_DTO_CONTROL
>+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT                                               0x8
>+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK                                                 0x00000300L
>+//AZALIA_SOCCLK_CONTROL
>+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                  0x1
>+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                    0x00000002L
>+//AZALIA_UNDERFLOW_FILLER_SAMPLE
>+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT                                 0x0
>+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK                                   0xFFFFFFFFL
>+//AZALIA_DATA_DMA_CONTROL
>+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT                                                    0x0
>+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT                                              0x2
>+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT                                                  0x4
>+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT                                            0x6
>+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT                                          0x10
>+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT                                              0x11
>+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK                                                      0x00000003L
>+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK                                                0x0000000CL
>+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK                                                    0x00000030L
>+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK                                              0x000000C0L
>+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK                                            0x00010000L
>+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK                                                0x00020000L
>+//AZALIA_BDL_DMA_CONTROL
>+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT                                                      0x0
>+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT                                                0x2
>+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT                                                    0x4
>+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT                                              0x6
>+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK                                                        0x00000003L
>+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK                                                  0x0000000CL
>+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK                                                      0x00000030L
>+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK                                                0x000000C0L
>+//AZALIA_RIRB_AND_DP_CONTROL
>+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT                                                     0x0
>+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT                                                   0x4
>+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT                                             0x5
>+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK                                                       0x00000001L
>+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK                                                     0x00000010L
>+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK                                               0x000001E0L
>+//AZALIA_CORB_DMA_CONTROL
>+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT                                                    0x0
>+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT                                                  0x4
>+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK                                                      0x00000001L
>+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK                                                    0x00000010L
>+//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
>+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT            0x0
>+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK              0xFFFFFFFFL
>+//AZALIA_CYCLIC_BUFFER_SYNC
>+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT                                           0x0
>+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK                                             0x00000001L
>+//AZALIA_GLOBAL_CAPABILITIES
>+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                               0x1
>+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                 0x00000006L
>+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
>+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                    0x0
>+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x10
>+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                      0x0000FFFFL
>+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFF0000L
>+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT                                     0x0
>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT                                    0x8
>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT                               0x10
>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK                                       0x000000FFL
>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK                                      0x00000100L
>+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK                                 0x00FF0000L
>+//AZALIA_INPUT_PAYLOAD_CAPABILITY
>+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                      0x0
>+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x10
>+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                        0x0000FFFFL
>+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFF0000L
>+//AZALIA_INPUT_CRC0_CONTROL0
>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
>+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
>+//AZALIA_INPUT_CRC0_CONTROL1
>+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
>+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
>+//AZALIA_INPUT_CRC0_CONTROL2
>+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
>+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
>+//AZALIA_INPUT_CRC0_CONTROL3
>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
>+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
>+//AZALIA_INPUT_CRC0_RESULT
>+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
>+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
>+//AZALIA_INPUT_CRC1_CONTROL0
>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
>+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
>+//AZALIA_INPUT_CRC1_CONTROL1
>+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
>+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
>+//AZALIA_INPUT_CRC1_CONTROL2
>+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
>+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
>+//AZALIA_INPUT_CRC1_CONTROL3
>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
>+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
>+//AZALIA_INPUT_CRC1_RESULT
>+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
>+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
>+//AZALIA_CRC0_CONTROL0
>+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT                                                                   0x0
>+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
>+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
>+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
>+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
>+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
>+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
>+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
>+//AZALIA_CRC0_CONTROL1
>+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
>+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
>+//AZALIA_CRC0_CONTROL2
>+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
>+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
>+//AZALIA_CRC0_CONTROL3
>+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
>+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
>+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
>+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
>+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
>+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
>+//AZALIA_CRC0_RESULT
>+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT                                                                 0x0
>+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
>+//AZALIA_CRC1_CONTROL0
>+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT                                                                   0x0
>+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
>+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
>+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
>+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
>+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
>+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
>+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
>+//AZALIA_CRC1_CONTROL1
>+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
>+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
>+//AZALIA_CRC1_CONTROL2
>+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
>+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
>+//AZALIA_CRC1_CONTROL3
>+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
>+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
>+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
>+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
>+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
>+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
>+//AZALIA_CRC1_RESULT
>+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT                                                                 0x0
>+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
>+//AZALIA_MEM_PWR_CTRL
>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT                                                          0x0
>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT                                                            0x2
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT                                            0x3
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT                                              0x5
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT                                            0x6
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT                                              0x8
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT                                            0x9
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT                                              0xb
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT                                            0xc
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT                                              0xe
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT                                            0xf
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT                                              0x11
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT                                            0x12
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT                                              0x14
>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT                                                       0x1c
>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK                                                            0x00000003L
>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK                                                              0x00000004L
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK                                              0x00000018L
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK                                                0x00000020L
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK                                              0x000000C0L
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK                                                0x00000100L
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK                                              0x00000600L
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK                                                0x00000800L
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK                                              0x00003000L
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK                                                0x00004000L
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK                                              0x00018000L
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK                                                0x00020000L
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK                                              0x000C0000L
>+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK                                                0x00100000L
>+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK                                                         0x30000000L
>+//AZALIA_MEM_PWR_STATUS
>+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT                                                        0x0
>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT                                          0x2
>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT                                          0x4
>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT                                          0x6
>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT                                          0x8
>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT                                          0xa
>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT                                          0xc
>+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK                                                          0x00000003L
>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK                                            0x0000000CL
>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK                                            0x00000030L
>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK                                            0x000000C0L
>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK                                            0x00000300L
>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK                                            0x00000C00L
>+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK                                            0x00003000L
>+
>+
>+// addressBlock: dce_dc_hda_azf0root_dispdec
>+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
>+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
>+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
>+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
>+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
>+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
>+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
>+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT                                       0x0
>+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT                                0x4
>+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK                                         0x00000007L
>+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK                                  0x00000070L
>+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
>+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT                        0x0
>+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK                          0x0000003FL
>+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
>+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
>+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
>+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
>+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
>+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
>+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
>+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
>+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
>+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
>+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
>+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT                                           0x0
>+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                           0x4
>+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK                                             0x00000007L
>+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                             0x00000010L
>+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
>+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT                               0x0
>+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT               0x4
>+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK                                 0x00000007L
>+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                 0x00000010L
>+//AZALIA_F0_GTC_GROUP_OFFSET0
>+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT                                                 0x0
>+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK                                                   0xFFFFFFFFL
>+//AZALIA_F0_GTC_GROUP_OFFSET1
>+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT                                                 0x0
>+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK                                                   0xFFFFFFFFL
>+//AZALIA_F0_GTC_GROUP_OFFSET2
>+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT                                                 0x0
>+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK                                                   0xFFFFFFFFL
>+//AZALIA_F0_GTC_GROUP_OFFSET3
>+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT                                                 0x0
>+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK                                                   0xFFFFFFFFL
>+//AZALIA_F0_GTC_GROUP_OFFSET4
>+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT                                                 0x0
>+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK                                                   0xFFFFFFFFL
>+//AZALIA_F0_GTC_GROUP_OFFSET5
>+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT                                                 0x0
>+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK                                                   0xFFFFFFFFL
>+//AZALIA_F0_GTC_GROUP_OFFSET6
>+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT                                                 0x0
>+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK                                                   0xFFFFFFFFL
>+//REG_DC_AUDIO_PORT_CONNECTIVITY
>+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT                                          0x0
>+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                          0x4
>+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK                                            0x00000007L
>+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                            0x00000010L
>+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
>+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT                              0x0
>+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT              0x4
>+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK                                0x00000007L
>+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                0x00000010L
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream8_dispdec
>+//AZF0STREAM8_AZALIA_STREAM_INDEX
>+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
>+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
>+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
>+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
>+//AZF0STREAM8_AZALIA_STREAM_DATA
>+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
>+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream9_dispdec
>+//AZF0STREAM9_AZALIA_STREAM_INDEX
>+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
>+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
>+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
>+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
>+//AZF0STREAM9_AZALIA_STREAM_DATA
>+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
>+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream10_dispdec
>+//AZF0STREAM10_AZALIA_STREAM_INDEX
>+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
>+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
>+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
>+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
>+//AZF0STREAM10_AZALIA_STREAM_DATA
>+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
>+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream11_dispdec
>+//AZF0STREAM11_AZALIA_STREAM_INDEX
>+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
>+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
>+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
>+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
>+//AZF0STREAM11_AZALIA_STREAM_DATA
>+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
>+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream12_dispdec
>+//AZF0STREAM12_AZALIA_STREAM_INDEX
>+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
>+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
>+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
>+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
>+//AZF0STREAM12_AZALIA_STREAM_DATA
>+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
>+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream13_dispdec
>+//AZF0STREAM13_AZALIA_STREAM_INDEX
>+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
>+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
>+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
>+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
>+//AZF0STREAM13_AZALIA_STREAM_DATA
>+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
>+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream14_dispdec
>+//AZF0STREAM14_AZALIA_STREAM_INDEX
>+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
>+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
>+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
>+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
>+//AZF0STREAM14_AZALIA_STREAM_DATA
>+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
>+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0stream15_dispdec
>+//AZF0STREAM15_AZALIA_STREAM_INDEX
>+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
>+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
>+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
>+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
>+//AZF0STREAM15_AZALIA_STREAM_DATA
>+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
>+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
>+//DCHUBBUB_SDPIF_CFG0
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT                                                  0x0
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT                                                         0x1
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT                                                0x3
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT                                                     0x6
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT                                                    0xa
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT                                               0xb
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT                                              0xc
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT                                                 0xd
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT                                                       0xe
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT                                                        0xf
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT                                             0x19
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK                                                    0x00000001L
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK                                                           0x00000006L
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK                                                  0x00000038L
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK                                                       0x000003C0L
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK                                                      0x00000400L
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK                                                 0x00000800L
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK                                                0x00001000L
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK                                                   0x00002000L
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK                                                         0x00004000L
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK                                                          0x00008000L
>+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK                                               0x7E000000L
>+//VM_REQUEST_PHYSICAL
>+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT                                                      0x0
>+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT                                                      0x3
>+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK                                                        0x00000001L
>+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK                                                        0x00000008L
>+//DCHUBBUB_FORCE_IO_STATUS_0
>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT                                              0x0
>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT                                       0x1
>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT                                        0x2
>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT                                      0x3
>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT                                 0x7
>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT                                      0xa
>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK                                                0x00000001L
>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK                                         0x00000002L
>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK                                          0x00000004L
>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK                                        0x00000078L
>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK                                   0x00000380L
>+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK                                        0xFFFFFC00L
>+//DCHUBBUB_FORCE_IO_STATUS_1
>+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT                                      0x0
>+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK                                        0x001FFFFFL
>+//DCN_VM_FB_LOCATION_BASE
>+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                               0x0
>+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                 0x00FFFFFFL
>+//DCN_VM_FB_LOCATION_TOP
>+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                 0x0
>+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                   0x00FFFFFFL
>+//DCN_VM_FB_OFFSET
>+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                    0x0
>+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK                                                                      0x00FFFFFFL
>+//DCN_VM_AGP_BOT
>+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT                                                                        0x0
>+#define DCN_VM_AGP_BOT__AGP_BOT_MASK                                                                          0x00FFFFFFL
>+//DCN_VM_AGP_TOP
>+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT                                                                        0x0
>+#define DCN_VM_AGP_TOP__AGP_TOP_MASK                                                                          0x00FFFFFFL
>+//DCN_VM_AGP_BASE
>+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT                                                                      0x0
>+#define DCN_VM_AGP_BASE__AGP_BASE_MASK                                                                        0x00FFFFFFL
>+//DCN_VM_LOCAL_HBM_ADDRESS_START
>+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT                                                  0x0
>+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK                                                    0x000FFFFFL
>+//DCN_VM_LOCAL_HBM_ADDRESS_END
>+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT                                                      0x0
>+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK                                                        0x000FFFFFL
>+//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
>+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0
>+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L
>+//DCHUBBUB_SDPIF_PIPE_SEC_LVL
>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT                                               0x0
>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT                                               0x3
>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT                                               0x6
>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT                                               0x9
>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK                                                 0x00000007L
>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK                                                 0x00000038L
>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK                                                 0x000001C0L
>+#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK                                                 0x00000E00L
>+//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL
>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT                                 0x0
>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT                                 0x3
>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT                                 0x6
>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT                                 0x9
>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK                                   0x00000007L
>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK                                   0x00000038L
>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK                                   0x000001C0L
>+#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK                                   0x00000E00L
>+//DCHUBBUB_SDPIF_MEM_PWR_CTRL
>+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT                                      0x0
>+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT                                        0x2
>+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK                                        0x00000003L
>+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK                                          0x00000004L
>+//DCHUBBUB_SDPIF_MEM_PWR_STATUS
>+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT                                    0x0
>+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK                                      0x00000003L
>+//DCHUBBUB_SDPIF_CFG1
>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT                                                 0x0
>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT                                                    0x1
>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x2
>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT                                                         0x8
>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK                                                   0x00000001L
>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK                                                      0x00000002L
>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000004L
>+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK                                                           0x00000100L
>+//DCHUBBUB_SDPIF_CFG2
>+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT                                                         0x0
>+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT                                                      0x8
>+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT                                                     0x10
>+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK                                                           0x00000001L
>+#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK                                                        0x00000700L
>+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK                                                       0x01FF0000L
>+
>+
>+// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
>+//DCHUBBUB_RET_PATH_DCC_CFG
>+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT                                                 0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK                                                   0x00000001L
>+//DCHUBBUB_RET_PATH_DCC_CFG0_0
>+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG0_1
>+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG1_0
>+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG1_1
>+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG2_0
>+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG2_1
>+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG3_0
>+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG3_1
>+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG4_0
>+#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG4_1
>+#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG5_0
>+#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG5_1
>+#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG6_0
>+#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG6_1
>+#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG7_0
>+#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_DCC_CFG7_1
>+#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1__SHIFT                                              0x0
>+#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1_MASK                                                0xFFFFFFFFL
>+//DCHUBBUB_RET_PATH_MEM_PWR_CTRL
>+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT                                0x0
>+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT                                  0x2
>+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK                                  0x00000003L
>+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK                                    0x00000004L
>+//DCHUBBUB_RET_PATH_MEM_PWR_STATUS
>+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT                              0x0
>+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK                                0x00000003L
>+//DCHUBBUB_CRC_CTRL
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT                                                             0x0
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT                                                        0x1
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT                                              0x2
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT                                              0x3
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT                                                       0x4
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT                                                       0x6
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT                                                       0x8
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT                                                       0xc
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_MASK_SURF_SEL_MSB__SHIFT                                              0xf
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT                                                   0x14
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK                                                               0x00000001L
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK                                                          0x00000002L
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK                                                0x00000004L
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK                                                0x00000008L
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK                                                         0x00000030L
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK                                                         0x000000C0L
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK                                                         0x00000F00L
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK                                                         0x00007000L
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_MASK_SURF_SEL_MSB_MASK                                                0x00008000L
>+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK                                                     0x00100000L
>+//DCHUBBUB_CRC0_VAL_R_G
>+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT                                                      0x0
>+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT                                                       0x10
>+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK                                                        0x0000FFFFL
>+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK                                                         0xFFFF0000L
>+//DCHUBBUB_CRC0_VAL_B_A
>+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT                                                      0x0
>+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT                                                     0x10
>+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK                                                        0x0000FFFFL
>+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK                                                       0xFFFF0000L
>+//DCHUBBUB_CRC1_VAL_R_G
>+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT                                                      0x0
>+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT                                                       0x10
>+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK                                                        0x0000FFFFL
>+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK                                                         0xFFFF0000L
>+//DCHUBBUB_CRC1_VAL_B_A
>+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT                                                      0x0
>+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT                                                     0x10
>+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK                                                        0x0000FFFFL
>+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK                                                       0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dchubbub_hubbub_dispdec
>+//DCHUBBUB_ARB_DF_REQ_OUTSTAND
>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT                                    0x0
>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT                                    0xc
>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT                   0x17
>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK                                      0x000001FFL
>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK                                      0x001FF000L
>+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK                     0xFF800000L
>+//DCHUBBUB_ARB_SAT_LEVEL
>+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT                                                 0x0
>+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK                                                   0xFFFFFFFFL
>+//DCHUBBUB_ARB_QOS_FORCE
>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT                                           0x0
>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT                                          0x8
>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK                                             0x0000000FL
>+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK                                            0x00000100L
>+//DCHUBBUB_ARB_DRAM_STATE_CNTL
>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT                      0x0
>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT                     0x1
>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT                     0x4
>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT                    0x5
>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST__SHIFT  0x8
>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL__SHIFT  0x9
>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK                        0x00000001L
>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK                       0x00000002L
>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK                       0x00000010L
>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK                      0x00000020L
>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_MASK  0x00000100L
>+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL_MASK  0x00000200L
>+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT                   0x0
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A__SHIFT                 0x10
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK                     0x00003FFFL
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A_MASK                   0x3FFF0000L
>+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A
>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT             0x0
>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK               0x00003FFFL
>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT               0x0
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A__SHIFT        0x10
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK                 0x0000FFFFL
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A_MASK          0xFFFF0000L
>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT                 0x0
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A__SHIFT          0x10
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK                   0x0000FFFFL
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A_MASK            0xFFFF0000L
>+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT  0x0
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT  0x10
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK   0x0000FFFFL
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK  0xFFFF0000L
>+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT                   0x0
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B__SHIFT                 0x10
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK                     0x00003FFFL
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B_MASK                   0x3FFF0000L
>+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B
>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT             0x0
>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK               0x00003FFFL
>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT               0x0
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B__SHIFT        0x10
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK                 0x0000FFFFL
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B_MASK          0xFFFF0000L
>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT                 0x0
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B__SHIFT          0x10
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK                   0x0000FFFFL
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B_MASK            0xFFFF0000L
>+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT  0x0
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT  0x10
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK   0x0000FFFFL
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK  0xFFFF0000L
>+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT                   0x0
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C__SHIFT                 0x10
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK                     0x00003FFFL
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C_MASK                   0x3FFF0000L
>+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C
>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT             0x0
>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK               0x00003FFFL
>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT               0x0
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C__SHIFT        0x10
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK                 0x0000FFFFL
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C_MASK          0xFFFF0000L
>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT                 0x0
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C__SHIFT          0x10
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK                   0x0000FFFFL
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C_MASK            0xFFFF0000L
>+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT  0x0
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT  0x10
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK   0x0000FFFFL
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK  0xFFFF0000L
>+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT                   0x0
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D__SHIFT                 0x10
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK                     0x00003FFFL
>+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D_MASK                   0x3FFF0000L
>+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT             0x0
>+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK               0x00003FFFL
>+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT               0x0
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D__SHIFT        0x10
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK                 0x0000FFFFL
>+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D_MASK          0xFFFF0000L
>+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT                 0x0
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D__SHIFT          0x10
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK                   0x0000FFFFL
>+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D_MASK            0xFFFF0000L
>+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT  0x0
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT  0x10
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK   0x0000FFFFL
>+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK  0xFFFF0000L
>+//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL
>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT                       0x0
>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT       0x4
>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT        0x5
>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT                      0x8
>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK                         0x00000003L
>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK         0x00000010L
>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK          0x00000020L
>+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK                        0x00000100L
>+//DCHUBBUB_ARB_TIMEOUT_ENABLE
>+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT                                       0x0
>+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK                                         0x00000001L
>+//DCHUBBUB_GLOBAL_TIMER_CNTL
>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT                                       0x0
>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT                                       0xc
>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT                                         0x10
>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK                                         0x0000000FL
>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK                                         0x00001000L
>+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK                                           0xFFFF0000L
>+//SURFACE_CHECK0_ADDRESS_LSB
>+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT                                         0x0
>+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
>+//SURFACE_CHECK0_ADDRESS_MSB
>+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT                                         0x0
>+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT                                             0x1f
>+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK                                           0x0000FFFFL
>+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK                                               0x80000000L
>+//SURFACE_CHECK1_ADDRESS_LSB
>+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT                                         0x0
>+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
>+//SURFACE_CHECK1_ADDRESS_MSB
>+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT                                         0x0
>+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT                                             0x1f
>+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK                                           0x0000FFFFL
>+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK                                               0x80000000L
>+//SURFACE_CHECK2_ADDRESS_LSB
>+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT                                         0x0
>+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
>+//SURFACE_CHECK2_ADDRESS_MSB
>+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT                                         0x0
>+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT                                             0x1f
>+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK                                           0x0000FFFFL
>+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK                                               0x80000000L
>+//SURFACE_CHECK3_ADDRESS_LSB
>+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT                                         0x0
>+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
>+//SURFACE_CHECK3_ADDRESS_MSB
>+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT                                         0x0
>+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT                                             0x1f
>+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK                                           0x0000FFFFL
>+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK                                               0x80000000L
>+//VTG0_CONTROL
>+#define VTG0_CONTROL__VTG0_FP2__SHIFT                                                                         0x0
>+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT                                                                 0x10
>+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT                                                                      0x1f
>+#define VTG0_CONTROL__VTG0_FP2_MASK                                                                           0x00007FFFL
>+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
>+#define VTG0_CONTROL__VTG0_ENABLE_MASK                                                                        0x80000000L
>+//VTG1_CONTROL
>+#define VTG1_CONTROL__VTG1_FP2__SHIFT                                                                         0x0
>+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT                                                                 0x10
>+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT                                                                      0x1f
>+#define VTG1_CONTROL__VTG1_FP2_MASK                                                                           0x00007FFFL
>+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
>+#define VTG1_CONTROL__VTG1_ENABLE_MASK                                                                        0x80000000L
>+//VTG2_CONTROL
>+#define VTG2_CONTROL__VTG2_FP2__SHIFT                                                                         0x0
>+#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT                                                                 0x10
>+#define VTG2_CONTROL__VTG2_ENABLE__SHIFT                                                                      0x1f
>+#define VTG2_CONTROL__VTG2_FP2_MASK                                                                           0x00007FFFL
>+#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
>+#define VTG2_CONTROL__VTG2_ENABLE_MASK                                                                        0x80000000L
>+//VTG3_CONTROL
>+#define VTG3_CONTROL__VTG3_FP2__SHIFT                                                                         0x0
>+#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT                                                                 0x10
>+#define VTG3_CONTROL__VTG3_ENABLE__SHIFT                                                                      0x1f
>+#define VTG3_CONTROL__VTG3_FP2_MASK                                                                           0x00007FFFL
>+#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
>+#define VTG3_CONTROL__VTG3_ENABLE_MASK                                                                        0x80000000L
>+//DCHUBBUB_SOFT_RESET
>+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT                                                0x0
>+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT                                                   0x1
>+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT                                                        0x4
>+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK                                                  0x00000001L
>+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK                                                     0x00000002L
>+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK                                                          0x00000010L
>+//DCHUBBUB_CLOCK_CNTL
>+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
>+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                               0x5
>+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                                0x6
>+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
>+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK                                                 0x00000020L
>+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK                                                  0x00000040L
>+//DCFCLK_CNTL
>+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT                                                              0x0
>+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT                                                             0x4
>+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT                                                                   0x1f
>+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK                                                                0x0000000FL
>+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK                                                               0x00000FF0L
>+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK                                                                     0x80000000L
>+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT                                 0x0
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT                                    0x3
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT                                0x7
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT                                  0xa
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT                                          0xb
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK                                   0x00000001L
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK                                      0x00000078L
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK                                  0x00000380L
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK                                    0x00000400L
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK                                            0x007FF800L
>+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT                          0x0
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT                     0x1
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT                         0x4
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT                                     0xc
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT                                     0x13
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT                               0x1f
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK                            0x00000001L
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK                       0x0000000EL
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK                           0x00000FF0L
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK                                       0x00007000L
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK                                       0x7FF80000L
>+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK                                 0x80000000L
>+//DCHUBBUB_VLINE_SNAPSHOT
>+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT                                               0x0
>+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK                                                 0x00000001L
>+//DCHUBBUB_CTRL_STATUS
>+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT                                                  0x0
>+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK                                                    0x00000001L
>+//DCHUBBUB_TIMEOUT_DETECTION_CTRL1
>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT                                0x0
>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT                         0x6
>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK                                  0x0000003FL
>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK                           0xFFFFFFC0L
>+//DCHUBBUB_TIMEOUT_DETECTION_CTRL2
>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT                      0x0
>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT                                0x1b
>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT                                 0x1c
>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK                        0x07FFFFFFL
>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK                                  0x08000000L
>+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK                                   0x10000000L
>+//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS
>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT                                 0x0
>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT                                 0x1
>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT                                  0x2
>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT                                   0x3
>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK                                   0x00000001L
>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK                                   0x00000002L
>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK                                    0x00000004L
>+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK                                     0x000000F8L
>+//DCHUBBUB_TEST_DEBUG_INDEX
>+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT                                           0x0
>+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK                                             0x000000FFL
>+//DCHUBBUB_TEST_DEBUG_DATA
>+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT                                             0x0
>+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK                                               0xFFFFFFFFL
>+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A
>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT                                 0x0
>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK                                   0x000003FFL
>+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A
>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT                               0x0
>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK                                 0x000003FFL
>+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B
>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT                                 0x0
>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK                                   0x000003FFL
>+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B
>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT                               0x0
>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK                                 0x000003FFL
>+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C
>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT                                 0x0
>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK                                   0x000003FFL
>+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C
>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT                               0x0
>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK                                 0x000003FFL
>+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D
>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT                                 0x0
>+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK                                   0x000003FFL
>+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D
>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT                               0x0
>+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK                                 0x000003FFL
>+//DCHUBBUB_ARB_HOSTVM_CNTL
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT                                          0x0
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT                                    0x1
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT                                                       0x2
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT                                                  0x3
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT                                                  0x4
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT                                           0x5
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT                                         0x6
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT                                          0x8
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT                                           0x10
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT                                                           0x18
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT                                0x1c
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK                                            0x00000001L
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK                                      0x00000002L
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK                                                         0x00000004L
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK                                                    0x00000008L
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK                                                    0x00000010L
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK                                             0x00000020L
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK                                           0x00000040L
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK                                            0x00003F00L
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK                                             0x00FF0000L
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK                                                             0x0F000000L
>+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK                                  0xF0000000L
>+//FMON_CTRL
>+#define FMON_CTRL__FMON_START__SHIFT                                                                          0x0
>+#define FMON_CTRL__FMON_MODE__SHIFT                                                                           0x1
>+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT                                                                  0x4
>+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT                                                                  0x5
>+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT                                                               0x6
>+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT                                                                  0x7
>+#define FMON_CTRL__FMON_STATE__SHIFT                                                                          0x9
>+#define FMON_CTRL__FMON_URG_FILTER__SHIFT                                                                     0xc
>+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT                                                                  0xd
>+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT                                                                   0x11
>+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT                                                                   0x16
>+#define FMON_CTRL__FMON_SOF_SEL__SHIFT                                                                        0x1b
>+#define FMON_CTRL__FMON_START_MASK                                                                            0x00000001L
>+#define FMON_CTRL__FMON_MODE_MASK                                                                             0x00000006L
>+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK                                                                    0x00000010L
>+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK                                                                    0x00000020L
>+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK                                                                 0x00000040L
>+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK                                                                    0x00000180L
>+#define FMON_CTRL__FMON_STATE_MASK                                                                            0x00000600L
>+#define FMON_CTRL__FMON_URG_FILTER_MASK                                                                       0x00001000L
>+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK                                                                    0x0001E000L
>+#define FMON_CTRL__FMON_FILTER_UID_1_MASK                                                                     0x003E0000L
>+#define FMON_CTRL__FMON_FILTER_UID_2_MASK                                                                     0x07C00000L
>+#define FMON_CTRL__FMON_SOF_SEL_MASK                                                                          0x38000000L
>+
>+
>+// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON6_PERFCOUNTER_CNTL
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
>+//DC_PERFMON6_PERFCOUNTER_CNTL2
>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
>+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
>+//DC_PERFMON6_PERFCOUNTER_STATE
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
>+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
>+//DC_PERFMON6_PERFMON_CNTL
>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
>+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
>+//DC_PERFMON6_PERFMON_CNTL2
>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
>+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
>+//DC_PERFMON6_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
>+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
>+//DC_PERFMON6_PERFMON_CVALUE_LOW
>+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
>+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
>+//DC_PERFMON6_PERFMON_HI
>+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
>+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
>+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
>+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
>+//DC_PERFMON6_PERFMON_LOW
>+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
>+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
>+//DCN_VM_CONTEXT0_CNTL
>+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT                                             0x1
>+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
>+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
>+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
>+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
>+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
>+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
>+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
>+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
>+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
>+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
>+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
>+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT1_CNTL
>+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT                                             0x1
>+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
>+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
>+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
>+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
>+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
>+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
>+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
>+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
>+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
>+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
>+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
>+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT2_CNTL
>+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT                                             0x1
>+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
>+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
>+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
>+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
>+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
>+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
>+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
>+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
>+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
>+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
>+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
>+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT3_CNTL
>+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT                                             0x1
>+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
>+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
>+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
>+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
>+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
>+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
>+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
>+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
>+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
>+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
>+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
>+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT4_CNTL
>+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT                                             0x1
>+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
>+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
>+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
>+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
>+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
>+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
>+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
>+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
>+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
>+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
>+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
>+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT5_CNTL
>+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT                                             0x1
>+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
>+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
>+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
>+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
>+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
>+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
>+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
>+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
>+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
>+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
>+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
>+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT6_CNTL
>+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT                                             0x1
>+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
>+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
>+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
>+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
>+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
>+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
>+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
>+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
>+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
>+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
>+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
>+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT7_CNTL
>+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT                                             0x1
>+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
>+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
>+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
>+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
>+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
>+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
>+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
>+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
>+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
>+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
>+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
>+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT8_CNTL
>+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT                                             0x1
>+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
>+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
>+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
>+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
>+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
>+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
>+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
>+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
>+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
>+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
>+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
>+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT9_CNTL
>+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT                                             0x1
>+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
>+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
>+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
>+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
>+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
>+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
>+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
>+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
>+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
>+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
>+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
>+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
>+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT10_CNTL
>+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT                                           0x1
>+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
>+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
>+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
>+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
>+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
>+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
>+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
>+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
>+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
>+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
>+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
>+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
>+//DCN_VM_CONTEXT11_CNTL
>+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT                                           0x1
>+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
>+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
>+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
>+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
>+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
>+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
>+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
>+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
>+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
>+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
>+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
>+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
>+//DCN_VM_CONTEXT12_CNTL
>+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT                                           0x1
>+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
>+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
>+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
>+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
>+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
>+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
>+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
>+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
>+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
>+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
>+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
>+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
>+//DCN_VM_CONTEXT13_CNTL
>+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT                                           0x1
>+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
>+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
>+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
>+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
>+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
>+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
>+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
>+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
>+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
>+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
>+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
>+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
>+//DCN_VM_CONTEXT14_CNTL
>+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT                                           0x1
>+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
>+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
>+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
>+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
>+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
>+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
>+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
>+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
>+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
>+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
>+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
>+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
>+//DCN_VM_CONTEXT15_CNTL
>+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT                                           0x1
>+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
>+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
>+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
>+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
>+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
>+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
>+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
>+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
>+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
>+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
>+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
>+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
>+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
>+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
>+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
>+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
>+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
>+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
>+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
>+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
>+//DCN_VM_DEFAULT_ADDR_MSB
>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT                                               0x0
>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT                                                    0x1c
>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT                                                  0x1d
>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK                                                 0x0000000FL
>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK                                                      0x10000000L
>+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK                                                    0x20000000L
>+//DCN_VM_DEFAULT_ADDR_LSB
>+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT                                               0x0
>+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK                                                 0xFFFFFFFFL
>+//DCN_VM_FAULT_CNTL
>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT                                                   0x0
>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT                                                    0x1
>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x2
>+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT                                                  0x8
>+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT                                                    0x9
>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK                                                     0x00000001L
>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK                                                      0x00000002L
>+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK                                                 0x00000004L
>+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK                                                    0x00000100L
>+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK                                                      0x00000200L
>+//DCN_VM_FAULT_STATUS
>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT                                                       0x0
>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT                                                         0x10
>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT                                                  0x14
>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT                                                         0x18
>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT                                             0x1f
>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK                                                         0x0000FFFFL
>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK                                                           0x000F0000L
>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK                                                    0x00300000L
>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK                                                           0x0F000000L
>+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK                                               0x80000000L
>+//DCN_VM_FAULT_ADDR_MSB
>+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT                                                   0x0
>+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK                                                     0x0000000FL
>+//DCN_VM_FAULT_ADDR_LSB
>+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT                                                   0x0
>+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK                                                     0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
>+//HUBP0_DCSURF_SURFACE_CONFIG
>+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
>+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
>+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
>+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
>+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
>+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
>+//HUBP0_DCSURF_ADDR_CONFIG
>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT                                                            0x3
>+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT                                                               0x8
>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                        0xa
>+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK                                                              0x00000038L
>+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_SE_MASK                                                                 0x00000300L
>+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                          0x00000C00L
>+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
>+//HUBP0_DCSURF_TILING_CONFIG
>+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
>+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
>+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
>+#define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT                                                         0xa
>+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
>+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
>+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
>+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
>+#define HUBP0_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK                                                           0x00000400L
>+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
>+//HUBP0_DCSURF_PRI_VIEWPORT_START
>+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
>+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
>+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
>+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
>+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
>+//HUBP0_DCSURF_PRI_VIEWPORT_START_C
>+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
>+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
>+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
>+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
>+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C
>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
>+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
>+//HUBP0_DCSURF_SEC_VIEWPORT_START
>+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
>+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
>+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
>+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
>+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION
>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
>+//HUBP0_DCSURF_SEC_VIEWPORT_START_C
>+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
>+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
>+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
>+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
>+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C
>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
>+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
>+//HUBP0_DCHUBP_REQ_SIZE_CONFIG
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
>+//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
>+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
>+//HUBP0_DCHUBP_CNTL
>+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
>+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
>+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
>+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
>+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
>+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
>+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
>+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
>+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
>+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
>+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
>+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
>+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
>+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
>+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
>+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
>+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
>+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
>+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
>+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
>+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
>+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
>+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
>+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
>+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
>+//HUBP0_HUBP_CLK_CNTL
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
>+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
>+//HUBP0_DCHUBP_VMPG_CONFIG
>+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
>+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
>+//HUBP0_HUBPREQ_DEBUG_DB
>+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
>+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
>+//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
>+//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
>+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
>+
>+
>+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
>+//HUBPREQ0_DCSURF_SURFACE_PITCH
>+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
>+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
>+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
>+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
>+//HUBPREQ0_DCSURF_SURFACE_PITCH_C
>+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
>+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
>+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
>+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
>+//HUBPREQ0_VMID_SETTINGS_0
>+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
>+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
>+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS
>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
>+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
>+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C
>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
>+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
>+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
>+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS
>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
>+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
>+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C
>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
>+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
>+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
>+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS
>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
>+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
>+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
>+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
>+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
>+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS
>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
>+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
>+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
>+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
>+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
>+//HUBPREQ0_DCSURF_SURFACE_CONTROL
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT                               0x2
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                             0x5
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT                             0xa
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                           0xd
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK                                 0x00000004L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK                               0x00000020L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK                               0x00000400L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK                             0x00002000L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
>+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
>+//HUBPREQ0_DCSURF_FLIP_CONTROL
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
>+//HUBPREQ0_DCSURF_FLIP_CONTROL2
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
>+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
>+//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
>+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
>+//HUBPREQ0_DCSURF_SURFACE_INUSE
>+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
>+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
>+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH
>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
>+//HUBPREQ0_DCSURF_SURFACE_INUSE_C
>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
>+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C
>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
>+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
>+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE
>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
>+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
>+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C
>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
>+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
>+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
>+//HUBPREQ0_DCN_EXPANSION_MODE
>+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
>+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
>+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
>+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
>+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
>+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
>+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
>+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
>+//HUBPREQ0_DCN_TTU_QOS_WM
>+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
>+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
>+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
>+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
>+//HUBPREQ0_DCN_GLOBAL_TTU_CNTL
>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
>+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
>+//HUBPREQ0_DCN_SURF0_TTU_CNTL0
>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
>+//HUBPREQ0_DCN_SURF0_TTU_CNTL1
>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
>+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
>+//HUBPREQ0_DCN_SURF1_TTU_CNTL0
>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
>+//HUBPREQ0_DCN_SURF1_TTU_CNTL1
>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
>+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
>+//HUBPREQ0_DCN_CUR0_TTU_CNTL0
>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
>+//HUBPREQ0_DCN_CUR0_TTU_CNTL1
>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
>+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
>+//HUBPREQ0_DCN_CUR1_TTU_CNTL0
>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
>+//HUBPREQ0_DCN_CUR1_TTU_CNTL1
>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
>+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
>+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
>+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
>+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
>+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
>+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
>+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
>+//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL
>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
>+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
>+//HUBPREQ0_BLANK_OFFSET_0
>+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
>+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
>+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
>+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
>+//HUBPREQ0_BLANK_OFFSET_1
>+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
>+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
>+//HUBPREQ0_DST_DIMENSIONS
>+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
>+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
>+//HUBPREQ0_DST_AFTER_SCALER
>+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
>+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
>+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
>+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
>+//HUBPREQ0_PREFETCH_SETTINGS
>+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
>+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
>+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
>+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
>+//HUBPREQ0_PREFETCH_SETTINGS_C
>+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
>+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
>+//HUBPREQ0_VBLANK_PARAMETERS_0
>+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
>+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
>+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
>+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
>+//HUBPREQ0_VBLANK_PARAMETERS_1
>+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
>+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
>+//HUBPREQ0_VBLANK_PARAMETERS_2
>+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
>+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
>+//HUBPREQ0_VBLANK_PARAMETERS_3
>+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
>+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
>+//HUBPREQ0_VBLANK_PARAMETERS_4
>+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
>+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
>+//HUBPREQ0_FLIP_PARAMETERS_0
>+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
>+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
>+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
>+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
>+//HUBPREQ0_FLIP_PARAMETERS_1
>+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
>+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
>+//HUBPREQ0_FLIP_PARAMETERS_2
>+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
>+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
>+//HUBPREQ0_NOM_PARAMETERS_0
>+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
>+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
>+//HUBPREQ0_NOM_PARAMETERS_1
>+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
>+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
>+//HUBPREQ0_NOM_PARAMETERS_2
>+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
>+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
>+//HUBPREQ0_NOM_PARAMETERS_3
>+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
>+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
>+//HUBPREQ0_NOM_PARAMETERS_4
>+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
>+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
>+//HUBPREQ0_NOM_PARAMETERS_5
>+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
>+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
>+//HUBPREQ0_NOM_PARAMETERS_6
>+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
>+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
>+//HUBPREQ0_NOM_PARAMETERS_7
>+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
>+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
>+//HUBPREQ0_PER_LINE_DELIVERY_PRE
>+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
>+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
>+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
>+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
>+//HUBPREQ0_PER_LINE_DELIVERY
>+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
>+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
>+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
>+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
>+//HUBPREQ0_CURSOR_SETTINGS
>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
>+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
>+//HUBPREQ0_REF_FREQ_TO_PIX_FREQ
>+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
>+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
>+//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT
>+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
>+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
>+//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
>+//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
>+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
>+//HUBPREQ0_VBLANK_PARAMETERS_5
>+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
>+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
>+//HUBPREQ0_VBLANK_PARAMETERS_6
>+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
>+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
>+//HUBPREQ0_FLIP_PARAMETERS_3
>+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
>+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
>+//HUBPREQ0_FLIP_PARAMETERS_4
>+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
>+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
>+//HUBPREQ0_FLIP_PARAMETERS_5
>+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
>+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
>+//HUBPREQ0_FLIP_PARAMETERS_6
>+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
>+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
>+
>+
>+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
>+//HUBPRET0_HUBPRET_CONTROL
>+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
>+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
>+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
>+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
>+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
>+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
>+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
>+//HUBPRET0_HUBPRET_MEM_PWR_CTRL
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
>+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
>+//HUBPRET0_HUBPRET_MEM_PWR_STATUS
>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
>+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
>+//HUBPRET0_HUBPRET_READ_LINE_CTRL0
>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
>+//HUBPRET0_HUBPRET_READ_LINE_CTRL1
>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
>+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
>+//HUBPRET0_HUBPRET_READ_LINE0
>+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
>+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
>+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
>+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
>+//HUBPRET0_HUBPRET_READ_LINE1
>+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
>+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
>+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
>+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
>+//HUBPRET0_HUBPRET_INTERRUPT
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
>+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
>+//HUBPRET0_HUBPRET_READ_LINE_VALUE
>+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
>+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
>+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
>+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
>+//HUBPRET0_HUBPRET_READ_LINE_STATUS
>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
>+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
>+
>+
>+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
>+//CURSOR0_0_CURSOR_CONTROL
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT                                                         0xd
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT                                                        0xe
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SNOOP_MASK                                                           0x00002000L
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_SYSTEM_MASK                                                          0x00004000L
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
>+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
>+//CURSOR0_0_CURSOR_SURFACE_ADDRESS
>+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
>+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
>+//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH
>+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
>+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
>+//CURSOR0_0_CURSOR_SIZE
>+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
>+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
>+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
>+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
>+//CURSOR0_0_CURSOR_POSITION
>+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
>+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
>+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
>+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
>+//CURSOR0_0_CURSOR_HOT_SPOT
>+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
>+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
>+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
>+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
>+//CURSOR0_0_CURSOR_STEREO_CONTROL
>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
>+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
>+//CURSOR0_0_CURSOR_DST_OFFSET
>+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
>+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
>+//CURSOR0_0_CURSOR_MEM_PWR_CTRL
>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
>+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
>+//CURSOR0_0_CURSOR_MEM_PWR_STATUS
>+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
>+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
>+//CURSOR0_0_DMDATA_ADDRESS_HIGH
>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT                                                   0x1c
>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT                                                    0x1d
>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK                                                     0x10000000L
>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK                                                      0x20000000L
>+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
>+//CURSOR0_0_DMDATA_ADDRESS_LOW
>+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
>+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
>+//CURSOR0_0_DMDATA_CNTL
>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
>+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
>+//CURSOR0_0_DMDATA_QOS_CNTL
>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
>+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
>+//CURSOR0_0_DMDATA_STATUS
>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
>+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
>+//CURSOR0_0_DMDATA_SW_CNTL
>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
>+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
>+//CURSOR0_0_DMDATA_SW_DATA
>+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
>+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON7_PERFCOUNTER_CNTL
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
>+//DC_PERFMON7_PERFCOUNTER_CNTL2
>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
>+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
>+//DC_PERFMON7_PERFCOUNTER_STATE
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
>+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
>+//DC_PERFMON7_PERFMON_CNTL
>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
>+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
>+//DC_PERFMON7_PERFMON_CNTL2
>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
>+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
>+//DC_PERFMON7_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
>+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
>+//DC_PERFMON7_PERFMON_CVALUE_LOW
>+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
>+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
>+//DC_PERFMON7_PERFMON_HI
>+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
>+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
>+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
>+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
>+//DC_PERFMON7_PERFMON_LOW
>+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
>+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
>+//HUBP1_DCSURF_SURFACE_CONFIG
>+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
>+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
>+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
>+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
>+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
>+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
>+//HUBP1_DCSURF_ADDR_CONFIG
>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT                                                            0x3
>+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT                                                               0x8
>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                        0xa
>+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK                                                              0x00000038L
>+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_SE_MASK                                                                 0x00000300L
>+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                          0x00000C00L
>+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
>+//HUBP1_DCSURF_TILING_CONFIG
>+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
>+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
>+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
>+#define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT                                                         0xa
>+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
>+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
>+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
>+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
>+#define HUBP1_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK                                                           0x00000400L
>+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
>+//HUBP1_DCSURF_PRI_VIEWPORT_START
>+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
>+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
>+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
>+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
>+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION
>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
>+//HUBP1_DCSURF_PRI_VIEWPORT_START_C
>+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
>+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
>+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
>+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
>+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C
>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
>+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
>+//HUBP1_DCSURF_SEC_VIEWPORT_START
>+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
>+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
>+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
>+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
>+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION
>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
>+//HUBP1_DCSURF_SEC_VIEWPORT_START_C
>+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
>+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
>+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
>+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
>+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C
>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
>+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
>+//HUBP1_DCHUBP_REQ_SIZE_CONFIG
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
>+//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
>+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
>+//HUBP1_DCHUBP_CNTL
>+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
>+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
>+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
>+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
>+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
>+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
>+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
>+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
>+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
>+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
>+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
>+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
>+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
>+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
>+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
>+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
>+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
>+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
>+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
>+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
>+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
>+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
>+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
>+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
>+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
>+//HUBP1_HUBP_CLK_CNTL
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
>+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
>+//HUBP1_DCHUBP_VMPG_CONFIG
>+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
>+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
>+//HUBP1_HUBPREQ_DEBUG_DB
>+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
>+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
>+//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
>+//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
>+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
>+
>+
>+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
>+//HUBPREQ1_DCSURF_SURFACE_PITCH
>+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
>+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
>+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
>+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
>+//HUBPREQ1_DCSURF_SURFACE_PITCH_C
>+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
>+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
>+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
>+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
>+//HUBPREQ1_VMID_SETTINGS_0
>+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
>+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
>+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS
>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
>+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
>+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C
>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
>+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
>+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
>+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS
>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
>+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
>+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C
>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
>+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
>+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
>+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS
>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
>+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
>+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
>+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
>+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
>+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS
>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
>+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
>+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
>+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
>+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
>+//HUBPREQ1_DCSURF_SURFACE_CONTROL
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT                               0x2
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                             0x5
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT                             0xa
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                           0xd
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK                                 0x00000004L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK                               0x00000020L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK                               0x00000400L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK                             0x00002000L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
>+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
>+//HUBPREQ1_DCSURF_FLIP_CONTROL
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
>+//HUBPREQ1_DCSURF_FLIP_CONTROL2
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
>+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
>+//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
>+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
>+//HUBPREQ1_DCSURF_SURFACE_INUSE
>+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
>+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
>+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH
>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
>+//HUBPREQ1_DCSURF_SURFACE_INUSE_C
>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
>+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C
>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
>+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
>+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE
>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
>+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
>+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C
>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
>+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
>+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
>+//HUBPREQ1_DCN_EXPANSION_MODE
>+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
>+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
>+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
>+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
>+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
>+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
>+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
>+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
>+//HUBPREQ1_DCN_TTU_QOS_WM
>+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
>+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
>+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
>+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
>+//HUBPREQ1_DCN_GLOBAL_TTU_CNTL
>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
>+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
>+//HUBPREQ1_DCN_SURF0_TTU_CNTL0
>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
>+//HUBPREQ1_DCN_SURF0_TTU_CNTL1
>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
>+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
>+//HUBPREQ1_DCN_SURF1_TTU_CNTL0
>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
>+//HUBPREQ1_DCN_SURF1_TTU_CNTL1
>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
>+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
>+//HUBPREQ1_DCN_CUR0_TTU_CNTL0
>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
>+//HUBPREQ1_DCN_CUR0_TTU_CNTL1
>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
>+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
>+//HUBPREQ1_DCN_CUR1_TTU_CNTL0
>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
>+//HUBPREQ1_DCN_CUR1_TTU_CNTL1
>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
>+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
>+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
>+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
>+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
>+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
>+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
>+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
>+//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL
>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
>+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
>+//HUBPREQ1_BLANK_OFFSET_0
>+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
>+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
>+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
>+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
>+//HUBPREQ1_BLANK_OFFSET_1
>+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
>+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
>+//HUBPREQ1_DST_DIMENSIONS
>+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
>+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
>+//HUBPREQ1_DST_AFTER_SCALER
>+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
>+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
>+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
>+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
>+//HUBPREQ1_PREFETCH_SETTINGS
>+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
>+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
>+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
>+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
>+//HUBPREQ1_PREFETCH_SETTINGS_C
>+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
>+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
>+//HUBPREQ1_VBLANK_PARAMETERS_0
>+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
>+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
>+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
>+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
>+//HUBPREQ1_VBLANK_PARAMETERS_1
>+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
>+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
>+//HUBPREQ1_VBLANK_PARAMETERS_2
>+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
>+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
>+//HUBPREQ1_VBLANK_PARAMETERS_3
>+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
>+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
>+//HUBPREQ1_VBLANK_PARAMETERS_4
>+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
>+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
>+//HUBPREQ1_FLIP_PARAMETERS_0
>+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
>+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
>+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
>+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
>+//HUBPREQ1_FLIP_PARAMETERS_1
>+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
>+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
>+//HUBPREQ1_FLIP_PARAMETERS_2
>+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
>+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
>+//HUBPREQ1_NOM_PARAMETERS_0
>+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
>+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
>+//HUBPREQ1_NOM_PARAMETERS_1
>+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
>+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
>+//HUBPREQ1_NOM_PARAMETERS_2
>+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
>+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
>+//HUBPREQ1_NOM_PARAMETERS_3
>+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
>+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
>+//HUBPREQ1_NOM_PARAMETERS_4
>+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
>+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
>+//HUBPREQ1_NOM_PARAMETERS_5
>+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
>+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
>+//HUBPREQ1_NOM_PARAMETERS_6
>+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
>+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
>+//HUBPREQ1_NOM_PARAMETERS_7
>+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
>+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
>+//HUBPREQ1_PER_LINE_DELIVERY_PRE
>+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
>+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
>+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
>+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
>+//HUBPREQ1_PER_LINE_DELIVERY
>+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
>+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
>+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
>+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
>+//HUBPREQ1_CURSOR_SETTINGS
>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
>+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
>+//HUBPREQ1_REF_FREQ_TO_PIX_FREQ
>+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
>+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
>+//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT
>+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
>+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
>+//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
>+//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
>+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
>+//HUBPREQ1_VBLANK_PARAMETERS_5
>+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
>+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
>+//HUBPREQ1_VBLANK_PARAMETERS_6
>+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
>+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
>+//HUBPREQ1_FLIP_PARAMETERS_3
>+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
>+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
>+//HUBPREQ1_FLIP_PARAMETERS_4
>+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
>+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
>+//HUBPREQ1_FLIP_PARAMETERS_5
>+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
>+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
>+//HUBPREQ1_FLIP_PARAMETERS_6
>+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
>+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
>+
>+
>+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
>+//HUBPRET1_HUBPRET_CONTROL
>+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
>+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
>+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
>+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
>+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
>+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
>+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
>+//HUBPRET1_HUBPRET_MEM_PWR_CTRL
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
>+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
>+//HUBPRET1_HUBPRET_MEM_PWR_STATUS
>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
>+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
>+//HUBPRET1_HUBPRET_READ_LINE_CTRL0
>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
>+//HUBPRET1_HUBPRET_READ_LINE_CTRL1
>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
>+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
>+//HUBPRET1_HUBPRET_READ_LINE0
>+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
>+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
>+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
>+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
>+//HUBPRET1_HUBPRET_READ_LINE1
>+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
>+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
>+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
>+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
>+//HUBPRET1_HUBPRET_INTERRUPT
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
>+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
>+//HUBPRET1_HUBPRET_READ_LINE_VALUE
>+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
>+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
>+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
>+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
>+//HUBPRET1_HUBPRET_READ_LINE_STATUS
>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
>+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
>+
>+
>+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
>+//CURSOR0_1_CURSOR_CONTROL
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT                                                         0xd
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT                                                        0xe
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SNOOP_MASK                                                           0x00002000L
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_SYSTEM_MASK                                                          0x00004000L
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
>+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
>+//CURSOR0_1_CURSOR_SURFACE_ADDRESS
>+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
>+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
>+//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH
>+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
>+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
>+//CURSOR0_1_CURSOR_SIZE
>+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
>+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
>+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
>+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
>+//CURSOR0_1_CURSOR_POSITION
>+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
>+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
>+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
>+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
>+//CURSOR0_1_CURSOR_HOT_SPOT
>+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
>+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
>+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
>+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
>+//CURSOR0_1_CURSOR_STEREO_CONTROL
>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
>+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
>+//CURSOR0_1_CURSOR_DST_OFFSET
>+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
>+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
>+//CURSOR0_1_CURSOR_MEM_PWR_CTRL
>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
>+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
>+//CURSOR0_1_CURSOR_MEM_PWR_STATUS
>+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
>+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
>+//CURSOR0_1_DMDATA_ADDRESS_HIGH
>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT                                                   0x1c
>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT                                                    0x1d
>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK                                                     0x10000000L
>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK                                                      0x20000000L
>+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
>+//CURSOR0_1_DMDATA_ADDRESS_LOW
>+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
>+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
>+//CURSOR0_1_DMDATA_CNTL
>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
>+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
>+//CURSOR0_1_DMDATA_QOS_CNTL
>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
>+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
>+//CURSOR0_1_DMDATA_STATUS
>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
>+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
>+//CURSOR0_1_DMDATA_SW_CNTL
>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
>+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
>+//CURSOR0_1_DMDATA_SW_DATA
>+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
>+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON8_PERFCOUNTER_CNTL
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
>+//DC_PERFMON8_PERFCOUNTER_CNTL2
>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
>+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
>+//DC_PERFMON8_PERFCOUNTER_STATE
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
>+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
>+//DC_PERFMON8_PERFMON_CNTL
>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
>+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
>+//DC_PERFMON8_PERFMON_CNTL2
>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
>+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
>+//DC_PERFMON8_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
>+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
>+//DC_PERFMON8_PERFMON_CVALUE_LOW
>+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
>+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
>+//DC_PERFMON8_PERFMON_HI
>+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
>+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
>+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
>+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
>+//DC_PERFMON8_PERFMON_LOW
>+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
>+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
>+//HUBP2_DCSURF_SURFACE_CONFIG
>+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
>+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
>+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
>+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
>+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
>+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
>+//HUBP2_DCSURF_ADDR_CONFIG
>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT                                                            0x3
>+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT                                                               0x8
>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                        0xa
>+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK                                                              0x00000038L
>+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_SE_MASK                                                                 0x00000300L
>+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                          0x00000C00L
>+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
>+//HUBP2_DCSURF_TILING_CONFIG
>+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
>+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
>+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
>+#define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT                                                         0xa
>+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
>+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
>+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
>+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
>+#define HUBP2_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK                                                           0x00000400L
>+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
>+//HUBP2_DCSURF_PRI_VIEWPORT_START
>+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
>+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
>+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
>+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
>+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION
>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
>+//HUBP2_DCSURF_PRI_VIEWPORT_START_C
>+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
>+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
>+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
>+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
>+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C
>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
>+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
>+//HUBP2_DCSURF_SEC_VIEWPORT_START
>+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
>+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
>+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
>+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
>+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION
>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
>+//HUBP2_DCSURF_SEC_VIEWPORT_START_C
>+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
>+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
>+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
>+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
>+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C
>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
>+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
>+//HUBP2_DCHUBP_REQ_SIZE_CONFIG
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
>+//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
>+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
>+//HUBP2_DCHUBP_CNTL
>+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
>+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
>+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
>+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
>+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
>+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
>+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
>+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
>+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
>+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
>+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
>+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
>+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
>+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
>+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
>+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
>+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
>+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
>+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
>+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
>+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
>+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
>+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
>+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
>+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
>+//HUBP2_HUBP_CLK_CNTL
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
>+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
>+//HUBP2_DCHUBP_VMPG_CONFIG
>+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
>+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
>+//HUBP2_HUBPREQ_DEBUG_DB
>+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
>+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
>+//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
>+//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
>+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
>+
>+
>+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
>+//HUBPREQ2_DCSURF_SURFACE_PITCH
>+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
>+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
>+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
>+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
>+//HUBPREQ2_DCSURF_SURFACE_PITCH_C
>+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
>+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
>+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
>+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
>+//HUBPREQ2_VMID_SETTINGS_0
>+#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
>+#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
>+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS
>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
>+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
>+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C
>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
>+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
>+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
>+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS
>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
>+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
>+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C
>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
>+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
>+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
>+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS
>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
>+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
>+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
>+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
>+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
>+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS
>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
>+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
>+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
>+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
>+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
>+//HUBPREQ2_DCSURF_SURFACE_CONTROL
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT                               0x2
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                             0x5
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT                             0xa
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                           0xd
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK                                 0x00000004L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK                               0x00000020L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK                               0x00000400L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK                             0x00002000L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
>+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
>+//HUBPREQ2_DCSURF_FLIP_CONTROL
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
>+//HUBPREQ2_DCSURF_FLIP_CONTROL2
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
>+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
>+//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
>+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
>+//HUBPREQ2_DCSURF_SURFACE_INUSE
>+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
>+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
>+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH
>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
>+//HUBPREQ2_DCSURF_SURFACE_INUSE_C
>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
>+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C
>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
>+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
>+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE
>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
>+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
>+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C
>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
>+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
>+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
>+//HUBPREQ2_DCN_EXPANSION_MODE
>+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
>+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
>+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
>+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
>+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
>+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
>+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
>+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
>+//HUBPREQ2_DCN_TTU_QOS_WM
>+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
>+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
>+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
>+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
>+//HUBPREQ2_DCN_GLOBAL_TTU_CNTL
>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
>+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
>+//HUBPREQ2_DCN_SURF0_TTU_CNTL0
>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
>+//HUBPREQ2_DCN_SURF0_TTU_CNTL1
>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
>+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
>+//HUBPREQ2_DCN_SURF1_TTU_CNTL0
>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
>+//HUBPREQ2_DCN_SURF1_TTU_CNTL1
>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
>+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
>+//HUBPREQ2_DCN_CUR0_TTU_CNTL0
>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
>+//HUBPREQ2_DCN_CUR0_TTU_CNTL1
>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
>+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
>+//HUBPREQ2_DCN_CUR1_TTU_CNTL0
>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
>+//HUBPREQ2_DCN_CUR1_TTU_CNTL1
>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
>+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
>+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
>+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
>+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
>+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
>+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
>+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
>+//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL
>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
>+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
>+//HUBPREQ2_BLANK_OFFSET_0
>+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
>+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
>+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
>+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
>+//HUBPREQ2_BLANK_OFFSET_1
>+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
>+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
>+//HUBPREQ2_DST_DIMENSIONS
>+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
>+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
>+//HUBPREQ2_DST_AFTER_SCALER
>+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
>+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
>+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
>+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
>+//HUBPREQ2_PREFETCH_SETTINGS
>+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
>+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
>+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
>+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
>+//HUBPREQ2_PREFETCH_SETTINGS_C
>+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
>+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
>+//HUBPREQ2_VBLANK_PARAMETERS_0
>+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
>+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
>+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
>+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
>+//HUBPREQ2_VBLANK_PARAMETERS_1
>+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
>+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
>+//HUBPREQ2_VBLANK_PARAMETERS_2
>+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
>+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
>+//HUBPREQ2_VBLANK_PARAMETERS_3
>+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
>+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
>+//HUBPREQ2_VBLANK_PARAMETERS_4
>+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
>+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
>+//HUBPREQ2_FLIP_PARAMETERS_0
>+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
>+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
>+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
>+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
>+//HUBPREQ2_FLIP_PARAMETERS_1
>+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
>+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
>+//HUBPREQ2_FLIP_PARAMETERS_2
>+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
>+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
>+//HUBPREQ2_NOM_PARAMETERS_0
>+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
>+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
>+//HUBPREQ2_NOM_PARAMETERS_1
>+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
>+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
>+//HUBPREQ2_NOM_PARAMETERS_2
>+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
>+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
>+//HUBPREQ2_NOM_PARAMETERS_3
>+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
>+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
>+//HUBPREQ2_NOM_PARAMETERS_4
>+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
>+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
>+//HUBPREQ2_NOM_PARAMETERS_5
>+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
>+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
>+//HUBPREQ2_NOM_PARAMETERS_6
>+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
>+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
>+//HUBPREQ2_NOM_PARAMETERS_7
>+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
>+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
>+//HUBPREQ2_PER_LINE_DELIVERY_PRE
>+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
>+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
>+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
>+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
>+//HUBPREQ2_PER_LINE_DELIVERY
>+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
>+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
>+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
>+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
>+//HUBPREQ2_CURSOR_SETTINGS
>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
>+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
>+//HUBPREQ2_REF_FREQ_TO_PIX_FREQ
>+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
>+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
>+//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT
>+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
>+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
>+//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
>+//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
>+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
>+//HUBPREQ2_VBLANK_PARAMETERS_5
>+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
>+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
>+//HUBPREQ2_VBLANK_PARAMETERS_6
>+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
>+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
>+//HUBPREQ2_FLIP_PARAMETERS_3
>+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
>+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
>+//HUBPREQ2_FLIP_PARAMETERS_4
>+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
>+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
>+//HUBPREQ2_FLIP_PARAMETERS_5
>+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
>+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
>+//HUBPREQ2_FLIP_PARAMETERS_6
>+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
>+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
>+
>+
>+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
>+//HUBPRET2_HUBPRET_CONTROL
>+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
>+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
>+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
>+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
>+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
>+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
>+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
>+//HUBPRET2_HUBPRET_MEM_PWR_CTRL
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
>+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
>+//HUBPRET2_HUBPRET_MEM_PWR_STATUS
>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
>+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
>+//HUBPRET2_HUBPRET_READ_LINE_CTRL0
>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
>+//HUBPRET2_HUBPRET_READ_LINE_CTRL1
>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
>+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
>+//HUBPRET2_HUBPRET_READ_LINE0
>+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
>+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
>+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
>+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
>+//HUBPRET2_HUBPRET_READ_LINE1
>+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
>+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
>+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
>+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
>+//HUBPRET2_HUBPRET_INTERRUPT
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
>+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
>+//HUBPRET2_HUBPRET_READ_LINE_VALUE
>+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
>+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
>+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
>+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
>+//HUBPRET2_HUBPRET_READ_LINE_STATUS
>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
>+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
>+
>+
>+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
>+//CURSOR0_2_CURSOR_CONTROL
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT                                                         0xd
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT                                                        0xe
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SNOOP_MASK                                                           0x00002000L
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_SYSTEM_MASK                                                          0x00004000L
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
>+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
>+//CURSOR0_2_CURSOR_SURFACE_ADDRESS
>+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
>+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
>+//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH
>+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
>+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
>+//CURSOR0_2_CURSOR_SIZE
>+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
>+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
>+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
>+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
>+//CURSOR0_2_CURSOR_POSITION
>+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
>+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
>+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
>+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
>+//CURSOR0_2_CURSOR_HOT_SPOT
>+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
>+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
>+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
>+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
>+//CURSOR0_2_CURSOR_STEREO_CONTROL
>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
>+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
>+//CURSOR0_2_CURSOR_DST_OFFSET
>+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
>+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
>+//CURSOR0_2_CURSOR_MEM_PWR_CTRL
>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
>+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
>+//CURSOR0_2_CURSOR_MEM_PWR_STATUS
>+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
>+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
>+//CURSOR0_2_DMDATA_ADDRESS_HIGH
>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT                                                   0x1c
>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT                                                    0x1d
>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK                                                     0x10000000L
>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK                                                      0x20000000L
>+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
>+//CURSOR0_2_DMDATA_ADDRESS_LOW
>+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
>+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
>+//CURSOR0_2_DMDATA_CNTL
>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
>+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
>+//CURSOR0_2_DMDATA_QOS_CNTL
>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
>+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
>+//CURSOR0_2_DMDATA_STATUS
>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
>+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
>+//CURSOR0_2_DMDATA_SW_CNTL
>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
>+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
>+//CURSOR0_2_DMDATA_SW_DATA
>+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
>+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON9_PERFCOUNTER_CNTL
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
>+//DC_PERFMON9_PERFCOUNTER_CNTL2
>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
>+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
>+//DC_PERFMON9_PERFCOUNTER_STATE
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
>+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
>+//DC_PERFMON9_PERFMON_CNTL
>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
>+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
>+//DC_PERFMON9_PERFMON_CNTL2
>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
>+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
>+//DC_PERFMON9_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
>+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
>+//DC_PERFMON9_PERFMON_CVALUE_LOW
>+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
>+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
>+//DC_PERFMON9_PERFMON_HI
>+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
>+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
>+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
>+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
>+//DC_PERFMON9_PERFMON_LOW
>+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
>+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
>+//HUBP3_DCSURF_SURFACE_CONFIG
>+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
>+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
>+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
>+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
>+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
>+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
>+//HUBP3_DCSURF_ADDR_CONFIG
>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS__SHIFT                                                            0x3
>+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE__SHIFT                                                               0x8
>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT                                                        0xa
>+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_BANKS_MASK                                                              0x00000038L
>+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_SE_MASK                                                                 0x00000300L
>+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_RB_PER_SE_MASK                                                          0x00000C00L
>+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
>+//HUBP3_DCSURF_TILING_CONFIG
>+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
>+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
>+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
>+#define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED__SHIFT                                                         0xa
>+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
>+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
>+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
>+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
>+#define HUBP3_DCSURF_TILING_CONFIG__RB_ALIGNED_MASK                                                           0x00000400L
>+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
>+//HUBP3_DCSURF_PRI_VIEWPORT_START
>+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
>+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
>+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
>+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
>+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION
>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
>+//HUBP3_DCSURF_PRI_VIEWPORT_START_C
>+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
>+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
>+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
>+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
>+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C
>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
>+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
>+//HUBP3_DCSURF_SEC_VIEWPORT_START
>+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
>+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
>+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
>+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
>+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION
>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
>+//HUBP3_DCSURF_SEC_VIEWPORT_START_C
>+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
>+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
>+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
>+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
>+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C
>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
>+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
>+//HUBP3_DCHUBP_REQ_SIZE_CONFIG
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
>+//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
>+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
>+//HUBP3_DCHUBP_CNTL
>+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
>+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
>+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE__SHIFT                                                                0x2
>+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
>+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
>+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
>+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
>+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
>+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
>+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
>+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
>+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
>+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
>+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
>+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_MASK                                                                  0x00000004L
>+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
>+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
>+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
>+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
>+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
>+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
>+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
>+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
>+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
>+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
>+//HUBP3_HUBP_CLK_CNTL
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
>+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
>+//HUBP3_DCHUBP_VMPG_CONFIG
>+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
>+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
>+//HUBP3_HUBPREQ_DEBUG_DB
>+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
>+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
>+//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
>+//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
>+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
>+
>+
>+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
>+//HUBPREQ3_DCSURF_SURFACE_PITCH
>+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
>+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
>+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
>+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
>+//HUBPREQ3_DCSURF_SURFACE_PITCH_C
>+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
>+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
>+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
>+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
>+//HUBPREQ3_VMID_SETTINGS_0
>+#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
>+#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
>+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS
>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
>+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
>+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C
>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
>+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
>+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
>+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS
>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
>+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
>+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C
>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
>+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
>+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
>+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS
>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
>+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
>+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
>+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
>+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
>+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS
>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
>+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
>+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
>+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
>+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
>+//HUBPREQ3_DCSURF_SURFACE_CONTROL
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK__SHIFT                               0x2
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                             0x5
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK__SHIFT                             0xa
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C__SHIFT                           0xd
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_MASK                                 0x00000004L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_64B_BLK_C_MASK                               0x00000020L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_MASK                               0x00000400L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_64B_BLK_C_MASK                             0x00002000L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
>+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
>+//HUBPREQ3_DCSURF_FLIP_CONTROL
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
>+//HUBPREQ3_DCSURF_FLIP_CONTROL2
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
>+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
>+//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
>+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
>+//HUBPREQ3_DCSURF_SURFACE_INUSE
>+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
>+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
>+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH
>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
>+//HUBPREQ3_DCSURF_SURFACE_INUSE_C
>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
>+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C
>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
>+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
>+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE
>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
>+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
>+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C
>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
>+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
>+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
>+//HUBPREQ3_DCN_EXPANSION_MODE
>+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
>+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
>+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
>+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
>+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
>+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
>+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
>+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
>+//HUBPREQ3_DCN_TTU_QOS_WM
>+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
>+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
>+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
>+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
>+//HUBPREQ3_DCN_GLOBAL_TTU_CNTL
>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
>+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
>+//HUBPREQ3_DCN_SURF0_TTU_CNTL0
>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
>+//HUBPREQ3_DCN_SURF0_TTU_CNTL1
>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
>+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
>+//HUBPREQ3_DCN_SURF1_TTU_CNTL0
>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
>+//HUBPREQ3_DCN_SURF1_TTU_CNTL1
>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
>+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
>+//HUBPREQ3_DCN_CUR0_TTU_CNTL0
>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
>+//HUBPREQ3_DCN_CUR0_TTU_CNTL1
>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
>+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
>+//HUBPREQ3_DCN_CUR1_TTU_CNTL0
>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
>+//HUBPREQ3_DCN_CUR1_TTU_CNTL1
>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
>+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
>+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
>+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
>+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
>+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
>+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
>+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
>+//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL
>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
>+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
>+//HUBPREQ3_BLANK_OFFSET_0
>+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
>+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
>+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
>+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
>+//HUBPREQ3_BLANK_OFFSET_1
>+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
>+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
>+//HUBPREQ3_DST_DIMENSIONS
>+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
>+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
>+//HUBPREQ3_DST_AFTER_SCALER
>+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
>+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
>+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
>+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
>+//HUBPREQ3_PREFETCH_SETTINGS
>+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
>+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
>+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
>+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
>+//HUBPREQ3_PREFETCH_SETTINGS_C
>+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
>+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
>+//HUBPREQ3_VBLANK_PARAMETERS_0
>+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
>+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
>+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
>+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
>+//HUBPREQ3_VBLANK_PARAMETERS_1
>+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
>+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
>+//HUBPREQ3_VBLANK_PARAMETERS_2
>+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
>+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
>+//HUBPREQ3_VBLANK_PARAMETERS_3
>+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
>+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
>+//HUBPREQ3_VBLANK_PARAMETERS_4
>+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
>+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
>+//HUBPREQ3_FLIP_PARAMETERS_0
>+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
>+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
>+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
>+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
>+//HUBPREQ3_FLIP_PARAMETERS_1
>+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
>+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
>+//HUBPREQ3_FLIP_PARAMETERS_2
>+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
>+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
>+//HUBPREQ3_NOM_PARAMETERS_0
>+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
>+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
>+//HUBPREQ3_NOM_PARAMETERS_1
>+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
>+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
>+//HUBPREQ3_NOM_PARAMETERS_2
>+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
>+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
>+//HUBPREQ3_NOM_PARAMETERS_3
>+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
>+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
>+//HUBPREQ3_NOM_PARAMETERS_4
>+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
>+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
>+//HUBPREQ3_NOM_PARAMETERS_5
>+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
>+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
>+//HUBPREQ3_NOM_PARAMETERS_6
>+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
>+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
>+//HUBPREQ3_NOM_PARAMETERS_7
>+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
>+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
>+//HUBPREQ3_PER_LINE_DELIVERY_PRE
>+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
>+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
>+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
>+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
>+//HUBPREQ3_PER_LINE_DELIVERY
>+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
>+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
>+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
>+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
>+//HUBPREQ3_CURSOR_SETTINGS
>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
>+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
>+//HUBPREQ3_REF_FREQ_TO_PIX_FREQ
>+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
>+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
>+//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT
>+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
>+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
>+//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
>+//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
>+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
>+//HUBPREQ3_VBLANK_PARAMETERS_5
>+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
>+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
>+//HUBPREQ3_VBLANK_PARAMETERS_6
>+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
>+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
>+//HUBPREQ3_FLIP_PARAMETERS_3
>+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
>+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
>+//HUBPREQ3_FLIP_PARAMETERS_4
>+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
>+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
>+//HUBPREQ3_FLIP_PARAMETERS_5
>+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
>+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
>+//HUBPREQ3_FLIP_PARAMETERS_6
>+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
>+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
>+
>+
>+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
>+//HUBPRET3_HUBPRET_CONTROL
>+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x0
>+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xc
>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
>+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
>+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00000FFFL
>+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00001000L
>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
>+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
>+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
>+//HUBPRET3_HUBPRET_MEM_PWR_CTRL
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE__SHIFT                                               0x0
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS__SHIFT                                                 0x2
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                             0x4
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_FORCE_MASK                                                 0x00000003L
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_DIS_MASK                                                   0x00000004L
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DET_MEM_PWR_LS_MODE_MASK                                               0x00000030L
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
>+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
>+//HUBPRET3_HUBPRET_MEM_PWR_STATUS
>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE__SHIFT                                             0x0
>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DET_MEM_PWR_STATE_MASK                                               0x00000003L
>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
>+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
>+//HUBPRET3_HUBPRET_READ_LINE_CTRL0
>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT                                0x10
>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK                                  0x3FFF0000L
>+//HUBPRET3_HUBPRET_READ_LINE_CTRL1
>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
>+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
>+//HUBPRET3_HUBPRET_READ_LINE0
>+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
>+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
>+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
>+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
>+//HUBPRET3_HUBPRET_READ_LINE1
>+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
>+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
>+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
>+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
>+//HUBPRET3_HUBPRET_INTERRUPT
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
>+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
>+//HUBPRET3_HUBPRET_READ_LINE_VALUE
>+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
>+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
>+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
>+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
>+//HUBPRET3_HUBPRET_READ_LINE_STATUS
>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
>+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
>+
>+
>+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
>+//CURSOR0_3_CURSOR_CONTROL
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SNOOP__SHIFT                                                         0xd
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SYSTEM__SHIFT                                                        0xe
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SNOOP_MASK                                                           0x00002000L
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_SYSTEM_MASK                                                          0x00004000L
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
>+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
>+//CURSOR0_3_CURSOR_SURFACE_ADDRESS
>+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
>+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
>+//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH
>+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
>+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
>+//CURSOR0_3_CURSOR_SIZE
>+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
>+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
>+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
>+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
>+//CURSOR0_3_CURSOR_POSITION
>+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
>+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
>+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
>+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
>+//CURSOR0_3_CURSOR_HOT_SPOT
>+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
>+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
>+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
>+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
>+//CURSOR0_3_CURSOR_STEREO_CONTROL
>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
>+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
>+//CURSOR0_3_CURSOR_DST_OFFSET
>+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
>+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
>+//CURSOR0_3_CURSOR_MEM_PWR_CTRL
>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
>+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
>+//CURSOR0_3_CURSOR_MEM_PWR_STATUS
>+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
>+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
>+//CURSOR0_3_DMDATA_ADDRESS_HIGH
>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM__SHIFT                                                   0x1c
>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP__SHIFT                                                    0x1d
>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SYSTEM_MASK                                                     0x10000000L
>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_SNOOP_MASK                                                      0x20000000L
>+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
>+//CURSOR0_3_DMDATA_ADDRESS_LOW
>+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
>+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
>+//CURSOR0_3_DMDATA_CNTL
>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
>+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
>+//CURSOR0_3_DMDATA_QOS_CNTL
>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
>+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
>+//CURSOR0_3_DMDATA_STATUS
>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
>+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
>+//CURSOR0_3_DMDATA_SW_CNTL
>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
>+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
>+//CURSOR0_3_DMDATA_SW_DATA
>+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
>+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON10_PERFCOUNTER_CNTL
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON10_PERFCOUNTER_CNTL2
>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON10_PERFCOUNTER_STATE
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON10_PERFMON_CNTL
>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON10_PERFMON_CNTL2
>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON10_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON10_PERFMON_CVALUE_LOW
>+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON10_PERFMON_HI
>+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON10_PERFMON_LOW
>+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
>+//DPP_TOP0_DPP_CONTROL
>+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT                                         0xe
>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0x10
>+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x12
>+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x14
>+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
>+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK                                           0x00004000L
>+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00010000L
>+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00040000L
>+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00100000L
>+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0xF0000000L
>+//DPP_TOP0_DPP_SOFT_RESET
>+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
>+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
>+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
>+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
>+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
>+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
>+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
>+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
>+//DPP_TOP0_DPP_CRC_VAL_R_G
>+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
>+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
>+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
>+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
>+//DPP_TOP0_DPP_CRC_VAL_B_A
>+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
>+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
>+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
>+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
>+//DPP_TOP0_DPP_CRC_CTRL
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT                                                 0x6
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x7
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x8
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0xa
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xc
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xf
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK                                                   0x00000040L
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000080L
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000300L
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000C00L
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00007000L
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x00008000L
>+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
>+//DPP_TOP0_HOST_READ_CONTROL
>+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
>+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
>+
>+
>+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
>+//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT
>+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
>+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
>+//CNVC_CFG0_FORMAT_CONTROL
>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
>+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
>+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
>+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
>+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
>+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
>+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
>+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
>+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
>+//CNVC_CFG0_FCNV_FP_BIAS_R
>+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
>+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
>+//CNVC_CFG0_FCNV_FP_BIAS_G
>+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
>+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
>+//CNVC_CFG0_FCNV_FP_BIAS_B
>+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
>+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
>+//CNVC_CFG0_FCNV_FP_SCALE_R
>+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
>+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
>+//CNVC_CFG0_FCNV_FP_SCALE_G
>+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
>+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
>+//CNVC_CFG0_FCNV_FP_SCALE_B
>+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
>+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
>+//CNVC_CFG0_COLOR_KEYER_CONTROL
>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
>+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
>+//CNVC_CFG0_COLOR_KEYER_ALPHA
>+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
>+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
>+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
>+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
>+//CNVC_CFG0_COLOR_KEYER_RED
>+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
>+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
>+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
>+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
>+//CNVC_CFG0_COLOR_KEYER_GREEN
>+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
>+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
>+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
>+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
>+//CNVC_CFG0_COLOR_KEYER_BLUE
>+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
>+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
>+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
>+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
>+//CNVC_CFG0_ALPHA_2BIT_LUT
>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
>+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
>+
>+
>+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
>+//CNVC_CUR0_CURSOR0_CONTROL
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
>+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
>+//CNVC_CUR0_CURSOR0_COLOR0
>+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
>+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
>+//CNVC_CUR0_CURSOR0_COLOR1
>+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
>+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
>+//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS
>+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
>+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
>+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
>+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
>+//DSCL0_SCL_COEF_RAM_TAP_SELECT
>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
>+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
>+//DSCL0_SCL_COEF_RAM_TAP_DATA
>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
>+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
>+//DSCL0_SCL_MODE
>+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
>+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
>+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
>+#define DSCL0_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
>+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
>+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
>+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
>+//DSCL0_SCL_TAP_CONTROL
>+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
>+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
>+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
>+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
>+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
>+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
>+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
>+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
>+//DSCL0_DSCL_CONTROL
>+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
>+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
>+//DSCL0_DSCL_2TAP_CONTROL
>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
>+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
>+//DSCL0_SCL_MANUAL_REPLICATE_CONTROL
>+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
>+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
>+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
>+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
>+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO
>+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
>+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x03FFFFFFL
>+//DSCL0_SCL_HORZ_FILTER_INIT
>+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
>+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
>+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
>+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
>+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C
>+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
>+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
>+//DSCL0_SCL_HORZ_FILTER_INIT_C
>+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
>+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
>+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
>+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
>+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO
>+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
>+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x03FFFFFFL
>+//DSCL0_SCL_VERT_FILTER_INIT
>+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
>+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
>+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
>+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
>+//DSCL0_SCL_VERT_FILTER_INIT_BOT
>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
>+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C
>+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
>+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
>+//DSCL0_SCL_VERT_FILTER_INIT_C
>+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
>+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
>+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
>+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
>+//DSCL0_SCL_VERT_FILTER_INIT_BOT_C
>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
>+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
>+//DSCL0_SCL_BLACK_OFFSET
>+#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT                                                 0x0
>+#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT                                                  0x10
>+#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK                                                   0x0000FFFFL
>+#define DSCL0_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK                                                    0xFFFF0000L
>+//DSCL0_DSCL_UPDATE
>+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
>+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
>+//DSCL0_DSCL_AUTOCAL
>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
>+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
>+//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT
>+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
>+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
>+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
>+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
>+//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM
>+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
>+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
>+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
>+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
>+//DSCL0_OTG_H_BLANK
>+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
>+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
>+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
>+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
>+//DSCL0_OTG_V_BLANK
>+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
>+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
>+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
>+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
>+//DSCL0_RECOUT_START
>+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
>+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
>+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
>+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
>+//DSCL0_RECOUT_SIZE
>+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
>+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
>+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
>+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
>+//DSCL0_MPC_SIZE
>+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
>+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
>+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
>+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
>+//DSCL0_LB_DATA_FORMAT
>+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
>+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
>+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
>+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
>+//DSCL0_LB_MEMORY_CTRL
>+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
>+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
>+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
>+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
>+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
>+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
>+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
>+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
>+//DSCL0_LB_V_COUNTER
>+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
>+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
>+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
>+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
>+//DSCL0_DSCL_MEM_PWR_CTRL
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
>+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
>+//DSCL0_DSCL_MEM_PWR_STATUS
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
>+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
>+//DSCL0_OBUF_CONTROL
>+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
>+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x4
>+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0xc
>+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x1c
>+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
>+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000010L
>+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00001000L
>+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0xF0000000L
>+//DSCL0_OBUF_MEM_PWR_CTRL
>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
>+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
>+
>+
>+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
>+//CM0_CM_CONTROL
>+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
>+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
>+#define CM0_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
>+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
>+//CM0_CM_ICSC_CONTROL
>+#define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT                                                              0x0
>+#define CM0_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK                                                                0x00000003L
>+//CM0_CM_ICSC_C11_C12
>+#define CM0_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT                                                               0x0
>+#define CM0_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT                                                               0x10
>+#define CM0_CM_ICSC_C11_C12__CM_ICSC_C11_MASK                                                                 0x0000FFFFL
>+#define CM0_CM_ICSC_C11_C12__CM_ICSC_C12_MASK                                                                 0xFFFF0000L
>+//CM0_CM_ICSC_C13_C14
>+#define CM0_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT                                                               0x0
>+#define CM0_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT                                                               0x10
>+#define CM0_CM_ICSC_C13_C14__CM_ICSC_C13_MASK                                                                 0x0000FFFFL
>+#define CM0_CM_ICSC_C13_C14__CM_ICSC_C14_MASK                                                                 0xFFFF0000L
>+//CM0_CM_ICSC_C21_C22
>+#define CM0_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT                                                               0x0
>+#define CM0_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT                                                               0x10
>+#define CM0_CM_ICSC_C21_C22__CM_ICSC_C21_MASK                                                                 0x0000FFFFL
>+#define CM0_CM_ICSC_C21_C22__CM_ICSC_C22_MASK                                                                 0xFFFF0000L
>+//CM0_CM_ICSC_C23_C24
>+#define CM0_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT                                                               0x0
>+#define CM0_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT                                                               0x10
>+#define CM0_CM_ICSC_C23_C24__CM_ICSC_C23_MASK                                                                 0x0000FFFFL
>+#define CM0_CM_ICSC_C23_C24__CM_ICSC_C24_MASK                                                                 0xFFFF0000L
>+//CM0_CM_ICSC_C31_C32
>+#define CM0_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT                                                               0x0
>+#define CM0_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT                                                               0x10
>+#define CM0_CM_ICSC_C31_C32__CM_ICSC_C31_MASK                                                                 0x0000FFFFL
>+#define CM0_CM_ICSC_C31_C32__CM_ICSC_C32_MASK                                                                 0xFFFF0000L
>+//CM0_CM_ICSC_C33_C34
>+#define CM0_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT                                                               0x0
>+#define CM0_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT                                                               0x10
>+#define CM0_CM_ICSC_C33_C34__CM_ICSC_C33_MASK                                                                 0x0000FFFFL
>+#define CM0_CM_ICSC_C33_C34__CM_ICSC_C34_MASK                                                                 0xFFFF0000L
>+//CM0_CM_ICSC_B_C11_C12
>+#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT                                                           0x0
>+#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT                                                           0x10
>+#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK                                                             0x0000FFFFL
>+#define CM0_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK                                                             0xFFFF0000L
>+//CM0_CM_ICSC_B_C13_C14
>+#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT                                                           0x0
>+#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT                                                           0x10
>+#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK                                                             0x0000FFFFL
>+#define CM0_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK                                                             0xFFFF0000L
>+//CM0_CM_ICSC_B_C21_C22
>+#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT                                                           0x0
>+#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT                                                           0x10
>+#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK                                                             0x0000FFFFL
>+#define CM0_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK                                                             0xFFFF0000L
>+//CM0_CM_ICSC_B_C23_C24
>+#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT                                                           0x0
>+#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT                                                           0x10
>+#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK                                                             0x0000FFFFL
>+#define CM0_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK                                                             0xFFFF0000L
>+//CM0_CM_ICSC_B_C31_C32
>+#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT                                                           0x0
>+#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT                                                           0x10
>+#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK                                                             0x0000FFFFL
>+#define CM0_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK                                                             0xFFFF0000L
>+//CM0_CM_ICSC_B_C33_C34
>+#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT                                                           0x0
>+#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT                                                           0x10
>+#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK                                                             0x0000FFFFL
>+#define CM0_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK                                                             0xFFFF0000L
>+//CM0_CM_GAMUT_REMAP_CONTROL
>+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
>+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
>+//CM0_CM_GAMUT_REMAP_C11_C12
>+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
>+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
>+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
>+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
>+//CM0_CM_GAMUT_REMAP_C13_C14
>+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
>+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
>+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
>+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
>+//CM0_CM_GAMUT_REMAP_C21_C22
>+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
>+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
>+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
>+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
>+//CM0_CM_GAMUT_REMAP_C23_C24
>+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
>+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
>+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
>+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
>+//CM0_CM_GAMUT_REMAP_C31_C32
>+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
>+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
>+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
>+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
>+//CM0_CM_GAMUT_REMAP_C33_C34
>+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
>+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
>+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
>+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
>+//CM0_CM_GAMUT_REMAP_B_C11_C12
>+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
>+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
>+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
>+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
>+//CM0_CM_GAMUT_REMAP_B_C13_C14
>+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
>+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
>+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
>+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
>+//CM0_CM_GAMUT_REMAP_B_C21_C22
>+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
>+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
>+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
>+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
>+//CM0_CM_GAMUT_REMAP_B_C23_C24
>+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
>+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
>+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
>+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
>+//CM0_CM_GAMUT_REMAP_B_C31_C32
>+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
>+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
>+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
>+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
>+//CM0_CM_GAMUT_REMAP_B_C33_C34
>+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
>+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
>+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
>+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
>+//CM0_CM_BIAS_CR_R
>+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
>+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
>+//CM0_CM_BIAS_Y_G_CB_B
>+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
>+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
>+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
>+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
>+//CM0_CM_DGAM_CONTROL
>+#define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT                                                          0x0
>+#define CM0_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK                                                            0x00000007L
>+//CM0_CM_DGAM_LUT_INDEX
>+#define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT                                                       0x0
>+#define CM0_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK                                                         0x000001FFL
>+//CM0_CM_DGAM_LUT_DATA
>+#define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT                                                         0x0
>+#define CM0_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK                                                           0x0007FFFFL
>+//CM0_CM_DGAM_LUT_WRITE_EN_MASK
>+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT                                       0x0
>+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT                                           0x4
>+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT                                           0x8
>+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT                                     0xc
>+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK                                         0x00000007L
>+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK                                             0x00000010L
>+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK                                             0x00000700L
>+#define CM0_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK                                       0x00001000L
>+//CM0_CM_DGAM_RAMA_START_CNTL_B
>+#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT                                 0x0
>+#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
>+#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK                                   0x0003FFFFL
>+#define CM0_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
>+//CM0_CM_DGAM_RAMA_START_CNTL_G
>+#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT                                 0x0
>+#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
>+#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK                                   0x0003FFFFL
>+#define CM0_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
>+//CM0_CM_DGAM_RAMA_START_CNTL_R
>+#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT                                 0x0
>+#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
>+#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK                                   0x0003FFFFL
>+#define CM0_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
>+//CM0_CM_DGAM_RAMA_SLOPE_CNTL_B
>+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
>+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
>+//CM0_CM_DGAM_RAMA_SLOPE_CNTL_G
>+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
>+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
>+//CM0_CM_DGAM_RAMA_SLOPE_CNTL_R
>+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
>+#define CM0_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
>+//CM0_CM_DGAM_RAMA_END_CNTL1_B
>+#define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT                                    0x0
>+#define CM0_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK                                      0x0000FFFFL
>+//CM0_CM_DGAM_RAMA_END_CNTL2_B
>+#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
>+#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
>+#define CM0_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
>+//CM0_CM_DGAM_RAMA_END_CNTL1_G
>+#define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT                                    0x0
>+#define CM0_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK                                      0x0000FFFFL
>+//CM0_CM_DGAM_RAMA_END_CNTL2_G
>+#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
>+#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
>+#define CM0_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
>+//CM0_CM_DGAM_RAMA_END_CNTL1_R
>+#define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT                                    0x0
>+#define CM0_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK                                      0x0000FFFFL
>+//CM0_CM_DGAM_RAMA_END_CNTL2_R
>+#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
>+#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
>+#define CM0_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
>+//CM0_CM_DGAM_RAMA_REGION_0_1
>+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
>+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM0_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM0_CM_DGAM_RAMA_REGION_2_3
>+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
>+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM0_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM0_CM_DGAM_RAMA_REGION_4_5
>+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
>+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM0_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM0_CM_DGAM_RAMA_REGION_6_7
>+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
>+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM0_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM0_CM_DGAM_RAMA_REGION_8_9
>+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
>+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM0_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM0_CM_DGAM_RAMA_REGION_10_11
>+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
>+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
>+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM0_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM0_CM_DGAM_RAMA_REGION_12_13
>+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
>+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
>+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM0_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM0_CM_DGAM_RAMA_REGION_14_15
>+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
>+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
>+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM0_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM0_CM_DGAM_RAMB_START_CNTL_B
>+#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT                                 0x0
>+#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
>+#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK                                   0x0003FFFFL
>+#define CM0_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
>+//CM0_CM_DGAM_RAMB_START_CNTL_G
>+#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT                                 0x0
>+#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
>+#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK                                   0x0003FFFFL
>+#define CM0_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
>+//CM0_CM_DGAM_RAMB_START_CNTL_R
>+#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT                                 0x0
>+#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
>+#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK                                   0x0003FFFFL
>+#define CM0_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
>+//CM0_CM_DGAM_RAMB_SLOPE_CNTL_B
>+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
>+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
>+//CM0_CM_DGAM_RAMB_SLOPE_CNTL_G
>+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
>+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
>+//CM0_CM_DGAM_RAMB_SLOPE_CNTL_R
>+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
>+#define CM0_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
>+//CM0_CM_DGAM_RAMB_END_CNTL1_B
>+#define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT                                    0x0
>+#define CM0_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK                                      0x0000FFFFL
>+//CM0_CM_DGAM_RAMB_END_CNTL2_B
>+#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
>+#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
>+#define CM0_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
>+//CM0_CM_DGAM_RAMB_END_CNTL1_G
>+#define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT                                    0x0
>+#define CM0_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK                                      0x0000FFFFL
>+//CM0_CM_DGAM_RAMB_END_CNTL2_G
>+#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
>+#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
>+#define CM0_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
>+//CM0_CM_DGAM_RAMB_END_CNTL1_R
>+#define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT                                    0x0
>+#define CM0_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK                                      0x0000FFFFL
>+//CM0_CM_DGAM_RAMB_END_CNTL2_R
>+#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
>+#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
>+#define CM0_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
>+//CM0_CM_DGAM_RAMB_REGION_0_1
>+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
>+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM0_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM0_CM_DGAM_RAMB_REGION_2_3
>+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
>+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM0_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM0_CM_DGAM_RAMB_REGION_4_5
>+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
>+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM0_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM0_CM_DGAM_RAMB_REGION_6_7
>+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
>+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM0_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM0_CM_DGAM_RAMB_REGION_8_9
>+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
>+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
>+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM0_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM0_CM_DGAM_RAMB_REGION_10_11
>+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
>+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
>+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM0_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM0_CM_DGAM_RAMB_REGION_12_13
>+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
>+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
>+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM0_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM0_CM_DGAM_RAMB_REGION_14_15
>+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
>+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
>+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM0_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM0_CM_BLNDGAM_CONTROL
>+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT                                                    0x0
>+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK                                                      0x00000003L
>+//CM0_CM_BLNDGAM_LUT_INDEX
>+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
>+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
>+//CM0_CM_BLNDGAM_LUT_DATA
>+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
>+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0007FFFFL
>+//CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK
>+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT                                 0x0
>+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT                                     0x4
>+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT                                     0x8
>+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK                                   0x00000007L
>+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK                                       0x00000010L
>+#define CM0_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK                                       0x00000300L
>+//CM0_CM_BLNDGAM_RAMA_START_CNTL_B
>+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
>+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
>+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
>+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
>+//CM0_CM_BLNDGAM_RAMA_START_CNTL_G
>+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
>+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
>+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
>+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
>+//CM0_CM_BLNDGAM_RAMA_START_CNTL_R
>+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
>+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
>+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
>+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
>+//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
>+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
>+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
>+//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
>+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
>+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
>+//CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
>+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
>+#define CM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
>+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_B
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
>+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_B
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
>+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_G
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
>+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_G
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
>+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_R
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
>+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_R
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
>+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_0_1
>+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_2_3
>+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_4_5
>+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_6_7
>+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_8_9
>+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_10_11
>+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_12_13
>+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_14_15
>+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_16_17
>+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_18_19
>+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_20_21
>+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_22_23
>+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_24_25
>+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_26_27
>+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_28_29
>+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_30_31
>+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMA_REGION_32_33
>+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_START_CNTL_B
>+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
>+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
>+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
>+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
>+//CM0_CM_BLNDGAM_RAMB_START_CNTL_G
>+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
>+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
>+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
>+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
>+//CM0_CM_BLNDGAM_RAMB_START_CNTL_R
>+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
>+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
>+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
>+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
>+//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
>+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
>+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
>+//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
>+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
>+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
>+//CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
>+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
>+#define CM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
>+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_B
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
>+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_B
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
>+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_G
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
>+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_G
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
>+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_R
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
>+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_R
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
>+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_0_1
>+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_2_3
>+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_4_5
>+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_6_7
>+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_8_9
>+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_10_11
>+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_12_13
>+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_14_15
>+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_16_17
>+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_18_19
>+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_20_21
>+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_22_23
>+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_24_25
>+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_26_27
>+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_28_29
>+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_30_31
>+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_BLNDGAM_RAMB_REGION_32_33
>+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
>+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
>+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM0_CM_HDR_MULT_COEF
>+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
>+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
>+//CM0_CM_MEM_PWR_CTRL
>+#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT                                                      0x0
>+#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT                                                        0x2
>+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
>+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
>+#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK                                                        0x00000003L
>+#define CM0_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK                                                          0x00000004L
>+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
>+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
>+//CM0_CM_MEM_PWR_STATUS
>+#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT                                                    0x0
>+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
>+#define CM0_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK                                                      0x00000003L
>+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
>+//CM0_CM_DEALPHA
>+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
>+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
>+//CM0_CM_COEF_FORMAT
>+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
>+#define CM0_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT                                                        0x4
>+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
>+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
>+#define CM0_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK                                                          0x00000010L
>+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
>+//CM0_CM_SHAPER_CONTROL
>+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
>+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
>+//CM0_CM_SHAPER_OFFSET_R
>+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
>+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
>+//CM0_CM_SHAPER_OFFSET_G
>+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
>+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
>+//CM0_CM_SHAPER_OFFSET_B
>+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
>+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
>+//CM0_CM_SHAPER_SCALE_R
>+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
>+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
>+//CM0_CM_SHAPER_SCALE_G_B
>+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
>+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
>+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
>+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
>+//CM0_CM_SHAPER_LUT_INDEX
>+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
>+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
>+//CM0_CM_SHAPER_LUT_DATA
>+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
>+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
>+//CM0_CM_SHAPER_LUT_WRITE_EN_MASK
>+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
>+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
>+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT                                       0x8
>+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
>+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
>+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK                                         0x00000300L
>+//CM0_CM_SHAPER_RAMA_START_CNTL_B
>+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
>+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
>+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
>+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
>+//CM0_CM_SHAPER_RAMA_START_CNTL_G
>+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
>+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
>+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
>+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
>+//CM0_CM_SHAPER_RAMA_START_CNTL_R
>+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
>+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
>+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
>+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
>+//CM0_CM_SHAPER_RAMA_END_CNTL_B
>+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
>+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
>+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
>+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
>+//CM0_CM_SHAPER_RAMA_END_CNTL_G
>+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
>+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
>+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
>+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
>+//CM0_CM_SHAPER_RAMA_END_CNTL_R
>+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
>+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
>+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
>+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
>+//CM0_CM_SHAPER_RAMA_REGION_0_1
>+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_2_3
>+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_4_5
>+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_6_7
>+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_8_9
>+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_10_11
>+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_12_13
>+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_14_15
>+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_16_17
>+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_18_19
>+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_20_21
>+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_22_23
>+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_24_25
>+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_26_27
>+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_28_29
>+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_30_31
>+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMA_REGION_32_33
>+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMB_START_CNTL_B
>+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
>+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
>+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
>+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
>+//CM0_CM_SHAPER_RAMB_START_CNTL_G
>+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
>+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
>+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
>+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
>+//CM0_CM_SHAPER_RAMB_START_CNTL_R
>+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
>+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
>+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
>+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
>+//CM0_CM_SHAPER_RAMB_END_CNTL_B
>+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
>+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
>+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
>+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
>+//CM0_CM_SHAPER_RAMB_END_CNTL_G
>+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
>+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
>+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
>+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
>+//CM0_CM_SHAPER_RAMB_END_CNTL_R
>+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
>+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
>+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
>+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
>+//CM0_CM_SHAPER_RAMB_REGION_0_1
>+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_2_3
>+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_4_5
>+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_6_7
>+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_8_9
>+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_10_11
>+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_12_13
>+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_14_15
>+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_16_17
>+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_18_19
>+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_20_21
>+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_22_23
>+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_24_25
>+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_26_27
>+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_28_29
>+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_30_31
>+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_SHAPER_RAMB_REGION_32_33
>+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
>+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
>+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM0_CM_MEM_PWR_CTRL2
>+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
>+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
>+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
>+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
>+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
>+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
>+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
>+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
>+//CM0_CM_MEM_PWR_STATUS2
>+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
>+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
>+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
>+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
>+//CM0_CM_3DLUT_MODE
>+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
>+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
>+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
>+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
>+//CM0_CM_3DLUT_INDEX
>+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
>+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
>+//CM0_CM_3DLUT_DATA
>+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
>+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
>+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
>+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
>+//CM0_CM_3DLUT_DATA_30BIT
>+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
>+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
>+//CM0_CM_3DLUT_READ_WRITE_CONTROL
>+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
>+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
>+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
>+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT                                        0xc
>+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
>+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
>+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
>+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
>+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK                                          0x00003000L
>+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
>+//CM0_CM_3DLUT_OUT_NORM_FACTOR
>+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
>+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
>+//CM0_CM_3DLUT_OUT_OFFSET_R
>+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
>+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
>+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
>+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
>+//CM0_CM_3DLUT_OUT_OFFSET_G
>+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
>+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
>+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
>+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
>+//CM0_CM_3DLUT_OUT_OFFSET_B
>+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
>+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
>+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
>+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
>+//CM0_CM_TEST_DEBUG_INDEX
>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
>+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
>+//CM0_CM_TEST_DEBUG_DATA
>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
>+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON11_PERFCOUNTER_CNTL
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON11_PERFCOUNTER_CNTL2
>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON11_PERFCOUNTER_STATE
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON11_PERFMON_CNTL
>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON11_PERFMON_CNTL2
>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON11_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON11_PERFMON_CVALUE_LOW
>+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON11_PERFMON_HI
>+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON11_PERFMON_LOW
>+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
>+//DPP_TOP1_DPP_CONTROL
>+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT                                         0xe
>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0x10
>+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x12
>+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x14
>+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
>+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK                                           0x00004000L
>+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00010000L
>+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00040000L
>+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00100000L
>+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0xF0000000L
>+//DPP_TOP1_DPP_SOFT_RESET
>+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
>+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
>+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
>+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
>+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
>+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
>+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
>+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
>+//DPP_TOP1_DPP_CRC_VAL_R_G
>+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
>+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
>+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
>+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
>+//DPP_TOP1_DPP_CRC_VAL_B_A
>+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
>+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
>+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
>+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
>+//DPP_TOP1_DPP_CRC_CTRL
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT                                                 0x6
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x7
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x8
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0xa
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xc
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xf
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK                                                   0x00000040L
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000080L
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000300L
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000C00L
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00007000L
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x00008000L
>+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
>+//DPP_TOP1_HOST_READ_CONTROL
>+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
>+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
>+
>+
>+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
>+//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT
>+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
>+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
>+//CNVC_CFG1_FORMAT_CONTROL
>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
>+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
>+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
>+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
>+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
>+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
>+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
>+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
>+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
>+//CNVC_CFG1_FCNV_FP_BIAS_R
>+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
>+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
>+//CNVC_CFG1_FCNV_FP_BIAS_G
>+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
>+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
>+//CNVC_CFG1_FCNV_FP_BIAS_B
>+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
>+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
>+//CNVC_CFG1_FCNV_FP_SCALE_R
>+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
>+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
>+//CNVC_CFG1_FCNV_FP_SCALE_G
>+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
>+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
>+//CNVC_CFG1_FCNV_FP_SCALE_B
>+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
>+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
>+//CNVC_CFG1_COLOR_KEYER_CONTROL
>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
>+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
>+//CNVC_CFG1_COLOR_KEYER_ALPHA
>+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
>+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
>+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
>+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
>+//CNVC_CFG1_COLOR_KEYER_RED
>+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
>+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
>+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
>+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
>+//CNVC_CFG1_COLOR_KEYER_GREEN
>+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
>+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
>+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
>+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
>+//CNVC_CFG1_COLOR_KEYER_BLUE
>+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
>+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
>+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
>+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
>+//CNVC_CFG1_ALPHA_2BIT_LUT
>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
>+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
>+
>+
>+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
>+//CNVC_CUR1_CURSOR0_CONTROL
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
>+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
>+//CNVC_CUR1_CURSOR0_COLOR0
>+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
>+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
>+//CNVC_CUR1_CURSOR0_COLOR1
>+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
>+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
>+//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS
>+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
>+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
>+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
>+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
>+//DSCL1_SCL_COEF_RAM_TAP_SELECT
>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
>+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
>+//DSCL1_SCL_COEF_RAM_TAP_DATA
>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
>+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
>+//DSCL1_SCL_MODE
>+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
>+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
>+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
>+#define DSCL1_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
>+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
>+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
>+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
>+//DSCL1_SCL_TAP_CONTROL
>+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
>+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
>+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
>+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
>+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
>+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
>+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
>+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
>+//DSCL1_DSCL_CONTROL
>+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
>+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
>+//DSCL1_DSCL_2TAP_CONTROL
>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
>+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
>+//DSCL1_SCL_MANUAL_REPLICATE_CONTROL
>+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
>+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
>+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
>+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
>+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO
>+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
>+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x03FFFFFFL
>+//DSCL1_SCL_HORZ_FILTER_INIT
>+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
>+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
>+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
>+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
>+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C
>+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
>+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
>+//DSCL1_SCL_HORZ_FILTER_INIT_C
>+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
>+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
>+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
>+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
>+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO
>+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
>+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x03FFFFFFL
>+//DSCL1_SCL_VERT_FILTER_INIT
>+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
>+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
>+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
>+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
>+//DSCL1_SCL_VERT_FILTER_INIT_BOT
>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
>+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C
>+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
>+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
>+//DSCL1_SCL_VERT_FILTER_INIT_C
>+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
>+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
>+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
>+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
>+//DSCL1_SCL_VERT_FILTER_INIT_BOT_C
>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
>+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
>+//DSCL1_SCL_BLACK_OFFSET
>+#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT                                                 0x0
>+#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT                                                  0x10
>+#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK                                                   0x0000FFFFL
>+#define DSCL1_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK                                                    0xFFFF0000L
>+//DSCL1_DSCL_UPDATE
>+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
>+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
>+//DSCL1_DSCL_AUTOCAL
>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
>+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
>+//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT
>+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
>+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
>+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
>+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
>+//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM
>+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
>+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
>+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
>+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
>+//DSCL1_OTG_H_BLANK
>+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
>+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
>+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
>+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
>+//DSCL1_OTG_V_BLANK
>+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
>+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
>+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
>+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
>+//DSCL1_RECOUT_START
>+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
>+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
>+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
>+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
>+//DSCL1_RECOUT_SIZE
>+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
>+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
>+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
>+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
>+//DSCL1_MPC_SIZE
>+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
>+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
>+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
>+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
>+//DSCL1_LB_DATA_FORMAT
>+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
>+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
>+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
>+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
>+//DSCL1_LB_MEMORY_CTRL
>+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
>+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
>+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
>+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
>+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
>+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
>+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
>+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
>+//DSCL1_LB_V_COUNTER
>+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
>+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
>+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
>+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
>+//DSCL1_DSCL_MEM_PWR_CTRL
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
>+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
>+//DSCL1_DSCL_MEM_PWR_STATUS
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
>+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
>+//DSCL1_OBUF_CONTROL
>+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
>+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x4
>+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0xc
>+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x1c
>+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
>+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000010L
>+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00001000L
>+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0xF0000000L
>+//DSCL1_OBUF_MEM_PWR_CTRL
>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
>+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
>+
>+
>+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
>+//CM1_CM_CONTROL
>+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
>+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
>+#define CM1_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
>+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
>+//CM1_CM_ICSC_CONTROL
>+#define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT                                                              0x0
>+#define CM1_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK                                                                0x00000003L
>+//CM1_CM_ICSC_C11_C12
>+#define CM1_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT                                                               0x0
>+#define CM1_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT                                                               0x10
>+#define CM1_CM_ICSC_C11_C12__CM_ICSC_C11_MASK                                                                 0x0000FFFFL
>+#define CM1_CM_ICSC_C11_C12__CM_ICSC_C12_MASK                                                                 0xFFFF0000L
>+//CM1_CM_ICSC_C13_C14
>+#define CM1_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT                                                               0x0
>+#define CM1_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT                                                               0x10
>+#define CM1_CM_ICSC_C13_C14__CM_ICSC_C13_MASK                                                                 0x0000FFFFL
>+#define CM1_CM_ICSC_C13_C14__CM_ICSC_C14_MASK                                                                 0xFFFF0000L
>+//CM1_CM_ICSC_C21_C22
>+#define CM1_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT                                                               0x0
>+#define CM1_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT                                                               0x10
>+#define CM1_CM_ICSC_C21_C22__CM_ICSC_C21_MASK                                                                 0x0000FFFFL
>+#define CM1_CM_ICSC_C21_C22__CM_ICSC_C22_MASK                                                                 0xFFFF0000L
>+//CM1_CM_ICSC_C23_C24
>+#define CM1_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT                                                               0x0
>+#define CM1_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT                                                               0x10
>+#define CM1_CM_ICSC_C23_C24__CM_ICSC_C23_MASK                                                                 0x0000FFFFL
>+#define CM1_CM_ICSC_C23_C24__CM_ICSC_C24_MASK                                                                 0xFFFF0000L
>+//CM1_CM_ICSC_C31_C32
>+#define CM1_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT                                                               0x0
>+#define CM1_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT                                                               0x10
>+#define CM1_CM_ICSC_C31_C32__CM_ICSC_C31_MASK                                                                 0x0000FFFFL
>+#define CM1_CM_ICSC_C31_C32__CM_ICSC_C32_MASK                                                                 0xFFFF0000L
>+//CM1_CM_ICSC_C33_C34
>+#define CM1_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT                                                               0x0
>+#define CM1_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT                                                               0x10
>+#define CM1_CM_ICSC_C33_C34__CM_ICSC_C33_MASK                                                                 0x0000FFFFL
>+#define CM1_CM_ICSC_C33_C34__CM_ICSC_C34_MASK                                                                 0xFFFF0000L
>+//CM1_CM_ICSC_B_C11_C12
>+#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT                                                           0x0
>+#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT                                                           0x10
>+#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK                                                             0x0000FFFFL
>+#define CM1_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK                                                             0xFFFF0000L
>+//CM1_CM_ICSC_B_C13_C14
>+#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT                                                           0x0
>+#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT                                                           0x10
>+#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK                                                             0x0000FFFFL
>+#define CM1_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK                                                             0xFFFF0000L
>+//CM1_CM_ICSC_B_C21_C22
>+#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT                                                           0x0
>+#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT                                                           0x10
>+#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK                                                             0x0000FFFFL
>+#define CM1_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK                                                             0xFFFF0000L
>+//CM1_CM_ICSC_B_C23_C24
>+#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT                                                           0x0
>+#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT                                                           0x10
>+#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK                                                             0x0000FFFFL
>+#define CM1_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK                                                             0xFFFF0000L
>+//CM1_CM_ICSC_B_C31_C32
>+#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT                                                           0x0
>+#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT                                                           0x10
>+#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK                                                             0x0000FFFFL
>+#define CM1_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK                                                             0xFFFF0000L
>+//CM1_CM_ICSC_B_C33_C34
>+#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT                                                           0x0
>+#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT                                                           0x10
>+#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK                                                             0x0000FFFFL
>+#define CM1_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK                                                             0xFFFF0000L
>+//CM1_CM_GAMUT_REMAP_CONTROL
>+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
>+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
>+//CM1_CM_GAMUT_REMAP_C11_C12
>+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
>+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
>+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
>+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
>+//CM1_CM_GAMUT_REMAP_C13_C14
>+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
>+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
>+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
>+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
>+//CM1_CM_GAMUT_REMAP_C21_C22
>+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
>+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
>+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
>+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
>+//CM1_CM_GAMUT_REMAP_C23_C24
>+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
>+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
>+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
>+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
>+//CM1_CM_GAMUT_REMAP_C31_C32
>+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
>+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
>+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
>+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
>+//CM1_CM_GAMUT_REMAP_C33_C34
>+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
>+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
>+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
>+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
>+//CM1_CM_GAMUT_REMAP_B_C11_C12
>+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
>+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
>+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
>+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
>+//CM1_CM_GAMUT_REMAP_B_C13_C14
>+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
>+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
>+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
>+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
>+//CM1_CM_GAMUT_REMAP_B_C21_C22
>+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
>+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
>+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
>+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
>+//CM1_CM_GAMUT_REMAP_B_C23_C24
>+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
>+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
>+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
>+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
>+//CM1_CM_GAMUT_REMAP_B_C31_C32
>+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
>+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
>+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
>+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
>+//CM1_CM_GAMUT_REMAP_B_C33_C34
>+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
>+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
>+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
>+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
>+//CM1_CM_BIAS_CR_R
>+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
>+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
>+//CM1_CM_BIAS_Y_G_CB_B
>+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
>+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
>+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
>+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
>+//CM1_CM_DGAM_CONTROL
>+#define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT                                                          0x0
>+#define CM1_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK                                                            0x00000007L
>+//CM1_CM_DGAM_LUT_INDEX
>+#define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT                                                       0x0
>+#define CM1_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK                                                         0x000001FFL
>+//CM1_CM_DGAM_LUT_DATA
>+#define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT                                                         0x0
>+#define CM1_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK                                                           0x0007FFFFL
>+//CM1_CM_DGAM_LUT_WRITE_EN_MASK
>+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT                                       0x0
>+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT                                           0x4
>+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT                                           0x8
>+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT                                     0xc
>+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK                                         0x00000007L
>+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK                                             0x00000010L
>+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK                                             0x00000700L
>+#define CM1_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK                                       0x00001000L
>+//CM1_CM_DGAM_RAMA_START_CNTL_B
>+#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT                                 0x0
>+#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
>+#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK                                   0x0003FFFFL
>+#define CM1_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
>+//CM1_CM_DGAM_RAMA_START_CNTL_G
>+#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT                                 0x0
>+#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
>+#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK                                   0x0003FFFFL
>+#define CM1_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
>+//CM1_CM_DGAM_RAMA_START_CNTL_R
>+#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT                                 0x0
>+#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
>+#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK                                   0x0003FFFFL
>+#define CM1_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
>+//CM1_CM_DGAM_RAMA_SLOPE_CNTL_B
>+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
>+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
>+//CM1_CM_DGAM_RAMA_SLOPE_CNTL_G
>+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
>+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
>+//CM1_CM_DGAM_RAMA_SLOPE_CNTL_R
>+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
>+#define CM1_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
>+//CM1_CM_DGAM_RAMA_END_CNTL1_B
>+#define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT                                    0x0
>+#define CM1_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK                                      0x0000FFFFL
>+//CM1_CM_DGAM_RAMA_END_CNTL2_B
>+#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
>+#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
>+#define CM1_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
>+//CM1_CM_DGAM_RAMA_END_CNTL1_G
>+#define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT                                    0x0
>+#define CM1_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK                                      0x0000FFFFL
>+//CM1_CM_DGAM_RAMA_END_CNTL2_G
>+#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
>+#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
>+#define CM1_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
>+//CM1_CM_DGAM_RAMA_END_CNTL1_R
>+#define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT                                    0x0
>+#define CM1_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK                                      0x0000FFFFL
>+//CM1_CM_DGAM_RAMA_END_CNTL2_R
>+#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
>+#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
>+#define CM1_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
>+//CM1_CM_DGAM_RAMA_REGION_0_1
>+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
>+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM1_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM1_CM_DGAM_RAMA_REGION_2_3
>+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
>+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM1_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM1_CM_DGAM_RAMA_REGION_4_5
>+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
>+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM1_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM1_CM_DGAM_RAMA_REGION_6_7
>+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
>+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM1_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM1_CM_DGAM_RAMA_REGION_8_9
>+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
>+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM1_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM1_CM_DGAM_RAMA_REGION_10_11
>+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
>+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
>+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM1_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM1_CM_DGAM_RAMA_REGION_12_13
>+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
>+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
>+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM1_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM1_CM_DGAM_RAMA_REGION_14_15
>+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
>+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
>+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM1_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM1_CM_DGAM_RAMB_START_CNTL_B
>+#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT                                 0x0
>+#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
>+#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK                                   0x0003FFFFL
>+#define CM1_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
>+//CM1_CM_DGAM_RAMB_START_CNTL_G
>+#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT                                 0x0
>+#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
>+#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK                                   0x0003FFFFL
>+#define CM1_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
>+//CM1_CM_DGAM_RAMB_START_CNTL_R
>+#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT                                 0x0
>+#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
>+#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK                                   0x0003FFFFL
>+#define CM1_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
>+//CM1_CM_DGAM_RAMB_SLOPE_CNTL_B
>+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
>+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
>+//CM1_CM_DGAM_RAMB_SLOPE_CNTL_G
>+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
>+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
>+//CM1_CM_DGAM_RAMB_SLOPE_CNTL_R
>+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
>+#define CM1_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
>+//CM1_CM_DGAM_RAMB_END_CNTL1_B
>+#define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT                                    0x0
>+#define CM1_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK                                      0x0000FFFFL
>+//CM1_CM_DGAM_RAMB_END_CNTL2_B
>+#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
>+#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
>+#define CM1_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
>+//CM1_CM_DGAM_RAMB_END_CNTL1_G
>+#define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT                                    0x0
>+#define CM1_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK                                      0x0000FFFFL
>+//CM1_CM_DGAM_RAMB_END_CNTL2_G
>+#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
>+#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
>+#define CM1_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
>+//CM1_CM_DGAM_RAMB_END_CNTL1_R
>+#define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT                                    0x0
>+#define CM1_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK                                      0x0000FFFFL
>+//CM1_CM_DGAM_RAMB_END_CNTL2_R
>+#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
>+#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
>+#define CM1_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
>+//CM1_CM_DGAM_RAMB_REGION_0_1
>+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
>+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM1_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM1_CM_DGAM_RAMB_REGION_2_3
>+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
>+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM1_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM1_CM_DGAM_RAMB_REGION_4_5
>+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
>+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM1_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM1_CM_DGAM_RAMB_REGION_6_7
>+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
>+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM1_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM1_CM_DGAM_RAMB_REGION_8_9
>+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
>+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
>+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM1_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM1_CM_DGAM_RAMB_REGION_10_11
>+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
>+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
>+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM1_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM1_CM_DGAM_RAMB_REGION_12_13
>+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
>+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
>+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM1_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM1_CM_DGAM_RAMB_REGION_14_15
>+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
>+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
>+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM1_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM1_CM_BLNDGAM_CONTROL
>+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT                                                    0x0
>+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK                                                      0x00000003L
>+//CM1_CM_BLNDGAM_LUT_INDEX
>+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
>+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
>+//CM1_CM_BLNDGAM_LUT_DATA
>+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
>+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0007FFFFL
>+//CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK
>+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT                                 0x0
>+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT                                     0x4
>+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT                                     0x8
>+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK                                   0x00000007L
>+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK                                       0x00000010L
>+#define CM1_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK                                       0x00000300L
>+//CM1_CM_BLNDGAM_RAMA_START_CNTL_B
>+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
>+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
>+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
>+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
>+//CM1_CM_BLNDGAM_RAMA_START_CNTL_G
>+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
>+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
>+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
>+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
>+//CM1_CM_BLNDGAM_RAMA_START_CNTL_R
>+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
>+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
>+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
>+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
>+//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
>+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
>+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
>+//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
>+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
>+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
>+//CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
>+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
>+#define CM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
>+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_B
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
>+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_B
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
>+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_G
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
>+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_G
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
>+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_R
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
>+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_R
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
>+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_0_1
>+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_2_3
>+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_4_5
>+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_6_7
>+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_8_9
>+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_10_11
>+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_12_13
>+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_14_15
>+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_16_17
>+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_18_19
>+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_20_21
>+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_22_23
>+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_24_25
>+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_26_27
>+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_28_29
>+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_30_31
>+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMA_REGION_32_33
>+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_START_CNTL_B
>+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
>+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
>+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
>+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
>+//CM1_CM_BLNDGAM_RAMB_START_CNTL_G
>+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
>+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
>+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
>+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
>+//CM1_CM_BLNDGAM_RAMB_START_CNTL_R
>+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
>+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
>+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
>+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
>+//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
>+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
>+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
>+//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
>+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
>+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
>+//CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
>+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
>+#define CM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
>+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_B
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
>+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_B
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
>+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_G
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
>+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_G
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
>+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_R
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
>+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_R
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
>+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_0_1
>+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_2_3
>+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_4_5
>+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_6_7
>+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_8_9
>+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_10_11
>+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_12_13
>+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_14_15
>+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_16_17
>+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_18_19
>+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_20_21
>+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_22_23
>+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_24_25
>+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_26_27
>+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_28_29
>+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_30_31
>+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_BLNDGAM_RAMB_REGION_32_33
>+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
>+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
>+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM1_CM_HDR_MULT_COEF
>+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
>+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
>+//CM1_CM_MEM_PWR_CTRL
>+#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT                                                      0x0
>+#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT                                                        0x2
>+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
>+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
>+#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK                                                        0x00000003L
>+#define CM1_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK                                                          0x00000004L
>+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
>+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
>+//CM1_CM_MEM_PWR_STATUS
>+#define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT                                                    0x0
>+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
>+#define CM1_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK                                                      0x00000003L
>+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
>+//CM1_CM_DEALPHA
>+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
>+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
>+//CM1_CM_COEF_FORMAT
>+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
>+#define CM1_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT                                                        0x4
>+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
>+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
>+#define CM1_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK                                                          0x00000010L
>+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
>+//CM1_CM_SHAPER_CONTROL
>+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
>+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
>+//CM1_CM_SHAPER_OFFSET_R
>+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
>+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
>+//CM1_CM_SHAPER_OFFSET_G
>+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
>+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
>+//CM1_CM_SHAPER_OFFSET_B
>+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
>+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
>+//CM1_CM_SHAPER_SCALE_R
>+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
>+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
>+//CM1_CM_SHAPER_SCALE_G_B
>+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
>+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
>+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
>+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
>+//CM1_CM_SHAPER_LUT_INDEX
>+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
>+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
>+//CM1_CM_SHAPER_LUT_DATA
>+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
>+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
>+//CM1_CM_SHAPER_LUT_WRITE_EN_MASK
>+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
>+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
>+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT                                       0x8
>+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
>+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
>+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK                                         0x00000300L
>+//CM1_CM_SHAPER_RAMA_START_CNTL_B
>+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
>+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
>+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
>+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
>+//CM1_CM_SHAPER_RAMA_START_CNTL_G
>+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
>+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
>+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
>+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
>+//CM1_CM_SHAPER_RAMA_START_CNTL_R
>+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
>+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
>+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
>+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
>+//CM1_CM_SHAPER_RAMA_END_CNTL_B
>+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
>+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
>+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
>+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
>+//CM1_CM_SHAPER_RAMA_END_CNTL_G
>+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
>+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
>+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
>+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
>+//CM1_CM_SHAPER_RAMA_END_CNTL_R
>+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
>+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
>+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
>+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
>+//CM1_CM_SHAPER_RAMA_REGION_0_1
>+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_2_3
>+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_4_5
>+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_6_7
>+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_8_9
>+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_10_11
>+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_12_13
>+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_14_15
>+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_16_17
>+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_18_19
>+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_20_21
>+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_22_23
>+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_24_25
>+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_26_27
>+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_28_29
>+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_30_31
>+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMA_REGION_32_33
>+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMB_START_CNTL_B
>+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
>+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
>+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
>+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
>+//CM1_CM_SHAPER_RAMB_START_CNTL_G
>+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
>+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
>+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
>+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
>+//CM1_CM_SHAPER_RAMB_START_CNTL_R
>+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
>+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
>+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
>+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
>+//CM1_CM_SHAPER_RAMB_END_CNTL_B
>+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
>+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
>+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
>+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
>+//CM1_CM_SHAPER_RAMB_END_CNTL_G
>+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
>+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
>+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
>+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
>+//CM1_CM_SHAPER_RAMB_END_CNTL_R
>+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
>+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
>+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
>+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
>+//CM1_CM_SHAPER_RAMB_REGION_0_1
>+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_2_3
>+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_4_5
>+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_6_7
>+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_8_9
>+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_10_11
>+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_12_13
>+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_14_15
>+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_16_17
>+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_18_19
>+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_20_21
>+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_22_23
>+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_24_25
>+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_26_27
>+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_28_29
>+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_30_31
>+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_SHAPER_RAMB_REGION_32_33
>+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
>+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
>+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM1_CM_MEM_PWR_CTRL2
>+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
>+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
>+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
>+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
>+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
>+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
>+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
>+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
>+//CM1_CM_MEM_PWR_STATUS2
>+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
>+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
>+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
>+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
>+//CM1_CM_3DLUT_MODE
>+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
>+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
>+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
>+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
>+//CM1_CM_3DLUT_INDEX
>+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
>+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
>+//CM1_CM_3DLUT_DATA
>+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
>+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
>+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
>+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
>+//CM1_CM_3DLUT_DATA_30BIT
>+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
>+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
>+//CM1_CM_3DLUT_READ_WRITE_CONTROL
>+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
>+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
>+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
>+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT                                        0xc
>+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
>+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
>+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
>+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
>+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK                                          0x00003000L
>+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
>+//CM1_CM_3DLUT_OUT_NORM_FACTOR
>+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
>+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
>+//CM1_CM_3DLUT_OUT_OFFSET_R
>+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
>+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
>+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
>+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
>+//CM1_CM_3DLUT_OUT_OFFSET_G
>+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
>+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
>+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
>+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
>+//CM1_CM_3DLUT_OUT_OFFSET_B
>+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
>+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
>+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
>+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
>+//CM1_CM_TEST_DEBUG_INDEX
>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
>+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
>+//CM1_CM_TEST_DEBUG_DATA
>+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
>+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON12_PERFCOUNTER_CNTL
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON12_PERFCOUNTER_CNTL2
>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON12_PERFCOUNTER_STATE
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON12_PERFMON_CNTL
>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON12_PERFMON_CNTL2
>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON12_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON12_PERFMON_CVALUE_LOW
>+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON12_PERFMON_HI
>+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON12_PERFMON_LOW
>+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
>+//DPP_TOP2_DPP_CONTROL
>+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT                                         0xe
>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0x10
>+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x12
>+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x14
>+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
>+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK                                           0x00004000L
>+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00010000L
>+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00040000L
>+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00100000L
>+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0xF0000000L
>+//DPP_TOP2_DPP_SOFT_RESET
>+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
>+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
>+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
>+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
>+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
>+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
>+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
>+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
>+//DPP_TOP2_DPP_CRC_VAL_R_G
>+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
>+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
>+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
>+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
>+//DPP_TOP2_DPP_CRC_VAL_B_A
>+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
>+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
>+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
>+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
>+//DPP_TOP2_DPP_CRC_CTRL
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT                                                 0x6
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x7
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x8
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0xa
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xc
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xf
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK                                                   0x00000040L
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000080L
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000300L
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000C00L
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00007000L
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x00008000L
>+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
>+//DPP_TOP2_HOST_READ_CONTROL
>+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
>+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
>+
>+
>+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
>+//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT
>+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
>+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
>+//CNVC_CFG2_FORMAT_CONTROL
>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
>+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
>+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
>+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
>+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
>+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
>+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
>+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
>+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
>+//CNVC_CFG2_FCNV_FP_BIAS_R
>+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
>+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
>+//CNVC_CFG2_FCNV_FP_BIAS_G
>+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
>+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
>+//CNVC_CFG2_FCNV_FP_BIAS_B
>+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
>+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
>+//CNVC_CFG2_FCNV_FP_SCALE_R
>+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
>+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
>+//CNVC_CFG2_FCNV_FP_SCALE_G
>+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
>+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
>+//CNVC_CFG2_FCNV_FP_SCALE_B
>+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
>+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
>+//CNVC_CFG2_COLOR_KEYER_CONTROL
>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
>+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
>+//CNVC_CFG2_COLOR_KEYER_ALPHA
>+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
>+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
>+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
>+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
>+//CNVC_CFG2_COLOR_KEYER_RED
>+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
>+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
>+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
>+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
>+//CNVC_CFG2_COLOR_KEYER_GREEN
>+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
>+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
>+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
>+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
>+//CNVC_CFG2_COLOR_KEYER_BLUE
>+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
>+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
>+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
>+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
>+//CNVC_CFG2_ALPHA_2BIT_LUT
>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
>+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
>+
>+
>+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
>+//CNVC_CUR2_CURSOR0_CONTROL
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
>+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
>+//CNVC_CUR2_CURSOR0_COLOR0
>+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
>+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
>+//CNVC_CUR2_CURSOR0_COLOR1
>+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
>+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
>+//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS
>+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
>+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
>+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
>+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
>+//DSCL2_SCL_COEF_RAM_TAP_SELECT
>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
>+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
>+//DSCL2_SCL_COEF_RAM_TAP_DATA
>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
>+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
>+//DSCL2_SCL_MODE
>+#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
>+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
>+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
>+#define DSCL2_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
>+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
>+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
>+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
>+//DSCL2_SCL_TAP_CONTROL
>+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
>+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
>+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
>+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
>+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
>+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
>+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
>+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
>+//DSCL2_DSCL_CONTROL
>+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
>+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
>+//DSCL2_DSCL_2TAP_CONTROL
>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
>+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
>+//DSCL2_SCL_MANUAL_REPLICATE_CONTROL
>+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
>+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
>+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
>+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
>+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO
>+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
>+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x03FFFFFFL
>+//DSCL2_SCL_HORZ_FILTER_INIT
>+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
>+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
>+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
>+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
>+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C
>+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
>+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
>+//DSCL2_SCL_HORZ_FILTER_INIT_C
>+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
>+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
>+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
>+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
>+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO
>+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
>+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x03FFFFFFL
>+//DSCL2_SCL_VERT_FILTER_INIT
>+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
>+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
>+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
>+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
>+//DSCL2_SCL_VERT_FILTER_INIT_BOT
>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
>+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C
>+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
>+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
>+//DSCL2_SCL_VERT_FILTER_INIT_C
>+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
>+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
>+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
>+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
>+//DSCL2_SCL_VERT_FILTER_INIT_BOT_C
>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
>+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
>+//DSCL2_SCL_BLACK_OFFSET
>+#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT                                                 0x0
>+#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT                                                  0x10
>+#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK                                                   0x0000FFFFL
>+#define DSCL2_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK                                                    0xFFFF0000L
>+//DSCL2_DSCL_UPDATE
>+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
>+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
>+//DSCL2_DSCL_AUTOCAL
>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
>+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
>+//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT
>+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
>+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
>+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
>+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
>+//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM
>+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
>+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
>+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
>+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
>+//DSCL2_OTG_H_BLANK
>+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
>+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
>+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
>+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
>+//DSCL2_OTG_V_BLANK
>+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
>+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
>+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
>+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
>+//DSCL2_RECOUT_START
>+#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
>+#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
>+#define DSCL2_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
>+#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
>+//DSCL2_RECOUT_SIZE
>+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
>+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
>+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
>+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
>+//DSCL2_MPC_SIZE
>+#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
>+#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
>+#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
>+#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
>+//DSCL2_LB_DATA_FORMAT
>+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
>+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
>+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
>+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
>+//DSCL2_LB_MEMORY_CTRL
>+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
>+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
>+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
>+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
>+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
>+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
>+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
>+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
>+//DSCL2_LB_V_COUNTER
>+#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
>+#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
>+#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
>+#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
>+//DSCL2_DSCL_MEM_PWR_CTRL
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
>+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
>+//DSCL2_DSCL_MEM_PWR_STATUS
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
>+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
>+//DSCL2_OBUF_CONTROL
>+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
>+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x4
>+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0xc
>+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x1c
>+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
>+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000010L
>+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00001000L
>+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0xF0000000L
>+//DSCL2_OBUF_MEM_PWR_CTRL
>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
>+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
>+
>+
>+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
>+//CM2_CM_CONTROL
>+#define CM2_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
>+#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
>+#define CM2_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
>+#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
>+//CM2_CM_ICSC_CONTROL
>+#define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT                                                              0x0
>+#define CM2_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK                                                                0x00000003L
>+//CM2_CM_ICSC_C11_C12
>+#define CM2_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT                                                               0x0
>+#define CM2_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT                                                               0x10
>+#define CM2_CM_ICSC_C11_C12__CM_ICSC_C11_MASK                                                                 0x0000FFFFL
>+#define CM2_CM_ICSC_C11_C12__CM_ICSC_C12_MASK                                                                 0xFFFF0000L
>+//CM2_CM_ICSC_C13_C14
>+#define CM2_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT                                                               0x0
>+#define CM2_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT                                                               0x10
>+#define CM2_CM_ICSC_C13_C14__CM_ICSC_C13_MASK                                                                 0x0000FFFFL
>+#define CM2_CM_ICSC_C13_C14__CM_ICSC_C14_MASK                                                                 0xFFFF0000L
>+//CM2_CM_ICSC_C21_C22
>+#define CM2_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT                                                               0x0
>+#define CM2_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT                                                               0x10
>+#define CM2_CM_ICSC_C21_C22__CM_ICSC_C21_MASK                                                                 0x0000FFFFL
>+#define CM2_CM_ICSC_C21_C22__CM_ICSC_C22_MASK                                                                 0xFFFF0000L
>+//CM2_CM_ICSC_C23_C24
>+#define CM2_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT                                                               0x0
>+#define CM2_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT                                                               0x10
>+#define CM2_CM_ICSC_C23_C24__CM_ICSC_C23_MASK                                                                 0x0000FFFFL
>+#define CM2_CM_ICSC_C23_C24__CM_ICSC_C24_MASK                                                                 0xFFFF0000L
>+//CM2_CM_ICSC_C31_C32
>+#define CM2_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT                                                               0x0
>+#define CM2_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT                                                               0x10
>+#define CM2_CM_ICSC_C31_C32__CM_ICSC_C31_MASK                                                                 0x0000FFFFL
>+#define CM2_CM_ICSC_C31_C32__CM_ICSC_C32_MASK                                                                 0xFFFF0000L
>+//CM2_CM_ICSC_C33_C34
>+#define CM2_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT                                                               0x0
>+#define CM2_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT                                                               0x10
>+#define CM2_CM_ICSC_C33_C34__CM_ICSC_C33_MASK                                                                 0x0000FFFFL
>+#define CM2_CM_ICSC_C33_C34__CM_ICSC_C34_MASK                                                                 0xFFFF0000L
>+//CM2_CM_ICSC_B_C11_C12
>+#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT                                                           0x0
>+#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT                                                           0x10
>+#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK                                                             0x0000FFFFL
>+#define CM2_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK                                                             0xFFFF0000L
>+//CM2_CM_ICSC_B_C13_C14
>+#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT                                                           0x0
>+#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT                                                           0x10
>+#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK                                                             0x0000FFFFL
>+#define CM2_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK                                                             0xFFFF0000L
>+//CM2_CM_ICSC_B_C21_C22
>+#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT                                                           0x0
>+#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT                                                           0x10
>+#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK                                                             0x0000FFFFL
>+#define CM2_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK                                                             0xFFFF0000L
>+//CM2_CM_ICSC_B_C23_C24
>+#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT                                                           0x0
>+#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT                                                           0x10
>+#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK                                                             0x0000FFFFL
>+#define CM2_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK                                                             0xFFFF0000L
>+//CM2_CM_ICSC_B_C31_C32
>+#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT                                                           0x0
>+#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT                                                           0x10
>+#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK                                                             0x0000FFFFL
>+#define CM2_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK                                                             0xFFFF0000L
>+//CM2_CM_ICSC_B_C33_C34
>+#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT                                                           0x0
>+#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT                                                           0x10
>+#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK                                                             0x0000FFFFL
>+#define CM2_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK                                                             0xFFFF0000L
>+//CM2_CM_GAMUT_REMAP_CONTROL
>+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
>+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
>+//CM2_CM_GAMUT_REMAP_C11_C12
>+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
>+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
>+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
>+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
>+//CM2_CM_GAMUT_REMAP_C13_C14
>+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
>+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
>+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
>+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
>+//CM2_CM_GAMUT_REMAP_C21_C22
>+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
>+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
>+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
>+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
>+//CM2_CM_GAMUT_REMAP_C23_C24
>+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
>+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
>+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
>+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
>+//CM2_CM_GAMUT_REMAP_C31_C32
>+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
>+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
>+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
>+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
>+//CM2_CM_GAMUT_REMAP_C33_C34
>+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
>+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
>+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
>+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
>+//CM2_CM_GAMUT_REMAP_B_C11_C12
>+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
>+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
>+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
>+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
>+//CM2_CM_GAMUT_REMAP_B_C13_C14
>+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
>+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
>+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
>+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
>+//CM2_CM_GAMUT_REMAP_B_C21_C22
>+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
>+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
>+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
>+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
>+//CM2_CM_GAMUT_REMAP_B_C23_C24
>+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
>+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
>+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
>+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
>+//CM2_CM_GAMUT_REMAP_B_C31_C32
>+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
>+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
>+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
>+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
>+//CM2_CM_GAMUT_REMAP_B_C33_C34
>+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
>+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
>+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
>+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
>+//CM2_CM_BIAS_CR_R
>+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
>+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
>+//CM2_CM_BIAS_Y_G_CB_B
>+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
>+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
>+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
>+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
>+//CM2_CM_DGAM_CONTROL
>+#define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT                                                          0x0
>+#define CM2_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK                                                            0x00000007L
>+//CM2_CM_DGAM_LUT_INDEX
>+#define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT                                                       0x0
>+#define CM2_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK                                                         0x000001FFL
>+//CM2_CM_DGAM_LUT_DATA
>+#define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT                                                         0x0
>+#define CM2_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK                                                           0x0007FFFFL
>+//CM2_CM_DGAM_LUT_WRITE_EN_MASK
>+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT                                       0x0
>+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT                                           0x4
>+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT                                           0x8
>+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT                                     0xc
>+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK                                         0x00000007L
>+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK                                             0x00000010L
>+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK                                             0x00000700L
>+#define CM2_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK                                       0x00001000L
>+//CM2_CM_DGAM_RAMA_START_CNTL_B
>+#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT                                 0x0
>+#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
>+#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK                                   0x0003FFFFL
>+#define CM2_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
>+//CM2_CM_DGAM_RAMA_START_CNTL_G
>+#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT                                 0x0
>+#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
>+#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK                                   0x0003FFFFL
>+#define CM2_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
>+//CM2_CM_DGAM_RAMA_START_CNTL_R
>+#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT                                 0x0
>+#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
>+#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK                                   0x0003FFFFL
>+#define CM2_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
>+//CM2_CM_DGAM_RAMA_SLOPE_CNTL_B
>+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
>+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
>+//CM2_CM_DGAM_RAMA_SLOPE_CNTL_G
>+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
>+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
>+//CM2_CM_DGAM_RAMA_SLOPE_CNTL_R
>+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
>+#define CM2_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
>+//CM2_CM_DGAM_RAMA_END_CNTL1_B
>+#define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT                                    0x0
>+#define CM2_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK                                      0x0000FFFFL
>+//CM2_CM_DGAM_RAMA_END_CNTL2_B
>+#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
>+#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
>+#define CM2_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
>+//CM2_CM_DGAM_RAMA_END_CNTL1_G
>+#define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT                                    0x0
>+#define CM2_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK                                      0x0000FFFFL
>+//CM2_CM_DGAM_RAMA_END_CNTL2_G
>+#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
>+#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
>+#define CM2_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
>+//CM2_CM_DGAM_RAMA_END_CNTL1_R
>+#define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT                                    0x0
>+#define CM2_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK                                      0x0000FFFFL
>+//CM2_CM_DGAM_RAMA_END_CNTL2_R
>+#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
>+#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
>+#define CM2_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
>+//CM2_CM_DGAM_RAMA_REGION_0_1
>+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
>+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM2_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM2_CM_DGAM_RAMA_REGION_2_3
>+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
>+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM2_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM2_CM_DGAM_RAMA_REGION_4_5
>+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
>+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM2_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM2_CM_DGAM_RAMA_REGION_6_7
>+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
>+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM2_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM2_CM_DGAM_RAMA_REGION_8_9
>+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
>+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM2_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM2_CM_DGAM_RAMA_REGION_10_11
>+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
>+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
>+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM2_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM2_CM_DGAM_RAMA_REGION_12_13
>+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
>+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
>+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM2_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM2_CM_DGAM_RAMA_REGION_14_15
>+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
>+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
>+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM2_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM2_CM_DGAM_RAMB_START_CNTL_B
>+#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT                                 0x0
>+#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
>+#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK                                   0x0003FFFFL
>+#define CM2_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
>+//CM2_CM_DGAM_RAMB_START_CNTL_G
>+#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT                                 0x0
>+#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
>+#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK                                   0x0003FFFFL
>+#define CM2_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
>+//CM2_CM_DGAM_RAMB_START_CNTL_R
>+#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT                                 0x0
>+#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
>+#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK                                   0x0003FFFFL
>+#define CM2_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
>+//CM2_CM_DGAM_RAMB_SLOPE_CNTL_B
>+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
>+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
>+//CM2_CM_DGAM_RAMB_SLOPE_CNTL_G
>+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
>+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
>+//CM2_CM_DGAM_RAMB_SLOPE_CNTL_R
>+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
>+#define CM2_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
>+//CM2_CM_DGAM_RAMB_END_CNTL1_B
>+#define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT                                    0x0
>+#define CM2_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK                                      0x0000FFFFL
>+//CM2_CM_DGAM_RAMB_END_CNTL2_B
>+#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
>+#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
>+#define CM2_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
>+//CM2_CM_DGAM_RAMB_END_CNTL1_G
>+#define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT                                    0x0
>+#define CM2_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK                                      0x0000FFFFL
>+//CM2_CM_DGAM_RAMB_END_CNTL2_G
>+#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
>+#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
>+#define CM2_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
>+//CM2_CM_DGAM_RAMB_END_CNTL1_R
>+#define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT                                    0x0
>+#define CM2_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK                                      0x0000FFFFL
>+//CM2_CM_DGAM_RAMB_END_CNTL2_R
>+#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
>+#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
>+#define CM2_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
>+//CM2_CM_DGAM_RAMB_REGION_0_1
>+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
>+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM2_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM2_CM_DGAM_RAMB_REGION_2_3
>+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
>+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM2_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM2_CM_DGAM_RAMB_REGION_4_5
>+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
>+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM2_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM2_CM_DGAM_RAMB_REGION_6_7
>+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
>+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM2_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM2_CM_DGAM_RAMB_REGION_8_9
>+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
>+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
>+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM2_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM2_CM_DGAM_RAMB_REGION_10_11
>+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
>+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
>+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM2_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM2_CM_DGAM_RAMB_REGION_12_13
>+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
>+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
>+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM2_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM2_CM_DGAM_RAMB_REGION_14_15
>+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
>+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
>+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM2_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM2_CM_BLNDGAM_CONTROL
>+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT                                                    0x0
>+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK                                                      0x00000003L
>+//CM2_CM_BLNDGAM_LUT_INDEX
>+#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
>+#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
>+//CM2_CM_BLNDGAM_LUT_DATA
>+#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
>+#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0007FFFFL
>+//CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK
>+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT                                 0x0
>+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT                                     0x4
>+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT                                     0x8
>+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK                                   0x00000007L
>+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK                                       0x00000010L
>+#define CM2_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK                                       0x00000300L
>+//CM2_CM_BLNDGAM_RAMA_START_CNTL_B
>+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
>+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
>+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
>+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
>+//CM2_CM_BLNDGAM_RAMA_START_CNTL_G
>+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
>+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
>+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
>+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
>+//CM2_CM_BLNDGAM_RAMA_START_CNTL_R
>+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
>+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
>+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
>+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
>+//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
>+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
>+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
>+//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
>+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
>+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
>+//CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
>+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
>+#define CM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
>+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_B
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
>+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_B
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
>+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_G
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
>+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_G
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
>+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_R
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
>+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_R
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
>+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_0_1
>+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_2_3
>+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_4_5
>+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_6_7
>+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_8_9
>+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_10_11
>+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_12_13
>+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_14_15
>+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_16_17
>+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_18_19
>+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_20_21
>+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_22_23
>+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_24_25
>+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_26_27
>+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_28_29
>+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_30_31
>+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMA_REGION_32_33
>+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_START_CNTL_B
>+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
>+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
>+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
>+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
>+//CM2_CM_BLNDGAM_RAMB_START_CNTL_G
>+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
>+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
>+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
>+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
>+//CM2_CM_BLNDGAM_RAMB_START_CNTL_R
>+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
>+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
>+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
>+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
>+//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
>+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
>+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
>+//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
>+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
>+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
>+//CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
>+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
>+#define CM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
>+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_B
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
>+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_B
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
>+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_G
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
>+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_G
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
>+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_R
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
>+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_R
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
>+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_0_1
>+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_2_3
>+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_4_5
>+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_6_7
>+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_8_9
>+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_10_11
>+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_12_13
>+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_14_15
>+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_16_17
>+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_18_19
>+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_20_21
>+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_22_23
>+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_24_25
>+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_26_27
>+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_28_29
>+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_30_31
>+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_BLNDGAM_RAMB_REGION_32_33
>+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
>+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
>+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM2_CM_HDR_MULT_COEF
>+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
>+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
>+//CM2_CM_MEM_PWR_CTRL
>+#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT                                                      0x0
>+#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT                                                        0x2
>+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
>+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
>+#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK                                                        0x00000003L
>+#define CM2_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK                                                          0x00000004L
>+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
>+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
>+//CM2_CM_MEM_PWR_STATUS
>+#define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT                                                    0x0
>+#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
>+#define CM2_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK                                                      0x00000003L
>+#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
>+//CM2_CM_DEALPHA
>+#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
>+#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
>+//CM2_CM_COEF_FORMAT
>+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
>+#define CM2_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT                                                        0x4
>+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
>+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
>+#define CM2_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK                                                          0x00000010L
>+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
>+//CM2_CM_SHAPER_CONTROL
>+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
>+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
>+//CM2_CM_SHAPER_OFFSET_R
>+#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
>+#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
>+//CM2_CM_SHAPER_OFFSET_G
>+#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
>+#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
>+//CM2_CM_SHAPER_OFFSET_B
>+#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
>+#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
>+//CM2_CM_SHAPER_SCALE_R
>+#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
>+#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
>+//CM2_CM_SHAPER_SCALE_G_B
>+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
>+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
>+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
>+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
>+//CM2_CM_SHAPER_LUT_INDEX
>+#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
>+#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
>+//CM2_CM_SHAPER_LUT_DATA
>+#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
>+#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
>+//CM2_CM_SHAPER_LUT_WRITE_EN_MASK
>+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
>+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
>+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT                                       0x8
>+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
>+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
>+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK                                         0x00000300L
>+//CM2_CM_SHAPER_RAMA_START_CNTL_B
>+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
>+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
>+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
>+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
>+//CM2_CM_SHAPER_RAMA_START_CNTL_G
>+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
>+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
>+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
>+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
>+//CM2_CM_SHAPER_RAMA_START_CNTL_R
>+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
>+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
>+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
>+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
>+//CM2_CM_SHAPER_RAMA_END_CNTL_B
>+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
>+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
>+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
>+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
>+//CM2_CM_SHAPER_RAMA_END_CNTL_G
>+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
>+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
>+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
>+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
>+//CM2_CM_SHAPER_RAMA_END_CNTL_R
>+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
>+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
>+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
>+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
>+//CM2_CM_SHAPER_RAMA_REGION_0_1
>+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_2_3
>+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_4_5
>+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_6_7
>+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_8_9
>+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_10_11
>+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_12_13
>+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_14_15
>+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_16_17
>+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_18_19
>+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_20_21
>+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_22_23
>+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_24_25
>+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_26_27
>+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_28_29
>+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_30_31
>+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMA_REGION_32_33
>+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMB_START_CNTL_B
>+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
>+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
>+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
>+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
>+//CM2_CM_SHAPER_RAMB_START_CNTL_G
>+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
>+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
>+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
>+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
>+//CM2_CM_SHAPER_RAMB_START_CNTL_R
>+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
>+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
>+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
>+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
>+//CM2_CM_SHAPER_RAMB_END_CNTL_B
>+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
>+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
>+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
>+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
>+//CM2_CM_SHAPER_RAMB_END_CNTL_G
>+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
>+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
>+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
>+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
>+//CM2_CM_SHAPER_RAMB_END_CNTL_R
>+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
>+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
>+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
>+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
>+//CM2_CM_SHAPER_RAMB_REGION_0_1
>+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_2_3
>+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_4_5
>+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_6_7
>+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_8_9
>+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_10_11
>+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_12_13
>+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_14_15
>+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_16_17
>+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_18_19
>+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_20_21
>+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_22_23
>+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_24_25
>+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_26_27
>+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_28_29
>+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_30_31
>+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_SHAPER_RAMB_REGION_32_33
>+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
>+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
>+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM2_CM_MEM_PWR_CTRL2
>+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
>+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
>+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
>+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
>+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
>+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
>+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
>+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
>+//CM2_CM_MEM_PWR_STATUS2
>+#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
>+#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
>+#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
>+#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
>+//CM2_CM_3DLUT_MODE
>+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
>+#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
>+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
>+#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
>+//CM2_CM_3DLUT_INDEX
>+#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
>+#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
>+//CM2_CM_3DLUT_DATA
>+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
>+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
>+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
>+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
>+//CM2_CM_3DLUT_DATA_30BIT
>+#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
>+#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
>+//CM2_CM_3DLUT_READ_WRITE_CONTROL
>+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
>+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
>+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
>+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT                                        0xc
>+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
>+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
>+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
>+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
>+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK                                          0x00003000L
>+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
>+//CM2_CM_3DLUT_OUT_NORM_FACTOR
>+#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
>+#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
>+//CM2_CM_3DLUT_OUT_OFFSET_R
>+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
>+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
>+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
>+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
>+//CM2_CM_3DLUT_OUT_OFFSET_G
>+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
>+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
>+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
>+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
>+//CM2_CM_3DLUT_OUT_OFFSET_B
>+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
>+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
>+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
>+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
>+//CM2_CM_TEST_DEBUG_INDEX
>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
>+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
>+//CM2_CM_TEST_DEBUG_DATA
>+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
>+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON13_PERFCOUNTER_CNTL
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON13_PERFCOUNTER_CNTL2
>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON13_PERFCOUNTER_STATE
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON13_PERFMON_CNTL
>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON13_PERFMON_CNTL2
>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON13_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON13_PERFMON_CVALUE_LOW
>+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON13_PERFMON_HI
>+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON13_PERFMON_LOW
>+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
>+//DPP_TOP3_DPP_CONTROL
>+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE__SHIFT                                         0xe
>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0x10
>+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x12
>+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x14
>+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
>+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_ALPHA_GATE_DISABLE_MASK                                           0x00004000L
>+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00010000L
>+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00040000L
>+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00100000L
>+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0xF0000000L
>+//DPP_TOP3_DPP_SOFT_RESET
>+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
>+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
>+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
>+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
>+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
>+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
>+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
>+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
>+//DPP_TOP3_DPP_CRC_VAL_R_G
>+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
>+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
>+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
>+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
>+//DPP_TOP3_DPP_CRC_VAL_B_A
>+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
>+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
>+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
>+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
>+//DPP_TOP3_DPP_CRC_CTRL
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL__SHIFT                                                 0x6
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x7
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x8
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0xa
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xc
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xf
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_BITS_SEL_MASK                                                   0x00000040L
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000080L
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000300L
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000C00L
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00007000L
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x00008000L
>+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
>+//DPP_TOP3_HOST_READ_CONTROL
>+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
>+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
>+
>+
>+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
>+//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT
>+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
>+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
>+//CNVC_CFG3_FORMAT_CONTROL
>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
>+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
>+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
>+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
>+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
>+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
>+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
>+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
>+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
>+//CNVC_CFG3_FCNV_FP_BIAS_R
>+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
>+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
>+//CNVC_CFG3_FCNV_FP_BIAS_G
>+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
>+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
>+//CNVC_CFG3_FCNV_FP_BIAS_B
>+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
>+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
>+//CNVC_CFG3_FCNV_FP_SCALE_R
>+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
>+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
>+//CNVC_CFG3_FCNV_FP_SCALE_G
>+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
>+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
>+//CNVC_CFG3_FCNV_FP_SCALE_B
>+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
>+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
>+//CNVC_CFG3_COLOR_KEYER_CONTROL
>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
>+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
>+//CNVC_CFG3_COLOR_KEYER_ALPHA
>+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
>+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
>+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
>+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
>+//CNVC_CFG3_COLOR_KEYER_RED
>+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
>+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
>+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
>+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
>+//CNVC_CFG3_COLOR_KEYER_GREEN
>+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
>+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
>+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
>+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
>+//CNVC_CFG3_COLOR_KEYER_BLUE
>+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
>+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
>+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
>+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
>+//CNVC_CFG3_ALPHA_2BIT_LUT
>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
>+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
>+
>+
>+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
>+//CNVC_CUR3_CURSOR0_CONTROL
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
>+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
>+//CNVC_CUR3_CURSOR0_COLOR0
>+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
>+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
>+//CNVC_CUR3_CURSOR0_COLOR1
>+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
>+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
>+//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS
>+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
>+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
>+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
>+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
>+//DSCL3_SCL_COEF_RAM_TAP_SELECT
>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
>+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
>+//DSCL3_SCL_COEF_RAM_TAP_DATA
>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
>+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
>+//DSCL3_SCL_MODE
>+#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
>+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
>+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
>+#define DSCL3_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
>+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
>+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
>+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
>+//DSCL3_SCL_TAP_CONTROL
>+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
>+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
>+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
>+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
>+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
>+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
>+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
>+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
>+//DSCL3_DSCL_CONTROL
>+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
>+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
>+//DSCL3_DSCL_2TAP_CONTROL
>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
>+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
>+//DSCL3_SCL_MANUAL_REPLICATE_CONTROL
>+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
>+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
>+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
>+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
>+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO
>+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
>+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x03FFFFFFL
>+//DSCL3_SCL_HORZ_FILTER_INIT
>+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
>+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
>+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
>+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
>+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C
>+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
>+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
>+//DSCL3_SCL_HORZ_FILTER_INIT_C
>+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
>+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
>+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
>+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
>+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO
>+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
>+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x03FFFFFFL
>+//DSCL3_SCL_VERT_FILTER_INIT
>+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
>+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
>+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
>+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
>+//DSCL3_SCL_VERT_FILTER_INIT_BOT
>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
>+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C
>+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
>+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x03FFFFFFL
>+//DSCL3_SCL_VERT_FILTER_INIT_C
>+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
>+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
>+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
>+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
>+//DSCL3_SCL_VERT_FILTER_INIT_BOT_C
>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
>+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
>+//DSCL3_SCL_BLACK_OFFSET
>+#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y__SHIFT                                                 0x0
>+#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR__SHIFT                                                  0x10
>+#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_RGB_Y_MASK                                                   0x0000FFFFL
>+#define DSCL3_SCL_BLACK_OFFSET__SCL_BLACK_OFFSET_CBCR_MASK                                                    0xFFFF0000L
>+//DSCL3_DSCL_UPDATE
>+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
>+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
>+//DSCL3_DSCL_AUTOCAL
>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
>+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
>+//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT
>+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
>+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
>+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
>+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
>+//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM
>+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
>+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
>+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
>+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
>+//DSCL3_OTG_H_BLANK
>+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
>+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
>+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
>+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
>+//DSCL3_OTG_V_BLANK
>+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
>+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
>+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
>+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
>+//DSCL3_RECOUT_START
>+#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
>+#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
>+#define DSCL3_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
>+#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
>+//DSCL3_RECOUT_SIZE
>+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
>+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
>+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
>+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
>+//DSCL3_MPC_SIZE
>+#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
>+#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
>+#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
>+#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
>+//DSCL3_LB_DATA_FORMAT
>+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
>+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
>+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
>+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
>+//DSCL3_LB_MEMORY_CTRL
>+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
>+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
>+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
>+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
>+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
>+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
>+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
>+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
>+//DSCL3_LB_V_COUNTER
>+#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
>+#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
>+#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
>+#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
>+//DSCL3_DSCL_MEM_PWR_CTRL
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
>+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
>+//DSCL3_DSCL_MEM_PWR_STATUS
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
>+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
>+//DSCL3_OBUF_CONTROL
>+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
>+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x4
>+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0xc
>+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x1c
>+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
>+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000010L
>+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00001000L
>+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0xF0000000L
>+//DSCL3_OBUF_MEM_PWR_CTRL
>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
>+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
>+
>+
>+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
>+//CM3_CM_CONTROL
>+#define CM3_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
>+#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
>+#define CM3_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
>+#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
>+//CM3_CM_ICSC_CONTROL
>+#define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE__SHIFT                                                              0x0
>+#define CM3_CM_ICSC_CONTROL__CM_ICSC_MODE_MASK                                                                0x00000003L
>+//CM3_CM_ICSC_C11_C12
>+#define CM3_CM_ICSC_C11_C12__CM_ICSC_C11__SHIFT                                                               0x0
>+#define CM3_CM_ICSC_C11_C12__CM_ICSC_C12__SHIFT                                                               0x10
>+#define CM3_CM_ICSC_C11_C12__CM_ICSC_C11_MASK                                                                 0x0000FFFFL
>+#define CM3_CM_ICSC_C11_C12__CM_ICSC_C12_MASK                                                                 0xFFFF0000L
>+//CM3_CM_ICSC_C13_C14
>+#define CM3_CM_ICSC_C13_C14__CM_ICSC_C13__SHIFT                                                               0x0
>+#define CM3_CM_ICSC_C13_C14__CM_ICSC_C14__SHIFT                                                               0x10
>+#define CM3_CM_ICSC_C13_C14__CM_ICSC_C13_MASK                                                                 0x0000FFFFL
>+#define CM3_CM_ICSC_C13_C14__CM_ICSC_C14_MASK                                                                 0xFFFF0000L
>+//CM3_CM_ICSC_C21_C22
>+#define CM3_CM_ICSC_C21_C22__CM_ICSC_C21__SHIFT                                                               0x0
>+#define CM3_CM_ICSC_C21_C22__CM_ICSC_C22__SHIFT                                                               0x10
>+#define CM3_CM_ICSC_C21_C22__CM_ICSC_C21_MASK                                                                 0x0000FFFFL
>+#define CM3_CM_ICSC_C21_C22__CM_ICSC_C22_MASK                                                                 0xFFFF0000L
>+//CM3_CM_ICSC_C23_C24
>+#define CM3_CM_ICSC_C23_C24__CM_ICSC_C23__SHIFT                                                               0x0
>+#define CM3_CM_ICSC_C23_C24__CM_ICSC_C24__SHIFT                                                               0x10
>+#define CM3_CM_ICSC_C23_C24__CM_ICSC_C23_MASK                                                                 0x0000FFFFL
>+#define CM3_CM_ICSC_C23_C24__CM_ICSC_C24_MASK                                                                 0xFFFF0000L
>+//CM3_CM_ICSC_C31_C32
>+#define CM3_CM_ICSC_C31_C32__CM_ICSC_C31__SHIFT                                                               0x0
>+#define CM3_CM_ICSC_C31_C32__CM_ICSC_C32__SHIFT                                                               0x10
>+#define CM3_CM_ICSC_C31_C32__CM_ICSC_C31_MASK                                                                 0x0000FFFFL
>+#define CM3_CM_ICSC_C31_C32__CM_ICSC_C32_MASK                                                                 0xFFFF0000L
>+//CM3_CM_ICSC_C33_C34
>+#define CM3_CM_ICSC_C33_C34__CM_ICSC_C33__SHIFT                                                               0x0
>+#define CM3_CM_ICSC_C33_C34__CM_ICSC_C34__SHIFT                                                               0x10
>+#define CM3_CM_ICSC_C33_C34__CM_ICSC_C33_MASK                                                                 0x0000FFFFL
>+#define CM3_CM_ICSC_C33_C34__CM_ICSC_C34_MASK                                                                 0xFFFF0000L
>+//CM3_CM_ICSC_B_C11_C12
>+#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C11__SHIFT                                                           0x0
>+#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C12__SHIFT                                                           0x10
>+#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C11_MASK                                                             0x0000FFFFL
>+#define CM3_CM_ICSC_B_C11_C12__CM_ICSC_B_C12_MASK                                                             0xFFFF0000L
>+//CM3_CM_ICSC_B_C13_C14
>+#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C13__SHIFT                                                           0x0
>+#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C14__SHIFT                                                           0x10
>+#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C13_MASK                                                             0x0000FFFFL
>+#define CM3_CM_ICSC_B_C13_C14__CM_ICSC_B_C14_MASK                                                             0xFFFF0000L
>+//CM3_CM_ICSC_B_C21_C22
>+#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C21__SHIFT                                                           0x0
>+#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C22__SHIFT                                                           0x10
>+#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C21_MASK                                                             0x0000FFFFL
>+#define CM3_CM_ICSC_B_C21_C22__CM_ICSC_B_C22_MASK                                                             0xFFFF0000L
>+//CM3_CM_ICSC_B_C23_C24
>+#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C23__SHIFT                                                           0x0
>+#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C24__SHIFT                                                           0x10
>+#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C23_MASK                                                             0x0000FFFFL
>+#define CM3_CM_ICSC_B_C23_C24__CM_ICSC_B_C24_MASK                                                             0xFFFF0000L
>+//CM3_CM_ICSC_B_C31_C32
>+#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C31__SHIFT                                                           0x0
>+#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C32__SHIFT                                                           0x10
>+#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C31_MASK                                                             0x0000FFFFL
>+#define CM3_CM_ICSC_B_C31_C32__CM_ICSC_B_C32_MASK                                                             0xFFFF0000L
>+//CM3_CM_ICSC_B_C33_C34
>+#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C33__SHIFT                                                           0x0
>+#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C34__SHIFT                                                           0x10
>+#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C33_MASK                                                             0x0000FFFFL
>+#define CM3_CM_ICSC_B_C33_C34__CM_ICSC_B_C34_MASK                                                             0xFFFF0000L
>+//CM3_CM_GAMUT_REMAP_CONTROL
>+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
>+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
>+//CM3_CM_GAMUT_REMAP_C11_C12
>+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
>+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
>+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
>+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
>+//CM3_CM_GAMUT_REMAP_C13_C14
>+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
>+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
>+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
>+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
>+//CM3_CM_GAMUT_REMAP_C21_C22
>+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
>+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
>+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
>+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
>+//CM3_CM_GAMUT_REMAP_C23_C24
>+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
>+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
>+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
>+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
>+//CM3_CM_GAMUT_REMAP_C31_C32
>+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
>+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
>+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
>+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
>+//CM3_CM_GAMUT_REMAP_C33_C34
>+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
>+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
>+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
>+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
>+//CM3_CM_GAMUT_REMAP_B_C11_C12
>+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
>+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
>+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
>+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
>+//CM3_CM_GAMUT_REMAP_B_C13_C14
>+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
>+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
>+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
>+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
>+//CM3_CM_GAMUT_REMAP_B_C21_C22
>+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
>+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
>+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
>+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
>+//CM3_CM_GAMUT_REMAP_B_C23_C24
>+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
>+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
>+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
>+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
>+//CM3_CM_GAMUT_REMAP_B_C31_C32
>+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
>+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
>+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
>+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
>+//CM3_CM_GAMUT_REMAP_B_C33_C34
>+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
>+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
>+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
>+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
>+//CM3_CM_BIAS_CR_R
>+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
>+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
>+//CM3_CM_BIAS_Y_G_CB_B
>+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
>+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
>+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
>+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
>+//CM3_CM_DGAM_CONTROL
>+#define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE__SHIFT                                                          0x0
>+#define CM3_CM_DGAM_CONTROL__CM_DGAM_LUT_MODE_MASK                                                            0x00000007L
>+//CM3_CM_DGAM_LUT_INDEX
>+#define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX__SHIFT                                                       0x0
>+#define CM3_CM_DGAM_LUT_INDEX__CM_DGAM_LUT_INDEX_MASK                                                         0x000001FFL
>+//CM3_CM_DGAM_LUT_DATA
>+#define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA__SHIFT                                                         0x0
>+#define CM3_CM_DGAM_LUT_DATA__CM_DGAM_LUT_DATA_MASK                                                           0x0007FFFFL
>+//CM3_CM_DGAM_LUT_WRITE_EN_MASK
>+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK__SHIFT                                       0x0
>+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL__SHIFT                                           0x4
>+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS__SHIFT                                           0x8
>+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY__SHIFT                                     0xc
>+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_EN_MASK_MASK                                         0x00000007L
>+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_LUT_WRITE_SEL_MASK                                             0x00000010L
>+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_CONFIG_STATUS_MASK                                             0x00000700L
>+#define CM3_CM_DGAM_LUT_WRITE_EN_MASK__CM_DGAM_WRITE_LUT_BASE_ONLY_MASK                                       0x00001000L
>+//CM3_CM_DGAM_RAMA_START_CNTL_B
>+#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B__SHIFT                                 0x0
>+#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
>+#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_B_MASK                                   0x0003FFFFL
>+#define CM3_CM_DGAM_RAMA_START_CNTL_B__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
>+//CM3_CM_DGAM_RAMA_START_CNTL_G
>+#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G__SHIFT                                 0x0
>+#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
>+#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_G_MASK                                   0x0003FFFFL
>+#define CM3_CM_DGAM_RAMA_START_CNTL_G__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
>+//CM3_CM_DGAM_RAMA_START_CNTL_R
>+#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R__SHIFT                                 0x0
>+#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
>+#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_R_MASK                                   0x0003FFFFL
>+#define CM3_CM_DGAM_RAMA_START_CNTL_R__CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
>+//CM3_CM_DGAM_RAMA_SLOPE_CNTL_B
>+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
>+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_B__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
>+//CM3_CM_DGAM_RAMA_SLOPE_CNTL_G
>+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
>+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_G__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
>+//CM3_CM_DGAM_RAMA_SLOPE_CNTL_R
>+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
>+#define CM3_CM_DGAM_RAMA_SLOPE_CNTL_R__CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
>+//CM3_CM_DGAM_RAMA_END_CNTL1_B
>+#define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B__SHIFT                                    0x0
>+#define CM3_CM_DGAM_RAMA_END_CNTL1_B__CM_DGAM_RAMA_EXP_REGION_END_B_MASK                                      0x0000FFFFL
>+//CM3_CM_DGAM_RAMA_END_CNTL2_B
>+#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
>+#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
>+#define CM3_CM_DGAM_RAMA_END_CNTL2_B__CM_DGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
>+//CM3_CM_DGAM_RAMA_END_CNTL1_G
>+#define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G__SHIFT                                    0x0
>+#define CM3_CM_DGAM_RAMA_END_CNTL1_G__CM_DGAM_RAMA_EXP_REGION_END_G_MASK                                      0x0000FFFFL
>+//CM3_CM_DGAM_RAMA_END_CNTL2_G
>+#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
>+#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
>+#define CM3_CM_DGAM_RAMA_END_CNTL2_G__CM_DGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
>+//CM3_CM_DGAM_RAMA_END_CNTL1_R
>+#define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R__SHIFT                                    0x0
>+#define CM3_CM_DGAM_RAMA_END_CNTL1_R__CM_DGAM_RAMA_EXP_REGION_END_R_MASK                                      0x0000FFFFL
>+//CM3_CM_DGAM_RAMA_END_CNTL2_R
>+#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
>+#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
>+#define CM3_CM_DGAM_RAMA_END_CNTL2_R__CM_DGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
>+//CM3_CM_DGAM_RAMA_REGION_0_1
>+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
>+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM3_CM_DGAM_RAMA_REGION_0_1__CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM3_CM_DGAM_RAMA_REGION_2_3
>+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
>+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM3_CM_DGAM_RAMA_REGION_2_3__CM_DGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM3_CM_DGAM_RAMA_REGION_4_5
>+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
>+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM3_CM_DGAM_RAMA_REGION_4_5__CM_DGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM3_CM_DGAM_RAMA_REGION_6_7
>+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
>+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM3_CM_DGAM_RAMA_REGION_6_7__CM_DGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM3_CM_DGAM_RAMA_REGION_8_9
>+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
>+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM3_CM_DGAM_RAMA_REGION_8_9__CM_DGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM3_CM_DGAM_RAMA_REGION_10_11
>+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
>+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
>+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM3_CM_DGAM_RAMA_REGION_10_11__CM_DGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM3_CM_DGAM_RAMA_REGION_12_13
>+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
>+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
>+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM3_CM_DGAM_RAMA_REGION_12_13__CM_DGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM3_CM_DGAM_RAMA_REGION_14_15
>+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
>+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
>+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM3_CM_DGAM_RAMA_REGION_14_15__CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM3_CM_DGAM_RAMB_START_CNTL_B
>+#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B__SHIFT                                 0x0
>+#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                         0x14
>+#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_B_MASK                                   0x0003FFFFL
>+#define CM3_CM_DGAM_RAMB_START_CNTL_B__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                           0x07F00000L
>+//CM3_CM_DGAM_RAMB_START_CNTL_G
>+#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G__SHIFT                                 0x0
>+#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                         0x14
>+#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_G_MASK                                   0x0003FFFFL
>+#define CM3_CM_DGAM_RAMB_START_CNTL_G__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                           0x07F00000L
>+//CM3_CM_DGAM_RAMB_START_CNTL_R
>+#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R__SHIFT                                 0x0
>+#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                         0x14
>+#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_R_MASK                                   0x0003FFFFL
>+#define CM3_CM_DGAM_RAMB_START_CNTL_R__CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                           0x07F00000L
>+//CM3_CM_DGAM_RAMB_SLOPE_CNTL_B
>+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                          0x0
>+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_B__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                            0x0003FFFFL
>+//CM3_CM_DGAM_RAMB_SLOPE_CNTL_G
>+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                          0x0
>+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_G__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                            0x0003FFFFL
>+//CM3_CM_DGAM_RAMB_SLOPE_CNTL_R
>+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                          0x0
>+#define CM3_CM_DGAM_RAMB_SLOPE_CNTL_R__CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                            0x0003FFFFL
>+//CM3_CM_DGAM_RAMB_END_CNTL1_B
>+#define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B__SHIFT                                    0x0
>+#define CM3_CM_DGAM_RAMB_END_CNTL1_B__CM_DGAM_RAMB_EXP_REGION_END_B_MASK                                      0x0000FFFFL
>+//CM3_CM_DGAM_RAMB_END_CNTL2_B
>+#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                              0x0
>+#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                0x0000FFFFL
>+#define CM3_CM_DGAM_RAMB_END_CNTL2_B__CM_DGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                 0xFFFF0000L
>+//CM3_CM_DGAM_RAMB_END_CNTL1_G
>+#define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G__SHIFT                                    0x0
>+#define CM3_CM_DGAM_RAMB_END_CNTL1_G__CM_DGAM_RAMB_EXP_REGION_END_G_MASK                                      0x0000FFFFL
>+//CM3_CM_DGAM_RAMB_END_CNTL2_G
>+#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                              0x0
>+#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                0x0000FFFFL
>+#define CM3_CM_DGAM_RAMB_END_CNTL2_G__CM_DGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                 0xFFFF0000L
>+//CM3_CM_DGAM_RAMB_END_CNTL1_R
>+#define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R__SHIFT                                    0x0
>+#define CM3_CM_DGAM_RAMB_END_CNTL1_R__CM_DGAM_RAMB_EXP_REGION_END_R_MASK                                      0x0000FFFFL
>+//CM3_CM_DGAM_RAMB_END_CNTL2_R
>+#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                              0x0
>+#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                0x0000FFFFL
>+#define CM3_CM_DGAM_RAMB_END_CNTL2_R__CM_DGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                 0xFFFF0000L
>+//CM3_CM_DGAM_RAMB_REGION_0_1
>+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                               0x0
>+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM3_CM_DGAM_RAMB_REGION_0_1__CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM3_CM_DGAM_RAMB_REGION_2_3
>+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                               0x0
>+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM3_CM_DGAM_RAMB_REGION_2_3__CM_DGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM3_CM_DGAM_RAMB_REGION_4_5
>+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                               0x0
>+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM3_CM_DGAM_RAMB_REGION_4_5__CM_DGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM3_CM_DGAM_RAMB_REGION_6_7
>+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                               0x0
>+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM3_CM_DGAM_RAMB_REGION_6_7__CM_DGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM3_CM_DGAM_RAMB_REGION_8_9
>+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                               0x0
>+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                             0xc
>+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                               0x10
>+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                             0x1c
>+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                 0x000001FFL
>+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                               0x00007000L
>+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                 0x01FF0000L
>+#define CM3_CM_DGAM_RAMB_REGION_8_9__CM_DGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                               0x70000000L
>+//CM3_CM_DGAM_RAMB_REGION_10_11
>+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                            0x0
>+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                            0x10
>+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM3_CM_DGAM_RAMB_REGION_10_11__CM_DGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM3_CM_DGAM_RAMB_REGION_12_13
>+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                            0x0
>+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                            0x10
>+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM3_CM_DGAM_RAMB_REGION_12_13__CM_DGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM3_CM_DGAM_RAMB_REGION_14_15
>+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                            0x0
>+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                          0xc
>+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                            0x10
>+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                          0x1c
>+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                              0x000001FFL
>+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                            0x00007000L
>+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                              0x01FF0000L
>+#define CM3_CM_DGAM_RAMB_REGION_14_15__CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                            0x70000000L
>+//CM3_CM_BLNDGAM_CONTROL
>+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE__SHIFT                                                    0x0
>+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_LUT_MODE_MASK                                                      0x00000003L
>+//CM3_CM_BLNDGAM_LUT_INDEX
>+#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
>+#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
>+//CM3_CM_BLNDGAM_LUT_DATA
>+#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
>+#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0007FFFFL
>+//CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK
>+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK__SHIFT                                 0x0
>+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL__SHIFT                                     0x4
>+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS__SHIFT                                     0x8
>+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_EN_MASK_MASK                                   0x00000007L
>+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_LUT_WRITE_SEL_MASK                                       0x00000010L
>+#define CM3_CM_BLNDGAM_LUT_WRITE_EN_MASK__CM_BLNDGAM_CONFIG_STATUS_MASK                                       0x00000300L
>+//CM3_CM_BLNDGAM_RAMA_START_CNTL_B
>+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
>+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
>+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
>+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
>+//CM3_CM_BLNDGAM_RAMA_START_CNTL_G
>+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
>+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
>+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
>+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
>+//CM3_CM_BLNDGAM_RAMA_START_CNTL_R
>+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
>+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
>+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
>+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
>+//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B
>+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
>+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
>+//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G
>+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
>+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
>+//CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R
>+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
>+#define CM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
>+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_B
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
>+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_B
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
>+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_G
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
>+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_G
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
>+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_R
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
>+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_R
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
>+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_0_1
>+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_2_3
>+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_4_5
>+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_6_7
>+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_8_9
>+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_10_11
>+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_12_13
>+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_14_15
>+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_16_17
>+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_18_19
>+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_20_21
>+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_22_23
>+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_24_25
>+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_26_27
>+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_28_29
>+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_30_31
>+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMA_REGION_32_33
>+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_START_CNTL_B
>+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
>+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
>+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
>+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
>+//CM3_CM_BLNDGAM_RAMB_START_CNTL_G
>+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
>+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
>+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
>+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
>+//CM3_CM_BLNDGAM_RAMB_START_CNTL_R
>+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
>+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
>+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
>+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
>+//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B
>+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT                    0x0
>+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                      0x0003FFFFL
>+//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G
>+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT                    0x0
>+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                      0x0003FFFFL
>+//CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R
>+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT                    0x0
>+#define CM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                      0x0003FFFFL
>+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_B
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
>+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_B
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x0
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0x0000FFFFL
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0xFFFF0000L
>+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_G
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
>+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_G
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x0
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0x0000FFFFL
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0xFFFF0000L
>+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_R
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
>+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_R
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x0
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0x0000FFFFL
>+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0xFFFF0000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_0_1
>+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_2_3
>+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_4_5
>+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_6_7
>+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_8_9
>+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_10_11
>+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_12_13
>+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_14_15
>+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_16_17
>+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_18_19
>+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_20_21
>+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_22_23
>+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_24_25
>+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_26_27
>+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_28_29
>+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_30_31
>+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_BLNDGAM_RAMB_REGION_32_33
>+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
>+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
>+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
>+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
>+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
>+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
>+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
>+//CM3_CM_HDR_MULT_COEF
>+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
>+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
>+//CM3_CM_MEM_PWR_CTRL
>+#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE__SHIFT                                                      0x0
>+#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS__SHIFT                                                        0x2
>+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
>+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
>+#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_FORCE_MASK                                                        0x00000003L
>+#define CM3_CM_MEM_PWR_CTRL__SHARED_MEM_PWR_DIS_MASK                                                          0x00000004L
>+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
>+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
>+//CM3_CM_MEM_PWR_STATUS
>+#define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE__SHIFT                                                    0x0
>+#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
>+#define CM3_CM_MEM_PWR_STATUS__SHARED_MEM_PWR_STATE_MASK                                                      0x00000003L
>+#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
>+//CM3_CM_DEALPHA
>+#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
>+#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
>+//CM3_CM_COEF_FORMAT
>+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
>+#define CM3_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT__SHIFT                                                        0x4
>+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
>+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
>+#define CM3_CM_COEF_FORMAT__CM_ICSC_COEF_FORMAT_MASK                                                          0x00000010L
>+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
>+//CM3_CM_SHAPER_CONTROL
>+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
>+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
>+//CM3_CM_SHAPER_OFFSET_R
>+#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
>+#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
>+//CM3_CM_SHAPER_OFFSET_G
>+#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
>+#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
>+//CM3_CM_SHAPER_OFFSET_B
>+#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
>+#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
>+//CM3_CM_SHAPER_SCALE_R
>+#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
>+#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
>+//CM3_CM_SHAPER_SCALE_G_B
>+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
>+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
>+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
>+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
>+//CM3_CM_SHAPER_LUT_INDEX
>+#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
>+#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
>+//CM3_CM_SHAPER_LUT_DATA
>+#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
>+#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
>+//CM3_CM_SHAPER_LUT_WRITE_EN_MASK
>+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
>+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
>+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS__SHIFT                                       0x8
>+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
>+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
>+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_CONFIG_STATUS_MASK                                         0x00000300L
>+//CM3_CM_SHAPER_RAMA_START_CNTL_B
>+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
>+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
>+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
>+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
>+//CM3_CM_SHAPER_RAMA_START_CNTL_G
>+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
>+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
>+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
>+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
>+//CM3_CM_SHAPER_RAMA_START_CNTL_R
>+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
>+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
>+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
>+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
>+//CM3_CM_SHAPER_RAMA_END_CNTL_B
>+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
>+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
>+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
>+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
>+//CM3_CM_SHAPER_RAMA_END_CNTL_G
>+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
>+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
>+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
>+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
>+//CM3_CM_SHAPER_RAMA_END_CNTL_R
>+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
>+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
>+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
>+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
>+//CM3_CM_SHAPER_RAMA_REGION_0_1
>+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_2_3
>+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_4_5
>+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_6_7
>+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_8_9
>+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_10_11
>+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_12_13
>+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_14_15
>+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_16_17
>+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_18_19
>+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_20_21
>+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_22_23
>+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_24_25
>+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_26_27
>+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_28_29
>+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_30_31
>+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMA_REGION_32_33
>+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMB_START_CNTL_B
>+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
>+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
>+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
>+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
>+//CM3_CM_SHAPER_RAMB_START_CNTL_G
>+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
>+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
>+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
>+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
>+//CM3_CM_SHAPER_RAMB_START_CNTL_R
>+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
>+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
>+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
>+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
>+//CM3_CM_SHAPER_RAMB_END_CNTL_B
>+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
>+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
>+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
>+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
>+//CM3_CM_SHAPER_RAMB_END_CNTL_G
>+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
>+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
>+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
>+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
>+//CM3_CM_SHAPER_RAMB_END_CNTL_R
>+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
>+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
>+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
>+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
>+//CM3_CM_SHAPER_RAMB_REGION_0_1
>+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_2_3
>+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_4_5
>+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_6_7
>+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_8_9
>+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_10_11
>+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_12_13
>+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_14_15
>+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_16_17
>+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_18_19
>+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_20_21
>+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_22_23
>+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_24_25
>+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_26_27
>+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_28_29
>+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_30_31
>+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_SHAPER_RAMB_REGION_32_33
>+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
>+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
>+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
>+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
>+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
>+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
>+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
>+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
>+//CM3_CM_MEM_PWR_CTRL2
>+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
>+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
>+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
>+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
>+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
>+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
>+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
>+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
>+//CM3_CM_MEM_PWR_STATUS2
>+#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
>+#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
>+#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
>+#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
>+//CM3_CM_3DLUT_MODE
>+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
>+#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
>+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
>+#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
>+//CM3_CM_3DLUT_INDEX
>+#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
>+#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
>+//CM3_CM_3DLUT_DATA
>+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
>+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
>+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
>+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
>+//CM3_CM_3DLUT_DATA_30BIT
>+#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
>+#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
>+//CM3_CM_3DLUT_READ_WRITE_CONTROL
>+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
>+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
>+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
>+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS__SHIFT                                        0xc
>+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
>+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
>+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
>+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
>+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_CONFIG_STATUS_MASK                                          0x00003000L
>+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
>+//CM3_CM_3DLUT_OUT_NORM_FACTOR
>+#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
>+#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
>+//CM3_CM_3DLUT_OUT_OFFSET_R
>+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
>+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
>+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
>+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
>+//CM3_CM_3DLUT_OUT_OFFSET_G
>+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
>+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
>+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
>+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
>+//CM3_CM_3DLUT_OUT_OFFSET_B
>+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
>+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
>+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
>+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
>+//CM3_CM_TEST_DEBUG_INDEX
>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
>+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
>+//CM3_CM_TEST_DEBUG_DATA
>+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
>+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON14_PERFCOUNTER_CNTL
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON14_PERFCOUNTER_CNTL2
>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON14_PERFCOUNTER_STATE
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON14_PERFMON_CNTL
>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON14_PERFMON_CNTL2
>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON14_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON14_PERFMON_CVALUE_LOW
>+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON14_PERFMON_HI
>+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON14_PERFMON_LOW
>+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc0_dispdec
>+//MPCC0_MPCC_TOP_SEL
>+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
>+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
>+//MPCC0_MPCC_BOT_SEL
>+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
>+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
>+//MPCC0_MPCC_OPP_ID
>+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
>+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
>+//MPCC0_MPCC_CONTROL
>+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
>+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
>+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
>+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
>+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
>+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
>+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
>+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
>+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
>+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
>+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
>+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
>+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
>+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
>+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
>+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
>+//MPCC0_MPCC_SM_CONTROL
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
>+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
>+//MPCC0_MPCC_UPDATE_LOCK_SEL
>+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
>+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
>+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
>+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
>+//MPCC0_MPCC_TOP_GAIN
>+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
>+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
>+//MPCC0_MPCC_BOT_GAIN_INSIDE
>+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
>+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
>+//MPCC0_MPCC_BOT_GAIN_OUTSIDE
>+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
>+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
>+//MPCC0_MPCC_BG_R_CR
>+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
>+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
>+//MPCC0_MPCC_BG_G_Y
>+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
>+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
>+//MPCC0_MPCC_BG_B_CB
>+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
>+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
>+//MPCC0_MPCC_MEM_PWR_CTRL
>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
>+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
>+//MPCC0_MPCC_STALL_STATUS
>+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
>+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
>+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
>+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
>+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
>+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
>+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
>+#define MPCC0_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
>+//MPCC0_MPCC_STATUS
>+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
>+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
>+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
>+#define MPCC0_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
>+#define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
>+#define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
>+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
>+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
>+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
>+#define MPCC0_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
>+#define MPCC0_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
>+#define MPCC0_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc1_dispdec
>+//MPCC1_MPCC_TOP_SEL
>+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
>+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
>+//MPCC1_MPCC_BOT_SEL
>+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
>+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
>+//MPCC1_MPCC_OPP_ID
>+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
>+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
>+//MPCC1_MPCC_CONTROL
>+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
>+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
>+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
>+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
>+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
>+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
>+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
>+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
>+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
>+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
>+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
>+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
>+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
>+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
>+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
>+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
>+//MPCC1_MPCC_SM_CONTROL
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
>+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
>+//MPCC1_MPCC_UPDATE_LOCK_SEL
>+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
>+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
>+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
>+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
>+//MPCC1_MPCC_TOP_GAIN
>+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
>+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
>+//MPCC1_MPCC_BOT_GAIN_INSIDE
>+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
>+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
>+//MPCC1_MPCC_BOT_GAIN_OUTSIDE
>+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
>+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
>+//MPCC1_MPCC_BG_R_CR
>+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
>+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
>+//MPCC1_MPCC_BG_G_Y
>+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
>+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
>+//MPCC1_MPCC_BG_B_CB
>+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
>+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
>+//MPCC1_MPCC_MEM_PWR_CTRL
>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
>+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
>+//MPCC1_MPCC_STALL_STATUS
>+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
>+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
>+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
>+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
>+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
>+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
>+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
>+#define MPCC1_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
>+//MPCC1_MPCC_STATUS
>+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
>+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
>+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
>+#define MPCC1_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
>+#define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
>+#define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
>+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
>+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
>+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
>+#define MPCC1_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
>+#define MPCC1_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
>+#define MPCC1_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc2_dispdec
>+//MPCC2_MPCC_TOP_SEL
>+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
>+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
>+//MPCC2_MPCC_BOT_SEL
>+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
>+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
>+//MPCC2_MPCC_OPP_ID
>+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
>+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
>+//MPCC2_MPCC_CONTROL
>+#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
>+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
>+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
>+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
>+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
>+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
>+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
>+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
>+#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
>+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
>+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
>+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
>+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
>+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
>+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
>+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
>+//MPCC2_MPCC_SM_CONTROL
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
>+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
>+//MPCC2_MPCC_UPDATE_LOCK_SEL
>+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
>+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
>+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
>+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
>+//MPCC2_MPCC_TOP_GAIN
>+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
>+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
>+//MPCC2_MPCC_BOT_GAIN_INSIDE
>+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
>+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
>+//MPCC2_MPCC_BOT_GAIN_OUTSIDE
>+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
>+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
>+//MPCC2_MPCC_BG_R_CR
>+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
>+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
>+//MPCC2_MPCC_BG_G_Y
>+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
>+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
>+//MPCC2_MPCC_BG_B_CB
>+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
>+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
>+//MPCC2_MPCC_MEM_PWR_CTRL
>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
>+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
>+//MPCC2_MPCC_STALL_STATUS
>+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
>+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
>+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
>+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
>+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
>+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
>+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
>+#define MPCC2_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
>+//MPCC2_MPCC_STATUS
>+#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
>+#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
>+#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
>+#define MPCC2_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
>+#define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
>+#define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
>+#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
>+#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
>+#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
>+#define MPCC2_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
>+#define MPCC2_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
>+#define MPCC2_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc3_dispdec
>+//MPCC3_MPCC_TOP_SEL
>+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
>+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
>+//MPCC3_MPCC_BOT_SEL
>+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
>+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
>+//MPCC3_MPCC_OPP_ID
>+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
>+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
>+//MPCC3_MPCC_CONTROL
>+#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
>+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
>+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
>+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
>+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
>+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
>+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
>+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
>+#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
>+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
>+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
>+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
>+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
>+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
>+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
>+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
>+//MPCC3_MPCC_SM_CONTROL
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
>+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
>+//MPCC3_MPCC_UPDATE_LOCK_SEL
>+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
>+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
>+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
>+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
>+//MPCC3_MPCC_TOP_GAIN
>+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
>+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
>+//MPCC3_MPCC_BOT_GAIN_INSIDE
>+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
>+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
>+//MPCC3_MPCC_BOT_GAIN_OUTSIDE
>+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
>+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
>+//MPCC3_MPCC_BG_R_CR
>+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
>+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
>+//MPCC3_MPCC_BG_G_Y
>+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
>+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
>+//MPCC3_MPCC_BG_B_CB
>+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
>+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
>+//MPCC3_MPCC_MEM_PWR_CTRL
>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
>+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
>+//MPCC3_MPCC_STALL_STATUS
>+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
>+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
>+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
>+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
>+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
>+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
>+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
>+#define MPCC3_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
>+//MPCC3_MPCC_STATUS
>+#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
>+#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
>+#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
>+#define MPCC3_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
>+#define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
>+#define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
>+#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
>+#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
>+#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
>+#define MPCC3_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
>+#define MPCC3_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
>+#define MPCC3_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc4_dispdec
>+//MPCC4_MPCC_TOP_SEL
>+#define MPCC4_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
>+#define MPCC4_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
>+//MPCC4_MPCC_BOT_SEL
>+#define MPCC4_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
>+#define MPCC4_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
>+//MPCC4_MPCC_OPP_ID
>+#define MPCC4_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
>+#define MPCC4_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
>+//MPCC4_MPCC_CONTROL
>+#define MPCC4_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
>+#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
>+#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
>+#define MPCC4_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
>+#define MPCC4_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
>+#define MPCC4_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
>+#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
>+#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
>+#define MPCC4_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
>+#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
>+#define MPCC4_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
>+#define MPCC4_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
>+#define MPCC4_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
>+#define MPCC4_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
>+#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
>+#define MPCC4_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
>+//MPCC4_MPCC_SM_CONTROL
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
>+#define MPCC4_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
>+//MPCC4_MPCC_UPDATE_LOCK_SEL
>+#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
>+#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
>+#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
>+#define MPCC4_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
>+//MPCC4_MPCC_TOP_GAIN
>+#define MPCC4_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
>+#define MPCC4_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
>+//MPCC4_MPCC_BOT_GAIN_INSIDE
>+#define MPCC4_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
>+#define MPCC4_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
>+//MPCC4_MPCC_BOT_GAIN_OUTSIDE
>+#define MPCC4_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
>+#define MPCC4_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
>+//MPCC4_MPCC_BG_R_CR
>+#define MPCC4_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
>+#define MPCC4_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
>+//MPCC4_MPCC_BG_G_Y
>+#define MPCC4_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
>+#define MPCC4_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
>+//MPCC4_MPCC_BG_B_CB
>+#define MPCC4_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
>+#define MPCC4_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
>+//MPCC4_MPCC_MEM_PWR_CTRL
>+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
>+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
>+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
>+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
>+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
>+#define MPCC4_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
>+//MPCC4_MPCC_STALL_STATUS
>+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
>+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
>+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
>+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
>+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
>+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
>+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
>+#define MPCC4_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
>+//MPCC4_MPCC_STATUS
>+#define MPCC4_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
>+#define MPCC4_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
>+#define MPCC4_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
>+#define MPCC4_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
>+#define MPCC4_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
>+#define MPCC4_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
>+#define MPCC4_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
>+#define MPCC4_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
>+#define MPCC4_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
>+#define MPCC4_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
>+#define MPCC4_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
>+#define MPCC4_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc5_dispdec
>+//MPCC5_MPCC_TOP_SEL
>+#define MPCC5_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
>+#define MPCC5_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
>+//MPCC5_MPCC_BOT_SEL
>+#define MPCC5_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
>+#define MPCC5_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
>+//MPCC5_MPCC_OPP_ID
>+#define MPCC5_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
>+#define MPCC5_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
>+//MPCC5_MPCC_CONTROL
>+#define MPCC5_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
>+#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
>+#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
>+#define MPCC5_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
>+#define MPCC5_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
>+#define MPCC5_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
>+#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
>+#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
>+#define MPCC5_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
>+#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
>+#define MPCC5_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
>+#define MPCC5_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
>+#define MPCC5_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
>+#define MPCC5_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
>+#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
>+#define MPCC5_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
>+//MPCC5_MPCC_SM_CONTROL
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
>+#define MPCC5_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
>+//MPCC5_MPCC_UPDATE_LOCK_SEL
>+#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
>+#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
>+#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
>+#define MPCC5_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
>+//MPCC5_MPCC_TOP_GAIN
>+#define MPCC5_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
>+#define MPCC5_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
>+//MPCC5_MPCC_BOT_GAIN_INSIDE
>+#define MPCC5_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
>+#define MPCC5_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
>+//MPCC5_MPCC_BOT_GAIN_OUTSIDE
>+#define MPCC5_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
>+#define MPCC5_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
>+//MPCC5_MPCC_BG_R_CR
>+#define MPCC5_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
>+#define MPCC5_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
>+//MPCC5_MPCC_BG_G_Y
>+#define MPCC5_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
>+#define MPCC5_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
>+//MPCC5_MPCC_BG_B_CB
>+#define MPCC5_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
>+#define MPCC5_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
>+//MPCC5_MPCC_MEM_PWR_CTRL
>+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
>+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
>+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
>+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
>+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
>+#define MPCC5_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
>+//MPCC5_MPCC_STALL_STATUS
>+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
>+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
>+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
>+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
>+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
>+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
>+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
>+#define MPCC5_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
>+//MPCC5_MPCC_STATUS
>+#define MPCC5_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
>+#define MPCC5_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
>+#define MPCC5_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
>+#define MPCC5_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
>+#define MPCC5_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
>+#define MPCC5_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
>+#define MPCC5_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
>+#define MPCC5_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
>+#define MPCC5_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
>+#define MPCC5_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
>+#define MPCC5_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
>+#define MPCC5_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc6_dispdec
>+//MPCC6_MPCC_TOP_SEL
>+#define MPCC6_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
>+#define MPCC6_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
>+//MPCC6_MPCC_BOT_SEL
>+#define MPCC6_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
>+#define MPCC6_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
>+//MPCC6_MPCC_OPP_ID
>+#define MPCC6_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
>+#define MPCC6_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
>+//MPCC6_MPCC_CONTROL
>+#define MPCC6_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
>+#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
>+#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
>+#define MPCC6_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
>+#define MPCC6_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
>+#define MPCC6_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
>+#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
>+#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
>+#define MPCC6_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
>+#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
>+#define MPCC6_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
>+#define MPCC6_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
>+#define MPCC6_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
>+#define MPCC6_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
>+#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
>+#define MPCC6_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
>+//MPCC6_MPCC_SM_CONTROL
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
>+#define MPCC6_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
>+//MPCC6_MPCC_UPDATE_LOCK_SEL
>+#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
>+#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
>+#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
>+#define MPCC6_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
>+//MPCC6_MPCC_TOP_GAIN
>+#define MPCC6_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
>+#define MPCC6_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
>+//MPCC6_MPCC_BOT_GAIN_INSIDE
>+#define MPCC6_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
>+#define MPCC6_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
>+//MPCC6_MPCC_BOT_GAIN_OUTSIDE
>+#define MPCC6_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
>+#define MPCC6_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
>+//MPCC6_MPCC_BG_R_CR
>+#define MPCC6_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
>+#define MPCC6_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
>+//MPCC6_MPCC_BG_G_Y
>+#define MPCC6_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
>+#define MPCC6_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
>+//MPCC6_MPCC_BG_B_CB
>+#define MPCC6_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
>+#define MPCC6_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
>+//MPCC6_MPCC_MEM_PWR_CTRL
>+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
>+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
>+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
>+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
>+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
>+#define MPCC6_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
>+//MPCC6_MPCC_STALL_STATUS
>+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
>+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
>+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
>+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
>+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
>+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
>+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
>+#define MPCC6_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
>+//MPCC6_MPCC_STATUS
>+#define MPCC6_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
>+#define MPCC6_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
>+#define MPCC6_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
>+#define MPCC6_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
>+#define MPCC6_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
>+#define MPCC6_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
>+#define MPCC6_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
>+#define MPCC6_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
>+#define MPCC6_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
>+#define MPCC6_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
>+#define MPCC6_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
>+#define MPCC6_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc7_dispdec
>+//MPCC7_MPCC_TOP_SEL
>+#define MPCC7_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
>+#define MPCC7_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
>+//MPCC7_MPCC_BOT_SEL
>+#define MPCC7_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
>+#define MPCC7_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
>+//MPCC7_MPCC_OPP_ID
>+#define MPCC7_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
>+#define MPCC7_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
>+//MPCC7_MPCC_CONTROL
>+#define MPCC7_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
>+#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
>+#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
>+#define MPCC7_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
>+#define MPCC7_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
>+#define MPCC7_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
>+#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
>+#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
>+#define MPCC7_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
>+#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
>+#define MPCC7_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
>+#define MPCC7_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
>+#define MPCC7_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
>+#define MPCC7_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
>+#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
>+#define MPCC7_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
>+//MPCC7_MPCC_SM_CONTROL
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
>+#define MPCC7_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
>+//MPCC7_MPCC_UPDATE_LOCK_SEL
>+#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
>+#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
>+#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
>+#define MPCC7_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
>+//MPCC7_MPCC_TOP_GAIN
>+#define MPCC7_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
>+#define MPCC7_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
>+//MPCC7_MPCC_BOT_GAIN_INSIDE
>+#define MPCC7_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
>+#define MPCC7_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
>+//MPCC7_MPCC_BOT_GAIN_OUTSIDE
>+#define MPCC7_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
>+#define MPCC7_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
>+//MPCC7_MPCC_BG_R_CR
>+#define MPCC7_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
>+#define MPCC7_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
>+//MPCC7_MPCC_BG_G_Y
>+#define MPCC7_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
>+#define MPCC7_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
>+//MPCC7_MPCC_BG_B_CB
>+#define MPCC7_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
>+#define MPCC7_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
>+//MPCC7_MPCC_MEM_PWR_CTRL
>+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
>+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
>+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x4
>+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
>+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
>+#define MPCC7_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000030L
>+//MPCC7_MPCC_STALL_STATUS
>+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED__SHIFT                                                0x0
>+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE__SHIFT                                                   0x4
>+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK__SHIFT                                                    0x8
>+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK__SHIFT                                                   0xc
>+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_OCCURED_MASK                                                  0x00000001L
>+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_TYPE_MASK                                                     0x00000010L
>+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_ACK_MASK                                                      0x00000100L
>+#define MPCC7_MPCC_STALL_STATUS__MPCC_STALL_INT_MASK_MASK                                                     0x00001000L
>+//MPCC7_MPCC_STATUS
>+#define MPCC7_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
>+#define MPCC7_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
>+#define MPCC7_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
>+#define MPCC7_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR__SHIFT                                                     0x1d
>+#define MPCC7_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE__SHIFT                                                 0x1e
>+#define MPCC7_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK__SHIFT                                                      0x1f
>+#define MPCC7_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
>+#define MPCC7_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
>+#define MPCC7_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
>+#define MPCC7_MPCC_STATUS__DPP_MPCC_PIX_DATA_ERROR_MASK                                                       0x20000000L
>+#define MPCC7_MPCC_STATUS__DPP_MPCC_INPUT_CHECK_ENABLE_MASK                                                   0x40000000L
>+#define MPCC7_MPCC_STATUS__DPP_MPCC_EXCEPTION_ACK_MASK                                                        0x80000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
>+//MPC_CLOCK_CONTROL
>+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                      0x1
>+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT                                                            0x4
>+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                        0x00000002L
>+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK                                                              0x00000030L
>+//MPC_SOFT_RESET
>+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT                                                               0x0
>+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT                                                               0x1
>+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT                                                               0x2
>+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT                                                               0x3
>+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT                                                            0xa
>+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT                                                            0xb
>+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT                                                            0xc
>+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT                                                            0xd
>+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT                                                            0x14
>+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT                                                            0x15
>+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT                                                            0x16
>+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT                                                            0x17
>+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x1f
>+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK                                                                 0x00000001L
>+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK                                                                 0x00000002L
>+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK                                                                 0x00000004L
>+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK                                                                 0x00000008L
>+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK                                                              0x00000400L
>+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK                                                              0x00000800L
>+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK                                                              0x00001000L
>+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK                                                              0x00002000L
>+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK                                                              0x00100000L
>+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK                                                              0x00200000L
>+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK                                                              0x00400000L
>+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK                                                              0x00800000L
>+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x80000000L
>+//MPC_CRC_CTRL
>+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT                                                                       0x0
>+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT                                                                  0x4
>+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT                                                              0x8
>+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT                                                                0xa
>+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT                                                           0xc
>+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT                                                                  0x18
>+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT                                                         0x1c
>+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT                                                           0x1e
>+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT                                                              0x1f
>+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK                                                                         0x00000001L
>+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK                                                                    0x00000010L
>+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK                                                                0x00000300L
>+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK                                                                  0x00000400L
>+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK                                                             0x00003000L
>+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK                                                                    0x03000000L
>+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK                                                           0x10000000L
>+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK                                                             0x40000000L
>+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK                                                                0x80000000L
>+//MPC_CRC_SEL_CONTROL
>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT                                                           0x0
>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT                                                           0x4
>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT                                                              0x10
>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK                                                             0x0000000FL
>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK                                                             0x000000F0L
>+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK                                                                0xFFFF0000L
>+//MPC_CRC_RESULT_AR
>+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT                                                            0x0
>+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT                                                            0x10
>+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK                                                              0x0000FFFFL
>+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK                                                              0xFFFF0000L
>+//MPC_CRC_RESULT_GB
>+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT                                                            0x0
>+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT                                                            0x10
>+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK                                                              0x0000FFFFL
>+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK                                                              0xFFFF0000L
>+//MPC_CRC_RESULT_C
>+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT                                                             0x0
>+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK                                                               0x0000FFFFL
>+//MPC_PERFMON_EVENT_CTRL
>+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT                                                   0x0
>+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK                                                     0x00000001L
>+//MPC_BYPASS_BG_AR
>+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT                                                          0x0
>+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT                                                           0x10
>+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK                                                            0x0000FFFFL
>+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK                                                             0xFFFF0000L
>+//MPC_BYPASS_BG_GB
>+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT                                                            0x0
>+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT                                                           0x10
>+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK                                                              0x0000FFFFL
>+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK                                                             0xFFFF0000L
>+//MPC_STALL_GRACE_WINDOW
>+#define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD__SHIFT                                          0x0
>+#define MPC_STALL_GRACE_WINDOW__MPC_STALL_GRACE_WINDOW_PERIOD_MASK                                            0x000000FFL
>+//MPC_HOST_READ_CONTROL
>+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                                  0x0
>+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                                    0x000000FFL
>+//MPC_PENDING_TAKEN_STATUS_REG1
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT                                  0x0
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_TAKEN__SHIFT                                    0x1
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT                                   0x2
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_TAKEN__SHIFT                                     0x3
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT                                   0x4
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_TAKEN__SHIFT                                     0x5
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT                                  0x6
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_TAKEN__SHIFT                                    0x7
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT                                   0x8
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_TAKEN__SHIFT                                     0x9
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT                                   0xa
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_TAKEN__SHIFT                                     0xb
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT                                  0xc
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_TAKEN__SHIFT                                    0xd
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT                                   0xe
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_TAKEN__SHIFT                                     0xf
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT                                   0x10
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_TAKEN__SHIFT                                     0x11
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT                                  0x12
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_TAKEN__SHIFT                                    0x13
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT                                   0x14
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_TAKEN__SHIFT                                     0x15
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT                                   0x16
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_TAKEN__SHIFT                                     0x17
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_PENDING_MASK                                    0x00000001L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_SURFACE_UPDATE_TAKEN_MASK                                      0x00000002L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_PENDING_MASK                                     0x00000004L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CONFIG_UPDATE_TAKEN_MASK                                       0x00000008L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_PENDING_MASK                                     0x00000010L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP0_CURSOR_UPDATE_TAKEN_MASK                                       0x00000020L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_PENDING_MASK                                    0x00000040L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_SURFACE_UPDATE_TAKEN_MASK                                      0x00000080L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_PENDING_MASK                                     0x00000100L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CONFIG_UPDATE_TAKEN_MASK                                       0x00000200L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_PENDING_MASK                                     0x00000400L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP1_CURSOR_UPDATE_TAKEN_MASK                                       0x00000800L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_PENDING_MASK                                    0x00001000L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_SURFACE_UPDATE_TAKEN_MASK                                      0x00002000L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_PENDING_MASK                                     0x00004000L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CONFIG_UPDATE_TAKEN_MASK                                       0x00008000L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_PENDING_MASK                                     0x00010000L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP2_CURSOR_UPDATE_TAKEN_MASK                                       0x00020000L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_PENDING_MASK                                    0x00040000L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_SURFACE_UPDATE_TAKEN_MASK                                      0x00080000L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_PENDING_MASK                                     0x00100000L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CONFIG_UPDATE_TAKEN_MASK                                       0x00200000L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_PENDING_MASK                                     0x00400000L
>+#define MPC_PENDING_TAKEN_STATUS_REG1__IN_DPP3_CURSOR_UPDATE_TAKEN_MASK                                       0x00800000L
>+//MPC_PENDING_TAKEN_STATUS_REG3
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT                                  0x0
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_TAKEN__SHIFT                                    0x1
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT                                  0x2
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_TAKEN__SHIFT                                    0x3
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT                                  0x4
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_TAKEN__SHIFT                                    0x5
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT                                  0x6
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_TAKEN__SHIFT                                    0x7
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_PENDING__SHIFT                                     0xc
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_TAKEN__SHIFT                                       0xd
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_PENDING__SHIFT                                     0xe
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_TAKEN__SHIFT                                       0xf
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_PENDING__SHIFT                                     0x10
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_TAKEN__SHIFT                                       0x11
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_PENDING__SHIFT                                     0x12
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_TAKEN__SHIFT                                       0x13
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK                                    0x00000001L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP0_CONFIG_UPDATE_TAKEN_MASK                                      0x00000002L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK                                    0x00000004L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP1_CONFIG_UPDATE_TAKEN_MASK                                      0x00000008L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK                                    0x00000010L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP2_CONFIG_UPDATE_TAKEN_MASK                                      0x00000020L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK                                    0x00000040L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__OUT_OPP3_CONFIG_UPDATE_TAKEN_MASK                                      0x00000080L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_PENDING_MASK                                       0x00001000L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC0_CONFIG_UPDATE_TAKEN_MASK                                         0x00002000L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_PENDING_MASK                                       0x00004000L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC1_CONFIG_UPDATE_TAKEN_MASK                                         0x00008000L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_PENDING_MASK                                       0x00010000L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC2_CONFIG_UPDATE_TAKEN_MASK                                         0x00020000L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_PENDING_MASK                                       0x00040000L
>+#define MPC_PENDING_TAKEN_STATUS_REG3__MPCC3_CONFIG_UPDATE_TAKEN_MASK                                         0x00080000L
>+//MPC_UPDATE_ACK_REG5
>+#define MPC_UPDATE_ACK_REG5__IN_DPP0_SURFACE_UPDATE_ACK__SHIFT                                                0x0
>+#define MPC_UPDATE_ACK_REG5__IN_DPP0_CONFIG_UPDATE_ACK__SHIFT                                                 0x1
>+#define MPC_UPDATE_ACK_REG5__IN_DPP0_CURSOR_UPDATE_ACK__SHIFT                                                 0x2
>+#define MPC_UPDATE_ACK_REG5__IN_DPP1_SURFACE_UPDATE_ACK__SHIFT                                                0x3
>+#define MPC_UPDATE_ACK_REG5__IN_DPP1_CONFIG_UPDATE_ACK__SHIFT                                                 0x4
>+#define MPC_UPDATE_ACK_REG5__IN_DPP1_CURSOR_UPDATE_ACK__SHIFT                                                 0x5
>+#define MPC_UPDATE_ACK_REG5__IN_DPP2_SURFACE_UPDATE_ACK__SHIFT                                                0x6
>+#define MPC_UPDATE_ACK_REG5__IN_DPP2_CONFIG_UPDATE_ACK__SHIFT                                                 0x7
>+#define MPC_UPDATE_ACK_REG5__IN_DPP2_CURSOR_UPDATE_ACK__SHIFT                                                 0x8
>+#define MPC_UPDATE_ACK_REG5__IN_DPP3_SURFACE_UPDATE_ACK__SHIFT                                                0x9
>+#define MPC_UPDATE_ACK_REG5__IN_DPP3_CONFIG_UPDATE_ACK__SHIFT                                                 0xa
>+#define MPC_UPDATE_ACK_REG5__IN_DPP3_CURSOR_UPDATE_ACK__SHIFT                                                 0xb
>+#define MPC_UPDATE_ACK_REG5__MPCC0_CONFIG_UPDATE_ACK__SHIFT                                                   0xf
>+#define MPC_UPDATE_ACK_REG5__MPCC1_CONFIG_UPDATE_ACK__SHIFT                                                   0x10
>+#define MPC_UPDATE_ACK_REG5__MPCC2_CONFIG_UPDATE_ACK__SHIFT                                                   0x11
>+#define MPC_UPDATE_ACK_REG5__MPCC3_CONFIG_UPDATE_ACK__SHIFT                                                   0x12
>+#define MPC_UPDATE_ACK_REG5__OUT_OPP0_CONFIG_UPDATE_ACK__SHIFT                                                0x14
>+#define MPC_UPDATE_ACK_REG5__OUT_OPP1_CONFIG_UPDATE_ACK__SHIFT                                                0x15
>+#define MPC_UPDATE_ACK_REG5__OUT_OPP2_CONFIG_UPDATE_ACK__SHIFT                                                0x16
>+#define MPC_UPDATE_ACK_REG5__OUT_OPP3_CONFIG_UPDATE_ACK__SHIFT                                                0x17
>+#define MPC_UPDATE_ACK_REG5__IN_DPP0_SURFACE_UPDATE_ACK_MASK                                                  0x00000001L
>+#define MPC_UPDATE_ACK_REG5__IN_DPP0_CONFIG_UPDATE_ACK_MASK                                                   0x00000002L
>+#define MPC_UPDATE_ACK_REG5__IN_DPP0_CURSOR_UPDATE_ACK_MASK                                                   0x00000004L
>+#define MPC_UPDATE_ACK_REG5__IN_DPP1_SURFACE_UPDATE_ACK_MASK                                                  0x00000008L
>+#define MPC_UPDATE_ACK_REG5__IN_DPP1_CONFIG_UPDATE_ACK_MASK                                                   0x00000010L
>+#define MPC_UPDATE_ACK_REG5__IN_DPP1_CURSOR_UPDATE_ACK_MASK                                                   0x00000020L
>+#define MPC_UPDATE_ACK_REG5__IN_DPP2_SURFACE_UPDATE_ACK_MASK                                                  0x00000040L
>+#define MPC_UPDATE_ACK_REG5__IN_DPP2_CONFIG_UPDATE_ACK_MASK                                                   0x00000080L
>+#define MPC_UPDATE_ACK_REG5__IN_DPP2_CURSOR_UPDATE_ACK_MASK                                                   0x00000100L
>+#define MPC_UPDATE_ACK_REG5__IN_DPP3_SURFACE_UPDATE_ACK_MASK                                                  0x00000200L
>+#define MPC_UPDATE_ACK_REG5__IN_DPP3_CONFIG_UPDATE_ACK_MASK                                                   0x00000400L
>+#define MPC_UPDATE_ACK_REG5__IN_DPP3_CURSOR_UPDATE_ACK_MASK                                                   0x00000800L
>+#define MPC_UPDATE_ACK_REG5__MPCC0_CONFIG_UPDATE_ACK_MASK                                                     0x00008000L
>+#define MPC_UPDATE_ACK_REG5__MPCC1_CONFIG_UPDATE_ACK_MASK                                                     0x00010000L
>+#define MPC_UPDATE_ACK_REG5__MPCC2_CONFIG_UPDATE_ACK_MASK                                                     0x00020000L
>+#define MPC_UPDATE_ACK_REG5__MPCC3_CONFIG_UPDATE_ACK_MASK                                                     0x00040000L
>+#define MPC_UPDATE_ACK_REG5__OUT_OPP0_CONFIG_UPDATE_ACK_MASK                                                  0x00100000L
>+#define MPC_UPDATE_ACK_REG5__OUT_OPP1_CONFIG_UPDATE_ACK_MASK                                                  0x00200000L
>+#define MPC_UPDATE_ACK_REG5__OUT_OPP2_CONFIG_UPDATE_ACK_MASK                                                  0x00400000L
>+#define MPC_UPDATE_ACK_REG5__OUT_OPP3_CONFIG_UPDATE_ACK_MASK                                                  0x00800000L
>+//ADR_CFG_CUR_VUPDATE_LOCK_SET0
>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
>+//ADR_CFG_VUPDATE_LOCK_SET0
>+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
>+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
>+//ADR_VUPDATE_LOCK_SET0
>+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
>+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
>+//CFG_VUPDATE_LOCK_SET0
>+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
>+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
>+//CUR_VUPDATE_LOCK_SET0
>+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
>+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
>+//ADR_CFG_CUR_VUPDATE_LOCK_SET1
>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
>+//ADR_CFG_VUPDATE_LOCK_SET1
>+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
>+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
>+//ADR_VUPDATE_LOCK_SET1
>+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
>+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
>+//CFG_VUPDATE_LOCK_SET1
>+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
>+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
>+//CUR_VUPDATE_LOCK_SET1
>+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
>+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
>+//ADR_CFG_CUR_VUPDATE_LOCK_SET2
>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
>+//ADR_CFG_VUPDATE_LOCK_SET2
>+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
>+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
>+//ADR_VUPDATE_LOCK_SET2
>+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
>+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
>+//CFG_VUPDATE_LOCK_SET2
>+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
>+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
>+//CUR_VUPDATE_LOCK_SET2
>+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
>+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
>+//ADR_CFG_CUR_VUPDATE_LOCK_SET3
>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
>+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
>+//ADR_CFG_VUPDATE_LOCK_SET3
>+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
>+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
>+//ADR_VUPDATE_LOCK_SET3
>+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
>+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
>+//CFG_VUPDATE_LOCK_SET3
>+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
>+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
>+//CUR_VUPDATE_LOCK_SET3
>+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
>+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
>+//MPC_OUT0_MUX
>+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
>+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
>+//MPC_OUT0_DENORM_CONTROL
>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
>+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
>+//MPC_OUT0_DENORM_CLAMP_G_Y
>+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
>+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
>+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
>+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
>+//MPC_OUT0_DENORM_CLAMP_B_CB
>+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
>+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
>+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
>+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
>+//MPC_OUT1_MUX
>+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
>+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
>+//MPC_OUT1_DENORM_CONTROL
>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
>+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
>+//MPC_OUT1_DENORM_CLAMP_G_Y
>+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
>+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
>+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
>+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
>+//MPC_OUT1_DENORM_CLAMP_B_CB
>+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
>+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
>+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
>+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
>+//MPC_OUT2_MUX
>+#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
>+#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
>+//MPC_OUT2_DENORM_CONTROL
>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
>+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
>+//MPC_OUT2_DENORM_CLAMP_G_Y
>+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
>+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
>+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
>+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
>+//MPC_OUT2_DENORM_CLAMP_B_CB
>+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
>+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
>+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
>+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
>+//MPC_OUT3_MUX
>+#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
>+#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
>+//MPC_OUT3_DENORM_CONTROL
>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
>+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
>+//MPC_OUT3_DENORM_CLAMP_G_Y
>+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
>+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
>+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
>+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
>+//MPC_OUT3_DENORM_CLAMP_B_CB
>+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
>+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
>+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
>+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
>+//MPCC_OGAM0_MPCC_OGAM_MODE
>+#define MPCC_OGAM0_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
>+#define MPCC_OGAM0_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
>+//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX
>+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
>+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
>+//MPCC_OGAM0_MPCC_OGAM_LUT_DATA
>+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
>+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL
>+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
>+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
>+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
>+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
>+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
>+#define MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
>+//MPCC_OGAM1_MPCC_OGAM_MODE
>+#define MPCC_OGAM1_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
>+#define MPCC_OGAM1_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
>+//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX
>+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
>+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
>+//MPCC_OGAM1_MPCC_OGAM_LUT_DATA
>+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
>+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL
>+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
>+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
>+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
>+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
>+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
>+#define MPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
>+//MPCC_OGAM2_MPCC_OGAM_MODE
>+#define MPCC_OGAM2_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
>+#define MPCC_OGAM2_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
>+//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX
>+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
>+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
>+//MPCC_OGAM2_MPCC_OGAM_LUT_DATA
>+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
>+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL
>+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
>+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
>+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
>+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
>+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
>+#define MPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
>+//MPCC_OGAM3_MPCC_OGAM_MODE
>+#define MPCC_OGAM3_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
>+#define MPCC_OGAM3_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
>+//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX
>+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
>+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
>+//MPCC_OGAM3_MPCC_OGAM_LUT_DATA
>+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
>+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL
>+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
>+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
>+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
>+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
>+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
>+#define MPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec
>+//MPCC_OGAM4_MPCC_OGAM_MODE
>+#define MPCC_OGAM4_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
>+#define MPCC_OGAM4_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
>+//MPCC_OGAM4_MPCC_OGAM_LUT_INDEX
>+#define MPCC_OGAM4_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
>+#define MPCC_OGAM4_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
>+//MPCC_OGAM4_MPCC_OGAM_LUT_DATA
>+#define MPCC_OGAM4_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
>+#define MPCC_OGAM4_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL
>+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
>+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
>+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
>+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
>+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
>+#define MPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec
>+//MPCC_OGAM5_MPCC_OGAM_MODE
>+#define MPCC_OGAM5_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
>+#define MPCC_OGAM5_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
>+//MPCC_OGAM5_MPCC_OGAM_LUT_INDEX
>+#define MPCC_OGAM5_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
>+#define MPCC_OGAM5_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
>+//MPCC_OGAM5_MPCC_OGAM_LUT_DATA
>+#define MPCC_OGAM5_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
>+#define MPCC_OGAM5_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL
>+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
>+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
>+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
>+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
>+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
>+#define MPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam6_dispdec
>+//MPCC_OGAM6_MPCC_OGAM_MODE
>+#define MPCC_OGAM6_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
>+#define MPCC_OGAM6_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
>+//MPCC_OGAM6_MPCC_OGAM_LUT_INDEX
>+#define MPCC_OGAM6_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
>+#define MPCC_OGAM6_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
>+//MPCC_OGAM6_MPCC_OGAM_LUT_DATA
>+#define MPCC_OGAM6_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
>+#define MPCC_OGAM6_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL
>+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
>+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
>+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
>+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
>+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
>+#define MPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpcc_ogam7_dispdec
>+//MPCC_OGAM7_MPCC_OGAM_MODE
>+#define MPCC_OGAM7_MPCC_OGAM_MODE__MPCC_OGAM_MODE__SHIFT                                                      0x0
>+#define MPCC_OGAM7_MPCC_OGAM_MODE__MPCC_OGAM_MODE_MASK                                                        0x00000003L
>+//MPCC_OGAM7_MPCC_OGAM_LUT_INDEX
>+#define MPCC_OGAM7_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
>+#define MPCC_OGAM7_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
>+//MPCC_OGAM7_MPCC_OGAM_LUT_DATA
>+#define MPCC_OGAM7_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
>+#define MPCC_OGAM7_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0007FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL
>+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK__SHIFT                              0x0
>+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL__SHIFT                                    0x3
>+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS__SHIFT                                  0x4
>+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_WRITE_EN_MASK_MASK                                0x00000007L
>+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_LUT_RAM_SEL_MASK                                      0x00000008L
>+#define MPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL__MPCC_OGAM_CONFIG_STATUS_MASK                                    0x00000030L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B__SHIFT               0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B_MASK                 0x0003FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G__SHIFT               0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G_MASK                 0x0003FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R__SHIFT               0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R_MASK                 0x0003FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0x0000FFFFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0xFFFF0000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0x0000FFFFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0xFFFF0000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0x0000FFFFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0xFFFF0000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
>+//MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
>+#define MPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
>+//MPC_OUT_CSC_COEF_FORMAT
>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT                                                 0x0
>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT                                                 0x1
>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT                                                 0x2
>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT                                                 0x3
>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK                                                   0x00000001L
>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK                                                   0x00000002L
>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK                                                   0x00000004L
>+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK                                                   0x00000008L
>+//MPC_OUT0_CSC_MODE
>+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
>+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
>+//MPC_OUT0_CSC_C11_C12_A
>+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
>+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
>+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT0_CSC_C13_C14_A
>+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
>+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
>+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT0_CSC_C21_C22_A
>+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
>+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
>+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT0_CSC_C23_C24_A
>+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
>+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
>+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT0_CSC_C31_C32_A
>+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
>+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
>+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT0_CSC_C33_C34_A
>+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
>+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
>+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT0_CSC_C11_C12_B
>+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
>+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
>+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT0_CSC_C13_C14_B
>+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
>+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
>+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT0_CSC_C21_C22_B
>+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
>+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
>+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT0_CSC_C23_C24_B
>+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
>+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
>+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT0_CSC_C31_C32_B
>+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
>+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
>+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT0_CSC_C33_C34_B
>+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
>+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
>+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT1_CSC_MODE
>+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
>+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
>+//MPC_OUT1_CSC_C11_C12_A
>+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
>+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
>+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT1_CSC_C13_C14_A
>+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
>+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
>+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT1_CSC_C21_C22_A
>+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
>+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
>+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT1_CSC_C23_C24_A
>+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
>+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
>+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT1_CSC_C31_C32_A
>+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
>+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
>+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT1_CSC_C33_C34_A
>+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
>+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
>+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT1_CSC_C11_C12_B
>+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
>+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
>+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT1_CSC_C13_C14_B
>+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
>+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
>+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT1_CSC_C21_C22_B
>+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
>+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
>+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT1_CSC_C23_C24_B
>+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
>+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
>+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT1_CSC_C31_C32_B
>+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
>+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
>+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT1_CSC_C33_C34_B
>+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
>+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
>+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT2_CSC_MODE
>+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
>+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
>+//MPC_OUT2_CSC_C11_C12_A
>+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
>+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
>+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT2_CSC_C13_C14_A
>+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
>+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
>+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT2_CSC_C21_C22_A
>+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
>+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
>+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT2_CSC_C23_C24_A
>+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
>+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
>+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT2_CSC_C31_C32_A
>+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
>+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
>+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT2_CSC_C33_C34_A
>+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
>+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
>+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT2_CSC_C11_C12_B
>+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
>+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
>+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT2_CSC_C13_C14_B
>+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
>+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
>+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT2_CSC_C21_C22_B
>+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
>+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
>+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT2_CSC_C23_C24_B
>+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
>+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
>+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT2_CSC_C31_C32_B
>+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
>+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
>+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT2_CSC_C33_C34_B
>+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
>+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
>+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT3_CSC_MODE
>+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
>+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
>+//MPC_OUT3_CSC_C11_C12_A
>+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
>+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
>+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT3_CSC_C13_C14_A
>+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
>+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
>+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT3_CSC_C21_C22_A
>+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
>+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
>+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT3_CSC_C23_C24_A
>+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
>+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
>+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT3_CSC_C31_C32_A
>+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
>+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
>+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT3_CSC_C33_C34_A
>+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
>+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
>+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
>+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
>+//MPC_OUT3_CSC_C11_C12_B
>+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
>+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
>+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT3_CSC_C13_C14_B
>+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
>+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
>+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT3_CSC_C21_C22_B
>+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
>+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
>+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT3_CSC_C23_C24_B
>+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
>+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
>+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT3_CSC_C31_C32_B
>+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
>+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
>+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
>+//MPC_OUT3_CSC_C33_C34_B
>+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
>+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
>+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
>+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON15_PERFCOUNTER_CNTL
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON15_PERFCOUNTER_CNTL2
>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON15_PERFCOUNTER_STATE
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON15_PERFMON_CNTL
>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON15_PERFMON_CNTL2
>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON15_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON15_PERFMON_CVALUE_LOW
>+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON15_PERFMON_HI
>+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON15_PERFMON_LOW
>+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_opp_abm0_dispdec
>+//BL1_PWM_AMBIENT_LIGHT_LEVEL
>+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                       0x0
>+#define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                         0x0001FFFFL
>+//BL1_PWM_USER_LEVEL
>+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                         0x0
>+#define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                           0x0001FFFFL
>+//BL1_PWM_TARGET_ABM_LEVEL
>+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                             0x0
>+#define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                               0x0001FFFFL
>+//BL1_PWM_CURRENT_ABM_LEVEL
>+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                           0x0
>+#define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                             0x0001FFFFL
>+//BL1_PWM_FINAL_DUTY_CYCLE
>+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                             0x0
>+#define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                               0x0001FFFFL
>+//BL1_PWM_MINIMUM_DUTY_CYCLE
>+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                         0x0
>+#define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                           0x0001FFFFL
>+//BL1_PWM_ABM_CNTL
>+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                           0x0
>+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                                 0x1
>+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                     0x2
>+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                        0x3
>+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                                    0x10
>+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                             0x00000001L
>+#define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                                   0x00000002L
>+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                       0x00000004L
>+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                          0x00000008L
>+#define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                      0xFFFF0000L
>+//BL1_PWM_BL_UPDATE_SAMPLE_RATE
>+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                          0x0
>+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT               0x1
>+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                       0x8
>+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT    0x10
>+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                              0x1f
>+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                            0x00000001L
>+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                 0x00000002L
>+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                         0x0000FF00L
>+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK      0x00FF0000L
>+#define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                0x80000000L
>+//BL1_PWM_GRP2_REG_LOCK
>+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                                   0x0
>+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                         0x8
>+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                      0x10
>+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                       0x11
>+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x18
>+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1f
>+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                     0x00000001L
>+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                           0x00000100L
>+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                        0x00010000L
>+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                         0x000E0000L
>+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                     0x01000000L
>+#define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                        0x80000000L
>+//DC_ABM1_CNTL
>+#define DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                          0x0
>+#define DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                           0x4
>+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT                                                               0x8
>+#define DC_ABM1_CNTL__ABM1_EN_MASK                                                                            0x00000001L
>+#define DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                             0x00000010L
>+#define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK                                                                 0x00000700L
>+//DC_ABM1_IPCSC_COEFF_SEL
>+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                                0x0
>+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                                0x8
>+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                                0x10
>+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                                    0x1f
>+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                                  0x0000000FL
>+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                                  0x00000F00L
>+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                                  0x000F0000L
>+#define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                      0x80000000L
>+//DC_ABM1_ACE_OFFSET_SLOPE_0
>+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                                   0x0
>+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                                  0x10
>+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                      0x1f
>+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                     0x00007FFFL
>+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                                    0x07FF0000L
>+#define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                        0x80000000L
>+//DC_ABM1_ACE_OFFSET_SLOPE_1
>+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                                   0x0
>+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                                  0x10
>+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                      0x1f
>+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                     0x00007FFFL
>+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                                    0x07FF0000L
>+#define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                        0x80000000L
>+//DC_ABM1_ACE_OFFSET_SLOPE_2
>+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                                   0x0
>+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                                  0x10
>+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                      0x1f
>+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                     0x00007FFFL
>+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                                    0x07FF0000L
>+#define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                        0x80000000L
>+//DC_ABM1_ACE_OFFSET_SLOPE_3
>+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                                   0x0
>+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                                  0x10
>+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                      0x1f
>+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                     0x00007FFFL
>+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                                    0x07FF0000L
>+#define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                        0x80000000L
>+//DC_ABM1_ACE_OFFSET_SLOPE_4
>+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                                   0x0
>+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                                  0x10
>+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                      0x1f
>+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                     0x00007FFFL
>+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                                    0x07FF0000L
>+#define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                        0x80000000L
>+//DC_ABM1_ACE_THRES_12
>+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                         0x0
>+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                         0x10
>+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                            0x1f
>+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                           0x000003FFL
>+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                           0x03FF0000L
>+#define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                              0x80000000L
>+//DC_ABM1_ACE_THRES_34
>+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                         0x0
>+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                         0x10
>+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                           0x1c
>+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                        0x1d
>+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                         0x1e
>+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                            0x1f
>+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                           0x000003FFL
>+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                           0x03FF0000L
>+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                             0x10000000L
>+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                          0x20000000L
>+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                           0x40000000L
>+#define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                              0x80000000L
>+//DC_ABM1_ACE_CNTL_MISC
>+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                            0x0
>+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                      0x8
>+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                              0x00000001L
>+#define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                        0x00000100L
>+//DC_ABM1_HGLS_REG_READ_PROGRESS
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                                   0x0
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                                   0x1
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                                   0x2
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                                  0x8
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                                  0x9
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                                  0xa
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                            0x10
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                            0x18
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                            0x1f
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                     0x00000001L
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                     0x00000002L
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                     0x00000004L
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                                    0x00000100L
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                                    0x00000200L
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                                    0x00000400L
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                              0x00010000L
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                              0x01000000L
>+#define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                              0x80000000L
>+//DC_ABM1_HG_MISC_CTRL
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                                  0x0
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                         0x8
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                                0xc
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                            0x10
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                           0x14
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                                  0x17
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                                  0x18
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                                 0x1c
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                          0x1d
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                        0x1e
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                       0x1f
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                                    0x00000003L
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                           0x00000100L
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                                  0x00001000L
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                              0x00030000L
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                             0x00100000L
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                                    0x00800000L
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                                    0x07000000L
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                                   0x10000000L
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                            0x20000000L
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                          0x40000000L
>+#define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                         0x80000000L
>+//DC_ABM1_LS_SUM_OF_LUMA
>+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                                    0x0
>+#define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                      0xFFFFFFFFL
>+//DC_ABM1_LS_MIN_MAX_LUMA
>+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                      0x0
>+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                      0x10
>+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                        0x000003FFL
>+#define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                        0x03FF0000L
>+//DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
>+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                                    0x0
>+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                                    0x10
>+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                      0x000003FFL
>+#define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                      0x03FF0000L
>+//DC_ABM1_LS_PIXEL_COUNT
>+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                                    0x0
>+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                                0x18
>+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                      0x00FFFFFFL
>+#define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                                  0xFF000000L
>+//DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
>+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                            0x0
>+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                            0x10
>+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                       0x1f
>+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                              0x000003FFL
>+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                              0x03FF0000L
>+#define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                         0x80000000L
>+//DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
>+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                                0x0
>+#define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                                  0x00FFFFFFL
>+//DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
>+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                                0x0
>+#define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                                  0x00FFFFFFL
>+//DC_ABM1_HG_SAMPLE_RATE
>+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                           0x0
>+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                                0x1
>+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                        0x8
>+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                     0x10
>+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                     0x1f
>+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                             0x00000001L
>+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                                  0x00000002L
>+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                          0x0000FF00L
>+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                       0x00FF0000L
>+#define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                       0x80000000L
>+//DC_ABM1_LS_SAMPLE_RATE
>+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                           0x0
>+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                                0x1
>+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                        0x8
>+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                     0x10
>+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                     0x1f
>+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                             0x00000001L
>+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                                  0x00000002L
>+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                          0x0000FF00L
>+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                       0x00FF0000L
>+#define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                       0x80000000L
>+//DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
>+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                                    0x0
>+#define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                      0xFFFFFFFFL
>+//DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
>+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                                    0x0
>+#define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                      0xFFFFFFFFL
>+//DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
>+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                                  0x0
>+#define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                                    0xFFFFFFFFL
>+//DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
>+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                                0x0
>+#define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                                  0xFFFFFFFFL
>+//DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
>+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                                0x0
>+#define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                                  0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_1
>+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                          0x0
>+#define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                            0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_2
>+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                          0x0
>+#define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                            0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_3
>+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                          0x0
>+#define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                            0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_4
>+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                          0x0
>+#define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                            0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_5
>+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                          0x0
>+#define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                            0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_6
>+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                          0x0
>+#define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                            0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_7
>+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                          0x0
>+#define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                            0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_8
>+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                          0x0
>+#define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                            0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_9
>+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                          0x0
>+#define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                            0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_10
>+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_11
>+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_12
>+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_13
>+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_14
>+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_15
>+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_16
>+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_17
>+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_18
>+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_19
>+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_20
>+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_21
>+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_22
>+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_23
>+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_HG_RESULT_24
>+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                        0x0
>+#define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                          0xFFFFFFFFL
>+//DC_ABM1_BL_MASTER_LOCK
>+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                                    0x1f
>+#define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                      0x80000000L
>+
>+
>+// addressBlock: dce_dc_opp_fmt0_dispdec
>+//FMT0_FMT_CLAMP_COMPONENT_R
>+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
>+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
>+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
>+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
>+//FMT0_FMT_CLAMP_COMPONENT_G
>+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
>+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
>+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
>+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
>+//FMT0_FMT_CLAMP_COMPONENT_B
>+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
>+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
>+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
>+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
>+//FMT0_FMT_DYNAMIC_EXP_CNTL
>+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
>+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
>+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
>+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
>+//FMT0_FMT_CONTROL
>+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
>+#define FMT0_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT                                                       0x4
>+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
>+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
>+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
>+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
>+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
>+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
>+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
>+#define FMT0_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT                                                               0x1c
>+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
>+#define FMT0_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK                                                         0x00000010L
>+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
>+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
>+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
>+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
>+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
>+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
>+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
>+#define FMT0_FMT_CONTROL__FMT_PTI_ENABLE_MASK                                                                 0x10000000L
>+//FMT0_FMT_BIT_DEPTH_CONTROL
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
>+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
>+//FMT0_FMT_DITHER_RAND_R_SEED
>+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
>+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
>+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
>+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
>+//FMT0_FMT_DITHER_RAND_G_SEED
>+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
>+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
>+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
>+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
>+//FMT0_FMT_DITHER_RAND_B_SEED
>+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
>+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
>+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
>+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
>+//FMT0_FMT_CLAMP_CNTL
>+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
>+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
>+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
>+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
>+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
>+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
>+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
>+//FMT0_FMT_MAP420_MEMORY_CONTROL
>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
>+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
>+//FMT0_FMT_422_CONTROL
>+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
>+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
>+
>+
>+// addressBlock: dce_dc_opp_dpg0_dispdec
>+//DPG0_DPG_CONTROL
>+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
>+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
>+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
>+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
>+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
>+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
>+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
>+#define DPG0_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
>+#define DPG0_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
>+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
>+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
>+#define DPG0_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
>+#define DPG0_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
>+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
>+//DPG0_DPG_RAMP_CONTROL
>+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
>+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
>+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
>+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
>+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
>+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
>+//DPG0_DPG_DIMENSIONS
>+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
>+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
>+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
>+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
>+//DPG0_DPG_COLOUR_R_CR
>+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
>+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
>+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
>+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
>+//DPG0_DPG_COLOUR_G_Y
>+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
>+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
>+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
>+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
>+//DPG0_DPG_COLOUR_B_CB
>+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
>+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
>+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
>+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
>+//DPG0_DPG_OFFSET_SEGMENT
>+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
>+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
>+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
>+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
>+//DPG0_DPG_STATUS
>+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
>+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
>+
>+
>+// addressBlock: dce_dc_opp_oppbuf0_dispdec
>+//OPPBUF0_OPPBUF_CONTROL
>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
>+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
>+//OPPBUF0_OPPBUF_3D_PARAMETERS_0
>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
>+//OPPBUF0_OPPBUF_3D_PARAMETERS_1
>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
>+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
>+//OPPBUF0_OPPBUF_CONTROL1
>+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
>+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
>+//OPP_PIPE0_OPP_PIPE_CONTROL
>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
>+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
>+//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
>+//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
>+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
>+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
>+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
>+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
>+
>+
>+// addressBlock: dce_dc_opp_fmt1_dispdec
>+//FMT1_FMT_CLAMP_COMPONENT_R
>+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
>+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
>+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
>+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
>+//FMT1_FMT_CLAMP_COMPONENT_G
>+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
>+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
>+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
>+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
>+//FMT1_FMT_CLAMP_COMPONENT_B
>+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
>+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
>+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
>+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
>+//FMT1_FMT_DYNAMIC_EXP_CNTL
>+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
>+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
>+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
>+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
>+//FMT1_FMT_CONTROL
>+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
>+#define FMT1_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT                                                       0x4
>+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
>+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
>+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
>+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
>+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
>+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
>+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
>+#define FMT1_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT                                                               0x1c
>+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
>+#define FMT1_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK                                                         0x00000010L
>+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
>+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
>+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
>+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
>+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
>+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
>+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
>+#define FMT1_FMT_CONTROL__FMT_PTI_ENABLE_MASK                                                                 0x10000000L
>+//FMT1_FMT_BIT_DEPTH_CONTROL
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
>+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
>+//FMT1_FMT_DITHER_RAND_R_SEED
>+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
>+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
>+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
>+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
>+//FMT1_FMT_DITHER_RAND_G_SEED
>+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
>+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
>+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
>+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
>+//FMT1_FMT_DITHER_RAND_B_SEED
>+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
>+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
>+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
>+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
>+//FMT1_FMT_CLAMP_CNTL
>+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
>+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
>+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
>+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
>+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
>+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
>+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
>+//FMT1_FMT_MAP420_MEMORY_CONTROL
>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
>+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
>+//FMT1_FMT_422_CONTROL
>+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
>+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
>+
>+
>+// addressBlock: dce_dc_opp_dpg1_dispdec
>+//DPG1_DPG_CONTROL
>+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
>+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
>+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
>+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
>+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
>+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
>+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
>+#define DPG1_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
>+#define DPG1_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
>+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
>+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
>+#define DPG1_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
>+#define DPG1_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
>+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
>+//DPG1_DPG_RAMP_CONTROL
>+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
>+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
>+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
>+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
>+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
>+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
>+//DPG1_DPG_DIMENSIONS
>+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
>+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
>+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
>+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
>+//DPG1_DPG_COLOUR_R_CR
>+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
>+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
>+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
>+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
>+//DPG1_DPG_COLOUR_G_Y
>+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
>+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
>+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
>+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
>+//DPG1_DPG_COLOUR_B_CB
>+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
>+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
>+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
>+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
>+//DPG1_DPG_OFFSET_SEGMENT
>+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
>+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
>+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
>+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
>+//DPG1_DPG_STATUS
>+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
>+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
>+
>+
>+// addressBlock: dce_dc_opp_oppbuf1_dispdec
>+//OPPBUF1_OPPBUF_CONTROL
>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
>+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
>+//OPPBUF1_OPPBUF_3D_PARAMETERS_0
>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
>+//OPPBUF1_OPPBUF_3D_PARAMETERS_1
>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
>+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
>+//OPPBUF1_OPPBUF_CONTROL1
>+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
>+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
>+//OPP_PIPE1_OPP_PIPE_CONTROL
>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
>+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
>+//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
>+//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
>+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
>+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
>+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
>+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
>+
>+
>+// addressBlock: dce_dc_opp_fmt2_dispdec
>+//FMT2_FMT_CLAMP_COMPONENT_R
>+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
>+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
>+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
>+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
>+//FMT2_FMT_CLAMP_COMPONENT_G
>+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
>+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
>+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
>+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
>+//FMT2_FMT_CLAMP_COMPONENT_B
>+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
>+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
>+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
>+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
>+//FMT2_FMT_DYNAMIC_EXP_CNTL
>+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
>+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
>+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
>+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
>+//FMT2_FMT_CONTROL
>+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
>+#define FMT2_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT                                                       0x4
>+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
>+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
>+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
>+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
>+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
>+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
>+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
>+#define FMT2_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT                                                               0x1c
>+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
>+#define FMT2_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK                                                         0x00000010L
>+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
>+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
>+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
>+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
>+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
>+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
>+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
>+#define FMT2_FMT_CONTROL__FMT_PTI_ENABLE_MASK                                                                 0x10000000L
>+//FMT2_FMT_BIT_DEPTH_CONTROL
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
>+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
>+//FMT2_FMT_DITHER_RAND_R_SEED
>+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
>+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
>+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
>+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
>+//FMT2_FMT_DITHER_RAND_G_SEED
>+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
>+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
>+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
>+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
>+//FMT2_FMT_DITHER_RAND_B_SEED
>+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
>+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
>+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
>+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
>+//FMT2_FMT_CLAMP_CNTL
>+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
>+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
>+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
>+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
>+//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL
>+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
>+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
>+//FMT2_FMT_MAP420_MEMORY_CONTROL
>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
>+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
>+//FMT2_FMT_422_CONTROL
>+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
>+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
>+
>+
>+// addressBlock: dce_dc_opp_dpg2_dispdec
>+//DPG2_DPG_CONTROL
>+#define DPG2_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
>+#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
>+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
>+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
>+#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
>+#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
>+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
>+#define DPG2_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
>+#define DPG2_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
>+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
>+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
>+#define DPG2_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
>+#define DPG2_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
>+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
>+//DPG2_DPG_RAMP_CONTROL
>+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
>+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
>+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
>+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
>+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
>+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
>+//DPG2_DPG_DIMENSIONS
>+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
>+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
>+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
>+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
>+//DPG2_DPG_COLOUR_R_CR
>+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
>+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
>+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
>+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
>+//DPG2_DPG_COLOUR_G_Y
>+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
>+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
>+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
>+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
>+//DPG2_DPG_COLOUR_B_CB
>+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
>+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
>+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
>+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
>+//DPG2_DPG_OFFSET_SEGMENT
>+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
>+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
>+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
>+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
>+//DPG2_DPG_STATUS
>+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
>+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
>+
>+
>+// addressBlock: dce_dc_opp_oppbuf2_dispdec
>+//OPPBUF2_OPPBUF_CONTROL
>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
>+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
>+//OPPBUF2_OPPBUF_3D_PARAMETERS_0
>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
>+//OPPBUF2_OPPBUF_3D_PARAMETERS_1
>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
>+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
>+//OPPBUF2_OPPBUF_CONTROL1
>+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
>+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
>+//OPP_PIPE2_OPP_PIPE_CONTROL
>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
>+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
>+//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
>+//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
>+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
>+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
>+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
>+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
>+
>+
>+// addressBlock: dce_dc_opp_fmt3_dispdec
>+//FMT3_FMT_CLAMP_COMPONENT_R
>+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
>+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
>+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
>+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
>+//FMT3_FMT_CLAMP_COMPONENT_G
>+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
>+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
>+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
>+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
>+//FMT3_FMT_CLAMP_COMPONENT_B
>+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
>+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
>+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
>+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
>+//FMT3_FMT_DYNAMIC_EXP_CNTL
>+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
>+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
>+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
>+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
>+//FMT3_FMT_CONTROL
>+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
>+#define FMT3_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT                                                       0x4
>+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
>+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
>+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
>+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
>+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
>+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
>+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
>+#define FMT3_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT                                                               0x1c
>+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
>+#define FMT3_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK                                                         0x00000010L
>+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
>+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
>+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
>+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
>+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
>+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
>+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
>+#define FMT3_FMT_CONTROL__FMT_PTI_ENABLE_MASK                                                                 0x10000000L
>+//FMT3_FMT_BIT_DEPTH_CONTROL
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
>+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
>+//FMT3_FMT_DITHER_RAND_R_SEED
>+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
>+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
>+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
>+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
>+//FMT3_FMT_DITHER_RAND_G_SEED
>+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
>+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
>+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
>+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
>+//FMT3_FMT_DITHER_RAND_B_SEED
>+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
>+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
>+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
>+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
>+//FMT3_FMT_CLAMP_CNTL
>+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
>+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
>+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
>+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
>+//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL
>+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
>+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
>+//FMT3_FMT_MAP420_MEMORY_CONTROL
>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
>+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
>+//FMT3_FMT_422_CONTROL
>+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
>+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
>+
>+
>+// addressBlock: dce_dc_opp_dpg3_dispdec
>+//DPG3_DPG_CONTROL
>+#define DPG3_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
>+#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
>+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
>+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
>+#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
>+#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
>+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
>+#define DPG3_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
>+#define DPG3_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
>+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
>+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
>+#define DPG3_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
>+#define DPG3_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
>+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
>+//DPG3_DPG_RAMP_CONTROL
>+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
>+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
>+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
>+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
>+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
>+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
>+//DPG3_DPG_DIMENSIONS
>+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
>+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
>+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
>+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
>+//DPG3_DPG_COLOUR_R_CR
>+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
>+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
>+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
>+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
>+//DPG3_DPG_COLOUR_G_Y
>+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
>+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
>+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
>+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
>+//DPG3_DPG_COLOUR_B_CB
>+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
>+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
>+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
>+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
>+//DPG3_DPG_OFFSET_SEGMENT
>+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
>+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
>+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
>+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
>+//DPG3_DPG_STATUS
>+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
>+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
>+
>+
>+// addressBlock: dce_dc_opp_oppbuf3_dispdec
>+//OPPBUF3_OPPBUF_CONTROL
>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
>+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
>+//OPPBUF3_OPPBUF_3D_PARAMETERS_0
>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
>+//OPPBUF3_OPPBUF_3D_PARAMETERS_1
>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
>+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
>+//OPPBUF3_OPPBUF_CONTROL1
>+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
>+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
>+//OPP_PIPE3_OPP_PIPE_CONTROL
>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
>+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
>+//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
>+//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
>+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
>+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
>+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
>+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
>+
>+
>+// addressBlock: dce_dc_opp_fmt4_dispdec
>+//FMT4_FMT_CLAMP_COMPONENT_R
>+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
>+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
>+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
>+#define FMT4_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
>+//FMT4_FMT_CLAMP_COMPONENT_G
>+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
>+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
>+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
>+#define FMT4_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
>+//FMT4_FMT_CLAMP_COMPONENT_B
>+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
>+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
>+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
>+#define FMT4_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
>+//FMT4_FMT_DYNAMIC_EXP_CNTL
>+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
>+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
>+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
>+#define FMT4_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
>+//FMT4_FMT_CONTROL
>+#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
>+#define FMT4_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT                                                       0x4
>+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
>+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
>+#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
>+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
>+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
>+#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
>+#define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
>+#define FMT4_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT                                                               0x1c
>+#define FMT4_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
>+#define FMT4_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK                                                         0x00000010L
>+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
>+#define FMT4_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
>+#define FMT4_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
>+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
>+#define FMT4_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
>+#define FMT4_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
>+#define FMT4_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
>+#define FMT4_FMT_CONTROL__FMT_PTI_ENABLE_MASK                                                                 0x10000000L
>+//FMT4_FMT_BIT_DEPTH_CONTROL
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
>+#define FMT4_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
>+//FMT4_FMT_DITHER_RAND_R_SEED
>+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
>+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
>+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
>+#define FMT4_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
>+//FMT4_FMT_DITHER_RAND_G_SEED
>+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
>+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
>+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
>+#define FMT4_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
>+//FMT4_FMT_DITHER_RAND_B_SEED
>+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
>+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
>+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
>+#define FMT4_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
>+//FMT4_FMT_CLAMP_CNTL
>+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
>+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
>+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
>+#define FMT4_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
>+//FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL
>+#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
>+#define FMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
>+//FMT4_FMT_MAP420_MEMORY_CONTROL
>+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
>+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
>+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
>+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
>+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
>+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
>+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
>+#define FMT4_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
>+//FMT4_FMT_422_CONTROL
>+#define FMT4_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
>+#define FMT4_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
>+
>+
>+// addressBlock: dce_dc_opp_dpg4_dispdec
>+//DPG4_DPG_CONTROL
>+#define DPG4_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
>+#define DPG4_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
>+#define DPG4_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
>+#define DPG4_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
>+#define DPG4_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
>+#define DPG4_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
>+#define DPG4_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
>+#define DPG4_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
>+#define DPG4_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
>+#define DPG4_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
>+#define DPG4_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
>+#define DPG4_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
>+#define DPG4_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
>+#define DPG4_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
>+//DPG4_DPG_RAMP_CONTROL
>+#define DPG4_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
>+#define DPG4_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
>+#define DPG4_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
>+#define DPG4_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
>+#define DPG4_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
>+#define DPG4_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
>+//DPG4_DPG_DIMENSIONS
>+#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
>+#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
>+#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
>+#define DPG4_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
>+//DPG4_DPG_COLOUR_R_CR
>+#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
>+#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
>+#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
>+#define DPG4_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
>+//DPG4_DPG_COLOUR_G_Y
>+#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
>+#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
>+#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
>+#define DPG4_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
>+//DPG4_DPG_COLOUR_B_CB
>+#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
>+#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
>+#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
>+#define DPG4_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
>+//DPG4_DPG_OFFSET_SEGMENT
>+#define DPG4_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
>+#define DPG4_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
>+#define DPG4_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
>+#define DPG4_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
>+//DPG4_DPG_STATUS
>+#define DPG4_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
>+#define DPG4_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
>+
>+
>+// addressBlock: dce_dc_opp_oppbuf4_dispdec
>+//OPPBUF4_OPPBUF_CONTROL
>+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
>+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
>+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
>+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
>+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
>+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
>+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
>+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
>+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
>+#define OPPBUF4_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
>+//OPPBUF4_OPPBUF_3D_PARAMETERS_0
>+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
>+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
>+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
>+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
>+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
>+#define OPPBUF4_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
>+//OPPBUF4_OPPBUF_3D_PARAMETERS_1
>+#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
>+#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
>+#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
>+#define OPPBUF4_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
>+//OPPBUF4_OPPBUF_CONTROL1
>+#define OPPBUF4_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
>+#define OPPBUF4_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe4_dispdec
>+//OPP_PIPE4_OPP_PIPE_CONTROL
>+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
>+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
>+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
>+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
>+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
>+#define OPP_PIPE4_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
>+//OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
>+//OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
>+//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
>+//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
>+//OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
>+#define OPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
>+
>+
>+// addressBlock: dce_dc_opp_fmt5_dispdec
>+//FMT5_FMT_CLAMP_COMPONENT_R
>+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
>+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
>+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
>+#define FMT5_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
>+//FMT5_FMT_CLAMP_COMPONENT_G
>+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
>+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
>+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
>+#define FMT5_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
>+//FMT5_FMT_CLAMP_COMPONENT_B
>+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
>+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
>+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
>+#define FMT5_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
>+//FMT5_FMT_DYNAMIC_EXP_CNTL
>+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
>+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
>+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
>+#define FMT5_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
>+//FMT5_FMT_CONTROL
>+#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
>+#define FMT5_FMT_CONTROL__FMT_PTI_FIELD_POLARITY__SHIFT                                                       0x4
>+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
>+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
>+#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
>+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
>+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
>+#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
>+#define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
>+#define FMT5_FMT_CONTROL__FMT_PTI_ENABLE__SHIFT                                                               0x1c
>+#define FMT5_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
>+#define FMT5_FMT_CONTROL__FMT_PTI_FIELD_POLARITY_MASK                                                         0x00000010L
>+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
>+#define FMT5_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
>+#define FMT5_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
>+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
>+#define FMT5_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
>+#define FMT5_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
>+#define FMT5_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
>+#define FMT5_FMT_CONTROL__FMT_PTI_ENABLE_MASK                                                                 0x10000000L
>+//FMT5_FMT_BIT_DEPTH_CONTROL
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
>+#define FMT5_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
>+//FMT5_FMT_DITHER_RAND_R_SEED
>+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
>+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
>+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
>+#define FMT5_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
>+//FMT5_FMT_DITHER_RAND_G_SEED
>+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
>+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
>+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
>+#define FMT5_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
>+//FMT5_FMT_DITHER_RAND_B_SEED
>+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
>+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
>+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
>+#define FMT5_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
>+//FMT5_FMT_CLAMP_CNTL
>+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
>+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
>+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
>+#define FMT5_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
>+//FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL
>+#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
>+#define FMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
>+//FMT5_FMT_MAP420_MEMORY_CONTROL
>+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
>+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
>+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
>+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
>+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
>+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
>+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
>+#define FMT5_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
>+//FMT5_FMT_422_CONTROL
>+#define FMT5_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
>+#define FMT5_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
>+
>+
>+// addressBlock: dce_dc_opp_dpg5_dispdec
>+//DPG5_DPG_CONTROL
>+#define DPG5_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
>+#define DPG5_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
>+#define DPG5_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
>+#define DPG5_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
>+#define DPG5_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
>+#define DPG5_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
>+#define DPG5_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
>+#define DPG5_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
>+#define DPG5_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
>+#define DPG5_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
>+#define DPG5_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
>+#define DPG5_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
>+#define DPG5_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
>+#define DPG5_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
>+//DPG5_DPG_RAMP_CONTROL
>+#define DPG5_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
>+#define DPG5_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
>+#define DPG5_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
>+#define DPG5_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
>+#define DPG5_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
>+#define DPG5_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
>+//DPG5_DPG_DIMENSIONS
>+#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
>+#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
>+#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
>+#define DPG5_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
>+//DPG5_DPG_COLOUR_R_CR
>+#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
>+#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
>+#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
>+#define DPG5_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
>+//DPG5_DPG_COLOUR_G_Y
>+#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
>+#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
>+#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
>+#define DPG5_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
>+//DPG5_DPG_COLOUR_B_CB
>+#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
>+#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
>+#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
>+#define DPG5_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
>+//DPG5_DPG_OFFSET_SEGMENT
>+#define DPG5_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
>+#define DPG5_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
>+#define DPG5_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
>+#define DPG5_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
>+//DPG5_DPG_STATUS
>+#define DPG5_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
>+#define DPG5_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
>+
>+
>+// addressBlock: dce_dc_opp_oppbuf5_dispdec
>+//OPPBUF5_OPPBUF_CONTROL
>+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
>+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
>+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
>+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
>+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
>+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
>+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
>+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
>+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
>+#define OPPBUF5_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
>+//OPPBUF5_OPPBUF_3D_PARAMETERS_0
>+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
>+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
>+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
>+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
>+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
>+#define OPPBUF5_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
>+//OPPBUF5_OPPBUF_3D_PARAMETERS_1
>+#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
>+#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
>+#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
>+#define OPPBUF5_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
>+//OPPBUF5_OPPBUF_CONTROL1
>+#define OPPBUF5_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
>+#define OPPBUF5_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe5_dispdec
>+//OPP_PIPE5_OPP_PIPE_CONTROL
>+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
>+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
>+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
>+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
>+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
>+#define OPP_PIPE5_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
>+
>+
>+// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
>+//OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
>+//OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
>+//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
>+//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
>+//OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
>+#define OPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
>+
>+
>+// addressBlock: dce_dc_opp_opp_top_dispdec
>+//OPP_TOP_CLK_CONTROL
>+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
>+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT                                                0x4
>+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT                                                          0x8
>+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT                                                         0xc
>+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT                                                         0xd
>+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
>+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK                                                  0x00000010L
>+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L
>+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK                                                           0x00001000L
>+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK                                                           0x00002000L
>+
>+
>+// addressBlock: dce_dc_opp_dscrm0_dispdec
>+//DSCRM0_DSCRM_DSC_FORWARD_CONFIG
>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
>+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
>+
>+
>+// addressBlock: dce_dc_opp_dscrm1_dispdec
>+//DSCRM1_DSCRM_DSC_FORWARD_CONFIG
>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
>+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
>+
>+
>+// addressBlock: dce_dc_opp_dscrm2_dispdec
>+//DSCRM2_DSCRM_DSC_FORWARD_CONFIG
>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
>+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
>+
>+
>+// addressBlock: dce_dc_opp_dscrm3_dispdec
>+//DSCRM3_DSCRM_DSC_FORWARD_CONFIG
>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
>+#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
>+
>+
>+// addressBlock: dce_dc_opp_dscrm4_dispdec
>+//DSCRM4_DSCRM_DSC_FORWARD_CONFIG
>+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
>+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
>+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
>+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
>+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
>+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
>+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
>+#define DSCRM4_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
>+
>+
>+// addressBlock: dce_dc_opp_dscrm5_dispdec
>+//DSCRM5_DSCRM_DSC_FORWARD_CONFIG
>+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
>+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
>+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
>+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
>+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
>+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
>+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
>+#define DSCRM5_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
>+
>+
>+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON16_PERFCOUNTER_CNTL
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON16_PERFCOUNTER_CNTL2
>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON16_PERFCOUNTER_STATE
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON16_PERFMON_CNTL
>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON16_PERFMON_CNTL2
>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON16_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON16_PERFMON_CVALUE_LOW
>+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON16_PERFMON_HI
>+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON16_PERFMON_LOW
>+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_odm0_dispdec
>+//ODM0_OPTC_INPUT_GLOBAL_CONTROL
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
>+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
>+//ODM0_OPTC_DATA_SOURCE_SELECT
>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000001L
>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
>+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
>+//ODM0_OPTC_DATA_FORMAT_CONTROL
>+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
>+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
>+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
>+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
>+//ODM0_OPTC_BYTES_PER_PIXEL
>+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
>+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
>+//ODM0_OPTC_WIDTH_CONTROL
>+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
>+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
>+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
>+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
>+//ODM0_OPTC_INPUT_CLOCK_CONTROL
>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
>+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
>+//ODM0_OPTC_MEMORY_CONFIG
>+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
>+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
>+//ODM0_OPTC_INPUT_SPARE_REGISTER
>+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
>+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_odm1_dispdec
>+//ODM1_OPTC_INPUT_GLOBAL_CONTROL
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
>+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
>+//ODM1_OPTC_DATA_SOURCE_SELECT
>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000001L
>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
>+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
>+//ODM1_OPTC_DATA_FORMAT_CONTROL
>+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
>+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
>+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
>+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
>+//ODM1_OPTC_BYTES_PER_PIXEL
>+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
>+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
>+//ODM1_OPTC_WIDTH_CONTROL
>+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
>+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
>+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
>+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
>+//ODM1_OPTC_INPUT_CLOCK_CONTROL
>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
>+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
>+//ODM1_OPTC_MEMORY_CONFIG
>+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
>+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
>+//ODM1_OPTC_INPUT_SPARE_REGISTER
>+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
>+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_odm2_dispdec
>+//ODM2_OPTC_INPUT_GLOBAL_CONTROL
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
>+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
>+//ODM2_OPTC_DATA_SOURCE_SELECT
>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000001L
>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
>+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
>+//ODM2_OPTC_DATA_FORMAT_CONTROL
>+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
>+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
>+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
>+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
>+//ODM2_OPTC_BYTES_PER_PIXEL
>+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
>+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
>+//ODM2_OPTC_WIDTH_CONTROL
>+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
>+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
>+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
>+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
>+//ODM2_OPTC_INPUT_CLOCK_CONTROL
>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
>+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
>+//ODM2_OPTC_MEMORY_CONFIG
>+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
>+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
>+//ODM2_OPTC_INPUT_SPARE_REGISTER
>+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
>+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_odm3_dispdec
>+//ODM3_OPTC_INPUT_GLOBAL_CONTROL
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
>+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
>+//ODM3_OPTC_DATA_SOURCE_SELECT
>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000001L
>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
>+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
>+//ODM3_OPTC_DATA_FORMAT_CONTROL
>+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
>+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
>+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
>+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
>+//ODM3_OPTC_BYTES_PER_PIXEL
>+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
>+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
>+//ODM3_OPTC_WIDTH_CONTROL
>+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
>+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
>+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
>+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
>+//ODM3_OPTC_INPUT_CLOCK_CONTROL
>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
>+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
>+//ODM3_OPTC_MEMORY_CONFIG
>+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
>+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
>+//ODM3_OPTC_INPUT_SPARE_REGISTER
>+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
>+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_odm4_dispdec
>+//ODM4_OPTC_INPUT_GLOBAL_CONTROL
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
>+#define ODM4_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
>+//ODM4_OPTC_DATA_SOURCE_SELECT
>+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
>+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
>+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
>+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
>+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000001L
>+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
>+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
>+#define ODM4_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
>+//ODM4_OPTC_DATA_FORMAT_CONTROL
>+#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
>+#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
>+#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
>+#define ODM4_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
>+//ODM4_OPTC_BYTES_PER_PIXEL
>+#define ODM4_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
>+#define ODM4_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
>+//ODM4_OPTC_WIDTH_CONTROL
>+#define ODM4_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
>+#define ODM4_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
>+#define ODM4_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
>+#define ODM4_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
>+//ODM4_OPTC_INPUT_CLOCK_CONTROL
>+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
>+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
>+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
>+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
>+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
>+#define ODM4_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
>+//ODM4_OPTC_MEMORY_CONFIG
>+#define ODM4_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
>+#define ODM4_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
>+//ODM4_OPTC_INPUT_SPARE_REGISTER
>+#define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
>+#define ODM4_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_odm5_dispdec
>+//ODM5_OPTC_INPUT_GLOBAL_CONTROL
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
>+#define ODM5_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
>+//ODM5_OPTC_DATA_SOURCE_SELECT
>+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
>+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x2
>+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x8
>+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0xc
>+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000001L
>+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x0000000CL
>+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x00000F00L
>+#define ODM5_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x0000F000L
>+//ODM5_OPTC_DATA_FORMAT_CONTROL
>+#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
>+#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
>+#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
>+#define ODM5_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
>+//ODM5_OPTC_BYTES_PER_PIXEL
>+#define ODM5_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
>+#define ODM5_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
>+//ODM5_OPTC_WIDTH_CONTROL
>+#define ODM5_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
>+#define ODM5_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
>+#define ODM5_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
>+#define ODM5_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
>+//ODM5_OPTC_INPUT_CLOCK_CONTROL
>+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
>+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
>+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
>+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
>+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
>+#define ODM5_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
>+//ODM5_OPTC_MEMORY_CONFIG
>+#define ODM5_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
>+#define ODM5_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
>+//ODM5_OPTC_INPUT_SPARE_REGISTER
>+#define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
>+#define ODM5_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_otg0_dispdec
>+//OTG0_OTG_H_TOTAL
>+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
>+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
>+//OTG0_OTG_H_BLANK_START_END
>+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
>+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
>+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
>+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
>+//OTG0_OTG_H_SYNC_A
>+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
>+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
>+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
>+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
>+//OTG0_OTG_H_SYNC_A_CNTL
>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
>+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
>+//OTG0_OTG_H_TIMING_CNTL
>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT                                                   0x0
>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT                                       0x8
>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK                                                     0x00000001L
>+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK                                         0x00000100L
>+//OTG0_OTG_V_TOTAL
>+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
>+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
>+//OTG0_OTG_V_TOTAL_MIN
>+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
>+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
>+//OTG0_OTG_V_TOTAL_MAX
>+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
>+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
>+//OTG0_OTG_V_TOTAL_MID
>+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
>+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
>+//OTG0_OTG_V_TOTAL_CONTROL
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
>+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
>+//OTG0_OTG_V_TOTAL_INT_STATUS
>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
>+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
>+//OTG0_OTG_VSYNC_NOM_INT_STATUS
>+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
>+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
>+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
>+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
>+//OTG0_OTG_V_BLANK_START_END
>+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
>+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
>+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
>+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
>+//OTG0_OTG_V_SYNC_A
>+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
>+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
>+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
>+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
>+//OTG0_OTG_V_SYNC_A_CNTL
>+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
>+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
>+//OTG0_OTG_TRIGA_CNTL
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
>+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
>+//OTG0_OTG_TRIGA_MANUAL_TRIG
>+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
>+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
>+//OTG0_OTG_TRIGB_CNTL
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
>+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
>+//OTG0_OTG_TRIGB_MANUAL_TRIG
>+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
>+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
>+//OTG0_OTG_FORCE_COUNT_NOW_CNTL
>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
>+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
>+//OTG0_OTG_FLOW_CONTROL
>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
>+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
>+//OTG0_OTG_STEREO_FORCE_NEXT_EYE
>+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
>+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT                                       0x8
>+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT                                        0x10
>+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
>+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK                                         0x0000FF00L
>+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK                                          0x1FFF0000L
>+//OTG0_OTG_CONTROL
>+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
>+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
>+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
>+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
>+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
>+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
>+#define OTG0_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT                                                0x18
>+#define OTG0_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT                                                     0x1e
>+#define OTG0_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT                                                0x1f
>+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
>+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
>+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
>+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
>+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
>+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
>+#define OTG0_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK                                                  0x01000000L
>+#define OTG0_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK                                                       0x40000000L
>+#define OTG0_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK                                                  0x80000000L
>+//OTG0_OTG_BLANK_CONTROL
>+#define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT                                                0x0
>+#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT                                                      0x8
>+#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT                                                      0x10
>+#define OTG0_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK                                                  0x00000001L
>+#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK                                                        0x00000100L
>+#define OTG0_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK                                                        0x00010000L
>+//OTG0_OTG_PIPE_ABORT_CONTROL
>+#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT                                                    0x0
>+#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT                                               0x8
>+#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK                                                      0x00000001L
>+#define OTG0_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK                                                 0x00000100L
>+//OTG0_OTG_INTERLACE_CONTROL
>+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
>+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
>+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
>+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
>+//OTG0_OTG_INTERLACE_STATUS
>+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
>+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
>+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
>+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
>+//OTG0_OTG_PIXEL_DATA_READBACK0
>+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
>+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
>+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
>+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
>+//OTG0_OTG_PIXEL_DATA_READBACK1
>+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
>+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
>+//OTG0_OTG_STATUS
>+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
>+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
>+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
>+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
>+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
>+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
>+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
>+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
>+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
>+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
>+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
>+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
>+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
>+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
>+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
>+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
>+//OTG0_OTG_STATUS_POSITION
>+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
>+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
>+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
>+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
>+//OTG0_OTG_NOM_VERT_POSITION
>+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
>+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
>+//OTG0_OTG_STATUS_FRAME_COUNT
>+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
>+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
>+//OTG0_OTG_STATUS_VF_COUNT
>+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
>+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
>+//OTG0_OTG_STATUS_HV_COUNT
>+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
>+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
>+//OTG0_OTG_COUNT_CONTROL
>+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
>+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
>+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
>+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
>+//OTG0_OTG_COUNT_RESET
>+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
>+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
>+//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
>+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
>+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
>+//OTG0_OTG_VERT_SYNC_CONTROL
>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
>+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
>+//OTG0_OTG_STEREO_STATUS
>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
>+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
>+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
>+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
>+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
>+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
>+//OTG0_OTG_STEREO_CONTROL
>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
>+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
>+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
>+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
>+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
>+//OTG0_OTG_SNAPSHOT_STATUS
>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
>+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
>+//OTG0_OTG_SNAPSHOT_CONTROL
>+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
>+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
>+//OTG0_OTG_SNAPSHOT_POSITION
>+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
>+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
>+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
>+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
>+//OTG0_OTG_SNAPSHOT_FRAME
>+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
>+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
>+//OTG0_OTG_INTERRUPT_CONTROL
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
>+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
>+//OTG0_OTG_UPDATE_LOCK
>+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
>+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
>+//OTG0_OTG_DOUBLE_BUFFER_CONTROL
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT                         0x2
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT                               0x3
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT                           0x4
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT                                0x10
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT                              0x18
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK                           0x00000004L
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK                                 0x00000008L
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK                             0x00000010L
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK                                  0x00010000L
>+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK                                0x03000000L
>+//OTG0_OTG_MASTER_EN
>+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
>+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
>+//OTG0_OTG_BLANK_DATA_COLOR
>+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
>+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
>+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
>+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
>+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
>+#define OTG0_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
>+//OTG0_OTG_BLANK_DATA_COLOR_EXT
>+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
>+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
>+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
>+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
>+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
>+#define OTG0_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
>+//OTG0_OTG_BLACK_COLOR
>+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT                                                     0x0
>+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT                                                      0xa
>+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT                                                     0x14
>+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK                                                       0x000003FFL
>+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK                                                        0x000FFC00L
>+#define OTG0_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK                                                       0x3FF00000L
>+//OTG0_OTG_BLACK_COLOR_EXT
>+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT                                             0x0
>+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT                                              0x8
>+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT                                             0x10
>+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK                                               0x0000003FL
>+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK                                                0x00003F00L
>+#define OTG0_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK                                               0x003F0000L
>+//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
>+//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
>+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
>+//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION
>+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
>+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
>+//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL
>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
>+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
>+//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION
>+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
>+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
>+//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL
>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
>+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
>+//OTG0_OTG_CRC_CNTL
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
>+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
>+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
>+//OTG0_OTG_CRC_CNTL2
>+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
>+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
>+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
>+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
>+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
>+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
>+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
>+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
>+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL
>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
>+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
>+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL
>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
>+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
>+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL
>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
>+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
>+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL
>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
>+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
>+//OTG0_OTG_CRC0_DATA_RG
>+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
>+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
>+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG0_OTG_CRC0_DATA_B
>+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
>+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
>+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
>+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL
>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
>+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
>+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL
>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
>+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
>+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL
>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
>+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
>+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL
>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
>+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
>+//OTG0_OTG_CRC1_DATA_RG
>+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
>+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
>+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG0_OTG_CRC1_DATA_B
>+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
>+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
>+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
>+//OTG0_OTG_CRC2_DATA_RG
>+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
>+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
>+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG0_OTG_CRC2_DATA_B
>+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
>+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
>+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
>+//OTG0_OTG_CRC3_DATA_RG
>+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
>+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
>+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG0_OTG_CRC3_DATA_B
>+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
>+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
>+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
>+//OTG0_OTG_CRC_SIG_RED_GREEN_MASK
>+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
>+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
>+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
>+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
>+//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK
>+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
>+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
>+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
>+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
>+//OTG0_OTG_STATIC_SCREEN_CONTROL
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
>+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
>+//OTG0_OTG_3D_STRUCTURE_CONTROL
>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
>+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
>+//OTG0_OTG_GSL_VSYNC_GAP
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
>+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
>+//OTG0_OTG_MASTER_UPDATE_MODE
>+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
>+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
>+//OTG0_OTG_CLOCK_CONTROL
>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
>+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
>+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
>+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
>+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
>+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
>+//OTG0_OTG_VSTARTUP_PARAM
>+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
>+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
>+//OTG0_OTG_VUPDATE_PARAM
>+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
>+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
>+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
>+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
>+//OTG0_OTG_VREADY_PARAM
>+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
>+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
>+//OTG0_OTG_GLOBAL_SYNC_STATUS
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
>+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
>+//OTG0_OTG_MASTER_UPDATE_LOCK
>+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
>+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
>+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
>+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
>+//OTG0_OTG_GSL_CONTROL
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
>+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
>+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
>+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
>+//OTG0_OTG_GSL_WINDOW_X
>+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
>+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
>+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
>+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
>+//OTG0_OTG_GSL_WINDOW_Y
>+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
>+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
>+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
>+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
>+//OTG0_OTG_VUPDATE_KEEPOUT
>+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
>+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
>+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
>+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
>+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
>+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
>+//OTG0_OTG_GLOBAL_CONTROL0
>+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT                                0x0
>+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT                             0x8
>+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
>+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK                                  0x000000FFL
>+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK                               0x00000100L
>+#define OTG0_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
>+//OTG0_OTG_GLOBAL_CONTROL1
>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT                                              0x0
>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT                                              0x10
>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK                                                0x00007FFFL
>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK                                                0x7FFF0000L
>+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
>+//OTG0_OTG_GLOBAL_CONTROL2
>+#define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT                                                  0x0
>+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
>+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
>+#define OTG0_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT                                        0x1d
>+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
>+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
>+#define OTG0_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK                                                    0x000003FFL
>+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
>+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
>+#define OTG0_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK                                          0x20000000L
>+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
>+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
>+//OTG0_OTG_GLOBAL_CONTROL3
>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT                          0x8
>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
>+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK                            0x00000100L
>+//OTG0_OTG_TRIG_MANUAL_CONTROL
>+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
>+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
>+//OTG0_OTG_MANUAL_FLOW_CONTROL
>+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
>+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
>+//OTG0_OTG_RANGE_TIMING_INT_STATUS
>+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                             0x0
>+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT                         0x4
>+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                       0x8
>+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                     0xc
>+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                    0x10
>+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK                               0x00000001L
>+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK                           0x00000010L
>+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK                         0x00000100L
>+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                       0x00001000L
>+#define OTG0_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                      0x00010000L
>+//OTG0_OTG_DRR_CONTROL
>+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
>+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
>+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000007L
>+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
>+//OTG0_OTG_REQUEST_CONTROL
>+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
>+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
>+//OTG0_OTG_DSC_START_POSITION
>+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
>+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
>+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
>+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
>+//OTG0_OTG_PIPE_UPDATE_STATUS
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT                                                    0x1
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT                                              0x2
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT                                           0x5
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT                                     0x6
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT                                           0x9
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT                                     0xa
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK                                                      0x00000002L
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK                                                0x00000004L
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK                                             0x00000020L
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK                                       0x00000040L
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK                                             0x00000200L
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK                                       0x00000400L
>+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
>+//OTG0_OTG_SPARE_REGISTER
>+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
>+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_otg1_dispdec
>+//OTG1_OTG_H_TOTAL
>+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
>+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
>+//OTG1_OTG_H_BLANK_START_END
>+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
>+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
>+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
>+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
>+//OTG1_OTG_H_SYNC_A
>+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
>+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
>+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
>+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
>+//OTG1_OTG_H_SYNC_A_CNTL
>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
>+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
>+//OTG1_OTG_H_TIMING_CNTL
>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT                                                   0x0
>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT                                       0x8
>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK                                                     0x00000001L
>+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK                                         0x00000100L
>+//OTG1_OTG_V_TOTAL
>+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
>+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
>+//OTG1_OTG_V_TOTAL_MIN
>+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
>+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
>+//OTG1_OTG_V_TOTAL_MAX
>+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
>+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
>+//OTG1_OTG_V_TOTAL_MID
>+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
>+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
>+//OTG1_OTG_V_TOTAL_CONTROL
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
>+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
>+//OTG1_OTG_V_TOTAL_INT_STATUS
>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
>+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
>+//OTG1_OTG_VSYNC_NOM_INT_STATUS
>+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
>+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
>+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
>+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
>+//OTG1_OTG_V_BLANK_START_END
>+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
>+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
>+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
>+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
>+//OTG1_OTG_V_SYNC_A
>+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
>+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
>+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
>+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
>+//OTG1_OTG_V_SYNC_A_CNTL
>+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
>+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
>+//OTG1_OTG_TRIGA_CNTL
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
>+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
>+//OTG1_OTG_TRIGA_MANUAL_TRIG
>+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
>+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
>+//OTG1_OTG_TRIGB_CNTL
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
>+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
>+//OTG1_OTG_TRIGB_MANUAL_TRIG
>+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
>+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
>+//OTG1_OTG_FORCE_COUNT_NOW_CNTL
>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
>+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
>+//OTG1_OTG_FLOW_CONTROL
>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
>+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
>+//OTG1_OTG_STEREO_FORCE_NEXT_EYE
>+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
>+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT                                       0x8
>+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT                                        0x10
>+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
>+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK                                         0x0000FF00L
>+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK                                          0x1FFF0000L
>+//OTG1_OTG_CONTROL
>+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
>+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
>+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
>+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
>+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
>+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
>+#define OTG1_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT                                                0x18
>+#define OTG1_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT                                                     0x1e
>+#define OTG1_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT                                                0x1f
>+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
>+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
>+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
>+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
>+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
>+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
>+#define OTG1_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK                                                  0x01000000L
>+#define OTG1_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK                                                       0x40000000L
>+#define OTG1_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK                                                  0x80000000L
>+//OTG1_OTG_BLANK_CONTROL
>+#define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT                                                0x0
>+#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT                                                      0x8
>+#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT                                                      0x10
>+#define OTG1_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK                                                  0x00000001L
>+#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK                                                        0x00000100L
>+#define OTG1_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK                                                        0x00010000L
>+//OTG1_OTG_PIPE_ABORT_CONTROL
>+#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT                                                    0x0
>+#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT                                               0x8
>+#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK                                                      0x00000001L
>+#define OTG1_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK                                                 0x00000100L
>+//OTG1_OTG_INTERLACE_CONTROL
>+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
>+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
>+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
>+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
>+//OTG1_OTG_INTERLACE_STATUS
>+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
>+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
>+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
>+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
>+//OTG1_OTG_PIXEL_DATA_READBACK0
>+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
>+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
>+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
>+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
>+//OTG1_OTG_PIXEL_DATA_READBACK1
>+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
>+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
>+//OTG1_OTG_STATUS
>+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
>+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
>+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
>+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
>+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
>+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
>+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
>+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
>+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
>+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
>+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
>+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
>+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
>+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
>+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
>+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
>+//OTG1_OTG_STATUS_POSITION
>+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
>+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
>+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
>+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
>+//OTG1_OTG_NOM_VERT_POSITION
>+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
>+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
>+//OTG1_OTG_STATUS_FRAME_COUNT
>+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
>+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
>+//OTG1_OTG_STATUS_VF_COUNT
>+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
>+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
>+//OTG1_OTG_STATUS_HV_COUNT
>+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
>+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
>+//OTG1_OTG_COUNT_CONTROL
>+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
>+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
>+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
>+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
>+//OTG1_OTG_COUNT_RESET
>+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
>+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
>+//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
>+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
>+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
>+//OTG1_OTG_VERT_SYNC_CONTROL
>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
>+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
>+//OTG1_OTG_STEREO_STATUS
>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
>+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
>+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
>+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
>+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
>+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
>+//OTG1_OTG_STEREO_CONTROL
>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
>+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
>+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
>+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
>+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
>+//OTG1_OTG_SNAPSHOT_STATUS
>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
>+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
>+//OTG1_OTG_SNAPSHOT_CONTROL
>+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
>+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
>+//OTG1_OTG_SNAPSHOT_POSITION
>+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
>+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
>+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
>+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
>+//OTG1_OTG_SNAPSHOT_FRAME
>+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
>+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
>+//OTG1_OTG_INTERRUPT_CONTROL
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
>+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
>+//OTG1_OTG_UPDATE_LOCK
>+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
>+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
>+//OTG1_OTG_DOUBLE_BUFFER_CONTROL
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT                         0x2
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT                               0x3
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT                           0x4
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT                                0x10
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT                              0x18
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK                           0x00000004L
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK                                 0x00000008L
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK                             0x00000010L
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK                                  0x00010000L
>+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK                                0x03000000L
>+//OTG1_OTG_MASTER_EN
>+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
>+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
>+//OTG1_OTG_BLANK_DATA_COLOR
>+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
>+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
>+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
>+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
>+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
>+#define OTG1_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
>+//OTG1_OTG_BLANK_DATA_COLOR_EXT
>+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
>+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
>+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
>+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
>+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
>+#define OTG1_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
>+//OTG1_OTG_BLACK_COLOR
>+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT                                                     0x0
>+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT                                                      0xa
>+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT                                                     0x14
>+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK                                                       0x000003FFL
>+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK                                                        0x000FFC00L
>+#define OTG1_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK                                                       0x3FF00000L
>+//OTG1_OTG_BLACK_COLOR_EXT
>+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT                                             0x0
>+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT                                              0x8
>+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT                                             0x10
>+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK                                               0x0000003FL
>+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK                                                0x00003F00L
>+#define OTG1_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK                                               0x003F0000L
>+//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
>+//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
>+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
>+//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION
>+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
>+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
>+//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL
>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
>+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
>+//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION
>+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
>+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
>+//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL
>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
>+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
>+//OTG1_OTG_CRC_CNTL
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
>+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
>+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
>+//OTG1_OTG_CRC_CNTL2
>+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
>+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
>+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
>+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
>+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
>+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
>+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
>+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
>+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL
>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
>+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
>+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL
>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
>+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
>+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL
>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
>+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
>+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL
>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
>+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
>+//OTG1_OTG_CRC0_DATA_RG
>+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
>+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
>+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG1_OTG_CRC0_DATA_B
>+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
>+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
>+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
>+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL
>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
>+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
>+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL
>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
>+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
>+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL
>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
>+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
>+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL
>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
>+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
>+//OTG1_OTG_CRC1_DATA_RG
>+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
>+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
>+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG1_OTG_CRC1_DATA_B
>+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
>+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
>+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
>+//OTG1_OTG_CRC2_DATA_RG
>+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
>+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
>+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG1_OTG_CRC2_DATA_B
>+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
>+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
>+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
>+//OTG1_OTG_CRC3_DATA_RG
>+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
>+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
>+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG1_OTG_CRC3_DATA_B
>+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
>+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
>+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
>+//OTG1_OTG_CRC_SIG_RED_GREEN_MASK
>+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
>+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
>+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
>+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
>+//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK
>+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
>+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
>+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
>+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
>+//OTG1_OTG_STATIC_SCREEN_CONTROL
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
>+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
>+//OTG1_OTG_3D_STRUCTURE_CONTROL
>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
>+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
>+//OTG1_OTG_GSL_VSYNC_GAP
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
>+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
>+//OTG1_OTG_MASTER_UPDATE_MODE
>+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
>+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
>+//OTG1_OTG_CLOCK_CONTROL
>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
>+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
>+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
>+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
>+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
>+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
>+//OTG1_OTG_VSTARTUP_PARAM
>+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
>+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
>+//OTG1_OTG_VUPDATE_PARAM
>+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
>+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
>+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
>+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
>+//OTG1_OTG_VREADY_PARAM
>+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
>+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
>+//OTG1_OTG_GLOBAL_SYNC_STATUS
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
>+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
>+//OTG1_OTG_MASTER_UPDATE_LOCK
>+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
>+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
>+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
>+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
>+//OTG1_OTG_GSL_CONTROL
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
>+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
>+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
>+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
>+//OTG1_OTG_GSL_WINDOW_X
>+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
>+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
>+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
>+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
>+//OTG1_OTG_GSL_WINDOW_Y
>+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
>+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
>+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
>+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
>+//OTG1_OTG_VUPDATE_KEEPOUT
>+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
>+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
>+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
>+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
>+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
>+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
>+//OTG1_OTG_GLOBAL_CONTROL0
>+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT                                0x0
>+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT                             0x8
>+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
>+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK                                  0x000000FFL
>+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK                               0x00000100L
>+#define OTG1_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
>+//OTG1_OTG_GLOBAL_CONTROL1
>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT                                              0x0
>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT                                              0x10
>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK                                                0x00007FFFL
>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK                                                0x7FFF0000L
>+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
>+//OTG1_OTG_GLOBAL_CONTROL2
>+#define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT                                                  0x0
>+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
>+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
>+#define OTG1_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT                                        0x1d
>+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
>+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
>+#define OTG1_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK                                                    0x000003FFL
>+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
>+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
>+#define OTG1_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK                                          0x20000000L
>+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
>+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
>+//OTG1_OTG_GLOBAL_CONTROL3
>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT                          0x8
>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
>+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK                            0x00000100L
>+//OTG1_OTG_TRIG_MANUAL_CONTROL
>+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
>+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
>+//OTG1_OTG_MANUAL_FLOW_CONTROL
>+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
>+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
>+//OTG1_OTG_RANGE_TIMING_INT_STATUS
>+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                             0x0
>+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT                         0x4
>+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                       0x8
>+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                     0xc
>+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                    0x10
>+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK                               0x00000001L
>+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK                           0x00000010L
>+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK                         0x00000100L
>+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                       0x00001000L
>+#define OTG1_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                      0x00010000L
>+//OTG1_OTG_DRR_CONTROL
>+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
>+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
>+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000007L
>+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
>+//OTG1_OTG_REQUEST_CONTROL
>+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
>+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
>+//OTG1_OTG_DSC_START_POSITION
>+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
>+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
>+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
>+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
>+//OTG1_OTG_PIPE_UPDATE_STATUS
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT                                                    0x1
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT                                              0x2
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT                                           0x5
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT                                     0x6
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT                                           0x9
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT                                     0xa
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK                                                      0x00000002L
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK                                                0x00000004L
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK                                             0x00000020L
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK                                       0x00000040L
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK                                             0x00000200L
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK                                       0x00000400L
>+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
>+//OTG1_OTG_SPARE_REGISTER
>+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
>+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_otg2_dispdec
>+//OTG2_OTG_H_TOTAL
>+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
>+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
>+//OTG2_OTG_H_BLANK_START_END
>+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
>+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
>+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
>+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
>+//OTG2_OTG_H_SYNC_A
>+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
>+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
>+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
>+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
>+//OTG2_OTG_H_SYNC_A_CNTL
>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
>+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
>+//OTG2_OTG_H_TIMING_CNTL
>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT                                                   0x0
>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT                                       0x8
>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK                                                     0x00000001L
>+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK                                         0x00000100L
>+//OTG2_OTG_V_TOTAL
>+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
>+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
>+//OTG2_OTG_V_TOTAL_MIN
>+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
>+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
>+//OTG2_OTG_V_TOTAL_MAX
>+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
>+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
>+//OTG2_OTG_V_TOTAL_MID
>+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
>+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
>+//OTG2_OTG_V_TOTAL_CONTROL
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
>+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
>+//OTG2_OTG_V_TOTAL_INT_STATUS
>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
>+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
>+//OTG2_OTG_VSYNC_NOM_INT_STATUS
>+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
>+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
>+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
>+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
>+//OTG2_OTG_V_BLANK_START_END
>+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
>+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
>+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
>+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
>+//OTG2_OTG_V_SYNC_A
>+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
>+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
>+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
>+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
>+//OTG2_OTG_V_SYNC_A_CNTL
>+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
>+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
>+//OTG2_OTG_TRIGA_CNTL
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
>+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
>+//OTG2_OTG_TRIGA_MANUAL_TRIG
>+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
>+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
>+//OTG2_OTG_TRIGB_CNTL
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
>+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
>+//OTG2_OTG_TRIGB_MANUAL_TRIG
>+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
>+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
>+//OTG2_OTG_FORCE_COUNT_NOW_CNTL
>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
>+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
>+//OTG2_OTG_FLOW_CONTROL
>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
>+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
>+//OTG2_OTG_STEREO_FORCE_NEXT_EYE
>+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
>+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT                                       0x8
>+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT                                        0x10
>+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
>+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK                                         0x0000FF00L
>+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK                                          0x1FFF0000L
>+//OTG2_OTG_CONTROL
>+#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
>+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
>+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
>+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
>+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
>+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
>+#define OTG2_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT                                                0x18
>+#define OTG2_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT                                                     0x1e
>+#define OTG2_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT                                                0x1f
>+#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
>+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
>+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
>+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
>+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
>+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
>+#define OTG2_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK                                                  0x01000000L
>+#define OTG2_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK                                                       0x40000000L
>+#define OTG2_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK                                                  0x80000000L
>+//OTG2_OTG_BLANK_CONTROL
>+#define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT                                                0x0
>+#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT                                                      0x8
>+#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT                                                      0x10
>+#define OTG2_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK                                                  0x00000001L
>+#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK                                                        0x00000100L
>+#define OTG2_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK                                                        0x00010000L
>+//OTG2_OTG_PIPE_ABORT_CONTROL
>+#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT                                                    0x0
>+#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT                                               0x8
>+#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK                                                      0x00000001L
>+#define OTG2_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK                                                 0x00000100L
>+//OTG2_OTG_INTERLACE_CONTROL
>+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
>+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
>+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
>+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
>+//OTG2_OTG_INTERLACE_STATUS
>+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
>+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
>+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
>+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
>+//OTG2_OTG_PIXEL_DATA_READBACK0
>+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
>+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
>+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
>+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
>+//OTG2_OTG_PIXEL_DATA_READBACK1
>+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
>+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
>+//OTG2_OTG_STATUS
>+#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
>+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
>+#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
>+#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
>+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
>+#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
>+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
>+#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
>+#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
>+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
>+#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
>+#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
>+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
>+#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
>+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
>+#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
>+//OTG2_OTG_STATUS_POSITION
>+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
>+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
>+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
>+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
>+//OTG2_OTG_NOM_VERT_POSITION
>+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
>+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
>+//OTG2_OTG_STATUS_FRAME_COUNT
>+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
>+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
>+//OTG2_OTG_STATUS_VF_COUNT
>+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
>+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
>+//OTG2_OTG_STATUS_HV_COUNT
>+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
>+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
>+//OTG2_OTG_COUNT_CONTROL
>+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
>+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
>+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
>+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
>+//OTG2_OTG_COUNT_RESET
>+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
>+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
>+//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
>+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
>+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
>+//OTG2_OTG_VERT_SYNC_CONTROL
>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
>+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
>+//OTG2_OTG_STEREO_STATUS
>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
>+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
>+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
>+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
>+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
>+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
>+//OTG2_OTG_STEREO_CONTROL
>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
>+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
>+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
>+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
>+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
>+//OTG2_OTG_SNAPSHOT_STATUS
>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
>+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
>+//OTG2_OTG_SNAPSHOT_CONTROL
>+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
>+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
>+//OTG2_OTG_SNAPSHOT_POSITION
>+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
>+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
>+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
>+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
>+//OTG2_OTG_SNAPSHOT_FRAME
>+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
>+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
>+//OTG2_OTG_INTERRUPT_CONTROL
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
>+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
>+//OTG2_OTG_UPDATE_LOCK
>+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
>+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
>+//OTG2_OTG_DOUBLE_BUFFER_CONTROL
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT                         0x2
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT                               0x3
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT                           0x4
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT                                0x10
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT                              0x18
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK                           0x00000004L
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK                                 0x00000008L
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK                             0x00000010L
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK                                  0x00010000L
>+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK                                0x03000000L
>+//OTG2_OTG_MASTER_EN
>+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
>+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
>+//OTG2_OTG_BLANK_DATA_COLOR
>+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
>+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
>+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
>+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
>+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
>+#define OTG2_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
>+//OTG2_OTG_BLANK_DATA_COLOR_EXT
>+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
>+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
>+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
>+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
>+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
>+#define OTG2_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
>+//OTG2_OTG_BLACK_COLOR
>+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT                                                     0x0
>+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT                                                      0xa
>+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT                                                     0x14
>+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK                                                       0x000003FFL
>+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK                                                        0x000FFC00L
>+#define OTG2_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK                                                       0x3FF00000L
>+//OTG2_OTG_BLACK_COLOR_EXT
>+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT                                             0x0
>+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT                                              0x8
>+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT                                             0x10
>+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK                                               0x0000003FL
>+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK                                                0x00003F00L
>+#define OTG2_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK                                               0x003F0000L
>+//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
>+//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
>+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
>+//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION
>+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
>+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
>+//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL
>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
>+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
>+//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION
>+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
>+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
>+//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL
>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
>+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
>+//OTG2_OTG_CRC_CNTL
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
>+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
>+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
>+//OTG2_OTG_CRC_CNTL2
>+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
>+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
>+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
>+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
>+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
>+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
>+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
>+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
>+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL
>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
>+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
>+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL
>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
>+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
>+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL
>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
>+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
>+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL
>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
>+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
>+//OTG2_OTG_CRC0_DATA_RG
>+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
>+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
>+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG2_OTG_CRC0_DATA_B
>+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
>+#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
>+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
>+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL
>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
>+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
>+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL
>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
>+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
>+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL
>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
>+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
>+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL
>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
>+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
>+//OTG2_OTG_CRC1_DATA_RG
>+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
>+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
>+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG2_OTG_CRC1_DATA_B
>+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
>+#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
>+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
>+//OTG2_OTG_CRC2_DATA_RG
>+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
>+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
>+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG2_OTG_CRC2_DATA_B
>+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
>+#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
>+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
>+//OTG2_OTG_CRC3_DATA_RG
>+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
>+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
>+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG2_OTG_CRC3_DATA_B
>+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
>+#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
>+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
>+//OTG2_OTG_CRC_SIG_RED_GREEN_MASK
>+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
>+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
>+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
>+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
>+//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK
>+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
>+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
>+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
>+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
>+//OTG2_OTG_STATIC_SCREEN_CONTROL
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
>+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
>+//OTG2_OTG_3D_STRUCTURE_CONTROL
>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
>+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
>+//OTG2_OTG_GSL_VSYNC_GAP
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
>+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
>+//OTG2_OTG_MASTER_UPDATE_MODE
>+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
>+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
>+//OTG2_OTG_CLOCK_CONTROL
>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
>+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
>+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
>+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
>+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
>+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
>+//OTG2_OTG_VSTARTUP_PARAM
>+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
>+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
>+//OTG2_OTG_VUPDATE_PARAM
>+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
>+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
>+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
>+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
>+//OTG2_OTG_VREADY_PARAM
>+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
>+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
>+//OTG2_OTG_GLOBAL_SYNC_STATUS
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
>+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
>+//OTG2_OTG_MASTER_UPDATE_LOCK
>+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
>+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
>+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
>+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
>+//OTG2_OTG_GSL_CONTROL
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
>+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
>+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
>+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
>+//OTG2_OTG_GSL_WINDOW_X
>+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
>+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
>+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
>+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
>+//OTG2_OTG_GSL_WINDOW_Y
>+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
>+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
>+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
>+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
>+//OTG2_OTG_VUPDATE_KEEPOUT
>+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
>+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
>+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
>+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
>+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
>+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
>+//OTG2_OTG_GLOBAL_CONTROL0
>+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT                                0x0
>+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT                             0x8
>+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
>+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK                                  0x000000FFL
>+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK                               0x00000100L
>+#define OTG2_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
>+//OTG2_OTG_GLOBAL_CONTROL1
>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT                                              0x0
>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT                                              0x10
>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK                                                0x00007FFFL
>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK                                                0x7FFF0000L
>+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
>+//OTG2_OTG_GLOBAL_CONTROL2
>+#define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT                                                  0x0
>+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
>+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
>+#define OTG2_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT                                        0x1d
>+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
>+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
>+#define OTG2_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK                                                    0x000003FFL
>+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
>+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
>+#define OTG2_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK                                          0x20000000L
>+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
>+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
>+//OTG2_OTG_GLOBAL_CONTROL3
>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT                          0x8
>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
>+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK                            0x00000100L
>+//OTG2_OTG_TRIG_MANUAL_CONTROL
>+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
>+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
>+//OTG2_OTG_MANUAL_FLOW_CONTROL
>+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
>+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
>+//OTG2_OTG_RANGE_TIMING_INT_STATUS
>+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                             0x0
>+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT                         0x4
>+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                       0x8
>+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                     0xc
>+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                    0x10
>+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK                               0x00000001L
>+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK                           0x00000010L
>+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK                         0x00000100L
>+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                       0x00001000L
>+#define OTG2_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                      0x00010000L
>+//OTG2_OTG_DRR_CONTROL
>+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
>+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
>+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000007L
>+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
>+//OTG2_OTG_REQUEST_CONTROL
>+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
>+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
>+//OTG2_OTG_DSC_START_POSITION
>+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
>+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
>+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
>+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
>+//OTG2_OTG_PIPE_UPDATE_STATUS
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT                                                    0x1
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT                                              0x2
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT                                           0x5
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT                                     0x6
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT                                           0x9
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT                                     0xa
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK                                                      0x00000002L
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK                                                0x00000004L
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK                                             0x00000020L
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK                                       0x00000040L
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK                                             0x00000200L
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK                                       0x00000400L
>+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
>+//OTG2_OTG_SPARE_REGISTER
>+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
>+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_otg3_dispdec
>+//OTG3_OTG_H_TOTAL
>+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
>+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
>+//OTG3_OTG_H_BLANK_START_END
>+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
>+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
>+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
>+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
>+//OTG3_OTG_H_SYNC_A
>+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
>+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
>+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
>+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
>+//OTG3_OTG_H_SYNC_A_CNTL
>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
>+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
>+//OTG3_OTG_H_TIMING_CNTL
>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT                                                   0x0
>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT                                       0x8
>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK                                                     0x00000001L
>+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK                                         0x00000100L
>+//OTG3_OTG_V_TOTAL
>+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
>+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
>+//OTG3_OTG_V_TOTAL_MIN
>+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
>+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
>+//OTG3_OTG_V_TOTAL_MAX
>+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
>+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
>+//OTG3_OTG_V_TOTAL_MID
>+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
>+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
>+//OTG3_OTG_V_TOTAL_CONTROL
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
>+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
>+//OTG3_OTG_V_TOTAL_INT_STATUS
>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
>+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
>+//OTG3_OTG_VSYNC_NOM_INT_STATUS
>+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
>+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
>+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
>+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
>+//OTG3_OTG_V_BLANK_START_END
>+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
>+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
>+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
>+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
>+//OTG3_OTG_V_SYNC_A
>+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
>+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
>+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
>+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
>+//OTG3_OTG_V_SYNC_A_CNTL
>+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
>+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
>+//OTG3_OTG_TRIGA_CNTL
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
>+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
>+//OTG3_OTG_TRIGA_MANUAL_TRIG
>+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
>+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
>+//OTG3_OTG_TRIGB_CNTL
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
>+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
>+//OTG3_OTG_TRIGB_MANUAL_TRIG
>+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
>+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
>+//OTG3_OTG_FORCE_COUNT_NOW_CNTL
>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
>+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
>+//OTG3_OTG_FLOW_CONTROL
>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
>+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
>+//OTG3_OTG_STEREO_FORCE_NEXT_EYE
>+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
>+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT                                       0x8
>+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT                                        0x10
>+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
>+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK                                         0x0000FF00L
>+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK                                          0x1FFF0000L
>+//OTG3_OTG_CONTROL
>+#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
>+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
>+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
>+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
>+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
>+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
>+#define OTG3_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT                                                0x18
>+#define OTG3_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT                                                     0x1e
>+#define OTG3_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT                                                0x1f
>+#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
>+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
>+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
>+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
>+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
>+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
>+#define OTG3_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK                                                  0x01000000L
>+#define OTG3_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK                                                       0x40000000L
>+#define OTG3_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK                                                  0x80000000L
>+//OTG3_OTG_BLANK_CONTROL
>+#define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT                                                0x0
>+#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT                                                      0x8
>+#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT                                                      0x10
>+#define OTG3_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK                                                  0x00000001L
>+#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK                                                        0x00000100L
>+#define OTG3_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK                                                        0x00010000L
>+//OTG3_OTG_PIPE_ABORT_CONTROL
>+#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT                                                    0x0
>+#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT                                               0x8
>+#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK                                                      0x00000001L
>+#define OTG3_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK                                                 0x00000100L
>+//OTG3_OTG_INTERLACE_CONTROL
>+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
>+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
>+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
>+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
>+//OTG3_OTG_INTERLACE_STATUS
>+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
>+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
>+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
>+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
>+//OTG3_OTG_PIXEL_DATA_READBACK0
>+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
>+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
>+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
>+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
>+//OTG3_OTG_PIXEL_DATA_READBACK1
>+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
>+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
>+//OTG3_OTG_STATUS
>+#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
>+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
>+#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
>+#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
>+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
>+#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
>+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
>+#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
>+#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
>+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
>+#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
>+#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
>+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
>+#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
>+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
>+#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
>+//OTG3_OTG_STATUS_POSITION
>+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
>+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
>+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
>+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
>+//OTG3_OTG_NOM_VERT_POSITION
>+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
>+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
>+//OTG3_OTG_STATUS_FRAME_COUNT
>+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
>+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
>+//OTG3_OTG_STATUS_VF_COUNT
>+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
>+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
>+//OTG3_OTG_STATUS_HV_COUNT
>+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
>+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
>+//OTG3_OTG_COUNT_CONTROL
>+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
>+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
>+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
>+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
>+//OTG3_OTG_COUNT_RESET
>+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
>+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
>+//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
>+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
>+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
>+//OTG3_OTG_VERT_SYNC_CONTROL
>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
>+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
>+//OTG3_OTG_STEREO_STATUS
>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
>+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
>+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
>+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
>+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
>+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
>+//OTG3_OTG_STEREO_CONTROL
>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
>+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
>+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
>+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
>+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
>+//OTG3_OTG_SNAPSHOT_STATUS
>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
>+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
>+//OTG3_OTG_SNAPSHOT_CONTROL
>+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
>+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
>+//OTG3_OTG_SNAPSHOT_POSITION
>+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
>+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
>+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
>+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
>+//OTG3_OTG_SNAPSHOT_FRAME
>+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
>+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
>+//OTG3_OTG_INTERRUPT_CONTROL
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
>+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
>+//OTG3_OTG_UPDATE_LOCK
>+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
>+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
>+//OTG3_OTG_DOUBLE_BUFFER_CONTROL
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT                         0x2
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT                               0x3
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT                           0x4
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT                                0x10
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT                              0x18
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK                           0x00000004L
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK                                 0x00000008L
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK                             0x00000010L
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK                                  0x00010000L
>+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK                                0x03000000L
>+//OTG3_OTG_MASTER_EN
>+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
>+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
>+//OTG3_OTG_BLANK_DATA_COLOR
>+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
>+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
>+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
>+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
>+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
>+#define OTG3_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
>+//OTG3_OTG_BLANK_DATA_COLOR_EXT
>+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
>+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
>+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
>+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
>+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
>+#define OTG3_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
>+//OTG3_OTG_BLACK_COLOR
>+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT                                                     0x0
>+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT                                                      0xa
>+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT                                                     0x14
>+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK                                                       0x000003FFL
>+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK                                                        0x000FFC00L
>+#define OTG3_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK                                                       0x3FF00000L
>+//OTG3_OTG_BLACK_COLOR_EXT
>+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT                                             0x0
>+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT                                              0x8
>+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT                                             0x10
>+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK                                               0x0000003FL
>+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK                                                0x00003F00L
>+#define OTG3_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK                                               0x003F0000L
>+//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
>+//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
>+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
>+//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION
>+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
>+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
>+//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL
>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
>+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
>+//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION
>+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
>+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
>+//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL
>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
>+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
>+//OTG3_OTG_CRC_CNTL
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
>+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
>+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
>+//OTG3_OTG_CRC_CNTL2
>+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
>+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
>+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
>+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
>+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
>+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
>+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
>+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
>+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL
>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
>+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
>+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL
>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
>+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
>+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL
>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
>+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
>+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL
>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
>+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
>+//OTG3_OTG_CRC0_DATA_RG
>+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
>+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
>+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG3_OTG_CRC0_DATA_B
>+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
>+#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
>+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
>+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL
>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
>+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
>+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL
>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
>+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
>+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL
>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
>+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
>+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL
>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
>+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
>+//OTG3_OTG_CRC1_DATA_RG
>+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
>+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
>+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG3_OTG_CRC1_DATA_B
>+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
>+#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
>+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
>+//OTG3_OTG_CRC2_DATA_RG
>+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
>+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
>+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG3_OTG_CRC2_DATA_B
>+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
>+#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
>+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
>+//OTG3_OTG_CRC3_DATA_RG
>+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
>+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
>+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG3_OTG_CRC3_DATA_B
>+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
>+#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
>+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
>+//OTG3_OTG_CRC_SIG_RED_GREEN_MASK
>+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
>+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
>+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
>+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
>+//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK
>+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
>+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
>+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
>+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
>+//OTG3_OTG_STATIC_SCREEN_CONTROL
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
>+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
>+//OTG3_OTG_3D_STRUCTURE_CONTROL
>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
>+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
>+//OTG3_OTG_GSL_VSYNC_GAP
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
>+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
>+//OTG3_OTG_MASTER_UPDATE_MODE
>+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
>+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
>+//OTG3_OTG_CLOCK_CONTROL
>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
>+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
>+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
>+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
>+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
>+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
>+//OTG3_OTG_VSTARTUP_PARAM
>+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
>+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
>+//OTG3_OTG_VUPDATE_PARAM
>+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
>+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
>+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
>+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
>+//OTG3_OTG_VREADY_PARAM
>+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
>+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
>+//OTG3_OTG_GLOBAL_SYNC_STATUS
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
>+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
>+//OTG3_OTG_MASTER_UPDATE_LOCK
>+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
>+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
>+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
>+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
>+//OTG3_OTG_GSL_CONTROL
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
>+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
>+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
>+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
>+//OTG3_OTG_GSL_WINDOW_X
>+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
>+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
>+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
>+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
>+//OTG3_OTG_GSL_WINDOW_Y
>+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
>+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
>+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
>+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
>+//OTG3_OTG_VUPDATE_KEEPOUT
>+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
>+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
>+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
>+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
>+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
>+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
>+//OTG3_OTG_GLOBAL_CONTROL0
>+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT                                0x0
>+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT                             0x8
>+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
>+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK                                  0x000000FFL
>+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK                               0x00000100L
>+#define OTG3_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
>+//OTG3_OTG_GLOBAL_CONTROL1
>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT                                              0x0
>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT                                              0x10
>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK                                                0x00007FFFL
>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK                                                0x7FFF0000L
>+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
>+//OTG3_OTG_GLOBAL_CONTROL2
>+#define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT                                                  0x0
>+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
>+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
>+#define OTG3_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT                                        0x1d
>+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
>+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
>+#define OTG3_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK                                                    0x000003FFL
>+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
>+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
>+#define OTG3_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK                                          0x20000000L
>+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
>+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
>+//OTG3_OTG_GLOBAL_CONTROL3
>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT                          0x8
>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
>+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK                            0x00000100L
>+//OTG3_OTG_TRIG_MANUAL_CONTROL
>+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
>+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
>+//OTG3_OTG_MANUAL_FLOW_CONTROL
>+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
>+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
>+//OTG3_OTG_RANGE_TIMING_INT_STATUS
>+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                             0x0
>+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT                         0x4
>+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                       0x8
>+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                     0xc
>+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                    0x10
>+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK                               0x00000001L
>+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK                           0x00000010L
>+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK                         0x00000100L
>+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                       0x00001000L
>+#define OTG3_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                      0x00010000L
>+//OTG3_OTG_DRR_CONTROL
>+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
>+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
>+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000007L
>+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
>+//OTG3_OTG_REQUEST_CONTROL
>+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
>+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
>+//OTG3_OTG_DSC_START_POSITION
>+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
>+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
>+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
>+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
>+//OTG3_OTG_PIPE_UPDATE_STATUS
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT                                                    0x1
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT                                              0x2
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT                                           0x5
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT                                     0x6
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT                                           0x9
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT                                     0xa
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK                                                      0x00000002L
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK                                                0x00000004L
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK                                             0x00000020L
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK                                       0x00000040L
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK                                             0x00000200L
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK                                       0x00000400L
>+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
>+//OTG3_OTG_SPARE_REGISTER
>+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
>+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_otg4_dispdec
>+//OTG4_OTG_H_TOTAL
>+#define OTG4_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
>+#define OTG4_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
>+//OTG4_OTG_H_BLANK_START_END
>+#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
>+#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
>+#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
>+#define OTG4_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
>+//OTG4_OTG_H_SYNC_A
>+#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
>+#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
>+#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
>+#define OTG4_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
>+//OTG4_OTG_H_SYNC_A_CNTL
>+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
>+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
>+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
>+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
>+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
>+#define OTG4_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
>+//OTG4_OTG_H_TIMING_CNTL
>+#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT                                                   0x0
>+#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT                                       0x8
>+#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK                                                     0x00000001L
>+#define OTG4_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK                                         0x00000100L
>+//OTG4_OTG_V_TOTAL
>+#define OTG4_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
>+#define OTG4_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
>+//OTG4_OTG_V_TOTAL_MIN
>+#define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
>+#define OTG4_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
>+//OTG4_OTG_V_TOTAL_MAX
>+#define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
>+#define OTG4_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
>+//OTG4_OTG_V_TOTAL_MID
>+#define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
>+#define OTG4_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
>+//OTG4_OTG_V_TOTAL_CONTROL
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
>+#define OTG4_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
>+//OTG4_OTG_V_TOTAL_INT_STATUS
>+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
>+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
>+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
>+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
>+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
>+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
>+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
>+#define OTG4_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
>+//OTG4_OTG_VSYNC_NOM_INT_STATUS
>+#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
>+#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
>+#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
>+#define OTG4_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
>+//OTG4_OTG_V_BLANK_START_END
>+#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
>+#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
>+#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
>+#define OTG4_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
>+//OTG4_OTG_V_SYNC_A
>+#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
>+#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
>+#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
>+#define OTG4_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
>+//OTG4_OTG_V_SYNC_A_CNTL
>+#define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
>+#define OTG4_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
>+//OTG4_OTG_TRIGA_CNTL
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
>+#define OTG4_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
>+//OTG4_OTG_TRIGA_MANUAL_TRIG
>+#define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
>+#define OTG4_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
>+//OTG4_OTG_TRIGB_CNTL
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
>+#define OTG4_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
>+//OTG4_OTG_TRIGB_MANUAL_TRIG
>+#define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
>+#define OTG4_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
>+//OTG4_OTG_FORCE_COUNT_NOW_CNTL
>+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
>+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
>+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
>+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
>+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
>+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
>+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
>+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
>+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
>+#define OTG4_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
>+//OTG4_OTG_FLOW_CONTROL
>+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
>+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
>+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
>+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
>+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
>+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
>+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
>+#define OTG4_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
>+//OTG4_OTG_STEREO_FORCE_NEXT_EYE
>+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
>+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT                                       0x8
>+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT                                        0x10
>+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
>+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK                                         0x0000FF00L
>+#define OTG4_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK                                          0x1FFF0000L
>+//OTG4_OTG_CONTROL
>+#define OTG4_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
>+#define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
>+#define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
>+#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
>+#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
>+#define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
>+#define OTG4_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT                                                0x18
>+#define OTG4_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT                                                     0x1e
>+#define OTG4_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT                                                0x1f
>+#define OTG4_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
>+#define OTG4_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
>+#define OTG4_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
>+#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
>+#define OTG4_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
>+#define OTG4_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
>+#define OTG4_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK                                                  0x01000000L
>+#define OTG4_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK                                                       0x40000000L
>+#define OTG4_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK                                                  0x80000000L
>+//OTG4_OTG_BLANK_CONTROL
>+#define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT                                                0x0
>+#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT                                                      0x8
>+#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT                                                      0x10
>+#define OTG4_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK                                                  0x00000001L
>+#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK                                                        0x00000100L
>+#define OTG4_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK                                                        0x00010000L
>+//OTG4_OTG_PIPE_ABORT_CONTROL
>+#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT                                                    0x0
>+#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT                                               0x8
>+#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK                                                      0x00000001L
>+#define OTG4_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK                                                 0x00000100L
>+//OTG4_OTG_INTERLACE_CONTROL
>+#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
>+#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
>+#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
>+#define OTG4_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
>+//OTG4_OTG_INTERLACE_STATUS
>+#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
>+#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
>+#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
>+#define OTG4_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
>+//OTG4_OTG_PIXEL_DATA_READBACK0
>+#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
>+#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
>+#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
>+#define OTG4_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
>+//OTG4_OTG_PIXEL_DATA_READBACK1
>+#define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
>+#define OTG4_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
>+//OTG4_OTG_STATUS
>+#define OTG4_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
>+#define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
>+#define OTG4_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
>+#define OTG4_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
>+#define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
>+#define OTG4_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
>+#define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
>+#define OTG4_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
>+#define OTG4_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
>+#define OTG4_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
>+#define OTG4_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
>+#define OTG4_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
>+#define OTG4_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
>+#define OTG4_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
>+#define OTG4_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
>+#define OTG4_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
>+//OTG4_OTG_STATUS_POSITION
>+#define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
>+#define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
>+#define OTG4_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
>+#define OTG4_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
>+//OTG4_OTG_NOM_VERT_POSITION
>+#define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
>+#define OTG4_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
>+//OTG4_OTG_STATUS_FRAME_COUNT
>+#define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
>+#define OTG4_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
>+//OTG4_OTG_STATUS_VF_COUNT
>+#define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
>+#define OTG4_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
>+//OTG4_OTG_STATUS_HV_COUNT
>+#define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
>+#define OTG4_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
>+//OTG4_OTG_COUNT_CONTROL
>+#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
>+#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
>+#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
>+#define OTG4_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
>+//OTG4_OTG_COUNT_RESET
>+#define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
>+#define OTG4_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
>+//OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
>+#define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
>+#define OTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
>+//OTG4_OTG_VERT_SYNC_CONTROL
>+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
>+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
>+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
>+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
>+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
>+#define OTG4_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
>+//OTG4_OTG_STEREO_STATUS
>+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
>+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
>+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
>+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
>+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
>+#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
>+#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
>+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
>+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
>+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
>+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
>+#define OTG4_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
>+#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
>+#define OTG4_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
>+//OTG4_OTG_STEREO_CONTROL
>+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
>+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
>+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
>+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
>+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
>+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
>+#define OTG4_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
>+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
>+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
>+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
>+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
>+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
>+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
>+#define OTG4_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
>+#define OTG4_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
>+#define OTG4_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
>+//OTG4_OTG_SNAPSHOT_STATUS
>+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
>+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
>+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
>+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
>+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
>+#define OTG4_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
>+//OTG4_OTG_SNAPSHOT_CONTROL
>+#define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
>+#define OTG4_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
>+//OTG4_OTG_SNAPSHOT_POSITION
>+#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
>+#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
>+#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
>+#define OTG4_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
>+//OTG4_OTG_SNAPSHOT_FRAME
>+#define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
>+#define OTG4_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
>+//OTG4_OTG_INTERRUPT_CONTROL
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
>+#define OTG4_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
>+//OTG4_OTG_UPDATE_LOCK
>+#define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
>+#define OTG4_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
>+//OTG4_OTG_DOUBLE_BUFFER_CONTROL
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT                         0x2
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT                               0x3
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT                           0x4
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT                                0x10
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT                              0x18
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK                           0x00000004L
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK                                 0x00000008L
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK                             0x00000010L
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK                                  0x00010000L
>+#define OTG4_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK                                0x03000000L
>+//OTG4_OTG_MASTER_EN
>+#define OTG4_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
>+#define OTG4_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
>+//OTG4_OTG_BLANK_DATA_COLOR
>+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
>+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
>+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
>+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
>+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
>+#define OTG4_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
>+//OTG4_OTG_BLANK_DATA_COLOR_EXT
>+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
>+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
>+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
>+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
>+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
>+#define OTG4_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
>+//OTG4_OTG_BLACK_COLOR
>+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT                                                     0x0
>+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT                                                      0xa
>+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT                                                     0x14
>+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK                                                       0x000003FFL
>+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK                                                        0x000FFC00L
>+#define OTG4_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK                                                       0x3FF00000L
>+//OTG4_OTG_BLACK_COLOR_EXT
>+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT                                             0x0
>+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT                                              0x8
>+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT                                             0x10
>+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK                                               0x0000003FL
>+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK                                                0x00003F00L
>+#define OTG4_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK                                               0x003F0000L
>+//OTG4_OTG_VERTICAL_INTERRUPT0_POSITION
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
>+//OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
>+#define OTG4_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
>+//OTG4_OTG_VERTICAL_INTERRUPT1_POSITION
>+#define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
>+#define OTG4_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
>+//OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL
>+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
>+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
>+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
>+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
>+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
>+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
>+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
>+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
>+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
>+#define OTG4_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
>+//OTG4_OTG_VERTICAL_INTERRUPT2_POSITION
>+#define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
>+#define OTG4_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
>+//OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL
>+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
>+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
>+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
>+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
>+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
>+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
>+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
>+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
>+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
>+#define OTG4_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
>+//OTG4_OTG_CRC_CNTL
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
>+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
>+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
>+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
>+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
>+#define OTG4_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
>+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
>+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
>+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
>+#define OTG4_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
>+//OTG4_OTG_CRC_CNTL2
>+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
>+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
>+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
>+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
>+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
>+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
>+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
>+#define OTG4_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
>+//OTG4_OTG_CRC0_WINDOWA_X_CONTROL
>+#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
>+#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
>+#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
>+#define OTG4_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
>+//OTG4_OTG_CRC0_WINDOWA_Y_CONTROL
>+#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
>+#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
>+#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
>+#define OTG4_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
>+//OTG4_OTG_CRC0_WINDOWB_X_CONTROL
>+#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
>+#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
>+#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
>+#define OTG4_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
>+//OTG4_OTG_CRC0_WINDOWB_Y_CONTROL
>+#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
>+#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
>+#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
>+#define OTG4_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
>+//OTG4_OTG_CRC0_DATA_RG
>+#define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
>+#define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
>+#define OTG4_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG4_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG4_OTG_CRC0_DATA_B
>+#define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
>+#define OTG4_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
>+#define OTG4_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG4_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
>+//OTG4_OTG_CRC1_WINDOWA_X_CONTROL
>+#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
>+#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
>+#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
>+#define OTG4_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
>+//OTG4_OTG_CRC1_WINDOWA_Y_CONTROL
>+#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
>+#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
>+#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
>+#define OTG4_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
>+//OTG4_OTG_CRC1_WINDOWB_X_CONTROL
>+#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
>+#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
>+#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
>+#define OTG4_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
>+//OTG4_OTG_CRC1_WINDOWB_Y_CONTROL
>+#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
>+#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
>+#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
>+#define OTG4_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
>+//OTG4_OTG_CRC1_DATA_RG
>+#define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
>+#define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
>+#define OTG4_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG4_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG4_OTG_CRC1_DATA_B
>+#define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
>+#define OTG4_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
>+#define OTG4_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG4_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
>+//OTG4_OTG_CRC2_DATA_RG
>+#define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
>+#define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
>+#define OTG4_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG4_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG4_OTG_CRC2_DATA_B
>+#define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
>+#define OTG4_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
>+#define OTG4_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG4_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
>+//OTG4_OTG_CRC3_DATA_RG
>+#define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
>+#define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
>+#define OTG4_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG4_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG4_OTG_CRC3_DATA_B
>+#define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
>+#define OTG4_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
>+#define OTG4_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG4_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
>+//OTG4_OTG_CRC_SIG_RED_GREEN_MASK
>+#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
>+#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
>+#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
>+#define OTG4_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
>+//OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK
>+#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
>+#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
>+#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
>+#define OTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
>+//OTG4_OTG_STATIC_SCREEN_CONTROL
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
>+#define OTG4_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
>+//OTG4_OTG_3D_STRUCTURE_CONTROL
>+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
>+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
>+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
>+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
>+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
>+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
>+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
>+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
>+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
>+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
>+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
>+#define OTG4_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
>+//OTG4_OTG_GSL_VSYNC_GAP
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
>+#define OTG4_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
>+//OTG4_OTG_MASTER_UPDATE_MODE
>+#define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
>+#define OTG4_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
>+//OTG4_OTG_CLOCK_CONTROL
>+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
>+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
>+#define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
>+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
>+#define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
>+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
>+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
>+#define OTG4_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
>+#define OTG4_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
>+#define OTG4_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
>+//OTG4_OTG_VSTARTUP_PARAM
>+#define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
>+#define OTG4_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
>+//OTG4_OTG_VUPDATE_PARAM
>+#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
>+#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
>+#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
>+#define OTG4_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
>+//OTG4_OTG_VREADY_PARAM
>+#define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
>+#define OTG4_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
>+//OTG4_OTG_GLOBAL_SYNC_STATUS
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
>+#define OTG4_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
>+//OTG4_OTG_MASTER_UPDATE_LOCK
>+#define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
>+#define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
>+#define OTG4_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
>+#define OTG4_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
>+//OTG4_OTG_GSL_CONTROL
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
>+#define OTG4_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
>+#define OTG4_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
>+#define OTG4_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
>+//OTG4_OTG_GSL_WINDOW_X
>+#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
>+#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
>+#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
>+#define OTG4_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
>+//OTG4_OTG_GSL_WINDOW_Y
>+#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
>+#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
>+#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
>+#define OTG4_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
>+//OTG4_OTG_VUPDATE_KEEPOUT
>+#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
>+#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
>+#define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
>+#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
>+#define OTG4_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
>+#define OTG4_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
>+//OTG4_OTG_GLOBAL_CONTROL0
>+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT                                0x0
>+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT                             0x8
>+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
>+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK                                  0x000000FFL
>+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK                               0x00000100L
>+#define OTG4_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
>+//OTG4_OTG_GLOBAL_CONTROL1
>+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT                                              0x0
>+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT                                              0x10
>+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
>+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK                                                0x00007FFFL
>+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK                                                0x7FFF0000L
>+#define OTG4_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
>+//OTG4_OTG_GLOBAL_CONTROL2
>+#define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT                                                  0x0
>+#define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
>+#define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
>+#define OTG4_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT                                        0x1d
>+#define OTG4_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
>+#define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
>+#define OTG4_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK                                                    0x000003FFL
>+#define OTG4_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
>+#define OTG4_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
>+#define OTG4_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK                                          0x20000000L
>+#define OTG4_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
>+#define OTG4_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
>+//OTG4_OTG_GLOBAL_CONTROL3
>+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
>+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
>+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT                          0x8
>+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
>+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
>+#define OTG4_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK                            0x00000100L
>+//OTG4_OTG_TRIG_MANUAL_CONTROL
>+#define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
>+#define OTG4_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
>+//OTG4_OTG_MANUAL_FLOW_CONTROL
>+#define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
>+#define OTG4_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
>+//OTG4_OTG_RANGE_TIMING_INT_STATUS
>+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                             0x0
>+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT                         0x4
>+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                       0x8
>+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                     0xc
>+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                    0x10
>+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK                               0x00000001L
>+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK                           0x00000010L
>+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK                         0x00000100L
>+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                       0x00001000L
>+#define OTG4_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                      0x00010000L
>+//OTG4_OTG_DRR_CONTROL
>+#define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
>+#define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
>+#define OTG4_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000007L
>+#define OTG4_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
>+//OTG4_OTG_REQUEST_CONTROL
>+#define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
>+#define OTG4_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
>+//OTG4_OTG_DSC_START_POSITION
>+#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
>+#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
>+#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
>+#define OTG4_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
>+//OTG4_OTG_PIPE_UPDATE_STATUS
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT                                                    0x1
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT                                              0x2
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT                                           0x5
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT                                     0x6
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT                                           0x9
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT                                     0xa
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK                                                      0x00000002L
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK                                                0x00000004L
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK                                             0x00000020L
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK                                       0x00000040L
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK                                             0x00000200L
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK                                       0x00000400L
>+#define OTG4_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
>+//OTG4_OTG_SPARE_REGISTER
>+#define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
>+#define OTG4_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_otg5_dispdec
>+//OTG5_OTG_H_TOTAL
>+#define OTG5_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
>+#define OTG5_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
>+//OTG5_OTG_H_BLANK_START_END
>+#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
>+#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
>+#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
>+#define OTG5_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
>+//OTG5_OTG_H_SYNC_A
>+#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
>+#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
>+#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
>+#define OTG5_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
>+//OTG5_OTG_H_SYNC_A_CNTL
>+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
>+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
>+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
>+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
>+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
>+#define OTG5_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
>+//OTG5_OTG_H_TIMING_CNTL
>+#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2__SHIFT                                                   0x0
>+#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE__SHIFT                                       0x8
>+#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_MASK                                                     0x00000001L
>+#define OTG5_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_BY2_UPDATE_MODE_MASK                                         0x00000100L
>+//OTG5_OTG_V_TOTAL
>+#define OTG5_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
>+#define OTG5_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
>+//OTG5_OTG_V_TOTAL_MIN
>+#define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
>+#define OTG5_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
>+//OTG5_OTG_V_TOTAL_MAX
>+#define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
>+#define OTG5_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
>+//OTG5_OTG_V_TOTAL_MID
>+#define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
>+#define OTG5_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
>+//OTG5_OTG_V_TOTAL_CONTROL
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN__SHIFT                                          0x7
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_EN_MASK                                            0x00000080L
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
>+#define OTG5_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
>+//OTG5_OTG_V_TOTAL_INT_STATUS
>+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
>+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
>+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
>+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
>+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
>+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
>+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
>+#define OTG5_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
>+//OTG5_OTG_VSYNC_NOM_INT_STATUS
>+#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
>+#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
>+#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
>+#define OTG5_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
>+//OTG5_OTG_V_BLANK_START_END
>+#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
>+#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
>+#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
>+#define OTG5_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
>+//OTG5_OTG_V_SYNC_A
>+#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
>+#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
>+#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
>+#define OTG5_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
>+//OTG5_OTG_V_SYNC_A_CNTL
>+#define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
>+#define OTG5_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
>+//OTG5_OTG_TRIGA_CNTL
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
>+#define OTG5_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
>+//OTG5_OTG_TRIGA_MANUAL_TRIG
>+#define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
>+#define OTG5_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
>+//OTG5_OTG_TRIGB_CNTL
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
>+#define OTG5_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
>+//OTG5_OTG_TRIGB_MANUAL_TRIG
>+#define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
>+#define OTG5_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
>+//OTG5_OTG_FORCE_COUNT_NOW_CNTL
>+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
>+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
>+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
>+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
>+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
>+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
>+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
>+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
>+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
>+#define OTG5_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
>+//OTG5_OTG_FLOW_CONTROL
>+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
>+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
>+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
>+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
>+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
>+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
>+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
>+#define OTG5_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
>+//OTG5_OTG_STEREO_FORCE_NEXT_EYE
>+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
>+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER__SHIFT                                       0x8
>+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER__SHIFT                                        0x10
>+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
>+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_FRAME_COUNTER_MASK                                         0x0000FF00L
>+#define OTG5_OTG_STEREO_FORCE_NEXT_EYE__OTG_AVSYNC_LINE_COUNTER_MASK                                          0x1FFF0000L
>+//OTG5_OTG_CONTROL
>+#define OTG5_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
>+#define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
>+#define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
>+#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
>+#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
>+#define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
>+#define OTG5_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE__SHIFT                                                0x18
>+#define OTG5_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT__SHIFT                                                     0x1e
>+#define OTG5_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE__SHIFT                                                0x1f
>+#define OTG5_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
>+#define OTG5_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
>+#define OTG5_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
>+#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
>+#define OTG5_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
>+#define OTG5_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
>+#define OTG5_OTG_CONTROL__OTG_DISP_READ_REQUEST_DISABLE_MASK                                                  0x01000000L
>+#define OTG5_OTG_CONTROL__OTG_AVSYNC_LOCK_SNAPSHOT_MASK                                                       0x40000000L
>+#define OTG5_OTG_CONTROL__OTG_AVSYNC_VSYNC_N_HSYNC_MODE_MASK                                                  0x80000000L
>+//OTG5_OTG_BLANK_CONTROL
>+#define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE__SHIFT                                                0x0
>+#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN__SHIFT                                                      0x8
>+#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE__SHIFT                                                      0x10
>+#define OTG5_OTG_BLANK_CONTROL__OTG_CURRENT_BLANK_STATE_MASK                                                  0x00000001L
>+#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DATA_EN_MASK                                                        0x00000100L
>+#define OTG5_OTG_BLANK_CONTROL__OTG_BLANK_DE_MODE_MASK                                                        0x00010000L
>+//OTG5_OTG_PIPE_ABORT_CONTROL
>+#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT__SHIFT                                                    0x0
>+#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE__SHIFT                                               0x8
>+#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_MASK                                                      0x00000001L
>+#define OTG5_OTG_PIPE_ABORT_CONTROL__OTG_PIPE_ABORT_DONE_MASK                                                 0x00000100L
>+//OTG5_OTG_INTERLACE_CONTROL
>+#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
>+#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
>+#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
>+#define OTG5_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
>+//OTG5_OTG_INTERLACE_STATUS
>+#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
>+#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
>+#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
>+#define OTG5_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
>+//OTG5_OTG_PIXEL_DATA_READBACK0
>+#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
>+#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
>+#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
>+#define OTG5_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
>+//OTG5_OTG_PIXEL_DATA_READBACK1
>+#define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
>+#define OTG5_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
>+//OTG5_OTG_STATUS
>+#define OTG5_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
>+#define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
>+#define OTG5_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
>+#define OTG5_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
>+#define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
>+#define OTG5_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
>+#define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
>+#define OTG5_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
>+#define OTG5_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
>+#define OTG5_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
>+#define OTG5_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
>+#define OTG5_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
>+#define OTG5_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
>+#define OTG5_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
>+#define OTG5_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
>+#define OTG5_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
>+//OTG5_OTG_STATUS_POSITION
>+#define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
>+#define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
>+#define OTG5_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
>+#define OTG5_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
>+//OTG5_OTG_NOM_VERT_POSITION
>+#define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
>+#define OTG5_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
>+//OTG5_OTG_STATUS_FRAME_COUNT
>+#define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
>+#define OTG5_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
>+//OTG5_OTG_STATUS_VF_COUNT
>+#define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
>+#define OTG5_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
>+//OTG5_OTG_STATUS_HV_COUNT
>+#define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
>+#define OTG5_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
>+//OTG5_OTG_COUNT_CONTROL
>+#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
>+#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
>+#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
>+#define OTG5_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
>+//OTG5_OTG_COUNT_RESET
>+#define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
>+#define OTG5_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
>+//OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
>+#define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
>+#define OTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
>+//OTG5_OTG_VERT_SYNC_CONTROL
>+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
>+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
>+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
>+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
>+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
>+#define OTG5_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
>+//OTG5_OTG_STEREO_STATUS
>+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
>+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
>+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
>+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
>+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
>+#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
>+#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
>+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
>+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
>+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
>+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
>+#define OTG5_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
>+#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
>+#define OTG5_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
>+//OTG5_OTG_STEREO_CONTROL
>+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
>+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
>+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
>+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
>+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
>+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
>+#define OTG5_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
>+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
>+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
>+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
>+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
>+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
>+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
>+#define OTG5_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
>+#define OTG5_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
>+#define OTG5_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
>+//OTG5_OTG_SNAPSHOT_STATUS
>+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
>+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
>+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
>+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
>+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
>+#define OTG5_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
>+//OTG5_OTG_SNAPSHOT_CONTROL
>+#define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
>+#define OTG5_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
>+//OTG5_OTG_SNAPSHOT_POSITION
>+#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
>+#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
>+#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
>+#define OTG5_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
>+//OTG5_OTG_SNAPSHOT_FRAME
>+#define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
>+#define OTG5_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
>+//OTG5_OTG_INTERRUPT_CONTROL
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
>+#define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
>+//OTG5_OTG_UPDATE_LOCK
>+#define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
>+#define OTG5_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
>+//OTG5_OTG_DOUBLE_BUFFER_CONTROL
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING__SHIFT                         0x2
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING__SHIFT                               0x3
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING__SHIFT                           0x4
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT                                0x10
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE__SHIFT                              0x18
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_BY2_DB_UPDATE_PENDING_MASK                           0x00000004L
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_EN_UPDATE_PENDING_MASK                                 0x00000008L
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_PENDING_MASK                             0x00000010L
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_BLANK_DATA_DOUBLE_BUFFER_EN_MASK                                  0x00010000L
>+#define OTG5_OTG_DOUBLE_BUFFER_CONTROL__OTG_RANGE_TIMING_DBUF_UPDATE_MODE_MASK                                0x03000000L
>+//OTG5_OTG_MASTER_EN
>+#define OTG5_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
>+#define OTG5_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
>+//OTG5_OTG_BLANK_DATA_COLOR
>+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB__SHIFT                                        0x0
>+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y__SHIFT                                        0xa
>+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR__SHIFT                                         0x14
>+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_BLUE_CB_MASK                                          0x000003FFL
>+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_GREEN_Y_MASK                                          0x000FFC00L
>+#define OTG5_OTG_BLANK_DATA_COLOR__OTG_BLANK_DATA_COLOR_RED_CR_MASK                                           0x3FF00000L
>+//OTG5_OTG_BLANK_DATA_COLOR_EXT
>+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT                                0x0
>+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT                                0x8
>+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT                                 0x10
>+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK                                  0x0000003FL
>+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK                                  0x00003F00L
>+#define OTG5_OTG_BLANK_DATA_COLOR_EXT__OTG_BLANK_DATA_COLOR_RED_CR_EXT_MASK                                   0x003F0000L
>+//OTG5_OTG_BLACK_COLOR
>+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB__SHIFT                                                     0x0
>+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y__SHIFT                                                      0xa
>+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR__SHIFT                                                     0x14
>+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_B_CB_MASK                                                       0x000003FFL
>+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_G_Y_MASK                                                        0x000FFC00L
>+#define OTG5_OTG_BLACK_COLOR__OTG_BLACK_COLOR_R_CR_MASK                                                       0x3FF00000L
>+//OTG5_OTG_BLACK_COLOR_EXT
>+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT__SHIFT                                             0x0
>+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT__SHIFT                                              0x8
>+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT__SHIFT                                             0x10
>+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_B_CB_EXT_MASK                                               0x0000003FL
>+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_G_Y_EXT_MASK                                                0x00003F00L
>+#define OTG5_OTG_BLACK_COLOR_EXT__OTG_BLACK_COLOR_R_CR_EXT_MASK                                               0x003F0000L
>+//OTG5_OTG_VERTICAL_INTERRUPT0_POSITION
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
>+//OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
>+#define OTG5_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
>+//OTG5_OTG_VERTICAL_INTERRUPT1_POSITION
>+#define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
>+#define OTG5_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
>+//OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL
>+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
>+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
>+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
>+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
>+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
>+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
>+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
>+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
>+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
>+#define OTG5_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
>+//OTG5_OTG_VERTICAL_INTERRUPT2_POSITION
>+#define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
>+#define OTG5_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
>+//OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL
>+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
>+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
>+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
>+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
>+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
>+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
>+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
>+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
>+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
>+#define OTG5_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
>+//OTG5_OTG_CRC_CNTL
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
>+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
>+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
>+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
>+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
>+#define OTG5_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
>+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
>+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
>+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
>+#define OTG5_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
>+//OTG5_OTG_CRC_CNTL2
>+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
>+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
>+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
>+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
>+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
>+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
>+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
>+#define OTG5_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
>+//OTG5_OTG_CRC0_WINDOWA_X_CONTROL
>+#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
>+#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
>+#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
>+#define OTG5_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
>+//OTG5_OTG_CRC0_WINDOWA_Y_CONTROL
>+#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
>+#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
>+#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
>+#define OTG5_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
>+//OTG5_OTG_CRC0_WINDOWB_X_CONTROL
>+#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
>+#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
>+#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
>+#define OTG5_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
>+//OTG5_OTG_CRC0_WINDOWB_Y_CONTROL
>+#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
>+#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
>+#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
>+#define OTG5_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
>+//OTG5_OTG_CRC0_DATA_RG
>+#define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
>+#define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
>+#define OTG5_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG5_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG5_OTG_CRC0_DATA_B
>+#define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
>+#define OTG5_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
>+#define OTG5_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG5_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
>+//OTG5_OTG_CRC1_WINDOWA_X_CONTROL
>+#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
>+#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
>+#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
>+#define OTG5_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
>+//OTG5_OTG_CRC1_WINDOWA_Y_CONTROL
>+#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
>+#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
>+#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
>+#define OTG5_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
>+//OTG5_OTG_CRC1_WINDOWB_X_CONTROL
>+#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
>+#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
>+#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
>+#define OTG5_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
>+//OTG5_OTG_CRC1_WINDOWB_Y_CONTROL
>+#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
>+#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
>+#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
>+#define OTG5_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
>+//OTG5_OTG_CRC1_DATA_RG
>+#define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
>+#define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
>+#define OTG5_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG5_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG5_OTG_CRC1_DATA_B
>+#define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
>+#define OTG5_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
>+#define OTG5_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG5_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
>+//OTG5_OTG_CRC2_DATA_RG
>+#define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
>+#define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
>+#define OTG5_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG5_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG5_OTG_CRC2_DATA_B
>+#define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
>+#define OTG5_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
>+#define OTG5_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG5_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
>+//OTG5_OTG_CRC3_DATA_RG
>+#define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
>+#define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
>+#define OTG5_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
>+#define OTG5_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
>+//OTG5_OTG_CRC3_DATA_B
>+#define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
>+#define OTG5_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
>+#define OTG5_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
>+#define OTG5_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
>+//OTG5_OTG_CRC_SIG_RED_GREEN_MASK
>+#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
>+#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
>+#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
>+#define OTG5_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
>+//OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK
>+#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
>+#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
>+#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
>+#define OTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
>+//OTG5_OTG_STATIC_SCREEN_CONTROL
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
>+#define OTG5_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
>+//OTG5_OTG_3D_STRUCTURE_CONTROL
>+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
>+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
>+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
>+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
>+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
>+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
>+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
>+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
>+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
>+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
>+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
>+#define OTG5_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
>+//OTG5_OTG_GSL_VSYNC_GAP
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
>+#define OTG5_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
>+//OTG5_OTG_MASTER_UPDATE_MODE
>+#define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
>+#define OTG5_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
>+//OTG5_OTG_CLOCK_CONTROL
>+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
>+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
>+#define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
>+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
>+#define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
>+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
>+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
>+#define OTG5_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
>+#define OTG5_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
>+#define OTG5_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
>+//OTG5_OTG_VSTARTUP_PARAM
>+#define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
>+#define OTG5_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
>+//OTG5_OTG_VUPDATE_PARAM
>+#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
>+#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
>+#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
>+#define OTG5_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
>+//OTG5_OTG_VREADY_PARAM
>+#define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
>+#define OTG5_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
>+//OTG5_OTG_GLOBAL_SYNC_STATUS
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
>+#define OTG5_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
>+//OTG5_OTG_MASTER_UPDATE_LOCK
>+#define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
>+#define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
>+#define OTG5_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
>+#define OTG5_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
>+//OTG5_OTG_GSL_CONTROL
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
>+#define OTG5_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
>+#define OTG5_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
>+#define OTG5_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
>+//OTG5_OTG_GSL_WINDOW_X
>+#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
>+#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
>+#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
>+#define OTG5_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
>+//OTG5_OTG_GSL_WINDOW_Y
>+#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
>+#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
>+#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
>+#define OTG5_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
>+//OTG5_OTG_VUPDATE_KEEPOUT
>+#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
>+#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
>+#define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
>+#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
>+#define OTG5_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
>+#define OTG5_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
>+//OTG5_OTG_GLOBAL_CONTROL0
>+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT__SHIFT                                0x0
>+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN__SHIFT                             0x8
>+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
>+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_MASK                                  0x000000FFL
>+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_HTOTAL_KEEPOUT_EN_MASK                               0x00000100L
>+#define OTG5_OTG_GLOBAL_CONTROL0__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
>+//OTG5_OTG_GLOBAL_CONTROL1
>+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X__SHIFT                                              0x0
>+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y__SHIFT                                              0x10
>+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
>+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_X_MASK                                                0x00007FFFL
>+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_Y_MASK                                                0x7FFF0000L
>+#define OTG5_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
>+//OTG5_OTG_GLOBAL_CONTROL2
>+#define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION__SHIFT                                                  0x0
>+#define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
>+#define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
>+#define OTG5_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL__SHIFT                                        0x1d
>+#define OTG5_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
>+#define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
>+#define OTG5_OTG_GLOBAL_CONTROL2__DIG_UPDATE_LOCATION_MASK                                                    0x000003FFL
>+#define OTG5_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
>+#define OTG5_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
>+#define OTG5_OTG_GLOBAL_CONTROL2__MASTER_UPDATE_LOCK_WINDOW_SEL_MASK                                          0x20000000L
>+#define OTG5_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
>+#define OTG5_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
>+//OTG5_OTG_GLOBAL_CONTROL3
>+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
>+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
>+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL__SHIFT                          0x8
>+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
>+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
>+#define OTG5_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_STEREO_FLAG_SEL_MASK                            0x00000100L
>+//OTG5_OTG_TRIG_MANUAL_CONTROL
>+#define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
>+#define OTG5_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
>+//OTG5_OTG_MANUAL_FLOW_CONTROL
>+#define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
>+#define OTG5_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
>+//OTG5_OTG_RANGE_TIMING_INT_STATUS
>+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                             0x0
>+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT__SHIFT                         0x4
>+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                       0x8
>+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                     0xc
>+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                    0x10
>+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_MASK                               0x00000001L
>+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MASK                           0x00000010L
>+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_CLEAR_MASK                         0x00000100L
>+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                       0x00001000L
>+#define OTG5_OTG_RANGE_TIMING_INT_STATUS__OTG_RANGE_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                      0x00010000L
>+//OTG5_OTG_DRR_CONTROL
>+#define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
>+#define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
>+#define OTG5_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000007L
>+#define OTG5_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
>+//OTG5_OTG_REQUEST_CONTROL
>+#define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
>+#define OTG5_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
>+//OTG5_OTG_DSC_START_POSITION
>+#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
>+#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
>+#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
>+#define OTG5_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
>+//OTG5_OTG_PIPE_UPDATE_STATUS
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN__SHIFT                                                    0x1
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR__SHIFT                                              0x2
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN__SHIFT                                           0x5
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR__SHIFT                                     0x6
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN__SHIFT                                           0x9
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR__SHIFT                                     0xa
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_MASK                                                      0x00000002L
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_TAKEN_CLEAR_MASK                                                0x00000004L
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_MASK                                             0x00000020L
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_TAKEN_CLEAR_MASK                                       0x00000040L
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_MASK                                             0x00000200L
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_TAKEN_CLEAR_MASK                                       0x00000400L
>+#define OTG5_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
>+//OTG5_OTG_SPARE_REGISTER
>+#define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
>+#define OTG5_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_optc_optc_misc_dispdec
>+//DWB_SOURCE_SELECT
>+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT                                                     0x0
>+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT                                                     0x3
>+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT__SHIFT                                                     0x6
>+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK                                                       0x00000007L
>+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK                                                       0x00000038L
>+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT_MASK                                                       0x000001C0L
>+//GSL_SOURCE_SELECT
>+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT                                                       0x0
>+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT                                                       0x4
>+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT                                                       0x8
>+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT                                                         0x10
>+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK                                                         0x00000007L
>+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK                                                         0x00000070L
>+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK                                                         0x00000700L
>+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK                                                           0x00070000L
>+//OPTC_CLOCK_CONTROL
>+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
>+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT                                                    0x1
>+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT                                                          0x8
>+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
>+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK                                                      0x00000002L
>+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK                                                            0x00000F00L
>+//ODM_MEM_PWR_CTRL
>+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT                                                           0x0
>+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT                                                             0x2
>+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT                                                           0x4
>+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT                                                             0x6
>+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT                                                           0x8
>+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT                                                             0xa
>+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT                                                           0xc
>+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT                                                             0xe
>+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT                                                           0x10
>+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT                                                             0x12
>+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT                                                           0x14
>+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT                                                             0x16
>+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT                                                           0x18
>+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT                                                             0x1a
>+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT                                                           0x1c
>+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT                                                             0x1e
>+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK                                                             0x00000003L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK                                                               0x00000004L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK                                                             0x00000030L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK                                                               0x00000040L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK                                                             0x00000300L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK                                                               0x00000400L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK                                                             0x00003000L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK                                                               0x00004000L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK                                                             0x00030000L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK                                                               0x00040000L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK                                                             0x00300000L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK                                                               0x00400000L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK                                                             0x03000000L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK                                                               0x04000000L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK                                                             0x30000000L
>+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK                                                               0x40000000L
>+//ODM_MEM_PWR_CTRL2
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE__SHIFT                                                          0x0
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS__SHIFT                                                            0x2
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE__SHIFT                                                          0x4
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS__SHIFT                                                            0x6
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE__SHIFT                                                         0x8
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS__SHIFT                                                           0xa
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE__SHIFT                                                         0xc
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS__SHIFT                                                           0xe
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_FORCE_MASK                                                            0x00000003L
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM8_PWR_DIS_MASK                                                              0x00000004L
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_FORCE_MASK                                                            0x00000030L
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM9_PWR_DIS_MASK                                                              0x00000040L
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_FORCE_MASK                                                           0x00000300L
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM10_PWR_DIS_MASK                                                             0x00000400L
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_FORCE_MASK                                                           0x00003000L
>+#define ODM_MEM_PWR_CTRL2__ODM_MEM11_PWR_DIS_MASK                                                             0x00004000L
>+//ODM_MEM_PWR_CTRL3
>+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT                                                 0x0
>+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT                                                     0x2
>+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK                                                   0x00000003L
>+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK                                                       0x0000000CL
>+//ODM_MEM_PWR_STATUS
>+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT                                                         0x0
>+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT                                                         0x2
>+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT                                                         0x4
>+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT                                                         0x6
>+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT                                                         0x8
>+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT                                                         0xa
>+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT                                                         0xc
>+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT                                                         0xe
>+#define ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE__SHIFT                                                         0x10
>+#define ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE__SHIFT                                                         0x12
>+#define ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE__SHIFT                                                        0x14
>+#define ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE__SHIFT                                                        0x16
>+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK                                                           0x00000003L
>+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL
>+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK                                                           0x00000030L
>+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK                                                           0x000000C0L
>+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK                                                           0x00000300L
>+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK                                                           0x00000C00L
>+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK                                                           0x00003000L
>+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK                                                           0x0000C000L
>+#define ODM_MEM_PWR_STATUS__ODM_MEM8_PWR_STATE_MASK                                                           0x00030000L
>+#define ODM_MEM_PWR_STATUS__ODM_MEM9_PWR_STATE_MASK                                                           0x000C0000L
>+#define ODM_MEM_PWR_STATUS__ODM_MEM10_PWR_STATE_MASK                                                          0x00300000L
>+#define ODM_MEM_PWR_STATUS__ODM_MEM11_PWR_STATE_MASK                                                          0x00C00000L
>+//OPTC_MISC_SPARE_REGISTER
>+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT                                                  0x0
>+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK                                                    0x000000FFL
>+
>+
>+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON17_PERFCOUNTER_CNTL
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON17_PERFCOUNTER_CNTL2
>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON17_PERFCOUNTER_STATE
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON17_PERFMON_CNTL
>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON17_PERFMON_CNTL2
>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON17_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON17_PERFMON_CVALUE_LOW
>+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON17_PERFMON_HI
>+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON17_PERFMON_LOW
>+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dio_dout_i2c_dispdec
>+//DC_I2C_CONTROL
>+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT                                                                      0x0
>+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT                                                              0x1
>+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT                                                              0x2
>+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT                                                         0x3
>+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT                                                              0x8
>+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT                                                       0x14
>+#define DC_I2C_CONTROL__DC_I2C_GO_MASK                                                                        0x00000001L
>+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK                                                                0x00000002L
>+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK                                                                0x00000004L
>+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK                                                           0x00000008L
>+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK                                                                0x00000700L
>+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK                                                         0x00300000L
>+//DC_I2C_ARBITRATION
>+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT                                                         0x0
>+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT                                                  0x2
>+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT                                                     0x4
>+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT                                                       0x8
>+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT                                                       0xc
>+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT                                                  0x14
>+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT                                               0x15
>+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT                                                0x18
>+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT                                             0x19
>+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK                                                           0x00000003L
>+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK                                                    0x0000000CL
>+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK                                                       0x00000010L
>+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK                                                         0x00000100L
>+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK                                                         0x00001000L
>+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK                                                    0x00100000L
>+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK                                                 0x00200000L
>+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK                                                  0x01000000L
>+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK                                               0x02000000L
>+//DC_I2C_INTERRUPT_CONTROL
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT                                                   0x0
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT                                                   0x1
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT                                                  0x2
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT                                              0x4
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT                                              0x5
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT                                             0x6
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT                                              0x8
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT                                              0x9
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT                                             0xa
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT                                              0xc
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT                                              0xd
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT                                             0xe
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT                                              0x10
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT                                              0x11
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT                                             0x12
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT                                              0x14
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT                                              0x15
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT                                             0x16
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT                                              0x18
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT                                              0x19
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT                                             0x1a
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT                                            0x1b
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT                                            0x1c
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT                                           0x1d
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK                                                     0x00000001L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK                                                     0x00000002L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK                                                    0x00000004L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK                                                0x00000010L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK                                                0x00000020L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK                                               0x00000040L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK                                                0x00000100L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK                                                0x00000200L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK                                               0x00000400L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK                                                0x00001000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK                                                0x00002000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK                                               0x00004000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK                                                0x00010000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK                                                0x00020000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK                                               0x00040000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK                                                0x00100000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK                                                0x00200000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK                                               0x00400000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK                                                0x01000000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK                                                0x02000000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK                                               0x04000000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK                                              0x08000000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK                                              0x10000000L
>+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK                                             0x20000000L
>+//DC_I2C_SW_STATUS
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT                                                             0x0
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT                                                               0x2
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT                                                            0x4
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT                                                            0x5
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT                                                        0x6
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT                                                    0x7
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT                                                    0x8
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT                                                              0xc
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT                                                              0xd
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT                                                              0xe
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT                                                              0xf
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT                                                                0x12
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK                                                               0x00000003L
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK                                                                 0x00000004L
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK                                                              0x00000010L
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK                                                              0x00000020L
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK                                                          0x00000040L
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK                                                      0x00000080L
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK                                                      0x00000100L
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK                                                                0x00001000L
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK                                                                0x00002000L
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK                                                                0x00004000L
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK                                                                0x00008000L
>+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK                                                                  0x00040000L
>+//DC_I2C_DDC1_HW_STATUS
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT                                                   0x0
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT                                                     0x3
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT                                                      0x10
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT                                                      0x11
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT                                          0x14
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT                                           0x1c
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK                                                     0x00000003L
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK                                                       0x00000008L
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK                                                        0x00010000L
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK                                                        0x00020000L
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK                                            0x00100000L
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
>+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK                                             0x70000000L
>+//DC_I2C_DDC2_HW_STATUS
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT                                                   0x0
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT                                                     0x3
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT                                                      0x10
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT                                                      0x11
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT                                          0x14
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT                                           0x1c
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK                                                     0x00000003L
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK                                                       0x00000008L
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK                                                        0x00010000L
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK                                                        0x00020000L
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK                                            0x00100000L
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
>+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK                                             0x70000000L
>+//DC_I2C_DDC3_HW_STATUS
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT                                                   0x0
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT                                                     0x3
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT                                                      0x10
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT                                                      0x11
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT                                          0x14
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT                                           0x1c
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK                                                     0x00000003L
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK                                                       0x00000008L
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK                                                        0x00010000L
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK                                                        0x00020000L
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK                                            0x00100000L
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
>+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK                                             0x70000000L
>+//DC_I2C_DDC4_HW_STATUS
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT                                                   0x0
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT                                                     0x3
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT                                                      0x10
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT                                                      0x11
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT                                          0x14
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT                                           0x1c
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK                                                     0x00000003L
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK                                                       0x00000008L
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK                                                        0x00010000L
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK                                                        0x00020000L
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK                                            0x00100000L
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
>+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK                                             0x70000000L
>+//DC_I2C_DDC5_HW_STATUS
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT                                                   0x0
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT                                                     0x3
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT                                                      0x10
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT                                                      0x11
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT                                          0x14
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT                                           0x1c
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK                                                     0x00000003L
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK                                                       0x00000008L
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK                                                        0x00010000L
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK                                                        0x00020000L
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK                                            0x00100000L
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
>+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK                                             0x70000000L
>+//DC_I2C_DDC1_SPEED
>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT                                                       0x0
>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT                                          0x8
>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT                                                        0x10
>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK                                                         0x00000003L
>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
>+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK                                                          0xFFFF0000L
>+//DC_I2C_DDC1_SETUP
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT                                                   0x0
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT                                                  0x1
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT                                               0x2
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT                                              0x4
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT                                                0x5
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT                                                          0x6
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT                                                    0x7
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT                                                0x8
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT                                                      0x18
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK                                                     0x00000001L
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK                                                    0x00000002L
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK                                                 0x00000004L
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK                                                0x00000010L
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK                                                  0x00000020L
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK                                                            0x00000040L
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK                                                      0x00000080L
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
>+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK                                                        0xFF000000L
>+//DC_I2C_DDC2_SPEED
>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT                                                       0x0
>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT                                          0x8
>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT                                                        0x10
>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK                                                         0x00000003L
>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
>+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK                                                          0xFFFF0000L
>+//DC_I2C_DDC2_SETUP
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT                                                   0x0
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT                                                  0x1
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT                                               0x2
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT                                              0x4
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT                                                0x5
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT                                                          0x6
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT                                                    0x7
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT                                                0x8
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT                                                      0x18
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK                                                     0x00000001L
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK                                                    0x00000002L
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK                                                 0x00000004L
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK                                                0x00000010L
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK                                                  0x00000020L
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK                                                            0x00000040L
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK                                                      0x00000080L
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
>+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK                                                        0xFF000000L
>+//DC_I2C_DDC3_SPEED
>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT                                                       0x0
>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT                                          0x8
>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT                                                        0x10
>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK                                                         0x00000003L
>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
>+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK                                                          0xFFFF0000L
>+//DC_I2C_DDC3_SETUP
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT                                                   0x0
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT                                                  0x1
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT                                               0x2
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT                                              0x4
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT                                                0x5
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT                                                          0x6
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT                                                    0x7
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT                                                0x8
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT                                                      0x18
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK                                                     0x00000001L
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK                                                    0x00000002L
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK                                                 0x00000004L
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK                                                0x00000010L
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK                                                  0x00000020L
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK                                                            0x00000040L
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK                                                      0x00000080L
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
>+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK                                                        0xFF000000L
>+//DC_I2C_DDC4_SPEED
>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT                                                       0x0
>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT                                          0x8
>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT                                                        0x10
>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK                                                         0x00000003L
>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
>+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK                                                          0xFFFF0000L
>+//DC_I2C_DDC4_SETUP
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT                                                   0x0
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT                                                  0x1
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT                                               0x2
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT                                              0x4
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT                                                0x5
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT                                                          0x6
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT                                                    0x7
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT                                                0x8
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT                                                      0x18
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK                                                     0x00000001L
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK                                                    0x00000002L
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK                                                 0x00000004L
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK                                                0x00000010L
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK                                                  0x00000020L
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK                                                            0x00000040L
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK                                                      0x00000080L
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
>+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK                                                        0xFF000000L
>+//DC_I2C_DDC5_SPEED
>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT                                                       0x0
>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT                                          0x8
>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT                                                        0x10
>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK                                                         0x00000003L
>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
>+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK                                                          0xFFFF0000L
>+//DC_I2C_DDC5_SETUP
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT                                                   0x0
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT                                                  0x1
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT                                               0x2
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT                                              0x4
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT                                                0x5
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT                                                          0x6
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT                                                    0x7
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT                                                0x8
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT                                                      0x18
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK                                                     0x00000001L
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK                                                    0x00000002L
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK                                                 0x00000004L
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK                                                0x00000010L
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK                                                  0x00000020L
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK                                                            0x00000040L
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK                                                      0x00000080L
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
>+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK                                                        0xFF000000L
>+//DC_I2C_TRANSACTION0
>+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT                                                                0x0
>+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT                                                      0x8
>+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT                                                             0xc
>+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT                                                              0xd
>+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT                                                             0x10
>+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK                                                                  0x00000001L
>+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK                                                        0x00000100L
>+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK                                                               0x00001000L
>+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK                                                                0x00002000L
>+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK                                                               0x03FF0000L
>+//DC_I2C_TRANSACTION1
>+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT                                                                0x0
>+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT                                                      0x8
>+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT                                                             0xc
>+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT                                                              0xd
>+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT                                                             0x10
>+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK                                                                  0x00000001L
>+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK                                                        0x00000100L
>+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK                                                               0x00001000L
>+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK                                                                0x00002000L
>+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK                                                               0x03FF0000L
>+//DC_I2C_TRANSACTION2
>+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT                                                                0x0
>+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT                                                      0x8
>+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT                                                             0xc
>+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT                                                              0xd
>+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT                                                             0x10
>+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK                                                                  0x00000001L
>+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK                                                        0x00000100L
>+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK                                                               0x00001000L
>+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK                                                                0x00002000L
>+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK                                                               0x03FF0000L
>+//DC_I2C_TRANSACTION3
>+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT                                                                0x0
>+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT                                                      0x8
>+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT                                                             0xc
>+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT                                                              0xd
>+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT                                                             0x10
>+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK                                                                  0x00000001L
>+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK                                                        0x00000100L
>+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK                                                               0x00001000L
>+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK                                                                0x00002000L
>+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK                                                               0x03FF0000L
>+//DC_I2C_DATA
>+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT                                                                    0x0
>+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT                                                                       0x8
>+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT                                                                      0x10
>+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT                                                                0x1f
>+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK                                                                      0x00000001L
>+#define DC_I2C_DATA__DC_I2C_DATA_MASK                                                                         0x0000FF00L
>+#define DC_I2C_DATA__DC_I2C_INDEX_MASK                                                                        0x03FF0000L
>+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK                                                                  0x80000000L
>+//DC_I2C_EDID_DETECT_CTRL
>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT                                          0x0
>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT                              0x14
>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT                                         0x1c
>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK                                            0x0000FFFFL
>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK                                0x00F00000L
>+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK                                           0x10000000L
>+//DC_I2C_READ_REQUEST_INTERRUPT
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT                               0x0
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT                                    0x1
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT                                    0x2
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT                                   0x3
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT                               0x4
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT                                    0x5
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT                                    0x6
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT                                   0x7
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT                               0x8
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT                                    0x9
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT                                    0xa
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT                                   0xb
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT                               0xc
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT                                    0xd
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT                                    0xe
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT                                   0xf
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT                               0x10
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT                                    0x11
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT                                    0x12
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT                                   0x13
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT                               0x14
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT                                    0x15
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT                                    0x16
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT                                   0x17
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT                             0x18
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT                                  0x19
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT                                  0x1a
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT                                 0x1b
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT                              0x1e
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT                                0x1f
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK                                 0x00000001L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK                                      0x00000002L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK                                      0x00000004L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK                                     0x00000008L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK                                 0x00000010L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK                                      0x00000020L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK                                      0x00000040L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK                                     0x00000080L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK                                 0x00000100L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK                                      0x00000200L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK                                      0x00000400L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK                                     0x00000800L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK                                 0x00001000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK                                      0x00002000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK                                      0x00004000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK                                     0x00008000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK                                 0x00010000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK                                      0x00020000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK                                      0x00040000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK                                     0x00080000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK                                 0x00100000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK                                      0x00200000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK                                      0x00400000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK                                     0x00800000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK                               0x01000000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK                                    0x02000000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK                                    0x04000000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK                                   0x08000000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK                                0x40000000L
>+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK                                  0x80000000L
>+
>+
>+//DIG_SOFT_RESET
>+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT                                                             0x0
>+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT                                                             0x1
>+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT                                                             0x4
>+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT                                                             0x5
>+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT                                                             0x8
>+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT                                                             0x9
>+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT                                                             0xc
>+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT                                                             0xd
>+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT                                                             0x10
>+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT                                                             0x11
>+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT                                                             0x14
>+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT                                                             0x15
>+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT                                                             0x18
>+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT                                                             0x19
>+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK                                                               0x00000001L
>+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK                                                               0x00000002L
>+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK                                                               0x00000010L
>+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK                                                               0x00000020L
>+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK                                                               0x00000100L
>+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK                                                               0x00000200L
>+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK                                                               0x00001000L
>+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK                                                               0x00002000L
>+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK                                                               0x00010000L
>+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK                                                               0x00020000L
>+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK                                                               0x00100000L
>+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK                                                               0x00200000L
>+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK                                                               0x01000000L
>+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK                                                               0x02000000L
>+//DIO_MEM_PWR_STATUS1
>+#define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE__SHIFT                                                       0x0
>+#define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE__SHIFT                                                       0x2
>+#define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE__SHIFT                                                       0x4
>+#define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE__SHIFT                                                       0x6
>+#define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE__SHIFT                                                       0x8
>+#define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE__SHIFT                                                       0xa
>+#define DIO_MEM_PWR_STATUS1__DME0_MEM_PWR_STATE__SHIFT                                                        0x10
>+#define DIO_MEM_PWR_STATUS1__DME1_MEM_PWR_STATE__SHIFT                                                        0x12
>+#define DIO_MEM_PWR_STATUS1__DME2_MEM_PWR_STATE__SHIFT                                                        0x14
>+#define DIO_MEM_PWR_STATUS1__DME3_MEM_PWR_STATE__SHIFT                                                        0x16
>+#define DIO_MEM_PWR_STATUS1__DME4_MEM_PWR_STATE__SHIFT                                                        0x18
>+#define DIO_MEM_PWR_STATUS1__DME5_MEM_PWR_STATE__SHIFT                                                        0x1a
>+#define DIO_MEM_PWR_STATUS1__AFMT0_MEM_PWR_STATE_MASK                                                         0x00000001L
>+#define DIO_MEM_PWR_STATUS1__AFMT1_MEM_PWR_STATE_MASK                                                         0x00000004L
>+#define DIO_MEM_PWR_STATUS1__AFMT2_MEM_PWR_STATE_MASK                                                         0x00000010L
>+#define DIO_MEM_PWR_STATUS1__AFMT3_MEM_PWR_STATE_MASK                                                         0x00000040L
>+#define DIO_MEM_PWR_STATUS1__AFMT4_MEM_PWR_STATE_MASK                                                         0x00000100L
>+#define DIO_MEM_PWR_STATUS1__AFMT5_MEM_PWR_STATE_MASK                                                         0x00000400L
>+#define DIO_MEM_PWR_STATUS1__DME0_MEM_PWR_STATE_MASK                                                          0x00030000L
>+#define DIO_MEM_PWR_STATUS1__DME1_MEM_PWR_STATE_MASK                                                          0x000C0000L
>+#define DIO_MEM_PWR_STATUS1__DME2_MEM_PWR_STATE_MASK                                                          0x00300000L
>+#define DIO_MEM_PWR_STATUS1__DME3_MEM_PWR_STATE_MASK                                                          0x00C00000L
>+#define DIO_MEM_PWR_STATUS1__DME4_MEM_PWR_STATE_MASK                                                          0x03000000L
>+#define DIO_MEM_PWR_STATUS1__DME5_MEM_PWR_STATE_MASK                                                          0x0C000000L
>+//DIO_CLK_CNTL2
>+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT                                                                0x0
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT                                                         0x7
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT                                                         0x8
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT                                                         0x9
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT                                                         0xa
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT                                                         0xb
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT                                                         0xc
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT                                                         0xd
>+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x11
>+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x12
>+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x13
>+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x14
>+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x15
>+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x16
>+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x17
>+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK                                                                  0x0000007FL
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK                                                           0x00000080L
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK                                                           0x00000100L
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK                                                           0x00000200L
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK                                                           0x00000400L
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK                                                           0x00000800L
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK                                                           0x00001000L
>+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK                                                           0x00002000L
>+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK                                                        0x00020000L
>+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK                                                        0x00040000L
>+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK                                                        0x00080000L
>+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK                                                        0x00100000L
>+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK                                                        0x00200000L
>+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK                                                        0x00400000L
>+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK                                                        0x00800000L
>+//DIO_CLK_CNTL3
>+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x0
>+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x1
>+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x2
>+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x3
>+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x4
>+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x5
>+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x6
>+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT                                                         0xa
>+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT                                                         0xb
>+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT                                                         0xc
>+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT                                                         0xd
>+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT                                                         0xe
>+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT                                                         0xf
>+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT                                                         0x10
>+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000001L
>+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000002L
>+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000004L
>+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000008L
>+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000010L
>+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000020L
>+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000040L
>+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK                                                           0x00000400L
>+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK                                                           0x00000800L
>+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK                                                           0x00001000L
>+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK                                                           0x00002000L
>+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK                                                           0x00004000L
>+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK                                                           0x00008000L
>+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK                                                           0x00010000L
>+//DIO_HDMI_RXSTATUS_TIMER_CONTROL
>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT                                0x0
>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT                                  0x4
>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT                                0x8
>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT                                  0xc
>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT                              0x10
>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK                                  0x00000001L
>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK                                    0x00000010L
>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK                                  0x00000100L
>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK                                    0x00001000L
>+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK                                0x0FFF0000L
>+//DIO_PSP_INTERRUPT_STATUS
>+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT                                             0x0
>+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT                                            0x1
>+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK                                               0x00000001L
>+#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK                                              0xFFFFFFFEL
>+//DIO_PSP_INTERRUPT_CLEAR
>+#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT                                               0x0
>+#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK                                                 0x00000001L
>+//DIO_GENERIC_INTERRUPT_MESSAGE
>+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT                                    0x0
>+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT                                   0x1
>+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK                                      0x00000001L
>+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK                                     0xFFFFFFFEL
>+//DIO_GENERIC_INTERRUPT_CLEAR
>+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT                                       0x0
>+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK                                         0x00000001L
>+
>+
>+// addressBlock: dce_dc_dio_hpd0_dispdec
>+//HPD0_DC_HPD_INT_STATUS
>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
>+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
>+//HPD0_DC_HPD_INT_CONTROL
>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
>+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
>+//HPD0_DC_HPD_CONTROL
>+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
>+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
>+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
>+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
>+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
>+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
>+//HPD0_DC_HPD_FAST_TRAIN_CNTL
>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
>+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
>+//HPD0_DC_HPD_TOGGLE_FILT_CNTL
>+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
>+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
>+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
>+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
>+
>+
>+// addressBlock: dce_dc_dio_hpd1_dispdec
>+//HPD1_DC_HPD_INT_STATUS
>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
>+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
>+//HPD1_DC_HPD_INT_CONTROL
>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
>+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
>+//HPD1_DC_HPD_CONTROL
>+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
>+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
>+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
>+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
>+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
>+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
>+//HPD1_DC_HPD_FAST_TRAIN_CNTL
>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
>+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
>+//HPD1_DC_HPD_TOGGLE_FILT_CNTL
>+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
>+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
>+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
>+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
>+
>+
>+// addressBlock: dce_dc_dio_hpd2_dispdec
>+//HPD2_DC_HPD_INT_STATUS
>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
>+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
>+//HPD2_DC_HPD_INT_CONTROL
>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
>+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
>+//HPD2_DC_HPD_CONTROL
>+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
>+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
>+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
>+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
>+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
>+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
>+//HPD2_DC_HPD_FAST_TRAIN_CNTL
>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
>+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
>+//HPD2_DC_HPD_TOGGLE_FILT_CNTL
>+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
>+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
>+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
>+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
>+
>+
>+// addressBlock: dce_dc_dio_hpd3_dispdec
>+//HPD3_DC_HPD_INT_STATUS
>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
>+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
>+//HPD3_DC_HPD_INT_CONTROL
>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
>+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
>+//HPD3_DC_HPD_CONTROL
>+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
>+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
>+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
>+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
>+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
>+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
>+//HPD3_DC_HPD_FAST_TRAIN_CNTL
>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
>+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
>+//HPD3_DC_HPD_TOGGLE_FILT_CNTL
>+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
>+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
>+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
>+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
>+
>+
>+// addressBlock: dce_dc_dio_hpd4_dispdec
>+//HPD4_DC_HPD_INT_STATUS
>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
>+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
>+//HPD4_DC_HPD_INT_CONTROL
>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
>+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
>+//HPD4_DC_HPD_CONTROL
>+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
>+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
>+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
>+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
>+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
>+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
>+//HPD4_DC_HPD_FAST_TRAIN_CNTL
>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
>+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
>+//HPD4_DC_HPD_TOGGLE_FILT_CNTL
>+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
>+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
>+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
>+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
>+
>+
>+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON18_PERFCOUNTER_CNTL
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON18_PERFCOUNTER_CNTL2
>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON18_PERFCOUNTER_STATE
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON18_PERFMON_CNTL
>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON18_PERFMON_CNTL2
>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON18_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON18_PERFMON_CVALUE_LOW
>+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON18_PERFMON_HI
>+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON18_PERFMON_LOW
>+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dio_dp_aux0_dispdec
>+//DP_AUX0_AUX_CONTROL
>+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
>+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
>+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
>+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
>+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
>+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
>+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
>+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
>+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
>+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
>+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
>+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
>+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
>+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
>+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
>+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
>+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
>+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
>+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
>+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
>+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
>+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
>+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
>+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
>+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
>+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
>+//DP_AUX0_AUX_SW_CONTROL
>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
>+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
>+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
>+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
>+//DP_AUX0_AUX_ARB_CONTROL
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
>+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
>+//DP_AUX0_AUX_INTERRUPT_CONTROL
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
>+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
>+//DP_AUX0_AUX_SW_STATUS
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
>+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
>+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
>+//DP_AUX0_AUX_LS_STATUS
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
>+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
>+//DP_AUX0_AUX_SW_DATA
>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
>+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
>+//DP_AUX0_AUX_LS_DATA
>+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
>+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
>+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
>+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
>+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
>+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
>+//DP_AUX0_AUX_DPHY_TX_CONTROL
>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
>+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
>+//DP_AUX0_AUX_DPHY_RX_CONTROL0
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
>+//DP_AUX0_AUX_DPHY_RX_CONTROL1
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
>+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
>+//DP_AUX0_AUX_DPHY_TX_STATUS
>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
>+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
>+//DP_AUX0_AUX_DPHY_RX_STATUS
>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
>+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
>+//DP_AUX0_AUX_GTC_SYNC_CONTROL
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
>+//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
>+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
>+//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
>+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
>+//DP_AUX0_AUX_GTC_SYNC_STATUS
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
>+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
>+//DP_AUX0_AUX_PHY_WAKE_CNTL
>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
>+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
>+
>+
>+// addressBlock: dce_dc_dio_dp_aux1_dispdec
>+//DP_AUX1_AUX_CONTROL
>+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
>+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
>+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
>+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
>+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
>+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
>+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
>+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
>+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
>+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
>+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
>+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
>+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
>+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
>+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
>+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
>+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
>+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
>+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
>+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
>+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
>+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
>+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
>+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
>+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
>+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
>+//DP_AUX1_AUX_SW_CONTROL
>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
>+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
>+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
>+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
>+//DP_AUX1_AUX_ARB_CONTROL
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
>+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
>+//DP_AUX1_AUX_INTERRUPT_CONTROL
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
>+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
>+//DP_AUX1_AUX_SW_STATUS
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
>+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
>+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
>+//DP_AUX1_AUX_LS_STATUS
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
>+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
>+//DP_AUX1_AUX_SW_DATA
>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
>+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
>+//DP_AUX1_AUX_LS_DATA
>+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
>+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
>+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
>+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
>+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
>+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
>+//DP_AUX1_AUX_DPHY_TX_CONTROL
>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
>+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
>+//DP_AUX1_AUX_DPHY_RX_CONTROL0
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
>+//DP_AUX1_AUX_DPHY_RX_CONTROL1
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
>+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
>+//DP_AUX1_AUX_DPHY_TX_STATUS
>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
>+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
>+//DP_AUX1_AUX_DPHY_RX_STATUS
>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
>+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
>+//DP_AUX1_AUX_GTC_SYNC_CONTROL
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
>+//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
>+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
>+//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
>+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
>+//DP_AUX1_AUX_GTC_SYNC_STATUS
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
>+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
>+//DP_AUX1_AUX_PHY_WAKE_CNTL
>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
>+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
>+
>+
>+// addressBlock: dce_dc_dio_dp_aux2_dispdec
>+//DP_AUX2_AUX_CONTROL
>+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
>+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
>+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
>+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
>+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
>+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
>+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
>+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
>+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
>+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
>+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
>+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
>+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
>+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
>+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
>+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
>+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
>+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
>+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
>+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
>+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
>+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
>+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
>+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
>+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
>+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
>+//DP_AUX2_AUX_SW_CONTROL
>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
>+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
>+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
>+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
>+//DP_AUX2_AUX_ARB_CONTROL
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
>+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
>+//DP_AUX2_AUX_INTERRUPT_CONTROL
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
>+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
>+//DP_AUX2_AUX_SW_STATUS
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
>+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
>+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
>+//DP_AUX2_AUX_LS_STATUS
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
>+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
>+//DP_AUX2_AUX_SW_DATA
>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
>+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
>+//DP_AUX2_AUX_LS_DATA
>+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
>+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
>+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
>+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
>+//DP_AUX2_AUX_DPHY_TX_REF_CONTROL
>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
>+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
>+//DP_AUX2_AUX_DPHY_TX_CONTROL
>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
>+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
>+//DP_AUX2_AUX_DPHY_RX_CONTROL0
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
>+//DP_AUX2_AUX_DPHY_RX_CONTROL1
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
>+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
>+//DP_AUX2_AUX_DPHY_TX_STATUS
>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
>+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
>+//DP_AUX2_AUX_DPHY_RX_STATUS
>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
>+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
>+//DP_AUX2_AUX_GTC_SYNC_CONTROL
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
>+//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL
>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
>+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
>+//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
>+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
>+//DP_AUX2_AUX_GTC_SYNC_STATUS
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
>+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
>+//DP_AUX2_AUX_PHY_WAKE_CNTL
>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
>+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
>+
>+
>+// addressBlock: dce_dc_dio_dp_aux3_dispdec
>+//DP_AUX3_AUX_CONTROL
>+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
>+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
>+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
>+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
>+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
>+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
>+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
>+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
>+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
>+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
>+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
>+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
>+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
>+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
>+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
>+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
>+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
>+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
>+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
>+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
>+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
>+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
>+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
>+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
>+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
>+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
>+//DP_AUX3_AUX_SW_CONTROL
>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
>+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
>+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
>+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
>+//DP_AUX3_AUX_ARB_CONTROL
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
>+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
>+//DP_AUX3_AUX_INTERRUPT_CONTROL
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
>+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
>+//DP_AUX3_AUX_SW_STATUS
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
>+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
>+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
>+//DP_AUX3_AUX_LS_STATUS
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
>+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
>+//DP_AUX3_AUX_SW_DATA
>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
>+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
>+//DP_AUX3_AUX_LS_DATA
>+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
>+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
>+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
>+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
>+//DP_AUX3_AUX_DPHY_TX_REF_CONTROL
>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
>+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
>+//DP_AUX3_AUX_DPHY_TX_CONTROL
>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
>+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
>+//DP_AUX3_AUX_DPHY_RX_CONTROL0
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
>+//DP_AUX3_AUX_DPHY_RX_CONTROL1
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
>+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
>+//DP_AUX3_AUX_DPHY_TX_STATUS
>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
>+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
>+//DP_AUX3_AUX_DPHY_RX_STATUS
>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
>+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
>+//DP_AUX3_AUX_GTC_SYNC_CONTROL
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
>+//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL
>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
>+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
>+//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
>+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
>+//DP_AUX3_AUX_GTC_SYNC_STATUS
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
>+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
>+//DP_AUX3_AUX_PHY_WAKE_CNTL
>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
>+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
>+
>+
>+// addressBlock: dce_dc_dio_dp_aux4_dispdec
>+//DP_AUX4_AUX_CONTROL
>+#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
>+#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
>+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
>+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
>+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
>+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
>+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
>+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
>+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
>+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
>+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
>+#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
>+#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
>+#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
>+#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
>+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
>+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
>+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
>+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
>+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
>+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
>+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
>+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
>+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
>+#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
>+#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
>+//DP_AUX4_AUX_SW_CONTROL
>+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
>+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
>+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
>+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
>+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
>+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
>+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
>+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
>+//DP_AUX4_AUX_ARB_CONTROL
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
>+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
>+//DP_AUX4_AUX_INTERRUPT_CONTROL
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
>+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
>+//DP_AUX4_AUX_SW_STATUS
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
>+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
>+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
>+//DP_AUX4_AUX_LS_STATUS
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
>+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
>+//DP_AUX4_AUX_SW_DATA
>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
>+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
>+//DP_AUX4_AUX_LS_DATA
>+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
>+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
>+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
>+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
>+//DP_AUX4_AUX_DPHY_TX_REF_CONTROL
>+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
>+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
>+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
>+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
>+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
>+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
>+//DP_AUX4_AUX_DPHY_TX_CONTROL
>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
>+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
>+//DP_AUX4_AUX_DPHY_RX_CONTROL0
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
>+//DP_AUX4_AUX_DPHY_RX_CONTROL1
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
>+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
>+//DP_AUX4_AUX_DPHY_TX_STATUS
>+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
>+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
>+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
>+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
>+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
>+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
>+//DP_AUX4_AUX_DPHY_RX_STATUS
>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
>+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
>+//DP_AUX4_AUX_GTC_SYNC_CONTROL
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
>+//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL
>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
>+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
>+//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
>+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
>+//DP_AUX4_AUX_GTC_SYNC_STATUS
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
>+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
>+//DP_AUX4_AUX_PHY_WAKE_CNTL
>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
>+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
>+
>+
>+// addressBlock: dce_dc_dio_dig0_dispdec
>+//DIG0_DIG_FE_CNTL
>+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
>+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
>+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
>+#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
>+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
>+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
>+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
>+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
>+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
>+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
>+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
>+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
>+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
>+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
>+#define DIG0_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
>+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
>+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
>+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
>+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
>+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
>+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
>+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
>+//DIG0_DIG_OUTPUT_CRC_CNTL
>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
>+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
>+//DIG0_DIG_OUTPUT_CRC_RESULT
>+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
>+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
>+//DIG0_DIG_CLOCK_PATTERN
>+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
>+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
>+//DIG0_DIG_TEST_PATTERN
>+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
>+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
>+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
>+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
>+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
>+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
>+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
>+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
>+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
>+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
>+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
>+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
>+//DIG0_DIG_RANDOM_PATTERN_SEED
>+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
>+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
>+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
>+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
>+//DIG0_DIG_FIFO_STATUS
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
>+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
>+//DIG0_HDMI_METADATA_PACKET_CONTROL
>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
>+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
>+//DIG0_HDMI_GENERIC_PACKET_CONTROL4
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
>+//DIG0_HDMI_CONTROL
>+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
>+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
>+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
>+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
>+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
>+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
>+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
>+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
>+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
>+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
>+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
>+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
>+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
>+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
>+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
>+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
>+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
>+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
>+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
>+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
>+//DIG0_HDMI_STATUS
>+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
>+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
>+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
>+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
>+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
>+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
>+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
>+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
>+//DIG0_HDMI_AUDIO_PACKET_CONTROL
>+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
>+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                    0x8
>+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                    0x10
>+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
>+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                      0x00000100L
>+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK                                      0x001F0000L
>+//DIG0_HDMI_ACR_PACKET_CONTROL
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
>+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
>+//DIG0_HDMI_VBI_PACKET_CONTROL
>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
>+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
>+//DIG0_HDMI_INFOFRAME_CONTROL0
>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
>+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
>+//DIG0_HDMI_INFOFRAME_CONTROL1
>+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
>+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
>+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
>+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
>+//DIG0_HDMI_GENERIC_PACKET_CONTROL0
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
>+//DIG0_HDMI_GC
>+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
>+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
>+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
>+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
>+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
>+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
>+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
>+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
>+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
>+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
>+//DIG0_AFMT_AUDIO_PACKET_CONTROL2
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                        0x0
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                      0x1
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                     0x8
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                       0x10
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                          0x18
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                           0x1c
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                          0x00000001L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                        0x00000002L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                       0x0000FF00L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                         0x00FF0000L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                            0x01000000L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                             0x10000000L
>+//DIG0_AFMT_ISRC1_0
>+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT                                                            0x0
>+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT                                                          0x6
>+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT                                                             0x7
>+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK                                                              0x00000007L
>+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK                                                            0x00000040L
>+#define DIG0_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK                                                               0x00000080L
>+//DIG0_AFMT_ISRC1_1
>+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT                                                          0x0
>+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT                                                          0x8
>+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT                                                          0x10
>+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT                                                          0x18
>+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK                                                            0x000000FFL
>+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK                                                            0x0000FF00L
>+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK                                                            0x00FF0000L
>+#define DIG0_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK                                                            0xFF000000L
>+//DIG0_AFMT_ISRC1_2
>+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT                                                          0x0
>+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT                                                          0x8
>+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT                                                          0x10
>+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT                                                          0x18
>+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK                                                            0x000000FFL
>+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK                                                            0x0000FF00L
>+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK                                                            0x00FF0000L
>+#define DIG0_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK                                                            0xFF000000L
>+//DIG0_AFMT_ISRC1_3
>+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT                                                          0x0
>+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT                                                          0x8
>+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT                                                         0x10
>+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT                                                         0x18
>+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK                                                            0x000000FFL
>+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK                                                            0x0000FF00L
>+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK                                                           0x00FF0000L
>+#define DIG0_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK                                                           0xFF000000L
>+//DIG0_AFMT_ISRC1_4
>+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT                                                         0x0
>+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT                                                         0x8
>+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT                                                         0x10
>+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT                                                         0x18
>+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK                                                           0x000000FFL
>+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK                                                           0x0000FF00L
>+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK                                                           0x00FF0000L
>+#define DIG0_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK                                                           0xFF000000L
>+//DIG0_AFMT_ISRC2_0
>+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT                                                         0x0
>+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT                                                         0x8
>+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT                                                         0x10
>+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT                                                         0x18
>+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK                                                           0x000000FFL
>+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK                                                           0x0000FF00L
>+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK                                                           0x00FF0000L
>+#define DIG0_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK                                                           0xFF000000L
>+//DIG0_AFMT_ISRC2_1
>+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT                                                         0x0
>+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT                                                         0x8
>+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT                                                         0x10
>+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT                                                         0x18
>+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK                                                           0x000000FFL
>+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK                                                           0x0000FF00L
>+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK                                                           0x00FF0000L
>+#define DIG0_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK                                                           0xFF000000L
>+//DIG0_AFMT_ISRC2_2
>+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT                                                         0x0
>+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT                                                         0x8
>+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT                                                         0x10
>+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT                                                         0x18
>+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK                                                           0x000000FFL
>+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK                                                           0x0000FF00L
>+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK                                                           0x00FF0000L
>+#define DIG0_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK                                                           0xFF000000L
>+//DIG0_AFMT_ISRC2_3
>+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT                                                         0x0
>+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT                                                         0x8
>+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT                                                         0x10
>+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT                                                         0x18
>+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK                                                           0x000000FFL
>+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK                                                           0x0000FF00L
>+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK                                                           0x00FF0000L
>+#define DIG0_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK                                                           0xFF000000L
>+//DIG0_HDMI_GENERIC_PACKET_CONTROL2
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
>+//DIG0_HDMI_GENERIC_PACKET_CONTROL3
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
>+//DIG0_HDMI_DB_CONTROL
>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
>+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
>+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
>+//DIG0_DME_CONTROL
>+#define DIG0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
>+#define DIG0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
>+#define DIG0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
>+#define DIG0_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
>+#define DIG0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
>+#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
>+#define DIG0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
>+#define DIG0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
>+#define DIG0_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
>+#define DIG0_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
>+#define DIG0_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
>+#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
>+#define DIG0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
>+#define DIG0_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
>+//DIG0_AFMT_MPEG_INFO0
>+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT                                                  0x0
>+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT                                                       0x8
>+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT                                                       0x10
>+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT                                                       0x18
>+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK                                                    0x000000FFL
>+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK                                                         0x0000FF00L
>+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK                                                         0x00FF0000L
>+#define DIG0_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK                                                         0xFF000000L
>+//DIG0_AFMT_MPEG_INFO1
>+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT                                                       0x0
>+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT                                                        0x8
>+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT                                                        0xc
>+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK                                                         0x000000FFL
>+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK                                                          0x00000300L
>+#define DIG0_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK                                                          0x00001000L
>+//DIG0_AFMT_GENERIC_HDR
>+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT                                                        0x0
>+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT                                                        0x8
>+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT                                                        0x10
>+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT                                                        0x18
>+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK                                                          0x000000FFL
>+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK                                                          0x0000FF00L
>+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK                                                          0x00FF0000L
>+#define DIG0_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK                                                          0xFF000000L
>+//DIG0_AFMT_GENERIC_0
>+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT                                                        0x0
>+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT                                                        0x8
>+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT                                                        0x10
>+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT                                                        0x18
>+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK                                                          0x000000FFL
>+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK                                                          0x0000FF00L
>+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK                                                          0x00FF0000L
>+#define DIG0_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK                                                          0xFF000000L
>+//DIG0_AFMT_GENERIC_1
>+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT                                                        0x0
>+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT                                                        0x8
>+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT                                                        0x10
>+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT                                                        0x18
>+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK                                                          0x000000FFL
>+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK                                                          0x0000FF00L
>+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK                                                          0x00FF0000L
>+#define DIG0_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK                                                          0xFF000000L
>+//DIG0_AFMT_GENERIC_2
>+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT                                                        0x0
>+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT                                                        0x8
>+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT                                                       0x10
>+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT                                                       0x18
>+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK                                                          0x000000FFL
>+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK                                                          0x0000FF00L
>+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK                                                         0x00FF0000L
>+#define DIG0_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK                                                         0xFF000000L
>+//DIG0_AFMT_GENERIC_3
>+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT                                                       0x0
>+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT                                                       0x8
>+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT                                                       0x10
>+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT                                                       0x18
>+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK                                                         0x000000FFL
>+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK                                                         0x0000FF00L
>+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK                                                         0x00FF0000L
>+#define DIG0_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK                                                         0xFF000000L
>+//DIG0_AFMT_GENERIC_4
>+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT                                                       0x0
>+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT                                                       0x8
>+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT                                                       0x10
>+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT                                                       0x18
>+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK                                                         0x000000FFL
>+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK                                                         0x0000FF00L
>+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK                                                         0x00FF0000L
>+#define DIG0_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK                                                         0xFF000000L
>+//DIG0_AFMT_GENERIC_5
>+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT                                                       0x0
>+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT                                                       0x8
>+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT                                                       0x10
>+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT                                                       0x18
>+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK                                                         0x000000FFL
>+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK                                                         0x0000FF00L
>+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK                                                         0x00FF0000L
>+#define DIG0_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK                                                         0xFF000000L
>+//DIG0_AFMT_GENERIC_6
>+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT                                                       0x0
>+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT                                                       0x8
>+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT                                                       0x10
>+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT                                                       0x18
>+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK                                                         0x000000FFL
>+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK                                                         0x0000FF00L
>+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK                                                         0x00FF0000L
>+#define DIG0_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK                                                         0xFF000000L
>+//DIG0_AFMT_GENERIC_7
>+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT                                                       0x0
>+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT                                                       0x8
>+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT                                                       0x10
>+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT                                                       0x18
>+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK                                                         0x000000FFL
>+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK                                                         0x0000FF00L
>+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK                                                         0x00FF0000L
>+#define DIG0_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK                                                         0xFF000000L
>+//DIG0_HDMI_GENERIC_PACKET_CONTROL1
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
>+//DIG0_HDMI_ACR_32_0
>+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
>+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
>+//DIG0_HDMI_ACR_32_1
>+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
>+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
>+//DIG0_HDMI_ACR_44_0
>+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
>+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
>+//DIG0_HDMI_ACR_44_1
>+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
>+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
>+//DIG0_HDMI_ACR_48_0
>+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
>+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
>+//DIG0_HDMI_ACR_48_1
>+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
>+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
>+//DIG0_HDMI_ACR_STATUS_0
>+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
>+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
>+//DIG0_HDMI_ACR_STATUS_1
>+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
>+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
>+//DIG0_AFMT_AUDIO_INFO0
>+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                                0x0
>+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                      0x8
>+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                      0xb
>+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                         0x10
>+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                     0x18
>+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                  0x000000FFL
>+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                        0x00000700L
>+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                        0x00007800L
>+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                           0x00FF0000L
>+#define DIG0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                       0x1F000000L
>+//DIG0_AFMT_AUDIO_INFO1
>+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                      0x0
>+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                     0xb
>+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                  0xf
>+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                  0x10
>+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                        0x000000FFL
>+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                       0x00007800L
>+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                    0x00008000L
>+#define DIG0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                    0x00030000L
>+//DIG0_AFMT_60958_0
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                             0x0
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                             0x1
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                             0x2
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                             0x3
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                          0x6
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                 0x8
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                 0x10
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                              0x14
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                            0x18
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                                0x1c
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                               0x00000001L
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                               0x00000002L
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                               0x00000004L
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                               0x00000038L
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                            0x000000C0L
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                   0x0000FF00L
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                   0x000F0000L
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                                0x00F00000L
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                              0x0F000000L
>+#define DIG0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                  0x30000000L
>+//DIG0_AFMT_60958_1
>+#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                   0x0
>+#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                   0x4
>+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                          0x10
>+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                          0x12
>+#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                              0x14
>+#define DIG0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                     0x0000000FL
>+#define DIG0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                     0x000000F0L
>+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                            0x00010000L
>+#define DIG0_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                            0x00040000L
>+#define DIG0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                                0x00F00000L
>+//DIG0_AFMT_AUDIO_CRC_CONTROL
>+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                 0x0
>+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                               0x4
>+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                             0x8
>+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                             0xc
>+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                              0x10
>+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                   0x00000001L
>+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                 0x00000010L
>+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                               0x00000100L
>+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                               0x0000F000L
>+#define DIG0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                                0xFFFF0000L
>+//DIG0_AFMT_RAMP_CONTROL0
>+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                   0x0
>+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                   0x1f
>+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                     0x00FFFFFFL
>+#define DIG0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                     0x80000000L
>+//DIG0_AFMT_RAMP_CONTROL1
>+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                   0x0
>+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                            0x18
>+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                     0x00FFFFFFL
>+#define DIG0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                              0xFF000000L
>+//DIG0_AFMT_RAMP_CONTROL2
>+#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                   0x0
>+#define DIG0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                     0x00FFFFFFL
>+//DIG0_AFMT_RAMP_CONTROL3
>+#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                   0x0
>+#define DIG0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                     0x00FFFFFFL
>+//DIG0_AFMT_60958_2
>+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                              0x0
>+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                              0x4
>+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                              0x8
>+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                              0xc
>+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                              0x10
>+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                              0x14
>+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                                0x0000000FL
>+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                                0x000000F0L
>+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                                0x00000F00L
>+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                                0x0000F000L
>+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                                0x000F0000L
>+#define DIG0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                                0x00F00000L
>+//DIG0_AFMT_AUDIO_CRC_RESULT
>+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                                0x0
>+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                     0x8
>+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                  0x00000001L
>+#define DIG0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                       0xFFFFFF00L
>+//DIG0_AFMT_STATUS
>+#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                            0x4
>+#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                           0x8
>+#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                     0x18
>+#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                     0x1e
>+#define DIG0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                              0x00000010L
>+#define DIG0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                             0x00000100L
>+#define DIG0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                       0x01000000L
>+#define DIG0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                       0x40000000L
>+//DIG0_AFMT_AUDIO_PACKET_CONTROL
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                         0x0
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                 0xb
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                             0xc
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                           0xe
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                   0x17
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                        0x18
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                           0x1a
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                   0x1e
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                                0x1f
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                           0x00000001L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                   0x00000800L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                               0x00001000L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                             0x00004000L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                     0x00800000L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                          0x01000000L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                             0x04000000L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                     0x40000000L
>+#define DIG0_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                  0x80000000L
>+//DIG0_AFMT_VBI_PACKET_CONTROL
>+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT                                         0x8
>+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT                                            0x10
>+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT                                        0x11
>+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT                                               0x1c
>+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK                                           0x00000100L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK                                              0x00010000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK                                          0x00020000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK                                                 0xF0000000L
>+//DIG0_AFMT_INFOFRAME_CONTROL0
>+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                           0x6
>+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                           0x7
>+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT                                            0xa
>+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                             0x00000040L
>+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                             0x00000080L
>+#define DIG0_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK                                              0x00000400L
>+//DIG0_AFMT_AUDIO_SRC_CONTROL
>+#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                             0x0
>+#define DIG0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                               0x00000007L
>+//DIG0_DIG_BE_CNTL
>+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
>+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
>+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
>+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
>+#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
>+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
>+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
>+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
>+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
>+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
>+#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
>+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
>+//DIG0_DIG_BE_EN_CNTL
>+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
>+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
>+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
>+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
>+//DIG0_TMDS_CNTL
>+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
>+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
>+//DIG0_TMDS_CONTROL_CHAR
>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
>+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
>+//DIG0_TMDS_CONTROL0_FEEDBACK
>+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
>+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
>+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
>+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
>+//DIG0_TMDS_STEREOSYNC_CTL_SEL
>+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
>+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
>+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
>+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
>+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
>+//DIG0_TMDS_CTL_BITS
>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
>+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
>+//DIG0_TMDS_DCBALANCER_CONTROL
>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
>+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
>+//DIG0_TMDS_SYNC_DCBALANCE_CHAR
>+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
>+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
>+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
>+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
>+//DIG0_TMDS_CTL0_1_GEN_CNTL
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
>+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
>+//DIG0_TMDS_CTL2_3_GEN_CNTL
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
>+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
>+//DIG0_DIG_VERSION
>+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
>+#define DIG0_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
>+//DIG0_DIG_LANE_ENABLE
>+#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
>+#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
>+#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
>+#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
>+#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
>+#define DIG0_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
>+#define DIG0_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
>+#define DIG0_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
>+#define DIG0_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
>+#define DIG0_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
>+//DIG0_AFMT_CNTL
>+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
>+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
>+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
>+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
>+//DIG0_AFMT_VBI_PACKET_CONTROL1
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x1
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT                                  0x2
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x3
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT                                      0x4
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x5
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT                                  0x6
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x7
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT                                      0x8
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x9
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT                                  0xa
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xb
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT                                      0xc
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0xd
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT                                  0xe
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xf
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT                                      0x10
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x11
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT                                  0x12
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x13
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT                                      0x14
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT                                  0x16
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x17
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT                                      0x18
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x19
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT                                  0x1a
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1b
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT                                      0x1c
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x1d
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT                                  0x1e
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1f
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00000002L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK                                    0x00000004L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000008L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK                                        0x00000010L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00000020L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK                                    0x00000040L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000080L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK                                        0x00000100L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00000200L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK                                    0x00000400L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000800L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK                                        0x00001000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00002000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK                                    0x00004000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                            0x00008000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK                                        0x00010000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00020000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK                                    0x00040000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                            0x00080000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK                                        0x00100000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK                                    0x00400000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                            0x00800000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK                                        0x01000000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x02000000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK                                    0x04000000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                            0x08000000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK                                        0x10000000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x20000000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK                                    0x40000000L
>+#define DIG0_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                            0x80000000L
>+//DIG0_HDMI_GENERIC_PACKET_CONTROL5
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
>+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
>+//DIG0_FORCE_DIG_DISABLE
>+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
>+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
>+
>+
>+// addressBlock: dce_dc_dio_dp0_dispdec
>+//DP0_DP_LINK_CNTL
>+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
>+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
>+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
>+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
>+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
>+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
>+//DP0_DP_PIXEL_FORMAT
>+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
>+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
>+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
>+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
>+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
>+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
>+//DP0_DP_MSA_COLORIMETRY
>+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
>+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
>+//DP0_DP_CONFIG
>+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
>+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
>+//DP0_DP_VID_STREAM_CNTL
>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
>+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
>+//DP0_DP_STEER_FIFO
>+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
>+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
>+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
>+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
>+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
>+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
>+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
>+//DP0_DP_MSA_MISC
>+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
>+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
>+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
>+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
>+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
>+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
>+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
>+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
>+//DP0_DP_VID_TIMING
>+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
>+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
>+#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
>+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
>+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
>+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
>+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
>+#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
>+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
>+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
>+//DP0_DP_VID_N
>+#define DP0_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
>+#define DP0_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
>+//DP0_DP_VID_M
>+#define DP0_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
>+#define DP0_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
>+//DP0_DP_LINK_FRAMING_CNTL
>+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
>+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
>+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
>+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
>+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
>+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
>+//DP0_DP_HBR2_EYE_PATTERN
>+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
>+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
>+//DP0_DP_VID_MSA_VBID
>+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
>+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
>+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
>+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
>+//DP0_DP_VID_INTERRUPT_CNTL
>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
>+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
>+//DP0_DP_DPHY_CNTL
>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
>+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
>+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
>+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
>+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
>+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
>+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
>+//DP0_DP_DPHY_TRAINING_PATTERN_SEL
>+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
>+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
>+//DP0_DP_DPHY_SYM0
>+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
>+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
>+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
>+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
>+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
>+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
>+//DP0_DP_DPHY_SYM1
>+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
>+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
>+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
>+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
>+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
>+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
>+//DP0_DP_DPHY_SYM2
>+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
>+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
>+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
>+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
>+//DP0_DP_DPHY_8B10B_CNTL
>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
>+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
>+//DP0_DP_DPHY_PRBS_CNTL
>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
>+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
>+//DP0_DP_DPHY_SCRAM_CNTL
>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
>+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
>+//DP0_DP_DPHY_CRC_EN
>+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
>+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
>+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
>+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
>+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
>+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
>+//DP0_DP_DPHY_CRC_CNTL
>+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
>+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
>+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
>+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
>+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
>+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
>+//DP0_DP_DPHY_CRC_RESULT
>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
>+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
>+//DP0_DP_DPHY_CRC_MST_CNTL
>+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
>+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
>+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
>+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
>+//DP0_DP_DPHY_CRC_MST_STATUS
>+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
>+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
>+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
>+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
>+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
>+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
>+//DP0_DP_DPHY_FAST_TRAINING
>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
>+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
>+//DP0_DP_DPHY_FAST_TRAINING_STATUS
>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
>+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
>+//DP0_DP_SEC_CNTL
>+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
>+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
>+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
>+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
>+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
>+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
>+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
>+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
>+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
>+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
>+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
>+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
>+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
>+//DP0_DP_SEC_CNTL1
>+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
>+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
>+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP0_DP_SEC_FRAMING1
>+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
>+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
>+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
>+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
>+//DP0_DP_SEC_FRAMING2
>+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
>+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
>+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
>+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
>+//DP0_DP_SEC_FRAMING3
>+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
>+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
>+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
>+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
>+//DP0_DP_SEC_FRAMING4
>+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
>+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
>+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
>+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
>+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
>+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
>+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
>+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
>+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
>+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
>+//DP0_DP_SEC_AUD_N
>+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
>+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
>+//DP0_DP_SEC_AUD_N_READBACK
>+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
>+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
>+//DP0_DP_SEC_AUD_M
>+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
>+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
>+//DP0_DP_SEC_AUD_M_READBACK
>+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
>+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
>+//DP0_DP_SEC_TIMESTAMP
>+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
>+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
>+//DP0_DP_SEC_PACKET_CNTL
>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
>+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
>+//DP0_DP_MSE_RATE_CNTL
>+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
>+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
>+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
>+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
>+//DP0_DP_MSE_RATE_UPDATE
>+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
>+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
>+//DP0_DP_MSE_SAT0
>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
>+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
>+//DP0_DP_MSE_SAT1
>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
>+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
>+//DP0_DP_MSE_SAT2
>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
>+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
>+//DP0_DP_MSE_SAT_UPDATE
>+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
>+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
>+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
>+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
>+//DP0_DP_MSE_LINK_TIMING
>+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
>+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
>+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
>+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
>+//DP0_DP_MSE_MISC_CNTL
>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
>+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
>+//DP0_DP_DPHY_BS_SR_SWAP_CNTL
>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
>+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
>+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
>+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
>+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
>+//DP0_DP_MSE_SAT0_STATUS
>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
>+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
>+//DP0_DP_MSE_SAT1_STATUS
>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
>+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
>+//DP0_DP_MSE_SAT2_STATUS
>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
>+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
>+//DP0_DP_MSA_TIMING_PARAM1
>+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
>+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
>+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
>+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
>+//DP0_DP_MSA_TIMING_PARAM2
>+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
>+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
>+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
>+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
>+//DP0_DP_MSA_TIMING_PARAM3
>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
>+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
>+//DP0_DP_MSA_TIMING_PARAM4
>+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
>+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
>+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
>+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
>+//DP0_DP_MSO_CNTL
>+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
>+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
>+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
>+//DP0_DP_MSO_CNTL1
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
>+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
>+//DP0_DP_DSC_CNTL
>+#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
>+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
>+#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
>+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
>+//DP0_DP_SEC_CNTL2
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT                                                              0x1c
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
>+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK                                                                0x10000000L
>+//DP0_DP_SEC_CNTL3
>+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
>+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
>+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP0_DP_SEC_CNTL4
>+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
>+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
>+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP0_DP_SEC_CNTL5
>+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
>+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
>+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP0_DP_SEC_CNTL6
>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
>+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
>+//DP0_DP_SEC_CNTL7
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
>+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
>+//DP0_DP_DB_CNTL
>+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
>+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
>+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
>+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
>+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
>+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
>+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
>+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
>+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
>+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
>+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
>+//DP0_DP_MSA_VBID_MISC
>+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
>+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
>+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
>+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
>+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
>+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
>+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
>+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
>+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
>+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
>+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
>+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
>+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
>+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
>+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
>+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
>+//DP0_DP_SEC_METADATA_TRANSMISSION
>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
>+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
>+//DP0_DP_DSC_BYTES_PER_PIXEL
>+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
>+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
>+//DP0_DP_ALPM_CNTL
>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
>+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
>+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
>+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dio_dig1_dispdec
>+//DIG1_DIG_FE_CNTL
>+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
>+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
>+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
>+#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
>+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
>+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
>+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
>+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
>+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
>+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
>+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
>+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
>+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
>+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
>+#define DIG1_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
>+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
>+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
>+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
>+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
>+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
>+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
>+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
>+//DIG1_DIG_OUTPUT_CRC_CNTL
>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
>+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
>+//DIG1_DIG_OUTPUT_CRC_RESULT
>+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
>+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
>+//DIG1_DIG_CLOCK_PATTERN
>+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
>+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
>+//DIG1_DIG_TEST_PATTERN
>+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
>+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
>+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
>+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
>+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
>+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
>+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
>+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
>+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
>+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
>+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
>+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
>+//DIG1_DIG_RANDOM_PATTERN_SEED
>+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
>+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
>+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
>+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
>+//DIG1_DIG_FIFO_STATUS
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
>+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
>+//DIG1_HDMI_METADATA_PACKET_CONTROL
>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
>+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
>+//DIG1_HDMI_GENERIC_PACKET_CONTROL4
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
>+//DIG1_HDMI_CONTROL
>+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
>+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
>+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
>+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
>+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
>+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
>+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
>+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
>+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
>+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
>+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
>+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
>+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
>+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
>+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
>+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
>+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
>+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
>+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
>+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
>+//DIG1_HDMI_STATUS
>+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
>+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
>+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
>+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
>+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
>+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
>+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
>+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
>+//DIG1_HDMI_AUDIO_PACKET_CONTROL
>+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
>+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                    0x8
>+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                    0x10
>+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
>+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                      0x00000100L
>+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK                                      0x001F0000L
>+//DIG1_HDMI_ACR_PACKET_CONTROL
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
>+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
>+//DIG1_HDMI_VBI_PACKET_CONTROL
>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
>+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
>+//DIG1_HDMI_INFOFRAME_CONTROL0
>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
>+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
>+//DIG1_HDMI_INFOFRAME_CONTROL1
>+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
>+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
>+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
>+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
>+//DIG1_HDMI_GENERIC_PACKET_CONTROL0
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
>+//DIG1_HDMI_GC
>+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
>+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
>+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
>+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
>+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
>+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
>+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
>+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
>+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
>+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
>+//DIG1_AFMT_AUDIO_PACKET_CONTROL2
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                        0x0
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                      0x1
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                     0x8
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                       0x10
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                          0x18
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                           0x1c
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                          0x00000001L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                        0x00000002L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                       0x0000FF00L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                         0x00FF0000L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                            0x01000000L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                             0x10000000L
>+//DIG1_AFMT_ISRC1_0
>+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT                                                            0x0
>+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT                                                          0x6
>+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT                                                             0x7
>+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK                                                              0x00000007L
>+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK                                                            0x00000040L
>+#define DIG1_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK                                                               0x00000080L
>+//DIG1_AFMT_ISRC1_1
>+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT                                                          0x0
>+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT                                                          0x8
>+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT                                                          0x10
>+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT                                                          0x18
>+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK                                                            0x000000FFL
>+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK                                                            0x0000FF00L
>+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK                                                            0x00FF0000L
>+#define DIG1_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK                                                            0xFF000000L
>+//DIG1_AFMT_ISRC1_2
>+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT                                                          0x0
>+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT                                                          0x8
>+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT                                                          0x10
>+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT                                                          0x18
>+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK                                                            0x000000FFL
>+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK                                                            0x0000FF00L
>+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK                                                            0x00FF0000L
>+#define DIG1_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK                                                            0xFF000000L
>+//DIG1_AFMT_ISRC1_3
>+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT                                                          0x0
>+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT                                                          0x8
>+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT                                                         0x10
>+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT                                                         0x18
>+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK                                                            0x000000FFL
>+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK                                                            0x0000FF00L
>+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK                                                           0x00FF0000L
>+#define DIG1_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK                                                           0xFF000000L
>+//DIG1_AFMT_ISRC1_4
>+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT                                                         0x0
>+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT                                                         0x8
>+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT                                                         0x10
>+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT                                                         0x18
>+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK                                                           0x000000FFL
>+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK                                                           0x0000FF00L
>+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK                                                           0x00FF0000L
>+#define DIG1_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK                                                           0xFF000000L
>+//DIG1_AFMT_ISRC2_0
>+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT                                                         0x0
>+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT                                                         0x8
>+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT                                                         0x10
>+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT                                                         0x18
>+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK                                                           0x000000FFL
>+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK                                                           0x0000FF00L
>+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK                                                           0x00FF0000L
>+#define DIG1_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK                                                           0xFF000000L
>+//DIG1_AFMT_ISRC2_1
>+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT                                                         0x0
>+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT                                                         0x8
>+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT                                                         0x10
>+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT                                                         0x18
>+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK                                                           0x000000FFL
>+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK                                                           0x0000FF00L
>+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK                                                           0x00FF0000L
>+#define DIG1_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK                                                           0xFF000000L
>+//DIG1_AFMT_ISRC2_2
>+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT                                                         0x0
>+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT                                                         0x8
>+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT                                                         0x10
>+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT                                                         0x18
>+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK                                                           0x000000FFL
>+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK                                                           0x0000FF00L
>+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK                                                           0x00FF0000L
>+#define DIG1_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK                                                           0xFF000000L
>+//DIG1_AFMT_ISRC2_3
>+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT                                                         0x0
>+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT                                                         0x8
>+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT                                                         0x10
>+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT                                                         0x18
>+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK                                                           0x000000FFL
>+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK                                                           0x0000FF00L
>+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK                                                           0x00FF0000L
>+#define DIG1_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK                                                           0xFF000000L
>+//DIG1_HDMI_GENERIC_PACKET_CONTROL2
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
>+//DIG1_HDMI_GENERIC_PACKET_CONTROL3
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
>+//DIG1_HDMI_DB_CONTROL
>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
>+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
>+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
>+//DIG1_DME_CONTROL
>+#define DIG1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
>+#define DIG1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
>+#define DIG1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
>+#define DIG1_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
>+#define DIG1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
>+#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
>+#define DIG1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
>+#define DIG1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
>+#define DIG1_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
>+#define DIG1_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
>+#define DIG1_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
>+#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
>+#define DIG1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
>+#define DIG1_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
>+//DIG1_AFMT_MPEG_INFO0
>+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT                                                  0x0
>+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT                                                       0x8
>+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT                                                       0x10
>+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT                                                       0x18
>+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK                                                    0x000000FFL
>+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK                                                         0x0000FF00L
>+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK                                                         0x00FF0000L
>+#define DIG1_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK                                                         0xFF000000L
>+//DIG1_AFMT_MPEG_INFO1
>+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT                                                       0x0
>+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT                                                        0x8
>+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT                                                        0xc
>+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK                                                         0x000000FFL
>+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK                                                          0x00000300L
>+#define DIG1_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK                                                          0x00001000L
>+//DIG1_AFMT_GENERIC_HDR
>+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT                                                        0x0
>+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT                                                        0x8
>+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT                                                        0x10
>+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT                                                        0x18
>+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK                                                          0x000000FFL
>+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK                                                          0x0000FF00L
>+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK                                                          0x00FF0000L
>+#define DIG1_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK                                                          0xFF000000L
>+//DIG1_AFMT_GENERIC_0
>+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT                                                        0x0
>+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT                                                        0x8
>+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT                                                        0x10
>+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT                                                        0x18
>+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK                                                          0x000000FFL
>+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK                                                          0x0000FF00L
>+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK                                                          0x00FF0000L
>+#define DIG1_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK                                                          0xFF000000L
>+//DIG1_AFMT_GENERIC_1
>+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT                                                        0x0
>+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT                                                        0x8
>+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT                                                        0x10
>+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT                                                        0x18
>+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK                                                          0x000000FFL
>+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK                                                          0x0000FF00L
>+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK                                                          0x00FF0000L
>+#define DIG1_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK                                                          0xFF000000L
>+//DIG1_AFMT_GENERIC_2
>+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT                                                        0x0
>+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT                                                        0x8
>+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT                                                       0x10
>+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT                                                       0x18
>+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK                                                          0x000000FFL
>+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK                                                          0x0000FF00L
>+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK                                                         0x00FF0000L
>+#define DIG1_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK                                                         0xFF000000L
>+//DIG1_AFMT_GENERIC_3
>+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT                                                       0x0
>+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT                                                       0x8
>+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT                                                       0x10
>+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT                                                       0x18
>+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK                                                         0x000000FFL
>+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK                                                         0x0000FF00L
>+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK                                                         0x00FF0000L
>+#define DIG1_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK                                                         0xFF000000L
>+//DIG1_AFMT_GENERIC_4
>+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT                                                       0x0
>+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT                                                       0x8
>+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT                                                       0x10
>+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT                                                       0x18
>+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK                                                         0x000000FFL
>+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK                                                         0x0000FF00L
>+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK                                                         0x00FF0000L
>+#define DIG1_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK                                                         0xFF000000L
>+//DIG1_AFMT_GENERIC_5
>+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT                                                       0x0
>+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT                                                       0x8
>+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT                                                       0x10
>+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT                                                       0x18
>+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK                                                         0x000000FFL
>+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK                                                         0x0000FF00L
>+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK                                                         0x00FF0000L
>+#define DIG1_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK                                                         0xFF000000L
>+//DIG1_AFMT_GENERIC_6
>+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT                                                       0x0
>+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT                                                       0x8
>+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT                                                       0x10
>+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT                                                       0x18
>+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK                                                         0x000000FFL
>+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK                                                         0x0000FF00L
>+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK                                                         0x00FF0000L
>+#define DIG1_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK                                                         0xFF000000L
>+//DIG1_AFMT_GENERIC_7
>+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT                                                       0x0
>+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT                                                       0x8
>+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT                                                       0x10
>+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT                                                       0x18
>+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK                                                         0x000000FFL
>+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK                                                         0x0000FF00L
>+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK                                                         0x00FF0000L
>+#define DIG1_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK                                                         0xFF000000L
>+//DIG1_HDMI_GENERIC_PACKET_CONTROL1
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
>+//DIG1_HDMI_ACR_32_0
>+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
>+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
>+//DIG1_HDMI_ACR_32_1
>+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
>+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
>+//DIG1_HDMI_ACR_44_0
>+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
>+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
>+//DIG1_HDMI_ACR_44_1
>+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
>+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
>+//DIG1_HDMI_ACR_48_0
>+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
>+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
>+//DIG1_HDMI_ACR_48_1
>+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
>+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
>+//DIG1_HDMI_ACR_STATUS_0
>+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
>+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
>+//DIG1_HDMI_ACR_STATUS_1
>+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
>+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
>+//DIG1_AFMT_AUDIO_INFO0
>+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                                0x0
>+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                      0x8
>+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                      0xb
>+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                         0x10
>+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                     0x18
>+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                  0x000000FFL
>+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                        0x00000700L
>+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                        0x00007800L
>+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                           0x00FF0000L
>+#define DIG1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                       0x1F000000L
>+//DIG1_AFMT_AUDIO_INFO1
>+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                      0x0
>+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                     0xb
>+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                  0xf
>+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                  0x10
>+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                        0x000000FFL
>+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                       0x00007800L
>+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                    0x00008000L
>+#define DIG1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                    0x00030000L
>+//DIG1_AFMT_60958_0
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                             0x0
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                             0x1
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                             0x2
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                             0x3
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                          0x6
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                 0x8
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                 0x10
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                              0x14
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                            0x18
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                                0x1c
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                               0x00000001L
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                               0x00000002L
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                               0x00000004L
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                               0x00000038L
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                            0x000000C0L
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                   0x0000FF00L
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                   0x000F0000L
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                                0x00F00000L
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                              0x0F000000L
>+#define DIG1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                  0x30000000L
>+//DIG1_AFMT_60958_1
>+#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                   0x0
>+#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                   0x4
>+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                          0x10
>+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                          0x12
>+#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                              0x14
>+#define DIG1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                     0x0000000FL
>+#define DIG1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                     0x000000F0L
>+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                            0x00010000L
>+#define DIG1_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                            0x00040000L
>+#define DIG1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                                0x00F00000L
>+//DIG1_AFMT_AUDIO_CRC_CONTROL
>+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                 0x0
>+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                               0x4
>+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                             0x8
>+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                             0xc
>+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                              0x10
>+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                   0x00000001L
>+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                 0x00000010L
>+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                               0x00000100L
>+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                               0x0000F000L
>+#define DIG1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                                0xFFFF0000L
>+//DIG1_AFMT_RAMP_CONTROL0
>+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                   0x0
>+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                   0x1f
>+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                     0x00FFFFFFL
>+#define DIG1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                     0x80000000L
>+//DIG1_AFMT_RAMP_CONTROL1
>+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                   0x0
>+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                            0x18
>+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                     0x00FFFFFFL
>+#define DIG1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                              0xFF000000L
>+//DIG1_AFMT_RAMP_CONTROL2
>+#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                   0x0
>+#define DIG1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                     0x00FFFFFFL
>+//DIG1_AFMT_RAMP_CONTROL3
>+#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                   0x0
>+#define DIG1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                     0x00FFFFFFL
>+//DIG1_AFMT_60958_2
>+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                              0x0
>+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                              0x4
>+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                              0x8
>+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                              0xc
>+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                              0x10
>+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                              0x14
>+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                                0x0000000FL
>+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                                0x000000F0L
>+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                                0x00000F00L
>+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                                0x0000F000L
>+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                                0x000F0000L
>+#define DIG1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                                0x00F00000L
>+//DIG1_AFMT_AUDIO_CRC_RESULT
>+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                                0x0
>+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                     0x8
>+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                  0x00000001L
>+#define DIG1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                       0xFFFFFF00L
>+//DIG1_AFMT_STATUS
>+#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                            0x4
>+#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                           0x8
>+#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                     0x18
>+#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                     0x1e
>+#define DIG1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                              0x00000010L
>+#define DIG1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                             0x00000100L
>+#define DIG1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                       0x01000000L
>+#define DIG1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                       0x40000000L
>+//DIG1_AFMT_AUDIO_PACKET_CONTROL
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                         0x0
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                 0xb
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                             0xc
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                           0xe
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                   0x17
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                        0x18
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                           0x1a
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                   0x1e
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                                0x1f
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                           0x00000001L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                   0x00000800L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                               0x00001000L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                             0x00004000L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                     0x00800000L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                          0x01000000L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                             0x04000000L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                     0x40000000L
>+#define DIG1_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                  0x80000000L
>+//DIG1_AFMT_VBI_PACKET_CONTROL
>+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT                                         0x8
>+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT                                            0x10
>+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT                                        0x11
>+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT                                               0x1c
>+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK                                           0x00000100L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK                                              0x00010000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK                                          0x00020000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK                                                 0xF0000000L
>+//DIG1_AFMT_INFOFRAME_CONTROL0
>+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                           0x6
>+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                           0x7
>+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT                                            0xa
>+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                             0x00000040L
>+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                             0x00000080L
>+#define DIG1_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK                                              0x00000400L
>+//DIG1_AFMT_AUDIO_SRC_CONTROL
>+#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                             0x0
>+#define DIG1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                               0x00000007L
>+//DIG1_DIG_BE_CNTL
>+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
>+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
>+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
>+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
>+#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
>+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
>+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
>+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
>+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
>+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
>+#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
>+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
>+//DIG1_DIG_BE_EN_CNTL
>+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
>+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
>+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
>+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
>+//DIG1_TMDS_CNTL
>+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
>+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
>+//DIG1_TMDS_CONTROL_CHAR
>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
>+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
>+//DIG1_TMDS_CONTROL0_FEEDBACK
>+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
>+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
>+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
>+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
>+//DIG1_TMDS_STEREOSYNC_CTL_SEL
>+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
>+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
>+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
>+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
>+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
>+//DIG1_TMDS_CTL_BITS
>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
>+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
>+//DIG1_TMDS_DCBALANCER_CONTROL
>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
>+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
>+//DIG1_TMDS_SYNC_DCBALANCE_CHAR
>+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
>+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
>+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
>+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
>+//DIG1_TMDS_CTL0_1_GEN_CNTL
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
>+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
>+//DIG1_TMDS_CTL2_3_GEN_CNTL
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
>+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
>+//DIG1_DIG_VERSION
>+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
>+#define DIG1_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
>+//DIG1_DIG_LANE_ENABLE
>+#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
>+#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
>+#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
>+#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
>+#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
>+#define DIG1_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
>+#define DIG1_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
>+#define DIG1_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
>+#define DIG1_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
>+#define DIG1_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
>+//DIG1_AFMT_CNTL
>+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
>+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
>+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
>+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
>+//DIG1_AFMT_VBI_PACKET_CONTROL1
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x1
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT                                  0x2
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x3
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT                                      0x4
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x5
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT                                  0x6
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x7
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT                                      0x8
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x9
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT                                  0xa
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xb
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT                                      0xc
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0xd
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT                                  0xe
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xf
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT                                      0x10
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x11
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT                                  0x12
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x13
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT                                      0x14
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT                                  0x16
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x17
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT                                      0x18
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x19
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT                                  0x1a
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1b
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT                                      0x1c
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x1d
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT                                  0x1e
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1f
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00000002L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK                                    0x00000004L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000008L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK                                        0x00000010L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00000020L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK                                    0x00000040L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000080L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK                                        0x00000100L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00000200L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK                                    0x00000400L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000800L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK                                        0x00001000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00002000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK                                    0x00004000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                            0x00008000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK                                        0x00010000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00020000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK                                    0x00040000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                            0x00080000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK                                        0x00100000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK                                    0x00400000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                            0x00800000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK                                        0x01000000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x02000000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK                                    0x04000000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                            0x08000000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK                                        0x10000000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x20000000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK                                    0x40000000L
>+#define DIG1_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                            0x80000000L
>+//DIG1_HDMI_GENERIC_PACKET_CONTROL5
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
>+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
>+//DIG1_FORCE_DIG_DISABLE
>+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
>+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
>+
>+
>+// addressBlock: dce_dc_dio_dp1_dispdec
>+//DP1_DP_LINK_CNTL
>+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
>+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
>+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
>+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
>+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
>+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
>+//DP1_DP_PIXEL_FORMAT
>+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
>+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
>+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
>+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
>+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
>+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
>+//DP1_DP_MSA_COLORIMETRY
>+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
>+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
>+//DP1_DP_CONFIG
>+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
>+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
>+//DP1_DP_VID_STREAM_CNTL
>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
>+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
>+//DP1_DP_STEER_FIFO
>+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
>+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
>+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
>+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
>+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
>+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
>+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
>+//DP1_DP_MSA_MISC
>+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
>+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
>+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
>+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
>+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
>+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
>+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
>+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
>+//DP1_DP_VID_TIMING
>+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
>+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
>+#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
>+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
>+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
>+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
>+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
>+#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
>+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
>+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
>+//DP1_DP_VID_N
>+#define DP1_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
>+#define DP1_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
>+//DP1_DP_VID_M
>+#define DP1_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
>+#define DP1_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
>+//DP1_DP_LINK_FRAMING_CNTL
>+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
>+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
>+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
>+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
>+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
>+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
>+//DP1_DP_HBR2_EYE_PATTERN
>+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
>+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
>+//DP1_DP_VID_MSA_VBID
>+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
>+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
>+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
>+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
>+//DP1_DP_VID_INTERRUPT_CNTL
>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
>+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
>+//DP1_DP_DPHY_CNTL
>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
>+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
>+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
>+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
>+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
>+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
>+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
>+//DP1_DP_DPHY_TRAINING_PATTERN_SEL
>+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
>+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
>+//DP1_DP_DPHY_SYM0
>+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
>+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
>+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
>+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
>+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
>+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
>+//DP1_DP_DPHY_SYM1
>+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
>+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
>+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
>+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
>+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
>+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
>+//DP1_DP_DPHY_SYM2
>+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
>+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
>+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
>+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
>+//DP1_DP_DPHY_8B10B_CNTL
>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
>+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
>+//DP1_DP_DPHY_PRBS_CNTL
>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
>+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
>+//DP1_DP_DPHY_SCRAM_CNTL
>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
>+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
>+//DP1_DP_DPHY_CRC_EN
>+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
>+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
>+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
>+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
>+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
>+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
>+//DP1_DP_DPHY_CRC_CNTL
>+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
>+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
>+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
>+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
>+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
>+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
>+//DP1_DP_DPHY_CRC_RESULT
>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
>+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
>+//DP1_DP_DPHY_CRC_MST_CNTL
>+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
>+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
>+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
>+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
>+//DP1_DP_DPHY_CRC_MST_STATUS
>+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
>+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
>+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
>+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
>+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
>+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
>+//DP1_DP_DPHY_FAST_TRAINING
>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
>+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
>+//DP1_DP_DPHY_FAST_TRAINING_STATUS
>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
>+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
>+//DP1_DP_SEC_CNTL
>+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
>+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
>+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
>+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
>+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
>+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
>+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
>+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
>+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
>+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
>+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
>+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
>+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
>+//DP1_DP_SEC_CNTL1
>+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
>+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
>+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP1_DP_SEC_FRAMING1
>+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
>+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
>+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
>+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
>+//DP1_DP_SEC_FRAMING2
>+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
>+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
>+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
>+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
>+//DP1_DP_SEC_FRAMING3
>+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
>+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
>+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
>+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
>+//DP1_DP_SEC_FRAMING4
>+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
>+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
>+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
>+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
>+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
>+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
>+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
>+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
>+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
>+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
>+//DP1_DP_SEC_AUD_N
>+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
>+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
>+//DP1_DP_SEC_AUD_N_READBACK
>+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
>+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
>+//DP1_DP_SEC_AUD_M
>+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
>+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
>+//DP1_DP_SEC_AUD_M_READBACK
>+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
>+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
>+//DP1_DP_SEC_TIMESTAMP
>+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
>+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
>+//DP1_DP_SEC_PACKET_CNTL
>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
>+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
>+//DP1_DP_MSE_RATE_CNTL
>+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
>+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
>+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
>+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
>+//DP1_DP_MSE_RATE_UPDATE
>+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
>+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
>+//DP1_DP_MSE_SAT0
>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
>+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
>+//DP1_DP_MSE_SAT1
>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
>+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
>+//DP1_DP_MSE_SAT2
>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
>+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
>+//DP1_DP_MSE_SAT_UPDATE
>+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
>+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
>+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
>+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
>+//DP1_DP_MSE_LINK_TIMING
>+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
>+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
>+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
>+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
>+//DP1_DP_MSE_MISC_CNTL
>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
>+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
>+//DP1_DP_DPHY_BS_SR_SWAP_CNTL
>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
>+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
>+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
>+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
>+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
>+//DP1_DP_MSE_SAT0_STATUS
>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
>+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
>+//DP1_DP_MSE_SAT1_STATUS
>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
>+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
>+//DP1_DP_MSE_SAT2_STATUS
>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
>+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
>+//DP1_DP_MSA_TIMING_PARAM1
>+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
>+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
>+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
>+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
>+//DP1_DP_MSA_TIMING_PARAM2
>+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
>+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
>+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
>+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
>+//DP1_DP_MSA_TIMING_PARAM3
>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
>+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
>+//DP1_DP_MSA_TIMING_PARAM4
>+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
>+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
>+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
>+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
>+//DP1_DP_MSO_CNTL
>+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
>+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
>+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
>+//DP1_DP_MSO_CNTL1
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
>+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
>+//DP1_DP_DSC_CNTL
>+#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
>+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
>+#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
>+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
>+//DP1_DP_SEC_CNTL2
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT                                                              0x1c
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
>+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK                                                                0x10000000L
>+//DP1_DP_SEC_CNTL3
>+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
>+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
>+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP1_DP_SEC_CNTL4
>+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
>+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
>+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP1_DP_SEC_CNTL5
>+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
>+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
>+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP1_DP_SEC_CNTL6
>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
>+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
>+//DP1_DP_SEC_CNTL7
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
>+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
>+//DP1_DP_DB_CNTL
>+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
>+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
>+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
>+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
>+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
>+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
>+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
>+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
>+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
>+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
>+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
>+//DP1_DP_MSA_VBID_MISC
>+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
>+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
>+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
>+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
>+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
>+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
>+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
>+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
>+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
>+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
>+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
>+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
>+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
>+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
>+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
>+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
>+//DP1_DP_SEC_METADATA_TRANSMISSION
>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
>+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
>+//DP1_DP_DSC_BYTES_PER_PIXEL
>+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
>+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
>+//DP1_DP_ALPM_CNTL
>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
>+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
>+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
>+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dio_dig2_dispdec
>+//DIG2_DIG_FE_CNTL
>+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
>+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
>+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
>+#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
>+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
>+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
>+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
>+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
>+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
>+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
>+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
>+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
>+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
>+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
>+#define DIG2_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
>+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
>+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
>+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
>+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
>+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
>+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
>+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
>+//DIG2_DIG_OUTPUT_CRC_CNTL
>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
>+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
>+//DIG2_DIG_OUTPUT_CRC_RESULT
>+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
>+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
>+//DIG2_DIG_CLOCK_PATTERN
>+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
>+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
>+//DIG2_DIG_TEST_PATTERN
>+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
>+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
>+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
>+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
>+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
>+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
>+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
>+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
>+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
>+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
>+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
>+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
>+//DIG2_DIG_RANDOM_PATTERN_SEED
>+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
>+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
>+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
>+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
>+//DIG2_DIG_FIFO_STATUS
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
>+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
>+//DIG2_HDMI_METADATA_PACKET_CONTROL
>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
>+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
>+//DIG2_HDMI_GENERIC_PACKET_CONTROL4
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
>+//DIG2_HDMI_CONTROL
>+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
>+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
>+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
>+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
>+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
>+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
>+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
>+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
>+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
>+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
>+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
>+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
>+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
>+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
>+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
>+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
>+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
>+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
>+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
>+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
>+//DIG2_HDMI_STATUS
>+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
>+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
>+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
>+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
>+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
>+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
>+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
>+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
>+//DIG2_HDMI_AUDIO_PACKET_CONTROL
>+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
>+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                    0x8
>+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                    0x10
>+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
>+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                      0x00000100L
>+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK                                      0x001F0000L
>+//DIG2_HDMI_ACR_PACKET_CONTROL
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
>+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
>+//DIG2_HDMI_VBI_PACKET_CONTROL
>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
>+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
>+//DIG2_HDMI_INFOFRAME_CONTROL0
>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
>+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
>+//DIG2_HDMI_INFOFRAME_CONTROL1
>+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
>+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
>+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
>+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
>+//DIG2_HDMI_GENERIC_PACKET_CONTROL0
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
>+//DIG2_HDMI_GC
>+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
>+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
>+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
>+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
>+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
>+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
>+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
>+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
>+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
>+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
>+//DIG2_AFMT_AUDIO_PACKET_CONTROL2
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                        0x0
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                      0x1
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                     0x8
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                       0x10
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                          0x18
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                           0x1c
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                          0x00000001L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                        0x00000002L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                       0x0000FF00L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                         0x00FF0000L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                            0x01000000L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                             0x10000000L
>+//DIG2_AFMT_ISRC1_0
>+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT                                                            0x0
>+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT                                                          0x6
>+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT                                                             0x7
>+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK                                                              0x00000007L
>+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK                                                            0x00000040L
>+#define DIG2_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK                                                               0x00000080L
>+//DIG2_AFMT_ISRC1_1
>+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT                                                          0x0
>+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT                                                          0x8
>+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT                                                          0x10
>+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT                                                          0x18
>+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK                                                            0x000000FFL
>+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK                                                            0x0000FF00L
>+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK                                                            0x00FF0000L
>+#define DIG2_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK                                                            0xFF000000L
>+//DIG2_AFMT_ISRC1_2
>+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT                                                          0x0
>+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT                                                          0x8
>+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT                                                          0x10
>+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT                                                          0x18
>+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK                                                            0x000000FFL
>+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK                                                            0x0000FF00L
>+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK                                                            0x00FF0000L
>+#define DIG2_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK                                                            0xFF000000L
>+//DIG2_AFMT_ISRC1_3
>+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT                                                          0x0
>+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT                                                          0x8
>+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT                                                         0x10
>+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT                                                         0x18
>+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK                                                            0x000000FFL
>+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK                                                            0x0000FF00L
>+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK                                                           0x00FF0000L
>+#define DIG2_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK                                                           0xFF000000L
>+//DIG2_AFMT_ISRC1_4
>+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT                                                         0x0
>+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT                                                         0x8
>+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT                                                         0x10
>+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT                                                         0x18
>+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK                                                           0x000000FFL
>+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK                                                           0x0000FF00L
>+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK                                                           0x00FF0000L
>+#define DIG2_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK                                                           0xFF000000L
>+//DIG2_AFMT_ISRC2_0
>+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT                                                         0x0
>+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT                                                         0x8
>+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT                                                         0x10
>+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT                                                         0x18
>+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK                                                           0x000000FFL
>+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK                                                           0x0000FF00L
>+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK                                                           0x00FF0000L
>+#define DIG2_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK                                                           0xFF000000L
>+//DIG2_AFMT_ISRC2_1
>+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT                                                         0x0
>+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT                                                         0x8
>+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT                                                         0x10
>+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT                                                         0x18
>+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK                                                           0x000000FFL
>+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK                                                           0x0000FF00L
>+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK                                                           0x00FF0000L
>+#define DIG2_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK                                                           0xFF000000L
>+//DIG2_AFMT_ISRC2_2
>+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT                                                         0x0
>+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT                                                         0x8
>+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT                                                         0x10
>+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT                                                         0x18
>+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK                                                           0x000000FFL
>+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK                                                           0x0000FF00L
>+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK                                                           0x00FF0000L
>+#define DIG2_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK                                                           0xFF000000L
>+//DIG2_AFMT_ISRC2_3
>+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT                                                         0x0
>+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT                                                         0x8
>+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT                                                         0x10
>+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT                                                         0x18
>+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK                                                           0x000000FFL
>+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK                                                           0x0000FF00L
>+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK                                                           0x00FF0000L
>+#define DIG2_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK                                                           0xFF000000L
>+//DIG2_HDMI_GENERIC_PACKET_CONTROL2
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
>+//DIG2_HDMI_GENERIC_PACKET_CONTROL3
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
>+//DIG2_HDMI_DB_CONTROL
>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
>+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
>+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
>+//DIG2_DME_CONTROL
>+#define DIG2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
>+#define DIG2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
>+#define DIG2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
>+#define DIG2_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
>+#define DIG2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
>+#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
>+#define DIG2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
>+#define DIG2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
>+#define DIG2_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
>+#define DIG2_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
>+#define DIG2_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
>+#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
>+#define DIG2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
>+#define DIG2_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
>+//DIG2_AFMT_MPEG_INFO0
>+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT                                                  0x0
>+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT                                                       0x8
>+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT                                                       0x10
>+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT                                                       0x18
>+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK                                                    0x000000FFL
>+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK                                                         0x0000FF00L
>+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK                                                         0x00FF0000L
>+#define DIG2_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK                                                         0xFF000000L
>+//DIG2_AFMT_MPEG_INFO1
>+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT                                                       0x0
>+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT                                                        0x8
>+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT                                                        0xc
>+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK                                                         0x000000FFL
>+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK                                                          0x00000300L
>+#define DIG2_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK                                                          0x00001000L
>+//DIG2_AFMT_GENERIC_HDR
>+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT                                                        0x0
>+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT                                                        0x8
>+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT                                                        0x10
>+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT                                                        0x18
>+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK                                                          0x000000FFL
>+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK                                                          0x0000FF00L
>+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK                                                          0x00FF0000L
>+#define DIG2_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK                                                          0xFF000000L
>+//DIG2_AFMT_GENERIC_0
>+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT                                                        0x0
>+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT                                                        0x8
>+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT                                                        0x10
>+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT                                                        0x18
>+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK                                                          0x000000FFL
>+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK                                                          0x0000FF00L
>+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK                                                          0x00FF0000L
>+#define DIG2_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK                                                          0xFF000000L
>+//DIG2_AFMT_GENERIC_1
>+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT                                                        0x0
>+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT                                                        0x8
>+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT                                                        0x10
>+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT                                                        0x18
>+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK                                                          0x000000FFL
>+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK                                                          0x0000FF00L
>+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK                                                          0x00FF0000L
>+#define DIG2_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK                                                          0xFF000000L
>+//DIG2_AFMT_GENERIC_2
>+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT                                                        0x0
>+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT                                                        0x8
>+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT                                                       0x10
>+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT                                                       0x18
>+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK                                                          0x000000FFL
>+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK                                                          0x0000FF00L
>+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK                                                         0x00FF0000L
>+#define DIG2_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK                                                         0xFF000000L
>+//DIG2_AFMT_GENERIC_3
>+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT                                                       0x0
>+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT                                                       0x8
>+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT                                                       0x10
>+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT                                                       0x18
>+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK                                                         0x000000FFL
>+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK                                                         0x0000FF00L
>+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK                                                         0x00FF0000L
>+#define DIG2_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK                                                         0xFF000000L
>+//DIG2_AFMT_GENERIC_4
>+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT                                                       0x0
>+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT                                                       0x8
>+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT                                                       0x10
>+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT                                                       0x18
>+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK                                                         0x000000FFL
>+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK                                                         0x0000FF00L
>+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK                                                         0x00FF0000L
>+#define DIG2_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK                                                         0xFF000000L
>+//DIG2_AFMT_GENERIC_5
>+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT                                                       0x0
>+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT                                                       0x8
>+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT                                                       0x10
>+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT                                                       0x18
>+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK                                                         0x000000FFL
>+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK                                                         0x0000FF00L
>+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK                                                         0x00FF0000L
>+#define DIG2_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK                                                         0xFF000000L
>+//DIG2_AFMT_GENERIC_6
>+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT                                                       0x0
>+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT                                                       0x8
>+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT                                                       0x10
>+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT                                                       0x18
>+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK                                                         0x000000FFL
>+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK                                                         0x0000FF00L
>+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK                                                         0x00FF0000L
>+#define DIG2_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK                                                         0xFF000000L
>+//DIG2_AFMT_GENERIC_7
>+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT                                                       0x0
>+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT                                                       0x8
>+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT                                                       0x10
>+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT                                                       0x18
>+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK                                                         0x000000FFL
>+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK                                                         0x0000FF00L
>+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK                                                         0x00FF0000L
>+#define DIG2_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK                                                         0xFF000000L
>+//DIG2_HDMI_GENERIC_PACKET_CONTROL1
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
>+//DIG2_HDMI_ACR_32_0
>+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
>+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
>+//DIG2_HDMI_ACR_32_1
>+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
>+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
>+//DIG2_HDMI_ACR_44_0
>+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
>+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
>+//DIG2_HDMI_ACR_44_1
>+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
>+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
>+//DIG2_HDMI_ACR_48_0
>+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
>+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
>+//DIG2_HDMI_ACR_48_1
>+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
>+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
>+//DIG2_HDMI_ACR_STATUS_0
>+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
>+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
>+//DIG2_HDMI_ACR_STATUS_1
>+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
>+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
>+//DIG2_AFMT_AUDIO_INFO0
>+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                                0x0
>+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                      0x8
>+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                      0xb
>+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                         0x10
>+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                     0x18
>+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                  0x000000FFL
>+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                        0x00000700L
>+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                        0x00007800L
>+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                           0x00FF0000L
>+#define DIG2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                       0x1F000000L
>+//DIG2_AFMT_AUDIO_INFO1
>+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                      0x0
>+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                     0xb
>+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                  0xf
>+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                  0x10
>+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                        0x000000FFL
>+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                       0x00007800L
>+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                    0x00008000L
>+#define DIG2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                    0x00030000L
>+//DIG2_AFMT_60958_0
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                             0x0
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                             0x1
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                             0x2
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                             0x3
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                          0x6
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                 0x8
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                 0x10
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                              0x14
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                            0x18
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                                0x1c
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                               0x00000001L
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                               0x00000002L
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                               0x00000004L
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                               0x00000038L
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                            0x000000C0L
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                   0x0000FF00L
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                   0x000F0000L
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                                0x00F00000L
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                              0x0F000000L
>+#define DIG2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                  0x30000000L
>+//DIG2_AFMT_60958_1
>+#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                   0x0
>+#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                   0x4
>+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                          0x10
>+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                          0x12
>+#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                              0x14
>+#define DIG2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                     0x0000000FL
>+#define DIG2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                     0x000000F0L
>+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                            0x00010000L
>+#define DIG2_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                            0x00040000L
>+#define DIG2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                                0x00F00000L
>+//DIG2_AFMT_AUDIO_CRC_CONTROL
>+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                 0x0
>+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                               0x4
>+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                             0x8
>+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                             0xc
>+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                              0x10
>+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                   0x00000001L
>+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                 0x00000010L
>+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                               0x00000100L
>+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                               0x0000F000L
>+#define DIG2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                                0xFFFF0000L
>+//DIG2_AFMT_RAMP_CONTROL0
>+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                   0x0
>+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                   0x1f
>+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                     0x00FFFFFFL
>+#define DIG2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                     0x80000000L
>+//DIG2_AFMT_RAMP_CONTROL1
>+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                   0x0
>+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                            0x18
>+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                     0x00FFFFFFL
>+#define DIG2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                              0xFF000000L
>+//DIG2_AFMT_RAMP_CONTROL2
>+#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                   0x0
>+#define DIG2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                     0x00FFFFFFL
>+//DIG2_AFMT_RAMP_CONTROL3
>+#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                   0x0
>+#define DIG2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                     0x00FFFFFFL
>+//DIG2_AFMT_60958_2
>+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                              0x0
>+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                              0x4
>+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                              0x8
>+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                              0xc
>+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                              0x10
>+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                              0x14
>+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                                0x0000000FL
>+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                                0x000000F0L
>+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                                0x00000F00L
>+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                                0x0000F000L
>+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                                0x000F0000L
>+#define DIG2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                                0x00F00000L
>+//DIG2_AFMT_AUDIO_CRC_RESULT
>+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                                0x0
>+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                     0x8
>+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                  0x00000001L
>+#define DIG2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                       0xFFFFFF00L
>+//DIG2_AFMT_STATUS
>+#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                            0x4
>+#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                           0x8
>+#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                     0x18
>+#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                     0x1e
>+#define DIG2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                              0x00000010L
>+#define DIG2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                             0x00000100L
>+#define DIG2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                       0x01000000L
>+#define DIG2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                       0x40000000L
>+//DIG2_AFMT_AUDIO_PACKET_CONTROL
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                         0x0
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                 0xb
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                             0xc
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                           0xe
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                   0x17
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                        0x18
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                           0x1a
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                   0x1e
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                                0x1f
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                           0x00000001L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                   0x00000800L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                               0x00001000L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                             0x00004000L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                     0x00800000L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                          0x01000000L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                             0x04000000L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                     0x40000000L
>+#define DIG2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                  0x80000000L
>+//DIG2_AFMT_VBI_PACKET_CONTROL
>+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT                                         0x8
>+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT                                            0x10
>+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT                                        0x11
>+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT                                               0x1c
>+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK                                           0x00000100L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK                                              0x00010000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK                                          0x00020000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK                                                 0xF0000000L
>+//DIG2_AFMT_INFOFRAME_CONTROL0
>+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                           0x6
>+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                           0x7
>+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT                                            0xa
>+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                             0x00000040L
>+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                             0x00000080L
>+#define DIG2_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK                                              0x00000400L
>+//DIG2_AFMT_AUDIO_SRC_CONTROL
>+#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                             0x0
>+#define DIG2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                               0x00000007L
>+//DIG2_DIG_BE_CNTL
>+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
>+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
>+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
>+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
>+#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
>+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
>+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
>+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
>+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
>+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
>+#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
>+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
>+//DIG2_DIG_BE_EN_CNTL
>+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
>+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
>+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
>+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
>+//DIG2_TMDS_CNTL
>+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
>+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
>+//DIG2_TMDS_CONTROL_CHAR
>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
>+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
>+//DIG2_TMDS_CONTROL0_FEEDBACK
>+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
>+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
>+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
>+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
>+//DIG2_TMDS_STEREOSYNC_CTL_SEL
>+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
>+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
>+//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1
>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
>+//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3
>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
>+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
>+//DIG2_TMDS_CTL_BITS
>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
>+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
>+//DIG2_TMDS_DCBALANCER_CONTROL
>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
>+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
>+//DIG2_TMDS_SYNC_DCBALANCE_CHAR
>+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
>+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
>+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
>+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
>+//DIG2_TMDS_CTL0_1_GEN_CNTL
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
>+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
>+//DIG2_TMDS_CTL2_3_GEN_CNTL
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
>+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
>+//DIG2_DIG_VERSION
>+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
>+#define DIG2_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
>+//DIG2_DIG_LANE_ENABLE
>+#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
>+#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
>+#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
>+#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
>+#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
>+#define DIG2_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
>+#define DIG2_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
>+#define DIG2_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
>+#define DIG2_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
>+#define DIG2_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
>+//DIG2_AFMT_CNTL
>+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
>+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
>+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
>+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
>+//DIG2_AFMT_VBI_PACKET_CONTROL1
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x1
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT                                  0x2
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x3
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT                                      0x4
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x5
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT                                  0x6
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x7
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT                                      0x8
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x9
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT                                  0xa
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xb
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT                                      0xc
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0xd
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT                                  0xe
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xf
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT                                      0x10
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x11
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT                                  0x12
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x13
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT                                      0x14
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT                                  0x16
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x17
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT                                      0x18
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x19
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT                                  0x1a
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1b
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT                                      0x1c
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x1d
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT                                  0x1e
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1f
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00000002L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK                                    0x00000004L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000008L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK                                        0x00000010L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00000020L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK                                    0x00000040L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000080L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK                                        0x00000100L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00000200L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK                                    0x00000400L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000800L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK                                        0x00001000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00002000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK                                    0x00004000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                            0x00008000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK                                        0x00010000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00020000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK                                    0x00040000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                            0x00080000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK                                        0x00100000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK                                    0x00400000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                            0x00800000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK                                        0x01000000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x02000000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK                                    0x04000000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                            0x08000000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK                                        0x10000000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x20000000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK                                    0x40000000L
>+#define DIG2_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                            0x80000000L
>+//DIG2_HDMI_GENERIC_PACKET_CONTROL5
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
>+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
>+//DIG2_FORCE_DIG_DISABLE
>+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
>+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
>+
>+
>+// addressBlock: dce_dc_dio_dp2_dispdec
>+//DP2_DP_LINK_CNTL
>+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
>+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
>+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
>+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
>+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
>+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
>+//DP2_DP_PIXEL_FORMAT
>+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
>+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
>+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
>+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
>+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
>+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
>+//DP2_DP_MSA_COLORIMETRY
>+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
>+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
>+//DP2_DP_CONFIG
>+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
>+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
>+//DP2_DP_VID_STREAM_CNTL
>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
>+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
>+//DP2_DP_STEER_FIFO
>+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
>+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
>+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
>+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
>+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
>+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
>+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
>+//DP2_DP_MSA_MISC
>+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
>+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
>+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
>+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
>+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
>+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
>+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
>+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
>+//DP2_DP_VID_TIMING
>+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
>+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
>+#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
>+#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
>+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
>+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
>+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
>+#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
>+#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
>+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
>+//DP2_DP_VID_N
>+#define DP2_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
>+#define DP2_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
>+//DP2_DP_VID_M
>+#define DP2_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
>+#define DP2_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
>+//DP2_DP_LINK_FRAMING_CNTL
>+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
>+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
>+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
>+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
>+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
>+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
>+//DP2_DP_HBR2_EYE_PATTERN
>+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
>+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
>+//DP2_DP_VID_MSA_VBID
>+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
>+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
>+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
>+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
>+//DP2_DP_VID_INTERRUPT_CNTL
>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
>+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
>+//DP2_DP_DPHY_CNTL
>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
>+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
>+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
>+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
>+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
>+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
>+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
>+//DP2_DP_DPHY_TRAINING_PATTERN_SEL
>+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
>+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
>+//DP2_DP_DPHY_SYM0
>+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
>+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
>+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
>+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
>+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
>+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
>+//DP2_DP_DPHY_SYM1
>+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
>+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
>+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
>+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
>+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
>+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
>+//DP2_DP_DPHY_SYM2
>+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
>+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
>+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
>+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
>+//DP2_DP_DPHY_8B10B_CNTL
>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
>+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
>+//DP2_DP_DPHY_PRBS_CNTL
>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
>+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
>+//DP2_DP_DPHY_SCRAM_CNTL
>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
>+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
>+//DP2_DP_DPHY_CRC_EN
>+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
>+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
>+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
>+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
>+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
>+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
>+//DP2_DP_DPHY_CRC_CNTL
>+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
>+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
>+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
>+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
>+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
>+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
>+//DP2_DP_DPHY_CRC_RESULT
>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
>+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
>+//DP2_DP_DPHY_CRC_MST_CNTL
>+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
>+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
>+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
>+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
>+//DP2_DP_DPHY_CRC_MST_STATUS
>+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
>+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
>+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
>+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
>+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
>+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
>+//DP2_DP_DPHY_FAST_TRAINING
>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
>+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
>+//DP2_DP_DPHY_FAST_TRAINING_STATUS
>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
>+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
>+//DP2_DP_SEC_CNTL
>+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
>+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
>+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
>+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
>+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
>+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
>+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
>+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
>+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
>+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
>+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
>+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
>+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
>+//DP2_DP_SEC_CNTL1
>+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
>+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
>+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP2_DP_SEC_FRAMING1
>+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
>+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
>+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
>+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
>+//DP2_DP_SEC_FRAMING2
>+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
>+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
>+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
>+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
>+//DP2_DP_SEC_FRAMING3
>+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
>+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
>+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
>+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
>+//DP2_DP_SEC_FRAMING4
>+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
>+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
>+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
>+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
>+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
>+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
>+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
>+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
>+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
>+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
>+//DP2_DP_SEC_AUD_N
>+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
>+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
>+//DP2_DP_SEC_AUD_N_READBACK
>+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
>+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
>+//DP2_DP_SEC_AUD_M
>+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
>+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
>+//DP2_DP_SEC_AUD_M_READBACK
>+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
>+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
>+//DP2_DP_SEC_TIMESTAMP
>+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
>+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
>+//DP2_DP_SEC_PACKET_CNTL
>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
>+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
>+//DP2_DP_MSE_RATE_CNTL
>+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
>+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
>+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
>+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
>+//DP2_DP_MSE_RATE_UPDATE
>+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
>+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
>+//DP2_DP_MSE_SAT0
>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
>+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
>+//DP2_DP_MSE_SAT1
>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
>+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
>+//DP2_DP_MSE_SAT2
>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
>+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
>+//DP2_DP_MSE_SAT_UPDATE
>+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
>+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
>+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
>+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
>+//DP2_DP_MSE_LINK_TIMING
>+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
>+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
>+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
>+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
>+//DP2_DP_MSE_MISC_CNTL
>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
>+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
>+//DP2_DP_DPHY_BS_SR_SWAP_CNTL
>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
>+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
>+//DP2_DP_DPHY_HBR2_PATTERN_CONTROL
>+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
>+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
>+//DP2_DP_MSE_SAT0_STATUS
>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
>+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
>+//DP2_DP_MSE_SAT1_STATUS
>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
>+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
>+//DP2_DP_MSE_SAT2_STATUS
>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
>+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
>+//DP2_DP_MSA_TIMING_PARAM1
>+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
>+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
>+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
>+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
>+//DP2_DP_MSA_TIMING_PARAM2
>+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
>+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
>+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
>+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
>+//DP2_DP_MSA_TIMING_PARAM3
>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
>+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
>+//DP2_DP_MSA_TIMING_PARAM4
>+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
>+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
>+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
>+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
>+//DP2_DP_MSO_CNTL
>+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
>+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
>+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
>+//DP2_DP_MSO_CNTL1
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
>+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
>+//DP2_DP_DSC_CNTL
>+#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
>+#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
>+#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
>+#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
>+//DP2_DP_SEC_CNTL2
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT                                                              0x1c
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
>+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK                                                                0x10000000L
>+//DP2_DP_SEC_CNTL3
>+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
>+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
>+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP2_DP_SEC_CNTL4
>+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
>+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
>+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP2_DP_SEC_CNTL5
>+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
>+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
>+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP2_DP_SEC_CNTL6
>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
>+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
>+//DP2_DP_SEC_CNTL7
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
>+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
>+//DP2_DP_DB_CNTL
>+#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
>+#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
>+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
>+#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
>+#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
>+#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
>+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
>+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
>+#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
>+#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
>+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
>+//DP2_DP_MSA_VBID_MISC
>+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
>+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
>+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
>+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
>+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
>+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
>+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
>+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
>+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
>+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
>+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
>+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
>+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
>+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
>+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
>+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
>+//DP2_DP_SEC_METADATA_TRANSMISSION
>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
>+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
>+//DP2_DP_DSC_BYTES_PER_PIXEL
>+#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
>+#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
>+//DP2_DP_ALPM_CNTL
>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
>+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
>+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
>+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dio_dig3_dispdec
>+//DIG3_DIG_FE_CNTL
>+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
>+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
>+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
>+#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
>+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
>+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
>+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
>+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
>+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
>+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
>+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
>+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
>+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
>+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
>+#define DIG3_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
>+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
>+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
>+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
>+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
>+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
>+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
>+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
>+//DIG3_DIG_OUTPUT_CRC_CNTL
>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
>+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
>+//DIG3_DIG_OUTPUT_CRC_RESULT
>+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
>+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
>+//DIG3_DIG_CLOCK_PATTERN
>+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
>+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
>+//DIG3_DIG_TEST_PATTERN
>+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
>+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
>+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
>+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
>+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
>+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
>+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
>+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
>+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
>+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
>+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
>+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
>+//DIG3_DIG_RANDOM_PATTERN_SEED
>+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
>+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
>+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
>+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
>+//DIG3_DIG_FIFO_STATUS
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
>+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
>+//DIG3_HDMI_METADATA_PACKET_CONTROL
>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
>+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
>+//DIG3_HDMI_GENERIC_PACKET_CONTROL4
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
>+//DIG3_HDMI_CONTROL
>+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
>+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
>+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
>+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
>+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
>+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
>+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
>+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
>+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
>+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
>+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
>+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
>+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
>+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
>+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
>+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
>+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
>+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
>+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
>+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
>+//DIG3_HDMI_STATUS
>+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
>+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
>+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
>+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
>+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
>+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
>+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
>+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
>+//DIG3_HDMI_AUDIO_PACKET_CONTROL
>+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
>+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                    0x8
>+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                    0x10
>+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
>+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                      0x00000100L
>+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK                                      0x001F0000L
>+//DIG3_HDMI_ACR_PACKET_CONTROL
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
>+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
>+//DIG3_HDMI_VBI_PACKET_CONTROL
>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
>+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
>+//DIG3_HDMI_INFOFRAME_CONTROL0
>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
>+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
>+//DIG3_HDMI_INFOFRAME_CONTROL1
>+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
>+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
>+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
>+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
>+//DIG3_HDMI_GENERIC_PACKET_CONTROL0
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
>+//DIG3_HDMI_GC
>+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
>+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
>+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
>+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
>+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
>+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
>+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
>+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
>+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
>+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
>+//DIG3_AFMT_AUDIO_PACKET_CONTROL2
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                        0x0
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                      0x1
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                     0x8
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                       0x10
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                          0x18
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                           0x1c
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                          0x00000001L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                        0x00000002L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                       0x0000FF00L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                         0x00FF0000L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                            0x01000000L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                             0x10000000L
>+//DIG3_AFMT_ISRC1_0
>+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT                                                            0x0
>+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT                                                          0x6
>+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT                                                             0x7
>+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK                                                              0x00000007L
>+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK                                                            0x00000040L
>+#define DIG3_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK                                                               0x00000080L
>+//DIG3_AFMT_ISRC1_1
>+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT                                                          0x0
>+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT                                                          0x8
>+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT                                                          0x10
>+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT                                                          0x18
>+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK                                                            0x000000FFL
>+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK                                                            0x0000FF00L
>+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK                                                            0x00FF0000L
>+#define DIG3_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK                                                            0xFF000000L
>+//DIG3_AFMT_ISRC1_2
>+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT                                                          0x0
>+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT                                                          0x8
>+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT                                                          0x10
>+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT                                                          0x18
>+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK                                                            0x000000FFL
>+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK                                                            0x0000FF00L
>+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK                                                            0x00FF0000L
>+#define DIG3_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK                                                            0xFF000000L
>+//DIG3_AFMT_ISRC1_3
>+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT                                                          0x0
>+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT                                                          0x8
>+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT                                                         0x10
>+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT                                                         0x18
>+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK                                                            0x000000FFL
>+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK                                                            0x0000FF00L
>+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK                                                           0x00FF0000L
>+#define DIG3_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK                                                           0xFF000000L
>+//DIG3_AFMT_ISRC1_4
>+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT                                                         0x0
>+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT                                                         0x8
>+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT                                                         0x10
>+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT                                                         0x18
>+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK                                                           0x000000FFL
>+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK                                                           0x0000FF00L
>+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK                                                           0x00FF0000L
>+#define DIG3_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK                                                           0xFF000000L
>+//DIG3_AFMT_ISRC2_0
>+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT                                                         0x0
>+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT                                                         0x8
>+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT                                                         0x10
>+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT                                                         0x18
>+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK                                                           0x000000FFL
>+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK                                                           0x0000FF00L
>+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK                                                           0x00FF0000L
>+#define DIG3_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK                                                           0xFF000000L
>+//DIG3_AFMT_ISRC2_1
>+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT                                                         0x0
>+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT                                                         0x8
>+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT                                                         0x10
>+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT                                                         0x18
>+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK                                                           0x000000FFL
>+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK                                                           0x0000FF00L
>+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK                                                           0x00FF0000L
>+#define DIG3_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK                                                           0xFF000000L
>+//DIG3_AFMT_ISRC2_2
>+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT                                                         0x0
>+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT                                                         0x8
>+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT                                                         0x10
>+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT                                                         0x18
>+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK                                                           0x000000FFL
>+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK                                                           0x0000FF00L
>+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK                                                           0x00FF0000L
>+#define DIG3_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK                                                           0xFF000000L
>+//DIG3_AFMT_ISRC2_3
>+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT                                                         0x0
>+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT                                                         0x8
>+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT                                                         0x10
>+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT                                                         0x18
>+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK                                                           0x000000FFL
>+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK                                                           0x0000FF00L
>+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK                                                           0x00FF0000L
>+#define DIG3_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK                                                           0xFF000000L
>+//DIG3_HDMI_GENERIC_PACKET_CONTROL2
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
>+//DIG3_HDMI_GENERIC_PACKET_CONTROL3
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
>+//DIG3_HDMI_DB_CONTROL
>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
>+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
>+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
>+//DIG3_DME_CONTROL
>+#define DIG3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
>+#define DIG3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
>+#define DIG3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
>+#define DIG3_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
>+#define DIG3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
>+#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
>+#define DIG3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
>+#define DIG3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
>+#define DIG3_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
>+#define DIG3_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
>+#define DIG3_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
>+#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
>+#define DIG3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
>+#define DIG3_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
>+//DIG3_AFMT_MPEG_INFO0
>+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT                                                  0x0
>+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT                                                       0x8
>+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT                                                       0x10
>+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT                                                       0x18
>+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK                                                    0x000000FFL
>+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK                                                         0x0000FF00L
>+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK                                                         0x00FF0000L
>+#define DIG3_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK                                                         0xFF000000L
>+//DIG3_AFMT_MPEG_INFO1
>+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT                                                       0x0
>+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT                                                        0x8
>+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT                                                        0xc
>+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK                                                         0x000000FFL
>+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK                                                          0x00000300L
>+#define DIG3_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK                                                          0x00001000L
>+//DIG3_AFMT_GENERIC_HDR
>+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT                                                        0x0
>+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT                                                        0x8
>+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT                                                        0x10
>+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT                                                        0x18
>+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK                                                          0x000000FFL
>+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK                                                          0x0000FF00L
>+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK                                                          0x00FF0000L
>+#define DIG3_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK                                                          0xFF000000L
>+//DIG3_AFMT_GENERIC_0
>+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT                                                        0x0
>+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT                                                        0x8
>+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT                                                        0x10
>+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT                                                        0x18
>+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK                                                          0x000000FFL
>+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK                                                          0x0000FF00L
>+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK                                                          0x00FF0000L
>+#define DIG3_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK                                                          0xFF000000L
>+//DIG3_AFMT_GENERIC_1
>+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT                                                        0x0
>+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT                                                        0x8
>+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT                                                        0x10
>+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT                                                        0x18
>+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK                                                          0x000000FFL
>+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK                                                          0x0000FF00L
>+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK                                                          0x00FF0000L
>+#define DIG3_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK                                                          0xFF000000L
>+//DIG3_AFMT_GENERIC_2
>+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT                                                        0x0
>+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT                                                        0x8
>+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT                                                       0x10
>+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT                                                       0x18
>+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK                                                          0x000000FFL
>+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK                                                          0x0000FF00L
>+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK                                                         0x00FF0000L
>+#define DIG3_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK                                                         0xFF000000L
>+//DIG3_AFMT_GENERIC_3
>+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT                                                       0x0
>+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT                                                       0x8
>+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT                                                       0x10
>+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT                                                       0x18
>+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK                                                         0x000000FFL
>+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK                                                         0x0000FF00L
>+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK                                                         0x00FF0000L
>+#define DIG3_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK                                                         0xFF000000L
>+//DIG3_AFMT_GENERIC_4
>+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT                                                       0x0
>+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT                                                       0x8
>+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT                                                       0x10
>+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT                                                       0x18
>+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK                                                         0x000000FFL
>+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK                                                         0x0000FF00L
>+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK                                                         0x00FF0000L
>+#define DIG3_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK                                                         0xFF000000L
>+//DIG3_AFMT_GENERIC_5
>+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT                                                       0x0
>+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT                                                       0x8
>+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT                                                       0x10
>+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT                                                       0x18
>+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK                                                         0x000000FFL
>+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK                                                         0x0000FF00L
>+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK                                                         0x00FF0000L
>+#define DIG3_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK                                                         0xFF000000L
>+//DIG3_AFMT_GENERIC_6
>+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT                                                       0x0
>+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT                                                       0x8
>+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT                                                       0x10
>+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT                                                       0x18
>+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK                                                         0x000000FFL
>+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK                                                         0x0000FF00L
>+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK                                                         0x00FF0000L
>+#define DIG3_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK                                                         0xFF000000L
>+//DIG3_AFMT_GENERIC_7
>+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT                                                       0x0
>+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT                                                       0x8
>+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT                                                       0x10
>+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT                                                       0x18
>+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK                                                         0x000000FFL
>+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK                                                         0x0000FF00L
>+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK                                                         0x00FF0000L
>+#define DIG3_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK                                                         0xFF000000L
>+//DIG3_HDMI_GENERIC_PACKET_CONTROL1
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
>+//DIG3_HDMI_ACR_32_0
>+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
>+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
>+//DIG3_HDMI_ACR_32_1
>+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
>+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
>+//DIG3_HDMI_ACR_44_0
>+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
>+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
>+//DIG3_HDMI_ACR_44_1
>+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
>+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
>+//DIG3_HDMI_ACR_48_0
>+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
>+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
>+//DIG3_HDMI_ACR_48_1
>+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
>+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
>+//DIG3_HDMI_ACR_STATUS_0
>+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
>+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
>+//DIG3_HDMI_ACR_STATUS_1
>+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
>+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
>+//DIG3_AFMT_AUDIO_INFO0
>+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                                0x0
>+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                      0x8
>+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                      0xb
>+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                         0x10
>+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                     0x18
>+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                  0x000000FFL
>+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                        0x00000700L
>+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                        0x00007800L
>+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                           0x00FF0000L
>+#define DIG3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                       0x1F000000L
>+//DIG3_AFMT_AUDIO_INFO1
>+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                      0x0
>+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                     0xb
>+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                  0xf
>+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                  0x10
>+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                        0x000000FFL
>+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                       0x00007800L
>+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                    0x00008000L
>+#define DIG3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                    0x00030000L
>+//DIG3_AFMT_60958_0
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                             0x0
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                             0x1
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                             0x2
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                             0x3
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                          0x6
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                 0x8
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                 0x10
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                              0x14
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                            0x18
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                                0x1c
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                               0x00000001L
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                               0x00000002L
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                               0x00000004L
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                               0x00000038L
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                            0x000000C0L
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                   0x0000FF00L
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                   0x000F0000L
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                                0x00F00000L
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                              0x0F000000L
>+#define DIG3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                  0x30000000L
>+//DIG3_AFMT_60958_1
>+#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                   0x0
>+#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                   0x4
>+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                          0x10
>+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                          0x12
>+#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                              0x14
>+#define DIG3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                     0x0000000FL
>+#define DIG3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                     0x000000F0L
>+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                            0x00010000L
>+#define DIG3_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                            0x00040000L
>+#define DIG3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                                0x00F00000L
>+//DIG3_AFMT_AUDIO_CRC_CONTROL
>+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                 0x0
>+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                               0x4
>+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                             0x8
>+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                             0xc
>+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                              0x10
>+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                   0x00000001L
>+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                 0x00000010L
>+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                               0x00000100L
>+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                               0x0000F000L
>+#define DIG3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                                0xFFFF0000L
>+//DIG3_AFMT_RAMP_CONTROL0
>+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                   0x0
>+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                   0x1f
>+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                     0x00FFFFFFL
>+#define DIG3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                     0x80000000L
>+//DIG3_AFMT_RAMP_CONTROL1
>+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                   0x0
>+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                            0x18
>+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                     0x00FFFFFFL
>+#define DIG3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                              0xFF000000L
>+//DIG3_AFMT_RAMP_CONTROL2
>+#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                   0x0
>+#define DIG3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                     0x00FFFFFFL
>+//DIG3_AFMT_RAMP_CONTROL3
>+#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                   0x0
>+#define DIG3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                     0x00FFFFFFL
>+//DIG3_AFMT_60958_2
>+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                              0x0
>+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                              0x4
>+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                              0x8
>+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                              0xc
>+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                              0x10
>+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                              0x14
>+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                                0x0000000FL
>+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                                0x000000F0L
>+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                                0x00000F00L
>+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                                0x0000F000L
>+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                                0x000F0000L
>+#define DIG3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                                0x00F00000L
>+//DIG3_AFMT_AUDIO_CRC_RESULT
>+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                                0x0
>+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                     0x8
>+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                  0x00000001L
>+#define DIG3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                       0xFFFFFF00L
>+//DIG3_AFMT_STATUS
>+#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                            0x4
>+#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                           0x8
>+#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                     0x18
>+#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                     0x1e
>+#define DIG3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                              0x00000010L
>+#define DIG3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                             0x00000100L
>+#define DIG3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                       0x01000000L
>+#define DIG3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                       0x40000000L
>+//DIG3_AFMT_AUDIO_PACKET_CONTROL
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                         0x0
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                 0xb
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                             0xc
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                           0xe
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                   0x17
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                        0x18
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                           0x1a
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                   0x1e
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                                0x1f
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                           0x00000001L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                   0x00000800L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                               0x00001000L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                             0x00004000L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                     0x00800000L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                          0x01000000L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                             0x04000000L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                     0x40000000L
>+#define DIG3_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                  0x80000000L
>+//DIG3_AFMT_VBI_PACKET_CONTROL
>+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT                                         0x8
>+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT                                            0x10
>+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT                                        0x11
>+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT                                               0x1c
>+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK                                           0x00000100L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK                                              0x00010000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK                                          0x00020000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK                                                 0xF0000000L
>+//DIG3_AFMT_INFOFRAME_CONTROL0
>+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                           0x6
>+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                           0x7
>+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT                                            0xa
>+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                             0x00000040L
>+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                             0x00000080L
>+#define DIG3_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK                                              0x00000400L
>+//DIG3_AFMT_AUDIO_SRC_CONTROL
>+#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                             0x0
>+#define DIG3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                               0x00000007L
>+//DIG3_DIG_BE_CNTL
>+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
>+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
>+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
>+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
>+#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
>+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
>+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
>+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
>+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
>+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
>+#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
>+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
>+//DIG3_DIG_BE_EN_CNTL
>+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
>+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
>+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
>+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
>+//DIG3_TMDS_CNTL
>+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
>+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
>+//DIG3_TMDS_CONTROL_CHAR
>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
>+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
>+//DIG3_TMDS_CONTROL0_FEEDBACK
>+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
>+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
>+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
>+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
>+//DIG3_TMDS_STEREOSYNC_CTL_SEL
>+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
>+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
>+//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1
>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
>+//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3
>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
>+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
>+//DIG3_TMDS_CTL_BITS
>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
>+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
>+//DIG3_TMDS_DCBALANCER_CONTROL
>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
>+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
>+//DIG3_TMDS_SYNC_DCBALANCE_CHAR
>+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
>+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
>+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
>+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
>+//DIG3_TMDS_CTL0_1_GEN_CNTL
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
>+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
>+//DIG3_TMDS_CTL2_3_GEN_CNTL
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
>+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
>+//DIG3_DIG_VERSION
>+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
>+#define DIG3_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
>+//DIG3_DIG_LANE_ENABLE
>+#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
>+#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
>+#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
>+#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
>+#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
>+#define DIG3_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
>+#define DIG3_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
>+#define DIG3_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
>+#define DIG3_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
>+#define DIG3_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
>+//DIG3_AFMT_CNTL
>+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
>+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
>+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
>+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
>+//DIG3_AFMT_VBI_PACKET_CONTROL1
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x1
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT                                  0x2
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x3
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT                                      0x4
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x5
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT                                  0x6
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x7
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT                                      0x8
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x9
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT                                  0xa
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xb
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT                                      0xc
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0xd
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT                                  0xe
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xf
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT                                      0x10
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x11
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT                                  0x12
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x13
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT                                      0x14
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT                                  0x16
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x17
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT                                      0x18
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x19
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT                                  0x1a
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1b
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT                                      0x1c
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x1d
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT                                  0x1e
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1f
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00000002L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK                                    0x00000004L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000008L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK                                        0x00000010L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00000020L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK                                    0x00000040L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000080L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK                                        0x00000100L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00000200L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK                                    0x00000400L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000800L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK                                        0x00001000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00002000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK                                    0x00004000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                            0x00008000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK                                        0x00010000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00020000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK                                    0x00040000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                            0x00080000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK                                        0x00100000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK                                    0x00400000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                            0x00800000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK                                        0x01000000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x02000000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK                                    0x04000000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                            0x08000000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK                                        0x10000000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x20000000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK                                    0x40000000L
>+#define DIG3_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                            0x80000000L
>+//DIG3_HDMI_GENERIC_PACKET_CONTROL5
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
>+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
>+//DIG3_FORCE_DIG_DISABLE
>+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
>+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
>+
>+
>+// addressBlock: dce_dc_dio_dp3_dispdec
>+//DP3_DP_LINK_CNTL
>+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
>+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
>+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
>+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
>+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
>+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
>+//DP3_DP_PIXEL_FORMAT
>+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
>+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
>+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
>+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
>+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
>+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
>+//DP3_DP_MSA_COLORIMETRY
>+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
>+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
>+//DP3_DP_CONFIG
>+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
>+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
>+//DP3_DP_VID_STREAM_CNTL
>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
>+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
>+//DP3_DP_STEER_FIFO
>+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
>+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
>+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
>+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
>+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
>+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
>+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
>+//DP3_DP_MSA_MISC
>+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
>+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
>+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
>+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
>+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
>+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
>+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
>+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
>+//DP3_DP_VID_TIMING
>+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
>+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
>+#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
>+#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
>+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
>+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
>+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
>+#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
>+#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
>+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
>+//DP3_DP_VID_N
>+#define DP3_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
>+#define DP3_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
>+//DP3_DP_VID_M
>+#define DP3_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
>+#define DP3_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
>+//DP3_DP_LINK_FRAMING_CNTL
>+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
>+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
>+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
>+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
>+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
>+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
>+//DP3_DP_HBR2_EYE_PATTERN
>+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
>+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
>+//DP3_DP_VID_MSA_VBID
>+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
>+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
>+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
>+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
>+//DP3_DP_VID_INTERRUPT_CNTL
>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
>+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
>+//DP3_DP_DPHY_CNTL
>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
>+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
>+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
>+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
>+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
>+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
>+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
>+//DP3_DP_DPHY_TRAINING_PATTERN_SEL
>+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
>+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
>+//DP3_DP_DPHY_SYM0
>+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
>+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
>+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
>+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
>+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
>+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
>+//DP3_DP_DPHY_SYM1
>+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
>+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
>+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
>+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
>+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
>+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
>+//DP3_DP_DPHY_SYM2
>+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
>+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
>+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
>+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
>+//DP3_DP_DPHY_8B10B_CNTL
>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
>+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
>+//DP3_DP_DPHY_PRBS_CNTL
>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
>+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
>+//DP3_DP_DPHY_SCRAM_CNTL
>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
>+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
>+//DP3_DP_DPHY_CRC_EN
>+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
>+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
>+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
>+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
>+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
>+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
>+//DP3_DP_DPHY_CRC_CNTL
>+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
>+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
>+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
>+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
>+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
>+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
>+//DP3_DP_DPHY_CRC_RESULT
>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
>+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
>+//DP3_DP_DPHY_CRC_MST_CNTL
>+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
>+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
>+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
>+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
>+//DP3_DP_DPHY_CRC_MST_STATUS
>+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
>+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
>+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
>+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
>+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
>+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
>+//DP3_DP_DPHY_FAST_TRAINING
>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
>+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
>+//DP3_DP_DPHY_FAST_TRAINING_STATUS
>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
>+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
>+//DP3_DP_SEC_CNTL
>+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
>+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
>+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
>+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
>+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
>+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
>+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
>+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
>+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
>+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
>+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
>+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
>+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
>+//DP3_DP_SEC_CNTL1
>+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
>+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
>+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP3_DP_SEC_FRAMING1
>+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
>+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
>+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
>+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
>+//DP3_DP_SEC_FRAMING2
>+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
>+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
>+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
>+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
>+//DP3_DP_SEC_FRAMING3
>+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
>+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
>+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
>+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
>+//DP3_DP_SEC_FRAMING4
>+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
>+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
>+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
>+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
>+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
>+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
>+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
>+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
>+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
>+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
>+//DP3_DP_SEC_AUD_N
>+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
>+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
>+//DP3_DP_SEC_AUD_N_READBACK
>+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
>+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
>+//DP3_DP_SEC_AUD_M
>+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
>+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
>+//DP3_DP_SEC_AUD_M_READBACK
>+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
>+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
>+//DP3_DP_SEC_TIMESTAMP
>+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
>+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
>+//DP3_DP_SEC_PACKET_CNTL
>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
>+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
>+//DP3_DP_MSE_RATE_CNTL
>+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
>+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
>+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
>+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
>+//DP3_DP_MSE_RATE_UPDATE
>+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
>+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
>+//DP3_DP_MSE_SAT0
>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
>+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
>+//DP3_DP_MSE_SAT1
>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
>+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
>+//DP3_DP_MSE_SAT2
>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
>+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
>+//DP3_DP_MSE_SAT_UPDATE
>+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
>+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
>+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
>+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
>+//DP3_DP_MSE_LINK_TIMING
>+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
>+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
>+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
>+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
>+//DP3_DP_MSE_MISC_CNTL
>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
>+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
>+//DP3_DP_DPHY_BS_SR_SWAP_CNTL
>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
>+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
>+//DP3_DP_DPHY_HBR2_PATTERN_CONTROL
>+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
>+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
>+//DP3_DP_MSE_SAT0_STATUS
>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
>+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
>+//DP3_DP_MSE_SAT1_STATUS
>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
>+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
>+//DP3_DP_MSE_SAT2_STATUS
>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
>+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
>+//DP3_DP_MSA_TIMING_PARAM1
>+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
>+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
>+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
>+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
>+//DP3_DP_MSA_TIMING_PARAM2
>+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
>+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
>+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
>+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
>+//DP3_DP_MSA_TIMING_PARAM3
>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
>+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
>+//DP3_DP_MSA_TIMING_PARAM4
>+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
>+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
>+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
>+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
>+//DP3_DP_MSO_CNTL
>+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
>+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
>+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
>+//DP3_DP_MSO_CNTL1
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
>+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
>+//DP3_DP_DSC_CNTL
>+#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
>+#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
>+#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
>+#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
>+//DP3_DP_SEC_CNTL2
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT                                                              0x1c
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
>+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK                                                                0x10000000L
>+//DP3_DP_SEC_CNTL3
>+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
>+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
>+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP3_DP_SEC_CNTL4
>+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
>+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
>+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP3_DP_SEC_CNTL5
>+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
>+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
>+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP3_DP_SEC_CNTL6
>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
>+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
>+//DP3_DP_SEC_CNTL7
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
>+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
>+//DP3_DP_DB_CNTL
>+#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
>+#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
>+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
>+#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
>+#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
>+#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
>+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
>+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
>+#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
>+#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
>+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
>+//DP3_DP_MSA_VBID_MISC
>+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
>+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
>+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
>+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
>+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
>+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
>+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
>+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
>+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
>+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
>+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
>+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
>+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
>+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
>+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
>+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
>+//DP3_DP_SEC_METADATA_TRANSMISSION
>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
>+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
>+//DP3_DP_DSC_BYTES_PER_PIXEL
>+#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
>+#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
>+//DP3_DP_ALPM_CNTL
>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
>+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
>+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
>+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dio_dig4_dispdec
>+//DIG4_DIG_FE_CNTL
>+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
>+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
>+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
>+#define DIG4_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
>+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
>+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
>+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
>+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
>+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
>+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
>+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
>+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
>+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
>+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
>+#define DIG4_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
>+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
>+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
>+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
>+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
>+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
>+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
>+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
>+//DIG4_DIG_OUTPUT_CRC_CNTL
>+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
>+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
>+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
>+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
>+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
>+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
>+//DIG4_DIG_OUTPUT_CRC_RESULT
>+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
>+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
>+//DIG4_DIG_CLOCK_PATTERN
>+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
>+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
>+//DIG4_DIG_TEST_PATTERN
>+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
>+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
>+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
>+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
>+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
>+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
>+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
>+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
>+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
>+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
>+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
>+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
>+//DIG4_DIG_RANDOM_PATTERN_SEED
>+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
>+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
>+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
>+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
>+//DIG4_DIG_FIFO_STATUS
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
>+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
>+//DIG4_HDMI_METADATA_PACKET_CONTROL
>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
>+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
>+//DIG4_HDMI_GENERIC_PACKET_CONTROL4
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
>+//DIG4_HDMI_CONTROL
>+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
>+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
>+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
>+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
>+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
>+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
>+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
>+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
>+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
>+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
>+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
>+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
>+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
>+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
>+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
>+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
>+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
>+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
>+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
>+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
>+//DIG4_HDMI_STATUS
>+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
>+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
>+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
>+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
>+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
>+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
>+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
>+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
>+//DIG4_HDMI_AUDIO_PACKET_CONTROL
>+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
>+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                    0x8
>+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                    0x10
>+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
>+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                      0x00000100L
>+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK                                      0x001F0000L
>+//DIG4_HDMI_ACR_PACKET_CONTROL
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
>+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
>+//DIG4_HDMI_VBI_PACKET_CONTROL
>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
>+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
>+//DIG4_HDMI_INFOFRAME_CONTROL0
>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
>+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
>+//DIG4_HDMI_INFOFRAME_CONTROL1
>+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
>+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
>+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
>+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
>+//DIG4_HDMI_GENERIC_PACKET_CONTROL0
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
>+//DIG4_HDMI_GC
>+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
>+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
>+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
>+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
>+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
>+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
>+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
>+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
>+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
>+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
>+//DIG4_AFMT_AUDIO_PACKET_CONTROL2
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                        0x0
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                      0x1
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                     0x8
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                       0x10
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                          0x18
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                           0x1c
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                          0x00000001L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                        0x00000002L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                       0x0000FF00L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                         0x00FF0000L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                            0x01000000L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                             0x10000000L
>+//DIG4_AFMT_ISRC1_0
>+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT                                                            0x0
>+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT                                                          0x6
>+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT                                                             0x7
>+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK                                                              0x00000007L
>+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK                                                            0x00000040L
>+#define DIG4_AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK                                                               0x00000080L
>+//DIG4_AFMT_ISRC1_1
>+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT                                                          0x0
>+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT                                                          0x8
>+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT                                                          0x10
>+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT                                                          0x18
>+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK                                                            0x000000FFL
>+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK                                                            0x0000FF00L
>+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK                                                            0x00FF0000L
>+#define DIG4_AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK                                                            0xFF000000L
>+//DIG4_AFMT_ISRC1_2
>+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT                                                          0x0
>+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT                                                          0x8
>+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT                                                          0x10
>+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT                                                          0x18
>+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK                                                            0x000000FFL
>+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK                                                            0x0000FF00L
>+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK                                                            0x00FF0000L
>+#define DIG4_AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK                                                            0xFF000000L
>+//DIG4_AFMT_ISRC1_3
>+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT                                                          0x0
>+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT                                                          0x8
>+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT                                                         0x10
>+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT                                                         0x18
>+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK                                                            0x000000FFL
>+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK                                                            0x0000FF00L
>+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK                                                           0x00FF0000L
>+#define DIG4_AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK                                                           0xFF000000L
>+//DIG4_AFMT_ISRC1_4
>+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT                                                         0x0
>+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT                                                         0x8
>+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT                                                         0x10
>+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT                                                         0x18
>+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK                                                           0x000000FFL
>+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK                                                           0x0000FF00L
>+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK                                                           0x00FF0000L
>+#define DIG4_AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK                                                           0xFF000000L
>+//DIG4_AFMT_ISRC2_0
>+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT                                                         0x0
>+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT                                                         0x8
>+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT                                                         0x10
>+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT                                                         0x18
>+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK                                                           0x000000FFL
>+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK                                                           0x0000FF00L
>+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK                                                           0x00FF0000L
>+#define DIG4_AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK                                                           0xFF000000L
>+//DIG4_AFMT_ISRC2_1
>+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT                                                         0x0
>+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT                                                         0x8
>+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT                                                         0x10
>+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT                                                         0x18
>+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK                                                           0x000000FFL
>+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK                                                           0x0000FF00L
>+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK                                                           0x00FF0000L
>+#define DIG4_AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK                                                           0xFF000000L
>+//DIG4_AFMT_ISRC2_2
>+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT                                                         0x0
>+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT                                                         0x8
>+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT                                                         0x10
>+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT                                                         0x18
>+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK                                                           0x000000FFL
>+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK                                                           0x0000FF00L
>+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK                                                           0x00FF0000L
>+#define DIG4_AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK                                                           0xFF000000L
>+//DIG4_AFMT_ISRC2_3
>+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT                                                         0x0
>+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT                                                         0x8
>+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT                                                         0x10
>+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT                                                         0x18
>+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK                                                           0x000000FFL
>+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK                                                           0x0000FF00L
>+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK                                                           0x00FF0000L
>+#define DIG4_AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK                                                           0xFF000000L
>+//DIG4_HDMI_GENERIC_PACKET_CONTROL2
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
>+//DIG4_HDMI_GENERIC_PACKET_CONTROL3
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
>+//DIG4_HDMI_DB_CONTROL
>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
>+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
>+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
>+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
>+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
>+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
>+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
>+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
>+//DIG4_DME_CONTROL
>+#define DIG4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
>+#define DIG4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
>+#define DIG4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
>+#define DIG4_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
>+#define DIG4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
>+#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
>+#define DIG4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
>+#define DIG4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
>+#define DIG4_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
>+#define DIG4_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
>+#define DIG4_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
>+#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
>+#define DIG4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
>+#define DIG4_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
>+//DIG4_AFMT_MPEG_INFO0
>+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT                                                  0x0
>+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT                                                       0x8
>+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT                                                       0x10
>+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT                                                       0x18
>+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK                                                    0x000000FFL
>+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK                                                         0x0000FF00L
>+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK                                                         0x00FF0000L
>+#define DIG4_AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK                                                         0xFF000000L
>+//DIG4_AFMT_MPEG_INFO1
>+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT                                                       0x0
>+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT                                                        0x8
>+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT                                                        0xc
>+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK                                                         0x000000FFL
>+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK                                                          0x00000300L
>+#define DIG4_AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK                                                          0x00001000L
>+//DIG4_AFMT_GENERIC_HDR
>+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT                                                        0x0
>+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT                                                        0x8
>+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT                                                        0x10
>+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT                                                        0x18
>+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK                                                          0x000000FFL
>+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK                                                          0x0000FF00L
>+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK                                                          0x00FF0000L
>+#define DIG4_AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK                                                          0xFF000000L
>+//DIG4_AFMT_GENERIC_0
>+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT                                                        0x0
>+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT                                                        0x8
>+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT                                                        0x10
>+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT                                                        0x18
>+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK                                                          0x000000FFL
>+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK                                                          0x0000FF00L
>+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK                                                          0x00FF0000L
>+#define DIG4_AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK                                                          0xFF000000L
>+//DIG4_AFMT_GENERIC_1
>+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT                                                        0x0
>+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT                                                        0x8
>+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT                                                        0x10
>+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT                                                        0x18
>+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK                                                          0x000000FFL
>+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK                                                          0x0000FF00L
>+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK                                                          0x00FF0000L
>+#define DIG4_AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK                                                          0xFF000000L
>+//DIG4_AFMT_GENERIC_2
>+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT                                                        0x0
>+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT                                                        0x8
>+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT                                                       0x10
>+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT                                                       0x18
>+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK                                                          0x000000FFL
>+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK                                                          0x0000FF00L
>+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK                                                         0x00FF0000L
>+#define DIG4_AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK                                                         0xFF000000L
>+//DIG4_AFMT_GENERIC_3
>+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT                                                       0x0
>+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT                                                       0x8
>+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT                                                       0x10
>+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT                                                       0x18
>+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK                                                         0x000000FFL
>+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK                                                         0x0000FF00L
>+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK                                                         0x00FF0000L
>+#define DIG4_AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK                                                         0xFF000000L
>+//DIG4_AFMT_GENERIC_4
>+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT                                                       0x0
>+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT                                                       0x8
>+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT                                                       0x10
>+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT                                                       0x18
>+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK                                                         0x000000FFL
>+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK                                                         0x0000FF00L
>+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK                                                         0x00FF0000L
>+#define DIG4_AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK                                                         0xFF000000L
>+//DIG4_AFMT_GENERIC_5
>+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT                                                       0x0
>+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT                                                       0x8
>+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT                                                       0x10
>+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT                                                       0x18
>+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK                                                         0x000000FFL
>+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK                                                         0x0000FF00L
>+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK                                                         0x00FF0000L
>+#define DIG4_AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK                                                         0xFF000000L
>+//DIG4_AFMT_GENERIC_6
>+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT                                                       0x0
>+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT                                                       0x8
>+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT                                                       0x10
>+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT                                                       0x18
>+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK                                                         0x000000FFL
>+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK                                                         0x0000FF00L
>+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK                                                         0x00FF0000L
>+#define DIG4_AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK                                                         0xFF000000L
>+//DIG4_AFMT_GENERIC_7
>+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT                                                       0x0
>+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT                                                       0x8
>+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT                                                       0x10
>+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT                                                       0x18
>+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK                                                         0x000000FFL
>+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK                                                         0x0000FF00L
>+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK                                                         0x00FF0000L
>+#define DIG4_AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK                                                         0xFF000000L
>+//DIG4_HDMI_GENERIC_PACKET_CONTROL1
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
>+//DIG4_HDMI_ACR_32_0
>+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
>+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
>+//DIG4_HDMI_ACR_32_1
>+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
>+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
>+//DIG4_HDMI_ACR_44_0
>+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
>+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
>+//DIG4_HDMI_ACR_44_1
>+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
>+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
>+//DIG4_HDMI_ACR_48_0
>+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
>+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
>+//DIG4_HDMI_ACR_48_1
>+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
>+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
>+//DIG4_HDMI_ACR_STATUS_0
>+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
>+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
>+//DIG4_HDMI_ACR_STATUS_1
>+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
>+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
>+//DIG4_AFMT_AUDIO_INFO0
>+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                                0x0
>+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                      0x8
>+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                      0xb
>+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                         0x10
>+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                     0x18
>+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                  0x000000FFL
>+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                        0x00000700L
>+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                        0x00007800L
>+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                           0x00FF0000L
>+#define DIG4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                       0x1F000000L
>+//DIG4_AFMT_AUDIO_INFO1
>+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                      0x0
>+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                     0xb
>+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                  0xf
>+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                  0x10
>+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                        0x000000FFL
>+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                       0x00007800L
>+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                    0x00008000L
>+#define DIG4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                    0x00030000L
>+//DIG4_AFMT_60958_0
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                             0x0
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                             0x1
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                             0x2
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                             0x3
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                          0x6
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                 0x8
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                 0x10
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                              0x14
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                            0x18
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                                0x1c
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                               0x00000001L
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                               0x00000002L
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                               0x00000004L
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                               0x00000038L
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                            0x000000C0L
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                   0x0000FF00L
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                   0x000F0000L
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                                0x00F00000L
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                              0x0F000000L
>+#define DIG4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                  0x30000000L
>+//DIG4_AFMT_60958_1
>+#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                   0x0
>+#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                   0x4
>+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                          0x10
>+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                          0x12
>+#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                              0x14
>+#define DIG4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                     0x0000000FL
>+#define DIG4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                     0x000000F0L
>+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                            0x00010000L
>+#define DIG4_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                            0x00040000L
>+#define DIG4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                                0x00F00000L
>+//DIG4_AFMT_AUDIO_CRC_CONTROL
>+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                 0x0
>+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                               0x4
>+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                             0x8
>+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                             0xc
>+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                              0x10
>+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                   0x00000001L
>+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                 0x00000010L
>+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                               0x00000100L
>+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                               0x0000F000L
>+#define DIG4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                                0xFFFF0000L
>+//DIG4_AFMT_RAMP_CONTROL0
>+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                   0x0
>+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                   0x1f
>+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                     0x00FFFFFFL
>+#define DIG4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                     0x80000000L
>+//DIG4_AFMT_RAMP_CONTROL1
>+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                   0x0
>+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                            0x18
>+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                     0x00FFFFFFL
>+#define DIG4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                              0xFF000000L
>+//DIG4_AFMT_RAMP_CONTROL2
>+#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                   0x0
>+#define DIG4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                     0x00FFFFFFL
>+//DIG4_AFMT_RAMP_CONTROL3
>+#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                   0x0
>+#define DIG4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                     0x00FFFFFFL
>+//DIG4_AFMT_60958_2
>+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                              0x0
>+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                              0x4
>+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                              0x8
>+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                              0xc
>+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                              0x10
>+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                              0x14
>+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                                0x0000000FL
>+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                                0x000000F0L
>+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                                0x00000F00L
>+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                                0x0000F000L
>+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                                0x000F0000L
>+#define DIG4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                                0x00F00000L
>+//DIG4_AFMT_AUDIO_CRC_RESULT
>+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                                0x0
>+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                     0x8
>+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                  0x00000001L
>+#define DIG4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                       0xFFFFFF00L
>+//DIG4_AFMT_STATUS
>+#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                            0x4
>+#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                           0x8
>+#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                     0x18
>+#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                     0x1e
>+#define DIG4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                              0x00000010L
>+#define DIG4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                             0x00000100L
>+#define DIG4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                       0x01000000L
>+#define DIG4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                       0x40000000L
>+//DIG4_AFMT_AUDIO_PACKET_CONTROL
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                         0x0
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                 0xb
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                             0xc
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                           0xe
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                   0x17
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                        0x18
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                           0x1a
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                   0x1e
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT                                0x1f
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                           0x00000001L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                   0x00000800L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                               0x00001000L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                             0x00004000L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                     0x00800000L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                          0x01000000L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                             0x04000000L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                     0x40000000L
>+#define DIG4_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK                                  0x80000000L
>+//DIG4_AFMT_VBI_PACKET_CONTROL
>+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS__SHIFT                                         0x8
>+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT__SHIFT                                            0x10
>+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR__SHIFT                                        0x11
>+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT                                               0x1c
>+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_LOCK_STATUS_MASK                                           0x00000100L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_MASK                                              0x00010000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_CONFLICT_CLR_MASK                                          0x00020000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK                                                 0xF0000000L
>+//DIG4_AFMT_INFOFRAME_CONTROL0
>+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                           0x6
>+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                           0x7
>+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT                                            0xa
>+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                             0x00000040L
>+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                             0x00000080L
>+#define DIG4_AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK                                              0x00000400L
>+//DIG4_AFMT_AUDIO_SRC_CONTROL
>+#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                             0x0
>+#define DIG4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                               0x00000007L
>+//DIG4_DIG_BE_CNTL
>+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
>+#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
>+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
>+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
>+#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
>+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
>+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
>+#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
>+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
>+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
>+#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
>+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
>+//DIG4_DIG_BE_EN_CNTL
>+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
>+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
>+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
>+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
>+//DIG4_TMDS_CNTL
>+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
>+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
>+//DIG4_TMDS_CONTROL_CHAR
>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
>+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
>+//DIG4_TMDS_CONTROL0_FEEDBACK
>+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
>+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
>+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
>+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
>+//DIG4_TMDS_STEREOSYNC_CTL_SEL
>+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
>+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
>+//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1
>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
>+//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3
>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
>+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
>+//DIG4_TMDS_CTL_BITS
>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
>+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
>+//DIG4_TMDS_DCBALANCER_CONTROL
>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
>+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
>+//DIG4_TMDS_SYNC_DCBALANCE_CHAR
>+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
>+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
>+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
>+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
>+//DIG4_TMDS_CTL0_1_GEN_CNTL
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
>+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
>+//DIG4_TMDS_CTL2_3_GEN_CNTL
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
>+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
>+//DIG4_DIG_VERSION
>+#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
>+#define DIG4_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
>+//DIG4_DIG_LANE_ENABLE
>+#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT                                                              0x0
>+#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT                                                              0x1
>+#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT                                                              0x2
>+#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT                                                              0x3
>+#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT                                                               0x8
>+#define DIG4_DIG_LANE_ENABLE__DIG_LANE0EN_MASK                                                                0x00000001L
>+#define DIG4_DIG_LANE_ENABLE__DIG_LANE1EN_MASK                                                                0x00000002L
>+#define DIG4_DIG_LANE_ENABLE__DIG_LANE2EN_MASK                                                                0x00000004L
>+#define DIG4_DIG_LANE_ENABLE__DIG_LANE3EN_MASK                                                                0x00000008L
>+#define DIG4_DIG_LANE_ENABLE__DIG_CLK_EN_MASK                                                                 0x00000100L
>+//DIG4_AFMT_CNTL
>+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
>+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
>+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
>+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
>+//DIG4_AFMT_VBI_PACKET_CONTROL1
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x1
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE__SHIFT                                  0x2
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x3
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE__SHIFT                                      0x4
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x5
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE__SHIFT                                  0x6
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x7
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE__SHIFT                                      0x8
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x9
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE__SHIFT                                  0xa
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xb
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE__SHIFT                                      0xc
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0xd
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE__SHIFT                                  0xe
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                          0xf
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE__SHIFT                                      0x10
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x11
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE__SHIFT                                  0x12
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x13
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE__SHIFT                                      0x14
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE__SHIFT                                  0x16
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x17
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE__SHIFT                                      0x18
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x19
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE__SHIFT                                  0x1a
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1b
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE__SHIFT                                      0x1c
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x1d
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE__SHIFT                                  0x1e
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                          0x1f
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00000002L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_MASK                                    0x00000004L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000008L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_MASK                                        0x00000010L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00000020L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_MASK                                    0x00000040L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000080L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_MASK                                        0x00000100L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00000200L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_MASK                                    0x00000400L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                            0x00000800L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_MASK                                        0x00001000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00002000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_MASK                                    0x00004000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                            0x00008000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_MASK                                        0x00010000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00020000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_MASK                                    0x00040000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                            0x00080000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_MASK                                        0x00100000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_MASK                                    0x00400000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                            0x00800000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_MASK                                        0x01000000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x02000000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_MASK                                    0x04000000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                            0x08000000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_MASK                                        0x10000000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x20000000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_MASK                                    0x40000000L
>+#define DIG4_AFMT_VBI_PACKET_CONTROL1__AFMT_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                            0x80000000L
>+//DIG4_HDMI_GENERIC_PACKET_CONTROL5
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
>+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
>+//DIG4_FORCE_DIG_DISABLE
>+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
>+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
>+
>+
>+// addressBlock: dce_dc_dio_dp4_dispdec
>+//DP4_DP_LINK_CNTL
>+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
>+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
>+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
>+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
>+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
>+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
>+//DP4_DP_PIXEL_FORMAT
>+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
>+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
>+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
>+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
>+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
>+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
>+//DP4_DP_MSA_COLORIMETRY
>+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
>+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
>+//DP4_DP_CONFIG
>+#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
>+#define DP4_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
>+//DP4_DP_VID_STREAM_CNTL
>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
>+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
>+//DP4_DP_STEER_FIFO
>+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
>+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
>+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
>+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
>+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
>+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
>+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
>+//DP4_DP_MSA_MISC
>+#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
>+#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
>+#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
>+#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
>+#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
>+#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
>+#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
>+#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
>+//DP4_DP_VID_TIMING
>+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
>+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
>+#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
>+#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
>+#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
>+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
>+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
>+#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
>+#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
>+#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
>+//DP4_DP_VID_N
>+#define DP4_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
>+#define DP4_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
>+//DP4_DP_VID_M
>+#define DP4_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
>+#define DP4_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
>+//DP4_DP_LINK_FRAMING_CNTL
>+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
>+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
>+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
>+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
>+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
>+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
>+//DP4_DP_HBR2_EYE_PATTERN
>+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
>+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
>+//DP4_DP_VID_MSA_VBID
>+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
>+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
>+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
>+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
>+//DP4_DP_VID_INTERRUPT_CNTL
>+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
>+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
>+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
>+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
>+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
>+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
>+//DP4_DP_DPHY_CNTL
>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
>+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
>+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
>+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
>+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
>+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
>+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
>+//DP4_DP_DPHY_TRAINING_PATTERN_SEL
>+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
>+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
>+//DP4_DP_DPHY_SYM0
>+#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
>+#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
>+#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
>+#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
>+#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
>+#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
>+//DP4_DP_DPHY_SYM1
>+#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
>+#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
>+#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
>+#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
>+#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
>+#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
>+//DP4_DP_DPHY_SYM2
>+#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
>+#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
>+#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
>+#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
>+//DP4_DP_DPHY_8B10B_CNTL
>+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
>+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
>+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
>+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
>+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
>+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
>+//DP4_DP_DPHY_PRBS_CNTL
>+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
>+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
>+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
>+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
>+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
>+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
>+//DP4_DP_DPHY_SCRAM_CNTL
>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
>+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
>+//DP4_DP_DPHY_CRC_EN
>+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
>+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
>+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
>+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
>+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
>+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
>+//DP4_DP_DPHY_CRC_CNTL
>+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
>+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
>+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
>+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
>+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
>+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
>+//DP4_DP_DPHY_CRC_RESULT
>+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
>+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
>+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
>+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
>+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
>+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
>+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
>+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
>+//DP4_DP_DPHY_CRC_MST_CNTL
>+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
>+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
>+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
>+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
>+//DP4_DP_DPHY_CRC_MST_STATUS
>+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
>+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
>+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
>+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
>+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
>+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
>+//DP4_DP_DPHY_FAST_TRAINING
>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
>+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
>+//DP4_DP_DPHY_FAST_TRAINING_STATUS
>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
>+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
>+//DP4_DP_SEC_CNTL
>+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
>+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
>+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
>+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
>+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
>+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
>+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
>+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
>+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
>+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
>+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
>+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
>+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
>+//DP4_DP_SEC_CNTL1
>+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
>+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
>+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP4_DP_SEC_FRAMING1
>+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
>+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
>+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
>+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
>+//DP4_DP_SEC_FRAMING2
>+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
>+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
>+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
>+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
>+//DP4_DP_SEC_FRAMING3
>+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
>+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
>+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
>+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
>+//DP4_DP_SEC_FRAMING4
>+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
>+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
>+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
>+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
>+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
>+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
>+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
>+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
>+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
>+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
>+//DP4_DP_SEC_AUD_N
>+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
>+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
>+//DP4_DP_SEC_AUD_N_READBACK
>+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
>+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
>+//DP4_DP_SEC_AUD_M
>+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
>+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
>+//DP4_DP_SEC_AUD_M_READBACK
>+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
>+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
>+//DP4_DP_SEC_TIMESTAMP
>+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
>+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
>+//DP4_DP_SEC_PACKET_CNTL
>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
>+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
>+//DP4_DP_MSE_RATE_CNTL
>+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
>+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
>+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
>+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
>+//DP4_DP_MSE_RATE_UPDATE
>+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
>+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
>+//DP4_DP_MSE_SAT0
>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
>+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
>+//DP4_DP_MSE_SAT1
>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
>+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
>+//DP4_DP_MSE_SAT2
>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
>+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
>+//DP4_DP_MSE_SAT_UPDATE
>+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
>+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
>+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
>+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
>+//DP4_DP_MSE_LINK_TIMING
>+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
>+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
>+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
>+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
>+//DP4_DP_MSE_MISC_CNTL
>+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
>+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
>+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
>+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
>+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
>+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
>+//DP4_DP_DPHY_BS_SR_SWAP_CNTL
>+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
>+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
>+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
>+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
>+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
>+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
>+//DP4_DP_DPHY_HBR2_PATTERN_CONTROL
>+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
>+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
>+//DP4_DP_MSE_SAT0_STATUS
>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
>+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
>+//DP4_DP_MSE_SAT1_STATUS
>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
>+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
>+//DP4_DP_MSE_SAT2_STATUS
>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
>+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
>+//DP4_DP_MSA_TIMING_PARAM1
>+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
>+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
>+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
>+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
>+//DP4_DP_MSA_TIMING_PARAM2
>+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
>+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
>+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
>+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
>+//DP4_DP_MSA_TIMING_PARAM3
>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
>+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
>+//DP4_DP_MSA_TIMING_PARAM4
>+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
>+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
>+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
>+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
>+//DP4_DP_MSO_CNTL
>+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
>+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
>+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
>+//DP4_DP_MSO_CNTL1
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
>+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
>+//DP4_DP_DSC_CNTL
>+#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
>+#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
>+#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
>+#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
>+//DP4_DP_SEC_CNTL2
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS__SHIFT                                                              0x1c
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
>+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_PPS_MASK                                                                0x10000000L
>+//DP4_DP_SEC_CNTL3
>+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
>+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
>+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP4_DP_SEC_CNTL4
>+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
>+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
>+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP4_DP_SEC_CNTL5
>+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
>+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
>+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
>+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
>+//DP4_DP_SEC_CNTL6
>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
>+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
>+//DP4_DP_SEC_CNTL7
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
>+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
>+//DP4_DP_DB_CNTL
>+#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
>+#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
>+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
>+#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
>+#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
>+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
>+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
>+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
>+#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
>+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
>+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
>+#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
>+#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
>+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
>+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
>+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
>+//DP4_DP_MSA_VBID_MISC
>+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
>+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
>+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
>+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
>+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
>+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
>+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
>+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
>+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
>+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
>+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
>+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
>+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
>+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
>+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
>+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
>+//DP4_DP_SEC_METADATA_TRANSMISSION
>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
>+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
>+//DP4_DP_DSC_BYTES_PER_PIXEL
>+#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
>+#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
>+//DP4_DP_ALPM_CNTL
>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
>+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
>+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
>+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dcio_dcio_dispdec
>+//DC_GENERICA
>+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0
>+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7
>+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
>+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
>+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
>+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
>+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L
>+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L
>+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
>+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
>+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
>+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
>+//DC_GENERICB
>+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0
>+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8
>+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
>+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
>+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
>+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
>+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L
>+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L
>+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
>+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
>+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
>+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
>+//DC_REF_CLK_CNTL
>+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
>+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
>+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK                                                               0x00000003L
>+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L
>+//UNIPHYA_LINK_CNTL
>+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
>+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
>+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
>+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
>+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
>+#define UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
>+#define UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
>+#define UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
>+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
>+#define UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
>+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
>+//UNIPHYA_CHANNEL_XBAR_CNTL
>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
>+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
>+//UNIPHYB_LINK_CNTL
>+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
>+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
>+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
>+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
>+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
>+#define UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
>+#define UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
>+#define UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
>+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
>+#define UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
>+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
>+//UNIPHYB_CHANNEL_XBAR_CNTL
>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
>+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
>+//UNIPHYC_LINK_CNTL
>+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
>+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
>+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
>+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
>+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
>+#define UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
>+#define UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
>+#define UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
>+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
>+#define UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
>+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
>+//UNIPHYC_CHANNEL_XBAR_CNTL
>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
>+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
>+//UNIPHYD_LINK_CNTL
>+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
>+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
>+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
>+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
>+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
>+#define UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
>+#define UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
>+#define UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
>+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
>+#define UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
>+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
>+//UNIPHYD_CHANNEL_XBAR_CNTL
>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
>+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
>+//UNIPHYE_LINK_CNTL
>+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT                                                             0x0
>+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT                                                         0x4
>+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT                                          0x8
>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
>+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT                                                   0x14
>+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT                                                 0x18
>+#define UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK                                                               0x00000001L
>+#define UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK                                                           0x00000010L
>+#define UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK                                            0x00000700L
>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
>+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
>+#define UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK                                                     0x00700000L
>+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK                                                   0x03000000L
>+//UNIPHYE_CHANNEL_XBAR_CNTL
>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT                                                  0x1c
>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
>+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK                                                    0x10000000L
>+//DCIO_WRCMD_DELAY
>+#define DCIO_WRCMD_DELAY__DAC_DELAY__SHIFT                                                                    0x4
>+#define DCIO_WRCMD_DELAY__DPHY_DELAY__SHIFT                                                                   0x8
>+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY__SHIFT                                                                0xc
>+#define DCIO_WRCMD_DELAY__ZCAL_DELAY__SHIFT                                                                   0x10
>+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18
>+#define DCIO_WRCMD_DELAY__DAC_DELAY_MASK                                                                      0x000000F0L
>+#define DCIO_WRCMD_DELAY__DPHY_DELAY_MASK                                                                     0x00000F00L
>+#define DCIO_WRCMD_DELAY__DCRXPHY_DELAY_MASK                                                                  0x0000F000L
>+#define DCIO_WRCMD_DELAY__ZCAL_DELAY_MASK                                                                     0x000F0000L
>+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L
>+//DC_PINSTRAPS
>+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd
>+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
>+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10
>+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT                                                        0x11
>+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L
>+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
>+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L
>+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK                                                          0x000E0000L
>+//LVTMA_PWRSEQ_CNTL
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT                                                             0x0
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT                                0x1
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT                                                   0x4
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT                                                                0x8
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT                                                           0x9
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT                                                            0xa
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT                                                                 0x10
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT                                                            0x11
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT                                                             0x12
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT                                                                  0x18
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT                                                             0x19
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT                                                              0x1a
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK                                                               0x00000001L
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK                                  0x00000002L
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK                                                     0x00000010L
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK                                                                  0x00000100L
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK                                                             0x00000200L
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK                                                              0x00000400L
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK                                                                   0x00010000L
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK                                                              0x00020000L
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK                                                               0x00040000L
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK                                                                    0x01000000L
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK                                                               0x02000000L
>+#define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK                                                                0x04000000L
>+//LVTMA_PWRSEQ_STATE
>+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT                                                0x0
>+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT                                                         0x1
>+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT                                                        0x2
>+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT                                                          0x3
>+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT                                                          0x4
>+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT                                                         0x8
>+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK                                                  0x00000001L
>+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK                                                           0x00000002L
>+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK                                                          0x00000004L
>+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK                                                            0x00000008L
>+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK                                                            0x00000010L
>+#define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK                                                           0x00000F00L
>+//LVTMA_PWRSEQ_REF_DIV
>+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT                                                     0x0
>+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT                                                           0x10
>+#define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK                                                       0x00000FFFL
>+#define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK                                                             0xFFFF0000L
>+//LVTMA_PWRSEQ_DELAY1
>+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT                                                        0x0
>+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT                                                        0x8
>+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT                                                        0x10
>+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT                                                        0x18
>+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK                                                          0x000000FFL
>+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK                                                          0x0000FF00L
>+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK                                                          0x00FF0000L
>+#define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK                                                          0xFF000000L
>+//LVTMA_PWRSEQ_DELAY2
>+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT                                                    0x0
>+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT                                                        0x8
>+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT                                                        0x10
>+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT                                                 0x18
>+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK                                                      0x000000FFL
>+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK                                                          0x0000FF00L
>+#define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK                                                          0x00FF0000L
>+#define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK                                                   0x01000000L
>+//BL_PWM_CNTL
>+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                            0x0
>+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                              0x1e
>+#define BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                         0x1f
>+#define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                              0x0000FFFFL
>+#define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                                0x40000000L
>+#define BL_PWM_CNTL__BL_PWM_EN_MASK                                                                           0x80000000L
>+//BL_PWM_CNTL2
>+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                                      0x0
>+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                                    0x1e
>+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT                                                  0x1f
>+#define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                        0x0000FFFFL
>+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                                      0x40000000L
>+#define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK                                                    0x80000000L
>+//BL_PWM_PERIOD_CNTL
>+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                              0x0
>+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                                       0x10
>+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                                0x0000FFFFL
>+#define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                         0x000F0000L
>+//BL_PWM_GRP1_REG_LOCK
>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                                     0x0
>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                           0x8
>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                        0x10
>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT                                         0x11
>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                                     0x18
>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                        0x1f
>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                                       0x00000001L
>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                             0x00000100L
>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                          0x00010000L
>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK                                           0x000E0000L
>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                                       0x01000000L
>+#define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                          0x80000000L
>+//DCIO_GSL_GENLK_PAD_CNTL
>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4
>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8
>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14
>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18
>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L
>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L
>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L
>+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L
>+//DCIO_GSL_SWAPLOCK_PAD_CNTL
>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4
>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8
>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14
>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18
>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L
>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L
>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L
>+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L
>+//DCIO_CLOCK_CNTL
>+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0
>+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5
>+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL
>+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L
>+//DCIO_SOFT_RESET
>+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0
>+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x1
>+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x2
>+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x3
>+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x4
>+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0x5
>+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x6
>+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0x7
>+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x8
>+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0x9
>+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0xa
>+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xb
>+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0xc
>+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xd
>+#define DCIO_SOFT_RESET__DACA_SOFT_RESET__SHIFT                                                               0x10
>+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET__SHIFT                                                            0x14
>+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET__SHIFT                                                               0x18
>+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET__SHIFT                                                               0x1a
>+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L
>+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000002L
>+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000004L
>+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000008L
>+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000010L
>+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000020L
>+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000040L
>+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000080L
>+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000100L
>+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00000200L
>+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000400L
>+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00000800L
>+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00001000L
>+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00002000L
>+#define DCIO_SOFT_RESET__DACA_SOFT_RESET_MASK                                                                 0x00010000L
>+#define DCIO_SOFT_RESET__DCRXPHY_SOFT_RESET_MASK                                                              0x00100000L
>+#define DCIO_SOFT_RESET__DPHY_SOFT_RESET_MASK                                                                 0x01000000L
>+#define DCIO_SOFT_RESET__ZCAL_SOFT_RESET_MASK                                                                 0x04000000L
>+
>+
>+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
>+//DC_GPIO_GENERIC_MASK
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L
>+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L
>+//DC_GPIO_GENERIC_A
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L
>+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L
>+//DC_GPIO_GENERIC_EN
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L
>+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L
>+//DC_GPIO_GENERIC_Y
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L
>+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L
>+//DC_GPIO_DDC1_MASK
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe
>+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10
>+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14
>+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L
>+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L
>+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L
>+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L
>+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L
>+//DC_GPIO_DDC1_A
>+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0
>+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8
>+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L
>+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L
>+//DC_GPIO_DDC1_EN
>+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0
>+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8
>+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L
>+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L
>+//DC_GPIO_DDC1_Y
>+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0
>+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8
>+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L
>+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L
>+//DC_GPIO_DDC2_MASK
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe
>+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10
>+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14
>+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L
>+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L
>+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L
>+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L
>+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L
>+//DC_GPIO_DDC2_A
>+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0
>+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8
>+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L
>+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L
>+//DC_GPIO_DDC2_EN
>+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0
>+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8
>+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L
>+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L
>+//DC_GPIO_DDC2_Y
>+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0
>+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8
>+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L
>+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L
>+//DC_GPIO_DDC3_MASK
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe
>+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10
>+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14
>+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L
>+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L
>+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L
>+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L
>+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L
>+//DC_GPIO_DDC3_A
>+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0
>+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8
>+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L
>+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L
>+//DC_GPIO_DDC3_EN
>+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0
>+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8
>+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L
>+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L
>+//DC_GPIO_DDC3_Y
>+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0
>+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8
>+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L
>+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L
>+//DC_GPIO_DDC4_MASK
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe
>+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10
>+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14
>+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L
>+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L
>+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L
>+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L
>+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L
>+//DC_GPIO_DDC4_A
>+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0
>+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8
>+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L
>+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L
>+//DC_GPIO_DDC4_EN
>+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0
>+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8
>+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L
>+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L
>+//DC_GPIO_DDC4_Y
>+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0
>+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8
>+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L
>+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L
>+//DC_GPIO_DDC5_MASK
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe
>+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
>+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14
>+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT                                                         0x18
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT                                                        0x1c
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L
>+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L
>+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L
>+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK                                                           0x0F000000L
>+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK                                                          0xF0000000L
>+//DC_GPIO_DDC5_A
>+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0
>+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8
>+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L
>+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L
>+//DC_GPIO_DDC5_EN
>+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0
>+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8
>+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L
>+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L
>+//DC_GPIO_DDC5_Y
>+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0
>+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8
>+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L
>+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L
>+//DC_GPIO_DDCVGA_MASK
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe
>+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10
>+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14
>+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L
>+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L
>+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L
>+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L
>+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L
>+//DC_GPIO_DDCVGA_A
>+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0
>+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8
>+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L
>+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L
>+//DC_GPIO_DDCVGA_EN
>+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0
>+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8
>+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L
>+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L
>+//DC_GPIO_DDCVGA_Y
>+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0
>+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8
>+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L
>+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L
>+//DC_GPIO_GENLK_MASK
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L
>+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L
>+//DC_GPIO_GENLK_A
>+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0
>+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8
>+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10
>+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18
>+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L
>+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L
>+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L
>+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L
>+//DC_GPIO_GENLK_EN
>+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0
>+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8
>+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10
>+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18
>+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L
>+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L
>+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L
>+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L
>+//DC_GPIO_GENLK_Y
>+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0
>+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8
>+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10
>+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18
>+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L
>+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L
>+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L
>+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L
>+//DC_GPIO_HPD_MASK
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0
>+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK__SHIFT                                                          0x1
>+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS__SHIFT                                                        0x2
>+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL__SHIFT                                                        0x3
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_MASK_MASK                                                            0x00000002L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_PD_DIS_MASK                                                          0x00000004L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_RX_HPD_RX_SEL_MASK                                                          0x00000008L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L
>+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L
>+//DC_GPIO_HPD_A
>+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0
>+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8
>+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10
>+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18
>+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a
>+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c
>+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L
>+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L
>+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L
>+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L
>+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L
>+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L
>+//DC_GPIO_HPD_EN
>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0
>+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1
>+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2
>+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI__SHIFT                                                               0x3
>+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE__SHIFT                                                               0x4
>+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5
>+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6
>+#define DC_GPIO_HPD_EN__RX_HPD_SEL0__SHIFT                                                                    0x7
>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8
>+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9
>+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa
>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10
>+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11
>+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12
>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14
>+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15
>+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16
>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18
>+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19
>+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a
>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c
>+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d
>+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e
>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L
>+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L
>+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L
>+#define DC_GPIO_HPD_EN__RX_HPD_SCHMEN_PI_MASK                                                                 0x00000008L
>+#define DC_GPIO_HPD_EN__RX_HPD_SLEWNCORE_MASK                                                                 0x00000010L
>+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L
>+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L
>+#define DC_GPIO_HPD_EN__RX_HPD_SEL0_MASK                                                                      0x00000080L
>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L
>+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L
>+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L
>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L
>+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L
>+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L
>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L
>+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L
>+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L
>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L
>+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L
>+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L
>+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L
>+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L
>+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L
>+//DC_GPIO_HPD_Y
>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0
>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8
>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10
>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18
>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a
>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c
>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L
>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L
>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L
>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L
>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L
>+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L
>+//DC_GPIO_PWRSEQ_MASK
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                         0x0
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                                       0x4
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                         0x6
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                        0x8
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                                      0xc
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                        0xe
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT                                                       0x10
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT                                                     0x14
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT                                                       0x16
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT                                                     0x18
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT                                                   0x19
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT                                                     0x1a
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT                                                     0x1c
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT                                                   0x1d
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT                                                     0x1e
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                           0x00000001L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                         0x00000010L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                           0x000000C0L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                          0x00000100L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                        0x00001000L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                          0x0000C000L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK                                                         0x00010000L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK                                                       0x00100000L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK                                                         0x00C00000L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK                                                       0x01000000L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK                                                     0x02000000L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK                                                       0x04000000L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK                                                       0x10000000L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK                                                     0x20000000L
>+#define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK                                                       0x40000000L
>+//DC_GPIO_PWRSEQ_A
>+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT                                                               0x0
>+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT                                                              0x8
>+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT                                                             0x10
>+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT                                                           0x18
>+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT                                                           0x1f
>+#define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK                                                                 0x00000001L
>+#define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK                                                                0x00000100L
>+#define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK                                                               0x00010000L
>+#define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK                                                             0x01000000L
>+#define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK                                                             0x80000000L
>+//DC_GPIO_PWRSEQ_EN
>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                             0x0
>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                 0x1
>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                            0x8
>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT                                                           0x10
>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT                                                         0x18
>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT                                                         0x1f
>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                               0x00000001L
>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                   0x00000002L
>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                              0x00000100L
>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK                                                             0x00010000L
>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK                                                           0x01000000L
>+#define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK                                                           0x80000000L
>+//DC_GPIO_PWRSEQ_Y
>+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT                                                               0x0
>+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT                                                              0x8
>+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT                                                             0x10
>+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT                                                             0x18
>+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT                                                             0x1f
>+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK                                                                 0x00000001L
>+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK                                                                0x00000100L
>+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK                                                               0x00010000L
>+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK                                                               0x01000000L
>+#define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK                                                               0x80000000L
>+//DC_GPIO_PAD_STRENGTH_1
>+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0
>+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4
>+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN__SHIFT                                                     0x8
>+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP__SHIFT                                                     0xc
>+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10
>+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14
>+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18
>+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c
>+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL
>+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L
>+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SN_MASK                                                       0x00000F00L
>+#define DC_GPIO_PAD_STRENGTH_1__RX_HPD_STRENGTH_SP_MASK                                                       0x0000F000L
>+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L
>+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L
>+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L
>+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L
>+//DC_GPIO_PAD_STRENGTH_2
>+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0
>+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4
>+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8
>+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc
>+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT                                                     0x10
>+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT                                                     0x14
>+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e
>+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL
>+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L
>+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L
>+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L
>+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK                                                       0x000F0000L
>+#define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK                                                       0x00F00000L
>+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L
>+//PHY_AUX_CNTL
>+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN__SHIFT                                                               0x0
>+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE__SHIFT                                                                0x1
>+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT                                                               0x2
>+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE__SHIFT                                                                0x3
>+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN__SHIFT                                                              0x4
>+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN__SHIFT                                                                 0x5
>+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN__SHIFT                                                               0x6
>+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN__SHIFT                                                                  0x7
>+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN__SHIFT                                                               0x8
>+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9
>+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa
>+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc
>+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe
>+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10
>+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12
>+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14
>+#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN__SHIFT                                                                0x17
>+#define PHY_AUX_CNTL__AUX_CAL_SPARE__SHIFT                                                                    0x18
>+#define PHY_AUX_CNTL__AUX_CAL_BIASENTST__SHIFT                                                                0x1c
>+#define PHY_AUX_CNTL__AUXSLAVE_PAD_SLEWN_MASK                                                                 0x00000001L
>+#define PHY_AUX_CNTL__AUXSLAVE_PAD_WAKE_MASK                                                                  0x00000002L
>+#define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL_MASK                                                                 0x00000004L
>+#define PHY_AUX_CNTL__AUXSLAVE_PAD_MODE_MASK                                                                  0x00000008L
>+#define PHY_AUX_CNTL__DDCSLAVE_DATA_PD_EN_MASK                                                                0x00000010L
>+#define PHY_AUX_CNTL__DDCSLAVE_DATA_EN_MASK                                                                   0x00000020L
>+#define PHY_AUX_CNTL__DDCSLAVE_CLK_PD_EN_MASK                                                                 0x00000040L
>+#define PHY_AUX_CNTL__DDCSLAVE_CLK_EN_MASK                                                                    0x00000080L
>+#define PHY_AUX_CNTL__AUXSLAVE_CLK_PD_EN_MASK                                                                 0x00000100L
>+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L
>+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L
>+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L
>+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L
>+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L
>+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L
>+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L
>+#define PHY_AUX_CNTL__AUX_CAL_RESBIASEN_MASK                                                                  0x00800000L
>+#define PHY_AUX_CNTL__AUX_CAL_SPARE_MASK                                                                      0x03000000L
>+#define PHY_AUX_CNTL__AUX_CAL_BIASENTST_MASK                                                                  0x70000000L
>+//DC_GPIO_TX12_EN
>+#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN__SHIFT                                                          0x0
>+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN__SHIFT                                                         0x1
>+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN__SHIFT                                                        0x2
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9
>+#define DC_GPIO_TX12_EN__DC_GPIO_BLON_TX12_EN_MASK                                                            0x00000001L
>+#define DC_GPIO_TX12_EN__DC_GPIO_DIGON_TX12_EN_MASK                                                           0x00000002L
>+#define DC_GPIO_TX12_EN__DC_GPIO_ENA_BL_TX12_EN_MASK                                                          0x00000004L
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L
>+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L
>+//DC_GPIO_AUX_CTRL_0
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00400000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L
>+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0x40000000L
>+//DC_GPIO_AUX_CTRL_1
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x9
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xc
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00000200L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00000800L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00001000L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x00040000L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L
>+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0x40000000L
>+//DC_GPIO_AUX_CTRL_2
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L
>+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L
>+//DC_GPIO_RXEN
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6
>+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8
>+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9
>+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa
>+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb
>+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc
>+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd
>+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe
>+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf
>+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10
>+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11
>+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12
>+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13
>+#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN__SHIFT                                                                0x14
>+#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN__SHIFT                                                               0x15
>+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN__SHIFT                                                              0x16
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L
>+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L
>+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L
>+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L
>+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L
>+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L
>+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L
>+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L
>+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L
>+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L
>+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L
>+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L
>+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L
>+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L
>+#define DC_GPIO_RXEN__DC_GPIO_BLON_RXEN_MASK                                                                  0x00100000L
>+#define DC_GPIO_RXEN__DC_GPIO_DIGON_RXEN_MASK                                                                 0x00200000L
>+#define DC_GPIO_RXEN__DC_GPIO_ENA_BL_RXEN_MASK                                                                0x00400000L
>+//DC_GPIO_PULLUPEN
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
>+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13
>+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN__SHIFT                                                           0x14
>+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN__SHIFT                                                          0x15
>+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN__SHIFT                                                         0x16
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_BLON_PU_EN_MASK                                                             0x00100000L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_DIGON_PU_EN_MASK                                                            0x00200000L
>+#define DC_GPIO_PULLUPEN__DC_GPIO_ENA_BL_PU_EN_MASK                                                           0x00400000L
>+//DC_GPIO_AUX_CTRL_3
>+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
>+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
>+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
>+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
>+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
>+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
>+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
>+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
>+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
>+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
>+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
>+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
>+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
>+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
>+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
>+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
>+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
>+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
>+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
>+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
>+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
>+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
>+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
>+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
>+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
>+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
>+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
>+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
>+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
>+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
>+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
>+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
>+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
>+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
>+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
>+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
>+//DC_GPIO_AUX_CTRL_4
>+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
>+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
>+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
>+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
>+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
>+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
>+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
>+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
>+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
>+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
>+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
>+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
>+//DC_GPIO_AUX_CTRL_5
>+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
>+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
>+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
>+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
>+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
>+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
>+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
>+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
>+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
>+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
>+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
>+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
>+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
>+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
>+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
>+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
>+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
>+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
>+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
>+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
>+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
>+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
>+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
>+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
>+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
>+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
>+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
>+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
>+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
>+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
>+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
>+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
>+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
>+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
>+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
>+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
>+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
>+//AUXI2C_PAD_ALL_PWR_OK
>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
>+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L
>+
>+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
>+//DSC_TOP0_DSC_TOP_CONTROL
>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
>+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
>+//DSC_TOP0_DSC_DEBUG_CONTROL
>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
>+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
>+
>+
>+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
>+//DSCCIF0_DSCCIF_CONFIG0
>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
>+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
>+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
>+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
>+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
>+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
>+//DSCCIF0_DSCCIF_CONFIG1
>+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
>+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
>+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
>+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
>+//DSCC0_DSCC_CONFIG0
>+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
>+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
>+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
>+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
>+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
>+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
>+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
>+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
>+//DSCC0_DSCC_CONFIG1
>+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
>+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
>+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
>+#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
>+//DSCC0_DSCC_STATUS
>+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
>+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
>+//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
>+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
>+//DSCC0_DSCC_PPS_CONFIG0
>+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
>+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
>+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
>+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
>+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
>+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
>+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
>+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
>+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
>+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
>+//DSCC0_DSCC_PPS_CONFIG1
>+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
>+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
>+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
>+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
>+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
>+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
>+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
>+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
>+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
>+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
>+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
>+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
>+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
>+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
>+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
>+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
>+//DSCC0_DSCC_PPS_CONFIG2
>+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
>+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
>+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
>+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
>+//DSCC0_DSCC_PPS_CONFIG3
>+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
>+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
>+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
>+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
>+//DSCC0_DSCC_PPS_CONFIG4
>+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
>+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
>+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
>+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
>+//DSCC0_DSCC_PPS_CONFIG5
>+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
>+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
>+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
>+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
>+//DSCC0_DSCC_PPS_CONFIG6
>+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
>+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
>+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
>+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
>+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
>+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
>+//DSCC0_DSCC_PPS_CONFIG7
>+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
>+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
>+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
>+//DSCC0_DSCC_PPS_CONFIG8
>+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
>+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
>+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
>+//DSCC0_DSCC_PPS_CONFIG9
>+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
>+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
>+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
>+//DSCC0_DSCC_PPS_CONFIG10
>+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
>+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
>+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
>+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
>+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
>+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
>+//DSCC0_DSCC_PPS_CONFIG11
>+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
>+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
>+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
>+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
>+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
>+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
>+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
>+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
>+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
>+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
>+//DSCC0_DSCC_PPS_CONFIG12
>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
>+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
>+//DSCC0_DSCC_PPS_CONFIG13
>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
>+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
>+//DSCC0_DSCC_PPS_CONFIG14
>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
>+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
>+//DSCC0_DSCC_PPS_CONFIG15
>+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
>+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
>+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
>+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
>+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
>+//DSCC0_DSCC_PPS_CONFIG16
>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
>+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
>+//DSCC0_DSCC_PPS_CONFIG17
>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
>+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
>+//DSCC0_DSCC_PPS_CONFIG18
>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
>+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
>+//DSCC0_DSCC_PPS_CONFIG19
>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
>+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
>+//DSCC0_DSCC_PPS_CONFIG20
>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
>+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
>+//DSCC0_DSCC_PPS_CONFIG21
>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
>+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
>+//DSCC0_DSCC_PPS_CONFIG22
>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
>+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
>+//DSCC0_DSCC_MEM_POWER_CONTROL
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
>+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
>+//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER
>+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
>+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
>+//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER
>+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
>+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
>+//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER
>+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
>+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
>+//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER
>+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
>+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
>+//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER
>+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
>+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
>+//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER
>+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
>+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
>+//DSCC0_DSCC_MAX_ABS_ERROR0
>+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
>+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
>+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
>+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
>+//DSCC0_DSCC_MAX_ABS_ERROR1
>+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
>+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
>+//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
>+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
>+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
>+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
>+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE
>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
>+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
>+
>+
>+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON19_PERFCOUNTER_CNTL
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON19_PERFCOUNTER_CNTL2
>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON19_PERFCOUNTER_STATE
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON19_PERFMON_CNTL
>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON19_PERFMON_CNTL2
>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON19_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON19_PERFMON_CVALUE_LOW
>+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON19_PERFMON_HI
>+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON19_PERFMON_LOW
>+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
>+//DSC_TOP1_DSC_TOP_CONTROL
>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
>+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
>+//DSC_TOP1_DSC_DEBUG_CONTROL
>+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
>+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
>+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
>+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
>+
>+
>+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
>+//DSCCIF1_DSCCIF_CONFIG0
>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
>+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
>+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
>+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
>+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
>+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
>+//DSCCIF1_DSCCIF_CONFIG1
>+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
>+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
>+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
>+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
>+//DSCC1_DSCC_CONFIG0
>+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
>+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
>+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
>+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
>+#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
>+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
>+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
>+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
>+//DSCC1_DSCC_CONFIG1
>+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
>+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
>+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
>+#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
>+//DSCC1_DSCC_STATUS
>+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
>+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
>+//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
>+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
>+//DSCC1_DSCC_PPS_CONFIG0
>+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
>+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
>+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
>+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
>+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
>+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
>+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
>+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
>+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
>+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
>+//DSCC1_DSCC_PPS_CONFIG1
>+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
>+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
>+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
>+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
>+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
>+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
>+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
>+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
>+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
>+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
>+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
>+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
>+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
>+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
>+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
>+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
>+//DSCC1_DSCC_PPS_CONFIG2
>+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
>+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
>+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
>+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
>+//DSCC1_DSCC_PPS_CONFIG3
>+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
>+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
>+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
>+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
>+//DSCC1_DSCC_PPS_CONFIG4
>+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
>+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
>+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
>+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
>+//DSCC1_DSCC_PPS_CONFIG5
>+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
>+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
>+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
>+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
>+//DSCC1_DSCC_PPS_CONFIG6
>+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
>+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
>+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
>+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
>+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
>+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
>+//DSCC1_DSCC_PPS_CONFIG7
>+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
>+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
>+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
>+//DSCC1_DSCC_PPS_CONFIG8
>+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
>+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
>+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
>+//DSCC1_DSCC_PPS_CONFIG9
>+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
>+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
>+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
>+//DSCC1_DSCC_PPS_CONFIG10
>+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
>+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
>+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
>+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
>+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
>+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
>+//DSCC1_DSCC_PPS_CONFIG11
>+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
>+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
>+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
>+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
>+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
>+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
>+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
>+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
>+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
>+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
>+//DSCC1_DSCC_PPS_CONFIG12
>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
>+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
>+//DSCC1_DSCC_PPS_CONFIG13
>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
>+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
>+//DSCC1_DSCC_PPS_CONFIG14
>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
>+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
>+//DSCC1_DSCC_PPS_CONFIG15
>+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
>+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
>+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
>+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
>+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
>+//DSCC1_DSCC_PPS_CONFIG16
>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
>+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
>+//DSCC1_DSCC_PPS_CONFIG17
>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
>+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
>+//DSCC1_DSCC_PPS_CONFIG18
>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
>+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
>+//DSCC1_DSCC_PPS_CONFIG19
>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
>+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
>+//DSCC1_DSCC_PPS_CONFIG20
>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
>+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
>+//DSCC1_DSCC_PPS_CONFIG21
>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
>+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
>+//DSCC1_DSCC_PPS_CONFIG22
>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
>+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
>+//DSCC1_DSCC_MEM_POWER_CONTROL
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
>+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
>+//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER
>+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
>+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
>+//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER
>+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
>+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
>+//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER
>+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
>+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
>+//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER
>+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
>+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
>+//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER
>+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
>+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
>+//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER
>+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
>+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
>+//DSCC1_DSCC_MAX_ABS_ERROR0
>+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
>+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
>+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
>+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
>+//DSCC1_DSCC_MAX_ABS_ERROR1
>+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
>+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
>+//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
>+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
>+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
>+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
>+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE
>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
>+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
>+
>+
>+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON20_PERFCOUNTER_CNTL
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON20_PERFCOUNTER_CNTL2
>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON20_PERFCOUNTER_STATE
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON20_PERFMON_CNTL
>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON20_PERFMON_CNTL2
>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON20_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON20_PERFMON_CVALUE_LOW
>+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON20_PERFMON_HI
>+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON20_PERFMON_LOW
>+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
>+//DSC_TOP2_DSC_TOP_CONTROL
>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
>+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
>+//DSC_TOP2_DSC_DEBUG_CONTROL
>+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
>+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
>+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
>+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
>+
>+
>+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
>+//DSCCIF2_DSCCIF_CONFIG0
>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
>+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
>+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
>+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
>+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
>+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
>+//DSCCIF2_DSCCIF_CONFIG1
>+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
>+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
>+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
>+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
>+//DSCC2_DSCC_CONFIG0
>+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
>+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
>+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
>+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
>+#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
>+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
>+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
>+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
>+//DSCC2_DSCC_CONFIG1
>+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
>+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
>+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
>+#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
>+//DSCC2_DSCC_STATUS
>+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
>+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
>+//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
>+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
>+//DSCC2_DSCC_PPS_CONFIG0
>+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
>+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
>+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
>+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
>+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
>+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
>+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
>+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
>+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
>+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
>+//DSCC2_DSCC_PPS_CONFIG1
>+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
>+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
>+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
>+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
>+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
>+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
>+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
>+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
>+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
>+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
>+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
>+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
>+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
>+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
>+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
>+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
>+//DSCC2_DSCC_PPS_CONFIG2
>+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
>+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
>+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
>+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
>+//DSCC2_DSCC_PPS_CONFIG3
>+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
>+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
>+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
>+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
>+//DSCC2_DSCC_PPS_CONFIG4
>+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
>+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
>+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
>+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
>+//DSCC2_DSCC_PPS_CONFIG5
>+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
>+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
>+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
>+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
>+//DSCC2_DSCC_PPS_CONFIG6
>+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
>+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
>+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
>+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
>+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
>+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
>+//DSCC2_DSCC_PPS_CONFIG7
>+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
>+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
>+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
>+//DSCC2_DSCC_PPS_CONFIG8
>+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
>+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
>+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
>+//DSCC2_DSCC_PPS_CONFIG9
>+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
>+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
>+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
>+//DSCC2_DSCC_PPS_CONFIG10
>+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
>+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
>+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
>+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
>+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
>+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
>+//DSCC2_DSCC_PPS_CONFIG11
>+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
>+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
>+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
>+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
>+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
>+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
>+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
>+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
>+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
>+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
>+//DSCC2_DSCC_PPS_CONFIG12
>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
>+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
>+//DSCC2_DSCC_PPS_CONFIG13
>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
>+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
>+//DSCC2_DSCC_PPS_CONFIG14
>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
>+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
>+//DSCC2_DSCC_PPS_CONFIG15
>+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
>+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
>+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
>+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
>+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
>+//DSCC2_DSCC_PPS_CONFIG16
>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
>+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
>+//DSCC2_DSCC_PPS_CONFIG17
>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
>+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
>+//DSCC2_DSCC_PPS_CONFIG18
>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
>+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
>+//DSCC2_DSCC_PPS_CONFIG19
>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
>+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
>+//DSCC2_DSCC_PPS_CONFIG20
>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
>+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
>+//DSCC2_DSCC_PPS_CONFIG21
>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
>+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
>+//DSCC2_DSCC_PPS_CONFIG22
>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
>+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
>+//DSCC2_DSCC_MEM_POWER_CONTROL
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
>+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
>+//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER
>+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
>+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
>+//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER
>+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
>+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
>+//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER
>+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
>+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
>+//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER
>+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
>+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
>+//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER
>+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
>+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
>+//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER
>+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
>+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
>+//DSCC2_DSCC_MAX_ABS_ERROR0
>+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
>+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
>+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
>+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
>+//DSCC2_DSCC_MAX_ABS_ERROR1
>+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
>+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
>+//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
>+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
>+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
>+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
>+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE
>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
>+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
>+
>+
>+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON21_PERFCOUNTER_CNTL
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON21_PERFCOUNTER_CNTL2
>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON21_PERFCOUNTER_STATE
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON21_PERFMON_CNTL
>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON21_PERFMON_CNTL2
>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON21_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON21_PERFMON_CVALUE_LOW
>+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON21_PERFMON_HI
>+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON21_PERFMON_LOW
>+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
>+//DSC_TOP3_DSC_TOP_CONTROL
>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
>+#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
>+//DSC_TOP3_DSC_DEBUG_CONTROL
>+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
>+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
>+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
>+#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
>+
>+
>+// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
>+//DSCCIF3_DSCCIF_CONFIG0
>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
>+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
>+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
>+#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
>+#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
>+#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
>+//DSCCIF3_DSCCIF_CONFIG1
>+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
>+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
>+#define DSCCIF3_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
>+#define DSCCIF3_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
>+//DSCC3_DSCC_CONFIG0
>+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
>+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
>+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
>+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
>+#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
>+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
>+#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
>+#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
>+//DSCC3_DSCC_CONFIG1
>+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
>+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
>+#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
>+#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
>+//DSCC3_DSCC_STATUS
>+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
>+#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
>+//DSCC3_DSCC_INTERRUPT_CONTROL_STATUS
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
>+#define DSCC3_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
>+//DSCC3_DSCC_PPS_CONFIG0
>+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
>+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
>+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
>+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
>+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
>+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
>+#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
>+#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
>+#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
>+#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
>+//DSCC3_DSCC_PPS_CONFIG1
>+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
>+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
>+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
>+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
>+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
>+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
>+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
>+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
>+#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
>+#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
>+#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
>+#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
>+#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
>+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
>+#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
>+#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
>+//DSCC3_DSCC_PPS_CONFIG2
>+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
>+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
>+#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
>+#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
>+//DSCC3_DSCC_PPS_CONFIG3
>+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
>+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
>+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
>+#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
>+//DSCC3_DSCC_PPS_CONFIG4
>+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
>+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
>+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
>+#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
>+//DSCC3_DSCC_PPS_CONFIG5
>+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
>+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
>+#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
>+#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
>+//DSCC3_DSCC_PPS_CONFIG6
>+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
>+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
>+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
>+#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
>+#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
>+#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
>+//DSCC3_DSCC_PPS_CONFIG7
>+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
>+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
>+#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
>+//DSCC3_DSCC_PPS_CONFIG8
>+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
>+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
>+#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
>+//DSCC3_DSCC_PPS_CONFIG9
>+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
>+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
>+#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
>+//DSCC3_DSCC_PPS_CONFIG10
>+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
>+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
>+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
>+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
>+#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
>+#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
>+//DSCC3_DSCC_PPS_CONFIG11
>+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
>+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
>+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
>+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
>+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
>+#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
>+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
>+#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
>+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
>+#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
>+//DSCC3_DSCC_PPS_CONFIG12
>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
>+#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
>+//DSCC3_DSCC_PPS_CONFIG13
>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
>+#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
>+//DSCC3_DSCC_PPS_CONFIG14
>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
>+#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
>+//DSCC3_DSCC_PPS_CONFIG15
>+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
>+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
>+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
>+#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
>+#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
>+//DSCC3_DSCC_PPS_CONFIG16
>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
>+#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
>+//DSCC3_DSCC_PPS_CONFIG17
>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
>+#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
>+//DSCC3_DSCC_PPS_CONFIG18
>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
>+#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
>+//DSCC3_DSCC_PPS_CONFIG19
>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
>+#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
>+//DSCC3_DSCC_PPS_CONFIG20
>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
>+#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
>+//DSCC3_DSCC_PPS_CONFIG21
>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
>+#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
>+//DSCC3_DSCC_PPS_CONFIG22
>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
>+#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
>+//DSCC3_DSCC_MEM_POWER_CONTROL
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
>+#define DSCC3_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
>+//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER
>+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
>+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
>+//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER
>+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
>+#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
>+//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER
>+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
>+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
>+//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER
>+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
>+#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
>+//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER
>+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
>+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
>+//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER
>+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
>+#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
>+//DSCC3_DSCC_MAX_ABS_ERROR0
>+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
>+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
>+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
>+#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
>+//DSCC3_DSCC_MAX_ABS_ERROR1
>+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
>+#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
>+//DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
>+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
>+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
>+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
>+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE
>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
>+#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
>+
>+
>+// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON22_PERFCOUNTER_CNTL
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON22_PERFCOUNTER_CNTL2
>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON22_PERFCOUNTER_STATE
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON22_PERFMON_CNTL
>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON22_PERFMON_CNTL2
>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON22_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON22_PERFMON_CVALUE_LOW
>+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON22_PERFMON_HI
>+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON22_PERFMON_LOW
>+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec
>+//DSC_TOP4_DSC_TOP_CONTROL
>+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
>+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
>+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
>+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
>+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
>+#define DSC_TOP4_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
>+//DSC_TOP4_DSC_DEBUG_CONTROL
>+#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
>+#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
>+#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
>+#define DSC_TOP4_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
>+
>+
>+// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec
>+//DSCCIF4_DSCCIF_CONFIG0
>+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
>+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
>+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
>+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
>+#define DSCCIF4_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
>+#define DSCCIF4_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
>+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
>+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
>+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
>+#define DSCCIF4_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
>+#define DSCCIF4_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
>+#define DSCCIF4_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
>+//DSCCIF4_DSCCIF_CONFIG1
>+#define DSCCIF4_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
>+#define DSCCIF4_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
>+#define DSCCIF4_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
>+#define DSCCIF4_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec
>+//DSCC4_DSCC_CONFIG0
>+#define DSCC4_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
>+#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
>+#define DSCC4_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
>+#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
>+#define DSCC4_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
>+#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
>+#define DSCC4_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
>+#define DSCC4_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
>+//DSCC4_DSCC_CONFIG1
>+#define DSCC4_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
>+#define DSCC4_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
>+#define DSCC4_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
>+#define DSCC4_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
>+//DSCC4_DSCC_STATUS
>+#define DSCC4_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
>+#define DSCC4_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
>+//DSCC4_DSCC_INTERRUPT_CONTROL_STATUS
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
>+#define DSCC4_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
>+//DSCC4_DSCC_PPS_CONFIG0
>+#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
>+#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
>+#define DSCC4_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
>+#define DSCC4_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
>+#define DSCC4_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
>+#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
>+#define DSCC4_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
>+#define DSCC4_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
>+#define DSCC4_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
>+#define DSCC4_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
>+//DSCC4_DSCC_PPS_CONFIG1
>+#define DSCC4_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
>+#define DSCC4_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
>+#define DSCC4_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
>+#define DSCC4_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
>+#define DSCC4_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
>+#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
>+#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
>+#define DSCC4_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
>+#define DSCC4_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
>+#define DSCC4_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
>+#define DSCC4_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
>+#define DSCC4_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
>+#define DSCC4_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
>+#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
>+#define DSCC4_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
>+#define DSCC4_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
>+//DSCC4_DSCC_PPS_CONFIG2
>+#define DSCC4_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
>+#define DSCC4_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
>+#define DSCC4_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
>+#define DSCC4_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
>+//DSCC4_DSCC_PPS_CONFIG3
>+#define DSCC4_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
>+#define DSCC4_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
>+#define DSCC4_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
>+#define DSCC4_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
>+//DSCC4_DSCC_PPS_CONFIG4
>+#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
>+#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
>+#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
>+#define DSCC4_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
>+//DSCC4_DSCC_PPS_CONFIG5
>+#define DSCC4_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
>+#define DSCC4_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
>+#define DSCC4_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
>+#define DSCC4_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
>+//DSCC4_DSCC_PPS_CONFIG6
>+#define DSCC4_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
>+#define DSCC4_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
>+#define DSCC4_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
>+#define DSCC4_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
>+#define DSCC4_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
>+#define DSCC4_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
>+//DSCC4_DSCC_PPS_CONFIG7
>+#define DSCC4_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
>+#define DSCC4_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
>+#define DSCC4_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC4_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
>+//DSCC4_DSCC_PPS_CONFIG8
>+#define DSCC4_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
>+#define DSCC4_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
>+#define DSCC4_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC4_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
>+//DSCC4_DSCC_PPS_CONFIG9
>+#define DSCC4_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
>+#define DSCC4_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
>+#define DSCC4_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC4_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
>+//DSCC4_DSCC_PPS_CONFIG10
>+#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
>+#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
>+#define DSCC4_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
>+#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
>+#define DSCC4_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
>+#define DSCC4_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
>+//DSCC4_DSCC_PPS_CONFIG11
>+#define DSCC4_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
>+#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
>+#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
>+#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
>+#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
>+#define DSCC4_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
>+#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
>+#define DSCC4_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
>+#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
>+#define DSCC4_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
>+//DSCC4_DSCC_PPS_CONFIG12
>+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
>+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
>+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
>+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
>+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
>+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
>+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
>+#define DSCC4_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
>+//DSCC4_DSCC_PPS_CONFIG13
>+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
>+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
>+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
>+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
>+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
>+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
>+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
>+#define DSCC4_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
>+//DSCC4_DSCC_PPS_CONFIG14
>+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
>+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
>+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
>+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
>+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
>+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
>+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
>+#define DSCC4_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
>+//DSCC4_DSCC_PPS_CONFIG15
>+#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
>+#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
>+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
>+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
>+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
>+#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
>+#define DSCC4_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
>+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
>+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
>+#define DSCC4_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
>+//DSCC4_DSCC_PPS_CONFIG16
>+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
>+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
>+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
>+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
>+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
>+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
>+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
>+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
>+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
>+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
>+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
>+#define DSCC4_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
>+//DSCC4_DSCC_PPS_CONFIG17
>+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
>+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
>+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
>+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
>+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
>+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
>+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
>+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
>+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
>+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
>+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
>+#define DSCC4_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
>+//DSCC4_DSCC_PPS_CONFIG18
>+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
>+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
>+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
>+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
>+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
>+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
>+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
>+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
>+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
>+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
>+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
>+#define DSCC4_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
>+//DSCC4_DSCC_PPS_CONFIG19
>+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
>+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
>+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
>+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
>+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
>+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
>+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
>+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
>+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
>+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
>+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
>+#define DSCC4_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
>+//DSCC4_DSCC_PPS_CONFIG20
>+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
>+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
>+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
>+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
>+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
>+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
>+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
>+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
>+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
>+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
>+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
>+#define DSCC4_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
>+//DSCC4_DSCC_PPS_CONFIG21
>+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
>+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
>+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
>+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
>+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
>+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
>+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
>+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
>+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
>+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
>+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
>+#define DSCC4_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
>+//DSCC4_DSCC_PPS_CONFIG22
>+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
>+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
>+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
>+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
>+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
>+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
>+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
>+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
>+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
>+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
>+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
>+#define DSCC4_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
>+//DSCC4_DSCC_MEM_POWER_CONTROL
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
>+#define DSCC4_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
>+//DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER
>+#define DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
>+#define DSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
>+//DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER
>+#define DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
>+#define DSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
>+//DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER
>+#define DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
>+#define DSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
>+//DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER
>+#define DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
>+#define DSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
>+//DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER
>+#define DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
>+#define DSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
>+//DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER
>+#define DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
>+#define DSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
>+//DSCC4_DSCC_MAX_ABS_ERROR0
>+#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
>+#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
>+#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
>+#define DSCC4_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
>+//DSCC4_DSCC_MAX_ABS_ERROR1
>+#define DSCC4_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
>+#define DSCC4_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
>+//DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
>+#define DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
>+#define DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
>+#define DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
>+#define DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
>+#define DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
>+#define DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
>+#define DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
>+#define DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE
>+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
>+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
>+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
>+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
>+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
>+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
>+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
>+#define DSCC4_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
>+
>+
>+// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON23_PERFCOUNTER_CNTL
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON23_PERFCOUNTER_CNTL2
>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON23_PERFCOUNTER_STATE
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON23_PERFMON_CNTL
>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON23_PERFMON_CNTL2
>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON23_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON23_PERFMON_CVALUE_LOW
>+#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON23_PERFMON_HI
>+#define DC_PERFMON23_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON23_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON23_PERFMON_LOW
>+#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec
>+//DSC_TOP5_DSC_TOP_CONTROL
>+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
>+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
>+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
>+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
>+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
>+#define DSC_TOP5_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
>+//DSC_TOP5_DSC_DEBUG_CONTROL
>+#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
>+#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
>+#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
>+#define DSC_TOP5_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
>+
>+
>+// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec
>+//DSCCIF5_DSCCIF_CONFIG0
>+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
>+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
>+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
>+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
>+#define DSCCIF5_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
>+#define DSCCIF5_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
>+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
>+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
>+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
>+#define DSCCIF5_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
>+#define DSCCIF5_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
>+#define DSCCIF5_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
>+//DSCCIF5_DSCCIF_CONFIG1
>+#define DSCCIF5_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
>+#define DSCCIF5_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
>+#define DSCCIF5_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
>+#define DSCCIF5_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
>+
>+
>+// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec
>+//DSCC5_DSCC_CONFIG0
>+#define DSCC5_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
>+#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
>+#define DSCC5_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
>+#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
>+#define DSCC5_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
>+#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
>+#define DSCC5_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
>+#define DSCC5_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
>+//DSCC5_DSCC_CONFIG1
>+#define DSCC5_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
>+#define DSCC5_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT                                                           0x18
>+#define DSCC5_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
>+#define DSCC5_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK                                                             0x01000000L
>+//DSCC5_DSCC_STATUS
>+#define DSCC5_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
>+#define DSCC5_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
>+//DSCC5_DSCC_INTERRUPT_CONTROL_STATUS
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
>+#define DSCC5_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
>+//DSCC5_DSCC_PPS_CONFIG0
>+#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
>+#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
>+#define DSCC5_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
>+#define DSCC5_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
>+#define DSCC5_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
>+#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
>+#define DSCC5_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
>+#define DSCC5_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
>+#define DSCC5_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
>+#define DSCC5_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
>+//DSCC5_DSCC_PPS_CONFIG1
>+#define DSCC5_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
>+#define DSCC5_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
>+#define DSCC5_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
>+#define DSCC5_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
>+#define DSCC5_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
>+#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
>+#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
>+#define DSCC5_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
>+#define DSCC5_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
>+#define DSCC5_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
>+#define DSCC5_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
>+#define DSCC5_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
>+#define DSCC5_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
>+#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
>+#define DSCC5_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
>+#define DSCC5_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
>+//DSCC5_DSCC_PPS_CONFIG2
>+#define DSCC5_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
>+#define DSCC5_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
>+#define DSCC5_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
>+#define DSCC5_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
>+//DSCC5_DSCC_PPS_CONFIG3
>+#define DSCC5_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
>+#define DSCC5_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
>+#define DSCC5_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
>+#define DSCC5_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
>+//DSCC5_DSCC_PPS_CONFIG4
>+#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
>+#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
>+#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
>+#define DSCC5_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
>+//DSCC5_DSCC_PPS_CONFIG5
>+#define DSCC5_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
>+#define DSCC5_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
>+#define DSCC5_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
>+#define DSCC5_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
>+//DSCC5_DSCC_PPS_CONFIG6
>+#define DSCC5_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
>+#define DSCC5_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
>+#define DSCC5_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
>+#define DSCC5_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
>+#define DSCC5_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
>+#define DSCC5_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
>+//DSCC5_DSCC_PPS_CONFIG7
>+#define DSCC5_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
>+#define DSCC5_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
>+#define DSCC5_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC5_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
>+//DSCC5_DSCC_PPS_CONFIG8
>+#define DSCC5_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
>+#define DSCC5_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
>+#define DSCC5_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC5_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
>+//DSCC5_DSCC_PPS_CONFIG9
>+#define DSCC5_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
>+#define DSCC5_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
>+#define DSCC5_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
>+#define DSCC5_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
>+//DSCC5_DSCC_PPS_CONFIG10
>+#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
>+#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
>+#define DSCC5_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
>+#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
>+#define DSCC5_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
>+#define DSCC5_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
>+//DSCC5_DSCC_PPS_CONFIG11
>+#define DSCC5_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
>+#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
>+#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
>+#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
>+#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
>+#define DSCC5_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
>+#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
>+#define DSCC5_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
>+#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
>+#define DSCC5_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
>+//DSCC5_DSCC_PPS_CONFIG12
>+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
>+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
>+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
>+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
>+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
>+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
>+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
>+#define DSCC5_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
>+//DSCC5_DSCC_PPS_CONFIG13
>+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
>+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
>+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
>+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
>+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
>+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
>+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
>+#define DSCC5_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
>+//DSCC5_DSCC_PPS_CONFIG14
>+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
>+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
>+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
>+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
>+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
>+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
>+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
>+#define DSCC5_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
>+//DSCC5_DSCC_PPS_CONFIG15
>+#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
>+#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
>+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
>+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
>+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
>+#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
>+#define DSCC5_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
>+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
>+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
>+#define DSCC5_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
>+//DSCC5_DSCC_PPS_CONFIG16
>+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
>+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
>+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
>+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
>+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
>+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
>+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
>+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
>+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
>+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
>+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
>+#define DSCC5_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
>+//DSCC5_DSCC_PPS_CONFIG17
>+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
>+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
>+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
>+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
>+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
>+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
>+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
>+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
>+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
>+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
>+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
>+#define DSCC5_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
>+//DSCC5_DSCC_PPS_CONFIG18
>+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
>+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
>+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
>+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
>+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
>+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
>+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
>+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
>+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
>+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
>+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
>+#define DSCC5_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
>+//DSCC5_DSCC_PPS_CONFIG19
>+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
>+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
>+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
>+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
>+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
>+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
>+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
>+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
>+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
>+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
>+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
>+#define DSCC5_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
>+//DSCC5_DSCC_PPS_CONFIG20
>+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
>+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
>+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
>+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
>+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
>+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
>+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
>+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
>+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
>+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
>+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
>+#define DSCC5_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
>+//DSCC5_DSCC_PPS_CONFIG21
>+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
>+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
>+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
>+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
>+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
>+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
>+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
>+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
>+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
>+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
>+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
>+#define DSCC5_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
>+//DSCC5_DSCC_PPS_CONFIG22
>+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
>+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
>+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
>+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
>+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
>+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
>+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
>+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
>+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
>+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
>+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
>+#define DSCC5_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
>+//DSCC5_DSCC_MEM_POWER_CONTROL
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
>+#define DSCC5_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
>+//DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER
>+#define DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
>+#define DSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
>+//DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER
>+#define DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
>+#define DSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
>+//DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER
>+#define DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
>+#define DSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
>+//DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER
>+#define DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
>+#define DSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
>+//DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER
>+#define DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
>+#define DSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
>+//DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER
>+#define DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
>+#define DSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
>+//DSCC5_DSCC_MAX_ABS_ERROR0
>+#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
>+#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
>+#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
>+#define DSCC5_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
>+//DSCC5_DSCC_MAX_ABS_ERROR1
>+#define DSCC5_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
>+#define DSCC5_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
>+//DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
>+#define DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
>+#define DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
>+#define DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
>+#define DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
>+#define DSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
>+//DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
>+#define DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
>+#define DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
>+#define DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
>+#define DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
>+#define DSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
>+//DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE
>+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
>+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
>+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
>+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
>+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
>+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
>+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
>+#define DSCC5_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
>+
>+
>+// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
>+//DC_PERFMON24_PERFCOUNTER_CNTL
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
>+//DC_PERFMON24_PERFCOUNTER_CNTL2
>+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
>+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
>+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
>+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
>+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
>+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
>+#define DC_PERFMON24_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
>+//DC_PERFMON24_PERFCOUNTER_STATE
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
>+#define DC_PERFMON24_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
>+//DC_PERFMON24_PERFMON_CNTL
>+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
>+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
>+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
>+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
>+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
>+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
>+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
>+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
>+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
>+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
>+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
>+#define DC_PERFMON24_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
>+//DC_PERFMON24_PERFMON_CNTL2
>+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
>+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
>+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
>+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
>+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
>+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
>+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
>+#define DC_PERFMON24_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
>+//DC_PERFMON24_PERFMON_CVALUE_INT_MISC
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
>+#define DC_PERFMON24_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
>+//DC_PERFMON24_PERFMON_CVALUE_LOW
>+#define DC_PERFMON24_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
>+#define DC_PERFMON24_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
>+//DC_PERFMON24_PERFMON_HI
>+#define DC_PERFMON24_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
>+#define DC_PERFMON24_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
>+#define DC_PERFMON24_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
>+#define DC_PERFMON24_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
>+//DC_PERFMON24_PERFMON_LOW
>+#define DC_PERFMON24_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
>+#define DC_PERFMON24_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
>+
>+
>+// addressBlock: dce_dc_dmu_dmcub_dispdec
>+//DMCUB_REGION0_OFFSET
>+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT                                                     0x8
>+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK                                                       0xFFFFFF00L
>+//DMCUB_REGION0_OFFSET_HIGH
>+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT                                           0x0
>+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK                                             0x0000FFFFL
>+//DMCUB_REGION1_OFFSET
>+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT                                                     0x8
>+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK                                                       0xFFFFFF00L
>+//DMCUB_REGION1_OFFSET_HIGH
>+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT                                           0x0
>+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK                                             0x0000FFFFL
>+//DMCUB_REGION2_OFFSET
>+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT                                                     0x8
>+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK                                                       0xFFFFFF00L
>+//DMCUB_REGION2_OFFSET_HIGH
>+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT                                           0x0
>+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK                                             0x0000FFFFL
>+//DMCUB_REGION4_OFFSET
>+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT                                                     0x8
>+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK                                                       0xFFFFFF00L
>+//DMCUB_REGION4_OFFSET_HIGH
>+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT                                           0x0
>+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK                                             0x0000FFFFL
>+//DMCUB_REGION5_OFFSET
>+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT                                                     0x8
>+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK                                                       0xFFFFFF00L
>+//DMCUB_REGION5_OFFSET_HIGH
>+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT                                           0x0
>+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK                                             0x0000FFFFL
>+//DMCUB_REGION6_OFFSET
>+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT                                                     0x8
>+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK                                                       0xFFFFFF00L
>+//DMCUB_REGION6_OFFSET_HIGH
>+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT                                           0x0
>+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK                                             0x0000FFFFL
>+//DMCUB_REGION7_OFFSET
>+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT                                                     0x8
>+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK                                                       0xFFFFFF00L
>+//DMCUB_REGION7_OFFSET_HIGH
>+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT                                           0x0
>+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK                                             0x0000FFFFL
>+//DMCUB_REGION0_TOP_ADDRESS
>+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT                                           0x0
>+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT                                                0x1f
>+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
>+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK                                                  0x80000000L
>+//DMCUB_REGION1_TOP_ADDRESS
>+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT                                           0x0
>+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT                                                0x1f
>+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
>+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK                                                  0x80000000L
>+//DMCUB_REGION2_TOP_ADDRESS
>+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT                                           0x0
>+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT                                                0x1f
>+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
>+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK                                                  0x80000000L
>+//DMCUB_REGION4_TOP_ADDRESS
>+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT                                           0x0
>+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT                                                0x1f
>+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
>+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK                                                  0x80000000L
>+//DMCUB_REGION5_TOP_ADDRESS
>+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT                                           0x0
>+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT                                                0x1f
>+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
>+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK                                                  0x80000000L
>+//DMCUB_REGION6_TOP_ADDRESS
>+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT                                           0x0
>+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT                                                0x1f
>+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
>+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK                                                  0x80000000L
>+//DMCUB_REGION7_TOP_ADDRESS
>+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT                                           0x0
>+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT                                                0x1f
>+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
>+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK                                                  0x80000000L
>+//DMCUB_REGION3_CW0_BASE_ADDRESS
>+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT                                 0x0
>+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
>+//DMCUB_REGION3_CW1_BASE_ADDRESS
>+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT                                 0x0
>+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
>+//DMCUB_REGION3_CW2_BASE_ADDRESS
>+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT                                 0x0
>+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
>+//DMCUB_REGION3_CW3_BASE_ADDRESS
>+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT                                 0x0
>+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
>+//DMCUB_REGION3_CW4_BASE_ADDRESS
>+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT                                 0x0
>+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
>+//DMCUB_REGION3_CW5_BASE_ADDRESS
>+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT                                 0x0
>+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
>+//DMCUB_REGION3_CW6_BASE_ADDRESS
>+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT                                 0x0
>+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
>+//DMCUB_REGION3_CW7_BASE_ADDRESS
>+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT                                 0x0
>+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
>+//DMCUB_REGION3_CW0_TOP_ADDRESS
>+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT                                        0x1f
>+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
>+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK                                          0x80000000L
>+//DMCUB_REGION3_CW1_TOP_ADDRESS
>+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT                                        0x1f
>+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
>+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK                                          0x80000000L
>+//DMCUB_REGION3_CW2_TOP_ADDRESS
>+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT                                        0x1f
>+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
>+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK                                          0x80000000L
>+//DMCUB_REGION3_CW3_TOP_ADDRESS
>+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT                                        0x1f
>+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
>+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK                                          0x80000000L
>+//DMCUB_REGION3_CW4_TOP_ADDRESS
>+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT                                        0x1f
>+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
>+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK                                          0x80000000L
>+//DMCUB_REGION3_CW5_TOP_ADDRESS
>+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT                                        0x1f
>+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
>+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK                                          0x80000000L
>+//DMCUB_REGION3_CW6_TOP_ADDRESS
>+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT                                        0x1f
>+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
>+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK                                          0x80000000L
>+//DMCUB_REGION3_CW7_TOP_ADDRESS
>+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT                                        0x1f
>+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
>+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK                                          0x80000000L
>+//DMCUB_REGION3_CW0_OFFSET
>+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT                                             0x8
>+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK                                               0xFFFFFF00L
>+//DMCUB_REGION3_CW0_OFFSET_HIGH
>+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK                                     0x0000FFFFL
>+//DMCUB_REGION3_CW1_OFFSET
>+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT                                             0x8
>+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK                                               0xFFFFFF00L
>+//DMCUB_REGION3_CW1_OFFSET_HIGH
>+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK                                     0x0000FFFFL
>+//DMCUB_REGION3_CW2_OFFSET
>+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT                                             0x8
>+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK                                               0xFFFFFF00L
>+//DMCUB_REGION3_CW2_OFFSET_HIGH
>+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK                                     0x0000FFFFL
>+//DMCUB_REGION3_CW3_OFFSET
>+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT                                             0x8
>+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK                                               0xFFFFFF00L
>+//DMCUB_REGION3_CW3_OFFSET_HIGH
>+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK                                     0x0000FFFFL
>+//DMCUB_REGION3_CW4_OFFSET
>+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT                                             0x8
>+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK                                               0xFFFFFF00L
>+//DMCUB_REGION3_CW4_OFFSET_HIGH
>+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK                                     0x0000FFFFL
>+//DMCUB_REGION3_CW5_OFFSET
>+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT                                             0x8
>+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK                                               0xFFFFFF00L
>+//DMCUB_REGION3_CW5_OFFSET_HIGH
>+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK                                     0x0000FFFFL
>+//DMCUB_REGION3_CW6_OFFSET
>+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT                                             0x8
>+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK                                               0xFFFFFF00L
>+//DMCUB_REGION3_CW6_OFFSET_HIGH
>+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK                                     0x0000FFFFL
>+//DMCUB_REGION3_CW7_OFFSET
>+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT                                             0x8
>+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK                                               0xFFFFFF00L
>+//DMCUB_REGION3_CW7_OFFSET_HIGH
>+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT                                   0x0
>+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK                                     0x0000FFFFL
>+//DMCUB_INTERRUPT_ENABLE
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT                                                    0x0
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT                                                    0x1
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT                                              0x2
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT                                               0x3
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT                                              0x4
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT                                               0x5
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT                                             0x6
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT                                              0x7
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT                                             0x8
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT                                              0x9
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT                                                    0xa
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT                                                    0xb
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT                                                    0xc
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT                                   0xd
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK                                                      0x00000001L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK                                                      0x00000002L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK                                                0x00000004L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK                                                 0x00000008L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK                                                0x00000010L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK                                                 0x00000020L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK                                               0x00000040L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK                                                0x00000080L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK                                               0x00000100L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK                                                0x00000200L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK                                                      0x00000400L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK                                                      0x00000800L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK                                                      0x00001000L
>+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK                                     0x00002000L
>+//DMCUB_INTERRUPT_ACK
>+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT                                                      0x0
>+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT                                                      0x1
>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT                                                0x2
>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT                                                 0x3
>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT                                                0x4
>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT                                                 0x5
>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT                                               0x6
>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT                                                0x7
>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT                                               0x8
>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT                                                0x9
>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT                                                      0xa
>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT                                                      0xb
>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT                                                      0xc
>+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT                                         0xd
>+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK                                                        0x00000001L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK                                                        0x00000002L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK                                                  0x00000004L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK                                                   0x00000008L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK                                                  0x00000010L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK                                                   0x00000020L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK                                                 0x00000040L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK                                                  0x00000080L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK                                                 0x00000100L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK                                                  0x00000200L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK                                                        0x00000400L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK                                                        0x00000800L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK                                                        0x00001000L
>+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK                                           0x00002000L
>+//DMCUB_INTERRUPT_STATUS
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT                                                  0x0
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT                                                  0x1
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT                                            0x2
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT                                             0x3
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT                                            0x4
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT                                             0x5
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT                                           0x6
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT                                            0x7
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT                                           0x8
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT                                            0x9
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT                                                  0xa
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT                                                  0xb
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT                                                  0xc
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT                                          0xd
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT                                                 0xe
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT                                                 0xf
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK                                                    0x00000001L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK                                                    0x00000002L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK                                              0x00000004L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK                                               0x00000008L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK                                              0x00000010L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK                                               0x00000020L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK                                             0x00000040L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK                                              0x00000080L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK                                             0x00000100L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK                                              0x00000200L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK                                                    0x00000400L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK                                                    0x00000800L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK                                                    0x00001000L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK                                            0x00002000L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK                                                   0x00004000L
>+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK                                                   0x00008000L
>+//DMCUB_INTERRUPT_TYPE
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT                                                    0x0
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT                                                    0x1
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT                                              0x2
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT                                               0x3
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT                                              0x4
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT                                               0x5
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT                                             0x6
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT                                              0x7
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT                                             0x8
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT                                              0x9
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT                                                    0xa
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT                                                    0xb
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT                                                    0xc
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT                                   0xd
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK                                                      0x00000001L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK                                                      0x00000002L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK                                                0x00000004L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK                                                 0x00000008L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK                                                0x00000010L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK                                                 0x00000020L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK                                               0x00000040L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK                                                0x00000080L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK                                               0x00000100L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK                                                0x00000200L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK                                                      0x00000400L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK                                                      0x00000800L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK                                                      0x00001000L
>+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK                                     0x00002000L
>+//DMCUB_EXT_INTERRUPT_STATUS
>+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT                                          0x0
>+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT                                             0x8
>+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK                                            0x000000FFL
>+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK                                               0x0000FF00L
>+//DMCUB_EXT_INTERRUPT_CTXID
>+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT                                           0x0
>+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK                                             0x0FFFFFFFL
>+//DMCUB_EXT_INTERRUPT_ACK
>+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT                                               0x0
>+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK                                                 0x00000001L
>+//DMCUB_INST_FETCH_FAULT_ADDR
>+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT                                       0x0
>+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK                                         0xFFFFFFFFL
>+//DMCUB_DATA_WRITE_FAULT_ADDR
>+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT                                       0x0
>+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK                                         0xFFFFFFFFL
>+//DMCUB_SEC_CNTL
>+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT                                                              0x0
>+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT                                                              0x8
>+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT                                                                0x10
>+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT                                                   0x11
>+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT                                                        0x14
>+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT                                                         0x15
>+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT                                                   0x18
>+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT                                                   0x19
>+#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK                                                                0x00000007L
>+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK                                                                0x00003F00L
>+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK                                                                  0x00010000L
>+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK                                                     0x00020000L
>+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK                                                          0x00100000L
>+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK                                                           0x00200000L
>+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK                                                     0x01000000L
>+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK                                                     0x02000000L
>+//DMCUB_MEM_CNTL
>+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT                                                            0x0
>+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT                                                             0x4
>+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE__SHIFT                                                          0x8
>+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE__SHIFT                                                           0xc
>+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK                                                              0x0000000FL
>+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK                                                               0x000000F0L
>+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_SPACE_MASK                                                            0x00000700L
>+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_SPACE_MASK                                                             0x00007000L
>+//DMCUB_INBOX0_BASE_ADDRESS
>+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT                                           0x0
>+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
>+//DMCUB_INBOX0_SIZE
>+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT                                                           0x0
>+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK                                                             0xFFFFFFFFL
>+//DMCUB_INBOX0_WPTR
>+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT                                                           0x0
>+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK                                                             0xFFFFFFFFL
>+//DMCUB_INBOX0_RPTR
>+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT                                                           0x0
>+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK                                                             0xFFFFFFFFL
>+//DMCUB_INBOX1_BASE_ADDRESS
>+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT                                           0x0
>+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
>+//DMCUB_INBOX1_SIZE
>+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT                                                           0x0
>+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK                                                             0xFFFFFFFFL
>+//DMCUB_INBOX1_WPTR
>+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT                                                           0x0
>+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK                                                             0xFFFFFFFFL
>+//DMCUB_INBOX1_RPTR
>+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT                                                           0x0
>+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK                                                             0xFFFFFFFFL
>+//DMCUB_OUTBOX0_BASE_ADDRESS
>+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT                                         0x0
>+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
>+//DMCUB_OUTBOX0_SIZE
>+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT                                                         0x0
>+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK                                                           0xFFFFFFFFL
>+//DMCUB_OUTBOX0_WPTR
>+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT                                                         0x0
>+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK                                                           0xFFFFFFFFL
>+//DMCUB_OUTBOX0_RPTR
>+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT                                                         0x0
>+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK                                                           0xFFFFFFFFL
>+//DMCUB_OUTBOX1_BASE_ADDRESS
>+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT                                         0x0
>+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
>+//DMCUB_OUTBOX1_SIZE
>+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT                                                         0x0
>+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK                                                           0xFFFFFFFFL
>+//DMCUB_OUTBOX1_WPTR
>+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT                                                         0x0
>+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK                                                           0xFFFFFFFFL
>+//DMCUB_OUTBOX1_RPTR
>+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT                                                         0x0
>+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK                                                           0xFFFFFFFFL
>+//DMCUB_TIMER_TRIGGER0
>+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT                                                     0x0
>+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK                                                       0xFFFFFFFFL
>+//DMCUB_TIMER_TRIGGER1
>+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT                                                     0x0
>+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK                                                       0xFFFFFFFFL
>+//DMCUB_TIMER_WINDOW
>+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT                                                         0x0
>+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK                                                           0x00000007L
>+//DMCUB_SCRATCH0
>+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT                                                                 0x0
>+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK                                                                   0xFFFFFFFFL
>+//DMCUB_SCRATCH1
>+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT                                                                 0x0
>+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK                                                                   0xFFFFFFFFL
>+//DMCUB_SCRATCH2
>+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT                                                                 0x0
>+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK                                                                   0xFFFFFFFFL
>+//DMCUB_SCRATCH3
>+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT                                                                 0x0
>+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK                                                                   0xFFFFFFFFL
>+//DMCUB_SCRATCH4
>+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT                                                                 0x0
>+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK                                                                   0xFFFFFFFFL
>+//DMCUB_SCRATCH5
>+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT                                                                 0x0
>+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK                                                                   0xFFFFFFFFL
>+//DMCUB_SCRATCH6
>+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT                                                                 0x0
>+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK                                                                   0xFFFFFFFFL
>+//DMCUB_SCRATCH7
>+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT                                                                 0x0
>+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK                                                                   0xFFFFFFFFL
>+//DMCUB_SCRATCH8
>+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT                                                                 0x0
>+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK                                                                   0xFFFFFFFFL
>+//DMCUB_SCRATCH9
>+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT                                                                 0x0
>+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK                                                                   0xFFFFFFFFL
>+//DMCUB_SCRATCH10
>+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT                                                               0x0
>+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK                                                                 0xFFFFFFFFL
>+//DMCUB_SCRATCH11
>+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT                                                               0x0
>+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK                                                                 0xFFFFFFFFL
>+//DMCUB_SCRATCH12
>+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT                                                               0x0
>+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK                                                                 0xFFFFFFFFL
>+//DMCUB_SCRATCH13
>+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT                                                               0x0
>+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK                                                                 0xFFFFFFFFL
>+//DMCUB_SCRATCH14
>+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT                                                               0x0
>+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK                                                                 0xFFFFFFFFL
>+//DMCUB_SCRATCH15
>+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT                                                               0x0
>+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK                                                                 0xFFFFFFFFL
>+//DMCUB_CNTL
>+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT                                                                0x0
>+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT                                                          0x8
>+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT                                                                       0x10
>+#define DMCUB_CNTL__DMCUB_SOFT_RESET__SHIFT                                                                   0x11
>+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT                                                      0x12
>+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT                                                                 0x13
>+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT                                                            0x14
>+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK                                                                  0x000000FFL
>+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK                                                            0x00000100L
>+#define DMCUB_CNTL__DMCUB_ENABLE_MASK                                                                         0x00010000L
>+#define DMCUB_CNTL__DMCUB_SOFT_RESET_MASK                                                                     0x00020000L
>+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK                                                        0x00040000L
>+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK                                                                   0x00080000L
>+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK                                                              0x00100000L
>+//DMCUB_GPINT_DATAIN0
>+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT                                                       0x0
>+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK                                                         0xFFFFFFFFL
>+//DMCUB_GPINT_DATAIN1
>+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT                                                       0x0
>+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK                                                         0xFFFFFFFFL
>+//DMCUB_GPINT_DATAOUT
>+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT                                                       0x0
>+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK                                                         0xFFFFFFFFL
>+//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR
>+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT                         0x0
>+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK                           0xFFFFFFFFL
>+//DMCUB_LS_WAKE_INT_ENABLE
>+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT                                             0x0
>+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK                                               0xFFFFFFFFL
>+//DMCUB_MEM_PWR_CNTL
>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT                                                        0x1
>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT                                                          0x3
>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT                                                        0x4
>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK                                                          0x00000006L
>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK                                                            0x00000008L
>+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK                                                          0x00000030L
>+//DMCUB_TIMER_CURRENT
>+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT                                                       0x0
>+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK                                                         0xFFFFFFFFL
>+//DMCUB_PROC_ID
>+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT                                                                   0x0
>+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK                                                                     0x0000FFFFL
>+
>+
>+// addressBlock: dce_dc_mmhubbub_mcif_wb2_dispdec
>+//MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                      0x0
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT                                   0x1
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                   0x4
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                  0x5
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                             0x6
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                           0x7
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                     0x8
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT                                             0x10
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                  0x18
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                        0x00000001L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK                                     0x00000002L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                     0x00000010L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                    0x00000020L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                               0x00000040L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                             0x00000080L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                       0x00000F00L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK                                               0x000F0000L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                    0x01000000L
>+//MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R
>+#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT                                  0x0
>+#define MCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK                                    0x00001FFFL
>+//MCIF_WB2_MCIF_WB_BUFMGR_STATUS
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                  0x0
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                   0x1
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                           0x2
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                         0x4
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                    0x7
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                          0x8
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                      0xc
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                        0x1c
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                    0x00000001L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                     0x00000002L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                             0x00000004L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                           0x00000070L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                      0x00000080L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                            0x00000F00L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                        0x01FFF000L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                          0x70000000L
>+//MCIF_WB2_MCIF_WB_BUF_PITCH
>+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                             0x8
>+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                           0x18
>+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                               0x0000FF00L
>+#define MCIF_WB2_MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                             0xFF000000L
>+//MCIF_WB2_MCIF_WB_BUF_1_STATUS
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                            0x0
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                         0x1
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                        0x2
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                          0x3
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                           0x4
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                              0x5
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                            0x8
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                           0xc
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT                                             0xf
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                        0x10
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT                                   0x1d
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT                                  0x1e
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT                                0x1f
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                              0x00000001L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                           0x00000002L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                          0x00000004L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                            0x00000008L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                             0x00000010L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                0x000000E0L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                              0x00000F00L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                             0x00007000L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK                                               0x00008000L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                          0x1FFF0000L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK                                     0x20000000L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK                                    0x40000000L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
>+//MCIF_WB2_MCIF_WB_BUF_1_STATUS2
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT                                       0x0
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                      0xd
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                      0xe
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                  0xf
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                              0x10
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                        0x11
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                        0x12
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                         0x13
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK                                         0x00001FFFL
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                        0x00002000L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                        0x00004000L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                0x00010000L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                          0x00020000L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                          0x00040000L
>+#define MCIF_WB2_MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                           0x00080000L
>+//MCIF_WB2_MCIF_WB_BUF_2_STATUS
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                            0x0
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                         0x1
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                        0x2
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                          0x3
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                           0x4
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                              0x5
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                            0x8
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                           0xc
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT                                             0xf
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                        0x10
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT                                   0x1d
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT                                  0x1e
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT                                0x1f
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                              0x00000001L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                           0x00000002L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                          0x00000004L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                            0x00000008L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                             0x00000010L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                0x000000E0L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                              0x00000F00L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                             0x00007000L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK                                               0x00008000L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                          0x1FFF0000L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK                                     0x20000000L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK                                    0x40000000L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
>+//MCIF_WB2_MCIF_WB_BUF_2_STATUS2
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT                                       0x0
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                      0xd
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                      0xe
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                  0xf
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                              0x10
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                        0x11
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                        0x12
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                         0x13
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK                                         0x00001FFFL
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                        0x00002000L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                        0x00004000L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                0x00010000L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                          0x00020000L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                          0x00040000L
>+#define MCIF_WB2_MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                           0x00080000L
>+//MCIF_WB2_MCIF_WB_BUF_3_STATUS
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                            0x0
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                         0x1
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                        0x2
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                          0x3
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                           0x4
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                              0x5
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                            0x8
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                           0xc
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT                                             0xf
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                        0x10
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT                                   0x1d
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT                                  0x1e
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT                                0x1f
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                              0x00000001L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                           0x00000002L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                          0x00000004L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                            0x00000008L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                             0x00000010L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                0x000000E0L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                              0x00000F00L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                             0x00007000L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK                                               0x00008000L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                          0x1FFF0000L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK                                     0x20000000L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK                                    0x40000000L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
>+//MCIF_WB2_MCIF_WB_BUF_3_STATUS2
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT                                       0x0
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                      0xd
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                      0xe
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                  0xf
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                              0x10
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                        0x11
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                        0x12
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                         0x13
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK                                         0x00001FFFL
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                        0x00002000L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                        0x00004000L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                0x00010000L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                          0x00020000L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                          0x00040000L
>+#define MCIF_WB2_MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                           0x00080000L
>+//MCIF_WB2_MCIF_WB_BUF_4_STATUS
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                            0x0
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                         0x1
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                        0x2
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                          0x3
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                           0x4
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                              0x5
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                            0x8
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                           0xc
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT                                             0xf
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                        0x10
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT                                   0x1d
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT                                  0x1e
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT                                0x1f
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                              0x00000001L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                           0x00000002L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                          0x00000004L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                            0x00000008L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                             0x00000010L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                0x000000E0L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                              0x00000F00L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                             0x00007000L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK                                               0x00008000L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                          0x1FFF0000L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK                                     0x20000000L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK                                    0x40000000L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK                                  0x80000000L
>+//MCIF_WB2_MCIF_WB_BUF_4_STATUS2
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT                                       0x0
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                      0xd
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                      0xe
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                  0xf
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                              0x10
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                        0x11
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                        0x12
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                         0x13
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK                                         0x00001FFFL
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                        0x00002000L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                        0x00004000L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                    0x00008000L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                0x00010000L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                          0x00020000L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                          0x00040000L
>+#define MCIF_WB2_MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                           0x00080000L
>+//MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL
>+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                         0x0
>+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                   0x16
>+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                           0x00000003L
>+#define MCIF_WB2_MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                     0xFFC00000L
>+//MCIF_WB2_MCIF_WB_SCLK_CHANGE
>+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                           0x0
>+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                       0x1
>+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                             0x00000001L
>+#define MCIF_WB2_MCIF_WB_SCLK_CHANGE__MCIF_WB_CLI_WATERMARK_MASK_MASK                                         0x0000000EL
>+//MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX
>+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT                                    0x0
>+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT                                 0x8
>+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK                                      0x000000FFL
>+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK                                   0x00000100L
>+//MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA
>+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT                                      0x0
>+#define MCIF_WB2_MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK                                        0xFFFFFFFFL
>+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y
>+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                            0x0
>+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                              0xFFFFFFFFL
>+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET
>+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT                              0x0
>+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C
>+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                            0x0
>+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                              0xFFFFFFFFL
>+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET
>+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT                              0x0
>+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y
>+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                            0x0
>+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                              0xFFFFFFFFL
>+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET
>+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT                              0x0
>+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C
>+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                            0x0
>+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                              0xFFFFFFFFL
>+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET
>+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT                              0x0
>+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y
>+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                            0x0
>+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                              0xFFFFFFFFL
>+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET
>+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT                              0x0
>+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C
>+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                            0x0
>+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                              0xFFFFFFFFL
>+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET
>+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT                              0x0
>+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y
>+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                            0x0
>+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                              0xFFFFFFFFL
>+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET
>+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT                              0x0
>+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C
>+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                            0x0
>+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                              0xFFFFFFFFL
>+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET
>+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT                              0x0
>+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK                                0x0003FFFFL
>+//MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL
>+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                            0x0
>+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                 0x4
>+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                0x5
>+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                           0x6
>+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                   0x8
>+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                 0x10
>+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                              0x00000001L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                   0x00000010L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                  0x00000020L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                             0x00000040L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                     0x00000F00L
>+#define MCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                   0x1FFF0000L
>+//MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
>+#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT               0x0
>+#define MCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                 0x0007FFFFL
>+//MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL
>+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT                     0x0
>+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                  0x1
>+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT                                 0x2
>+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                            0x4
>+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK                       0x00000001L
>+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                    0x00000002L
>+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK                                   0x00000004L
>+#define MCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                              0x00000070L
>+//MCIF_WB2_MCIF_WB_WATERMARK
>+#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                              0x0
>+#define MCIF_WB2_MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                0x0000FFFFL
>+//MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL
>+#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                         0x0
>+#define MCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                           0x00000001L
>+//MCIF_WB2_MCIF_WB_WARM_UP_CNTL
>+#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP__SHIFT                                       0x8
>+#define MCIF_WB2_MCIF_WB_WARM_UP_CNTL__MCIF_WB_PITCH_SIZE_WARMUP_MASK                                         0x0000FF00L
>+//MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL
>+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT                                0x0
>+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                   0x1
>+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK                                  0x00000001L
>+#define MCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                     0x00000002L
>+//MCIF_WB2_MULTI_LEVEL_QOS_CTRL
>+#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                       0x0
>+#define MCIF_WB2_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                         0x003FFFFFL
>+//MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE
>+#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                          0x0
>+#define MCIF_WB2_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                            0x000FFFFFL
>+//MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE
>+#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                      0x0
>+#define MCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                        0x000FFFFFL
>+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH
>+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                  0x0
>+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH
>+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                  0x0
>+#define MCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH
>+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                  0x0
>+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH
>+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                  0x0
>+#define MCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH
>+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                  0x0
>+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH
>+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                  0x0
>+#define MCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH
>+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                  0x0
>+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH
>+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                  0x0
>+#define MCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                    0x000000FFL
>+//MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION
>+#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                              0x0
>+#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                             0x10
>+#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                0x00001FFFL
>+#define MCIF_WB2_MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
>+//MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION
>+#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                              0x0
>+#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                             0x10
>+#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                0x00001FFFL
>+#define MCIF_WB2_MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
>+//MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION
>+#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                              0x0
>+#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                             0x10
>+#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                0x00001FFFL
>+#define MCIF_WB2_MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
>+//MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION
>+#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                              0x0
>+#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                             0x10
>+#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                0x00001FFFL
>+#define MCIF_WB2_MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                               0x1FFF0000L
>+
>+
>+// addressBlock: dce_dc_dchvm_hvm_dispdec
>+//DCHVM_CTRL0
>+#define DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT                                                                   0x0
>+#define DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK                                                                     0x00000001L
>+//DCHVM_CTRL1
>+#define DCHVM_CTRL1__DUMMY1__SHIFT                                                                            0x0
>+#define DCHVM_CTRL1__DUMMY1_MASK                                                                              0xFFFFFFFFL
>+//DCHVM_CLK_CTRL
>+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT                                                         0x0
>+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT                                                         0x1
>+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT                                                          0x4
>+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT                                                          0x5
>+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT                                                          0x8
>+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT                                                         0xa
>+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK                                                           0x00000001L
>+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK                                                           0x00000002L
>+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK                                                            0x00000010L
>+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK                                                            0x00000020L
>+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK                                                            0x00000300L
>+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK                                                           0x00000C00L
>+//DCHVM_MEM_CTRL
>+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT                                                       0x0
>+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT                                                         0x2
>+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT                                                      0x4
>+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK                                                         0x00000001L
>+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK                                                           0x0000000CL
>+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK                                                        0x00000030L
>+//DCHVM_RIOMMU_CTRL0
>+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT                                                        0x0
>+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT                                                         0x1
>+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK                                                          0x00000001L
>+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK                                                           0x00000002L
>+//DCHVM_RIOMMU_STAT0
>+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT                                                              0x0
>+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT                                                       0x1
>+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK                                                                0x00000001L
>+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK                                                         0x00000002L
>+
>+
>+// addressBlock: vga_vgaseqind
>+//SEQ00
>+#define SEQ00__SEQ_RST0B__SHIFT                                                                               0x0
>+#define SEQ00__SEQ_RST1B__SHIFT                                                                               0x1
>+#define SEQ00__SEQ_RST0B_MASK                                                                                 0x01L
>+#define SEQ00__SEQ_RST1B_MASK                                                                                 0x02L
>+//SEQ01
>+#define SEQ01__SEQ_DOT8__SHIFT                                                                                0x0
>+#define SEQ01__SEQ_SHIFT2__SHIFT                                                                              0x2
>+#define SEQ01__SEQ_PCLKBY2__SHIFT                                                                             0x3
>+#define SEQ01__SEQ_SHIFT4__SHIFT                                                                              0x4
>+#define SEQ01__SEQ_MAXBW__SHIFT                                                                               0x5
>+#define SEQ01__SEQ_DOT8_MASK                                                                                  0x01L
>+#define SEQ01__SEQ_SHIFT2_MASK                                                                                0x04L
>+#define SEQ01__SEQ_PCLKBY2_MASK                                                                               0x08L
>+#define SEQ01__SEQ_SHIFT4_MASK                                                                                0x10L
>+#define SEQ01__SEQ_MAXBW_MASK                                                                                 0x20L
>+//SEQ02
>+#define SEQ02__SEQ_MAP0_EN__SHIFT                                                                             0x0
>+#define SEQ02__SEQ_MAP1_EN__SHIFT                                                                             0x1
>+#define SEQ02__SEQ_MAP2_EN__SHIFT                                                                             0x2
>+#define SEQ02__SEQ_MAP3_EN__SHIFT                                                                             0x3
>+#define SEQ02__SEQ_MAP0_EN_MASK                                                                               0x01L
>+#define SEQ02__SEQ_MAP1_EN_MASK                                                                               0x02L
>+#define SEQ02__SEQ_MAP2_EN_MASK                                                                               0x04L
>+#define SEQ02__SEQ_MAP3_EN_MASK                                                                               0x08L
>+//SEQ03
>+#define SEQ03__SEQ_FONT_B1__SHIFT                                                                             0x0
>+#define SEQ03__SEQ_FONT_B2__SHIFT                                                                             0x1
>+#define SEQ03__SEQ_FONT_A1__SHIFT                                                                             0x2
>+#define SEQ03__SEQ_FONT_A2__SHIFT                                                                             0x3
>+#define SEQ03__SEQ_FONT_B0__SHIFT                                                                             0x4
>+#define SEQ03__SEQ_FONT_A0__SHIFT                                                                             0x5
>+#define SEQ03__SEQ_FONT_B1_MASK                                                                               0x01L
>+#define SEQ03__SEQ_FONT_B2_MASK                                                                               0x02L
>+#define SEQ03__SEQ_FONT_A1_MASK                                                                               0x04L
>+#define SEQ03__SEQ_FONT_A2_MASK                                                                               0x08L
>+#define SEQ03__SEQ_FONT_B0_MASK                                                                               0x10L
>+#define SEQ03__SEQ_FONT_A0_MASK                                                                               0x20L
>+//SEQ04
>+#define SEQ04__SEQ_256K__SHIFT                                                                                0x1
>+#define SEQ04__SEQ_ODDEVEN__SHIFT                                                                             0x2
>+#define SEQ04__SEQ_CHAIN__SHIFT                                                                               0x3
>+#define SEQ04__SEQ_256K_MASK                                                                                  0x02L
>+#define SEQ04__SEQ_ODDEVEN_MASK                                                                               0x04L
>+#define SEQ04__SEQ_CHAIN_MASK                                                                                 0x08L
>+
>+
>+// addressBlock: vga_vgacrtind
>+//CRT00
>+#define CRT00__H_TOTAL__SHIFT                                                                                 0x0
>+#define CRT00__H_TOTAL_MASK                                                                                   0xFFL
>+//CRT01
>+#define CRT01__H_DISP_END__SHIFT                                                                              0x0
>+#define CRT01__H_DISP_END_MASK                                                                                0xFFL
>+//CRT02
>+#define CRT02__H_BLANK_START__SHIFT                                                                           0x0
>+#define CRT02__H_BLANK_START_MASK                                                                             0xFFL
>+//CRT03
>+#define CRT03__H_BLANK_END__SHIFT                                                                             0x0
>+#define CRT03__H_DE_SKEW__SHIFT                                                                               0x5
>+#define CRT03__CR10CR11_R_DIS_B__SHIFT                                                                        0x7
>+#define CRT03__H_BLANK_END_MASK                                                                               0x1FL
>+#define CRT03__H_DE_SKEW_MASK                                                                                 0x60L
>+#define CRT03__CR10CR11_R_DIS_B_MASK                                                                          0x80L
>+//CRT04
>+#define CRT04__H_SYNC_START__SHIFT                                                                            0x0
>+#define CRT04__H_SYNC_START_MASK                                                                              0xFFL
>+//CRT05
>+#define CRT05__H_SYNC_END__SHIFT                                                                              0x0
>+#define CRT05__H_SYNC_SKEW__SHIFT                                                                             0x5
>+#define CRT05__H_BLANK_END_B5__SHIFT                                                                          0x7
>+#define CRT05__H_SYNC_END_MASK                                                                                0x1FL
>+#define CRT05__H_SYNC_SKEW_MASK                                                                               0x60L
>+#define CRT05__H_BLANK_END_B5_MASK                                                                            0x80L
>+//CRT06
>+#define CRT06__V_TOTAL__SHIFT                                                                                 0x0
>+#define CRT06__V_TOTAL_MASK                                                                                   0xFFL
>+//CRT07
>+#define CRT07__V_TOTAL_B8__SHIFT                                                                              0x0
>+#define CRT07__V_DISP_END_B8__SHIFT                                                                           0x1
>+#define CRT07__V_SYNC_START_B8__SHIFT                                                                         0x2
>+#define CRT07__V_BLANK_START_B8__SHIFT                                                                        0x3
>+#define CRT07__LINE_CMP_B8__SHIFT                                                                             0x4
>+#define CRT07__V_TOTAL_B9__SHIFT                                                                              0x5
>+#define CRT07__V_DISP_END_B9__SHIFT                                                                           0x6
>+#define CRT07__V_SYNC_START_B9__SHIFT                                                                         0x7
>+#define CRT07__V_TOTAL_B8_MASK                                                                                0x01L
>+#define CRT07__V_DISP_END_B8_MASK                                                                             0x02L
>+#define CRT07__V_SYNC_START_B8_MASK                                                                           0x04L
>+#define CRT07__V_BLANK_START_B8_MASK                                                                          0x08L
>+#define CRT07__LINE_CMP_B8_MASK                                                                               0x10L
>+#define CRT07__V_TOTAL_B9_MASK                                                                                0x20L
>+#define CRT07__V_DISP_END_B9_MASK                                                                             0x40L
>+#define CRT07__V_SYNC_START_B9_MASK                                                                           0x80L
>+//CRT08
>+#define CRT08__ROW_SCAN_START__SHIFT                                                                          0x0
>+#define CRT08__BYTE_PAN__SHIFT                                                                                0x5
>+#define CRT08__ROW_SCAN_START_MASK                                                                            0x1FL
>+#define CRT08__BYTE_PAN_MASK                                                                                  0x60L
>+//CRT09
>+#define CRT09__MAX_ROW_SCAN__SHIFT                                                                            0x0
>+#define CRT09__V_BLANK_START_B9__SHIFT                                                                        0x5
>+#define CRT09__LINE_CMP_B9__SHIFT                                                                             0x6
>+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT                                                                      0x7
>+#define CRT09__MAX_ROW_SCAN_MASK                                                                              0x1FL
>+#define CRT09__V_BLANK_START_B9_MASK                                                                          0x20L
>+#define CRT09__LINE_CMP_B9_MASK                                                                               0x40L
>+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK                                                                        0x80L
>+//CRT0A
>+#define CRT0A__CURSOR_START__SHIFT                                                                            0x0
>+#define CRT0A__CURSOR_DISABLE__SHIFT                                                                          0x5
>+#define CRT0A__CURSOR_START_MASK                                                                              0x1FL
>+#define CRT0A__CURSOR_DISABLE_MASK                                                                            0x20L
>+//CRT0B
>+#define CRT0B__CURSOR_END__SHIFT                                                                              0x0
>+#define CRT0B__CURSOR_SKEW__SHIFT                                                                             0x5
>+#define CRT0B__CURSOR_END_MASK                                                                                0x1FL
>+#define CRT0B__CURSOR_SKEW_MASK                                                                               0x60L
>+//CRT0C
>+#define CRT0C__DISP_START__SHIFT                                                                              0x0
>+#define CRT0C__DISP_START_MASK                                                                                0xFFL
>+//CRT0D
>+#define CRT0D__DISP_START__SHIFT                                                                              0x0
>+#define CRT0D__DISP_START_MASK                                                                                0xFFL
>+//CRT0E
>+#define CRT0E__CURSOR_LOC_HI__SHIFT                                                                           0x0
>+#define CRT0E__CURSOR_LOC_HI_MASK                                                                             0xFFL
>+//CRT0F
>+#define CRT0F__CURSOR_LOC_LO__SHIFT                                                                           0x0
>+#define CRT0F__CURSOR_LOC_LO_MASK                                                                             0xFFL
>+//CRT10
>+#define CRT10__V_SYNC_START__SHIFT                                                                            0x0
>+#define CRT10__V_SYNC_START_MASK                                                                              0xFFL
>+//CRT11
>+#define CRT11__V_SYNC_END__SHIFT                                                                              0x0
>+#define CRT11__V_INTR_CLR__SHIFT                                                                              0x4
>+#define CRT11__V_INTR_EN__SHIFT                                                                               0x5
>+#define CRT11__SEL5_REFRESH_CYC__SHIFT                                                                        0x6
>+#define CRT11__C0T7_WR_ONLY__SHIFT                                                                            0x7
>+#define CRT11__V_SYNC_END_MASK                                                                                0x0FL
>+#define CRT11__V_INTR_CLR_MASK                                                                                0x10L
>+#define CRT11__V_INTR_EN_MASK                                                                                 0x20L
>+#define CRT11__SEL5_REFRESH_CYC_MASK                                                                          0x40L
>+#define CRT11__C0T7_WR_ONLY_MASK                                                                              0x80L
>+//CRT12
>+#define CRT12__V_DISP_END__SHIFT                                                                              0x0
>+#define CRT12__V_DISP_END_MASK                                                                                0xFFL
>+//CRT13
>+#define CRT13__DISP_PITCH__SHIFT                                                                              0x0
>+#define CRT13__DISP_PITCH_MASK                                                                                0xFFL
>+//CRT14
>+#define CRT14__UNDRLN_LOC__SHIFT                                                                              0x0
>+#define CRT14__ADDR_CNT_BY4__SHIFT                                                                            0x5
>+#define CRT14__DOUBLE_WORD__SHIFT                                                                             0x6
>+#define CRT14__UNDRLN_LOC_MASK                                                                                0x1FL
>+#define CRT14__ADDR_CNT_BY4_MASK                                                                              0x20L
>+#define CRT14__DOUBLE_WORD_MASK                                                                               0x40L
>+//CRT15
>+#define CRT15__V_BLANK_START__SHIFT                                                                           0x0
>+#define CRT15__V_BLANK_START_MASK                                                                             0xFFL
>+//CRT16
>+#define CRT16__V_BLANK_END__SHIFT                                                                             0x0
>+#define CRT16__V_BLANK_END_MASK                                                                               0xFFL
>+//CRT17
>+#define CRT17__RA0_AS_A13B__SHIFT                                                                             0x0
>+#define CRT17__RA1_AS_A14B__SHIFT                                                                             0x1
>+#define CRT17__VCOUNT_BY2__SHIFT                                                                              0x2
>+#define CRT17__ADDR_CNT_BY2__SHIFT                                                                            0x3
>+#define CRT17__WRAP_A15TOA0__SHIFT                                                                            0x5
>+#define CRT17__BYTE_MODE__SHIFT                                                                               0x6
>+#define CRT17__CRTC_SYNC_EN__SHIFT                                                                            0x7
>+#define CRT17__RA0_AS_A13B_MASK                                                                               0x01L
>+#define CRT17__RA1_AS_A14B_MASK                                                                               0x02L
>+#define CRT17__VCOUNT_BY2_MASK                                                                                0x04L
>+#define CRT17__ADDR_CNT_BY2_MASK                                                                              0x08L
>+#define CRT17__WRAP_A15TOA0_MASK                                                                              0x20L
>+#define CRT17__BYTE_MODE_MASK                                                                                 0x40L
>+#define CRT17__CRTC_SYNC_EN_MASK                                                                              0x80L
>+//CRT18
>+#define CRT18__LINE_CMP__SHIFT                                                                                0x0
>+#define CRT18__LINE_CMP_MASK                                                                                  0xFFL
>+//CRT1E
>+#define CRT1E__GRPH_DEC_RD1__SHIFT                                                                            0x1
>+#define CRT1E__GRPH_DEC_RD1_MASK                                                                              0x02L
>+//CRT1F
>+#define CRT1F__GRPH_DEC_RD0__SHIFT                                                                            0x0
>+#define CRT1F__GRPH_DEC_RD0_MASK                                                                              0xFFL
>+//CRT22
>+#define CRT22__GRPH_LATCH_DATA__SHIFT                                                                         0x0
>+#define CRT22__GRPH_LATCH_DATA_MASK                                                                           0xFFL
>+
>+
>+// addressBlock: vga_vgagrphind
>+//GRA00
>+#define GRA00__GRPH_SET_RESET0__SHIFT                                                                         0x0
>+#define GRA00__GRPH_SET_RESET1__SHIFT                                                                         0x1
>+#define GRA00__GRPH_SET_RESET2__SHIFT                                                                         0x2
>+#define GRA00__GRPH_SET_RESET3__SHIFT                                                                         0x3
>+#define GRA00__GRPH_SET_RESET0_MASK                                                                           0x01L
>+#define GRA00__GRPH_SET_RESET1_MASK                                                                           0x02L
>+#define GRA00__GRPH_SET_RESET2_MASK                                                                           0x04L
>+#define GRA00__GRPH_SET_RESET3_MASK                                                                           0x08L
>+//GRA01
>+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT                                                                     0x0
>+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT                                                                     0x1
>+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT                                                                     0x2
>+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT                                                                     0x3
>+#define GRA01__GRPH_SET_RESET_ENA0_MASK                                                                       0x01L
>+#define GRA01__GRPH_SET_RESET_ENA1_MASK                                                                       0x02L
>+#define GRA01__GRPH_SET_RESET_ENA2_MASK                                                                       0x04L
>+#define GRA01__GRPH_SET_RESET_ENA3_MASK                                                                       0x08L
>+//GRA02
>+#define GRA02__GRPH_CCOMP__SHIFT                                                                              0x0
>+#define GRA02__GRPH_CCOMP_MASK                                                                                0x0FL
>+//GRA03
>+#define GRA03__GRPH_ROTATE__SHIFT                                                                             0x0
>+#define GRA03__GRPH_FN_SEL__SHIFT                                                                             0x3
>+#define GRA03__GRPH_ROTATE_MASK                                                                               0x07L
>+#define GRA03__GRPH_FN_SEL_MASK                                                                               0x18L
>+//GRA04
>+#define GRA04__GRPH_RMAP__SHIFT                                                                               0x0
>+#define GRA04__GRPH_RMAP_MASK                                                                                 0x03L
>+//GRA05
>+#define GRA05__GRPH_WRITE_MODE__SHIFT                                                                         0x0
>+#define GRA05__GRPH_READ1__SHIFT                                                                              0x3
>+#define GRA05__CGA_ODDEVEN__SHIFT                                                                             0x4
>+#define GRA05__GRPH_OES__SHIFT                                                                                0x5
>+#define GRA05__GRPH_PACK__SHIFT                                                                               0x6
>+#define GRA05__GRPH_WRITE_MODE_MASK                                                                           0x03L
>+#define GRA05__GRPH_READ1_MASK                                                                                0x08L
>+#define GRA05__CGA_ODDEVEN_MASK                                                                               0x10L
>+#define GRA05__GRPH_OES_MASK                                                                                  0x20L
>+#define GRA05__GRPH_PACK_MASK                                                                                 0x40L
>+//GRA06
>+#define GRA06__GRPH_GRAPHICS__SHIFT                                                                           0x0
>+#define GRA06__GRPH_ODDEVEN__SHIFT                                                                            0x1
>+#define GRA06__GRPH_ADRSEL__SHIFT                                                                             0x2
>+#define GRA06__GRPH_GRAPHICS_MASK                                                                             0x01L
>+#define GRA06__GRPH_ODDEVEN_MASK                                                                              0x02L
>+#define GRA06__GRPH_ADRSEL_MASK                                                                               0x0CL
>+//GRA07
>+#define GRA07__GRPH_XCARE0__SHIFT                                                                             0x0
>+#define GRA07__GRPH_XCARE1__SHIFT                                                                             0x1
>+#define GRA07__GRPH_XCARE2__SHIFT                                                                             0x2
>+#define GRA07__GRPH_XCARE3__SHIFT                                                                             0x3
>+#define GRA07__GRPH_XCARE0_MASK                                                                               0x01L
>+#define GRA07__GRPH_XCARE1_MASK                                                                               0x02L
>+#define GRA07__GRPH_XCARE2_MASK                                                                               0x04L
>+#define GRA07__GRPH_XCARE3_MASK                                                                               0x08L
>+//GRA08
>+#define GRA08__GRPH_BMSK__SHIFT                                                                               0x0
>+#define GRA08__GRPH_BMSK_MASK                                                                                 0xFFL
>+
>+
>+// addressBlock: vga_vgaattrind
>+//ATTR00
>+#define ATTR00__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR00__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR01
>+#define ATTR01__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR01__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR02
>+#define ATTR02__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR02__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR03
>+#define ATTR03__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR03__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR04
>+#define ATTR04__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR04__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR05
>+#define ATTR05__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR05__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR06
>+#define ATTR06__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR06__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR07
>+#define ATTR07__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR07__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR08
>+#define ATTR08__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR08__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR09
>+#define ATTR09__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR09__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR0A
>+#define ATTR0A__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR0A__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR0B
>+#define ATTR0B__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR0B__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR0C
>+#define ATTR0C__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR0C__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR0D
>+#define ATTR0D__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR0D__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR0E
>+#define ATTR0E__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR0E__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR0F
>+#define ATTR0F__ATTR_PAL__SHIFT                                                                               0x0
>+#define ATTR0F__ATTR_PAL_MASK                                                                                 0x3FL
>+//ATTR10
>+#define ATTR10__ATTR_GRPH_MODE__SHIFT                                                                         0x0
>+#define ATTR10__ATTR_MONO_EN__SHIFT                                                                           0x1
>+#define ATTR10__ATTR_LGRPH_EN__SHIFT                                                                          0x2
>+#define ATTR10__ATTR_BLINK_EN__SHIFT                                                                          0x3
>+#define ATTR10__ATTR_PANTOPONLY__SHIFT                                                                        0x5
>+#define ATTR10__ATTR_PCLKBY2__SHIFT                                                                           0x6
>+#define ATTR10__ATTR_CSEL_EN__SHIFT                                                                           0x7
>+#define ATTR10__ATTR_GRPH_MODE_MASK                                                                           0x01L
>+#define ATTR10__ATTR_MONO_EN_MASK                                                                             0x02L
>+#define ATTR10__ATTR_LGRPH_EN_MASK                                                                            0x04L
>+#define ATTR10__ATTR_BLINK_EN_MASK                                                                            0x08L
>+#define ATTR10__ATTR_PANTOPONLY_MASK                                                                          0x20L
>+#define ATTR10__ATTR_PCLKBY2_MASK                                                                             0x40L
>+#define ATTR10__ATTR_CSEL_EN_MASK                                                                             0x80L
>+//ATTR11
>+#define ATTR11__ATTR_OVSC__SHIFT                                                                              0x0
>+#define ATTR11__ATTR_OVSC_MASK                                                                                0xFFL
>+//ATTR12
>+#define ATTR12__ATTR_MAP_EN__SHIFT                                                                            0x0
>+#define ATTR12__ATTR_VSMUX__SHIFT                                                                             0x4
>+#define ATTR12__ATTR_MAP_EN_MASK                                                                              0x0FL
>+#define ATTR12__ATTR_VSMUX_MASK                                                                               0x30L
>+//ATTR13
>+#define ATTR13__ATTR_PPAN__SHIFT                                                                              0x0
>+#define ATTR13__ATTR_PPAN_MASK                                                                                0x0FL
>+//ATTR14
>+#define ATTR14__ATTR_CSEL1__SHIFT                                                                             0x0
>+#define ATTR14__ATTR_CSEL2__SHIFT                                                                             0x2
>+#define ATTR14__ATTR_CSEL1_MASK                                                                               0x03L
>+#define ATTR14__ATTR_CSEL2_MASK                                                                               0x0CL
>+
>+
>+// addressBlock: azendpoint_f2codecind
>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                         0x0
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                            0x4
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                        0x8
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                       0xb
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                           0xe
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                                0xf
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT                              0xf
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                           0x0000000FL
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                              0x00000070L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                          0x00000700L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                         0x00003800L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                             0x00004000L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                                  0x00008000L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK                                0x00008000L
>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                                0x0
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                                 0x4
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                                  0x0000000FL
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                                   0x000000F0L
>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                                     0x0
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                         0x1
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                      0x2
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                       0x3
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                      0x4
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                                 0x5
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                       0x6
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                         0x7
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                        0x8
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                                 0x17
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                       0x00000001L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                           0x00000002L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                        0x00000004L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                         0x00000008L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                        0x00000010L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                                   0x00000020L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                         0x00000040L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                           0x00000080L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                          0x00007F00L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                                   0x00800000L
>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT                                      0x0
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK                                        0x0000007FL
>+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
>+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                                       0x0
>+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                                    0x14
>+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                                         0x00000003L
>+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                                      0x00700000L
>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT                               0x7
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK                                 0x00000080L
>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                                         0x0
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                                           0x000000FFL
>+//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT            0x0
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT              0x1
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT             0x4
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK              0x00000001L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK                0x00000002L
>+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK               0x00000070L
>+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT                 0x4
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK                   0x00000010L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
>+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT              0x0
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT               0x10
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                0x00000FFFL
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                 0x001F0000L
>+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                             0x0
>+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                               0xFFFFFFFFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT              0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK                0xFFFFFFFFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
>+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                                         0x6
>+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                                           0x00000040L
>+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                          0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                       0x7
>+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                            0x0000003FL
>+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                         0x00000080L
>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                                0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                                0x1f
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                                  0x7FFFFFFFL
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                                  0x80000000L
>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                           0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT                0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                               0x8
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                              0xc
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT                    0x10
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT                     0x14
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                           0x18
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT                  0x1e
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                             0x0000000FL
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK                  0x000000F0L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                                 0x00000F00L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                                0x0000F000L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                      0x000F0000L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                       0x00F00000L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                             0x3F000000L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK                    0xC0000000L
>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                             0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                            0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                               0x0000000FL
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                              0x000000F0L
>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT                  0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT                   0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK                    0x0000000FL
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK                     0x000000F0L
>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                         0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT                0x6
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                           0x0000003FL
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK                  0x000000C0L
>+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT                    0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT                       0x8
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT                         0x9
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT                 0xa
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK                      0x0000007FL
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK                         0x00000100L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK                           0x00000200L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK                   0x0000FC00L
>+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
>+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                             0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                               0x000000FFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT                                  0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT                                         0x3
>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT                                    0x7
>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK                                    0x00000003L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK                                           0x00000078L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK                                      0x00000080L
>+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT                                     0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT                                      0x3
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT                            0x8
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT                                0x10
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT                     0x18
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK                                       0x00000007L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK                                        0x00000078L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK                              0x0000FF00L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK                                  0x00FF0000L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK                       0xFF000000L
>+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT                                  0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK                                    0xFFFFFFFFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT                       0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT                         0x1
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT                   0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK                         0x00000001L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK                           0x00000002L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK                     0x000000F0L
>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT                       0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT                         0x1
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT                   0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK                         0x00000001L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK                           0x00000002L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK                     0x000000F0L
>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT                       0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT                         0x1
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT                   0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK                         0x00000001L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK                           0x00000002L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK                     0x000000F0L
>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT                       0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT                         0x1
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT                   0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK                         0x00000001L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK                           0x00000002L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK                     0x000000F0L
>+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
>+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT                                             0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT                                             0x8
>+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK                                               0x000000FFL
>+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK                                               0x0000FF00L
>+//AZALIA_F2_CODEC_PIN_CONTROL_HBR
>+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                                   0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                                     0x00000001L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                      0x00000010L
>+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT                             0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK                               0x000000FFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT                                    0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK                                      0xFFFFFFFFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                         0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                           0x1
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT                     0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                           0x00000001L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                             0x00000002L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                       0x000000F0L
>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                         0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                           0x1
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT                     0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                           0x00000001L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                             0x00000002L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                       0x000000F0L
>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                         0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                           0x1
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT                     0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                           0x00000001L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                             0x00000002L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                       0x000000F0L
>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                         0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                           0x1
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT                     0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                           0x00000001L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                             0x00000002L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                       0x000000F0L
>+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                               0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                                 0x00000001L
>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                                   0x0
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT                          0x2
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                                     0x00000003L
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK                            0x0000003CL
>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT                         0x0
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT                0x2
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT                            0x3
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT                   0x7
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK                           0x00000003L
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK                  0x00000004L
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                              0x00000078L
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK                     0x00000080L
>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT                     0x0
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT            0x6
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK                       0x0000003FL
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK              0x00000040L
>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT            0x0
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT   0x4
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK              0x0000000FL
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK     0x00000010L
>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT               0x0
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT                     0x4
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                                 0x5
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT                           0x7
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK                 0x0000000FL
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK                       0x00000010L
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                                   0x00000060L
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK                             0x00000080L
>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT                       0x0
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT                       0x4
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK                         0x0000000FL
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK                         0x000000F0L
>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT                       0x0
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT                       0x4
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK                         0x0000000FL
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK                         0x000000F0L
>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT                       0x0
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT                       0x4
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK                         0x0000000FL
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK                         0x000000F0L
>+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT                       0x0
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT                       0x4
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK                         0x0000000FL
>+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK                         0x000000F0L
>+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
>+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                                         0x0
>+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                                           0xFFFFFFFFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
>+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                               0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                                 0x00000001L
>+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                          0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT                    0x8
>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                            0x00000001L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                      0x0000FF00L
>+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                                         0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                                           0xFFFFFFFFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                           0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                             0xFFFFFFFFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                                           0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                                             0x000000FFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                                     0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT                       0x1
>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                               0x8
>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT                             0x10
>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                                       0x00000001L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK                         0x00000002L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                                 0x0000FF00L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                               0x00FF0000L
>+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
>+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT   0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK     0x00000003L
>+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
>+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT                         0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT                     0x4
>+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK                           0x00000001L
>+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK                       0x00000010L
>+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT            0x0
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT               0x1
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT              0x2
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT          0x3
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                                0x5
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT                     0x6
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT       0x7
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                       0x8
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                               0x9
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                         0xa
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                               0xb
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT       0x10
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                                  0x14
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK              0x00000001L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK                 0x00000002L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK                0x00000004L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK            0x00000008L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                                  0x00000020L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                       0x00000040L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK         0x00000080L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                         0x00000100L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                                 0x00000200L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                           0x00000400L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                                 0x00000800L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK         0x000F0000L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                                    0x00F00000L
>+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                            0x0
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                                   0x1
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                          0x2
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                            0x3
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                                     0x4
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                      0x5
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                                  0x6
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                               0x7
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                       0x8
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                       0x10
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                                 0x18
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                              0x00000001L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                                     0x00000002L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                            0x00000004L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                              0x00000008L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                       0x00000010L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                        0x00000020L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                                    0x00000040L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                                 0x00000080L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                         0x0000FF00L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                         0x00010000L
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                                   0x01000000L
>+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK                     0xFFFFFFFFL
>+
>+
>+// addressBlock: azendpoint_descriptorind
>+//AUDIO_DESCRIPTOR0
>+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                                                                0x0
>+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
>+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
>+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
>+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                                                                  0x00000007L
>+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
>+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
>+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
>+//AUDIO_DESCRIPTOR1
>+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                                                                0x0
>+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
>+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
>+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
>+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                                                                  0x00000007L
>+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
>+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
>+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
>+//AUDIO_DESCRIPTOR2
>+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                                                                0x0
>+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
>+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
>+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
>+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                                                                  0x00000007L
>+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
>+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
>+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
>+//AUDIO_DESCRIPTOR3
>+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                                                                0x0
>+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
>+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
>+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
>+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                                                                  0x00000007L
>+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
>+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
>+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
>+//AUDIO_DESCRIPTOR4
>+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                                                                0x0
>+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
>+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
>+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
>+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                                                                  0x00000007L
>+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
>+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
>+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
>+//AUDIO_DESCRIPTOR5
>+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                                                                0x0
>+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
>+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
>+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
>+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                                                                  0x00000007L
>+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
>+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
>+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
>+//AUDIO_DESCRIPTOR6
>+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                                                                0x0
>+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
>+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
>+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
>+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                                                                  0x00000007L
>+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
>+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
>+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
>+//AUDIO_DESCRIPTOR7
>+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                                                                0x0
>+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
>+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
>+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
>+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                                                                  0x00000007L
>+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
>+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
>+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
>+//AUDIO_DESCRIPTOR8
>+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                                                                0x0
>+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
>+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
>+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
>+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                                                                  0x00000007L
>+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
>+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
>+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
>+//AUDIO_DESCRIPTOR9
>+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                                                                0x0
>+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
>+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
>+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
>+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                                                                  0x00000007L
>+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
>+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
>+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
>+//AUDIO_DESCRIPTOR10
>+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                                                               0x0
>+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
>+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
>+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
>+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                                                                 0x00000007L
>+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
>+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
>+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
>+//AUDIO_DESCRIPTOR11
>+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                                                               0x0
>+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
>+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
>+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
>+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                                                                 0x00000007L
>+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
>+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
>+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
>+//AUDIO_DESCRIPTOR12
>+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                                                               0x0
>+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
>+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
>+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
>+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                                                                 0x00000007L
>+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
>+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
>+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
>+//AUDIO_DESCRIPTOR13
>+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                                                               0x0
>+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
>+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
>+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
>+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                                                                 0x00000007L
>+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
>+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
>+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
>+
>+
>+// addressBlock: azendpoint_sinkinfoind
>+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT                                   0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK                                     0x0000FFFFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
>+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT                                             0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK                                               0x0000FFFFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
>+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT                         0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK                           0x000000FFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT                                                    0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK                                                      0xFFFFFFFFL
>+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
>+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT                                                    0x0
>+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK                                                      0xFFFFFFFFL
>+//SINK_DESCRIPTION0
>+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT                                                                 0x0
>+#define SINK_DESCRIPTION0__DESCRIPTION_MASK                                                                   0x000000FFL
>+//SINK_DESCRIPTION1
>+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT                                                                 0x0
>+#define SINK_DESCRIPTION1__DESCRIPTION_MASK                                                                   0x000000FFL
>+//SINK_DESCRIPTION2
>+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT                                                                 0x0
>+#define SINK_DESCRIPTION2__DESCRIPTION_MASK                                                                   0x000000FFL
>+//SINK_DESCRIPTION3
>+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT                                                                 0x0
>+#define SINK_DESCRIPTION3__DESCRIPTION_MASK                                                                   0x000000FFL
>+//SINK_DESCRIPTION4
>+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT                                                                 0x0
>+#define SINK_DESCRIPTION4__DESCRIPTION_MASK                                                                   0x000000FFL
>+//SINK_DESCRIPTION5
>+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT                                                                 0x0
>+#define SINK_DESCRIPTION5__DESCRIPTION_MASK                                                                   0x000000FFL
>+//SINK_DESCRIPTION6
>+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT                                                                 0x0
>+#define SINK_DESCRIPTION6__DESCRIPTION_MASK                                                                   0x000000FFL
>+//SINK_DESCRIPTION7
>+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT                                                                 0x0
>+#define SINK_DESCRIPTION7__DESCRIPTION_MASK                                                                   0x000000FFL
>+//SINK_DESCRIPTION8
>+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT                                                                 0x0
>+#define SINK_DESCRIPTION8__DESCRIPTION_MASK                                                                   0x000000FFL
>+//SINK_DESCRIPTION9
>+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT                                                                 0x0
>+#define SINK_DESCRIPTION9__DESCRIPTION_MASK                                                                   0x000000FFL
>+//SINK_DESCRIPTION10
>+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT                                                                0x0
>+#define SINK_DESCRIPTION10__DESCRIPTION_MASK                                                                  0x000000FFL
>+//SINK_DESCRIPTION11
>+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT                                                                0x0
>+#define SINK_DESCRIPTION11__DESCRIPTION_MASK                                                                  0x000000FFL
>+//SINK_DESCRIPTION12
>+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT                                                                0x0
>+#define SINK_DESCRIPTION12__DESCRIPTION_MASK                                                                  0x000000FFL
>+//SINK_DESCRIPTION13
>+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT                                                                0x0
>+#define SINK_DESCRIPTION13__DESCRIPTION_MASK                                                                  0x000000FFL
>+//SINK_DESCRIPTION14
>+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT                                                                0x0
>+#define SINK_DESCRIPTION14__DESCRIPTION_MASK                                                                  0x000000FFL
>+//SINK_DESCRIPTION15
>+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT                                                                0x0
>+#define SINK_DESCRIPTION15__DESCRIPTION_MASK                                                                  0x000000FFL
>+//SINK_DESCRIPTION16
>+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT                                                                0x0
>+#define SINK_DESCRIPTION16__DESCRIPTION_MASK                                                                  0x000000FFL
>+//SINK_DESCRIPTION17
>+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT                                                                0x0
>+#define SINK_DESCRIPTION17__DESCRIPTION_MASK                                                                  0x000000FFL
>+
>+
>+// addressBlock: azf0controller_azinputcrc0resultind
>+//AZALIA_INPUT_CRC0_CHANNEL0
>+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC0_CHANNEL1
>+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC0_CHANNEL2
>+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC0_CHANNEL3
>+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC0_CHANNEL4
>+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC0_CHANNEL5
>+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC0_CHANNEL6
>+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC0_CHANNEL7
>+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0controller_azinputcrc1resultind
>+//AZALIA_INPUT_CRC1_CHANNEL0
>+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC1_CHANNEL1
>+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC1_CHANNEL2
>+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC1_CHANNEL3
>+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC1_CHANNEL4
>+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC1_CHANNEL5
>+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC1_CHANNEL6
>+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
>+//AZALIA_INPUT_CRC1_CHANNEL7
>+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
>+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0controller_azcrc0resultind
>+//AZALIA_CRC0_CHANNEL0
>+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
>+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC0_CHANNEL1
>+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
>+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC0_CHANNEL2
>+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
>+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC0_CHANNEL3
>+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
>+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC0_CHANNEL4
>+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
>+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC0_CHANNEL5
>+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
>+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC0_CHANNEL6
>+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
>+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC0_CHANNEL7
>+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
>+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0controller_azcrc1resultind
>+//AZALIA_CRC1_CHANNEL0
>+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
>+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC1_CHANNEL1
>+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
>+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC1_CHANNEL2
>+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
>+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC1_CHANNEL3
>+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
>+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC1_CHANNEL4
>+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
>+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC1_CHANNEL5
>+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
>+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC1_CHANNEL6
>+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
>+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
>+//AZALIA_CRC1_CHANNEL7
>+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
>+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
>+
>+
>+// addressBlock: azinputendpoint_f2codecind
>+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                      0x4
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                  0x8
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                 0xb
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                     0xe
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                          0xf
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                     0x0000000FL
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                        0x00000070L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                    0x00000700L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                   0x00003800L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                       0x00004000L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                            0x00008000L
>+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                          0x0
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                           0x4
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                            0x0000000FL
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                             0x000000F0L
>+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                               0x0
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                   0x1
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                0x2
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                 0x3
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                0x4
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                           0x5
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                 0x6
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                   0x7
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                  0x8
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                           0x17
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                 0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                     0x00000002L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                  0x00000004L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                   0x00000008L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                  0x00000010L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                             0x00000020L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                   0x00000040L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                     0x00000080L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                    0x00007F00L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                             0x00800000L
>+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT   0x1
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT           0x4
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                    0x5
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT         0x6
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT           0x8
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                   0x9
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT             0xa
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                   0xb
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                      0x14
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK     0x00000002L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK    0x00000004L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK             0x00000010L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                      0x00000020L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK           0x00000040L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK             0x00000100L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                     0x00000200L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK               0x00000400L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                     0x00000800L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                        0x00F00000L
>+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT        0x0
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT         0x10
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK          0x00000FFFL
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK           0x001F0000L
>+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                       0x0
>+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                         0xFFFFFFFFL
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                                    0x5
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                                      0x00000020L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                    0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                 0x7
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                      0x0000003FL
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                   0x00000080L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                          0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                          0x1f
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                            0x7FFFFFFFL
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                            0x80000000L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                     0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT          0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                         0x8
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                        0xc
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT              0x10
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT               0x14
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                     0x18
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT            0x1e
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                       0x0000000FL
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK            0x000000F0L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                           0x00000F00L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                          0x0000F000L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                0x000F0000L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                 0x00F00000L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                       0x3F000000L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK              0xC0000000L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                       0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                      0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                         0x0000000FL
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                        0x000000F0L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT            0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT             0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK              0x0000000FL
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK               0x000000F0L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT          0x6
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                     0x0000003FL
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK            0x000000C0L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                       0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                         0x000000FFL
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT                     0x1
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT               0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK                     0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK                       0x00000002L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK                 0x000000F0L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT                     0x1
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT               0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK                     0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK                       0x00000002L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK                 0x000000F0L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT                     0x1
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT               0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK                     0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK                       0x00000002L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK                 0x000000F0L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT                     0x1
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT               0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK                     0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK                       0x00000002L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK                 0x000000F0L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                             0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                              0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                               0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                0x00000010L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                     0x1
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT               0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                     0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                       0x00000002L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                 0x000000F0L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                     0x1
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT               0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                     0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                       0x00000002L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                 0x000000F0L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                     0x1
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT               0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                     0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                       0x00000002L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                 0x000000F0L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                     0x1
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT               0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                     0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                       0x00000002L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                 0x000000F0L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                    0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT              0x8
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                      0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                0x0000FF00L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                                   0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                                     0xFFFFFFFFL
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                     0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                       0xFFFFFFFFL
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT                         0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT                         0x1
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT               0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK                           0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK                           0x00000006L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK                 0x00000010L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK   0x00000020L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                                     0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT                                0x8
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT                                  0x10
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                                   0x1f
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                                       0x00000007L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK                                  0x0000FF00L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                                    0x00FF0000L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                                     0x80000000L
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT                           0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK                             0xFFFFFFFFL
>+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT                           0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK                             0xFFFFFFFFL
>+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
>+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                      0x0
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                             0x1
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                    0x2
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                      0x3
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                               0x4
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                0x5
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                            0x6
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                         0x7
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                 0x8
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                 0x10
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                           0x18
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                        0x00000001L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                               0x00000002L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                      0x00000004L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                        0x00000008L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                 0x00000010L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                  0x00000020L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                              0x00000040L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                           0x00000080L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                   0x0000FF00L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                   0x00010000L
>+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                                             0x01000000L
>+
>+
>+// addressBlock: azroot_f2codecind
>+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
>+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
>+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
>+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK                     0x000000FFL
>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK                     0x000000FFL
>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT                   0x0
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK                     0x000000FFL
>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
>+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
>+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
>+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
>+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
>+
>+
>+// addressBlock: azf0stream0_streamind
>+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
>+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
>+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
>+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
>+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
>+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
>+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
>+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
>+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
>+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream1_streamind
>+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
>+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
>+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
>+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
>+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
>+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
>+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
>+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
>+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
>+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream2_streamind
>+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
>+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
>+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
>+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
>+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
>+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
>+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
>+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
>+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
>+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream3_streamind
>+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
>+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
>+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
>+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
>+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
>+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
>+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
>+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
>+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
>+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream4_streamind
>+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
>+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
>+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
>+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
>+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
>+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
>+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
>+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
>+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
>+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream5_streamind
>+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
>+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
>+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
>+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
>+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
>+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
>+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
>+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
>+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
>+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream6_streamind
>+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
>+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
>+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
>+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
>+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
>+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
>+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
>+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
>+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
>+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream7_streamind
>+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
>+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
>+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
>+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
>+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
>+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
>+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
>+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
>+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
>+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream8_streamind
>+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
>+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
>+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
>+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
>+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
>+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
>+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
>+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
>+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
>+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream9_streamind
>+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
>+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
>+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
>+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
>+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
>+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
>+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
>+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
>+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
>+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream10_streamind
>+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
>+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
>+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
>+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
>+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
>+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
>+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
>+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
>+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
>+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream11_streamind
>+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
>+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
>+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
>+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
>+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
>+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
>+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
>+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
>+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
>+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream12_streamind
>+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
>+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
>+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
>+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
>+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
>+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
>+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
>+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
>+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
>+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream13_streamind
>+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
>+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
>+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
>+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
>+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
>+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
>+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
>+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
>+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
>+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream14_streamind
>+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
>+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
>+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
>+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
>+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
>+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
>+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
>+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
>+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
>+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0stream15_streamind
>+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
>+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
>+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
>+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
>+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
>+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
>+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
>+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
>+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
>+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
>+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
>+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
>+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
>+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
>+
>+
>+// addressBlock: azf0endpoint0_endpointind
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
>+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
>+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
>+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
>+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
>+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
>+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
>+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
>+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
>+
>+
>+// addressBlock: azf0endpoint1_endpointind
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
>+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
>+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
>+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
>+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
>+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
>+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
>+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
>+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
>+
>+
>+// addressBlock: azf0endpoint2_endpointind
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
>+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
>+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
>+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
>+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
>+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
>+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
>+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
>+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
>+
>+
>+// addressBlock: azf0endpoint3_endpointind
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
>+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
>+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
>+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
>+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
>+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
>+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
>+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
>+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
>+
>+
>+// addressBlock: azf0endpoint4_endpointind
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
>+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
>+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
>+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
>+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
>+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
>+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
>+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
>+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
>+
>+
>+// addressBlock: azf0endpoint5_endpointind
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
>+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
>+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
>+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
>+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
>+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
>+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
>+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
>+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
>+
>+
>+// addressBlock: azf0endpoint6_endpointind
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
>+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
>+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
>+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
>+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
>+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
>+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
>+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
>+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
>+
>+
>+// addressBlock: azf0endpoint7_endpointind
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
>+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
>+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
>+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
>+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
>+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
>+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
>+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
>+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
>+
>+
>+// addressBlock: azf0inputendpoint0_inputendpointind
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
>+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
>+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
>+
>+
>+// addressBlock: azf0inputendpoint1_inputendpointind
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
>+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
>+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
>+
>+
>+// addressBlock: azf0inputendpoint2_inputendpointind
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
>+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
>+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
>+
>+
>+// addressBlock: azf0inputendpoint3_inputendpointind
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
>+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
>+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
>+
>+
>+// addressBlock: azf0inputendpoint4_inputendpointind
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
>+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
>+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
>+
>+
>+// addressBlock: azf0inputendpoint5_inputendpointind
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
>+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
>+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
>+
>+
>+// addressBlock: azf0inputendpoint6_inputendpointind
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
>+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
>+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
>+
>+
>+// addressBlock: azf0inputendpoint7_inputendpointind
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
>+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
>+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
>+
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h	2019-08-31 15:01:11.886736171 -0500
>@@ -0,0 +1,565 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _dpcs_2_1_0_OFFSET_HEADER
>+#define _dpcs_2_1_0_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
>+// base address: 0x0
>+#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL                                                                 0x2928
>+#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
>+#define mmDPCSTX0_DPCSTX_TX_CNTL                                                                       0x2929
>+#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX                                                              2
>+#define mmDPCSTX0_DPCSTX_CBUS_CNTL                                                                     0x292a
>+#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
>+#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL                                                                0x292b
>+#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
>+#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR                                                               0x292c
>+#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
>+#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA                                                               0x292d
>+#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
>+#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG                                                                  0x292e
>+#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
>+
>+
>+// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
>+// base address: 0x0
>+#define mmRDPCSTX0_RDPCSTX_CNTL                                                                        0x2930
>+#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX                                                               2
>+#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL                                                                  0x2931
>+#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
>+#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL                                                           0x2932
>+#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
>+#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA                                                             0x2933
>+#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
>+#define mmRDPCSTX0_RDPCS_TX_CR_ADDR                                                                    0x2934
>+#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
>+#define mmRDPCSTX0_RDPCS_TX_CR_DATA                                                                    0x2935
>+#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
>+#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL                                                                  0x2936
>+#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
>+#define mmRDPCSTX0_RDPCSTX_SCRATCH                                                                     0x2937
>+#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX                                                            2
>+#define mmRDPCSTX0_RDPCSTX_SPARE                                                                       0x2938
>+#define mmRDPCSTX0_RDPCSTX_SPARE_BASE_IDX                                                              2
>+#define mmRDPCSTX0_RDPCSTX_CNTL2                                                                       0x2939
>+#define mmRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2
>+#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x293c
>+#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
>+#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG                                                                0x293d
>+#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2                                                                   0x2942
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3                                                                   0x2943
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4                                                                   0x2944
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5                                                                   0x2945
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6                                                                   0x2946
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7                                                                   0x2947
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8                                                                   0x2948
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9                                                                   0x2949
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10                                                                  0x294a
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11                                                                  0x294b
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12                                                                  0x294c
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13                                                                  0x294d
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14                                                                  0x294e
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
>+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0                                                                   0x294f
>+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1                                                                   0x2950
>+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2                                                                   0x2951
>+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3                                                                   0x2952
>+#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
>+#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL                                                               0x2953
>+#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
>+#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2954
>+#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
>+#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2955
>+#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
>+#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG                                                           0x2956
>+#define mmRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL15                                                                  0x2958
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL16                                                                  0x2959
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL17                                                                  0x295a
>+#define mmRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
>+#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2                                                               0x295b
>+#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dpcssys_dpcssys_cr0_dispdec
>+// base address: 0x0
>+#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR                                                                  0x2934
>+#define mmDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
>+#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA                                                                  0x2935
>+#define mmDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX                                                         2
>+
>+
>+// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
>+// base address: 0x360
>+#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL                                                                 0x2a00
>+#define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
>+#define mmDPCSTX1_DPCSTX_TX_CNTL                                                                       0x2a01
>+#define mmDPCSTX1_DPCSTX_TX_CNTL_BASE_IDX                                                              2
>+#define mmDPCSTX1_DPCSTX_CBUS_CNTL                                                                     0x2a02
>+#define mmDPCSTX1_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
>+#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL                                                                0x2a03
>+#define mmDPCSTX1_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
>+#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR                                                               0x2a04
>+#define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
>+#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA                                                               0x2a05
>+#define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
>+#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG                                                                  0x2a06
>+#define mmDPCSTX1_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
>+
>+
>+// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
>+// base address: 0x360
>+#define mmRDPCSTX1_RDPCSTX_CNTL                                                                        0x2a08
>+#define mmRDPCSTX1_RDPCSTX_CNTL_BASE_IDX                                                               2
>+#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL                                                                  0x2a09
>+#define mmRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
>+#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL                                                           0x2a0a
>+#define mmRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
>+#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA                                                             0x2a0b
>+#define mmRDPCSTX1_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
>+#define mmRDPCSTX1_RDPCS_TX_CR_ADDR                                                                    0x2a0c
>+#define mmRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
>+#define mmRDPCSTX1_RDPCS_TX_CR_DATA                                                                    0x2a0d
>+#define mmRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
>+#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL                                                                  0x2a0e
>+#define mmRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
>+#define mmRDPCSTX1_RDPCSTX_SCRATCH                                                                     0x2a0f
>+#define mmRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX                                                            2
>+#define mmRDPCSTX1_RDPCSTX_SPARE                                                                       0x2a10
>+#define mmRDPCSTX1_RDPCSTX_SPARE_BASE_IDX                                                              2
>+#define mmRDPCSTX1_RDPCSTX_CNTL2                                                                       0x2a11
>+#define mmRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2
>+#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2a14
>+#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
>+#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG                                                                0x2a15
>+#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2                                                                   0x2a1a
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3                                                                   0x2a1b
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4                                                                   0x2a1c
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5                                                                   0x2a1d
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6                                                                   0x2a1e
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7                                                                   0x2a1f
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8                                                                   0x2a20
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9                                                                   0x2a21
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10                                                                  0x2a22
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11                                                                  0x2a23
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12                                                                  0x2a24
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13                                                                  0x2a25
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14                                                                  0x2a26
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
>+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0                                                                   0x2a27
>+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1                                                                   0x2a28
>+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2                                                                   0x2a29
>+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3                                                                   0x2a2a
>+#define mmRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
>+#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL                                                               0x2a2b
>+#define mmRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
>+#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2a2c
>+#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
>+#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2a2d
>+#define mmRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
>+#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG                                                           0x2a2e
>+#define mmRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL15                                                                  0x2a30
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL16                                                                  0x2a31
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL17                                                                  0x2a32
>+#define mmRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
>+#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2                                                               0x2a33
>+#define mmRDPCSTX1_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dpcssys_dpcssys_cr1_dispdec
>+// base address: 0x360
>+#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR                                                                  0x2a0c
>+#define mmDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
>+#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA                                                                  0x2a0d
>+#define mmDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX                                                         2
>+
>+
>+// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec
>+// base address: 0x6c0
>+#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL                                                                 0x2ad8
>+#define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
>+#define mmDPCSTX2_DPCSTX_TX_CNTL                                                                       0x2ad9
>+#define mmDPCSTX2_DPCSTX_TX_CNTL_BASE_IDX                                                              2
>+#define mmDPCSTX2_DPCSTX_CBUS_CNTL                                                                     0x2ada
>+#define mmDPCSTX2_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
>+#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL                                                                0x2adb
>+#define mmDPCSTX2_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
>+#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR                                                               0x2adc
>+#define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
>+#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA                                                               0x2add
>+#define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
>+#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG                                                                  0x2ade
>+#define mmDPCSTX2_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
>+
>+
>+// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
>+// base address: 0x6c0
>+#define mmRDPCSTX2_RDPCSTX_CNTL                                                                        0x2ae0
>+#define mmRDPCSTX2_RDPCSTX_CNTL_BASE_IDX                                                               2
>+#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL                                                                  0x2ae1
>+#define mmRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
>+#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL                                                           0x2ae2
>+#define mmRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
>+#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA                                                             0x2ae3
>+#define mmRDPCSTX2_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
>+#define mmRDPCSTX2_RDPCS_TX_CR_ADDR                                                                    0x2ae4
>+#define mmRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
>+#define mmRDPCSTX2_RDPCS_TX_CR_DATA                                                                    0x2ae5
>+#define mmRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
>+#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL                                                                  0x2ae6
>+#define mmRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
>+#define mmRDPCSTX2_RDPCSTX_SCRATCH                                                                     0x2ae7
>+#define mmRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX                                                            2
>+#define mmRDPCSTX2_RDPCSTX_SPARE                                                                       0x2ae8
>+#define mmRDPCSTX2_RDPCSTX_SPARE_BASE_IDX                                                              2
>+#define mmRDPCSTX2_RDPCSTX_CNTL2                                                                       0x2ae9
>+#define mmRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX                                                              2
>+#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2aec
>+#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
>+#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG                                                                0x2aed
>+#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0                                                                   0x2af0
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1                                                                   0x2af1
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2                                                                   0x2af2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3                                                                   0x2af3
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4                                                                   0x2af4
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5                                                                   0x2af5
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6                                                                   0x2af6
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7                                                                   0x2af7
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8                                                                   0x2af8
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9                                                                   0x2af9
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10                                                                  0x2afa
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11                                                                  0x2afb
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12                                                                  0x2afc
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13                                                                  0x2afd
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14                                                                  0x2afe
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
>+#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0                                                                   0x2aff
>+#define mmRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1                                                                   0x2b00
>+#define mmRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2                                                                   0x2b01
>+#define mmRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3                                                                   0x2b02
>+#define mmRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
>+#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL                                                               0x2b03
>+#define mmRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
>+#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2b04
>+#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
>+#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2b05
>+#define mmRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
>+#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG                                                           0x2b06
>+#define mmRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL15                                                                  0x2b08
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL16                                                                  0x2b09
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL17                                                                  0x2b0a
>+#define mmRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
>+#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2                                                               0x2b0b
>+#define mmRDPCSTX2_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dpcssys_dpcssys_cr2_dispdec
>+// base address: 0x6c0
>+#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR                                                                  0x2ae4
>+#define mmDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
>+#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA                                                                  0x2ae5
>+#define mmDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX                                                         2
>+
>+
>+// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec
>+// base address: 0xa20
>+#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL                                                                 0x2bb0
>+#define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
>+#define mmDPCSTX3_DPCSTX_TX_CNTL                                                                       0x2bb1
>+#define mmDPCSTX3_DPCSTX_TX_CNTL_BASE_IDX                                                              2
>+#define mmDPCSTX3_DPCSTX_CBUS_CNTL                                                                     0x2bb2
>+#define mmDPCSTX3_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
>+#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL                                                                0x2bb3
>+#define mmDPCSTX3_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
>+#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR                                                               0x2bb4
>+#define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
>+#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA                                                               0x2bb5
>+#define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
>+#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG                                                                  0x2bb6
>+#define mmDPCSTX3_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
>+
>+
>+// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
>+// base address: 0xa20
>+#define mmRDPCSTX3_RDPCSTX_CNTL                                                                        0x2bb8
>+#define mmRDPCSTX3_RDPCSTX_CNTL_BASE_IDX                                                               2
>+#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL                                                                  0x2bb9
>+#define mmRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
>+#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL                                                           0x2bba
>+#define mmRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
>+#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA                                                             0x2bbb
>+#define mmRDPCSTX3_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
>+#define mmRDPCSTX3_RDPCS_TX_CR_ADDR                                                                    0x2bbc
>+#define mmRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
>+#define mmRDPCSTX3_RDPCS_TX_CR_DATA                                                                    0x2bbd
>+#define mmRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
>+#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL                                                                  0x2bbe
>+#define mmRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
>+#define mmRDPCSTX3_RDPCSTX_SCRATCH                                                                     0x2bbf
>+#define mmRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX                                                            2
>+#define mmRDPCSTX3_RDPCSTX_SPARE                                                                       0x2bc0
>+#define mmRDPCSTX3_RDPCSTX_SPARE_BASE_IDX                                                              2
>+#define mmRDPCSTX3_RDPCSTX_CNTL2                                                                       0x2bc1
>+#define mmRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX                                                              2
>+#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2bc4
>+#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
>+#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG                                                                0x2bc5
>+#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0                                                                   0x2bc8
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1                                                                   0x2bc9
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2                                                                   0x2bca
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3                                                                   0x2bcb
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4                                                                   0x2bcc
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5                                                                   0x2bcd
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6                                                                   0x2bce
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7                                                                   0x2bcf
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8                                                                   0x2bd0
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9                                                                   0x2bd1
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10                                                                  0x2bd2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11                                                                  0x2bd3
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12                                                                  0x2bd4
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13                                                                  0x2bd5
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14                                                                  0x2bd6
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
>+#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0                                                                   0x2bd7
>+#define mmRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1                                                                   0x2bd8
>+#define mmRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2                                                                   0x2bd9
>+#define mmRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3                                                                   0x2bda
>+#define mmRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
>+#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL                                                               0x2bdb
>+#define mmRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
>+#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2bdc
>+#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
>+#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2bdd
>+#define mmRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
>+#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG                                                           0x2bde
>+#define mmRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL15                                                                  0x2be0
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL16                                                                  0x2be1
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL17                                                                  0x2be2
>+#define mmRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
>+#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2                                                               0x2be3
>+#define mmRDPCSTX3_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dpcssys_dpcssys_cr3_dispdec
>+// base address: 0xa20
>+#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR                                                                  0x2bbc
>+#define mmDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
>+#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA                                                                  0x2bbd
>+#define mmDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX                                                         2
>+
>+
>+// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec
>+// base address: 0xd80
>+#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL                                                                 0x2c88
>+#define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL_BASE_IDX                                                        2
>+#define mmDPCSTX4_DPCSTX_TX_CNTL                                                                       0x2c89
>+#define mmDPCSTX4_DPCSTX_TX_CNTL_BASE_IDX                                                              2
>+#define mmDPCSTX4_DPCSTX_CBUS_CNTL                                                                     0x2c8a
>+#define mmDPCSTX4_DPCSTX_CBUS_CNTL_BASE_IDX                                                            2
>+#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL                                                                0x2c8b
>+#define mmDPCSTX4_DPCSTX_INTERRUPT_CNTL_BASE_IDX                                                       2
>+#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR                                                               0x2c8c
>+#define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX                                                      2
>+#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA                                                               0x2c8d
>+#define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                      2
>+#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG                                                                  0x2c8e
>+#define mmDPCSTX4_DPCSTX_DEBUG_CONFIG_BASE_IDX                                                         2
>+
>+
>+// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
>+// base address: 0xd80
>+#define mmRDPCSTX4_RDPCSTX_CNTL                                                                        0x2c90
>+#define mmRDPCSTX4_RDPCSTX_CNTL_BASE_IDX                                                               2
>+#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL                                                                  0x2c91
>+#define mmRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
>+#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL                                                           0x2c92
>+#define mmRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
>+#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA                                                             0x2c93
>+#define mmRDPCSTX4_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX                                                    2
>+#define mmRDPCSTX4_RDPCS_TX_CR_ADDR                                                                    0x2c94
>+#define mmRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
>+#define mmRDPCSTX4_RDPCS_TX_CR_DATA                                                                    0x2c95
>+#define mmRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
>+#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL                                                                  0x2c96
>+#define mmRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
>+#define mmRDPCSTX4_RDPCSTX_SCRATCH                                                                     0x2c97
>+#define mmRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX                                                            2
>+#define mmRDPCSTX4_RDPCSTX_SPARE                                                                       0x2c98
>+#define mmRDPCSTX4_RDPCSTX_SPARE_BASE_IDX                                                              2
>+#define mmRDPCSTX4_RDPCSTX_CNTL2                                                                       0x2c99
>+#define mmRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX                                                              2
>+#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2c9c
>+#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
>+#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG                                                                0x2c9d
>+#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG_BASE_IDX                                                       2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0                                                                   0x2ca0
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1                                                                   0x2ca1
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2                                                                   0x2ca2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3                                                                   0x2ca3
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4                                                                   0x2ca4
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5                                                                   0x2ca5
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6                                                                   0x2ca6
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7                                                                   0x2ca7
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8                                                                   0x2ca8
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9                                                                   0x2ca9
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10                                                                  0x2caa
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11                                                                  0x2cab
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12                                                                  0x2cac
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13                                                                  0x2cad
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14                                                                  0x2cae
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
>+#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0                                                                   0x2caf
>+#define mmRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1                                                                   0x2cb0
>+#define mmRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2                                                                   0x2cb1
>+#define mmRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3                                                                   0x2cb2
>+#define mmRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
>+#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL                                                               0x2cb3
>+#define mmRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
>+#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2cb4
>+#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
>+#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2cb5
>+#define mmRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
>+#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG                                                           0x2cb6
>+#define mmRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL15                                                                  0x2cb8
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL16                                                                  0x2cb9
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL17                                                                  0x2cba
>+#define mmRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
>+#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2                                                               0x2cbb
>+#define mmRDPCSTX4_RDPCSTX_DEBUG_CONFIG2_BASE_IDX                                                      2
>+
>+
>+// addressBlock: dpcssys_dpcssys_cr4_dispdec
>+// base address: 0xd80
>+#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR                                                                  0x2c94
>+#define mmDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
>+#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA                                                                  0x2c95
>+#define mmDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX                                                         2
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h	2019-08-31 15:01:11.887736171 -0500
>@@ -0,0 +1,3430 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _dpcs_2_1_0_SH_MASK_HEADER
>+#define _dpcs_2_1_0_SH_MASK_HEADER
>+
>+
>+// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
>+//DPCSTX0_DPCSTX_TX_CLOCK_CNTL
>+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT                                             0x0
>+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT                                                   0x1
>+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT                                             0x2
>+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0x3
>+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK                                               0x00000001L
>+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK                                                     0x00000002L
>+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK                                               0x00000004L
>+#define DPCSTX0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000008L
>+//DPCSTX0_DPCSTX_TX_CNTL
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0xc
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xd
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT                                                      0xe
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT                                              0xf
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT                                                        0x10
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT                                                     0x11
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00001000L
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00002000L
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK                                                        0x00004000L
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK                                                0x00008000L
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK                                                          0x00010000L
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK                                                       0x00020000L
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x00F00000L
>+#define DPCSTX0_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
>+//DPCSTX0_DPCSTX_CBUS_CNTL
>+#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT                                               0x0
>+#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT                                                 0x1f
>+#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK                                                 0x000000FFL
>+#define DPCSTX0_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK                                                   0x80000000L
>+//DPCSTX0_DPCSTX_INTERRUPT_CNTL
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT                                          0x0
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT                                              0x1
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT                                        0x4
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT                                             0x8
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT                                             0x9
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT                                             0xa
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT                                             0xb
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT                                               0xc
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT                                         0x10
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT                                             0x14
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK                                            0x00000001L
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK                                                0x00000002L
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK                                          0x00000010L
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK                                               0x00000100L
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK                                               0x00000200L
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK                                               0x00000400L
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK                                               0x00000800L
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK                                                 0x00001000L
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK                                           0x00010000L
>+#define DPCSTX0_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK                                               0x00100000L
>+//DPCSTX0_DPCSTX_PLL_UPDATE_ADDR
>+#define DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT                                           0x0
>+#define DPCSTX0_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK                                             0x0003FFFFL
>+//DPCSTX0_DPCSTX_PLL_UPDATE_DATA
>+#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0
>+#define DPCSTX0_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL
>+//DPCSTX0_DPCSTX_DEBUG_CONFIG
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT                                                       0x0
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT                                               0x1
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT                                            0x4
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT                                       0x8
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT                                                 0xe
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT                                          0x10
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT                                             0x18
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK                                                         0x00000001L
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK                                                 0x0000000EL
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK                                              0x00000070L
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK                                         0x00000700L
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK                                                   0x00004000L
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK                                            0x00010000L
>+#define DPCSTX0_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK                                               0xFF000000L
>+
>+
>+
>+// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
>+//RDPCSTX0_RDPCSTX_CNTL
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x4
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x10
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x11
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1a
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000010L
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x00010000L
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x00020000L
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x04000000L
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
>+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
>+//RDPCSTX0_RDPCSTX_CLOCK_CNTL
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT                                          0x4
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT                                          0x5
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT                                          0x6
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT                                          0x7
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT                                        0x8
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT                                              0x9
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0xa
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK                                            0x00000010L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK                                            0x00000020L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK                                            0x00000040L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK                                            0x00000080L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK                                          0x00000100L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK                                                0x00000200L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000400L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
>+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
>+//RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
>+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
>+//RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA
>+#define RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                        0x0
>+#define RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                          0x00000001L
>+//RDPCSTX0_RDPCS_TX_CR_ADDR
>+#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
>+#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
>+//RDPCSTX0_RDPCS_TX_CR_DATA
>+#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
>+#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
>+//RDPCSTX0_RDPCS_TX_SRAM_CNTL
>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
>+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
>+//RDPCSTX0_RDPCSTX_SCRATCH
>+#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
>+#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
>+//RDPCSTX0_RDPCSTX_SPARE
>+#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
>+#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
>+//RDPCSTX0_RDPCSTX_CNTL2
>+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
>+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
>+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
>+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
>+//RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT              0x4
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK                0x00000010L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
>+//RDPCSTX0_RDPCSTX_DEBUG_CONFIG
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL1
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL2
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL3
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL4
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL5
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL6
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL7
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL8
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
>+//RDPCSTX0_RDPCSTX_PHY_CNTL9
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL10
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
>+//RDPCSTX0_RDPCSTX_PHY_CNTL11
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL12
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL13
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL14
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
>+//RDPCSTX0_RDPCSTX_PHY_FUSE0
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
>+//RDPCSTX0_RDPCSTX_PHY_FUSE1
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
>+//RDPCSTX0_RDPCSTX_PHY_FUSE2
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
>+//RDPCSTX0_RDPCSTX_PHY_FUSE3
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
>+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
>+//RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL
>+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
>+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
>+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
>+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
>+//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
>+//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
>+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
>+//RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG
>+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
>+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
>+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
>+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
>+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
>+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL15
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL16
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
>+//RDPCSTX0_RDPCSTX_PHY_CNTL17
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
>+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
>+//RDPCSTX0_RDPCSTX_DEBUG_CONFIG2
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
>+#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
>+
>+
>+// addressBlock: dpcssys_dpcssys_cr0_dispdec
>+//DPCSSYS_CR0_DPCSSYS_CR_ADDR
>+#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
>+#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
>+//DPCSSYS_CR0_DPCSSYS_CR_DATA
>+#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
>+#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
>+
>+
>+// addressBlock: dpcssys_dpcs0_dpcstx1_dispdec
>+//DPCSTX1_DPCSTX_TX_CLOCK_CNTL
>+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT                                             0x0
>+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT                                                   0x1
>+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT                                             0x2
>+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0x3
>+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK                                               0x00000001L
>+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK                                                     0x00000002L
>+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK                                               0x00000004L
>+#define DPCSTX1_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000008L
>+//DPCSTX1_DPCSTX_TX_CNTL
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0xc
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xd
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT                                                      0xe
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT                                              0xf
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT                                                        0x10
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT                                                     0x11
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00001000L
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00002000L
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK                                                        0x00004000L
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK                                                0x00008000L
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK                                                          0x00010000L
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK                                                       0x00020000L
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x00F00000L
>+#define DPCSTX1_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
>+//DPCSTX1_DPCSTX_CBUS_CNTL
>+#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT                                               0x0
>+#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT                                                 0x1f
>+#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK                                                 0x000000FFL
>+#define DPCSTX1_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK                                                   0x80000000L
>+//DPCSTX1_DPCSTX_INTERRUPT_CNTL
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT                                          0x0
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT                                              0x1
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT                                        0x4
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT                                             0x8
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT                                             0x9
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT                                             0xa
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT                                             0xb
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT                                               0xc
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT                                         0x10
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT                                             0x14
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK                                            0x00000001L
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK                                                0x00000002L
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK                                          0x00000010L
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK                                               0x00000100L
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK                                               0x00000200L
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK                                               0x00000400L
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK                                               0x00000800L
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK                                                 0x00001000L
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK                                           0x00010000L
>+#define DPCSTX1_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK                                               0x00100000L
>+//DPCSTX1_DPCSTX_PLL_UPDATE_ADDR
>+#define DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT                                           0x0
>+#define DPCSTX1_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK                                             0x0003FFFFL
>+//DPCSTX1_DPCSTX_PLL_UPDATE_DATA
>+#define DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0
>+#define DPCSTX1_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL
>+//DPCSTX1_DPCSTX_DEBUG_CONFIG
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT                                                       0x0
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT                                               0x1
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT                                            0x4
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT                                       0x8
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT                                                 0xe
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT                                          0x10
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT                                             0x18
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK                                                         0x00000001L
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK                                                 0x0000000EL
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK                                              0x00000070L
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK                                         0x00000700L
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK                                                   0x00004000L
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK                                            0x00010000L
>+#define DPCSTX1_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK                                               0xFF000000L
>+
>+
>+// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
>+//RDPCSTX1_RDPCSTX_CNTL
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x4
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x10
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x11
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1a
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000010L
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x00010000L
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x00020000L
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x04000000L
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
>+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
>+//RDPCSTX1_RDPCSTX_CLOCK_CNTL
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT                                          0x4
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT                                          0x5
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT                                          0x6
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT                                          0x7
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT                                        0x8
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT                                              0x9
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0xa
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK                                            0x00000010L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK                                            0x00000020L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK                                            0x00000040L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK                                            0x00000080L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK                                          0x00000100L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK                                                0x00000200L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000400L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
>+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
>+//RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
>+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
>+//RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA
>+#define RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                        0x0
>+#define RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                          0x00000001L
>+//RDPCSTX1_RDPCS_TX_CR_ADDR
>+#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
>+#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
>+//RDPCSTX1_RDPCS_TX_CR_DATA
>+#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
>+#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
>+//RDPCSTX1_RDPCS_TX_SRAM_CNTL
>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
>+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
>+//RDPCSTX1_RDPCSTX_SCRATCH
>+#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
>+#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
>+//RDPCSTX1_RDPCSTX_SPARE
>+#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
>+#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
>+//RDPCSTX1_RDPCSTX_CNTL2
>+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
>+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
>+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
>+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
>+//RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT              0x4
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK                0x00000010L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
>+//RDPCSTX1_RDPCSTX_DEBUG_CONFIG
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL1
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL2
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL3
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL4
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL5
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL6
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL7
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL8
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
>+//RDPCSTX1_RDPCSTX_PHY_CNTL9
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL10
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
>+//RDPCSTX1_RDPCSTX_PHY_CNTL11
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL12
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL13
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL14
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
>+//RDPCSTX1_RDPCSTX_PHY_FUSE0
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
>+//RDPCSTX1_RDPCSTX_PHY_FUSE1
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
>+//RDPCSTX1_RDPCSTX_PHY_FUSE2
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
>+//RDPCSTX1_RDPCSTX_PHY_FUSE3
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
>+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
>+//RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL
>+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
>+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
>+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
>+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
>+//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
>+//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
>+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
>+//RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG
>+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
>+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
>+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
>+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
>+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
>+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL15
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL16
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
>+//RDPCSTX1_RDPCSTX_PHY_CNTL17
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
>+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
>+//RDPCSTX1_RDPCSTX_DEBUG_CONFIG2
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
>+#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
>+
>+
>+// addressBlock: dpcssys_dpcssys_cr1_dispdec
>+//DPCSSYS_CR1_DPCSSYS_CR_ADDR
>+#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
>+#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
>+//DPCSSYS_CR1_DPCSSYS_CR_DATA
>+#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
>+#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
>+
>+
>+// addressBlock: dpcssys_dpcs0_dpcstx2_dispdec
>+//DPCSTX2_DPCSTX_TX_CLOCK_CNTL
>+#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT                                             0x0
>+#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT                                                   0x1
>+#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT                                             0x2
>+#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0x3
>+#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK                                               0x00000001L
>+#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK                                                     0x00000002L
>+#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK                                               0x00000004L
>+#define DPCSTX2_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000008L
>+//DPCSTX2_DPCSTX_TX_CNTL
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0xc
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xd
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT                                                      0xe
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT                                              0xf
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT                                                        0x10
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT                                                     0x11
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00001000L
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00002000L
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK                                                        0x00004000L
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK                                                0x00008000L
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK                                                          0x00010000L
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK                                                       0x00020000L
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x00F00000L
>+#define DPCSTX2_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
>+//DPCSTX2_DPCSTX_CBUS_CNTL
>+#define DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT                                               0x0
>+#define DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT                                                 0x1f
>+#define DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK                                                 0x000000FFL
>+#define DPCSTX2_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK                                                   0x80000000L
>+//DPCSTX2_DPCSTX_INTERRUPT_CNTL
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT                                          0x0
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT                                              0x1
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT                                        0x4
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT                                             0x8
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT                                             0x9
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT                                             0xa
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT                                             0xb
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT                                               0xc
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT                                         0x10
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT                                             0x14
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK                                            0x00000001L
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK                                                0x00000002L
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK                                          0x00000010L
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK                                               0x00000100L
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK                                               0x00000200L
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK                                               0x00000400L
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK                                               0x00000800L
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK                                                 0x00001000L
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK                                           0x00010000L
>+#define DPCSTX2_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK                                               0x00100000L
>+//DPCSTX2_DPCSTX_PLL_UPDATE_ADDR
>+#define DPCSTX2_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT                                           0x0
>+#define DPCSTX2_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK                                             0x0003FFFFL
>+//DPCSTX2_DPCSTX_PLL_UPDATE_DATA
>+#define DPCSTX2_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0
>+#define DPCSTX2_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL
>+//DPCSTX2_DPCSTX_DEBUG_CONFIG
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT                                                       0x0
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT                                               0x1
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT                                            0x4
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT                                       0x8
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT                                                 0xe
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT                                          0x10
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT                                             0x18
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK                                                         0x00000001L
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK                                                 0x0000000EL
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK                                              0x00000070L
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK                                         0x00000700L
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK                                                   0x00004000L
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK                                            0x00010000L
>+#define DPCSTX2_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK                                               0xFF000000L
>+
>+
>+// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
>+//RDPCSTX2_RDPCSTX_CNTL
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x4
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x10
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x11
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1a
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000010L
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x00010000L
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x00020000L
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x04000000L
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
>+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
>+//RDPCSTX2_RDPCSTX_CLOCK_CNTL
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT                                          0x4
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT                                          0x5
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT                                          0x6
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT                                          0x7
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT                                        0x8
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT                                              0x9
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0xa
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK                                            0x00000010L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK                                            0x00000020L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK                                            0x00000040L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK                                            0x00000080L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK                                          0x00000100L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK                                                0x00000200L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000400L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
>+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
>+//RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
>+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
>+//RDPCSTX2_RDPCSTX_PLL_UPDATE_DATA
>+#define RDPCSTX2_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                        0x0
>+#define RDPCSTX2_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                          0x00000001L
>+//RDPCSTX2_RDPCS_TX_CR_ADDR
>+#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
>+#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
>+//RDPCSTX2_RDPCS_TX_CR_DATA
>+#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
>+#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
>+//RDPCSTX2_RDPCS_TX_SRAM_CNTL
>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
>+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
>+//RDPCSTX2_RDPCSTX_SCRATCH
>+#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
>+#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
>+//RDPCSTX2_RDPCSTX_SPARE
>+#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
>+#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
>+//RDPCSTX2_RDPCSTX_CNTL2
>+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
>+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
>+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
>+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
>+//RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT              0x4
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK                0x00000010L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
>+//RDPCSTX2_RDPCSTX_DEBUG_CONFIG
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL1
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL2
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL3
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL4
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL5
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL6
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL7
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL8
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
>+//RDPCSTX2_RDPCSTX_PHY_CNTL9
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL10
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
>+//RDPCSTX2_RDPCSTX_PHY_CNTL11
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL12
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL13
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL14
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
>+//RDPCSTX2_RDPCSTX_PHY_FUSE0
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
>+//RDPCSTX2_RDPCSTX_PHY_FUSE1
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
>+//RDPCSTX2_RDPCSTX_PHY_FUSE2
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
>+//RDPCSTX2_RDPCSTX_PHY_FUSE3
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
>+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
>+//RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL
>+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
>+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
>+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
>+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
>+//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
>+//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
>+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
>+//RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG
>+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
>+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
>+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
>+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
>+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
>+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL15
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL16
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
>+//RDPCSTX2_RDPCSTX_PHY_CNTL17
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
>+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
>+//RDPCSTX2_RDPCSTX_DEBUG_CONFIG2
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
>+#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
>+
>+
>+// addressBlock: dpcssys_dpcssys_cr2_dispdec
>+//DPCSSYS_CR2_DPCSSYS_CR_ADDR
>+#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
>+#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
>+//DPCSSYS_CR2_DPCSSYS_CR_DATA
>+#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
>+#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
>+
>+
>+// addressBlock: dpcssys_dpcs0_dpcstx3_dispdec
>+//DPCSTX3_DPCSTX_TX_CLOCK_CNTL
>+#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT                                             0x0
>+#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT                                                   0x1
>+#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT                                             0x2
>+#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0x3
>+#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK                                               0x00000001L
>+#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK                                                     0x00000002L
>+#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK                                               0x00000004L
>+#define DPCSTX3_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000008L
>+//DPCSTX3_DPCSTX_TX_CNTL
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0xc
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xd
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT                                                      0xe
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT                                              0xf
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT                                                        0x10
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT                                                     0x11
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00001000L
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00002000L
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK                                                        0x00004000L
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK                                                0x00008000L
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK                                                          0x00010000L
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK                                                       0x00020000L
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x00F00000L
>+#define DPCSTX3_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
>+//DPCSTX3_DPCSTX_CBUS_CNTL
>+#define DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT                                               0x0
>+#define DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT                                                 0x1f
>+#define DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK                                                 0x000000FFL
>+#define DPCSTX3_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK                                                   0x80000000L
>+//DPCSTX3_DPCSTX_INTERRUPT_CNTL
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT                                          0x0
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT                                              0x1
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT                                        0x4
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT                                             0x8
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT                                             0x9
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT                                             0xa
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT                                             0xb
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT                                               0xc
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT                                         0x10
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT                                             0x14
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK                                            0x00000001L
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK                                                0x00000002L
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK                                          0x00000010L
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK                                               0x00000100L
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK                                               0x00000200L
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK                                               0x00000400L
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK                                               0x00000800L
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK                                                 0x00001000L
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK                                           0x00010000L
>+#define DPCSTX3_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK                                               0x00100000L
>+//DPCSTX3_DPCSTX_PLL_UPDATE_ADDR
>+#define DPCSTX3_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT                                           0x0
>+#define DPCSTX3_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK                                             0x0003FFFFL
>+//DPCSTX3_DPCSTX_PLL_UPDATE_DATA
>+#define DPCSTX3_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0
>+#define DPCSTX3_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL
>+//DPCSTX3_DPCSTX_DEBUG_CONFIG
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT                                                       0x0
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT                                               0x1
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT                                            0x4
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT                                       0x8
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT                                                 0xe
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT                                          0x10
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT                                             0x18
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK                                                         0x00000001L
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK                                                 0x0000000EL
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK                                              0x00000070L
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK                                         0x00000700L
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK                                                   0x00004000L
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK                                            0x00010000L
>+#define DPCSTX3_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK                                               0xFF000000L
>+
>+
>+// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
>+//RDPCSTX3_RDPCSTX_CNTL
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x4
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x10
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x11
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1a
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000010L
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x00010000L
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x00020000L
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x04000000L
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
>+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
>+//RDPCSTX3_RDPCSTX_CLOCK_CNTL
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT                                          0x4
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT                                          0x5
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT                                          0x6
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT                                          0x7
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT                                        0x8
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT                                              0x9
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0xa
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK                                            0x00000010L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK                                            0x00000020L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK                                            0x00000040L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK                                            0x00000080L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK                                          0x00000100L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK                                                0x00000200L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000400L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
>+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
>+//RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
>+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
>+//RDPCSTX3_RDPCSTX_PLL_UPDATE_DATA
>+#define RDPCSTX3_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                        0x0
>+#define RDPCSTX3_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                          0x00000001L
>+//RDPCSTX3_RDPCS_TX_CR_ADDR
>+#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
>+#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
>+//RDPCSTX3_RDPCS_TX_CR_DATA
>+#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
>+#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
>+//RDPCSTX3_RDPCS_TX_SRAM_CNTL
>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
>+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
>+//RDPCSTX3_RDPCSTX_SCRATCH
>+#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
>+#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
>+//RDPCSTX3_RDPCSTX_SPARE
>+#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
>+#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
>+//RDPCSTX3_RDPCSTX_CNTL2
>+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
>+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
>+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
>+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
>+//RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT              0x4
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK                0x00000010L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
>+//RDPCSTX3_RDPCSTX_DEBUG_CONFIG
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL1
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL2
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL3
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL4
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL5
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL6
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL7
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL8
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
>+//RDPCSTX3_RDPCSTX_PHY_CNTL9
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL10
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
>+//RDPCSTX3_RDPCSTX_PHY_CNTL11
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL12
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL13
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL14
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
>+//RDPCSTX3_RDPCSTX_PHY_FUSE0
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
>+//RDPCSTX3_RDPCSTX_PHY_FUSE1
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
>+//RDPCSTX3_RDPCSTX_PHY_FUSE2
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
>+//RDPCSTX3_RDPCSTX_PHY_FUSE3
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
>+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
>+//RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL
>+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
>+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
>+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
>+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
>+//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
>+//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
>+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
>+//RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG
>+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
>+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
>+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
>+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
>+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
>+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL15
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL16
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
>+//RDPCSTX3_RDPCSTX_PHY_CNTL17
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
>+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
>+//RDPCSTX3_RDPCSTX_DEBUG_CONFIG2
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
>+#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
>+
>+
>+// addressBlock: dpcssys_dpcssys_cr3_dispdec
>+//DPCSSYS_CR3_DPCSSYS_CR_ADDR
>+#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
>+#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
>+//DPCSSYS_CR3_DPCSSYS_CR_DATA
>+#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
>+#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
>+
>+
>+// addressBlock: dpcssys_dpcs0_dpcstx4_dispdec
>+//DPCSTX4_DPCSTX_TX_CLOCK_CNTL
>+#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT                                             0x0
>+#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT                                                   0x1
>+#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT                                             0x2
>+#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0x3
>+#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK                                               0x00000001L
>+#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK                                                     0x00000002L
>+#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK                                               0x00000004L
>+#define DPCSTX4_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000008L
>+//DPCSTX4_DPCSTX_TX_CNTL
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0xc
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xd
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP__SHIFT                                                      0xe
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT__SHIFT                                              0xf
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN__SHIFT                                                        0x10
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START__SHIFT                                                     0x11
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00001000L
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00002000L
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_SWAP_MASK                                                        0x00004000L
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_DATA_ORDER_INVERT_MASK                                                0x00008000L
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_EN_MASK                                                          0x00010000L
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_START_MASK                                                       0x00020000L
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x00F00000L
>+#define DPCSTX4_DPCSTX_TX_CNTL__DPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
>+//DPCSTX4_DPCSTX_CBUS_CNTL
>+#define DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY__SHIFT                                               0x0
>+#define DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET__SHIFT                                                 0x1f
>+#define DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_WR_CMD_DELAY_MASK                                                 0x000000FFL
>+#define DPCSTX4_DPCSTX_CBUS_CNTL__DPCS_CBUS_SOFT_RESET_MASK                                                   0x80000000L
>+//DPCSTX4_DPCSTX_INTERRUPT_CNTL
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW__SHIFT                                          0x0
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR__SHIFT                                              0x1
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK__SHIFT                                        0x4
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR__SHIFT                                             0x8
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR__SHIFT                                             0x9
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR__SHIFT                                             0xa
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR__SHIFT                                             0xb
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR__SHIFT                                               0xc
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK__SHIFT                                         0x10
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK__SHIFT                                             0x14
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_OVERFLOW_MASK                                            0x00000001L
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_ERROR_CLR_MASK                                                0x00000002L
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_REG_FIFO_ERROR_MASK_MASK                                          0x00000010L
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX0_FIFO_ERROR_MASK                                               0x00000100L
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX1_FIFO_ERROR_MASK                                               0x00000200L
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX2_FIFO_ERROR_MASK                                               0x00000400L
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX3_FIFO_ERROR_MASK                                               0x00000800L
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_ERROR_CLR_MASK                                                 0x00001000L
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_TX_FIFO_ERROR_MASK_MASK                                           0x00010000L
>+#define DPCSTX4_DPCSTX_INTERRUPT_CNTL__DPCS_INTERRUPT_MASK_MASK                                               0x00100000L
>+//DPCSTX4_DPCSTX_PLL_UPDATE_ADDR
>+#define DPCSTX4_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR__SHIFT                                           0x0
>+#define DPCSTX4_DPCSTX_PLL_UPDATE_ADDR__DPCS_PLL_UPDATE_ADDR_MASK                                             0x0003FFFFL
>+//DPCSTX4_DPCSTX_PLL_UPDATE_DATA
>+#define DPCSTX4_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA__SHIFT                                           0x0
>+#define DPCSTX4_DPCSTX_PLL_UPDATE_DATA__DPCS_PLL_UPDATE_DATA_MASK                                             0xFFFFFFFFL
>+//DPCSTX4_DPCSTX_DEBUG_CONFIG
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN__SHIFT                                                       0x0
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL__SHIFT                                               0x1
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL__SHIFT                                            0x4
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL__SHIFT                                       0x8
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS__SHIFT                                                 0xe
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN__SHIFT                                          0x10
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX__SHIFT                                             0x18
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_EN_MASK                                                         0x00000001L
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CFGCLK_SEL_MASK                                                 0x0000000EL
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_SEL_MASK                                              0x00000070L
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_TX_SYMCLK_DIV2_SEL_MASK                                         0x00000700L
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_DBG_CBUS_DIS_MASK                                                   0x00004000L
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_WRITE_EN_MASK                                            0x00010000L
>+#define DPCSTX4_DPCSTX_DEBUG_CONFIG__DPCS_TEST_DEBUG_INDEX_MASK                                               0xFF000000L
>+
>+
>+// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
>+//RDPCSTX4_RDPCSTX_CNTL
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x4
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x10
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x11
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1a
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000010L
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x00010000L
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x00020000L
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x04000000L
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
>+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
>+//RDPCSTX4_RDPCSTX_CLOCK_CNTL
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT                                          0x4
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT                                          0x5
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT                                          0x6
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT                                          0x7
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT                                        0x8
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT                                              0x9
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT                                        0xa
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK                                            0x00000010L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK                                            0x00000020L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK                                            0x00000040L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK                                            0x00000080L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK                                          0x00000100L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK                                                0x00000200L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK                                          0x00000400L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
>+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
>+//RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
>+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
>+//RDPCSTX4_RDPCSTX_PLL_UPDATE_DATA
>+#define RDPCSTX4_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                        0x0
>+#define RDPCSTX4_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                          0x00000001L
>+//RDPCSTX4_RDPCS_TX_CR_ADDR
>+#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
>+#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
>+//RDPCSTX4_RDPCS_TX_CR_DATA
>+#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
>+#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
>+//RDPCSTX4_RDPCS_TX_SRAM_CNTL
>+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
>+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
>+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
>+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
>+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
>+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
>+//RDPCSTX4_RDPCSTX_SCRATCH
>+#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
>+#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
>+//RDPCSTX4_RDPCSTX_SPARE
>+#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
>+#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
>+//RDPCSTX4_RDPCSTX_CNTL2
>+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
>+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
>+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
>+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
>+//RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT              0x4
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK                0x00000010L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
>+//RDPCSTX4_RDPCSTX_DEBUG_CONFIG
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL1
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL2
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL3
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL4
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL5
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL6
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL7
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL8
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
>+//RDPCSTX4_RDPCSTX_PHY_CNTL9
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL10
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
>+//RDPCSTX4_RDPCSTX_PHY_CNTL11
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL12
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL13
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL14
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
>+//RDPCSTX4_RDPCSTX_PHY_FUSE0
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
>+//RDPCSTX4_RDPCSTX_PHY_FUSE1
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
>+//RDPCSTX4_RDPCSTX_PHY_FUSE2
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
>+//RDPCSTX4_RDPCSTX_PHY_FUSE3
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
>+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
>+//RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL
>+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
>+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
>+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
>+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
>+//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
>+//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
>+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
>+//RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG
>+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
>+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
>+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
>+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
>+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
>+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL15
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL16
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
>+//RDPCSTX4_RDPCSTX_PHY_CNTL17
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
>+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
>+//RDPCSTX4_RDPCSTX_DEBUG_CONFIG2
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
>+#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
>+
>+
>+// addressBlock: dpcssys_dpcssys_cr4_dispdec
>+//DPCSSYS_CR4_DPCSSYS_CR_ADDR
>+#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
>+#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
>+//DPCSSYS_CR4_DPCSSYS_CR_DATA
>+#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
>+#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h	2019-08-31 15:01:11.887736171 -0500
>@@ -48,4 +48,8 @@
> #define smnPerfMonCtrLo3					0x01d478UL
> #define smnPerfMonCtrHi3					0x01d47cUL
> 
>+#define smnDF_PIE_AON_FabricIndirectConfigAccessAddress3	0x1d05cUL
>+#define smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3		0x1d098UL
>+#define smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3		0x1d09cUL
>+
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h	2019-08-31 15:01:11.889736171 -0500
>@@ -10107,6 +10107,8 @@
> #define mmCGTT_IA_CLK_CTRL_BASE_IDX                                                                    1
> #define mmCGTT_WD_CLK_CTRL                                                                             0x5086
> #define mmCGTT_WD_CLK_CTRL_BASE_IDX                                                                    1
>+#define mmCGTT_GS_NGG_CLK_CTRL                                                                         0x5087
>+#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX                                                                1
> #define mmCGTT_PA_CLK_CTRL                                                                             0x5088
> #define mmCGTT_PA_CLK_CTRL_BASE_IDX                                                                    1
> #define mmCGTT_SC_CLK_CTRL0                                                                            0x5089
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h	2019-08-31 15:01:11.903736172 -0500
>@@ -37872,6 +37872,45 @@
> #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK                                                                  0x20000000L
> #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK                                                            0x40000000L
> #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK                                                                   0x80000000L
>+//CGTT_GS_NGG_CLK_CTRL
>+#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT                                                                 0x0
>+#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                           0x4
>+#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT                                                              0xf
>+#define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE__SHIFT                                                               0x10
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT                                                     0x11
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT                                                     0x12
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT                                                     0x13
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT                                                     0x14
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT                                                     0x15
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT                                                     0x16
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT                                                     0x17
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                           0x18
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                           0x19
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                           0x1a
>+#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT                                                         0x1b
>+#define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE__SHIFT                                                             0x1c
>+#define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE__SHIFT                                                             0x1d
>+#define CGTT_GS_NGG_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT                                                      0x1e
>+#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT                                                             0x1f
>+#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK                                                                   0x0000000FL
>+#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK                                                             0x00000FF0L
>+#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK                                                                0x00008000L
>+#define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE_MASK                                                                 0x00010000L
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK                                                       0x00020000L
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK                                                       0x00040000L
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK                                                       0x00080000L
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK                                                       0x00100000L
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK                                                       0x00200000L
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK                                                       0x00400000L
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK                                                       0x00800000L
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                             0x01000000L
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                             0x02000000L
>+#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                             0x04000000L
>+#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK                                                           0x08000000L
>+#define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE_MASK                                                               0x10000000L
>+#define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE_MASK                                                               0x20000000L
>+#define CGTT_GS_NGG_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK                                                        0x40000000L
>+#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK                                                               0x80000000L
> //CGTT_PA_CLK_CTRL
> #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT                                                                     0x0
> #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                               0x4
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h	2019-08-31 15:01:11.904736172 -0500
>@@ -1700,6 +1700,8 @@
> #define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX                                                           0
> #define mmTCP_EDC_CNT                                                                                  0x0b17
> #define mmTCP_EDC_CNT_BASE_IDX                                                                         0
>+#define mmTCP_EDC_CNT_NEW                                                                              0x0b18
>+#define mmTCP_EDC_CNT_NEW_BASE_IDX                                                                     0
> #define mmTC_CFG_L1_LOAD_POLICY0                                                                       0x0b1a
> #define mmTC_CFG_L1_LOAD_POLICY0_BASE_IDX                                                              0
> #define mmTC_CFG_L1_LOAD_POLICY1                                                                       0x0b1b
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h	2019-08-31 15:01:11.905736172 -0500
>@@ -21,6 +21,105 @@
> #ifndef _gc_9_0_SH_MASK_HEADER
> #define _gc_9_0_SH_MASK_HEADER
> 
>+//GCEA_EDC_CNT
>+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                          0x0
>+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                          0x2
>+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                          0x4
>+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
>+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                         0x8
>+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                         0xa
>+#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                            0xc
>+#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                            0xe
>+#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                            0x10
>+#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                            0x12
>+#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                         0x14
>+#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                         0x16
>+#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                            0x18
>+#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                            0x1a
>+#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                           0x1c
>+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                            0x00000003L
>+#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                            0x0000000CL
>+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                            0x00000030L
>+#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
>+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                           0x00000300L
>+#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                           0x00000C00L
>+#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                              0x00003000L
>+#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                              0x0000C000L
>+#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                              0x00030000L
>+#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                              0x000C0000L
>+#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                           0x00300000L
>+#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                           0x00C00000L
>+#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                              0x03000000L
>+#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                              0x0C000000L
>+#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                             0x30000000L
>+
>+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                          0x0
>+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                          0x2
>+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                          0x4
>+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
>+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                         0x8
>+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                         0xa
>+#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                         0xc
>+#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                         0xe
>+#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                             0x10
>+#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                             0x12
>+#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                             0x14
>+#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                             0x16
>+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                            0x00000003L
>+#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                            0x0000000CL
>+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                            0x00000030L
>+#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
>+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                           0x00000300L
>+#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                           0x00000C00L
>+#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                           0x00003000L
>+#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                           0x0000C000L
>+#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                               0x00030000L
>+#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                               0x000C0000L
>+#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                               0x00300000L
>+#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                               0x00C00000L
>+
>+// addressBlock: gc_cppdec2
>+//CPF_EDC_TAG_CNT
>+#define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT                                                                     0x0
>+#define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT                                                                     0x2
>+#define CPF_EDC_TAG_CNT__DED_COUNT_MASK                                                                       0x00000003L
>+#define CPF_EDC_TAG_CNT__SEC_COUNT_MASK                                                                       0x0000000CL
>+//CPF_EDC_ROQ_CNT
>+#define CPF_EDC_ROQ_CNT__COUNT_ME1__SHIFT                                                                     0x0
>+#define CPF_EDC_ROQ_CNT__COUNT_ME2__SHIFT                                                                     0x2
>+#define CPF_EDC_ROQ_CNT__COUNT_ME1_MASK                                                                       0x00000003L
>+#define CPF_EDC_ROQ_CNT__COUNT_ME2_MASK                                                                       0x0000000CL
>+//CPG_EDC_TAG_CNT
>+#define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT                                                                     0x0
>+#define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT                                                                     0x2
>+#define CPG_EDC_TAG_CNT__DED_COUNT_MASK                                                                       0x00000003L
>+#define CPG_EDC_TAG_CNT__SEC_COUNT_MASK                                                                       0x0000000CL
>+//CPG_EDC_DMA_CNT
>+#define CPG_EDC_DMA_CNT__ROQ_COUNT__SHIFT                                                                     0x0
>+#define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT                                                                 0x2
>+#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT                                                                 0x4
>+#define CPG_EDC_DMA_CNT__ROQ_COUNT_MASK                                                                       0x00000003L
>+#define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK                                                                   0x0000000CL
>+#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK                                                                   0x00000030L
>+//CPC_EDC_SCRATCH_CNT
>+#define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT                                                                 0x0
>+#define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT                                                                 0x2
>+#define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK                                                                   0x00000003L
>+#define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK                                                                   0x0000000CL
>+//CPC_EDC_UCODE_CNT
>+#define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT                                                                   0x0
>+#define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT                                                                   0x2
>+#define CPC_EDC_UCODE_CNT__DED_COUNT_MASK                                                                     0x00000003L
>+#define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK                                                                     0x0000000CL
>+//DC_EDC_STATE_CNT
>+#define DC_EDC_STATE_CNT__COUNT_ME1__SHIFT                                                                    0x0
>+#define DC_EDC_STATE_CNT__COUNT_ME1_MASK                                                                      0x00000003L
>+//DC_EDC_CSINVOC_CNT
>+#define DC_EDC_CSINVOC_CNT__COUNT_ME1__SHIFT                                                                  0x0
>+#define DC_EDC_CSINVOC_CNT__COUNT_ME1_MASK                                                                    0x00000003L
>+//DC_EDC_RESTORE_CNT
>+#define DC_EDC_RESTORE_CNT__COUNT_ME1__SHIFT                                                                  0x0
>+#define DC_EDC_RESTORE_CNT__COUNT_ME1_MASK                                                                    0x00000003L
> 
> // addressBlock: gc_grbmdec
> //GRBM_CNTL
>@@ -9033,11 +9132,15 @@
> #define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT                                                      0x4
> #define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT                                                  0x6
> #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT                                                   0x8
>+#define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT__SHIFT                                                 0xa
>+#define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT__SHIFT                                                   0xc
> #define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK                                                             0x00000003L
> #define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK                                                         0x0000000CL
> #define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK                                                        0x00000030L
> #define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK                                                    0x000000C0L
> #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK                                                     0x00000300L
>+#define TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT_MASK                                                   0x00000C00L
>+#define TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT_MASK                                                     0x00003000L
> //TCC_REDUNDANCY
> #define TCC_REDUNDANCY__MC_SEL0__SHIFT                                                                        0x0
> #define TCC_REDUNDANCY__MC_SEL1__SHIFT                                                                        0x1
>@@ -29818,6 +29921,60 @@
> #define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT                                         0x0
> #define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK                                           0xFFFFFFFFL
> 
>-
>+//TA_EDC_CNT
>+#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT                                                              0x0
>+#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT                                                              0x2
>+#define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT__SHIFT                                                              0x4
>+#define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT__SHIFT                                                              0x6
>+#define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT__SHIFT                                                              0x8
>+#define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT__SHIFT                                                              0xa
>+#define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK                                                                0x00000003L
>+#define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK                                                                0x0000000CL
>+#define TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT_MASK                                                                0x00000030L
>+#define TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT_MASK                                                                0x000000C0L
>+#define TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT_MASK                                                                0x00000300L
>+#define TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT_MASK                                                                0x00000C00L
>+
>+//TCI_EDC_CNT
>+#define TCI_EDC_CNT__WRITE_RAM_SED_COUNT__SHIFT                                                               0x0
>+#define TCI_EDC_CNT__WRITE_RAM_SED_COUNT_MASK                                                                 0x00000003L
>+
>+//TCP_EDC_CNT_NEW
>+#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT                                                           0x0
>+#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT                                                           0x2
>+#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT                                                           0x4
>+#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT                                                           0x6
>+#define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT__SHIFT                                                            0x8
>+#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT                                                             0xa
>+#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT                                                             0xc
>+#define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT__SHIFT                                                              0xe
>+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT                                                        0x10
>+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT                                                        0x12
>+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT                                                        0x14
>+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT                                                        0x16
>+#define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK                                                             0x00000003L
>+#define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK                                                             0x0000000CL
>+#define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK                                                             0x00000030L
>+#define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK                                                             0x000000C0L
>+#define TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT_MASK                                                              0x00000300L
>+#define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK                                                               0x00000C00L
>+#define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK                                                               0x00003000L
>+#define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT_MASK                                                                0x0000C000L
>+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK                                                          0x00030000L
>+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK                                                          0x000C0000L
>+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK                                                          0x00300000L
>+#define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK                                                          0x00C00000L
>+
>+//TD_EDC_CNT
>+#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT                                                               0x0
>+#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT                                                               0x2
>+#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT                                                               0x4
>+#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT                                                               0x6
>+#define TD_EDC_CNT__CS_FIFO_SED_COUNT__SHIFT                                                                  0x8
>+#define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK                                                                 0x00000003L
>+#define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK                                                                 0x0000000CL
>+#define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK                                                                 0x00000030L
>+#define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK                                                                 0x000000C0L
>+#define TD_EDC_CNT__CS_FIFO_SED_COUNT_MASK                                                                    0x00000300L
> 
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_offset.h	2019-08-31 15:01:11.905736172 -0500
>@@ -21,6 +21,27 @@
> #ifndef _mmhub_9_4_0_OFFSET_HEADER
> #define _mmhub_9_4_0_OFFSET_HEADER
> 
>+/* MMEA */
>+#define mmMMEA0_SDP_ARB_FINAL_VG20                                                                     0x01ee
>+#define mmMMEA0_SDP_ARB_FINAL_VG20_BASE_IDX                                                            0
>+#define mmMMEA0_EDC_CNT_VG20                                                                           0x0206
>+#define mmMMEA0_EDC_CNT_VG20_BASE_IDX                                                                  0
>+#define mmMMEA0_EDC_CNT2_VG20                                                                          0x0207
>+#define mmMMEA0_EDC_CNT2_VG20_BASE_IDX                                                                 0
>+#define mmMMEA0_EDC_MODE_VG20                                                                          0x0210
>+#define mmMMEA0_EDC_MODE_VG20_BASE_IDX                                                                 0
>+#define mmMMEA0_ERR_STATUS_VG20                                                                        0x0211
>+#define mmMMEA0_ERR_STATUS_VG20_BASE_IDX                                                               0
>+#define mmMMEA1_SDP_ARB_FINAL_VG20                                                                     0x032e
>+#define mmMMEA1_SDP_ARB_FINAL_VG20_BASE_IDX                                                            0
>+#define mmMMEA1_EDC_CNT_VG20                                                                           0x0346
>+#define mmMMEA1_EDC_CNT_VG20_BASE_IDX                                                                  0
>+#define mmMMEA1_EDC_CNT2_VG20                                                                          0x0347
>+#define mmMMEA1_EDC_CNT2_VG20_BASE_IDX                                                                 0
>+#define mmMMEA1_EDC_MODE_VG20                                                                          0x0350
>+#define mmMMEA1_EDC_MODE_VG20_BASE_IDX                                                                 0
>+#define mmMMEA1_ERR_STATUS_VG20                                                                        0x0351
>+#define mmMMEA1_ERR_STATUS_VG20_BASE_IDX                                                               0
> 
> // addressBlock: mmhub_utcl2_vmsharedpfdec
> // base address: 0x6a040
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_0_sh_mask.h	2019-08-31 15:01:11.905736172 -0500
>@@ -21,6 +21,228 @@
> #ifndef _mmhub_9_4_0_SH_MASK_HEADER
> #define _mmhub_9_4_0_SH_MASK_HEADER
> 
>+//MMEA0_SDP_ARB_FINAL
>+#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
>+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
>+#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
>+#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
>+#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
>+#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
>+#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
>+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
>+#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
>+#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
>+#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
>+#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
>+//MMEA0_EDC_CNT
>+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
>+#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
>+#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
>+#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
>+#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
>+#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
>+#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
>+#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
>+#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
>+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
>+#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
>+#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
>+#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
>+#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
>+#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
>+#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
>+#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
>+#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
>+//MMEA0_EDC_CNT2
>+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
>+#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
>+#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
>+#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
>+#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
>+#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
>+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
>+#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
>+#define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
>+#define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
>+#define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
>+#define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
>+//MMEA0_EDC_MODE
>+#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
>+#define MMEA0_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
>+#define MMEA0_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
>+#define MMEA0_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
>+#define MMEA0_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
>+#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
>+#define MMEA0_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
>+#define MMEA0_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
>+#define MMEA0_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
>+#define MMEA0_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
>+//MMEA0_ERR_STATUS
>+#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
>+#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
>+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
>+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
>+#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
>+#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
>+#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
>+#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
>+#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
>+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
>+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
>+#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
>+#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
>+#define MMEA0_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
>+//MMEA1_SDP_ARB_FINAL
>+#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
>+#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
>+#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
>+#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
>+#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
>+#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
>+#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
>+#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
>+#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
>+#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
>+#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
>+#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
>+//MMEA1_EDC_CNT
>+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
>+#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
>+#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
>+#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
>+#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
>+#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
>+#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
>+#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
>+#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
>+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
>+#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
>+#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
>+#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
>+#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
>+#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
>+#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
>+#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
>+#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
>+//MMEA1_EDC_CNT2
>+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
>+#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
>+#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT                                                            0x10
>+#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT                                                            0x12
>+#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT                                                            0x14
>+#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT                                                            0x16
>+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
>+#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
>+#define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK                                                              0x00030000L
>+#define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK                                                              0x000C0000L
>+#define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK                                                              0x00300000L
>+#define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK                                                              0x00C00000L
>+//MMEA1_EDC_MODE
>+#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
>+#define MMEA1_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
>+#define MMEA1_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
>+#define MMEA1_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
>+#define MMEA1_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
>+#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
>+#define MMEA1_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
>+#define MMEA1_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
>+#define MMEA1_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
>+#define MMEA1_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
>+//MMEA1_ERR_STATUS
>+#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
>+#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
>+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
>+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
>+#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
>+#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
>+#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
>+#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
>+#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
>+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
>+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
>+#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
>+#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
>+#define MMEA1_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
> 
> // addressBlock: mmhub_utcl2_vmsharedpfdec
> //MC_VM_XGMI_LFB_CNTL
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_default.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_default.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_default.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_default.h	2019-08-31 15:01:11.906736172 -0500
>@@ -0,0 +1,3933 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _mmhub_9_4_1_DEFAULT_HEADER
>+#define _mmhub_9_4_1_DEFAULT_HEADER
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec0
>+#define mmDAGB0_RDCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_RDCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_RDCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_RDCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_RDCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_RDCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_RDCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_RDCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_RDCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_RDCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_RDCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB0_RDCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB0_RDCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB0_RDCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB0_RDCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB0_RDCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB0_RD_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB0_RD_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB0_RD_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB0_RD_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_RD_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_RD_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_RD_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_RD_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_RD_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_RD_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_RD_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_RD_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB0_RD_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB0_WRCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_WRCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_WRCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_WRCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_WRCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_WRCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_WRCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_WRCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_WRCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_WRCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB0_WRCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB0_WRCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB0_WRCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB0_WRCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB0_WRCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB0_WRCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB0_WR_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB0_WR_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB0_WR_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB0_WR_DATA_DAGB_DEFAULT                                             0x00000001
>+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT                                  0x11111111
>+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT                                 0x00000000
>+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT                                  0x11111111
>+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT                                 0x00000000
>+#define mmDAGB0_WR_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_WR_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_WR_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_WR_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_WR_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_WR_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_WR_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_WR_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB0_WR_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB0_WR_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB0_WR_DATA_CREDIT_DEFAULT                                           0x60606070
>+#define mmDAGB0_WR_MISC_CREDIT_DEFAULT                                           0x0078dc88
>+#define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB0_WRCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT                                   0x00000000
>+#define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB0_DAGB_DLY_DEFAULT                                                 0x00000000
>+#define mmDAGB0_CNTL_MISC_DEFAULT                                                0xcf7c1ffa
>+#define mmDAGB0_CNTL_MISC2_DEFAULT                                               0x003c0000
>+#define mmDAGB0_FIFO_EMPTY_DEFAULT                                               0x00ffffff
>+#define mmDAGB0_FIFO_FULL_DEFAULT                                                0x00000000
>+#define mmDAGB0_WR_CREDITS_FULL_DEFAULT                                          0x1fffffff
>+#define mmDAGB0_RD_CREDITS_FULL_DEFAULT                                          0x0003ffff
>+#define mmDAGB0_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmDAGB0_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmDAGB0_RESERVE0_DEFAULT                                                 0xffffffff
>+#define mmDAGB0_RESERVE1_DEFAULT                                                 0xffffffff
>+#define mmDAGB0_RESERVE2_DEFAULT                                                 0xffffffff
>+#define mmDAGB0_RESERVE3_DEFAULT                                                 0xffffffff
>+#define mmDAGB0_RESERVE4_DEFAULT                                                 0xffffffff
>+#define mmDAGB0_RESERVE5_DEFAULT                                                 0xffffffff
>+#define mmDAGB0_RESERVE6_DEFAULT                                                 0xffffffff
>+#define mmDAGB0_RESERVE7_DEFAULT                                                 0xffffffff
>+#define mmDAGB0_RESERVE8_DEFAULT                                                 0xffffffff
>+#define mmDAGB0_RESERVE9_DEFAULT                                                 0xffffffff
>+#define mmDAGB0_RESERVE10_DEFAULT                                                0xffffffff
>+#define mmDAGB0_RESERVE11_DEFAULT                                                0xffffffff
>+#define mmDAGB0_RESERVE12_DEFAULT                                                0xffffffff
>+#define mmDAGB0_RESERVE13_DEFAULT                                                0xffffffff
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec1
>+#define mmDAGB1_RDCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_RDCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_RDCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_RDCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_RDCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_RDCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_RDCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_RDCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_RDCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_RDCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_RDCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB1_RDCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB1_RDCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB1_RDCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB1_RDCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB1_RDCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB1_RD_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB1_RD_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB1_RD_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB1_RD_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB1_RD_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_RD_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_RD_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_RD_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_RD_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_RD_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_RD_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_RD_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_RD_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB1_RD_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB1_RDCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB1_RDCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB1_RDCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB1_RDCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB1_RDCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB1_RDCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB1_WRCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_WRCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_WRCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_WRCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_WRCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_WRCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_WRCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_WRCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_WRCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_WRCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB1_WRCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB1_WRCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB1_WRCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB1_WRCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB1_WRCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB1_WRCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB1_WR_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB1_WR_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB1_WR_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB1_WR_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB1_WR_DATA_DAGB_DEFAULT                                             0x00000001
>+#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_DEFAULT                                  0x11111111
>+#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT                                 0x00000000
>+#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_DEFAULT                                  0x11111111
>+#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT                                 0x00000000
>+#define mmDAGB1_WR_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_WR_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_WR_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_WR_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_WR_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_WR_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_WR_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_WR_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB1_WR_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB1_WR_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB1_WR_DATA_CREDIT_DEFAULT                                           0x60606070
>+#define mmDAGB1_WR_MISC_CREDIT_DEFAULT                                           0x0078dc88
>+#define mmDAGB1_WRCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB1_WRCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB1_WRCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB1_WRCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB1_WRCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB1_WRCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_DEFAULT                                   0x00000000
>+#define mmDAGB1_WRCLI_DBUS_GO_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB1_DAGB_DLY_DEFAULT                                                 0x00000000
>+#define mmDAGB1_CNTL_MISC_DEFAULT                                                0xcf7c1ffa
>+#define mmDAGB1_CNTL_MISC2_DEFAULT                                               0x003c0000
>+#define mmDAGB1_FIFO_EMPTY_DEFAULT                                               0x00ffffff
>+#define mmDAGB1_FIFO_FULL_DEFAULT                                                0x00000000
>+#define mmDAGB1_WR_CREDITS_FULL_DEFAULT                                          0x1fffffff
>+#define mmDAGB1_RD_CREDITS_FULL_DEFAULT                                          0x0003ffff
>+#define mmDAGB1_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmDAGB1_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmDAGB1_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB1_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB1_PERFCOUNTER2_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmDAGB1_RESERVE0_DEFAULT                                                 0xffffffff
>+#define mmDAGB1_RESERVE1_DEFAULT                                                 0xffffffff
>+#define mmDAGB1_RESERVE2_DEFAULT                                                 0xffffffff
>+#define mmDAGB1_RESERVE3_DEFAULT                                                 0xffffffff
>+#define mmDAGB1_RESERVE4_DEFAULT                                                 0xffffffff
>+#define mmDAGB1_RESERVE5_DEFAULT                                                 0xffffffff
>+#define mmDAGB1_RESERVE6_DEFAULT                                                 0xffffffff
>+#define mmDAGB1_RESERVE7_DEFAULT                                                 0xffffffff
>+#define mmDAGB1_RESERVE8_DEFAULT                                                 0xffffffff
>+#define mmDAGB1_RESERVE9_DEFAULT                                                 0xffffffff
>+#define mmDAGB1_RESERVE10_DEFAULT                                                0xffffffff
>+#define mmDAGB1_RESERVE11_DEFAULT                                                0xffffffff
>+#define mmDAGB1_RESERVE12_DEFAULT                                                0xffffffff
>+#define mmDAGB1_RESERVE13_DEFAULT                                                0xffffffff
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec2
>+#define mmDAGB2_RDCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_RDCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_RDCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_RDCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_RDCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_RDCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_RDCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_RDCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_RDCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_RDCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_RDCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB2_RDCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB2_RDCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB2_RDCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB2_RDCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB2_RDCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB2_RD_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB2_RD_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB2_RD_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB2_RD_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB2_RD_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_RD_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_RD_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_RD_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_RD_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_RD_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_RD_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_RD_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_RD_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB2_RD_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB2_RDCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB2_RDCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB2_RDCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB2_RDCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB2_RDCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB2_RDCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB2_WRCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_WRCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_WRCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_WRCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_WRCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_WRCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_WRCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_WRCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_WRCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_WRCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB2_WRCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB2_WRCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB2_WRCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB2_WRCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB2_WRCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB2_WRCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB2_WR_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB2_WR_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB2_WR_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB2_WR_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB2_WR_DATA_DAGB_DEFAULT                                             0x00000001
>+#define mmDAGB2_WR_DATA_DAGB_MAX_BURST0_DEFAULT                                  0x11111111
>+#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT                                 0x00000000
>+#define mmDAGB2_WR_DATA_DAGB_MAX_BURST1_DEFAULT                                  0x11111111
>+#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT                                 0x00000000
>+#define mmDAGB2_WR_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_WR_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_WR_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_WR_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_WR_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_WR_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_WR_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_WR_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB2_WR_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB2_WR_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB2_WR_DATA_CREDIT_DEFAULT                                           0x60606070
>+#define mmDAGB2_WR_MISC_CREDIT_DEFAULT                                           0x0078dc88
>+#define mmDAGB2_WRCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB2_WRCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB2_WRCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB2_WRCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB2_WRCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB2_WRCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB2_WRCLI_DBUS_ASK_PENDING_DEFAULT                                   0x00000000
>+#define mmDAGB2_WRCLI_DBUS_GO_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB2_DAGB_DLY_DEFAULT                                                 0x00000000
>+#define mmDAGB2_CNTL_MISC_DEFAULT                                                0xcf7c1ffa
>+#define mmDAGB2_CNTL_MISC2_DEFAULT                                               0x003c0000
>+#define mmDAGB2_FIFO_EMPTY_DEFAULT                                               0x00ffffff
>+#define mmDAGB2_FIFO_FULL_DEFAULT                                                0x00000000
>+#define mmDAGB2_WR_CREDITS_FULL_DEFAULT                                          0x1fffffff
>+#define mmDAGB2_RD_CREDITS_FULL_DEFAULT                                          0x0003ffff
>+#define mmDAGB2_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmDAGB2_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmDAGB2_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB2_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB2_PERFCOUNTER2_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB2_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmDAGB2_RESERVE0_DEFAULT                                                 0xffffffff
>+#define mmDAGB2_RESERVE1_DEFAULT                                                 0xffffffff
>+#define mmDAGB2_RESERVE2_DEFAULT                                                 0xffffffff
>+#define mmDAGB2_RESERVE3_DEFAULT                                                 0xffffffff
>+#define mmDAGB2_RESERVE4_DEFAULT                                                 0xffffffff
>+#define mmDAGB2_RESERVE5_DEFAULT                                                 0xffffffff
>+#define mmDAGB2_RESERVE6_DEFAULT                                                 0xffffffff
>+#define mmDAGB2_RESERVE7_DEFAULT                                                 0xffffffff
>+#define mmDAGB2_RESERVE8_DEFAULT                                                 0xffffffff
>+#define mmDAGB2_RESERVE9_DEFAULT                                                 0xffffffff
>+#define mmDAGB2_RESERVE10_DEFAULT                                                0xffffffff
>+#define mmDAGB2_RESERVE11_DEFAULT                                                0xffffffff
>+#define mmDAGB2_RESERVE12_DEFAULT                                                0xffffffff
>+#define mmDAGB2_RESERVE13_DEFAULT                                                0xffffffff
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec3
>+#define mmDAGB3_RDCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_RDCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_RDCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_RDCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_RDCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_RDCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_RDCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_RDCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_RDCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_RDCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_RDCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB3_RDCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB3_RDCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB3_RDCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB3_RDCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB3_RDCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB3_RD_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB3_RD_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB3_RD_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB3_RD_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB3_RD_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_RD_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_RD_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_RD_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_RD_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_RD_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_RD_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_RD_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_RD_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB3_RD_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB3_RDCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB3_RDCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB3_RDCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB3_RDCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB3_RDCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB3_RDCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB3_WRCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_WRCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_WRCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_WRCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_WRCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_WRCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_WRCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_WRCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_WRCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_WRCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB3_WRCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB3_WRCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB3_WRCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB3_WRCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB3_WRCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB3_WRCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB3_WR_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB3_WR_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB3_WR_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB3_WR_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB3_WR_DATA_DAGB_DEFAULT                                             0x00000001
>+#define mmDAGB3_WR_DATA_DAGB_MAX_BURST0_DEFAULT                                  0x11111111
>+#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT                                 0x00000000
>+#define mmDAGB3_WR_DATA_DAGB_MAX_BURST1_DEFAULT                                  0x11111111
>+#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT                                 0x00000000
>+#define mmDAGB3_WR_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_WR_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_WR_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_WR_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_WR_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_WR_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_WR_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_WR_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB3_WR_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB3_WR_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB3_WR_DATA_CREDIT_DEFAULT                                           0x60606070
>+#define mmDAGB3_WR_MISC_CREDIT_DEFAULT                                           0x0078dc88
>+#define mmDAGB3_WRCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB3_WRCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB3_WRCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB3_WRCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB3_WRCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB3_WRCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB3_WRCLI_DBUS_ASK_PENDING_DEFAULT                                   0x00000000
>+#define mmDAGB3_WRCLI_DBUS_GO_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB3_DAGB_DLY_DEFAULT                                                 0x00000000
>+#define mmDAGB3_CNTL_MISC_DEFAULT                                                0xcf7c1ffa
>+#define mmDAGB3_CNTL_MISC2_DEFAULT                                               0x003c0000
>+#define mmDAGB3_FIFO_EMPTY_DEFAULT                                               0x00ffffff
>+#define mmDAGB3_FIFO_FULL_DEFAULT                                                0x00000000
>+#define mmDAGB3_WR_CREDITS_FULL_DEFAULT                                          0x1fffffff
>+#define mmDAGB3_RD_CREDITS_FULL_DEFAULT                                          0x0003ffff
>+#define mmDAGB3_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmDAGB3_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmDAGB3_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB3_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB3_PERFCOUNTER2_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB3_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmDAGB3_RESERVE0_DEFAULT                                                 0xffffffff
>+#define mmDAGB3_RESERVE1_DEFAULT                                                 0xffffffff
>+#define mmDAGB3_RESERVE2_DEFAULT                                                 0xffffffff
>+#define mmDAGB3_RESERVE3_DEFAULT                                                 0xffffffff
>+#define mmDAGB3_RESERVE4_DEFAULT                                                 0xffffffff
>+#define mmDAGB3_RESERVE5_DEFAULT                                                 0xffffffff
>+#define mmDAGB3_RESERVE6_DEFAULT                                                 0xffffffff
>+#define mmDAGB3_RESERVE7_DEFAULT                                                 0xffffffff
>+#define mmDAGB3_RESERVE8_DEFAULT                                                 0xffffffff
>+#define mmDAGB3_RESERVE9_DEFAULT                                                 0xffffffff
>+#define mmDAGB3_RESERVE10_DEFAULT                                                0xffffffff
>+#define mmDAGB3_RESERVE11_DEFAULT                                                0xffffffff
>+#define mmDAGB3_RESERVE12_DEFAULT                                                0xffffffff
>+#define mmDAGB3_RESERVE13_DEFAULT                                                0xffffffff
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec4
>+#define mmDAGB4_RDCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_RDCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_RDCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_RDCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_RDCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_RDCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_RDCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_RDCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_RDCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_RDCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_RDCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB4_RDCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB4_RDCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB4_RDCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB4_RDCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB4_RDCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB4_RD_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB4_RD_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB4_RD_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB4_RD_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB4_RD_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_RD_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_RD_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_RD_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_RD_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_RD_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_RD_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_RD_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_RD_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB4_RD_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB4_RDCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB4_RDCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB4_RDCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB4_RDCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB4_RDCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB4_RDCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB4_WRCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_WRCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_WRCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_WRCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_WRCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_WRCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_WRCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_WRCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_WRCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_WRCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB4_WRCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB4_WRCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB4_WRCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB4_WRCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB4_WRCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB4_WRCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB4_WR_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB4_WR_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB4_WR_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB4_WR_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB4_WR_DATA_DAGB_DEFAULT                                             0x00000001
>+#define mmDAGB4_WR_DATA_DAGB_MAX_BURST0_DEFAULT                                  0x11111111
>+#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT                                 0x00000000
>+#define mmDAGB4_WR_DATA_DAGB_MAX_BURST1_DEFAULT                                  0x11111111
>+#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT                                 0x00000000
>+#define mmDAGB4_WR_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_WR_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_WR_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_WR_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_WR_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_WR_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_WR_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_WR_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB4_WR_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB4_WR_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB4_WR_DATA_CREDIT_DEFAULT                                           0x60606070
>+#define mmDAGB4_WR_MISC_CREDIT_DEFAULT                                           0x0078dc88
>+#define mmDAGB4_WRCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB4_WRCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB4_WRCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB4_WRCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB4_WRCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB4_WRCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB4_WRCLI_DBUS_ASK_PENDING_DEFAULT                                   0x00000000
>+#define mmDAGB4_WRCLI_DBUS_GO_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB4_DAGB_DLY_DEFAULT                                                 0x00000000
>+#define mmDAGB4_CNTL_MISC_DEFAULT                                                0xcf7c1ffa
>+#define mmDAGB4_CNTL_MISC2_DEFAULT                                               0x003c0000
>+#define mmDAGB4_FIFO_EMPTY_DEFAULT                                               0x00ffffff
>+#define mmDAGB4_FIFO_FULL_DEFAULT                                                0x00000000
>+#define mmDAGB4_WR_CREDITS_FULL_DEFAULT                                          0x1fffffff
>+#define mmDAGB4_RD_CREDITS_FULL_DEFAULT                                          0x0003ffff
>+#define mmDAGB4_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmDAGB4_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmDAGB4_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB4_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB4_PERFCOUNTER2_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB4_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmDAGB4_RESERVE0_DEFAULT                                                 0xffffffff
>+#define mmDAGB4_RESERVE1_DEFAULT                                                 0xffffffff
>+#define mmDAGB4_RESERVE2_DEFAULT                                                 0xffffffff
>+#define mmDAGB4_RESERVE3_DEFAULT                                                 0xffffffff
>+#define mmDAGB4_RESERVE4_DEFAULT                                                 0xffffffff
>+#define mmDAGB4_RESERVE5_DEFAULT                                                 0xffffffff
>+#define mmDAGB4_RESERVE6_DEFAULT                                                 0xffffffff
>+#define mmDAGB4_RESERVE7_DEFAULT                                                 0xffffffff
>+#define mmDAGB4_RESERVE8_DEFAULT                                                 0xffffffff
>+#define mmDAGB4_RESERVE9_DEFAULT                                                 0xffffffff
>+#define mmDAGB4_RESERVE10_DEFAULT                                                0xffffffff
>+#define mmDAGB4_RESERVE11_DEFAULT                                                0xffffffff
>+#define mmDAGB4_RESERVE12_DEFAULT                                                0xffffffff
>+#define mmDAGB4_RESERVE13_DEFAULT                                                0xffffffff
>+
>+
>+// addressBlock: mmhub_ea_mmeadec0
>+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA0_DRAM_RD_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA0_DRAM_WR_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA0_DRAM_PAGE_BURST_DEFAULT                                          0x20002000
>+#define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA0_GMI_RD_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA0_GMI_RD_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA0_GMI_WR_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA0_GMI_WR_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA0_GMI_RD_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA0_GMI_WR_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA0_GMI_RD_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA0_GMI_WR_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA0_GMI_RD_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA0_GMI_WR_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA0_GMI_PAGE_BURST_DEFAULT                                           0x20002000
>+#define mmMMEA0_GMI_RD_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA0_GMI_WR_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA0_GMI_RD_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA0_GMI_WR_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA0_GMI_RD_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA0_GMI_WR_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA0_GMI_RD_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA0_GMI_WR_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA0_GMI_RD_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA0_GMI_RD_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA0_GMI_RD_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA0_GMI_WR_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA0_GMI_WR_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA0_GMI_WR_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT                                      0x00000000
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT                                     0x00000000
>+#define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT                                      0x00000000
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT                                     0x00000000
>+#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT                                    0x00000000
>+#define mmMMEA0_ADDRNORM_BASE_ADDR2_DEFAULT                                      0x00000000
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR2_DEFAULT                                     0x00000000
>+#define mmMMEA0_ADDRNORM_BASE_ADDR3_DEFAULT                                      0x00000000
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR3_DEFAULT                                     0x00000000
>+#define mmMMEA0_ADDRNORM_OFFSET_ADDR3_DEFAULT                                    0x00000000
>+#define mmMMEA0_ADDRNORM_BASE_ADDR4_DEFAULT                                      0x00000000
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR4_DEFAULT                                     0x00000000
>+#define mmMMEA0_ADDRNORM_BASE_ADDR5_DEFAULT                                      0x00000000
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR5_DEFAULT                                     0x00000000
>+#define mmMMEA0_ADDRNORM_OFFSET_ADDR5_DEFAULT                                    0x00000000
>+#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRNORMGMI_HOLE_CNTL_DEFAULT                                    0x00000000
>+#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT                             0x00000000
>+#define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT                              0x00000000
>+#define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT                                         0x000003cf
>+#define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT                                         0xfffff000
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT                              0x00000000
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT                              0x00000000
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT                              0x00000000
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT                              0x00000000
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT                              0x00000000
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT                              0x00000000
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT                                 0x00000000
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT                               0x00000000
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT                               0x00000000
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT                               0x00000000
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT                               0x00000000
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT                               0x00000000
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT                               0x00000000
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT                               0x00000000
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC_DEFAULT                                  0x00000000
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT                                 0x00000000
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT                                 0x00000000
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT                                 0x00000000
>+#define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA0_ADDRDEC2_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA0_ADDRDEC2_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT                                 0x00600000
>+#define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT                                  0x00600000
>+#define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA0_IO_GROUP_BURST_DEFAULT                                           0x1f031f03
>+#define mmMMEA0_IO_RD_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA0_IO_WR_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA0_SDP_ARB_DRAM_DEFAULT                                             0x00101e40
>+#define mmMMEA0_SDP_ARB_GMI_DEFAULT                                              0x00101e40
>+#define mmMMEA0_SDP_ARB_FINAL_DEFAULT                                            0x00007fff
>+#define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT                                        0x00000000
>+#define mmMMEA0_SDP_GMI_PRIORITY_DEFAULT                                         0x00000000
>+#define mmMMEA0_SDP_IO_PRIORITY_DEFAULT                                          0x00000000
>+#define mmMMEA0_SDP_CREDITS_DEFAULT                                              0x000101bf
>+#define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA0_SDP_REQ_CNTL_DEFAULT                                             0x0000001f
>+#define mmMMEA0_MISC_DEFAULT                                                     0x0c00a070
>+#define mmMMEA0_LATENCY_SAMPLING_DEFAULT                                         0x00000000
>+#define mmMMEA0_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmMMEA0_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmMMEA0_EDC_CNT_DEFAULT                                                  0x00000000
>+#define mmMMEA0_EDC_CNT2_DEFAULT                                                 0x00000000
>+#define mmMMEA0_DSM_CNTL_DEFAULT                                                 0x00000000
>+#define mmMMEA0_DSM_CNTLA_DEFAULT                                                0x00000000
>+#define mmMMEA0_DSM_CNTLB_DEFAULT                                                0x00000000
>+#define mmMMEA0_DSM_CNTL2_DEFAULT                                                0x00000000
>+#define mmMMEA0_DSM_CNTL2A_DEFAULT                                               0x00000000
>+#define mmMMEA0_DSM_CNTL2B_DEFAULT                                               0x00000000
>+#define mmMMEA0_CGTT_CLK_CTRL_DEFAULT                                            0x00000100
>+#define mmMMEA0_EDC_MODE_DEFAULT                                                 0x00000000
>+#define mmMMEA0_ERR_STATUS_DEFAULT                                               0x00000300
>+#define mmMMEA0_MISC2_DEFAULT                                                    0x00000000
>+#define mmMMEA0_ADDRDEC_SELECT_DEFAULT                                           0x00000000
>+#define mmMMEA0_EDC_CNT3_DEFAULT                                                 0x00000000
>+
>+
>+// addressBlock: mmhub_ea_mmeadec1
>+#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA1_DRAM_RD_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA1_DRAM_WR_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA1_DRAM_RD_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA1_DRAM_WR_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA1_DRAM_RD_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA1_DRAM_WR_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA1_DRAM_PAGE_BURST_DEFAULT                                          0x20002000
>+#define mmMMEA1_DRAM_RD_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA1_DRAM_WR_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA1_DRAM_RD_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA1_DRAM_WR_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA1_DRAM_RD_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA1_DRAM_WR_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA1_DRAM_RD_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA1_DRAM_WR_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA1_GMI_RD_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA1_GMI_RD_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA1_GMI_WR_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA1_GMI_WR_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA1_GMI_RD_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA1_GMI_WR_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA1_GMI_RD_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA1_GMI_WR_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA1_GMI_RD_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA1_GMI_WR_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA1_GMI_PAGE_BURST_DEFAULT                                           0x20002000
>+#define mmMMEA1_GMI_RD_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA1_GMI_WR_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA1_GMI_RD_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA1_GMI_WR_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA1_GMI_RD_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA1_GMI_WR_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA1_GMI_RD_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA1_GMI_WR_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA1_GMI_RD_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA1_GMI_RD_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA1_GMI_RD_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA1_GMI_WR_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA1_GMI_WR_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA1_GMI_WR_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA1_ADDRNORM_BASE_ADDR0_DEFAULT                                      0x00000000
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_DEFAULT                                     0x00000000
>+#define mmMMEA1_ADDRNORM_BASE_ADDR1_DEFAULT                                      0x00000000
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_DEFAULT                                     0x00000000
>+#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_DEFAULT                                    0x00000000
>+#define mmMMEA1_ADDRNORM_BASE_ADDR2_DEFAULT                                      0x00000000
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR2_DEFAULT                                     0x00000000
>+#define mmMMEA1_ADDRNORM_BASE_ADDR3_DEFAULT                                      0x00000000
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR3_DEFAULT                                     0x00000000
>+#define mmMMEA1_ADDRNORM_OFFSET_ADDR3_DEFAULT                                    0x00000000
>+#define mmMMEA1_ADDRNORM_BASE_ADDR4_DEFAULT                                      0x00000000
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR4_DEFAULT                                     0x00000000
>+#define mmMMEA1_ADDRNORM_BASE_ADDR5_DEFAULT                                      0x00000000
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR5_DEFAULT                                     0x00000000
>+#define mmMMEA1_ADDRNORM_OFFSET_ADDR5_DEFAULT                                    0x00000000
>+#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRNORMGMI_HOLE_CNTL_DEFAULT                                    0x00000000
>+#define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT                             0x00000000
>+#define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT                              0x00000000
>+#define mmMMEA1_ADDRDEC_BANK_CFG_DEFAULT                                         0x000003cf
>+#define mmMMEA1_ADDRDEC_MISC_CFG_DEFAULT                                         0xfffff000
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT                              0x00000000
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT                              0x00000000
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT                              0x00000000
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT                              0x00000000
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT                              0x00000000
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT                              0x00000000
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT                                 0x00000000
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT                               0x00000000
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT                               0x00000000
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT                               0x00000000
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT                               0x00000000
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT                               0x00000000
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT                               0x00000000
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT                               0x00000000
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC_DEFAULT                                  0x00000000
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT                                 0x00000000
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT                                 0x00000000
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT                                 0x00000000
>+#define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA1_ADDRDEC2_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA1_ADDRDEC2_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT                                 0x00600000
>+#define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT                                  0x00600000
>+#define mmMMEA1_IO_RD_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA1_IO_RD_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA1_IO_WR_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA1_IO_WR_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA1_IO_RD_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA1_IO_WR_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA1_IO_GROUP_BURST_DEFAULT                                           0x1f031f03
>+#define mmMMEA1_IO_RD_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA1_IO_WR_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA1_IO_RD_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA1_IO_WR_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA1_IO_RD_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA1_IO_WR_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA1_IO_RD_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA1_IO_WR_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA1_IO_RD_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA1_IO_WR_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA1_SDP_ARB_DRAM_DEFAULT                                             0x00101e40
>+#define mmMMEA1_SDP_ARB_GMI_DEFAULT                                              0x00101e40
>+#define mmMMEA1_SDP_ARB_FINAL_DEFAULT                                            0x00007fff
>+#define mmMMEA1_SDP_DRAM_PRIORITY_DEFAULT                                        0x00000000
>+#define mmMMEA1_SDP_GMI_PRIORITY_DEFAULT                                         0x00000000
>+#define mmMMEA1_SDP_IO_PRIORITY_DEFAULT                                          0x00000000
>+#define mmMMEA1_SDP_CREDITS_DEFAULT                                              0x000101bf
>+#define mmMMEA1_SDP_TAG_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA1_SDP_TAG_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA1_SDP_VCC_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA1_SDP_VCC_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA1_SDP_VCD_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA1_SDP_VCD_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA1_SDP_REQ_CNTL_DEFAULT                                             0x0000001f
>+#define mmMMEA1_MISC_DEFAULT                                                     0x0c00a070
>+#define mmMMEA1_LATENCY_SAMPLING_DEFAULT                                         0x00000000
>+#define mmMMEA1_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmMMEA1_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmMMEA1_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA1_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmMMEA1_EDC_CNT_DEFAULT                                                  0x00000000
>+#define mmMMEA1_EDC_CNT2_DEFAULT                                                 0x00000000
>+#define mmMMEA1_DSM_CNTL_DEFAULT                                                 0x00000000
>+#define mmMMEA1_DSM_CNTLA_DEFAULT                                                0x00000000
>+#define mmMMEA1_DSM_CNTLB_DEFAULT                                                0x00000000
>+#define mmMMEA1_DSM_CNTL2_DEFAULT                                                0x00000000
>+#define mmMMEA1_DSM_CNTL2A_DEFAULT                                               0x00000000
>+#define mmMMEA1_DSM_CNTL2B_DEFAULT                                               0x00000000
>+#define mmMMEA1_CGTT_CLK_CTRL_DEFAULT                                            0x00000100
>+#define mmMMEA1_EDC_MODE_DEFAULT                                                 0x00000000
>+#define mmMMEA1_ERR_STATUS_DEFAULT                                               0x00000300
>+#define mmMMEA1_MISC2_DEFAULT                                                    0x00000000
>+#define mmMMEA1_ADDRDEC_SELECT_DEFAULT                                           0x00000000
>+#define mmMMEA1_EDC_CNT3_DEFAULT                                                 0x00000000
>+
>+
>+// addressBlock: mmhub_ea_mmeadec2
>+#define mmMMEA2_DRAM_RD_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA2_DRAM_RD_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA2_DRAM_WR_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA2_DRAM_WR_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA2_DRAM_RD_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA2_DRAM_WR_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA2_DRAM_RD_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA2_DRAM_WR_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA2_DRAM_RD_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA2_DRAM_WR_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA2_DRAM_PAGE_BURST_DEFAULT                                          0x20002000
>+#define mmMMEA2_DRAM_RD_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA2_DRAM_WR_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA2_DRAM_RD_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA2_DRAM_WR_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA2_DRAM_RD_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA2_DRAM_WR_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA2_DRAM_RD_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA2_DRAM_WR_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA2_GMI_RD_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA2_GMI_RD_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA2_GMI_WR_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA2_GMI_WR_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA2_GMI_RD_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA2_GMI_WR_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA2_GMI_RD_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA2_GMI_WR_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA2_GMI_RD_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA2_GMI_WR_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA2_GMI_PAGE_BURST_DEFAULT                                           0x20002000
>+#define mmMMEA2_GMI_RD_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA2_GMI_WR_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA2_GMI_RD_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA2_GMI_WR_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA2_GMI_RD_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA2_GMI_WR_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA2_GMI_RD_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA2_GMI_WR_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA2_GMI_RD_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA2_GMI_RD_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA2_GMI_RD_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA2_GMI_WR_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA2_GMI_WR_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA2_GMI_WR_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA2_ADDRNORM_BASE_ADDR0_DEFAULT                                      0x00000000
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR0_DEFAULT                                     0x00000000
>+#define mmMMEA2_ADDRNORM_BASE_ADDR1_DEFAULT                                      0x00000000
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR1_DEFAULT                                     0x00000000
>+#define mmMMEA2_ADDRNORM_OFFSET_ADDR1_DEFAULT                                    0x00000000
>+#define mmMMEA2_ADDRNORM_BASE_ADDR2_DEFAULT                                      0x00000000
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR2_DEFAULT                                     0x00000000
>+#define mmMMEA2_ADDRNORM_BASE_ADDR3_DEFAULT                                      0x00000000
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR3_DEFAULT                                     0x00000000
>+#define mmMMEA2_ADDRNORM_OFFSET_ADDR3_DEFAULT                                    0x00000000
>+#define mmMMEA2_ADDRNORM_BASE_ADDR4_DEFAULT                                      0x00000000
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR4_DEFAULT                                     0x00000000
>+#define mmMMEA2_ADDRNORM_BASE_ADDR5_DEFAULT                                      0x00000000
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR5_DEFAULT                                     0x00000000
>+#define mmMMEA2_ADDRNORM_OFFSET_ADDR5_DEFAULT                                    0x00000000
>+#define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRNORMGMI_HOLE_CNTL_DEFAULT                                    0x00000000
>+#define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT                             0x00000000
>+#define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT                              0x00000000
>+#define mmMMEA2_ADDRDEC_BANK_CFG_DEFAULT                                         0x000003cf
>+#define mmMMEA2_ADDRDEC_MISC_CFG_DEFAULT                                         0xfffff000
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT                              0x00000000
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT                              0x00000000
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT                              0x00000000
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT                              0x00000000
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT                              0x00000000
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT                              0x00000000
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT                                 0x00000000
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT                               0x00000000
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT                               0x00000000
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT                               0x00000000
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT                               0x00000000
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT                               0x00000000
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT                               0x00000000
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT                               0x00000000
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC_DEFAULT                                  0x00000000
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT                                 0x00000000
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT                                 0x00000000
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT                                 0x00000000
>+#define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA2_ADDRDEC0_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA2_ADDRDEC0_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA2_ADDRDEC1_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA2_ADDRDEC1_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA2_ADDRDEC2_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA2_ADDRDEC2_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT                                 0x00600000
>+#define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT                                  0x00600000
>+#define mmMMEA2_IO_RD_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA2_IO_RD_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA2_IO_WR_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA2_IO_WR_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA2_IO_RD_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA2_IO_WR_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA2_IO_GROUP_BURST_DEFAULT                                           0x1f031f03
>+#define mmMMEA2_IO_RD_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA2_IO_WR_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA2_IO_RD_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA2_IO_WR_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA2_IO_RD_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA2_IO_WR_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA2_IO_RD_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA2_IO_WR_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA2_IO_RD_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA2_IO_WR_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA2_IO_RD_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA2_IO_RD_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA2_IO_RD_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA2_IO_WR_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA2_IO_WR_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA2_IO_WR_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA2_SDP_ARB_DRAM_DEFAULT                                             0x00101e40
>+#define mmMMEA2_SDP_ARB_GMI_DEFAULT                                              0x00101e40
>+#define mmMMEA2_SDP_ARB_FINAL_DEFAULT                                            0x00007fff
>+#define mmMMEA2_SDP_DRAM_PRIORITY_DEFAULT                                        0x00000000
>+#define mmMMEA2_SDP_GMI_PRIORITY_DEFAULT                                         0x00000000
>+#define mmMMEA2_SDP_IO_PRIORITY_DEFAULT                                          0x00000000
>+#define mmMMEA2_SDP_CREDITS_DEFAULT                                              0x000101bf
>+#define mmMMEA2_SDP_TAG_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA2_SDP_TAG_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA2_SDP_VCC_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA2_SDP_VCC_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA2_SDP_VCD_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA2_SDP_VCD_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA2_SDP_REQ_CNTL_DEFAULT                                             0x0000001f
>+#define mmMMEA2_MISC_DEFAULT                                                     0x0c00a070
>+#define mmMMEA2_LATENCY_SAMPLING_DEFAULT                                         0x00000000
>+#define mmMMEA2_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmMMEA2_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmMMEA2_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA2_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA2_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmMMEA2_EDC_CNT_DEFAULT                                                  0x00000000
>+#define mmMMEA2_EDC_CNT2_DEFAULT                                                 0x00000000
>+#define mmMMEA2_DSM_CNTL_DEFAULT                                                 0x00000000
>+#define mmMMEA2_DSM_CNTLA_DEFAULT                                                0x00000000
>+#define mmMMEA2_DSM_CNTLB_DEFAULT                                                0x00000000
>+#define mmMMEA2_DSM_CNTL2_DEFAULT                                                0x00000000
>+#define mmMMEA2_DSM_CNTL2A_DEFAULT                                               0x00000000
>+#define mmMMEA2_DSM_CNTL2B_DEFAULT                                               0x00000000
>+#define mmMMEA2_CGTT_CLK_CTRL_DEFAULT                                            0x00000100
>+#define mmMMEA2_EDC_MODE_DEFAULT                                                 0x00000000
>+#define mmMMEA2_ERR_STATUS_DEFAULT                                               0x00000300
>+#define mmMMEA2_MISC2_DEFAULT                                                    0x00000000
>+#define mmMMEA2_ADDRDEC_SELECT_DEFAULT                                           0x00000000
>+#define mmMMEA2_EDC_CNT3_DEFAULT                                                 0x00000000
>+
>+
>+// addressBlock: mmhub_ea_mmeadec3
>+#define mmMMEA3_DRAM_RD_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA3_DRAM_RD_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA3_DRAM_WR_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA3_DRAM_WR_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA3_DRAM_RD_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA3_DRAM_WR_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA3_DRAM_RD_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA3_DRAM_WR_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA3_DRAM_RD_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA3_DRAM_WR_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA3_DRAM_PAGE_BURST_DEFAULT                                          0x20002000
>+#define mmMMEA3_DRAM_RD_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA3_DRAM_WR_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA3_DRAM_RD_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA3_DRAM_WR_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA3_DRAM_RD_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA3_DRAM_WR_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA3_DRAM_RD_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA3_DRAM_WR_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA3_GMI_RD_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA3_GMI_RD_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA3_GMI_WR_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA3_GMI_WR_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA3_GMI_RD_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA3_GMI_WR_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA3_GMI_RD_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA3_GMI_WR_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA3_GMI_RD_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA3_GMI_WR_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA3_GMI_PAGE_BURST_DEFAULT                                           0x20002000
>+#define mmMMEA3_GMI_RD_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA3_GMI_WR_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA3_GMI_RD_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA3_GMI_WR_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA3_GMI_RD_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA3_GMI_WR_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA3_GMI_RD_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA3_GMI_WR_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA3_GMI_RD_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA3_GMI_RD_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA3_GMI_RD_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA3_GMI_WR_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA3_GMI_WR_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA3_GMI_WR_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA3_ADDRNORM_BASE_ADDR0_DEFAULT                                      0x00000000
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR0_DEFAULT                                     0x00000000
>+#define mmMMEA3_ADDRNORM_BASE_ADDR1_DEFAULT                                      0x00000000
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR1_DEFAULT                                     0x00000000
>+#define mmMMEA3_ADDRNORM_OFFSET_ADDR1_DEFAULT                                    0x00000000
>+#define mmMMEA3_ADDRNORM_BASE_ADDR2_DEFAULT                                      0x00000000
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR2_DEFAULT                                     0x00000000
>+#define mmMMEA3_ADDRNORM_BASE_ADDR3_DEFAULT                                      0x00000000
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR3_DEFAULT                                     0x00000000
>+#define mmMMEA3_ADDRNORM_OFFSET_ADDR3_DEFAULT                                    0x00000000
>+#define mmMMEA3_ADDRNORM_BASE_ADDR4_DEFAULT                                      0x00000000
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR4_DEFAULT                                     0x00000000
>+#define mmMMEA3_ADDRNORM_BASE_ADDR5_DEFAULT                                      0x00000000
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR5_DEFAULT                                     0x00000000
>+#define mmMMEA3_ADDRNORM_OFFSET_ADDR5_DEFAULT                                    0x00000000
>+#define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRNORMGMI_HOLE_CNTL_DEFAULT                                    0x00000000
>+#define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT                             0x00000000
>+#define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT                              0x00000000
>+#define mmMMEA3_ADDRDEC_BANK_CFG_DEFAULT                                         0x000003cf
>+#define mmMMEA3_ADDRDEC_MISC_CFG_DEFAULT                                         0xfffff000
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT                              0x00000000
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT                              0x00000000
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT                              0x00000000
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT                              0x00000000
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT                              0x00000000
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT                              0x00000000
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT                                 0x00000000
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT                               0x00000000
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT                               0x00000000
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT                               0x00000000
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT                               0x00000000
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT                               0x00000000
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT                               0x00000000
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT                               0x00000000
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC_DEFAULT                                  0x00000000
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT                                 0x00000000
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT                                 0x00000000
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT                                 0x00000000
>+#define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA3_ADDRDEC0_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA3_ADDRDEC0_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA3_ADDRDEC1_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA3_ADDRDEC1_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA3_ADDRDEC2_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA3_ADDRDEC2_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT                                 0x00600000
>+#define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT                                  0x00600000
>+#define mmMMEA3_IO_RD_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA3_IO_RD_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA3_IO_WR_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA3_IO_WR_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA3_IO_RD_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA3_IO_WR_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA3_IO_GROUP_BURST_DEFAULT                                           0x1f031f03
>+#define mmMMEA3_IO_RD_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA3_IO_WR_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA3_IO_RD_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA3_IO_WR_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA3_IO_RD_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA3_IO_WR_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA3_IO_RD_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA3_IO_WR_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA3_IO_RD_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA3_IO_WR_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA3_IO_RD_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA3_IO_RD_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA3_IO_RD_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA3_IO_WR_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA3_IO_WR_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA3_IO_WR_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA3_SDP_ARB_DRAM_DEFAULT                                             0x00101e40
>+#define mmMMEA3_SDP_ARB_GMI_DEFAULT                                              0x00101e40
>+#define mmMMEA3_SDP_ARB_FINAL_DEFAULT                                            0x00007fff
>+#define mmMMEA3_SDP_DRAM_PRIORITY_DEFAULT                                        0x00000000
>+#define mmMMEA3_SDP_GMI_PRIORITY_DEFAULT                                         0x00000000
>+#define mmMMEA3_SDP_IO_PRIORITY_DEFAULT                                          0x00000000
>+#define mmMMEA3_SDP_CREDITS_DEFAULT                                              0x000101bf
>+#define mmMMEA3_SDP_TAG_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA3_SDP_TAG_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA3_SDP_VCC_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA3_SDP_VCC_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA3_SDP_VCD_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA3_SDP_VCD_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA3_SDP_REQ_CNTL_DEFAULT                                             0x0000001f
>+#define mmMMEA3_MISC_DEFAULT                                                     0x0c00a070
>+#define mmMMEA3_LATENCY_SAMPLING_DEFAULT                                         0x00000000
>+#define mmMMEA3_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmMMEA3_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmMMEA3_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA3_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA3_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmMMEA3_EDC_CNT_DEFAULT                                                  0x00000000
>+#define mmMMEA3_EDC_CNT2_DEFAULT                                                 0x00000000
>+#define mmMMEA3_DSM_CNTL_DEFAULT                                                 0x00000000
>+#define mmMMEA3_DSM_CNTLA_DEFAULT                                                0x00000000
>+#define mmMMEA3_DSM_CNTLB_DEFAULT                                                0x00000000
>+#define mmMMEA3_DSM_CNTL2_DEFAULT                                                0x00000000
>+#define mmMMEA3_DSM_CNTL2A_DEFAULT                                               0x00000000
>+#define mmMMEA3_DSM_CNTL2B_DEFAULT                                               0x00000000
>+#define mmMMEA3_CGTT_CLK_CTRL_DEFAULT                                            0x00000100
>+#define mmMMEA3_EDC_MODE_DEFAULT                                                 0x00000000
>+#define mmMMEA3_ERR_STATUS_DEFAULT                                               0x00000300
>+#define mmMMEA3_MISC2_DEFAULT                                                    0x00000000
>+#define mmMMEA3_ADDRDEC_SELECT_DEFAULT                                           0x00000000
>+#define mmMMEA3_EDC_CNT3_DEFAULT                                                 0x00000000
>+
>+
>+// addressBlock: mmhub_ea_mmeadec4
>+#define mmMMEA4_DRAM_RD_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA4_DRAM_RD_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA4_DRAM_WR_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA4_DRAM_WR_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA4_DRAM_RD_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA4_DRAM_WR_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA4_DRAM_RD_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA4_DRAM_WR_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA4_DRAM_RD_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA4_DRAM_WR_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA4_DRAM_PAGE_BURST_DEFAULT                                          0x20002000
>+#define mmMMEA4_DRAM_RD_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA4_DRAM_WR_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA4_DRAM_RD_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA4_DRAM_WR_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA4_DRAM_RD_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA4_DRAM_WR_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA4_DRAM_RD_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA4_DRAM_WR_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA4_GMI_RD_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA4_GMI_RD_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA4_GMI_WR_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA4_GMI_WR_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA4_GMI_RD_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA4_GMI_WR_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA4_GMI_RD_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA4_GMI_WR_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA4_GMI_RD_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA4_GMI_WR_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA4_GMI_PAGE_BURST_DEFAULT                                           0x20002000
>+#define mmMMEA4_GMI_RD_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA4_GMI_WR_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA4_GMI_RD_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA4_GMI_WR_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA4_GMI_RD_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA4_GMI_WR_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA4_GMI_RD_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA4_GMI_WR_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA4_GMI_RD_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA4_GMI_RD_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA4_GMI_RD_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA4_GMI_WR_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA4_GMI_WR_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA4_GMI_WR_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA4_ADDRNORM_BASE_ADDR0_DEFAULT                                      0x00000000
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR0_DEFAULT                                     0x00000000
>+#define mmMMEA4_ADDRNORM_BASE_ADDR1_DEFAULT                                      0x00000000
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR1_DEFAULT                                     0x00000000
>+#define mmMMEA4_ADDRNORM_OFFSET_ADDR1_DEFAULT                                    0x00000000
>+#define mmMMEA4_ADDRNORM_BASE_ADDR2_DEFAULT                                      0x00000000
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR2_DEFAULT                                     0x00000000
>+#define mmMMEA4_ADDRNORM_BASE_ADDR3_DEFAULT                                      0x00000000
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR3_DEFAULT                                     0x00000000
>+#define mmMMEA4_ADDRNORM_OFFSET_ADDR3_DEFAULT                                    0x00000000
>+#define mmMMEA4_ADDRNORM_BASE_ADDR4_DEFAULT                                      0x00000000
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR4_DEFAULT                                     0x00000000
>+#define mmMMEA4_ADDRNORM_BASE_ADDR5_DEFAULT                                      0x00000000
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR5_DEFAULT                                     0x00000000
>+#define mmMMEA4_ADDRNORM_OFFSET_ADDR5_DEFAULT                                    0x00000000
>+#define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRNORMGMI_HOLE_CNTL_DEFAULT                                    0x00000000
>+#define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT                             0x00000000
>+#define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT                              0x00000000
>+#define mmMMEA4_ADDRDEC_BANK_CFG_DEFAULT                                         0x000003cf
>+#define mmMMEA4_ADDRDEC_MISC_CFG_DEFAULT                                         0xfffff000
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT                              0x00000000
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT                              0x00000000
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT                              0x00000000
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT                              0x00000000
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT                              0x00000000
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT                              0x00000000
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT                                 0x00000000
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT                               0x00000000
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT                               0x00000000
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT                               0x00000000
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT                               0x00000000
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT                               0x00000000
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT                               0x00000000
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT                               0x00000000
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC_DEFAULT                                  0x00000000
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT                                 0x00000000
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT                                 0x00000000
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT                                 0x00000000
>+#define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA4_ADDRDEC0_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA4_ADDRDEC0_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA4_ADDRDEC1_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA4_ADDRDEC1_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA4_ADDRDEC2_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA4_ADDRDEC2_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT                                 0x00600000
>+#define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT                                  0x00600000
>+#define mmMMEA4_IO_RD_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA4_IO_RD_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA4_IO_WR_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA4_IO_WR_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA4_IO_RD_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA4_IO_WR_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA4_IO_GROUP_BURST_DEFAULT                                           0x1f031f03
>+#define mmMMEA4_IO_RD_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA4_IO_WR_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA4_IO_RD_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA4_IO_WR_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA4_IO_RD_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA4_IO_WR_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA4_IO_RD_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA4_IO_WR_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA4_IO_RD_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA4_IO_WR_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA4_IO_RD_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA4_IO_RD_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA4_IO_RD_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA4_IO_WR_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA4_IO_WR_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA4_IO_WR_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA4_SDP_ARB_DRAM_DEFAULT                                             0x00101e40
>+#define mmMMEA4_SDP_ARB_GMI_DEFAULT                                              0x00101e40
>+#define mmMMEA4_SDP_ARB_FINAL_DEFAULT                                            0x00007fff
>+#define mmMMEA4_SDP_DRAM_PRIORITY_DEFAULT                                        0x00000000
>+#define mmMMEA4_SDP_GMI_PRIORITY_DEFAULT                                         0x00000000
>+#define mmMMEA4_SDP_IO_PRIORITY_DEFAULT                                          0x00000000
>+#define mmMMEA4_SDP_CREDITS_DEFAULT                                              0x000101bf
>+#define mmMMEA4_SDP_TAG_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA4_SDP_TAG_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA4_SDP_VCC_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA4_SDP_VCC_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA4_SDP_VCD_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA4_SDP_VCD_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA4_SDP_REQ_CNTL_DEFAULT                                             0x0000001f
>+#define mmMMEA4_MISC_DEFAULT                                                     0x0c00a070
>+#define mmMMEA4_LATENCY_SAMPLING_DEFAULT                                         0x00000000
>+#define mmMMEA4_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmMMEA4_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmMMEA4_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA4_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA4_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmMMEA4_EDC_CNT_DEFAULT                                                  0x00000000
>+#define mmMMEA4_EDC_CNT2_DEFAULT                                                 0x00000000
>+#define mmMMEA4_DSM_CNTL_DEFAULT                                                 0x00000000
>+#define mmMMEA4_DSM_CNTLA_DEFAULT                                                0x00000000
>+#define mmMMEA4_DSM_CNTLB_DEFAULT                                                0x00000000
>+#define mmMMEA4_DSM_CNTL2_DEFAULT                                                0x00000000
>+#define mmMMEA4_DSM_CNTL2A_DEFAULT                                               0x00000000
>+#define mmMMEA4_DSM_CNTL2B_DEFAULT                                               0x00000000
>+#define mmMMEA4_CGTT_CLK_CTRL_DEFAULT                                            0x00000100
>+#define mmMMEA4_EDC_MODE_DEFAULT                                                 0x00000000
>+#define mmMMEA4_ERR_STATUS_DEFAULT                                               0x00000300
>+#define mmMMEA4_MISC2_DEFAULT                                                    0x00000000
>+#define mmMMEA4_ADDRDEC_SELECT_DEFAULT                                           0x00000000
>+#define mmMMEA4_EDC_CNT3_DEFAULT                                                 0x00000000
>+
>+
>+// addressBlock: mmhub_pctldec0
>+#define mmPCTL0_CTRL_DEFAULT                                                     0x00011040
>+#define mmPCTL0_MMHUB_DEEPSLEEP_IB_DEFAULT                                       0x00000000
>+#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT                                 0x00000000
>+#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_DEFAULT                              0x00000000
>+#define mmPCTL0_PG_IGNORE_DEEPSLEEP_DEFAULT                                      0x00000000
>+#define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB_DEFAULT                                   0x00000000
>+#define mmPCTL0_SLICE0_CFG_DAGB_BUSY_DEFAULT                                     0x00000000
>+#define mmPCTL0_SLICE0_CFG_DS_ALLOW_DEFAULT                                      0x00000000
>+#define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB_DEFAULT                                   0x00000000
>+#define mmPCTL0_SLICE1_CFG_DAGB_BUSY_DEFAULT                                     0x00000000
>+#define mmPCTL0_SLICE1_CFG_DS_ALLOW_DEFAULT                                      0x00000000
>+#define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB_DEFAULT                                   0x00000000
>+#define mmPCTL0_SLICE2_CFG_DAGB_BUSY_DEFAULT                                     0x00000000
>+#define mmPCTL0_SLICE2_CFG_DS_ALLOW_DEFAULT                                      0x00000000
>+#define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB_DEFAULT                                   0x00000000
>+#define mmPCTL0_SLICE3_CFG_DAGB_BUSY_DEFAULT                                     0x00000000
>+#define mmPCTL0_SLICE3_CFG_DS_ALLOW_DEFAULT                                      0x00000000
>+#define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB_DEFAULT                                   0x00000000
>+#define mmPCTL0_SLICE4_CFG_DAGB_BUSY_DEFAULT                                     0x00000000
>+#define mmPCTL0_SLICE4_CFG_DS_ALLOW_DEFAULT                                      0x00000000
>+#define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB_DEFAULT                                   0x00000000
>+#define mmPCTL0_UTCL2_MISC_DEFAULT                                               0x00011000
>+#define mmPCTL0_SLICE0_MISC_DEFAULT                                              0x00000800
>+#define mmPCTL0_SLICE1_MISC_DEFAULT                                              0x00000800
>+#define mmPCTL0_SLICE2_MISC_DEFAULT                                              0x00000800
>+#define mmPCTL0_SLICE3_MISC_DEFAULT                                              0x00000800
>+#define mmPCTL0_SLICE4_MISC_DEFAULT                                              0x00000800
>+#define mmPCTL0_UTCL2_RENG_EXECUTE_DEFAULT                                       0x00000000
>+#define mmPCTL0_SLICE0_RENG_EXECUTE_DEFAULT                                      0x00000000
>+#define mmPCTL0_SLICE1_RENG_EXECUTE_DEFAULT                                      0x00000000
>+#define mmPCTL0_SLICE2_RENG_EXECUTE_DEFAULT                                      0x00000000
>+#define mmPCTL0_SLICE3_RENG_EXECUTE_DEFAULT                                      0x00000000
>+#define mmPCTL0_SLICE4_RENG_EXECUTE_DEFAULT                                      0x00000000
>+#define mmPCTL0_UTCL2_RENG_RAM_INDEX_DEFAULT                                     0x00000000
>+#define mmPCTL0_UTCL2_RENG_RAM_DATA_DEFAULT                                      0x00000000
>+#define mmPCTL0_SLICE0_RENG_RAM_INDEX_DEFAULT                                    0x00000000
>+#define mmPCTL0_SLICE0_RENG_RAM_DATA_DEFAULT                                     0x00000000
>+#define mmPCTL0_SLICE1_RENG_RAM_INDEX_DEFAULT                                    0x00000000
>+#define mmPCTL0_SLICE1_RENG_RAM_DATA_DEFAULT                                     0x00000000
>+#define mmPCTL0_SLICE2_RENG_RAM_INDEX_DEFAULT                                    0x00000000
>+#define mmPCTL0_SLICE2_RENG_RAM_DATA_DEFAULT                                     0x00000000
>+#define mmPCTL0_SLICE3_RENG_RAM_INDEX_DEFAULT                                    0x00000000
>+#define mmPCTL0_SLICE3_RENG_RAM_DATA_DEFAULT                                     0x00000000
>+#define mmPCTL0_SLICE4_RENG_RAM_INDEX_DEFAULT                                    0x00000000
>+#define mmPCTL0_SLICE4_RENG_RAM_DATA_DEFAULT                                     0x00000000
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                        0x00000000
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                        0x00000000
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                        0x00000000
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                        0x00000000
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                        0x00000000
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                     0xffffffff
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                     0xffffffff
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                    0xffffffff
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                    0xffffffff
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                    0xffffffff
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                    0xffffffff
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                    0xffffffff
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                    0xffffffff
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                    0xffffffff
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                    0xffffffff
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                       0x00000000
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                    0xffffffff
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                    0xffffffff
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1dec
>+#define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS_DEFAULT                                 0x00000000
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1pldec
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT                           0x00000000
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT                           0x00000000
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT                           0x00000000
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT                           0x00000000
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT                      0x04000000
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1prdec
>+#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT                             0x00000000
>+#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT                             0x00000000
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2dec
>+#define mmATCL2_0_ATC_L2_CNTL_DEFAULT                                            0x0001c0c9
>+#define mmATCL2_0_ATC_L2_CNTL2_DEFAULT                                           0x00600100
>+#define mmATCL2_0_ATC_L2_CACHE_DATA0_DEFAULT                                     0x00000000
>+#define mmATCL2_0_ATC_L2_CACHE_DATA1_DEFAULT                                     0x00000000
>+#define mmATCL2_0_ATC_L2_CACHE_DATA2_DEFAULT                                     0x00000000
>+#define mmATCL2_0_ATC_L2_CNTL3_DEFAULT                                           0x000001f8
>+#define mmATCL2_0_ATC_L2_STATUS_DEFAULT                                          0x00000000
>+#define mmATCL2_0_ATC_L2_STATUS2_DEFAULT                                         0x00000000
>+#define mmATCL2_0_ATC_L2_STATUS3_DEFAULT                                         0x00000000
>+#define mmATCL2_0_ATC_L2_MISC_CG_DEFAULT                                         0x00000200
>+#define mmATCL2_0_ATC_L2_MEM_POWER_LS_DEFAULT                                    0x00000208
>+#define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL_DEFAULT                                   0x00000080
>+#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX_DEFAULT                              0x00000000
>+#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX_DEFAULT                              0x00000000
>+#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL_DEFAULT                               0x00000000
>+#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL_DEFAULT                               0x00000000
>+#define mmATCL2_0_ATC_L2_CNTL4_DEFAULT                                           0x00000000
>+#define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES_DEFAULT                             0x00000005
>+
>+
>+// addressBlock: mmhub_utcl2_vml2pfdec
>+#define mmVML2PF0_VM_L2_CNTL_DEFAULT                                             0x00080602
>+#define mmVML2PF0_VM_L2_CNTL2_DEFAULT                                            0x00000000
>+#define mmVML2PF0_VM_L2_CNTL3_DEFAULT                                            0x80100007
>+#define mmVML2PF0_VM_L2_STATUS_DEFAULT                                           0x00000000
>+#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL_DEFAULT                               0x00000090
>+#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT                          0x00000000
>+#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT                          0x00000000
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL_DEFAULT                            0x3ffffffc
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2_DEFAULT                           0x000a0000
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT                        0xffffffff
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT                        0xffffffff
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS_DEFAULT                          0x00000000
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT                       0x00000000
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT                       0x00000000
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT               0x00000000
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT               0x00000000
>+#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT         0x00000000
>+#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT         0x00000000
>+#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT        0x00000000
>+#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT        0x00000000
>+#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT            0x00000000
>+#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT            0x00000000
>+#define mmVML2PF0_VM_L2_CNTL4_DEFAULT                                            0x000000c1
>+#define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES_DEFAULT                              0x00000000
>+#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID_DEFAULT                         0x00000000
>+#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT                        0x00000000
>+#define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL_DEFAULT                                0x00000000
>+#define mmVML2PF0_VM_L2_CGTT_CLK_CTRL_DEFAULT                                    0x00000080
>+
>+
>+// addressBlock: mmhub_utcl2_vml2vcdec
>+#define mmVML2VC0_VM_CONTEXT0_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT1_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT2_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT3_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT4_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT5_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT6_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT7_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT8_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT9_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT10_CNTL_DEFAULT                                      0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT11_CNTL_DEFAULT                                      0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT12_CNTL_DEFAULT                                      0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT13_CNTL_DEFAULT                                      0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT14_CNTL_DEFAULT                                      0x007ffe80
>+#define mmVML2VC0_VM_CONTEXT15_CNTL_DEFAULT                                      0x007ffe80
>+#define mmVML2VC0_VM_CONTEXTS_DISABLE_DEFAULT                                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedpfdec
>+#define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE_DEFAULT                                  0x00000000
>+#define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT_DEFAULT                                 0x00000000
>+#define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL_DEFAULT                                  0x00000000
>+#define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB_DEFAULT                                   0x00000008
>+#define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT                         0x00000000
>+#define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT                        0x00000000
>+#define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT                        0x00000000
>+#define mmVMSHAREDPF0_MC_VM_FB_OFFSET_DEFAULT                                    0x00000000
>+#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT             0x00000000
>+#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT             0x00000000
>+#define mmVMSHAREDPF0_MC_VM_STEERING_DEFAULT                                     0x00000001
>+#define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ_DEFAULT                           0x00000000
>+#define mmVMSHAREDPF0_MC_MEM_POWER_LS_DEFAULT                                    0x00000208
>+#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT                 0x00000000
>+#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT                   0x00000000
>+#define mmVMSHAREDPF0_MC_VM_APT_CNTL_DEFAULT                                     0x00000000
>+#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT                      0x00000000
>+#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT                        0x000fffff
>+#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT                  0x00000000
>+#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL_DEFAULT                                0x00000000
>+#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE_DEFAULT                                0x00000000
>+#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL_DEFAULT                          0x00000000
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedvcdec
>+#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE_DEFAULT                             0x00000000
>+#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP_DEFAULT                              0x00000000
>+#define mmVMSHAREDVC0_MC_VM_AGP_TOP_DEFAULT                                      0x00000000
>+#define mmVMSHAREDVC0_MC_VM_AGP_BOT_DEFAULT                                      0x00000000
>+#define mmVMSHAREDVC0_MC_VM_AGP_BASE_DEFAULT                                     0x00000000
>+#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT                     0x00000000
>+#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT                    0x00000000
>+#define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL_DEFAULT                               0x00002501
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedhvdec
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1_DEFAULT                              0x00000100
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_DEFAULT                                   0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10_DEFAULT                             0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11_DEFAULT                             0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12_DEFAULT                             0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13_DEFAULT                             0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14_DEFAULT                             0x00000000
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15_DEFAULT                             0x00000000
>+#define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL_DEFAULT                                0x00000080
>+#define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID_DEFAULT                            0x00000000
>+#define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE_DEFAULT                           0x00000000
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2pfcntrdec
>+#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO_DEFAULT                             0x00000000
>+#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI_DEFAULT                             0x00000000
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2pfcntldec
>+#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG_DEFAULT                           0x00000000
>+#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG_DEFAULT                           0x00000000
>+#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT                      0x04000000
>+
>+
>+// addressBlock: mmhub_utcl2_vml2pldec
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT                         0x04000000
>+
>+
>+// addressBlock: mmhub_utcl2_vml2prdec
>+#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO_DEFAULT                                0x00000000
>+#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI_DEFAULT                                0x00000000
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec5
>+#define mmDAGB5_RDCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_RDCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_RDCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_RDCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_RDCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_RDCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_RDCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_RDCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_RDCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_RDCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_RDCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB5_RDCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB5_RDCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB5_RDCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB5_RDCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB5_RDCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB5_RD_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB5_RD_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB5_RD_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB5_RD_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB5_RD_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_RD_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_RD_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_RD_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_RD_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_RD_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_RD_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_RD_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_RD_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB5_RD_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB5_RDCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB5_RDCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB5_RDCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB5_RDCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB5_RDCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB5_RDCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB5_WRCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_WRCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_WRCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_WRCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_WRCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_WRCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_WRCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_WRCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_WRCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_WRCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB5_WRCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB5_WRCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB5_WRCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB5_WRCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB5_WRCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB5_WRCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB5_WR_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB5_WR_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB5_WR_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB5_WR_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB5_WR_DATA_DAGB_DEFAULT                                             0x00000001
>+#define mmDAGB5_WR_DATA_DAGB_MAX_BURST0_DEFAULT                                  0x11111111
>+#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT                                 0x00000000
>+#define mmDAGB5_WR_DATA_DAGB_MAX_BURST1_DEFAULT                                  0x11111111
>+#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT                                 0x00000000
>+#define mmDAGB5_WR_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_WR_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_WR_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_WR_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_WR_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_WR_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_WR_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_WR_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB5_WR_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB5_WR_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB5_WR_DATA_CREDIT_DEFAULT                                           0x60606070
>+#define mmDAGB5_WR_MISC_CREDIT_DEFAULT                                           0x0078dc88
>+#define mmDAGB5_WRCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB5_WRCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB5_WRCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB5_WRCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB5_WRCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB5_WRCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB5_WRCLI_DBUS_ASK_PENDING_DEFAULT                                   0x00000000
>+#define mmDAGB5_WRCLI_DBUS_GO_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB5_DAGB_DLY_DEFAULT                                                 0x00000000
>+#define mmDAGB5_CNTL_MISC_DEFAULT                                                0xcf7c1ffa
>+#define mmDAGB5_CNTL_MISC2_DEFAULT                                               0x003c0000
>+#define mmDAGB5_FIFO_EMPTY_DEFAULT                                               0x00ffffff
>+#define mmDAGB5_FIFO_FULL_DEFAULT                                                0x00000000
>+#define mmDAGB5_WR_CREDITS_FULL_DEFAULT                                          0x1fffffff
>+#define mmDAGB5_RD_CREDITS_FULL_DEFAULT                                          0x0003ffff
>+#define mmDAGB5_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmDAGB5_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmDAGB5_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB5_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB5_PERFCOUNTER2_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB5_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmDAGB5_RESERVE0_DEFAULT                                                 0xffffffff
>+#define mmDAGB5_RESERVE1_DEFAULT                                                 0xffffffff
>+#define mmDAGB5_RESERVE2_DEFAULT                                                 0xffffffff
>+#define mmDAGB5_RESERVE3_DEFAULT                                                 0xffffffff
>+#define mmDAGB5_RESERVE4_DEFAULT                                                 0xffffffff
>+#define mmDAGB5_RESERVE5_DEFAULT                                                 0xffffffff
>+#define mmDAGB5_RESERVE6_DEFAULT                                                 0xffffffff
>+#define mmDAGB5_RESERVE7_DEFAULT                                                 0xffffffff
>+#define mmDAGB5_RESERVE8_DEFAULT                                                 0xffffffff
>+#define mmDAGB5_RESERVE9_DEFAULT                                                 0xffffffff
>+#define mmDAGB5_RESERVE10_DEFAULT                                                0xffffffff
>+#define mmDAGB5_RESERVE11_DEFAULT                                                0xffffffff
>+#define mmDAGB5_RESERVE12_DEFAULT                                                0xffffffff
>+#define mmDAGB5_RESERVE13_DEFAULT                                                0xffffffff
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec6
>+#define mmDAGB6_RDCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_RDCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_RDCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_RDCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_RDCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_RDCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_RDCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_RDCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_RDCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_RDCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_RDCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB6_RDCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB6_RDCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB6_RDCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB6_RDCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB6_RDCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB6_RD_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB6_RD_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB6_RD_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB6_RD_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB6_RD_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_RD_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_RD_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_RD_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_RD_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_RD_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_RD_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_RD_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_RD_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB6_RD_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB6_RDCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB6_RDCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB6_RDCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB6_RDCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB6_RDCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB6_RDCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB6_WRCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_WRCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_WRCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_WRCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_WRCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_WRCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_WRCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_WRCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_WRCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_WRCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB6_WRCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB6_WRCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB6_WRCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB6_WRCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB6_WRCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB6_WRCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB6_WR_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB6_WR_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB6_WR_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB6_WR_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB6_WR_DATA_DAGB_DEFAULT                                             0x00000001
>+#define mmDAGB6_WR_DATA_DAGB_MAX_BURST0_DEFAULT                                  0x11111111
>+#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT                                 0x00000000
>+#define mmDAGB6_WR_DATA_DAGB_MAX_BURST1_DEFAULT                                  0x11111111
>+#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT                                 0x00000000
>+#define mmDAGB6_WR_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_WR_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_WR_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_WR_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_WR_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_WR_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_WR_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_WR_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB6_WR_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB6_WR_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB6_WR_DATA_CREDIT_DEFAULT                                           0x60606070
>+#define mmDAGB6_WR_MISC_CREDIT_DEFAULT                                           0x0078dc88
>+#define mmDAGB6_WRCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB6_WRCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB6_WRCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB6_WRCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB6_WRCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB6_WRCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB6_WRCLI_DBUS_ASK_PENDING_DEFAULT                                   0x00000000
>+#define mmDAGB6_WRCLI_DBUS_GO_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB6_DAGB_DLY_DEFAULT                                                 0x00000000
>+#define mmDAGB6_CNTL_MISC_DEFAULT                                                0xcf7c1ffa
>+#define mmDAGB6_CNTL_MISC2_DEFAULT                                               0x003c0000
>+#define mmDAGB6_FIFO_EMPTY_DEFAULT                                               0x00ffffff
>+#define mmDAGB6_FIFO_FULL_DEFAULT                                                0x00000000
>+#define mmDAGB6_WR_CREDITS_FULL_DEFAULT                                          0x1fffffff
>+#define mmDAGB6_RD_CREDITS_FULL_DEFAULT                                          0x0003ffff
>+#define mmDAGB6_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmDAGB6_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmDAGB6_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB6_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB6_PERFCOUNTER2_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB6_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmDAGB6_RESERVE0_DEFAULT                                                 0xffffffff
>+#define mmDAGB6_RESERVE1_DEFAULT                                                 0xffffffff
>+#define mmDAGB6_RESERVE2_DEFAULT                                                 0xffffffff
>+#define mmDAGB6_RESERVE3_DEFAULT                                                 0xffffffff
>+#define mmDAGB6_RESERVE4_DEFAULT                                                 0xffffffff
>+#define mmDAGB6_RESERVE5_DEFAULT                                                 0xffffffff
>+#define mmDAGB6_RESERVE6_DEFAULT                                                 0xffffffff
>+#define mmDAGB6_RESERVE7_DEFAULT                                                 0xffffffff
>+#define mmDAGB6_RESERVE8_DEFAULT                                                 0xffffffff
>+#define mmDAGB6_RESERVE9_DEFAULT                                                 0xffffffff
>+#define mmDAGB6_RESERVE10_DEFAULT                                                0xffffffff
>+#define mmDAGB6_RESERVE11_DEFAULT                                                0xffffffff
>+#define mmDAGB6_RESERVE12_DEFAULT                                                0xffffffff
>+#define mmDAGB6_RESERVE13_DEFAULT                                                0xffffffff
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec7
>+#define mmDAGB7_RDCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_RDCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_RDCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_RDCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_RDCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_RDCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_RDCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_RDCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_RDCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_RDCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_RDCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB7_RDCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB7_RDCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB7_RDCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB7_RDCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB7_RDCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB7_RD_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB7_RD_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB7_RD_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB7_RD_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB7_RD_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_RD_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_RD_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_RD_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_RD_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_RD_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_RD_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_RD_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_RD_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB7_RD_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB7_RDCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB7_RDCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB7_RDCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB7_RDCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB7_RDCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB7_RDCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB7_WRCLI0_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_WRCLI1_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_WRCLI2_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_WRCLI3_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_WRCLI4_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_WRCLI5_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_WRCLI6_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_WRCLI7_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_WRCLI8_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_WRCLI9_DEFAULT                                                   0xfe5fe0f9
>+#define mmDAGB7_WRCLI10_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB7_WRCLI11_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB7_WRCLI12_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB7_WRCLI13_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB7_WRCLI14_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB7_WRCLI15_DEFAULT                                                  0xfe5fe0f9
>+#define mmDAGB7_WR_CNTL_DEFAULT                                                  0x03527df8
>+#define mmDAGB7_WR_GMI_CNTL_DEFAULT                                              0x00003045
>+#define mmDAGB7_WR_ADDR_DAGB_DEFAULT                                             0x00000039
>+#define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT                                 0x88888888
>+#define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT                                0x11111111
>+#define mmDAGB7_WR_CGTT_CLK_CTRL_DEFAULT                                         0x00000100
>+#define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT                                   0x00000100
>+#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0_DEFAULT                                  0x88888888
>+#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT                                 0x11111111
>+#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1_DEFAULT                                  0x88888888
>+#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT                                 0x11111111
>+#define mmDAGB7_WR_DATA_DAGB_DEFAULT                                             0x00000001
>+#define mmDAGB7_WR_DATA_DAGB_MAX_BURST0_DEFAULT                                  0x11111111
>+#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT                                 0x00000000
>+#define mmDAGB7_WR_DATA_DAGB_MAX_BURST1_DEFAULT                                  0x11111111
>+#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT                                 0x00000000
>+#define mmDAGB7_WR_VC0_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_WR_VC1_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_WR_VC2_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_WR_VC3_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_WR_VC4_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_WR_VC5_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_WR_VC6_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_WR_VC7_CNTL_DEFAULT                                              0xff2ff082
>+#define mmDAGB7_WR_CNTL_MISC_DEFAULT                                             0x69a0e408
>+#define mmDAGB7_WR_TLB_CREDIT_DEFAULT                                            0x2f7bdef7
>+#define mmDAGB7_WR_DATA_CREDIT_DEFAULT                                           0x60606070
>+#define mmDAGB7_WR_MISC_CREDIT_DEFAULT                                           0x0078dc88
>+#define mmDAGB7_WRCLI_ASK_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB7_WRCLI_GO_PENDING_DEFAULT                                         0x00000000
>+#define mmDAGB7_WRCLI_GBLSEND_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB7_WRCLI_TLB_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB7_WRCLI_OARB_PENDING_DEFAULT                                       0x00000000
>+#define mmDAGB7_WRCLI_OSD_PENDING_DEFAULT                                        0x00000000
>+#define mmDAGB7_WRCLI_DBUS_ASK_PENDING_DEFAULT                                   0x00000000
>+#define mmDAGB7_WRCLI_DBUS_GO_PENDING_DEFAULT                                    0x00000000
>+#define mmDAGB7_DAGB_DLY_DEFAULT                                                 0x00000000
>+#define mmDAGB7_CNTL_MISC_DEFAULT                                                0xcf7c1ffa
>+#define mmDAGB7_CNTL_MISC2_DEFAULT                                               0x003c0000
>+#define mmDAGB7_FIFO_EMPTY_DEFAULT                                               0x00ffffff
>+#define mmDAGB7_FIFO_FULL_DEFAULT                                                0x00000000
>+#define mmDAGB7_WR_CREDITS_FULL_DEFAULT                                          0x1fffffff
>+#define mmDAGB7_RD_CREDITS_FULL_DEFAULT                                          0x0003ffff
>+#define mmDAGB7_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmDAGB7_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmDAGB7_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB7_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB7_PERFCOUNTER2_CFG_DEFAULT                                         0x00000000
>+#define mmDAGB7_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmDAGB7_RESERVE0_DEFAULT                                                 0xffffffff
>+#define mmDAGB7_RESERVE1_DEFAULT                                                 0xffffffff
>+#define mmDAGB7_RESERVE2_DEFAULT                                                 0xffffffff
>+#define mmDAGB7_RESERVE3_DEFAULT                                                 0xffffffff
>+#define mmDAGB7_RESERVE4_DEFAULT                                                 0xffffffff
>+#define mmDAGB7_RESERVE5_DEFAULT                                                 0xffffffff
>+#define mmDAGB7_RESERVE6_DEFAULT                                                 0xffffffff
>+#define mmDAGB7_RESERVE7_DEFAULT                                                 0xffffffff
>+#define mmDAGB7_RESERVE8_DEFAULT                                                 0xffffffff
>+#define mmDAGB7_RESERVE9_DEFAULT                                                 0xffffffff
>+#define mmDAGB7_RESERVE10_DEFAULT                                                0xffffffff
>+#define mmDAGB7_RESERVE11_DEFAULT                                                0xffffffff
>+#define mmDAGB7_RESERVE12_DEFAULT                                                0xffffffff
>+#define mmDAGB7_RESERVE13_DEFAULT                                                0xffffffff
>+
>+
>+// addressBlock: mmhub_ea_mmeadec5
>+#define mmMMEA5_DRAM_RD_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA5_DRAM_RD_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA5_DRAM_WR_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA5_DRAM_WR_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA5_DRAM_RD_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA5_DRAM_WR_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA5_DRAM_RD_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA5_DRAM_WR_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA5_DRAM_RD_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA5_DRAM_WR_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA5_DRAM_PAGE_BURST_DEFAULT                                          0x20002000
>+#define mmMMEA5_DRAM_RD_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA5_DRAM_WR_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA5_DRAM_RD_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA5_DRAM_WR_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA5_DRAM_RD_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA5_DRAM_WR_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA5_DRAM_RD_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA5_DRAM_WR_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA5_GMI_RD_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA5_GMI_RD_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA5_GMI_WR_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA5_GMI_WR_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA5_GMI_RD_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA5_GMI_WR_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA5_GMI_RD_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA5_GMI_WR_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA5_GMI_RD_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA5_GMI_WR_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA5_GMI_PAGE_BURST_DEFAULT                                           0x20002000
>+#define mmMMEA5_GMI_RD_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA5_GMI_WR_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA5_GMI_RD_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA5_GMI_WR_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA5_GMI_RD_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA5_GMI_WR_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA5_GMI_RD_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA5_GMI_WR_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA5_GMI_RD_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA5_GMI_RD_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA5_GMI_RD_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA5_GMI_WR_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA5_GMI_WR_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA5_GMI_WR_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA5_ADDRNORM_BASE_ADDR0_DEFAULT                                      0x00000000
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR0_DEFAULT                                     0x00000000
>+#define mmMMEA5_ADDRNORM_BASE_ADDR1_DEFAULT                                      0x00000000
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR1_DEFAULT                                     0x00000000
>+#define mmMMEA5_ADDRNORM_OFFSET_ADDR1_DEFAULT                                    0x00000000
>+#define mmMMEA5_ADDRNORM_BASE_ADDR2_DEFAULT                                      0x00000000
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR2_DEFAULT                                     0x00000000
>+#define mmMMEA5_ADDRNORM_BASE_ADDR3_DEFAULT                                      0x00000000
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR3_DEFAULT                                     0x00000000
>+#define mmMMEA5_ADDRNORM_OFFSET_ADDR3_DEFAULT                                    0x00000000
>+#define mmMMEA5_ADDRNORM_BASE_ADDR4_DEFAULT                                      0x00000000
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR4_DEFAULT                                     0x00000000
>+#define mmMMEA5_ADDRNORM_BASE_ADDR5_DEFAULT                                      0x00000000
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR5_DEFAULT                                     0x00000000
>+#define mmMMEA5_ADDRNORM_OFFSET_ADDR5_DEFAULT                                    0x00000000
>+#define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRNORMGMI_HOLE_CNTL_DEFAULT                                    0x00000000
>+#define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT                             0x00000000
>+#define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT                              0x00000000
>+#define mmMMEA5_ADDRDEC_BANK_CFG_DEFAULT                                         0x000003cf
>+#define mmMMEA5_ADDRDEC_MISC_CFG_DEFAULT                                         0xfffff000
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT                              0x00000000
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT                              0x00000000
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT                              0x00000000
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT                              0x00000000
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT                              0x00000000
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT                              0x00000000
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT                                 0x00000000
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT                               0x00000000
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT                               0x00000000
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT                               0x00000000
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT                               0x00000000
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT                               0x00000000
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT                               0x00000000
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT                               0x00000000
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC_DEFAULT                                  0x00000000
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT                                 0x00000000
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT                                 0x00000000
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT                                 0x00000000
>+#define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA5_ADDRDEC0_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA5_ADDRDEC0_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA5_ADDRDEC1_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA5_ADDRDEC1_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA5_ADDRDEC2_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA5_ADDRDEC2_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT                                 0x00600000
>+#define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT                                  0x00600000
>+#define mmMMEA5_IO_RD_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA5_IO_RD_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA5_IO_WR_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA5_IO_WR_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA5_IO_RD_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA5_IO_WR_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA5_IO_GROUP_BURST_DEFAULT                                           0x1f031f03
>+#define mmMMEA5_IO_RD_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA5_IO_WR_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA5_IO_RD_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA5_IO_WR_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA5_IO_RD_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA5_IO_WR_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA5_IO_RD_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA5_IO_WR_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA5_IO_RD_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA5_IO_WR_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA5_IO_RD_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA5_IO_RD_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA5_IO_RD_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA5_IO_WR_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA5_IO_WR_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA5_IO_WR_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA5_SDP_ARB_DRAM_DEFAULT                                             0x00101e40
>+#define mmMMEA5_SDP_ARB_GMI_DEFAULT                                              0x00101e40
>+#define mmMMEA5_SDP_ARB_FINAL_DEFAULT                                            0x00007fff
>+#define mmMMEA5_SDP_DRAM_PRIORITY_DEFAULT                                        0x00000000
>+#define mmMMEA5_SDP_GMI_PRIORITY_DEFAULT                                         0x00000000
>+#define mmMMEA5_SDP_IO_PRIORITY_DEFAULT                                          0x00000000
>+#define mmMMEA5_SDP_CREDITS_DEFAULT                                              0x000101bf
>+#define mmMMEA5_SDP_TAG_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA5_SDP_TAG_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA5_SDP_VCC_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA5_SDP_VCC_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA5_SDP_VCD_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA5_SDP_VCD_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA5_SDP_REQ_CNTL_DEFAULT                                             0x0000001f
>+#define mmMMEA5_MISC_DEFAULT                                                     0x0c00a070
>+#define mmMMEA5_LATENCY_SAMPLING_DEFAULT                                         0x00000000
>+#define mmMMEA5_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmMMEA5_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmMMEA5_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA5_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA5_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmMMEA5_EDC_CNT_DEFAULT                                                  0x00000000
>+#define mmMMEA5_EDC_CNT2_DEFAULT                                                 0x00000000
>+#define mmMMEA5_DSM_CNTL_DEFAULT                                                 0x00000000
>+#define mmMMEA5_DSM_CNTLA_DEFAULT                                                0x00000000
>+#define mmMMEA5_DSM_CNTLB_DEFAULT                                                0x00000000
>+#define mmMMEA5_DSM_CNTL2_DEFAULT                                                0x00000000
>+#define mmMMEA5_DSM_CNTL2A_DEFAULT                                               0x00000000
>+#define mmMMEA5_DSM_CNTL2B_DEFAULT                                               0x00000000
>+#define mmMMEA5_CGTT_CLK_CTRL_DEFAULT                                            0x00000100
>+#define mmMMEA5_EDC_MODE_DEFAULT                                                 0x00000000
>+#define mmMMEA5_ERR_STATUS_DEFAULT                                               0x00000300
>+#define mmMMEA5_MISC2_DEFAULT                                                    0x00000000
>+#define mmMMEA5_ADDRDEC_SELECT_DEFAULT                                           0x00000000
>+#define mmMMEA5_EDC_CNT3_DEFAULT                                                 0x00000000
>+
>+
>+// addressBlock: mmhub_ea_mmeadec6
>+#define mmMMEA6_DRAM_RD_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA6_DRAM_RD_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA6_DRAM_WR_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA6_DRAM_WR_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA6_DRAM_RD_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA6_DRAM_WR_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA6_DRAM_RD_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA6_DRAM_WR_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA6_DRAM_RD_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA6_DRAM_WR_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA6_DRAM_PAGE_BURST_DEFAULT                                          0x20002000
>+#define mmMMEA6_DRAM_RD_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA6_DRAM_WR_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA6_DRAM_RD_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA6_DRAM_WR_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA6_DRAM_RD_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA6_DRAM_WR_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA6_DRAM_RD_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA6_DRAM_WR_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA6_GMI_RD_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA6_GMI_RD_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA6_GMI_WR_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA6_GMI_WR_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA6_GMI_RD_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA6_GMI_WR_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA6_GMI_RD_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA6_GMI_WR_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA6_GMI_RD_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA6_GMI_WR_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA6_GMI_PAGE_BURST_DEFAULT                                           0x20002000
>+#define mmMMEA6_GMI_RD_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA6_GMI_WR_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA6_GMI_RD_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA6_GMI_WR_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA6_GMI_RD_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA6_GMI_WR_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA6_GMI_RD_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA6_GMI_WR_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA6_GMI_RD_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA6_GMI_RD_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA6_GMI_RD_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA6_GMI_WR_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA6_GMI_WR_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA6_GMI_WR_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA6_ADDRNORM_BASE_ADDR0_DEFAULT                                      0x00000000
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR0_DEFAULT                                     0x00000000
>+#define mmMMEA6_ADDRNORM_BASE_ADDR1_DEFAULT                                      0x00000000
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR1_DEFAULT                                     0x00000000
>+#define mmMMEA6_ADDRNORM_OFFSET_ADDR1_DEFAULT                                    0x00000000
>+#define mmMMEA6_ADDRNORM_BASE_ADDR2_DEFAULT                                      0x00000000
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR2_DEFAULT                                     0x00000000
>+#define mmMMEA6_ADDRNORM_BASE_ADDR3_DEFAULT                                      0x00000000
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR3_DEFAULT                                     0x00000000
>+#define mmMMEA6_ADDRNORM_OFFSET_ADDR3_DEFAULT                                    0x00000000
>+#define mmMMEA6_ADDRNORM_BASE_ADDR4_DEFAULT                                      0x00000000
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR4_DEFAULT                                     0x00000000
>+#define mmMMEA6_ADDRNORM_BASE_ADDR5_DEFAULT                                      0x00000000
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR5_DEFAULT                                     0x00000000
>+#define mmMMEA6_ADDRNORM_OFFSET_ADDR5_DEFAULT                                    0x00000000
>+#define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRNORMGMI_HOLE_CNTL_DEFAULT                                    0x00000000
>+#define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT                             0x00000000
>+#define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT                              0x00000000
>+#define mmMMEA6_ADDRDEC_BANK_CFG_DEFAULT                                         0x000003cf
>+#define mmMMEA6_ADDRDEC_MISC_CFG_DEFAULT                                         0xfffff000
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT                              0x00000000
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT                              0x00000000
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT                              0x00000000
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT                              0x00000000
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT                              0x00000000
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT                              0x00000000
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT                                 0x00000000
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT                               0x00000000
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT                               0x00000000
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT                               0x00000000
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT                               0x00000000
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT                               0x00000000
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT                               0x00000000
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT                               0x00000000
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC_DEFAULT                                  0x00000000
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT                                 0x00000000
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT                                 0x00000000
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT                                 0x00000000
>+#define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA6_ADDRDEC0_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA6_ADDRDEC0_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA6_ADDRDEC1_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA6_ADDRDEC1_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA6_ADDRDEC2_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA6_ADDRDEC2_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT                                 0x00600000
>+#define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT                                  0x00600000
>+#define mmMMEA6_IO_RD_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA6_IO_RD_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA6_IO_WR_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA6_IO_WR_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA6_IO_RD_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA6_IO_WR_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA6_IO_GROUP_BURST_DEFAULT                                           0x1f031f03
>+#define mmMMEA6_IO_RD_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA6_IO_WR_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA6_IO_RD_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA6_IO_WR_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA6_IO_RD_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA6_IO_WR_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA6_IO_RD_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA6_IO_WR_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA6_IO_RD_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA6_IO_WR_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA6_IO_RD_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA6_IO_RD_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA6_IO_RD_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA6_IO_WR_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA6_IO_WR_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA6_IO_WR_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA6_SDP_ARB_DRAM_DEFAULT                                             0x00101e40
>+#define mmMMEA6_SDP_ARB_GMI_DEFAULT                                              0x00101e40
>+#define mmMMEA6_SDP_ARB_FINAL_DEFAULT                                            0x00007fff
>+#define mmMMEA6_SDP_DRAM_PRIORITY_DEFAULT                                        0x00000000
>+#define mmMMEA6_SDP_GMI_PRIORITY_DEFAULT                                         0x00000000
>+#define mmMMEA6_SDP_IO_PRIORITY_DEFAULT                                          0x00000000
>+#define mmMMEA6_SDP_CREDITS_DEFAULT                                              0x000101bf
>+#define mmMMEA6_SDP_TAG_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA6_SDP_TAG_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA6_SDP_VCC_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA6_SDP_VCC_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA6_SDP_VCD_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA6_SDP_VCD_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA6_SDP_REQ_CNTL_DEFAULT                                             0x0000001f
>+#define mmMMEA6_MISC_DEFAULT                                                     0x0c00a070
>+#define mmMMEA6_LATENCY_SAMPLING_DEFAULT                                         0x00000000
>+#define mmMMEA6_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmMMEA6_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmMMEA6_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA6_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA6_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmMMEA6_EDC_CNT_DEFAULT                                                  0x00000000
>+#define mmMMEA6_EDC_CNT2_DEFAULT                                                 0x00000000
>+#define mmMMEA6_DSM_CNTL_DEFAULT                                                 0x00000000
>+#define mmMMEA6_DSM_CNTLA_DEFAULT                                                0x00000000
>+#define mmMMEA6_DSM_CNTLB_DEFAULT                                                0x00000000
>+#define mmMMEA6_DSM_CNTL2_DEFAULT                                                0x00000000
>+#define mmMMEA6_DSM_CNTL2A_DEFAULT                                               0x00000000
>+#define mmMMEA6_DSM_CNTL2B_DEFAULT                                               0x00000000
>+#define mmMMEA6_CGTT_CLK_CTRL_DEFAULT                                            0x00000100
>+#define mmMMEA6_EDC_MODE_DEFAULT                                                 0x00000000
>+#define mmMMEA6_ERR_STATUS_DEFAULT                                               0x00000300
>+#define mmMMEA6_MISC2_DEFAULT                                                    0x00000000
>+#define mmMMEA6_ADDRDEC_SELECT_DEFAULT                                           0x00000000
>+#define mmMMEA6_EDC_CNT3_DEFAULT                                                 0x00000000
>+
>+
>+// addressBlock: mmhub_ea_mmeadec7
>+#define mmMMEA7_DRAM_RD_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA7_DRAM_RD_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA7_DRAM_WR_CLI2GRP_MAP0_DEFAULT                                     0x55555555
>+#define mmMMEA7_DRAM_WR_CLI2GRP_MAP1_DEFAULT                                     0x55555555
>+#define mmMMEA7_DRAM_RD_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA7_DRAM_WR_GRP2VC_MAP_DEFAULT                                       0x00000e25
>+#define mmMMEA7_DRAM_RD_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA7_DRAM_WR_LAZY_DEFAULT                                             0x78000924
>+#define mmMMEA7_DRAM_RD_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA7_DRAM_WR_CAM_CNTL_DEFAULT                                         0x16db4444
>+#define mmMMEA7_DRAM_PAGE_BURST_DEFAULT                                          0x20002000
>+#define mmMMEA7_DRAM_RD_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA7_DRAM_WR_PRI_AGE_DEFAULT                                          0x00db6249
>+#define mmMMEA7_DRAM_RD_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA7_DRAM_WR_PRI_QUEUING_DEFAULT                                      0x00000db6
>+#define mmMMEA7_DRAM_RD_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA7_DRAM_WR_PRI_FIXED_DEFAULT                                        0x00000924
>+#define mmMMEA7_DRAM_RD_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA7_DRAM_WR_PRI_URGENCY_DEFAULT                                      0x0000fdb6
>+#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1_DEFAULT                                   0x3f3f3f3f
>+#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2_DEFAULT                                   0x7f7f7f7f
>+#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3_DEFAULT                                   0xffffffff
>+#define mmMMEA7_GMI_RD_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA7_GMI_RD_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA7_GMI_WR_CLI2GRP_MAP0_DEFAULT                                      0x00000000
>+#define mmMMEA7_GMI_WR_CLI2GRP_MAP1_DEFAULT                                      0x00000000
>+#define mmMMEA7_GMI_RD_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA7_GMI_WR_GRP2VC_MAP_DEFAULT                                        0x00000fff
>+#define mmMMEA7_GMI_RD_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA7_GMI_WR_LAZY_DEFAULT                                              0x78000924
>+#define mmMMEA7_GMI_RD_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA7_GMI_WR_CAM_CNTL_DEFAULT                                          0x16db4444
>+#define mmMMEA7_GMI_PAGE_BURST_DEFAULT                                           0x20002000
>+#define mmMMEA7_GMI_RD_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA7_GMI_WR_PRI_AGE_DEFAULT                                           0x00db6249
>+#define mmMMEA7_GMI_RD_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA7_GMI_WR_PRI_QUEUING_DEFAULT                                       0x00000db6
>+#define mmMMEA7_GMI_RD_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA7_GMI_WR_PRI_FIXED_DEFAULT                                         0x00000924
>+#define mmMMEA7_GMI_RD_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA7_GMI_WR_PRI_URGENCY_DEFAULT                                       0x0000fdb6
>+#define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING_DEFAULT                               0xffffffff
>+#define mmMMEA7_GMI_RD_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA7_GMI_RD_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA7_GMI_RD_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA7_GMI_WR_PRI_QUANT_PRI1_DEFAULT                                    0x3f3f3f3f
>+#define mmMMEA7_GMI_WR_PRI_QUANT_PRI2_DEFAULT                                    0x7f7f7f7f
>+#define mmMMEA7_GMI_WR_PRI_QUANT_PRI3_DEFAULT                                    0xffffffff
>+#define mmMMEA7_ADDRNORM_BASE_ADDR0_DEFAULT                                      0x00000000
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR0_DEFAULT                                     0x00000000
>+#define mmMMEA7_ADDRNORM_BASE_ADDR1_DEFAULT                                      0x00000000
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR1_DEFAULT                                     0x00000000
>+#define mmMMEA7_ADDRNORM_OFFSET_ADDR1_DEFAULT                                    0x00000000
>+#define mmMMEA7_ADDRNORM_BASE_ADDR2_DEFAULT                                      0x00000000
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR2_DEFAULT                                     0x00000000
>+#define mmMMEA7_ADDRNORM_BASE_ADDR3_DEFAULT                                      0x00000000
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR3_DEFAULT                                     0x00000000
>+#define mmMMEA7_ADDRNORM_OFFSET_ADDR3_DEFAULT                                    0x00000000
>+#define mmMMEA7_ADDRNORM_BASE_ADDR4_DEFAULT                                      0x00000000
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR4_DEFAULT                                     0x00000000
>+#define mmMMEA7_ADDRNORM_BASE_ADDR5_DEFAULT                                      0x00000000
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR5_DEFAULT                                     0x00000000
>+#define mmMMEA7_ADDRNORM_OFFSET_ADDR5_DEFAULT                                    0x00000000
>+#define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRNORMGMI_HOLE_CNTL_DEFAULT                                    0x00000000
>+#define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT                             0x00000000
>+#define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG_DEFAULT                              0x00000000
>+#define mmMMEA7_ADDRDEC_BANK_CFG_DEFAULT                                         0x000003cf
>+#define mmMMEA7_ADDRDEC_MISC_CFG_DEFAULT                                         0xfffff000
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT                              0x00000000
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT                              0x00000000
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT                              0x00000000
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT                              0x00000000
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT                              0x00000000
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5_DEFAULT                              0x00000000
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT                                 0x00000000
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT                               0x00000000
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0_DEFAULT                               0x00000000
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1_DEFAULT                               0x00000000
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2_DEFAULT                               0x00000000
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3_DEFAULT                               0x00000000
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4_DEFAULT                               0x00000000
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5_DEFAULT                               0x00000000
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC_DEFAULT                                  0x00000000
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2_DEFAULT                                 0x00000000
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0_DEFAULT                                 0x00000000
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1_DEFAULT                                 0x00000000
>+#define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA7_ADDRDEC0_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA7_ADDRDEC0_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA7_ADDRDEC1_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA7_ADDRDEC1_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3_DEFAULT                                   0x00000000
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3_DEFAULT                                0x00000000
>+#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01_DEFAULT                                  0xfffffffe
>+#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23_DEFAULT                                  0xfffffffe
>+#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01_DEFAULT                               0xfffffffe
>+#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23_DEFAULT                               0xfffffffe
>+#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01_DEFAULT                                   0x00050408
>+#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23_DEFAULT                                   0x00050408
>+#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01_DEFAULT                                   0x04076543
>+#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23_DEFAULT                                   0x04076543
>+#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01_DEFAULT                                  0x00000008
>+#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23_DEFAULT                                  0x00000008
>+#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01_DEFAULT                                 0x87654321
>+#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23_DEFAULT                                 0x87654321
>+#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01_DEFAULT                                 0xa9876543
>+#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23_DEFAULT                                 0xa9876543
>+#define mmMMEA7_ADDRDEC2_RM_SEL_CS01_DEFAULT                                     0x00000000
>+#define mmMMEA7_ADDRDEC2_RM_SEL_CS23_DEFAULT                                     0x00000000
>+#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01_DEFAULT                                  0x00000000
>+#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23_DEFAULT                                  0x00000000
>+#define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL_DEFAULT                                 0x00600000
>+#define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL_DEFAULT                                  0x00600000
>+#define mmMMEA7_IO_RD_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA7_IO_RD_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA7_IO_WR_CLI2GRP_MAP0_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA7_IO_WR_CLI2GRP_MAP1_DEFAULT                                       0xe4e4e4e4
>+#define mmMMEA7_IO_RD_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA7_IO_WR_COMBINE_FLUSH_DEFAULT                                      0x00007777
>+#define mmMMEA7_IO_GROUP_BURST_DEFAULT                                           0x1f031f03
>+#define mmMMEA7_IO_RD_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA7_IO_WR_PRI_AGE_DEFAULT                                            0x00db6249
>+#define mmMMEA7_IO_RD_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA7_IO_WR_PRI_QUEUING_DEFAULT                                        0x00000db6
>+#define mmMMEA7_IO_RD_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA7_IO_WR_PRI_FIXED_DEFAULT                                          0x00000924
>+#define mmMMEA7_IO_RD_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA7_IO_WR_PRI_URGENCY_DEFAULT                                        0x00000492
>+#define mmMMEA7_IO_RD_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA7_IO_WR_PRI_URGENCY_MASKING_DEFAULT                                0xffffffff
>+#define mmMMEA7_IO_RD_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA7_IO_RD_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA7_IO_RD_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA7_IO_WR_PRI_QUANT_PRI1_DEFAULT                                     0x3f3f3f3f
>+#define mmMMEA7_IO_WR_PRI_QUANT_PRI2_DEFAULT                                     0x7f7f7f7f
>+#define mmMMEA7_IO_WR_PRI_QUANT_PRI3_DEFAULT                                     0xffffffff
>+#define mmMMEA7_SDP_ARB_DRAM_DEFAULT                                             0x00101e40
>+#define mmMMEA7_SDP_ARB_GMI_DEFAULT                                              0x00101e40
>+#define mmMMEA7_SDP_ARB_FINAL_DEFAULT                                            0x00007fff
>+#define mmMMEA7_SDP_DRAM_PRIORITY_DEFAULT                                        0x00000000
>+#define mmMMEA7_SDP_GMI_PRIORITY_DEFAULT                                         0x00000000
>+#define mmMMEA7_SDP_IO_PRIORITY_DEFAULT                                          0x00000000
>+#define mmMMEA7_SDP_CREDITS_DEFAULT                                              0x000101bf
>+#define mmMMEA7_SDP_TAG_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA7_SDP_TAG_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA7_SDP_VCC_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA7_SDP_VCC_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA7_SDP_VCD_RESERVE0_DEFAULT                                         0x00000000
>+#define mmMMEA7_SDP_VCD_RESERVE1_DEFAULT                                         0x00000000
>+#define mmMMEA7_SDP_REQ_CNTL_DEFAULT                                             0x0000001f
>+#define mmMMEA7_MISC_DEFAULT                                                     0x0c00a070
>+#define mmMMEA7_LATENCY_SAMPLING_DEFAULT                                         0x00000000
>+#define mmMMEA7_PERFCOUNTER_LO_DEFAULT                                           0x00000000
>+#define mmMMEA7_PERFCOUNTER_HI_DEFAULT                                           0x00000000
>+#define mmMMEA7_PERFCOUNTER0_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA7_PERFCOUNTER1_CFG_DEFAULT                                         0x00000000
>+#define mmMMEA7_PERFCOUNTER_RSLT_CNTL_DEFAULT                                    0x04000000
>+#define mmMMEA7_EDC_CNT_DEFAULT                                                  0x00000000
>+#define mmMMEA7_EDC_CNT2_DEFAULT                                                 0x00000000
>+#define mmMMEA7_DSM_CNTL_DEFAULT                                                 0x00000000
>+#define mmMMEA7_DSM_CNTLA_DEFAULT                                                0x00000000
>+#define mmMMEA7_DSM_CNTLB_DEFAULT                                                0x00000000
>+#define mmMMEA7_DSM_CNTL2_DEFAULT                                                0x00000000
>+#define mmMMEA7_DSM_CNTL2A_DEFAULT                                               0x00000000
>+#define mmMMEA7_DSM_CNTL2B_DEFAULT                                               0x00000000
>+#define mmMMEA7_CGTT_CLK_CTRL_DEFAULT                                            0x00000100
>+#define mmMMEA7_EDC_MODE_DEFAULT                                                 0x00000000
>+#define mmMMEA7_ERR_STATUS_DEFAULT                                               0x00000300
>+#define mmMMEA7_MISC2_DEFAULT                                                    0x00000000
>+#define mmMMEA7_ADDRDEC_SELECT_DEFAULT                                           0x00000000
>+#define mmMMEA7_EDC_CNT3_DEFAULT                                                 0x00000000
>+
>+
>+// addressBlock: mmhub_pctldec1
>+#define mmPCTL1_CTRL_DEFAULT                                                     0x00011040
>+#define mmPCTL1_MMHUB_DEEPSLEEP_IB_DEFAULT                                       0x00000000
>+#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT                                 0x00000000
>+#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB_DEFAULT                              0x00000000
>+#define mmPCTL1_PG_IGNORE_DEEPSLEEP_DEFAULT                                      0x00000000
>+#define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB_DEFAULT                                   0x00000000
>+#define mmPCTL1_SLICE0_CFG_DAGB_BUSY_DEFAULT                                     0x00000000
>+#define mmPCTL1_SLICE0_CFG_DS_ALLOW_DEFAULT                                      0x00000000
>+#define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB_DEFAULT                                   0x00000000
>+#define mmPCTL1_SLICE1_CFG_DAGB_BUSY_DEFAULT                                     0x00000000
>+#define mmPCTL1_SLICE1_CFG_DS_ALLOW_DEFAULT                                      0x00000000
>+#define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB_DEFAULT                                   0x00000000
>+#define mmPCTL1_SLICE2_CFG_DAGB_BUSY_DEFAULT                                     0x00000000
>+#define mmPCTL1_SLICE2_CFG_DS_ALLOW_DEFAULT                                      0x00000000
>+#define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB_DEFAULT                                   0x00000000
>+#define mmPCTL1_SLICE3_CFG_DAGB_BUSY_DEFAULT                                     0x00000000
>+#define mmPCTL1_SLICE3_CFG_DS_ALLOW_DEFAULT                                      0x00000000
>+#define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB_DEFAULT                                   0x00000000
>+#define mmPCTL1_SLICE4_CFG_DAGB_BUSY_DEFAULT                                     0x00000000
>+#define mmPCTL1_SLICE4_CFG_DS_ALLOW_DEFAULT                                      0x00000000
>+#define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB_DEFAULT                                   0x00000000
>+#define mmPCTL1_UTCL2_MISC_DEFAULT                                               0x00011000
>+#define mmPCTL1_SLICE0_MISC_DEFAULT                                              0x00000800
>+#define mmPCTL1_SLICE1_MISC_DEFAULT                                              0x00000800
>+#define mmPCTL1_SLICE2_MISC_DEFAULT                                              0x00000800
>+#define mmPCTL1_SLICE3_MISC_DEFAULT                                              0x00000800
>+#define mmPCTL1_SLICE4_MISC_DEFAULT                                              0x00000800
>+#define mmPCTL1_UTCL2_RENG_EXECUTE_DEFAULT                                       0x00000000
>+#define mmPCTL1_SLICE0_RENG_EXECUTE_DEFAULT                                      0x00000000
>+#define mmPCTL1_SLICE1_RENG_EXECUTE_DEFAULT                                      0x00000000
>+#define mmPCTL1_SLICE2_RENG_EXECUTE_DEFAULT                                      0x00000000
>+#define mmPCTL1_SLICE3_RENG_EXECUTE_DEFAULT                                      0x00000000
>+#define mmPCTL1_SLICE4_RENG_EXECUTE_DEFAULT                                      0x00000000
>+#define mmPCTL1_UTCL2_RENG_RAM_INDEX_DEFAULT                                     0x00000000
>+#define mmPCTL1_UTCL2_RENG_RAM_DATA_DEFAULT                                      0x00000000
>+#define mmPCTL1_SLICE0_RENG_RAM_INDEX_DEFAULT                                    0x00000000
>+#define mmPCTL1_SLICE0_RENG_RAM_DATA_DEFAULT                                     0x00000000
>+#define mmPCTL1_SLICE1_RENG_RAM_INDEX_DEFAULT                                    0x00000000
>+#define mmPCTL1_SLICE1_RENG_RAM_DATA_DEFAULT                                     0x00000000
>+#define mmPCTL1_SLICE2_RENG_RAM_INDEX_DEFAULT                                    0x00000000
>+#define mmPCTL1_SLICE2_RENG_RAM_DATA_DEFAULT                                     0x00000000
>+#define mmPCTL1_SLICE3_RENG_RAM_INDEX_DEFAULT                                    0x00000000
>+#define mmPCTL1_SLICE3_RENG_RAM_DATA_DEFAULT                                     0x00000000
>+#define mmPCTL1_SLICE4_RENG_RAM_INDEX_DEFAULT                                    0x00000000
>+#define mmPCTL1_SLICE4_RENG_RAM_DATA_DEFAULT                                     0x00000000
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                        0x00000000
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                        0x00000000
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                        0x00000000
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                        0x00000000
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                        0x00000000
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                     0xffffffff
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                     0xffffffff
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                    0xffffffff
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                    0xffffffff
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                    0xffffffff
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                    0xffffffff
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                    0xffffffff
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                    0xffffffff
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                    0xffffffff
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                    0xffffffff
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT                       0x00000000
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_DEFAULT                    0xffffffff
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT                    0xffffffff
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1dec:1
>+#define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS_DEFAULT                                 0x00000000
>+#define mmVML1_1_MC_VM_MX_L1_TMZ_CNTL_DEFAULT                                    0x00000000
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1pldec:1
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT                           0x00000000
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT                           0x00000000
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT                           0x00000000
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT                           0x00000000
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT                      0x04000000
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1prdec:1
>+#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT                             0x00000000
>+#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT                             0x00000000
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2dec:1
>+#define mmATCL2_1_ATC_L2_CNTL_DEFAULT                                            0x0001c0c9
>+#define mmATCL2_1_ATC_L2_CNTL2_DEFAULT                                           0x00600100
>+#define mmATCL2_1_ATC_L2_CACHE_DATA0_DEFAULT                                     0x00000000
>+#define mmATCL2_1_ATC_L2_CACHE_DATA1_DEFAULT                                     0x00000000
>+#define mmATCL2_1_ATC_L2_CACHE_DATA2_DEFAULT                                     0x00000000
>+#define mmATCL2_1_ATC_L2_CNTL3_DEFAULT                                           0x000001f8
>+#define mmATCL2_1_ATC_L2_STATUS_DEFAULT                                          0x00000000
>+#define mmATCL2_1_ATC_L2_STATUS2_DEFAULT                                         0x00000000
>+#define mmATCL2_1_ATC_L2_STATUS3_DEFAULT                                         0x00000000
>+#define mmATCL2_1_ATC_L2_MISC_CG_DEFAULT                                         0x00000200
>+#define mmATCL2_1_ATC_L2_MEM_POWER_LS_DEFAULT                                    0x00000208
>+#define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL_DEFAULT                                   0x00000080
>+#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX_DEFAULT                              0x00000000
>+#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX_DEFAULT                              0x00000000
>+#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL_DEFAULT                               0x00000000
>+#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL_DEFAULT                               0x00000000
>+#define mmATCL2_1_ATC_L2_CNTL4_DEFAULT                                           0x00000000
>+#define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES_DEFAULT                             0x00000005
>+
>+
>+// addressBlock: mmhub_utcl2_vml2pfdec:1
>+#define mmVML2PF1_VM_L2_CNTL_DEFAULT                                             0x00080602
>+#define mmVML2PF1_VM_L2_CNTL2_DEFAULT                                            0x00000000
>+#define mmVML2PF1_VM_L2_CNTL3_DEFAULT                                            0x80100007
>+#define mmVML2PF1_VM_L2_STATUS_DEFAULT                                           0x00000000
>+#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL_DEFAULT                               0x00000090
>+#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT                          0x00000000
>+#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT                          0x00000000
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL_DEFAULT                            0x3ffffffc
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2_DEFAULT                           0x000a0000
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT                        0xffffffff
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT                        0xffffffff
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS_DEFAULT                          0x00000000
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT                       0x00000000
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT                       0x00000000
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT               0x00000000
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT               0x00000000
>+#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT         0x00000000
>+#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT         0x00000000
>+#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT        0x00000000
>+#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT        0x00000000
>+#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT            0x00000000
>+#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT            0x00000000
>+#define mmVML2PF1_VM_L2_CNTL4_DEFAULT                                            0x000000c1
>+#define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES_DEFAULT                              0x00000000
>+#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID_DEFAULT                         0x00000000
>+#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT                        0x00000000
>+#define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL_DEFAULT                                0x00000000
>+#define mmVML2PF1_VM_L2_CGTT_CLK_CTRL_DEFAULT                                    0x00000080
>+
>+
>+// addressBlock: mmhub_utcl2_vml2vcdec:1
>+#define mmVML2VC1_VM_CONTEXT0_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT1_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT2_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT3_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT4_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT5_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT6_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT7_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT8_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT9_CNTL_DEFAULT                                       0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT10_CNTL_DEFAULT                                      0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT11_CNTL_DEFAULT                                      0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT12_CNTL_DEFAULT                                      0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT13_CNTL_DEFAULT                                      0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT14_CNTL_DEFAULT                                      0x007ffe80
>+#define mmVML2VC1_VM_CONTEXT15_CNTL_DEFAULT                                      0x007ffe80
>+#define mmVML2VC1_VM_CONTEXTS_DISABLE_DEFAULT                                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_SEM_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_SEM_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_REQ_DEFAULT                                 0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_REQ_DEFAULT                                0x017c0000
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_ACK_DEFAULT                                 0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_ACK_DEFAULT                                0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT                     0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT                    0x00000000
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT                 0x00000000
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT                0x00000000
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT                0x00000000
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT                   0x00000000
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT                  0x00000000
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT                  0x00000000
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedpfdec:1
>+#define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE_DEFAULT                                  0x00000000
>+#define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT_DEFAULT                                 0x00000000
>+#define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL_DEFAULT                                  0x00000000
>+#define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB_DEFAULT                                   0x00000008
>+#define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT                         0x00000000
>+#define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT                        0x00000000
>+#define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT                        0x00000000
>+#define mmVMSHAREDPF1_MC_VM_FB_OFFSET_DEFAULT                                    0x00000000
>+#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT             0x00000000
>+#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT             0x00000000
>+#define mmVMSHAREDPF1_MC_VM_STEERING_DEFAULT                                     0x00000001
>+#define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ_DEFAULT                           0x00000000
>+#define mmVMSHAREDPF1_MC_MEM_POWER_LS_DEFAULT                                    0x00000208
>+#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT                 0x00000000
>+#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT                   0x00000000
>+#define mmVMSHAREDPF1_MC_VM_APT_CNTL_DEFAULT                                     0x00000000
>+#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT                      0x00000000
>+#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT                        0x000fffff
>+#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT                  0x00000000
>+#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL_DEFAULT                                0x00000000
>+#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE_DEFAULT                                0x00000000
>+#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL_DEFAULT                          0x00000000
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedvcdec:1
>+#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE_DEFAULT                             0x00000000
>+#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP_DEFAULT                              0x00000000
>+#define mmVMSHAREDVC1_MC_VM_AGP_TOP_DEFAULT                                      0x00000000
>+#define mmVMSHAREDVC1_MC_VM_AGP_BOT_DEFAULT                                      0x00000000
>+#define mmVMSHAREDVC1_MC_VM_AGP_BASE_DEFAULT                                     0x00000000
>+#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT                     0x00000000
>+#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT                    0x00000000
>+#define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL_DEFAULT                               0x00002501
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedhvdec:1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9_DEFAULT                           0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1_DEFAULT                              0x00000100
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3_DEFAULT                               0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3_DEFAULT                                0x00000000
>+#define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER_DEFAULT                          0x00000000
>+#define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_DEFAULT                                   0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9_DEFAULT                              0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10_DEFAULT                             0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11_DEFAULT                             0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12_DEFAULT                             0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13_DEFAULT                             0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14_DEFAULT                             0x00000000
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15_DEFAULT                             0x00000000
>+#define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL_DEFAULT                                0x00000080
>+#define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID_DEFAULT                            0x00000000
>+#define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE_DEFAULT                           0x00000000
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2pfcntrdec:1
>+#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO_DEFAULT                             0x00000000
>+#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI_DEFAULT                             0x00000000
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2pfcntldec:1
>+#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG_DEFAULT                           0x00000000
>+#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG_DEFAULT                           0x00000000
>+#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT                      0x04000000
>+
>+
>+// addressBlock: mmhub_utcl2_vml2pldec:1
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG_DEFAULT                              0x00000000
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT                         0x04000000
>+
>+
>+// addressBlock: mmhub_utcl2_vml2prdec:1
>+#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO_DEFAULT                                0x00000000
>+#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI_DEFAULT                                0x00000000
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h	2019-08-31 15:01:11.906736172 -0500
>@@ -0,0 +1,7753 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _mmhub_9_4_1_OFFSET_HEADER
>+#define _mmhub_9_4_1_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec0
>+// base address: 0x68000
>+#define mmDAGB0_RDCLI0                                                                                 0x0000
>+#define mmDAGB0_RDCLI0_BASE_IDX                                                                        1
>+#define mmDAGB0_RDCLI1                                                                                 0x0001
>+#define mmDAGB0_RDCLI1_BASE_IDX                                                                        1
>+#define mmDAGB0_RDCLI2                                                                                 0x0002
>+#define mmDAGB0_RDCLI2_BASE_IDX                                                                        1
>+#define mmDAGB0_RDCLI3                                                                                 0x0003
>+#define mmDAGB0_RDCLI3_BASE_IDX                                                                        1
>+#define mmDAGB0_RDCLI4                                                                                 0x0004
>+#define mmDAGB0_RDCLI4_BASE_IDX                                                                        1
>+#define mmDAGB0_RDCLI5                                                                                 0x0005
>+#define mmDAGB0_RDCLI5_BASE_IDX                                                                        1
>+#define mmDAGB0_RDCLI6                                                                                 0x0006
>+#define mmDAGB0_RDCLI6_BASE_IDX                                                                        1
>+#define mmDAGB0_RDCLI7                                                                                 0x0007
>+#define mmDAGB0_RDCLI7_BASE_IDX                                                                        1
>+#define mmDAGB0_RDCLI8                                                                                 0x0008
>+#define mmDAGB0_RDCLI8_BASE_IDX                                                                        1
>+#define mmDAGB0_RDCLI9                                                                                 0x0009
>+#define mmDAGB0_RDCLI9_BASE_IDX                                                                        1
>+#define mmDAGB0_RDCLI10                                                                                0x000a
>+#define mmDAGB0_RDCLI10_BASE_IDX                                                                       1
>+#define mmDAGB0_RDCLI11                                                                                0x000b
>+#define mmDAGB0_RDCLI11_BASE_IDX                                                                       1
>+#define mmDAGB0_RDCLI12                                                                                0x000c
>+#define mmDAGB0_RDCLI12_BASE_IDX                                                                       1
>+#define mmDAGB0_RDCLI13                                                                                0x000d
>+#define mmDAGB0_RDCLI13_BASE_IDX                                                                       1
>+#define mmDAGB0_RDCLI14                                                                                0x000e
>+#define mmDAGB0_RDCLI14_BASE_IDX                                                                       1
>+#define mmDAGB0_RDCLI15                                                                                0x000f
>+#define mmDAGB0_RDCLI15_BASE_IDX                                                                       1
>+#define mmDAGB0_RD_CNTL                                                                                0x0010
>+#define mmDAGB0_RD_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB0_RD_GMI_CNTL                                                                            0x0011
>+#define mmDAGB0_RD_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_RD_ADDR_DAGB                                                                           0x0012
>+#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST                                                               0x0013
>+#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER                                                              0x0014
>+#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB0_RD_CGTT_CLK_CTRL                                                                       0x0015
>+#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL                                                                 0x0016
>+#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL                                                                 0x0017
>+#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0                                                                0x0018
>+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0                                                               0x0019
>+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1                                                                0x001a
>+#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1                                                               0x001b
>+#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB0_RD_VC0_CNTL                                                                            0x001c
>+#define mmDAGB0_RD_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_RD_VC1_CNTL                                                                            0x001d
>+#define mmDAGB0_RD_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_RD_VC2_CNTL                                                                            0x001e
>+#define mmDAGB0_RD_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_RD_VC3_CNTL                                                                            0x001f
>+#define mmDAGB0_RD_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_RD_VC4_CNTL                                                                            0x0020
>+#define mmDAGB0_RD_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_RD_VC5_CNTL                                                                            0x0021
>+#define mmDAGB0_RD_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_RD_VC6_CNTL                                                                            0x0022
>+#define mmDAGB0_RD_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_RD_VC7_CNTL                                                                            0x0023
>+#define mmDAGB0_RD_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_RD_CNTL_MISC                                                                           0x0024
>+#define mmDAGB0_RD_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB0_RD_TLB_CREDIT                                                                          0x0025
>+#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB0_RDCLI_ASK_PENDING                                                                      0x0026
>+#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB0_RDCLI_GO_PENDING                                                                       0x0027
>+#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB0_RDCLI_GBLSEND_PENDING                                                                  0x0028
>+#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB0_RDCLI_TLB_PENDING                                                                      0x0029
>+#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB0_RDCLI_OARB_PENDING                                                                     0x002a
>+#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB0_RDCLI_OSD_PENDING                                                                      0x002b
>+#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB0_WRCLI0                                                                                 0x002c
>+#define mmDAGB0_WRCLI0_BASE_IDX                                                                        1
>+#define mmDAGB0_WRCLI1                                                                                 0x002d
>+#define mmDAGB0_WRCLI1_BASE_IDX                                                                        1
>+#define mmDAGB0_WRCLI2                                                                                 0x002e
>+#define mmDAGB0_WRCLI2_BASE_IDX                                                                        1
>+#define mmDAGB0_WRCLI3                                                                                 0x002f
>+#define mmDAGB0_WRCLI3_BASE_IDX                                                                        1
>+#define mmDAGB0_WRCLI4                                                                                 0x0030
>+#define mmDAGB0_WRCLI4_BASE_IDX                                                                        1
>+#define mmDAGB0_WRCLI5                                                                                 0x0031
>+#define mmDAGB0_WRCLI5_BASE_IDX                                                                        1
>+#define mmDAGB0_WRCLI6                                                                                 0x0032
>+#define mmDAGB0_WRCLI6_BASE_IDX                                                                        1
>+#define mmDAGB0_WRCLI7                                                                                 0x0033
>+#define mmDAGB0_WRCLI7_BASE_IDX                                                                        1
>+#define mmDAGB0_WRCLI8                                                                                 0x0034
>+#define mmDAGB0_WRCLI8_BASE_IDX                                                                        1
>+#define mmDAGB0_WRCLI9                                                                                 0x0035
>+#define mmDAGB0_WRCLI9_BASE_IDX                                                                        1
>+#define mmDAGB0_WRCLI10                                                                                0x0036
>+#define mmDAGB0_WRCLI10_BASE_IDX                                                                       1
>+#define mmDAGB0_WRCLI11                                                                                0x0037
>+#define mmDAGB0_WRCLI11_BASE_IDX                                                                       1
>+#define mmDAGB0_WRCLI12                                                                                0x0038
>+#define mmDAGB0_WRCLI12_BASE_IDX                                                                       1
>+#define mmDAGB0_WRCLI13                                                                                0x0039
>+#define mmDAGB0_WRCLI13_BASE_IDX                                                                       1
>+#define mmDAGB0_WRCLI14                                                                                0x003a
>+#define mmDAGB0_WRCLI14_BASE_IDX                                                                       1
>+#define mmDAGB0_WRCLI15                                                                                0x003b
>+#define mmDAGB0_WRCLI15_BASE_IDX                                                                       1
>+#define mmDAGB0_WR_CNTL                                                                                0x003c
>+#define mmDAGB0_WR_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB0_WR_GMI_CNTL                                                                            0x003d
>+#define mmDAGB0_WR_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_WR_ADDR_DAGB                                                                           0x003e
>+#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST                                                               0x003f
>+#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER                                                              0x0040
>+#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB0_WR_CGTT_CLK_CTRL                                                                       0x0041
>+#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL                                                                 0x0042
>+#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL                                                                 0x0043
>+#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0                                                                0x0044
>+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0                                                               0x0045
>+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1                                                                0x0046
>+#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1                                                               0x0047
>+#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB0_WR_DATA_DAGB                                                                           0x0048
>+#define mmDAGB0_WR_DATA_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0                                                                0x0049
>+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0                                                               0x004a
>+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1                                                                0x004b
>+#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1                                                               0x004c
>+#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB0_WR_VC0_CNTL                                                                            0x004d
>+#define mmDAGB0_WR_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_WR_VC1_CNTL                                                                            0x004e
>+#define mmDAGB0_WR_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_WR_VC2_CNTL                                                                            0x004f
>+#define mmDAGB0_WR_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_WR_VC3_CNTL                                                                            0x0050
>+#define mmDAGB0_WR_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_WR_VC4_CNTL                                                                            0x0051
>+#define mmDAGB0_WR_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_WR_VC5_CNTL                                                                            0x0052
>+#define mmDAGB0_WR_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_WR_VC6_CNTL                                                                            0x0053
>+#define mmDAGB0_WR_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_WR_VC7_CNTL                                                                            0x0054
>+#define mmDAGB0_WR_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB0_WR_CNTL_MISC                                                                           0x0055
>+#define mmDAGB0_WR_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB0_WR_TLB_CREDIT                                                                          0x0056
>+#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB0_WR_DATA_CREDIT                                                                         0x0057
>+#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB0_WR_MISC_CREDIT                                                                         0x0058
>+#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB0_WRCLI_ASK_PENDING                                                                      0x005d
>+#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB0_WRCLI_GO_PENDING                                                                       0x005e
>+#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB0_WRCLI_GBLSEND_PENDING                                                                  0x005f
>+#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB0_WRCLI_TLB_PENDING                                                                      0x0060
>+#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB0_WRCLI_OARB_PENDING                                                                     0x0061
>+#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB0_WRCLI_OSD_PENDING                                                                      0x0062
>+#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB0_WRCLI_DBUS_ASK_PENDING                                                                 0x0063
>+#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX                                                        1
>+#define mmDAGB0_WRCLI_DBUS_GO_PENDING                                                                  0x0064
>+#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX                                                         1
>+#define mmDAGB0_DAGB_DLY                                                                               0x0065
>+#define mmDAGB0_DAGB_DLY_BASE_IDX                                                                      1
>+#define mmDAGB0_CNTL_MISC                                                                              0x0066
>+#define mmDAGB0_CNTL_MISC_BASE_IDX                                                                     1
>+#define mmDAGB0_CNTL_MISC2                                                                             0x0067
>+#define mmDAGB0_CNTL_MISC2_BASE_IDX                                                                    1
>+#define mmDAGB0_FIFO_EMPTY                                                                             0x0068
>+#define mmDAGB0_FIFO_EMPTY_BASE_IDX                                                                    1
>+#define mmDAGB0_FIFO_FULL                                                                              0x0069
>+#define mmDAGB0_FIFO_FULL_BASE_IDX                                                                     1
>+#define mmDAGB0_WR_CREDITS_FULL                                                                        0x006a
>+#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB0_RD_CREDITS_FULL                                                                        0x006b
>+#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB0_PERFCOUNTER_LO                                                                         0x006c
>+#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmDAGB0_PERFCOUNTER_HI                                                                         0x006d
>+#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmDAGB0_PERFCOUNTER0_CFG                                                                       0x006e
>+#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmDAGB0_PERFCOUNTER1_CFG                                                                       0x006f
>+#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmDAGB0_PERFCOUNTER2_CFG                                                                       0x0070
>+#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX                                                              1
>+#define mmDAGB0_PERFCOUNTER_RSLT_CNTL                                                                  0x0071
>+#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmDAGB0_RESERVE0                                                                               0x0072
>+#define mmDAGB0_RESERVE0_BASE_IDX                                                                      1
>+#define mmDAGB0_RESERVE1                                                                               0x0073
>+#define mmDAGB0_RESERVE1_BASE_IDX                                                                      1
>+#define mmDAGB0_RESERVE2                                                                               0x0074
>+#define mmDAGB0_RESERVE2_BASE_IDX                                                                      1
>+#define mmDAGB0_RESERVE3                                                                               0x0075
>+#define mmDAGB0_RESERVE3_BASE_IDX                                                                      1
>+#define mmDAGB0_RESERVE4                                                                               0x0076
>+#define mmDAGB0_RESERVE4_BASE_IDX                                                                      1
>+#define mmDAGB0_RESERVE5                                                                               0x0077
>+#define mmDAGB0_RESERVE5_BASE_IDX                                                                      1
>+#define mmDAGB0_RESERVE6                                                                               0x0078
>+#define mmDAGB0_RESERVE6_BASE_IDX                                                                      1
>+#define mmDAGB0_RESERVE7                                                                               0x0079
>+#define mmDAGB0_RESERVE7_BASE_IDX                                                                      1
>+#define mmDAGB0_RESERVE8                                                                               0x007a
>+#define mmDAGB0_RESERVE8_BASE_IDX                                                                      1
>+#define mmDAGB0_RESERVE9                                                                               0x007b
>+#define mmDAGB0_RESERVE9_BASE_IDX                                                                      1
>+#define mmDAGB0_RESERVE10                                                                              0x007c
>+#define mmDAGB0_RESERVE10_BASE_IDX                                                                     1
>+#define mmDAGB0_RESERVE11                                                                              0x007d
>+#define mmDAGB0_RESERVE11_BASE_IDX                                                                     1
>+#define mmDAGB0_RESERVE12                                                                              0x007e
>+#define mmDAGB0_RESERVE12_BASE_IDX                                                                     1
>+#define mmDAGB0_RESERVE13                                                                              0x007f
>+#define mmDAGB0_RESERVE13_BASE_IDX                                                                     1
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec1
>+// base address: 0x68200
>+#define mmDAGB1_RDCLI0                                                                                 0x0080
>+#define mmDAGB1_RDCLI0_BASE_IDX                                                                        1
>+#define mmDAGB1_RDCLI1                                                                                 0x0081
>+#define mmDAGB1_RDCLI1_BASE_IDX                                                                        1
>+#define mmDAGB1_RDCLI2                                                                                 0x0082
>+#define mmDAGB1_RDCLI2_BASE_IDX                                                                        1
>+#define mmDAGB1_RDCLI3                                                                                 0x0083
>+#define mmDAGB1_RDCLI3_BASE_IDX                                                                        1
>+#define mmDAGB1_RDCLI4                                                                                 0x0084
>+#define mmDAGB1_RDCLI4_BASE_IDX                                                                        1
>+#define mmDAGB1_RDCLI5                                                                                 0x0085
>+#define mmDAGB1_RDCLI5_BASE_IDX                                                                        1
>+#define mmDAGB1_RDCLI6                                                                                 0x0086
>+#define mmDAGB1_RDCLI6_BASE_IDX                                                                        1
>+#define mmDAGB1_RDCLI7                                                                                 0x0087
>+#define mmDAGB1_RDCLI7_BASE_IDX                                                                        1
>+#define mmDAGB1_RDCLI8                                                                                 0x0088
>+#define mmDAGB1_RDCLI8_BASE_IDX                                                                        1
>+#define mmDAGB1_RDCLI9                                                                                 0x0089
>+#define mmDAGB1_RDCLI9_BASE_IDX                                                                        1
>+#define mmDAGB1_RDCLI10                                                                                0x008a
>+#define mmDAGB1_RDCLI10_BASE_IDX                                                                       1
>+#define mmDAGB1_RDCLI11                                                                                0x008b
>+#define mmDAGB1_RDCLI11_BASE_IDX                                                                       1
>+#define mmDAGB1_RDCLI12                                                                                0x008c
>+#define mmDAGB1_RDCLI12_BASE_IDX                                                                       1
>+#define mmDAGB1_RDCLI13                                                                                0x008d
>+#define mmDAGB1_RDCLI13_BASE_IDX                                                                       1
>+#define mmDAGB1_RDCLI14                                                                                0x008e
>+#define mmDAGB1_RDCLI14_BASE_IDX                                                                       1
>+#define mmDAGB1_RDCLI15                                                                                0x008f
>+#define mmDAGB1_RDCLI15_BASE_IDX                                                                       1
>+#define mmDAGB1_RD_CNTL                                                                                0x0090
>+#define mmDAGB1_RD_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB1_RD_GMI_CNTL                                                                            0x0091
>+#define mmDAGB1_RD_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_RD_ADDR_DAGB                                                                           0x0092
>+#define mmDAGB1_RD_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST                                                               0x0093
>+#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER                                                              0x0094
>+#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB1_RD_CGTT_CLK_CTRL                                                                       0x0095
>+#define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL                                                                 0x0096
>+#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL                                                                 0x0097
>+#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0                                                                0x0098
>+#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0                                                               0x0099
>+#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1                                                                0x009a
>+#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1                                                               0x009b
>+#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB1_RD_VC0_CNTL                                                                            0x009c
>+#define mmDAGB1_RD_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_RD_VC1_CNTL                                                                            0x009d
>+#define mmDAGB1_RD_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_RD_VC2_CNTL                                                                            0x009e
>+#define mmDAGB1_RD_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_RD_VC3_CNTL                                                                            0x009f
>+#define mmDAGB1_RD_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_RD_VC4_CNTL                                                                            0x00a0
>+#define mmDAGB1_RD_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_RD_VC5_CNTL                                                                            0x00a1
>+#define mmDAGB1_RD_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_RD_VC6_CNTL                                                                            0x00a2
>+#define mmDAGB1_RD_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_RD_VC7_CNTL                                                                            0x00a3
>+#define mmDAGB1_RD_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_RD_CNTL_MISC                                                                           0x00a4
>+#define mmDAGB1_RD_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB1_RD_TLB_CREDIT                                                                          0x00a5
>+#define mmDAGB1_RD_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB1_RDCLI_ASK_PENDING                                                                      0x00a6
>+#define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB1_RDCLI_GO_PENDING                                                                       0x00a7
>+#define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB1_RDCLI_GBLSEND_PENDING                                                                  0x00a8
>+#define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB1_RDCLI_TLB_PENDING                                                                      0x00a9
>+#define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB1_RDCLI_OARB_PENDING                                                                     0x00aa
>+#define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB1_RDCLI_OSD_PENDING                                                                      0x00ab
>+#define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB1_WRCLI0                                                                                 0x00ac
>+#define mmDAGB1_WRCLI0_BASE_IDX                                                                        1
>+#define mmDAGB1_WRCLI1                                                                                 0x00ad
>+#define mmDAGB1_WRCLI1_BASE_IDX                                                                        1
>+#define mmDAGB1_WRCLI2                                                                                 0x00ae
>+#define mmDAGB1_WRCLI2_BASE_IDX                                                                        1
>+#define mmDAGB1_WRCLI3                                                                                 0x00af
>+#define mmDAGB1_WRCLI3_BASE_IDX                                                                        1
>+#define mmDAGB1_WRCLI4                                                                                 0x00b0
>+#define mmDAGB1_WRCLI4_BASE_IDX                                                                        1
>+#define mmDAGB1_WRCLI5                                                                                 0x00b1
>+#define mmDAGB1_WRCLI5_BASE_IDX                                                                        1
>+#define mmDAGB1_WRCLI6                                                                                 0x00b2
>+#define mmDAGB1_WRCLI6_BASE_IDX                                                                        1
>+#define mmDAGB1_WRCLI7                                                                                 0x00b3
>+#define mmDAGB1_WRCLI7_BASE_IDX                                                                        1
>+#define mmDAGB1_WRCLI8                                                                                 0x00b4
>+#define mmDAGB1_WRCLI8_BASE_IDX                                                                        1
>+#define mmDAGB1_WRCLI9                                                                                 0x00b5
>+#define mmDAGB1_WRCLI9_BASE_IDX                                                                        1
>+#define mmDAGB1_WRCLI10                                                                                0x00b6
>+#define mmDAGB1_WRCLI10_BASE_IDX                                                                       1
>+#define mmDAGB1_WRCLI11                                                                                0x00b7
>+#define mmDAGB1_WRCLI11_BASE_IDX                                                                       1
>+#define mmDAGB1_WRCLI12                                                                                0x00b8
>+#define mmDAGB1_WRCLI12_BASE_IDX                                                                       1
>+#define mmDAGB1_WRCLI13                                                                                0x00b9
>+#define mmDAGB1_WRCLI13_BASE_IDX                                                                       1
>+#define mmDAGB1_WRCLI14                                                                                0x00ba
>+#define mmDAGB1_WRCLI14_BASE_IDX                                                                       1
>+#define mmDAGB1_WRCLI15                                                                                0x00bb
>+#define mmDAGB1_WRCLI15_BASE_IDX                                                                       1
>+#define mmDAGB1_WR_CNTL                                                                                0x00bc
>+#define mmDAGB1_WR_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB1_WR_GMI_CNTL                                                                            0x00bd
>+#define mmDAGB1_WR_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_WR_ADDR_DAGB                                                                           0x00be
>+#define mmDAGB1_WR_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST                                                               0x00bf
>+#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER                                                              0x00c0
>+#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB1_WR_CGTT_CLK_CTRL                                                                       0x00c1
>+#define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL                                                                 0x00c2
>+#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL                                                                 0x00c3
>+#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0                                                                0x00c4
>+#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0                                                               0x00c5
>+#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1                                                                0x00c6
>+#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1                                                               0x00c7
>+#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB1_WR_DATA_DAGB                                                                           0x00c8
>+#define mmDAGB1_WR_DATA_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0                                                                0x00c9
>+#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0                                                               0x00ca
>+#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1                                                                0x00cb
>+#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1                                                               0x00cc
>+#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB1_WR_VC0_CNTL                                                                            0x00cd
>+#define mmDAGB1_WR_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_WR_VC1_CNTL                                                                            0x00ce
>+#define mmDAGB1_WR_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_WR_VC2_CNTL                                                                            0x00cf
>+#define mmDAGB1_WR_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_WR_VC3_CNTL                                                                            0x00d0
>+#define mmDAGB1_WR_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_WR_VC4_CNTL                                                                            0x00d1
>+#define mmDAGB1_WR_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_WR_VC5_CNTL                                                                            0x00d2
>+#define mmDAGB1_WR_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_WR_VC6_CNTL                                                                            0x00d3
>+#define mmDAGB1_WR_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_WR_VC7_CNTL                                                                            0x00d4
>+#define mmDAGB1_WR_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB1_WR_CNTL_MISC                                                                           0x00d5
>+#define mmDAGB1_WR_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB1_WR_TLB_CREDIT                                                                          0x00d6
>+#define mmDAGB1_WR_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB1_WR_DATA_CREDIT                                                                         0x00d7
>+#define mmDAGB1_WR_DATA_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB1_WR_MISC_CREDIT                                                                         0x00d8
>+#define mmDAGB1_WR_MISC_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB1_WRCLI_ASK_PENDING                                                                      0x00dd
>+#define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB1_WRCLI_GO_PENDING                                                                       0x00de
>+#define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB1_WRCLI_GBLSEND_PENDING                                                                  0x00df
>+#define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB1_WRCLI_TLB_PENDING                                                                      0x00e0
>+#define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB1_WRCLI_OARB_PENDING                                                                     0x00e1
>+#define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB1_WRCLI_OSD_PENDING                                                                      0x00e2
>+#define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB1_WRCLI_DBUS_ASK_PENDING                                                                 0x00e3
>+#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX                                                        1
>+#define mmDAGB1_WRCLI_DBUS_GO_PENDING                                                                  0x00e4
>+#define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX                                                         1
>+#define mmDAGB1_DAGB_DLY                                                                               0x00e5
>+#define mmDAGB1_DAGB_DLY_BASE_IDX                                                                      1
>+#define mmDAGB1_CNTL_MISC                                                                              0x00e6
>+#define mmDAGB1_CNTL_MISC_BASE_IDX                                                                     1
>+#define mmDAGB1_CNTL_MISC2                                                                             0x00e7
>+#define mmDAGB1_CNTL_MISC2_BASE_IDX                                                                    1
>+#define mmDAGB1_FIFO_EMPTY                                                                             0x00e8
>+#define mmDAGB1_FIFO_EMPTY_BASE_IDX                                                                    1
>+#define mmDAGB1_FIFO_FULL                                                                              0x00e9
>+#define mmDAGB1_FIFO_FULL_BASE_IDX                                                                     1
>+#define mmDAGB1_WR_CREDITS_FULL                                                                        0x00ea
>+#define mmDAGB1_WR_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB1_RD_CREDITS_FULL                                                                        0x00eb
>+#define mmDAGB1_RD_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB1_PERFCOUNTER_LO                                                                         0x00ec
>+#define mmDAGB1_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmDAGB1_PERFCOUNTER_HI                                                                         0x00ed
>+#define mmDAGB1_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmDAGB1_PERFCOUNTER0_CFG                                                                       0x00ee
>+#define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmDAGB1_PERFCOUNTER1_CFG                                                                       0x00ef
>+#define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmDAGB1_PERFCOUNTER2_CFG                                                                       0x00f0
>+#define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX                                                              1
>+#define mmDAGB1_PERFCOUNTER_RSLT_CNTL                                                                  0x00f1
>+#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmDAGB1_RESERVE0                                                                               0x00f2
>+#define mmDAGB1_RESERVE0_BASE_IDX                                                                      1
>+#define mmDAGB1_RESERVE1                                                                               0x00f3
>+#define mmDAGB1_RESERVE1_BASE_IDX                                                                      1
>+#define mmDAGB1_RESERVE2                                                                               0x00f4
>+#define mmDAGB1_RESERVE2_BASE_IDX                                                                      1
>+#define mmDAGB1_RESERVE3                                                                               0x00f5
>+#define mmDAGB1_RESERVE3_BASE_IDX                                                                      1
>+#define mmDAGB1_RESERVE4                                                                               0x00f6
>+#define mmDAGB1_RESERVE4_BASE_IDX                                                                      1
>+#define mmDAGB1_RESERVE5                                                                               0x00f7
>+#define mmDAGB1_RESERVE5_BASE_IDX                                                                      1
>+#define mmDAGB1_RESERVE6                                                                               0x00f8
>+#define mmDAGB1_RESERVE6_BASE_IDX                                                                      1
>+#define mmDAGB1_RESERVE7                                                                               0x00f9
>+#define mmDAGB1_RESERVE7_BASE_IDX                                                                      1
>+#define mmDAGB1_RESERVE8                                                                               0x00fa
>+#define mmDAGB1_RESERVE8_BASE_IDX                                                                      1
>+#define mmDAGB1_RESERVE9                                                                               0x00fb
>+#define mmDAGB1_RESERVE9_BASE_IDX                                                                      1
>+#define mmDAGB1_RESERVE10                                                                              0x00fc
>+#define mmDAGB1_RESERVE10_BASE_IDX                                                                     1
>+#define mmDAGB1_RESERVE11                                                                              0x00fd
>+#define mmDAGB1_RESERVE11_BASE_IDX                                                                     1
>+#define mmDAGB1_RESERVE12                                                                              0x00fe
>+#define mmDAGB1_RESERVE12_BASE_IDX                                                                     1
>+#define mmDAGB1_RESERVE13                                                                              0x00ff
>+#define mmDAGB1_RESERVE13_BASE_IDX                                                                     1
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec2
>+// base address: 0x68400
>+#define mmDAGB2_RDCLI0                                                                                 0x0100
>+#define mmDAGB2_RDCLI0_BASE_IDX                                                                        1
>+#define mmDAGB2_RDCLI1                                                                                 0x0101
>+#define mmDAGB2_RDCLI1_BASE_IDX                                                                        1
>+#define mmDAGB2_RDCLI2                                                                                 0x0102
>+#define mmDAGB2_RDCLI2_BASE_IDX                                                                        1
>+#define mmDAGB2_RDCLI3                                                                                 0x0103
>+#define mmDAGB2_RDCLI3_BASE_IDX                                                                        1
>+#define mmDAGB2_RDCLI4                                                                                 0x0104
>+#define mmDAGB2_RDCLI4_BASE_IDX                                                                        1
>+#define mmDAGB2_RDCLI5                                                                                 0x0105
>+#define mmDAGB2_RDCLI5_BASE_IDX                                                                        1
>+#define mmDAGB2_RDCLI6                                                                                 0x0106
>+#define mmDAGB2_RDCLI6_BASE_IDX                                                                        1
>+#define mmDAGB2_RDCLI7                                                                                 0x0107
>+#define mmDAGB2_RDCLI7_BASE_IDX                                                                        1
>+#define mmDAGB2_RDCLI8                                                                                 0x0108
>+#define mmDAGB2_RDCLI8_BASE_IDX                                                                        1
>+#define mmDAGB2_RDCLI9                                                                                 0x0109
>+#define mmDAGB2_RDCLI9_BASE_IDX                                                                        1
>+#define mmDAGB2_RDCLI10                                                                                0x010a
>+#define mmDAGB2_RDCLI10_BASE_IDX                                                                       1
>+#define mmDAGB2_RDCLI11                                                                                0x010b
>+#define mmDAGB2_RDCLI11_BASE_IDX                                                                       1
>+#define mmDAGB2_RDCLI12                                                                                0x010c
>+#define mmDAGB2_RDCLI12_BASE_IDX                                                                       1
>+#define mmDAGB2_RDCLI13                                                                                0x010d
>+#define mmDAGB2_RDCLI13_BASE_IDX                                                                       1
>+#define mmDAGB2_RDCLI14                                                                                0x010e
>+#define mmDAGB2_RDCLI14_BASE_IDX                                                                       1
>+#define mmDAGB2_RDCLI15                                                                                0x010f
>+#define mmDAGB2_RDCLI15_BASE_IDX                                                                       1
>+#define mmDAGB2_RD_CNTL                                                                                0x0110
>+#define mmDAGB2_RD_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB2_RD_GMI_CNTL                                                                            0x0111
>+#define mmDAGB2_RD_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_RD_ADDR_DAGB                                                                           0x0112
>+#define mmDAGB2_RD_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST                                                               0x0113
>+#define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER                                                              0x0114
>+#define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB2_RD_CGTT_CLK_CTRL                                                                       0x0115
>+#define mmDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL                                                                 0x0116
>+#define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL                                                                 0x0117
>+#define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0                                                                0x0118
>+#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0                                                               0x0119
>+#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1                                                                0x011a
>+#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1                                                               0x011b
>+#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB2_RD_VC0_CNTL                                                                            0x011c
>+#define mmDAGB2_RD_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_RD_VC1_CNTL                                                                            0x011d
>+#define mmDAGB2_RD_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_RD_VC2_CNTL                                                                            0x011e
>+#define mmDAGB2_RD_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_RD_VC3_CNTL                                                                            0x011f
>+#define mmDAGB2_RD_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_RD_VC4_CNTL                                                                            0x0120
>+#define mmDAGB2_RD_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_RD_VC5_CNTL                                                                            0x0121
>+#define mmDAGB2_RD_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_RD_VC6_CNTL                                                                            0x0122
>+#define mmDAGB2_RD_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_RD_VC7_CNTL                                                                            0x0123
>+#define mmDAGB2_RD_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_RD_CNTL_MISC                                                                           0x0124
>+#define mmDAGB2_RD_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB2_RD_TLB_CREDIT                                                                          0x0125
>+#define mmDAGB2_RD_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB2_RDCLI_ASK_PENDING                                                                      0x0126
>+#define mmDAGB2_RDCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB2_RDCLI_GO_PENDING                                                                       0x0127
>+#define mmDAGB2_RDCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB2_RDCLI_GBLSEND_PENDING                                                                  0x0128
>+#define mmDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB2_RDCLI_TLB_PENDING                                                                      0x0129
>+#define mmDAGB2_RDCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB2_RDCLI_OARB_PENDING                                                                     0x012a
>+#define mmDAGB2_RDCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB2_RDCLI_OSD_PENDING                                                                      0x012b
>+#define mmDAGB2_RDCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB2_WRCLI0                                                                                 0x012c
>+#define mmDAGB2_WRCLI0_BASE_IDX                                                                        1
>+#define mmDAGB2_WRCLI1                                                                                 0x012d
>+#define mmDAGB2_WRCLI1_BASE_IDX                                                                        1
>+#define mmDAGB2_WRCLI2                                                                                 0x012e
>+#define mmDAGB2_WRCLI2_BASE_IDX                                                                        1
>+#define mmDAGB2_WRCLI3                                                                                 0x012f
>+#define mmDAGB2_WRCLI3_BASE_IDX                                                                        1
>+#define mmDAGB2_WRCLI4                                                                                 0x0130
>+#define mmDAGB2_WRCLI4_BASE_IDX                                                                        1
>+#define mmDAGB2_WRCLI5                                                                                 0x0131
>+#define mmDAGB2_WRCLI5_BASE_IDX                                                                        1
>+#define mmDAGB2_WRCLI6                                                                                 0x0132
>+#define mmDAGB2_WRCLI6_BASE_IDX                                                                        1
>+#define mmDAGB2_WRCLI7                                                                                 0x0133
>+#define mmDAGB2_WRCLI7_BASE_IDX                                                                        1
>+#define mmDAGB2_WRCLI8                                                                                 0x0134
>+#define mmDAGB2_WRCLI8_BASE_IDX                                                                        1
>+#define mmDAGB2_WRCLI9                                                                                 0x0135
>+#define mmDAGB2_WRCLI9_BASE_IDX                                                                        1
>+#define mmDAGB2_WRCLI10                                                                                0x0136
>+#define mmDAGB2_WRCLI10_BASE_IDX                                                                       1
>+#define mmDAGB2_WRCLI11                                                                                0x0137
>+#define mmDAGB2_WRCLI11_BASE_IDX                                                                       1
>+#define mmDAGB2_WRCLI12                                                                                0x0138
>+#define mmDAGB2_WRCLI12_BASE_IDX                                                                       1
>+#define mmDAGB2_WRCLI13                                                                                0x0139
>+#define mmDAGB2_WRCLI13_BASE_IDX                                                                       1
>+#define mmDAGB2_WRCLI14                                                                                0x013a
>+#define mmDAGB2_WRCLI14_BASE_IDX                                                                       1
>+#define mmDAGB2_WRCLI15                                                                                0x013b
>+#define mmDAGB2_WRCLI15_BASE_IDX                                                                       1
>+#define mmDAGB2_WR_CNTL                                                                                0x013c
>+#define mmDAGB2_WR_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB2_WR_GMI_CNTL                                                                            0x013d
>+#define mmDAGB2_WR_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_WR_ADDR_DAGB                                                                           0x013e
>+#define mmDAGB2_WR_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST                                                               0x013f
>+#define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER                                                              0x0140
>+#define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB2_WR_CGTT_CLK_CTRL                                                                       0x0141
>+#define mmDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL                                                                 0x0142
>+#define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL                                                                 0x0143
>+#define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0                                                                0x0144
>+#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0                                                               0x0145
>+#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1                                                                0x0146
>+#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1                                                               0x0147
>+#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB2_WR_DATA_DAGB                                                                           0x0148
>+#define mmDAGB2_WR_DATA_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB2_WR_DATA_DAGB_MAX_BURST0                                                                0x0149
>+#define mmDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0                                                               0x014a
>+#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB2_WR_DATA_DAGB_MAX_BURST1                                                                0x014b
>+#define mmDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1                                                               0x014c
>+#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB2_WR_VC0_CNTL                                                                            0x014d
>+#define mmDAGB2_WR_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_WR_VC1_CNTL                                                                            0x014e
>+#define mmDAGB2_WR_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_WR_VC2_CNTL                                                                            0x014f
>+#define mmDAGB2_WR_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_WR_VC3_CNTL                                                                            0x0150
>+#define mmDAGB2_WR_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_WR_VC4_CNTL                                                                            0x0151
>+#define mmDAGB2_WR_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_WR_VC5_CNTL                                                                            0x0152
>+#define mmDAGB2_WR_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_WR_VC6_CNTL                                                                            0x0153
>+#define mmDAGB2_WR_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_WR_VC7_CNTL                                                                            0x0154
>+#define mmDAGB2_WR_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB2_WR_CNTL_MISC                                                                           0x0155
>+#define mmDAGB2_WR_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB2_WR_TLB_CREDIT                                                                          0x0156
>+#define mmDAGB2_WR_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB2_WR_DATA_CREDIT                                                                         0x0157
>+#define mmDAGB2_WR_DATA_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB2_WR_MISC_CREDIT                                                                         0x0158
>+#define mmDAGB2_WR_MISC_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB2_WRCLI_ASK_PENDING                                                                      0x015d
>+#define mmDAGB2_WRCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB2_WRCLI_GO_PENDING                                                                       0x015e
>+#define mmDAGB2_WRCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB2_WRCLI_GBLSEND_PENDING                                                                  0x015f
>+#define mmDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB2_WRCLI_TLB_PENDING                                                                      0x0160
>+#define mmDAGB2_WRCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB2_WRCLI_OARB_PENDING                                                                     0x0161
>+#define mmDAGB2_WRCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB2_WRCLI_OSD_PENDING                                                                      0x0162
>+#define mmDAGB2_WRCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB2_WRCLI_DBUS_ASK_PENDING                                                                 0x0163
>+#define mmDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX                                                        1
>+#define mmDAGB2_WRCLI_DBUS_GO_PENDING                                                                  0x0164
>+#define mmDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX                                                         1
>+#define mmDAGB2_DAGB_DLY                                                                               0x0165
>+#define mmDAGB2_DAGB_DLY_BASE_IDX                                                                      1
>+#define mmDAGB2_CNTL_MISC                                                                              0x0166
>+#define mmDAGB2_CNTL_MISC_BASE_IDX                                                                     1
>+#define mmDAGB2_CNTL_MISC2                                                                             0x0167
>+#define mmDAGB2_CNTL_MISC2_BASE_IDX                                                                    1
>+#define mmDAGB2_FIFO_EMPTY                                                                             0x0168
>+#define mmDAGB2_FIFO_EMPTY_BASE_IDX                                                                    1
>+#define mmDAGB2_FIFO_FULL                                                                              0x0169
>+#define mmDAGB2_FIFO_FULL_BASE_IDX                                                                     1
>+#define mmDAGB2_WR_CREDITS_FULL                                                                        0x016a
>+#define mmDAGB2_WR_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB2_RD_CREDITS_FULL                                                                        0x016b
>+#define mmDAGB2_RD_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB2_PERFCOUNTER_LO                                                                         0x016c
>+#define mmDAGB2_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmDAGB2_PERFCOUNTER_HI                                                                         0x016d
>+#define mmDAGB2_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmDAGB2_PERFCOUNTER0_CFG                                                                       0x016e
>+#define mmDAGB2_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmDAGB2_PERFCOUNTER1_CFG                                                                       0x016f
>+#define mmDAGB2_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmDAGB2_PERFCOUNTER2_CFG                                                                       0x0170
>+#define mmDAGB2_PERFCOUNTER2_CFG_BASE_IDX                                                              1
>+#define mmDAGB2_PERFCOUNTER_RSLT_CNTL                                                                  0x0171
>+#define mmDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmDAGB2_RESERVE0                                                                               0x0172
>+#define mmDAGB2_RESERVE0_BASE_IDX                                                                      1
>+#define mmDAGB2_RESERVE1                                                                               0x0173
>+#define mmDAGB2_RESERVE1_BASE_IDX                                                                      1
>+#define mmDAGB2_RESERVE2                                                                               0x0174
>+#define mmDAGB2_RESERVE2_BASE_IDX                                                                      1
>+#define mmDAGB2_RESERVE3                                                                               0x0175
>+#define mmDAGB2_RESERVE3_BASE_IDX                                                                      1
>+#define mmDAGB2_RESERVE4                                                                               0x0176
>+#define mmDAGB2_RESERVE4_BASE_IDX                                                                      1
>+#define mmDAGB2_RESERVE5                                                                               0x0177
>+#define mmDAGB2_RESERVE5_BASE_IDX                                                                      1
>+#define mmDAGB2_RESERVE6                                                                               0x0178
>+#define mmDAGB2_RESERVE6_BASE_IDX                                                                      1
>+#define mmDAGB2_RESERVE7                                                                               0x0179
>+#define mmDAGB2_RESERVE7_BASE_IDX                                                                      1
>+#define mmDAGB2_RESERVE8                                                                               0x017a
>+#define mmDAGB2_RESERVE8_BASE_IDX                                                                      1
>+#define mmDAGB2_RESERVE9                                                                               0x017b
>+#define mmDAGB2_RESERVE9_BASE_IDX                                                                      1
>+#define mmDAGB2_RESERVE10                                                                              0x017c
>+#define mmDAGB2_RESERVE10_BASE_IDX                                                                     1
>+#define mmDAGB2_RESERVE11                                                                              0x017d
>+#define mmDAGB2_RESERVE11_BASE_IDX                                                                     1
>+#define mmDAGB2_RESERVE12                                                                              0x017e
>+#define mmDAGB2_RESERVE12_BASE_IDX                                                                     1
>+#define mmDAGB2_RESERVE13                                                                              0x017f
>+#define mmDAGB2_RESERVE13_BASE_IDX                                                                     1
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec3
>+// base address: 0x68600
>+#define mmDAGB3_RDCLI0                                                                                 0x0180
>+#define mmDAGB3_RDCLI0_BASE_IDX                                                                        1
>+#define mmDAGB3_RDCLI1                                                                                 0x0181
>+#define mmDAGB3_RDCLI1_BASE_IDX                                                                        1
>+#define mmDAGB3_RDCLI2                                                                                 0x0182
>+#define mmDAGB3_RDCLI2_BASE_IDX                                                                        1
>+#define mmDAGB3_RDCLI3                                                                                 0x0183
>+#define mmDAGB3_RDCLI3_BASE_IDX                                                                        1
>+#define mmDAGB3_RDCLI4                                                                                 0x0184
>+#define mmDAGB3_RDCLI4_BASE_IDX                                                                        1
>+#define mmDAGB3_RDCLI5                                                                                 0x0185
>+#define mmDAGB3_RDCLI5_BASE_IDX                                                                        1
>+#define mmDAGB3_RDCLI6                                                                                 0x0186
>+#define mmDAGB3_RDCLI6_BASE_IDX                                                                        1
>+#define mmDAGB3_RDCLI7                                                                                 0x0187
>+#define mmDAGB3_RDCLI7_BASE_IDX                                                                        1
>+#define mmDAGB3_RDCLI8                                                                                 0x0188
>+#define mmDAGB3_RDCLI8_BASE_IDX                                                                        1
>+#define mmDAGB3_RDCLI9                                                                                 0x0189
>+#define mmDAGB3_RDCLI9_BASE_IDX                                                                        1
>+#define mmDAGB3_RDCLI10                                                                                0x018a
>+#define mmDAGB3_RDCLI10_BASE_IDX                                                                       1
>+#define mmDAGB3_RDCLI11                                                                                0x018b
>+#define mmDAGB3_RDCLI11_BASE_IDX                                                                       1
>+#define mmDAGB3_RDCLI12                                                                                0x018c
>+#define mmDAGB3_RDCLI12_BASE_IDX                                                                       1
>+#define mmDAGB3_RDCLI13                                                                                0x018d
>+#define mmDAGB3_RDCLI13_BASE_IDX                                                                       1
>+#define mmDAGB3_RDCLI14                                                                                0x018e
>+#define mmDAGB3_RDCLI14_BASE_IDX                                                                       1
>+#define mmDAGB3_RDCLI15                                                                                0x018f
>+#define mmDAGB3_RDCLI15_BASE_IDX                                                                       1
>+#define mmDAGB3_RD_CNTL                                                                                0x0190
>+#define mmDAGB3_RD_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB3_RD_GMI_CNTL                                                                            0x0191
>+#define mmDAGB3_RD_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_RD_ADDR_DAGB                                                                           0x0192
>+#define mmDAGB3_RD_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST                                                               0x0193
>+#define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER                                                              0x0194
>+#define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB3_RD_CGTT_CLK_CTRL                                                                       0x0195
>+#define mmDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL                                                                 0x0196
>+#define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL                                                                 0x0197
>+#define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0                                                                0x0198
>+#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0                                                               0x0199
>+#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1                                                                0x019a
>+#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1                                                               0x019b
>+#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB3_RD_VC0_CNTL                                                                            0x019c
>+#define mmDAGB3_RD_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_RD_VC1_CNTL                                                                            0x019d
>+#define mmDAGB3_RD_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_RD_VC2_CNTL                                                                            0x019e
>+#define mmDAGB3_RD_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_RD_VC3_CNTL                                                                            0x019f
>+#define mmDAGB3_RD_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_RD_VC4_CNTL                                                                            0x01a0
>+#define mmDAGB3_RD_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_RD_VC5_CNTL                                                                            0x01a1
>+#define mmDAGB3_RD_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_RD_VC6_CNTL                                                                            0x01a2
>+#define mmDAGB3_RD_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_RD_VC7_CNTL                                                                            0x01a3
>+#define mmDAGB3_RD_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_RD_CNTL_MISC                                                                           0x01a4
>+#define mmDAGB3_RD_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB3_RD_TLB_CREDIT                                                                          0x01a5
>+#define mmDAGB3_RD_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB3_RDCLI_ASK_PENDING                                                                      0x01a6
>+#define mmDAGB3_RDCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB3_RDCLI_GO_PENDING                                                                       0x01a7
>+#define mmDAGB3_RDCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB3_RDCLI_GBLSEND_PENDING                                                                  0x01a8
>+#define mmDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB3_RDCLI_TLB_PENDING                                                                      0x01a9
>+#define mmDAGB3_RDCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB3_RDCLI_OARB_PENDING                                                                     0x01aa
>+#define mmDAGB3_RDCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB3_RDCLI_OSD_PENDING                                                                      0x01ab
>+#define mmDAGB3_RDCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB3_WRCLI0                                                                                 0x01ac
>+#define mmDAGB3_WRCLI0_BASE_IDX                                                                        1
>+#define mmDAGB3_WRCLI1                                                                                 0x01ad
>+#define mmDAGB3_WRCLI1_BASE_IDX                                                                        1
>+#define mmDAGB3_WRCLI2                                                                                 0x01ae
>+#define mmDAGB3_WRCLI2_BASE_IDX                                                                        1
>+#define mmDAGB3_WRCLI3                                                                                 0x01af
>+#define mmDAGB3_WRCLI3_BASE_IDX                                                                        1
>+#define mmDAGB3_WRCLI4                                                                                 0x01b0
>+#define mmDAGB3_WRCLI4_BASE_IDX                                                                        1
>+#define mmDAGB3_WRCLI5                                                                                 0x01b1
>+#define mmDAGB3_WRCLI5_BASE_IDX                                                                        1
>+#define mmDAGB3_WRCLI6                                                                                 0x01b2
>+#define mmDAGB3_WRCLI6_BASE_IDX                                                                        1
>+#define mmDAGB3_WRCLI7                                                                                 0x01b3
>+#define mmDAGB3_WRCLI7_BASE_IDX                                                                        1
>+#define mmDAGB3_WRCLI8                                                                                 0x01b4
>+#define mmDAGB3_WRCLI8_BASE_IDX                                                                        1
>+#define mmDAGB3_WRCLI9                                                                                 0x01b5
>+#define mmDAGB3_WRCLI9_BASE_IDX                                                                        1
>+#define mmDAGB3_WRCLI10                                                                                0x01b6
>+#define mmDAGB3_WRCLI10_BASE_IDX                                                                       1
>+#define mmDAGB3_WRCLI11                                                                                0x01b7
>+#define mmDAGB3_WRCLI11_BASE_IDX                                                                       1
>+#define mmDAGB3_WRCLI12                                                                                0x01b8
>+#define mmDAGB3_WRCLI12_BASE_IDX                                                                       1
>+#define mmDAGB3_WRCLI13                                                                                0x01b9
>+#define mmDAGB3_WRCLI13_BASE_IDX                                                                       1
>+#define mmDAGB3_WRCLI14                                                                                0x01ba
>+#define mmDAGB3_WRCLI14_BASE_IDX                                                                       1
>+#define mmDAGB3_WRCLI15                                                                                0x01bb
>+#define mmDAGB3_WRCLI15_BASE_IDX                                                                       1
>+#define mmDAGB3_WR_CNTL                                                                                0x01bc
>+#define mmDAGB3_WR_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB3_WR_GMI_CNTL                                                                            0x01bd
>+#define mmDAGB3_WR_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_WR_ADDR_DAGB                                                                           0x01be
>+#define mmDAGB3_WR_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST                                                               0x01bf
>+#define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER                                                              0x01c0
>+#define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB3_WR_CGTT_CLK_CTRL                                                                       0x01c1
>+#define mmDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL                                                                 0x01c2
>+#define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL                                                                 0x01c3
>+#define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0                                                                0x01c4
>+#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0                                                               0x01c5
>+#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1                                                                0x01c6
>+#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1                                                               0x01c7
>+#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB3_WR_DATA_DAGB                                                                           0x01c8
>+#define mmDAGB3_WR_DATA_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB3_WR_DATA_DAGB_MAX_BURST0                                                                0x01c9
>+#define mmDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0                                                               0x01ca
>+#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB3_WR_DATA_DAGB_MAX_BURST1                                                                0x01cb
>+#define mmDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1                                                               0x01cc
>+#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB3_WR_VC0_CNTL                                                                            0x01cd
>+#define mmDAGB3_WR_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_WR_VC1_CNTL                                                                            0x01ce
>+#define mmDAGB3_WR_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_WR_VC2_CNTL                                                                            0x01cf
>+#define mmDAGB3_WR_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_WR_VC3_CNTL                                                                            0x01d0
>+#define mmDAGB3_WR_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_WR_VC4_CNTL                                                                            0x01d1
>+#define mmDAGB3_WR_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_WR_VC5_CNTL                                                                            0x01d2
>+#define mmDAGB3_WR_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_WR_VC6_CNTL                                                                            0x01d3
>+#define mmDAGB3_WR_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_WR_VC7_CNTL                                                                            0x01d4
>+#define mmDAGB3_WR_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB3_WR_CNTL_MISC                                                                           0x01d5
>+#define mmDAGB3_WR_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB3_WR_TLB_CREDIT                                                                          0x01d6
>+#define mmDAGB3_WR_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB3_WR_DATA_CREDIT                                                                         0x01d7
>+#define mmDAGB3_WR_DATA_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB3_WR_MISC_CREDIT                                                                         0x01d8
>+#define mmDAGB3_WR_MISC_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB3_WRCLI_ASK_PENDING                                                                      0x01dd
>+#define mmDAGB3_WRCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB3_WRCLI_GO_PENDING                                                                       0x01de
>+#define mmDAGB3_WRCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB3_WRCLI_GBLSEND_PENDING                                                                  0x01df
>+#define mmDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB3_WRCLI_TLB_PENDING                                                                      0x01e0
>+#define mmDAGB3_WRCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB3_WRCLI_OARB_PENDING                                                                     0x01e1
>+#define mmDAGB3_WRCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB3_WRCLI_OSD_PENDING                                                                      0x01e2
>+#define mmDAGB3_WRCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB3_WRCLI_DBUS_ASK_PENDING                                                                 0x01e3
>+#define mmDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX                                                        1
>+#define mmDAGB3_WRCLI_DBUS_GO_PENDING                                                                  0x01e4
>+#define mmDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX                                                         1
>+#define mmDAGB3_DAGB_DLY                                                                               0x01e5
>+#define mmDAGB3_DAGB_DLY_BASE_IDX                                                                      1
>+#define mmDAGB3_CNTL_MISC                                                                              0x01e6
>+#define mmDAGB3_CNTL_MISC_BASE_IDX                                                                     1
>+#define mmDAGB3_CNTL_MISC2                                                                             0x01e7
>+#define mmDAGB3_CNTL_MISC2_BASE_IDX                                                                    1
>+#define mmDAGB3_FIFO_EMPTY                                                                             0x01e8
>+#define mmDAGB3_FIFO_EMPTY_BASE_IDX                                                                    1
>+#define mmDAGB3_FIFO_FULL                                                                              0x01e9
>+#define mmDAGB3_FIFO_FULL_BASE_IDX                                                                     1
>+#define mmDAGB3_WR_CREDITS_FULL                                                                        0x01ea
>+#define mmDAGB3_WR_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB3_RD_CREDITS_FULL                                                                        0x01eb
>+#define mmDAGB3_RD_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB3_PERFCOUNTER_LO                                                                         0x01ec
>+#define mmDAGB3_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmDAGB3_PERFCOUNTER_HI                                                                         0x01ed
>+#define mmDAGB3_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmDAGB3_PERFCOUNTER0_CFG                                                                       0x01ee
>+#define mmDAGB3_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmDAGB3_PERFCOUNTER1_CFG                                                                       0x01ef
>+#define mmDAGB3_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmDAGB3_PERFCOUNTER2_CFG                                                                       0x01f0
>+#define mmDAGB3_PERFCOUNTER2_CFG_BASE_IDX                                                              1
>+#define mmDAGB3_PERFCOUNTER_RSLT_CNTL                                                                  0x01f1
>+#define mmDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmDAGB3_RESERVE0                                                                               0x01f2
>+#define mmDAGB3_RESERVE0_BASE_IDX                                                                      1
>+#define mmDAGB3_RESERVE1                                                                               0x01f3
>+#define mmDAGB3_RESERVE1_BASE_IDX                                                                      1
>+#define mmDAGB3_RESERVE2                                                                               0x01f4
>+#define mmDAGB3_RESERVE2_BASE_IDX                                                                      1
>+#define mmDAGB3_RESERVE3                                                                               0x01f5
>+#define mmDAGB3_RESERVE3_BASE_IDX                                                                      1
>+#define mmDAGB3_RESERVE4                                                                               0x01f6
>+#define mmDAGB3_RESERVE4_BASE_IDX                                                                      1
>+#define mmDAGB3_RESERVE5                                                                               0x01f7
>+#define mmDAGB3_RESERVE5_BASE_IDX                                                                      1
>+#define mmDAGB3_RESERVE6                                                                               0x01f8
>+#define mmDAGB3_RESERVE6_BASE_IDX                                                                      1
>+#define mmDAGB3_RESERVE7                                                                               0x01f9
>+#define mmDAGB3_RESERVE7_BASE_IDX                                                                      1
>+#define mmDAGB3_RESERVE8                                                                               0x01fa
>+#define mmDAGB3_RESERVE8_BASE_IDX                                                                      1
>+#define mmDAGB3_RESERVE9                                                                               0x01fb
>+#define mmDAGB3_RESERVE9_BASE_IDX                                                                      1
>+#define mmDAGB3_RESERVE10                                                                              0x01fc
>+#define mmDAGB3_RESERVE10_BASE_IDX                                                                     1
>+#define mmDAGB3_RESERVE11                                                                              0x01fd
>+#define mmDAGB3_RESERVE11_BASE_IDX                                                                     1
>+#define mmDAGB3_RESERVE12                                                                              0x01fe
>+#define mmDAGB3_RESERVE12_BASE_IDX                                                                     1
>+#define mmDAGB3_RESERVE13                                                                              0x01ff
>+#define mmDAGB3_RESERVE13_BASE_IDX                                                                     1
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec4
>+// base address: 0x68800
>+#define mmDAGB4_RDCLI0                                                                                 0x0200
>+#define mmDAGB4_RDCLI0_BASE_IDX                                                                        1
>+#define mmDAGB4_RDCLI1                                                                                 0x0201
>+#define mmDAGB4_RDCLI1_BASE_IDX                                                                        1
>+#define mmDAGB4_RDCLI2                                                                                 0x0202
>+#define mmDAGB4_RDCLI2_BASE_IDX                                                                        1
>+#define mmDAGB4_RDCLI3                                                                                 0x0203
>+#define mmDAGB4_RDCLI3_BASE_IDX                                                                        1
>+#define mmDAGB4_RDCLI4                                                                                 0x0204
>+#define mmDAGB4_RDCLI4_BASE_IDX                                                                        1
>+#define mmDAGB4_RDCLI5                                                                                 0x0205
>+#define mmDAGB4_RDCLI5_BASE_IDX                                                                        1
>+#define mmDAGB4_RDCLI6                                                                                 0x0206
>+#define mmDAGB4_RDCLI6_BASE_IDX                                                                        1
>+#define mmDAGB4_RDCLI7                                                                                 0x0207
>+#define mmDAGB4_RDCLI7_BASE_IDX                                                                        1
>+#define mmDAGB4_RDCLI8                                                                                 0x0208
>+#define mmDAGB4_RDCLI8_BASE_IDX                                                                        1
>+#define mmDAGB4_RDCLI9                                                                                 0x0209
>+#define mmDAGB4_RDCLI9_BASE_IDX                                                                        1
>+#define mmDAGB4_RDCLI10                                                                                0x020a
>+#define mmDAGB4_RDCLI10_BASE_IDX                                                                       1
>+#define mmDAGB4_RDCLI11                                                                                0x020b
>+#define mmDAGB4_RDCLI11_BASE_IDX                                                                       1
>+#define mmDAGB4_RDCLI12                                                                                0x020c
>+#define mmDAGB4_RDCLI12_BASE_IDX                                                                       1
>+#define mmDAGB4_RDCLI13                                                                                0x020d
>+#define mmDAGB4_RDCLI13_BASE_IDX                                                                       1
>+#define mmDAGB4_RDCLI14                                                                                0x020e
>+#define mmDAGB4_RDCLI14_BASE_IDX                                                                       1
>+#define mmDAGB4_RDCLI15                                                                                0x020f
>+#define mmDAGB4_RDCLI15_BASE_IDX                                                                       1
>+#define mmDAGB4_RD_CNTL                                                                                0x0210
>+#define mmDAGB4_RD_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB4_RD_GMI_CNTL                                                                            0x0211
>+#define mmDAGB4_RD_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_RD_ADDR_DAGB                                                                           0x0212
>+#define mmDAGB4_RD_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST                                                               0x0213
>+#define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER                                                              0x0214
>+#define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB4_RD_CGTT_CLK_CTRL                                                                       0x0215
>+#define mmDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL                                                                 0x0216
>+#define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL                                                                 0x0217
>+#define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0                                                                0x0218
>+#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0                                                               0x0219
>+#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1                                                                0x021a
>+#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1                                                               0x021b
>+#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB4_RD_VC0_CNTL                                                                            0x021c
>+#define mmDAGB4_RD_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_RD_VC1_CNTL                                                                            0x021d
>+#define mmDAGB4_RD_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_RD_VC2_CNTL                                                                            0x021e
>+#define mmDAGB4_RD_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_RD_VC3_CNTL                                                                            0x021f
>+#define mmDAGB4_RD_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_RD_VC4_CNTL                                                                            0x0220
>+#define mmDAGB4_RD_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_RD_VC5_CNTL                                                                            0x0221
>+#define mmDAGB4_RD_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_RD_VC6_CNTL                                                                            0x0222
>+#define mmDAGB4_RD_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_RD_VC7_CNTL                                                                            0x0223
>+#define mmDAGB4_RD_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_RD_CNTL_MISC                                                                           0x0224
>+#define mmDAGB4_RD_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB4_RD_TLB_CREDIT                                                                          0x0225
>+#define mmDAGB4_RD_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB4_RDCLI_ASK_PENDING                                                                      0x0226
>+#define mmDAGB4_RDCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB4_RDCLI_GO_PENDING                                                                       0x0227
>+#define mmDAGB4_RDCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB4_RDCLI_GBLSEND_PENDING                                                                  0x0228
>+#define mmDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB4_RDCLI_TLB_PENDING                                                                      0x0229
>+#define mmDAGB4_RDCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB4_RDCLI_OARB_PENDING                                                                     0x022a
>+#define mmDAGB4_RDCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB4_RDCLI_OSD_PENDING                                                                      0x022b
>+#define mmDAGB4_RDCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB4_WRCLI0                                                                                 0x022c
>+#define mmDAGB4_WRCLI0_BASE_IDX                                                                        1
>+#define mmDAGB4_WRCLI1                                                                                 0x022d
>+#define mmDAGB4_WRCLI1_BASE_IDX                                                                        1
>+#define mmDAGB4_WRCLI2                                                                                 0x022e
>+#define mmDAGB4_WRCLI2_BASE_IDX                                                                        1
>+#define mmDAGB4_WRCLI3                                                                                 0x022f
>+#define mmDAGB4_WRCLI3_BASE_IDX                                                                        1
>+#define mmDAGB4_WRCLI4                                                                                 0x0230
>+#define mmDAGB4_WRCLI4_BASE_IDX                                                                        1
>+#define mmDAGB4_WRCLI5                                                                                 0x0231
>+#define mmDAGB4_WRCLI5_BASE_IDX                                                                        1
>+#define mmDAGB4_WRCLI6                                                                                 0x0232
>+#define mmDAGB4_WRCLI6_BASE_IDX                                                                        1
>+#define mmDAGB4_WRCLI7                                                                                 0x0233
>+#define mmDAGB4_WRCLI7_BASE_IDX                                                                        1
>+#define mmDAGB4_WRCLI8                                                                                 0x0234
>+#define mmDAGB4_WRCLI8_BASE_IDX                                                                        1
>+#define mmDAGB4_WRCLI9                                                                                 0x0235
>+#define mmDAGB4_WRCLI9_BASE_IDX                                                                        1
>+#define mmDAGB4_WRCLI10                                                                                0x0236
>+#define mmDAGB4_WRCLI10_BASE_IDX                                                                       1
>+#define mmDAGB4_WRCLI11                                                                                0x0237
>+#define mmDAGB4_WRCLI11_BASE_IDX                                                                       1
>+#define mmDAGB4_WRCLI12                                                                                0x0238
>+#define mmDAGB4_WRCLI12_BASE_IDX                                                                       1
>+#define mmDAGB4_WRCLI13                                                                                0x0239
>+#define mmDAGB4_WRCLI13_BASE_IDX                                                                       1
>+#define mmDAGB4_WRCLI14                                                                                0x023a
>+#define mmDAGB4_WRCLI14_BASE_IDX                                                                       1
>+#define mmDAGB4_WRCLI15                                                                                0x023b
>+#define mmDAGB4_WRCLI15_BASE_IDX                                                                       1
>+#define mmDAGB4_WR_CNTL                                                                                0x023c
>+#define mmDAGB4_WR_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB4_WR_GMI_CNTL                                                                            0x023d
>+#define mmDAGB4_WR_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_WR_ADDR_DAGB                                                                           0x023e
>+#define mmDAGB4_WR_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST                                                               0x023f
>+#define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER                                                              0x0240
>+#define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB4_WR_CGTT_CLK_CTRL                                                                       0x0241
>+#define mmDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL                                                                 0x0242
>+#define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL                                                                 0x0243
>+#define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0                                                                0x0244
>+#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0                                                               0x0245
>+#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1                                                                0x0246
>+#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1                                                               0x0247
>+#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB4_WR_DATA_DAGB                                                                           0x0248
>+#define mmDAGB4_WR_DATA_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB4_WR_DATA_DAGB_MAX_BURST0                                                                0x0249
>+#define mmDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0                                                               0x024a
>+#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB4_WR_DATA_DAGB_MAX_BURST1                                                                0x024b
>+#define mmDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1                                                               0x024c
>+#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB4_WR_VC0_CNTL                                                                            0x024d
>+#define mmDAGB4_WR_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_WR_VC1_CNTL                                                                            0x024e
>+#define mmDAGB4_WR_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_WR_VC2_CNTL                                                                            0x024f
>+#define mmDAGB4_WR_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_WR_VC3_CNTL                                                                            0x0250
>+#define mmDAGB4_WR_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_WR_VC4_CNTL                                                                            0x0251
>+#define mmDAGB4_WR_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_WR_VC5_CNTL                                                                            0x0252
>+#define mmDAGB4_WR_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_WR_VC6_CNTL                                                                            0x0253
>+#define mmDAGB4_WR_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_WR_VC7_CNTL                                                                            0x0254
>+#define mmDAGB4_WR_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB4_WR_CNTL_MISC                                                                           0x0255
>+#define mmDAGB4_WR_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB4_WR_TLB_CREDIT                                                                          0x0256
>+#define mmDAGB4_WR_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB4_WR_DATA_CREDIT                                                                         0x0257
>+#define mmDAGB4_WR_DATA_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB4_WR_MISC_CREDIT                                                                         0x0258
>+#define mmDAGB4_WR_MISC_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB4_WRCLI_ASK_PENDING                                                                      0x025d
>+#define mmDAGB4_WRCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB4_WRCLI_GO_PENDING                                                                       0x025e
>+#define mmDAGB4_WRCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB4_WRCLI_GBLSEND_PENDING                                                                  0x025f
>+#define mmDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB4_WRCLI_TLB_PENDING                                                                      0x0260
>+#define mmDAGB4_WRCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB4_WRCLI_OARB_PENDING                                                                     0x0261
>+#define mmDAGB4_WRCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB4_WRCLI_OSD_PENDING                                                                      0x0262
>+#define mmDAGB4_WRCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB4_WRCLI_DBUS_ASK_PENDING                                                                 0x0263
>+#define mmDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX                                                        1
>+#define mmDAGB4_WRCLI_DBUS_GO_PENDING                                                                  0x0264
>+#define mmDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX                                                         1
>+#define mmDAGB4_DAGB_DLY                                                                               0x0265
>+#define mmDAGB4_DAGB_DLY_BASE_IDX                                                                      1
>+#define mmDAGB4_CNTL_MISC                                                                              0x0266
>+#define mmDAGB4_CNTL_MISC_BASE_IDX                                                                     1
>+#define mmDAGB4_CNTL_MISC2                                                                             0x0267
>+#define mmDAGB4_CNTL_MISC2_BASE_IDX                                                                    1
>+#define mmDAGB4_FIFO_EMPTY                                                                             0x0268
>+#define mmDAGB4_FIFO_EMPTY_BASE_IDX                                                                    1
>+#define mmDAGB4_FIFO_FULL                                                                              0x0269
>+#define mmDAGB4_FIFO_FULL_BASE_IDX                                                                     1
>+#define mmDAGB4_WR_CREDITS_FULL                                                                        0x026a
>+#define mmDAGB4_WR_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB4_RD_CREDITS_FULL                                                                        0x026b
>+#define mmDAGB4_RD_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB4_PERFCOUNTER_LO                                                                         0x026c
>+#define mmDAGB4_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmDAGB4_PERFCOUNTER_HI                                                                         0x026d
>+#define mmDAGB4_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmDAGB4_PERFCOUNTER0_CFG                                                                       0x026e
>+#define mmDAGB4_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmDAGB4_PERFCOUNTER1_CFG                                                                       0x026f
>+#define mmDAGB4_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmDAGB4_PERFCOUNTER2_CFG                                                                       0x0270
>+#define mmDAGB4_PERFCOUNTER2_CFG_BASE_IDX                                                              1
>+#define mmDAGB4_PERFCOUNTER_RSLT_CNTL                                                                  0x0271
>+#define mmDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmDAGB4_RESERVE0                                                                               0x0272
>+#define mmDAGB4_RESERVE0_BASE_IDX                                                                      1
>+#define mmDAGB4_RESERVE1                                                                               0x0273
>+#define mmDAGB4_RESERVE1_BASE_IDX                                                                      1
>+#define mmDAGB4_RESERVE2                                                                               0x0274
>+#define mmDAGB4_RESERVE2_BASE_IDX                                                                      1
>+#define mmDAGB4_RESERVE3                                                                               0x0275
>+#define mmDAGB4_RESERVE3_BASE_IDX                                                                      1
>+#define mmDAGB4_RESERVE4                                                                               0x0276
>+#define mmDAGB4_RESERVE4_BASE_IDX                                                                      1
>+#define mmDAGB4_RESERVE5                                                                               0x0277
>+#define mmDAGB4_RESERVE5_BASE_IDX                                                                      1
>+#define mmDAGB4_RESERVE6                                                                               0x0278
>+#define mmDAGB4_RESERVE6_BASE_IDX                                                                      1
>+#define mmDAGB4_RESERVE7                                                                               0x0279
>+#define mmDAGB4_RESERVE7_BASE_IDX                                                                      1
>+#define mmDAGB4_RESERVE8                                                                               0x027a
>+#define mmDAGB4_RESERVE8_BASE_IDX                                                                      1
>+#define mmDAGB4_RESERVE9                                                                               0x027b
>+#define mmDAGB4_RESERVE9_BASE_IDX                                                                      1
>+#define mmDAGB4_RESERVE10                                                                              0x027c
>+#define mmDAGB4_RESERVE10_BASE_IDX                                                                     1
>+#define mmDAGB4_RESERVE11                                                                              0x027d
>+#define mmDAGB4_RESERVE11_BASE_IDX                                                                     1
>+#define mmDAGB4_RESERVE12                                                                              0x027e
>+#define mmDAGB4_RESERVE12_BASE_IDX                                                                     1
>+#define mmDAGB4_RESERVE13                                                                              0x027f
>+#define mmDAGB4_RESERVE13_BASE_IDX                                                                     1
>+
>+
>+// addressBlock: mmhub_ea_mmeadec0
>+// base address: 0x68a00
>+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0                                                                   0x0280
>+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1                                                                   0x0281
>+#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0                                                                   0x0282
>+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1                                                                   0x0283
>+#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA0_DRAM_RD_GRP2VC_MAP                                                                     0x0284
>+#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA0_DRAM_WR_GRP2VC_MAP                                                                     0x0285
>+#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA0_DRAM_RD_LAZY                                                                           0x0286
>+#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA0_DRAM_WR_LAZY                                                                           0x0287
>+#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA0_DRAM_RD_CAM_CNTL                                                                       0x0288
>+#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA0_DRAM_WR_CAM_CNTL                                                                       0x0289
>+#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA0_DRAM_PAGE_BURST                                                                        0x028a
>+#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX                                                               1
>+#define mmMMEA0_DRAM_RD_PRI_AGE                                                                        0x028b
>+#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA0_DRAM_WR_PRI_AGE                                                                        0x028c
>+#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA0_DRAM_RD_PRI_QUEUING                                                                    0x028d
>+#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA0_DRAM_WR_PRI_QUEUING                                                                    0x028e
>+#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA0_DRAM_RD_PRI_FIXED                                                                      0x028f
>+#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA0_DRAM_WR_PRI_FIXED                                                                      0x0290
>+#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA0_DRAM_RD_PRI_URGENCY                                                                    0x0291
>+#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA0_DRAM_WR_PRI_URGENCY                                                                    0x0292
>+#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1                                                                 0x0293
>+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2                                                                 0x0294
>+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3                                                                 0x0295
>+#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1                                                                 0x0296
>+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2                                                                 0x0297
>+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3                                                                 0x0298
>+#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA0_GMI_RD_CLI2GRP_MAP0                                                                    0x0299
>+#define mmMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA0_GMI_RD_CLI2GRP_MAP1                                                                    0x029a
>+#define mmMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA0_GMI_WR_CLI2GRP_MAP0                                                                    0x029b
>+#define mmMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA0_GMI_WR_CLI2GRP_MAP1                                                                    0x029c
>+#define mmMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA0_GMI_RD_GRP2VC_MAP                                                                      0x029d
>+#define mmMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA0_GMI_WR_GRP2VC_MAP                                                                      0x029e
>+#define mmMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA0_GMI_RD_LAZY                                                                            0x029f
>+#define mmMMEA0_GMI_RD_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA0_GMI_WR_LAZY                                                                            0x02a0
>+#define mmMMEA0_GMI_WR_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA0_GMI_RD_CAM_CNTL                                                                        0x02a1
>+#define mmMMEA0_GMI_RD_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA0_GMI_WR_CAM_CNTL                                                                        0x02a2
>+#define mmMMEA0_GMI_WR_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA0_GMI_PAGE_BURST                                                                         0x02a3
>+#define mmMMEA0_GMI_PAGE_BURST_BASE_IDX                                                                1
>+#define mmMMEA0_GMI_RD_PRI_AGE                                                                         0x02a4
>+#define mmMMEA0_GMI_RD_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA0_GMI_WR_PRI_AGE                                                                         0x02a5
>+#define mmMMEA0_GMI_WR_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA0_GMI_RD_PRI_QUEUING                                                                     0x02a6
>+#define mmMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA0_GMI_WR_PRI_QUEUING                                                                     0x02a7
>+#define mmMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA0_GMI_RD_PRI_FIXED                                                                       0x02a8
>+#define mmMMEA0_GMI_RD_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA0_GMI_WR_PRI_FIXED                                                                       0x02a9
>+#define mmMMEA0_GMI_WR_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA0_GMI_RD_PRI_URGENCY                                                                     0x02aa
>+#define mmMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA0_GMI_WR_PRI_URGENCY                                                                     0x02ab
>+#define mmMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING                                                             0x02ac
>+#define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING                                                             0x02ad
>+#define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA0_GMI_RD_PRI_QUANT_PRI1                                                                  0x02ae
>+#define mmMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA0_GMI_RD_PRI_QUANT_PRI2                                                                  0x02af
>+#define mmMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA0_GMI_RD_PRI_QUANT_PRI3                                                                  0x02b0
>+#define mmMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA0_GMI_WR_PRI_QUANT_PRI1                                                                  0x02b1
>+#define mmMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA0_GMI_WR_PRI_QUANT_PRI2                                                                  0x02b2
>+#define mmMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA0_GMI_WR_PRI_QUANT_PRI3                                                                  0x02b3
>+#define mmMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA0_ADDRNORM_BASE_ADDR0                                                                    0x02b4
>+#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX                                                           1
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR0                                                                   0x02b5
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX                                                          1
>+#define mmMMEA0_ADDRNORM_BASE_ADDR1                                                                    0x02b6
>+#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX                                                           1
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR1                                                                   0x02b7
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX                                                          1
>+#define mmMMEA0_ADDRNORM_OFFSET_ADDR1                                                                  0x02b8
>+#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX                                                         1
>+#define mmMMEA0_ADDRNORM_BASE_ADDR2                                                                    0x02b9
>+#define mmMMEA0_ADDRNORM_BASE_ADDR2_BASE_IDX                                                           1
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR2                                                                   0x02ba
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR2_BASE_IDX                                                          1
>+#define mmMMEA0_ADDRNORM_BASE_ADDR3                                                                    0x02bb
>+#define mmMMEA0_ADDRNORM_BASE_ADDR3_BASE_IDX                                                           1
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR3                                                                   0x02bc
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR3_BASE_IDX                                                          1
>+#define mmMMEA0_ADDRNORM_OFFSET_ADDR3                                                                  0x02bd
>+#define mmMMEA0_ADDRNORM_OFFSET_ADDR3_BASE_IDX                                                         1
>+#define mmMMEA0_ADDRNORM_BASE_ADDR4                                                                    0x02be
>+#define mmMMEA0_ADDRNORM_BASE_ADDR4_BASE_IDX                                                           1
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR4                                                                   0x02bf
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR4_BASE_IDX                                                          1
>+#define mmMMEA0_ADDRNORM_BASE_ADDR5                                                                    0x02c0
>+#define mmMMEA0_ADDRNORM_BASE_ADDR5_BASE_IDX                                                           1
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR5                                                                   0x02c1
>+#define mmMMEA0_ADDRNORM_LIMIT_ADDR5_BASE_IDX                                                          1
>+#define mmMMEA0_ADDRNORM_OFFSET_ADDR5                                                                  0x02c2
>+#define mmMMEA0_ADDRNORM_OFFSET_ADDR5_BASE_IDX                                                         1
>+#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL                                                                 0x02c3
>+#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRNORMGMI_HOLE_CNTL                                                                  0x02c4
>+#define mmMMEA0_ADDRNORMGMI_HOLE_CNTL_BASE_IDX                                                         1
>+#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG                                                           0x02c5
>+#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX                                                  1
>+#define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG                                                            0x02c6
>+#define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX                                                   1
>+#define mmMMEA0_ADDRDEC_BANK_CFG                                                                       0x02c7
>+#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX                                                              1
>+#define mmMMEA0_ADDRDEC_MISC_CFG                                                                       0x02c8
>+#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX                                                              1
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0                                                            0x02c9
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX                                                   1
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1                                                            0x02ca
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX                                                   1
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2                                                            0x02cb
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX                                                   1
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3                                                            0x02cc
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX                                                   1
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4                                                            0x02cd
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX                                                   1
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5                                                            0x02ce
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX                                                   1
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC                                                               0x02cf
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2                                                              0x02d0
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0                                                              0x02d1
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1                                                              0x02d2
>+#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE                                                             0x02d3
>+#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0                                                             0x02d4
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1                                                             0x02d5
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2                                                             0x02d6
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3                                                             0x02d7
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4                                                             0x02d8
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5                                                             0x02d9
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC                                                                0x02da
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2                                                               0x02db
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0                                                               0x02dc
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1                                                               0x02dd
>+#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE                                                              0x02de
>+#define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0                                                                 0x02df
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1                                                                 0x02e0
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2                                                                 0x02e1
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3                                                                 0x02e2
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0                                                              0x02e3
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1                                                              0x02e4
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2                                                              0x02e5
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3                                                              0x02e6
>+#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01                                                                0x02e7
>+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23                                                                0x02e8
>+#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01                                                             0x02e9
>+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23                                                             0x02ea
>+#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01                                                                 0x02eb
>+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23                                                                 0x02ec
>+#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01                                                                 0x02ed
>+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23                                                                 0x02ee
>+#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01                                                                0x02ef
>+#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23                                                                0x02f0
>+#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01                                                               0x02f1
>+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23                                                               0x02f2
>+#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01                                                               0x02f3
>+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23                                                               0x02f4
>+#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDEC0_RM_SEL_CS01                                                                   0x02f5
>+#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA0_ADDRDEC0_RM_SEL_CS23                                                                   0x02f6
>+#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01                                                                0x02f7
>+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23                                                                0x02f8
>+#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0                                                                 0x02f9
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1                                                                 0x02fa
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2                                                                 0x02fb
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3                                                                 0x02fc
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0                                                              0x02fd
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1                                                              0x02fe
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2                                                              0x02ff
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3                                                              0x0300
>+#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01                                                                0x0301
>+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23                                                                0x0302
>+#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01                                                             0x0303
>+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23                                                             0x0304
>+#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01                                                                 0x0305
>+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23                                                                 0x0306
>+#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01                                                                 0x0307
>+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23                                                                 0x0308
>+#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01                                                                0x0309
>+#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23                                                                0x030a
>+#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01                                                               0x030b
>+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23                                                               0x030c
>+#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01                                                               0x030d
>+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23                                                               0x030e
>+#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDEC1_RM_SEL_CS01                                                                   0x030f
>+#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA0_ADDRDEC1_RM_SEL_CS23                                                                   0x0310
>+#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01                                                                0x0311
>+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23                                                                0x0312
>+#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0                                                                 0x0313
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1                                                                 0x0314
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2                                                                 0x0315
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3                                                                 0x0316
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0                                                              0x0317
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1                                                              0x0318
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2                                                              0x0319
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3                                                              0x031a
>+#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01                                                                0x031b
>+#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23                                                                0x031c
>+#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01                                                             0x031d
>+#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23                                                             0x031e
>+#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01                                                                 0x031f
>+#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23                                                                 0x0320
>+#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01                                                                 0x0321
>+#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23                                                                 0x0322
>+#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01                                                                0x0323
>+#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23                                                                0x0324
>+#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01                                                               0x0325
>+#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23                                                               0x0326
>+#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01                                                               0x0327
>+#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23                                                               0x0328
>+#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRDEC2_RM_SEL_CS01                                                                   0x0329
>+#define mmMMEA0_ADDRDEC2_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA0_ADDRDEC2_RM_SEL_CS23                                                                   0x032a
>+#define mmMMEA0_ADDRDEC2_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01                                                                0x032b
>+#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23                                                                0x032c
>+#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL                                                               0x032d
>+#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX                                                      1
>+#define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL                                                                0x032e
>+#define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX                                                       1
>+#define mmMMEA0_IO_RD_CLI2GRP_MAP0                                                                     0x0355
>+#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA0_IO_RD_CLI2GRP_MAP1                                                                     0x0356
>+#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA0_IO_WR_CLI2GRP_MAP0                                                                     0x0357
>+#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA0_IO_WR_CLI2GRP_MAP1                                                                     0x0358
>+#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA0_IO_RD_COMBINE_FLUSH                                                                    0x0359
>+#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA0_IO_WR_COMBINE_FLUSH                                                                    0x035a
>+#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA0_IO_GROUP_BURST                                                                         0x035b
>+#define mmMMEA0_IO_GROUP_BURST_BASE_IDX                                                                1
>+#define mmMMEA0_IO_RD_PRI_AGE                                                                          0x035c
>+#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA0_IO_WR_PRI_AGE                                                                          0x035d
>+#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA0_IO_RD_PRI_QUEUING                                                                      0x035e
>+#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA0_IO_WR_PRI_QUEUING                                                                      0x035f
>+#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA0_IO_RD_PRI_FIXED                                                                        0x0360
>+#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA0_IO_WR_PRI_FIXED                                                                        0x0361
>+#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA0_IO_RD_PRI_URGENCY                                                                      0x0362
>+#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA0_IO_WR_PRI_URGENCY                                                                      0x0363
>+#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING                                                              0x0364
>+#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING                                                              0x0365
>+#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA0_IO_RD_PRI_QUANT_PRI1                                                                   0x0366
>+#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA0_IO_RD_PRI_QUANT_PRI2                                                                   0x0367
>+#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA0_IO_RD_PRI_QUANT_PRI3                                                                   0x0368
>+#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA0_IO_WR_PRI_QUANT_PRI1                                                                   0x0369
>+#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA0_IO_WR_PRI_QUANT_PRI2                                                                   0x036a
>+#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA0_IO_WR_PRI_QUANT_PRI3                                                                   0x036b
>+#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA0_SDP_ARB_DRAM                                                                           0x036c
>+#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX                                                                  1
>+#define mmMMEA0_SDP_ARB_GMI                                                                            0x036d
>+#define mmMMEA0_SDP_ARB_GMI_BASE_IDX                                                                   1
>+#define mmMMEA0_SDP_ARB_FINAL                                                                          0x036e
>+#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX                                                                 1
>+#define mmMMEA0_SDP_DRAM_PRIORITY                                                                      0x036f
>+#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX                                                             1
>+#define mmMMEA0_SDP_GMI_PRIORITY                                                                       0x0370
>+#define mmMMEA0_SDP_GMI_PRIORITY_BASE_IDX                                                              1
>+#define mmMMEA0_SDP_IO_PRIORITY                                                                        0x0371
>+#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX                                                               1
>+#define mmMMEA0_SDP_CREDITS                                                                            0x0372
>+#define mmMMEA0_SDP_CREDITS_BASE_IDX                                                                   1
>+#define mmMMEA0_SDP_TAG_RESERVE0                                                                       0x0373
>+#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA0_SDP_TAG_RESERVE1                                                                       0x0374
>+#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA0_SDP_VCC_RESERVE0                                                                       0x0375
>+#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA0_SDP_VCC_RESERVE1                                                                       0x0376
>+#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA0_SDP_VCD_RESERVE0                                                                       0x0377
>+#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA0_SDP_VCD_RESERVE1                                                                       0x0378
>+#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA0_SDP_REQ_CNTL                                                                           0x0379
>+#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX                                                                  1
>+#define mmMMEA0_MISC                                                                                   0x037a
>+#define mmMMEA0_MISC_BASE_IDX                                                                          1
>+#define mmMMEA0_LATENCY_SAMPLING                                                                       0x037b
>+#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX                                                              1
>+#define mmMMEA0_PERFCOUNTER_LO                                                                         0x037c
>+#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmMMEA0_PERFCOUNTER_HI                                                                         0x037d
>+#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmMMEA0_PERFCOUNTER0_CFG                                                                       0x037e
>+#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmMMEA0_PERFCOUNTER1_CFG                                                                       0x037f
>+#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmMMEA0_PERFCOUNTER_RSLT_CNTL                                                                  0x0380
>+#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmMMEA0_EDC_CNT                                                                                0x0386
>+#define mmMMEA0_EDC_CNT_BASE_IDX                                                                       1
>+#define mmMMEA0_EDC_CNT2                                                                               0x0387
>+#define mmMMEA0_EDC_CNT2_BASE_IDX                                                                      1
>+#define mmMMEA0_DSM_CNTL                                                                               0x0388
>+#define mmMMEA0_DSM_CNTL_BASE_IDX                                                                      1
>+#define mmMMEA0_DSM_CNTLA                                                                              0x0389
>+#define mmMMEA0_DSM_CNTLA_BASE_IDX                                                                     1
>+#define mmMMEA0_DSM_CNTLB                                                                              0x038a
>+#define mmMMEA0_DSM_CNTLB_BASE_IDX                                                                     1
>+#define mmMMEA0_DSM_CNTL2                                                                              0x038b
>+#define mmMMEA0_DSM_CNTL2_BASE_IDX                                                                     1
>+#define mmMMEA0_DSM_CNTL2A                                                                             0x038c
>+#define mmMMEA0_DSM_CNTL2A_BASE_IDX                                                                    1
>+#define mmMMEA0_DSM_CNTL2B                                                                             0x038d
>+#define mmMMEA0_DSM_CNTL2B_BASE_IDX                                                                    1
>+#define mmMMEA0_CGTT_CLK_CTRL                                                                          0x038f
>+#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX                                                                 1
>+#define mmMMEA0_EDC_MODE                                                                               0x0390
>+#define mmMMEA0_EDC_MODE_BASE_IDX                                                                      1
>+#define mmMMEA0_ERR_STATUS                                                                             0x0391
>+#define mmMMEA0_ERR_STATUS_BASE_IDX                                                                    1
>+#define mmMMEA0_MISC2                                                                                  0x0392
>+#define mmMMEA0_MISC2_BASE_IDX                                                                         1
>+#define mmMMEA0_ADDRDEC_SELECT                                                                         0x0393
>+#define mmMMEA0_ADDRDEC_SELECT_BASE_IDX                                                                1
>+#define mmMMEA0_EDC_CNT3                                                                               0x0394
>+#define mmMMEA0_EDC_CNT3_BASE_IDX                                                                      1
>+
>+
>+// addressBlock: mmhub_ea_mmeadec1
>+// base address: 0x68f00
>+#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0                                                                   0x03c0
>+#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1                                                                   0x03c1
>+#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0                                                                   0x03c2
>+#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1                                                                   0x03c3
>+#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA1_DRAM_RD_GRP2VC_MAP                                                                     0x03c4
>+#define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA1_DRAM_WR_GRP2VC_MAP                                                                     0x03c5
>+#define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA1_DRAM_RD_LAZY                                                                           0x03c6
>+#define mmMMEA1_DRAM_RD_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA1_DRAM_WR_LAZY                                                                           0x03c7
>+#define mmMMEA1_DRAM_WR_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA1_DRAM_RD_CAM_CNTL                                                                       0x03c8
>+#define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA1_DRAM_WR_CAM_CNTL                                                                       0x03c9
>+#define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA1_DRAM_PAGE_BURST                                                                        0x03ca
>+#define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX                                                               1
>+#define mmMMEA1_DRAM_RD_PRI_AGE                                                                        0x03cb
>+#define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA1_DRAM_WR_PRI_AGE                                                                        0x03cc
>+#define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA1_DRAM_RD_PRI_QUEUING                                                                    0x03cd
>+#define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA1_DRAM_WR_PRI_QUEUING                                                                    0x03ce
>+#define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA1_DRAM_RD_PRI_FIXED                                                                      0x03cf
>+#define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA1_DRAM_WR_PRI_FIXED                                                                      0x03d0
>+#define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA1_DRAM_RD_PRI_URGENCY                                                                    0x03d1
>+#define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA1_DRAM_WR_PRI_URGENCY                                                                    0x03d2
>+#define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1                                                                 0x03d3
>+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2                                                                 0x03d4
>+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3                                                                 0x03d5
>+#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1                                                                 0x03d6
>+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2                                                                 0x03d7
>+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3                                                                 0x03d8
>+#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA1_GMI_RD_CLI2GRP_MAP0                                                                    0x03d9
>+#define mmMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA1_GMI_RD_CLI2GRP_MAP1                                                                    0x03da
>+#define mmMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA1_GMI_WR_CLI2GRP_MAP0                                                                    0x03db
>+#define mmMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA1_GMI_WR_CLI2GRP_MAP1                                                                    0x03dc
>+#define mmMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA1_GMI_RD_GRP2VC_MAP                                                                      0x03dd
>+#define mmMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA1_GMI_WR_GRP2VC_MAP                                                                      0x03de
>+#define mmMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA1_GMI_RD_LAZY                                                                            0x03df
>+#define mmMMEA1_GMI_RD_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA1_GMI_WR_LAZY                                                                            0x03e0
>+#define mmMMEA1_GMI_WR_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA1_GMI_RD_CAM_CNTL                                                                        0x03e1
>+#define mmMMEA1_GMI_RD_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA1_GMI_WR_CAM_CNTL                                                                        0x03e2
>+#define mmMMEA1_GMI_WR_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA1_GMI_PAGE_BURST                                                                         0x03e3
>+#define mmMMEA1_GMI_PAGE_BURST_BASE_IDX                                                                1
>+#define mmMMEA1_GMI_RD_PRI_AGE                                                                         0x03e4
>+#define mmMMEA1_GMI_RD_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA1_GMI_WR_PRI_AGE                                                                         0x03e5
>+#define mmMMEA1_GMI_WR_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA1_GMI_RD_PRI_QUEUING                                                                     0x03e6
>+#define mmMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA1_GMI_WR_PRI_QUEUING                                                                     0x03e7
>+#define mmMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA1_GMI_RD_PRI_FIXED                                                                       0x03e8
>+#define mmMMEA1_GMI_RD_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA1_GMI_WR_PRI_FIXED                                                                       0x03e9
>+#define mmMMEA1_GMI_WR_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA1_GMI_RD_PRI_URGENCY                                                                     0x03ea
>+#define mmMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA1_GMI_WR_PRI_URGENCY                                                                     0x03eb
>+#define mmMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING                                                             0x03ec
>+#define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING                                                             0x03ed
>+#define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA1_GMI_RD_PRI_QUANT_PRI1                                                                  0x03ee
>+#define mmMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA1_GMI_RD_PRI_QUANT_PRI2                                                                  0x03ef
>+#define mmMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA1_GMI_RD_PRI_QUANT_PRI3                                                                  0x03f0
>+#define mmMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA1_GMI_WR_PRI_QUANT_PRI1                                                                  0x03f1
>+#define mmMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA1_GMI_WR_PRI_QUANT_PRI2                                                                  0x03f2
>+#define mmMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA1_GMI_WR_PRI_QUANT_PRI3                                                                  0x03f3
>+#define mmMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA1_ADDRNORM_BASE_ADDR0                                                                    0x03f4
>+#define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX                                                           1
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR0                                                                   0x03f5
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX                                                          1
>+#define mmMMEA1_ADDRNORM_BASE_ADDR1                                                                    0x03f6
>+#define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX                                                           1
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR1                                                                   0x03f7
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX                                                          1
>+#define mmMMEA1_ADDRNORM_OFFSET_ADDR1                                                                  0x03f8
>+#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX                                                         1
>+#define mmMMEA1_ADDRNORM_BASE_ADDR2                                                                    0x03f9
>+#define mmMMEA1_ADDRNORM_BASE_ADDR2_BASE_IDX                                                           1
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR2                                                                   0x03fa
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR2_BASE_IDX                                                          1
>+#define mmMMEA1_ADDRNORM_BASE_ADDR3                                                                    0x03fb
>+#define mmMMEA1_ADDRNORM_BASE_ADDR3_BASE_IDX                                                           1
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR3                                                                   0x03fc
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR3_BASE_IDX                                                          1
>+#define mmMMEA1_ADDRNORM_OFFSET_ADDR3                                                                  0x03fd
>+#define mmMMEA1_ADDRNORM_OFFSET_ADDR3_BASE_IDX                                                         1
>+#define mmMMEA1_ADDRNORM_BASE_ADDR4                                                                    0x03fe
>+#define mmMMEA1_ADDRNORM_BASE_ADDR4_BASE_IDX                                                           1
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR4                                                                   0x03ff
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR4_BASE_IDX                                                          1
>+#define mmMMEA1_ADDRNORM_BASE_ADDR5                                                                    0x0400
>+#define mmMMEA1_ADDRNORM_BASE_ADDR5_BASE_IDX                                                           1
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR5                                                                   0x0401
>+#define mmMMEA1_ADDRNORM_LIMIT_ADDR5_BASE_IDX                                                          1
>+#define mmMMEA1_ADDRNORM_OFFSET_ADDR5                                                                  0x0402
>+#define mmMMEA1_ADDRNORM_OFFSET_ADDR5_BASE_IDX                                                         1
>+#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL                                                                 0x0403
>+#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRNORMGMI_HOLE_CNTL                                                                  0x0404
>+#define mmMMEA1_ADDRNORMGMI_HOLE_CNTL_BASE_IDX                                                         1
>+#define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG                                                           0x0405
>+#define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX                                                  1
>+#define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG                                                            0x0406
>+#define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX                                                   1
>+#define mmMMEA1_ADDRDEC_BANK_CFG                                                                       0x0407
>+#define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX                                                              1
>+#define mmMMEA1_ADDRDEC_MISC_CFG                                                                       0x0408
>+#define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX                                                              1
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0                                                            0x0409
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX                                                   1
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1                                                            0x040a
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX                                                   1
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2                                                            0x040b
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX                                                   1
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3                                                            0x040c
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX                                                   1
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4                                                            0x040d
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX                                                   1
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5                                                            0x040e
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX                                                   1
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC                                                               0x040f
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2                                                              0x0410
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0                                                              0x0411
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1                                                              0x0412
>+#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE                                                             0x0413
>+#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0                                                             0x0414
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1                                                             0x0415
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2                                                             0x0416
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3                                                             0x0417
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4                                                             0x0418
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5                                                             0x0419
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC                                                                0x041a
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2                                                               0x041b
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0                                                               0x041c
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1                                                               0x041d
>+#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE                                                              0x041e
>+#define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0                                                                 0x041f
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1                                                                 0x0420
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2                                                                 0x0421
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3                                                                 0x0422
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0                                                              0x0423
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1                                                              0x0424
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2                                                              0x0425
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3                                                              0x0426
>+#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01                                                                0x0427
>+#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23                                                                0x0428
>+#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01                                                             0x0429
>+#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23                                                             0x042a
>+#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01                                                                 0x042b
>+#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23                                                                 0x042c
>+#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01                                                                 0x042d
>+#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23                                                                 0x042e
>+#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01                                                                0x042f
>+#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23                                                                0x0430
>+#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01                                                               0x0431
>+#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23                                                               0x0432
>+#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01                                                               0x0433
>+#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23                                                               0x0434
>+#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDEC0_RM_SEL_CS01                                                                   0x0435
>+#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA1_ADDRDEC0_RM_SEL_CS23                                                                   0x0436
>+#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01                                                                0x0437
>+#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23                                                                0x0438
>+#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0                                                                 0x0439
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1                                                                 0x043a
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2                                                                 0x043b
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3                                                                 0x043c
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0                                                              0x043d
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1                                                              0x043e
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2                                                              0x043f
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3                                                              0x0440
>+#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01                                                                0x0441
>+#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23                                                                0x0442
>+#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01                                                             0x0443
>+#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23                                                             0x0444
>+#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01                                                                 0x0445
>+#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23                                                                 0x0446
>+#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01                                                                 0x0447
>+#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23                                                                 0x0448
>+#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01                                                                0x0449
>+#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23                                                                0x044a
>+#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01                                                               0x044b
>+#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23                                                               0x044c
>+#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01                                                               0x044d
>+#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23                                                               0x044e
>+#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDEC1_RM_SEL_CS01                                                                   0x044f
>+#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA1_ADDRDEC1_RM_SEL_CS23                                                                   0x0450
>+#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01                                                                0x0451
>+#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23                                                                0x0452
>+#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0                                                                 0x0453
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1                                                                 0x0454
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2                                                                 0x0455
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3                                                                 0x0456
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0                                                              0x0457
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1                                                              0x0458
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2                                                              0x0459
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3                                                              0x045a
>+#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01                                                                0x045b
>+#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23                                                                0x045c
>+#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01                                                             0x045d
>+#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23                                                             0x045e
>+#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01                                                                 0x045f
>+#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23                                                                 0x0460
>+#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01                                                                 0x0461
>+#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23                                                                 0x0462
>+#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01                                                                0x0463
>+#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23                                                                0x0464
>+#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01                                                               0x0465
>+#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23                                                               0x0466
>+#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01                                                               0x0467
>+#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23                                                               0x0468
>+#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRDEC2_RM_SEL_CS01                                                                   0x0469
>+#define mmMMEA1_ADDRDEC2_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA1_ADDRDEC2_RM_SEL_CS23                                                                   0x046a
>+#define mmMMEA1_ADDRDEC2_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01                                                                0x046b
>+#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23                                                                0x046c
>+#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL                                                               0x046d
>+#define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX                                                      1
>+#define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL                                                                0x046e
>+#define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX                                                       1
>+#define mmMMEA1_IO_RD_CLI2GRP_MAP0                                                                     0x0495
>+#define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA1_IO_RD_CLI2GRP_MAP1                                                                     0x0496
>+#define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA1_IO_WR_CLI2GRP_MAP0                                                                     0x0497
>+#define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA1_IO_WR_CLI2GRP_MAP1                                                                     0x0498
>+#define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA1_IO_RD_COMBINE_FLUSH                                                                    0x0499
>+#define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA1_IO_WR_COMBINE_FLUSH                                                                    0x049a
>+#define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA1_IO_GROUP_BURST                                                                         0x049b
>+#define mmMMEA1_IO_GROUP_BURST_BASE_IDX                                                                1
>+#define mmMMEA1_IO_RD_PRI_AGE                                                                          0x049c
>+#define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA1_IO_WR_PRI_AGE                                                                          0x049d
>+#define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA1_IO_RD_PRI_QUEUING                                                                      0x049e
>+#define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA1_IO_WR_PRI_QUEUING                                                                      0x049f
>+#define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA1_IO_RD_PRI_FIXED                                                                        0x04a0
>+#define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA1_IO_WR_PRI_FIXED                                                                        0x04a1
>+#define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA1_IO_RD_PRI_URGENCY                                                                      0x04a2
>+#define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA1_IO_WR_PRI_URGENCY                                                                      0x04a3
>+#define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA1_IO_RD_PRI_URGENCY_MASKING                                                              0x04a4
>+#define mmMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA1_IO_WR_PRI_URGENCY_MASKING                                                              0x04a5
>+#define mmMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA1_IO_RD_PRI_QUANT_PRI1                                                                   0x04a6
>+#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA1_IO_RD_PRI_QUANT_PRI2                                                                   0x04a7
>+#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA1_IO_RD_PRI_QUANT_PRI3                                                                   0x04a8
>+#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA1_IO_WR_PRI_QUANT_PRI1                                                                   0x04a9
>+#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA1_IO_WR_PRI_QUANT_PRI2                                                                   0x04aa
>+#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA1_IO_WR_PRI_QUANT_PRI3                                                                   0x04ab
>+#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA1_SDP_ARB_DRAM                                                                           0x04ac
>+#define mmMMEA1_SDP_ARB_DRAM_BASE_IDX                                                                  1
>+#define mmMMEA1_SDP_ARB_GMI                                                                            0x04ad
>+#define mmMMEA1_SDP_ARB_GMI_BASE_IDX                                                                   1
>+#define mmMMEA1_SDP_ARB_FINAL                                                                          0x04ae
>+#define mmMMEA1_SDP_ARB_FINAL_BASE_IDX                                                                 1
>+#define mmMMEA1_SDP_DRAM_PRIORITY                                                                      0x04af
>+#define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX                                                             1
>+#define mmMMEA1_SDP_GMI_PRIORITY                                                                       0x04b0
>+#define mmMMEA1_SDP_GMI_PRIORITY_BASE_IDX                                                              1
>+#define mmMMEA1_SDP_IO_PRIORITY                                                                        0x04b1
>+#define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX                                                               1
>+#define mmMMEA1_SDP_CREDITS                                                                            0x04b2
>+#define mmMMEA1_SDP_CREDITS_BASE_IDX                                                                   1
>+#define mmMMEA1_SDP_TAG_RESERVE0                                                                       0x04b3
>+#define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA1_SDP_TAG_RESERVE1                                                                       0x04b4
>+#define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA1_SDP_VCC_RESERVE0                                                                       0x04b5
>+#define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA1_SDP_VCC_RESERVE1                                                                       0x04b6
>+#define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA1_SDP_VCD_RESERVE0                                                                       0x04b7
>+#define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA1_SDP_VCD_RESERVE1                                                                       0x04b8
>+#define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA1_SDP_REQ_CNTL                                                                           0x04b9
>+#define mmMMEA1_SDP_REQ_CNTL_BASE_IDX                                                                  1
>+#define mmMMEA1_MISC                                                                                   0x04ba
>+#define mmMMEA1_MISC_BASE_IDX                                                                          1
>+#define mmMMEA1_LATENCY_SAMPLING                                                                       0x04bb
>+#define mmMMEA1_LATENCY_SAMPLING_BASE_IDX                                                              1
>+#define mmMMEA1_PERFCOUNTER_LO                                                                         0x04bc
>+#define mmMMEA1_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmMMEA1_PERFCOUNTER_HI                                                                         0x04bd
>+#define mmMMEA1_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmMMEA1_PERFCOUNTER0_CFG                                                                       0x04be
>+#define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmMMEA1_PERFCOUNTER1_CFG                                                                       0x04bf
>+#define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmMMEA1_PERFCOUNTER_RSLT_CNTL                                                                  0x04c0
>+#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmMMEA1_EDC_CNT                                                                                0x04c6
>+#define mmMMEA1_EDC_CNT_BASE_IDX                                                                       1
>+#define mmMMEA1_EDC_CNT2                                                                               0x04c7
>+#define mmMMEA1_EDC_CNT2_BASE_IDX                                                                      1
>+#define mmMMEA1_DSM_CNTL                                                                               0x04c8
>+#define mmMMEA1_DSM_CNTL_BASE_IDX                                                                      1
>+#define mmMMEA1_DSM_CNTLA                                                                              0x04c9
>+#define mmMMEA1_DSM_CNTLA_BASE_IDX                                                                     1
>+#define mmMMEA1_DSM_CNTLB                                                                              0x04ca
>+#define mmMMEA1_DSM_CNTLB_BASE_IDX                                                                     1
>+#define mmMMEA1_DSM_CNTL2                                                                              0x04cb
>+#define mmMMEA1_DSM_CNTL2_BASE_IDX                                                                     1
>+#define mmMMEA1_DSM_CNTL2A                                                                             0x04cc
>+#define mmMMEA1_DSM_CNTL2A_BASE_IDX                                                                    1
>+#define mmMMEA1_DSM_CNTL2B                                                                             0x04cd
>+#define mmMMEA1_DSM_CNTL2B_BASE_IDX                                                                    1
>+#define mmMMEA1_CGTT_CLK_CTRL                                                                          0x04cf
>+#define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX                                                                 1
>+#define mmMMEA1_EDC_MODE                                                                               0x04d0
>+#define mmMMEA1_EDC_MODE_BASE_IDX                                                                      1
>+#define mmMMEA1_ERR_STATUS                                                                             0x04d1
>+#define mmMMEA1_ERR_STATUS_BASE_IDX                                                                    1
>+#define mmMMEA1_MISC2                                                                                  0x04d2
>+#define mmMMEA1_MISC2_BASE_IDX                                                                         1
>+#define mmMMEA1_ADDRDEC_SELECT                                                                         0x04d3
>+#define mmMMEA1_ADDRDEC_SELECT_BASE_IDX                                                                1
>+#define mmMMEA1_EDC_CNT3                                                                               0x04d4
>+#define mmMMEA1_EDC_CNT3_BASE_IDX                                                                      1
>+
>+
>+// addressBlock: mmhub_ea_mmeadec2
>+// base address: 0x69400
>+#define mmMMEA2_DRAM_RD_CLI2GRP_MAP0                                                                   0x0500
>+#define mmMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA2_DRAM_RD_CLI2GRP_MAP1                                                                   0x0501
>+#define mmMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA2_DRAM_WR_CLI2GRP_MAP0                                                                   0x0502
>+#define mmMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA2_DRAM_WR_CLI2GRP_MAP1                                                                   0x0503
>+#define mmMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA2_DRAM_RD_GRP2VC_MAP                                                                     0x0504
>+#define mmMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA2_DRAM_WR_GRP2VC_MAP                                                                     0x0505
>+#define mmMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA2_DRAM_RD_LAZY                                                                           0x0506
>+#define mmMMEA2_DRAM_RD_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA2_DRAM_WR_LAZY                                                                           0x0507
>+#define mmMMEA2_DRAM_WR_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA2_DRAM_RD_CAM_CNTL                                                                       0x0508
>+#define mmMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA2_DRAM_WR_CAM_CNTL                                                                       0x0509
>+#define mmMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA2_DRAM_PAGE_BURST                                                                        0x050a
>+#define mmMMEA2_DRAM_PAGE_BURST_BASE_IDX                                                               1
>+#define mmMMEA2_DRAM_RD_PRI_AGE                                                                        0x050b
>+#define mmMMEA2_DRAM_RD_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA2_DRAM_WR_PRI_AGE                                                                        0x050c
>+#define mmMMEA2_DRAM_WR_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA2_DRAM_RD_PRI_QUEUING                                                                    0x050d
>+#define mmMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA2_DRAM_WR_PRI_QUEUING                                                                    0x050e
>+#define mmMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA2_DRAM_RD_PRI_FIXED                                                                      0x050f
>+#define mmMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA2_DRAM_WR_PRI_FIXED                                                                      0x0510
>+#define mmMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA2_DRAM_RD_PRI_URGENCY                                                                    0x0511
>+#define mmMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA2_DRAM_WR_PRI_URGENCY                                                                    0x0512
>+#define mmMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1                                                                 0x0513
>+#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2                                                                 0x0514
>+#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3                                                                 0x0515
>+#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1                                                                 0x0516
>+#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2                                                                 0x0517
>+#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3                                                                 0x0518
>+#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA2_GMI_RD_CLI2GRP_MAP0                                                                    0x0519
>+#define mmMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA2_GMI_RD_CLI2GRP_MAP1                                                                    0x051a
>+#define mmMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA2_GMI_WR_CLI2GRP_MAP0                                                                    0x051b
>+#define mmMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA2_GMI_WR_CLI2GRP_MAP1                                                                    0x051c
>+#define mmMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA2_GMI_RD_GRP2VC_MAP                                                                      0x051d
>+#define mmMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA2_GMI_WR_GRP2VC_MAP                                                                      0x051e
>+#define mmMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA2_GMI_RD_LAZY                                                                            0x051f
>+#define mmMMEA2_GMI_RD_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA2_GMI_WR_LAZY                                                                            0x0520
>+#define mmMMEA2_GMI_WR_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA2_GMI_RD_CAM_CNTL                                                                        0x0521
>+#define mmMMEA2_GMI_RD_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA2_GMI_WR_CAM_CNTL                                                                        0x0522
>+#define mmMMEA2_GMI_WR_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA2_GMI_PAGE_BURST                                                                         0x0523
>+#define mmMMEA2_GMI_PAGE_BURST_BASE_IDX                                                                1
>+#define mmMMEA2_GMI_RD_PRI_AGE                                                                         0x0524
>+#define mmMMEA2_GMI_RD_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA2_GMI_WR_PRI_AGE                                                                         0x0525
>+#define mmMMEA2_GMI_WR_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA2_GMI_RD_PRI_QUEUING                                                                     0x0526
>+#define mmMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA2_GMI_WR_PRI_QUEUING                                                                     0x0527
>+#define mmMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA2_GMI_RD_PRI_FIXED                                                                       0x0528
>+#define mmMMEA2_GMI_RD_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA2_GMI_WR_PRI_FIXED                                                                       0x0529
>+#define mmMMEA2_GMI_WR_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA2_GMI_RD_PRI_URGENCY                                                                     0x052a
>+#define mmMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA2_GMI_WR_PRI_URGENCY                                                                     0x052b
>+#define mmMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING                                                             0x052c
>+#define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING                                                             0x052d
>+#define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA2_GMI_RD_PRI_QUANT_PRI1                                                                  0x052e
>+#define mmMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA2_GMI_RD_PRI_QUANT_PRI2                                                                  0x052f
>+#define mmMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA2_GMI_RD_PRI_QUANT_PRI3                                                                  0x0530
>+#define mmMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA2_GMI_WR_PRI_QUANT_PRI1                                                                  0x0531
>+#define mmMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA2_GMI_WR_PRI_QUANT_PRI2                                                                  0x0532
>+#define mmMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA2_GMI_WR_PRI_QUANT_PRI3                                                                  0x0533
>+#define mmMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA2_ADDRNORM_BASE_ADDR0                                                                    0x0534
>+#define mmMMEA2_ADDRNORM_BASE_ADDR0_BASE_IDX                                                           1
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR0                                                                   0x0535
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR0_BASE_IDX                                                          1
>+#define mmMMEA2_ADDRNORM_BASE_ADDR1                                                                    0x0536
>+#define mmMMEA2_ADDRNORM_BASE_ADDR1_BASE_IDX                                                           1
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR1                                                                   0x0537
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR1_BASE_IDX                                                          1
>+#define mmMMEA2_ADDRNORM_OFFSET_ADDR1                                                                  0x0538
>+#define mmMMEA2_ADDRNORM_OFFSET_ADDR1_BASE_IDX                                                         1
>+#define mmMMEA2_ADDRNORM_BASE_ADDR2                                                                    0x0539
>+#define mmMMEA2_ADDRNORM_BASE_ADDR2_BASE_IDX                                                           1
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR2                                                                   0x053a
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR2_BASE_IDX                                                          1
>+#define mmMMEA2_ADDRNORM_BASE_ADDR3                                                                    0x053b
>+#define mmMMEA2_ADDRNORM_BASE_ADDR3_BASE_IDX                                                           1
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR3                                                                   0x053c
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR3_BASE_IDX                                                          1
>+#define mmMMEA2_ADDRNORM_OFFSET_ADDR3                                                                  0x053d
>+#define mmMMEA2_ADDRNORM_OFFSET_ADDR3_BASE_IDX                                                         1
>+#define mmMMEA2_ADDRNORM_BASE_ADDR4                                                                    0x053e
>+#define mmMMEA2_ADDRNORM_BASE_ADDR4_BASE_IDX                                                           1
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR4                                                                   0x053f
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR4_BASE_IDX                                                          1
>+#define mmMMEA2_ADDRNORM_BASE_ADDR5                                                                    0x0540
>+#define mmMMEA2_ADDRNORM_BASE_ADDR5_BASE_IDX                                                           1
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR5                                                                   0x0541
>+#define mmMMEA2_ADDRNORM_LIMIT_ADDR5_BASE_IDX                                                          1
>+#define mmMMEA2_ADDRNORM_OFFSET_ADDR5                                                                  0x0542
>+#define mmMMEA2_ADDRNORM_OFFSET_ADDR5_BASE_IDX                                                         1
>+#define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL                                                                 0x0543
>+#define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRNORMGMI_HOLE_CNTL                                                                  0x0544
>+#define mmMMEA2_ADDRNORMGMI_HOLE_CNTL_BASE_IDX                                                         1
>+#define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG                                                           0x0545
>+#define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX                                                  1
>+#define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG                                                            0x0546
>+#define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX                                                   1
>+#define mmMMEA2_ADDRDEC_BANK_CFG                                                                       0x0547
>+#define mmMMEA2_ADDRDEC_BANK_CFG_BASE_IDX                                                              1
>+#define mmMMEA2_ADDRDEC_MISC_CFG                                                                       0x0548
>+#define mmMMEA2_ADDRDEC_MISC_CFG_BASE_IDX                                                              1
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0                                                            0x0549
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX                                                   1
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1                                                            0x054a
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX                                                   1
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2                                                            0x054b
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX                                                   1
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3                                                            0x054c
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX                                                   1
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4                                                            0x054d
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX                                                   1
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5                                                            0x054e
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX                                                   1
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC                                                               0x054f
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2                                                              0x0550
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0                                                              0x0551
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1                                                              0x0552
>+#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE                                                             0x0553
>+#define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0                                                             0x0554
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1                                                             0x0555
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2                                                             0x0556
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3                                                             0x0557
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4                                                             0x0558
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5                                                             0x0559
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC                                                                0x055a
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2                                                               0x055b
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0                                                               0x055c
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1                                                               0x055d
>+#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE                                                              0x055e
>+#define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0                                                                 0x055f
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1                                                                 0x0560
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2                                                                 0x0561
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3                                                                 0x0562
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0                                                              0x0563
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1                                                              0x0564
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2                                                              0x0565
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3                                                              0x0566
>+#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01                                                                0x0567
>+#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23                                                                0x0568
>+#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01                                                             0x0569
>+#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23                                                             0x056a
>+#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01                                                                 0x056b
>+#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23                                                                 0x056c
>+#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01                                                                 0x056d
>+#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23                                                                 0x056e
>+#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01                                                                0x056f
>+#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23                                                                0x0570
>+#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01                                                               0x0571
>+#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23                                                               0x0572
>+#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01                                                               0x0573
>+#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23                                                               0x0574
>+#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDEC0_RM_SEL_CS01                                                                   0x0575
>+#define mmMMEA2_ADDRDEC0_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA2_ADDRDEC0_RM_SEL_CS23                                                                   0x0576
>+#define mmMMEA2_ADDRDEC0_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01                                                                0x0577
>+#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23                                                                0x0578
>+#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0                                                                 0x0579
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1                                                                 0x057a
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2                                                                 0x057b
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3                                                                 0x057c
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0                                                              0x057d
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1                                                              0x057e
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2                                                              0x057f
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3                                                              0x0580
>+#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01                                                                0x0581
>+#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23                                                                0x0582
>+#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01                                                             0x0583
>+#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23                                                             0x0584
>+#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01                                                                 0x0585
>+#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23                                                                 0x0586
>+#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01                                                                 0x0587
>+#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23                                                                 0x0588
>+#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01                                                                0x0589
>+#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23                                                                0x058a
>+#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01                                                               0x058b
>+#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23                                                               0x058c
>+#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01                                                               0x058d
>+#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23                                                               0x058e
>+#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDEC1_RM_SEL_CS01                                                                   0x058f
>+#define mmMMEA2_ADDRDEC1_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA2_ADDRDEC1_RM_SEL_CS23                                                                   0x0590
>+#define mmMMEA2_ADDRDEC1_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01                                                                0x0591
>+#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23                                                                0x0592
>+#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0                                                                 0x0593
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1                                                                 0x0594
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2                                                                 0x0595
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3                                                                 0x0596
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0                                                              0x0597
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1                                                              0x0598
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2                                                              0x0599
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3                                                              0x059a
>+#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01                                                                0x059b
>+#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23                                                                0x059c
>+#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01                                                             0x059d
>+#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23                                                             0x059e
>+#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01                                                                 0x059f
>+#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23                                                                 0x05a0
>+#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01                                                                 0x05a1
>+#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23                                                                 0x05a2
>+#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01                                                                0x05a3
>+#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23                                                                0x05a4
>+#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01                                                               0x05a5
>+#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23                                                               0x05a6
>+#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01                                                               0x05a7
>+#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23                                                               0x05a8
>+#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRDEC2_RM_SEL_CS01                                                                   0x05a9
>+#define mmMMEA2_ADDRDEC2_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA2_ADDRDEC2_RM_SEL_CS23                                                                   0x05aa
>+#define mmMMEA2_ADDRDEC2_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01                                                                0x05ab
>+#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23                                                                0x05ac
>+#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL                                                               0x05ad
>+#define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX                                                      1
>+#define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL                                                                0x05ae
>+#define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX                                                       1
>+#define mmMMEA2_IO_RD_CLI2GRP_MAP0                                                                     0x05d5
>+#define mmMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA2_IO_RD_CLI2GRP_MAP1                                                                     0x05d6
>+#define mmMMEA2_IO_RD_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA2_IO_WR_CLI2GRP_MAP0                                                                     0x05d7
>+#define mmMMEA2_IO_WR_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA2_IO_WR_CLI2GRP_MAP1                                                                     0x05d8
>+#define mmMMEA2_IO_WR_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA2_IO_RD_COMBINE_FLUSH                                                                    0x05d9
>+#define mmMMEA2_IO_RD_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA2_IO_WR_COMBINE_FLUSH                                                                    0x05da
>+#define mmMMEA2_IO_WR_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA2_IO_GROUP_BURST                                                                         0x05db
>+#define mmMMEA2_IO_GROUP_BURST_BASE_IDX                                                                1
>+#define mmMMEA2_IO_RD_PRI_AGE                                                                          0x05dc
>+#define mmMMEA2_IO_RD_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA2_IO_WR_PRI_AGE                                                                          0x05dd
>+#define mmMMEA2_IO_WR_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA2_IO_RD_PRI_QUEUING                                                                      0x05de
>+#define mmMMEA2_IO_RD_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA2_IO_WR_PRI_QUEUING                                                                      0x05df
>+#define mmMMEA2_IO_WR_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA2_IO_RD_PRI_FIXED                                                                        0x05e0
>+#define mmMMEA2_IO_RD_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA2_IO_WR_PRI_FIXED                                                                        0x05e1
>+#define mmMMEA2_IO_WR_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA2_IO_RD_PRI_URGENCY                                                                      0x05e2
>+#define mmMMEA2_IO_RD_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA2_IO_WR_PRI_URGENCY                                                                      0x05e3
>+#define mmMMEA2_IO_WR_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA2_IO_RD_PRI_URGENCY_MASKING                                                              0x05e4
>+#define mmMMEA2_IO_RD_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA2_IO_WR_PRI_URGENCY_MASKING                                                              0x05e5
>+#define mmMMEA2_IO_WR_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA2_IO_RD_PRI_QUANT_PRI1                                                                   0x05e6
>+#define mmMMEA2_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA2_IO_RD_PRI_QUANT_PRI2                                                                   0x05e7
>+#define mmMMEA2_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA2_IO_RD_PRI_QUANT_PRI3                                                                   0x05e8
>+#define mmMMEA2_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA2_IO_WR_PRI_QUANT_PRI1                                                                   0x05e9
>+#define mmMMEA2_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA2_IO_WR_PRI_QUANT_PRI2                                                                   0x05ea
>+#define mmMMEA2_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA2_IO_WR_PRI_QUANT_PRI3                                                                   0x05eb
>+#define mmMMEA2_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA2_SDP_ARB_DRAM                                                                           0x05ec
>+#define mmMMEA2_SDP_ARB_DRAM_BASE_IDX                                                                  1
>+#define mmMMEA2_SDP_ARB_GMI                                                                            0x05ed
>+#define mmMMEA2_SDP_ARB_GMI_BASE_IDX                                                                   1
>+#define mmMMEA2_SDP_ARB_FINAL                                                                          0x05ee
>+#define mmMMEA2_SDP_ARB_FINAL_BASE_IDX                                                                 1
>+#define mmMMEA2_SDP_DRAM_PRIORITY                                                                      0x05ef
>+#define mmMMEA2_SDP_DRAM_PRIORITY_BASE_IDX                                                             1
>+#define mmMMEA2_SDP_GMI_PRIORITY                                                                       0x05f0
>+#define mmMMEA2_SDP_GMI_PRIORITY_BASE_IDX                                                              1
>+#define mmMMEA2_SDP_IO_PRIORITY                                                                        0x05f1
>+#define mmMMEA2_SDP_IO_PRIORITY_BASE_IDX                                                               1
>+#define mmMMEA2_SDP_CREDITS                                                                            0x05f2
>+#define mmMMEA2_SDP_CREDITS_BASE_IDX                                                                   1
>+#define mmMMEA2_SDP_TAG_RESERVE0                                                                       0x05f3
>+#define mmMMEA2_SDP_TAG_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA2_SDP_TAG_RESERVE1                                                                       0x05f4
>+#define mmMMEA2_SDP_TAG_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA2_SDP_VCC_RESERVE0                                                                       0x05f5
>+#define mmMMEA2_SDP_VCC_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA2_SDP_VCC_RESERVE1                                                                       0x05f6
>+#define mmMMEA2_SDP_VCC_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA2_SDP_VCD_RESERVE0                                                                       0x05f7
>+#define mmMMEA2_SDP_VCD_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA2_SDP_VCD_RESERVE1                                                                       0x05f8
>+#define mmMMEA2_SDP_VCD_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA2_SDP_REQ_CNTL                                                                           0x05f9
>+#define mmMMEA2_SDP_REQ_CNTL_BASE_IDX                                                                  1
>+#define mmMMEA2_MISC                                                                                   0x05fa
>+#define mmMMEA2_MISC_BASE_IDX                                                                          1
>+#define mmMMEA2_LATENCY_SAMPLING                                                                       0x05fb
>+#define mmMMEA2_LATENCY_SAMPLING_BASE_IDX                                                              1
>+#define mmMMEA2_PERFCOUNTER_LO                                                                         0x05fc
>+#define mmMMEA2_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmMMEA2_PERFCOUNTER_HI                                                                         0x05fd
>+#define mmMMEA2_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmMMEA2_PERFCOUNTER0_CFG                                                                       0x05fe
>+#define mmMMEA2_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmMMEA2_PERFCOUNTER1_CFG                                                                       0x05ff
>+#define mmMMEA2_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmMMEA2_PERFCOUNTER_RSLT_CNTL                                                                  0x0600
>+#define mmMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmMMEA2_EDC_CNT                                                                                0x0606
>+#define mmMMEA2_EDC_CNT_BASE_IDX                                                                       1
>+#define mmMMEA2_EDC_CNT2                                                                               0x0607
>+#define mmMMEA2_EDC_CNT2_BASE_IDX                                                                      1
>+#define mmMMEA2_DSM_CNTL                                                                               0x0608
>+#define mmMMEA2_DSM_CNTL_BASE_IDX                                                                      1
>+#define mmMMEA2_DSM_CNTLA                                                                              0x0609
>+#define mmMMEA2_DSM_CNTLA_BASE_IDX                                                                     1
>+#define mmMMEA2_DSM_CNTLB                                                                              0x060a
>+#define mmMMEA2_DSM_CNTLB_BASE_IDX                                                                     1
>+#define mmMMEA2_DSM_CNTL2                                                                              0x060b
>+#define mmMMEA2_DSM_CNTL2_BASE_IDX                                                                     1
>+#define mmMMEA2_DSM_CNTL2A                                                                             0x060c
>+#define mmMMEA2_DSM_CNTL2A_BASE_IDX                                                                    1
>+#define mmMMEA2_DSM_CNTL2B                                                                             0x060d
>+#define mmMMEA2_DSM_CNTL2B_BASE_IDX                                                                    1
>+#define mmMMEA2_CGTT_CLK_CTRL                                                                          0x060f
>+#define mmMMEA2_CGTT_CLK_CTRL_BASE_IDX                                                                 1
>+#define mmMMEA2_EDC_MODE                                                                               0x0610
>+#define mmMMEA2_EDC_MODE_BASE_IDX                                                                      1
>+#define mmMMEA2_ERR_STATUS                                                                             0x0611
>+#define mmMMEA2_ERR_STATUS_BASE_IDX                                                                    1
>+#define mmMMEA2_MISC2                                                                                  0x0612
>+#define mmMMEA2_MISC2_BASE_IDX                                                                         1
>+#define mmMMEA2_ADDRDEC_SELECT                                                                         0x0613
>+#define mmMMEA2_ADDRDEC_SELECT_BASE_IDX                                                                1
>+#define mmMMEA2_EDC_CNT3                                                                               0x0614
>+#define mmMMEA2_EDC_CNT3_BASE_IDX                                                                      1
>+
>+
>+// addressBlock: mmhub_ea_mmeadec3
>+// base address: 0x69900
>+#define mmMMEA3_DRAM_RD_CLI2GRP_MAP0                                                                   0x0640
>+#define mmMMEA3_DRAM_RD_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA3_DRAM_RD_CLI2GRP_MAP1                                                                   0x0641
>+#define mmMMEA3_DRAM_RD_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA3_DRAM_WR_CLI2GRP_MAP0                                                                   0x0642
>+#define mmMMEA3_DRAM_WR_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA3_DRAM_WR_CLI2GRP_MAP1                                                                   0x0643
>+#define mmMMEA3_DRAM_WR_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA3_DRAM_RD_GRP2VC_MAP                                                                     0x0644
>+#define mmMMEA3_DRAM_RD_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA3_DRAM_WR_GRP2VC_MAP                                                                     0x0645
>+#define mmMMEA3_DRAM_WR_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA3_DRAM_RD_LAZY                                                                           0x0646
>+#define mmMMEA3_DRAM_RD_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA3_DRAM_WR_LAZY                                                                           0x0647
>+#define mmMMEA3_DRAM_WR_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA3_DRAM_RD_CAM_CNTL                                                                       0x0648
>+#define mmMMEA3_DRAM_RD_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA3_DRAM_WR_CAM_CNTL                                                                       0x0649
>+#define mmMMEA3_DRAM_WR_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA3_DRAM_PAGE_BURST                                                                        0x064a
>+#define mmMMEA3_DRAM_PAGE_BURST_BASE_IDX                                                               1
>+#define mmMMEA3_DRAM_RD_PRI_AGE                                                                        0x064b
>+#define mmMMEA3_DRAM_RD_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA3_DRAM_WR_PRI_AGE                                                                        0x064c
>+#define mmMMEA3_DRAM_WR_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA3_DRAM_RD_PRI_QUEUING                                                                    0x064d
>+#define mmMMEA3_DRAM_RD_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA3_DRAM_WR_PRI_QUEUING                                                                    0x064e
>+#define mmMMEA3_DRAM_WR_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA3_DRAM_RD_PRI_FIXED                                                                      0x064f
>+#define mmMMEA3_DRAM_RD_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA3_DRAM_WR_PRI_FIXED                                                                      0x0650
>+#define mmMMEA3_DRAM_WR_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA3_DRAM_RD_PRI_URGENCY                                                                    0x0651
>+#define mmMMEA3_DRAM_RD_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA3_DRAM_WR_PRI_URGENCY                                                                    0x0652
>+#define mmMMEA3_DRAM_WR_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1                                                                 0x0653
>+#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2                                                                 0x0654
>+#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3                                                                 0x0655
>+#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1                                                                 0x0656
>+#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2                                                                 0x0657
>+#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3                                                                 0x0658
>+#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA3_GMI_RD_CLI2GRP_MAP0                                                                    0x0659
>+#define mmMMEA3_GMI_RD_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA3_GMI_RD_CLI2GRP_MAP1                                                                    0x065a
>+#define mmMMEA3_GMI_RD_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA3_GMI_WR_CLI2GRP_MAP0                                                                    0x065b
>+#define mmMMEA3_GMI_WR_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA3_GMI_WR_CLI2GRP_MAP1                                                                    0x065c
>+#define mmMMEA3_GMI_WR_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA3_GMI_RD_GRP2VC_MAP                                                                      0x065d
>+#define mmMMEA3_GMI_RD_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA3_GMI_WR_GRP2VC_MAP                                                                      0x065e
>+#define mmMMEA3_GMI_WR_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA3_GMI_RD_LAZY                                                                            0x065f
>+#define mmMMEA3_GMI_RD_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA3_GMI_WR_LAZY                                                                            0x0660
>+#define mmMMEA3_GMI_WR_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA3_GMI_RD_CAM_CNTL                                                                        0x0661
>+#define mmMMEA3_GMI_RD_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA3_GMI_WR_CAM_CNTL                                                                        0x0662
>+#define mmMMEA3_GMI_WR_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA3_GMI_PAGE_BURST                                                                         0x0663
>+#define mmMMEA3_GMI_PAGE_BURST_BASE_IDX                                                                1
>+#define mmMMEA3_GMI_RD_PRI_AGE                                                                         0x0664
>+#define mmMMEA3_GMI_RD_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA3_GMI_WR_PRI_AGE                                                                         0x0665
>+#define mmMMEA3_GMI_WR_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA3_GMI_RD_PRI_QUEUING                                                                     0x0666
>+#define mmMMEA3_GMI_RD_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA3_GMI_WR_PRI_QUEUING                                                                     0x0667
>+#define mmMMEA3_GMI_WR_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA3_GMI_RD_PRI_FIXED                                                                       0x0668
>+#define mmMMEA3_GMI_RD_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA3_GMI_WR_PRI_FIXED                                                                       0x0669
>+#define mmMMEA3_GMI_WR_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA3_GMI_RD_PRI_URGENCY                                                                     0x066a
>+#define mmMMEA3_GMI_RD_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA3_GMI_WR_PRI_URGENCY                                                                     0x066b
>+#define mmMMEA3_GMI_WR_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING                                                             0x066c
>+#define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING                                                             0x066d
>+#define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA3_GMI_RD_PRI_QUANT_PRI1                                                                  0x066e
>+#define mmMMEA3_GMI_RD_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA3_GMI_RD_PRI_QUANT_PRI2                                                                  0x066f
>+#define mmMMEA3_GMI_RD_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA3_GMI_RD_PRI_QUANT_PRI3                                                                  0x0670
>+#define mmMMEA3_GMI_RD_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA3_GMI_WR_PRI_QUANT_PRI1                                                                  0x0671
>+#define mmMMEA3_GMI_WR_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA3_GMI_WR_PRI_QUANT_PRI2                                                                  0x0672
>+#define mmMMEA3_GMI_WR_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA3_GMI_WR_PRI_QUANT_PRI3                                                                  0x0673
>+#define mmMMEA3_GMI_WR_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA3_ADDRNORM_BASE_ADDR0                                                                    0x0674
>+#define mmMMEA3_ADDRNORM_BASE_ADDR0_BASE_IDX                                                           1
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR0                                                                   0x0675
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR0_BASE_IDX                                                          1
>+#define mmMMEA3_ADDRNORM_BASE_ADDR1                                                                    0x0676
>+#define mmMMEA3_ADDRNORM_BASE_ADDR1_BASE_IDX                                                           1
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR1                                                                   0x0677
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR1_BASE_IDX                                                          1
>+#define mmMMEA3_ADDRNORM_OFFSET_ADDR1                                                                  0x0678
>+#define mmMMEA3_ADDRNORM_OFFSET_ADDR1_BASE_IDX                                                         1
>+#define mmMMEA3_ADDRNORM_BASE_ADDR2                                                                    0x0679
>+#define mmMMEA3_ADDRNORM_BASE_ADDR2_BASE_IDX                                                           1
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR2                                                                   0x067a
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR2_BASE_IDX                                                          1
>+#define mmMMEA3_ADDRNORM_BASE_ADDR3                                                                    0x067b
>+#define mmMMEA3_ADDRNORM_BASE_ADDR3_BASE_IDX                                                           1
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR3                                                                   0x067c
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR3_BASE_IDX                                                          1
>+#define mmMMEA3_ADDRNORM_OFFSET_ADDR3                                                                  0x067d
>+#define mmMMEA3_ADDRNORM_OFFSET_ADDR3_BASE_IDX                                                         1
>+#define mmMMEA3_ADDRNORM_BASE_ADDR4                                                                    0x067e
>+#define mmMMEA3_ADDRNORM_BASE_ADDR4_BASE_IDX                                                           1
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR4                                                                   0x067f
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR4_BASE_IDX                                                          1
>+#define mmMMEA3_ADDRNORM_BASE_ADDR5                                                                    0x0680
>+#define mmMMEA3_ADDRNORM_BASE_ADDR5_BASE_IDX                                                           1
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR5                                                                   0x0681
>+#define mmMMEA3_ADDRNORM_LIMIT_ADDR5_BASE_IDX                                                          1
>+#define mmMMEA3_ADDRNORM_OFFSET_ADDR5                                                                  0x0682
>+#define mmMMEA3_ADDRNORM_OFFSET_ADDR5_BASE_IDX                                                         1
>+#define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL                                                                 0x0683
>+#define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRNORMGMI_HOLE_CNTL                                                                  0x0684
>+#define mmMMEA3_ADDRNORMGMI_HOLE_CNTL_BASE_IDX                                                         1
>+#define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG                                                           0x0685
>+#define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX                                                  1
>+#define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG                                                            0x0686
>+#define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX                                                   1
>+#define mmMMEA3_ADDRDEC_BANK_CFG                                                                       0x0687
>+#define mmMMEA3_ADDRDEC_BANK_CFG_BASE_IDX                                                              1
>+#define mmMMEA3_ADDRDEC_MISC_CFG                                                                       0x0688
>+#define mmMMEA3_ADDRDEC_MISC_CFG_BASE_IDX                                                              1
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0                                                            0x0689
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX                                                   1
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1                                                            0x068a
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX                                                   1
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2                                                            0x068b
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX                                                   1
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3                                                            0x068c
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX                                                   1
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4                                                            0x068d
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX                                                   1
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5                                                            0x068e
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX                                                   1
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC                                                               0x068f
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2                                                              0x0690
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0                                                              0x0691
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1                                                              0x0692
>+#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE                                                             0x0693
>+#define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0                                                             0x0694
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1                                                             0x0695
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2                                                             0x0696
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3                                                             0x0697
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4                                                             0x0698
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5                                                             0x0699
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC                                                                0x069a
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2                                                               0x069b
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0                                                               0x069c
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1                                                               0x069d
>+#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE                                                              0x069e
>+#define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0                                                                 0x069f
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1                                                                 0x06a0
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2                                                                 0x06a1
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3                                                                 0x06a2
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0                                                              0x06a3
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1                                                              0x06a4
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2                                                              0x06a5
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3                                                              0x06a6
>+#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01                                                                0x06a7
>+#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23                                                                0x06a8
>+#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01                                                             0x06a9
>+#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23                                                             0x06aa
>+#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01                                                                 0x06ab
>+#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23                                                                 0x06ac
>+#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01                                                                 0x06ad
>+#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23                                                                 0x06ae
>+#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01                                                                0x06af
>+#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23                                                                0x06b0
>+#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01                                                               0x06b1
>+#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23                                                               0x06b2
>+#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01                                                               0x06b3
>+#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23                                                               0x06b4
>+#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDEC0_RM_SEL_CS01                                                                   0x06b5
>+#define mmMMEA3_ADDRDEC0_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA3_ADDRDEC0_RM_SEL_CS23                                                                   0x06b6
>+#define mmMMEA3_ADDRDEC0_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01                                                                0x06b7
>+#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23                                                                0x06b8
>+#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0                                                                 0x06b9
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1                                                                 0x06ba
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2                                                                 0x06bb
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3                                                                 0x06bc
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0                                                              0x06bd
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1                                                              0x06be
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2                                                              0x06bf
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3                                                              0x06c0
>+#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01                                                                0x06c1
>+#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23                                                                0x06c2
>+#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01                                                             0x06c3
>+#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23                                                             0x06c4
>+#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01                                                                 0x06c5
>+#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23                                                                 0x06c6
>+#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01                                                                 0x06c7
>+#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23                                                                 0x06c8
>+#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01                                                                0x06c9
>+#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23                                                                0x06ca
>+#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01                                                               0x06cb
>+#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23                                                               0x06cc
>+#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01                                                               0x06cd
>+#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23                                                               0x06ce
>+#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDEC1_RM_SEL_CS01                                                                   0x06cf
>+#define mmMMEA3_ADDRDEC1_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA3_ADDRDEC1_RM_SEL_CS23                                                                   0x06d0
>+#define mmMMEA3_ADDRDEC1_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01                                                                0x06d1
>+#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23                                                                0x06d2
>+#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0                                                                 0x06d3
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1                                                                 0x06d4
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2                                                                 0x06d5
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3                                                                 0x06d6
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0                                                              0x06d7
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1                                                              0x06d8
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2                                                              0x06d9
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3                                                              0x06da
>+#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01                                                                0x06db
>+#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23                                                                0x06dc
>+#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01                                                             0x06dd
>+#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23                                                             0x06de
>+#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01                                                                 0x06df
>+#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23                                                                 0x06e0
>+#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01                                                                 0x06e1
>+#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23                                                                 0x06e2
>+#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01                                                                0x06e3
>+#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23                                                                0x06e4
>+#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01                                                               0x06e5
>+#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23                                                               0x06e6
>+#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01                                                               0x06e7
>+#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23                                                               0x06e8
>+#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRDEC2_RM_SEL_CS01                                                                   0x06e9
>+#define mmMMEA3_ADDRDEC2_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA3_ADDRDEC2_RM_SEL_CS23                                                                   0x06ea
>+#define mmMMEA3_ADDRDEC2_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01                                                                0x06eb
>+#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23                                                                0x06ec
>+#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL                                                               0x06ed
>+#define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX                                                      1
>+#define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL                                                                0x06ee
>+#define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX                                                       1
>+#define mmMMEA3_IO_RD_CLI2GRP_MAP0                                                                     0x0715
>+#define mmMMEA3_IO_RD_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA3_IO_RD_CLI2GRP_MAP1                                                                     0x0716
>+#define mmMMEA3_IO_RD_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA3_IO_WR_CLI2GRP_MAP0                                                                     0x0717
>+#define mmMMEA3_IO_WR_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA3_IO_WR_CLI2GRP_MAP1                                                                     0x0718
>+#define mmMMEA3_IO_WR_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA3_IO_RD_COMBINE_FLUSH                                                                    0x0719
>+#define mmMMEA3_IO_RD_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA3_IO_WR_COMBINE_FLUSH                                                                    0x071a
>+#define mmMMEA3_IO_WR_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA3_IO_GROUP_BURST                                                                         0x071b
>+#define mmMMEA3_IO_GROUP_BURST_BASE_IDX                                                                1
>+#define mmMMEA3_IO_RD_PRI_AGE                                                                          0x071c
>+#define mmMMEA3_IO_RD_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA3_IO_WR_PRI_AGE                                                                          0x071d
>+#define mmMMEA3_IO_WR_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA3_IO_RD_PRI_QUEUING                                                                      0x071e
>+#define mmMMEA3_IO_RD_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA3_IO_WR_PRI_QUEUING                                                                      0x071f
>+#define mmMMEA3_IO_WR_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA3_IO_RD_PRI_FIXED                                                                        0x0720
>+#define mmMMEA3_IO_RD_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA3_IO_WR_PRI_FIXED                                                                        0x0721
>+#define mmMMEA3_IO_WR_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA3_IO_RD_PRI_URGENCY                                                                      0x0722
>+#define mmMMEA3_IO_RD_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA3_IO_WR_PRI_URGENCY                                                                      0x0723
>+#define mmMMEA3_IO_WR_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA3_IO_RD_PRI_URGENCY_MASKING                                                              0x0724
>+#define mmMMEA3_IO_RD_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA3_IO_WR_PRI_URGENCY_MASKING                                                              0x0725
>+#define mmMMEA3_IO_WR_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA3_IO_RD_PRI_QUANT_PRI1                                                                   0x0726
>+#define mmMMEA3_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA3_IO_RD_PRI_QUANT_PRI2                                                                   0x0727
>+#define mmMMEA3_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA3_IO_RD_PRI_QUANT_PRI3                                                                   0x0728
>+#define mmMMEA3_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA3_IO_WR_PRI_QUANT_PRI1                                                                   0x0729
>+#define mmMMEA3_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA3_IO_WR_PRI_QUANT_PRI2                                                                   0x072a
>+#define mmMMEA3_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA3_IO_WR_PRI_QUANT_PRI3                                                                   0x072b
>+#define mmMMEA3_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA3_SDP_ARB_DRAM                                                                           0x072c
>+#define mmMMEA3_SDP_ARB_DRAM_BASE_IDX                                                                  1
>+#define mmMMEA3_SDP_ARB_GMI                                                                            0x072d
>+#define mmMMEA3_SDP_ARB_GMI_BASE_IDX                                                                   1
>+#define mmMMEA3_SDP_ARB_FINAL                                                                          0x072e
>+#define mmMMEA3_SDP_ARB_FINAL_BASE_IDX                                                                 1
>+#define mmMMEA3_SDP_DRAM_PRIORITY                                                                      0x072f
>+#define mmMMEA3_SDP_DRAM_PRIORITY_BASE_IDX                                                             1
>+#define mmMMEA3_SDP_GMI_PRIORITY                                                                       0x0730
>+#define mmMMEA3_SDP_GMI_PRIORITY_BASE_IDX                                                              1
>+#define mmMMEA3_SDP_IO_PRIORITY                                                                        0x0731
>+#define mmMMEA3_SDP_IO_PRIORITY_BASE_IDX                                                               1
>+#define mmMMEA3_SDP_CREDITS                                                                            0x0732
>+#define mmMMEA3_SDP_CREDITS_BASE_IDX                                                                   1
>+#define mmMMEA3_SDP_TAG_RESERVE0                                                                       0x0733
>+#define mmMMEA3_SDP_TAG_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA3_SDP_TAG_RESERVE1                                                                       0x0734
>+#define mmMMEA3_SDP_TAG_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA3_SDP_VCC_RESERVE0                                                                       0x0735
>+#define mmMMEA3_SDP_VCC_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA3_SDP_VCC_RESERVE1                                                                       0x0736
>+#define mmMMEA3_SDP_VCC_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA3_SDP_VCD_RESERVE0                                                                       0x0737
>+#define mmMMEA3_SDP_VCD_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA3_SDP_VCD_RESERVE1                                                                       0x0738
>+#define mmMMEA3_SDP_VCD_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA3_SDP_REQ_CNTL                                                                           0x0739
>+#define mmMMEA3_SDP_REQ_CNTL_BASE_IDX                                                                  1
>+#define mmMMEA3_MISC                                                                                   0x073a
>+#define mmMMEA3_MISC_BASE_IDX                                                                          1
>+#define mmMMEA3_LATENCY_SAMPLING                                                                       0x073b
>+#define mmMMEA3_LATENCY_SAMPLING_BASE_IDX                                                              1
>+#define mmMMEA3_PERFCOUNTER_LO                                                                         0x073c
>+#define mmMMEA3_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmMMEA3_PERFCOUNTER_HI                                                                         0x073d
>+#define mmMMEA3_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmMMEA3_PERFCOUNTER0_CFG                                                                       0x073e
>+#define mmMMEA3_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmMMEA3_PERFCOUNTER1_CFG                                                                       0x073f
>+#define mmMMEA3_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmMMEA3_PERFCOUNTER_RSLT_CNTL                                                                  0x0740
>+#define mmMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmMMEA3_EDC_CNT                                                                                0x0746
>+#define mmMMEA3_EDC_CNT_BASE_IDX                                                                       1
>+#define mmMMEA3_EDC_CNT2                                                                               0x0747
>+#define mmMMEA3_EDC_CNT2_BASE_IDX                                                                      1
>+#define mmMMEA3_DSM_CNTL                                                                               0x0748
>+#define mmMMEA3_DSM_CNTL_BASE_IDX                                                                      1
>+#define mmMMEA3_DSM_CNTLA                                                                              0x0749
>+#define mmMMEA3_DSM_CNTLA_BASE_IDX                                                                     1
>+#define mmMMEA3_DSM_CNTLB                                                                              0x074a
>+#define mmMMEA3_DSM_CNTLB_BASE_IDX                                                                     1
>+#define mmMMEA3_DSM_CNTL2                                                                              0x074b
>+#define mmMMEA3_DSM_CNTL2_BASE_IDX                                                                     1
>+#define mmMMEA3_DSM_CNTL2A                                                                             0x074c
>+#define mmMMEA3_DSM_CNTL2A_BASE_IDX                                                                    1
>+#define mmMMEA3_DSM_CNTL2B                                                                             0x074d
>+#define mmMMEA3_DSM_CNTL2B_BASE_IDX                                                                    1
>+#define mmMMEA3_CGTT_CLK_CTRL                                                                          0x074f
>+#define mmMMEA3_CGTT_CLK_CTRL_BASE_IDX                                                                 1
>+#define mmMMEA3_EDC_MODE                                                                               0x0750
>+#define mmMMEA3_EDC_MODE_BASE_IDX                                                                      1
>+#define mmMMEA3_ERR_STATUS                                                                             0x0751
>+#define mmMMEA3_ERR_STATUS_BASE_IDX                                                                    1
>+#define mmMMEA3_MISC2                                                                                  0x0752
>+#define mmMMEA3_MISC2_BASE_IDX                                                                         1
>+#define mmMMEA3_ADDRDEC_SELECT                                                                         0x0753
>+#define mmMMEA3_ADDRDEC_SELECT_BASE_IDX                                                                1
>+#define mmMMEA3_EDC_CNT3                                                                               0x0754
>+#define mmMMEA3_EDC_CNT3_BASE_IDX                                                                      1
>+
>+
>+// addressBlock: mmhub_ea_mmeadec4
>+// base address: 0x69e00
>+#define mmMMEA4_DRAM_RD_CLI2GRP_MAP0                                                                   0x0780
>+#define mmMMEA4_DRAM_RD_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA4_DRAM_RD_CLI2GRP_MAP1                                                                   0x0781
>+#define mmMMEA4_DRAM_RD_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA4_DRAM_WR_CLI2GRP_MAP0                                                                   0x0782
>+#define mmMMEA4_DRAM_WR_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA4_DRAM_WR_CLI2GRP_MAP1                                                                   0x0783
>+#define mmMMEA4_DRAM_WR_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA4_DRAM_RD_GRP2VC_MAP                                                                     0x0784
>+#define mmMMEA4_DRAM_RD_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA4_DRAM_WR_GRP2VC_MAP                                                                     0x0785
>+#define mmMMEA4_DRAM_WR_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA4_DRAM_RD_LAZY                                                                           0x0786
>+#define mmMMEA4_DRAM_RD_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA4_DRAM_WR_LAZY                                                                           0x0787
>+#define mmMMEA4_DRAM_WR_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA4_DRAM_RD_CAM_CNTL                                                                       0x0788
>+#define mmMMEA4_DRAM_RD_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA4_DRAM_WR_CAM_CNTL                                                                       0x0789
>+#define mmMMEA4_DRAM_WR_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA4_DRAM_PAGE_BURST                                                                        0x078a
>+#define mmMMEA4_DRAM_PAGE_BURST_BASE_IDX                                                               1
>+#define mmMMEA4_DRAM_RD_PRI_AGE                                                                        0x078b
>+#define mmMMEA4_DRAM_RD_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA4_DRAM_WR_PRI_AGE                                                                        0x078c
>+#define mmMMEA4_DRAM_WR_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA4_DRAM_RD_PRI_QUEUING                                                                    0x078d
>+#define mmMMEA4_DRAM_RD_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA4_DRAM_WR_PRI_QUEUING                                                                    0x078e
>+#define mmMMEA4_DRAM_WR_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA4_DRAM_RD_PRI_FIXED                                                                      0x078f
>+#define mmMMEA4_DRAM_RD_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA4_DRAM_WR_PRI_FIXED                                                                      0x0790
>+#define mmMMEA4_DRAM_WR_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA4_DRAM_RD_PRI_URGENCY                                                                    0x0791
>+#define mmMMEA4_DRAM_RD_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA4_DRAM_WR_PRI_URGENCY                                                                    0x0792
>+#define mmMMEA4_DRAM_WR_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1                                                                 0x0793
>+#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2                                                                 0x0794
>+#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3                                                                 0x0795
>+#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1                                                                 0x0796
>+#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2                                                                 0x0797
>+#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3                                                                 0x0798
>+#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA4_GMI_RD_CLI2GRP_MAP0                                                                    0x0799
>+#define mmMMEA4_GMI_RD_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA4_GMI_RD_CLI2GRP_MAP1                                                                    0x079a
>+#define mmMMEA4_GMI_RD_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA4_GMI_WR_CLI2GRP_MAP0                                                                    0x079b
>+#define mmMMEA4_GMI_WR_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA4_GMI_WR_CLI2GRP_MAP1                                                                    0x079c
>+#define mmMMEA4_GMI_WR_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA4_GMI_RD_GRP2VC_MAP                                                                      0x079d
>+#define mmMMEA4_GMI_RD_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA4_GMI_WR_GRP2VC_MAP                                                                      0x079e
>+#define mmMMEA4_GMI_WR_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA4_GMI_RD_LAZY                                                                            0x079f
>+#define mmMMEA4_GMI_RD_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA4_GMI_WR_LAZY                                                                            0x07a0
>+#define mmMMEA4_GMI_WR_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA4_GMI_RD_CAM_CNTL                                                                        0x07a1
>+#define mmMMEA4_GMI_RD_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA4_GMI_WR_CAM_CNTL                                                                        0x07a2
>+#define mmMMEA4_GMI_WR_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA4_GMI_PAGE_BURST                                                                         0x07a3
>+#define mmMMEA4_GMI_PAGE_BURST_BASE_IDX                                                                1
>+#define mmMMEA4_GMI_RD_PRI_AGE                                                                         0x07a4
>+#define mmMMEA4_GMI_RD_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA4_GMI_WR_PRI_AGE                                                                         0x07a5
>+#define mmMMEA4_GMI_WR_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA4_GMI_RD_PRI_QUEUING                                                                     0x07a6
>+#define mmMMEA4_GMI_RD_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA4_GMI_WR_PRI_QUEUING                                                                     0x07a7
>+#define mmMMEA4_GMI_WR_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA4_GMI_RD_PRI_FIXED                                                                       0x07a8
>+#define mmMMEA4_GMI_RD_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA4_GMI_WR_PRI_FIXED                                                                       0x07a9
>+#define mmMMEA4_GMI_WR_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA4_GMI_RD_PRI_URGENCY                                                                     0x07aa
>+#define mmMMEA4_GMI_RD_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA4_GMI_WR_PRI_URGENCY                                                                     0x07ab
>+#define mmMMEA4_GMI_WR_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING                                                             0x07ac
>+#define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING                                                             0x07ad
>+#define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA4_GMI_RD_PRI_QUANT_PRI1                                                                  0x07ae
>+#define mmMMEA4_GMI_RD_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA4_GMI_RD_PRI_QUANT_PRI2                                                                  0x07af
>+#define mmMMEA4_GMI_RD_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA4_GMI_RD_PRI_QUANT_PRI3                                                                  0x07b0
>+#define mmMMEA4_GMI_RD_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA4_GMI_WR_PRI_QUANT_PRI1                                                                  0x07b1
>+#define mmMMEA4_GMI_WR_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA4_GMI_WR_PRI_QUANT_PRI2                                                                  0x07b2
>+#define mmMMEA4_GMI_WR_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA4_GMI_WR_PRI_QUANT_PRI3                                                                  0x07b3
>+#define mmMMEA4_GMI_WR_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA4_ADDRNORM_BASE_ADDR0                                                                    0x07b4
>+#define mmMMEA4_ADDRNORM_BASE_ADDR0_BASE_IDX                                                           1
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR0                                                                   0x07b5
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR0_BASE_IDX                                                          1
>+#define mmMMEA4_ADDRNORM_BASE_ADDR1                                                                    0x07b6
>+#define mmMMEA4_ADDRNORM_BASE_ADDR1_BASE_IDX                                                           1
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR1                                                                   0x07b7
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR1_BASE_IDX                                                          1
>+#define mmMMEA4_ADDRNORM_OFFSET_ADDR1                                                                  0x07b8
>+#define mmMMEA4_ADDRNORM_OFFSET_ADDR1_BASE_IDX                                                         1
>+#define mmMMEA4_ADDRNORM_BASE_ADDR2                                                                    0x07b9
>+#define mmMMEA4_ADDRNORM_BASE_ADDR2_BASE_IDX                                                           1
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR2                                                                   0x07ba
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR2_BASE_IDX                                                          1
>+#define mmMMEA4_ADDRNORM_BASE_ADDR3                                                                    0x07bb
>+#define mmMMEA4_ADDRNORM_BASE_ADDR3_BASE_IDX                                                           1
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR3                                                                   0x07bc
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR3_BASE_IDX                                                          1
>+#define mmMMEA4_ADDRNORM_OFFSET_ADDR3                                                                  0x07bd
>+#define mmMMEA4_ADDRNORM_OFFSET_ADDR3_BASE_IDX                                                         1
>+#define mmMMEA4_ADDRNORM_BASE_ADDR4                                                                    0x07be
>+#define mmMMEA4_ADDRNORM_BASE_ADDR4_BASE_IDX                                                           1
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR4                                                                   0x07bf
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR4_BASE_IDX                                                          1
>+#define mmMMEA4_ADDRNORM_BASE_ADDR5                                                                    0x07c0
>+#define mmMMEA4_ADDRNORM_BASE_ADDR5_BASE_IDX                                                           1
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR5                                                                   0x07c1
>+#define mmMMEA4_ADDRNORM_LIMIT_ADDR5_BASE_IDX                                                          1
>+#define mmMMEA4_ADDRNORM_OFFSET_ADDR5                                                                  0x07c2
>+#define mmMMEA4_ADDRNORM_OFFSET_ADDR5_BASE_IDX                                                         1
>+#define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL                                                                 0x07c3
>+#define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRNORMGMI_HOLE_CNTL                                                                  0x07c4
>+#define mmMMEA4_ADDRNORMGMI_HOLE_CNTL_BASE_IDX                                                         1
>+#define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG                                                           0x07c5
>+#define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX                                                  1
>+#define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG                                                            0x07c6
>+#define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX                                                   1
>+#define mmMMEA4_ADDRDEC_BANK_CFG                                                                       0x07c7
>+#define mmMMEA4_ADDRDEC_BANK_CFG_BASE_IDX                                                              1
>+#define mmMMEA4_ADDRDEC_MISC_CFG                                                                       0x07c8
>+#define mmMMEA4_ADDRDEC_MISC_CFG_BASE_IDX                                                              1
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0                                                            0x07c9
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX                                                   1
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1                                                            0x07ca
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX                                                   1
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2                                                            0x07cb
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX                                                   1
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3                                                            0x07cc
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX                                                   1
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4                                                            0x07cd
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX                                                   1
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5                                                            0x07ce
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX                                                   1
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC                                                               0x07cf
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2                                                              0x07d0
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0                                                              0x07d1
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1                                                              0x07d2
>+#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE                                                             0x07d3
>+#define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0                                                             0x07d4
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1                                                             0x07d5
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2                                                             0x07d6
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3                                                             0x07d7
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4                                                             0x07d8
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5                                                             0x07d9
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC                                                                0x07da
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2                                                               0x07db
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0                                                               0x07dc
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1                                                               0x07dd
>+#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE                                                              0x07de
>+#define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0                                                                 0x07df
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1                                                                 0x07e0
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2                                                                 0x07e1
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3                                                                 0x07e2
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0                                                              0x07e3
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1                                                              0x07e4
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2                                                              0x07e5
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3                                                              0x07e6
>+#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01                                                                0x07e7
>+#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23                                                                0x07e8
>+#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01                                                             0x07e9
>+#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23                                                             0x07ea
>+#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01                                                                 0x07eb
>+#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23                                                                 0x07ec
>+#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01                                                                 0x07ed
>+#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23                                                                 0x07ee
>+#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01                                                                0x07ef
>+#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23                                                                0x07f0
>+#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01                                                               0x07f1
>+#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23                                                               0x07f2
>+#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01                                                               0x07f3
>+#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23                                                               0x07f4
>+#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDEC0_RM_SEL_CS01                                                                   0x07f5
>+#define mmMMEA4_ADDRDEC0_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA4_ADDRDEC0_RM_SEL_CS23                                                                   0x07f6
>+#define mmMMEA4_ADDRDEC0_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01                                                                0x07f7
>+#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23                                                                0x07f8
>+#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0                                                                 0x07f9
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1                                                                 0x07fa
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2                                                                 0x07fb
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3                                                                 0x07fc
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0                                                              0x07fd
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1                                                              0x07fe
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2                                                              0x07ff
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3                                                              0x0800
>+#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01                                                                0x0801
>+#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23                                                                0x0802
>+#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01                                                             0x0803
>+#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23                                                             0x0804
>+#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01                                                                 0x0805
>+#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23                                                                 0x0806
>+#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01                                                                 0x0807
>+#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23                                                                 0x0808
>+#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01                                                                0x0809
>+#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23                                                                0x080a
>+#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01                                                               0x080b
>+#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23                                                               0x080c
>+#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01                                                               0x080d
>+#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23                                                               0x080e
>+#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDEC1_RM_SEL_CS01                                                                   0x080f
>+#define mmMMEA4_ADDRDEC1_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA4_ADDRDEC1_RM_SEL_CS23                                                                   0x0810
>+#define mmMMEA4_ADDRDEC1_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01                                                                0x0811
>+#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23                                                                0x0812
>+#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0                                                                 0x0813
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1                                                                 0x0814
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2                                                                 0x0815
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3                                                                 0x0816
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0                                                              0x0817
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1                                                              0x0818
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2                                                              0x0819
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3                                                              0x081a
>+#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01                                                                0x081b
>+#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23                                                                0x081c
>+#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01                                                             0x081d
>+#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23                                                             0x081e
>+#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01                                                                 0x081f
>+#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23                                                                 0x0820
>+#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01                                                                 0x0821
>+#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23                                                                 0x0822
>+#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01                                                                0x0823
>+#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23                                                                0x0824
>+#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01                                                               0x0825
>+#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23                                                               0x0826
>+#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01                                                               0x0827
>+#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23                                                               0x0828
>+#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRDEC2_RM_SEL_CS01                                                                   0x0829
>+#define mmMMEA4_ADDRDEC2_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA4_ADDRDEC2_RM_SEL_CS23                                                                   0x082a
>+#define mmMMEA4_ADDRDEC2_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01                                                                0x082b
>+#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23                                                                0x082c
>+#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL                                                               0x082d
>+#define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX                                                      1
>+#define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL                                                                0x082e
>+#define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX                                                       1
>+#define mmMMEA4_IO_RD_CLI2GRP_MAP0                                                                     0x0855
>+#define mmMMEA4_IO_RD_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA4_IO_RD_CLI2GRP_MAP1                                                                     0x0856
>+#define mmMMEA4_IO_RD_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA4_IO_WR_CLI2GRP_MAP0                                                                     0x0857
>+#define mmMMEA4_IO_WR_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA4_IO_WR_CLI2GRP_MAP1                                                                     0x0858
>+#define mmMMEA4_IO_WR_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA4_IO_RD_COMBINE_FLUSH                                                                    0x0859
>+#define mmMMEA4_IO_RD_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA4_IO_WR_COMBINE_FLUSH                                                                    0x085a
>+#define mmMMEA4_IO_WR_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA4_IO_GROUP_BURST                                                                         0x085b
>+#define mmMMEA4_IO_GROUP_BURST_BASE_IDX                                                                1
>+#define mmMMEA4_IO_RD_PRI_AGE                                                                          0x085c
>+#define mmMMEA4_IO_RD_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA4_IO_WR_PRI_AGE                                                                          0x085d
>+#define mmMMEA4_IO_WR_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA4_IO_RD_PRI_QUEUING                                                                      0x085e
>+#define mmMMEA4_IO_RD_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA4_IO_WR_PRI_QUEUING                                                                      0x085f
>+#define mmMMEA4_IO_WR_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA4_IO_RD_PRI_FIXED                                                                        0x0860
>+#define mmMMEA4_IO_RD_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA4_IO_WR_PRI_FIXED                                                                        0x0861
>+#define mmMMEA4_IO_WR_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA4_IO_RD_PRI_URGENCY                                                                      0x0862
>+#define mmMMEA4_IO_RD_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA4_IO_WR_PRI_URGENCY                                                                      0x0863
>+#define mmMMEA4_IO_WR_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA4_IO_RD_PRI_URGENCY_MASKING                                                              0x0864
>+#define mmMMEA4_IO_RD_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA4_IO_WR_PRI_URGENCY_MASKING                                                              0x0865
>+#define mmMMEA4_IO_WR_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA4_IO_RD_PRI_QUANT_PRI1                                                                   0x0866
>+#define mmMMEA4_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA4_IO_RD_PRI_QUANT_PRI2                                                                   0x0867
>+#define mmMMEA4_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA4_IO_RD_PRI_QUANT_PRI3                                                                   0x0868
>+#define mmMMEA4_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA4_IO_WR_PRI_QUANT_PRI1                                                                   0x0869
>+#define mmMMEA4_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA4_IO_WR_PRI_QUANT_PRI2                                                                   0x086a
>+#define mmMMEA4_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA4_IO_WR_PRI_QUANT_PRI3                                                                   0x086b
>+#define mmMMEA4_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA4_SDP_ARB_DRAM                                                                           0x086c
>+#define mmMMEA4_SDP_ARB_DRAM_BASE_IDX                                                                  1
>+#define mmMMEA4_SDP_ARB_GMI                                                                            0x086d
>+#define mmMMEA4_SDP_ARB_GMI_BASE_IDX                                                                   1
>+#define mmMMEA4_SDP_ARB_FINAL                                                                          0x086e
>+#define mmMMEA4_SDP_ARB_FINAL_BASE_IDX                                                                 1
>+#define mmMMEA4_SDP_DRAM_PRIORITY                                                                      0x086f
>+#define mmMMEA4_SDP_DRAM_PRIORITY_BASE_IDX                                                             1
>+#define mmMMEA4_SDP_GMI_PRIORITY                                                                       0x0870
>+#define mmMMEA4_SDP_GMI_PRIORITY_BASE_IDX                                                              1
>+#define mmMMEA4_SDP_IO_PRIORITY                                                                        0x0871
>+#define mmMMEA4_SDP_IO_PRIORITY_BASE_IDX                                                               1
>+#define mmMMEA4_SDP_CREDITS                                                                            0x0872
>+#define mmMMEA4_SDP_CREDITS_BASE_IDX                                                                   1
>+#define mmMMEA4_SDP_TAG_RESERVE0                                                                       0x0873
>+#define mmMMEA4_SDP_TAG_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA4_SDP_TAG_RESERVE1                                                                       0x0874
>+#define mmMMEA4_SDP_TAG_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA4_SDP_VCC_RESERVE0                                                                       0x0875
>+#define mmMMEA4_SDP_VCC_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA4_SDP_VCC_RESERVE1                                                                       0x0876
>+#define mmMMEA4_SDP_VCC_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA4_SDP_VCD_RESERVE0                                                                       0x0877
>+#define mmMMEA4_SDP_VCD_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA4_SDP_VCD_RESERVE1                                                                       0x0878
>+#define mmMMEA4_SDP_VCD_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA4_SDP_REQ_CNTL                                                                           0x0879
>+#define mmMMEA4_SDP_REQ_CNTL_BASE_IDX                                                                  1
>+#define mmMMEA4_MISC                                                                                   0x087a
>+#define mmMMEA4_MISC_BASE_IDX                                                                          1
>+#define mmMMEA4_LATENCY_SAMPLING                                                                       0x087b
>+#define mmMMEA4_LATENCY_SAMPLING_BASE_IDX                                                              1
>+#define mmMMEA4_PERFCOUNTER_LO                                                                         0x087c
>+#define mmMMEA4_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmMMEA4_PERFCOUNTER_HI                                                                         0x087d
>+#define mmMMEA4_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmMMEA4_PERFCOUNTER0_CFG                                                                       0x087e
>+#define mmMMEA4_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmMMEA4_PERFCOUNTER1_CFG                                                                       0x087f
>+#define mmMMEA4_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmMMEA4_PERFCOUNTER_RSLT_CNTL                                                                  0x0880
>+#define mmMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmMMEA4_EDC_CNT                                                                                0x0886
>+#define mmMMEA4_EDC_CNT_BASE_IDX                                                                       1
>+#define mmMMEA4_EDC_CNT2                                                                               0x0887
>+#define mmMMEA4_EDC_CNT2_BASE_IDX                                                                      1
>+#define mmMMEA4_DSM_CNTL                                                                               0x0888
>+#define mmMMEA4_DSM_CNTL_BASE_IDX                                                                      1
>+#define mmMMEA4_DSM_CNTLA                                                                              0x0889
>+#define mmMMEA4_DSM_CNTLA_BASE_IDX                                                                     1
>+#define mmMMEA4_DSM_CNTLB                                                                              0x088a
>+#define mmMMEA4_DSM_CNTLB_BASE_IDX                                                                     1
>+#define mmMMEA4_DSM_CNTL2                                                                              0x088b
>+#define mmMMEA4_DSM_CNTL2_BASE_IDX                                                                     1
>+#define mmMMEA4_DSM_CNTL2A                                                                             0x088c
>+#define mmMMEA4_DSM_CNTL2A_BASE_IDX                                                                    1
>+#define mmMMEA4_DSM_CNTL2B                                                                             0x088d
>+#define mmMMEA4_DSM_CNTL2B_BASE_IDX                                                                    1
>+#define mmMMEA4_CGTT_CLK_CTRL                                                                          0x088f
>+#define mmMMEA4_CGTT_CLK_CTRL_BASE_IDX                                                                 1
>+#define mmMMEA4_EDC_MODE                                                                               0x0890
>+#define mmMMEA4_EDC_MODE_BASE_IDX                                                                      1
>+#define mmMMEA4_ERR_STATUS                                                                             0x0891
>+#define mmMMEA4_ERR_STATUS_BASE_IDX                                                                    1
>+#define mmMMEA4_MISC2                                                                                  0x0892
>+#define mmMMEA4_MISC2_BASE_IDX                                                                         1
>+#define mmMMEA4_ADDRDEC_SELECT                                                                         0x0893
>+#define mmMMEA4_ADDRDEC_SELECT_BASE_IDX                                                                1
>+#define mmMMEA4_EDC_CNT3                                                                               0x0894
>+#define mmMMEA4_EDC_CNT3_BASE_IDX                                                                      1
>+
>+
>+// addressBlock: mmhub_pctldec0
>+// base address: 0x6a300
>+#define mmPCTL0_CTRL                                                                                   0x08c0
>+#define mmPCTL0_CTRL_BASE_IDX                                                                          1
>+#define mmPCTL0_MMHUB_DEEPSLEEP_IB                                                                     0x08c1
>+#define mmPCTL0_MMHUB_DEEPSLEEP_IB_BASE_IDX                                                            1
>+#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE                                                               0x08c2
>+#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX                                                      1
>+#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB                                                            0x08c3
>+#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX                                                   1
>+#define mmPCTL0_PG_IGNORE_DEEPSLEEP                                                                    0x08c4
>+#define mmPCTL0_PG_IGNORE_DEEPSLEEP_BASE_IDX                                                           1
>+#define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB                                                                 0x08c5
>+#define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX                                                        1
>+#define mmPCTL0_SLICE0_CFG_DAGB_BUSY                                                                   0x08c6
>+#define mmPCTL0_SLICE0_CFG_DAGB_BUSY_BASE_IDX                                                          1
>+#define mmPCTL0_SLICE0_CFG_DS_ALLOW                                                                    0x08c7
>+#define mmPCTL0_SLICE0_CFG_DS_ALLOW_BASE_IDX                                                           1
>+#define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB                                                                 0x08c8
>+#define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX                                                        1
>+#define mmPCTL0_SLICE1_CFG_DAGB_BUSY                                                                   0x08c9
>+#define mmPCTL0_SLICE1_CFG_DAGB_BUSY_BASE_IDX                                                          1
>+#define mmPCTL0_SLICE1_CFG_DS_ALLOW                                                                    0x08ca
>+#define mmPCTL0_SLICE1_CFG_DS_ALLOW_BASE_IDX                                                           1
>+#define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB                                                                 0x08cb
>+#define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX                                                        1
>+#define mmPCTL0_SLICE2_CFG_DAGB_BUSY                                                                   0x08cc
>+#define mmPCTL0_SLICE2_CFG_DAGB_BUSY_BASE_IDX                                                          1
>+#define mmPCTL0_SLICE2_CFG_DS_ALLOW                                                                    0x08cd
>+#define mmPCTL0_SLICE2_CFG_DS_ALLOW_BASE_IDX                                                           1
>+#define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB                                                                 0x08ce
>+#define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX                                                        1
>+#define mmPCTL0_SLICE3_CFG_DAGB_BUSY                                                                   0x08cf
>+#define mmPCTL0_SLICE3_CFG_DAGB_BUSY_BASE_IDX                                                          1
>+#define mmPCTL0_SLICE3_CFG_DS_ALLOW                                                                    0x08d0
>+#define mmPCTL0_SLICE3_CFG_DS_ALLOW_BASE_IDX                                                           1
>+#define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB                                                                 0x08d1
>+#define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX                                                        1
>+#define mmPCTL0_SLICE4_CFG_DAGB_BUSY                                                                   0x08d2
>+#define mmPCTL0_SLICE4_CFG_DAGB_BUSY_BASE_IDX                                                          1
>+#define mmPCTL0_SLICE4_CFG_DS_ALLOW                                                                    0x08d3
>+#define mmPCTL0_SLICE4_CFG_DS_ALLOW_BASE_IDX                                                           1
>+#define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB                                                                 0x08d4
>+#define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX                                                        1
>+#define mmPCTL0_UTCL2_MISC                                                                             0x08d5
>+#define mmPCTL0_UTCL2_MISC_BASE_IDX                                                                    1
>+#define mmPCTL0_SLICE0_MISC                                                                            0x08d6
>+#define mmPCTL0_SLICE0_MISC_BASE_IDX                                                                   1
>+#define mmPCTL0_SLICE1_MISC                                                                            0x08d7
>+#define mmPCTL0_SLICE1_MISC_BASE_IDX                                                                   1
>+#define mmPCTL0_SLICE2_MISC                                                                            0x08d8
>+#define mmPCTL0_SLICE2_MISC_BASE_IDX                                                                   1
>+#define mmPCTL0_SLICE3_MISC                                                                            0x08d9
>+#define mmPCTL0_SLICE3_MISC_BASE_IDX                                                                   1
>+#define mmPCTL0_SLICE4_MISC                                                                            0x08da
>+#define mmPCTL0_SLICE4_MISC_BASE_IDX                                                                   1
>+#define mmPCTL0_UTCL2_RENG_EXECUTE                                                                     0x08db
>+#define mmPCTL0_UTCL2_RENG_EXECUTE_BASE_IDX                                                            1
>+#define mmPCTL0_SLICE0_RENG_EXECUTE                                                                    0x08dc
>+#define mmPCTL0_SLICE0_RENG_EXECUTE_BASE_IDX                                                           1
>+#define mmPCTL0_SLICE1_RENG_EXECUTE                                                                    0x08dd
>+#define mmPCTL0_SLICE1_RENG_EXECUTE_BASE_IDX                                                           1
>+#define mmPCTL0_SLICE2_RENG_EXECUTE                                                                    0x08de
>+#define mmPCTL0_SLICE2_RENG_EXECUTE_BASE_IDX                                                           1
>+#define mmPCTL0_SLICE3_RENG_EXECUTE                                                                    0x08df
>+#define mmPCTL0_SLICE3_RENG_EXECUTE_BASE_IDX                                                           1
>+#define mmPCTL0_SLICE4_RENG_EXECUTE                                                                    0x08e0
>+#define mmPCTL0_SLICE4_RENG_EXECUTE_BASE_IDX                                                           1
>+#define mmPCTL0_UTCL2_RENG_RAM_INDEX                                                                   0x08e1
>+#define mmPCTL0_UTCL2_RENG_RAM_INDEX_BASE_IDX                                                          1
>+#define mmPCTL0_UTCL2_RENG_RAM_DATA                                                                    0x08e2
>+#define mmPCTL0_UTCL2_RENG_RAM_DATA_BASE_IDX                                                           1
>+#define mmPCTL0_SLICE0_RENG_RAM_INDEX                                                                  0x08e3
>+#define mmPCTL0_SLICE0_RENG_RAM_INDEX_BASE_IDX                                                         1
>+#define mmPCTL0_SLICE0_RENG_RAM_DATA                                                                   0x08e4
>+#define mmPCTL0_SLICE0_RENG_RAM_DATA_BASE_IDX                                                          1
>+#define mmPCTL0_SLICE1_RENG_RAM_INDEX                                                                  0x08e5
>+#define mmPCTL0_SLICE1_RENG_RAM_INDEX_BASE_IDX                                                         1
>+#define mmPCTL0_SLICE1_RENG_RAM_DATA                                                                   0x08e6
>+#define mmPCTL0_SLICE1_RENG_RAM_DATA_BASE_IDX                                                          1
>+#define mmPCTL0_SLICE2_RENG_RAM_INDEX                                                                  0x08e7
>+#define mmPCTL0_SLICE2_RENG_RAM_INDEX_BASE_IDX                                                         1
>+#define mmPCTL0_SLICE2_RENG_RAM_DATA                                                                   0x08e8
>+#define mmPCTL0_SLICE2_RENG_RAM_DATA_BASE_IDX                                                          1
>+#define mmPCTL0_SLICE3_RENG_RAM_INDEX                                                                  0x08e9
>+#define mmPCTL0_SLICE3_RENG_RAM_INDEX_BASE_IDX                                                         1
>+#define mmPCTL0_SLICE3_RENG_RAM_DATA                                                                   0x08ea
>+#define mmPCTL0_SLICE3_RENG_RAM_DATA_BASE_IDX                                                          1
>+#define mmPCTL0_SLICE4_RENG_RAM_INDEX                                                                  0x08eb
>+#define mmPCTL0_SLICE4_RENG_RAM_INDEX_BASE_IDX                                                         1
>+#define mmPCTL0_SLICE4_RENG_RAM_DATA                                                                   0x08ec
>+#define mmPCTL0_SLICE4_RENG_RAM_DATA_BASE_IDX                                                          1
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0                                                      0x08ed
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                             1
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1                                                      0x08ee
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                             1
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2                                                      0x08ef
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                             1
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3                                                      0x08f0
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                             1
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4                                                      0x08f1
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                             1
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0                                                   0x08f2
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                          1
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1                                                   0x08f3
>+#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                          1
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0                                                     0x08f4
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                            1
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1                                                     0x08f5
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                            1
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2                                                     0x08f6
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                            1
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3                                                     0x08f7
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                            1
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4                                                     0x08f8
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                            1
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0                                                  0x08f9
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                         1
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1                                                  0x08fa
>+#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                         1
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0                                                     0x08fb
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                            1
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1                                                     0x08fc
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                            1
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2                                                     0x08fd
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                            1
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3                                                     0x08fe
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                            1
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4                                                     0x08ff
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                            1
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0                                                  0x0900
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                         1
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1                                                  0x0901
>+#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                         1
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0                                                     0x0902
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                            1
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1                                                     0x0903
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                            1
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2                                                     0x0904
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                            1
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3                                                     0x0905
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                            1
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4                                                     0x0906
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                            1
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0                                                  0x0907
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                         1
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1                                                  0x0908
>+#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                         1
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0                                                     0x0909
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                            1
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1                                                     0x090a
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                            1
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2                                                     0x090b
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                            1
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3                                                     0x090c
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                            1
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4                                                     0x090d
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                            1
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0                                                  0x090e
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                         1
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1                                                  0x090f
>+#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                         1
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0                                                     0x0910
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                            1
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1                                                     0x0911
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                            1
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2                                                     0x0912
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                            1
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3                                                     0x0913
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                            1
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4                                                     0x0914
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                            1
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0                                                  0x0915
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                         1
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1                                                  0x0916
>+#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                         1
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1dec
>+// base address: 0x6a500
>+#define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS                                                               0x0948
>+#define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS_BASE_IDX                                                      1
>+#define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS                                                               0x0949
>+#define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS_BASE_IDX                                                      1
>+#define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS                                                               0x094a
>+#define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS_BASE_IDX                                                      1
>+#define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS                                                               0x094b
>+#define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS_BASE_IDX                                                      1
>+#define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS                                                               0x094c
>+#define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS_BASE_IDX                                                      1
>+#define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS                                                               0x094d
>+#define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS_BASE_IDX                                                      1
>+#define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS                                                               0x094e
>+#define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS_BASE_IDX                                                      1
>+#define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS                                                               0x094f
>+#define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS_BASE_IDX                                                      1
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1pldec
>+// base address: 0x6a580
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG                                                         0x0960
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX                                                1
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG                                                         0x0961
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX                                                1
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG                                                         0x0962
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX                                                1
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG                                                         0x0963
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX                                                1
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL                                                    0x0964
>+#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                           1
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1prdec
>+// base address: 0x6a5c0
>+#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO                                                           0x0970
>+#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX                                                  1
>+#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI                                                           0x0971
>+#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX                                                  1
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2dec
>+// base address: 0x6a600
>+#define mmATCL2_0_ATC_L2_CNTL                                                                          0x0980
>+#define mmATCL2_0_ATC_L2_CNTL_BASE_IDX                                                                 1
>+#define mmATCL2_0_ATC_L2_CNTL2                                                                         0x0981
>+#define mmATCL2_0_ATC_L2_CNTL2_BASE_IDX                                                                1
>+#define mmATCL2_0_ATC_L2_CACHE_DATA0                                                                   0x0984
>+#define mmATCL2_0_ATC_L2_CACHE_DATA0_BASE_IDX                                                          1
>+#define mmATCL2_0_ATC_L2_CACHE_DATA1                                                                   0x0985
>+#define mmATCL2_0_ATC_L2_CACHE_DATA1_BASE_IDX                                                          1
>+#define mmATCL2_0_ATC_L2_CACHE_DATA2                                                                   0x0986
>+#define mmATCL2_0_ATC_L2_CACHE_DATA2_BASE_IDX                                                          1
>+#define mmATCL2_0_ATC_L2_CNTL3                                                                         0x0987
>+#define mmATCL2_0_ATC_L2_CNTL3_BASE_IDX                                                                1
>+#define mmATCL2_0_ATC_L2_STATUS                                                                        0x0988
>+#define mmATCL2_0_ATC_L2_STATUS_BASE_IDX                                                               1
>+#define mmATCL2_0_ATC_L2_STATUS2                                                                       0x0989
>+#define mmATCL2_0_ATC_L2_STATUS2_BASE_IDX                                                              1
>+#define mmATCL2_0_ATC_L2_STATUS3                                                                       0x098a
>+#define mmATCL2_0_ATC_L2_STATUS3_BASE_IDX                                                              1
>+#define mmATCL2_0_ATC_L2_MISC_CG                                                                       0x098b
>+#define mmATCL2_0_ATC_L2_MISC_CG_BASE_IDX                                                              1
>+#define mmATCL2_0_ATC_L2_MEM_POWER_LS                                                                  0x098c
>+#define mmATCL2_0_ATC_L2_MEM_POWER_LS_BASE_IDX                                                         1
>+#define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL                                                                 0x098d
>+#define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX                                                            0x098e
>+#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX                                                   1
>+#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX                                                            0x098f
>+#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX                                                   1
>+#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL                                                             0x0990
>+#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX                                                    1
>+#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL                                                             0x0991
>+#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX                                                    1
>+#define mmATCL2_0_ATC_L2_CNTL4                                                                         0x0992
>+#define mmATCL2_0_ATC_L2_CNTL4_BASE_IDX                                                                1
>+#define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES                                                           0x0993
>+#define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                  1
>+
>+
>+// addressBlock: mmhub_utcl2_vml2pfdec
>+// base address: 0x6a700
>+#define mmVML2PF0_VM_L2_CNTL                                                                           0x09c0
>+#define mmVML2PF0_VM_L2_CNTL_BASE_IDX                                                                  1
>+#define mmVML2PF0_VM_L2_CNTL2                                                                          0x09c1
>+#define mmVML2PF0_VM_L2_CNTL2_BASE_IDX                                                                 1
>+#define mmVML2PF0_VM_L2_CNTL3                                                                          0x09c2
>+#define mmVML2PF0_VM_L2_CNTL3_BASE_IDX                                                                 1
>+#define mmVML2PF0_VM_L2_STATUS                                                                         0x09c3
>+#define mmVML2PF0_VM_L2_STATUS_BASE_IDX                                                                1
>+#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL                                                             0x09c4
>+#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX                                                    1
>+#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32                                                        0x09c5
>+#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX                                               1
>+#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32                                                        0x09c6
>+#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX                                               1
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL                                                          0x09c7
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL_BASE_IDX                                                 1
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2                                                         0x09c8
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX                                                1
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3                                                      0x09c9
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX                                             1
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4                                                      0x09ca
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX                                             1
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS                                                        0x09cb
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS_BASE_IDX                                               1
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32                                                     0x09cc
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX                                            1
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32                                                     0x09cd
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX                                            1
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32                                             0x09ce
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX                                    1
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32                                             0x09cf
>+#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX                                    1
>+#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32                                       0x09d1
>+#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX                              1
>+#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32                                       0x09d2
>+#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX                              1
>+#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32                                      0x09d3
>+#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX                             1
>+#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32                                      0x09d4
>+#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX                             1
>+#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32                                          0x09d5
>+#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX                                 1
>+#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32                                          0x09d6
>+#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX                                 1
>+#define mmVML2PF0_VM_L2_CNTL4                                                                          0x09d7
>+#define mmVML2PF0_VM_L2_CNTL4_BASE_IDX                                                                 1
>+#define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES                                                            0x09d8
>+#define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                   1
>+#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID                                                       0x09d9
>+#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX                                              1
>+#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2                                                      0x09da
>+#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX                                             1
>+#define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL                                                              0x09db
>+#define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL_BASE_IDX                                                     1
>+#define mmVML2PF0_VM_L2_CGTT_CLK_CTRL                                                                  0x09de
>+#define mmVML2PF0_VM_L2_CGTT_CLK_CTRL_BASE_IDX                                                         1
>+
>+
>+// addressBlock: mmhub_utcl2_vml2vcdec
>+// base address: 0x6a800
>+#define mmVML2VC0_VM_CONTEXT0_CNTL                                                                     0x0a00
>+#define mmVML2VC0_VM_CONTEXT0_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC0_VM_CONTEXT1_CNTL                                                                     0x0a01
>+#define mmVML2VC0_VM_CONTEXT1_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC0_VM_CONTEXT2_CNTL                                                                     0x0a02
>+#define mmVML2VC0_VM_CONTEXT2_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC0_VM_CONTEXT3_CNTL                                                                     0x0a03
>+#define mmVML2VC0_VM_CONTEXT3_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC0_VM_CONTEXT4_CNTL                                                                     0x0a04
>+#define mmVML2VC0_VM_CONTEXT4_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC0_VM_CONTEXT5_CNTL                                                                     0x0a05
>+#define mmVML2VC0_VM_CONTEXT5_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC0_VM_CONTEXT6_CNTL                                                                     0x0a06
>+#define mmVML2VC0_VM_CONTEXT6_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC0_VM_CONTEXT7_CNTL                                                                     0x0a07
>+#define mmVML2VC0_VM_CONTEXT7_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC0_VM_CONTEXT8_CNTL                                                                     0x0a08
>+#define mmVML2VC0_VM_CONTEXT8_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC0_VM_CONTEXT9_CNTL                                                                     0x0a09
>+#define mmVML2VC0_VM_CONTEXT9_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC0_VM_CONTEXT10_CNTL                                                                    0x0a0a
>+#define mmVML2VC0_VM_CONTEXT10_CNTL_BASE_IDX                                                           1
>+#define mmVML2VC0_VM_CONTEXT11_CNTL                                                                    0x0a0b
>+#define mmVML2VC0_VM_CONTEXT11_CNTL_BASE_IDX                                                           1
>+#define mmVML2VC0_VM_CONTEXT12_CNTL                                                                    0x0a0c
>+#define mmVML2VC0_VM_CONTEXT12_CNTL_BASE_IDX                                                           1
>+#define mmVML2VC0_VM_CONTEXT13_CNTL                                                                    0x0a0d
>+#define mmVML2VC0_VM_CONTEXT13_CNTL_BASE_IDX                                                           1
>+#define mmVML2VC0_VM_CONTEXT14_CNTL                                                                    0x0a0e
>+#define mmVML2VC0_VM_CONTEXT14_CNTL_BASE_IDX                                                           1
>+#define mmVML2VC0_VM_CONTEXT15_CNTL                                                                    0x0a0f
>+#define mmVML2VC0_VM_CONTEXT15_CNTL_BASE_IDX                                                           1
>+#define mmVML2VC0_VM_CONTEXTS_DISABLE                                                                  0x0a10
>+#define mmVML2VC0_VM_CONTEXTS_DISABLE_BASE_IDX                                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_SEM                                                               0x0a11
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_SEM_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_SEM                                                               0x0a12
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_SEM_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_SEM                                                               0x0a13
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_SEM_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_SEM                                                               0x0a14
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_SEM_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_SEM                                                               0x0a15
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_SEM_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_SEM                                                               0x0a16
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_SEM_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_SEM                                                               0x0a17
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_SEM_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_SEM                                                               0x0a18
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_SEM_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_SEM                                                               0x0a19
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_SEM_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_SEM                                                               0x0a1a
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_SEM_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_SEM                                                              0x0a1b
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_SEM_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_SEM                                                              0x0a1c
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_SEM_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_SEM                                                              0x0a1d
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_SEM_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_SEM                                                              0x0a1e
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_SEM_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_SEM                                                              0x0a1f
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_SEM_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_SEM                                                              0x0a20
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_SEM_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_SEM                                                              0x0a21
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_SEM_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_SEM                                                              0x0a22
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_SEM_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_REQ                                                               0x0a23
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_REQ_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_REQ                                                               0x0a24
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_REQ_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_REQ                                                               0x0a25
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_REQ_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_REQ                                                               0x0a26
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_REQ_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_REQ                                                               0x0a27
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_REQ_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_REQ                                                               0x0a28
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_REQ_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_REQ                                                               0x0a29
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_REQ_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_REQ                                                               0x0a2a
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_REQ_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_REQ                                                               0x0a2b
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_REQ_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_REQ                                                               0x0a2c
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_REQ_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_REQ                                                              0x0a2d
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_REQ_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_REQ                                                              0x0a2e
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_REQ_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_REQ                                                              0x0a2f
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_REQ_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_REQ                                                              0x0a30
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_REQ_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_REQ                                                              0x0a31
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_REQ_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_REQ                                                              0x0a32
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_REQ_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_REQ                                                              0x0a33
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_REQ_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_REQ                                                              0x0a34
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_REQ_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_ACK                                                               0x0a35
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_ACK_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_ACK                                                               0x0a36
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_ACK_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_ACK                                                               0x0a37
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_ACK_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_ACK                                                               0x0a38
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_ACK_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_ACK                                                               0x0a39
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_ACK_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_ACK                                                               0x0a3a
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_ACK_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_ACK                                                               0x0a3b
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_ACK_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_ACK                                                               0x0a3c
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_ACK_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_ACK                                                               0x0a3d
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_ACK_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_ACK                                                               0x0a3e
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_ACK_BASE_IDX                                                      1
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_ACK                                                              0x0a3f
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_ACK_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_ACK                                                              0x0a40
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_ACK_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_ACK                                                              0x0a41
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_ACK_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_ACK                                                              0x0a42
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_ACK_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_ACK                                                              0x0a43
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_ACK_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_ACK                                                              0x0a44
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_ACK_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_ACK                                                              0x0a45
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_ACK_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_ACK                                                              0x0a46
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_ACK_BASE_IDX                                                     1
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32                                                   0x0a47
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32                                                   0x0a48
>+#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32                                                   0x0a49
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32                                                   0x0a4a
>+#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32                                                   0x0a4b
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32                                                   0x0a4c
>+#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32                                                   0x0a4d
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32                                                   0x0a4e
>+#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32                                                   0x0a4f
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32                                                   0x0a50
>+#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32                                                   0x0a51
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32                                                   0x0a52
>+#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32                                                   0x0a53
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32                                                   0x0a54
>+#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32                                                   0x0a55
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32                                                   0x0a56
>+#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32                                                   0x0a57
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32                                                   0x0a58
>+#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32                                                   0x0a59
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32                                                   0x0a5a
>+#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32                                                  0x0a5b
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32                                                  0x0a5c
>+#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32                                                  0x0a5d
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32                                                  0x0a5e
>+#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32                                                  0x0a5f
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32                                                  0x0a60
>+#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32                                                  0x0a61
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32                                                  0x0a62
>+#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32                                                  0x0a63
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32                                                  0x0a64
>+#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32                                                  0x0a65
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32                                                  0x0a66
>+#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32                                                  0x0a67
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32                                                  0x0a68
>+#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32                                                  0x0a69
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32                                                  0x0a6a
>+#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                0x0a6b
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                0x0a6c
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                0x0a6d
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                0x0a6e
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                0x0a6f
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                0x0a70
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                0x0a71
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                0x0a72
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                0x0a73
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                0x0a74
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                0x0a75
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                0x0a76
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                0x0a77
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                0x0a78
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                0x0a79
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                0x0a7a
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                0x0a7b
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                0x0a7c
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                0x0a7d
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                0x0a7e
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                               0x0a7f
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                               0x0a80
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                               0x0a81
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                               0x0a82
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                               0x0a83
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                               0x0a84
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                               0x0a85
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                               0x0a86
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                               0x0a87
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                               0x0a88
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                               0x0a89
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                               0x0a8a
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                               0x0a8b
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                               0x0a8c
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                               0x0a8d
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                               0x0a8e
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                               0x0a8f
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                               0x0a90
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                               0x0a91
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                               0x0a92
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                               0x0a93
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                               0x0a94
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                               0x0a95
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                               0x0a96
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                               0x0a97
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                               0x0a98
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                               0x0a99
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                               0x0a9a
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                               0x0a9b
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                               0x0a9c
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                               0x0a9d
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                               0x0a9e
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                              0x0a9f
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                              0x0aa0
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                              0x0aa1
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                              0x0aa2
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                              0x0aa3
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                              0x0aa4
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                              0x0aa5
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                              0x0aa6
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                              0x0aa7
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                              0x0aa8
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                              0x0aa9
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                              0x0aaa
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                 0x0aab
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                 0x0aac
>+#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                 0x0aad
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                 0x0aae
>+#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                 0x0aaf
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                 0x0ab0
>+#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                 0x0ab1
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                 0x0ab2
>+#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                 0x0ab3
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                 0x0ab4
>+#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                 0x0ab5
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                 0x0ab6
>+#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                 0x0ab7
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                 0x0ab8
>+#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                 0x0ab9
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                 0x0aba
>+#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                 0x0abb
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                 0x0abc
>+#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                 0x0abd
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                 0x0abe
>+#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                0x0abf
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                0x0ac0
>+#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                0x0ac1
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                0x0ac2
>+#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                0x0ac3
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                0x0ac4
>+#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                0x0ac5
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                0x0ac6
>+#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                0x0ac7
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                0x0ac8
>+#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                0x0ac9
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                0x0aca
>+#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedpfdec
>+// base address: 0x6ab90
>+#define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE                                                                0x0ae4
>+#define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE_BASE_IDX                                                       1
>+#define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT                                                               0x0ae5
>+#define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT_BASE_IDX                                                      1
>+#define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL                                                                0x0ae6
>+#define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL_BASE_IDX                                                       1
>+#define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB                                                                 0x0ae7
>+#define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB_BASE_IDX                                                        1
>+#define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1                                                       0x0ae8
>+#define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX                                              1
>+#define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2                                                      0x0ae9
>+#define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX                                             1
>+#define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2                                                      0x0aea
>+#define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX                                             1
>+#define mmVMSHAREDPF0_MC_VM_FB_OFFSET                                                                  0x0aeb
>+#define mmVMSHAREDPF0_MC_VM_FB_OFFSET_BASE_IDX                                                         1
>+#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB                                           0x0aec
>+#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX                                  1
>+#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB                                           0x0aed
>+#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX                                  1
>+#define mmVMSHAREDPF0_MC_VM_STEERING                                                                   0x0aee
>+#define mmVMSHAREDPF0_MC_VM_STEERING_BASE_IDX                                                          1
>+#define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ                                                         0x0aef
>+#define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ_BASE_IDX                                                1
>+#define mmVMSHAREDPF0_MC_MEM_POWER_LS                                                                  0x0af0
>+#define mmVMSHAREDPF0_MC_MEM_POWER_LS_BASE_IDX                                                         1
>+#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START                                               0x0af1
>+#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX                                      1
>+#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END                                                 0x0af2
>+#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX                                        1
>+#define mmVMSHAREDPF0_MC_VM_APT_CNTL                                                                   0x0af3
>+#define mmVMSHAREDPF0_MC_VM_APT_CNTL_BASE_IDX                                                          1
>+#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START                                                    0x0af4
>+#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                           1
>+#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END                                                      0x0af5
>+#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                             1
>+#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                0x0af6
>+#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                       1
>+#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL                                                              0x0af7
>+#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL_BASE_IDX                                                     1
>+#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE                                                              0x0af8
>+#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE_BASE_IDX                                                     1
>+#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL                                                        0x0af9
>+#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX                                               1
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedvcdec
>+// base address: 0x6ac00
>+#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE                                                           0x0b00
>+#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE_BASE_IDX                                                  1
>+#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP                                                            0x0b01
>+#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP_BASE_IDX                                                   1
>+#define mmVMSHAREDVC0_MC_VM_AGP_TOP                                                                    0x0b02
>+#define mmVMSHAREDVC0_MC_VM_AGP_TOP_BASE_IDX                                                           1
>+#define mmVMSHAREDVC0_MC_VM_AGP_BOT                                                                    0x0b03
>+#define mmVMSHAREDVC0_MC_VM_AGP_BOT_BASE_IDX                                                           1
>+#define mmVMSHAREDVC0_MC_VM_AGP_BASE                                                                   0x0b04
>+#define mmVMSHAREDVC0_MC_VM_AGP_BASE_BASE_IDX                                                          1
>+#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR                                                   0x0b05
>+#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                          1
>+#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR                                                  0x0b06
>+#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                         1
>+#define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL                                                             0x0b07
>+#define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL_BASE_IDX                                                    1
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedhvdec
>+// base address: 0x6ac80
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0                                                         0x0b20
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX                                                1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1                                                         0x0b21
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX                                                1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2                                                         0x0b22
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX                                                1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3                                                         0x0b23
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX                                                1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4                                                         0x0b24
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX                                                1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5                                                         0x0b25
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX                                                1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6                                                         0x0b26
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX                                                1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7                                                         0x0b27
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX                                                1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8                                                         0x0b28
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX                                                1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9                                                         0x0b29
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX                                                1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10                                                        0x0b2a
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX                                               1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11                                                        0x0b2b
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX                                               1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12                                                        0x0b2c
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX                                               1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13                                                        0x0b2d
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX                                               1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14                                                        0x0b2e
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX                                               1
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15                                                        0x0b2f
>+#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX                                               1
>+#define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1                                                            0x0b30
>+#define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0                                                             0x0b31
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0_BASE_IDX                                                    1
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1                                                             0x0b32
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1_BASE_IDX                                                    1
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2                                                             0x0b33
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2_BASE_IDX                                                    1
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3                                                             0x0b34
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3_BASE_IDX                                                    1
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0                                                             0x0b35
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0_BASE_IDX                                                    1
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1                                                             0x0b36
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1_BASE_IDX                                                    1
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2                                                             0x0b37
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2_BASE_IDX                                                    1
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3                                                             0x0b38
>+#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3_BASE_IDX                                                    1
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0                                                            0x0b39
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1                                                            0x0b3a
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2                                                            0x0b3b
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3                                                            0x0b3c
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0                                                            0x0b3d
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1                                                            0x0b3e
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2                                                            0x0b3f
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3                                                            0x0b40
>+#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0                                                              0x0b41
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0_BASE_IDX                                                     1
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1                                                              0x0b42
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1_BASE_IDX                                                     1
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2                                                              0x0b43
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2_BASE_IDX                                                     1
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3                                                              0x0b44
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3_BASE_IDX                                                     1
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0                                                              0x0b45
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0_BASE_IDX                                                     1
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1                                                              0x0b46
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1_BASE_IDX                                                     1
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2                                                              0x0b47
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2_BASE_IDX                                                     1
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3                                                              0x0b48
>+#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3_BASE_IDX                                                     1
>+#define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER                                                        0x0b49
>+#define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER_BASE_IDX                                               1
>+#define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER                               0x0b4a
>+#define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX                      1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL                                                                 0x0b4b
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_BASE_IDX                                                        1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0                                                            0x0b4c
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1                                                            0x0b4d
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2                                                            0x0b4e
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3                                                            0x0b4f
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4                                                            0x0b50
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5                                                            0x0b51
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6                                                            0x0b52
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7                                                            0x0b53
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8                                                            0x0b54
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9                                                            0x0b55
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9_BASE_IDX                                                   1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10                                                           0x0b56
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10_BASE_IDX                                                  1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11                                                           0x0b57
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11_BASE_IDX                                                  1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12                                                           0x0b58
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12_BASE_IDX                                                  1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13                                                           0x0b59
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13_BASE_IDX                                                  1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14                                                           0x0b5a
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14_BASE_IDX                                                  1
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15                                                           0x0b5b
>+#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15_BASE_IDX                                                  1
>+#define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL                                                              0x0b5c
>+#define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL_BASE_IDX                                                     1
>+#define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID                                                          0x0b5d
>+#define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID_BASE_IDX                                                 1
>+#define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE                                                         0x0b5e
>+#define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX                                                1
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2pfcntrdec
>+// base address: 0x6adc0
>+#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO                                                           0x0b70
>+#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO_BASE_IDX                                                  1
>+#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI                                                           0x0b71
>+#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI_BASE_IDX                                                  1
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2pfcntldec
>+// base address: 0x6add0
>+#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG                                                         0x0b74
>+#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX                                                1
>+#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG                                                         0x0b75
>+#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX                                                1
>+#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL                                                    0x0b76
>+#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                           1
>+
>+
>+// addressBlock: mmhub_utcl2_vml2pldec
>+// base address: 0x6ae00
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG                                                            0x0b80
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX                                                   1
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG                                                            0x0b81
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX                                                   1
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG                                                            0x0b82
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX                                                   1
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG                                                            0x0b83
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX                                                   1
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG                                                            0x0b84
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX                                                   1
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG                                                            0x0b85
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX                                                   1
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG                                                            0x0b86
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX                                                   1
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG                                                            0x0b87
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX                                                   1
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL                                                       0x0b88
>+#define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                              1
>+
>+
>+// addressBlock: mmhub_utcl2_vml2prdec
>+// base address: 0x6ae40
>+#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO                                                              0x0b90
>+#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO_BASE_IDX                                                     1
>+#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI                                                              0x0b91
>+#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI_BASE_IDX                                                     1
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec5
>+// base address: 0x74000
>+#define mmDAGB5_RDCLI0                                                                                 0x3000
>+#define mmDAGB5_RDCLI0_BASE_IDX                                                                        1
>+#define mmDAGB5_RDCLI1                                                                                 0x3001
>+#define mmDAGB5_RDCLI1_BASE_IDX                                                                        1
>+#define mmDAGB5_RDCLI2                                                                                 0x3002
>+#define mmDAGB5_RDCLI2_BASE_IDX                                                                        1
>+#define mmDAGB5_RDCLI3                                                                                 0x3003
>+#define mmDAGB5_RDCLI3_BASE_IDX                                                                        1
>+#define mmDAGB5_RDCLI4                                                                                 0x3004
>+#define mmDAGB5_RDCLI4_BASE_IDX                                                                        1
>+#define mmDAGB5_RDCLI5                                                                                 0x3005
>+#define mmDAGB5_RDCLI5_BASE_IDX                                                                        1
>+#define mmDAGB5_RDCLI6                                                                                 0x3006
>+#define mmDAGB5_RDCLI6_BASE_IDX                                                                        1
>+#define mmDAGB5_RDCLI7                                                                                 0x3007
>+#define mmDAGB5_RDCLI7_BASE_IDX                                                                        1
>+#define mmDAGB5_RDCLI8                                                                                 0x3008
>+#define mmDAGB5_RDCLI8_BASE_IDX                                                                        1
>+#define mmDAGB5_RDCLI9                                                                                 0x3009
>+#define mmDAGB5_RDCLI9_BASE_IDX                                                                        1
>+#define mmDAGB5_RDCLI10                                                                                0x300a
>+#define mmDAGB5_RDCLI10_BASE_IDX                                                                       1
>+#define mmDAGB5_RDCLI11                                                                                0x300b
>+#define mmDAGB5_RDCLI11_BASE_IDX                                                                       1
>+#define mmDAGB5_RDCLI12                                                                                0x300c
>+#define mmDAGB5_RDCLI12_BASE_IDX                                                                       1
>+#define mmDAGB5_RDCLI13                                                                                0x300d
>+#define mmDAGB5_RDCLI13_BASE_IDX                                                                       1
>+#define mmDAGB5_RDCLI14                                                                                0x300e
>+#define mmDAGB5_RDCLI14_BASE_IDX                                                                       1
>+#define mmDAGB5_RDCLI15                                                                                0x300f
>+#define mmDAGB5_RDCLI15_BASE_IDX                                                                       1
>+#define mmDAGB5_RD_CNTL                                                                                0x3010
>+#define mmDAGB5_RD_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB5_RD_GMI_CNTL                                                                            0x3011
>+#define mmDAGB5_RD_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_RD_ADDR_DAGB                                                                           0x3012
>+#define mmDAGB5_RD_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST                                                               0x3013
>+#define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER                                                              0x3014
>+#define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB5_RD_CGTT_CLK_CTRL                                                                       0x3015
>+#define mmDAGB5_RD_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL                                                                 0x3016
>+#define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL                                                                 0x3017
>+#define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0                                                                0x3018
>+#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0                                                               0x3019
>+#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1                                                                0x301a
>+#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1                                                               0x301b
>+#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB5_RD_VC0_CNTL                                                                            0x301c
>+#define mmDAGB5_RD_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_RD_VC1_CNTL                                                                            0x301d
>+#define mmDAGB5_RD_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_RD_VC2_CNTL                                                                            0x301e
>+#define mmDAGB5_RD_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_RD_VC3_CNTL                                                                            0x301f
>+#define mmDAGB5_RD_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_RD_VC4_CNTL                                                                            0x3020
>+#define mmDAGB5_RD_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_RD_VC5_CNTL                                                                            0x3021
>+#define mmDAGB5_RD_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_RD_VC6_CNTL                                                                            0x3022
>+#define mmDAGB5_RD_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_RD_VC7_CNTL                                                                            0x3023
>+#define mmDAGB5_RD_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_RD_CNTL_MISC                                                                           0x3024
>+#define mmDAGB5_RD_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB5_RD_TLB_CREDIT                                                                          0x3025
>+#define mmDAGB5_RD_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB5_RDCLI_ASK_PENDING                                                                      0x3026
>+#define mmDAGB5_RDCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB5_RDCLI_GO_PENDING                                                                       0x3027
>+#define mmDAGB5_RDCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB5_RDCLI_GBLSEND_PENDING                                                                  0x3028
>+#define mmDAGB5_RDCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB5_RDCLI_TLB_PENDING                                                                      0x3029
>+#define mmDAGB5_RDCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB5_RDCLI_OARB_PENDING                                                                     0x302a
>+#define mmDAGB5_RDCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB5_RDCLI_OSD_PENDING                                                                      0x302b
>+#define mmDAGB5_RDCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB5_WRCLI0                                                                                 0x302c
>+#define mmDAGB5_WRCLI0_BASE_IDX                                                                        1
>+#define mmDAGB5_WRCLI1                                                                                 0x302d
>+#define mmDAGB5_WRCLI1_BASE_IDX                                                                        1
>+#define mmDAGB5_WRCLI2                                                                                 0x302e
>+#define mmDAGB5_WRCLI2_BASE_IDX                                                                        1
>+#define mmDAGB5_WRCLI3                                                                                 0x302f
>+#define mmDAGB5_WRCLI3_BASE_IDX                                                                        1
>+#define mmDAGB5_WRCLI4                                                                                 0x3030
>+#define mmDAGB5_WRCLI4_BASE_IDX                                                                        1
>+#define mmDAGB5_WRCLI5                                                                                 0x3031
>+#define mmDAGB5_WRCLI5_BASE_IDX                                                                        1
>+#define mmDAGB5_WRCLI6                                                                                 0x3032
>+#define mmDAGB5_WRCLI6_BASE_IDX                                                                        1
>+#define mmDAGB5_WRCLI7                                                                                 0x3033
>+#define mmDAGB5_WRCLI7_BASE_IDX                                                                        1
>+#define mmDAGB5_WRCLI8                                                                                 0x3034
>+#define mmDAGB5_WRCLI8_BASE_IDX                                                                        1
>+#define mmDAGB5_WRCLI9                                                                                 0x3035
>+#define mmDAGB5_WRCLI9_BASE_IDX                                                                        1
>+#define mmDAGB5_WRCLI10                                                                                0x3036
>+#define mmDAGB5_WRCLI10_BASE_IDX                                                                       1
>+#define mmDAGB5_WRCLI11                                                                                0x3037
>+#define mmDAGB5_WRCLI11_BASE_IDX                                                                       1
>+#define mmDAGB5_WRCLI12                                                                                0x3038
>+#define mmDAGB5_WRCLI12_BASE_IDX                                                                       1
>+#define mmDAGB5_WRCLI13                                                                                0x3039
>+#define mmDAGB5_WRCLI13_BASE_IDX                                                                       1
>+#define mmDAGB5_WRCLI14                                                                                0x303a
>+#define mmDAGB5_WRCLI14_BASE_IDX                                                                       1
>+#define mmDAGB5_WRCLI15                                                                                0x303b
>+#define mmDAGB5_WRCLI15_BASE_IDX                                                                       1
>+#define mmDAGB5_WR_CNTL                                                                                0x303c
>+#define mmDAGB5_WR_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB5_WR_GMI_CNTL                                                                            0x303d
>+#define mmDAGB5_WR_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_WR_ADDR_DAGB                                                                           0x303e
>+#define mmDAGB5_WR_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST                                                               0x303f
>+#define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER                                                              0x3040
>+#define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB5_WR_CGTT_CLK_CTRL                                                                       0x3041
>+#define mmDAGB5_WR_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL                                                                 0x3042
>+#define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL                                                                 0x3043
>+#define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0                                                                0x3044
>+#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0                                                               0x3045
>+#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1                                                                0x3046
>+#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1                                                               0x3047
>+#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB5_WR_DATA_DAGB                                                                           0x3048
>+#define mmDAGB5_WR_DATA_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB5_WR_DATA_DAGB_MAX_BURST0                                                                0x3049
>+#define mmDAGB5_WR_DATA_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0                                                               0x304a
>+#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB5_WR_DATA_DAGB_MAX_BURST1                                                                0x304b
>+#define mmDAGB5_WR_DATA_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1                                                               0x304c
>+#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB5_WR_VC0_CNTL                                                                            0x304d
>+#define mmDAGB5_WR_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_WR_VC1_CNTL                                                                            0x304e
>+#define mmDAGB5_WR_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_WR_VC2_CNTL                                                                            0x304f
>+#define mmDAGB5_WR_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_WR_VC3_CNTL                                                                            0x3050
>+#define mmDAGB5_WR_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_WR_VC4_CNTL                                                                            0x3051
>+#define mmDAGB5_WR_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_WR_VC5_CNTL                                                                            0x3052
>+#define mmDAGB5_WR_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_WR_VC6_CNTL                                                                            0x3053
>+#define mmDAGB5_WR_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_WR_VC7_CNTL                                                                            0x3054
>+#define mmDAGB5_WR_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB5_WR_CNTL_MISC                                                                           0x3055
>+#define mmDAGB5_WR_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB5_WR_TLB_CREDIT                                                                          0x3056
>+#define mmDAGB5_WR_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB5_WR_DATA_CREDIT                                                                         0x3057
>+#define mmDAGB5_WR_DATA_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB5_WR_MISC_CREDIT                                                                         0x3058
>+#define mmDAGB5_WR_MISC_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB5_WRCLI_ASK_PENDING                                                                      0x305d
>+#define mmDAGB5_WRCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB5_WRCLI_GO_PENDING                                                                       0x305e
>+#define mmDAGB5_WRCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB5_WRCLI_GBLSEND_PENDING                                                                  0x305f
>+#define mmDAGB5_WRCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB5_WRCLI_TLB_PENDING                                                                      0x3060
>+#define mmDAGB5_WRCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB5_WRCLI_OARB_PENDING                                                                     0x3061
>+#define mmDAGB5_WRCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB5_WRCLI_OSD_PENDING                                                                      0x3062
>+#define mmDAGB5_WRCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB5_WRCLI_DBUS_ASK_PENDING                                                                 0x3063
>+#define mmDAGB5_WRCLI_DBUS_ASK_PENDING_BASE_IDX                                                        1
>+#define mmDAGB5_WRCLI_DBUS_GO_PENDING                                                                  0x3064
>+#define mmDAGB5_WRCLI_DBUS_GO_PENDING_BASE_IDX                                                         1
>+#define mmDAGB5_DAGB_DLY                                                                               0x3065
>+#define mmDAGB5_DAGB_DLY_BASE_IDX                                                                      1
>+#define mmDAGB5_CNTL_MISC                                                                              0x3066
>+#define mmDAGB5_CNTL_MISC_BASE_IDX                                                                     1
>+#define mmDAGB5_CNTL_MISC2                                                                             0x3067
>+#define mmDAGB5_CNTL_MISC2_BASE_IDX                                                                    1
>+#define mmDAGB5_FIFO_EMPTY                                                                             0x3068
>+#define mmDAGB5_FIFO_EMPTY_BASE_IDX                                                                    1
>+#define mmDAGB5_FIFO_FULL                                                                              0x3069
>+#define mmDAGB5_FIFO_FULL_BASE_IDX                                                                     1
>+#define mmDAGB5_WR_CREDITS_FULL                                                                        0x306a
>+#define mmDAGB5_WR_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB5_RD_CREDITS_FULL                                                                        0x306b
>+#define mmDAGB5_RD_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB5_PERFCOUNTER_LO                                                                         0x306c
>+#define mmDAGB5_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmDAGB5_PERFCOUNTER_HI                                                                         0x306d
>+#define mmDAGB5_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmDAGB5_PERFCOUNTER0_CFG                                                                       0x306e
>+#define mmDAGB5_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmDAGB5_PERFCOUNTER1_CFG                                                                       0x306f
>+#define mmDAGB5_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmDAGB5_PERFCOUNTER2_CFG                                                                       0x3070
>+#define mmDAGB5_PERFCOUNTER2_CFG_BASE_IDX                                                              1
>+#define mmDAGB5_PERFCOUNTER_RSLT_CNTL                                                                  0x3071
>+#define mmDAGB5_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmDAGB5_RESERVE0                                                                               0x3072
>+#define mmDAGB5_RESERVE0_BASE_IDX                                                                      1
>+#define mmDAGB5_RESERVE1                                                                               0x3073
>+#define mmDAGB5_RESERVE1_BASE_IDX                                                                      1
>+#define mmDAGB5_RESERVE2                                                                               0x3074
>+#define mmDAGB5_RESERVE2_BASE_IDX                                                                      1
>+#define mmDAGB5_RESERVE3                                                                               0x3075
>+#define mmDAGB5_RESERVE3_BASE_IDX                                                                      1
>+#define mmDAGB5_RESERVE4                                                                               0x3076
>+#define mmDAGB5_RESERVE4_BASE_IDX                                                                      1
>+#define mmDAGB5_RESERVE5                                                                               0x3077
>+#define mmDAGB5_RESERVE5_BASE_IDX                                                                      1
>+#define mmDAGB5_RESERVE6                                                                               0x3078
>+#define mmDAGB5_RESERVE6_BASE_IDX                                                                      1
>+#define mmDAGB5_RESERVE7                                                                               0x3079
>+#define mmDAGB5_RESERVE7_BASE_IDX                                                                      1
>+#define mmDAGB5_RESERVE8                                                                               0x307a
>+#define mmDAGB5_RESERVE8_BASE_IDX                                                                      1
>+#define mmDAGB5_RESERVE9                                                                               0x307b
>+#define mmDAGB5_RESERVE9_BASE_IDX                                                                      1
>+#define mmDAGB5_RESERVE10                                                                              0x307c
>+#define mmDAGB5_RESERVE10_BASE_IDX                                                                     1
>+#define mmDAGB5_RESERVE11                                                                              0x307d
>+#define mmDAGB5_RESERVE11_BASE_IDX                                                                     1
>+#define mmDAGB5_RESERVE12                                                                              0x307e
>+#define mmDAGB5_RESERVE12_BASE_IDX                                                                     1
>+#define mmDAGB5_RESERVE13                                                                              0x307f
>+#define mmDAGB5_RESERVE13_BASE_IDX                                                                     1
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec6
>+// base address: 0x74200
>+#define mmDAGB6_RDCLI0                                                                                 0x3080
>+#define mmDAGB6_RDCLI0_BASE_IDX                                                                        1
>+#define mmDAGB6_RDCLI1                                                                                 0x3081
>+#define mmDAGB6_RDCLI1_BASE_IDX                                                                        1
>+#define mmDAGB6_RDCLI2                                                                                 0x3082
>+#define mmDAGB6_RDCLI2_BASE_IDX                                                                        1
>+#define mmDAGB6_RDCLI3                                                                                 0x3083
>+#define mmDAGB6_RDCLI3_BASE_IDX                                                                        1
>+#define mmDAGB6_RDCLI4                                                                                 0x3084
>+#define mmDAGB6_RDCLI4_BASE_IDX                                                                        1
>+#define mmDAGB6_RDCLI5                                                                                 0x3085
>+#define mmDAGB6_RDCLI5_BASE_IDX                                                                        1
>+#define mmDAGB6_RDCLI6                                                                                 0x3086
>+#define mmDAGB6_RDCLI6_BASE_IDX                                                                        1
>+#define mmDAGB6_RDCLI7                                                                                 0x3087
>+#define mmDAGB6_RDCLI7_BASE_IDX                                                                        1
>+#define mmDAGB6_RDCLI8                                                                                 0x3088
>+#define mmDAGB6_RDCLI8_BASE_IDX                                                                        1
>+#define mmDAGB6_RDCLI9                                                                                 0x3089
>+#define mmDAGB6_RDCLI9_BASE_IDX                                                                        1
>+#define mmDAGB6_RDCLI10                                                                                0x308a
>+#define mmDAGB6_RDCLI10_BASE_IDX                                                                       1
>+#define mmDAGB6_RDCLI11                                                                                0x308b
>+#define mmDAGB6_RDCLI11_BASE_IDX                                                                       1
>+#define mmDAGB6_RDCLI12                                                                                0x308c
>+#define mmDAGB6_RDCLI12_BASE_IDX                                                                       1
>+#define mmDAGB6_RDCLI13                                                                                0x308d
>+#define mmDAGB6_RDCLI13_BASE_IDX                                                                       1
>+#define mmDAGB6_RDCLI14                                                                                0x308e
>+#define mmDAGB6_RDCLI14_BASE_IDX                                                                       1
>+#define mmDAGB6_RDCLI15                                                                                0x308f
>+#define mmDAGB6_RDCLI15_BASE_IDX                                                                       1
>+#define mmDAGB6_RD_CNTL                                                                                0x3090
>+#define mmDAGB6_RD_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB6_RD_GMI_CNTL                                                                            0x3091
>+#define mmDAGB6_RD_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_RD_ADDR_DAGB                                                                           0x3092
>+#define mmDAGB6_RD_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST                                                               0x3093
>+#define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER                                                              0x3094
>+#define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB6_RD_CGTT_CLK_CTRL                                                                       0x3095
>+#define mmDAGB6_RD_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL                                                                 0x3096
>+#define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL                                                                 0x3097
>+#define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0                                                                0x3098
>+#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0                                                               0x3099
>+#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1                                                                0x309a
>+#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1                                                               0x309b
>+#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB6_RD_VC0_CNTL                                                                            0x309c
>+#define mmDAGB6_RD_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_RD_VC1_CNTL                                                                            0x309d
>+#define mmDAGB6_RD_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_RD_VC2_CNTL                                                                            0x309e
>+#define mmDAGB6_RD_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_RD_VC3_CNTL                                                                            0x309f
>+#define mmDAGB6_RD_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_RD_VC4_CNTL                                                                            0x30a0
>+#define mmDAGB6_RD_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_RD_VC5_CNTL                                                                            0x30a1
>+#define mmDAGB6_RD_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_RD_VC6_CNTL                                                                            0x30a2
>+#define mmDAGB6_RD_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_RD_VC7_CNTL                                                                            0x30a3
>+#define mmDAGB6_RD_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_RD_CNTL_MISC                                                                           0x30a4
>+#define mmDAGB6_RD_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB6_RD_TLB_CREDIT                                                                          0x30a5
>+#define mmDAGB6_RD_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB6_RDCLI_ASK_PENDING                                                                      0x30a6
>+#define mmDAGB6_RDCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB6_RDCLI_GO_PENDING                                                                       0x30a7
>+#define mmDAGB6_RDCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB6_RDCLI_GBLSEND_PENDING                                                                  0x30a8
>+#define mmDAGB6_RDCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB6_RDCLI_TLB_PENDING                                                                      0x30a9
>+#define mmDAGB6_RDCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB6_RDCLI_OARB_PENDING                                                                     0x30aa
>+#define mmDAGB6_RDCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB6_RDCLI_OSD_PENDING                                                                      0x30ab
>+#define mmDAGB6_RDCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB6_WRCLI0                                                                                 0x30ac
>+#define mmDAGB6_WRCLI0_BASE_IDX                                                                        1
>+#define mmDAGB6_WRCLI1                                                                                 0x30ad
>+#define mmDAGB6_WRCLI1_BASE_IDX                                                                        1
>+#define mmDAGB6_WRCLI2                                                                                 0x30ae
>+#define mmDAGB6_WRCLI2_BASE_IDX                                                                        1
>+#define mmDAGB6_WRCLI3                                                                                 0x30af
>+#define mmDAGB6_WRCLI3_BASE_IDX                                                                        1
>+#define mmDAGB6_WRCLI4                                                                                 0x30b0
>+#define mmDAGB6_WRCLI4_BASE_IDX                                                                        1
>+#define mmDAGB6_WRCLI5                                                                                 0x30b1
>+#define mmDAGB6_WRCLI5_BASE_IDX                                                                        1
>+#define mmDAGB6_WRCLI6                                                                                 0x30b2
>+#define mmDAGB6_WRCLI6_BASE_IDX                                                                        1
>+#define mmDAGB6_WRCLI7                                                                                 0x30b3
>+#define mmDAGB6_WRCLI7_BASE_IDX                                                                        1
>+#define mmDAGB6_WRCLI8                                                                                 0x30b4
>+#define mmDAGB6_WRCLI8_BASE_IDX                                                                        1
>+#define mmDAGB6_WRCLI9                                                                                 0x30b5
>+#define mmDAGB6_WRCLI9_BASE_IDX                                                                        1
>+#define mmDAGB6_WRCLI10                                                                                0x30b6
>+#define mmDAGB6_WRCLI10_BASE_IDX                                                                       1
>+#define mmDAGB6_WRCLI11                                                                                0x30b7
>+#define mmDAGB6_WRCLI11_BASE_IDX                                                                       1
>+#define mmDAGB6_WRCLI12                                                                                0x30b8
>+#define mmDAGB6_WRCLI12_BASE_IDX                                                                       1
>+#define mmDAGB6_WRCLI13                                                                                0x30b9
>+#define mmDAGB6_WRCLI13_BASE_IDX                                                                       1
>+#define mmDAGB6_WRCLI14                                                                                0x30ba
>+#define mmDAGB6_WRCLI14_BASE_IDX                                                                       1
>+#define mmDAGB6_WRCLI15                                                                                0x30bb
>+#define mmDAGB6_WRCLI15_BASE_IDX                                                                       1
>+#define mmDAGB6_WR_CNTL                                                                                0x30bc
>+#define mmDAGB6_WR_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB6_WR_GMI_CNTL                                                                            0x30bd
>+#define mmDAGB6_WR_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_WR_ADDR_DAGB                                                                           0x30be
>+#define mmDAGB6_WR_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST                                                               0x30bf
>+#define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER                                                              0x30c0
>+#define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB6_WR_CGTT_CLK_CTRL                                                                       0x30c1
>+#define mmDAGB6_WR_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL                                                                 0x30c2
>+#define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL                                                                 0x30c3
>+#define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0                                                                0x30c4
>+#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0                                                               0x30c5
>+#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1                                                                0x30c6
>+#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1                                                               0x30c7
>+#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB6_WR_DATA_DAGB                                                                           0x30c8
>+#define mmDAGB6_WR_DATA_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB6_WR_DATA_DAGB_MAX_BURST0                                                                0x30c9
>+#define mmDAGB6_WR_DATA_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0                                                               0x30ca
>+#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB6_WR_DATA_DAGB_MAX_BURST1                                                                0x30cb
>+#define mmDAGB6_WR_DATA_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1                                                               0x30cc
>+#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB6_WR_VC0_CNTL                                                                            0x30cd
>+#define mmDAGB6_WR_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_WR_VC1_CNTL                                                                            0x30ce
>+#define mmDAGB6_WR_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_WR_VC2_CNTL                                                                            0x30cf
>+#define mmDAGB6_WR_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_WR_VC3_CNTL                                                                            0x30d0
>+#define mmDAGB6_WR_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_WR_VC4_CNTL                                                                            0x30d1
>+#define mmDAGB6_WR_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_WR_VC5_CNTL                                                                            0x30d2
>+#define mmDAGB6_WR_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_WR_VC6_CNTL                                                                            0x30d3
>+#define mmDAGB6_WR_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_WR_VC7_CNTL                                                                            0x30d4
>+#define mmDAGB6_WR_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB6_WR_CNTL_MISC                                                                           0x30d5
>+#define mmDAGB6_WR_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB6_WR_TLB_CREDIT                                                                          0x30d6
>+#define mmDAGB6_WR_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB6_WR_DATA_CREDIT                                                                         0x30d7
>+#define mmDAGB6_WR_DATA_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB6_WR_MISC_CREDIT                                                                         0x30d8
>+#define mmDAGB6_WR_MISC_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB6_WRCLI_ASK_PENDING                                                                      0x30dd
>+#define mmDAGB6_WRCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB6_WRCLI_GO_PENDING                                                                       0x30de
>+#define mmDAGB6_WRCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB6_WRCLI_GBLSEND_PENDING                                                                  0x30df
>+#define mmDAGB6_WRCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB6_WRCLI_TLB_PENDING                                                                      0x30e0
>+#define mmDAGB6_WRCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB6_WRCLI_OARB_PENDING                                                                     0x30e1
>+#define mmDAGB6_WRCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB6_WRCLI_OSD_PENDING                                                                      0x30e2
>+#define mmDAGB6_WRCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB6_WRCLI_DBUS_ASK_PENDING                                                                 0x30e3
>+#define mmDAGB6_WRCLI_DBUS_ASK_PENDING_BASE_IDX                                                        1
>+#define mmDAGB6_WRCLI_DBUS_GO_PENDING                                                                  0x30e4
>+#define mmDAGB6_WRCLI_DBUS_GO_PENDING_BASE_IDX                                                         1
>+#define mmDAGB6_DAGB_DLY                                                                               0x30e5
>+#define mmDAGB6_DAGB_DLY_BASE_IDX                                                                      1
>+#define mmDAGB6_CNTL_MISC                                                                              0x30e6
>+#define mmDAGB6_CNTL_MISC_BASE_IDX                                                                     1
>+#define mmDAGB6_CNTL_MISC2                                                                             0x30e7
>+#define mmDAGB6_CNTL_MISC2_BASE_IDX                                                                    1
>+#define mmDAGB6_FIFO_EMPTY                                                                             0x30e8
>+#define mmDAGB6_FIFO_EMPTY_BASE_IDX                                                                    1
>+#define mmDAGB6_FIFO_FULL                                                                              0x30e9
>+#define mmDAGB6_FIFO_FULL_BASE_IDX                                                                     1
>+#define mmDAGB6_WR_CREDITS_FULL                                                                        0x30ea
>+#define mmDAGB6_WR_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB6_RD_CREDITS_FULL                                                                        0x30eb
>+#define mmDAGB6_RD_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB6_PERFCOUNTER_LO                                                                         0x30ec
>+#define mmDAGB6_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmDAGB6_PERFCOUNTER_HI                                                                         0x30ed
>+#define mmDAGB6_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmDAGB6_PERFCOUNTER0_CFG                                                                       0x30ee
>+#define mmDAGB6_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmDAGB6_PERFCOUNTER1_CFG                                                                       0x30ef
>+#define mmDAGB6_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmDAGB6_PERFCOUNTER2_CFG                                                                       0x30f0
>+#define mmDAGB6_PERFCOUNTER2_CFG_BASE_IDX                                                              1
>+#define mmDAGB6_PERFCOUNTER_RSLT_CNTL                                                                  0x30f1
>+#define mmDAGB6_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmDAGB6_RESERVE0                                                                               0x30f2
>+#define mmDAGB6_RESERVE0_BASE_IDX                                                                      1
>+#define mmDAGB6_RESERVE1                                                                               0x30f3
>+#define mmDAGB6_RESERVE1_BASE_IDX                                                                      1
>+#define mmDAGB6_RESERVE2                                                                               0x30f4
>+#define mmDAGB6_RESERVE2_BASE_IDX                                                                      1
>+#define mmDAGB6_RESERVE3                                                                               0x30f5
>+#define mmDAGB6_RESERVE3_BASE_IDX                                                                      1
>+#define mmDAGB6_RESERVE4                                                                               0x30f6
>+#define mmDAGB6_RESERVE4_BASE_IDX                                                                      1
>+#define mmDAGB6_RESERVE5                                                                               0x30f7
>+#define mmDAGB6_RESERVE5_BASE_IDX                                                                      1
>+#define mmDAGB6_RESERVE6                                                                               0x30f8
>+#define mmDAGB6_RESERVE6_BASE_IDX                                                                      1
>+#define mmDAGB6_RESERVE7                                                                               0x30f9
>+#define mmDAGB6_RESERVE7_BASE_IDX                                                                      1
>+#define mmDAGB6_RESERVE8                                                                               0x30fa
>+#define mmDAGB6_RESERVE8_BASE_IDX                                                                      1
>+#define mmDAGB6_RESERVE9                                                                               0x30fb
>+#define mmDAGB6_RESERVE9_BASE_IDX                                                                      1
>+#define mmDAGB6_RESERVE10                                                                              0x30fc
>+#define mmDAGB6_RESERVE10_BASE_IDX                                                                     1
>+#define mmDAGB6_RESERVE11                                                                              0x30fd
>+#define mmDAGB6_RESERVE11_BASE_IDX                                                                     1
>+#define mmDAGB6_RESERVE12                                                                              0x30fe
>+#define mmDAGB6_RESERVE12_BASE_IDX                                                                     1
>+#define mmDAGB6_RESERVE13                                                                              0x30ff
>+#define mmDAGB6_RESERVE13_BASE_IDX                                                                     1
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec7
>+// base address: 0x74400
>+#define mmDAGB7_RDCLI0                                                                                 0x3100
>+#define mmDAGB7_RDCLI0_BASE_IDX                                                                        1
>+#define mmDAGB7_RDCLI1                                                                                 0x3101
>+#define mmDAGB7_RDCLI1_BASE_IDX                                                                        1
>+#define mmDAGB7_RDCLI2                                                                                 0x3102
>+#define mmDAGB7_RDCLI2_BASE_IDX                                                                        1
>+#define mmDAGB7_RDCLI3                                                                                 0x3103
>+#define mmDAGB7_RDCLI3_BASE_IDX                                                                        1
>+#define mmDAGB7_RDCLI4                                                                                 0x3104
>+#define mmDAGB7_RDCLI4_BASE_IDX                                                                        1
>+#define mmDAGB7_RDCLI5                                                                                 0x3105
>+#define mmDAGB7_RDCLI5_BASE_IDX                                                                        1
>+#define mmDAGB7_RDCLI6                                                                                 0x3106
>+#define mmDAGB7_RDCLI6_BASE_IDX                                                                        1
>+#define mmDAGB7_RDCLI7                                                                                 0x3107
>+#define mmDAGB7_RDCLI7_BASE_IDX                                                                        1
>+#define mmDAGB7_RDCLI8                                                                                 0x3108
>+#define mmDAGB7_RDCLI8_BASE_IDX                                                                        1
>+#define mmDAGB7_RDCLI9                                                                                 0x3109
>+#define mmDAGB7_RDCLI9_BASE_IDX                                                                        1
>+#define mmDAGB7_RDCLI10                                                                                0x310a
>+#define mmDAGB7_RDCLI10_BASE_IDX                                                                       1
>+#define mmDAGB7_RDCLI11                                                                                0x310b
>+#define mmDAGB7_RDCLI11_BASE_IDX                                                                       1
>+#define mmDAGB7_RDCLI12                                                                                0x310c
>+#define mmDAGB7_RDCLI12_BASE_IDX                                                                       1
>+#define mmDAGB7_RDCLI13                                                                                0x310d
>+#define mmDAGB7_RDCLI13_BASE_IDX                                                                       1
>+#define mmDAGB7_RDCLI14                                                                                0x310e
>+#define mmDAGB7_RDCLI14_BASE_IDX                                                                       1
>+#define mmDAGB7_RDCLI15                                                                                0x310f
>+#define mmDAGB7_RDCLI15_BASE_IDX                                                                       1
>+#define mmDAGB7_RD_CNTL                                                                                0x3110
>+#define mmDAGB7_RD_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB7_RD_GMI_CNTL                                                                            0x3111
>+#define mmDAGB7_RD_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_RD_ADDR_DAGB                                                                           0x3112
>+#define mmDAGB7_RD_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST                                                               0x3113
>+#define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER                                                              0x3114
>+#define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB7_RD_CGTT_CLK_CTRL                                                                       0x3115
>+#define mmDAGB7_RD_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL                                                                 0x3116
>+#define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL                                                                 0x3117
>+#define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0                                                                0x3118
>+#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0                                                               0x3119
>+#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1                                                                0x311a
>+#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1                                                               0x311b
>+#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB7_RD_VC0_CNTL                                                                            0x311c
>+#define mmDAGB7_RD_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_RD_VC1_CNTL                                                                            0x311d
>+#define mmDAGB7_RD_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_RD_VC2_CNTL                                                                            0x311e
>+#define mmDAGB7_RD_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_RD_VC3_CNTL                                                                            0x311f
>+#define mmDAGB7_RD_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_RD_VC4_CNTL                                                                            0x3120
>+#define mmDAGB7_RD_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_RD_VC5_CNTL                                                                            0x3121
>+#define mmDAGB7_RD_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_RD_VC6_CNTL                                                                            0x3122
>+#define mmDAGB7_RD_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_RD_VC7_CNTL                                                                            0x3123
>+#define mmDAGB7_RD_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_RD_CNTL_MISC                                                                           0x3124
>+#define mmDAGB7_RD_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB7_RD_TLB_CREDIT                                                                          0x3125
>+#define mmDAGB7_RD_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB7_RDCLI_ASK_PENDING                                                                      0x3126
>+#define mmDAGB7_RDCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB7_RDCLI_GO_PENDING                                                                       0x3127
>+#define mmDAGB7_RDCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB7_RDCLI_GBLSEND_PENDING                                                                  0x3128
>+#define mmDAGB7_RDCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB7_RDCLI_TLB_PENDING                                                                      0x3129
>+#define mmDAGB7_RDCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB7_RDCLI_OARB_PENDING                                                                     0x312a
>+#define mmDAGB7_RDCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB7_RDCLI_OSD_PENDING                                                                      0x312b
>+#define mmDAGB7_RDCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB7_WRCLI0                                                                                 0x312c
>+#define mmDAGB7_WRCLI0_BASE_IDX                                                                        1
>+#define mmDAGB7_WRCLI1                                                                                 0x312d
>+#define mmDAGB7_WRCLI1_BASE_IDX                                                                        1
>+#define mmDAGB7_WRCLI2                                                                                 0x312e
>+#define mmDAGB7_WRCLI2_BASE_IDX                                                                        1
>+#define mmDAGB7_WRCLI3                                                                                 0x312f
>+#define mmDAGB7_WRCLI3_BASE_IDX                                                                        1
>+#define mmDAGB7_WRCLI4                                                                                 0x3130
>+#define mmDAGB7_WRCLI4_BASE_IDX                                                                        1
>+#define mmDAGB7_WRCLI5                                                                                 0x3131
>+#define mmDAGB7_WRCLI5_BASE_IDX                                                                        1
>+#define mmDAGB7_WRCLI6                                                                                 0x3132
>+#define mmDAGB7_WRCLI6_BASE_IDX                                                                        1
>+#define mmDAGB7_WRCLI7                                                                                 0x3133
>+#define mmDAGB7_WRCLI7_BASE_IDX                                                                        1
>+#define mmDAGB7_WRCLI8                                                                                 0x3134
>+#define mmDAGB7_WRCLI8_BASE_IDX                                                                        1
>+#define mmDAGB7_WRCLI9                                                                                 0x3135
>+#define mmDAGB7_WRCLI9_BASE_IDX                                                                        1
>+#define mmDAGB7_WRCLI10                                                                                0x3136
>+#define mmDAGB7_WRCLI10_BASE_IDX                                                                       1
>+#define mmDAGB7_WRCLI11                                                                                0x3137
>+#define mmDAGB7_WRCLI11_BASE_IDX                                                                       1
>+#define mmDAGB7_WRCLI12                                                                                0x3138
>+#define mmDAGB7_WRCLI12_BASE_IDX                                                                       1
>+#define mmDAGB7_WRCLI13                                                                                0x3139
>+#define mmDAGB7_WRCLI13_BASE_IDX                                                                       1
>+#define mmDAGB7_WRCLI14                                                                                0x313a
>+#define mmDAGB7_WRCLI14_BASE_IDX                                                                       1
>+#define mmDAGB7_WRCLI15                                                                                0x313b
>+#define mmDAGB7_WRCLI15_BASE_IDX                                                                       1
>+#define mmDAGB7_WR_CNTL                                                                                0x313c
>+#define mmDAGB7_WR_CNTL_BASE_IDX                                                                       1
>+#define mmDAGB7_WR_GMI_CNTL                                                                            0x313d
>+#define mmDAGB7_WR_GMI_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_WR_ADDR_DAGB                                                                           0x313e
>+#define mmDAGB7_WR_ADDR_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST                                                               0x313f
>+#define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX                                                      1
>+#define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER                                                              0x3140
>+#define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX                                                     1
>+#define mmDAGB7_WR_CGTT_CLK_CTRL                                                                       0x3141
>+#define mmDAGB7_WR_CGTT_CLK_CTRL_BASE_IDX                                                              1
>+#define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL                                                                 0x3142
>+#define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL                                                                 0x3143
>+#define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0                                                                0x3144
>+#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0                                                               0x3145
>+#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1                                                                0x3146
>+#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1                                                               0x3147
>+#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB7_WR_DATA_DAGB                                                                           0x3148
>+#define mmDAGB7_WR_DATA_DAGB_BASE_IDX                                                                  1
>+#define mmDAGB7_WR_DATA_DAGB_MAX_BURST0                                                                0x3149
>+#define mmDAGB7_WR_DATA_DAGB_MAX_BURST0_BASE_IDX                                                       1
>+#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0                                                               0x314a
>+#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX                                                      1
>+#define mmDAGB7_WR_DATA_DAGB_MAX_BURST1                                                                0x314b
>+#define mmDAGB7_WR_DATA_DAGB_MAX_BURST1_BASE_IDX                                                       1
>+#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1                                                               0x314c
>+#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX                                                      1
>+#define mmDAGB7_WR_VC0_CNTL                                                                            0x314d
>+#define mmDAGB7_WR_VC0_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_WR_VC1_CNTL                                                                            0x314e
>+#define mmDAGB7_WR_VC1_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_WR_VC2_CNTL                                                                            0x314f
>+#define mmDAGB7_WR_VC2_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_WR_VC3_CNTL                                                                            0x3150
>+#define mmDAGB7_WR_VC3_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_WR_VC4_CNTL                                                                            0x3151
>+#define mmDAGB7_WR_VC4_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_WR_VC5_CNTL                                                                            0x3152
>+#define mmDAGB7_WR_VC5_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_WR_VC6_CNTL                                                                            0x3153
>+#define mmDAGB7_WR_VC6_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_WR_VC7_CNTL                                                                            0x3154
>+#define mmDAGB7_WR_VC7_CNTL_BASE_IDX                                                                   1
>+#define mmDAGB7_WR_CNTL_MISC                                                                           0x3155
>+#define mmDAGB7_WR_CNTL_MISC_BASE_IDX                                                                  1
>+#define mmDAGB7_WR_TLB_CREDIT                                                                          0x3156
>+#define mmDAGB7_WR_TLB_CREDIT_BASE_IDX                                                                 1
>+#define mmDAGB7_WR_DATA_CREDIT                                                                         0x3157
>+#define mmDAGB7_WR_DATA_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB7_WR_MISC_CREDIT                                                                         0x3158
>+#define mmDAGB7_WR_MISC_CREDIT_BASE_IDX                                                                1
>+#define mmDAGB7_WRCLI_ASK_PENDING                                                                      0x315d
>+#define mmDAGB7_WRCLI_ASK_PENDING_BASE_IDX                                                             1
>+#define mmDAGB7_WRCLI_GO_PENDING                                                                       0x315e
>+#define mmDAGB7_WRCLI_GO_PENDING_BASE_IDX                                                              1
>+#define mmDAGB7_WRCLI_GBLSEND_PENDING                                                                  0x315f
>+#define mmDAGB7_WRCLI_GBLSEND_PENDING_BASE_IDX                                                         1
>+#define mmDAGB7_WRCLI_TLB_PENDING                                                                      0x3160
>+#define mmDAGB7_WRCLI_TLB_PENDING_BASE_IDX                                                             1
>+#define mmDAGB7_WRCLI_OARB_PENDING                                                                     0x3161
>+#define mmDAGB7_WRCLI_OARB_PENDING_BASE_IDX                                                            1
>+#define mmDAGB7_WRCLI_OSD_PENDING                                                                      0x3162
>+#define mmDAGB7_WRCLI_OSD_PENDING_BASE_IDX                                                             1
>+#define mmDAGB7_WRCLI_DBUS_ASK_PENDING                                                                 0x3163
>+#define mmDAGB7_WRCLI_DBUS_ASK_PENDING_BASE_IDX                                                        1
>+#define mmDAGB7_WRCLI_DBUS_GO_PENDING                                                                  0x3164
>+#define mmDAGB7_WRCLI_DBUS_GO_PENDING_BASE_IDX                                                         1
>+#define mmDAGB7_DAGB_DLY                                                                               0x3165
>+#define mmDAGB7_DAGB_DLY_BASE_IDX                                                                      1
>+#define mmDAGB7_CNTL_MISC                                                                              0x3166
>+#define mmDAGB7_CNTL_MISC_BASE_IDX                                                                     1
>+#define mmDAGB7_CNTL_MISC2                                                                             0x3167
>+#define mmDAGB7_CNTL_MISC2_BASE_IDX                                                                    1
>+#define mmDAGB7_FIFO_EMPTY                                                                             0x3168
>+#define mmDAGB7_FIFO_EMPTY_BASE_IDX                                                                    1
>+#define mmDAGB7_FIFO_FULL                                                                              0x3169
>+#define mmDAGB7_FIFO_FULL_BASE_IDX                                                                     1
>+#define mmDAGB7_WR_CREDITS_FULL                                                                        0x316a
>+#define mmDAGB7_WR_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB7_RD_CREDITS_FULL                                                                        0x316b
>+#define mmDAGB7_RD_CREDITS_FULL_BASE_IDX                                                               1
>+#define mmDAGB7_PERFCOUNTER_LO                                                                         0x316c
>+#define mmDAGB7_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmDAGB7_PERFCOUNTER_HI                                                                         0x316d
>+#define mmDAGB7_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmDAGB7_PERFCOUNTER0_CFG                                                                       0x316e
>+#define mmDAGB7_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmDAGB7_PERFCOUNTER1_CFG                                                                       0x316f
>+#define mmDAGB7_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmDAGB7_PERFCOUNTER2_CFG                                                                       0x3170
>+#define mmDAGB7_PERFCOUNTER2_CFG_BASE_IDX                                                              1
>+#define mmDAGB7_PERFCOUNTER_RSLT_CNTL                                                                  0x3171
>+#define mmDAGB7_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmDAGB7_RESERVE0                                                                               0x3172
>+#define mmDAGB7_RESERVE0_BASE_IDX                                                                      1
>+#define mmDAGB7_RESERVE1                                                                               0x3173
>+#define mmDAGB7_RESERVE1_BASE_IDX                                                                      1
>+#define mmDAGB7_RESERVE2                                                                               0x3174
>+#define mmDAGB7_RESERVE2_BASE_IDX                                                                      1
>+#define mmDAGB7_RESERVE3                                                                               0x3175
>+#define mmDAGB7_RESERVE3_BASE_IDX                                                                      1
>+#define mmDAGB7_RESERVE4                                                                               0x3176
>+#define mmDAGB7_RESERVE4_BASE_IDX                                                                      1
>+#define mmDAGB7_RESERVE5                                                                               0x3177
>+#define mmDAGB7_RESERVE5_BASE_IDX                                                                      1
>+#define mmDAGB7_RESERVE6                                                                               0x3178
>+#define mmDAGB7_RESERVE6_BASE_IDX                                                                      1
>+#define mmDAGB7_RESERVE7                                                                               0x3179
>+#define mmDAGB7_RESERVE7_BASE_IDX                                                                      1
>+#define mmDAGB7_RESERVE8                                                                               0x317a
>+#define mmDAGB7_RESERVE8_BASE_IDX                                                                      1
>+#define mmDAGB7_RESERVE9                                                                               0x317b
>+#define mmDAGB7_RESERVE9_BASE_IDX                                                                      1
>+#define mmDAGB7_RESERVE10                                                                              0x317c
>+#define mmDAGB7_RESERVE10_BASE_IDX                                                                     1
>+#define mmDAGB7_RESERVE11                                                                              0x317d
>+#define mmDAGB7_RESERVE11_BASE_IDX                                                                     1
>+#define mmDAGB7_RESERVE12                                                                              0x317e
>+#define mmDAGB7_RESERVE12_BASE_IDX                                                                     1
>+#define mmDAGB7_RESERVE13                                                                              0x317f
>+#define mmDAGB7_RESERVE13_BASE_IDX                                                                     1
>+
>+
>+// addressBlock: mmhub_ea_mmeadec5
>+// base address: 0x74a00
>+#define mmMMEA5_DRAM_RD_CLI2GRP_MAP0                                                                   0x3280
>+#define mmMMEA5_DRAM_RD_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA5_DRAM_RD_CLI2GRP_MAP1                                                                   0x3281
>+#define mmMMEA5_DRAM_RD_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA5_DRAM_WR_CLI2GRP_MAP0                                                                   0x3282
>+#define mmMMEA5_DRAM_WR_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA5_DRAM_WR_CLI2GRP_MAP1                                                                   0x3283
>+#define mmMMEA5_DRAM_WR_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA5_DRAM_RD_GRP2VC_MAP                                                                     0x3284
>+#define mmMMEA5_DRAM_RD_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA5_DRAM_WR_GRP2VC_MAP                                                                     0x3285
>+#define mmMMEA5_DRAM_WR_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA5_DRAM_RD_LAZY                                                                           0x3286
>+#define mmMMEA5_DRAM_RD_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA5_DRAM_WR_LAZY                                                                           0x3287
>+#define mmMMEA5_DRAM_WR_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA5_DRAM_RD_CAM_CNTL                                                                       0x3288
>+#define mmMMEA5_DRAM_RD_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA5_DRAM_WR_CAM_CNTL                                                                       0x3289
>+#define mmMMEA5_DRAM_WR_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA5_DRAM_PAGE_BURST                                                                        0x328a
>+#define mmMMEA5_DRAM_PAGE_BURST_BASE_IDX                                                               1
>+#define mmMMEA5_DRAM_RD_PRI_AGE                                                                        0x328b
>+#define mmMMEA5_DRAM_RD_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA5_DRAM_WR_PRI_AGE                                                                        0x328c
>+#define mmMMEA5_DRAM_WR_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA5_DRAM_RD_PRI_QUEUING                                                                    0x328d
>+#define mmMMEA5_DRAM_RD_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA5_DRAM_WR_PRI_QUEUING                                                                    0x328e
>+#define mmMMEA5_DRAM_WR_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA5_DRAM_RD_PRI_FIXED                                                                      0x328f
>+#define mmMMEA5_DRAM_RD_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA5_DRAM_WR_PRI_FIXED                                                                      0x3290
>+#define mmMMEA5_DRAM_WR_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA5_DRAM_RD_PRI_URGENCY                                                                    0x3291
>+#define mmMMEA5_DRAM_RD_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA5_DRAM_WR_PRI_URGENCY                                                                    0x3292
>+#define mmMMEA5_DRAM_WR_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1                                                                 0x3293
>+#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2                                                                 0x3294
>+#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3                                                                 0x3295
>+#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1                                                                 0x3296
>+#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2                                                                 0x3297
>+#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3                                                                 0x3298
>+#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA5_GMI_RD_CLI2GRP_MAP0                                                                    0x3299
>+#define mmMMEA5_GMI_RD_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA5_GMI_RD_CLI2GRP_MAP1                                                                    0x329a
>+#define mmMMEA5_GMI_RD_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA5_GMI_WR_CLI2GRP_MAP0                                                                    0x329b
>+#define mmMMEA5_GMI_WR_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA5_GMI_WR_CLI2GRP_MAP1                                                                    0x329c
>+#define mmMMEA5_GMI_WR_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA5_GMI_RD_GRP2VC_MAP                                                                      0x329d
>+#define mmMMEA5_GMI_RD_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA5_GMI_WR_GRP2VC_MAP                                                                      0x329e
>+#define mmMMEA5_GMI_WR_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA5_GMI_RD_LAZY                                                                            0x329f
>+#define mmMMEA5_GMI_RD_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA5_GMI_WR_LAZY                                                                            0x32a0
>+#define mmMMEA5_GMI_WR_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA5_GMI_RD_CAM_CNTL                                                                        0x32a1
>+#define mmMMEA5_GMI_RD_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA5_GMI_WR_CAM_CNTL                                                                        0x32a2
>+#define mmMMEA5_GMI_WR_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA5_GMI_PAGE_BURST                                                                         0x32a3
>+#define mmMMEA5_GMI_PAGE_BURST_BASE_IDX                                                                1
>+#define mmMMEA5_GMI_RD_PRI_AGE                                                                         0x32a4
>+#define mmMMEA5_GMI_RD_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA5_GMI_WR_PRI_AGE                                                                         0x32a5
>+#define mmMMEA5_GMI_WR_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA5_GMI_RD_PRI_QUEUING                                                                     0x32a6
>+#define mmMMEA5_GMI_RD_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA5_GMI_WR_PRI_QUEUING                                                                     0x32a7
>+#define mmMMEA5_GMI_WR_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA5_GMI_RD_PRI_FIXED                                                                       0x32a8
>+#define mmMMEA5_GMI_RD_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA5_GMI_WR_PRI_FIXED                                                                       0x32a9
>+#define mmMMEA5_GMI_WR_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA5_GMI_RD_PRI_URGENCY                                                                     0x32aa
>+#define mmMMEA5_GMI_RD_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA5_GMI_WR_PRI_URGENCY                                                                     0x32ab
>+#define mmMMEA5_GMI_WR_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING                                                             0x32ac
>+#define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING                                                             0x32ad
>+#define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA5_GMI_RD_PRI_QUANT_PRI1                                                                  0x32ae
>+#define mmMMEA5_GMI_RD_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA5_GMI_RD_PRI_QUANT_PRI2                                                                  0x32af
>+#define mmMMEA5_GMI_RD_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA5_GMI_RD_PRI_QUANT_PRI3                                                                  0x32b0
>+#define mmMMEA5_GMI_RD_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA5_GMI_WR_PRI_QUANT_PRI1                                                                  0x32b1
>+#define mmMMEA5_GMI_WR_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA5_GMI_WR_PRI_QUANT_PRI2                                                                  0x32b2
>+#define mmMMEA5_GMI_WR_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA5_GMI_WR_PRI_QUANT_PRI3                                                                  0x32b3
>+#define mmMMEA5_GMI_WR_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA5_ADDRNORM_BASE_ADDR0                                                                    0x32b4
>+#define mmMMEA5_ADDRNORM_BASE_ADDR0_BASE_IDX                                                           1
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR0                                                                   0x32b5
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR0_BASE_IDX                                                          1
>+#define mmMMEA5_ADDRNORM_BASE_ADDR1                                                                    0x32b6
>+#define mmMMEA5_ADDRNORM_BASE_ADDR1_BASE_IDX                                                           1
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR1                                                                   0x32b7
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR1_BASE_IDX                                                          1
>+#define mmMMEA5_ADDRNORM_OFFSET_ADDR1                                                                  0x32b8
>+#define mmMMEA5_ADDRNORM_OFFSET_ADDR1_BASE_IDX                                                         1
>+#define mmMMEA5_ADDRNORM_BASE_ADDR2                                                                    0x32b9
>+#define mmMMEA5_ADDRNORM_BASE_ADDR2_BASE_IDX                                                           1
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR2                                                                   0x32ba
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR2_BASE_IDX                                                          1
>+#define mmMMEA5_ADDRNORM_BASE_ADDR3                                                                    0x32bb
>+#define mmMMEA5_ADDRNORM_BASE_ADDR3_BASE_IDX                                                           1
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR3                                                                   0x32bc
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR3_BASE_IDX                                                          1
>+#define mmMMEA5_ADDRNORM_OFFSET_ADDR3                                                                  0x32bd
>+#define mmMMEA5_ADDRNORM_OFFSET_ADDR3_BASE_IDX                                                         1
>+#define mmMMEA5_ADDRNORM_BASE_ADDR4                                                                    0x32be
>+#define mmMMEA5_ADDRNORM_BASE_ADDR4_BASE_IDX                                                           1
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR4                                                                   0x32bf
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR4_BASE_IDX                                                          1
>+#define mmMMEA5_ADDRNORM_BASE_ADDR5                                                                    0x32c0
>+#define mmMMEA5_ADDRNORM_BASE_ADDR5_BASE_IDX                                                           1
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR5                                                                   0x32c1
>+#define mmMMEA5_ADDRNORM_LIMIT_ADDR5_BASE_IDX                                                          1
>+#define mmMMEA5_ADDRNORM_OFFSET_ADDR5                                                                  0x32c2
>+#define mmMMEA5_ADDRNORM_OFFSET_ADDR5_BASE_IDX                                                         1
>+#define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL                                                                 0x32c3
>+#define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRNORMGMI_HOLE_CNTL                                                                  0x32c4
>+#define mmMMEA5_ADDRNORMGMI_HOLE_CNTL_BASE_IDX                                                         1
>+#define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG                                                           0x32c5
>+#define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX                                                  1
>+#define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG                                                            0x32c6
>+#define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX                                                   1
>+#define mmMMEA5_ADDRDEC_BANK_CFG                                                                       0x32c7
>+#define mmMMEA5_ADDRDEC_BANK_CFG_BASE_IDX                                                              1
>+#define mmMMEA5_ADDRDEC_MISC_CFG                                                                       0x32c8
>+#define mmMMEA5_ADDRDEC_MISC_CFG_BASE_IDX                                                              1
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0                                                            0x32c9
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX                                                   1
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1                                                            0x32ca
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX                                                   1
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2                                                            0x32cb
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX                                                   1
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3                                                            0x32cc
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX                                                   1
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4                                                            0x32cd
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX                                                   1
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5                                                            0x32ce
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX                                                   1
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC                                                               0x32cf
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2                                                              0x32d0
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0                                                              0x32d1
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1                                                              0x32d2
>+#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE                                                             0x32d3
>+#define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0                                                             0x32d4
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1                                                             0x32d5
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2                                                             0x32d6
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3                                                             0x32d7
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4                                                             0x32d8
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5                                                             0x32d9
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC                                                                0x32da
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2                                                               0x32db
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0                                                               0x32dc
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1                                                               0x32dd
>+#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE                                                              0x32de
>+#define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0                                                                 0x32df
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1                                                                 0x32e0
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2                                                                 0x32e1
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3                                                                 0x32e2
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0                                                              0x32e3
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1                                                              0x32e4
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2                                                              0x32e5
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3                                                              0x32e6
>+#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01                                                                0x32e7
>+#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23                                                                0x32e8
>+#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01                                                             0x32e9
>+#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23                                                             0x32ea
>+#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01                                                                 0x32eb
>+#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23                                                                 0x32ec
>+#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01                                                                 0x32ed
>+#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23                                                                 0x32ee
>+#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01                                                                0x32ef
>+#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23                                                                0x32f0
>+#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01                                                               0x32f1
>+#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23                                                               0x32f2
>+#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01                                                               0x32f3
>+#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23                                                               0x32f4
>+#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDEC0_RM_SEL_CS01                                                                   0x32f5
>+#define mmMMEA5_ADDRDEC0_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA5_ADDRDEC0_RM_SEL_CS23                                                                   0x32f6
>+#define mmMMEA5_ADDRDEC0_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01                                                                0x32f7
>+#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23                                                                0x32f8
>+#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0                                                                 0x32f9
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1                                                                 0x32fa
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2                                                                 0x32fb
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3                                                                 0x32fc
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0                                                              0x32fd
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1                                                              0x32fe
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2                                                              0x32ff
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3                                                              0x3300
>+#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01                                                                0x3301
>+#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23                                                                0x3302
>+#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01                                                             0x3303
>+#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23                                                             0x3304
>+#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01                                                                 0x3305
>+#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23                                                                 0x3306
>+#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01                                                                 0x3307
>+#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23                                                                 0x3308
>+#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01                                                                0x3309
>+#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23                                                                0x330a
>+#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01                                                               0x330b
>+#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23                                                               0x330c
>+#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01                                                               0x330d
>+#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23                                                               0x330e
>+#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDEC1_RM_SEL_CS01                                                                   0x330f
>+#define mmMMEA5_ADDRDEC1_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA5_ADDRDEC1_RM_SEL_CS23                                                                   0x3310
>+#define mmMMEA5_ADDRDEC1_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01                                                                0x3311
>+#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23                                                                0x3312
>+#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0                                                                 0x3313
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1                                                                 0x3314
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2                                                                 0x3315
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3                                                                 0x3316
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0                                                              0x3317
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1                                                              0x3318
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2                                                              0x3319
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3                                                              0x331a
>+#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01                                                                0x331b
>+#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23                                                                0x331c
>+#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01                                                             0x331d
>+#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23                                                             0x331e
>+#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01                                                                 0x331f
>+#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23                                                                 0x3320
>+#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01                                                                 0x3321
>+#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23                                                                 0x3322
>+#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01                                                                0x3323
>+#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23                                                                0x3324
>+#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01                                                               0x3325
>+#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23                                                               0x3326
>+#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01                                                               0x3327
>+#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23                                                               0x3328
>+#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRDEC2_RM_SEL_CS01                                                                   0x3329
>+#define mmMMEA5_ADDRDEC2_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA5_ADDRDEC2_RM_SEL_CS23                                                                   0x332a
>+#define mmMMEA5_ADDRDEC2_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01                                                                0x332b
>+#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23                                                                0x332c
>+#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL                                                               0x332d
>+#define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX                                                      1
>+#define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL                                                                0x332e
>+#define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX                                                       1
>+#define mmMMEA5_IO_RD_CLI2GRP_MAP0                                                                     0x3355
>+#define mmMMEA5_IO_RD_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA5_IO_RD_CLI2GRP_MAP1                                                                     0x3356
>+#define mmMMEA5_IO_RD_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA5_IO_WR_CLI2GRP_MAP0                                                                     0x3357
>+#define mmMMEA5_IO_WR_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA5_IO_WR_CLI2GRP_MAP1                                                                     0x3358
>+#define mmMMEA5_IO_WR_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA5_IO_RD_COMBINE_FLUSH                                                                    0x3359
>+#define mmMMEA5_IO_RD_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA5_IO_WR_COMBINE_FLUSH                                                                    0x335a
>+#define mmMMEA5_IO_WR_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA5_IO_GROUP_BURST                                                                         0x335b
>+#define mmMMEA5_IO_GROUP_BURST_BASE_IDX                                                                1
>+#define mmMMEA5_IO_RD_PRI_AGE                                                                          0x335c
>+#define mmMMEA5_IO_RD_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA5_IO_WR_PRI_AGE                                                                          0x335d
>+#define mmMMEA5_IO_WR_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA5_IO_RD_PRI_QUEUING                                                                      0x335e
>+#define mmMMEA5_IO_RD_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA5_IO_WR_PRI_QUEUING                                                                      0x335f
>+#define mmMMEA5_IO_WR_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA5_IO_RD_PRI_FIXED                                                                        0x3360
>+#define mmMMEA5_IO_RD_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA5_IO_WR_PRI_FIXED                                                                        0x3361
>+#define mmMMEA5_IO_WR_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA5_IO_RD_PRI_URGENCY                                                                      0x3362
>+#define mmMMEA5_IO_RD_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA5_IO_WR_PRI_URGENCY                                                                      0x3363
>+#define mmMMEA5_IO_WR_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA5_IO_RD_PRI_URGENCY_MASKING                                                              0x3364
>+#define mmMMEA5_IO_RD_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA5_IO_WR_PRI_URGENCY_MASKING                                                              0x3365
>+#define mmMMEA5_IO_WR_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA5_IO_RD_PRI_QUANT_PRI1                                                                   0x3366
>+#define mmMMEA5_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA5_IO_RD_PRI_QUANT_PRI2                                                                   0x3367
>+#define mmMMEA5_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA5_IO_RD_PRI_QUANT_PRI3                                                                   0x3368
>+#define mmMMEA5_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA5_IO_WR_PRI_QUANT_PRI1                                                                   0x3369
>+#define mmMMEA5_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA5_IO_WR_PRI_QUANT_PRI2                                                                   0x336a
>+#define mmMMEA5_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA5_IO_WR_PRI_QUANT_PRI3                                                                   0x336b
>+#define mmMMEA5_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA5_SDP_ARB_DRAM                                                                           0x336c
>+#define mmMMEA5_SDP_ARB_DRAM_BASE_IDX                                                                  1
>+#define mmMMEA5_SDP_ARB_GMI                                                                            0x336d
>+#define mmMMEA5_SDP_ARB_GMI_BASE_IDX                                                                   1
>+#define mmMMEA5_SDP_ARB_FINAL                                                                          0x336e
>+#define mmMMEA5_SDP_ARB_FINAL_BASE_IDX                                                                 1
>+#define mmMMEA5_SDP_DRAM_PRIORITY                                                                      0x336f
>+#define mmMMEA5_SDP_DRAM_PRIORITY_BASE_IDX                                                             1
>+#define mmMMEA5_SDP_GMI_PRIORITY                                                                       0x3370
>+#define mmMMEA5_SDP_GMI_PRIORITY_BASE_IDX                                                              1
>+#define mmMMEA5_SDP_IO_PRIORITY                                                                        0x3371
>+#define mmMMEA5_SDP_IO_PRIORITY_BASE_IDX                                                               1
>+#define mmMMEA5_SDP_CREDITS                                                                            0x3372
>+#define mmMMEA5_SDP_CREDITS_BASE_IDX                                                                   1
>+#define mmMMEA5_SDP_TAG_RESERVE0                                                                       0x3373
>+#define mmMMEA5_SDP_TAG_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA5_SDP_TAG_RESERVE1                                                                       0x3374
>+#define mmMMEA5_SDP_TAG_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA5_SDP_VCC_RESERVE0                                                                       0x3375
>+#define mmMMEA5_SDP_VCC_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA5_SDP_VCC_RESERVE1                                                                       0x3376
>+#define mmMMEA5_SDP_VCC_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA5_SDP_VCD_RESERVE0                                                                       0x3377
>+#define mmMMEA5_SDP_VCD_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA5_SDP_VCD_RESERVE1                                                                       0x3378
>+#define mmMMEA5_SDP_VCD_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA5_SDP_REQ_CNTL                                                                           0x3379
>+#define mmMMEA5_SDP_REQ_CNTL_BASE_IDX                                                                  1
>+#define mmMMEA5_MISC                                                                                   0x337a
>+#define mmMMEA5_MISC_BASE_IDX                                                                          1
>+#define mmMMEA5_LATENCY_SAMPLING                                                                       0x337b
>+#define mmMMEA5_LATENCY_SAMPLING_BASE_IDX                                                              1
>+#define mmMMEA5_PERFCOUNTER_LO                                                                         0x337c
>+#define mmMMEA5_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmMMEA5_PERFCOUNTER_HI                                                                         0x337d
>+#define mmMMEA5_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmMMEA5_PERFCOUNTER0_CFG                                                                       0x337e
>+#define mmMMEA5_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmMMEA5_PERFCOUNTER1_CFG                                                                       0x337f
>+#define mmMMEA5_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmMMEA5_PERFCOUNTER_RSLT_CNTL                                                                  0x3380
>+#define mmMMEA5_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmMMEA5_EDC_CNT                                                                                0x3386
>+#define mmMMEA5_EDC_CNT_BASE_IDX                                                                       1
>+#define mmMMEA5_EDC_CNT2                                                                               0x3387
>+#define mmMMEA5_EDC_CNT2_BASE_IDX                                                                      1
>+#define mmMMEA5_DSM_CNTL                                                                               0x3388
>+#define mmMMEA5_DSM_CNTL_BASE_IDX                                                                      1
>+#define mmMMEA5_DSM_CNTLA                                                                              0x3389
>+#define mmMMEA5_DSM_CNTLA_BASE_IDX                                                                     1
>+#define mmMMEA5_DSM_CNTLB                                                                              0x338a
>+#define mmMMEA5_DSM_CNTLB_BASE_IDX                                                                     1
>+#define mmMMEA5_DSM_CNTL2                                                                              0x338b
>+#define mmMMEA5_DSM_CNTL2_BASE_IDX                                                                     1
>+#define mmMMEA5_DSM_CNTL2A                                                                             0x338c
>+#define mmMMEA5_DSM_CNTL2A_BASE_IDX                                                                    1
>+#define mmMMEA5_DSM_CNTL2B                                                                             0x338d
>+#define mmMMEA5_DSM_CNTL2B_BASE_IDX                                                                    1
>+#define mmMMEA5_CGTT_CLK_CTRL                                                                          0x338f
>+#define mmMMEA5_CGTT_CLK_CTRL_BASE_IDX                                                                 1
>+#define mmMMEA5_EDC_MODE                                                                               0x3390
>+#define mmMMEA5_EDC_MODE_BASE_IDX                                                                      1
>+#define mmMMEA5_ERR_STATUS                                                                             0x3391
>+#define mmMMEA5_ERR_STATUS_BASE_IDX                                                                    1
>+#define mmMMEA5_MISC2                                                                                  0x3392
>+#define mmMMEA5_MISC2_BASE_IDX                                                                         1
>+#define mmMMEA5_ADDRDEC_SELECT                                                                         0x3393
>+#define mmMMEA5_ADDRDEC_SELECT_BASE_IDX                                                                1
>+#define mmMMEA5_EDC_CNT3                                                                               0x3394
>+#define mmMMEA5_EDC_CNT3_BASE_IDX                                                                      1
>+
>+
>+// addressBlock: mmhub_ea_mmeadec6
>+// base address: 0x74f00
>+#define mmMMEA6_DRAM_RD_CLI2GRP_MAP0                                                                   0x33c0
>+#define mmMMEA6_DRAM_RD_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA6_DRAM_RD_CLI2GRP_MAP1                                                                   0x33c1
>+#define mmMMEA6_DRAM_RD_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA6_DRAM_WR_CLI2GRP_MAP0                                                                   0x33c2
>+#define mmMMEA6_DRAM_WR_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA6_DRAM_WR_CLI2GRP_MAP1                                                                   0x33c3
>+#define mmMMEA6_DRAM_WR_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA6_DRAM_RD_GRP2VC_MAP                                                                     0x33c4
>+#define mmMMEA6_DRAM_RD_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA6_DRAM_WR_GRP2VC_MAP                                                                     0x33c5
>+#define mmMMEA6_DRAM_WR_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA6_DRAM_RD_LAZY                                                                           0x33c6
>+#define mmMMEA6_DRAM_RD_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA6_DRAM_WR_LAZY                                                                           0x33c7
>+#define mmMMEA6_DRAM_WR_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA6_DRAM_RD_CAM_CNTL                                                                       0x33c8
>+#define mmMMEA6_DRAM_RD_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA6_DRAM_WR_CAM_CNTL                                                                       0x33c9
>+#define mmMMEA6_DRAM_WR_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA6_DRAM_PAGE_BURST                                                                        0x33ca
>+#define mmMMEA6_DRAM_PAGE_BURST_BASE_IDX                                                               1
>+#define mmMMEA6_DRAM_RD_PRI_AGE                                                                        0x33cb
>+#define mmMMEA6_DRAM_RD_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA6_DRAM_WR_PRI_AGE                                                                        0x33cc
>+#define mmMMEA6_DRAM_WR_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA6_DRAM_RD_PRI_QUEUING                                                                    0x33cd
>+#define mmMMEA6_DRAM_RD_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA6_DRAM_WR_PRI_QUEUING                                                                    0x33ce
>+#define mmMMEA6_DRAM_WR_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA6_DRAM_RD_PRI_FIXED                                                                      0x33cf
>+#define mmMMEA6_DRAM_RD_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA6_DRAM_WR_PRI_FIXED                                                                      0x33d0
>+#define mmMMEA6_DRAM_WR_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA6_DRAM_RD_PRI_URGENCY                                                                    0x33d1
>+#define mmMMEA6_DRAM_RD_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA6_DRAM_WR_PRI_URGENCY                                                                    0x33d2
>+#define mmMMEA6_DRAM_WR_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1                                                                 0x33d3
>+#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2                                                                 0x33d4
>+#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3                                                                 0x33d5
>+#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1                                                                 0x33d6
>+#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2                                                                 0x33d7
>+#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3                                                                 0x33d8
>+#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA6_GMI_RD_CLI2GRP_MAP0                                                                    0x33d9
>+#define mmMMEA6_GMI_RD_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA6_GMI_RD_CLI2GRP_MAP1                                                                    0x33da
>+#define mmMMEA6_GMI_RD_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA6_GMI_WR_CLI2GRP_MAP0                                                                    0x33db
>+#define mmMMEA6_GMI_WR_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA6_GMI_WR_CLI2GRP_MAP1                                                                    0x33dc
>+#define mmMMEA6_GMI_WR_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA6_GMI_RD_GRP2VC_MAP                                                                      0x33dd
>+#define mmMMEA6_GMI_RD_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA6_GMI_WR_GRP2VC_MAP                                                                      0x33de
>+#define mmMMEA6_GMI_WR_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA6_GMI_RD_LAZY                                                                            0x33df
>+#define mmMMEA6_GMI_RD_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA6_GMI_WR_LAZY                                                                            0x33e0
>+#define mmMMEA6_GMI_WR_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA6_GMI_RD_CAM_CNTL                                                                        0x33e1
>+#define mmMMEA6_GMI_RD_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA6_GMI_WR_CAM_CNTL                                                                        0x33e2
>+#define mmMMEA6_GMI_WR_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA6_GMI_PAGE_BURST                                                                         0x33e3
>+#define mmMMEA6_GMI_PAGE_BURST_BASE_IDX                                                                1
>+#define mmMMEA6_GMI_RD_PRI_AGE                                                                         0x33e4
>+#define mmMMEA6_GMI_RD_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA6_GMI_WR_PRI_AGE                                                                         0x33e5
>+#define mmMMEA6_GMI_WR_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA6_GMI_RD_PRI_QUEUING                                                                     0x33e6
>+#define mmMMEA6_GMI_RD_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA6_GMI_WR_PRI_QUEUING                                                                     0x33e7
>+#define mmMMEA6_GMI_WR_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA6_GMI_RD_PRI_FIXED                                                                       0x33e8
>+#define mmMMEA6_GMI_RD_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA6_GMI_WR_PRI_FIXED                                                                       0x33e9
>+#define mmMMEA6_GMI_WR_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA6_GMI_RD_PRI_URGENCY                                                                     0x33ea
>+#define mmMMEA6_GMI_RD_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA6_GMI_WR_PRI_URGENCY                                                                     0x33eb
>+#define mmMMEA6_GMI_WR_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING                                                             0x33ec
>+#define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING                                                             0x33ed
>+#define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA6_GMI_RD_PRI_QUANT_PRI1                                                                  0x33ee
>+#define mmMMEA6_GMI_RD_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA6_GMI_RD_PRI_QUANT_PRI2                                                                  0x33ef
>+#define mmMMEA6_GMI_RD_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA6_GMI_RD_PRI_QUANT_PRI3                                                                  0x33f0
>+#define mmMMEA6_GMI_RD_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA6_GMI_WR_PRI_QUANT_PRI1                                                                  0x33f1
>+#define mmMMEA6_GMI_WR_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA6_GMI_WR_PRI_QUANT_PRI2                                                                  0x33f2
>+#define mmMMEA6_GMI_WR_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA6_GMI_WR_PRI_QUANT_PRI3                                                                  0x33f3
>+#define mmMMEA6_GMI_WR_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA6_ADDRNORM_BASE_ADDR0                                                                    0x33f4
>+#define mmMMEA6_ADDRNORM_BASE_ADDR0_BASE_IDX                                                           1
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR0                                                                   0x33f5
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR0_BASE_IDX                                                          1
>+#define mmMMEA6_ADDRNORM_BASE_ADDR1                                                                    0x33f6
>+#define mmMMEA6_ADDRNORM_BASE_ADDR1_BASE_IDX                                                           1
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR1                                                                   0x33f7
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR1_BASE_IDX                                                          1
>+#define mmMMEA6_ADDRNORM_OFFSET_ADDR1                                                                  0x33f8
>+#define mmMMEA6_ADDRNORM_OFFSET_ADDR1_BASE_IDX                                                         1
>+#define mmMMEA6_ADDRNORM_BASE_ADDR2                                                                    0x33f9
>+#define mmMMEA6_ADDRNORM_BASE_ADDR2_BASE_IDX                                                           1
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR2                                                                   0x33fa
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR2_BASE_IDX                                                          1
>+#define mmMMEA6_ADDRNORM_BASE_ADDR3                                                                    0x33fb
>+#define mmMMEA6_ADDRNORM_BASE_ADDR3_BASE_IDX                                                           1
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR3                                                                   0x33fc
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR3_BASE_IDX                                                          1
>+#define mmMMEA6_ADDRNORM_OFFSET_ADDR3                                                                  0x33fd
>+#define mmMMEA6_ADDRNORM_OFFSET_ADDR3_BASE_IDX                                                         1
>+#define mmMMEA6_ADDRNORM_BASE_ADDR4                                                                    0x33fe
>+#define mmMMEA6_ADDRNORM_BASE_ADDR4_BASE_IDX                                                           1
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR4                                                                   0x33ff
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR4_BASE_IDX                                                          1
>+#define mmMMEA6_ADDRNORM_BASE_ADDR5                                                                    0x3400
>+#define mmMMEA6_ADDRNORM_BASE_ADDR5_BASE_IDX                                                           1
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR5                                                                   0x3401
>+#define mmMMEA6_ADDRNORM_LIMIT_ADDR5_BASE_IDX                                                          1
>+#define mmMMEA6_ADDRNORM_OFFSET_ADDR5                                                                  0x3402
>+#define mmMMEA6_ADDRNORM_OFFSET_ADDR5_BASE_IDX                                                         1
>+#define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL                                                                 0x3403
>+#define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRNORMGMI_HOLE_CNTL                                                                  0x3404
>+#define mmMMEA6_ADDRNORMGMI_HOLE_CNTL_BASE_IDX                                                         1
>+#define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG                                                           0x3405
>+#define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX                                                  1
>+#define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG                                                            0x3406
>+#define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX                                                   1
>+#define mmMMEA6_ADDRDEC_BANK_CFG                                                                       0x3407
>+#define mmMMEA6_ADDRDEC_BANK_CFG_BASE_IDX                                                              1
>+#define mmMMEA6_ADDRDEC_MISC_CFG                                                                       0x3408
>+#define mmMMEA6_ADDRDEC_MISC_CFG_BASE_IDX                                                              1
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0                                                            0x3409
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX                                                   1
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1                                                            0x340a
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX                                                   1
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2                                                            0x340b
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX                                                   1
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3                                                            0x340c
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX                                                   1
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4                                                            0x340d
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX                                                   1
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5                                                            0x340e
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX                                                   1
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC                                                               0x340f
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2                                                              0x3410
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0                                                              0x3411
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1                                                              0x3412
>+#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE                                                             0x3413
>+#define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0                                                             0x3414
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1                                                             0x3415
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2                                                             0x3416
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3                                                             0x3417
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4                                                             0x3418
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5                                                             0x3419
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC                                                                0x341a
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2                                                               0x341b
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0                                                               0x341c
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1                                                               0x341d
>+#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE                                                              0x341e
>+#define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0                                                                 0x341f
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1                                                                 0x3420
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2                                                                 0x3421
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3                                                                 0x3422
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0                                                              0x3423
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1                                                              0x3424
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2                                                              0x3425
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3                                                              0x3426
>+#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01                                                                0x3427
>+#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23                                                                0x3428
>+#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01                                                             0x3429
>+#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23                                                             0x342a
>+#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01                                                                 0x342b
>+#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23                                                                 0x342c
>+#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01                                                                 0x342d
>+#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23                                                                 0x342e
>+#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01                                                                0x342f
>+#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23                                                                0x3430
>+#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01                                                               0x3431
>+#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23                                                               0x3432
>+#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01                                                               0x3433
>+#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23                                                               0x3434
>+#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDEC0_RM_SEL_CS01                                                                   0x3435
>+#define mmMMEA6_ADDRDEC0_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA6_ADDRDEC0_RM_SEL_CS23                                                                   0x3436
>+#define mmMMEA6_ADDRDEC0_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01                                                                0x3437
>+#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23                                                                0x3438
>+#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0                                                                 0x3439
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1                                                                 0x343a
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2                                                                 0x343b
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3                                                                 0x343c
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0                                                              0x343d
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1                                                              0x343e
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2                                                              0x343f
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3                                                              0x3440
>+#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01                                                                0x3441
>+#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23                                                                0x3442
>+#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01                                                             0x3443
>+#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23                                                             0x3444
>+#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01                                                                 0x3445
>+#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23                                                                 0x3446
>+#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01                                                                 0x3447
>+#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23                                                                 0x3448
>+#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01                                                                0x3449
>+#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23                                                                0x344a
>+#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01                                                               0x344b
>+#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23                                                               0x344c
>+#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01                                                               0x344d
>+#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23                                                               0x344e
>+#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDEC1_RM_SEL_CS01                                                                   0x344f
>+#define mmMMEA6_ADDRDEC1_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA6_ADDRDEC1_RM_SEL_CS23                                                                   0x3450
>+#define mmMMEA6_ADDRDEC1_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01                                                                0x3451
>+#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23                                                                0x3452
>+#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0                                                                 0x3453
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1                                                                 0x3454
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2                                                                 0x3455
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3                                                                 0x3456
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0                                                              0x3457
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1                                                              0x3458
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2                                                              0x3459
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3                                                              0x345a
>+#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01                                                                0x345b
>+#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23                                                                0x345c
>+#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01                                                             0x345d
>+#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23                                                             0x345e
>+#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01                                                                 0x345f
>+#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23                                                                 0x3460
>+#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01                                                                 0x3461
>+#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23                                                                 0x3462
>+#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01                                                                0x3463
>+#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23                                                                0x3464
>+#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01                                                               0x3465
>+#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23                                                               0x3466
>+#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01                                                               0x3467
>+#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23                                                               0x3468
>+#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRDEC2_RM_SEL_CS01                                                                   0x3469
>+#define mmMMEA6_ADDRDEC2_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA6_ADDRDEC2_RM_SEL_CS23                                                                   0x346a
>+#define mmMMEA6_ADDRDEC2_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01                                                                0x346b
>+#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23                                                                0x346c
>+#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL                                                               0x346d
>+#define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX                                                      1
>+#define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL                                                                0x346e
>+#define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX                                                       1
>+#define mmMMEA6_IO_RD_CLI2GRP_MAP0                                                                     0x3495
>+#define mmMMEA6_IO_RD_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA6_IO_RD_CLI2GRP_MAP1                                                                     0x3496
>+#define mmMMEA6_IO_RD_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA6_IO_WR_CLI2GRP_MAP0                                                                     0x3497
>+#define mmMMEA6_IO_WR_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA6_IO_WR_CLI2GRP_MAP1                                                                     0x3498
>+#define mmMMEA6_IO_WR_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA6_IO_RD_COMBINE_FLUSH                                                                    0x3499
>+#define mmMMEA6_IO_RD_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA6_IO_WR_COMBINE_FLUSH                                                                    0x349a
>+#define mmMMEA6_IO_WR_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA6_IO_GROUP_BURST                                                                         0x349b
>+#define mmMMEA6_IO_GROUP_BURST_BASE_IDX                                                                1
>+#define mmMMEA6_IO_RD_PRI_AGE                                                                          0x349c
>+#define mmMMEA6_IO_RD_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA6_IO_WR_PRI_AGE                                                                          0x349d
>+#define mmMMEA6_IO_WR_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA6_IO_RD_PRI_QUEUING                                                                      0x349e
>+#define mmMMEA6_IO_RD_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA6_IO_WR_PRI_QUEUING                                                                      0x349f
>+#define mmMMEA6_IO_WR_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA6_IO_RD_PRI_FIXED                                                                        0x34a0
>+#define mmMMEA6_IO_RD_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA6_IO_WR_PRI_FIXED                                                                        0x34a1
>+#define mmMMEA6_IO_WR_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA6_IO_RD_PRI_URGENCY                                                                      0x34a2
>+#define mmMMEA6_IO_RD_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA6_IO_WR_PRI_URGENCY                                                                      0x34a3
>+#define mmMMEA6_IO_WR_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA6_IO_RD_PRI_URGENCY_MASKING                                                              0x34a4
>+#define mmMMEA6_IO_RD_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA6_IO_WR_PRI_URGENCY_MASKING                                                              0x34a5
>+#define mmMMEA6_IO_WR_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA6_IO_RD_PRI_QUANT_PRI1                                                                   0x34a6
>+#define mmMMEA6_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA6_IO_RD_PRI_QUANT_PRI2                                                                   0x34a7
>+#define mmMMEA6_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA6_IO_RD_PRI_QUANT_PRI3                                                                   0x34a8
>+#define mmMMEA6_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA6_IO_WR_PRI_QUANT_PRI1                                                                   0x34a9
>+#define mmMMEA6_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA6_IO_WR_PRI_QUANT_PRI2                                                                   0x34aa
>+#define mmMMEA6_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA6_IO_WR_PRI_QUANT_PRI3                                                                   0x34ab
>+#define mmMMEA6_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA6_SDP_ARB_DRAM                                                                           0x34ac
>+#define mmMMEA6_SDP_ARB_DRAM_BASE_IDX                                                                  1
>+#define mmMMEA6_SDP_ARB_GMI                                                                            0x34ad
>+#define mmMMEA6_SDP_ARB_GMI_BASE_IDX                                                                   1
>+#define mmMMEA6_SDP_ARB_FINAL                                                                          0x34ae
>+#define mmMMEA6_SDP_ARB_FINAL_BASE_IDX                                                                 1
>+#define mmMMEA6_SDP_DRAM_PRIORITY                                                                      0x34af
>+#define mmMMEA6_SDP_DRAM_PRIORITY_BASE_IDX                                                             1
>+#define mmMMEA6_SDP_GMI_PRIORITY                                                                       0x34b0
>+#define mmMMEA6_SDP_GMI_PRIORITY_BASE_IDX                                                              1
>+#define mmMMEA6_SDP_IO_PRIORITY                                                                        0x34b1
>+#define mmMMEA6_SDP_IO_PRIORITY_BASE_IDX                                                               1
>+#define mmMMEA6_SDP_CREDITS                                                                            0x34b2
>+#define mmMMEA6_SDP_CREDITS_BASE_IDX                                                                   1
>+#define mmMMEA6_SDP_TAG_RESERVE0                                                                       0x34b3
>+#define mmMMEA6_SDP_TAG_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA6_SDP_TAG_RESERVE1                                                                       0x34b4
>+#define mmMMEA6_SDP_TAG_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA6_SDP_VCC_RESERVE0                                                                       0x34b5
>+#define mmMMEA6_SDP_VCC_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA6_SDP_VCC_RESERVE1                                                                       0x34b6
>+#define mmMMEA6_SDP_VCC_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA6_SDP_VCD_RESERVE0                                                                       0x34b7
>+#define mmMMEA6_SDP_VCD_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA6_SDP_VCD_RESERVE1                                                                       0x34b8
>+#define mmMMEA6_SDP_VCD_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA6_SDP_REQ_CNTL                                                                           0x34b9
>+#define mmMMEA6_SDP_REQ_CNTL_BASE_IDX                                                                  1
>+#define mmMMEA6_MISC                                                                                   0x34ba
>+#define mmMMEA6_MISC_BASE_IDX                                                                          1
>+#define mmMMEA6_LATENCY_SAMPLING                                                                       0x34bb
>+#define mmMMEA6_LATENCY_SAMPLING_BASE_IDX                                                              1
>+#define mmMMEA6_PERFCOUNTER_LO                                                                         0x34bc
>+#define mmMMEA6_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmMMEA6_PERFCOUNTER_HI                                                                         0x34bd
>+#define mmMMEA6_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmMMEA6_PERFCOUNTER0_CFG                                                                       0x34be
>+#define mmMMEA6_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmMMEA6_PERFCOUNTER1_CFG                                                                       0x34bf
>+#define mmMMEA6_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmMMEA6_PERFCOUNTER_RSLT_CNTL                                                                  0x34c0
>+#define mmMMEA6_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmMMEA6_EDC_CNT                                                                                0x34c6
>+#define mmMMEA6_EDC_CNT_BASE_IDX                                                                       1
>+#define mmMMEA6_EDC_CNT2                                                                               0x34c7
>+#define mmMMEA6_EDC_CNT2_BASE_IDX                                                                      1
>+#define mmMMEA6_DSM_CNTL                                                                               0x34c8
>+#define mmMMEA6_DSM_CNTL_BASE_IDX                                                                      1
>+#define mmMMEA6_DSM_CNTLA                                                                              0x34c9
>+#define mmMMEA6_DSM_CNTLA_BASE_IDX                                                                     1
>+#define mmMMEA6_DSM_CNTLB                                                                              0x34ca
>+#define mmMMEA6_DSM_CNTLB_BASE_IDX                                                                     1
>+#define mmMMEA6_DSM_CNTL2                                                                              0x34cb
>+#define mmMMEA6_DSM_CNTL2_BASE_IDX                                                                     1
>+#define mmMMEA6_DSM_CNTL2A                                                                             0x34cc
>+#define mmMMEA6_DSM_CNTL2A_BASE_IDX                                                                    1
>+#define mmMMEA6_DSM_CNTL2B                                                                             0x34cd
>+#define mmMMEA6_DSM_CNTL2B_BASE_IDX                                                                    1
>+#define mmMMEA6_CGTT_CLK_CTRL                                                                          0x34cf
>+#define mmMMEA6_CGTT_CLK_CTRL_BASE_IDX                                                                 1
>+#define mmMMEA6_EDC_MODE                                                                               0x34d0
>+#define mmMMEA6_EDC_MODE_BASE_IDX                                                                      1
>+#define mmMMEA6_ERR_STATUS                                                                             0x34d1
>+#define mmMMEA6_ERR_STATUS_BASE_IDX                                                                    1
>+#define mmMMEA6_MISC2                                                                                  0x34d2
>+#define mmMMEA6_MISC2_BASE_IDX                                                                         1
>+#define mmMMEA6_ADDRDEC_SELECT                                                                         0x34d3
>+#define mmMMEA6_ADDRDEC_SELECT_BASE_IDX                                                                1
>+#define mmMMEA6_EDC_CNT3                                                                               0x34d4
>+#define mmMMEA6_EDC_CNT3_BASE_IDX                                                                      1
>+
>+
>+// addressBlock: mmhub_ea_mmeadec7
>+// base address: 0x75400
>+#define mmMMEA7_DRAM_RD_CLI2GRP_MAP0                                                                   0x3500
>+#define mmMMEA7_DRAM_RD_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA7_DRAM_RD_CLI2GRP_MAP1                                                                   0x3501
>+#define mmMMEA7_DRAM_RD_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA7_DRAM_WR_CLI2GRP_MAP0                                                                   0x3502
>+#define mmMMEA7_DRAM_WR_CLI2GRP_MAP0_BASE_IDX                                                          1
>+#define mmMMEA7_DRAM_WR_CLI2GRP_MAP1                                                                   0x3503
>+#define mmMMEA7_DRAM_WR_CLI2GRP_MAP1_BASE_IDX                                                          1
>+#define mmMMEA7_DRAM_RD_GRP2VC_MAP                                                                     0x3504
>+#define mmMMEA7_DRAM_RD_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA7_DRAM_WR_GRP2VC_MAP                                                                     0x3505
>+#define mmMMEA7_DRAM_WR_GRP2VC_MAP_BASE_IDX                                                            1
>+#define mmMMEA7_DRAM_RD_LAZY                                                                           0x3506
>+#define mmMMEA7_DRAM_RD_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA7_DRAM_WR_LAZY                                                                           0x3507
>+#define mmMMEA7_DRAM_WR_LAZY_BASE_IDX                                                                  1
>+#define mmMMEA7_DRAM_RD_CAM_CNTL                                                                       0x3508
>+#define mmMMEA7_DRAM_RD_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA7_DRAM_WR_CAM_CNTL                                                                       0x3509
>+#define mmMMEA7_DRAM_WR_CAM_CNTL_BASE_IDX                                                              1
>+#define mmMMEA7_DRAM_PAGE_BURST                                                                        0x350a
>+#define mmMMEA7_DRAM_PAGE_BURST_BASE_IDX                                                               1
>+#define mmMMEA7_DRAM_RD_PRI_AGE                                                                        0x350b
>+#define mmMMEA7_DRAM_RD_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA7_DRAM_WR_PRI_AGE                                                                        0x350c
>+#define mmMMEA7_DRAM_WR_PRI_AGE_BASE_IDX                                                               1
>+#define mmMMEA7_DRAM_RD_PRI_QUEUING                                                                    0x350d
>+#define mmMMEA7_DRAM_RD_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA7_DRAM_WR_PRI_QUEUING                                                                    0x350e
>+#define mmMMEA7_DRAM_WR_PRI_QUEUING_BASE_IDX                                                           1
>+#define mmMMEA7_DRAM_RD_PRI_FIXED                                                                      0x350f
>+#define mmMMEA7_DRAM_RD_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA7_DRAM_WR_PRI_FIXED                                                                      0x3510
>+#define mmMMEA7_DRAM_WR_PRI_FIXED_BASE_IDX                                                             1
>+#define mmMMEA7_DRAM_RD_PRI_URGENCY                                                                    0x3511
>+#define mmMMEA7_DRAM_RD_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA7_DRAM_WR_PRI_URGENCY                                                                    0x3512
>+#define mmMMEA7_DRAM_WR_PRI_URGENCY_BASE_IDX                                                           1
>+#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1                                                                 0x3513
>+#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2                                                                 0x3514
>+#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3                                                                 0x3515
>+#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1                                                                 0x3516
>+#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                        1
>+#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2                                                                 0x3517
>+#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                        1
>+#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3                                                                 0x3518
>+#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX                                                        1
>+#define mmMMEA7_GMI_RD_CLI2GRP_MAP0                                                                    0x3519
>+#define mmMMEA7_GMI_RD_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA7_GMI_RD_CLI2GRP_MAP1                                                                    0x351a
>+#define mmMMEA7_GMI_RD_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA7_GMI_WR_CLI2GRP_MAP0                                                                    0x351b
>+#define mmMMEA7_GMI_WR_CLI2GRP_MAP0_BASE_IDX                                                           1
>+#define mmMMEA7_GMI_WR_CLI2GRP_MAP1                                                                    0x351c
>+#define mmMMEA7_GMI_WR_CLI2GRP_MAP1_BASE_IDX                                                           1
>+#define mmMMEA7_GMI_RD_GRP2VC_MAP                                                                      0x351d
>+#define mmMMEA7_GMI_RD_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA7_GMI_WR_GRP2VC_MAP                                                                      0x351e
>+#define mmMMEA7_GMI_WR_GRP2VC_MAP_BASE_IDX                                                             1
>+#define mmMMEA7_GMI_RD_LAZY                                                                            0x351f
>+#define mmMMEA7_GMI_RD_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA7_GMI_WR_LAZY                                                                            0x3520
>+#define mmMMEA7_GMI_WR_LAZY_BASE_IDX                                                                   1
>+#define mmMMEA7_GMI_RD_CAM_CNTL                                                                        0x3521
>+#define mmMMEA7_GMI_RD_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA7_GMI_WR_CAM_CNTL                                                                        0x3522
>+#define mmMMEA7_GMI_WR_CAM_CNTL_BASE_IDX                                                               1
>+#define mmMMEA7_GMI_PAGE_BURST                                                                         0x3523
>+#define mmMMEA7_GMI_PAGE_BURST_BASE_IDX                                                                1
>+#define mmMMEA7_GMI_RD_PRI_AGE                                                                         0x3524
>+#define mmMMEA7_GMI_RD_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA7_GMI_WR_PRI_AGE                                                                         0x3525
>+#define mmMMEA7_GMI_WR_PRI_AGE_BASE_IDX                                                                1
>+#define mmMMEA7_GMI_RD_PRI_QUEUING                                                                     0x3526
>+#define mmMMEA7_GMI_RD_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA7_GMI_WR_PRI_QUEUING                                                                     0x3527
>+#define mmMMEA7_GMI_WR_PRI_QUEUING_BASE_IDX                                                            1
>+#define mmMMEA7_GMI_RD_PRI_FIXED                                                                       0x3528
>+#define mmMMEA7_GMI_RD_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA7_GMI_WR_PRI_FIXED                                                                       0x3529
>+#define mmMMEA7_GMI_WR_PRI_FIXED_BASE_IDX                                                              1
>+#define mmMMEA7_GMI_RD_PRI_URGENCY                                                                     0x352a
>+#define mmMMEA7_GMI_RD_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA7_GMI_WR_PRI_URGENCY                                                                     0x352b
>+#define mmMMEA7_GMI_WR_PRI_URGENCY_BASE_IDX                                                            1
>+#define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING                                                             0x352c
>+#define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING                                                             0x352d
>+#define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX                                                    1
>+#define mmMMEA7_GMI_RD_PRI_QUANT_PRI1                                                                  0x352e
>+#define mmMMEA7_GMI_RD_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA7_GMI_RD_PRI_QUANT_PRI2                                                                  0x352f
>+#define mmMMEA7_GMI_RD_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA7_GMI_RD_PRI_QUANT_PRI3                                                                  0x3530
>+#define mmMMEA7_GMI_RD_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA7_GMI_WR_PRI_QUANT_PRI1                                                                  0x3531
>+#define mmMMEA7_GMI_WR_PRI_QUANT_PRI1_BASE_IDX                                                         1
>+#define mmMMEA7_GMI_WR_PRI_QUANT_PRI2                                                                  0x3532
>+#define mmMMEA7_GMI_WR_PRI_QUANT_PRI2_BASE_IDX                                                         1
>+#define mmMMEA7_GMI_WR_PRI_QUANT_PRI3                                                                  0x3533
>+#define mmMMEA7_GMI_WR_PRI_QUANT_PRI3_BASE_IDX                                                         1
>+#define mmMMEA7_ADDRNORM_BASE_ADDR0                                                                    0x3534
>+#define mmMMEA7_ADDRNORM_BASE_ADDR0_BASE_IDX                                                           1
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR0                                                                   0x3535
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR0_BASE_IDX                                                          1
>+#define mmMMEA7_ADDRNORM_BASE_ADDR1                                                                    0x3536
>+#define mmMMEA7_ADDRNORM_BASE_ADDR1_BASE_IDX                                                           1
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR1                                                                   0x3537
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR1_BASE_IDX                                                          1
>+#define mmMMEA7_ADDRNORM_OFFSET_ADDR1                                                                  0x3538
>+#define mmMMEA7_ADDRNORM_OFFSET_ADDR1_BASE_IDX                                                         1
>+#define mmMMEA7_ADDRNORM_BASE_ADDR2                                                                    0x3539
>+#define mmMMEA7_ADDRNORM_BASE_ADDR2_BASE_IDX                                                           1
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR2                                                                   0x353a
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR2_BASE_IDX                                                          1
>+#define mmMMEA7_ADDRNORM_BASE_ADDR3                                                                    0x353b
>+#define mmMMEA7_ADDRNORM_BASE_ADDR3_BASE_IDX                                                           1
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR3                                                                   0x353c
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR3_BASE_IDX                                                          1
>+#define mmMMEA7_ADDRNORM_OFFSET_ADDR3                                                                  0x353d
>+#define mmMMEA7_ADDRNORM_OFFSET_ADDR3_BASE_IDX                                                         1
>+#define mmMMEA7_ADDRNORM_BASE_ADDR4                                                                    0x353e
>+#define mmMMEA7_ADDRNORM_BASE_ADDR4_BASE_IDX                                                           1
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR4                                                                   0x353f
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR4_BASE_IDX                                                          1
>+#define mmMMEA7_ADDRNORM_BASE_ADDR5                                                                    0x3540
>+#define mmMMEA7_ADDRNORM_BASE_ADDR5_BASE_IDX                                                           1
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR5                                                                   0x3541
>+#define mmMMEA7_ADDRNORM_LIMIT_ADDR5_BASE_IDX                                                          1
>+#define mmMMEA7_ADDRNORM_OFFSET_ADDR5                                                                  0x3542
>+#define mmMMEA7_ADDRNORM_OFFSET_ADDR5_BASE_IDX                                                         1
>+#define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL                                                                 0x3543
>+#define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRNORMGMI_HOLE_CNTL                                                                  0x3544
>+#define mmMMEA7_ADDRNORMGMI_HOLE_CNTL_BASE_IDX                                                         1
>+#define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG                                                           0x3545
>+#define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX                                                  1
>+#define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG                                                            0x3546
>+#define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX                                                   1
>+#define mmMMEA7_ADDRDEC_BANK_CFG                                                                       0x3547
>+#define mmMMEA7_ADDRDEC_BANK_CFG_BASE_IDX                                                              1
>+#define mmMMEA7_ADDRDEC_MISC_CFG                                                                       0x3548
>+#define mmMMEA7_ADDRDEC_MISC_CFG_BASE_IDX                                                              1
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0                                                            0x3549
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX                                                   1
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1                                                            0x354a
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX                                                   1
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2                                                            0x354b
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX                                                   1
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3                                                            0x354c
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX                                                   1
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4                                                            0x354d
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX                                                   1
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5                                                            0x354e
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX                                                   1
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC                                                               0x354f
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2                                                              0x3550
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0                                                              0x3551
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1                                                              0x3552
>+#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE                                                             0x3553
>+#define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0                                                             0x3554
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1                                                             0x3555
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2                                                             0x3556
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3                                                             0x3557
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4                                                             0x3558
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5                                                             0x3559
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC                                                                0x355a
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2                                                               0x355b
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0                                                               0x355c
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1                                                               0x355d
>+#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE                                                              0x355e
>+#define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0                                                                 0x355f
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1                                                                 0x3560
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2                                                                 0x3561
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3                                                                 0x3562
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0                                                              0x3563
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1                                                              0x3564
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2                                                              0x3565
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3                                                              0x3566
>+#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01                                                                0x3567
>+#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23                                                                0x3568
>+#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01                                                             0x3569
>+#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23                                                             0x356a
>+#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01                                                                 0x356b
>+#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23                                                                 0x356c
>+#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01                                                                 0x356d
>+#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23                                                                 0x356e
>+#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01                                                                0x356f
>+#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23                                                                0x3570
>+#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01                                                               0x3571
>+#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23                                                               0x3572
>+#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01                                                               0x3573
>+#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23                                                               0x3574
>+#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDEC0_RM_SEL_CS01                                                                   0x3575
>+#define mmMMEA7_ADDRDEC0_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA7_ADDRDEC0_RM_SEL_CS23                                                                   0x3576
>+#define mmMMEA7_ADDRDEC0_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01                                                                0x3577
>+#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23                                                                0x3578
>+#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0                                                                 0x3579
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1                                                                 0x357a
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2                                                                 0x357b
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3                                                                 0x357c
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0                                                              0x357d
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1                                                              0x357e
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2                                                              0x357f
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3                                                              0x3580
>+#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01                                                                0x3581
>+#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23                                                                0x3582
>+#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01                                                             0x3583
>+#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23                                                             0x3584
>+#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01                                                                 0x3585
>+#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23                                                                 0x3586
>+#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01                                                                 0x3587
>+#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23                                                                 0x3588
>+#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01                                                                0x3589
>+#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23                                                                0x358a
>+#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01                                                               0x358b
>+#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23                                                               0x358c
>+#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01                                                               0x358d
>+#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23                                                               0x358e
>+#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDEC1_RM_SEL_CS01                                                                   0x358f
>+#define mmMMEA7_ADDRDEC1_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA7_ADDRDEC1_RM_SEL_CS23                                                                   0x3590
>+#define mmMMEA7_ADDRDEC1_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01                                                                0x3591
>+#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23                                                                0x3592
>+#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0                                                                 0x3593
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1                                                                 0x3594
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2                                                                 0x3595
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3                                                                 0x3596
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0                                                              0x3597
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1                                                              0x3598
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2                                                              0x3599
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3                                                              0x359a
>+#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX                                                     1
>+#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01                                                                0x359b
>+#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23                                                                0x359c
>+#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01                                                             0x359d
>+#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23                                                             0x359e
>+#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX                                                    1
>+#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01                                                                 0x359f
>+#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23                                                                 0x35a0
>+#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01                                                                 0x35a1
>+#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23                                                                 0x35a2
>+#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX                                                        1
>+#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01                                                                0x35a3
>+#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23                                                                0x35a4
>+#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01                                                               0x35a5
>+#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23                                                               0x35a6
>+#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01                                                               0x35a7
>+#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23                                                               0x35a8
>+#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRDEC2_RM_SEL_CS01                                                                   0x35a9
>+#define mmMMEA7_ADDRDEC2_RM_SEL_CS01_BASE_IDX                                                          1
>+#define mmMMEA7_ADDRDEC2_RM_SEL_CS23                                                                   0x35aa
>+#define mmMMEA7_ADDRDEC2_RM_SEL_CS23_BASE_IDX                                                          1
>+#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01                                                                0x35ab
>+#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23                                                                0x35ac
>+#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX                                                       1
>+#define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL                                                               0x35ad
>+#define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX                                                      1
>+#define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL                                                                0x35ae
>+#define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX                                                       1
>+#define mmMMEA7_IO_RD_CLI2GRP_MAP0                                                                     0x35d5
>+#define mmMMEA7_IO_RD_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA7_IO_RD_CLI2GRP_MAP1                                                                     0x35d6
>+#define mmMMEA7_IO_RD_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA7_IO_WR_CLI2GRP_MAP0                                                                     0x35d7
>+#define mmMMEA7_IO_WR_CLI2GRP_MAP0_BASE_IDX                                                            1
>+#define mmMMEA7_IO_WR_CLI2GRP_MAP1                                                                     0x35d8
>+#define mmMMEA7_IO_WR_CLI2GRP_MAP1_BASE_IDX                                                            1
>+#define mmMMEA7_IO_RD_COMBINE_FLUSH                                                                    0x35d9
>+#define mmMMEA7_IO_RD_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA7_IO_WR_COMBINE_FLUSH                                                                    0x35da
>+#define mmMMEA7_IO_WR_COMBINE_FLUSH_BASE_IDX                                                           1
>+#define mmMMEA7_IO_GROUP_BURST                                                                         0x35db
>+#define mmMMEA7_IO_GROUP_BURST_BASE_IDX                                                                1
>+#define mmMMEA7_IO_RD_PRI_AGE                                                                          0x35dc
>+#define mmMMEA7_IO_RD_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA7_IO_WR_PRI_AGE                                                                          0x35dd
>+#define mmMMEA7_IO_WR_PRI_AGE_BASE_IDX                                                                 1
>+#define mmMMEA7_IO_RD_PRI_QUEUING                                                                      0x35de
>+#define mmMMEA7_IO_RD_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA7_IO_WR_PRI_QUEUING                                                                      0x35df
>+#define mmMMEA7_IO_WR_PRI_QUEUING_BASE_IDX                                                             1
>+#define mmMMEA7_IO_RD_PRI_FIXED                                                                        0x35e0
>+#define mmMMEA7_IO_RD_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA7_IO_WR_PRI_FIXED                                                                        0x35e1
>+#define mmMMEA7_IO_WR_PRI_FIXED_BASE_IDX                                                               1
>+#define mmMMEA7_IO_RD_PRI_URGENCY                                                                      0x35e2
>+#define mmMMEA7_IO_RD_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA7_IO_WR_PRI_URGENCY                                                                      0x35e3
>+#define mmMMEA7_IO_WR_PRI_URGENCY_BASE_IDX                                                             1
>+#define mmMMEA7_IO_RD_PRI_URGENCY_MASKING                                                              0x35e4
>+#define mmMMEA7_IO_RD_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA7_IO_WR_PRI_URGENCY_MASKING                                                              0x35e5
>+#define mmMMEA7_IO_WR_PRI_URGENCY_MASKING_BASE_IDX                                                     1
>+#define mmMMEA7_IO_RD_PRI_QUANT_PRI1                                                                   0x35e6
>+#define mmMMEA7_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA7_IO_RD_PRI_QUANT_PRI2                                                                   0x35e7
>+#define mmMMEA7_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA7_IO_RD_PRI_QUANT_PRI3                                                                   0x35e8
>+#define mmMMEA7_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA7_IO_WR_PRI_QUANT_PRI1                                                                   0x35e9
>+#define mmMMEA7_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                          1
>+#define mmMMEA7_IO_WR_PRI_QUANT_PRI2                                                                   0x35ea
>+#define mmMMEA7_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                          1
>+#define mmMMEA7_IO_WR_PRI_QUANT_PRI3                                                                   0x35eb
>+#define mmMMEA7_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                          1
>+#define mmMMEA7_SDP_ARB_DRAM                                                                           0x35ec
>+#define mmMMEA7_SDP_ARB_DRAM_BASE_IDX                                                                  1
>+#define mmMMEA7_SDP_ARB_GMI                                                                            0x35ed
>+#define mmMMEA7_SDP_ARB_GMI_BASE_IDX                                                                   1
>+#define mmMMEA7_SDP_ARB_FINAL                                                                          0x35ee
>+#define mmMMEA7_SDP_ARB_FINAL_BASE_IDX                                                                 1
>+#define mmMMEA7_SDP_DRAM_PRIORITY                                                                      0x35ef
>+#define mmMMEA7_SDP_DRAM_PRIORITY_BASE_IDX                                                             1
>+#define mmMMEA7_SDP_GMI_PRIORITY                                                                       0x35f0
>+#define mmMMEA7_SDP_GMI_PRIORITY_BASE_IDX                                                              1
>+#define mmMMEA7_SDP_IO_PRIORITY                                                                        0x35f1
>+#define mmMMEA7_SDP_IO_PRIORITY_BASE_IDX                                                               1
>+#define mmMMEA7_SDP_CREDITS                                                                            0x35f2
>+#define mmMMEA7_SDP_CREDITS_BASE_IDX                                                                   1
>+#define mmMMEA7_SDP_TAG_RESERVE0                                                                       0x35f3
>+#define mmMMEA7_SDP_TAG_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA7_SDP_TAG_RESERVE1                                                                       0x35f4
>+#define mmMMEA7_SDP_TAG_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA7_SDP_VCC_RESERVE0                                                                       0x35f5
>+#define mmMMEA7_SDP_VCC_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA7_SDP_VCC_RESERVE1                                                                       0x35f6
>+#define mmMMEA7_SDP_VCC_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA7_SDP_VCD_RESERVE0                                                                       0x35f7
>+#define mmMMEA7_SDP_VCD_RESERVE0_BASE_IDX                                                              1
>+#define mmMMEA7_SDP_VCD_RESERVE1                                                                       0x35f8
>+#define mmMMEA7_SDP_VCD_RESERVE1_BASE_IDX                                                              1
>+#define mmMMEA7_SDP_REQ_CNTL                                                                           0x35f9
>+#define mmMMEA7_SDP_REQ_CNTL_BASE_IDX                                                                  1
>+#define mmMMEA7_MISC                                                                                   0x35fa
>+#define mmMMEA7_MISC_BASE_IDX                                                                          1
>+#define mmMMEA7_LATENCY_SAMPLING                                                                       0x35fb
>+#define mmMMEA7_LATENCY_SAMPLING_BASE_IDX                                                              1
>+#define mmMMEA7_PERFCOUNTER_LO                                                                         0x35fc
>+#define mmMMEA7_PERFCOUNTER_LO_BASE_IDX                                                                1
>+#define mmMMEA7_PERFCOUNTER_HI                                                                         0x35fd
>+#define mmMMEA7_PERFCOUNTER_HI_BASE_IDX                                                                1
>+#define mmMMEA7_PERFCOUNTER0_CFG                                                                       0x35fe
>+#define mmMMEA7_PERFCOUNTER0_CFG_BASE_IDX                                                              1
>+#define mmMMEA7_PERFCOUNTER1_CFG                                                                       0x35ff
>+#define mmMMEA7_PERFCOUNTER1_CFG_BASE_IDX                                                              1
>+#define mmMMEA7_PERFCOUNTER_RSLT_CNTL                                                                  0x3600
>+#define mmMMEA7_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                         1
>+#define mmMMEA7_EDC_CNT                                                                                0x3606
>+#define mmMMEA7_EDC_CNT_BASE_IDX                                                                       1
>+#define mmMMEA7_EDC_CNT2                                                                               0x3607
>+#define mmMMEA7_EDC_CNT2_BASE_IDX                                                                      1
>+#define mmMMEA7_DSM_CNTL                                                                               0x3608
>+#define mmMMEA7_DSM_CNTL_BASE_IDX                                                                      1
>+#define mmMMEA7_DSM_CNTLA                                                                              0x3609
>+#define mmMMEA7_DSM_CNTLA_BASE_IDX                                                                     1
>+#define mmMMEA7_DSM_CNTLB                                                                              0x360a
>+#define mmMMEA7_DSM_CNTLB_BASE_IDX                                                                     1
>+#define mmMMEA7_DSM_CNTL2                                                                              0x360b
>+#define mmMMEA7_DSM_CNTL2_BASE_IDX                                                                     1
>+#define mmMMEA7_DSM_CNTL2A                                                                             0x360c
>+#define mmMMEA7_DSM_CNTL2A_BASE_IDX                                                                    1
>+#define mmMMEA7_DSM_CNTL2B                                                                             0x360d
>+#define mmMMEA7_DSM_CNTL2B_BASE_IDX                                                                    1
>+#define mmMMEA7_CGTT_CLK_CTRL                                                                          0x360f
>+#define mmMMEA7_CGTT_CLK_CTRL_BASE_IDX                                                                 1
>+#define mmMMEA7_EDC_MODE                                                                               0x3610
>+#define mmMMEA7_EDC_MODE_BASE_IDX                                                                      1
>+#define mmMMEA7_ERR_STATUS                                                                             0x3611
>+#define mmMMEA7_ERR_STATUS_BASE_IDX                                                                    1
>+#define mmMMEA7_MISC2                                                                                  0x3612
>+#define mmMMEA7_MISC2_BASE_IDX                                                                         1
>+#define mmMMEA7_ADDRDEC_SELECT                                                                         0x3613
>+#define mmMMEA7_ADDRDEC_SELECT_BASE_IDX                                                                1
>+#define mmMMEA7_EDC_CNT3                                                                               0x3614
>+#define mmMMEA7_EDC_CNT3_BASE_IDX                                                                      1
>+
>+
>+// addressBlock: mmhub_pctldec1
>+// base address: 0x76300
>+#define mmPCTL1_CTRL                                                                                   0x38c0
>+#define mmPCTL1_CTRL_BASE_IDX                                                                          1
>+#define mmPCTL1_MMHUB_DEEPSLEEP_IB                                                                     0x38c1
>+#define mmPCTL1_MMHUB_DEEPSLEEP_IB_BASE_IDX                                                            1
>+#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE                                                               0x38c2
>+#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX                                                      1
>+#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB                                                            0x38c3
>+#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX                                                   1
>+#define mmPCTL1_PG_IGNORE_DEEPSLEEP                                                                    0x38c4
>+#define mmPCTL1_PG_IGNORE_DEEPSLEEP_BASE_IDX                                                           1
>+#define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB                                                                 0x38c5
>+#define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX                                                        1
>+#define mmPCTL1_SLICE0_CFG_DAGB_BUSY                                                                   0x38c6
>+#define mmPCTL1_SLICE0_CFG_DAGB_BUSY_BASE_IDX                                                          1
>+#define mmPCTL1_SLICE0_CFG_DS_ALLOW                                                                    0x38c7
>+#define mmPCTL1_SLICE0_CFG_DS_ALLOW_BASE_IDX                                                           1
>+#define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB                                                                 0x38c8
>+#define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX                                                        1
>+#define mmPCTL1_SLICE1_CFG_DAGB_BUSY                                                                   0x38c9
>+#define mmPCTL1_SLICE1_CFG_DAGB_BUSY_BASE_IDX                                                          1
>+#define mmPCTL1_SLICE1_CFG_DS_ALLOW                                                                    0x38ca
>+#define mmPCTL1_SLICE1_CFG_DS_ALLOW_BASE_IDX                                                           1
>+#define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB                                                                 0x38cb
>+#define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX                                                        1
>+#define mmPCTL1_SLICE2_CFG_DAGB_BUSY                                                                   0x38cc
>+#define mmPCTL1_SLICE2_CFG_DAGB_BUSY_BASE_IDX                                                          1
>+#define mmPCTL1_SLICE2_CFG_DS_ALLOW                                                                    0x38cd
>+#define mmPCTL1_SLICE2_CFG_DS_ALLOW_BASE_IDX                                                           1
>+#define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB                                                                 0x38ce
>+#define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX                                                        1
>+#define mmPCTL1_SLICE3_CFG_DAGB_BUSY                                                                   0x38cf
>+#define mmPCTL1_SLICE3_CFG_DAGB_BUSY_BASE_IDX                                                          1
>+#define mmPCTL1_SLICE3_CFG_DS_ALLOW                                                                    0x38d0
>+#define mmPCTL1_SLICE3_CFG_DS_ALLOW_BASE_IDX                                                           1
>+#define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB                                                                 0x38d1
>+#define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX                                                        1
>+#define mmPCTL1_SLICE4_CFG_DAGB_BUSY                                                                   0x38d2
>+#define mmPCTL1_SLICE4_CFG_DAGB_BUSY_BASE_IDX                                                          1
>+#define mmPCTL1_SLICE4_CFG_DS_ALLOW                                                                    0x38d3
>+#define mmPCTL1_SLICE4_CFG_DS_ALLOW_BASE_IDX                                                           1
>+#define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB                                                                 0x38d4
>+#define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX                                                        1
>+#define mmPCTL1_UTCL2_MISC                                                                             0x38d5
>+#define mmPCTL1_UTCL2_MISC_BASE_IDX                                                                    1
>+#define mmPCTL1_SLICE0_MISC                                                                            0x38d6
>+#define mmPCTL1_SLICE0_MISC_BASE_IDX                                                                   1
>+#define mmPCTL1_SLICE1_MISC                                                                            0x38d7
>+#define mmPCTL1_SLICE1_MISC_BASE_IDX                                                                   1
>+#define mmPCTL1_SLICE2_MISC                                                                            0x38d8
>+#define mmPCTL1_SLICE2_MISC_BASE_IDX                                                                   1
>+#define mmPCTL1_SLICE3_MISC                                                                            0x38d9
>+#define mmPCTL1_SLICE3_MISC_BASE_IDX                                                                   1
>+#define mmPCTL1_SLICE4_MISC                                                                            0x38da
>+#define mmPCTL1_SLICE4_MISC_BASE_IDX                                                                   1
>+#define mmPCTL1_UTCL2_RENG_EXECUTE                                                                     0x38db
>+#define mmPCTL1_UTCL2_RENG_EXECUTE_BASE_IDX                                                            1
>+#define mmPCTL1_SLICE0_RENG_EXECUTE                                                                    0x38dc
>+#define mmPCTL1_SLICE0_RENG_EXECUTE_BASE_IDX                                                           1
>+#define mmPCTL1_SLICE1_RENG_EXECUTE                                                                    0x38dd
>+#define mmPCTL1_SLICE1_RENG_EXECUTE_BASE_IDX                                                           1
>+#define mmPCTL1_SLICE2_RENG_EXECUTE                                                                    0x38de
>+#define mmPCTL1_SLICE2_RENG_EXECUTE_BASE_IDX                                                           1
>+#define mmPCTL1_SLICE3_RENG_EXECUTE                                                                    0x38df
>+#define mmPCTL1_SLICE3_RENG_EXECUTE_BASE_IDX                                                           1
>+#define mmPCTL1_SLICE4_RENG_EXECUTE                                                                    0x38e0
>+#define mmPCTL1_SLICE4_RENG_EXECUTE_BASE_IDX                                                           1
>+#define mmPCTL1_UTCL2_RENG_RAM_INDEX                                                                   0x38e1
>+#define mmPCTL1_UTCL2_RENG_RAM_INDEX_BASE_IDX                                                          1
>+#define mmPCTL1_UTCL2_RENG_RAM_DATA                                                                    0x38e2
>+#define mmPCTL1_UTCL2_RENG_RAM_DATA_BASE_IDX                                                           1
>+#define mmPCTL1_SLICE0_RENG_RAM_INDEX                                                                  0x38e3
>+#define mmPCTL1_SLICE0_RENG_RAM_INDEX_BASE_IDX                                                         1
>+#define mmPCTL1_SLICE0_RENG_RAM_DATA                                                                   0x38e4
>+#define mmPCTL1_SLICE0_RENG_RAM_DATA_BASE_IDX                                                          1
>+#define mmPCTL1_SLICE1_RENG_RAM_INDEX                                                                  0x38e5
>+#define mmPCTL1_SLICE1_RENG_RAM_INDEX_BASE_IDX                                                         1
>+#define mmPCTL1_SLICE1_RENG_RAM_DATA                                                                   0x38e6
>+#define mmPCTL1_SLICE1_RENG_RAM_DATA_BASE_IDX                                                          1
>+#define mmPCTL1_SLICE2_RENG_RAM_INDEX                                                                  0x38e7
>+#define mmPCTL1_SLICE2_RENG_RAM_INDEX_BASE_IDX                                                         1
>+#define mmPCTL1_SLICE2_RENG_RAM_DATA                                                                   0x38e8
>+#define mmPCTL1_SLICE2_RENG_RAM_DATA_BASE_IDX                                                          1
>+#define mmPCTL1_SLICE3_RENG_RAM_INDEX                                                                  0x38e9
>+#define mmPCTL1_SLICE3_RENG_RAM_INDEX_BASE_IDX                                                         1
>+#define mmPCTL1_SLICE3_RENG_RAM_DATA                                                                   0x38ea
>+#define mmPCTL1_SLICE3_RENG_RAM_DATA_BASE_IDX                                                          1
>+#define mmPCTL1_SLICE4_RENG_RAM_INDEX                                                                  0x38eb
>+#define mmPCTL1_SLICE4_RENG_RAM_INDEX_BASE_IDX                                                         1
>+#define mmPCTL1_SLICE4_RENG_RAM_DATA                                                                   0x38ec
>+#define mmPCTL1_SLICE4_RENG_RAM_DATA_BASE_IDX                                                          1
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0                                                      0x38ed
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                             1
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1                                                      0x38ee
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                             1
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2                                                      0x38ef
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                             1
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3                                                      0x38f0
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                             1
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4                                                      0x38f1
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                             1
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0                                                   0x38f2
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                          1
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1                                                   0x38f3
>+#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                          1
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0                                                     0x38f4
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                            1
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1                                                     0x38f5
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                            1
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2                                                     0x38f6
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                            1
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3                                                     0x38f7
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                            1
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4                                                     0x38f8
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                            1
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0                                                  0x38f9
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                         1
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1                                                  0x38fa
>+#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                         1
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0                                                     0x38fb
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                            1
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1                                                     0x38fc
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                            1
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2                                                     0x38fd
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                            1
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3                                                     0x38fe
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                            1
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4                                                     0x38ff
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                            1
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0                                                  0x3900
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                         1
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1                                                  0x3901
>+#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                         1
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0                                                     0x3902
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                            1
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1                                                     0x3903
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                            1
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2                                                     0x3904
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                            1
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3                                                     0x3905
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                            1
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4                                                     0x3906
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                            1
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0                                                  0x3907
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                         1
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1                                                  0x3908
>+#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                         1
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0                                                     0x3909
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                            1
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1                                                     0x390a
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                            1
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2                                                     0x390b
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                            1
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3                                                     0x390c
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                            1
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4                                                     0x390d
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                            1
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0                                                  0x390e
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                         1
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1                                                  0x390f
>+#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                         1
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0                                                     0x3910
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX                                            1
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1                                                     0x3911
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX                                            1
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2                                                     0x3912
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX                                            1
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3                                                     0x3913
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX                                            1
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4                                                     0x3914
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX                                            1
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0                                                  0x3915
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX                                         1
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1                                                  0x3916
>+#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX                                         1
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1dec:1
>+// base address: 0x76500
>+#define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS                                                               0x3948
>+#define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS_BASE_IDX                                                      1
>+#define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS                                                               0x3949
>+#define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS_BASE_IDX                                                      1
>+#define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS                                                               0x394a
>+#define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS_BASE_IDX                                                      1
>+#define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS                                                               0x394b
>+#define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS_BASE_IDX                                                      1
>+#define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS                                                               0x394c
>+#define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS_BASE_IDX                                                      1
>+#define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS                                                               0x394d
>+#define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS_BASE_IDX                                                      1
>+#define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS                                                               0x394e
>+#define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS_BASE_IDX                                                      1
>+#define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS                                                               0x394f
>+#define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS_BASE_IDX                                                      1
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1pldec:1
>+// base address: 0x76580
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG                                                         0x3960
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX                                                1
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG                                                         0x3961
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX                                                1
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG                                                         0x3962
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX                                                1
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG                                                         0x3963
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX                                                1
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL                                                    0x3964
>+#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                           1
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1prdec:1
>+// base address: 0x765c0
>+#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO                                                           0x3970
>+#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX                                                  1
>+#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI                                                           0x3971
>+#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX                                                  1
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2dec:1
>+// base address: 0x76600
>+#define mmATCL2_1_ATC_L2_CNTL                                                                          0x3980
>+#define mmATCL2_1_ATC_L2_CNTL_BASE_IDX                                                                 1
>+#define mmATCL2_1_ATC_L2_CNTL2                                                                         0x3981
>+#define mmATCL2_1_ATC_L2_CNTL2_BASE_IDX                                                                1
>+#define mmATCL2_1_ATC_L2_CACHE_DATA0                                                                   0x3984
>+#define mmATCL2_1_ATC_L2_CACHE_DATA0_BASE_IDX                                                          1
>+#define mmATCL2_1_ATC_L2_CACHE_DATA1                                                                   0x3985
>+#define mmATCL2_1_ATC_L2_CACHE_DATA1_BASE_IDX                                                          1
>+#define mmATCL2_1_ATC_L2_CACHE_DATA2                                                                   0x3986
>+#define mmATCL2_1_ATC_L2_CACHE_DATA2_BASE_IDX                                                          1
>+#define mmATCL2_1_ATC_L2_CNTL3                                                                         0x3987
>+#define mmATCL2_1_ATC_L2_CNTL3_BASE_IDX                                                                1
>+#define mmATCL2_1_ATC_L2_STATUS                                                                        0x3988
>+#define mmATCL2_1_ATC_L2_STATUS_BASE_IDX                                                               1
>+#define mmATCL2_1_ATC_L2_STATUS2                                                                       0x3989
>+#define mmATCL2_1_ATC_L2_STATUS2_BASE_IDX                                                              1
>+#define mmATCL2_1_ATC_L2_STATUS3                                                                       0x398a
>+#define mmATCL2_1_ATC_L2_STATUS3_BASE_IDX                                                              1
>+#define mmATCL2_1_ATC_L2_MISC_CG                                                                       0x398b
>+#define mmATCL2_1_ATC_L2_MISC_CG_BASE_IDX                                                              1
>+#define mmATCL2_1_ATC_L2_MEM_POWER_LS                                                                  0x398c
>+#define mmATCL2_1_ATC_L2_MEM_POWER_LS_BASE_IDX                                                         1
>+#define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL                                                                 0x398d
>+#define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL_BASE_IDX                                                        1
>+#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX                                                            0x398e
>+#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX                                                   1
>+#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX                                                            0x398f
>+#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX                                                   1
>+#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL                                                             0x3990
>+#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX                                                    1
>+#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL                                                             0x3991
>+#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX                                                    1
>+#define mmATCL2_1_ATC_L2_CNTL4                                                                         0x3992
>+#define mmATCL2_1_ATC_L2_CNTL4_BASE_IDX                                                                1
>+#define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES                                                           0x3993
>+#define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                  1
>+
>+
>+// addressBlock: mmhub_utcl2_vml2pfdec:1
>+// base address: 0x76700
>+#define mmVML2PF1_VM_L2_CNTL                                                                           0x39c0
>+#define mmVML2PF1_VM_L2_CNTL_BASE_IDX                                                                  1
>+#define mmVML2PF1_VM_L2_CNTL2                                                                          0x39c1
>+#define mmVML2PF1_VM_L2_CNTL2_BASE_IDX                                                                 1
>+#define mmVML2PF1_VM_L2_CNTL3                                                                          0x39c2
>+#define mmVML2PF1_VM_L2_CNTL3_BASE_IDX                                                                 1
>+#define mmVML2PF1_VM_L2_STATUS                                                                         0x39c3
>+#define mmVML2PF1_VM_L2_STATUS_BASE_IDX                                                                1
>+#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL                                                             0x39c4
>+#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX                                                    1
>+#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32                                                        0x39c5
>+#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX                                               1
>+#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32                                                        0x39c6
>+#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX                                               1
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL                                                          0x39c7
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL_BASE_IDX                                                 1
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2                                                         0x39c8
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX                                                1
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3                                                      0x39c9
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX                                             1
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4                                                      0x39ca
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX                                             1
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS                                                        0x39cb
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS_BASE_IDX                                               1
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32                                                     0x39cc
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX                                            1
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32                                                     0x39cd
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX                                            1
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32                                             0x39ce
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX                                    1
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32                                             0x39cf
>+#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX                                    1
>+#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32                                       0x39d1
>+#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX                              1
>+#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32                                       0x39d2
>+#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX                              1
>+#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32                                      0x39d3
>+#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX                             1
>+#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32                                      0x39d4
>+#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX                             1
>+#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32                                          0x39d5
>+#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX                                 1
>+#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32                                          0x39d6
>+#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX                                 1
>+#define mmVML2PF1_VM_L2_CNTL4                                                                          0x39d7
>+#define mmVML2PF1_VM_L2_CNTL4_BASE_IDX                                                                 1
>+#define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES                                                            0x39d8
>+#define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                   1
>+#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID                                                       0x39d9
>+#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX                                              1
>+#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2                                                      0x39da
>+#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX                                             1
>+#define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL                                                              0x39db
>+#define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL_BASE_IDX                                                     1
>+#define mmVML2PF1_VM_L2_CGTT_CLK_CTRL                                                                  0x39de
>+#define mmVML2PF1_VM_L2_CGTT_CLK_CTRL_BASE_IDX                                                         1
>+
>+
>+// addressBlock: mmhub_utcl2_vml2vcdec:1
>+// base address: 0x76800
>+#define mmVML2VC1_VM_CONTEXT0_CNTL                                                                     0x3a00
>+#define mmVML2VC1_VM_CONTEXT0_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC1_VM_CONTEXT1_CNTL                                                                     0x3a01
>+#define mmVML2VC1_VM_CONTEXT1_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC1_VM_CONTEXT2_CNTL                                                                     0x3a02
>+#define mmVML2VC1_VM_CONTEXT2_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC1_VM_CONTEXT3_CNTL                                                                     0x3a03
>+#define mmVML2VC1_VM_CONTEXT3_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC1_VM_CONTEXT4_CNTL                                                                     0x3a04
>+#define mmVML2VC1_VM_CONTEXT4_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC1_VM_CONTEXT5_CNTL                                                                     0x3a05
>+#define mmVML2VC1_VM_CONTEXT5_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC1_VM_CONTEXT6_CNTL                                                                     0x3a06
>+#define mmVML2VC1_VM_CONTEXT6_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC1_VM_CONTEXT7_CNTL                                                                     0x3a07
>+#define mmVML2VC1_VM_CONTEXT7_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC1_VM_CONTEXT8_CNTL                                                                     0x3a08
>+#define mmVML2VC1_VM_CONTEXT8_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC1_VM_CONTEXT9_CNTL                                                                     0x3a09
>+#define mmVML2VC1_VM_CONTEXT9_CNTL_BASE_IDX                                                            1
>+#define mmVML2VC1_VM_CONTEXT10_CNTL                                                                    0x3a0a
>+#define mmVML2VC1_VM_CONTEXT10_CNTL_BASE_IDX                                                           1
>+#define mmVML2VC1_VM_CONTEXT11_CNTL                                                                    0x3a0b
>+#define mmVML2VC1_VM_CONTEXT11_CNTL_BASE_IDX                                                           1
>+#define mmVML2VC1_VM_CONTEXT12_CNTL                                                                    0x3a0c
>+#define mmVML2VC1_VM_CONTEXT12_CNTL_BASE_IDX                                                           1
>+#define mmVML2VC1_VM_CONTEXT13_CNTL                                                                    0x3a0d
>+#define mmVML2VC1_VM_CONTEXT13_CNTL_BASE_IDX                                                           1
>+#define mmVML2VC1_VM_CONTEXT14_CNTL                                                                    0x3a0e
>+#define mmVML2VC1_VM_CONTEXT14_CNTL_BASE_IDX                                                           1
>+#define mmVML2VC1_VM_CONTEXT15_CNTL                                                                    0x3a0f
>+#define mmVML2VC1_VM_CONTEXT15_CNTL_BASE_IDX                                                           1
>+#define mmVML2VC1_VM_CONTEXTS_DISABLE                                                                  0x3a10
>+#define mmVML2VC1_VM_CONTEXTS_DISABLE_BASE_IDX                                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_SEM                                                               0x3a11
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_SEM_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_SEM                                                               0x3a12
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_SEM_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_SEM                                                               0x3a13
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_SEM_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_SEM                                                               0x3a14
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_SEM_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_SEM                                                               0x3a15
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_SEM_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_SEM                                                               0x3a16
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_SEM_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_SEM                                                               0x3a17
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_SEM_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_SEM                                                               0x3a18
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_SEM_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_SEM                                                               0x3a19
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_SEM_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_SEM                                                               0x3a1a
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_SEM_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_SEM                                                              0x3a1b
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_SEM_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_SEM                                                              0x3a1c
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_SEM_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_SEM                                                              0x3a1d
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_SEM_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_SEM                                                              0x3a1e
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_SEM_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_SEM                                                              0x3a1f
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_SEM_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_SEM                                                              0x3a20
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_SEM_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_SEM                                                              0x3a21
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_SEM_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_SEM                                                              0x3a22
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_SEM_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_REQ                                                               0x3a23
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_REQ_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_REQ                                                               0x3a24
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_REQ_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_REQ                                                               0x3a25
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_REQ_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_REQ                                                               0x3a26
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_REQ_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_REQ                                                               0x3a27
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_REQ_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_REQ                                                               0x3a28
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_REQ_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_REQ                                                               0x3a29
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_REQ_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_REQ                                                               0x3a2a
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_REQ_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_REQ                                                               0x3a2b
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_REQ_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_REQ                                                               0x3a2c
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_REQ_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_REQ                                                              0x3a2d
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_REQ_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_REQ                                                              0x3a2e
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_REQ_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_REQ                                                              0x3a2f
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_REQ_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_REQ                                                              0x3a30
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_REQ_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_REQ                                                              0x3a31
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_REQ_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_REQ                                                              0x3a32
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_REQ_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_REQ                                                              0x3a33
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_REQ_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_REQ                                                              0x3a34
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_REQ_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_ACK                                                               0x3a35
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_ACK_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_ACK                                                               0x3a36
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_ACK_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_ACK                                                               0x3a37
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_ACK_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_ACK                                                               0x3a38
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_ACK_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_ACK                                                               0x3a39
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_ACK_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_ACK                                                               0x3a3a
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_ACK_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_ACK                                                               0x3a3b
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_ACK_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_ACK                                                               0x3a3c
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_ACK_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_ACK                                                               0x3a3d
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_ACK_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_ACK                                                               0x3a3e
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_ACK_BASE_IDX                                                      1
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_ACK                                                              0x3a3f
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_ACK_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_ACK                                                              0x3a40
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_ACK_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_ACK                                                              0x3a41
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_ACK_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_ACK                                                              0x3a42
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_ACK_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_ACK                                                              0x3a43
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_ACK_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_ACK                                                              0x3a44
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_ACK_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_ACK                                                              0x3a45
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_ACK_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_ACK                                                              0x3a46
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_ACK_BASE_IDX                                                     1
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32                                                   0x3a47
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32                                                   0x3a48
>+#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32                                                   0x3a49
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32                                                   0x3a4a
>+#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32                                                   0x3a4b
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32                                                   0x3a4c
>+#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32                                                   0x3a4d
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32                                                   0x3a4e
>+#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32                                                   0x3a4f
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32                                                   0x3a50
>+#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32                                                   0x3a51
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32                                                   0x3a52
>+#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32                                                   0x3a53
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32                                                   0x3a54
>+#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32                                                   0x3a55
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32                                                   0x3a56
>+#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32                                                   0x3a57
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32                                                   0x3a58
>+#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32                                                   0x3a59
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32                                                   0x3a5a
>+#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX                                          1
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32                                                  0x3a5b
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32                                                  0x3a5c
>+#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32                                                  0x3a5d
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32                                                  0x3a5e
>+#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32                                                  0x3a5f
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32                                                  0x3a60
>+#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32                                                  0x3a61
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32                                                  0x3a62
>+#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32                                                  0x3a63
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32                                                  0x3a64
>+#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32                                                  0x3a65
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32                                                  0x3a66
>+#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32                                                  0x3a67
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32                                                  0x3a68
>+#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32                                                  0x3a69
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32                                                  0x3a6a
>+#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX                                         1
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                0x3a6b
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                0x3a6c
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                0x3a6d
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                0x3a6e
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                0x3a6f
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                0x3a70
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                0x3a71
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                0x3a72
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                0x3a73
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                0x3a74
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                0x3a75
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                0x3a76
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                0x3a77
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                0x3a78
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                0x3a79
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                0x3a7a
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                0x3a7b
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                0x3a7c
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                0x3a7d
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                0x3a7e
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                               0x3a7f
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                               0x3a80
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                               0x3a81
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                               0x3a82
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                               0x3a83
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                               0x3a84
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                               0x3a85
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                               0x3a86
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                               0x3a87
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                               0x3a88
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                               0x3a89
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                               0x3a8a
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                               0x3a8b
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                               0x3a8c
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                               0x3a8d
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                               0x3a8e
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                               0x3a8f
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                               0x3a90
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                               0x3a91
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                               0x3a92
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                               0x3a93
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                               0x3a94
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                               0x3a95
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                               0x3a96
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                               0x3a97
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                               0x3a98
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                               0x3a99
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                               0x3a9a
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                               0x3a9b
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                               0x3a9c
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                               0x3a9d
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                               0x3a9e
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                      1
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                              0x3a9f
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                              0x3aa0
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                              0x3aa1
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                              0x3aa2
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                              0x3aa3
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                              0x3aa4
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                              0x3aa5
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                              0x3aa6
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                              0x3aa7
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                              0x3aa8
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                              0x3aa9
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                     1
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                              0x3aaa
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                     1
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                 0x3aab
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                 0x3aac
>+#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                 0x3aad
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                 0x3aae
>+#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                 0x3aaf
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                 0x3ab0
>+#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                 0x3ab1
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                 0x3ab2
>+#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                 0x3ab3
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                 0x3ab4
>+#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                 0x3ab5
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                 0x3ab6
>+#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                 0x3ab7
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                 0x3ab8
>+#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                 0x3ab9
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                 0x3aba
>+#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                 0x3abb
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                 0x3abc
>+#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                 0x3abd
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                 0x3abe
>+#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                        1
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                0x3abf
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                0x3ac0
>+#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                0x3ac1
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                0x3ac2
>+#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                0x3ac3
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                0x3ac4
>+#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                0x3ac5
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                0x3ac6
>+#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                0x3ac7
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                0x3ac8
>+#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                0x3ac9
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                       1
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                0x3aca
>+#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                       1
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedpfdec:1
>+// base address: 0x76b90
>+#define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE                                                                0x3ae4
>+#define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE_BASE_IDX                                                       1
>+#define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT                                                               0x3ae5
>+#define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT_BASE_IDX                                                      1
>+#define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL                                                                0x3ae6
>+#define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL_BASE_IDX                                                       1
>+#define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB                                                                 0x3ae7
>+#define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB_BASE_IDX                                                        1
>+#define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1                                                       0x3ae8
>+#define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX                                              1
>+#define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2                                                      0x3ae9
>+#define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX                                             1
>+#define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2                                                      0x3aea
>+#define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX                                             1
>+#define mmVMSHAREDPF1_MC_VM_FB_OFFSET                                                                  0x3aeb
>+#define mmVMSHAREDPF1_MC_VM_FB_OFFSET_BASE_IDX                                                         1
>+#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB                                           0x3aec
>+#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX                                  1
>+#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB                                           0x3aed
>+#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX                                  1
>+#define mmVMSHAREDPF1_MC_VM_STEERING                                                                   0x3aee
>+#define mmVMSHAREDPF1_MC_VM_STEERING_BASE_IDX                                                          1
>+#define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ                                                         0x3aef
>+#define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ_BASE_IDX                                                1
>+#define mmVMSHAREDPF1_MC_MEM_POWER_LS                                                                  0x3af0
>+#define mmVMSHAREDPF1_MC_MEM_POWER_LS_BASE_IDX                                                         1
>+#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START                                               0x3af1
>+#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX                                      1
>+#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END                                                 0x3af2
>+#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX                                        1
>+#define mmVMSHAREDPF1_MC_VM_APT_CNTL                                                                   0x3af3
>+#define mmVMSHAREDPF1_MC_VM_APT_CNTL_BASE_IDX                                                          1
>+#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START                                                    0x3af4
>+#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                           1
>+#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END                                                      0x3af5
>+#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                             1
>+#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                0x3af6
>+#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                       1
>+#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL                                                              0x3af7
>+#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL_BASE_IDX                                                     1
>+#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE                                                              0x3af8
>+#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE_BASE_IDX                                                     1
>+#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL                                                        0x3af9
>+#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX                                               1
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedvcdec:1
>+// base address: 0x76c00
>+#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE                                                           0x3b00
>+#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE_BASE_IDX                                                  1
>+#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP                                                            0x3b01
>+#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP_BASE_IDX                                                   1
>+#define mmVMSHAREDVC1_MC_VM_AGP_TOP                                                                    0x3b02
>+#define mmVMSHAREDVC1_MC_VM_AGP_TOP_BASE_IDX                                                           1
>+#define mmVMSHAREDVC1_MC_VM_AGP_BOT                                                                    0x3b03
>+#define mmVMSHAREDVC1_MC_VM_AGP_BOT_BASE_IDX                                                           1
>+#define mmVMSHAREDVC1_MC_VM_AGP_BASE                                                                   0x3b04
>+#define mmVMSHAREDVC1_MC_VM_AGP_BASE_BASE_IDX                                                          1
>+#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR                                                   0x3b05
>+#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                          1
>+#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR                                                  0x3b06
>+#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                         1
>+#define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL                                                             0x3b07
>+#define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL_BASE_IDX                                                    1
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedhvdec:1
>+// base address: 0x76c80
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0                                                         0x3b20
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX                                                1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1                                                         0x3b21
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX                                                1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2                                                         0x3b22
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX                                                1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3                                                         0x3b23
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX                                                1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4                                                         0x3b24
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX                                                1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5                                                         0x3b25
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX                                                1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6                                                         0x3b26
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX                                                1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7                                                         0x3b27
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX                                                1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8                                                         0x3b28
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX                                                1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9                                                         0x3b29
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX                                                1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10                                                        0x3b2a
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX                                               1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11                                                        0x3b2b
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX                                               1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12                                                        0x3b2c
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX                                               1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13                                                        0x3b2d
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX                                               1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14                                                        0x3b2e
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX                                               1
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15                                                        0x3b2f
>+#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX                                               1
>+#define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1                                                            0x3b30
>+#define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0                                                             0x3b31
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0_BASE_IDX                                                    1
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1                                                             0x3b32
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1_BASE_IDX                                                    1
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2                                                             0x3b33
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2_BASE_IDX                                                    1
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3                                                             0x3b34
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3_BASE_IDX                                                    1
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0                                                             0x3b35
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0_BASE_IDX                                                    1
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1                                                             0x3b36
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1_BASE_IDX                                                    1
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2                                                             0x3b37
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2_BASE_IDX                                                    1
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3                                                             0x3b38
>+#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3_BASE_IDX                                                    1
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0                                                            0x3b39
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1                                                            0x3b3a
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2                                                            0x3b3b
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3                                                            0x3b3c
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0                                                            0x3b3d
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1                                                            0x3b3e
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2                                                            0x3b3f
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3                                                            0x3b40
>+#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0                                                              0x3b41
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0_BASE_IDX                                                     1
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1                                                              0x3b42
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1_BASE_IDX                                                     1
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2                                                              0x3b43
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2_BASE_IDX                                                     1
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3                                                              0x3b44
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3_BASE_IDX                                                     1
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0                                                              0x3b45
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0_BASE_IDX                                                     1
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1                                                              0x3b46
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1_BASE_IDX                                                     1
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2                                                              0x3b47
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2_BASE_IDX                                                     1
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3                                                              0x3b48
>+#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3_BASE_IDX                                                     1
>+#define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER                                                        0x3b49
>+#define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER_BASE_IDX                                               1
>+#define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER                               0x3b4a
>+#define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX                      1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL                                                                 0x3b4b
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_BASE_IDX                                                        1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0                                                            0x3b4c
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1                                                            0x3b4d
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2                                                            0x3b4e
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3                                                            0x3b4f
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4                                                            0x3b50
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5                                                            0x3b51
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6                                                            0x3b52
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7                                                            0x3b53
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8                                                            0x3b54
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9                                                            0x3b55
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9_BASE_IDX                                                   1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10                                                           0x3b56
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10_BASE_IDX                                                  1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11                                                           0x3b57
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11_BASE_IDX                                                  1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12                                                           0x3b58
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12_BASE_IDX                                                  1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13                                                           0x3b59
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13_BASE_IDX                                                  1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14                                                           0x3b5a
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14_BASE_IDX                                                  1
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15                                                           0x3b5b
>+#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15_BASE_IDX                                                  1
>+#define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL                                                              0x3b5c
>+#define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL_BASE_IDX                                                     1
>+#define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID                                                          0x3b5d
>+#define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID_BASE_IDX                                                 1
>+#define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE                                                         0x3b5e
>+#define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX                                                1
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2pfcntrdec:1
>+// base address: 0x76dc0
>+#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO                                                           0x3b70
>+#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO_BASE_IDX                                                  1
>+#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI                                                           0x3b71
>+#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI_BASE_IDX                                                  1
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2pfcntldec:1
>+// base address: 0x76dd0
>+#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG                                                         0x3b74
>+#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX                                                1
>+#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG                                                         0x3b75
>+#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX                                                1
>+#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL                                                    0x3b76
>+#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                           1
>+
>+
>+// addressBlock: mmhub_utcl2_vml2pldec:1
>+// base address: 0x76e00
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG                                                            0x3b80
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX                                                   1
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG                                                            0x3b81
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX                                                   1
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG                                                            0x3b82
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX                                                   1
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG                                                            0x3b83
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX                                                   1
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG                                                            0x3b84
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX                                                   1
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG                                                            0x3b85
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX                                                   1
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG                                                            0x3b86
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX                                                   1
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG                                                            0x3b87
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX                                                   1
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL                                                       0x3b88
>+#define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                              1
>+
>+
>+// addressBlock: mmhub_utcl2_vml2prdec:1
>+// base address: 0x76e40
>+#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO                                                              0x3b90
>+#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO_BASE_IDX                                                     1
>+#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI                                                              0x3b91
>+#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI_BASE_IDX                                                     1
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h	2019-08-31 15:01:11.908736173 -0500
>@@ -0,0 +1,44884 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _mmhub_9_4_1_SH_MASK_HEADER
>+#define _mmhub_9_4_1_SH_MASK_HEADER
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec0
>+//DAGB0_RDCLI0
>+#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_RDCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_RDCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_RDCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_RDCLI1
>+#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_RDCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_RDCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_RDCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_RDCLI2
>+#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_RDCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_RDCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_RDCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_RDCLI3
>+#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_RDCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_RDCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_RDCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_RDCLI4
>+#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_RDCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_RDCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_RDCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_RDCLI5
>+#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_RDCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_RDCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_RDCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_RDCLI6
>+#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_RDCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_RDCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_RDCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_RDCLI7
>+#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_RDCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_RDCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_RDCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_RDCLI8
>+#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_RDCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_RDCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_RDCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_RDCLI9
>+#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_RDCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_RDCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_RDCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_RDCLI10
>+#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB0_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB0_RDCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB0_RDCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB0_RDCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB0_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB0_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB0_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB0_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB0_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB0_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB0_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB0_RDCLI11
>+#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB0_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB0_RDCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB0_RDCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB0_RDCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB0_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB0_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB0_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB0_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB0_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB0_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB0_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB0_RDCLI12
>+#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB0_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB0_RDCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB0_RDCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB0_RDCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB0_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB0_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB0_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB0_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB0_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB0_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB0_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB0_RDCLI13
>+#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB0_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB0_RDCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB0_RDCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB0_RDCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB0_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB0_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB0_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB0_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB0_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB0_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB0_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB0_RDCLI14
>+#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB0_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB0_RDCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB0_RDCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB0_RDCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB0_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB0_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB0_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB0_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB0_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB0_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB0_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB0_RDCLI15
>+#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB0_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB0_RDCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB0_RDCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB0_RDCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB0_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB0_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB0_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB0_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB0_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB0_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB0_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB0_RD_CNTL
>+#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB0_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB0_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB0_RD_GMI_CNTL
>+#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB0_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB0_RD_ADDR_DAGB
>+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB0_RD_OUTPUT_DAGB_MAX_BURST
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB0_RD_CGTT_CLK_CTRL
>+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB0_ATCVM_RD_CGTT_CLK_CTRL
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB0_RD_ADDR_DAGB_MAX_BURST0
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB0_RD_ADDR_DAGB_MAX_BURST1
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB0_RD_VC0_CNTL
>+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_RD_VC1_CNTL
>+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_RD_VC2_CNTL
>+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_RD_VC3_CNTL
>+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_RD_VC4_CNTL
>+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_RD_VC5_CNTL
>+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_RD_VC6_CNTL
>+#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_RD_VC7_CNTL
>+#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_RD_CNTL_MISC
>+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB0_RD_TLB_CREDIT
>+#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB0_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB0_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB0_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB0_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB0_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB0_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB0_RDCLI_ASK_PENDING
>+#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB0_RDCLI_GO_PENDING
>+#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB0_RDCLI_GBLSEND_PENDING
>+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB0_RDCLI_TLB_PENDING
>+#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB0_RDCLI_OARB_PENDING
>+#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB0_RDCLI_OSD_PENDING
>+#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB0_WRCLI0
>+#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_WRCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_WRCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_WRCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_WRCLI1
>+#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_WRCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_WRCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_WRCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_WRCLI2
>+#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_WRCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_WRCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_WRCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_WRCLI3
>+#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_WRCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_WRCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_WRCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_WRCLI4
>+#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_WRCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_WRCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_WRCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_WRCLI5
>+#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_WRCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_WRCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_WRCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_WRCLI6
>+#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_WRCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_WRCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_WRCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_WRCLI7
>+#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_WRCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_WRCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_WRCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_WRCLI8
>+#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_WRCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_WRCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_WRCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_WRCLI9
>+#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB0_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB0_WRCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB0_WRCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB0_WRCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB0_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB0_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB0_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB0_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB0_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB0_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB0_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB0_WRCLI10
>+#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB0_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB0_WRCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB0_WRCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB0_WRCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB0_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB0_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB0_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB0_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB0_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB0_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB0_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB0_WRCLI11
>+#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB0_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB0_WRCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB0_WRCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB0_WRCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB0_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB0_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB0_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB0_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB0_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB0_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB0_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB0_WRCLI12
>+#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB0_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB0_WRCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB0_WRCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB0_WRCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB0_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB0_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB0_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB0_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB0_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB0_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB0_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB0_WRCLI13
>+#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB0_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB0_WRCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB0_WRCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB0_WRCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB0_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB0_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB0_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB0_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB0_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB0_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB0_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB0_WRCLI14
>+#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB0_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB0_WRCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB0_WRCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB0_WRCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB0_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB0_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB0_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB0_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB0_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB0_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB0_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB0_WRCLI15
>+#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB0_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB0_WRCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB0_WRCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB0_WRCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB0_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB0_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB0_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB0_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB0_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB0_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB0_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB0_WR_CNTL
>+#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB0_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB0_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB0_WR_GMI_CNTL
>+#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB0_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB0_WR_ADDR_DAGB
>+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB0_WR_OUTPUT_DAGB_MAX_BURST
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB0_WR_CGTT_CLK_CTRL
>+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB0_ATCVM_WR_CGTT_CLK_CTRL
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB0_WR_ADDR_DAGB_MAX_BURST0
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB0_WR_ADDR_DAGB_MAX_BURST1
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB0_WR_DATA_DAGB
>+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB0_WR_DATA_DAGB_MAX_BURST0
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB0_WR_DATA_DAGB_MAX_BURST1
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB0_WR_VC0_CNTL
>+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_WR_VC1_CNTL
>+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_WR_VC2_CNTL
>+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_WR_VC3_CNTL
>+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_WR_VC4_CNTL
>+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_WR_VC5_CNTL
>+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_WR_VC6_CNTL
>+#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_WR_VC7_CNTL
>+#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB0_WR_CNTL_MISC
>+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB0_WR_TLB_CREDIT
>+#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB0_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB0_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB0_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB0_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB0_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB0_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB0_WR_DATA_CREDIT
>+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
>+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
>+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
>+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
>+#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
>+#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
>+#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
>+#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
>+//DAGB0_WR_MISC_CREDIT
>+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
>+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
>+#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
>+#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
>+#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
>+#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
>+#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
>+#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
>+//DAGB0_WRCLI_ASK_PENDING
>+#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB0_WRCLI_GO_PENDING
>+#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB0_WRCLI_GBLSEND_PENDING
>+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB0_WRCLI_TLB_PENDING
>+#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB0_WRCLI_OARB_PENDING
>+#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB0_WRCLI_OSD_PENDING
>+#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB0_WRCLI_DBUS_ASK_PENDING
>+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
>+#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
>+//DAGB0_WRCLI_DBUS_GO_PENDING
>+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB0_DAGB_DLY
>+#define DAGB0_DAGB_DLY__DLY__SHIFT                                                                            0x0
>+#define DAGB0_DAGB_DLY__CLI__SHIFT                                                                            0x8
>+#define DAGB0_DAGB_DLY__POS__SHIFT                                                                            0x10
>+#define DAGB0_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
>+#define DAGB0_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
>+#define DAGB0_DAGB_DLY__POS_MASK                                                                              0x000F0000L
>+//DAGB0_CNTL_MISC
>+#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
>+#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
>+#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
>+#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
>+#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
>+#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
>+#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
>+#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
>+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
>+#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
>+#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
>+#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
>+#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
>+#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
>+#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
>+#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
>+#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
>+#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
>+#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
>+#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
>+//DAGB0_CNTL_MISC2
>+#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
>+#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
>+#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
>+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
>+#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
>+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
>+#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
>+#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
>+#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
>+#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
>+#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
>+#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
>+#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
>+#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
>+#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
>+#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
>+#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
>+#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
>+#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
>+#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
>+#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
>+#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
>+#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
>+#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
>+#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
>+#define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
>+//DAGB0_FIFO_EMPTY
>+#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
>+#define DAGB0_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
>+//DAGB0_FIFO_FULL
>+#define DAGB0_FIFO_FULL__FULL__SHIFT                                                                          0x0
>+#define DAGB0_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
>+//DAGB0_WR_CREDITS_FULL
>+#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB0_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
>+//DAGB0_RD_CREDITS_FULL
>+#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB0_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
>+//DAGB0_PERFCOUNTER_LO
>+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//DAGB0_PERFCOUNTER_HI
>+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//DAGB0_PERFCOUNTER0_CFG
>+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB0_PERFCOUNTER1_CFG
>+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB0_PERFCOUNTER2_CFG
>+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB0_PERFCOUNTER_RSLT_CNTL
>+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//DAGB0_RESERVE0
>+#define DAGB0_RESERVE0__RESERVE__SHIFT                                                                        0x0
>+#define DAGB0_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB0_RESERVE1
>+#define DAGB0_RESERVE1__RESERVE__SHIFT                                                                        0x0
>+#define DAGB0_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB0_RESERVE2
>+#define DAGB0_RESERVE2__RESERVE__SHIFT                                                                        0x0
>+#define DAGB0_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB0_RESERVE3
>+#define DAGB0_RESERVE3__RESERVE__SHIFT                                                                        0x0
>+#define DAGB0_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB0_RESERVE4
>+#define DAGB0_RESERVE4__RESERVE__SHIFT                                                                        0x0
>+#define DAGB0_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB0_RESERVE5
>+#define DAGB0_RESERVE5__RESERVE__SHIFT                                                                        0x0
>+#define DAGB0_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB0_RESERVE6
>+#define DAGB0_RESERVE6__RESERVE__SHIFT                                                                        0x0
>+#define DAGB0_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB0_RESERVE7
>+#define DAGB0_RESERVE7__RESERVE__SHIFT                                                                        0x0
>+#define DAGB0_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB0_RESERVE8
>+#define DAGB0_RESERVE8__RESERVE__SHIFT                                                                        0x0
>+#define DAGB0_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB0_RESERVE9
>+#define DAGB0_RESERVE9__RESERVE__SHIFT                                                                        0x0
>+#define DAGB0_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB0_RESERVE10
>+#define DAGB0_RESERVE10__RESERVE__SHIFT                                                                       0x0
>+#define DAGB0_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB0_RESERVE11
>+#define DAGB0_RESERVE11__RESERVE__SHIFT                                                                       0x0
>+#define DAGB0_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB0_RESERVE12
>+#define DAGB0_RESERVE12__RESERVE__SHIFT                                                                       0x0
>+#define DAGB0_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB0_RESERVE13
>+#define DAGB0_RESERVE13__RESERVE__SHIFT                                                                       0x0
>+#define DAGB0_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec1
>+//DAGB1_RDCLI0
>+#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_RDCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_RDCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_RDCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_RDCLI1
>+#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_RDCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_RDCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_RDCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_RDCLI2
>+#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_RDCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_RDCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_RDCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_RDCLI3
>+#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_RDCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_RDCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_RDCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_RDCLI4
>+#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_RDCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_RDCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_RDCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_RDCLI5
>+#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_RDCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_RDCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_RDCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_RDCLI6
>+#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_RDCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_RDCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_RDCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_RDCLI7
>+#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_RDCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_RDCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_RDCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_RDCLI8
>+#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_RDCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_RDCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_RDCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_RDCLI9
>+#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_RDCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_RDCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_RDCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_RDCLI10
>+#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB1_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB1_RDCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB1_RDCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB1_RDCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB1_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB1_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB1_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB1_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB1_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB1_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB1_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB1_RDCLI11
>+#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB1_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB1_RDCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB1_RDCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB1_RDCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB1_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB1_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB1_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB1_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB1_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB1_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB1_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB1_RDCLI12
>+#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB1_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB1_RDCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB1_RDCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB1_RDCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB1_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB1_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB1_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB1_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB1_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB1_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB1_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB1_RDCLI13
>+#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB1_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB1_RDCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB1_RDCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB1_RDCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB1_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB1_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB1_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB1_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB1_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB1_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB1_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB1_RDCLI14
>+#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB1_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB1_RDCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB1_RDCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB1_RDCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB1_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB1_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB1_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB1_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB1_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB1_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB1_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB1_RDCLI15
>+#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB1_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB1_RDCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB1_RDCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB1_RDCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB1_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB1_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB1_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB1_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB1_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB1_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB1_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB1_RD_CNTL
>+#define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB1_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB1_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB1_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB1_RD_GMI_CNTL
>+#define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB1_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB1_RD_ADDR_DAGB
>+#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB1_RD_OUTPUT_DAGB_MAX_BURST
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB1_RD_CGTT_CLK_CTRL
>+#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB1_L1TLB_RD_CGTT_CLK_CTRL
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB1_ATCVM_RD_CGTT_CLK_CTRL
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB1_RD_ADDR_DAGB_MAX_BURST0
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB1_RD_ADDR_DAGB_MAX_BURST1
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB1_RD_VC0_CNTL
>+#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_RD_VC1_CNTL
>+#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_RD_VC2_CNTL
>+#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_RD_VC3_CNTL
>+#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_RD_VC4_CNTL
>+#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_RD_VC5_CNTL
>+#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_RD_VC6_CNTL
>+#define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_RD_VC7_CNTL
>+#define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_RD_CNTL_MISC
>+#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB1_RD_TLB_CREDIT
>+#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB1_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB1_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB1_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB1_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB1_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB1_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB1_RDCLI_ASK_PENDING
>+#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB1_RDCLI_GO_PENDING
>+#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB1_RDCLI_GBLSEND_PENDING
>+#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB1_RDCLI_TLB_PENDING
>+#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB1_RDCLI_OARB_PENDING
>+#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB1_RDCLI_OSD_PENDING
>+#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB1_WRCLI0
>+#define DAGB1_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_WRCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_WRCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_WRCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_WRCLI1
>+#define DAGB1_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_WRCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_WRCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_WRCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_WRCLI2
>+#define DAGB1_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_WRCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_WRCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_WRCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_WRCLI3
>+#define DAGB1_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_WRCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_WRCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_WRCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_WRCLI4
>+#define DAGB1_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_WRCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_WRCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_WRCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_WRCLI5
>+#define DAGB1_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_WRCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_WRCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_WRCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_WRCLI6
>+#define DAGB1_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_WRCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_WRCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_WRCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_WRCLI7
>+#define DAGB1_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_WRCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_WRCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_WRCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_WRCLI8
>+#define DAGB1_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_WRCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_WRCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_WRCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_WRCLI9
>+#define DAGB1_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB1_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB1_WRCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB1_WRCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB1_WRCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB1_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB1_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB1_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB1_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB1_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB1_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB1_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB1_WRCLI10
>+#define DAGB1_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB1_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB1_WRCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB1_WRCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB1_WRCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB1_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB1_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB1_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB1_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB1_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB1_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB1_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB1_WRCLI11
>+#define DAGB1_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB1_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB1_WRCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB1_WRCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB1_WRCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB1_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB1_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB1_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB1_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB1_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB1_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB1_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB1_WRCLI12
>+#define DAGB1_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB1_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB1_WRCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB1_WRCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB1_WRCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB1_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB1_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB1_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB1_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB1_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB1_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB1_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB1_WRCLI13
>+#define DAGB1_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB1_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB1_WRCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB1_WRCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB1_WRCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB1_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB1_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB1_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB1_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB1_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB1_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB1_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB1_WRCLI14
>+#define DAGB1_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB1_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB1_WRCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB1_WRCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB1_WRCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB1_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB1_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB1_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB1_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB1_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB1_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB1_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB1_WRCLI15
>+#define DAGB1_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB1_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB1_WRCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB1_WRCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB1_WRCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB1_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB1_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB1_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB1_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB1_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB1_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB1_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB1_WR_CNTL
>+#define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB1_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB1_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB1_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB1_WR_GMI_CNTL
>+#define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB1_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB1_WR_ADDR_DAGB
>+#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB1_WR_OUTPUT_DAGB_MAX_BURST
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB1_WR_CGTT_CLK_CTRL
>+#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB1_L1TLB_WR_CGTT_CLK_CTRL
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB1_ATCVM_WR_CGTT_CLK_CTRL
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB1_WR_ADDR_DAGB_MAX_BURST0
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB1_WR_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB1_WR_ADDR_DAGB_MAX_BURST1
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB1_WR_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB1_WR_DATA_DAGB
>+#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB1_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB1_WR_DATA_DAGB_MAX_BURST0
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB1_WR_DATA_DAGB_LAZY_TIMER0
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB1_WR_DATA_DAGB_MAX_BURST1
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB1_WR_DATA_DAGB_LAZY_TIMER1
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB1_WR_VC0_CNTL
>+#define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_WR_VC1_CNTL
>+#define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_WR_VC2_CNTL
>+#define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_WR_VC3_CNTL
>+#define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_WR_VC4_CNTL
>+#define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_WR_VC5_CNTL
>+#define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_WR_VC6_CNTL
>+#define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_WR_VC7_CNTL
>+#define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB1_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB1_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB1_WR_CNTL_MISC
>+#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB1_WR_TLB_CREDIT
>+#define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB1_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB1_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB1_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB1_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB1_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB1_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB1_WR_DATA_CREDIT
>+#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
>+#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
>+#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
>+#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
>+#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
>+#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
>+#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
>+#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
>+//DAGB1_WR_MISC_CREDIT
>+#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
>+#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
>+#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
>+#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
>+#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
>+#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
>+#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
>+#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
>+//DAGB1_WRCLI_ASK_PENDING
>+#define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB1_WRCLI_GO_PENDING
>+#define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB1_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB1_WRCLI_GBLSEND_PENDING
>+#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB1_WRCLI_TLB_PENDING
>+#define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB1_WRCLI_OARB_PENDING
>+#define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB1_WRCLI_OSD_PENDING
>+#define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB1_WRCLI_DBUS_ASK_PENDING
>+#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
>+#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
>+//DAGB1_WRCLI_DBUS_GO_PENDING
>+#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB1_DAGB_DLY
>+#define DAGB1_DAGB_DLY__DLY__SHIFT                                                                            0x0
>+#define DAGB1_DAGB_DLY__CLI__SHIFT                                                                            0x8
>+#define DAGB1_DAGB_DLY__POS__SHIFT                                                                            0x10
>+#define DAGB1_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
>+#define DAGB1_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
>+#define DAGB1_DAGB_DLY__POS_MASK                                                                              0x000F0000L
>+//DAGB1_CNTL_MISC
>+#define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
>+#define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
>+#define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
>+#define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
>+#define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
>+#define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
>+#define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
>+#define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
>+#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
>+#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
>+#define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
>+#define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
>+#define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
>+#define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
>+#define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
>+#define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
>+#define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
>+#define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
>+#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
>+#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
>+//DAGB1_CNTL_MISC2
>+#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
>+#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
>+#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
>+#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
>+#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
>+#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
>+#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
>+#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
>+#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
>+#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
>+#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
>+#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
>+#define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
>+#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
>+#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
>+#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
>+#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
>+#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
>+#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
>+#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
>+#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
>+#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
>+#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
>+#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
>+#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
>+#define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
>+//DAGB1_FIFO_EMPTY
>+#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
>+#define DAGB1_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
>+//DAGB1_FIFO_FULL
>+#define DAGB1_FIFO_FULL__FULL__SHIFT                                                                          0x0
>+#define DAGB1_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
>+//DAGB1_WR_CREDITS_FULL
>+#define DAGB1_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB1_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
>+//DAGB1_RD_CREDITS_FULL
>+#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB1_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
>+//DAGB1_PERFCOUNTER_LO
>+#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//DAGB1_PERFCOUNTER_HI
>+#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//DAGB1_PERFCOUNTER0_CFG
>+#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB1_PERFCOUNTER1_CFG
>+#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB1_PERFCOUNTER2_CFG
>+#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB1_PERFCOUNTER_RSLT_CNTL
>+#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//DAGB1_RESERVE0
>+#define DAGB1_RESERVE0__RESERVE__SHIFT                                                                        0x0
>+#define DAGB1_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB1_RESERVE1
>+#define DAGB1_RESERVE1__RESERVE__SHIFT                                                                        0x0
>+#define DAGB1_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB1_RESERVE2
>+#define DAGB1_RESERVE2__RESERVE__SHIFT                                                                        0x0
>+#define DAGB1_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB1_RESERVE3
>+#define DAGB1_RESERVE3__RESERVE__SHIFT                                                                        0x0
>+#define DAGB1_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB1_RESERVE4
>+#define DAGB1_RESERVE4__RESERVE__SHIFT                                                                        0x0
>+#define DAGB1_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB1_RESERVE5
>+#define DAGB1_RESERVE5__RESERVE__SHIFT                                                                        0x0
>+#define DAGB1_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB1_RESERVE6
>+#define DAGB1_RESERVE6__RESERVE__SHIFT                                                                        0x0
>+#define DAGB1_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB1_RESERVE7
>+#define DAGB1_RESERVE7__RESERVE__SHIFT                                                                        0x0
>+#define DAGB1_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB1_RESERVE8
>+#define DAGB1_RESERVE8__RESERVE__SHIFT                                                                        0x0
>+#define DAGB1_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB1_RESERVE9
>+#define DAGB1_RESERVE9__RESERVE__SHIFT                                                                        0x0
>+#define DAGB1_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB1_RESERVE10
>+#define DAGB1_RESERVE10__RESERVE__SHIFT                                                                       0x0
>+#define DAGB1_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB1_RESERVE11
>+#define DAGB1_RESERVE11__RESERVE__SHIFT                                                                       0x0
>+#define DAGB1_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB1_RESERVE12
>+#define DAGB1_RESERVE12__RESERVE__SHIFT                                                                       0x0
>+#define DAGB1_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB1_RESERVE13
>+#define DAGB1_RESERVE13__RESERVE__SHIFT                                                                       0x0
>+#define DAGB1_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec2
>+//DAGB2_RDCLI0
>+#define DAGB2_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_RDCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_RDCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_RDCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_RDCLI1
>+#define DAGB2_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_RDCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_RDCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_RDCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_RDCLI2
>+#define DAGB2_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_RDCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_RDCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_RDCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_RDCLI3
>+#define DAGB2_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_RDCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_RDCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_RDCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_RDCLI4
>+#define DAGB2_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_RDCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_RDCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_RDCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_RDCLI5
>+#define DAGB2_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_RDCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_RDCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_RDCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_RDCLI6
>+#define DAGB2_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_RDCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_RDCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_RDCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_RDCLI7
>+#define DAGB2_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_RDCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_RDCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_RDCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_RDCLI8
>+#define DAGB2_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_RDCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_RDCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_RDCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_RDCLI9
>+#define DAGB2_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_RDCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_RDCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_RDCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_RDCLI10
>+#define DAGB2_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB2_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB2_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB2_RDCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB2_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB2_RDCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB2_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB2_RDCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB2_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB2_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB2_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB2_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB2_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB2_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB2_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB2_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB2_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB2_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB2_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB2_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB2_RDCLI11
>+#define DAGB2_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB2_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB2_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB2_RDCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB2_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB2_RDCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB2_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB2_RDCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB2_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB2_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB2_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB2_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB2_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB2_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB2_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB2_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB2_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB2_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB2_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB2_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB2_RDCLI12
>+#define DAGB2_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB2_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB2_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB2_RDCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB2_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB2_RDCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB2_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB2_RDCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB2_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB2_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB2_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB2_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB2_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB2_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB2_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB2_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB2_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB2_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB2_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB2_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB2_RDCLI13
>+#define DAGB2_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB2_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB2_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB2_RDCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB2_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB2_RDCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB2_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB2_RDCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB2_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB2_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB2_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB2_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB2_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB2_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB2_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB2_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB2_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB2_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB2_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB2_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB2_RDCLI14
>+#define DAGB2_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB2_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB2_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB2_RDCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB2_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB2_RDCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB2_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB2_RDCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB2_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB2_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB2_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB2_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB2_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB2_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB2_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB2_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB2_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB2_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB2_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB2_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB2_RDCLI15
>+#define DAGB2_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB2_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB2_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB2_RDCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB2_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB2_RDCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB2_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB2_RDCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB2_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB2_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB2_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB2_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB2_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB2_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB2_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB2_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB2_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB2_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB2_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB2_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB2_RD_CNTL
>+#define DAGB2_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB2_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB2_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB2_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB2_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB2_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB2_RD_GMI_CNTL
>+#define DAGB2_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB2_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB2_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB2_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB2_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB2_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB2_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB2_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB2_RD_ADDR_DAGB
>+#define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB2_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB2_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB2_RD_OUTPUT_DAGB_MAX_BURST
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB2_RD_CGTT_CLK_CTRL
>+#define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB2_L1TLB_RD_CGTT_CLK_CTRL
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB2_ATCVM_RD_CGTT_CLK_CTRL
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB2_RD_ADDR_DAGB_MAX_BURST0
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB2_RD_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB2_RD_ADDR_DAGB_MAX_BURST1
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB2_RD_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB2_RD_VC0_CNTL
>+#define DAGB2_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_RD_VC1_CNTL
>+#define DAGB2_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_RD_VC2_CNTL
>+#define DAGB2_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_RD_VC3_CNTL
>+#define DAGB2_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_RD_VC4_CNTL
>+#define DAGB2_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_RD_VC5_CNTL
>+#define DAGB2_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_RD_VC6_CNTL
>+#define DAGB2_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_RD_VC7_CNTL
>+#define DAGB2_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_RD_CNTL_MISC
>+#define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB2_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB2_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB2_RD_TLB_CREDIT
>+#define DAGB2_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB2_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB2_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB2_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB2_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB2_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB2_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB2_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB2_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB2_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB2_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB2_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB2_RDCLI_ASK_PENDING
>+#define DAGB2_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB2_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB2_RDCLI_GO_PENDING
>+#define DAGB2_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB2_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB2_RDCLI_GBLSEND_PENDING
>+#define DAGB2_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB2_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB2_RDCLI_TLB_PENDING
>+#define DAGB2_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB2_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB2_RDCLI_OARB_PENDING
>+#define DAGB2_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB2_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB2_RDCLI_OSD_PENDING
>+#define DAGB2_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB2_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB2_WRCLI0
>+#define DAGB2_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_WRCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_WRCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_WRCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_WRCLI1
>+#define DAGB2_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_WRCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_WRCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_WRCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_WRCLI2
>+#define DAGB2_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_WRCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_WRCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_WRCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_WRCLI3
>+#define DAGB2_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_WRCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_WRCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_WRCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_WRCLI4
>+#define DAGB2_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_WRCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_WRCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_WRCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_WRCLI5
>+#define DAGB2_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_WRCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_WRCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_WRCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_WRCLI6
>+#define DAGB2_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_WRCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_WRCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_WRCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_WRCLI7
>+#define DAGB2_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_WRCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_WRCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_WRCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_WRCLI8
>+#define DAGB2_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_WRCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_WRCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_WRCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_WRCLI9
>+#define DAGB2_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB2_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB2_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB2_WRCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB2_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB2_WRCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB2_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB2_WRCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB2_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB2_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB2_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB2_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB2_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB2_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB2_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB2_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB2_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB2_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB2_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB2_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB2_WRCLI10
>+#define DAGB2_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB2_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB2_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB2_WRCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB2_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB2_WRCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB2_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB2_WRCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB2_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB2_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB2_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB2_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB2_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB2_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB2_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB2_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB2_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB2_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB2_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB2_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB2_WRCLI11
>+#define DAGB2_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB2_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB2_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB2_WRCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB2_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB2_WRCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB2_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB2_WRCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB2_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB2_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB2_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB2_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB2_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB2_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB2_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB2_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB2_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB2_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB2_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB2_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB2_WRCLI12
>+#define DAGB2_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB2_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB2_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB2_WRCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB2_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB2_WRCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB2_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB2_WRCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB2_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB2_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB2_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB2_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB2_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB2_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB2_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB2_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB2_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB2_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB2_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB2_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB2_WRCLI13
>+#define DAGB2_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB2_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB2_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB2_WRCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB2_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB2_WRCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB2_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB2_WRCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB2_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB2_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB2_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB2_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB2_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB2_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB2_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB2_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB2_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB2_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB2_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB2_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB2_WRCLI14
>+#define DAGB2_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB2_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB2_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB2_WRCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB2_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB2_WRCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB2_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB2_WRCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB2_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB2_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB2_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB2_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB2_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB2_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB2_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB2_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB2_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB2_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB2_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB2_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB2_WRCLI15
>+#define DAGB2_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB2_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB2_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB2_WRCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB2_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB2_WRCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB2_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB2_WRCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB2_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB2_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB2_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB2_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB2_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB2_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB2_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB2_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB2_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB2_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB2_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB2_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB2_WR_CNTL
>+#define DAGB2_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB2_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB2_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB2_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB2_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB2_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB2_WR_GMI_CNTL
>+#define DAGB2_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB2_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB2_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB2_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB2_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB2_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB2_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB2_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB2_WR_ADDR_DAGB
>+#define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB2_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB2_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB2_WR_OUTPUT_DAGB_MAX_BURST
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB2_WR_CGTT_CLK_CTRL
>+#define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB2_L1TLB_WR_CGTT_CLK_CTRL
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB2_ATCVM_WR_CGTT_CLK_CTRL
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB2_WR_ADDR_DAGB_MAX_BURST0
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB2_WR_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB2_WR_ADDR_DAGB_MAX_BURST1
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB2_WR_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB2_WR_DATA_DAGB
>+#define DAGB2_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB2_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB2_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB2_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB2_WR_DATA_DAGB_MAX_BURST0
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB2_WR_DATA_DAGB_LAZY_TIMER0
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB2_WR_DATA_DAGB_MAX_BURST1
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB2_WR_DATA_DAGB_LAZY_TIMER1
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB2_WR_VC0_CNTL
>+#define DAGB2_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_WR_VC1_CNTL
>+#define DAGB2_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_WR_VC2_CNTL
>+#define DAGB2_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_WR_VC3_CNTL
>+#define DAGB2_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_WR_VC4_CNTL
>+#define DAGB2_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_WR_VC5_CNTL
>+#define DAGB2_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_WR_VC6_CNTL
>+#define DAGB2_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_WR_VC7_CNTL
>+#define DAGB2_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB2_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB2_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB2_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB2_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB2_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB2_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB2_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB2_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB2_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB2_WR_CNTL_MISC
>+#define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB2_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB2_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB2_WR_TLB_CREDIT
>+#define DAGB2_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB2_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB2_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB2_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB2_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB2_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB2_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB2_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB2_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB2_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB2_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB2_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB2_WR_DATA_CREDIT
>+#define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
>+#define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
>+#define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
>+#define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
>+#define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
>+#define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
>+#define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
>+#define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
>+//DAGB2_WR_MISC_CREDIT
>+#define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
>+#define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
>+#define DAGB2_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
>+#define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
>+#define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
>+#define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
>+#define DAGB2_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
>+#define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
>+//DAGB2_WRCLI_ASK_PENDING
>+#define DAGB2_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB2_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB2_WRCLI_GO_PENDING
>+#define DAGB2_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB2_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB2_WRCLI_GBLSEND_PENDING
>+#define DAGB2_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB2_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB2_WRCLI_TLB_PENDING
>+#define DAGB2_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB2_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB2_WRCLI_OARB_PENDING
>+#define DAGB2_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB2_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB2_WRCLI_OSD_PENDING
>+#define DAGB2_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB2_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB2_WRCLI_DBUS_ASK_PENDING
>+#define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
>+#define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
>+//DAGB2_WRCLI_DBUS_GO_PENDING
>+#define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB2_DAGB_DLY
>+#define DAGB2_DAGB_DLY__DLY__SHIFT                                                                            0x0
>+#define DAGB2_DAGB_DLY__CLI__SHIFT                                                                            0x8
>+#define DAGB2_DAGB_DLY__POS__SHIFT                                                                            0x10
>+#define DAGB2_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
>+#define DAGB2_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
>+#define DAGB2_DAGB_DLY__POS_MASK                                                                              0x000F0000L
>+//DAGB2_CNTL_MISC
>+#define DAGB2_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
>+#define DAGB2_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
>+#define DAGB2_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
>+#define DAGB2_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
>+#define DAGB2_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
>+#define DAGB2_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
>+#define DAGB2_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
>+#define DAGB2_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
>+#define DAGB2_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
>+#define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
>+#define DAGB2_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
>+#define DAGB2_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
>+#define DAGB2_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
>+#define DAGB2_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
>+#define DAGB2_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
>+#define DAGB2_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
>+#define DAGB2_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
>+#define DAGB2_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
>+#define DAGB2_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
>+#define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
>+//DAGB2_CNTL_MISC2
>+#define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
>+#define DAGB2_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
>+#define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
>+#define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
>+#define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
>+#define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
>+#define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
>+#define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
>+#define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
>+#define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
>+#define DAGB2_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
>+#define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
>+#define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
>+#define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
>+#define DAGB2_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
>+#define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
>+#define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
>+#define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
>+#define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
>+#define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
>+#define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
>+#define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
>+#define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
>+#define DAGB2_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
>+#define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
>+#define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
>+//DAGB2_FIFO_EMPTY
>+#define DAGB2_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
>+#define DAGB2_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
>+//DAGB2_FIFO_FULL
>+#define DAGB2_FIFO_FULL__FULL__SHIFT                                                                          0x0
>+#define DAGB2_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
>+//DAGB2_WR_CREDITS_FULL
>+#define DAGB2_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB2_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
>+//DAGB2_RD_CREDITS_FULL
>+#define DAGB2_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB2_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
>+//DAGB2_PERFCOUNTER_LO
>+#define DAGB2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define DAGB2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//DAGB2_PERFCOUNTER_HI
>+#define DAGB2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define DAGB2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//DAGB2_PERFCOUNTER0_CFG
>+#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB2_PERFCOUNTER1_CFG
>+#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB2_PERFCOUNTER2_CFG
>+#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB2_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB2_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB2_PERFCOUNTER_RSLT_CNTL
>+#define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//DAGB2_RESERVE0
>+#define DAGB2_RESERVE0__RESERVE__SHIFT                                                                        0x0
>+#define DAGB2_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB2_RESERVE1
>+#define DAGB2_RESERVE1__RESERVE__SHIFT                                                                        0x0
>+#define DAGB2_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB2_RESERVE2
>+#define DAGB2_RESERVE2__RESERVE__SHIFT                                                                        0x0
>+#define DAGB2_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB2_RESERVE3
>+#define DAGB2_RESERVE3__RESERVE__SHIFT                                                                        0x0
>+#define DAGB2_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB2_RESERVE4
>+#define DAGB2_RESERVE4__RESERVE__SHIFT                                                                        0x0
>+#define DAGB2_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB2_RESERVE5
>+#define DAGB2_RESERVE5__RESERVE__SHIFT                                                                        0x0
>+#define DAGB2_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB2_RESERVE6
>+#define DAGB2_RESERVE6__RESERVE__SHIFT                                                                        0x0
>+#define DAGB2_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB2_RESERVE7
>+#define DAGB2_RESERVE7__RESERVE__SHIFT                                                                        0x0
>+#define DAGB2_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB2_RESERVE8
>+#define DAGB2_RESERVE8__RESERVE__SHIFT                                                                        0x0
>+#define DAGB2_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB2_RESERVE9
>+#define DAGB2_RESERVE9__RESERVE__SHIFT                                                                        0x0
>+#define DAGB2_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB2_RESERVE10
>+#define DAGB2_RESERVE10__RESERVE__SHIFT                                                                       0x0
>+#define DAGB2_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB2_RESERVE11
>+#define DAGB2_RESERVE11__RESERVE__SHIFT                                                                       0x0
>+#define DAGB2_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB2_RESERVE12
>+#define DAGB2_RESERVE12__RESERVE__SHIFT                                                                       0x0
>+#define DAGB2_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB2_RESERVE13
>+#define DAGB2_RESERVE13__RESERVE__SHIFT                                                                       0x0
>+#define DAGB2_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec3
>+//DAGB3_RDCLI0
>+#define DAGB3_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_RDCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_RDCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_RDCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_RDCLI1
>+#define DAGB3_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_RDCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_RDCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_RDCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_RDCLI2
>+#define DAGB3_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_RDCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_RDCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_RDCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_RDCLI3
>+#define DAGB3_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_RDCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_RDCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_RDCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_RDCLI4
>+#define DAGB3_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_RDCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_RDCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_RDCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_RDCLI5
>+#define DAGB3_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_RDCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_RDCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_RDCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_RDCLI6
>+#define DAGB3_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_RDCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_RDCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_RDCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_RDCLI7
>+#define DAGB3_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_RDCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_RDCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_RDCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_RDCLI8
>+#define DAGB3_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_RDCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_RDCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_RDCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_RDCLI9
>+#define DAGB3_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_RDCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_RDCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_RDCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_RDCLI10
>+#define DAGB3_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB3_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB3_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB3_RDCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB3_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB3_RDCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB3_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB3_RDCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB3_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB3_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB3_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB3_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB3_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB3_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB3_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB3_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB3_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB3_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB3_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB3_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB3_RDCLI11
>+#define DAGB3_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB3_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB3_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB3_RDCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB3_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB3_RDCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB3_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB3_RDCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB3_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB3_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB3_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB3_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB3_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB3_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB3_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB3_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB3_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB3_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB3_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB3_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB3_RDCLI12
>+#define DAGB3_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB3_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB3_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB3_RDCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB3_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB3_RDCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB3_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB3_RDCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB3_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB3_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB3_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB3_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB3_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB3_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB3_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB3_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB3_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB3_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB3_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB3_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB3_RDCLI13
>+#define DAGB3_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB3_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB3_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB3_RDCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB3_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB3_RDCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB3_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB3_RDCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB3_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB3_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB3_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB3_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB3_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB3_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB3_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB3_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB3_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB3_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB3_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB3_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB3_RDCLI14
>+#define DAGB3_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB3_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB3_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB3_RDCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB3_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB3_RDCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB3_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB3_RDCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB3_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB3_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB3_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB3_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB3_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB3_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB3_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB3_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB3_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB3_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB3_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB3_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB3_RDCLI15
>+#define DAGB3_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB3_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB3_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB3_RDCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB3_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB3_RDCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB3_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB3_RDCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB3_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB3_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB3_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB3_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB3_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB3_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB3_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB3_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB3_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB3_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB3_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB3_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB3_RD_CNTL
>+#define DAGB3_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB3_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB3_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB3_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB3_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB3_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB3_RD_GMI_CNTL
>+#define DAGB3_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB3_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB3_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB3_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB3_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB3_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB3_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB3_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB3_RD_ADDR_DAGB
>+#define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB3_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB3_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB3_RD_OUTPUT_DAGB_MAX_BURST
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB3_RD_CGTT_CLK_CTRL
>+#define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB3_L1TLB_RD_CGTT_CLK_CTRL
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB3_ATCVM_RD_CGTT_CLK_CTRL
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB3_RD_ADDR_DAGB_MAX_BURST0
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB3_RD_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB3_RD_ADDR_DAGB_MAX_BURST1
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB3_RD_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB3_RD_VC0_CNTL
>+#define DAGB3_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_RD_VC1_CNTL
>+#define DAGB3_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_RD_VC2_CNTL
>+#define DAGB3_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_RD_VC3_CNTL
>+#define DAGB3_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_RD_VC4_CNTL
>+#define DAGB3_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_RD_VC5_CNTL
>+#define DAGB3_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_RD_VC6_CNTL
>+#define DAGB3_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_RD_VC7_CNTL
>+#define DAGB3_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_RD_CNTL_MISC
>+#define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB3_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB3_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB3_RD_TLB_CREDIT
>+#define DAGB3_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB3_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB3_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB3_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB3_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB3_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB3_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB3_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB3_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB3_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB3_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB3_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB3_RDCLI_ASK_PENDING
>+#define DAGB3_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB3_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB3_RDCLI_GO_PENDING
>+#define DAGB3_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB3_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB3_RDCLI_GBLSEND_PENDING
>+#define DAGB3_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB3_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB3_RDCLI_TLB_PENDING
>+#define DAGB3_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB3_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB3_RDCLI_OARB_PENDING
>+#define DAGB3_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB3_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB3_RDCLI_OSD_PENDING
>+#define DAGB3_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB3_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB3_WRCLI0
>+#define DAGB3_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_WRCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_WRCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_WRCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_WRCLI1
>+#define DAGB3_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_WRCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_WRCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_WRCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_WRCLI2
>+#define DAGB3_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_WRCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_WRCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_WRCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_WRCLI3
>+#define DAGB3_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_WRCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_WRCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_WRCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_WRCLI4
>+#define DAGB3_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_WRCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_WRCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_WRCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_WRCLI5
>+#define DAGB3_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_WRCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_WRCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_WRCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_WRCLI6
>+#define DAGB3_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_WRCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_WRCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_WRCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_WRCLI7
>+#define DAGB3_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_WRCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_WRCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_WRCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_WRCLI8
>+#define DAGB3_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_WRCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_WRCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_WRCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_WRCLI9
>+#define DAGB3_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB3_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB3_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB3_WRCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB3_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB3_WRCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB3_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB3_WRCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB3_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB3_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB3_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB3_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB3_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB3_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB3_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB3_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB3_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB3_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB3_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB3_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB3_WRCLI10
>+#define DAGB3_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB3_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB3_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB3_WRCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB3_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB3_WRCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB3_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB3_WRCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB3_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB3_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB3_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB3_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB3_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB3_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB3_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB3_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB3_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB3_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB3_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB3_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB3_WRCLI11
>+#define DAGB3_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB3_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB3_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB3_WRCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB3_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB3_WRCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB3_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB3_WRCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB3_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB3_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB3_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB3_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB3_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB3_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB3_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB3_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB3_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB3_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB3_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB3_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB3_WRCLI12
>+#define DAGB3_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB3_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB3_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB3_WRCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB3_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB3_WRCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB3_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB3_WRCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB3_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB3_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB3_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB3_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB3_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB3_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB3_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB3_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB3_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB3_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB3_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB3_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB3_WRCLI13
>+#define DAGB3_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB3_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB3_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB3_WRCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB3_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB3_WRCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB3_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB3_WRCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB3_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB3_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB3_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB3_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB3_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB3_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB3_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB3_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB3_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB3_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB3_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB3_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB3_WRCLI14
>+#define DAGB3_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB3_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB3_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB3_WRCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB3_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB3_WRCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB3_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB3_WRCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB3_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB3_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB3_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB3_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB3_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB3_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB3_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB3_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB3_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB3_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB3_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB3_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB3_WRCLI15
>+#define DAGB3_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB3_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB3_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB3_WRCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB3_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB3_WRCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB3_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB3_WRCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB3_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB3_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB3_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB3_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB3_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB3_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB3_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB3_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB3_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB3_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB3_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB3_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB3_WR_CNTL
>+#define DAGB3_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB3_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB3_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB3_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB3_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB3_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB3_WR_GMI_CNTL
>+#define DAGB3_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB3_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB3_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB3_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB3_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB3_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB3_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB3_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB3_WR_ADDR_DAGB
>+#define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB3_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB3_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB3_WR_OUTPUT_DAGB_MAX_BURST
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB3_WR_CGTT_CLK_CTRL
>+#define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB3_L1TLB_WR_CGTT_CLK_CTRL
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB3_ATCVM_WR_CGTT_CLK_CTRL
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB3_WR_ADDR_DAGB_MAX_BURST0
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB3_WR_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB3_WR_ADDR_DAGB_MAX_BURST1
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB3_WR_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB3_WR_DATA_DAGB
>+#define DAGB3_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB3_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB3_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB3_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB3_WR_DATA_DAGB_MAX_BURST0
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB3_WR_DATA_DAGB_LAZY_TIMER0
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB3_WR_DATA_DAGB_MAX_BURST1
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB3_WR_DATA_DAGB_LAZY_TIMER1
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB3_WR_VC0_CNTL
>+#define DAGB3_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_WR_VC1_CNTL
>+#define DAGB3_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_WR_VC2_CNTL
>+#define DAGB3_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_WR_VC3_CNTL
>+#define DAGB3_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_WR_VC4_CNTL
>+#define DAGB3_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_WR_VC5_CNTL
>+#define DAGB3_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_WR_VC6_CNTL
>+#define DAGB3_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_WR_VC7_CNTL
>+#define DAGB3_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB3_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB3_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB3_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB3_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB3_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB3_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB3_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB3_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB3_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB3_WR_CNTL_MISC
>+#define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB3_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB3_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB3_WR_TLB_CREDIT
>+#define DAGB3_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB3_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB3_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB3_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB3_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB3_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB3_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB3_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB3_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB3_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB3_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB3_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB3_WR_DATA_CREDIT
>+#define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
>+#define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
>+#define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
>+#define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
>+#define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
>+#define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
>+#define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
>+#define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
>+//DAGB3_WR_MISC_CREDIT
>+#define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
>+#define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
>+#define DAGB3_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
>+#define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
>+#define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
>+#define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
>+#define DAGB3_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
>+#define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
>+//DAGB3_WRCLI_ASK_PENDING
>+#define DAGB3_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB3_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB3_WRCLI_GO_PENDING
>+#define DAGB3_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB3_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB3_WRCLI_GBLSEND_PENDING
>+#define DAGB3_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB3_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB3_WRCLI_TLB_PENDING
>+#define DAGB3_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB3_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB3_WRCLI_OARB_PENDING
>+#define DAGB3_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB3_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB3_WRCLI_OSD_PENDING
>+#define DAGB3_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB3_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB3_WRCLI_DBUS_ASK_PENDING
>+#define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
>+#define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
>+//DAGB3_WRCLI_DBUS_GO_PENDING
>+#define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB3_DAGB_DLY
>+#define DAGB3_DAGB_DLY__DLY__SHIFT                                                                            0x0
>+#define DAGB3_DAGB_DLY__CLI__SHIFT                                                                            0x8
>+#define DAGB3_DAGB_DLY__POS__SHIFT                                                                            0x10
>+#define DAGB3_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
>+#define DAGB3_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
>+#define DAGB3_DAGB_DLY__POS_MASK                                                                              0x000F0000L
>+//DAGB3_CNTL_MISC
>+#define DAGB3_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
>+#define DAGB3_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
>+#define DAGB3_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
>+#define DAGB3_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
>+#define DAGB3_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
>+#define DAGB3_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
>+#define DAGB3_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
>+#define DAGB3_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
>+#define DAGB3_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
>+#define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
>+#define DAGB3_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
>+#define DAGB3_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
>+#define DAGB3_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
>+#define DAGB3_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
>+#define DAGB3_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
>+#define DAGB3_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
>+#define DAGB3_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
>+#define DAGB3_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
>+#define DAGB3_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
>+#define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
>+//DAGB3_CNTL_MISC2
>+#define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
>+#define DAGB3_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
>+#define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
>+#define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
>+#define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
>+#define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
>+#define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
>+#define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
>+#define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
>+#define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
>+#define DAGB3_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
>+#define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
>+#define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
>+#define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
>+#define DAGB3_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
>+#define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
>+#define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
>+#define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
>+#define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
>+#define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
>+#define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
>+#define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
>+#define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
>+#define DAGB3_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
>+#define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
>+#define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
>+//DAGB3_FIFO_EMPTY
>+#define DAGB3_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
>+#define DAGB3_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
>+//DAGB3_FIFO_FULL
>+#define DAGB3_FIFO_FULL__FULL__SHIFT                                                                          0x0
>+#define DAGB3_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
>+//DAGB3_WR_CREDITS_FULL
>+#define DAGB3_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB3_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
>+//DAGB3_RD_CREDITS_FULL
>+#define DAGB3_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB3_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
>+//DAGB3_PERFCOUNTER_LO
>+#define DAGB3_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define DAGB3_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//DAGB3_PERFCOUNTER_HI
>+#define DAGB3_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define DAGB3_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//DAGB3_PERFCOUNTER0_CFG
>+#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB3_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB3_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB3_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB3_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB3_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB3_PERFCOUNTER1_CFG
>+#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB3_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB3_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB3_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB3_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB3_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB3_PERFCOUNTER2_CFG
>+#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB3_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB3_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB3_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB3_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB3_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB3_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB3_PERFCOUNTER_RSLT_CNTL
>+#define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//DAGB3_RESERVE0
>+#define DAGB3_RESERVE0__RESERVE__SHIFT                                                                        0x0
>+#define DAGB3_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB3_RESERVE1
>+#define DAGB3_RESERVE1__RESERVE__SHIFT                                                                        0x0
>+#define DAGB3_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB3_RESERVE2
>+#define DAGB3_RESERVE2__RESERVE__SHIFT                                                                        0x0
>+#define DAGB3_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB3_RESERVE3
>+#define DAGB3_RESERVE3__RESERVE__SHIFT                                                                        0x0
>+#define DAGB3_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB3_RESERVE4
>+#define DAGB3_RESERVE4__RESERVE__SHIFT                                                                        0x0
>+#define DAGB3_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB3_RESERVE5
>+#define DAGB3_RESERVE5__RESERVE__SHIFT                                                                        0x0
>+#define DAGB3_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB3_RESERVE6
>+#define DAGB3_RESERVE6__RESERVE__SHIFT                                                                        0x0
>+#define DAGB3_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB3_RESERVE7
>+#define DAGB3_RESERVE7__RESERVE__SHIFT                                                                        0x0
>+#define DAGB3_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB3_RESERVE8
>+#define DAGB3_RESERVE8__RESERVE__SHIFT                                                                        0x0
>+#define DAGB3_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB3_RESERVE9
>+#define DAGB3_RESERVE9__RESERVE__SHIFT                                                                        0x0
>+#define DAGB3_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB3_RESERVE10
>+#define DAGB3_RESERVE10__RESERVE__SHIFT                                                                       0x0
>+#define DAGB3_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB3_RESERVE11
>+#define DAGB3_RESERVE11__RESERVE__SHIFT                                                                       0x0
>+#define DAGB3_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB3_RESERVE12
>+#define DAGB3_RESERVE12__RESERVE__SHIFT                                                                       0x0
>+#define DAGB3_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB3_RESERVE13
>+#define DAGB3_RESERVE13__RESERVE__SHIFT                                                                       0x0
>+#define DAGB3_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec4
>+//DAGB4_RDCLI0
>+#define DAGB4_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_RDCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_RDCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_RDCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_RDCLI1
>+#define DAGB4_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_RDCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_RDCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_RDCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_RDCLI2
>+#define DAGB4_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_RDCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_RDCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_RDCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_RDCLI3
>+#define DAGB4_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_RDCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_RDCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_RDCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_RDCLI4
>+#define DAGB4_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_RDCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_RDCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_RDCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_RDCLI5
>+#define DAGB4_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_RDCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_RDCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_RDCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_RDCLI6
>+#define DAGB4_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_RDCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_RDCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_RDCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_RDCLI7
>+#define DAGB4_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_RDCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_RDCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_RDCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_RDCLI8
>+#define DAGB4_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_RDCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_RDCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_RDCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_RDCLI9
>+#define DAGB4_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_RDCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_RDCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_RDCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_RDCLI10
>+#define DAGB4_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB4_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB4_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB4_RDCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB4_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB4_RDCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB4_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB4_RDCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB4_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB4_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB4_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB4_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB4_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB4_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB4_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB4_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB4_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB4_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB4_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB4_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB4_RDCLI11
>+#define DAGB4_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB4_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB4_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB4_RDCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB4_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB4_RDCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB4_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB4_RDCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB4_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB4_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB4_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB4_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB4_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB4_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB4_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB4_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB4_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB4_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB4_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB4_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB4_RDCLI12
>+#define DAGB4_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB4_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB4_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB4_RDCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB4_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB4_RDCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB4_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB4_RDCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB4_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB4_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB4_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB4_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB4_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB4_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB4_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB4_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB4_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB4_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB4_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB4_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB4_RDCLI13
>+#define DAGB4_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB4_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB4_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB4_RDCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB4_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB4_RDCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB4_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB4_RDCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB4_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB4_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB4_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB4_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB4_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB4_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB4_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB4_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB4_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB4_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB4_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB4_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB4_RDCLI14
>+#define DAGB4_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB4_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB4_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB4_RDCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB4_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB4_RDCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB4_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB4_RDCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB4_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB4_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB4_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB4_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB4_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB4_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB4_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB4_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB4_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB4_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB4_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB4_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB4_RDCLI15
>+#define DAGB4_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB4_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB4_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB4_RDCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB4_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB4_RDCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB4_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB4_RDCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB4_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB4_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB4_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB4_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB4_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB4_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB4_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB4_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB4_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB4_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB4_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB4_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB4_RD_CNTL
>+#define DAGB4_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB4_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB4_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB4_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB4_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB4_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB4_RD_GMI_CNTL
>+#define DAGB4_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB4_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB4_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB4_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB4_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB4_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB4_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB4_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB4_RD_ADDR_DAGB
>+#define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB4_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB4_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB4_RD_OUTPUT_DAGB_MAX_BURST
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB4_RD_CGTT_CLK_CTRL
>+#define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB4_L1TLB_RD_CGTT_CLK_CTRL
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB4_ATCVM_RD_CGTT_CLK_CTRL
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB4_RD_ADDR_DAGB_MAX_BURST0
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB4_RD_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB4_RD_ADDR_DAGB_MAX_BURST1
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB4_RD_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB4_RD_VC0_CNTL
>+#define DAGB4_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_RD_VC1_CNTL
>+#define DAGB4_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_RD_VC2_CNTL
>+#define DAGB4_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_RD_VC3_CNTL
>+#define DAGB4_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_RD_VC4_CNTL
>+#define DAGB4_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_RD_VC5_CNTL
>+#define DAGB4_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_RD_VC6_CNTL
>+#define DAGB4_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_RD_VC7_CNTL
>+#define DAGB4_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_RD_CNTL_MISC
>+#define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB4_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB4_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB4_RD_TLB_CREDIT
>+#define DAGB4_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB4_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB4_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB4_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB4_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB4_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB4_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB4_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB4_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB4_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB4_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB4_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB4_RDCLI_ASK_PENDING
>+#define DAGB4_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB4_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB4_RDCLI_GO_PENDING
>+#define DAGB4_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB4_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB4_RDCLI_GBLSEND_PENDING
>+#define DAGB4_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB4_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB4_RDCLI_TLB_PENDING
>+#define DAGB4_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB4_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB4_RDCLI_OARB_PENDING
>+#define DAGB4_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB4_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB4_RDCLI_OSD_PENDING
>+#define DAGB4_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB4_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB4_WRCLI0
>+#define DAGB4_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_WRCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_WRCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_WRCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_WRCLI1
>+#define DAGB4_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_WRCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_WRCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_WRCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_WRCLI2
>+#define DAGB4_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_WRCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_WRCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_WRCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_WRCLI3
>+#define DAGB4_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_WRCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_WRCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_WRCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_WRCLI4
>+#define DAGB4_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_WRCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_WRCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_WRCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_WRCLI5
>+#define DAGB4_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_WRCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_WRCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_WRCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_WRCLI6
>+#define DAGB4_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_WRCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_WRCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_WRCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_WRCLI7
>+#define DAGB4_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_WRCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_WRCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_WRCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_WRCLI8
>+#define DAGB4_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_WRCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_WRCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_WRCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_WRCLI9
>+#define DAGB4_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB4_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB4_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB4_WRCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB4_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB4_WRCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB4_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB4_WRCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB4_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB4_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB4_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB4_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB4_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB4_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB4_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB4_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB4_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB4_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB4_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB4_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB4_WRCLI10
>+#define DAGB4_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB4_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB4_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB4_WRCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB4_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB4_WRCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB4_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB4_WRCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB4_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB4_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB4_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB4_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB4_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB4_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB4_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB4_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB4_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB4_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB4_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB4_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB4_WRCLI11
>+#define DAGB4_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB4_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB4_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB4_WRCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB4_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB4_WRCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB4_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB4_WRCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB4_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB4_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB4_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB4_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB4_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB4_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB4_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB4_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB4_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB4_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB4_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB4_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB4_WRCLI12
>+#define DAGB4_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB4_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB4_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB4_WRCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB4_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB4_WRCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB4_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB4_WRCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB4_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB4_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB4_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB4_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB4_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB4_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB4_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB4_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB4_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB4_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB4_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB4_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB4_WRCLI13
>+#define DAGB4_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB4_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB4_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB4_WRCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB4_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB4_WRCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB4_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB4_WRCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB4_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB4_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB4_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB4_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB4_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB4_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB4_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB4_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB4_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB4_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB4_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB4_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB4_WRCLI14
>+#define DAGB4_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB4_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB4_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB4_WRCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB4_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB4_WRCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB4_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB4_WRCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB4_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB4_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB4_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB4_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB4_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB4_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB4_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB4_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB4_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB4_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB4_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB4_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB4_WRCLI15
>+#define DAGB4_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB4_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB4_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB4_WRCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB4_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB4_WRCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB4_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB4_WRCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB4_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB4_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB4_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB4_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB4_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB4_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB4_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB4_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB4_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB4_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB4_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB4_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB4_WR_CNTL
>+#define DAGB4_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB4_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB4_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB4_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB4_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB4_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB4_WR_GMI_CNTL
>+#define DAGB4_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB4_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB4_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB4_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB4_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB4_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB4_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB4_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB4_WR_ADDR_DAGB
>+#define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB4_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB4_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB4_WR_OUTPUT_DAGB_MAX_BURST
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB4_WR_CGTT_CLK_CTRL
>+#define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB4_L1TLB_WR_CGTT_CLK_CTRL
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB4_ATCVM_WR_CGTT_CLK_CTRL
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB4_WR_ADDR_DAGB_MAX_BURST0
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB4_WR_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB4_WR_ADDR_DAGB_MAX_BURST1
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB4_WR_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB4_WR_DATA_DAGB
>+#define DAGB4_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB4_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB4_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB4_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB4_WR_DATA_DAGB_MAX_BURST0
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB4_WR_DATA_DAGB_LAZY_TIMER0
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB4_WR_DATA_DAGB_MAX_BURST1
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB4_WR_DATA_DAGB_LAZY_TIMER1
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB4_WR_VC0_CNTL
>+#define DAGB4_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_WR_VC1_CNTL
>+#define DAGB4_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_WR_VC2_CNTL
>+#define DAGB4_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_WR_VC3_CNTL
>+#define DAGB4_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_WR_VC4_CNTL
>+#define DAGB4_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_WR_VC5_CNTL
>+#define DAGB4_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_WR_VC6_CNTL
>+#define DAGB4_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_WR_VC7_CNTL
>+#define DAGB4_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB4_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB4_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB4_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB4_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB4_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB4_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB4_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB4_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB4_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB4_WR_CNTL_MISC
>+#define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB4_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB4_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB4_WR_TLB_CREDIT
>+#define DAGB4_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB4_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB4_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB4_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB4_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB4_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB4_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB4_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB4_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB4_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB4_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB4_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB4_WR_DATA_CREDIT
>+#define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
>+#define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
>+#define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
>+#define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
>+#define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
>+#define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
>+#define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
>+#define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
>+//DAGB4_WR_MISC_CREDIT
>+#define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
>+#define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
>+#define DAGB4_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
>+#define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
>+#define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
>+#define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
>+#define DAGB4_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
>+#define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
>+//DAGB4_WRCLI_ASK_PENDING
>+#define DAGB4_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB4_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB4_WRCLI_GO_PENDING
>+#define DAGB4_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB4_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB4_WRCLI_GBLSEND_PENDING
>+#define DAGB4_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB4_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB4_WRCLI_TLB_PENDING
>+#define DAGB4_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB4_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB4_WRCLI_OARB_PENDING
>+#define DAGB4_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB4_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB4_WRCLI_OSD_PENDING
>+#define DAGB4_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB4_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB4_WRCLI_DBUS_ASK_PENDING
>+#define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
>+#define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
>+//DAGB4_WRCLI_DBUS_GO_PENDING
>+#define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB4_DAGB_DLY
>+#define DAGB4_DAGB_DLY__DLY__SHIFT                                                                            0x0
>+#define DAGB4_DAGB_DLY__CLI__SHIFT                                                                            0x8
>+#define DAGB4_DAGB_DLY__POS__SHIFT                                                                            0x10
>+#define DAGB4_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
>+#define DAGB4_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
>+#define DAGB4_DAGB_DLY__POS_MASK                                                                              0x000F0000L
>+//DAGB4_CNTL_MISC
>+#define DAGB4_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
>+#define DAGB4_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
>+#define DAGB4_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
>+#define DAGB4_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
>+#define DAGB4_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
>+#define DAGB4_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
>+#define DAGB4_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
>+#define DAGB4_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
>+#define DAGB4_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
>+#define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
>+#define DAGB4_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
>+#define DAGB4_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
>+#define DAGB4_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
>+#define DAGB4_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
>+#define DAGB4_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
>+#define DAGB4_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
>+#define DAGB4_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
>+#define DAGB4_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
>+#define DAGB4_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
>+#define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
>+//DAGB4_CNTL_MISC2
>+#define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
>+#define DAGB4_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
>+#define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
>+#define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
>+#define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
>+#define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
>+#define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
>+#define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
>+#define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
>+#define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
>+#define DAGB4_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
>+#define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
>+#define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
>+#define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
>+#define DAGB4_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
>+#define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
>+#define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
>+#define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
>+#define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
>+#define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
>+#define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
>+#define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
>+#define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
>+#define DAGB4_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
>+#define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
>+#define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
>+//DAGB4_FIFO_EMPTY
>+#define DAGB4_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
>+#define DAGB4_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
>+//DAGB4_FIFO_FULL
>+#define DAGB4_FIFO_FULL__FULL__SHIFT                                                                          0x0
>+#define DAGB4_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
>+//DAGB4_WR_CREDITS_FULL
>+#define DAGB4_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB4_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
>+//DAGB4_RD_CREDITS_FULL
>+#define DAGB4_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB4_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
>+//DAGB4_PERFCOUNTER_LO
>+#define DAGB4_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define DAGB4_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//DAGB4_PERFCOUNTER_HI
>+#define DAGB4_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define DAGB4_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//DAGB4_PERFCOUNTER0_CFG
>+#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB4_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB4_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB4_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB4_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB4_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB4_PERFCOUNTER1_CFG
>+#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB4_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB4_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB4_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB4_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB4_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB4_PERFCOUNTER2_CFG
>+#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB4_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB4_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB4_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB4_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB4_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB4_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB4_PERFCOUNTER_RSLT_CNTL
>+#define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//DAGB4_RESERVE0
>+#define DAGB4_RESERVE0__RESERVE__SHIFT                                                                        0x0
>+#define DAGB4_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB4_RESERVE1
>+#define DAGB4_RESERVE1__RESERVE__SHIFT                                                                        0x0
>+#define DAGB4_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB4_RESERVE2
>+#define DAGB4_RESERVE2__RESERVE__SHIFT                                                                        0x0
>+#define DAGB4_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB4_RESERVE3
>+#define DAGB4_RESERVE3__RESERVE__SHIFT                                                                        0x0
>+#define DAGB4_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB4_RESERVE4
>+#define DAGB4_RESERVE4__RESERVE__SHIFT                                                                        0x0
>+#define DAGB4_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB4_RESERVE5
>+#define DAGB4_RESERVE5__RESERVE__SHIFT                                                                        0x0
>+#define DAGB4_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB4_RESERVE6
>+#define DAGB4_RESERVE6__RESERVE__SHIFT                                                                        0x0
>+#define DAGB4_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB4_RESERVE7
>+#define DAGB4_RESERVE7__RESERVE__SHIFT                                                                        0x0
>+#define DAGB4_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB4_RESERVE8
>+#define DAGB4_RESERVE8__RESERVE__SHIFT                                                                        0x0
>+#define DAGB4_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB4_RESERVE9
>+#define DAGB4_RESERVE9__RESERVE__SHIFT                                                                        0x0
>+#define DAGB4_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB4_RESERVE10
>+#define DAGB4_RESERVE10__RESERVE__SHIFT                                                                       0x0
>+#define DAGB4_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB4_RESERVE11
>+#define DAGB4_RESERVE11__RESERVE__SHIFT                                                                       0x0
>+#define DAGB4_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB4_RESERVE12
>+#define DAGB4_RESERVE12__RESERVE__SHIFT                                                                       0x0
>+#define DAGB4_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB4_RESERVE13
>+#define DAGB4_RESERVE13__RESERVE__SHIFT                                                                       0x0
>+#define DAGB4_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: mmhub_ea_mmeadec0
>+//MMEA0_DRAM_RD_CLI2GRP_MAP0
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA0_DRAM_RD_CLI2GRP_MAP1
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA0_DRAM_WR_CLI2GRP_MAP0
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA0_DRAM_WR_CLI2GRP_MAP1
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA0_DRAM_RD_GRP2VC_MAP
>+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA0_DRAM_WR_GRP2VC_MAP
>+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA0_DRAM_RD_LAZY
>+#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA0_DRAM_WR_LAZY
>+#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA0_DRAM_RD_CAM_CNTL
>+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA0_DRAM_WR_CAM_CNTL
>+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA0_DRAM_PAGE_BURST
>+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
>+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
>+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
>+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
>+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
>+#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
>+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
>+#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
>+//MMEA0_DRAM_RD_PRI_AGE
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA0_DRAM_WR_PRI_AGE
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA0_DRAM_RD_PRI_QUEUING
>+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA0_DRAM_WR_PRI_QUEUING
>+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA0_DRAM_RD_PRI_FIXED
>+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA0_DRAM_WR_PRI_FIXED
>+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA0_DRAM_RD_PRI_URGENCY
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA0_DRAM_WR_PRI_URGENCY
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA0_DRAM_RD_PRI_QUANT_PRI1
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA0_DRAM_RD_PRI_QUANT_PRI2
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA0_DRAM_RD_PRI_QUANT_PRI3
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA0_DRAM_WR_PRI_QUANT_PRI1
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA0_DRAM_WR_PRI_QUANT_PRI2
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA0_DRAM_WR_PRI_QUANT_PRI3
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA0_GMI_RD_CLI2GRP_MAP0
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA0_GMI_RD_CLI2GRP_MAP1
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA0_GMI_WR_CLI2GRP_MAP0
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA0_GMI_WR_CLI2GRP_MAP1
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA0_GMI_RD_GRP2VC_MAP
>+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA0_GMI_WR_GRP2VC_MAP
>+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA0_GMI_RD_LAZY
>+#define MMEA0_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA0_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA0_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA0_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA0_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA0_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA0_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA0_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA0_GMI_WR_LAZY
>+#define MMEA0_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA0_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA0_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA0_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA0_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA0_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA0_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA0_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA0_GMI_RD_CAM_CNTL
>+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA0_GMI_WR_CAM_CNTL
>+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA0_GMI_PAGE_BURST
>+#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA0_GMI_RD_PRI_AGE
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA0_GMI_WR_PRI_AGE
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA0_GMI_RD_PRI_QUEUING
>+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA0_GMI_WR_PRI_QUEUING
>+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA0_GMI_RD_PRI_FIXED
>+#define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA0_GMI_WR_PRI_FIXED
>+#define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA0_GMI_RD_PRI_URGENCY
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA0_GMI_WR_PRI_URGENCY
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA0_GMI_RD_PRI_URGENCY_MASKING
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA0_GMI_WR_PRI_URGENCY_MASKING
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA0_GMI_RD_PRI_QUANT_PRI1
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA0_GMI_RD_PRI_QUANT_PRI2
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA0_GMI_RD_PRI_QUANT_PRI3
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA0_GMI_WR_PRI_QUANT_PRI1
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA0_GMI_WR_PRI_QUANT_PRI2
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA0_GMI_WR_PRI_QUANT_PRI3
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA0_ADDRNORM_BASE_ADDR0
>+#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA0_ADDRNORM_LIMIT_ADDR0
>+#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA0_ADDRNORM_BASE_ADDR1
>+#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA0_ADDRNORM_LIMIT_ADDR1
>+#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA0_ADDRNORM_OFFSET_ADDR1
>+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA0_ADDRNORM_BASE_ADDR2
>+#define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA0_ADDRNORM_LIMIT_ADDR2
>+#define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA0_ADDRNORM_BASE_ADDR3
>+#define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA0_ADDRNORM_LIMIT_ADDR3
>+#define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA0_ADDRNORM_OFFSET_ADDR3
>+#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA0_ADDRNORM_BASE_ADDR4
>+#define MMEA0_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA0_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA0_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA0_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA0_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA0_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA0_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA0_ADDRNORM_LIMIT_ADDR4
>+#define MMEA0_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA0_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA0_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA0_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA0_ADDRNORM_BASE_ADDR5
>+#define MMEA0_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA0_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA0_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA0_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA0_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA0_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA0_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA0_ADDRNORM_LIMIT_ADDR5
>+#define MMEA0_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA0_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA0_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA0_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA0_ADDRNORM_OFFSET_ADDR5
>+#define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA0_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA0_ADDRNORMDRAM_HOLE_CNTL
>+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
>+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
>+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
>+#define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
>+//MMEA0_ADDRNORMGMI_HOLE_CNTL
>+#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
>+#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
>+#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
>+#define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
>+//MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG
>+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
>+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
>+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
>+#define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
>+//MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG
>+#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
>+#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
>+#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
>+#define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
>+//MMEA0_ADDRDEC_BANK_CFG
>+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
>+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
>+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
>+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
>+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
>+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
>+#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
>+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
>+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
>+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
>+#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
>+//MMEA0_ADDRDEC_MISC_CFG
>+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
>+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
>+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
>+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
>+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
>+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
>+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
>+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
>+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
>+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
>+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
>+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
>+#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
>+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
>+#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
>+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
>+#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
>+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
>+#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
>+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
>+#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
>+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA0_ADDRDECDRAM_ADDR_HASH_PC
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
>+//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
>+//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDECDRAM_HARVEST_ENABLE
>+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
>+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
>+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
>+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
>+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
>+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
>+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
>+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
>+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
>+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
>+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
>+#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
>+//MMEA0_ADDRDECGMI_ADDR_HASH_BANK0
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA0_ADDRDECGMI_ADDR_HASH_BANK1
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA0_ADDRDECGMI_ADDR_HASH_BANK2
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA0_ADDRDECGMI_ADDR_HASH_BANK3
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA0_ADDRDECGMI_ADDR_HASH_BANK4
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA0_ADDRDECGMI_ADDR_HASH_BANK5
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA0_ADDRDECGMI_ADDR_HASH_PC
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
>+//MMEA0_ADDRDECGMI_ADDR_HASH_PC2
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
>+//MMEA0_ADDRDECGMI_ADDR_HASH_CS0
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA0_ADDRDECGMI_ADDR_HASH_CS1
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA0_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA0_ADDRDECGMI_HARVEST_ENABLE
>+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
>+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
>+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
>+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
>+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
>+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
>+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
>+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
>+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
>+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
>+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
>+#define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
>+//MMEA0_ADDRDEC0_BASE_ADDR_CS0
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDEC0_BASE_ADDR_CS1
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDEC0_BASE_ADDR_CS2
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDEC0_BASE_ADDR_CS3
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA0_ADDRDEC0_ADDR_MASK_CS01
>+#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA0_ADDRDEC0_ADDR_MASK_CS23
>+#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01
>+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23
>+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA0_ADDRDEC0_ADDR_CFG_CS01
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA0_ADDRDEC0_ADDR_CFG_CS23
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA0_ADDRDEC0_ADDR_SEL_CS01
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA0_ADDRDEC0_ADDR_SEL_CS23
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA0_ADDRDEC0_ADDR_SEL2_CS01
>+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA0_ADDRDEC0_ADDR_SEL2_CS23
>+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA0_ADDRDEC0_COL_SEL_LO_CS01
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA0_ADDRDEC0_COL_SEL_LO_CS23
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA0_ADDRDEC0_COL_SEL_HI_CS01
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA0_ADDRDEC0_COL_SEL_HI_CS23
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA0_ADDRDEC0_RM_SEL_CS01
>+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA0_ADDRDEC0_RM_SEL_CS23
>+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA0_ADDRDEC0_RM_SEL_SECCS01
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA0_ADDRDEC0_RM_SEL_SECCS23
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA0_ADDRDEC1_BASE_ADDR_CS0
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDEC1_BASE_ADDR_CS1
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDEC1_BASE_ADDR_CS2
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDEC1_BASE_ADDR_CS3
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA0_ADDRDEC1_ADDR_MASK_CS01
>+#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA0_ADDRDEC1_ADDR_MASK_CS23
>+#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01
>+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23
>+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA0_ADDRDEC1_ADDR_CFG_CS01
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA0_ADDRDEC1_ADDR_CFG_CS23
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA0_ADDRDEC1_ADDR_SEL_CS01
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA0_ADDRDEC1_ADDR_SEL_CS23
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA0_ADDRDEC1_ADDR_SEL2_CS01
>+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA0_ADDRDEC1_ADDR_SEL2_CS23
>+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA0_ADDRDEC1_COL_SEL_LO_CS01
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA0_ADDRDEC1_COL_SEL_LO_CS23
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA0_ADDRDEC1_COL_SEL_HI_CS01
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA0_ADDRDEC1_COL_SEL_HI_CS23
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA0_ADDRDEC1_RM_SEL_CS01
>+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA0_ADDRDEC1_RM_SEL_CS23
>+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA0_ADDRDEC1_RM_SEL_SECCS01
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA0_ADDRDEC1_RM_SEL_SECCS23
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA0_ADDRDEC2_BASE_ADDR_CS0
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDEC2_BASE_ADDR_CS1
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDEC2_BASE_ADDR_CS2
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDEC2_BASE_ADDR_CS3
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA0_ADDRDEC2_BASE_ADDR_SECCS0
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA0_ADDRDEC2_BASE_ADDR_SECCS1
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA0_ADDRDEC2_BASE_ADDR_SECCS2
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA0_ADDRDEC2_BASE_ADDR_SECCS3
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA0_ADDRDEC2_ADDR_MASK_CS01
>+#define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA0_ADDRDEC2_ADDR_MASK_CS23
>+#define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA0_ADDRDEC2_ADDR_MASK_SECCS01
>+#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA0_ADDRDEC2_ADDR_MASK_SECCS23
>+#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA0_ADDRDEC2_ADDR_CFG_CS01
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA0_ADDRDEC2_ADDR_CFG_CS23
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA0_ADDRDEC2_ADDR_SEL_CS01
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA0_ADDRDEC2_ADDR_SEL_CS23
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA0_ADDRDEC2_ADDR_SEL2_CS01
>+#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA0_ADDRDEC2_ADDR_SEL2_CS23
>+#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA0_ADDRDEC2_COL_SEL_LO_CS01
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA0_ADDRDEC2_COL_SEL_LO_CS23
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA0_ADDRDEC2_COL_SEL_HI_CS01
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA0_ADDRDEC2_COL_SEL_HI_CS23
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA0_ADDRDEC2_RM_SEL_CS01
>+#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA0_ADDRDEC2_RM_SEL_CS23
>+#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA0_ADDRDEC2_RM_SEL_SECCS01
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA0_ADDRDEC2_RM_SEL_SECCS23
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA0_ADDRNORMDRAM_GLOBAL_CNTL
>+#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
>+#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
>+#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
>+#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
>+#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
>+#define MMEA0_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
>+//MMEA0_ADDRNORMGMI_GLOBAL_CNTL
>+#define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
>+#define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
>+#define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
>+#define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
>+#define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
>+#define MMEA0_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
>+//MMEA0_IO_RD_CLI2GRP_MAP0
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA0_IO_RD_CLI2GRP_MAP1
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA0_IO_WR_CLI2GRP_MAP0
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA0_IO_WR_CLI2GRP_MAP1
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA0_IO_RD_COMBINE_FLUSH
>+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA0_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA0_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA0_IO_WR_COMBINE_FLUSH
>+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA0_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA0_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA0_IO_GROUP_BURST
>+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA0_IO_RD_PRI_AGE
>+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA0_IO_WR_PRI_AGE
>+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA0_IO_RD_PRI_QUEUING
>+#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA0_IO_WR_PRI_QUEUING
>+#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA0_IO_RD_PRI_FIXED
>+#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA0_IO_WR_PRI_FIXED
>+#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA0_IO_RD_PRI_URGENCY
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA0_IO_WR_PRI_URGENCY
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA0_IO_RD_PRI_URGENCY_MASKING
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA0_IO_WR_PRI_URGENCY_MASKING
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA0_IO_RD_PRI_QUANT_PRI1
>+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA0_IO_RD_PRI_QUANT_PRI2
>+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA0_IO_RD_PRI_QUANT_PRI3
>+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA0_IO_WR_PRI_QUANT_PRI1
>+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA0_IO_WR_PRI_QUANT_PRI2
>+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA0_IO_WR_PRI_QUANT_PRI3
>+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA0_SDP_ARB_DRAM
>+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
>+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
>+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
>+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
>+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
>+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
>+#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
>+#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
>+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
>+#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
>+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
>+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
>+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
>+#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
>+#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
>+#define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
>+//MMEA0_SDP_ARB_GMI
>+#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
>+#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
>+#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
>+#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
>+#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
>+#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
>+#define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
>+#define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
>+#define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
>+#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
>+#define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
>+#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
>+#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
>+#define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
>+#define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
>+#define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
>+#define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
>+#define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
>+//MMEA0_SDP_ARB_FINAL
>+#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
>+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
>+#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
>+#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
>+#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
>+#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
>+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
>+#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
>+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
>+#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
>+#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
>+#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
>+#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
>+#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
>+#define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
>+//MMEA0_SDP_DRAM_PRIORITY
>+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
>+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
>+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
>+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
>+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
>+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
>+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
>+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
>+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
>+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
>+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
>+#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
>+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
>+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
>+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
>+#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
>+//MMEA0_SDP_GMI_PRIORITY
>+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
>+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
>+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
>+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
>+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
>+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
>+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
>+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
>+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
>+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
>+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
>+#define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
>+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
>+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
>+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
>+#define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
>+//MMEA0_SDP_IO_PRIORITY
>+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
>+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
>+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
>+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
>+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
>+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
>+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
>+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
>+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
>+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
>+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
>+#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
>+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
>+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
>+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
>+#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
>+//MMEA0_SDP_CREDITS
>+#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
>+#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
>+#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
>+#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
>+#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
>+#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
>+//MMEA0_SDP_TAG_RESERVE0
>+#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
>+#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
>+#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
>+#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
>+#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
>+#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
>+#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
>+#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
>+//MMEA0_SDP_TAG_RESERVE1
>+#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
>+#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
>+#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
>+#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
>+#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
>+#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
>+#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
>+#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
>+//MMEA0_SDP_VCC_RESERVE0
>+#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA0_SDP_VCC_RESERVE1
>+#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA0_SDP_VCD_RESERVE0
>+#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA0_SDP_VCD_RESERVE1
>+#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA0_SDP_REQ_CNTL
>+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
>+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
>+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
>+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
>+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
>+#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
>+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
>+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
>+#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
>+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
>+#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
>+#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
>+//MMEA0_MISC
>+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
>+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
>+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
>+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
>+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
>+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
>+#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
>+#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
>+#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
>+#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
>+#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
>+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
>+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
>+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
>+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
>+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
>+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
>+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
>+#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
>+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
>+#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
>+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
>+#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
>+#define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
>+#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
>+#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
>+#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
>+#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
>+#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
>+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
>+#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
>+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
>+#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
>+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
>+#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
>+//MMEA0_LATENCY_SAMPLING
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
>+#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
>+//MMEA0_PERFCOUNTER_LO
>+#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//MMEA0_PERFCOUNTER_HI
>+#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//MMEA0_PERFCOUNTER0_CFG
>+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA0_PERFCOUNTER1_CFG
>+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA0_PERFCOUNTER_RSLT_CNTL
>+#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//MMEA0_EDC_CNT
>+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
>+#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
>+#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
>+#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
>+#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
>+#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
>+#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
>+#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
>+#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
>+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
>+#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
>+#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
>+#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
>+#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
>+#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
>+#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
>+#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
>+#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
>+//MMEA0_EDC_CNT2
>+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
>+#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
>+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
>+#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
>+//MMEA0_DSM_CNTL
>+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
>+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
>+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
>+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
>+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
>+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
>+#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
>+#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
>+#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
>+#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
>+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
>+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
>+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
>+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
>+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
>+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
>+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
>+#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
>+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
>+#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
>+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
>+#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
>+#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
>+#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
>+#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
>+#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
>+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
>+#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
>+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
>+#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
>+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
>+#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
>+//MMEA0_DSM_CNTLA
>+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
>+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
>+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
>+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
>+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
>+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
>+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
>+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
>+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
>+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
>+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
>+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
>+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
>+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
>+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
>+#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
>+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
>+#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
>+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
>+#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
>+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
>+#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
>+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
>+#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
>+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
>+#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
>+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
>+#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
>+//MMEA0_DSM_CNTL2
>+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
>+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
>+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
>+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
>+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
>+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
>+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
>+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
>+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
>+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
>+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
>+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
>+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
>+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
>+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
>+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
>+#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
>+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
>+#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
>+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
>+#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
>+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
>+#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
>+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
>+#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
>+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
>+#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
>+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
>+#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
>+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
>+#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
>+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
>+#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
>+#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
>+//MMEA0_DSM_CNTL2A
>+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
>+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
>+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
>+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
>+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
>+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
>+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
>+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
>+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
>+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
>+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
>+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
>+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
>+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
>+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
>+#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
>+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
>+#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
>+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
>+#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
>+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
>+#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
>+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
>+#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
>+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
>+#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
>+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
>+#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
>+//MMEA0_CGTT_CLK_CTRL
>+#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
>+#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
>+#define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
>+#define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
>+#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
>+#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
>+#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
>+#define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
>+#define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
>+#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
>+#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
>+//MMEA0_EDC_MODE
>+#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
>+#define MMEA0_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
>+#define MMEA0_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
>+#define MMEA0_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
>+#define MMEA0_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
>+#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
>+#define MMEA0_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
>+#define MMEA0_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
>+#define MMEA0_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
>+#define MMEA0_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
>+//MMEA0_ERR_STATUS
>+#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
>+#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
>+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
>+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
>+#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
>+#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
>+#define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
>+#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
>+#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
>+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
>+#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
>+#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
>+#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
>+#define MMEA0_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
>+//MMEA0_MISC2
>+#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
>+#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
>+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
>+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
>+#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
>+#define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
>+#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
>+#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
>+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
>+#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
>+#define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
>+#define MMEA0_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
>+//MMEA0_ADDRDEC_SELECT
>+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
>+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
>+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
>+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
>+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
>+#define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
>+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
>+#define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
>+//MMEA0_EDC_CNT3
>+#define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
>+#define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
>+#define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
>+#define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
>+#define MMEA0_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
>+#define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
>+#define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
>+#define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
>+#define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
>+#define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
>+#define MMEA0_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
>+#define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
>+
>+
>+// addressBlock: mmhub_ea_mmeadec1
>+//MMEA1_DRAM_RD_CLI2GRP_MAP0
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA1_DRAM_RD_CLI2GRP_MAP1
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA1_DRAM_WR_CLI2GRP_MAP0
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA1_DRAM_WR_CLI2GRP_MAP1
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA1_DRAM_RD_GRP2VC_MAP
>+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA1_DRAM_WR_GRP2VC_MAP
>+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA1_DRAM_RD_LAZY
>+#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA1_DRAM_WR_LAZY
>+#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA1_DRAM_RD_CAM_CNTL
>+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA1_DRAM_WR_CAM_CNTL
>+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA1_DRAM_PAGE_BURST
>+#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
>+#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
>+#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
>+#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
>+#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
>+#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
>+#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
>+#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
>+//MMEA1_DRAM_RD_PRI_AGE
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA1_DRAM_WR_PRI_AGE
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA1_DRAM_RD_PRI_QUEUING
>+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA1_DRAM_WR_PRI_QUEUING
>+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA1_DRAM_RD_PRI_FIXED
>+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA1_DRAM_WR_PRI_FIXED
>+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA1_DRAM_RD_PRI_URGENCY
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA1_DRAM_WR_PRI_URGENCY
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA1_DRAM_RD_PRI_QUANT_PRI1
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA1_DRAM_RD_PRI_QUANT_PRI2
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA1_DRAM_RD_PRI_QUANT_PRI3
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA1_DRAM_WR_PRI_QUANT_PRI1
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA1_DRAM_WR_PRI_QUANT_PRI2
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA1_DRAM_WR_PRI_QUANT_PRI3
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA1_GMI_RD_CLI2GRP_MAP0
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA1_GMI_RD_CLI2GRP_MAP1
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA1_GMI_WR_CLI2GRP_MAP0
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA1_GMI_WR_CLI2GRP_MAP1
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA1_GMI_RD_GRP2VC_MAP
>+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA1_GMI_WR_GRP2VC_MAP
>+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA1_GMI_RD_LAZY
>+#define MMEA1_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA1_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA1_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA1_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA1_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA1_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA1_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA1_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA1_GMI_WR_LAZY
>+#define MMEA1_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA1_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA1_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA1_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA1_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA1_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA1_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA1_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA1_GMI_RD_CAM_CNTL
>+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA1_GMI_WR_CAM_CNTL
>+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA1_GMI_PAGE_BURST
>+#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA1_GMI_RD_PRI_AGE
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA1_GMI_WR_PRI_AGE
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA1_GMI_RD_PRI_QUEUING
>+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA1_GMI_WR_PRI_QUEUING
>+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA1_GMI_RD_PRI_FIXED
>+#define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA1_GMI_WR_PRI_FIXED
>+#define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA1_GMI_RD_PRI_URGENCY
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA1_GMI_WR_PRI_URGENCY
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA1_GMI_RD_PRI_URGENCY_MASKING
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA1_GMI_WR_PRI_URGENCY_MASKING
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA1_GMI_RD_PRI_QUANT_PRI1
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA1_GMI_RD_PRI_QUANT_PRI2
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA1_GMI_RD_PRI_QUANT_PRI3
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA1_GMI_WR_PRI_QUANT_PRI1
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA1_GMI_WR_PRI_QUANT_PRI2
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA1_GMI_WR_PRI_QUANT_PRI3
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA1_ADDRNORM_BASE_ADDR0
>+#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA1_ADDRNORM_LIMIT_ADDR0
>+#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA1_ADDRNORM_BASE_ADDR1
>+#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA1_ADDRNORM_LIMIT_ADDR1
>+#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA1_ADDRNORM_OFFSET_ADDR1
>+#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA1_ADDRNORM_BASE_ADDR2
>+#define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA1_ADDRNORM_LIMIT_ADDR2
>+#define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA1_ADDRNORM_BASE_ADDR3
>+#define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA1_ADDRNORM_LIMIT_ADDR3
>+#define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA1_ADDRNORM_OFFSET_ADDR3
>+#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA1_ADDRNORM_BASE_ADDR4
>+#define MMEA1_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA1_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA1_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA1_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA1_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA1_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA1_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA1_ADDRNORM_LIMIT_ADDR4
>+#define MMEA1_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA1_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA1_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA1_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA1_ADDRNORM_BASE_ADDR5
>+#define MMEA1_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA1_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA1_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA1_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA1_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA1_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA1_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA1_ADDRNORM_LIMIT_ADDR5
>+#define MMEA1_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA1_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA1_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA1_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA1_ADDRNORM_OFFSET_ADDR5
>+#define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA1_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA1_ADDRNORMDRAM_HOLE_CNTL
>+#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
>+#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
>+#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
>+#define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
>+//MMEA1_ADDRNORMGMI_HOLE_CNTL
>+#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
>+#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
>+#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
>+#define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
>+//MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG
>+#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
>+#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
>+#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
>+#define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
>+//MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG
>+#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
>+#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
>+#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
>+#define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
>+//MMEA1_ADDRDEC_BANK_CFG
>+#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
>+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
>+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
>+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
>+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
>+#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
>+#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
>+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
>+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
>+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
>+#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
>+//MMEA1_ADDRDEC_MISC_CFG
>+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
>+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
>+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
>+#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
>+#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
>+#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
>+#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
>+#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
>+#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
>+#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
>+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
>+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
>+#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
>+#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
>+#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
>+#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
>+#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
>+#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
>+#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
>+#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
>+#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
>+//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA1_ADDRDECDRAM_ADDR_HASH_PC
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
>+//MMEA1_ADDRDECDRAM_ADDR_HASH_PC2
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
>+//MMEA1_ADDRDECDRAM_ADDR_HASH_CS0
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDECDRAM_ADDR_HASH_CS1
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDECDRAM_HARVEST_ENABLE
>+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
>+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
>+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
>+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
>+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
>+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
>+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
>+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
>+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
>+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
>+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
>+#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
>+//MMEA1_ADDRDECGMI_ADDR_HASH_BANK0
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA1_ADDRDECGMI_ADDR_HASH_BANK1
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA1_ADDRDECGMI_ADDR_HASH_BANK2
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA1_ADDRDECGMI_ADDR_HASH_BANK3
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA1_ADDRDECGMI_ADDR_HASH_BANK4
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA1_ADDRDECGMI_ADDR_HASH_BANK5
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA1_ADDRDECGMI_ADDR_HASH_PC
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
>+//MMEA1_ADDRDECGMI_ADDR_HASH_PC2
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
>+//MMEA1_ADDRDECGMI_ADDR_HASH_CS0
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA1_ADDRDECGMI_ADDR_HASH_CS1
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA1_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA1_ADDRDECGMI_HARVEST_ENABLE
>+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
>+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
>+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
>+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
>+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
>+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
>+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
>+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
>+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
>+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
>+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
>+#define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
>+//MMEA1_ADDRDEC0_BASE_ADDR_CS0
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDEC0_BASE_ADDR_CS1
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDEC0_BASE_ADDR_CS2
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDEC0_BASE_ADDR_CS3
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDEC0_BASE_ADDR_SECCS0
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA1_ADDRDEC0_BASE_ADDR_SECCS1
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA1_ADDRDEC0_BASE_ADDR_SECCS2
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA1_ADDRDEC0_BASE_ADDR_SECCS3
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA1_ADDRDEC0_ADDR_MASK_CS01
>+#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA1_ADDRDEC0_ADDR_MASK_CS23
>+#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA1_ADDRDEC0_ADDR_MASK_SECCS01
>+#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA1_ADDRDEC0_ADDR_MASK_SECCS23
>+#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA1_ADDRDEC0_ADDR_CFG_CS01
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA1_ADDRDEC0_ADDR_CFG_CS23
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA1_ADDRDEC0_ADDR_SEL_CS01
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA1_ADDRDEC0_ADDR_SEL_CS23
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA1_ADDRDEC0_ADDR_SEL2_CS01
>+#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA1_ADDRDEC0_ADDR_SEL2_CS23
>+#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA1_ADDRDEC0_COL_SEL_LO_CS01
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA1_ADDRDEC0_COL_SEL_LO_CS23
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA1_ADDRDEC0_COL_SEL_HI_CS01
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA1_ADDRDEC0_COL_SEL_HI_CS23
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA1_ADDRDEC0_RM_SEL_CS01
>+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA1_ADDRDEC0_RM_SEL_CS23
>+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA1_ADDRDEC0_RM_SEL_SECCS01
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA1_ADDRDEC0_RM_SEL_SECCS23
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA1_ADDRDEC1_BASE_ADDR_CS0
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDEC1_BASE_ADDR_CS1
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDEC1_BASE_ADDR_CS2
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDEC1_BASE_ADDR_CS3
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDEC1_BASE_ADDR_SECCS0
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA1_ADDRDEC1_BASE_ADDR_SECCS1
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA1_ADDRDEC1_BASE_ADDR_SECCS2
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA1_ADDRDEC1_BASE_ADDR_SECCS3
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA1_ADDRDEC1_ADDR_MASK_CS01
>+#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA1_ADDRDEC1_ADDR_MASK_CS23
>+#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA1_ADDRDEC1_ADDR_MASK_SECCS01
>+#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA1_ADDRDEC1_ADDR_MASK_SECCS23
>+#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA1_ADDRDEC1_ADDR_CFG_CS01
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA1_ADDRDEC1_ADDR_CFG_CS23
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA1_ADDRDEC1_ADDR_SEL_CS01
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA1_ADDRDEC1_ADDR_SEL_CS23
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA1_ADDRDEC1_ADDR_SEL2_CS01
>+#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA1_ADDRDEC1_ADDR_SEL2_CS23
>+#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA1_ADDRDEC1_COL_SEL_LO_CS01
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA1_ADDRDEC1_COL_SEL_LO_CS23
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA1_ADDRDEC1_COL_SEL_HI_CS01
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA1_ADDRDEC1_COL_SEL_HI_CS23
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA1_ADDRDEC1_RM_SEL_CS01
>+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA1_ADDRDEC1_RM_SEL_CS23
>+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA1_ADDRDEC1_RM_SEL_SECCS01
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA1_ADDRDEC1_RM_SEL_SECCS23
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA1_ADDRDEC2_BASE_ADDR_CS0
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDEC2_BASE_ADDR_CS1
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDEC2_BASE_ADDR_CS2
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDEC2_BASE_ADDR_CS3
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA1_ADDRDEC2_BASE_ADDR_SECCS0
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA1_ADDRDEC2_BASE_ADDR_SECCS1
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA1_ADDRDEC2_BASE_ADDR_SECCS2
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA1_ADDRDEC2_BASE_ADDR_SECCS3
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA1_ADDRDEC2_ADDR_MASK_CS01
>+#define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA1_ADDRDEC2_ADDR_MASK_CS23
>+#define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA1_ADDRDEC2_ADDR_MASK_SECCS01
>+#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA1_ADDRDEC2_ADDR_MASK_SECCS23
>+#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA1_ADDRDEC2_ADDR_CFG_CS01
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA1_ADDRDEC2_ADDR_CFG_CS23
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA1_ADDRDEC2_ADDR_SEL_CS01
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA1_ADDRDEC2_ADDR_SEL_CS23
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA1_ADDRDEC2_ADDR_SEL2_CS01
>+#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA1_ADDRDEC2_ADDR_SEL2_CS23
>+#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA1_ADDRDEC2_COL_SEL_LO_CS01
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA1_ADDRDEC2_COL_SEL_LO_CS23
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA1_ADDRDEC2_COL_SEL_HI_CS01
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA1_ADDRDEC2_COL_SEL_HI_CS23
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA1_ADDRDEC2_RM_SEL_CS01
>+#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA1_ADDRDEC2_RM_SEL_CS23
>+#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA1_ADDRDEC2_RM_SEL_SECCS01
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA1_ADDRDEC2_RM_SEL_SECCS23
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA1_ADDRNORMDRAM_GLOBAL_CNTL
>+#define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
>+#define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
>+#define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
>+#define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
>+#define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
>+#define MMEA1_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
>+//MMEA1_ADDRNORMGMI_GLOBAL_CNTL
>+#define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
>+#define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
>+#define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
>+#define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
>+#define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
>+#define MMEA1_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
>+//MMEA1_IO_RD_CLI2GRP_MAP0
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA1_IO_RD_CLI2GRP_MAP1
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA1_IO_WR_CLI2GRP_MAP0
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA1_IO_WR_CLI2GRP_MAP1
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA1_IO_RD_COMBINE_FLUSH
>+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA1_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA1_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA1_IO_WR_COMBINE_FLUSH
>+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA1_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA1_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA1_IO_GROUP_BURST
>+#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA1_IO_RD_PRI_AGE
>+#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA1_IO_WR_PRI_AGE
>+#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA1_IO_RD_PRI_QUEUING
>+#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA1_IO_WR_PRI_QUEUING
>+#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA1_IO_RD_PRI_FIXED
>+#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA1_IO_WR_PRI_FIXED
>+#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA1_IO_RD_PRI_URGENCY
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA1_IO_WR_PRI_URGENCY
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA1_IO_RD_PRI_URGENCY_MASKING
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA1_IO_WR_PRI_URGENCY_MASKING
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA1_IO_RD_PRI_QUANT_PRI1
>+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA1_IO_RD_PRI_QUANT_PRI2
>+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA1_IO_RD_PRI_QUANT_PRI3
>+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA1_IO_WR_PRI_QUANT_PRI1
>+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA1_IO_WR_PRI_QUANT_PRI2
>+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA1_IO_WR_PRI_QUANT_PRI3
>+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA1_SDP_ARB_DRAM
>+#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
>+#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
>+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
>+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
>+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
>+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
>+#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
>+#define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
>+#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
>+#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
>+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
>+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
>+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
>+#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
>+#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
>+#define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
>+//MMEA1_SDP_ARB_GMI
>+#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
>+#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
>+#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
>+#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
>+#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
>+#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
>+#define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
>+#define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
>+#define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
>+#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
>+#define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
>+#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
>+#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
>+#define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
>+#define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
>+#define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
>+#define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
>+#define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
>+//MMEA1_SDP_ARB_FINAL
>+#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
>+#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
>+#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
>+#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
>+#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
>+#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
>+#define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
>+#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
>+#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
>+#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
>+#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
>+#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
>+#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
>+#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
>+#define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
>+//MMEA1_SDP_DRAM_PRIORITY
>+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
>+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
>+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
>+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
>+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
>+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
>+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
>+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
>+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
>+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
>+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
>+#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
>+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
>+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
>+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
>+#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
>+//MMEA1_SDP_GMI_PRIORITY
>+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
>+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
>+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
>+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
>+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
>+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
>+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
>+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
>+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
>+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
>+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
>+#define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
>+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
>+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
>+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
>+#define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
>+//MMEA1_SDP_IO_PRIORITY
>+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
>+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
>+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
>+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
>+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
>+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
>+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
>+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
>+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
>+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
>+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
>+#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
>+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
>+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
>+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
>+#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
>+//MMEA1_SDP_CREDITS
>+#define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
>+#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
>+#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
>+#define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
>+#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
>+#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
>+//MMEA1_SDP_TAG_RESERVE0
>+#define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
>+#define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
>+#define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
>+#define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
>+#define MMEA1_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
>+#define MMEA1_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
>+#define MMEA1_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
>+#define MMEA1_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
>+//MMEA1_SDP_TAG_RESERVE1
>+#define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
>+#define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
>+#define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
>+#define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
>+#define MMEA1_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
>+#define MMEA1_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
>+#define MMEA1_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
>+#define MMEA1_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
>+//MMEA1_SDP_VCC_RESERVE0
>+#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA1_SDP_VCC_RESERVE1
>+#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA1_SDP_VCD_RESERVE0
>+#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA1_SDP_VCD_RESERVE1
>+#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA1_SDP_REQ_CNTL
>+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
>+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
>+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
>+#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
>+#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
>+#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
>+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
>+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
>+#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
>+#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
>+#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
>+#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
>+//MMEA1_MISC
>+#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
>+#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
>+#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
>+#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
>+#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
>+#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
>+#define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
>+#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
>+#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
>+#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
>+#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
>+#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
>+#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
>+#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
>+#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
>+#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
>+#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
>+#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
>+#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
>+#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
>+#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
>+#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
>+#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
>+#define MMEA1_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
>+#define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
>+#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
>+#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
>+#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
>+#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
>+#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
>+#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
>+#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
>+#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
>+#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
>+#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
>+//MMEA1_LATENCY_SAMPLING
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
>+#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
>+//MMEA1_PERFCOUNTER_LO
>+#define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//MMEA1_PERFCOUNTER_HI
>+#define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//MMEA1_PERFCOUNTER0_CFG
>+#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA1_PERFCOUNTER1_CFG
>+#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA1_PERFCOUNTER_RSLT_CNTL
>+#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//MMEA1_EDC_CNT
>+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
>+#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
>+#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
>+#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
>+#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
>+#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
>+#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
>+#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
>+#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
>+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
>+#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
>+#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
>+#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
>+#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
>+#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
>+#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
>+#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
>+#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
>+//MMEA1_EDC_CNT2
>+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
>+#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
>+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
>+#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
>+//MMEA1_DSM_CNTL
>+#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
>+#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
>+#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
>+#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
>+#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
>+#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
>+#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
>+#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
>+#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
>+#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
>+#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
>+#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
>+#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
>+#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
>+#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
>+#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
>+#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
>+#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
>+#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
>+#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
>+#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
>+#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
>+#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
>+#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
>+#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
>+#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
>+#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
>+#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
>+#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
>+#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
>+#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
>+#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
>+//MMEA1_DSM_CNTLA
>+#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
>+#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
>+#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
>+#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
>+#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
>+#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
>+#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
>+#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
>+#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
>+#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
>+#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
>+#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
>+#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
>+#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
>+#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
>+#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
>+#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
>+#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
>+#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
>+#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
>+#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
>+#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
>+#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
>+#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
>+#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
>+#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
>+#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
>+#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
>+//MMEA1_DSM_CNTL2
>+#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
>+#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
>+#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
>+#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
>+#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
>+#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
>+#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
>+#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
>+#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
>+#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
>+#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
>+#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
>+#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
>+#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
>+#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
>+#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
>+#define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
>+#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
>+#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
>+#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
>+#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
>+#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
>+#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
>+#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
>+#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
>+#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
>+#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
>+#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
>+#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
>+#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
>+#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
>+#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
>+#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
>+#define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
>+//MMEA1_DSM_CNTL2A
>+#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
>+#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
>+#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
>+#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
>+#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
>+#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
>+#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
>+#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
>+#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
>+#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
>+#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
>+#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
>+#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
>+#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
>+#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
>+#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
>+#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
>+#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
>+#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
>+#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
>+#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
>+#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
>+#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
>+#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
>+#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
>+#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
>+#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
>+#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
>+//MMEA1_CGTT_CLK_CTRL
>+#define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
>+#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
>+#define MMEA1_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
>+#define MMEA1_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
>+#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
>+#define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
>+#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
>+#define MMEA1_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
>+#define MMEA1_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
>+#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
>+#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
>+//MMEA1_EDC_MODE
>+#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
>+#define MMEA1_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
>+#define MMEA1_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
>+#define MMEA1_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
>+#define MMEA1_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
>+#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
>+#define MMEA1_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
>+#define MMEA1_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
>+#define MMEA1_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
>+#define MMEA1_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
>+//MMEA1_ERR_STATUS
>+#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
>+#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
>+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
>+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
>+#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
>+#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
>+#define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
>+#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
>+#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
>+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
>+#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
>+#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
>+#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
>+#define MMEA1_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
>+//MMEA1_MISC2
>+#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
>+#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
>+#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
>+#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
>+#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
>+#define MMEA1_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
>+#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
>+#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
>+#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
>+#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
>+#define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
>+#define MMEA1_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
>+//MMEA1_ADDRDEC_SELECT
>+#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
>+#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
>+#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
>+#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
>+#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
>+#define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
>+#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
>+#define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
>+//MMEA1_EDC_CNT3
>+#define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
>+#define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
>+#define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
>+#define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
>+#define MMEA1_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
>+#define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
>+#define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
>+#define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
>+#define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
>+#define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
>+#define MMEA1_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
>+#define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
>+
>+
>+// addressBlock: mmhub_ea_mmeadec2
>+//MMEA2_DRAM_RD_CLI2GRP_MAP0
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA2_DRAM_RD_CLI2GRP_MAP1
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA2_DRAM_WR_CLI2GRP_MAP0
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA2_DRAM_WR_CLI2GRP_MAP1
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA2_DRAM_RD_GRP2VC_MAP
>+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA2_DRAM_WR_GRP2VC_MAP
>+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA2_DRAM_RD_LAZY
>+#define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA2_DRAM_WR_LAZY
>+#define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA2_DRAM_RD_CAM_CNTL
>+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA2_DRAM_WR_CAM_CNTL
>+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA2_DRAM_PAGE_BURST
>+#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
>+#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
>+#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
>+#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
>+#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
>+#define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
>+#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
>+#define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
>+//MMEA2_DRAM_RD_PRI_AGE
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA2_DRAM_WR_PRI_AGE
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA2_DRAM_RD_PRI_QUEUING
>+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA2_DRAM_WR_PRI_QUEUING
>+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA2_DRAM_RD_PRI_FIXED
>+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA2_DRAM_WR_PRI_FIXED
>+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA2_DRAM_RD_PRI_URGENCY
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA2_DRAM_WR_PRI_URGENCY
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA2_DRAM_RD_PRI_QUANT_PRI1
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA2_DRAM_RD_PRI_QUANT_PRI2
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA2_DRAM_RD_PRI_QUANT_PRI3
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA2_DRAM_WR_PRI_QUANT_PRI1
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA2_DRAM_WR_PRI_QUANT_PRI2
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA2_DRAM_WR_PRI_QUANT_PRI3
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA2_GMI_RD_CLI2GRP_MAP0
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA2_GMI_RD_CLI2GRP_MAP1
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA2_GMI_WR_CLI2GRP_MAP0
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA2_GMI_WR_CLI2GRP_MAP1
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA2_GMI_RD_GRP2VC_MAP
>+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA2_GMI_WR_GRP2VC_MAP
>+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA2_GMI_RD_LAZY
>+#define MMEA2_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA2_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA2_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA2_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA2_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA2_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA2_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA2_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA2_GMI_WR_LAZY
>+#define MMEA2_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA2_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA2_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA2_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA2_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA2_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA2_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA2_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA2_GMI_RD_CAM_CNTL
>+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA2_GMI_WR_CAM_CNTL
>+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA2_GMI_PAGE_BURST
>+#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA2_GMI_RD_PRI_AGE
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA2_GMI_WR_PRI_AGE
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA2_GMI_RD_PRI_QUEUING
>+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA2_GMI_WR_PRI_QUEUING
>+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA2_GMI_RD_PRI_FIXED
>+#define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA2_GMI_WR_PRI_FIXED
>+#define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA2_GMI_RD_PRI_URGENCY
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA2_GMI_WR_PRI_URGENCY
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA2_GMI_RD_PRI_URGENCY_MASKING
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA2_GMI_WR_PRI_URGENCY_MASKING
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA2_GMI_RD_PRI_QUANT_PRI1
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA2_GMI_RD_PRI_QUANT_PRI2
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA2_GMI_RD_PRI_QUANT_PRI3
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA2_GMI_WR_PRI_QUANT_PRI1
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA2_GMI_WR_PRI_QUANT_PRI2
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA2_GMI_WR_PRI_QUANT_PRI3
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA2_ADDRNORM_BASE_ADDR0
>+#define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA2_ADDRNORM_LIMIT_ADDR0
>+#define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA2_ADDRNORM_BASE_ADDR1
>+#define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA2_ADDRNORM_LIMIT_ADDR1
>+#define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA2_ADDRNORM_OFFSET_ADDR1
>+#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA2_ADDRNORM_BASE_ADDR2
>+#define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA2_ADDRNORM_LIMIT_ADDR2
>+#define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA2_ADDRNORM_BASE_ADDR3
>+#define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA2_ADDRNORM_LIMIT_ADDR3
>+#define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA2_ADDRNORM_OFFSET_ADDR3
>+#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA2_ADDRNORM_BASE_ADDR4
>+#define MMEA2_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA2_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA2_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA2_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA2_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA2_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA2_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA2_ADDRNORM_LIMIT_ADDR4
>+#define MMEA2_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA2_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA2_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA2_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA2_ADDRNORM_BASE_ADDR5
>+#define MMEA2_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA2_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA2_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA2_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA2_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA2_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA2_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA2_ADDRNORM_LIMIT_ADDR5
>+#define MMEA2_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA2_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA2_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA2_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA2_ADDRNORM_OFFSET_ADDR5
>+#define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA2_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA2_ADDRNORMDRAM_HOLE_CNTL
>+#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
>+#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
>+#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
>+#define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
>+//MMEA2_ADDRNORMGMI_HOLE_CNTL
>+#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
>+#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
>+#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
>+#define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
>+//MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG
>+#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
>+#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
>+#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
>+#define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
>+//MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG
>+#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
>+#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
>+#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
>+#define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
>+//MMEA2_ADDRDEC_BANK_CFG
>+#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
>+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
>+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
>+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
>+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
>+#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
>+#define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
>+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
>+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
>+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
>+#define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
>+//MMEA2_ADDRDEC_MISC_CFG
>+#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
>+#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
>+#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
>+#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
>+#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
>+#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
>+#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
>+#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
>+#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
>+#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
>+#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
>+#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
>+#define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
>+#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
>+#define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
>+#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
>+#define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
>+#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
>+#define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
>+#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
>+#define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
>+//MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA2_ADDRDECDRAM_ADDR_HASH_PC
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
>+//MMEA2_ADDRDECDRAM_ADDR_HASH_PC2
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
>+//MMEA2_ADDRDECDRAM_ADDR_HASH_CS0
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDECDRAM_ADDR_HASH_CS1
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA2_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDECDRAM_HARVEST_ENABLE
>+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
>+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
>+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
>+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
>+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
>+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
>+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
>+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
>+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
>+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
>+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
>+#define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
>+//MMEA2_ADDRDECGMI_ADDR_HASH_BANK0
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA2_ADDRDECGMI_ADDR_HASH_BANK1
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA2_ADDRDECGMI_ADDR_HASH_BANK2
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA2_ADDRDECGMI_ADDR_HASH_BANK3
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA2_ADDRDECGMI_ADDR_HASH_BANK4
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA2_ADDRDECGMI_ADDR_HASH_BANK5
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA2_ADDRDECGMI_ADDR_HASH_PC
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
>+//MMEA2_ADDRDECGMI_ADDR_HASH_PC2
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
>+//MMEA2_ADDRDECGMI_ADDR_HASH_CS0
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA2_ADDRDECGMI_ADDR_HASH_CS1
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA2_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA2_ADDRDECGMI_HARVEST_ENABLE
>+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
>+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
>+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
>+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
>+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
>+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
>+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
>+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
>+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
>+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
>+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
>+#define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
>+//MMEA2_ADDRDEC0_BASE_ADDR_CS0
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDEC0_BASE_ADDR_CS1
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDEC0_BASE_ADDR_CS2
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDEC0_BASE_ADDR_CS3
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDEC0_BASE_ADDR_SECCS0
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA2_ADDRDEC0_BASE_ADDR_SECCS1
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA2_ADDRDEC0_BASE_ADDR_SECCS2
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA2_ADDRDEC0_BASE_ADDR_SECCS3
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA2_ADDRDEC0_ADDR_MASK_CS01
>+#define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA2_ADDRDEC0_ADDR_MASK_CS23
>+#define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA2_ADDRDEC0_ADDR_MASK_SECCS01
>+#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA2_ADDRDEC0_ADDR_MASK_SECCS23
>+#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA2_ADDRDEC0_ADDR_CFG_CS01
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA2_ADDRDEC0_ADDR_CFG_CS23
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA2_ADDRDEC0_ADDR_SEL_CS01
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA2_ADDRDEC0_ADDR_SEL_CS23
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA2_ADDRDEC0_ADDR_SEL2_CS01
>+#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA2_ADDRDEC0_ADDR_SEL2_CS23
>+#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA2_ADDRDEC0_COL_SEL_LO_CS01
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA2_ADDRDEC0_COL_SEL_LO_CS23
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA2_ADDRDEC0_COL_SEL_HI_CS01
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA2_ADDRDEC0_COL_SEL_HI_CS23
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA2_ADDRDEC0_RM_SEL_CS01
>+#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA2_ADDRDEC0_RM_SEL_CS23
>+#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA2_ADDRDEC0_RM_SEL_SECCS01
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA2_ADDRDEC0_RM_SEL_SECCS23
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA2_ADDRDEC1_BASE_ADDR_CS0
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDEC1_BASE_ADDR_CS1
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDEC1_BASE_ADDR_CS2
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDEC1_BASE_ADDR_CS3
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDEC1_BASE_ADDR_SECCS0
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA2_ADDRDEC1_BASE_ADDR_SECCS1
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA2_ADDRDEC1_BASE_ADDR_SECCS2
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA2_ADDRDEC1_BASE_ADDR_SECCS3
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA2_ADDRDEC1_ADDR_MASK_CS01
>+#define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA2_ADDRDEC1_ADDR_MASK_CS23
>+#define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA2_ADDRDEC1_ADDR_MASK_SECCS01
>+#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA2_ADDRDEC1_ADDR_MASK_SECCS23
>+#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA2_ADDRDEC1_ADDR_CFG_CS01
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA2_ADDRDEC1_ADDR_CFG_CS23
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA2_ADDRDEC1_ADDR_SEL_CS01
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA2_ADDRDEC1_ADDR_SEL_CS23
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA2_ADDRDEC1_ADDR_SEL2_CS01
>+#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA2_ADDRDEC1_ADDR_SEL2_CS23
>+#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA2_ADDRDEC1_COL_SEL_LO_CS01
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA2_ADDRDEC1_COL_SEL_LO_CS23
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA2_ADDRDEC1_COL_SEL_HI_CS01
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA2_ADDRDEC1_COL_SEL_HI_CS23
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA2_ADDRDEC1_RM_SEL_CS01
>+#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA2_ADDRDEC1_RM_SEL_CS23
>+#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA2_ADDRDEC1_RM_SEL_SECCS01
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA2_ADDRDEC1_RM_SEL_SECCS23
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA2_ADDRDEC2_BASE_ADDR_CS0
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDEC2_BASE_ADDR_CS1
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDEC2_BASE_ADDR_CS2
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDEC2_BASE_ADDR_CS3
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA2_ADDRDEC2_BASE_ADDR_SECCS0
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA2_ADDRDEC2_BASE_ADDR_SECCS1
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA2_ADDRDEC2_BASE_ADDR_SECCS2
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA2_ADDRDEC2_BASE_ADDR_SECCS3
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA2_ADDRDEC2_ADDR_MASK_CS01
>+#define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA2_ADDRDEC2_ADDR_MASK_CS23
>+#define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA2_ADDRDEC2_ADDR_MASK_SECCS01
>+#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA2_ADDRDEC2_ADDR_MASK_SECCS23
>+#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA2_ADDRDEC2_ADDR_CFG_CS01
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA2_ADDRDEC2_ADDR_CFG_CS23
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA2_ADDRDEC2_ADDR_SEL_CS01
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA2_ADDRDEC2_ADDR_SEL_CS23
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA2_ADDRDEC2_ADDR_SEL2_CS01
>+#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA2_ADDRDEC2_ADDR_SEL2_CS23
>+#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA2_ADDRDEC2_COL_SEL_LO_CS01
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA2_ADDRDEC2_COL_SEL_LO_CS23
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA2_ADDRDEC2_COL_SEL_HI_CS01
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA2_ADDRDEC2_COL_SEL_HI_CS23
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA2_ADDRDEC2_RM_SEL_CS01
>+#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA2_ADDRDEC2_RM_SEL_CS23
>+#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA2_ADDRDEC2_RM_SEL_SECCS01
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA2_ADDRDEC2_RM_SEL_SECCS23
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA2_ADDRNORMDRAM_GLOBAL_CNTL
>+#define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
>+#define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
>+#define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
>+#define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
>+#define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
>+#define MMEA2_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
>+//MMEA2_ADDRNORMGMI_GLOBAL_CNTL
>+#define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
>+#define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
>+#define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
>+#define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
>+#define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
>+#define MMEA2_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
>+//MMEA2_IO_RD_CLI2GRP_MAP0
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA2_IO_RD_CLI2GRP_MAP1
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA2_IO_WR_CLI2GRP_MAP0
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA2_IO_WR_CLI2GRP_MAP1
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA2_IO_RD_COMBINE_FLUSH
>+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA2_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA2_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA2_IO_WR_COMBINE_FLUSH
>+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA2_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA2_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA2_IO_GROUP_BURST
>+#define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA2_IO_RD_PRI_AGE
>+#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA2_IO_WR_PRI_AGE
>+#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA2_IO_RD_PRI_QUEUING
>+#define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA2_IO_WR_PRI_QUEUING
>+#define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA2_IO_RD_PRI_FIXED
>+#define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA2_IO_WR_PRI_FIXED
>+#define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA2_IO_RD_PRI_URGENCY
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA2_IO_WR_PRI_URGENCY
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA2_IO_RD_PRI_URGENCY_MASKING
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA2_IO_WR_PRI_URGENCY_MASKING
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA2_IO_RD_PRI_QUANT_PRI1
>+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA2_IO_RD_PRI_QUANT_PRI2
>+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA2_IO_RD_PRI_QUANT_PRI3
>+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA2_IO_WR_PRI_QUANT_PRI1
>+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA2_IO_WR_PRI_QUANT_PRI2
>+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA2_IO_WR_PRI_QUANT_PRI3
>+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA2_SDP_ARB_DRAM
>+#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
>+#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
>+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
>+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
>+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
>+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
>+#define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
>+#define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
>+#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
>+#define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
>+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
>+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
>+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
>+#define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
>+#define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
>+#define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
>+//MMEA2_SDP_ARB_GMI
>+#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
>+#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
>+#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
>+#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
>+#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
>+#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
>+#define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
>+#define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
>+#define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
>+#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
>+#define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
>+#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
>+#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
>+#define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
>+#define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
>+#define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
>+#define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
>+#define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
>+//MMEA2_SDP_ARB_FINAL
>+#define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
>+#define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
>+#define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
>+#define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
>+#define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
>+#define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
>+#define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
>+#define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
>+#define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
>+#define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
>+#define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
>+#define MMEA2_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
>+#define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
>+#define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
>+#define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
>+//MMEA2_SDP_DRAM_PRIORITY
>+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
>+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
>+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
>+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
>+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
>+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
>+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
>+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
>+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
>+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
>+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
>+#define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
>+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
>+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
>+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
>+#define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
>+//MMEA2_SDP_GMI_PRIORITY
>+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
>+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
>+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
>+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
>+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
>+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
>+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
>+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
>+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
>+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
>+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
>+#define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
>+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
>+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
>+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
>+#define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
>+//MMEA2_SDP_IO_PRIORITY
>+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
>+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
>+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
>+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
>+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
>+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
>+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
>+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
>+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
>+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
>+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
>+#define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
>+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
>+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
>+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
>+#define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
>+//MMEA2_SDP_CREDITS
>+#define MMEA2_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
>+#define MMEA2_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
>+#define MMEA2_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
>+#define MMEA2_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
>+#define MMEA2_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
>+#define MMEA2_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
>+//MMEA2_SDP_TAG_RESERVE0
>+#define MMEA2_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
>+#define MMEA2_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
>+#define MMEA2_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
>+#define MMEA2_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
>+#define MMEA2_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
>+#define MMEA2_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
>+#define MMEA2_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
>+#define MMEA2_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
>+//MMEA2_SDP_TAG_RESERVE1
>+#define MMEA2_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
>+#define MMEA2_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
>+#define MMEA2_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
>+#define MMEA2_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
>+#define MMEA2_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
>+#define MMEA2_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
>+#define MMEA2_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
>+#define MMEA2_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
>+//MMEA2_SDP_VCC_RESERVE0
>+#define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA2_SDP_VCC_RESERVE1
>+#define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA2_SDP_VCD_RESERVE0
>+#define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA2_SDP_VCD_RESERVE1
>+#define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA2_SDP_REQ_CNTL
>+#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
>+#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
>+#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
>+#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
>+#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
>+#define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
>+#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
>+#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
>+#define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
>+#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
>+#define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
>+#define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
>+//MMEA2_MISC
>+#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
>+#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
>+#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
>+#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
>+#define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
>+#define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
>+#define MMEA2_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
>+#define MMEA2_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
>+#define MMEA2_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
>+#define MMEA2_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
>+#define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
>+#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
>+#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
>+#define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
>+#define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
>+#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
>+#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
>+#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
>+#define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
>+#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
>+#define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
>+#define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
>+#define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
>+#define MMEA2_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
>+#define MMEA2_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
>+#define MMEA2_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
>+#define MMEA2_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
>+#define MMEA2_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
>+#define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
>+#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
>+#define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
>+#define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
>+#define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
>+#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
>+#define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
>+//MMEA2_LATENCY_SAMPLING
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
>+#define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
>+//MMEA2_PERFCOUNTER_LO
>+#define MMEA2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define MMEA2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//MMEA2_PERFCOUNTER_HI
>+#define MMEA2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define MMEA2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//MMEA2_PERFCOUNTER0_CFG
>+#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA2_PERFCOUNTER1_CFG
>+#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA2_PERFCOUNTER_RSLT_CNTL
>+#define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//MMEA2_EDC_CNT
>+#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
>+#define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
>+#define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
>+#define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
>+#define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
>+#define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
>+#define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
>+#define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
>+#define MMEA2_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
>+#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
>+#define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
>+#define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
>+#define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
>+#define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
>+#define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
>+#define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
>+#define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
>+#define MMEA2_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
>+//MMEA2_EDC_CNT2
>+#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
>+#define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
>+#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
>+#define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
>+//MMEA2_DSM_CNTL
>+#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
>+#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
>+#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
>+#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
>+#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
>+#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
>+#define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
>+#define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
>+#define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
>+#define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
>+#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
>+#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
>+#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
>+#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
>+#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
>+#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
>+#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
>+#define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
>+#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
>+#define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
>+#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
>+#define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
>+#define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
>+#define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
>+#define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
>+#define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
>+#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
>+#define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
>+#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
>+#define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
>+#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
>+#define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
>+//MMEA2_DSM_CNTLA
>+#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
>+#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
>+#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
>+#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
>+#define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
>+#define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
>+#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
>+#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
>+#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
>+#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
>+#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
>+#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
>+#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
>+#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
>+#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
>+#define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
>+#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
>+#define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
>+#define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
>+#define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
>+#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
>+#define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
>+#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
>+#define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
>+#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
>+#define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
>+#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
>+#define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
>+//MMEA2_DSM_CNTL2
>+#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
>+#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
>+#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
>+#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
>+#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
>+#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
>+#define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
>+#define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
>+#define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
>+#define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
>+#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
>+#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
>+#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
>+#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
>+#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
>+#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
>+#define MMEA2_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
>+#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
>+#define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
>+#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
>+#define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
>+#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
>+#define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
>+#define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
>+#define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
>+#define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
>+#define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
>+#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
>+#define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
>+#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
>+#define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
>+#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
>+#define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
>+#define MMEA2_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
>+//MMEA2_DSM_CNTL2A
>+#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
>+#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
>+#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
>+#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
>+#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
>+#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
>+#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
>+#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
>+#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
>+#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
>+#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
>+#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
>+#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
>+#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
>+#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
>+#define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
>+#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
>+#define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
>+#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
>+#define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
>+#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
>+#define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
>+#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
>+#define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
>+#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
>+#define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
>+#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
>+#define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
>+//MMEA2_CGTT_CLK_CTRL
>+#define MMEA2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
>+#define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
>+#define MMEA2_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
>+#define MMEA2_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
>+#define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
>+#define MMEA2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
>+#define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
>+#define MMEA2_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
>+#define MMEA2_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
>+#define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
>+#define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
>+//MMEA2_EDC_MODE
>+#define MMEA2_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
>+#define MMEA2_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
>+#define MMEA2_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
>+#define MMEA2_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
>+#define MMEA2_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
>+#define MMEA2_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
>+#define MMEA2_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
>+#define MMEA2_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
>+#define MMEA2_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
>+#define MMEA2_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
>+//MMEA2_ERR_STATUS
>+#define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
>+#define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
>+#define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
>+#define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
>+#define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
>+#define MMEA2_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
>+#define MMEA2_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
>+#define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
>+#define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
>+#define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
>+#define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
>+#define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
>+#define MMEA2_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
>+#define MMEA2_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
>+//MMEA2_MISC2
>+#define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
>+#define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
>+#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
>+#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
>+#define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
>+#define MMEA2_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
>+#define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
>+#define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
>+#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
>+#define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
>+#define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
>+#define MMEA2_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
>+//MMEA2_ADDRDEC_SELECT
>+#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
>+#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
>+#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
>+#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
>+#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
>+#define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
>+#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
>+#define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
>+//MMEA2_EDC_CNT3
>+#define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
>+#define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
>+#define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
>+#define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
>+#define MMEA2_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
>+#define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
>+#define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
>+#define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
>+#define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
>+#define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
>+#define MMEA2_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
>+#define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
>+
>+
>+// addressBlock: mmhub_ea_mmeadec3
>+//MMEA3_DRAM_RD_CLI2GRP_MAP0
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA3_DRAM_RD_CLI2GRP_MAP1
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA3_DRAM_WR_CLI2GRP_MAP0
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA3_DRAM_WR_CLI2GRP_MAP1
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA3_DRAM_RD_GRP2VC_MAP
>+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA3_DRAM_WR_GRP2VC_MAP
>+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA3_DRAM_RD_LAZY
>+#define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA3_DRAM_WR_LAZY
>+#define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA3_DRAM_RD_CAM_CNTL
>+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA3_DRAM_WR_CAM_CNTL
>+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA3_DRAM_PAGE_BURST
>+#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
>+#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
>+#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
>+#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
>+#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
>+#define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
>+#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
>+#define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
>+//MMEA3_DRAM_RD_PRI_AGE
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA3_DRAM_WR_PRI_AGE
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA3_DRAM_RD_PRI_QUEUING
>+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA3_DRAM_WR_PRI_QUEUING
>+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA3_DRAM_RD_PRI_FIXED
>+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA3_DRAM_WR_PRI_FIXED
>+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA3_DRAM_RD_PRI_URGENCY
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA3_DRAM_WR_PRI_URGENCY
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA3_DRAM_RD_PRI_QUANT_PRI1
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA3_DRAM_RD_PRI_QUANT_PRI2
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA3_DRAM_RD_PRI_QUANT_PRI3
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA3_DRAM_WR_PRI_QUANT_PRI1
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA3_DRAM_WR_PRI_QUANT_PRI2
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA3_DRAM_WR_PRI_QUANT_PRI3
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA3_GMI_RD_CLI2GRP_MAP0
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA3_GMI_RD_CLI2GRP_MAP1
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA3_GMI_WR_CLI2GRP_MAP0
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA3_GMI_WR_CLI2GRP_MAP1
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA3_GMI_RD_GRP2VC_MAP
>+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA3_GMI_WR_GRP2VC_MAP
>+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA3_GMI_RD_LAZY
>+#define MMEA3_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA3_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA3_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA3_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA3_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA3_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA3_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA3_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA3_GMI_WR_LAZY
>+#define MMEA3_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA3_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA3_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA3_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA3_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA3_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA3_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA3_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA3_GMI_RD_CAM_CNTL
>+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA3_GMI_WR_CAM_CNTL
>+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA3_GMI_PAGE_BURST
>+#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA3_GMI_RD_PRI_AGE
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA3_GMI_WR_PRI_AGE
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA3_GMI_RD_PRI_QUEUING
>+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA3_GMI_WR_PRI_QUEUING
>+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA3_GMI_RD_PRI_FIXED
>+#define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA3_GMI_WR_PRI_FIXED
>+#define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA3_GMI_RD_PRI_URGENCY
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA3_GMI_WR_PRI_URGENCY
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA3_GMI_RD_PRI_URGENCY_MASKING
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA3_GMI_WR_PRI_URGENCY_MASKING
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA3_GMI_RD_PRI_QUANT_PRI1
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA3_GMI_RD_PRI_QUANT_PRI2
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA3_GMI_RD_PRI_QUANT_PRI3
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA3_GMI_WR_PRI_QUANT_PRI1
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA3_GMI_WR_PRI_QUANT_PRI2
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA3_GMI_WR_PRI_QUANT_PRI3
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA3_ADDRNORM_BASE_ADDR0
>+#define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA3_ADDRNORM_LIMIT_ADDR0
>+#define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA3_ADDRNORM_BASE_ADDR1
>+#define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA3_ADDRNORM_LIMIT_ADDR1
>+#define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA3_ADDRNORM_OFFSET_ADDR1
>+#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA3_ADDRNORM_BASE_ADDR2
>+#define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA3_ADDRNORM_LIMIT_ADDR2
>+#define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA3_ADDRNORM_BASE_ADDR3
>+#define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA3_ADDRNORM_LIMIT_ADDR3
>+#define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA3_ADDRNORM_OFFSET_ADDR3
>+#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA3_ADDRNORM_BASE_ADDR4
>+#define MMEA3_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA3_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA3_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA3_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA3_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA3_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA3_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA3_ADDRNORM_LIMIT_ADDR4
>+#define MMEA3_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA3_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA3_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA3_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA3_ADDRNORM_BASE_ADDR5
>+#define MMEA3_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA3_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA3_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA3_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA3_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA3_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA3_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA3_ADDRNORM_LIMIT_ADDR5
>+#define MMEA3_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA3_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA3_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA3_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA3_ADDRNORM_OFFSET_ADDR5
>+#define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA3_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA3_ADDRNORMDRAM_HOLE_CNTL
>+#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
>+#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
>+#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
>+#define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
>+//MMEA3_ADDRNORMGMI_HOLE_CNTL
>+#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
>+#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
>+#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
>+#define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
>+//MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG
>+#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
>+#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
>+#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
>+#define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
>+//MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG
>+#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
>+#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
>+#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
>+#define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
>+//MMEA3_ADDRDEC_BANK_CFG
>+#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
>+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
>+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
>+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
>+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
>+#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
>+#define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
>+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
>+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
>+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
>+#define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
>+//MMEA3_ADDRDEC_MISC_CFG
>+#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
>+#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
>+#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
>+#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
>+#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
>+#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
>+#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
>+#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
>+#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
>+#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
>+#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
>+#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
>+#define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
>+#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
>+#define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
>+#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
>+#define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
>+#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
>+#define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
>+#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
>+#define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
>+//MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA3_ADDRDECDRAM_ADDR_HASH_PC
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
>+//MMEA3_ADDRDECDRAM_ADDR_HASH_PC2
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
>+//MMEA3_ADDRDECDRAM_ADDR_HASH_CS0
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDECDRAM_ADDR_HASH_CS1
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA3_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDECDRAM_HARVEST_ENABLE
>+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
>+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
>+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
>+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
>+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
>+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
>+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
>+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
>+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
>+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
>+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
>+#define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
>+//MMEA3_ADDRDECGMI_ADDR_HASH_BANK0
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA3_ADDRDECGMI_ADDR_HASH_BANK1
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA3_ADDRDECGMI_ADDR_HASH_BANK2
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA3_ADDRDECGMI_ADDR_HASH_BANK3
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA3_ADDRDECGMI_ADDR_HASH_BANK4
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA3_ADDRDECGMI_ADDR_HASH_BANK5
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA3_ADDRDECGMI_ADDR_HASH_PC
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
>+//MMEA3_ADDRDECGMI_ADDR_HASH_PC2
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
>+//MMEA3_ADDRDECGMI_ADDR_HASH_CS0
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA3_ADDRDECGMI_ADDR_HASH_CS1
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA3_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA3_ADDRDECGMI_HARVEST_ENABLE
>+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
>+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
>+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
>+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
>+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
>+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
>+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
>+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
>+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
>+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
>+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
>+#define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
>+//MMEA3_ADDRDEC0_BASE_ADDR_CS0
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDEC0_BASE_ADDR_CS1
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDEC0_BASE_ADDR_CS2
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDEC0_BASE_ADDR_CS3
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDEC0_BASE_ADDR_SECCS0
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA3_ADDRDEC0_BASE_ADDR_SECCS1
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA3_ADDRDEC0_BASE_ADDR_SECCS2
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA3_ADDRDEC0_BASE_ADDR_SECCS3
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA3_ADDRDEC0_ADDR_MASK_CS01
>+#define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA3_ADDRDEC0_ADDR_MASK_CS23
>+#define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA3_ADDRDEC0_ADDR_MASK_SECCS01
>+#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA3_ADDRDEC0_ADDR_MASK_SECCS23
>+#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA3_ADDRDEC0_ADDR_CFG_CS01
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA3_ADDRDEC0_ADDR_CFG_CS23
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA3_ADDRDEC0_ADDR_SEL_CS01
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA3_ADDRDEC0_ADDR_SEL_CS23
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA3_ADDRDEC0_ADDR_SEL2_CS01
>+#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA3_ADDRDEC0_ADDR_SEL2_CS23
>+#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA3_ADDRDEC0_COL_SEL_LO_CS01
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA3_ADDRDEC0_COL_SEL_LO_CS23
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA3_ADDRDEC0_COL_SEL_HI_CS01
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA3_ADDRDEC0_COL_SEL_HI_CS23
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA3_ADDRDEC0_RM_SEL_CS01
>+#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA3_ADDRDEC0_RM_SEL_CS23
>+#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA3_ADDRDEC0_RM_SEL_SECCS01
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA3_ADDRDEC0_RM_SEL_SECCS23
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA3_ADDRDEC1_BASE_ADDR_CS0
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDEC1_BASE_ADDR_CS1
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDEC1_BASE_ADDR_CS2
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDEC1_BASE_ADDR_CS3
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDEC1_BASE_ADDR_SECCS0
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA3_ADDRDEC1_BASE_ADDR_SECCS1
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA3_ADDRDEC1_BASE_ADDR_SECCS2
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA3_ADDRDEC1_BASE_ADDR_SECCS3
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA3_ADDRDEC1_ADDR_MASK_CS01
>+#define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA3_ADDRDEC1_ADDR_MASK_CS23
>+#define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA3_ADDRDEC1_ADDR_MASK_SECCS01
>+#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA3_ADDRDEC1_ADDR_MASK_SECCS23
>+#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA3_ADDRDEC1_ADDR_CFG_CS01
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA3_ADDRDEC1_ADDR_CFG_CS23
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA3_ADDRDEC1_ADDR_SEL_CS01
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA3_ADDRDEC1_ADDR_SEL_CS23
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA3_ADDRDEC1_ADDR_SEL2_CS01
>+#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA3_ADDRDEC1_ADDR_SEL2_CS23
>+#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA3_ADDRDEC1_COL_SEL_LO_CS01
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA3_ADDRDEC1_COL_SEL_LO_CS23
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA3_ADDRDEC1_COL_SEL_HI_CS01
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA3_ADDRDEC1_COL_SEL_HI_CS23
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA3_ADDRDEC1_RM_SEL_CS01
>+#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA3_ADDRDEC1_RM_SEL_CS23
>+#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA3_ADDRDEC1_RM_SEL_SECCS01
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA3_ADDRDEC1_RM_SEL_SECCS23
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA3_ADDRDEC2_BASE_ADDR_CS0
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDEC2_BASE_ADDR_CS1
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDEC2_BASE_ADDR_CS2
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDEC2_BASE_ADDR_CS3
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA3_ADDRDEC2_BASE_ADDR_SECCS0
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA3_ADDRDEC2_BASE_ADDR_SECCS1
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA3_ADDRDEC2_BASE_ADDR_SECCS2
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA3_ADDRDEC2_BASE_ADDR_SECCS3
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA3_ADDRDEC2_ADDR_MASK_CS01
>+#define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA3_ADDRDEC2_ADDR_MASK_CS23
>+#define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA3_ADDRDEC2_ADDR_MASK_SECCS01
>+#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA3_ADDRDEC2_ADDR_MASK_SECCS23
>+#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA3_ADDRDEC2_ADDR_CFG_CS01
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA3_ADDRDEC2_ADDR_CFG_CS23
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA3_ADDRDEC2_ADDR_SEL_CS01
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA3_ADDRDEC2_ADDR_SEL_CS23
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA3_ADDRDEC2_ADDR_SEL2_CS01
>+#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA3_ADDRDEC2_ADDR_SEL2_CS23
>+#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA3_ADDRDEC2_COL_SEL_LO_CS01
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA3_ADDRDEC2_COL_SEL_LO_CS23
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA3_ADDRDEC2_COL_SEL_HI_CS01
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA3_ADDRDEC2_COL_SEL_HI_CS23
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA3_ADDRDEC2_RM_SEL_CS01
>+#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA3_ADDRDEC2_RM_SEL_CS23
>+#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA3_ADDRDEC2_RM_SEL_SECCS01
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA3_ADDRDEC2_RM_SEL_SECCS23
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA3_ADDRNORMDRAM_GLOBAL_CNTL
>+#define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
>+#define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
>+#define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
>+#define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
>+#define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
>+#define MMEA3_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
>+//MMEA3_ADDRNORMGMI_GLOBAL_CNTL
>+#define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
>+#define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
>+#define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
>+#define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
>+#define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
>+#define MMEA3_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
>+//MMEA3_IO_RD_CLI2GRP_MAP0
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA3_IO_RD_CLI2GRP_MAP1
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA3_IO_WR_CLI2GRP_MAP0
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA3_IO_WR_CLI2GRP_MAP1
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA3_IO_RD_COMBINE_FLUSH
>+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA3_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA3_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA3_IO_WR_COMBINE_FLUSH
>+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA3_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA3_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA3_IO_GROUP_BURST
>+#define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA3_IO_RD_PRI_AGE
>+#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA3_IO_WR_PRI_AGE
>+#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA3_IO_RD_PRI_QUEUING
>+#define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA3_IO_WR_PRI_QUEUING
>+#define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA3_IO_RD_PRI_FIXED
>+#define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA3_IO_WR_PRI_FIXED
>+#define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA3_IO_RD_PRI_URGENCY
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA3_IO_WR_PRI_URGENCY
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA3_IO_RD_PRI_URGENCY_MASKING
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA3_IO_WR_PRI_URGENCY_MASKING
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA3_IO_RD_PRI_QUANT_PRI1
>+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA3_IO_RD_PRI_QUANT_PRI2
>+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA3_IO_RD_PRI_QUANT_PRI3
>+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA3_IO_WR_PRI_QUANT_PRI1
>+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA3_IO_WR_PRI_QUANT_PRI2
>+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA3_IO_WR_PRI_QUANT_PRI3
>+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA3_SDP_ARB_DRAM
>+#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
>+#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
>+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
>+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
>+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
>+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
>+#define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
>+#define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
>+#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
>+#define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
>+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
>+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
>+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
>+#define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
>+#define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
>+#define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
>+//MMEA3_SDP_ARB_GMI
>+#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
>+#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
>+#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
>+#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
>+#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
>+#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
>+#define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
>+#define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
>+#define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
>+#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
>+#define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
>+#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
>+#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
>+#define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
>+#define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
>+#define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
>+#define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
>+#define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
>+//MMEA3_SDP_ARB_FINAL
>+#define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
>+#define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
>+#define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
>+#define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
>+#define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
>+#define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
>+#define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
>+#define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
>+#define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
>+#define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
>+#define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
>+#define MMEA3_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
>+#define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
>+#define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
>+#define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
>+//MMEA3_SDP_DRAM_PRIORITY
>+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
>+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
>+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
>+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
>+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
>+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
>+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
>+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
>+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
>+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
>+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
>+#define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
>+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
>+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
>+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
>+#define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
>+//MMEA3_SDP_GMI_PRIORITY
>+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
>+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
>+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
>+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
>+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
>+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
>+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
>+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
>+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
>+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
>+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
>+#define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
>+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
>+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
>+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
>+#define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
>+//MMEA3_SDP_IO_PRIORITY
>+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
>+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
>+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
>+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
>+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
>+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
>+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
>+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
>+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
>+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
>+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
>+#define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
>+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
>+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
>+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
>+#define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
>+//MMEA3_SDP_CREDITS
>+#define MMEA3_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
>+#define MMEA3_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
>+#define MMEA3_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
>+#define MMEA3_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
>+#define MMEA3_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
>+#define MMEA3_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
>+//MMEA3_SDP_TAG_RESERVE0
>+#define MMEA3_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
>+#define MMEA3_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
>+#define MMEA3_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
>+#define MMEA3_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
>+#define MMEA3_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
>+#define MMEA3_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
>+#define MMEA3_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
>+#define MMEA3_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
>+//MMEA3_SDP_TAG_RESERVE1
>+#define MMEA3_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
>+#define MMEA3_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
>+#define MMEA3_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
>+#define MMEA3_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
>+#define MMEA3_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
>+#define MMEA3_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
>+#define MMEA3_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
>+#define MMEA3_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
>+//MMEA3_SDP_VCC_RESERVE0
>+#define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA3_SDP_VCC_RESERVE1
>+#define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA3_SDP_VCD_RESERVE0
>+#define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA3_SDP_VCD_RESERVE1
>+#define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA3_SDP_REQ_CNTL
>+#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
>+#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
>+#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
>+#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
>+#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
>+#define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
>+#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
>+#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
>+#define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
>+#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
>+#define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
>+#define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
>+//MMEA3_MISC
>+#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
>+#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
>+#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
>+#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
>+#define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
>+#define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
>+#define MMEA3_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
>+#define MMEA3_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
>+#define MMEA3_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
>+#define MMEA3_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
>+#define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
>+#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
>+#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
>+#define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
>+#define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
>+#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
>+#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
>+#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
>+#define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
>+#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
>+#define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
>+#define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
>+#define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
>+#define MMEA3_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
>+#define MMEA3_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
>+#define MMEA3_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
>+#define MMEA3_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
>+#define MMEA3_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
>+#define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
>+#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
>+#define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
>+#define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
>+#define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
>+#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
>+#define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
>+//MMEA3_LATENCY_SAMPLING
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
>+#define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
>+//MMEA3_PERFCOUNTER_LO
>+#define MMEA3_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define MMEA3_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//MMEA3_PERFCOUNTER_HI
>+#define MMEA3_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define MMEA3_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//MMEA3_PERFCOUNTER0_CFG
>+#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA3_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA3_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA3_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA3_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA3_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA3_PERFCOUNTER1_CFG
>+#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA3_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA3_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA3_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA3_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA3_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA3_PERFCOUNTER_RSLT_CNTL
>+#define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//MMEA3_EDC_CNT
>+#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
>+#define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
>+#define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
>+#define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
>+#define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
>+#define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
>+#define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
>+#define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
>+#define MMEA3_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
>+#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
>+#define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
>+#define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
>+#define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
>+#define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
>+#define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
>+#define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
>+#define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
>+#define MMEA3_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
>+//MMEA3_EDC_CNT2
>+#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
>+#define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
>+#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
>+#define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
>+//MMEA3_DSM_CNTL
>+#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
>+#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
>+#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
>+#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
>+#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
>+#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
>+#define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
>+#define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
>+#define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
>+#define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
>+#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
>+#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
>+#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
>+#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
>+#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
>+#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
>+#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
>+#define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
>+#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
>+#define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
>+#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
>+#define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
>+#define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
>+#define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
>+#define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
>+#define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
>+#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
>+#define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
>+#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
>+#define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
>+#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
>+#define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
>+//MMEA3_DSM_CNTLA
>+#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
>+#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
>+#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
>+#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
>+#define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
>+#define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
>+#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
>+#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
>+#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
>+#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
>+#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
>+#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
>+#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
>+#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
>+#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
>+#define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
>+#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
>+#define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
>+#define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
>+#define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
>+#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
>+#define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
>+#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
>+#define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
>+#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
>+#define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
>+#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
>+#define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
>+//MMEA3_DSM_CNTL2
>+#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
>+#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
>+#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
>+#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
>+#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
>+#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
>+#define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
>+#define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
>+#define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
>+#define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
>+#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
>+#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
>+#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
>+#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
>+#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
>+#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
>+#define MMEA3_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
>+#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
>+#define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
>+#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
>+#define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
>+#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
>+#define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
>+#define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
>+#define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
>+#define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
>+#define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
>+#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
>+#define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
>+#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
>+#define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
>+#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
>+#define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
>+#define MMEA3_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
>+//MMEA3_DSM_CNTL2A
>+#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
>+#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
>+#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
>+#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
>+#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
>+#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
>+#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
>+#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
>+#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
>+#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
>+#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
>+#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
>+#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
>+#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
>+#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
>+#define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
>+#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
>+#define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
>+#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
>+#define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
>+#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
>+#define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
>+#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
>+#define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
>+#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
>+#define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
>+#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
>+#define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
>+//MMEA3_CGTT_CLK_CTRL
>+#define MMEA3_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
>+#define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
>+#define MMEA3_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
>+#define MMEA3_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
>+#define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
>+#define MMEA3_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
>+#define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
>+#define MMEA3_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
>+#define MMEA3_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
>+#define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
>+#define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
>+//MMEA3_EDC_MODE
>+#define MMEA3_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
>+#define MMEA3_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
>+#define MMEA3_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
>+#define MMEA3_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
>+#define MMEA3_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
>+#define MMEA3_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
>+#define MMEA3_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
>+#define MMEA3_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
>+#define MMEA3_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
>+#define MMEA3_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
>+//MMEA3_ERR_STATUS
>+#define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
>+#define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
>+#define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
>+#define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
>+#define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
>+#define MMEA3_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
>+#define MMEA3_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
>+#define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
>+#define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
>+#define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
>+#define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
>+#define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
>+#define MMEA3_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
>+#define MMEA3_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
>+//MMEA3_MISC2
>+#define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
>+#define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
>+#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
>+#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
>+#define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
>+#define MMEA3_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
>+#define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
>+#define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
>+#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
>+#define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
>+#define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
>+#define MMEA3_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
>+//MMEA3_ADDRDEC_SELECT
>+#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
>+#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
>+#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
>+#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
>+#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
>+#define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
>+#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
>+#define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
>+//MMEA3_EDC_CNT3
>+#define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
>+#define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
>+#define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
>+#define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
>+#define MMEA3_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
>+#define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
>+#define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
>+#define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
>+#define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
>+#define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
>+#define MMEA3_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
>+#define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
>+
>+
>+// addressBlock: mmhub_ea_mmeadec4
>+//MMEA4_DRAM_RD_CLI2GRP_MAP0
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA4_DRAM_RD_CLI2GRP_MAP1
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA4_DRAM_WR_CLI2GRP_MAP0
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA4_DRAM_WR_CLI2GRP_MAP1
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA4_DRAM_RD_GRP2VC_MAP
>+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA4_DRAM_WR_GRP2VC_MAP
>+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA4_DRAM_RD_LAZY
>+#define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA4_DRAM_WR_LAZY
>+#define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA4_DRAM_RD_CAM_CNTL
>+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA4_DRAM_WR_CAM_CNTL
>+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA4_DRAM_PAGE_BURST
>+#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
>+#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
>+#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
>+#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
>+#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
>+#define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
>+#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
>+#define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
>+//MMEA4_DRAM_RD_PRI_AGE
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA4_DRAM_WR_PRI_AGE
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA4_DRAM_RD_PRI_QUEUING
>+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA4_DRAM_WR_PRI_QUEUING
>+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA4_DRAM_RD_PRI_FIXED
>+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA4_DRAM_WR_PRI_FIXED
>+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA4_DRAM_RD_PRI_URGENCY
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA4_DRAM_WR_PRI_URGENCY
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA4_DRAM_RD_PRI_QUANT_PRI1
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA4_DRAM_RD_PRI_QUANT_PRI2
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA4_DRAM_RD_PRI_QUANT_PRI3
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA4_DRAM_WR_PRI_QUANT_PRI1
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA4_DRAM_WR_PRI_QUANT_PRI2
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA4_DRAM_WR_PRI_QUANT_PRI3
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA4_GMI_RD_CLI2GRP_MAP0
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA4_GMI_RD_CLI2GRP_MAP1
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA4_GMI_WR_CLI2GRP_MAP0
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA4_GMI_WR_CLI2GRP_MAP1
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA4_GMI_RD_GRP2VC_MAP
>+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA4_GMI_WR_GRP2VC_MAP
>+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA4_GMI_RD_LAZY
>+#define MMEA4_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA4_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA4_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA4_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA4_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA4_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA4_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA4_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA4_GMI_WR_LAZY
>+#define MMEA4_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA4_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA4_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA4_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA4_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA4_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA4_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA4_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA4_GMI_RD_CAM_CNTL
>+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA4_GMI_WR_CAM_CNTL
>+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA4_GMI_PAGE_BURST
>+#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA4_GMI_RD_PRI_AGE
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA4_GMI_WR_PRI_AGE
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA4_GMI_RD_PRI_QUEUING
>+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA4_GMI_WR_PRI_QUEUING
>+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA4_GMI_RD_PRI_FIXED
>+#define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA4_GMI_WR_PRI_FIXED
>+#define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA4_GMI_RD_PRI_URGENCY
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA4_GMI_WR_PRI_URGENCY
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA4_GMI_RD_PRI_URGENCY_MASKING
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA4_GMI_WR_PRI_URGENCY_MASKING
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA4_GMI_RD_PRI_QUANT_PRI1
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA4_GMI_RD_PRI_QUANT_PRI2
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA4_GMI_RD_PRI_QUANT_PRI3
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA4_GMI_WR_PRI_QUANT_PRI1
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA4_GMI_WR_PRI_QUANT_PRI2
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA4_GMI_WR_PRI_QUANT_PRI3
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA4_ADDRNORM_BASE_ADDR0
>+#define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA4_ADDRNORM_LIMIT_ADDR0
>+#define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA4_ADDRNORM_BASE_ADDR1
>+#define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA4_ADDRNORM_LIMIT_ADDR1
>+#define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA4_ADDRNORM_OFFSET_ADDR1
>+#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA4_ADDRNORM_BASE_ADDR2
>+#define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA4_ADDRNORM_LIMIT_ADDR2
>+#define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA4_ADDRNORM_BASE_ADDR3
>+#define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA4_ADDRNORM_LIMIT_ADDR3
>+#define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA4_ADDRNORM_OFFSET_ADDR3
>+#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA4_ADDRNORM_BASE_ADDR4
>+#define MMEA4_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA4_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA4_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA4_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA4_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA4_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA4_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA4_ADDRNORM_LIMIT_ADDR4
>+#define MMEA4_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA4_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA4_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA4_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA4_ADDRNORM_BASE_ADDR5
>+#define MMEA4_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA4_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA4_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA4_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA4_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA4_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA4_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA4_ADDRNORM_LIMIT_ADDR5
>+#define MMEA4_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA4_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA4_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA4_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA4_ADDRNORM_OFFSET_ADDR5
>+#define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA4_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA4_ADDRNORMDRAM_HOLE_CNTL
>+#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
>+#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
>+#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
>+#define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
>+//MMEA4_ADDRNORMGMI_HOLE_CNTL
>+#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
>+#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
>+#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
>+#define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
>+//MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG
>+#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
>+#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
>+#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
>+#define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
>+//MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG
>+#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
>+#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
>+#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
>+#define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
>+//MMEA4_ADDRDEC_BANK_CFG
>+#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
>+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
>+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
>+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
>+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
>+#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
>+#define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
>+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
>+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
>+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
>+#define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
>+//MMEA4_ADDRDEC_MISC_CFG
>+#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
>+#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
>+#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
>+#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
>+#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
>+#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
>+#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
>+#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
>+#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
>+#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
>+#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
>+#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
>+#define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
>+#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
>+#define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
>+#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
>+#define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
>+#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
>+#define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
>+#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
>+#define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
>+//MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA4_ADDRDECDRAM_ADDR_HASH_PC
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
>+//MMEA4_ADDRDECDRAM_ADDR_HASH_PC2
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
>+//MMEA4_ADDRDECDRAM_ADDR_HASH_CS0
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDECDRAM_ADDR_HASH_CS1
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA4_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDECDRAM_HARVEST_ENABLE
>+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
>+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
>+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
>+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
>+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
>+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
>+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
>+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
>+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
>+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
>+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
>+#define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
>+//MMEA4_ADDRDECGMI_ADDR_HASH_BANK0
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA4_ADDRDECGMI_ADDR_HASH_BANK1
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA4_ADDRDECGMI_ADDR_HASH_BANK2
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA4_ADDRDECGMI_ADDR_HASH_BANK3
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA4_ADDRDECGMI_ADDR_HASH_BANK4
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA4_ADDRDECGMI_ADDR_HASH_BANK5
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA4_ADDRDECGMI_ADDR_HASH_PC
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
>+//MMEA4_ADDRDECGMI_ADDR_HASH_PC2
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
>+//MMEA4_ADDRDECGMI_ADDR_HASH_CS0
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA4_ADDRDECGMI_ADDR_HASH_CS1
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA4_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA4_ADDRDECGMI_HARVEST_ENABLE
>+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
>+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
>+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
>+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
>+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
>+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
>+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
>+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
>+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
>+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
>+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
>+#define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
>+//MMEA4_ADDRDEC0_BASE_ADDR_CS0
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDEC0_BASE_ADDR_CS1
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDEC0_BASE_ADDR_CS2
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDEC0_BASE_ADDR_CS3
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDEC0_BASE_ADDR_SECCS0
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA4_ADDRDEC0_BASE_ADDR_SECCS1
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA4_ADDRDEC0_BASE_ADDR_SECCS2
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA4_ADDRDEC0_BASE_ADDR_SECCS3
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA4_ADDRDEC0_ADDR_MASK_CS01
>+#define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA4_ADDRDEC0_ADDR_MASK_CS23
>+#define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA4_ADDRDEC0_ADDR_MASK_SECCS01
>+#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA4_ADDRDEC0_ADDR_MASK_SECCS23
>+#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA4_ADDRDEC0_ADDR_CFG_CS01
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA4_ADDRDEC0_ADDR_CFG_CS23
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA4_ADDRDEC0_ADDR_SEL_CS01
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA4_ADDRDEC0_ADDR_SEL_CS23
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA4_ADDRDEC0_ADDR_SEL2_CS01
>+#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA4_ADDRDEC0_ADDR_SEL2_CS23
>+#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA4_ADDRDEC0_COL_SEL_LO_CS01
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA4_ADDRDEC0_COL_SEL_LO_CS23
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA4_ADDRDEC0_COL_SEL_HI_CS01
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA4_ADDRDEC0_COL_SEL_HI_CS23
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA4_ADDRDEC0_RM_SEL_CS01
>+#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA4_ADDRDEC0_RM_SEL_CS23
>+#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA4_ADDRDEC0_RM_SEL_SECCS01
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA4_ADDRDEC0_RM_SEL_SECCS23
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA4_ADDRDEC1_BASE_ADDR_CS0
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDEC1_BASE_ADDR_CS1
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDEC1_BASE_ADDR_CS2
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDEC1_BASE_ADDR_CS3
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDEC1_BASE_ADDR_SECCS0
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA4_ADDRDEC1_BASE_ADDR_SECCS1
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA4_ADDRDEC1_BASE_ADDR_SECCS2
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA4_ADDRDEC1_BASE_ADDR_SECCS3
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA4_ADDRDEC1_ADDR_MASK_CS01
>+#define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA4_ADDRDEC1_ADDR_MASK_CS23
>+#define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA4_ADDRDEC1_ADDR_MASK_SECCS01
>+#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA4_ADDRDEC1_ADDR_MASK_SECCS23
>+#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA4_ADDRDEC1_ADDR_CFG_CS01
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA4_ADDRDEC1_ADDR_CFG_CS23
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA4_ADDRDEC1_ADDR_SEL_CS01
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA4_ADDRDEC1_ADDR_SEL_CS23
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA4_ADDRDEC1_ADDR_SEL2_CS01
>+#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA4_ADDRDEC1_ADDR_SEL2_CS23
>+#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA4_ADDRDEC1_COL_SEL_LO_CS01
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA4_ADDRDEC1_COL_SEL_LO_CS23
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA4_ADDRDEC1_COL_SEL_HI_CS01
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA4_ADDRDEC1_COL_SEL_HI_CS23
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA4_ADDRDEC1_RM_SEL_CS01
>+#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA4_ADDRDEC1_RM_SEL_CS23
>+#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA4_ADDRDEC1_RM_SEL_SECCS01
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA4_ADDRDEC1_RM_SEL_SECCS23
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA4_ADDRDEC2_BASE_ADDR_CS0
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDEC2_BASE_ADDR_CS1
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDEC2_BASE_ADDR_CS2
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDEC2_BASE_ADDR_CS3
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA4_ADDRDEC2_BASE_ADDR_SECCS0
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA4_ADDRDEC2_BASE_ADDR_SECCS1
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA4_ADDRDEC2_BASE_ADDR_SECCS2
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA4_ADDRDEC2_BASE_ADDR_SECCS3
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA4_ADDRDEC2_ADDR_MASK_CS01
>+#define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA4_ADDRDEC2_ADDR_MASK_CS23
>+#define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA4_ADDRDEC2_ADDR_MASK_SECCS01
>+#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA4_ADDRDEC2_ADDR_MASK_SECCS23
>+#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA4_ADDRDEC2_ADDR_CFG_CS01
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA4_ADDRDEC2_ADDR_CFG_CS23
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA4_ADDRDEC2_ADDR_SEL_CS01
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA4_ADDRDEC2_ADDR_SEL_CS23
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA4_ADDRDEC2_ADDR_SEL2_CS01
>+#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA4_ADDRDEC2_ADDR_SEL2_CS23
>+#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA4_ADDRDEC2_COL_SEL_LO_CS01
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA4_ADDRDEC2_COL_SEL_LO_CS23
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA4_ADDRDEC2_COL_SEL_HI_CS01
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA4_ADDRDEC2_COL_SEL_HI_CS23
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA4_ADDRDEC2_RM_SEL_CS01
>+#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA4_ADDRDEC2_RM_SEL_CS23
>+#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA4_ADDRDEC2_RM_SEL_SECCS01
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA4_ADDRDEC2_RM_SEL_SECCS23
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA4_ADDRNORMDRAM_GLOBAL_CNTL
>+#define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
>+#define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
>+#define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
>+#define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
>+#define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
>+#define MMEA4_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
>+//MMEA4_ADDRNORMGMI_GLOBAL_CNTL
>+#define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
>+#define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
>+#define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
>+#define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
>+#define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
>+#define MMEA4_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
>+//MMEA4_IO_RD_CLI2GRP_MAP0
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA4_IO_RD_CLI2GRP_MAP1
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA4_IO_WR_CLI2GRP_MAP0
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA4_IO_WR_CLI2GRP_MAP1
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA4_IO_RD_COMBINE_FLUSH
>+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA4_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA4_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA4_IO_WR_COMBINE_FLUSH
>+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA4_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA4_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA4_IO_GROUP_BURST
>+#define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA4_IO_RD_PRI_AGE
>+#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA4_IO_WR_PRI_AGE
>+#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA4_IO_RD_PRI_QUEUING
>+#define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA4_IO_WR_PRI_QUEUING
>+#define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA4_IO_RD_PRI_FIXED
>+#define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA4_IO_WR_PRI_FIXED
>+#define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA4_IO_RD_PRI_URGENCY
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA4_IO_WR_PRI_URGENCY
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA4_IO_RD_PRI_URGENCY_MASKING
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA4_IO_WR_PRI_URGENCY_MASKING
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA4_IO_RD_PRI_QUANT_PRI1
>+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA4_IO_RD_PRI_QUANT_PRI2
>+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA4_IO_RD_PRI_QUANT_PRI3
>+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA4_IO_WR_PRI_QUANT_PRI1
>+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA4_IO_WR_PRI_QUANT_PRI2
>+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA4_IO_WR_PRI_QUANT_PRI3
>+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA4_SDP_ARB_DRAM
>+#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
>+#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
>+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
>+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
>+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
>+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
>+#define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
>+#define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
>+#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
>+#define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
>+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
>+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
>+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
>+#define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
>+#define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
>+#define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
>+//MMEA4_SDP_ARB_GMI
>+#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
>+#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
>+#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
>+#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
>+#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
>+#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
>+#define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
>+#define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
>+#define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
>+#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
>+#define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
>+#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
>+#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
>+#define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
>+#define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
>+#define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
>+#define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
>+#define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
>+//MMEA4_SDP_ARB_FINAL
>+#define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
>+#define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
>+#define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
>+#define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
>+#define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
>+#define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
>+#define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
>+#define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
>+#define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
>+#define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
>+#define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
>+#define MMEA4_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
>+#define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
>+#define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
>+#define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
>+//MMEA4_SDP_DRAM_PRIORITY
>+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
>+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
>+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
>+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
>+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
>+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
>+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
>+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
>+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
>+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
>+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
>+#define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
>+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
>+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
>+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
>+#define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
>+//MMEA4_SDP_GMI_PRIORITY
>+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
>+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
>+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
>+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
>+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
>+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
>+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
>+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
>+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
>+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
>+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
>+#define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
>+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
>+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
>+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
>+#define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
>+//MMEA4_SDP_IO_PRIORITY
>+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
>+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
>+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
>+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
>+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
>+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
>+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
>+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
>+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
>+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
>+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
>+#define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
>+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
>+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
>+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
>+#define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
>+//MMEA4_SDP_CREDITS
>+#define MMEA4_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
>+#define MMEA4_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
>+#define MMEA4_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
>+#define MMEA4_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
>+#define MMEA4_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
>+#define MMEA4_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
>+//MMEA4_SDP_TAG_RESERVE0
>+#define MMEA4_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
>+#define MMEA4_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
>+#define MMEA4_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
>+#define MMEA4_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
>+#define MMEA4_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
>+#define MMEA4_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
>+#define MMEA4_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
>+#define MMEA4_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
>+//MMEA4_SDP_TAG_RESERVE1
>+#define MMEA4_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
>+#define MMEA4_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
>+#define MMEA4_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
>+#define MMEA4_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
>+#define MMEA4_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
>+#define MMEA4_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
>+#define MMEA4_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
>+#define MMEA4_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
>+//MMEA4_SDP_VCC_RESERVE0
>+#define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA4_SDP_VCC_RESERVE1
>+#define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA4_SDP_VCD_RESERVE0
>+#define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA4_SDP_VCD_RESERVE1
>+#define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA4_SDP_REQ_CNTL
>+#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
>+#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
>+#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
>+#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
>+#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
>+#define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
>+#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
>+#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
>+#define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
>+#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
>+#define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
>+#define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
>+//MMEA4_MISC
>+#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
>+#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
>+#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
>+#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
>+#define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
>+#define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
>+#define MMEA4_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
>+#define MMEA4_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
>+#define MMEA4_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
>+#define MMEA4_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
>+#define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
>+#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
>+#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
>+#define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
>+#define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
>+#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
>+#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
>+#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
>+#define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
>+#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
>+#define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
>+#define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
>+#define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
>+#define MMEA4_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
>+#define MMEA4_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
>+#define MMEA4_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
>+#define MMEA4_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
>+#define MMEA4_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
>+#define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
>+#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
>+#define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
>+#define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
>+#define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
>+#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
>+#define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
>+//MMEA4_LATENCY_SAMPLING
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
>+#define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
>+//MMEA4_PERFCOUNTER_LO
>+#define MMEA4_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define MMEA4_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//MMEA4_PERFCOUNTER_HI
>+#define MMEA4_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define MMEA4_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//MMEA4_PERFCOUNTER0_CFG
>+#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA4_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA4_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA4_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA4_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA4_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA4_PERFCOUNTER1_CFG
>+#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA4_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA4_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA4_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA4_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA4_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA4_PERFCOUNTER_RSLT_CNTL
>+#define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//MMEA4_EDC_CNT
>+#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
>+#define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
>+#define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
>+#define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
>+#define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
>+#define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
>+#define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
>+#define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
>+#define MMEA4_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
>+#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
>+#define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
>+#define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
>+#define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
>+#define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
>+#define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
>+#define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
>+#define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
>+#define MMEA4_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
>+//MMEA4_EDC_CNT2
>+#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
>+#define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
>+#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
>+#define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
>+//MMEA4_DSM_CNTL
>+#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
>+#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
>+#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
>+#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
>+#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
>+#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
>+#define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
>+#define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
>+#define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
>+#define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
>+#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
>+#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
>+#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
>+#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
>+#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
>+#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
>+#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
>+#define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
>+#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
>+#define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
>+#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
>+#define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
>+#define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
>+#define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
>+#define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
>+#define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
>+#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
>+#define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
>+#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
>+#define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
>+#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
>+#define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
>+//MMEA4_DSM_CNTLA
>+#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
>+#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
>+#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
>+#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
>+#define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
>+#define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
>+#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
>+#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
>+#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
>+#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
>+#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
>+#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
>+#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
>+#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
>+#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
>+#define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
>+#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
>+#define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
>+#define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
>+#define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
>+#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
>+#define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
>+#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
>+#define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
>+#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
>+#define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
>+#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
>+#define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
>+//MMEA4_DSM_CNTL2
>+#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
>+#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
>+#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
>+#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
>+#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
>+#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
>+#define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
>+#define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
>+#define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
>+#define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
>+#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
>+#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
>+#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
>+#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
>+#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
>+#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
>+#define MMEA4_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
>+#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
>+#define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
>+#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
>+#define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
>+#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
>+#define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
>+#define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
>+#define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
>+#define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
>+#define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
>+#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
>+#define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
>+#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
>+#define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
>+#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
>+#define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
>+#define MMEA4_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
>+//MMEA4_DSM_CNTL2A
>+#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
>+#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
>+#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
>+#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
>+#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
>+#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
>+#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
>+#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
>+#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
>+#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
>+#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
>+#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
>+#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
>+#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
>+#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
>+#define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
>+#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
>+#define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
>+#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
>+#define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
>+#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
>+#define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
>+#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
>+#define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
>+#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
>+#define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
>+#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
>+#define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
>+//MMEA4_CGTT_CLK_CTRL
>+#define MMEA4_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
>+#define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
>+#define MMEA4_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
>+#define MMEA4_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
>+#define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
>+#define MMEA4_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
>+#define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
>+#define MMEA4_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
>+#define MMEA4_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
>+#define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
>+#define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
>+//MMEA4_EDC_MODE
>+#define MMEA4_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
>+#define MMEA4_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
>+#define MMEA4_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
>+#define MMEA4_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
>+#define MMEA4_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
>+#define MMEA4_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
>+#define MMEA4_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
>+#define MMEA4_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
>+#define MMEA4_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
>+#define MMEA4_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
>+//MMEA4_ERR_STATUS
>+#define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
>+#define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
>+#define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
>+#define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
>+#define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
>+#define MMEA4_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
>+#define MMEA4_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
>+#define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
>+#define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
>+#define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
>+#define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
>+#define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
>+#define MMEA4_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
>+#define MMEA4_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
>+//MMEA4_MISC2
>+#define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
>+#define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
>+#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
>+#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
>+#define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
>+#define MMEA4_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
>+#define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
>+#define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
>+#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
>+#define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
>+#define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
>+#define MMEA4_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
>+//MMEA4_ADDRDEC_SELECT
>+#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
>+#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
>+#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
>+#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
>+#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
>+#define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
>+#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
>+#define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
>+//MMEA4_EDC_CNT3
>+#define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
>+#define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
>+#define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
>+#define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
>+#define MMEA4_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
>+#define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
>+#define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
>+#define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
>+#define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
>+#define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
>+#define MMEA4_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
>+#define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
>+
>+
>+// addressBlock: mmhub_pctldec0
>+//PCTL0_CTRL
>+#define PCTL0_CTRL__PG_ENABLE__SHIFT                                                                          0x0
>+#define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT                                                              0x1
>+#define PCTL0_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT                                                         0x4
>+#define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT                                                         0xb
>+#define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT                                                     0x10
>+#define PCTL0_CTRL__OVR_EA0_SDP_PARTACK__SHIFT                                                                0x11
>+#define PCTL0_CTRL__OVR_EA1_SDP_PARTACK__SHIFT                                                                0x12
>+#define PCTL0_CTRL__OVR_EA2_SDP_PARTACK__SHIFT                                                                0x13
>+#define PCTL0_CTRL__OVR_EA3_SDP_PARTACK__SHIFT                                                                0x14
>+#define PCTL0_CTRL__OVR_EA4_SDP_PARTACK__SHIFT                                                                0x15
>+#define PCTL0_CTRL__OVR_EA0_SDP_FULLACK__SHIFT                                                                0x16
>+#define PCTL0_CTRL__OVR_EA1_SDP_FULLACK__SHIFT                                                                0x17
>+#define PCTL0_CTRL__OVR_EA2_SDP_FULLACK__SHIFT                                                                0x18
>+#define PCTL0_CTRL__OVR_EA3_SDP_FULLACK__SHIFT                                                                0x19
>+#define PCTL0_CTRL__OVR_EA4_SDP_FULLACK__SHIFT                                                                0x1a
>+#define PCTL0_CTRL__PGFSM_CMD_STATUS__SHIFT                                                                   0x1b
>+#define PCTL0_CTRL__PG_ENABLE_MASK                                                                            0x00000001L
>+#define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK                                                                0x0000000EL
>+#define PCTL0_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK                                                           0x000007F0L
>+#define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK                                                           0x0000F800L
>+#define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK                                                       0x00010000L
>+#define PCTL0_CTRL__OVR_EA0_SDP_PARTACK_MASK                                                                  0x00020000L
>+#define PCTL0_CTRL__OVR_EA1_SDP_PARTACK_MASK                                                                  0x00040000L
>+#define PCTL0_CTRL__OVR_EA2_SDP_PARTACK_MASK                                                                  0x00080000L
>+#define PCTL0_CTRL__OVR_EA3_SDP_PARTACK_MASK                                                                  0x00100000L
>+#define PCTL0_CTRL__OVR_EA4_SDP_PARTACK_MASK                                                                  0x00200000L
>+#define PCTL0_CTRL__OVR_EA0_SDP_FULLACK_MASK                                                                  0x00400000L
>+#define PCTL0_CTRL__OVR_EA1_SDP_FULLACK_MASK                                                                  0x00800000L
>+#define PCTL0_CTRL__OVR_EA2_SDP_FULLACK_MASK                                                                  0x01000000L
>+#define PCTL0_CTRL__OVR_EA3_SDP_FULLACK_MASK                                                                  0x02000000L
>+#define PCTL0_CTRL__OVR_EA4_SDP_FULLACK_MASK                                                                  0x04000000L
>+#define PCTL0_CTRL__PGFSM_CMD_STATUS_MASK                                                                     0x18000000L
>+//PCTL0_MMHUB_DEEPSLEEP_IB
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS0__SHIFT                                                                  0x0
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS1__SHIFT                                                                  0x1
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS2__SHIFT                                                                  0x2
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS3__SHIFT                                                                  0x3
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS4__SHIFT                                                                  0x4
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS5__SHIFT                                                                  0x5
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS6__SHIFT                                                                  0x6
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS7__SHIFT                                                                  0x7
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS8__SHIFT                                                                  0x8
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS9__SHIFT                                                                  0x9
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS10__SHIFT                                                                 0xa
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS11__SHIFT                                                                 0xb
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS12__SHIFT                                                                 0xc
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS13__SHIFT                                                                 0xd
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS14__SHIFT                                                                 0xe
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS15__SHIFT                                                                 0xf
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS16__SHIFT                                                                 0x10
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT                                                             0x1f
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS0_MASK                                                                    0x00000001L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS1_MASK                                                                    0x00000002L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS2_MASK                                                                    0x00000004L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS3_MASK                                                                    0x00000008L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS4_MASK                                                                    0x00000010L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS5_MASK                                                                    0x00000020L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS6_MASK                                                                    0x00000040L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS7_MASK                                                                    0x00000080L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS8_MASK                                                                    0x00000100L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS9_MASK                                                                    0x00000200L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS10_MASK                                                                   0x00000400L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS11_MASK                                                                   0x00000800L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS12_MASK                                                                   0x00001000L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS13_MASK                                                                   0x00002000L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS14_MASK                                                                   0x00004000L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS15_MASK                                                                   0x00008000L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__DS16_MASK                                                                   0x00010000L
>+#define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK                                                               0x80000000L
>+//PCTL0_MMHUB_DEEPSLEEP_OVERRIDE
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT                                                            0x0
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT                                                            0x1
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT                                                            0x2
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT                                                            0x3
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT                                                            0x4
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT                                                            0x5
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT                                                            0x6
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT                                                            0x7
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT                                                            0x8
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT                                                            0x9
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT                                                           0xa
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT                                                           0xb
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT                                                           0xc
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT                                                           0xd
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT                                                           0xe
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT                                                           0xf
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT                                                           0x10
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT                                                       0x11
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK                                                              0x00000001L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK                                                              0x00000002L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK                                                              0x00000004L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK                                                              0x00000008L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK                                                              0x00000010L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK                                                              0x00000020L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK                                                              0x00000040L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK                                                              0x00000080L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK                                                              0x00000100L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK                                                              0x00000200L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK                                                             0x00000400L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK                                                             0x00000800L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK                                                             0x00001000L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK                                                             0x00002000L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK                                                             0x00004000L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK                                                             0x00008000L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK                                                             0x00010000L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK                                                         0x00020000L
>+//PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT                                                         0x0
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT                                                         0x1
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT                                                         0x2
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT                                                         0x3
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT                                                         0x4
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT                                                         0x5
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT                                                         0x6
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT                                                         0x7
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT                                                         0x8
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT                                                         0x9
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT                                                        0xa
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT                                                        0xb
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT                                                        0xc
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT                                                        0xd
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT                                                        0xe
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT                                                        0xf
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT                                                        0x10
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK                                                           0x00000001L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK                                                           0x00000002L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK                                                           0x00000004L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK                                                           0x00000008L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK                                                           0x00000010L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK                                                           0x00000020L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK                                                           0x00000040L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK                                                           0x00000080L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK                                                           0x00000100L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK                                                           0x00000200L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK                                                          0x00000400L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK                                                          0x00000800L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK                                                          0x00001000L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK                                                          0x00002000L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK                                                          0x00004000L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK                                                          0x00008000L
>+#define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK                                                          0x00010000L
>+//PCTL0_PG_IGNORE_DEEPSLEEP
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS0__SHIFT                                                                 0x0
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS1__SHIFT                                                                 0x1
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS2__SHIFT                                                                 0x2
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS3__SHIFT                                                                 0x3
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS4__SHIFT                                                                 0x4
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS5__SHIFT                                                                 0x5
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS6__SHIFT                                                                 0x6
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS7__SHIFT                                                                 0x7
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS8__SHIFT                                                                 0x8
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS9__SHIFT                                                                 0x9
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS10__SHIFT                                                                0xa
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS11__SHIFT                                                                0xb
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS12__SHIFT                                                                0xc
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS13__SHIFT                                                                0xd
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS14__SHIFT                                                                0xe
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS15__SHIFT                                                                0xf
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS16__SHIFT                                                                0x10
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT                                                            0x11
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT                                                              0x12
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS0_MASK                                                                   0x00000001L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS1_MASK                                                                   0x00000002L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS2_MASK                                                                   0x00000004L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS3_MASK                                                                   0x00000008L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS4_MASK                                                                   0x00000010L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS5_MASK                                                                   0x00000020L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS6_MASK                                                                   0x00000040L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS7_MASK                                                                   0x00000080L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS8_MASK                                                                   0x00000100L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS9_MASK                                                                   0x00000200L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS10_MASK                                                                  0x00000400L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS11_MASK                                                                  0x00000800L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS12_MASK                                                                  0x00001000L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS13_MASK                                                                  0x00002000L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS14_MASK                                                                  0x00004000L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS15_MASK                                                                  0x00008000L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS16_MASK                                                                  0x00010000L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK                                                              0x00020000L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK                                                                0x00040000L
>+//PCTL0_PG_IGNORE_DEEPSLEEP_IB
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT                                                              0x0
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT                                                              0x1
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT                                                              0x2
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT                                                              0x3
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT                                                              0x4
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT                                                              0x5
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT                                                              0x6
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT                                                              0x7
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT                                                              0x8
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT                                                              0x9
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT                                                             0xa
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT                                                             0xb
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT                                                             0xc
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT                                                             0xd
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT                                                             0xe
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT                                                             0xf
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT                                                             0x10
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT                                                           0x11
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK                                                                0x00000001L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK                                                                0x00000002L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK                                                                0x00000004L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK                                                                0x00000008L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK                                                                0x00000010L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK                                                                0x00000020L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK                                                                0x00000040L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK                                                                0x00000080L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK                                                                0x00000100L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK                                                                0x00000200L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK                                                               0x00000400L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK                                                               0x00000800L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK                                                               0x00001000L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK                                                               0x00002000L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK                                                               0x00004000L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK                                                               0x00008000L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK                                                               0x00010000L
>+#define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK                                                             0x00020000L
>+//PCTL0_SLICE0_CFG_DAGB_BUSY
>+#define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
>+#define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
>+//PCTL0_SLICE0_CFG_DS_ALLOW
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
>+//PCTL0_SLICE0_CFG_DS_ALLOW_IB
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
>+#define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
>+//PCTL0_SLICE1_CFG_DAGB_BUSY
>+#define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
>+#define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
>+//PCTL0_SLICE1_CFG_DS_ALLOW
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
>+//PCTL0_SLICE1_CFG_DS_ALLOW_IB
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
>+#define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
>+//PCTL0_SLICE2_CFG_DAGB_BUSY
>+#define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
>+#define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
>+//PCTL0_SLICE2_CFG_DS_ALLOW
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
>+//PCTL0_SLICE2_CFG_DS_ALLOW_IB
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
>+#define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
>+//PCTL0_SLICE3_CFG_DAGB_BUSY
>+#define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
>+#define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
>+//PCTL0_SLICE3_CFG_DS_ALLOW
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
>+//PCTL0_SLICE3_CFG_DS_ALLOW_IB
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
>+#define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
>+//PCTL0_SLICE4_CFG_DAGB_BUSY
>+#define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
>+#define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
>+//PCTL0_SLICE4_CFG_DS_ALLOW
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
>+//PCTL0_SLICE4_CFG_DS_ALLOW_IB
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
>+#define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
>+//PCTL0_UTCL2_MISC
>+#define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                           0xb
>+#define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                          0xc
>+#define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                           0xf
>+#define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                  0x10
>+#define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                   0x11
>+#define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT                                                              0x12
>+#define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK                                                             0x00000800L
>+#define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK                                                            0x00007000L
>+#define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK                                                             0x00008000L
>+#define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                    0x00010000L
>+#define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                     0x00020000L
>+#define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE_MASK                                                                0x00040000L
>+//PCTL0_SLICE0_MISC
>+#define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
>+#define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
>+#define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
>+#define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
>+#define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
>+#define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
>+#define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
>+#define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
>+#define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
>+#define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
>+#define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
>+#define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
>+#define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
>+#define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
>+//PCTL0_SLICE1_MISC
>+#define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
>+#define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
>+#define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
>+#define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
>+#define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
>+#define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
>+#define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
>+#define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
>+#define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
>+#define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
>+#define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
>+#define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
>+#define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
>+#define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
>+//PCTL0_SLICE2_MISC
>+#define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
>+#define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
>+#define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
>+#define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
>+#define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
>+#define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
>+#define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
>+#define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
>+#define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
>+#define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
>+#define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
>+#define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
>+#define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
>+#define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
>+//PCTL0_SLICE3_MISC
>+#define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
>+#define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
>+#define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
>+#define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
>+#define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
>+#define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
>+#define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
>+#define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
>+#define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
>+#define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
>+#define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
>+#define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
>+#define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
>+#define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
>+//PCTL0_SLICE4_MISC
>+#define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
>+#define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
>+#define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
>+#define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
>+#define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
>+#define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
>+#define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
>+#define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
>+#define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
>+#define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
>+#define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
>+#define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
>+#define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
>+#define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
>+//PCTL0_UTCL2_RENG_EXECUTE
>+#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                     0x0
>+#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                0x1
>+#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                           0x2
>+#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                 0xd
>+#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                       0x00000001L
>+#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                  0x00000002L
>+#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                             0x00001FFCL
>+#define PCTL0_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                   0x00FFE000L
>+//PCTL0_SLICE0_RENG_EXECUTE
>+#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
>+#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
>+#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
>+#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
>+#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
>+#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
>+#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
>+#define PCTL0_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
>+//PCTL0_SLICE1_RENG_EXECUTE
>+#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
>+#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
>+#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
>+#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
>+#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
>+#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
>+#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
>+#define PCTL0_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
>+//PCTL0_SLICE2_RENG_EXECUTE
>+#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
>+#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
>+#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
>+#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
>+#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
>+#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
>+#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
>+#define PCTL0_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
>+//PCTL0_SLICE3_RENG_EXECUTE
>+#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
>+#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
>+#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
>+#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
>+#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
>+#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
>+#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
>+#define PCTL0_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
>+//PCTL0_SLICE4_RENG_EXECUTE
>+#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
>+#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
>+#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
>+#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
>+#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
>+#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
>+#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
>+#define PCTL0_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
>+//PCTL0_UTCL2_RENG_RAM_INDEX
>+#define PCTL0_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                     0x0
>+#define PCTL0_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                       0x000007FFL
>+//PCTL0_UTCL2_RENG_RAM_DATA
>+#define PCTL0_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                       0x0
>+#define PCTL0_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                         0xFFFFFFFFL
>+//PCTL0_SLICE0_RENG_RAM_INDEX
>+#define PCTL0_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
>+#define PCTL0_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
>+//PCTL0_SLICE0_RENG_RAM_DATA
>+#define PCTL0_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
>+#define PCTL0_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
>+//PCTL0_SLICE1_RENG_RAM_INDEX
>+#define PCTL0_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
>+#define PCTL0_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
>+//PCTL0_SLICE1_RENG_RAM_DATA
>+#define PCTL0_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
>+#define PCTL0_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
>+//PCTL0_SLICE2_RENG_RAM_INDEX
>+#define PCTL0_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
>+#define PCTL0_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
>+//PCTL0_SLICE2_RENG_RAM_DATA
>+#define PCTL0_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
>+#define PCTL0_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
>+//PCTL0_SLICE3_RENG_RAM_INDEX
>+#define PCTL0_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
>+#define PCTL0_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
>+//PCTL0_SLICE3_RENG_RAM_DATA
>+#define PCTL0_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
>+#define PCTL0_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
>+//PCTL0_SLICE4_RENG_RAM_INDEX
>+#define PCTL0_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
>+#define PCTL0_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
>+//PCTL0_SLICE4_RENG_RAM_DATA
>+#define PCTL0_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
>+#define PCTL0_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
>+//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
>+//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
>+//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
>+//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
>+//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
>+//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
>+//PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
>+#define PCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
>+//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1dec
>+//VML1_0_MC_VM_MX_L1_TLB0_STATUS
>+#define VML1_0_MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_0_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_0_MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_0_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_0_MC_VM_MX_L1_TLB1_STATUS
>+#define VML1_0_MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_0_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_0_MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_0_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_0_MC_VM_MX_L1_TLB2_STATUS
>+#define VML1_0_MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_0_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_0_MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_0_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_0_MC_VM_MX_L1_TLB3_STATUS
>+#define VML1_0_MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_0_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_0_MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_0_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_0_MC_VM_MX_L1_TLB4_STATUS
>+#define VML1_0_MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_0_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_0_MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_0_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_0_MC_VM_MX_L1_TLB5_STATUS
>+#define VML1_0_MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_0_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_0_MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_0_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_0_MC_VM_MX_L1_TLB6_STATUS
>+#define VML1_0_MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_0_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_0_MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_0_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_0_MC_VM_MX_L1_TLB7_STATUS
>+#define VML1_0_MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_0_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_0_MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_0_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1pldec
>+//VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                 0x0
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                             0x8
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                0x18
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                   0x1c
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                    0x1d
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                   0x000000FFL
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                  0x0F000000L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK                                                     0x10000000L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK                                                      0x20000000L
>+//VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                 0x0
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                             0x8
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                0x18
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                   0x1c
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                    0x1d
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                   0x000000FFL
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                  0x0F000000L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK                                                     0x10000000L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK                                                      0x20000000L
>+//VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                 0x0
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                             0x8
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                0x18
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                   0x1c
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                    0x1d
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                   0x000000FFL
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                  0x0F000000L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK                                                     0x10000000L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK                                                      0x20000000L
>+//VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                 0x0
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                             0x8
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                0x18
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                   0x1c
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                    0x1d
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                   0x000000FFL
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                  0x0F000000L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK                                                     0x10000000L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK                                                      0x20000000L
>+//VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                 0x0
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                       0x8
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                        0x10
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                          0x18
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                           0x19
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                0x1a
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                   0x0000000FL
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                         0x0000FF00L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                          0x00FF0000L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                            0x01000000L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                             0x02000000L
>+#define VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                  0x04000000L
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1prdec
>+//VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO
>+#define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                 0x0
>+#define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                   0xFFFFFFFFL
>+//VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI
>+#define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                 0x0
>+#define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                              0x10
>+#define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                   0x0000FFFFL
>+#define VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                0xFFFF0000L
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2dec
>+//ATCL2_0_ATC_L2_CNTL
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT                                       0x0
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT                                      0x3
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                           0x6
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                          0x7
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT                                  0x8
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT                                 0xb
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                      0xe
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                     0xf
>+#define ATCL2_0_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT                                                     0x10
>+#define ATCL2_0_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                  0x13
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK                                         0x00000003L
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK                                        0x00000018L
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                             0x00000040L
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                            0x00000080L
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK                                    0x00000300L
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK                                   0x00001800L
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                        0x00004000L
>+#define ATCL2_0_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                       0x00008000L
>+#define ATCL2_0_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK                                                       0x00070000L
>+#define ATCL2_0_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                    0x00080000L
>+//ATCL2_0_ATC_L2_CNTL2
>+#define ATCL2_0_ATC_L2_CNTL2__BANK_SELECT__SHIFT                                                              0x0
>+#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT                                                     0x6
>+#define ATCL2_0_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                      0x8
>+#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT                                             0x9
>+#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT                                                       0xc
>+#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                 0xf
>+#define ATCL2_0_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE__SHIFT                                                    0x15
>+#define ATCL2_0_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE__SHIFT                                                   0x1b
>+#define ATCL2_0_ATC_L2_CNTL2__BANK_SELECT_MASK                                                                0x0000003FL
>+#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK                                                       0x000000C0L
>+#define ATCL2_0_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK                                        0x00000100L
>+#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK                                               0x00000E00L
>+#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK                                                         0x00007000L
>+#define ATCL2_0_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                   0x001F8000L
>+#define ATCL2_0_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE_MASK                                                      0x07E00000L
>+#define ATCL2_0_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE_MASK                                                     0x08000000L
>+//ATCL2_0_ATC_L2_CACHE_DATA0
>+#define ATCL2_0_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT                                                0x0
>+#define ATCL2_0_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT                                                  0x1
>+#define ATCL2_0_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT                                                  0x2
>+#define ATCL2_0_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT                                          0x17
>+#define ATCL2_0_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK                                                  0x00000001L
>+#define ATCL2_0_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK                                                    0x00000002L
>+#define ATCL2_0_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK                                                    0x007FFFFCL
>+#define ATCL2_0_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK                                            0x07800000L
>+//ATCL2_0_ATC_L2_CACHE_DATA1
>+#define ATCL2_0_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT                                           0x0
>+#define ATCL2_0_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK                                             0xFFFFFFFFL
>+//ATCL2_0_ATC_L2_CACHE_DATA2
>+#define ATCL2_0_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT                                              0x0
>+#define ATCL2_0_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK                                                0xFFFFFFFFL
>+//ATCL2_0_ATC_L2_CNTL3
>+#define ATCL2_0_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT                                          0x0
>+#define ATCL2_0_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT                                                0x3
>+#define ATCL2_0_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT                                                0x9
>+#define ATCL2_0_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK                                            0x00000007L
>+#define ATCL2_0_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK                                                  0x000001F8L
>+#define ATCL2_0_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK                                                  0x00000E00L
>+//ATCL2_0_ATC_L2_STATUS
>+#define ATCL2_0_ATC_L2_STATUS__BUSY__SHIFT                                                                    0x0
>+#define ATCL2_0_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT                                                       0x1
>+#define ATCL2_0_ATC_L2_STATUS__BUSY_MASK                                                                      0x00000001L
>+#define ATCL2_0_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK                                                         0x7FFFFFFEL
>+//ATCL2_0_ATC_L2_STATUS2
>+#define ATCL2_0_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT                                      0x0
>+#define ATCL2_0_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT                                          0x8
>+#define ATCL2_0_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK                                        0x000000FFL
>+#define ATCL2_0_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK                                            0x0000FF00L
>+//ATCL2_0_ATC_L2_STATUS3
>+#define ATCL2_0_ATC_L2_STATUS3__BUSY__SHIFT                                                                   0x0
>+#define ATCL2_0_ATC_L2_STATUS3__PARITY_ERROR_INFO__SHIFT                                                      0x1
>+#define ATCL2_0_ATC_L2_STATUS3__BUSY_MASK                                                                     0x00000001L
>+#define ATCL2_0_ATC_L2_STATUS3__PARITY_ERROR_INFO_MASK                                                        0x7FFFFFFEL
>+//ATCL2_0_ATC_L2_MISC_CG
>+#define ATCL2_0_ATC_L2_MISC_CG__OFFDLY__SHIFT                                                                 0x6
>+#define ATCL2_0_ATC_L2_MISC_CG__ENABLE__SHIFT                                                                 0x12
>+#define ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT                                                          0x13
>+#define ATCL2_0_ATC_L2_MISC_CG__OFFDLY_MASK                                                                   0x00000FC0L
>+#define ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK                                                                   0x00040000L
>+#define ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK                                                            0x00080000L
>+//ATCL2_0_ATC_L2_MEM_POWER_LS
>+#define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT                                                          0x0
>+#define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT                                                           0x6
>+#define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK                                                            0x0000003FL
>+#define ATCL2_0_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK                                                             0x00000FC0L
>+//ATCL2_0_ATC_L2_CGTT_CLK_CTRL
>+#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                    0xf
>+#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x10
>+#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                    0x18
>+#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                      0x00008000L
>+#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00FF0000L
>+#define ATCL2_0_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                      0xFF000000L
>+//ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT                                                       0x0
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK                                                         0x000000FFL
>+//ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT                                                       0x0
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK                                                         0x000000FFL
>+//ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT                                                 0x0
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                           0x6
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                          0x8
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                          0x9
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                          0xb
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT                                               0xc
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT                                                    0xd
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT                                                    0xf
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT                                                     0x11
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK                                                   0x0000003FL
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                             0x000000C0L
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                            0x00000100L
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                            0x00000600L
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                            0x00000800L
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK                                                 0x00001000L
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK                                                      0x00006000L
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK                                                      0x00018000L
>+#define ATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK                                                       0x00020000L
>+//ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT                                                 0x0
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                           0x6
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                          0x8
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                          0x9
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                          0xb
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT                                               0xc
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT                                                    0xd
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT                                                    0xf
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT                                                     0x11
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK                                                   0x0000003FL
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                             0x000000C0L
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                            0x00000100L
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                            0x00000600L
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                            0x00000800L
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK                                                 0x00001000L
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK                                                      0x00006000L
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK                                                      0x00018000L
>+#define ATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK                                                       0x00020000L
>+//ATCL2_0_ATC_L2_CNTL4
>+#define ATCL2_0_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                  0x0
>+#define ATCL2_0_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                 0xa
>+#define ATCL2_0_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                    0x000003FFL
>+#define ATCL2_0_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                   0x000FFC00L
>+//ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES
>+#define ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT                                             0x0
>+#define ATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK                                               0xFFFFFFFFL
>+
>+
>+// addressBlock: mmhub_utcl2_vml2pfdec
>+//VML2PF0_VM_L2_CNTL
>+#define VML2PF0_VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                            0x0
>+#define VML2PF0_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                              0x1
>+#define VML2PF0_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                              0x2
>+#define VML2PF0_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                              0x4
>+#define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                          0x8
>+#define VML2PF0_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                    0x9
>+#define VML2PF0_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                   0xa
>+#define VML2PF0_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                   0xb
>+#define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                   0xc
>+#define VML2PF0_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                    0xf
>+#define VML2PF0_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                   0x12
>+#define VML2PF0_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                              0x13
>+#define VML2PF0_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                0x15
>+#define VML2PF0_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                     0x1a
>+#define VML2PF0_VM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                              0x00000001L
>+#define VML2PF0_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                0x00000002L
>+#define VML2PF0_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                0x0000000CL
>+#define VML2PF0_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                0x00000030L
>+#define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                            0x00000100L
>+#define VML2PF0_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                      0x00000200L
>+#define VML2PF0_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                     0x00000400L
>+#define VML2PF0_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                     0x00000800L
>+#define VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                     0x00007000L
>+#define VML2PF0_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                      0x00038000L
>+#define VML2PF0_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                     0x00040000L
>+#define VML2PF0_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                0x00180000L
>+#define VML2PF0_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                  0x03E00000L
>+#define VML2PF0_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                       0x0C000000L
>+//VML2PF0_VM_L2_CNTL2
>+#define VML2PF0_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                    0x0
>+#define VML2PF0_VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                       0x1
>+#define VML2PF0_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                             0x15
>+#define VML2PF0_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                           0x16
>+#define VML2PF0_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                    0x17
>+#define VML2PF0_VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                     0x1a
>+#define VML2PF0_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                  0x1c
>+#define VML2PF0_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                      0x00000001L
>+#define VML2PF0_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                         0x00000002L
>+#define VML2PF0_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                               0x00200000L
>+#define VML2PF0_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                             0x00400000L
>+#define VML2PF0_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                      0x03800000L
>+#define VML2PF0_VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                       0x0C000000L
>+#define VML2PF0_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                    0x70000000L
>+//VML2PF0_VM_L2_CNTL3
>+#define VML2PF0_VM_L2_CNTL3__BANK_SELECT__SHIFT                                                               0x0
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                      0x6
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                  0x8
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                               0xf
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                               0x14
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                0x15
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                              0x18
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                    0x1c
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                  0x1d
>+#define VML2PF0_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                      0x1e
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                 0x1f
>+#define VML2PF0_VM_L2_CNTL3__BANK_SELECT_MASK                                                                 0x0000003FL
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                        0x000000C0L
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                    0x00001F00L
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                 0x000F8000L
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                 0x00100000L
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                  0x00E00000L
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                0x0F000000L
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                      0x10000000L
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                    0x20000000L
>+#define VML2PF0_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                        0x40000000L
>+#define VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                   0x80000000L
>+//VML2PF0_VM_L2_STATUS
>+#define VML2PF0_VM_L2_STATUS__L2_BUSY__SHIFT                                                                  0x0
>+#define VML2PF0_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                      0x1
>+#define VML2PF0_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                         0x11
>+#define VML2PF0_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                       0x12
>+#define VML2PF0_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                           0x13
>+#define VML2PF0_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                           0x14
>+#define VML2PF0_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                           0x15
>+#define VML2PF0_VM_L2_STATUS__L2_BUSY_MASK                                                                    0x00000001L
>+#define VML2PF0_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                        0x0001FFFEL
>+#define VML2PF0_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                           0x00020000L
>+#define VML2PF0_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                         0x00040000L
>+#define VML2PF0_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                             0x00080000L
>+#define VML2PF0_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                             0x00100000L
>+#define VML2PF0_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                             0x00200000L
>+//VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL
>+#define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                      0x0
>+#define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                   0x1
>+#define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                      0x2
>+#define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                        0x00000001L
>+#define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                     0x00000002L
>+#define VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                        0x000000FCL
>+//VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32
>+#define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                    0x0
>+#define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                      0xFFFFFFFFL
>+//VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32
>+#define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                     0x0
>+#define VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                       0x0000000FL
>+//VML2PF0_VM_L2_PROTECTION_FAULT_CNTL
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                        0x0
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT     0x1
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                     0x2
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x3
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x4
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x5
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT         0x6
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x7
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                0x8
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                     0x9
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0xa
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                     0xb
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                   0xc
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                        0xd
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                  0x1d
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                   0x1e
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                      0x1f
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                          0x00000001L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK       0x00000002L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                       0x00000004L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000008L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000010L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000020L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK           0x00000040L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000080L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                  0x00000100L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                       0x00000200L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000400L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                       0x00000800L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                     0x00001000L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                          0x1FFFE000L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                    0x20000000L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                     0x40000000L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                        0x80000000L
>+//VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                            0x0
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                      0x10
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                0x11
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                     0x12
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                             0x13
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                              0x0000FFFFL
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                        0x00010000L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                  0x00020000L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                       0x00040000L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                               0x00080000L
>+//VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT          0x0
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK            0xFFFFFFFFL
>+//VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT         0x0
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK           0xFFFFFFFFL
>+//VML2PF0_VM_L2_PROTECTION_FAULT_STATUS
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                             0x0
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                            0x1
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                       0x4
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                           0x8
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                     0x9
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                      0x12
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                  0x13
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                    0x14
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                      0x18
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                    0x19
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                               0x00000001L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                              0x0000000EL
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                         0x000000F0L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                             0x00000100L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                       0x0003FE00L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                        0x00040000L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                    0x00080000L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                      0x00F00000L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                        0x01000000L
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                      0x1E000000L
>+//VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                               0x0
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                 0xFFFFFFFFL
>+//VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                0x0
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                  0x0000000FL
>+//VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                      0x0
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                        0xFFFFFFFFL
>+//VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                       0x0
>+#define VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                         0x0000000FL
>+//VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
>+#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT               0x0
>+#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                 0xFFFFFFFFL
>+//VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
>+#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                0x0
>+#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                  0x0000000FL
>+//VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
>+#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT              0x0
>+#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                0xFFFFFFFFL
>+//VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
>+#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT               0x0
>+#define VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                 0x0000000FL
>+//VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
>+#define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                 0x0
>+#define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                   0xFFFFFFFFL
>+//VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
>+#define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                  0x0
>+#define VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                    0x0000000FL
>+//VML2PF0_VM_L2_CNTL4
>+#define VML2PF0_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                               0x0
>+#define VML2PF0_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                              0x6
>+#define VML2PF0_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                              0x7
>+#define VML2PF0_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                   0x8
>+#define VML2PF0_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                  0x12
>+#define VML2PF0_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                       0x1c
>+#define VML2PF0_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                 0x0000003FL
>+#define VML2PF0_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                0x00000040L
>+#define VML2PF0_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                0x00000080L
>+#define VML2PF0_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                     0x0003FF00L
>+#define VML2PF0_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                    0x0FFC0000L
>+#define VML2PF0_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                         0x10000000L
>+//VML2PF0_VM_L2_MM_GROUP_RT_CLASSES
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                            0x0
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                            0x1
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                            0x2
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                            0x3
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                            0x4
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                            0x5
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                            0x6
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                            0x7
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                            0x8
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                            0x9
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                           0xa
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                           0xb
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                           0xc
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                           0xd
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                           0xe
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                           0xf
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                           0x10
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                           0x11
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                           0x12
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                           0x13
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                           0x14
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                           0x15
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                           0x16
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                           0x17
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                           0x18
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                           0x19
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                           0x1a
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                           0x1b
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                           0x1c
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                           0x1d
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                           0x1e
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                           0x1f
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                              0x00000001L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                              0x00000002L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                              0x00000004L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                              0x00000008L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                              0x00000010L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                              0x00000020L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                              0x00000040L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                              0x00000080L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                              0x00000100L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                              0x00000200L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                             0x00000400L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                             0x00000800L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                             0x00001000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                             0x00002000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                             0x00004000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                             0x00008000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                             0x00010000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                             0x00020000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                             0x00040000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                             0x00080000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                             0x00100000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                             0x00200000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                             0x00400000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                             0x00800000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                             0x01000000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                             0x02000000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                             0x04000000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                             0x08000000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                             0x10000000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                             0x20000000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                             0x40000000L
>+#define VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                             0x80000000L
>+//VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                0x0
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                               0xa
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                 0x14
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                       0x18
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                    0x19
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                  0x000001FFL
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                 0x0007FC00L
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                   0x00100000L
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                         0x01000000L
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                      0x02000000L
>+//VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                               0x0
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                              0xa
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                0x14
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                      0x18
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                   0x19
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                 0x000001FFL
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                0x0007FC00L
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                  0x00100000L
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                        0x01000000L
>+#define VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                     0x02000000L
>+//VML2PF0_VM_L2_CACHE_PARITY_CNTL
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                         0x0
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                       0x1
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                            0x2
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                         0x3
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                       0x4
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                            0x5
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                              0x6
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                            0x9
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                             0xc
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                           0x00000001L
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                         0x00000002L
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                              0x00000004L
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                           0x00000008L
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                         0x00000010L
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                              0x00000020L
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                0x000001C0L
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                              0x00000E00L
>+#define VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                               0x0000F000L
>+//VML2PF0_VM_L2_CGTT_CLK_CTRL
>+#define VML2PF0_VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                          0x0
>+#define VML2PF0_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                    0x4
>+#define VML2PF0_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                     0xf
>+#define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                               0x10
>+#define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                     0x18
>+#define VML2PF0_VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                            0x0000000FL
>+#define VML2PF0_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                      0x00000FF0L
>+#define VML2PF0_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                       0x00008000L
>+#define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                 0x00FF0000L
>+#define VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                       0xFF000000L
>+
>+
>+// addressBlock: mmhub_utcl2_vml2vcdec
>+//VML2VC0_VM_CONTEXT0_CNTL
>+#define VML2VC0_VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC0_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC0_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC0_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC0_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC0_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC0_VM_CONTEXT1_CNTL
>+#define VML2VC0_VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC0_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC0_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC0_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC0_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC0_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC0_VM_CONTEXT2_CNTL
>+#define VML2VC0_VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC0_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC0_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC0_VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC0_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC0_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC0_VM_CONTEXT3_CNTL
>+#define VML2VC0_VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC0_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC0_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC0_VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC0_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC0_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC0_VM_CONTEXT4_CNTL
>+#define VML2VC0_VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC0_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC0_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC0_VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC0_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC0_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC0_VM_CONTEXT5_CNTL
>+#define VML2VC0_VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC0_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC0_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC0_VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC0_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC0_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC0_VM_CONTEXT6_CNTL
>+#define VML2VC0_VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC0_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC0_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC0_VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC0_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC0_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC0_VM_CONTEXT7_CNTL
>+#define VML2VC0_VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC0_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC0_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC0_VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC0_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC0_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC0_VM_CONTEXT8_CNTL
>+#define VML2VC0_VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC0_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC0_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC0_VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC0_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC0_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC0_VM_CONTEXT9_CNTL
>+#define VML2VC0_VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC0_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC0_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC0_VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC0_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC0_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC0_VM_CONTEXT10_CNTL
>+#define VML2VC0_VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
>+#define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
>+#define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
>+#define VML2VC0_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
>+#define VML2VC0_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
>+#define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
>+#define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
>+#define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
>+#define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
>+#define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
>+#define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
>+#define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
>+#define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
>+#define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
>+#define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
>+#define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
>+#define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
>+#define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
>+#define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
>+#define VML2VC0_VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
>+#define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
>+#define VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
>+#define VML2VC0_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
>+#define VML2VC0_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
>+#define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
>+#define VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
>+#define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
>+#define VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
>+#define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
>+#define VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
>+#define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
>+#define VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
>+#define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
>+#define VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
>+#define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
>+#define VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
>+#define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
>+#define VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
>+//VML2VC0_VM_CONTEXT11_CNTL
>+#define VML2VC0_VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
>+#define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
>+#define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
>+#define VML2VC0_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
>+#define VML2VC0_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
>+#define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
>+#define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
>+#define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
>+#define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
>+#define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
>+#define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
>+#define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
>+#define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
>+#define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
>+#define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
>+#define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
>+#define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
>+#define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
>+#define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
>+#define VML2VC0_VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
>+#define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
>+#define VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
>+#define VML2VC0_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
>+#define VML2VC0_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
>+#define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
>+#define VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
>+#define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
>+#define VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
>+#define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
>+#define VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
>+#define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
>+#define VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
>+#define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
>+#define VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
>+#define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
>+#define VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
>+#define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
>+#define VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
>+//VML2VC0_VM_CONTEXT12_CNTL
>+#define VML2VC0_VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
>+#define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
>+#define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
>+#define VML2VC0_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
>+#define VML2VC0_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
>+#define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
>+#define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
>+#define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
>+#define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
>+#define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
>+#define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
>+#define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
>+#define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
>+#define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
>+#define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
>+#define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
>+#define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
>+#define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
>+#define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
>+#define VML2VC0_VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
>+#define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
>+#define VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
>+#define VML2VC0_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
>+#define VML2VC0_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
>+#define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
>+#define VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
>+#define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
>+#define VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
>+#define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
>+#define VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
>+#define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
>+#define VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
>+#define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
>+#define VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
>+#define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
>+#define VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
>+#define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
>+#define VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
>+//VML2VC0_VM_CONTEXT13_CNTL
>+#define VML2VC0_VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
>+#define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
>+#define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
>+#define VML2VC0_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
>+#define VML2VC0_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
>+#define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
>+#define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
>+#define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
>+#define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
>+#define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
>+#define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
>+#define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
>+#define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
>+#define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
>+#define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
>+#define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
>+#define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
>+#define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
>+#define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
>+#define VML2VC0_VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
>+#define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
>+#define VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
>+#define VML2VC0_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
>+#define VML2VC0_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
>+#define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
>+#define VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
>+#define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
>+#define VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
>+#define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
>+#define VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
>+#define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
>+#define VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
>+#define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
>+#define VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
>+#define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
>+#define VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
>+#define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
>+#define VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
>+//VML2VC0_VM_CONTEXT14_CNTL
>+#define VML2VC0_VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
>+#define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
>+#define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
>+#define VML2VC0_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
>+#define VML2VC0_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
>+#define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
>+#define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
>+#define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
>+#define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
>+#define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
>+#define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
>+#define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
>+#define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
>+#define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
>+#define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
>+#define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
>+#define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
>+#define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
>+#define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
>+#define VML2VC0_VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
>+#define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
>+#define VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
>+#define VML2VC0_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
>+#define VML2VC0_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
>+#define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
>+#define VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
>+#define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
>+#define VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
>+#define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
>+#define VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
>+#define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
>+#define VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
>+#define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
>+#define VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
>+#define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
>+#define VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
>+#define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
>+#define VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
>+//VML2VC0_VM_CONTEXT15_CNTL
>+#define VML2VC0_VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
>+#define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
>+#define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
>+#define VML2VC0_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
>+#define VML2VC0_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
>+#define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
>+#define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
>+#define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
>+#define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
>+#define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
>+#define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
>+#define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
>+#define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
>+#define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
>+#define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
>+#define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
>+#define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
>+#define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
>+#define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
>+#define VML2VC0_VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
>+#define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
>+#define VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
>+#define VML2VC0_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
>+#define VML2VC0_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
>+#define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
>+#define VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
>+#define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
>+#define VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
>+#define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
>+#define VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
>+#define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
>+#define VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
>+#define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
>+#define VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
>+#define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
>+#define VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
>+#define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
>+#define VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
>+//VML2VC0_VM_CONTEXTS_DISABLE
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                 0x0
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                 0x1
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                 0x2
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                 0x3
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                 0x4
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                 0x5
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                 0x6
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                 0x7
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                 0x8
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                 0x9
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                0xa
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                0xb
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                0xc
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                0xd
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                0xe
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                0xf
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                   0x00000001L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                   0x00000002L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                   0x00000004L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                   0x00000008L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                   0x00000010L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                   0x00000020L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                   0x00000040L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                   0x00000080L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                   0x00000100L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                   0x00000200L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                  0x00000400L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                  0x00000800L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                  0x00001000L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                  0x00002000L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                  0x00004000L
>+#define VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                  0x00008000L
>+//VML2VC0_VM_INVALIDATE_ENG0_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC0_VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG1_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC0_VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG2_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC0_VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG3_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC0_VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG4_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC0_VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG5_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC0_VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG6_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC0_VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG7_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC0_VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG8_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC0_VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG9_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC0_VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG10_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC0_VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG11_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC0_VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG12_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC0_VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG13_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC0_VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG14_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC0_VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG15_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC0_VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG16_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC0_VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG17_SEM
>+#define VML2VC0_VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC0_VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC0_VM_INVALIDATE_ENG0_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG1_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG2_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG3_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG4_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG5_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG6_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG7_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG8_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG9_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG10_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG11_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG12_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG13_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG14_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG15_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG16_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG17_REQ
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC0_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC0_VM_INVALIDATE_ENG0_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC0_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG1_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC0_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG2_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC0_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG3_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC0_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG4_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC0_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG5_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC0_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG6_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC0_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG7_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC0_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG8_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC0_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG9_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC0_VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC0_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG10_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG11_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG12_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG13_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG14_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG15_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG16_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG17_ACK
>+#define VML2VC0_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC0_VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC0_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC0_VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
>+#define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
>+#define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
>+//VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
>+//VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
>+//VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
>+//VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
>+//VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
>+#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
>+#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
>+//VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
>+//VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
>+//VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
>+//VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
>+//VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
>+//VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
>+#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
>+//VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
>+#define VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedpfdec
>+//VMSHAREDPF0_MC_VM_NB_MMIOBASE
>+#define VMSHAREDPF0_MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT                                                        0x0
>+#define VMSHAREDPF0_MC_VM_NB_MMIOBASE__MMIOBASE_MASK                                                          0xFFFFFFFFL
>+//VMSHAREDPF0_MC_VM_NB_MMIOLIMIT
>+#define VMSHAREDPF0_MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                      0x0
>+#define VMSHAREDPF0_MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK                                                        0xFFFFFFFFL
>+//VMSHAREDPF0_MC_VM_NB_PCI_CTRL
>+#define VMSHAREDPF0_MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT                                                      0x17
>+#define VMSHAREDPF0_MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK                                                        0x00800000L
>+//VMSHAREDPF0_MC_VM_NB_PCI_ARB
>+#define VMSHAREDPF0_MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT                                                         0x3
>+#define VMSHAREDPF0_MC_VM_NB_PCI_ARB__VGA_HOLE_MASK                                                           0x00000008L
>+//VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1
>+#define VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT                                            0x17
>+#define VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK                                              0xFF800000L
>+//VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2
>+#define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                0x0
>+#define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                            0x17
>+#define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                  0x00000001L
>+#define VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                              0xFF800000L
>+//VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2
>+#define VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                            0x0
>+#define VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                              0x00000FFFL
>+//VMSHAREDPF0_MC_VM_FB_OFFSET
>+#define VMSHAREDPF0_MC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                         0x0
>+#define VMSHAREDPF0_MC_VM_FB_OFFSET__FB_OFFSET_MASK                                                           0x00FFFFFFL
>+//VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
>+#define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                   0x0
>+#define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                     0xFFFFFFFFL
>+//VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
>+#define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                   0x0
>+#define VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                     0x0000000FL
>+//VMSHAREDPF0_MC_VM_STEERING
>+#define VMSHAREDPF0_MC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                   0x0
>+#define VMSHAREDPF0_MC_VM_STEERING__DEFAULT_STEERING_MASK                                                     0x00000003L
>+//VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ
>+#define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                       0x0
>+#define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                       0x1f
>+#define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__VF_MASK                                                         0x0000FFFFL
>+#define VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__PF_MASK                                                         0x80000000L
>+//VMSHAREDPF0_MC_MEM_POWER_LS
>+#define VMSHAREDPF0_MC_MEM_POWER_LS__LS_SETUP__SHIFT                                                          0x0
>+#define VMSHAREDPF0_MC_MEM_POWER_LS__LS_HOLD__SHIFT                                                           0x6
>+#define VMSHAREDPF0_MC_MEM_POWER_LS__LS_SETUP_MASK                                                            0x0000003FL
>+#define VMSHAREDPF0_MC_MEM_POWER_LS__LS_HOLD_MASK                                                             0x00000FC0L
>+//VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START
>+#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                        0x0
>+#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                          0x000FFFFFL
>+//VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END
>+#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                          0x0
>+#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                            0x000FFFFFL
>+//VMSHAREDPF0_MC_VM_APT_CNTL
>+#define VMSHAREDPF0_MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                     0x0
>+#define VMSHAREDPF0_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                   0x1
>+#define VMSHAREDPF0_MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                       0x00000001L
>+#define VMSHAREDPF0_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                     0x00000002L
>+//VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START
>+#define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT                                             0x0
>+#define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK                                               0x000FFFFFL
>+//VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END
>+#define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT                                               0x0
>+#define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK                                                 0x000FFFFFL
>+//VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
>+#define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                            0x0
>+#define VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                              0x00000001L
>+//VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL
>+#define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT                                                 0x0
>+#define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT                                                 0x4
>+#define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK                                                   0x0000000FL
>+#define VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK                                                   0x000000F0L
>+//VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE
>+#define VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT                                                   0x0
>+#define VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK                                                     0x0001FFFFL
>+//VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL
>+#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT                  0x0
>+#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK                    0x00000001L
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedvcdec
>+//VMSHAREDVC0_MC_VM_FB_LOCATION_BASE
>+#define VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                    0x0
>+#define VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                      0x00FFFFFFL
>+//VMSHAREDVC0_MC_VM_FB_LOCATION_TOP
>+#define VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                      0x0
>+#define VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                        0x00FFFFFFL
>+//VMSHAREDVC0_MC_VM_AGP_TOP
>+#define VMSHAREDVC0_MC_VM_AGP_TOP__AGP_TOP__SHIFT                                                             0x0
>+#define VMSHAREDVC0_MC_VM_AGP_TOP__AGP_TOP_MASK                                                               0x00FFFFFFL
>+//VMSHAREDVC0_MC_VM_AGP_BOT
>+#define VMSHAREDVC0_MC_VM_AGP_BOT__AGP_BOT__SHIFT                                                             0x0
>+#define VMSHAREDVC0_MC_VM_AGP_BOT__AGP_BOT_MASK                                                               0x00FFFFFFL
>+//VMSHAREDVC0_MC_VM_AGP_BASE
>+#define VMSHAREDVC0_MC_VM_AGP_BASE__AGP_BASE__SHIFT                                                           0x0
>+#define VMSHAREDVC0_MC_VM_AGP_BASE__AGP_BASE_MASK                                                             0x00FFFFFFL
>+//VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR
>+#define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                       0x0
>+#define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                         0x3FFFFFFFL
>+//VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
>+#define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                      0x0
>+#define VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                        0x3FFFFFFFL
>+//VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                0x0
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                           0x3
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                              0x5
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                 0x6
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                     0x7
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                        0xb
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT                                                       0xd
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                  0x00000001L
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                             0x00000018L
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                0x00000020L
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                   0x00000040L
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                       0x00000780L
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                          0x00001800L
>+#define VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK                                                         0x00002000L
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedhvdec
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT                                              0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT                                            0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK                                                0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK                                              0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT                                              0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT                                            0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK                                                0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK                                              0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT                                              0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT                                            0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK                                                0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK                                              0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT                                              0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT                                            0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK                                                0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK                                              0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT                                              0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT                                            0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK                                                0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK                                              0xFFFF0000L
>+//VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT                                              0x0
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT                                            0x10
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK                                                0x0000FFFFL
>+#define VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK                                              0xFFFF0000L
>+//VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1
>+#define VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT                                                     0x8
>+#define VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK                                                       0x00000100L
>+//VMSHAREDHV0_MC_VM_MARC_BASE_LO_0
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT                                               0xc
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK                                                 0xFFFFF000L
>+//VMSHAREDHV0_MC_VM_MARC_BASE_LO_1
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT                                               0xc
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK                                                 0xFFFFF000L
>+//VMSHAREDHV0_MC_VM_MARC_BASE_LO_2
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT                                               0xc
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK                                                 0xFFFFF000L
>+//VMSHAREDHV0_MC_VM_MARC_BASE_LO_3
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT                                               0xc
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK                                                 0xFFFFF000L
>+//VMSHAREDHV0_MC_VM_MARC_BASE_HI_0
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK                                                 0x000FFFFFL
>+//VMSHAREDHV0_MC_VM_MARC_BASE_HI_1
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK                                                 0x000FFFFFL
>+//VMSHAREDHV0_MC_VM_MARC_BASE_HI_2
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK                                                 0x000FFFFFL
>+//VMSHAREDHV0_MC_VM_MARC_BASE_HI_3
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK                                                 0x000FFFFFL
>+//VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT                                             0x1
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT                                             0xc
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK                                                 0x00000001L
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK                                               0x00000002L
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK                                               0xFFFFF000L
>+//VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT                                             0x1
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT                                             0xc
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK                                                 0x00000001L
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK                                               0x00000002L
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK                                               0xFFFFF000L
>+//VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT                                             0x1
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT                                             0xc
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK                                                 0x00000001L
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK                                               0x00000002L
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK                                               0xFFFFF000L
>+//VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT                                             0x1
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT                                             0xc
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK                                                 0x00000001L
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK                                               0x00000002L
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK                                               0xFFFFF000L
>+//VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT                                             0x0
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK                                               0x000FFFFFL
>+//VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT                                             0x0
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK                                               0x000FFFFFL
>+//VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT                                             0x0
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK                                               0x000FFFFFL
>+//VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT                                             0x0
>+#define VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK                                               0x000FFFFFL
>+//VMSHAREDHV0_MC_VM_MARC_LEN_LO_0
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT                                                 0xc
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK                                                   0xFFFFF000L
>+//VMSHAREDHV0_MC_VM_MARC_LEN_LO_1
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT                                                 0xc
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK                                                   0xFFFFF000L
>+//VMSHAREDHV0_MC_VM_MARC_LEN_LO_2
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT                                                 0xc
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK                                                   0xFFFFF000L
>+//VMSHAREDHV0_MC_VM_MARC_LEN_LO_3
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT                                                 0xc
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK                                                   0xFFFFF000L
>+//VMSHAREDHV0_MC_VM_MARC_LEN_HI_0
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT                                                 0x0
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK                                                   0x000FFFFFL
>+//VMSHAREDHV0_MC_VM_MARC_LEN_HI_1
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT                                                 0x0
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK                                                   0x000FFFFFL
>+//VMSHAREDHV0_MC_VM_MARC_LEN_HI_2
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT                                                 0x0
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK                                                   0x000FFFFFL
>+//VMSHAREDHV0_MC_VM_MARC_LEN_HI_3
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT                                                 0x0
>+#define VMSHAREDHV0_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK                                                   0x000FFFFFL
>+//VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER
>+#define VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                 0x0
>+#define VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK                                                   0x00000001L
>+//VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
>+#define VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT                      0xd
>+#define VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK                        0x00002000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL__STU__SHIFT                                                              0x10
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                       0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL__STU_MASK                                                                0x001F0000L
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                         0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT                                                 0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK                                                   0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT                                                 0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK                                                   0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT                                                 0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK                                                   0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT                                                 0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK                                                   0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT                                                 0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK                                                   0x80000000L
>+//VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT                                                 0x1f
>+#define VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK                                                   0x80000000L
>+//VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL
>+#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                      0x0
>+#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                0x4
>+#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT                                           0xc
>+#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                 0xf
>+#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                           0x10
>+#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                 0x18
>+#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                        0x0000000FL
>+#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                  0x00000FF0L
>+#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK                                             0x00007000L
>+#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                   0x00008000L
>+#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                             0x00FF0000L
>+#define VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                   0xFF000000L
>+//VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID
>+#define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT                                                      0x0
>+#define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT                                                        0x1f
>+#define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VFID_MASK                                                        0x0000000FL
>+#define VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VF_MASK                                                          0x80000000L
>+//VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT                                               0x0
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT                                               0x1
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT                                               0x2
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT                                               0x3
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT                                               0x4
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT                                               0x5
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT                                               0x6
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT                                               0x7
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT                                               0x8
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT                                               0x9
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT                                              0xa
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT                                              0xb
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT                                              0xc
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT                                              0xd
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT                                              0xe
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT                                              0xf
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT                                                0x1f
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK                                                 0x00000001L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK                                                 0x00000002L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK                                                 0x00000004L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK                                                 0x00000008L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK                                                 0x00000010L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK                                                 0x00000020L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK                                                 0x00000040L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK                                                 0x00000080L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK                                                 0x00000100L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK                                                 0x00000200L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK                                                0x00000400L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK                                                0x00000800L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK                                                0x00001000L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK                                                0x00002000L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK                                                0x00004000L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK                                                0x00008000L
>+#define VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK                                                  0x80000000L
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2pfcntrdec
>+//ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO
>+#define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                 0x0
>+#define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                   0xFFFFFFFFL
>+//ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI
>+#define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                 0x0
>+#define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                              0x10
>+#define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                   0x0000FFFFL
>+#define ATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                0xFFFF0000L
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2pfcntldec
>+//ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                 0x0
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                             0x8
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                0x18
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                   0x1c
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                    0x1d
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                   0x000000FFL
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                  0x0F000000L
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                     0x10000000L
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                      0x20000000L
>+//ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                 0x0
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                             0x8
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                0x18
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                   0x1c
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                    0x1d
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                   0x000000FFL
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                  0x0F000000L
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                     0x10000000L
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                      0x20000000L
>+//ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                 0x0
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                       0x8
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                        0x10
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                          0x18
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                           0x19
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                0x1a
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                   0x0000000FL
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                         0x0000FF00L
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                          0x00FF0000L
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                            0x01000000L
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                             0x02000000L
>+#define ATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                  0x04000000L
>+
>+
>+// addressBlock: mmhub_utcl2_vml2pldec
>+//VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                    0x0
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                          0x8
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                           0x10
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                             0x18
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                              0x19
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                   0x1a
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                      0x0000000FL
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                            0x0000FF00L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                             0x00FF0000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                               0x01000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                0x02000000L
>+#define VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                     0x04000000L
>+
>+
>+// addressBlock: mmhub_utcl2_vml2prdec
>+//VML2PR0_MC_VM_L2_PERFCOUNTER_LO
>+#define VML2PR0_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                    0x0
>+#define VML2PR0_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                      0xFFFFFFFFL
>+//VML2PR0_MC_VM_L2_PERFCOUNTER_HI
>+#define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                    0x0
>+#define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                 0x10
>+#define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                      0x0000FFFFL
>+#define VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                   0xFFFF0000L
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec5
>+//DAGB5_RDCLI0
>+#define DAGB5_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_RDCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_RDCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_RDCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_RDCLI1
>+#define DAGB5_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_RDCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_RDCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_RDCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_RDCLI2
>+#define DAGB5_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_RDCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_RDCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_RDCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_RDCLI3
>+#define DAGB5_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_RDCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_RDCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_RDCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_RDCLI4
>+#define DAGB5_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_RDCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_RDCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_RDCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_RDCLI5
>+#define DAGB5_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_RDCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_RDCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_RDCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_RDCLI6
>+#define DAGB5_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_RDCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_RDCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_RDCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_RDCLI7
>+#define DAGB5_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_RDCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_RDCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_RDCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_RDCLI8
>+#define DAGB5_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_RDCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_RDCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_RDCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_RDCLI9
>+#define DAGB5_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_RDCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_RDCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_RDCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_RDCLI10
>+#define DAGB5_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB5_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB5_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB5_RDCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB5_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB5_RDCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB5_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB5_RDCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB5_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB5_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB5_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB5_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB5_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB5_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB5_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB5_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB5_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB5_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB5_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB5_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB5_RDCLI11
>+#define DAGB5_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB5_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB5_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB5_RDCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB5_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB5_RDCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB5_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB5_RDCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB5_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB5_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB5_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB5_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB5_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB5_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB5_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB5_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB5_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB5_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB5_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB5_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB5_RDCLI12
>+#define DAGB5_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB5_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB5_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB5_RDCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB5_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB5_RDCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB5_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB5_RDCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB5_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB5_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB5_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB5_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB5_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB5_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB5_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB5_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB5_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB5_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB5_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB5_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB5_RDCLI13
>+#define DAGB5_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB5_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB5_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB5_RDCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB5_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB5_RDCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB5_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB5_RDCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB5_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB5_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB5_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB5_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB5_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB5_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB5_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB5_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB5_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB5_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB5_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB5_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB5_RDCLI14
>+#define DAGB5_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB5_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB5_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB5_RDCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB5_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB5_RDCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB5_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB5_RDCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB5_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB5_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB5_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB5_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB5_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB5_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB5_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB5_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB5_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB5_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB5_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB5_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB5_RDCLI15
>+#define DAGB5_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB5_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB5_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB5_RDCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB5_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB5_RDCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB5_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB5_RDCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB5_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB5_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB5_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB5_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB5_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB5_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB5_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB5_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB5_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB5_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB5_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB5_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB5_RD_CNTL
>+#define DAGB5_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB5_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB5_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB5_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB5_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB5_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB5_RD_GMI_CNTL
>+#define DAGB5_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB5_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB5_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB5_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB5_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB5_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB5_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB5_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB5_RD_ADDR_DAGB
>+#define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB5_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB5_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB5_RD_OUTPUT_DAGB_MAX_BURST
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB5_RD_CGTT_CLK_CTRL
>+#define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB5_L1TLB_RD_CGTT_CLK_CTRL
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB5_ATCVM_RD_CGTT_CLK_CTRL
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB5_RD_ADDR_DAGB_MAX_BURST0
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB5_RD_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB5_RD_ADDR_DAGB_MAX_BURST1
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB5_RD_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB5_RD_VC0_CNTL
>+#define DAGB5_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_RD_VC1_CNTL
>+#define DAGB5_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_RD_VC2_CNTL
>+#define DAGB5_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_RD_VC3_CNTL
>+#define DAGB5_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_RD_VC4_CNTL
>+#define DAGB5_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_RD_VC5_CNTL
>+#define DAGB5_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_RD_VC6_CNTL
>+#define DAGB5_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_RD_VC7_CNTL
>+#define DAGB5_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_RD_CNTL_MISC
>+#define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB5_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB5_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB5_RD_TLB_CREDIT
>+#define DAGB5_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB5_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB5_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB5_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB5_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB5_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB5_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB5_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB5_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB5_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB5_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB5_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB5_RDCLI_ASK_PENDING
>+#define DAGB5_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB5_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB5_RDCLI_GO_PENDING
>+#define DAGB5_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB5_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB5_RDCLI_GBLSEND_PENDING
>+#define DAGB5_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB5_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB5_RDCLI_TLB_PENDING
>+#define DAGB5_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB5_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB5_RDCLI_OARB_PENDING
>+#define DAGB5_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB5_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB5_RDCLI_OSD_PENDING
>+#define DAGB5_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB5_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB5_WRCLI0
>+#define DAGB5_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_WRCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_WRCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_WRCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_WRCLI1
>+#define DAGB5_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_WRCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_WRCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_WRCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_WRCLI2
>+#define DAGB5_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_WRCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_WRCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_WRCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_WRCLI3
>+#define DAGB5_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_WRCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_WRCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_WRCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_WRCLI4
>+#define DAGB5_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_WRCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_WRCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_WRCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_WRCLI5
>+#define DAGB5_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_WRCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_WRCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_WRCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_WRCLI6
>+#define DAGB5_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_WRCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_WRCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_WRCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_WRCLI7
>+#define DAGB5_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_WRCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_WRCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_WRCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_WRCLI8
>+#define DAGB5_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_WRCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_WRCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_WRCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_WRCLI9
>+#define DAGB5_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB5_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB5_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB5_WRCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB5_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB5_WRCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB5_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB5_WRCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB5_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB5_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB5_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB5_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB5_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB5_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB5_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB5_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB5_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB5_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB5_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB5_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB5_WRCLI10
>+#define DAGB5_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB5_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB5_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB5_WRCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB5_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB5_WRCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB5_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB5_WRCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB5_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB5_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB5_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB5_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB5_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB5_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB5_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB5_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB5_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB5_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB5_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB5_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB5_WRCLI11
>+#define DAGB5_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB5_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB5_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB5_WRCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB5_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB5_WRCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB5_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB5_WRCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB5_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB5_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB5_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB5_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB5_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB5_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB5_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB5_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB5_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB5_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB5_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB5_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB5_WRCLI12
>+#define DAGB5_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB5_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB5_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB5_WRCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB5_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB5_WRCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB5_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB5_WRCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB5_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB5_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB5_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB5_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB5_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB5_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB5_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB5_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB5_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB5_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB5_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB5_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB5_WRCLI13
>+#define DAGB5_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB5_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB5_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB5_WRCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB5_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB5_WRCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB5_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB5_WRCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB5_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB5_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB5_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB5_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB5_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB5_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB5_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB5_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB5_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB5_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB5_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB5_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB5_WRCLI14
>+#define DAGB5_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB5_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB5_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB5_WRCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB5_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB5_WRCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB5_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB5_WRCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB5_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB5_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB5_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB5_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB5_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB5_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB5_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB5_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB5_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB5_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB5_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB5_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB5_WRCLI15
>+#define DAGB5_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB5_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB5_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB5_WRCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB5_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB5_WRCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB5_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB5_WRCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB5_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB5_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB5_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB5_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB5_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB5_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB5_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB5_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB5_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB5_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB5_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB5_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB5_WR_CNTL
>+#define DAGB5_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB5_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB5_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB5_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB5_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB5_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB5_WR_GMI_CNTL
>+#define DAGB5_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB5_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB5_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB5_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB5_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB5_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB5_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB5_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB5_WR_ADDR_DAGB
>+#define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB5_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB5_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB5_WR_OUTPUT_DAGB_MAX_BURST
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB5_WR_CGTT_CLK_CTRL
>+#define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB5_L1TLB_WR_CGTT_CLK_CTRL
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB5_ATCVM_WR_CGTT_CLK_CTRL
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB5_WR_ADDR_DAGB_MAX_BURST0
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB5_WR_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB5_WR_ADDR_DAGB_MAX_BURST1
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB5_WR_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB5_WR_DATA_DAGB
>+#define DAGB5_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB5_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB5_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB5_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB5_WR_DATA_DAGB_MAX_BURST0
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB5_WR_DATA_DAGB_LAZY_TIMER0
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB5_WR_DATA_DAGB_MAX_BURST1
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB5_WR_DATA_DAGB_LAZY_TIMER1
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB5_WR_VC0_CNTL
>+#define DAGB5_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_WR_VC1_CNTL
>+#define DAGB5_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_WR_VC2_CNTL
>+#define DAGB5_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_WR_VC3_CNTL
>+#define DAGB5_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_WR_VC4_CNTL
>+#define DAGB5_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_WR_VC5_CNTL
>+#define DAGB5_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_WR_VC6_CNTL
>+#define DAGB5_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_WR_VC7_CNTL
>+#define DAGB5_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB5_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB5_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB5_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB5_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB5_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB5_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB5_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB5_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB5_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB5_WR_CNTL_MISC
>+#define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB5_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB5_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB5_WR_TLB_CREDIT
>+#define DAGB5_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB5_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB5_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB5_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB5_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB5_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB5_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB5_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB5_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB5_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB5_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB5_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB5_WR_DATA_CREDIT
>+#define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
>+#define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
>+#define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
>+#define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
>+#define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
>+#define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
>+#define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
>+#define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
>+//DAGB5_WR_MISC_CREDIT
>+#define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
>+#define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
>+#define DAGB5_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
>+#define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
>+#define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
>+#define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
>+#define DAGB5_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
>+#define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
>+//DAGB5_WRCLI_ASK_PENDING
>+#define DAGB5_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB5_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB5_WRCLI_GO_PENDING
>+#define DAGB5_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB5_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB5_WRCLI_GBLSEND_PENDING
>+#define DAGB5_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB5_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB5_WRCLI_TLB_PENDING
>+#define DAGB5_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB5_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB5_WRCLI_OARB_PENDING
>+#define DAGB5_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB5_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB5_WRCLI_OSD_PENDING
>+#define DAGB5_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB5_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB5_WRCLI_DBUS_ASK_PENDING
>+#define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
>+#define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
>+//DAGB5_WRCLI_DBUS_GO_PENDING
>+#define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB5_DAGB_DLY
>+#define DAGB5_DAGB_DLY__DLY__SHIFT                                                                            0x0
>+#define DAGB5_DAGB_DLY__CLI__SHIFT                                                                            0x8
>+#define DAGB5_DAGB_DLY__POS__SHIFT                                                                            0x10
>+#define DAGB5_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
>+#define DAGB5_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
>+#define DAGB5_DAGB_DLY__POS_MASK                                                                              0x000F0000L
>+//DAGB5_CNTL_MISC
>+#define DAGB5_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
>+#define DAGB5_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
>+#define DAGB5_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
>+#define DAGB5_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
>+#define DAGB5_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
>+#define DAGB5_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
>+#define DAGB5_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
>+#define DAGB5_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
>+#define DAGB5_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
>+#define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
>+#define DAGB5_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
>+#define DAGB5_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
>+#define DAGB5_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
>+#define DAGB5_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
>+#define DAGB5_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
>+#define DAGB5_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
>+#define DAGB5_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
>+#define DAGB5_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
>+#define DAGB5_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
>+#define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
>+//DAGB5_CNTL_MISC2
>+#define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
>+#define DAGB5_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
>+#define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
>+#define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
>+#define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
>+#define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
>+#define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
>+#define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
>+#define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
>+#define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
>+#define DAGB5_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
>+#define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
>+#define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
>+#define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
>+#define DAGB5_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
>+#define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
>+#define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
>+#define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
>+#define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
>+#define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
>+#define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
>+#define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
>+#define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
>+#define DAGB5_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
>+#define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
>+#define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
>+//DAGB5_FIFO_EMPTY
>+#define DAGB5_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
>+#define DAGB5_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
>+//DAGB5_FIFO_FULL
>+#define DAGB5_FIFO_FULL__FULL__SHIFT                                                                          0x0
>+#define DAGB5_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
>+//DAGB5_WR_CREDITS_FULL
>+#define DAGB5_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB5_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
>+//DAGB5_RD_CREDITS_FULL
>+#define DAGB5_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB5_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
>+//DAGB5_PERFCOUNTER_LO
>+#define DAGB5_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define DAGB5_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//DAGB5_PERFCOUNTER_HI
>+#define DAGB5_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define DAGB5_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//DAGB5_PERFCOUNTER0_CFG
>+#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB5_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB5_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB5_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB5_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB5_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB5_PERFCOUNTER1_CFG
>+#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB5_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB5_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB5_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB5_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB5_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB5_PERFCOUNTER2_CFG
>+#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB5_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB5_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB5_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB5_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB5_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB5_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB5_PERFCOUNTER_RSLT_CNTL
>+#define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//DAGB5_RESERVE0
>+#define DAGB5_RESERVE0__RESERVE__SHIFT                                                                        0x0
>+#define DAGB5_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB5_RESERVE1
>+#define DAGB5_RESERVE1__RESERVE__SHIFT                                                                        0x0
>+#define DAGB5_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB5_RESERVE2
>+#define DAGB5_RESERVE2__RESERVE__SHIFT                                                                        0x0
>+#define DAGB5_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB5_RESERVE3
>+#define DAGB5_RESERVE3__RESERVE__SHIFT                                                                        0x0
>+#define DAGB5_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB5_RESERVE4
>+#define DAGB5_RESERVE4__RESERVE__SHIFT                                                                        0x0
>+#define DAGB5_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB5_RESERVE5
>+#define DAGB5_RESERVE5__RESERVE__SHIFT                                                                        0x0
>+#define DAGB5_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB5_RESERVE6
>+#define DAGB5_RESERVE6__RESERVE__SHIFT                                                                        0x0
>+#define DAGB5_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB5_RESERVE7
>+#define DAGB5_RESERVE7__RESERVE__SHIFT                                                                        0x0
>+#define DAGB5_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB5_RESERVE8
>+#define DAGB5_RESERVE8__RESERVE__SHIFT                                                                        0x0
>+#define DAGB5_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB5_RESERVE9
>+#define DAGB5_RESERVE9__RESERVE__SHIFT                                                                        0x0
>+#define DAGB5_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB5_RESERVE10
>+#define DAGB5_RESERVE10__RESERVE__SHIFT                                                                       0x0
>+#define DAGB5_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB5_RESERVE11
>+#define DAGB5_RESERVE11__RESERVE__SHIFT                                                                       0x0
>+#define DAGB5_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB5_RESERVE12
>+#define DAGB5_RESERVE12__RESERVE__SHIFT                                                                       0x0
>+#define DAGB5_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB5_RESERVE13
>+#define DAGB5_RESERVE13__RESERVE__SHIFT                                                                       0x0
>+#define DAGB5_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec6
>+//DAGB6_RDCLI0
>+#define DAGB6_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_RDCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_RDCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_RDCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_RDCLI1
>+#define DAGB6_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_RDCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_RDCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_RDCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_RDCLI2
>+#define DAGB6_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_RDCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_RDCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_RDCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_RDCLI3
>+#define DAGB6_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_RDCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_RDCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_RDCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_RDCLI4
>+#define DAGB6_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_RDCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_RDCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_RDCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_RDCLI5
>+#define DAGB6_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_RDCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_RDCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_RDCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_RDCLI6
>+#define DAGB6_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_RDCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_RDCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_RDCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_RDCLI7
>+#define DAGB6_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_RDCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_RDCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_RDCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_RDCLI8
>+#define DAGB6_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_RDCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_RDCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_RDCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_RDCLI9
>+#define DAGB6_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_RDCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_RDCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_RDCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_RDCLI10
>+#define DAGB6_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB6_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB6_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB6_RDCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB6_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB6_RDCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB6_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB6_RDCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB6_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB6_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB6_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB6_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB6_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB6_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB6_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB6_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB6_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB6_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB6_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB6_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB6_RDCLI11
>+#define DAGB6_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB6_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB6_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB6_RDCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB6_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB6_RDCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB6_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB6_RDCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB6_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB6_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB6_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB6_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB6_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB6_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB6_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB6_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB6_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB6_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB6_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB6_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB6_RDCLI12
>+#define DAGB6_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB6_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB6_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB6_RDCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB6_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB6_RDCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB6_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB6_RDCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB6_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB6_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB6_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB6_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB6_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB6_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB6_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB6_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB6_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB6_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB6_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB6_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB6_RDCLI13
>+#define DAGB6_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB6_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB6_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB6_RDCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB6_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB6_RDCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB6_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB6_RDCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB6_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB6_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB6_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB6_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB6_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB6_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB6_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB6_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB6_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB6_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB6_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB6_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB6_RDCLI14
>+#define DAGB6_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB6_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB6_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB6_RDCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB6_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB6_RDCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB6_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB6_RDCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB6_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB6_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB6_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB6_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB6_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB6_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB6_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB6_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB6_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB6_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB6_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB6_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB6_RDCLI15
>+#define DAGB6_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB6_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB6_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB6_RDCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB6_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB6_RDCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB6_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB6_RDCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB6_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB6_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB6_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB6_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB6_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB6_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB6_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB6_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB6_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB6_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB6_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB6_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB6_RD_CNTL
>+#define DAGB6_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB6_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB6_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB6_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB6_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB6_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB6_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB6_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB6_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB6_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB6_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB6_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB6_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB6_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB6_RD_GMI_CNTL
>+#define DAGB6_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB6_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB6_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB6_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB6_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB6_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB6_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB6_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB6_RD_ADDR_DAGB
>+#define DAGB6_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB6_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB6_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB6_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB6_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB6_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB6_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB6_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB6_RD_OUTPUT_DAGB_MAX_BURST
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB6_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB6_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB6_RD_CGTT_CLK_CTRL
>+#define DAGB6_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB6_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB6_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB6_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB6_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB6_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB6_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB6_L1TLB_RD_CGTT_CLK_CTRL
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB6_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB6_ATCVM_RD_CGTT_CLK_CTRL
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB6_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB6_RD_ADDR_DAGB_MAX_BURST0
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB6_RD_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB6_RD_ADDR_DAGB_MAX_BURST1
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB6_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB6_RD_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB6_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB6_RD_VC0_CNTL
>+#define DAGB6_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_RD_VC1_CNTL
>+#define DAGB6_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_RD_VC2_CNTL
>+#define DAGB6_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_RD_VC3_CNTL
>+#define DAGB6_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_RD_VC4_CNTL
>+#define DAGB6_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_RD_VC5_CNTL
>+#define DAGB6_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_RD_VC6_CNTL
>+#define DAGB6_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_RD_VC7_CNTL
>+#define DAGB6_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_RD_CNTL_MISC
>+#define DAGB6_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB6_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB6_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB6_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB6_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB6_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB6_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB6_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB6_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB6_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB6_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB6_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB6_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB6_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB6_RD_TLB_CREDIT
>+#define DAGB6_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB6_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB6_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB6_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB6_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB6_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB6_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB6_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB6_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB6_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB6_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB6_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB6_RDCLI_ASK_PENDING
>+#define DAGB6_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB6_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB6_RDCLI_GO_PENDING
>+#define DAGB6_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB6_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB6_RDCLI_GBLSEND_PENDING
>+#define DAGB6_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB6_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB6_RDCLI_TLB_PENDING
>+#define DAGB6_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB6_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB6_RDCLI_OARB_PENDING
>+#define DAGB6_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB6_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB6_RDCLI_OSD_PENDING
>+#define DAGB6_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB6_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB6_WRCLI0
>+#define DAGB6_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_WRCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_WRCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_WRCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_WRCLI1
>+#define DAGB6_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_WRCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_WRCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_WRCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_WRCLI2
>+#define DAGB6_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_WRCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_WRCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_WRCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_WRCLI3
>+#define DAGB6_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_WRCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_WRCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_WRCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_WRCLI4
>+#define DAGB6_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_WRCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_WRCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_WRCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_WRCLI5
>+#define DAGB6_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_WRCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_WRCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_WRCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_WRCLI6
>+#define DAGB6_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_WRCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_WRCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_WRCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_WRCLI7
>+#define DAGB6_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_WRCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_WRCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_WRCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_WRCLI8
>+#define DAGB6_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_WRCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_WRCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_WRCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_WRCLI9
>+#define DAGB6_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB6_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB6_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB6_WRCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB6_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB6_WRCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB6_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB6_WRCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB6_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB6_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB6_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB6_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB6_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB6_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB6_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB6_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB6_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB6_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB6_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB6_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB6_WRCLI10
>+#define DAGB6_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB6_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB6_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB6_WRCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB6_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB6_WRCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB6_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB6_WRCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB6_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB6_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB6_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB6_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB6_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB6_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB6_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB6_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB6_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB6_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB6_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB6_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB6_WRCLI11
>+#define DAGB6_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB6_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB6_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB6_WRCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB6_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB6_WRCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB6_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB6_WRCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB6_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB6_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB6_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB6_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB6_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB6_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB6_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB6_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB6_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB6_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB6_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB6_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB6_WRCLI12
>+#define DAGB6_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB6_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB6_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB6_WRCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB6_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB6_WRCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB6_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB6_WRCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB6_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB6_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB6_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB6_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB6_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB6_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB6_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB6_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB6_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB6_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB6_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB6_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB6_WRCLI13
>+#define DAGB6_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB6_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB6_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB6_WRCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB6_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB6_WRCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB6_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB6_WRCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB6_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB6_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB6_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB6_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB6_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB6_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB6_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB6_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB6_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB6_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB6_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB6_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB6_WRCLI14
>+#define DAGB6_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB6_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB6_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB6_WRCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB6_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB6_WRCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB6_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB6_WRCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB6_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB6_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB6_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB6_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB6_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB6_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB6_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB6_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB6_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB6_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB6_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB6_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB6_WRCLI15
>+#define DAGB6_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB6_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB6_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB6_WRCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB6_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB6_WRCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB6_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB6_WRCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB6_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB6_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB6_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB6_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB6_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB6_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB6_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB6_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB6_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB6_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB6_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB6_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB6_WR_CNTL
>+#define DAGB6_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB6_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB6_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB6_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB6_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB6_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB6_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB6_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB6_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB6_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB6_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB6_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB6_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB6_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB6_WR_GMI_CNTL
>+#define DAGB6_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB6_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB6_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB6_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB6_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB6_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB6_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB6_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB6_WR_ADDR_DAGB
>+#define DAGB6_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB6_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB6_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB6_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB6_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB6_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB6_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB6_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB6_WR_OUTPUT_DAGB_MAX_BURST
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB6_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB6_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB6_WR_CGTT_CLK_CTRL
>+#define DAGB6_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB6_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB6_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB6_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB6_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB6_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB6_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB6_L1TLB_WR_CGTT_CLK_CTRL
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB6_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB6_ATCVM_WR_CGTT_CLK_CTRL
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB6_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB6_WR_ADDR_DAGB_MAX_BURST0
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB6_WR_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB6_WR_ADDR_DAGB_MAX_BURST1
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB6_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB6_WR_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB6_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB6_WR_DATA_DAGB
>+#define DAGB6_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB6_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB6_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB6_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB6_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB6_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB6_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB6_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB6_WR_DATA_DAGB_MAX_BURST0
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB6_WR_DATA_DAGB_LAZY_TIMER0
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB6_WR_DATA_DAGB_MAX_BURST1
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB6_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB6_WR_DATA_DAGB_LAZY_TIMER1
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB6_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB6_WR_VC0_CNTL
>+#define DAGB6_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_WR_VC1_CNTL
>+#define DAGB6_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_WR_VC2_CNTL
>+#define DAGB6_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_WR_VC3_CNTL
>+#define DAGB6_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_WR_VC4_CNTL
>+#define DAGB6_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_WR_VC5_CNTL
>+#define DAGB6_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_WR_VC6_CNTL
>+#define DAGB6_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_WR_VC7_CNTL
>+#define DAGB6_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB6_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB6_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB6_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB6_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB6_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB6_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB6_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB6_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB6_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB6_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB6_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB6_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB6_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB6_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB6_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB6_WR_CNTL_MISC
>+#define DAGB6_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB6_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB6_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB6_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB6_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB6_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB6_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB6_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB6_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB6_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB6_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB6_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB6_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB6_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB6_WR_TLB_CREDIT
>+#define DAGB6_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB6_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB6_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB6_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB6_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB6_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB6_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB6_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB6_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB6_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB6_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB6_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB6_WR_DATA_CREDIT
>+#define DAGB6_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
>+#define DAGB6_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
>+#define DAGB6_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
>+#define DAGB6_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
>+#define DAGB6_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
>+#define DAGB6_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
>+#define DAGB6_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
>+#define DAGB6_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
>+//DAGB6_WR_MISC_CREDIT
>+#define DAGB6_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
>+#define DAGB6_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
>+#define DAGB6_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
>+#define DAGB6_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
>+#define DAGB6_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
>+#define DAGB6_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
>+#define DAGB6_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
>+#define DAGB6_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
>+//DAGB6_WRCLI_ASK_PENDING
>+#define DAGB6_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB6_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB6_WRCLI_GO_PENDING
>+#define DAGB6_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB6_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB6_WRCLI_GBLSEND_PENDING
>+#define DAGB6_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB6_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB6_WRCLI_TLB_PENDING
>+#define DAGB6_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB6_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB6_WRCLI_OARB_PENDING
>+#define DAGB6_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB6_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB6_WRCLI_OSD_PENDING
>+#define DAGB6_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB6_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB6_WRCLI_DBUS_ASK_PENDING
>+#define DAGB6_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
>+#define DAGB6_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
>+//DAGB6_WRCLI_DBUS_GO_PENDING
>+#define DAGB6_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB6_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB6_DAGB_DLY
>+#define DAGB6_DAGB_DLY__DLY__SHIFT                                                                            0x0
>+#define DAGB6_DAGB_DLY__CLI__SHIFT                                                                            0x8
>+#define DAGB6_DAGB_DLY__POS__SHIFT                                                                            0x10
>+#define DAGB6_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
>+#define DAGB6_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
>+#define DAGB6_DAGB_DLY__POS_MASK                                                                              0x000F0000L
>+//DAGB6_CNTL_MISC
>+#define DAGB6_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
>+#define DAGB6_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
>+#define DAGB6_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
>+#define DAGB6_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
>+#define DAGB6_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
>+#define DAGB6_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
>+#define DAGB6_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
>+#define DAGB6_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
>+#define DAGB6_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
>+#define DAGB6_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
>+#define DAGB6_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
>+#define DAGB6_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
>+#define DAGB6_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
>+#define DAGB6_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
>+#define DAGB6_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
>+#define DAGB6_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
>+#define DAGB6_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
>+#define DAGB6_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
>+#define DAGB6_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
>+#define DAGB6_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
>+//DAGB6_CNTL_MISC2
>+#define DAGB6_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
>+#define DAGB6_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
>+#define DAGB6_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
>+#define DAGB6_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
>+#define DAGB6_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
>+#define DAGB6_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
>+#define DAGB6_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
>+#define DAGB6_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
>+#define DAGB6_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
>+#define DAGB6_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
>+#define DAGB6_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
>+#define DAGB6_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
>+#define DAGB6_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
>+#define DAGB6_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
>+#define DAGB6_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
>+#define DAGB6_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
>+#define DAGB6_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
>+#define DAGB6_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
>+#define DAGB6_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
>+#define DAGB6_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
>+#define DAGB6_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
>+#define DAGB6_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
>+#define DAGB6_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
>+#define DAGB6_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
>+#define DAGB6_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
>+#define DAGB6_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
>+//DAGB6_FIFO_EMPTY
>+#define DAGB6_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
>+#define DAGB6_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
>+//DAGB6_FIFO_FULL
>+#define DAGB6_FIFO_FULL__FULL__SHIFT                                                                          0x0
>+#define DAGB6_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
>+//DAGB6_WR_CREDITS_FULL
>+#define DAGB6_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB6_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
>+//DAGB6_RD_CREDITS_FULL
>+#define DAGB6_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB6_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
>+//DAGB6_PERFCOUNTER_LO
>+#define DAGB6_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define DAGB6_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//DAGB6_PERFCOUNTER_HI
>+#define DAGB6_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define DAGB6_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define DAGB6_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define DAGB6_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//DAGB6_PERFCOUNTER0_CFG
>+#define DAGB6_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB6_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB6_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB6_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB6_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB6_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB6_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB6_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB6_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB6_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB6_PERFCOUNTER1_CFG
>+#define DAGB6_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB6_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB6_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB6_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB6_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB6_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB6_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB6_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB6_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB6_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB6_PERFCOUNTER2_CFG
>+#define DAGB6_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB6_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB6_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB6_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB6_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB6_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB6_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB6_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB6_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB6_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB6_PERFCOUNTER_RSLT_CNTL
>+#define DAGB6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define DAGB6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define DAGB6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define DAGB6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define DAGB6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define DAGB6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define DAGB6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define DAGB6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define DAGB6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//DAGB6_RESERVE0
>+#define DAGB6_RESERVE0__RESERVE__SHIFT                                                                        0x0
>+#define DAGB6_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB6_RESERVE1
>+#define DAGB6_RESERVE1__RESERVE__SHIFT                                                                        0x0
>+#define DAGB6_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB6_RESERVE2
>+#define DAGB6_RESERVE2__RESERVE__SHIFT                                                                        0x0
>+#define DAGB6_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB6_RESERVE3
>+#define DAGB6_RESERVE3__RESERVE__SHIFT                                                                        0x0
>+#define DAGB6_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB6_RESERVE4
>+#define DAGB6_RESERVE4__RESERVE__SHIFT                                                                        0x0
>+#define DAGB6_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB6_RESERVE5
>+#define DAGB6_RESERVE5__RESERVE__SHIFT                                                                        0x0
>+#define DAGB6_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB6_RESERVE6
>+#define DAGB6_RESERVE6__RESERVE__SHIFT                                                                        0x0
>+#define DAGB6_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB6_RESERVE7
>+#define DAGB6_RESERVE7__RESERVE__SHIFT                                                                        0x0
>+#define DAGB6_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB6_RESERVE8
>+#define DAGB6_RESERVE8__RESERVE__SHIFT                                                                        0x0
>+#define DAGB6_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB6_RESERVE9
>+#define DAGB6_RESERVE9__RESERVE__SHIFT                                                                        0x0
>+#define DAGB6_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB6_RESERVE10
>+#define DAGB6_RESERVE10__RESERVE__SHIFT                                                                       0x0
>+#define DAGB6_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB6_RESERVE11
>+#define DAGB6_RESERVE11__RESERVE__SHIFT                                                                       0x0
>+#define DAGB6_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB6_RESERVE12
>+#define DAGB6_RESERVE12__RESERVE__SHIFT                                                                       0x0
>+#define DAGB6_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB6_RESERVE13
>+#define DAGB6_RESERVE13__RESERVE__SHIFT                                                                       0x0
>+#define DAGB6_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: mmhub_dagb_dagbdec7
>+//DAGB7_RDCLI0
>+#define DAGB7_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_RDCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_RDCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_RDCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_RDCLI1
>+#define DAGB7_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_RDCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_RDCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_RDCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_RDCLI2
>+#define DAGB7_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_RDCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_RDCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_RDCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_RDCLI3
>+#define DAGB7_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_RDCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_RDCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_RDCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_RDCLI4
>+#define DAGB7_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_RDCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_RDCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_RDCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_RDCLI5
>+#define DAGB7_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_RDCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_RDCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_RDCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_RDCLI6
>+#define DAGB7_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_RDCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_RDCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_RDCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_RDCLI7
>+#define DAGB7_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_RDCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_RDCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_RDCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_RDCLI8
>+#define DAGB7_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_RDCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_RDCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_RDCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_RDCLI9
>+#define DAGB7_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_RDCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_RDCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_RDCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_RDCLI10
>+#define DAGB7_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB7_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB7_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB7_RDCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB7_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB7_RDCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB7_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB7_RDCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB7_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB7_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB7_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB7_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB7_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB7_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB7_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB7_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB7_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB7_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB7_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB7_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB7_RDCLI11
>+#define DAGB7_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB7_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB7_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB7_RDCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB7_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB7_RDCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB7_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB7_RDCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB7_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB7_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB7_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB7_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB7_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB7_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB7_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB7_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB7_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB7_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB7_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB7_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB7_RDCLI12
>+#define DAGB7_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB7_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB7_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB7_RDCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB7_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB7_RDCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB7_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB7_RDCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB7_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB7_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB7_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB7_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB7_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB7_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB7_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB7_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB7_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB7_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB7_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB7_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB7_RDCLI13
>+#define DAGB7_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB7_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB7_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB7_RDCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB7_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB7_RDCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB7_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB7_RDCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB7_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB7_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB7_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB7_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB7_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB7_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB7_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB7_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB7_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB7_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB7_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB7_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB7_RDCLI14
>+#define DAGB7_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB7_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB7_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB7_RDCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB7_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB7_RDCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB7_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB7_RDCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB7_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB7_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB7_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB7_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB7_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB7_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB7_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB7_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB7_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB7_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB7_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB7_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB7_RDCLI15
>+#define DAGB7_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB7_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB7_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB7_RDCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB7_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB7_RDCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB7_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB7_RDCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB7_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB7_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB7_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB7_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB7_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB7_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB7_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB7_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB7_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB7_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB7_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB7_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB7_RD_CNTL
>+#define DAGB7_RD_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB7_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB7_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB7_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB7_RD_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB7_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB7_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB7_RD_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB7_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB7_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB7_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB7_RD_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB7_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB7_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB7_RD_GMI_CNTL
>+#define DAGB7_RD_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB7_RD_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB7_RD_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB7_RD_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB7_RD_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB7_RD_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB7_RD_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB7_RD_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB7_RD_ADDR_DAGB
>+#define DAGB7_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB7_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB7_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB7_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB7_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB7_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB7_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB7_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB7_RD_OUTPUT_DAGB_MAX_BURST
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB7_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB7_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB7_RD_CGTT_CLK_CTRL
>+#define DAGB7_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB7_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB7_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB7_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB7_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB7_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB7_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB7_L1TLB_RD_CGTT_CLK_CTRL
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB7_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB7_ATCVM_RD_CGTT_CLK_CTRL
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB7_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB7_RD_ADDR_DAGB_MAX_BURST0
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB7_RD_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB7_RD_ADDR_DAGB_MAX_BURST1
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB7_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB7_RD_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB7_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB7_RD_VC0_CNTL
>+#define DAGB7_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_RD_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_RD_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_RD_VC1_CNTL
>+#define DAGB7_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_RD_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_RD_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_RD_VC2_CNTL
>+#define DAGB7_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_RD_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_RD_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_RD_VC3_CNTL
>+#define DAGB7_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_RD_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_RD_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_RD_VC4_CNTL
>+#define DAGB7_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_RD_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_RD_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_RD_VC5_CNTL
>+#define DAGB7_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_RD_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_RD_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_RD_VC6_CNTL
>+#define DAGB7_RD_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_RD_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_RD_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_RD_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_RD_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_RD_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_RD_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_RD_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_RD_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_RD_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_RD_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_RD_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_RD_VC7_CNTL
>+#define DAGB7_RD_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_RD_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_RD_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_RD_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_RD_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_RD_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_RD_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_RD_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_RD_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_RD_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_RD_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_RD_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_RD_CNTL_MISC
>+#define DAGB7_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB7_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB7_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB7_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB7_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB7_RD_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB7_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB7_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB7_RD_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB7_RD_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB7_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB7_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB7_RD_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB7_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB7_RD_TLB_CREDIT
>+#define DAGB7_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB7_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB7_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB7_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB7_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB7_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB7_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB7_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB7_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB7_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB7_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB7_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB7_RDCLI_ASK_PENDING
>+#define DAGB7_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB7_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB7_RDCLI_GO_PENDING
>+#define DAGB7_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB7_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB7_RDCLI_GBLSEND_PENDING
>+#define DAGB7_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB7_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB7_RDCLI_TLB_PENDING
>+#define DAGB7_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB7_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB7_RDCLI_OARB_PENDING
>+#define DAGB7_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB7_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB7_RDCLI_OSD_PENDING
>+#define DAGB7_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB7_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB7_WRCLI0
>+#define DAGB7_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_WRCLI0__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_WRCLI0__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_WRCLI0__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_WRCLI1
>+#define DAGB7_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_WRCLI1__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_WRCLI1__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_WRCLI1__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_WRCLI2
>+#define DAGB7_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_WRCLI2__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_WRCLI2__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_WRCLI2__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_WRCLI3
>+#define DAGB7_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_WRCLI3__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_WRCLI3__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_WRCLI3__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_WRCLI4
>+#define DAGB7_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_WRCLI4__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_WRCLI4__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_WRCLI4__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_WRCLI5
>+#define DAGB7_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_WRCLI5__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_WRCLI5__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_WRCLI5__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_WRCLI6
>+#define DAGB7_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_WRCLI6__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_WRCLI6__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_WRCLI6__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_WRCLI7
>+#define DAGB7_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_WRCLI7__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_WRCLI7__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_WRCLI7__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_WRCLI8
>+#define DAGB7_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_WRCLI8__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_WRCLI8__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_WRCLI8__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_WRCLI9
>+#define DAGB7_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
>+#define DAGB7_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
>+#define DAGB7_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
>+#define DAGB7_WRCLI9__URG_LOW__SHIFT                                                                          0x8
>+#define DAGB7_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
>+#define DAGB7_WRCLI9__MAX_BW__SHIFT                                                                           0xd
>+#define DAGB7_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
>+#define DAGB7_WRCLI9__MIN_BW__SHIFT                                                                           0x16
>+#define DAGB7_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
>+#define DAGB7_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
>+#define DAGB7_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
>+#define DAGB7_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
>+#define DAGB7_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
>+#define DAGB7_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
>+#define DAGB7_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
>+#define DAGB7_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
>+#define DAGB7_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
>+#define DAGB7_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
>+#define DAGB7_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
>+#define DAGB7_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
>+//DAGB7_WRCLI10
>+#define DAGB7_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB7_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB7_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB7_WRCLI10__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB7_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB7_WRCLI10__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB7_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB7_WRCLI10__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB7_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB7_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB7_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB7_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB7_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB7_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB7_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB7_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB7_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB7_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB7_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB7_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB7_WRCLI11
>+#define DAGB7_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB7_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB7_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB7_WRCLI11__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB7_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB7_WRCLI11__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB7_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB7_WRCLI11__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB7_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB7_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB7_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB7_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB7_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB7_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB7_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB7_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB7_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB7_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB7_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB7_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB7_WRCLI12
>+#define DAGB7_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB7_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB7_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB7_WRCLI12__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB7_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB7_WRCLI12__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB7_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB7_WRCLI12__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB7_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB7_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB7_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB7_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB7_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB7_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB7_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB7_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB7_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB7_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB7_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB7_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB7_WRCLI13
>+#define DAGB7_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB7_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB7_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB7_WRCLI13__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB7_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB7_WRCLI13__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB7_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB7_WRCLI13__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB7_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB7_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB7_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB7_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB7_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB7_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB7_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB7_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB7_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB7_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB7_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB7_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB7_WRCLI14
>+#define DAGB7_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB7_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB7_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB7_WRCLI14__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB7_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB7_WRCLI14__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB7_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB7_WRCLI14__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB7_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB7_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB7_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB7_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB7_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB7_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB7_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB7_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB7_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB7_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB7_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB7_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB7_WRCLI15
>+#define DAGB7_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
>+#define DAGB7_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
>+#define DAGB7_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
>+#define DAGB7_WRCLI15__URG_LOW__SHIFT                                                                         0x8
>+#define DAGB7_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
>+#define DAGB7_WRCLI15__MAX_BW__SHIFT                                                                          0xd
>+#define DAGB7_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
>+#define DAGB7_WRCLI15__MIN_BW__SHIFT                                                                          0x16
>+#define DAGB7_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
>+#define DAGB7_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
>+#define DAGB7_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
>+#define DAGB7_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
>+#define DAGB7_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
>+#define DAGB7_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
>+#define DAGB7_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
>+#define DAGB7_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
>+#define DAGB7_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
>+#define DAGB7_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
>+#define DAGB7_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
>+#define DAGB7_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
>+//DAGB7_WR_CNTL
>+#define DAGB7_WR_CNTL__SCLK_FREQ__SHIFT                                                                       0x0
>+#define DAGB7_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x4
>+#define DAGB7_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0xa
>+#define DAGB7_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT                                                        0x10
>+#define DAGB7_WR_CNTL__IO_LEVEL__SHIFT                                                                        0x11
>+#define DAGB7_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT                                                              0x14
>+#define DAGB7_WR_CNTL__SHARE_VC_NUM__SHIFT                                                                    0x17
>+#define DAGB7_WR_CNTL__SCLK_FREQ_MASK                                                                         0x0000000FL
>+#define DAGB7_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x000003F0L
>+#define DAGB7_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x0000FC00L
>+#define DAGB7_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK                                                          0x00010000L
>+#define DAGB7_WR_CNTL__IO_LEVEL_MASK                                                                          0x000E0000L
>+#define DAGB7_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK                                                                0x00700000L
>+#define DAGB7_WR_CNTL__SHARE_VC_NUM_MASK                                                                      0x03800000L
>+//DAGB7_WR_GMI_CNTL
>+#define DAGB7_WR_GMI_CNTL__EA_CREDIT__SHIFT                                                                   0x0
>+#define DAGB7_WR_GMI_CNTL__LEVEL__SHIFT                                                                       0x6
>+#define DAGB7_WR_GMI_CNTL__MAX_BURST__SHIFT                                                                   0x9
>+#define DAGB7_WR_GMI_CNTL__LAZY_TIMER__SHIFT                                                                  0xd
>+#define DAGB7_WR_GMI_CNTL__EA_CREDIT_MASK                                                                     0x0000003FL
>+#define DAGB7_WR_GMI_CNTL__LEVEL_MASK                                                                         0x000001C0L
>+#define DAGB7_WR_GMI_CNTL__MAX_BURST_MASK                                                                     0x00001E00L
>+#define DAGB7_WR_GMI_CNTL__LAZY_TIMER_MASK                                                                    0x0001E000L
>+//DAGB7_WR_ADDR_DAGB
>+#define DAGB7_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB7_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB7_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB7_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB7_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB7_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB7_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB7_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB7_WR_OUTPUT_DAGB_MAX_BURST
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT                                                            0x0
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT                                                            0x4
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT                                                            0x8
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT                                                            0xc
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT                                                            0x10
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT                                                            0x14
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT                                                            0x18
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT                                                            0x1c
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK                                                              0x0000000FL
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK                                                              0x000000F0L
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK                                                              0x00000F00L
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK                                                              0x0000F000L
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK                                                              0x000F0000L
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK                                                              0x00F00000L
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK                                                              0x0F000000L
>+#define DAGB7_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK                                                              0xF0000000L
>+//DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT                                                           0x0
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT                                                           0x4
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT                                                           0x8
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT                                                           0xc
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT                                                           0x10
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT                                                           0x14
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT                                                           0x18
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT                                                           0x1c
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK                                                             0x0000000FL
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK                                                             0x000000F0L
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK                                                             0x00000F00L
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK                                                             0x0000F000L
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK                                                             0x000F0000L
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK                                                             0x00F00000L
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK                                                             0x0F000000L
>+#define DAGB7_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK                                                             0xF0000000L
>+//DAGB7_WR_CGTT_CLK_CTRL
>+#define DAGB7_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
>+#define DAGB7_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x4
>+#define DAGB7_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                                    0x16
>+#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                            0x1b
>+#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                      0x1c
>+#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                       0x1d
>+#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                                     0x1e
>+#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                                   0x1f
>+#define DAGB7_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000000FL
>+#define DAGB7_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00000FF0L
>+#define DAGB7_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                      0x00400000L
>+#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                              0x08000000L
>+#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                        0x10000000L
>+#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                         0x20000000L
>+#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                       0x40000000L
>+#define DAGB7_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                                     0x80000000L
>+//DAGB7_L1TLB_WR_CGTT_CLK_CTRL
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB7_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB7_ATCVM_WR_CGTT_CLK_CTRL
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x16
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                      0x1b
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT                                                0x1c
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT                                                 0x1d
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT                                               0x1e
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT                                             0x1f
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00400000L
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                        0x08000000L
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK                                                  0x10000000L
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK                                                   0x20000000L
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK                                                 0x40000000L
>+#define DAGB7_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK                                               0x80000000L
>+//DAGB7_WR_ADDR_DAGB_MAX_BURST0
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB7_WR_ADDR_DAGB_LAZY_TIMER0
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB7_WR_ADDR_DAGB_MAX_BURST1
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB7_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB7_WR_ADDR_DAGB_LAZY_TIMER1
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB7_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB7_WR_DATA_DAGB
>+#define DAGB7_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
>+#define DAGB7_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
>+#define DAGB7_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
>+#define DAGB7_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
>+#define DAGB7_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
>+#define DAGB7_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
>+#define DAGB7_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
>+#define DAGB7_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
>+//DAGB7_WR_DATA_DAGB_MAX_BURST0
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
>+//DAGB7_WR_DATA_DAGB_LAZY_TIMER0
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
>+//DAGB7_WR_DATA_DAGB_MAX_BURST1
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
>+#define DAGB7_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
>+//DAGB7_WR_DATA_DAGB_LAZY_TIMER1
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
>+#define DAGB7_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
>+//DAGB7_WR_VC0_CNTL
>+#define DAGB7_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_WR_VC0_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_WR_VC0_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_WR_VC1_CNTL
>+#define DAGB7_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_WR_VC1_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_WR_VC1_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_WR_VC2_CNTL
>+#define DAGB7_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_WR_VC2_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_WR_VC2_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_WR_VC3_CNTL
>+#define DAGB7_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_WR_VC3_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_WR_VC3_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_WR_VC4_CNTL
>+#define DAGB7_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_WR_VC4_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_WR_VC4_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_WR_VC5_CNTL
>+#define DAGB7_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_WR_VC5_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_WR_VC5_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_WR_VC6_CNTL
>+#define DAGB7_WR_VC6_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_WR_VC6_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_WR_VC6_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_WR_VC6_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_WR_VC6_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_WR_VC6_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_WR_VC6_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_WR_VC6_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_WR_VC6_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_WR_VC6_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_WR_VC6_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_WR_VC6_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_WR_VC7_CNTL
>+#define DAGB7_WR_VC7_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
>+#define DAGB7_WR_VC7_CNTL__EA_CREDIT__SHIFT                                                                   0x5
>+#define DAGB7_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
>+#define DAGB7_WR_VC7_CNTL__MAX_BW__SHIFT                                                                      0xc
>+#define DAGB7_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
>+#define DAGB7_WR_VC7_CNTL__MIN_BW__SHIFT                                                                      0x15
>+#define DAGB7_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
>+#define DAGB7_WR_VC7_CNTL__MAX_OSD__SHIFT                                                                     0x19
>+#define DAGB7_WR_VC7_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
>+#define DAGB7_WR_VC7_CNTL__EA_CREDIT_MASK                                                                     0x000007E0L
>+#define DAGB7_WR_VC7_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
>+#define DAGB7_WR_VC7_CNTL__MAX_BW_MASK                                                                        0x000FF000L
>+#define DAGB7_WR_VC7_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
>+#define DAGB7_WR_VC7_CNTL__MIN_BW_MASK                                                                        0x00E00000L
>+#define DAGB7_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
>+#define DAGB7_WR_VC7_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
>+//DAGB7_WR_CNTL_MISC
>+#define DAGB7_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
>+#define DAGB7_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT                                                             0x6
>+#define DAGB7_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT                                                               0xd
>+#define DAGB7_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT                                                        0x13
>+#define DAGB7_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT                                                          0x14
>+#define DAGB7_WR_CNTL_MISC__UTCL2_CID__SHIFT                                                                  0x15
>+#define DAGB7_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT                                                         0x1a
>+#define DAGB7_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
>+#define DAGB7_WR_CNTL_MISC__EA_POOL_CREDIT_MASK                                                               0x00001FC0L
>+#define DAGB7_WR_CNTL_MISC__IO_EA_CREDIT_MASK                                                                 0x0007E000L
>+#define DAGB7_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK                                                          0x00080000L
>+#define DAGB7_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK                                                            0x00100000L
>+#define DAGB7_WR_CNTL_MISC__UTCL2_CID_MASK                                                                    0x03E00000L
>+#define DAGB7_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK                                                           0xFC000000L
>+//DAGB7_WR_TLB_CREDIT
>+#define DAGB7_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
>+#define DAGB7_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
>+#define DAGB7_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
>+#define DAGB7_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
>+#define DAGB7_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
>+#define DAGB7_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
>+#define DAGB7_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
>+#define DAGB7_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
>+#define DAGB7_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
>+#define DAGB7_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
>+#define DAGB7_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
>+#define DAGB7_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
>+//DAGB7_WR_DATA_CREDIT
>+#define DAGB7_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
>+#define DAGB7_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
>+#define DAGB7_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
>+#define DAGB7_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
>+#define DAGB7_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
>+#define DAGB7_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
>+#define DAGB7_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
>+#define DAGB7_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
>+//DAGB7_WR_MISC_CREDIT
>+#define DAGB7_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
>+#define DAGB7_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
>+#define DAGB7_WR_MISC_CREDIT__OSD_CREDIT__SHIFT                                                               0x9
>+#define DAGB7_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT                                                         0x10
>+#define DAGB7_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
>+#define DAGB7_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
>+#define DAGB7_WR_MISC_CREDIT__OSD_CREDIT_MASK                                                                 0x0000FE00L
>+#define DAGB7_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK                                                           0x007F0000L
>+//DAGB7_WRCLI_ASK_PENDING
>+#define DAGB7_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB7_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB7_WRCLI_GO_PENDING
>+#define DAGB7_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
>+#define DAGB7_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
>+//DAGB7_WRCLI_GBLSEND_PENDING
>+#define DAGB7_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB7_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB7_WRCLI_TLB_PENDING
>+#define DAGB7_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB7_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB7_WRCLI_OARB_PENDING
>+#define DAGB7_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
>+#define DAGB7_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
>+//DAGB7_WRCLI_OSD_PENDING
>+#define DAGB7_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
>+#define DAGB7_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
>+//DAGB7_WRCLI_DBUS_ASK_PENDING
>+#define DAGB7_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
>+#define DAGB7_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
>+//DAGB7_WRCLI_DBUS_GO_PENDING
>+#define DAGB7_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
>+#define DAGB7_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
>+//DAGB7_DAGB_DLY
>+#define DAGB7_DAGB_DLY__DLY__SHIFT                                                                            0x0
>+#define DAGB7_DAGB_DLY__CLI__SHIFT                                                                            0x8
>+#define DAGB7_DAGB_DLY__POS__SHIFT                                                                            0x10
>+#define DAGB7_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
>+#define DAGB7_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
>+#define DAGB7_DAGB_DLY__POS_MASK                                                                              0x000F0000L
>+//DAGB7_CNTL_MISC
>+#define DAGB7_CNTL_MISC__EA_VC0_REMAP__SHIFT                                                                  0x0
>+#define DAGB7_CNTL_MISC__EA_VC1_REMAP__SHIFT                                                                  0x3
>+#define DAGB7_CNTL_MISC__EA_VC2_REMAP__SHIFT                                                                  0x6
>+#define DAGB7_CNTL_MISC__EA_VC3_REMAP__SHIFT                                                                  0x9
>+#define DAGB7_CNTL_MISC__EA_VC4_REMAP__SHIFT                                                                  0xc
>+#define DAGB7_CNTL_MISC__EA_VC5_REMAP__SHIFT                                                                  0xf
>+#define DAGB7_CNTL_MISC__EA_VC6_REMAP__SHIFT                                                                  0x12
>+#define DAGB7_CNTL_MISC__EA_VC7_REMAP__SHIFT                                                                  0x15
>+#define DAGB7_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x18
>+#define DAGB7_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT                                                               0x1e
>+#define DAGB7_CNTL_MISC__EA_VC0_REMAP_MASK                                                                    0x00000007L
>+#define DAGB7_CNTL_MISC__EA_VC1_REMAP_MASK                                                                    0x00000038L
>+#define DAGB7_CNTL_MISC__EA_VC2_REMAP_MASK                                                                    0x000001C0L
>+#define DAGB7_CNTL_MISC__EA_VC3_REMAP_MASK                                                                    0x00000E00L
>+#define DAGB7_CNTL_MISC__EA_VC4_REMAP_MASK                                                                    0x00007000L
>+#define DAGB7_CNTL_MISC__EA_VC5_REMAP_MASK                                                                    0x00038000L
>+#define DAGB7_CNTL_MISC__EA_VC6_REMAP_MASK                                                                    0x001C0000L
>+#define DAGB7_CNTL_MISC__EA_VC7_REMAP_MASK                                                                    0x00E00000L
>+#define DAGB7_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x3F000000L
>+#define DAGB7_CNTL_MISC__BW_RW_GAP_CYCLE_MASK                                                                 0xC0000000L
>+//DAGB7_CNTL_MISC2
>+#define DAGB7_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT                                                             0x0
>+#define DAGB7_CNTL_MISC2__URG_HALT_ENABLE__SHIFT                                                              0x1
>+#define DAGB7_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT                                                             0x2
>+#define DAGB7_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT                                                             0x3
>+#define DAGB7_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT                                                             0x4
>+#define DAGB7_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT                                                             0x5
>+#define DAGB7_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT                                                             0x6
>+#define DAGB7_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT                                                             0x7
>+#define DAGB7_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT                                                         0x8
>+#define DAGB7_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT                                                         0x9
>+#define DAGB7_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0xa
>+#define DAGB7_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0xb
>+#define DAGB7_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT                                                     0x11
>+#define DAGB7_CNTL_MISC2__URG_BOOST_ENABLE_MASK                                                               0x00000001L
>+#define DAGB7_CNTL_MISC2__URG_HALT_ENABLE_MASK                                                                0x00000002L
>+#define DAGB7_CNTL_MISC2__DISABLE_WRREQ_CG_MASK                                                               0x00000004L
>+#define DAGB7_CNTL_MISC2__DISABLE_WRRET_CG_MASK                                                               0x00000008L
>+#define DAGB7_CNTL_MISC2__DISABLE_RDREQ_CG_MASK                                                               0x00000010L
>+#define DAGB7_CNTL_MISC2__DISABLE_RDRET_CG_MASK                                                               0x00000020L
>+#define DAGB7_CNTL_MISC2__DISABLE_TLBWR_CG_MASK                                                               0x00000040L
>+#define DAGB7_CNTL_MISC2__DISABLE_TLBRD_CG_MASK                                                               0x00000080L
>+#define DAGB7_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK                                                           0x00000100L
>+#define DAGB7_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK                                                           0x00000200L
>+#define DAGB7_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000400L
>+#define DAGB7_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000800L
>+#define DAGB7_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK                                                       0x007E0000L
>+//DAGB7_FIFO_EMPTY
>+#define DAGB7_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
>+#define DAGB7_FIFO_EMPTY__EMPTY_MASK                                                                          0x00FFFFFFL
>+//DAGB7_FIFO_FULL
>+#define DAGB7_FIFO_FULL__FULL__SHIFT                                                                          0x0
>+#define DAGB7_FIFO_FULL__FULL_MASK                                                                            0x007FFFFFL
>+//DAGB7_WR_CREDITS_FULL
>+#define DAGB7_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB7_WR_CREDITS_FULL__FULL_MASK                                                                      0x1FFFFFFFL
>+//DAGB7_RD_CREDITS_FULL
>+#define DAGB7_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
>+#define DAGB7_RD_CREDITS_FULL__FULL_MASK                                                                      0x0003FFFFL
>+//DAGB7_PERFCOUNTER_LO
>+#define DAGB7_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define DAGB7_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//DAGB7_PERFCOUNTER_HI
>+#define DAGB7_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define DAGB7_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define DAGB7_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define DAGB7_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//DAGB7_PERFCOUNTER0_CFG
>+#define DAGB7_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB7_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB7_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB7_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB7_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB7_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB7_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB7_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB7_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB7_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB7_PERFCOUNTER1_CFG
>+#define DAGB7_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB7_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB7_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB7_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB7_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB7_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB7_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB7_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB7_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB7_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB7_PERFCOUNTER2_CFG
>+#define DAGB7_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define DAGB7_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define DAGB7_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define DAGB7_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define DAGB7_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define DAGB7_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define DAGB7_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define DAGB7_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define DAGB7_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define DAGB7_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
>+//DAGB7_PERFCOUNTER_RSLT_CNTL
>+#define DAGB7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define DAGB7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define DAGB7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define DAGB7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define DAGB7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define DAGB7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define DAGB7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define DAGB7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define DAGB7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//DAGB7_RESERVE0
>+#define DAGB7_RESERVE0__RESERVE__SHIFT                                                                        0x0
>+#define DAGB7_RESERVE0__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB7_RESERVE1
>+#define DAGB7_RESERVE1__RESERVE__SHIFT                                                                        0x0
>+#define DAGB7_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB7_RESERVE2
>+#define DAGB7_RESERVE2__RESERVE__SHIFT                                                                        0x0
>+#define DAGB7_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB7_RESERVE3
>+#define DAGB7_RESERVE3__RESERVE__SHIFT                                                                        0x0
>+#define DAGB7_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB7_RESERVE4
>+#define DAGB7_RESERVE4__RESERVE__SHIFT                                                                        0x0
>+#define DAGB7_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB7_RESERVE5
>+#define DAGB7_RESERVE5__RESERVE__SHIFT                                                                        0x0
>+#define DAGB7_RESERVE5__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB7_RESERVE6
>+#define DAGB7_RESERVE6__RESERVE__SHIFT                                                                        0x0
>+#define DAGB7_RESERVE6__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB7_RESERVE7
>+#define DAGB7_RESERVE7__RESERVE__SHIFT                                                                        0x0
>+#define DAGB7_RESERVE7__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB7_RESERVE8
>+#define DAGB7_RESERVE8__RESERVE__SHIFT                                                                        0x0
>+#define DAGB7_RESERVE8__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB7_RESERVE9
>+#define DAGB7_RESERVE9__RESERVE__SHIFT                                                                        0x0
>+#define DAGB7_RESERVE9__RESERVE_MASK                                                                          0xFFFFFFFFL
>+//DAGB7_RESERVE10
>+#define DAGB7_RESERVE10__RESERVE__SHIFT                                                                       0x0
>+#define DAGB7_RESERVE10__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB7_RESERVE11
>+#define DAGB7_RESERVE11__RESERVE__SHIFT                                                                       0x0
>+#define DAGB7_RESERVE11__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB7_RESERVE12
>+#define DAGB7_RESERVE12__RESERVE__SHIFT                                                                       0x0
>+#define DAGB7_RESERVE12__RESERVE_MASK                                                                         0xFFFFFFFFL
>+//DAGB7_RESERVE13
>+#define DAGB7_RESERVE13__RESERVE__SHIFT                                                                       0x0
>+#define DAGB7_RESERVE13__RESERVE_MASK                                                                         0xFFFFFFFFL
>+
>+
>+// addressBlock: mmhub_ea_mmeadec5
>+//MMEA5_DRAM_RD_CLI2GRP_MAP0
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA5_DRAM_RD_CLI2GRP_MAP1
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA5_DRAM_WR_CLI2GRP_MAP0
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA5_DRAM_WR_CLI2GRP_MAP1
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA5_DRAM_RD_GRP2VC_MAP
>+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA5_DRAM_WR_GRP2VC_MAP
>+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA5_DRAM_RD_LAZY
>+#define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA5_DRAM_WR_LAZY
>+#define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA5_DRAM_RD_CAM_CNTL
>+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA5_DRAM_WR_CAM_CNTL
>+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA5_DRAM_PAGE_BURST
>+#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
>+#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
>+#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
>+#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
>+#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
>+#define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
>+#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
>+#define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
>+//MMEA5_DRAM_RD_PRI_AGE
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA5_DRAM_WR_PRI_AGE
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA5_DRAM_RD_PRI_QUEUING
>+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA5_DRAM_WR_PRI_QUEUING
>+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA5_DRAM_RD_PRI_FIXED
>+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA5_DRAM_WR_PRI_FIXED
>+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA5_DRAM_RD_PRI_URGENCY
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA5_DRAM_WR_PRI_URGENCY
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA5_DRAM_RD_PRI_QUANT_PRI1
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA5_DRAM_RD_PRI_QUANT_PRI2
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA5_DRAM_RD_PRI_QUANT_PRI3
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA5_DRAM_WR_PRI_QUANT_PRI1
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA5_DRAM_WR_PRI_QUANT_PRI2
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA5_DRAM_WR_PRI_QUANT_PRI3
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA5_GMI_RD_CLI2GRP_MAP0
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA5_GMI_RD_CLI2GRP_MAP1
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA5_GMI_WR_CLI2GRP_MAP0
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA5_GMI_WR_CLI2GRP_MAP1
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA5_GMI_RD_GRP2VC_MAP
>+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA5_GMI_WR_GRP2VC_MAP
>+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA5_GMI_RD_LAZY
>+#define MMEA5_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA5_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA5_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA5_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA5_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA5_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA5_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA5_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA5_GMI_WR_LAZY
>+#define MMEA5_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA5_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA5_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA5_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA5_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA5_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA5_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA5_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA5_GMI_RD_CAM_CNTL
>+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA5_GMI_WR_CAM_CNTL
>+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA5_GMI_PAGE_BURST
>+#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA5_GMI_RD_PRI_AGE
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA5_GMI_WR_PRI_AGE
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA5_GMI_RD_PRI_QUEUING
>+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA5_GMI_WR_PRI_QUEUING
>+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA5_GMI_RD_PRI_FIXED
>+#define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA5_GMI_WR_PRI_FIXED
>+#define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA5_GMI_RD_PRI_URGENCY
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA5_GMI_WR_PRI_URGENCY
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA5_GMI_RD_PRI_URGENCY_MASKING
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA5_GMI_WR_PRI_URGENCY_MASKING
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA5_GMI_RD_PRI_QUANT_PRI1
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA5_GMI_RD_PRI_QUANT_PRI2
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA5_GMI_RD_PRI_QUANT_PRI3
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA5_GMI_WR_PRI_QUANT_PRI1
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA5_GMI_WR_PRI_QUANT_PRI2
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA5_GMI_WR_PRI_QUANT_PRI3
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA5_ADDRNORM_BASE_ADDR0
>+#define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA5_ADDRNORM_LIMIT_ADDR0
>+#define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA5_ADDRNORM_BASE_ADDR1
>+#define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA5_ADDRNORM_LIMIT_ADDR1
>+#define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA5_ADDRNORM_OFFSET_ADDR1
>+#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA5_ADDRNORM_BASE_ADDR2
>+#define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA5_ADDRNORM_LIMIT_ADDR2
>+#define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA5_ADDRNORM_BASE_ADDR3
>+#define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA5_ADDRNORM_LIMIT_ADDR3
>+#define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA5_ADDRNORM_OFFSET_ADDR3
>+#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA5_ADDRNORM_BASE_ADDR4
>+#define MMEA5_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA5_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA5_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA5_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA5_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA5_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA5_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA5_ADDRNORM_LIMIT_ADDR4
>+#define MMEA5_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA5_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA5_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA5_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA5_ADDRNORM_BASE_ADDR5
>+#define MMEA5_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA5_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA5_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA5_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA5_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA5_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA5_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA5_ADDRNORM_LIMIT_ADDR5
>+#define MMEA5_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA5_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA5_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA5_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA5_ADDRNORM_OFFSET_ADDR5
>+#define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA5_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA5_ADDRNORMDRAM_HOLE_CNTL
>+#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
>+#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
>+#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
>+#define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
>+//MMEA5_ADDRNORMGMI_HOLE_CNTL
>+#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
>+#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
>+#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
>+#define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
>+//MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG
>+#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
>+#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
>+#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
>+#define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
>+//MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG
>+#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
>+#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
>+#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
>+#define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
>+//MMEA5_ADDRDEC_BANK_CFG
>+#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
>+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
>+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
>+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
>+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
>+#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
>+#define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
>+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
>+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
>+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
>+#define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
>+//MMEA5_ADDRDEC_MISC_CFG
>+#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
>+#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
>+#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
>+#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
>+#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
>+#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
>+#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
>+#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
>+#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
>+#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
>+#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
>+#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
>+#define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
>+#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
>+#define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
>+#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
>+#define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
>+#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
>+#define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
>+#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
>+#define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
>+//MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA5_ADDRDECDRAM_ADDR_HASH_PC
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
>+//MMEA5_ADDRDECDRAM_ADDR_HASH_PC2
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
>+//MMEA5_ADDRDECDRAM_ADDR_HASH_CS0
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDECDRAM_ADDR_HASH_CS1
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA5_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDECDRAM_HARVEST_ENABLE
>+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
>+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
>+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
>+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
>+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
>+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
>+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
>+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
>+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
>+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
>+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
>+#define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
>+//MMEA5_ADDRDECGMI_ADDR_HASH_BANK0
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA5_ADDRDECGMI_ADDR_HASH_BANK1
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA5_ADDRDECGMI_ADDR_HASH_BANK2
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA5_ADDRDECGMI_ADDR_HASH_BANK3
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA5_ADDRDECGMI_ADDR_HASH_BANK4
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA5_ADDRDECGMI_ADDR_HASH_BANK5
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA5_ADDRDECGMI_ADDR_HASH_PC
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
>+//MMEA5_ADDRDECGMI_ADDR_HASH_PC2
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
>+//MMEA5_ADDRDECGMI_ADDR_HASH_CS0
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA5_ADDRDECGMI_ADDR_HASH_CS1
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA5_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA5_ADDRDECGMI_HARVEST_ENABLE
>+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
>+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
>+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
>+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
>+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
>+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
>+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
>+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
>+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
>+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
>+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
>+#define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
>+//MMEA5_ADDRDEC0_BASE_ADDR_CS0
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDEC0_BASE_ADDR_CS1
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDEC0_BASE_ADDR_CS2
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDEC0_BASE_ADDR_CS3
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDEC0_BASE_ADDR_SECCS0
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA5_ADDRDEC0_BASE_ADDR_SECCS1
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA5_ADDRDEC0_BASE_ADDR_SECCS2
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA5_ADDRDEC0_BASE_ADDR_SECCS3
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA5_ADDRDEC0_ADDR_MASK_CS01
>+#define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA5_ADDRDEC0_ADDR_MASK_CS23
>+#define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA5_ADDRDEC0_ADDR_MASK_SECCS01
>+#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA5_ADDRDEC0_ADDR_MASK_SECCS23
>+#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA5_ADDRDEC0_ADDR_CFG_CS01
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA5_ADDRDEC0_ADDR_CFG_CS23
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA5_ADDRDEC0_ADDR_SEL_CS01
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA5_ADDRDEC0_ADDR_SEL_CS23
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA5_ADDRDEC0_ADDR_SEL2_CS01
>+#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA5_ADDRDEC0_ADDR_SEL2_CS23
>+#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA5_ADDRDEC0_COL_SEL_LO_CS01
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA5_ADDRDEC0_COL_SEL_LO_CS23
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA5_ADDRDEC0_COL_SEL_HI_CS01
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA5_ADDRDEC0_COL_SEL_HI_CS23
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA5_ADDRDEC0_RM_SEL_CS01
>+#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA5_ADDRDEC0_RM_SEL_CS23
>+#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA5_ADDRDEC0_RM_SEL_SECCS01
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA5_ADDRDEC0_RM_SEL_SECCS23
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA5_ADDRDEC1_BASE_ADDR_CS0
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDEC1_BASE_ADDR_CS1
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDEC1_BASE_ADDR_CS2
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDEC1_BASE_ADDR_CS3
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDEC1_BASE_ADDR_SECCS0
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA5_ADDRDEC1_BASE_ADDR_SECCS1
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA5_ADDRDEC1_BASE_ADDR_SECCS2
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA5_ADDRDEC1_BASE_ADDR_SECCS3
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA5_ADDRDEC1_ADDR_MASK_CS01
>+#define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA5_ADDRDEC1_ADDR_MASK_CS23
>+#define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA5_ADDRDEC1_ADDR_MASK_SECCS01
>+#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA5_ADDRDEC1_ADDR_MASK_SECCS23
>+#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA5_ADDRDEC1_ADDR_CFG_CS01
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA5_ADDRDEC1_ADDR_CFG_CS23
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA5_ADDRDEC1_ADDR_SEL_CS01
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA5_ADDRDEC1_ADDR_SEL_CS23
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA5_ADDRDEC1_ADDR_SEL2_CS01
>+#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA5_ADDRDEC1_ADDR_SEL2_CS23
>+#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA5_ADDRDEC1_COL_SEL_LO_CS01
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA5_ADDRDEC1_COL_SEL_LO_CS23
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA5_ADDRDEC1_COL_SEL_HI_CS01
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA5_ADDRDEC1_COL_SEL_HI_CS23
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA5_ADDRDEC1_RM_SEL_CS01
>+#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA5_ADDRDEC1_RM_SEL_CS23
>+#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA5_ADDRDEC1_RM_SEL_SECCS01
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA5_ADDRDEC1_RM_SEL_SECCS23
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA5_ADDRDEC2_BASE_ADDR_CS0
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDEC2_BASE_ADDR_CS1
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDEC2_BASE_ADDR_CS2
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDEC2_BASE_ADDR_CS3
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA5_ADDRDEC2_BASE_ADDR_SECCS0
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA5_ADDRDEC2_BASE_ADDR_SECCS1
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA5_ADDRDEC2_BASE_ADDR_SECCS2
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA5_ADDRDEC2_BASE_ADDR_SECCS3
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA5_ADDRDEC2_ADDR_MASK_CS01
>+#define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA5_ADDRDEC2_ADDR_MASK_CS23
>+#define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA5_ADDRDEC2_ADDR_MASK_SECCS01
>+#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA5_ADDRDEC2_ADDR_MASK_SECCS23
>+#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA5_ADDRDEC2_ADDR_CFG_CS01
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA5_ADDRDEC2_ADDR_CFG_CS23
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA5_ADDRDEC2_ADDR_SEL_CS01
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA5_ADDRDEC2_ADDR_SEL_CS23
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA5_ADDRDEC2_ADDR_SEL2_CS01
>+#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA5_ADDRDEC2_ADDR_SEL2_CS23
>+#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA5_ADDRDEC2_COL_SEL_LO_CS01
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA5_ADDRDEC2_COL_SEL_LO_CS23
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA5_ADDRDEC2_COL_SEL_HI_CS01
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA5_ADDRDEC2_COL_SEL_HI_CS23
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA5_ADDRDEC2_RM_SEL_CS01
>+#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA5_ADDRDEC2_RM_SEL_CS23
>+#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA5_ADDRDEC2_RM_SEL_SECCS01
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA5_ADDRDEC2_RM_SEL_SECCS23
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA5_ADDRNORMDRAM_GLOBAL_CNTL
>+#define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
>+#define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
>+#define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
>+#define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
>+#define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
>+#define MMEA5_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
>+//MMEA5_ADDRNORMGMI_GLOBAL_CNTL
>+#define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
>+#define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
>+#define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
>+#define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
>+#define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
>+#define MMEA5_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
>+//MMEA5_IO_RD_CLI2GRP_MAP0
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA5_IO_RD_CLI2GRP_MAP1
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA5_IO_WR_CLI2GRP_MAP0
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA5_IO_WR_CLI2GRP_MAP1
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA5_IO_RD_COMBINE_FLUSH
>+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA5_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA5_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA5_IO_WR_COMBINE_FLUSH
>+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA5_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA5_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA5_IO_GROUP_BURST
>+#define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA5_IO_RD_PRI_AGE
>+#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA5_IO_WR_PRI_AGE
>+#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA5_IO_RD_PRI_QUEUING
>+#define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA5_IO_WR_PRI_QUEUING
>+#define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA5_IO_RD_PRI_FIXED
>+#define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA5_IO_WR_PRI_FIXED
>+#define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA5_IO_RD_PRI_URGENCY
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA5_IO_WR_PRI_URGENCY
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA5_IO_RD_PRI_URGENCY_MASKING
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA5_IO_WR_PRI_URGENCY_MASKING
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA5_IO_RD_PRI_QUANT_PRI1
>+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA5_IO_RD_PRI_QUANT_PRI2
>+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA5_IO_RD_PRI_QUANT_PRI3
>+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA5_IO_WR_PRI_QUANT_PRI1
>+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA5_IO_WR_PRI_QUANT_PRI2
>+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA5_IO_WR_PRI_QUANT_PRI3
>+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA5_SDP_ARB_DRAM
>+#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
>+#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
>+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
>+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
>+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
>+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
>+#define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
>+#define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
>+#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
>+#define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
>+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
>+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
>+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
>+#define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
>+#define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
>+#define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
>+//MMEA5_SDP_ARB_GMI
>+#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
>+#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
>+#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
>+#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
>+#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
>+#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
>+#define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
>+#define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
>+#define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
>+#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
>+#define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
>+#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
>+#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
>+#define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
>+#define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
>+#define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
>+#define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
>+#define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
>+//MMEA5_SDP_ARB_FINAL
>+#define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
>+#define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
>+#define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
>+#define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
>+#define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
>+#define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
>+#define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
>+#define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
>+#define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
>+#define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
>+#define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
>+#define MMEA5_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
>+#define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
>+#define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
>+#define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
>+//MMEA5_SDP_DRAM_PRIORITY
>+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
>+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
>+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
>+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
>+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
>+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
>+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
>+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
>+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
>+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
>+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
>+#define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
>+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
>+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
>+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
>+#define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
>+//MMEA5_SDP_GMI_PRIORITY
>+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
>+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
>+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
>+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
>+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
>+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
>+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
>+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
>+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
>+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
>+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
>+#define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
>+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
>+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
>+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
>+#define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
>+//MMEA5_SDP_IO_PRIORITY
>+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
>+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
>+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
>+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
>+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
>+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
>+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
>+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
>+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
>+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
>+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
>+#define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
>+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
>+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
>+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
>+#define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
>+//MMEA5_SDP_CREDITS
>+#define MMEA5_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
>+#define MMEA5_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
>+#define MMEA5_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
>+#define MMEA5_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
>+#define MMEA5_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
>+#define MMEA5_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
>+//MMEA5_SDP_TAG_RESERVE0
>+#define MMEA5_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
>+#define MMEA5_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
>+#define MMEA5_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
>+#define MMEA5_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
>+#define MMEA5_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
>+#define MMEA5_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
>+#define MMEA5_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
>+#define MMEA5_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
>+//MMEA5_SDP_TAG_RESERVE1
>+#define MMEA5_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
>+#define MMEA5_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
>+#define MMEA5_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
>+#define MMEA5_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
>+#define MMEA5_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
>+#define MMEA5_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
>+#define MMEA5_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
>+#define MMEA5_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
>+//MMEA5_SDP_VCC_RESERVE0
>+#define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA5_SDP_VCC_RESERVE1
>+#define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA5_SDP_VCD_RESERVE0
>+#define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA5_SDP_VCD_RESERVE1
>+#define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA5_SDP_REQ_CNTL
>+#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
>+#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
>+#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
>+#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
>+#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
>+#define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
>+#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
>+#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
>+#define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
>+#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
>+#define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
>+#define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
>+//MMEA5_MISC
>+#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
>+#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
>+#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
>+#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
>+#define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
>+#define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
>+#define MMEA5_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
>+#define MMEA5_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
>+#define MMEA5_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
>+#define MMEA5_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
>+#define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
>+#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
>+#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
>+#define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
>+#define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
>+#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
>+#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
>+#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
>+#define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
>+#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
>+#define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
>+#define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
>+#define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
>+#define MMEA5_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
>+#define MMEA5_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
>+#define MMEA5_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
>+#define MMEA5_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
>+#define MMEA5_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
>+#define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
>+#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
>+#define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
>+#define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
>+#define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
>+#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
>+#define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
>+//MMEA5_LATENCY_SAMPLING
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
>+#define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
>+//MMEA5_PERFCOUNTER_LO
>+#define MMEA5_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define MMEA5_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//MMEA5_PERFCOUNTER_HI
>+#define MMEA5_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define MMEA5_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//MMEA5_PERFCOUNTER0_CFG
>+#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA5_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA5_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA5_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA5_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA5_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA5_PERFCOUNTER1_CFG
>+#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA5_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA5_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA5_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA5_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA5_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA5_PERFCOUNTER_RSLT_CNTL
>+#define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//MMEA5_EDC_CNT
>+#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
>+#define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
>+#define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
>+#define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
>+#define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
>+#define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
>+#define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
>+#define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
>+#define MMEA5_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
>+#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
>+#define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
>+#define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
>+#define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
>+#define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
>+#define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
>+#define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
>+#define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
>+#define MMEA5_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
>+//MMEA5_EDC_CNT2
>+#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
>+#define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
>+#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
>+#define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
>+//MMEA5_DSM_CNTL
>+#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
>+#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
>+#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
>+#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
>+#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
>+#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
>+#define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
>+#define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
>+#define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
>+#define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
>+#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
>+#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
>+#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
>+#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
>+#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
>+#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
>+#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
>+#define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
>+#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
>+#define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
>+#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
>+#define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
>+#define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
>+#define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
>+#define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
>+#define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
>+#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
>+#define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
>+#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
>+#define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
>+#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
>+#define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
>+//MMEA5_DSM_CNTLA
>+#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
>+#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
>+#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
>+#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
>+#define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
>+#define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
>+#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
>+#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
>+#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
>+#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
>+#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
>+#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
>+#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
>+#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
>+#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
>+#define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
>+#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
>+#define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
>+#define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
>+#define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
>+#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
>+#define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
>+#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
>+#define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
>+#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
>+#define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
>+#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
>+#define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
>+//MMEA5_DSM_CNTL2
>+#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
>+#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
>+#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
>+#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
>+#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
>+#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
>+#define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
>+#define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
>+#define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
>+#define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
>+#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
>+#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
>+#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
>+#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
>+#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
>+#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
>+#define MMEA5_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
>+#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
>+#define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
>+#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
>+#define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
>+#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
>+#define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
>+#define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
>+#define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
>+#define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
>+#define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
>+#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
>+#define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
>+#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
>+#define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
>+#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
>+#define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
>+#define MMEA5_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
>+//MMEA5_DSM_CNTL2A
>+#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
>+#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
>+#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
>+#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
>+#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
>+#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
>+#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
>+#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
>+#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
>+#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
>+#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
>+#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
>+#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
>+#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
>+#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
>+#define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
>+#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
>+#define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
>+#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
>+#define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
>+#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
>+#define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
>+#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
>+#define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
>+#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
>+#define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
>+#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
>+#define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
>+//MMEA5_CGTT_CLK_CTRL
>+#define MMEA5_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
>+#define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
>+#define MMEA5_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
>+#define MMEA5_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
>+#define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
>+#define MMEA5_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
>+#define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
>+#define MMEA5_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
>+#define MMEA5_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
>+#define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
>+#define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
>+//MMEA5_EDC_MODE
>+#define MMEA5_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
>+#define MMEA5_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
>+#define MMEA5_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
>+#define MMEA5_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
>+#define MMEA5_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
>+#define MMEA5_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
>+#define MMEA5_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
>+#define MMEA5_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
>+#define MMEA5_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
>+#define MMEA5_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
>+//MMEA5_ERR_STATUS
>+#define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
>+#define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
>+#define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
>+#define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
>+#define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
>+#define MMEA5_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
>+#define MMEA5_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
>+#define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
>+#define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
>+#define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
>+#define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
>+#define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
>+#define MMEA5_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
>+#define MMEA5_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
>+//MMEA5_MISC2
>+#define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
>+#define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
>+#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
>+#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
>+#define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
>+#define MMEA5_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
>+#define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
>+#define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
>+#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
>+#define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
>+#define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
>+#define MMEA5_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
>+//MMEA5_ADDRDEC_SELECT
>+#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
>+#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
>+#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
>+#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
>+#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
>+#define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
>+#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
>+#define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
>+//MMEA5_EDC_CNT3
>+#define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
>+#define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
>+#define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
>+#define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
>+#define MMEA5_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
>+#define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
>+#define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
>+#define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
>+#define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
>+#define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
>+#define MMEA5_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
>+#define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
>+
>+
>+// addressBlock: mmhub_ea_mmeadec6
>+//MMEA6_DRAM_RD_CLI2GRP_MAP0
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA6_DRAM_RD_CLI2GRP_MAP1
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA6_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA6_DRAM_WR_CLI2GRP_MAP0
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA6_DRAM_WR_CLI2GRP_MAP1
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA6_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA6_DRAM_RD_GRP2VC_MAP
>+#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA6_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA6_DRAM_WR_GRP2VC_MAP
>+#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA6_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA6_DRAM_RD_LAZY
>+#define MMEA6_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA6_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA6_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA6_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA6_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA6_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA6_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA6_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA6_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA6_DRAM_WR_LAZY
>+#define MMEA6_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA6_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA6_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA6_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA6_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA6_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA6_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA6_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA6_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA6_DRAM_RD_CAM_CNTL
>+#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA6_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA6_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA6_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA6_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA6_DRAM_WR_CAM_CNTL
>+#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA6_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA6_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA6_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA6_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA6_DRAM_PAGE_BURST
>+#define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
>+#define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
>+#define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
>+#define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
>+#define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
>+#define MMEA6_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
>+#define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
>+#define MMEA6_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
>+//MMEA6_DRAM_RD_PRI_AGE
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA6_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA6_DRAM_WR_PRI_AGE
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA6_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA6_DRAM_RD_PRI_QUEUING
>+#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA6_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA6_DRAM_WR_PRI_QUEUING
>+#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA6_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA6_DRAM_RD_PRI_FIXED
>+#define MMEA6_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA6_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA6_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA6_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA6_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA6_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA6_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA6_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA6_DRAM_WR_PRI_FIXED
>+#define MMEA6_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA6_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA6_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA6_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA6_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA6_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA6_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA6_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA6_DRAM_RD_PRI_URGENCY
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA6_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA6_DRAM_WR_PRI_URGENCY
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA6_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA6_DRAM_RD_PRI_QUANT_PRI1
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA6_DRAM_RD_PRI_QUANT_PRI2
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA6_DRAM_RD_PRI_QUANT_PRI3
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA6_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA6_DRAM_WR_PRI_QUANT_PRI1
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA6_DRAM_WR_PRI_QUANT_PRI2
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA6_DRAM_WR_PRI_QUANT_PRI3
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA6_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA6_GMI_RD_CLI2GRP_MAP0
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA6_GMI_RD_CLI2GRP_MAP1
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA6_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA6_GMI_WR_CLI2GRP_MAP0
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA6_GMI_WR_CLI2GRP_MAP1
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA6_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA6_GMI_RD_GRP2VC_MAP
>+#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA6_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA6_GMI_WR_GRP2VC_MAP
>+#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA6_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA6_GMI_RD_LAZY
>+#define MMEA6_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA6_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA6_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA6_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA6_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA6_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA6_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA6_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA6_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA6_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA6_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA6_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA6_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA6_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA6_GMI_WR_LAZY
>+#define MMEA6_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA6_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA6_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA6_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA6_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA6_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA6_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA6_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA6_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA6_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA6_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA6_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA6_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA6_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA6_GMI_RD_CAM_CNTL
>+#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA6_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA6_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA6_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA6_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA6_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA6_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA6_GMI_WR_CAM_CNTL
>+#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA6_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA6_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA6_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA6_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA6_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA6_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA6_GMI_PAGE_BURST
>+#define MMEA6_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA6_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA6_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA6_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA6_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA6_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA6_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA6_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA6_GMI_RD_PRI_AGE
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA6_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA6_GMI_WR_PRI_AGE
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA6_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA6_GMI_RD_PRI_QUEUING
>+#define MMEA6_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA6_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA6_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA6_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA6_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA6_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA6_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA6_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA6_GMI_WR_PRI_QUEUING
>+#define MMEA6_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA6_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA6_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA6_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA6_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA6_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA6_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA6_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA6_GMI_RD_PRI_FIXED
>+#define MMEA6_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA6_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA6_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA6_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA6_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA6_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA6_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA6_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA6_GMI_WR_PRI_FIXED
>+#define MMEA6_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA6_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA6_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA6_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA6_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA6_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA6_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA6_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA6_GMI_RD_PRI_URGENCY
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA6_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA6_GMI_WR_PRI_URGENCY
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA6_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA6_GMI_RD_PRI_URGENCY_MASKING
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA6_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA6_GMI_WR_PRI_URGENCY_MASKING
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA6_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA6_GMI_RD_PRI_QUANT_PRI1
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA6_GMI_RD_PRI_QUANT_PRI2
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA6_GMI_RD_PRI_QUANT_PRI3
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA6_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA6_GMI_WR_PRI_QUANT_PRI1
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA6_GMI_WR_PRI_QUANT_PRI2
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA6_GMI_WR_PRI_QUANT_PRI3
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA6_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA6_ADDRNORM_BASE_ADDR0
>+#define MMEA6_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA6_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA6_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA6_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA6_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA6_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA6_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA6_ADDRNORM_LIMIT_ADDR0
>+#define MMEA6_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA6_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA6_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA6_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA6_ADDRNORM_BASE_ADDR1
>+#define MMEA6_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA6_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA6_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA6_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA6_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA6_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA6_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA6_ADDRNORM_LIMIT_ADDR1
>+#define MMEA6_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA6_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA6_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA6_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA6_ADDRNORM_OFFSET_ADDR1
>+#define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA6_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA6_ADDRNORM_BASE_ADDR2
>+#define MMEA6_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA6_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA6_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA6_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA6_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA6_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA6_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA6_ADDRNORM_LIMIT_ADDR2
>+#define MMEA6_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA6_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA6_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA6_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA6_ADDRNORM_BASE_ADDR3
>+#define MMEA6_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA6_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA6_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA6_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA6_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA6_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA6_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA6_ADDRNORM_LIMIT_ADDR3
>+#define MMEA6_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA6_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA6_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA6_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA6_ADDRNORM_OFFSET_ADDR3
>+#define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA6_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA6_ADDRNORM_BASE_ADDR4
>+#define MMEA6_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA6_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA6_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA6_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA6_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA6_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA6_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA6_ADDRNORM_LIMIT_ADDR4
>+#define MMEA6_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA6_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA6_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA6_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA6_ADDRNORM_BASE_ADDR5
>+#define MMEA6_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA6_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA6_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA6_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA6_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA6_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA6_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA6_ADDRNORM_LIMIT_ADDR5
>+#define MMEA6_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA6_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA6_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA6_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA6_ADDRNORM_OFFSET_ADDR5
>+#define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA6_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA6_ADDRNORMDRAM_HOLE_CNTL
>+#define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
>+#define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
>+#define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
>+#define MMEA6_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
>+//MMEA6_ADDRNORMGMI_HOLE_CNTL
>+#define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
>+#define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
>+#define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
>+#define MMEA6_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
>+//MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG
>+#define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
>+#define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
>+#define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
>+#define MMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
>+//MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG
>+#define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
>+#define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
>+#define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
>+#define MMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
>+//MMEA6_ADDRDEC_BANK_CFG
>+#define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
>+#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
>+#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
>+#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
>+#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
>+#define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
>+#define MMEA6_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
>+#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
>+#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
>+#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
>+#define MMEA6_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
>+//MMEA6_ADDRDEC_MISC_CFG
>+#define MMEA6_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
>+#define MMEA6_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
>+#define MMEA6_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
>+#define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
>+#define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
>+#define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
>+#define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
>+#define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
>+#define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
>+#define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
>+#define MMEA6_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
>+#define MMEA6_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
>+#define MMEA6_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
>+#define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
>+#define MMEA6_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
>+#define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
>+#define MMEA6_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
>+#define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
>+#define MMEA6_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
>+#define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
>+#define MMEA6_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
>+//MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA6_ADDRDECDRAM_ADDR_HASH_PC
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
>+//MMEA6_ADDRDECDRAM_ADDR_HASH_PC2
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
>+//MMEA6_ADDRDECDRAM_ADDR_HASH_CS0
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDECDRAM_ADDR_HASH_CS1
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA6_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDECDRAM_HARVEST_ENABLE
>+#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
>+#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
>+#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
>+#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
>+#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
>+#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
>+#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
>+#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
>+#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
>+#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
>+#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
>+#define MMEA6_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
>+//MMEA6_ADDRDECGMI_ADDR_HASH_BANK0
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA6_ADDRDECGMI_ADDR_HASH_BANK1
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA6_ADDRDECGMI_ADDR_HASH_BANK2
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA6_ADDRDECGMI_ADDR_HASH_BANK3
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA6_ADDRDECGMI_ADDR_HASH_BANK4
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA6_ADDRDECGMI_ADDR_HASH_BANK5
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA6_ADDRDECGMI_ADDR_HASH_PC
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
>+//MMEA6_ADDRDECGMI_ADDR_HASH_PC2
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
>+//MMEA6_ADDRDECGMI_ADDR_HASH_CS0
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA6_ADDRDECGMI_ADDR_HASH_CS1
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA6_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA6_ADDRDECGMI_HARVEST_ENABLE
>+#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
>+#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
>+#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
>+#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
>+#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
>+#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
>+#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
>+#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
>+#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
>+#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
>+#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
>+#define MMEA6_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
>+//MMEA6_ADDRDEC0_BASE_ADDR_CS0
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDEC0_BASE_ADDR_CS1
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDEC0_BASE_ADDR_CS2
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDEC0_BASE_ADDR_CS3
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA6_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDEC0_BASE_ADDR_SECCS0
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA6_ADDRDEC0_BASE_ADDR_SECCS1
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA6_ADDRDEC0_BASE_ADDR_SECCS2
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA6_ADDRDEC0_BASE_ADDR_SECCS3
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA6_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA6_ADDRDEC0_ADDR_MASK_CS01
>+#define MMEA6_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA6_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA6_ADDRDEC0_ADDR_MASK_CS23
>+#define MMEA6_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA6_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA6_ADDRDEC0_ADDR_MASK_SECCS01
>+#define MMEA6_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA6_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA6_ADDRDEC0_ADDR_MASK_SECCS23
>+#define MMEA6_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA6_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA6_ADDRDEC0_ADDR_CFG_CS01
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA6_ADDRDEC0_ADDR_CFG_CS23
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA6_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA6_ADDRDEC0_ADDR_SEL_CS01
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA6_ADDRDEC0_ADDR_SEL_CS23
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA6_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA6_ADDRDEC0_ADDR_SEL2_CS01
>+#define MMEA6_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA6_ADDRDEC0_ADDR_SEL2_CS23
>+#define MMEA6_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA6_ADDRDEC0_COL_SEL_LO_CS01
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA6_ADDRDEC0_COL_SEL_LO_CS23
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA6_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA6_ADDRDEC0_COL_SEL_HI_CS01
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA6_ADDRDEC0_COL_SEL_HI_CS23
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA6_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA6_ADDRDEC0_RM_SEL_CS01
>+#define MMEA6_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA6_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA6_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA6_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA6_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA6_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA6_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA6_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA6_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA6_ADDRDEC0_RM_SEL_CS23
>+#define MMEA6_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA6_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA6_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA6_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA6_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA6_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA6_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA6_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA6_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA6_ADDRDEC0_RM_SEL_SECCS01
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA6_ADDRDEC0_RM_SEL_SECCS23
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA6_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA6_ADDRDEC1_BASE_ADDR_CS0
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDEC1_BASE_ADDR_CS1
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDEC1_BASE_ADDR_CS2
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDEC1_BASE_ADDR_CS3
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA6_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDEC1_BASE_ADDR_SECCS0
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA6_ADDRDEC1_BASE_ADDR_SECCS1
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA6_ADDRDEC1_BASE_ADDR_SECCS2
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA6_ADDRDEC1_BASE_ADDR_SECCS3
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA6_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA6_ADDRDEC1_ADDR_MASK_CS01
>+#define MMEA6_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA6_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA6_ADDRDEC1_ADDR_MASK_CS23
>+#define MMEA6_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA6_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA6_ADDRDEC1_ADDR_MASK_SECCS01
>+#define MMEA6_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA6_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA6_ADDRDEC1_ADDR_MASK_SECCS23
>+#define MMEA6_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA6_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA6_ADDRDEC1_ADDR_CFG_CS01
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA6_ADDRDEC1_ADDR_CFG_CS23
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA6_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA6_ADDRDEC1_ADDR_SEL_CS01
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA6_ADDRDEC1_ADDR_SEL_CS23
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA6_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA6_ADDRDEC1_ADDR_SEL2_CS01
>+#define MMEA6_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA6_ADDRDEC1_ADDR_SEL2_CS23
>+#define MMEA6_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA6_ADDRDEC1_COL_SEL_LO_CS01
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA6_ADDRDEC1_COL_SEL_LO_CS23
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA6_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA6_ADDRDEC1_COL_SEL_HI_CS01
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA6_ADDRDEC1_COL_SEL_HI_CS23
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA6_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA6_ADDRDEC1_RM_SEL_CS01
>+#define MMEA6_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA6_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA6_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA6_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA6_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA6_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA6_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA6_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA6_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA6_ADDRDEC1_RM_SEL_CS23
>+#define MMEA6_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA6_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA6_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA6_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA6_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA6_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA6_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA6_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA6_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA6_ADDRDEC1_RM_SEL_SECCS01
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA6_ADDRDEC1_RM_SEL_SECCS23
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA6_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA6_ADDRDEC2_BASE_ADDR_CS0
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDEC2_BASE_ADDR_CS1
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDEC2_BASE_ADDR_CS2
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDEC2_BASE_ADDR_CS3
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA6_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA6_ADDRDEC2_BASE_ADDR_SECCS0
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA6_ADDRDEC2_BASE_ADDR_SECCS1
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA6_ADDRDEC2_BASE_ADDR_SECCS2
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA6_ADDRDEC2_BASE_ADDR_SECCS3
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA6_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA6_ADDRDEC2_ADDR_MASK_CS01
>+#define MMEA6_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA6_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA6_ADDRDEC2_ADDR_MASK_CS23
>+#define MMEA6_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA6_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA6_ADDRDEC2_ADDR_MASK_SECCS01
>+#define MMEA6_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA6_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA6_ADDRDEC2_ADDR_MASK_SECCS23
>+#define MMEA6_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA6_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA6_ADDRDEC2_ADDR_CFG_CS01
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA6_ADDRDEC2_ADDR_CFG_CS23
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA6_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA6_ADDRDEC2_ADDR_SEL_CS01
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA6_ADDRDEC2_ADDR_SEL_CS23
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA6_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA6_ADDRDEC2_ADDR_SEL2_CS01
>+#define MMEA6_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA6_ADDRDEC2_ADDR_SEL2_CS23
>+#define MMEA6_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA6_ADDRDEC2_COL_SEL_LO_CS01
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA6_ADDRDEC2_COL_SEL_LO_CS23
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA6_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA6_ADDRDEC2_COL_SEL_HI_CS01
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA6_ADDRDEC2_COL_SEL_HI_CS23
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA6_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA6_ADDRDEC2_RM_SEL_CS01
>+#define MMEA6_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA6_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA6_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA6_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA6_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA6_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA6_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA6_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA6_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA6_ADDRDEC2_RM_SEL_CS23
>+#define MMEA6_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA6_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA6_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA6_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA6_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA6_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA6_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA6_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA6_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA6_ADDRDEC2_RM_SEL_SECCS01
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA6_ADDRDEC2_RM_SEL_SECCS23
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA6_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA6_ADDRNORMDRAM_GLOBAL_CNTL
>+#define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
>+#define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
>+#define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
>+#define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
>+#define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
>+#define MMEA6_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
>+//MMEA6_ADDRNORMGMI_GLOBAL_CNTL
>+#define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
>+#define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
>+#define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
>+#define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
>+#define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
>+#define MMEA6_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
>+//MMEA6_IO_RD_CLI2GRP_MAP0
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA6_IO_RD_CLI2GRP_MAP1
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA6_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA6_IO_WR_CLI2GRP_MAP0
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA6_IO_WR_CLI2GRP_MAP1
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA6_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA6_IO_RD_COMBINE_FLUSH
>+#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA6_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA6_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA6_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA6_IO_WR_COMBINE_FLUSH
>+#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA6_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA6_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA6_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA6_IO_GROUP_BURST
>+#define MMEA6_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA6_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA6_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA6_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA6_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA6_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA6_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA6_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA6_IO_RD_PRI_AGE
>+#define MMEA6_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA6_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA6_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA6_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA6_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA6_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA6_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA6_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA6_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA6_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA6_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA6_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA6_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA6_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA6_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA6_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA6_IO_WR_PRI_AGE
>+#define MMEA6_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA6_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA6_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA6_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA6_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA6_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA6_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA6_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA6_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA6_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA6_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA6_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA6_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA6_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA6_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA6_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA6_IO_RD_PRI_QUEUING
>+#define MMEA6_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA6_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA6_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA6_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA6_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA6_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA6_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA6_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA6_IO_WR_PRI_QUEUING
>+#define MMEA6_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA6_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA6_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA6_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA6_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA6_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA6_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA6_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA6_IO_RD_PRI_FIXED
>+#define MMEA6_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA6_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA6_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA6_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA6_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA6_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA6_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA6_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA6_IO_WR_PRI_FIXED
>+#define MMEA6_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA6_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA6_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA6_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA6_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA6_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA6_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA6_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA6_IO_RD_PRI_URGENCY
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA6_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA6_IO_WR_PRI_URGENCY
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA6_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA6_IO_RD_PRI_URGENCY_MASKING
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA6_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA6_IO_WR_PRI_URGENCY_MASKING
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA6_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA6_IO_RD_PRI_QUANT_PRI1
>+#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA6_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA6_IO_RD_PRI_QUANT_PRI2
>+#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA6_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA6_IO_RD_PRI_QUANT_PRI3
>+#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA6_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA6_IO_WR_PRI_QUANT_PRI1
>+#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA6_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA6_IO_WR_PRI_QUANT_PRI2
>+#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA6_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA6_IO_WR_PRI_QUANT_PRI3
>+#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA6_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA6_SDP_ARB_DRAM
>+#define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
>+#define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
>+#define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
>+#define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
>+#define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
>+#define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
>+#define MMEA6_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
>+#define MMEA6_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
>+#define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
>+#define MMEA6_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
>+#define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
>+#define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
>+#define MMEA6_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
>+#define MMEA6_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
>+#define MMEA6_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
>+#define MMEA6_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
>+//MMEA6_SDP_ARB_GMI
>+#define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
>+#define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
>+#define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
>+#define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
>+#define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
>+#define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
>+#define MMEA6_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
>+#define MMEA6_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
>+#define MMEA6_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
>+#define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
>+#define MMEA6_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
>+#define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
>+#define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
>+#define MMEA6_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
>+#define MMEA6_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
>+#define MMEA6_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
>+#define MMEA6_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
>+#define MMEA6_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
>+//MMEA6_SDP_ARB_FINAL
>+#define MMEA6_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
>+#define MMEA6_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
>+#define MMEA6_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
>+#define MMEA6_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
>+#define MMEA6_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
>+#define MMEA6_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
>+#define MMEA6_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
>+#define MMEA6_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
>+#define MMEA6_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
>+#define MMEA6_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
>+#define MMEA6_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
>+#define MMEA6_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
>+#define MMEA6_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
>+#define MMEA6_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
>+#define MMEA6_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
>+//MMEA6_SDP_DRAM_PRIORITY
>+#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
>+#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
>+#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
>+#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
>+#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
>+#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
>+#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
>+#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
>+#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
>+#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
>+#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
>+#define MMEA6_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
>+#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
>+#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
>+#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
>+#define MMEA6_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
>+//MMEA6_SDP_GMI_PRIORITY
>+#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
>+#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
>+#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
>+#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
>+#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
>+#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
>+#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
>+#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
>+#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
>+#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
>+#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
>+#define MMEA6_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
>+#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
>+#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
>+#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
>+#define MMEA6_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
>+//MMEA6_SDP_IO_PRIORITY
>+#define MMEA6_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
>+#define MMEA6_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
>+#define MMEA6_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
>+#define MMEA6_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
>+#define MMEA6_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
>+#define MMEA6_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
>+#define MMEA6_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
>+#define MMEA6_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
>+#define MMEA6_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
>+#define MMEA6_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
>+#define MMEA6_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
>+#define MMEA6_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
>+#define MMEA6_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
>+#define MMEA6_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
>+#define MMEA6_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
>+#define MMEA6_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
>+//MMEA6_SDP_CREDITS
>+#define MMEA6_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
>+#define MMEA6_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
>+#define MMEA6_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
>+#define MMEA6_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
>+#define MMEA6_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
>+#define MMEA6_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
>+//MMEA6_SDP_TAG_RESERVE0
>+#define MMEA6_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
>+#define MMEA6_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
>+#define MMEA6_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
>+#define MMEA6_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
>+#define MMEA6_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
>+#define MMEA6_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
>+#define MMEA6_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
>+#define MMEA6_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
>+//MMEA6_SDP_TAG_RESERVE1
>+#define MMEA6_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
>+#define MMEA6_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
>+#define MMEA6_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
>+#define MMEA6_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
>+#define MMEA6_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
>+#define MMEA6_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
>+#define MMEA6_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
>+#define MMEA6_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
>+//MMEA6_SDP_VCC_RESERVE0
>+#define MMEA6_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA6_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA6_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA6_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA6_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA6_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA6_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA6_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA6_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA6_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA6_SDP_VCC_RESERVE1
>+#define MMEA6_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA6_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA6_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA6_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA6_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA6_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA6_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA6_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA6_SDP_VCD_RESERVE0
>+#define MMEA6_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA6_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA6_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA6_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA6_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA6_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA6_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA6_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA6_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA6_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA6_SDP_VCD_RESERVE1
>+#define MMEA6_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA6_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA6_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA6_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA6_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA6_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA6_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA6_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA6_SDP_REQ_CNTL
>+#define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
>+#define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
>+#define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
>+#define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
>+#define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
>+#define MMEA6_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
>+#define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
>+#define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
>+#define MMEA6_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
>+#define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
>+#define MMEA6_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
>+#define MMEA6_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
>+//MMEA6_MISC
>+#define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
>+#define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
>+#define MMEA6_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
>+#define MMEA6_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
>+#define MMEA6_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
>+#define MMEA6_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
>+#define MMEA6_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
>+#define MMEA6_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
>+#define MMEA6_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
>+#define MMEA6_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
>+#define MMEA6_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
>+#define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
>+#define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
>+#define MMEA6_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
>+#define MMEA6_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
>+#define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
>+#define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
>+#define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
>+#define MMEA6_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
>+#define MMEA6_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
>+#define MMEA6_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
>+#define MMEA6_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
>+#define MMEA6_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
>+#define MMEA6_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
>+#define MMEA6_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
>+#define MMEA6_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
>+#define MMEA6_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
>+#define MMEA6_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
>+#define MMEA6_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
>+#define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
>+#define MMEA6_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
>+#define MMEA6_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
>+#define MMEA6_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
>+#define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
>+#define MMEA6_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
>+//MMEA6_LATENCY_SAMPLING
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
>+#define MMEA6_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
>+//MMEA6_PERFCOUNTER_LO
>+#define MMEA6_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define MMEA6_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//MMEA6_PERFCOUNTER_HI
>+#define MMEA6_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define MMEA6_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define MMEA6_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define MMEA6_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//MMEA6_PERFCOUNTER0_CFG
>+#define MMEA6_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA6_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA6_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA6_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA6_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA6_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA6_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA6_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA6_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA6_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA6_PERFCOUNTER1_CFG
>+#define MMEA6_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA6_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA6_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA6_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA6_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA6_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA6_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA6_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA6_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA6_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA6_PERFCOUNTER_RSLT_CNTL
>+#define MMEA6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define MMEA6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define MMEA6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define MMEA6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define MMEA6_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define MMEA6_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define MMEA6_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define MMEA6_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define MMEA6_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//MMEA6_EDC_CNT
>+#define MMEA6_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA6_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA6_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA6_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA6_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA6_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA6_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
>+#define MMEA6_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
>+#define MMEA6_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
>+#define MMEA6_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
>+#define MMEA6_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
>+#define MMEA6_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
>+#define MMEA6_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
>+#define MMEA6_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
>+#define MMEA6_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
>+#define MMEA6_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA6_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA6_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA6_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA6_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA6_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA6_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
>+#define MMEA6_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
>+#define MMEA6_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
>+#define MMEA6_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
>+#define MMEA6_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
>+#define MMEA6_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
>+#define MMEA6_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
>+#define MMEA6_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
>+#define MMEA6_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
>+//MMEA6_EDC_CNT2
>+#define MMEA6_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA6_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA6_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA6_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA6_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA6_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA6_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
>+#define MMEA6_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
>+#define MMEA6_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA6_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA6_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA6_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA6_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA6_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA6_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
>+#define MMEA6_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
>+//MMEA6_DSM_CNTL
>+#define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
>+#define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
>+#define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
>+#define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
>+#define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
>+#define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
>+#define MMEA6_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
>+#define MMEA6_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
>+#define MMEA6_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
>+#define MMEA6_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
>+#define MMEA6_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
>+#define MMEA6_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
>+#define MMEA6_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
>+#define MMEA6_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
>+#define MMEA6_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
>+#define MMEA6_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
>+#define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
>+#define MMEA6_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
>+#define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
>+#define MMEA6_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
>+#define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
>+#define MMEA6_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
>+#define MMEA6_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
>+#define MMEA6_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
>+#define MMEA6_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
>+#define MMEA6_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
>+#define MMEA6_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
>+#define MMEA6_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
>+#define MMEA6_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
>+#define MMEA6_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
>+#define MMEA6_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
>+#define MMEA6_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
>+//MMEA6_DSM_CNTLA
>+#define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
>+#define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
>+#define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
>+#define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
>+#define MMEA6_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
>+#define MMEA6_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
>+#define MMEA6_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
>+#define MMEA6_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
>+#define MMEA6_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
>+#define MMEA6_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
>+#define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
>+#define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
>+#define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
>+#define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
>+#define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
>+#define MMEA6_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
>+#define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
>+#define MMEA6_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
>+#define MMEA6_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
>+#define MMEA6_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
>+#define MMEA6_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
>+#define MMEA6_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
>+#define MMEA6_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
>+#define MMEA6_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
>+#define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
>+#define MMEA6_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
>+#define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
>+#define MMEA6_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
>+//MMEA6_DSM_CNTL2
>+#define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
>+#define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
>+#define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
>+#define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
>+#define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
>+#define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
>+#define MMEA6_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
>+#define MMEA6_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
>+#define MMEA6_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
>+#define MMEA6_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
>+#define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
>+#define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
>+#define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
>+#define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
>+#define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
>+#define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
>+#define MMEA6_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
>+#define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
>+#define MMEA6_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
>+#define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
>+#define MMEA6_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
>+#define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
>+#define MMEA6_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
>+#define MMEA6_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
>+#define MMEA6_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
>+#define MMEA6_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
>+#define MMEA6_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
>+#define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
>+#define MMEA6_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
>+#define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
>+#define MMEA6_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
>+#define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
>+#define MMEA6_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
>+#define MMEA6_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
>+//MMEA6_DSM_CNTL2A
>+#define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
>+#define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
>+#define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
>+#define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
>+#define MMEA6_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
>+#define MMEA6_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
>+#define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
>+#define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
>+#define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
>+#define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
>+#define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
>+#define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
>+#define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
>+#define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
>+#define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
>+#define MMEA6_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
>+#define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
>+#define MMEA6_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
>+#define MMEA6_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
>+#define MMEA6_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
>+#define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
>+#define MMEA6_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
>+#define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
>+#define MMEA6_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
>+#define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
>+#define MMEA6_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
>+#define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
>+#define MMEA6_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
>+//MMEA6_CGTT_CLK_CTRL
>+#define MMEA6_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
>+#define MMEA6_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
>+#define MMEA6_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
>+#define MMEA6_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
>+#define MMEA6_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
>+#define MMEA6_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
>+#define MMEA6_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
>+#define MMEA6_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
>+#define MMEA6_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
>+#define MMEA6_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
>+#define MMEA6_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
>+//MMEA6_EDC_MODE
>+#define MMEA6_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
>+#define MMEA6_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
>+#define MMEA6_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
>+#define MMEA6_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
>+#define MMEA6_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
>+#define MMEA6_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
>+#define MMEA6_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
>+#define MMEA6_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
>+#define MMEA6_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
>+#define MMEA6_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
>+//MMEA6_ERR_STATUS
>+#define MMEA6_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
>+#define MMEA6_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
>+#define MMEA6_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
>+#define MMEA6_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
>+#define MMEA6_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
>+#define MMEA6_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
>+#define MMEA6_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
>+#define MMEA6_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
>+#define MMEA6_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
>+#define MMEA6_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
>+#define MMEA6_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
>+#define MMEA6_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
>+#define MMEA6_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
>+#define MMEA6_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
>+//MMEA6_MISC2
>+#define MMEA6_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
>+#define MMEA6_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
>+#define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
>+#define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
>+#define MMEA6_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
>+#define MMEA6_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
>+#define MMEA6_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
>+#define MMEA6_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
>+#define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
>+#define MMEA6_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
>+#define MMEA6_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
>+#define MMEA6_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
>+//MMEA6_ADDRDEC_SELECT
>+#define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
>+#define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
>+#define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
>+#define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
>+#define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
>+#define MMEA6_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
>+#define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
>+#define MMEA6_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
>+//MMEA6_EDC_CNT3
>+#define MMEA6_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
>+#define MMEA6_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
>+#define MMEA6_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
>+#define MMEA6_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
>+#define MMEA6_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
>+#define MMEA6_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA6_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
>+#define MMEA6_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
>+#define MMEA6_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
>+#define MMEA6_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
>+#define MMEA6_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
>+#define MMEA6_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
>+#define MMEA6_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA6_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
>+
>+
>+// addressBlock: mmhub_ea_mmeadec7
>+//MMEA7_DRAM_RD_CLI2GRP_MAP0
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA7_DRAM_RD_CLI2GRP_MAP1
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA7_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA7_DRAM_WR_CLI2GRP_MAP0
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                         0x0
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                         0x2
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                         0x4
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                         0x6
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                         0x8
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                         0xa
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                         0xc
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                         0xe
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                         0x10
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                         0x12
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                        0x14
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                        0x16
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                        0x18
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                        0x1a
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                        0x1c
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                        0x1e
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                           0x00000003L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                           0x0000000CL
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                           0x00000030L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                           0x000000C0L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                           0x00000300L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                           0x00000C00L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                           0x00003000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                           0x0000C000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                           0x00030000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                           0x000C0000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                          0x00300000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                          0x00C00000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                          0x03000000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                          0x0C000000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                          0x30000000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                          0xC0000000L
>+//MMEA7_DRAM_WR_CLI2GRP_MAP1
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                        0x0
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                        0x2
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                        0x4
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                        0x6
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                        0x8
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                        0xa
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                        0xc
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                        0xe
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                        0x10
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                        0x12
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                        0x14
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                        0x16
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                        0x18
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                        0x1a
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                        0x1c
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                        0x1e
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                          0x00000003L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                          0x0000000CL
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                          0x00000030L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                          0x000000C0L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                          0x00000300L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                          0x00000C00L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                          0x00003000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                          0x0000C000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                          0x00030000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                          0x000C0000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                          0x00300000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                          0x00C00000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                          0x03000000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                          0x0C000000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                          0x30000000L
>+#define MMEA7_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                          0xC0000000L
>+//MMEA7_DRAM_RD_GRP2VC_MAP
>+#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA7_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA7_DRAM_WR_GRP2VC_MAP
>+#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                            0x0
>+#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                            0x3
>+#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                            0x6
>+#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                            0x9
>+#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                              0x00000007L
>+#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                              0x00000038L
>+#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                              0x000001C0L
>+#define MMEA7_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                              0x00000E00L
>+//MMEA7_DRAM_RD_LAZY
>+#define MMEA7_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA7_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA7_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA7_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA7_DRAM_RD_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA7_DRAM_RD_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA7_DRAM_RD_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA7_DRAM_RD_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA7_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA7_DRAM_WR_LAZY
>+#define MMEA7_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT                                                               0x0
>+#define MMEA7_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT                                                               0x3
>+#define MMEA7_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT                                                               0x6
>+#define MMEA7_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT                                                               0x9
>+#define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                           0xc
>+#define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                          0x14
>+#define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                          0x1b
>+#define MMEA7_DRAM_WR_LAZY__GROUP0_DELAY_MASK                                                                 0x00000007L
>+#define MMEA7_DRAM_WR_LAZY__GROUP1_DELAY_MASK                                                                 0x00000038L
>+#define MMEA7_DRAM_WR_LAZY__GROUP2_DELAY_MASK                                                                 0x000001C0L
>+#define MMEA7_DRAM_WR_LAZY__GROUP3_DELAY_MASK                                                                 0x00000E00L
>+#define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                             0x0003F000L
>+#define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                            0x07F00000L
>+#define MMEA7_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                            0x78000000L
>+//MMEA7_DRAM_RD_CAM_CNTL
>+#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA7_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA7_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA7_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA7_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA7_DRAM_WR_CAM_CNTL
>+#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                           0x0
>+#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                           0x4
>+#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                           0x8
>+#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                           0xc
>+#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                   0x10
>+#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                   0x13
>+#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                   0x16
>+#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                   0x19
>+#define MMEA7_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                           0x1c
>+#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                             0x0000000FL
>+#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                             0x000000F0L
>+#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                             0x00000F00L
>+#define MMEA7_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                             0x0000F000L
>+#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                     0x00070000L
>+#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                     0x00380000L
>+#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                     0x01C00000L
>+#define MMEA7_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                     0x0E000000L
>+#define MMEA7_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                             0x10000000L
>+//MMEA7_DRAM_PAGE_BURST
>+#define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                             0x0
>+#define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                             0x8
>+#define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                             0x10
>+#define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                             0x18
>+#define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK                                                               0x000000FFL
>+#define MMEA7_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK                                                               0x0000FF00L
>+#define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK                                                               0x00FF0000L
>+#define MMEA7_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK                                                               0xFF000000L
>+//MMEA7_DRAM_RD_PRI_AGE
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA7_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA7_DRAM_WR_PRI_AGE
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                       0x0
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                       0x3
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                       0x6
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                       0x9
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                  0xc
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                  0xf
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                  0x12
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                  0x15
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                         0x00000007L
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                         0x00000038L
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                         0x000001C0L
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                         0x00000E00L
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                    0x00007000L
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                    0x00038000L
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                    0x001C0000L
>+#define MMEA7_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                    0x00E00000L
>+//MMEA7_DRAM_RD_PRI_QUEUING
>+#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA7_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA7_DRAM_WR_PRI_QUEUING
>+#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA7_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                            0x00000E00L
>+//MMEA7_DRAM_RD_PRI_FIXED
>+#define MMEA7_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA7_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA7_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA7_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA7_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA7_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA7_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA7_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA7_DRAM_WR_PRI_FIXED
>+#define MMEA7_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                              0x0
>+#define MMEA7_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                              0x3
>+#define MMEA7_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                              0x6
>+#define MMEA7_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                              0x9
>+#define MMEA7_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                0x00000007L
>+#define MMEA7_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                0x00000038L
>+#define MMEA7_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                0x000001C0L
>+#define MMEA7_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                0x00000E00L
>+//MMEA7_DRAM_RD_PRI_URGENCY
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA7_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA7_DRAM_WR_PRI_URGENCY
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                          0x0
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                          0x3
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                          0x6
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                          0x9
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                 0xc
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                 0xd
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                 0xe
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                 0xf
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                            0x00000007L
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                            0x00000038L
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                            0x000001C0L
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                            0x00000E00L
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                   0x00001000L
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                   0x00002000L
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                   0x00004000L
>+#define MMEA7_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                   0x00008000L
>+//MMEA7_DRAM_RD_PRI_QUANT_PRI1
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA7_DRAM_RD_PRI_QUANT_PRI2
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA7_DRAM_RD_PRI_QUANT_PRI3
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA7_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA7_DRAM_WR_PRI_QUANT_PRI1
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA7_DRAM_WR_PRI_QUANT_PRI2
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA7_DRAM_WR_PRI_QUANT_PRI3
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                 0x0
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                 0x8
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                 0x10
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                 0x18
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                   0x000000FFL
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                   0x0000FF00L
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                   0x00FF0000L
>+#define MMEA7_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                   0xFF000000L
>+//MMEA7_GMI_RD_CLI2GRP_MAP0
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA7_GMI_RD_CLI2GRP_MAP1
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA7_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA7_GMI_WR_CLI2GRP_MAP0
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                          0x0
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                          0x2
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                          0x4
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                          0x6
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                          0x8
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                          0xa
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                          0xc
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                          0xe
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                          0x10
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                          0x12
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                         0x14
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                         0x16
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                         0x18
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                         0x1a
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                         0x1c
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                         0x1e
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                            0x00000003L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                            0x0000000CL
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                            0x00000030L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                            0x000000C0L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                            0x00000300L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                            0x00000C00L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                            0x00003000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                            0x0000C000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                            0x00030000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                            0x000C0000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                           0x00300000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                           0x00C00000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                           0x03000000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                           0x0C000000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                           0x30000000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                           0xC0000000L
>+//MMEA7_GMI_WR_CLI2GRP_MAP1
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                         0x0
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                         0x2
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                         0x4
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                         0x6
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                         0x8
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                         0xa
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                         0xc
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                         0xe
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                         0x10
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                         0x12
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                         0x14
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                         0x16
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                         0x18
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                         0x1a
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                         0x1c
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                         0x1e
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                           0x00000003L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                           0x0000000CL
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                           0x00000030L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                           0x000000C0L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                           0x00000300L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                           0x00000C00L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                           0x00003000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                           0x0000C000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                           0x00030000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                           0x000C0000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                           0x00300000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                           0x00C00000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                           0x03000000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                           0x0C000000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                           0x30000000L
>+#define MMEA7_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                           0xC0000000L
>+//MMEA7_GMI_RD_GRP2VC_MAP
>+#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA7_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA7_GMI_WR_GRP2VC_MAP
>+#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT                                                             0x0
>+#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT                                                             0x3
>+#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT                                                             0x6
>+#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT                                                             0x9
>+#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK                                                               0x00000007L
>+#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK                                                               0x00000038L
>+#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK                                                               0x000001C0L
>+#define MMEA7_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK                                                               0x00000E00L
>+//MMEA7_GMI_RD_LAZY
>+#define MMEA7_GMI_RD_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA7_GMI_RD_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA7_GMI_RD_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA7_GMI_RD_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA7_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA7_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA7_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA7_GMI_RD_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA7_GMI_RD_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA7_GMI_RD_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA7_GMI_RD_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA7_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA7_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA7_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA7_GMI_WR_LAZY
>+#define MMEA7_GMI_WR_LAZY__GROUP0_DELAY__SHIFT                                                                0x0
>+#define MMEA7_GMI_WR_LAZY__GROUP1_DELAY__SHIFT                                                                0x3
>+#define MMEA7_GMI_WR_LAZY__GROUP2_DELAY__SHIFT                                                                0x6
>+#define MMEA7_GMI_WR_LAZY__GROUP3_DELAY__SHIFT                                                                0x9
>+#define MMEA7_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT                                                            0xc
>+#define MMEA7_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT                                                           0x14
>+#define MMEA7_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT                                                           0x1b
>+#define MMEA7_GMI_WR_LAZY__GROUP0_DELAY_MASK                                                                  0x00000007L
>+#define MMEA7_GMI_WR_LAZY__GROUP1_DELAY_MASK                                                                  0x00000038L
>+#define MMEA7_GMI_WR_LAZY__GROUP2_DELAY_MASK                                                                  0x000001C0L
>+#define MMEA7_GMI_WR_LAZY__GROUP3_DELAY_MASK                                                                  0x00000E00L
>+#define MMEA7_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK                                                              0x0003F000L
>+#define MMEA7_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK                                                             0x07F00000L
>+#define MMEA7_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK                                                             0x78000000L
>+//MMEA7_GMI_RD_CAM_CNTL
>+#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA7_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA7_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA7_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA7_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA7_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA7_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA7_GMI_WR_CAM_CNTL
>+#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT                                                            0x0
>+#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT                                                            0x4
>+#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT                                                            0x8
>+#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT                                                            0xc
>+#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT                                                    0x10
>+#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT                                                    0x13
>+#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT                                                    0x16
>+#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT                                                    0x19
>+#define MMEA7_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT                                                            0x1c
>+#define MMEA7_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT                                                      0x1d
>+#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK                                                              0x0000000FL
>+#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK                                                              0x000000F0L
>+#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK                                                              0x00000F00L
>+#define MMEA7_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK                                                              0x0000F000L
>+#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK                                                      0x00070000L
>+#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK                                                      0x00380000L
>+#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK                                                      0x01C00000L
>+#define MMEA7_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK                                                      0x0E000000L
>+#define MMEA7_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK                                                              0x10000000L
>+#define MMEA7_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK                                                        0x20000000L
>+//MMEA7_GMI_PAGE_BURST
>+#define MMEA7_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA7_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA7_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA7_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA7_GMI_PAGE_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA7_GMI_PAGE_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA7_GMI_PAGE_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA7_GMI_PAGE_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA7_GMI_RD_PRI_AGE
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA7_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA7_GMI_WR_PRI_AGE
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                        0x0
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                        0x3
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                        0x6
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                        0x9
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                   0xc
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                   0xf
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                   0x12
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                   0x15
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                          0x00000007L
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                          0x00000038L
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                          0x000001C0L
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                          0x00000E00L
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                     0x00007000L
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                     0x00038000L
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                     0x001C0000L
>+#define MMEA7_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                     0x00E00000L
>+//MMEA7_GMI_RD_PRI_QUEUING
>+#define MMEA7_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA7_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA7_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA7_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA7_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA7_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA7_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA7_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA7_GMI_WR_PRI_QUEUING
>+#define MMEA7_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA7_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA7_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA7_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA7_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA7_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA7_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA7_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                             0x00000E00L
>+//MMEA7_GMI_RD_PRI_FIXED
>+#define MMEA7_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA7_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA7_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA7_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA7_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA7_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA7_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA7_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA7_GMI_WR_PRI_FIXED
>+#define MMEA7_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                               0x0
>+#define MMEA7_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                               0x3
>+#define MMEA7_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                               0x6
>+#define MMEA7_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                               0x9
>+#define MMEA7_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                 0x00000007L
>+#define MMEA7_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                 0x00000038L
>+#define MMEA7_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                 0x000001C0L
>+#define MMEA7_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                 0x00000E00L
>+//MMEA7_GMI_RD_PRI_URGENCY
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA7_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA7_GMI_WR_PRI_URGENCY
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                           0x0
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                           0x3
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                           0x6
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                           0x9
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                  0xc
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                  0xd
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                  0xe
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                  0xf
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                             0x00000007L
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                             0x00000038L
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                             0x000001C0L
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                             0x00000E00L
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                    0x00001000L
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                    0x00002000L
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                    0x00004000L
>+#define MMEA7_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                    0x00008000L
>+//MMEA7_GMI_RD_PRI_URGENCY_MASKING
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA7_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA7_GMI_WR_PRI_URGENCY_MASKING
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                    0x0
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                    0x1
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                    0x2
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                    0x3
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                    0x4
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                    0x5
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                    0x6
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                    0x7
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                    0x8
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                    0x9
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                   0xa
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                   0xb
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                   0xc
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                   0xd
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                   0xe
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                   0xf
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                   0x10
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                   0x11
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                   0x12
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                   0x13
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                   0x14
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                   0x15
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                   0x16
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                   0x17
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                   0x18
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                   0x19
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                   0x1a
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                   0x1b
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                   0x1c
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                   0x1d
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                   0x1e
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                   0x1f
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                      0x00000001L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                      0x00000002L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                      0x00000004L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                      0x00000008L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                      0x00000010L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                      0x00000020L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                      0x00000040L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                      0x00000080L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                      0x00000100L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                      0x00000200L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                     0x00000400L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                     0x00000800L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                     0x00001000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                     0x00002000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                     0x00004000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                     0x00008000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                     0x00010000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                     0x00020000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                     0x00040000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                     0x00080000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                     0x00100000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                     0x00200000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                     0x00400000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                     0x00800000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                     0x01000000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                     0x02000000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                     0x04000000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                     0x08000000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                     0x10000000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                     0x20000000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                     0x40000000L
>+#define MMEA7_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                     0x80000000L
>+//MMEA7_GMI_RD_PRI_QUANT_PRI1
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA7_GMI_RD_PRI_QUANT_PRI2
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA7_GMI_RD_PRI_QUANT_PRI3
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA7_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA7_GMI_WR_PRI_QUANT_PRI1
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA7_GMI_WR_PRI_QUANT_PRI2
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA7_GMI_WR_PRI_QUANT_PRI3
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                  0x0
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                  0x8
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                  0x10
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                  0x18
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                    0x000000FFL
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                    0x0000FF00L
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                    0x00FF0000L
>+#define MMEA7_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                    0xFF000000L
>+//MMEA7_ADDRNORM_BASE_ADDR0
>+#define MMEA7_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA7_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA7_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA7_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA7_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA7_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA7_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA7_ADDRNORM_LIMIT_ADDR0
>+#define MMEA7_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA7_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA7_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA7_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA7_ADDRNORM_BASE_ADDR1
>+#define MMEA7_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA7_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA7_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA7_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA7_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA7_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA7_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA7_ADDRNORM_LIMIT_ADDR1
>+#define MMEA7_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA7_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA7_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA7_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA7_ADDRNORM_OFFSET_ADDR1
>+#define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA7_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA7_ADDRNORM_BASE_ADDR2
>+#define MMEA7_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA7_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA7_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA7_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA7_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA7_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA7_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA7_ADDRNORM_LIMIT_ADDR2
>+#define MMEA7_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA7_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA7_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA7_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA7_ADDRNORM_BASE_ADDR3
>+#define MMEA7_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA7_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA7_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA7_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA7_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA7_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA7_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA7_ADDRNORM_LIMIT_ADDR3
>+#define MMEA7_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA7_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA7_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA7_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA7_ADDRNORM_OFFSET_ADDR3
>+#define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA7_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA7_ADDRNORM_BASE_ADDR4
>+#define MMEA7_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA7_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA7_ADDRNORM_BASE_ADDR4__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA7_ADDRNORM_BASE_ADDR4__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA7_ADDRNORM_BASE_ADDR4__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA7_ADDRNORM_BASE_ADDR4__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA7_ADDRNORM_BASE_ADDR4__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA7_ADDRNORM_LIMIT_ADDR4
>+#define MMEA7_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA7_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA7_ADDRNORM_LIMIT_ADDR4__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA7_ADDRNORM_LIMIT_ADDR4__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA7_ADDRNORM_BASE_ADDR5
>+#define MMEA7_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL__SHIFT                                                        0x0
>+#define MMEA7_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN__SHIFT                                                   0x1
>+#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN__SHIFT                                                      0x2
>+#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES__SHIFT                                                      0x6
>+#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS__SHIFT                                                   0x8
>+#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL__SHIFT                                                      0x9
>+#define MMEA7_ADDRNORM_BASE_ADDR5__BASE_ADDR__SHIFT                                                           0xc
>+#define MMEA7_ADDRNORM_BASE_ADDR5__ADDR_RNG_VAL_MASK                                                          0x00000001L
>+#define MMEA7_ADDRNORM_BASE_ADDR5__LGCY_MMIO_HOLE_EN_MASK                                                     0x00000002L
>+#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_CHAN_MASK                                                        0x0000003CL
>+#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_DIES_MASK                                                        0x000000C0L
>+#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_NUM_SOCKETS_MASK                                                     0x00000100L
>+#define MMEA7_ADDRNORM_BASE_ADDR5__INTLV_ADDR_SEL_MASK                                                        0x00000E00L
>+#define MMEA7_ADDRNORM_BASE_ADDR5__BASE_ADDR_MASK                                                             0xFFFFF000L
>+//MMEA7_ADDRNORM_LIMIT_ADDR5
>+#define MMEA7_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID__SHIFT                                                      0x0
>+#define MMEA7_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR__SHIFT                                                         0xc
>+#define MMEA7_ADDRNORM_LIMIT_ADDR5__DST_FABRIC_ID_MASK                                                        0x0000001FL
>+#define MMEA7_ADDRNORM_LIMIT_ADDR5__LIMIT_ADDR_MASK                                                           0xFFFFF000L
>+//MMEA7_ADDRNORM_OFFSET_ADDR5
>+#define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN__SHIFT                                                 0x0
>+#define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET__SHIFT                                                    0x14
>+#define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_EN_MASK                                                   0x00000001L
>+#define MMEA7_ADDRNORM_OFFSET_ADDR5__HI_ADDR_OFFSET_MASK                                                      0xFFF00000L
>+//MMEA7_ADDRNORMDRAM_HOLE_CNTL
>+#define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                  0x0
>+#define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                 0x7
>+#define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                    0x00000001L
>+#define MMEA7_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                   0x0000FF80L
>+//MMEA7_ADDRNORMGMI_HOLE_CNTL
>+#define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT                                                   0x0
>+#define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT                                                  0x7
>+#define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK                                                     0x00000001L
>+#define MMEA7_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK                                                    0x0000FF80L
>+//MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG
>+#define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT                                        0x0
>+#define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT                                        0x6
>+#define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK                                          0x0000003FL
>+#define MMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK                                          0x00000FC0L
>+//MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG
>+#define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT                                         0x0
>+#define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT                                         0x6
>+#define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK                                           0x0000003FL
>+#define MMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK                                           0x00000FC0L
>+//MMEA7_ADDRDEC_BANK_CFG
>+#define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT                                                          0x6
>+#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT                                                     0xc
>+#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT                                                      0xf
>+#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT                                              0x12
>+#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT                                               0x13
>+#define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK                                                           0x0000003FL
>+#define MMEA7_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK                                                            0x00000FC0L
>+#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK                                                       0x00007000L
>+#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK                                                        0x00038000L
>+#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK                                                0x00040000L
>+#define MMEA7_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK                                                 0x00080000L
>+//MMEA7_ADDRDEC_MISC_CFG
>+#define MMEA7_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT                                                                0x0
>+#define MMEA7_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT                                                                0x1
>+#define MMEA7_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT                                                                0x2
>+#define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT                                                          0x8
>+#define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT                                                           0x9
>+#define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT                                                            0x11
>+#define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT                                                           0x16
>+#define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT                                                            0x18
>+#define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT                                                           0x1a
>+#define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT                                                            0x1d
>+#define MMEA7_ADDRDEC_MISC_CFG__VCM_EN0_MASK                                                                  0x00000001L
>+#define MMEA7_ADDRDEC_MISC_CFG__VCM_EN1_MASK                                                                  0x00000002L
>+#define MMEA7_ADDRDEC_MISC_CFG__VCM_EN2_MASK                                                                  0x00000004L
>+#define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK                                                            0x00000100L
>+#define MMEA7_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK                                                             0x00000200L
>+#define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK                                                             0x0001F000L
>+#define MMEA7_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK                                                              0x003E0000L
>+#define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK                                                             0x00C00000L
>+#define MMEA7_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK                                                              0x03000000L
>+#define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK                                                             0x1C000000L
>+#define MMEA7_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK                                                              0xE0000000L
>+//MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                  0x0
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                     0xe
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                    0x00000001L
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__COL_XOR_MASK                                                       0x00003FFEL
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_BANK5__ROW_XOR_MASK                                                       0xFFFFC000L
>+//MMEA7_ADDRDECDRAM_ADDR_HASH_PC
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT                                                        0xe
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK                                                          0x00003FFEL
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK                                                          0xFFFFC000L
>+//MMEA7_ADDRDECDRAM_ADDR_HASH_PC2
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                      0x0
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK                                                        0x0000003FL
>+//MMEA7_ADDRDECDRAM_ADDR_HASH_CS0
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDECDRAM_ADDR_HASH_CS1
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                    0x0
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                      0x00000001L
>+#define MMEA7_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDECDRAM_HARVEST_ENABLE
>+#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                  0x0
>+#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                 0x1
>+#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                  0x2
>+#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                 0x3
>+#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                  0x4
>+#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                 0x5
>+#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                    0x00000001L
>+#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                   0x00000002L
>+#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                    0x00000004L
>+#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                   0x00000008L
>+#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                    0x00000010L
>+#define MMEA7_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                   0x00000020L
>+//MMEA7_ADDRDECGMI_ADDR_HASH_BANK0
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR__SHIFT                                                      0x1
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK0__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA7_ADDRDECGMI_ADDR_HASH_BANK1
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR__SHIFT                                                      0x1
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK1__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA7_ADDRDECGMI_ADDR_HASH_BANK2
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR__SHIFT                                                      0x1
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK2__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA7_ADDRDECGMI_ADDR_HASH_BANK3
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR__SHIFT                                                      0x1
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK3__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA7_ADDRDECGMI_ADDR_HASH_BANK4
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR__SHIFT                                                      0x1
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK4__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA7_ADDRDECGMI_ADDR_HASH_BANK5
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE__SHIFT                                                   0x0
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR__SHIFT                                                      0x1
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR__SHIFT                                                      0xe
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__XOR_ENABLE_MASK                                                     0x00000001L
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__COL_XOR_MASK                                                        0x00003FFEL
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_BANK5__ROW_XOR_MASK                                                        0xFFFFC000L
>+//MMEA7_ADDRDECGMI_ADDR_HASH_PC
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE__SHIFT                                                      0x0
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_PC__COL_XOR__SHIFT                                                         0x1
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR__SHIFT                                                         0xe
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_PC__XOR_ENABLE_MASK                                                        0x00000001L
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_PC__COL_XOR_MASK                                                           0x00003FFEL
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_PC__ROW_XOR_MASK                                                           0xFFFFC000L
>+//MMEA7_ADDRDECGMI_ADDR_HASH_PC2
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR__SHIFT                                                       0x0
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_PC2__BANK_XOR_MASK                                                         0x0000003FL
>+//MMEA7_ADDRDECGMI_ADDR_HASH_CS0
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR__SHIFT                                                         0x1
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_CS0__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA7_ADDRDECGMI_ADDR_HASH_CS1
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE__SHIFT                                                     0x0
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR__SHIFT                                                         0x1
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__XOR_ENABLE_MASK                                                       0x00000001L
>+#define MMEA7_ADDRDECGMI_ADDR_HASH_CS1__NA_XOR_MASK                                                           0xFFFFFFFEL
>+//MMEA7_ADDRDECGMI_HARVEST_ENABLE
>+#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT                                                   0x0
>+#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT                                                  0x1
>+#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT                                                   0x2
>+#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT                                                  0x3
>+#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT                                                   0x4
>+#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT                                                  0x5
>+#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK                                                     0x00000001L
>+#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK                                                    0x00000002L
>+#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK                                                     0x00000004L
>+#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK                                                    0x00000008L
>+#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK                                                     0x00000010L
>+#define MMEA7_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK                                                    0x00000020L
>+//MMEA7_ADDRDEC0_BASE_ADDR_CS0
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDEC0_BASE_ADDR_CS1
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDEC0_BASE_ADDR_CS2
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDEC0_BASE_ADDR_CS3
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA7_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDEC0_BASE_ADDR_SECCS0
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA7_ADDRDEC0_BASE_ADDR_SECCS1
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA7_ADDRDEC0_BASE_ADDR_SECCS2
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA7_ADDRDEC0_BASE_ADDR_SECCS3
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA7_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA7_ADDRDEC0_ADDR_MASK_CS01
>+#define MMEA7_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA7_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA7_ADDRDEC0_ADDR_MASK_CS23
>+#define MMEA7_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA7_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA7_ADDRDEC0_ADDR_MASK_SECCS01
>+#define MMEA7_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA7_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA7_ADDRDEC0_ADDR_MASK_SECCS23
>+#define MMEA7_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA7_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA7_ADDRDEC0_ADDR_CFG_CS01
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA7_ADDRDEC0_ADDR_CFG_CS23
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA7_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA7_ADDRDEC0_ADDR_SEL_CS01
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA7_ADDRDEC0_ADDR_SEL_CS23
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA7_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA7_ADDRDEC0_ADDR_SEL2_CS01
>+#define MMEA7_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA7_ADDRDEC0_ADDR_SEL2_CS23
>+#define MMEA7_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA7_ADDRDEC0_COL_SEL_LO_CS01
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA7_ADDRDEC0_COL_SEL_LO_CS23
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA7_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA7_ADDRDEC0_COL_SEL_HI_CS01
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA7_ADDRDEC0_COL_SEL_HI_CS23
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA7_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA7_ADDRDEC0_RM_SEL_CS01
>+#define MMEA7_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA7_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA7_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA7_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA7_ADDRDEC0_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA7_ADDRDEC0_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA7_ADDRDEC0_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA7_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA7_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA7_ADDRDEC0_RM_SEL_CS23
>+#define MMEA7_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA7_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA7_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA7_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA7_ADDRDEC0_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA7_ADDRDEC0_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA7_ADDRDEC0_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA7_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA7_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA7_ADDRDEC0_RM_SEL_SECCS01
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA7_ADDRDEC0_RM_SEL_SECCS23
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA7_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA7_ADDRDEC1_BASE_ADDR_CS0
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDEC1_BASE_ADDR_CS1
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDEC1_BASE_ADDR_CS2
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDEC1_BASE_ADDR_CS3
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA7_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDEC1_BASE_ADDR_SECCS0
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA7_ADDRDEC1_BASE_ADDR_SECCS1
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA7_ADDRDEC1_BASE_ADDR_SECCS2
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA7_ADDRDEC1_BASE_ADDR_SECCS3
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA7_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA7_ADDRDEC1_ADDR_MASK_CS01
>+#define MMEA7_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA7_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA7_ADDRDEC1_ADDR_MASK_CS23
>+#define MMEA7_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA7_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA7_ADDRDEC1_ADDR_MASK_SECCS01
>+#define MMEA7_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA7_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA7_ADDRDEC1_ADDR_MASK_SECCS23
>+#define MMEA7_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA7_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA7_ADDRDEC1_ADDR_CFG_CS01
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA7_ADDRDEC1_ADDR_CFG_CS23
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA7_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA7_ADDRDEC1_ADDR_SEL_CS01
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA7_ADDRDEC1_ADDR_SEL_CS23
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA7_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA7_ADDRDEC1_ADDR_SEL2_CS01
>+#define MMEA7_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA7_ADDRDEC1_ADDR_SEL2_CS23
>+#define MMEA7_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA7_ADDRDEC1_COL_SEL_LO_CS01
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA7_ADDRDEC1_COL_SEL_LO_CS23
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA7_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA7_ADDRDEC1_COL_SEL_HI_CS01
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA7_ADDRDEC1_COL_SEL_HI_CS23
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA7_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA7_ADDRDEC1_RM_SEL_CS01
>+#define MMEA7_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA7_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA7_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA7_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA7_ADDRDEC1_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA7_ADDRDEC1_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA7_ADDRDEC1_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA7_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA7_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA7_ADDRDEC1_RM_SEL_CS23
>+#define MMEA7_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA7_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA7_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA7_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA7_ADDRDEC1_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA7_ADDRDEC1_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA7_ADDRDEC1_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA7_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA7_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA7_ADDRDEC1_RM_SEL_SECCS01
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA7_ADDRDEC1_RM_SEL_SECCS23
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA7_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA7_ADDRDEC2_BASE_ADDR_CS0
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK                                                              0x00000001L
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDEC2_BASE_ADDR_CS1
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK                                                              0x00000001L
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDEC2_BASE_ADDR_CS2
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK                                                              0x00000001L
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDEC2_BASE_ADDR_CS3
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT                                                        0x1
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK                                                              0x00000001L
>+#define MMEA7_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK                                                          0xFFFFFFFEL
>+//MMEA7_ADDRDEC2_BASE_ADDR_SECCS0
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK                                                           0x00000001L
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA7_ADDRDEC2_BASE_ADDR_SECCS1
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK                                                           0x00000001L
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA7_ADDRDEC2_BASE_ADDR_SECCS2
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK                                                           0x00000001L
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA7_ADDRDEC2_BASE_ADDR_SECCS3
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT                                                         0x0
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT                                                     0x1
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK                                                           0x00000001L
>+#define MMEA7_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK                                                       0xFFFFFFFEL
>+//MMEA7_ADDRDEC2_ADDR_MASK_CS01
>+#define MMEA7_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA7_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA7_ADDRDEC2_ADDR_MASK_CS23
>+#define MMEA7_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT                                                       0x1
>+#define MMEA7_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK                                                         0xFFFFFFFEL
>+//MMEA7_ADDRDEC2_ADDR_MASK_SECCS01
>+#define MMEA7_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA7_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA7_ADDRDEC2_ADDR_MASK_SECCS23
>+#define MMEA7_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT                                                    0x1
>+#define MMEA7_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK                                                      0xFFFFFFFEL
>+//MMEA7_ADDRDEC2_ADDR_CFG_CS01
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT                                                          0x10
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA7_ADDRDEC2_ADDR_CFG_CS23
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT                                                  0x1
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT                                                       0x8
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT                                                       0xc
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT                                                          0x10
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT                                                        0x14
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT                                                        0x1f
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK                                                    0x0000000EL
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK                                                             0x00000030L
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK                                                         0x00000F00L
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK                                                         0x0000F000L
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK                                                            0x000F0000L
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK                                                          0x00300000L
>+#define MMEA7_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK                                                          0x80000000L
>+//MMEA7_ADDRDEC2_ADDR_SEL_CS01
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT                                                            0x4
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT                                                            0x8
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT                                                            0xc
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT                                                            0x10
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT                                                           0x18
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK                                                              0x0000000FL
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK                                                              0x000000F0L
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK                                                              0x00000F00L
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK                                                              0x0000F000L
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK                                                              0x001F0000L
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA7_ADDRDEC2_ADDR_SEL_CS23
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT                                                            0x0
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT                                                            0x4
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT                                                            0x8
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT                                                            0xc
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT                                                            0x10
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT                                                           0x18
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT                                                           0x1c
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK                                                              0x0000000FL
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK                                                              0x000000F0L
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK                                                              0x00000F00L
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK                                                              0x0000F000L
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK                                                              0x001F0000L
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK                                                             0x0F000000L
>+#define MMEA7_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK                                                             0xF0000000L
>+//MMEA7_ADDRDEC2_ADDR_SEL2_CS01
>+#define MMEA7_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK                                                             0x0000001FL
>+//MMEA7_ADDRDEC2_ADDR_SEL2_CS23
>+#define MMEA7_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK                                                             0x0000001FL
>+//MMEA7_ADDRDEC2_COL_SEL_LO_CS01
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT                                                           0x8
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT                                                           0x10
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT                                                           0x14
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT                                                           0x18
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT                                                           0x1c
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK                                                             0x0000000FL
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK                                                             0x000000F0L
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK                                                             0x00000F00L
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK                                                             0x0000F000L
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK                                                             0x000F0000L
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK                                                             0x00F00000L
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK                                                             0x0F000000L
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK                                                             0xF0000000L
>+//MMEA7_ADDRDEC2_COL_SEL_LO_CS23
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT                                                           0x8
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT                                                           0x10
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT                                                           0x14
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT                                                           0x18
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT                                                           0x1c
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK                                                             0x0000000FL
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK                                                             0x000000F0L
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK                                                             0x00000F00L
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK                                                             0x0000F000L
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK                                                             0x000F0000L
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK                                                             0x00F00000L
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK                                                             0x0F000000L
>+#define MMEA7_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK                                                             0xF0000000L
>+//MMEA7_ADDRDEC2_COL_SEL_HI_CS01
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT                                                          0x8
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT                                                          0xc
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT                                                          0x10
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT                                                          0x14
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT                                                          0x18
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT                                                          0x1c
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK                                                             0x0000000FL
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK                                                             0x000000F0L
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK                                                            0x00000F00L
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK                                                            0x0000F000L
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK                                                            0x000F0000L
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK                                                            0x00F00000L
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK                                                            0x0F000000L
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK                                                            0xF0000000L
>+//MMEA7_ADDRDEC2_COL_SEL_HI_CS23
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT                                                           0x0
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT                                                           0x4
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT                                                          0x8
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT                                                          0xc
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT                                                          0x10
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT                                                          0x14
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT                                                          0x18
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT                                                          0x1c
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK                                                             0x0000000FL
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK                                                             0x000000F0L
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK                                                            0x00000F00L
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK                                                            0x0000F000L
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK                                                            0x000F0000L
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK                                                            0x00F00000L
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK                                                            0x0F000000L
>+#define MMEA7_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK                                                            0xF0000000L
>+//MMEA7_ADDRDEC2_RM_SEL_CS01
>+#define MMEA7_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT                                                                0x0
>+#define MMEA7_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT                                                                0x4
>+#define MMEA7_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT                                                                0x8
>+#define MMEA7_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA7_ADDRDEC2_RM_SEL_CS01__RM0_MASK                                                                  0x0000000FL
>+#define MMEA7_ADDRDEC2_RM_SEL_CS01__RM1_MASK                                                                  0x000000F0L
>+#define MMEA7_ADDRDEC2_RM_SEL_CS01__RM2_MASK                                                                  0x00000F00L
>+#define MMEA7_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA7_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA7_ADDRDEC2_RM_SEL_CS23
>+#define MMEA7_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT                                                                0x0
>+#define MMEA7_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT                                                                0x4
>+#define MMEA7_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT                                                                0x8
>+#define MMEA7_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT                                                           0xc
>+#define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT                                               0x10
>+#define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT                                                0x12
>+#define MMEA7_ADDRDEC2_RM_SEL_CS23__RM0_MASK                                                                  0x0000000FL
>+#define MMEA7_ADDRDEC2_RM_SEL_CS23__RM1_MASK                                                                  0x000000F0L
>+#define MMEA7_ADDRDEC2_RM_SEL_CS23__RM2_MASK                                                                  0x00000F00L
>+#define MMEA7_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK                                                             0x0000F000L
>+#define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK                                                 0x00030000L
>+#define MMEA7_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK                                                  0x000C0000L
>+//MMEA7_ADDRDEC2_RM_SEL_SECCS01
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT                                                             0x0
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT                                                             0x4
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT                                                             0x8
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK                                                               0x0000000FL
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK                                                               0x000000F0L
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK                                                               0x00000F00L
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA7_ADDRDEC2_RM_SEL_SECCS23
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT                                                             0x0
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT                                                             0x4
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT                                                             0x8
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT                                                        0xc
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT                                            0x10
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT                                             0x12
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK                                                               0x0000000FL
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK                                                               0x000000F0L
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK                                                               0x00000F00L
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK                                                          0x0000F000L
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK                                              0x00030000L
>+#define MMEA7_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK                                               0x000C0000L
>+//MMEA7_ADDRNORMDRAM_GLOBAL_CNTL
>+#define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                         0x14
>+#define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                          0x15
>+#define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                          0x16
>+#define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                           0x00100000L
>+#define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                            0x00200000L
>+#define MMEA7_ADDRNORMDRAM_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                            0x00400000L
>+//MMEA7_ADDRNORMGMI_GLOBAL_CNTL
>+#define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K__SHIFT                                          0x14
>+#define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M__SHIFT                                           0x15
>+#define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G__SHIFT                                           0x16
>+#define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_64K_MASK                                            0x00100000L
>+#define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_2M_MASK                                             0x00200000L
>+#define MMEA7_ADDRNORMGMI_GLOBAL_CNTL__GLB_HASH_INTLV_CTL_1G_MASK                                             0x00400000L
>+//MMEA7_IO_RD_CLI2GRP_MAP0
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA7_IO_RD_CLI2GRP_MAP1
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA7_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA7_IO_WR_CLI2GRP_MAP0
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT                                                           0x0
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT                                                           0x2
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT                                                           0x4
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT                                                           0x6
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT                                                           0x8
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT                                                           0xa
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT                                                           0xc
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT                                                           0xe
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT                                                           0x10
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT                                                           0x12
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT                                                          0x14
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT                                                          0x16
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT                                                          0x18
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT                                                          0x1a
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT                                                          0x1c
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT                                                          0x1e
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK                                                             0x00000003L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK                                                             0x0000000CL
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK                                                             0x00000030L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK                                                             0x000000C0L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK                                                             0x00000300L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK                                                             0x00000C00L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK                                                             0x00003000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK                                                             0x0000C000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK                                                             0x00030000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK                                                             0x000C0000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK                                                            0x00300000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK                                                            0x00C00000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK                                                            0x03000000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK                                                            0x0C000000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK                                                            0x30000000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK                                                            0xC0000000L
>+//MMEA7_IO_WR_CLI2GRP_MAP1
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT                                                          0x0
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT                                                          0x2
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT                                                          0x4
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT                                                          0x6
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT                                                          0x8
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT                                                          0xa
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT                                                          0xc
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT                                                          0xe
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT                                                          0x10
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT                                                          0x12
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT                                                          0x14
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT                                                          0x16
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT                                                          0x18
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT                                                          0x1a
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT                                                          0x1c
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT                                                          0x1e
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK                                                            0x00000003L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK                                                            0x0000000CL
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK                                                            0x00000030L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK                                                            0x000000C0L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK                                                            0x00000300L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK                                                            0x00000C00L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK                                                            0x00003000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK                                                            0x0000C000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK                                                            0x00030000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK                                                            0x000C0000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK                                                            0x00300000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK                                                            0x00C00000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK                                                            0x03000000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK                                                            0x0C000000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK                                                            0x30000000L
>+#define MMEA7_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK                                                            0xC0000000L
>+//MMEA7_IO_RD_COMBINE_FLUSH
>+#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA7_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA7_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA7_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA7_IO_WR_COMBINE_FLUSH
>+#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT                                                        0x0
>+#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT                                                        0x4
>+#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT                                                        0x8
>+#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT                                                        0xc
>+#define MMEA7_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT                                                   0x10
>+#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK                                                          0x0000000FL
>+#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK                                                          0x000000F0L
>+#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK                                                          0x00000F00L
>+#define MMEA7_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK                                                          0x0000F000L
>+#define MMEA7_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK                                                     0x00010000L
>+//MMEA7_IO_GROUP_BURST
>+#define MMEA7_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT                                                              0x0
>+#define MMEA7_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT                                                              0x8
>+#define MMEA7_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT                                                              0x10
>+#define MMEA7_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT                                                              0x18
>+#define MMEA7_IO_GROUP_BURST__RD_LIMIT_LO_MASK                                                                0x000000FFL
>+#define MMEA7_IO_GROUP_BURST__RD_LIMIT_HI_MASK                                                                0x0000FF00L
>+#define MMEA7_IO_GROUP_BURST__WR_LIMIT_LO_MASK                                                                0x00FF0000L
>+#define MMEA7_IO_GROUP_BURST__WR_LIMIT_HI_MASK                                                                0xFF000000L
>+//MMEA7_IO_RD_PRI_AGE
>+#define MMEA7_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA7_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA7_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA7_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA7_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA7_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA7_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA7_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA7_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA7_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA7_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA7_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA7_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA7_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA7_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA7_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA7_IO_WR_PRI_AGE
>+#define MMEA7_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT                                                         0x0
>+#define MMEA7_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT                                                         0x3
>+#define MMEA7_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT                                                         0x6
>+#define MMEA7_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT                                                         0x9
>+#define MMEA7_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT                                                    0xc
>+#define MMEA7_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT                                                    0xf
>+#define MMEA7_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT                                                    0x12
>+#define MMEA7_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT                                                    0x15
>+#define MMEA7_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK                                                           0x00000007L
>+#define MMEA7_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK                                                           0x00000038L
>+#define MMEA7_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK                                                           0x000001C0L
>+#define MMEA7_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK                                                           0x00000E00L
>+#define MMEA7_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK                                                      0x00007000L
>+#define MMEA7_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK                                                      0x00038000L
>+#define MMEA7_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK                                                      0x001C0000L
>+#define MMEA7_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK                                                      0x00E00000L
>+//MMEA7_IO_RD_PRI_QUEUING
>+#define MMEA7_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA7_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA7_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA7_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA7_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA7_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA7_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA7_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA7_IO_WR_PRI_QUEUING
>+#define MMEA7_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA7_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA7_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA7_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA7_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA7_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA7_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA7_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK                                              0x00000E00L
>+//MMEA7_IO_RD_PRI_FIXED
>+#define MMEA7_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA7_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA7_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA7_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA7_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA7_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA7_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA7_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA7_IO_WR_PRI_FIXED
>+#define MMEA7_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT                                                0x0
>+#define MMEA7_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT                                                0x3
>+#define MMEA7_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT                                                0x6
>+#define MMEA7_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT                                                0x9
>+#define MMEA7_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK                                                  0x00000007L
>+#define MMEA7_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK                                                  0x00000038L
>+#define MMEA7_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK                                                  0x000001C0L
>+#define MMEA7_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK                                                  0x00000E00L
>+//MMEA7_IO_RD_PRI_URGENCY
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA7_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA7_IO_WR_PRI_URGENCY
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT                                            0x0
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT                                            0x3
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT                                            0x6
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT                                            0x9
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT                                                   0xc
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT                                                   0xd
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT                                                   0xe
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT                                                   0xf
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK                                              0x00000007L
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK                                              0x00000038L
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK                                              0x000001C0L
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK                                              0x00000E00L
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK                                                     0x00001000L
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK                                                     0x00002000L
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK                                                     0x00004000L
>+#define MMEA7_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK                                                     0x00008000L
>+//MMEA7_IO_RD_PRI_URGENCY_MASKING
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA7_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA7_IO_WR_PRI_URGENCY_MASKING
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT                                                     0x0
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT                                                     0x1
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT                                                     0x2
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT                                                     0x3
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT                                                     0x4
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT                                                     0x5
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT                                                     0x6
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT                                                     0x7
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT                                                     0x8
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT                                                     0x9
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT                                                    0xa
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT                                                    0xb
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT                                                    0xc
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT                                                    0xd
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT                                                    0xe
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT                                                    0xf
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT                                                    0x10
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT                                                    0x11
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT                                                    0x12
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT                                                    0x13
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT                                                    0x14
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT                                                    0x15
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT                                                    0x16
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT                                                    0x17
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT                                                    0x18
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT                                                    0x19
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT                                                    0x1a
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT                                                    0x1b
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT                                                    0x1c
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT                                                    0x1d
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT                                                    0x1e
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT                                                    0x1f
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK                                                       0x00000001L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK                                                       0x00000002L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK                                                       0x00000004L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK                                                       0x00000008L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK                                                       0x00000010L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK                                                       0x00000020L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK                                                       0x00000040L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK                                                       0x00000080L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK                                                       0x00000100L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK                                                       0x00000200L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK                                                      0x00000400L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK                                                      0x00000800L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK                                                      0x00001000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK                                                      0x00002000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK                                                      0x00004000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK                                                      0x00008000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK                                                      0x00010000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK                                                      0x00020000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK                                                      0x00040000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK                                                      0x00080000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK                                                      0x00100000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK                                                      0x00200000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK                                                      0x00400000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK                                                      0x00800000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK                                                      0x01000000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK                                                      0x02000000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK                                                      0x04000000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK                                                      0x08000000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK                                                      0x10000000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK                                                      0x20000000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK                                                      0x40000000L
>+#define MMEA7_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK                                                      0x80000000L
>+//MMEA7_IO_RD_PRI_QUANT_PRI1
>+#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA7_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA7_IO_RD_PRI_QUANT_PRI2
>+#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA7_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA7_IO_RD_PRI_QUANT_PRI3
>+#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA7_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA7_IO_WR_PRI_QUANT_PRI1
>+#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA7_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA7_IO_WR_PRI_QUANT_PRI2
>+#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA7_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA7_IO_WR_PRI_QUANT_PRI3
>+#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT                                                   0x0
>+#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT                                                   0x8
>+#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT                                                   0x10
>+#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT                                                   0x18
>+#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK                                                     0x000000FFL
>+#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK                                                     0x0000FF00L
>+#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK                                                     0x00FF0000L
>+#define MMEA7_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK                                                     0xFF000000L
>+//MMEA7_SDP_ARB_DRAM
>+#define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT                                                      0x0
>+#define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT                                                      0x8
>+#define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT                                                         0x10
>+#define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT                                                         0x11
>+#define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT                                                         0x12
>+#define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT                                                         0x13
>+#define MMEA7_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT                                                              0x14
>+#define MMEA7_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                     0x15
>+#define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK                                                        0x0000007FL
>+#define MMEA7_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK                                                        0x00007F00L
>+#define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK                                                           0x00010000L
>+#define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK                                                           0x00020000L
>+#define MMEA7_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK                                                           0x00040000L
>+#define MMEA7_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK                                                           0x00080000L
>+#define MMEA7_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK                                                                0x00100000L
>+#define MMEA7_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK                                                       0x00200000L
>+//MMEA7_SDP_ARB_GMI
>+#define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT                                                       0x0
>+#define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT                                                       0x8
>+#define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT                                                          0x10
>+#define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT                                                          0x11
>+#define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT                                                          0x12
>+#define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT                                                          0x13
>+#define MMEA7_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT                                                               0x14
>+#define MMEA7_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT                                                      0x15
>+#define MMEA7_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT                                                        0x16
>+#define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
>+#define MMEA7_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK                                                         0x00007F00L
>+#define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK                                                            0x00010000L
>+#define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK                                                            0x00020000L
>+#define MMEA7_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK                                                            0x00040000L
>+#define MMEA7_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK                                                            0x00080000L
>+#define MMEA7_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK                                                                 0x00100000L
>+#define MMEA7_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK                                                        0x00200000L
>+#define MMEA7_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK                                                          0x00400000L
>+//MMEA7_SDP_ARB_FINAL
>+#define MMEA7_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT                                                          0x0
>+#define MMEA7_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT                                                           0x5
>+#define MMEA7_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT                                                            0xa
>+#define MMEA7_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT                                                    0xf
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC0__SHIFT                                                                0x11
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC1__SHIFT                                                                0x12
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC2__SHIFT                                                                0x13
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC3__SHIFT                                                                0x14
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC4__SHIFT                                                                0x15
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC5__SHIFT                                                                0x16
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC6__SHIFT                                                                0x17
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC7__SHIFT                                                                0x18
>+#define MMEA7_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT                                                         0x19
>+#define MMEA7_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT                                                          0x1a
>+#define MMEA7_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT                                                         0x1b
>+#define MMEA7_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK                                                            0x0000001FL
>+#define MMEA7_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK                                                             0x000003E0L
>+#define MMEA7_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK                                                              0x00007C00L
>+#define MMEA7_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK                                                      0x00018000L
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC0_MASK                                                                  0x00020000L
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC1_MASK                                                                  0x00040000L
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC2_MASK                                                                  0x00080000L
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC3_MASK                                                                  0x00100000L
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC4_MASK                                                                  0x00200000L
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC5_MASK                                                                  0x00400000L
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC6_MASK                                                                  0x00800000L
>+#define MMEA7_SDP_ARB_FINAL__RDONLY_VC7_MASK                                                                  0x01000000L
>+#define MMEA7_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK                                                           0x02000000L
>+#define MMEA7_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK                                                            0x04000000L
>+#define MMEA7_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK                                                           0x08000000L
>+//MMEA7_SDP_DRAM_PRIORITY
>+#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                    0x0
>+#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                    0x4
>+#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                    0x8
>+#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                    0xc
>+#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                    0x10
>+#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                    0x14
>+#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                    0x18
>+#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                    0x1c
>+#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                      0x0000000FL
>+#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                      0x000000F0L
>+#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                      0x00000F00L
>+#define MMEA7_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                      0x0000F000L
>+#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                      0x000F0000L
>+#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                      0x00F00000L
>+#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                      0x0F000000L
>+#define MMEA7_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                      0xF0000000L
>+//MMEA7_SDP_GMI_PRIORITY
>+#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                     0x0
>+#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                     0x4
>+#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                     0x8
>+#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                     0xc
>+#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                     0x10
>+#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                     0x14
>+#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                     0x18
>+#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                     0x1c
>+#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                       0x0000000FL
>+#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                       0x000000F0L
>+#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                       0x00000F00L
>+#define MMEA7_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                       0x0000F000L
>+#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                       0x000F0000L
>+#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                       0x00F00000L
>+#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                       0x0F000000L
>+#define MMEA7_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                       0xF0000000L
>+//MMEA7_SDP_IO_PRIORITY
>+#define MMEA7_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT                                                      0x0
>+#define MMEA7_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT                                                      0x4
>+#define MMEA7_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT                                                      0x8
>+#define MMEA7_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT                                                      0xc
>+#define MMEA7_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT                                                      0x10
>+#define MMEA7_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT                                                      0x14
>+#define MMEA7_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT                                                      0x18
>+#define MMEA7_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT                                                      0x1c
>+#define MMEA7_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK                                                        0x0000000FL
>+#define MMEA7_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK                                                        0x000000F0L
>+#define MMEA7_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK                                                        0x00000F00L
>+#define MMEA7_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK                                                        0x0000F000L
>+#define MMEA7_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK                                                        0x000F0000L
>+#define MMEA7_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK                                                        0x00F00000L
>+#define MMEA7_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK                                                        0x0F000000L
>+#define MMEA7_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK                                                        0xF0000000L
>+//MMEA7_SDP_CREDITS
>+#define MMEA7_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
>+#define MMEA7_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
>+#define MMEA7_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
>+#define MMEA7_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
>+#define MMEA7_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
>+#define MMEA7_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x007F0000L
>+//MMEA7_SDP_TAG_RESERVE0
>+#define MMEA7_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
>+#define MMEA7_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
>+#define MMEA7_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
>+#define MMEA7_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
>+#define MMEA7_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
>+#define MMEA7_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
>+#define MMEA7_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
>+#define MMEA7_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
>+//MMEA7_SDP_TAG_RESERVE1
>+#define MMEA7_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
>+#define MMEA7_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
>+#define MMEA7_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
>+#define MMEA7_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
>+#define MMEA7_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
>+#define MMEA7_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
>+#define MMEA7_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
>+#define MMEA7_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
>+//MMEA7_SDP_VCC_RESERVE0
>+#define MMEA7_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA7_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA7_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA7_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA7_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA7_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA7_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA7_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA7_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA7_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA7_SDP_VCC_RESERVE1
>+#define MMEA7_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA7_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA7_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA7_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA7_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA7_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA7_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA7_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA7_SDP_VCD_RESERVE0
>+#define MMEA7_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
>+#define MMEA7_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
>+#define MMEA7_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
>+#define MMEA7_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
>+#define MMEA7_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
>+#define MMEA7_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA7_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA7_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA7_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
>+#define MMEA7_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
>+//MMEA7_SDP_VCD_RESERVE1
>+#define MMEA7_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
>+#define MMEA7_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
>+#define MMEA7_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
>+#define MMEA7_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
>+#define MMEA7_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
>+#define MMEA7_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
>+#define MMEA7_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
>+#define MMEA7_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
>+//MMEA7_SDP_REQ_CNTL
>+#define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
>+#define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
>+#define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
>+#define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
>+#define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
>+#define MMEA7_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
>+#define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
>+#define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
>+#define MMEA7_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
>+#define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
>+#define MMEA7_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
>+#define MMEA7_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
>+//MMEA7_MISC
>+#define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT                                                        0x0
>+#define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT                                                        0x1
>+#define MMEA7_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT                                                         0x2
>+#define MMEA7_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT                                                         0x3
>+#define MMEA7_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT                                                          0x4
>+#define MMEA7_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT                                                          0x5
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                              0x6
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                              0x7
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                              0x8
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                              0x9
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                              0xa
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                              0xb
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                              0xc
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                              0xd
>+#define MMEA7_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                                 0xe
>+#define MMEA7_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                               0xf
>+#define MMEA7_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                             0x11
>+#define MMEA7_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                            0x13
>+#define MMEA7_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                             0x15
>+#define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT                                                     0x1a
>+#define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT                                                      0x1b
>+#define MMEA7_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT                                                         0x1c
>+#define MMEA7_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT                                                          0x1d
>+#define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT                                                       0x1e
>+#define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT                                                        0x1f
>+#define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK                                                          0x00000001L
>+#define MMEA7_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK                                                          0x00000002L
>+#define MMEA7_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK                                                           0x00000004L
>+#define MMEA7_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK                                                           0x00000008L
>+#define MMEA7_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK                                                            0x00000010L
>+#define MMEA7_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK                                                            0x00000020L
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                                0x00000040L
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                                0x00000080L
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                                0x00000100L
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                                0x00000200L
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                                0x00000400L
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                                0x00000800L
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                                0x00001000L
>+#define MMEA7_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                                0x00002000L
>+#define MMEA7_MISC__EARLY_SDP_ORIGDATA_MASK                                                                   0x00004000L
>+#define MMEA7_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                                 0x00018000L
>+#define MMEA7_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                               0x00060000L
>+#define MMEA7_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                              0x00180000L
>+#define MMEA7_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                               0x03E00000L
>+#define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK                                                       0x04000000L
>+#define MMEA7_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK                                                        0x08000000L
>+#define MMEA7_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK                                                           0x10000000L
>+#define MMEA7_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK                                                            0x20000000L
>+#define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK                                                         0x40000000L
>+#define MMEA7_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK                                                          0x80000000L
>+//MMEA7_LATENCY_SAMPLING
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                          0x0
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                          0x1
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                           0x2
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                           0x3
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                            0x4
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                            0x5
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                          0x6
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                          0x7
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                         0x8
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                         0x9
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                    0xa
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                    0xb
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                                  0xc
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                                  0xd
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                            0xe
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                            0x16
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                            0x00000001L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                            0x00000002L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                             0x00000004L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                             0x00000008L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                              0x00000010L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                              0x00000020L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                            0x00000040L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                            0x00000080L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                           0x00000100L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                           0x00000200L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                      0x00000400L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                      0x00000800L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                    0x00001000L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                    0x00002000L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                              0x003FC000L
>+#define MMEA7_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                              0x3FC00000L
>+//MMEA7_PERFCOUNTER_LO
>+#define MMEA7_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
>+#define MMEA7_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
>+//MMEA7_PERFCOUNTER_HI
>+#define MMEA7_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
>+#define MMEA7_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
>+#define MMEA7_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
>+#define MMEA7_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
>+//MMEA7_PERFCOUNTER0_CFG
>+#define MMEA7_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA7_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA7_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA7_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA7_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA7_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA7_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA7_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA7_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA7_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA7_PERFCOUNTER1_CFG
>+#define MMEA7_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
>+#define MMEA7_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
>+#define MMEA7_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
>+#define MMEA7_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
>+#define MMEA7_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
>+#define MMEA7_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
>+#define MMEA7_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
>+#define MMEA7_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
>+#define MMEA7_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
>+#define MMEA7_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
>+//MMEA7_PERFCOUNTER_RSLT_CNTL
>+#define MMEA7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
>+#define MMEA7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
>+#define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
>+#define MMEA7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
>+#define MMEA7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
>+#define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
>+#define MMEA7_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x0000000FL
>+#define MMEA7_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
>+#define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
>+#define MMEA7_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
>+#define MMEA7_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
>+#define MMEA7_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
>+//MMEA7_EDC_CNT
>+#define MMEA7_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA7_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA7_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA7_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA7_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA7_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA7_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT                                                           0xc
>+#define MMEA7_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT                                                           0xe
>+#define MMEA7_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT                                                           0x10
>+#define MMEA7_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT                                                           0x12
>+#define MMEA7_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT                                                        0x14
>+#define MMEA7_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT                                                        0x16
>+#define MMEA7_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT                                                           0x18
>+#define MMEA7_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT                                                           0x1a
>+#define MMEA7_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT                                                          0x1c
>+#define MMEA7_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA7_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA7_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA7_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA7_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA7_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA7_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK                                                             0x00003000L
>+#define MMEA7_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK                                                             0x0000C000L
>+#define MMEA7_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK                                                             0x00030000L
>+#define MMEA7_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK                                                             0x000C0000L
>+#define MMEA7_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK                                                          0x00300000L
>+#define MMEA7_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK                                                          0x00C00000L
>+#define MMEA7_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK                                                             0x03000000L
>+#define MMEA7_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK                                                             0x0C000000L
>+#define MMEA7_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK                                                            0x30000000L
>+//MMEA7_EDC_CNT2
>+#define MMEA7_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT                                                         0x0
>+#define MMEA7_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT                                                         0x2
>+#define MMEA7_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT                                                         0x4
>+#define MMEA7_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT                                                         0x6
>+#define MMEA7_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT                                                        0x8
>+#define MMEA7_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA7_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT                                                        0xc
>+#define MMEA7_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT                                                        0xe
>+#define MMEA7_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK                                                           0x00000003L
>+#define MMEA7_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK                                                           0x0000000CL
>+#define MMEA7_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK                                                           0x00000030L
>+#define MMEA7_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK                                                           0x000000C0L
>+#define MMEA7_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK                                                          0x00000300L
>+#define MMEA7_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA7_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK                                                          0x00003000L
>+#define MMEA7_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK                                                          0x0000C000L
>+//MMEA7_DSM_CNTL
>+#define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x0
>+#define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x2
>+#define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x3
>+#define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x5
>+#define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x6
>+#define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x8
>+#define MMEA7_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0x9
>+#define MMEA7_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xb
>+#define MMEA7_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT                                                 0xc
>+#define MMEA7_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT                                                0xe
>+#define MMEA7_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0xf
>+#define MMEA7_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x11
>+#define MMEA7_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x12
>+#define MMEA7_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x14
>+#define MMEA7_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0x15
>+#define MMEA7_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0x17
>+#define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000003L
>+#define MMEA7_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000004L
>+#define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00000018L
>+#define MMEA7_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00000020L
>+#define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                0x000000C0L
>+#define MMEA7_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00000100L
>+#define MMEA7_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00000600L
>+#define MMEA7_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00000800L
>+#define MMEA7_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK                                                   0x00003000L
>+#define MMEA7_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK                                                  0x00004000L
>+#define MMEA7_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00018000L
>+#define MMEA7_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00020000L
>+#define MMEA7_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000C0000L
>+#define MMEA7_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00100000L
>+#define MMEA7_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00600000L
>+#define MMEA7_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00800000L
>+//MMEA7_DSM_CNTLA
>+#define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x0
>+#define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x2
>+#define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                             0x3
>+#define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                            0x5
>+#define MMEA7_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x6
>+#define MMEA7_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0x8
>+#define MMEA7_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT                                                0x9
>+#define MMEA7_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT                                               0xb
>+#define MMEA7_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT                                               0xc
>+#define MMEA7_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT                                              0xe
>+#define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0xf
>+#define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x11
>+#define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT                                              0x12
>+#define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT                                             0x14
>+#define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000003L
>+#define MMEA7_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000004L
>+#define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                               0x00000018L
>+#define MMEA7_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                              0x00000020L
>+#define MMEA7_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x000000C0L
>+#define MMEA7_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000100L
>+#define MMEA7_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK                                                  0x00000600L
>+#define MMEA7_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK                                                 0x00000800L
>+#define MMEA7_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK                                                 0x00003000L
>+#define MMEA7_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK                                                0x00004000L
>+#define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x00018000L
>+#define MMEA7_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00020000L
>+#define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK                                                0x000C0000L
>+#define MMEA7_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK                                               0x00100000L
>+//MMEA7_DSM_CNTL2
>+#define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x0
>+#define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x2
>+#define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x3
>+#define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                             0x5
>+#define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x6
>+#define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                            0x8
>+#define MMEA7_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0x9
>+#define MMEA7_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xb
>+#define MMEA7_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT                                               0xc
>+#define MMEA7_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT                                               0xe
>+#define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0xf
>+#define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x11
>+#define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x12
>+#define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x14
>+#define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0x15
>+#define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0x17
>+#define MMEA7_DSM_CNTL2__INJECT_DELAY__SHIFT                                                                  0x1a
>+#define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000003L
>+#define MMEA7_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000004L
>+#define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                               0x00000018L
>+#define MMEA7_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                               0x00000020L
>+#define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                              0x000000C0L
>+#define MMEA7_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                              0x00000100L
>+#define MMEA7_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00000600L
>+#define MMEA7_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00000800L
>+#define MMEA7_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK                                                 0x00003000L
>+#define MMEA7_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK                                                 0x00004000L
>+#define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00018000L
>+#define MMEA7_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00020000L
>+#define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000C0000L
>+#define MMEA7_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00100000L
>+#define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00600000L
>+#define MMEA7_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00800000L
>+#define MMEA7_DSM_CNTL2__INJECT_DELAY_MASK                                                                    0xFC000000L
>+//MMEA7_DSM_CNTL2A
>+#define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x0
>+#define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x2
>+#define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                           0x3
>+#define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                           0x5
>+#define MMEA7_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x6
>+#define MMEA7_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0x8
>+#define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT                                              0x9
>+#define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT                                              0xb
>+#define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT                                             0xc
>+#define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT                                             0xe
>+#define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0xf
>+#define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x11
>+#define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT                                            0x12
>+#define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT                                            0x14
>+#define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000003L
>+#define MMEA7_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000004L
>+#define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                             0x00000018L
>+#define MMEA7_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                             0x00000020L
>+#define MMEA7_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x000000C0L
>+#define MMEA7_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000100L
>+#define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK                                                0x00000600L
>+#define MMEA7_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK                                                0x00000800L
>+#define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK                                               0x00003000L
>+#define MMEA7_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK                                               0x00004000L
>+#define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x00018000L
>+#define MMEA7_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00020000L
>+#define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK                                              0x000C0000L
>+#define MMEA7_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK                                              0x00100000L
>+//MMEA7_CGTT_CLK_CTRL
>+#define MMEA7_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                  0x0
>+#define MMEA7_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                            0x4
>+#define MMEA7_CGTT_CLK_CTRL__SPARE0__SHIFT                                                                    0xc
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT                                                 0x14
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT                                                  0x15
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT                                                0x16
>+#define MMEA7_CGTT_CLK_CTRL__SPARE1__SHIFT                                                                    0x17
>+#define MMEA7_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT                                                               0x1b
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT                                                       0x1c
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT                                                        0x1d
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT                                                      0x1e
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT                                                    0x1f
>+#define MMEA7_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                    0x0000000FL
>+#define MMEA7_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                              0x00000FF0L
>+#define MMEA7_CGTT_CLK_CTRL__SPARE0_MASK                                                                      0x000FF000L
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK                                                   0x00100000L
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK                                                    0x00200000L
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK                                                  0x00400000L
>+#define MMEA7_CGTT_CLK_CTRL__SPARE1_MASK                                                                      0x07800000L
>+#define MMEA7_CGTT_CLK_CTRL__LS_OVERRIDE_MASK                                                                 0x08000000L
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK                                                         0x10000000L
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK                                                          0x20000000L
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK                                                        0x40000000L
>+#define MMEA7_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK                                                      0x80000000L
>+//MMEA7_EDC_MODE
>+#define MMEA7_EDC_MODE__COUNT_FED_OUT__SHIFT                                                                  0x10
>+#define MMEA7_EDC_MODE__GATE_FUE__SHIFT                                                                       0x11
>+#define MMEA7_EDC_MODE__DED_MODE__SHIFT                                                                       0x14
>+#define MMEA7_EDC_MODE__PROP_FED__SHIFT                                                                       0x1d
>+#define MMEA7_EDC_MODE__BYPASS__SHIFT                                                                         0x1f
>+#define MMEA7_EDC_MODE__COUNT_FED_OUT_MASK                                                                    0x00010000L
>+#define MMEA7_EDC_MODE__GATE_FUE_MASK                                                                         0x00020000L
>+#define MMEA7_EDC_MODE__DED_MODE_MASK                                                                         0x00300000L
>+#define MMEA7_EDC_MODE__PROP_FED_MASK                                                                         0x20000000L
>+#define MMEA7_EDC_MODE__BYPASS_MASK                                                                           0x80000000L
>+//MMEA7_ERR_STATUS
>+#define MMEA7_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                             0x0
>+#define MMEA7_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                             0x4
>+#define MMEA7_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                         0x8
>+#define MMEA7_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                                   0xa
>+#define MMEA7_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                           0xb
>+#define MMEA7_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                                0xc
>+#define MMEA7_ERR_STATUS__FUE_FLAG__SHIFT                                                                     0xd
>+#define MMEA7_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                               0x0000000FL
>+#define MMEA7_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                               0x000000F0L
>+#define MMEA7_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                           0x00000300L
>+#define MMEA7_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                     0x00000400L
>+#define MMEA7_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                             0x00000800L
>+#define MMEA7_ERR_STATUS__BUSY_ON_ERROR_MASK                                                                  0x00001000L
>+#define MMEA7_ERR_STATUS__FUE_FLAG_MASK                                                                       0x00002000L
>+//MMEA7_MISC2
>+#define MMEA7_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT                                                          0x0
>+#define MMEA7_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT                                                           0x1
>+#define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT                                                       0x2
>+#define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT                                                        0x7
>+#define MMEA7_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT                                                           0xc
>+#define MMEA7_MISC2__RRET_SWAP_MODE__SHIFT                                                                    0xd
>+#define MMEA7_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK                                                            0x00000001L
>+#define MMEA7_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK                                                             0x00000002L
>+#define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK                                                         0x0000007CL
>+#define MMEA7_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK                                                          0x00000F80L
>+#define MMEA7_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK                                                             0x00001000L
>+#define MMEA7_MISC2__RRET_SWAP_MODE_MASK                                                                      0x00002000L
>+//MMEA7_ADDRDEC_SELECT
>+#define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT                                               0x0
>+#define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT                                                 0x5
>+#define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT                                                0xa
>+#define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT                                                  0xf
>+#define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK                                                 0x0000001FL
>+#define MMEA7_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK                                                   0x000003E0L
>+#define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK                                                  0x00007C00L
>+#define MMEA7_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK                                                    0x000F8000L
>+//MMEA7_EDC_CNT3
>+#define MMEA7_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT                                                       0x0
>+#define MMEA7_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT                                                       0x2
>+#define MMEA7_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT                                                          0x4
>+#define MMEA7_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT                                                          0x6
>+#define MMEA7_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT                                                         0x8
>+#define MMEA7_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT                                                        0xa
>+#define MMEA7_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT                                                        0xc
>+#define MMEA7_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK                                                         0x00000003L
>+#define MMEA7_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK                                                         0x0000000CL
>+#define MMEA7_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK                                                            0x00000030L
>+#define MMEA7_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK                                                            0x000000C0L
>+#define MMEA7_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK                                                           0x00000300L
>+#define MMEA7_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK                                                          0x00000C00L
>+#define MMEA7_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK                                                          0x00003000L
>+
>+
>+// addressBlock: mmhub_pctldec1
>+//PCTL1_CTRL
>+#define PCTL1_CTRL__PG_ENABLE__SHIFT                                                                          0x0
>+#define PCTL1_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT                                                              0x1
>+#define PCTL1_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT                                                         0x4
>+#define PCTL1_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT                                                         0xb
>+#define PCTL1_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT                                                     0x10
>+#define PCTL1_CTRL__OVR_EA0_SDP_PARTACK__SHIFT                                                                0x11
>+#define PCTL1_CTRL__OVR_EA1_SDP_PARTACK__SHIFT                                                                0x12
>+#define PCTL1_CTRL__OVR_EA2_SDP_PARTACK__SHIFT                                                                0x13
>+#define PCTL1_CTRL__OVR_EA3_SDP_PARTACK__SHIFT                                                                0x14
>+#define PCTL1_CTRL__OVR_EA4_SDP_PARTACK__SHIFT                                                                0x15
>+#define PCTL1_CTRL__OVR_EA0_SDP_FULLACK__SHIFT                                                                0x16
>+#define PCTL1_CTRL__OVR_EA1_SDP_FULLACK__SHIFT                                                                0x17
>+#define PCTL1_CTRL__OVR_EA2_SDP_FULLACK__SHIFT                                                                0x18
>+#define PCTL1_CTRL__OVR_EA3_SDP_FULLACK__SHIFT                                                                0x19
>+#define PCTL1_CTRL__OVR_EA4_SDP_FULLACK__SHIFT                                                                0x1a
>+#define PCTL1_CTRL__PGFSM_CMD_STATUS__SHIFT                                                                   0x1b
>+#define PCTL1_CTRL__PG_ENABLE_MASK                                                                            0x00000001L
>+#define PCTL1_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK                                                                0x0000000EL
>+#define PCTL1_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK                                                           0x000007F0L
>+#define PCTL1_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK                                                           0x0000F800L
>+#define PCTL1_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK                                                       0x00010000L
>+#define PCTL1_CTRL__OVR_EA0_SDP_PARTACK_MASK                                                                  0x00020000L
>+#define PCTL1_CTRL__OVR_EA1_SDP_PARTACK_MASK                                                                  0x00040000L
>+#define PCTL1_CTRL__OVR_EA2_SDP_PARTACK_MASK                                                                  0x00080000L
>+#define PCTL1_CTRL__OVR_EA3_SDP_PARTACK_MASK                                                                  0x00100000L
>+#define PCTL1_CTRL__OVR_EA4_SDP_PARTACK_MASK                                                                  0x00200000L
>+#define PCTL1_CTRL__OVR_EA0_SDP_FULLACK_MASK                                                                  0x00400000L
>+#define PCTL1_CTRL__OVR_EA1_SDP_FULLACK_MASK                                                                  0x00800000L
>+#define PCTL1_CTRL__OVR_EA2_SDP_FULLACK_MASK                                                                  0x01000000L
>+#define PCTL1_CTRL__OVR_EA3_SDP_FULLACK_MASK                                                                  0x02000000L
>+#define PCTL1_CTRL__OVR_EA4_SDP_FULLACK_MASK                                                                  0x04000000L
>+#define PCTL1_CTRL__PGFSM_CMD_STATUS_MASK                                                                     0x18000000L
>+//PCTL1_MMHUB_DEEPSLEEP_IB
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS0__SHIFT                                                                  0x0
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS1__SHIFT                                                                  0x1
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS2__SHIFT                                                                  0x2
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS3__SHIFT                                                                  0x3
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS4__SHIFT                                                                  0x4
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS5__SHIFT                                                                  0x5
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS6__SHIFT                                                                  0x6
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS7__SHIFT                                                                  0x7
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS8__SHIFT                                                                  0x8
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS9__SHIFT                                                                  0x9
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS10__SHIFT                                                                 0xa
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS11__SHIFT                                                                 0xb
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS12__SHIFT                                                                 0xc
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS13__SHIFT                                                                 0xd
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS14__SHIFT                                                                 0xe
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS15__SHIFT                                                                 0xf
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS16__SHIFT                                                                 0x10
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT                                                             0x1f
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS0_MASK                                                                    0x00000001L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS1_MASK                                                                    0x00000002L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS2_MASK                                                                    0x00000004L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS3_MASK                                                                    0x00000008L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS4_MASK                                                                    0x00000010L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS5_MASK                                                                    0x00000020L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS6_MASK                                                                    0x00000040L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS7_MASK                                                                    0x00000080L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS8_MASK                                                                    0x00000100L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS9_MASK                                                                    0x00000200L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS10_MASK                                                                   0x00000400L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS11_MASK                                                                   0x00000800L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS12_MASK                                                                   0x00001000L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS13_MASK                                                                   0x00002000L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS14_MASK                                                                   0x00004000L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS15_MASK                                                                   0x00008000L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__DS16_MASK                                                                   0x00010000L
>+#define PCTL1_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK                                                               0x80000000L
>+//PCTL1_MMHUB_DEEPSLEEP_OVERRIDE
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT                                                            0x0
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT                                                            0x1
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT                                                            0x2
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT                                                            0x3
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT                                                            0x4
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT                                                            0x5
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT                                                            0x6
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT                                                            0x7
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT                                                            0x8
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT                                                            0x9
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT                                                           0xa
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT                                                           0xb
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT                                                           0xc
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT                                                           0xd
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT                                                           0xe
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT                                                           0xf
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT                                                           0x10
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT                                                       0x11
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK                                                              0x00000001L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK                                                              0x00000002L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK                                                              0x00000004L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK                                                              0x00000008L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK                                                              0x00000010L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK                                                              0x00000020L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK                                                              0x00000040L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK                                                              0x00000080L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK                                                              0x00000100L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK                                                              0x00000200L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK                                                             0x00000400L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK                                                             0x00000800L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK                                                             0x00001000L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK                                                             0x00002000L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK                                                             0x00004000L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK                                                             0x00008000L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK                                                             0x00010000L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK                                                         0x00020000L
>+//PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT                                                         0x0
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT                                                         0x1
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT                                                         0x2
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT                                                         0x3
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT                                                         0x4
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT                                                         0x5
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT                                                         0x6
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT                                                         0x7
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT                                                         0x8
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT                                                         0x9
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT                                                        0xa
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT                                                        0xb
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT                                                        0xc
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT                                                        0xd
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT                                                        0xe
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT                                                        0xf
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT                                                        0x10
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK                                                           0x00000001L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK                                                           0x00000002L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK                                                           0x00000004L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK                                                           0x00000008L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK                                                           0x00000010L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK                                                           0x00000020L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK                                                           0x00000040L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK                                                           0x00000080L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK                                                           0x00000100L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK                                                           0x00000200L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK                                                          0x00000400L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK                                                          0x00000800L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK                                                          0x00001000L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK                                                          0x00002000L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK                                                          0x00004000L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK                                                          0x00008000L
>+#define PCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK                                                          0x00010000L
>+//PCTL1_PG_IGNORE_DEEPSLEEP
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS0__SHIFT                                                                 0x0
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS1__SHIFT                                                                 0x1
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS2__SHIFT                                                                 0x2
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS3__SHIFT                                                                 0x3
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS4__SHIFT                                                                 0x4
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS5__SHIFT                                                                 0x5
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS6__SHIFT                                                                 0x6
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS7__SHIFT                                                                 0x7
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS8__SHIFT                                                                 0x8
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS9__SHIFT                                                                 0x9
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS10__SHIFT                                                                0xa
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS11__SHIFT                                                                0xb
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS12__SHIFT                                                                0xc
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS13__SHIFT                                                                0xd
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS14__SHIFT                                                                0xe
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS15__SHIFT                                                                0xf
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS16__SHIFT                                                                0x10
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT                                                            0x11
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT                                                              0x12
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS0_MASK                                                                   0x00000001L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS1_MASK                                                                   0x00000002L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS2_MASK                                                                   0x00000004L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS3_MASK                                                                   0x00000008L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS4_MASK                                                                   0x00000010L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS5_MASK                                                                   0x00000020L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS6_MASK                                                                   0x00000040L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS7_MASK                                                                   0x00000080L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS8_MASK                                                                   0x00000100L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS9_MASK                                                                   0x00000200L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS10_MASK                                                                  0x00000400L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS11_MASK                                                                  0x00000800L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS12_MASK                                                                  0x00001000L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS13_MASK                                                                  0x00002000L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS14_MASK                                                                  0x00004000L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS15_MASK                                                                  0x00008000L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS16_MASK                                                                  0x00010000L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK                                                              0x00020000L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK                                                                0x00040000L
>+//PCTL1_PG_IGNORE_DEEPSLEEP_IB
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT                                                              0x0
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT                                                              0x1
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT                                                              0x2
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT                                                              0x3
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT                                                              0x4
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT                                                              0x5
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT                                                              0x6
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT                                                              0x7
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT                                                              0x8
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT                                                              0x9
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT                                                             0xa
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT                                                             0xb
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT                                                             0xc
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT                                                             0xd
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT                                                             0xe
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT                                                             0xf
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT                                                             0x10
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT                                                           0x11
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK                                                                0x00000001L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK                                                                0x00000002L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK                                                                0x00000004L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK                                                                0x00000008L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK                                                                0x00000010L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK                                                                0x00000020L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK                                                                0x00000040L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK                                                                0x00000080L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK                                                                0x00000100L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK                                                                0x00000200L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK                                                               0x00000400L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK                                                               0x00000800L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK                                                               0x00001000L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK                                                               0x00002000L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK                                                               0x00004000L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK                                                               0x00008000L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK                                                               0x00010000L
>+#define PCTL1_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK                                                             0x00020000L
>+//PCTL1_SLICE0_CFG_DAGB_BUSY
>+#define PCTL1_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
>+#define PCTL1_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
>+//PCTL1_SLICE0_CFG_DS_ALLOW
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
>+//PCTL1_SLICE0_CFG_DS_ALLOW_IB
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
>+#define PCTL1_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
>+//PCTL1_SLICE1_CFG_DAGB_BUSY
>+#define PCTL1_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
>+#define PCTL1_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
>+//PCTL1_SLICE1_CFG_DS_ALLOW
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
>+//PCTL1_SLICE1_CFG_DS_ALLOW_IB
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
>+#define PCTL1_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
>+//PCTL1_SLICE2_CFG_DAGB_BUSY
>+#define PCTL1_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
>+#define PCTL1_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
>+//PCTL1_SLICE2_CFG_DS_ALLOW
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
>+//PCTL1_SLICE2_CFG_DS_ALLOW_IB
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
>+#define PCTL1_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
>+//PCTL1_SLICE3_CFG_DAGB_BUSY
>+#define PCTL1_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
>+#define PCTL1_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
>+//PCTL1_SLICE3_CFG_DS_ALLOW
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
>+//PCTL1_SLICE3_CFG_DS_ALLOW_IB
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
>+#define PCTL1_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
>+//PCTL1_SLICE4_CFG_DAGB_BUSY
>+#define PCTL1_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT                                                           0x0
>+#define PCTL1_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK                                                             0xFFFFFFFFL
>+//PCTL1_SLICE4_CFG_DS_ALLOW
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS0__SHIFT                                                                 0x0
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS1__SHIFT                                                                 0x1
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS2__SHIFT                                                                 0x2
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS3__SHIFT                                                                 0x3
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS4__SHIFT                                                                 0x4
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS5__SHIFT                                                                 0x5
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS6__SHIFT                                                                 0x6
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS7__SHIFT                                                                 0x7
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS8__SHIFT                                                                 0x8
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS9__SHIFT                                                                 0x9
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS10__SHIFT                                                                0xa
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS11__SHIFT                                                                0xb
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS12__SHIFT                                                                0xc
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS13__SHIFT                                                                0xd
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS14__SHIFT                                                                0xe
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS15__SHIFT                                                                0xf
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS16__SHIFT                                                                0x10
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS0_MASK                                                                   0x00000001L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS1_MASK                                                                   0x00000002L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS2_MASK                                                                   0x00000004L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS3_MASK                                                                   0x00000008L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS4_MASK                                                                   0x00000010L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS5_MASK                                                                   0x00000020L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS6_MASK                                                                   0x00000040L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS7_MASK                                                                   0x00000080L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS8_MASK                                                                   0x00000100L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS9_MASK                                                                   0x00000200L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS10_MASK                                                                  0x00000400L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS11_MASK                                                                  0x00000800L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS12_MASK                                                                  0x00001000L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS13_MASK                                                                  0x00002000L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS14_MASK                                                                  0x00004000L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS15_MASK                                                                  0x00008000L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW__DS16_MASK                                                                  0x00010000L
>+//PCTL1_SLICE4_CFG_DS_ALLOW_IB
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT                                                              0x0
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT                                                              0x1
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT                                                              0x2
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT                                                              0x3
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT                                                              0x4
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT                                                              0x5
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT                                                              0x6
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT                                                              0x7
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT                                                              0x8
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT                                                              0x9
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT                                                             0xa
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT                                                             0xb
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT                                                             0xc
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT                                                             0xd
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT                                                             0xe
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT                                                             0xf
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT                                                             0x10
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK                                                                0x00000001L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK                                                                0x00000002L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK                                                                0x00000004L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK                                                                0x00000008L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK                                                                0x00000010L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK                                                                0x00000020L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK                                                                0x00000040L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK                                                                0x00000080L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK                                                                0x00000100L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK                                                                0x00000200L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK                                                               0x00000400L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK                                                               0x00000800L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK                                                               0x00001000L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK                                                               0x00002000L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK                                                               0x00004000L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK                                                               0x00008000L
>+#define PCTL1_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK                                                               0x00010000L
>+//PCTL1_UTCL2_MISC
>+#define PCTL1_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                           0xb
>+#define PCTL1_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                          0xc
>+#define PCTL1_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                           0xf
>+#define PCTL1_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                  0x10
>+#define PCTL1_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                   0x11
>+#define PCTL1_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT                                                              0x12
>+#define PCTL1_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK                                                             0x00000800L
>+#define PCTL1_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK                                                            0x00007000L
>+#define PCTL1_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK                                                             0x00008000L
>+#define PCTL1_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                    0x00010000L
>+#define PCTL1_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                     0x00020000L
>+#define PCTL1_UTCL2_MISC__RD_TIMER_ENABLE_MASK                                                                0x00040000L
>+//PCTL1_SLICE0_MISC
>+#define PCTL1_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
>+#define PCTL1_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
>+#define PCTL1_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
>+#define PCTL1_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
>+#define PCTL1_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
>+#define PCTL1_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
>+#define PCTL1_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
>+#define PCTL1_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
>+#define PCTL1_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
>+#define PCTL1_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
>+#define PCTL1_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
>+#define PCTL1_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
>+#define PCTL1_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
>+#define PCTL1_SLICE0_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
>+//PCTL1_SLICE1_MISC
>+#define PCTL1_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
>+#define PCTL1_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
>+#define PCTL1_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
>+#define PCTL1_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
>+#define PCTL1_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
>+#define PCTL1_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
>+#define PCTL1_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
>+#define PCTL1_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
>+#define PCTL1_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
>+#define PCTL1_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
>+#define PCTL1_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
>+#define PCTL1_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
>+#define PCTL1_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
>+#define PCTL1_SLICE1_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
>+//PCTL1_SLICE2_MISC
>+#define PCTL1_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
>+#define PCTL1_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
>+#define PCTL1_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
>+#define PCTL1_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
>+#define PCTL1_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
>+#define PCTL1_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
>+#define PCTL1_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
>+#define PCTL1_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
>+#define PCTL1_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
>+#define PCTL1_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
>+#define PCTL1_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
>+#define PCTL1_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
>+#define PCTL1_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
>+#define PCTL1_SLICE2_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
>+//PCTL1_SLICE3_MISC
>+#define PCTL1_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
>+#define PCTL1_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
>+#define PCTL1_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
>+#define PCTL1_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
>+#define PCTL1_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
>+#define PCTL1_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
>+#define PCTL1_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
>+#define PCTL1_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
>+#define PCTL1_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
>+#define PCTL1_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
>+#define PCTL1_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
>+#define PCTL1_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
>+#define PCTL1_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
>+#define PCTL1_SLICE3_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
>+//PCTL1_SLICE4_MISC
>+#define PCTL1_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT                                                          0xa
>+#define PCTL1_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                         0xb
>+#define PCTL1_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                          0xe
>+#define PCTL1_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                 0xf
>+#define PCTL1_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                           0x10
>+#define PCTL1_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                  0x11
>+#define PCTL1_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT                                                             0x12
>+#define PCTL1_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK                                                            0x00000400L
>+#define PCTL1_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK                                                           0x00003800L
>+#define PCTL1_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK                                                            0x00004000L
>+#define PCTL1_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                   0x00008000L
>+#define PCTL1_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK                                                             0x00010000L
>+#define PCTL1_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                    0x00020000L
>+#define PCTL1_SLICE4_MISC__RD_TIMER_ENABLE_MASK                                                               0x00040000L
>+//PCTL1_UTCL2_RENG_EXECUTE
>+#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                     0x0
>+#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                0x1
>+#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                           0x2
>+#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                 0xd
>+#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                       0x00000001L
>+#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                  0x00000002L
>+#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                             0x00001FFCL
>+#define PCTL1_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                   0x00FFE000L
>+//PCTL1_SLICE0_RENG_EXECUTE
>+#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
>+#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
>+#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
>+#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
>+#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
>+#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
>+#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
>+#define PCTL1_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
>+//PCTL1_SLICE1_RENG_EXECUTE
>+#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
>+#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
>+#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
>+#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
>+#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
>+#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
>+#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
>+#define PCTL1_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
>+//PCTL1_SLICE2_RENG_EXECUTE
>+#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
>+#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
>+#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
>+#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
>+#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
>+#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
>+#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
>+#define PCTL1_SLICE2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
>+//PCTL1_SLICE3_RENG_EXECUTE
>+#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
>+#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
>+#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
>+#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
>+#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
>+#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
>+#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
>+#define PCTL1_SLICE3_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
>+//PCTL1_SLICE4_RENG_EXECUTE
>+#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                    0x0
>+#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                               0x1
>+#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                          0x2
>+#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                0xc
>+#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                      0x00000001L
>+#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                 0x00000002L
>+#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                            0x00000FFCL
>+#define PCTL1_SLICE4_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                  0x003FF000L
>+//PCTL1_UTCL2_RENG_RAM_INDEX
>+#define PCTL1_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                     0x0
>+#define PCTL1_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                       0x000007FFL
>+//PCTL1_UTCL2_RENG_RAM_DATA
>+#define PCTL1_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                       0x0
>+#define PCTL1_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                         0xFFFFFFFFL
>+//PCTL1_SLICE0_RENG_RAM_INDEX
>+#define PCTL1_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
>+#define PCTL1_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
>+//PCTL1_SLICE0_RENG_RAM_DATA
>+#define PCTL1_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
>+#define PCTL1_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
>+//PCTL1_SLICE1_RENG_RAM_INDEX
>+#define PCTL1_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
>+#define PCTL1_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
>+//PCTL1_SLICE1_RENG_RAM_DATA
>+#define PCTL1_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
>+#define PCTL1_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
>+//PCTL1_SLICE2_RENG_RAM_INDEX
>+#define PCTL1_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
>+#define PCTL1_SLICE2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
>+//PCTL1_SLICE2_RENG_RAM_DATA
>+#define PCTL1_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
>+#define PCTL1_SLICE2_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
>+//PCTL1_SLICE3_RENG_RAM_INDEX
>+#define PCTL1_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
>+#define PCTL1_SLICE3_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
>+//PCTL1_SLICE3_RENG_RAM_DATA
>+#define PCTL1_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
>+#define PCTL1_SLICE3_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
>+//PCTL1_SLICE4_RENG_RAM_INDEX
>+#define PCTL1_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                    0x0
>+#define PCTL1_SLICE4_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                      0x000003FFL
>+//PCTL1_SLICE4_RENG_RAM_DATA
>+#define PCTL1_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                      0x0
>+#define PCTL1_SLICE4_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                        0xFFFFFFFFL
>+//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
>+//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
>+//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
>+//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
>+//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
>+//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
>+//PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
>+#define PCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
>+//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                            0x0
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                           0x10
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                              0x0000FFFFL
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                             0xFFFF0000L
>+//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+//PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                        0x0
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                        0x10
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL0_MASK                          0x0000FFFFL
>+#define PCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL1_MASK                          0xFFFF0000L
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1dec:1
>+//VML1_1_MC_VM_MX_L1_TLB0_STATUS
>+#define VML1_1_MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_1_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_1_MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_1_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_1_MC_VM_MX_L1_TLB1_STATUS
>+#define VML1_1_MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_1_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_1_MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_1_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_1_MC_VM_MX_L1_TLB2_STATUS
>+#define VML1_1_MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_1_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_1_MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_1_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_1_MC_VM_MX_L1_TLB3_STATUS
>+#define VML1_1_MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_1_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_1_MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_1_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_1_MC_VM_MX_L1_TLB4_STATUS
>+#define VML1_1_MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_1_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_1_MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_1_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_1_MC_VM_MX_L1_TLB5_STATUS
>+#define VML1_1_MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_1_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_1_MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_1_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_1_MC_VM_MX_L1_TLB6_STATUS
>+#define VML1_1_MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_1_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_1_MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_1_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+//VML1_1_MC_VM_MX_L1_TLB7_STATUS
>+#define VML1_1_MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT                                                           0x0
>+#define VML1_1_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT                                            0x1
>+#define VML1_1_MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK                                                             0x00000001L
>+#define VML1_1_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK                                              0x00000002L
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1pldec:1
>+//VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                 0x0
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                             0x8
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                0x18
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                   0x1c
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                    0x1d
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                   0x000000FFL
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                  0x0F000000L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK                                                     0x10000000L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK                                                      0x20000000L
>+//VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                 0x0
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                             0x8
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                0x18
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                   0x1c
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                    0x1d
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                   0x000000FFL
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                  0x0F000000L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK                                                     0x10000000L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK                                                      0x20000000L
>+//VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                 0x0
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                             0x8
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                0x18
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                   0x1c
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                    0x1d
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                   0x000000FFL
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                  0x0F000000L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK                                                     0x10000000L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK                                                      0x20000000L
>+//VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                 0x0
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                             0x8
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                0x18
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                   0x1c
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                    0x1d
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                   0x000000FFL
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                  0x0F000000L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK                                                     0x10000000L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK                                                      0x20000000L
>+//VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                 0x0
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                       0x8
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                        0x10
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                          0x18
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                           0x19
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                0x1a
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                   0x0000000FL
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                         0x0000FF00L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                          0x00FF0000L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                            0x01000000L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                             0x02000000L
>+#define VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                  0x04000000L
>+
>+
>+// addressBlock: mmhub_l1tlb_vml1prdec:1
>+//VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO
>+#define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                 0x0
>+#define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                   0xFFFFFFFFL
>+//VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI
>+#define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                 0x0
>+#define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                              0x10
>+#define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                   0x0000FFFFL
>+#define VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                0xFFFF0000L
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2dec:1
>+//ATCL2_1_ATC_L2_CNTL
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT                                       0x0
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT                                      0x3
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                           0x6
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                          0x7
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT                                  0x8
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT                                 0xb
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                      0xe
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                     0xf
>+#define ATCL2_1_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT                                                     0x10
>+#define ATCL2_1_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                  0x13
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK                                         0x00000003L
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK                                        0x00000018L
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                             0x00000040L
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                            0x00000080L
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK                                    0x00000300L
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK                                   0x00001800L
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                        0x00004000L
>+#define ATCL2_1_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                       0x00008000L
>+#define ATCL2_1_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK                                                       0x00070000L
>+#define ATCL2_1_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                    0x00080000L
>+//ATCL2_1_ATC_L2_CNTL2
>+#define ATCL2_1_ATC_L2_CNTL2__BANK_SELECT__SHIFT                                                              0x0
>+#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT                                                     0x6
>+#define ATCL2_1_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                      0x8
>+#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT                                             0x9
>+#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT                                                       0xc
>+#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                 0xf
>+#define ATCL2_1_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE__SHIFT                                                    0x15
>+#define ATCL2_1_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE__SHIFT                                                   0x1b
>+#define ATCL2_1_ATC_L2_CNTL2__BANK_SELECT_MASK                                                                0x0000003FL
>+#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK                                                       0x000000C0L
>+#define ATCL2_1_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK                                        0x00000100L
>+#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK                                               0x00000E00L
>+#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK                                                         0x00007000L
>+#define ATCL2_1_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                   0x001F8000L
>+#define ATCL2_1_ATC_L2_CNTL2__L2_BIGK_FRAGMENT_SIZE_MASK                                                      0x07E00000L
>+#define ATCL2_1_ATC_L2_CNTL2__L2_4K_BIGK_SWAP_ENABLE_MASK                                                     0x08000000L
>+//ATCL2_1_ATC_L2_CACHE_DATA0
>+#define ATCL2_1_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT                                                0x0
>+#define ATCL2_1_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT                                                  0x1
>+#define ATCL2_1_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT                                                  0x2
>+#define ATCL2_1_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT                                          0x17
>+#define ATCL2_1_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK                                                  0x00000001L
>+#define ATCL2_1_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK                                                    0x00000002L
>+#define ATCL2_1_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK                                                    0x007FFFFCL
>+#define ATCL2_1_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK                                            0x07800000L
>+//ATCL2_1_ATC_L2_CACHE_DATA1
>+#define ATCL2_1_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT                                           0x0
>+#define ATCL2_1_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK                                             0xFFFFFFFFL
>+//ATCL2_1_ATC_L2_CACHE_DATA2
>+#define ATCL2_1_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT                                              0x0
>+#define ATCL2_1_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK                                                0xFFFFFFFFL
>+//ATCL2_1_ATC_L2_CNTL3
>+#define ATCL2_1_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT                                          0x0
>+#define ATCL2_1_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT                                                0x3
>+#define ATCL2_1_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT                                                0x9
>+#define ATCL2_1_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK                                            0x00000007L
>+#define ATCL2_1_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK                                                  0x000001F8L
>+#define ATCL2_1_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK                                                  0x00000E00L
>+//ATCL2_1_ATC_L2_STATUS
>+#define ATCL2_1_ATC_L2_STATUS__BUSY__SHIFT                                                                    0x0
>+#define ATCL2_1_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT                                                       0x1
>+#define ATCL2_1_ATC_L2_STATUS__BUSY_MASK                                                                      0x00000001L
>+#define ATCL2_1_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK                                                         0x7FFFFFFEL
>+//ATCL2_1_ATC_L2_STATUS2
>+#define ATCL2_1_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT                                      0x0
>+#define ATCL2_1_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT                                          0x8
>+#define ATCL2_1_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK                                        0x000000FFL
>+#define ATCL2_1_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK                                            0x0000FF00L
>+//ATCL2_1_ATC_L2_STATUS3
>+#define ATCL2_1_ATC_L2_STATUS3__BUSY__SHIFT                                                                   0x0
>+#define ATCL2_1_ATC_L2_STATUS3__PARITY_ERROR_INFO__SHIFT                                                      0x1
>+#define ATCL2_1_ATC_L2_STATUS3__BUSY_MASK                                                                     0x00000001L
>+#define ATCL2_1_ATC_L2_STATUS3__PARITY_ERROR_INFO_MASK                                                        0x7FFFFFFEL
>+//ATCL2_1_ATC_L2_MISC_CG
>+#define ATCL2_1_ATC_L2_MISC_CG__OFFDLY__SHIFT                                                                 0x6
>+#define ATCL2_1_ATC_L2_MISC_CG__ENABLE__SHIFT                                                                 0x12
>+#define ATCL2_1_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT                                                          0x13
>+#define ATCL2_1_ATC_L2_MISC_CG__OFFDLY_MASK                                                                   0x00000FC0L
>+#define ATCL2_1_ATC_L2_MISC_CG__ENABLE_MASK                                                                   0x00040000L
>+#define ATCL2_1_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK                                                            0x00080000L
>+//ATCL2_1_ATC_L2_MEM_POWER_LS
>+#define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT                                                          0x0
>+#define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT                                                           0x6
>+#define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK                                                            0x0000003FL
>+#define ATCL2_1_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK                                                             0x00000FC0L
>+//ATCL2_1_ATC_L2_CGTT_CLK_CTRL
>+#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
>+#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x4
>+#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                    0xf
>+#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                              0x10
>+#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                    0x18
>+#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000000FL
>+#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00000FF0L
>+#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                      0x00008000L
>+#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                0x00FF0000L
>+#define ATCL2_1_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                      0xFF000000L
>+//ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT                                                       0x0
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK                                                         0x000000FFL
>+//ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT                                                       0x0
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK                                                         0x000000FFL
>+//ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT                                                 0x0
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                           0x6
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                          0x8
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                          0x9
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                          0xb
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT                                               0xc
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT                                                    0xd
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT                                                    0xf
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT                                                     0x11
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK                                                   0x0000003FL
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                             0x000000C0L
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                            0x00000100L
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                            0x00000600L
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                            0x00000800L
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK                                                 0x00001000L
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK                                                      0x00006000L
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK                                                      0x00018000L
>+#define ATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK                                                       0x00020000L
>+//ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT                                                 0x0
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT                                           0x6
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT                                          0x8
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT                                          0x9
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT                                          0xb
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT                                               0xc
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT                                                    0xd
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT                                                    0xf
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT                                                     0x11
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK                                                   0x0000003FL
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK                                             0x000000C0L
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK                                            0x00000100L
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK                                            0x00000600L
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK                                            0x00000800L
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK                                                 0x00001000L
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK                                                      0x00006000L
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK                                                      0x00018000L
>+#define ATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK                                                       0x00020000L
>+//ATCL2_1_ATC_L2_CNTL4
>+#define ATCL2_1_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                  0x0
>+#define ATCL2_1_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                 0xa
>+#define ATCL2_1_ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                    0x000003FFL
>+#define ATCL2_1_ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                   0x000FFC00L
>+//ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES
>+#define ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT                                             0x0
>+#define ATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK                                               0xFFFFFFFFL
>+
>+
>+// addressBlock: mmhub_utcl2_vml2pfdec:1
>+//VML2PF1_VM_L2_CNTL
>+#define VML2PF1_VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                            0x0
>+#define VML2PF1_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                              0x1
>+#define VML2PF1_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                              0x2
>+#define VML2PF1_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                              0x4
>+#define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                          0x8
>+#define VML2PF1_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                    0x9
>+#define VML2PF1_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                   0xa
>+#define VML2PF1_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                   0xb
>+#define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                   0xc
>+#define VML2PF1_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                    0xf
>+#define VML2PF1_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                   0x12
>+#define VML2PF1_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                              0x13
>+#define VML2PF1_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                0x15
>+#define VML2PF1_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                     0x1a
>+#define VML2PF1_VM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                              0x00000001L
>+#define VML2PF1_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                0x00000002L
>+#define VML2PF1_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                0x0000000CL
>+#define VML2PF1_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                0x00000030L
>+#define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                            0x00000100L
>+#define VML2PF1_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                      0x00000200L
>+#define VML2PF1_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                     0x00000400L
>+#define VML2PF1_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                     0x00000800L
>+#define VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                     0x00007000L
>+#define VML2PF1_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                      0x00038000L
>+#define VML2PF1_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                     0x00040000L
>+#define VML2PF1_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                0x00180000L
>+#define VML2PF1_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                  0x03E00000L
>+#define VML2PF1_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                       0x0C000000L
>+//VML2PF1_VM_L2_CNTL2
>+#define VML2PF1_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                    0x0
>+#define VML2PF1_VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                       0x1
>+#define VML2PF1_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                             0x15
>+#define VML2PF1_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                           0x16
>+#define VML2PF1_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                    0x17
>+#define VML2PF1_VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                     0x1a
>+#define VML2PF1_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                  0x1c
>+#define VML2PF1_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                      0x00000001L
>+#define VML2PF1_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                         0x00000002L
>+#define VML2PF1_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                               0x00200000L
>+#define VML2PF1_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                             0x00400000L
>+#define VML2PF1_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                      0x03800000L
>+#define VML2PF1_VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                       0x0C000000L
>+#define VML2PF1_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                    0x70000000L
>+//VML2PF1_VM_L2_CNTL3
>+#define VML2PF1_VM_L2_CNTL3__BANK_SELECT__SHIFT                                                               0x0
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                      0x6
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                  0x8
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                               0xf
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                               0x14
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                0x15
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                              0x18
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                    0x1c
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                  0x1d
>+#define VML2PF1_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                      0x1e
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                 0x1f
>+#define VML2PF1_VM_L2_CNTL3__BANK_SELECT_MASK                                                                 0x0000003FL
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                        0x000000C0L
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                    0x00001F00L
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                 0x000F8000L
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                 0x00100000L
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                  0x00E00000L
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                0x0F000000L
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                      0x10000000L
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                    0x20000000L
>+#define VML2PF1_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                        0x40000000L
>+#define VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                   0x80000000L
>+//VML2PF1_VM_L2_STATUS
>+#define VML2PF1_VM_L2_STATUS__L2_BUSY__SHIFT                                                                  0x0
>+#define VML2PF1_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                      0x1
>+#define VML2PF1_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                         0x11
>+#define VML2PF1_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                       0x12
>+#define VML2PF1_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                           0x13
>+#define VML2PF1_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                           0x14
>+#define VML2PF1_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                           0x15
>+#define VML2PF1_VM_L2_STATUS__L2_BUSY_MASK                                                                    0x00000001L
>+#define VML2PF1_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                        0x0001FFFEL
>+#define VML2PF1_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                           0x00020000L
>+#define VML2PF1_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                         0x00040000L
>+#define VML2PF1_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                             0x00080000L
>+#define VML2PF1_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                             0x00100000L
>+#define VML2PF1_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                             0x00200000L
>+//VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL
>+#define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                      0x0
>+#define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                   0x1
>+#define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                      0x2
>+#define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                        0x00000001L
>+#define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                     0x00000002L
>+#define VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                        0x000000FCL
>+//VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32
>+#define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                    0x0
>+#define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                      0xFFFFFFFFL
>+//VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32
>+#define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                     0x0
>+#define VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                       0x0000000FL
>+//VML2PF1_VM_L2_PROTECTION_FAULT_CNTL
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                        0x0
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT     0x1
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                     0x2
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x3
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x4
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x5
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT         0x6
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x7
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                0x8
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                     0x9
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0xa
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                     0xb
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                   0xc
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                        0xd
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                  0x1d
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                   0x1e
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                      0x1f
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                          0x00000001L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK       0x00000002L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                       0x00000004L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000008L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000010L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000020L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK           0x00000040L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000080L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                  0x00000100L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                       0x00000200L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000400L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                       0x00000800L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                     0x00001000L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                          0x1FFFE000L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                    0x20000000L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                     0x40000000L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                        0x80000000L
>+//VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                            0x0
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                      0x10
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                0x11
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                     0x12
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                             0x13
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                              0x0000FFFFL
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                        0x00010000L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                  0x00020000L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                       0x00040000L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                               0x00080000L
>+//VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT          0x0
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK            0xFFFFFFFFL
>+//VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT         0x0
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK           0xFFFFFFFFL
>+//VML2PF1_VM_L2_PROTECTION_FAULT_STATUS
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                             0x0
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                            0x1
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                       0x4
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                           0x8
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                     0x9
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                      0x12
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                  0x13
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                    0x14
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                      0x18
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                    0x19
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                               0x00000001L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                              0x0000000EL
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                         0x000000F0L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                             0x00000100L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                       0x0003FE00L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                        0x00040000L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                    0x00080000L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                      0x00F00000L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                        0x01000000L
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                      0x1E000000L
>+//VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                               0x0
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                 0xFFFFFFFFL
>+//VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                0x0
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                  0x0000000FL
>+//VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                      0x0
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                        0xFFFFFFFFL
>+//VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                       0x0
>+#define VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                         0x0000000FL
>+//VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
>+#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT               0x0
>+#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                 0xFFFFFFFFL
>+//VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
>+#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                0x0
>+#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                  0x0000000FL
>+//VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
>+#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT              0x0
>+#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                0xFFFFFFFFL
>+//VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
>+#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT               0x0
>+#define VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                 0x0000000FL
>+//VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
>+#define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                 0x0
>+#define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                   0xFFFFFFFFL
>+//VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
>+#define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                  0x0
>+#define VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                    0x0000000FL
>+//VML2PF1_VM_L2_CNTL4
>+#define VML2PF1_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                               0x0
>+#define VML2PF1_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                              0x6
>+#define VML2PF1_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                              0x7
>+#define VML2PF1_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                   0x8
>+#define VML2PF1_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                  0x12
>+#define VML2PF1_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                       0x1c
>+#define VML2PF1_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                 0x0000003FL
>+#define VML2PF1_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                0x00000040L
>+#define VML2PF1_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                0x00000080L
>+#define VML2PF1_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                     0x0003FF00L
>+#define VML2PF1_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                    0x0FFC0000L
>+#define VML2PF1_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                         0x10000000L
>+//VML2PF1_VM_L2_MM_GROUP_RT_CLASSES
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                            0x0
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                            0x1
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                            0x2
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                            0x3
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                            0x4
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                            0x5
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                            0x6
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                            0x7
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                            0x8
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                            0x9
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                           0xa
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                           0xb
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                           0xc
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                           0xd
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                           0xe
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                           0xf
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                           0x10
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                           0x11
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                           0x12
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                           0x13
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                           0x14
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                           0x15
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                           0x16
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                           0x17
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                           0x18
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                           0x19
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                           0x1a
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                           0x1b
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                           0x1c
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                           0x1d
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                           0x1e
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                           0x1f
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                              0x00000001L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                              0x00000002L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                              0x00000004L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                              0x00000008L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                              0x00000010L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                              0x00000020L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                              0x00000040L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                              0x00000080L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                              0x00000100L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                              0x00000200L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                             0x00000400L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                             0x00000800L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                             0x00001000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                             0x00002000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                             0x00004000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                             0x00008000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                             0x00010000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                             0x00020000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                             0x00040000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                             0x00080000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                             0x00100000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                             0x00200000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                             0x00400000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                             0x00800000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                             0x01000000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                             0x02000000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                             0x04000000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                             0x08000000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                             0x10000000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                             0x20000000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                             0x40000000L
>+#define VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                             0x80000000L
>+//VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                0x0
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                               0xa
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                 0x14
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                       0x18
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                    0x19
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                  0x000001FFL
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                 0x0007FC00L
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                   0x00100000L
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                         0x01000000L
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                      0x02000000L
>+//VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                               0x0
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                              0xa
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                0x14
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                      0x18
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                   0x19
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                 0x000001FFL
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                0x0007FC00L
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                  0x00100000L
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                        0x01000000L
>+#define VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                     0x02000000L
>+//VML2PF1_VM_L2_CACHE_PARITY_CNTL
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                         0x0
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                       0x1
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                            0x2
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                         0x3
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                       0x4
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                            0x5
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                              0x6
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                            0x9
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                             0xc
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                           0x00000001L
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                         0x00000002L
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                              0x00000004L
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                           0x00000008L
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                         0x00000010L
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                              0x00000020L
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                0x000001C0L
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                              0x00000E00L
>+#define VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                               0x0000F000L
>+//VML2PF1_VM_L2_CGTT_CLK_CTRL
>+#define VML2PF1_VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                          0x0
>+#define VML2PF1_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                    0x4
>+#define VML2PF1_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                     0xf
>+#define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                               0x10
>+#define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                     0x18
>+#define VML2PF1_VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                            0x0000000FL
>+#define VML2PF1_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                      0x00000FF0L
>+#define VML2PF1_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                       0x00008000L
>+#define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                                 0x00FF0000L
>+#define VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                       0xFF000000L
>+
>+
>+// addressBlock: mmhub_utcl2_vml2vcdec:1
>+//VML2VC1_VM_CONTEXT0_CNTL
>+#define VML2VC1_VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC1_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC1_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC1_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC1_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC1_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC1_VM_CONTEXT1_CNTL
>+#define VML2VC1_VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC1_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC1_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC1_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC1_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC1_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC1_VM_CONTEXT2_CNTL
>+#define VML2VC1_VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC1_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC1_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC1_VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC1_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC1_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC1_VM_CONTEXT3_CNTL
>+#define VML2VC1_VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC1_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC1_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC1_VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC1_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC1_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC1_VM_CONTEXT4_CNTL
>+#define VML2VC1_VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC1_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC1_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC1_VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC1_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC1_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC1_VM_CONTEXT5_CNTL
>+#define VML2VC1_VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC1_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC1_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC1_VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC1_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC1_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC1_VM_CONTEXT6_CNTL
>+#define VML2VC1_VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC1_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC1_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC1_VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC1_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC1_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC1_VM_CONTEXT7_CNTL
>+#define VML2VC1_VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC1_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC1_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC1_VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC1_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC1_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC1_VM_CONTEXT8_CNTL
>+#define VML2VC1_VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC1_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC1_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC1_VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC1_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC1_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC1_VM_CONTEXT9_CNTL
>+#define VML2VC1_VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                       0x0
>+#define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                     0x1
>+#define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                0x3
>+#define VML2VC1_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                               0x7
>+#define VML2VC1_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                    0x8
>+#define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
>+#define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
>+#define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                         0xb
>+#define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xc
>+#define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xd
>+#define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xe
>+#define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
>+#define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
>+#define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0x11
>+#define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0x12
>+#define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x13
>+#define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x14
>+#define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x15
>+#define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x16
>+#define VML2VC1_VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                         0x00000001L
>+#define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                       0x00000006L
>+#define VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                  0x00000078L
>+#define VML2VC1_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                 0x00000080L
>+#define VML2VC1_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                      0x00000100L
>+#define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
>+#define VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
>+#define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                           0x00000800L
>+#define VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00001000L
>+#define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00002000L
>+#define VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00004000L
>+#define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
>+#define VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
>+#define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00020000L
>+#define VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00040000L
>+#define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00080000L
>+#define VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00100000L
>+#define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x00200000L
>+#define VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x00400000L
>+//VML2VC1_VM_CONTEXT10_CNTL
>+#define VML2VC1_VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
>+#define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
>+#define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
>+#define VML2VC1_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
>+#define VML2VC1_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
>+#define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
>+#define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
>+#define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
>+#define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
>+#define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
>+#define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
>+#define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
>+#define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
>+#define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
>+#define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
>+#define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
>+#define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
>+#define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
>+#define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
>+#define VML2VC1_VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
>+#define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
>+#define VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
>+#define VML2VC1_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
>+#define VML2VC1_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
>+#define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
>+#define VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
>+#define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
>+#define VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
>+#define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
>+#define VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
>+#define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
>+#define VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
>+#define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
>+#define VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
>+#define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
>+#define VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
>+#define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
>+#define VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
>+//VML2VC1_VM_CONTEXT11_CNTL
>+#define VML2VC1_VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
>+#define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
>+#define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
>+#define VML2VC1_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
>+#define VML2VC1_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
>+#define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
>+#define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
>+#define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
>+#define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
>+#define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
>+#define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
>+#define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
>+#define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
>+#define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
>+#define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
>+#define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
>+#define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
>+#define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
>+#define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
>+#define VML2VC1_VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
>+#define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
>+#define VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
>+#define VML2VC1_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
>+#define VML2VC1_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
>+#define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
>+#define VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
>+#define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
>+#define VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
>+#define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
>+#define VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
>+#define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
>+#define VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
>+#define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
>+#define VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
>+#define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
>+#define VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
>+#define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
>+#define VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
>+//VML2VC1_VM_CONTEXT12_CNTL
>+#define VML2VC1_VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
>+#define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
>+#define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
>+#define VML2VC1_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
>+#define VML2VC1_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
>+#define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
>+#define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
>+#define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
>+#define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
>+#define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
>+#define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
>+#define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
>+#define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
>+#define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
>+#define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
>+#define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
>+#define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
>+#define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
>+#define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
>+#define VML2VC1_VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
>+#define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
>+#define VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
>+#define VML2VC1_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
>+#define VML2VC1_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
>+#define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
>+#define VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
>+#define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
>+#define VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
>+#define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
>+#define VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
>+#define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
>+#define VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
>+#define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
>+#define VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
>+#define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
>+#define VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
>+#define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
>+#define VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
>+//VML2VC1_VM_CONTEXT13_CNTL
>+#define VML2VC1_VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
>+#define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
>+#define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
>+#define VML2VC1_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
>+#define VML2VC1_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
>+#define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
>+#define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
>+#define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
>+#define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
>+#define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
>+#define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
>+#define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
>+#define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
>+#define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
>+#define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
>+#define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
>+#define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
>+#define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
>+#define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
>+#define VML2VC1_VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
>+#define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
>+#define VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
>+#define VML2VC1_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
>+#define VML2VC1_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
>+#define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
>+#define VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
>+#define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
>+#define VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
>+#define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
>+#define VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
>+#define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
>+#define VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
>+#define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
>+#define VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
>+#define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
>+#define VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
>+#define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
>+#define VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
>+//VML2VC1_VM_CONTEXT14_CNTL
>+#define VML2VC1_VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
>+#define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
>+#define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
>+#define VML2VC1_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
>+#define VML2VC1_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
>+#define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
>+#define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
>+#define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
>+#define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
>+#define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
>+#define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
>+#define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
>+#define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
>+#define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
>+#define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
>+#define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
>+#define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
>+#define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
>+#define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
>+#define VML2VC1_VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
>+#define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
>+#define VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
>+#define VML2VC1_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
>+#define VML2VC1_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
>+#define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
>+#define VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
>+#define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
>+#define VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
>+#define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
>+#define VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
>+#define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
>+#define VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
>+#define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
>+#define VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
>+#define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
>+#define VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
>+#define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
>+#define VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
>+//VML2VC1_VM_CONTEXT15_CNTL
>+#define VML2VC1_VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
>+#define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
>+#define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x3
>+#define VML2VC1_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                              0x7
>+#define VML2VC1_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                   0x8
>+#define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x9
>+#define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xa
>+#define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0xb
>+#define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0xc
>+#define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xd
>+#define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xe
>+#define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xf
>+#define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x10
>+#define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x11
>+#define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x12
>+#define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x13
>+#define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x14
>+#define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
>+#define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
>+#define VML2VC1_VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
>+#define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
>+#define VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x00000078L
>+#define VML2VC1_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                0x00000080L
>+#define VML2VC1_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                     0x00000100L
>+#define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000200L
>+#define VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000400L
>+#define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000800L
>+#define VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00001000L
>+#define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00002000L
>+#define VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00004000L
>+#define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00008000L
>+#define VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00010000L
>+#define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00020000L
>+#define VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00040000L
>+#define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00080000L
>+#define VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00100000L
>+#define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
>+#define VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
>+//VML2VC1_VM_CONTEXTS_DISABLE
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                 0x0
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                 0x1
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                 0x2
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                 0x3
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                 0x4
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                 0x5
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                 0x6
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                 0x7
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                 0x8
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                 0x9
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                0xa
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                0xb
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                0xc
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                0xd
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                0xe
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                0xf
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                   0x00000001L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                   0x00000002L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                   0x00000004L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                   0x00000008L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                   0x00000010L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                   0x00000020L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                   0x00000040L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                   0x00000080L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                   0x00000100L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                   0x00000200L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                  0x00000400L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                  0x00000800L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                  0x00001000L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                  0x00002000L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                  0x00004000L
>+#define VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                  0x00008000L
>+//VML2VC1_VM_INVALIDATE_ENG0_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC1_VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG1_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC1_VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG2_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC1_VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG3_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC1_VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG4_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC1_VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG5_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC1_VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG6_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC1_VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG7_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC1_VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG8_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC1_VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG9_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                      0x0
>+#define VML2VC1_VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                        0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG10_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC1_VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG11_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC1_VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG12_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC1_VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG13_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC1_VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG14_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC1_VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG15_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC1_VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG16_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC1_VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG17_SEM
>+#define VML2VC1_VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                     0x0
>+#define VML2VC1_VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                       0x00000001L
>+//VML2VC1_VM_INVALIDATE_ENG0_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG1_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG2_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG3_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG4_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG5_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG6_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG7_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG8_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG9_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                             0x12
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                             0x13
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                             0x14
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                             0x15
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                             0x16
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                             0x17
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                       0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                               0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                               0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                               0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                               0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                               0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                               0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG10_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG11_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG12_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG13_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG14_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG15_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG16_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG17_REQ
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                    0x10
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                            0x12
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                            0x13
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                            0x14
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                            0x15
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                            0x16
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                            0x17
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                      0x00030000L
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                              0x00040000L
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                              0x00080000L
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                              0x00100000L
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                              0x00200000L
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                              0x00400000L
>+#define VML2VC1_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                              0x00800000L
>+//VML2VC1_VM_INVALIDATE_ENG0_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC1_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG1_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC1_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG2_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC1_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG3_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC1_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG4_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC1_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG5_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC1_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG6_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC1_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG7_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC1_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG8_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC1_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG9_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                        0x0
>+#define VML2VC1_VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                      0x10
>+#define VML2VC1_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                          0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                        0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG10_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG11_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG12_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG13_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG14_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG15_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG16_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG17_ACK
>+#define VML2VC1_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                       0x0
>+#define VML2VC1_VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                     0x10
>+#define VML2VC1_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                         0x0000FFFFL
>+#define VML2VC1_VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                       0x00010000L
>+//VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                              0x0
>+#define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                          0x1
>+#define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                            0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                           0x0
>+#define VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                             0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32
>+#define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                             0x0
>+#define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                         0x1
>+#define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                               0x00000001L
>+#define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                           0xFFFFFFFEL
>+//VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32
>+#define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                          0x0
>+#define VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                            0x0000001FL
>+//VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                         0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                          0x0000000FL
>+//VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
>+//VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
>+//VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
>+//VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
>+//VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
>+//VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
>+#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
>+#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
>+//VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                           0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                          0x0
>+#define VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                            0x0000000FL
>+//VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
>+//VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
>+//VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
>+//VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
>+//VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
>+//VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
>+#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
>+#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
>+//VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
>+#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
>+#define VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedpfdec:1
>+//VMSHAREDPF1_MC_VM_NB_MMIOBASE
>+#define VMSHAREDPF1_MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT                                                        0x0
>+#define VMSHAREDPF1_MC_VM_NB_MMIOBASE__MMIOBASE_MASK                                                          0xFFFFFFFFL
>+//VMSHAREDPF1_MC_VM_NB_MMIOLIMIT
>+#define VMSHAREDPF1_MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                      0x0
>+#define VMSHAREDPF1_MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK                                                        0xFFFFFFFFL
>+//VMSHAREDPF1_MC_VM_NB_PCI_CTRL
>+#define VMSHAREDPF1_MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT                                                      0x17
>+#define VMSHAREDPF1_MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK                                                        0x00800000L
>+//VMSHAREDPF1_MC_VM_NB_PCI_ARB
>+#define VMSHAREDPF1_MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT                                                         0x3
>+#define VMSHAREDPF1_MC_VM_NB_PCI_ARB__VGA_HOLE_MASK                                                           0x00000008L
>+//VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1
>+#define VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT                                            0x17
>+#define VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK                                              0xFF800000L
>+//VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2
>+#define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                0x0
>+#define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                            0x17
>+#define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                  0x00000001L
>+#define VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                              0xFF800000L
>+//VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2
>+#define VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                            0x0
>+#define VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                              0x00000FFFL
>+//VMSHAREDPF1_MC_VM_FB_OFFSET
>+#define VMSHAREDPF1_MC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                         0x0
>+#define VMSHAREDPF1_MC_VM_FB_OFFSET__FB_OFFSET_MASK                                                           0x00FFFFFFL
>+//VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
>+#define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                   0x0
>+#define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                     0xFFFFFFFFL
>+//VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
>+#define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                   0x0
>+#define VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                     0x0000000FL
>+//VMSHAREDPF1_MC_VM_STEERING
>+#define VMSHAREDPF1_MC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                   0x0
>+#define VMSHAREDPF1_MC_VM_STEERING__DEFAULT_STEERING_MASK                                                     0x00000003L
>+//VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ
>+#define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                       0x0
>+#define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                       0x1f
>+#define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__VF_MASK                                                         0x0000FFFFL
>+#define VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__PF_MASK                                                         0x80000000L
>+//VMSHAREDPF1_MC_MEM_POWER_LS
>+#define VMSHAREDPF1_MC_MEM_POWER_LS__LS_SETUP__SHIFT                                                          0x0
>+#define VMSHAREDPF1_MC_MEM_POWER_LS__LS_HOLD__SHIFT                                                           0x6
>+#define VMSHAREDPF1_MC_MEM_POWER_LS__LS_SETUP_MASK                                                            0x0000003FL
>+#define VMSHAREDPF1_MC_MEM_POWER_LS__LS_HOLD_MASK                                                             0x00000FC0L
>+//VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START
>+#define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                        0x0
>+#define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                          0x000FFFFFL
>+//VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END
>+#define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                          0x0
>+#define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                            0x000FFFFFL
>+//VMSHAREDPF1_MC_VM_APT_CNTL
>+#define VMSHAREDPF1_MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                     0x0
>+#define VMSHAREDPF1_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                   0x1
>+#define VMSHAREDPF1_MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                       0x00000001L
>+#define VMSHAREDPF1_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                     0x00000002L
>+//VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START
>+#define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT                                             0x0
>+#define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK                                               0x000FFFFFL
>+//VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END
>+#define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT                                               0x0
>+#define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK                                                 0x000FFFFFL
>+//VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
>+#define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                            0x0
>+#define VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                              0x00000001L
>+//VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL
>+#define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT                                                 0x0
>+#define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT                                                 0x4
>+#define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK                                                   0x0000000FL
>+#define VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK                                                   0x000000F0L
>+//VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE
>+#define VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT                                                   0x0
>+#define VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK                                                     0x0001FFFFL
>+//VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL
>+#define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT                  0x0
>+#define VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK                    0x00000001L
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedvcdec:1
>+//VMSHAREDVC1_MC_VM_FB_LOCATION_BASE
>+#define VMSHAREDVC1_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                    0x0
>+#define VMSHAREDVC1_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                      0x00FFFFFFL
>+//VMSHAREDVC1_MC_VM_FB_LOCATION_TOP
>+#define VMSHAREDVC1_MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                      0x0
>+#define VMSHAREDVC1_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                        0x00FFFFFFL
>+//VMSHAREDVC1_MC_VM_AGP_TOP
>+#define VMSHAREDVC1_MC_VM_AGP_TOP__AGP_TOP__SHIFT                                                             0x0
>+#define VMSHAREDVC1_MC_VM_AGP_TOP__AGP_TOP_MASK                                                               0x00FFFFFFL
>+//VMSHAREDVC1_MC_VM_AGP_BOT
>+#define VMSHAREDVC1_MC_VM_AGP_BOT__AGP_BOT__SHIFT                                                             0x0
>+#define VMSHAREDVC1_MC_VM_AGP_BOT__AGP_BOT_MASK                                                               0x00FFFFFFL
>+//VMSHAREDVC1_MC_VM_AGP_BASE
>+#define VMSHAREDVC1_MC_VM_AGP_BASE__AGP_BASE__SHIFT                                                           0x0
>+#define VMSHAREDVC1_MC_VM_AGP_BASE__AGP_BASE_MASK                                                             0x00FFFFFFL
>+//VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR
>+#define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                       0x0
>+#define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                         0x3FFFFFFFL
>+//VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
>+#define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                      0x0
>+#define VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                        0x3FFFFFFFL
>+//VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                0x0
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                           0x3
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                              0x5
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                 0x6
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                     0x7
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                        0xb
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT                                                       0xd
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                  0x00000001L
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                             0x00000018L
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                0x00000020L
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                   0x00000040L
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                       0x00000780L
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                          0x00001800L
>+#define VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK                                                         0x00002000L
>+
>+
>+// addressBlock: mmhub_utcl2_vmsharedhvdec:1
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT                                             0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK                                                 0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK                                               0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT                                              0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT                                            0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK                                                0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK                                              0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT                                              0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT                                            0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK                                                0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK                                              0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT                                              0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT                                            0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK                                                0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK                                              0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT                                              0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT                                            0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK                                                0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK                                              0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT                                              0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT                                            0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK                                                0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK                                              0xFFFF0000L
>+//VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT                                              0x0
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT                                            0x10
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK                                                0x0000FFFFL
>+#define VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK                                              0xFFFF0000L
>+//VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1
>+#define VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT                                                     0x8
>+#define VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK                                                       0x00000100L
>+//VMSHAREDHV1_MC_VM_MARC_BASE_LO_0
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT                                               0xc
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK                                                 0xFFFFF000L
>+//VMSHAREDHV1_MC_VM_MARC_BASE_LO_1
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT                                               0xc
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK                                                 0xFFFFF000L
>+//VMSHAREDHV1_MC_VM_MARC_BASE_LO_2
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT                                               0xc
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK                                                 0xFFFFF000L
>+//VMSHAREDHV1_MC_VM_MARC_BASE_LO_3
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT                                               0xc
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK                                                 0xFFFFF000L
>+//VMSHAREDHV1_MC_VM_MARC_BASE_HI_0
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK                                                 0x000FFFFFL
>+//VMSHAREDHV1_MC_VM_MARC_BASE_HI_1
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK                                                 0x000FFFFFL
>+//VMSHAREDHV1_MC_VM_MARC_BASE_HI_2
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK                                                 0x000FFFFFL
>+//VMSHAREDHV1_MC_VM_MARC_BASE_HI_3
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK                                                 0x000FFFFFL
>+//VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT                                             0x1
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT                                             0xc
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK                                                 0x00000001L
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK                                               0x00000002L
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK                                               0xFFFFF000L
>+//VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT                                             0x1
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT                                             0xc
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK                                                 0x00000001L
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK                                               0x00000002L
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK                                               0xFFFFF000L
>+//VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT                                             0x1
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT                                             0xc
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK                                                 0x00000001L
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK                                               0x00000002L
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK                                               0xFFFFF000L
>+//VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT                                             0x1
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT                                             0xc
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK                                                 0x00000001L
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK                                               0x00000002L
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK                                               0xFFFFF000L
>+//VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT                                             0x0
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK                                               0x000FFFFFL
>+//VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT                                             0x0
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK                                               0x000FFFFFL
>+//VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT                                             0x0
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK                                               0x000FFFFFL
>+//VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT                                             0x0
>+#define VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK                                               0x000FFFFFL
>+//VMSHAREDHV1_MC_VM_MARC_LEN_LO_0
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT                                                 0xc
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK                                                   0xFFFFF000L
>+//VMSHAREDHV1_MC_VM_MARC_LEN_LO_1
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT                                                 0xc
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK                                                   0xFFFFF000L
>+//VMSHAREDHV1_MC_VM_MARC_LEN_LO_2
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT                                                 0xc
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK                                                   0xFFFFF000L
>+//VMSHAREDHV1_MC_VM_MARC_LEN_LO_3
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT                                                 0xc
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK                                                   0xFFFFF000L
>+//VMSHAREDHV1_MC_VM_MARC_LEN_HI_0
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT                                                 0x0
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK                                                   0x000FFFFFL
>+//VMSHAREDHV1_MC_VM_MARC_LEN_HI_1
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT                                                 0x0
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK                                                   0x000FFFFFL
>+//VMSHAREDHV1_MC_VM_MARC_LEN_HI_2
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT                                                 0x0
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK                                                   0x000FFFFFL
>+//VMSHAREDHV1_MC_VM_MARC_LEN_HI_3
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT                                                 0x0
>+#define VMSHAREDHV1_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK                                                   0x000FFFFFL
>+//VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER
>+#define VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                 0x0
>+#define VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK                                                   0x00000001L
>+//VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
>+#define VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT                      0xd
>+#define VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK                        0x00002000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL__STU__SHIFT                                                              0x10
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                       0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL__STU_MASK                                                                0x001F0000L
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                         0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT                                                  0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK                                                    0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT                                                 0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK                                                   0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT                                                 0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK                                                   0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT                                                 0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK                                                   0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT                                                 0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK                                                   0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT                                                 0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK                                                   0x80000000L
>+//VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT                                                 0x1f
>+#define VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK                                                   0x80000000L
>+//VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL
>+#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                      0x0
>+#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                0x4
>+#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT                                           0xc
>+#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT                                                 0xf
>+#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT                                           0x10
>+#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT                                                 0x18
>+#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                        0x0000000FL
>+#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                  0x00000FF0L
>+#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK                                             0x00007000L
>+#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK                                                   0x00008000L
>+#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK                                             0x00FF0000L
>+#define VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK                                                   0xFF000000L
>+//VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID
>+#define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT                                                      0x0
>+#define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT                                                        0x1f
>+#define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VFID_MASK                                                        0x0000000FL
>+#define VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VF_MASK                                                          0x80000000L
>+//VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT                                               0x0
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT                                               0x1
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT                                               0x2
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT                                               0x3
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT                                               0x4
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT                                               0x5
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT                                               0x6
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT                                               0x7
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT                                               0x8
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT                                               0x9
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT                                              0xa
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT                                              0xb
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT                                              0xc
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT                                              0xd
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT                                              0xe
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT                                              0xf
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT                                                0x1f
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK                                                 0x00000001L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK                                                 0x00000002L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK                                                 0x00000004L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK                                                 0x00000008L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK                                                 0x00000010L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK                                                 0x00000020L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK                                                 0x00000040L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK                                                 0x00000080L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK                                                 0x00000100L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK                                                 0x00000200L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK                                                0x00000400L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK                                                0x00000800L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK                                                0x00001000L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK                                                0x00002000L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK                                                0x00004000L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK                                                0x00008000L
>+#define VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK                                                  0x80000000L
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2pfcntrdec:1
>+//ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO
>+#define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                 0x0
>+#define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                   0xFFFFFFFFL
>+//ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI
>+#define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                 0x0
>+#define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                              0x10
>+#define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                   0x0000FFFFL
>+#define ATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                0xFFFF0000L
>+
>+
>+// addressBlock: mmhub_utcl2_atcl2pfcntldec:1
>+//ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                 0x0
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                             0x8
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                0x18
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                   0x1c
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                    0x1d
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                   0x000000FFL
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                  0x0F000000L
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                     0x10000000L
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                      0x20000000L
>+//ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                 0x0
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                             0x8
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                0x18
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                   0x1c
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                    0x1d
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                   0x000000FFL
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                               0x0000FF00L
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                  0x0F000000L
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                     0x10000000L
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                      0x20000000L
>+//ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                 0x0
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                       0x8
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                        0x10
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                          0x18
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                           0x19
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                0x1a
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                   0x0000000FL
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                         0x0000FF00L
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                          0x00FF0000L
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                            0x01000000L
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                             0x02000000L
>+#define ATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                  0x04000000L
>+
>+
>+// addressBlock: mmhub_utcl2_vml2pldec:1
>+//VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                    0x0
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                0x8
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                   0x18
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                      0x1c
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                       0x1d
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                      0x000000FFL
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                  0x0000FF00L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                     0x0F000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                        0x10000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                         0x20000000L
>+//VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                    0x0
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                          0x8
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                           0x10
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                             0x18
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                              0x19
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                   0x1a
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                      0x0000000FL
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                            0x0000FF00L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                             0x00FF0000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                               0x01000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                0x02000000L
>+#define VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                     0x04000000L
>+
>+
>+// addressBlock: mmhub_utcl2_vml2prdec:1
>+//VML2PR1_MC_VM_L2_PERFCOUNTER_LO
>+#define VML2PR1_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                    0x0
>+#define VML2PR1_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                      0xFFFFFFFFL
>+//VML2PR1_MC_VM_L2_PERFCOUNTER_HI
>+#define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                    0x0
>+#define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                 0x10
>+#define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                      0x0000FFFFL
>+#define VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                   0xFFFF0000L
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_offset.h	2019-08-31 15:01:11.909736173 -0500
>@@ -0,0 +1,336 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _mp_12_0_0_OFFSET_HEADER
>+#define _mp_12_0_0_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: mp_SmuMp0_SmnDec
>+// base address: 0x0
>+#define mmMP0_SMN_C2PMSG_32                                                                            0x0060
>+#define mmMP0_SMN_C2PMSG_32_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_33                                                                            0x0061
>+#define mmMP0_SMN_C2PMSG_33_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_34                                                                            0x0062
>+#define mmMP0_SMN_C2PMSG_34_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_35                                                                            0x0063
>+#define mmMP0_SMN_C2PMSG_35_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_36                                                                            0x0064
>+#define mmMP0_SMN_C2PMSG_36_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_37                                                                            0x0065
>+#define mmMP0_SMN_C2PMSG_37_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_38                                                                            0x0066
>+#define mmMP0_SMN_C2PMSG_38_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_39                                                                            0x0067
>+#define mmMP0_SMN_C2PMSG_39_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_40                                                                            0x0068
>+#define mmMP0_SMN_C2PMSG_40_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_41                                                                            0x0069
>+#define mmMP0_SMN_C2PMSG_41_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_42                                                                            0x006a
>+#define mmMP0_SMN_C2PMSG_42_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_43                                                                            0x006b
>+#define mmMP0_SMN_C2PMSG_43_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_44                                                                            0x006c
>+#define mmMP0_SMN_C2PMSG_44_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_45                                                                            0x006d
>+#define mmMP0_SMN_C2PMSG_45_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_46                                                                            0x006e
>+#define mmMP0_SMN_C2PMSG_46_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_47                                                                            0x006f
>+#define mmMP0_SMN_C2PMSG_47_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_48                                                                            0x0070
>+#define mmMP0_SMN_C2PMSG_48_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_49                                                                            0x0071
>+#define mmMP0_SMN_C2PMSG_49_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_50                                                                            0x0072
>+#define mmMP0_SMN_C2PMSG_50_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_51                                                                            0x0073
>+#define mmMP0_SMN_C2PMSG_51_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_52                                                                            0x0074
>+#define mmMP0_SMN_C2PMSG_52_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_53                                                                            0x0075
>+#define mmMP0_SMN_C2PMSG_53_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_54                                                                            0x0076
>+#define mmMP0_SMN_C2PMSG_54_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_55                                                                            0x0077
>+#define mmMP0_SMN_C2PMSG_55_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_56                                                                            0x0078
>+#define mmMP0_SMN_C2PMSG_56_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_57                                                                            0x0079
>+#define mmMP0_SMN_C2PMSG_57_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_58                                                                            0x007a
>+#define mmMP0_SMN_C2PMSG_58_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_59                                                                            0x007b
>+#define mmMP0_SMN_C2PMSG_59_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_60                                                                            0x007c
>+#define mmMP0_SMN_C2PMSG_60_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_61                                                                            0x007d
>+#define mmMP0_SMN_C2PMSG_61_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_62                                                                            0x007e
>+#define mmMP0_SMN_C2PMSG_62_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_63                                                                            0x007f
>+#define mmMP0_SMN_C2PMSG_63_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_64                                                                            0x0080
>+#define mmMP0_SMN_C2PMSG_64_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_65                                                                            0x0081
>+#define mmMP0_SMN_C2PMSG_65_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_66                                                                            0x0082
>+#define mmMP0_SMN_C2PMSG_66_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_67                                                                            0x0083
>+#define mmMP0_SMN_C2PMSG_67_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_68                                                                            0x0084
>+#define mmMP0_SMN_C2PMSG_68_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_69                                                                            0x0085
>+#define mmMP0_SMN_C2PMSG_69_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_70                                                                            0x0086
>+#define mmMP0_SMN_C2PMSG_70_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_71                                                                            0x0087
>+#define mmMP0_SMN_C2PMSG_71_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_72                                                                            0x0088
>+#define mmMP0_SMN_C2PMSG_72_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_73                                                                            0x0089
>+#define mmMP0_SMN_C2PMSG_73_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_74                                                                            0x008a
>+#define mmMP0_SMN_C2PMSG_74_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_75                                                                            0x008b
>+#define mmMP0_SMN_C2PMSG_75_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_76                                                                            0x008c
>+#define mmMP0_SMN_C2PMSG_76_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_77                                                                            0x008d
>+#define mmMP0_SMN_C2PMSG_77_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_78                                                                            0x008e
>+#define mmMP0_SMN_C2PMSG_78_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_79                                                                            0x008f
>+#define mmMP0_SMN_C2PMSG_79_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_80                                                                            0x0090
>+#define mmMP0_SMN_C2PMSG_80_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_81                                                                            0x0091
>+#define mmMP0_SMN_C2PMSG_81_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_82                                                                            0x0092
>+#define mmMP0_SMN_C2PMSG_82_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_83                                                                            0x0093
>+#define mmMP0_SMN_C2PMSG_83_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_84                                                                            0x0094
>+#define mmMP0_SMN_C2PMSG_84_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_85                                                                            0x0095
>+#define mmMP0_SMN_C2PMSG_85_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_86                                                                            0x0096
>+#define mmMP0_SMN_C2PMSG_86_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_87                                                                            0x0097
>+#define mmMP0_SMN_C2PMSG_87_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_88                                                                            0x0098
>+#define mmMP0_SMN_C2PMSG_88_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_89                                                                            0x0099
>+#define mmMP0_SMN_C2PMSG_89_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_90                                                                            0x009a
>+#define mmMP0_SMN_C2PMSG_90_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_91                                                                            0x009b
>+#define mmMP0_SMN_C2PMSG_91_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_92                                                                            0x009c
>+#define mmMP0_SMN_C2PMSG_92_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_93                                                                            0x009d
>+#define mmMP0_SMN_C2PMSG_93_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_94                                                                            0x009e
>+#define mmMP0_SMN_C2PMSG_94_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_95                                                                            0x009f
>+#define mmMP0_SMN_C2PMSG_95_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_96                                                                            0x00a0
>+#define mmMP0_SMN_C2PMSG_96_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_97                                                                            0x00a1
>+#define mmMP0_SMN_C2PMSG_97_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_98                                                                            0x00a2
>+#define mmMP0_SMN_C2PMSG_98_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_99                                                                            0x00a3
>+#define mmMP0_SMN_C2PMSG_99_BASE_IDX                                                                   0
>+#define mmMP0_SMN_C2PMSG_100                                                                           0x00a4
>+#define mmMP0_SMN_C2PMSG_100_BASE_IDX                                                                  0
>+#define mmMP0_SMN_C2PMSG_101                                                                           0x00a5
>+#define mmMP0_SMN_C2PMSG_101_BASE_IDX                                                                  0
>+#define mmMP0_SMN_C2PMSG_102                                                                           0x00a6
>+#define mmMP0_SMN_C2PMSG_102_BASE_IDX                                                                  0
>+#define mmMP0_SMN_C2PMSG_103                                                                           0x00a7
>+#define mmMP0_SMN_C2PMSG_103_BASE_IDX                                                                  0
>+#define mmMP0_SMN_IH_CREDIT                                                                            0x00c1
>+#define mmMP0_SMN_IH_CREDIT_BASE_IDX                                                                   0
>+#define mmMP0_SMN_IH_SW_INT                                                                            0x00c2
>+#define mmMP0_SMN_IH_SW_INT_BASE_IDX                                                                   0
>+#define mmMP0_SMN_IH_SW_INT_CTRL                                                                       0x00c3
>+#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
>+
>+
>+// addressBlock: mp_SmuMp1_SmnDec
>+// base address: 0x0
>+#define mmMP1_SMN_C2PMSG_32                                                                            0x0260
>+#define mmMP1_SMN_C2PMSG_32_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_33                                                                            0x0261
>+#define mmMP1_SMN_C2PMSG_33_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_34                                                                            0x0262
>+#define mmMP1_SMN_C2PMSG_34_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_35                                                                            0x0263
>+#define mmMP1_SMN_C2PMSG_35_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_36                                                                            0x0264
>+#define mmMP1_SMN_C2PMSG_36_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_37                                                                            0x0265
>+#define mmMP1_SMN_C2PMSG_37_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_38                                                                            0x0266
>+#define mmMP1_SMN_C2PMSG_38_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_39                                                                            0x0267
>+#define mmMP1_SMN_C2PMSG_39_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_40                                                                            0x0268
>+#define mmMP1_SMN_C2PMSG_40_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_41                                                                            0x0269
>+#define mmMP1_SMN_C2PMSG_41_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_42                                                                            0x026a
>+#define mmMP1_SMN_C2PMSG_42_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_43                                                                            0x026b
>+#define mmMP1_SMN_C2PMSG_43_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_44                                                                            0x026c
>+#define mmMP1_SMN_C2PMSG_44_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_45                                                                            0x026d
>+#define mmMP1_SMN_C2PMSG_45_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_46                                                                            0x026e
>+#define mmMP1_SMN_C2PMSG_46_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_47                                                                            0x026f
>+#define mmMP1_SMN_C2PMSG_47_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_48                                                                            0x0270
>+#define mmMP1_SMN_C2PMSG_48_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_49                                                                            0x0271
>+#define mmMP1_SMN_C2PMSG_49_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_50                                                                            0x0272
>+#define mmMP1_SMN_C2PMSG_50_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_51                                                                            0x0273
>+#define mmMP1_SMN_C2PMSG_51_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_52                                                                            0x0274
>+#define mmMP1_SMN_C2PMSG_52_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_53                                                                            0x0275
>+#define mmMP1_SMN_C2PMSG_53_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_54                                                                            0x0276
>+#define mmMP1_SMN_C2PMSG_54_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_55                                                                            0x0277
>+#define mmMP1_SMN_C2PMSG_55_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_56                                                                            0x0278
>+#define mmMP1_SMN_C2PMSG_56_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_57                                                                            0x0279
>+#define mmMP1_SMN_C2PMSG_57_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_58                                                                            0x027a
>+#define mmMP1_SMN_C2PMSG_58_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_59                                                                            0x027b
>+#define mmMP1_SMN_C2PMSG_59_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_60                                                                            0x027c
>+#define mmMP1_SMN_C2PMSG_60_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_61                                                                            0x027d
>+#define mmMP1_SMN_C2PMSG_61_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_62                                                                            0x027e
>+#define mmMP1_SMN_C2PMSG_62_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_63                                                                            0x027f
>+#define mmMP1_SMN_C2PMSG_63_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_64                                                                            0x0280
>+#define mmMP1_SMN_C2PMSG_64_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_65                                                                            0x0281
>+#define mmMP1_SMN_C2PMSG_65_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_66                                                                            0x0282
>+#define mmMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_67                                                                            0x0283
>+#define mmMP1_SMN_C2PMSG_67_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_68                                                                            0x0284
>+#define mmMP1_SMN_C2PMSG_68_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_69                                                                            0x0285
>+#define mmMP1_SMN_C2PMSG_69_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_70                                                                            0x0286
>+#define mmMP1_SMN_C2PMSG_70_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_71                                                                            0x0287
>+#define mmMP1_SMN_C2PMSG_71_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_72                                                                            0x0288
>+#define mmMP1_SMN_C2PMSG_72_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_73                                                                            0x0289
>+#define mmMP1_SMN_C2PMSG_73_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_74                                                                            0x028a
>+#define mmMP1_SMN_C2PMSG_74_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_75                                                                            0x028b
>+#define mmMP1_SMN_C2PMSG_75_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_76                                                                            0x028c
>+#define mmMP1_SMN_C2PMSG_76_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_77                                                                            0x028d
>+#define mmMP1_SMN_C2PMSG_77_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_78                                                                            0x028e
>+#define mmMP1_SMN_C2PMSG_78_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_79                                                                            0x028f
>+#define mmMP1_SMN_C2PMSG_79_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_80                                                                            0x0290
>+#define mmMP1_SMN_C2PMSG_80_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_81                                                                            0x0291
>+#define mmMP1_SMN_C2PMSG_81_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_82                                                                            0x0292
>+#define mmMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_83                                                                            0x0293
>+#define mmMP1_SMN_C2PMSG_83_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_84                                                                            0x0294
>+#define mmMP1_SMN_C2PMSG_84_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_85                                                                            0x0295
>+#define mmMP1_SMN_C2PMSG_85_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_86                                                                            0x0296
>+#define mmMP1_SMN_C2PMSG_86_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_87                                                                            0x0297
>+#define mmMP1_SMN_C2PMSG_87_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_88                                                                            0x0298
>+#define mmMP1_SMN_C2PMSG_88_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_89                                                                            0x0299
>+#define mmMP1_SMN_C2PMSG_89_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_90                                                                            0x029a
>+#define mmMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_91                                                                            0x029b
>+#define mmMP1_SMN_C2PMSG_91_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_92                                                                            0x029c
>+#define mmMP1_SMN_C2PMSG_92_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_93                                                                            0x029d
>+#define mmMP1_SMN_C2PMSG_93_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_94                                                                            0x029e
>+#define mmMP1_SMN_C2PMSG_94_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_95                                                                            0x029f
>+#define mmMP1_SMN_C2PMSG_95_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_96                                                                            0x02a0
>+#define mmMP1_SMN_C2PMSG_96_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_97                                                                            0x02a1
>+#define mmMP1_SMN_C2PMSG_97_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_98                                                                            0x02a2
>+#define mmMP1_SMN_C2PMSG_98_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_99                                                                            0x02a3
>+#define mmMP1_SMN_C2PMSG_99_BASE_IDX                                                                   0
>+#define mmMP1_SMN_C2PMSG_100                                                                           0x02a4
>+#define mmMP1_SMN_C2PMSG_100_BASE_IDX                                                                  0
>+#define mmMP1_SMN_C2PMSG_101                                                                           0x02a5
>+#define mmMP1_SMN_C2PMSG_101_BASE_IDX                                                                  0
>+#define mmMP1_SMN_C2PMSG_102                                                                           0x02a6
>+#define mmMP1_SMN_C2PMSG_102_BASE_IDX                                                                  0
>+#define mmMP1_SMN_C2PMSG_103                                                                           0x02a7
>+#define mmMP1_SMN_C2PMSG_103_BASE_IDX                                                                  0
>+#define mmMP1_SMN_IH_CREDIT                                                                            0x02c1
>+#define mmMP1_SMN_IH_CREDIT_BASE_IDX                                                                   0
>+#define mmMP1_SMN_IH_SW_INT                                                                            0x02c2
>+#define mmMP1_SMN_IH_SW_INT_BASE_IDX                                                                   0
>+#define mmMP1_SMN_IH_SW_INT_CTRL                                                                       0x02c3
>+#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
>+#define mmMP1_SMN_FPS_CNT                                                                              0x02c4
>+#define mmMP1_SMN_FPS_CNT_BASE_IDX                                                                     0
>+
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/mp/mp_12_0_0_sh_mask.h	2019-08-31 15:01:11.909736173 -0500
>@@ -0,0 +1,866 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _mp_12_0_0_SH_MASK_HEADER
>+#define _mp_12_0_0_SH_MASK_HEADER
>+
>+
>+// addressBlock: mp_SmuMp0_SmnDec
>+//MP0_SMN_C2PMSG_32
>+#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_33
>+#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_34
>+#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_35
>+#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_36
>+#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_37
>+#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_38
>+#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_39
>+#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_40
>+#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_41
>+#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_42
>+#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_43
>+#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_44
>+#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_45
>+#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_46
>+#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_47
>+#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_48
>+#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_49
>+#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_50
>+#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_51
>+#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_52
>+#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_53
>+#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_54
>+#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_55
>+#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_56
>+#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_57
>+#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_58
>+#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_59
>+#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_60
>+#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_61
>+#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_62
>+#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_63
>+#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_64
>+#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_65
>+#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_66
>+#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_67
>+#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_68
>+#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_69
>+#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_70
>+#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_71
>+#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_72
>+#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_73
>+#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_74
>+#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_75
>+#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_76
>+#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_77
>+#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_78
>+#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_79
>+#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_80
>+#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_81
>+#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_82
>+#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_83
>+#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_84
>+#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_85
>+#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_86
>+#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_87
>+#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_88
>+#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_89
>+#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_90
>+#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_91
>+#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_92
>+#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_93
>+#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_94
>+#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_95
>+#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_96
>+#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_97
>+#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_98
>+#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_99
>+#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
>+#define MP0_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_100
>+#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
>+#define MP0_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_101
>+#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
>+#define MP0_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_102
>+#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
>+#define MP0_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
>+//MP0_SMN_C2PMSG_103
>+#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
>+#define MP0_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
>+//MP0_SMN_IH_CREDIT
>+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
>+#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
>+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
>+#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
>+//MP0_SMN_IH_SW_INT
>+#define MP0_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
>+#define MP0_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
>+#define MP0_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
>+#define MP0_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
>+
>+
>+// addressBlock: mp_SmuMp1_SmnDec
>+//MP1_SMN_C2PMSG_32
>+#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_33
>+#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_34
>+#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_35
>+#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_36
>+#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_37
>+#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_38
>+#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_39
>+#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_40
>+#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_41
>+#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_42
>+#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_43
>+#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_44
>+#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_45
>+#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_46
>+#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_47
>+#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_48
>+#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_49
>+#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_50
>+#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_51
>+#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_52
>+#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_53
>+#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_54
>+#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_55
>+#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_56
>+#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_57
>+#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_58
>+#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_59
>+#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_60
>+#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_61
>+#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_62
>+#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_63
>+#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_64
>+#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_65
>+#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_66
>+#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_67
>+#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_68
>+#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_69
>+#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_70
>+#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_71
>+#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_72
>+#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_73
>+#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_74
>+#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_75
>+#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_76
>+#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_77
>+#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_78
>+#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_79
>+#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_80
>+#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_81
>+#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_82
>+#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_83
>+#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_84
>+#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_85
>+#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_86
>+#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_87
>+#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_88
>+#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_89
>+#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_90
>+#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_91
>+#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_92
>+#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_93
>+#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_94
>+#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_95
>+#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_96
>+#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_97
>+#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_98
>+#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_99
>+#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
>+#define MP1_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_100
>+#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
>+#define MP1_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_101
>+#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
>+#define MP1_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_102
>+#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
>+#define MP1_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
>+//MP1_SMN_C2PMSG_103
>+#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
>+#define MP1_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
>+//MP1_SMN_IH_CREDIT
>+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
>+#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
>+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
>+#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
>+//MP1_SMN_IH_SW_INT
>+#define MP1_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
>+#define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
>+#define MP1_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
>+#define MP1_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
>+//MP1_SMN_FPS_CNT
>+#define MP1_SMN_FPS_CNT__COUNT__SHIFT                                                                         0x0
>+#define MP1_SMN_FPS_CNT__COUNT_MASK                                                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: mp_SmuMp0Pub_CruDec
>+//MP0_IH_CREDIT
>+#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                    0x0
>+#define MP0_IH_CREDIT__CLIENT_ID__SHIFT                                                                       0x10
>+#define MP0_IH_CREDIT__CREDIT_VALUE_MASK                                                                      0x00000003L
>+#define MP0_IH_CREDIT__CLIENT_ID_MASK                                                                         0x00FF0000L
>+//MP0_IH_SW_INT
>+#define MP0_IH_SW_INT__ID__SHIFT                                                                              0x0
>+#define MP0_IH_SW_INT__VALID__SHIFT                                                                           0x8
>+#define MP0_IH_SW_INT__ID_MASK                                                                                0x000000FFL
>+#define MP0_IH_SW_INT__VALID_MASK                                                                             0x00000100L
>+//MP0_IH_SW_INT_CTRL
>+#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                                   0x0
>+#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                    0x8
>+#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK                                                                     0x00000001L
>+#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK                                                                      0x00000100L
>+
>+
>+// addressBlock: mp_SmuMp1Pub_CruDec
>+//MP1_FIRMWARE_FLAGS
>+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT                                                         0x0
>+#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT                                                                   0x1
>+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK                                                           0x00000001L
>+#define MP1_FIRMWARE_FLAGS__RESERVED_MASK                                                                     0xFFFFFFFEL
>+//MP1_C2PMSG_0
>+#define MP1_C2PMSG_0__CONTENT__SHIFT                                                                          0x0
>+#define MP1_C2PMSG_0__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_C2PMSG_1
>+#define MP1_C2PMSG_1__CONTENT__SHIFT                                                                          0x0
>+#define MP1_C2PMSG_1__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_C2PMSG_2
>+#define MP1_C2PMSG_2__CONTENT__SHIFT                                                                          0x0
>+#define MP1_C2PMSG_2__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_C2PMSG_3
>+#define MP1_C2PMSG_3__CONTENT__SHIFT                                                                          0x0
>+#define MP1_C2PMSG_3__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_C2PMSG_4
>+#define MP1_C2PMSG_4__CONTENT__SHIFT                                                                          0x0
>+#define MP1_C2PMSG_4__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_C2PMSG_5
>+#define MP1_C2PMSG_5__CONTENT__SHIFT                                                                          0x0
>+#define MP1_C2PMSG_5__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_C2PMSG_6
>+#define MP1_C2PMSG_6__CONTENT__SHIFT                                                                          0x0
>+#define MP1_C2PMSG_6__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_C2PMSG_7
>+#define MP1_C2PMSG_7__CONTENT__SHIFT                                                                          0x0
>+#define MP1_C2PMSG_7__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_C2PMSG_8
>+#define MP1_C2PMSG_8__CONTENT__SHIFT                                                                          0x0
>+#define MP1_C2PMSG_8__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_C2PMSG_9
>+#define MP1_C2PMSG_9__CONTENT__SHIFT                                                                          0x0
>+#define MP1_C2PMSG_9__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_C2PMSG_10
>+#define MP1_C2PMSG_10__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_10__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_11
>+#define MP1_C2PMSG_11__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_11__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_12
>+#define MP1_C2PMSG_12__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_12__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_13
>+#define MP1_C2PMSG_13__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_13__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_14
>+#define MP1_C2PMSG_14__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_14__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_15
>+#define MP1_C2PMSG_15__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_15__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_16
>+#define MP1_C2PMSG_16__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_16__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_17
>+#define MP1_C2PMSG_17__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_17__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_18
>+#define MP1_C2PMSG_18__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_18__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_19
>+#define MP1_C2PMSG_19__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_19__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_20
>+#define MP1_C2PMSG_20__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_20__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_21
>+#define MP1_C2PMSG_21__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_21__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_22
>+#define MP1_C2PMSG_22__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_22__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_23
>+#define MP1_C2PMSG_23__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_23__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_24
>+#define MP1_C2PMSG_24__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_24__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_25
>+#define MP1_C2PMSG_25__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_25__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_26
>+#define MP1_C2PMSG_26__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_26__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_27
>+#define MP1_C2PMSG_27__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_27__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_28
>+#define MP1_C2PMSG_28__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_28__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_29
>+#define MP1_C2PMSG_29__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_29__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_30
>+#define MP1_C2PMSG_30__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_30__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_31
>+#define MP1_C2PMSG_31__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_31__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_P2CMSG_0
>+#define MP1_P2CMSG_0__CONTENT__SHIFT                                                                          0x0
>+#define MP1_P2CMSG_0__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_P2CMSG_1
>+#define MP1_P2CMSG_1__CONTENT__SHIFT                                                                          0x0
>+#define MP1_P2CMSG_1__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_P2CMSG_2
>+#define MP1_P2CMSG_2__CONTENT__SHIFT                                                                          0x0
>+#define MP1_P2CMSG_2__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_P2CMSG_3
>+#define MP1_P2CMSG_3__CONTENT__SHIFT                                                                          0x0
>+#define MP1_P2CMSG_3__CONTENT_MASK                                                                            0xFFFFFFFFL
>+//MP1_P2CMSG_INTEN
>+#define MP1_P2CMSG_INTEN__INTEN__SHIFT                                                                        0x0
>+#define MP1_P2CMSG_INTEN__INTEN_MASK                                                                          0x0000000FL
>+//MP1_P2CMSG_INTSTS
>+#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT                                                                     0x0
>+#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT                                                                     0x1
>+#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT                                                                     0x2
>+#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT                                                                     0x3
>+#define MP1_P2CMSG_INTSTS__INTSTS0_MASK                                                                       0x00000001L
>+#define MP1_P2CMSG_INTSTS__INTSTS1_MASK                                                                       0x00000002L
>+#define MP1_P2CMSG_INTSTS__INTSTS2_MASK                                                                       0x00000004L
>+#define MP1_P2CMSG_INTSTS__INTSTS3_MASK                                                                       0x00000008L
>+//MP1_C2PMSG_32
>+#define MP1_C2PMSG_32__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_32__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_33
>+#define MP1_C2PMSG_33__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_33__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_34
>+#define MP1_C2PMSG_34__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_34__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_35
>+#define MP1_C2PMSG_35__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_35__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_36
>+#define MP1_C2PMSG_36__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_36__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_37
>+#define MP1_C2PMSG_37__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_37__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_38
>+#define MP1_C2PMSG_38__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_38__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_39
>+#define MP1_C2PMSG_39__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_39__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_40
>+#define MP1_C2PMSG_40__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_40__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_41
>+#define MP1_C2PMSG_41__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_41__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_42
>+#define MP1_C2PMSG_42__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_42__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_43
>+#define MP1_C2PMSG_43__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_43__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_44
>+#define MP1_C2PMSG_44__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_44__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_45
>+#define MP1_C2PMSG_45__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_45__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_46
>+#define MP1_C2PMSG_46__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_46__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_47
>+#define MP1_C2PMSG_47__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_47__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_48
>+#define MP1_C2PMSG_48__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_48__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_49
>+#define MP1_C2PMSG_49__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_49__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_50
>+#define MP1_C2PMSG_50__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_50__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_51
>+#define MP1_C2PMSG_51__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_51__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_52
>+#define MP1_C2PMSG_52__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_52__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_53
>+#define MP1_C2PMSG_53__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_53__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_54
>+#define MP1_C2PMSG_54__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_54__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_55
>+#define MP1_C2PMSG_55__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_55__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_56
>+#define MP1_C2PMSG_56__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_56__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_57
>+#define MP1_C2PMSG_57__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_57__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_58
>+#define MP1_C2PMSG_58__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_58__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_59
>+#define MP1_C2PMSG_59__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_59__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_60
>+#define MP1_C2PMSG_60__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_60__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_61
>+#define MP1_C2PMSG_61__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_61__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_62
>+#define MP1_C2PMSG_62__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_62__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_63
>+#define MP1_C2PMSG_63__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_63__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_64
>+#define MP1_C2PMSG_64__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_64__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_65
>+#define MP1_C2PMSG_65__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_65__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_66
>+#define MP1_C2PMSG_66__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_66__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_67
>+#define MP1_C2PMSG_67__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_67__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_68
>+#define MP1_C2PMSG_68__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_68__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_69
>+#define MP1_C2PMSG_69__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_69__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_70
>+#define MP1_C2PMSG_70__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_70__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_71
>+#define MP1_C2PMSG_71__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_71__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_72
>+#define MP1_C2PMSG_72__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_72__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_73
>+#define MP1_C2PMSG_73__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_73__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_74
>+#define MP1_C2PMSG_74__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_74__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_75
>+#define MP1_C2PMSG_75__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_75__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_76
>+#define MP1_C2PMSG_76__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_76__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_77
>+#define MP1_C2PMSG_77__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_77__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_78
>+#define MP1_C2PMSG_78__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_78__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_79
>+#define MP1_C2PMSG_79__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_79__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_80
>+#define MP1_C2PMSG_80__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_80__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_81
>+#define MP1_C2PMSG_81__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_81__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_82
>+#define MP1_C2PMSG_82__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_82__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_83
>+#define MP1_C2PMSG_83__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_83__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_84
>+#define MP1_C2PMSG_84__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_84__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_85
>+#define MP1_C2PMSG_85__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_85__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_86
>+#define MP1_C2PMSG_86__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_86__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_87
>+#define MP1_C2PMSG_87__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_87__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_88
>+#define MP1_C2PMSG_88__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_88__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_89
>+#define MP1_C2PMSG_89__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_89__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_90
>+#define MP1_C2PMSG_90__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_90__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_91
>+#define MP1_C2PMSG_91__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_91__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_92
>+#define MP1_C2PMSG_92__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_92__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_93
>+#define MP1_C2PMSG_93__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_93__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_94
>+#define MP1_C2PMSG_94__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_94__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_95
>+#define MP1_C2PMSG_95__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_95__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_96
>+#define MP1_C2PMSG_96__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_96__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_97
>+#define MP1_C2PMSG_97__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_97__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_98
>+#define MP1_C2PMSG_98__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_98__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_99
>+#define MP1_C2PMSG_99__CONTENT__SHIFT                                                                         0x0
>+#define MP1_C2PMSG_99__CONTENT_MASK                                                                           0xFFFFFFFFL
>+//MP1_C2PMSG_100
>+#define MP1_C2PMSG_100__CONTENT__SHIFT                                                                        0x0
>+#define MP1_C2PMSG_100__CONTENT_MASK                                                                          0xFFFFFFFFL
>+//MP1_C2PMSG_101
>+#define MP1_C2PMSG_101__CONTENT__SHIFT                                                                        0x0
>+#define MP1_C2PMSG_101__CONTENT_MASK                                                                          0xFFFFFFFFL
>+//MP1_C2PMSG_102
>+#define MP1_C2PMSG_102__CONTENT__SHIFT                                                                        0x0
>+#define MP1_C2PMSG_102__CONTENT_MASK                                                                          0xFFFFFFFFL
>+//MP1_C2PMSG_103
>+#define MP1_C2PMSG_103__CONTENT__SHIFT                                                                        0x0
>+#define MP1_C2PMSG_103__CONTENT_MASK                                                                          0xFFFFFFFFL
>+//MP1_IH_CREDIT
>+#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                    0x0
>+#define MP1_IH_CREDIT__CLIENT_ID__SHIFT                                                                       0x10
>+#define MP1_IH_CREDIT__CREDIT_VALUE_MASK                                                                      0x00000003L
>+#define MP1_IH_CREDIT__CLIENT_ID_MASK                                                                         0x00FF0000L
>+//MP1_IH_SW_INT
>+#define MP1_IH_SW_INT__ID__SHIFT                                                                              0x0
>+#define MP1_IH_SW_INT__VALID__SHIFT                                                                           0x8
>+#define MP1_IH_SW_INT__ID_MASK                                                                                0x000000FFL
>+#define MP1_IH_SW_INT__VALID_MASK                                                                             0x00000100L
>+//MP1_IH_SW_INT_CTRL
>+#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                                   0x0
>+#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                    0x8
>+#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK                                                                     0x00000001L
>+#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK                                                                      0x00000100L
>+//MP1_FPS_CNT
>+#define MP1_FPS_CNT__COUNT__SHIFT                                                                             0x0
>+#define MP1_FPS_CNT__COUNT_MASK                                                                               0xFFFFFFFFL
>+
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h	2019-08-31 15:01:11.929736174 -0500
>@@ -74709,6 +74709,36 @@
> //PCIE_PERF_COUNT1_TXCLK2
> #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT                                                              0x0
> #define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK                                                                0xFFFFFFFFL
>+//PCIE_PERF_CNTL_TXCLK3
>+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT                                                              0x0
>+#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT                                                              0x8
>+#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER__SHIFT                                                          0x10
>+#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER__SHIFT                                                          0x18
>+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK                                                                0x000000FFL
>+#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK                                                                0x0000FF00L
>+#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER_MASK                                                            0x00FF0000L
>+#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER_MASK                                                            0xFF000000L
>+//PCIE_PERF_COUNT0_TXCLK3
>+#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT                                                              0x0
>+#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK                                                                0xFFFFFFFFL
>+//PCIE_PERF_COUNT1_TXCLK3
>+#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT                                                              0x0
>+#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK                                                                0xFFFFFFFFL
>+//PCIE_PERF_CNTL_TXCLK4
>+#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT                                                              0x0
>+#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT                                                              0x8
>+#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER__SHIFT                                                          0x10
>+#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER__SHIFT                                                          0x18
>+#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK                                                                0x000000FFL
>+#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK                                                                0x0000FF00L
>+#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER_MASK                                                            0x00FF0000L
>+#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER_MASK                                                            0xFF000000L
>+//PCIE_PERF_COUNT0_TXCLK4
>+#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT                                                              0x0
>+#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK                                                                0xFFFFFFFFL
>+//PCIE_PERF_COUNT1_TXCLK4
>+#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT                                                              0x0
>+#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK                                                                0xFFFFFFFFL
> //PCIE_PRBS_CLR
> #define PCIE_PRBS_CLR__PRBS_CLR__SHIFT                                                                        0x0
> #define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT                                                                0x18
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h	2019-08-31 15:01:11.929736174 -0500
>@@ -50,6 +50,12 @@
> #define smnPCIE_PERF_CNTL_TXCLK2			0x11180254
> #define smnPCIE_PERF_COUNT0_TXCLK2			0x11180258
> #define smnPCIE_PERF_COUNT1_TXCLK2			0x1118025c
>+#define smnPCIE_PERF_CNTL_TXCLK3                        0x1118021c
>+#define smnPCIE_PERF_COUNT0_TXCLK3                      0x11180220
>+#define smnPCIE_PERF_COUNT1_TXCLK3                      0x11180224
>+#define smnPCIE_PERF_CNTL_TXCLK4                        0x11180228
>+#define smnPCIE_PERF_COUNT0_TXCLK4                      0x1118022c
>+#define smnPCIE_PERF_COUNT1_TXCLK4                      0x11180230
> 
> #define smnPCIE_RX_NUM_NAK				0x11180038
> #define smnPCIE_RX_NUM_NAK_GENERATED			0x1118003c
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_4_0_sh_mask.h	2019-08-31 15:01:11.929736174 -0500
>@@ -1109,7 +1109,11 @@
> #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK                                                               0x00FF0000L
> //IH_CHICKEN
> #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT                                                          0x0
>+#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT                                                               0x3
>+#define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT                                                                0x4
> #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK                                                            0x00000001L
>+#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK                                                                 0x00000008L
>+#define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK                                                                  0x00000010L
> //IH_MMHUB_CNTL
> #define IH_MMHUB_CNTL__UNITID__SHIFT                                                                          0x0
> #define IH_MMHUB_CNTL__IV_TLVL__SHIFT                                                                         0x8
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_offset.h	2019-08-31 15:01:11.930736175 -0500
>@@ -0,0 +1,27 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _rsmu_0_0_2_OFFSET_HEADER
>+#define _rsmu_0_0_2_OFFSET_HEADER
>+
>+#define	mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU								0x0d91
>+#define	mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU_BASE_IDX						0
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/rsmu/rsmu_0_0_2_sh_mask.h	2019-08-31 15:01:11.930736175 -0500
>@@ -0,0 +1,32 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _rsmu_0_0_2_SH_MASK_HEADER
>+#define _rsmu_0_0_2_SH_MASK_HEADER
>+
>+//RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU
>+#define	RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_WREN__SHIFT				0x0
>+#define	RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_INSTANCE__SHIFT				0x10
>+#define	RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_MODE_EN__SHIFT				0x1f
>+#define	RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_WREN_MASK					0x0000FFFFL
>+#define	RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_INSTANCE_MASK				0x000F0000L
>+#define	RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_MODE_EN_MASK				0x80000000L
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_offset.h	2019-08-31 15:01:11.930736175 -0500
>@@ -0,0 +1,1051 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma0_4_2_2_OFFSET_HEADER
>+#define _sdma0_4_2_2_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: sdma0_sdma0dec
>+// base address: 0x4980
>+#define mmSDMA0_UCODE_ADDR                                                                             0x0000
>+#define mmSDMA0_UCODE_ADDR_BASE_IDX                                                                    0
>+#define mmSDMA0_UCODE_DATA                                                                             0x0001
>+#define mmSDMA0_UCODE_DATA_BASE_IDX                                                                    0
>+#define mmSDMA0_VM_CNTL                                                                                0x0004
>+#define mmSDMA0_VM_CNTL_BASE_IDX                                                                       0
>+#define mmSDMA0_VM_CTX_LO                                                                              0x0005
>+#define mmSDMA0_VM_CTX_LO_BASE_IDX                                                                     0
>+#define mmSDMA0_VM_CTX_HI                                                                              0x0006
>+#define mmSDMA0_VM_CTX_HI_BASE_IDX                                                                     0
>+#define mmSDMA0_ACTIVE_FCN_ID                                                                          0x0007
>+#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX                                                                 0
>+#define mmSDMA0_VM_CTX_CNTL                                                                            0x0008
>+#define mmSDMA0_VM_CTX_CNTL_BASE_IDX                                                                   0
>+#define mmSDMA0_VIRT_RESET_REQ                                                                         0x0009
>+#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX                                                                0
>+#define mmSDMA0_VF_ENABLE                                                                              0x000a
>+#define mmSDMA0_VF_ENABLE_BASE_IDX                                                                     0
>+#define mmSDMA0_CONTEXT_REG_TYPE0                                                                      0x000b
>+#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX                                                             0
>+#define mmSDMA0_CONTEXT_REG_TYPE1                                                                      0x000c
>+#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX                                                             0
>+#define mmSDMA0_CONTEXT_REG_TYPE2                                                                      0x000d
>+#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX                                                             0
>+#define mmSDMA0_CONTEXT_REG_TYPE3                                                                      0x000e
>+#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX                                                             0
>+#define mmSDMA0_PUB_REG_TYPE0                                                                          0x000f
>+#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX                                                                 0
>+#define mmSDMA0_PUB_REG_TYPE1                                                                          0x0010
>+#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX                                                                 0
>+#define mmSDMA0_PUB_REG_TYPE2                                                                          0x0011
>+#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX                                                                 0
>+#define mmSDMA0_PUB_REG_TYPE3                                                                          0x0012
>+#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX                                                                 0
>+#define mmSDMA0_MMHUB_CNTL                                                                             0x0013
>+#define mmSDMA0_MMHUB_CNTL_BASE_IDX                                                                    0
>+#define mmSDMA0_CONTEXT_GROUP_BOUNDARY                                                                 0x0019
>+#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX                                                        0
>+#define mmSDMA0_POWER_CNTL                                                                             0x001a
>+#define mmSDMA0_POWER_CNTL_BASE_IDX                                                                    0
>+#define mmSDMA0_CLK_CTRL                                                                               0x001b
>+#define mmSDMA0_CLK_CTRL_BASE_IDX                                                                      0
>+#define mmSDMA0_CNTL                                                                                   0x001c
>+#define mmSDMA0_CNTL_BASE_IDX                                                                          0
>+#define mmSDMA0_CHICKEN_BITS                                                                           0x001d
>+#define mmSDMA0_CHICKEN_BITS_BASE_IDX                                                                  0
>+#define mmSDMA0_GB_ADDR_CONFIG                                                                         0x001e
>+#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX                                                                0
>+#define mmSDMA0_GB_ADDR_CONFIG_READ                                                                    0x001f
>+#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX                                                           0
>+#define mmSDMA0_RB_RPTR_FETCH_HI                                                                       0x0020
>+#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX                                                              0
>+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0021
>+#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      0
>+#define mmSDMA0_RB_RPTR_FETCH                                                                          0x0022
>+#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX                                                                 0
>+#define mmSDMA0_IB_OFFSET_FETCH                                                                        0x0023
>+#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX                                                               0
>+#define mmSDMA0_PROGRAM                                                                                0x0024
>+#define mmSDMA0_PROGRAM_BASE_IDX                                                                       0
>+#define mmSDMA0_STATUS_REG                                                                             0x0025
>+#define mmSDMA0_STATUS_REG_BASE_IDX                                                                    0
>+#define mmSDMA0_STATUS1_REG                                                                            0x0026
>+#define mmSDMA0_STATUS1_REG_BASE_IDX                                                                   0
>+#define mmSDMA0_RD_BURST_CNTL                                                                          0x0027
>+#define mmSDMA0_RD_BURST_CNTL_BASE_IDX                                                                 0
>+#define mmSDMA0_HBM_PAGE_CONFIG                                                                        0x0028
>+#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX                                                               0
>+#define mmSDMA0_UCODE_CHECKSUM                                                                         0x0029
>+#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX                                                                0
>+#define mmSDMA0_F32_CNTL                                                                               0x002a
>+#define mmSDMA0_F32_CNTL_BASE_IDX                                                                      0
>+#define mmSDMA0_FREEZE                                                                                 0x002b
>+#define mmSDMA0_FREEZE_BASE_IDX                                                                        0
>+#define mmSDMA0_PHASE0_QUANTUM                                                                         0x002c
>+#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX                                                                0
>+#define mmSDMA0_PHASE1_QUANTUM                                                                         0x002d
>+#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX                                                                0
>+#define mmSDMA_POWER_GATING                                                                            0x002e
>+#define mmSDMA_POWER_GATING_BASE_IDX                                                                   0
>+#define mmSDMA_PGFSM_CONFIG                                                                            0x002f
>+#define mmSDMA_PGFSM_CONFIG_BASE_IDX                                                                   0
>+#define mmSDMA_PGFSM_WRITE                                                                             0x0030
>+#define mmSDMA_PGFSM_WRITE_BASE_IDX                                                                    0
>+#define mmSDMA_PGFSM_READ                                                                              0x0031
>+#define mmSDMA_PGFSM_READ_BASE_IDX                                                                     0
>+#define mmSDMA0_EDC_CONFIG                                                                             0x0032
>+#define mmSDMA0_EDC_CONFIG_BASE_IDX                                                                    0
>+#define mmSDMA0_BA_THRESHOLD                                                                           0x0033
>+#define mmSDMA0_BA_THRESHOLD_BASE_IDX                                                                  0
>+#define mmSDMA0_ID                                                                                     0x0034
>+#define mmSDMA0_ID_BASE_IDX                                                                            0
>+#define mmSDMA0_VERSION                                                                                0x0035
>+#define mmSDMA0_VERSION_BASE_IDX                                                                       0
>+#define mmSDMA0_EDC_COUNTER                                                                            0x0036
>+#define mmSDMA0_EDC_COUNTER_BASE_IDX                                                                   0
>+#define mmSDMA0_EDC_COUNTER_CLEAR                                                                      0x0037
>+#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX                                                             0
>+#define mmSDMA0_STATUS2_REG                                                                            0x0038
>+#define mmSDMA0_STATUS2_REG_BASE_IDX                                                                   0
>+#define mmSDMA0_ATOMIC_CNTL                                                                            0x0039
>+#define mmSDMA0_ATOMIC_CNTL_BASE_IDX                                                                   0
>+#define mmSDMA0_ATOMIC_PREOP_LO                                                                        0x003a
>+#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX                                                               0
>+#define mmSDMA0_ATOMIC_PREOP_HI                                                                        0x003b
>+#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX                                                               0
>+#define mmSDMA0_UTCL1_CNTL                                                                             0x003c
>+#define mmSDMA0_UTCL1_CNTL_BASE_IDX                                                                    0
>+#define mmSDMA0_UTCL1_WATERMK                                                                          0x003d
>+#define mmSDMA0_UTCL1_WATERMK_BASE_IDX                                                                 0
>+#define mmSDMA0_UTCL1_RD_STATUS                                                                        0x003e
>+#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX                                                               0
>+#define mmSDMA0_UTCL1_WR_STATUS                                                                        0x003f
>+#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX                                                               0
>+#define mmSDMA0_UTCL1_INV0                                                                             0x0040
>+#define mmSDMA0_UTCL1_INV0_BASE_IDX                                                                    0
>+#define mmSDMA0_UTCL1_INV1                                                                             0x0041
>+#define mmSDMA0_UTCL1_INV1_BASE_IDX                                                                    0
>+#define mmSDMA0_UTCL1_INV2                                                                             0x0042
>+#define mmSDMA0_UTCL1_INV2_BASE_IDX                                                                    0
>+#define mmSDMA0_UTCL1_RD_XNACK0                                                                        0x0043
>+#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX                                                               0
>+#define mmSDMA0_UTCL1_RD_XNACK1                                                                        0x0044
>+#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX                                                               0
>+#define mmSDMA0_UTCL1_WR_XNACK0                                                                        0x0045
>+#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX                                                               0
>+#define mmSDMA0_UTCL1_WR_XNACK1                                                                        0x0046
>+#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX                                                               0
>+#define mmSDMA0_UTCL1_TIMEOUT                                                                          0x0047
>+#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX                                                                 0
>+#define mmSDMA0_UTCL1_PAGE                                                                             0x0048
>+#define mmSDMA0_UTCL1_PAGE_BASE_IDX                                                                    0
>+#define mmSDMA0_POWER_CNTL_IDLE                                                                        0x0049
>+#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX                                                               0
>+#define mmSDMA0_RELAX_ORDERING_LUT                                                                     0x004a
>+#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX                                                            0
>+#define mmSDMA0_CHICKEN_BITS_2                                                                         0x004b
>+#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX                                                                0
>+#define mmSDMA0_STATUS3_REG                                                                            0x004c
>+#define mmSDMA0_STATUS3_REG_BASE_IDX                                                                   0
>+#define mmSDMA0_PHYSICAL_ADDR_LO                                                                       0x004d
>+#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA0_PHYSICAL_ADDR_HI                                                                       0x004e
>+#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA0_PHASE2_QUANTUM                                                                         0x004f
>+#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX                                                                0
>+#define mmSDMA0_ERROR_LOG                                                                              0x0050
>+#define mmSDMA0_ERROR_LOG_BASE_IDX                                                                     0
>+#define mmSDMA0_PUB_DUMMY_REG0                                                                         0x0051
>+#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX                                                                0
>+#define mmSDMA0_PUB_DUMMY_REG1                                                                         0x0052
>+#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX                                                                0
>+#define mmSDMA0_PUB_DUMMY_REG2                                                                         0x0053
>+#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX                                                                0
>+#define mmSDMA0_PUB_DUMMY_REG3                                                                         0x0054
>+#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX                                                                0
>+#define mmSDMA0_F32_COUNTER                                                                            0x0055
>+#define mmSDMA0_F32_COUNTER_BASE_IDX                                                                   0
>+#define mmSDMA0_UNBREAKABLE                                                                            0x0056
>+#define mmSDMA0_UNBREAKABLE_BASE_IDX                                                                   0
>+#define mmSDMA0_PERFMON_CNTL                                                                           0x0057
>+#define mmSDMA0_PERFMON_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_PERFCOUNTER0_RESULT                                                                    0x0058
>+#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX                                                           0
>+#define mmSDMA0_PERFCOUNTER1_RESULT                                                                    0x0059
>+#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX                                                           0
>+#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE                                                            0x005a
>+#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX                                                   0
>+#define mmSDMA0_CRD_CNTL                                                                               0x005b
>+#define mmSDMA0_CRD_CNTL_BASE_IDX                                                                      0
>+#define mmSDMA0_GPU_IOV_VIOLATION_LOG                                                                  0x005d
>+#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX                                                         0
>+#define mmSDMA0_ULV_CNTL                                                                               0x005e
>+#define mmSDMA0_ULV_CNTL_BASE_IDX                                                                      0
>+#define mmSDMA0_EA_DBIT_ADDR_DATA                                                                      0x0060
>+#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX                                                             0
>+#define mmSDMA0_EA_DBIT_ADDR_INDEX                                                                     0x0061
>+#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            0
>+#define mmSDMA0_GPU_IOV_VIOLATION_LOG2                                                                 0x0062
>+#define mmSDMA0_GPU_IOV_VIOLATION_LOG2_BASE_IDX                                                        0
>+#define mmSDMA0_GFX_RB_CNTL                                                                            0x0080
>+#define mmSDMA0_GFX_RB_CNTL_BASE_IDX                                                                   0
>+#define mmSDMA0_GFX_RB_BASE                                                                            0x0081
>+#define mmSDMA0_GFX_RB_BASE_BASE_IDX                                                                   0
>+#define mmSDMA0_GFX_RB_BASE_HI                                                                         0x0082
>+#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX                                                                0
>+#define mmSDMA0_GFX_RB_RPTR                                                                            0x0083
>+#define mmSDMA0_GFX_RB_RPTR_BASE_IDX                                                                   0
>+#define mmSDMA0_GFX_RB_RPTR_HI                                                                         0x0084
>+#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX                                                                0
>+#define mmSDMA0_GFX_RB_WPTR                                                                            0x0085
>+#define mmSDMA0_GFX_RB_WPTR_BASE_IDX                                                                   0
>+#define mmSDMA0_GFX_RB_WPTR_HI                                                                         0x0086
>+#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX                                                                0
>+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
>+#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
>+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI                                                                    0x0088
>+#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
>+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO                                                                    0x0089
>+#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
>+#define mmSDMA0_GFX_IB_CNTL                                                                            0x008a
>+#define mmSDMA0_GFX_IB_CNTL_BASE_IDX                                                                   0
>+#define mmSDMA0_GFX_IB_RPTR                                                                            0x008b
>+#define mmSDMA0_GFX_IB_RPTR_BASE_IDX                                                                   0
>+#define mmSDMA0_GFX_IB_OFFSET                                                                          0x008c
>+#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX                                                                 0
>+#define mmSDMA0_GFX_IB_BASE_LO                                                                         0x008d
>+#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX                                                                0
>+#define mmSDMA0_GFX_IB_BASE_HI                                                                         0x008e
>+#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX                                                                0
>+#define mmSDMA0_GFX_IB_SIZE                                                                            0x008f
>+#define mmSDMA0_GFX_IB_SIZE_BASE_IDX                                                                   0
>+#define mmSDMA0_GFX_SKIP_CNTL                                                                          0x0090
>+#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX                                                                 0
>+#define mmSDMA0_GFX_CONTEXT_STATUS                                                                     0x0091
>+#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX                                                            0
>+#define mmSDMA0_GFX_DOORBELL                                                                           0x0092
>+#define mmSDMA0_GFX_DOORBELL_BASE_IDX                                                                  0
>+#define mmSDMA0_GFX_CONTEXT_CNTL                                                                       0x0093
>+#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_GFX_STATUS                                                                             0x00a8
>+#define mmSDMA0_GFX_STATUS_BASE_IDX                                                                    0
>+#define mmSDMA0_GFX_DOORBELL_LOG                                                                       0x00a9
>+#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX                                                              0
>+#define mmSDMA0_GFX_WATERMARK                                                                          0x00aa
>+#define mmSDMA0_GFX_WATERMARK_BASE_IDX                                                                 0
>+#define mmSDMA0_GFX_DOORBELL_OFFSET                                                                    0x00ab
>+#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX                                                           0
>+#define mmSDMA0_GFX_CSA_ADDR_LO                                                                        0x00ac
>+#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX                                                               0
>+#define mmSDMA0_GFX_CSA_ADDR_HI                                                                        0x00ad
>+#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_GFX_IB_SUB_REMAIN                                                                      0x00af
>+#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX                                                             0
>+#define mmSDMA0_GFX_PREEMPT                                                                            0x00b0
>+#define mmSDMA0_GFX_PREEMPT_BASE_IDX                                                                   0
>+#define mmSDMA0_GFX_DUMMY_REG                                                                          0x00b1
>+#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX                                                                 0
>+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x00b2
>+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
>+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x00b3
>+#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
>+#define mmSDMA0_GFX_RB_AQL_CNTL                                                                        0x00b4
>+#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX                                                               0
>+#define mmSDMA0_GFX_MINOR_PTR_UPDATE                                                                   0x00b5
>+#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          0
>+#define mmSDMA0_GFX_MIDCMD_DATA0                                                                       0x00c0
>+#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX                                                              0
>+#define mmSDMA0_GFX_MIDCMD_DATA1                                                                       0x00c1
>+#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX                                                              0
>+#define mmSDMA0_GFX_MIDCMD_DATA2                                                                       0x00c2
>+#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX                                                              0
>+#define mmSDMA0_GFX_MIDCMD_DATA3                                                                       0x00c3
>+#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX                                                              0
>+#define mmSDMA0_GFX_MIDCMD_DATA4                                                                       0x00c4
>+#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX                                                              0
>+#define mmSDMA0_GFX_MIDCMD_DATA5                                                                       0x00c5
>+#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX                                                              0
>+#define mmSDMA0_GFX_MIDCMD_DATA6                                                                       0x00c6
>+#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX                                                              0
>+#define mmSDMA0_GFX_MIDCMD_DATA7                                                                       0x00c7
>+#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX                                                              0
>+#define mmSDMA0_GFX_MIDCMD_DATA8                                                                       0x00c8
>+#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX                                                              0
>+#define mmSDMA0_GFX_MIDCMD_CNTL                                                                        0x00c9
>+#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX                                                               0
>+#define mmSDMA0_PAGE_RB_CNTL                                                                           0x00d8
>+#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_PAGE_RB_BASE                                                                           0x00d9
>+#define mmSDMA0_PAGE_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA0_PAGE_RB_BASE_HI                                                                        0x00da
>+#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_PAGE_RB_RPTR                                                                           0x00db
>+#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_PAGE_RB_RPTR_HI                                                                        0x00dc
>+#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_PAGE_RB_WPTR                                                                           0x00dd
>+#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_PAGE_RB_WPTR_HI                                                                        0x00de
>+#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL                                                                 0x00df
>+#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI                                                                   0x00e0
>+#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO                                                                   0x00e1
>+#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA0_PAGE_IB_CNTL                                                                           0x00e2
>+#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_PAGE_IB_RPTR                                                                           0x00e3
>+#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_PAGE_IB_OFFSET                                                                         0x00e4
>+#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA0_PAGE_IB_BASE_LO                                                                        0x00e5
>+#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA0_PAGE_IB_BASE_HI                                                                        0x00e6
>+#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_PAGE_IB_SIZE                                                                           0x00e7
>+#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA0_PAGE_SKIP_CNTL                                                                         0x00e8
>+#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA0_PAGE_CONTEXT_STATUS                                                                    0x00e9
>+#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA0_PAGE_DOORBELL                                                                          0x00ea
>+#define mmSDMA0_PAGE_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA0_PAGE_STATUS                                                                            0x0100
>+#define mmSDMA0_PAGE_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA0_PAGE_DOORBELL_LOG                                                                      0x0101
>+#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA0_PAGE_WATERMARK                                                                         0x0102
>+#define mmSDMA0_PAGE_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA0_PAGE_DOORBELL_OFFSET                                                                   0x0103
>+#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA0_PAGE_CSA_ADDR_LO                                                                       0x0104
>+#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA0_PAGE_CSA_ADDR_HI                                                                       0x0105
>+#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA0_PAGE_IB_SUB_REMAIN                                                                     0x0107
>+#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA0_PAGE_PREEMPT                                                                           0x0108
>+#define mmSDMA0_PAGE_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA0_PAGE_DUMMY_REG                                                                         0x0109
>+#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x010a
>+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x010b
>+#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA0_PAGE_RB_AQL_CNTL                                                                       0x010c
>+#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_PAGE_MINOR_PTR_UPDATE                                                                  0x010d
>+#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA0_PAGE_MIDCMD_DATA0                                                                      0x0118
>+#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA0_PAGE_MIDCMD_DATA1                                                                      0x0119
>+#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA0_PAGE_MIDCMD_DATA2                                                                      0x011a
>+#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA0_PAGE_MIDCMD_DATA3                                                                      0x011b
>+#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA0_PAGE_MIDCMD_DATA4                                                                      0x011c
>+#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA0_PAGE_MIDCMD_DATA5                                                                      0x011d
>+#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA0_PAGE_MIDCMD_DATA6                                                                      0x011e
>+#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA0_PAGE_MIDCMD_DATA7                                                                      0x011f
>+#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA0_PAGE_MIDCMD_DATA8                                                                      0x0120
>+#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA0_PAGE_MIDCMD_CNTL                                                                       0x0121
>+#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC0_RB_CNTL                                                                           0x0130
>+#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC0_RB_BASE                                                                           0x0131
>+#define mmSDMA0_RLC0_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC0_RB_BASE_HI                                                                        0x0132
>+#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC0_RB_RPTR                                                                           0x0133
>+#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC0_RB_RPTR_HI                                                                        0x0134
>+#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC0_RB_WPTR                                                                           0x0135
>+#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC0_RB_WPTR_HI                                                                        0x0136
>+#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0137
>+#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI                                                                   0x0138
>+#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO                                                                   0x0139
>+#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA0_RLC0_IB_CNTL                                                                           0x013a
>+#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC0_IB_RPTR                                                                           0x013b
>+#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC0_IB_OFFSET                                                                         0x013c
>+#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA0_RLC0_IB_BASE_LO                                                                        0x013d
>+#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA0_RLC0_IB_BASE_HI                                                                        0x013e
>+#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC0_IB_SIZE                                                                           0x013f
>+#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC0_SKIP_CNTL                                                                         0x0140
>+#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA0_RLC0_CONTEXT_STATUS                                                                    0x0141
>+#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA0_RLC0_DOORBELL                                                                          0x0142
>+#define mmSDMA0_RLC0_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA0_RLC0_STATUS                                                                            0x0158
>+#define mmSDMA0_RLC0_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA0_RLC0_DOORBELL_LOG                                                                      0x0159
>+#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA0_RLC0_WATERMARK                                                                         0x015a
>+#define mmSDMA0_RLC0_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA0_RLC0_DOORBELL_OFFSET                                                                   0x015b
>+#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA0_RLC0_CSA_ADDR_LO                                                                       0x015c
>+#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA0_RLC0_CSA_ADDR_HI                                                                       0x015d
>+#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA0_RLC0_IB_SUB_REMAIN                                                                     0x015f
>+#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA0_RLC0_PREEMPT                                                                           0x0160
>+#define mmSDMA0_RLC0_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC0_DUMMY_REG                                                                         0x0161
>+#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0162
>+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0163
>+#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA0_RLC0_RB_AQL_CNTL                                                                       0x0164
>+#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC0_MINOR_PTR_UPDATE                                                                  0x0165
>+#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA0_RLC0_MIDCMD_DATA0                                                                      0x0170
>+#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA0_RLC0_MIDCMD_DATA1                                                                      0x0171
>+#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA0_RLC0_MIDCMD_DATA2                                                                      0x0172
>+#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA0_RLC0_MIDCMD_DATA3                                                                      0x0173
>+#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA0_RLC0_MIDCMD_DATA4                                                                      0x0174
>+#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA0_RLC0_MIDCMD_DATA5                                                                      0x0175
>+#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA0_RLC0_MIDCMD_DATA6                                                                      0x0176
>+#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA0_RLC0_MIDCMD_DATA7                                                                      0x0177
>+#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA0_RLC0_MIDCMD_DATA8                                                                      0x0178
>+#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA0_RLC0_MIDCMD_CNTL                                                                       0x0179
>+#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC1_RB_CNTL                                                                           0x0188
>+#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC1_RB_BASE                                                                           0x0189
>+#define mmSDMA0_RLC1_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC1_RB_BASE_HI                                                                        0x018a
>+#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC1_RB_RPTR                                                                           0x018b
>+#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC1_RB_RPTR_HI                                                                        0x018c
>+#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC1_RB_WPTR                                                                           0x018d
>+#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC1_RB_WPTR_HI                                                                        0x018e
>+#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL                                                                 0x018f
>+#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI                                                                   0x0190
>+#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO                                                                   0x0191
>+#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA0_RLC1_IB_CNTL                                                                           0x0192
>+#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC1_IB_RPTR                                                                           0x0193
>+#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC1_IB_OFFSET                                                                         0x0194
>+#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA0_RLC1_IB_BASE_LO                                                                        0x0195
>+#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA0_RLC1_IB_BASE_HI                                                                        0x0196
>+#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC1_IB_SIZE                                                                           0x0197
>+#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC1_SKIP_CNTL                                                                         0x0198
>+#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA0_RLC1_CONTEXT_STATUS                                                                    0x0199
>+#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA0_RLC1_DOORBELL                                                                          0x019a
>+#define mmSDMA0_RLC1_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA0_RLC1_STATUS                                                                            0x01b0
>+#define mmSDMA0_RLC1_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA0_RLC1_DOORBELL_LOG                                                                      0x01b1
>+#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA0_RLC1_WATERMARK                                                                         0x01b2
>+#define mmSDMA0_RLC1_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA0_RLC1_DOORBELL_OFFSET                                                                   0x01b3
>+#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA0_RLC1_CSA_ADDR_LO                                                                       0x01b4
>+#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA0_RLC1_CSA_ADDR_HI                                                                       0x01b5
>+#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA0_RLC1_IB_SUB_REMAIN                                                                     0x01b7
>+#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA0_RLC1_PREEMPT                                                                           0x01b8
>+#define mmSDMA0_RLC1_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC1_DUMMY_REG                                                                         0x01b9
>+#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x01ba
>+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x01bb
>+#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA0_RLC1_RB_AQL_CNTL                                                                       0x01bc
>+#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC1_MINOR_PTR_UPDATE                                                                  0x01bd
>+#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA0_RLC1_MIDCMD_DATA0                                                                      0x01c8
>+#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA0_RLC1_MIDCMD_DATA1                                                                      0x01c9
>+#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA0_RLC1_MIDCMD_DATA2                                                                      0x01ca
>+#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA0_RLC1_MIDCMD_DATA3                                                                      0x01cb
>+#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA0_RLC1_MIDCMD_DATA4                                                                      0x01cc
>+#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA0_RLC1_MIDCMD_DATA5                                                                      0x01cd
>+#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA0_RLC1_MIDCMD_DATA6                                                                      0x01ce
>+#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA0_RLC1_MIDCMD_DATA7                                                                      0x01cf
>+#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA0_RLC1_MIDCMD_DATA8                                                                      0x01d0
>+#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA0_RLC1_MIDCMD_CNTL                                                                       0x01d1
>+#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC2_RB_CNTL                                                                           0x01e0
>+#define mmSDMA0_RLC2_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC2_RB_BASE                                                                           0x01e1
>+#define mmSDMA0_RLC2_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC2_RB_BASE_HI                                                                        0x01e2
>+#define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC2_RB_RPTR                                                                           0x01e3
>+#define mmSDMA0_RLC2_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC2_RB_RPTR_HI                                                                        0x01e4
>+#define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC2_RB_WPTR                                                                           0x01e5
>+#define mmSDMA0_RLC2_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC2_RB_WPTR_HI                                                                        0x01e6
>+#define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL                                                                 0x01e7
>+#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI                                                                   0x01e8
>+#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO                                                                   0x01e9
>+#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA0_RLC2_IB_CNTL                                                                           0x01ea
>+#define mmSDMA0_RLC2_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC2_IB_RPTR                                                                           0x01eb
>+#define mmSDMA0_RLC2_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC2_IB_OFFSET                                                                         0x01ec
>+#define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA0_RLC2_IB_BASE_LO                                                                        0x01ed
>+#define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA0_RLC2_IB_BASE_HI                                                                        0x01ee
>+#define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC2_IB_SIZE                                                                           0x01ef
>+#define mmSDMA0_RLC2_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC2_SKIP_CNTL                                                                         0x01f0
>+#define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA0_RLC2_CONTEXT_STATUS                                                                    0x01f1
>+#define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA0_RLC2_DOORBELL                                                                          0x01f2
>+#define mmSDMA0_RLC2_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA0_RLC2_STATUS                                                                            0x0208
>+#define mmSDMA0_RLC2_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA0_RLC2_DOORBELL_LOG                                                                      0x0209
>+#define mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA0_RLC2_WATERMARK                                                                         0x020a
>+#define mmSDMA0_RLC2_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA0_RLC2_DOORBELL_OFFSET                                                                   0x020b
>+#define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA0_RLC2_CSA_ADDR_LO                                                                       0x020c
>+#define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA0_RLC2_CSA_ADDR_HI                                                                       0x020d
>+#define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA0_RLC2_IB_SUB_REMAIN                                                                     0x020f
>+#define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA0_RLC2_PREEMPT                                                                           0x0210
>+#define mmSDMA0_RLC2_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC2_DUMMY_REG                                                                         0x0211
>+#define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0212
>+#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0213
>+#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA0_RLC2_RB_AQL_CNTL                                                                       0x0214
>+#define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC2_MINOR_PTR_UPDATE                                                                  0x0215
>+#define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA0_RLC2_MIDCMD_DATA0                                                                      0x0220
>+#define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA0_RLC2_MIDCMD_DATA1                                                                      0x0221
>+#define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA0_RLC2_MIDCMD_DATA2                                                                      0x0222
>+#define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA0_RLC2_MIDCMD_DATA3                                                                      0x0223
>+#define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA0_RLC2_MIDCMD_DATA4                                                                      0x0224
>+#define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA0_RLC2_MIDCMD_DATA5                                                                      0x0225
>+#define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA0_RLC2_MIDCMD_DATA6                                                                      0x0226
>+#define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA0_RLC2_MIDCMD_DATA7                                                                      0x0227
>+#define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA0_RLC2_MIDCMD_DATA8                                                                      0x0228
>+#define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA0_RLC2_MIDCMD_CNTL                                                                       0x0229
>+#define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC3_RB_CNTL                                                                           0x0238
>+#define mmSDMA0_RLC3_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC3_RB_BASE                                                                           0x0239
>+#define mmSDMA0_RLC3_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC3_RB_BASE_HI                                                                        0x023a
>+#define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC3_RB_RPTR                                                                           0x023b
>+#define mmSDMA0_RLC3_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC3_RB_RPTR_HI                                                                        0x023c
>+#define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC3_RB_WPTR                                                                           0x023d
>+#define mmSDMA0_RLC3_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC3_RB_WPTR_HI                                                                        0x023e
>+#define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL                                                                 0x023f
>+#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI                                                                   0x0240
>+#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO                                                                   0x0241
>+#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA0_RLC3_IB_CNTL                                                                           0x0242
>+#define mmSDMA0_RLC3_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC3_IB_RPTR                                                                           0x0243
>+#define mmSDMA0_RLC3_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC3_IB_OFFSET                                                                         0x0244
>+#define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA0_RLC3_IB_BASE_LO                                                                        0x0245
>+#define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA0_RLC3_IB_BASE_HI                                                                        0x0246
>+#define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC3_IB_SIZE                                                                           0x0247
>+#define mmSDMA0_RLC3_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC3_SKIP_CNTL                                                                         0x0248
>+#define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA0_RLC3_CONTEXT_STATUS                                                                    0x0249
>+#define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA0_RLC3_DOORBELL                                                                          0x024a
>+#define mmSDMA0_RLC3_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA0_RLC3_STATUS                                                                            0x0260
>+#define mmSDMA0_RLC3_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA0_RLC3_DOORBELL_LOG                                                                      0x0261
>+#define mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA0_RLC3_WATERMARK                                                                         0x0262
>+#define mmSDMA0_RLC3_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA0_RLC3_DOORBELL_OFFSET                                                                   0x0263
>+#define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA0_RLC3_CSA_ADDR_LO                                                                       0x0264
>+#define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA0_RLC3_CSA_ADDR_HI                                                                       0x0265
>+#define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA0_RLC3_IB_SUB_REMAIN                                                                     0x0267
>+#define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA0_RLC3_PREEMPT                                                                           0x0268
>+#define mmSDMA0_RLC3_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC3_DUMMY_REG                                                                         0x0269
>+#define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x026a
>+#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x026b
>+#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA0_RLC3_RB_AQL_CNTL                                                                       0x026c
>+#define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC3_MINOR_PTR_UPDATE                                                                  0x026d
>+#define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA0_RLC3_MIDCMD_DATA0                                                                      0x0278
>+#define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA0_RLC3_MIDCMD_DATA1                                                                      0x0279
>+#define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA0_RLC3_MIDCMD_DATA2                                                                      0x027a
>+#define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA0_RLC3_MIDCMD_DATA3                                                                      0x027b
>+#define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA0_RLC3_MIDCMD_DATA4                                                                      0x027c
>+#define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA0_RLC3_MIDCMD_DATA5                                                                      0x027d
>+#define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA0_RLC3_MIDCMD_DATA6                                                                      0x027e
>+#define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA0_RLC3_MIDCMD_DATA7                                                                      0x027f
>+#define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA0_RLC3_MIDCMD_DATA8                                                                      0x0280
>+#define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA0_RLC3_MIDCMD_CNTL                                                                       0x0281
>+#define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC4_RB_CNTL                                                                           0x0290
>+#define mmSDMA0_RLC4_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC4_RB_BASE                                                                           0x0291
>+#define mmSDMA0_RLC4_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC4_RB_BASE_HI                                                                        0x0292
>+#define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC4_RB_RPTR                                                                           0x0293
>+#define mmSDMA0_RLC4_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC4_RB_RPTR_HI                                                                        0x0294
>+#define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC4_RB_WPTR                                                                           0x0295
>+#define mmSDMA0_RLC4_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC4_RB_WPTR_HI                                                                        0x0296
>+#define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL                                                                 0x0297
>+#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI                                                                   0x0298
>+#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO                                                                   0x0299
>+#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA0_RLC4_IB_CNTL                                                                           0x029a
>+#define mmSDMA0_RLC4_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC4_IB_RPTR                                                                           0x029b
>+#define mmSDMA0_RLC4_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC4_IB_OFFSET                                                                         0x029c
>+#define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA0_RLC4_IB_BASE_LO                                                                        0x029d
>+#define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA0_RLC4_IB_BASE_HI                                                                        0x029e
>+#define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC4_IB_SIZE                                                                           0x029f
>+#define mmSDMA0_RLC4_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC4_SKIP_CNTL                                                                         0x02a0
>+#define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA0_RLC4_CONTEXT_STATUS                                                                    0x02a1
>+#define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA0_RLC4_DOORBELL                                                                          0x02a2
>+#define mmSDMA0_RLC4_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA0_RLC4_STATUS                                                                            0x02b8
>+#define mmSDMA0_RLC4_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA0_RLC4_DOORBELL_LOG                                                                      0x02b9
>+#define mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA0_RLC4_WATERMARK                                                                         0x02ba
>+#define mmSDMA0_RLC4_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA0_RLC4_DOORBELL_OFFSET                                                                   0x02bb
>+#define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA0_RLC4_CSA_ADDR_LO                                                                       0x02bc
>+#define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA0_RLC4_CSA_ADDR_HI                                                                       0x02bd
>+#define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA0_RLC4_IB_SUB_REMAIN                                                                     0x02bf
>+#define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA0_RLC4_PREEMPT                                                                           0x02c0
>+#define mmSDMA0_RLC4_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC4_DUMMY_REG                                                                         0x02c1
>+#define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x02c2
>+#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x02c3
>+#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA0_RLC4_RB_AQL_CNTL                                                                       0x02c4
>+#define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC4_MINOR_PTR_UPDATE                                                                  0x02c5
>+#define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA0_RLC4_MIDCMD_DATA0                                                                      0x02d0
>+#define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA0_RLC4_MIDCMD_DATA1                                                                      0x02d1
>+#define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA0_RLC4_MIDCMD_DATA2                                                                      0x02d2
>+#define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA0_RLC4_MIDCMD_DATA3                                                                      0x02d3
>+#define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA0_RLC4_MIDCMD_DATA4                                                                      0x02d4
>+#define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA0_RLC4_MIDCMD_DATA5                                                                      0x02d5
>+#define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA0_RLC4_MIDCMD_DATA6                                                                      0x02d6
>+#define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA0_RLC4_MIDCMD_DATA7                                                                      0x02d7
>+#define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA0_RLC4_MIDCMD_DATA8                                                                      0x02d8
>+#define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA0_RLC4_MIDCMD_CNTL                                                                       0x02d9
>+#define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC5_RB_CNTL                                                                           0x02e8
>+#define mmSDMA0_RLC5_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC5_RB_BASE                                                                           0x02e9
>+#define mmSDMA0_RLC5_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC5_RB_BASE_HI                                                                        0x02ea
>+#define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC5_RB_RPTR                                                                           0x02eb
>+#define mmSDMA0_RLC5_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC5_RB_RPTR_HI                                                                        0x02ec
>+#define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC5_RB_WPTR                                                                           0x02ed
>+#define mmSDMA0_RLC5_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC5_RB_WPTR_HI                                                                        0x02ee
>+#define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL                                                                 0x02ef
>+#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI                                                                   0x02f0
>+#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO                                                                   0x02f1
>+#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA0_RLC5_IB_CNTL                                                                           0x02f2
>+#define mmSDMA0_RLC5_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC5_IB_RPTR                                                                           0x02f3
>+#define mmSDMA0_RLC5_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC5_IB_OFFSET                                                                         0x02f4
>+#define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA0_RLC5_IB_BASE_LO                                                                        0x02f5
>+#define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA0_RLC5_IB_BASE_HI                                                                        0x02f6
>+#define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC5_IB_SIZE                                                                           0x02f7
>+#define mmSDMA0_RLC5_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC5_SKIP_CNTL                                                                         0x02f8
>+#define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA0_RLC5_CONTEXT_STATUS                                                                    0x02f9
>+#define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA0_RLC5_DOORBELL                                                                          0x02fa
>+#define mmSDMA0_RLC5_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA0_RLC5_STATUS                                                                            0x0310
>+#define mmSDMA0_RLC5_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA0_RLC5_DOORBELL_LOG                                                                      0x0311
>+#define mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA0_RLC5_WATERMARK                                                                         0x0312
>+#define mmSDMA0_RLC5_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA0_RLC5_DOORBELL_OFFSET                                                                   0x0313
>+#define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA0_RLC5_CSA_ADDR_LO                                                                       0x0314
>+#define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA0_RLC5_CSA_ADDR_HI                                                                       0x0315
>+#define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA0_RLC5_IB_SUB_REMAIN                                                                     0x0317
>+#define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA0_RLC5_PREEMPT                                                                           0x0318
>+#define mmSDMA0_RLC5_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC5_DUMMY_REG                                                                         0x0319
>+#define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x031a
>+#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x031b
>+#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA0_RLC5_RB_AQL_CNTL                                                                       0x031c
>+#define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC5_MINOR_PTR_UPDATE                                                                  0x031d
>+#define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA0_RLC5_MIDCMD_DATA0                                                                      0x0328
>+#define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA0_RLC5_MIDCMD_DATA1                                                                      0x0329
>+#define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA0_RLC5_MIDCMD_DATA2                                                                      0x032a
>+#define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA0_RLC5_MIDCMD_DATA3                                                                      0x032b
>+#define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA0_RLC5_MIDCMD_DATA4                                                                      0x032c
>+#define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA0_RLC5_MIDCMD_DATA5                                                                      0x032d
>+#define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA0_RLC5_MIDCMD_DATA6                                                                      0x032e
>+#define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA0_RLC5_MIDCMD_DATA7                                                                      0x032f
>+#define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA0_RLC5_MIDCMD_DATA8                                                                      0x0330
>+#define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA0_RLC5_MIDCMD_CNTL                                                                       0x0331
>+#define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC6_RB_CNTL                                                                           0x0340
>+#define mmSDMA0_RLC6_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC6_RB_BASE                                                                           0x0341
>+#define mmSDMA0_RLC6_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC6_RB_BASE_HI                                                                        0x0342
>+#define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC6_RB_RPTR                                                                           0x0343
>+#define mmSDMA0_RLC6_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC6_RB_RPTR_HI                                                                        0x0344
>+#define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC6_RB_WPTR                                                                           0x0345
>+#define mmSDMA0_RLC6_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC6_RB_WPTR_HI                                                                        0x0346
>+#define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0347
>+#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI                                                                   0x0348
>+#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO                                                                   0x0349
>+#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA0_RLC6_IB_CNTL                                                                           0x034a
>+#define mmSDMA0_RLC6_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC6_IB_RPTR                                                                           0x034b
>+#define mmSDMA0_RLC6_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC6_IB_OFFSET                                                                         0x034c
>+#define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA0_RLC6_IB_BASE_LO                                                                        0x034d
>+#define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA0_RLC6_IB_BASE_HI                                                                        0x034e
>+#define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC6_IB_SIZE                                                                           0x034f
>+#define mmSDMA0_RLC6_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC6_SKIP_CNTL                                                                         0x0350
>+#define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA0_RLC6_CONTEXT_STATUS                                                                    0x0351
>+#define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA0_RLC6_DOORBELL                                                                          0x0352
>+#define mmSDMA0_RLC6_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA0_RLC6_STATUS                                                                            0x0368
>+#define mmSDMA0_RLC6_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA0_RLC6_DOORBELL_LOG                                                                      0x0369
>+#define mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA0_RLC6_WATERMARK                                                                         0x036a
>+#define mmSDMA0_RLC6_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA0_RLC6_DOORBELL_OFFSET                                                                   0x036b
>+#define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA0_RLC6_CSA_ADDR_LO                                                                       0x036c
>+#define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA0_RLC6_CSA_ADDR_HI                                                                       0x036d
>+#define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA0_RLC6_IB_SUB_REMAIN                                                                     0x036f
>+#define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA0_RLC6_PREEMPT                                                                           0x0370
>+#define mmSDMA0_RLC6_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC6_DUMMY_REG                                                                         0x0371
>+#define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x0372
>+#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x0373
>+#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA0_RLC6_RB_AQL_CNTL                                                                       0x0374
>+#define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC6_MINOR_PTR_UPDATE                                                                  0x0375
>+#define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA0_RLC6_MIDCMD_DATA0                                                                      0x0380
>+#define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA0_RLC6_MIDCMD_DATA1                                                                      0x0381
>+#define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA0_RLC6_MIDCMD_DATA2                                                                      0x0382
>+#define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA0_RLC6_MIDCMD_DATA3                                                                      0x0383
>+#define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA0_RLC6_MIDCMD_DATA4                                                                      0x0384
>+#define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA0_RLC6_MIDCMD_DATA5                                                                      0x0385
>+#define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA0_RLC6_MIDCMD_DATA6                                                                      0x0386
>+#define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA0_RLC6_MIDCMD_DATA7                                                                      0x0387
>+#define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA0_RLC6_MIDCMD_DATA8                                                                      0x0388
>+#define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA0_RLC6_MIDCMD_CNTL                                                                       0x0389
>+#define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC7_RB_CNTL                                                                           0x0398
>+#define mmSDMA0_RLC7_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC7_RB_BASE                                                                           0x0399
>+#define mmSDMA0_RLC7_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC7_RB_BASE_HI                                                                        0x039a
>+#define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC7_RB_RPTR                                                                           0x039b
>+#define mmSDMA0_RLC7_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC7_RB_RPTR_HI                                                                        0x039c
>+#define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC7_RB_WPTR                                                                           0x039d
>+#define mmSDMA0_RLC7_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC7_RB_WPTR_HI                                                                        0x039e
>+#define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL                                                                 0x039f
>+#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI                                                                   0x03a0
>+#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO                                                                   0x03a1
>+#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA0_RLC7_IB_CNTL                                                                           0x03a2
>+#define mmSDMA0_RLC7_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC7_IB_RPTR                                                                           0x03a3
>+#define mmSDMA0_RLC7_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC7_IB_OFFSET                                                                         0x03a4
>+#define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA0_RLC7_IB_BASE_LO                                                                        0x03a5
>+#define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA0_RLC7_IB_BASE_HI                                                                        0x03a6
>+#define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA0_RLC7_IB_SIZE                                                                           0x03a7
>+#define mmSDMA0_RLC7_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC7_SKIP_CNTL                                                                         0x03a8
>+#define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA0_RLC7_CONTEXT_STATUS                                                                    0x03a9
>+#define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA0_RLC7_DOORBELL                                                                          0x03aa
>+#define mmSDMA0_RLC7_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA0_RLC7_STATUS                                                                            0x03c0
>+#define mmSDMA0_RLC7_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA0_RLC7_DOORBELL_LOG                                                                      0x03c1
>+#define mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA0_RLC7_WATERMARK                                                                         0x03c2
>+#define mmSDMA0_RLC7_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA0_RLC7_DOORBELL_OFFSET                                                                   0x03c3
>+#define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA0_RLC7_CSA_ADDR_LO                                                                       0x03c4
>+#define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA0_RLC7_CSA_ADDR_HI                                                                       0x03c5
>+#define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA0_RLC7_IB_SUB_REMAIN                                                                     0x03c7
>+#define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA0_RLC7_PREEMPT                                                                           0x03c8
>+#define mmSDMA0_RLC7_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA0_RLC7_DUMMY_REG                                                                         0x03c9
>+#define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x03ca
>+#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x03cb
>+#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA0_RLC7_RB_AQL_CNTL                                                                       0x03cc
>+#define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA0_RLC7_MINOR_PTR_UPDATE                                                                  0x03cd
>+#define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA0_RLC7_MIDCMD_DATA0                                                                      0x03d8
>+#define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA0_RLC7_MIDCMD_DATA1                                                                      0x03d9
>+#define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA0_RLC7_MIDCMD_DATA2                                                                      0x03da
>+#define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA0_RLC7_MIDCMD_DATA3                                                                      0x03db
>+#define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA0_RLC7_MIDCMD_DATA4                                                                      0x03dc
>+#define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA0_RLC7_MIDCMD_DATA5                                                                      0x03dd
>+#define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA0_RLC7_MIDCMD_DATA6                                                                      0x03de
>+#define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA0_RLC7_MIDCMD_DATA7                                                                      0x03df
>+#define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA0_RLC7_MIDCMD_DATA8                                                                      0x03e0
>+#define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA0_RLC7_MIDCMD_CNTL                                                                       0x03e1
>+#define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX                                                              0
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h	2019-08-31 15:01:11.931736175 -0500
>@@ -0,0 +1,3002 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma0_4_2_2_SH_MASK_HEADER
>+#define _sdma0_4_2_2_SH_MASK_HEADER
>+
>+
>+// addressBlock: sdma0_sdma0dec
>+//SDMA0_UCODE_ADDR
>+#define SDMA0_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
>+#define SDMA0_UCODE_ADDR__VALUE_MASK                                                                          0x00001FFFL
>+//SDMA0_UCODE_DATA
>+#define SDMA0_UCODE_DATA__VALUE__SHIFT                                                                        0x0
>+#define SDMA0_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
>+//SDMA0_VM_CNTL
>+#define SDMA0_VM_CNTL__CMD__SHIFT                                                                             0x0
>+#define SDMA0_VM_CNTL__CMD_MASK                                                                               0x0000000FL
>+//SDMA0_VM_CTX_LO
>+#define SDMA0_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
>+#define SDMA0_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
>+//SDMA0_VM_CTX_HI
>+#define SDMA0_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
>+#define SDMA0_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
>+//SDMA0_ACTIVE_FCN_ID
>+#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
>+#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x4
>+#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
>+#define SDMA0_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000000FL
>+#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFF0L
>+#define SDMA0_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
>+//SDMA0_VM_CTX_CNTL
>+#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
>+#define SDMA0_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
>+#define SDMA0_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
>+#define SDMA0_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
>+//SDMA0_VIRT_RESET_REQ
>+#define SDMA0_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
>+#define SDMA0_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
>+#define SDMA0_VIRT_RESET_REQ__VF_MASK                                                                         0x0000FFFFL
>+#define SDMA0_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
>+//SDMA0_VF_ENABLE
>+#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
>+#define SDMA0_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
>+//SDMA0_CONTEXT_REG_TYPE0
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT                                                     0x0
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT                                                     0x1
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT                                                  0x2
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT                                                     0x3
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT                                                  0x4
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT                                                     0x5
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT                                                  0x6
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT                                                     0xa
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT                                                     0xb
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT                                                   0xc
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT                                                  0xd
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT                                                  0xe
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT                                                     0xf
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT                                                   0x10
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT                                              0x11
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT                                                    0x12
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT                                                0x13
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK                                                       0x00000001L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK                                                       0x00000002L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK                                                    0x00000004L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK                                                       0x00000008L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK                                                       0x00000020L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK                                                       0x00000400L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK                                                       0x00000800L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK                                                     0x00001000L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK                                                    0x00002000L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK                                                    0x00004000L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK                                                       0x00008000L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK                                                     0x00010000L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK                                                      0x00040000L
>+#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
>+//SDMA0_CONTEXT_REG_TYPE1
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT                                                      0x8
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT                                                0x9
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT                                                   0xa
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
>+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT                                                     0x10
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT                                                   0x11
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
>+#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x16
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK                                                        0x00000100L
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK                                                     0x00000400L
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
>+#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK                                                       0x00010000L
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK                                                     0x00020000L
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
>+#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
>+#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFFC00000L
>+//SDMA0_CONTEXT_REG_TYPE2
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT                                                0x0
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT                                                0x1
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT                                                0x2
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT                                                0x3
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT                                                0x4
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT                                                0x5
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT                                                0x6
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT                                                0x7
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT                                                0x8
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT                                                 0x9
>+#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
>+#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK                                                   0x00000200L
>+#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFFC00L
>+//SDMA0_CONTEXT_REG_TYPE3
>+#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
>+#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
>+//SDMA0_PUB_REG_TYPE0
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT                                                          0x0
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT                                                          0x1
>+#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT                                                                 0x3
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT                                                             0x4
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT                                                           0x5
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT                                                           0x6
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT                                                       0x7
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT                                                         0x8
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT                                                      0x9
>+#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT                                                                0xa
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT                                                   0xb
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT                                                   0xc
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT                                                   0xd
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT                                                   0xe
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT                                                       0xf
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT                                                       0x10
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT                                                       0x11
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT                                                       0x12
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT                                                          0x13
>+#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x15
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT                                              0x19
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT                                                          0x1a
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT                                                            0x1b
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT                                                                0x1c
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT                                                        0x1d
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT                                                      0x1e
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK                                                            0x00000001L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK                                                            0x00000002L
>+#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK                                                                   0x00000008L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK                                                               0x00000010L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK                                                             0x00000020L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK                                                             0x00000040L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK                                                         0x00000080L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK                                                           0x00000100L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK                                                        0x00000200L
>+#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK                                                                  0x00000400L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK                                                     0x00000800L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK                                                     0x00001000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK                                                     0x00002000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK                                                     0x00004000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK                                                         0x00008000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK                                                         0x00010000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK                                                         0x00020000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK                                                         0x00040000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK                                                            0x00080000L
>+#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x01E00000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK                                                0x02000000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK                                                            0x04000000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK                                                              0x08000000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK                                                                  0x10000000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK                                                          0x20000000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK                                                        0x40000000L
>+#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
>+//SDMA0_PUB_REG_TYPE1
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT                                                       0x2
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT                                                     0x3
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT                                                             0x4
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT                                                          0x5
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT                                                         0x6
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT                                                       0x7
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT                                                     0x8
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT                                                      0x9
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT                                                            0xa
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT                                                              0xb
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT                                                      0xc
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT                                                      0xd
>+#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT                                                         0xe
>+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT                                                         0xf
>+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT                                                          0x10
>+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT                                                           0x11
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT                                                          0x12
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT                                                        0x13
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT                                                                  0x14
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT                                                             0x15
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT                                                         0x16
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT                                                         0x18
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT                                                         0x19
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT                                                          0x1c
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT                                                       0x1d
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT                                                     0x1e
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT                                                     0x1f
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK                                                         0x00000004L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK                                                       0x00000008L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK                                                               0x00000010L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK                                                            0x00000020L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK                                                           0x00000040L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK                                                         0x00000080L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK                                                        0x00000200L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK                                                              0x00000400L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK                                                                0x00000800L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK                                                        0x00001000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK                                                        0x00002000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK                                                           0x00004000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK                                                           0x00008000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK                                                            0x00010000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK                                                             0x00020000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK                                                            0x00040000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK                                                          0x00080000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK                                                                    0x00100000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK                                                               0x00200000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK                                                           0x00400000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK                                                           0x01000000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK                                                           0x02000000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK                                                            0x10000000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK                                                         0x20000000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK                                                       0x40000000L
>+#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK                                                       0x80000000L
>+//SDMA0_PUB_REG_TYPE2
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT                                                          0x0
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT                                                          0x1
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT                                                          0x2
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT                                                     0x3
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT                                                     0x4
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT                                                     0x5
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT                                                     0x6
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT                                                       0x7
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT                                                          0x8
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT                                                     0x9
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT                                                  0xa
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT                                                      0xb
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT                                                         0xc
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT                                                      0xf
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT                                                           0x10
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT                                                      0x11
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT                                                      0x12
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT                                                      0x13
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT                                                      0x14
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT                                                         0x15
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT                                                         0x16
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT                                                        0x17
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT                                                 0x18
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT                                                 0x19
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT                                         0x1a
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT                                                            0x1b
>+#define SDMA0_PUB_REG_TYPE2__RESERVED28__SHIFT                                                                0x1c
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT                                               0x1d
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT                                                            0x1e
>+#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT                                                                  0x1f
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK                                                            0x00000001L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK                                                            0x00000002L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK                                                            0x00000004L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK                                                         0x00000080L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK                                                            0x00000100L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK                                                       0x00000200L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK                                                        0x00000800L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK                                                           0x00001000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK                                                        0x00008000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK                                                             0x00010000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK                                                        0x00020000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK                                                        0x00040000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK                                                        0x00080000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK                                                        0x00100000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK                                                           0x00200000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK                                                           0x00400000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK                                                          0x00800000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK                                                   0x01000000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK                                                   0x02000000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK                                           0x04000000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK                                                              0x08000000L
>+#define SDMA0_PUB_REG_TYPE2__RESERVED28_MASK                                                                  0x10000000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK                                                 0x20000000L
>+#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK                                                              0x40000000L
>+#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK                                                                    0x80000000L
>+//SDMA0_PUB_REG_TYPE3
>+#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
>+#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
>+#define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2__SHIFT                                              0x2
>+#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x3
>+#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
>+#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
>+#define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2_MASK                                                0x00000004L
>+#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xFFFFFFF8L
>+//SDMA0_MMHUB_CNTL
>+#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT                                                                      0x0
>+#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK                                                                        0x0000003FL
>+//SDMA0_CONTEXT_GROUP_BOUNDARY
>+#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT                                                         0x0
>+#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK                                                           0xFFFFFFFFL
>+//SDMA0_POWER_CNTL
>+#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT                                                               0x0
>+#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT                                                          0x1
>+#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT                                                         0x2
>+#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT                                                   0x3
>+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
>+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT                                                              0x9
>+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT                                                              0xa
>+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT                                                              0xb
>+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT                                                              0xc
>+#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT                                                  0x1a
>+#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK                                                                 0x00000001L
>+#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK                                                            0x00000002L
>+#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK                                                           0x00000004L
>+#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK                                                     0x000000F8L
>+#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
>+#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK                                                                0x00000200L
>+#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK                                                                0x00000400L
>+#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK                                                                0x00000800L
>+#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK                                                                0x003FF000L
>+#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK                                                    0xFC000000L
>+//SDMA0_CLK_CTRL
>+#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
>+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
>+#define SDMA0_CLK_CTRL__RESERVED__SHIFT                                                                       0xc
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                                 0x18
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                                 0x19
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                                 0x1a
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1b
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1c
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1d
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1e
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1f
>+#define SDMA0_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
>+#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
>+#define SDMA0_CLK_CTRL__RESERVED_MASK                                                                         0x00FFF000L
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                   0x01000000L
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                   0x02000000L
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                   0x04000000L
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x08000000L
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x10000000L
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x20000000L
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x40000000L
>+#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x80000000L
>+//SDMA0_CNTL
>+#define SDMA0_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
>+#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
>+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
>+#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
>+#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
>+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
>+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
>+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
>+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
>+#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
>+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
>+#define SDMA0_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
>+#define SDMA0_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
>+#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
>+#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
>+#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
>+#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
>+#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
>+#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
>+#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
>+#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
>+#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
>+//SDMA0_CHICKEN_BITS
>+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
>+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
>+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
>+#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
>+#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
>+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
>+#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
>+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
>+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
>+#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
>+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
>+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
>+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
>+#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
>+#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
>+#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
>+#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
>+#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
>+#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
>+#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
>+#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
>+#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
>+#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
>+#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
>+#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
>+#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
>+//SDMA0_GB_ADDR_CONFIG
>+#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
>+#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
>+#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
>+#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
>+#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
>+#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
>+#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
>+#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
>+#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
>+#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
>+//SDMA0_GB_ADDR_CONFIG_READ
>+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
>+#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
>+#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                0x8
>+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                           0xc
>+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
>+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
>+#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
>+#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                  0x00000700L
>+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                             0x00007000L
>+#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
>+//SDMA0_RB_RPTR_FETCH_HI
>+#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
>+#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL
>+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
>+#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
>+//SDMA0_RB_RPTR_FETCH
>+#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
>+#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
>+//SDMA0_IB_OFFSET_FETCH
>+#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
>+#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
>+//SDMA0_PROGRAM
>+#define SDMA0_PROGRAM__STREAM__SHIFT                                                                          0x0
>+#define SDMA0_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
>+//SDMA0_STATUS_REG
>+#define SDMA0_STATUS_REG__IDLE__SHIFT                                                                         0x0
>+#define SDMA0_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
>+#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
>+#define SDMA0_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
>+#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
>+#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
>+#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
>+#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
>+#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
>+#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
>+#define SDMA0_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
>+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
>+#define SDMA0_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
>+#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
>+#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
>+#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
>+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
>+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
>+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
>+#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
>+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
>+#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
>+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
>+#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
>+#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
>+#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
>+#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
>+#define SDMA0_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
>+#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
>+#define SDMA0_STATUS_REG__IDLE_MASK                                                                           0x00000001L
>+#define SDMA0_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
>+#define SDMA0_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
>+#define SDMA0_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
>+#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
>+#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
>+#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
>+#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
>+#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
>+#define SDMA0_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
>+#define SDMA0_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
>+#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
>+#define SDMA0_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
>+#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
>+#define SDMA0_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
>+#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
>+#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
>+#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
>+#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
>+#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
>+#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
>+#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
>+#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
>+#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
>+#define SDMA0_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
>+#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
>+#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
>+#define SDMA0_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
>+#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
>+//SDMA0_STATUS1_REG
>+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
>+#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
>+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
>+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
>+#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
>+#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
>+#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
>+#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
>+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
>+#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
>+#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
>+#define SDMA0_STATUS1_REG__EX_START__SHIFT                                                                    0xf
>+#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
>+#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
>+#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
>+#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
>+#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
>+#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
>+#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
>+#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
>+#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
>+#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
>+#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
>+#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
>+#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
>+#define SDMA0_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
>+#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
>+#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
>+//SDMA0_RD_BURST_CNTL
>+#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
>+#define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT                                                       0x2
>+#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
>+#define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK                                                         0x0000000CL
>+//SDMA0_HBM_PAGE_CONFIG
>+#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
>+#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000003L
>+//SDMA0_UCODE_CHECKSUM
>+#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
>+#define SDMA0_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_F32_CNTL
>+#define SDMA0_F32_CNTL__HALT__SHIFT                                                                           0x0
>+#define SDMA0_F32_CNTL__STEP__SHIFT                                                                           0x1
>+#define SDMA0_F32_CNTL__HALT_MASK                                                                             0x00000001L
>+#define SDMA0_F32_CNTL__STEP_MASK                                                                             0x00000002L
>+//SDMA0_FREEZE
>+#define SDMA0_FREEZE__PREEMPT__SHIFT                                                                          0x0
>+#define SDMA0_FREEZE__FREEZE__SHIFT                                                                           0x4
>+#define SDMA0_FREEZE__FROZEN__SHIFT                                                                           0x5
>+#define SDMA0_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
>+#define SDMA0_FREEZE__PREEMPT_MASK                                                                            0x00000001L
>+#define SDMA0_FREEZE__FREEZE_MASK                                                                             0x00000010L
>+#define SDMA0_FREEZE__FROZEN_MASK                                                                             0x00000020L
>+#define SDMA0_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
>+//SDMA0_PHASE0_QUANTUM
>+#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA0_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA0_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA0_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA0_PHASE1_QUANTUM
>+#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA0_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA0_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA0_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA_POWER_GATING
>+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT                                                   0x0
>+#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT                                                    0x1
>+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT                                                         0x2
>+#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT                                                          0x3
>+#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT                                                              0x4
>+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK                                                     0x00000001L
>+#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK                                                      0x00000002L
>+#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK                                                           0x00000004L
>+#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK                                                            0x00000008L
>+#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK                                                                0x00000030L
>+//SDMA_PGFSM_CONFIG
>+#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT                                                                    0x0
>+#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT                                                                  0x8
>+#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT                                                                    0x9
>+#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT                                                                   0xa
>+#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT                                                                   0xb
>+#define SDMA_PGFSM_CONFIG__WRITE__SHIFT                                                                       0xc
>+#define SDMA_PGFSM_CONFIG__READ__SHIFT                                                                        0xd
>+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT                                                               0x1b
>+#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT                                                                    0x1c
>+#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK                                                                      0x000000FFL
>+#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK                                                                    0x00000100L
>+#define SDMA_PGFSM_CONFIG__POWER_UP_MASK                                                                      0x00000200L
>+#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK                                                                     0x00000400L
>+#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK                                                                     0x00000800L
>+#define SDMA_PGFSM_CONFIG__WRITE_MASK                                                                         0x00001000L
>+#define SDMA_PGFSM_CONFIG__READ_MASK                                                                          0x00002000L
>+#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK                                                                 0x08000000L
>+#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK                                                                      0xF0000000L
>+//SDMA_PGFSM_WRITE
>+#define SDMA_PGFSM_WRITE__VALUE__SHIFT                                                                        0x0
>+#define SDMA_PGFSM_WRITE__VALUE_MASK                                                                          0xFFFFFFFFL
>+//SDMA_PGFSM_READ
>+#define SDMA_PGFSM_READ__VALUE__SHIFT                                                                         0x0
>+#define SDMA_PGFSM_READ__VALUE_MASK                                                                           0x00FFFFFFL
>+//SDMA0_EDC_CONFIG
>+#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
>+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
>+#define SDMA0_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
>+#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
>+//SDMA0_BA_THRESHOLD
>+#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
>+#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
>+#define SDMA0_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
>+#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
>+//SDMA0_ID
>+#define SDMA0_ID__DEVICE_ID__SHIFT                                                                            0x0
>+#define SDMA0_ID__DEVICE_ID_MASK                                                                              0x000000FFL
>+//SDMA0_VERSION
>+#define SDMA0_VERSION__MINVER__SHIFT                                                                          0x0
>+#define SDMA0_VERSION__MAJVER__SHIFT                                                                          0x8
>+#define SDMA0_VERSION__REV__SHIFT                                                                             0x10
>+#define SDMA0_VERSION__MINVER_MASK                                                                            0x0000007FL
>+#define SDMA0_VERSION__MAJVER_MASK                                                                            0x00007F00L
>+#define SDMA0_VERSION__REV_MASK                                                                               0x003F0000L
>+//SDMA0_EDC_COUNTER
>+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT                                                          0x0
>+#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
>+#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
>+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
>+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
>+#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT                                                    0xf
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT                                                    0x10
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT                                                   0x11
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT                                                   0x12
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT                                                   0x13
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT                                                   0x14
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT                                                   0x15
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT                                                   0x16
>+#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0x17
>+#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x18
>+#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK                                                            0x00000001L
>+#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
>+#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
>+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
>+#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
>+#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK                                                      0x00008000L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK                                                      0x00010000L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK                                                     0x00020000L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK                                                     0x00040000L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK                                                     0x00080000L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK                                                     0x00100000L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK                                                     0x00200000L
>+#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK                                                     0x00400000L
>+#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00800000L
>+#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x01000000L
>+//SDMA0_EDC_COUNTER_CLEAR
>+#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
>+#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
>+//SDMA0_STATUS2_REG
>+#define SDMA0_STATUS2_REG__ID__SHIFT                                                                          0x0
>+#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x3
>+#define SDMA0_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
>+#define SDMA0_STATUS2_REG__ID_MASK                                                                            0x00000007L
>+#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFF8L
>+#define SDMA0_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
>+//SDMA0_ATOMIC_CNTL
>+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
>+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
>+#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
>+#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
>+//SDMA0_ATOMIC_PREOP_LO
>+#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
>+#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_ATOMIC_PREOP_HI
>+#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
>+#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_UTCL1_CNTL
>+#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
>+#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0xb
>+#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0xe
>+#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
>+#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
>+#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x000007FEL
>+#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x00003800L
>+#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FFC000L
>+#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
>+#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
>+//SDMA0_UTCL1_WATERMK
>+#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
>+#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0x9
>+#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x11
>+#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x19
>+#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000001FFL
>+#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0001FE00L
>+#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x01FE0000L
>+#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFE000000L
>+//SDMA0_UTCL1_RD_STATUS
>+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT                                                             0x15
>+#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x16
>+#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x1a
>+#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x1d
>+#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT                                                            0x1e
>+#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT                                                             0x1f
>+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK                                                               0x00200000L
>+#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x03C00000L
>+#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x1C000000L
>+#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x20000000L
>+#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK                                                              0x40000000L
>+#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK                                                               0x80000000L
>+//SDMA0_UTCL1_WR_STATUS
>+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15
>+#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x16
>+#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19
>+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
>+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
>+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
>+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
>+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x00200000L
>+#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x01C00000L
>+#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x0E000000L
>+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
>+#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
>+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
>+#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
>+//SDMA0_UTCL1_INV0
>+#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT                                                                   0x0
>+#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT                                                                   0x1
>+#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT                                                                   0x2
>+#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT                                                                 0x3
>+#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT                                                                 0x4
>+#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT                                                                 0x5
>+#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT                                                              0x6
>+#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT                                                                0x7
>+#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT                                                              0x8
>+#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT                                                              0x9
>+#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT                                                               0xa
>+#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT                                                                0xb
>+#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT                                                                 0xc
>+#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT                                                                  0x1c
>+#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK                                                                     0x00000001L
>+#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK                                                                     0x00000002L
>+#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK                                                                     0x00000004L
>+#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK                                                                   0x00000008L
>+#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK                                                                   0x00000010L
>+#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK                                                                   0x00000020L
>+#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK                                                                0x00000040L
>+#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK                                                                  0x00000080L
>+#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK                                                                0x00000100L
>+#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK                                                                0x00000200L
>+#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK                                                                 0x00000400L
>+#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK                                                                  0x00000800L
>+#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK                                                                   0x0FFFF000L
>+#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK                                                                    0xF0000000L
>+//SDMA0_UTCL1_INV1
>+#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
>+#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_UTCL1_INV2
>+#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT                                                          0x0
>+#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK                                                            0xFFFFFFFFL
>+//SDMA0_UTCL1_RD_XNACK0
>+#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA0_UTCL1_RD_XNACK1
>+#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA0_UTCL1_WR_XNACK0
>+#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA0_UTCL1_WR_XNACK1
>+#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA0_UTCL1_TIMEOUT
>+#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
>+#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
>+#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
>+#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
>+//SDMA0_UTCL1_PAGE
>+#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
>+#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
>+#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
>+#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0x9
>+#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
>+#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
>+#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000001C0L
>+#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000200L
>+//SDMA0_POWER_CNTL_IDLE
>+#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT                                                                  0x0
>+#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT                                                                  0x10
>+#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT                                                                  0x18
>+#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK                                                                    0x0000FFFFL
>+#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK                                                                    0x00FF0000L
>+#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK                                                                    0xFF000000L
>+//SDMA0_RELAX_ORDERING_LUT
>+#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
>+#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
>+#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
>+#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
>+#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
>+#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
>+#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
>+#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
>+#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
>+#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
>+#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
>+#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
>+#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
>+#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
>+#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
>+#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
>+#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
>+#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
>+#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
>+#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
>+#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
>+#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
>+#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
>+#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
>+#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
>+#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
>+#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
>+#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
>+#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
>+#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
>+#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
>+#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
>+#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
>+#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
>+#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
>+#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
>+#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
>+#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
>+//SDMA0_CHICKEN_BITS_2
>+#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
>+#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
>+//SDMA0_STATUS3_REG
>+#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
>+#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
>+#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
>+#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x15
>+#define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x16
>+#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
>+#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
>+#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
>+#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x00200000L
>+#define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x03C00000L
>+//SDMA0_PHYSICAL_ADDR_LO
>+#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
>+#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
>+#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
>+#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
>+#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
>+#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
>+#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
>+#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
>+//SDMA0_PHYSICAL_ADDR_HI
>+#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
>+//SDMA0_PHASE2_QUANTUM
>+#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA0_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA0_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA0_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA0_ERROR_LOG
>+#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
>+#define SDMA0_ERROR_LOG__STATUS__SHIFT                                                                        0x10
>+#define SDMA0_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
>+#define SDMA0_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
>+//SDMA0_PUB_DUMMY_REG0
>+#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
>+#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_PUB_DUMMY_REG1
>+#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
>+#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_PUB_DUMMY_REG2
>+#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
>+#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_PUB_DUMMY_REG3
>+#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
>+#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_F32_COUNTER
>+#define SDMA0_F32_COUNTER__VALUE__SHIFT                                                                       0x0
>+#define SDMA0_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
>+//SDMA0_UNBREAKABLE
>+#define SDMA0_UNBREAKABLE__VALUE__SHIFT                                                                       0x0
>+#define SDMA0_UNBREAKABLE__VALUE_MASK                                                                         0x00000001L
>+//SDMA0_PERFMON_CNTL
>+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT                                                               0x0
>+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT                                                                0x1
>+#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT                                                                  0x2
>+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT                                                               0xa
>+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT                                                                0xb
>+#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT                                                                  0xc
>+#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK                                                                 0x00000001L
>+#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK                                                                  0x00000002L
>+#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK                                                                    0x000003FCL
>+#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK                                                                 0x00000400L
>+#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK                                                                  0x00000800L
>+#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK                                                                    0x000FF000L
>+//SDMA0_PERFCOUNTER0_RESULT
>+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA0_PERFCOUNTER1_RESULT
>+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE
>+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT                                                   0x0
>+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT                                                  0xe
>+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT                                                   0x1c
>+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK                                                     0x00003FFFL
>+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK                                                    0x0FFFC000L
>+#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK                                                     0x10000000L
>+//SDMA0_CRD_CNTL
>+#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
>+#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
>+#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
>+#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
>+//SDMA0_GPU_IOV_VIOLATION_LOG
>+#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT                                                  0x0
>+#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT                                         0x1
>+#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT                                                           0x2
>+#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT                                                   0x14
>+#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT                                                                0x15
>+#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT                                                              0x16
>+#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK                                                    0x00000001L
>+#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK                                           0x00000002L
>+#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK                                                             0x000FFFFCL
>+#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK                                                     0x00100000L
>+#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK                                                                  0x00200000L
>+#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK                                                                0x03C00000L
>+//SDMA0_ULV_CNTL
>+#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT                                                                     0x0
>+#define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT                                                              0x1b
>+#define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT                                                               0x1c
>+#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT                                                                  0x1d
>+#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT                                                                   0x1e
>+#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT                                                                     0x1f
>+#define SDMA0_ULV_CNTL__HYSTERESIS_MASK                                                                       0x0000001FL
>+#define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK                                                                0x08000000L
>+#define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK                                                                 0x10000000L
>+#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK                                                                    0x20000000L
>+#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK                                                                     0x40000000L
>+#define SDMA0_ULV_CNTL__ULV_STATUS_MASK                                                                       0x80000000L
>+//SDMA0_EA_DBIT_ADDR_DATA
>+#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
>+#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_EA_DBIT_ADDR_INDEX
>+#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
>+#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
>+//SDMA0_GPU_IOV_VIOLATION_LOG2
>+#define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                     0x0
>+#define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                       0x000000FFL
>+//SDMA0_GFX_RB_CNTL
>+#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
>+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
>+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
>+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
>+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
>+#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
>+#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
>+#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
>+#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
>+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
>+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
>+#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
>+#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
>+#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
>+//SDMA0_GFX_RB_BASE
>+#define SDMA0_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
>+#define SDMA0_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
>+//SDMA0_GFX_RB_BASE_HI
>+#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
>+//SDMA0_GFX_RB_RPTR
>+#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA0_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA0_GFX_RB_RPTR_HI
>+#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA0_GFX_RB_WPTR
>+#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA0_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA0_GFX_RB_WPTR_HI
>+#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA0_GFX_RB_WPTR_POLL_CNTL
>+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
>+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
>+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
>+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
>+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
>+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
>+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
>+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
>+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
>+#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
>+//SDMA0_GFX_RB_RPTR_ADDR_HI
>+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
>+#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
>+//SDMA0_GFX_RB_RPTR_ADDR_LO
>+#define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                        0x0
>+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
>+#define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                          0x00000001L
>+#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
>+//SDMA0_GFX_IB_CNTL
>+#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
>+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
>+#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
>+#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
>+#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
>+#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
>+//SDMA0_GFX_IB_RPTR
>+#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
>+#define SDMA0_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
>+//SDMA0_GFX_IB_OFFSET
>+#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
>+#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
>+//SDMA0_GFX_IB_BASE_LO
>+#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
>+#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
>+//SDMA0_GFX_IB_BASE_HI
>+#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_GFX_IB_SIZE
>+#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
>+#define SDMA0_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
>+//SDMA0_GFX_SKIP_CNTL
>+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
>+#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
>+//SDMA0_GFX_CONTEXT_STATUS
>+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
>+#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
>+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
>+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
>+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
>+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
>+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
>+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
>+#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
>+#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
>+#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
>+#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
>+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
>+#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
>+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
>+#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
>+//SDMA0_GFX_DOORBELL
>+#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
>+#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
>+#define SDMA0_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
>+#define SDMA0_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
>+//SDMA0_GFX_CONTEXT_CNTL
>+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
>+#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
>+//SDMA0_GFX_STATUS
>+#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
>+#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
>+#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
>+#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
>+//SDMA0_GFX_DOORBELL_LOG
>+#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
>+#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
>+#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
>+#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
>+//SDMA0_GFX_WATERMARK
>+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
>+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
>+#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
>+#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
>+//SDMA0_GFX_DOORBELL_OFFSET
>+#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
>+#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
>+//SDMA0_GFX_CSA_ADDR_LO
>+#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
>+#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
>+//SDMA0_GFX_CSA_ADDR_HI
>+#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_GFX_IB_SUB_REMAIN
>+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
>+#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x000FFFFFL
>+//SDMA0_GFX_PREEMPT
>+#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
>+#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
>+//SDMA0_GFX_DUMMY_REG
>+#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
>+#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI
>+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
>+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
>+//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
>+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
>+#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
>+//SDMA0_GFX_RB_AQL_CNTL
>+#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
>+#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
>+#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
>+#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
>+#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
>+#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
>+//SDMA0_GFX_MINOR_PTR_UPDATE
>+#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
>+#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
>+//SDMA0_GFX_MIDCMD_DATA0
>+#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
>+#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_GFX_MIDCMD_DATA1
>+#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
>+#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_GFX_MIDCMD_DATA2
>+#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
>+#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_GFX_MIDCMD_DATA3
>+#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
>+#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_GFX_MIDCMD_DATA4
>+#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
>+#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_GFX_MIDCMD_DATA5
>+#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
>+#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_GFX_MIDCMD_DATA6
>+#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
>+#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_GFX_MIDCMD_DATA7
>+#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
>+#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_GFX_MIDCMD_DATA8
>+#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
>+#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_GFX_MIDCMD_CNTL
>+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
>+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
>+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
>+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
>+#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
>+#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
>+#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
>+#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
>+//SDMA0_PAGE_RB_CNTL
>+#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA0_PAGE_RB_BASE
>+#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA0_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA0_PAGE_RB_BASE_HI
>+#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA0_PAGE_RB_RPTR
>+#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_PAGE_RB_RPTR_HI
>+#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_PAGE_RB_WPTR
>+#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_PAGE_RB_WPTR_HI
>+#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_PAGE_RB_WPTR_POLL_CNTL
>+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA0_PAGE_RB_RPTR_ADDR_HI
>+#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA0_PAGE_RB_RPTR_ADDR_LO
>+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA0_PAGE_IB_CNTL
>+#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA0_PAGE_IB_RPTR
>+#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA0_PAGE_IB_OFFSET
>+#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA0_PAGE_IB_BASE_LO
>+#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA0_PAGE_IB_BASE_HI
>+#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_PAGE_IB_SIZE
>+#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA0_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA0_PAGE_SKIP_CNTL
>+#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA0_PAGE_CONTEXT_STATUS
>+#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA0_PAGE_DOORBELL
>+#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA0_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA0_PAGE_STATUS
>+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA0_PAGE_DOORBELL_LOG
>+#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA0_PAGE_WATERMARK
>+#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA0_PAGE_DOORBELL_OFFSET
>+#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA0_PAGE_CSA_ADDR_LO
>+#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA0_PAGE_CSA_ADDR_HI
>+#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA0_PAGE_IB_SUB_REMAIN
>+#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA0_PAGE_PREEMPT
>+#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA0_PAGE_DUMMY_REG
>+#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI
>+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO
>+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA0_PAGE_RB_AQL_CNTL
>+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA0_PAGE_MINOR_PTR_UPDATE
>+#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA0_PAGE_MIDCMD_DATA0
>+#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_PAGE_MIDCMD_DATA1
>+#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_PAGE_MIDCMD_DATA2
>+#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_PAGE_MIDCMD_DATA3
>+#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_PAGE_MIDCMD_DATA4
>+#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_PAGE_MIDCMD_DATA5
>+#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_PAGE_MIDCMD_DATA6
>+#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_PAGE_MIDCMD_DATA7
>+#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_PAGE_MIDCMD_DATA8
>+#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_PAGE_MIDCMD_CNTL
>+#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA0_RLC0_RB_CNTL
>+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA0_RLC0_RB_BASE
>+#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA0_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA0_RLC0_RB_BASE_HI
>+#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA0_RLC0_RB_RPTR
>+#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC0_RB_RPTR_HI
>+#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC0_RB_WPTR
>+#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC0_RB_WPTR_HI
>+#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC0_RB_WPTR_POLL_CNTL
>+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA0_RLC0_RB_RPTR_ADDR_HI
>+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA0_RLC0_RB_RPTR_ADDR_LO
>+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA0_RLC0_IB_CNTL
>+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA0_RLC0_IB_RPTR
>+#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA0_RLC0_IB_OFFSET
>+#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA0_RLC0_IB_BASE_LO
>+#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA0_RLC0_IB_BASE_HI
>+#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC0_IB_SIZE
>+#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA0_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA0_RLC0_SKIP_CNTL
>+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA0_RLC0_CONTEXT_STATUS
>+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA0_RLC0_DOORBELL
>+#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA0_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA0_RLC0_STATUS
>+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA0_RLC0_DOORBELL_LOG
>+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA0_RLC0_WATERMARK
>+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA0_RLC0_DOORBELL_OFFSET
>+#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA0_RLC0_CSA_ADDR_LO
>+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA0_RLC0_CSA_ADDR_HI
>+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA0_RLC0_IB_SUB_REMAIN
>+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA0_RLC0_PREEMPT
>+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA0_RLC0_DUMMY_REG
>+#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI
>+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO
>+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA0_RLC0_RB_AQL_CNTL
>+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA0_RLC0_MINOR_PTR_UPDATE
>+#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA0_RLC0_MIDCMD_DATA0
>+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC0_MIDCMD_DATA1
>+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC0_MIDCMD_DATA2
>+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC0_MIDCMD_DATA3
>+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC0_MIDCMD_DATA4
>+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC0_MIDCMD_DATA5
>+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC0_MIDCMD_DATA6
>+#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC0_MIDCMD_DATA7
>+#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC0_MIDCMD_DATA8
>+#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC0_MIDCMD_CNTL
>+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA0_RLC1_RB_CNTL
>+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA0_RLC1_RB_BASE
>+#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA0_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA0_RLC1_RB_BASE_HI
>+#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA0_RLC1_RB_RPTR
>+#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC1_RB_RPTR_HI
>+#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC1_RB_WPTR
>+#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC1_RB_WPTR_HI
>+#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC1_RB_WPTR_POLL_CNTL
>+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA0_RLC1_RB_RPTR_ADDR_HI
>+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA0_RLC1_RB_RPTR_ADDR_LO
>+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA0_RLC1_IB_CNTL
>+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA0_RLC1_IB_RPTR
>+#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA0_RLC1_IB_OFFSET
>+#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA0_RLC1_IB_BASE_LO
>+#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA0_RLC1_IB_BASE_HI
>+#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC1_IB_SIZE
>+#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA0_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA0_RLC1_SKIP_CNTL
>+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA0_RLC1_CONTEXT_STATUS
>+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA0_RLC1_DOORBELL
>+#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA0_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA0_RLC1_STATUS
>+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA0_RLC1_DOORBELL_LOG
>+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA0_RLC1_WATERMARK
>+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA0_RLC1_DOORBELL_OFFSET
>+#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA0_RLC1_CSA_ADDR_LO
>+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA0_RLC1_CSA_ADDR_HI
>+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA0_RLC1_IB_SUB_REMAIN
>+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA0_RLC1_PREEMPT
>+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA0_RLC1_DUMMY_REG
>+#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI
>+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO
>+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA0_RLC1_RB_AQL_CNTL
>+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA0_RLC1_MINOR_PTR_UPDATE
>+#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA0_RLC1_MIDCMD_DATA0
>+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC1_MIDCMD_DATA1
>+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC1_MIDCMD_DATA2
>+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC1_MIDCMD_DATA3
>+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC1_MIDCMD_DATA4
>+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC1_MIDCMD_DATA5
>+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC1_MIDCMD_DATA6
>+#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC1_MIDCMD_DATA7
>+#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC1_MIDCMD_DATA8
>+#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC1_MIDCMD_CNTL
>+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA0_RLC2_RB_CNTL
>+#define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA0_RLC2_RB_BASE
>+#define SDMA0_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA0_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA0_RLC2_RB_BASE_HI
>+#define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA0_RLC2_RB_RPTR
>+#define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC2_RB_RPTR_HI
>+#define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC2_RB_WPTR
>+#define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC2_RB_WPTR_HI
>+#define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC2_RB_WPTR_POLL_CNTL
>+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA0_RLC2_RB_RPTR_ADDR_HI
>+#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA0_RLC2_RB_RPTR_ADDR_LO
>+#define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA0_RLC2_IB_CNTL
>+#define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA0_RLC2_IB_RPTR
>+#define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA0_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA0_RLC2_IB_OFFSET
>+#define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA0_RLC2_IB_BASE_LO
>+#define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA0_RLC2_IB_BASE_HI
>+#define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC2_IB_SIZE
>+#define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA0_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA0_RLC2_SKIP_CNTL
>+#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA0_RLC2_CONTEXT_STATUS
>+#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA0_RLC2_DOORBELL
>+#define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA0_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA0_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA0_RLC2_STATUS
>+#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA0_RLC2_DOORBELL_LOG
>+#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA0_RLC2_WATERMARK
>+#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA0_RLC2_DOORBELL_OFFSET
>+#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA0_RLC2_CSA_ADDR_LO
>+#define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA0_RLC2_CSA_ADDR_HI
>+#define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA0_RLC2_IB_SUB_REMAIN
>+#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA0_RLC2_PREEMPT
>+#define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA0_RLC2_DUMMY_REG
>+#define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI
>+#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO
>+#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA0_RLC2_RB_AQL_CNTL
>+#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA0_RLC2_MINOR_PTR_UPDATE
>+#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA0_RLC2_MIDCMD_DATA0
>+#define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC2_MIDCMD_DATA1
>+#define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC2_MIDCMD_DATA2
>+#define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC2_MIDCMD_DATA3
>+#define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC2_MIDCMD_DATA4
>+#define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC2_MIDCMD_DATA5
>+#define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC2_MIDCMD_DATA6
>+#define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC2_MIDCMD_DATA7
>+#define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC2_MIDCMD_DATA8
>+#define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC2_MIDCMD_CNTL
>+#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA0_RLC3_RB_CNTL
>+#define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA0_RLC3_RB_BASE
>+#define SDMA0_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA0_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA0_RLC3_RB_BASE_HI
>+#define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA0_RLC3_RB_RPTR
>+#define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC3_RB_RPTR_HI
>+#define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC3_RB_WPTR
>+#define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC3_RB_WPTR_HI
>+#define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC3_RB_WPTR_POLL_CNTL
>+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA0_RLC3_RB_RPTR_ADDR_HI
>+#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA0_RLC3_RB_RPTR_ADDR_LO
>+#define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA0_RLC3_IB_CNTL
>+#define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA0_RLC3_IB_RPTR
>+#define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA0_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA0_RLC3_IB_OFFSET
>+#define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA0_RLC3_IB_BASE_LO
>+#define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA0_RLC3_IB_BASE_HI
>+#define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC3_IB_SIZE
>+#define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA0_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA0_RLC3_SKIP_CNTL
>+#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA0_RLC3_CONTEXT_STATUS
>+#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA0_RLC3_DOORBELL
>+#define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA0_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA0_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA0_RLC3_STATUS
>+#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA0_RLC3_DOORBELL_LOG
>+#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA0_RLC3_WATERMARK
>+#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA0_RLC3_DOORBELL_OFFSET
>+#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA0_RLC3_CSA_ADDR_LO
>+#define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA0_RLC3_CSA_ADDR_HI
>+#define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA0_RLC3_IB_SUB_REMAIN
>+#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA0_RLC3_PREEMPT
>+#define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA0_RLC3_DUMMY_REG
>+#define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI
>+#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO
>+#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA0_RLC3_RB_AQL_CNTL
>+#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA0_RLC3_MINOR_PTR_UPDATE
>+#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA0_RLC3_MIDCMD_DATA0
>+#define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC3_MIDCMD_DATA1
>+#define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC3_MIDCMD_DATA2
>+#define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC3_MIDCMD_DATA3
>+#define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC3_MIDCMD_DATA4
>+#define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC3_MIDCMD_DATA5
>+#define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC3_MIDCMD_DATA6
>+#define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC3_MIDCMD_DATA7
>+#define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC3_MIDCMD_DATA8
>+#define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC3_MIDCMD_CNTL
>+#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA0_RLC4_RB_CNTL
>+#define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA0_RLC4_RB_BASE
>+#define SDMA0_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA0_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA0_RLC4_RB_BASE_HI
>+#define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA0_RLC4_RB_RPTR
>+#define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC4_RB_RPTR_HI
>+#define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC4_RB_WPTR
>+#define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC4_RB_WPTR_HI
>+#define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC4_RB_WPTR_POLL_CNTL
>+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA0_RLC4_RB_RPTR_ADDR_HI
>+#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA0_RLC4_RB_RPTR_ADDR_LO
>+#define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA0_RLC4_IB_CNTL
>+#define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA0_RLC4_IB_RPTR
>+#define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA0_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA0_RLC4_IB_OFFSET
>+#define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA0_RLC4_IB_BASE_LO
>+#define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA0_RLC4_IB_BASE_HI
>+#define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC4_IB_SIZE
>+#define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA0_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA0_RLC4_SKIP_CNTL
>+#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA0_RLC4_CONTEXT_STATUS
>+#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA0_RLC4_DOORBELL
>+#define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA0_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA0_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA0_RLC4_STATUS
>+#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA0_RLC4_DOORBELL_LOG
>+#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA0_RLC4_WATERMARK
>+#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA0_RLC4_DOORBELL_OFFSET
>+#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA0_RLC4_CSA_ADDR_LO
>+#define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA0_RLC4_CSA_ADDR_HI
>+#define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA0_RLC4_IB_SUB_REMAIN
>+#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA0_RLC4_PREEMPT
>+#define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA0_RLC4_DUMMY_REG
>+#define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI
>+#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO
>+#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA0_RLC4_RB_AQL_CNTL
>+#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA0_RLC4_MINOR_PTR_UPDATE
>+#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA0_RLC4_MIDCMD_DATA0
>+#define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC4_MIDCMD_DATA1
>+#define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC4_MIDCMD_DATA2
>+#define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC4_MIDCMD_DATA3
>+#define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC4_MIDCMD_DATA4
>+#define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC4_MIDCMD_DATA5
>+#define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC4_MIDCMD_DATA6
>+#define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC4_MIDCMD_DATA7
>+#define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC4_MIDCMD_DATA8
>+#define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC4_MIDCMD_CNTL
>+#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA0_RLC5_RB_CNTL
>+#define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA0_RLC5_RB_BASE
>+#define SDMA0_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA0_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA0_RLC5_RB_BASE_HI
>+#define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA0_RLC5_RB_RPTR
>+#define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC5_RB_RPTR_HI
>+#define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC5_RB_WPTR
>+#define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC5_RB_WPTR_HI
>+#define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC5_RB_WPTR_POLL_CNTL
>+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA0_RLC5_RB_RPTR_ADDR_HI
>+#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA0_RLC5_RB_RPTR_ADDR_LO
>+#define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA0_RLC5_IB_CNTL
>+#define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA0_RLC5_IB_RPTR
>+#define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA0_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA0_RLC5_IB_OFFSET
>+#define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA0_RLC5_IB_BASE_LO
>+#define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA0_RLC5_IB_BASE_HI
>+#define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC5_IB_SIZE
>+#define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA0_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA0_RLC5_SKIP_CNTL
>+#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA0_RLC5_CONTEXT_STATUS
>+#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA0_RLC5_DOORBELL
>+#define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA0_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA0_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA0_RLC5_STATUS
>+#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA0_RLC5_DOORBELL_LOG
>+#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA0_RLC5_WATERMARK
>+#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA0_RLC5_DOORBELL_OFFSET
>+#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA0_RLC5_CSA_ADDR_LO
>+#define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA0_RLC5_CSA_ADDR_HI
>+#define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA0_RLC5_IB_SUB_REMAIN
>+#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA0_RLC5_PREEMPT
>+#define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA0_RLC5_DUMMY_REG
>+#define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI
>+#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO
>+#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA0_RLC5_RB_AQL_CNTL
>+#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA0_RLC5_MINOR_PTR_UPDATE
>+#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA0_RLC5_MIDCMD_DATA0
>+#define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC5_MIDCMD_DATA1
>+#define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC5_MIDCMD_DATA2
>+#define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC5_MIDCMD_DATA3
>+#define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC5_MIDCMD_DATA4
>+#define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC5_MIDCMD_DATA5
>+#define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC5_MIDCMD_DATA6
>+#define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC5_MIDCMD_DATA7
>+#define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC5_MIDCMD_DATA8
>+#define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC5_MIDCMD_CNTL
>+#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA0_RLC6_RB_CNTL
>+#define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA0_RLC6_RB_BASE
>+#define SDMA0_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA0_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA0_RLC6_RB_BASE_HI
>+#define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA0_RLC6_RB_RPTR
>+#define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC6_RB_RPTR_HI
>+#define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC6_RB_WPTR
>+#define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC6_RB_WPTR_HI
>+#define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC6_RB_WPTR_POLL_CNTL
>+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA0_RLC6_RB_RPTR_ADDR_HI
>+#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA0_RLC6_RB_RPTR_ADDR_LO
>+#define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA0_RLC6_IB_CNTL
>+#define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA0_RLC6_IB_RPTR
>+#define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA0_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA0_RLC6_IB_OFFSET
>+#define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA0_RLC6_IB_BASE_LO
>+#define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA0_RLC6_IB_BASE_HI
>+#define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC6_IB_SIZE
>+#define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA0_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA0_RLC6_SKIP_CNTL
>+#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA0_RLC6_CONTEXT_STATUS
>+#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA0_RLC6_DOORBELL
>+#define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA0_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA0_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA0_RLC6_STATUS
>+#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA0_RLC6_DOORBELL_LOG
>+#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA0_RLC6_WATERMARK
>+#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA0_RLC6_DOORBELL_OFFSET
>+#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA0_RLC6_CSA_ADDR_LO
>+#define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA0_RLC6_CSA_ADDR_HI
>+#define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA0_RLC6_IB_SUB_REMAIN
>+#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA0_RLC6_PREEMPT
>+#define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA0_RLC6_DUMMY_REG
>+#define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI
>+#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO
>+#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA0_RLC6_RB_AQL_CNTL
>+#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA0_RLC6_MINOR_PTR_UPDATE
>+#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA0_RLC6_MIDCMD_DATA0
>+#define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC6_MIDCMD_DATA1
>+#define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC6_MIDCMD_DATA2
>+#define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC6_MIDCMD_DATA3
>+#define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC6_MIDCMD_DATA4
>+#define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC6_MIDCMD_DATA5
>+#define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC6_MIDCMD_DATA6
>+#define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC6_MIDCMD_DATA7
>+#define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC6_MIDCMD_DATA8
>+#define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC6_MIDCMD_CNTL
>+#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA0_RLC7_RB_CNTL
>+#define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA0_RLC7_RB_BASE
>+#define SDMA0_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA0_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA0_RLC7_RB_BASE_HI
>+#define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA0_RLC7_RB_RPTR
>+#define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC7_RB_RPTR_HI
>+#define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC7_RB_WPTR
>+#define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA0_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA0_RLC7_RB_WPTR_HI
>+#define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA0_RLC7_RB_WPTR_POLL_CNTL
>+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA0_RLC7_RB_RPTR_ADDR_HI
>+#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA0_RLC7_RB_RPTR_ADDR_LO
>+#define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA0_RLC7_IB_CNTL
>+#define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA0_RLC7_IB_RPTR
>+#define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA0_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA0_RLC7_IB_OFFSET
>+#define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA0_RLC7_IB_BASE_LO
>+#define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA0_RLC7_IB_BASE_HI
>+#define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC7_IB_SIZE
>+#define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA0_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA0_RLC7_SKIP_CNTL
>+#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA0_RLC7_CONTEXT_STATUS
>+#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA0_RLC7_DOORBELL
>+#define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA0_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA0_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA0_RLC7_STATUS
>+#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA0_RLC7_DOORBELL_LOG
>+#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA0_RLC7_WATERMARK
>+#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA0_RLC7_DOORBELL_OFFSET
>+#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA0_RLC7_CSA_ADDR_LO
>+#define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA0_RLC7_CSA_ADDR_HI
>+#define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA0_RLC7_IB_SUB_REMAIN
>+#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA0_RLC7_PREEMPT
>+#define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA0_RLC7_DUMMY_REG
>+#define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI
>+#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO
>+#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA0_RLC7_RB_AQL_CNTL
>+#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA0_RLC7_MINOR_PTR_UPDATE
>+#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA0_RLC7_MIDCMD_DATA0
>+#define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC7_MIDCMD_DATA1
>+#define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC7_MIDCMD_DATA2
>+#define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC7_MIDCMD_DATA3
>+#define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC7_MIDCMD_DATA4
>+#define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC7_MIDCMD_DATA5
>+#define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC7_MIDCMD_DATA6
>+#define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC7_MIDCMD_DATA7
>+#define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC7_MIDCMD_DATA8
>+#define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA0_RLC7_MIDCMD_CNTL
>+#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_offset.h	2019-08-31 15:01:11.931736175 -0500
>@@ -0,0 +1,1043 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma1_4_2_2_OFFSET_HEADER
>+#define _sdma1_4_2_2_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: sdma1_sdma1dec
>+// base address: 0x6180
>+#define mmSDMA1_UCODE_ADDR                                                                             0x0000
>+#define mmSDMA1_UCODE_ADDR_BASE_IDX                                                                    0
>+#define mmSDMA1_UCODE_DATA                                                                             0x0001
>+#define mmSDMA1_UCODE_DATA_BASE_IDX                                                                    0
>+#define mmSDMA1_VM_CNTL                                                                                0x0004
>+#define mmSDMA1_VM_CNTL_BASE_IDX                                                                       0
>+#define mmSDMA1_VM_CTX_LO                                                                              0x0005
>+#define mmSDMA1_VM_CTX_LO_BASE_IDX                                                                     0
>+#define mmSDMA1_VM_CTX_HI                                                                              0x0006
>+#define mmSDMA1_VM_CTX_HI_BASE_IDX                                                                     0
>+#define mmSDMA1_ACTIVE_FCN_ID                                                                          0x0007
>+#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX                                                                 0
>+#define mmSDMA1_VM_CTX_CNTL                                                                            0x0008
>+#define mmSDMA1_VM_CTX_CNTL_BASE_IDX                                                                   0
>+#define mmSDMA1_VIRT_RESET_REQ                                                                         0x0009
>+#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX                                                                0
>+#define mmSDMA1_VF_ENABLE                                                                              0x000a
>+#define mmSDMA1_VF_ENABLE_BASE_IDX                                                                     0
>+#define mmSDMA1_CONTEXT_REG_TYPE0                                                                      0x000b
>+#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX                                                             0
>+#define mmSDMA1_CONTEXT_REG_TYPE1                                                                      0x000c
>+#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX                                                             0
>+#define mmSDMA1_CONTEXT_REG_TYPE2                                                                      0x000d
>+#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX                                                             0
>+#define mmSDMA1_CONTEXT_REG_TYPE3                                                                      0x000e
>+#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX                                                             0
>+#define mmSDMA1_PUB_REG_TYPE0                                                                          0x000f
>+#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX                                                                 0
>+#define mmSDMA1_PUB_REG_TYPE1                                                                          0x0010
>+#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX                                                                 0
>+#define mmSDMA1_PUB_REG_TYPE2                                                                          0x0011
>+#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX                                                                 0
>+#define mmSDMA1_PUB_REG_TYPE3                                                                          0x0012
>+#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX                                                                 0
>+#define mmSDMA1_MMHUB_CNTL                                                                             0x0013
>+#define mmSDMA1_MMHUB_CNTL_BASE_IDX                                                                    0
>+#define mmSDMA1_CONTEXT_GROUP_BOUNDARY                                                                 0x0019
>+#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX                                                        0
>+#define mmSDMA1_POWER_CNTL                                                                             0x001a
>+#define mmSDMA1_POWER_CNTL_BASE_IDX                                                                    0
>+#define mmSDMA1_CLK_CTRL                                                                               0x001b
>+#define mmSDMA1_CLK_CTRL_BASE_IDX                                                                      0
>+#define mmSDMA1_CNTL                                                                                   0x001c
>+#define mmSDMA1_CNTL_BASE_IDX                                                                          0
>+#define mmSDMA1_CHICKEN_BITS                                                                           0x001d
>+#define mmSDMA1_CHICKEN_BITS_BASE_IDX                                                                  0
>+#define mmSDMA1_GB_ADDR_CONFIG                                                                         0x001e
>+#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX                                                                0
>+#define mmSDMA1_GB_ADDR_CONFIG_READ                                                                    0x001f
>+#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX                                                           0
>+#define mmSDMA1_RB_RPTR_FETCH_HI                                                                       0x0020
>+#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX                                                              0
>+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0021
>+#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      0
>+#define mmSDMA1_RB_RPTR_FETCH                                                                          0x0022
>+#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX                                                                 0
>+#define mmSDMA1_IB_OFFSET_FETCH                                                                        0x0023
>+#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX                                                               0
>+#define mmSDMA1_PROGRAM                                                                                0x0024
>+#define mmSDMA1_PROGRAM_BASE_IDX                                                                       0
>+#define mmSDMA1_STATUS_REG                                                                             0x0025
>+#define mmSDMA1_STATUS_REG_BASE_IDX                                                                    0
>+#define mmSDMA1_STATUS1_REG                                                                            0x0026
>+#define mmSDMA1_STATUS1_REG_BASE_IDX                                                                   0
>+#define mmSDMA1_RD_BURST_CNTL                                                                          0x0027
>+#define mmSDMA1_RD_BURST_CNTL_BASE_IDX                                                                 0
>+#define mmSDMA1_HBM_PAGE_CONFIG                                                                        0x0028
>+#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX                                                               0
>+#define mmSDMA1_UCODE_CHECKSUM                                                                         0x0029
>+#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX                                                                0
>+#define mmSDMA1_F32_CNTL                                                                               0x002a
>+#define mmSDMA1_F32_CNTL_BASE_IDX                                                                      0
>+#define mmSDMA1_FREEZE                                                                                 0x002b
>+#define mmSDMA1_FREEZE_BASE_IDX                                                                        0
>+#define mmSDMA1_PHASE0_QUANTUM                                                                         0x002c
>+#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX                                                                0
>+#define mmSDMA1_PHASE1_QUANTUM                                                                         0x002d
>+#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX                                                                0
>+#define mmSDMA1_EDC_CONFIG                                                                             0x0032
>+#define mmSDMA1_EDC_CONFIG_BASE_IDX                                                                    0
>+#define mmSDMA1_BA_THRESHOLD                                                                           0x0033
>+#define mmSDMA1_BA_THRESHOLD_BASE_IDX                                                                  0
>+#define mmSDMA1_ID                                                                                     0x0034
>+#define mmSDMA1_ID_BASE_IDX                                                                            0
>+#define mmSDMA1_VERSION                                                                                0x0035
>+#define mmSDMA1_VERSION_BASE_IDX                                                                       0
>+#define mmSDMA1_EDC_COUNTER                                                                            0x0036
>+#define mmSDMA1_EDC_COUNTER_BASE_IDX                                                                   0
>+#define mmSDMA1_EDC_COUNTER_CLEAR                                                                      0x0037
>+#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX                                                             0
>+#define mmSDMA1_STATUS2_REG                                                                            0x0038
>+#define mmSDMA1_STATUS2_REG_BASE_IDX                                                                   0
>+#define mmSDMA1_ATOMIC_CNTL                                                                            0x0039
>+#define mmSDMA1_ATOMIC_CNTL_BASE_IDX                                                                   0
>+#define mmSDMA1_ATOMIC_PREOP_LO                                                                        0x003a
>+#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX                                                               0
>+#define mmSDMA1_ATOMIC_PREOP_HI                                                                        0x003b
>+#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX                                                               0
>+#define mmSDMA1_UTCL1_CNTL                                                                             0x003c
>+#define mmSDMA1_UTCL1_CNTL_BASE_IDX                                                                    0
>+#define mmSDMA1_UTCL1_WATERMK                                                                          0x003d
>+#define mmSDMA1_UTCL1_WATERMK_BASE_IDX                                                                 0
>+#define mmSDMA1_UTCL1_RD_STATUS                                                                        0x003e
>+#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX                                                               0
>+#define mmSDMA1_UTCL1_WR_STATUS                                                                        0x003f
>+#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX                                                               0
>+#define mmSDMA1_UTCL1_INV0                                                                             0x0040
>+#define mmSDMA1_UTCL1_INV0_BASE_IDX                                                                    0
>+#define mmSDMA1_UTCL1_INV1                                                                             0x0041
>+#define mmSDMA1_UTCL1_INV1_BASE_IDX                                                                    0
>+#define mmSDMA1_UTCL1_INV2                                                                             0x0042
>+#define mmSDMA1_UTCL1_INV2_BASE_IDX                                                                    0
>+#define mmSDMA1_UTCL1_RD_XNACK0                                                                        0x0043
>+#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX                                                               0
>+#define mmSDMA1_UTCL1_RD_XNACK1                                                                        0x0044
>+#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX                                                               0
>+#define mmSDMA1_UTCL1_WR_XNACK0                                                                        0x0045
>+#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX                                                               0
>+#define mmSDMA1_UTCL1_WR_XNACK1                                                                        0x0046
>+#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX                                                               0
>+#define mmSDMA1_UTCL1_TIMEOUT                                                                          0x0047
>+#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX                                                                 0
>+#define mmSDMA1_UTCL1_PAGE                                                                             0x0048
>+#define mmSDMA1_UTCL1_PAGE_BASE_IDX                                                                    0
>+#define mmSDMA1_POWER_CNTL_IDLE                                                                        0x0049
>+#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX                                                               0
>+#define mmSDMA1_RELAX_ORDERING_LUT                                                                     0x004a
>+#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX                                                            0
>+#define mmSDMA1_CHICKEN_BITS_2                                                                         0x004b
>+#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX                                                                0
>+#define mmSDMA1_STATUS3_REG                                                                            0x004c
>+#define mmSDMA1_STATUS3_REG_BASE_IDX                                                                   0
>+#define mmSDMA1_PHYSICAL_ADDR_LO                                                                       0x004d
>+#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA1_PHYSICAL_ADDR_HI                                                                       0x004e
>+#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA1_PHASE2_QUANTUM                                                                         0x004f
>+#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX                                                                0
>+#define mmSDMA1_ERROR_LOG                                                                              0x0050
>+#define mmSDMA1_ERROR_LOG_BASE_IDX                                                                     0
>+#define mmSDMA1_PUB_DUMMY_REG0                                                                         0x0051
>+#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX                                                                0
>+#define mmSDMA1_PUB_DUMMY_REG1                                                                         0x0052
>+#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX                                                                0
>+#define mmSDMA1_PUB_DUMMY_REG2                                                                         0x0053
>+#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX                                                                0
>+#define mmSDMA1_PUB_DUMMY_REG3                                                                         0x0054
>+#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX                                                                0
>+#define mmSDMA1_F32_COUNTER                                                                            0x0055
>+#define mmSDMA1_F32_COUNTER_BASE_IDX                                                                   0
>+#define mmSDMA1_UNBREAKABLE                                                                            0x0056
>+#define mmSDMA1_UNBREAKABLE_BASE_IDX                                                                   0
>+#define mmSDMA1_PERFMON_CNTL                                                                           0x0057
>+#define mmSDMA1_PERFMON_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_PERFCOUNTER0_RESULT                                                                    0x0058
>+#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX                                                           0
>+#define mmSDMA1_PERFCOUNTER1_RESULT                                                                    0x0059
>+#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX                                                           0
>+#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE                                                            0x005a
>+#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX                                                   0
>+#define mmSDMA1_CRD_CNTL                                                                               0x005b
>+#define mmSDMA1_CRD_CNTL_BASE_IDX                                                                      0
>+#define mmSDMA1_GPU_IOV_VIOLATION_LOG                                                                  0x005d
>+#define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX                                                         0
>+#define mmSDMA1_ULV_CNTL                                                                               0x005e
>+#define mmSDMA1_ULV_CNTL_BASE_IDX                                                                      0
>+#define mmSDMA1_EA_DBIT_ADDR_DATA                                                                      0x0060
>+#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX                                                             0
>+#define mmSDMA1_EA_DBIT_ADDR_INDEX                                                                     0x0061
>+#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            0
>+#define mmSDMA1_GPU_IOV_VIOLATION_LOG2                                                                 0x0062
>+#define mmSDMA1_GPU_IOV_VIOLATION_LOG2_BASE_IDX                                                        0
>+#define mmSDMA1_GFX_RB_CNTL                                                                            0x0080
>+#define mmSDMA1_GFX_RB_CNTL_BASE_IDX                                                                   0
>+#define mmSDMA1_GFX_RB_BASE                                                                            0x0081
>+#define mmSDMA1_GFX_RB_BASE_BASE_IDX                                                                   0
>+#define mmSDMA1_GFX_RB_BASE_HI                                                                         0x0082
>+#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX                                                                0
>+#define mmSDMA1_GFX_RB_RPTR                                                                            0x0083
>+#define mmSDMA1_GFX_RB_RPTR_BASE_IDX                                                                   0
>+#define mmSDMA1_GFX_RB_RPTR_HI                                                                         0x0084
>+#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX                                                                0
>+#define mmSDMA1_GFX_RB_WPTR                                                                            0x0085
>+#define mmSDMA1_GFX_RB_WPTR_BASE_IDX                                                                   0
>+#define mmSDMA1_GFX_RB_WPTR_HI                                                                         0x0086
>+#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX                                                                0
>+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
>+#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
>+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI                                                                    0x0088
>+#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
>+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO                                                                    0x0089
>+#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
>+#define mmSDMA1_GFX_IB_CNTL                                                                            0x008a
>+#define mmSDMA1_GFX_IB_CNTL_BASE_IDX                                                                   0
>+#define mmSDMA1_GFX_IB_RPTR                                                                            0x008b
>+#define mmSDMA1_GFX_IB_RPTR_BASE_IDX                                                                   0
>+#define mmSDMA1_GFX_IB_OFFSET                                                                          0x008c
>+#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX                                                                 0
>+#define mmSDMA1_GFX_IB_BASE_LO                                                                         0x008d
>+#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX                                                                0
>+#define mmSDMA1_GFX_IB_BASE_HI                                                                         0x008e
>+#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX                                                                0
>+#define mmSDMA1_GFX_IB_SIZE                                                                            0x008f
>+#define mmSDMA1_GFX_IB_SIZE_BASE_IDX                                                                   0
>+#define mmSDMA1_GFX_SKIP_CNTL                                                                          0x0090
>+#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX                                                                 0
>+#define mmSDMA1_GFX_CONTEXT_STATUS                                                                     0x0091
>+#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX                                                            0
>+#define mmSDMA1_GFX_DOORBELL                                                                           0x0092
>+#define mmSDMA1_GFX_DOORBELL_BASE_IDX                                                                  0
>+#define mmSDMA1_GFX_CONTEXT_CNTL                                                                       0x0093
>+#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_GFX_STATUS                                                                             0x00a8
>+#define mmSDMA1_GFX_STATUS_BASE_IDX                                                                    0
>+#define mmSDMA1_GFX_DOORBELL_LOG                                                                       0x00a9
>+#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX                                                              0
>+#define mmSDMA1_GFX_WATERMARK                                                                          0x00aa
>+#define mmSDMA1_GFX_WATERMARK_BASE_IDX                                                                 0
>+#define mmSDMA1_GFX_DOORBELL_OFFSET                                                                    0x00ab
>+#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX                                                           0
>+#define mmSDMA1_GFX_CSA_ADDR_LO                                                                        0x00ac
>+#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX                                                               0
>+#define mmSDMA1_GFX_CSA_ADDR_HI                                                                        0x00ad
>+#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_GFX_IB_SUB_REMAIN                                                                      0x00af
>+#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX                                                             0
>+#define mmSDMA1_GFX_PREEMPT                                                                            0x00b0
>+#define mmSDMA1_GFX_PREEMPT_BASE_IDX                                                                   0
>+#define mmSDMA1_GFX_DUMMY_REG                                                                          0x00b1
>+#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX                                                                 0
>+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x00b2
>+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
>+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x00b3
>+#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
>+#define mmSDMA1_GFX_RB_AQL_CNTL                                                                        0x00b4
>+#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX                                                               0
>+#define mmSDMA1_GFX_MINOR_PTR_UPDATE                                                                   0x00b5
>+#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          0
>+#define mmSDMA1_GFX_MIDCMD_DATA0                                                                       0x00c0
>+#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX                                                              0
>+#define mmSDMA1_GFX_MIDCMD_DATA1                                                                       0x00c1
>+#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX                                                              0
>+#define mmSDMA1_GFX_MIDCMD_DATA2                                                                       0x00c2
>+#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX                                                              0
>+#define mmSDMA1_GFX_MIDCMD_DATA3                                                                       0x00c3
>+#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX                                                              0
>+#define mmSDMA1_GFX_MIDCMD_DATA4                                                                       0x00c4
>+#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX                                                              0
>+#define mmSDMA1_GFX_MIDCMD_DATA5                                                                       0x00c5
>+#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX                                                              0
>+#define mmSDMA1_GFX_MIDCMD_DATA6                                                                       0x00c6
>+#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX                                                              0
>+#define mmSDMA1_GFX_MIDCMD_DATA7                                                                       0x00c7
>+#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX                                                              0
>+#define mmSDMA1_GFX_MIDCMD_DATA8                                                                       0x00c8
>+#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX                                                              0
>+#define mmSDMA1_GFX_MIDCMD_CNTL                                                                        0x00c9
>+#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX                                                               0
>+#define mmSDMA1_PAGE_RB_CNTL                                                                           0x00d8
>+#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_PAGE_RB_BASE                                                                           0x00d9
>+#define mmSDMA1_PAGE_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA1_PAGE_RB_BASE_HI                                                                        0x00da
>+#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_PAGE_RB_RPTR                                                                           0x00db
>+#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_PAGE_RB_RPTR_HI                                                                        0x00dc
>+#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_PAGE_RB_WPTR                                                                           0x00dd
>+#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_PAGE_RB_WPTR_HI                                                                        0x00de
>+#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL                                                                 0x00df
>+#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI                                                                   0x00e0
>+#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO                                                                   0x00e1
>+#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA1_PAGE_IB_CNTL                                                                           0x00e2
>+#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_PAGE_IB_RPTR                                                                           0x00e3
>+#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_PAGE_IB_OFFSET                                                                         0x00e4
>+#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA1_PAGE_IB_BASE_LO                                                                        0x00e5
>+#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA1_PAGE_IB_BASE_HI                                                                        0x00e6
>+#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_PAGE_IB_SIZE                                                                           0x00e7
>+#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA1_PAGE_SKIP_CNTL                                                                         0x00e8
>+#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA1_PAGE_CONTEXT_STATUS                                                                    0x00e9
>+#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA1_PAGE_DOORBELL                                                                          0x00ea
>+#define mmSDMA1_PAGE_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA1_PAGE_STATUS                                                                            0x0100
>+#define mmSDMA1_PAGE_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA1_PAGE_DOORBELL_LOG                                                                      0x0101
>+#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA1_PAGE_WATERMARK                                                                         0x0102
>+#define mmSDMA1_PAGE_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA1_PAGE_DOORBELL_OFFSET                                                                   0x0103
>+#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA1_PAGE_CSA_ADDR_LO                                                                       0x0104
>+#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA1_PAGE_CSA_ADDR_HI                                                                       0x0105
>+#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA1_PAGE_IB_SUB_REMAIN                                                                     0x0107
>+#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA1_PAGE_PREEMPT                                                                           0x0108
>+#define mmSDMA1_PAGE_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA1_PAGE_DUMMY_REG                                                                         0x0109
>+#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x010a
>+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x010b
>+#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA1_PAGE_RB_AQL_CNTL                                                                       0x010c
>+#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_PAGE_MINOR_PTR_UPDATE                                                                  0x010d
>+#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA1_PAGE_MIDCMD_DATA0                                                                      0x0118
>+#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA1_PAGE_MIDCMD_DATA1                                                                      0x0119
>+#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA1_PAGE_MIDCMD_DATA2                                                                      0x011a
>+#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA1_PAGE_MIDCMD_DATA3                                                                      0x011b
>+#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA1_PAGE_MIDCMD_DATA4                                                                      0x011c
>+#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA1_PAGE_MIDCMD_DATA5                                                                      0x011d
>+#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA1_PAGE_MIDCMD_DATA6                                                                      0x011e
>+#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA1_PAGE_MIDCMD_DATA7                                                                      0x011f
>+#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA1_PAGE_MIDCMD_DATA8                                                                      0x0120
>+#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA1_PAGE_MIDCMD_CNTL                                                                       0x0121
>+#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC0_RB_CNTL                                                                           0x0130
>+#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC0_RB_BASE                                                                           0x0131
>+#define mmSDMA1_RLC0_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC0_RB_BASE_HI                                                                        0x0132
>+#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC0_RB_RPTR                                                                           0x0133
>+#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC0_RB_RPTR_HI                                                                        0x0134
>+#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC0_RB_WPTR                                                                           0x0135
>+#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC0_RB_WPTR_HI                                                                        0x0136
>+#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0137
>+#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI                                                                   0x0138
>+#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO                                                                   0x0139
>+#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA1_RLC0_IB_CNTL                                                                           0x013a
>+#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC0_IB_RPTR                                                                           0x013b
>+#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC0_IB_OFFSET                                                                         0x013c
>+#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA1_RLC0_IB_BASE_LO                                                                        0x013d
>+#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA1_RLC0_IB_BASE_HI                                                                        0x013e
>+#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC0_IB_SIZE                                                                           0x013f
>+#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC0_SKIP_CNTL                                                                         0x0140
>+#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA1_RLC0_CONTEXT_STATUS                                                                    0x0141
>+#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA1_RLC0_DOORBELL                                                                          0x0142
>+#define mmSDMA1_RLC0_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA1_RLC0_STATUS                                                                            0x0158
>+#define mmSDMA1_RLC0_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA1_RLC0_DOORBELL_LOG                                                                      0x0159
>+#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA1_RLC0_WATERMARK                                                                         0x015a
>+#define mmSDMA1_RLC0_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA1_RLC0_DOORBELL_OFFSET                                                                   0x015b
>+#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA1_RLC0_CSA_ADDR_LO                                                                       0x015c
>+#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA1_RLC0_CSA_ADDR_HI                                                                       0x015d
>+#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA1_RLC0_IB_SUB_REMAIN                                                                     0x015f
>+#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA1_RLC0_PREEMPT                                                                           0x0160
>+#define mmSDMA1_RLC0_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC0_DUMMY_REG                                                                         0x0161
>+#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0162
>+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0163
>+#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA1_RLC0_RB_AQL_CNTL                                                                       0x0164
>+#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC0_MINOR_PTR_UPDATE                                                                  0x0165
>+#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA1_RLC0_MIDCMD_DATA0                                                                      0x0170
>+#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA1_RLC0_MIDCMD_DATA1                                                                      0x0171
>+#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA1_RLC0_MIDCMD_DATA2                                                                      0x0172
>+#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA1_RLC0_MIDCMD_DATA3                                                                      0x0173
>+#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA1_RLC0_MIDCMD_DATA4                                                                      0x0174
>+#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA1_RLC0_MIDCMD_DATA5                                                                      0x0175
>+#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA1_RLC0_MIDCMD_DATA6                                                                      0x0176
>+#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA1_RLC0_MIDCMD_DATA7                                                                      0x0177
>+#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA1_RLC0_MIDCMD_DATA8                                                                      0x0178
>+#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA1_RLC0_MIDCMD_CNTL                                                                       0x0179
>+#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC1_RB_CNTL                                                                           0x0188
>+#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC1_RB_BASE                                                                           0x0189
>+#define mmSDMA1_RLC1_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC1_RB_BASE_HI                                                                        0x018a
>+#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC1_RB_RPTR                                                                           0x018b
>+#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC1_RB_RPTR_HI                                                                        0x018c
>+#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC1_RB_WPTR                                                                           0x018d
>+#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC1_RB_WPTR_HI                                                                        0x018e
>+#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL                                                                 0x018f
>+#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI                                                                   0x0190
>+#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO                                                                   0x0191
>+#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA1_RLC1_IB_CNTL                                                                           0x0192
>+#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC1_IB_RPTR                                                                           0x0193
>+#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC1_IB_OFFSET                                                                         0x0194
>+#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA1_RLC1_IB_BASE_LO                                                                        0x0195
>+#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA1_RLC1_IB_BASE_HI                                                                        0x0196
>+#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC1_IB_SIZE                                                                           0x0197
>+#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC1_SKIP_CNTL                                                                         0x0198
>+#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA1_RLC1_CONTEXT_STATUS                                                                    0x0199
>+#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA1_RLC1_DOORBELL                                                                          0x019a
>+#define mmSDMA1_RLC1_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA1_RLC1_STATUS                                                                            0x01b0
>+#define mmSDMA1_RLC1_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA1_RLC1_DOORBELL_LOG                                                                      0x01b1
>+#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA1_RLC1_WATERMARK                                                                         0x01b2
>+#define mmSDMA1_RLC1_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA1_RLC1_DOORBELL_OFFSET                                                                   0x01b3
>+#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA1_RLC1_CSA_ADDR_LO                                                                       0x01b4
>+#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA1_RLC1_CSA_ADDR_HI                                                                       0x01b5
>+#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA1_RLC1_IB_SUB_REMAIN                                                                     0x01b7
>+#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA1_RLC1_PREEMPT                                                                           0x01b8
>+#define mmSDMA1_RLC1_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC1_DUMMY_REG                                                                         0x01b9
>+#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x01ba
>+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x01bb
>+#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA1_RLC1_RB_AQL_CNTL                                                                       0x01bc
>+#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC1_MINOR_PTR_UPDATE                                                                  0x01bd
>+#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA1_RLC1_MIDCMD_DATA0                                                                      0x01c8
>+#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA1_RLC1_MIDCMD_DATA1                                                                      0x01c9
>+#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA1_RLC1_MIDCMD_DATA2                                                                      0x01ca
>+#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA1_RLC1_MIDCMD_DATA3                                                                      0x01cb
>+#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA1_RLC1_MIDCMD_DATA4                                                                      0x01cc
>+#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA1_RLC1_MIDCMD_DATA5                                                                      0x01cd
>+#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA1_RLC1_MIDCMD_DATA6                                                                      0x01ce
>+#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA1_RLC1_MIDCMD_DATA7                                                                      0x01cf
>+#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA1_RLC1_MIDCMD_DATA8                                                                      0x01d0
>+#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA1_RLC1_MIDCMD_CNTL                                                                       0x01d1
>+#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC2_RB_CNTL                                                                           0x01e0
>+#define mmSDMA1_RLC2_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC2_RB_BASE                                                                           0x01e1
>+#define mmSDMA1_RLC2_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC2_RB_BASE_HI                                                                        0x01e2
>+#define mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC2_RB_RPTR                                                                           0x01e3
>+#define mmSDMA1_RLC2_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC2_RB_RPTR_HI                                                                        0x01e4
>+#define mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC2_RB_WPTR                                                                           0x01e5
>+#define mmSDMA1_RLC2_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC2_RB_WPTR_HI                                                                        0x01e6
>+#define mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL                                                                 0x01e7
>+#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI                                                                   0x01e8
>+#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO                                                                   0x01e9
>+#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA1_RLC2_IB_CNTL                                                                           0x01ea
>+#define mmSDMA1_RLC2_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC2_IB_RPTR                                                                           0x01eb
>+#define mmSDMA1_RLC2_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC2_IB_OFFSET                                                                         0x01ec
>+#define mmSDMA1_RLC2_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA1_RLC2_IB_BASE_LO                                                                        0x01ed
>+#define mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA1_RLC2_IB_BASE_HI                                                                        0x01ee
>+#define mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC2_IB_SIZE                                                                           0x01ef
>+#define mmSDMA1_RLC2_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC2_SKIP_CNTL                                                                         0x01f0
>+#define mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA1_RLC2_CONTEXT_STATUS                                                                    0x01f1
>+#define mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA1_RLC2_DOORBELL                                                                          0x01f2
>+#define mmSDMA1_RLC2_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA1_RLC2_STATUS                                                                            0x0208
>+#define mmSDMA1_RLC2_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA1_RLC2_DOORBELL_LOG                                                                      0x0209
>+#define mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA1_RLC2_WATERMARK                                                                         0x020a
>+#define mmSDMA1_RLC2_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA1_RLC2_DOORBELL_OFFSET                                                                   0x020b
>+#define mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA1_RLC2_CSA_ADDR_LO                                                                       0x020c
>+#define mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA1_RLC2_CSA_ADDR_HI                                                                       0x020d
>+#define mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA1_RLC2_IB_SUB_REMAIN                                                                     0x020f
>+#define mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA1_RLC2_PREEMPT                                                                           0x0210
>+#define mmSDMA1_RLC2_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC2_DUMMY_REG                                                                         0x0211
>+#define mmSDMA1_RLC2_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0212
>+#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0213
>+#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA1_RLC2_RB_AQL_CNTL                                                                       0x0214
>+#define mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC2_MINOR_PTR_UPDATE                                                                  0x0215
>+#define mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA1_RLC2_MIDCMD_DATA0                                                                      0x0220
>+#define mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA1_RLC2_MIDCMD_DATA1                                                                      0x0221
>+#define mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA1_RLC2_MIDCMD_DATA2                                                                      0x0222
>+#define mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA1_RLC2_MIDCMD_DATA3                                                                      0x0223
>+#define mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA1_RLC2_MIDCMD_DATA4                                                                      0x0224
>+#define mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA1_RLC2_MIDCMD_DATA5                                                                      0x0225
>+#define mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA1_RLC2_MIDCMD_DATA6                                                                      0x0226
>+#define mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA1_RLC2_MIDCMD_DATA7                                                                      0x0227
>+#define mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA1_RLC2_MIDCMD_DATA8                                                                      0x0228
>+#define mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA1_RLC2_MIDCMD_CNTL                                                                       0x0229
>+#define mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC3_RB_CNTL                                                                           0x0238
>+#define mmSDMA1_RLC3_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC3_RB_BASE                                                                           0x0239
>+#define mmSDMA1_RLC3_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC3_RB_BASE_HI                                                                        0x023a
>+#define mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC3_RB_RPTR                                                                           0x023b
>+#define mmSDMA1_RLC3_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC3_RB_RPTR_HI                                                                        0x023c
>+#define mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC3_RB_WPTR                                                                           0x023d
>+#define mmSDMA1_RLC3_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC3_RB_WPTR_HI                                                                        0x023e
>+#define mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL                                                                 0x023f
>+#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI                                                                   0x0240
>+#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO                                                                   0x0241
>+#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA1_RLC3_IB_CNTL                                                                           0x0242
>+#define mmSDMA1_RLC3_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC3_IB_RPTR                                                                           0x0243
>+#define mmSDMA1_RLC3_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC3_IB_OFFSET                                                                         0x0244
>+#define mmSDMA1_RLC3_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA1_RLC3_IB_BASE_LO                                                                        0x0245
>+#define mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA1_RLC3_IB_BASE_HI                                                                        0x0246
>+#define mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC3_IB_SIZE                                                                           0x0247
>+#define mmSDMA1_RLC3_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC3_SKIP_CNTL                                                                         0x0248
>+#define mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA1_RLC3_CONTEXT_STATUS                                                                    0x0249
>+#define mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA1_RLC3_DOORBELL                                                                          0x024a
>+#define mmSDMA1_RLC3_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA1_RLC3_STATUS                                                                            0x0260
>+#define mmSDMA1_RLC3_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA1_RLC3_DOORBELL_LOG                                                                      0x0261
>+#define mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA1_RLC3_WATERMARK                                                                         0x0262
>+#define mmSDMA1_RLC3_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA1_RLC3_DOORBELL_OFFSET                                                                   0x0263
>+#define mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA1_RLC3_CSA_ADDR_LO                                                                       0x0264
>+#define mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA1_RLC3_CSA_ADDR_HI                                                                       0x0265
>+#define mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA1_RLC3_IB_SUB_REMAIN                                                                     0x0267
>+#define mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA1_RLC3_PREEMPT                                                                           0x0268
>+#define mmSDMA1_RLC3_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC3_DUMMY_REG                                                                         0x0269
>+#define mmSDMA1_RLC3_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x026a
>+#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x026b
>+#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA1_RLC3_RB_AQL_CNTL                                                                       0x026c
>+#define mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC3_MINOR_PTR_UPDATE                                                                  0x026d
>+#define mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA1_RLC3_MIDCMD_DATA0                                                                      0x0278
>+#define mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA1_RLC3_MIDCMD_DATA1                                                                      0x0279
>+#define mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA1_RLC3_MIDCMD_DATA2                                                                      0x027a
>+#define mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA1_RLC3_MIDCMD_DATA3                                                                      0x027b
>+#define mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA1_RLC3_MIDCMD_DATA4                                                                      0x027c
>+#define mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA1_RLC3_MIDCMD_DATA5                                                                      0x027d
>+#define mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA1_RLC3_MIDCMD_DATA6                                                                      0x027e
>+#define mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA1_RLC3_MIDCMD_DATA7                                                                      0x027f
>+#define mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA1_RLC3_MIDCMD_DATA8                                                                      0x0280
>+#define mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA1_RLC3_MIDCMD_CNTL                                                                       0x0281
>+#define mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC4_RB_CNTL                                                                           0x0290
>+#define mmSDMA1_RLC4_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC4_RB_BASE                                                                           0x0291
>+#define mmSDMA1_RLC4_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC4_RB_BASE_HI                                                                        0x0292
>+#define mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC4_RB_RPTR                                                                           0x0293
>+#define mmSDMA1_RLC4_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC4_RB_RPTR_HI                                                                        0x0294
>+#define mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC4_RB_WPTR                                                                           0x0295
>+#define mmSDMA1_RLC4_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC4_RB_WPTR_HI                                                                        0x0296
>+#define mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL                                                                 0x0297
>+#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI                                                                   0x0298
>+#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO                                                                   0x0299
>+#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA1_RLC4_IB_CNTL                                                                           0x029a
>+#define mmSDMA1_RLC4_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC4_IB_RPTR                                                                           0x029b
>+#define mmSDMA1_RLC4_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC4_IB_OFFSET                                                                         0x029c
>+#define mmSDMA1_RLC4_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA1_RLC4_IB_BASE_LO                                                                        0x029d
>+#define mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA1_RLC4_IB_BASE_HI                                                                        0x029e
>+#define mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC4_IB_SIZE                                                                           0x029f
>+#define mmSDMA1_RLC4_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC4_SKIP_CNTL                                                                         0x02a0
>+#define mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA1_RLC4_CONTEXT_STATUS                                                                    0x02a1
>+#define mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA1_RLC4_DOORBELL                                                                          0x02a2
>+#define mmSDMA1_RLC4_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA1_RLC4_STATUS                                                                            0x02b8
>+#define mmSDMA1_RLC4_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA1_RLC4_DOORBELL_LOG                                                                      0x02b9
>+#define mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA1_RLC4_WATERMARK                                                                         0x02ba
>+#define mmSDMA1_RLC4_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA1_RLC4_DOORBELL_OFFSET                                                                   0x02bb
>+#define mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA1_RLC4_CSA_ADDR_LO                                                                       0x02bc
>+#define mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA1_RLC4_CSA_ADDR_HI                                                                       0x02bd
>+#define mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA1_RLC4_IB_SUB_REMAIN                                                                     0x02bf
>+#define mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA1_RLC4_PREEMPT                                                                           0x02c0
>+#define mmSDMA1_RLC4_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC4_DUMMY_REG                                                                         0x02c1
>+#define mmSDMA1_RLC4_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x02c2
>+#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x02c3
>+#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA1_RLC4_RB_AQL_CNTL                                                                       0x02c4
>+#define mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC4_MINOR_PTR_UPDATE                                                                  0x02c5
>+#define mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA1_RLC4_MIDCMD_DATA0                                                                      0x02d0
>+#define mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA1_RLC4_MIDCMD_DATA1                                                                      0x02d1
>+#define mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA1_RLC4_MIDCMD_DATA2                                                                      0x02d2
>+#define mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA1_RLC4_MIDCMD_DATA3                                                                      0x02d3
>+#define mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA1_RLC4_MIDCMD_DATA4                                                                      0x02d4
>+#define mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA1_RLC4_MIDCMD_DATA5                                                                      0x02d5
>+#define mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA1_RLC4_MIDCMD_DATA6                                                                      0x02d6
>+#define mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA1_RLC4_MIDCMD_DATA7                                                                      0x02d7
>+#define mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA1_RLC4_MIDCMD_DATA8                                                                      0x02d8
>+#define mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA1_RLC4_MIDCMD_CNTL                                                                       0x02d9
>+#define mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC5_RB_CNTL                                                                           0x02e8
>+#define mmSDMA1_RLC5_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC5_RB_BASE                                                                           0x02e9
>+#define mmSDMA1_RLC5_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC5_RB_BASE_HI                                                                        0x02ea
>+#define mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC5_RB_RPTR                                                                           0x02eb
>+#define mmSDMA1_RLC5_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC5_RB_RPTR_HI                                                                        0x02ec
>+#define mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC5_RB_WPTR                                                                           0x02ed
>+#define mmSDMA1_RLC5_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC5_RB_WPTR_HI                                                                        0x02ee
>+#define mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL                                                                 0x02ef
>+#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI                                                                   0x02f0
>+#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO                                                                   0x02f1
>+#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA1_RLC5_IB_CNTL                                                                           0x02f2
>+#define mmSDMA1_RLC5_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC5_IB_RPTR                                                                           0x02f3
>+#define mmSDMA1_RLC5_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC5_IB_OFFSET                                                                         0x02f4
>+#define mmSDMA1_RLC5_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA1_RLC5_IB_BASE_LO                                                                        0x02f5
>+#define mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA1_RLC5_IB_BASE_HI                                                                        0x02f6
>+#define mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC5_IB_SIZE                                                                           0x02f7
>+#define mmSDMA1_RLC5_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC5_SKIP_CNTL                                                                         0x02f8
>+#define mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA1_RLC5_CONTEXT_STATUS                                                                    0x02f9
>+#define mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA1_RLC5_DOORBELL                                                                          0x02fa
>+#define mmSDMA1_RLC5_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA1_RLC5_STATUS                                                                            0x0310
>+#define mmSDMA1_RLC5_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA1_RLC5_DOORBELL_LOG                                                                      0x0311
>+#define mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA1_RLC5_WATERMARK                                                                         0x0312
>+#define mmSDMA1_RLC5_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA1_RLC5_DOORBELL_OFFSET                                                                   0x0313
>+#define mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA1_RLC5_CSA_ADDR_LO                                                                       0x0314
>+#define mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA1_RLC5_CSA_ADDR_HI                                                                       0x0315
>+#define mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA1_RLC5_IB_SUB_REMAIN                                                                     0x0317
>+#define mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA1_RLC5_PREEMPT                                                                           0x0318
>+#define mmSDMA1_RLC5_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC5_DUMMY_REG                                                                         0x0319
>+#define mmSDMA1_RLC5_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x031a
>+#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x031b
>+#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA1_RLC5_RB_AQL_CNTL                                                                       0x031c
>+#define mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC5_MINOR_PTR_UPDATE                                                                  0x031d
>+#define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA1_RLC5_MIDCMD_DATA0                                                                      0x0328
>+#define mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA1_RLC5_MIDCMD_DATA1                                                                      0x0329
>+#define mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA1_RLC5_MIDCMD_DATA2                                                                      0x032a
>+#define mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA1_RLC5_MIDCMD_DATA3                                                                      0x032b
>+#define mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA1_RLC5_MIDCMD_DATA4                                                                      0x032c
>+#define mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA1_RLC5_MIDCMD_DATA5                                                                      0x032d
>+#define mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA1_RLC5_MIDCMD_DATA6                                                                      0x032e
>+#define mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA1_RLC5_MIDCMD_DATA7                                                                      0x032f
>+#define mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA1_RLC5_MIDCMD_DATA8                                                                      0x0330
>+#define mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA1_RLC5_MIDCMD_CNTL                                                                       0x0331
>+#define mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC6_RB_CNTL                                                                           0x0340
>+#define mmSDMA1_RLC6_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC6_RB_BASE                                                                           0x0341
>+#define mmSDMA1_RLC6_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC6_RB_BASE_HI                                                                        0x0342
>+#define mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC6_RB_RPTR                                                                           0x0343
>+#define mmSDMA1_RLC6_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC6_RB_RPTR_HI                                                                        0x0344
>+#define mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC6_RB_WPTR                                                                           0x0345
>+#define mmSDMA1_RLC6_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC6_RB_WPTR_HI                                                                        0x0346
>+#define mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0347
>+#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI                                                                   0x0348
>+#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO                                                                   0x0349
>+#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA1_RLC6_IB_CNTL                                                                           0x034a
>+#define mmSDMA1_RLC6_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC6_IB_RPTR                                                                           0x034b
>+#define mmSDMA1_RLC6_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC6_IB_OFFSET                                                                         0x034c
>+#define mmSDMA1_RLC6_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA1_RLC6_IB_BASE_LO                                                                        0x034d
>+#define mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA1_RLC6_IB_BASE_HI                                                                        0x034e
>+#define mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC6_IB_SIZE                                                                           0x034f
>+#define mmSDMA1_RLC6_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC6_SKIP_CNTL                                                                         0x0350
>+#define mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA1_RLC6_CONTEXT_STATUS                                                                    0x0351
>+#define mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA1_RLC6_DOORBELL                                                                          0x0352
>+#define mmSDMA1_RLC6_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA1_RLC6_STATUS                                                                            0x0368
>+#define mmSDMA1_RLC6_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA1_RLC6_DOORBELL_LOG                                                                      0x0369
>+#define mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA1_RLC6_WATERMARK                                                                         0x036a
>+#define mmSDMA1_RLC6_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA1_RLC6_DOORBELL_OFFSET                                                                   0x036b
>+#define mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA1_RLC6_CSA_ADDR_LO                                                                       0x036c
>+#define mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA1_RLC6_CSA_ADDR_HI                                                                       0x036d
>+#define mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA1_RLC6_IB_SUB_REMAIN                                                                     0x036f
>+#define mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA1_RLC6_PREEMPT                                                                           0x0370
>+#define mmSDMA1_RLC6_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC6_DUMMY_REG                                                                         0x0371
>+#define mmSDMA1_RLC6_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x0372
>+#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x0373
>+#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA1_RLC6_RB_AQL_CNTL                                                                       0x0374
>+#define mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC6_MINOR_PTR_UPDATE                                                                  0x0375
>+#define mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA1_RLC6_MIDCMD_DATA0                                                                      0x0380
>+#define mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA1_RLC6_MIDCMD_DATA1                                                                      0x0381
>+#define mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA1_RLC6_MIDCMD_DATA2                                                                      0x0382
>+#define mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA1_RLC6_MIDCMD_DATA3                                                                      0x0383
>+#define mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA1_RLC6_MIDCMD_DATA4                                                                      0x0384
>+#define mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA1_RLC6_MIDCMD_DATA5                                                                      0x0385
>+#define mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA1_RLC6_MIDCMD_DATA6                                                                      0x0386
>+#define mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA1_RLC6_MIDCMD_DATA7                                                                      0x0387
>+#define mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA1_RLC6_MIDCMD_DATA8                                                                      0x0388
>+#define mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA1_RLC6_MIDCMD_CNTL                                                                       0x0389
>+#define mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC7_RB_CNTL                                                                           0x0398
>+#define mmSDMA1_RLC7_RB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC7_RB_BASE                                                                           0x0399
>+#define mmSDMA1_RLC7_RB_BASE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC7_RB_BASE_HI                                                                        0x039a
>+#define mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC7_RB_RPTR                                                                           0x039b
>+#define mmSDMA1_RLC7_RB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC7_RB_RPTR_HI                                                                        0x039c
>+#define mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC7_RB_WPTR                                                                           0x039d
>+#define mmSDMA1_RLC7_RB_WPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC7_RB_WPTR_HI                                                                        0x039e
>+#define mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL                                                                 0x039f
>+#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
>+#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI                                                                   0x03a0
>+#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
>+#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO                                                                   0x03a1
>+#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
>+#define mmSDMA1_RLC7_IB_CNTL                                                                           0x03a2
>+#define mmSDMA1_RLC7_IB_CNTL_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC7_IB_RPTR                                                                           0x03a3
>+#define mmSDMA1_RLC7_IB_RPTR_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC7_IB_OFFSET                                                                         0x03a4
>+#define mmSDMA1_RLC7_IB_OFFSET_BASE_IDX                                                                0
>+#define mmSDMA1_RLC7_IB_BASE_LO                                                                        0x03a5
>+#define mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX                                                               0
>+#define mmSDMA1_RLC7_IB_BASE_HI                                                                        0x03a6
>+#define mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX                                                               0
>+#define mmSDMA1_RLC7_IB_SIZE                                                                           0x03a7
>+#define mmSDMA1_RLC7_IB_SIZE_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC7_SKIP_CNTL                                                                         0x03a8
>+#define mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX                                                                0
>+#define mmSDMA1_RLC7_CONTEXT_STATUS                                                                    0x03a9
>+#define mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX                                                           0
>+#define mmSDMA1_RLC7_DOORBELL                                                                          0x03aa
>+#define mmSDMA1_RLC7_DOORBELL_BASE_IDX                                                                 0
>+#define mmSDMA1_RLC7_STATUS                                                                            0x03c0
>+#define mmSDMA1_RLC7_STATUS_BASE_IDX                                                                   0
>+#define mmSDMA1_RLC7_DOORBELL_LOG                                                                      0x03c1
>+#define mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX                                                             0
>+#define mmSDMA1_RLC7_WATERMARK                                                                         0x03c2
>+#define mmSDMA1_RLC7_WATERMARK_BASE_IDX                                                                0
>+#define mmSDMA1_RLC7_DOORBELL_OFFSET                                                                   0x03c3
>+#define mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          0
>+#define mmSDMA1_RLC7_CSA_ADDR_LO                                                                       0x03c4
>+#define mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX                                                              0
>+#define mmSDMA1_RLC7_CSA_ADDR_HI                                                                       0x03c5
>+#define mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX                                                              0
>+#define mmSDMA1_RLC7_IB_SUB_REMAIN                                                                     0x03c7
>+#define mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            0
>+#define mmSDMA1_RLC7_PREEMPT                                                                           0x03c8
>+#define mmSDMA1_RLC7_PREEMPT_BASE_IDX                                                                  0
>+#define mmSDMA1_RLC7_DUMMY_REG                                                                         0x03c9
>+#define mmSDMA1_RLC7_DUMMY_REG_BASE_IDX                                                                0
>+#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x03ca
>+#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
>+#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x03cb
>+#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
>+#define mmSDMA1_RLC7_RB_AQL_CNTL                                                                       0x03cc
>+#define mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX                                                              0
>+#define mmSDMA1_RLC7_MINOR_PTR_UPDATE                                                                  0x03cd
>+#define mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         0
>+#define mmSDMA1_RLC7_MIDCMD_DATA0                                                                      0x03d8
>+#define mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX                                                             0
>+#define mmSDMA1_RLC7_MIDCMD_DATA1                                                                      0x03d9
>+#define mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX                                                             0
>+#define mmSDMA1_RLC7_MIDCMD_DATA2                                                                      0x03da
>+#define mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX                                                             0
>+#define mmSDMA1_RLC7_MIDCMD_DATA3                                                                      0x03db
>+#define mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX                                                             0
>+#define mmSDMA1_RLC7_MIDCMD_DATA4                                                                      0x03dc
>+#define mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX                                                             0
>+#define mmSDMA1_RLC7_MIDCMD_DATA5                                                                      0x03dd
>+#define mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX                                                             0
>+#define mmSDMA1_RLC7_MIDCMD_DATA6                                                                      0x03de
>+#define mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX                                                             0
>+#define mmSDMA1_RLC7_MIDCMD_DATA7                                                                      0x03df
>+#define mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX                                                             0
>+#define mmSDMA1_RLC7_MIDCMD_DATA8                                                                      0x03e0
>+#define mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX                                                             0
>+#define mmSDMA1_RLC7_MIDCMD_CNTL                                                                       0x03e1
>+#define mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX                                                              0
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_2_sh_mask.h	2019-08-31 15:01:11.931736175 -0500
>@@ -0,0 +1,2956 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma1_4_2_2_SH_MASK_HEADER
>+#define _sdma1_4_2_2_SH_MASK_HEADER
>+
>+
>+// addressBlock: sdma1_sdma1dec
>+//SDMA1_UCODE_ADDR
>+#define SDMA1_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
>+#define SDMA1_UCODE_ADDR__VALUE_MASK                                                                          0x00001FFFL
>+//SDMA1_UCODE_DATA
>+#define SDMA1_UCODE_DATA__VALUE__SHIFT                                                                        0x0
>+#define SDMA1_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
>+//SDMA1_VM_CNTL
>+#define SDMA1_VM_CNTL__CMD__SHIFT                                                                             0x0
>+#define SDMA1_VM_CNTL__CMD_MASK                                                                               0x0000000FL
>+//SDMA1_VM_CTX_LO
>+#define SDMA1_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
>+#define SDMA1_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
>+//SDMA1_VM_CTX_HI
>+#define SDMA1_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
>+#define SDMA1_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
>+//SDMA1_ACTIVE_FCN_ID
>+#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
>+#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x4
>+#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
>+#define SDMA1_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000000FL
>+#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFF0L
>+#define SDMA1_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
>+//SDMA1_VM_CTX_CNTL
>+#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
>+#define SDMA1_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
>+#define SDMA1_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
>+#define SDMA1_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
>+//SDMA1_VIRT_RESET_REQ
>+#define SDMA1_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
>+#define SDMA1_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
>+#define SDMA1_VIRT_RESET_REQ__VF_MASK                                                                         0x0000FFFFL
>+#define SDMA1_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
>+//SDMA1_VF_ENABLE
>+#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
>+#define SDMA1_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
>+//SDMA1_CONTEXT_REG_TYPE0
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT                                                     0x0
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT                                                     0x1
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT                                                  0x2
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT                                                     0x3
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT                                                  0x4
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT                                                     0x5
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT                                                  0x6
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT                                                     0xa
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT                                                     0xb
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT                                                   0xc
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT                                                  0xd
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT                                                  0xe
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT                                                     0xf
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT                                                   0x10
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT                                              0x11
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT                                                    0x12
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT                                                0x13
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK                                                       0x00000001L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK                                                       0x00000002L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK                                                    0x00000004L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK                                                       0x00000008L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK                                                       0x00000020L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK                                                       0x00000400L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK                                                       0x00000800L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK                                                     0x00001000L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK                                                    0x00002000L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK                                                    0x00004000L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK                                                       0x00008000L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK                                                     0x00010000L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK                                                      0x00040000L
>+#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
>+//SDMA1_CONTEXT_REG_TYPE1
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT                                                      0x8
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT                                                0x9
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT                                                   0xa
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
>+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT                                                     0x10
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT                                                   0x11
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
>+#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x16
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK                                                        0x00000100L
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK                                                     0x00000400L
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
>+#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK                                                       0x00010000L
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK                                                     0x00020000L
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
>+#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
>+#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFFC00000L
>+//SDMA1_CONTEXT_REG_TYPE2
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT                                                0x0
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT                                                0x1
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT                                                0x2
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT                                                0x3
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT                                                0x4
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT                                                0x5
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT                                                0x6
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT                                                0x7
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT                                                0x8
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT                                                 0x9
>+#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
>+#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK                                                   0x00000200L
>+#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFFC00L
>+//SDMA1_CONTEXT_REG_TYPE3
>+#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
>+#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
>+//SDMA1_PUB_REG_TYPE0
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT                                                          0x0
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT                                                          0x1
>+#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT                                                                 0x3
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT                                                             0x4
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT                                                           0x5
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT                                                           0x6
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT                                                       0x7
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT                                                         0x8
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT                                                      0x9
>+#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT                                                                0xa
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT                                                   0xb
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT                                                   0xc
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT                                                   0xd
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT                                                   0xe
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT                                                       0xf
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT                                                       0x10
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT                                                       0x11
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT                                                       0x12
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT                                                          0x13
>+#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x15
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT                                              0x19
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT                                                          0x1a
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT                                                            0x1b
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT                                                                0x1c
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT                                                        0x1d
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT                                                      0x1e
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK                                                            0x00000001L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK                                                            0x00000002L
>+#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK                                                                   0x00000008L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK                                                               0x00000010L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK                                                             0x00000020L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK                                                             0x00000040L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK                                                         0x00000080L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK                                                           0x00000100L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK                                                        0x00000200L
>+#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK                                                                  0x00000400L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK                                                     0x00000800L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK                                                     0x00001000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK                                                     0x00002000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK                                                     0x00004000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK                                                         0x00008000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK                                                         0x00010000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK                                                         0x00020000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK                                                         0x00040000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK                                                            0x00080000L
>+#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x01E00000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK                                                0x02000000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK                                                            0x04000000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK                                                              0x08000000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK                                                                  0x10000000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK                                                          0x20000000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK                                                        0x40000000L
>+#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
>+//SDMA1_PUB_REG_TYPE1
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT                                                       0x2
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT                                                     0x3
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT                                                             0x4
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT                                                          0x5
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT                                                         0x6
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT                                                       0x7
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT                                                     0x8
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT                                                      0x9
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT                                                            0xa
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT                                                              0xb
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT                                                      0xc
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT                                                      0xd
>+#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT                                                         0xe
>+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT                                                         0xf
>+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT                                                          0x10
>+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT                                                           0x11
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT                                                          0x12
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT                                                        0x13
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT                                                                  0x14
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT                                                             0x15
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT                                                         0x16
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT                                                         0x18
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT                                                         0x19
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT                                                          0x1c
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT                                                       0x1d
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT                                                     0x1e
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT                                                     0x1f
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK                                                         0x00000004L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK                                                       0x00000008L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK                                                               0x00000010L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK                                                            0x00000020L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK                                                           0x00000040L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK                                                         0x00000080L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK                                                        0x00000200L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK                                                              0x00000400L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK                                                                0x00000800L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK                                                        0x00001000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK                                                        0x00002000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK                                                           0x00004000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK                                                           0x00008000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK                                                            0x00010000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK                                                             0x00020000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK                                                            0x00040000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK                                                          0x00080000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK                                                                    0x00100000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK                                                               0x00200000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK                                                           0x00400000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK                                                           0x01000000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK                                                           0x02000000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK                                                            0x10000000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK                                                         0x20000000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK                                                       0x40000000L
>+#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK                                                       0x80000000L
>+//SDMA1_PUB_REG_TYPE2
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT                                                          0x0
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT                                                          0x1
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT                                                          0x2
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT                                                     0x3
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT                                                     0x4
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT                                                     0x5
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT                                                     0x6
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT                                                       0x7
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT                                                          0x8
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT                                                     0x9
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT                                                  0xa
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT                                                      0xb
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT                                                         0xc
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT                                                      0xf
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT                                                           0x10
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT                                                      0x11
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT                                                      0x12
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT                                                      0x13
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT                                                      0x14
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT                                                         0x15
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT                                                         0x16
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT                                                        0x17
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT                                                 0x18
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT                                                 0x19
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT                                         0x1a
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT                                                            0x1b
>+#define SDMA1_PUB_REG_TYPE2__RESERVED28__SHIFT                                                                0x1c
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT                                               0x1d
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT                                                            0x1e
>+#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT                                                                  0x1f
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK                                                            0x00000001L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK                                                            0x00000002L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK                                                            0x00000004L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK                                                         0x00000080L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK                                                            0x00000100L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK                                                       0x00000200L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK                                                        0x00000800L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK                                                           0x00001000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK                                                        0x00008000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK                                                             0x00010000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK                                                        0x00020000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK                                                        0x00040000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK                                                        0x00080000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK                                                        0x00100000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK                                                           0x00200000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK                                                           0x00400000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK                                                          0x00800000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK                                                   0x01000000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK                                                   0x02000000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK                                           0x04000000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK                                                              0x08000000L
>+#define SDMA1_PUB_REG_TYPE2__RESERVED28_MASK                                                                  0x10000000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK                                                 0x20000000L
>+#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK                                                              0x40000000L
>+#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK                                                                    0x80000000L
>+//SDMA1_PUB_REG_TYPE3
>+#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
>+#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
>+#define SDMA1_PUB_REG_TYPE3__SDMA1_GPU_IOV_VIOLATION_LOG2__SHIFT                                              0x2
>+#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x3
>+#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
>+#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
>+#define SDMA1_PUB_REG_TYPE3__SDMA1_GPU_IOV_VIOLATION_LOG2_MASK                                                0x00000004L
>+#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xFFFFFFF8L
>+//SDMA1_MMHUB_CNTL
>+#define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT                                                                      0x0
>+#define SDMA1_MMHUB_CNTL__UNIT_ID_MASK                                                                        0x0000003FL
>+//SDMA1_CONTEXT_GROUP_BOUNDARY
>+#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT                                                         0x0
>+#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK                                                           0xFFFFFFFFL
>+//SDMA1_POWER_CNTL
>+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
>+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT                                                              0x9
>+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT                                                              0xa
>+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT                                                              0xb
>+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT                                                              0xc
>+#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
>+#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK                                                                0x00000200L
>+#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK                                                                0x00000400L
>+#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK                                                                0x00000800L
>+#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK                                                                0x003FF000L
>+//SDMA1_CLK_CTRL
>+#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
>+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
>+#define SDMA1_CLK_CTRL__RESERVED__SHIFT                                                                       0xc
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                                 0x18
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                                 0x19
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                                 0x1a
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1b
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1c
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1d
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1e
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1f
>+#define SDMA1_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
>+#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
>+#define SDMA1_CLK_CTRL__RESERVED_MASK                                                                         0x00FFF000L
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                   0x01000000L
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                   0x02000000L
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                   0x04000000L
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x08000000L
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x10000000L
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x20000000L
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x40000000L
>+#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x80000000L
>+//SDMA1_CNTL
>+#define SDMA1_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
>+#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
>+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
>+#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
>+#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
>+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
>+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
>+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
>+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
>+#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
>+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
>+#define SDMA1_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
>+#define SDMA1_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
>+#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
>+#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
>+#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
>+#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
>+#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
>+#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
>+#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
>+#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
>+#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
>+//SDMA1_CHICKEN_BITS
>+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
>+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
>+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
>+#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
>+#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
>+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
>+#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
>+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
>+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
>+#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
>+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
>+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
>+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
>+#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
>+#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
>+#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
>+#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
>+#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
>+#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
>+#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
>+#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
>+#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
>+#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
>+#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
>+#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
>+#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
>+//SDMA1_GB_ADDR_CONFIG
>+#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
>+#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
>+#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
>+#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
>+#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
>+#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
>+#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
>+#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
>+#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
>+#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
>+//SDMA1_GB_ADDR_CONFIG_READ
>+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
>+#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
>+#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                0x8
>+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                           0xc
>+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
>+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
>+#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
>+#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                  0x00000700L
>+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                             0x00007000L
>+#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
>+//SDMA1_RB_RPTR_FETCH_HI
>+#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
>+#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL
>+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
>+#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
>+//SDMA1_RB_RPTR_FETCH
>+#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
>+#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
>+//SDMA1_IB_OFFSET_FETCH
>+#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
>+#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
>+//SDMA1_PROGRAM
>+#define SDMA1_PROGRAM__STREAM__SHIFT                                                                          0x0
>+#define SDMA1_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
>+//SDMA1_STATUS_REG
>+#define SDMA1_STATUS_REG__IDLE__SHIFT                                                                         0x0
>+#define SDMA1_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
>+#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
>+#define SDMA1_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
>+#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
>+#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
>+#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
>+#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
>+#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
>+#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
>+#define SDMA1_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
>+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
>+#define SDMA1_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
>+#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
>+#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
>+#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
>+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
>+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
>+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
>+#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
>+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
>+#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
>+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
>+#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
>+#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
>+#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
>+#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
>+#define SDMA1_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
>+#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
>+#define SDMA1_STATUS_REG__IDLE_MASK                                                                           0x00000001L
>+#define SDMA1_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
>+#define SDMA1_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
>+#define SDMA1_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
>+#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
>+#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
>+#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
>+#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
>+#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
>+#define SDMA1_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
>+#define SDMA1_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
>+#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
>+#define SDMA1_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
>+#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
>+#define SDMA1_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
>+#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
>+#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
>+#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
>+#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
>+#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
>+#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
>+#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
>+#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
>+#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
>+#define SDMA1_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
>+#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
>+#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
>+#define SDMA1_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
>+#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
>+//SDMA1_STATUS1_REG
>+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
>+#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
>+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
>+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
>+#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
>+#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
>+#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
>+#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
>+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
>+#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
>+#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
>+#define SDMA1_STATUS1_REG__EX_START__SHIFT                                                                    0xf
>+#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
>+#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
>+#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
>+#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
>+#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
>+#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
>+#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
>+#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
>+#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
>+#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
>+#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
>+#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
>+#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
>+#define SDMA1_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
>+#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
>+#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
>+//SDMA1_RD_BURST_CNTL
>+#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
>+#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT                                                       0x2
>+#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
>+#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK                                                         0x0000000CL
>+//SDMA1_HBM_PAGE_CONFIG
>+#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
>+#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000001L
>+//SDMA1_UCODE_CHECKSUM
>+#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
>+#define SDMA1_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_F32_CNTL
>+#define SDMA1_F32_CNTL__HALT__SHIFT                                                                           0x0
>+#define SDMA1_F32_CNTL__STEP__SHIFT                                                                           0x1
>+#define SDMA1_F32_CNTL__HALT_MASK                                                                             0x00000001L
>+#define SDMA1_F32_CNTL__STEP_MASK                                                                             0x00000002L
>+//SDMA1_FREEZE
>+#define SDMA1_FREEZE__PREEMPT__SHIFT                                                                          0x0
>+#define SDMA1_FREEZE__FREEZE__SHIFT                                                                           0x4
>+#define SDMA1_FREEZE__FROZEN__SHIFT                                                                           0x5
>+#define SDMA1_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
>+#define SDMA1_FREEZE__PREEMPT_MASK                                                                            0x00000001L
>+#define SDMA1_FREEZE__FREEZE_MASK                                                                             0x00000010L
>+#define SDMA1_FREEZE__FROZEN_MASK                                                                             0x00000020L
>+#define SDMA1_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
>+//SDMA1_PHASE0_QUANTUM
>+#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA1_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA1_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA1_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA1_PHASE1_QUANTUM
>+#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA1_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA1_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA1_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA1_EDC_CONFIG
>+#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
>+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
>+#define SDMA1_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
>+#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
>+//SDMA1_BA_THRESHOLD
>+#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
>+#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
>+#define SDMA1_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
>+#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
>+//SDMA1_ID
>+#define SDMA1_ID__DEVICE_ID__SHIFT                                                                            0x0
>+#define SDMA1_ID__DEVICE_ID_MASK                                                                              0x000000FFL
>+//SDMA1_VERSION
>+#define SDMA1_VERSION__MINVER__SHIFT                                                                          0x0
>+#define SDMA1_VERSION__MAJVER__SHIFT                                                                          0x8
>+#define SDMA1_VERSION__REV__SHIFT                                                                             0x10
>+#define SDMA1_VERSION__MINVER_MASK                                                                            0x0000007FL
>+#define SDMA1_VERSION__MAJVER_MASK                                                                            0x00007F00L
>+#define SDMA1_VERSION__REV_MASK                                                                               0x003F0000L
>+//SDMA1_EDC_COUNTER
>+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT                                                          0x0
>+#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
>+#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
>+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
>+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
>+#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT                                                    0xf
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT                                                    0x10
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT                                                   0x11
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT                                                   0x12
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT                                                   0x13
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT                                                   0x14
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT                                                   0x15
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT                                                   0x16
>+#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0x17
>+#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x18
>+#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK                                                            0x00000001L
>+#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
>+#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
>+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
>+#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
>+#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK                                                      0x00008000L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK                                                      0x00010000L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK                                                     0x00020000L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK                                                     0x00040000L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK                                                     0x00080000L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK                                                     0x00100000L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK                                                     0x00200000L
>+#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK                                                     0x00400000L
>+#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00800000L
>+#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x01000000L
>+//SDMA1_EDC_COUNTER_CLEAR
>+#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
>+#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
>+//SDMA1_STATUS2_REG
>+#define SDMA1_STATUS2_REG__ID__SHIFT                                                                          0x0
>+#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x3
>+#define SDMA1_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
>+#define SDMA1_STATUS2_REG__ID_MASK                                                                            0x00000007L
>+#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFF8L
>+#define SDMA1_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
>+//SDMA1_ATOMIC_CNTL
>+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
>+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
>+#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
>+#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
>+//SDMA1_ATOMIC_PREOP_LO
>+#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
>+#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_ATOMIC_PREOP_HI
>+#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
>+#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_UTCL1_CNTL
>+#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
>+#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0xb
>+#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0xe
>+#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
>+#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
>+#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x000007FEL
>+#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x00003800L
>+#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FFC000L
>+#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
>+#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
>+//SDMA1_UTCL1_WATERMK
>+#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
>+#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0x9
>+#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x11
>+#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x19
>+#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000001FFL
>+#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0001FE00L
>+#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x01FE0000L
>+#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFE000000L
>+//SDMA1_UTCL1_RD_STATUS
>+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT                                                             0x15
>+#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x16
>+#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x1a
>+#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x1d
>+#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT                                                            0x1e
>+#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT                                                             0x1f
>+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK                                                               0x00200000L
>+#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x03C00000L
>+#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x1C000000L
>+#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x20000000L
>+#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK                                                              0x40000000L
>+#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK                                                               0x80000000L
>+//SDMA1_UTCL1_WR_STATUS
>+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15
>+#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x16
>+#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19
>+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
>+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
>+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
>+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
>+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x00200000L
>+#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x01C00000L
>+#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x0E000000L
>+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
>+#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
>+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
>+#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
>+//SDMA1_UTCL1_INV0
>+#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT                                                                   0x0
>+#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT                                                                   0x1
>+#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT                                                                   0x2
>+#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT                                                                 0x3
>+#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT                                                                 0x4
>+#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT                                                                 0x5
>+#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT                                                              0x6
>+#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT                                                                0x7
>+#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT                                                              0x8
>+#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT                                                              0x9
>+#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT                                                               0xa
>+#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT                                                                0xb
>+#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT                                                                 0xc
>+#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT                                                                  0x1c
>+#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK                                                                     0x00000001L
>+#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK                                                                     0x00000002L
>+#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK                                                                     0x00000004L
>+#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK                                                                   0x00000008L
>+#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK                                                                   0x00000010L
>+#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK                                                                   0x00000020L
>+#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK                                                                0x00000040L
>+#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK                                                                  0x00000080L
>+#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK                                                                0x00000100L
>+#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK                                                                0x00000200L
>+#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK                                                                 0x00000400L
>+#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK                                                                  0x00000800L
>+#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK                                                                   0x0FFFF000L
>+#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK                                                                    0xF0000000L
>+//SDMA1_UTCL1_INV1
>+#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
>+#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_UTCL1_INV2
>+#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT                                                          0x0
>+#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK                                                            0xFFFFFFFFL
>+//SDMA1_UTCL1_RD_XNACK0
>+#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA1_UTCL1_RD_XNACK1
>+#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA1_UTCL1_WR_XNACK0
>+#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA1_UTCL1_WR_XNACK1
>+#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA1_UTCL1_TIMEOUT
>+#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
>+#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
>+#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
>+#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
>+//SDMA1_UTCL1_PAGE
>+#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
>+#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
>+#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
>+#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0x9
>+#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
>+#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
>+#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000001C0L
>+#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000200L
>+//SDMA1_POWER_CNTL_IDLE
>+#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT                                                                  0x0
>+#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT                                                                  0x10
>+#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT                                                                  0x18
>+#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK                                                                    0x0000FFFFL
>+#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK                                                                    0x00FF0000L
>+#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK                                                                    0xFF000000L
>+//SDMA1_RELAX_ORDERING_LUT
>+#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
>+#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
>+#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
>+#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
>+#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
>+#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
>+#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
>+#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
>+#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
>+#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
>+#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
>+#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
>+#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
>+#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
>+#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
>+#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
>+#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
>+#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
>+#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
>+#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
>+#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
>+#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
>+#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
>+#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
>+#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
>+#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
>+#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
>+#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
>+#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
>+#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
>+#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
>+#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
>+#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
>+#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
>+#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
>+#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
>+#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
>+#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
>+//SDMA1_CHICKEN_BITS_2
>+#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
>+#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
>+//SDMA1_STATUS3_REG
>+#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
>+#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
>+#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
>+#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x15
>+#define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x16
>+#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
>+#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
>+#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
>+#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x00200000L
>+#define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x03C00000L
>+//SDMA1_PHYSICAL_ADDR_LO
>+#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
>+#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
>+#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
>+#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
>+#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
>+#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
>+#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
>+#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
>+//SDMA1_PHYSICAL_ADDR_HI
>+#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
>+//SDMA1_PHASE2_QUANTUM
>+#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA1_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA1_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA1_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA1_ERROR_LOG
>+#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
>+#define SDMA1_ERROR_LOG__STATUS__SHIFT                                                                        0x10
>+#define SDMA1_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
>+#define SDMA1_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
>+//SDMA1_PUB_DUMMY_REG0
>+#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
>+#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_PUB_DUMMY_REG1
>+#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
>+#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_PUB_DUMMY_REG2
>+#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
>+#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_PUB_DUMMY_REG3
>+#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
>+#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_F32_COUNTER
>+#define SDMA1_F32_COUNTER__VALUE__SHIFT                                                                       0x0
>+#define SDMA1_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
>+//SDMA1_UNBREAKABLE
>+#define SDMA1_UNBREAKABLE__VALUE__SHIFT                                                                       0x0
>+#define SDMA1_UNBREAKABLE__VALUE_MASK                                                                         0x00000001L
>+//SDMA1_PERFMON_CNTL
>+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT                                                               0x0
>+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT                                                                0x1
>+#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT                                                                  0x2
>+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT                                                               0xa
>+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT                                                                0xb
>+#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT                                                                  0xc
>+#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK                                                                 0x00000001L
>+#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK                                                                  0x00000002L
>+#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK                                                                    0x000003FCL
>+#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK                                                                 0x00000400L
>+#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK                                                                  0x00000800L
>+#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK                                                                    0x000FF000L
>+//SDMA1_PERFCOUNTER0_RESULT
>+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA1_PERFCOUNTER1_RESULT
>+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE
>+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT                                                   0x0
>+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT                                                  0xe
>+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT                                                   0x1c
>+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK                                                     0x00003FFFL
>+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK                                                    0x0FFFC000L
>+#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK                                                     0x10000000L
>+//SDMA1_CRD_CNTL
>+#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
>+#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
>+#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
>+#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
>+//SDMA1_GPU_IOV_VIOLATION_LOG
>+#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT                                                  0x0
>+#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT                                         0x1
>+#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT                                                           0x2
>+#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT                                                   0x14
>+#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT                                                                0x15
>+#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT                                                              0x16
>+#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK                                                    0x00000001L
>+#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK                                           0x00000002L
>+#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK                                                             0x000FFFFCL
>+#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK                                                     0x00100000L
>+#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK                                                                  0x00200000L
>+#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK                                                                0x03C00000L
>+//SDMA1_ULV_CNTL
>+#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT                                                                     0x0
>+#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT                                                              0x1b
>+#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT                                                               0x1c
>+#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT                                                                  0x1d
>+#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT                                                                   0x1e
>+#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT                                                                     0x1f
>+#define SDMA1_ULV_CNTL__HYSTERESIS_MASK                                                                       0x0000001FL
>+#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR_MASK                                                                0x08000000L
>+#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR_MASK                                                                 0x10000000L
>+#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK                                                                    0x20000000L
>+#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK                                                                     0x40000000L
>+#define SDMA1_ULV_CNTL__ULV_STATUS_MASK                                                                       0x80000000L
>+//SDMA1_EA_DBIT_ADDR_DATA
>+#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
>+#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_EA_DBIT_ADDR_INDEX
>+#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
>+#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
>+//SDMA1_GPU_IOV_VIOLATION_LOG2
>+#define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                     0x0
>+#define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                       0x000000FFL
>+//SDMA1_GFX_RB_CNTL
>+#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
>+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
>+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
>+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
>+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
>+#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
>+#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
>+#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
>+#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
>+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
>+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
>+#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
>+#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
>+#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
>+//SDMA1_GFX_RB_BASE
>+#define SDMA1_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
>+#define SDMA1_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
>+//SDMA1_GFX_RB_BASE_HI
>+#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
>+//SDMA1_GFX_RB_RPTR
>+#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA1_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA1_GFX_RB_RPTR_HI
>+#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA1_GFX_RB_WPTR
>+#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA1_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA1_GFX_RB_WPTR_HI
>+#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA1_GFX_RB_WPTR_POLL_CNTL
>+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
>+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
>+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
>+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
>+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
>+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
>+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
>+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
>+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
>+#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
>+//SDMA1_GFX_RB_RPTR_ADDR_HI
>+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
>+#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
>+//SDMA1_GFX_RB_RPTR_ADDR_LO
>+#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                        0x0
>+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
>+#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                          0x00000001L
>+#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
>+//SDMA1_GFX_IB_CNTL
>+#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
>+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
>+#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
>+#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
>+#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
>+#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
>+//SDMA1_GFX_IB_RPTR
>+#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
>+#define SDMA1_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
>+//SDMA1_GFX_IB_OFFSET
>+#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
>+#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
>+//SDMA1_GFX_IB_BASE_LO
>+#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
>+#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
>+//SDMA1_GFX_IB_BASE_HI
>+#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_GFX_IB_SIZE
>+#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
>+#define SDMA1_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
>+//SDMA1_GFX_SKIP_CNTL
>+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
>+#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
>+//SDMA1_GFX_CONTEXT_STATUS
>+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
>+#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
>+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
>+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
>+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
>+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
>+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
>+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
>+#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
>+#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
>+#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
>+#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
>+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
>+#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
>+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
>+#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
>+//SDMA1_GFX_DOORBELL
>+#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
>+#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
>+#define SDMA1_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
>+#define SDMA1_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
>+//SDMA1_GFX_CONTEXT_CNTL
>+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
>+#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
>+//SDMA1_GFX_STATUS
>+#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
>+#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
>+#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
>+#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
>+//SDMA1_GFX_DOORBELL_LOG
>+#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
>+#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
>+#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
>+#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
>+//SDMA1_GFX_WATERMARK
>+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
>+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
>+#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
>+#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
>+//SDMA1_GFX_DOORBELL_OFFSET
>+#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
>+#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
>+//SDMA1_GFX_CSA_ADDR_LO
>+#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
>+#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
>+//SDMA1_GFX_CSA_ADDR_HI
>+#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_GFX_IB_SUB_REMAIN
>+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
>+#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x000FFFFFL
>+//SDMA1_GFX_PREEMPT
>+#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
>+#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
>+//SDMA1_GFX_DUMMY_REG
>+#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
>+#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI
>+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
>+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
>+//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO
>+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
>+#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
>+//SDMA1_GFX_RB_AQL_CNTL
>+#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
>+#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
>+#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
>+#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
>+#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
>+#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
>+//SDMA1_GFX_MINOR_PTR_UPDATE
>+#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
>+#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
>+//SDMA1_GFX_MIDCMD_DATA0
>+#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
>+#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_GFX_MIDCMD_DATA1
>+#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
>+#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_GFX_MIDCMD_DATA2
>+#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
>+#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_GFX_MIDCMD_DATA3
>+#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
>+#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_GFX_MIDCMD_DATA4
>+#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
>+#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_GFX_MIDCMD_DATA5
>+#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
>+#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_GFX_MIDCMD_DATA6
>+#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
>+#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_GFX_MIDCMD_DATA7
>+#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
>+#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_GFX_MIDCMD_DATA8
>+#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
>+#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_GFX_MIDCMD_CNTL
>+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
>+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
>+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
>+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
>+#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
>+#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
>+#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
>+#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
>+//SDMA1_PAGE_RB_CNTL
>+#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA1_PAGE_RB_BASE
>+#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA1_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA1_PAGE_RB_BASE_HI
>+#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA1_PAGE_RB_RPTR
>+#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_PAGE_RB_RPTR_HI
>+#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_PAGE_RB_WPTR
>+#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_PAGE_RB_WPTR_HI
>+#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_PAGE_RB_WPTR_POLL_CNTL
>+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA1_PAGE_RB_RPTR_ADDR_HI
>+#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA1_PAGE_RB_RPTR_ADDR_LO
>+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA1_PAGE_IB_CNTL
>+#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA1_PAGE_IB_RPTR
>+#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA1_PAGE_IB_OFFSET
>+#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA1_PAGE_IB_BASE_LO
>+#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA1_PAGE_IB_BASE_HI
>+#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_PAGE_IB_SIZE
>+#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA1_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA1_PAGE_SKIP_CNTL
>+#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA1_PAGE_CONTEXT_STATUS
>+#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA1_PAGE_DOORBELL
>+#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA1_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA1_PAGE_STATUS
>+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA1_PAGE_DOORBELL_LOG
>+#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA1_PAGE_WATERMARK
>+#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA1_PAGE_DOORBELL_OFFSET
>+#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA1_PAGE_CSA_ADDR_LO
>+#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA1_PAGE_CSA_ADDR_HI
>+#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA1_PAGE_IB_SUB_REMAIN
>+#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA1_PAGE_PREEMPT
>+#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA1_PAGE_DUMMY_REG
>+#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI
>+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO
>+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA1_PAGE_RB_AQL_CNTL
>+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA1_PAGE_MINOR_PTR_UPDATE
>+#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA1_PAGE_MIDCMD_DATA0
>+#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_PAGE_MIDCMD_DATA1
>+#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_PAGE_MIDCMD_DATA2
>+#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_PAGE_MIDCMD_DATA3
>+#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_PAGE_MIDCMD_DATA4
>+#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_PAGE_MIDCMD_DATA5
>+#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_PAGE_MIDCMD_DATA6
>+#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_PAGE_MIDCMD_DATA7
>+#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_PAGE_MIDCMD_DATA8
>+#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_PAGE_MIDCMD_CNTL
>+#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA1_RLC0_RB_CNTL
>+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA1_RLC0_RB_BASE
>+#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA1_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA1_RLC0_RB_BASE_HI
>+#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA1_RLC0_RB_RPTR
>+#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC0_RB_RPTR_HI
>+#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC0_RB_WPTR
>+#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC0_RB_WPTR_HI
>+#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC0_RB_WPTR_POLL_CNTL
>+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA1_RLC0_RB_RPTR_ADDR_HI
>+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA1_RLC0_RB_RPTR_ADDR_LO
>+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA1_RLC0_IB_CNTL
>+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA1_RLC0_IB_RPTR
>+#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA1_RLC0_IB_OFFSET
>+#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA1_RLC0_IB_BASE_LO
>+#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA1_RLC0_IB_BASE_HI
>+#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC0_IB_SIZE
>+#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA1_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA1_RLC0_SKIP_CNTL
>+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA1_RLC0_CONTEXT_STATUS
>+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA1_RLC0_DOORBELL
>+#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA1_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA1_RLC0_STATUS
>+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA1_RLC0_DOORBELL_LOG
>+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA1_RLC0_WATERMARK
>+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA1_RLC0_DOORBELL_OFFSET
>+#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA1_RLC0_CSA_ADDR_LO
>+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA1_RLC0_CSA_ADDR_HI
>+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA1_RLC0_IB_SUB_REMAIN
>+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA1_RLC0_PREEMPT
>+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA1_RLC0_DUMMY_REG
>+#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI
>+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO
>+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA1_RLC0_RB_AQL_CNTL
>+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA1_RLC0_MINOR_PTR_UPDATE
>+#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA1_RLC0_MIDCMD_DATA0
>+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC0_MIDCMD_DATA1
>+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC0_MIDCMD_DATA2
>+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC0_MIDCMD_DATA3
>+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC0_MIDCMD_DATA4
>+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC0_MIDCMD_DATA5
>+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC0_MIDCMD_DATA6
>+#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC0_MIDCMD_DATA7
>+#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC0_MIDCMD_DATA8
>+#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC0_MIDCMD_CNTL
>+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA1_RLC1_RB_CNTL
>+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA1_RLC1_RB_BASE
>+#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA1_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA1_RLC1_RB_BASE_HI
>+#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA1_RLC1_RB_RPTR
>+#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC1_RB_RPTR_HI
>+#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC1_RB_WPTR
>+#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC1_RB_WPTR_HI
>+#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC1_RB_WPTR_POLL_CNTL
>+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA1_RLC1_RB_RPTR_ADDR_HI
>+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA1_RLC1_RB_RPTR_ADDR_LO
>+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA1_RLC1_IB_CNTL
>+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA1_RLC1_IB_RPTR
>+#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA1_RLC1_IB_OFFSET
>+#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA1_RLC1_IB_BASE_LO
>+#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA1_RLC1_IB_BASE_HI
>+#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC1_IB_SIZE
>+#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA1_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA1_RLC1_SKIP_CNTL
>+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA1_RLC1_CONTEXT_STATUS
>+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA1_RLC1_DOORBELL
>+#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA1_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA1_RLC1_STATUS
>+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA1_RLC1_DOORBELL_LOG
>+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA1_RLC1_WATERMARK
>+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA1_RLC1_DOORBELL_OFFSET
>+#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA1_RLC1_CSA_ADDR_LO
>+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA1_RLC1_CSA_ADDR_HI
>+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA1_RLC1_IB_SUB_REMAIN
>+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA1_RLC1_PREEMPT
>+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA1_RLC1_DUMMY_REG
>+#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI
>+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO
>+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA1_RLC1_RB_AQL_CNTL
>+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA1_RLC1_MINOR_PTR_UPDATE
>+#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA1_RLC1_MIDCMD_DATA0
>+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC1_MIDCMD_DATA1
>+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC1_MIDCMD_DATA2
>+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC1_MIDCMD_DATA3
>+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC1_MIDCMD_DATA4
>+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC1_MIDCMD_DATA5
>+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC1_MIDCMD_DATA6
>+#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC1_MIDCMD_DATA7
>+#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC1_MIDCMD_DATA8
>+#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC1_MIDCMD_CNTL
>+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA1_RLC2_RB_CNTL
>+#define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA1_RLC2_RB_BASE
>+#define SDMA1_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA1_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA1_RLC2_RB_BASE_HI
>+#define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA1_RLC2_RB_RPTR
>+#define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC2_RB_RPTR_HI
>+#define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC2_RB_WPTR
>+#define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC2_RB_WPTR_HI
>+#define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC2_RB_WPTR_POLL_CNTL
>+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA1_RLC2_RB_RPTR_ADDR_HI
>+#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA1_RLC2_RB_RPTR_ADDR_LO
>+#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA1_RLC2_IB_CNTL
>+#define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA1_RLC2_IB_RPTR
>+#define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA1_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA1_RLC2_IB_OFFSET
>+#define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA1_RLC2_IB_BASE_LO
>+#define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA1_RLC2_IB_BASE_HI
>+#define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC2_IB_SIZE
>+#define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA1_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA1_RLC2_SKIP_CNTL
>+#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA1_RLC2_CONTEXT_STATUS
>+#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA1_RLC2_DOORBELL
>+#define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA1_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA1_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA1_RLC2_STATUS
>+#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA1_RLC2_DOORBELL_LOG
>+#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA1_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA1_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA1_RLC2_WATERMARK
>+#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA1_RLC2_DOORBELL_OFFSET
>+#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA1_RLC2_CSA_ADDR_LO
>+#define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA1_RLC2_CSA_ADDR_HI
>+#define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA1_RLC2_IB_SUB_REMAIN
>+#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA1_RLC2_PREEMPT
>+#define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA1_RLC2_DUMMY_REG
>+#define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI
>+#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO
>+#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA1_RLC2_RB_AQL_CNTL
>+#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA1_RLC2_MINOR_PTR_UPDATE
>+#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA1_RLC2_MIDCMD_DATA0
>+#define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC2_MIDCMD_DATA1
>+#define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC2_MIDCMD_DATA2
>+#define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC2_MIDCMD_DATA3
>+#define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC2_MIDCMD_DATA4
>+#define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC2_MIDCMD_DATA5
>+#define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC2_MIDCMD_DATA6
>+#define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC2_MIDCMD_DATA7
>+#define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC2_MIDCMD_DATA8
>+#define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC2_MIDCMD_CNTL
>+#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA1_RLC3_RB_CNTL
>+#define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA1_RLC3_RB_BASE
>+#define SDMA1_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA1_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA1_RLC3_RB_BASE_HI
>+#define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA1_RLC3_RB_RPTR
>+#define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC3_RB_RPTR_HI
>+#define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC3_RB_WPTR
>+#define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC3_RB_WPTR_HI
>+#define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC3_RB_WPTR_POLL_CNTL
>+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA1_RLC3_RB_RPTR_ADDR_HI
>+#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA1_RLC3_RB_RPTR_ADDR_LO
>+#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA1_RLC3_IB_CNTL
>+#define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA1_RLC3_IB_RPTR
>+#define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA1_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA1_RLC3_IB_OFFSET
>+#define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA1_RLC3_IB_BASE_LO
>+#define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA1_RLC3_IB_BASE_HI
>+#define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC3_IB_SIZE
>+#define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA1_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA1_RLC3_SKIP_CNTL
>+#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA1_RLC3_CONTEXT_STATUS
>+#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA1_RLC3_DOORBELL
>+#define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA1_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA1_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA1_RLC3_STATUS
>+#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA1_RLC3_DOORBELL_LOG
>+#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA1_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA1_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA1_RLC3_WATERMARK
>+#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA1_RLC3_DOORBELL_OFFSET
>+#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA1_RLC3_CSA_ADDR_LO
>+#define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA1_RLC3_CSA_ADDR_HI
>+#define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA1_RLC3_IB_SUB_REMAIN
>+#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA1_RLC3_PREEMPT
>+#define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA1_RLC3_DUMMY_REG
>+#define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI
>+#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO
>+#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA1_RLC3_RB_AQL_CNTL
>+#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA1_RLC3_MINOR_PTR_UPDATE
>+#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA1_RLC3_MIDCMD_DATA0
>+#define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC3_MIDCMD_DATA1
>+#define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC3_MIDCMD_DATA2
>+#define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC3_MIDCMD_DATA3
>+#define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC3_MIDCMD_DATA4
>+#define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC3_MIDCMD_DATA5
>+#define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC3_MIDCMD_DATA6
>+#define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC3_MIDCMD_DATA7
>+#define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC3_MIDCMD_DATA8
>+#define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC3_MIDCMD_CNTL
>+#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA1_RLC4_RB_CNTL
>+#define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA1_RLC4_RB_BASE
>+#define SDMA1_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA1_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA1_RLC4_RB_BASE_HI
>+#define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA1_RLC4_RB_RPTR
>+#define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC4_RB_RPTR_HI
>+#define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC4_RB_WPTR
>+#define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC4_RB_WPTR_HI
>+#define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC4_RB_WPTR_POLL_CNTL
>+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA1_RLC4_RB_RPTR_ADDR_HI
>+#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA1_RLC4_RB_RPTR_ADDR_LO
>+#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA1_RLC4_IB_CNTL
>+#define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA1_RLC4_IB_RPTR
>+#define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA1_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA1_RLC4_IB_OFFSET
>+#define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA1_RLC4_IB_BASE_LO
>+#define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA1_RLC4_IB_BASE_HI
>+#define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC4_IB_SIZE
>+#define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA1_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA1_RLC4_SKIP_CNTL
>+#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA1_RLC4_CONTEXT_STATUS
>+#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA1_RLC4_DOORBELL
>+#define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA1_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA1_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA1_RLC4_STATUS
>+#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA1_RLC4_DOORBELL_LOG
>+#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA1_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA1_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA1_RLC4_WATERMARK
>+#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA1_RLC4_DOORBELL_OFFSET
>+#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA1_RLC4_CSA_ADDR_LO
>+#define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA1_RLC4_CSA_ADDR_HI
>+#define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA1_RLC4_IB_SUB_REMAIN
>+#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA1_RLC4_PREEMPT
>+#define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA1_RLC4_DUMMY_REG
>+#define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI
>+#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO
>+#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA1_RLC4_RB_AQL_CNTL
>+#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA1_RLC4_MINOR_PTR_UPDATE
>+#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA1_RLC4_MIDCMD_DATA0
>+#define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC4_MIDCMD_DATA1
>+#define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC4_MIDCMD_DATA2
>+#define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC4_MIDCMD_DATA3
>+#define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC4_MIDCMD_DATA4
>+#define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC4_MIDCMD_DATA5
>+#define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC4_MIDCMD_DATA6
>+#define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC4_MIDCMD_DATA7
>+#define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC4_MIDCMD_DATA8
>+#define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC4_MIDCMD_CNTL
>+#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA1_RLC5_RB_CNTL
>+#define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA1_RLC5_RB_BASE
>+#define SDMA1_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA1_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA1_RLC5_RB_BASE_HI
>+#define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA1_RLC5_RB_RPTR
>+#define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC5_RB_RPTR_HI
>+#define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC5_RB_WPTR
>+#define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC5_RB_WPTR_HI
>+#define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC5_RB_WPTR_POLL_CNTL
>+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA1_RLC5_RB_RPTR_ADDR_HI
>+#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA1_RLC5_RB_RPTR_ADDR_LO
>+#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA1_RLC5_IB_CNTL
>+#define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA1_RLC5_IB_RPTR
>+#define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA1_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA1_RLC5_IB_OFFSET
>+#define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA1_RLC5_IB_BASE_LO
>+#define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA1_RLC5_IB_BASE_HI
>+#define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC5_IB_SIZE
>+#define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA1_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA1_RLC5_SKIP_CNTL
>+#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA1_RLC5_CONTEXT_STATUS
>+#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA1_RLC5_DOORBELL
>+#define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA1_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA1_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA1_RLC5_STATUS
>+#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA1_RLC5_DOORBELL_LOG
>+#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA1_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA1_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA1_RLC5_WATERMARK
>+#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA1_RLC5_DOORBELL_OFFSET
>+#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA1_RLC5_CSA_ADDR_LO
>+#define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA1_RLC5_CSA_ADDR_HI
>+#define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA1_RLC5_IB_SUB_REMAIN
>+#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA1_RLC5_PREEMPT
>+#define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA1_RLC5_DUMMY_REG
>+#define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI
>+#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO
>+#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA1_RLC5_RB_AQL_CNTL
>+#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA1_RLC5_MINOR_PTR_UPDATE
>+#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA1_RLC5_MIDCMD_DATA0
>+#define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC5_MIDCMD_DATA1
>+#define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC5_MIDCMD_DATA2
>+#define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC5_MIDCMD_DATA3
>+#define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC5_MIDCMD_DATA4
>+#define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC5_MIDCMD_DATA5
>+#define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC5_MIDCMD_DATA6
>+#define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC5_MIDCMD_DATA7
>+#define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC5_MIDCMD_DATA8
>+#define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC5_MIDCMD_CNTL
>+#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA1_RLC6_RB_CNTL
>+#define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA1_RLC6_RB_BASE
>+#define SDMA1_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA1_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA1_RLC6_RB_BASE_HI
>+#define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA1_RLC6_RB_RPTR
>+#define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC6_RB_RPTR_HI
>+#define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC6_RB_WPTR
>+#define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC6_RB_WPTR_HI
>+#define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC6_RB_WPTR_POLL_CNTL
>+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA1_RLC6_RB_RPTR_ADDR_HI
>+#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA1_RLC6_RB_RPTR_ADDR_LO
>+#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA1_RLC6_IB_CNTL
>+#define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA1_RLC6_IB_RPTR
>+#define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA1_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA1_RLC6_IB_OFFSET
>+#define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA1_RLC6_IB_BASE_LO
>+#define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA1_RLC6_IB_BASE_HI
>+#define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC6_IB_SIZE
>+#define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA1_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA1_RLC6_SKIP_CNTL
>+#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA1_RLC6_CONTEXT_STATUS
>+#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA1_RLC6_DOORBELL
>+#define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA1_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA1_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA1_RLC6_STATUS
>+#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA1_RLC6_DOORBELL_LOG
>+#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA1_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA1_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA1_RLC6_WATERMARK
>+#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA1_RLC6_DOORBELL_OFFSET
>+#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA1_RLC6_CSA_ADDR_LO
>+#define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA1_RLC6_CSA_ADDR_HI
>+#define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA1_RLC6_IB_SUB_REMAIN
>+#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA1_RLC6_PREEMPT
>+#define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA1_RLC6_DUMMY_REG
>+#define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI
>+#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO
>+#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA1_RLC6_RB_AQL_CNTL
>+#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA1_RLC6_MINOR_PTR_UPDATE
>+#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA1_RLC6_MIDCMD_DATA0
>+#define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC6_MIDCMD_DATA1
>+#define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC6_MIDCMD_DATA2
>+#define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC6_MIDCMD_DATA3
>+#define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC6_MIDCMD_DATA4
>+#define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC6_MIDCMD_DATA5
>+#define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC6_MIDCMD_DATA6
>+#define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC6_MIDCMD_DATA7
>+#define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC6_MIDCMD_DATA8
>+#define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC6_MIDCMD_CNTL
>+#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA1_RLC7_RB_CNTL
>+#define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA1_RLC7_RB_BASE
>+#define SDMA1_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA1_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA1_RLC7_RB_BASE_HI
>+#define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA1_RLC7_RB_RPTR
>+#define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC7_RB_RPTR_HI
>+#define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC7_RB_WPTR
>+#define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA1_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA1_RLC7_RB_WPTR_HI
>+#define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA1_RLC7_RB_WPTR_POLL_CNTL
>+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA1_RLC7_RB_RPTR_ADDR_HI
>+#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA1_RLC7_RB_RPTR_ADDR_LO
>+#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA1_RLC7_IB_CNTL
>+#define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA1_RLC7_IB_RPTR
>+#define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA1_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA1_RLC7_IB_OFFSET
>+#define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA1_RLC7_IB_BASE_LO
>+#define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA1_RLC7_IB_BASE_HI
>+#define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC7_IB_SIZE
>+#define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA1_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA1_RLC7_SKIP_CNTL
>+#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA1_RLC7_CONTEXT_STATUS
>+#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA1_RLC7_DOORBELL
>+#define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA1_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA1_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA1_RLC7_STATUS
>+#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA1_RLC7_DOORBELL_LOG
>+#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA1_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA1_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA1_RLC7_WATERMARK
>+#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA1_RLC7_DOORBELL_OFFSET
>+#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA1_RLC7_CSA_ADDR_LO
>+#define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA1_RLC7_CSA_ADDR_HI
>+#define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA1_RLC7_IB_SUB_REMAIN
>+#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA1_RLC7_PREEMPT
>+#define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA1_RLC7_DUMMY_REG
>+#define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI
>+#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO
>+#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA1_RLC7_RB_AQL_CNTL
>+#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA1_RLC7_MINOR_PTR_UPDATE
>+#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA1_RLC7_MIDCMD_DATA0
>+#define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC7_MIDCMD_DATA1
>+#define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC7_MIDCMD_DATA2
>+#define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC7_MIDCMD_DATA3
>+#define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC7_MIDCMD_DATA4
>+#define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC7_MIDCMD_DATA5
>+#define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC7_MIDCMD_DATA6
>+#define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC7_MIDCMD_DATA7
>+#define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC7_MIDCMD_DATA8
>+#define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA1_RLC7_MIDCMD_CNTL
>+#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_offset.h	2019-08-31 15:01:11.931736175 -0500
>@@ -0,0 +1,1043 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma2_4_2_2_OFFSET_HEADER
>+#define _sdma2_4_2_2_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: sdma2_sdma2dec
>+// base address: 0x78000
>+#define mmSDMA2_UCODE_ADDR                                                                             0x0000
>+#define mmSDMA2_UCODE_ADDR_BASE_IDX                                                                    1
>+#define mmSDMA2_UCODE_DATA                                                                             0x0001
>+#define mmSDMA2_UCODE_DATA_BASE_IDX                                                                    1
>+#define mmSDMA2_VM_CNTL                                                                                0x0004
>+#define mmSDMA2_VM_CNTL_BASE_IDX                                                                       1
>+#define mmSDMA2_VM_CTX_LO                                                                              0x0005
>+#define mmSDMA2_VM_CTX_LO_BASE_IDX                                                                     1
>+#define mmSDMA2_VM_CTX_HI                                                                              0x0006
>+#define mmSDMA2_VM_CTX_HI_BASE_IDX                                                                     1
>+#define mmSDMA2_ACTIVE_FCN_ID                                                                          0x0007
>+#define mmSDMA2_ACTIVE_FCN_ID_BASE_IDX                                                                 1
>+#define mmSDMA2_VM_CTX_CNTL                                                                            0x0008
>+#define mmSDMA2_VM_CTX_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA2_VIRT_RESET_REQ                                                                         0x0009
>+#define mmSDMA2_VIRT_RESET_REQ_BASE_IDX                                                                1
>+#define mmSDMA2_VF_ENABLE                                                                              0x000a
>+#define mmSDMA2_VF_ENABLE_BASE_IDX                                                                     1
>+#define mmSDMA2_CONTEXT_REG_TYPE0                                                                      0x000b
>+#define mmSDMA2_CONTEXT_REG_TYPE0_BASE_IDX                                                             1
>+#define mmSDMA2_CONTEXT_REG_TYPE1                                                                      0x000c
>+#define mmSDMA2_CONTEXT_REG_TYPE1_BASE_IDX                                                             1
>+#define mmSDMA2_CONTEXT_REG_TYPE2                                                                      0x000d
>+#define mmSDMA2_CONTEXT_REG_TYPE2_BASE_IDX                                                             1
>+#define mmSDMA2_CONTEXT_REG_TYPE3                                                                      0x000e
>+#define mmSDMA2_CONTEXT_REG_TYPE3_BASE_IDX                                                             1
>+#define mmSDMA2_PUB_REG_TYPE0                                                                          0x000f
>+#define mmSDMA2_PUB_REG_TYPE0_BASE_IDX                                                                 1
>+#define mmSDMA2_PUB_REG_TYPE1                                                                          0x0010
>+#define mmSDMA2_PUB_REG_TYPE1_BASE_IDX                                                                 1
>+#define mmSDMA2_PUB_REG_TYPE2                                                                          0x0011
>+#define mmSDMA2_PUB_REG_TYPE2_BASE_IDX                                                                 1
>+#define mmSDMA2_PUB_REG_TYPE3                                                                          0x0012
>+#define mmSDMA2_PUB_REG_TYPE3_BASE_IDX                                                                 1
>+#define mmSDMA2_MMHUB_CNTL                                                                             0x0013
>+#define mmSDMA2_MMHUB_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA2_CONTEXT_GROUP_BOUNDARY                                                                 0x0019
>+#define mmSDMA2_CONTEXT_GROUP_BOUNDARY_BASE_IDX                                                        1
>+#define mmSDMA2_POWER_CNTL                                                                             0x001a
>+#define mmSDMA2_POWER_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA2_CLK_CTRL                                                                               0x001b
>+#define mmSDMA2_CLK_CTRL_BASE_IDX                                                                      1
>+#define mmSDMA2_CNTL                                                                                   0x001c
>+#define mmSDMA2_CNTL_BASE_IDX                                                                          1
>+#define mmSDMA2_CHICKEN_BITS                                                                           0x001d
>+#define mmSDMA2_CHICKEN_BITS_BASE_IDX                                                                  1
>+#define mmSDMA2_GB_ADDR_CONFIG                                                                         0x001e
>+#define mmSDMA2_GB_ADDR_CONFIG_BASE_IDX                                                                1
>+#define mmSDMA2_GB_ADDR_CONFIG_READ                                                                    0x001f
>+#define mmSDMA2_GB_ADDR_CONFIG_READ_BASE_IDX                                                           1
>+#define mmSDMA2_RB_RPTR_FETCH_HI                                                                       0x0020
>+#define mmSDMA2_RB_RPTR_FETCH_HI_BASE_IDX                                                              1
>+#define mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0021
>+#define mmSDMA2_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      1
>+#define mmSDMA2_RB_RPTR_FETCH                                                                          0x0022
>+#define mmSDMA2_RB_RPTR_FETCH_BASE_IDX                                                                 1
>+#define mmSDMA2_IB_OFFSET_FETCH                                                                        0x0023
>+#define mmSDMA2_IB_OFFSET_FETCH_BASE_IDX                                                               1
>+#define mmSDMA2_PROGRAM                                                                                0x0024
>+#define mmSDMA2_PROGRAM_BASE_IDX                                                                       1
>+#define mmSDMA2_STATUS_REG                                                                             0x0025
>+#define mmSDMA2_STATUS_REG_BASE_IDX                                                                    1
>+#define mmSDMA2_STATUS1_REG                                                                            0x0026
>+#define mmSDMA2_STATUS1_REG_BASE_IDX                                                                   1
>+#define mmSDMA2_RD_BURST_CNTL                                                                          0x0027
>+#define mmSDMA2_RD_BURST_CNTL_BASE_IDX                                                                 1
>+#define mmSDMA2_HBM_PAGE_CONFIG                                                                        0x0028
>+#define mmSDMA2_HBM_PAGE_CONFIG_BASE_IDX                                                               1
>+#define mmSDMA2_UCODE_CHECKSUM                                                                         0x0029
>+#define mmSDMA2_UCODE_CHECKSUM_BASE_IDX                                                                1
>+#define mmSDMA2_F32_CNTL                                                                               0x002a
>+#define mmSDMA2_F32_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA2_FREEZE                                                                                 0x002b
>+#define mmSDMA2_FREEZE_BASE_IDX                                                                        1
>+#define mmSDMA2_PHASE0_QUANTUM                                                                         0x002c
>+#define mmSDMA2_PHASE0_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA2_PHASE1_QUANTUM                                                                         0x002d
>+#define mmSDMA2_PHASE1_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA2_EDC_CONFIG                                                                             0x0032
>+#define mmSDMA2_EDC_CONFIG_BASE_IDX                                                                    1
>+#define mmSDMA2_BA_THRESHOLD                                                                           0x0033
>+#define mmSDMA2_BA_THRESHOLD_BASE_IDX                                                                  1
>+#define mmSDMA2_ID                                                                                     0x0034
>+#define mmSDMA2_ID_BASE_IDX                                                                            1
>+#define mmSDMA2_VERSION                                                                                0x0035
>+#define mmSDMA2_VERSION_BASE_IDX                                                                       1
>+#define mmSDMA2_EDC_COUNTER                                                                            0x0036
>+#define mmSDMA2_EDC_COUNTER_BASE_IDX                                                                   1
>+#define mmSDMA2_EDC_COUNTER_CLEAR                                                                      0x0037
>+#define mmSDMA2_EDC_COUNTER_CLEAR_BASE_IDX                                                             1
>+#define mmSDMA2_STATUS2_REG                                                                            0x0038
>+#define mmSDMA2_STATUS2_REG_BASE_IDX                                                                   1
>+#define mmSDMA2_ATOMIC_CNTL                                                                            0x0039
>+#define mmSDMA2_ATOMIC_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA2_ATOMIC_PREOP_LO                                                                        0x003a
>+#define mmSDMA2_ATOMIC_PREOP_LO_BASE_IDX                                                               1
>+#define mmSDMA2_ATOMIC_PREOP_HI                                                                        0x003b
>+#define mmSDMA2_ATOMIC_PREOP_HI_BASE_IDX                                                               1
>+#define mmSDMA2_UTCL1_CNTL                                                                             0x003c
>+#define mmSDMA2_UTCL1_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA2_UTCL1_WATERMK                                                                          0x003d
>+#define mmSDMA2_UTCL1_WATERMK_BASE_IDX                                                                 1
>+#define mmSDMA2_UTCL1_RD_STATUS                                                                        0x003e
>+#define mmSDMA2_UTCL1_RD_STATUS_BASE_IDX                                                               1
>+#define mmSDMA2_UTCL1_WR_STATUS                                                                        0x003f
>+#define mmSDMA2_UTCL1_WR_STATUS_BASE_IDX                                                               1
>+#define mmSDMA2_UTCL1_INV0                                                                             0x0040
>+#define mmSDMA2_UTCL1_INV0_BASE_IDX                                                                    1
>+#define mmSDMA2_UTCL1_INV1                                                                             0x0041
>+#define mmSDMA2_UTCL1_INV1_BASE_IDX                                                                    1
>+#define mmSDMA2_UTCL1_INV2                                                                             0x0042
>+#define mmSDMA2_UTCL1_INV2_BASE_IDX                                                                    1
>+#define mmSDMA2_UTCL1_RD_XNACK0                                                                        0x0043
>+#define mmSDMA2_UTCL1_RD_XNACK0_BASE_IDX                                                               1
>+#define mmSDMA2_UTCL1_RD_XNACK1                                                                        0x0044
>+#define mmSDMA2_UTCL1_RD_XNACK1_BASE_IDX                                                               1
>+#define mmSDMA2_UTCL1_WR_XNACK0                                                                        0x0045
>+#define mmSDMA2_UTCL1_WR_XNACK0_BASE_IDX                                                               1
>+#define mmSDMA2_UTCL1_WR_XNACK1                                                                        0x0046
>+#define mmSDMA2_UTCL1_WR_XNACK1_BASE_IDX                                                               1
>+#define mmSDMA2_UTCL1_TIMEOUT                                                                          0x0047
>+#define mmSDMA2_UTCL1_TIMEOUT_BASE_IDX                                                                 1
>+#define mmSDMA2_UTCL1_PAGE                                                                             0x0048
>+#define mmSDMA2_UTCL1_PAGE_BASE_IDX                                                                    1
>+#define mmSDMA2_POWER_CNTL_IDLE                                                                        0x0049
>+#define mmSDMA2_POWER_CNTL_IDLE_BASE_IDX                                                               1
>+#define mmSDMA2_RELAX_ORDERING_LUT                                                                     0x004a
>+#define mmSDMA2_RELAX_ORDERING_LUT_BASE_IDX                                                            1
>+#define mmSDMA2_CHICKEN_BITS_2                                                                         0x004b
>+#define mmSDMA2_CHICKEN_BITS_2_BASE_IDX                                                                1
>+#define mmSDMA2_STATUS3_REG                                                                            0x004c
>+#define mmSDMA2_STATUS3_REG_BASE_IDX                                                                   1
>+#define mmSDMA2_PHYSICAL_ADDR_LO                                                                       0x004d
>+#define mmSDMA2_PHYSICAL_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA2_PHYSICAL_ADDR_HI                                                                       0x004e
>+#define mmSDMA2_PHYSICAL_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA2_PHASE2_QUANTUM                                                                         0x004f
>+#define mmSDMA2_PHASE2_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA2_ERROR_LOG                                                                              0x0050
>+#define mmSDMA2_ERROR_LOG_BASE_IDX                                                                     1
>+#define mmSDMA2_PUB_DUMMY_REG0                                                                         0x0051
>+#define mmSDMA2_PUB_DUMMY_REG0_BASE_IDX                                                                1
>+#define mmSDMA2_PUB_DUMMY_REG1                                                                         0x0052
>+#define mmSDMA2_PUB_DUMMY_REG1_BASE_IDX                                                                1
>+#define mmSDMA2_PUB_DUMMY_REG2                                                                         0x0053
>+#define mmSDMA2_PUB_DUMMY_REG2_BASE_IDX                                                                1
>+#define mmSDMA2_PUB_DUMMY_REG3                                                                         0x0054
>+#define mmSDMA2_PUB_DUMMY_REG3_BASE_IDX                                                                1
>+#define mmSDMA2_F32_COUNTER                                                                            0x0055
>+#define mmSDMA2_F32_COUNTER_BASE_IDX                                                                   1
>+#define mmSDMA2_UNBREAKABLE                                                                            0x0056
>+#define mmSDMA2_UNBREAKABLE_BASE_IDX                                                                   1
>+#define mmSDMA2_PERFMON_CNTL                                                                           0x0057
>+#define mmSDMA2_PERFMON_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_PERFCOUNTER0_RESULT                                                                    0x0058
>+#define mmSDMA2_PERFCOUNTER0_RESULT_BASE_IDX                                                           1
>+#define mmSDMA2_PERFCOUNTER1_RESULT                                                                    0x0059
>+#define mmSDMA2_PERFCOUNTER1_RESULT_BASE_IDX                                                           1
>+#define mmSDMA2_PERFCOUNTER_TAG_DELAY_RANGE                                                            0x005a
>+#define mmSDMA2_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX                                                   1
>+#define mmSDMA2_CRD_CNTL                                                                               0x005b
>+#define mmSDMA2_CRD_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA2_GPU_IOV_VIOLATION_LOG                                                                  0x005d
>+#define mmSDMA2_GPU_IOV_VIOLATION_LOG_BASE_IDX                                                         1
>+#define mmSDMA2_ULV_CNTL                                                                               0x005e
>+#define mmSDMA2_ULV_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA2_EA_DBIT_ADDR_DATA                                                                      0x0060
>+#define mmSDMA2_EA_DBIT_ADDR_DATA_BASE_IDX                                                             1
>+#define mmSDMA2_EA_DBIT_ADDR_INDEX                                                                     0x0061
>+#define mmSDMA2_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            1
>+#define mmSDMA2_GPU_IOV_VIOLATION_LOG2                                                                 0x0062
>+#define mmSDMA2_GPU_IOV_VIOLATION_LOG2_BASE_IDX                                                        1
>+#define mmSDMA2_GFX_RB_CNTL                                                                            0x0080
>+#define mmSDMA2_GFX_RB_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA2_GFX_RB_BASE                                                                            0x0081
>+#define mmSDMA2_GFX_RB_BASE_BASE_IDX                                                                   1
>+#define mmSDMA2_GFX_RB_BASE_HI                                                                         0x0082
>+#define mmSDMA2_GFX_RB_BASE_HI_BASE_IDX                                                                1
>+#define mmSDMA2_GFX_RB_RPTR                                                                            0x0083
>+#define mmSDMA2_GFX_RB_RPTR_BASE_IDX                                                                   1
>+#define mmSDMA2_GFX_RB_RPTR_HI                                                                         0x0084
>+#define mmSDMA2_GFX_RB_RPTR_HI_BASE_IDX                                                                1
>+#define mmSDMA2_GFX_RB_WPTR                                                                            0x0085
>+#define mmSDMA2_GFX_RB_WPTR_BASE_IDX                                                                   1
>+#define mmSDMA2_GFX_RB_WPTR_HI                                                                         0x0086
>+#define mmSDMA2_GFX_RB_WPTR_HI_BASE_IDX                                                                1
>+#define mmSDMA2_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
>+#define mmSDMA2_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         1
>+#define mmSDMA2_GFX_RB_RPTR_ADDR_HI                                                                    0x0088
>+#define mmSDMA2_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           1
>+#define mmSDMA2_GFX_RB_RPTR_ADDR_LO                                                                    0x0089
>+#define mmSDMA2_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           1
>+#define mmSDMA2_GFX_IB_CNTL                                                                            0x008a
>+#define mmSDMA2_GFX_IB_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA2_GFX_IB_RPTR                                                                            0x008b
>+#define mmSDMA2_GFX_IB_RPTR_BASE_IDX                                                                   1
>+#define mmSDMA2_GFX_IB_OFFSET                                                                          0x008c
>+#define mmSDMA2_GFX_IB_OFFSET_BASE_IDX                                                                 1
>+#define mmSDMA2_GFX_IB_BASE_LO                                                                         0x008d
>+#define mmSDMA2_GFX_IB_BASE_LO_BASE_IDX                                                                1
>+#define mmSDMA2_GFX_IB_BASE_HI                                                                         0x008e
>+#define mmSDMA2_GFX_IB_BASE_HI_BASE_IDX                                                                1
>+#define mmSDMA2_GFX_IB_SIZE                                                                            0x008f
>+#define mmSDMA2_GFX_IB_SIZE_BASE_IDX                                                                   1
>+#define mmSDMA2_GFX_SKIP_CNTL                                                                          0x0090
>+#define mmSDMA2_GFX_SKIP_CNTL_BASE_IDX                                                                 1
>+#define mmSDMA2_GFX_CONTEXT_STATUS                                                                     0x0091
>+#define mmSDMA2_GFX_CONTEXT_STATUS_BASE_IDX                                                            1
>+#define mmSDMA2_GFX_DOORBELL                                                                           0x0092
>+#define mmSDMA2_GFX_DOORBELL_BASE_IDX                                                                  1
>+#define mmSDMA2_GFX_CONTEXT_CNTL                                                                       0x0093
>+#define mmSDMA2_GFX_CONTEXT_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_GFX_STATUS                                                                             0x00a8
>+#define mmSDMA2_GFX_STATUS_BASE_IDX                                                                    1
>+#define mmSDMA2_GFX_DOORBELL_LOG                                                                       0x00a9
>+#define mmSDMA2_GFX_DOORBELL_LOG_BASE_IDX                                                              1
>+#define mmSDMA2_GFX_WATERMARK                                                                          0x00aa
>+#define mmSDMA2_GFX_WATERMARK_BASE_IDX                                                                 1
>+#define mmSDMA2_GFX_DOORBELL_OFFSET                                                                    0x00ab
>+#define mmSDMA2_GFX_DOORBELL_OFFSET_BASE_IDX                                                           1
>+#define mmSDMA2_GFX_CSA_ADDR_LO                                                                        0x00ac
>+#define mmSDMA2_GFX_CSA_ADDR_LO_BASE_IDX                                                               1
>+#define mmSDMA2_GFX_CSA_ADDR_HI                                                                        0x00ad
>+#define mmSDMA2_GFX_CSA_ADDR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_GFX_IB_SUB_REMAIN                                                                      0x00af
>+#define mmSDMA2_GFX_IB_SUB_REMAIN_BASE_IDX                                                             1
>+#define mmSDMA2_GFX_PREEMPT                                                                            0x00b0
>+#define mmSDMA2_GFX_PREEMPT_BASE_IDX                                                                   1
>+#define mmSDMA2_GFX_DUMMY_REG                                                                          0x00b1
>+#define mmSDMA2_GFX_DUMMY_REG_BASE_IDX                                                                 1
>+#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x00b2
>+#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      1
>+#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x00b3
>+#define mmSDMA2_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      1
>+#define mmSDMA2_GFX_RB_AQL_CNTL                                                                        0x00b4
>+#define mmSDMA2_GFX_RB_AQL_CNTL_BASE_IDX                                                               1
>+#define mmSDMA2_GFX_MINOR_PTR_UPDATE                                                                   0x00b5
>+#define mmSDMA2_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          1
>+#define mmSDMA2_GFX_MIDCMD_DATA0                                                                       0x00c0
>+#define mmSDMA2_GFX_MIDCMD_DATA0_BASE_IDX                                                              1
>+#define mmSDMA2_GFX_MIDCMD_DATA1                                                                       0x00c1
>+#define mmSDMA2_GFX_MIDCMD_DATA1_BASE_IDX                                                              1
>+#define mmSDMA2_GFX_MIDCMD_DATA2                                                                       0x00c2
>+#define mmSDMA2_GFX_MIDCMD_DATA2_BASE_IDX                                                              1
>+#define mmSDMA2_GFX_MIDCMD_DATA3                                                                       0x00c3
>+#define mmSDMA2_GFX_MIDCMD_DATA3_BASE_IDX                                                              1
>+#define mmSDMA2_GFX_MIDCMD_DATA4                                                                       0x00c4
>+#define mmSDMA2_GFX_MIDCMD_DATA4_BASE_IDX                                                              1
>+#define mmSDMA2_GFX_MIDCMD_DATA5                                                                       0x00c5
>+#define mmSDMA2_GFX_MIDCMD_DATA5_BASE_IDX                                                              1
>+#define mmSDMA2_GFX_MIDCMD_DATA6                                                                       0x00c6
>+#define mmSDMA2_GFX_MIDCMD_DATA6_BASE_IDX                                                              1
>+#define mmSDMA2_GFX_MIDCMD_DATA7                                                                       0x00c7
>+#define mmSDMA2_GFX_MIDCMD_DATA7_BASE_IDX                                                              1
>+#define mmSDMA2_GFX_MIDCMD_DATA8                                                                       0x00c8
>+#define mmSDMA2_GFX_MIDCMD_DATA8_BASE_IDX                                                              1
>+#define mmSDMA2_GFX_MIDCMD_CNTL                                                                        0x00c9
>+#define mmSDMA2_GFX_MIDCMD_CNTL_BASE_IDX                                                               1
>+#define mmSDMA2_PAGE_RB_CNTL                                                                           0x00d8
>+#define mmSDMA2_PAGE_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_PAGE_RB_BASE                                                                           0x00d9
>+#define mmSDMA2_PAGE_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA2_PAGE_RB_BASE_HI                                                                        0x00da
>+#define mmSDMA2_PAGE_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_PAGE_RB_RPTR                                                                           0x00db
>+#define mmSDMA2_PAGE_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_PAGE_RB_RPTR_HI                                                                        0x00dc
>+#define mmSDMA2_PAGE_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_PAGE_RB_WPTR                                                                           0x00dd
>+#define mmSDMA2_PAGE_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_PAGE_RB_WPTR_HI                                                                        0x00de
>+#define mmSDMA2_PAGE_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_PAGE_RB_WPTR_POLL_CNTL                                                                 0x00df
>+#define mmSDMA2_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA2_PAGE_RB_RPTR_ADDR_HI                                                                   0x00e0
>+#define mmSDMA2_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA2_PAGE_RB_RPTR_ADDR_LO                                                                   0x00e1
>+#define mmSDMA2_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA2_PAGE_IB_CNTL                                                                           0x00e2
>+#define mmSDMA2_PAGE_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_PAGE_IB_RPTR                                                                           0x00e3
>+#define mmSDMA2_PAGE_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_PAGE_IB_OFFSET                                                                         0x00e4
>+#define mmSDMA2_PAGE_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA2_PAGE_IB_BASE_LO                                                                        0x00e5
>+#define mmSDMA2_PAGE_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA2_PAGE_IB_BASE_HI                                                                        0x00e6
>+#define mmSDMA2_PAGE_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_PAGE_IB_SIZE                                                                           0x00e7
>+#define mmSDMA2_PAGE_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA2_PAGE_SKIP_CNTL                                                                         0x00e8
>+#define mmSDMA2_PAGE_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA2_PAGE_CONTEXT_STATUS                                                                    0x00e9
>+#define mmSDMA2_PAGE_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA2_PAGE_DOORBELL                                                                          0x00ea
>+#define mmSDMA2_PAGE_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA2_PAGE_STATUS                                                                            0x0100
>+#define mmSDMA2_PAGE_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA2_PAGE_DOORBELL_LOG                                                                      0x0101
>+#define mmSDMA2_PAGE_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA2_PAGE_WATERMARK                                                                         0x0102
>+#define mmSDMA2_PAGE_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA2_PAGE_DOORBELL_OFFSET                                                                   0x0103
>+#define mmSDMA2_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA2_PAGE_CSA_ADDR_LO                                                                       0x0104
>+#define mmSDMA2_PAGE_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA2_PAGE_CSA_ADDR_HI                                                                       0x0105
>+#define mmSDMA2_PAGE_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA2_PAGE_IB_SUB_REMAIN                                                                     0x0107
>+#define mmSDMA2_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA2_PAGE_PREEMPT                                                                           0x0108
>+#define mmSDMA2_PAGE_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA2_PAGE_DUMMY_REG                                                                         0x0109
>+#define mmSDMA2_PAGE_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x010a
>+#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x010b
>+#define mmSDMA2_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA2_PAGE_RB_AQL_CNTL                                                                       0x010c
>+#define mmSDMA2_PAGE_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_PAGE_MINOR_PTR_UPDATE                                                                  0x010d
>+#define mmSDMA2_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA2_PAGE_MIDCMD_DATA0                                                                      0x0118
>+#define mmSDMA2_PAGE_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA2_PAGE_MIDCMD_DATA1                                                                      0x0119
>+#define mmSDMA2_PAGE_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA2_PAGE_MIDCMD_DATA2                                                                      0x011a
>+#define mmSDMA2_PAGE_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA2_PAGE_MIDCMD_DATA3                                                                      0x011b
>+#define mmSDMA2_PAGE_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA2_PAGE_MIDCMD_DATA4                                                                      0x011c
>+#define mmSDMA2_PAGE_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA2_PAGE_MIDCMD_DATA5                                                                      0x011d
>+#define mmSDMA2_PAGE_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA2_PAGE_MIDCMD_DATA6                                                                      0x011e
>+#define mmSDMA2_PAGE_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA2_PAGE_MIDCMD_DATA7                                                                      0x011f
>+#define mmSDMA2_PAGE_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA2_PAGE_MIDCMD_DATA8                                                                      0x0120
>+#define mmSDMA2_PAGE_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA2_PAGE_MIDCMD_CNTL                                                                       0x0121
>+#define mmSDMA2_PAGE_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC0_RB_CNTL                                                                           0x0130
>+#define mmSDMA2_RLC0_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC0_RB_BASE                                                                           0x0131
>+#define mmSDMA2_RLC0_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC0_RB_BASE_HI                                                                        0x0132
>+#define mmSDMA2_RLC0_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC0_RB_RPTR                                                                           0x0133
>+#define mmSDMA2_RLC0_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC0_RB_RPTR_HI                                                                        0x0134
>+#define mmSDMA2_RLC0_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC0_RB_WPTR                                                                           0x0135
>+#define mmSDMA2_RLC0_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC0_RB_WPTR_HI                                                                        0x0136
>+#define mmSDMA2_RLC0_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0137
>+#define mmSDMA2_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA2_RLC0_RB_RPTR_ADDR_HI                                                                   0x0138
>+#define mmSDMA2_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA2_RLC0_RB_RPTR_ADDR_LO                                                                   0x0139
>+#define mmSDMA2_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA2_RLC0_IB_CNTL                                                                           0x013a
>+#define mmSDMA2_RLC0_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC0_IB_RPTR                                                                           0x013b
>+#define mmSDMA2_RLC0_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC0_IB_OFFSET                                                                         0x013c
>+#define mmSDMA2_RLC0_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA2_RLC0_IB_BASE_LO                                                                        0x013d
>+#define mmSDMA2_RLC0_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA2_RLC0_IB_BASE_HI                                                                        0x013e
>+#define mmSDMA2_RLC0_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC0_IB_SIZE                                                                           0x013f
>+#define mmSDMA2_RLC0_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC0_SKIP_CNTL                                                                         0x0140
>+#define mmSDMA2_RLC0_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA2_RLC0_CONTEXT_STATUS                                                                    0x0141
>+#define mmSDMA2_RLC0_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA2_RLC0_DOORBELL                                                                          0x0142
>+#define mmSDMA2_RLC0_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA2_RLC0_STATUS                                                                            0x0158
>+#define mmSDMA2_RLC0_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA2_RLC0_DOORBELL_LOG                                                                      0x0159
>+#define mmSDMA2_RLC0_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA2_RLC0_WATERMARK                                                                         0x015a
>+#define mmSDMA2_RLC0_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA2_RLC0_DOORBELL_OFFSET                                                                   0x015b
>+#define mmSDMA2_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA2_RLC0_CSA_ADDR_LO                                                                       0x015c
>+#define mmSDMA2_RLC0_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA2_RLC0_CSA_ADDR_HI                                                                       0x015d
>+#define mmSDMA2_RLC0_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA2_RLC0_IB_SUB_REMAIN                                                                     0x015f
>+#define mmSDMA2_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA2_RLC0_PREEMPT                                                                           0x0160
>+#define mmSDMA2_RLC0_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC0_DUMMY_REG                                                                         0x0161
>+#define mmSDMA2_RLC0_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0162
>+#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0163
>+#define mmSDMA2_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA2_RLC0_RB_AQL_CNTL                                                                       0x0164
>+#define mmSDMA2_RLC0_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC0_MINOR_PTR_UPDATE                                                                  0x0165
>+#define mmSDMA2_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA2_RLC0_MIDCMD_DATA0                                                                      0x0170
>+#define mmSDMA2_RLC0_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA2_RLC0_MIDCMD_DATA1                                                                      0x0171
>+#define mmSDMA2_RLC0_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA2_RLC0_MIDCMD_DATA2                                                                      0x0172
>+#define mmSDMA2_RLC0_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA2_RLC0_MIDCMD_DATA3                                                                      0x0173
>+#define mmSDMA2_RLC0_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA2_RLC0_MIDCMD_DATA4                                                                      0x0174
>+#define mmSDMA2_RLC0_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA2_RLC0_MIDCMD_DATA5                                                                      0x0175
>+#define mmSDMA2_RLC0_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA2_RLC0_MIDCMD_DATA6                                                                      0x0176
>+#define mmSDMA2_RLC0_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA2_RLC0_MIDCMD_DATA7                                                                      0x0177
>+#define mmSDMA2_RLC0_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA2_RLC0_MIDCMD_DATA8                                                                      0x0178
>+#define mmSDMA2_RLC0_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA2_RLC0_MIDCMD_CNTL                                                                       0x0179
>+#define mmSDMA2_RLC0_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC1_RB_CNTL                                                                           0x0188
>+#define mmSDMA2_RLC1_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC1_RB_BASE                                                                           0x0189
>+#define mmSDMA2_RLC1_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC1_RB_BASE_HI                                                                        0x018a
>+#define mmSDMA2_RLC1_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC1_RB_RPTR                                                                           0x018b
>+#define mmSDMA2_RLC1_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC1_RB_RPTR_HI                                                                        0x018c
>+#define mmSDMA2_RLC1_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC1_RB_WPTR                                                                           0x018d
>+#define mmSDMA2_RLC1_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC1_RB_WPTR_HI                                                                        0x018e
>+#define mmSDMA2_RLC1_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC1_RB_WPTR_POLL_CNTL                                                                 0x018f
>+#define mmSDMA2_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA2_RLC1_RB_RPTR_ADDR_HI                                                                   0x0190
>+#define mmSDMA2_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA2_RLC1_RB_RPTR_ADDR_LO                                                                   0x0191
>+#define mmSDMA2_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA2_RLC1_IB_CNTL                                                                           0x0192
>+#define mmSDMA2_RLC1_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC1_IB_RPTR                                                                           0x0193
>+#define mmSDMA2_RLC1_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC1_IB_OFFSET                                                                         0x0194
>+#define mmSDMA2_RLC1_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA2_RLC1_IB_BASE_LO                                                                        0x0195
>+#define mmSDMA2_RLC1_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA2_RLC1_IB_BASE_HI                                                                        0x0196
>+#define mmSDMA2_RLC1_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC1_IB_SIZE                                                                           0x0197
>+#define mmSDMA2_RLC1_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC1_SKIP_CNTL                                                                         0x0198
>+#define mmSDMA2_RLC1_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA2_RLC1_CONTEXT_STATUS                                                                    0x0199
>+#define mmSDMA2_RLC1_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA2_RLC1_DOORBELL                                                                          0x019a
>+#define mmSDMA2_RLC1_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA2_RLC1_STATUS                                                                            0x01b0
>+#define mmSDMA2_RLC1_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA2_RLC1_DOORBELL_LOG                                                                      0x01b1
>+#define mmSDMA2_RLC1_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA2_RLC1_WATERMARK                                                                         0x01b2
>+#define mmSDMA2_RLC1_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA2_RLC1_DOORBELL_OFFSET                                                                   0x01b3
>+#define mmSDMA2_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA2_RLC1_CSA_ADDR_LO                                                                       0x01b4
>+#define mmSDMA2_RLC1_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA2_RLC1_CSA_ADDR_HI                                                                       0x01b5
>+#define mmSDMA2_RLC1_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA2_RLC1_IB_SUB_REMAIN                                                                     0x01b7
>+#define mmSDMA2_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA2_RLC1_PREEMPT                                                                           0x01b8
>+#define mmSDMA2_RLC1_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC1_DUMMY_REG                                                                         0x01b9
>+#define mmSDMA2_RLC1_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x01ba
>+#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x01bb
>+#define mmSDMA2_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA2_RLC1_RB_AQL_CNTL                                                                       0x01bc
>+#define mmSDMA2_RLC1_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC1_MINOR_PTR_UPDATE                                                                  0x01bd
>+#define mmSDMA2_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA2_RLC1_MIDCMD_DATA0                                                                      0x01c8
>+#define mmSDMA2_RLC1_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA2_RLC1_MIDCMD_DATA1                                                                      0x01c9
>+#define mmSDMA2_RLC1_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA2_RLC1_MIDCMD_DATA2                                                                      0x01ca
>+#define mmSDMA2_RLC1_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA2_RLC1_MIDCMD_DATA3                                                                      0x01cb
>+#define mmSDMA2_RLC1_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA2_RLC1_MIDCMD_DATA4                                                                      0x01cc
>+#define mmSDMA2_RLC1_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA2_RLC1_MIDCMD_DATA5                                                                      0x01cd
>+#define mmSDMA2_RLC1_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA2_RLC1_MIDCMD_DATA6                                                                      0x01ce
>+#define mmSDMA2_RLC1_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA2_RLC1_MIDCMD_DATA7                                                                      0x01cf
>+#define mmSDMA2_RLC1_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA2_RLC1_MIDCMD_DATA8                                                                      0x01d0
>+#define mmSDMA2_RLC1_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA2_RLC1_MIDCMD_CNTL                                                                       0x01d1
>+#define mmSDMA2_RLC1_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC2_RB_CNTL                                                                           0x01e0
>+#define mmSDMA2_RLC2_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC2_RB_BASE                                                                           0x01e1
>+#define mmSDMA2_RLC2_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC2_RB_BASE_HI                                                                        0x01e2
>+#define mmSDMA2_RLC2_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC2_RB_RPTR                                                                           0x01e3
>+#define mmSDMA2_RLC2_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC2_RB_RPTR_HI                                                                        0x01e4
>+#define mmSDMA2_RLC2_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC2_RB_WPTR                                                                           0x01e5
>+#define mmSDMA2_RLC2_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC2_RB_WPTR_HI                                                                        0x01e6
>+#define mmSDMA2_RLC2_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC2_RB_WPTR_POLL_CNTL                                                                 0x01e7
>+#define mmSDMA2_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA2_RLC2_RB_RPTR_ADDR_HI                                                                   0x01e8
>+#define mmSDMA2_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA2_RLC2_RB_RPTR_ADDR_LO                                                                   0x01e9
>+#define mmSDMA2_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA2_RLC2_IB_CNTL                                                                           0x01ea
>+#define mmSDMA2_RLC2_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC2_IB_RPTR                                                                           0x01eb
>+#define mmSDMA2_RLC2_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC2_IB_OFFSET                                                                         0x01ec
>+#define mmSDMA2_RLC2_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA2_RLC2_IB_BASE_LO                                                                        0x01ed
>+#define mmSDMA2_RLC2_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA2_RLC2_IB_BASE_HI                                                                        0x01ee
>+#define mmSDMA2_RLC2_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC2_IB_SIZE                                                                           0x01ef
>+#define mmSDMA2_RLC2_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC2_SKIP_CNTL                                                                         0x01f0
>+#define mmSDMA2_RLC2_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA2_RLC2_CONTEXT_STATUS                                                                    0x01f1
>+#define mmSDMA2_RLC2_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA2_RLC2_DOORBELL                                                                          0x01f2
>+#define mmSDMA2_RLC2_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA2_RLC2_STATUS                                                                            0x0208
>+#define mmSDMA2_RLC2_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA2_RLC2_DOORBELL_LOG                                                                      0x0209
>+#define mmSDMA2_RLC2_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA2_RLC2_WATERMARK                                                                         0x020a
>+#define mmSDMA2_RLC2_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA2_RLC2_DOORBELL_OFFSET                                                                   0x020b
>+#define mmSDMA2_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA2_RLC2_CSA_ADDR_LO                                                                       0x020c
>+#define mmSDMA2_RLC2_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA2_RLC2_CSA_ADDR_HI                                                                       0x020d
>+#define mmSDMA2_RLC2_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA2_RLC2_IB_SUB_REMAIN                                                                     0x020f
>+#define mmSDMA2_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA2_RLC2_PREEMPT                                                                           0x0210
>+#define mmSDMA2_RLC2_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC2_DUMMY_REG                                                                         0x0211
>+#define mmSDMA2_RLC2_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0212
>+#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0213
>+#define mmSDMA2_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA2_RLC2_RB_AQL_CNTL                                                                       0x0214
>+#define mmSDMA2_RLC2_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC2_MINOR_PTR_UPDATE                                                                  0x0215
>+#define mmSDMA2_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA2_RLC2_MIDCMD_DATA0                                                                      0x0220
>+#define mmSDMA2_RLC2_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA2_RLC2_MIDCMD_DATA1                                                                      0x0221
>+#define mmSDMA2_RLC2_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA2_RLC2_MIDCMD_DATA2                                                                      0x0222
>+#define mmSDMA2_RLC2_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA2_RLC2_MIDCMD_DATA3                                                                      0x0223
>+#define mmSDMA2_RLC2_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA2_RLC2_MIDCMD_DATA4                                                                      0x0224
>+#define mmSDMA2_RLC2_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA2_RLC2_MIDCMD_DATA5                                                                      0x0225
>+#define mmSDMA2_RLC2_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA2_RLC2_MIDCMD_DATA6                                                                      0x0226
>+#define mmSDMA2_RLC2_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA2_RLC2_MIDCMD_DATA7                                                                      0x0227
>+#define mmSDMA2_RLC2_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA2_RLC2_MIDCMD_DATA8                                                                      0x0228
>+#define mmSDMA2_RLC2_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA2_RLC2_MIDCMD_CNTL                                                                       0x0229
>+#define mmSDMA2_RLC2_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC3_RB_CNTL                                                                           0x0238
>+#define mmSDMA2_RLC3_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC3_RB_BASE                                                                           0x0239
>+#define mmSDMA2_RLC3_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC3_RB_BASE_HI                                                                        0x023a
>+#define mmSDMA2_RLC3_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC3_RB_RPTR                                                                           0x023b
>+#define mmSDMA2_RLC3_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC3_RB_RPTR_HI                                                                        0x023c
>+#define mmSDMA2_RLC3_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC3_RB_WPTR                                                                           0x023d
>+#define mmSDMA2_RLC3_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC3_RB_WPTR_HI                                                                        0x023e
>+#define mmSDMA2_RLC3_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC3_RB_WPTR_POLL_CNTL                                                                 0x023f
>+#define mmSDMA2_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA2_RLC3_RB_RPTR_ADDR_HI                                                                   0x0240
>+#define mmSDMA2_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA2_RLC3_RB_RPTR_ADDR_LO                                                                   0x0241
>+#define mmSDMA2_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA2_RLC3_IB_CNTL                                                                           0x0242
>+#define mmSDMA2_RLC3_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC3_IB_RPTR                                                                           0x0243
>+#define mmSDMA2_RLC3_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC3_IB_OFFSET                                                                         0x0244
>+#define mmSDMA2_RLC3_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA2_RLC3_IB_BASE_LO                                                                        0x0245
>+#define mmSDMA2_RLC3_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA2_RLC3_IB_BASE_HI                                                                        0x0246
>+#define mmSDMA2_RLC3_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC3_IB_SIZE                                                                           0x0247
>+#define mmSDMA2_RLC3_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC3_SKIP_CNTL                                                                         0x0248
>+#define mmSDMA2_RLC3_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA2_RLC3_CONTEXT_STATUS                                                                    0x0249
>+#define mmSDMA2_RLC3_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA2_RLC3_DOORBELL                                                                          0x024a
>+#define mmSDMA2_RLC3_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA2_RLC3_STATUS                                                                            0x0260
>+#define mmSDMA2_RLC3_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA2_RLC3_DOORBELL_LOG                                                                      0x0261
>+#define mmSDMA2_RLC3_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA2_RLC3_WATERMARK                                                                         0x0262
>+#define mmSDMA2_RLC3_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA2_RLC3_DOORBELL_OFFSET                                                                   0x0263
>+#define mmSDMA2_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA2_RLC3_CSA_ADDR_LO                                                                       0x0264
>+#define mmSDMA2_RLC3_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA2_RLC3_CSA_ADDR_HI                                                                       0x0265
>+#define mmSDMA2_RLC3_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA2_RLC3_IB_SUB_REMAIN                                                                     0x0267
>+#define mmSDMA2_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA2_RLC3_PREEMPT                                                                           0x0268
>+#define mmSDMA2_RLC3_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC3_DUMMY_REG                                                                         0x0269
>+#define mmSDMA2_RLC3_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x026a
>+#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x026b
>+#define mmSDMA2_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA2_RLC3_RB_AQL_CNTL                                                                       0x026c
>+#define mmSDMA2_RLC3_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC3_MINOR_PTR_UPDATE                                                                  0x026d
>+#define mmSDMA2_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA2_RLC3_MIDCMD_DATA0                                                                      0x0278
>+#define mmSDMA2_RLC3_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA2_RLC3_MIDCMD_DATA1                                                                      0x0279
>+#define mmSDMA2_RLC3_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA2_RLC3_MIDCMD_DATA2                                                                      0x027a
>+#define mmSDMA2_RLC3_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA2_RLC3_MIDCMD_DATA3                                                                      0x027b
>+#define mmSDMA2_RLC3_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA2_RLC3_MIDCMD_DATA4                                                                      0x027c
>+#define mmSDMA2_RLC3_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA2_RLC3_MIDCMD_DATA5                                                                      0x027d
>+#define mmSDMA2_RLC3_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA2_RLC3_MIDCMD_DATA6                                                                      0x027e
>+#define mmSDMA2_RLC3_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA2_RLC3_MIDCMD_DATA7                                                                      0x027f
>+#define mmSDMA2_RLC3_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA2_RLC3_MIDCMD_DATA8                                                                      0x0280
>+#define mmSDMA2_RLC3_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA2_RLC3_MIDCMD_CNTL                                                                       0x0281
>+#define mmSDMA2_RLC3_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC4_RB_CNTL                                                                           0x0290
>+#define mmSDMA2_RLC4_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC4_RB_BASE                                                                           0x0291
>+#define mmSDMA2_RLC4_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC4_RB_BASE_HI                                                                        0x0292
>+#define mmSDMA2_RLC4_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC4_RB_RPTR                                                                           0x0293
>+#define mmSDMA2_RLC4_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC4_RB_RPTR_HI                                                                        0x0294
>+#define mmSDMA2_RLC4_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC4_RB_WPTR                                                                           0x0295
>+#define mmSDMA2_RLC4_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC4_RB_WPTR_HI                                                                        0x0296
>+#define mmSDMA2_RLC4_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC4_RB_WPTR_POLL_CNTL                                                                 0x0297
>+#define mmSDMA2_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA2_RLC4_RB_RPTR_ADDR_HI                                                                   0x0298
>+#define mmSDMA2_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA2_RLC4_RB_RPTR_ADDR_LO                                                                   0x0299
>+#define mmSDMA2_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA2_RLC4_IB_CNTL                                                                           0x029a
>+#define mmSDMA2_RLC4_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC4_IB_RPTR                                                                           0x029b
>+#define mmSDMA2_RLC4_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC4_IB_OFFSET                                                                         0x029c
>+#define mmSDMA2_RLC4_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA2_RLC4_IB_BASE_LO                                                                        0x029d
>+#define mmSDMA2_RLC4_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA2_RLC4_IB_BASE_HI                                                                        0x029e
>+#define mmSDMA2_RLC4_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC4_IB_SIZE                                                                           0x029f
>+#define mmSDMA2_RLC4_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC4_SKIP_CNTL                                                                         0x02a0
>+#define mmSDMA2_RLC4_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA2_RLC4_CONTEXT_STATUS                                                                    0x02a1
>+#define mmSDMA2_RLC4_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA2_RLC4_DOORBELL                                                                          0x02a2
>+#define mmSDMA2_RLC4_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA2_RLC4_STATUS                                                                            0x02b8
>+#define mmSDMA2_RLC4_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA2_RLC4_DOORBELL_LOG                                                                      0x02b9
>+#define mmSDMA2_RLC4_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA2_RLC4_WATERMARK                                                                         0x02ba
>+#define mmSDMA2_RLC4_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA2_RLC4_DOORBELL_OFFSET                                                                   0x02bb
>+#define mmSDMA2_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA2_RLC4_CSA_ADDR_LO                                                                       0x02bc
>+#define mmSDMA2_RLC4_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA2_RLC4_CSA_ADDR_HI                                                                       0x02bd
>+#define mmSDMA2_RLC4_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA2_RLC4_IB_SUB_REMAIN                                                                     0x02bf
>+#define mmSDMA2_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA2_RLC4_PREEMPT                                                                           0x02c0
>+#define mmSDMA2_RLC4_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC4_DUMMY_REG                                                                         0x02c1
>+#define mmSDMA2_RLC4_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x02c2
>+#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x02c3
>+#define mmSDMA2_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA2_RLC4_RB_AQL_CNTL                                                                       0x02c4
>+#define mmSDMA2_RLC4_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC4_MINOR_PTR_UPDATE                                                                  0x02c5
>+#define mmSDMA2_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA2_RLC4_MIDCMD_DATA0                                                                      0x02d0
>+#define mmSDMA2_RLC4_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA2_RLC4_MIDCMD_DATA1                                                                      0x02d1
>+#define mmSDMA2_RLC4_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA2_RLC4_MIDCMD_DATA2                                                                      0x02d2
>+#define mmSDMA2_RLC4_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA2_RLC4_MIDCMD_DATA3                                                                      0x02d3
>+#define mmSDMA2_RLC4_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA2_RLC4_MIDCMD_DATA4                                                                      0x02d4
>+#define mmSDMA2_RLC4_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA2_RLC4_MIDCMD_DATA5                                                                      0x02d5
>+#define mmSDMA2_RLC4_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA2_RLC4_MIDCMD_DATA6                                                                      0x02d6
>+#define mmSDMA2_RLC4_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA2_RLC4_MIDCMD_DATA7                                                                      0x02d7
>+#define mmSDMA2_RLC4_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA2_RLC4_MIDCMD_DATA8                                                                      0x02d8
>+#define mmSDMA2_RLC4_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA2_RLC4_MIDCMD_CNTL                                                                       0x02d9
>+#define mmSDMA2_RLC4_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC5_RB_CNTL                                                                           0x02e8
>+#define mmSDMA2_RLC5_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC5_RB_BASE                                                                           0x02e9
>+#define mmSDMA2_RLC5_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC5_RB_BASE_HI                                                                        0x02ea
>+#define mmSDMA2_RLC5_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC5_RB_RPTR                                                                           0x02eb
>+#define mmSDMA2_RLC5_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC5_RB_RPTR_HI                                                                        0x02ec
>+#define mmSDMA2_RLC5_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC5_RB_WPTR                                                                           0x02ed
>+#define mmSDMA2_RLC5_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC5_RB_WPTR_HI                                                                        0x02ee
>+#define mmSDMA2_RLC5_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC5_RB_WPTR_POLL_CNTL                                                                 0x02ef
>+#define mmSDMA2_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA2_RLC5_RB_RPTR_ADDR_HI                                                                   0x02f0
>+#define mmSDMA2_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA2_RLC5_RB_RPTR_ADDR_LO                                                                   0x02f1
>+#define mmSDMA2_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA2_RLC5_IB_CNTL                                                                           0x02f2
>+#define mmSDMA2_RLC5_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC5_IB_RPTR                                                                           0x02f3
>+#define mmSDMA2_RLC5_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC5_IB_OFFSET                                                                         0x02f4
>+#define mmSDMA2_RLC5_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA2_RLC5_IB_BASE_LO                                                                        0x02f5
>+#define mmSDMA2_RLC5_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA2_RLC5_IB_BASE_HI                                                                        0x02f6
>+#define mmSDMA2_RLC5_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC5_IB_SIZE                                                                           0x02f7
>+#define mmSDMA2_RLC5_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC5_SKIP_CNTL                                                                         0x02f8
>+#define mmSDMA2_RLC5_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA2_RLC5_CONTEXT_STATUS                                                                    0x02f9
>+#define mmSDMA2_RLC5_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA2_RLC5_DOORBELL                                                                          0x02fa
>+#define mmSDMA2_RLC5_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA2_RLC5_STATUS                                                                            0x0310
>+#define mmSDMA2_RLC5_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA2_RLC5_DOORBELL_LOG                                                                      0x0311
>+#define mmSDMA2_RLC5_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA2_RLC5_WATERMARK                                                                         0x0312
>+#define mmSDMA2_RLC5_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA2_RLC5_DOORBELL_OFFSET                                                                   0x0313
>+#define mmSDMA2_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA2_RLC5_CSA_ADDR_LO                                                                       0x0314
>+#define mmSDMA2_RLC5_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA2_RLC5_CSA_ADDR_HI                                                                       0x0315
>+#define mmSDMA2_RLC5_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA2_RLC5_IB_SUB_REMAIN                                                                     0x0317
>+#define mmSDMA2_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA2_RLC5_PREEMPT                                                                           0x0318
>+#define mmSDMA2_RLC5_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC5_DUMMY_REG                                                                         0x0319
>+#define mmSDMA2_RLC5_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x031a
>+#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x031b
>+#define mmSDMA2_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA2_RLC5_RB_AQL_CNTL                                                                       0x031c
>+#define mmSDMA2_RLC5_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC5_MINOR_PTR_UPDATE                                                                  0x031d
>+#define mmSDMA2_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA2_RLC5_MIDCMD_DATA0                                                                      0x0328
>+#define mmSDMA2_RLC5_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA2_RLC5_MIDCMD_DATA1                                                                      0x0329
>+#define mmSDMA2_RLC5_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA2_RLC5_MIDCMD_DATA2                                                                      0x032a
>+#define mmSDMA2_RLC5_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA2_RLC5_MIDCMD_DATA3                                                                      0x032b
>+#define mmSDMA2_RLC5_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA2_RLC5_MIDCMD_DATA4                                                                      0x032c
>+#define mmSDMA2_RLC5_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA2_RLC5_MIDCMD_DATA5                                                                      0x032d
>+#define mmSDMA2_RLC5_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA2_RLC5_MIDCMD_DATA6                                                                      0x032e
>+#define mmSDMA2_RLC5_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA2_RLC5_MIDCMD_DATA7                                                                      0x032f
>+#define mmSDMA2_RLC5_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA2_RLC5_MIDCMD_DATA8                                                                      0x0330
>+#define mmSDMA2_RLC5_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA2_RLC5_MIDCMD_CNTL                                                                       0x0331
>+#define mmSDMA2_RLC5_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC6_RB_CNTL                                                                           0x0340
>+#define mmSDMA2_RLC6_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC6_RB_BASE                                                                           0x0341
>+#define mmSDMA2_RLC6_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC6_RB_BASE_HI                                                                        0x0342
>+#define mmSDMA2_RLC6_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC6_RB_RPTR                                                                           0x0343
>+#define mmSDMA2_RLC6_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC6_RB_RPTR_HI                                                                        0x0344
>+#define mmSDMA2_RLC6_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC6_RB_WPTR                                                                           0x0345
>+#define mmSDMA2_RLC6_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC6_RB_WPTR_HI                                                                        0x0346
>+#define mmSDMA2_RLC6_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0347
>+#define mmSDMA2_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA2_RLC6_RB_RPTR_ADDR_HI                                                                   0x0348
>+#define mmSDMA2_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA2_RLC6_RB_RPTR_ADDR_LO                                                                   0x0349
>+#define mmSDMA2_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA2_RLC6_IB_CNTL                                                                           0x034a
>+#define mmSDMA2_RLC6_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC6_IB_RPTR                                                                           0x034b
>+#define mmSDMA2_RLC6_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC6_IB_OFFSET                                                                         0x034c
>+#define mmSDMA2_RLC6_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA2_RLC6_IB_BASE_LO                                                                        0x034d
>+#define mmSDMA2_RLC6_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA2_RLC6_IB_BASE_HI                                                                        0x034e
>+#define mmSDMA2_RLC6_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC6_IB_SIZE                                                                           0x034f
>+#define mmSDMA2_RLC6_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC6_SKIP_CNTL                                                                         0x0350
>+#define mmSDMA2_RLC6_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA2_RLC6_CONTEXT_STATUS                                                                    0x0351
>+#define mmSDMA2_RLC6_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA2_RLC6_DOORBELL                                                                          0x0352
>+#define mmSDMA2_RLC6_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA2_RLC6_STATUS                                                                            0x0368
>+#define mmSDMA2_RLC6_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA2_RLC6_DOORBELL_LOG                                                                      0x0369
>+#define mmSDMA2_RLC6_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA2_RLC6_WATERMARK                                                                         0x036a
>+#define mmSDMA2_RLC6_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA2_RLC6_DOORBELL_OFFSET                                                                   0x036b
>+#define mmSDMA2_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA2_RLC6_CSA_ADDR_LO                                                                       0x036c
>+#define mmSDMA2_RLC6_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA2_RLC6_CSA_ADDR_HI                                                                       0x036d
>+#define mmSDMA2_RLC6_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA2_RLC6_IB_SUB_REMAIN                                                                     0x036f
>+#define mmSDMA2_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA2_RLC6_PREEMPT                                                                           0x0370
>+#define mmSDMA2_RLC6_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC6_DUMMY_REG                                                                         0x0371
>+#define mmSDMA2_RLC6_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x0372
>+#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x0373
>+#define mmSDMA2_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA2_RLC6_RB_AQL_CNTL                                                                       0x0374
>+#define mmSDMA2_RLC6_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC6_MINOR_PTR_UPDATE                                                                  0x0375
>+#define mmSDMA2_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA2_RLC6_MIDCMD_DATA0                                                                      0x0380
>+#define mmSDMA2_RLC6_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA2_RLC6_MIDCMD_DATA1                                                                      0x0381
>+#define mmSDMA2_RLC6_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA2_RLC6_MIDCMD_DATA2                                                                      0x0382
>+#define mmSDMA2_RLC6_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA2_RLC6_MIDCMD_DATA3                                                                      0x0383
>+#define mmSDMA2_RLC6_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA2_RLC6_MIDCMD_DATA4                                                                      0x0384
>+#define mmSDMA2_RLC6_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA2_RLC6_MIDCMD_DATA5                                                                      0x0385
>+#define mmSDMA2_RLC6_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA2_RLC6_MIDCMD_DATA6                                                                      0x0386
>+#define mmSDMA2_RLC6_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA2_RLC6_MIDCMD_DATA7                                                                      0x0387
>+#define mmSDMA2_RLC6_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA2_RLC6_MIDCMD_DATA8                                                                      0x0388
>+#define mmSDMA2_RLC6_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA2_RLC6_MIDCMD_CNTL                                                                       0x0389
>+#define mmSDMA2_RLC6_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC7_RB_CNTL                                                                           0x0398
>+#define mmSDMA2_RLC7_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC7_RB_BASE                                                                           0x0399
>+#define mmSDMA2_RLC7_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC7_RB_BASE_HI                                                                        0x039a
>+#define mmSDMA2_RLC7_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC7_RB_RPTR                                                                           0x039b
>+#define mmSDMA2_RLC7_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC7_RB_RPTR_HI                                                                        0x039c
>+#define mmSDMA2_RLC7_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC7_RB_WPTR                                                                           0x039d
>+#define mmSDMA2_RLC7_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC7_RB_WPTR_HI                                                                        0x039e
>+#define mmSDMA2_RLC7_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC7_RB_WPTR_POLL_CNTL                                                                 0x039f
>+#define mmSDMA2_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA2_RLC7_RB_RPTR_ADDR_HI                                                                   0x03a0
>+#define mmSDMA2_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA2_RLC7_RB_RPTR_ADDR_LO                                                                   0x03a1
>+#define mmSDMA2_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA2_RLC7_IB_CNTL                                                                           0x03a2
>+#define mmSDMA2_RLC7_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC7_IB_RPTR                                                                           0x03a3
>+#define mmSDMA2_RLC7_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC7_IB_OFFSET                                                                         0x03a4
>+#define mmSDMA2_RLC7_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA2_RLC7_IB_BASE_LO                                                                        0x03a5
>+#define mmSDMA2_RLC7_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA2_RLC7_IB_BASE_HI                                                                        0x03a6
>+#define mmSDMA2_RLC7_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA2_RLC7_IB_SIZE                                                                           0x03a7
>+#define mmSDMA2_RLC7_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC7_SKIP_CNTL                                                                         0x03a8
>+#define mmSDMA2_RLC7_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA2_RLC7_CONTEXT_STATUS                                                                    0x03a9
>+#define mmSDMA2_RLC7_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA2_RLC7_DOORBELL                                                                          0x03aa
>+#define mmSDMA2_RLC7_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA2_RLC7_STATUS                                                                            0x03c0
>+#define mmSDMA2_RLC7_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA2_RLC7_DOORBELL_LOG                                                                      0x03c1
>+#define mmSDMA2_RLC7_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA2_RLC7_WATERMARK                                                                         0x03c2
>+#define mmSDMA2_RLC7_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA2_RLC7_DOORBELL_OFFSET                                                                   0x03c3
>+#define mmSDMA2_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA2_RLC7_CSA_ADDR_LO                                                                       0x03c4
>+#define mmSDMA2_RLC7_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA2_RLC7_CSA_ADDR_HI                                                                       0x03c5
>+#define mmSDMA2_RLC7_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA2_RLC7_IB_SUB_REMAIN                                                                     0x03c7
>+#define mmSDMA2_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA2_RLC7_PREEMPT                                                                           0x03c8
>+#define mmSDMA2_RLC7_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA2_RLC7_DUMMY_REG                                                                         0x03c9
>+#define mmSDMA2_RLC7_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x03ca
>+#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x03cb
>+#define mmSDMA2_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA2_RLC7_RB_AQL_CNTL                                                                       0x03cc
>+#define mmSDMA2_RLC7_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA2_RLC7_MINOR_PTR_UPDATE                                                                  0x03cd
>+#define mmSDMA2_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA2_RLC7_MIDCMD_DATA0                                                                      0x03d8
>+#define mmSDMA2_RLC7_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA2_RLC7_MIDCMD_DATA1                                                                      0x03d9
>+#define mmSDMA2_RLC7_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA2_RLC7_MIDCMD_DATA2                                                                      0x03da
>+#define mmSDMA2_RLC7_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA2_RLC7_MIDCMD_DATA3                                                                      0x03db
>+#define mmSDMA2_RLC7_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA2_RLC7_MIDCMD_DATA4                                                                      0x03dc
>+#define mmSDMA2_RLC7_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA2_RLC7_MIDCMD_DATA5                                                                      0x03dd
>+#define mmSDMA2_RLC7_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA2_RLC7_MIDCMD_DATA6                                                                      0x03de
>+#define mmSDMA2_RLC7_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA2_RLC7_MIDCMD_DATA7                                                                      0x03df
>+#define mmSDMA2_RLC7_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA2_RLC7_MIDCMD_DATA8                                                                      0x03e0
>+#define mmSDMA2_RLC7_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA2_RLC7_MIDCMD_CNTL                                                                       0x03e1
>+#define mmSDMA2_RLC7_MIDCMD_CNTL_BASE_IDX                                                              1
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma2/sdma2_4_2_2_sh_mask.h	2019-08-31 15:01:11.932736175 -0500
>@@ -0,0 +1,2956 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma2_4_2_2_SH_MASK_HEADER
>+#define _sdma2_4_2_2_SH_MASK_HEADER
>+
>+
>+// addressBlock: sdma2_sdma2dec
>+//SDMA2_UCODE_ADDR
>+#define SDMA2_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
>+#define SDMA2_UCODE_ADDR__VALUE_MASK                                                                          0x00001FFFL
>+//SDMA2_UCODE_DATA
>+#define SDMA2_UCODE_DATA__VALUE__SHIFT                                                                        0x0
>+#define SDMA2_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
>+//SDMA2_VM_CNTL
>+#define SDMA2_VM_CNTL__CMD__SHIFT                                                                             0x0
>+#define SDMA2_VM_CNTL__CMD_MASK                                                                               0x0000000FL
>+//SDMA2_VM_CTX_LO
>+#define SDMA2_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
>+#define SDMA2_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
>+//SDMA2_VM_CTX_HI
>+#define SDMA2_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
>+#define SDMA2_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
>+//SDMA2_ACTIVE_FCN_ID
>+#define SDMA2_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
>+#define SDMA2_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x4
>+#define SDMA2_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
>+#define SDMA2_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000000FL
>+#define SDMA2_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFF0L
>+#define SDMA2_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
>+//SDMA2_VM_CTX_CNTL
>+#define SDMA2_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
>+#define SDMA2_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
>+#define SDMA2_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
>+#define SDMA2_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
>+//SDMA2_VIRT_RESET_REQ
>+#define SDMA2_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
>+#define SDMA2_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
>+#define SDMA2_VIRT_RESET_REQ__VF_MASK                                                                         0x0000FFFFL
>+#define SDMA2_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
>+//SDMA2_VF_ENABLE
>+#define SDMA2_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
>+#define SDMA2_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
>+//SDMA2_CONTEXT_REG_TYPE0
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_CNTL__SHIFT                                                     0x0
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE__SHIFT                                                     0x1
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_HI__SHIFT                                                  0x2
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR__SHIFT                                                     0x3
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_HI__SHIFT                                                  0x4
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR__SHIFT                                                     0x5
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_HI__SHIFT                                                  0x6
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL__SHIFT                                                     0xa
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_RPTR__SHIFT                                                     0xb
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_OFFSET__SHIFT                                                   0xc
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_LO__SHIFT                                                  0xd
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_HI__SHIFT                                                  0xe
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_SIZE__SHIFT                                                     0xf
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_SKIP_CNTL__SHIFT                                                   0x10
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_STATUS__SHIFT                                              0x11
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_DOORBELL__SHIFT                                                    0x12
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_CNTL__SHIFT                                                0x13
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_CNTL_MASK                                                       0x00000001L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_MASK                                                       0x00000002L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_HI_MASK                                                    0x00000004L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_MASK                                                       0x00000008L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_MASK                                                       0x00000020L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL_MASK                                                       0x00000400L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_RPTR_MASK                                                       0x00000800L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_OFFSET_MASK                                                     0x00001000L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_LO_MASK                                                    0x00002000L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_HI_MASK                                                    0x00004000L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_SIZE_MASK                                                       0x00008000L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_SKIP_CNTL_MASK                                                     0x00010000L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_DOORBELL_MASK                                                      0x00040000L
>+#define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
>+//SDMA2_CONTEXT_REG_TYPE1
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_STATUS__SHIFT                                                      0x8
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_LOG__SHIFT                                                0x9
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK__SHIFT                                                   0xa
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
>+#define SDMA2_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_PREEMPT__SHIFT                                                     0x10
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DUMMY_REG__SHIFT                                                   0x11
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
>+#define SDMA2_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x16
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_STATUS_MASK                                                        0x00000100L
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK_MASK                                                     0x00000400L
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
>+#define SDMA2_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_PREEMPT_MASK                                                       0x00010000L
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DUMMY_REG_MASK                                                     0x00020000L
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
>+#define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
>+#define SDMA2_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFFC00000L
>+//SDMA2_CONTEXT_REG_TYPE2
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA0__SHIFT                                                0x0
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA1__SHIFT                                                0x1
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA2__SHIFT                                                0x2
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA3__SHIFT                                                0x3
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA4__SHIFT                                                0x4
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA5__SHIFT                                                0x5
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA6__SHIFT                                                0x6
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA7__SHIFT                                                0x7
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA8__SHIFT                                                0x8
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_CNTL__SHIFT                                                 0x9
>+#define SDMA2_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
>+#define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_CNTL_MASK                                                   0x00000200L
>+#define SDMA2_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFFC00L
>+//SDMA2_CONTEXT_REG_TYPE3
>+#define SDMA2_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
>+#define SDMA2_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
>+//SDMA2_PUB_REG_TYPE0
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR__SHIFT                                                          0x0
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA__SHIFT                                                          0x1
>+#define SDMA2_PUB_REG_TYPE0__RESERVED3__SHIFT                                                                 0x3
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CNTL__SHIFT                                                             0x4
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_LO__SHIFT                                                           0x5
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_HI__SHIFT                                                           0x6
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_ACTIVE_FCN_ID__SHIFT                                                       0x7
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_CNTL__SHIFT                                                         0x8
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_VIRT_RESET_REQ__SHIFT                                                      0x9
>+#define SDMA2_PUB_REG_TYPE0__RESERVED10__SHIFT                                                                0xa
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE0__SHIFT                                                   0xb
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE1__SHIFT                                                   0xc
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE2__SHIFT                                                   0xd
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE3__SHIFT                                                   0xe
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE0__SHIFT                                                       0xf
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE1__SHIFT                                                       0x10
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE2__SHIFT                                                       0x11
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE3__SHIFT                                                       0x12
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_MMHUB_CNTL__SHIFT                                                          0x13
>+#define SDMA2_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x15
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_GROUP_BOUNDARY__SHIFT                                              0x19
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_POWER_CNTL__SHIFT                                                          0x1a
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CLK_CTRL__SHIFT                                                            0x1b
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CNTL__SHIFT                                                                0x1c
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS__SHIFT                                                        0x1d
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG__SHIFT                                                      0x1e
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR_MASK                                                            0x00000001L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA_MASK                                                            0x00000002L
>+#define SDMA2_PUB_REG_TYPE0__RESERVED3_MASK                                                                   0x00000008L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CNTL_MASK                                                               0x00000010L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_LO_MASK                                                             0x00000020L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_HI_MASK                                                             0x00000040L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_ACTIVE_FCN_ID_MASK                                                         0x00000080L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_CNTL_MASK                                                           0x00000100L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_VIRT_RESET_REQ_MASK                                                        0x00000200L
>+#define SDMA2_PUB_REG_TYPE0__RESERVED10_MASK                                                                  0x00000400L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE0_MASK                                                     0x00000800L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE1_MASK                                                     0x00001000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE2_MASK                                                     0x00002000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE3_MASK                                                     0x00004000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE0_MASK                                                         0x00008000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE1_MASK                                                         0x00010000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE2_MASK                                                         0x00020000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE3_MASK                                                         0x00040000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_MMHUB_CNTL_MASK                                                            0x00080000L
>+#define SDMA2_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x01E00000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_GROUP_BOUNDARY_MASK                                                0x02000000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_POWER_CNTL_MASK                                                            0x04000000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CLK_CTRL_MASK                                                              0x08000000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CNTL_MASK                                                                  0x10000000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS_MASK                                                          0x20000000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_MASK                                                        0x40000000L
>+#define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
>+//SDMA2_PUB_REG_TYPE1
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH__SHIFT                                                       0x2
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_IB_OFFSET_FETCH__SHIFT                                                     0x3
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_PROGRAM__SHIFT                                                             0x4
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS_REG__SHIFT                                                          0x5
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS1_REG__SHIFT                                                         0x6
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_RD_BURST_CNTL__SHIFT                                                       0x7
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_HBM_PAGE_CONFIG__SHIFT                                                     0x8
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_UCODE_CHECKSUM__SHIFT                                                      0x9
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL__SHIFT                                                            0xa
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_FREEZE__SHIFT                                                              0xb
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE0_QUANTUM__SHIFT                                                      0xc
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE1_QUANTUM__SHIFT                                                      0xd
>+#define SDMA2_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT                                                         0xe
>+#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT                                                         0xf
>+#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT                                                          0x10
>+#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT                                                           0x11
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_CONFIG__SHIFT                                                          0x12
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_BA_THRESHOLD__SHIFT                                                        0x13
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_ID__SHIFT                                                                  0x14
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_VERSION__SHIFT                                                             0x15
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER__SHIFT                                                         0x16
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS2_REG__SHIFT                                                         0x18
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_CNTL__SHIFT                                                         0x19
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_CNTL__SHIFT                                                          0x1c
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK__SHIFT                                                       0x1d
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_RD_STATUS__SHIFT                                                     0x1e
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WR_STATUS__SHIFT                                                     0x1f
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_MASK                                                         0x00000004L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_IB_OFFSET_FETCH_MASK                                                       0x00000008L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_PROGRAM_MASK                                                               0x00000010L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS_REG_MASK                                                            0x00000020L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS1_REG_MASK                                                           0x00000040L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_RD_BURST_CNTL_MASK                                                         0x00000080L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_UCODE_CHECKSUM_MASK                                                        0x00000200L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL_MASK                                                              0x00000400L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_FREEZE_MASK                                                                0x00000800L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE0_QUANTUM_MASK                                                        0x00001000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE1_QUANTUM_MASK                                                        0x00002000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK                                                           0x00004000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK                                                           0x00008000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK                                                            0x00010000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK                                                             0x00020000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_CONFIG_MASK                                                            0x00040000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_BA_THRESHOLD_MASK                                                          0x00080000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_ID_MASK                                                                    0x00100000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_VERSION_MASK                                                               0x00200000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_MASK                                                           0x00400000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS2_REG_MASK                                                           0x01000000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_CNTL_MASK                                                           0x02000000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_CNTL_MASK                                                            0x10000000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK_MASK                                                         0x20000000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_RD_STATUS_MASK                                                       0x40000000L
>+#define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WR_STATUS_MASK                                                       0x80000000L
>+//SDMA2_PUB_REG_TYPE2
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV0__SHIFT                                                          0x0
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV1__SHIFT                                                          0x1
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV2__SHIFT                                                          0x2
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK0__SHIFT                                                     0x3
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK1__SHIFT                                                     0x4
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK0__SHIFT                                                     0x5
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK1__SHIFT                                                     0x6
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_TIMEOUT__SHIFT                                                       0x7
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_PAGE__SHIFT                                                          0x8
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_POWER_CNTL_IDLE__SHIFT                                                     0x9
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT__SHIFT                                                  0xa
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_CHICKEN_BITS_2__SHIFT                                                      0xb
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_STATUS3_REG__SHIFT                                                         0xc
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PHASE2_QUANTUM__SHIFT                                                      0xf
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_ERROR_LOG__SHIFT                                                           0x10
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG0__SHIFT                                                      0x11
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG1__SHIFT                                                      0x12
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG2__SHIFT                                                      0x13
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG3__SHIFT                                                      0x14
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_F32_COUNTER__SHIFT                                                         0x15
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UNBREAKABLE__SHIFT                                                         0x16
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFMON_CNTL__SHIFT                                                        0x17
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER0_RESULT__SHIFT                                                 0x18
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER1_RESULT__SHIFT                                                 0x19
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT                                         0x1a
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_CRD_CNTL__SHIFT                                                            0x1b
>+#define SDMA2_PUB_REG_TYPE2__RESERVED28__SHIFT                                                                0x1c
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_GPU_IOV_VIOLATION_LOG__SHIFT                                               0x1d
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_ULV_CNTL__SHIFT                                                            0x1e
>+#define SDMA2_PUB_REG_TYPE2__RESERVED__SHIFT                                                                  0x1f
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV0_MASK                                                            0x00000001L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV1_MASK                                                            0x00000002L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV2_MASK                                                            0x00000004L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_TIMEOUT_MASK                                                         0x00000080L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_PAGE_MASK                                                            0x00000100L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_POWER_CNTL_IDLE_MASK                                                       0x00000200L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_CHICKEN_BITS_2_MASK                                                        0x00000800L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_STATUS3_REG_MASK                                                           0x00001000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PHASE2_QUANTUM_MASK                                                        0x00008000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_ERROR_LOG_MASK                                                             0x00010000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG0_MASK                                                        0x00020000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG1_MASK                                                        0x00040000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG2_MASK                                                        0x00080000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG3_MASK                                                        0x00100000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_F32_COUNTER_MASK                                                           0x00200000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_UNBREAKABLE_MASK                                                           0x00400000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFMON_CNTL_MASK                                                          0x00800000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER0_RESULT_MASK                                                   0x01000000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER1_RESULT_MASK                                                   0x02000000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCOUNTER_TAG_DELAY_RANGE_MASK                                           0x04000000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_CRD_CNTL_MASK                                                              0x08000000L
>+#define SDMA2_PUB_REG_TYPE2__RESERVED28_MASK                                                                  0x10000000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_GPU_IOV_VIOLATION_LOG_MASK                                                 0x20000000L
>+#define SDMA2_PUB_REG_TYPE2__SDMA2_ULV_CNTL_MASK                                                              0x40000000L
>+#define SDMA2_PUB_REG_TYPE2__RESERVED_MASK                                                                    0x80000000L
>+//SDMA2_PUB_REG_TYPE3
>+#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
>+#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
>+#define SDMA2_PUB_REG_TYPE3__SDMA2_GPU_IOV_VIOLATION_LOG2__SHIFT                                              0x2
>+#define SDMA2_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x3
>+#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
>+#define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
>+#define SDMA2_PUB_REG_TYPE3__SDMA2_GPU_IOV_VIOLATION_LOG2_MASK                                                0x00000004L
>+#define SDMA2_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xFFFFFFF8L
>+//SDMA2_MMHUB_CNTL
>+#define SDMA2_MMHUB_CNTL__UNIT_ID__SHIFT                                                                      0x0
>+#define SDMA2_MMHUB_CNTL__UNIT_ID_MASK                                                                        0x0000003FL
>+//SDMA2_CONTEXT_GROUP_BOUNDARY
>+#define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT                                                         0x0
>+#define SDMA2_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK                                                           0xFFFFFFFFL
>+//SDMA2_POWER_CNTL
>+#define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
>+#define SDMA2_POWER_CNTL__MEM_POWER_LS_EN__SHIFT                                                              0x9
>+#define SDMA2_POWER_CNTL__MEM_POWER_DS_EN__SHIFT                                                              0xa
>+#define SDMA2_POWER_CNTL__MEM_POWER_SD_EN__SHIFT                                                              0xb
>+#define SDMA2_POWER_CNTL__MEM_POWER_DELAY__SHIFT                                                              0xc
>+#define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
>+#define SDMA2_POWER_CNTL__MEM_POWER_LS_EN_MASK                                                                0x00000200L
>+#define SDMA2_POWER_CNTL__MEM_POWER_DS_EN_MASK                                                                0x00000400L
>+#define SDMA2_POWER_CNTL__MEM_POWER_SD_EN_MASK                                                                0x00000800L
>+#define SDMA2_POWER_CNTL__MEM_POWER_DELAY_MASK                                                                0x003FF000L
>+//SDMA2_CLK_CTRL
>+#define SDMA2_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
>+#define SDMA2_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
>+#define SDMA2_CLK_CTRL__RESERVED__SHIFT                                                                       0xc
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                                 0x18
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                                 0x19
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                                 0x1a
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1b
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1c
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1d
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1e
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1f
>+#define SDMA2_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
>+#define SDMA2_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
>+#define SDMA2_CLK_CTRL__RESERVED_MASK                                                                         0x00FFF000L
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                   0x01000000L
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                   0x02000000L
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                   0x04000000L
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x08000000L
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x10000000L
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x20000000L
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x40000000L
>+#define SDMA2_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x80000000L
>+//SDMA2_CNTL
>+#define SDMA2_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
>+#define SDMA2_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
>+#define SDMA2_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
>+#define SDMA2_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
>+#define SDMA2_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
>+#define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
>+#define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
>+#define SDMA2_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
>+#define SDMA2_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
>+#define SDMA2_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
>+#define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
>+#define SDMA2_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
>+#define SDMA2_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
>+#define SDMA2_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
>+#define SDMA2_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
>+#define SDMA2_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
>+#define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
>+#define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
>+#define SDMA2_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
>+#define SDMA2_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
>+#define SDMA2_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
>+#define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
>+//SDMA2_CHICKEN_BITS
>+#define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
>+#define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
>+#define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
>+#define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
>+#define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
>+#define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
>+#define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
>+#define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
>+#define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
>+#define SDMA2_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
>+#define SDMA2_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
>+#define SDMA2_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
>+#define SDMA2_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
>+#define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
>+#define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
>+#define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
>+#define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
>+#define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
>+#define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
>+#define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
>+#define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
>+#define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
>+#define SDMA2_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
>+#define SDMA2_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
>+#define SDMA2_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
>+#define SDMA2_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
>+//SDMA2_GB_ADDR_CONFIG
>+#define SDMA2_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
>+#define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
>+#define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
>+#define SDMA2_GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
>+#define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
>+#define SDMA2_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
>+#define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
>+#define SDMA2_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
>+#define SDMA2_GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
>+#define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
>+//SDMA2_GB_ADDR_CONFIG_READ
>+#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
>+#define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
>+#define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                0x8
>+#define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                           0xc
>+#define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
>+#define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
>+#define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
>+#define SDMA2_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                  0x00000700L
>+#define SDMA2_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                             0x00007000L
>+#define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
>+//SDMA2_RB_RPTR_FETCH_HI
>+#define SDMA2_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
>+#define SDMA2_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_SEM_WAIT_FAIL_TIMER_CNTL
>+#define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
>+#define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
>+//SDMA2_RB_RPTR_FETCH
>+#define SDMA2_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
>+#define SDMA2_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
>+//SDMA2_IB_OFFSET_FETCH
>+#define SDMA2_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
>+#define SDMA2_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
>+//SDMA2_PROGRAM
>+#define SDMA2_PROGRAM__STREAM__SHIFT                                                                          0x0
>+#define SDMA2_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
>+//SDMA2_STATUS_REG
>+#define SDMA2_STATUS_REG__IDLE__SHIFT                                                                         0x0
>+#define SDMA2_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
>+#define SDMA2_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
>+#define SDMA2_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
>+#define SDMA2_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
>+#define SDMA2_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
>+#define SDMA2_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
>+#define SDMA2_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
>+#define SDMA2_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
>+#define SDMA2_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
>+#define SDMA2_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
>+#define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
>+#define SDMA2_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
>+#define SDMA2_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
>+#define SDMA2_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
>+#define SDMA2_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
>+#define SDMA2_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
>+#define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
>+#define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
>+#define SDMA2_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
>+#define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
>+#define SDMA2_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
>+#define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
>+#define SDMA2_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
>+#define SDMA2_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
>+#define SDMA2_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
>+#define SDMA2_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
>+#define SDMA2_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
>+#define SDMA2_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
>+#define SDMA2_STATUS_REG__IDLE_MASK                                                                           0x00000001L
>+#define SDMA2_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
>+#define SDMA2_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
>+#define SDMA2_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
>+#define SDMA2_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
>+#define SDMA2_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
>+#define SDMA2_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
>+#define SDMA2_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
>+#define SDMA2_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
>+#define SDMA2_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
>+#define SDMA2_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
>+#define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
>+#define SDMA2_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
>+#define SDMA2_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
>+#define SDMA2_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
>+#define SDMA2_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
>+#define SDMA2_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
>+#define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
>+#define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
>+#define SDMA2_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
>+#define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
>+#define SDMA2_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
>+#define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
>+#define SDMA2_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
>+#define SDMA2_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
>+#define SDMA2_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
>+#define SDMA2_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
>+#define SDMA2_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
>+#define SDMA2_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
>+//SDMA2_STATUS1_REG
>+#define SDMA2_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
>+#define SDMA2_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
>+#define SDMA2_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
>+#define SDMA2_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
>+#define SDMA2_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
>+#define SDMA2_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
>+#define SDMA2_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
>+#define SDMA2_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
>+#define SDMA2_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
>+#define SDMA2_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
>+#define SDMA2_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
>+#define SDMA2_STATUS1_REG__EX_START__SHIFT                                                                    0xf
>+#define SDMA2_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
>+#define SDMA2_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
>+#define SDMA2_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
>+#define SDMA2_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
>+#define SDMA2_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
>+#define SDMA2_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
>+#define SDMA2_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
>+#define SDMA2_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
>+#define SDMA2_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
>+#define SDMA2_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
>+#define SDMA2_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
>+#define SDMA2_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
>+#define SDMA2_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
>+#define SDMA2_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
>+#define SDMA2_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
>+#define SDMA2_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
>+//SDMA2_RD_BURST_CNTL
>+#define SDMA2_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
>+#define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT                                                       0x2
>+#define SDMA2_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
>+#define SDMA2_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK                                                         0x0000000CL
>+//SDMA2_HBM_PAGE_CONFIG
>+#define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
>+#define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000001L
>+//SDMA2_UCODE_CHECKSUM
>+#define SDMA2_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
>+#define SDMA2_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_F32_CNTL
>+#define SDMA2_F32_CNTL__HALT__SHIFT                                                                           0x0
>+#define SDMA2_F32_CNTL__STEP__SHIFT                                                                           0x1
>+#define SDMA2_F32_CNTL__HALT_MASK                                                                             0x00000001L
>+#define SDMA2_F32_CNTL__STEP_MASK                                                                             0x00000002L
>+//SDMA2_FREEZE
>+#define SDMA2_FREEZE__PREEMPT__SHIFT                                                                          0x0
>+#define SDMA2_FREEZE__FREEZE__SHIFT                                                                           0x4
>+#define SDMA2_FREEZE__FROZEN__SHIFT                                                                           0x5
>+#define SDMA2_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
>+#define SDMA2_FREEZE__PREEMPT_MASK                                                                            0x00000001L
>+#define SDMA2_FREEZE__FREEZE_MASK                                                                             0x00000010L
>+#define SDMA2_FREEZE__FROZEN_MASK                                                                             0x00000020L
>+#define SDMA2_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
>+//SDMA2_PHASE0_QUANTUM
>+#define SDMA2_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA2_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA2_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA2_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA2_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA2_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA2_PHASE1_QUANTUM
>+#define SDMA2_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA2_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA2_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA2_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA2_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA2_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA2_EDC_CONFIG
>+#define SDMA2_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
>+#define SDMA2_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
>+#define SDMA2_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
>+#define SDMA2_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
>+//SDMA2_BA_THRESHOLD
>+#define SDMA2_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
>+#define SDMA2_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
>+#define SDMA2_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
>+#define SDMA2_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
>+//SDMA2_ID
>+#define SDMA2_ID__DEVICE_ID__SHIFT                                                                            0x0
>+#define SDMA2_ID__DEVICE_ID_MASK                                                                              0x000000FFL
>+//SDMA2_VERSION
>+#define SDMA2_VERSION__MINVER__SHIFT                                                                          0x0
>+#define SDMA2_VERSION__MAJVER__SHIFT                                                                          0x8
>+#define SDMA2_VERSION__REV__SHIFT                                                                             0x10
>+#define SDMA2_VERSION__MINVER_MASK                                                                            0x0000007FL
>+#define SDMA2_VERSION__MAJVER_MASK                                                                            0x00007F00L
>+#define SDMA2_VERSION__REV_MASK                                                                               0x003F0000L
>+//SDMA2_EDC_COUNTER
>+#define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT                                                          0x0
>+#define SDMA2_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
>+#define SDMA2_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
>+#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
>+#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
>+#define SDMA2_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT                                                    0xf
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT                                                    0x10
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT                                                   0x11
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT                                                   0x12
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT                                                   0x13
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT                                                   0x14
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT                                                   0x15
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT                                                   0x16
>+#define SDMA2_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0x17
>+#define SDMA2_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x18
>+#define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK                                                            0x00000001L
>+#define SDMA2_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
>+#define SDMA2_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
>+#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
>+#define SDMA2_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
>+#define SDMA2_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK                                                      0x00008000L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK                                                      0x00010000L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK                                                     0x00020000L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK                                                     0x00040000L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK                                                     0x00080000L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK                                                     0x00100000L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK                                                     0x00200000L
>+#define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK                                                     0x00400000L
>+#define SDMA2_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00800000L
>+#define SDMA2_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x01000000L
>+//SDMA2_EDC_COUNTER_CLEAR
>+#define SDMA2_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
>+#define SDMA2_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
>+//SDMA2_STATUS2_REG
>+#define SDMA2_STATUS2_REG__ID__SHIFT                                                                          0x0
>+#define SDMA2_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x3
>+#define SDMA2_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
>+#define SDMA2_STATUS2_REG__ID_MASK                                                                            0x00000007L
>+#define SDMA2_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFF8L
>+#define SDMA2_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
>+//SDMA2_ATOMIC_CNTL
>+#define SDMA2_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
>+#define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
>+#define SDMA2_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
>+#define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
>+//SDMA2_ATOMIC_PREOP_LO
>+#define SDMA2_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
>+#define SDMA2_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_ATOMIC_PREOP_HI
>+#define SDMA2_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
>+#define SDMA2_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_UTCL1_CNTL
>+#define SDMA2_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
>+#define SDMA2_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0xb
>+#define SDMA2_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0xe
>+#define SDMA2_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
>+#define SDMA2_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
>+#define SDMA2_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x000007FEL
>+#define SDMA2_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x00003800L
>+#define SDMA2_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FFC000L
>+#define SDMA2_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
>+#define SDMA2_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
>+//SDMA2_UTCL1_WATERMK
>+#define SDMA2_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
>+#define SDMA2_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0x9
>+#define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x11
>+#define SDMA2_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x19
>+#define SDMA2_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000001FFL
>+#define SDMA2_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0001FE00L
>+#define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x01FE0000L
>+#define SDMA2_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFE000000L
>+//SDMA2_UTCL1_RD_STATUS
>+#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT                                                             0x15
>+#define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x16
>+#define SDMA2_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x1a
>+#define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x1d
>+#define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT                                                            0x1e
>+#define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT                                                             0x1f
>+#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA2_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA2_UTCL1_RD_STATUS__CE_L1_STALL_MASK                                                               0x00200000L
>+#define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x03C00000L
>+#define SDMA2_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x1C000000L
>+#define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x20000000L
>+#define SDMA2_UTCL1_RD_STATUS__WPTR_POLLING_MASK                                                              0x40000000L
>+#define SDMA2_UTCL1_RD_STATUS__INVREQ_SIZE_MASK                                                               0x80000000L
>+//SDMA2_UTCL1_WR_STATUS
>+#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15
>+#define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x16
>+#define SDMA2_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19
>+#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
>+#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
>+#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
>+#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
>+#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA2_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x00200000L
>+#define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x01C00000L
>+#define SDMA2_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x0E000000L
>+#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
>+#define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
>+#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
>+#define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
>+//SDMA2_UTCL1_INV0
>+#define SDMA2_UTCL1_INV0__INV_MIDDLE__SHIFT                                                                   0x0
>+#define SDMA2_UTCL1_INV0__RD_TIMEOUT__SHIFT                                                                   0x1
>+#define SDMA2_UTCL1_INV0__WR_TIMEOUT__SHIFT                                                                   0x2
>+#define SDMA2_UTCL1_INV0__RD_IN_INVADR__SHIFT                                                                 0x3
>+#define SDMA2_UTCL1_INV0__WR_IN_INVADR__SHIFT                                                                 0x4
>+#define SDMA2_UTCL1_INV0__PAGE_NULL_SW__SHIFT                                                                 0x5
>+#define SDMA2_UTCL1_INV0__XNACK_IS_INVADR__SHIFT                                                              0x6
>+#define SDMA2_UTCL1_INV0__INVREQ_ENABLE__SHIFT                                                                0x7
>+#define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT                                                              0x8
>+#define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT                                                              0x9
>+#define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT                                                               0xa
>+#define SDMA2_UTCL1_INV0__INV_FLUSHTYPE__SHIFT                                                                0xb
>+#define SDMA2_UTCL1_INV0__INV_VMID_VEC__SHIFT                                                                 0xc
>+#define SDMA2_UTCL1_INV0__INV_ADDR_HI__SHIFT                                                                  0x1c
>+#define SDMA2_UTCL1_INV0__INV_MIDDLE_MASK                                                                     0x00000001L
>+#define SDMA2_UTCL1_INV0__RD_TIMEOUT_MASK                                                                     0x00000002L
>+#define SDMA2_UTCL1_INV0__WR_TIMEOUT_MASK                                                                     0x00000004L
>+#define SDMA2_UTCL1_INV0__RD_IN_INVADR_MASK                                                                   0x00000008L
>+#define SDMA2_UTCL1_INV0__WR_IN_INVADR_MASK                                                                   0x00000010L
>+#define SDMA2_UTCL1_INV0__PAGE_NULL_SW_MASK                                                                   0x00000020L
>+#define SDMA2_UTCL1_INV0__XNACK_IS_INVADR_MASK                                                                0x00000040L
>+#define SDMA2_UTCL1_INV0__INVREQ_ENABLE_MASK                                                                  0x00000080L
>+#define SDMA2_UTCL1_INV0__NACK_TIMEOUT_SW_MASK                                                                0x00000100L
>+#define SDMA2_UTCL1_INV0__NFLUSH_INV_IDLE_MASK                                                                0x00000200L
>+#define SDMA2_UTCL1_INV0__FLUSH_INV_IDLE_MASK                                                                 0x00000400L
>+#define SDMA2_UTCL1_INV0__INV_FLUSHTYPE_MASK                                                                  0x00000800L
>+#define SDMA2_UTCL1_INV0__INV_VMID_VEC_MASK                                                                   0x0FFFF000L
>+#define SDMA2_UTCL1_INV0__INV_ADDR_HI_MASK                                                                    0xF0000000L
>+//SDMA2_UTCL1_INV1
>+#define SDMA2_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
>+#define SDMA2_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_UTCL1_INV2
>+#define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT                                                          0x0
>+#define SDMA2_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK                                                            0xFFFFFFFFL
>+//SDMA2_UTCL1_RD_XNACK0
>+#define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA2_UTCL1_RD_XNACK1
>+#define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA2_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA2_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA2_UTCL1_WR_XNACK0
>+#define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA2_UTCL1_WR_XNACK1
>+#define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA2_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA2_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA2_UTCL1_TIMEOUT
>+#define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
>+#define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
>+#define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
>+#define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
>+//SDMA2_UTCL1_PAGE
>+#define SDMA2_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
>+#define SDMA2_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
>+#define SDMA2_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
>+#define SDMA2_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0x9
>+#define SDMA2_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
>+#define SDMA2_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
>+#define SDMA2_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000001C0L
>+#define SDMA2_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000200L
>+//SDMA2_POWER_CNTL_IDLE
>+#define SDMA2_POWER_CNTL_IDLE__DELAY0__SHIFT                                                                  0x0
>+#define SDMA2_POWER_CNTL_IDLE__DELAY1__SHIFT                                                                  0x10
>+#define SDMA2_POWER_CNTL_IDLE__DELAY2__SHIFT                                                                  0x18
>+#define SDMA2_POWER_CNTL_IDLE__DELAY0_MASK                                                                    0x0000FFFFL
>+#define SDMA2_POWER_CNTL_IDLE__DELAY1_MASK                                                                    0x00FF0000L
>+#define SDMA2_POWER_CNTL_IDLE__DELAY2_MASK                                                                    0xFF000000L
>+//SDMA2_RELAX_ORDERING_LUT
>+#define SDMA2_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
>+#define SDMA2_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
>+#define SDMA2_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
>+#define SDMA2_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
>+#define SDMA2_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
>+#define SDMA2_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
>+#define SDMA2_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
>+#define SDMA2_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
>+#define SDMA2_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
>+#define SDMA2_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
>+#define SDMA2_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
>+#define SDMA2_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
>+#define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
>+#define SDMA2_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
>+#define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
>+#define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
>+#define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
>+#define SDMA2_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
>+#define SDMA2_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
>+#define SDMA2_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
>+#define SDMA2_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
>+#define SDMA2_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
>+#define SDMA2_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
>+#define SDMA2_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
>+#define SDMA2_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
>+#define SDMA2_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
>+#define SDMA2_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
>+#define SDMA2_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
>+#define SDMA2_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
>+#define SDMA2_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
>+#define SDMA2_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
>+#define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
>+#define SDMA2_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
>+#define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
>+#define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
>+#define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
>+#define SDMA2_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
>+#define SDMA2_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
>+//SDMA2_CHICKEN_BITS_2
>+#define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
>+#define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
>+//SDMA2_STATUS3_REG
>+#define SDMA2_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
>+#define SDMA2_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
>+#define SDMA2_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
>+#define SDMA2_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x15
>+#define SDMA2_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x16
>+#define SDMA2_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
>+#define SDMA2_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
>+#define SDMA2_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
>+#define SDMA2_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x00200000L
>+#define SDMA2_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x03C00000L
>+//SDMA2_PHYSICAL_ADDR_LO
>+#define SDMA2_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
>+#define SDMA2_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
>+#define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
>+#define SDMA2_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
>+#define SDMA2_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
>+#define SDMA2_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
>+#define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
>+#define SDMA2_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
>+//SDMA2_PHYSICAL_ADDR_HI
>+#define SDMA2_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA2_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
>+//SDMA2_PHASE2_QUANTUM
>+#define SDMA2_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA2_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA2_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA2_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA2_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA2_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA2_ERROR_LOG
>+#define SDMA2_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
>+#define SDMA2_ERROR_LOG__STATUS__SHIFT                                                                        0x10
>+#define SDMA2_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
>+#define SDMA2_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
>+//SDMA2_PUB_DUMMY_REG0
>+#define SDMA2_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
>+#define SDMA2_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_PUB_DUMMY_REG1
>+#define SDMA2_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
>+#define SDMA2_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_PUB_DUMMY_REG2
>+#define SDMA2_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
>+#define SDMA2_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_PUB_DUMMY_REG3
>+#define SDMA2_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
>+#define SDMA2_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_F32_COUNTER
>+#define SDMA2_F32_COUNTER__VALUE__SHIFT                                                                       0x0
>+#define SDMA2_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
>+//SDMA2_UNBREAKABLE
>+#define SDMA2_UNBREAKABLE__VALUE__SHIFT                                                                       0x0
>+#define SDMA2_UNBREAKABLE__VALUE_MASK                                                                         0x00000001L
>+//SDMA2_PERFMON_CNTL
>+#define SDMA2_PERFMON_CNTL__PERF_ENABLE0__SHIFT                                                               0x0
>+#define SDMA2_PERFMON_CNTL__PERF_CLEAR0__SHIFT                                                                0x1
>+#define SDMA2_PERFMON_CNTL__PERF_SEL0__SHIFT                                                                  0x2
>+#define SDMA2_PERFMON_CNTL__PERF_ENABLE1__SHIFT                                                               0xa
>+#define SDMA2_PERFMON_CNTL__PERF_CLEAR1__SHIFT                                                                0xb
>+#define SDMA2_PERFMON_CNTL__PERF_SEL1__SHIFT                                                                  0xc
>+#define SDMA2_PERFMON_CNTL__PERF_ENABLE0_MASK                                                                 0x00000001L
>+#define SDMA2_PERFMON_CNTL__PERF_CLEAR0_MASK                                                                  0x00000002L
>+#define SDMA2_PERFMON_CNTL__PERF_SEL0_MASK                                                                    0x000003FCL
>+#define SDMA2_PERFMON_CNTL__PERF_ENABLE1_MASK                                                                 0x00000400L
>+#define SDMA2_PERFMON_CNTL__PERF_CLEAR1_MASK                                                                  0x00000800L
>+#define SDMA2_PERFMON_CNTL__PERF_SEL1_MASK                                                                    0x000FF000L
>+//SDMA2_PERFCOUNTER0_RESULT
>+#define SDMA2_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA2_PERFCOUNTER0_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA2_PERFCOUNTER1_RESULT
>+#define SDMA2_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA2_PERFCOUNTER1_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA2_PERFCOUNTER_TAG_DELAY_RANGE
>+#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT                                                   0x0
>+#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT                                                  0xe
>+#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT                                                   0x1c
>+#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK                                                     0x00003FFFL
>+#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK                                                    0x0FFFC000L
>+#define SDMA2_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK                                                     0x10000000L
>+//SDMA2_CRD_CNTL
>+#define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
>+#define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
>+#define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
>+#define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
>+//SDMA2_GPU_IOV_VIOLATION_LOG
>+#define SDMA2_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT                                                  0x0
>+#define SDMA2_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT                                         0x1
>+#define SDMA2_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT                                                           0x2
>+#define SDMA2_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT                                                   0x14
>+#define SDMA2_GPU_IOV_VIOLATION_LOG__VF__SHIFT                                                                0x15
>+#define SDMA2_GPU_IOV_VIOLATION_LOG__VFID__SHIFT                                                              0x16
>+#define SDMA2_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK                                                    0x00000001L
>+#define SDMA2_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK                                           0x00000002L
>+#define SDMA2_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK                                                             0x000FFFFCL
>+#define SDMA2_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK                                                     0x00100000L
>+#define SDMA2_GPU_IOV_VIOLATION_LOG__VF_MASK                                                                  0x00200000L
>+#define SDMA2_GPU_IOV_VIOLATION_LOG__VFID_MASK                                                                0x03C00000L
>+//SDMA2_ULV_CNTL
>+#define SDMA2_ULV_CNTL__HYSTERESIS__SHIFT                                                                     0x0
>+#define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT                                                              0x1b
>+#define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT                                                               0x1c
>+#define SDMA2_ULV_CNTL__ENTER_ULV_INT__SHIFT                                                                  0x1d
>+#define SDMA2_ULV_CNTL__EXIT_ULV_INT__SHIFT                                                                   0x1e
>+#define SDMA2_ULV_CNTL__ULV_STATUS__SHIFT                                                                     0x1f
>+#define SDMA2_ULV_CNTL__HYSTERESIS_MASK                                                                       0x0000001FL
>+#define SDMA2_ULV_CNTL__ENTER_ULV_INT_CLR_MASK                                                                0x08000000L
>+#define SDMA2_ULV_CNTL__EXIT_ULV_INT_CLR_MASK                                                                 0x10000000L
>+#define SDMA2_ULV_CNTL__ENTER_ULV_INT_MASK                                                                    0x20000000L
>+#define SDMA2_ULV_CNTL__EXIT_ULV_INT_MASK                                                                     0x40000000L
>+#define SDMA2_ULV_CNTL__ULV_STATUS_MASK                                                                       0x80000000L
>+//SDMA2_EA_DBIT_ADDR_DATA
>+#define SDMA2_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
>+#define SDMA2_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_EA_DBIT_ADDR_INDEX
>+#define SDMA2_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
>+#define SDMA2_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
>+//SDMA2_GPU_IOV_VIOLATION_LOG2
>+#define SDMA2_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                     0x0
>+#define SDMA2_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                       0x000000FFL
>+//SDMA2_GFX_RB_CNTL
>+#define SDMA2_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA2_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
>+#define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
>+#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
>+#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
>+#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
>+#define SDMA2_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
>+#define SDMA2_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
>+#define SDMA2_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA2_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
>+#define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
>+#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
>+#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
>+#define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
>+#define SDMA2_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
>+#define SDMA2_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
>+//SDMA2_GFX_RB_BASE
>+#define SDMA2_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
>+#define SDMA2_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
>+//SDMA2_GFX_RB_BASE_HI
>+#define SDMA2_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA2_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
>+//SDMA2_GFX_RB_RPTR
>+#define SDMA2_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA2_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA2_GFX_RB_RPTR_HI
>+#define SDMA2_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA2_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA2_GFX_RB_WPTR
>+#define SDMA2_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA2_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA2_GFX_RB_WPTR_HI
>+#define SDMA2_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA2_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA2_GFX_RB_WPTR_POLL_CNTL
>+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
>+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
>+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
>+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
>+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
>+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
>+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
>+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
>+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
>+#define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
>+//SDMA2_GFX_RB_RPTR_ADDR_HI
>+#define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
>+#define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
>+//SDMA2_GFX_RB_RPTR_ADDR_LO
>+#define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                        0x0
>+#define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
>+#define SDMA2_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                          0x00000001L
>+#define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
>+//SDMA2_GFX_IB_CNTL
>+#define SDMA2_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
>+#define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
>+#define SDMA2_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
>+#define SDMA2_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
>+#define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
>+#define SDMA2_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
>+//SDMA2_GFX_IB_RPTR
>+#define SDMA2_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
>+#define SDMA2_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
>+//SDMA2_GFX_IB_OFFSET
>+#define SDMA2_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
>+#define SDMA2_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
>+//SDMA2_GFX_IB_BASE_LO
>+#define SDMA2_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
>+#define SDMA2_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
>+//SDMA2_GFX_IB_BASE_HI
>+#define SDMA2_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA2_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_GFX_IB_SIZE
>+#define SDMA2_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
>+#define SDMA2_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
>+//SDMA2_GFX_SKIP_CNTL
>+#define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
>+#define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
>+//SDMA2_GFX_CONTEXT_STATUS
>+#define SDMA2_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
>+#define SDMA2_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
>+#define SDMA2_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
>+#define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
>+#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
>+#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
>+#define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
>+#define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
>+#define SDMA2_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
>+#define SDMA2_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
>+#define SDMA2_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
>+#define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
>+#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
>+#define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
>+#define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
>+#define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
>+//SDMA2_GFX_DOORBELL
>+#define SDMA2_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
>+#define SDMA2_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
>+#define SDMA2_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
>+#define SDMA2_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
>+//SDMA2_GFX_CONTEXT_CNTL
>+#define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
>+#define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
>+//SDMA2_GFX_STATUS
>+#define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
>+#define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
>+#define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
>+#define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
>+//SDMA2_GFX_DOORBELL_LOG
>+#define SDMA2_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
>+#define SDMA2_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
>+#define SDMA2_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
>+#define SDMA2_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
>+//SDMA2_GFX_WATERMARK
>+#define SDMA2_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
>+#define SDMA2_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
>+#define SDMA2_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
>+#define SDMA2_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
>+//SDMA2_GFX_DOORBELL_OFFSET
>+#define SDMA2_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
>+#define SDMA2_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
>+//SDMA2_GFX_CSA_ADDR_LO
>+#define SDMA2_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
>+#define SDMA2_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
>+//SDMA2_GFX_CSA_ADDR_HI
>+#define SDMA2_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_GFX_IB_SUB_REMAIN
>+#define SDMA2_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
>+#define SDMA2_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x000FFFFFL
>+//SDMA2_GFX_PREEMPT
>+#define SDMA2_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
>+#define SDMA2_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
>+//SDMA2_GFX_DUMMY_REG
>+#define SDMA2_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
>+#define SDMA2_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_GFX_RB_WPTR_POLL_ADDR_HI
>+#define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
>+#define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
>+//SDMA2_GFX_RB_WPTR_POLL_ADDR_LO
>+#define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
>+#define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
>+//SDMA2_GFX_RB_AQL_CNTL
>+#define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
>+#define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
>+#define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
>+#define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
>+#define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
>+#define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
>+//SDMA2_GFX_MINOR_PTR_UPDATE
>+#define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
>+#define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
>+//SDMA2_GFX_MIDCMD_DATA0
>+#define SDMA2_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
>+#define SDMA2_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_GFX_MIDCMD_DATA1
>+#define SDMA2_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
>+#define SDMA2_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_GFX_MIDCMD_DATA2
>+#define SDMA2_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
>+#define SDMA2_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_GFX_MIDCMD_DATA3
>+#define SDMA2_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
>+#define SDMA2_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_GFX_MIDCMD_DATA4
>+#define SDMA2_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
>+#define SDMA2_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_GFX_MIDCMD_DATA5
>+#define SDMA2_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
>+#define SDMA2_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_GFX_MIDCMD_DATA6
>+#define SDMA2_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
>+#define SDMA2_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_GFX_MIDCMD_DATA7
>+#define SDMA2_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
>+#define SDMA2_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_GFX_MIDCMD_DATA8
>+#define SDMA2_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
>+#define SDMA2_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_GFX_MIDCMD_CNTL
>+#define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
>+#define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
>+#define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
>+#define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
>+#define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
>+#define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
>+#define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
>+#define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
>+//SDMA2_PAGE_RB_CNTL
>+#define SDMA2_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA2_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA2_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA2_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA2_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA2_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA2_PAGE_RB_BASE
>+#define SDMA2_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA2_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA2_PAGE_RB_BASE_HI
>+#define SDMA2_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA2_PAGE_RB_RPTR
>+#define SDMA2_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_PAGE_RB_RPTR_HI
>+#define SDMA2_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_PAGE_RB_WPTR
>+#define SDMA2_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_PAGE_RB_WPTR_HI
>+#define SDMA2_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_PAGE_RB_WPTR_POLL_CNTL
>+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA2_PAGE_RB_RPTR_ADDR_HI
>+#define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA2_PAGE_RB_RPTR_ADDR_LO
>+#define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA2_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA2_PAGE_IB_CNTL
>+#define SDMA2_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA2_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA2_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA2_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA2_PAGE_IB_RPTR
>+#define SDMA2_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA2_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA2_PAGE_IB_OFFSET
>+#define SDMA2_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA2_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA2_PAGE_IB_BASE_LO
>+#define SDMA2_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA2_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA2_PAGE_IB_BASE_HI
>+#define SDMA2_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_PAGE_IB_SIZE
>+#define SDMA2_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA2_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA2_PAGE_SKIP_CNTL
>+#define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA2_PAGE_CONTEXT_STATUS
>+#define SDMA2_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA2_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA2_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA2_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA2_PAGE_DOORBELL
>+#define SDMA2_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA2_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA2_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA2_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA2_PAGE_STATUS
>+#define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA2_PAGE_DOORBELL_LOG
>+#define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA2_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA2_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA2_PAGE_WATERMARK
>+#define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA2_PAGE_DOORBELL_OFFSET
>+#define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA2_PAGE_CSA_ADDR_LO
>+#define SDMA2_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA2_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA2_PAGE_CSA_ADDR_HI
>+#define SDMA2_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA2_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA2_PAGE_IB_SUB_REMAIN
>+#define SDMA2_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA2_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA2_PAGE_PREEMPT
>+#define SDMA2_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA2_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA2_PAGE_DUMMY_REG
>+#define SDMA2_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA2_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI
>+#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO
>+#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA2_PAGE_RB_AQL_CNTL
>+#define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA2_PAGE_MINOR_PTR_UPDATE
>+#define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA2_PAGE_MIDCMD_DATA0
>+#define SDMA2_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA2_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_PAGE_MIDCMD_DATA1
>+#define SDMA2_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA2_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_PAGE_MIDCMD_DATA2
>+#define SDMA2_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA2_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_PAGE_MIDCMD_DATA3
>+#define SDMA2_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA2_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_PAGE_MIDCMD_DATA4
>+#define SDMA2_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA2_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_PAGE_MIDCMD_DATA5
>+#define SDMA2_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA2_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_PAGE_MIDCMD_DATA6
>+#define SDMA2_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA2_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_PAGE_MIDCMD_DATA7
>+#define SDMA2_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA2_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_PAGE_MIDCMD_DATA8
>+#define SDMA2_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA2_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_PAGE_MIDCMD_CNTL
>+#define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA2_RLC0_RB_CNTL
>+#define SDMA2_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA2_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA2_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA2_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA2_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA2_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA2_RLC0_RB_BASE
>+#define SDMA2_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA2_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA2_RLC0_RB_BASE_HI
>+#define SDMA2_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA2_RLC0_RB_RPTR
>+#define SDMA2_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC0_RB_RPTR_HI
>+#define SDMA2_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC0_RB_WPTR
>+#define SDMA2_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC0_RB_WPTR_HI
>+#define SDMA2_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC0_RB_WPTR_POLL_CNTL
>+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA2_RLC0_RB_RPTR_ADDR_HI
>+#define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA2_RLC0_RB_RPTR_ADDR_LO
>+#define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA2_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA2_RLC0_IB_CNTL
>+#define SDMA2_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA2_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA2_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA2_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA2_RLC0_IB_RPTR
>+#define SDMA2_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA2_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA2_RLC0_IB_OFFSET
>+#define SDMA2_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA2_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA2_RLC0_IB_BASE_LO
>+#define SDMA2_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA2_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA2_RLC0_IB_BASE_HI
>+#define SDMA2_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC0_IB_SIZE
>+#define SDMA2_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA2_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA2_RLC0_SKIP_CNTL
>+#define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA2_RLC0_CONTEXT_STATUS
>+#define SDMA2_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA2_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA2_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA2_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA2_RLC0_DOORBELL
>+#define SDMA2_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA2_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA2_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA2_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA2_RLC0_STATUS
>+#define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA2_RLC0_DOORBELL_LOG
>+#define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA2_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA2_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA2_RLC0_WATERMARK
>+#define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA2_RLC0_DOORBELL_OFFSET
>+#define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA2_RLC0_CSA_ADDR_LO
>+#define SDMA2_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA2_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA2_RLC0_CSA_ADDR_HI
>+#define SDMA2_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA2_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA2_RLC0_IB_SUB_REMAIN
>+#define SDMA2_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA2_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA2_RLC0_PREEMPT
>+#define SDMA2_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA2_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA2_RLC0_DUMMY_REG
>+#define SDMA2_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA2_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI
>+#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO
>+#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA2_RLC0_RB_AQL_CNTL
>+#define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA2_RLC0_MINOR_PTR_UPDATE
>+#define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA2_RLC0_MIDCMD_DATA0
>+#define SDMA2_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA2_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC0_MIDCMD_DATA1
>+#define SDMA2_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA2_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC0_MIDCMD_DATA2
>+#define SDMA2_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA2_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC0_MIDCMD_DATA3
>+#define SDMA2_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA2_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC0_MIDCMD_DATA4
>+#define SDMA2_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA2_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC0_MIDCMD_DATA5
>+#define SDMA2_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA2_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC0_MIDCMD_DATA6
>+#define SDMA2_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA2_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC0_MIDCMD_DATA7
>+#define SDMA2_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA2_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC0_MIDCMD_DATA8
>+#define SDMA2_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA2_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC0_MIDCMD_CNTL
>+#define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA2_RLC1_RB_CNTL
>+#define SDMA2_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA2_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA2_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA2_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA2_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA2_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA2_RLC1_RB_BASE
>+#define SDMA2_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA2_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA2_RLC1_RB_BASE_HI
>+#define SDMA2_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA2_RLC1_RB_RPTR
>+#define SDMA2_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC1_RB_RPTR_HI
>+#define SDMA2_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC1_RB_WPTR
>+#define SDMA2_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC1_RB_WPTR_HI
>+#define SDMA2_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC1_RB_WPTR_POLL_CNTL
>+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA2_RLC1_RB_RPTR_ADDR_HI
>+#define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA2_RLC1_RB_RPTR_ADDR_LO
>+#define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA2_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA2_RLC1_IB_CNTL
>+#define SDMA2_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA2_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA2_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA2_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA2_RLC1_IB_RPTR
>+#define SDMA2_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA2_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA2_RLC1_IB_OFFSET
>+#define SDMA2_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA2_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA2_RLC1_IB_BASE_LO
>+#define SDMA2_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA2_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA2_RLC1_IB_BASE_HI
>+#define SDMA2_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC1_IB_SIZE
>+#define SDMA2_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA2_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA2_RLC1_SKIP_CNTL
>+#define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA2_RLC1_CONTEXT_STATUS
>+#define SDMA2_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA2_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA2_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA2_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA2_RLC1_DOORBELL
>+#define SDMA2_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA2_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA2_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA2_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA2_RLC1_STATUS
>+#define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA2_RLC1_DOORBELL_LOG
>+#define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA2_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA2_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA2_RLC1_WATERMARK
>+#define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA2_RLC1_DOORBELL_OFFSET
>+#define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA2_RLC1_CSA_ADDR_LO
>+#define SDMA2_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA2_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA2_RLC1_CSA_ADDR_HI
>+#define SDMA2_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA2_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA2_RLC1_IB_SUB_REMAIN
>+#define SDMA2_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA2_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA2_RLC1_PREEMPT
>+#define SDMA2_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA2_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA2_RLC1_DUMMY_REG
>+#define SDMA2_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA2_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI
>+#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO
>+#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA2_RLC1_RB_AQL_CNTL
>+#define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA2_RLC1_MINOR_PTR_UPDATE
>+#define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA2_RLC1_MIDCMD_DATA0
>+#define SDMA2_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA2_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC1_MIDCMD_DATA1
>+#define SDMA2_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA2_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC1_MIDCMD_DATA2
>+#define SDMA2_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA2_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC1_MIDCMD_DATA3
>+#define SDMA2_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA2_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC1_MIDCMD_DATA4
>+#define SDMA2_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA2_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC1_MIDCMD_DATA5
>+#define SDMA2_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA2_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC1_MIDCMD_DATA6
>+#define SDMA2_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA2_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC1_MIDCMD_DATA7
>+#define SDMA2_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA2_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC1_MIDCMD_DATA8
>+#define SDMA2_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA2_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC1_MIDCMD_CNTL
>+#define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA2_RLC2_RB_CNTL
>+#define SDMA2_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA2_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA2_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA2_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA2_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA2_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA2_RLC2_RB_BASE
>+#define SDMA2_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA2_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA2_RLC2_RB_BASE_HI
>+#define SDMA2_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA2_RLC2_RB_RPTR
>+#define SDMA2_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC2_RB_RPTR_HI
>+#define SDMA2_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC2_RB_WPTR
>+#define SDMA2_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC2_RB_WPTR_HI
>+#define SDMA2_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC2_RB_WPTR_POLL_CNTL
>+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA2_RLC2_RB_RPTR_ADDR_HI
>+#define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA2_RLC2_RB_RPTR_ADDR_LO
>+#define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA2_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA2_RLC2_IB_CNTL
>+#define SDMA2_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA2_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA2_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA2_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA2_RLC2_IB_RPTR
>+#define SDMA2_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA2_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA2_RLC2_IB_OFFSET
>+#define SDMA2_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA2_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA2_RLC2_IB_BASE_LO
>+#define SDMA2_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA2_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA2_RLC2_IB_BASE_HI
>+#define SDMA2_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC2_IB_SIZE
>+#define SDMA2_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA2_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA2_RLC2_SKIP_CNTL
>+#define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA2_RLC2_CONTEXT_STATUS
>+#define SDMA2_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA2_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA2_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA2_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA2_RLC2_DOORBELL
>+#define SDMA2_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA2_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA2_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA2_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA2_RLC2_STATUS
>+#define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA2_RLC2_DOORBELL_LOG
>+#define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA2_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA2_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA2_RLC2_WATERMARK
>+#define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA2_RLC2_DOORBELL_OFFSET
>+#define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA2_RLC2_CSA_ADDR_LO
>+#define SDMA2_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA2_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA2_RLC2_CSA_ADDR_HI
>+#define SDMA2_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA2_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA2_RLC2_IB_SUB_REMAIN
>+#define SDMA2_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA2_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA2_RLC2_PREEMPT
>+#define SDMA2_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA2_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA2_RLC2_DUMMY_REG
>+#define SDMA2_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA2_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI
>+#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO
>+#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA2_RLC2_RB_AQL_CNTL
>+#define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA2_RLC2_MINOR_PTR_UPDATE
>+#define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA2_RLC2_MIDCMD_DATA0
>+#define SDMA2_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA2_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC2_MIDCMD_DATA1
>+#define SDMA2_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA2_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC2_MIDCMD_DATA2
>+#define SDMA2_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA2_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC2_MIDCMD_DATA3
>+#define SDMA2_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA2_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC2_MIDCMD_DATA4
>+#define SDMA2_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA2_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC2_MIDCMD_DATA5
>+#define SDMA2_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA2_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC2_MIDCMD_DATA6
>+#define SDMA2_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA2_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC2_MIDCMD_DATA7
>+#define SDMA2_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA2_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC2_MIDCMD_DATA8
>+#define SDMA2_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA2_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC2_MIDCMD_CNTL
>+#define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA2_RLC3_RB_CNTL
>+#define SDMA2_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA2_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA2_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA2_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA2_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA2_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA2_RLC3_RB_BASE
>+#define SDMA2_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA2_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA2_RLC3_RB_BASE_HI
>+#define SDMA2_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA2_RLC3_RB_RPTR
>+#define SDMA2_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC3_RB_RPTR_HI
>+#define SDMA2_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC3_RB_WPTR
>+#define SDMA2_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC3_RB_WPTR_HI
>+#define SDMA2_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC3_RB_WPTR_POLL_CNTL
>+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA2_RLC3_RB_RPTR_ADDR_HI
>+#define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA2_RLC3_RB_RPTR_ADDR_LO
>+#define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA2_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA2_RLC3_IB_CNTL
>+#define SDMA2_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA2_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA2_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA2_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA2_RLC3_IB_RPTR
>+#define SDMA2_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA2_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA2_RLC3_IB_OFFSET
>+#define SDMA2_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA2_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA2_RLC3_IB_BASE_LO
>+#define SDMA2_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA2_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA2_RLC3_IB_BASE_HI
>+#define SDMA2_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC3_IB_SIZE
>+#define SDMA2_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA2_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA2_RLC3_SKIP_CNTL
>+#define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA2_RLC3_CONTEXT_STATUS
>+#define SDMA2_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA2_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA2_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA2_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA2_RLC3_DOORBELL
>+#define SDMA2_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA2_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA2_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA2_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA2_RLC3_STATUS
>+#define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA2_RLC3_DOORBELL_LOG
>+#define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA2_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA2_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA2_RLC3_WATERMARK
>+#define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA2_RLC3_DOORBELL_OFFSET
>+#define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA2_RLC3_CSA_ADDR_LO
>+#define SDMA2_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA2_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA2_RLC3_CSA_ADDR_HI
>+#define SDMA2_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA2_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA2_RLC3_IB_SUB_REMAIN
>+#define SDMA2_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA2_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA2_RLC3_PREEMPT
>+#define SDMA2_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA2_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA2_RLC3_DUMMY_REG
>+#define SDMA2_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA2_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI
>+#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO
>+#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA2_RLC3_RB_AQL_CNTL
>+#define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA2_RLC3_MINOR_PTR_UPDATE
>+#define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA2_RLC3_MIDCMD_DATA0
>+#define SDMA2_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA2_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC3_MIDCMD_DATA1
>+#define SDMA2_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA2_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC3_MIDCMD_DATA2
>+#define SDMA2_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA2_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC3_MIDCMD_DATA3
>+#define SDMA2_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA2_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC3_MIDCMD_DATA4
>+#define SDMA2_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA2_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC3_MIDCMD_DATA5
>+#define SDMA2_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA2_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC3_MIDCMD_DATA6
>+#define SDMA2_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA2_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC3_MIDCMD_DATA7
>+#define SDMA2_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA2_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC3_MIDCMD_DATA8
>+#define SDMA2_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA2_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC3_MIDCMD_CNTL
>+#define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA2_RLC4_RB_CNTL
>+#define SDMA2_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA2_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA2_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA2_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA2_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA2_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA2_RLC4_RB_BASE
>+#define SDMA2_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA2_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA2_RLC4_RB_BASE_HI
>+#define SDMA2_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA2_RLC4_RB_RPTR
>+#define SDMA2_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC4_RB_RPTR_HI
>+#define SDMA2_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC4_RB_WPTR
>+#define SDMA2_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC4_RB_WPTR_HI
>+#define SDMA2_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC4_RB_WPTR_POLL_CNTL
>+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA2_RLC4_RB_RPTR_ADDR_HI
>+#define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA2_RLC4_RB_RPTR_ADDR_LO
>+#define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA2_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA2_RLC4_IB_CNTL
>+#define SDMA2_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA2_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA2_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA2_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA2_RLC4_IB_RPTR
>+#define SDMA2_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA2_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA2_RLC4_IB_OFFSET
>+#define SDMA2_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA2_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA2_RLC4_IB_BASE_LO
>+#define SDMA2_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA2_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA2_RLC4_IB_BASE_HI
>+#define SDMA2_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC4_IB_SIZE
>+#define SDMA2_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA2_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA2_RLC4_SKIP_CNTL
>+#define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA2_RLC4_CONTEXT_STATUS
>+#define SDMA2_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA2_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA2_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA2_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA2_RLC4_DOORBELL
>+#define SDMA2_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA2_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA2_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA2_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA2_RLC4_STATUS
>+#define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA2_RLC4_DOORBELL_LOG
>+#define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA2_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA2_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA2_RLC4_WATERMARK
>+#define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA2_RLC4_DOORBELL_OFFSET
>+#define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA2_RLC4_CSA_ADDR_LO
>+#define SDMA2_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA2_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA2_RLC4_CSA_ADDR_HI
>+#define SDMA2_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA2_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA2_RLC4_IB_SUB_REMAIN
>+#define SDMA2_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA2_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA2_RLC4_PREEMPT
>+#define SDMA2_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA2_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA2_RLC4_DUMMY_REG
>+#define SDMA2_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA2_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI
>+#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO
>+#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA2_RLC4_RB_AQL_CNTL
>+#define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA2_RLC4_MINOR_PTR_UPDATE
>+#define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA2_RLC4_MIDCMD_DATA0
>+#define SDMA2_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA2_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC4_MIDCMD_DATA1
>+#define SDMA2_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA2_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC4_MIDCMD_DATA2
>+#define SDMA2_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA2_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC4_MIDCMD_DATA3
>+#define SDMA2_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA2_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC4_MIDCMD_DATA4
>+#define SDMA2_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA2_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC4_MIDCMD_DATA5
>+#define SDMA2_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA2_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC4_MIDCMD_DATA6
>+#define SDMA2_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA2_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC4_MIDCMD_DATA7
>+#define SDMA2_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA2_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC4_MIDCMD_DATA8
>+#define SDMA2_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA2_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC4_MIDCMD_CNTL
>+#define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA2_RLC5_RB_CNTL
>+#define SDMA2_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA2_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA2_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA2_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA2_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA2_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA2_RLC5_RB_BASE
>+#define SDMA2_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA2_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA2_RLC5_RB_BASE_HI
>+#define SDMA2_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA2_RLC5_RB_RPTR
>+#define SDMA2_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC5_RB_RPTR_HI
>+#define SDMA2_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC5_RB_WPTR
>+#define SDMA2_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC5_RB_WPTR_HI
>+#define SDMA2_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC5_RB_WPTR_POLL_CNTL
>+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA2_RLC5_RB_RPTR_ADDR_HI
>+#define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA2_RLC5_RB_RPTR_ADDR_LO
>+#define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA2_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA2_RLC5_IB_CNTL
>+#define SDMA2_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA2_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA2_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA2_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA2_RLC5_IB_RPTR
>+#define SDMA2_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA2_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA2_RLC5_IB_OFFSET
>+#define SDMA2_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA2_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA2_RLC5_IB_BASE_LO
>+#define SDMA2_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA2_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA2_RLC5_IB_BASE_HI
>+#define SDMA2_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC5_IB_SIZE
>+#define SDMA2_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA2_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA2_RLC5_SKIP_CNTL
>+#define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA2_RLC5_CONTEXT_STATUS
>+#define SDMA2_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA2_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA2_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA2_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA2_RLC5_DOORBELL
>+#define SDMA2_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA2_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA2_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA2_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA2_RLC5_STATUS
>+#define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA2_RLC5_DOORBELL_LOG
>+#define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA2_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA2_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA2_RLC5_WATERMARK
>+#define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA2_RLC5_DOORBELL_OFFSET
>+#define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA2_RLC5_CSA_ADDR_LO
>+#define SDMA2_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA2_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA2_RLC5_CSA_ADDR_HI
>+#define SDMA2_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA2_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA2_RLC5_IB_SUB_REMAIN
>+#define SDMA2_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA2_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA2_RLC5_PREEMPT
>+#define SDMA2_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA2_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA2_RLC5_DUMMY_REG
>+#define SDMA2_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA2_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI
>+#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO
>+#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA2_RLC5_RB_AQL_CNTL
>+#define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA2_RLC5_MINOR_PTR_UPDATE
>+#define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA2_RLC5_MIDCMD_DATA0
>+#define SDMA2_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA2_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC5_MIDCMD_DATA1
>+#define SDMA2_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA2_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC5_MIDCMD_DATA2
>+#define SDMA2_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA2_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC5_MIDCMD_DATA3
>+#define SDMA2_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA2_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC5_MIDCMD_DATA4
>+#define SDMA2_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA2_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC5_MIDCMD_DATA5
>+#define SDMA2_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA2_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC5_MIDCMD_DATA6
>+#define SDMA2_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA2_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC5_MIDCMD_DATA7
>+#define SDMA2_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA2_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC5_MIDCMD_DATA8
>+#define SDMA2_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA2_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC5_MIDCMD_CNTL
>+#define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA2_RLC6_RB_CNTL
>+#define SDMA2_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA2_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA2_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA2_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA2_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA2_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA2_RLC6_RB_BASE
>+#define SDMA2_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA2_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA2_RLC6_RB_BASE_HI
>+#define SDMA2_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA2_RLC6_RB_RPTR
>+#define SDMA2_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC6_RB_RPTR_HI
>+#define SDMA2_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC6_RB_WPTR
>+#define SDMA2_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC6_RB_WPTR_HI
>+#define SDMA2_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC6_RB_WPTR_POLL_CNTL
>+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA2_RLC6_RB_RPTR_ADDR_HI
>+#define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA2_RLC6_RB_RPTR_ADDR_LO
>+#define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA2_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA2_RLC6_IB_CNTL
>+#define SDMA2_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA2_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA2_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA2_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA2_RLC6_IB_RPTR
>+#define SDMA2_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA2_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA2_RLC6_IB_OFFSET
>+#define SDMA2_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA2_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA2_RLC6_IB_BASE_LO
>+#define SDMA2_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA2_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA2_RLC6_IB_BASE_HI
>+#define SDMA2_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC6_IB_SIZE
>+#define SDMA2_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA2_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA2_RLC6_SKIP_CNTL
>+#define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA2_RLC6_CONTEXT_STATUS
>+#define SDMA2_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA2_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA2_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA2_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA2_RLC6_DOORBELL
>+#define SDMA2_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA2_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA2_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA2_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA2_RLC6_STATUS
>+#define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA2_RLC6_DOORBELL_LOG
>+#define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA2_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA2_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA2_RLC6_WATERMARK
>+#define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA2_RLC6_DOORBELL_OFFSET
>+#define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA2_RLC6_CSA_ADDR_LO
>+#define SDMA2_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA2_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA2_RLC6_CSA_ADDR_HI
>+#define SDMA2_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA2_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA2_RLC6_IB_SUB_REMAIN
>+#define SDMA2_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA2_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA2_RLC6_PREEMPT
>+#define SDMA2_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA2_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA2_RLC6_DUMMY_REG
>+#define SDMA2_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA2_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI
>+#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO
>+#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA2_RLC6_RB_AQL_CNTL
>+#define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA2_RLC6_MINOR_PTR_UPDATE
>+#define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA2_RLC6_MIDCMD_DATA0
>+#define SDMA2_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA2_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC6_MIDCMD_DATA1
>+#define SDMA2_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA2_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC6_MIDCMD_DATA2
>+#define SDMA2_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA2_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC6_MIDCMD_DATA3
>+#define SDMA2_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA2_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC6_MIDCMD_DATA4
>+#define SDMA2_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA2_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC6_MIDCMD_DATA5
>+#define SDMA2_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA2_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC6_MIDCMD_DATA6
>+#define SDMA2_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA2_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC6_MIDCMD_DATA7
>+#define SDMA2_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA2_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC6_MIDCMD_DATA8
>+#define SDMA2_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA2_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC6_MIDCMD_CNTL
>+#define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA2_RLC7_RB_CNTL
>+#define SDMA2_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA2_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA2_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA2_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA2_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA2_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA2_RLC7_RB_BASE
>+#define SDMA2_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA2_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA2_RLC7_RB_BASE_HI
>+#define SDMA2_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA2_RLC7_RB_RPTR
>+#define SDMA2_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC7_RB_RPTR_HI
>+#define SDMA2_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC7_RB_WPTR
>+#define SDMA2_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA2_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA2_RLC7_RB_WPTR_HI
>+#define SDMA2_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA2_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA2_RLC7_RB_WPTR_POLL_CNTL
>+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA2_RLC7_RB_RPTR_ADDR_HI
>+#define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA2_RLC7_RB_RPTR_ADDR_LO
>+#define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA2_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA2_RLC7_IB_CNTL
>+#define SDMA2_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA2_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA2_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA2_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA2_RLC7_IB_RPTR
>+#define SDMA2_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA2_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA2_RLC7_IB_OFFSET
>+#define SDMA2_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA2_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA2_RLC7_IB_BASE_LO
>+#define SDMA2_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA2_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA2_RLC7_IB_BASE_HI
>+#define SDMA2_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA2_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC7_IB_SIZE
>+#define SDMA2_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA2_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA2_RLC7_SKIP_CNTL
>+#define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA2_RLC7_CONTEXT_STATUS
>+#define SDMA2_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA2_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA2_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA2_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA2_RLC7_DOORBELL
>+#define SDMA2_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA2_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA2_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA2_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA2_RLC7_STATUS
>+#define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA2_RLC7_DOORBELL_LOG
>+#define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA2_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA2_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA2_RLC7_WATERMARK
>+#define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA2_RLC7_DOORBELL_OFFSET
>+#define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA2_RLC7_CSA_ADDR_LO
>+#define SDMA2_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA2_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA2_RLC7_CSA_ADDR_HI
>+#define SDMA2_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA2_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA2_RLC7_IB_SUB_REMAIN
>+#define SDMA2_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA2_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA2_RLC7_PREEMPT
>+#define SDMA2_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA2_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA2_RLC7_DUMMY_REG
>+#define SDMA2_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA2_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI
>+#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO
>+#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA2_RLC7_RB_AQL_CNTL
>+#define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA2_RLC7_MINOR_PTR_UPDATE
>+#define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA2_RLC7_MIDCMD_DATA0
>+#define SDMA2_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA2_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC7_MIDCMD_DATA1
>+#define SDMA2_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA2_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC7_MIDCMD_DATA2
>+#define SDMA2_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA2_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC7_MIDCMD_DATA3
>+#define SDMA2_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA2_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC7_MIDCMD_DATA4
>+#define SDMA2_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA2_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC7_MIDCMD_DATA5
>+#define SDMA2_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA2_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC7_MIDCMD_DATA6
>+#define SDMA2_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA2_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC7_MIDCMD_DATA7
>+#define SDMA2_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA2_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC7_MIDCMD_DATA8
>+#define SDMA2_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA2_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA2_RLC7_MIDCMD_CNTL
>+#define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_offset.h	2019-08-31 15:01:11.932736175 -0500
>@@ -0,0 +1,1043 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma3_4_2_2_OFFSET_HEADER
>+#define _sdma3_4_2_2_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: sdma3_sdma3dec
>+// base address: 0x79000
>+#define mmSDMA3_UCODE_ADDR                                                                             0x0000
>+#define mmSDMA3_UCODE_ADDR_BASE_IDX                                                                    1
>+#define mmSDMA3_UCODE_DATA                                                                             0x0001
>+#define mmSDMA3_UCODE_DATA_BASE_IDX                                                                    1
>+#define mmSDMA3_VM_CNTL                                                                                0x0004
>+#define mmSDMA3_VM_CNTL_BASE_IDX                                                                       1
>+#define mmSDMA3_VM_CTX_LO                                                                              0x0005
>+#define mmSDMA3_VM_CTX_LO_BASE_IDX                                                                     1
>+#define mmSDMA3_VM_CTX_HI                                                                              0x0006
>+#define mmSDMA3_VM_CTX_HI_BASE_IDX                                                                     1
>+#define mmSDMA3_ACTIVE_FCN_ID                                                                          0x0007
>+#define mmSDMA3_ACTIVE_FCN_ID_BASE_IDX                                                                 1
>+#define mmSDMA3_VM_CTX_CNTL                                                                            0x0008
>+#define mmSDMA3_VM_CTX_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA3_VIRT_RESET_REQ                                                                         0x0009
>+#define mmSDMA3_VIRT_RESET_REQ_BASE_IDX                                                                1
>+#define mmSDMA3_VF_ENABLE                                                                              0x000a
>+#define mmSDMA3_VF_ENABLE_BASE_IDX                                                                     1
>+#define mmSDMA3_CONTEXT_REG_TYPE0                                                                      0x000b
>+#define mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX                                                             1
>+#define mmSDMA3_CONTEXT_REG_TYPE1                                                                      0x000c
>+#define mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX                                                             1
>+#define mmSDMA3_CONTEXT_REG_TYPE2                                                                      0x000d
>+#define mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX                                                             1
>+#define mmSDMA3_CONTEXT_REG_TYPE3                                                                      0x000e
>+#define mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX                                                             1
>+#define mmSDMA3_PUB_REG_TYPE0                                                                          0x000f
>+#define mmSDMA3_PUB_REG_TYPE0_BASE_IDX                                                                 1
>+#define mmSDMA3_PUB_REG_TYPE1                                                                          0x0010
>+#define mmSDMA3_PUB_REG_TYPE1_BASE_IDX                                                                 1
>+#define mmSDMA3_PUB_REG_TYPE2                                                                          0x0011
>+#define mmSDMA3_PUB_REG_TYPE2_BASE_IDX                                                                 1
>+#define mmSDMA3_PUB_REG_TYPE3                                                                          0x0012
>+#define mmSDMA3_PUB_REG_TYPE3_BASE_IDX                                                                 1
>+#define mmSDMA3_MMHUB_CNTL                                                                             0x0013
>+#define mmSDMA3_MMHUB_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA3_CONTEXT_GROUP_BOUNDARY                                                                 0x0019
>+#define mmSDMA3_CONTEXT_GROUP_BOUNDARY_BASE_IDX                                                        1
>+#define mmSDMA3_POWER_CNTL                                                                             0x001a
>+#define mmSDMA3_POWER_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA3_CLK_CTRL                                                                               0x001b
>+#define mmSDMA3_CLK_CTRL_BASE_IDX                                                                      1
>+#define mmSDMA3_CNTL                                                                                   0x001c
>+#define mmSDMA3_CNTL_BASE_IDX                                                                          1
>+#define mmSDMA3_CHICKEN_BITS                                                                           0x001d
>+#define mmSDMA3_CHICKEN_BITS_BASE_IDX                                                                  1
>+#define mmSDMA3_GB_ADDR_CONFIG                                                                         0x001e
>+#define mmSDMA3_GB_ADDR_CONFIG_BASE_IDX                                                                1
>+#define mmSDMA3_GB_ADDR_CONFIG_READ                                                                    0x001f
>+#define mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX                                                           1
>+#define mmSDMA3_RB_RPTR_FETCH_HI                                                                       0x0020
>+#define mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX                                                              1
>+#define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0021
>+#define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      1
>+#define mmSDMA3_RB_RPTR_FETCH                                                                          0x0022
>+#define mmSDMA3_RB_RPTR_FETCH_BASE_IDX                                                                 1
>+#define mmSDMA3_IB_OFFSET_FETCH                                                                        0x0023
>+#define mmSDMA3_IB_OFFSET_FETCH_BASE_IDX                                                               1
>+#define mmSDMA3_PROGRAM                                                                                0x0024
>+#define mmSDMA3_PROGRAM_BASE_IDX                                                                       1
>+#define mmSDMA3_STATUS_REG                                                                             0x0025
>+#define mmSDMA3_STATUS_REG_BASE_IDX                                                                    1
>+#define mmSDMA3_STATUS1_REG                                                                            0x0026
>+#define mmSDMA3_STATUS1_REG_BASE_IDX                                                                   1
>+#define mmSDMA3_RD_BURST_CNTL                                                                          0x0027
>+#define mmSDMA3_RD_BURST_CNTL_BASE_IDX                                                                 1
>+#define mmSDMA3_HBM_PAGE_CONFIG                                                                        0x0028
>+#define mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX                                                               1
>+#define mmSDMA3_UCODE_CHECKSUM                                                                         0x0029
>+#define mmSDMA3_UCODE_CHECKSUM_BASE_IDX                                                                1
>+#define mmSDMA3_F32_CNTL                                                                               0x002a
>+#define mmSDMA3_F32_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA3_FREEZE                                                                                 0x002b
>+#define mmSDMA3_FREEZE_BASE_IDX                                                                        1
>+#define mmSDMA3_PHASE0_QUANTUM                                                                         0x002c
>+#define mmSDMA3_PHASE0_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA3_PHASE1_QUANTUM                                                                         0x002d
>+#define mmSDMA3_PHASE1_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA3_EDC_CONFIG                                                                             0x0032
>+#define mmSDMA3_EDC_CONFIG_BASE_IDX                                                                    1
>+#define mmSDMA3_BA_THRESHOLD                                                                           0x0033
>+#define mmSDMA3_BA_THRESHOLD_BASE_IDX                                                                  1
>+#define mmSDMA3_ID                                                                                     0x0034
>+#define mmSDMA3_ID_BASE_IDX                                                                            1
>+#define mmSDMA3_VERSION                                                                                0x0035
>+#define mmSDMA3_VERSION_BASE_IDX                                                                       1
>+#define mmSDMA3_EDC_COUNTER                                                                            0x0036
>+#define mmSDMA3_EDC_COUNTER_BASE_IDX                                                                   1
>+#define mmSDMA3_EDC_COUNTER_CLEAR                                                                      0x0037
>+#define mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX                                                             1
>+#define mmSDMA3_STATUS2_REG                                                                            0x0038
>+#define mmSDMA3_STATUS2_REG_BASE_IDX                                                                   1
>+#define mmSDMA3_ATOMIC_CNTL                                                                            0x0039
>+#define mmSDMA3_ATOMIC_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA3_ATOMIC_PREOP_LO                                                                        0x003a
>+#define mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX                                                               1
>+#define mmSDMA3_ATOMIC_PREOP_HI                                                                        0x003b
>+#define mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX                                                               1
>+#define mmSDMA3_UTCL1_CNTL                                                                             0x003c
>+#define mmSDMA3_UTCL1_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA3_UTCL1_WATERMK                                                                          0x003d
>+#define mmSDMA3_UTCL1_WATERMK_BASE_IDX                                                                 1
>+#define mmSDMA3_UTCL1_RD_STATUS                                                                        0x003e
>+#define mmSDMA3_UTCL1_RD_STATUS_BASE_IDX                                                               1
>+#define mmSDMA3_UTCL1_WR_STATUS                                                                        0x003f
>+#define mmSDMA3_UTCL1_WR_STATUS_BASE_IDX                                                               1
>+#define mmSDMA3_UTCL1_INV0                                                                             0x0040
>+#define mmSDMA3_UTCL1_INV0_BASE_IDX                                                                    1
>+#define mmSDMA3_UTCL1_INV1                                                                             0x0041
>+#define mmSDMA3_UTCL1_INV1_BASE_IDX                                                                    1
>+#define mmSDMA3_UTCL1_INV2                                                                             0x0042
>+#define mmSDMA3_UTCL1_INV2_BASE_IDX                                                                    1
>+#define mmSDMA3_UTCL1_RD_XNACK0                                                                        0x0043
>+#define mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX                                                               1
>+#define mmSDMA3_UTCL1_RD_XNACK1                                                                        0x0044
>+#define mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX                                                               1
>+#define mmSDMA3_UTCL1_WR_XNACK0                                                                        0x0045
>+#define mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX                                                               1
>+#define mmSDMA3_UTCL1_WR_XNACK1                                                                        0x0046
>+#define mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX                                                               1
>+#define mmSDMA3_UTCL1_TIMEOUT                                                                          0x0047
>+#define mmSDMA3_UTCL1_TIMEOUT_BASE_IDX                                                                 1
>+#define mmSDMA3_UTCL1_PAGE                                                                             0x0048
>+#define mmSDMA3_UTCL1_PAGE_BASE_IDX                                                                    1
>+#define mmSDMA3_POWER_CNTL_IDLE                                                                        0x0049
>+#define mmSDMA3_POWER_CNTL_IDLE_BASE_IDX                                                               1
>+#define mmSDMA3_RELAX_ORDERING_LUT                                                                     0x004a
>+#define mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX                                                            1
>+#define mmSDMA3_CHICKEN_BITS_2                                                                         0x004b
>+#define mmSDMA3_CHICKEN_BITS_2_BASE_IDX                                                                1
>+#define mmSDMA3_STATUS3_REG                                                                            0x004c
>+#define mmSDMA3_STATUS3_REG_BASE_IDX                                                                   1
>+#define mmSDMA3_PHYSICAL_ADDR_LO                                                                       0x004d
>+#define mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA3_PHYSICAL_ADDR_HI                                                                       0x004e
>+#define mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA3_PHASE2_QUANTUM                                                                         0x004f
>+#define mmSDMA3_PHASE2_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA3_ERROR_LOG                                                                              0x0050
>+#define mmSDMA3_ERROR_LOG_BASE_IDX                                                                     1
>+#define mmSDMA3_PUB_DUMMY_REG0                                                                         0x0051
>+#define mmSDMA3_PUB_DUMMY_REG0_BASE_IDX                                                                1
>+#define mmSDMA3_PUB_DUMMY_REG1                                                                         0x0052
>+#define mmSDMA3_PUB_DUMMY_REG1_BASE_IDX                                                                1
>+#define mmSDMA3_PUB_DUMMY_REG2                                                                         0x0053
>+#define mmSDMA3_PUB_DUMMY_REG2_BASE_IDX                                                                1
>+#define mmSDMA3_PUB_DUMMY_REG3                                                                         0x0054
>+#define mmSDMA3_PUB_DUMMY_REG3_BASE_IDX                                                                1
>+#define mmSDMA3_F32_COUNTER                                                                            0x0055
>+#define mmSDMA3_F32_COUNTER_BASE_IDX                                                                   1
>+#define mmSDMA3_UNBREAKABLE                                                                            0x0056
>+#define mmSDMA3_UNBREAKABLE_BASE_IDX                                                                   1
>+#define mmSDMA3_PERFMON_CNTL                                                                           0x0057
>+#define mmSDMA3_PERFMON_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_PERFCOUNTER0_RESULT                                                                    0x0058
>+#define mmSDMA3_PERFCOUNTER0_RESULT_BASE_IDX                                                           1
>+#define mmSDMA3_PERFCOUNTER1_RESULT                                                                    0x0059
>+#define mmSDMA3_PERFCOUNTER1_RESULT_BASE_IDX                                                           1
>+#define mmSDMA3_PERFCOUNTER_TAG_DELAY_RANGE                                                            0x005a
>+#define mmSDMA3_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX                                                   1
>+#define mmSDMA3_CRD_CNTL                                                                               0x005b
>+#define mmSDMA3_CRD_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA3_GPU_IOV_VIOLATION_LOG                                                                  0x005d
>+#define mmSDMA3_GPU_IOV_VIOLATION_LOG_BASE_IDX                                                         1
>+#define mmSDMA3_ULV_CNTL                                                                               0x005e
>+#define mmSDMA3_ULV_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA3_EA_DBIT_ADDR_DATA                                                                      0x0060
>+#define mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX                                                             1
>+#define mmSDMA3_EA_DBIT_ADDR_INDEX                                                                     0x0061
>+#define mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            1
>+#define mmSDMA3_GPU_IOV_VIOLATION_LOG2                                                                 0x0062
>+#define mmSDMA3_GPU_IOV_VIOLATION_LOG2_BASE_IDX                                                        1
>+#define mmSDMA3_GFX_RB_CNTL                                                                            0x0080
>+#define mmSDMA3_GFX_RB_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA3_GFX_RB_BASE                                                                            0x0081
>+#define mmSDMA3_GFX_RB_BASE_BASE_IDX                                                                   1
>+#define mmSDMA3_GFX_RB_BASE_HI                                                                         0x0082
>+#define mmSDMA3_GFX_RB_BASE_HI_BASE_IDX                                                                1
>+#define mmSDMA3_GFX_RB_RPTR                                                                            0x0083
>+#define mmSDMA3_GFX_RB_RPTR_BASE_IDX                                                                   1
>+#define mmSDMA3_GFX_RB_RPTR_HI                                                                         0x0084
>+#define mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX                                                                1
>+#define mmSDMA3_GFX_RB_WPTR                                                                            0x0085
>+#define mmSDMA3_GFX_RB_WPTR_BASE_IDX                                                                   1
>+#define mmSDMA3_GFX_RB_WPTR_HI                                                                         0x0086
>+#define mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX                                                                1
>+#define mmSDMA3_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
>+#define mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         1
>+#define mmSDMA3_GFX_RB_RPTR_ADDR_HI                                                                    0x0088
>+#define mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           1
>+#define mmSDMA3_GFX_RB_RPTR_ADDR_LO                                                                    0x0089
>+#define mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           1
>+#define mmSDMA3_GFX_IB_CNTL                                                                            0x008a
>+#define mmSDMA3_GFX_IB_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA3_GFX_IB_RPTR                                                                            0x008b
>+#define mmSDMA3_GFX_IB_RPTR_BASE_IDX                                                                   1
>+#define mmSDMA3_GFX_IB_OFFSET                                                                          0x008c
>+#define mmSDMA3_GFX_IB_OFFSET_BASE_IDX                                                                 1
>+#define mmSDMA3_GFX_IB_BASE_LO                                                                         0x008d
>+#define mmSDMA3_GFX_IB_BASE_LO_BASE_IDX                                                                1
>+#define mmSDMA3_GFX_IB_BASE_HI                                                                         0x008e
>+#define mmSDMA3_GFX_IB_BASE_HI_BASE_IDX                                                                1
>+#define mmSDMA3_GFX_IB_SIZE                                                                            0x008f
>+#define mmSDMA3_GFX_IB_SIZE_BASE_IDX                                                                   1
>+#define mmSDMA3_GFX_SKIP_CNTL                                                                          0x0090
>+#define mmSDMA3_GFX_SKIP_CNTL_BASE_IDX                                                                 1
>+#define mmSDMA3_GFX_CONTEXT_STATUS                                                                     0x0091
>+#define mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX                                                            1
>+#define mmSDMA3_GFX_DOORBELL                                                                           0x0092
>+#define mmSDMA3_GFX_DOORBELL_BASE_IDX                                                                  1
>+#define mmSDMA3_GFX_CONTEXT_CNTL                                                                       0x0093
>+#define mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_GFX_STATUS                                                                             0x00a8
>+#define mmSDMA3_GFX_STATUS_BASE_IDX                                                                    1
>+#define mmSDMA3_GFX_DOORBELL_LOG                                                                       0x00a9
>+#define mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX                                                              1
>+#define mmSDMA3_GFX_WATERMARK                                                                          0x00aa
>+#define mmSDMA3_GFX_WATERMARK_BASE_IDX                                                                 1
>+#define mmSDMA3_GFX_DOORBELL_OFFSET                                                                    0x00ab
>+#define mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX                                                           1
>+#define mmSDMA3_GFX_CSA_ADDR_LO                                                                        0x00ac
>+#define mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX                                                               1
>+#define mmSDMA3_GFX_CSA_ADDR_HI                                                                        0x00ad
>+#define mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_GFX_IB_SUB_REMAIN                                                                      0x00af
>+#define mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX                                                             1
>+#define mmSDMA3_GFX_PREEMPT                                                                            0x00b0
>+#define mmSDMA3_GFX_PREEMPT_BASE_IDX                                                                   1
>+#define mmSDMA3_GFX_DUMMY_REG                                                                          0x00b1
>+#define mmSDMA3_GFX_DUMMY_REG_BASE_IDX                                                                 1
>+#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x00b2
>+#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      1
>+#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x00b3
>+#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      1
>+#define mmSDMA3_GFX_RB_AQL_CNTL                                                                        0x00b4
>+#define mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX                                                               1
>+#define mmSDMA3_GFX_MINOR_PTR_UPDATE                                                                   0x00b5
>+#define mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          1
>+#define mmSDMA3_GFX_MIDCMD_DATA0                                                                       0x00c0
>+#define mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX                                                              1
>+#define mmSDMA3_GFX_MIDCMD_DATA1                                                                       0x00c1
>+#define mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX                                                              1
>+#define mmSDMA3_GFX_MIDCMD_DATA2                                                                       0x00c2
>+#define mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX                                                              1
>+#define mmSDMA3_GFX_MIDCMD_DATA3                                                                       0x00c3
>+#define mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX                                                              1
>+#define mmSDMA3_GFX_MIDCMD_DATA4                                                                       0x00c4
>+#define mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX                                                              1
>+#define mmSDMA3_GFX_MIDCMD_DATA5                                                                       0x00c5
>+#define mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX                                                              1
>+#define mmSDMA3_GFX_MIDCMD_DATA6                                                                       0x00c6
>+#define mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX                                                              1
>+#define mmSDMA3_GFX_MIDCMD_DATA7                                                                       0x00c7
>+#define mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX                                                              1
>+#define mmSDMA3_GFX_MIDCMD_DATA8                                                                       0x00c8
>+#define mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX                                                              1
>+#define mmSDMA3_GFX_MIDCMD_CNTL                                                                        0x00c9
>+#define mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX                                                               1
>+#define mmSDMA3_PAGE_RB_CNTL                                                                           0x00d8
>+#define mmSDMA3_PAGE_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_PAGE_RB_BASE                                                                           0x00d9
>+#define mmSDMA3_PAGE_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA3_PAGE_RB_BASE_HI                                                                        0x00da
>+#define mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_PAGE_RB_RPTR                                                                           0x00db
>+#define mmSDMA3_PAGE_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_PAGE_RB_RPTR_HI                                                                        0x00dc
>+#define mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_PAGE_RB_WPTR                                                                           0x00dd
>+#define mmSDMA3_PAGE_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_PAGE_RB_WPTR_HI                                                                        0x00de
>+#define mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL                                                                 0x00df
>+#define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA3_PAGE_RB_RPTR_ADDR_HI                                                                   0x00e0
>+#define mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA3_PAGE_RB_RPTR_ADDR_LO                                                                   0x00e1
>+#define mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA3_PAGE_IB_CNTL                                                                           0x00e2
>+#define mmSDMA3_PAGE_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_PAGE_IB_RPTR                                                                           0x00e3
>+#define mmSDMA3_PAGE_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_PAGE_IB_OFFSET                                                                         0x00e4
>+#define mmSDMA3_PAGE_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA3_PAGE_IB_BASE_LO                                                                        0x00e5
>+#define mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA3_PAGE_IB_BASE_HI                                                                        0x00e6
>+#define mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_PAGE_IB_SIZE                                                                           0x00e7
>+#define mmSDMA3_PAGE_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA3_PAGE_SKIP_CNTL                                                                         0x00e8
>+#define mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA3_PAGE_CONTEXT_STATUS                                                                    0x00e9
>+#define mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA3_PAGE_DOORBELL                                                                          0x00ea
>+#define mmSDMA3_PAGE_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA3_PAGE_STATUS                                                                            0x0100
>+#define mmSDMA3_PAGE_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA3_PAGE_DOORBELL_LOG                                                                      0x0101
>+#define mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA3_PAGE_WATERMARK                                                                         0x0102
>+#define mmSDMA3_PAGE_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA3_PAGE_DOORBELL_OFFSET                                                                   0x0103
>+#define mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA3_PAGE_CSA_ADDR_LO                                                                       0x0104
>+#define mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA3_PAGE_CSA_ADDR_HI                                                                       0x0105
>+#define mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA3_PAGE_IB_SUB_REMAIN                                                                     0x0107
>+#define mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA3_PAGE_PREEMPT                                                                           0x0108
>+#define mmSDMA3_PAGE_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA3_PAGE_DUMMY_REG                                                                         0x0109
>+#define mmSDMA3_PAGE_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x010a
>+#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x010b
>+#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA3_PAGE_RB_AQL_CNTL                                                                       0x010c
>+#define mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_PAGE_MINOR_PTR_UPDATE                                                                  0x010d
>+#define mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA3_PAGE_MIDCMD_DATA0                                                                      0x0118
>+#define mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA3_PAGE_MIDCMD_DATA1                                                                      0x0119
>+#define mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA3_PAGE_MIDCMD_DATA2                                                                      0x011a
>+#define mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA3_PAGE_MIDCMD_DATA3                                                                      0x011b
>+#define mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA3_PAGE_MIDCMD_DATA4                                                                      0x011c
>+#define mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA3_PAGE_MIDCMD_DATA5                                                                      0x011d
>+#define mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA3_PAGE_MIDCMD_DATA6                                                                      0x011e
>+#define mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA3_PAGE_MIDCMD_DATA7                                                                      0x011f
>+#define mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA3_PAGE_MIDCMD_DATA8                                                                      0x0120
>+#define mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA3_PAGE_MIDCMD_CNTL                                                                       0x0121
>+#define mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC0_RB_CNTL                                                                           0x0130
>+#define mmSDMA3_RLC0_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC0_RB_BASE                                                                           0x0131
>+#define mmSDMA3_RLC0_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC0_RB_BASE_HI                                                                        0x0132
>+#define mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC0_RB_RPTR                                                                           0x0133
>+#define mmSDMA3_RLC0_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC0_RB_RPTR_HI                                                                        0x0134
>+#define mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC0_RB_WPTR                                                                           0x0135
>+#define mmSDMA3_RLC0_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC0_RB_WPTR_HI                                                                        0x0136
>+#define mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0137
>+#define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA3_RLC0_RB_RPTR_ADDR_HI                                                                   0x0138
>+#define mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA3_RLC0_RB_RPTR_ADDR_LO                                                                   0x0139
>+#define mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA3_RLC0_IB_CNTL                                                                           0x013a
>+#define mmSDMA3_RLC0_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC0_IB_RPTR                                                                           0x013b
>+#define mmSDMA3_RLC0_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC0_IB_OFFSET                                                                         0x013c
>+#define mmSDMA3_RLC0_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA3_RLC0_IB_BASE_LO                                                                        0x013d
>+#define mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA3_RLC0_IB_BASE_HI                                                                        0x013e
>+#define mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC0_IB_SIZE                                                                           0x013f
>+#define mmSDMA3_RLC0_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC0_SKIP_CNTL                                                                         0x0140
>+#define mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA3_RLC0_CONTEXT_STATUS                                                                    0x0141
>+#define mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA3_RLC0_DOORBELL                                                                          0x0142
>+#define mmSDMA3_RLC0_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA3_RLC0_STATUS                                                                            0x0158
>+#define mmSDMA3_RLC0_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA3_RLC0_DOORBELL_LOG                                                                      0x0159
>+#define mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA3_RLC0_WATERMARK                                                                         0x015a
>+#define mmSDMA3_RLC0_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA3_RLC0_DOORBELL_OFFSET                                                                   0x015b
>+#define mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA3_RLC0_CSA_ADDR_LO                                                                       0x015c
>+#define mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA3_RLC0_CSA_ADDR_HI                                                                       0x015d
>+#define mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA3_RLC0_IB_SUB_REMAIN                                                                     0x015f
>+#define mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA3_RLC0_PREEMPT                                                                           0x0160
>+#define mmSDMA3_RLC0_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC0_DUMMY_REG                                                                         0x0161
>+#define mmSDMA3_RLC0_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0162
>+#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0163
>+#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA3_RLC0_RB_AQL_CNTL                                                                       0x0164
>+#define mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC0_MINOR_PTR_UPDATE                                                                  0x0165
>+#define mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA3_RLC0_MIDCMD_DATA0                                                                      0x0170
>+#define mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA3_RLC0_MIDCMD_DATA1                                                                      0x0171
>+#define mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA3_RLC0_MIDCMD_DATA2                                                                      0x0172
>+#define mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA3_RLC0_MIDCMD_DATA3                                                                      0x0173
>+#define mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA3_RLC0_MIDCMD_DATA4                                                                      0x0174
>+#define mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA3_RLC0_MIDCMD_DATA5                                                                      0x0175
>+#define mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA3_RLC0_MIDCMD_DATA6                                                                      0x0176
>+#define mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA3_RLC0_MIDCMD_DATA7                                                                      0x0177
>+#define mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA3_RLC0_MIDCMD_DATA8                                                                      0x0178
>+#define mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA3_RLC0_MIDCMD_CNTL                                                                       0x0179
>+#define mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC1_RB_CNTL                                                                           0x0188
>+#define mmSDMA3_RLC1_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC1_RB_BASE                                                                           0x0189
>+#define mmSDMA3_RLC1_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC1_RB_BASE_HI                                                                        0x018a
>+#define mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC1_RB_RPTR                                                                           0x018b
>+#define mmSDMA3_RLC1_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC1_RB_RPTR_HI                                                                        0x018c
>+#define mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC1_RB_WPTR                                                                           0x018d
>+#define mmSDMA3_RLC1_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC1_RB_WPTR_HI                                                                        0x018e
>+#define mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL                                                                 0x018f
>+#define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA3_RLC1_RB_RPTR_ADDR_HI                                                                   0x0190
>+#define mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA3_RLC1_RB_RPTR_ADDR_LO                                                                   0x0191
>+#define mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA3_RLC1_IB_CNTL                                                                           0x0192
>+#define mmSDMA3_RLC1_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC1_IB_RPTR                                                                           0x0193
>+#define mmSDMA3_RLC1_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC1_IB_OFFSET                                                                         0x0194
>+#define mmSDMA3_RLC1_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA3_RLC1_IB_BASE_LO                                                                        0x0195
>+#define mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA3_RLC1_IB_BASE_HI                                                                        0x0196
>+#define mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC1_IB_SIZE                                                                           0x0197
>+#define mmSDMA3_RLC1_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC1_SKIP_CNTL                                                                         0x0198
>+#define mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA3_RLC1_CONTEXT_STATUS                                                                    0x0199
>+#define mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA3_RLC1_DOORBELL                                                                          0x019a
>+#define mmSDMA3_RLC1_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA3_RLC1_STATUS                                                                            0x01b0
>+#define mmSDMA3_RLC1_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA3_RLC1_DOORBELL_LOG                                                                      0x01b1
>+#define mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA3_RLC1_WATERMARK                                                                         0x01b2
>+#define mmSDMA3_RLC1_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA3_RLC1_DOORBELL_OFFSET                                                                   0x01b3
>+#define mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA3_RLC1_CSA_ADDR_LO                                                                       0x01b4
>+#define mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA3_RLC1_CSA_ADDR_HI                                                                       0x01b5
>+#define mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA3_RLC1_IB_SUB_REMAIN                                                                     0x01b7
>+#define mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA3_RLC1_PREEMPT                                                                           0x01b8
>+#define mmSDMA3_RLC1_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC1_DUMMY_REG                                                                         0x01b9
>+#define mmSDMA3_RLC1_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x01ba
>+#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x01bb
>+#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA3_RLC1_RB_AQL_CNTL                                                                       0x01bc
>+#define mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC1_MINOR_PTR_UPDATE                                                                  0x01bd
>+#define mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA3_RLC1_MIDCMD_DATA0                                                                      0x01c8
>+#define mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA3_RLC1_MIDCMD_DATA1                                                                      0x01c9
>+#define mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA3_RLC1_MIDCMD_DATA2                                                                      0x01ca
>+#define mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA3_RLC1_MIDCMD_DATA3                                                                      0x01cb
>+#define mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA3_RLC1_MIDCMD_DATA4                                                                      0x01cc
>+#define mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA3_RLC1_MIDCMD_DATA5                                                                      0x01cd
>+#define mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA3_RLC1_MIDCMD_DATA6                                                                      0x01ce
>+#define mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA3_RLC1_MIDCMD_DATA7                                                                      0x01cf
>+#define mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA3_RLC1_MIDCMD_DATA8                                                                      0x01d0
>+#define mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA3_RLC1_MIDCMD_CNTL                                                                       0x01d1
>+#define mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC2_RB_CNTL                                                                           0x01e0
>+#define mmSDMA3_RLC2_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC2_RB_BASE                                                                           0x01e1
>+#define mmSDMA3_RLC2_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC2_RB_BASE_HI                                                                        0x01e2
>+#define mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC2_RB_RPTR                                                                           0x01e3
>+#define mmSDMA3_RLC2_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC2_RB_RPTR_HI                                                                        0x01e4
>+#define mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC2_RB_WPTR                                                                           0x01e5
>+#define mmSDMA3_RLC2_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC2_RB_WPTR_HI                                                                        0x01e6
>+#define mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL                                                                 0x01e7
>+#define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA3_RLC2_RB_RPTR_ADDR_HI                                                                   0x01e8
>+#define mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA3_RLC2_RB_RPTR_ADDR_LO                                                                   0x01e9
>+#define mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA3_RLC2_IB_CNTL                                                                           0x01ea
>+#define mmSDMA3_RLC2_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC2_IB_RPTR                                                                           0x01eb
>+#define mmSDMA3_RLC2_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC2_IB_OFFSET                                                                         0x01ec
>+#define mmSDMA3_RLC2_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA3_RLC2_IB_BASE_LO                                                                        0x01ed
>+#define mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA3_RLC2_IB_BASE_HI                                                                        0x01ee
>+#define mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC2_IB_SIZE                                                                           0x01ef
>+#define mmSDMA3_RLC2_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC2_SKIP_CNTL                                                                         0x01f0
>+#define mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA3_RLC2_CONTEXT_STATUS                                                                    0x01f1
>+#define mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA3_RLC2_DOORBELL                                                                          0x01f2
>+#define mmSDMA3_RLC2_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA3_RLC2_STATUS                                                                            0x0208
>+#define mmSDMA3_RLC2_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA3_RLC2_DOORBELL_LOG                                                                      0x0209
>+#define mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA3_RLC2_WATERMARK                                                                         0x020a
>+#define mmSDMA3_RLC2_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA3_RLC2_DOORBELL_OFFSET                                                                   0x020b
>+#define mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA3_RLC2_CSA_ADDR_LO                                                                       0x020c
>+#define mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA3_RLC2_CSA_ADDR_HI                                                                       0x020d
>+#define mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA3_RLC2_IB_SUB_REMAIN                                                                     0x020f
>+#define mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA3_RLC2_PREEMPT                                                                           0x0210
>+#define mmSDMA3_RLC2_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC2_DUMMY_REG                                                                         0x0211
>+#define mmSDMA3_RLC2_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0212
>+#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0213
>+#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA3_RLC2_RB_AQL_CNTL                                                                       0x0214
>+#define mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC2_MINOR_PTR_UPDATE                                                                  0x0215
>+#define mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA3_RLC2_MIDCMD_DATA0                                                                      0x0220
>+#define mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA3_RLC2_MIDCMD_DATA1                                                                      0x0221
>+#define mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA3_RLC2_MIDCMD_DATA2                                                                      0x0222
>+#define mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA3_RLC2_MIDCMD_DATA3                                                                      0x0223
>+#define mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA3_RLC2_MIDCMD_DATA4                                                                      0x0224
>+#define mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA3_RLC2_MIDCMD_DATA5                                                                      0x0225
>+#define mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA3_RLC2_MIDCMD_DATA6                                                                      0x0226
>+#define mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA3_RLC2_MIDCMD_DATA7                                                                      0x0227
>+#define mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA3_RLC2_MIDCMD_DATA8                                                                      0x0228
>+#define mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA3_RLC2_MIDCMD_CNTL                                                                       0x0229
>+#define mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC3_RB_CNTL                                                                           0x0238
>+#define mmSDMA3_RLC3_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC3_RB_BASE                                                                           0x0239
>+#define mmSDMA3_RLC3_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC3_RB_BASE_HI                                                                        0x023a
>+#define mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC3_RB_RPTR                                                                           0x023b
>+#define mmSDMA3_RLC3_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC3_RB_RPTR_HI                                                                        0x023c
>+#define mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC3_RB_WPTR                                                                           0x023d
>+#define mmSDMA3_RLC3_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC3_RB_WPTR_HI                                                                        0x023e
>+#define mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL                                                                 0x023f
>+#define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA3_RLC3_RB_RPTR_ADDR_HI                                                                   0x0240
>+#define mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA3_RLC3_RB_RPTR_ADDR_LO                                                                   0x0241
>+#define mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA3_RLC3_IB_CNTL                                                                           0x0242
>+#define mmSDMA3_RLC3_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC3_IB_RPTR                                                                           0x0243
>+#define mmSDMA3_RLC3_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC3_IB_OFFSET                                                                         0x0244
>+#define mmSDMA3_RLC3_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA3_RLC3_IB_BASE_LO                                                                        0x0245
>+#define mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA3_RLC3_IB_BASE_HI                                                                        0x0246
>+#define mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC3_IB_SIZE                                                                           0x0247
>+#define mmSDMA3_RLC3_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC3_SKIP_CNTL                                                                         0x0248
>+#define mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA3_RLC3_CONTEXT_STATUS                                                                    0x0249
>+#define mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA3_RLC3_DOORBELL                                                                          0x024a
>+#define mmSDMA3_RLC3_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA3_RLC3_STATUS                                                                            0x0260
>+#define mmSDMA3_RLC3_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA3_RLC3_DOORBELL_LOG                                                                      0x0261
>+#define mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA3_RLC3_WATERMARK                                                                         0x0262
>+#define mmSDMA3_RLC3_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA3_RLC3_DOORBELL_OFFSET                                                                   0x0263
>+#define mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA3_RLC3_CSA_ADDR_LO                                                                       0x0264
>+#define mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA3_RLC3_CSA_ADDR_HI                                                                       0x0265
>+#define mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA3_RLC3_IB_SUB_REMAIN                                                                     0x0267
>+#define mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA3_RLC3_PREEMPT                                                                           0x0268
>+#define mmSDMA3_RLC3_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC3_DUMMY_REG                                                                         0x0269
>+#define mmSDMA3_RLC3_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x026a
>+#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x026b
>+#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA3_RLC3_RB_AQL_CNTL                                                                       0x026c
>+#define mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC3_MINOR_PTR_UPDATE                                                                  0x026d
>+#define mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA3_RLC3_MIDCMD_DATA0                                                                      0x0278
>+#define mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA3_RLC3_MIDCMD_DATA1                                                                      0x0279
>+#define mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA3_RLC3_MIDCMD_DATA2                                                                      0x027a
>+#define mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA3_RLC3_MIDCMD_DATA3                                                                      0x027b
>+#define mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA3_RLC3_MIDCMD_DATA4                                                                      0x027c
>+#define mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA3_RLC3_MIDCMD_DATA5                                                                      0x027d
>+#define mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA3_RLC3_MIDCMD_DATA6                                                                      0x027e
>+#define mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA3_RLC3_MIDCMD_DATA7                                                                      0x027f
>+#define mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA3_RLC3_MIDCMD_DATA8                                                                      0x0280
>+#define mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA3_RLC3_MIDCMD_CNTL                                                                       0x0281
>+#define mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC4_RB_CNTL                                                                           0x0290
>+#define mmSDMA3_RLC4_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC4_RB_BASE                                                                           0x0291
>+#define mmSDMA3_RLC4_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC4_RB_BASE_HI                                                                        0x0292
>+#define mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC4_RB_RPTR                                                                           0x0293
>+#define mmSDMA3_RLC4_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC4_RB_RPTR_HI                                                                        0x0294
>+#define mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC4_RB_WPTR                                                                           0x0295
>+#define mmSDMA3_RLC4_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC4_RB_WPTR_HI                                                                        0x0296
>+#define mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL                                                                 0x0297
>+#define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA3_RLC4_RB_RPTR_ADDR_HI                                                                   0x0298
>+#define mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA3_RLC4_RB_RPTR_ADDR_LO                                                                   0x0299
>+#define mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA3_RLC4_IB_CNTL                                                                           0x029a
>+#define mmSDMA3_RLC4_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC4_IB_RPTR                                                                           0x029b
>+#define mmSDMA3_RLC4_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC4_IB_OFFSET                                                                         0x029c
>+#define mmSDMA3_RLC4_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA3_RLC4_IB_BASE_LO                                                                        0x029d
>+#define mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA3_RLC4_IB_BASE_HI                                                                        0x029e
>+#define mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC4_IB_SIZE                                                                           0x029f
>+#define mmSDMA3_RLC4_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC4_SKIP_CNTL                                                                         0x02a0
>+#define mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA3_RLC4_CONTEXT_STATUS                                                                    0x02a1
>+#define mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA3_RLC4_DOORBELL                                                                          0x02a2
>+#define mmSDMA3_RLC4_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA3_RLC4_STATUS                                                                            0x02b8
>+#define mmSDMA3_RLC4_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA3_RLC4_DOORBELL_LOG                                                                      0x02b9
>+#define mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA3_RLC4_WATERMARK                                                                         0x02ba
>+#define mmSDMA3_RLC4_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA3_RLC4_DOORBELL_OFFSET                                                                   0x02bb
>+#define mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA3_RLC4_CSA_ADDR_LO                                                                       0x02bc
>+#define mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA3_RLC4_CSA_ADDR_HI                                                                       0x02bd
>+#define mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA3_RLC4_IB_SUB_REMAIN                                                                     0x02bf
>+#define mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA3_RLC4_PREEMPT                                                                           0x02c0
>+#define mmSDMA3_RLC4_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC4_DUMMY_REG                                                                         0x02c1
>+#define mmSDMA3_RLC4_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x02c2
>+#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x02c3
>+#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA3_RLC4_RB_AQL_CNTL                                                                       0x02c4
>+#define mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC4_MINOR_PTR_UPDATE                                                                  0x02c5
>+#define mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA3_RLC4_MIDCMD_DATA0                                                                      0x02d0
>+#define mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA3_RLC4_MIDCMD_DATA1                                                                      0x02d1
>+#define mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA3_RLC4_MIDCMD_DATA2                                                                      0x02d2
>+#define mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA3_RLC4_MIDCMD_DATA3                                                                      0x02d3
>+#define mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA3_RLC4_MIDCMD_DATA4                                                                      0x02d4
>+#define mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA3_RLC4_MIDCMD_DATA5                                                                      0x02d5
>+#define mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA3_RLC4_MIDCMD_DATA6                                                                      0x02d6
>+#define mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA3_RLC4_MIDCMD_DATA7                                                                      0x02d7
>+#define mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA3_RLC4_MIDCMD_DATA8                                                                      0x02d8
>+#define mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA3_RLC4_MIDCMD_CNTL                                                                       0x02d9
>+#define mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC5_RB_CNTL                                                                           0x02e8
>+#define mmSDMA3_RLC5_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC5_RB_BASE                                                                           0x02e9
>+#define mmSDMA3_RLC5_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC5_RB_BASE_HI                                                                        0x02ea
>+#define mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC5_RB_RPTR                                                                           0x02eb
>+#define mmSDMA3_RLC5_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC5_RB_RPTR_HI                                                                        0x02ec
>+#define mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC5_RB_WPTR                                                                           0x02ed
>+#define mmSDMA3_RLC5_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC5_RB_WPTR_HI                                                                        0x02ee
>+#define mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL                                                                 0x02ef
>+#define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA3_RLC5_RB_RPTR_ADDR_HI                                                                   0x02f0
>+#define mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA3_RLC5_RB_RPTR_ADDR_LO                                                                   0x02f1
>+#define mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA3_RLC5_IB_CNTL                                                                           0x02f2
>+#define mmSDMA3_RLC5_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC5_IB_RPTR                                                                           0x02f3
>+#define mmSDMA3_RLC5_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC5_IB_OFFSET                                                                         0x02f4
>+#define mmSDMA3_RLC5_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA3_RLC5_IB_BASE_LO                                                                        0x02f5
>+#define mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA3_RLC5_IB_BASE_HI                                                                        0x02f6
>+#define mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC5_IB_SIZE                                                                           0x02f7
>+#define mmSDMA3_RLC5_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC5_SKIP_CNTL                                                                         0x02f8
>+#define mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA3_RLC5_CONTEXT_STATUS                                                                    0x02f9
>+#define mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA3_RLC5_DOORBELL                                                                          0x02fa
>+#define mmSDMA3_RLC5_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA3_RLC5_STATUS                                                                            0x0310
>+#define mmSDMA3_RLC5_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA3_RLC5_DOORBELL_LOG                                                                      0x0311
>+#define mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA3_RLC5_WATERMARK                                                                         0x0312
>+#define mmSDMA3_RLC5_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA3_RLC5_DOORBELL_OFFSET                                                                   0x0313
>+#define mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA3_RLC5_CSA_ADDR_LO                                                                       0x0314
>+#define mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA3_RLC5_CSA_ADDR_HI                                                                       0x0315
>+#define mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA3_RLC5_IB_SUB_REMAIN                                                                     0x0317
>+#define mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA3_RLC5_PREEMPT                                                                           0x0318
>+#define mmSDMA3_RLC5_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC5_DUMMY_REG                                                                         0x0319
>+#define mmSDMA3_RLC5_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x031a
>+#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x031b
>+#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA3_RLC5_RB_AQL_CNTL                                                                       0x031c
>+#define mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC5_MINOR_PTR_UPDATE                                                                  0x031d
>+#define mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA3_RLC5_MIDCMD_DATA0                                                                      0x0328
>+#define mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA3_RLC5_MIDCMD_DATA1                                                                      0x0329
>+#define mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA3_RLC5_MIDCMD_DATA2                                                                      0x032a
>+#define mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA3_RLC5_MIDCMD_DATA3                                                                      0x032b
>+#define mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA3_RLC5_MIDCMD_DATA4                                                                      0x032c
>+#define mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA3_RLC5_MIDCMD_DATA5                                                                      0x032d
>+#define mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA3_RLC5_MIDCMD_DATA6                                                                      0x032e
>+#define mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA3_RLC5_MIDCMD_DATA7                                                                      0x032f
>+#define mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA3_RLC5_MIDCMD_DATA8                                                                      0x0330
>+#define mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA3_RLC5_MIDCMD_CNTL                                                                       0x0331
>+#define mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC6_RB_CNTL                                                                           0x0340
>+#define mmSDMA3_RLC6_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC6_RB_BASE                                                                           0x0341
>+#define mmSDMA3_RLC6_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC6_RB_BASE_HI                                                                        0x0342
>+#define mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC6_RB_RPTR                                                                           0x0343
>+#define mmSDMA3_RLC6_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC6_RB_RPTR_HI                                                                        0x0344
>+#define mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC6_RB_WPTR                                                                           0x0345
>+#define mmSDMA3_RLC6_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC6_RB_WPTR_HI                                                                        0x0346
>+#define mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0347
>+#define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA3_RLC6_RB_RPTR_ADDR_HI                                                                   0x0348
>+#define mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA3_RLC6_RB_RPTR_ADDR_LO                                                                   0x0349
>+#define mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA3_RLC6_IB_CNTL                                                                           0x034a
>+#define mmSDMA3_RLC6_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC6_IB_RPTR                                                                           0x034b
>+#define mmSDMA3_RLC6_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC6_IB_OFFSET                                                                         0x034c
>+#define mmSDMA3_RLC6_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA3_RLC6_IB_BASE_LO                                                                        0x034d
>+#define mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA3_RLC6_IB_BASE_HI                                                                        0x034e
>+#define mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC6_IB_SIZE                                                                           0x034f
>+#define mmSDMA3_RLC6_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC6_SKIP_CNTL                                                                         0x0350
>+#define mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA3_RLC6_CONTEXT_STATUS                                                                    0x0351
>+#define mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA3_RLC6_DOORBELL                                                                          0x0352
>+#define mmSDMA3_RLC6_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA3_RLC6_STATUS                                                                            0x0368
>+#define mmSDMA3_RLC6_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA3_RLC6_DOORBELL_LOG                                                                      0x0369
>+#define mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA3_RLC6_WATERMARK                                                                         0x036a
>+#define mmSDMA3_RLC6_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA3_RLC6_DOORBELL_OFFSET                                                                   0x036b
>+#define mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA3_RLC6_CSA_ADDR_LO                                                                       0x036c
>+#define mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA3_RLC6_CSA_ADDR_HI                                                                       0x036d
>+#define mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA3_RLC6_IB_SUB_REMAIN                                                                     0x036f
>+#define mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA3_RLC6_PREEMPT                                                                           0x0370
>+#define mmSDMA3_RLC6_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC6_DUMMY_REG                                                                         0x0371
>+#define mmSDMA3_RLC6_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x0372
>+#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x0373
>+#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA3_RLC6_RB_AQL_CNTL                                                                       0x0374
>+#define mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC6_MINOR_PTR_UPDATE                                                                  0x0375
>+#define mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA3_RLC6_MIDCMD_DATA0                                                                      0x0380
>+#define mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA3_RLC6_MIDCMD_DATA1                                                                      0x0381
>+#define mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA3_RLC6_MIDCMD_DATA2                                                                      0x0382
>+#define mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA3_RLC6_MIDCMD_DATA3                                                                      0x0383
>+#define mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA3_RLC6_MIDCMD_DATA4                                                                      0x0384
>+#define mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA3_RLC6_MIDCMD_DATA5                                                                      0x0385
>+#define mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA3_RLC6_MIDCMD_DATA6                                                                      0x0386
>+#define mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA3_RLC6_MIDCMD_DATA7                                                                      0x0387
>+#define mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA3_RLC6_MIDCMD_DATA8                                                                      0x0388
>+#define mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA3_RLC6_MIDCMD_CNTL                                                                       0x0389
>+#define mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC7_RB_CNTL                                                                           0x0398
>+#define mmSDMA3_RLC7_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC7_RB_BASE                                                                           0x0399
>+#define mmSDMA3_RLC7_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC7_RB_BASE_HI                                                                        0x039a
>+#define mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC7_RB_RPTR                                                                           0x039b
>+#define mmSDMA3_RLC7_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC7_RB_RPTR_HI                                                                        0x039c
>+#define mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC7_RB_WPTR                                                                           0x039d
>+#define mmSDMA3_RLC7_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC7_RB_WPTR_HI                                                                        0x039e
>+#define mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL                                                                 0x039f
>+#define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA3_RLC7_RB_RPTR_ADDR_HI                                                                   0x03a0
>+#define mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA3_RLC7_RB_RPTR_ADDR_LO                                                                   0x03a1
>+#define mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA3_RLC7_IB_CNTL                                                                           0x03a2
>+#define mmSDMA3_RLC7_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC7_IB_RPTR                                                                           0x03a3
>+#define mmSDMA3_RLC7_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC7_IB_OFFSET                                                                         0x03a4
>+#define mmSDMA3_RLC7_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA3_RLC7_IB_BASE_LO                                                                        0x03a5
>+#define mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA3_RLC7_IB_BASE_HI                                                                        0x03a6
>+#define mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA3_RLC7_IB_SIZE                                                                           0x03a7
>+#define mmSDMA3_RLC7_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC7_SKIP_CNTL                                                                         0x03a8
>+#define mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA3_RLC7_CONTEXT_STATUS                                                                    0x03a9
>+#define mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA3_RLC7_DOORBELL                                                                          0x03aa
>+#define mmSDMA3_RLC7_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA3_RLC7_STATUS                                                                            0x03c0
>+#define mmSDMA3_RLC7_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA3_RLC7_DOORBELL_LOG                                                                      0x03c1
>+#define mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA3_RLC7_WATERMARK                                                                         0x03c2
>+#define mmSDMA3_RLC7_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA3_RLC7_DOORBELL_OFFSET                                                                   0x03c3
>+#define mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA3_RLC7_CSA_ADDR_LO                                                                       0x03c4
>+#define mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA3_RLC7_CSA_ADDR_HI                                                                       0x03c5
>+#define mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA3_RLC7_IB_SUB_REMAIN                                                                     0x03c7
>+#define mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA3_RLC7_PREEMPT                                                                           0x03c8
>+#define mmSDMA3_RLC7_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA3_RLC7_DUMMY_REG                                                                         0x03c9
>+#define mmSDMA3_RLC7_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x03ca
>+#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x03cb
>+#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA3_RLC7_RB_AQL_CNTL                                                                       0x03cc
>+#define mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA3_RLC7_MINOR_PTR_UPDATE                                                                  0x03cd
>+#define mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA3_RLC7_MIDCMD_DATA0                                                                      0x03d8
>+#define mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA3_RLC7_MIDCMD_DATA1                                                                      0x03d9
>+#define mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA3_RLC7_MIDCMD_DATA2                                                                      0x03da
>+#define mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA3_RLC7_MIDCMD_DATA3                                                                      0x03db
>+#define mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA3_RLC7_MIDCMD_DATA4                                                                      0x03dc
>+#define mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA3_RLC7_MIDCMD_DATA5                                                                      0x03dd
>+#define mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA3_RLC7_MIDCMD_DATA6                                                                      0x03de
>+#define mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA3_RLC7_MIDCMD_DATA7                                                                      0x03df
>+#define mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA3_RLC7_MIDCMD_DATA8                                                                      0x03e0
>+#define mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA3_RLC7_MIDCMD_CNTL                                                                       0x03e1
>+#define mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX                                                              1
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma3/sdma3_4_2_2_sh_mask.h	2019-08-31 15:01:11.932736175 -0500
>@@ -0,0 +1,2956 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma3_4_2_2_SH_MASK_HEADER
>+#define _sdma3_4_2_2_SH_MASK_HEADER
>+
>+
>+// addressBlock: sdma3_sdma3dec
>+//SDMA3_UCODE_ADDR
>+#define SDMA3_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
>+#define SDMA3_UCODE_ADDR__VALUE_MASK                                                                          0x00001FFFL
>+//SDMA3_UCODE_DATA
>+#define SDMA3_UCODE_DATA__VALUE__SHIFT                                                                        0x0
>+#define SDMA3_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
>+//SDMA3_VM_CNTL
>+#define SDMA3_VM_CNTL__CMD__SHIFT                                                                             0x0
>+#define SDMA3_VM_CNTL__CMD_MASK                                                                               0x0000000FL
>+//SDMA3_VM_CTX_LO
>+#define SDMA3_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
>+#define SDMA3_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
>+//SDMA3_VM_CTX_HI
>+#define SDMA3_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
>+#define SDMA3_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
>+//SDMA3_ACTIVE_FCN_ID
>+#define SDMA3_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
>+#define SDMA3_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x4
>+#define SDMA3_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
>+#define SDMA3_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000000FL
>+#define SDMA3_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFF0L
>+#define SDMA3_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
>+//SDMA3_VM_CTX_CNTL
>+#define SDMA3_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
>+#define SDMA3_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
>+#define SDMA3_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
>+#define SDMA3_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
>+//SDMA3_VIRT_RESET_REQ
>+#define SDMA3_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
>+#define SDMA3_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
>+#define SDMA3_VIRT_RESET_REQ__VF_MASK                                                                         0x0000FFFFL
>+#define SDMA3_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
>+//SDMA3_VF_ENABLE
>+#define SDMA3_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
>+#define SDMA3_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
>+//SDMA3_CONTEXT_REG_TYPE0
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_CNTL__SHIFT                                                     0x0
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE__SHIFT                                                     0x1
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_HI__SHIFT                                                  0x2
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR__SHIFT                                                     0x3
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_HI__SHIFT                                                  0x4
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR__SHIFT                                                     0x5
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_HI__SHIFT                                                  0x6
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL__SHIFT                                                     0xa
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_RPTR__SHIFT                                                     0xb
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_OFFSET__SHIFT                                                   0xc
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_LO__SHIFT                                                  0xd
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_HI__SHIFT                                                  0xe
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_SIZE__SHIFT                                                     0xf
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_SKIP_CNTL__SHIFT                                                   0x10
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_STATUS__SHIFT                                              0x11
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_DOORBELL__SHIFT                                                    0x12
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_CNTL__SHIFT                                                0x13
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_CNTL_MASK                                                       0x00000001L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_MASK                                                       0x00000002L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_HI_MASK                                                    0x00000004L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_MASK                                                       0x00000008L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_MASK                                                       0x00000020L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL_MASK                                                       0x00000400L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_RPTR_MASK                                                       0x00000800L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_OFFSET_MASK                                                     0x00001000L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_LO_MASK                                                    0x00002000L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_HI_MASK                                                    0x00004000L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_SIZE_MASK                                                       0x00008000L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_SKIP_CNTL_MASK                                                     0x00010000L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_DOORBELL_MASK                                                      0x00040000L
>+#define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
>+//SDMA3_CONTEXT_REG_TYPE1
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_STATUS__SHIFT                                                      0x8
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_LOG__SHIFT                                                0x9
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK__SHIFT                                                   0xa
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
>+#define SDMA3_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_PREEMPT__SHIFT                                                     0x10
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DUMMY_REG__SHIFT                                                   0x11
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
>+#define SDMA3_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x16
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_STATUS_MASK                                                        0x00000100L
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK_MASK                                                     0x00000400L
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
>+#define SDMA3_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_PREEMPT_MASK                                                       0x00010000L
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DUMMY_REG_MASK                                                     0x00020000L
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
>+#define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
>+#define SDMA3_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFFC00000L
>+//SDMA3_CONTEXT_REG_TYPE2
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA0__SHIFT                                                0x0
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA1__SHIFT                                                0x1
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA2__SHIFT                                                0x2
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA3__SHIFT                                                0x3
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA4__SHIFT                                                0x4
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA5__SHIFT                                                0x5
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA6__SHIFT                                                0x6
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA7__SHIFT                                                0x7
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA8__SHIFT                                                0x8
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_CNTL__SHIFT                                                 0x9
>+#define SDMA3_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
>+#define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_CNTL_MASK                                                   0x00000200L
>+#define SDMA3_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFFC00L
>+//SDMA3_CONTEXT_REG_TYPE3
>+#define SDMA3_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
>+#define SDMA3_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
>+//SDMA3_PUB_REG_TYPE0
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR__SHIFT                                                          0x0
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA__SHIFT                                                          0x1
>+#define SDMA3_PUB_REG_TYPE0__RESERVED3__SHIFT                                                                 0x3
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CNTL__SHIFT                                                             0x4
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_LO__SHIFT                                                           0x5
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_HI__SHIFT                                                           0x6
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_ACTIVE_FCN_ID__SHIFT                                                       0x7
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_CNTL__SHIFT                                                         0x8
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_VIRT_RESET_REQ__SHIFT                                                      0x9
>+#define SDMA3_PUB_REG_TYPE0__RESERVED10__SHIFT                                                                0xa
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE0__SHIFT                                                   0xb
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE1__SHIFT                                                   0xc
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE2__SHIFT                                                   0xd
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE3__SHIFT                                                   0xe
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE0__SHIFT                                                       0xf
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE1__SHIFT                                                       0x10
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE2__SHIFT                                                       0x11
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE3__SHIFT                                                       0x12
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_MMHUB_CNTL__SHIFT                                                          0x13
>+#define SDMA3_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x15
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_GROUP_BOUNDARY__SHIFT                                              0x19
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_POWER_CNTL__SHIFT                                                          0x1a
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CLK_CTRL__SHIFT                                                            0x1b
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CNTL__SHIFT                                                                0x1c
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS__SHIFT                                                        0x1d
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG__SHIFT                                                      0x1e
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR_MASK                                                            0x00000001L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA_MASK                                                            0x00000002L
>+#define SDMA3_PUB_REG_TYPE0__RESERVED3_MASK                                                                   0x00000008L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CNTL_MASK                                                               0x00000010L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_LO_MASK                                                             0x00000020L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_HI_MASK                                                             0x00000040L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_ACTIVE_FCN_ID_MASK                                                         0x00000080L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_CNTL_MASK                                                           0x00000100L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_VIRT_RESET_REQ_MASK                                                        0x00000200L
>+#define SDMA3_PUB_REG_TYPE0__RESERVED10_MASK                                                                  0x00000400L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE0_MASK                                                     0x00000800L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE1_MASK                                                     0x00001000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE2_MASK                                                     0x00002000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE3_MASK                                                     0x00004000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE0_MASK                                                         0x00008000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE1_MASK                                                         0x00010000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE2_MASK                                                         0x00020000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE3_MASK                                                         0x00040000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_MMHUB_CNTL_MASK                                                            0x00080000L
>+#define SDMA3_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x01E00000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_GROUP_BOUNDARY_MASK                                                0x02000000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_POWER_CNTL_MASK                                                            0x04000000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CLK_CTRL_MASK                                                              0x08000000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CNTL_MASK                                                                  0x10000000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS_MASK                                                          0x20000000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_MASK                                                        0x40000000L
>+#define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
>+//SDMA3_PUB_REG_TYPE1
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH__SHIFT                                                       0x2
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_IB_OFFSET_FETCH__SHIFT                                                     0x3
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_PROGRAM__SHIFT                                                             0x4
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS_REG__SHIFT                                                          0x5
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS1_REG__SHIFT                                                         0x6
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_RD_BURST_CNTL__SHIFT                                                       0x7
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_HBM_PAGE_CONFIG__SHIFT                                                     0x8
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_UCODE_CHECKSUM__SHIFT                                                      0x9
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL__SHIFT                                                            0xa
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_FREEZE__SHIFT                                                              0xb
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE0_QUANTUM__SHIFT                                                      0xc
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE1_QUANTUM__SHIFT                                                      0xd
>+#define SDMA3_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT                                                         0xe
>+#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT                                                         0xf
>+#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT                                                          0x10
>+#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT                                                           0x11
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_CONFIG__SHIFT                                                          0x12
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_BA_THRESHOLD__SHIFT                                                        0x13
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_ID__SHIFT                                                                  0x14
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_VERSION__SHIFT                                                             0x15
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER__SHIFT                                                         0x16
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS2_REG__SHIFT                                                         0x18
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_CNTL__SHIFT                                                         0x19
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_CNTL__SHIFT                                                          0x1c
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK__SHIFT                                                       0x1d
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_RD_STATUS__SHIFT                                                     0x1e
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WR_STATUS__SHIFT                                                     0x1f
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_MASK                                                         0x00000004L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_IB_OFFSET_FETCH_MASK                                                       0x00000008L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_PROGRAM_MASK                                                               0x00000010L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS_REG_MASK                                                            0x00000020L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS1_REG_MASK                                                           0x00000040L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_RD_BURST_CNTL_MASK                                                         0x00000080L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_UCODE_CHECKSUM_MASK                                                        0x00000200L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL_MASK                                                              0x00000400L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_FREEZE_MASK                                                                0x00000800L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE0_QUANTUM_MASK                                                        0x00001000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE1_QUANTUM_MASK                                                        0x00002000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK                                                           0x00004000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK                                                           0x00008000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK                                                            0x00010000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK                                                             0x00020000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_CONFIG_MASK                                                            0x00040000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_BA_THRESHOLD_MASK                                                          0x00080000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_ID_MASK                                                                    0x00100000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_VERSION_MASK                                                               0x00200000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_MASK                                                           0x00400000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS2_REG_MASK                                                           0x01000000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_CNTL_MASK                                                           0x02000000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_CNTL_MASK                                                            0x10000000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK_MASK                                                         0x20000000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_RD_STATUS_MASK                                                       0x40000000L
>+#define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WR_STATUS_MASK                                                       0x80000000L
>+//SDMA3_PUB_REG_TYPE2
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV0__SHIFT                                                          0x0
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV1__SHIFT                                                          0x1
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV2__SHIFT                                                          0x2
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK0__SHIFT                                                     0x3
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK1__SHIFT                                                     0x4
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK0__SHIFT                                                     0x5
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK1__SHIFT                                                     0x6
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_TIMEOUT__SHIFT                                                       0x7
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_PAGE__SHIFT                                                          0x8
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_POWER_CNTL_IDLE__SHIFT                                                     0x9
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT__SHIFT                                                  0xa
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_CHICKEN_BITS_2__SHIFT                                                      0xb
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_STATUS3_REG__SHIFT                                                         0xc
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PHASE2_QUANTUM__SHIFT                                                      0xf
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_ERROR_LOG__SHIFT                                                           0x10
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG0__SHIFT                                                      0x11
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG1__SHIFT                                                      0x12
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG2__SHIFT                                                      0x13
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG3__SHIFT                                                      0x14
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_F32_COUNTER__SHIFT                                                         0x15
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UNBREAKABLE__SHIFT                                                         0x16
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFMON_CNTL__SHIFT                                                        0x17
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER0_RESULT__SHIFT                                                 0x18
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER1_RESULT__SHIFT                                                 0x19
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT                                         0x1a
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_CRD_CNTL__SHIFT                                                            0x1b
>+#define SDMA3_PUB_REG_TYPE2__RESERVED28__SHIFT                                                                0x1c
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_GPU_IOV_VIOLATION_LOG__SHIFT                                               0x1d
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_ULV_CNTL__SHIFT                                                            0x1e
>+#define SDMA3_PUB_REG_TYPE2__RESERVED__SHIFT                                                                  0x1f
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV0_MASK                                                            0x00000001L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV1_MASK                                                            0x00000002L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV2_MASK                                                            0x00000004L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_TIMEOUT_MASK                                                         0x00000080L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_PAGE_MASK                                                            0x00000100L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_POWER_CNTL_IDLE_MASK                                                       0x00000200L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_CHICKEN_BITS_2_MASK                                                        0x00000800L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_STATUS3_REG_MASK                                                           0x00001000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PHASE2_QUANTUM_MASK                                                        0x00008000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_ERROR_LOG_MASK                                                             0x00010000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG0_MASK                                                        0x00020000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG1_MASK                                                        0x00040000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG2_MASK                                                        0x00080000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG3_MASK                                                        0x00100000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_F32_COUNTER_MASK                                                           0x00200000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_UNBREAKABLE_MASK                                                           0x00400000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFMON_CNTL_MASK                                                          0x00800000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER0_RESULT_MASK                                                   0x01000000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER1_RESULT_MASK                                                   0x02000000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCOUNTER_TAG_DELAY_RANGE_MASK                                           0x04000000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_CRD_CNTL_MASK                                                              0x08000000L
>+#define SDMA3_PUB_REG_TYPE2__RESERVED28_MASK                                                                  0x10000000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_GPU_IOV_VIOLATION_LOG_MASK                                                 0x20000000L
>+#define SDMA3_PUB_REG_TYPE2__SDMA3_ULV_CNTL_MASK                                                              0x40000000L
>+#define SDMA3_PUB_REG_TYPE2__RESERVED_MASK                                                                    0x80000000L
>+//SDMA3_PUB_REG_TYPE3
>+#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
>+#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
>+#define SDMA3_PUB_REG_TYPE3__SDMA3_GPU_IOV_VIOLATION_LOG2__SHIFT                                              0x2
>+#define SDMA3_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x3
>+#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
>+#define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
>+#define SDMA3_PUB_REG_TYPE3__SDMA3_GPU_IOV_VIOLATION_LOG2_MASK                                                0x00000004L
>+#define SDMA3_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xFFFFFFF8L
>+//SDMA3_MMHUB_CNTL
>+#define SDMA3_MMHUB_CNTL__UNIT_ID__SHIFT                                                                      0x0
>+#define SDMA3_MMHUB_CNTL__UNIT_ID_MASK                                                                        0x0000003FL
>+//SDMA3_CONTEXT_GROUP_BOUNDARY
>+#define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT                                                         0x0
>+#define SDMA3_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK                                                           0xFFFFFFFFL
>+//SDMA3_POWER_CNTL
>+#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
>+#define SDMA3_POWER_CNTL__MEM_POWER_LS_EN__SHIFT                                                              0x9
>+#define SDMA3_POWER_CNTL__MEM_POWER_DS_EN__SHIFT                                                              0xa
>+#define SDMA3_POWER_CNTL__MEM_POWER_SD_EN__SHIFT                                                              0xb
>+#define SDMA3_POWER_CNTL__MEM_POWER_DELAY__SHIFT                                                              0xc
>+#define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
>+#define SDMA3_POWER_CNTL__MEM_POWER_LS_EN_MASK                                                                0x00000200L
>+#define SDMA3_POWER_CNTL__MEM_POWER_DS_EN_MASK                                                                0x00000400L
>+#define SDMA3_POWER_CNTL__MEM_POWER_SD_EN_MASK                                                                0x00000800L
>+#define SDMA3_POWER_CNTL__MEM_POWER_DELAY_MASK                                                                0x003FF000L
>+//SDMA3_CLK_CTRL
>+#define SDMA3_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
>+#define SDMA3_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
>+#define SDMA3_CLK_CTRL__RESERVED__SHIFT                                                                       0xc
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                                 0x18
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                                 0x19
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                                 0x1a
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1b
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1c
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1d
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1e
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1f
>+#define SDMA3_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
>+#define SDMA3_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
>+#define SDMA3_CLK_CTRL__RESERVED_MASK                                                                         0x00FFF000L
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                   0x01000000L
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                   0x02000000L
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                   0x04000000L
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x08000000L
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x10000000L
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x20000000L
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x40000000L
>+#define SDMA3_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x80000000L
>+//SDMA3_CNTL
>+#define SDMA3_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
>+#define SDMA3_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
>+#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
>+#define SDMA3_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
>+#define SDMA3_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
>+#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
>+#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
>+#define SDMA3_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
>+#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
>+#define SDMA3_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
>+#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
>+#define SDMA3_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
>+#define SDMA3_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
>+#define SDMA3_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
>+#define SDMA3_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
>+#define SDMA3_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
>+#define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
>+#define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
>+#define SDMA3_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
>+#define SDMA3_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
>+#define SDMA3_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
>+#define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
>+//SDMA3_CHICKEN_BITS
>+#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
>+#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
>+#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
>+#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
>+#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
>+#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
>+#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
>+#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
>+#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
>+#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
>+#define SDMA3_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
>+#define SDMA3_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
>+#define SDMA3_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
>+#define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
>+#define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
>+#define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
>+#define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
>+#define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
>+#define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
>+#define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
>+#define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
>+#define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
>+#define SDMA3_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
>+#define SDMA3_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
>+#define SDMA3_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
>+#define SDMA3_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
>+//SDMA3_GB_ADDR_CONFIG
>+#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
>+#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
>+#define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
>+#define SDMA3_GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
>+#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
>+#define SDMA3_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
>+#define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
>+#define SDMA3_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
>+#define SDMA3_GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
>+#define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
>+//SDMA3_GB_ADDR_CONFIG_READ
>+#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
>+#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
>+#define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                0x8
>+#define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                           0xc
>+#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
>+#define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
>+#define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
>+#define SDMA3_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                  0x00000700L
>+#define SDMA3_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                             0x00007000L
>+#define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
>+//SDMA3_RB_RPTR_FETCH_HI
>+#define SDMA3_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
>+#define SDMA3_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_SEM_WAIT_FAIL_TIMER_CNTL
>+#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
>+#define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
>+//SDMA3_RB_RPTR_FETCH
>+#define SDMA3_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
>+#define SDMA3_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
>+//SDMA3_IB_OFFSET_FETCH
>+#define SDMA3_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
>+#define SDMA3_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
>+//SDMA3_PROGRAM
>+#define SDMA3_PROGRAM__STREAM__SHIFT                                                                          0x0
>+#define SDMA3_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
>+//SDMA3_STATUS_REG
>+#define SDMA3_STATUS_REG__IDLE__SHIFT                                                                         0x0
>+#define SDMA3_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
>+#define SDMA3_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
>+#define SDMA3_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
>+#define SDMA3_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
>+#define SDMA3_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
>+#define SDMA3_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
>+#define SDMA3_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
>+#define SDMA3_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
>+#define SDMA3_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
>+#define SDMA3_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
>+#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
>+#define SDMA3_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
>+#define SDMA3_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
>+#define SDMA3_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
>+#define SDMA3_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
>+#define SDMA3_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
>+#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
>+#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
>+#define SDMA3_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
>+#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
>+#define SDMA3_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
>+#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
>+#define SDMA3_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
>+#define SDMA3_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
>+#define SDMA3_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
>+#define SDMA3_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
>+#define SDMA3_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
>+#define SDMA3_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
>+#define SDMA3_STATUS_REG__IDLE_MASK                                                                           0x00000001L
>+#define SDMA3_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
>+#define SDMA3_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
>+#define SDMA3_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
>+#define SDMA3_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
>+#define SDMA3_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
>+#define SDMA3_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
>+#define SDMA3_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
>+#define SDMA3_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
>+#define SDMA3_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
>+#define SDMA3_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
>+#define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
>+#define SDMA3_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
>+#define SDMA3_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
>+#define SDMA3_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
>+#define SDMA3_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
>+#define SDMA3_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
>+#define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
>+#define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
>+#define SDMA3_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
>+#define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
>+#define SDMA3_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
>+#define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
>+#define SDMA3_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
>+#define SDMA3_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
>+#define SDMA3_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
>+#define SDMA3_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
>+#define SDMA3_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
>+#define SDMA3_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
>+//SDMA3_STATUS1_REG
>+#define SDMA3_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
>+#define SDMA3_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
>+#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
>+#define SDMA3_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
>+#define SDMA3_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
>+#define SDMA3_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
>+#define SDMA3_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
>+#define SDMA3_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
>+#define SDMA3_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
>+#define SDMA3_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
>+#define SDMA3_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
>+#define SDMA3_STATUS1_REG__EX_START__SHIFT                                                                    0xf
>+#define SDMA3_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
>+#define SDMA3_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
>+#define SDMA3_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
>+#define SDMA3_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
>+#define SDMA3_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
>+#define SDMA3_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
>+#define SDMA3_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
>+#define SDMA3_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
>+#define SDMA3_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
>+#define SDMA3_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
>+#define SDMA3_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
>+#define SDMA3_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
>+#define SDMA3_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
>+#define SDMA3_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
>+#define SDMA3_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
>+#define SDMA3_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
>+//SDMA3_RD_BURST_CNTL
>+#define SDMA3_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
>+#define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT                                                       0x2
>+#define SDMA3_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
>+#define SDMA3_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK                                                         0x0000000CL
>+//SDMA3_HBM_PAGE_CONFIG
>+#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
>+#define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000001L
>+//SDMA3_UCODE_CHECKSUM
>+#define SDMA3_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
>+#define SDMA3_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_F32_CNTL
>+#define SDMA3_F32_CNTL__HALT__SHIFT                                                                           0x0
>+#define SDMA3_F32_CNTL__STEP__SHIFT                                                                           0x1
>+#define SDMA3_F32_CNTL__HALT_MASK                                                                             0x00000001L
>+#define SDMA3_F32_CNTL__STEP_MASK                                                                             0x00000002L
>+//SDMA3_FREEZE
>+#define SDMA3_FREEZE__PREEMPT__SHIFT                                                                          0x0
>+#define SDMA3_FREEZE__FREEZE__SHIFT                                                                           0x4
>+#define SDMA3_FREEZE__FROZEN__SHIFT                                                                           0x5
>+#define SDMA3_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
>+#define SDMA3_FREEZE__PREEMPT_MASK                                                                            0x00000001L
>+#define SDMA3_FREEZE__FREEZE_MASK                                                                             0x00000010L
>+#define SDMA3_FREEZE__FROZEN_MASK                                                                             0x00000020L
>+#define SDMA3_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
>+//SDMA3_PHASE0_QUANTUM
>+#define SDMA3_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA3_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA3_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA3_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA3_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA3_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA3_PHASE1_QUANTUM
>+#define SDMA3_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA3_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA3_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA3_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA3_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA3_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA3_EDC_CONFIG
>+#define SDMA3_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
>+#define SDMA3_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
>+#define SDMA3_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
>+#define SDMA3_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
>+//SDMA3_BA_THRESHOLD
>+#define SDMA3_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
>+#define SDMA3_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
>+#define SDMA3_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
>+#define SDMA3_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
>+//SDMA3_ID
>+#define SDMA3_ID__DEVICE_ID__SHIFT                                                                            0x0
>+#define SDMA3_ID__DEVICE_ID_MASK                                                                              0x000000FFL
>+//SDMA3_VERSION
>+#define SDMA3_VERSION__MINVER__SHIFT                                                                          0x0
>+#define SDMA3_VERSION__MAJVER__SHIFT                                                                          0x8
>+#define SDMA3_VERSION__REV__SHIFT                                                                             0x10
>+#define SDMA3_VERSION__MINVER_MASK                                                                            0x0000007FL
>+#define SDMA3_VERSION__MAJVER_MASK                                                                            0x00007F00L
>+#define SDMA3_VERSION__REV_MASK                                                                               0x003F0000L
>+//SDMA3_EDC_COUNTER
>+#define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT                                                          0x0
>+#define SDMA3_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
>+#define SDMA3_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
>+#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
>+#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
>+#define SDMA3_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT                                                    0xf
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT                                                    0x10
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT                                                   0x11
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT                                                   0x12
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT                                                   0x13
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT                                                   0x14
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT                                                   0x15
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT                                                   0x16
>+#define SDMA3_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0x17
>+#define SDMA3_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x18
>+#define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK                                                            0x00000001L
>+#define SDMA3_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
>+#define SDMA3_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
>+#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
>+#define SDMA3_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
>+#define SDMA3_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK                                                      0x00008000L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK                                                      0x00010000L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK                                                     0x00020000L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK                                                     0x00040000L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK                                                     0x00080000L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK                                                     0x00100000L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK                                                     0x00200000L
>+#define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK                                                     0x00400000L
>+#define SDMA3_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00800000L
>+#define SDMA3_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x01000000L
>+//SDMA3_EDC_COUNTER_CLEAR
>+#define SDMA3_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
>+#define SDMA3_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
>+//SDMA3_STATUS2_REG
>+#define SDMA3_STATUS2_REG__ID__SHIFT                                                                          0x0
>+#define SDMA3_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x3
>+#define SDMA3_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
>+#define SDMA3_STATUS2_REG__ID_MASK                                                                            0x00000007L
>+#define SDMA3_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFF8L
>+#define SDMA3_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
>+//SDMA3_ATOMIC_CNTL
>+#define SDMA3_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
>+#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
>+#define SDMA3_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
>+#define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
>+//SDMA3_ATOMIC_PREOP_LO
>+#define SDMA3_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
>+#define SDMA3_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_ATOMIC_PREOP_HI
>+#define SDMA3_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
>+#define SDMA3_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_UTCL1_CNTL
>+#define SDMA3_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
>+#define SDMA3_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0xb
>+#define SDMA3_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0xe
>+#define SDMA3_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
>+#define SDMA3_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
>+#define SDMA3_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x000007FEL
>+#define SDMA3_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x00003800L
>+#define SDMA3_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FFC000L
>+#define SDMA3_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
>+#define SDMA3_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
>+//SDMA3_UTCL1_WATERMK
>+#define SDMA3_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
>+#define SDMA3_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0x9
>+#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x11
>+#define SDMA3_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x19
>+#define SDMA3_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000001FFL
>+#define SDMA3_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0001FE00L
>+#define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x01FE0000L
>+#define SDMA3_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFE000000L
>+//SDMA3_UTCL1_RD_STATUS
>+#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT                                                             0x15
>+#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x16
>+#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x1a
>+#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x1d
>+#define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT                                                            0x1e
>+#define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT                                                             0x1f
>+#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA3_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA3_UTCL1_RD_STATUS__CE_L1_STALL_MASK                                                               0x00200000L
>+#define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x03C00000L
>+#define SDMA3_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x1C000000L
>+#define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x20000000L
>+#define SDMA3_UTCL1_RD_STATUS__WPTR_POLLING_MASK                                                              0x40000000L
>+#define SDMA3_UTCL1_RD_STATUS__INVREQ_SIZE_MASK                                                               0x80000000L
>+//SDMA3_UTCL1_WR_STATUS
>+#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15
>+#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x16
>+#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19
>+#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
>+#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
>+#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
>+#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
>+#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA3_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x00200000L
>+#define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x01C00000L
>+#define SDMA3_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x0E000000L
>+#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
>+#define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
>+#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
>+#define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
>+//SDMA3_UTCL1_INV0
>+#define SDMA3_UTCL1_INV0__INV_MIDDLE__SHIFT                                                                   0x0
>+#define SDMA3_UTCL1_INV0__RD_TIMEOUT__SHIFT                                                                   0x1
>+#define SDMA3_UTCL1_INV0__WR_TIMEOUT__SHIFT                                                                   0x2
>+#define SDMA3_UTCL1_INV0__RD_IN_INVADR__SHIFT                                                                 0x3
>+#define SDMA3_UTCL1_INV0__WR_IN_INVADR__SHIFT                                                                 0x4
>+#define SDMA3_UTCL1_INV0__PAGE_NULL_SW__SHIFT                                                                 0x5
>+#define SDMA3_UTCL1_INV0__XNACK_IS_INVADR__SHIFT                                                              0x6
>+#define SDMA3_UTCL1_INV0__INVREQ_ENABLE__SHIFT                                                                0x7
>+#define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT                                                              0x8
>+#define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT                                                              0x9
>+#define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT                                                               0xa
>+#define SDMA3_UTCL1_INV0__INV_FLUSHTYPE__SHIFT                                                                0xb
>+#define SDMA3_UTCL1_INV0__INV_VMID_VEC__SHIFT                                                                 0xc
>+#define SDMA3_UTCL1_INV0__INV_ADDR_HI__SHIFT                                                                  0x1c
>+#define SDMA3_UTCL1_INV0__INV_MIDDLE_MASK                                                                     0x00000001L
>+#define SDMA3_UTCL1_INV0__RD_TIMEOUT_MASK                                                                     0x00000002L
>+#define SDMA3_UTCL1_INV0__WR_TIMEOUT_MASK                                                                     0x00000004L
>+#define SDMA3_UTCL1_INV0__RD_IN_INVADR_MASK                                                                   0x00000008L
>+#define SDMA3_UTCL1_INV0__WR_IN_INVADR_MASK                                                                   0x00000010L
>+#define SDMA3_UTCL1_INV0__PAGE_NULL_SW_MASK                                                                   0x00000020L
>+#define SDMA3_UTCL1_INV0__XNACK_IS_INVADR_MASK                                                                0x00000040L
>+#define SDMA3_UTCL1_INV0__INVREQ_ENABLE_MASK                                                                  0x00000080L
>+#define SDMA3_UTCL1_INV0__NACK_TIMEOUT_SW_MASK                                                                0x00000100L
>+#define SDMA3_UTCL1_INV0__NFLUSH_INV_IDLE_MASK                                                                0x00000200L
>+#define SDMA3_UTCL1_INV0__FLUSH_INV_IDLE_MASK                                                                 0x00000400L
>+#define SDMA3_UTCL1_INV0__INV_FLUSHTYPE_MASK                                                                  0x00000800L
>+#define SDMA3_UTCL1_INV0__INV_VMID_VEC_MASK                                                                   0x0FFFF000L
>+#define SDMA3_UTCL1_INV0__INV_ADDR_HI_MASK                                                                    0xF0000000L
>+//SDMA3_UTCL1_INV1
>+#define SDMA3_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
>+#define SDMA3_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_UTCL1_INV2
>+#define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT                                                          0x0
>+#define SDMA3_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK                                                            0xFFFFFFFFL
>+//SDMA3_UTCL1_RD_XNACK0
>+#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA3_UTCL1_RD_XNACK1
>+#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA3_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA3_UTCL1_WR_XNACK0
>+#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA3_UTCL1_WR_XNACK1
>+#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA3_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA3_UTCL1_TIMEOUT
>+#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
>+#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
>+#define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
>+#define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
>+//SDMA3_UTCL1_PAGE
>+#define SDMA3_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
>+#define SDMA3_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
>+#define SDMA3_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
>+#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0x9
>+#define SDMA3_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
>+#define SDMA3_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
>+#define SDMA3_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000001C0L
>+#define SDMA3_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000200L
>+//SDMA3_POWER_CNTL_IDLE
>+#define SDMA3_POWER_CNTL_IDLE__DELAY0__SHIFT                                                                  0x0
>+#define SDMA3_POWER_CNTL_IDLE__DELAY1__SHIFT                                                                  0x10
>+#define SDMA3_POWER_CNTL_IDLE__DELAY2__SHIFT                                                                  0x18
>+#define SDMA3_POWER_CNTL_IDLE__DELAY0_MASK                                                                    0x0000FFFFL
>+#define SDMA3_POWER_CNTL_IDLE__DELAY1_MASK                                                                    0x00FF0000L
>+#define SDMA3_POWER_CNTL_IDLE__DELAY2_MASK                                                                    0xFF000000L
>+//SDMA3_RELAX_ORDERING_LUT
>+#define SDMA3_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
>+#define SDMA3_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
>+#define SDMA3_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
>+#define SDMA3_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
>+#define SDMA3_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
>+#define SDMA3_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
>+#define SDMA3_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
>+#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
>+#define SDMA3_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
>+#define SDMA3_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
>+#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
>+#define SDMA3_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
>+#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
>+#define SDMA3_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
>+#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
>+#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
>+#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
>+#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
>+#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
>+#define SDMA3_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
>+#define SDMA3_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
>+#define SDMA3_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
>+#define SDMA3_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
>+#define SDMA3_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
>+#define SDMA3_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
>+#define SDMA3_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
>+#define SDMA3_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
>+#define SDMA3_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
>+#define SDMA3_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
>+#define SDMA3_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
>+#define SDMA3_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
>+#define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
>+#define SDMA3_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
>+#define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
>+#define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
>+#define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
>+#define SDMA3_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
>+#define SDMA3_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
>+//SDMA3_CHICKEN_BITS_2
>+#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
>+#define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
>+//SDMA3_STATUS3_REG
>+#define SDMA3_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
>+#define SDMA3_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
>+#define SDMA3_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
>+#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x15
>+#define SDMA3_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x16
>+#define SDMA3_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
>+#define SDMA3_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
>+#define SDMA3_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
>+#define SDMA3_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x00200000L
>+#define SDMA3_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x03C00000L
>+//SDMA3_PHYSICAL_ADDR_LO
>+#define SDMA3_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
>+#define SDMA3_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
>+#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
>+#define SDMA3_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
>+#define SDMA3_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
>+#define SDMA3_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
>+#define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
>+#define SDMA3_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
>+//SDMA3_PHYSICAL_ADDR_HI
>+#define SDMA3_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA3_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
>+//SDMA3_PHASE2_QUANTUM
>+#define SDMA3_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA3_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA3_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA3_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA3_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA3_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA3_ERROR_LOG
>+#define SDMA3_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
>+#define SDMA3_ERROR_LOG__STATUS__SHIFT                                                                        0x10
>+#define SDMA3_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
>+#define SDMA3_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
>+//SDMA3_PUB_DUMMY_REG0
>+#define SDMA3_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
>+#define SDMA3_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_PUB_DUMMY_REG1
>+#define SDMA3_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
>+#define SDMA3_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_PUB_DUMMY_REG2
>+#define SDMA3_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
>+#define SDMA3_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_PUB_DUMMY_REG3
>+#define SDMA3_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
>+#define SDMA3_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_F32_COUNTER
>+#define SDMA3_F32_COUNTER__VALUE__SHIFT                                                                       0x0
>+#define SDMA3_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
>+//SDMA3_UNBREAKABLE
>+#define SDMA3_UNBREAKABLE__VALUE__SHIFT                                                                       0x0
>+#define SDMA3_UNBREAKABLE__VALUE_MASK                                                                         0x00000001L
>+//SDMA3_PERFMON_CNTL
>+#define SDMA3_PERFMON_CNTL__PERF_ENABLE0__SHIFT                                                               0x0
>+#define SDMA3_PERFMON_CNTL__PERF_CLEAR0__SHIFT                                                                0x1
>+#define SDMA3_PERFMON_CNTL__PERF_SEL0__SHIFT                                                                  0x2
>+#define SDMA3_PERFMON_CNTL__PERF_ENABLE1__SHIFT                                                               0xa
>+#define SDMA3_PERFMON_CNTL__PERF_CLEAR1__SHIFT                                                                0xb
>+#define SDMA3_PERFMON_CNTL__PERF_SEL1__SHIFT                                                                  0xc
>+#define SDMA3_PERFMON_CNTL__PERF_ENABLE0_MASK                                                                 0x00000001L
>+#define SDMA3_PERFMON_CNTL__PERF_CLEAR0_MASK                                                                  0x00000002L
>+#define SDMA3_PERFMON_CNTL__PERF_SEL0_MASK                                                                    0x000003FCL
>+#define SDMA3_PERFMON_CNTL__PERF_ENABLE1_MASK                                                                 0x00000400L
>+#define SDMA3_PERFMON_CNTL__PERF_CLEAR1_MASK                                                                  0x00000800L
>+#define SDMA3_PERFMON_CNTL__PERF_SEL1_MASK                                                                    0x000FF000L
>+//SDMA3_PERFCOUNTER0_RESULT
>+#define SDMA3_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA3_PERFCOUNTER0_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA3_PERFCOUNTER1_RESULT
>+#define SDMA3_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA3_PERFCOUNTER1_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA3_PERFCOUNTER_TAG_DELAY_RANGE
>+#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT                                                   0x0
>+#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT                                                  0xe
>+#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT                                                   0x1c
>+#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK                                                     0x00003FFFL
>+#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK                                                    0x0FFFC000L
>+#define SDMA3_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK                                                     0x10000000L
>+//SDMA3_CRD_CNTL
>+#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
>+#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
>+#define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
>+#define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
>+//SDMA3_GPU_IOV_VIOLATION_LOG
>+#define SDMA3_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT                                                  0x0
>+#define SDMA3_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT                                         0x1
>+#define SDMA3_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT                                                           0x2
>+#define SDMA3_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT                                                   0x14
>+#define SDMA3_GPU_IOV_VIOLATION_LOG__VF__SHIFT                                                                0x15
>+#define SDMA3_GPU_IOV_VIOLATION_LOG__VFID__SHIFT                                                              0x16
>+#define SDMA3_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK                                                    0x00000001L
>+#define SDMA3_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK                                           0x00000002L
>+#define SDMA3_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK                                                             0x000FFFFCL
>+#define SDMA3_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK                                                     0x00100000L
>+#define SDMA3_GPU_IOV_VIOLATION_LOG__VF_MASK                                                                  0x00200000L
>+#define SDMA3_GPU_IOV_VIOLATION_LOG__VFID_MASK                                                                0x03C00000L
>+//SDMA3_ULV_CNTL
>+#define SDMA3_ULV_CNTL__HYSTERESIS__SHIFT                                                                     0x0
>+#define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT                                                              0x1b
>+#define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT                                                               0x1c
>+#define SDMA3_ULV_CNTL__ENTER_ULV_INT__SHIFT                                                                  0x1d
>+#define SDMA3_ULV_CNTL__EXIT_ULV_INT__SHIFT                                                                   0x1e
>+#define SDMA3_ULV_CNTL__ULV_STATUS__SHIFT                                                                     0x1f
>+#define SDMA3_ULV_CNTL__HYSTERESIS_MASK                                                                       0x0000001FL
>+#define SDMA3_ULV_CNTL__ENTER_ULV_INT_CLR_MASK                                                                0x08000000L
>+#define SDMA3_ULV_CNTL__EXIT_ULV_INT_CLR_MASK                                                                 0x10000000L
>+#define SDMA3_ULV_CNTL__ENTER_ULV_INT_MASK                                                                    0x20000000L
>+#define SDMA3_ULV_CNTL__EXIT_ULV_INT_MASK                                                                     0x40000000L
>+#define SDMA3_ULV_CNTL__ULV_STATUS_MASK                                                                       0x80000000L
>+//SDMA3_EA_DBIT_ADDR_DATA
>+#define SDMA3_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
>+#define SDMA3_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_EA_DBIT_ADDR_INDEX
>+#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
>+#define SDMA3_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
>+//SDMA3_GPU_IOV_VIOLATION_LOG2
>+#define SDMA3_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                     0x0
>+#define SDMA3_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                       0x000000FFL
>+//SDMA3_GFX_RB_CNTL
>+#define SDMA3_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA3_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
>+#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
>+#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
>+#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
>+#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
>+#define SDMA3_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
>+#define SDMA3_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
>+#define SDMA3_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA3_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
>+#define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
>+#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
>+#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
>+#define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
>+#define SDMA3_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
>+#define SDMA3_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
>+//SDMA3_GFX_RB_BASE
>+#define SDMA3_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
>+#define SDMA3_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
>+//SDMA3_GFX_RB_BASE_HI
>+#define SDMA3_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA3_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
>+//SDMA3_GFX_RB_RPTR
>+#define SDMA3_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA3_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA3_GFX_RB_RPTR_HI
>+#define SDMA3_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA3_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA3_GFX_RB_WPTR
>+#define SDMA3_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA3_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA3_GFX_RB_WPTR_HI
>+#define SDMA3_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA3_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA3_GFX_RB_WPTR_POLL_CNTL
>+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
>+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
>+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
>+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
>+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
>+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
>+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
>+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
>+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
>+#define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
>+//SDMA3_GFX_RB_RPTR_ADDR_HI
>+#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
>+#define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
>+//SDMA3_GFX_RB_RPTR_ADDR_LO
>+#define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                        0x0
>+#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
>+#define SDMA3_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                          0x00000001L
>+#define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
>+//SDMA3_GFX_IB_CNTL
>+#define SDMA3_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
>+#define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
>+#define SDMA3_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
>+#define SDMA3_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
>+#define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
>+#define SDMA3_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
>+//SDMA3_GFX_IB_RPTR
>+#define SDMA3_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
>+#define SDMA3_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
>+//SDMA3_GFX_IB_OFFSET
>+#define SDMA3_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
>+#define SDMA3_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
>+//SDMA3_GFX_IB_BASE_LO
>+#define SDMA3_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
>+#define SDMA3_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
>+//SDMA3_GFX_IB_BASE_HI
>+#define SDMA3_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA3_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_GFX_IB_SIZE
>+#define SDMA3_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
>+#define SDMA3_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
>+//SDMA3_GFX_SKIP_CNTL
>+#define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
>+#define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
>+//SDMA3_GFX_CONTEXT_STATUS
>+#define SDMA3_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
>+#define SDMA3_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
>+#define SDMA3_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
>+#define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
>+#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
>+#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
>+#define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
>+#define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
>+#define SDMA3_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
>+#define SDMA3_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
>+#define SDMA3_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
>+#define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
>+#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
>+#define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
>+#define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
>+#define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
>+//SDMA3_GFX_DOORBELL
>+#define SDMA3_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
>+#define SDMA3_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
>+#define SDMA3_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
>+#define SDMA3_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
>+//SDMA3_GFX_CONTEXT_CNTL
>+#define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
>+#define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
>+//SDMA3_GFX_STATUS
>+#define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
>+#define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
>+#define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
>+#define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
>+//SDMA3_GFX_DOORBELL_LOG
>+#define SDMA3_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
>+#define SDMA3_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
>+#define SDMA3_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
>+#define SDMA3_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
>+//SDMA3_GFX_WATERMARK
>+#define SDMA3_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
>+#define SDMA3_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
>+#define SDMA3_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
>+#define SDMA3_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
>+//SDMA3_GFX_DOORBELL_OFFSET
>+#define SDMA3_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
>+#define SDMA3_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
>+//SDMA3_GFX_CSA_ADDR_LO
>+#define SDMA3_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
>+#define SDMA3_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
>+//SDMA3_GFX_CSA_ADDR_HI
>+#define SDMA3_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_GFX_IB_SUB_REMAIN
>+#define SDMA3_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
>+#define SDMA3_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x000FFFFFL
>+//SDMA3_GFX_PREEMPT
>+#define SDMA3_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
>+#define SDMA3_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
>+//SDMA3_GFX_DUMMY_REG
>+#define SDMA3_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
>+#define SDMA3_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_GFX_RB_WPTR_POLL_ADDR_HI
>+#define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
>+#define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
>+//SDMA3_GFX_RB_WPTR_POLL_ADDR_LO
>+#define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
>+#define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
>+//SDMA3_GFX_RB_AQL_CNTL
>+#define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
>+#define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
>+#define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
>+#define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
>+#define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
>+#define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
>+//SDMA3_GFX_MINOR_PTR_UPDATE
>+#define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
>+#define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
>+//SDMA3_GFX_MIDCMD_DATA0
>+#define SDMA3_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
>+#define SDMA3_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_GFX_MIDCMD_DATA1
>+#define SDMA3_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
>+#define SDMA3_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_GFX_MIDCMD_DATA2
>+#define SDMA3_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
>+#define SDMA3_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_GFX_MIDCMD_DATA3
>+#define SDMA3_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
>+#define SDMA3_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_GFX_MIDCMD_DATA4
>+#define SDMA3_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
>+#define SDMA3_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_GFX_MIDCMD_DATA5
>+#define SDMA3_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
>+#define SDMA3_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_GFX_MIDCMD_DATA6
>+#define SDMA3_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
>+#define SDMA3_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_GFX_MIDCMD_DATA7
>+#define SDMA3_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
>+#define SDMA3_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_GFX_MIDCMD_DATA8
>+#define SDMA3_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
>+#define SDMA3_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_GFX_MIDCMD_CNTL
>+#define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
>+#define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
>+#define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
>+#define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
>+#define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
>+#define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
>+#define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
>+#define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
>+//SDMA3_PAGE_RB_CNTL
>+#define SDMA3_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA3_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA3_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA3_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA3_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA3_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA3_PAGE_RB_BASE
>+#define SDMA3_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA3_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA3_PAGE_RB_BASE_HI
>+#define SDMA3_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA3_PAGE_RB_RPTR
>+#define SDMA3_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_PAGE_RB_RPTR_HI
>+#define SDMA3_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_PAGE_RB_WPTR
>+#define SDMA3_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_PAGE_RB_WPTR_HI
>+#define SDMA3_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_PAGE_RB_WPTR_POLL_CNTL
>+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA3_PAGE_RB_RPTR_ADDR_HI
>+#define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA3_PAGE_RB_RPTR_ADDR_LO
>+#define SDMA3_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA3_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA3_PAGE_IB_CNTL
>+#define SDMA3_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA3_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA3_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA3_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA3_PAGE_IB_RPTR
>+#define SDMA3_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA3_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA3_PAGE_IB_OFFSET
>+#define SDMA3_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA3_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA3_PAGE_IB_BASE_LO
>+#define SDMA3_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA3_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA3_PAGE_IB_BASE_HI
>+#define SDMA3_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_PAGE_IB_SIZE
>+#define SDMA3_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA3_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA3_PAGE_SKIP_CNTL
>+#define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA3_PAGE_CONTEXT_STATUS
>+#define SDMA3_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA3_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA3_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA3_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA3_PAGE_DOORBELL
>+#define SDMA3_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA3_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA3_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA3_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA3_PAGE_STATUS
>+#define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA3_PAGE_DOORBELL_LOG
>+#define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA3_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA3_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA3_PAGE_WATERMARK
>+#define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA3_PAGE_DOORBELL_OFFSET
>+#define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA3_PAGE_CSA_ADDR_LO
>+#define SDMA3_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA3_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA3_PAGE_CSA_ADDR_HI
>+#define SDMA3_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA3_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA3_PAGE_IB_SUB_REMAIN
>+#define SDMA3_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA3_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA3_PAGE_PREEMPT
>+#define SDMA3_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA3_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA3_PAGE_DUMMY_REG
>+#define SDMA3_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA3_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI
>+#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO
>+#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA3_PAGE_RB_AQL_CNTL
>+#define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA3_PAGE_MINOR_PTR_UPDATE
>+#define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA3_PAGE_MIDCMD_DATA0
>+#define SDMA3_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA3_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_PAGE_MIDCMD_DATA1
>+#define SDMA3_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA3_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_PAGE_MIDCMD_DATA2
>+#define SDMA3_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA3_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_PAGE_MIDCMD_DATA3
>+#define SDMA3_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA3_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_PAGE_MIDCMD_DATA4
>+#define SDMA3_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA3_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_PAGE_MIDCMD_DATA5
>+#define SDMA3_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA3_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_PAGE_MIDCMD_DATA6
>+#define SDMA3_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA3_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_PAGE_MIDCMD_DATA7
>+#define SDMA3_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA3_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_PAGE_MIDCMD_DATA8
>+#define SDMA3_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA3_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_PAGE_MIDCMD_CNTL
>+#define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA3_RLC0_RB_CNTL
>+#define SDMA3_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA3_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA3_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA3_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA3_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA3_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA3_RLC0_RB_BASE
>+#define SDMA3_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA3_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA3_RLC0_RB_BASE_HI
>+#define SDMA3_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA3_RLC0_RB_RPTR
>+#define SDMA3_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC0_RB_RPTR_HI
>+#define SDMA3_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC0_RB_WPTR
>+#define SDMA3_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC0_RB_WPTR_HI
>+#define SDMA3_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC0_RB_WPTR_POLL_CNTL
>+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA3_RLC0_RB_RPTR_ADDR_HI
>+#define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA3_RLC0_RB_RPTR_ADDR_LO
>+#define SDMA3_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA3_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA3_RLC0_IB_CNTL
>+#define SDMA3_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA3_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA3_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA3_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA3_RLC0_IB_RPTR
>+#define SDMA3_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA3_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA3_RLC0_IB_OFFSET
>+#define SDMA3_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA3_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA3_RLC0_IB_BASE_LO
>+#define SDMA3_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA3_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA3_RLC0_IB_BASE_HI
>+#define SDMA3_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC0_IB_SIZE
>+#define SDMA3_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA3_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA3_RLC0_SKIP_CNTL
>+#define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA3_RLC0_CONTEXT_STATUS
>+#define SDMA3_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA3_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA3_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA3_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA3_RLC0_DOORBELL
>+#define SDMA3_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA3_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA3_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA3_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA3_RLC0_STATUS
>+#define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA3_RLC0_DOORBELL_LOG
>+#define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA3_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA3_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA3_RLC0_WATERMARK
>+#define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA3_RLC0_DOORBELL_OFFSET
>+#define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA3_RLC0_CSA_ADDR_LO
>+#define SDMA3_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA3_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA3_RLC0_CSA_ADDR_HI
>+#define SDMA3_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA3_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA3_RLC0_IB_SUB_REMAIN
>+#define SDMA3_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA3_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA3_RLC0_PREEMPT
>+#define SDMA3_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA3_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA3_RLC0_DUMMY_REG
>+#define SDMA3_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA3_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI
>+#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO
>+#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA3_RLC0_RB_AQL_CNTL
>+#define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA3_RLC0_MINOR_PTR_UPDATE
>+#define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA3_RLC0_MIDCMD_DATA0
>+#define SDMA3_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA3_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC0_MIDCMD_DATA1
>+#define SDMA3_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA3_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC0_MIDCMD_DATA2
>+#define SDMA3_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA3_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC0_MIDCMD_DATA3
>+#define SDMA3_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA3_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC0_MIDCMD_DATA4
>+#define SDMA3_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA3_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC0_MIDCMD_DATA5
>+#define SDMA3_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA3_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC0_MIDCMD_DATA6
>+#define SDMA3_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA3_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC0_MIDCMD_DATA7
>+#define SDMA3_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA3_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC0_MIDCMD_DATA8
>+#define SDMA3_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA3_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC0_MIDCMD_CNTL
>+#define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA3_RLC1_RB_CNTL
>+#define SDMA3_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA3_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA3_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA3_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA3_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA3_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA3_RLC1_RB_BASE
>+#define SDMA3_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA3_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA3_RLC1_RB_BASE_HI
>+#define SDMA3_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA3_RLC1_RB_RPTR
>+#define SDMA3_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC1_RB_RPTR_HI
>+#define SDMA3_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC1_RB_WPTR
>+#define SDMA3_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC1_RB_WPTR_HI
>+#define SDMA3_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC1_RB_WPTR_POLL_CNTL
>+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA3_RLC1_RB_RPTR_ADDR_HI
>+#define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA3_RLC1_RB_RPTR_ADDR_LO
>+#define SDMA3_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA3_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA3_RLC1_IB_CNTL
>+#define SDMA3_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA3_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA3_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA3_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA3_RLC1_IB_RPTR
>+#define SDMA3_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA3_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA3_RLC1_IB_OFFSET
>+#define SDMA3_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA3_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA3_RLC1_IB_BASE_LO
>+#define SDMA3_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA3_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA3_RLC1_IB_BASE_HI
>+#define SDMA3_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC1_IB_SIZE
>+#define SDMA3_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA3_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA3_RLC1_SKIP_CNTL
>+#define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA3_RLC1_CONTEXT_STATUS
>+#define SDMA3_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA3_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA3_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA3_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA3_RLC1_DOORBELL
>+#define SDMA3_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA3_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA3_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA3_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA3_RLC1_STATUS
>+#define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA3_RLC1_DOORBELL_LOG
>+#define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA3_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA3_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA3_RLC1_WATERMARK
>+#define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA3_RLC1_DOORBELL_OFFSET
>+#define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA3_RLC1_CSA_ADDR_LO
>+#define SDMA3_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA3_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA3_RLC1_CSA_ADDR_HI
>+#define SDMA3_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA3_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA3_RLC1_IB_SUB_REMAIN
>+#define SDMA3_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA3_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA3_RLC1_PREEMPT
>+#define SDMA3_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA3_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA3_RLC1_DUMMY_REG
>+#define SDMA3_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA3_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI
>+#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO
>+#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA3_RLC1_RB_AQL_CNTL
>+#define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA3_RLC1_MINOR_PTR_UPDATE
>+#define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA3_RLC1_MIDCMD_DATA0
>+#define SDMA3_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA3_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC1_MIDCMD_DATA1
>+#define SDMA3_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA3_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC1_MIDCMD_DATA2
>+#define SDMA3_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA3_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC1_MIDCMD_DATA3
>+#define SDMA3_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA3_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC1_MIDCMD_DATA4
>+#define SDMA3_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA3_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC1_MIDCMD_DATA5
>+#define SDMA3_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA3_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC1_MIDCMD_DATA6
>+#define SDMA3_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA3_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC1_MIDCMD_DATA7
>+#define SDMA3_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA3_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC1_MIDCMD_DATA8
>+#define SDMA3_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA3_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC1_MIDCMD_CNTL
>+#define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA3_RLC2_RB_CNTL
>+#define SDMA3_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA3_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA3_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA3_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA3_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA3_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA3_RLC2_RB_BASE
>+#define SDMA3_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA3_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA3_RLC2_RB_BASE_HI
>+#define SDMA3_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA3_RLC2_RB_RPTR
>+#define SDMA3_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC2_RB_RPTR_HI
>+#define SDMA3_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC2_RB_WPTR
>+#define SDMA3_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC2_RB_WPTR_HI
>+#define SDMA3_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC2_RB_WPTR_POLL_CNTL
>+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA3_RLC2_RB_RPTR_ADDR_HI
>+#define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA3_RLC2_RB_RPTR_ADDR_LO
>+#define SDMA3_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA3_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA3_RLC2_IB_CNTL
>+#define SDMA3_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA3_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA3_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA3_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA3_RLC2_IB_RPTR
>+#define SDMA3_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA3_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA3_RLC2_IB_OFFSET
>+#define SDMA3_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA3_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA3_RLC2_IB_BASE_LO
>+#define SDMA3_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA3_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA3_RLC2_IB_BASE_HI
>+#define SDMA3_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC2_IB_SIZE
>+#define SDMA3_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA3_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA3_RLC2_SKIP_CNTL
>+#define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA3_RLC2_CONTEXT_STATUS
>+#define SDMA3_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA3_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA3_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA3_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA3_RLC2_DOORBELL
>+#define SDMA3_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA3_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA3_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA3_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA3_RLC2_STATUS
>+#define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA3_RLC2_DOORBELL_LOG
>+#define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA3_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA3_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA3_RLC2_WATERMARK
>+#define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA3_RLC2_DOORBELL_OFFSET
>+#define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA3_RLC2_CSA_ADDR_LO
>+#define SDMA3_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA3_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA3_RLC2_CSA_ADDR_HI
>+#define SDMA3_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA3_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA3_RLC2_IB_SUB_REMAIN
>+#define SDMA3_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA3_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA3_RLC2_PREEMPT
>+#define SDMA3_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA3_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA3_RLC2_DUMMY_REG
>+#define SDMA3_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA3_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI
>+#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO
>+#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA3_RLC2_RB_AQL_CNTL
>+#define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA3_RLC2_MINOR_PTR_UPDATE
>+#define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA3_RLC2_MIDCMD_DATA0
>+#define SDMA3_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA3_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC2_MIDCMD_DATA1
>+#define SDMA3_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA3_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC2_MIDCMD_DATA2
>+#define SDMA3_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA3_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC2_MIDCMD_DATA3
>+#define SDMA3_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA3_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC2_MIDCMD_DATA4
>+#define SDMA3_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA3_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC2_MIDCMD_DATA5
>+#define SDMA3_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA3_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC2_MIDCMD_DATA6
>+#define SDMA3_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA3_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC2_MIDCMD_DATA7
>+#define SDMA3_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA3_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC2_MIDCMD_DATA8
>+#define SDMA3_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA3_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC2_MIDCMD_CNTL
>+#define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA3_RLC3_RB_CNTL
>+#define SDMA3_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA3_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA3_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA3_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA3_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA3_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA3_RLC3_RB_BASE
>+#define SDMA3_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA3_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA3_RLC3_RB_BASE_HI
>+#define SDMA3_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA3_RLC3_RB_RPTR
>+#define SDMA3_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC3_RB_RPTR_HI
>+#define SDMA3_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC3_RB_WPTR
>+#define SDMA3_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC3_RB_WPTR_HI
>+#define SDMA3_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC3_RB_WPTR_POLL_CNTL
>+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA3_RLC3_RB_RPTR_ADDR_HI
>+#define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA3_RLC3_RB_RPTR_ADDR_LO
>+#define SDMA3_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA3_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA3_RLC3_IB_CNTL
>+#define SDMA3_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA3_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA3_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA3_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA3_RLC3_IB_RPTR
>+#define SDMA3_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA3_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA3_RLC3_IB_OFFSET
>+#define SDMA3_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA3_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA3_RLC3_IB_BASE_LO
>+#define SDMA3_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA3_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA3_RLC3_IB_BASE_HI
>+#define SDMA3_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC3_IB_SIZE
>+#define SDMA3_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA3_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA3_RLC3_SKIP_CNTL
>+#define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA3_RLC3_CONTEXT_STATUS
>+#define SDMA3_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA3_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA3_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA3_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA3_RLC3_DOORBELL
>+#define SDMA3_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA3_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA3_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA3_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA3_RLC3_STATUS
>+#define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA3_RLC3_DOORBELL_LOG
>+#define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA3_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA3_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA3_RLC3_WATERMARK
>+#define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA3_RLC3_DOORBELL_OFFSET
>+#define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA3_RLC3_CSA_ADDR_LO
>+#define SDMA3_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA3_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA3_RLC3_CSA_ADDR_HI
>+#define SDMA3_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA3_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA3_RLC3_IB_SUB_REMAIN
>+#define SDMA3_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA3_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA3_RLC3_PREEMPT
>+#define SDMA3_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA3_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA3_RLC3_DUMMY_REG
>+#define SDMA3_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA3_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI
>+#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO
>+#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA3_RLC3_RB_AQL_CNTL
>+#define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA3_RLC3_MINOR_PTR_UPDATE
>+#define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA3_RLC3_MIDCMD_DATA0
>+#define SDMA3_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA3_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC3_MIDCMD_DATA1
>+#define SDMA3_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA3_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC3_MIDCMD_DATA2
>+#define SDMA3_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA3_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC3_MIDCMD_DATA3
>+#define SDMA3_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA3_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC3_MIDCMD_DATA4
>+#define SDMA3_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA3_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC3_MIDCMD_DATA5
>+#define SDMA3_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA3_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC3_MIDCMD_DATA6
>+#define SDMA3_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA3_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC3_MIDCMD_DATA7
>+#define SDMA3_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA3_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC3_MIDCMD_DATA8
>+#define SDMA3_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA3_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC3_MIDCMD_CNTL
>+#define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA3_RLC4_RB_CNTL
>+#define SDMA3_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA3_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA3_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA3_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA3_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA3_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA3_RLC4_RB_BASE
>+#define SDMA3_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA3_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA3_RLC4_RB_BASE_HI
>+#define SDMA3_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA3_RLC4_RB_RPTR
>+#define SDMA3_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC4_RB_RPTR_HI
>+#define SDMA3_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC4_RB_WPTR
>+#define SDMA3_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC4_RB_WPTR_HI
>+#define SDMA3_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC4_RB_WPTR_POLL_CNTL
>+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA3_RLC4_RB_RPTR_ADDR_HI
>+#define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA3_RLC4_RB_RPTR_ADDR_LO
>+#define SDMA3_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA3_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA3_RLC4_IB_CNTL
>+#define SDMA3_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA3_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA3_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA3_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA3_RLC4_IB_RPTR
>+#define SDMA3_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA3_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA3_RLC4_IB_OFFSET
>+#define SDMA3_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA3_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA3_RLC4_IB_BASE_LO
>+#define SDMA3_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA3_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA3_RLC4_IB_BASE_HI
>+#define SDMA3_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC4_IB_SIZE
>+#define SDMA3_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA3_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA3_RLC4_SKIP_CNTL
>+#define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA3_RLC4_CONTEXT_STATUS
>+#define SDMA3_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA3_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA3_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA3_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA3_RLC4_DOORBELL
>+#define SDMA3_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA3_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA3_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA3_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA3_RLC4_STATUS
>+#define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA3_RLC4_DOORBELL_LOG
>+#define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA3_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA3_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA3_RLC4_WATERMARK
>+#define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA3_RLC4_DOORBELL_OFFSET
>+#define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA3_RLC4_CSA_ADDR_LO
>+#define SDMA3_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA3_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA3_RLC4_CSA_ADDR_HI
>+#define SDMA3_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA3_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA3_RLC4_IB_SUB_REMAIN
>+#define SDMA3_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA3_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA3_RLC4_PREEMPT
>+#define SDMA3_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA3_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA3_RLC4_DUMMY_REG
>+#define SDMA3_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA3_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI
>+#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO
>+#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA3_RLC4_RB_AQL_CNTL
>+#define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA3_RLC4_MINOR_PTR_UPDATE
>+#define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA3_RLC4_MIDCMD_DATA0
>+#define SDMA3_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA3_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC4_MIDCMD_DATA1
>+#define SDMA3_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA3_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC4_MIDCMD_DATA2
>+#define SDMA3_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA3_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC4_MIDCMD_DATA3
>+#define SDMA3_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA3_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC4_MIDCMD_DATA4
>+#define SDMA3_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA3_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC4_MIDCMD_DATA5
>+#define SDMA3_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA3_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC4_MIDCMD_DATA6
>+#define SDMA3_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA3_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC4_MIDCMD_DATA7
>+#define SDMA3_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA3_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC4_MIDCMD_DATA8
>+#define SDMA3_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA3_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC4_MIDCMD_CNTL
>+#define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA3_RLC5_RB_CNTL
>+#define SDMA3_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA3_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA3_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA3_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA3_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA3_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA3_RLC5_RB_BASE
>+#define SDMA3_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA3_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA3_RLC5_RB_BASE_HI
>+#define SDMA3_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA3_RLC5_RB_RPTR
>+#define SDMA3_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC5_RB_RPTR_HI
>+#define SDMA3_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC5_RB_WPTR
>+#define SDMA3_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC5_RB_WPTR_HI
>+#define SDMA3_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC5_RB_WPTR_POLL_CNTL
>+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA3_RLC5_RB_RPTR_ADDR_HI
>+#define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA3_RLC5_RB_RPTR_ADDR_LO
>+#define SDMA3_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA3_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA3_RLC5_IB_CNTL
>+#define SDMA3_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA3_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA3_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA3_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA3_RLC5_IB_RPTR
>+#define SDMA3_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA3_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA3_RLC5_IB_OFFSET
>+#define SDMA3_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA3_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA3_RLC5_IB_BASE_LO
>+#define SDMA3_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA3_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA3_RLC5_IB_BASE_HI
>+#define SDMA3_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC5_IB_SIZE
>+#define SDMA3_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA3_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA3_RLC5_SKIP_CNTL
>+#define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA3_RLC5_CONTEXT_STATUS
>+#define SDMA3_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA3_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA3_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA3_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA3_RLC5_DOORBELL
>+#define SDMA3_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA3_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA3_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA3_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA3_RLC5_STATUS
>+#define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA3_RLC5_DOORBELL_LOG
>+#define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA3_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA3_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA3_RLC5_WATERMARK
>+#define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA3_RLC5_DOORBELL_OFFSET
>+#define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA3_RLC5_CSA_ADDR_LO
>+#define SDMA3_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA3_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA3_RLC5_CSA_ADDR_HI
>+#define SDMA3_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA3_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA3_RLC5_IB_SUB_REMAIN
>+#define SDMA3_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA3_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA3_RLC5_PREEMPT
>+#define SDMA3_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA3_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA3_RLC5_DUMMY_REG
>+#define SDMA3_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA3_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI
>+#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO
>+#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA3_RLC5_RB_AQL_CNTL
>+#define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA3_RLC5_MINOR_PTR_UPDATE
>+#define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA3_RLC5_MIDCMD_DATA0
>+#define SDMA3_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA3_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC5_MIDCMD_DATA1
>+#define SDMA3_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA3_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC5_MIDCMD_DATA2
>+#define SDMA3_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA3_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC5_MIDCMD_DATA3
>+#define SDMA3_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA3_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC5_MIDCMD_DATA4
>+#define SDMA3_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA3_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC5_MIDCMD_DATA5
>+#define SDMA3_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA3_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC5_MIDCMD_DATA6
>+#define SDMA3_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA3_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC5_MIDCMD_DATA7
>+#define SDMA3_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA3_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC5_MIDCMD_DATA8
>+#define SDMA3_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA3_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC5_MIDCMD_CNTL
>+#define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA3_RLC6_RB_CNTL
>+#define SDMA3_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA3_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA3_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA3_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA3_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA3_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA3_RLC6_RB_BASE
>+#define SDMA3_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA3_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA3_RLC6_RB_BASE_HI
>+#define SDMA3_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA3_RLC6_RB_RPTR
>+#define SDMA3_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC6_RB_RPTR_HI
>+#define SDMA3_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC6_RB_WPTR
>+#define SDMA3_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC6_RB_WPTR_HI
>+#define SDMA3_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC6_RB_WPTR_POLL_CNTL
>+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA3_RLC6_RB_RPTR_ADDR_HI
>+#define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA3_RLC6_RB_RPTR_ADDR_LO
>+#define SDMA3_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA3_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA3_RLC6_IB_CNTL
>+#define SDMA3_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA3_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA3_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA3_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA3_RLC6_IB_RPTR
>+#define SDMA3_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA3_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA3_RLC6_IB_OFFSET
>+#define SDMA3_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA3_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA3_RLC6_IB_BASE_LO
>+#define SDMA3_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA3_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA3_RLC6_IB_BASE_HI
>+#define SDMA3_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC6_IB_SIZE
>+#define SDMA3_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA3_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA3_RLC6_SKIP_CNTL
>+#define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA3_RLC6_CONTEXT_STATUS
>+#define SDMA3_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA3_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA3_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA3_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA3_RLC6_DOORBELL
>+#define SDMA3_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA3_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA3_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA3_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA3_RLC6_STATUS
>+#define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA3_RLC6_DOORBELL_LOG
>+#define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA3_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA3_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA3_RLC6_WATERMARK
>+#define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA3_RLC6_DOORBELL_OFFSET
>+#define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA3_RLC6_CSA_ADDR_LO
>+#define SDMA3_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA3_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA3_RLC6_CSA_ADDR_HI
>+#define SDMA3_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA3_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA3_RLC6_IB_SUB_REMAIN
>+#define SDMA3_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA3_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA3_RLC6_PREEMPT
>+#define SDMA3_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA3_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA3_RLC6_DUMMY_REG
>+#define SDMA3_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA3_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI
>+#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO
>+#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA3_RLC6_RB_AQL_CNTL
>+#define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA3_RLC6_MINOR_PTR_UPDATE
>+#define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA3_RLC6_MIDCMD_DATA0
>+#define SDMA3_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA3_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC6_MIDCMD_DATA1
>+#define SDMA3_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA3_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC6_MIDCMD_DATA2
>+#define SDMA3_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA3_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC6_MIDCMD_DATA3
>+#define SDMA3_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA3_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC6_MIDCMD_DATA4
>+#define SDMA3_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA3_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC6_MIDCMD_DATA5
>+#define SDMA3_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA3_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC6_MIDCMD_DATA6
>+#define SDMA3_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA3_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC6_MIDCMD_DATA7
>+#define SDMA3_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA3_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC6_MIDCMD_DATA8
>+#define SDMA3_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA3_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC6_MIDCMD_CNTL
>+#define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA3_RLC7_RB_CNTL
>+#define SDMA3_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA3_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA3_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA3_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA3_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA3_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA3_RLC7_RB_BASE
>+#define SDMA3_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA3_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA3_RLC7_RB_BASE_HI
>+#define SDMA3_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA3_RLC7_RB_RPTR
>+#define SDMA3_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC7_RB_RPTR_HI
>+#define SDMA3_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC7_RB_WPTR
>+#define SDMA3_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA3_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA3_RLC7_RB_WPTR_HI
>+#define SDMA3_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA3_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA3_RLC7_RB_WPTR_POLL_CNTL
>+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA3_RLC7_RB_RPTR_ADDR_HI
>+#define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA3_RLC7_RB_RPTR_ADDR_LO
>+#define SDMA3_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA3_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA3_RLC7_IB_CNTL
>+#define SDMA3_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA3_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA3_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA3_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA3_RLC7_IB_RPTR
>+#define SDMA3_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA3_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA3_RLC7_IB_OFFSET
>+#define SDMA3_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA3_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA3_RLC7_IB_BASE_LO
>+#define SDMA3_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA3_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA3_RLC7_IB_BASE_HI
>+#define SDMA3_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA3_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC7_IB_SIZE
>+#define SDMA3_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA3_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA3_RLC7_SKIP_CNTL
>+#define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA3_RLC7_CONTEXT_STATUS
>+#define SDMA3_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA3_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA3_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA3_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA3_RLC7_DOORBELL
>+#define SDMA3_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA3_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA3_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA3_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA3_RLC7_STATUS
>+#define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA3_RLC7_DOORBELL_LOG
>+#define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA3_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA3_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA3_RLC7_WATERMARK
>+#define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA3_RLC7_DOORBELL_OFFSET
>+#define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA3_RLC7_CSA_ADDR_LO
>+#define SDMA3_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA3_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA3_RLC7_CSA_ADDR_HI
>+#define SDMA3_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA3_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA3_RLC7_IB_SUB_REMAIN
>+#define SDMA3_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA3_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA3_RLC7_PREEMPT
>+#define SDMA3_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA3_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA3_RLC7_DUMMY_REG
>+#define SDMA3_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA3_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI
>+#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO
>+#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA3_RLC7_RB_AQL_CNTL
>+#define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA3_RLC7_MINOR_PTR_UPDATE
>+#define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA3_RLC7_MIDCMD_DATA0
>+#define SDMA3_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA3_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC7_MIDCMD_DATA1
>+#define SDMA3_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA3_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC7_MIDCMD_DATA2
>+#define SDMA3_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA3_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC7_MIDCMD_DATA3
>+#define SDMA3_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA3_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC7_MIDCMD_DATA4
>+#define SDMA3_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA3_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC7_MIDCMD_DATA5
>+#define SDMA3_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA3_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC7_MIDCMD_DATA6
>+#define SDMA3_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA3_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC7_MIDCMD_DATA7
>+#define SDMA3_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA3_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC7_MIDCMD_DATA8
>+#define SDMA3_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA3_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA3_RLC7_MIDCMD_CNTL
>+#define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_offset.h	2019-08-31 15:01:11.932736175 -0500
>@@ -0,0 +1,1043 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma4_4_2_2_OFFSET_HEADER
>+#define _sdma4_4_2_2_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: sdma4_sdma4dec
>+// base address: 0x7a000
>+#define mmSDMA4_UCODE_ADDR                                                                             0x0000
>+#define mmSDMA4_UCODE_ADDR_BASE_IDX                                                                    1
>+#define mmSDMA4_UCODE_DATA                                                                             0x0001
>+#define mmSDMA4_UCODE_DATA_BASE_IDX                                                                    1
>+#define mmSDMA4_VM_CNTL                                                                                0x0004
>+#define mmSDMA4_VM_CNTL_BASE_IDX                                                                       1
>+#define mmSDMA4_VM_CTX_LO                                                                              0x0005
>+#define mmSDMA4_VM_CTX_LO_BASE_IDX                                                                     1
>+#define mmSDMA4_VM_CTX_HI                                                                              0x0006
>+#define mmSDMA4_VM_CTX_HI_BASE_IDX                                                                     1
>+#define mmSDMA4_ACTIVE_FCN_ID                                                                          0x0007
>+#define mmSDMA4_ACTIVE_FCN_ID_BASE_IDX                                                                 1
>+#define mmSDMA4_VM_CTX_CNTL                                                                            0x0008
>+#define mmSDMA4_VM_CTX_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA4_VIRT_RESET_REQ                                                                         0x0009
>+#define mmSDMA4_VIRT_RESET_REQ_BASE_IDX                                                                1
>+#define mmSDMA4_VF_ENABLE                                                                              0x000a
>+#define mmSDMA4_VF_ENABLE_BASE_IDX                                                                     1
>+#define mmSDMA4_CONTEXT_REG_TYPE0                                                                      0x000b
>+#define mmSDMA4_CONTEXT_REG_TYPE0_BASE_IDX                                                             1
>+#define mmSDMA4_CONTEXT_REG_TYPE1                                                                      0x000c
>+#define mmSDMA4_CONTEXT_REG_TYPE1_BASE_IDX                                                             1
>+#define mmSDMA4_CONTEXT_REG_TYPE2                                                                      0x000d
>+#define mmSDMA4_CONTEXT_REG_TYPE2_BASE_IDX                                                             1
>+#define mmSDMA4_CONTEXT_REG_TYPE3                                                                      0x000e
>+#define mmSDMA4_CONTEXT_REG_TYPE3_BASE_IDX                                                             1
>+#define mmSDMA4_PUB_REG_TYPE0                                                                          0x000f
>+#define mmSDMA4_PUB_REG_TYPE0_BASE_IDX                                                                 1
>+#define mmSDMA4_PUB_REG_TYPE1                                                                          0x0010
>+#define mmSDMA4_PUB_REG_TYPE1_BASE_IDX                                                                 1
>+#define mmSDMA4_PUB_REG_TYPE2                                                                          0x0011
>+#define mmSDMA4_PUB_REG_TYPE2_BASE_IDX                                                                 1
>+#define mmSDMA4_PUB_REG_TYPE3                                                                          0x0012
>+#define mmSDMA4_PUB_REG_TYPE3_BASE_IDX                                                                 1
>+#define mmSDMA4_MMHUB_CNTL                                                                             0x0013
>+#define mmSDMA4_MMHUB_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA4_CONTEXT_GROUP_BOUNDARY                                                                 0x0019
>+#define mmSDMA4_CONTEXT_GROUP_BOUNDARY_BASE_IDX                                                        1
>+#define mmSDMA4_POWER_CNTL                                                                             0x001a
>+#define mmSDMA4_POWER_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA4_CLK_CTRL                                                                               0x001b
>+#define mmSDMA4_CLK_CTRL_BASE_IDX                                                                      1
>+#define mmSDMA4_CNTL                                                                                   0x001c
>+#define mmSDMA4_CNTL_BASE_IDX                                                                          1
>+#define mmSDMA4_CHICKEN_BITS                                                                           0x001d
>+#define mmSDMA4_CHICKEN_BITS_BASE_IDX                                                                  1
>+#define mmSDMA4_GB_ADDR_CONFIG                                                                         0x001e
>+#define mmSDMA4_GB_ADDR_CONFIG_BASE_IDX                                                                1
>+#define mmSDMA4_GB_ADDR_CONFIG_READ                                                                    0x001f
>+#define mmSDMA4_GB_ADDR_CONFIG_READ_BASE_IDX                                                           1
>+#define mmSDMA4_RB_RPTR_FETCH_HI                                                                       0x0020
>+#define mmSDMA4_RB_RPTR_FETCH_HI_BASE_IDX                                                              1
>+#define mmSDMA4_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0021
>+#define mmSDMA4_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      1
>+#define mmSDMA4_RB_RPTR_FETCH                                                                          0x0022
>+#define mmSDMA4_RB_RPTR_FETCH_BASE_IDX                                                                 1
>+#define mmSDMA4_IB_OFFSET_FETCH                                                                        0x0023
>+#define mmSDMA4_IB_OFFSET_FETCH_BASE_IDX                                                               1
>+#define mmSDMA4_PROGRAM                                                                                0x0024
>+#define mmSDMA4_PROGRAM_BASE_IDX                                                                       1
>+#define mmSDMA4_STATUS_REG                                                                             0x0025
>+#define mmSDMA4_STATUS_REG_BASE_IDX                                                                    1
>+#define mmSDMA4_STATUS1_REG                                                                            0x0026
>+#define mmSDMA4_STATUS1_REG_BASE_IDX                                                                   1
>+#define mmSDMA4_RD_BURST_CNTL                                                                          0x0027
>+#define mmSDMA4_RD_BURST_CNTL_BASE_IDX                                                                 1
>+#define mmSDMA4_HBM_PAGE_CONFIG                                                                        0x0028
>+#define mmSDMA4_HBM_PAGE_CONFIG_BASE_IDX                                                               1
>+#define mmSDMA4_UCODE_CHECKSUM                                                                         0x0029
>+#define mmSDMA4_UCODE_CHECKSUM_BASE_IDX                                                                1
>+#define mmSDMA4_F32_CNTL                                                                               0x002a
>+#define mmSDMA4_F32_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA4_FREEZE                                                                                 0x002b
>+#define mmSDMA4_FREEZE_BASE_IDX                                                                        1
>+#define mmSDMA4_PHASE0_QUANTUM                                                                         0x002c
>+#define mmSDMA4_PHASE0_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA4_PHASE1_QUANTUM                                                                         0x002d
>+#define mmSDMA4_PHASE1_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA4_EDC_CONFIG                                                                             0x0032
>+#define mmSDMA4_EDC_CONFIG_BASE_IDX                                                                    1
>+#define mmSDMA4_BA_THRESHOLD                                                                           0x0033
>+#define mmSDMA4_BA_THRESHOLD_BASE_IDX                                                                  1
>+#define mmSDMA4_ID                                                                                     0x0034
>+#define mmSDMA4_ID_BASE_IDX                                                                            1
>+#define mmSDMA4_VERSION                                                                                0x0035
>+#define mmSDMA4_VERSION_BASE_IDX                                                                       1
>+#define mmSDMA4_EDC_COUNTER                                                                            0x0036
>+#define mmSDMA4_EDC_COUNTER_BASE_IDX                                                                   1
>+#define mmSDMA4_EDC_COUNTER_CLEAR                                                                      0x0037
>+#define mmSDMA4_EDC_COUNTER_CLEAR_BASE_IDX                                                             1
>+#define mmSDMA4_STATUS2_REG                                                                            0x0038
>+#define mmSDMA4_STATUS2_REG_BASE_IDX                                                                   1
>+#define mmSDMA4_ATOMIC_CNTL                                                                            0x0039
>+#define mmSDMA4_ATOMIC_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA4_ATOMIC_PREOP_LO                                                                        0x003a
>+#define mmSDMA4_ATOMIC_PREOP_LO_BASE_IDX                                                               1
>+#define mmSDMA4_ATOMIC_PREOP_HI                                                                        0x003b
>+#define mmSDMA4_ATOMIC_PREOP_HI_BASE_IDX                                                               1
>+#define mmSDMA4_UTCL1_CNTL                                                                             0x003c
>+#define mmSDMA4_UTCL1_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA4_UTCL1_WATERMK                                                                          0x003d
>+#define mmSDMA4_UTCL1_WATERMK_BASE_IDX                                                                 1
>+#define mmSDMA4_UTCL1_RD_STATUS                                                                        0x003e
>+#define mmSDMA4_UTCL1_RD_STATUS_BASE_IDX                                                               1
>+#define mmSDMA4_UTCL1_WR_STATUS                                                                        0x003f
>+#define mmSDMA4_UTCL1_WR_STATUS_BASE_IDX                                                               1
>+#define mmSDMA4_UTCL1_INV0                                                                             0x0040
>+#define mmSDMA4_UTCL1_INV0_BASE_IDX                                                                    1
>+#define mmSDMA4_UTCL1_INV1                                                                             0x0041
>+#define mmSDMA4_UTCL1_INV1_BASE_IDX                                                                    1
>+#define mmSDMA4_UTCL1_INV2                                                                             0x0042
>+#define mmSDMA4_UTCL1_INV2_BASE_IDX                                                                    1
>+#define mmSDMA4_UTCL1_RD_XNACK0                                                                        0x0043
>+#define mmSDMA4_UTCL1_RD_XNACK0_BASE_IDX                                                               1
>+#define mmSDMA4_UTCL1_RD_XNACK1                                                                        0x0044
>+#define mmSDMA4_UTCL1_RD_XNACK1_BASE_IDX                                                               1
>+#define mmSDMA4_UTCL1_WR_XNACK0                                                                        0x0045
>+#define mmSDMA4_UTCL1_WR_XNACK0_BASE_IDX                                                               1
>+#define mmSDMA4_UTCL1_WR_XNACK1                                                                        0x0046
>+#define mmSDMA4_UTCL1_WR_XNACK1_BASE_IDX                                                               1
>+#define mmSDMA4_UTCL1_TIMEOUT                                                                          0x0047
>+#define mmSDMA4_UTCL1_TIMEOUT_BASE_IDX                                                                 1
>+#define mmSDMA4_UTCL1_PAGE                                                                             0x0048
>+#define mmSDMA4_UTCL1_PAGE_BASE_IDX                                                                    1
>+#define mmSDMA4_POWER_CNTL_IDLE                                                                        0x0049
>+#define mmSDMA4_POWER_CNTL_IDLE_BASE_IDX                                                               1
>+#define mmSDMA4_RELAX_ORDERING_LUT                                                                     0x004a
>+#define mmSDMA4_RELAX_ORDERING_LUT_BASE_IDX                                                            1
>+#define mmSDMA4_CHICKEN_BITS_2                                                                         0x004b
>+#define mmSDMA4_CHICKEN_BITS_2_BASE_IDX                                                                1
>+#define mmSDMA4_STATUS3_REG                                                                            0x004c
>+#define mmSDMA4_STATUS3_REG_BASE_IDX                                                                   1
>+#define mmSDMA4_PHYSICAL_ADDR_LO                                                                       0x004d
>+#define mmSDMA4_PHYSICAL_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA4_PHYSICAL_ADDR_HI                                                                       0x004e
>+#define mmSDMA4_PHYSICAL_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA4_PHASE2_QUANTUM                                                                         0x004f
>+#define mmSDMA4_PHASE2_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA4_ERROR_LOG                                                                              0x0050
>+#define mmSDMA4_ERROR_LOG_BASE_IDX                                                                     1
>+#define mmSDMA4_PUB_DUMMY_REG0                                                                         0x0051
>+#define mmSDMA4_PUB_DUMMY_REG0_BASE_IDX                                                                1
>+#define mmSDMA4_PUB_DUMMY_REG1                                                                         0x0052
>+#define mmSDMA4_PUB_DUMMY_REG1_BASE_IDX                                                                1
>+#define mmSDMA4_PUB_DUMMY_REG2                                                                         0x0053
>+#define mmSDMA4_PUB_DUMMY_REG2_BASE_IDX                                                                1
>+#define mmSDMA4_PUB_DUMMY_REG3                                                                         0x0054
>+#define mmSDMA4_PUB_DUMMY_REG3_BASE_IDX                                                                1
>+#define mmSDMA4_F32_COUNTER                                                                            0x0055
>+#define mmSDMA4_F32_COUNTER_BASE_IDX                                                                   1
>+#define mmSDMA4_UNBREAKABLE                                                                            0x0056
>+#define mmSDMA4_UNBREAKABLE_BASE_IDX                                                                   1
>+#define mmSDMA4_PERFMON_CNTL                                                                           0x0057
>+#define mmSDMA4_PERFMON_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_PERFCOUNTER0_RESULT                                                                    0x0058
>+#define mmSDMA4_PERFCOUNTER0_RESULT_BASE_IDX                                                           1
>+#define mmSDMA4_PERFCOUNTER1_RESULT                                                                    0x0059
>+#define mmSDMA4_PERFCOUNTER1_RESULT_BASE_IDX                                                           1
>+#define mmSDMA4_PERFCOUNTER_TAG_DELAY_RANGE                                                            0x005a
>+#define mmSDMA4_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX                                                   1
>+#define mmSDMA4_CRD_CNTL                                                                               0x005b
>+#define mmSDMA4_CRD_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA4_GPU_IOV_VIOLATION_LOG                                                                  0x005d
>+#define mmSDMA4_GPU_IOV_VIOLATION_LOG_BASE_IDX                                                         1
>+#define mmSDMA4_ULV_CNTL                                                                               0x005e
>+#define mmSDMA4_ULV_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA4_EA_DBIT_ADDR_DATA                                                                      0x0060
>+#define mmSDMA4_EA_DBIT_ADDR_DATA_BASE_IDX                                                             1
>+#define mmSDMA4_EA_DBIT_ADDR_INDEX                                                                     0x0061
>+#define mmSDMA4_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            1
>+#define mmSDMA4_GPU_IOV_VIOLATION_LOG2                                                                 0x0062
>+#define mmSDMA4_GPU_IOV_VIOLATION_LOG2_BASE_IDX                                                        1
>+#define mmSDMA4_GFX_RB_CNTL                                                                            0x0080
>+#define mmSDMA4_GFX_RB_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA4_GFX_RB_BASE                                                                            0x0081
>+#define mmSDMA4_GFX_RB_BASE_BASE_IDX                                                                   1
>+#define mmSDMA4_GFX_RB_BASE_HI                                                                         0x0082
>+#define mmSDMA4_GFX_RB_BASE_HI_BASE_IDX                                                                1
>+#define mmSDMA4_GFX_RB_RPTR                                                                            0x0083
>+#define mmSDMA4_GFX_RB_RPTR_BASE_IDX                                                                   1
>+#define mmSDMA4_GFX_RB_RPTR_HI                                                                         0x0084
>+#define mmSDMA4_GFX_RB_RPTR_HI_BASE_IDX                                                                1
>+#define mmSDMA4_GFX_RB_WPTR                                                                            0x0085
>+#define mmSDMA4_GFX_RB_WPTR_BASE_IDX                                                                   1
>+#define mmSDMA4_GFX_RB_WPTR_HI                                                                         0x0086
>+#define mmSDMA4_GFX_RB_WPTR_HI_BASE_IDX                                                                1
>+#define mmSDMA4_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
>+#define mmSDMA4_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         1
>+#define mmSDMA4_GFX_RB_RPTR_ADDR_HI                                                                    0x0088
>+#define mmSDMA4_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           1
>+#define mmSDMA4_GFX_RB_RPTR_ADDR_LO                                                                    0x0089
>+#define mmSDMA4_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           1
>+#define mmSDMA4_GFX_IB_CNTL                                                                            0x008a
>+#define mmSDMA4_GFX_IB_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA4_GFX_IB_RPTR                                                                            0x008b
>+#define mmSDMA4_GFX_IB_RPTR_BASE_IDX                                                                   1
>+#define mmSDMA4_GFX_IB_OFFSET                                                                          0x008c
>+#define mmSDMA4_GFX_IB_OFFSET_BASE_IDX                                                                 1
>+#define mmSDMA4_GFX_IB_BASE_LO                                                                         0x008d
>+#define mmSDMA4_GFX_IB_BASE_LO_BASE_IDX                                                                1
>+#define mmSDMA4_GFX_IB_BASE_HI                                                                         0x008e
>+#define mmSDMA4_GFX_IB_BASE_HI_BASE_IDX                                                                1
>+#define mmSDMA4_GFX_IB_SIZE                                                                            0x008f
>+#define mmSDMA4_GFX_IB_SIZE_BASE_IDX                                                                   1
>+#define mmSDMA4_GFX_SKIP_CNTL                                                                          0x0090
>+#define mmSDMA4_GFX_SKIP_CNTL_BASE_IDX                                                                 1
>+#define mmSDMA4_GFX_CONTEXT_STATUS                                                                     0x0091
>+#define mmSDMA4_GFX_CONTEXT_STATUS_BASE_IDX                                                            1
>+#define mmSDMA4_GFX_DOORBELL                                                                           0x0092
>+#define mmSDMA4_GFX_DOORBELL_BASE_IDX                                                                  1
>+#define mmSDMA4_GFX_CONTEXT_CNTL                                                                       0x0093
>+#define mmSDMA4_GFX_CONTEXT_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_GFX_STATUS                                                                             0x00a8
>+#define mmSDMA4_GFX_STATUS_BASE_IDX                                                                    1
>+#define mmSDMA4_GFX_DOORBELL_LOG                                                                       0x00a9
>+#define mmSDMA4_GFX_DOORBELL_LOG_BASE_IDX                                                              1
>+#define mmSDMA4_GFX_WATERMARK                                                                          0x00aa
>+#define mmSDMA4_GFX_WATERMARK_BASE_IDX                                                                 1
>+#define mmSDMA4_GFX_DOORBELL_OFFSET                                                                    0x00ab
>+#define mmSDMA4_GFX_DOORBELL_OFFSET_BASE_IDX                                                           1
>+#define mmSDMA4_GFX_CSA_ADDR_LO                                                                        0x00ac
>+#define mmSDMA4_GFX_CSA_ADDR_LO_BASE_IDX                                                               1
>+#define mmSDMA4_GFX_CSA_ADDR_HI                                                                        0x00ad
>+#define mmSDMA4_GFX_CSA_ADDR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_GFX_IB_SUB_REMAIN                                                                      0x00af
>+#define mmSDMA4_GFX_IB_SUB_REMAIN_BASE_IDX                                                             1
>+#define mmSDMA4_GFX_PREEMPT                                                                            0x00b0
>+#define mmSDMA4_GFX_PREEMPT_BASE_IDX                                                                   1
>+#define mmSDMA4_GFX_DUMMY_REG                                                                          0x00b1
>+#define mmSDMA4_GFX_DUMMY_REG_BASE_IDX                                                                 1
>+#define mmSDMA4_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x00b2
>+#define mmSDMA4_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      1
>+#define mmSDMA4_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x00b3
>+#define mmSDMA4_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      1
>+#define mmSDMA4_GFX_RB_AQL_CNTL                                                                        0x00b4
>+#define mmSDMA4_GFX_RB_AQL_CNTL_BASE_IDX                                                               1
>+#define mmSDMA4_GFX_MINOR_PTR_UPDATE                                                                   0x00b5
>+#define mmSDMA4_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          1
>+#define mmSDMA4_GFX_MIDCMD_DATA0                                                                       0x00c0
>+#define mmSDMA4_GFX_MIDCMD_DATA0_BASE_IDX                                                              1
>+#define mmSDMA4_GFX_MIDCMD_DATA1                                                                       0x00c1
>+#define mmSDMA4_GFX_MIDCMD_DATA1_BASE_IDX                                                              1
>+#define mmSDMA4_GFX_MIDCMD_DATA2                                                                       0x00c2
>+#define mmSDMA4_GFX_MIDCMD_DATA2_BASE_IDX                                                              1
>+#define mmSDMA4_GFX_MIDCMD_DATA3                                                                       0x00c3
>+#define mmSDMA4_GFX_MIDCMD_DATA3_BASE_IDX                                                              1
>+#define mmSDMA4_GFX_MIDCMD_DATA4                                                                       0x00c4
>+#define mmSDMA4_GFX_MIDCMD_DATA4_BASE_IDX                                                              1
>+#define mmSDMA4_GFX_MIDCMD_DATA5                                                                       0x00c5
>+#define mmSDMA4_GFX_MIDCMD_DATA5_BASE_IDX                                                              1
>+#define mmSDMA4_GFX_MIDCMD_DATA6                                                                       0x00c6
>+#define mmSDMA4_GFX_MIDCMD_DATA6_BASE_IDX                                                              1
>+#define mmSDMA4_GFX_MIDCMD_DATA7                                                                       0x00c7
>+#define mmSDMA4_GFX_MIDCMD_DATA7_BASE_IDX                                                              1
>+#define mmSDMA4_GFX_MIDCMD_DATA8                                                                       0x00c8
>+#define mmSDMA4_GFX_MIDCMD_DATA8_BASE_IDX                                                              1
>+#define mmSDMA4_GFX_MIDCMD_CNTL                                                                        0x00c9
>+#define mmSDMA4_GFX_MIDCMD_CNTL_BASE_IDX                                                               1
>+#define mmSDMA4_PAGE_RB_CNTL                                                                           0x00d8
>+#define mmSDMA4_PAGE_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_PAGE_RB_BASE                                                                           0x00d9
>+#define mmSDMA4_PAGE_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA4_PAGE_RB_BASE_HI                                                                        0x00da
>+#define mmSDMA4_PAGE_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_PAGE_RB_RPTR                                                                           0x00db
>+#define mmSDMA4_PAGE_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_PAGE_RB_RPTR_HI                                                                        0x00dc
>+#define mmSDMA4_PAGE_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_PAGE_RB_WPTR                                                                           0x00dd
>+#define mmSDMA4_PAGE_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_PAGE_RB_WPTR_HI                                                                        0x00de
>+#define mmSDMA4_PAGE_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_PAGE_RB_WPTR_POLL_CNTL                                                                 0x00df
>+#define mmSDMA4_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA4_PAGE_RB_RPTR_ADDR_HI                                                                   0x00e0
>+#define mmSDMA4_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA4_PAGE_RB_RPTR_ADDR_LO                                                                   0x00e1
>+#define mmSDMA4_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA4_PAGE_IB_CNTL                                                                           0x00e2
>+#define mmSDMA4_PAGE_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_PAGE_IB_RPTR                                                                           0x00e3
>+#define mmSDMA4_PAGE_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_PAGE_IB_OFFSET                                                                         0x00e4
>+#define mmSDMA4_PAGE_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA4_PAGE_IB_BASE_LO                                                                        0x00e5
>+#define mmSDMA4_PAGE_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA4_PAGE_IB_BASE_HI                                                                        0x00e6
>+#define mmSDMA4_PAGE_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_PAGE_IB_SIZE                                                                           0x00e7
>+#define mmSDMA4_PAGE_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA4_PAGE_SKIP_CNTL                                                                         0x00e8
>+#define mmSDMA4_PAGE_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA4_PAGE_CONTEXT_STATUS                                                                    0x00e9
>+#define mmSDMA4_PAGE_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA4_PAGE_DOORBELL                                                                          0x00ea
>+#define mmSDMA4_PAGE_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA4_PAGE_STATUS                                                                            0x0100
>+#define mmSDMA4_PAGE_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA4_PAGE_DOORBELL_LOG                                                                      0x0101
>+#define mmSDMA4_PAGE_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA4_PAGE_WATERMARK                                                                         0x0102
>+#define mmSDMA4_PAGE_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA4_PAGE_DOORBELL_OFFSET                                                                   0x0103
>+#define mmSDMA4_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA4_PAGE_CSA_ADDR_LO                                                                       0x0104
>+#define mmSDMA4_PAGE_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA4_PAGE_CSA_ADDR_HI                                                                       0x0105
>+#define mmSDMA4_PAGE_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA4_PAGE_IB_SUB_REMAIN                                                                     0x0107
>+#define mmSDMA4_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA4_PAGE_PREEMPT                                                                           0x0108
>+#define mmSDMA4_PAGE_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA4_PAGE_DUMMY_REG                                                                         0x0109
>+#define mmSDMA4_PAGE_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x010a
>+#define mmSDMA4_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x010b
>+#define mmSDMA4_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA4_PAGE_RB_AQL_CNTL                                                                       0x010c
>+#define mmSDMA4_PAGE_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_PAGE_MINOR_PTR_UPDATE                                                                  0x010d
>+#define mmSDMA4_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA4_PAGE_MIDCMD_DATA0                                                                      0x0118
>+#define mmSDMA4_PAGE_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA4_PAGE_MIDCMD_DATA1                                                                      0x0119
>+#define mmSDMA4_PAGE_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA4_PAGE_MIDCMD_DATA2                                                                      0x011a
>+#define mmSDMA4_PAGE_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA4_PAGE_MIDCMD_DATA3                                                                      0x011b
>+#define mmSDMA4_PAGE_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA4_PAGE_MIDCMD_DATA4                                                                      0x011c
>+#define mmSDMA4_PAGE_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA4_PAGE_MIDCMD_DATA5                                                                      0x011d
>+#define mmSDMA4_PAGE_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA4_PAGE_MIDCMD_DATA6                                                                      0x011e
>+#define mmSDMA4_PAGE_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA4_PAGE_MIDCMD_DATA7                                                                      0x011f
>+#define mmSDMA4_PAGE_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA4_PAGE_MIDCMD_DATA8                                                                      0x0120
>+#define mmSDMA4_PAGE_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA4_PAGE_MIDCMD_CNTL                                                                       0x0121
>+#define mmSDMA4_PAGE_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC0_RB_CNTL                                                                           0x0130
>+#define mmSDMA4_RLC0_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC0_RB_BASE                                                                           0x0131
>+#define mmSDMA4_RLC0_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC0_RB_BASE_HI                                                                        0x0132
>+#define mmSDMA4_RLC0_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC0_RB_RPTR                                                                           0x0133
>+#define mmSDMA4_RLC0_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC0_RB_RPTR_HI                                                                        0x0134
>+#define mmSDMA4_RLC0_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC0_RB_WPTR                                                                           0x0135
>+#define mmSDMA4_RLC0_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC0_RB_WPTR_HI                                                                        0x0136
>+#define mmSDMA4_RLC0_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0137
>+#define mmSDMA4_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA4_RLC0_RB_RPTR_ADDR_HI                                                                   0x0138
>+#define mmSDMA4_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA4_RLC0_RB_RPTR_ADDR_LO                                                                   0x0139
>+#define mmSDMA4_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA4_RLC0_IB_CNTL                                                                           0x013a
>+#define mmSDMA4_RLC0_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC0_IB_RPTR                                                                           0x013b
>+#define mmSDMA4_RLC0_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC0_IB_OFFSET                                                                         0x013c
>+#define mmSDMA4_RLC0_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA4_RLC0_IB_BASE_LO                                                                        0x013d
>+#define mmSDMA4_RLC0_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA4_RLC0_IB_BASE_HI                                                                        0x013e
>+#define mmSDMA4_RLC0_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC0_IB_SIZE                                                                           0x013f
>+#define mmSDMA4_RLC0_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC0_SKIP_CNTL                                                                         0x0140
>+#define mmSDMA4_RLC0_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA4_RLC0_CONTEXT_STATUS                                                                    0x0141
>+#define mmSDMA4_RLC0_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA4_RLC0_DOORBELL                                                                          0x0142
>+#define mmSDMA4_RLC0_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA4_RLC0_STATUS                                                                            0x0158
>+#define mmSDMA4_RLC0_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA4_RLC0_DOORBELL_LOG                                                                      0x0159
>+#define mmSDMA4_RLC0_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA4_RLC0_WATERMARK                                                                         0x015a
>+#define mmSDMA4_RLC0_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA4_RLC0_DOORBELL_OFFSET                                                                   0x015b
>+#define mmSDMA4_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA4_RLC0_CSA_ADDR_LO                                                                       0x015c
>+#define mmSDMA4_RLC0_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA4_RLC0_CSA_ADDR_HI                                                                       0x015d
>+#define mmSDMA4_RLC0_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA4_RLC0_IB_SUB_REMAIN                                                                     0x015f
>+#define mmSDMA4_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA4_RLC0_PREEMPT                                                                           0x0160
>+#define mmSDMA4_RLC0_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC0_DUMMY_REG                                                                         0x0161
>+#define mmSDMA4_RLC0_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0162
>+#define mmSDMA4_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0163
>+#define mmSDMA4_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA4_RLC0_RB_AQL_CNTL                                                                       0x0164
>+#define mmSDMA4_RLC0_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC0_MINOR_PTR_UPDATE                                                                  0x0165
>+#define mmSDMA4_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA4_RLC0_MIDCMD_DATA0                                                                      0x0170
>+#define mmSDMA4_RLC0_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA4_RLC0_MIDCMD_DATA1                                                                      0x0171
>+#define mmSDMA4_RLC0_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA4_RLC0_MIDCMD_DATA2                                                                      0x0172
>+#define mmSDMA4_RLC0_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA4_RLC0_MIDCMD_DATA3                                                                      0x0173
>+#define mmSDMA4_RLC0_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA4_RLC0_MIDCMD_DATA4                                                                      0x0174
>+#define mmSDMA4_RLC0_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA4_RLC0_MIDCMD_DATA5                                                                      0x0175
>+#define mmSDMA4_RLC0_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA4_RLC0_MIDCMD_DATA6                                                                      0x0176
>+#define mmSDMA4_RLC0_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA4_RLC0_MIDCMD_DATA7                                                                      0x0177
>+#define mmSDMA4_RLC0_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA4_RLC0_MIDCMD_DATA8                                                                      0x0178
>+#define mmSDMA4_RLC0_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA4_RLC0_MIDCMD_CNTL                                                                       0x0179
>+#define mmSDMA4_RLC0_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC1_RB_CNTL                                                                           0x0188
>+#define mmSDMA4_RLC1_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC1_RB_BASE                                                                           0x0189
>+#define mmSDMA4_RLC1_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC1_RB_BASE_HI                                                                        0x018a
>+#define mmSDMA4_RLC1_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC1_RB_RPTR                                                                           0x018b
>+#define mmSDMA4_RLC1_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC1_RB_RPTR_HI                                                                        0x018c
>+#define mmSDMA4_RLC1_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC1_RB_WPTR                                                                           0x018d
>+#define mmSDMA4_RLC1_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC1_RB_WPTR_HI                                                                        0x018e
>+#define mmSDMA4_RLC1_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC1_RB_WPTR_POLL_CNTL                                                                 0x018f
>+#define mmSDMA4_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA4_RLC1_RB_RPTR_ADDR_HI                                                                   0x0190
>+#define mmSDMA4_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA4_RLC1_RB_RPTR_ADDR_LO                                                                   0x0191
>+#define mmSDMA4_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA4_RLC1_IB_CNTL                                                                           0x0192
>+#define mmSDMA4_RLC1_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC1_IB_RPTR                                                                           0x0193
>+#define mmSDMA4_RLC1_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC1_IB_OFFSET                                                                         0x0194
>+#define mmSDMA4_RLC1_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA4_RLC1_IB_BASE_LO                                                                        0x0195
>+#define mmSDMA4_RLC1_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA4_RLC1_IB_BASE_HI                                                                        0x0196
>+#define mmSDMA4_RLC1_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC1_IB_SIZE                                                                           0x0197
>+#define mmSDMA4_RLC1_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC1_SKIP_CNTL                                                                         0x0198
>+#define mmSDMA4_RLC1_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA4_RLC1_CONTEXT_STATUS                                                                    0x0199
>+#define mmSDMA4_RLC1_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA4_RLC1_DOORBELL                                                                          0x019a
>+#define mmSDMA4_RLC1_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA4_RLC1_STATUS                                                                            0x01b0
>+#define mmSDMA4_RLC1_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA4_RLC1_DOORBELL_LOG                                                                      0x01b1
>+#define mmSDMA4_RLC1_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA4_RLC1_WATERMARK                                                                         0x01b2
>+#define mmSDMA4_RLC1_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA4_RLC1_DOORBELL_OFFSET                                                                   0x01b3
>+#define mmSDMA4_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA4_RLC1_CSA_ADDR_LO                                                                       0x01b4
>+#define mmSDMA4_RLC1_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA4_RLC1_CSA_ADDR_HI                                                                       0x01b5
>+#define mmSDMA4_RLC1_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA4_RLC1_IB_SUB_REMAIN                                                                     0x01b7
>+#define mmSDMA4_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA4_RLC1_PREEMPT                                                                           0x01b8
>+#define mmSDMA4_RLC1_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC1_DUMMY_REG                                                                         0x01b9
>+#define mmSDMA4_RLC1_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x01ba
>+#define mmSDMA4_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x01bb
>+#define mmSDMA4_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA4_RLC1_RB_AQL_CNTL                                                                       0x01bc
>+#define mmSDMA4_RLC1_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC1_MINOR_PTR_UPDATE                                                                  0x01bd
>+#define mmSDMA4_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA4_RLC1_MIDCMD_DATA0                                                                      0x01c8
>+#define mmSDMA4_RLC1_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA4_RLC1_MIDCMD_DATA1                                                                      0x01c9
>+#define mmSDMA4_RLC1_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA4_RLC1_MIDCMD_DATA2                                                                      0x01ca
>+#define mmSDMA4_RLC1_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA4_RLC1_MIDCMD_DATA3                                                                      0x01cb
>+#define mmSDMA4_RLC1_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA4_RLC1_MIDCMD_DATA4                                                                      0x01cc
>+#define mmSDMA4_RLC1_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA4_RLC1_MIDCMD_DATA5                                                                      0x01cd
>+#define mmSDMA4_RLC1_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA4_RLC1_MIDCMD_DATA6                                                                      0x01ce
>+#define mmSDMA4_RLC1_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA4_RLC1_MIDCMD_DATA7                                                                      0x01cf
>+#define mmSDMA4_RLC1_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA4_RLC1_MIDCMD_DATA8                                                                      0x01d0
>+#define mmSDMA4_RLC1_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA4_RLC1_MIDCMD_CNTL                                                                       0x01d1
>+#define mmSDMA4_RLC1_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC2_RB_CNTL                                                                           0x01e0
>+#define mmSDMA4_RLC2_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC2_RB_BASE                                                                           0x01e1
>+#define mmSDMA4_RLC2_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC2_RB_BASE_HI                                                                        0x01e2
>+#define mmSDMA4_RLC2_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC2_RB_RPTR                                                                           0x01e3
>+#define mmSDMA4_RLC2_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC2_RB_RPTR_HI                                                                        0x01e4
>+#define mmSDMA4_RLC2_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC2_RB_WPTR                                                                           0x01e5
>+#define mmSDMA4_RLC2_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC2_RB_WPTR_HI                                                                        0x01e6
>+#define mmSDMA4_RLC2_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC2_RB_WPTR_POLL_CNTL                                                                 0x01e7
>+#define mmSDMA4_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA4_RLC2_RB_RPTR_ADDR_HI                                                                   0x01e8
>+#define mmSDMA4_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA4_RLC2_RB_RPTR_ADDR_LO                                                                   0x01e9
>+#define mmSDMA4_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA4_RLC2_IB_CNTL                                                                           0x01ea
>+#define mmSDMA4_RLC2_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC2_IB_RPTR                                                                           0x01eb
>+#define mmSDMA4_RLC2_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC2_IB_OFFSET                                                                         0x01ec
>+#define mmSDMA4_RLC2_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA4_RLC2_IB_BASE_LO                                                                        0x01ed
>+#define mmSDMA4_RLC2_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA4_RLC2_IB_BASE_HI                                                                        0x01ee
>+#define mmSDMA4_RLC2_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC2_IB_SIZE                                                                           0x01ef
>+#define mmSDMA4_RLC2_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC2_SKIP_CNTL                                                                         0x01f0
>+#define mmSDMA4_RLC2_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA4_RLC2_CONTEXT_STATUS                                                                    0x01f1
>+#define mmSDMA4_RLC2_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA4_RLC2_DOORBELL                                                                          0x01f2
>+#define mmSDMA4_RLC2_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA4_RLC2_STATUS                                                                            0x0208
>+#define mmSDMA4_RLC2_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA4_RLC2_DOORBELL_LOG                                                                      0x0209
>+#define mmSDMA4_RLC2_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA4_RLC2_WATERMARK                                                                         0x020a
>+#define mmSDMA4_RLC2_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA4_RLC2_DOORBELL_OFFSET                                                                   0x020b
>+#define mmSDMA4_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA4_RLC2_CSA_ADDR_LO                                                                       0x020c
>+#define mmSDMA4_RLC2_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA4_RLC2_CSA_ADDR_HI                                                                       0x020d
>+#define mmSDMA4_RLC2_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA4_RLC2_IB_SUB_REMAIN                                                                     0x020f
>+#define mmSDMA4_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA4_RLC2_PREEMPT                                                                           0x0210
>+#define mmSDMA4_RLC2_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC2_DUMMY_REG                                                                         0x0211
>+#define mmSDMA4_RLC2_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0212
>+#define mmSDMA4_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0213
>+#define mmSDMA4_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA4_RLC2_RB_AQL_CNTL                                                                       0x0214
>+#define mmSDMA4_RLC2_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC2_MINOR_PTR_UPDATE                                                                  0x0215
>+#define mmSDMA4_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA4_RLC2_MIDCMD_DATA0                                                                      0x0220
>+#define mmSDMA4_RLC2_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA4_RLC2_MIDCMD_DATA1                                                                      0x0221
>+#define mmSDMA4_RLC2_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA4_RLC2_MIDCMD_DATA2                                                                      0x0222
>+#define mmSDMA4_RLC2_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA4_RLC2_MIDCMD_DATA3                                                                      0x0223
>+#define mmSDMA4_RLC2_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA4_RLC2_MIDCMD_DATA4                                                                      0x0224
>+#define mmSDMA4_RLC2_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA4_RLC2_MIDCMD_DATA5                                                                      0x0225
>+#define mmSDMA4_RLC2_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA4_RLC2_MIDCMD_DATA6                                                                      0x0226
>+#define mmSDMA4_RLC2_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA4_RLC2_MIDCMD_DATA7                                                                      0x0227
>+#define mmSDMA4_RLC2_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA4_RLC2_MIDCMD_DATA8                                                                      0x0228
>+#define mmSDMA4_RLC2_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA4_RLC2_MIDCMD_CNTL                                                                       0x0229
>+#define mmSDMA4_RLC2_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC3_RB_CNTL                                                                           0x0238
>+#define mmSDMA4_RLC3_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC3_RB_BASE                                                                           0x0239
>+#define mmSDMA4_RLC3_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC3_RB_BASE_HI                                                                        0x023a
>+#define mmSDMA4_RLC3_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC3_RB_RPTR                                                                           0x023b
>+#define mmSDMA4_RLC3_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC3_RB_RPTR_HI                                                                        0x023c
>+#define mmSDMA4_RLC3_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC3_RB_WPTR                                                                           0x023d
>+#define mmSDMA4_RLC3_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC3_RB_WPTR_HI                                                                        0x023e
>+#define mmSDMA4_RLC3_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC3_RB_WPTR_POLL_CNTL                                                                 0x023f
>+#define mmSDMA4_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA4_RLC3_RB_RPTR_ADDR_HI                                                                   0x0240
>+#define mmSDMA4_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA4_RLC3_RB_RPTR_ADDR_LO                                                                   0x0241
>+#define mmSDMA4_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA4_RLC3_IB_CNTL                                                                           0x0242
>+#define mmSDMA4_RLC3_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC3_IB_RPTR                                                                           0x0243
>+#define mmSDMA4_RLC3_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC3_IB_OFFSET                                                                         0x0244
>+#define mmSDMA4_RLC3_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA4_RLC3_IB_BASE_LO                                                                        0x0245
>+#define mmSDMA4_RLC3_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA4_RLC3_IB_BASE_HI                                                                        0x0246
>+#define mmSDMA4_RLC3_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC3_IB_SIZE                                                                           0x0247
>+#define mmSDMA4_RLC3_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC3_SKIP_CNTL                                                                         0x0248
>+#define mmSDMA4_RLC3_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA4_RLC3_CONTEXT_STATUS                                                                    0x0249
>+#define mmSDMA4_RLC3_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA4_RLC3_DOORBELL                                                                          0x024a
>+#define mmSDMA4_RLC3_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA4_RLC3_STATUS                                                                            0x0260
>+#define mmSDMA4_RLC3_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA4_RLC3_DOORBELL_LOG                                                                      0x0261
>+#define mmSDMA4_RLC3_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA4_RLC3_WATERMARK                                                                         0x0262
>+#define mmSDMA4_RLC3_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA4_RLC3_DOORBELL_OFFSET                                                                   0x0263
>+#define mmSDMA4_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA4_RLC3_CSA_ADDR_LO                                                                       0x0264
>+#define mmSDMA4_RLC3_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA4_RLC3_CSA_ADDR_HI                                                                       0x0265
>+#define mmSDMA4_RLC3_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA4_RLC3_IB_SUB_REMAIN                                                                     0x0267
>+#define mmSDMA4_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA4_RLC3_PREEMPT                                                                           0x0268
>+#define mmSDMA4_RLC3_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC3_DUMMY_REG                                                                         0x0269
>+#define mmSDMA4_RLC3_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x026a
>+#define mmSDMA4_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x026b
>+#define mmSDMA4_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA4_RLC3_RB_AQL_CNTL                                                                       0x026c
>+#define mmSDMA4_RLC3_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC3_MINOR_PTR_UPDATE                                                                  0x026d
>+#define mmSDMA4_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA4_RLC3_MIDCMD_DATA0                                                                      0x0278
>+#define mmSDMA4_RLC3_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA4_RLC3_MIDCMD_DATA1                                                                      0x0279
>+#define mmSDMA4_RLC3_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA4_RLC3_MIDCMD_DATA2                                                                      0x027a
>+#define mmSDMA4_RLC3_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA4_RLC3_MIDCMD_DATA3                                                                      0x027b
>+#define mmSDMA4_RLC3_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA4_RLC3_MIDCMD_DATA4                                                                      0x027c
>+#define mmSDMA4_RLC3_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA4_RLC3_MIDCMD_DATA5                                                                      0x027d
>+#define mmSDMA4_RLC3_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA4_RLC3_MIDCMD_DATA6                                                                      0x027e
>+#define mmSDMA4_RLC3_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA4_RLC3_MIDCMD_DATA7                                                                      0x027f
>+#define mmSDMA4_RLC3_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA4_RLC3_MIDCMD_DATA8                                                                      0x0280
>+#define mmSDMA4_RLC3_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA4_RLC3_MIDCMD_CNTL                                                                       0x0281
>+#define mmSDMA4_RLC3_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC4_RB_CNTL                                                                           0x0290
>+#define mmSDMA4_RLC4_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC4_RB_BASE                                                                           0x0291
>+#define mmSDMA4_RLC4_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC4_RB_BASE_HI                                                                        0x0292
>+#define mmSDMA4_RLC4_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC4_RB_RPTR                                                                           0x0293
>+#define mmSDMA4_RLC4_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC4_RB_RPTR_HI                                                                        0x0294
>+#define mmSDMA4_RLC4_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC4_RB_WPTR                                                                           0x0295
>+#define mmSDMA4_RLC4_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC4_RB_WPTR_HI                                                                        0x0296
>+#define mmSDMA4_RLC4_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC4_RB_WPTR_POLL_CNTL                                                                 0x0297
>+#define mmSDMA4_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA4_RLC4_RB_RPTR_ADDR_HI                                                                   0x0298
>+#define mmSDMA4_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA4_RLC4_RB_RPTR_ADDR_LO                                                                   0x0299
>+#define mmSDMA4_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA4_RLC4_IB_CNTL                                                                           0x029a
>+#define mmSDMA4_RLC4_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC4_IB_RPTR                                                                           0x029b
>+#define mmSDMA4_RLC4_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC4_IB_OFFSET                                                                         0x029c
>+#define mmSDMA4_RLC4_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA4_RLC4_IB_BASE_LO                                                                        0x029d
>+#define mmSDMA4_RLC4_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA4_RLC4_IB_BASE_HI                                                                        0x029e
>+#define mmSDMA4_RLC4_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC4_IB_SIZE                                                                           0x029f
>+#define mmSDMA4_RLC4_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC4_SKIP_CNTL                                                                         0x02a0
>+#define mmSDMA4_RLC4_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA4_RLC4_CONTEXT_STATUS                                                                    0x02a1
>+#define mmSDMA4_RLC4_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA4_RLC4_DOORBELL                                                                          0x02a2
>+#define mmSDMA4_RLC4_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA4_RLC4_STATUS                                                                            0x02b8
>+#define mmSDMA4_RLC4_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA4_RLC4_DOORBELL_LOG                                                                      0x02b9
>+#define mmSDMA4_RLC4_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA4_RLC4_WATERMARK                                                                         0x02ba
>+#define mmSDMA4_RLC4_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA4_RLC4_DOORBELL_OFFSET                                                                   0x02bb
>+#define mmSDMA4_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA4_RLC4_CSA_ADDR_LO                                                                       0x02bc
>+#define mmSDMA4_RLC4_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA4_RLC4_CSA_ADDR_HI                                                                       0x02bd
>+#define mmSDMA4_RLC4_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA4_RLC4_IB_SUB_REMAIN                                                                     0x02bf
>+#define mmSDMA4_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA4_RLC4_PREEMPT                                                                           0x02c0
>+#define mmSDMA4_RLC4_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC4_DUMMY_REG                                                                         0x02c1
>+#define mmSDMA4_RLC4_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x02c2
>+#define mmSDMA4_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x02c3
>+#define mmSDMA4_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA4_RLC4_RB_AQL_CNTL                                                                       0x02c4
>+#define mmSDMA4_RLC4_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC4_MINOR_PTR_UPDATE                                                                  0x02c5
>+#define mmSDMA4_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA4_RLC4_MIDCMD_DATA0                                                                      0x02d0
>+#define mmSDMA4_RLC4_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA4_RLC4_MIDCMD_DATA1                                                                      0x02d1
>+#define mmSDMA4_RLC4_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA4_RLC4_MIDCMD_DATA2                                                                      0x02d2
>+#define mmSDMA4_RLC4_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA4_RLC4_MIDCMD_DATA3                                                                      0x02d3
>+#define mmSDMA4_RLC4_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA4_RLC4_MIDCMD_DATA4                                                                      0x02d4
>+#define mmSDMA4_RLC4_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA4_RLC4_MIDCMD_DATA5                                                                      0x02d5
>+#define mmSDMA4_RLC4_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA4_RLC4_MIDCMD_DATA6                                                                      0x02d6
>+#define mmSDMA4_RLC4_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA4_RLC4_MIDCMD_DATA7                                                                      0x02d7
>+#define mmSDMA4_RLC4_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA4_RLC4_MIDCMD_DATA8                                                                      0x02d8
>+#define mmSDMA4_RLC4_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA4_RLC4_MIDCMD_CNTL                                                                       0x02d9
>+#define mmSDMA4_RLC4_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC5_RB_CNTL                                                                           0x02e8
>+#define mmSDMA4_RLC5_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC5_RB_BASE                                                                           0x02e9
>+#define mmSDMA4_RLC5_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC5_RB_BASE_HI                                                                        0x02ea
>+#define mmSDMA4_RLC5_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC5_RB_RPTR                                                                           0x02eb
>+#define mmSDMA4_RLC5_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC5_RB_RPTR_HI                                                                        0x02ec
>+#define mmSDMA4_RLC5_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC5_RB_WPTR                                                                           0x02ed
>+#define mmSDMA4_RLC5_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC5_RB_WPTR_HI                                                                        0x02ee
>+#define mmSDMA4_RLC5_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC5_RB_WPTR_POLL_CNTL                                                                 0x02ef
>+#define mmSDMA4_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA4_RLC5_RB_RPTR_ADDR_HI                                                                   0x02f0
>+#define mmSDMA4_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA4_RLC5_RB_RPTR_ADDR_LO                                                                   0x02f1
>+#define mmSDMA4_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA4_RLC5_IB_CNTL                                                                           0x02f2
>+#define mmSDMA4_RLC5_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC5_IB_RPTR                                                                           0x02f3
>+#define mmSDMA4_RLC5_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC5_IB_OFFSET                                                                         0x02f4
>+#define mmSDMA4_RLC5_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA4_RLC5_IB_BASE_LO                                                                        0x02f5
>+#define mmSDMA4_RLC5_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA4_RLC5_IB_BASE_HI                                                                        0x02f6
>+#define mmSDMA4_RLC5_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC5_IB_SIZE                                                                           0x02f7
>+#define mmSDMA4_RLC5_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC5_SKIP_CNTL                                                                         0x02f8
>+#define mmSDMA4_RLC5_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA4_RLC5_CONTEXT_STATUS                                                                    0x02f9
>+#define mmSDMA4_RLC5_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA4_RLC5_DOORBELL                                                                          0x02fa
>+#define mmSDMA4_RLC5_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA4_RLC5_STATUS                                                                            0x0310
>+#define mmSDMA4_RLC5_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA4_RLC5_DOORBELL_LOG                                                                      0x0311
>+#define mmSDMA4_RLC5_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA4_RLC5_WATERMARK                                                                         0x0312
>+#define mmSDMA4_RLC5_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA4_RLC5_DOORBELL_OFFSET                                                                   0x0313
>+#define mmSDMA4_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA4_RLC5_CSA_ADDR_LO                                                                       0x0314
>+#define mmSDMA4_RLC5_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA4_RLC5_CSA_ADDR_HI                                                                       0x0315
>+#define mmSDMA4_RLC5_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA4_RLC5_IB_SUB_REMAIN                                                                     0x0317
>+#define mmSDMA4_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA4_RLC5_PREEMPT                                                                           0x0318
>+#define mmSDMA4_RLC5_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC5_DUMMY_REG                                                                         0x0319
>+#define mmSDMA4_RLC5_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x031a
>+#define mmSDMA4_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x031b
>+#define mmSDMA4_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA4_RLC5_RB_AQL_CNTL                                                                       0x031c
>+#define mmSDMA4_RLC5_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC5_MINOR_PTR_UPDATE                                                                  0x031d
>+#define mmSDMA4_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA4_RLC5_MIDCMD_DATA0                                                                      0x0328
>+#define mmSDMA4_RLC5_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA4_RLC5_MIDCMD_DATA1                                                                      0x0329
>+#define mmSDMA4_RLC5_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA4_RLC5_MIDCMD_DATA2                                                                      0x032a
>+#define mmSDMA4_RLC5_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA4_RLC5_MIDCMD_DATA3                                                                      0x032b
>+#define mmSDMA4_RLC5_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA4_RLC5_MIDCMD_DATA4                                                                      0x032c
>+#define mmSDMA4_RLC5_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA4_RLC5_MIDCMD_DATA5                                                                      0x032d
>+#define mmSDMA4_RLC5_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA4_RLC5_MIDCMD_DATA6                                                                      0x032e
>+#define mmSDMA4_RLC5_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA4_RLC5_MIDCMD_DATA7                                                                      0x032f
>+#define mmSDMA4_RLC5_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA4_RLC5_MIDCMD_DATA8                                                                      0x0330
>+#define mmSDMA4_RLC5_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA4_RLC5_MIDCMD_CNTL                                                                       0x0331
>+#define mmSDMA4_RLC5_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC6_RB_CNTL                                                                           0x0340
>+#define mmSDMA4_RLC6_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC6_RB_BASE                                                                           0x0341
>+#define mmSDMA4_RLC6_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC6_RB_BASE_HI                                                                        0x0342
>+#define mmSDMA4_RLC6_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC6_RB_RPTR                                                                           0x0343
>+#define mmSDMA4_RLC6_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC6_RB_RPTR_HI                                                                        0x0344
>+#define mmSDMA4_RLC6_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC6_RB_WPTR                                                                           0x0345
>+#define mmSDMA4_RLC6_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC6_RB_WPTR_HI                                                                        0x0346
>+#define mmSDMA4_RLC6_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0347
>+#define mmSDMA4_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA4_RLC6_RB_RPTR_ADDR_HI                                                                   0x0348
>+#define mmSDMA4_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA4_RLC6_RB_RPTR_ADDR_LO                                                                   0x0349
>+#define mmSDMA4_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA4_RLC6_IB_CNTL                                                                           0x034a
>+#define mmSDMA4_RLC6_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC6_IB_RPTR                                                                           0x034b
>+#define mmSDMA4_RLC6_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC6_IB_OFFSET                                                                         0x034c
>+#define mmSDMA4_RLC6_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA4_RLC6_IB_BASE_LO                                                                        0x034d
>+#define mmSDMA4_RLC6_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA4_RLC6_IB_BASE_HI                                                                        0x034e
>+#define mmSDMA4_RLC6_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC6_IB_SIZE                                                                           0x034f
>+#define mmSDMA4_RLC6_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC6_SKIP_CNTL                                                                         0x0350
>+#define mmSDMA4_RLC6_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA4_RLC6_CONTEXT_STATUS                                                                    0x0351
>+#define mmSDMA4_RLC6_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA4_RLC6_DOORBELL                                                                          0x0352
>+#define mmSDMA4_RLC6_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA4_RLC6_STATUS                                                                            0x0368
>+#define mmSDMA4_RLC6_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA4_RLC6_DOORBELL_LOG                                                                      0x0369
>+#define mmSDMA4_RLC6_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA4_RLC6_WATERMARK                                                                         0x036a
>+#define mmSDMA4_RLC6_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA4_RLC6_DOORBELL_OFFSET                                                                   0x036b
>+#define mmSDMA4_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA4_RLC6_CSA_ADDR_LO                                                                       0x036c
>+#define mmSDMA4_RLC6_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA4_RLC6_CSA_ADDR_HI                                                                       0x036d
>+#define mmSDMA4_RLC6_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA4_RLC6_IB_SUB_REMAIN                                                                     0x036f
>+#define mmSDMA4_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA4_RLC6_PREEMPT                                                                           0x0370
>+#define mmSDMA4_RLC6_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC6_DUMMY_REG                                                                         0x0371
>+#define mmSDMA4_RLC6_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x0372
>+#define mmSDMA4_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x0373
>+#define mmSDMA4_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA4_RLC6_RB_AQL_CNTL                                                                       0x0374
>+#define mmSDMA4_RLC6_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC6_MINOR_PTR_UPDATE                                                                  0x0375
>+#define mmSDMA4_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA4_RLC6_MIDCMD_DATA0                                                                      0x0380
>+#define mmSDMA4_RLC6_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA4_RLC6_MIDCMD_DATA1                                                                      0x0381
>+#define mmSDMA4_RLC6_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA4_RLC6_MIDCMD_DATA2                                                                      0x0382
>+#define mmSDMA4_RLC6_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA4_RLC6_MIDCMD_DATA3                                                                      0x0383
>+#define mmSDMA4_RLC6_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA4_RLC6_MIDCMD_DATA4                                                                      0x0384
>+#define mmSDMA4_RLC6_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA4_RLC6_MIDCMD_DATA5                                                                      0x0385
>+#define mmSDMA4_RLC6_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA4_RLC6_MIDCMD_DATA6                                                                      0x0386
>+#define mmSDMA4_RLC6_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA4_RLC6_MIDCMD_DATA7                                                                      0x0387
>+#define mmSDMA4_RLC6_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA4_RLC6_MIDCMD_DATA8                                                                      0x0388
>+#define mmSDMA4_RLC6_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA4_RLC6_MIDCMD_CNTL                                                                       0x0389
>+#define mmSDMA4_RLC6_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC7_RB_CNTL                                                                           0x0398
>+#define mmSDMA4_RLC7_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC7_RB_BASE                                                                           0x0399
>+#define mmSDMA4_RLC7_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC7_RB_BASE_HI                                                                        0x039a
>+#define mmSDMA4_RLC7_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC7_RB_RPTR                                                                           0x039b
>+#define mmSDMA4_RLC7_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC7_RB_RPTR_HI                                                                        0x039c
>+#define mmSDMA4_RLC7_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC7_RB_WPTR                                                                           0x039d
>+#define mmSDMA4_RLC7_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC7_RB_WPTR_HI                                                                        0x039e
>+#define mmSDMA4_RLC7_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC7_RB_WPTR_POLL_CNTL                                                                 0x039f
>+#define mmSDMA4_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA4_RLC7_RB_RPTR_ADDR_HI                                                                   0x03a0
>+#define mmSDMA4_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA4_RLC7_RB_RPTR_ADDR_LO                                                                   0x03a1
>+#define mmSDMA4_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA4_RLC7_IB_CNTL                                                                           0x03a2
>+#define mmSDMA4_RLC7_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC7_IB_RPTR                                                                           0x03a3
>+#define mmSDMA4_RLC7_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC7_IB_OFFSET                                                                         0x03a4
>+#define mmSDMA4_RLC7_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA4_RLC7_IB_BASE_LO                                                                        0x03a5
>+#define mmSDMA4_RLC7_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA4_RLC7_IB_BASE_HI                                                                        0x03a6
>+#define mmSDMA4_RLC7_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA4_RLC7_IB_SIZE                                                                           0x03a7
>+#define mmSDMA4_RLC7_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC7_SKIP_CNTL                                                                         0x03a8
>+#define mmSDMA4_RLC7_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA4_RLC7_CONTEXT_STATUS                                                                    0x03a9
>+#define mmSDMA4_RLC7_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA4_RLC7_DOORBELL                                                                          0x03aa
>+#define mmSDMA4_RLC7_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA4_RLC7_STATUS                                                                            0x03c0
>+#define mmSDMA4_RLC7_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA4_RLC7_DOORBELL_LOG                                                                      0x03c1
>+#define mmSDMA4_RLC7_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA4_RLC7_WATERMARK                                                                         0x03c2
>+#define mmSDMA4_RLC7_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA4_RLC7_DOORBELL_OFFSET                                                                   0x03c3
>+#define mmSDMA4_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA4_RLC7_CSA_ADDR_LO                                                                       0x03c4
>+#define mmSDMA4_RLC7_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA4_RLC7_CSA_ADDR_HI                                                                       0x03c5
>+#define mmSDMA4_RLC7_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA4_RLC7_IB_SUB_REMAIN                                                                     0x03c7
>+#define mmSDMA4_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA4_RLC7_PREEMPT                                                                           0x03c8
>+#define mmSDMA4_RLC7_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA4_RLC7_DUMMY_REG                                                                         0x03c9
>+#define mmSDMA4_RLC7_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x03ca
>+#define mmSDMA4_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x03cb
>+#define mmSDMA4_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA4_RLC7_RB_AQL_CNTL                                                                       0x03cc
>+#define mmSDMA4_RLC7_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA4_RLC7_MINOR_PTR_UPDATE                                                                  0x03cd
>+#define mmSDMA4_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA4_RLC7_MIDCMD_DATA0                                                                      0x03d8
>+#define mmSDMA4_RLC7_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA4_RLC7_MIDCMD_DATA1                                                                      0x03d9
>+#define mmSDMA4_RLC7_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA4_RLC7_MIDCMD_DATA2                                                                      0x03da
>+#define mmSDMA4_RLC7_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA4_RLC7_MIDCMD_DATA3                                                                      0x03db
>+#define mmSDMA4_RLC7_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA4_RLC7_MIDCMD_DATA4                                                                      0x03dc
>+#define mmSDMA4_RLC7_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA4_RLC7_MIDCMD_DATA5                                                                      0x03dd
>+#define mmSDMA4_RLC7_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA4_RLC7_MIDCMD_DATA6                                                                      0x03de
>+#define mmSDMA4_RLC7_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA4_RLC7_MIDCMD_DATA7                                                                      0x03df
>+#define mmSDMA4_RLC7_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA4_RLC7_MIDCMD_DATA8                                                                      0x03e0
>+#define mmSDMA4_RLC7_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA4_RLC7_MIDCMD_CNTL                                                                       0x03e1
>+#define mmSDMA4_RLC7_MIDCMD_CNTL_BASE_IDX                                                              1
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma4/sdma4_4_2_2_sh_mask.h	2019-08-31 15:01:11.933736175 -0500
>@@ -0,0 +1,2956 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma4_4_2_2_SH_MASK_HEADER
>+#define _sdma4_4_2_2_SH_MASK_HEADER
>+
>+
>+// addressBlock: sdma4_sdma4dec
>+//SDMA4_UCODE_ADDR
>+#define SDMA4_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
>+#define SDMA4_UCODE_ADDR__VALUE_MASK                                                                          0x00001FFFL
>+//SDMA4_UCODE_DATA
>+#define SDMA4_UCODE_DATA__VALUE__SHIFT                                                                        0x0
>+#define SDMA4_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
>+//SDMA4_VM_CNTL
>+#define SDMA4_VM_CNTL__CMD__SHIFT                                                                             0x0
>+#define SDMA4_VM_CNTL__CMD_MASK                                                                               0x0000000FL
>+//SDMA4_VM_CTX_LO
>+#define SDMA4_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
>+#define SDMA4_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
>+//SDMA4_VM_CTX_HI
>+#define SDMA4_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
>+#define SDMA4_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
>+//SDMA4_ACTIVE_FCN_ID
>+#define SDMA4_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
>+#define SDMA4_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x4
>+#define SDMA4_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
>+#define SDMA4_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000000FL
>+#define SDMA4_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFF0L
>+#define SDMA4_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
>+//SDMA4_VM_CTX_CNTL
>+#define SDMA4_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
>+#define SDMA4_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
>+#define SDMA4_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
>+#define SDMA4_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
>+//SDMA4_VIRT_RESET_REQ
>+#define SDMA4_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
>+#define SDMA4_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
>+#define SDMA4_VIRT_RESET_REQ__VF_MASK                                                                         0x0000FFFFL
>+#define SDMA4_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
>+//SDMA4_VF_ENABLE
>+#define SDMA4_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
>+#define SDMA4_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
>+//SDMA4_CONTEXT_REG_TYPE0
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_CNTL__SHIFT                                                     0x0
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_BASE__SHIFT                                                     0x1
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_BASE_HI__SHIFT                                                  0x2
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR__SHIFT                                                     0x3
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_HI__SHIFT                                                  0x4
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR__SHIFT                                                     0x5
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_HI__SHIFT                                                  0x6
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_CNTL__SHIFT                                                     0xa
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_RPTR__SHIFT                                                     0xb
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_OFFSET__SHIFT                                                   0xc
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_BASE_LO__SHIFT                                                  0xd
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_BASE_HI__SHIFT                                                  0xe
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_SIZE__SHIFT                                                     0xf
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_SKIP_CNTL__SHIFT                                                   0x10
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_CONTEXT_STATUS__SHIFT                                              0x11
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_DOORBELL__SHIFT                                                    0x12
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_CONTEXT_CNTL__SHIFT                                                0x13
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_CNTL_MASK                                                       0x00000001L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_BASE_MASK                                                       0x00000002L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_BASE_HI_MASK                                                    0x00000004L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_MASK                                                       0x00000008L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_MASK                                                       0x00000020L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_CNTL_MASK                                                       0x00000400L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_RPTR_MASK                                                       0x00000800L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_OFFSET_MASK                                                     0x00001000L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_BASE_LO_MASK                                                    0x00002000L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_BASE_HI_MASK                                                    0x00004000L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_IB_SIZE_MASK                                                       0x00008000L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_SKIP_CNTL_MASK                                                     0x00010000L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_DOORBELL_MASK                                                      0x00040000L
>+#define SDMA4_CONTEXT_REG_TYPE0__SDMA4_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
>+//SDMA4_CONTEXT_REG_TYPE1
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_STATUS__SHIFT                                                      0x8
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DOORBELL_LOG__SHIFT                                                0x9
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_WATERMARK__SHIFT                                                   0xa
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
>+#define SDMA4_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_PREEMPT__SHIFT                                                     0x10
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DUMMY_REG__SHIFT                                                   0x11
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
>+#define SDMA4_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x16
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_STATUS_MASK                                                        0x00000100L
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_WATERMARK_MASK                                                     0x00000400L
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
>+#define SDMA4_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_PREEMPT_MASK                                                       0x00010000L
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_DUMMY_REG_MASK                                                     0x00020000L
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
>+#define SDMA4_CONTEXT_REG_TYPE1__SDMA4_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
>+#define SDMA4_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFFC00000L
>+//SDMA4_CONTEXT_REG_TYPE2
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA0__SHIFT                                                0x0
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA1__SHIFT                                                0x1
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA2__SHIFT                                                0x2
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA3__SHIFT                                                0x3
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA4__SHIFT                                                0x4
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA5__SHIFT                                                0x5
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA6__SHIFT                                                0x6
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA7__SHIFT                                                0x7
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA8__SHIFT                                                0x8
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_CNTL__SHIFT                                                 0x9
>+#define SDMA4_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
>+#define SDMA4_CONTEXT_REG_TYPE2__SDMA4_GFX_MIDCMD_CNTL_MASK                                                   0x00000200L
>+#define SDMA4_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFFC00L
>+//SDMA4_CONTEXT_REG_TYPE3
>+#define SDMA4_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
>+#define SDMA4_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
>+//SDMA4_PUB_REG_TYPE0
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_ADDR__SHIFT                                                          0x0
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_DATA__SHIFT                                                          0x1
>+#define SDMA4_PUB_REG_TYPE0__RESERVED3__SHIFT                                                                 0x3
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CNTL__SHIFT                                                             0x4
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_LO__SHIFT                                                           0x5
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_HI__SHIFT                                                           0x6
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_ACTIVE_FCN_ID__SHIFT                                                       0x7
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_CNTL__SHIFT                                                         0x8
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_VIRT_RESET_REQ__SHIFT                                                      0x9
>+#define SDMA4_PUB_REG_TYPE0__RESERVED10__SHIFT                                                                0xa
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE0__SHIFT                                                   0xb
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE1__SHIFT                                                   0xc
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE2__SHIFT                                                   0xd
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE3__SHIFT                                                   0xe
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE0__SHIFT                                                       0xf
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE1__SHIFT                                                       0x10
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE2__SHIFT                                                       0x11
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE3__SHIFT                                                       0x12
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_MMHUB_CNTL__SHIFT                                                          0x13
>+#define SDMA4_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x15
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_GROUP_BOUNDARY__SHIFT                                              0x19
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_POWER_CNTL__SHIFT                                                          0x1a
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CLK_CTRL__SHIFT                                                            0x1b
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CNTL__SHIFT                                                                0x1c
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CHICKEN_BITS__SHIFT                                                        0x1d
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_GB_ADDR_CONFIG__SHIFT                                                      0x1e
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_ADDR_MASK                                                            0x00000001L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_UCODE_DATA_MASK                                                            0x00000002L
>+#define SDMA4_PUB_REG_TYPE0__RESERVED3_MASK                                                                   0x00000008L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CNTL_MASK                                                               0x00000010L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_LO_MASK                                                             0x00000020L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_HI_MASK                                                             0x00000040L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_ACTIVE_FCN_ID_MASK                                                         0x00000080L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_VM_CTX_CNTL_MASK                                                           0x00000100L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_VIRT_RESET_REQ_MASK                                                        0x00000200L
>+#define SDMA4_PUB_REG_TYPE0__RESERVED10_MASK                                                                  0x00000400L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE0_MASK                                                     0x00000800L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE1_MASK                                                     0x00001000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE2_MASK                                                     0x00002000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_REG_TYPE3_MASK                                                     0x00004000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE0_MASK                                                         0x00008000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE1_MASK                                                         0x00010000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE2_MASK                                                         0x00020000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_PUB_REG_TYPE3_MASK                                                         0x00040000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_MMHUB_CNTL_MASK                                                            0x00080000L
>+#define SDMA4_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x01E00000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CONTEXT_GROUP_BOUNDARY_MASK                                                0x02000000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_POWER_CNTL_MASK                                                            0x04000000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CLK_CTRL_MASK                                                              0x08000000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CNTL_MASK                                                                  0x10000000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_CHICKEN_BITS_MASK                                                          0x20000000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_GB_ADDR_CONFIG_MASK                                                        0x40000000L
>+#define SDMA4_PUB_REG_TYPE0__SDMA4_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
>+//SDMA4_PUB_REG_TYPE1
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_RB_RPTR_FETCH__SHIFT                                                       0x2
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_IB_OFFSET_FETCH__SHIFT                                                     0x3
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_PROGRAM__SHIFT                                                             0x4
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS_REG__SHIFT                                                          0x5
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS1_REG__SHIFT                                                         0x6
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_RD_BURST_CNTL__SHIFT                                                       0x7
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_HBM_PAGE_CONFIG__SHIFT                                                     0x8
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_UCODE_CHECKSUM__SHIFT                                                      0x9
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_F32_CNTL__SHIFT                                                            0xa
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_FREEZE__SHIFT                                                              0xb
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_PHASE0_QUANTUM__SHIFT                                                      0xc
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_PHASE1_QUANTUM__SHIFT                                                      0xd
>+#define SDMA4_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT                                                         0xe
>+#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT                                                         0xf
>+#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT                                                          0x10
>+#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT                                                           0x11
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_CONFIG__SHIFT                                                          0x12
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_BA_THRESHOLD__SHIFT                                                        0x13
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_ID__SHIFT                                                                  0x14
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_VERSION__SHIFT                                                             0x15
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_COUNTER__SHIFT                                                         0x16
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS2_REG__SHIFT                                                         0x18
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_CNTL__SHIFT                                                         0x19
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_CNTL__SHIFT                                                          0x1c
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WATERMK__SHIFT                                                       0x1d
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_RD_STATUS__SHIFT                                                     0x1e
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WR_STATUS__SHIFT                                                     0x1f
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_RB_RPTR_FETCH_MASK                                                         0x00000004L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_IB_OFFSET_FETCH_MASK                                                       0x00000008L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_PROGRAM_MASK                                                               0x00000010L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS_REG_MASK                                                            0x00000020L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS1_REG_MASK                                                           0x00000040L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_RD_BURST_CNTL_MASK                                                         0x00000080L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_UCODE_CHECKSUM_MASK                                                        0x00000200L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_F32_CNTL_MASK                                                              0x00000400L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_FREEZE_MASK                                                                0x00000800L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_PHASE0_QUANTUM_MASK                                                        0x00001000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_PHASE1_QUANTUM_MASK                                                        0x00002000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK                                                           0x00004000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK                                                           0x00008000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK                                                            0x00010000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK                                                             0x00020000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_CONFIG_MASK                                                            0x00040000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_BA_THRESHOLD_MASK                                                          0x00080000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_ID_MASK                                                                    0x00100000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_VERSION_MASK                                                               0x00200000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_COUNTER_MASK                                                           0x00400000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_STATUS2_REG_MASK                                                           0x01000000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_CNTL_MASK                                                           0x02000000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_CNTL_MASK                                                            0x10000000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WATERMK_MASK                                                         0x20000000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_RD_STATUS_MASK                                                       0x40000000L
>+#define SDMA4_PUB_REG_TYPE1__SDMA4_UTCL1_WR_STATUS_MASK                                                       0x80000000L
>+//SDMA4_PUB_REG_TYPE2
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV0__SHIFT                                                          0x0
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV1__SHIFT                                                          0x1
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV2__SHIFT                                                          0x2
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_RD_XNACK0__SHIFT                                                     0x3
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_RD_XNACK1__SHIFT                                                     0x4
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_WR_XNACK0__SHIFT                                                     0x5
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_WR_XNACK1__SHIFT                                                     0x6
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_TIMEOUT__SHIFT                                                       0x7
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_PAGE__SHIFT                                                          0x8
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_POWER_CNTL_IDLE__SHIFT                                                     0x9
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_RELAX_ORDERING_LUT__SHIFT                                                  0xa
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_CHICKEN_BITS_2__SHIFT                                                      0xb
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_STATUS3_REG__SHIFT                                                         0xc
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PHASE2_QUANTUM__SHIFT                                                      0xf
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_ERROR_LOG__SHIFT                                                           0x10
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG0__SHIFT                                                      0x11
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG1__SHIFT                                                      0x12
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG2__SHIFT                                                      0x13
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG3__SHIFT                                                      0x14
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_F32_COUNTER__SHIFT                                                         0x15
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UNBREAKABLE__SHIFT                                                         0x16
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFMON_CNTL__SHIFT                                                        0x17
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER0_RESULT__SHIFT                                                 0x18
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER1_RESULT__SHIFT                                                 0x19
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT                                         0x1a
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_CRD_CNTL__SHIFT                                                            0x1b
>+#define SDMA4_PUB_REG_TYPE2__RESERVED28__SHIFT                                                                0x1c
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_GPU_IOV_VIOLATION_LOG__SHIFT                                               0x1d
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_ULV_CNTL__SHIFT                                                            0x1e
>+#define SDMA4_PUB_REG_TYPE2__RESERVED__SHIFT                                                                  0x1f
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV0_MASK                                                            0x00000001L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV1_MASK                                                            0x00000002L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_INV2_MASK                                                            0x00000004L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_TIMEOUT_MASK                                                         0x00000080L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UTCL1_PAGE_MASK                                                            0x00000100L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_POWER_CNTL_IDLE_MASK                                                       0x00000200L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_CHICKEN_BITS_2_MASK                                                        0x00000800L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_STATUS3_REG_MASK                                                           0x00001000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PHASE2_QUANTUM_MASK                                                        0x00008000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_ERROR_LOG_MASK                                                             0x00010000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG0_MASK                                                        0x00020000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG1_MASK                                                        0x00040000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG2_MASK                                                        0x00080000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PUB_DUMMY_REG3_MASK                                                        0x00100000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_F32_COUNTER_MASK                                                           0x00200000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_UNBREAKABLE_MASK                                                           0x00400000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFMON_CNTL_MASK                                                          0x00800000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER0_RESULT_MASK                                                   0x01000000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER1_RESULT_MASK                                                   0x02000000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_PERFCOUNTER_TAG_DELAY_RANGE_MASK                                           0x04000000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_CRD_CNTL_MASK                                                              0x08000000L
>+#define SDMA4_PUB_REG_TYPE2__RESERVED28_MASK                                                                  0x10000000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_GPU_IOV_VIOLATION_LOG_MASK                                                 0x20000000L
>+#define SDMA4_PUB_REG_TYPE2__SDMA4_ULV_CNTL_MASK                                                              0x40000000L
>+#define SDMA4_PUB_REG_TYPE2__RESERVED_MASK                                                                    0x80000000L
>+//SDMA4_PUB_REG_TYPE3
>+#define SDMA4_PUB_REG_TYPE3__SDMA4_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
>+#define SDMA4_PUB_REG_TYPE3__SDMA4_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
>+#define SDMA4_PUB_REG_TYPE3__SDMA4_GPU_IOV_VIOLATION_LOG2__SHIFT                                              0x2
>+#define SDMA4_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x3
>+#define SDMA4_PUB_REG_TYPE3__SDMA4_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
>+#define SDMA4_PUB_REG_TYPE3__SDMA4_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
>+#define SDMA4_PUB_REG_TYPE3__SDMA4_GPU_IOV_VIOLATION_LOG2_MASK                                                0x00000004L
>+#define SDMA4_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xFFFFFFF8L
>+//SDMA4_MMHUB_CNTL
>+#define SDMA4_MMHUB_CNTL__UNIT_ID__SHIFT                                                                      0x0
>+#define SDMA4_MMHUB_CNTL__UNIT_ID_MASK                                                                        0x0000003FL
>+//SDMA4_CONTEXT_GROUP_BOUNDARY
>+#define SDMA4_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT                                                         0x0
>+#define SDMA4_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK                                                           0xFFFFFFFFL
>+//SDMA4_POWER_CNTL
>+#define SDMA4_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
>+#define SDMA4_POWER_CNTL__MEM_POWER_LS_EN__SHIFT                                                              0x9
>+#define SDMA4_POWER_CNTL__MEM_POWER_DS_EN__SHIFT                                                              0xa
>+#define SDMA4_POWER_CNTL__MEM_POWER_SD_EN__SHIFT                                                              0xb
>+#define SDMA4_POWER_CNTL__MEM_POWER_DELAY__SHIFT                                                              0xc
>+#define SDMA4_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
>+#define SDMA4_POWER_CNTL__MEM_POWER_LS_EN_MASK                                                                0x00000200L
>+#define SDMA4_POWER_CNTL__MEM_POWER_DS_EN_MASK                                                                0x00000400L
>+#define SDMA4_POWER_CNTL__MEM_POWER_SD_EN_MASK                                                                0x00000800L
>+#define SDMA4_POWER_CNTL__MEM_POWER_DELAY_MASK                                                                0x003FF000L
>+//SDMA4_CLK_CTRL
>+#define SDMA4_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
>+#define SDMA4_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
>+#define SDMA4_CLK_CTRL__RESERVED__SHIFT                                                                       0xc
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                                 0x18
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                                 0x19
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                                 0x1a
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1b
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1c
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1d
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1e
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1f
>+#define SDMA4_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
>+#define SDMA4_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
>+#define SDMA4_CLK_CTRL__RESERVED_MASK                                                                         0x00FFF000L
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                   0x01000000L
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                   0x02000000L
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                   0x04000000L
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x08000000L
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x10000000L
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x20000000L
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x40000000L
>+#define SDMA4_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x80000000L
>+//SDMA4_CNTL
>+#define SDMA4_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
>+#define SDMA4_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
>+#define SDMA4_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
>+#define SDMA4_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
>+#define SDMA4_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
>+#define SDMA4_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
>+#define SDMA4_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
>+#define SDMA4_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
>+#define SDMA4_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
>+#define SDMA4_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
>+#define SDMA4_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
>+#define SDMA4_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
>+#define SDMA4_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
>+#define SDMA4_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
>+#define SDMA4_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
>+#define SDMA4_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
>+#define SDMA4_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
>+#define SDMA4_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
>+#define SDMA4_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
>+#define SDMA4_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
>+#define SDMA4_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
>+#define SDMA4_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
>+//SDMA4_CHICKEN_BITS
>+#define SDMA4_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
>+#define SDMA4_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
>+#define SDMA4_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
>+#define SDMA4_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
>+#define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
>+#define SDMA4_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
>+#define SDMA4_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
>+#define SDMA4_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
>+#define SDMA4_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
>+#define SDMA4_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
>+#define SDMA4_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
>+#define SDMA4_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
>+#define SDMA4_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
>+#define SDMA4_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
>+#define SDMA4_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
>+#define SDMA4_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
>+#define SDMA4_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
>+#define SDMA4_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
>+#define SDMA4_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
>+#define SDMA4_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
>+#define SDMA4_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
>+#define SDMA4_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
>+#define SDMA4_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
>+#define SDMA4_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
>+#define SDMA4_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
>+#define SDMA4_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
>+//SDMA4_GB_ADDR_CONFIG
>+#define SDMA4_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
>+#define SDMA4_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
>+#define SDMA4_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
>+#define SDMA4_GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
>+#define SDMA4_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
>+#define SDMA4_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
>+#define SDMA4_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
>+#define SDMA4_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
>+#define SDMA4_GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
>+#define SDMA4_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
>+//SDMA4_GB_ADDR_CONFIG_READ
>+#define SDMA4_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
>+#define SDMA4_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
>+#define SDMA4_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                0x8
>+#define SDMA4_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                           0xc
>+#define SDMA4_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
>+#define SDMA4_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
>+#define SDMA4_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
>+#define SDMA4_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                  0x00000700L
>+#define SDMA4_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                             0x00007000L
>+#define SDMA4_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
>+//SDMA4_RB_RPTR_FETCH_HI
>+#define SDMA4_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
>+#define SDMA4_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_SEM_WAIT_FAIL_TIMER_CNTL
>+#define SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
>+#define SDMA4_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
>+//SDMA4_RB_RPTR_FETCH
>+#define SDMA4_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
>+#define SDMA4_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
>+//SDMA4_IB_OFFSET_FETCH
>+#define SDMA4_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
>+#define SDMA4_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
>+//SDMA4_PROGRAM
>+#define SDMA4_PROGRAM__STREAM__SHIFT                                                                          0x0
>+#define SDMA4_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
>+//SDMA4_STATUS_REG
>+#define SDMA4_STATUS_REG__IDLE__SHIFT                                                                         0x0
>+#define SDMA4_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
>+#define SDMA4_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
>+#define SDMA4_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
>+#define SDMA4_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
>+#define SDMA4_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
>+#define SDMA4_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
>+#define SDMA4_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
>+#define SDMA4_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
>+#define SDMA4_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
>+#define SDMA4_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
>+#define SDMA4_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
>+#define SDMA4_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
>+#define SDMA4_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
>+#define SDMA4_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
>+#define SDMA4_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
>+#define SDMA4_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
>+#define SDMA4_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
>+#define SDMA4_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
>+#define SDMA4_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
>+#define SDMA4_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
>+#define SDMA4_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
>+#define SDMA4_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
>+#define SDMA4_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
>+#define SDMA4_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
>+#define SDMA4_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
>+#define SDMA4_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
>+#define SDMA4_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
>+#define SDMA4_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
>+#define SDMA4_STATUS_REG__IDLE_MASK                                                                           0x00000001L
>+#define SDMA4_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
>+#define SDMA4_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
>+#define SDMA4_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
>+#define SDMA4_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
>+#define SDMA4_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
>+#define SDMA4_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
>+#define SDMA4_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
>+#define SDMA4_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
>+#define SDMA4_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
>+#define SDMA4_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
>+#define SDMA4_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
>+#define SDMA4_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
>+#define SDMA4_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
>+#define SDMA4_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
>+#define SDMA4_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
>+#define SDMA4_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
>+#define SDMA4_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
>+#define SDMA4_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
>+#define SDMA4_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
>+#define SDMA4_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
>+#define SDMA4_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
>+#define SDMA4_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
>+#define SDMA4_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
>+#define SDMA4_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
>+#define SDMA4_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
>+#define SDMA4_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
>+#define SDMA4_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
>+#define SDMA4_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
>+//SDMA4_STATUS1_REG
>+#define SDMA4_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
>+#define SDMA4_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
>+#define SDMA4_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
>+#define SDMA4_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
>+#define SDMA4_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
>+#define SDMA4_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
>+#define SDMA4_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
>+#define SDMA4_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
>+#define SDMA4_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
>+#define SDMA4_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
>+#define SDMA4_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
>+#define SDMA4_STATUS1_REG__EX_START__SHIFT                                                                    0xf
>+#define SDMA4_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
>+#define SDMA4_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
>+#define SDMA4_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
>+#define SDMA4_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
>+#define SDMA4_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
>+#define SDMA4_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
>+#define SDMA4_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
>+#define SDMA4_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
>+#define SDMA4_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
>+#define SDMA4_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
>+#define SDMA4_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
>+#define SDMA4_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
>+#define SDMA4_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
>+#define SDMA4_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
>+#define SDMA4_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
>+#define SDMA4_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
>+//SDMA4_RD_BURST_CNTL
>+#define SDMA4_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
>+#define SDMA4_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT                                                       0x2
>+#define SDMA4_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
>+#define SDMA4_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK                                                         0x0000000CL
>+//SDMA4_HBM_PAGE_CONFIG
>+#define SDMA4_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
>+#define SDMA4_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000001L
>+//SDMA4_UCODE_CHECKSUM
>+#define SDMA4_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
>+#define SDMA4_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_F32_CNTL
>+#define SDMA4_F32_CNTL__HALT__SHIFT                                                                           0x0
>+#define SDMA4_F32_CNTL__STEP__SHIFT                                                                           0x1
>+#define SDMA4_F32_CNTL__HALT_MASK                                                                             0x00000001L
>+#define SDMA4_F32_CNTL__STEP_MASK                                                                             0x00000002L
>+//SDMA4_FREEZE
>+#define SDMA4_FREEZE__PREEMPT__SHIFT                                                                          0x0
>+#define SDMA4_FREEZE__FREEZE__SHIFT                                                                           0x4
>+#define SDMA4_FREEZE__FROZEN__SHIFT                                                                           0x5
>+#define SDMA4_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
>+#define SDMA4_FREEZE__PREEMPT_MASK                                                                            0x00000001L
>+#define SDMA4_FREEZE__FREEZE_MASK                                                                             0x00000010L
>+#define SDMA4_FREEZE__FROZEN_MASK                                                                             0x00000020L
>+#define SDMA4_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
>+//SDMA4_PHASE0_QUANTUM
>+#define SDMA4_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA4_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA4_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA4_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA4_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA4_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA4_PHASE1_QUANTUM
>+#define SDMA4_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA4_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA4_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA4_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA4_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA4_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA4_EDC_CONFIG
>+#define SDMA4_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
>+#define SDMA4_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
>+#define SDMA4_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
>+#define SDMA4_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
>+//SDMA4_BA_THRESHOLD
>+#define SDMA4_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
>+#define SDMA4_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
>+#define SDMA4_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
>+#define SDMA4_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
>+//SDMA4_ID
>+#define SDMA4_ID__DEVICE_ID__SHIFT                                                                            0x0
>+#define SDMA4_ID__DEVICE_ID_MASK                                                                              0x000000FFL
>+//SDMA4_VERSION
>+#define SDMA4_VERSION__MINVER__SHIFT                                                                          0x0
>+#define SDMA4_VERSION__MAJVER__SHIFT                                                                          0x8
>+#define SDMA4_VERSION__REV__SHIFT                                                                             0x10
>+#define SDMA4_VERSION__MINVER_MASK                                                                            0x0000007FL
>+#define SDMA4_VERSION__MAJVER_MASK                                                                            0x00007F00L
>+#define SDMA4_VERSION__REV_MASK                                                                               0x003F0000L
>+//SDMA4_EDC_COUNTER
>+#define SDMA4_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT                                                          0x0
>+#define SDMA4_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
>+#define SDMA4_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
>+#define SDMA4_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
>+#define SDMA4_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
>+#define SDMA4_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT                                                    0xf
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT                                                    0x10
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT                                                   0x11
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT                                                   0x12
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT                                                   0x13
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT                                                   0x14
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT                                                   0x15
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT                                                   0x16
>+#define SDMA4_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0x17
>+#define SDMA4_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x18
>+#define SDMA4_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK                                                            0x00000001L
>+#define SDMA4_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
>+#define SDMA4_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
>+#define SDMA4_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
>+#define SDMA4_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
>+#define SDMA4_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK                                                      0x00008000L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK                                                      0x00010000L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK                                                     0x00020000L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK                                                     0x00040000L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK                                                     0x00080000L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK                                                     0x00100000L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK                                                     0x00200000L
>+#define SDMA4_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK                                                     0x00400000L
>+#define SDMA4_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00800000L
>+#define SDMA4_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x01000000L
>+//SDMA4_EDC_COUNTER_CLEAR
>+#define SDMA4_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
>+#define SDMA4_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
>+//SDMA4_STATUS2_REG
>+#define SDMA4_STATUS2_REG__ID__SHIFT                                                                          0x0
>+#define SDMA4_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x3
>+#define SDMA4_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
>+#define SDMA4_STATUS2_REG__ID_MASK                                                                            0x00000007L
>+#define SDMA4_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFF8L
>+#define SDMA4_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
>+//SDMA4_ATOMIC_CNTL
>+#define SDMA4_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
>+#define SDMA4_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
>+#define SDMA4_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
>+#define SDMA4_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
>+//SDMA4_ATOMIC_PREOP_LO
>+#define SDMA4_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
>+#define SDMA4_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_ATOMIC_PREOP_HI
>+#define SDMA4_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
>+#define SDMA4_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_UTCL1_CNTL
>+#define SDMA4_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
>+#define SDMA4_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0xb
>+#define SDMA4_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0xe
>+#define SDMA4_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
>+#define SDMA4_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
>+#define SDMA4_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x000007FEL
>+#define SDMA4_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x00003800L
>+#define SDMA4_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FFC000L
>+#define SDMA4_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
>+#define SDMA4_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
>+//SDMA4_UTCL1_WATERMK
>+#define SDMA4_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
>+#define SDMA4_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0x9
>+#define SDMA4_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x11
>+#define SDMA4_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x19
>+#define SDMA4_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000001FFL
>+#define SDMA4_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0001FE00L
>+#define SDMA4_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x01FE0000L
>+#define SDMA4_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFE000000L
>+//SDMA4_UTCL1_RD_STATUS
>+#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA4_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA4_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA4_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA4_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT                                                             0x15
>+#define SDMA4_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x16
>+#define SDMA4_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x1a
>+#define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x1d
>+#define SDMA4_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT                                                            0x1e
>+#define SDMA4_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT                                                             0x1f
>+#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA4_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA4_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA4_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA4_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA4_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA4_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA4_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA4_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA4_UTCL1_RD_STATUS__CE_L1_STALL_MASK                                                               0x00200000L
>+#define SDMA4_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x03C00000L
>+#define SDMA4_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x1C000000L
>+#define SDMA4_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x20000000L
>+#define SDMA4_UTCL1_RD_STATUS__WPTR_POLLING_MASK                                                              0x40000000L
>+#define SDMA4_UTCL1_RD_STATUS__INVREQ_SIZE_MASK                                                               0x80000000L
>+//SDMA4_UTCL1_WR_STATUS
>+#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA4_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA4_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA4_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA4_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15
>+#define SDMA4_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x16
>+#define SDMA4_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19
>+#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
>+#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
>+#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
>+#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
>+#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA4_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA4_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA4_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA4_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA4_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA4_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA4_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA4_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA4_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x00200000L
>+#define SDMA4_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x01C00000L
>+#define SDMA4_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x0E000000L
>+#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
>+#define SDMA4_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
>+#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
>+#define SDMA4_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
>+//SDMA4_UTCL1_INV0
>+#define SDMA4_UTCL1_INV0__INV_MIDDLE__SHIFT                                                                   0x0
>+#define SDMA4_UTCL1_INV0__RD_TIMEOUT__SHIFT                                                                   0x1
>+#define SDMA4_UTCL1_INV0__WR_TIMEOUT__SHIFT                                                                   0x2
>+#define SDMA4_UTCL1_INV0__RD_IN_INVADR__SHIFT                                                                 0x3
>+#define SDMA4_UTCL1_INV0__WR_IN_INVADR__SHIFT                                                                 0x4
>+#define SDMA4_UTCL1_INV0__PAGE_NULL_SW__SHIFT                                                                 0x5
>+#define SDMA4_UTCL1_INV0__XNACK_IS_INVADR__SHIFT                                                              0x6
>+#define SDMA4_UTCL1_INV0__INVREQ_ENABLE__SHIFT                                                                0x7
>+#define SDMA4_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT                                                              0x8
>+#define SDMA4_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT                                                              0x9
>+#define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT                                                               0xa
>+#define SDMA4_UTCL1_INV0__INV_FLUSHTYPE__SHIFT                                                                0xb
>+#define SDMA4_UTCL1_INV0__INV_VMID_VEC__SHIFT                                                                 0xc
>+#define SDMA4_UTCL1_INV0__INV_ADDR_HI__SHIFT                                                                  0x1c
>+#define SDMA4_UTCL1_INV0__INV_MIDDLE_MASK                                                                     0x00000001L
>+#define SDMA4_UTCL1_INV0__RD_TIMEOUT_MASK                                                                     0x00000002L
>+#define SDMA4_UTCL1_INV0__WR_TIMEOUT_MASK                                                                     0x00000004L
>+#define SDMA4_UTCL1_INV0__RD_IN_INVADR_MASK                                                                   0x00000008L
>+#define SDMA4_UTCL1_INV0__WR_IN_INVADR_MASK                                                                   0x00000010L
>+#define SDMA4_UTCL1_INV0__PAGE_NULL_SW_MASK                                                                   0x00000020L
>+#define SDMA4_UTCL1_INV0__XNACK_IS_INVADR_MASK                                                                0x00000040L
>+#define SDMA4_UTCL1_INV0__INVREQ_ENABLE_MASK                                                                  0x00000080L
>+#define SDMA4_UTCL1_INV0__NACK_TIMEOUT_SW_MASK                                                                0x00000100L
>+#define SDMA4_UTCL1_INV0__NFLUSH_INV_IDLE_MASK                                                                0x00000200L
>+#define SDMA4_UTCL1_INV0__FLUSH_INV_IDLE_MASK                                                                 0x00000400L
>+#define SDMA4_UTCL1_INV0__INV_FLUSHTYPE_MASK                                                                  0x00000800L
>+#define SDMA4_UTCL1_INV0__INV_VMID_VEC_MASK                                                                   0x0FFFF000L
>+#define SDMA4_UTCL1_INV0__INV_ADDR_HI_MASK                                                                    0xF0000000L
>+//SDMA4_UTCL1_INV1
>+#define SDMA4_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
>+#define SDMA4_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_UTCL1_INV2
>+#define SDMA4_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT                                                          0x0
>+#define SDMA4_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK                                                            0xFFFFFFFFL
>+//SDMA4_UTCL1_RD_XNACK0
>+#define SDMA4_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA4_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA4_UTCL1_RD_XNACK1
>+#define SDMA4_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA4_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA4_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA4_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA4_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA4_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA4_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA4_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA4_UTCL1_WR_XNACK0
>+#define SDMA4_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA4_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA4_UTCL1_WR_XNACK1
>+#define SDMA4_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA4_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA4_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA4_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA4_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA4_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA4_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA4_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA4_UTCL1_TIMEOUT
>+#define SDMA4_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
>+#define SDMA4_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
>+#define SDMA4_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
>+#define SDMA4_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
>+//SDMA4_UTCL1_PAGE
>+#define SDMA4_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
>+#define SDMA4_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
>+#define SDMA4_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
>+#define SDMA4_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0x9
>+#define SDMA4_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
>+#define SDMA4_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
>+#define SDMA4_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000001C0L
>+#define SDMA4_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000200L
>+//SDMA4_POWER_CNTL_IDLE
>+#define SDMA4_POWER_CNTL_IDLE__DELAY0__SHIFT                                                                  0x0
>+#define SDMA4_POWER_CNTL_IDLE__DELAY1__SHIFT                                                                  0x10
>+#define SDMA4_POWER_CNTL_IDLE__DELAY2__SHIFT                                                                  0x18
>+#define SDMA4_POWER_CNTL_IDLE__DELAY0_MASK                                                                    0x0000FFFFL
>+#define SDMA4_POWER_CNTL_IDLE__DELAY1_MASK                                                                    0x00FF0000L
>+#define SDMA4_POWER_CNTL_IDLE__DELAY2_MASK                                                                    0xFF000000L
>+//SDMA4_RELAX_ORDERING_LUT
>+#define SDMA4_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
>+#define SDMA4_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
>+#define SDMA4_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
>+#define SDMA4_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
>+#define SDMA4_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
>+#define SDMA4_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
>+#define SDMA4_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
>+#define SDMA4_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
>+#define SDMA4_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
>+#define SDMA4_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
>+#define SDMA4_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
>+#define SDMA4_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
>+#define SDMA4_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
>+#define SDMA4_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
>+#define SDMA4_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
>+#define SDMA4_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
>+#define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
>+#define SDMA4_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
>+#define SDMA4_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
>+#define SDMA4_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
>+#define SDMA4_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
>+#define SDMA4_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
>+#define SDMA4_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
>+#define SDMA4_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
>+#define SDMA4_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
>+#define SDMA4_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
>+#define SDMA4_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
>+#define SDMA4_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
>+#define SDMA4_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
>+#define SDMA4_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
>+#define SDMA4_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
>+#define SDMA4_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
>+#define SDMA4_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
>+#define SDMA4_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
>+#define SDMA4_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
>+#define SDMA4_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
>+#define SDMA4_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
>+#define SDMA4_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
>+//SDMA4_CHICKEN_BITS_2
>+#define SDMA4_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
>+#define SDMA4_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
>+//SDMA4_STATUS3_REG
>+#define SDMA4_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
>+#define SDMA4_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
>+#define SDMA4_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
>+#define SDMA4_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x15
>+#define SDMA4_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x16
>+#define SDMA4_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
>+#define SDMA4_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
>+#define SDMA4_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
>+#define SDMA4_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x00200000L
>+#define SDMA4_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x03C00000L
>+//SDMA4_PHYSICAL_ADDR_LO
>+#define SDMA4_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
>+#define SDMA4_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
>+#define SDMA4_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
>+#define SDMA4_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
>+#define SDMA4_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
>+#define SDMA4_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
>+#define SDMA4_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
>+#define SDMA4_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
>+//SDMA4_PHYSICAL_ADDR_HI
>+#define SDMA4_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA4_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
>+//SDMA4_PHASE2_QUANTUM
>+#define SDMA4_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA4_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA4_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA4_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA4_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA4_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA4_ERROR_LOG
>+#define SDMA4_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
>+#define SDMA4_ERROR_LOG__STATUS__SHIFT                                                                        0x10
>+#define SDMA4_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
>+#define SDMA4_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
>+//SDMA4_PUB_DUMMY_REG0
>+#define SDMA4_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
>+#define SDMA4_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_PUB_DUMMY_REG1
>+#define SDMA4_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
>+#define SDMA4_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_PUB_DUMMY_REG2
>+#define SDMA4_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
>+#define SDMA4_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_PUB_DUMMY_REG3
>+#define SDMA4_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
>+#define SDMA4_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_F32_COUNTER
>+#define SDMA4_F32_COUNTER__VALUE__SHIFT                                                                       0x0
>+#define SDMA4_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
>+//SDMA4_UNBREAKABLE
>+#define SDMA4_UNBREAKABLE__VALUE__SHIFT                                                                       0x0
>+#define SDMA4_UNBREAKABLE__VALUE_MASK                                                                         0x00000001L
>+//SDMA4_PERFMON_CNTL
>+#define SDMA4_PERFMON_CNTL__PERF_ENABLE0__SHIFT                                                               0x0
>+#define SDMA4_PERFMON_CNTL__PERF_CLEAR0__SHIFT                                                                0x1
>+#define SDMA4_PERFMON_CNTL__PERF_SEL0__SHIFT                                                                  0x2
>+#define SDMA4_PERFMON_CNTL__PERF_ENABLE1__SHIFT                                                               0xa
>+#define SDMA4_PERFMON_CNTL__PERF_CLEAR1__SHIFT                                                                0xb
>+#define SDMA4_PERFMON_CNTL__PERF_SEL1__SHIFT                                                                  0xc
>+#define SDMA4_PERFMON_CNTL__PERF_ENABLE0_MASK                                                                 0x00000001L
>+#define SDMA4_PERFMON_CNTL__PERF_CLEAR0_MASK                                                                  0x00000002L
>+#define SDMA4_PERFMON_CNTL__PERF_SEL0_MASK                                                                    0x000003FCL
>+#define SDMA4_PERFMON_CNTL__PERF_ENABLE1_MASK                                                                 0x00000400L
>+#define SDMA4_PERFMON_CNTL__PERF_CLEAR1_MASK                                                                  0x00000800L
>+#define SDMA4_PERFMON_CNTL__PERF_SEL1_MASK                                                                    0x000FF000L
>+//SDMA4_PERFCOUNTER0_RESULT
>+#define SDMA4_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA4_PERFCOUNTER0_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA4_PERFCOUNTER1_RESULT
>+#define SDMA4_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA4_PERFCOUNTER1_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA4_PERFCOUNTER_TAG_DELAY_RANGE
>+#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT                                                   0x0
>+#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT                                                  0xe
>+#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT                                                   0x1c
>+#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK                                                     0x00003FFFL
>+#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK                                                    0x0FFFC000L
>+#define SDMA4_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK                                                     0x10000000L
>+//SDMA4_CRD_CNTL
>+#define SDMA4_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
>+#define SDMA4_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
>+#define SDMA4_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
>+#define SDMA4_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
>+//SDMA4_GPU_IOV_VIOLATION_LOG
>+#define SDMA4_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT                                                  0x0
>+#define SDMA4_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT                                         0x1
>+#define SDMA4_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT                                                           0x2
>+#define SDMA4_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT                                                   0x14
>+#define SDMA4_GPU_IOV_VIOLATION_LOG__VF__SHIFT                                                                0x15
>+#define SDMA4_GPU_IOV_VIOLATION_LOG__VFID__SHIFT                                                              0x16
>+#define SDMA4_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK                                                    0x00000001L
>+#define SDMA4_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK                                           0x00000002L
>+#define SDMA4_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK                                                             0x000FFFFCL
>+#define SDMA4_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK                                                     0x00100000L
>+#define SDMA4_GPU_IOV_VIOLATION_LOG__VF_MASK                                                                  0x00200000L
>+#define SDMA4_GPU_IOV_VIOLATION_LOG__VFID_MASK                                                                0x03C00000L
>+//SDMA4_ULV_CNTL
>+#define SDMA4_ULV_CNTL__HYSTERESIS__SHIFT                                                                     0x0
>+#define SDMA4_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT                                                              0x1b
>+#define SDMA4_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT                                                               0x1c
>+#define SDMA4_ULV_CNTL__ENTER_ULV_INT__SHIFT                                                                  0x1d
>+#define SDMA4_ULV_CNTL__EXIT_ULV_INT__SHIFT                                                                   0x1e
>+#define SDMA4_ULV_CNTL__ULV_STATUS__SHIFT                                                                     0x1f
>+#define SDMA4_ULV_CNTL__HYSTERESIS_MASK                                                                       0x0000001FL
>+#define SDMA4_ULV_CNTL__ENTER_ULV_INT_CLR_MASK                                                                0x08000000L
>+#define SDMA4_ULV_CNTL__EXIT_ULV_INT_CLR_MASK                                                                 0x10000000L
>+#define SDMA4_ULV_CNTL__ENTER_ULV_INT_MASK                                                                    0x20000000L
>+#define SDMA4_ULV_CNTL__EXIT_ULV_INT_MASK                                                                     0x40000000L
>+#define SDMA4_ULV_CNTL__ULV_STATUS_MASK                                                                       0x80000000L
>+//SDMA4_EA_DBIT_ADDR_DATA
>+#define SDMA4_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
>+#define SDMA4_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_EA_DBIT_ADDR_INDEX
>+#define SDMA4_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
>+#define SDMA4_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
>+//SDMA4_GPU_IOV_VIOLATION_LOG2
>+#define SDMA4_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                     0x0
>+#define SDMA4_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                       0x000000FFL
>+//SDMA4_GFX_RB_CNTL
>+#define SDMA4_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA4_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
>+#define SDMA4_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
>+#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
>+#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
>+#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
>+#define SDMA4_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
>+#define SDMA4_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
>+#define SDMA4_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA4_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
>+#define SDMA4_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
>+#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
>+#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
>+#define SDMA4_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
>+#define SDMA4_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
>+#define SDMA4_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
>+//SDMA4_GFX_RB_BASE
>+#define SDMA4_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
>+#define SDMA4_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
>+//SDMA4_GFX_RB_BASE_HI
>+#define SDMA4_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA4_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
>+//SDMA4_GFX_RB_RPTR
>+#define SDMA4_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA4_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA4_GFX_RB_RPTR_HI
>+#define SDMA4_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA4_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA4_GFX_RB_WPTR
>+#define SDMA4_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA4_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA4_GFX_RB_WPTR_HI
>+#define SDMA4_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA4_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA4_GFX_RB_WPTR_POLL_CNTL
>+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
>+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
>+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
>+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
>+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
>+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
>+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
>+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
>+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
>+#define SDMA4_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
>+//SDMA4_GFX_RB_RPTR_ADDR_HI
>+#define SDMA4_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
>+#define SDMA4_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
>+//SDMA4_GFX_RB_RPTR_ADDR_LO
>+#define SDMA4_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                        0x0
>+#define SDMA4_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
>+#define SDMA4_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                          0x00000001L
>+#define SDMA4_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
>+//SDMA4_GFX_IB_CNTL
>+#define SDMA4_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA4_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
>+#define SDMA4_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
>+#define SDMA4_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
>+#define SDMA4_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA4_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
>+#define SDMA4_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
>+#define SDMA4_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
>+//SDMA4_GFX_IB_RPTR
>+#define SDMA4_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
>+#define SDMA4_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
>+//SDMA4_GFX_IB_OFFSET
>+#define SDMA4_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
>+#define SDMA4_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
>+//SDMA4_GFX_IB_BASE_LO
>+#define SDMA4_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
>+#define SDMA4_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
>+//SDMA4_GFX_IB_BASE_HI
>+#define SDMA4_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA4_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_GFX_IB_SIZE
>+#define SDMA4_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
>+#define SDMA4_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
>+//SDMA4_GFX_SKIP_CNTL
>+#define SDMA4_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
>+#define SDMA4_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
>+//SDMA4_GFX_CONTEXT_STATUS
>+#define SDMA4_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
>+#define SDMA4_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
>+#define SDMA4_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
>+#define SDMA4_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
>+#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
>+#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
>+#define SDMA4_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
>+#define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
>+#define SDMA4_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
>+#define SDMA4_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
>+#define SDMA4_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
>+#define SDMA4_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
>+#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
>+#define SDMA4_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
>+#define SDMA4_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
>+#define SDMA4_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
>+//SDMA4_GFX_DOORBELL
>+#define SDMA4_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
>+#define SDMA4_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
>+#define SDMA4_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
>+#define SDMA4_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
>+//SDMA4_GFX_CONTEXT_CNTL
>+#define SDMA4_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
>+#define SDMA4_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
>+//SDMA4_GFX_STATUS
>+#define SDMA4_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
>+#define SDMA4_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
>+#define SDMA4_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
>+#define SDMA4_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
>+//SDMA4_GFX_DOORBELL_LOG
>+#define SDMA4_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
>+#define SDMA4_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
>+#define SDMA4_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
>+#define SDMA4_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
>+//SDMA4_GFX_WATERMARK
>+#define SDMA4_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
>+#define SDMA4_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
>+#define SDMA4_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
>+#define SDMA4_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
>+//SDMA4_GFX_DOORBELL_OFFSET
>+#define SDMA4_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
>+#define SDMA4_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
>+//SDMA4_GFX_CSA_ADDR_LO
>+#define SDMA4_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
>+#define SDMA4_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
>+//SDMA4_GFX_CSA_ADDR_HI
>+#define SDMA4_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_GFX_IB_SUB_REMAIN
>+#define SDMA4_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
>+#define SDMA4_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x000FFFFFL
>+//SDMA4_GFX_PREEMPT
>+#define SDMA4_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
>+#define SDMA4_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
>+//SDMA4_GFX_DUMMY_REG
>+#define SDMA4_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
>+#define SDMA4_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_GFX_RB_WPTR_POLL_ADDR_HI
>+#define SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
>+#define SDMA4_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
>+//SDMA4_GFX_RB_WPTR_POLL_ADDR_LO
>+#define SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
>+#define SDMA4_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
>+//SDMA4_GFX_RB_AQL_CNTL
>+#define SDMA4_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
>+#define SDMA4_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
>+#define SDMA4_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
>+#define SDMA4_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
>+#define SDMA4_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
>+#define SDMA4_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
>+//SDMA4_GFX_MINOR_PTR_UPDATE
>+#define SDMA4_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
>+#define SDMA4_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
>+//SDMA4_GFX_MIDCMD_DATA0
>+#define SDMA4_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
>+#define SDMA4_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_GFX_MIDCMD_DATA1
>+#define SDMA4_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
>+#define SDMA4_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_GFX_MIDCMD_DATA2
>+#define SDMA4_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
>+#define SDMA4_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_GFX_MIDCMD_DATA3
>+#define SDMA4_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
>+#define SDMA4_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_GFX_MIDCMD_DATA4
>+#define SDMA4_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
>+#define SDMA4_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_GFX_MIDCMD_DATA5
>+#define SDMA4_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
>+#define SDMA4_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_GFX_MIDCMD_DATA6
>+#define SDMA4_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
>+#define SDMA4_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_GFX_MIDCMD_DATA7
>+#define SDMA4_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
>+#define SDMA4_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_GFX_MIDCMD_DATA8
>+#define SDMA4_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
>+#define SDMA4_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_GFX_MIDCMD_CNTL
>+#define SDMA4_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
>+#define SDMA4_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
>+#define SDMA4_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
>+#define SDMA4_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
>+#define SDMA4_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
>+#define SDMA4_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
>+#define SDMA4_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
>+#define SDMA4_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
>+//SDMA4_PAGE_RB_CNTL
>+#define SDMA4_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA4_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA4_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA4_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA4_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA4_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA4_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA4_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA4_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA4_PAGE_RB_BASE
>+#define SDMA4_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA4_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA4_PAGE_RB_BASE_HI
>+#define SDMA4_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA4_PAGE_RB_RPTR
>+#define SDMA4_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_PAGE_RB_RPTR_HI
>+#define SDMA4_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_PAGE_RB_WPTR
>+#define SDMA4_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_PAGE_RB_WPTR_HI
>+#define SDMA4_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_PAGE_RB_WPTR_POLL_CNTL
>+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA4_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA4_PAGE_RB_RPTR_ADDR_HI
>+#define SDMA4_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA4_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA4_PAGE_RB_RPTR_ADDR_LO
>+#define SDMA4_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA4_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA4_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA4_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA4_PAGE_IB_CNTL
>+#define SDMA4_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA4_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA4_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA4_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA4_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA4_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA4_PAGE_IB_RPTR
>+#define SDMA4_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA4_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA4_PAGE_IB_OFFSET
>+#define SDMA4_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA4_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA4_PAGE_IB_BASE_LO
>+#define SDMA4_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA4_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA4_PAGE_IB_BASE_HI
>+#define SDMA4_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_PAGE_IB_SIZE
>+#define SDMA4_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA4_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA4_PAGE_SKIP_CNTL
>+#define SDMA4_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA4_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA4_PAGE_CONTEXT_STATUS
>+#define SDMA4_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA4_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA4_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA4_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA4_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA4_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA4_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA4_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA4_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA4_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA4_PAGE_DOORBELL
>+#define SDMA4_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA4_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA4_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA4_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA4_PAGE_STATUS
>+#define SDMA4_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA4_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA4_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA4_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA4_PAGE_DOORBELL_LOG
>+#define SDMA4_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA4_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA4_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA4_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA4_PAGE_WATERMARK
>+#define SDMA4_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA4_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA4_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA4_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA4_PAGE_DOORBELL_OFFSET
>+#define SDMA4_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA4_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA4_PAGE_CSA_ADDR_LO
>+#define SDMA4_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA4_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA4_PAGE_CSA_ADDR_HI
>+#define SDMA4_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA4_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA4_PAGE_IB_SUB_REMAIN
>+#define SDMA4_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA4_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA4_PAGE_PREEMPT
>+#define SDMA4_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA4_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA4_PAGE_DUMMY_REG
>+#define SDMA4_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA4_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI
>+#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO
>+#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA4_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA4_PAGE_RB_AQL_CNTL
>+#define SDMA4_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA4_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA4_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA4_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA4_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA4_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA4_PAGE_MINOR_PTR_UPDATE
>+#define SDMA4_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA4_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA4_PAGE_MIDCMD_DATA0
>+#define SDMA4_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA4_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_PAGE_MIDCMD_DATA1
>+#define SDMA4_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA4_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_PAGE_MIDCMD_DATA2
>+#define SDMA4_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA4_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_PAGE_MIDCMD_DATA3
>+#define SDMA4_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA4_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_PAGE_MIDCMD_DATA4
>+#define SDMA4_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA4_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_PAGE_MIDCMD_DATA5
>+#define SDMA4_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA4_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_PAGE_MIDCMD_DATA6
>+#define SDMA4_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA4_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_PAGE_MIDCMD_DATA7
>+#define SDMA4_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA4_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_PAGE_MIDCMD_DATA8
>+#define SDMA4_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA4_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_PAGE_MIDCMD_CNTL
>+#define SDMA4_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA4_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA4_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA4_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA4_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA4_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA4_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA4_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA4_RLC0_RB_CNTL
>+#define SDMA4_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA4_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA4_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA4_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA4_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA4_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA4_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA4_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA4_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA4_RLC0_RB_BASE
>+#define SDMA4_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA4_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA4_RLC0_RB_BASE_HI
>+#define SDMA4_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA4_RLC0_RB_RPTR
>+#define SDMA4_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC0_RB_RPTR_HI
>+#define SDMA4_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC0_RB_WPTR
>+#define SDMA4_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC0_RB_WPTR_HI
>+#define SDMA4_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC0_RB_WPTR_POLL_CNTL
>+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA4_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA4_RLC0_RB_RPTR_ADDR_HI
>+#define SDMA4_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA4_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA4_RLC0_RB_RPTR_ADDR_LO
>+#define SDMA4_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA4_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA4_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA4_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA4_RLC0_IB_CNTL
>+#define SDMA4_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA4_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA4_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA4_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA4_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA4_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA4_RLC0_IB_RPTR
>+#define SDMA4_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA4_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA4_RLC0_IB_OFFSET
>+#define SDMA4_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA4_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA4_RLC0_IB_BASE_LO
>+#define SDMA4_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA4_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA4_RLC0_IB_BASE_HI
>+#define SDMA4_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC0_IB_SIZE
>+#define SDMA4_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA4_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA4_RLC0_SKIP_CNTL
>+#define SDMA4_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA4_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA4_RLC0_CONTEXT_STATUS
>+#define SDMA4_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA4_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA4_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA4_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA4_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA4_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA4_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA4_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA4_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA4_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA4_RLC0_DOORBELL
>+#define SDMA4_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA4_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA4_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA4_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA4_RLC0_STATUS
>+#define SDMA4_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA4_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA4_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA4_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA4_RLC0_DOORBELL_LOG
>+#define SDMA4_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA4_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA4_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA4_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA4_RLC0_WATERMARK
>+#define SDMA4_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA4_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA4_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA4_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA4_RLC0_DOORBELL_OFFSET
>+#define SDMA4_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA4_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA4_RLC0_CSA_ADDR_LO
>+#define SDMA4_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA4_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA4_RLC0_CSA_ADDR_HI
>+#define SDMA4_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA4_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA4_RLC0_IB_SUB_REMAIN
>+#define SDMA4_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA4_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA4_RLC0_PREEMPT
>+#define SDMA4_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA4_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA4_RLC0_DUMMY_REG
>+#define SDMA4_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA4_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI
>+#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO
>+#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA4_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA4_RLC0_RB_AQL_CNTL
>+#define SDMA4_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA4_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA4_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA4_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA4_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA4_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA4_RLC0_MINOR_PTR_UPDATE
>+#define SDMA4_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA4_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA4_RLC0_MIDCMD_DATA0
>+#define SDMA4_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA4_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC0_MIDCMD_DATA1
>+#define SDMA4_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA4_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC0_MIDCMD_DATA2
>+#define SDMA4_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA4_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC0_MIDCMD_DATA3
>+#define SDMA4_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA4_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC0_MIDCMD_DATA4
>+#define SDMA4_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA4_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC0_MIDCMD_DATA5
>+#define SDMA4_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA4_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC0_MIDCMD_DATA6
>+#define SDMA4_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA4_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC0_MIDCMD_DATA7
>+#define SDMA4_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA4_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC0_MIDCMD_DATA8
>+#define SDMA4_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA4_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC0_MIDCMD_CNTL
>+#define SDMA4_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA4_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA4_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA4_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA4_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA4_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA4_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA4_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA4_RLC1_RB_CNTL
>+#define SDMA4_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA4_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA4_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA4_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA4_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA4_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA4_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA4_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA4_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA4_RLC1_RB_BASE
>+#define SDMA4_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA4_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA4_RLC1_RB_BASE_HI
>+#define SDMA4_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA4_RLC1_RB_RPTR
>+#define SDMA4_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC1_RB_RPTR_HI
>+#define SDMA4_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC1_RB_WPTR
>+#define SDMA4_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC1_RB_WPTR_HI
>+#define SDMA4_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC1_RB_WPTR_POLL_CNTL
>+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA4_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA4_RLC1_RB_RPTR_ADDR_HI
>+#define SDMA4_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA4_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA4_RLC1_RB_RPTR_ADDR_LO
>+#define SDMA4_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA4_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA4_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA4_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA4_RLC1_IB_CNTL
>+#define SDMA4_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA4_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA4_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA4_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA4_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA4_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA4_RLC1_IB_RPTR
>+#define SDMA4_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA4_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA4_RLC1_IB_OFFSET
>+#define SDMA4_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA4_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA4_RLC1_IB_BASE_LO
>+#define SDMA4_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA4_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA4_RLC1_IB_BASE_HI
>+#define SDMA4_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC1_IB_SIZE
>+#define SDMA4_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA4_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA4_RLC1_SKIP_CNTL
>+#define SDMA4_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA4_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA4_RLC1_CONTEXT_STATUS
>+#define SDMA4_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA4_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA4_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA4_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA4_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA4_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA4_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA4_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA4_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA4_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA4_RLC1_DOORBELL
>+#define SDMA4_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA4_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA4_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA4_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA4_RLC1_STATUS
>+#define SDMA4_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA4_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA4_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA4_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA4_RLC1_DOORBELL_LOG
>+#define SDMA4_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA4_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA4_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA4_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA4_RLC1_WATERMARK
>+#define SDMA4_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA4_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA4_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA4_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA4_RLC1_DOORBELL_OFFSET
>+#define SDMA4_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA4_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA4_RLC1_CSA_ADDR_LO
>+#define SDMA4_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA4_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA4_RLC1_CSA_ADDR_HI
>+#define SDMA4_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA4_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA4_RLC1_IB_SUB_REMAIN
>+#define SDMA4_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA4_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA4_RLC1_PREEMPT
>+#define SDMA4_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA4_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA4_RLC1_DUMMY_REG
>+#define SDMA4_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA4_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI
>+#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO
>+#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA4_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA4_RLC1_RB_AQL_CNTL
>+#define SDMA4_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA4_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA4_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA4_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA4_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA4_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA4_RLC1_MINOR_PTR_UPDATE
>+#define SDMA4_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA4_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA4_RLC1_MIDCMD_DATA0
>+#define SDMA4_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA4_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC1_MIDCMD_DATA1
>+#define SDMA4_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA4_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC1_MIDCMD_DATA2
>+#define SDMA4_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA4_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC1_MIDCMD_DATA3
>+#define SDMA4_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA4_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC1_MIDCMD_DATA4
>+#define SDMA4_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA4_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC1_MIDCMD_DATA5
>+#define SDMA4_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA4_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC1_MIDCMD_DATA6
>+#define SDMA4_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA4_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC1_MIDCMD_DATA7
>+#define SDMA4_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA4_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC1_MIDCMD_DATA8
>+#define SDMA4_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA4_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC1_MIDCMD_CNTL
>+#define SDMA4_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA4_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA4_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA4_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA4_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA4_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA4_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA4_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA4_RLC2_RB_CNTL
>+#define SDMA4_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA4_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA4_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA4_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA4_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA4_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA4_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA4_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA4_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA4_RLC2_RB_BASE
>+#define SDMA4_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA4_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA4_RLC2_RB_BASE_HI
>+#define SDMA4_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA4_RLC2_RB_RPTR
>+#define SDMA4_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC2_RB_RPTR_HI
>+#define SDMA4_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC2_RB_WPTR
>+#define SDMA4_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC2_RB_WPTR_HI
>+#define SDMA4_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC2_RB_WPTR_POLL_CNTL
>+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA4_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA4_RLC2_RB_RPTR_ADDR_HI
>+#define SDMA4_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA4_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA4_RLC2_RB_RPTR_ADDR_LO
>+#define SDMA4_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA4_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA4_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA4_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA4_RLC2_IB_CNTL
>+#define SDMA4_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA4_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA4_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA4_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA4_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA4_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA4_RLC2_IB_RPTR
>+#define SDMA4_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA4_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA4_RLC2_IB_OFFSET
>+#define SDMA4_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA4_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA4_RLC2_IB_BASE_LO
>+#define SDMA4_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA4_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA4_RLC2_IB_BASE_HI
>+#define SDMA4_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC2_IB_SIZE
>+#define SDMA4_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA4_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA4_RLC2_SKIP_CNTL
>+#define SDMA4_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA4_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA4_RLC2_CONTEXT_STATUS
>+#define SDMA4_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA4_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA4_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA4_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA4_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA4_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA4_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA4_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA4_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA4_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA4_RLC2_DOORBELL
>+#define SDMA4_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA4_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA4_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA4_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA4_RLC2_STATUS
>+#define SDMA4_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA4_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA4_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA4_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA4_RLC2_DOORBELL_LOG
>+#define SDMA4_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA4_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA4_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA4_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA4_RLC2_WATERMARK
>+#define SDMA4_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA4_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA4_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA4_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA4_RLC2_DOORBELL_OFFSET
>+#define SDMA4_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA4_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA4_RLC2_CSA_ADDR_LO
>+#define SDMA4_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA4_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA4_RLC2_CSA_ADDR_HI
>+#define SDMA4_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA4_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA4_RLC2_IB_SUB_REMAIN
>+#define SDMA4_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA4_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA4_RLC2_PREEMPT
>+#define SDMA4_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA4_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA4_RLC2_DUMMY_REG
>+#define SDMA4_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA4_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI
>+#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO
>+#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA4_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA4_RLC2_RB_AQL_CNTL
>+#define SDMA4_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA4_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA4_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA4_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA4_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA4_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA4_RLC2_MINOR_PTR_UPDATE
>+#define SDMA4_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA4_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA4_RLC2_MIDCMD_DATA0
>+#define SDMA4_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA4_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC2_MIDCMD_DATA1
>+#define SDMA4_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA4_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC2_MIDCMD_DATA2
>+#define SDMA4_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA4_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC2_MIDCMD_DATA3
>+#define SDMA4_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA4_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC2_MIDCMD_DATA4
>+#define SDMA4_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA4_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC2_MIDCMD_DATA5
>+#define SDMA4_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA4_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC2_MIDCMD_DATA6
>+#define SDMA4_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA4_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC2_MIDCMD_DATA7
>+#define SDMA4_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA4_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC2_MIDCMD_DATA8
>+#define SDMA4_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA4_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC2_MIDCMD_CNTL
>+#define SDMA4_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA4_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA4_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA4_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA4_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA4_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA4_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA4_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA4_RLC3_RB_CNTL
>+#define SDMA4_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA4_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA4_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA4_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA4_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA4_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA4_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA4_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA4_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA4_RLC3_RB_BASE
>+#define SDMA4_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA4_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA4_RLC3_RB_BASE_HI
>+#define SDMA4_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA4_RLC3_RB_RPTR
>+#define SDMA4_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC3_RB_RPTR_HI
>+#define SDMA4_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC3_RB_WPTR
>+#define SDMA4_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC3_RB_WPTR_HI
>+#define SDMA4_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC3_RB_WPTR_POLL_CNTL
>+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA4_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA4_RLC3_RB_RPTR_ADDR_HI
>+#define SDMA4_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA4_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA4_RLC3_RB_RPTR_ADDR_LO
>+#define SDMA4_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA4_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA4_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA4_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA4_RLC3_IB_CNTL
>+#define SDMA4_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA4_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA4_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA4_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA4_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA4_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA4_RLC3_IB_RPTR
>+#define SDMA4_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA4_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA4_RLC3_IB_OFFSET
>+#define SDMA4_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA4_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA4_RLC3_IB_BASE_LO
>+#define SDMA4_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA4_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA4_RLC3_IB_BASE_HI
>+#define SDMA4_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC3_IB_SIZE
>+#define SDMA4_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA4_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA4_RLC3_SKIP_CNTL
>+#define SDMA4_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA4_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA4_RLC3_CONTEXT_STATUS
>+#define SDMA4_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA4_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA4_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA4_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA4_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA4_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA4_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA4_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA4_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA4_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA4_RLC3_DOORBELL
>+#define SDMA4_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA4_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA4_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA4_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA4_RLC3_STATUS
>+#define SDMA4_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA4_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA4_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA4_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA4_RLC3_DOORBELL_LOG
>+#define SDMA4_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA4_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA4_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA4_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA4_RLC3_WATERMARK
>+#define SDMA4_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA4_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA4_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA4_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA4_RLC3_DOORBELL_OFFSET
>+#define SDMA4_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA4_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA4_RLC3_CSA_ADDR_LO
>+#define SDMA4_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA4_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA4_RLC3_CSA_ADDR_HI
>+#define SDMA4_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA4_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA4_RLC3_IB_SUB_REMAIN
>+#define SDMA4_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA4_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA4_RLC3_PREEMPT
>+#define SDMA4_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA4_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA4_RLC3_DUMMY_REG
>+#define SDMA4_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA4_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI
>+#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO
>+#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA4_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA4_RLC3_RB_AQL_CNTL
>+#define SDMA4_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA4_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA4_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA4_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA4_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA4_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA4_RLC3_MINOR_PTR_UPDATE
>+#define SDMA4_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA4_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA4_RLC3_MIDCMD_DATA0
>+#define SDMA4_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA4_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC3_MIDCMD_DATA1
>+#define SDMA4_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA4_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC3_MIDCMD_DATA2
>+#define SDMA4_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA4_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC3_MIDCMD_DATA3
>+#define SDMA4_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA4_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC3_MIDCMD_DATA4
>+#define SDMA4_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA4_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC3_MIDCMD_DATA5
>+#define SDMA4_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA4_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC3_MIDCMD_DATA6
>+#define SDMA4_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA4_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC3_MIDCMD_DATA7
>+#define SDMA4_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA4_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC3_MIDCMD_DATA8
>+#define SDMA4_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA4_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC3_MIDCMD_CNTL
>+#define SDMA4_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA4_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA4_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA4_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA4_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA4_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA4_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA4_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA4_RLC4_RB_CNTL
>+#define SDMA4_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA4_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA4_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA4_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA4_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA4_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA4_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA4_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA4_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA4_RLC4_RB_BASE
>+#define SDMA4_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA4_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA4_RLC4_RB_BASE_HI
>+#define SDMA4_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA4_RLC4_RB_RPTR
>+#define SDMA4_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC4_RB_RPTR_HI
>+#define SDMA4_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC4_RB_WPTR
>+#define SDMA4_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC4_RB_WPTR_HI
>+#define SDMA4_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC4_RB_WPTR_POLL_CNTL
>+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA4_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA4_RLC4_RB_RPTR_ADDR_HI
>+#define SDMA4_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA4_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA4_RLC4_RB_RPTR_ADDR_LO
>+#define SDMA4_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA4_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA4_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA4_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA4_RLC4_IB_CNTL
>+#define SDMA4_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA4_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA4_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA4_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA4_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA4_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA4_RLC4_IB_RPTR
>+#define SDMA4_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA4_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA4_RLC4_IB_OFFSET
>+#define SDMA4_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA4_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA4_RLC4_IB_BASE_LO
>+#define SDMA4_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA4_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA4_RLC4_IB_BASE_HI
>+#define SDMA4_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC4_IB_SIZE
>+#define SDMA4_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA4_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA4_RLC4_SKIP_CNTL
>+#define SDMA4_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA4_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA4_RLC4_CONTEXT_STATUS
>+#define SDMA4_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA4_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA4_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA4_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA4_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA4_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA4_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA4_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA4_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA4_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA4_RLC4_DOORBELL
>+#define SDMA4_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA4_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA4_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA4_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA4_RLC4_STATUS
>+#define SDMA4_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA4_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA4_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA4_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA4_RLC4_DOORBELL_LOG
>+#define SDMA4_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA4_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA4_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA4_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA4_RLC4_WATERMARK
>+#define SDMA4_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA4_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA4_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA4_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA4_RLC4_DOORBELL_OFFSET
>+#define SDMA4_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA4_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA4_RLC4_CSA_ADDR_LO
>+#define SDMA4_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA4_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA4_RLC4_CSA_ADDR_HI
>+#define SDMA4_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA4_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA4_RLC4_IB_SUB_REMAIN
>+#define SDMA4_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA4_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA4_RLC4_PREEMPT
>+#define SDMA4_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA4_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA4_RLC4_DUMMY_REG
>+#define SDMA4_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA4_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI
>+#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO
>+#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA4_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA4_RLC4_RB_AQL_CNTL
>+#define SDMA4_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA4_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA4_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA4_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA4_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA4_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA4_RLC4_MINOR_PTR_UPDATE
>+#define SDMA4_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA4_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA4_RLC4_MIDCMD_DATA0
>+#define SDMA4_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA4_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC4_MIDCMD_DATA1
>+#define SDMA4_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA4_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC4_MIDCMD_DATA2
>+#define SDMA4_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA4_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC4_MIDCMD_DATA3
>+#define SDMA4_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA4_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC4_MIDCMD_DATA4
>+#define SDMA4_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA4_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC4_MIDCMD_DATA5
>+#define SDMA4_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA4_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC4_MIDCMD_DATA6
>+#define SDMA4_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA4_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC4_MIDCMD_DATA7
>+#define SDMA4_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA4_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC4_MIDCMD_DATA8
>+#define SDMA4_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA4_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC4_MIDCMD_CNTL
>+#define SDMA4_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA4_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA4_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA4_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA4_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA4_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA4_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA4_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA4_RLC5_RB_CNTL
>+#define SDMA4_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA4_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA4_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA4_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA4_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA4_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA4_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA4_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA4_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA4_RLC5_RB_BASE
>+#define SDMA4_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA4_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA4_RLC5_RB_BASE_HI
>+#define SDMA4_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA4_RLC5_RB_RPTR
>+#define SDMA4_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC5_RB_RPTR_HI
>+#define SDMA4_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC5_RB_WPTR
>+#define SDMA4_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC5_RB_WPTR_HI
>+#define SDMA4_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC5_RB_WPTR_POLL_CNTL
>+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA4_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA4_RLC5_RB_RPTR_ADDR_HI
>+#define SDMA4_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA4_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA4_RLC5_RB_RPTR_ADDR_LO
>+#define SDMA4_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA4_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA4_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA4_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA4_RLC5_IB_CNTL
>+#define SDMA4_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA4_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA4_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA4_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA4_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA4_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA4_RLC5_IB_RPTR
>+#define SDMA4_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA4_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA4_RLC5_IB_OFFSET
>+#define SDMA4_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA4_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA4_RLC5_IB_BASE_LO
>+#define SDMA4_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA4_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA4_RLC5_IB_BASE_HI
>+#define SDMA4_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC5_IB_SIZE
>+#define SDMA4_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA4_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA4_RLC5_SKIP_CNTL
>+#define SDMA4_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA4_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA4_RLC5_CONTEXT_STATUS
>+#define SDMA4_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA4_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA4_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA4_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA4_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA4_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA4_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA4_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA4_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA4_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA4_RLC5_DOORBELL
>+#define SDMA4_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA4_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA4_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA4_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA4_RLC5_STATUS
>+#define SDMA4_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA4_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA4_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA4_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA4_RLC5_DOORBELL_LOG
>+#define SDMA4_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA4_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA4_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA4_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA4_RLC5_WATERMARK
>+#define SDMA4_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA4_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA4_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA4_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA4_RLC5_DOORBELL_OFFSET
>+#define SDMA4_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA4_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA4_RLC5_CSA_ADDR_LO
>+#define SDMA4_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA4_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA4_RLC5_CSA_ADDR_HI
>+#define SDMA4_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA4_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA4_RLC5_IB_SUB_REMAIN
>+#define SDMA4_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA4_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA4_RLC5_PREEMPT
>+#define SDMA4_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA4_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA4_RLC5_DUMMY_REG
>+#define SDMA4_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA4_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI
>+#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO
>+#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA4_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA4_RLC5_RB_AQL_CNTL
>+#define SDMA4_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA4_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA4_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA4_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA4_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA4_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA4_RLC5_MINOR_PTR_UPDATE
>+#define SDMA4_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA4_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA4_RLC5_MIDCMD_DATA0
>+#define SDMA4_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA4_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC5_MIDCMD_DATA1
>+#define SDMA4_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA4_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC5_MIDCMD_DATA2
>+#define SDMA4_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA4_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC5_MIDCMD_DATA3
>+#define SDMA4_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA4_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC5_MIDCMD_DATA4
>+#define SDMA4_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA4_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC5_MIDCMD_DATA5
>+#define SDMA4_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA4_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC5_MIDCMD_DATA6
>+#define SDMA4_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA4_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC5_MIDCMD_DATA7
>+#define SDMA4_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA4_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC5_MIDCMD_DATA8
>+#define SDMA4_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA4_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC5_MIDCMD_CNTL
>+#define SDMA4_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA4_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA4_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA4_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA4_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA4_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA4_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA4_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA4_RLC6_RB_CNTL
>+#define SDMA4_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA4_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA4_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA4_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA4_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA4_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA4_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA4_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA4_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA4_RLC6_RB_BASE
>+#define SDMA4_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA4_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA4_RLC6_RB_BASE_HI
>+#define SDMA4_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA4_RLC6_RB_RPTR
>+#define SDMA4_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC6_RB_RPTR_HI
>+#define SDMA4_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC6_RB_WPTR
>+#define SDMA4_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC6_RB_WPTR_HI
>+#define SDMA4_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC6_RB_WPTR_POLL_CNTL
>+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA4_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA4_RLC6_RB_RPTR_ADDR_HI
>+#define SDMA4_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA4_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA4_RLC6_RB_RPTR_ADDR_LO
>+#define SDMA4_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA4_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA4_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA4_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA4_RLC6_IB_CNTL
>+#define SDMA4_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA4_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA4_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA4_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA4_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA4_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA4_RLC6_IB_RPTR
>+#define SDMA4_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA4_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA4_RLC6_IB_OFFSET
>+#define SDMA4_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA4_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA4_RLC6_IB_BASE_LO
>+#define SDMA4_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA4_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA4_RLC6_IB_BASE_HI
>+#define SDMA4_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC6_IB_SIZE
>+#define SDMA4_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA4_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA4_RLC6_SKIP_CNTL
>+#define SDMA4_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA4_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA4_RLC6_CONTEXT_STATUS
>+#define SDMA4_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA4_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA4_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA4_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA4_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA4_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA4_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA4_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA4_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA4_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA4_RLC6_DOORBELL
>+#define SDMA4_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA4_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA4_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA4_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA4_RLC6_STATUS
>+#define SDMA4_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA4_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA4_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA4_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA4_RLC6_DOORBELL_LOG
>+#define SDMA4_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA4_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA4_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA4_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA4_RLC6_WATERMARK
>+#define SDMA4_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA4_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA4_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA4_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA4_RLC6_DOORBELL_OFFSET
>+#define SDMA4_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA4_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA4_RLC6_CSA_ADDR_LO
>+#define SDMA4_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA4_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA4_RLC6_CSA_ADDR_HI
>+#define SDMA4_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA4_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA4_RLC6_IB_SUB_REMAIN
>+#define SDMA4_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA4_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA4_RLC6_PREEMPT
>+#define SDMA4_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA4_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA4_RLC6_DUMMY_REG
>+#define SDMA4_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA4_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI
>+#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO
>+#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA4_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA4_RLC6_RB_AQL_CNTL
>+#define SDMA4_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA4_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA4_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA4_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA4_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA4_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA4_RLC6_MINOR_PTR_UPDATE
>+#define SDMA4_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA4_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA4_RLC6_MIDCMD_DATA0
>+#define SDMA4_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA4_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC6_MIDCMD_DATA1
>+#define SDMA4_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA4_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC6_MIDCMD_DATA2
>+#define SDMA4_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA4_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC6_MIDCMD_DATA3
>+#define SDMA4_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA4_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC6_MIDCMD_DATA4
>+#define SDMA4_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA4_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC6_MIDCMD_DATA5
>+#define SDMA4_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA4_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC6_MIDCMD_DATA6
>+#define SDMA4_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA4_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC6_MIDCMD_DATA7
>+#define SDMA4_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA4_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC6_MIDCMD_DATA8
>+#define SDMA4_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA4_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC6_MIDCMD_CNTL
>+#define SDMA4_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA4_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA4_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA4_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA4_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA4_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA4_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA4_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA4_RLC7_RB_CNTL
>+#define SDMA4_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA4_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA4_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA4_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA4_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA4_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA4_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA4_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA4_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA4_RLC7_RB_BASE
>+#define SDMA4_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA4_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA4_RLC7_RB_BASE_HI
>+#define SDMA4_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA4_RLC7_RB_RPTR
>+#define SDMA4_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC7_RB_RPTR_HI
>+#define SDMA4_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC7_RB_WPTR
>+#define SDMA4_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA4_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA4_RLC7_RB_WPTR_HI
>+#define SDMA4_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA4_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA4_RLC7_RB_WPTR_POLL_CNTL
>+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA4_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA4_RLC7_RB_RPTR_ADDR_HI
>+#define SDMA4_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA4_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA4_RLC7_RB_RPTR_ADDR_LO
>+#define SDMA4_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA4_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA4_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA4_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA4_RLC7_IB_CNTL
>+#define SDMA4_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA4_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA4_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA4_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA4_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA4_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA4_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA4_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA4_RLC7_IB_RPTR
>+#define SDMA4_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA4_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA4_RLC7_IB_OFFSET
>+#define SDMA4_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA4_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA4_RLC7_IB_BASE_LO
>+#define SDMA4_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA4_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA4_RLC7_IB_BASE_HI
>+#define SDMA4_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA4_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC7_IB_SIZE
>+#define SDMA4_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA4_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA4_RLC7_SKIP_CNTL
>+#define SDMA4_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA4_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA4_RLC7_CONTEXT_STATUS
>+#define SDMA4_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA4_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA4_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA4_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA4_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA4_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA4_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA4_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA4_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA4_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA4_RLC7_DOORBELL
>+#define SDMA4_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA4_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA4_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA4_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA4_RLC7_STATUS
>+#define SDMA4_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA4_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA4_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA4_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA4_RLC7_DOORBELL_LOG
>+#define SDMA4_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA4_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA4_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA4_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA4_RLC7_WATERMARK
>+#define SDMA4_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA4_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA4_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA4_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA4_RLC7_DOORBELL_OFFSET
>+#define SDMA4_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA4_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA4_RLC7_CSA_ADDR_LO
>+#define SDMA4_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA4_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA4_RLC7_CSA_ADDR_HI
>+#define SDMA4_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA4_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA4_RLC7_IB_SUB_REMAIN
>+#define SDMA4_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA4_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA4_RLC7_PREEMPT
>+#define SDMA4_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA4_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA4_RLC7_DUMMY_REG
>+#define SDMA4_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA4_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI
>+#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO
>+#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA4_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA4_RLC7_RB_AQL_CNTL
>+#define SDMA4_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA4_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA4_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA4_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA4_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA4_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA4_RLC7_MINOR_PTR_UPDATE
>+#define SDMA4_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA4_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA4_RLC7_MIDCMD_DATA0
>+#define SDMA4_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA4_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC7_MIDCMD_DATA1
>+#define SDMA4_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA4_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC7_MIDCMD_DATA2
>+#define SDMA4_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA4_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC7_MIDCMD_DATA3
>+#define SDMA4_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA4_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC7_MIDCMD_DATA4
>+#define SDMA4_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA4_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC7_MIDCMD_DATA5
>+#define SDMA4_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA4_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC7_MIDCMD_DATA6
>+#define SDMA4_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA4_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC7_MIDCMD_DATA7
>+#define SDMA4_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA4_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC7_MIDCMD_DATA8
>+#define SDMA4_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA4_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA4_RLC7_MIDCMD_CNTL
>+#define SDMA4_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA4_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA4_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA4_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA4_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA4_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA4_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA4_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_offset.h	2019-08-31 15:01:11.933736175 -0500
>@@ -0,0 +1,1043 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma5_4_2_2_OFFSET_HEADER
>+#define _sdma5_4_2_2_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: sdma5_sdma5dec
>+// base address: 0x7b000
>+#define mmSDMA5_UCODE_ADDR                                                                             0x0000
>+#define mmSDMA5_UCODE_ADDR_BASE_IDX                                                                    1
>+#define mmSDMA5_UCODE_DATA                                                                             0x0001
>+#define mmSDMA5_UCODE_DATA_BASE_IDX                                                                    1
>+#define mmSDMA5_VM_CNTL                                                                                0x0004
>+#define mmSDMA5_VM_CNTL_BASE_IDX                                                                       1
>+#define mmSDMA5_VM_CTX_LO                                                                              0x0005
>+#define mmSDMA5_VM_CTX_LO_BASE_IDX                                                                     1
>+#define mmSDMA5_VM_CTX_HI                                                                              0x0006
>+#define mmSDMA5_VM_CTX_HI_BASE_IDX                                                                     1
>+#define mmSDMA5_ACTIVE_FCN_ID                                                                          0x0007
>+#define mmSDMA5_ACTIVE_FCN_ID_BASE_IDX                                                                 1
>+#define mmSDMA5_VM_CTX_CNTL                                                                            0x0008
>+#define mmSDMA5_VM_CTX_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA5_VIRT_RESET_REQ                                                                         0x0009
>+#define mmSDMA5_VIRT_RESET_REQ_BASE_IDX                                                                1
>+#define mmSDMA5_VF_ENABLE                                                                              0x000a
>+#define mmSDMA5_VF_ENABLE_BASE_IDX                                                                     1
>+#define mmSDMA5_CONTEXT_REG_TYPE0                                                                      0x000b
>+#define mmSDMA5_CONTEXT_REG_TYPE0_BASE_IDX                                                             1
>+#define mmSDMA5_CONTEXT_REG_TYPE1                                                                      0x000c
>+#define mmSDMA5_CONTEXT_REG_TYPE1_BASE_IDX                                                             1
>+#define mmSDMA5_CONTEXT_REG_TYPE2                                                                      0x000d
>+#define mmSDMA5_CONTEXT_REG_TYPE2_BASE_IDX                                                             1
>+#define mmSDMA5_CONTEXT_REG_TYPE3                                                                      0x000e
>+#define mmSDMA5_CONTEXT_REG_TYPE3_BASE_IDX                                                             1
>+#define mmSDMA5_PUB_REG_TYPE0                                                                          0x000f
>+#define mmSDMA5_PUB_REG_TYPE0_BASE_IDX                                                                 1
>+#define mmSDMA5_PUB_REG_TYPE1                                                                          0x0010
>+#define mmSDMA5_PUB_REG_TYPE1_BASE_IDX                                                                 1
>+#define mmSDMA5_PUB_REG_TYPE2                                                                          0x0011
>+#define mmSDMA5_PUB_REG_TYPE2_BASE_IDX                                                                 1
>+#define mmSDMA5_PUB_REG_TYPE3                                                                          0x0012
>+#define mmSDMA5_PUB_REG_TYPE3_BASE_IDX                                                                 1
>+#define mmSDMA5_MMHUB_CNTL                                                                             0x0013
>+#define mmSDMA5_MMHUB_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA5_CONTEXT_GROUP_BOUNDARY                                                                 0x0019
>+#define mmSDMA5_CONTEXT_GROUP_BOUNDARY_BASE_IDX                                                        1
>+#define mmSDMA5_POWER_CNTL                                                                             0x001a
>+#define mmSDMA5_POWER_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA5_CLK_CTRL                                                                               0x001b
>+#define mmSDMA5_CLK_CTRL_BASE_IDX                                                                      1
>+#define mmSDMA5_CNTL                                                                                   0x001c
>+#define mmSDMA5_CNTL_BASE_IDX                                                                          1
>+#define mmSDMA5_CHICKEN_BITS                                                                           0x001d
>+#define mmSDMA5_CHICKEN_BITS_BASE_IDX                                                                  1
>+#define mmSDMA5_GB_ADDR_CONFIG                                                                         0x001e
>+#define mmSDMA5_GB_ADDR_CONFIG_BASE_IDX                                                                1
>+#define mmSDMA5_GB_ADDR_CONFIG_READ                                                                    0x001f
>+#define mmSDMA5_GB_ADDR_CONFIG_READ_BASE_IDX                                                           1
>+#define mmSDMA5_RB_RPTR_FETCH_HI                                                                       0x0020
>+#define mmSDMA5_RB_RPTR_FETCH_HI_BASE_IDX                                                              1
>+#define mmSDMA5_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0021
>+#define mmSDMA5_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      1
>+#define mmSDMA5_RB_RPTR_FETCH                                                                          0x0022
>+#define mmSDMA5_RB_RPTR_FETCH_BASE_IDX                                                                 1
>+#define mmSDMA5_IB_OFFSET_FETCH                                                                        0x0023
>+#define mmSDMA5_IB_OFFSET_FETCH_BASE_IDX                                                               1
>+#define mmSDMA5_PROGRAM                                                                                0x0024
>+#define mmSDMA5_PROGRAM_BASE_IDX                                                                       1
>+#define mmSDMA5_STATUS_REG                                                                             0x0025
>+#define mmSDMA5_STATUS_REG_BASE_IDX                                                                    1
>+#define mmSDMA5_STATUS1_REG                                                                            0x0026
>+#define mmSDMA5_STATUS1_REG_BASE_IDX                                                                   1
>+#define mmSDMA5_RD_BURST_CNTL                                                                          0x0027
>+#define mmSDMA5_RD_BURST_CNTL_BASE_IDX                                                                 1
>+#define mmSDMA5_HBM_PAGE_CONFIG                                                                        0x0028
>+#define mmSDMA5_HBM_PAGE_CONFIG_BASE_IDX                                                               1
>+#define mmSDMA5_UCODE_CHECKSUM                                                                         0x0029
>+#define mmSDMA5_UCODE_CHECKSUM_BASE_IDX                                                                1
>+#define mmSDMA5_F32_CNTL                                                                               0x002a
>+#define mmSDMA5_F32_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA5_FREEZE                                                                                 0x002b
>+#define mmSDMA5_FREEZE_BASE_IDX                                                                        1
>+#define mmSDMA5_PHASE0_QUANTUM                                                                         0x002c
>+#define mmSDMA5_PHASE0_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA5_PHASE1_QUANTUM                                                                         0x002d
>+#define mmSDMA5_PHASE1_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA5_EDC_CONFIG                                                                             0x0032
>+#define mmSDMA5_EDC_CONFIG_BASE_IDX                                                                    1
>+#define mmSDMA5_BA_THRESHOLD                                                                           0x0033
>+#define mmSDMA5_BA_THRESHOLD_BASE_IDX                                                                  1
>+#define mmSDMA5_ID                                                                                     0x0034
>+#define mmSDMA5_ID_BASE_IDX                                                                            1
>+#define mmSDMA5_VERSION                                                                                0x0035
>+#define mmSDMA5_VERSION_BASE_IDX                                                                       1
>+#define mmSDMA5_EDC_COUNTER                                                                            0x0036
>+#define mmSDMA5_EDC_COUNTER_BASE_IDX                                                                   1
>+#define mmSDMA5_EDC_COUNTER_CLEAR                                                                      0x0037
>+#define mmSDMA5_EDC_COUNTER_CLEAR_BASE_IDX                                                             1
>+#define mmSDMA5_STATUS2_REG                                                                            0x0038
>+#define mmSDMA5_STATUS2_REG_BASE_IDX                                                                   1
>+#define mmSDMA5_ATOMIC_CNTL                                                                            0x0039
>+#define mmSDMA5_ATOMIC_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA5_ATOMIC_PREOP_LO                                                                        0x003a
>+#define mmSDMA5_ATOMIC_PREOP_LO_BASE_IDX                                                               1
>+#define mmSDMA5_ATOMIC_PREOP_HI                                                                        0x003b
>+#define mmSDMA5_ATOMIC_PREOP_HI_BASE_IDX                                                               1
>+#define mmSDMA5_UTCL1_CNTL                                                                             0x003c
>+#define mmSDMA5_UTCL1_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA5_UTCL1_WATERMK                                                                          0x003d
>+#define mmSDMA5_UTCL1_WATERMK_BASE_IDX                                                                 1
>+#define mmSDMA5_UTCL1_RD_STATUS                                                                        0x003e
>+#define mmSDMA5_UTCL1_RD_STATUS_BASE_IDX                                                               1
>+#define mmSDMA5_UTCL1_WR_STATUS                                                                        0x003f
>+#define mmSDMA5_UTCL1_WR_STATUS_BASE_IDX                                                               1
>+#define mmSDMA5_UTCL1_INV0                                                                             0x0040
>+#define mmSDMA5_UTCL1_INV0_BASE_IDX                                                                    1
>+#define mmSDMA5_UTCL1_INV1                                                                             0x0041
>+#define mmSDMA5_UTCL1_INV1_BASE_IDX                                                                    1
>+#define mmSDMA5_UTCL1_INV2                                                                             0x0042
>+#define mmSDMA5_UTCL1_INV2_BASE_IDX                                                                    1
>+#define mmSDMA5_UTCL1_RD_XNACK0                                                                        0x0043
>+#define mmSDMA5_UTCL1_RD_XNACK0_BASE_IDX                                                               1
>+#define mmSDMA5_UTCL1_RD_XNACK1                                                                        0x0044
>+#define mmSDMA5_UTCL1_RD_XNACK1_BASE_IDX                                                               1
>+#define mmSDMA5_UTCL1_WR_XNACK0                                                                        0x0045
>+#define mmSDMA5_UTCL1_WR_XNACK0_BASE_IDX                                                               1
>+#define mmSDMA5_UTCL1_WR_XNACK1                                                                        0x0046
>+#define mmSDMA5_UTCL1_WR_XNACK1_BASE_IDX                                                               1
>+#define mmSDMA5_UTCL1_TIMEOUT                                                                          0x0047
>+#define mmSDMA5_UTCL1_TIMEOUT_BASE_IDX                                                                 1
>+#define mmSDMA5_UTCL1_PAGE                                                                             0x0048
>+#define mmSDMA5_UTCL1_PAGE_BASE_IDX                                                                    1
>+#define mmSDMA5_POWER_CNTL_IDLE                                                                        0x0049
>+#define mmSDMA5_POWER_CNTL_IDLE_BASE_IDX                                                               1
>+#define mmSDMA5_RELAX_ORDERING_LUT                                                                     0x004a
>+#define mmSDMA5_RELAX_ORDERING_LUT_BASE_IDX                                                            1
>+#define mmSDMA5_CHICKEN_BITS_2                                                                         0x004b
>+#define mmSDMA5_CHICKEN_BITS_2_BASE_IDX                                                                1
>+#define mmSDMA5_STATUS3_REG                                                                            0x004c
>+#define mmSDMA5_STATUS3_REG_BASE_IDX                                                                   1
>+#define mmSDMA5_PHYSICAL_ADDR_LO                                                                       0x004d
>+#define mmSDMA5_PHYSICAL_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA5_PHYSICAL_ADDR_HI                                                                       0x004e
>+#define mmSDMA5_PHYSICAL_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA5_PHASE2_QUANTUM                                                                         0x004f
>+#define mmSDMA5_PHASE2_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA5_ERROR_LOG                                                                              0x0050
>+#define mmSDMA5_ERROR_LOG_BASE_IDX                                                                     1
>+#define mmSDMA5_PUB_DUMMY_REG0                                                                         0x0051
>+#define mmSDMA5_PUB_DUMMY_REG0_BASE_IDX                                                                1
>+#define mmSDMA5_PUB_DUMMY_REG1                                                                         0x0052
>+#define mmSDMA5_PUB_DUMMY_REG1_BASE_IDX                                                                1
>+#define mmSDMA5_PUB_DUMMY_REG2                                                                         0x0053
>+#define mmSDMA5_PUB_DUMMY_REG2_BASE_IDX                                                                1
>+#define mmSDMA5_PUB_DUMMY_REG3                                                                         0x0054
>+#define mmSDMA5_PUB_DUMMY_REG3_BASE_IDX                                                                1
>+#define mmSDMA5_F32_COUNTER                                                                            0x0055
>+#define mmSDMA5_F32_COUNTER_BASE_IDX                                                                   1
>+#define mmSDMA5_UNBREAKABLE                                                                            0x0056
>+#define mmSDMA5_UNBREAKABLE_BASE_IDX                                                                   1
>+#define mmSDMA5_PERFMON_CNTL                                                                           0x0057
>+#define mmSDMA5_PERFMON_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_PERFCOUNTER0_RESULT                                                                    0x0058
>+#define mmSDMA5_PERFCOUNTER0_RESULT_BASE_IDX                                                           1
>+#define mmSDMA5_PERFCOUNTER1_RESULT                                                                    0x0059
>+#define mmSDMA5_PERFCOUNTER1_RESULT_BASE_IDX                                                           1
>+#define mmSDMA5_PERFCOUNTER_TAG_DELAY_RANGE                                                            0x005a
>+#define mmSDMA5_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX                                                   1
>+#define mmSDMA5_CRD_CNTL                                                                               0x005b
>+#define mmSDMA5_CRD_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA5_GPU_IOV_VIOLATION_LOG                                                                  0x005d
>+#define mmSDMA5_GPU_IOV_VIOLATION_LOG_BASE_IDX                                                         1
>+#define mmSDMA5_ULV_CNTL                                                                               0x005e
>+#define mmSDMA5_ULV_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA5_EA_DBIT_ADDR_DATA                                                                      0x0060
>+#define mmSDMA5_EA_DBIT_ADDR_DATA_BASE_IDX                                                             1
>+#define mmSDMA5_EA_DBIT_ADDR_INDEX                                                                     0x0061
>+#define mmSDMA5_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            1
>+#define mmSDMA5_GPU_IOV_VIOLATION_LOG2                                                                 0x0062
>+#define mmSDMA5_GPU_IOV_VIOLATION_LOG2_BASE_IDX                                                        1
>+#define mmSDMA5_GFX_RB_CNTL                                                                            0x0080
>+#define mmSDMA5_GFX_RB_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA5_GFX_RB_BASE                                                                            0x0081
>+#define mmSDMA5_GFX_RB_BASE_BASE_IDX                                                                   1
>+#define mmSDMA5_GFX_RB_BASE_HI                                                                         0x0082
>+#define mmSDMA5_GFX_RB_BASE_HI_BASE_IDX                                                                1
>+#define mmSDMA5_GFX_RB_RPTR                                                                            0x0083
>+#define mmSDMA5_GFX_RB_RPTR_BASE_IDX                                                                   1
>+#define mmSDMA5_GFX_RB_RPTR_HI                                                                         0x0084
>+#define mmSDMA5_GFX_RB_RPTR_HI_BASE_IDX                                                                1
>+#define mmSDMA5_GFX_RB_WPTR                                                                            0x0085
>+#define mmSDMA5_GFX_RB_WPTR_BASE_IDX                                                                   1
>+#define mmSDMA5_GFX_RB_WPTR_HI                                                                         0x0086
>+#define mmSDMA5_GFX_RB_WPTR_HI_BASE_IDX                                                                1
>+#define mmSDMA5_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
>+#define mmSDMA5_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         1
>+#define mmSDMA5_GFX_RB_RPTR_ADDR_HI                                                                    0x0088
>+#define mmSDMA5_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           1
>+#define mmSDMA5_GFX_RB_RPTR_ADDR_LO                                                                    0x0089
>+#define mmSDMA5_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           1
>+#define mmSDMA5_GFX_IB_CNTL                                                                            0x008a
>+#define mmSDMA5_GFX_IB_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA5_GFX_IB_RPTR                                                                            0x008b
>+#define mmSDMA5_GFX_IB_RPTR_BASE_IDX                                                                   1
>+#define mmSDMA5_GFX_IB_OFFSET                                                                          0x008c
>+#define mmSDMA5_GFX_IB_OFFSET_BASE_IDX                                                                 1
>+#define mmSDMA5_GFX_IB_BASE_LO                                                                         0x008d
>+#define mmSDMA5_GFX_IB_BASE_LO_BASE_IDX                                                                1
>+#define mmSDMA5_GFX_IB_BASE_HI                                                                         0x008e
>+#define mmSDMA5_GFX_IB_BASE_HI_BASE_IDX                                                                1
>+#define mmSDMA5_GFX_IB_SIZE                                                                            0x008f
>+#define mmSDMA5_GFX_IB_SIZE_BASE_IDX                                                                   1
>+#define mmSDMA5_GFX_SKIP_CNTL                                                                          0x0090
>+#define mmSDMA5_GFX_SKIP_CNTL_BASE_IDX                                                                 1
>+#define mmSDMA5_GFX_CONTEXT_STATUS                                                                     0x0091
>+#define mmSDMA5_GFX_CONTEXT_STATUS_BASE_IDX                                                            1
>+#define mmSDMA5_GFX_DOORBELL                                                                           0x0092
>+#define mmSDMA5_GFX_DOORBELL_BASE_IDX                                                                  1
>+#define mmSDMA5_GFX_CONTEXT_CNTL                                                                       0x0093
>+#define mmSDMA5_GFX_CONTEXT_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_GFX_STATUS                                                                             0x00a8
>+#define mmSDMA5_GFX_STATUS_BASE_IDX                                                                    1
>+#define mmSDMA5_GFX_DOORBELL_LOG                                                                       0x00a9
>+#define mmSDMA5_GFX_DOORBELL_LOG_BASE_IDX                                                              1
>+#define mmSDMA5_GFX_WATERMARK                                                                          0x00aa
>+#define mmSDMA5_GFX_WATERMARK_BASE_IDX                                                                 1
>+#define mmSDMA5_GFX_DOORBELL_OFFSET                                                                    0x00ab
>+#define mmSDMA5_GFX_DOORBELL_OFFSET_BASE_IDX                                                           1
>+#define mmSDMA5_GFX_CSA_ADDR_LO                                                                        0x00ac
>+#define mmSDMA5_GFX_CSA_ADDR_LO_BASE_IDX                                                               1
>+#define mmSDMA5_GFX_CSA_ADDR_HI                                                                        0x00ad
>+#define mmSDMA5_GFX_CSA_ADDR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_GFX_IB_SUB_REMAIN                                                                      0x00af
>+#define mmSDMA5_GFX_IB_SUB_REMAIN_BASE_IDX                                                             1
>+#define mmSDMA5_GFX_PREEMPT                                                                            0x00b0
>+#define mmSDMA5_GFX_PREEMPT_BASE_IDX                                                                   1
>+#define mmSDMA5_GFX_DUMMY_REG                                                                          0x00b1
>+#define mmSDMA5_GFX_DUMMY_REG_BASE_IDX                                                                 1
>+#define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x00b2
>+#define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      1
>+#define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x00b3
>+#define mmSDMA5_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      1
>+#define mmSDMA5_GFX_RB_AQL_CNTL                                                                        0x00b4
>+#define mmSDMA5_GFX_RB_AQL_CNTL_BASE_IDX                                                               1
>+#define mmSDMA5_GFX_MINOR_PTR_UPDATE                                                                   0x00b5
>+#define mmSDMA5_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          1
>+#define mmSDMA5_GFX_MIDCMD_DATA0                                                                       0x00c0
>+#define mmSDMA5_GFX_MIDCMD_DATA0_BASE_IDX                                                              1
>+#define mmSDMA5_GFX_MIDCMD_DATA1                                                                       0x00c1
>+#define mmSDMA5_GFX_MIDCMD_DATA1_BASE_IDX                                                              1
>+#define mmSDMA5_GFX_MIDCMD_DATA2                                                                       0x00c2
>+#define mmSDMA5_GFX_MIDCMD_DATA2_BASE_IDX                                                              1
>+#define mmSDMA5_GFX_MIDCMD_DATA3                                                                       0x00c3
>+#define mmSDMA5_GFX_MIDCMD_DATA3_BASE_IDX                                                              1
>+#define mmSDMA5_GFX_MIDCMD_DATA4                                                                       0x00c4
>+#define mmSDMA5_GFX_MIDCMD_DATA4_BASE_IDX                                                              1
>+#define mmSDMA5_GFX_MIDCMD_DATA5                                                                       0x00c5
>+#define mmSDMA5_GFX_MIDCMD_DATA5_BASE_IDX                                                              1
>+#define mmSDMA5_GFX_MIDCMD_DATA6                                                                       0x00c6
>+#define mmSDMA5_GFX_MIDCMD_DATA6_BASE_IDX                                                              1
>+#define mmSDMA5_GFX_MIDCMD_DATA7                                                                       0x00c7
>+#define mmSDMA5_GFX_MIDCMD_DATA7_BASE_IDX                                                              1
>+#define mmSDMA5_GFX_MIDCMD_DATA8                                                                       0x00c8
>+#define mmSDMA5_GFX_MIDCMD_DATA8_BASE_IDX                                                              1
>+#define mmSDMA5_GFX_MIDCMD_CNTL                                                                        0x00c9
>+#define mmSDMA5_GFX_MIDCMD_CNTL_BASE_IDX                                                               1
>+#define mmSDMA5_PAGE_RB_CNTL                                                                           0x00d8
>+#define mmSDMA5_PAGE_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_PAGE_RB_BASE                                                                           0x00d9
>+#define mmSDMA5_PAGE_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA5_PAGE_RB_BASE_HI                                                                        0x00da
>+#define mmSDMA5_PAGE_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_PAGE_RB_RPTR                                                                           0x00db
>+#define mmSDMA5_PAGE_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_PAGE_RB_RPTR_HI                                                                        0x00dc
>+#define mmSDMA5_PAGE_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_PAGE_RB_WPTR                                                                           0x00dd
>+#define mmSDMA5_PAGE_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_PAGE_RB_WPTR_HI                                                                        0x00de
>+#define mmSDMA5_PAGE_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_PAGE_RB_WPTR_POLL_CNTL                                                                 0x00df
>+#define mmSDMA5_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA5_PAGE_RB_RPTR_ADDR_HI                                                                   0x00e0
>+#define mmSDMA5_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA5_PAGE_RB_RPTR_ADDR_LO                                                                   0x00e1
>+#define mmSDMA5_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA5_PAGE_IB_CNTL                                                                           0x00e2
>+#define mmSDMA5_PAGE_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_PAGE_IB_RPTR                                                                           0x00e3
>+#define mmSDMA5_PAGE_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_PAGE_IB_OFFSET                                                                         0x00e4
>+#define mmSDMA5_PAGE_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA5_PAGE_IB_BASE_LO                                                                        0x00e5
>+#define mmSDMA5_PAGE_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA5_PAGE_IB_BASE_HI                                                                        0x00e6
>+#define mmSDMA5_PAGE_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_PAGE_IB_SIZE                                                                           0x00e7
>+#define mmSDMA5_PAGE_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA5_PAGE_SKIP_CNTL                                                                         0x00e8
>+#define mmSDMA5_PAGE_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA5_PAGE_CONTEXT_STATUS                                                                    0x00e9
>+#define mmSDMA5_PAGE_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA5_PAGE_DOORBELL                                                                          0x00ea
>+#define mmSDMA5_PAGE_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA5_PAGE_STATUS                                                                            0x0100
>+#define mmSDMA5_PAGE_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA5_PAGE_DOORBELL_LOG                                                                      0x0101
>+#define mmSDMA5_PAGE_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA5_PAGE_WATERMARK                                                                         0x0102
>+#define mmSDMA5_PAGE_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA5_PAGE_DOORBELL_OFFSET                                                                   0x0103
>+#define mmSDMA5_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA5_PAGE_CSA_ADDR_LO                                                                       0x0104
>+#define mmSDMA5_PAGE_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA5_PAGE_CSA_ADDR_HI                                                                       0x0105
>+#define mmSDMA5_PAGE_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA5_PAGE_IB_SUB_REMAIN                                                                     0x0107
>+#define mmSDMA5_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA5_PAGE_PREEMPT                                                                           0x0108
>+#define mmSDMA5_PAGE_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA5_PAGE_DUMMY_REG                                                                         0x0109
>+#define mmSDMA5_PAGE_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x010a
>+#define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x010b
>+#define mmSDMA5_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA5_PAGE_RB_AQL_CNTL                                                                       0x010c
>+#define mmSDMA5_PAGE_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_PAGE_MINOR_PTR_UPDATE                                                                  0x010d
>+#define mmSDMA5_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA5_PAGE_MIDCMD_DATA0                                                                      0x0118
>+#define mmSDMA5_PAGE_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA5_PAGE_MIDCMD_DATA1                                                                      0x0119
>+#define mmSDMA5_PAGE_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA5_PAGE_MIDCMD_DATA2                                                                      0x011a
>+#define mmSDMA5_PAGE_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA5_PAGE_MIDCMD_DATA3                                                                      0x011b
>+#define mmSDMA5_PAGE_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA5_PAGE_MIDCMD_DATA4                                                                      0x011c
>+#define mmSDMA5_PAGE_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA5_PAGE_MIDCMD_DATA5                                                                      0x011d
>+#define mmSDMA5_PAGE_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA5_PAGE_MIDCMD_DATA6                                                                      0x011e
>+#define mmSDMA5_PAGE_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA5_PAGE_MIDCMD_DATA7                                                                      0x011f
>+#define mmSDMA5_PAGE_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA5_PAGE_MIDCMD_DATA8                                                                      0x0120
>+#define mmSDMA5_PAGE_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA5_PAGE_MIDCMD_CNTL                                                                       0x0121
>+#define mmSDMA5_PAGE_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC0_RB_CNTL                                                                           0x0130
>+#define mmSDMA5_RLC0_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC0_RB_BASE                                                                           0x0131
>+#define mmSDMA5_RLC0_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC0_RB_BASE_HI                                                                        0x0132
>+#define mmSDMA5_RLC0_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC0_RB_RPTR                                                                           0x0133
>+#define mmSDMA5_RLC0_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC0_RB_RPTR_HI                                                                        0x0134
>+#define mmSDMA5_RLC0_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC0_RB_WPTR                                                                           0x0135
>+#define mmSDMA5_RLC0_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC0_RB_WPTR_HI                                                                        0x0136
>+#define mmSDMA5_RLC0_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0137
>+#define mmSDMA5_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA5_RLC0_RB_RPTR_ADDR_HI                                                                   0x0138
>+#define mmSDMA5_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA5_RLC0_RB_RPTR_ADDR_LO                                                                   0x0139
>+#define mmSDMA5_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA5_RLC0_IB_CNTL                                                                           0x013a
>+#define mmSDMA5_RLC0_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC0_IB_RPTR                                                                           0x013b
>+#define mmSDMA5_RLC0_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC0_IB_OFFSET                                                                         0x013c
>+#define mmSDMA5_RLC0_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA5_RLC0_IB_BASE_LO                                                                        0x013d
>+#define mmSDMA5_RLC0_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA5_RLC0_IB_BASE_HI                                                                        0x013e
>+#define mmSDMA5_RLC0_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC0_IB_SIZE                                                                           0x013f
>+#define mmSDMA5_RLC0_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC0_SKIP_CNTL                                                                         0x0140
>+#define mmSDMA5_RLC0_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA5_RLC0_CONTEXT_STATUS                                                                    0x0141
>+#define mmSDMA5_RLC0_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA5_RLC0_DOORBELL                                                                          0x0142
>+#define mmSDMA5_RLC0_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA5_RLC0_STATUS                                                                            0x0158
>+#define mmSDMA5_RLC0_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA5_RLC0_DOORBELL_LOG                                                                      0x0159
>+#define mmSDMA5_RLC0_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA5_RLC0_WATERMARK                                                                         0x015a
>+#define mmSDMA5_RLC0_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA5_RLC0_DOORBELL_OFFSET                                                                   0x015b
>+#define mmSDMA5_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA5_RLC0_CSA_ADDR_LO                                                                       0x015c
>+#define mmSDMA5_RLC0_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA5_RLC0_CSA_ADDR_HI                                                                       0x015d
>+#define mmSDMA5_RLC0_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA5_RLC0_IB_SUB_REMAIN                                                                     0x015f
>+#define mmSDMA5_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA5_RLC0_PREEMPT                                                                           0x0160
>+#define mmSDMA5_RLC0_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC0_DUMMY_REG                                                                         0x0161
>+#define mmSDMA5_RLC0_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0162
>+#define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0163
>+#define mmSDMA5_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA5_RLC0_RB_AQL_CNTL                                                                       0x0164
>+#define mmSDMA5_RLC0_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC0_MINOR_PTR_UPDATE                                                                  0x0165
>+#define mmSDMA5_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA5_RLC0_MIDCMD_DATA0                                                                      0x0170
>+#define mmSDMA5_RLC0_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA5_RLC0_MIDCMD_DATA1                                                                      0x0171
>+#define mmSDMA5_RLC0_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA5_RLC0_MIDCMD_DATA2                                                                      0x0172
>+#define mmSDMA5_RLC0_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA5_RLC0_MIDCMD_DATA3                                                                      0x0173
>+#define mmSDMA5_RLC0_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA5_RLC0_MIDCMD_DATA4                                                                      0x0174
>+#define mmSDMA5_RLC0_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA5_RLC0_MIDCMD_DATA5                                                                      0x0175
>+#define mmSDMA5_RLC0_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA5_RLC0_MIDCMD_DATA6                                                                      0x0176
>+#define mmSDMA5_RLC0_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA5_RLC0_MIDCMD_DATA7                                                                      0x0177
>+#define mmSDMA5_RLC0_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA5_RLC0_MIDCMD_DATA8                                                                      0x0178
>+#define mmSDMA5_RLC0_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA5_RLC0_MIDCMD_CNTL                                                                       0x0179
>+#define mmSDMA5_RLC0_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC1_RB_CNTL                                                                           0x0188
>+#define mmSDMA5_RLC1_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC1_RB_BASE                                                                           0x0189
>+#define mmSDMA5_RLC1_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC1_RB_BASE_HI                                                                        0x018a
>+#define mmSDMA5_RLC1_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC1_RB_RPTR                                                                           0x018b
>+#define mmSDMA5_RLC1_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC1_RB_RPTR_HI                                                                        0x018c
>+#define mmSDMA5_RLC1_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC1_RB_WPTR                                                                           0x018d
>+#define mmSDMA5_RLC1_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC1_RB_WPTR_HI                                                                        0x018e
>+#define mmSDMA5_RLC1_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC1_RB_WPTR_POLL_CNTL                                                                 0x018f
>+#define mmSDMA5_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA5_RLC1_RB_RPTR_ADDR_HI                                                                   0x0190
>+#define mmSDMA5_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA5_RLC1_RB_RPTR_ADDR_LO                                                                   0x0191
>+#define mmSDMA5_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA5_RLC1_IB_CNTL                                                                           0x0192
>+#define mmSDMA5_RLC1_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC1_IB_RPTR                                                                           0x0193
>+#define mmSDMA5_RLC1_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC1_IB_OFFSET                                                                         0x0194
>+#define mmSDMA5_RLC1_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA5_RLC1_IB_BASE_LO                                                                        0x0195
>+#define mmSDMA5_RLC1_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA5_RLC1_IB_BASE_HI                                                                        0x0196
>+#define mmSDMA5_RLC1_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC1_IB_SIZE                                                                           0x0197
>+#define mmSDMA5_RLC1_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC1_SKIP_CNTL                                                                         0x0198
>+#define mmSDMA5_RLC1_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA5_RLC1_CONTEXT_STATUS                                                                    0x0199
>+#define mmSDMA5_RLC1_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA5_RLC1_DOORBELL                                                                          0x019a
>+#define mmSDMA5_RLC1_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA5_RLC1_STATUS                                                                            0x01b0
>+#define mmSDMA5_RLC1_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA5_RLC1_DOORBELL_LOG                                                                      0x01b1
>+#define mmSDMA5_RLC1_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA5_RLC1_WATERMARK                                                                         0x01b2
>+#define mmSDMA5_RLC1_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA5_RLC1_DOORBELL_OFFSET                                                                   0x01b3
>+#define mmSDMA5_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA5_RLC1_CSA_ADDR_LO                                                                       0x01b4
>+#define mmSDMA5_RLC1_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA5_RLC1_CSA_ADDR_HI                                                                       0x01b5
>+#define mmSDMA5_RLC1_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA5_RLC1_IB_SUB_REMAIN                                                                     0x01b7
>+#define mmSDMA5_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA5_RLC1_PREEMPT                                                                           0x01b8
>+#define mmSDMA5_RLC1_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC1_DUMMY_REG                                                                         0x01b9
>+#define mmSDMA5_RLC1_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x01ba
>+#define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x01bb
>+#define mmSDMA5_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA5_RLC1_RB_AQL_CNTL                                                                       0x01bc
>+#define mmSDMA5_RLC1_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC1_MINOR_PTR_UPDATE                                                                  0x01bd
>+#define mmSDMA5_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA5_RLC1_MIDCMD_DATA0                                                                      0x01c8
>+#define mmSDMA5_RLC1_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA5_RLC1_MIDCMD_DATA1                                                                      0x01c9
>+#define mmSDMA5_RLC1_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA5_RLC1_MIDCMD_DATA2                                                                      0x01ca
>+#define mmSDMA5_RLC1_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA5_RLC1_MIDCMD_DATA3                                                                      0x01cb
>+#define mmSDMA5_RLC1_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA5_RLC1_MIDCMD_DATA4                                                                      0x01cc
>+#define mmSDMA5_RLC1_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA5_RLC1_MIDCMD_DATA5                                                                      0x01cd
>+#define mmSDMA5_RLC1_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA5_RLC1_MIDCMD_DATA6                                                                      0x01ce
>+#define mmSDMA5_RLC1_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA5_RLC1_MIDCMD_DATA7                                                                      0x01cf
>+#define mmSDMA5_RLC1_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA5_RLC1_MIDCMD_DATA8                                                                      0x01d0
>+#define mmSDMA5_RLC1_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA5_RLC1_MIDCMD_CNTL                                                                       0x01d1
>+#define mmSDMA5_RLC1_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC2_RB_CNTL                                                                           0x01e0
>+#define mmSDMA5_RLC2_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC2_RB_BASE                                                                           0x01e1
>+#define mmSDMA5_RLC2_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC2_RB_BASE_HI                                                                        0x01e2
>+#define mmSDMA5_RLC2_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC2_RB_RPTR                                                                           0x01e3
>+#define mmSDMA5_RLC2_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC2_RB_RPTR_HI                                                                        0x01e4
>+#define mmSDMA5_RLC2_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC2_RB_WPTR                                                                           0x01e5
>+#define mmSDMA5_RLC2_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC2_RB_WPTR_HI                                                                        0x01e6
>+#define mmSDMA5_RLC2_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC2_RB_WPTR_POLL_CNTL                                                                 0x01e7
>+#define mmSDMA5_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA5_RLC2_RB_RPTR_ADDR_HI                                                                   0x01e8
>+#define mmSDMA5_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA5_RLC2_RB_RPTR_ADDR_LO                                                                   0x01e9
>+#define mmSDMA5_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA5_RLC2_IB_CNTL                                                                           0x01ea
>+#define mmSDMA5_RLC2_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC2_IB_RPTR                                                                           0x01eb
>+#define mmSDMA5_RLC2_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC2_IB_OFFSET                                                                         0x01ec
>+#define mmSDMA5_RLC2_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA5_RLC2_IB_BASE_LO                                                                        0x01ed
>+#define mmSDMA5_RLC2_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA5_RLC2_IB_BASE_HI                                                                        0x01ee
>+#define mmSDMA5_RLC2_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC2_IB_SIZE                                                                           0x01ef
>+#define mmSDMA5_RLC2_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC2_SKIP_CNTL                                                                         0x01f0
>+#define mmSDMA5_RLC2_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA5_RLC2_CONTEXT_STATUS                                                                    0x01f1
>+#define mmSDMA5_RLC2_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA5_RLC2_DOORBELL                                                                          0x01f2
>+#define mmSDMA5_RLC2_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA5_RLC2_STATUS                                                                            0x0208
>+#define mmSDMA5_RLC2_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA5_RLC2_DOORBELL_LOG                                                                      0x0209
>+#define mmSDMA5_RLC2_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA5_RLC2_WATERMARK                                                                         0x020a
>+#define mmSDMA5_RLC2_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA5_RLC2_DOORBELL_OFFSET                                                                   0x020b
>+#define mmSDMA5_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA5_RLC2_CSA_ADDR_LO                                                                       0x020c
>+#define mmSDMA5_RLC2_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA5_RLC2_CSA_ADDR_HI                                                                       0x020d
>+#define mmSDMA5_RLC2_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA5_RLC2_IB_SUB_REMAIN                                                                     0x020f
>+#define mmSDMA5_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA5_RLC2_PREEMPT                                                                           0x0210
>+#define mmSDMA5_RLC2_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC2_DUMMY_REG                                                                         0x0211
>+#define mmSDMA5_RLC2_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0212
>+#define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0213
>+#define mmSDMA5_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA5_RLC2_RB_AQL_CNTL                                                                       0x0214
>+#define mmSDMA5_RLC2_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC2_MINOR_PTR_UPDATE                                                                  0x0215
>+#define mmSDMA5_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA5_RLC2_MIDCMD_DATA0                                                                      0x0220
>+#define mmSDMA5_RLC2_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA5_RLC2_MIDCMD_DATA1                                                                      0x0221
>+#define mmSDMA5_RLC2_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA5_RLC2_MIDCMD_DATA2                                                                      0x0222
>+#define mmSDMA5_RLC2_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA5_RLC2_MIDCMD_DATA3                                                                      0x0223
>+#define mmSDMA5_RLC2_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA5_RLC2_MIDCMD_DATA4                                                                      0x0224
>+#define mmSDMA5_RLC2_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA5_RLC2_MIDCMD_DATA5                                                                      0x0225
>+#define mmSDMA5_RLC2_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA5_RLC2_MIDCMD_DATA6                                                                      0x0226
>+#define mmSDMA5_RLC2_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA5_RLC2_MIDCMD_DATA7                                                                      0x0227
>+#define mmSDMA5_RLC2_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA5_RLC2_MIDCMD_DATA8                                                                      0x0228
>+#define mmSDMA5_RLC2_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA5_RLC2_MIDCMD_CNTL                                                                       0x0229
>+#define mmSDMA5_RLC2_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC3_RB_CNTL                                                                           0x0238
>+#define mmSDMA5_RLC3_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC3_RB_BASE                                                                           0x0239
>+#define mmSDMA5_RLC3_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC3_RB_BASE_HI                                                                        0x023a
>+#define mmSDMA5_RLC3_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC3_RB_RPTR                                                                           0x023b
>+#define mmSDMA5_RLC3_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC3_RB_RPTR_HI                                                                        0x023c
>+#define mmSDMA5_RLC3_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC3_RB_WPTR                                                                           0x023d
>+#define mmSDMA5_RLC3_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC3_RB_WPTR_HI                                                                        0x023e
>+#define mmSDMA5_RLC3_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC3_RB_WPTR_POLL_CNTL                                                                 0x023f
>+#define mmSDMA5_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA5_RLC3_RB_RPTR_ADDR_HI                                                                   0x0240
>+#define mmSDMA5_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA5_RLC3_RB_RPTR_ADDR_LO                                                                   0x0241
>+#define mmSDMA5_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA5_RLC3_IB_CNTL                                                                           0x0242
>+#define mmSDMA5_RLC3_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC3_IB_RPTR                                                                           0x0243
>+#define mmSDMA5_RLC3_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC3_IB_OFFSET                                                                         0x0244
>+#define mmSDMA5_RLC3_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA5_RLC3_IB_BASE_LO                                                                        0x0245
>+#define mmSDMA5_RLC3_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA5_RLC3_IB_BASE_HI                                                                        0x0246
>+#define mmSDMA5_RLC3_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC3_IB_SIZE                                                                           0x0247
>+#define mmSDMA5_RLC3_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC3_SKIP_CNTL                                                                         0x0248
>+#define mmSDMA5_RLC3_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA5_RLC3_CONTEXT_STATUS                                                                    0x0249
>+#define mmSDMA5_RLC3_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA5_RLC3_DOORBELL                                                                          0x024a
>+#define mmSDMA5_RLC3_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA5_RLC3_STATUS                                                                            0x0260
>+#define mmSDMA5_RLC3_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA5_RLC3_DOORBELL_LOG                                                                      0x0261
>+#define mmSDMA5_RLC3_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA5_RLC3_WATERMARK                                                                         0x0262
>+#define mmSDMA5_RLC3_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA5_RLC3_DOORBELL_OFFSET                                                                   0x0263
>+#define mmSDMA5_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA5_RLC3_CSA_ADDR_LO                                                                       0x0264
>+#define mmSDMA5_RLC3_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA5_RLC3_CSA_ADDR_HI                                                                       0x0265
>+#define mmSDMA5_RLC3_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA5_RLC3_IB_SUB_REMAIN                                                                     0x0267
>+#define mmSDMA5_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA5_RLC3_PREEMPT                                                                           0x0268
>+#define mmSDMA5_RLC3_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC3_DUMMY_REG                                                                         0x0269
>+#define mmSDMA5_RLC3_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x026a
>+#define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x026b
>+#define mmSDMA5_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA5_RLC3_RB_AQL_CNTL                                                                       0x026c
>+#define mmSDMA5_RLC3_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC3_MINOR_PTR_UPDATE                                                                  0x026d
>+#define mmSDMA5_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA5_RLC3_MIDCMD_DATA0                                                                      0x0278
>+#define mmSDMA5_RLC3_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA5_RLC3_MIDCMD_DATA1                                                                      0x0279
>+#define mmSDMA5_RLC3_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA5_RLC3_MIDCMD_DATA2                                                                      0x027a
>+#define mmSDMA5_RLC3_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA5_RLC3_MIDCMD_DATA3                                                                      0x027b
>+#define mmSDMA5_RLC3_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA5_RLC3_MIDCMD_DATA4                                                                      0x027c
>+#define mmSDMA5_RLC3_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA5_RLC3_MIDCMD_DATA5                                                                      0x027d
>+#define mmSDMA5_RLC3_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA5_RLC3_MIDCMD_DATA6                                                                      0x027e
>+#define mmSDMA5_RLC3_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA5_RLC3_MIDCMD_DATA7                                                                      0x027f
>+#define mmSDMA5_RLC3_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA5_RLC3_MIDCMD_DATA8                                                                      0x0280
>+#define mmSDMA5_RLC3_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA5_RLC3_MIDCMD_CNTL                                                                       0x0281
>+#define mmSDMA5_RLC3_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC4_RB_CNTL                                                                           0x0290
>+#define mmSDMA5_RLC4_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC4_RB_BASE                                                                           0x0291
>+#define mmSDMA5_RLC4_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC4_RB_BASE_HI                                                                        0x0292
>+#define mmSDMA5_RLC4_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC4_RB_RPTR                                                                           0x0293
>+#define mmSDMA5_RLC4_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC4_RB_RPTR_HI                                                                        0x0294
>+#define mmSDMA5_RLC4_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC4_RB_WPTR                                                                           0x0295
>+#define mmSDMA5_RLC4_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC4_RB_WPTR_HI                                                                        0x0296
>+#define mmSDMA5_RLC4_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC4_RB_WPTR_POLL_CNTL                                                                 0x0297
>+#define mmSDMA5_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA5_RLC4_RB_RPTR_ADDR_HI                                                                   0x0298
>+#define mmSDMA5_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA5_RLC4_RB_RPTR_ADDR_LO                                                                   0x0299
>+#define mmSDMA5_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA5_RLC4_IB_CNTL                                                                           0x029a
>+#define mmSDMA5_RLC4_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC4_IB_RPTR                                                                           0x029b
>+#define mmSDMA5_RLC4_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC4_IB_OFFSET                                                                         0x029c
>+#define mmSDMA5_RLC4_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA5_RLC4_IB_BASE_LO                                                                        0x029d
>+#define mmSDMA5_RLC4_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA5_RLC4_IB_BASE_HI                                                                        0x029e
>+#define mmSDMA5_RLC4_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC4_IB_SIZE                                                                           0x029f
>+#define mmSDMA5_RLC4_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC4_SKIP_CNTL                                                                         0x02a0
>+#define mmSDMA5_RLC4_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA5_RLC4_CONTEXT_STATUS                                                                    0x02a1
>+#define mmSDMA5_RLC4_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA5_RLC4_DOORBELL                                                                          0x02a2
>+#define mmSDMA5_RLC4_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA5_RLC4_STATUS                                                                            0x02b8
>+#define mmSDMA5_RLC4_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA5_RLC4_DOORBELL_LOG                                                                      0x02b9
>+#define mmSDMA5_RLC4_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA5_RLC4_WATERMARK                                                                         0x02ba
>+#define mmSDMA5_RLC4_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA5_RLC4_DOORBELL_OFFSET                                                                   0x02bb
>+#define mmSDMA5_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA5_RLC4_CSA_ADDR_LO                                                                       0x02bc
>+#define mmSDMA5_RLC4_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA5_RLC4_CSA_ADDR_HI                                                                       0x02bd
>+#define mmSDMA5_RLC4_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA5_RLC4_IB_SUB_REMAIN                                                                     0x02bf
>+#define mmSDMA5_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA5_RLC4_PREEMPT                                                                           0x02c0
>+#define mmSDMA5_RLC4_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC4_DUMMY_REG                                                                         0x02c1
>+#define mmSDMA5_RLC4_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x02c2
>+#define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x02c3
>+#define mmSDMA5_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA5_RLC4_RB_AQL_CNTL                                                                       0x02c4
>+#define mmSDMA5_RLC4_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC4_MINOR_PTR_UPDATE                                                                  0x02c5
>+#define mmSDMA5_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA5_RLC4_MIDCMD_DATA0                                                                      0x02d0
>+#define mmSDMA5_RLC4_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA5_RLC4_MIDCMD_DATA1                                                                      0x02d1
>+#define mmSDMA5_RLC4_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA5_RLC4_MIDCMD_DATA2                                                                      0x02d2
>+#define mmSDMA5_RLC4_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA5_RLC4_MIDCMD_DATA3                                                                      0x02d3
>+#define mmSDMA5_RLC4_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA5_RLC4_MIDCMD_DATA4                                                                      0x02d4
>+#define mmSDMA5_RLC4_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA5_RLC4_MIDCMD_DATA5                                                                      0x02d5
>+#define mmSDMA5_RLC4_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA5_RLC4_MIDCMD_DATA6                                                                      0x02d6
>+#define mmSDMA5_RLC4_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA5_RLC4_MIDCMD_DATA7                                                                      0x02d7
>+#define mmSDMA5_RLC4_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA5_RLC4_MIDCMD_DATA8                                                                      0x02d8
>+#define mmSDMA5_RLC4_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA5_RLC4_MIDCMD_CNTL                                                                       0x02d9
>+#define mmSDMA5_RLC4_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC5_RB_CNTL                                                                           0x02e8
>+#define mmSDMA5_RLC5_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC5_RB_BASE                                                                           0x02e9
>+#define mmSDMA5_RLC5_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC5_RB_BASE_HI                                                                        0x02ea
>+#define mmSDMA5_RLC5_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC5_RB_RPTR                                                                           0x02eb
>+#define mmSDMA5_RLC5_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC5_RB_RPTR_HI                                                                        0x02ec
>+#define mmSDMA5_RLC5_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC5_RB_WPTR                                                                           0x02ed
>+#define mmSDMA5_RLC5_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC5_RB_WPTR_HI                                                                        0x02ee
>+#define mmSDMA5_RLC5_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC5_RB_WPTR_POLL_CNTL                                                                 0x02ef
>+#define mmSDMA5_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA5_RLC5_RB_RPTR_ADDR_HI                                                                   0x02f0
>+#define mmSDMA5_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA5_RLC5_RB_RPTR_ADDR_LO                                                                   0x02f1
>+#define mmSDMA5_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA5_RLC5_IB_CNTL                                                                           0x02f2
>+#define mmSDMA5_RLC5_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC5_IB_RPTR                                                                           0x02f3
>+#define mmSDMA5_RLC5_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC5_IB_OFFSET                                                                         0x02f4
>+#define mmSDMA5_RLC5_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA5_RLC5_IB_BASE_LO                                                                        0x02f5
>+#define mmSDMA5_RLC5_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA5_RLC5_IB_BASE_HI                                                                        0x02f6
>+#define mmSDMA5_RLC5_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC5_IB_SIZE                                                                           0x02f7
>+#define mmSDMA5_RLC5_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC5_SKIP_CNTL                                                                         0x02f8
>+#define mmSDMA5_RLC5_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA5_RLC5_CONTEXT_STATUS                                                                    0x02f9
>+#define mmSDMA5_RLC5_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA5_RLC5_DOORBELL                                                                          0x02fa
>+#define mmSDMA5_RLC5_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA5_RLC5_STATUS                                                                            0x0310
>+#define mmSDMA5_RLC5_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA5_RLC5_DOORBELL_LOG                                                                      0x0311
>+#define mmSDMA5_RLC5_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA5_RLC5_WATERMARK                                                                         0x0312
>+#define mmSDMA5_RLC5_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA5_RLC5_DOORBELL_OFFSET                                                                   0x0313
>+#define mmSDMA5_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA5_RLC5_CSA_ADDR_LO                                                                       0x0314
>+#define mmSDMA5_RLC5_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA5_RLC5_CSA_ADDR_HI                                                                       0x0315
>+#define mmSDMA5_RLC5_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA5_RLC5_IB_SUB_REMAIN                                                                     0x0317
>+#define mmSDMA5_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA5_RLC5_PREEMPT                                                                           0x0318
>+#define mmSDMA5_RLC5_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC5_DUMMY_REG                                                                         0x0319
>+#define mmSDMA5_RLC5_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x031a
>+#define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x031b
>+#define mmSDMA5_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA5_RLC5_RB_AQL_CNTL                                                                       0x031c
>+#define mmSDMA5_RLC5_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC5_MINOR_PTR_UPDATE                                                                  0x031d
>+#define mmSDMA5_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA5_RLC5_MIDCMD_DATA0                                                                      0x0328
>+#define mmSDMA5_RLC5_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA5_RLC5_MIDCMD_DATA1                                                                      0x0329
>+#define mmSDMA5_RLC5_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA5_RLC5_MIDCMD_DATA2                                                                      0x032a
>+#define mmSDMA5_RLC5_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA5_RLC5_MIDCMD_DATA3                                                                      0x032b
>+#define mmSDMA5_RLC5_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA5_RLC5_MIDCMD_DATA4                                                                      0x032c
>+#define mmSDMA5_RLC5_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA5_RLC5_MIDCMD_DATA5                                                                      0x032d
>+#define mmSDMA5_RLC5_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA5_RLC5_MIDCMD_DATA6                                                                      0x032e
>+#define mmSDMA5_RLC5_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA5_RLC5_MIDCMD_DATA7                                                                      0x032f
>+#define mmSDMA5_RLC5_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA5_RLC5_MIDCMD_DATA8                                                                      0x0330
>+#define mmSDMA5_RLC5_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA5_RLC5_MIDCMD_CNTL                                                                       0x0331
>+#define mmSDMA5_RLC5_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC6_RB_CNTL                                                                           0x0340
>+#define mmSDMA5_RLC6_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC6_RB_BASE                                                                           0x0341
>+#define mmSDMA5_RLC6_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC6_RB_BASE_HI                                                                        0x0342
>+#define mmSDMA5_RLC6_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC6_RB_RPTR                                                                           0x0343
>+#define mmSDMA5_RLC6_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC6_RB_RPTR_HI                                                                        0x0344
>+#define mmSDMA5_RLC6_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC6_RB_WPTR                                                                           0x0345
>+#define mmSDMA5_RLC6_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC6_RB_WPTR_HI                                                                        0x0346
>+#define mmSDMA5_RLC6_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0347
>+#define mmSDMA5_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA5_RLC6_RB_RPTR_ADDR_HI                                                                   0x0348
>+#define mmSDMA5_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA5_RLC6_RB_RPTR_ADDR_LO                                                                   0x0349
>+#define mmSDMA5_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA5_RLC6_IB_CNTL                                                                           0x034a
>+#define mmSDMA5_RLC6_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC6_IB_RPTR                                                                           0x034b
>+#define mmSDMA5_RLC6_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC6_IB_OFFSET                                                                         0x034c
>+#define mmSDMA5_RLC6_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA5_RLC6_IB_BASE_LO                                                                        0x034d
>+#define mmSDMA5_RLC6_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA5_RLC6_IB_BASE_HI                                                                        0x034e
>+#define mmSDMA5_RLC6_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC6_IB_SIZE                                                                           0x034f
>+#define mmSDMA5_RLC6_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC6_SKIP_CNTL                                                                         0x0350
>+#define mmSDMA5_RLC6_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA5_RLC6_CONTEXT_STATUS                                                                    0x0351
>+#define mmSDMA5_RLC6_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA5_RLC6_DOORBELL                                                                          0x0352
>+#define mmSDMA5_RLC6_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA5_RLC6_STATUS                                                                            0x0368
>+#define mmSDMA5_RLC6_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA5_RLC6_DOORBELL_LOG                                                                      0x0369
>+#define mmSDMA5_RLC6_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA5_RLC6_WATERMARK                                                                         0x036a
>+#define mmSDMA5_RLC6_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA5_RLC6_DOORBELL_OFFSET                                                                   0x036b
>+#define mmSDMA5_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA5_RLC6_CSA_ADDR_LO                                                                       0x036c
>+#define mmSDMA5_RLC6_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA5_RLC6_CSA_ADDR_HI                                                                       0x036d
>+#define mmSDMA5_RLC6_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA5_RLC6_IB_SUB_REMAIN                                                                     0x036f
>+#define mmSDMA5_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA5_RLC6_PREEMPT                                                                           0x0370
>+#define mmSDMA5_RLC6_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC6_DUMMY_REG                                                                         0x0371
>+#define mmSDMA5_RLC6_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x0372
>+#define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x0373
>+#define mmSDMA5_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA5_RLC6_RB_AQL_CNTL                                                                       0x0374
>+#define mmSDMA5_RLC6_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC6_MINOR_PTR_UPDATE                                                                  0x0375
>+#define mmSDMA5_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA5_RLC6_MIDCMD_DATA0                                                                      0x0380
>+#define mmSDMA5_RLC6_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA5_RLC6_MIDCMD_DATA1                                                                      0x0381
>+#define mmSDMA5_RLC6_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA5_RLC6_MIDCMD_DATA2                                                                      0x0382
>+#define mmSDMA5_RLC6_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA5_RLC6_MIDCMD_DATA3                                                                      0x0383
>+#define mmSDMA5_RLC6_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA5_RLC6_MIDCMD_DATA4                                                                      0x0384
>+#define mmSDMA5_RLC6_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA5_RLC6_MIDCMD_DATA5                                                                      0x0385
>+#define mmSDMA5_RLC6_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA5_RLC6_MIDCMD_DATA6                                                                      0x0386
>+#define mmSDMA5_RLC6_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA5_RLC6_MIDCMD_DATA7                                                                      0x0387
>+#define mmSDMA5_RLC6_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA5_RLC6_MIDCMD_DATA8                                                                      0x0388
>+#define mmSDMA5_RLC6_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA5_RLC6_MIDCMD_CNTL                                                                       0x0389
>+#define mmSDMA5_RLC6_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC7_RB_CNTL                                                                           0x0398
>+#define mmSDMA5_RLC7_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC7_RB_BASE                                                                           0x0399
>+#define mmSDMA5_RLC7_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC7_RB_BASE_HI                                                                        0x039a
>+#define mmSDMA5_RLC7_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC7_RB_RPTR                                                                           0x039b
>+#define mmSDMA5_RLC7_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC7_RB_RPTR_HI                                                                        0x039c
>+#define mmSDMA5_RLC7_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC7_RB_WPTR                                                                           0x039d
>+#define mmSDMA5_RLC7_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC7_RB_WPTR_HI                                                                        0x039e
>+#define mmSDMA5_RLC7_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC7_RB_WPTR_POLL_CNTL                                                                 0x039f
>+#define mmSDMA5_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA5_RLC7_RB_RPTR_ADDR_HI                                                                   0x03a0
>+#define mmSDMA5_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA5_RLC7_RB_RPTR_ADDR_LO                                                                   0x03a1
>+#define mmSDMA5_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA5_RLC7_IB_CNTL                                                                           0x03a2
>+#define mmSDMA5_RLC7_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC7_IB_RPTR                                                                           0x03a3
>+#define mmSDMA5_RLC7_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC7_IB_OFFSET                                                                         0x03a4
>+#define mmSDMA5_RLC7_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA5_RLC7_IB_BASE_LO                                                                        0x03a5
>+#define mmSDMA5_RLC7_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA5_RLC7_IB_BASE_HI                                                                        0x03a6
>+#define mmSDMA5_RLC7_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA5_RLC7_IB_SIZE                                                                           0x03a7
>+#define mmSDMA5_RLC7_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC7_SKIP_CNTL                                                                         0x03a8
>+#define mmSDMA5_RLC7_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA5_RLC7_CONTEXT_STATUS                                                                    0x03a9
>+#define mmSDMA5_RLC7_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA5_RLC7_DOORBELL                                                                          0x03aa
>+#define mmSDMA5_RLC7_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA5_RLC7_STATUS                                                                            0x03c0
>+#define mmSDMA5_RLC7_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA5_RLC7_DOORBELL_LOG                                                                      0x03c1
>+#define mmSDMA5_RLC7_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA5_RLC7_WATERMARK                                                                         0x03c2
>+#define mmSDMA5_RLC7_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA5_RLC7_DOORBELL_OFFSET                                                                   0x03c3
>+#define mmSDMA5_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA5_RLC7_CSA_ADDR_LO                                                                       0x03c4
>+#define mmSDMA5_RLC7_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA5_RLC7_CSA_ADDR_HI                                                                       0x03c5
>+#define mmSDMA5_RLC7_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA5_RLC7_IB_SUB_REMAIN                                                                     0x03c7
>+#define mmSDMA5_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA5_RLC7_PREEMPT                                                                           0x03c8
>+#define mmSDMA5_RLC7_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA5_RLC7_DUMMY_REG                                                                         0x03c9
>+#define mmSDMA5_RLC7_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x03ca
>+#define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x03cb
>+#define mmSDMA5_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA5_RLC7_RB_AQL_CNTL                                                                       0x03cc
>+#define mmSDMA5_RLC7_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA5_RLC7_MINOR_PTR_UPDATE                                                                  0x03cd
>+#define mmSDMA5_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA5_RLC7_MIDCMD_DATA0                                                                      0x03d8
>+#define mmSDMA5_RLC7_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA5_RLC7_MIDCMD_DATA1                                                                      0x03d9
>+#define mmSDMA5_RLC7_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA5_RLC7_MIDCMD_DATA2                                                                      0x03da
>+#define mmSDMA5_RLC7_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA5_RLC7_MIDCMD_DATA3                                                                      0x03db
>+#define mmSDMA5_RLC7_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA5_RLC7_MIDCMD_DATA4                                                                      0x03dc
>+#define mmSDMA5_RLC7_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA5_RLC7_MIDCMD_DATA5                                                                      0x03dd
>+#define mmSDMA5_RLC7_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA5_RLC7_MIDCMD_DATA6                                                                      0x03de
>+#define mmSDMA5_RLC7_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA5_RLC7_MIDCMD_DATA7                                                                      0x03df
>+#define mmSDMA5_RLC7_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA5_RLC7_MIDCMD_DATA8                                                                      0x03e0
>+#define mmSDMA5_RLC7_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA5_RLC7_MIDCMD_CNTL                                                                       0x03e1
>+#define mmSDMA5_RLC7_MIDCMD_CNTL_BASE_IDX                                                              1
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma5/sdma5_4_2_2_sh_mask.h	2019-08-31 15:01:11.933736175 -0500
>@@ -0,0 +1,2956 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma5_4_2_2_SH_MASK_HEADER
>+#define _sdma5_4_2_2_SH_MASK_HEADER
>+
>+
>+// addressBlock: sdma5_sdma5dec
>+//SDMA5_UCODE_ADDR
>+#define SDMA5_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
>+#define SDMA5_UCODE_ADDR__VALUE_MASK                                                                          0x00001FFFL
>+//SDMA5_UCODE_DATA
>+#define SDMA5_UCODE_DATA__VALUE__SHIFT                                                                        0x0
>+#define SDMA5_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
>+//SDMA5_VM_CNTL
>+#define SDMA5_VM_CNTL__CMD__SHIFT                                                                             0x0
>+#define SDMA5_VM_CNTL__CMD_MASK                                                                               0x0000000FL
>+//SDMA5_VM_CTX_LO
>+#define SDMA5_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
>+#define SDMA5_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
>+//SDMA5_VM_CTX_HI
>+#define SDMA5_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
>+#define SDMA5_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
>+//SDMA5_ACTIVE_FCN_ID
>+#define SDMA5_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
>+#define SDMA5_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x4
>+#define SDMA5_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
>+#define SDMA5_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000000FL
>+#define SDMA5_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFF0L
>+#define SDMA5_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
>+//SDMA5_VM_CTX_CNTL
>+#define SDMA5_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
>+#define SDMA5_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
>+#define SDMA5_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
>+#define SDMA5_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
>+//SDMA5_VIRT_RESET_REQ
>+#define SDMA5_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
>+#define SDMA5_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
>+#define SDMA5_VIRT_RESET_REQ__VF_MASK                                                                         0x0000FFFFL
>+#define SDMA5_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
>+//SDMA5_VF_ENABLE
>+#define SDMA5_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
>+#define SDMA5_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
>+//SDMA5_CONTEXT_REG_TYPE0
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_CNTL__SHIFT                                                     0x0
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE__SHIFT                                                     0x1
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE_HI__SHIFT                                                  0x2
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR__SHIFT                                                     0x3
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_HI__SHIFT                                                  0x4
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR__SHIFT                                                     0x5
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_HI__SHIFT                                                  0x6
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_CNTL__SHIFT                                                     0xa
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_RPTR__SHIFT                                                     0xb
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_OFFSET__SHIFT                                                   0xc
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_LO__SHIFT                                                  0xd
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_HI__SHIFT                                                  0xe
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_SIZE__SHIFT                                                     0xf
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_SKIP_CNTL__SHIFT                                                   0x10
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_STATUS__SHIFT                                              0x11
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_DOORBELL__SHIFT                                                    0x12
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_CNTL__SHIFT                                                0x13
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_CNTL_MASK                                                       0x00000001L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE_MASK                                                       0x00000002L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_BASE_HI_MASK                                                    0x00000004L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_MASK                                                       0x00000008L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_MASK                                                       0x00000020L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_CNTL_MASK                                                       0x00000400L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_RPTR_MASK                                                       0x00000800L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_OFFSET_MASK                                                     0x00001000L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_LO_MASK                                                    0x00002000L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_BASE_HI_MASK                                                    0x00004000L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_IB_SIZE_MASK                                                       0x00008000L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_SKIP_CNTL_MASK                                                     0x00010000L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_DOORBELL_MASK                                                      0x00040000L
>+#define SDMA5_CONTEXT_REG_TYPE0__SDMA5_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
>+//SDMA5_CONTEXT_REG_TYPE1
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_STATUS__SHIFT                                                      0x8
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_LOG__SHIFT                                                0x9
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_WATERMARK__SHIFT                                                   0xa
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
>+#define SDMA5_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_PREEMPT__SHIFT                                                     0x10
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DUMMY_REG__SHIFT                                                   0x11
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
>+#define SDMA5_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x16
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_STATUS_MASK                                                        0x00000100L
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_WATERMARK_MASK                                                     0x00000400L
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
>+#define SDMA5_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_PREEMPT_MASK                                                       0x00010000L
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_DUMMY_REG_MASK                                                     0x00020000L
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
>+#define SDMA5_CONTEXT_REG_TYPE1__SDMA5_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
>+#define SDMA5_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFFC00000L
>+//SDMA5_CONTEXT_REG_TYPE2
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA0__SHIFT                                                0x0
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA1__SHIFT                                                0x1
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA2__SHIFT                                                0x2
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA3__SHIFT                                                0x3
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA4__SHIFT                                                0x4
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA5__SHIFT                                                0x5
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA6__SHIFT                                                0x6
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA7__SHIFT                                                0x7
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA8__SHIFT                                                0x8
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_CNTL__SHIFT                                                 0x9
>+#define SDMA5_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
>+#define SDMA5_CONTEXT_REG_TYPE2__SDMA5_GFX_MIDCMD_CNTL_MASK                                                   0x00000200L
>+#define SDMA5_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFFC00L
>+//SDMA5_CONTEXT_REG_TYPE3
>+#define SDMA5_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
>+#define SDMA5_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
>+//SDMA5_PUB_REG_TYPE0
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_ADDR__SHIFT                                                          0x0
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_DATA__SHIFT                                                          0x1
>+#define SDMA5_PUB_REG_TYPE0__RESERVED3__SHIFT                                                                 0x3
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CNTL__SHIFT                                                             0x4
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_LO__SHIFT                                                           0x5
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_HI__SHIFT                                                           0x6
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_ACTIVE_FCN_ID__SHIFT                                                       0x7
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_CNTL__SHIFT                                                         0x8
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_VIRT_RESET_REQ__SHIFT                                                      0x9
>+#define SDMA5_PUB_REG_TYPE0__RESERVED10__SHIFT                                                                0xa
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE0__SHIFT                                                   0xb
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE1__SHIFT                                                   0xc
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE2__SHIFT                                                   0xd
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE3__SHIFT                                                   0xe
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE0__SHIFT                                                       0xf
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE1__SHIFT                                                       0x10
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE2__SHIFT                                                       0x11
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE3__SHIFT                                                       0x12
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_MMHUB_CNTL__SHIFT                                                          0x13
>+#define SDMA5_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x15
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_GROUP_BOUNDARY__SHIFT                                              0x19
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_POWER_CNTL__SHIFT                                                          0x1a
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CLK_CTRL__SHIFT                                                            0x1b
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CNTL__SHIFT                                                                0x1c
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CHICKEN_BITS__SHIFT                                                        0x1d
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG__SHIFT                                                      0x1e
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_ADDR_MASK                                                            0x00000001L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_UCODE_DATA_MASK                                                            0x00000002L
>+#define SDMA5_PUB_REG_TYPE0__RESERVED3_MASK                                                                   0x00000008L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CNTL_MASK                                                               0x00000010L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_LO_MASK                                                             0x00000020L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_HI_MASK                                                             0x00000040L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_ACTIVE_FCN_ID_MASK                                                         0x00000080L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_VM_CTX_CNTL_MASK                                                           0x00000100L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_VIRT_RESET_REQ_MASK                                                        0x00000200L
>+#define SDMA5_PUB_REG_TYPE0__RESERVED10_MASK                                                                  0x00000400L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE0_MASK                                                     0x00000800L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE1_MASK                                                     0x00001000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE2_MASK                                                     0x00002000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_REG_TYPE3_MASK                                                     0x00004000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE0_MASK                                                         0x00008000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE1_MASK                                                         0x00010000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE2_MASK                                                         0x00020000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_PUB_REG_TYPE3_MASK                                                         0x00040000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_MMHUB_CNTL_MASK                                                            0x00080000L
>+#define SDMA5_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x01E00000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CONTEXT_GROUP_BOUNDARY_MASK                                                0x02000000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_POWER_CNTL_MASK                                                            0x04000000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CLK_CTRL_MASK                                                              0x08000000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CNTL_MASK                                                                  0x10000000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_CHICKEN_BITS_MASK                                                          0x20000000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG_MASK                                                        0x40000000L
>+#define SDMA5_PUB_REG_TYPE0__SDMA5_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
>+//SDMA5_PUB_REG_TYPE1
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH__SHIFT                                                       0x2
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_IB_OFFSET_FETCH__SHIFT                                                     0x3
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_PROGRAM__SHIFT                                                             0x4
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS_REG__SHIFT                                                          0x5
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS1_REG__SHIFT                                                         0x6
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_RD_BURST_CNTL__SHIFT                                                       0x7
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_HBM_PAGE_CONFIG__SHIFT                                                     0x8
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_UCODE_CHECKSUM__SHIFT                                                      0x9
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_F32_CNTL__SHIFT                                                            0xa
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_FREEZE__SHIFT                                                              0xb
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE0_QUANTUM__SHIFT                                                      0xc
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE1_QUANTUM__SHIFT                                                      0xd
>+#define SDMA5_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT                                                         0xe
>+#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT                                                         0xf
>+#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT                                                          0x10
>+#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT                                                           0x11
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_CONFIG__SHIFT                                                          0x12
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_BA_THRESHOLD__SHIFT                                                        0x13
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_ID__SHIFT                                                                  0x14
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_VERSION__SHIFT                                                             0x15
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER__SHIFT                                                         0x16
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS2_REG__SHIFT                                                         0x18
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_CNTL__SHIFT                                                         0x19
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_CNTL__SHIFT                                                          0x1c
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WATERMK__SHIFT                                                       0x1d
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_RD_STATUS__SHIFT                                                     0x1e
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WR_STATUS__SHIFT                                                     0x1f
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_RB_RPTR_FETCH_MASK                                                         0x00000004L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_IB_OFFSET_FETCH_MASK                                                       0x00000008L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_PROGRAM_MASK                                                               0x00000010L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS_REG_MASK                                                            0x00000020L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS1_REG_MASK                                                           0x00000040L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_RD_BURST_CNTL_MASK                                                         0x00000080L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_UCODE_CHECKSUM_MASK                                                        0x00000200L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_F32_CNTL_MASK                                                              0x00000400L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_FREEZE_MASK                                                                0x00000800L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE0_QUANTUM_MASK                                                        0x00001000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_PHASE1_QUANTUM_MASK                                                        0x00002000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK                                                           0x00004000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK                                                           0x00008000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK                                                            0x00010000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK                                                             0x00020000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_CONFIG_MASK                                                            0x00040000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_BA_THRESHOLD_MASK                                                          0x00080000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_ID_MASK                                                                    0x00100000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_VERSION_MASK                                                               0x00200000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER_MASK                                                           0x00400000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_STATUS2_REG_MASK                                                           0x01000000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_CNTL_MASK                                                           0x02000000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_CNTL_MASK                                                            0x10000000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WATERMK_MASK                                                         0x20000000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_RD_STATUS_MASK                                                       0x40000000L
>+#define SDMA5_PUB_REG_TYPE1__SDMA5_UTCL1_WR_STATUS_MASK                                                       0x80000000L
>+//SDMA5_PUB_REG_TYPE2
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV0__SHIFT                                                          0x0
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV1__SHIFT                                                          0x1
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV2__SHIFT                                                          0x2
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK0__SHIFT                                                     0x3
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK1__SHIFT                                                     0x4
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK0__SHIFT                                                     0x5
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK1__SHIFT                                                     0x6
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_TIMEOUT__SHIFT                                                       0x7
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_PAGE__SHIFT                                                          0x8
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_POWER_CNTL_IDLE__SHIFT                                                     0x9
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_RELAX_ORDERING_LUT__SHIFT                                                  0xa
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_CHICKEN_BITS_2__SHIFT                                                      0xb
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_STATUS3_REG__SHIFT                                                         0xc
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PHASE2_QUANTUM__SHIFT                                                      0xf
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_ERROR_LOG__SHIFT                                                           0x10
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG0__SHIFT                                                      0x11
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG1__SHIFT                                                      0x12
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG2__SHIFT                                                      0x13
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG3__SHIFT                                                      0x14
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_F32_COUNTER__SHIFT                                                         0x15
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UNBREAKABLE__SHIFT                                                         0x16
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFMON_CNTL__SHIFT                                                        0x17
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER0_RESULT__SHIFT                                                 0x18
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER1_RESULT__SHIFT                                                 0x19
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT                                         0x1a
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_CRD_CNTL__SHIFT                                                            0x1b
>+#define SDMA5_PUB_REG_TYPE2__RESERVED28__SHIFT                                                                0x1c
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_GPU_IOV_VIOLATION_LOG__SHIFT                                               0x1d
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_ULV_CNTL__SHIFT                                                            0x1e
>+#define SDMA5_PUB_REG_TYPE2__RESERVED__SHIFT                                                                  0x1f
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV0_MASK                                                            0x00000001L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV1_MASK                                                            0x00000002L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_INV2_MASK                                                            0x00000004L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_TIMEOUT_MASK                                                         0x00000080L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UTCL1_PAGE_MASK                                                            0x00000100L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_POWER_CNTL_IDLE_MASK                                                       0x00000200L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_CHICKEN_BITS_2_MASK                                                        0x00000800L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_STATUS3_REG_MASK                                                           0x00001000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PHASE2_QUANTUM_MASK                                                        0x00008000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_ERROR_LOG_MASK                                                             0x00010000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG0_MASK                                                        0x00020000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG1_MASK                                                        0x00040000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG2_MASK                                                        0x00080000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PUB_DUMMY_REG3_MASK                                                        0x00100000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_F32_COUNTER_MASK                                                           0x00200000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_UNBREAKABLE_MASK                                                           0x00400000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFMON_CNTL_MASK                                                          0x00800000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER0_RESULT_MASK                                                   0x01000000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER1_RESULT_MASK                                                   0x02000000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_PERFCOUNTER_TAG_DELAY_RANGE_MASK                                           0x04000000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_CRD_CNTL_MASK                                                              0x08000000L
>+#define SDMA5_PUB_REG_TYPE2__RESERVED28_MASK                                                                  0x10000000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_GPU_IOV_VIOLATION_LOG_MASK                                                 0x20000000L
>+#define SDMA5_PUB_REG_TYPE2__SDMA5_ULV_CNTL_MASK                                                              0x40000000L
>+#define SDMA5_PUB_REG_TYPE2__RESERVED_MASK                                                                    0x80000000L
>+//SDMA5_PUB_REG_TYPE3
>+#define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
>+#define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
>+#define SDMA5_PUB_REG_TYPE3__SDMA5_GPU_IOV_VIOLATION_LOG2__SHIFT                                              0x2
>+#define SDMA5_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x3
>+#define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
>+#define SDMA5_PUB_REG_TYPE3__SDMA5_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
>+#define SDMA5_PUB_REG_TYPE3__SDMA5_GPU_IOV_VIOLATION_LOG2_MASK                                                0x00000004L
>+#define SDMA5_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xFFFFFFF8L
>+//SDMA5_MMHUB_CNTL
>+#define SDMA5_MMHUB_CNTL__UNIT_ID__SHIFT                                                                      0x0
>+#define SDMA5_MMHUB_CNTL__UNIT_ID_MASK                                                                        0x0000003FL
>+//SDMA5_CONTEXT_GROUP_BOUNDARY
>+#define SDMA5_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT                                                         0x0
>+#define SDMA5_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK                                                           0xFFFFFFFFL
>+//SDMA5_POWER_CNTL
>+#define SDMA5_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
>+#define SDMA5_POWER_CNTL__MEM_POWER_LS_EN__SHIFT                                                              0x9
>+#define SDMA5_POWER_CNTL__MEM_POWER_DS_EN__SHIFT                                                              0xa
>+#define SDMA5_POWER_CNTL__MEM_POWER_SD_EN__SHIFT                                                              0xb
>+#define SDMA5_POWER_CNTL__MEM_POWER_DELAY__SHIFT                                                              0xc
>+#define SDMA5_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
>+#define SDMA5_POWER_CNTL__MEM_POWER_LS_EN_MASK                                                                0x00000200L
>+#define SDMA5_POWER_CNTL__MEM_POWER_DS_EN_MASK                                                                0x00000400L
>+#define SDMA5_POWER_CNTL__MEM_POWER_SD_EN_MASK                                                                0x00000800L
>+#define SDMA5_POWER_CNTL__MEM_POWER_DELAY_MASK                                                                0x003FF000L
>+//SDMA5_CLK_CTRL
>+#define SDMA5_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
>+#define SDMA5_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
>+#define SDMA5_CLK_CTRL__RESERVED__SHIFT                                                                       0xc
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                                 0x18
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                                 0x19
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                                 0x1a
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1b
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1c
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1d
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1e
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1f
>+#define SDMA5_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
>+#define SDMA5_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
>+#define SDMA5_CLK_CTRL__RESERVED_MASK                                                                         0x00FFF000L
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                   0x01000000L
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                   0x02000000L
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                   0x04000000L
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x08000000L
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x10000000L
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x20000000L
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x40000000L
>+#define SDMA5_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x80000000L
>+//SDMA5_CNTL
>+#define SDMA5_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
>+#define SDMA5_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
>+#define SDMA5_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
>+#define SDMA5_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
>+#define SDMA5_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
>+#define SDMA5_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
>+#define SDMA5_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
>+#define SDMA5_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
>+#define SDMA5_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
>+#define SDMA5_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
>+#define SDMA5_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
>+#define SDMA5_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
>+#define SDMA5_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
>+#define SDMA5_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
>+#define SDMA5_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
>+#define SDMA5_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
>+#define SDMA5_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
>+#define SDMA5_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
>+#define SDMA5_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
>+#define SDMA5_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
>+#define SDMA5_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
>+#define SDMA5_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
>+//SDMA5_CHICKEN_BITS
>+#define SDMA5_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
>+#define SDMA5_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
>+#define SDMA5_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
>+#define SDMA5_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
>+#define SDMA5_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
>+#define SDMA5_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
>+#define SDMA5_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
>+#define SDMA5_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
>+#define SDMA5_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
>+#define SDMA5_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
>+#define SDMA5_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
>+#define SDMA5_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
>+#define SDMA5_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
>+#define SDMA5_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
>+#define SDMA5_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
>+#define SDMA5_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
>+#define SDMA5_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
>+#define SDMA5_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
>+#define SDMA5_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
>+#define SDMA5_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
>+#define SDMA5_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
>+#define SDMA5_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
>+#define SDMA5_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
>+#define SDMA5_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
>+#define SDMA5_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
>+#define SDMA5_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
>+//SDMA5_GB_ADDR_CONFIG
>+#define SDMA5_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
>+#define SDMA5_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
>+#define SDMA5_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
>+#define SDMA5_GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
>+#define SDMA5_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
>+#define SDMA5_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
>+#define SDMA5_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
>+#define SDMA5_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
>+#define SDMA5_GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
>+#define SDMA5_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
>+//SDMA5_GB_ADDR_CONFIG_READ
>+#define SDMA5_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
>+#define SDMA5_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
>+#define SDMA5_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                0x8
>+#define SDMA5_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                           0xc
>+#define SDMA5_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
>+#define SDMA5_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
>+#define SDMA5_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
>+#define SDMA5_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                  0x00000700L
>+#define SDMA5_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                             0x00007000L
>+#define SDMA5_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
>+//SDMA5_RB_RPTR_FETCH_HI
>+#define SDMA5_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
>+#define SDMA5_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_SEM_WAIT_FAIL_TIMER_CNTL
>+#define SDMA5_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
>+#define SDMA5_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
>+//SDMA5_RB_RPTR_FETCH
>+#define SDMA5_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
>+#define SDMA5_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
>+//SDMA5_IB_OFFSET_FETCH
>+#define SDMA5_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
>+#define SDMA5_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
>+//SDMA5_PROGRAM
>+#define SDMA5_PROGRAM__STREAM__SHIFT                                                                          0x0
>+#define SDMA5_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
>+//SDMA5_STATUS_REG
>+#define SDMA5_STATUS_REG__IDLE__SHIFT                                                                         0x0
>+#define SDMA5_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
>+#define SDMA5_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
>+#define SDMA5_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
>+#define SDMA5_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
>+#define SDMA5_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
>+#define SDMA5_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
>+#define SDMA5_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
>+#define SDMA5_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
>+#define SDMA5_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
>+#define SDMA5_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
>+#define SDMA5_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
>+#define SDMA5_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
>+#define SDMA5_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
>+#define SDMA5_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
>+#define SDMA5_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
>+#define SDMA5_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
>+#define SDMA5_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
>+#define SDMA5_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
>+#define SDMA5_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
>+#define SDMA5_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
>+#define SDMA5_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
>+#define SDMA5_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
>+#define SDMA5_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
>+#define SDMA5_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
>+#define SDMA5_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
>+#define SDMA5_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
>+#define SDMA5_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
>+#define SDMA5_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
>+#define SDMA5_STATUS_REG__IDLE_MASK                                                                           0x00000001L
>+#define SDMA5_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
>+#define SDMA5_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
>+#define SDMA5_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
>+#define SDMA5_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
>+#define SDMA5_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
>+#define SDMA5_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
>+#define SDMA5_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
>+#define SDMA5_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
>+#define SDMA5_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
>+#define SDMA5_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
>+#define SDMA5_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
>+#define SDMA5_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
>+#define SDMA5_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
>+#define SDMA5_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
>+#define SDMA5_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
>+#define SDMA5_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
>+#define SDMA5_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
>+#define SDMA5_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
>+#define SDMA5_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
>+#define SDMA5_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
>+#define SDMA5_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
>+#define SDMA5_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
>+#define SDMA5_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
>+#define SDMA5_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
>+#define SDMA5_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
>+#define SDMA5_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
>+#define SDMA5_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
>+#define SDMA5_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
>+//SDMA5_STATUS1_REG
>+#define SDMA5_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
>+#define SDMA5_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
>+#define SDMA5_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
>+#define SDMA5_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
>+#define SDMA5_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
>+#define SDMA5_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
>+#define SDMA5_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
>+#define SDMA5_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
>+#define SDMA5_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
>+#define SDMA5_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
>+#define SDMA5_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
>+#define SDMA5_STATUS1_REG__EX_START__SHIFT                                                                    0xf
>+#define SDMA5_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
>+#define SDMA5_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
>+#define SDMA5_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
>+#define SDMA5_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
>+#define SDMA5_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
>+#define SDMA5_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
>+#define SDMA5_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
>+#define SDMA5_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
>+#define SDMA5_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
>+#define SDMA5_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
>+#define SDMA5_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
>+#define SDMA5_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
>+#define SDMA5_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
>+#define SDMA5_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
>+#define SDMA5_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
>+#define SDMA5_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
>+//SDMA5_RD_BURST_CNTL
>+#define SDMA5_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
>+#define SDMA5_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT                                                       0x2
>+#define SDMA5_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
>+#define SDMA5_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK                                                         0x0000000CL
>+//SDMA5_HBM_PAGE_CONFIG
>+#define SDMA5_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
>+#define SDMA5_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000001L
>+//SDMA5_UCODE_CHECKSUM
>+#define SDMA5_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
>+#define SDMA5_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_F32_CNTL
>+#define SDMA5_F32_CNTL__HALT__SHIFT                                                                           0x0
>+#define SDMA5_F32_CNTL__STEP__SHIFT                                                                           0x1
>+#define SDMA5_F32_CNTL__HALT_MASK                                                                             0x00000001L
>+#define SDMA5_F32_CNTL__STEP_MASK                                                                             0x00000002L
>+//SDMA5_FREEZE
>+#define SDMA5_FREEZE__PREEMPT__SHIFT                                                                          0x0
>+#define SDMA5_FREEZE__FREEZE__SHIFT                                                                           0x4
>+#define SDMA5_FREEZE__FROZEN__SHIFT                                                                           0x5
>+#define SDMA5_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
>+#define SDMA5_FREEZE__PREEMPT_MASK                                                                            0x00000001L
>+#define SDMA5_FREEZE__FREEZE_MASK                                                                             0x00000010L
>+#define SDMA5_FREEZE__FROZEN_MASK                                                                             0x00000020L
>+#define SDMA5_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
>+//SDMA5_PHASE0_QUANTUM
>+#define SDMA5_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA5_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA5_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA5_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA5_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA5_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA5_PHASE1_QUANTUM
>+#define SDMA5_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA5_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA5_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA5_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA5_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA5_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA5_EDC_CONFIG
>+#define SDMA5_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
>+#define SDMA5_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
>+#define SDMA5_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
>+#define SDMA5_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
>+//SDMA5_BA_THRESHOLD
>+#define SDMA5_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
>+#define SDMA5_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
>+#define SDMA5_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
>+#define SDMA5_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
>+//SDMA5_ID
>+#define SDMA5_ID__DEVICE_ID__SHIFT                                                                            0x0
>+#define SDMA5_ID__DEVICE_ID_MASK                                                                              0x000000FFL
>+//SDMA5_VERSION
>+#define SDMA5_VERSION__MINVER__SHIFT                                                                          0x0
>+#define SDMA5_VERSION__MAJVER__SHIFT                                                                          0x8
>+#define SDMA5_VERSION__REV__SHIFT                                                                             0x10
>+#define SDMA5_VERSION__MINVER_MASK                                                                            0x0000007FL
>+#define SDMA5_VERSION__MAJVER_MASK                                                                            0x00007F00L
>+#define SDMA5_VERSION__REV_MASK                                                                               0x003F0000L
>+//SDMA5_EDC_COUNTER
>+#define SDMA5_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT                                                          0x0
>+#define SDMA5_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
>+#define SDMA5_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
>+#define SDMA5_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
>+#define SDMA5_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
>+#define SDMA5_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT                                                    0xf
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT                                                    0x10
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT                                                   0x11
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT                                                   0x12
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT                                                   0x13
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT                                                   0x14
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT                                                   0x15
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT                                                   0x16
>+#define SDMA5_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0x17
>+#define SDMA5_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x18
>+#define SDMA5_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK                                                            0x00000001L
>+#define SDMA5_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
>+#define SDMA5_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
>+#define SDMA5_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
>+#define SDMA5_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
>+#define SDMA5_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK                                                      0x00008000L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK                                                      0x00010000L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK                                                     0x00020000L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK                                                     0x00040000L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK                                                     0x00080000L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK                                                     0x00100000L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK                                                     0x00200000L
>+#define SDMA5_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK                                                     0x00400000L
>+#define SDMA5_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00800000L
>+#define SDMA5_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x01000000L
>+//SDMA5_EDC_COUNTER_CLEAR
>+#define SDMA5_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
>+#define SDMA5_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
>+//SDMA5_STATUS2_REG
>+#define SDMA5_STATUS2_REG__ID__SHIFT                                                                          0x0
>+#define SDMA5_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x3
>+#define SDMA5_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
>+#define SDMA5_STATUS2_REG__ID_MASK                                                                            0x00000007L
>+#define SDMA5_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFF8L
>+#define SDMA5_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
>+//SDMA5_ATOMIC_CNTL
>+#define SDMA5_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
>+#define SDMA5_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
>+#define SDMA5_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
>+#define SDMA5_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
>+//SDMA5_ATOMIC_PREOP_LO
>+#define SDMA5_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
>+#define SDMA5_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_ATOMIC_PREOP_HI
>+#define SDMA5_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
>+#define SDMA5_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_UTCL1_CNTL
>+#define SDMA5_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
>+#define SDMA5_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0xb
>+#define SDMA5_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0xe
>+#define SDMA5_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
>+#define SDMA5_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
>+#define SDMA5_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x000007FEL
>+#define SDMA5_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x00003800L
>+#define SDMA5_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FFC000L
>+#define SDMA5_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
>+#define SDMA5_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
>+//SDMA5_UTCL1_WATERMK
>+#define SDMA5_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
>+#define SDMA5_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0x9
>+#define SDMA5_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x11
>+#define SDMA5_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x19
>+#define SDMA5_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000001FFL
>+#define SDMA5_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0001FE00L
>+#define SDMA5_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x01FE0000L
>+#define SDMA5_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFE000000L
>+//SDMA5_UTCL1_RD_STATUS
>+#define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA5_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA5_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA5_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA5_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT                                                             0x15
>+#define SDMA5_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x16
>+#define SDMA5_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x1a
>+#define SDMA5_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x1d
>+#define SDMA5_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT                                                            0x1e
>+#define SDMA5_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT                                                             0x1f
>+#define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA5_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA5_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA5_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA5_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA5_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA5_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA5_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA5_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA5_UTCL1_RD_STATUS__CE_L1_STALL_MASK                                                               0x00200000L
>+#define SDMA5_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x03C00000L
>+#define SDMA5_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x1C000000L
>+#define SDMA5_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x20000000L
>+#define SDMA5_UTCL1_RD_STATUS__WPTR_POLLING_MASK                                                              0x40000000L
>+#define SDMA5_UTCL1_RD_STATUS__INVREQ_SIZE_MASK                                                               0x80000000L
>+//SDMA5_UTCL1_WR_STATUS
>+#define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA5_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA5_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA5_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA5_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15
>+#define SDMA5_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x16
>+#define SDMA5_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19
>+#define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
>+#define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
>+#define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
>+#define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
>+#define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA5_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA5_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA5_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA5_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA5_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA5_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA5_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA5_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA5_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x00200000L
>+#define SDMA5_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x01C00000L
>+#define SDMA5_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x0E000000L
>+#define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
>+#define SDMA5_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
>+#define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
>+#define SDMA5_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
>+//SDMA5_UTCL1_INV0
>+#define SDMA5_UTCL1_INV0__INV_MIDDLE__SHIFT                                                                   0x0
>+#define SDMA5_UTCL1_INV0__RD_TIMEOUT__SHIFT                                                                   0x1
>+#define SDMA5_UTCL1_INV0__WR_TIMEOUT__SHIFT                                                                   0x2
>+#define SDMA5_UTCL1_INV0__RD_IN_INVADR__SHIFT                                                                 0x3
>+#define SDMA5_UTCL1_INV0__WR_IN_INVADR__SHIFT                                                                 0x4
>+#define SDMA5_UTCL1_INV0__PAGE_NULL_SW__SHIFT                                                                 0x5
>+#define SDMA5_UTCL1_INV0__XNACK_IS_INVADR__SHIFT                                                              0x6
>+#define SDMA5_UTCL1_INV0__INVREQ_ENABLE__SHIFT                                                                0x7
>+#define SDMA5_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT                                                              0x8
>+#define SDMA5_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT                                                              0x9
>+#define SDMA5_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT                                                               0xa
>+#define SDMA5_UTCL1_INV0__INV_FLUSHTYPE__SHIFT                                                                0xb
>+#define SDMA5_UTCL1_INV0__INV_VMID_VEC__SHIFT                                                                 0xc
>+#define SDMA5_UTCL1_INV0__INV_ADDR_HI__SHIFT                                                                  0x1c
>+#define SDMA5_UTCL1_INV0__INV_MIDDLE_MASK                                                                     0x00000001L
>+#define SDMA5_UTCL1_INV0__RD_TIMEOUT_MASK                                                                     0x00000002L
>+#define SDMA5_UTCL1_INV0__WR_TIMEOUT_MASK                                                                     0x00000004L
>+#define SDMA5_UTCL1_INV0__RD_IN_INVADR_MASK                                                                   0x00000008L
>+#define SDMA5_UTCL1_INV0__WR_IN_INVADR_MASK                                                                   0x00000010L
>+#define SDMA5_UTCL1_INV0__PAGE_NULL_SW_MASK                                                                   0x00000020L
>+#define SDMA5_UTCL1_INV0__XNACK_IS_INVADR_MASK                                                                0x00000040L
>+#define SDMA5_UTCL1_INV0__INVREQ_ENABLE_MASK                                                                  0x00000080L
>+#define SDMA5_UTCL1_INV0__NACK_TIMEOUT_SW_MASK                                                                0x00000100L
>+#define SDMA5_UTCL1_INV0__NFLUSH_INV_IDLE_MASK                                                                0x00000200L
>+#define SDMA5_UTCL1_INV0__FLUSH_INV_IDLE_MASK                                                                 0x00000400L
>+#define SDMA5_UTCL1_INV0__INV_FLUSHTYPE_MASK                                                                  0x00000800L
>+#define SDMA5_UTCL1_INV0__INV_VMID_VEC_MASK                                                                   0x0FFFF000L
>+#define SDMA5_UTCL1_INV0__INV_ADDR_HI_MASK                                                                    0xF0000000L
>+//SDMA5_UTCL1_INV1
>+#define SDMA5_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
>+#define SDMA5_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_UTCL1_INV2
>+#define SDMA5_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT                                                          0x0
>+#define SDMA5_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK                                                            0xFFFFFFFFL
>+//SDMA5_UTCL1_RD_XNACK0
>+#define SDMA5_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA5_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA5_UTCL1_RD_XNACK1
>+#define SDMA5_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA5_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA5_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA5_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA5_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA5_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA5_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA5_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA5_UTCL1_WR_XNACK0
>+#define SDMA5_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA5_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA5_UTCL1_WR_XNACK1
>+#define SDMA5_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA5_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA5_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA5_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA5_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA5_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA5_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA5_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA5_UTCL1_TIMEOUT
>+#define SDMA5_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
>+#define SDMA5_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
>+#define SDMA5_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
>+#define SDMA5_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
>+//SDMA5_UTCL1_PAGE
>+#define SDMA5_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
>+#define SDMA5_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
>+#define SDMA5_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
>+#define SDMA5_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0x9
>+#define SDMA5_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
>+#define SDMA5_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
>+#define SDMA5_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000001C0L
>+#define SDMA5_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000200L
>+//SDMA5_POWER_CNTL_IDLE
>+#define SDMA5_POWER_CNTL_IDLE__DELAY0__SHIFT                                                                  0x0
>+#define SDMA5_POWER_CNTL_IDLE__DELAY1__SHIFT                                                                  0x10
>+#define SDMA5_POWER_CNTL_IDLE__DELAY2__SHIFT                                                                  0x18
>+#define SDMA5_POWER_CNTL_IDLE__DELAY0_MASK                                                                    0x0000FFFFL
>+#define SDMA5_POWER_CNTL_IDLE__DELAY1_MASK                                                                    0x00FF0000L
>+#define SDMA5_POWER_CNTL_IDLE__DELAY2_MASK                                                                    0xFF000000L
>+//SDMA5_RELAX_ORDERING_LUT
>+#define SDMA5_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
>+#define SDMA5_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
>+#define SDMA5_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
>+#define SDMA5_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
>+#define SDMA5_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
>+#define SDMA5_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
>+#define SDMA5_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
>+#define SDMA5_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
>+#define SDMA5_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
>+#define SDMA5_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
>+#define SDMA5_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
>+#define SDMA5_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
>+#define SDMA5_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
>+#define SDMA5_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
>+#define SDMA5_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
>+#define SDMA5_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
>+#define SDMA5_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
>+#define SDMA5_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
>+#define SDMA5_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
>+#define SDMA5_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
>+#define SDMA5_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
>+#define SDMA5_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
>+#define SDMA5_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
>+#define SDMA5_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
>+#define SDMA5_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
>+#define SDMA5_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
>+#define SDMA5_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
>+#define SDMA5_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
>+#define SDMA5_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
>+#define SDMA5_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
>+#define SDMA5_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
>+#define SDMA5_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
>+#define SDMA5_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
>+#define SDMA5_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
>+#define SDMA5_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
>+#define SDMA5_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
>+#define SDMA5_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
>+#define SDMA5_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
>+//SDMA5_CHICKEN_BITS_2
>+#define SDMA5_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
>+#define SDMA5_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
>+//SDMA5_STATUS3_REG
>+#define SDMA5_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
>+#define SDMA5_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
>+#define SDMA5_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
>+#define SDMA5_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x15
>+#define SDMA5_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x16
>+#define SDMA5_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
>+#define SDMA5_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
>+#define SDMA5_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
>+#define SDMA5_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x00200000L
>+#define SDMA5_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x03C00000L
>+//SDMA5_PHYSICAL_ADDR_LO
>+#define SDMA5_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
>+#define SDMA5_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
>+#define SDMA5_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
>+#define SDMA5_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
>+#define SDMA5_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
>+#define SDMA5_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
>+#define SDMA5_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
>+#define SDMA5_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
>+//SDMA5_PHYSICAL_ADDR_HI
>+#define SDMA5_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA5_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
>+//SDMA5_PHASE2_QUANTUM
>+#define SDMA5_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA5_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA5_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA5_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA5_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA5_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA5_ERROR_LOG
>+#define SDMA5_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
>+#define SDMA5_ERROR_LOG__STATUS__SHIFT                                                                        0x10
>+#define SDMA5_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
>+#define SDMA5_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
>+//SDMA5_PUB_DUMMY_REG0
>+#define SDMA5_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
>+#define SDMA5_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_PUB_DUMMY_REG1
>+#define SDMA5_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
>+#define SDMA5_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_PUB_DUMMY_REG2
>+#define SDMA5_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
>+#define SDMA5_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_PUB_DUMMY_REG3
>+#define SDMA5_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
>+#define SDMA5_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_F32_COUNTER
>+#define SDMA5_F32_COUNTER__VALUE__SHIFT                                                                       0x0
>+#define SDMA5_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
>+//SDMA5_UNBREAKABLE
>+#define SDMA5_UNBREAKABLE__VALUE__SHIFT                                                                       0x0
>+#define SDMA5_UNBREAKABLE__VALUE_MASK                                                                         0x00000001L
>+//SDMA5_PERFMON_CNTL
>+#define SDMA5_PERFMON_CNTL__PERF_ENABLE0__SHIFT                                                               0x0
>+#define SDMA5_PERFMON_CNTL__PERF_CLEAR0__SHIFT                                                                0x1
>+#define SDMA5_PERFMON_CNTL__PERF_SEL0__SHIFT                                                                  0x2
>+#define SDMA5_PERFMON_CNTL__PERF_ENABLE1__SHIFT                                                               0xa
>+#define SDMA5_PERFMON_CNTL__PERF_CLEAR1__SHIFT                                                                0xb
>+#define SDMA5_PERFMON_CNTL__PERF_SEL1__SHIFT                                                                  0xc
>+#define SDMA5_PERFMON_CNTL__PERF_ENABLE0_MASK                                                                 0x00000001L
>+#define SDMA5_PERFMON_CNTL__PERF_CLEAR0_MASK                                                                  0x00000002L
>+#define SDMA5_PERFMON_CNTL__PERF_SEL0_MASK                                                                    0x000003FCL
>+#define SDMA5_PERFMON_CNTL__PERF_ENABLE1_MASK                                                                 0x00000400L
>+#define SDMA5_PERFMON_CNTL__PERF_CLEAR1_MASK                                                                  0x00000800L
>+#define SDMA5_PERFMON_CNTL__PERF_SEL1_MASK                                                                    0x000FF000L
>+//SDMA5_PERFCOUNTER0_RESULT
>+#define SDMA5_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA5_PERFCOUNTER0_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA5_PERFCOUNTER1_RESULT
>+#define SDMA5_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA5_PERFCOUNTER1_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA5_PERFCOUNTER_TAG_DELAY_RANGE
>+#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT                                                   0x0
>+#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT                                                  0xe
>+#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT                                                   0x1c
>+#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK                                                     0x00003FFFL
>+#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK                                                    0x0FFFC000L
>+#define SDMA5_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK                                                     0x10000000L
>+//SDMA5_CRD_CNTL
>+#define SDMA5_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
>+#define SDMA5_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
>+#define SDMA5_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
>+#define SDMA5_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
>+//SDMA5_GPU_IOV_VIOLATION_LOG
>+#define SDMA5_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT                                                  0x0
>+#define SDMA5_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT                                         0x1
>+#define SDMA5_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT                                                           0x2
>+#define SDMA5_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT                                                   0x14
>+#define SDMA5_GPU_IOV_VIOLATION_LOG__VF__SHIFT                                                                0x15
>+#define SDMA5_GPU_IOV_VIOLATION_LOG__VFID__SHIFT                                                              0x16
>+#define SDMA5_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK                                                    0x00000001L
>+#define SDMA5_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK                                           0x00000002L
>+#define SDMA5_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK                                                             0x000FFFFCL
>+#define SDMA5_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK                                                     0x00100000L
>+#define SDMA5_GPU_IOV_VIOLATION_LOG__VF_MASK                                                                  0x00200000L
>+#define SDMA5_GPU_IOV_VIOLATION_LOG__VFID_MASK                                                                0x03C00000L
>+//SDMA5_ULV_CNTL
>+#define SDMA5_ULV_CNTL__HYSTERESIS__SHIFT                                                                     0x0
>+#define SDMA5_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT                                                              0x1b
>+#define SDMA5_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT                                                               0x1c
>+#define SDMA5_ULV_CNTL__ENTER_ULV_INT__SHIFT                                                                  0x1d
>+#define SDMA5_ULV_CNTL__EXIT_ULV_INT__SHIFT                                                                   0x1e
>+#define SDMA5_ULV_CNTL__ULV_STATUS__SHIFT                                                                     0x1f
>+#define SDMA5_ULV_CNTL__HYSTERESIS_MASK                                                                       0x0000001FL
>+#define SDMA5_ULV_CNTL__ENTER_ULV_INT_CLR_MASK                                                                0x08000000L
>+#define SDMA5_ULV_CNTL__EXIT_ULV_INT_CLR_MASK                                                                 0x10000000L
>+#define SDMA5_ULV_CNTL__ENTER_ULV_INT_MASK                                                                    0x20000000L
>+#define SDMA5_ULV_CNTL__EXIT_ULV_INT_MASK                                                                     0x40000000L
>+#define SDMA5_ULV_CNTL__ULV_STATUS_MASK                                                                       0x80000000L
>+//SDMA5_EA_DBIT_ADDR_DATA
>+#define SDMA5_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
>+#define SDMA5_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_EA_DBIT_ADDR_INDEX
>+#define SDMA5_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
>+#define SDMA5_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
>+//SDMA5_GPU_IOV_VIOLATION_LOG2
>+#define SDMA5_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                     0x0
>+#define SDMA5_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                       0x000000FFL
>+//SDMA5_GFX_RB_CNTL
>+#define SDMA5_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA5_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
>+#define SDMA5_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
>+#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
>+#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
>+#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
>+#define SDMA5_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
>+#define SDMA5_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
>+#define SDMA5_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA5_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
>+#define SDMA5_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
>+#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
>+#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
>+#define SDMA5_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
>+#define SDMA5_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
>+#define SDMA5_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
>+//SDMA5_GFX_RB_BASE
>+#define SDMA5_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
>+#define SDMA5_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
>+//SDMA5_GFX_RB_BASE_HI
>+#define SDMA5_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA5_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
>+//SDMA5_GFX_RB_RPTR
>+#define SDMA5_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA5_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA5_GFX_RB_RPTR_HI
>+#define SDMA5_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA5_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA5_GFX_RB_WPTR
>+#define SDMA5_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA5_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA5_GFX_RB_WPTR_HI
>+#define SDMA5_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA5_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA5_GFX_RB_WPTR_POLL_CNTL
>+#define SDMA5_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
>+#define SDMA5_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
>+#define SDMA5_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
>+#define SDMA5_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
>+#define SDMA5_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
>+#define SDMA5_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
>+#define SDMA5_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
>+#define SDMA5_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
>+#define SDMA5_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
>+#define SDMA5_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
>+//SDMA5_GFX_RB_RPTR_ADDR_HI
>+#define SDMA5_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
>+#define SDMA5_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
>+//SDMA5_GFX_RB_RPTR_ADDR_LO
>+#define SDMA5_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                        0x0
>+#define SDMA5_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
>+#define SDMA5_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                          0x00000001L
>+#define SDMA5_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
>+//SDMA5_GFX_IB_CNTL
>+#define SDMA5_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA5_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
>+#define SDMA5_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
>+#define SDMA5_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
>+#define SDMA5_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA5_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
>+#define SDMA5_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
>+#define SDMA5_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
>+//SDMA5_GFX_IB_RPTR
>+#define SDMA5_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
>+#define SDMA5_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
>+//SDMA5_GFX_IB_OFFSET
>+#define SDMA5_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
>+#define SDMA5_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
>+//SDMA5_GFX_IB_BASE_LO
>+#define SDMA5_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
>+#define SDMA5_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
>+//SDMA5_GFX_IB_BASE_HI
>+#define SDMA5_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA5_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_GFX_IB_SIZE
>+#define SDMA5_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
>+#define SDMA5_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
>+//SDMA5_GFX_SKIP_CNTL
>+#define SDMA5_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
>+#define SDMA5_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
>+//SDMA5_GFX_CONTEXT_STATUS
>+#define SDMA5_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
>+#define SDMA5_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
>+#define SDMA5_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
>+#define SDMA5_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
>+#define SDMA5_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
>+#define SDMA5_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
>+#define SDMA5_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
>+#define SDMA5_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
>+#define SDMA5_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
>+#define SDMA5_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
>+#define SDMA5_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
>+#define SDMA5_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
>+#define SDMA5_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
>+#define SDMA5_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
>+#define SDMA5_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
>+#define SDMA5_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
>+//SDMA5_GFX_DOORBELL
>+#define SDMA5_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
>+#define SDMA5_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
>+#define SDMA5_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
>+#define SDMA5_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
>+//SDMA5_GFX_CONTEXT_CNTL
>+#define SDMA5_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
>+#define SDMA5_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
>+//SDMA5_GFX_STATUS
>+#define SDMA5_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
>+#define SDMA5_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
>+#define SDMA5_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
>+#define SDMA5_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
>+//SDMA5_GFX_DOORBELL_LOG
>+#define SDMA5_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
>+#define SDMA5_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
>+#define SDMA5_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
>+#define SDMA5_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
>+//SDMA5_GFX_WATERMARK
>+#define SDMA5_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
>+#define SDMA5_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
>+#define SDMA5_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
>+#define SDMA5_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
>+//SDMA5_GFX_DOORBELL_OFFSET
>+#define SDMA5_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
>+#define SDMA5_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
>+//SDMA5_GFX_CSA_ADDR_LO
>+#define SDMA5_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
>+#define SDMA5_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
>+//SDMA5_GFX_CSA_ADDR_HI
>+#define SDMA5_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_GFX_IB_SUB_REMAIN
>+#define SDMA5_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
>+#define SDMA5_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x000FFFFFL
>+//SDMA5_GFX_PREEMPT
>+#define SDMA5_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
>+#define SDMA5_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
>+//SDMA5_GFX_DUMMY_REG
>+#define SDMA5_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
>+#define SDMA5_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_GFX_RB_WPTR_POLL_ADDR_HI
>+#define SDMA5_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
>+#define SDMA5_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
>+//SDMA5_GFX_RB_WPTR_POLL_ADDR_LO
>+#define SDMA5_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
>+#define SDMA5_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
>+//SDMA5_GFX_RB_AQL_CNTL
>+#define SDMA5_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
>+#define SDMA5_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
>+#define SDMA5_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
>+#define SDMA5_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
>+#define SDMA5_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
>+#define SDMA5_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
>+//SDMA5_GFX_MINOR_PTR_UPDATE
>+#define SDMA5_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
>+#define SDMA5_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
>+//SDMA5_GFX_MIDCMD_DATA0
>+#define SDMA5_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
>+#define SDMA5_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_GFX_MIDCMD_DATA1
>+#define SDMA5_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
>+#define SDMA5_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_GFX_MIDCMD_DATA2
>+#define SDMA5_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
>+#define SDMA5_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_GFX_MIDCMD_DATA3
>+#define SDMA5_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
>+#define SDMA5_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_GFX_MIDCMD_DATA4
>+#define SDMA5_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
>+#define SDMA5_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_GFX_MIDCMD_DATA5
>+#define SDMA5_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
>+#define SDMA5_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_GFX_MIDCMD_DATA6
>+#define SDMA5_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
>+#define SDMA5_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_GFX_MIDCMD_DATA7
>+#define SDMA5_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
>+#define SDMA5_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_GFX_MIDCMD_DATA8
>+#define SDMA5_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
>+#define SDMA5_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_GFX_MIDCMD_CNTL
>+#define SDMA5_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
>+#define SDMA5_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
>+#define SDMA5_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
>+#define SDMA5_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
>+#define SDMA5_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
>+#define SDMA5_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
>+#define SDMA5_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
>+#define SDMA5_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
>+//SDMA5_PAGE_RB_CNTL
>+#define SDMA5_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA5_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA5_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA5_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA5_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA5_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA5_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA5_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA5_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA5_PAGE_RB_BASE
>+#define SDMA5_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA5_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA5_PAGE_RB_BASE_HI
>+#define SDMA5_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA5_PAGE_RB_RPTR
>+#define SDMA5_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_PAGE_RB_RPTR_HI
>+#define SDMA5_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_PAGE_RB_WPTR
>+#define SDMA5_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_PAGE_RB_WPTR_HI
>+#define SDMA5_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_PAGE_RB_WPTR_POLL_CNTL
>+#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA5_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA5_PAGE_RB_RPTR_ADDR_HI
>+#define SDMA5_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA5_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA5_PAGE_RB_RPTR_ADDR_LO
>+#define SDMA5_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA5_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA5_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA5_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA5_PAGE_IB_CNTL
>+#define SDMA5_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA5_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA5_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA5_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA5_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA5_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA5_PAGE_IB_RPTR
>+#define SDMA5_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA5_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA5_PAGE_IB_OFFSET
>+#define SDMA5_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA5_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA5_PAGE_IB_BASE_LO
>+#define SDMA5_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA5_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA5_PAGE_IB_BASE_HI
>+#define SDMA5_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_PAGE_IB_SIZE
>+#define SDMA5_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA5_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA5_PAGE_SKIP_CNTL
>+#define SDMA5_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA5_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA5_PAGE_CONTEXT_STATUS
>+#define SDMA5_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA5_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA5_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA5_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA5_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA5_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA5_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA5_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA5_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA5_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA5_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA5_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA5_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA5_PAGE_DOORBELL
>+#define SDMA5_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA5_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA5_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA5_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA5_PAGE_STATUS
>+#define SDMA5_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA5_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA5_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA5_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA5_PAGE_DOORBELL_LOG
>+#define SDMA5_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA5_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA5_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA5_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA5_PAGE_WATERMARK
>+#define SDMA5_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA5_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA5_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA5_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA5_PAGE_DOORBELL_OFFSET
>+#define SDMA5_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA5_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA5_PAGE_CSA_ADDR_LO
>+#define SDMA5_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA5_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA5_PAGE_CSA_ADDR_HI
>+#define SDMA5_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA5_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA5_PAGE_IB_SUB_REMAIN
>+#define SDMA5_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA5_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA5_PAGE_PREEMPT
>+#define SDMA5_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA5_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA5_PAGE_DUMMY_REG
>+#define SDMA5_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA5_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_PAGE_RB_WPTR_POLL_ADDR_HI
>+#define SDMA5_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA5_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA5_PAGE_RB_WPTR_POLL_ADDR_LO
>+#define SDMA5_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA5_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA5_PAGE_RB_AQL_CNTL
>+#define SDMA5_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA5_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA5_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA5_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA5_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA5_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA5_PAGE_MINOR_PTR_UPDATE
>+#define SDMA5_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA5_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA5_PAGE_MIDCMD_DATA0
>+#define SDMA5_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA5_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_PAGE_MIDCMD_DATA1
>+#define SDMA5_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA5_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_PAGE_MIDCMD_DATA2
>+#define SDMA5_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA5_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_PAGE_MIDCMD_DATA3
>+#define SDMA5_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA5_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_PAGE_MIDCMD_DATA4
>+#define SDMA5_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA5_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_PAGE_MIDCMD_DATA5
>+#define SDMA5_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA5_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_PAGE_MIDCMD_DATA6
>+#define SDMA5_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA5_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_PAGE_MIDCMD_DATA7
>+#define SDMA5_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA5_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_PAGE_MIDCMD_DATA8
>+#define SDMA5_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA5_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_PAGE_MIDCMD_CNTL
>+#define SDMA5_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA5_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA5_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA5_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA5_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA5_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA5_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA5_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA5_RLC0_RB_CNTL
>+#define SDMA5_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA5_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA5_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA5_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA5_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA5_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA5_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA5_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA5_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA5_RLC0_RB_BASE
>+#define SDMA5_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA5_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA5_RLC0_RB_BASE_HI
>+#define SDMA5_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA5_RLC0_RB_RPTR
>+#define SDMA5_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC0_RB_RPTR_HI
>+#define SDMA5_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC0_RB_WPTR
>+#define SDMA5_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC0_RB_WPTR_HI
>+#define SDMA5_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC0_RB_WPTR_POLL_CNTL
>+#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA5_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA5_RLC0_RB_RPTR_ADDR_HI
>+#define SDMA5_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA5_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA5_RLC0_RB_RPTR_ADDR_LO
>+#define SDMA5_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA5_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA5_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA5_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA5_RLC0_IB_CNTL
>+#define SDMA5_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA5_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA5_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA5_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA5_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA5_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA5_RLC0_IB_RPTR
>+#define SDMA5_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA5_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA5_RLC0_IB_OFFSET
>+#define SDMA5_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA5_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA5_RLC0_IB_BASE_LO
>+#define SDMA5_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA5_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA5_RLC0_IB_BASE_HI
>+#define SDMA5_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC0_IB_SIZE
>+#define SDMA5_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA5_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA5_RLC0_SKIP_CNTL
>+#define SDMA5_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA5_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA5_RLC0_CONTEXT_STATUS
>+#define SDMA5_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA5_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA5_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA5_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA5_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA5_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA5_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA5_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA5_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA5_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA5_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA5_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA5_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA5_RLC0_DOORBELL
>+#define SDMA5_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA5_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA5_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA5_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA5_RLC0_STATUS
>+#define SDMA5_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA5_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA5_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA5_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA5_RLC0_DOORBELL_LOG
>+#define SDMA5_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA5_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA5_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA5_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA5_RLC0_WATERMARK
>+#define SDMA5_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA5_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA5_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA5_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA5_RLC0_DOORBELL_OFFSET
>+#define SDMA5_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA5_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA5_RLC0_CSA_ADDR_LO
>+#define SDMA5_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA5_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA5_RLC0_CSA_ADDR_HI
>+#define SDMA5_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA5_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA5_RLC0_IB_SUB_REMAIN
>+#define SDMA5_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA5_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA5_RLC0_PREEMPT
>+#define SDMA5_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA5_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA5_RLC0_DUMMY_REG
>+#define SDMA5_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA5_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC0_RB_WPTR_POLL_ADDR_HI
>+#define SDMA5_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA5_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA5_RLC0_RB_WPTR_POLL_ADDR_LO
>+#define SDMA5_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA5_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA5_RLC0_RB_AQL_CNTL
>+#define SDMA5_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA5_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA5_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA5_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA5_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA5_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA5_RLC0_MINOR_PTR_UPDATE
>+#define SDMA5_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA5_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA5_RLC0_MIDCMD_DATA0
>+#define SDMA5_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA5_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC0_MIDCMD_DATA1
>+#define SDMA5_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA5_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC0_MIDCMD_DATA2
>+#define SDMA5_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA5_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC0_MIDCMD_DATA3
>+#define SDMA5_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA5_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC0_MIDCMD_DATA4
>+#define SDMA5_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA5_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC0_MIDCMD_DATA5
>+#define SDMA5_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA5_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC0_MIDCMD_DATA6
>+#define SDMA5_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA5_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC0_MIDCMD_DATA7
>+#define SDMA5_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA5_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC0_MIDCMD_DATA8
>+#define SDMA5_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA5_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC0_MIDCMD_CNTL
>+#define SDMA5_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA5_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA5_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA5_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA5_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA5_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA5_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA5_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA5_RLC1_RB_CNTL
>+#define SDMA5_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA5_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA5_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA5_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA5_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA5_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA5_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA5_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA5_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA5_RLC1_RB_BASE
>+#define SDMA5_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA5_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA5_RLC1_RB_BASE_HI
>+#define SDMA5_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA5_RLC1_RB_RPTR
>+#define SDMA5_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC1_RB_RPTR_HI
>+#define SDMA5_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC1_RB_WPTR
>+#define SDMA5_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC1_RB_WPTR_HI
>+#define SDMA5_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC1_RB_WPTR_POLL_CNTL
>+#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA5_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA5_RLC1_RB_RPTR_ADDR_HI
>+#define SDMA5_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA5_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA5_RLC1_RB_RPTR_ADDR_LO
>+#define SDMA5_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA5_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA5_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA5_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA5_RLC1_IB_CNTL
>+#define SDMA5_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA5_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA5_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA5_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA5_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA5_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA5_RLC1_IB_RPTR
>+#define SDMA5_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA5_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA5_RLC1_IB_OFFSET
>+#define SDMA5_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA5_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA5_RLC1_IB_BASE_LO
>+#define SDMA5_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA5_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA5_RLC1_IB_BASE_HI
>+#define SDMA5_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC1_IB_SIZE
>+#define SDMA5_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA5_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA5_RLC1_SKIP_CNTL
>+#define SDMA5_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA5_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA5_RLC1_CONTEXT_STATUS
>+#define SDMA5_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA5_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA5_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA5_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA5_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA5_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA5_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA5_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA5_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA5_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA5_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA5_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA5_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA5_RLC1_DOORBELL
>+#define SDMA5_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA5_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA5_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA5_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA5_RLC1_STATUS
>+#define SDMA5_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA5_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA5_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA5_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA5_RLC1_DOORBELL_LOG
>+#define SDMA5_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA5_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA5_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA5_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA5_RLC1_WATERMARK
>+#define SDMA5_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA5_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA5_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA5_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA5_RLC1_DOORBELL_OFFSET
>+#define SDMA5_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA5_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA5_RLC1_CSA_ADDR_LO
>+#define SDMA5_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA5_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA5_RLC1_CSA_ADDR_HI
>+#define SDMA5_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA5_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA5_RLC1_IB_SUB_REMAIN
>+#define SDMA5_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA5_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA5_RLC1_PREEMPT
>+#define SDMA5_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA5_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA5_RLC1_DUMMY_REG
>+#define SDMA5_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA5_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC1_RB_WPTR_POLL_ADDR_HI
>+#define SDMA5_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA5_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA5_RLC1_RB_WPTR_POLL_ADDR_LO
>+#define SDMA5_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA5_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA5_RLC1_RB_AQL_CNTL
>+#define SDMA5_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA5_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA5_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA5_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA5_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA5_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA5_RLC1_MINOR_PTR_UPDATE
>+#define SDMA5_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA5_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA5_RLC1_MIDCMD_DATA0
>+#define SDMA5_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA5_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC1_MIDCMD_DATA1
>+#define SDMA5_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA5_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC1_MIDCMD_DATA2
>+#define SDMA5_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA5_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC1_MIDCMD_DATA3
>+#define SDMA5_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA5_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC1_MIDCMD_DATA4
>+#define SDMA5_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA5_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC1_MIDCMD_DATA5
>+#define SDMA5_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA5_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC1_MIDCMD_DATA6
>+#define SDMA5_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA5_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC1_MIDCMD_DATA7
>+#define SDMA5_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA5_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC1_MIDCMD_DATA8
>+#define SDMA5_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA5_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC1_MIDCMD_CNTL
>+#define SDMA5_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA5_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA5_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA5_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA5_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA5_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA5_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA5_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA5_RLC2_RB_CNTL
>+#define SDMA5_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA5_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA5_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA5_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA5_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA5_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA5_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA5_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA5_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA5_RLC2_RB_BASE
>+#define SDMA5_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA5_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA5_RLC2_RB_BASE_HI
>+#define SDMA5_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA5_RLC2_RB_RPTR
>+#define SDMA5_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC2_RB_RPTR_HI
>+#define SDMA5_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC2_RB_WPTR
>+#define SDMA5_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC2_RB_WPTR_HI
>+#define SDMA5_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC2_RB_WPTR_POLL_CNTL
>+#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA5_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA5_RLC2_RB_RPTR_ADDR_HI
>+#define SDMA5_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA5_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA5_RLC2_RB_RPTR_ADDR_LO
>+#define SDMA5_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA5_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA5_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA5_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA5_RLC2_IB_CNTL
>+#define SDMA5_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA5_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA5_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA5_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA5_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA5_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA5_RLC2_IB_RPTR
>+#define SDMA5_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA5_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA5_RLC2_IB_OFFSET
>+#define SDMA5_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA5_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA5_RLC2_IB_BASE_LO
>+#define SDMA5_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA5_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA5_RLC2_IB_BASE_HI
>+#define SDMA5_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC2_IB_SIZE
>+#define SDMA5_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA5_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA5_RLC2_SKIP_CNTL
>+#define SDMA5_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA5_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA5_RLC2_CONTEXT_STATUS
>+#define SDMA5_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA5_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA5_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA5_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA5_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA5_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA5_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA5_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA5_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA5_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA5_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA5_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA5_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA5_RLC2_DOORBELL
>+#define SDMA5_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA5_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA5_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA5_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA5_RLC2_STATUS
>+#define SDMA5_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA5_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA5_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA5_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA5_RLC2_DOORBELL_LOG
>+#define SDMA5_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA5_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA5_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA5_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA5_RLC2_WATERMARK
>+#define SDMA5_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA5_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA5_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA5_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA5_RLC2_DOORBELL_OFFSET
>+#define SDMA5_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA5_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA5_RLC2_CSA_ADDR_LO
>+#define SDMA5_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA5_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA5_RLC2_CSA_ADDR_HI
>+#define SDMA5_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA5_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA5_RLC2_IB_SUB_REMAIN
>+#define SDMA5_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA5_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA5_RLC2_PREEMPT
>+#define SDMA5_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA5_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA5_RLC2_DUMMY_REG
>+#define SDMA5_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA5_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC2_RB_WPTR_POLL_ADDR_HI
>+#define SDMA5_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA5_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA5_RLC2_RB_WPTR_POLL_ADDR_LO
>+#define SDMA5_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA5_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA5_RLC2_RB_AQL_CNTL
>+#define SDMA5_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA5_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA5_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA5_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA5_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA5_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA5_RLC2_MINOR_PTR_UPDATE
>+#define SDMA5_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA5_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA5_RLC2_MIDCMD_DATA0
>+#define SDMA5_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA5_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC2_MIDCMD_DATA1
>+#define SDMA5_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA5_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC2_MIDCMD_DATA2
>+#define SDMA5_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA5_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC2_MIDCMD_DATA3
>+#define SDMA5_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA5_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC2_MIDCMD_DATA4
>+#define SDMA5_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA5_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC2_MIDCMD_DATA5
>+#define SDMA5_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA5_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC2_MIDCMD_DATA6
>+#define SDMA5_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA5_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC2_MIDCMD_DATA7
>+#define SDMA5_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA5_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC2_MIDCMD_DATA8
>+#define SDMA5_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA5_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC2_MIDCMD_CNTL
>+#define SDMA5_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA5_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA5_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA5_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA5_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA5_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA5_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA5_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA5_RLC3_RB_CNTL
>+#define SDMA5_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA5_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA5_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA5_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA5_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA5_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA5_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA5_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA5_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA5_RLC3_RB_BASE
>+#define SDMA5_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA5_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA5_RLC3_RB_BASE_HI
>+#define SDMA5_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA5_RLC3_RB_RPTR
>+#define SDMA5_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC3_RB_RPTR_HI
>+#define SDMA5_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC3_RB_WPTR
>+#define SDMA5_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC3_RB_WPTR_HI
>+#define SDMA5_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC3_RB_WPTR_POLL_CNTL
>+#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA5_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA5_RLC3_RB_RPTR_ADDR_HI
>+#define SDMA5_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA5_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA5_RLC3_RB_RPTR_ADDR_LO
>+#define SDMA5_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA5_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA5_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA5_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA5_RLC3_IB_CNTL
>+#define SDMA5_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA5_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA5_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA5_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA5_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA5_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA5_RLC3_IB_RPTR
>+#define SDMA5_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA5_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA5_RLC3_IB_OFFSET
>+#define SDMA5_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA5_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA5_RLC3_IB_BASE_LO
>+#define SDMA5_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA5_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA5_RLC3_IB_BASE_HI
>+#define SDMA5_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC3_IB_SIZE
>+#define SDMA5_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA5_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA5_RLC3_SKIP_CNTL
>+#define SDMA5_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA5_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA5_RLC3_CONTEXT_STATUS
>+#define SDMA5_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA5_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA5_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA5_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA5_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA5_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA5_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA5_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA5_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA5_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA5_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA5_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA5_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA5_RLC3_DOORBELL
>+#define SDMA5_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA5_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA5_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA5_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA5_RLC3_STATUS
>+#define SDMA5_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA5_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA5_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA5_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA5_RLC3_DOORBELL_LOG
>+#define SDMA5_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA5_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA5_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA5_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA5_RLC3_WATERMARK
>+#define SDMA5_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA5_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA5_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA5_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA5_RLC3_DOORBELL_OFFSET
>+#define SDMA5_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA5_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA5_RLC3_CSA_ADDR_LO
>+#define SDMA5_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA5_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA5_RLC3_CSA_ADDR_HI
>+#define SDMA5_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA5_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA5_RLC3_IB_SUB_REMAIN
>+#define SDMA5_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA5_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA5_RLC3_PREEMPT
>+#define SDMA5_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA5_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA5_RLC3_DUMMY_REG
>+#define SDMA5_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA5_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC3_RB_WPTR_POLL_ADDR_HI
>+#define SDMA5_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA5_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA5_RLC3_RB_WPTR_POLL_ADDR_LO
>+#define SDMA5_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA5_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA5_RLC3_RB_AQL_CNTL
>+#define SDMA5_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA5_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA5_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA5_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA5_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA5_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA5_RLC3_MINOR_PTR_UPDATE
>+#define SDMA5_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA5_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA5_RLC3_MIDCMD_DATA0
>+#define SDMA5_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA5_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC3_MIDCMD_DATA1
>+#define SDMA5_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA5_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC3_MIDCMD_DATA2
>+#define SDMA5_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA5_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC3_MIDCMD_DATA3
>+#define SDMA5_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA5_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC3_MIDCMD_DATA4
>+#define SDMA5_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA5_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC3_MIDCMD_DATA5
>+#define SDMA5_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA5_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC3_MIDCMD_DATA6
>+#define SDMA5_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA5_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC3_MIDCMD_DATA7
>+#define SDMA5_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA5_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC3_MIDCMD_DATA8
>+#define SDMA5_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA5_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC3_MIDCMD_CNTL
>+#define SDMA5_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA5_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA5_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA5_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA5_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA5_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA5_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA5_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA5_RLC4_RB_CNTL
>+#define SDMA5_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA5_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA5_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA5_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA5_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA5_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA5_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA5_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA5_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA5_RLC4_RB_BASE
>+#define SDMA5_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA5_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA5_RLC4_RB_BASE_HI
>+#define SDMA5_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA5_RLC4_RB_RPTR
>+#define SDMA5_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC4_RB_RPTR_HI
>+#define SDMA5_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC4_RB_WPTR
>+#define SDMA5_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC4_RB_WPTR_HI
>+#define SDMA5_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC4_RB_WPTR_POLL_CNTL
>+#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA5_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA5_RLC4_RB_RPTR_ADDR_HI
>+#define SDMA5_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA5_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA5_RLC4_RB_RPTR_ADDR_LO
>+#define SDMA5_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA5_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA5_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA5_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA5_RLC4_IB_CNTL
>+#define SDMA5_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA5_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA5_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA5_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA5_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA5_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA5_RLC4_IB_RPTR
>+#define SDMA5_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA5_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA5_RLC4_IB_OFFSET
>+#define SDMA5_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA5_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA5_RLC4_IB_BASE_LO
>+#define SDMA5_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA5_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA5_RLC4_IB_BASE_HI
>+#define SDMA5_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC4_IB_SIZE
>+#define SDMA5_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA5_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA5_RLC4_SKIP_CNTL
>+#define SDMA5_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA5_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA5_RLC4_CONTEXT_STATUS
>+#define SDMA5_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA5_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA5_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA5_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA5_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA5_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA5_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA5_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA5_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA5_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA5_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA5_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA5_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA5_RLC4_DOORBELL
>+#define SDMA5_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA5_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA5_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA5_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA5_RLC4_STATUS
>+#define SDMA5_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA5_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA5_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA5_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA5_RLC4_DOORBELL_LOG
>+#define SDMA5_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA5_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA5_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA5_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA5_RLC4_WATERMARK
>+#define SDMA5_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA5_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA5_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA5_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA5_RLC4_DOORBELL_OFFSET
>+#define SDMA5_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA5_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA5_RLC4_CSA_ADDR_LO
>+#define SDMA5_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA5_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA5_RLC4_CSA_ADDR_HI
>+#define SDMA5_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA5_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA5_RLC4_IB_SUB_REMAIN
>+#define SDMA5_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA5_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA5_RLC4_PREEMPT
>+#define SDMA5_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA5_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA5_RLC4_DUMMY_REG
>+#define SDMA5_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA5_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC4_RB_WPTR_POLL_ADDR_HI
>+#define SDMA5_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA5_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA5_RLC4_RB_WPTR_POLL_ADDR_LO
>+#define SDMA5_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA5_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA5_RLC4_RB_AQL_CNTL
>+#define SDMA5_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA5_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA5_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA5_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA5_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA5_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA5_RLC4_MINOR_PTR_UPDATE
>+#define SDMA5_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA5_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA5_RLC4_MIDCMD_DATA0
>+#define SDMA5_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA5_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC4_MIDCMD_DATA1
>+#define SDMA5_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA5_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC4_MIDCMD_DATA2
>+#define SDMA5_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA5_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC4_MIDCMD_DATA3
>+#define SDMA5_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA5_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC4_MIDCMD_DATA4
>+#define SDMA5_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA5_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC4_MIDCMD_DATA5
>+#define SDMA5_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA5_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC4_MIDCMD_DATA6
>+#define SDMA5_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA5_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC4_MIDCMD_DATA7
>+#define SDMA5_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA5_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC4_MIDCMD_DATA8
>+#define SDMA5_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA5_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC4_MIDCMD_CNTL
>+#define SDMA5_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA5_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA5_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA5_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA5_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA5_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA5_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA5_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA5_RLC5_RB_CNTL
>+#define SDMA5_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA5_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA5_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA5_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA5_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA5_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA5_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA5_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA5_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA5_RLC5_RB_BASE
>+#define SDMA5_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA5_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA5_RLC5_RB_BASE_HI
>+#define SDMA5_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA5_RLC5_RB_RPTR
>+#define SDMA5_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC5_RB_RPTR_HI
>+#define SDMA5_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC5_RB_WPTR
>+#define SDMA5_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC5_RB_WPTR_HI
>+#define SDMA5_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC5_RB_WPTR_POLL_CNTL
>+#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA5_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA5_RLC5_RB_RPTR_ADDR_HI
>+#define SDMA5_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA5_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA5_RLC5_RB_RPTR_ADDR_LO
>+#define SDMA5_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA5_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA5_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA5_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA5_RLC5_IB_CNTL
>+#define SDMA5_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA5_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA5_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA5_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA5_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA5_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA5_RLC5_IB_RPTR
>+#define SDMA5_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA5_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA5_RLC5_IB_OFFSET
>+#define SDMA5_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA5_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA5_RLC5_IB_BASE_LO
>+#define SDMA5_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA5_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA5_RLC5_IB_BASE_HI
>+#define SDMA5_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC5_IB_SIZE
>+#define SDMA5_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA5_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA5_RLC5_SKIP_CNTL
>+#define SDMA5_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA5_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA5_RLC5_CONTEXT_STATUS
>+#define SDMA5_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA5_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA5_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA5_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA5_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA5_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA5_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA5_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA5_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA5_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA5_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA5_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA5_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA5_RLC5_DOORBELL
>+#define SDMA5_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA5_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA5_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA5_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA5_RLC5_STATUS
>+#define SDMA5_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA5_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA5_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA5_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA5_RLC5_DOORBELL_LOG
>+#define SDMA5_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA5_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA5_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA5_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA5_RLC5_WATERMARK
>+#define SDMA5_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA5_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA5_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA5_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA5_RLC5_DOORBELL_OFFSET
>+#define SDMA5_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA5_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA5_RLC5_CSA_ADDR_LO
>+#define SDMA5_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA5_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA5_RLC5_CSA_ADDR_HI
>+#define SDMA5_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA5_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA5_RLC5_IB_SUB_REMAIN
>+#define SDMA5_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA5_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA5_RLC5_PREEMPT
>+#define SDMA5_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA5_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA5_RLC5_DUMMY_REG
>+#define SDMA5_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA5_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC5_RB_WPTR_POLL_ADDR_HI
>+#define SDMA5_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA5_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA5_RLC5_RB_WPTR_POLL_ADDR_LO
>+#define SDMA5_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA5_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA5_RLC5_RB_AQL_CNTL
>+#define SDMA5_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA5_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA5_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA5_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA5_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA5_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA5_RLC5_MINOR_PTR_UPDATE
>+#define SDMA5_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA5_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA5_RLC5_MIDCMD_DATA0
>+#define SDMA5_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA5_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC5_MIDCMD_DATA1
>+#define SDMA5_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA5_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC5_MIDCMD_DATA2
>+#define SDMA5_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA5_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC5_MIDCMD_DATA3
>+#define SDMA5_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA5_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC5_MIDCMD_DATA4
>+#define SDMA5_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA5_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC5_MIDCMD_DATA5
>+#define SDMA5_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA5_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC5_MIDCMD_DATA6
>+#define SDMA5_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA5_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC5_MIDCMD_DATA7
>+#define SDMA5_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA5_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC5_MIDCMD_DATA8
>+#define SDMA5_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA5_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC5_MIDCMD_CNTL
>+#define SDMA5_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA5_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA5_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA5_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA5_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA5_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA5_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA5_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA5_RLC6_RB_CNTL
>+#define SDMA5_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA5_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA5_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA5_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA5_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA5_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA5_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA5_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA5_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA5_RLC6_RB_BASE
>+#define SDMA5_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA5_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA5_RLC6_RB_BASE_HI
>+#define SDMA5_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA5_RLC6_RB_RPTR
>+#define SDMA5_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC6_RB_RPTR_HI
>+#define SDMA5_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC6_RB_WPTR
>+#define SDMA5_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC6_RB_WPTR_HI
>+#define SDMA5_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC6_RB_WPTR_POLL_CNTL
>+#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA5_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA5_RLC6_RB_RPTR_ADDR_HI
>+#define SDMA5_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA5_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA5_RLC6_RB_RPTR_ADDR_LO
>+#define SDMA5_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA5_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA5_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA5_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA5_RLC6_IB_CNTL
>+#define SDMA5_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA5_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA5_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA5_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA5_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA5_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA5_RLC6_IB_RPTR
>+#define SDMA5_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA5_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA5_RLC6_IB_OFFSET
>+#define SDMA5_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA5_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA5_RLC6_IB_BASE_LO
>+#define SDMA5_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA5_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA5_RLC6_IB_BASE_HI
>+#define SDMA5_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC6_IB_SIZE
>+#define SDMA5_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA5_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA5_RLC6_SKIP_CNTL
>+#define SDMA5_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA5_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA5_RLC6_CONTEXT_STATUS
>+#define SDMA5_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA5_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA5_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA5_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA5_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA5_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA5_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA5_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA5_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA5_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA5_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA5_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA5_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA5_RLC6_DOORBELL
>+#define SDMA5_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA5_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA5_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA5_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA5_RLC6_STATUS
>+#define SDMA5_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA5_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA5_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA5_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA5_RLC6_DOORBELL_LOG
>+#define SDMA5_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA5_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA5_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA5_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA5_RLC6_WATERMARK
>+#define SDMA5_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA5_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA5_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA5_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA5_RLC6_DOORBELL_OFFSET
>+#define SDMA5_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA5_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA5_RLC6_CSA_ADDR_LO
>+#define SDMA5_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA5_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA5_RLC6_CSA_ADDR_HI
>+#define SDMA5_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA5_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA5_RLC6_IB_SUB_REMAIN
>+#define SDMA5_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA5_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA5_RLC6_PREEMPT
>+#define SDMA5_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA5_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA5_RLC6_DUMMY_REG
>+#define SDMA5_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA5_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC6_RB_WPTR_POLL_ADDR_HI
>+#define SDMA5_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA5_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA5_RLC6_RB_WPTR_POLL_ADDR_LO
>+#define SDMA5_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA5_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA5_RLC6_RB_AQL_CNTL
>+#define SDMA5_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA5_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA5_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA5_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA5_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA5_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA5_RLC6_MINOR_PTR_UPDATE
>+#define SDMA5_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA5_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA5_RLC6_MIDCMD_DATA0
>+#define SDMA5_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA5_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC6_MIDCMD_DATA1
>+#define SDMA5_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA5_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC6_MIDCMD_DATA2
>+#define SDMA5_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA5_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC6_MIDCMD_DATA3
>+#define SDMA5_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA5_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC6_MIDCMD_DATA4
>+#define SDMA5_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA5_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC6_MIDCMD_DATA5
>+#define SDMA5_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA5_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC6_MIDCMD_DATA6
>+#define SDMA5_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA5_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC6_MIDCMD_DATA7
>+#define SDMA5_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA5_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC6_MIDCMD_DATA8
>+#define SDMA5_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA5_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC6_MIDCMD_CNTL
>+#define SDMA5_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA5_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA5_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA5_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA5_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA5_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA5_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA5_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA5_RLC7_RB_CNTL
>+#define SDMA5_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA5_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA5_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA5_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA5_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA5_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA5_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA5_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA5_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA5_RLC7_RB_BASE
>+#define SDMA5_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA5_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA5_RLC7_RB_BASE_HI
>+#define SDMA5_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA5_RLC7_RB_RPTR
>+#define SDMA5_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC7_RB_RPTR_HI
>+#define SDMA5_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC7_RB_WPTR
>+#define SDMA5_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA5_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA5_RLC7_RB_WPTR_HI
>+#define SDMA5_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA5_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA5_RLC7_RB_WPTR_POLL_CNTL
>+#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA5_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA5_RLC7_RB_RPTR_ADDR_HI
>+#define SDMA5_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA5_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA5_RLC7_RB_RPTR_ADDR_LO
>+#define SDMA5_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA5_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA5_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA5_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA5_RLC7_IB_CNTL
>+#define SDMA5_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA5_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA5_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA5_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA5_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA5_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA5_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA5_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA5_RLC7_IB_RPTR
>+#define SDMA5_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA5_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA5_RLC7_IB_OFFSET
>+#define SDMA5_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA5_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA5_RLC7_IB_BASE_LO
>+#define SDMA5_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA5_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA5_RLC7_IB_BASE_HI
>+#define SDMA5_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA5_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC7_IB_SIZE
>+#define SDMA5_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA5_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA5_RLC7_SKIP_CNTL
>+#define SDMA5_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA5_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA5_RLC7_CONTEXT_STATUS
>+#define SDMA5_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA5_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA5_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA5_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA5_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA5_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA5_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA5_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA5_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA5_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA5_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA5_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA5_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA5_RLC7_DOORBELL
>+#define SDMA5_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA5_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA5_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA5_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA5_RLC7_STATUS
>+#define SDMA5_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA5_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA5_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA5_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA5_RLC7_DOORBELL_LOG
>+#define SDMA5_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA5_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA5_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA5_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA5_RLC7_WATERMARK
>+#define SDMA5_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA5_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA5_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA5_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA5_RLC7_DOORBELL_OFFSET
>+#define SDMA5_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA5_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA5_RLC7_CSA_ADDR_LO
>+#define SDMA5_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA5_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA5_RLC7_CSA_ADDR_HI
>+#define SDMA5_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA5_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA5_RLC7_IB_SUB_REMAIN
>+#define SDMA5_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA5_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA5_RLC7_PREEMPT
>+#define SDMA5_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA5_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA5_RLC7_DUMMY_REG
>+#define SDMA5_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA5_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA5_RLC7_RB_WPTR_POLL_ADDR_HI
>+#define SDMA5_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA5_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA5_RLC7_RB_WPTR_POLL_ADDR_LO
>+#define SDMA5_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA5_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA5_RLC7_RB_AQL_CNTL
>+#define SDMA5_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA5_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA5_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA5_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA5_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA5_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA5_RLC7_MINOR_PTR_UPDATE
>+#define SDMA5_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA5_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA5_RLC7_MIDCMD_DATA0
>+#define SDMA5_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA5_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC7_MIDCMD_DATA1
>+#define SDMA5_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA5_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC7_MIDCMD_DATA2
>+#define SDMA5_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA5_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC7_MIDCMD_DATA3
>+#define SDMA5_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA5_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC7_MIDCMD_DATA4
>+#define SDMA5_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA5_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC7_MIDCMD_DATA5
>+#define SDMA5_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA5_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC7_MIDCMD_DATA6
>+#define SDMA5_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA5_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC7_MIDCMD_DATA7
>+#define SDMA5_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA5_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC7_MIDCMD_DATA8
>+#define SDMA5_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA5_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA5_RLC7_MIDCMD_CNTL
>+#define SDMA5_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA5_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA5_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA5_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA5_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA5_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA5_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA5_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_offset.h	2019-08-31 15:01:11.933736175 -0500
>@@ -0,0 +1,1043 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma6_4_2_2_OFFSET_HEADER
>+#define _sdma6_4_2_2_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: sdma6_sdma6dec
>+// base address: 0x7c000
>+#define mmSDMA6_UCODE_ADDR                                                                             0x0000
>+#define mmSDMA6_UCODE_ADDR_BASE_IDX                                                                    1
>+#define mmSDMA6_UCODE_DATA                                                                             0x0001
>+#define mmSDMA6_UCODE_DATA_BASE_IDX                                                                    1
>+#define mmSDMA6_VM_CNTL                                                                                0x0004
>+#define mmSDMA6_VM_CNTL_BASE_IDX                                                                       1
>+#define mmSDMA6_VM_CTX_LO                                                                              0x0005
>+#define mmSDMA6_VM_CTX_LO_BASE_IDX                                                                     1
>+#define mmSDMA6_VM_CTX_HI                                                                              0x0006
>+#define mmSDMA6_VM_CTX_HI_BASE_IDX                                                                     1
>+#define mmSDMA6_ACTIVE_FCN_ID                                                                          0x0007
>+#define mmSDMA6_ACTIVE_FCN_ID_BASE_IDX                                                                 1
>+#define mmSDMA6_VM_CTX_CNTL                                                                            0x0008
>+#define mmSDMA6_VM_CTX_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA6_VIRT_RESET_REQ                                                                         0x0009
>+#define mmSDMA6_VIRT_RESET_REQ_BASE_IDX                                                                1
>+#define mmSDMA6_VF_ENABLE                                                                              0x000a
>+#define mmSDMA6_VF_ENABLE_BASE_IDX                                                                     1
>+#define mmSDMA6_CONTEXT_REG_TYPE0                                                                      0x000b
>+#define mmSDMA6_CONTEXT_REG_TYPE0_BASE_IDX                                                             1
>+#define mmSDMA6_CONTEXT_REG_TYPE1                                                                      0x000c
>+#define mmSDMA6_CONTEXT_REG_TYPE1_BASE_IDX                                                             1
>+#define mmSDMA6_CONTEXT_REG_TYPE2                                                                      0x000d
>+#define mmSDMA6_CONTEXT_REG_TYPE2_BASE_IDX                                                             1
>+#define mmSDMA6_CONTEXT_REG_TYPE3                                                                      0x000e
>+#define mmSDMA6_CONTEXT_REG_TYPE3_BASE_IDX                                                             1
>+#define mmSDMA6_PUB_REG_TYPE0                                                                          0x000f
>+#define mmSDMA6_PUB_REG_TYPE0_BASE_IDX                                                                 1
>+#define mmSDMA6_PUB_REG_TYPE1                                                                          0x0010
>+#define mmSDMA6_PUB_REG_TYPE1_BASE_IDX                                                                 1
>+#define mmSDMA6_PUB_REG_TYPE2                                                                          0x0011
>+#define mmSDMA6_PUB_REG_TYPE2_BASE_IDX                                                                 1
>+#define mmSDMA6_PUB_REG_TYPE3                                                                          0x0012
>+#define mmSDMA6_PUB_REG_TYPE3_BASE_IDX                                                                 1
>+#define mmSDMA6_MMHUB_CNTL                                                                             0x0013
>+#define mmSDMA6_MMHUB_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA6_CONTEXT_GROUP_BOUNDARY                                                                 0x0019
>+#define mmSDMA6_CONTEXT_GROUP_BOUNDARY_BASE_IDX                                                        1
>+#define mmSDMA6_POWER_CNTL                                                                             0x001a
>+#define mmSDMA6_POWER_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA6_CLK_CTRL                                                                               0x001b
>+#define mmSDMA6_CLK_CTRL_BASE_IDX                                                                      1
>+#define mmSDMA6_CNTL                                                                                   0x001c
>+#define mmSDMA6_CNTL_BASE_IDX                                                                          1
>+#define mmSDMA6_CHICKEN_BITS                                                                           0x001d
>+#define mmSDMA6_CHICKEN_BITS_BASE_IDX                                                                  1
>+#define mmSDMA6_GB_ADDR_CONFIG                                                                         0x001e
>+#define mmSDMA6_GB_ADDR_CONFIG_BASE_IDX                                                                1
>+#define mmSDMA6_GB_ADDR_CONFIG_READ                                                                    0x001f
>+#define mmSDMA6_GB_ADDR_CONFIG_READ_BASE_IDX                                                           1
>+#define mmSDMA6_RB_RPTR_FETCH_HI                                                                       0x0020
>+#define mmSDMA6_RB_RPTR_FETCH_HI_BASE_IDX                                                              1
>+#define mmSDMA6_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0021
>+#define mmSDMA6_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      1
>+#define mmSDMA6_RB_RPTR_FETCH                                                                          0x0022
>+#define mmSDMA6_RB_RPTR_FETCH_BASE_IDX                                                                 1
>+#define mmSDMA6_IB_OFFSET_FETCH                                                                        0x0023
>+#define mmSDMA6_IB_OFFSET_FETCH_BASE_IDX                                                               1
>+#define mmSDMA6_PROGRAM                                                                                0x0024
>+#define mmSDMA6_PROGRAM_BASE_IDX                                                                       1
>+#define mmSDMA6_STATUS_REG                                                                             0x0025
>+#define mmSDMA6_STATUS_REG_BASE_IDX                                                                    1
>+#define mmSDMA6_STATUS1_REG                                                                            0x0026
>+#define mmSDMA6_STATUS1_REG_BASE_IDX                                                                   1
>+#define mmSDMA6_RD_BURST_CNTL                                                                          0x0027
>+#define mmSDMA6_RD_BURST_CNTL_BASE_IDX                                                                 1
>+#define mmSDMA6_HBM_PAGE_CONFIG                                                                        0x0028
>+#define mmSDMA6_HBM_PAGE_CONFIG_BASE_IDX                                                               1
>+#define mmSDMA6_UCODE_CHECKSUM                                                                         0x0029
>+#define mmSDMA6_UCODE_CHECKSUM_BASE_IDX                                                                1
>+#define mmSDMA6_F32_CNTL                                                                               0x002a
>+#define mmSDMA6_F32_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA6_FREEZE                                                                                 0x002b
>+#define mmSDMA6_FREEZE_BASE_IDX                                                                        1
>+#define mmSDMA6_PHASE0_QUANTUM                                                                         0x002c
>+#define mmSDMA6_PHASE0_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA6_PHASE1_QUANTUM                                                                         0x002d
>+#define mmSDMA6_PHASE1_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA6_EDC_CONFIG                                                                             0x0032
>+#define mmSDMA6_EDC_CONFIG_BASE_IDX                                                                    1
>+#define mmSDMA6_BA_THRESHOLD                                                                           0x0033
>+#define mmSDMA6_BA_THRESHOLD_BASE_IDX                                                                  1
>+#define mmSDMA6_ID                                                                                     0x0034
>+#define mmSDMA6_ID_BASE_IDX                                                                            1
>+#define mmSDMA6_VERSION                                                                                0x0035
>+#define mmSDMA6_VERSION_BASE_IDX                                                                       1
>+#define mmSDMA6_EDC_COUNTER                                                                            0x0036
>+#define mmSDMA6_EDC_COUNTER_BASE_IDX                                                                   1
>+#define mmSDMA6_EDC_COUNTER_CLEAR                                                                      0x0037
>+#define mmSDMA6_EDC_COUNTER_CLEAR_BASE_IDX                                                             1
>+#define mmSDMA6_STATUS2_REG                                                                            0x0038
>+#define mmSDMA6_STATUS2_REG_BASE_IDX                                                                   1
>+#define mmSDMA6_ATOMIC_CNTL                                                                            0x0039
>+#define mmSDMA6_ATOMIC_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA6_ATOMIC_PREOP_LO                                                                        0x003a
>+#define mmSDMA6_ATOMIC_PREOP_LO_BASE_IDX                                                               1
>+#define mmSDMA6_ATOMIC_PREOP_HI                                                                        0x003b
>+#define mmSDMA6_ATOMIC_PREOP_HI_BASE_IDX                                                               1
>+#define mmSDMA6_UTCL1_CNTL                                                                             0x003c
>+#define mmSDMA6_UTCL1_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA6_UTCL1_WATERMK                                                                          0x003d
>+#define mmSDMA6_UTCL1_WATERMK_BASE_IDX                                                                 1
>+#define mmSDMA6_UTCL1_RD_STATUS                                                                        0x003e
>+#define mmSDMA6_UTCL1_RD_STATUS_BASE_IDX                                                               1
>+#define mmSDMA6_UTCL1_WR_STATUS                                                                        0x003f
>+#define mmSDMA6_UTCL1_WR_STATUS_BASE_IDX                                                               1
>+#define mmSDMA6_UTCL1_INV0                                                                             0x0040
>+#define mmSDMA6_UTCL1_INV0_BASE_IDX                                                                    1
>+#define mmSDMA6_UTCL1_INV1                                                                             0x0041
>+#define mmSDMA6_UTCL1_INV1_BASE_IDX                                                                    1
>+#define mmSDMA6_UTCL1_INV2                                                                             0x0042
>+#define mmSDMA6_UTCL1_INV2_BASE_IDX                                                                    1
>+#define mmSDMA6_UTCL1_RD_XNACK0                                                                        0x0043
>+#define mmSDMA6_UTCL1_RD_XNACK0_BASE_IDX                                                               1
>+#define mmSDMA6_UTCL1_RD_XNACK1                                                                        0x0044
>+#define mmSDMA6_UTCL1_RD_XNACK1_BASE_IDX                                                               1
>+#define mmSDMA6_UTCL1_WR_XNACK0                                                                        0x0045
>+#define mmSDMA6_UTCL1_WR_XNACK0_BASE_IDX                                                               1
>+#define mmSDMA6_UTCL1_WR_XNACK1                                                                        0x0046
>+#define mmSDMA6_UTCL1_WR_XNACK1_BASE_IDX                                                               1
>+#define mmSDMA6_UTCL1_TIMEOUT                                                                          0x0047
>+#define mmSDMA6_UTCL1_TIMEOUT_BASE_IDX                                                                 1
>+#define mmSDMA6_UTCL1_PAGE                                                                             0x0048
>+#define mmSDMA6_UTCL1_PAGE_BASE_IDX                                                                    1
>+#define mmSDMA6_POWER_CNTL_IDLE                                                                        0x0049
>+#define mmSDMA6_POWER_CNTL_IDLE_BASE_IDX                                                               1
>+#define mmSDMA6_RELAX_ORDERING_LUT                                                                     0x004a
>+#define mmSDMA6_RELAX_ORDERING_LUT_BASE_IDX                                                            1
>+#define mmSDMA6_CHICKEN_BITS_2                                                                         0x004b
>+#define mmSDMA6_CHICKEN_BITS_2_BASE_IDX                                                                1
>+#define mmSDMA6_STATUS3_REG                                                                            0x004c
>+#define mmSDMA6_STATUS3_REG_BASE_IDX                                                                   1
>+#define mmSDMA6_PHYSICAL_ADDR_LO                                                                       0x004d
>+#define mmSDMA6_PHYSICAL_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA6_PHYSICAL_ADDR_HI                                                                       0x004e
>+#define mmSDMA6_PHYSICAL_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA6_PHASE2_QUANTUM                                                                         0x004f
>+#define mmSDMA6_PHASE2_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA6_ERROR_LOG                                                                              0x0050
>+#define mmSDMA6_ERROR_LOG_BASE_IDX                                                                     1
>+#define mmSDMA6_PUB_DUMMY_REG0                                                                         0x0051
>+#define mmSDMA6_PUB_DUMMY_REG0_BASE_IDX                                                                1
>+#define mmSDMA6_PUB_DUMMY_REG1                                                                         0x0052
>+#define mmSDMA6_PUB_DUMMY_REG1_BASE_IDX                                                                1
>+#define mmSDMA6_PUB_DUMMY_REG2                                                                         0x0053
>+#define mmSDMA6_PUB_DUMMY_REG2_BASE_IDX                                                                1
>+#define mmSDMA6_PUB_DUMMY_REG3                                                                         0x0054
>+#define mmSDMA6_PUB_DUMMY_REG3_BASE_IDX                                                                1
>+#define mmSDMA6_F32_COUNTER                                                                            0x0055
>+#define mmSDMA6_F32_COUNTER_BASE_IDX                                                                   1
>+#define mmSDMA6_UNBREAKABLE                                                                            0x0056
>+#define mmSDMA6_UNBREAKABLE_BASE_IDX                                                                   1
>+#define mmSDMA6_PERFMON_CNTL                                                                           0x0057
>+#define mmSDMA6_PERFMON_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_PERFCOUNTER0_RESULT                                                                    0x0058
>+#define mmSDMA6_PERFCOUNTER0_RESULT_BASE_IDX                                                           1
>+#define mmSDMA6_PERFCOUNTER1_RESULT                                                                    0x0059
>+#define mmSDMA6_PERFCOUNTER1_RESULT_BASE_IDX                                                           1
>+#define mmSDMA6_PERFCOUNTER_TAG_DELAY_RANGE                                                            0x005a
>+#define mmSDMA6_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX                                                   1
>+#define mmSDMA6_CRD_CNTL                                                                               0x005b
>+#define mmSDMA6_CRD_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA6_GPU_IOV_VIOLATION_LOG                                                                  0x005d
>+#define mmSDMA6_GPU_IOV_VIOLATION_LOG_BASE_IDX                                                         1
>+#define mmSDMA6_ULV_CNTL                                                                               0x005e
>+#define mmSDMA6_ULV_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA6_EA_DBIT_ADDR_DATA                                                                      0x0060
>+#define mmSDMA6_EA_DBIT_ADDR_DATA_BASE_IDX                                                             1
>+#define mmSDMA6_EA_DBIT_ADDR_INDEX                                                                     0x0061
>+#define mmSDMA6_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            1
>+#define mmSDMA6_GPU_IOV_VIOLATION_LOG2                                                                 0x0062
>+#define mmSDMA6_GPU_IOV_VIOLATION_LOG2_BASE_IDX                                                        1
>+#define mmSDMA6_GFX_RB_CNTL                                                                            0x0080
>+#define mmSDMA6_GFX_RB_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA6_GFX_RB_BASE                                                                            0x0081
>+#define mmSDMA6_GFX_RB_BASE_BASE_IDX                                                                   1
>+#define mmSDMA6_GFX_RB_BASE_HI                                                                         0x0082
>+#define mmSDMA6_GFX_RB_BASE_HI_BASE_IDX                                                                1
>+#define mmSDMA6_GFX_RB_RPTR                                                                            0x0083
>+#define mmSDMA6_GFX_RB_RPTR_BASE_IDX                                                                   1
>+#define mmSDMA6_GFX_RB_RPTR_HI                                                                         0x0084
>+#define mmSDMA6_GFX_RB_RPTR_HI_BASE_IDX                                                                1
>+#define mmSDMA6_GFX_RB_WPTR                                                                            0x0085
>+#define mmSDMA6_GFX_RB_WPTR_BASE_IDX                                                                   1
>+#define mmSDMA6_GFX_RB_WPTR_HI                                                                         0x0086
>+#define mmSDMA6_GFX_RB_WPTR_HI_BASE_IDX                                                                1
>+#define mmSDMA6_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
>+#define mmSDMA6_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         1
>+#define mmSDMA6_GFX_RB_RPTR_ADDR_HI                                                                    0x0088
>+#define mmSDMA6_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           1
>+#define mmSDMA6_GFX_RB_RPTR_ADDR_LO                                                                    0x0089
>+#define mmSDMA6_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           1
>+#define mmSDMA6_GFX_IB_CNTL                                                                            0x008a
>+#define mmSDMA6_GFX_IB_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA6_GFX_IB_RPTR                                                                            0x008b
>+#define mmSDMA6_GFX_IB_RPTR_BASE_IDX                                                                   1
>+#define mmSDMA6_GFX_IB_OFFSET                                                                          0x008c
>+#define mmSDMA6_GFX_IB_OFFSET_BASE_IDX                                                                 1
>+#define mmSDMA6_GFX_IB_BASE_LO                                                                         0x008d
>+#define mmSDMA6_GFX_IB_BASE_LO_BASE_IDX                                                                1
>+#define mmSDMA6_GFX_IB_BASE_HI                                                                         0x008e
>+#define mmSDMA6_GFX_IB_BASE_HI_BASE_IDX                                                                1
>+#define mmSDMA6_GFX_IB_SIZE                                                                            0x008f
>+#define mmSDMA6_GFX_IB_SIZE_BASE_IDX                                                                   1
>+#define mmSDMA6_GFX_SKIP_CNTL                                                                          0x0090
>+#define mmSDMA6_GFX_SKIP_CNTL_BASE_IDX                                                                 1
>+#define mmSDMA6_GFX_CONTEXT_STATUS                                                                     0x0091
>+#define mmSDMA6_GFX_CONTEXT_STATUS_BASE_IDX                                                            1
>+#define mmSDMA6_GFX_DOORBELL                                                                           0x0092
>+#define mmSDMA6_GFX_DOORBELL_BASE_IDX                                                                  1
>+#define mmSDMA6_GFX_CONTEXT_CNTL                                                                       0x0093
>+#define mmSDMA6_GFX_CONTEXT_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_GFX_STATUS                                                                             0x00a8
>+#define mmSDMA6_GFX_STATUS_BASE_IDX                                                                    1
>+#define mmSDMA6_GFX_DOORBELL_LOG                                                                       0x00a9
>+#define mmSDMA6_GFX_DOORBELL_LOG_BASE_IDX                                                              1
>+#define mmSDMA6_GFX_WATERMARK                                                                          0x00aa
>+#define mmSDMA6_GFX_WATERMARK_BASE_IDX                                                                 1
>+#define mmSDMA6_GFX_DOORBELL_OFFSET                                                                    0x00ab
>+#define mmSDMA6_GFX_DOORBELL_OFFSET_BASE_IDX                                                           1
>+#define mmSDMA6_GFX_CSA_ADDR_LO                                                                        0x00ac
>+#define mmSDMA6_GFX_CSA_ADDR_LO_BASE_IDX                                                               1
>+#define mmSDMA6_GFX_CSA_ADDR_HI                                                                        0x00ad
>+#define mmSDMA6_GFX_CSA_ADDR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_GFX_IB_SUB_REMAIN                                                                      0x00af
>+#define mmSDMA6_GFX_IB_SUB_REMAIN_BASE_IDX                                                             1
>+#define mmSDMA6_GFX_PREEMPT                                                                            0x00b0
>+#define mmSDMA6_GFX_PREEMPT_BASE_IDX                                                                   1
>+#define mmSDMA6_GFX_DUMMY_REG                                                                          0x00b1
>+#define mmSDMA6_GFX_DUMMY_REG_BASE_IDX                                                                 1
>+#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x00b2
>+#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      1
>+#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x00b3
>+#define mmSDMA6_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      1
>+#define mmSDMA6_GFX_RB_AQL_CNTL                                                                        0x00b4
>+#define mmSDMA6_GFX_RB_AQL_CNTL_BASE_IDX                                                               1
>+#define mmSDMA6_GFX_MINOR_PTR_UPDATE                                                                   0x00b5
>+#define mmSDMA6_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          1
>+#define mmSDMA6_GFX_MIDCMD_DATA0                                                                       0x00c0
>+#define mmSDMA6_GFX_MIDCMD_DATA0_BASE_IDX                                                              1
>+#define mmSDMA6_GFX_MIDCMD_DATA1                                                                       0x00c1
>+#define mmSDMA6_GFX_MIDCMD_DATA1_BASE_IDX                                                              1
>+#define mmSDMA6_GFX_MIDCMD_DATA2                                                                       0x00c2
>+#define mmSDMA6_GFX_MIDCMD_DATA2_BASE_IDX                                                              1
>+#define mmSDMA6_GFX_MIDCMD_DATA3                                                                       0x00c3
>+#define mmSDMA6_GFX_MIDCMD_DATA3_BASE_IDX                                                              1
>+#define mmSDMA6_GFX_MIDCMD_DATA4                                                                       0x00c4
>+#define mmSDMA6_GFX_MIDCMD_DATA4_BASE_IDX                                                              1
>+#define mmSDMA6_GFX_MIDCMD_DATA5                                                                       0x00c5
>+#define mmSDMA6_GFX_MIDCMD_DATA5_BASE_IDX                                                              1
>+#define mmSDMA6_GFX_MIDCMD_DATA6                                                                       0x00c6
>+#define mmSDMA6_GFX_MIDCMD_DATA6_BASE_IDX                                                              1
>+#define mmSDMA6_GFX_MIDCMD_DATA7                                                                       0x00c7
>+#define mmSDMA6_GFX_MIDCMD_DATA7_BASE_IDX                                                              1
>+#define mmSDMA6_GFX_MIDCMD_DATA8                                                                       0x00c8
>+#define mmSDMA6_GFX_MIDCMD_DATA8_BASE_IDX                                                              1
>+#define mmSDMA6_GFX_MIDCMD_CNTL                                                                        0x00c9
>+#define mmSDMA6_GFX_MIDCMD_CNTL_BASE_IDX                                                               1
>+#define mmSDMA6_PAGE_RB_CNTL                                                                           0x00d8
>+#define mmSDMA6_PAGE_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_PAGE_RB_BASE                                                                           0x00d9
>+#define mmSDMA6_PAGE_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA6_PAGE_RB_BASE_HI                                                                        0x00da
>+#define mmSDMA6_PAGE_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_PAGE_RB_RPTR                                                                           0x00db
>+#define mmSDMA6_PAGE_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_PAGE_RB_RPTR_HI                                                                        0x00dc
>+#define mmSDMA6_PAGE_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_PAGE_RB_WPTR                                                                           0x00dd
>+#define mmSDMA6_PAGE_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_PAGE_RB_WPTR_HI                                                                        0x00de
>+#define mmSDMA6_PAGE_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_PAGE_RB_WPTR_POLL_CNTL                                                                 0x00df
>+#define mmSDMA6_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA6_PAGE_RB_RPTR_ADDR_HI                                                                   0x00e0
>+#define mmSDMA6_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA6_PAGE_RB_RPTR_ADDR_LO                                                                   0x00e1
>+#define mmSDMA6_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA6_PAGE_IB_CNTL                                                                           0x00e2
>+#define mmSDMA6_PAGE_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_PAGE_IB_RPTR                                                                           0x00e3
>+#define mmSDMA6_PAGE_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_PAGE_IB_OFFSET                                                                         0x00e4
>+#define mmSDMA6_PAGE_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA6_PAGE_IB_BASE_LO                                                                        0x00e5
>+#define mmSDMA6_PAGE_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA6_PAGE_IB_BASE_HI                                                                        0x00e6
>+#define mmSDMA6_PAGE_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_PAGE_IB_SIZE                                                                           0x00e7
>+#define mmSDMA6_PAGE_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA6_PAGE_SKIP_CNTL                                                                         0x00e8
>+#define mmSDMA6_PAGE_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA6_PAGE_CONTEXT_STATUS                                                                    0x00e9
>+#define mmSDMA6_PAGE_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA6_PAGE_DOORBELL                                                                          0x00ea
>+#define mmSDMA6_PAGE_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA6_PAGE_STATUS                                                                            0x0100
>+#define mmSDMA6_PAGE_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA6_PAGE_DOORBELL_LOG                                                                      0x0101
>+#define mmSDMA6_PAGE_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA6_PAGE_WATERMARK                                                                         0x0102
>+#define mmSDMA6_PAGE_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA6_PAGE_DOORBELL_OFFSET                                                                   0x0103
>+#define mmSDMA6_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA6_PAGE_CSA_ADDR_LO                                                                       0x0104
>+#define mmSDMA6_PAGE_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA6_PAGE_CSA_ADDR_HI                                                                       0x0105
>+#define mmSDMA6_PAGE_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA6_PAGE_IB_SUB_REMAIN                                                                     0x0107
>+#define mmSDMA6_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA6_PAGE_PREEMPT                                                                           0x0108
>+#define mmSDMA6_PAGE_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA6_PAGE_DUMMY_REG                                                                         0x0109
>+#define mmSDMA6_PAGE_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x010a
>+#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x010b
>+#define mmSDMA6_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA6_PAGE_RB_AQL_CNTL                                                                       0x010c
>+#define mmSDMA6_PAGE_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_PAGE_MINOR_PTR_UPDATE                                                                  0x010d
>+#define mmSDMA6_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA6_PAGE_MIDCMD_DATA0                                                                      0x0118
>+#define mmSDMA6_PAGE_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA6_PAGE_MIDCMD_DATA1                                                                      0x0119
>+#define mmSDMA6_PAGE_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA6_PAGE_MIDCMD_DATA2                                                                      0x011a
>+#define mmSDMA6_PAGE_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA6_PAGE_MIDCMD_DATA3                                                                      0x011b
>+#define mmSDMA6_PAGE_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA6_PAGE_MIDCMD_DATA4                                                                      0x011c
>+#define mmSDMA6_PAGE_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA6_PAGE_MIDCMD_DATA5                                                                      0x011d
>+#define mmSDMA6_PAGE_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA6_PAGE_MIDCMD_DATA6                                                                      0x011e
>+#define mmSDMA6_PAGE_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA6_PAGE_MIDCMD_DATA7                                                                      0x011f
>+#define mmSDMA6_PAGE_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA6_PAGE_MIDCMD_DATA8                                                                      0x0120
>+#define mmSDMA6_PAGE_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA6_PAGE_MIDCMD_CNTL                                                                       0x0121
>+#define mmSDMA6_PAGE_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC0_RB_CNTL                                                                           0x0130
>+#define mmSDMA6_RLC0_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC0_RB_BASE                                                                           0x0131
>+#define mmSDMA6_RLC0_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC0_RB_BASE_HI                                                                        0x0132
>+#define mmSDMA6_RLC0_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC0_RB_RPTR                                                                           0x0133
>+#define mmSDMA6_RLC0_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC0_RB_RPTR_HI                                                                        0x0134
>+#define mmSDMA6_RLC0_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC0_RB_WPTR                                                                           0x0135
>+#define mmSDMA6_RLC0_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC0_RB_WPTR_HI                                                                        0x0136
>+#define mmSDMA6_RLC0_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0137
>+#define mmSDMA6_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA6_RLC0_RB_RPTR_ADDR_HI                                                                   0x0138
>+#define mmSDMA6_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA6_RLC0_RB_RPTR_ADDR_LO                                                                   0x0139
>+#define mmSDMA6_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA6_RLC0_IB_CNTL                                                                           0x013a
>+#define mmSDMA6_RLC0_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC0_IB_RPTR                                                                           0x013b
>+#define mmSDMA6_RLC0_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC0_IB_OFFSET                                                                         0x013c
>+#define mmSDMA6_RLC0_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA6_RLC0_IB_BASE_LO                                                                        0x013d
>+#define mmSDMA6_RLC0_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA6_RLC0_IB_BASE_HI                                                                        0x013e
>+#define mmSDMA6_RLC0_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC0_IB_SIZE                                                                           0x013f
>+#define mmSDMA6_RLC0_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC0_SKIP_CNTL                                                                         0x0140
>+#define mmSDMA6_RLC0_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA6_RLC0_CONTEXT_STATUS                                                                    0x0141
>+#define mmSDMA6_RLC0_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA6_RLC0_DOORBELL                                                                          0x0142
>+#define mmSDMA6_RLC0_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA6_RLC0_STATUS                                                                            0x0158
>+#define mmSDMA6_RLC0_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA6_RLC0_DOORBELL_LOG                                                                      0x0159
>+#define mmSDMA6_RLC0_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA6_RLC0_WATERMARK                                                                         0x015a
>+#define mmSDMA6_RLC0_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA6_RLC0_DOORBELL_OFFSET                                                                   0x015b
>+#define mmSDMA6_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA6_RLC0_CSA_ADDR_LO                                                                       0x015c
>+#define mmSDMA6_RLC0_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA6_RLC0_CSA_ADDR_HI                                                                       0x015d
>+#define mmSDMA6_RLC0_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA6_RLC0_IB_SUB_REMAIN                                                                     0x015f
>+#define mmSDMA6_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA6_RLC0_PREEMPT                                                                           0x0160
>+#define mmSDMA6_RLC0_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC0_DUMMY_REG                                                                         0x0161
>+#define mmSDMA6_RLC0_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0162
>+#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0163
>+#define mmSDMA6_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA6_RLC0_RB_AQL_CNTL                                                                       0x0164
>+#define mmSDMA6_RLC0_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC0_MINOR_PTR_UPDATE                                                                  0x0165
>+#define mmSDMA6_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA6_RLC0_MIDCMD_DATA0                                                                      0x0170
>+#define mmSDMA6_RLC0_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA6_RLC0_MIDCMD_DATA1                                                                      0x0171
>+#define mmSDMA6_RLC0_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA6_RLC0_MIDCMD_DATA2                                                                      0x0172
>+#define mmSDMA6_RLC0_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA6_RLC0_MIDCMD_DATA3                                                                      0x0173
>+#define mmSDMA6_RLC0_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA6_RLC0_MIDCMD_DATA4                                                                      0x0174
>+#define mmSDMA6_RLC0_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA6_RLC0_MIDCMD_DATA5                                                                      0x0175
>+#define mmSDMA6_RLC0_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA6_RLC0_MIDCMD_DATA6                                                                      0x0176
>+#define mmSDMA6_RLC0_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA6_RLC0_MIDCMD_DATA7                                                                      0x0177
>+#define mmSDMA6_RLC0_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA6_RLC0_MIDCMD_DATA8                                                                      0x0178
>+#define mmSDMA6_RLC0_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA6_RLC0_MIDCMD_CNTL                                                                       0x0179
>+#define mmSDMA6_RLC0_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC1_RB_CNTL                                                                           0x0188
>+#define mmSDMA6_RLC1_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC1_RB_BASE                                                                           0x0189
>+#define mmSDMA6_RLC1_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC1_RB_BASE_HI                                                                        0x018a
>+#define mmSDMA6_RLC1_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC1_RB_RPTR                                                                           0x018b
>+#define mmSDMA6_RLC1_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC1_RB_RPTR_HI                                                                        0x018c
>+#define mmSDMA6_RLC1_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC1_RB_WPTR                                                                           0x018d
>+#define mmSDMA6_RLC1_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC1_RB_WPTR_HI                                                                        0x018e
>+#define mmSDMA6_RLC1_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC1_RB_WPTR_POLL_CNTL                                                                 0x018f
>+#define mmSDMA6_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA6_RLC1_RB_RPTR_ADDR_HI                                                                   0x0190
>+#define mmSDMA6_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA6_RLC1_RB_RPTR_ADDR_LO                                                                   0x0191
>+#define mmSDMA6_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA6_RLC1_IB_CNTL                                                                           0x0192
>+#define mmSDMA6_RLC1_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC1_IB_RPTR                                                                           0x0193
>+#define mmSDMA6_RLC1_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC1_IB_OFFSET                                                                         0x0194
>+#define mmSDMA6_RLC1_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA6_RLC1_IB_BASE_LO                                                                        0x0195
>+#define mmSDMA6_RLC1_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA6_RLC1_IB_BASE_HI                                                                        0x0196
>+#define mmSDMA6_RLC1_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC1_IB_SIZE                                                                           0x0197
>+#define mmSDMA6_RLC1_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC1_SKIP_CNTL                                                                         0x0198
>+#define mmSDMA6_RLC1_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA6_RLC1_CONTEXT_STATUS                                                                    0x0199
>+#define mmSDMA6_RLC1_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA6_RLC1_DOORBELL                                                                          0x019a
>+#define mmSDMA6_RLC1_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA6_RLC1_STATUS                                                                            0x01b0
>+#define mmSDMA6_RLC1_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA6_RLC1_DOORBELL_LOG                                                                      0x01b1
>+#define mmSDMA6_RLC1_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA6_RLC1_WATERMARK                                                                         0x01b2
>+#define mmSDMA6_RLC1_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA6_RLC1_DOORBELL_OFFSET                                                                   0x01b3
>+#define mmSDMA6_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA6_RLC1_CSA_ADDR_LO                                                                       0x01b4
>+#define mmSDMA6_RLC1_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA6_RLC1_CSA_ADDR_HI                                                                       0x01b5
>+#define mmSDMA6_RLC1_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA6_RLC1_IB_SUB_REMAIN                                                                     0x01b7
>+#define mmSDMA6_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA6_RLC1_PREEMPT                                                                           0x01b8
>+#define mmSDMA6_RLC1_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC1_DUMMY_REG                                                                         0x01b9
>+#define mmSDMA6_RLC1_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x01ba
>+#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x01bb
>+#define mmSDMA6_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA6_RLC1_RB_AQL_CNTL                                                                       0x01bc
>+#define mmSDMA6_RLC1_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC1_MINOR_PTR_UPDATE                                                                  0x01bd
>+#define mmSDMA6_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA6_RLC1_MIDCMD_DATA0                                                                      0x01c8
>+#define mmSDMA6_RLC1_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA6_RLC1_MIDCMD_DATA1                                                                      0x01c9
>+#define mmSDMA6_RLC1_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA6_RLC1_MIDCMD_DATA2                                                                      0x01ca
>+#define mmSDMA6_RLC1_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA6_RLC1_MIDCMD_DATA3                                                                      0x01cb
>+#define mmSDMA6_RLC1_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA6_RLC1_MIDCMD_DATA4                                                                      0x01cc
>+#define mmSDMA6_RLC1_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA6_RLC1_MIDCMD_DATA5                                                                      0x01cd
>+#define mmSDMA6_RLC1_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA6_RLC1_MIDCMD_DATA6                                                                      0x01ce
>+#define mmSDMA6_RLC1_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA6_RLC1_MIDCMD_DATA7                                                                      0x01cf
>+#define mmSDMA6_RLC1_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA6_RLC1_MIDCMD_DATA8                                                                      0x01d0
>+#define mmSDMA6_RLC1_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA6_RLC1_MIDCMD_CNTL                                                                       0x01d1
>+#define mmSDMA6_RLC1_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC2_RB_CNTL                                                                           0x01e0
>+#define mmSDMA6_RLC2_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC2_RB_BASE                                                                           0x01e1
>+#define mmSDMA6_RLC2_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC2_RB_BASE_HI                                                                        0x01e2
>+#define mmSDMA6_RLC2_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC2_RB_RPTR                                                                           0x01e3
>+#define mmSDMA6_RLC2_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC2_RB_RPTR_HI                                                                        0x01e4
>+#define mmSDMA6_RLC2_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC2_RB_WPTR                                                                           0x01e5
>+#define mmSDMA6_RLC2_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC2_RB_WPTR_HI                                                                        0x01e6
>+#define mmSDMA6_RLC2_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC2_RB_WPTR_POLL_CNTL                                                                 0x01e7
>+#define mmSDMA6_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA6_RLC2_RB_RPTR_ADDR_HI                                                                   0x01e8
>+#define mmSDMA6_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA6_RLC2_RB_RPTR_ADDR_LO                                                                   0x01e9
>+#define mmSDMA6_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA6_RLC2_IB_CNTL                                                                           0x01ea
>+#define mmSDMA6_RLC2_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC2_IB_RPTR                                                                           0x01eb
>+#define mmSDMA6_RLC2_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC2_IB_OFFSET                                                                         0x01ec
>+#define mmSDMA6_RLC2_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA6_RLC2_IB_BASE_LO                                                                        0x01ed
>+#define mmSDMA6_RLC2_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA6_RLC2_IB_BASE_HI                                                                        0x01ee
>+#define mmSDMA6_RLC2_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC2_IB_SIZE                                                                           0x01ef
>+#define mmSDMA6_RLC2_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC2_SKIP_CNTL                                                                         0x01f0
>+#define mmSDMA6_RLC2_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA6_RLC2_CONTEXT_STATUS                                                                    0x01f1
>+#define mmSDMA6_RLC2_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA6_RLC2_DOORBELL                                                                          0x01f2
>+#define mmSDMA6_RLC2_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA6_RLC2_STATUS                                                                            0x0208
>+#define mmSDMA6_RLC2_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA6_RLC2_DOORBELL_LOG                                                                      0x0209
>+#define mmSDMA6_RLC2_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA6_RLC2_WATERMARK                                                                         0x020a
>+#define mmSDMA6_RLC2_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA6_RLC2_DOORBELL_OFFSET                                                                   0x020b
>+#define mmSDMA6_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA6_RLC2_CSA_ADDR_LO                                                                       0x020c
>+#define mmSDMA6_RLC2_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA6_RLC2_CSA_ADDR_HI                                                                       0x020d
>+#define mmSDMA6_RLC2_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA6_RLC2_IB_SUB_REMAIN                                                                     0x020f
>+#define mmSDMA6_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA6_RLC2_PREEMPT                                                                           0x0210
>+#define mmSDMA6_RLC2_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC2_DUMMY_REG                                                                         0x0211
>+#define mmSDMA6_RLC2_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0212
>+#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0213
>+#define mmSDMA6_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA6_RLC2_RB_AQL_CNTL                                                                       0x0214
>+#define mmSDMA6_RLC2_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC2_MINOR_PTR_UPDATE                                                                  0x0215
>+#define mmSDMA6_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA6_RLC2_MIDCMD_DATA0                                                                      0x0220
>+#define mmSDMA6_RLC2_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA6_RLC2_MIDCMD_DATA1                                                                      0x0221
>+#define mmSDMA6_RLC2_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA6_RLC2_MIDCMD_DATA2                                                                      0x0222
>+#define mmSDMA6_RLC2_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA6_RLC2_MIDCMD_DATA3                                                                      0x0223
>+#define mmSDMA6_RLC2_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA6_RLC2_MIDCMD_DATA4                                                                      0x0224
>+#define mmSDMA6_RLC2_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA6_RLC2_MIDCMD_DATA5                                                                      0x0225
>+#define mmSDMA6_RLC2_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA6_RLC2_MIDCMD_DATA6                                                                      0x0226
>+#define mmSDMA6_RLC2_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA6_RLC2_MIDCMD_DATA7                                                                      0x0227
>+#define mmSDMA6_RLC2_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA6_RLC2_MIDCMD_DATA8                                                                      0x0228
>+#define mmSDMA6_RLC2_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA6_RLC2_MIDCMD_CNTL                                                                       0x0229
>+#define mmSDMA6_RLC2_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC3_RB_CNTL                                                                           0x0238
>+#define mmSDMA6_RLC3_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC3_RB_BASE                                                                           0x0239
>+#define mmSDMA6_RLC3_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC3_RB_BASE_HI                                                                        0x023a
>+#define mmSDMA6_RLC3_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC3_RB_RPTR                                                                           0x023b
>+#define mmSDMA6_RLC3_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC3_RB_RPTR_HI                                                                        0x023c
>+#define mmSDMA6_RLC3_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC3_RB_WPTR                                                                           0x023d
>+#define mmSDMA6_RLC3_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC3_RB_WPTR_HI                                                                        0x023e
>+#define mmSDMA6_RLC3_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC3_RB_WPTR_POLL_CNTL                                                                 0x023f
>+#define mmSDMA6_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA6_RLC3_RB_RPTR_ADDR_HI                                                                   0x0240
>+#define mmSDMA6_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA6_RLC3_RB_RPTR_ADDR_LO                                                                   0x0241
>+#define mmSDMA6_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA6_RLC3_IB_CNTL                                                                           0x0242
>+#define mmSDMA6_RLC3_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC3_IB_RPTR                                                                           0x0243
>+#define mmSDMA6_RLC3_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC3_IB_OFFSET                                                                         0x0244
>+#define mmSDMA6_RLC3_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA6_RLC3_IB_BASE_LO                                                                        0x0245
>+#define mmSDMA6_RLC3_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA6_RLC3_IB_BASE_HI                                                                        0x0246
>+#define mmSDMA6_RLC3_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC3_IB_SIZE                                                                           0x0247
>+#define mmSDMA6_RLC3_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC3_SKIP_CNTL                                                                         0x0248
>+#define mmSDMA6_RLC3_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA6_RLC3_CONTEXT_STATUS                                                                    0x0249
>+#define mmSDMA6_RLC3_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA6_RLC3_DOORBELL                                                                          0x024a
>+#define mmSDMA6_RLC3_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA6_RLC3_STATUS                                                                            0x0260
>+#define mmSDMA6_RLC3_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA6_RLC3_DOORBELL_LOG                                                                      0x0261
>+#define mmSDMA6_RLC3_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA6_RLC3_WATERMARK                                                                         0x0262
>+#define mmSDMA6_RLC3_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA6_RLC3_DOORBELL_OFFSET                                                                   0x0263
>+#define mmSDMA6_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA6_RLC3_CSA_ADDR_LO                                                                       0x0264
>+#define mmSDMA6_RLC3_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA6_RLC3_CSA_ADDR_HI                                                                       0x0265
>+#define mmSDMA6_RLC3_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA6_RLC3_IB_SUB_REMAIN                                                                     0x0267
>+#define mmSDMA6_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA6_RLC3_PREEMPT                                                                           0x0268
>+#define mmSDMA6_RLC3_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC3_DUMMY_REG                                                                         0x0269
>+#define mmSDMA6_RLC3_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x026a
>+#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x026b
>+#define mmSDMA6_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA6_RLC3_RB_AQL_CNTL                                                                       0x026c
>+#define mmSDMA6_RLC3_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC3_MINOR_PTR_UPDATE                                                                  0x026d
>+#define mmSDMA6_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA6_RLC3_MIDCMD_DATA0                                                                      0x0278
>+#define mmSDMA6_RLC3_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA6_RLC3_MIDCMD_DATA1                                                                      0x0279
>+#define mmSDMA6_RLC3_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA6_RLC3_MIDCMD_DATA2                                                                      0x027a
>+#define mmSDMA6_RLC3_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA6_RLC3_MIDCMD_DATA3                                                                      0x027b
>+#define mmSDMA6_RLC3_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA6_RLC3_MIDCMD_DATA4                                                                      0x027c
>+#define mmSDMA6_RLC3_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA6_RLC3_MIDCMD_DATA5                                                                      0x027d
>+#define mmSDMA6_RLC3_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA6_RLC3_MIDCMD_DATA6                                                                      0x027e
>+#define mmSDMA6_RLC3_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA6_RLC3_MIDCMD_DATA7                                                                      0x027f
>+#define mmSDMA6_RLC3_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA6_RLC3_MIDCMD_DATA8                                                                      0x0280
>+#define mmSDMA6_RLC3_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA6_RLC3_MIDCMD_CNTL                                                                       0x0281
>+#define mmSDMA6_RLC3_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC4_RB_CNTL                                                                           0x0290
>+#define mmSDMA6_RLC4_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC4_RB_BASE                                                                           0x0291
>+#define mmSDMA6_RLC4_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC4_RB_BASE_HI                                                                        0x0292
>+#define mmSDMA6_RLC4_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC4_RB_RPTR                                                                           0x0293
>+#define mmSDMA6_RLC4_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC4_RB_RPTR_HI                                                                        0x0294
>+#define mmSDMA6_RLC4_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC4_RB_WPTR                                                                           0x0295
>+#define mmSDMA6_RLC4_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC4_RB_WPTR_HI                                                                        0x0296
>+#define mmSDMA6_RLC4_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC4_RB_WPTR_POLL_CNTL                                                                 0x0297
>+#define mmSDMA6_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA6_RLC4_RB_RPTR_ADDR_HI                                                                   0x0298
>+#define mmSDMA6_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA6_RLC4_RB_RPTR_ADDR_LO                                                                   0x0299
>+#define mmSDMA6_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA6_RLC4_IB_CNTL                                                                           0x029a
>+#define mmSDMA6_RLC4_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC4_IB_RPTR                                                                           0x029b
>+#define mmSDMA6_RLC4_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC4_IB_OFFSET                                                                         0x029c
>+#define mmSDMA6_RLC4_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA6_RLC4_IB_BASE_LO                                                                        0x029d
>+#define mmSDMA6_RLC4_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA6_RLC4_IB_BASE_HI                                                                        0x029e
>+#define mmSDMA6_RLC4_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC4_IB_SIZE                                                                           0x029f
>+#define mmSDMA6_RLC4_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC4_SKIP_CNTL                                                                         0x02a0
>+#define mmSDMA6_RLC4_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA6_RLC4_CONTEXT_STATUS                                                                    0x02a1
>+#define mmSDMA6_RLC4_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA6_RLC4_DOORBELL                                                                          0x02a2
>+#define mmSDMA6_RLC4_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA6_RLC4_STATUS                                                                            0x02b8
>+#define mmSDMA6_RLC4_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA6_RLC4_DOORBELL_LOG                                                                      0x02b9
>+#define mmSDMA6_RLC4_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA6_RLC4_WATERMARK                                                                         0x02ba
>+#define mmSDMA6_RLC4_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA6_RLC4_DOORBELL_OFFSET                                                                   0x02bb
>+#define mmSDMA6_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA6_RLC4_CSA_ADDR_LO                                                                       0x02bc
>+#define mmSDMA6_RLC4_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA6_RLC4_CSA_ADDR_HI                                                                       0x02bd
>+#define mmSDMA6_RLC4_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA6_RLC4_IB_SUB_REMAIN                                                                     0x02bf
>+#define mmSDMA6_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA6_RLC4_PREEMPT                                                                           0x02c0
>+#define mmSDMA6_RLC4_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC4_DUMMY_REG                                                                         0x02c1
>+#define mmSDMA6_RLC4_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x02c2
>+#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x02c3
>+#define mmSDMA6_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA6_RLC4_RB_AQL_CNTL                                                                       0x02c4
>+#define mmSDMA6_RLC4_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC4_MINOR_PTR_UPDATE                                                                  0x02c5
>+#define mmSDMA6_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA6_RLC4_MIDCMD_DATA0                                                                      0x02d0
>+#define mmSDMA6_RLC4_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA6_RLC4_MIDCMD_DATA1                                                                      0x02d1
>+#define mmSDMA6_RLC4_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA6_RLC4_MIDCMD_DATA2                                                                      0x02d2
>+#define mmSDMA6_RLC4_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA6_RLC4_MIDCMD_DATA3                                                                      0x02d3
>+#define mmSDMA6_RLC4_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA6_RLC4_MIDCMD_DATA4                                                                      0x02d4
>+#define mmSDMA6_RLC4_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA6_RLC4_MIDCMD_DATA5                                                                      0x02d5
>+#define mmSDMA6_RLC4_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA6_RLC4_MIDCMD_DATA6                                                                      0x02d6
>+#define mmSDMA6_RLC4_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA6_RLC4_MIDCMD_DATA7                                                                      0x02d7
>+#define mmSDMA6_RLC4_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA6_RLC4_MIDCMD_DATA8                                                                      0x02d8
>+#define mmSDMA6_RLC4_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA6_RLC4_MIDCMD_CNTL                                                                       0x02d9
>+#define mmSDMA6_RLC4_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC5_RB_CNTL                                                                           0x02e8
>+#define mmSDMA6_RLC5_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC5_RB_BASE                                                                           0x02e9
>+#define mmSDMA6_RLC5_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC5_RB_BASE_HI                                                                        0x02ea
>+#define mmSDMA6_RLC5_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC5_RB_RPTR                                                                           0x02eb
>+#define mmSDMA6_RLC5_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC5_RB_RPTR_HI                                                                        0x02ec
>+#define mmSDMA6_RLC5_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC5_RB_WPTR                                                                           0x02ed
>+#define mmSDMA6_RLC5_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC5_RB_WPTR_HI                                                                        0x02ee
>+#define mmSDMA6_RLC5_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC5_RB_WPTR_POLL_CNTL                                                                 0x02ef
>+#define mmSDMA6_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA6_RLC5_RB_RPTR_ADDR_HI                                                                   0x02f0
>+#define mmSDMA6_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA6_RLC5_RB_RPTR_ADDR_LO                                                                   0x02f1
>+#define mmSDMA6_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA6_RLC5_IB_CNTL                                                                           0x02f2
>+#define mmSDMA6_RLC5_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC5_IB_RPTR                                                                           0x02f3
>+#define mmSDMA6_RLC5_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC5_IB_OFFSET                                                                         0x02f4
>+#define mmSDMA6_RLC5_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA6_RLC5_IB_BASE_LO                                                                        0x02f5
>+#define mmSDMA6_RLC5_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA6_RLC5_IB_BASE_HI                                                                        0x02f6
>+#define mmSDMA6_RLC5_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC5_IB_SIZE                                                                           0x02f7
>+#define mmSDMA6_RLC5_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC5_SKIP_CNTL                                                                         0x02f8
>+#define mmSDMA6_RLC5_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA6_RLC5_CONTEXT_STATUS                                                                    0x02f9
>+#define mmSDMA6_RLC5_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA6_RLC5_DOORBELL                                                                          0x02fa
>+#define mmSDMA6_RLC5_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA6_RLC5_STATUS                                                                            0x0310
>+#define mmSDMA6_RLC5_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA6_RLC5_DOORBELL_LOG                                                                      0x0311
>+#define mmSDMA6_RLC5_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA6_RLC5_WATERMARK                                                                         0x0312
>+#define mmSDMA6_RLC5_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA6_RLC5_DOORBELL_OFFSET                                                                   0x0313
>+#define mmSDMA6_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA6_RLC5_CSA_ADDR_LO                                                                       0x0314
>+#define mmSDMA6_RLC5_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA6_RLC5_CSA_ADDR_HI                                                                       0x0315
>+#define mmSDMA6_RLC5_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA6_RLC5_IB_SUB_REMAIN                                                                     0x0317
>+#define mmSDMA6_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA6_RLC5_PREEMPT                                                                           0x0318
>+#define mmSDMA6_RLC5_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC5_DUMMY_REG                                                                         0x0319
>+#define mmSDMA6_RLC5_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x031a
>+#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x031b
>+#define mmSDMA6_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA6_RLC5_RB_AQL_CNTL                                                                       0x031c
>+#define mmSDMA6_RLC5_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC5_MINOR_PTR_UPDATE                                                                  0x031d
>+#define mmSDMA6_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA6_RLC5_MIDCMD_DATA0                                                                      0x0328
>+#define mmSDMA6_RLC5_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA6_RLC5_MIDCMD_DATA1                                                                      0x0329
>+#define mmSDMA6_RLC5_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA6_RLC5_MIDCMD_DATA2                                                                      0x032a
>+#define mmSDMA6_RLC5_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA6_RLC5_MIDCMD_DATA3                                                                      0x032b
>+#define mmSDMA6_RLC5_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA6_RLC5_MIDCMD_DATA4                                                                      0x032c
>+#define mmSDMA6_RLC5_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA6_RLC5_MIDCMD_DATA5                                                                      0x032d
>+#define mmSDMA6_RLC5_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA6_RLC5_MIDCMD_DATA6                                                                      0x032e
>+#define mmSDMA6_RLC5_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA6_RLC5_MIDCMD_DATA7                                                                      0x032f
>+#define mmSDMA6_RLC5_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA6_RLC5_MIDCMD_DATA8                                                                      0x0330
>+#define mmSDMA6_RLC5_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA6_RLC5_MIDCMD_CNTL                                                                       0x0331
>+#define mmSDMA6_RLC5_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC6_RB_CNTL                                                                           0x0340
>+#define mmSDMA6_RLC6_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC6_RB_BASE                                                                           0x0341
>+#define mmSDMA6_RLC6_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC6_RB_BASE_HI                                                                        0x0342
>+#define mmSDMA6_RLC6_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC6_RB_RPTR                                                                           0x0343
>+#define mmSDMA6_RLC6_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC6_RB_RPTR_HI                                                                        0x0344
>+#define mmSDMA6_RLC6_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC6_RB_WPTR                                                                           0x0345
>+#define mmSDMA6_RLC6_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC6_RB_WPTR_HI                                                                        0x0346
>+#define mmSDMA6_RLC6_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0347
>+#define mmSDMA6_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA6_RLC6_RB_RPTR_ADDR_HI                                                                   0x0348
>+#define mmSDMA6_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA6_RLC6_RB_RPTR_ADDR_LO                                                                   0x0349
>+#define mmSDMA6_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA6_RLC6_IB_CNTL                                                                           0x034a
>+#define mmSDMA6_RLC6_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC6_IB_RPTR                                                                           0x034b
>+#define mmSDMA6_RLC6_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC6_IB_OFFSET                                                                         0x034c
>+#define mmSDMA6_RLC6_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA6_RLC6_IB_BASE_LO                                                                        0x034d
>+#define mmSDMA6_RLC6_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA6_RLC6_IB_BASE_HI                                                                        0x034e
>+#define mmSDMA6_RLC6_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC6_IB_SIZE                                                                           0x034f
>+#define mmSDMA6_RLC6_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC6_SKIP_CNTL                                                                         0x0350
>+#define mmSDMA6_RLC6_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA6_RLC6_CONTEXT_STATUS                                                                    0x0351
>+#define mmSDMA6_RLC6_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA6_RLC6_DOORBELL                                                                          0x0352
>+#define mmSDMA6_RLC6_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA6_RLC6_STATUS                                                                            0x0368
>+#define mmSDMA6_RLC6_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA6_RLC6_DOORBELL_LOG                                                                      0x0369
>+#define mmSDMA6_RLC6_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA6_RLC6_WATERMARK                                                                         0x036a
>+#define mmSDMA6_RLC6_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA6_RLC6_DOORBELL_OFFSET                                                                   0x036b
>+#define mmSDMA6_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA6_RLC6_CSA_ADDR_LO                                                                       0x036c
>+#define mmSDMA6_RLC6_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA6_RLC6_CSA_ADDR_HI                                                                       0x036d
>+#define mmSDMA6_RLC6_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA6_RLC6_IB_SUB_REMAIN                                                                     0x036f
>+#define mmSDMA6_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA6_RLC6_PREEMPT                                                                           0x0370
>+#define mmSDMA6_RLC6_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC6_DUMMY_REG                                                                         0x0371
>+#define mmSDMA6_RLC6_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x0372
>+#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x0373
>+#define mmSDMA6_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA6_RLC6_RB_AQL_CNTL                                                                       0x0374
>+#define mmSDMA6_RLC6_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC6_MINOR_PTR_UPDATE                                                                  0x0375
>+#define mmSDMA6_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA6_RLC6_MIDCMD_DATA0                                                                      0x0380
>+#define mmSDMA6_RLC6_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA6_RLC6_MIDCMD_DATA1                                                                      0x0381
>+#define mmSDMA6_RLC6_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA6_RLC6_MIDCMD_DATA2                                                                      0x0382
>+#define mmSDMA6_RLC6_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA6_RLC6_MIDCMD_DATA3                                                                      0x0383
>+#define mmSDMA6_RLC6_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA6_RLC6_MIDCMD_DATA4                                                                      0x0384
>+#define mmSDMA6_RLC6_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA6_RLC6_MIDCMD_DATA5                                                                      0x0385
>+#define mmSDMA6_RLC6_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA6_RLC6_MIDCMD_DATA6                                                                      0x0386
>+#define mmSDMA6_RLC6_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA6_RLC6_MIDCMD_DATA7                                                                      0x0387
>+#define mmSDMA6_RLC6_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA6_RLC6_MIDCMD_DATA8                                                                      0x0388
>+#define mmSDMA6_RLC6_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA6_RLC6_MIDCMD_CNTL                                                                       0x0389
>+#define mmSDMA6_RLC6_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC7_RB_CNTL                                                                           0x0398
>+#define mmSDMA6_RLC7_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC7_RB_BASE                                                                           0x0399
>+#define mmSDMA6_RLC7_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC7_RB_BASE_HI                                                                        0x039a
>+#define mmSDMA6_RLC7_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC7_RB_RPTR                                                                           0x039b
>+#define mmSDMA6_RLC7_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC7_RB_RPTR_HI                                                                        0x039c
>+#define mmSDMA6_RLC7_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC7_RB_WPTR                                                                           0x039d
>+#define mmSDMA6_RLC7_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC7_RB_WPTR_HI                                                                        0x039e
>+#define mmSDMA6_RLC7_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC7_RB_WPTR_POLL_CNTL                                                                 0x039f
>+#define mmSDMA6_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA6_RLC7_RB_RPTR_ADDR_HI                                                                   0x03a0
>+#define mmSDMA6_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA6_RLC7_RB_RPTR_ADDR_LO                                                                   0x03a1
>+#define mmSDMA6_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA6_RLC7_IB_CNTL                                                                           0x03a2
>+#define mmSDMA6_RLC7_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC7_IB_RPTR                                                                           0x03a3
>+#define mmSDMA6_RLC7_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC7_IB_OFFSET                                                                         0x03a4
>+#define mmSDMA6_RLC7_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA6_RLC7_IB_BASE_LO                                                                        0x03a5
>+#define mmSDMA6_RLC7_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA6_RLC7_IB_BASE_HI                                                                        0x03a6
>+#define mmSDMA6_RLC7_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA6_RLC7_IB_SIZE                                                                           0x03a7
>+#define mmSDMA6_RLC7_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC7_SKIP_CNTL                                                                         0x03a8
>+#define mmSDMA6_RLC7_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA6_RLC7_CONTEXT_STATUS                                                                    0x03a9
>+#define mmSDMA6_RLC7_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA6_RLC7_DOORBELL                                                                          0x03aa
>+#define mmSDMA6_RLC7_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA6_RLC7_STATUS                                                                            0x03c0
>+#define mmSDMA6_RLC7_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA6_RLC7_DOORBELL_LOG                                                                      0x03c1
>+#define mmSDMA6_RLC7_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA6_RLC7_WATERMARK                                                                         0x03c2
>+#define mmSDMA6_RLC7_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA6_RLC7_DOORBELL_OFFSET                                                                   0x03c3
>+#define mmSDMA6_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA6_RLC7_CSA_ADDR_LO                                                                       0x03c4
>+#define mmSDMA6_RLC7_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA6_RLC7_CSA_ADDR_HI                                                                       0x03c5
>+#define mmSDMA6_RLC7_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA6_RLC7_IB_SUB_REMAIN                                                                     0x03c7
>+#define mmSDMA6_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA6_RLC7_PREEMPT                                                                           0x03c8
>+#define mmSDMA6_RLC7_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA6_RLC7_DUMMY_REG                                                                         0x03c9
>+#define mmSDMA6_RLC7_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x03ca
>+#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x03cb
>+#define mmSDMA6_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA6_RLC7_RB_AQL_CNTL                                                                       0x03cc
>+#define mmSDMA6_RLC7_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA6_RLC7_MINOR_PTR_UPDATE                                                                  0x03cd
>+#define mmSDMA6_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA6_RLC7_MIDCMD_DATA0                                                                      0x03d8
>+#define mmSDMA6_RLC7_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA6_RLC7_MIDCMD_DATA1                                                                      0x03d9
>+#define mmSDMA6_RLC7_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA6_RLC7_MIDCMD_DATA2                                                                      0x03da
>+#define mmSDMA6_RLC7_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA6_RLC7_MIDCMD_DATA3                                                                      0x03db
>+#define mmSDMA6_RLC7_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA6_RLC7_MIDCMD_DATA4                                                                      0x03dc
>+#define mmSDMA6_RLC7_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA6_RLC7_MIDCMD_DATA5                                                                      0x03dd
>+#define mmSDMA6_RLC7_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA6_RLC7_MIDCMD_DATA6                                                                      0x03de
>+#define mmSDMA6_RLC7_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA6_RLC7_MIDCMD_DATA7                                                                      0x03df
>+#define mmSDMA6_RLC7_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA6_RLC7_MIDCMD_DATA8                                                                      0x03e0
>+#define mmSDMA6_RLC7_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA6_RLC7_MIDCMD_CNTL                                                                       0x03e1
>+#define mmSDMA6_RLC7_MIDCMD_CNTL_BASE_IDX                                                              1
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma6/sdma6_4_2_2_sh_mask.h	2019-08-31 15:01:11.933736175 -0500
>@@ -0,0 +1,2956 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma6_4_2_2_SH_MASK_HEADER
>+#define _sdma6_4_2_2_SH_MASK_HEADER
>+
>+
>+// addressBlock: sdma6_sdma6dec
>+//SDMA6_UCODE_ADDR
>+#define SDMA6_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
>+#define SDMA6_UCODE_ADDR__VALUE_MASK                                                                          0x00001FFFL
>+//SDMA6_UCODE_DATA
>+#define SDMA6_UCODE_DATA__VALUE__SHIFT                                                                        0x0
>+#define SDMA6_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
>+//SDMA6_VM_CNTL
>+#define SDMA6_VM_CNTL__CMD__SHIFT                                                                             0x0
>+#define SDMA6_VM_CNTL__CMD_MASK                                                                               0x0000000FL
>+//SDMA6_VM_CTX_LO
>+#define SDMA6_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
>+#define SDMA6_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
>+//SDMA6_VM_CTX_HI
>+#define SDMA6_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
>+#define SDMA6_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
>+//SDMA6_ACTIVE_FCN_ID
>+#define SDMA6_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
>+#define SDMA6_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x4
>+#define SDMA6_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
>+#define SDMA6_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000000FL
>+#define SDMA6_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFF0L
>+#define SDMA6_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
>+//SDMA6_VM_CTX_CNTL
>+#define SDMA6_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
>+#define SDMA6_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
>+#define SDMA6_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
>+#define SDMA6_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
>+//SDMA6_VIRT_RESET_REQ
>+#define SDMA6_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
>+#define SDMA6_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
>+#define SDMA6_VIRT_RESET_REQ__VF_MASK                                                                         0x0000FFFFL
>+#define SDMA6_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
>+//SDMA6_VF_ENABLE
>+#define SDMA6_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
>+#define SDMA6_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
>+//SDMA6_CONTEXT_REG_TYPE0
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_CNTL__SHIFT                                                     0x0
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_BASE__SHIFT                                                     0x1
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_BASE_HI__SHIFT                                                  0x2
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR__SHIFT                                                     0x3
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_HI__SHIFT                                                  0x4
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR__SHIFT                                                     0x5
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_HI__SHIFT                                                  0x6
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_CNTL__SHIFT                                                     0xa
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_RPTR__SHIFT                                                     0xb
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_OFFSET__SHIFT                                                   0xc
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_BASE_LO__SHIFT                                                  0xd
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_BASE_HI__SHIFT                                                  0xe
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_SIZE__SHIFT                                                     0xf
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_SKIP_CNTL__SHIFT                                                   0x10
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_CONTEXT_STATUS__SHIFT                                              0x11
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_DOORBELL__SHIFT                                                    0x12
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_CONTEXT_CNTL__SHIFT                                                0x13
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_CNTL_MASK                                                       0x00000001L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_BASE_MASK                                                       0x00000002L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_BASE_HI_MASK                                                    0x00000004L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_MASK                                                       0x00000008L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_MASK                                                       0x00000020L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_CNTL_MASK                                                       0x00000400L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_RPTR_MASK                                                       0x00000800L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_OFFSET_MASK                                                     0x00001000L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_BASE_LO_MASK                                                    0x00002000L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_BASE_HI_MASK                                                    0x00004000L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_IB_SIZE_MASK                                                       0x00008000L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_SKIP_CNTL_MASK                                                     0x00010000L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_DOORBELL_MASK                                                      0x00040000L
>+#define SDMA6_CONTEXT_REG_TYPE0__SDMA6_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
>+//SDMA6_CONTEXT_REG_TYPE1
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_STATUS__SHIFT                                                      0x8
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DOORBELL_LOG__SHIFT                                                0x9
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_WATERMARK__SHIFT                                                   0xa
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
>+#define SDMA6_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_PREEMPT__SHIFT                                                     0x10
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DUMMY_REG__SHIFT                                                   0x11
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
>+#define SDMA6_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x16
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_STATUS_MASK                                                        0x00000100L
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_WATERMARK_MASK                                                     0x00000400L
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
>+#define SDMA6_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_PREEMPT_MASK                                                       0x00010000L
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_DUMMY_REG_MASK                                                     0x00020000L
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
>+#define SDMA6_CONTEXT_REG_TYPE1__SDMA6_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
>+#define SDMA6_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFFC00000L
>+//SDMA6_CONTEXT_REG_TYPE2
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA0__SHIFT                                                0x0
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA1__SHIFT                                                0x1
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA2__SHIFT                                                0x2
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA3__SHIFT                                                0x3
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA4__SHIFT                                                0x4
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA5__SHIFT                                                0x5
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA6__SHIFT                                                0x6
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA7__SHIFT                                                0x7
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA8__SHIFT                                                0x8
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_CNTL__SHIFT                                                 0x9
>+#define SDMA6_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
>+#define SDMA6_CONTEXT_REG_TYPE2__SDMA6_GFX_MIDCMD_CNTL_MASK                                                   0x00000200L
>+#define SDMA6_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFFC00L
>+//SDMA6_CONTEXT_REG_TYPE3
>+#define SDMA6_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
>+#define SDMA6_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
>+//SDMA6_PUB_REG_TYPE0
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_UCODE_ADDR__SHIFT                                                          0x0
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_UCODE_DATA__SHIFT                                                          0x1
>+#define SDMA6_PUB_REG_TYPE0__RESERVED3__SHIFT                                                                 0x3
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CNTL__SHIFT                                                             0x4
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_LO__SHIFT                                                           0x5
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_HI__SHIFT                                                           0x6
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_ACTIVE_FCN_ID__SHIFT                                                       0x7
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_CNTL__SHIFT                                                         0x8
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_VIRT_RESET_REQ__SHIFT                                                      0x9
>+#define SDMA6_PUB_REG_TYPE0__RESERVED10__SHIFT                                                                0xa
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE0__SHIFT                                                   0xb
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE1__SHIFT                                                   0xc
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE2__SHIFT                                                   0xd
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE3__SHIFT                                                   0xe
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE0__SHIFT                                                       0xf
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE1__SHIFT                                                       0x10
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE2__SHIFT                                                       0x11
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE3__SHIFT                                                       0x12
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_MMHUB_CNTL__SHIFT                                                          0x13
>+#define SDMA6_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x15
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_GROUP_BOUNDARY__SHIFT                                              0x19
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_POWER_CNTL__SHIFT                                                          0x1a
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CLK_CTRL__SHIFT                                                            0x1b
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CNTL__SHIFT                                                                0x1c
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CHICKEN_BITS__SHIFT                                                        0x1d
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_GB_ADDR_CONFIG__SHIFT                                                      0x1e
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_UCODE_ADDR_MASK                                                            0x00000001L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_UCODE_DATA_MASK                                                            0x00000002L
>+#define SDMA6_PUB_REG_TYPE0__RESERVED3_MASK                                                                   0x00000008L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CNTL_MASK                                                               0x00000010L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_LO_MASK                                                             0x00000020L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_HI_MASK                                                             0x00000040L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_ACTIVE_FCN_ID_MASK                                                         0x00000080L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_VM_CTX_CNTL_MASK                                                           0x00000100L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_VIRT_RESET_REQ_MASK                                                        0x00000200L
>+#define SDMA6_PUB_REG_TYPE0__RESERVED10_MASK                                                                  0x00000400L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE0_MASK                                                     0x00000800L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE1_MASK                                                     0x00001000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE2_MASK                                                     0x00002000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_REG_TYPE3_MASK                                                     0x00004000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE0_MASK                                                         0x00008000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE1_MASK                                                         0x00010000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE2_MASK                                                         0x00020000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_PUB_REG_TYPE3_MASK                                                         0x00040000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_MMHUB_CNTL_MASK                                                            0x00080000L
>+#define SDMA6_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x01E00000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CONTEXT_GROUP_BOUNDARY_MASK                                                0x02000000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_POWER_CNTL_MASK                                                            0x04000000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CLK_CTRL_MASK                                                              0x08000000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CNTL_MASK                                                                  0x10000000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_CHICKEN_BITS_MASK                                                          0x20000000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_GB_ADDR_CONFIG_MASK                                                        0x40000000L
>+#define SDMA6_PUB_REG_TYPE0__SDMA6_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
>+//SDMA6_PUB_REG_TYPE1
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_RB_RPTR_FETCH__SHIFT                                                       0x2
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_IB_OFFSET_FETCH__SHIFT                                                     0x3
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_PROGRAM__SHIFT                                                             0x4
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS_REG__SHIFT                                                          0x5
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS1_REG__SHIFT                                                         0x6
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_RD_BURST_CNTL__SHIFT                                                       0x7
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_HBM_PAGE_CONFIG__SHIFT                                                     0x8
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_UCODE_CHECKSUM__SHIFT                                                      0x9
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_F32_CNTL__SHIFT                                                            0xa
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_FREEZE__SHIFT                                                              0xb
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_PHASE0_QUANTUM__SHIFT                                                      0xc
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_PHASE1_QUANTUM__SHIFT                                                      0xd
>+#define SDMA6_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT                                                         0xe
>+#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT                                                         0xf
>+#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT                                                          0x10
>+#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT                                                           0x11
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_CONFIG__SHIFT                                                          0x12
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_BA_THRESHOLD__SHIFT                                                        0x13
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_ID__SHIFT                                                                  0x14
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_VERSION__SHIFT                                                             0x15
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_COUNTER__SHIFT                                                         0x16
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS2_REG__SHIFT                                                         0x18
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_CNTL__SHIFT                                                         0x19
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_CNTL__SHIFT                                                          0x1c
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WATERMK__SHIFT                                                       0x1d
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_RD_STATUS__SHIFT                                                     0x1e
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WR_STATUS__SHIFT                                                     0x1f
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_RB_RPTR_FETCH_MASK                                                         0x00000004L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_IB_OFFSET_FETCH_MASK                                                       0x00000008L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_PROGRAM_MASK                                                               0x00000010L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS_REG_MASK                                                            0x00000020L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS1_REG_MASK                                                           0x00000040L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_RD_BURST_CNTL_MASK                                                         0x00000080L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_UCODE_CHECKSUM_MASK                                                        0x00000200L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_F32_CNTL_MASK                                                              0x00000400L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_FREEZE_MASK                                                                0x00000800L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_PHASE0_QUANTUM_MASK                                                        0x00001000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_PHASE1_QUANTUM_MASK                                                        0x00002000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK                                                           0x00004000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK                                                           0x00008000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK                                                            0x00010000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK                                                             0x00020000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_CONFIG_MASK                                                            0x00040000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_BA_THRESHOLD_MASK                                                          0x00080000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_ID_MASK                                                                    0x00100000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_VERSION_MASK                                                               0x00200000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_COUNTER_MASK                                                           0x00400000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_STATUS2_REG_MASK                                                           0x01000000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_CNTL_MASK                                                           0x02000000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_CNTL_MASK                                                            0x10000000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WATERMK_MASK                                                         0x20000000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_RD_STATUS_MASK                                                       0x40000000L
>+#define SDMA6_PUB_REG_TYPE1__SDMA6_UTCL1_WR_STATUS_MASK                                                       0x80000000L
>+//SDMA6_PUB_REG_TYPE2
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV0__SHIFT                                                          0x0
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV1__SHIFT                                                          0x1
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV2__SHIFT                                                          0x2
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_RD_XNACK0__SHIFT                                                     0x3
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_RD_XNACK1__SHIFT                                                     0x4
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_WR_XNACK0__SHIFT                                                     0x5
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_WR_XNACK1__SHIFT                                                     0x6
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_TIMEOUT__SHIFT                                                       0x7
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_PAGE__SHIFT                                                          0x8
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_POWER_CNTL_IDLE__SHIFT                                                     0x9
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_RELAX_ORDERING_LUT__SHIFT                                                  0xa
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_CHICKEN_BITS_2__SHIFT                                                      0xb
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_STATUS3_REG__SHIFT                                                         0xc
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PHASE2_QUANTUM__SHIFT                                                      0xf
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_ERROR_LOG__SHIFT                                                           0x10
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG0__SHIFT                                                      0x11
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG1__SHIFT                                                      0x12
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG2__SHIFT                                                      0x13
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG3__SHIFT                                                      0x14
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_F32_COUNTER__SHIFT                                                         0x15
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UNBREAKABLE__SHIFT                                                         0x16
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFMON_CNTL__SHIFT                                                        0x17
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER0_RESULT__SHIFT                                                 0x18
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER1_RESULT__SHIFT                                                 0x19
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT                                         0x1a
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_CRD_CNTL__SHIFT                                                            0x1b
>+#define SDMA6_PUB_REG_TYPE2__RESERVED28__SHIFT                                                                0x1c
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_GPU_IOV_VIOLATION_LOG__SHIFT                                               0x1d
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_ULV_CNTL__SHIFT                                                            0x1e
>+#define SDMA6_PUB_REG_TYPE2__RESERVED__SHIFT                                                                  0x1f
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV0_MASK                                                            0x00000001L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV1_MASK                                                            0x00000002L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_INV2_MASK                                                            0x00000004L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_TIMEOUT_MASK                                                         0x00000080L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UTCL1_PAGE_MASK                                                            0x00000100L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_POWER_CNTL_IDLE_MASK                                                       0x00000200L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_CHICKEN_BITS_2_MASK                                                        0x00000800L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_STATUS3_REG_MASK                                                           0x00001000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PHASE2_QUANTUM_MASK                                                        0x00008000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_ERROR_LOG_MASK                                                             0x00010000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG0_MASK                                                        0x00020000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG1_MASK                                                        0x00040000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG2_MASK                                                        0x00080000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PUB_DUMMY_REG3_MASK                                                        0x00100000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_F32_COUNTER_MASK                                                           0x00200000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_UNBREAKABLE_MASK                                                           0x00400000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFMON_CNTL_MASK                                                          0x00800000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER0_RESULT_MASK                                                   0x01000000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER1_RESULT_MASK                                                   0x02000000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_PERFCOUNTER_TAG_DELAY_RANGE_MASK                                           0x04000000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_CRD_CNTL_MASK                                                              0x08000000L
>+#define SDMA6_PUB_REG_TYPE2__RESERVED28_MASK                                                                  0x10000000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_GPU_IOV_VIOLATION_LOG_MASK                                                 0x20000000L
>+#define SDMA6_PUB_REG_TYPE2__SDMA6_ULV_CNTL_MASK                                                              0x40000000L
>+#define SDMA6_PUB_REG_TYPE2__RESERVED_MASK                                                                    0x80000000L
>+//SDMA6_PUB_REG_TYPE3
>+#define SDMA6_PUB_REG_TYPE3__SDMA6_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
>+#define SDMA6_PUB_REG_TYPE3__SDMA6_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
>+#define SDMA6_PUB_REG_TYPE3__SDMA6_GPU_IOV_VIOLATION_LOG2__SHIFT                                              0x2
>+#define SDMA6_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x3
>+#define SDMA6_PUB_REG_TYPE3__SDMA6_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
>+#define SDMA6_PUB_REG_TYPE3__SDMA6_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
>+#define SDMA6_PUB_REG_TYPE3__SDMA6_GPU_IOV_VIOLATION_LOG2_MASK                                                0x00000004L
>+#define SDMA6_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xFFFFFFF8L
>+//SDMA6_MMHUB_CNTL
>+#define SDMA6_MMHUB_CNTL__UNIT_ID__SHIFT                                                                      0x0
>+#define SDMA6_MMHUB_CNTL__UNIT_ID_MASK                                                                        0x0000003FL
>+//SDMA6_CONTEXT_GROUP_BOUNDARY
>+#define SDMA6_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT                                                         0x0
>+#define SDMA6_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK                                                           0xFFFFFFFFL
>+//SDMA6_POWER_CNTL
>+#define SDMA6_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
>+#define SDMA6_POWER_CNTL__MEM_POWER_LS_EN__SHIFT                                                              0x9
>+#define SDMA6_POWER_CNTL__MEM_POWER_DS_EN__SHIFT                                                              0xa
>+#define SDMA6_POWER_CNTL__MEM_POWER_SD_EN__SHIFT                                                              0xb
>+#define SDMA6_POWER_CNTL__MEM_POWER_DELAY__SHIFT                                                              0xc
>+#define SDMA6_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
>+#define SDMA6_POWER_CNTL__MEM_POWER_LS_EN_MASK                                                                0x00000200L
>+#define SDMA6_POWER_CNTL__MEM_POWER_DS_EN_MASK                                                                0x00000400L
>+#define SDMA6_POWER_CNTL__MEM_POWER_SD_EN_MASK                                                                0x00000800L
>+#define SDMA6_POWER_CNTL__MEM_POWER_DELAY_MASK                                                                0x003FF000L
>+//SDMA6_CLK_CTRL
>+#define SDMA6_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
>+#define SDMA6_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
>+#define SDMA6_CLK_CTRL__RESERVED__SHIFT                                                                       0xc
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                                 0x18
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                                 0x19
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                                 0x1a
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1b
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1c
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1d
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1e
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1f
>+#define SDMA6_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
>+#define SDMA6_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
>+#define SDMA6_CLK_CTRL__RESERVED_MASK                                                                         0x00FFF000L
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                   0x01000000L
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                   0x02000000L
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                   0x04000000L
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x08000000L
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x10000000L
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x20000000L
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x40000000L
>+#define SDMA6_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x80000000L
>+//SDMA6_CNTL
>+#define SDMA6_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
>+#define SDMA6_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
>+#define SDMA6_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
>+#define SDMA6_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
>+#define SDMA6_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
>+#define SDMA6_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
>+#define SDMA6_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
>+#define SDMA6_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
>+#define SDMA6_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
>+#define SDMA6_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
>+#define SDMA6_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
>+#define SDMA6_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
>+#define SDMA6_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
>+#define SDMA6_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
>+#define SDMA6_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
>+#define SDMA6_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
>+#define SDMA6_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
>+#define SDMA6_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
>+#define SDMA6_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
>+#define SDMA6_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
>+#define SDMA6_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
>+#define SDMA6_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
>+//SDMA6_CHICKEN_BITS
>+#define SDMA6_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
>+#define SDMA6_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
>+#define SDMA6_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
>+#define SDMA6_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
>+#define SDMA6_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
>+#define SDMA6_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
>+#define SDMA6_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
>+#define SDMA6_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
>+#define SDMA6_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
>+#define SDMA6_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
>+#define SDMA6_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
>+#define SDMA6_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
>+#define SDMA6_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
>+#define SDMA6_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
>+#define SDMA6_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
>+#define SDMA6_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
>+#define SDMA6_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
>+#define SDMA6_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
>+#define SDMA6_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
>+#define SDMA6_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
>+#define SDMA6_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
>+#define SDMA6_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
>+#define SDMA6_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
>+#define SDMA6_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
>+#define SDMA6_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
>+#define SDMA6_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
>+//SDMA6_GB_ADDR_CONFIG
>+#define SDMA6_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
>+#define SDMA6_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
>+#define SDMA6_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
>+#define SDMA6_GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
>+#define SDMA6_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
>+#define SDMA6_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
>+#define SDMA6_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
>+#define SDMA6_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
>+#define SDMA6_GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
>+#define SDMA6_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
>+//SDMA6_GB_ADDR_CONFIG_READ
>+#define SDMA6_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
>+#define SDMA6_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
>+#define SDMA6_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                0x8
>+#define SDMA6_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                           0xc
>+#define SDMA6_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
>+#define SDMA6_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
>+#define SDMA6_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
>+#define SDMA6_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                  0x00000700L
>+#define SDMA6_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                             0x00007000L
>+#define SDMA6_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
>+//SDMA6_RB_RPTR_FETCH_HI
>+#define SDMA6_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
>+#define SDMA6_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_SEM_WAIT_FAIL_TIMER_CNTL
>+#define SDMA6_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
>+#define SDMA6_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
>+//SDMA6_RB_RPTR_FETCH
>+#define SDMA6_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
>+#define SDMA6_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
>+//SDMA6_IB_OFFSET_FETCH
>+#define SDMA6_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
>+#define SDMA6_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
>+//SDMA6_PROGRAM
>+#define SDMA6_PROGRAM__STREAM__SHIFT                                                                          0x0
>+#define SDMA6_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
>+//SDMA6_STATUS_REG
>+#define SDMA6_STATUS_REG__IDLE__SHIFT                                                                         0x0
>+#define SDMA6_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
>+#define SDMA6_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
>+#define SDMA6_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
>+#define SDMA6_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
>+#define SDMA6_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
>+#define SDMA6_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
>+#define SDMA6_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
>+#define SDMA6_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
>+#define SDMA6_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
>+#define SDMA6_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
>+#define SDMA6_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
>+#define SDMA6_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
>+#define SDMA6_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
>+#define SDMA6_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
>+#define SDMA6_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
>+#define SDMA6_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
>+#define SDMA6_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
>+#define SDMA6_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
>+#define SDMA6_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
>+#define SDMA6_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
>+#define SDMA6_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
>+#define SDMA6_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
>+#define SDMA6_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
>+#define SDMA6_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
>+#define SDMA6_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
>+#define SDMA6_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
>+#define SDMA6_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
>+#define SDMA6_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
>+#define SDMA6_STATUS_REG__IDLE_MASK                                                                           0x00000001L
>+#define SDMA6_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
>+#define SDMA6_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
>+#define SDMA6_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
>+#define SDMA6_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
>+#define SDMA6_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
>+#define SDMA6_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
>+#define SDMA6_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
>+#define SDMA6_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
>+#define SDMA6_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
>+#define SDMA6_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
>+#define SDMA6_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
>+#define SDMA6_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
>+#define SDMA6_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
>+#define SDMA6_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
>+#define SDMA6_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
>+#define SDMA6_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
>+#define SDMA6_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
>+#define SDMA6_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
>+#define SDMA6_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
>+#define SDMA6_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
>+#define SDMA6_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
>+#define SDMA6_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
>+#define SDMA6_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
>+#define SDMA6_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
>+#define SDMA6_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
>+#define SDMA6_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
>+#define SDMA6_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
>+#define SDMA6_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
>+//SDMA6_STATUS1_REG
>+#define SDMA6_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
>+#define SDMA6_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
>+#define SDMA6_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
>+#define SDMA6_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
>+#define SDMA6_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
>+#define SDMA6_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
>+#define SDMA6_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
>+#define SDMA6_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
>+#define SDMA6_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
>+#define SDMA6_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
>+#define SDMA6_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
>+#define SDMA6_STATUS1_REG__EX_START__SHIFT                                                                    0xf
>+#define SDMA6_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
>+#define SDMA6_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
>+#define SDMA6_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
>+#define SDMA6_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
>+#define SDMA6_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
>+#define SDMA6_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
>+#define SDMA6_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
>+#define SDMA6_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
>+#define SDMA6_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
>+#define SDMA6_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
>+#define SDMA6_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
>+#define SDMA6_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
>+#define SDMA6_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
>+#define SDMA6_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
>+#define SDMA6_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
>+#define SDMA6_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
>+//SDMA6_RD_BURST_CNTL
>+#define SDMA6_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
>+#define SDMA6_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT                                                       0x2
>+#define SDMA6_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
>+#define SDMA6_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK                                                         0x0000000CL
>+//SDMA6_HBM_PAGE_CONFIG
>+#define SDMA6_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
>+#define SDMA6_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000001L
>+//SDMA6_UCODE_CHECKSUM
>+#define SDMA6_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
>+#define SDMA6_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_F32_CNTL
>+#define SDMA6_F32_CNTL__HALT__SHIFT                                                                           0x0
>+#define SDMA6_F32_CNTL__STEP__SHIFT                                                                           0x1
>+#define SDMA6_F32_CNTL__HALT_MASK                                                                             0x00000001L
>+#define SDMA6_F32_CNTL__STEP_MASK                                                                             0x00000002L
>+//SDMA6_FREEZE
>+#define SDMA6_FREEZE__PREEMPT__SHIFT                                                                          0x0
>+#define SDMA6_FREEZE__FREEZE__SHIFT                                                                           0x4
>+#define SDMA6_FREEZE__FROZEN__SHIFT                                                                           0x5
>+#define SDMA6_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
>+#define SDMA6_FREEZE__PREEMPT_MASK                                                                            0x00000001L
>+#define SDMA6_FREEZE__FREEZE_MASK                                                                             0x00000010L
>+#define SDMA6_FREEZE__FROZEN_MASK                                                                             0x00000020L
>+#define SDMA6_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
>+//SDMA6_PHASE0_QUANTUM
>+#define SDMA6_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA6_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA6_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA6_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA6_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA6_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA6_PHASE1_QUANTUM
>+#define SDMA6_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA6_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA6_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA6_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA6_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA6_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA6_EDC_CONFIG
>+#define SDMA6_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
>+#define SDMA6_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
>+#define SDMA6_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
>+#define SDMA6_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
>+//SDMA6_BA_THRESHOLD
>+#define SDMA6_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
>+#define SDMA6_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
>+#define SDMA6_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
>+#define SDMA6_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
>+//SDMA6_ID
>+#define SDMA6_ID__DEVICE_ID__SHIFT                                                                            0x0
>+#define SDMA6_ID__DEVICE_ID_MASK                                                                              0x000000FFL
>+//SDMA6_VERSION
>+#define SDMA6_VERSION__MINVER__SHIFT                                                                          0x0
>+#define SDMA6_VERSION__MAJVER__SHIFT                                                                          0x8
>+#define SDMA6_VERSION__REV__SHIFT                                                                             0x10
>+#define SDMA6_VERSION__MINVER_MASK                                                                            0x0000007FL
>+#define SDMA6_VERSION__MAJVER_MASK                                                                            0x00007F00L
>+#define SDMA6_VERSION__REV_MASK                                                                               0x003F0000L
>+//SDMA6_EDC_COUNTER
>+#define SDMA6_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT                                                          0x0
>+#define SDMA6_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
>+#define SDMA6_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
>+#define SDMA6_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
>+#define SDMA6_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
>+#define SDMA6_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT                                                    0xf
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT                                                    0x10
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT                                                   0x11
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT                                                   0x12
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT                                                   0x13
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT                                                   0x14
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT                                                   0x15
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT                                                   0x16
>+#define SDMA6_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0x17
>+#define SDMA6_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x18
>+#define SDMA6_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK                                                            0x00000001L
>+#define SDMA6_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
>+#define SDMA6_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
>+#define SDMA6_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
>+#define SDMA6_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
>+#define SDMA6_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK                                                      0x00008000L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK                                                      0x00010000L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK                                                     0x00020000L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK                                                     0x00040000L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK                                                     0x00080000L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK                                                     0x00100000L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK                                                     0x00200000L
>+#define SDMA6_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK                                                     0x00400000L
>+#define SDMA6_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00800000L
>+#define SDMA6_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x01000000L
>+//SDMA6_EDC_COUNTER_CLEAR
>+#define SDMA6_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
>+#define SDMA6_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
>+//SDMA6_STATUS2_REG
>+#define SDMA6_STATUS2_REG__ID__SHIFT                                                                          0x0
>+#define SDMA6_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x3
>+#define SDMA6_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
>+#define SDMA6_STATUS2_REG__ID_MASK                                                                            0x00000007L
>+#define SDMA6_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFF8L
>+#define SDMA6_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
>+//SDMA6_ATOMIC_CNTL
>+#define SDMA6_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
>+#define SDMA6_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
>+#define SDMA6_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
>+#define SDMA6_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
>+//SDMA6_ATOMIC_PREOP_LO
>+#define SDMA6_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
>+#define SDMA6_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_ATOMIC_PREOP_HI
>+#define SDMA6_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
>+#define SDMA6_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_UTCL1_CNTL
>+#define SDMA6_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
>+#define SDMA6_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0xb
>+#define SDMA6_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0xe
>+#define SDMA6_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
>+#define SDMA6_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
>+#define SDMA6_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x000007FEL
>+#define SDMA6_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x00003800L
>+#define SDMA6_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FFC000L
>+#define SDMA6_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
>+#define SDMA6_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
>+//SDMA6_UTCL1_WATERMK
>+#define SDMA6_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
>+#define SDMA6_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0x9
>+#define SDMA6_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x11
>+#define SDMA6_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x19
>+#define SDMA6_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000001FFL
>+#define SDMA6_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0001FE00L
>+#define SDMA6_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x01FE0000L
>+#define SDMA6_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFE000000L
>+//SDMA6_UTCL1_RD_STATUS
>+#define SDMA6_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA6_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA6_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA6_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA6_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA6_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA6_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA6_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA6_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA6_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA6_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA6_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT                                                             0x15
>+#define SDMA6_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x16
>+#define SDMA6_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x1a
>+#define SDMA6_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x1d
>+#define SDMA6_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT                                                            0x1e
>+#define SDMA6_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT                                                             0x1f
>+#define SDMA6_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA6_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA6_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA6_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA6_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA6_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA6_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA6_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA6_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA6_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA6_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA6_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA6_UTCL1_RD_STATUS__CE_L1_STALL_MASK                                                               0x00200000L
>+#define SDMA6_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x03C00000L
>+#define SDMA6_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x1C000000L
>+#define SDMA6_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x20000000L
>+#define SDMA6_UTCL1_RD_STATUS__WPTR_POLLING_MASK                                                              0x40000000L
>+#define SDMA6_UTCL1_RD_STATUS__INVREQ_SIZE_MASK                                                               0x80000000L
>+//SDMA6_UTCL1_WR_STATUS
>+#define SDMA6_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA6_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA6_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA6_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA6_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA6_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA6_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA6_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA6_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA6_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA6_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA6_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15
>+#define SDMA6_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x16
>+#define SDMA6_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19
>+#define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
>+#define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
>+#define SDMA6_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
>+#define SDMA6_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
>+#define SDMA6_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA6_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA6_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA6_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA6_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA6_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA6_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA6_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA6_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA6_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA6_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA6_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA6_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x00200000L
>+#define SDMA6_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x01C00000L
>+#define SDMA6_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x0E000000L
>+#define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
>+#define SDMA6_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
>+#define SDMA6_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
>+#define SDMA6_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
>+//SDMA6_UTCL1_INV0
>+#define SDMA6_UTCL1_INV0__INV_MIDDLE__SHIFT                                                                   0x0
>+#define SDMA6_UTCL1_INV0__RD_TIMEOUT__SHIFT                                                                   0x1
>+#define SDMA6_UTCL1_INV0__WR_TIMEOUT__SHIFT                                                                   0x2
>+#define SDMA6_UTCL1_INV0__RD_IN_INVADR__SHIFT                                                                 0x3
>+#define SDMA6_UTCL1_INV0__WR_IN_INVADR__SHIFT                                                                 0x4
>+#define SDMA6_UTCL1_INV0__PAGE_NULL_SW__SHIFT                                                                 0x5
>+#define SDMA6_UTCL1_INV0__XNACK_IS_INVADR__SHIFT                                                              0x6
>+#define SDMA6_UTCL1_INV0__INVREQ_ENABLE__SHIFT                                                                0x7
>+#define SDMA6_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT                                                              0x8
>+#define SDMA6_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT                                                              0x9
>+#define SDMA6_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT                                                               0xa
>+#define SDMA6_UTCL1_INV0__INV_FLUSHTYPE__SHIFT                                                                0xb
>+#define SDMA6_UTCL1_INV0__INV_VMID_VEC__SHIFT                                                                 0xc
>+#define SDMA6_UTCL1_INV0__INV_ADDR_HI__SHIFT                                                                  0x1c
>+#define SDMA6_UTCL1_INV0__INV_MIDDLE_MASK                                                                     0x00000001L
>+#define SDMA6_UTCL1_INV0__RD_TIMEOUT_MASK                                                                     0x00000002L
>+#define SDMA6_UTCL1_INV0__WR_TIMEOUT_MASK                                                                     0x00000004L
>+#define SDMA6_UTCL1_INV0__RD_IN_INVADR_MASK                                                                   0x00000008L
>+#define SDMA6_UTCL1_INV0__WR_IN_INVADR_MASK                                                                   0x00000010L
>+#define SDMA6_UTCL1_INV0__PAGE_NULL_SW_MASK                                                                   0x00000020L
>+#define SDMA6_UTCL1_INV0__XNACK_IS_INVADR_MASK                                                                0x00000040L
>+#define SDMA6_UTCL1_INV0__INVREQ_ENABLE_MASK                                                                  0x00000080L
>+#define SDMA6_UTCL1_INV0__NACK_TIMEOUT_SW_MASK                                                                0x00000100L
>+#define SDMA6_UTCL1_INV0__NFLUSH_INV_IDLE_MASK                                                                0x00000200L
>+#define SDMA6_UTCL1_INV0__FLUSH_INV_IDLE_MASK                                                                 0x00000400L
>+#define SDMA6_UTCL1_INV0__INV_FLUSHTYPE_MASK                                                                  0x00000800L
>+#define SDMA6_UTCL1_INV0__INV_VMID_VEC_MASK                                                                   0x0FFFF000L
>+#define SDMA6_UTCL1_INV0__INV_ADDR_HI_MASK                                                                    0xF0000000L
>+//SDMA6_UTCL1_INV1
>+#define SDMA6_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
>+#define SDMA6_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_UTCL1_INV2
>+#define SDMA6_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT                                                          0x0
>+#define SDMA6_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK                                                            0xFFFFFFFFL
>+//SDMA6_UTCL1_RD_XNACK0
>+#define SDMA6_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA6_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA6_UTCL1_RD_XNACK1
>+#define SDMA6_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA6_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA6_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA6_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA6_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA6_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA6_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA6_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA6_UTCL1_WR_XNACK0
>+#define SDMA6_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA6_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA6_UTCL1_WR_XNACK1
>+#define SDMA6_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA6_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA6_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA6_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA6_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA6_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA6_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA6_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA6_UTCL1_TIMEOUT
>+#define SDMA6_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
>+#define SDMA6_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
>+#define SDMA6_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
>+#define SDMA6_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
>+//SDMA6_UTCL1_PAGE
>+#define SDMA6_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
>+#define SDMA6_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
>+#define SDMA6_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
>+#define SDMA6_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0x9
>+#define SDMA6_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
>+#define SDMA6_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
>+#define SDMA6_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000001C0L
>+#define SDMA6_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000200L
>+//SDMA6_POWER_CNTL_IDLE
>+#define SDMA6_POWER_CNTL_IDLE__DELAY0__SHIFT                                                                  0x0
>+#define SDMA6_POWER_CNTL_IDLE__DELAY1__SHIFT                                                                  0x10
>+#define SDMA6_POWER_CNTL_IDLE__DELAY2__SHIFT                                                                  0x18
>+#define SDMA6_POWER_CNTL_IDLE__DELAY0_MASK                                                                    0x0000FFFFL
>+#define SDMA6_POWER_CNTL_IDLE__DELAY1_MASK                                                                    0x00FF0000L
>+#define SDMA6_POWER_CNTL_IDLE__DELAY2_MASK                                                                    0xFF000000L
>+//SDMA6_RELAX_ORDERING_LUT
>+#define SDMA6_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
>+#define SDMA6_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
>+#define SDMA6_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
>+#define SDMA6_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
>+#define SDMA6_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
>+#define SDMA6_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
>+#define SDMA6_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
>+#define SDMA6_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
>+#define SDMA6_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
>+#define SDMA6_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
>+#define SDMA6_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
>+#define SDMA6_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
>+#define SDMA6_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
>+#define SDMA6_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
>+#define SDMA6_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
>+#define SDMA6_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
>+#define SDMA6_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
>+#define SDMA6_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
>+#define SDMA6_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
>+#define SDMA6_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
>+#define SDMA6_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
>+#define SDMA6_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
>+#define SDMA6_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
>+#define SDMA6_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
>+#define SDMA6_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
>+#define SDMA6_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
>+#define SDMA6_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
>+#define SDMA6_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
>+#define SDMA6_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
>+#define SDMA6_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
>+#define SDMA6_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
>+#define SDMA6_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
>+#define SDMA6_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
>+#define SDMA6_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
>+#define SDMA6_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
>+#define SDMA6_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
>+#define SDMA6_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
>+#define SDMA6_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
>+//SDMA6_CHICKEN_BITS_2
>+#define SDMA6_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
>+#define SDMA6_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
>+//SDMA6_STATUS3_REG
>+#define SDMA6_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
>+#define SDMA6_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
>+#define SDMA6_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
>+#define SDMA6_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x15
>+#define SDMA6_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x16
>+#define SDMA6_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
>+#define SDMA6_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
>+#define SDMA6_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
>+#define SDMA6_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x00200000L
>+#define SDMA6_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x03C00000L
>+//SDMA6_PHYSICAL_ADDR_LO
>+#define SDMA6_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
>+#define SDMA6_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
>+#define SDMA6_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
>+#define SDMA6_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
>+#define SDMA6_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
>+#define SDMA6_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
>+#define SDMA6_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
>+#define SDMA6_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
>+//SDMA6_PHYSICAL_ADDR_HI
>+#define SDMA6_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA6_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
>+//SDMA6_PHASE2_QUANTUM
>+#define SDMA6_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA6_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA6_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA6_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA6_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA6_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA6_ERROR_LOG
>+#define SDMA6_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
>+#define SDMA6_ERROR_LOG__STATUS__SHIFT                                                                        0x10
>+#define SDMA6_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
>+#define SDMA6_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
>+//SDMA6_PUB_DUMMY_REG0
>+#define SDMA6_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
>+#define SDMA6_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_PUB_DUMMY_REG1
>+#define SDMA6_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
>+#define SDMA6_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_PUB_DUMMY_REG2
>+#define SDMA6_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
>+#define SDMA6_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_PUB_DUMMY_REG3
>+#define SDMA6_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
>+#define SDMA6_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_F32_COUNTER
>+#define SDMA6_F32_COUNTER__VALUE__SHIFT                                                                       0x0
>+#define SDMA6_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
>+//SDMA6_UNBREAKABLE
>+#define SDMA6_UNBREAKABLE__VALUE__SHIFT                                                                       0x0
>+#define SDMA6_UNBREAKABLE__VALUE_MASK                                                                         0x00000001L
>+//SDMA6_PERFMON_CNTL
>+#define SDMA6_PERFMON_CNTL__PERF_ENABLE0__SHIFT                                                               0x0
>+#define SDMA6_PERFMON_CNTL__PERF_CLEAR0__SHIFT                                                                0x1
>+#define SDMA6_PERFMON_CNTL__PERF_SEL0__SHIFT                                                                  0x2
>+#define SDMA6_PERFMON_CNTL__PERF_ENABLE1__SHIFT                                                               0xa
>+#define SDMA6_PERFMON_CNTL__PERF_CLEAR1__SHIFT                                                                0xb
>+#define SDMA6_PERFMON_CNTL__PERF_SEL1__SHIFT                                                                  0xc
>+#define SDMA6_PERFMON_CNTL__PERF_ENABLE0_MASK                                                                 0x00000001L
>+#define SDMA6_PERFMON_CNTL__PERF_CLEAR0_MASK                                                                  0x00000002L
>+#define SDMA6_PERFMON_CNTL__PERF_SEL0_MASK                                                                    0x000003FCL
>+#define SDMA6_PERFMON_CNTL__PERF_ENABLE1_MASK                                                                 0x00000400L
>+#define SDMA6_PERFMON_CNTL__PERF_CLEAR1_MASK                                                                  0x00000800L
>+#define SDMA6_PERFMON_CNTL__PERF_SEL1_MASK                                                                    0x000FF000L
>+//SDMA6_PERFCOUNTER0_RESULT
>+#define SDMA6_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA6_PERFCOUNTER0_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA6_PERFCOUNTER1_RESULT
>+#define SDMA6_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA6_PERFCOUNTER1_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA6_PERFCOUNTER_TAG_DELAY_RANGE
>+#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT                                                   0x0
>+#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT                                                  0xe
>+#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT                                                   0x1c
>+#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK                                                     0x00003FFFL
>+#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK                                                    0x0FFFC000L
>+#define SDMA6_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK                                                     0x10000000L
>+//SDMA6_CRD_CNTL
>+#define SDMA6_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
>+#define SDMA6_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
>+#define SDMA6_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
>+#define SDMA6_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
>+//SDMA6_GPU_IOV_VIOLATION_LOG
>+#define SDMA6_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT                                                  0x0
>+#define SDMA6_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT                                         0x1
>+#define SDMA6_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT                                                           0x2
>+#define SDMA6_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT                                                   0x14
>+#define SDMA6_GPU_IOV_VIOLATION_LOG__VF__SHIFT                                                                0x15
>+#define SDMA6_GPU_IOV_VIOLATION_LOG__VFID__SHIFT                                                              0x16
>+#define SDMA6_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK                                                    0x00000001L
>+#define SDMA6_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK                                           0x00000002L
>+#define SDMA6_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK                                                             0x000FFFFCL
>+#define SDMA6_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK                                                     0x00100000L
>+#define SDMA6_GPU_IOV_VIOLATION_LOG__VF_MASK                                                                  0x00200000L
>+#define SDMA6_GPU_IOV_VIOLATION_LOG__VFID_MASK                                                                0x03C00000L
>+//SDMA6_ULV_CNTL
>+#define SDMA6_ULV_CNTL__HYSTERESIS__SHIFT                                                                     0x0
>+#define SDMA6_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT                                                              0x1b
>+#define SDMA6_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT                                                               0x1c
>+#define SDMA6_ULV_CNTL__ENTER_ULV_INT__SHIFT                                                                  0x1d
>+#define SDMA6_ULV_CNTL__EXIT_ULV_INT__SHIFT                                                                   0x1e
>+#define SDMA6_ULV_CNTL__ULV_STATUS__SHIFT                                                                     0x1f
>+#define SDMA6_ULV_CNTL__HYSTERESIS_MASK                                                                       0x0000001FL
>+#define SDMA6_ULV_CNTL__ENTER_ULV_INT_CLR_MASK                                                                0x08000000L
>+#define SDMA6_ULV_CNTL__EXIT_ULV_INT_CLR_MASK                                                                 0x10000000L
>+#define SDMA6_ULV_CNTL__ENTER_ULV_INT_MASK                                                                    0x20000000L
>+#define SDMA6_ULV_CNTL__EXIT_ULV_INT_MASK                                                                     0x40000000L
>+#define SDMA6_ULV_CNTL__ULV_STATUS_MASK                                                                       0x80000000L
>+//SDMA6_EA_DBIT_ADDR_DATA
>+#define SDMA6_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
>+#define SDMA6_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_EA_DBIT_ADDR_INDEX
>+#define SDMA6_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
>+#define SDMA6_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
>+//SDMA6_GPU_IOV_VIOLATION_LOG2
>+#define SDMA6_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                     0x0
>+#define SDMA6_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                       0x000000FFL
>+//SDMA6_GFX_RB_CNTL
>+#define SDMA6_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA6_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
>+#define SDMA6_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
>+#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
>+#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
>+#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
>+#define SDMA6_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
>+#define SDMA6_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
>+#define SDMA6_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA6_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
>+#define SDMA6_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
>+#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
>+#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
>+#define SDMA6_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
>+#define SDMA6_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
>+#define SDMA6_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
>+//SDMA6_GFX_RB_BASE
>+#define SDMA6_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
>+#define SDMA6_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
>+//SDMA6_GFX_RB_BASE_HI
>+#define SDMA6_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA6_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
>+//SDMA6_GFX_RB_RPTR
>+#define SDMA6_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA6_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA6_GFX_RB_RPTR_HI
>+#define SDMA6_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA6_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA6_GFX_RB_WPTR
>+#define SDMA6_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA6_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA6_GFX_RB_WPTR_HI
>+#define SDMA6_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA6_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA6_GFX_RB_WPTR_POLL_CNTL
>+#define SDMA6_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
>+#define SDMA6_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
>+#define SDMA6_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
>+#define SDMA6_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
>+#define SDMA6_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
>+#define SDMA6_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
>+#define SDMA6_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
>+#define SDMA6_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
>+#define SDMA6_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
>+#define SDMA6_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
>+//SDMA6_GFX_RB_RPTR_ADDR_HI
>+#define SDMA6_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
>+#define SDMA6_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
>+//SDMA6_GFX_RB_RPTR_ADDR_LO
>+#define SDMA6_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                        0x0
>+#define SDMA6_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
>+#define SDMA6_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                          0x00000001L
>+#define SDMA6_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
>+//SDMA6_GFX_IB_CNTL
>+#define SDMA6_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA6_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
>+#define SDMA6_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
>+#define SDMA6_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
>+#define SDMA6_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA6_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
>+#define SDMA6_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
>+#define SDMA6_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
>+//SDMA6_GFX_IB_RPTR
>+#define SDMA6_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
>+#define SDMA6_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
>+//SDMA6_GFX_IB_OFFSET
>+#define SDMA6_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
>+#define SDMA6_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
>+//SDMA6_GFX_IB_BASE_LO
>+#define SDMA6_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
>+#define SDMA6_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
>+//SDMA6_GFX_IB_BASE_HI
>+#define SDMA6_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA6_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_GFX_IB_SIZE
>+#define SDMA6_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
>+#define SDMA6_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
>+//SDMA6_GFX_SKIP_CNTL
>+#define SDMA6_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
>+#define SDMA6_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
>+//SDMA6_GFX_CONTEXT_STATUS
>+#define SDMA6_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
>+#define SDMA6_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
>+#define SDMA6_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
>+#define SDMA6_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
>+#define SDMA6_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
>+#define SDMA6_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
>+#define SDMA6_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
>+#define SDMA6_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
>+#define SDMA6_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
>+#define SDMA6_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
>+#define SDMA6_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
>+#define SDMA6_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
>+#define SDMA6_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
>+#define SDMA6_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
>+#define SDMA6_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
>+#define SDMA6_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
>+//SDMA6_GFX_DOORBELL
>+#define SDMA6_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
>+#define SDMA6_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
>+#define SDMA6_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
>+#define SDMA6_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
>+//SDMA6_GFX_CONTEXT_CNTL
>+#define SDMA6_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
>+#define SDMA6_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
>+//SDMA6_GFX_STATUS
>+#define SDMA6_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
>+#define SDMA6_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
>+#define SDMA6_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
>+#define SDMA6_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
>+//SDMA6_GFX_DOORBELL_LOG
>+#define SDMA6_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
>+#define SDMA6_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
>+#define SDMA6_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
>+#define SDMA6_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
>+//SDMA6_GFX_WATERMARK
>+#define SDMA6_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
>+#define SDMA6_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
>+#define SDMA6_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
>+#define SDMA6_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
>+//SDMA6_GFX_DOORBELL_OFFSET
>+#define SDMA6_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
>+#define SDMA6_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
>+//SDMA6_GFX_CSA_ADDR_LO
>+#define SDMA6_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
>+#define SDMA6_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
>+//SDMA6_GFX_CSA_ADDR_HI
>+#define SDMA6_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_GFX_IB_SUB_REMAIN
>+#define SDMA6_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
>+#define SDMA6_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x000FFFFFL
>+//SDMA6_GFX_PREEMPT
>+#define SDMA6_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
>+#define SDMA6_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
>+//SDMA6_GFX_DUMMY_REG
>+#define SDMA6_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
>+#define SDMA6_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_GFX_RB_WPTR_POLL_ADDR_HI
>+#define SDMA6_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
>+#define SDMA6_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
>+//SDMA6_GFX_RB_WPTR_POLL_ADDR_LO
>+#define SDMA6_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
>+#define SDMA6_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
>+//SDMA6_GFX_RB_AQL_CNTL
>+#define SDMA6_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
>+#define SDMA6_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
>+#define SDMA6_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
>+#define SDMA6_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
>+#define SDMA6_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
>+#define SDMA6_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
>+//SDMA6_GFX_MINOR_PTR_UPDATE
>+#define SDMA6_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
>+#define SDMA6_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
>+//SDMA6_GFX_MIDCMD_DATA0
>+#define SDMA6_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
>+#define SDMA6_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_GFX_MIDCMD_DATA1
>+#define SDMA6_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
>+#define SDMA6_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_GFX_MIDCMD_DATA2
>+#define SDMA6_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
>+#define SDMA6_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_GFX_MIDCMD_DATA3
>+#define SDMA6_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
>+#define SDMA6_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_GFX_MIDCMD_DATA4
>+#define SDMA6_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
>+#define SDMA6_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_GFX_MIDCMD_DATA5
>+#define SDMA6_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
>+#define SDMA6_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_GFX_MIDCMD_DATA6
>+#define SDMA6_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
>+#define SDMA6_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_GFX_MIDCMD_DATA7
>+#define SDMA6_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
>+#define SDMA6_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_GFX_MIDCMD_DATA8
>+#define SDMA6_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
>+#define SDMA6_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_GFX_MIDCMD_CNTL
>+#define SDMA6_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
>+#define SDMA6_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
>+#define SDMA6_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
>+#define SDMA6_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
>+#define SDMA6_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
>+#define SDMA6_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
>+#define SDMA6_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
>+#define SDMA6_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
>+//SDMA6_PAGE_RB_CNTL
>+#define SDMA6_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA6_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA6_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA6_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA6_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA6_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA6_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA6_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA6_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA6_PAGE_RB_BASE
>+#define SDMA6_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA6_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA6_PAGE_RB_BASE_HI
>+#define SDMA6_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA6_PAGE_RB_RPTR
>+#define SDMA6_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_PAGE_RB_RPTR_HI
>+#define SDMA6_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_PAGE_RB_WPTR
>+#define SDMA6_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_PAGE_RB_WPTR_HI
>+#define SDMA6_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_PAGE_RB_WPTR_POLL_CNTL
>+#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA6_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA6_PAGE_RB_RPTR_ADDR_HI
>+#define SDMA6_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA6_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA6_PAGE_RB_RPTR_ADDR_LO
>+#define SDMA6_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA6_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA6_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA6_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA6_PAGE_IB_CNTL
>+#define SDMA6_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA6_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA6_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA6_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA6_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA6_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA6_PAGE_IB_RPTR
>+#define SDMA6_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA6_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA6_PAGE_IB_OFFSET
>+#define SDMA6_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA6_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA6_PAGE_IB_BASE_LO
>+#define SDMA6_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA6_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA6_PAGE_IB_BASE_HI
>+#define SDMA6_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_PAGE_IB_SIZE
>+#define SDMA6_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA6_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA6_PAGE_SKIP_CNTL
>+#define SDMA6_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA6_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA6_PAGE_CONTEXT_STATUS
>+#define SDMA6_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA6_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA6_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA6_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA6_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA6_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA6_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA6_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA6_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA6_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA6_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA6_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA6_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA6_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA6_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA6_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA6_PAGE_DOORBELL
>+#define SDMA6_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA6_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA6_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA6_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA6_PAGE_STATUS
>+#define SDMA6_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA6_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA6_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA6_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA6_PAGE_DOORBELL_LOG
>+#define SDMA6_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA6_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA6_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA6_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA6_PAGE_WATERMARK
>+#define SDMA6_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA6_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA6_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA6_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA6_PAGE_DOORBELL_OFFSET
>+#define SDMA6_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA6_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA6_PAGE_CSA_ADDR_LO
>+#define SDMA6_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA6_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA6_PAGE_CSA_ADDR_HI
>+#define SDMA6_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA6_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA6_PAGE_IB_SUB_REMAIN
>+#define SDMA6_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA6_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA6_PAGE_PREEMPT
>+#define SDMA6_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA6_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA6_PAGE_DUMMY_REG
>+#define SDMA6_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA6_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_PAGE_RB_WPTR_POLL_ADDR_HI
>+#define SDMA6_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA6_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA6_PAGE_RB_WPTR_POLL_ADDR_LO
>+#define SDMA6_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA6_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA6_PAGE_RB_AQL_CNTL
>+#define SDMA6_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA6_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA6_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA6_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA6_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA6_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA6_PAGE_MINOR_PTR_UPDATE
>+#define SDMA6_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA6_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA6_PAGE_MIDCMD_DATA0
>+#define SDMA6_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA6_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_PAGE_MIDCMD_DATA1
>+#define SDMA6_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA6_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_PAGE_MIDCMD_DATA2
>+#define SDMA6_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA6_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_PAGE_MIDCMD_DATA3
>+#define SDMA6_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA6_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_PAGE_MIDCMD_DATA4
>+#define SDMA6_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA6_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_PAGE_MIDCMD_DATA5
>+#define SDMA6_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA6_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_PAGE_MIDCMD_DATA6
>+#define SDMA6_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA6_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_PAGE_MIDCMD_DATA7
>+#define SDMA6_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA6_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_PAGE_MIDCMD_DATA8
>+#define SDMA6_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA6_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_PAGE_MIDCMD_CNTL
>+#define SDMA6_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA6_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA6_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA6_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA6_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA6_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA6_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA6_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA6_RLC0_RB_CNTL
>+#define SDMA6_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA6_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA6_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA6_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA6_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA6_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA6_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA6_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA6_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA6_RLC0_RB_BASE
>+#define SDMA6_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA6_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA6_RLC0_RB_BASE_HI
>+#define SDMA6_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA6_RLC0_RB_RPTR
>+#define SDMA6_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC0_RB_RPTR_HI
>+#define SDMA6_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC0_RB_WPTR
>+#define SDMA6_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC0_RB_WPTR_HI
>+#define SDMA6_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC0_RB_WPTR_POLL_CNTL
>+#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA6_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA6_RLC0_RB_RPTR_ADDR_HI
>+#define SDMA6_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA6_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA6_RLC0_RB_RPTR_ADDR_LO
>+#define SDMA6_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA6_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA6_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA6_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA6_RLC0_IB_CNTL
>+#define SDMA6_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA6_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA6_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA6_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA6_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA6_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA6_RLC0_IB_RPTR
>+#define SDMA6_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA6_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA6_RLC0_IB_OFFSET
>+#define SDMA6_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA6_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA6_RLC0_IB_BASE_LO
>+#define SDMA6_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA6_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA6_RLC0_IB_BASE_HI
>+#define SDMA6_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC0_IB_SIZE
>+#define SDMA6_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA6_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA6_RLC0_SKIP_CNTL
>+#define SDMA6_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA6_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA6_RLC0_CONTEXT_STATUS
>+#define SDMA6_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA6_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA6_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA6_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA6_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA6_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA6_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA6_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA6_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA6_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA6_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA6_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA6_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA6_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA6_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA6_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA6_RLC0_DOORBELL
>+#define SDMA6_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA6_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA6_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA6_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA6_RLC0_STATUS
>+#define SDMA6_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA6_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA6_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA6_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA6_RLC0_DOORBELL_LOG
>+#define SDMA6_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA6_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA6_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA6_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA6_RLC0_WATERMARK
>+#define SDMA6_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA6_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA6_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA6_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA6_RLC0_DOORBELL_OFFSET
>+#define SDMA6_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA6_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA6_RLC0_CSA_ADDR_LO
>+#define SDMA6_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA6_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA6_RLC0_CSA_ADDR_HI
>+#define SDMA6_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA6_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA6_RLC0_IB_SUB_REMAIN
>+#define SDMA6_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA6_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA6_RLC0_PREEMPT
>+#define SDMA6_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA6_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA6_RLC0_DUMMY_REG
>+#define SDMA6_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA6_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC0_RB_WPTR_POLL_ADDR_HI
>+#define SDMA6_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA6_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA6_RLC0_RB_WPTR_POLL_ADDR_LO
>+#define SDMA6_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA6_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA6_RLC0_RB_AQL_CNTL
>+#define SDMA6_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA6_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA6_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA6_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA6_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA6_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA6_RLC0_MINOR_PTR_UPDATE
>+#define SDMA6_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA6_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA6_RLC0_MIDCMD_DATA0
>+#define SDMA6_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA6_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC0_MIDCMD_DATA1
>+#define SDMA6_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA6_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC0_MIDCMD_DATA2
>+#define SDMA6_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA6_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC0_MIDCMD_DATA3
>+#define SDMA6_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA6_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC0_MIDCMD_DATA4
>+#define SDMA6_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA6_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC0_MIDCMD_DATA5
>+#define SDMA6_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA6_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC0_MIDCMD_DATA6
>+#define SDMA6_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA6_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC0_MIDCMD_DATA7
>+#define SDMA6_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA6_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC0_MIDCMD_DATA8
>+#define SDMA6_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA6_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC0_MIDCMD_CNTL
>+#define SDMA6_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA6_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA6_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA6_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA6_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA6_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA6_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA6_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA6_RLC1_RB_CNTL
>+#define SDMA6_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA6_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA6_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA6_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA6_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA6_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA6_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA6_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA6_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA6_RLC1_RB_BASE
>+#define SDMA6_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA6_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA6_RLC1_RB_BASE_HI
>+#define SDMA6_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA6_RLC1_RB_RPTR
>+#define SDMA6_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC1_RB_RPTR_HI
>+#define SDMA6_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC1_RB_WPTR
>+#define SDMA6_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC1_RB_WPTR_HI
>+#define SDMA6_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC1_RB_WPTR_POLL_CNTL
>+#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA6_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA6_RLC1_RB_RPTR_ADDR_HI
>+#define SDMA6_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA6_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA6_RLC1_RB_RPTR_ADDR_LO
>+#define SDMA6_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA6_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA6_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA6_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA6_RLC1_IB_CNTL
>+#define SDMA6_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA6_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA6_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA6_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA6_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA6_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA6_RLC1_IB_RPTR
>+#define SDMA6_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA6_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA6_RLC1_IB_OFFSET
>+#define SDMA6_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA6_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA6_RLC1_IB_BASE_LO
>+#define SDMA6_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA6_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA6_RLC1_IB_BASE_HI
>+#define SDMA6_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC1_IB_SIZE
>+#define SDMA6_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA6_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA6_RLC1_SKIP_CNTL
>+#define SDMA6_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA6_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA6_RLC1_CONTEXT_STATUS
>+#define SDMA6_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA6_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA6_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA6_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA6_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA6_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA6_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA6_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA6_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA6_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA6_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA6_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA6_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA6_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA6_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA6_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA6_RLC1_DOORBELL
>+#define SDMA6_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA6_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA6_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA6_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA6_RLC1_STATUS
>+#define SDMA6_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA6_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA6_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA6_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA6_RLC1_DOORBELL_LOG
>+#define SDMA6_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA6_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA6_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA6_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA6_RLC1_WATERMARK
>+#define SDMA6_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA6_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA6_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA6_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA6_RLC1_DOORBELL_OFFSET
>+#define SDMA6_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA6_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA6_RLC1_CSA_ADDR_LO
>+#define SDMA6_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA6_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA6_RLC1_CSA_ADDR_HI
>+#define SDMA6_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA6_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA6_RLC1_IB_SUB_REMAIN
>+#define SDMA6_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA6_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA6_RLC1_PREEMPT
>+#define SDMA6_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA6_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA6_RLC1_DUMMY_REG
>+#define SDMA6_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA6_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC1_RB_WPTR_POLL_ADDR_HI
>+#define SDMA6_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA6_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA6_RLC1_RB_WPTR_POLL_ADDR_LO
>+#define SDMA6_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA6_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA6_RLC1_RB_AQL_CNTL
>+#define SDMA6_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA6_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA6_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA6_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA6_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA6_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA6_RLC1_MINOR_PTR_UPDATE
>+#define SDMA6_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA6_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA6_RLC1_MIDCMD_DATA0
>+#define SDMA6_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA6_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC1_MIDCMD_DATA1
>+#define SDMA6_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA6_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC1_MIDCMD_DATA2
>+#define SDMA6_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA6_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC1_MIDCMD_DATA3
>+#define SDMA6_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA6_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC1_MIDCMD_DATA4
>+#define SDMA6_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA6_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC1_MIDCMD_DATA5
>+#define SDMA6_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA6_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC1_MIDCMD_DATA6
>+#define SDMA6_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA6_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC1_MIDCMD_DATA7
>+#define SDMA6_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA6_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC1_MIDCMD_DATA8
>+#define SDMA6_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA6_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC1_MIDCMD_CNTL
>+#define SDMA6_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA6_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA6_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA6_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA6_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA6_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA6_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA6_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA6_RLC2_RB_CNTL
>+#define SDMA6_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA6_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA6_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA6_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA6_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA6_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA6_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA6_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA6_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA6_RLC2_RB_BASE
>+#define SDMA6_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA6_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA6_RLC2_RB_BASE_HI
>+#define SDMA6_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA6_RLC2_RB_RPTR
>+#define SDMA6_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC2_RB_RPTR_HI
>+#define SDMA6_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC2_RB_WPTR
>+#define SDMA6_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC2_RB_WPTR_HI
>+#define SDMA6_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC2_RB_WPTR_POLL_CNTL
>+#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA6_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA6_RLC2_RB_RPTR_ADDR_HI
>+#define SDMA6_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA6_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA6_RLC2_RB_RPTR_ADDR_LO
>+#define SDMA6_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA6_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA6_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA6_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA6_RLC2_IB_CNTL
>+#define SDMA6_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA6_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA6_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA6_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA6_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA6_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA6_RLC2_IB_RPTR
>+#define SDMA6_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA6_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA6_RLC2_IB_OFFSET
>+#define SDMA6_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA6_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA6_RLC2_IB_BASE_LO
>+#define SDMA6_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA6_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA6_RLC2_IB_BASE_HI
>+#define SDMA6_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC2_IB_SIZE
>+#define SDMA6_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA6_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA6_RLC2_SKIP_CNTL
>+#define SDMA6_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA6_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA6_RLC2_CONTEXT_STATUS
>+#define SDMA6_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA6_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA6_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA6_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA6_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA6_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA6_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA6_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA6_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA6_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA6_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA6_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA6_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA6_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA6_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA6_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA6_RLC2_DOORBELL
>+#define SDMA6_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA6_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA6_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA6_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA6_RLC2_STATUS
>+#define SDMA6_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA6_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA6_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA6_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA6_RLC2_DOORBELL_LOG
>+#define SDMA6_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA6_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA6_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA6_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA6_RLC2_WATERMARK
>+#define SDMA6_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA6_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA6_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA6_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA6_RLC2_DOORBELL_OFFSET
>+#define SDMA6_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA6_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA6_RLC2_CSA_ADDR_LO
>+#define SDMA6_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA6_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA6_RLC2_CSA_ADDR_HI
>+#define SDMA6_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA6_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA6_RLC2_IB_SUB_REMAIN
>+#define SDMA6_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA6_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA6_RLC2_PREEMPT
>+#define SDMA6_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA6_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA6_RLC2_DUMMY_REG
>+#define SDMA6_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA6_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC2_RB_WPTR_POLL_ADDR_HI
>+#define SDMA6_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA6_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA6_RLC2_RB_WPTR_POLL_ADDR_LO
>+#define SDMA6_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA6_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA6_RLC2_RB_AQL_CNTL
>+#define SDMA6_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA6_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA6_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA6_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA6_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA6_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA6_RLC2_MINOR_PTR_UPDATE
>+#define SDMA6_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA6_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA6_RLC2_MIDCMD_DATA0
>+#define SDMA6_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA6_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC2_MIDCMD_DATA1
>+#define SDMA6_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA6_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC2_MIDCMD_DATA2
>+#define SDMA6_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA6_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC2_MIDCMD_DATA3
>+#define SDMA6_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA6_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC2_MIDCMD_DATA4
>+#define SDMA6_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA6_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC2_MIDCMD_DATA5
>+#define SDMA6_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA6_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC2_MIDCMD_DATA6
>+#define SDMA6_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA6_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC2_MIDCMD_DATA7
>+#define SDMA6_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA6_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC2_MIDCMD_DATA8
>+#define SDMA6_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA6_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC2_MIDCMD_CNTL
>+#define SDMA6_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA6_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA6_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA6_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA6_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA6_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA6_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA6_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA6_RLC3_RB_CNTL
>+#define SDMA6_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA6_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA6_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA6_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA6_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA6_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA6_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA6_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA6_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA6_RLC3_RB_BASE
>+#define SDMA6_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA6_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA6_RLC3_RB_BASE_HI
>+#define SDMA6_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA6_RLC3_RB_RPTR
>+#define SDMA6_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC3_RB_RPTR_HI
>+#define SDMA6_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC3_RB_WPTR
>+#define SDMA6_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC3_RB_WPTR_HI
>+#define SDMA6_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC3_RB_WPTR_POLL_CNTL
>+#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA6_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA6_RLC3_RB_RPTR_ADDR_HI
>+#define SDMA6_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA6_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA6_RLC3_RB_RPTR_ADDR_LO
>+#define SDMA6_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA6_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA6_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA6_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA6_RLC3_IB_CNTL
>+#define SDMA6_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA6_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA6_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA6_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA6_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA6_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA6_RLC3_IB_RPTR
>+#define SDMA6_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA6_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA6_RLC3_IB_OFFSET
>+#define SDMA6_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA6_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA6_RLC3_IB_BASE_LO
>+#define SDMA6_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA6_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA6_RLC3_IB_BASE_HI
>+#define SDMA6_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC3_IB_SIZE
>+#define SDMA6_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA6_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA6_RLC3_SKIP_CNTL
>+#define SDMA6_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA6_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA6_RLC3_CONTEXT_STATUS
>+#define SDMA6_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA6_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA6_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA6_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA6_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA6_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA6_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA6_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA6_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA6_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA6_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA6_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA6_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA6_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA6_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA6_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA6_RLC3_DOORBELL
>+#define SDMA6_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA6_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA6_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA6_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA6_RLC3_STATUS
>+#define SDMA6_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA6_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA6_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA6_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA6_RLC3_DOORBELL_LOG
>+#define SDMA6_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA6_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA6_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA6_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA6_RLC3_WATERMARK
>+#define SDMA6_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA6_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA6_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA6_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA6_RLC3_DOORBELL_OFFSET
>+#define SDMA6_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA6_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA6_RLC3_CSA_ADDR_LO
>+#define SDMA6_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA6_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA6_RLC3_CSA_ADDR_HI
>+#define SDMA6_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA6_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA6_RLC3_IB_SUB_REMAIN
>+#define SDMA6_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA6_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA6_RLC3_PREEMPT
>+#define SDMA6_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA6_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA6_RLC3_DUMMY_REG
>+#define SDMA6_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA6_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC3_RB_WPTR_POLL_ADDR_HI
>+#define SDMA6_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA6_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA6_RLC3_RB_WPTR_POLL_ADDR_LO
>+#define SDMA6_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA6_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA6_RLC3_RB_AQL_CNTL
>+#define SDMA6_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA6_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA6_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA6_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA6_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA6_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA6_RLC3_MINOR_PTR_UPDATE
>+#define SDMA6_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA6_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA6_RLC3_MIDCMD_DATA0
>+#define SDMA6_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA6_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC3_MIDCMD_DATA1
>+#define SDMA6_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA6_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC3_MIDCMD_DATA2
>+#define SDMA6_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA6_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC3_MIDCMD_DATA3
>+#define SDMA6_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA6_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC3_MIDCMD_DATA4
>+#define SDMA6_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA6_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC3_MIDCMD_DATA5
>+#define SDMA6_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA6_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC3_MIDCMD_DATA6
>+#define SDMA6_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA6_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC3_MIDCMD_DATA7
>+#define SDMA6_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA6_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC3_MIDCMD_DATA8
>+#define SDMA6_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA6_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC3_MIDCMD_CNTL
>+#define SDMA6_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA6_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA6_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA6_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA6_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA6_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA6_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA6_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA6_RLC4_RB_CNTL
>+#define SDMA6_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA6_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA6_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA6_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA6_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA6_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA6_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA6_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA6_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA6_RLC4_RB_BASE
>+#define SDMA6_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA6_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA6_RLC4_RB_BASE_HI
>+#define SDMA6_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA6_RLC4_RB_RPTR
>+#define SDMA6_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC4_RB_RPTR_HI
>+#define SDMA6_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC4_RB_WPTR
>+#define SDMA6_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC4_RB_WPTR_HI
>+#define SDMA6_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC4_RB_WPTR_POLL_CNTL
>+#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA6_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA6_RLC4_RB_RPTR_ADDR_HI
>+#define SDMA6_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA6_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA6_RLC4_RB_RPTR_ADDR_LO
>+#define SDMA6_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA6_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA6_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA6_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA6_RLC4_IB_CNTL
>+#define SDMA6_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA6_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA6_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA6_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA6_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA6_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA6_RLC4_IB_RPTR
>+#define SDMA6_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA6_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA6_RLC4_IB_OFFSET
>+#define SDMA6_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA6_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA6_RLC4_IB_BASE_LO
>+#define SDMA6_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA6_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA6_RLC4_IB_BASE_HI
>+#define SDMA6_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC4_IB_SIZE
>+#define SDMA6_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA6_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA6_RLC4_SKIP_CNTL
>+#define SDMA6_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA6_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA6_RLC4_CONTEXT_STATUS
>+#define SDMA6_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA6_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA6_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA6_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA6_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA6_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA6_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA6_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA6_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA6_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA6_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA6_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA6_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA6_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA6_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA6_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA6_RLC4_DOORBELL
>+#define SDMA6_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA6_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA6_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA6_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA6_RLC4_STATUS
>+#define SDMA6_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA6_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA6_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA6_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA6_RLC4_DOORBELL_LOG
>+#define SDMA6_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA6_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA6_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA6_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA6_RLC4_WATERMARK
>+#define SDMA6_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA6_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA6_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA6_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA6_RLC4_DOORBELL_OFFSET
>+#define SDMA6_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA6_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA6_RLC4_CSA_ADDR_LO
>+#define SDMA6_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA6_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA6_RLC4_CSA_ADDR_HI
>+#define SDMA6_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA6_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA6_RLC4_IB_SUB_REMAIN
>+#define SDMA6_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA6_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA6_RLC4_PREEMPT
>+#define SDMA6_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA6_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA6_RLC4_DUMMY_REG
>+#define SDMA6_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA6_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC4_RB_WPTR_POLL_ADDR_HI
>+#define SDMA6_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA6_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA6_RLC4_RB_WPTR_POLL_ADDR_LO
>+#define SDMA6_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA6_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA6_RLC4_RB_AQL_CNTL
>+#define SDMA6_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA6_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA6_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA6_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA6_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA6_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA6_RLC4_MINOR_PTR_UPDATE
>+#define SDMA6_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA6_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA6_RLC4_MIDCMD_DATA0
>+#define SDMA6_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA6_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC4_MIDCMD_DATA1
>+#define SDMA6_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA6_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC4_MIDCMD_DATA2
>+#define SDMA6_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA6_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC4_MIDCMD_DATA3
>+#define SDMA6_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA6_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC4_MIDCMD_DATA4
>+#define SDMA6_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA6_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC4_MIDCMD_DATA5
>+#define SDMA6_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA6_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC4_MIDCMD_DATA6
>+#define SDMA6_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA6_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC4_MIDCMD_DATA7
>+#define SDMA6_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA6_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC4_MIDCMD_DATA8
>+#define SDMA6_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA6_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC4_MIDCMD_CNTL
>+#define SDMA6_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA6_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA6_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA6_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA6_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA6_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA6_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA6_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA6_RLC5_RB_CNTL
>+#define SDMA6_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA6_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA6_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA6_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA6_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA6_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA6_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA6_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA6_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA6_RLC5_RB_BASE
>+#define SDMA6_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA6_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA6_RLC5_RB_BASE_HI
>+#define SDMA6_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA6_RLC5_RB_RPTR
>+#define SDMA6_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC5_RB_RPTR_HI
>+#define SDMA6_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC5_RB_WPTR
>+#define SDMA6_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC5_RB_WPTR_HI
>+#define SDMA6_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC5_RB_WPTR_POLL_CNTL
>+#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA6_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA6_RLC5_RB_RPTR_ADDR_HI
>+#define SDMA6_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA6_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA6_RLC5_RB_RPTR_ADDR_LO
>+#define SDMA6_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA6_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA6_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA6_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA6_RLC5_IB_CNTL
>+#define SDMA6_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA6_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA6_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA6_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA6_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA6_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA6_RLC5_IB_RPTR
>+#define SDMA6_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA6_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA6_RLC5_IB_OFFSET
>+#define SDMA6_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA6_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA6_RLC5_IB_BASE_LO
>+#define SDMA6_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA6_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA6_RLC5_IB_BASE_HI
>+#define SDMA6_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC5_IB_SIZE
>+#define SDMA6_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA6_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA6_RLC5_SKIP_CNTL
>+#define SDMA6_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA6_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA6_RLC5_CONTEXT_STATUS
>+#define SDMA6_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA6_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA6_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA6_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA6_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA6_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA6_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA6_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA6_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA6_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA6_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA6_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA6_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA6_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA6_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA6_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA6_RLC5_DOORBELL
>+#define SDMA6_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA6_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA6_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA6_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA6_RLC5_STATUS
>+#define SDMA6_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA6_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA6_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA6_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA6_RLC5_DOORBELL_LOG
>+#define SDMA6_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA6_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA6_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA6_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA6_RLC5_WATERMARK
>+#define SDMA6_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA6_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA6_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA6_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA6_RLC5_DOORBELL_OFFSET
>+#define SDMA6_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA6_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA6_RLC5_CSA_ADDR_LO
>+#define SDMA6_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA6_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA6_RLC5_CSA_ADDR_HI
>+#define SDMA6_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA6_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA6_RLC5_IB_SUB_REMAIN
>+#define SDMA6_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA6_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA6_RLC5_PREEMPT
>+#define SDMA6_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA6_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA6_RLC5_DUMMY_REG
>+#define SDMA6_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA6_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC5_RB_WPTR_POLL_ADDR_HI
>+#define SDMA6_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA6_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA6_RLC5_RB_WPTR_POLL_ADDR_LO
>+#define SDMA6_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA6_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA6_RLC5_RB_AQL_CNTL
>+#define SDMA6_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA6_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA6_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA6_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA6_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA6_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA6_RLC5_MINOR_PTR_UPDATE
>+#define SDMA6_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA6_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA6_RLC5_MIDCMD_DATA0
>+#define SDMA6_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA6_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC5_MIDCMD_DATA1
>+#define SDMA6_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA6_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC5_MIDCMD_DATA2
>+#define SDMA6_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA6_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC5_MIDCMD_DATA3
>+#define SDMA6_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA6_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC5_MIDCMD_DATA4
>+#define SDMA6_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA6_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC5_MIDCMD_DATA5
>+#define SDMA6_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA6_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC5_MIDCMD_DATA6
>+#define SDMA6_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA6_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC5_MIDCMD_DATA7
>+#define SDMA6_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA6_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC5_MIDCMD_DATA8
>+#define SDMA6_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA6_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC5_MIDCMD_CNTL
>+#define SDMA6_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA6_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA6_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA6_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA6_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA6_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA6_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA6_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA6_RLC6_RB_CNTL
>+#define SDMA6_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA6_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA6_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA6_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA6_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA6_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA6_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA6_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA6_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA6_RLC6_RB_BASE
>+#define SDMA6_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA6_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA6_RLC6_RB_BASE_HI
>+#define SDMA6_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA6_RLC6_RB_RPTR
>+#define SDMA6_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC6_RB_RPTR_HI
>+#define SDMA6_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC6_RB_WPTR
>+#define SDMA6_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC6_RB_WPTR_HI
>+#define SDMA6_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC6_RB_WPTR_POLL_CNTL
>+#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA6_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA6_RLC6_RB_RPTR_ADDR_HI
>+#define SDMA6_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA6_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA6_RLC6_RB_RPTR_ADDR_LO
>+#define SDMA6_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA6_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA6_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA6_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA6_RLC6_IB_CNTL
>+#define SDMA6_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA6_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA6_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA6_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA6_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA6_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA6_RLC6_IB_RPTR
>+#define SDMA6_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA6_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA6_RLC6_IB_OFFSET
>+#define SDMA6_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA6_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA6_RLC6_IB_BASE_LO
>+#define SDMA6_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA6_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA6_RLC6_IB_BASE_HI
>+#define SDMA6_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC6_IB_SIZE
>+#define SDMA6_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA6_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA6_RLC6_SKIP_CNTL
>+#define SDMA6_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA6_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA6_RLC6_CONTEXT_STATUS
>+#define SDMA6_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA6_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA6_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA6_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA6_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA6_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA6_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA6_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA6_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA6_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA6_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA6_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA6_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA6_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA6_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA6_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA6_RLC6_DOORBELL
>+#define SDMA6_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA6_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA6_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA6_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA6_RLC6_STATUS
>+#define SDMA6_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA6_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA6_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA6_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA6_RLC6_DOORBELL_LOG
>+#define SDMA6_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA6_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA6_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA6_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA6_RLC6_WATERMARK
>+#define SDMA6_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA6_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA6_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA6_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA6_RLC6_DOORBELL_OFFSET
>+#define SDMA6_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA6_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA6_RLC6_CSA_ADDR_LO
>+#define SDMA6_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA6_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA6_RLC6_CSA_ADDR_HI
>+#define SDMA6_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA6_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA6_RLC6_IB_SUB_REMAIN
>+#define SDMA6_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA6_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA6_RLC6_PREEMPT
>+#define SDMA6_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA6_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA6_RLC6_DUMMY_REG
>+#define SDMA6_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA6_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC6_RB_WPTR_POLL_ADDR_HI
>+#define SDMA6_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA6_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA6_RLC6_RB_WPTR_POLL_ADDR_LO
>+#define SDMA6_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA6_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA6_RLC6_RB_AQL_CNTL
>+#define SDMA6_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA6_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA6_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA6_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA6_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA6_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA6_RLC6_MINOR_PTR_UPDATE
>+#define SDMA6_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA6_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA6_RLC6_MIDCMD_DATA0
>+#define SDMA6_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA6_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC6_MIDCMD_DATA1
>+#define SDMA6_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA6_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC6_MIDCMD_DATA2
>+#define SDMA6_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA6_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC6_MIDCMD_DATA3
>+#define SDMA6_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA6_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC6_MIDCMD_DATA4
>+#define SDMA6_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA6_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC6_MIDCMD_DATA5
>+#define SDMA6_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA6_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC6_MIDCMD_DATA6
>+#define SDMA6_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA6_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC6_MIDCMD_DATA7
>+#define SDMA6_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA6_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC6_MIDCMD_DATA8
>+#define SDMA6_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA6_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC6_MIDCMD_CNTL
>+#define SDMA6_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA6_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA6_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA6_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA6_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA6_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA6_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA6_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA6_RLC7_RB_CNTL
>+#define SDMA6_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA6_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA6_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA6_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA6_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA6_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA6_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA6_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA6_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA6_RLC7_RB_BASE
>+#define SDMA6_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA6_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA6_RLC7_RB_BASE_HI
>+#define SDMA6_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA6_RLC7_RB_RPTR
>+#define SDMA6_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC7_RB_RPTR_HI
>+#define SDMA6_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC7_RB_WPTR
>+#define SDMA6_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA6_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA6_RLC7_RB_WPTR_HI
>+#define SDMA6_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA6_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA6_RLC7_RB_WPTR_POLL_CNTL
>+#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA6_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA6_RLC7_RB_RPTR_ADDR_HI
>+#define SDMA6_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA6_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA6_RLC7_RB_RPTR_ADDR_LO
>+#define SDMA6_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA6_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA6_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA6_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA6_RLC7_IB_CNTL
>+#define SDMA6_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA6_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA6_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA6_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA6_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA6_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA6_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA6_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA6_RLC7_IB_RPTR
>+#define SDMA6_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA6_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA6_RLC7_IB_OFFSET
>+#define SDMA6_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA6_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA6_RLC7_IB_BASE_LO
>+#define SDMA6_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA6_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA6_RLC7_IB_BASE_HI
>+#define SDMA6_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA6_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC7_IB_SIZE
>+#define SDMA6_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA6_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA6_RLC7_SKIP_CNTL
>+#define SDMA6_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA6_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA6_RLC7_CONTEXT_STATUS
>+#define SDMA6_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA6_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA6_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA6_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA6_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA6_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA6_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA6_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA6_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA6_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA6_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA6_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA6_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA6_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA6_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA6_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA6_RLC7_DOORBELL
>+#define SDMA6_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA6_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA6_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA6_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA6_RLC7_STATUS
>+#define SDMA6_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA6_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA6_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA6_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA6_RLC7_DOORBELL_LOG
>+#define SDMA6_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA6_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA6_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA6_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA6_RLC7_WATERMARK
>+#define SDMA6_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA6_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA6_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA6_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA6_RLC7_DOORBELL_OFFSET
>+#define SDMA6_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA6_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA6_RLC7_CSA_ADDR_LO
>+#define SDMA6_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA6_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA6_RLC7_CSA_ADDR_HI
>+#define SDMA6_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA6_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA6_RLC7_IB_SUB_REMAIN
>+#define SDMA6_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA6_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA6_RLC7_PREEMPT
>+#define SDMA6_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA6_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA6_RLC7_DUMMY_REG
>+#define SDMA6_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA6_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA6_RLC7_RB_WPTR_POLL_ADDR_HI
>+#define SDMA6_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA6_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA6_RLC7_RB_WPTR_POLL_ADDR_LO
>+#define SDMA6_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA6_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA6_RLC7_RB_AQL_CNTL
>+#define SDMA6_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA6_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA6_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA6_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA6_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA6_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA6_RLC7_MINOR_PTR_UPDATE
>+#define SDMA6_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA6_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA6_RLC7_MIDCMD_DATA0
>+#define SDMA6_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA6_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC7_MIDCMD_DATA1
>+#define SDMA6_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA6_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC7_MIDCMD_DATA2
>+#define SDMA6_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA6_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC7_MIDCMD_DATA3
>+#define SDMA6_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA6_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC7_MIDCMD_DATA4
>+#define SDMA6_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA6_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC7_MIDCMD_DATA5
>+#define SDMA6_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA6_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC7_MIDCMD_DATA6
>+#define SDMA6_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA6_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC7_MIDCMD_DATA7
>+#define SDMA6_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA6_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC7_MIDCMD_DATA8
>+#define SDMA6_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA6_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA6_RLC7_MIDCMD_CNTL
>+#define SDMA6_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA6_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA6_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA6_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA6_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA6_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA6_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA6_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_offset.h	2019-08-31 15:01:11.934736175 -0500
>@@ -0,0 +1,1043 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma7_4_2_2_OFFSET_HEADER
>+#define _sdma7_4_2_2_OFFSET_HEADER
>+
>+
>+
>+// addressBlock: sdma7_sdma7dec
>+// base address: 0x7d000
>+#define mmSDMA7_UCODE_ADDR                                                                             0x0000
>+#define mmSDMA7_UCODE_ADDR_BASE_IDX                                                                    1
>+#define mmSDMA7_UCODE_DATA                                                                             0x0001
>+#define mmSDMA7_UCODE_DATA_BASE_IDX                                                                    1
>+#define mmSDMA7_VM_CNTL                                                                                0x0004
>+#define mmSDMA7_VM_CNTL_BASE_IDX                                                                       1
>+#define mmSDMA7_VM_CTX_LO                                                                              0x0005
>+#define mmSDMA7_VM_CTX_LO_BASE_IDX                                                                     1
>+#define mmSDMA7_VM_CTX_HI                                                                              0x0006
>+#define mmSDMA7_VM_CTX_HI_BASE_IDX                                                                     1
>+#define mmSDMA7_ACTIVE_FCN_ID                                                                          0x0007
>+#define mmSDMA7_ACTIVE_FCN_ID_BASE_IDX                                                                 1
>+#define mmSDMA7_VM_CTX_CNTL                                                                            0x0008
>+#define mmSDMA7_VM_CTX_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA7_VIRT_RESET_REQ                                                                         0x0009
>+#define mmSDMA7_VIRT_RESET_REQ_BASE_IDX                                                                1
>+#define mmSDMA7_VF_ENABLE                                                                              0x000a
>+#define mmSDMA7_VF_ENABLE_BASE_IDX                                                                     1
>+#define mmSDMA7_CONTEXT_REG_TYPE0                                                                      0x000b
>+#define mmSDMA7_CONTEXT_REG_TYPE0_BASE_IDX                                                             1
>+#define mmSDMA7_CONTEXT_REG_TYPE1                                                                      0x000c
>+#define mmSDMA7_CONTEXT_REG_TYPE1_BASE_IDX                                                             1
>+#define mmSDMA7_CONTEXT_REG_TYPE2                                                                      0x000d
>+#define mmSDMA7_CONTEXT_REG_TYPE2_BASE_IDX                                                             1
>+#define mmSDMA7_CONTEXT_REG_TYPE3                                                                      0x000e
>+#define mmSDMA7_CONTEXT_REG_TYPE3_BASE_IDX                                                             1
>+#define mmSDMA7_PUB_REG_TYPE0                                                                          0x000f
>+#define mmSDMA7_PUB_REG_TYPE0_BASE_IDX                                                                 1
>+#define mmSDMA7_PUB_REG_TYPE1                                                                          0x0010
>+#define mmSDMA7_PUB_REG_TYPE1_BASE_IDX                                                                 1
>+#define mmSDMA7_PUB_REG_TYPE2                                                                          0x0011
>+#define mmSDMA7_PUB_REG_TYPE2_BASE_IDX                                                                 1
>+#define mmSDMA7_PUB_REG_TYPE3                                                                          0x0012
>+#define mmSDMA7_PUB_REG_TYPE3_BASE_IDX                                                                 1
>+#define mmSDMA7_MMHUB_CNTL                                                                             0x0013
>+#define mmSDMA7_MMHUB_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA7_CONTEXT_GROUP_BOUNDARY                                                                 0x0019
>+#define mmSDMA7_CONTEXT_GROUP_BOUNDARY_BASE_IDX                                                        1
>+#define mmSDMA7_POWER_CNTL                                                                             0x001a
>+#define mmSDMA7_POWER_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA7_CLK_CTRL                                                                               0x001b
>+#define mmSDMA7_CLK_CTRL_BASE_IDX                                                                      1
>+#define mmSDMA7_CNTL                                                                                   0x001c
>+#define mmSDMA7_CNTL_BASE_IDX                                                                          1
>+#define mmSDMA7_CHICKEN_BITS                                                                           0x001d
>+#define mmSDMA7_CHICKEN_BITS_BASE_IDX                                                                  1
>+#define mmSDMA7_GB_ADDR_CONFIG                                                                         0x001e
>+#define mmSDMA7_GB_ADDR_CONFIG_BASE_IDX                                                                1
>+#define mmSDMA7_GB_ADDR_CONFIG_READ                                                                    0x001f
>+#define mmSDMA7_GB_ADDR_CONFIG_READ_BASE_IDX                                                           1
>+#define mmSDMA7_RB_RPTR_FETCH_HI                                                                       0x0020
>+#define mmSDMA7_RB_RPTR_FETCH_HI_BASE_IDX                                                              1
>+#define mmSDMA7_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0021
>+#define mmSDMA7_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      1
>+#define mmSDMA7_RB_RPTR_FETCH                                                                          0x0022
>+#define mmSDMA7_RB_RPTR_FETCH_BASE_IDX                                                                 1
>+#define mmSDMA7_IB_OFFSET_FETCH                                                                        0x0023
>+#define mmSDMA7_IB_OFFSET_FETCH_BASE_IDX                                                               1
>+#define mmSDMA7_PROGRAM                                                                                0x0024
>+#define mmSDMA7_PROGRAM_BASE_IDX                                                                       1
>+#define mmSDMA7_STATUS_REG                                                                             0x0025
>+#define mmSDMA7_STATUS_REG_BASE_IDX                                                                    1
>+#define mmSDMA7_STATUS1_REG                                                                            0x0026
>+#define mmSDMA7_STATUS1_REG_BASE_IDX                                                                   1
>+#define mmSDMA7_RD_BURST_CNTL                                                                          0x0027
>+#define mmSDMA7_RD_BURST_CNTL_BASE_IDX                                                                 1
>+#define mmSDMA7_HBM_PAGE_CONFIG                                                                        0x0028
>+#define mmSDMA7_HBM_PAGE_CONFIG_BASE_IDX                                                               1
>+#define mmSDMA7_UCODE_CHECKSUM                                                                         0x0029
>+#define mmSDMA7_UCODE_CHECKSUM_BASE_IDX                                                                1
>+#define mmSDMA7_F32_CNTL                                                                               0x002a
>+#define mmSDMA7_F32_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA7_FREEZE                                                                                 0x002b
>+#define mmSDMA7_FREEZE_BASE_IDX                                                                        1
>+#define mmSDMA7_PHASE0_QUANTUM                                                                         0x002c
>+#define mmSDMA7_PHASE0_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA7_PHASE1_QUANTUM                                                                         0x002d
>+#define mmSDMA7_PHASE1_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA7_EDC_CONFIG                                                                             0x0032
>+#define mmSDMA7_EDC_CONFIG_BASE_IDX                                                                    1
>+#define mmSDMA7_BA_THRESHOLD                                                                           0x0033
>+#define mmSDMA7_BA_THRESHOLD_BASE_IDX                                                                  1
>+#define mmSDMA7_ID                                                                                     0x0034
>+#define mmSDMA7_ID_BASE_IDX                                                                            1
>+#define mmSDMA7_VERSION                                                                                0x0035
>+#define mmSDMA7_VERSION_BASE_IDX                                                                       1
>+#define mmSDMA7_EDC_COUNTER                                                                            0x0036
>+#define mmSDMA7_EDC_COUNTER_BASE_IDX                                                                   1
>+#define mmSDMA7_EDC_COUNTER_CLEAR                                                                      0x0037
>+#define mmSDMA7_EDC_COUNTER_CLEAR_BASE_IDX                                                             1
>+#define mmSDMA7_STATUS2_REG                                                                            0x0038
>+#define mmSDMA7_STATUS2_REG_BASE_IDX                                                                   1
>+#define mmSDMA7_ATOMIC_CNTL                                                                            0x0039
>+#define mmSDMA7_ATOMIC_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA7_ATOMIC_PREOP_LO                                                                        0x003a
>+#define mmSDMA7_ATOMIC_PREOP_LO_BASE_IDX                                                               1
>+#define mmSDMA7_ATOMIC_PREOP_HI                                                                        0x003b
>+#define mmSDMA7_ATOMIC_PREOP_HI_BASE_IDX                                                               1
>+#define mmSDMA7_UTCL1_CNTL                                                                             0x003c
>+#define mmSDMA7_UTCL1_CNTL_BASE_IDX                                                                    1
>+#define mmSDMA7_UTCL1_WATERMK                                                                          0x003d
>+#define mmSDMA7_UTCL1_WATERMK_BASE_IDX                                                                 1
>+#define mmSDMA7_UTCL1_RD_STATUS                                                                        0x003e
>+#define mmSDMA7_UTCL1_RD_STATUS_BASE_IDX                                                               1
>+#define mmSDMA7_UTCL1_WR_STATUS                                                                        0x003f
>+#define mmSDMA7_UTCL1_WR_STATUS_BASE_IDX                                                               1
>+#define mmSDMA7_UTCL1_INV0                                                                             0x0040
>+#define mmSDMA7_UTCL1_INV0_BASE_IDX                                                                    1
>+#define mmSDMA7_UTCL1_INV1                                                                             0x0041
>+#define mmSDMA7_UTCL1_INV1_BASE_IDX                                                                    1
>+#define mmSDMA7_UTCL1_INV2                                                                             0x0042
>+#define mmSDMA7_UTCL1_INV2_BASE_IDX                                                                    1
>+#define mmSDMA7_UTCL1_RD_XNACK0                                                                        0x0043
>+#define mmSDMA7_UTCL1_RD_XNACK0_BASE_IDX                                                               1
>+#define mmSDMA7_UTCL1_RD_XNACK1                                                                        0x0044
>+#define mmSDMA7_UTCL1_RD_XNACK1_BASE_IDX                                                               1
>+#define mmSDMA7_UTCL1_WR_XNACK0                                                                        0x0045
>+#define mmSDMA7_UTCL1_WR_XNACK0_BASE_IDX                                                               1
>+#define mmSDMA7_UTCL1_WR_XNACK1                                                                        0x0046
>+#define mmSDMA7_UTCL1_WR_XNACK1_BASE_IDX                                                               1
>+#define mmSDMA7_UTCL1_TIMEOUT                                                                          0x0047
>+#define mmSDMA7_UTCL1_TIMEOUT_BASE_IDX                                                                 1
>+#define mmSDMA7_UTCL1_PAGE                                                                             0x0048
>+#define mmSDMA7_UTCL1_PAGE_BASE_IDX                                                                    1
>+#define mmSDMA7_POWER_CNTL_IDLE                                                                        0x0049
>+#define mmSDMA7_POWER_CNTL_IDLE_BASE_IDX                                                               1
>+#define mmSDMA7_RELAX_ORDERING_LUT                                                                     0x004a
>+#define mmSDMA7_RELAX_ORDERING_LUT_BASE_IDX                                                            1
>+#define mmSDMA7_CHICKEN_BITS_2                                                                         0x004b
>+#define mmSDMA7_CHICKEN_BITS_2_BASE_IDX                                                                1
>+#define mmSDMA7_STATUS3_REG                                                                            0x004c
>+#define mmSDMA7_STATUS3_REG_BASE_IDX                                                                   1
>+#define mmSDMA7_PHYSICAL_ADDR_LO                                                                       0x004d
>+#define mmSDMA7_PHYSICAL_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA7_PHYSICAL_ADDR_HI                                                                       0x004e
>+#define mmSDMA7_PHYSICAL_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA7_PHASE2_QUANTUM                                                                         0x004f
>+#define mmSDMA7_PHASE2_QUANTUM_BASE_IDX                                                                1
>+#define mmSDMA7_ERROR_LOG                                                                              0x0050
>+#define mmSDMA7_ERROR_LOG_BASE_IDX                                                                     1
>+#define mmSDMA7_PUB_DUMMY_REG0                                                                         0x0051
>+#define mmSDMA7_PUB_DUMMY_REG0_BASE_IDX                                                                1
>+#define mmSDMA7_PUB_DUMMY_REG1                                                                         0x0052
>+#define mmSDMA7_PUB_DUMMY_REG1_BASE_IDX                                                                1
>+#define mmSDMA7_PUB_DUMMY_REG2                                                                         0x0053
>+#define mmSDMA7_PUB_DUMMY_REG2_BASE_IDX                                                                1
>+#define mmSDMA7_PUB_DUMMY_REG3                                                                         0x0054
>+#define mmSDMA7_PUB_DUMMY_REG3_BASE_IDX                                                                1
>+#define mmSDMA7_F32_COUNTER                                                                            0x0055
>+#define mmSDMA7_F32_COUNTER_BASE_IDX                                                                   1
>+#define mmSDMA7_UNBREAKABLE                                                                            0x0056
>+#define mmSDMA7_UNBREAKABLE_BASE_IDX                                                                   1
>+#define mmSDMA7_PERFMON_CNTL                                                                           0x0057
>+#define mmSDMA7_PERFMON_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_PERFCOUNTER0_RESULT                                                                    0x0058
>+#define mmSDMA7_PERFCOUNTER0_RESULT_BASE_IDX                                                           1
>+#define mmSDMA7_PERFCOUNTER1_RESULT                                                                    0x0059
>+#define mmSDMA7_PERFCOUNTER1_RESULT_BASE_IDX                                                           1
>+#define mmSDMA7_PERFCOUNTER_TAG_DELAY_RANGE                                                            0x005a
>+#define mmSDMA7_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX                                                   1
>+#define mmSDMA7_CRD_CNTL                                                                               0x005b
>+#define mmSDMA7_CRD_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA7_GPU_IOV_VIOLATION_LOG                                                                  0x005d
>+#define mmSDMA7_GPU_IOV_VIOLATION_LOG_BASE_IDX                                                         1
>+#define mmSDMA7_ULV_CNTL                                                                               0x005e
>+#define mmSDMA7_ULV_CNTL_BASE_IDX                                                                      1
>+#define mmSDMA7_EA_DBIT_ADDR_DATA                                                                      0x0060
>+#define mmSDMA7_EA_DBIT_ADDR_DATA_BASE_IDX                                                             1
>+#define mmSDMA7_EA_DBIT_ADDR_INDEX                                                                     0x0061
>+#define mmSDMA7_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            1
>+#define mmSDMA7_GPU_IOV_VIOLATION_LOG2                                                                 0x0062
>+#define mmSDMA7_GPU_IOV_VIOLATION_LOG2_BASE_IDX                                                        1
>+#define mmSDMA7_GFX_RB_CNTL                                                                            0x0080
>+#define mmSDMA7_GFX_RB_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA7_GFX_RB_BASE                                                                            0x0081
>+#define mmSDMA7_GFX_RB_BASE_BASE_IDX                                                                   1
>+#define mmSDMA7_GFX_RB_BASE_HI                                                                         0x0082
>+#define mmSDMA7_GFX_RB_BASE_HI_BASE_IDX                                                                1
>+#define mmSDMA7_GFX_RB_RPTR                                                                            0x0083
>+#define mmSDMA7_GFX_RB_RPTR_BASE_IDX                                                                   1
>+#define mmSDMA7_GFX_RB_RPTR_HI                                                                         0x0084
>+#define mmSDMA7_GFX_RB_RPTR_HI_BASE_IDX                                                                1
>+#define mmSDMA7_GFX_RB_WPTR                                                                            0x0085
>+#define mmSDMA7_GFX_RB_WPTR_BASE_IDX                                                                   1
>+#define mmSDMA7_GFX_RB_WPTR_HI                                                                         0x0086
>+#define mmSDMA7_GFX_RB_WPTR_HI_BASE_IDX                                                                1
>+#define mmSDMA7_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
>+#define mmSDMA7_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         1
>+#define mmSDMA7_GFX_RB_RPTR_ADDR_HI                                                                    0x0088
>+#define mmSDMA7_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           1
>+#define mmSDMA7_GFX_RB_RPTR_ADDR_LO                                                                    0x0089
>+#define mmSDMA7_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           1
>+#define mmSDMA7_GFX_IB_CNTL                                                                            0x008a
>+#define mmSDMA7_GFX_IB_CNTL_BASE_IDX                                                                   1
>+#define mmSDMA7_GFX_IB_RPTR                                                                            0x008b
>+#define mmSDMA7_GFX_IB_RPTR_BASE_IDX                                                                   1
>+#define mmSDMA7_GFX_IB_OFFSET                                                                          0x008c
>+#define mmSDMA7_GFX_IB_OFFSET_BASE_IDX                                                                 1
>+#define mmSDMA7_GFX_IB_BASE_LO                                                                         0x008d
>+#define mmSDMA7_GFX_IB_BASE_LO_BASE_IDX                                                                1
>+#define mmSDMA7_GFX_IB_BASE_HI                                                                         0x008e
>+#define mmSDMA7_GFX_IB_BASE_HI_BASE_IDX                                                                1
>+#define mmSDMA7_GFX_IB_SIZE                                                                            0x008f
>+#define mmSDMA7_GFX_IB_SIZE_BASE_IDX                                                                   1
>+#define mmSDMA7_GFX_SKIP_CNTL                                                                          0x0090
>+#define mmSDMA7_GFX_SKIP_CNTL_BASE_IDX                                                                 1
>+#define mmSDMA7_GFX_CONTEXT_STATUS                                                                     0x0091
>+#define mmSDMA7_GFX_CONTEXT_STATUS_BASE_IDX                                                            1
>+#define mmSDMA7_GFX_DOORBELL                                                                           0x0092
>+#define mmSDMA7_GFX_DOORBELL_BASE_IDX                                                                  1
>+#define mmSDMA7_GFX_CONTEXT_CNTL                                                                       0x0093
>+#define mmSDMA7_GFX_CONTEXT_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_GFX_STATUS                                                                             0x00a8
>+#define mmSDMA7_GFX_STATUS_BASE_IDX                                                                    1
>+#define mmSDMA7_GFX_DOORBELL_LOG                                                                       0x00a9
>+#define mmSDMA7_GFX_DOORBELL_LOG_BASE_IDX                                                              1
>+#define mmSDMA7_GFX_WATERMARK                                                                          0x00aa
>+#define mmSDMA7_GFX_WATERMARK_BASE_IDX                                                                 1
>+#define mmSDMA7_GFX_DOORBELL_OFFSET                                                                    0x00ab
>+#define mmSDMA7_GFX_DOORBELL_OFFSET_BASE_IDX                                                           1
>+#define mmSDMA7_GFX_CSA_ADDR_LO                                                                        0x00ac
>+#define mmSDMA7_GFX_CSA_ADDR_LO_BASE_IDX                                                               1
>+#define mmSDMA7_GFX_CSA_ADDR_HI                                                                        0x00ad
>+#define mmSDMA7_GFX_CSA_ADDR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_GFX_IB_SUB_REMAIN                                                                      0x00af
>+#define mmSDMA7_GFX_IB_SUB_REMAIN_BASE_IDX                                                             1
>+#define mmSDMA7_GFX_PREEMPT                                                                            0x00b0
>+#define mmSDMA7_GFX_PREEMPT_BASE_IDX                                                                   1
>+#define mmSDMA7_GFX_DUMMY_REG                                                                          0x00b1
>+#define mmSDMA7_GFX_DUMMY_REG_BASE_IDX                                                                 1
>+#define mmSDMA7_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x00b2
>+#define mmSDMA7_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      1
>+#define mmSDMA7_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x00b3
>+#define mmSDMA7_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      1
>+#define mmSDMA7_GFX_RB_AQL_CNTL                                                                        0x00b4
>+#define mmSDMA7_GFX_RB_AQL_CNTL_BASE_IDX                                                               1
>+#define mmSDMA7_GFX_MINOR_PTR_UPDATE                                                                   0x00b5
>+#define mmSDMA7_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          1
>+#define mmSDMA7_GFX_MIDCMD_DATA0                                                                       0x00c0
>+#define mmSDMA7_GFX_MIDCMD_DATA0_BASE_IDX                                                              1
>+#define mmSDMA7_GFX_MIDCMD_DATA1                                                                       0x00c1
>+#define mmSDMA7_GFX_MIDCMD_DATA1_BASE_IDX                                                              1
>+#define mmSDMA7_GFX_MIDCMD_DATA2                                                                       0x00c2
>+#define mmSDMA7_GFX_MIDCMD_DATA2_BASE_IDX                                                              1
>+#define mmSDMA7_GFX_MIDCMD_DATA3                                                                       0x00c3
>+#define mmSDMA7_GFX_MIDCMD_DATA3_BASE_IDX                                                              1
>+#define mmSDMA7_GFX_MIDCMD_DATA4                                                                       0x00c4
>+#define mmSDMA7_GFX_MIDCMD_DATA4_BASE_IDX                                                              1
>+#define mmSDMA7_GFX_MIDCMD_DATA5                                                                       0x00c5
>+#define mmSDMA7_GFX_MIDCMD_DATA5_BASE_IDX                                                              1
>+#define mmSDMA7_GFX_MIDCMD_DATA6                                                                       0x00c6
>+#define mmSDMA7_GFX_MIDCMD_DATA6_BASE_IDX                                                              1
>+#define mmSDMA7_GFX_MIDCMD_DATA7                                                                       0x00c7
>+#define mmSDMA7_GFX_MIDCMD_DATA7_BASE_IDX                                                              1
>+#define mmSDMA7_GFX_MIDCMD_DATA8                                                                       0x00c8
>+#define mmSDMA7_GFX_MIDCMD_DATA8_BASE_IDX                                                              1
>+#define mmSDMA7_GFX_MIDCMD_CNTL                                                                        0x00c9
>+#define mmSDMA7_GFX_MIDCMD_CNTL_BASE_IDX                                                               1
>+#define mmSDMA7_PAGE_RB_CNTL                                                                           0x00d8
>+#define mmSDMA7_PAGE_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_PAGE_RB_BASE                                                                           0x00d9
>+#define mmSDMA7_PAGE_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA7_PAGE_RB_BASE_HI                                                                        0x00da
>+#define mmSDMA7_PAGE_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_PAGE_RB_RPTR                                                                           0x00db
>+#define mmSDMA7_PAGE_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_PAGE_RB_RPTR_HI                                                                        0x00dc
>+#define mmSDMA7_PAGE_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_PAGE_RB_WPTR                                                                           0x00dd
>+#define mmSDMA7_PAGE_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_PAGE_RB_WPTR_HI                                                                        0x00de
>+#define mmSDMA7_PAGE_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_PAGE_RB_WPTR_POLL_CNTL                                                                 0x00df
>+#define mmSDMA7_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA7_PAGE_RB_RPTR_ADDR_HI                                                                   0x00e0
>+#define mmSDMA7_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA7_PAGE_RB_RPTR_ADDR_LO                                                                   0x00e1
>+#define mmSDMA7_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA7_PAGE_IB_CNTL                                                                           0x00e2
>+#define mmSDMA7_PAGE_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_PAGE_IB_RPTR                                                                           0x00e3
>+#define mmSDMA7_PAGE_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_PAGE_IB_OFFSET                                                                         0x00e4
>+#define mmSDMA7_PAGE_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA7_PAGE_IB_BASE_LO                                                                        0x00e5
>+#define mmSDMA7_PAGE_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA7_PAGE_IB_BASE_HI                                                                        0x00e6
>+#define mmSDMA7_PAGE_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_PAGE_IB_SIZE                                                                           0x00e7
>+#define mmSDMA7_PAGE_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA7_PAGE_SKIP_CNTL                                                                         0x00e8
>+#define mmSDMA7_PAGE_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA7_PAGE_CONTEXT_STATUS                                                                    0x00e9
>+#define mmSDMA7_PAGE_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA7_PAGE_DOORBELL                                                                          0x00ea
>+#define mmSDMA7_PAGE_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA7_PAGE_STATUS                                                                            0x0100
>+#define mmSDMA7_PAGE_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA7_PAGE_DOORBELL_LOG                                                                      0x0101
>+#define mmSDMA7_PAGE_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA7_PAGE_WATERMARK                                                                         0x0102
>+#define mmSDMA7_PAGE_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA7_PAGE_DOORBELL_OFFSET                                                                   0x0103
>+#define mmSDMA7_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA7_PAGE_CSA_ADDR_LO                                                                       0x0104
>+#define mmSDMA7_PAGE_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA7_PAGE_CSA_ADDR_HI                                                                       0x0105
>+#define mmSDMA7_PAGE_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA7_PAGE_IB_SUB_REMAIN                                                                     0x0107
>+#define mmSDMA7_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA7_PAGE_PREEMPT                                                                           0x0108
>+#define mmSDMA7_PAGE_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA7_PAGE_DUMMY_REG                                                                         0x0109
>+#define mmSDMA7_PAGE_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA7_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x010a
>+#define mmSDMA7_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA7_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x010b
>+#define mmSDMA7_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA7_PAGE_RB_AQL_CNTL                                                                       0x010c
>+#define mmSDMA7_PAGE_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_PAGE_MINOR_PTR_UPDATE                                                                  0x010d
>+#define mmSDMA7_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA7_PAGE_MIDCMD_DATA0                                                                      0x0118
>+#define mmSDMA7_PAGE_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA7_PAGE_MIDCMD_DATA1                                                                      0x0119
>+#define mmSDMA7_PAGE_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA7_PAGE_MIDCMD_DATA2                                                                      0x011a
>+#define mmSDMA7_PAGE_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA7_PAGE_MIDCMD_DATA3                                                                      0x011b
>+#define mmSDMA7_PAGE_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA7_PAGE_MIDCMD_DATA4                                                                      0x011c
>+#define mmSDMA7_PAGE_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA7_PAGE_MIDCMD_DATA5                                                                      0x011d
>+#define mmSDMA7_PAGE_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA7_PAGE_MIDCMD_DATA6                                                                      0x011e
>+#define mmSDMA7_PAGE_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA7_PAGE_MIDCMD_DATA7                                                                      0x011f
>+#define mmSDMA7_PAGE_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA7_PAGE_MIDCMD_DATA8                                                                      0x0120
>+#define mmSDMA7_PAGE_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA7_PAGE_MIDCMD_CNTL                                                                       0x0121
>+#define mmSDMA7_PAGE_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC0_RB_CNTL                                                                           0x0130
>+#define mmSDMA7_RLC0_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC0_RB_BASE                                                                           0x0131
>+#define mmSDMA7_RLC0_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC0_RB_BASE_HI                                                                        0x0132
>+#define mmSDMA7_RLC0_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC0_RB_RPTR                                                                           0x0133
>+#define mmSDMA7_RLC0_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC0_RB_RPTR_HI                                                                        0x0134
>+#define mmSDMA7_RLC0_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC0_RB_WPTR                                                                           0x0135
>+#define mmSDMA7_RLC0_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC0_RB_WPTR_HI                                                                        0x0136
>+#define mmSDMA7_RLC0_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0137
>+#define mmSDMA7_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA7_RLC0_RB_RPTR_ADDR_HI                                                                   0x0138
>+#define mmSDMA7_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA7_RLC0_RB_RPTR_ADDR_LO                                                                   0x0139
>+#define mmSDMA7_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA7_RLC0_IB_CNTL                                                                           0x013a
>+#define mmSDMA7_RLC0_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC0_IB_RPTR                                                                           0x013b
>+#define mmSDMA7_RLC0_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC0_IB_OFFSET                                                                         0x013c
>+#define mmSDMA7_RLC0_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA7_RLC0_IB_BASE_LO                                                                        0x013d
>+#define mmSDMA7_RLC0_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA7_RLC0_IB_BASE_HI                                                                        0x013e
>+#define mmSDMA7_RLC0_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC0_IB_SIZE                                                                           0x013f
>+#define mmSDMA7_RLC0_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC0_SKIP_CNTL                                                                         0x0140
>+#define mmSDMA7_RLC0_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA7_RLC0_CONTEXT_STATUS                                                                    0x0141
>+#define mmSDMA7_RLC0_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA7_RLC0_DOORBELL                                                                          0x0142
>+#define mmSDMA7_RLC0_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA7_RLC0_STATUS                                                                            0x0158
>+#define mmSDMA7_RLC0_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA7_RLC0_DOORBELL_LOG                                                                      0x0159
>+#define mmSDMA7_RLC0_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA7_RLC0_WATERMARK                                                                         0x015a
>+#define mmSDMA7_RLC0_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA7_RLC0_DOORBELL_OFFSET                                                                   0x015b
>+#define mmSDMA7_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA7_RLC0_CSA_ADDR_LO                                                                       0x015c
>+#define mmSDMA7_RLC0_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA7_RLC0_CSA_ADDR_HI                                                                       0x015d
>+#define mmSDMA7_RLC0_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA7_RLC0_IB_SUB_REMAIN                                                                     0x015f
>+#define mmSDMA7_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA7_RLC0_PREEMPT                                                                           0x0160
>+#define mmSDMA7_RLC0_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC0_DUMMY_REG                                                                         0x0161
>+#define mmSDMA7_RLC0_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA7_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0162
>+#define mmSDMA7_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA7_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0163
>+#define mmSDMA7_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA7_RLC0_RB_AQL_CNTL                                                                       0x0164
>+#define mmSDMA7_RLC0_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC0_MINOR_PTR_UPDATE                                                                  0x0165
>+#define mmSDMA7_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA7_RLC0_MIDCMD_DATA0                                                                      0x0170
>+#define mmSDMA7_RLC0_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA7_RLC0_MIDCMD_DATA1                                                                      0x0171
>+#define mmSDMA7_RLC0_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA7_RLC0_MIDCMD_DATA2                                                                      0x0172
>+#define mmSDMA7_RLC0_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA7_RLC0_MIDCMD_DATA3                                                                      0x0173
>+#define mmSDMA7_RLC0_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA7_RLC0_MIDCMD_DATA4                                                                      0x0174
>+#define mmSDMA7_RLC0_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA7_RLC0_MIDCMD_DATA5                                                                      0x0175
>+#define mmSDMA7_RLC0_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA7_RLC0_MIDCMD_DATA6                                                                      0x0176
>+#define mmSDMA7_RLC0_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA7_RLC0_MIDCMD_DATA7                                                                      0x0177
>+#define mmSDMA7_RLC0_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA7_RLC0_MIDCMD_DATA8                                                                      0x0178
>+#define mmSDMA7_RLC0_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA7_RLC0_MIDCMD_CNTL                                                                       0x0179
>+#define mmSDMA7_RLC0_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC1_RB_CNTL                                                                           0x0188
>+#define mmSDMA7_RLC1_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC1_RB_BASE                                                                           0x0189
>+#define mmSDMA7_RLC1_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC1_RB_BASE_HI                                                                        0x018a
>+#define mmSDMA7_RLC1_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC1_RB_RPTR                                                                           0x018b
>+#define mmSDMA7_RLC1_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC1_RB_RPTR_HI                                                                        0x018c
>+#define mmSDMA7_RLC1_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC1_RB_WPTR                                                                           0x018d
>+#define mmSDMA7_RLC1_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC1_RB_WPTR_HI                                                                        0x018e
>+#define mmSDMA7_RLC1_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC1_RB_WPTR_POLL_CNTL                                                                 0x018f
>+#define mmSDMA7_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA7_RLC1_RB_RPTR_ADDR_HI                                                                   0x0190
>+#define mmSDMA7_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA7_RLC1_RB_RPTR_ADDR_LO                                                                   0x0191
>+#define mmSDMA7_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA7_RLC1_IB_CNTL                                                                           0x0192
>+#define mmSDMA7_RLC1_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC1_IB_RPTR                                                                           0x0193
>+#define mmSDMA7_RLC1_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC1_IB_OFFSET                                                                         0x0194
>+#define mmSDMA7_RLC1_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA7_RLC1_IB_BASE_LO                                                                        0x0195
>+#define mmSDMA7_RLC1_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA7_RLC1_IB_BASE_HI                                                                        0x0196
>+#define mmSDMA7_RLC1_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC1_IB_SIZE                                                                           0x0197
>+#define mmSDMA7_RLC1_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC1_SKIP_CNTL                                                                         0x0198
>+#define mmSDMA7_RLC1_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA7_RLC1_CONTEXT_STATUS                                                                    0x0199
>+#define mmSDMA7_RLC1_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA7_RLC1_DOORBELL                                                                          0x019a
>+#define mmSDMA7_RLC1_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA7_RLC1_STATUS                                                                            0x01b0
>+#define mmSDMA7_RLC1_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA7_RLC1_DOORBELL_LOG                                                                      0x01b1
>+#define mmSDMA7_RLC1_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA7_RLC1_WATERMARK                                                                         0x01b2
>+#define mmSDMA7_RLC1_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA7_RLC1_DOORBELL_OFFSET                                                                   0x01b3
>+#define mmSDMA7_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA7_RLC1_CSA_ADDR_LO                                                                       0x01b4
>+#define mmSDMA7_RLC1_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA7_RLC1_CSA_ADDR_HI                                                                       0x01b5
>+#define mmSDMA7_RLC1_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA7_RLC1_IB_SUB_REMAIN                                                                     0x01b7
>+#define mmSDMA7_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA7_RLC1_PREEMPT                                                                           0x01b8
>+#define mmSDMA7_RLC1_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC1_DUMMY_REG                                                                         0x01b9
>+#define mmSDMA7_RLC1_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA7_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x01ba
>+#define mmSDMA7_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA7_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x01bb
>+#define mmSDMA7_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA7_RLC1_RB_AQL_CNTL                                                                       0x01bc
>+#define mmSDMA7_RLC1_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC1_MINOR_PTR_UPDATE                                                                  0x01bd
>+#define mmSDMA7_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA7_RLC1_MIDCMD_DATA0                                                                      0x01c8
>+#define mmSDMA7_RLC1_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA7_RLC1_MIDCMD_DATA1                                                                      0x01c9
>+#define mmSDMA7_RLC1_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA7_RLC1_MIDCMD_DATA2                                                                      0x01ca
>+#define mmSDMA7_RLC1_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA7_RLC1_MIDCMD_DATA3                                                                      0x01cb
>+#define mmSDMA7_RLC1_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA7_RLC1_MIDCMD_DATA4                                                                      0x01cc
>+#define mmSDMA7_RLC1_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA7_RLC1_MIDCMD_DATA5                                                                      0x01cd
>+#define mmSDMA7_RLC1_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA7_RLC1_MIDCMD_DATA6                                                                      0x01ce
>+#define mmSDMA7_RLC1_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA7_RLC1_MIDCMD_DATA7                                                                      0x01cf
>+#define mmSDMA7_RLC1_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA7_RLC1_MIDCMD_DATA8                                                                      0x01d0
>+#define mmSDMA7_RLC1_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA7_RLC1_MIDCMD_CNTL                                                                       0x01d1
>+#define mmSDMA7_RLC1_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC2_RB_CNTL                                                                           0x01e0
>+#define mmSDMA7_RLC2_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC2_RB_BASE                                                                           0x01e1
>+#define mmSDMA7_RLC2_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC2_RB_BASE_HI                                                                        0x01e2
>+#define mmSDMA7_RLC2_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC2_RB_RPTR                                                                           0x01e3
>+#define mmSDMA7_RLC2_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC2_RB_RPTR_HI                                                                        0x01e4
>+#define mmSDMA7_RLC2_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC2_RB_WPTR                                                                           0x01e5
>+#define mmSDMA7_RLC2_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC2_RB_WPTR_HI                                                                        0x01e6
>+#define mmSDMA7_RLC2_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC2_RB_WPTR_POLL_CNTL                                                                 0x01e7
>+#define mmSDMA7_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA7_RLC2_RB_RPTR_ADDR_HI                                                                   0x01e8
>+#define mmSDMA7_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA7_RLC2_RB_RPTR_ADDR_LO                                                                   0x01e9
>+#define mmSDMA7_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA7_RLC2_IB_CNTL                                                                           0x01ea
>+#define mmSDMA7_RLC2_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC2_IB_RPTR                                                                           0x01eb
>+#define mmSDMA7_RLC2_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC2_IB_OFFSET                                                                         0x01ec
>+#define mmSDMA7_RLC2_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA7_RLC2_IB_BASE_LO                                                                        0x01ed
>+#define mmSDMA7_RLC2_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA7_RLC2_IB_BASE_HI                                                                        0x01ee
>+#define mmSDMA7_RLC2_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC2_IB_SIZE                                                                           0x01ef
>+#define mmSDMA7_RLC2_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC2_SKIP_CNTL                                                                         0x01f0
>+#define mmSDMA7_RLC2_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA7_RLC2_CONTEXT_STATUS                                                                    0x01f1
>+#define mmSDMA7_RLC2_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA7_RLC2_DOORBELL                                                                          0x01f2
>+#define mmSDMA7_RLC2_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA7_RLC2_STATUS                                                                            0x0208
>+#define mmSDMA7_RLC2_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA7_RLC2_DOORBELL_LOG                                                                      0x0209
>+#define mmSDMA7_RLC2_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA7_RLC2_WATERMARK                                                                         0x020a
>+#define mmSDMA7_RLC2_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA7_RLC2_DOORBELL_OFFSET                                                                   0x020b
>+#define mmSDMA7_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA7_RLC2_CSA_ADDR_LO                                                                       0x020c
>+#define mmSDMA7_RLC2_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA7_RLC2_CSA_ADDR_HI                                                                       0x020d
>+#define mmSDMA7_RLC2_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA7_RLC2_IB_SUB_REMAIN                                                                     0x020f
>+#define mmSDMA7_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA7_RLC2_PREEMPT                                                                           0x0210
>+#define mmSDMA7_RLC2_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC2_DUMMY_REG                                                                         0x0211
>+#define mmSDMA7_RLC2_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA7_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0212
>+#define mmSDMA7_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA7_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0213
>+#define mmSDMA7_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA7_RLC2_RB_AQL_CNTL                                                                       0x0214
>+#define mmSDMA7_RLC2_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC2_MINOR_PTR_UPDATE                                                                  0x0215
>+#define mmSDMA7_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA7_RLC2_MIDCMD_DATA0                                                                      0x0220
>+#define mmSDMA7_RLC2_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA7_RLC2_MIDCMD_DATA1                                                                      0x0221
>+#define mmSDMA7_RLC2_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA7_RLC2_MIDCMD_DATA2                                                                      0x0222
>+#define mmSDMA7_RLC2_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA7_RLC2_MIDCMD_DATA3                                                                      0x0223
>+#define mmSDMA7_RLC2_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA7_RLC2_MIDCMD_DATA4                                                                      0x0224
>+#define mmSDMA7_RLC2_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA7_RLC2_MIDCMD_DATA5                                                                      0x0225
>+#define mmSDMA7_RLC2_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA7_RLC2_MIDCMD_DATA6                                                                      0x0226
>+#define mmSDMA7_RLC2_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA7_RLC2_MIDCMD_DATA7                                                                      0x0227
>+#define mmSDMA7_RLC2_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA7_RLC2_MIDCMD_DATA8                                                                      0x0228
>+#define mmSDMA7_RLC2_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA7_RLC2_MIDCMD_CNTL                                                                       0x0229
>+#define mmSDMA7_RLC2_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC3_RB_CNTL                                                                           0x0238
>+#define mmSDMA7_RLC3_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC3_RB_BASE                                                                           0x0239
>+#define mmSDMA7_RLC3_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC3_RB_BASE_HI                                                                        0x023a
>+#define mmSDMA7_RLC3_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC3_RB_RPTR                                                                           0x023b
>+#define mmSDMA7_RLC3_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC3_RB_RPTR_HI                                                                        0x023c
>+#define mmSDMA7_RLC3_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC3_RB_WPTR                                                                           0x023d
>+#define mmSDMA7_RLC3_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC3_RB_WPTR_HI                                                                        0x023e
>+#define mmSDMA7_RLC3_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC3_RB_WPTR_POLL_CNTL                                                                 0x023f
>+#define mmSDMA7_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA7_RLC3_RB_RPTR_ADDR_HI                                                                   0x0240
>+#define mmSDMA7_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA7_RLC3_RB_RPTR_ADDR_LO                                                                   0x0241
>+#define mmSDMA7_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA7_RLC3_IB_CNTL                                                                           0x0242
>+#define mmSDMA7_RLC3_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC3_IB_RPTR                                                                           0x0243
>+#define mmSDMA7_RLC3_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC3_IB_OFFSET                                                                         0x0244
>+#define mmSDMA7_RLC3_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA7_RLC3_IB_BASE_LO                                                                        0x0245
>+#define mmSDMA7_RLC3_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA7_RLC3_IB_BASE_HI                                                                        0x0246
>+#define mmSDMA7_RLC3_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC3_IB_SIZE                                                                           0x0247
>+#define mmSDMA7_RLC3_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC3_SKIP_CNTL                                                                         0x0248
>+#define mmSDMA7_RLC3_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA7_RLC3_CONTEXT_STATUS                                                                    0x0249
>+#define mmSDMA7_RLC3_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA7_RLC3_DOORBELL                                                                          0x024a
>+#define mmSDMA7_RLC3_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA7_RLC3_STATUS                                                                            0x0260
>+#define mmSDMA7_RLC3_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA7_RLC3_DOORBELL_LOG                                                                      0x0261
>+#define mmSDMA7_RLC3_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA7_RLC3_WATERMARK                                                                         0x0262
>+#define mmSDMA7_RLC3_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA7_RLC3_DOORBELL_OFFSET                                                                   0x0263
>+#define mmSDMA7_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA7_RLC3_CSA_ADDR_LO                                                                       0x0264
>+#define mmSDMA7_RLC3_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA7_RLC3_CSA_ADDR_HI                                                                       0x0265
>+#define mmSDMA7_RLC3_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA7_RLC3_IB_SUB_REMAIN                                                                     0x0267
>+#define mmSDMA7_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA7_RLC3_PREEMPT                                                                           0x0268
>+#define mmSDMA7_RLC3_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC3_DUMMY_REG                                                                         0x0269
>+#define mmSDMA7_RLC3_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA7_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x026a
>+#define mmSDMA7_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA7_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x026b
>+#define mmSDMA7_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA7_RLC3_RB_AQL_CNTL                                                                       0x026c
>+#define mmSDMA7_RLC3_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC3_MINOR_PTR_UPDATE                                                                  0x026d
>+#define mmSDMA7_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA7_RLC3_MIDCMD_DATA0                                                                      0x0278
>+#define mmSDMA7_RLC3_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA7_RLC3_MIDCMD_DATA1                                                                      0x0279
>+#define mmSDMA7_RLC3_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA7_RLC3_MIDCMD_DATA2                                                                      0x027a
>+#define mmSDMA7_RLC3_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA7_RLC3_MIDCMD_DATA3                                                                      0x027b
>+#define mmSDMA7_RLC3_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA7_RLC3_MIDCMD_DATA4                                                                      0x027c
>+#define mmSDMA7_RLC3_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA7_RLC3_MIDCMD_DATA5                                                                      0x027d
>+#define mmSDMA7_RLC3_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA7_RLC3_MIDCMD_DATA6                                                                      0x027e
>+#define mmSDMA7_RLC3_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA7_RLC3_MIDCMD_DATA7                                                                      0x027f
>+#define mmSDMA7_RLC3_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA7_RLC3_MIDCMD_DATA8                                                                      0x0280
>+#define mmSDMA7_RLC3_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA7_RLC3_MIDCMD_CNTL                                                                       0x0281
>+#define mmSDMA7_RLC3_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC4_RB_CNTL                                                                           0x0290
>+#define mmSDMA7_RLC4_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC4_RB_BASE                                                                           0x0291
>+#define mmSDMA7_RLC4_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC4_RB_BASE_HI                                                                        0x0292
>+#define mmSDMA7_RLC4_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC4_RB_RPTR                                                                           0x0293
>+#define mmSDMA7_RLC4_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC4_RB_RPTR_HI                                                                        0x0294
>+#define mmSDMA7_RLC4_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC4_RB_WPTR                                                                           0x0295
>+#define mmSDMA7_RLC4_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC4_RB_WPTR_HI                                                                        0x0296
>+#define mmSDMA7_RLC4_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC4_RB_WPTR_POLL_CNTL                                                                 0x0297
>+#define mmSDMA7_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA7_RLC4_RB_RPTR_ADDR_HI                                                                   0x0298
>+#define mmSDMA7_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA7_RLC4_RB_RPTR_ADDR_LO                                                                   0x0299
>+#define mmSDMA7_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA7_RLC4_IB_CNTL                                                                           0x029a
>+#define mmSDMA7_RLC4_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC4_IB_RPTR                                                                           0x029b
>+#define mmSDMA7_RLC4_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC4_IB_OFFSET                                                                         0x029c
>+#define mmSDMA7_RLC4_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA7_RLC4_IB_BASE_LO                                                                        0x029d
>+#define mmSDMA7_RLC4_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA7_RLC4_IB_BASE_HI                                                                        0x029e
>+#define mmSDMA7_RLC4_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC4_IB_SIZE                                                                           0x029f
>+#define mmSDMA7_RLC4_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC4_SKIP_CNTL                                                                         0x02a0
>+#define mmSDMA7_RLC4_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA7_RLC4_CONTEXT_STATUS                                                                    0x02a1
>+#define mmSDMA7_RLC4_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA7_RLC4_DOORBELL                                                                          0x02a2
>+#define mmSDMA7_RLC4_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA7_RLC4_STATUS                                                                            0x02b8
>+#define mmSDMA7_RLC4_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA7_RLC4_DOORBELL_LOG                                                                      0x02b9
>+#define mmSDMA7_RLC4_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA7_RLC4_WATERMARK                                                                         0x02ba
>+#define mmSDMA7_RLC4_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA7_RLC4_DOORBELL_OFFSET                                                                   0x02bb
>+#define mmSDMA7_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA7_RLC4_CSA_ADDR_LO                                                                       0x02bc
>+#define mmSDMA7_RLC4_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA7_RLC4_CSA_ADDR_HI                                                                       0x02bd
>+#define mmSDMA7_RLC4_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA7_RLC4_IB_SUB_REMAIN                                                                     0x02bf
>+#define mmSDMA7_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA7_RLC4_PREEMPT                                                                           0x02c0
>+#define mmSDMA7_RLC4_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC4_DUMMY_REG                                                                         0x02c1
>+#define mmSDMA7_RLC4_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA7_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x02c2
>+#define mmSDMA7_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA7_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x02c3
>+#define mmSDMA7_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA7_RLC4_RB_AQL_CNTL                                                                       0x02c4
>+#define mmSDMA7_RLC4_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC4_MINOR_PTR_UPDATE                                                                  0x02c5
>+#define mmSDMA7_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA7_RLC4_MIDCMD_DATA0                                                                      0x02d0
>+#define mmSDMA7_RLC4_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA7_RLC4_MIDCMD_DATA1                                                                      0x02d1
>+#define mmSDMA7_RLC4_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA7_RLC4_MIDCMD_DATA2                                                                      0x02d2
>+#define mmSDMA7_RLC4_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA7_RLC4_MIDCMD_DATA3                                                                      0x02d3
>+#define mmSDMA7_RLC4_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA7_RLC4_MIDCMD_DATA4                                                                      0x02d4
>+#define mmSDMA7_RLC4_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA7_RLC4_MIDCMD_DATA5                                                                      0x02d5
>+#define mmSDMA7_RLC4_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA7_RLC4_MIDCMD_DATA6                                                                      0x02d6
>+#define mmSDMA7_RLC4_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA7_RLC4_MIDCMD_DATA7                                                                      0x02d7
>+#define mmSDMA7_RLC4_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA7_RLC4_MIDCMD_DATA8                                                                      0x02d8
>+#define mmSDMA7_RLC4_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA7_RLC4_MIDCMD_CNTL                                                                       0x02d9
>+#define mmSDMA7_RLC4_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC5_RB_CNTL                                                                           0x02e8
>+#define mmSDMA7_RLC5_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC5_RB_BASE                                                                           0x02e9
>+#define mmSDMA7_RLC5_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC5_RB_BASE_HI                                                                        0x02ea
>+#define mmSDMA7_RLC5_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC5_RB_RPTR                                                                           0x02eb
>+#define mmSDMA7_RLC5_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC5_RB_RPTR_HI                                                                        0x02ec
>+#define mmSDMA7_RLC5_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC5_RB_WPTR                                                                           0x02ed
>+#define mmSDMA7_RLC5_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC5_RB_WPTR_HI                                                                        0x02ee
>+#define mmSDMA7_RLC5_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC5_RB_WPTR_POLL_CNTL                                                                 0x02ef
>+#define mmSDMA7_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA7_RLC5_RB_RPTR_ADDR_HI                                                                   0x02f0
>+#define mmSDMA7_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA7_RLC5_RB_RPTR_ADDR_LO                                                                   0x02f1
>+#define mmSDMA7_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA7_RLC5_IB_CNTL                                                                           0x02f2
>+#define mmSDMA7_RLC5_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC5_IB_RPTR                                                                           0x02f3
>+#define mmSDMA7_RLC5_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC5_IB_OFFSET                                                                         0x02f4
>+#define mmSDMA7_RLC5_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA7_RLC5_IB_BASE_LO                                                                        0x02f5
>+#define mmSDMA7_RLC5_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA7_RLC5_IB_BASE_HI                                                                        0x02f6
>+#define mmSDMA7_RLC5_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC5_IB_SIZE                                                                           0x02f7
>+#define mmSDMA7_RLC5_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC5_SKIP_CNTL                                                                         0x02f8
>+#define mmSDMA7_RLC5_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA7_RLC5_CONTEXT_STATUS                                                                    0x02f9
>+#define mmSDMA7_RLC5_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA7_RLC5_DOORBELL                                                                          0x02fa
>+#define mmSDMA7_RLC5_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA7_RLC5_STATUS                                                                            0x0310
>+#define mmSDMA7_RLC5_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA7_RLC5_DOORBELL_LOG                                                                      0x0311
>+#define mmSDMA7_RLC5_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA7_RLC5_WATERMARK                                                                         0x0312
>+#define mmSDMA7_RLC5_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA7_RLC5_DOORBELL_OFFSET                                                                   0x0313
>+#define mmSDMA7_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA7_RLC5_CSA_ADDR_LO                                                                       0x0314
>+#define mmSDMA7_RLC5_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA7_RLC5_CSA_ADDR_HI                                                                       0x0315
>+#define mmSDMA7_RLC5_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA7_RLC5_IB_SUB_REMAIN                                                                     0x0317
>+#define mmSDMA7_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA7_RLC5_PREEMPT                                                                           0x0318
>+#define mmSDMA7_RLC5_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC5_DUMMY_REG                                                                         0x0319
>+#define mmSDMA7_RLC5_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA7_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x031a
>+#define mmSDMA7_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA7_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x031b
>+#define mmSDMA7_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA7_RLC5_RB_AQL_CNTL                                                                       0x031c
>+#define mmSDMA7_RLC5_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC5_MINOR_PTR_UPDATE                                                                  0x031d
>+#define mmSDMA7_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA7_RLC5_MIDCMD_DATA0                                                                      0x0328
>+#define mmSDMA7_RLC5_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA7_RLC5_MIDCMD_DATA1                                                                      0x0329
>+#define mmSDMA7_RLC5_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA7_RLC5_MIDCMD_DATA2                                                                      0x032a
>+#define mmSDMA7_RLC5_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA7_RLC5_MIDCMD_DATA3                                                                      0x032b
>+#define mmSDMA7_RLC5_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA7_RLC5_MIDCMD_DATA4                                                                      0x032c
>+#define mmSDMA7_RLC5_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA7_RLC5_MIDCMD_DATA5                                                                      0x032d
>+#define mmSDMA7_RLC5_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA7_RLC5_MIDCMD_DATA6                                                                      0x032e
>+#define mmSDMA7_RLC5_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA7_RLC5_MIDCMD_DATA7                                                                      0x032f
>+#define mmSDMA7_RLC5_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA7_RLC5_MIDCMD_DATA8                                                                      0x0330
>+#define mmSDMA7_RLC5_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA7_RLC5_MIDCMD_CNTL                                                                       0x0331
>+#define mmSDMA7_RLC5_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC6_RB_CNTL                                                                           0x0340
>+#define mmSDMA7_RLC6_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC6_RB_BASE                                                                           0x0341
>+#define mmSDMA7_RLC6_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC6_RB_BASE_HI                                                                        0x0342
>+#define mmSDMA7_RLC6_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC6_RB_RPTR                                                                           0x0343
>+#define mmSDMA7_RLC6_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC6_RB_RPTR_HI                                                                        0x0344
>+#define mmSDMA7_RLC6_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC6_RB_WPTR                                                                           0x0345
>+#define mmSDMA7_RLC6_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC6_RB_WPTR_HI                                                                        0x0346
>+#define mmSDMA7_RLC6_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0347
>+#define mmSDMA7_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA7_RLC6_RB_RPTR_ADDR_HI                                                                   0x0348
>+#define mmSDMA7_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA7_RLC6_RB_RPTR_ADDR_LO                                                                   0x0349
>+#define mmSDMA7_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA7_RLC6_IB_CNTL                                                                           0x034a
>+#define mmSDMA7_RLC6_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC6_IB_RPTR                                                                           0x034b
>+#define mmSDMA7_RLC6_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC6_IB_OFFSET                                                                         0x034c
>+#define mmSDMA7_RLC6_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA7_RLC6_IB_BASE_LO                                                                        0x034d
>+#define mmSDMA7_RLC6_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA7_RLC6_IB_BASE_HI                                                                        0x034e
>+#define mmSDMA7_RLC6_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC6_IB_SIZE                                                                           0x034f
>+#define mmSDMA7_RLC6_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC6_SKIP_CNTL                                                                         0x0350
>+#define mmSDMA7_RLC6_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA7_RLC6_CONTEXT_STATUS                                                                    0x0351
>+#define mmSDMA7_RLC6_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA7_RLC6_DOORBELL                                                                          0x0352
>+#define mmSDMA7_RLC6_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA7_RLC6_STATUS                                                                            0x0368
>+#define mmSDMA7_RLC6_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA7_RLC6_DOORBELL_LOG                                                                      0x0369
>+#define mmSDMA7_RLC6_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA7_RLC6_WATERMARK                                                                         0x036a
>+#define mmSDMA7_RLC6_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA7_RLC6_DOORBELL_OFFSET                                                                   0x036b
>+#define mmSDMA7_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA7_RLC6_CSA_ADDR_LO                                                                       0x036c
>+#define mmSDMA7_RLC6_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA7_RLC6_CSA_ADDR_HI                                                                       0x036d
>+#define mmSDMA7_RLC6_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA7_RLC6_IB_SUB_REMAIN                                                                     0x036f
>+#define mmSDMA7_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA7_RLC6_PREEMPT                                                                           0x0370
>+#define mmSDMA7_RLC6_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC6_DUMMY_REG                                                                         0x0371
>+#define mmSDMA7_RLC6_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA7_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x0372
>+#define mmSDMA7_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA7_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x0373
>+#define mmSDMA7_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA7_RLC6_RB_AQL_CNTL                                                                       0x0374
>+#define mmSDMA7_RLC6_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC6_MINOR_PTR_UPDATE                                                                  0x0375
>+#define mmSDMA7_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA7_RLC6_MIDCMD_DATA0                                                                      0x0380
>+#define mmSDMA7_RLC6_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA7_RLC6_MIDCMD_DATA1                                                                      0x0381
>+#define mmSDMA7_RLC6_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA7_RLC6_MIDCMD_DATA2                                                                      0x0382
>+#define mmSDMA7_RLC6_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA7_RLC6_MIDCMD_DATA3                                                                      0x0383
>+#define mmSDMA7_RLC6_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA7_RLC6_MIDCMD_DATA4                                                                      0x0384
>+#define mmSDMA7_RLC6_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA7_RLC6_MIDCMD_DATA5                                                                      0x0385
>+#define mmSDMA7_RLC6_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA7_RLC6_MIDCMD_DATA6                                                                      0x0386
>+#define mmSDMA7_RLC6_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA7_RLC6_MIDCMD_DATA7                                                                      0x0387
>+#define mmSDMA7_RLC6_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA7_RLC6_MIDCMD_DATA8                                                                      0x0388
>+#define mmSDMA7_RLC6_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA7_RLC6_MIDCMD_CNTL                                                                       0x0389
>+#define mmSDMA7_RLC6_MIDCMD_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC7_RB_CNTL                                                                           0x0398
>+#define mmSDMA7_RLC7_RB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC7_RB_BASE                                                                           0x0399
>+#define mmSDMA7_RLC7_RB_BASE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC7_RB_BASE_HI                                                                        0x039a
>+#define mmSDMA7_RLC7_RB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC7_RB_RPTR                                                                           0x039b
>+#define mmSDMA7_RLC7_RB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC7_RB_RPTR_HI                                                                        0x039c
>+#define mmSDMA7_RLC7_RB_RPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC7_RB_WPTR                                                                           0x039d
>+#define mmSDMA7_RLC7_RB_WPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC7_RB_WPTR_HI                                                                        0x039e
>+#define mmSDMA7_RLC7_RB_WPTR_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC7_RB_WPTR_POLL_CNTL                                                                 0x039f
>+#define mmSDMA7_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        1
>+#define mmSDMA7_RLC7_RB_RPTR_ADDR_HI                                                                   0x03a0
>+#define mmSDMA7_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          1
>+#define mmSDMA7_RLC7_RB_RPTR_ADDR_LO                                                                   0x03a1
>+#define mmSDMA7_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          1
>+#define mmSDMA7_RLC7_IB_CNTL                                                                           0x03a2
>+#define mmSDMA7_RLC7_IB_CNTL_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC7_IB_RPTR                                                                           0x03a3
>+#define mmSDMA7_RLC7_IB_RPTR_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC7_IB_OFFSET                                                                         0x03a4
>+#define mmSDMA7_RLC7_IB_OFFSET_BASE_IDX                                                                1
>+#define mmSDMA7_RLC7_IB_BASE_LO                                                                        0x03a5
>+#define mmSDMA7_RLC7_IB_BASE_LO_BASE_IDX                                                               1
>+#define mmSDMA7_RLC7_IB_BASE_HI                                                                        0x03a6
>+#define mmSDMA7_RLC7_IB_BASE_HI_BASE_IDX                                                               1
>+#define mmSDMA7_RLC7_IB_SIZE                                                                           0x03a7
>+#define mmSDMA7_RLC7_IB_SIZE_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC7_SKIP_CNTL                                                                         0x03a8
>+#define mmSDMA7_RLC7_SKIP_CNTL_BASE_IDX                                                                1
>+#define mmSDMA7_RLC7_CONTEXT_STATUS                                                                    0x03a9
>+#define mmSDMA7_RLC7_CONTEXT_STATUS_BASE_IDX                                                           1
>+#define mmSDMA7_RLC7_DOORBELL                                                                          0x03aa
>+#define mmSDMA7_RLC7_DOORBELL_BASE_IDX                                                                 1
>+#define mmSDMA7_RLC7_STATUS                                                                            0x03c0
>+#define mmSDMA7_RLC7_STATUS_BASE_IDX                                                                   1
>+#define mmSDMA7_RLC7_DOORBELL_LOG                                                                      0x03c1
>+#define mmSDMA7_RLC7_DOORBELL_LOG_BASE_IDX                                                             1
>+#define mmSDMA7_RLC7_WATERMARK                                                                         0x03c2
>+#define mmSDMA7_RLC7_WATERMARK_BASE_IDX                                                                1
>+#define mmSDMA7_RLC7_DOORBELL_OFFSET                                                                   0x03c3
>+#define mmSDMA7_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          1
>+#define mmSDMA7_RLC7_CSA_ADDR_LO                                                                       0x03c4
>+#define mmSDMA7_RLC7_CSA_ADDR_LO_BASE_IDX                                                              1
>+#define mmSDMA7_RLC7_CSA_ADDR_HI                                                                       0x03c5
>+#define mmSDMA7_RLC7_CSA_ADDR_HI_BASE_IDX                                                              1
>+#define mmSDMA7_RLC7_IB_SUB_REMAIN                                                                     0x03c7
>+#define mmSDMA7_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            1
>+#define mmSDMA7_RLC7_PREEMPT                                                                           0x03c8
>+#define mmSDMA7_RLC7_PREEMPT_BASE_IDX                                                                  1
>+#define mmSDMA7_RLC7_DUMMY_REG                                                                         0x03c9
>+#define mmSDMA7_RLC7_DUMMY_REG_BASE_IDX                                                                1
>+#define mmSDMA7_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x03ca
>+#define mmSDMA7_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     1
>+#define mmSDMA7_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x03cb
>+#define mmSDMA7_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     1
>+#define mmSDMA7_RLC7_RB_AQL_CNTL                                                                       0x03cc
>+#define mmSDMA7_RLC7_RB_AQL_CNTL_BASE_IDX                                                              1
>+#define mmSDMA7_RLC7_MINOR_PTR_UPDATE                                                                  0x03cd
>+#define mmSDMA7_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         1
>+#define mmSDMA7_RLC7_MIDCMD_DATA0                                                                      0x03d8
>+#define mmSDMA7_RLC7_MIDCMD_DATA0_BASE_IDX                                                             1
>+#define mmSDMA7_RLC7_MIDCMD_DATA1                                                                      0x03d9
>+#define mmSDMA7_RLC7_MIDCMD_DATA1_BASE_IDX                                                             1
>+#define mmSDMA7_RLC7_MIDCMD_DATA2                                                                      0x03da
>+#define mmSDMA7_RLC7_MIDCMD_DATA2_BASE_IDX                                                             1
>+#define mmSDMA7_RLC7_MIDCMD_DATA3                                                                      0x03db
>+#define mmSDMA7_RLC7_MIDCMD_DATA3_BASE_IDX                                                             1
>+#define mmSDMA7_RLC7_MIDCMD_DATA4                                                                      0x03dc
>+#define mmSDMA7_RLC7_MIDCMD_DATA4_BASE_IDX                                                             1
>+#define mmSDMA7_RLC7_MIDCMD_DATA5                                                                      0x03dd
>+#define mmSDMA7_RLC7_MIDCMD_DATA5_BASE_IDX                                                             1
>+#define mmSDMA7_RLC7_MIDCMD_DATA6                                                                      0x03de
>+#define mmSDMA7_RLC7_MIDCMD_DATA6_BASE_IDX                                                             1
>+#define mmSDMA7_RLC7_MIDCMD_DATA7                                                                      0x03df
>+#define mmSDMA7_RLC7_MIDCMD_DATA7_BASE_IDX                                                             1
>+#define mmSDMA7_RLC7_MIDCMD_DATA8                                                                      0x03e0
>+#define mmSDMA7_RLC7_MIDCMD_DATA8_BASE_IDX                                                             1
>+#define mmSDMA7_RLC7_MIDCMD_CNTL                                                                       0x03e1
>+#define mmSDMA7_RLC7_MIDCMD_CNTL_BASE_IDX                                                              1
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/sdma7/sdma7_4_2_2_sh_mask.h	2019-08-31 15:01:11.934736175 -0500
>@@ -0,0 +1,2956 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _sdma7_4_2_2_SH_MASK_HEADER
>+#define _sdma7_4_2_2_SH_MASK_HEADER
>+
>+
>+// addressBlock: sdma7_sdma7dec
>+//SDMA7_UCODE_ADDR
>+#define SDMA7_UCODE_ADDR__VALUE__SHIFT                                                                        0x0
>+#define SDMA7_UCODE_ADDR__VALUE_MASK                                                                          0x00001FFFL
>+//SDMA7_UCODE_DATA
>+#define SDMA7_UCODE_DATA__VALUE__SHIFT                                                                        0x0
>+#define SDMA7_UCODE_DATA__VALUE_MASK                                                                          0xFFFFFFFFL
>+//SDMA7_VM_CNTL
>+#define SDMA7_VM_CNTL__CMD__SHIFT                                                                             0x0
>+#define SDMA7_VM_CNTL__CMD_MASK                                                                               0x0000000FL
>+//SDMA7_VM_CTX_LO
>+#define SDMA7_VM_CTX_LO__ADDR__SHIFT                                                                          0x2
>+#define SDMA7_VM_CTX_LO__ADDR_MASK                                                                            0xFFFFFFFCL
>+//SDMA7_VM_CTX_HI
>+#define SDMA7_VM_CTX_HI__ADDR__SHIFT                                                                          0x0
>+#define SDMA7_VM_CTX_HI__ADDR_MASK                                                                            0xFFFFFFFFL
>+//SDMA7_ACTIVE_FCN_ID
>+#define SDMA7_ACTIVE_FCN_ID__VFID__SHIFT                                                                      0x0
>+#define SDMA7_ACTIVE_FCN_ID__RESERVED__SHIFT                                                                  0x4
>+#define SDMA7_ACTIVE_FCN_ID__VF__SHIFT                                                                        0x1f
>+#define SDMA7_ACTIVE_FCN_ID__VFID_MASK                                                                        0x0000000FL
>+#define SDMA7_ACTIVE_FCN_ID__RESERVED_MASK                                                                    0x7FFFFFF0L
>+#define SDMA7_ACTIVE_FCN_ID__VF_MASK                                                                          0x80000000L
>+//SDMA7_VM_CTX_CNTL
>+#define SDMA7_VM_CTX_CNTL__PRIV__SHIFT                                                                        0x0
>+#define SDMA7_VM_CTX_CNTL__VMID__SHIFT                                                                        0x4
>+#define SDMA7_VM_CTX_CNTL__PRIV_MASK                                                                          0x00000001L
>+#define SDMA7_VM_CTX_CNTL__VMID_MASK                                                                          0x000000F0L
>+//SDMA7_VIRT_RESET_REQ
>+#define SDMA7_VIRT_RESET_REQ__VF__SHIFT                                                                       0x0
>+#define SDMA7_VIRT_RESET_REQ__PF__SHIFT                                                                       0x1f
>+#define SDMA7_VIRT_RESET_REQ__VF_MASK                                                                         0x0000FFFFL
>+#define SDMA7_VIRT_RESET_REQ__PF_MASK                                                                         0x80000000L
>+//SDMA7_VF_ENABLE
>+#define SDMA7_VF_ENABLE__VF_ENABLE__SHIFT                                                                     0x0
>+#define SDMA7_VF_ENABLE__VF_ENABLE_MASK                                                                       0x00000001L
>+//SDMA7_CONTEXT_REG_TYPE0
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_CNTL__SHIFT                                                     0x0
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE__SHIFT                                                     0x1
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE_HI__SHIFT                                                  0x2
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR__SHIFT                                                     0x3
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_HI__SHIFT                                                  0x4
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR__SHIFT                                                     0x5
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_HI__SHIFT                                                  0x6
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_POLL_CNTL__SHIFT                                           0x7
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_HI__SHIFT                                             0x8
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_LO__SHIFT                                             0x9
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_CNTL__SHIFT                                                     0xa
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_RPTR__SHIFT                                                     0xb
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_OFFSET__SHIFT                                                   0xc
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_LO__SHIFT                                                  0xd
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_HI__SHIFT                                                  0xe
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_SIZE__SHIFT                                                     0xf
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_SKIP_CNTL__SHIFT                                                   0x10
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_STATUS__SHIFT                                              0x11
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_DOORBELL__SHIFT                                                    0x12
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_CNTL__SHIFT                                                0x13
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_CNTL_MASK                                                       0x00000001L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE_MASK                                                       0x00000002L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_BASE_HI_MASK                                                    0x00000004L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_MASK                                                       0x00000008L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_HI_MASK                                                    0x00000010L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_MASK                                                       0x00000020L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_HI_MASK                                                    0x00000040L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_WPTR_POLL_CNTL_MASK                                             0x00000080L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_HI_MASK                                               0x00000100L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_RB_RPTR_ADDR_LO_MASK                                               0x00000200L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_CNTL_MASK                                                       0x00000400L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_RPTR_MASK                                                       0x00000800L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_OFFSET_MASK                                                     0x00001000L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_LO_MASK                                                    0x00002000L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_BASE_HI_MASK                                                    0x00004000L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_IB_SIZE_MASK                                                       0x00008000L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_SKIP_CNTL_MASK                                                     0x00010000L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_STATUS_MASK                                                0x00020000L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_DOORBELL_MASK                                                      0x00040000L
>+#define SDMA7_CONTEXT_REG_TYPE0__SDMA7_GFX_CONTEXT_CNTL_MASK                                                  0x00080000L
>+//SDMA7_CONTEXT_REG_TYPE1
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_STATUS__SHIFT                                                      0x8
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_LOG__SHIFT                                                0x9
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_WATERMARK__SHIFT                                                   0xa
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_OFFSET__SHIFT                                             0xb
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_LO__SHIFT                                                 0xc
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_HI__SHIFT                                                 0xd
>+#define SDMA7_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT                                                             0xe
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_IB_SUB_REMAIN__SHIFT                                               0xf
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_PREEMPT__SHIFT                                                     0x10
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DUMMY_REG__SHIFT                                                   0x11
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT                                        0x12
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT                                        0x13
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_AQL_CNTL__SHIFT                                                 0x14
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_MINOR_PTR_UPDATE__SHIFT                                            0x15
>+#define SDMA7_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x16
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_STATUS_MASK                                                        0x00000100L
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_LOG_MASK                                                  0x00000200L
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_WATERMARK_MASK                                                     0x00000400L
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DOORBELL_OFFSET_MASK                                               0x00000800L
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_LO_MASK                                                   0x00001000L
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_CSA_ADDR_HI_MASK                                                   0x00002000L
>+#define SDMA7_CONTEXT_REG_TYPE1__VOID_REG2_MASK                                                               0x00004000L
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_IB_SUB_REMAIN_MASK                                                 0x00008000L
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_PREEMPT_MASK                                                       0x00010000L
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_DUMMY_REG_MASK                                                     0x00020000L
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_HI_MASK                                          0x00040000L
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_WPTR_POLL_ADDR_LO_MASK                                          0x00080000L
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_RB_AQL_CNTL_MASK                                                   0x00100000L
>+#define SDMA7_CONTEXT_REG_TYPE1__SDMA7_GFX_MINOR_PTR_UPDATE_MASK                                              0x00200000L
>+#define SDMA7_CONTEXT_REG_TYPE1__RESERVED_MASK                                                                0xFFC00000L
>+//SDMA7_CONTEXT_REG_TYPE2
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA0__SHIFT                                                0x0
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA1__SHIFT                                                0x1
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA2__SHIFT                                                0x2
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA3__SHIFT                                                0x3
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA4__SHIFT                                                0x4
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA5__SHIFT                                                0x5
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA6__SHIFT                                                0x6
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA7__SHIFT                                                0x7
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA8__SHIFT                                                0x8
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_CNTL__SHIFT                                                 0x9
>+#define SDMA7_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA0_MASK                                                  0x00000001L
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA1_MASK                                                  0x00000002L
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA2_MASK                                                  0x00000004L
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA3_MASK                                                  0x00000008L
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA4_MASK                                                  0x00000010L
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA5_MASK                                                  0x00000020L
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA6_MASK                                                  0x00000040L
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA7_MASK                                                  0x00000080L
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_DATA8_MASK                                                  0x00000100L
>+#define SDMA7_CONTEXT_REG_TYPE2__SDMA7_GFX_MIDCMD_CNTL_MASK                                                   0x00000200L
>+#define SDMA7_CONTEXT_REG_TYPE2__RESERVED_MASK                                                                0xFFFFFC00L
>+//SDMA7_CONTEXT_REG_TYPE3
>+#define SDMA7_CONTEXT_REG_TYPE3__RESERVED__SHIFT                                                              0x0
>+#define SDMA7_CONTEXT_REG_TYPE3__RESERVED_MASK                                                                0xFFFFFFFFL
>+//SDMA7_PUB_REG_TYPE0
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_ADDR__SHIFT                                                          0x0
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_DATA__SHIFT                                                          0x1
>+#define SDMA7_PUB_REG_TYPE0__RESERVED3__SHIFT                                                                 0x3
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CNTL__SHIFT                                                             0x4
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_LO__SHIFT                                                           0x5
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_HI__SHIFT                                                           0x6
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_ACTIVE_FCN_ID__SHIFT                                                       0x7
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_CNTL__SHIFT                                                         0x8
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_VIRT_RESET_REQ__SHIFT                                                      0x9
>+#define SDMA7_PUB_REG_TYPE0__RESERVED10__SHIFT                                                                0xa
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE0__SHIFT                                                   0xb
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE1__SHIFT                                                   0xc
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE2__SHIFT                                                   0xd
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE3__SHIFT                                                   0xe
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE0__SHIFT                                                       0xf
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE1__SHIFT                                                       0x10
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE2__SHIFT                                                       0x11
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE3__SHIFT                                                       0x12
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_MMHUB_CNTL__SHIFT                                                          0x13
>+#define SDMA7_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT                                           0x15
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_GROUP_BOUNDARY__SHIFT                                              0x19
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_POWER_CNTL__SHIFT                                                          0x1a
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CLK_CTRL__SHIFT                                                            0x1b
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CNTL__SHIFT                                                                0x1c
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CHICKEN_BITS__SHIFT                                                        0x1d
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG__SHIFT                                                      0x1e
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG_READ__SHIFT                                                 0x1f
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_ADDR_MASK                                                            0x00000001L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_UCODE_DATA_MASK                                                            0x00000002L
>+#define SDMA7_PUB_REG_TYPE0__RESERVED3_MASK                                                                   0x00000008L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CNTL_MASK                                                               0x00000010L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_LO_MASK                                                             0x00000020L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_HI_MASK                                                             0x00000040L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_ACTIVE_FCN_ID_MASK                                                         0x00000080L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_VM_CTX_CNTL_MASK                                                           0x00000100L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_VIRT_RESET_REQ_MASK                                                        0x00000200L
>+#define SDMA7_PUB_REG_TYPE0__RESERVED10_MASK                                                                  0x00000400L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE0_MASK                                                     0x00000800L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE1_MASK                                                     0x00001000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE2_MASK                                                     0x00002000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_REG_TYPE3_MASK                                                     0x00004000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE0_MASK                                                         0x00008000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE1_MASK                                                         0x00010000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE2_MASK                                                         0x00020000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_PUB_REG_TYPE3_MASK                                                         0x00040000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_MMHUB_CNTL_MASK                                                            0x00080000L
>+#define SDMA7_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK                                             0x01E00000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CONTEXT_GROUP_BOUNDARY_MASK                                                0x02000000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_POWER_CNTL_MASK                                                            0x04000000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CLK_CTRL_MASK                                                              0x08000000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CNTL_MASK                                                                  0x10000000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_CHICKEN_BITS_MASK                                                          0x20000000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG_MASK                                                        0x40000000L
>+#define SDMA7_PUB_REG_TYPE0__SDMA7_GB_ADDR_CONFIG_READ_MASK                                                   0x80000000L
>+//SDMA7_PUB_REG_TYPE1
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH_HI__SHIFT                                                    0x0
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT                                            0x1
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH__SHIFT                                                       0x2
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_IB_OFFSET_FETCH__SHIFT                                                     0x3
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_PROGRAM__SHIFT                                                             0x4
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS_REG__SHIFT                                                          0x5
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS1_REG__SHIFT                                                         0x6
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_RD_BURST_CNTL__SHIFT                                                       0x7
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_HBM_PAGE_CONFIG__SHIFT                                                     0x8
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_UCODE_CHECKSUM__SHIFT                                                      0x9
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_F32_CNTL__SHIFT                                                            0xa
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_FREEZE__SHIFT                                                              0xb
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE0_QUANTUM__SHIFT                                                      0xc
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE1_QUANTUM__SHIFT                                                      0xd
>+#define SDMA7_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT                                                         0xe
>+#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT                                                         0xf
>+#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT                                                          0x10
>+#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT                                                           0x11
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_CONFIG__SHIFT                                                          0x12
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_BA_THRESHOLD__SHIFT                                                        0x13
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_ID__SHIFT                                                                  0x14
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_VERSION__SHIFT                                                             0x15
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER__SHIFT                                                         0x16
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER_CLEAR__SHIFT                                                   0x17
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS2_REG__SHIFT                                                         0x18
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_CNTL__SHIFT                                                         0x19
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_LO__SHIFT                                                     0x1a
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_HI__SHIFT                                                     0x1b
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_CNTL__SHIFT                                                          0x1c
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WATERMK__SHIFT                                                       0x1d
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_RD_STATUS__SHIFT                                                     0x1e
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WR_STATUS__SHIFT                                                     0x1f
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH_HI_MASK                                                      0x00000001L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_SEM_WAIT_FAIL_TIMER_CNTL_MASK                                              0x00000002L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_RB_RPTR_FETCH_MASK                                                         0x00000004L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_IB_OFFSET_FETCH_MASK                                                       0x00000008L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_PROGRAM_MASK                                                               0x00000010L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS_REG_MASK                                                            0x00000020L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS1_REG_MASK                                                           0x00000040L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_RD_BURST_CNTL_MASK                                                         0x00000080L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_HBM_PAGE_CONFIG_MASK                                                       0x00000100L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_UCODE_CHECKSUM_MASK                                                        0x00000200L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_F32_CNTL_MASK                                                              0x00000400L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_FREEZE_MASK                                                                0x00000800L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE0_QUANTUM_MASK                                                        0x00001000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_PHASE1_QUANTUM_MASK                                                        0x00002000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK                                                           0x00004000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK                                                           0x00008000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK                                                            0x00010000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK                                                             0x00020000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_CONFIG_MASK                                                            0x00040000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_BA_THRESHOLD_MASK                                                          0x00080000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_ID_MASK                                                                    0x00100000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_VERSION_MASK                                                               0x00200000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER_MASK                                                           0x00400000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_EDC_COUNTER_CLEAR_MASK                                                     0x00800000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_STATUS2_REG_MASK                                                           0x01000000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_CNTL_MASK                                                           0x02000000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_LO_MASK                                                       0x04000000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_ATOMIC_PREOP_HI_MASK                                                       0x08000000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_CNTL_MASK                                                            0x10000000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WATERMK_MASK                                                         0x20000000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_RD_STATUS_MASK                                                       0x40000000L
>+#define SDMA7_PUB_REG_TYPE1__SDMA7_UTCL1_WR_STATUS_MASK                                                       0x80000000L
>+//SDMA7_PUB_REG_TYPE2
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV0__SHIFT                                                          0x0
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV1__SHIFT                                                          0x1
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV2__SHIFT                                                          0x2
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK0__SHIFT                                                     0x3
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK1__SHIFT                                                     0x4
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK0__SHIFT                                                     0x5
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK1__SHIFT                                                     0x6
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_TIMEOUT__SHIFT                                                       0x7
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_PAGE__SHIFT                                                          0x8
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_POWER_CNTL_IDLE__SHIFT                                                     0x9
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_RELAX_ORDERING_LUT__SHIFT                                                  0xa
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_CHICKEN_BITS_2__SHIFT                                                      0xb
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_STATUS3_REG__SHIFT                                                         0xc
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_LO__SHIFT                                                    0xd
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_HI__SHIFT                                                    0xe
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PHASE2_QUANTUM__SHIFT                                                      0xf
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_ERROR_LOG__SHIFT                                                           0x10
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG0__SHIFT                                                      0x11
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG1__SHIFT                                                      0x12
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG2__SHIFT                                                      0x13
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG3__SHIFT                                                      0x14
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_F32_COUNTER__SHIFT                                                         0x15
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UNBREAKABLE__SHIFT                                                         0x16
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFMON_CNTL__SHIFT                                                        0x17
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER0_RESULT__SHIFT                                                 0x18
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER1_RESULT__SHIFT                                                 0x19
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT                                         0x1a
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_CRD_CNTL__SHIFT                                                            0x1b
>+#define SDMA7_PUB_REG_TYPE2__RESERVED28__SHIFT                                                                0x1c
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_GPU_IOV_VIOLATION_LOG__SHIFT                                               0x1d
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_ULV_CNTL__SHIFT                                                            0x1e
>+#define SDMA7_PUB_REG_TYPE2__RESERVED__SHIFT                                                                  0x1f
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV0_MASK                                                            0x00000001L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV1_MASK                                                            0x00000002L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_INV2_MASK                                                            0x00000004L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK0_MASK                                                       0x00000008L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_RD_XNACK1_MASK                                                       0x00000010L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK0_MASK                                                       0x00000020L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_WR_XNACK1_MASK                                                       0x00000040L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_TIMEOUT_MASK                                                         0x00000080L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UTCL1_PAGE_MASK                                                            0x00000100L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_POWER_CNTL_IDLE_MASK                                                       0x00000200L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_RELAX_ORDERING_LUT_MASK                                                    0x00000400L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_CHICKEN_BITS_2_MASK                                                        0x00000800L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_STATUS3_REG_MASK                                                           0x00001000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_LO_MASK                                                      0x00002000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PHYSICAL_ADDR_HI_MASK                                                      0x00004000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PHASE2_QUANTUM_MASK                                                        0x00008000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_ERROR_LOG_MASK                                                             0x00010000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG0_MASK                                                        0x00020000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG1_MASK                                                        0x00040000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG2_MASK                                                        0x00080000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PUB_DUMMY_REG3_MASK                                                        0x00100000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_F32_COUNTER_MASK                                                           0x00200000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_UNBREAKABLE_MASK                                                           0x00400000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFMON_CNTL_MASK                                                          0x00800000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER0_RESULT_MASK                                                   0x01000000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER1_RESULT_MASK                                                   0x02000000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_PERFCOUNTER_TAG_DELAY_RANGE_MASK                                           0x04000000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_CRD_CNTL_MASK                                                              0x08000000L
>+#define SDMA7_PUB_REG_TYPE2__RESERVED28_MASK                                                                  0x10000000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_GPU_IOV_VIOLATION_LOG_MASK                                                 0x20000000L
>+#define SDMA7_PUB_REG_TYPE2__SDMA7_ULV_CNTL_MASK                                                              0x40000000L
>+#define SDMA7_PUB_REG_TYPE2__RESERVED_MASK                                                                    0x80000000L
>+//SDMA7_PUB_REG_TYPE3
>+#define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_DATA__SHIFT                                                   0x0
>+#define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_INDEX__SHIFT                                                  0x1
>+#define SDMA7_PUB_REG_TYPE3__SDMA7_GPU_IOV_VIOLATION_LOG2__SHIFT                                              0x2
>+#define SDMA7_PUB_REG_TYPE3__RESERVED__SHIFT                                                                  0x3
>+#define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_DATA_MASK                                                     0x00000001L
>+#define SDMA7_PUB_REG_TYPE3__SDMA7_EA_DBIT_ADDR_INDEX_MASK                                                    0x00000002L
>+#define SDMA7_PUB_REG_TYPE3__SDMA7_GPU_IOV_VIOLATION_LOG2_MASK                                                0x00000004L
>+#define SDMA7_PUB_REG_TYPE3__RESERVED_MASK                                                                    0xFFFFFFF8L
>+//SDMA7_MMHUB_CNTL
>+#define SDMA7_MMHUB_CNTL__UNIT_ID__SHIFT                                                                      0x0
>+#define SDMA7_MMHUB_CNTL__UNIT_ID_MASK                                                                        0x0000003FL
>+//SDMA7_CONTEXT_GROUP_BOUNDARY
>+#define SDMA7_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT                                                         0x0
>+#define SDMA7_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK                                                           0xFFFFFFFFL
>+//SDMA7_POWER_CNTL
>+#define SDMA7_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT                                                           0x8
>+#define SDMA7_POWER_CNTL__MEM_POWER_LS_EN__SHIFT                                                              0x9
>+#define SDMA7_POWER_CNTL__MEM_POWER_DS_EN__SHIFT                                                              0xa
>+#define SDMA7_POWER_CNTL__MEM_POWER_SD_EN__SHIFT                                                              0xb
>+#define SDMA7_POWER_CNTL__MEM_POWER_DELAY__SHIFT                                                              0xc
>+#define SDMA7_POWER_CNTL__MEM_POWER_OVERRIDE_MASK                                                             0x00000100L
>+#define SDMA7_POWER_CNTL__MEM_POWER_LS_EN_MASK                                                                0x00000200L
>+#define SDMA7_POWER_CNTL__MEM_POWER_DS_EN_MASK                                                                0x00000400L
>+#define SDMA7_POWER_CNTL__MEM_POWER_SD_EN_MASK                                                                0x00000800L
>+#define SDMA7_POWER_CNTL__MEM_POWER_DELAY_MASK                                                                0x003FF000L
>+//SDMA7_CLK_CTRL
>+#define SDMA7_CLK_CTRL__ON_DELAY__SHIFT                                                                       0x0
>+#define SDMA7_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                                 0x4
>+#define SDMA7_CLK_CTRL__RESERVED__SHIFT                                                                       0xc
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE7__SHIFT                                                                 0x18
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE6__SHIFT                                                                 0x19
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE5__SHIFT                                                                 0x1a
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE4__SHIFT                                                                 0x1b
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE3__SHIFT                                                                 0x1c
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE2__SHIFT                                                                 0x1d
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE1__SHIFT                                                                 0x1e
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE0__SHIFT                                                                 0x1f
>+#define SDMA7_CLK_CTRL__ON_DELAY_MASK                                                                         0x0000000FL
>+#define SDMA7_CLK_CTRL__OFF_HYSTERESIS_MASK                                                                   0x00000FF0L
>+#define SDMA7_CLK_CTRL__RESERVED_MASK                                                                         0x00FFF000L
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE7_MASK                                                                   0x01000000L
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE6_MASK                                                                   0x02000000L
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE5_MASK                                                                   0x04000000L
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE4_MASK                                                                   0x08000000L
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE3_MASK                                                                   0x10000000L
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE2_MASK                                                                   0x20000000L
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE1_MASK                                                                   0x40000000L
>+#define SDMA7_CLK_CTRL__SOFT_OVERRIDE0_MASK                                                                   0x80000000L
>+//SDMA7_CNTL
>+#define SDMA7_CNTL__TRAP_ENABLE__SHIFT                                                                        0x0
>+#define SDMA7_CNTL__UTC_L1_ENABLE__SHIFT                                                                      0x1
>+#define SDMA7_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
>+#define SDMA7_CNTL__DATA_SWAP_ENABLE__SHIFT                                                                   0x3
>+#define SDMA7_CNTL__FENCE_SWAP_ENABLE__SHIFT                                                                  0x4
>+#define SDMA7_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT                                                              0x5
>+#define SDMA7_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT                                                          0x11
>+#define SDMA7_CNTL__AUTO_CTXSW_ENABLE__SHIFT                                                                  0x12
>+#define SDMA7_CNTL__CTXEMPTY_INT_ENABLE__SHIFT                                                                0x1c
>+#define SDMA7_CNTL__FROZEN_INT_ENABLE__SHIFT                                                                  0x1d
>+#define SDMA7_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT                                                              0x1e
>+#define SDMA7_CNTL__TRAP_ENABLE_MASK                                                                          0x00000001L
>+#define SDMA7_CNTL__UTC_L1_ENABLE_MASK                                                                        0x00000002L
>+#define SDMA7_CNTL__SEM_WAIT_INT_ENABLE_MASK                                                                  0x00000004L
>+#define SDMA7_CNTL__DATA_SWAP_ENABLE_MASK                                                                     0x00000008L
>+#define SDMA7_CNTL__FENCE_SWAP_ENABLE_MASK                                                                    0x00000010L
>+#define SDMA7_CNTL__MIDCMD_PREEMPT_ENABLE_MASK                                                                0x00000020L
>+#define SDMA7_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK                                                            0x00020000L
>+#define SDMA7_CNTL__AUTO_CTXSW_ENABLE_MASK                                                                    0x00040000L
>+#define SDMA7_CNTL__CTXEMPTY_INT_ENABLE_MASK                                                                  0x10000000L
>+#define SDMA7_CNTL__FROZEN_INT_ENABLE_MASK                                                                    0x20000000L
>+#define SDMA7_CNTL__IB_PREEMPT_INT_ENABLE_MASK                                                                0x40000000L
>+//SDMA7_CHICKEN_BITS
>+#define SDMA7_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT                                                     0x0
>+#define SDMA7_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT                                                 0x1
>+#define SDMA7_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT                                        0x2
>+#define SDMA7_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT                                                         0x8
>+#define SDMA7_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT                                                     0xa
>+#define SDMA7_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT                                                        0x10
>+#define SDMA7_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT                                                           0x11
>+#define SDMA7_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT                                                         0x14
>+#define SDMA7_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT                                                           0x17
>+#define SDMA7_CHICKEN_BITS__TIME_BASED_QOS__SHIFT                                                             0x19
>+#define SDMA7_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT                                                         0x1a
>+#define SDMA7_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
>+#define SDMA7_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT                                                         0x1e
>+#define SDMA7_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK                                                       0x00000001L
>+#define SDMA7_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK                                                   0x00000002L
>+#define SDMA7_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK                                          0x00000004L
>+#define SDMA7_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK                                                           0x00000300L
>+#define SDMA7_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK                                                       0x00001C00L
>+#define SDMA7_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK                                                          0x00010000L
>+#define SDMA7_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK                                                             0x00020000L
>+#define SDMA7_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK                                                           0x00100000L
>+#define SDMA7_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK                                                             0x00800000L
>+#define SDMA7_CHICKEN_BITS__TIME_BASED_QOS_MASK                                                               0x02000000L
>+#define SDMA7_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK                                                           0x0C000000L
>+#define SDMA7_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK                                                           0x30000000L
>+#define SDMA7_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK                                                           0xC0000000L
>+//SDMA7_GB_ADDR_CONFIG
>+#define SDMA7_GB_ADDR_CONFIG__NUM_PIPES__SHIFT                                                                0x0
>+#define SDMA7_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x3
>+#define SDMA7_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT                                                     0x8
>+#define SDMA7_GB_ADDR_CONFIG__NUM_BANKS__SHIFT                                                                0xc
>+#define SDMA7_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                       0x13
>+#define SDMA7_GB_ADDR_CONFIG__NUM_PIPES_MASK                                                                  0x00000007L
>+#define SDMA7_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000038L
>+#define SDMA7_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK                                                       0x00000700L
>+#define SDMA7_GB_ADDR_CONFIG__NUM_BANKS_MASK                                                                  0x00007000L
>+#define SDMA7_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                         0x00180000L
>+//SDMA7_GB_ADDR_CONFIG_READ
>+#define SDMA7_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT                                                           0x0
>+#define SDMA7_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x3
>+#define SDMA7_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT                                                0x8
>+#define SDMA7_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT                                                           0xc
>+#define SDMA7_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT                                                  0x13
>+#define SDMA7_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK                                                             0x00000007L
>+#define SDMA7_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000038L
>+#define SDMA7_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK                                                  0x00000700L
>+#define SDMA7_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK                                                             0x00007000L
>+#define SDMA7_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK                                                    0x00180000L
>+//SDMA7_RB_RPTR_FETCH_HI
>+#define SDMA7_RB_RPTR_FETCH_HI__OFFSET__SHIFT                                                                 0x0
>+#define SDMA7_RB_RPTR_FETCH_HI__OFFSET_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_SEM_WAIT_FAIL_TIMER_CNTL
>+#define SDMA7_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
>+#define SDMA7_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK                                                            0xFFFFFFFFL
>+//SDMA7_RB_RPTR_FETCH
>+#define SDMA7_RB_RPTR_FETCH__OFFSET__SHIFT                                                                    0x2
>+#define SDMA7_RB_RPTR_FETCH__OFFSET_MASK                                                                      0xFFFFFFFCL
>+//SDMA7_IB_OFFSET_FETCH
>+#define SDMA7_IB_OFFSET_FETCH__OFFSET__SHIFT                                                                  0x2
>+#define SDMA7_IB_OFFSET_FETCH__OFFSET_MASK                                                                    0x003FFFFCL
>+//SDMA7_PROGRAM
>+#define SDMA7_PROGRAM__STREAM__SHIFT                                                                          0x0
>+#define SDMA7_PROGRAM__STREAM_MASK                                                                            0xFFFFFFFFL
>+//SDMA7_STATUS_REG
>+#define SDMA7_STATUS_REG__IDLE__SHIFT                                                                         0x0
>+#define SDMA7_STATUS_REG__REG_IDLE__SHIFT                                                                     0x1
>+#define SDMA7_STATUS_REG__RB_EMPTY__SHIFT                                                                     0x2
>+#define SDMA7_STATUS_REG__RB_FULL__SHIFT                                                                      0x3
>+#define SDMA7_STATUS_REG__RB_CMD_IDLE__SHIFT                                                                  0x4
>+#define SDMA7_STATUS_REG__RB_CMD_FULL__SHIFT                                                                  0x5
>+#define SDMA7_STATUS_REG__IB_CMD_IDLE__SHIFT                                                                  0x6
>+#define SDMA7_STATUS_REG__IB_CMD_FULL__SHIFT                                                                  0x7
>+#define SDMA7_STATUS_REG__BLOCK_IDLE__SHIFT                                                                   0x8
>+#define SDMA7_STATUS_REG__INSIDE_IB__SHIFT                                                                    0x9
>+#define SDMA7_STATUS_REG__EX_IDLE__SHIFT                                                                      0xa
>+#define SDMA7_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT                                                    0xb
>+#define SDMA7_STATUS_REG__PACKET_READY__SHIFT                                                                 0xc
>+#define SDMA7_STATUS_REG__MC_WR_IDLE__SHIFT                                                                   0xd
>+#define SDMA7_STATUS_REG__SRBM_IDLE__SHIFT                                                                    0xe
>+#define SDMA7_STATUS_REG__CONTEXT_EMPTY__SHIFT                                                                0xf
>+#define SDMA7_STATUS_REG__DELTA_RPTR_FULL__SHIFT                                                              0x10
>+#define SDMA7_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT                                                              0x11
>+#define SDMA7_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT                                                              0x12
>+#define SDMA7_STATUS_REG__MC_RD_IDLE__SHIFT                                                                   0x13
>+#define SDMA7_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT                                                             0x14
>+#define SDMA7_STATUS_REG__MC_RD_RET_STALL__SHIFT                                                              0x15
>+#define SDMA7_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT                                                           0x16
>+#define SDMA7_STATUS_REG__PREV_CMD_IDLE__SHIFT                                                                0x19
>+#define SDMA7_STATUS_REG__SEM_IDLE__SHIFT                                                                     0x1a
>+#define SDMA7_STATUS_REG__SEM_REQ_STALL__SHIFT                                                                0x1b
>+#define SDMA7_STATUS_REG__SEM_RESP_STATE__SHIFT                                                               0x1c
>+#define SDMA7_STATUS_REG__INT_IDLE__SHIFT                                                                     0x1e
>+#define SDMA7_STATUS_REG__INT_REQ_STALL__SHIFT                                                                0x1f
>+#define SDMA7_STATUS_REG__IDLE_MASK                                                                           0x00000001L
>+#define SDMA7_STATUS_REG__REG_IDLE_MASK                                                                       0x00000002L
>+#define SDMA7_STATUS_REG__RB_EMPTY_MASK                                                                       0x00000004L
>+#define SDMA7_STATUS_REG__RB_FULL_MASK                                                                        0x00000008L
>+#define SDMA7_STATUS_REG__RB_CMD_IDLE_MASK                                                                    0x00000010L
>+#define SDMA7_STATUS_REG__RB_CMD_FULL_MASK                                                                    0x00000020L
>+#define SDMA7_STATUS_REG__IB_CMD_IDLE_MASK                                                                    0x00000040L
>+#define SDMA7_STATUS_REG__IB_CMD_FULL_MASK                                                                    0x00000080L
>+#define SDMA7_STATUS_REG__BLOCK_IDLE_MASK                                                                     0x00000100L
>+#define SDMA7_STATUS_REG__INSIDE_IB_MASK                                                                      0x00000200L
>+#define SDMA7_STATUS_REG__EX_IDLE_MASK                                                                        0x00000400L
>+#define SDMA7_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK                                                      0x00000800L
>+#define SDMA7_STATUS_REG__PACKET_READY_MASK                                                                   0x00001000L
>+#define SDMA7_STATUS_REG__MC_WR_IDLE_MASK                                                                     0x00002000L
>+#define SDMA7_STATUS_REG__SRBM_IDLE_MASK                                                                      0x00004000L
>+#define SDMA7_STATUS_REG__CONTEXT_EMPTY_MASK                                                                  0x00008000L
>+#define SDMA7_STATUS_REG__DELTA_RPTR_FULL_MASK                                                                0x00010000L
>+#define SDMA7_STATUS_REG__RB_MC_RREQ_IDLE_MASK                                                                0x00020000L
>+#define SDMA7_STATUS_REG__IB_MC_RREQ_IDLE_MASK                                                                0x00040000L
>+#define SDMA7_STATUS_REG__MC_RD_IDLE_MASK                                                                     0x00080000L
>+#define SDMA7_STATUS_REG__DELTA_RPTR_EMPTY_MASK                                                               0x00100000L
>+#define SDMA7_STATUS_REG__MC_RD_RET_STALL_MASK                                                                0x00200000L
>+#define SDMA7_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK                                                             0x00400000L
>+#define SDMA7_STATUS_REG__PREV_CMD_IDLE_MASK                                                                  0x02000000L
>+#define SDMA7_STATUS_REG__SEM_IDLE_MASK                                                                       0x04000000L
>+#define SDMA7_STATUS_REG__SEM_REQ_STALL_MASK                                                                  0x08000000L
>+#define SDMA7_STATUS_REG__SEM_RESP_STATE_MASK                                                                 0x30000000L
>+#define SDMA7_STATUS_REG__INT_IDLE_MASK                                                                       0x40000000L
>+#define SDMA7_STATUS_REG__INT_REQ_STALL_MASK                                                                  0x80000000L
>+//SDMA7_STATUS1_REG
>+#define SDMA7_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
>+#define SDMA7_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
>+#define SDMA7_STATUS1_REG__CE_SPLIT_IDLE__SHIFT                                                               0x2
>+#define SDMA7_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
>+#define SDMA7_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
>+#define SDMA7_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
>+#define SDMA7_STATUS1_REG__CE_DST_IDLE__SHIFT                                                                 0x6
>+#define SDMA7_STATUS1_REG__CE_CMD_IDLE__SHIFT                                                                 0x9
>+#define SDMA7_STATUS1_REG__CE_AFIFO_FULL__SHIFT                                                               0xa
>+#define SDMA7_STATUS1_REG__CE_INFO_FULL__SHIFT                                                                0xd
>+#define SDMA7_STATUS1_REG__CE_INFO1_FULL__SHIFT                                                               0xe
>+#define SDMA7_STATUS1_REG__EX_START__SHIFT                                                                    0xf
>+#define SDMA7_STATUS1_REG__CE_RD_STALL__SHIFT                                                                 0x11
>+#define SDMA7_STATUS1_REG__CE_WR_STALL__SHIFT                                                                 0x12
>+#define SDMA7_STATUS1_REG__CE_WREQ_IDLE_MASK                                                                  0x00000001L
>+#define SDMA7_STATUS1_REG__CE_WR_IDLE_MASK                                                                    0x00000002L
>+#define SDMA7_STATUS1_REG__CE_SPLIT_IDLE_MASK                                                                 0x00000004L
>+#define SDMA7_STATUS1_REG__CE_RREQ_IDLE_MASK                                                                  0x00000008L
>+#define SDMA7_STATUS1_REG__CE_OUT_IDLE_MASK                                                                   0x00000010L
>+#define SDMA7_STATUS1_REG__CE_IN_IDLE_MASK                                                                    0x00000020L
>+#define SDMA7_STATUS1_REG__CE_DST_IDLE_MASK                                                                   0x00000040L
>+#define SDMA7_STATUS1_REG__CE_CMD_IDLE_MASK                                                                   0x00000200L
>+#define SDMA7_STATUS1_REG__CE_AFIFO_FULL_MASK                                                                 0x00000400L
>+#define SDMA7_STATUS1_REG__CE_INFO_FULL_MASK                                                                  0x00002000L
>+#define SDMA7_STATUS1_REG__CE_INFO1_FULL_MASK                                                                 0x00004000L
>+#define SDMA7_STATUS1_REG__EX_START_MASK                                                                      0x00008000L
>+#define SDMA7_STATUS1_REG__CE_RD_STALL_MASK                                                                   0x00020000L
>+#define SDMA7_STATUS1_REG__CE_WR_STALL_MASK                                                                   0x00040000L
>+//SDMA7_RD_BURST_CNTL
>+#define SDMA7_RD_BURST_CNTL__RD_BURST__SHIFT                                                                  0x0
>+#define SDMA7_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT                                                       0x2
>+#define SDMA7_RD_BURST_CNTL__RD_BURST_MASK                                                                    0x00000003L
>+#define SDMA7_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK                                                         0x0000000CL
>+//SDMA7_HBM_PAGE_CONFIG
>+#define SDMA7_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT                                                      0x0
>+#define SDMA7_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK                                                        0x00000001L
>+//SDMA7_UCODE_CHECKSUM
>+#define SDMA7_UCODE_CHECKSUM__DATA__SHIFT                                                                     0x0
>+#define SDMA7_UCODE_CHECKSUM__DATA_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_F32_CNTL
>+#define SDMA7_F32_CNTL__HALT__SHIFT                                                                           0x0
>+#define SDMA7_F32_CNTL__STEP__SHIFT                                                                           0x1
>+#define SDMA7_F32_CNTL__HALT_MASK                                                                             0x00000001L
>+#define SDMA7_F32_CNTL__STEP_MASK                                                                             0x00000002L
>+//SDMA7_FREEZE
>+#define SDMA7_FREEZE__PREEMPT__SHIFT                                                                          0x0
>+#define SDMA7_FREEZE__FREEZE__SHIFT                                                                           0x4
>+#define SDMA7_FREEZE__FROZEN__SHIFT                                                                           0x5
>+#define SDMA7_FREEZE__F32_FREEZE__SHIFT                                                                       0x6
>+#define SDMA7_FREEZE__PREEMPT_MASK                                                                            0x00000001L
>+#define SDMA7_FREEZE__FREEZE_MASK                                                                             0x00000010L
>+#define SDMA7_FREEZE__FROZEN_MASK                                                                             0x00000020L
>+#define SDMA7_FREEZE__F32_FREEZE_MASK                                                                         0x00000040L
>+//SDMA7_PHASE0_QUANTUM
>+#define SDMA7_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA7_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA7_PHASE0_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA7_PHASE0_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA7_PHASE0_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA7_PHASE0_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA7_PHASE1_QUANTUM
>+#define SDMA7_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA7_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA7_PHASE1_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA7_PHASE1_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA7_PHASE1_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA7_PHASE1_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA7_EDC_CONFIG
>+#define SDMA7_EDC_CONFIG__DIS_EDC__SHIFT                                                                      0x1
>+#define SDMA7_EDC_CONFIG__ECC_INT_ENABLE__SHIFT                                                               0x2
>+#define SDMA7_EDC_CONFIG__DIS_EDC_MASK                                                                        0x00000002L
>+#define SDMA7_EDC_CONFIG__ECC_INT_ENABLE_MASK                                                                 0x00000004L
>+//SDMA7_BA_THRESHOLD
>+#define SDMA7_BA_THRESHOLD__READ_THRES__SHIFT                                                                 0x0
>+#define SDMA7_BA_THRESHOLD__WRITE_THRES__SHIFT                                                                0x10
>+#define SDMA7_BA_THRESHOLD__READ_THRES_MASK                                                                   0x000003FFL
>+#define SDMA7_BA_THRESHOLD__WRITE_THRES_MASK                                                                  0x03FF0000L
>+//SDMA7_ID
>+#define SDMA7_ID__DEVICE_ID__SHIFT                                                                            0x0
>+#define SDMA7_ID__DEVICE_ID_MASK                                                                              0x000000FFL
>+//SDMA7_VERSION
>+#define SDMA7_VERSION__MINVER__SHIFT                                                                          0x0
>+#define SDMA7_VERSION__MAJVER__SHIFT                                                                          0x8
>+#define SDMA7_VERSION__REV__SHIFT                                                                             0x10
>+#define SDMA7_VERSION__MINVER_MASK                                                                            0x0000007FL
>+#define SDMA7_VERSION__MAJVER_MASK                                                                            0x00007F00L
>+#define SDMA7_VERSION__REV_MASK                                                                               0x003F0000L
>+//SDMA7_EDC_COUNTER
>+#define SDMA7_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT                                                          0x0
>+#define SDMA7_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT                                                         0x2
>+#define SDMA7_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT                                                         0x3
>+#define SDMA7_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT                                                      0x4
>+#define SDMA7_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT                                                   0x5
>+#define SDMA7_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT                                                      0x6
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT                                                    0x7
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT                                                    0x8
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT                                                    0x9
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT                                                    0xb
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT                                                    0xd
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT                                                    0xe
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT                                                    0xf
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT                                                    0x10
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT                                                   0x11
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT                                                   0x12
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT                                                   0x13
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT                                                   0x14
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT                                                   0x15
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT                                                   0x16
>+#define SDMA7_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT                                                      0x17
>+#define SDMA7_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT                                                    0x18
>+#define SDMA7_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK                                                            0x00000001L
>+#define SDMA7_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK                                                           0x00000004L
>+#define SDMA7_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK                                                           0x00000008L
>+#define SDMA7_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK                                                        0x00000010L
>+#define SDMA7_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK                                                     0x00000020L
>+#define SDMA7_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK                                                        0x00000040L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK                                                      0x00000080L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK                                                      0x00000100L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK                                                      0x00000200L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK                                                      0x00000400L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK                                                      0x00000800L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK                                                      0x00001000L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK                                                      0x00002000L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK                                                      0x00004000L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK                                                      0x00008000L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK                                                      0x00010000L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK                                                     0x00020000L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK                                                     0x00040000L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK                                                     0x00080000L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK                                                     0x00100000L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK                                                     0x00200000L
>+#define SDMA7_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK                                                     0x00400000L
>+#define SDMA7_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK                                                        0x00800000L
>+#define SDMA7_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK                                                      0x01000000L
>+//SDMA7_EDC_COUNTER_CLEAR
>+#define SDMA7_EDC_COUNTER_CLEAR__DUMMY__SHIFT                                                                 0x0
>+#define SDMA7_EDC_COUNTER_CLEAR__DUMMY_MASK                                                                   0x00000001L
>+//SDMA7_STATUS2_REG
>+#define SDMA7_STATUS2_REG__ID__SHIFT                                                                          0x0
>+#define SDMA7_STATUS2_REG__F32_INSTR_PTR__SHIFT                                                               0x3
>+#define SDMA7_STATUS2_REG__CMD_OP__SHIFT                                                                      0x10
>+#define SDMA7_STATUS2_REG__ID_MASK                                                                            0x00000007L
>+#define SDMA7_STATUS2_REG__F32_INSTR_PTR_MASK                                                                 0x0000FFF8L
>+#define SDMA7_STATUS2_REG__CMD_OP_MASK                                                                        0xFFFF0000L
>+//SDMA7_ATOMIC_CNTL
>+#define SDMA7_ATOMIC_CNTL__LOOP_TIMER__SHIFT                                                                  0x0
>+#define SDMA7_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT                                                       0x1f
>+#define SDMA7_ATOMIC_CNTL__LOOP_TIMER_MASK                                                                    0x7FFFFFFFL
>+#define SDMA7_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK                                                         0x80000000L
>+//SDMA7_ATOMIC_PREOP_LO
>+#define SDMA7_ATOMIC_PREOP_LO__DATA__SHIFT                                                                    0x0
>+#define SDMA7_ATOMIC_PREOP_LO__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_ATOMIC_PREOP_HI
>+#define SDMA7_ATOMIC_PREOP_HI__DATA__SHIFT                                                                    0x0
>+#define SDMA7_ATOMIC_PREOP_HI__DATA_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_UTCL1_CNTL
>+#define SDMA7_UTCL1_CNTL__REDO_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_UTCL1_CNTL__REDO_DELAY__SHIFT                                                                   0x1
>+#define SDMA7_UTCL1_CNTL__REDO_WATERMK__SHIFT                                                                 0xb
>+#define SDMA7_UTCL1_CNTL__INVACK_DELAY__SHIFT                                                                 0xe
>+#define SDMA7_UTCL1_CNTL__REQL2_CREDIT__SHIFT                                                                 0x18
>+#define SDMA7_UTCL1_CNTL__VADDR_WATERMK__SHIFT                                                                0x1d
>+#define SDMA7_UTCL1_CNTL__REDO_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_UTCL1_CNTL__REDO_DELAY_MASK                                                                     0x000007FEL
>+#define SDMA7_UTCL1_CNTL__REDO_WATERMK_MASK                                                                   0x00003800L
>+#define SDMA7_UTCL1_CNTL__INVACK_DELAY_MASK                                                                   0x00FFC000L
>+#define SDMA7_UTCL1_CNTL__REQL2_CREDIT_MASK                                                                   0x1F000000L
>+#define SDMA7_UTCL1_CNTL__VADDR_WATERMK_MASK                                                                  0xE0000000L
>+//SDMA7_UTCL1_WATERMK
>+#define SDMA7_UTCL1_WATERMK__REQMC_WATERMK__SHIFT                                                             0x0
>+#define SDMA7_UTCL1_WATERMK__REQPG_WATERMK__SHIFT                                                             0x9
>+#define SDMA7_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT                                                            0x11
>+#define SDMA7_UTCL1_WATERMK__XNACK_WATERMK__SHIFT                                                             0x19
>+#define SDMA7_UTCL1_WATERMK__REQMC_WATERMK_MASK                                                               0x000001FFL
>+#define SDMA7_UTCL1_WATERMK__REQPG_WATERMK_MASK                                                               0x0001FE00L
>+#define SDMA7_UTCL1_WATERMK__INVREQ_WATERMK_MASK                                                              0x01FE0000L
>+#define SDMA7_UTCL1_WATERMK__XNACK_WATERMK_MASK                                                               0xFE000000L
>+//SDMA7_UTCL1_RD_STATUS
>+#define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA7_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA7_UTCL1_RD_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA7_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA7_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT                                                             0x15
>+#define SDMA7_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT                                                          0x16
>+#define SDMA7_UTCL1_RD_STATUS__MERGE_STATE__SHIFT                                                             0x1a
>+#define SDMA7_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT                                                             0x1d
>+#define SDMA7_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT                                                            0x1e
>+#define SDMA7_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT                                                             0x1f
>+#define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA7_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA7_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA7_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA7_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA7_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA7_UTCL1_RD_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA7_UTCL1_RD_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA7_UTCL1_RD_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA7_UTCL1_RD_STATUS__CE_L1_STALL_MASK                                                               0x00200000L
>+#define SDMA7_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK                                                            0x03C00000L
>+#define SDMA7_UTCL1_RD_STATUS__MERGE_STATE_MASK                                                               0x1C000000L
>+#define SDMA7_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK                                                               0x20000000L
>+#define SDMA7_UTCL1_RD_STATUS__WPTR_POLLING_MASK                                                              0x40000000L
>+#define SDMA7_UTCL1_RD_STATUS__INVREQ_SIZE_MASK                                                               0x80000000L
>+//SDMA7_UTCL1_WR_STATUS
>+#define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT                                                0x0
>+#define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT                                                     0x1
>+#define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT                                                      0x2
>+#define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT                                                   0x3
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT                                               0x4
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT                                                    0x5
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT                                                 0x6
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT                                                   0x7
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT                                                  0x8
>+#define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT                                                 0x9
>+#define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT                                                      0xa
>+#define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT                                                       0xb
>+#define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT                                                    0xc
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT                                                0xd
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT                                                     0xe
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT                                                  0xf
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT                                                    0x10
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT                                                   0x11
>+#define SDMA7_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT                                                              0x12
>+#define SDMA7_UTCL1_WR_STATUS__PAGE_NULL__SHIFT                                                               0x13
>+#define SDMA7_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT                                                              0x14
>+#define SDMA7_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT                                                              0x15
>+#define SDMA7_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT                                                          0x16
>+#define SDMA7_UTCL1_WR_STATUS__MERGE_STATE__SHIFT                                                             0x19
>+#define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT                                                    0x1c
>+#define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT                                                     0x1d
>+#define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT                                                   0x1e
>+#define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT                                                    0x1f
>+#define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK                                                  0x00000001L
>+#define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK                                                       0x00000002L
>+#define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK                                                        0x00000004L
>+#define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK                                                     0x00000008L
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK                                                 0x00000010L
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK                                                      0x00000020L
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK                                                   0x00000040L
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK                                                     0x00000080L
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK                                                    0x00000100L
>+#define SDMA7_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK                                                   0x00000200L
>+#define SDMA7_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK                                                        0x00000400L
>+#define SDMA7_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK                                                         0x00000800L
>+#define SDMA7_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK                                                      0x00001000L
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK                                                  0x00002000L
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK                                                       0x00004000L
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK                                                    0x00008000L
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK                                                      0x00010000L
>+#define SDMA7_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK                                                     0x00020000L
>+#define SDMA7_UTCL1_WR_STATUS__PAGE_FAULT_MASK                                                                0x00040000L
>+#define SDMA7_UTCL1_WR_STATUS__PAGE_NULL_MASK                                                                 0x00080000L
>+#define SDMA7_UTCL1_WR_STATUS__REQL2_IDLE_MASK                                                                0x00100000L
>+#define SDMA7_UTCL1_WR_STATUS__F32_WR_RTR_MASK                                                                0x00200000L
>+#define SDMA7_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK                                                            0x01C00000L
>+#define SDMA7_UTCL1_WR_STATUS__MERGE_STATE_MASK                                                               0x0E000000L
>+#define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK                                                      0x10000000L
>+#define SDMA7_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK                                                       0x20000000L
>+#define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK                                                     0x40000000L
>+#define SDMA7_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK                                                      0x80000000L
>+//SDMA7_UTCL1_INV0
>+#define SDMA7_UTCL1_INV0__INV_MIDDLE__SHIFT                                                                   0x0
>+#define SDMA7_UTCL1_INV0__RD_TIMEOUT__SHIFT                                                                   0x1
>+#define SDMA7_UTCL1_INV0__WR_TIMEOUT__SHIFT                                                                   0x2
>+#define SDMA7_UTCL1_INV0__RD_IN_INVADR__SHIFT                                                                 0x3
>+#define SDMA7_UTCL1_INV0__WR_IN_INVADR__SHIFT                                                                 0x4
>+#define SDMA7_UTCL1_INV0__PAGE_NULL_SW__SHIFT                                                                 0x5
>+#define SDMA7_UTCL1_INV0__XNACK_IS_INVADR__SHIFT                                                              0x6
>+#define SDMA7_UTCL1_INV0__INVREQ_ENABLE__SHIFT                                                                0x7
>+#define SDMA7_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT                                                              0x8
>+#define SDMA7_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT                                                              0x9
>+#define SDMA7_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT                                                               0xa
>+#define SDMA7_UTCL1_INV0__INV_FLUSHTYPE__SHIFT                                                                0xb
>+#define SDMA7_UTCL1_INV0__INV_VMID_VEC__SHIFT                                                                 0xc
>+#define SDMA7_UTCL1_INV0__INV_ADDR_HI__SHIFT                                                                  0x1c
>+#define SDMA7_UTCL1_INV0__INV_MIDDLE_MASK                                                                     0x00000001L
>+#define SDMA7_UTCL1_INV0__RD_TIMEOUT_MASK                                                                     0x00000002L
>+#define SDMA7_UTCL1_INV0__WR_TIMEOUT_MASK                                                                     0x00000004L
>+#define SDMA7_UTCL1_INV0__RD_IN_INVADR_MASK                                                                   0x00000008L
>+#define SDMA7_UTCL1_INV0__WR_IN_INVADR_MASK                                                                   0x00000010L
>+#define SDMA7_UTCL1_INV0__PAGE_NULL_SW_MASK                                                                   0x00000020L
>+#define SDMA7_UTCL1_INV0__XNACK_IS_INVADR_MASK                                                                0x00000040L
>+#define SDMA7_UTCL1_INV0__INVREQ_ENABLE_MASK                                                                  0x00000080L
>+#define SDMA7_UTCL1_INV0__NACK_TIMEOUT_SW_MASK                                                                0x00000100L
>+#define SDMA7_UTCL1_INV0__NFLUSH_INV_IDLE_MASK                                                                0x00000200L
>+#define SDMA7_UTCL1_INV0__FLUSH_INV_IDLE_MASK                                                                 0x00000400L
>+#define SDMA7_UTCL1_INV0__INV_FLUSHTYPE_MASK                                                                  0x00000800L
>+#define SDMA7_UTCL1_INV0__INV_VMID_VEC_MASK                                                                   0x0FFFF000L
>+#define SDMA7_UTCL1_INV0__INV_ADDR_HI_MASK                                                                    0xF0000000L
>+//SDMA7_UTCL1_INV1
>+#define SDMA7_UTCL1_INV1__INV_ADDR_LO__SHIFT                                                                  0x0
>+#define SDMA7_UTCL1_INV1__INV_ADDR_LO_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_UTCL1_INV2
>+#define SDMA7_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT                                                          0x0
>+#define SDMA7_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK                                                            0xFFFFFFFFL
>+//SDMA7_UTCL1_RD_XNACK0
>+#define SDMA7_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA7_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA7_UTCL1_RD_XNACK1
>+#define SDMA7_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA7_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA7_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA7_UTCL1_RD_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA7_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA7_UTCL1_RD_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA7_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA7_UTCL1_RD_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA7_UTCL1_WR_XNACK0
>+#define SDMA7_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT                                                           0x0
>+#define SDMA7_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK                                                             0xFFFFFFFFL
>+//SDMA7_UTCL1_WR_XNACK1
>+#define SDMA7_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT                                                           0x0
>+#define SDMA7_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT                                                              0x4
>+#define SDMA7_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT                                                            0x8
>+#define SDMA7_UTCL1_WR_XNACK1__IS_XNACK__SHIFT                                                                0x1a
>+#define SDMA7_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK                                                             0x0000000FL
>+#define SDMA7_UTCL1_WR_XNACK1__XNACK_VMID_MASK                                                                0x000000F0L
>+#define SDMA7_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK                                                              0x03FFFF00L
>+#define SDMA7_UTCL1_WR_XNACK1__IS_XNACK_MASK                                                                  0x0C000000L
>+//SDMA7_UTCL1_TIMEOUT
>+#define SDMA7_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT                                                            0x0
>+#define SDMA7_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT                                                            0x10
>+#define SDMA7_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK                                                              0x0000FFFFL
>+#define SDMA7_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK                                                              0xFFFF0000L
>+//SDMA7_UTCL1_PAGE
>+#define SDMA7_UTCL1_PAGE__VM_HOLE__SHIFT                                                                      0x0
>+#define SDMA7_UTCL1_PAGE__REQ_TYPE__SHIFT                                                                     0x1
>+#define SDMA7_UTCL1_PAGE__USE_MTYPE__SHIFT                                                                    0x6
>+#define SDMA7_UTCL1_PAGE__USE_PT_SNOOP__SHIFT                                                                 0x9
>+#define SDMA7_UTCL1_PAGE__VM_HOLE_MASK                                                                        0x00000001L
>+#define SDMA7_UTCL1_PAGE__REQ_TYPE_MASK                                                                       0x0000001EL
>+#define SDMA7_UTCL1_PAGE__USE_MTYPE_MASK                                                                      0x000001C0L
>+#define SDMA7_UTCL1_PAGE__USE_PT_SNOOP_MASK                                                                   0x00000200L
>+//SDMA7_POWER_CNTL_IDLE
>+#define SDMA7_POWER_CNTL_IDLE__DELAY0__SHIFT                                                                  0x0
>+#define SDMA7_POWER_CNTL_IDLE__DELAY1__SHIFT                                                                  0x10
>+#define SDMA7_POWER_CNTL_IDLE__DELAY2__SHIFT                                                                  0x18
>+#define SDMA7_POWER_CNTL_IDLE__DELAY0_MASK                                                                    0x0000FFFFL
>+#define SDMA7_POWER_CNTL_IDLE__DELAY1_MASK                                                                    0x00FF0000L
>+#define SDMA7_POWER_CNTL_IDLE__DELAY2_MASK                                                                    0xFF000000L
>+//SDMA7_RELAX_ORDERING_LUT
>+#define SDMA7_RELAX_ORDERING_LUT__RESERVED0__SHIFT                                                            0x0
>+#define SDMA7_RELAX_ORDERING_LUT__COPY__SHIFT                                                                 0x1
>+#define SDMA7_RELAX_ORDERING_LUT__WRITE__SHIFT                                                                0x2
>+#define SDMA7_RELAX_ORDERING_LUT__RESERVED3__SHIFT                                                            0x3
>+#define SDMA7_RELAX_ORDERING_LUT__RESERVED4__SHIFT                                                            0x4
>+#define SDMA7_RELAX_ORDERING_LUT__FENCE__SHIFT                                                                0x5
>+#define SDMA7_RELAX_ORDERING_LUT__RESERVED76__SHIFT                                                           0x6
>+#define SDMA7_RELAX_ORDERING_LUT__POLL_MEM__SHIFT                                                             0x8
>+#define SDMA7_RELAX_ORDERING_LUT__COND_EXE__SHIFT                                                             0x9
>+#define SDMA7_RELAX_ORDERING_LUT__ATOMIC__SHIFT                                                               0xa
>+#define SDMA7_RELAX_ORDERING_LUT__CONST_FILL__SHIFT                                                           0xb
>+#define SDMA7_RELAX_ORDERING_LUT__PTEPDE__SHIFT                                                               0xc
>+#define SDMA7_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT                                                            0xd
>+#define SDMA7_RELAX_ORDERING_LUT__RESERVED__SHIFT                                                             0xe
>+#define SDMA7_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT                                                         0x1b
>+#define SDMA7_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT                                                             0x1c
>+#define SDMA7_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT                                                            0x1d
>+#define SDMA7_RELAX_ORDERING_LUT__IB_FETCH__SHIFT                                                             0x1e
>+#define SDMA7_RELAX_ORDERING_LUT__RB_FETCH__SHIFT                                                             0x1f
>+#define SDMA7_RELAX_ORDERING_LUT__RESERVED0_MASK                                                              0x00000001L
>+#define SDMA7_RELAX_ORDERING_LUT__COPY_MASK                                                                   0x00000002L
>+#define SDMA7_RELAX_ORDERING_LUT__WRITE_MASK                                                                  0x00000004L
>+#define SDMA7_RELAX_ORDERING_LUT__RESERVED3_MASK                                                              0x00000008L
>+#define SDMA7_RELAX_ORDERING_LUT__RESERVED4_MASK                                                              0x00000010L
>+#define SDMA7_RELAX_ORDERING_LUT__FENCE_MASK                                                                  0x00000020L
>+#define SDMA7_RELAX_ORDERING_LUT__RESERVED76_MASK                                                             0x000000C0L
>+#define SDMA7_RELAX_ORDERING_LUT__POLL_MEM_MASK                                                               0x00000100L
>+#define SDMA7_RELAX_ORDERING_LUT__COND_EXE_MASK                                                               0x00000200L
>+#define SDMA7_RELAX_ORDERING_LUT__ATOMIC_MASK                                                                 0x00000400L
>+#define SDMA7_RELAX_ORDERING_LUT__CONST_FILL_MASK                                                             0x00000800L
>+#define SDMA7_RELAX_ORDERING_LUT__PTEPDE_MASK                                                                 0x00001000L
>+#define SDMA7_RELAX_ORDERING_LUT__TIMESTAMP_MASK                                                              0x00002000L
>+#define SDMA7_RELAX_ORDERING_LUT__RESERVED_MASK                                                               0x07FFC000L
>+#define SDMA7_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK                                                           0x08000000L
>+#define SDMA7_RELAX_ORDERING_LUT__RPTR_WRB_MASK                                                               0x10000000L
>+#define SDMA7_RELAX_ORDERING_LUT__WPTR_POLL_MASK                                                              0x20000000L
>+#define SDMA7_RELAX_ORDERING_LUT__IB_FETCH_MASK                                                               0x40000000L
>+#define SDMA7_RELAX_ORDERING_LUT__RB_FETCH_MASK                                                               0x80000000L
>+//SDMA7_CHICKEN_BITS_2
>+#define SDMA7_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT                                                       0x0
>+#define SDMA7_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK                                                         0x0000000FL
>+//SDMA7_STATUS3_REG
>+#define SDMA7_STATUS3_REG__CMD_OP_STATUS__SHIFT                                                               0x0
>+#define SDMA7_STATUS3_REG__PREV_VM_CMD__SHIFT                                                                 0x10
>+#define SDMA7_STATUS3_REG__EXCEPTION_IDLE__SHIFT                                                              0x14
>+#define SDMA7_STATUS3_REG__QUEUE_ID_MATCH__SHIFT                                                              0x15
>+#define SDMA7_STATUS3_REG__INT_QUEUE_ID__SHIFT                                                                0x16
>+#define SDMA7_STATUS3_REG__CMD_OP_STATUS_MASK                                                                 0x0000FFFFL
>+#define SDMA7_STATUS3_REG__PREV_VM_CMD_MASK                                                                   0x000F0000L
>+#define SDMA7_STATUS3_REG__EXCEPTION_IDLE_MASK                                                                0x00100000L
>+#define SDMA7_STATUS3_REG__QUEUE_ID_MATCH_MASK                                                                0x00200000L
>+#define SDMA7_STATUS3_REG__INT_QUEUE_ID_MASK                                                                  0x03C00000L
>+//SDMA7_PHYSICAL_ADDR_LO
>+#define SDMA7_PHYSICAL_ADDR_LO__D_VALID__SHIFT                                                                0x0
>+#define SDMA7_PHYSICAL_ADDR_LO__DIRTY__SHIFT                                                                  0x1
>+#define SDMA7_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT                                                              0x2
>+#define SDMA7_PHYSICAL_ADDR_LO__ADDR__SHIFT                                                                   0xc
>+#define SDMA7_PHYSICAL_ADDR_LO__D_VALID_MASK                                                                  0x00000001L
>+#define SDMA7_PHYSICAL_ADDR_LO__DIRTY_MASK                                                                    0x00000002L
>+#define SDMA7_PHYSICAL_ADDR_LO__PHY_VALID_MASK                                                                0x00000004L
>+#define SDMA7_PHYSICAL_ADDR_LO__ADDR_MASK                                                                     0xFFFFF000L
>+//SDMA7_PHYSICAL_ADDR_HI
>+#define SDMA7_PHYSICAL_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA7_PHYSICAL_ADDR_HI__ADDR_MASK                                                                     0x0000FFFFL
>+//SDMA7_PHASE2_QUANTUM
>+#define SDMA7_PHASE2_QUANTUM__UNIT__SHIFT                                                                     0x0
>+#define SDMA7_PHASE2_QUANTUM__VALUE__SHIFT                                                                    0x8
>+#define SDMA7_PHASE2_QUANTUM__PREFER__SHIFT                                                                   0x1e
>+#define SDMA7_PHASE2_QUANTUM__UNIT_MASK                                                                       0x0000000FL
>+#define SDMA7_PHASE2_QUANTUM__VALUE_MASK                                                                      0x00FFFF00L
>+#define SDMA7_PHASE2_QUANTUM__PREFER_MASK                                                                     0x40000000L
>+//SDMA7_ERROR_LOG
>+#define SDMA7_ERROR_LOG__OVERRIDE__SHIFT                                                                      0x0
>+#define SDMA7_ERROR_LOG__STATUS__SHIFT                                                                        0x10
>+#define SDMA7_ERROR_LOG__OVERRIDE_MASK                                                                        0x0000FFFFL
>+#define SDMA7_ERROR_LOG__STATUS_MASK                                                                          0xFFFF0000L
>+//SDMA7_PUB_DUMMY_REG0
>+#define SDMA7_PUB_DUMMY_REG0__VALUE__SHIFT                                                                    0x0
>+#define SDMA7_PUB_DUMMY_REG0__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_PUB_DUMMY_REG1
>+#define SDMA7_PUB_DUMMY_REG1__VALUE__SHIFT                                                                    0x0
>+#define SDMA7_PUB_DUMMY_REG1__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_PUB_DUMMY_REG2
>+#define SDMA7_PUB_DUMMY_REG2__VALUE__SHIFT                                                                    0x0
>+#define SDMA7_PUB_DUMMY_REG2__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_PUB_DUMMY_REG3
>+#define SDMA7_PUB_DUMMY_REG3__VALUE__SHIFT                                                                    0x0
>+#define SDMA7_PUB_DUMMY_REG3__VALUE_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_F32_COUNTER
>+#define SDMA7_F32_COUNTER__VALUE__SHIFT                                                                       0x0
>+#define SDMA7_F32_COUNTER__VALUE_MASK                                                                         0xFFFFFFFFL
>+//SDMA7_UNBREAKABLE
>+#define SDMA7_UNBREAKABLE__VALUE__SHIFT                                                                       0x0
>+#define SDMA7_UNBREAKABLE__VALUE_MASK                                                                         0x00000001L
>+//SDMA7_PERFMON_CNTL
>+#define SDMA7_PERFMON_CNTL__PERF_ENABLE0__SHIFT                                                               0x0
>+#define SDMA7_PERFMON_CNTL__PERF_CLEAR0__SHIFT                                                                0x1
>+#define SDMA7_PERFMON_CNTL__PERF_SEL0__SHIFT                                                                  0x2
>+#define SDMA7_PERFMON_CNTL__PERF_ENABLE1__SHIFT                                                               0xa
>+#define SDMA7_PERFMON_CNTL__PERF_CLEAR1__SHIFT                                                                0xb
>+#define SDMA7_PERFMON_CNTL__PERF_SEL1__SHIFT                                                                  0xc
>+#define SDMA7_PERFMON_CNTL__PERF_ENABLE0_MASK                                                                 0x00000001L
>+#define SDMA7_PERFMON_CNTL__PERF_CLEAR0_MASK                                                                  0x00000002L
>+#define SDMA7_PERFMON_CNTL__PERF_SEL0_MASK                                                                    0x000003FCL
>+#define SDMA7_PERFMON_CNTL__PERF_ENABLE1_MASK                                                                 0x00000400L
>+#define SDMA7_PERFMON_CNTL__PERF_CLEAR1_MASK                                                                  0x00000800L
>+#define SDMA7_PERFMON_CNTL__PERF_SEL1_MASK                                                                    0x000FF000L
>+//SDMA7_PERFCOUNTER0_RESULT
>+#define SDMA7_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA7_PERFCOUNTER0_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA7_PERFCOUNTER1_RESULT
>+#define SDMA7_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT                                                          0x0
>+#define SDMA7_PERFCOUNTER1_RESULT__PERF_COUNT_MASK                                                            0xFFFFFFFFL
>+//SDMA7_PERFCOUNTER_TAG_DELAY_RANGE
>+#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT                                                   0x0
>+#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT                                                  0xe
>+#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT                                                   0x1c
>+#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK                                                     0x00003FFFL
>+#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK                                                    0x0FFFC000L
>+#define SDMA7_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK                                                     0x10000000L
>+//SDMA7_CRD_CNTL
>+#define SDMA7_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT                                                                0x7
>+#define SDMA7_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT                                                                0xd
>+#define SDMA7_CRD_CNTL__MC_WRREQ_CREDIT_MASK                                                                  0x00001F80L
>+#define SDMA7_CRD_CNTL__MC_RDREQ_CREDIT_MASK                                                                  0x0007E000L
>+//SDMA7_GPU_IOV_VIOLATION_LOG
>+#define SDMA7_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT                                                  0x0
>+#define SDMA7_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT                                         0x1
>+#define SDMA7_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT                                                           0x2
>+#define SDMA7_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT                                                   0x14
>+#define SDMA7_GPU_IOV_VIOLATION_LOG__VF__SHIFT                                                                0x15
>+#define SDMA7_GPU_IOV_VIOLATION_LOG__VFID__SHIFT                                                              0x16
>+#define SDMA7_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK                                                    0x00000001L
>+#define SDMA7_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK                                           0x00000002L
>+#define SDMA7_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK                                                             0x000FFFFCL
>+#define SDMA7_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK                                                     0x00100000L
>+#define SDMA7_GPU_IOV_VIOLATION_LOG__VF_MASK                                                                  0x00200000L
>+#define SDMA7_GPU_IOV_VIOLATION_LOG__VFID_MASK                                                                0x03C00000L
>+//SDMA7_ULV_CNTL
>+#define SDMA7_ULV_CNTL__HYSTERESIS__SHIFT                                                                     0x0
>+#define SDMA7_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT                                                              0x1b
>+#define SDMA7_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT                                                               0x1c
>+#define SDMA7_ULV_CNTL__ENTER_ULV_INT__SHIFT                                                                  0x1d
>+#define SDMA7_ULV_CNTL__EXIT_ULV_INT__SHIFT                                                                   0x1e
>+#define SDMA7_ULV_CNTL__ULV_STATUS__SHIFT                                                                     0x1f
>+#define SDMA7_ULV_CNTL__HYSTERESIS_MASK                                                                       0x0000001FL
>+#define SDMA7_ULV_CNTL__ENTER_ULV_INT_CLR_MASK                                                                0x08000000L
>+#define SDMA7_ULV_CNTL__EXIT_ULV_INT_CLR_MASK                                                                 0x10000000L
>+#define SDMA7_ULV_CNTL__ENTER_ULV_INT_MASK                                                                    0x20000000L
>+#define SDMA7_ULV_CNTL__EXIT_ULV_INT_MASK                                                                     0x40000000L
>+#define SDMA7_ULV_CNTL__ULV_STATUS_MASK                                                                       0x80000000L
>+//SDMA7_EA_DBIT_ADDR_DATA
>+#define SDMA7_EA_DBIT_ADDR_DATA__VALUE__SHIFT                                                                 0x0
>+#define SDMA7_EA_DBIT_ADDR_DATA__VALUE_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_EA_DBIT_ADDR_INDEX
>+#define SDMA7_EA_DBIT_ADDR_INDEX__VALUE__SHIFT                                                                0x0
>+#define SDMA7_EA_DBIT_ADDR_INDEX__VALUE_MASK                                                                  0x00000007L
>+//SDMA7_GPU_IOV_VIOLATION_LOG2
>+#define SDMA7_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT                                                     0x0
>+#define SDMA7_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK                                                       0x000000FFL
>+//SDMA7_GFX_RB_CNTL
>+#define SDMA7_GFX_RB_CNTL__RB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA7_GFX_RB_CNTL__RB_SIZE__SHIFT                                                                     0x1
>+#define SDMA7_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                              0x9
>+#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                       0xc
>+#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                  0xd
>+#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                        0x10
>+#define SDMA7_GFX_RB_CNTL__RB_PRIV__SHIFT                                                                     0x17
>+#define SDMA7_GFX_RB_CNTL__RB_VMID__SHIFT                                                                     0x18
>+#define SDMA7_GFX_RB_CNTL__RB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA7_GFX_RB_CNTL__RB_SIZE_MASK                                                                       0x0000003EL
>+#define SDMA7_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK                                                                0x00000200L
>+#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                         0x00001000L
>+#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                    0x00002000L
>+#define SDMA7_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                          0x001F0000L
>+#define SDMA7_GFX_RB_CNTL__RB_PRIV_MASK                                                                       0x00800000L
>+#define SDMA7_GFX_RB_CNTL__RB_VMID_MASK                                                                       0x0F000000L
>+//SDMA7_GFX_RB_BASE
>+#define SDMA7_GFX_RB_BASE__ADDR__SHIFT                                                                        0x0
>+#define SDMA7_GFX_RB_BASE__ADDR_MASK                                                                          0xFFFFFFFFL
>+//SDMA7_GFX_RB_BASE_HI
>+#define SDMA7_GFX_RB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA7_GFX_RB_BASE_HI__ADDR_MASK                                                                       0x00FFFFFFL
>+//SDMA7_GFX_RB_RPTR
>+#define SDMA7_GFX_RB_RPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA7_GFX_RB_RPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA7_GFX_RB_RPTR_HI
>+#define SDMA7_GFX_RB_RPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA7_GFX_RB_RPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA7_GFX_RB_WPTR
>+#define SDMA7_GFX_RB_WPTR__OFFSET__SHIFT                                                                      0x0
>+#define SDMA7_GFX_RB_WPTR__OFFSET_MASK                                                                        0xFFFFFFFFL
>+//SDMA7_GFX_RB_WPTR_HI
>+#define SDMA7_GFX_RB_WPTR_HI__OFFSET__SHIFT                                                                   0x0
>+#define SDMA7_GFX_RB_WPTR_HI__OFFSET_MASK                                                                     0xFFFFFFFFL
>+//SDMA7_GFX_RB_WPTR_POLL_CNTL
>+#define SDMA7_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                            0x0
>+#define SDMA7_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                       0x1
>+#define SDMA7_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                   0x2
>+#define SDMA7_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
>+#define SDMA7_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                   0x10
>+#define SDMA7_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                              0x00000001L
>+#define SDMA7_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                         0x00000002L
>+#define SDMA7_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                     0x00000004L
>+#define SDMA7_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                           0x0000FFF0L
>+#define SDMA7_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                     0xFFFF0000L
>+//SDMA7_GFX_RB_RPTR_ADDR_HI
>+#define SDMA7_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                                0x0
>+#define SDMA7_GFX_RB_RPTR_ADDR_HI__ADDR_MASK                                                                  0xFFFFFFFFL
>+//SDMA7_GFX_RB_RPTR_ADDR_LO
>+#define SDMA7_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                        0x0
>+#define SDMA7_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                                0x2
>+#define SDMA7_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                          0x00000001L
>+#define SDMA7_GFX_RB_RPTR_ADDR_LO__ADDR_MASK                                                                  0xFFFFFFFCL
>+//SDMA7_GFX_IB_CNTL
>+#define SDMA7_GFX_IB_CNTL__IB_ENABLE__SHIFT                                                                   0x0
>+#define SDMA7_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                              0x4
>+#define SDMA7_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                            0x8
>+#define SDMA7_GFX_IB_CNTL__CMD_VMID__SHIFT                                                                    0x10
>+#define SDMA7_GFX_IB_CNTL__IB_ENABLE_MASK                                                                     0x00000001L
>+#define SDMA7_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK                                                                0x00000010L
>+#define SDMA7_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                              0x00000100L
>+#define SDMA7_GFX_IB_CNTL__CMD_VMID_MASK                                                                      0x000F0000L
>+//SDMA7_GFX_IB_RPTR
>+#define SDMA7_GFX_IB_RPTR__OFFSET__SHIFT                                                                      0x2
>+#define SDMA7_GFX_IB_RPTR__OFFSET_MASK                                                                        0x003FFFFCL
>+//SDMA7_GFX_IB_OFFSET
>+#define SDMA7_GFX_IB_OFFSET__OFFSET__SHIFT                                                                    0x2
>+#define SDMA7_GFX_IB_OFFSET__OFFSET_MASK                                                                      0x003FFFFCL
>+//SDMA7_GFX_IB_BASE_LO
>+#define SDMA7_GFX_IB_BASE_LO__ADDR__SHIFT                                                                     0x5
>+#define SDMA7_GFX_IB_BASE_LO__ADDR_MASK                                                                       0xFFFFFFE0L
>+//SDMA7_GFX_IB_BASE_HI
>+#define SDMA7_GFX_IB_BASE_HI__ADDR__SHIFT                                                                     0x0
>+#define SDMA7_GFX_IB_BASE_HI__ADDR_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_GFX_IB_SIZE
>+#define SDMA7_GFX_IB_SIZE__SIZE__SHIFT                                                                        0x0
>+#define SDMA7_GFX_IB_SIZE__SIZE_MASK                                                                          0x000FFFFFL
>+//SDMA7_GFX_SKIP_CNTL
>+#define SDMA7_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT                                                                0x0
>+#define SDMA7_GFX_SKIP_CNTL__SKIP_COUNT_MASK                                                                  0x000FFFFFL
>+//SDMA7_GFX_CONTEXT_STATUS
>+#define SDMA7_GFX_CONTEXT_STATUS__SELECTED__SHIFT                                                             0x0
>+#define SDMA7_GFX_CONTEXT_STATUS__IDLE__SHIFT                                                                 0x2
>+#define SDMA7_GFX_CONTEXT_STATUS__EXPIRED__SHIFT                                                              0x3
>+#define SDMA7_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT                                                            0x4
>+#define SDMA7_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                           0x7
>+#define SDMA7_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                          0x8
>+#define SDMA7_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT                                                            0x9
>+#define SDMA7_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                      0xa
>+#define SDMA7_GFX_CONTEXT_STATUS__SELECTED_MASK                                                               0x00000001L
>+#define SDMA7_GFX_CONTEXT_STATUS__IDLE_MASK                                                                   0x00000004L
>+#define SDMA7_GFX_CONTEXT_STATUS__EXPIRED_MASK                                                                0x00000008L
>+#define SDMA7_GFX_CONTEXT_STATUS__EXCEPTION_MASK                                                              0x00000070L
>+#define SDMA7_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                             0x00000080L
>+#define SDMA7_GFX_CONTEXT_STATUS__CTXSW_READY_MASK                                                            0x00000100L
>+#define SDMA7_GFX_CONTEXT_STATUS__PREEMPTED_MASK                                                              0x00000200L
>+#define SDMA7_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                        0x00000400L
>+//SDMA7_GFX_DOORBELL
>+#define SDMA7_GFX_DOORBELL__ENABLE__SHIFT                                                                     0x1c
>+#define SDMA7_GFX_DOORBELL__CAPTURED__SHIFT                                                                   0x1e
>+#define SDMA7_GFX_DOORBELL__ENABLE_MASK                                                                       0x10000000L
>+#define SDMA7_GFX_DOORBELL__CAPTURED_MASK                                                                     0x40000000L
>+//SDMA7_GFX_CONTEXT_CNTL
>+#define SDMA7_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT                                                             0x10
>+#define SDMA7_GFX_CONTEXT_CNTL__RESUME_CTX_MASK                                                               0x00010000L
>+//SDMA7_GFX_STATUS
>+#define SDMA7_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
>+#define SDMA7_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                          0x8
>+#define SDMA7_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                         0x000000FFL
>+#define SDMA7_GFX_STATUS__WPTR_UPDATE_PENDING_MASK                                                            0x00000100L
>+//SDMA7_GFX_DOORBELL_LOG
>+#define SDMA7_GFX_DOORBELL_LOG__BE_ERROR__SHIFT                                                               0x0
>+#define SDMA7_GFX_DOORBELL_LOG__DATA__SHIFT                                                                   0x2
>+#define SDMA7_GFX_DOORBELL_LOG__BE_ERROR_MASK                                                                 0x00000001L
>+#define SDMA7_GFX_DOORBELL_LOG__DATA_MASK                                                                     0xFFFFFFFCL
>+//SDMA7_GFX_WATERMARK
>+#define SDMA7_GFX_WATERMARK__RD_OUTSTANDING__SHIFT                                                            0x0
>+#define SDMA7_GFX_WATERMARK__WR_OUTSTANDING__SHIFT                                                            0x10
>+#define SDMA7_GFX_WATERMARK__RD_OUTSTANDING_MASK                                                              0x00000FFFL
>+#define SDMA7_GFX_WATERMARK__WR_OUTSTANDING_MASK                                                              0x03FF0000L
>+//SDMA7_GFX_DOORBELL_OFFSET
>+#define SDMA7_GFX_DOORBELL_OFFSET__OFFSET__SHIFT                                                              0x2
>+#define SDMA7_GFX_DOORBELL_OFFSET__OFFSET_MASK                                                                0x0FFFFFFCL
>+//SDMA7_GFX_CSA_ADDR_LO
>+#define SDMA7_GFX_CSA_ADDR_LO__ADDR__SHIFT                                                                    0x2
>+#define SDMA7_GFX_CSA_ADDR_LO__ADDR_MASK                                                                      0xFFFFFFFCL
>+//SDMA7_GFX_CSA_ADDR_HI
>+#define SDMA7_GFX_CSA_ADDR_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_GFX_CSA_ADDR_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_GFX_IB_SUB_REMAIN
>+#define SDMA7_GFX_IB_SUB_REMAIN__SIZE__SHIFT                                                                  0x0
>+#define SDMA7_GFX_IB_SUB_REMAIN__SIZE_MASK                                                                    0x000FFFFFL
>+//SDMA7_GFX_PREEMPT
>+#define SDMA7_GFX_PREEMPT__IB_PREEMPT__SHIFT                                                                  0x0
>+#define SDMA7_GFX_PREEMPT__IB_PREEMPT_MASK                                                                    0x00000001L
>+//SDMA7_GFX_DUMMY_REG
>+#define SDMA7_GFX_DUMMY_REG__DUMMY__SHIFT                                                                     0x0
>+#define SDMA7_GFX_DUMMY_REG__DUMMY_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_GFX_RB_WPTR_POLL_ADDR_HI
>+#define SDMA7_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
>+#define SDMA7_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                             0xFFFFFFFFL
>+//SDMA7_GFX_RB_WPTR_POLL_ADDR_LO
>+#define SDMA7_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                           0x2
>+#define SDMA7_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
>+//SDMA7_GFX_RB_AQL_CNTL
>+#define SDMA7_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                              0x0
>+#define SDMA7_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                         0x1
>+#define SDMA7_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                             0x8
>+#define SDMA7_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK                                                                0x00000001L
>+#define SDMA7_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                           0x000000FEL
>+#define SDMA7_GFX_RB_AQL_CNTL__PACKET_STEP_MASK                                                               0x0000FF00L
>+//SDMA7_GFX_MINOR_PTR_UPDATE
>+#define SDMA7_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                             0x0
>+#define SDMA7_GFX_MINOR_PTR_UPDATE__ENABLE_MASK                                                               0x00000001L
>+//SDMA7_GFX_MIDCMD_DATA0
>+#define SDMA7_GFX_MIDCMD_DATA0__DATA0__SHIFT                                                                  0x0
>+#define SDMA7_GFX_MIDCMD_DATA0__DATA0_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_GFX_MIDCMD_DATA1
>+#define SDMA7_GFX_MIDCMD_DATA1__DATA1__SHIFT                                                                  0x0
>+#define SDMA7_GFX_MIDCMD_DATA1__DATA1_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_GFX_MIDCMD_DATA2
>+#define SDMA7_GFX_MIDCMD_DATA2__DATA2__SHIFT                                                                  0x0
>+#define SDMA7_GFX_MIDCMD_DATA2__DATA2_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_GFX_MIDCMD_DATA3
>+#define SDMA7_GFX_MIDCMD_DATA3__DATA3__SHIFT                                                                  0x0
>+#define SDMA7_GFX_MIDCMD_DATA3__DATA3_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_GFX_MIDCMD_DATA4
>+#define SDMA7_GFX_MIDCMD_DATA4__DATA4__SHIFT                                                                  0x0
>+#define SDMA7_GFX_MIDCMD_DATA4__DATA4_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_GFX_MIDCMD_DATA5
>+#define SDMA7_GFX_MIDCMD_DATA5__DATA5__SHIFT                                                                  0x0
>+#define SDMA7_GFX_MIDCMD_DATA5__DATA5_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_GFX_MIDCMD_DATA6
>+#define SDMA7_GFX_MIDCMD_DATA6__DATA6__SHIFT                                                                  0x0
>+#define SDMA7_GFX_MIDCMD_DATA6__DATA6_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_GFX_MIDCMD_DATA7
>+#define SDMA7_GFX_MIDCMD_DATA7__DATA7__SHIFT                                                                  0x0
>+#define SDMA7_GFX_MIDCMD_DATA7__DATA7_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_GFX_MIDCMD_DATA8
>+#define SDMA7_GFX_MIDCMD_DATA8__DATA8__SHIFT                                                                  0x0
>+#define SDMA7_GFX_MIDCMD_DATA8__DATA8_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_GFX_MIDCMD_CNTL
>+#define SDMA7_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT                                                              0x0
>+#define SDMA7_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT                                                               0x1
>+#define SDMA7_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
>+#define SDMA7_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                           0x8
>+#define SDMA7_GFX_MIDCMD_CNTL__DATA_VALID_MASK                                                                0x00000001L
>+#define SDMA7_GFX_MIDCMD_CNTL__COPY_MODE_MASK                                                                 0x00000002L
>+#define SDMA7_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK                                                               0x000000F0L
>+#define SDMA7_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                             0x00000100L
>+//SDMA7_PAGE_RB_CNTL
>+#define SDMA7_PAGE_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_PAGE_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA7_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA7_PAGE_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA7_PAGE_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA7_PAGE_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_PAGE_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA7_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA7_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA7_PAGE_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA7_PAGE_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA7_PAGE_RB_BASE
>+#define SDMA7_PAGE_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA7_PAGE_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA7_PAGE_RB_BASE_HI
>+#define SDMA7_PAGE_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_PAGE_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA7_PAGE_RB_RPTR
>+#define SDMA7_PAGE_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_PAGE_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_PAGE_RB_RPTR_HI
>+#define SDMA7_PAGE_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_PAGE_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_PAGE_RB_WPTR
>+#define SDMA7_PAGE_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_PAGE_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_PAGE_RB_WPTR_HI
>+#define SDMA7_PAGE_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_PAGE_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_PAGE_RB_WPTR_POLL_CNTL
>+#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA7_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA7_PAGE_RB_RPTR_ADDR_HI
>+#define SDMA7_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA7_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA7_PAGE_RB_RPTR_ADDR_LO
>+#define SDMA7_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA7_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA7_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA7_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA7_PAGE_IB_CNTL
>+#define SDMA7_PAGE_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA7_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA7_PAGE_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA7_PAGE_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA7_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA7_PAGE_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA7_PAGE_IB_RPTR
>+#define SDMA7_PAGE_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA7_PAGE_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA7_PAGE_IB_OFFSET
>+#define SDMA7_PAGE_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA7_PAGE_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA7_PAGE_IB_BASE_LO
>+#define SDMA7_PAGE_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA7_PAGE_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA7_PAGE_IB_BASE_HI
>+#define SDMA7_PAGE_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_PAGE_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_PAGE_IB_SIZE
>+#define SDMA7_PAGE_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA7_PAGE_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA7_PAGE_SKIP_CNTL
>+#define SDMA7_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA7_PAGE_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA7_PAGE_CONTEXT_STATUS
>+#define SDMA7_PAGE_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA7_PAGE_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA7_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA7_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA7_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA7_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA7_PAGE_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA7_PAGE_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA7_PAGE_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA7_PAGE_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA7_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA7_PAGE_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA7_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA7_PAGE_DOORBELL
>+#define SDMA7_PAGE_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA7_PAGE_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA7_PAGE_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA7_PAGE_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA7_PAGE_STATUS
>+#define SDMA7_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA7_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA7_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA7_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA7_PAGE_DOORBELL_LOG
>+#define SDMA7_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA7_PAGE_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA7_PAGE_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA7_PAGE_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA7_PAGE_WATERMARK
>+#define SDMA7_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA7_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA7_PAGE_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA7_PAGE_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA7_PAGE_DOORBELL_OFFSET
>+#define SDMA7_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA7_PAGE_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA7_PAGE_CSA_ADDR_LO
>+#define SDMA7_PAGE_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA7_PAGE_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA7_PAGE_CSA_ADDR_HI
>+#define SDMA7_PAGE_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA7_PAGE_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA7_PAGE_IB_SUB_REMAIN
>+#define SDMA7_PAGE_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA7_PAGE_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA7_PAGE_PREEMPT
>+#define SDMA7_PAGE_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA7_PAGE_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA7_PAGE_DUMMY_REG
>+#define SDMA7_PAGE_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA7_PAGE_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_PAGE_RB_WPTR_POLL_ADDR_HI
>+#define SDMA7_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA7_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA7_PAGE_RB_WPTR_POLL_ADDR_LO
>+#define SDMA7_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA7_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA7_PAGE_RB_AQL_CNTL
>+#define SDMA7_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA7_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA7_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA7_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA7_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA7_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA7_PAGE_MINOR_PTR_UPDATE
>+#define SDMA7_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA7_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA7_PAGE_MIDCMD_DATA0
>+#define SDMA7_PAGE_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA7_PAGE_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_PAGE_MIDCMD_DATA1
>+#define SDMA7_PAGE_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA7_PAGE_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_PAGE_MIDCMD_DATA2
>+#define SDMA7_PAGE_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA7_PAGE_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_PAGE_MIDCMD_DATA3
>+#define SDMA7_PAGE_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA7_PAGE_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_PAGE_MIDCMD_DATA4
>+#define SDMA7_PAGE_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA7_PAGE_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_PAGE_MIDCMD_DATA5
>+#define SDMA7_PAGE_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA7_PAGE_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_PAGE_MIDCMD_DATA6
>+#define SDMA7_PAGE_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA7_PAGE_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_PAGE_MIDCMD_DATA7
>+#define SDMA7_PAGE_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA7_PAGE_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_PAGE_MIDCMD_DATA8
>+#define SDMA7_PAGE_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA7_PAGE_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_PAGE_MIDCMD_CNTL
>+#define SDMA7_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA7_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA7_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA7_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA7_PAGE_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA7_PAGE_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA7_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA7_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA7_RLC0_RB_CNTL
>+#define SDMA7_RLC0_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC0_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA7_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA7_RLC0_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA7_RLC0_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA7_RLC0_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC0_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA7_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA7_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA7_RLC0_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA7_RLC0_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA7_RLC0_RB_BASE
>+#define SDMA7_RLC0_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA7_RLC0_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA7_RLC0_RB_BASE_HI
>+#define SDMA7_RLC0_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC0_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA7_RLC0_RB_RPTR
>+#define SDMA7_RLC0_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC0_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC0_RB_RPTR_HI
>+#define SDMA7_RLC0_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC0_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC0_RB_WPTR
>+#define SDMA7_RLC0_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC0_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC0_RB_WPTR_HI
>+#define SDMA7_RLC0_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC0_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC0_RB_WPTR_POLL_CNTL
>+#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA7_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA7_RLC0_RB_RPTR_ADDR_HI
>+#define SDMA7_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA7_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA7_RLC0_RB_RPTR_ADDR_LO
>+#define SDMA7_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA7_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA7_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA7_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA7_RLC0_IB_CNTL
>+#define SDMA7_RLC0_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA7_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA7_RLC0_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA7_RLC0_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA7_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA7_RLC0_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA7_RLC0_IB_RPTR
>+#define SDMA7_RLC0_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA7_RLC0_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA7_RLC0_IB_OFFSET
>+#define SDMA7_RLC0_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA7_RLC0_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA7_RLC0_IB_BASE_LO
>+#define SDMA7_RLC0_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA7_RLC0_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA7_RLC0_IB_BASE_HI
>+#define SDMA7_RLC0_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC0_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC0_IB_SIZE
>+#define SDMA7_RLC0_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA7_RLC0_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA7_RLC0_SKIP_CNTL
>+#define SDMA7_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA7_RLC0_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA7_RLC0_CONTEXT_STATUS
>+#define SDMA7_RLC0_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA7_RLC0_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA7_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA7_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA7_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA7_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA7_RLC0_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA7_RLC0_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA7_RLC0_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA7_RLC0_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA7_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA7_RLC0_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA7_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA7_RLC0_DOORBELL
>+#define SDMA7_RLC0_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA7_RLC0_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA7_RLC0_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA7_RLC0_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA7_RLC0_STATUS
>+#define SDMA7_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA7_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA7_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA7_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA7_RLC0_DOORBELL_LOG
>+#define SDMA7_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA7_RLC0_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA7_RLC0_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA7_RLC0_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA7_RLC0_WATERMARK
>+#define SDMA7_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA7_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA7_RLC0_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA7_RLC0_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA7_RLC0_DOORBELL_OFFSET
>+#define SDMA7_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA7_RLC0_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA7_RLC0_CSA_ADDR_LO
>+#define SDMA7_RLC0_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA7_RLC0_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA7_RLC0_CSA_ADDR_HI
>+#define SDMA7_RLC0_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA7_RLC0_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA7_RLC0_IB_SUB_REMAIN
>+#define SDMA7_RLC0_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA7_RLC0_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA7_RLC0_PREEMPT
>+#define SDMA7_RLC0_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA7_RLC0_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA7_RLC0_DUMMY_REG
>+#define SDMA7_RLC0_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA7_RLC0_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC0_RB_WPTR_POLL_ADDR_HI
>+#define SDMA7_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA7_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA7_RLC0_RB_WPTR_POLL_ADDR_LO
>+#define SDMA7_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA7_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA7_RLC0_RB_AQL_CNTL
>+#define SDMA7_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA7_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA7_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA7_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA7_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA7_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA7_RLC0_MINOR_PTR_UPDATE
>+#define SDMA7_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA7_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA7_RLC0_MIDCMD_DATA0
>+#define SDMA7_RLC0_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA7_RLC0_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC0_MIDCMD_DATA1
>+#define SDMA7_RLC0_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA7_RLC0_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC0_MIDCMD_DATA2
>+#define SDMA7_RLC0_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA7_RLC0_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC0_MIDCMD_DATA3
>+#define SDMA7_RLC0_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA7_RLC0_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC0_MIDCMD_DATA4
>+#define SDMA7_RLC0_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA7_RLC0_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC0_MIDCMD_DATA5
>+#define SDMA7_RLC0_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA7_RLC0_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC0_MIDCMD_DATA6
>+#define SDMA7_RLC0_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA7_RLC0_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC0_MIDCMD_DATA7
>+#define SDMA7_RLC0_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA7_RLC0_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC0_MIDCMD_DATA8
>+#define SDMA7_RLC0_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA7_RLC0_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC0_MIDCMD_CNTL
>+#define SDMA7_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA7_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA7_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA7_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA7_RLC0_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA7_RLC0_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA7_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA7_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA7_RLC1_RB_CNTL
>+#define SDMA7_RLC1_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC1_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA7_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA7_RLC1_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA7_RLC1_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA7_RLC1_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC1_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA7_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA7_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA7_RLC1_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA7_RLC1_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA7_RLC1_RB_BASE
>+#define SDMA7_RLC1_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA7_RLC1_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA7_RLC1_RB_BASE_HI
>+#define SDMA7_RLC1_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC1_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA7_RLC1_RB_RPTR
>+#define SDMA7_RLC1_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC1_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC1_RB_RPTR_HI
>+#define SDMA7_RLC1_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC1_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC1_RB_WPTR
>+#define SDMA7_RLC1_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC1_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC1_RB_WPTR_HI
>+#define SDMA7_RLC1_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC1_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC1_RB_WPTR_POLL_CNTL
>+#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA7_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA7_RLC1_RB_RPTR_ADDR_HI
>+#define SDMA7_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA7_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA7_RLC1_RB_RPTR_ADDR_LO
>+#define SDMA7_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA7_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA7_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA7_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA7_RLC1_IB_CNTL
>+#define SDMA7_RLC1_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA7_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA7_RLC1_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA7_RLC1_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA7_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA7_RLC1_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA7_RLC1_IB_RPTR
>+#define SDMA7_RLC1_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA7_RLC1_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA7_RLC1_IB_OFFSET
>+#define SDMA7_RLC1_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA7_RLC1_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA7_RLC1_IB_BASE_LO
>+#define SDMA7_RLC1_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA7_RLC1_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA7_RLC1_IB_BASE_HI
>+#define SDMA7_RLC1_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC1_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC1_IB_SIZE
>+#define SDMA7_RLC1_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA7_RLC1_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA7_RLC1_SKIP_CNTL
>+#define SDMA7_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA7_RLC1_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA7_RLC1_CONTEXT_STATUS
>+#define SDMA7_RLC1_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA7_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA7_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA7_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA7_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA7_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA7_RLC1_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA7_RLC1_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA7_RLC1_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA7_RLC1_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA7_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA7_RLC1_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA7_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA7_RLC1_DOORBELL
>+#define SDMA7_RLC1_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA7_RLC1_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA7_RLC1_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA7_RLC1_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA7_RLC1_STATUS
>+#define SDMA7_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA7_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA7_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA7_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA7_RLC1_DOORBELL_LOG
>+#define SDMA7_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA7_RLC1_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA7_RLC1_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA7_RLC1_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA7_RLC1_WATERMARK
>+#define SDMA7_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA7_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA7_RLC1_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA7_RLC1_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA7_RLC1_DOORBELL_OFFSET
>+#define SDMA7_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA7_RLC1_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA7_RLC1_CSA_ADDR_LO
>+#define SDMA7_RLC1_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA7_RLC1_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA7_RLC1_CSA_ADDR_HI
>+#define SDMA7_RLC1_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA7_RLC1_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA7_RLC1_IB_SUB_REMAIN
>+#define SDMA7_RLC1_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA7_RLC1_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA7_RLC1_PREEMPT
>+#define SDMA7_RLC1_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA7_RLC1_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA7_RLC1_DUMMY_REG
>+#define SDMA7_RLC1_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA7_RLC1_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC1_RB_WPTR_POLL_ADDR_HI
>+#define SDMA7_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA7_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA7_RLC1_RB_WPTR_POLL_ADDR_LO
>+#define SDMA7_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA7_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA7_RLC1_RB_AQL_CNTL
>+#define SDMA7_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA7_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA7_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA7_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA7_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA7_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA7_RLC1_MINOR_PTR_UPDATE
>+#define SDMA7_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA7_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA7_RLC1_MIDCMD_DATA0
>+#define SDMA7_RLC1_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA7_RLC1_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC1_MIDCMD_DATA1
>+#define SDMA7_RLC1_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA7_RLC1_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC1_MIDCMD_DATA2
>+#define SDMA7_RLC1_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA7_RLC1_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC1_MIDCMD_DATA3
>+#define SDMA7_RLC1_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA7_RLC1_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC1_MIDCMD_DATA4
>+#define SDMA7_RLC1_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA7_RLC1_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC1_MIDCMD_DATA5
>+#define SDMA7_RLC1_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA7_RLC1_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC1_MIDCMD_DATA6
>+#define SDMA7_RLC1_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA7_RLC1_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC1_MIDCMD_DATA7
>+#define SDMA7_RLC1_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA7_RLC1_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC1_MIDCMD_DATA8
>+#define SDMA7_RLC1_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA7_RLC1_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC1_MIDCMD_CNTL
>+#define SDMA7_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA7_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA7_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA7_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA7_RLC1_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA7_RLC1_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA7_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA7_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA7_RLC2_RB_CNTL
>+#define SDMA7_RLC2_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC2_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA7_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA7_RLC2_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA7_RLC2_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA7_RLC2_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC2_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA7_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA7_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA7_RLC2_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA7_RLC2_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA7_RLC2_RB_BASE
>+#define SDMA7_RLC2_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA7_RLC2_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA7_RLC2_RB_BASE_HI
>+#define SDMA7_RLC2_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC2_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA7_RLC2_RB_RPTR
>+#define SDMA7_RLC2_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC2_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC2_RB_RPTR_HI
>+#define SDMA7_RLC2_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC2_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC2_RB_WPTR
>+#define SDMA7_RLC2_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC2_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC2_RB_WPTR_HI
>+#define SDMA7_RLC2_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC2_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC2_RB_WPTR_POLL_CNTL
>+#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA7_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA7_RLC2_RB_RPTR_ADDR_HI
>+#define SDMA7_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA7_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA7_RLC2_RB_RPTR_ADDR_LO
>+#define SDMA7_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA7_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA7_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA7_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA7_RLC2_IB_CNTL
>+#define SDMA7_RLC2_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA7_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA7_RLC2_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA7_RLC2_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA7_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA7_RLC2_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA7_RLC2_IB_RPTR
>+#define SDMA7_RLC2_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA7_RLC2_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA7_RLC2_IB_OFFSET
>+#define SDMA7_RLC2_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA7_RLC2_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA7_RLC2_IB_BASE_LO
>+#define SDMA7_RLC2_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA7_RLC2_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA7_RLC2_IB_BASE_HI
>+#define SDMA7_RLC2_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC2_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC2_IB_SIZE
>+#define SDMA7_RLC2_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA7_RLC2_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA7_RLC2_SKIP_CNTL
>+#define SDMA7_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA7_RLC2_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA7_RLC2_CONTEXT_STATUS
>+#define SDMA7_RLC2_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA7_RLC2_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA7_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA7_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA7_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA7_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA7_RLC2_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA7_RLC2_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA7_RLC2_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA7_RLC2_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA7_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA7_RLC2_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA7_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA7_RLC2_DOORBELL
>+#define SDMA7_RLC2_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA7_RLC2_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA7_RLC2_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA7_RLC2_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA7_RLC2_STATUS
>+#define SDMA7_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA7_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA7_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA7_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA7_RLC2_DOORBELL_LOG
>+#define SDMA7_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA7_RLC2_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA7_RLC2_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA7_RLC2_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA7_RLC2_WATERMARK
>+#define SDMA7_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA7_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA7_RLC2_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA7_RLC2_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA7_RLC2_DOORBELL_OFFSET
>+#define SDMA7_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA7_RLC2_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA7_RLC2_CSA_ADDR_LO
>+#define SDMA7_RLC2_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA7_RLC2_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA7_RLC2_CSA_ADDR_HI
>+#define SDMA7_RLC2_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA7_RLC2_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA7_RLC2_IB_SUB_REMAIN
>+#define SDMA7_RLC2_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA7_RLC2_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA7_RLC2_PREEMPT
>+#define SDMA7_RLC2_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA7_RLC2_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA7_RLC2_DUMMY_REG
>+#define SDMA7_RLC2_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA7_RLC2_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC2_RB_WPTR_POLL_ADDR_HI
>+#define SDMA7_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA7_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA7_RLC2_RB_WPTR_POLL_ADDR_LO
>+#define SDMA7_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA7_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA7_RLC2_RB_AQL_CNTL
>+#define SDMA7_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA7_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA7_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA7_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA7_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA7_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA7_RLC2_MINOR_PTR_UPDATE
>+#define SDMA7_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA7_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA7_RLC2_MIDCMD_DATA0
>+#define SDMA7_RLC2_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA7_RLC2_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC2_MIDCMD_DATA1
>+#define SDMA7_RLC2_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA7_RLC2_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC2_MIDCMD_DATA2
>+#define SDMA7_RLC2_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA7_RLC2_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC2_MIDCMD_DATA3
>+#define SDMA7_RLC2_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA7_RLC2_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC2_MIDCMD_DATA4
>+#define SDMA7_RLC2_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA7_RLC2_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC2_MIDCMD_DATA5
>+#define SDMA7_RLC2_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA7_RLC2_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC2_MIDCMD_DATA6
>+#define SDMA7_RLC2_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA7_RLC2_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC2_MIDCMD_DATA7
>+#define SDMA7_RLC2_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA7_RLC2_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC2_MIDCMD_DATA8
>+#define SDMA7_RLC2_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA7_RLC2_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC2_MIDCMD_CNTL
>+#define SDMA7_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA7_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA7_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA7_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA7_RLC2_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA7_RLC2_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA7_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA7_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA7_RLC3_RB_CNTL
>+#define SDMA7_RLC3_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC3_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA7_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA7_RLC3_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA7_RLC3_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA7_RLC3_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC3_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA7_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA7_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA7_RLC3_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA7_RLC3_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA7_RLC3_RB_BASE
>+#define SDMA7_RLC3_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA7_RLC3_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA7_RLC3_RB_BASE_HI
>+#define SDMA7_RLC3_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC3_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA7_RLC3_RB_RPTR
>+#define SDMA7_RLC3_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC3_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC3_RB_RPTR_HI
>+#define SDMA7_RLC3_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC3_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC3_RB_WPTR
>+#define SDMA7_RLC3_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC3_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC3_RB_WPTR_HI
>+#define SDMA7_RLC3_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC3_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC3_RB_WPTR_POLL_CNTL
>+#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA7_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA7_RLC3_RB_RPTR_ADDR_HI
>+#define SDMA7_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA7_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA7_RLC3_RB_RPTR_ADDR_LO
>+#define SDMA7_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA7_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA7_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA7_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA7_RLC3_IB_CNTL
>+#define SDMA7_RLC3_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA7_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA7_RLC3_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA7_RLC3_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA7_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA7_RLC3_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA7_RLC3_IB_RPTR
>+#define SDMA7_RLC3_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA7_RLC3_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA7_RLC3_IB_OFFSET
>+#define SDMA7_RLC3_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA7_RLC3_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA7_RLC3_IB_BASE_LO
>+#define SDMA7_RLC3_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA7_RLC3_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA7_RLC3_IB_BASE_HI
>+#define SDMA7_RLC3_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC3_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC3_IB_SIZE
>+#define SDMA7_RLC3_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA7_RLC3_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA7_RLC3_SKIP_CNTL
>+#define SDMA7_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA7_RLC3_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA7_RLC3_CONTEXT_STATUS
>+#define SDMA7_RLC3_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA7_RLC3_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA7_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA7_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA7_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA7_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA7_RLC3_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA7_RLC3_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA7_RLC3_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA7_RLC3_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA7_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA7_RLC3_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA7_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA7_RLC3_DOORBELL
>+#define SDMA7_RLC3_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA7_RLC3_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA7_RLC3_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA7_RLC3_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA7_RLC3_STATUS
>+#define SDMA7_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA7_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA7_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA7_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA7_RLC3_DOORBELL_LOG
>+#define SDMA7_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA7_RLC3_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA7_RLC3_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA7_RLC3_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA7_RLC3_WATERMARK
>+#define SDMA7_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA7_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA7_RLC3_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA7_RLC3_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA7_RLC3_DOORBELL_OFFSET
>+#define SDMA7_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA7_RLC3_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA7_RLC3_CSA_ADDR_LO
>+#define SDMA7_RLC3_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA7_RLC3_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA7_RLC3_CSA_ADDR_HI
>+#define SDMA7_RLC3_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA7_RLC3_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA7_RLC3_IB_SUB_REMAIN
>+#define SDMA7_RLC3_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA7_RLC3_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA7_RLC3_PREEMPT
>+#define SDMA7_RLC3_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA7_RLC3_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA7_RLC3_DUMMY_REG
>+#define SDMA7_RLC3_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA7_RLC3_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC3_RB_WPTR_POLL_ADDR_HI
>+#define SDMA7_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA7_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA7_RLC3_RB_WPTR_POLL_ADDR_LO
>+#define SDMA7_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA7_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA7_RLC3_RB_AQL_CNTL
>+#define SDMA7_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA7_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA7_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA7_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA7_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA7_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA7_RLC3_MINOR_PTR_UPDATE
>+#define SDMA7_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA7_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA7_RLC3_MIDCMD_DATA0
>+#define SDMA7_RLC3_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA7_RLC3_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC3_MIDCMD_DATA1
>+#define SDMA7_RLC3_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA7_RLC3_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC3_MIDCMD_DATA2
>+#define SDMA7_RLC3_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA7_RLC3_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC3_MIDCMD_DATA3
>+#define SDMA7_RLC3_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA7_RLC3_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC3_MIDCMD_DATA4
>+#define SDMA7_RLC3_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA7_RLC3_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC3_MIDCMD_DATA5
>+#define SDMA7_RLC3_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA7_RLC3_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC3_MIDCMD_DATA6
>+#define SDMA7_RLC3_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA7_RLC3_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC3_MIDCMD_DATA7
>+#define SDMA7_RLC3_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA7_RLC3_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC3_MIDCMD_DATA8
>+#define SDMA7_RLC3_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA7_RLC3_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC3_MIDCMD_CNTL
>+#define SDMA7_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA7_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA7_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA7_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA7_RLC3_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA7_RLC3_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA7_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA7_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA7_RLC4_RB_CNTL
>+#define SDMA7_RLC4_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC4_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA7_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA7_RLC4_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA7_RLC4_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA7_RLC4_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC4_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA7_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA7_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA7_RLC4_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA7_RLC4_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA7_RLC4_RB_BASE
>+#define SDMA7_RLC4_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA7_RLC4_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA7_RLC4_RB_BASE_HI
>+#define SDMA7_RLC4_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC4_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA7_RLC4_RB_RPTR
>+#define SDMA7_RLC4_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC4_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC4_RB_RPTR_HI
>+#define SDMA7_RLC4_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC4_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC4_RB_WPTR
>+#define SDMA7_RLC4_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC4_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC4_RB_WPTR_HI
>+#define SDMA7_RLC4_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC4_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC4_RB_WPTR_POLL_CNTL
>+#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA7_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA7_RLC4_RB_RPTR_ADDR_HI
>+#define SDMA7_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA7_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA7_RLC4_RB_RPTR_ADDR_LO
>+#define SDMA7_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA7_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA7_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA7_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA7_RLC4_IB_CNTL
>+#define SDMA7_RLC4_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA7_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA7_RLC4_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA7_RLC4_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA7_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA7_RLC4_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA7_RLC4_IB_RPTR
>+#define SDMA7_RLC4_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA7_RLC4_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA7_RLC4_IB_OFFSET
>+#define SDMA7_RLC4_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA7_RLC4_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA7_RLC4_IB_BASE_LO
>+#define SDMA7_RLC4_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA7_RLC4_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA7_RLC4_IB_BASE_HI
>+#define SDMA7_RLC4_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC4_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC4_IB_SIZE
>+#define SDMA7_RLC4_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA7_RLC4_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA7_RLC4_SKIP_CNTL
>+#define SDMA7_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA7_RLC4_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA7_RLC4_CONTEXT_STATUS
>+#define SDMA7_RLC4_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA7_RLC4_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA7_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA7_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA7_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA7_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA7_RLC4_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA7_RLC4_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA7_RLC4_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA7_RLC4_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA7_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA7_RLC4_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA7_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA7_RLC4_DOORBELL
>+#define SDMA7_RLC4_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA7_RLC4_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA7_RLC4_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA7_RLC4_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA7_RLC4_STATUS
>+#define SDMA7_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA7_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA7_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA7_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA7_RLC4_DOORBELL_LOG
>+#define SDMA7_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA7_RLC4_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA7_RLC4_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA7_RLC4_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA7_RLC4_WATERMARK
>+#define SDMA7_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA7_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA7_RLC4_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA7_RLC4_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA7_RLC4_DOORBELL_OFFSET
>+#define SDMA7_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA7_RLC4_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA7_RLC4_CSA_ADDR_LO
>+#define SDMA7_RLC4_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA7_RLC4_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA7_RLC4_CSA_ADDR_HI
>+#define SDMA7_RLC4_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA7_RLC4_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA7_RLC4_IB_SUB_REMAIN
>+#define SDMA7_RLC4_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA7_RLC4_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA7_RLC4_PREEMPT
>+#define SDMA7_RLC4_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA7_RLC4_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA7_RLC4_DUMMY_REG
>+#define SDMA7_RLC4_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA7_RLC4_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC4_RB_WPTR_POLL_ADDR_HI
>+#define SDMA7_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA7_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA7_RLC4_RB_WPTR_POLL_ADDR_LO
>+#define SDMA7_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA7_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA7_RLC4_RB_AQL_CNTL
>+#define SDMA7_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA7_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA7_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA7_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA7_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA7_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA7_RLC4_MINOR_PTR_UPDATE
>+#define SDMA7_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA7_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA7_RLC4_MIDCMD_DATA0
>+#define SDMA7_RLC4_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA7_RLC4_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC4_MIDCMD_DATA1
>+#define SDMA7_RLC4_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA7_RLC4_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC4_MIDCMD_DATA2
>+#define SDMA7_RLC4_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA7_RLC4_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC4_MIDCMD_DATA3
>+#define SDMA7_RLC4_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA7_RLC4_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC4_MIDCMD_DATA4
>+#define SDMA7_RLC4_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA7_RLC4_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC4_MIDCMD_DATA5
>+#define SDMA7_RLC4_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA7_RLC4_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC4_MIDCMD_DATA6
>+#define SDMA7_RLC4_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA7_RLC4_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC4_MIDCMD_DATA7
>+#define SDMA7_RLC4_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA7_RLC4_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC4_MIDCMD_DATA8
>+#define SDMA7_RLC4_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA7_RLC4_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC4_MIDCMD_CNTL
>+#define SDMA7_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA7_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA7_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA7_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA7_RLC4_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA7_RLC4_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA7_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA7_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA7_RLC5_RB_CNTL
>+#define SDMA7_RLC5_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC5_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA7_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA7_RLC5_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA7_RLC5_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA7_RLC5_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC5_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA7_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA7_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA7_RLC5_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA7_RLC5_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA7_RLC5_RB_BASE
>+#define SDMA7_RLC5_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA7_RLC5_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA7_RLC5_RB_BASE_HI
>+#define SDMA7_RLC5_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC5_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA7_RLC5_RB_RPTR
>+#define SDMA7_RLC5_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC5_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC5_RB_RPTR_HI
>+#define SDMA7_RLC5_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC5_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC5_RB_WPTR
>+#define SDMA7_RLC5_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC5_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC5_RB_WPTR_HI
>+#define SDMA7_RLC5_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC5_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC5_RB_WPTR_POLL_CNTL
>+#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA7_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA7_RLC5_RB_RPTR_ADDR_HI
>+#define SDMA7_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA7_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA7_RLC5_RB_RPTR_ADDR_LO
>+#define SDMA7_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA7_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA7_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA7_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA7_RLC5_IB_CNTL
>+#define SDMA7_RLC5_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA7_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA7_RLC5_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA7_RLC5_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA7_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA7_RLC5_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA7_RLC5_IB_RPTR
>+#define SDMA7_RLC5_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA7_RLC5_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA7_RLC5_IB_OFFSET
>+#define SDMA7_RLC5_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA7_RLC5_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA7_RLC5_IB_BASE_LO
>+#define SDMA7_RLC5_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA7_RLC5_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA7_RLC5_IB_BASE_HI
>+#define SDMA7_RLC5_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC5_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC5_IB_SIZE
>+#define SDMA7_RLC5_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA7_RLC5_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA7_RLC5_SKIP_CNTL
>+#define SDMA7_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA7_RLC5_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA7_RLC5_CONTEXT_STATUS
>+#define SDMA7_RLC5_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA7_RLC5_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA7_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA7_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA7_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA7_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA7_RLC5_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA7_RLC5_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA7_RLC5_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA7_RLC5_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA7_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA7_RLC5_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA7_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA7_RLC5_DOORBELL
>+#define SDMA7_RLC5_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA7_RLC5_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA7_RLC5_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA7_RLC5_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA7_RLC5_STATUS
>+#define SDMA7_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA7_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA7_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA7_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA7_RLC5_DOORBELL_LOG
>+#define SDMA7_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA7_RLC5_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA7_RLC5_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA7_RLC5_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA7_RLC5_WATERMARK
>+#define SDMA7_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA7_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA7_RLC5_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA7_RLC5_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA7_RLC5_DOORBELL_OFFSET
>+#define SDMA7_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA7_RLC5_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA7_RLC5_CSA_ADDR_LO
>+#define SDMA7_RLC5_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA7_RLC5_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA7_RLC5_CSA_ADDR_HI
>+#define SDMA7_RLC5_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA7_RLC5_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA7_RLC5_IB_SUB_REMAIN
>+#define SDMA7_RLC5_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA7_RLC5_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA7_RLC5_PREEMPT
>+#define SDMA7_RLC5_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA7_RLC5_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA7_RLC5_DUMMY_REG
>+#define SDMA7_RLC5_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA7_RLC5_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC5_RB_WPTR_POLL_ADDR_HI
>+#define SDMA7_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA7_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA7_RLC5_RB_WPTR_POLL_ADDR_LO
>+#define SDMA7_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA7_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA7_RLC5_RB_AQL_CNTL
>+#define SDMA7_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA7_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA7_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA7_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA7_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA7_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA7_RLC5_MINOR_PTR_UPDATE
>+#define SDMA7_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA7_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA7_RLC5_MIDCMD_DATA0
>+#define SDMA7_RLC5_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA7_RLC5_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC5_MIDCMD_DATA1
>+#define SDMA7_RLC5_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA7_RLC5_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC5_MIDCMD_DATA2
>+#define SDMA7_RLC5_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA7_RLC5_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC5_MIDCMD_DATA3
>+#define SDMA7_RLC5_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA7_RLC5_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC5_MIDCMD_DATA4
>+#define SDMA7_RLC5_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA7_RLC5_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC5_MIDCMD_DATA5
>+#define SDMA7_RLC5_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA7_RLC5_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC5_MIDCMD_DATA6
>+#define SDMA7_RLC5_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA7_RLC5_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC5_MIDCMD_DATA7
>+#define SDMA7_RLC5_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA7_RLC5_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC5_MIDCMD_DATA8
>+#define SDMA7_RLC5_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA7_RLC5_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC5_MIDCMD_CNTL
>+#define SDMA7_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA7_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA7_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA7_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA7_RLC5_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA7_RLC5_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA7_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA7_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA7_RLC6_RB_CNTL
>+#define SDMA7_RLC6_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC6_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA7_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA7_RLC6_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA7_RLC6_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA7_RLC6_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC6_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA7_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA7_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA7_RLC6_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA7_RLC6_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA7_RLC6_RB_BASE
>+#define SDMA7_RLC6_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA7_RLC6_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA7_RLC6_RB_BASE_HI
>+#define SDMA7_RLC6_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC6_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA7_RLC6_RB_RPTR
>+#define SDMA7_RLC6_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC6_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC6_RB_RPTR_HI
>+#define SDMA7_RLC6_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC6_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC6_RB_WPTR
>+#define SDMA7_RLC6_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC6_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC6_RB_WPTR_HI
>+#define SDMA7_RLC6_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC6_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC6_RB_WPTR_POLL_CNTL
>+#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA7_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA7_RLC6_RB_RPTR_ADDR_HI
>+#define SDMA7_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA7_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA7_RLC6_RB_RPTR_ADDR_LO
>+#define SDMA7_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA7_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA7_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA7_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA7_RLC6_IB_CNTL
>+#define SDMA7_RLC6_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA7_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA7_RLC6_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA7_RLC6_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA7_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA7_RLC6_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA7_RLC6_IB_RPTR
>+#define SDMA7_RLC6_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA7_RLC6_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA7_RLC6_IB_OFFSET
>+#define SDMA7_RLC6_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA7_RLC6_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA7_RLC6_IB_BASE_LO
>+#define SDMA7_RLC6_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA7_RLC6_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA7_RLC6_IB_BASE_HI
>+#define SDMA7_RLC6_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC6_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC6_IB_SIZE
>+#define SDMA7_RLC6_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA7_RLC6_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA7_RLC6_SKIP_CNTL
>+#define SDMA7_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA7_RLC6_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA7_RLC6_CONTEXT_STATUS
>+#define SDMA7_RLC6_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA7_RLC6_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA7_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA7_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA7_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA7_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA7_RLC6_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA7_RLC6_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA7_RLC6_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA7_RLC6_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA7_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA7_RLC6_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA7_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA7_RLC6_DOORBELL
>+#define SDMA7_RLC6_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA7_RLC6_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA7_RLC6_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA7_RLC6_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA7_RLC6_STATUS
>+#define SDMA7_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA7_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA7_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA7_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA7_RLC6_DOORBELL_LOG
>+#define SDMA7_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA7_RLC6_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA7_RLC6_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA7_RLC6_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA7_RLC6_WATERMARK
>+#define SDMA7_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA7_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA7_RLC6_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA7_RLC6_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA7_RLC6_DOORBELL_OFFSET
>+#define SDMA7_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA7_RLC6_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA7_RLC6_CSA_ADDR_LO
>+#define SDMA7_RLC6_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA7_RLC6_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA7_RLC6_CSA_ADDR_HI
>+#define SDMA7_RLC6_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA7_RLC6_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA7_RLC6_IB_SUB_REMAIN
>+#define SDMA7_RLC6_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA7_RLC6_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA7_RLC6_PREEMPT
>+#define SDMA7_RLC6_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA7_RLC6_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA7_RLC6_DUMMY_REG
>+#define SDMA7_RLC6_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA7_RLC6_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC6_RB_WPTR_POLL_ADDR_HI
>+#define SDMA7_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA7_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA7_RLC6_RB_WPTR_POLL_ADDR_LO
>+#define SDMA7_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA7_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA7_RLC6_RB_AQL_CNTL
>+#define SDMA7_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA7_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA7_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA7_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA7_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA7_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA7_RLC6_MINOR_PTR_UPDATE
>+#define SDMA7_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA7_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA7_RLC6_MIDCMD_DATA0
>+#define SDMA7_RLC6_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA7_RLC6_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC6_MIDCMD_DATA1
>+#define SDMA7_RLC6_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA7_RLC6_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC6_MIDCMD_DATA2
>+#define SDMA7_RLC6_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA7_RLC6_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC6_MIDCMD_DATA3
>+#define SDMA7_RLC6_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA7_RLC6_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC6_MIDCMD_DATA4
>+#define SDMA7_RLC6_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA7_RLC6_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC6_MIDCMD_DATA5
>+#define SDMA7_RLC6_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA7_RLC6_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC6_MIDCMD_DATA6
>+#define SDMA7_RLC6_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA7_RLC6_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC6_MIDCMD_DATA7
>+#define SDMA7_RLC6_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA7_RLC6_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC6_MIDCMD_DATA8
>+#define SDMA7_RLC6_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA7_RLC6_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC6_MIDCMD_CNTL
>+#define SDMA7_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA7_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA7_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA7_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA7_RLC6_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA7_RLC6_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA7_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA7_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+//SDMA7_RLC7_RB_CNTL
>+#define SDMA7_RLC7_RB_CNTL__RB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC7_RB_CNTL__RB_SIZE__SHIFT                                                                    0x1
>+#define SDMA7_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT                                                             0x9
>+#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT                                                      0xc
>+#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT                                                 0xd
>+#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
>+#define SDMA7_RLC7_RB_CNTL__RB_PRIV__SHIFT                                                                    0x17
>+#define SDMA7_RLC7_RB_CNTL__RB_VMID__SHIFT                                                                    0x18
>+#define SDMA7_RLC7_RB_CNTL__RB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC7_RB_CNTL__RB_SIZE_MASK                                                                      0x0000003EL
>+#define SDMA7_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK                                                               0x00000200L
>+#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK                                                        0x00001000L
>+#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK                                                   0x00002000L
>+#define SDMA7_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK                                                         0x001F0000L
>+#define SDMA7_RLC7_RB_CNTL__RB_PRIV_MASK                                                                      0x00800000L
>+#define SDMA7_RLC7_RB_CNTL__RB_VMID_MASK                                                                      0x0F000000L
>+//SDMA7_RLC7_RB_BASE
>+#define SDMA7_RLC7_RB_BASE__ADDR__SHIFT                                                                       0x0
>+#define SDMA7_RLC7_RB_BASE__ADDR_MASK                                                                         0xFFFFFFFFL
>+//SDMA7_RLC7_RB_BASE_HI
>+#define SDMA7_RLC7_RB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC7_RB_BASE_HI__ADDR_MASK                                                                      0x00FFFFFFL
>+//SDMA7_RLC7_RB_RPTR
>+#define SDMA7_RLC7_RB_RPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC7_RB_RPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC7_RB_RPTR_HI
>+#define SDMA7_RLC7_RB_RPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC7_RB_RPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC7_RB_WPTR
>+#define SDMA7_RLC7_RB_WPTR__OFFSET__SHIFT                                                                     0x0
>+#define SDMA7_RLC7_RB_WPTR__OFFSET_MASK                                                                       0xFFFFFFFFL
>+//SDMA7_RLC7_RB_WPTR_HI
>+#define SDMA7_RLC7_RB_WPTR_HI__OFFSET__SHIFT                                                                  0x0
>+#define SDMA7_RLC7_RB_WPTR_HI__OFFSET_MASK                                                                    0xFFFFFFFFL
>+//SDMA7_RLC7_RB_WPTR_POLL_CNTL
>+#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT                                                           0x0
>+#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT                                                      0x1
>+#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT                                                  0x2
>+#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                        0x4
>+#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                  0x10
>+#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK                                                             0x00000001L
>+#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK                                                        0x00000002L
>+#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK                                                    0x00000004L
>+#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK                                                          0x0000FFF0L
>+#define SDMA7_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                    0xFFFF0000L
>+//SDMA7_RLC7_RB_RPTR_ADDR_HI
>+#define SDMA7_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT                                                               0x0
>+#define SDMA7_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK                                                                 0xFFFFFFFFL
>+//SDMA7_RLC7_RB_RPTR_ADDR_LO
>+#define SDMA7_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT                                                       0x0
>+#define SDMA7_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT                                                               0x2
>+#define SDMA7_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK                                                         0x00000001L
>+#define SDMA7_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK                                                                 0xFFFFFFFCL
>+//SDMA7_RLC7_IB_CNTL
>+#define SDMA7_RLC7_IB_CNTL__IB_ENABLE__SHIFT                                                                  0x0
>+#define SDMA7_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT                                                             0x4
>+#define SDMA7_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT                                                           0x8
>+#define SDMA7_RLC7_IB_CNTL__CMD_VMID__SHIFT                                                                   0x10
>+#define SDMA7_RLC7_IB_CNTL__IB_ENABLE_MASK                                                                    0x00000001L
>+#define SDMA7_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK                                                               0x00000010L
>+#define SDMA7_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK                                                             0x00000100L
>+#define SDMA7_RLC7_IB_CNTL__CMD_VMID_MASK                                                                     0x000F0000L
>+//SDMA7_RLC7_IB_RPTR
>+#define SDMA7_RLC7_IB_RPTR__OFFSET__SHIFT                                                                     0x2
>+#define SDMA7_RLC7_IB_RPTR__OFFSET_MASK                                                                       0x003FFFFCL
>+//SDMA7_RLC7_IB_OFFSET
>+#define SDMA7_RLC7_IB_OFFSET__OFFSET__SHIFT                                                                   0x2
>+#define SDMA7_RLC7_IB_OFFSET__OFFSET_MASK                                                                     0x003FFFFCL
>+//SDMA7_RLC7_IB_BASE_LO
>+#define SDMA7_RLC7_IB_BASE_LO__ADDR__SHIFT                                                                    0x5
>+#define SDMA7_RLC7_IB_BASE_LO__ADDR_MASK                                                                      0xFFFFFFE0L
>+//SDMA7_RLC7_IB_BASE_HI
>+#define SDMA7_RLC7_IB_BASE_HI__ADDR__SHIFT                                                                    0x0
>+#define SDMA7_RLC7_IB_BASE_HI__ADDR_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC7_IB_SIZE
>+#define SDMA7_RLC7_IB_SIZE__SIZE__SHIFT                                                                       0x0
>+#define SDMA7_RLC7_IB_SIZE__SIZE_MASK                                                                         0x000FFFFFL
>+//SDMA7_RLC7_SKIP_CNTL
>+#define SDMA7_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT                                                               0x0
>+#define SDMA7_RLC7_SKIP_CNTL__SKIP_COUNT_MASK                                                                 0x000FFFFFL
>+//SDMA7_RLC7_CONTEXT_STATUS
>+#define SDMA7_RLC7_CONTEXT_STATUS__SELECTED__SHIFT                                                            0x0
>+#define SDMA7_RLC7_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
>+#define SDMA7_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT                                                             0x3
>+#define SDMA7_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT                                                           0x4
>+#define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT                                                          0x7
>+#define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT                                                         0x8
>+#define SDMA7_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT                                                           0x9
>+#define SDMA7_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT                                                     0xa
>+#define SDMA7_RLC7_CONTEXT_STATUS__SELECTED_MASK                                                              0x00000001L
>+#define SDMA7_RLC7_CONTEXT_STATUS__IDLE_MASK                                                                  0x00000004L
>+#define SDMA7_RLC7_CONTEXT_STATUS__EXPIRED_MASK                                                               0x00000008L
>+#define SDMA7_RLC7_CONTEXT_STATUS__EXCEPTION_MASK                                                             0x00000070L
>+#define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK                                                            0x00000080L
>+#define SDMA7_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK                                                           0x00000100L
>+#define SDMA7_RLC7_CONTEXT_STATUS__PREEMPTED_MASK                                                             0x00000200L
>+#define SDMA7_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK                                                       0x00000400L
>+//SDMA7_RLC7_DOORBELL
>+#define SDMA7_RLC7_DOORBELL__ENABLE__SHIFT                                                                    0x1c
>+#define SDMA7_RLC7_DOORBELL__CAPTURED__SHIFT                                                                  0x1e
>+#define SDMA7_RLC7_DOORBELL__ENABLE_MASK                                                                      0x10000000L
>+#define SDMA7_RLC7_DOORBELL__CAPTURED_MASK                                                                    0x40000000L
>+//SDMA7_RLC7_STATUS
>+#define SDMA7_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
>+#define SDMA7_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
>+#define SDMA7_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK                                                        0x000000FFL
>+#define SDMA7_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK                                                           0x00000100L
>+//SDMA7_RLC7_DOORBELL_LOG
>+#define SDMA7_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT                                                              0x0
>+#define SDMA7_RLC7_DOORBELL_LOG__DATA__SHIFT                                                                  0x2
>+#define SDMA7_RLC7_DOORBELL_LOG__BE_ERROR_MASK                                                                0x00000001L
>+#define SDMA7_RLC7_DOORBELL_LOG__DATA_MASK                                                                    0xFFFFFFFCL
>+//SDMA7_RLC7_WATERMARK
>+#define SDMA7_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT                                                           0x0
>+#define SDMA7_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT                                                           0x10
>+#define SDMA7_RLC7_WATERMARK__RD_OUTSTANDING_MASK                                                             0x00000FFFL
>+#define SDMA7_RLC7_WATERMARK__WR_OUTSTANDING_MASK                                                             0x03FF0000L
>+//SDMA7_RLC7_DOORBELL_OFFSET
>+#define SDMA7_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT                                                             0x2
>+#define SDMA7_RLC7_DOORBELL_OFFSET__OFFSET_MASK                                                               0x0FFFFFFCL
>+//SDMA7_RLC7_CSA_ADDR_LO
>+#define SDMA7_RLC7_CSA_ADDR_LO__ADDR__SHIFT                                                                   0x2
>+#define SDMA7_RLC7_CSA_ADDR_LO__ADDR_MASK                                                                     0xFFFFFFFCL
>+//SDMA7_RLC7_CSA_ADDR_HI
>+#define SDMA7_RLC7_CSA_ADDR_HI__ADDR__SHIFT                                                                   0x0
>+#define SDMA7_RLC7_CSA_ADDR_HI__ADDR_MASK                                                                     0xFFFFFFFFL
>+//SDMA7_RLC7_IB_SUB_REMAIN
>+#define SDMA7_RLC7_IB_SUB_REMAIN__SIZE__SHIFT                                                                 0x0
>+#define SDMA7_RLC7_IB_SUB_REMAIN__SIZE_MASK                                                                   0x000FFFFFL
>+//SDMA7_RLC7_PREEMPT
>+#define SDMA7_RLC7_PREEMPT__IB_PREEMPT__SHIFT                                                                 0x0
>+#define SDMA7_RLC7_PREEMPT__IB_PREEMPT_MASK                                                                   0x00000001L
>+//SDMA7_RLC7_DUMMY_REG
>+#define SDMA7_RLC7_DUMMY_REG__DUMMY__SHIFT                                                                    0x0
>+#define SDMA7_RLC7_DUMMY_REG__DUMMY_MASK                                                                      0xFFFFFFFFL
>+//SDMA7_RLC7_RB_WPTR_POLL_ADDR_HI
>+#define SDMA7_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
>+#define SDMA7_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK                                                            0xFFFFFFFFL
>+//SDMA7_RLC7_RB_WPTR_POLL_ADDR_LO
>+#define SDMA7_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT                                                          0x2
>+#define SDMA7_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK                                                            0xFFFFFFFCL
>+//SDMA7_RLC7_RB_AQL_CNTL
>+#define SDMA7_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT                                                             0x0
>+#define SDMA7_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT                                                        0x1
>+#define SDMA7_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT                                                            0x8
>+#define SDMA7_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK                                                               0x00000001L
>+#define SDMA7_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK                                                          0x000000FEL
>+#define SDMA7_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK                                                              0x0000FF00L
>+//SDMA7_RLC7_MINOR_PTR_UPDATE
>+#define SDMA7_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT                                                            0x0
>+#define SDMA7_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK                                                              0x00000001L
>+//SDMA7_RLC7_MIDCMD_DATA0
>+#define SDMA7_RLC7_MIDCMD_DATA0__DATA0__SHIFT                                                                 0x0
>+#define SDMA7_RLC7_MIDCMD_DATA0__DATA0_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC7_MIDCMD_DATA1
>+#define SDMA7_RLC7_MIDCMD_DATA1__DATA1__SHIFT                                                                 0x0
>+#define SDMA7_RLC7_MIDCMD_DATA1__DATA1_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC7_MIDCMD_DATA2
>+#define SDMA7_RLC7_MIDCMD_DATA2__DATA2__SHIFT                                                                 0x0
>+#define SDMA7_RLC7_MIDCMD_DATA2__DATA2_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC7_MIDCMD_DATA3
>+#define SDMA7_RLC7_MIDCMD_DATA3__DATA3__SHIFT                                                                 0x0
>+#define SDMA7_RLC7_MIDCMD_DATA3__DATA3_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC7_MIDCMD_DATA4
>+#define SDMA7_RLC7_MIDCMD_DATA4__DATA4__SHIFT                                                                 0x0
>+#define SDMA7_RLC7_MIDCMD_DATA4__DATA4_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC7_MIDCMD_DATA5
>+#define SDMA7_RLC7_MIDCMD_DATA5__DATA5__SHIFT                                                                 0x0
>+#define SDMA7_RLC7_MIDCMD_DATA5__DATA5_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC7_MIDCMD_DATA6
>+#define SDMA7_RLC7_MIDCMD_DATA6__DATA6__SHIFT                                                                 0x0
>+#define SDMA7_RLC7_MIDCMD_DATA6__DATA6_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC7_MIDCMD_DATA7
>+#define SDMA7_RLC7_MIDCMD_DATA7__DATA7__SHIFT                                                                 0x0
>+#define SDMA7_RLC7_MIDCMD_DATA7__DATA7_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC7_MIDCMD_DATA8
>+#define SDMA7_RLC7_MIDCMD_DATA8__DATA8__SHIFT                                                                 0x0
>+#define SDMA7_RLC7_MIDCMD_DATA8__DATA8_MASK                                                                   0xFFFFFFFFL
>+//SDMA7_RLC7_MIDCMD_CNTL
>+#define SDMA7_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT                                                             0x0
>+#define SDMA7_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT                                                              0x1
>+#define SDMA7_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
>+#define SDMA7_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT                                                          0x8
>+#define SDMA7_RLC7_MIDCMD_CNTL__DATA_VALID_MASK                                                               0x00000001L
>+#define SDMA7_RLC7_MIDCMD_CNTL__COPY_MODE_MASK                                                                0x00000002L
>+#define SDMA7_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK                                                              0x000000F0L
>+#define SDMA7_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK                                                            0x00000100L
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_offset.h	2019-08-31 15:01:11.934736175 -0500
>@@ -29,6 +29,98 @@
> #define mmSMUSVI0_TEL_PLANE0_BASE_IDX                                                                  0
> #define mmSMUIO_MCM_CONFIG                                                                             0x0024
> #define mmSMUIO_MCM_CONFIG_BASE_IDX                                                                    0
>+#define mmCKSVII2C_IC_CON                                                                              0x0040
>+#define mmCKSVII2C_IC_CON_BASE_IDX                                                                     0
>+#define mmCKSVII2C_IC_TAR                                                                              0x0041
>+#define mmCKSVII2C_IC_TAR_BASE_IDX                                                                     0
>+#define mmCKSVII2C_IC_SAR                                                                              0x0042
>+#define mmCKSVII2C_IC_SAR_BASE_IDX                                                                     0
>+#define mmCKSVII2C_IC_HS_MADDR                                                                         0x0043
>+#define mmCKSVII2C_IC_HS_MADDR_BASE_IDX                                                                0
>+#define mmCKSVII2C_IC_DATA_CMD                                                                         0x0044
>+#define mmCKSVII2C_IC_DATA_CMD_BASE_IDX                                                                0
>+#define mmCKSVII2C_IC_SS_SCL_HCNT                                                                      0x0045
>+#define mmCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX                                                             0
>+#define mmCKSVII2C_IC_SS_SCL_LCNT                                                                      0x0046
>+#define mmCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX                                                             0
>+#define mmCKSVII2C_IC_FS_SCL_HCNT                                                                      0x0047
>+#define mmCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX                                                             0
>+#define mmCKSVII2C_IC_FS_SCL_LCNT                                                                      0x0048
>+#define mmCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX                                                             0
>+#define mmCKSVII2C_IC_HS_SCL_HCNT                                                                      0x0049
>+#define mmCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX                                                             0
>+#define mmCKSVII2C_IC_HS_SCL_LCNT                                                                      0x004a
>+#define mmCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX                                                             0
>+#define mmCKSVII2C_IC_INTR_STAT                                                                        0x004b
>+#define mmCKSVII2C_IC_INTR_STAT_BASE_IDX                                                               0
>+#define mmCKSVII2C_IC_INTR_MASK                                                                        0x004c
>+#define mmCKSVII2C_IC_INTR_MASK_BASE_IDX                                                               0
>+#define mmCKSVII2C_IC_RAW_INTR_STAT                                                                    0x004d
>+#define mmCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX                                                           0
>+#define mmCKSVII2C_IC_RX_TL                                                                            0x004e
>+#define mmCKSVII2C_IC_RX_TL_BASE_IDX                                                                   0
>+#define mmCKSVII2C_IC_TX_TL                                                                            0x004f
>+#define mmCKSVII2C_IC_TX_TL_BASE_IDX                                                                   0
>+#define mmCKSVII2C_IC_CLR_INTR                                                                         0x0050
>+#define mmCKSVII2C_IC_CLR_INTR_BASE_IDX                                                                0
>+#define mmCKSVII2C_IC_CLR_RX_UNDER                                                                     0x0051
>+#define mmCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX                                                            0
>+#define mmCKSVII2C_IC_CLR_RX_OVER                                                                      0x0052
>+#define mmCKSVII2C_IC_CLR_RX_OVER_BASE_IDX                                                             0
>+#define mmCKSVII2C_IC_CLR_TX_OVER                                                                      0x0053
>+#define mmCKSVII2C_IC_CLR_TX_OVER_BASE_IDX                                                             0
>+#define mmCKSVII2C_IC_CLR_RD_REQ                                                                       0x0054
>+#define mmCKSVII2C_IC_CLR_RD_REQ_BASE_IDX                                                              0
>+#define mmCKSVII2C_IC_CLR_TX_ABRT                                                                      0x0055
>+#define mmCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX                                                             0
>+#define mmCKSVII2C_IC_CLR_RX_DONE                                                                      0x0056
>+#define mmCKSVII2C_IC_CLR_RX_DONE_BASE_IDX                                                             0
>+#define mmCKSVII2C_IC_CLR_ACTIVITY                                                                     0x0057
>+#define mmCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX                                                            0
>+#define mmCKSVII2C_IC_CLR_STOP_DET                                                                     0x0058
>+#define mmCKSVII2C_IC_CLR_STOP_DET_BASE_IDX                                                            0
>+#define mmCKSVII2C_IC_CLR_START_DET                                                                    0x0059
>+#define mmCKSVII2C_IC_CLR_START_DET_BASE_IDX                                                           0
>+#define mmCKSVII2C_IC_CLR_GEN_CALL                                                                     0x005a
>+#define mmCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX                                                            0
>+#define mmCKSVII2C_IC_ENABLE                                                                           0x005b
>+#define mmCKSVII2C_IC_ENABLE_BASE_IDX                                                                  0
>+#define mmCKSVII2C_IC_STATUS                                                                           0x005c
>+#define mmCKSVII2C_IC_STATUS_BASE_IDX                                                                  0
>+#define mmCKSVII2C_IC_TXFLR                                                                            0x005d
>+#define mmCKSVII2C_IC_TXFLR_BASE_IDX                                                                   0
>+#define mmCKSVII2C_IC_RXFLR                                                                            0x005e
>+#define mmCKSVII2C_IC_RXFLR_BASE_IDX                                                                   0
>+#define mmCKSVII2C_IC_SDA_HOLD                                                                         0x005f
>+#define mmCKSVII2C_IC_SDA_HOLD_BASE_IDX                                                                0
>+#define mmCKSVII2C_IC_TX_ABRT_SOURCE                                                                   0x0060
>+#define mmCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX                                                          0
>+#define mmCKSVII2C_IC_SLV_DATA_NACK_ONLY                                                               0x0061
>+#define mmCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX                                                      0
>+#define mmCKSVII2C_IC_DMA_CR                                                                           0x0062
>+#define mmCKSVII2C_IC_DMA_CR_BASE_IDX                                                                  0
>+#define mmCKSVII2C_IC_DMA_TDLR                                                                         0x0063
>+#define mmCKSVII2C_IC_DMA_TDLR_BASE_IDX                                                                0
>+#define mmCKSVII2C_IC_DMA_RDLR                                                                         0x0064
>+#define mmCKSVII2C_IC_DMA_RDLR_BASE_IDX                                                                0
>+#define mmCKSVII2C_IC_SDA_SETUP                                                                        0x0065
>+#define mmCKSVII2C_IC_SDA_SETUP_BASE_IDX                                                               0
>+#define mmCKSVII2C_IC_ACK_GENERAL_CALL                                                                 0x0066
>+#define mmCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX                                                        0
>+#define mmCKSVII2C_IC_ENABLE_STATUS                                                                    0x0067
>+#define mmCKSVII2C_IC_ENABLE_STATUS_BASE_IDX                                                           0
>+#define mmCKSVII2C_IC_FS_SPKLEN                                                                        0x0068
>+#define mmCKSVII2C_IC_FS_SPKLEN_BASE_IDX                                                               0
>+#define mmCKSVII2C_IC_HS_SPKLEN                                                                        0x0069
>+#define mmCKSVII2C_IC_HS_SPKLEN_BASE_IDX                                                               0
>+#define mmCKSVII2C_IC_CLR_RESTART_DET                                                                  0x006a
>+#define mmCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX                                                         0
>+#define mmCKSVII2C_IC_COMP_PARAM_1                                                                     0x006b
>+#define mmCKSVII2C_IC_COMP_PARAM_1_BASE_IDX                                                            0
>+#define mmCKSVII2C_IC_COMP_VERSION                                                                     0x006c
>+#define mmCKSVII2C_IC_COMP_VERSION_BASE_IDX                                                            0
>+#define mmCKSVII2C_IC_COMP_TYPE                                                                        0x006d
>+#define mmCKSVII2C_IC_COMP_TYPE_BASE_IDX                                                               0
> #define mmSMUIO_MP_RESET_INTR                                                                          0x00c1
> #define mmSMUIO_MP_RESET_INTR_BASE_IDX                                                                 0
> #define mmSMUIO_SOC_HALT                                                                               0x00c2
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_11_0_0_sh_mask.h	2019-08-31 15:01:11.934736175 -0500
>@@ -37,6 +37,237 @@
> #define SMUIO_MCM_CONFIG__PKG_TYPE_MASK                                                                       0x0000001CL
> #define SMUIO_MCM_CONFIG__SOCKET_ID_MASK                                                                      0x00000020L
> #define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK                                                                    0x000000C0L
>+//CKSVII2C_IC_CON
>+#define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT                                                                0x0
>+#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT                                                             0x1
>+#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT                                                            0x3
>+#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT                                                           0x4
>+#define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT                                                                 0x5
>+#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT                                                              0x6
>+#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT                                                          0x7
>+#define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT                                                                 0x8
>+#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT                                                         0x9
>+#define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK                                                                  0x00000001L
>+#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK                                                               0x00000006L
>+#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK                                                              0x00000008L
>+#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK                                                             0x00000010L
>+#define CKSVII2C_IC_CON__IC_RESTART_EN_MASK                                                                   0x00000020L
>+#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK                                                                0x00000040L
>+#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK                                                            0x00000080L
>+#define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK                                                                   0x00000100L
>+#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK                                                           0x00000200L
>+//CKSVII2C_IC_TAR
>+#define CKSVII2C_IC_TAR__IC_TAR__SHIFT                                                                        0x0
>+#define CKSVII2C_IC_TAR__GC_OR_START__SHIFT                                                                   0xa
>+#define CKSVII2C_IC_TAR__SPECIAL__SHIFT                                                                       0xb
>+#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT                                                           0xc
>+#define CKSVII2C_IC_TAR__IC_TAR_MASK                                                                          0x000003FFL
>+#define CKSVII2C_IC_TAR__GC_OR_START_MASK                                                                     0x00000400L
>+#define CKSVII2C_IC_TAR__SPECIAL_MASK                                                                         0x00000800L
>+#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK                                                             0x00001000L
>+//CKSVII2C_IC_SAR
>+#define CKSVII2C_IC_SAR__IC_SAR__SHIFT                                                                        0x0
>+#define CKSVII2C_IC_SAR__IC_SAR_MASK                                                                          0x000003FFL
>+//CKSVII2C_IC_HS_MADDR
>+#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT                                                              0x0
>+#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK                                                                0x00000007L
>+//CKSVII2C_IC_DATA_CMD
>+#define CKSVII2C_IC_DATA_CMD__DAT__SHIFT                                                                      0x0
>+#define CKSVII2C_IC_DATA_CMD__CMD__SHIFT                                                                      0x8
>+#define CKSVII2C_IC_DATA_CMD__STOP__SHIFT                                                                     0x9
>+#define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT                                                                  0xa
>+#define CKSVII2C_IC_DATA_CMD__DAT_MASK                                                                        0x000000FFL
>+#define CKSVII2C_IC_DATA_CMD__CMD_MASK                                                                        0x00000100L
>+#define CKSVII2C_IC_DATA_CMD__STOP_MASK                                                                       0x00000200L
>+#define CKSVII2C_IC_DATA_CMD__RESTART_MASK                                                                    0x00000400L
>+//CKSVII2C_IC_SS_SCL_HCNT
>+#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT                                                        0x0
>+#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK                                                          0x0000FFFFL
>+//CKSVII2C_IC_SS_SCL_LCNT
>+#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT                                                        0x0
>+#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK                                                          0x0000FFFFL
>+//CKSVII2C_IC_FS_SCL_HCNT
>+#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT                                                        0x0
>+#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK                                                          0x0000FFFFL
>+//CKSVII2C_IC_FS_SCL_LCNT
>+#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT                                                        0x0
>+#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK                                                          0x0000FFFFL
>+//CKSVII2C_IC_HS_SCL_HCNT
>+#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT                                                        0x0
>+#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK                                                          0x0000FFFFL
>+//CKSVII2C_IC_HS_SCL_LCNT
>+#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT                                                        0x0
>+#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK                                                          0x0000FFFFL
>+//CKSVII2C_IC_INTR_STAT
>+#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT                                                              0x0
>+#define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT                                                               0x1
>+#define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT                                                               0x2
>+#define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT                                                               0x3
>+#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT                                                              0x4
>+#define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT                                                                0x5
>+#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT                                                               0x6
>+#define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT                                                               0x7
>+#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT                                                              0x8
>+#define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT                                                              0x9
>+#define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT                                                             0xa
>+#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT                                                              0xb
>+#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT                                                           0xc
>+#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT                                                           0xd
>+#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK                                                                0x00000001L
>+#define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK                                                                 0x00000002L
>+#define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK                                                                 0x00000004L
>+#define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK                                                                 0x00000008L
>+#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK                                                                0x00000010L
>+#define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK                                                                  0x00000020L
>+#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK                                                                 0x00000040L
>+#define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK                                                                 0x00000080L
>+#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK                                                                0x00000100L
>+#define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK                                                                0x00000200L
>+#define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK                                                               0x00000400L
>+#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK                                                                0x00000800L
>+#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK                                                             0x00001000L
>+#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK                                                             0x00002000L
>+//CKSVII2C_IC_INTR_MASK
>+#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT                                                              0x0
>+#define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT                                                               0x1
>+#define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT                                                               0x2
>+#define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT                                                               0x3
>+#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT                                                              0x4
>+#define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT                                                                0x5
>+#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT                                                               0x6
>+#define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT                                                               0x7
>+#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT                                                              0x8
>+#define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT                                                              0x9
>+#define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT                                                             0xa
>+#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT                                                              0xb
>+#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT                                                           0xc
>+#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT                                                           0xd
>+#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK                                                                0x00000001L
>+#define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK                                                                 0x00000002L
>+#define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK                                                                 0x00000004L
>+#define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK                                                                 0x00000008L
>+#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK                                                                0x00000010L
>+#define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK                                                                  0x00000020L
>+#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK                                                                 0x00000040L
>+#define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK                                                                 0x00000080L
>+#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK                                                                0x00000100L
>+#define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK                                                                0x00000200L
>+#define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK                                                               0x00000400L
>+#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK                                                                0x00000800L
>+#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK                                                             0x00001000L
>+#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK                                                             0x00002000L
>+//CKSVII2C_IC_RAW_INTR_STAT
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_UNDER__SHIFT                                                              0x0
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_OVER__SHIFT                                                               0x1
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_FULL__SHIFT                                                               0x2
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_OVER__SHIFT                                                               0x3
>+#define CKSVII2C_IC__RAW_INTR_STAT__R_TX_EMPTY__SHIFT                                                              0x4
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_RD_REQ__SHIFT                                                                0x5
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_ABRT__SHIFT                                                               0x6
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_DONE__SHIFT                                                               0x7
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_ACTIVITY__SHIFT                                                              0x8
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_STOP_DET__SHIFT                                                              0x9
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET__SHIFT                                                             0xa
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_GEN_CALL__SHIFT                                                              0xb
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_RESTART_DET__SHIFT                                                           0xc
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_MST_ON_HOLD__SHIFT                                                           0xd
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_UNDER_MASK                                                                0x00000001L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_OVER_MASK                                                                 0x00000002L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_FULL_MASK                                                                 0x00000004L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_OVER_MASK                                                                 0x00000008L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_EMPTY_MASK                                                                0x00000010L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_RD_REQ_MASK                                                                  0x00000020L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_TX_ABRT_MASK                                                                 0x00000040L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_RX_DONE_MASK                                                                 0x00000080L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_ACTIVITY_MASK                                                                0x00000100L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_STOP_DET_MASK                                                                0x00000200L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_START_DET_MASK                                                               0x00000400L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_GEN_CALL_MASK                                                                0x00000800L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_RESTART_DET_MASK                                                             0x00001000L
>+#define CKSVII2C_IC_RAW_INTR_STAT__R_MST_ON_HOLD_MASK                                                             0x00002000L
>+//CKSVII2C_IC_RX_TL
>+//CKSVII2C_IC_TX_TL
>+//CKSVII2C_IC_CLR_INTR
>+//CKSVII2C_IC_CLR_RX_UNDER
>+//CKSVII2C_IC_CLR_RX_OVER
>+//CKSVII2C_IC_CLR_TX_OVER
>+//CKSVII2C_IC_CLR_RD_REQ
>+//CKSVII2C_IC_CLR_TX_ABRT
>+//CKSVII2C_IC_CLR_RX_DONE
>+//CKSVII2C_IC_CLR_ACTIVITY
>+#define CKSVII2C_IC_CLR_ACTIVITY__CLR_ACTIVITY__SHIFT                                                         0x0
>+#define CKSVII2C_IC_CLR_ACTIVITY__CLR_ACTIVITY_MASK                                                           0x00000001L
>+//CKSVII2C_IC_CLR_STOP_DET
>+//CKSVII2C_IC_CLR_START_DET
>+//CKSVII2C_IC_CLR_GEN_CALL
>+//CKSVII2C_IC_ENABLE
>+#define CKSVII2C_IC_ENABLE__ENABLE__SHIFT                                                                     0x0
>+#define CKSVII2C_IC_ENABLE__ABORT__SHIFT                                                                      0x1
>+#define CKSVII2C_IC_ENABLE__ENABLE_MASK                                                                       0x00000001L
>+#define CKSVII2C_IC_ENABLE__ABORT_MASK                                                                        0x00000002L
>+//CKSVII2C_IC_STATUS
>+#define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT                                                                   0x0
>+#define CKSVII2C_IC_STATUS__TFNF__SHIFT                                                                       0x1
>+#define CKSVII2C_IC_STATUS__TFE__SHIFT                                                                        0x2
>+#define CKSVII2C_IC_STATUS__RFNE__SHIFT                                                                       0x3
>+#define CKSVII2C_IC_STATUS__RFF__SHIFT                                                                        0x4
>+#define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT                                                               0x5
>+#define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT                                                               0x6
>+#define CKSVII2C_IC_STATUS__ACTIVITY_MASK                                                                     0x00000001L
>+#define CKSVII2C_IC_STATUS__TFNF_MASK                                                                         0x00000002L
>+#define CKSVII2C_IC_STATUS__TFE_MASK                                                                          0x00000004L
>+#define CKSVII2C_IC_STATUS__RFNE_MASK                                                                         0x00000008L
>+#define CKSVII2C_IC_STATUS__RFF_MASK                                                                          0x00000010L
>+#define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK                                                                 0x00000020L
>+#define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK                                                                 0x00000040L
>+//CKSVII2C_IC_TXFLR
>+//CKSVII2C_IC_RXFLR
>+//CKSVII2C_IC_SDA_HOLD
>+#define CKSVII2C_IC_SDA_HOLD__IC_SDA_HOLD__SHIFT                                                              0x0
>+#define CKSVII2C_IC_SDA_HOLD__IC_SDA_HOLD_MASK                                                                0x00FFFFFFL
>+//CKSVII2C_IC_TX_ABRT_SOURCE
>+
>+#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_7B_ADDR_NOACK__SHIFT                                                  0x0
>+#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR1_NOACK__SHIFT                                                  0x1
>+#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR2_NOACK__SHIFT                                                  0x2
>+#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_TXDATA_NOACK__SHIFT                                                   0x3
>+#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_7B_ADDR_NOACK_MASK                                                   0x00000001L
>+#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR1_NOACK_MASK                                                   0x00000002L
>+#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_10ADDR2_NOACK_MASK                                                   0x00000004L
>+#define CKSVII2C_IC_TX_ABRT_SOURCE__ABRT_TXDATA_NOACK_MASK                                                    0x00000008L
>+//CKSVII2C_IC_SLV_DATA_NACK_ONLY
>+//CKSVII2C_IC_DMA_CR
>+//CKSVII2C_IC_DMA_TDLR
>+//CKSVII2C_IC_DMA_RDLR
>+//CKSVII2C_IC_SDA_SETUP
>+#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT                                                               0x0
>+#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK                                                                 0x000000FFL
>+//CKSVII2C_IC_ACK_GENERAL_CALL
>+#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL__SHIFT                                                 0x0
>+#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL_MASK                                                   0x00000001L
>+//CKSVII2C_IC_ENABLE_STATUS
>+#define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT                                                               0x0
>+#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_ABORTED__SHIFT                                                      0x1
>+#define CKSVII2C_IC_ENABLE_STATUS__SLV_FIFO_FILLED_AND_FLUSHED__SHIFT                                         0x2
>+#define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK                                                                 0x00000001L
>+#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_ABORTED_MASK                                                        0x00000002L
>+#define CKSVII2C_IC_ENABLE_STATUS__SLV_FIFO_FILLED_AND_FLUSHED_MASK                                           0x00000004L
>+//CKSVII2C_IC_FS_SPKLEN
>+#define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN__SHIFT                                                               0x0
>+#define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN_MASK                                                                 0x000000FFL
>+//CKSVII2C_IC_HS_SPKLEN
>+#define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN__SHIFT                                                               0x0
>+#define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN_MASK                                                                 0x000000FFL
>+//CKSVII2C_IC_CLR_RESTART_DET
>+//CKSVII2C_IC_COMP_PARAM_1
>+#define CKSVII2C_IC_COMP_PARAM_1__COMP_PARAM_1__SHIFT                                                         0x0
>+#define CKSVII2C_IC_COMP_PARAM_1__COMP_PARAM_1_MASK                                                           0xFFFFFFFFL
>+//CKSVII2C_IC_COMP_VERSION
>+#define CKSVII2C_IC_COMP_VERSION__COMP_VERSION__SHIFT                                                         0x0
>+#define CKSVII2C_IC_COMP_VERSION__COMP_VERSION_MASK                                                           0xFFFFFFFFL
>+//CKSVII2C_IC_COMP_TYPE
>+#define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT                                                               0x0
>+#define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK                                                                 0xFFFFFFFFL
> //SMUIO_MP_RESET_INTR
> #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR__SHIFT                                                       0x0
> #define SMUIO_MP_RESET_INTR__SMUIO_MP_RESET_INTR_MASK                                                         0x00000001L
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_offset.h	2019-08-31 15:01:11.934736175 -0500
>@@ -0,0 +1,31 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _umc_6_1_1_OFFSET_HEADER
>+#define _umc_6_1_1_OFFSET_HEADER
>+
>+#define mmUMCCH0_0_EccErrCntSel                                                                        0x0360
>+#define mmUMCCH0_0_EccErrCntSel_BASE_IDX                                                               0
>+#define mmUMCCH0_0_EccErrCnt                                                                           0x0361
>+#define mmUMCCH0_0_EccErrCnt_BASE_IDX                                                                  0
>+#define mmMCA_UMC_UMC0_MCUMC_STATUST0                                                                  0x03c2
>+#define mmMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX                                                         0
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_1_1_sh_mask.h	2019-08-31 15:01:11.934736175 -0500
>@@ -0,0 +1,91 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _umc_6_1_1_SH_MASK_HEADER
>+#define _umc_6_1_1_SH_MASK_HEADER
>+
>+//UMCCH0_0_EccErrCntSel
>+#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel__SHIFT                                                          0x0
>+#define UMCCH0_0_EccErrCntSel__EccErrInt__SHIFT                                                               0xc
>+#define UMCCH0_0_EccErrCntSel__EccErrCntEn__SHIFT                                                             0xf
>+#define UMCCH0_0_EccErrCntSel__EccErrCntCsSel_MASK                                                            0x0000000FL
>+#define UMCCH0_0_EccErrCntSel__EccErrInt_MASK                                                                 0x00003000L
>+#define UMCCH0_0_EccErrCntSel__EccErrCntEn_MASK                                                               0x00008000L
>+//UMCCH0_0_EccErrCnt
>+#define UMCCH0_0_EccErrCnt__EccErrCnt__SHIFT                                                                  0x0
>+#define UMCCH0_0_EccErrCnt__EccErrCnt_MASK                                                                    0x0000FFFFL
>+//MCA_UMC_UMC0_MCUMC_STATUST0
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT                                                         0x0
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT                                                      0x10
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV0__SHIFT                                                           0x16
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT                                                         0x20
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV1__SHIFT                                                           0x26
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT                                                             0x28
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV2__SHIFT                                                           0x29
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT                                                            0x2b
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT                                                          0x2c
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT                                                              0x2d
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT                                                              0x2e
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV3__SHIFT                                                           0x2f
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT                                                       0x34
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT                                                             0x35
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV4__SHIFT                                                           0x36
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT                                                               0x37
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT                                                      0x38
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT                                                               0x39
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT                                                             0x3a
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT                                                             0x3b
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT                                                                0x3c
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT                                                                0x3d
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT                                                          0x3e
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT                                                               0x3f
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK                                                           0x000000000000FFFFL
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK                                                        0x00000000003F0000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV0_MASK                                                             0x00000000FFC00000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK                                                           0x0000003F00000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV1_MASK                                                             0x000000C000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK                                                               0x0000010000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV2_MASK                                                             0x0000060000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK                                                              0x0000080000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK                                                            0x0000100000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK                                                                0x0000200000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK                                                                0x0000400000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV3_MASK                                                             0x000F800000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK                                                         0x0010000000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK                                                               0x0020000000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV4_MASK                                                             0x0040000000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK                                                                 0x0080000000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK                                                        0x0100000000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK                                                                 0x0200000000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK                                                               0x0400000000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK                                                               0x0800000000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK                                                                  0x1000000000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK                                                                  0x2000000000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK                                                            0x4000000000000000L
>+#define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK                                                                 0x8000000000000000L
>+//MCA_UMC_UMC0_MCUMC_ADDRT0
>+#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT                                                           0x0
>+#define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB__SHIFT                                                                 0x38
>+#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT                                                            0x3e
>+#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK                                                             0x00FFFFFFFFFFFFFFL
>+#define MCA_UMC_UMC0_MCUMC_ADDRT0__LSB_MASK                                                                   0x3F00000000000000L
>+#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK                                                              0xC000000000000000L
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h	2019-08-31 15:01:11.934736175 -0500
>@@ -0,0 +1,979 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+
>+#ifndef _vcn_2_5_OFFSET_HEADER
>+#define _vcn_2_5_OFFSET_HEADER
>+
>+// addressBlock: uvd0_mmsch_dec
>+// base address: 0x1e000
>+
>+
>+// addressBlock: uvd0_jpegnpdec
>+// base address: 0x1e200
>+#define mmUVD_JPEG_CNTL                                                                                0x0080
>+#define mmUVD_JPEG_CNTL_BASE_IDX                                                                       0
>+#define mmUVD_JPEG_RB_BASE                                                                             0x0081
>+#define mmUVD_JPEG_RB_BASE_BASE_IDX                                                                    0
>+#define mmUVD_JPEG_RB_WPTR                                                                             0x0082
>+#define mmUVD_JPEG_RB_WPTR_BASE_IDX                                                                    0
>+#define mmUVD_JPEG_RB_RPTR                                                                             0x0083
>+#define mmUVD_JPEG_RB_RPTR_BASE_IDX                                                                    0
>+#define mmUVD_JPEG_RB_SIZE                                                                             0x0084
>+#define mmUVD_JPEG_RB_SIZE_BASE_IDX                                                                    0
>+#define mmUVD_JPEG_DEC_SCRATCH0                                                                        0x0089
>+#define mmUVD_JPEG_DEC_SCRATCH0_BASE_IDX                                                               0
>+#define mmUVD_JPEG_INT_EN                                                                              0x008a
>+#define mmUVD_JPEG_INT_EN_BASE_IDX                                                                     0
>+#define mmUVD_JPEG_INT_STAT                                                                            0x008b
>+#define mmUVD_JPEG_INT_STAT_BASE_IDX                                                                   0
>+#define mmUVD_JPEG_PITCH                                                                               0x009f
>+#define mmUVD_JPEG_PITCH_BASE_IDX                                                                      0
>+#define mmUVD_JPEG_UV_PITCH                                                                            0x00a0
>+#define mmUVD_JPEG_UV_PITCH_BASE_IDX                                                                   0
>+#define mmJPEG_DEC_Y_GFX8_TILING_SURFACE                                                               0x00a1
>+#define mmJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX                                                      0
>+#define mmJPEG_DEC_UV_GFX8_TILING_SURFACE                                                              0x00a2
>+#define mmJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX                                                     0
>+#define mmJPEG_DEC_GFX8_ADDR_CONFIG                                                                    0x00a3
>+#define mmJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX                                                           0
>+#define mmJPEG_DEC_Y_GFX10_TILING_SURFACE                                                              0x00a4
>+#define mmJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX                                                     0
>+#define mmJPEG_DEC_UV_GFX10_TILING_SURFACE                                                             0x00a5
>+#define mmJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX                                                    0
>+#define mmJPEG_DEC_GFX10_ADDR_CONFIG                                                                   0x00a6
>+#define mmJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX                                                          0
>+#define mmJPEG_DEC_ADDR_MODE                                                                           0x00a7
>+#define mmJPEG_DEC_ADDR_MODE_BASE_IDX                                                                  0
>+#define mmUVD_JPEG_GPCOM_CMD                                                                           0x00a9
>+#define mmUVD_JPEG_GPCOM_CMD_BASE_IDX                                                                  0
>+#define mmUVD_JPEG_GPCOM_DATA0                                                                         0x00aa
>+#define mmUVD_JPEG_GPCOM_DATA0_BASE_IDX                                                                0
>+#define mmUVD_JPEG_GPCOM_DATA1                                                                         0x00ab
>+#define mmUVD_JPEG_GPCOM_DATA1_BASE_IDX                                                                0
>+#define mmUVD_JPEG_SCRATCH1                                                                            0x00ae
>+#define mmUVD_JPEG_SCRATCH1_BASE_IDX                                                                   0
>+#define mmUVD_JPEG_DEC_SOFT_RST                                                                        0x00af
>+#define mmUVD_JPEG_DEC_SOFT_RST_BASE_IDX                                                               0
>+
>+
>+// addressBlock: uvd0_uvd_jpeg_enc_dec
>+// base address: 0x1e300
>+#define mmUVD_JPEG_ENC_INT_EN                                                                          0x00c1
>+#define mmUVD_JPEG_ENC_INT_EN_BASE_IDX                                                                 0
>+#define mmUVD_JPEG_ENC_INT_STATUS                                                                      0x00c2
>+#define mmUVD_JPEG_ENC_INT_STATUS_BASE_IDX                                                             0
>+#define mmUVD_JPEG_ENC_ENGINE_CNTL                                                                     0x00c5
>+#define mmUVD_JPEG_ENC_ENGINE_CNTL_BASE_IDX                                                            0
>+#define mmUVD_JPEG_ENC_SCRATCH1                                                                        0x00ce
>+#define mmUVD_JPEG_ENC_SCRATCH1_BASE_IDX                                                               0
>+
>+
>+// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
>+// base address: 0x1e380
>+#define mmUVD_JPEG_ENC_STATUS                                                                          0x00e5
>+#define mmUVD_JPEG_ENC_STATUS_BASE_IDX                                                                 0
>+#define mmUVD_JPEG_ENC_PITCH                                                                           0x00e6
>+#define mmUVD_JPEG_ENC_PITCH_BASE_IDX                                                                  0
>+#define mmUVD_JPEG_ENC_LUMA_BASE                                                                       0x00e7
>+#define mmUVD_JPEG_ENC_LUMA_BASE_BASE_IDX                                                              0
>+#define mmUVD_JPEG_ENC_CHROMAU_BASE                                                                    0x00e8
>+#define mmUVD_JPEG_ENC_CHROMAU_BASE_BASE_IDX                                                           0
>+#define mmUVD_JPEG_ENC_CHROMAV_BASE                                                                    0x00e9
>+#define mmUVD_JPEG_ENC_CHROMAV_BASE_BASE_IDX                                                           0
>+#define mmJPEG_ENC_Y_GFX10_TILING_SURFACE                                                              0x00ea
>+#define mmJPEG_ENC_Y_GFX10_TILING_SURFACE_BASE_IDX                                                     0
>+#define mmJPEG_ENC_UV_GFX10_TILING_SURFACE                                                             0x00eb
>+#define mmJPEG_ENC_UV_GFX10_TILING_SURFACE_BASE_IDX                                                    0
>+#define mmJPEG_ENC_GFX10_ADDR_CONFIG                                                                   0x00ec
>+#define mmJPEG_ENC_GFX10_ADDR_CONFIG_BASE_IDX                                                          0
>+#define mmJPEG_ENC_ADDR_MODE                                                                           0x00ed
>+#define mmJPEG_ENC_ADDR_MODE_BASE_IDX                                                                  0
>+#define mmUVD_JPEG_ENC_GPCOM_CMD                                                                       0x00ee
>+#define mmUVD_JPEG_ENC_GPCOM_CMD_BASE_IDX                                                              0
>+#define mmUVD_JPEG_ENC_GPCOM_DATA0                                                                     0x00ef
>+#define mmUVD_JPEG_ENC_GPCOM_DATA0_BASE_IDX                                                            0
>+#define mmUVD_JPEG_ENC_GPCOM_DATA1                                                                     0x00f0
>+#define mmUVD_JPEG_ENC_GPCOM_DATA1_BASE_IDX                                                            0
>+#define mmUVD_JPEG_ENC_CGC_CNTL                                                                        0x00f5
>+#define mmUVD_JPEG_ENC_CGC_CNTL_BASE_IDX                                                               0
>+#define mmUVD_JPEG_ENC_SCRATCH0                                                                        0x00f6
>+#define mmUVD_JPEG_ENC_SCRATCH0_BASE_IDX                                                               0
>+#define mmUVD_JPEG_ENC_SOFT_RST                                                                        0x00f7
>+#define mmUVD_JPEG_ENC_SOFT_RST_BASE_IDX                                                               0
>+
>+
>+// addressBlock: uvd0_uvd_jrbc_dec
>+// base address: 0x1e400
>+#define mmUVD_JRBC_RB_WPTR                                                                             0x0100
>+#define mmUVD_JRBC_RB_WPTR_BASE_IDX                                                                    0
>+#define mmUVD_JRBC_RB_CNTL                                                                             0x0101
>+#define mmUVD_JRBC_RB_CNTL_BASE_IDX                                                                    0
>+#define mmUVD_JRBC_IB_SIZE                                                                             0x0102
>+#define mmUVD_JRBC_IB_SIZE_BASE_IDX                                                                    0
>+#define mmUVD_JRBC_URGENT_CNTL                                                                         0x0103
>+#define mmUVD_JRBC_URGENT_CNTL_BASE_IDX                                                                0
>+#define mmUVD_JRBC_RB_REF_DATA                                                                         0x0104
>+#define mmUVD_JRBC_RB_REF_DATA_BASE_IDX                                                                0
>+#define mmUVD_JRBC_RB_COND_RD_TIMER                                                                    0x0105
>+#define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX                                                           0
>+#define mmUVD_JRBC_SOFT_RESET                                                                          0x0108
>+#define mmUVD_JRBC_SOFT_RESET_BASE_IDX                                                                 0
>+#define mmUVD_JRBC_STATUS                                                                              0x0109
>+#define mmUVD_JRBC_STATUS_BASE_IDX                                                                     0
>+#define mmUVD_JRBC_RB_RPTR                                                                             0x010a
>+#define mmUVD_JRBC_RB_RPTR_BASE_IDX                                                                    0
>+#define mmUVD_JRBC_RB_BUF_STATUS                                                                       0x010b
>+#define mmUVD_JRBC_RB_BUF_STATUS_BASE_IDX                                                              0
>+#define mmUVD_JRBC_IB_BUF_STATUS                                                                       0x010c
>+#define mmUVD_JRBC_IB_BUF_STATUS_BASE_IDX                                                              0
>+#define mmUVD_JRBC_IB_SIZE_UPDATE                                                                      0x010d
>+#define mmUVD_JRBC_IB_SIZE_UPDATE_BASE_IDX                                                             0
>+#define mmUVD_JRBC_IB_COND_RD_TIMER                                                                    0x010e
>+#define mmUVD_JRBC_IB_COND_RD_TIMER_BASE_IDX                                                           0
>+#define mmUVD_JRBC_IB_REF_DATA                                                                         0x010f
>+#define mmUVD_JRBC_IB_REF_DATA_BASE_IDX                                                                0
>+#define mmUVD_JPEG_PREEMPT_CMD                                                                         0x0110
>+#define mmUVD_JPEG_PREEMPT_CMD_BASE_IDX                                                                0
>+#define mmUVD_JPEG_PREEMPT_FENCE_DATA0                                                                 0x0111
>+#define mmUVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX                                                        0
>+#define mmUVD_JPEG_PREEMPT_FENCE_DATA1                                                                 0x0112
>+#define mmUVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX                                                        0
>+#define mmUVD_JRBC_RB_SIZE                                                                             0x0113
>+#define mmUVD_JRBC_RB_SIZE_BASE_IDX                                                                    0
>+#define mmUVD_JRBC_SCRATCH0                                                                            0x0114
>+#define mmUVD_JRBC_SCRATCH0_BASE_IDX                                                                   0
>+
>+
>+// addressBlock: uvd0_uvd_jrbc_enc_dec
>+// base address: 0x1e480
>+#define mmUVD_JRBC_ENC_RB_WPTR                                                                         0x0120
>+#define mmUVD_JRBC_ENC_RB_WPTR_BASE_IDX                                                                0
>+#define mmUVD_JRBC_ENC_RB_CNTL                                                                         0x0121
>+#define mmUVD_JRBC_ENC_RB_CNTL_BASE_IDX                                                                0
>+#define mmUVD_JRBC_ENC_IB_SIZE                                                                         0x0122
>+#define mmUVD_JRBC_ENC_IB_SIZE_BASE_IDX                                                                0
>+#define mmUVD_JRBC_ENC_URGENT_CNTL                                                                     0x0123
>+#define mmUVD_JRBC_ENC_URGENT_CNTL_BASE_IDX                                                            0
>+#define mmUVD_JRBC_ENC_RB_REF_DATA                                                                     0x0124
>+#define mmUVD_JRBC_ENC_RB_REF_DATA_BASE_IDX                                                            0
>+#define mmUVD_JRBC_ENC_RB_COND_RD_TIMER                                                                0x0125
>+#define mmUVD_JRBC_ENC_RB_COND_RD_TIMER_BASE_IDX                                                       0
>+#define mmUVD_JRBC_ENC_SOFT_RESET                                                                      0x0128
>+#define mmUVD_JRBC_ENC_SOFT_RESET_BASE_IDX                                                             0
>+#define mmUVD_JRBC_ENC_STATUS                                                                          0x0129
>+#define mmUVD_JRBC_ENC_STATUS_BASE_IDX                                                                 0
>+#define mmUVD_JRBC_ENC_RB_RPTR                                                                         0x012a
>+#define mmUVD_JRBC_ENC_RB_RPTR_BASE_IDX                                                                0
>+#define mmUVD_JRBC_ENC_RB_BUF_STATUS                                                                   0x012b
>+#define mmUVD_JRBC_ENC_RB_BUF_STATUS_BASE_IDX                                                          0
>+#define mmUVD_JRBC_ENC_IB_BUF_STATUS                                                                   0x012c
>+#define mmUVD_JRBC_ENC_IB_BUF_STATUS_BASE_IDX                                                          0
>+#define mmUVD_JRBC_ENC_IB_SIZE_UPDATE                                                                  0x012d
>+#define mmUVD_JRBC_ENC_IB_SIZE_UPDATE_BASE_IDX                                                         0
>+#define mmUVD_JRBC_ENC_IB_COND_RD_TIMER                                                                0x012e
>+#define mmUVD_JRBC_ENC_IB_COND_RD_TIMER_BASE_IDX                                                       0
>+#define mmUVD_JRBC_ENC_IB_REF_DATA                                                                     0x012f
>+#define mmUVD_JRBC_ENC_IB_REF_DATA_BASE_IDX                                                            0
>+#define mmUVD_JPEG_ENC_PREEMPT_CMD                                                                     0x0130
>+#define mmUVD_JPEG_ENC_PREEMPT_CMD_BASE_IDX                                                            0
>+#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0                                                             0x0131
>+#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA0_BASE_IDX                                                    0
>+#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1                                                             0x0132
>+#define mmUVD_JPEG_ENC_PREEMPT_FENCE_DATA1_BASE_IDX                                                    0
>+#define mmUVD_JRBC_ENC_RB_SIZE                                                                         0x0133
>+#define mmUVD_JRBC_ENC_RB_SIZE_BASE_IDX                                                                0
>+#define mmUVD_JRBC_ENC_SCRATCH0                                                                        0x0134
>+#define mmUVD_JRBC_ENC_SCRATCH0_BASE_IDX                                                               0
>+
>+
>+// addressBlock: uvd0_uvd_jmi_dec
>+// base address: 0x1e500
>+#define mmUVD_JMI_CTRL                                                                                 0x0145
>+#define mmUVD_JMI_CTRL_BASE_IDX                                                                        0
>+#define mmUVD_LMI_JRBC_CTRL                                                                            0x0146
>+#define mmUVD_LMI_JRBC_CTRL_BASE_IDX                                                                   0
>+#define mmUVD_LMI_JPEG_CTRL                                                                            0x0147
>+#define mmUVD_LMI_JPEG_CTRL_BASE_IDX                                                                   0
>+#define mmUVD_JMI_EJRBC_CTRL                                                                           0x0148
>+#define mmUVD_JMI_EJRBC_CTRL_BASE_IDX                                                                  0
>+#define mmUVD_LMI_EJPEG_CTRL                                                                           0x0149
>+#define mmUVD_LMI_EJPEG_CTRL_BASE_IDX                                                                  0
>+#define mmUVD_LMI_JRBC_IB_VMID                                                                         0x014f
>+#define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX                                                                0
>+#define mmUVD_LMI_JRBC_RB_VMID                                                                         0x0150
>+#define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX                                                                0
>+#define mmUVD_LMI_JPEG_VMID                                                                            0x0151
>+#define mmUVD_LMI_JPEG_VMID_BASE_IDX                                                                   0
>+#define mmUVD_JMI_ENC_JRBC_IB_VMID                                                                     0x0152
>+#define mmUVD_JMI_ENC_JRBC_IB_VMID_BASE_IDX                                                            0
>+#define mmUVD_JMI_ENC_JRBC_RB_VMID                                                                     0x0153
>+#define mmUVD_JMI_ENC_JRBC_RB_VMID_BASE_IDX                                                            0
>+#define mmUVD_JMI_ENC_JPEG_VMID                                                                        0x0154
>+#define mmUVD_JMI_ENC_JPEG_VMID_BASE_IDX                                                               0
>+#define mmUVD_JMI_PERFMON_CTRL                                                                         0x015c
>+#define mmUVD_JMI_PERFMON_CTRL_BASE_IDX                                                                0
>+#define mmUVD_JMI_PERFMON_COUNT_LO                                                                     0x015d
>+#define mmUVD_JMI_PERFMON_COUNT_LO_BASE_IDX                                                            0
>+#define mmUVD_JMI_PERFMON_COUNT_HI                                                                     0x015e
>+#define mmUVD_JMI_PERFMON_COUNT_HI_BASE_IDX                                                            0
>+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW                                                              0x0160
>+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX                                                     0
>+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH                                                             0x0161
>+#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX                                                    0
>+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW                                                             0x0162
>+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX                                                    0
>+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH                                                            0x0163
>+#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX                                                   0
>+#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW                                                     0x0164
>+#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX                                            0
>+#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH                                                    0x0165
>+#define mmUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX                                           0
>+#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW                                                                0x0166
>+#define mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX                                                       0
>+#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH                                                               0x0167
>+#define mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX                                                      0
>+#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW                                                                0x0168
>+#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX                                                       0
>+#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH                                                               0x0169
>+#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX                                                      0
>+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW                                                         0x016a
>+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                                0
>+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH                                                        0x016b
>+#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                               0
>+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW                                                         0x016c
>+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                                0
>+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH                                                        0x016d
>+#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                               0
>+#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW                                                         0x016e
>+#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                                0
>+#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH                                                        0x016f
>+#define mmUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                               0
>+#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW                                                         0x0170
>+#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                                0
>+#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH                                                        0x0171
>+#define mmUVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                               0
>+#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW                                                    0x017a
>+#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX                                           0
>+#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH                                                   0x017b
>+#define mmUVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX                                          0
>+#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW                                                               0x017c
>+#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_LOW_BASE_IDX                                                      0
>+#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH                                                              0x017d
>+#define mmUVD_LMI_EJRBC_RB_64BIT_BAR_HIGH_BASE_IDX                                                     0
>+#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW                                                               0x017e
>+#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_LOW_BASE_IDX                                                      0
>+#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH                                                              0x017f
>+#define mmUVD_LMI_EJRBC_IB_64BIT_BAR_HIGH_BASE_IDX                                                     0
>+#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW                                                        0x0180
>+#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                               0
>+#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH                                                       0x0181
>+#define mmUVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                              0
>+#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW                                                        0x0182
>+#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                               0
>+#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH                                                       0x0183
>+#define mmUVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                              0
>+#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW                                                        0x0184
>+#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX                                               0
>+#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH                                                       0x0185
>+#define mmUVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX                                              0
>+#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW                                                        0x0186
>+#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW_BASE_IDX                                               0
>+#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH                                                       0x0187
>+#define mmUVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX                                              0
>+#define mmUVD_LMI_JPEG_PREEMPT_VMID                                                                    0x0188
>+#define mmUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX                                                           0
>+#define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID                                                                0x0189
>+#define mmUVD_LMI_ENC_JPEG_PREEMPT_VMID_BASE_IDX                                                       0
>+#define mmUVD_LMI_JPEG2_VMID                                                                           0x018a
>+#define mmUVD_LMI_JPEG2_VMID_BASE_IDX                                                                  0
>+#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW                                                             0x018b
>+#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_LOW_BASE_IDX                                                    0
>+#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH                                                            0x018c
>+#define mmUVD_LMI_JPEG2_READ_64BIT_BAR_HIGH_BASE_IDX                                                   0
>+#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW                                                            0x018d
>+#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW_BASE_IDX                                                   0
>+#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH                                                           0x018e
>+#define mmUVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH_BASE_IDX                                                  0
>+#define mmUVD_LMI_JPEG_CTRL2                                                                           0x018f
>+#define mmUVD_LMI_JPEG_CTRL2_BASE_IDX                                                                  0
>+#define mmUVD_JMI_DEC_SWAP_CNTL                                                                        0x0190
>+#define mmUVD_JMI_DEC_SWAP_CNTL_BASE_IDX                                                               0
>+#define mmUVD_JMI_ENC_SWAP_CNTL                                                                        0x0191
>+#define mmUVD_JMI_ENC_SWAP_CNTL_BASE_IDX                                                               0
>+#define mmUVD_JMI_CNTL                                                                                 0x0192
>+#define mmUVD_JMI_CNTL_BASE_IDX                                                                        0
>+#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW                                                             0x019a
>+#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_LOW_BASE_IDX                                                    0
>+#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH                                                            0x019b
>+#define mmUVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH_BASE_IDX                                                   0
>+#define mmUVD_JMI_DEC_SWAP_CNTL2                                                                       0x019c
>+#define mmUVD_JMI_DEC_SWAP_CNTL2_BASE_IDX                                                              0
>+
>+
>+// addressBlock: uvd0_uvd_jpeg_common_dec
>+// base address: 0x1e700
>+#define mmJPEG_SOFT_RESET_STATUS                                                                       0x01c0
>+#define mmJPEG_SOFT_RESET_STATUS_BASE_IDX                                                              0
>+#define mmJPEG_SYS_INT_EN                                                                              0x01c1
>+#define mmJPEG_SYS_INT_EN_BASE_IDX                                                                     0
>+#define mmJPEG_SYS_INT_STATUS                                                                          0x01c2
>+#define mmJPEG_SYS_INT_STATUS_BASE_IDX                                                                 0
>+#define mmJPEG_SYS_INT_ACK                                                                             0x01c3
>+#define mmJPEG_SYS_INT_ACK_BASE_IDX                                                                    0
>+#define mmJPEG_MASTINT_EN                                                                              0x01c8
>+#define mmJPEG_MASTINT_EN_BASE_IDX                                                                     0
>+#define mmJPEG_IH_CTRL                                                                                 0x01c9
>+#define mmJPEG_IH_CTRL_BASE_IDX                                                                        0
>+#define mmJRBBM_ARB_CTRL                                                                               0x01cb
>+#define mmJRBBM_ARB_CTRL_BASE_IDX                                                                      0
>+
>+
>+// addressBlock: uvd0_uvd_jpeg_common_sclk_dec
>+// base address: 0x1e780
>+#define mmJPEG_CGC_GATE                                                                                0x01e0
>+#define mmJPEG_CGC_GATE_BASE_IDX                                                                       0
>+#define mmJPEG_CGC_CTRL                                                                                0x01e1
>+#define mmJPEG_CGC_CTRL_BASE_IDX                                                                       0
>+#define mmJPEG_CGC_STATUS                                                                              0x01e2
>+#define mmJPEG_CGC_STATUS_BASE_IDX                                                                     0
>+#define mmJPEG_COMN_CGC_MEM_CTRL                                                                       0x01e3
>+#define mmJPEG_COMN_CGC_MEM_CTRL_BASE_IDX                                                              0
>+#define mmJPEG_DEC_CGC_MEM_CTRL                                                                        0x01e4
>+#define mmJPEG_DEC_CGC_MEM_CTRL_BASE_IDX                                                               0
>+#define mmJPEG2_DEC_CGC_MEM_CTRL                                                                       0x01e5
>+#define mmJPEG2_DEC_CGC_MEM_CTRL_BASE_IDX                                                              0
>+#define mmJPEG_ENC_CGC_MEM_CTRL                                                                        0x01e6
>+#define mmJPEG_ENC_CGC_MEM_CTRL_BASE_IDX                                                               0
>+#define mmJPEG_SOFT_RESET2                                                                             0x01e7
>+#define mmJPEG_SOFT_RESET2_BASE_IDX                                                                    0
>+#define mmJPEG_PERF_BANK_CONF                                                                          0x01e8
>+#define mmJPEG_PERF_BANK_CONF_BASE_IDX                                                                 0
>+#define mmJPEG_PERF_BANK_EVENT_SEL                                                                     0x01e9
>+#define mmJPEG_PERF_BANK_EVENT_SEL_BASE_IDX                                                            0
>+#define mmJPEG_PERF_BANK_COUNT0                                                                        0x01ea
>+#define mmJPEG_PERF_BANK_COUNT0_BASE_IDX                                                               0
>+#define mmJPEG_PERF_BANK_COUNT1                                                                        0x01eb
>+#define mmJPEG_PERF_BANK_COUNT1_BASE_IDX                                                               0
>+#define mmJPEG_PERF_BANK_COUNT2                                                                        0x01ec
>+#define mmJPEG_PERF_BANK_COUNT2_BASE_IDX                                                               0
>+#define mmJPEG_PERF_BANK_COUNT3                                                                        0x01ed
>+#define mmJPEG_PERF_BANK_COUNT3_BASE_IDX                                                               0
>+
>+
>+// addressBlock: uvd0_uvd_pg_dec
>+// base address: 0x1f800
>+#define mmUVD_PGFSM_CONFIG                                                                             0x0000
>+#define mmUVD_PGFSM_CONFIG_BASE_IDX                                                                    1
>+#define mmUVD_PGFSM_STATUS                                                                             0x0001
>+#define mmUVD_PGFSM_STATUS_BASE_IDX                                                                    1
>+#define mmUVD_POWER_STATUS                                                                             0x0004
>+#define mmUVD_POWER_STATUS_BASE_IDX                                                                    1
>+#define mmUVD_PG_IND_INDEX                                                                             0x0005
>+#define mmUVD_PG_IND_INDEX_BASE_IDX                                                                    1
>+#define mmUVD_PG_IND_DATA                                                                              0x0006
>+#define mmUVD_PG_IND_DATA_BASE_IDX                                                                     1
>+#define mmCC_UVD_HARVESTING                                                                            0x0007
>+#define mmCC_UVD_HARVESTING_BASE_IDX                                                                   1
>+#define mmUVD_JPEG_POWER_STATUS                                                                        0x000a
>+#define mmUVD_JPEG_POWER_STATUS_BASE_IDX                                                               1
>+#define mmUVD_DPG_LMA_CTL                                                                              0x0011
>+#define mmUVD_DPG_LMA_CTL_BASE_IDX                                                                     1
>+#define mmUVD_DPG_LMA_DATA                                                                             0x0012
>+#define mmUVD_DPG_LMA_DATA_BASE_IDX                                                                    1
>+#define mmUVD_DPG_LMA_MASK                                                                             0x0013
>+#define mmUVD_DPG_LMA_MASK_BASE_IDX                                                                    1
>+#define mmUVD_DPG_PAUSE                                                                                0x0014
>+#define mmUVD_DPG_PAUSE_BASE_IDX                                                                       1
>+#define mmUVD_SCRATCH1                                                                                 0x0015
>+#define mmUVD_SCRATCH1_BASE_IDX                                                                        1
>+#define mmUVD_SCRATCH2                                                                                 0x0016
>+#define mmUVD_SCRATCH2_BASE_IDX                                                                        1
>+#define mmUVD_SCRATCH3                                                                                 0x0017
>+#define mmUVD_SCRATCH3_BASE_IDX                                                                        1
>+#define mmUVD_SCRATCH4                                                                                 0x0018
>+#define mmUVD_SCRATCH4_BASE_IDX                                                                        1
>+#define mmUVD_SCRATCH5                                                                                 0x0019
>+#define mmUVD_SCRATCH5_BASE_IDX                                                                        1
>+#define mmUVD_SCRATCH6                                                                                 0x001a
>+#define mmUVD_SCRATCH6_BASE_IDX                                                                        1
>+#define mmUVD_SCRATCH7                                                                                 0x001b
>+#define mmUVD_SCRATCH7_BASE_IDX                                                                        1
>+#define mmUVD_SCRATCH8                                                                                 0x001c
>+#define mmUVD_SCRATCH8_BASE_IDX                                                                        1
>+#define mmUVD_SCRATCH9                                                                                 0x001d
>+#define mmUVD_SCRATCH9_BASE_IDX                                                                        1
>+#define mmUVD_SCRATCH10                                                                                0x001e
>+#define mmUVD_SCRATCH10_BASE_IDX                                                                       1
>+#define mmUVD_SCRATCH11                                                                                0x001f
>+#define mmUVD_SCRATCH11_BASE_IDX                                                                       1
>+#define mmUVD_SCRATCH12                                                                                0x0020
>+#define mmUVD_SCRATCH12_BASE_IDX                                                                       1
>+#define mmUVD_SCRATCH13                                                                                0x0021
>+#define mmUVD_SCRATCH13_BASE_IDX                                                                       1
>+#define mmUVD_SCRATCH14                                                                                0x0022
>+#define mmUVD_SCRATCH14_BASE_IDX                                                                       1
>+#define mmUVD_FREE_COUNTER_REG                                                                         0x0024
>+#define mmUVD_FREE_COUNTER_REG_BASE_IDX                                                                1
>+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW                                                         0x0025
>+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX                                                1
>+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                                        0x0026
>+#define mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX                                               1
>+#define mmUVD_DPG_VCPU_CACHE_OFFSET0                                                                   0x0027
>+#define mmUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX                                                          1
>+#define mmUVD_DPG_LMI_VCPU_CACHE_VMID                                                                  0x0028
>+#define mmUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX                                                         1
>+#define mmUVD_PF_STATUS                                                                                0x0039
>+#define mmUVD_PF_STATUS_BASE_IDX                                                                       1
>+#define mmUVD_DPG_CLK_EN_VCPU_REPORT                                                                   0x003c
>+#define mmUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX                                                          1
>+#define mmUVD_GFX8_ADDR_CONFIG                                                                         0x0049
>+#define mmUVD_GFX8_ADDR_CONFIG_BASE_IDX                                                                1
>+#define mmUVD_GFX10_ADDR_CONFIG                                                                        0x004a
>+#define mmUVD_GFX10_ADDR_CONFIG_BASE_IDX                                                               1
>+#define mmUVD_GPCNT2_CNTL                                                                              0x004b
>+#define mmUVD_GPCNT2_CNTL_BASE_IDX                                                                     1
>+#define mmUVD_GPCNT2_TARGET_LOWER                                                                      0x004c
>+#define mmUVD_GPCNT2_TARGET_LOWER_BASE_IDX                                                             1
>+#define mmUVD_GPCNT2_STATUS_LOWER                                                                      0x004d
>+#define mmUVD_GPCNT2_STATUS_LOWER_BASE_IDX                                                             1
>+#define mmUVD_GPCNT2_TARGET_UPPER                                                                      0x004e
>+#define mmUVD_GPCNT2_TARGET_UPPER_BASE_IDX                                                             1
>+#define mmUVD_GPCNT2_STATUS_UPPER                                                                      0x004f
>+#define mmUVD_GPCNT2_STATUS_UPPER_BASE_IDX                                                             1
>+#define mmUVD_GPCNT3_CNTL                                                                              0x0050
>+#define mmUVD_GPCNT3_CNTL_BASE_IDX                                                                     1
>+#define mmUVD_GPCNT3_TARGET_LOWER                                                                      0x0051
>+#define mmUVD_GPCNT3_TARGET_LOWER_BASE_IDX                                                             1
>+#define mmUVD_GPCNT3_STATUS_LOWER                                                                      0x0052
>+#define mmUVD_GPCNT3_STATUS_LOWER_BASE_IDX                                                             1
>+#define mmUVD_GPCNT3_TARGET_UPPER                                                                      0x0053
>+#define mmUVD_GPCNT3_TARGET_UPPER_BASE_IDX                                                             1
>+#define mmUVD_GPCNT3_STATUS_UPPER                                                                      0x0054
>+#define mmUVD_GPCNT3_STATUS_UPPER_BASE_IDX                                                             1
>+
>+
>+// addressBlock: uvd0_uvddec
>+// base address: 0x1fa00
>+#define mmUVD_STATUS                                                                                   0x0080
>+#define mmUVD_STATUS_BASE_IDX                                                                          1
>+#define mmUVD_ENC_PIPE_BUSY                                                                            0x0081
>+#define mmUVD_ENC_PIPE_BUSY_BASE_IDX                                                                   1
>+#define mmUVD_SOFT_RESET                                                                               0x0084
>+#define mmUVD_SOFT_RESET_BASE_IDX                                                                      1
>+#define mmUVD_SOFT_RESET2                                                                              0x0085
>+#define mmUVD_SOFT_RESET2_BASE_IDX                                                                     1
>+#define mmUVD_MMSCH_SOFT_RESET                                                                         0x0086
>+#define mmUVD_MMSCH_SOFT_RESET_BASE_IDX                                                                1
>+#define mmUVD_CGC_GATE                                                                                 0x0088
>+#define mmUVD_CGC_GATE_BASE_IDX                                                                        1
>+#define mmUVD_CGC_STATUS                                                                               0x0089
>+#define mmUVD_CGC_STATUS_BASE_IDX                                                                      1
>+#define mmUVD_CGC_CTRL                                                                                 0x008a
>+#define mmUVD_CGC_CTRL_BASE_IDX                                                                        1
>+#define mmUVD_CGC_UDEC_STATUS                                                                          0x008b
>+#define mmUVD_CGC_UDEC_STATUS_BASE_IDX                                                                 1
>+#define mmUVD_SUVD_CGC_GATE                                                                            0x008c
>+#define mmUVD_SUVD_CGC_GATE_BASE_IDX                                                                   1
>+#define mmUVD_SUVD_CGC_STATUS                                                                          0x008d
>+#define mmUVD_SUVD_CGC_STATUS_BASE_IDX                                                                 1
>+#define mmUVD_SUVD_CGC_CTRL                                                                            0x008e
>+#define mmUVD_SUVD_CGC_CTRL_BASE_IDX                                                                   1
>+#define mmUVD_GPCOM_VCPU_CMD                                                                           0x008f
>+#define mmUVD_GPCOM_VCPU_CMD_BASE_IDX                                                                  1
>+#define mmUVD_GPCOM_VCPU_DATA0                                                                         0x0090
>+#define mmUVD_GPCOM_VCPU_DATA0_BASE_IDX                                                                1
>+#define mmUVD_GPCOM_VCPU_DATA1                                                                         0x0091
>+#define mmUVD_GPCOM_VCPU_DATA1_BASE_IDX                                                                1
>+#define mmUVD_GPCOM_SYS_CMD                                                                            0x0092
>+#define mmUVD_GPCOM_SYS_CMD_BASE_IDX                                                                   1
>+#define mmUVD_GPCOM_SYS_DATA0                                                                          0x0093
>+#define mmUVD_GPCOM_SYS_DATA0_BASE_IDX                                                                 1
>+#define mmUVD_GPCOM_SYS_DATA1                                                                          0x0094
>+#define mmUVD_GPCOM_SYS_DATA1_BASE_IDX                                                                 1
>+#define mmUVD_VCPU_INT_EN                                                                              0x0095
>+#define mmUVD_VCPU_INT_EN_BASE_IDX                                                                     1
>+#define mmUVD_VCPU_INT_ACK                                                                             0x0097
>+#define mmUVD_VCPU_INT_ACK_BASE_IDX                                                                    1
>+#define mmUVD_VCPU_INT_ROUTE                                                                           0x0098
>+#define mmUVD_VCPU_INT_ROUTE_BASE_IDX                                                                  1
>+#define mmUVD_ENC_VCPU_INT_EN                                                                          0x009e
>+#define mmUVD_ENC_VCPU_INT_EN_BASE_IDX                                                                 1
>+#define mmUVD_ENC_VCPU_INT_ACK                                                                         0x00a0
>+#define mmUVD_ENC_VCPU_INT_ACK_BASE_IDX                                                                1
>+#define mmUVD_MASTINT_EN                                                                               0x00a1
>+#define mmUVD_MASTINT_EN_BASE_IDX                                                                      1
>+#define mmUVD_SYS_INT_EN                                                                               0x00a2
>+#define mmUVD_SYS_INT_EN_BASE_IDX                                                                      1
>+#define mmUVD_SYS_INT_STATUS                                                                           0x00a3
>+#define mmUVD_SYS_INT_STATUS_BASE_IDX                                                                  1
>+#define mmUVD_SYS_INT_ACK                                                                              0x00a4
>+#define mmUVD_SYS_INT_ACK_BASE_IDX                                                                     1
>+#define mmUVD_JOB_DONE                                                                                 0x00a5
>+#define mmUVD_JOB_DONE_BASE_IDX                                                                        1
>+#define mmUVD_CBUF_ID                                                                                  0x00a6
>+#define mmUVD_CBUF_ID_BASE_IDX                                                                         1
>+#define mmUVD_CONTEXT_ID                                                                               0x00a7
>+#define mmUVD_CONTEXT_ID_BASE_IDX                                                                      1
>+#define mmUVD_CONTEXT_ID2                                                                              0x00a8
>+#define mmUVD_CONTEXT_ID2_BASE_IDX                                                                     1
>+#define mmUVD_NO_OP                                                                                    0x00a9
>+#define mmUVD_NO_OP_BASE_IDX                                                                           1
>+#define mmUVD_RB_BASE_LO                                                                               0x00aa
>+#define mmUVD_RB_BASE_LO_BASE_IDX                                                                      1
>+#define mmUVD_RB_BASE_HI                                                                               0x00ab
>+#define mmUVD_RB_BASE_HI_BASE_IDX                                                                      1
>+#define mmUVD_RB_SIZE                                                                                  0x00ac
>+#define mmUVD_RB_SIZE_BASE_IDX                                                                         1
>+#define mmUVD_RB_RPTR                                                                                  0x00ad
>+#define mmUVD_RB_RPTR_BASE_IDX                                                                         1
>+#define mmUVD_RB_WPTR                                                                                  0x00ae
>+#define mmUVD_RB_WPTR_BASE_IDX                                                                         1
>+#define mmUVD_RB_BASE_LO2                                                                              0x00af
>+#define mmUVD_RB_BASE_LO2_BASE_IDX                                                                     1
>+#define mmUVD_RB_BASE_HI2                                                                              0x00b0
>+#define mmUVD_RB_BASE_HI2_BASE_IDX                                                                     1
>+#define mmUVD_RB_SIZE2                                                                                 0x00b1
>+#define mmUVD_RB_SIZE2_BASE_IDX                                                                        1
>+#define mmUVD_RB_RPTR2                                                                                 0x00b2
>+#define mmUVD_RB_RPTR2_BASE_IDX                                                                        1
>+#define mmUVD_RB_WPTR2                                                                                 0x00b3
>+#define mmUVD_RB_WPTR2_BASE_IDX                                                                        1
>+#define mmUVD_RB_BASE_LO3                                                                              0x00b4
>+#define mmUVD_RB_BASE_LO3_BASE_IDX                                                                     1
>+#define mmUVD_RB_BASE_HI3                                                                              0x00b5
>+#define mmUVD_RB_BASE_HI3_BASE_IDX                                                                     1
>+#define mmUVD_RB_SIZE3                                                                                 0x00b6
>+#define mmUVD_RB_SIZE3_BASE_IDX                                                                        1
>+#define mmUVD_RB_RPTR3                                                                                 0x00b7
>+#define mmUVD_RB_RPTR3_BASE_IDX                                                                        1
>+#define mmUVD_RB_WPTR3                                                                                 0x00b8
>+#define mmUVD_RB_WPTR3_BASE_IDX                                                                        1
>+#define mmUVD_RB_BASE_LO4                                                                              0x00b9
>+#define mmUVD_RB_BASE_LO4_BASE_IDX                                                                     1
>+#define mmUVD_RB_BASE_HI4                                                                              0x00ba
>+#define mmUVD_RB_BASE_HI4_BASE_IDX                                                                     1
>+#define mmUVD_RB_SIZE4                                                                                 0x00bb
>+#define mmUVD_RB_SIZE4_BASE_IDX                                                                        1
>+#define mmUVD_RB_RPTR4                                                                                 0x00bc
>+#define mmUVD_RB_RPTR4_BASE_IDX                                                                        1
>+#define mmUVD_RB_WPTR4                                                                                 0x00bd
>+#define mmUVD_RB_WPTR4_BASE_IDX                                                                        1
>+#define mmUVD_OUT_RB_BASE_LO                                                                           0x00be
>+#define mmUVD_OUT_RB_BASE_LO_BASE_IDX                                                                  1
>+#define mmUVD_OUT_RB_BASE_HI                                                                           0x00bf
>+#define mmUVD_OUT_RB_BASE_HI_BASE_IDX                                                                  1
>+#define mmUVD_OUT_RB_SIZE                                                                              0x00c0
>+#define mmUVD_OUT_RB_SIZE_BASE_IDX                                                                     1
>+#define mmUVD_OUT_RB_RPTR                                                                              0x00c1
>+#define mmUVD_OUT_RB_RPTR_BASE_IDX                                                                     1
>+#define mmUVD_OUT_RB_WPTR                                                                              0x00c2
>+#define mmUVD_OUT_RB_WPTR_BASE_IDX                                                                     1
>+#define mmUVD_RB_ARB_CTRL                                                                              0x00c6
>+#define mmUVD_RB_ARB_CTRL_BASE_IDX                                                                     1
>+#define mmUVD_CTX_INDEX                                                                                0x00c7
>+#define mmUVD_CTX_INDEX_BASE_IDX                                                                       1
>+#define mmUVD_CTX_DATA                                                                                 0x00c8
>+#define mmUVD_CTX_DATA_BASE_IDX                                                                        1
>+#define mmUVD_CXW_WR                                                                                   0x00c9
>+#define mmUVD_CXW_WR_BASE_IDX                                                                          1
>+#define mmUVD_CXW_WR_INT_ID                                                                            0x00ca
>+#define mmUVD_CXW_WR_INT_ID_BASE_IDX                                                                   1
>+#define mmUVD_CXW_WR_INT_CTX_ID                                                                        0x00cb
>+#define mmUVD_CXW_WR_INT_CTX_ID_BASE_IDX                                                               1
>+#define mmUVD_CXW_INT_ID                                                                               0x00cc
>+#define mmUVD_CXW_INT_ID_BASE_IDX                                                                      1
>+#define mmUVD_TOP_CTRL                                                                                 0x00cf
>+#define mmUVD_TOP_CTRL_BASE_IDX                                                                        1
>+#define mmUVD_YBASE                                                                                    0x00d0
>+#define mmUVD_YBASE_BASE_IDX                                                                           1
>+#define mmUVD_UVBASE                                                                                   0x00d1
>+#define mmUVD_UVBASE_BASE_IDX                                                                          1
>+#define mmUVD_PITCH                                                                                    0x00d2
>+#define mmUVD_PITCH_BASE_IDX                                                                           1
>+#define mmUVD_WIDTH                                                                                    0x00d3
>+#define mmUVD_WIDTH_BASE_IDX                                                                           1
>+#define mmUVD_HEIGHT                                                                                   0x00d4
>+#define mmUVD_HEIGHT_BASE_IDX                                                                          1
>+#define mmUVD_PICCOUNT                                                                                 0x00d5
>+#define mmUVD_PICCOUNT_BASE_IDX                                                                        1
>+#define mmUVD_SCRATCH_NP                                                                               0x00db
>+#define mmUVD_SCRATCH_NP_BASE_IDX                                                                      1
>+#define mmUVD_VERSION                                                                                  0x00dd
>+#define mmUVD_VERSION_BASE_IDX                                                                         1
>+#define mmUVD_GP_SCRATCH0                                                                              0x00de
>+#define mmUVD_GP_SCRATCH0_BASE_IDX                                                                     1
>+#define mmUVD_GP_SCRATCH1                                                                              0x00df
>+#define mmUVD_GP_SCRATCH1_BASE_IDX                                                                     1
>+#define mmUVD_GP_SCRATCH2                                                                              0x00e0
>+#define mmUVD_GP_SCRATCH2_BASE_IDX                                                                     1
>+#define mmUVD_GP_SCRATCH3                                                                              0x00e1
>+#define mmUVD_GP_SCRATCH3_BASE_IDX                                                                     1
>+#define mmUVD_GP_SCRATCH4                                                                              0x00e2
>+#define mmUVD_GP_SCRATCH4_BASE_IDX                                                                     1
>+#define mmUVD_GP_SCRATCH5                                                                              0x00e3
>+#define mmUVD_GP_SCRATCH5_BASE_IDX                                                                     1
>+#define mmUVD_GP_SCRATCH6                                                                              0x00e4
>+#define mmUVD_GP_SCRATCH6_BASE_IDX                                                                     1
>+#define mmUVD_GP_SCRATCH7                                                                              0x00e5
>+#define mmUVD_GP_SCRATCH7_BASE_IDX                                                                     1
>+#define mmUVD_GP_SCRATCH8                                                                              0x00e6
>+#define mmUVD_GP_SCRATCH8_BASE_IDX                                                                     1
>+#define mmUVD_GP_SCRATCH9                                                                              0x00e7
>+#define mmUVD_GP_SCRATCH9_BASE_IDX                                                                     1
>+#define mmUVD_GP_SCRATCH10                                                                             0x00e8
>+#define mmUVD_GP_SCRATCH10_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH11                                                                             0x00e9
>+#define mmUVD_GP_SCRATCH11_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH12                                                                             0x00ea
>+#define mmUVD_GP_SCRATCH12_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH13                                                                             0x00eb
>+#define mmUVD_GP_SCRATCH13_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH14                                                                             0x00ec
>+#define mmUVD_GP_SCRATCH14_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH15                                                                             0x00ed
>+#define mmUVD_GP_SCRATCH15_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH16                                                                             0x00ee
>+#define mmUVD_GP_SCRATCH16_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH17                                                                             0x00ef
>+#define mmUVD_GP_SCRATCH17_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH18                                                                             0x00f0
>+#define mmUVD_GP_SCRATCH18_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH19                                                                             0x00f1
>+#define mmUVD_GP_SCRATCH19_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH20                                                                             0x00f2
>+#define mmUVD_GP_SCRATCH20_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH21                                                                             0x00f3
>+#define mmUVD_GP_SCRATCH21_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH22                                                                             0x00f4
>+#define mmUVD_GP_SCRATCH22_BASE_IDX                                                                    1
>+#define mmUVD_GP_SCRATCH23                                                                             0x00f5
>+#define mmUVD_GP_SCRATCH23_BASE_IDX                                                                    1
>+
>+
>+// addressBlock: uvd0_ecpudec
>+// base address: 0x1fd00
>+#define mmUVD_VCPU_CACHE_OFFSET0                                                                       0x0140
>+#define mmUVD_VCPU_CACHE_OFFSET0_BASE_IDX                                                              1
>+#define mmUVD_VCPU_CACHE_SIZE0                                                                         0x0141
>+#define mmUVD_VCPU_CACHE_SIZE0_BASE_IDX                                                                1
>+#define mmUVD_VCPU_CACHE_OFFSET1                                                                       0x0142
>+#define mmUVD_VCPU_CACHE_OFFSET1_BASE_IDX                                                              1
>+#define mmUVD_VCPU_CACHE_SIZE1                                                                         0x0143
>+#define mmUVD_VCPU_CACHE_SIZE1_BASE_IDX                                                                1
>+#define mmUVD_VCPU_CACHE_OFFSET2                                                                       0x0144
>+#define mmUVD_VCPU_CACHE_OFFSET2_BASE_IDX                                                              1
>+#define mmUVD_VCPU_CACHE_SIZE2                                                                         0x0145
>+#define mmUVD_VCPU_CACHE_SIZE2_BASE_IDX                                                                1
>+#define mmUVD_VCPU_CACHE_OFFSET3                                                                       0x0146
>+#define mmUVD_VCPU_CACHE_OFFSET3_BASE_IDX                                                              1
>+#define mmUVD_VCPU_CACHE_SIZE3                                                                         0x0147
>+#define mmUVD_VCPU_CACHE_SIZE3_BASE_IDX                                                                1
>+#define mmUVD_VCPU_CACHE_OFFSET4                                                                       0x0148
>+#define mmUVD_VCPU_CACHE_OFFSET4_BASE_IDX                                                              1
>+#define mmUVD_VCPU_CACHE_SIZE4                                                                         0x0149
>+#define mmUVD_VCPU_CACHE_SIZE4_BASE_IDX                                                                1
>+#define mmUVD_VCPU_CACHE_OFFSET5                                                                       0x014a
>+#define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX                                                              1
>+#define mmUVD_VCPU_CACHE_SIZE5                                                                         0x014b
>+#define mmUVD_VCPU_CACHE_SIZE5_BASE_IDX                                                                1
>+#define mmUVD_VCPU_CACHE_OFFSET6                                                                       0x014c
>+#define mmUVD_VCPU_CACHE_OFFSET6_BASE_IDX                                                              1
>+#define mmUVD_VCPU_CACHE_SIZE6                                                                         0x014d
>+#define mmUVD_VCPU_CACHE_SIZE6_BASE_IDX                                                                1
>+#define mmUVD_VCPU_CACHE_OFFSET7                                                                       0x014e
>+#define mmUVD_VCPU_CACHE_OFFSET7_BASE_IDX                                                              1
>+#define mmUVD_VCPU_CACHE_SIZE7                                                                         0x014f
>+#define mmUVD_VCPU_CACHE_SIZE7_BASE_IDX                                                                1
>+#define mmUVD_VCPU_CACHE_OFFSET8                                                                       0x0150
>+#define mmUVD_VCPU_CACHE_OFFSET8_BASE_IDX                                                              1
>+#define mmUVD_VCPU_CACHE_SIZE8                                                                         0x0151
>+#define mmUVD_VCPU_CACHE_SIZE8_BASE_IDX                                                                1
>+#define mmUVD_VCPU_NONCACHE_OFFSET0                                                                    0x0152
>+#define mmUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX                                                           1
>+#define mmUVD_VCPU_NONCACHE_SIZE0                                                                      0x0153
>+#define mmUVD_VCPU_NONCACHE_SIZE0_BASE_IDX                                                             1
>+#define mmUVD_VCPU_NONCACHE_OFFSET1                                                                    0x0154
>+#define mmUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX                                                           1
>+#define mmUVD_VCPU_NONCACHE_SIZE1                                                                      0x0155
>+#define mmUVD_VCPU_NONCACHE_SIZE1_BASE_IDX                                                             1
>+#define mmUVD_VCPU_CNTL                                                                                0x0156
>+#define mmUVD_VCPU_CNTL_BASE_IDX                                                                       1
>+#define mmUVD_VCPU_PRID                                                                                0x0157
>+#define mmUVD_VCPU_PRID_BASE_IDX                                                                       1
>+#define mmUVD_VCPU_TRCE                                                                                0x0158
>+#define mmUVD_VCPU_TRCE_BASE_IDX                                                                       1
>+#define mmUVD_VCPU_TRCE_RD                                                                             0x0159
>+#define mmUVD_VCPU_TRCE_RD_BASE_IDX                                                                    1
>+
>+
>+// addressBlock: uvd0_uvd_mpcdec
>+// base address: 0x20310
>+#define mmUVD_MP_SWAP_CNTL                                                                             0x02c4
>+#define mmUVD_MP_SWAP_CNTL_BASE_IDX                                                                    1
>+#define mmUVD_MP_SWAP_CNTL2                                                                            0x02c5
>+#define mmUVD_MP_SWAP_CNTL2_BASE_IDX                                                                   1
>+#define mmUVD_MPC_LUMA_SRCH                                                                            0x02c6
>+#define mmUVD_MPC_LUMA_SRCH_BASE_IDX                                                                   1
>+#define mmUVD_MPC_LUMA_HIT                                                                             0x02c7
>+#define mmUVD_MPC_LUMA_HIT_BASE_IDX                                                                    1
>+#define mmUVD_MPC_LUMA_HITPEND                                                                         0x02c8
>+#define mmUVD_MPC_LUMA_HITPEND_BASE_IDX                                                                1
>+#define mmUVD_MPC_CHROMA_SRCH                                                                          0x02c9
>+#define mmUVD_MPC_CHROMA_SRCH_BASE_IDX                                                                 1
>+#define mmUVD_MPC_CHROMA_HIT                                                                           0x02ca
>+#define mmUVD_MPC_CHROMA_HIT_BASE_IDX                                                                  1
>+#define mmUVD_MPC_CHROMA_HITPEND                                                                       0x02cb
>+#define mmUVD_MPC_CHROMA_HITPEND_BASE_IDX                                                              1
>+#define mmUVD_MPC_CNTL                                                                                 0x02cc
>+#define mmUVD_MPC_CNTL_BASE_IDX                                                                        1
>+#define mmUVD_MPC_PITCH                                                                                0x02cd
>+#define mmUVD_MPC_PITCH_BASE_IDX                                                                       1
>+#define mmUVD_MPC_SET_MUXA0                                                                            0x02ce
>+#define mmUVD_MPC_SET_MUXA0_BASE_IDX                                                                   1
>+#define mmUVD_MPC_SET_MUXA1                                                                            0x02cf
>+#define mmUVD_MPC_SET_MUXA1_BASE_IDX                                                                   1
>+#define mmUVD_MPC_SET_MUXB0                                                                            0x02d0
>+#define mmUVD_MPC_SET_MUXB0_BASE_IDX                                                                   1
>+#define mmUVD_MPC_SET_MUXB1                                                                            0x02d1
>+#define mmUVD_MPC_SET_MUXB1_BASE_IDX                                                                   1
>+#define mmUVD_MPC_SET_MUX                                                                              0x02d2
>+#define mmUVD_MPC_SET_MUX_BASE_IDX                                                                     1
>+#define mmUVD_MPC_SET_ALU                                                                              0x02d3
>+#define mmUVD_MPC_SET_ALU_BASE_IDX                                                                     1
>+#define mmUVD_MPC_PERF0                                                                                0x02d4
>+#define mmUVD_MPC_PERF0_BASE_IDX                                                                       1
>+#define mmUVD_MPC_PERF1                                                                                0x02d5
>+#define mmUVD_MPC_PERF1_BASE_IDX                                                                       1
>+
>+
>+// addressBlock: uvd0_uvd_rbcdec
>+// base address: 0x20370
>+#define mmUVD_RBC_IB_SIZE                                                                              0x02dc
>+#define mmUVD_RBC_IB_SIZE_BASE_IDX                                                                     1
>+#define mmUVD_RBC_IB_SIZE_UPDATE                                                                       0x02dd
>+#define mmUVD_RBC_IB_SIZE_UPDATE_BASE_IDX                                                              1
>+#define mmUVD_RBC_RB_CNTL                                                                              0x02de
>+#define mmUVD_RBC_RB_CNTL_BASE_IDX                                                                     1
>+#define mmUVD_RBC_RB_RPTR_ADDR                                                                         0x02df
>+#define mmUVD_RBC_RB_RPTR_ADDR_BASE_IDX                                                                1
>+#define mmUVD_RBC_RB_RPTR                                                                              0x02e0
>+#define mmUVD_RBC_RB_RPTR_BASE_IDX                                                                     1
>+#define mmUVD_RBC_RB_WPTR                                                                              0x02e1
>+#define mmUVD_RBC_RB_WPTR_BASE_IDX                                                                     1
>+#define mmUVD_RBC_VCPU_ACCESS                                                                          0x02e2
>+#define mmUVD_RBC_VCPU_ACCESS_BASE_IDX                                                                 1
>+#define mmUVD_RBC_READ_REQ_URGENT_CNTL                                                                 0x02e5
>+#define mmUVD_RBC_READ_REQ_URGENT_CNTL_BASE_IDX                                                        1
>+#define mmUVD_RBC_RB_WPTR_CNTL                                                                         0x02e6
>+#define mmUVD_RBC_RB_WPTR_CNTL_BASE_IDX                                                                1
>+#define mmUVD_RBC_WPTR_STATUS                                                                          0x02e7
>+#define mmUVD_RBC_WPTR_STATUS_BASE_IDX                                                                 1
>+#define mmUVD_RBC_WPTR_POLL_CNTL                                                                       0x02e8
>+#define mmUVD_RBC_WPTR_POLL_CNTL_BASE_IDX                                                              1
>+#define mmUVD_RBC_WPTR_POLL_ADDR                                                                       0x02e9
>+#define mmUVD_RBC_WPTR_POLL_ADDR_BASE_IDX                                                              1
>+#define mmUVD_SEMA_CMD                                                                                 0x02ea
>+#define mmUVD_SEMA_CMD_BASE_IDX                                                                        1
>+#define mmUVD_SEMA_ADDR_LOW                                                                            0x02eb
>+#define mmUVD_SEMA_ADDR_LOW_BASE_IDX                                                                   1
>+#define mmUVD_SEMA_ADDR_HIGH                                                                           0x02ec
>+#define mmUVD_SEMA_ADDR_HIGH_BASE_IDX                                                                  1
>+#define mmUVD_ENGINE_CNTL                                                                              0x02ed
>+#define mmUVD_ENGINE_CNTL_BASE_IDX                                                                     1
>+#define mmUVD_SEMA_TIMEOUT_STATUS                                                                      0x02ee
>+#define mmUVD_SEMA_TIMEOUT_STATUS_BASE_IDX                                                             1
>+#define mmUVD_SEMA_CNTL                                                                                0x02ef
>+#define mmUVD_SEMA_CNTL_BASE_IDX                                                                       1
>+#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL                                                      0x02f0
>+#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX                                             1
>+#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL                                                             0x02f1
>+#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL_BASE_IDX                                                    1
>+#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL                                                        0x02f2
>+#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL_BASE_IDX                                               1
>+#define mmUVD_JOB_START                                                                                0x02f3
>+#define mmUVD_JOB_START_BASE_IDX                                                                       1
>+#define mmUVD_RBC_BUF_STATUS                                                                           0x02f4
>+#define mmUVD_RBC_BUF_STATUS_BASE_IDX                                                                  1
>+
>+
>+// addressBlock: uvd0_uvdgendec
>+// base address: 0x20470
>+#define mmUVD_LCM_CGC_CNTRL                                                                            0x033f
>+#define mmUVD_LCM_CGC_CNTRL_BASE_IDX                                                                   1
>+#define mmUVD_MIF_CURR_UV_ADDR_CONFIG                                                                  0x03a0
>+#define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX                                                         1
>+#define mmUVD_MIF_REF_UV_ADDR_CONFIG                                                                   0x03a1
>+#define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX                                                          1
>+#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG                                                                0x03a2
>+#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX                                                       1
>+#define mmUVD_MIF_CURR_ADDR_CONFIG                                                                     0x03ae
>+#define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX                                                            1
>+#define mmUVD_MIF_REF_ADDR_CONFIG                                                                      0x03af
>+#define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX                                                             1
>+#define mmUVD_MIF_RECON1_ADDR_CONFIG                                                                   0x03e1
>+#define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX                                                          1
>+
>+
>+// addressBlock: uvd0_lmi_adpdec
>+// base address: 0x20870
>+#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW                                                                 0x0432
>+#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX                                                        1
>+#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH                                                                0x0433
>+#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX                                                       1
>+#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW                                                                 0x0434
>+#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX                                                        1
>+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH                                                                0x0435
>+#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX                                                       1
>+#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW                                                               0x0438
>+#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX                                                      1
>+#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH                                                              0x0439
>+#define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX                                                     1
>+#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW                                                               0x043a
>+#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX                                                      1
>+#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH                                                              0x043b
>+#define mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX                                                     1
>+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW                                                             0x043c
>+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX                                                    1
>+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH                                                            0x043d
>+#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX                                                   1
>+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW                                                            0x0468
>+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX                                                   1
>+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH                                                           0x0469
>+#define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX                                                  1
>+#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW                                                            0x046a
>+#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX                                                   1
>+#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH                                                           0x046b
>+#define mmUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX                                                  1
>+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW                                                            0x046c
>+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX                                                   1
>+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH                                                           0x046d
>+#define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX                                                  1
>+#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW                                                            0x046e
>+#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX                                                   1
>+#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH                                                           0x046f
>+#define mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX                                                  1
>+#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW                                                            0x0470
>+#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX                                                   1
>+#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH                                                           0x0471
>+#define mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX                                                  1
>+#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW                                                            0x0472
>+#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX                                                   1
>+#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH                                                           0x0473
>+#define mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX                                                  1
>+#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW                                                            0x0474
>+#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX                                                   1
>+#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH                                                           0x0475
>+#define mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX                                                  1
>+#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW                                                            0x0476
>+#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX                                                   1
>+#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH                                                           0x0477
>+#define mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX                                                  1
>+#define mmUVD_LMI_SPH_64BIT_BAR_HIGH                                                                   0x047c
>+#define mmUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX                                                          1
>+#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW                                                              0x047d
>+#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX                                                     1
>+#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH                                                             0x047e
>+#define mmUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX                                                    1
>+#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW                                                              0x047f
>+#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX                                                     1
>+#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH                                                             0x0480
>+#define mmUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX                                                    1
>+#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW                                                              0x0481
>+#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX                                                     1
>+#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH                                                             0x0482
>+#define mmUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX                                                    1
>+#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW                                                              0x0483
>+#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX                                                     1
>+#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH                                                             0x0484
>+#define mmUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX                                                    1
>+#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW                                                              0x0485
>+#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX                                                     1
>+#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH                                                             0x0486
>+#define mmUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX                                                    1
>+#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW                                                              0x0487
>+#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX                                                     1
>+#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH                                                             0x0488
>+#define mmUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX                                                    1
>+#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW                                                              0x0489
>+#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX                                                     1
>+#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH                                                             0x048a
>+#define mmUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX                                                    1
>+#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW                                                              0x048b
>+#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX                                                     1
>+#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH                                                             0x048c
>+#define mmUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX                                                    1
>+#define mmUVD_LMI_MMSCH_NC_VMID                                                                        0x048d
>+#define mmUVD_LMI_MMSCH_NC_VMID_BASE_IDX                                                               1
>+#define mmUVD_LMI_MMSCH_CTRL                                                                           0x048e
>+#define mmUVD_LMI_MMSCH_CTRL_BASE_IDX                                                                  1
>+#define mmUVD_LMI_ARB_CTRL2                                                                            0x049a
>+#define mmUVD_LMI_ARB_CTRL2_BASE_IDX                                                                   1
>+#define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI                                                               0x049f
>+#define mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX                                                      1
>+#define mmUVD_LMI_VCPU_NC_VMIDS_MULTI                                                                  0x04a0
>+#define mmUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX                                                         1
>+#define mmUVD_LMI_LAT_CTRL                                                                             0x04a1
>+#define mmUVD_LMI_LAT_CTRL_BASE_IDX                                                                    1
>+#define mmUVD_LMI_LAT_CNTR                                                                             0x04a2
>+#define mmUVD_LMI_LAT_CNTR_BASE_IDX                                                                    1
>+#define mmUVD_LMI_AVG_LAT_CNTR                                                                         0x04a3
>+#define mmUVD_LMI_AVG_LAT_CNTR_BASE_IDX                                                                1
>+#define mmUVD_LMI_SPH                                                                                  0x04a4
>+#define mmUVD_LMI_SPH_BASE_IDX                                                                         1
>+#define mmUVD_LMI_VCPU_CACHE_VMID                                                                      0x04a5
>+#define mmUVD_LMI_VCPU_CACHE_VMID_BASE_IDX                                                             1
>+#define mmUVD_LMI_CTRL2                                                                                0x04a6
>+#define mmUVD_LMI_CTRL2_BASE_IDX                                                                       1
>+#define mmUVD_LMI_URGENT_CTRL                                                                          0x04a7
>+#define mmUVD_LMI_URGENT_CTRL_BASE_IDX                                                                 1
>+#define mmUVD_LMI_CTRL                                                                                 0x04a8
>+#define mmUVD_LMI_CTRL_BASE_IDX                                                                        1
>+#define mmUVD_LMI_STATUS                                                                               0x04a9
>+#define mmUVD_LMI_STATUS_BASE_IDX                                                                      1
>+#define mmUVD_LMI_PERFMON_CTRL                                                                         0x04ac
>+#define mmUVD_LMI_PERFMON_CTRL_BASE_IDX                                                                1
>+#define mmUVD_LMI_PERFMON_COUNT_LO                                                                     0x04ad
>+#define mmUVD_LMI_PERFMON_COUNT_LO_BASE_IDX                                                            1
>+#define mmUVD_LMI_PERFMON_COUNT_HI                                                                     0x04ae
>+#define mmUVD_LMI_PERFMON_COUNT_HI_BASE_IDX                                                            1
>+#define mmUVD_LMI_RBC_RB_VMID                                                                          0x04b0
>+#define mmUVD_LMI_RBC_RB_VMID_BASE_IDX                                                                 1
>+#define mmUVD_LMI_RBC_IB_VMID                                                                          0x04b1
>+#define mmUVD_LMI_RBC_IB_VMID_BASE_IDX                                                                 1
>+#define mmUVD_LMI_MC_CREDITS                                                                           0x04b2
>+#define mmUVD_LMI_MC_CREDITS_BASE_IDX                                                                  1
>+
>+
>+// addressBlock: uvd0_uvdnpdec
>+// base address: 0x20bd0
>+#define mmMDM_DMA_CMD                                                                                  0x06f4
>+#define mmMDM_DMA_CMD_BASE_IDX                                                                         1
>+#define mmMDM_DMA_STATUS                                                                               0x06f5
>+#define mmMDM_DMA_STATUS_BASE_IDX                                                                      1
>+#define mmMDM_DMA_CTL                                                                                  0x06f6
>+#define mmMDM_DMA_CTL_BASE_IDX                                                                         1
>+#define mmMDM_ENC_PIPE_BUSY                                                                            0x06f7
>+#define mmMDM_ENC_PIPE_BUSY_BASE_IDX                                                                   1
>+#define mmMDM_WIG_PIPE_BUSY                                                                            0x06f9
>+#define mmMDM_WIG_PIPE_BUSY_BASE_IDX                                                                   1
>+
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h	2019-08-31 15:01:11.935736175 -0500
>@@ -0,0 +1,3609 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+
>+#ifndef _vcn_2_5_SH_MASK_HEADER
>+#define _vcn_2_5_SH_MASK_HEADER
>+
>+// addressBlock: uvd0_mmsch_dec
>+//MMSCH_UCODE_ADDR
>+#define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT                                                                   0x2
>+#define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT                                                                   0x1f
>+#define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK                                                                     0x00003FFCL
>+#define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK                                                                     0x80000000L
>+//MMSCH_UCODE_DATA
>+#define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT                                                                   0x0
>+#define MMSCH_UCODE_DATA__UCODE_DATA_MASK                                                                     0xFFFFFFFFL
>+//MMSCH_SRAM_ADDR
>+#define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT                                                                     0x2
>+#define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT                                                                     0x1f
>+#define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK                                                                       0x00001FFCL
>+#define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK                                                                       0x80000000L
>+//MMSCH_SRAM_DATA
>+#define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT                                                                     0x0
>+#define MMSCH_SRAM_DATA__SRAM_DATA_MASK                                                                       0xFFFFFFFFL
>+//MMSCH_VF_SRAM_OFFSET
>+#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT                                                           0x2
>+#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT                                                    0x10
>+#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK                                                             0x00001FFCL
>+#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK                                                      0x00FF0000L
>+//MMSCH_DB_SRAM_OFFSET
>+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT                                                           0x2
>+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT                                                          0x10
>+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT                                                 0x18
>+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK                                                             0x00001FFCL
>+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK                                                            0x00FF0000L
>+#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK                                                   0xFF000000L
>+//MMSCH_CTX_SRAM_OFFSET
>+#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT                                                         0x2
>+#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT                                                           0x10
>+#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK                                                           0x00001FFCL
>+#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK                                                             0xFFFF0000L
>+//MMSCH_CTL
>+#define MMSCH_CTL__P_RUNSTALL__SHIFT                                                                          0x0
>+#define MMSCH_CTL__P_RESET__SHIFT                                                                             0x1
>+#define MMSCH_CTL__VFID_FIFO_EN__SHIFT                                                                        0x4
>+#define MMSCH_CTL__P_LOCK__SHIFT                                                                              0x1f
>+#define MMSCH_CTL__P_RUNSTALL_MASK                                                                            0x00000001L
>+#define MMSCH_CTL__P_RESET_MASK                                                                               0x00000002L
>+#define MMSCH_CTL__VFID_FIFO_EN_MASK                                                                          0x00000010L
>+#define MMSCH_CTL__P_LOCK_MASK                                                                                0x80000000L
>+//MMSCH_INTR
>+#define MMSCH_INTR__INTR__SHIFT                                                                               0x0
>+#define MMSCH_INTR__INTR_MASK                                                                                 0x00001FFFL
>+//MMSCH_INTR_ACK
>+#define MMSCH_INTR_ACK__INTR__SHIFT                                                                           0x0
>+#define MMSCH_INTR_ACK__INTR_MASK                                                                             0x00001FFFL
>+//MMSCH_INTR_STATUS
>+#define MMSCH_INTR_STATUS__INTR__SHIFT                                                                        0x0
>+#define MMSCH_INTR_STATUS__INTR_MASK                                                                          0x00001FFFL
>+//MMSCH_VF_VMID
>+#define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT                                                                     0x0
>+#define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT                                                                   0x5
>+#define MMSCH_VF_VMID__VF_CTX_VMID_MASK                                                                       0x0000001FL
>+#define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK                                                                     0x000003E0L
>+//MMSCH_VF_CTX_ADDR_LO
>+#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT                                                           0x6
>+#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK                                                             0xFFFFFFC0L
>+//MMSCH_VF_CTX_ADDR_HI
>+#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT                                                           0x0
>+#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK                                                             0xFFFFFFFFL
>+//MMSCH_VF_CTX_SIZE
>+#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT                                                                 0x0
>+#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK                                                                   0xFFFFFFFFL
>+//MMSCH_VF_GPCOM_ADDR_LO
>+#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT                                                       0x6
>+#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK                                                         0xFFFFFFC0L
>+//MMSCH_VF_GPCOM_ADDR_HI
>+#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT                                                       0x0
>+#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK                                                         0xFFFFFFFFL
>+//MMSCH_VF_GPCOM_SIZE
>+#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT                                                             0x0
>+#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK                                                               0xFFFFFFFFL
>+//MMSCH_VF_MAILBOX_HOST
>+#define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT                                                                    0x0
>+#define MMSCH_VF_MAILBOX_HOST__DATA_MASK                                                                      0xFFFFFFFFL
>+//MMSCH_VF_MAILBOX_RESP
>+#define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT                                                                    0x0
>+#define MMSCH_VF_MAILBOX_RESP__RESP_MASK                                                                      0xFFFFFFFFL
>+//MMSCH_VF_MAILBOX_0
>+#define MMSCH_VF_MAILBOX_0__DATA__SHIFT                                                                       0x0
>+#define MMSCH_VF_MAILBOX_0__DATA_MASK                                                                         0xFFFFFFFFL
>+//MMSCH_VF_MAILBOX_0_RESP
>+#define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT                                                                  0x0
>+#define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK                                                                    0xFFFFFFFFL
>+//MMSCH_VF_MAILBOX_1
>+#define MMSCH_VF_MAILBOX_1__DATA__SHIFT                                                                       0x0
>+#define MMSCH_VF_MAILBOX_1__DATA_MASK                                                                         0xFFFFFFFFL
>+//MMSCH_VF_MAILBOX_1_RESP
>+#define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT                                                                  0x0
>+#define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK                                                                    0xFFFFFFFFL
>+//MMSCH_CNTL
>+#define MMSCH_CNTL__CLK_EN__SHIFT                                                                             0x0
>+#define MMSCH_CNTL__ED_ENABLE__SHIFT                                                                          0x1
>+#define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT                                                                      0x5
>+#define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT                                                                 0x9
>+#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT                                                              0xa
>+#define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT                                                                    0x14
>+#define MMSCH_CNTL__TIMEOUT_DIS__SHIFT                                                                        0x1c
>+#define MMSCH_CNTL__CLK_EN_MASK                                                                               0x00000001L
>+#define MMSCH_CNTL__ED_ENABLE_MASK                                                                            0x00000002L
>+#define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK                                                                        0x000001E0L
>+#define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK                                                                   0x00000200L
>+#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK                                                                0x00000400L
>+#define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK                                                                      0x0FF00000L
>+#define MMSCH_CNTL__TIMEOUT_DIS_MASK                                                                          0x10000000L
>+//MMSCH_NONCACHE_OFFSET0
>+#define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT                                                                 0x0
>+#define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK                                                                   0x0FFFFFFFL
>+//MMSCH_NONCACHE_SIZE0
>+#define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT                                                                     0x0
>+#define MMSCH_NONCACHE_SIZE0__SIZE_MASK                                                                       0x00FFFFFFL
>+//MMSCH_NONCACHE_OFFSET1
>+#define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT                                                                 0x0
>+#define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK                                                                   0x0FFFFFFFL
>+//MMSCH_NONCACHE_SIZE1
>+#define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT                                                                     0x0
>+#define MMSCH_NONCACHE_SIZE1__SIZE_MASK                                                                       0x00FFFFFFL
>+//MMSCH_PROC_STATE1
>+#define MMSCH_PROC_STATE1__PC__SHIFT                                                                          0x0
>+#define MMSCH_PROC_STATE1__PC_MASK                                                                            0xFFFFFFFFL
>+//MMSCH_LAST_MC_ADDR
>+#define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT                                                                    0x0
>+#define MMSCH_LAST_MC_ADDR__RW__SHIFT                                                                         0x1f
>+#define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK                                                                      0x0FFFFFFFL
>+#define MMSCH_LAST_MC_ADDR__RW_MASK                                                                           0x80000000L
>+//MMSCH_LAST_MEM_ACCESS_HI
>+#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT                                                             0x0
>+#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT                                                            0x8
>+#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT                                                            0xc
>+#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK                                                               0x00000007L
>+#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK                                                              0x00000700L
>+#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK                                                              0x00007000L
>+//MMSCH_LAST_MEM_ACCESS_LO
>+#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT                                                            0x0
>+#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK                                                              0xFFFFFFFFL
>+//MMSCH_IOV_ACTIVE_FCN_ID
>+#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT                                                          0x0
>+#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT                                                          0x1f
>+#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK                                                            0x0000001FL
>+#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK                                                            0x80000000L
>+//MMSCH_SCRATCH_0
>+#define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT                                                                     0x0
>+#define MMSCH_SCRATCH_0__SCRATCH_0_MASK                                                                       0xFFFFFFFFL
>+//MMSCH_SCRATCH_1
>+#define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT                                                                     0x0
>+#define MMSCH_SCRATCH_1__SCRATCH_1_MASK                                                                       0xFFFFFFFFL
>+//MMSCH_GPUIOV_SCH_BLOCK_0
>+#define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT                                                                   0x0
>+#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT                                                              0x4
>+#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT                                                                 0x8
>+#define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK                                                                     0x0000000FL
>+#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK                                                                0x000000F0L
>+#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK                                                                   0x0000FF00L
>+//MMSCH_GPUIOV_CMD_CONTROL_0
>+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT                                                           0x0
>+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT                                                        0x4
>+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT                                                0x5
>+#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT                                                    0x6
>+#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT                                                        0x8
>+#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT                                                   0x10
>+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK                                                             0x0000000FL
>+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK                                                          0x00000010L
>+#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK                                                  0x00000020L
>+#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK                                                      0x00000040L
>+#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK                                                          0x0000FF00L
>+#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK                                                     0x00FF0000L
>+//MMSCH_GPUIOV_CMD_STATUS_0
>+#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT                                                          0x0
>+#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK                                                            0x0000000FL
>+//MMSCH_GPUIOV_VM_BUSY_STATUS_0
>+#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT                                                            0x0
>+#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK                                                              0xFFFFFFFFL
>+//MMSCH_GPUIOV_ACTIVE_FCNS_0
>+#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT                                                        0x0
>+#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK                                                          0xFFFFFFFFL
>+//MMSCH_GPUIOV_ACTIVE_FCN_ID_0
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT                                                               0x0
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT                                                        0x8
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK                                                                 0x000000FFL
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK                                                          0x00000F00L
>+//MMSCH_GPUIOV_DW6_0
>+#define MMSCH_GPUIOV_DW6_0__DATA__SHIFT                                                                       0x0
>+#define MMSCH_GPUIOV_DW6_0__DATA_MASK                                                                         0xFFFFFFFFL
>+//MMSCH_GPUIOV_DW7_0
>+#define MMSCH_GPUIOV_DW7_0__DATA__SHIFT                                                                       0x0
>+#define MMSCH_GPUIOV_DW7_0__DATA_MASK                                                                         0xFFFFFFFFL
>+//MMSCH_GPUIOV_DW8_0
>+#define MMSCH_GPUIOV_DW8_0__DATA__SHIFT                                                                       0x0
>+#define MMSCH_GPUIOV_DW8_0__DATA_MASK                                                                         0xFFFFFFFFL
>+//MMSCH_GPUIOV_SCH_BLOCK_1
>+#define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT                                                                   0x0
>+#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT                                                              0x4
>+#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT                                                                 0x8
>+#define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK                                                                     0x0000000FL
>+#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK                                                                0x000000F0L
>+#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK                                                                   0x0000FF00L
>+//MMSCH_GPUIOV_CMD_CONTROL_1
>+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT                                                           0x0
>+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT                                                        0x4
>+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT                                                0x5
>+#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT                                                    0x6
>+#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT                                                        0x8
>+#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT                                                   0x10
>+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK                                                             0x0000000FL
>+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK                                                          0x00000010L
>+#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK                                                  0x00000020L
>+#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK                                                      0x00000040L
>+#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK                                                          0x0000FF00L
>+#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK                                                     0x00FF0000L
>+//MMSCH_GPUIOV_CMD_STATUS_1
>+#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT                                                          0x0
>+#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK                                                            0x0000000FL
>+//MMSCH_GPUIOV_VM_BUSY_STATUS_1
>+#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT                                                            0x0
>+#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK                                                              0xFFFFFFFFL
>+//MMSCH_GPUIOV_ACTIVE_FCNS_1
>+#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT                                                        0x0
>+#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK                                                          0xFFFFFFFFL
>+//MMSCH_GPUIOV_ACTIVE_FCN_ID_1
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT                                                               0x0
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT                                                        0x8
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK                                                                 0x000000FFL
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK                                                          0x00000F00L
>+//MMSCH_GPUIOV_DW6_1
>+#define MMSCH_GPUIOV_DW6_1__DATA__SHIFT                                                                       0x0
>+#define MMSCH_GPUIOV_DW6_1__DATA_MASK                                                                         0xFFFFFFFFL
>+//MMSCH_GPUIOV_DW7_1
>+#define MMSCH_GPUIOV_DW7_1__DATA__SHIFT                                                                       0x0
>+#define MMSCH_GPUIOV_DW7_1__DATA_MASK                                                                         0xFFFFFFFFL
>+//MMSCH_GPUIOV_DW8_1
>+#define MMSCH_GPUIOV_DW8_1__DATA__SHIFT                                                                       0x0
>+#define MMSCH_GPUIOV_DW8_1__DATA_MASK                                                                         0xFFFFFFFFL
>+//MMSCH_GPUIOV_CNTXT
>+#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT                                                                 0x0
>+#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT                                                             0x7
>+#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT                                                               0xa
>+#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK                                                                   0x0000007FL
>+#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK                                                               0x00000080L
>+#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK                                                                 0xFFFFFC00L
>+//MMSCH_SCRATCH_2
>+#define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT                                                                     0x0
>+#define MMSCH_SCRATCH_2__SCRATCH_2_MASK                                                                       0xFFFFFFFFL
>+//MMSCH_SCRATCH_3
>+#define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT                                                                     0x0
>+#define MMSCH_SCRATCH_3__SCRATCH_3_MASK                                                                       0xFFFFFFFFL
>+//MMSCH_SCRATCH_4
>+#define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT                                                                     0x0
>+#define MMSCH_SCRATCH_4__SCRATCH_4_MASK                                                                       0xFFFFFFFFL
>+//MMSCH_SCRATCH_5
>+#define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT                                                                     0x0
>+#define MMSCH_SCRATCH_5__SCRATCH_5_MASK                                                                       0xFFFFFFFFL
>+//MMSCH_SCRATCH_6
>+#define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT                                                                     0x0
>+#define MMSCH_SCRATCH_6__SCRATCH_6_MASK                                                                       0xFFFFFFFFL
>+//MMSCH_SCRATCH_7
>+#define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT                                                                     0x0
>+#define MMSCH_SCRATCH_7__SCRATCH_7_MASK                                                                       0xFFFFFFFFL
>+//MMSCH_VFID_FIFO_HEAD_0
>+#define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT                                                                   0x0
>+#define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK                                                                     0x0000003FL
>+//MMSCH_VFID_FIFO_TAIL_0
>+#define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT                                                                   0x0
>+#define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK                                                                     0x0000003FL
>+//MMSCH_VFID_FIFO_HEAD_1
>+#define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT                                                                   0x0
>+#define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK                                                                     0x0000003FL
>+//MMSCH_VFID_FIFO_TAIL_1
>+#define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT                                                                   0x0
>+#define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK                                                                     0x0000003FL
>+//MMSCH_NACK_STATUS
>+#define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT                                                              0x0
>+#define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT                                                              0x2
>+#define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK                                                                0x00000003L
>+#define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK                                                                0x0000000CL
>+//MMSCH_VF_MAILBOX0_DATA
>+#define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT                                                                   0x0
>+#define MMSCH_VF_MAILBOX0_DATA__DATA_MASK                                                                     0xFFFFFFFFL
>+//MMSCH_VF_MAILBOX1_DATA
>+#define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT                                                                   0x0
>+#define MMSCH_VF_MAILBOX1_DATA__DATA_MASK                                                                     0xFFFFFFFFL
>+//MMSCH_GPUIOV_SCH_BLOCK_IP_0
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT                                                                0x0
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT                                                           0x4
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT                                                              0x8
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK                                                                  0x0000000FL
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK                                                             0x000000F0L
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK                                                                0x0000FF00L
>+//MMSCH_GPUIOV_CMD_STATUS_IP_0
>+#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT                                                       0x0
>+#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK                                                         0x0000000FL
>+//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT                                                            0x0
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT                                                     0x8
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK                                                              0x000000FFL
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK                                                       0x00000F00L
>+//MMSCH_GPUIOV_SCH_BLOCK_IP_1
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT                                                                0x0
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT                                                           0x4
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT                                                              0x8
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK                                                                  0x0000000FL
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK                                                             0x000000F0L
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK                                                                0x0000FF00L
>+//MMSCH_GPUIOV_CMD_STATUS_IP_1
>+#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT                                                       0x0
>+#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK                                                         0x0000000FL
>+//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT                                                            0x0
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT                                                     0x8
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK                                                              0x000000FFL
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK                                                       0x00000F00L
>+//MMSCH_GPUIOV_CNTXT_IP
>+#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT                                                              0x0
>+#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT                                                          0x7
>+#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK                                                                0x0000007FL
>+#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK                                                            0x00000080L
>+//MMSCH_GPUIOV_SCH_BLOCK_2
>+#define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT                                                                   0x0
>+#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT                                                              0x4
>+#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT                                                                 0x8
>+#define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK                                                                     0x0000000FL
>+#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK                                                                0x000000F0L
>+#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK                                                                   0x0000FF00L
>+//MMSCH_GPUIOV_CMD_CONTROL_2
>+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT                                                           0x0
>+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT                                                        0x4
>+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT                                                0x5
>+#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT                                                    0x6
>+#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT                                                        0x8
>+#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT                                                   0x10
>+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK                                                             0x0000000FL
>+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK                                                          0x00000010L
>+#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK                                                  0x00000020L
>+#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK                                                      0x00000040L
>+#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK                                                          0x0000FF00L
>+#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK                                                     0x00FF0000L
>+//MMSCH_GPUIOV_CMD_STATUS_2
>+#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT                                                          0x0
>+#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK                                                            0x0000000FL
>+//MMSCH_GPUIOV_VM_BUSY_STATUS_2
>+#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT                                                            0x0
>+#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK                                                              0xFFFFFFFFL
>+//MMSCH_GPUIOV_ACTIVE_FCNS_2
>+#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT                                                        0x0
>+#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK                                                          0xFFFFFFFFL
>+//MMSCH_GPUIOV_ACTIVE_FCN_ID_2
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT                                                               0x0
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT                                                        0x8
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK                                                                 0x000000FFL
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK                                                          0x00000F00L
>+//MMSCH_GPUIOV_DW6_2
>+#define MMSCH_GPUIOV_DW6_2__DATA__SHIFT                                                                       0x0
>+#define MMSCH_GPUIOV_DW6_2__DATA_MASK                                                                         0xFFFFFFFFL
>+//MMSCH_GPUIOV_DW7_2
>+#define MMSCH_GPUIOV_DW7_2__DATA__SHIFT                                                                       0x0
>+#define MMSCH_GPUIOV_DW7_2__DATA_MASK                                                                         0xFFFFFFFFL
>+//MMSCH_GPUIOV_DW8_2
>+#define MMSCH_GPUIOV_DW8_2__DATA__SHIFT                                                                       0x0
>+#define MMSCH_GPUIOV_DW8_2__DATA_MASK                                                                         0xFFFFFFFFL
>+//MMSCH_GPUIOV_SCH_BLOCK_IP_2
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT                                                                0x0
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT                                                           0x4
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT                                                              0x8
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK                                                                  0x0000000FL
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK                                                             0x000000F0L
>+#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK                                                                0x0000FF00L
>+//MMSCH_GPUIOV_CMD_STATUS_IP_2
>+#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT                                                       0x0
>+#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK                                                         0x0000000FL
>+//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT                                                            0x0
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT                                                     0x8
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK                                                              0x000000FFL
>+#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK                                                       0x00000F00L
>+//MMSCH_VFID_FIFO_HEAD_2
>+#define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT                                                                   0x0
>+#define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK                                                                     0x0000003FL
>+//MMSCH_VFID_FIFO_TAIL_2
>+#define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT                                                                   0x0
>+#define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK                                                                     0x0000003FL
>+//MMSCH_VM_BUSY_STATUS_0
>+#define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT                                                                   0x0
>+#define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK                                                                     0xFFFFFFFFL
>+//MMSCH_VM_BUSY_STATUS_1
>+#define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT                                                                   0x0
>+#define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK                                                                     0xFFFFFFFFL
>+//MMSCH_VM_BUSY_STATUS_2
>+#define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT                                                                   0x0
>+#define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK                                                                     0xFFFFFFFFL
>+
>+
>+// addressBlock: uvd0_jpegnpdec
>+//UVD_JPEG_CNTL
>+#define UVD_JPEG_CNTL__REQUEST_EN__SHIFT                                                                      0x1
>+#define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT                                                                      0x2
>+#define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT                                                                   0x3
>+#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT                                                               0x4
>+#define UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT                                                                     0x8
>+#define UVD_JPEG_CNTL__REQUEST_EN_MASK                                                                        0x00000002L
>+#define UVD_JPEG_CNTL__ERR_RST_EN_MASK                                                                        0x00000004L
>+#define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK                                                                     0x00000008L
>+#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK                                                                 0x00000010L
>+#define UVD_JPEG_CNTL__DBG_MUX_SEL_MASK                                                                       0x00007F00L
>+//UVD_JPEG_RB_BASE
>+#define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT                                                                  0x0
>+#define UVD_JPEG_RB_BASE__RB_BASE__SHIFT                                                                      0x6
>+#define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK                                                                    0x0000003FL
>+#define UVD_JPEG_RB_BASE__RB_BASE_MASK                                                                        0xFFFFFFC0L
>+//UVD_JPEG_RB_WPTR
>+#define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT                                                                      0x4
>+#define UVD_JPEG_RB_WPTR__RB_WPTR_MASK                                                                        0x3FFFFFF0L
>+//UVD_JPEG_RB_RPTR
>+#define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT                                                                      0x4
>+#define UVD_JPEG_RB_RPTR__RB_RPTR_MASK                                                                        0x3FFFFFF0L
>+//UVD_JPEG_RB_SIZE
>+#define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT                                                                      0x4
>+#define UVD_JPEG_RB_SIZE__RB_SIZE_MASK                                                                        0x3FFFFFF0L
>+//UVD_JPEG_DEC_SCRATCH0
>+#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT                                                                0x0
>+#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK                                                                  0xFFFFFFFFL
>+//UVD_JPEG_INT_EN
>+#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT                                                            0x0
>+#define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT                                                                  0x1
>+#define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT                                                                  0x2
>+#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT                                                          0x6
>+#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT                                                    0x7
>+#define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT                                                                    0x8
>+#define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT                                                                    0x9
>+#define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT                                                                    0xa
>+#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT                                                                 0xb
>+#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT                                                                0xc
>+#define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT                                                                 0xd
>+#define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT                                                                    0xe
>+#define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT                                                                0xf
>+#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK                                                              0x00000001L
>+#define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK                                                                    0x00000002L
>+#define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK                                                                    0x00000004L
>+#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK                                                            0x00000040L
>+#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK                                                      0x00000080L
>+#define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK                                                                      0x00000100L
>+#define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK                                                                      0x00000200L
>+#define UVD_JPEG_INT_EN__RST_ERR_EN_MASK                                                                      0x00000400L
>+#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK                                                                   0x00000800L
>+#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK                                                                  0x00001000L
>+#define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK                                                                   0x00002000L
>+#define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK                                                                      0x00004000L
>+#define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK                                                                  0x00008000L
>+//UVD_JPEG_INT_STAT
>+#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT                                                         0x0
>+#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT                                                               0x1
>+#define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT                                                               0x2
>+#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT                                                       0x6
>+#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT                                                 0x7
>+#define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT                                                                 0x8
>+#define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT                                                                 0x9
>+#define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT                                                                 0xa
>+#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT                                                              0xb
>+#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT                                                             0xc
>+#define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT                                                              0xd
>+#define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT                                                                 0xe
>+#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT                                                             0xf
>+#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK                                                           0x00000001L
>+#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK                                                                 0x00000002L
>+#define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK                                                                 0x00000004L
>+#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK                                                         0x00000040L
>+#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK                                                   0x00000080L
>+#define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK                                                                   0x00000100L
>+#define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK                                                                   0x00000200L
>+#define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK                                                                   0x00000400L
>+#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK                                                                0x00000800L
>+#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK                                                               0x00001000L
>+#define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK                                                                0x00002000L
>+#define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK                                                                   0x00004000L
>+#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK                                                               0x00008000L
>+//UVD_JPEG_PITCH
>+#define UVD_JPEG_PITCH__PITCH__SHIFT                                                                          0x0
>+#define UVD_JPEG_PITCH__PITCH_MASK                                                                            0xFFFFFFFFL
>+//UVD_JPEG_UV_PITCH
>+#define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT                                                                    0x0
>+#define UVD_JPEG_UV_PITCH__UV_PITCH_MASK                                                                      0xFFFFFFFFL
>+//JPEG_DEC_Y_GFX8_TILING_SURFACE
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT                                                     0x0
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT                                                    0x2
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT                                              0x4
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT                                                      0x6
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT                                                    0x8
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT                                                     0xd
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT                                                     0x10
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK                                                       0x00000003L
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK                                                      0x0000000CL
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK                                                0x00000030L
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK                                                        0x000000C0L
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK                                                      0x00001F00L
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK                                                       0x0000E000L
>+#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK                                                       0x000F0000L
>+//JPEG_DEC_UV_GFX8_TILING_SURFACE
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT                                                    0x0
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT                                                   0x2
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT                                             0x4
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT                                                     0x6
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT                                                   0x8
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT                                                    0xd
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT                                                    0x10
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK                                                      0x00000003L
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK                                                     0x0000000CL
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK                                               0x00000030L
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK                                                       0x000000C0L
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK                                                     0x00001F00L
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK                                                      0x0000E000L
>+#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK                                                      0x000F0000L
>+//JPEG_DEC_GFX8_ADDR_CONFIG
>+#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                0x4
>+#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                  0x00000070L
>+//JPEG_DEC_Y_GFX10_TILING_SURFACE
>+#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT                                                  0x0
>+#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK                                                    0x0000001FL
>+//JPEG_DEC_UV_GFX10_TILING_SURFACE
>+#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT                                                 0x0
>+#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK                                                   0x0000001FL
>+//JPEG_DEC_GFX10_ADDR_CONFIG
>+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT                                                          0x0
>+#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                               0x3
>+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT                                                          0xc
>+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                 0x13
>+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK                                                            0x00000007L
>+#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                 0x00000038L
>+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK                                                            0x00007000L
>+#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                   0x00180000L
>+//JPEG_DEC_ADDR_MODE
>+#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT                                                                0x0
>+#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT                                                               0x2
>+#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT                                                               0xc
>+#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK                                                                  0x00000003L
>+#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK                                                                 0x0000000CL
>+#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK                                                                 0x00007000L
>+//UVD_JPEG_OUTPUT_XY
>+//UVD_JPEG_GPCOM_CMD
>+#define UVD_JPEG_GPCOM_CMD__CMD__SHIFT                                                                        0x1
>+#define UVD_JPEG_GPCOM_CMD__CMD_MASK                                                                          0x0000000EL
>+//UVD_JPEG_GPCOM_DATA0
>+#define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT                                                                    0x0
>+#define UVD_JPEG_GPCOM_DATA0__DATA0_MASK                                                                      0xFFFFFFFFL
>+//UVD_JPEG_GPCOM_DATA1
>+#define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT                                                                    0x0
>+#define UVD_JPEG_GPCOM_DATA1__DATA1_MASK                                                                      0xFFFFFFFFL
>+//UVD_JPEG_SCRATCH1
>+#define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT                                                                    0x0
>+#define UVD_JPEG_SCRATCH1__SCRATCH1_MASK                                                                      0xFFFFFFFFL
>+//UVD_JPEG_DEC_SOFT_RST
>+#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT                                                              0x0
>+#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT                                                            0x10
>+#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK                                                                0x00000001L
>+#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK                                                              0x00010000L
>+
>+
>+// addressBlock: uvd0_uvd_jpeg_enc_dec
>+//UVD_JPEG_ENC_INT_EN
>+#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT                                                      0x0
>+#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT                                                      0x1
>+#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT                                                         0x2
>+#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT                                                         0x3
>+#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT                                                         0x4
>+#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT                                                     0x5
>+#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT                                                          0x6
>+#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK                                                        0x00000001L
>+#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK                                                        0x00000002L
>+#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK                                                           0x00000004L
>+#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK                                                           0x00000008L
>+#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK                                                           0x00000010L
>+#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK                                                       0x00000020L
>+#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK                                                            0x00000040L
>+//UVD_JPEG_ENC_INT_STATUS
>+#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT                                                  0x0
>+#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT                                                  0x1
>+#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT                                                     0x2
>+#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT                                                     0x3
>+#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT                                                     0x4
>+#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT                                                 0x5
>+#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT                                                      0x6
>+#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK                                                    0x00000001L
>+#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK                                                    0x00000002L
>+#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK                                                       0x00000004L
>+#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK                                                       0x00000008L
>+#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK                                                       0x00000010L
>+#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK                                                   0x00000020L
>+#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK                                                        0x00000040L
>+//UVD_JPEG_ENC_ENGINE_CNTL
>+#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT                                                     0x0
>+#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT                                         0x1
>+#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT                                                            0x2
>+#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT                                                            0x3
>+#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT                                                           0x4
>+#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT                                                  0x9
>+#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK                                                       0x00000001L
>+#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK                                           0x00000002L
>+#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK                                                              0x00000004L
>+#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK                                                              0x00000008L
>+#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK                                                             0x00000010L
>+#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK                                                    0x00000200L
>+//UVD_JPEG_ENC_SCRATCH1
>+#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT                                                                0x0
>+#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK                                                                  0xFFFFFFFFL
>+
>+
>+// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec
>+//UVD_JPEG_ENC_STATUS
>+#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT                                                            0x0
>+#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT                                                            0x1
>+#define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT                                                                 0x2
>+#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT                                                               0x3
>+#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK                                                              0x00000001L
>+#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK                                                              0x00000002L
>+#define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK                                                                   0x00000004L
>+#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK                                                                 0x00000008L
>+//UVD_JPEG_ENC_PITCH
>+#define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT                                                                    0x0
>+#define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT                                                                   0x10
>+#define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK                                                                      0x00000FFFL
>+#define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK                                                                     0x0FFF0000L
>+//UVD_JPEG_ENC_LUMA_BASE
>+#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT                                                              0x0
>+#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK                                                                0xFFFFFFFFL
>+//UVD_JPEG_ENC_CHROMAU_BASE
>+#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT                                                        0x0
>+#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK                                                          0xFFFFFFFFL
>+//UVD_JPEG_ENC_CHROMAV_BASE
>+#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT                                                        0x0
>+#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK                                                          0xFFFFFFFFL
>+//JPEG_ENC_Y_GFX10_TILING_SURFACE
>+#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT                                                  0x0
>+#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK                                                    0x0000001FL
>+//JPEG_ENC_UV_GFX10_TILING_SURFACE
>+#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT                                                 0x0
>+#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK                                                   0x0000001FL
>+//JPEG_ENC_GFX10_ADDR_CONFIG
>+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT                                                          0x0
>+#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                               0x3
>+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT                                                          0xc
>+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                 0x13
>+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK                                                            0x00000007L
>+#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                 0x00000038L
>+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK                                                            0x00007000L
>+#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                   0x00180000L
>+//JPEG_ENC_ADDR_MODE
>+#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT                                                                0x0
>+#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT                                                               0x2
>+#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT                                                               0xc
>+#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK                                                                  0x00000003L
>+#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK                                                                 0x0000000CL
>+#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK                                                                 0x00007000L
>+//UVD_JPEG_ENC_GPCOM_CMD
>+#define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT                                                                    0x1
>+#define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK                                                                      0x0000000EL
>+//UVD_JPEG_ENC_GPCOM_DATA0
>+#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT                                                                0x0
>+#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK                                                                  0xFFFFFFFFL
>+//UVD_JPEG_ENC_GPCOM_DATA1
>+#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT                                                                0x0
>+#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK                                                                  0xFFFFFFFFL
>+//UVD_JPEG_ENC_CGC_CNTL
>+#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT                                                                  0x0
>+#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK                                                                    0x00000001L
>+//UVD_JPEG_ENC_SCRATCH0
>+#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT                                                                0x0
>+#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK                                                                  0xFFFFFFFFL
>+//UVD_JPEG_ENC_SOFT_RST
>+#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT                                                                0x0
>+#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT                                                            0x10
>+#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK                                                                  0x00000001L
>+#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK                                                              0x00010000L
>+
>+
>+// addressBlock: uvd0_uvd_jrbc_dec
>+//UVD_JRBC_RB_WPTR
>+#define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT                                                                      0x4
>+#define UVD_JRBC_RB_WPTR__RB_WPTR_MASK                                                                        0x007FFFF0L
>+//UVD_JRBC_RB_CNTL
>+#define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT                                                                  0x0
>+#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT                                                                0x1
>+#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT                                                           0x4
>+#define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK                                                                    0x00000001L
>+#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK                                                                  0x00000002L
>+#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK                                                             0x0007FFF0L
>+//UVD_JRBC_IB_SIZE
>+#define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT                                                                      0x4
>+#define UVD_JRBC_IB_SIZE__IB_SIZE_MASK                                                                        0x007FFFF0L
>+//UVD_JRBC_URGENT_CNTL
>+#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT                                               0x0
>+#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK                                                 0x00000003L
>+//UVD_JRBC_RB_REF_DATA
>+#define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT                                                                 0x0
>+#define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK                                                                   0xFFFFFFFFL
>+//UVD_JRBC_RB_COND_RD_TIMER
>+#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT                                                     0x0
>+#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT                                                  0x10
>+#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT                                                  0x18
>+#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT                                                      0x19
>+#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK                                                       0x0000FFFFL
>+#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK                                                    0x00FF0000L
>+#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK                                                    0x01000000L
>+#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK                                                        0x02000000L
>+//UVD_JRBC_SOFT_RESET
>+#define UVD_JRBC_SOFT_RESET__RESET__SHIFT                                                                     0x0
>+#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT                                                         0x11
>+#define UVD_JRBC_SOFT_RESET__RESET_MASK                                                                       0x00000001L
>+#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK                                                           0x00020000L
>+//UVD_JRBC_STATUS
>+#define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT                                                                   0x0
>+#define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT                                                                   0x1
>+#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT                                                                0x2
>+#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT                                                        0x3
>+#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT                                                             0x4
>+#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT                                                             0x5
>+#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT                                                                0x6
>+#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT                                                        0x7
>+#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT                                                             0x8
>+#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT                                                             0x9
>+#define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT                                                                0xa
>+#define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT                                                                0xb
>+#define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT                                                                0xc
>+#define UVD_JRBC_STATUS__INT_EN__SHIFT                                                                        0x10
>+#define UVD_JRBC_STATUS__INT_ACK__SHIFT                                                                       0x11
>+#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK                                                                     0x00000001L
>+#define UVD_JRBC_STATUS__IB_JOB_DONE_MASK                                                                     0x00000002L
>+#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK                                                                  0x00000004L
>+#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK                                                          0x00000008L
>+#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK                                                               0x00000010L
>+#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK                                                               0x00000020L
>+#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK                                                                  0x00000040L
>+#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK                                                          0x00000080L
>+#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK                                                               0x00000100L
>+#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK                                                               0x00000200L
>+#define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK                                                                  0x00000400L
>+#define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK                                                                  0x00000800L
>+#define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK                                                                  0x00001000L
>+#define UVD_JRBC_STATUS__INT_EN_MASK                                                                          0x00010000L
>+#define UVD_JRBC_STATUS__INT_ACK_MASK                                                                         0x00020000L
>+//UVD_JRBC_RB_RPTR
>+#define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT                                                                      0x4
>+#define UVD_JRBC_RB_RPTR__RB_RPTR_MASK                                                                        0x007FFFF0L
>+//UVD_JRBC_RB_BUF_STATUS
>+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT                                                           0x0
>+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT                                                         0x10
>+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT                                                         0x18
>+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK                                                             0x0000FFFFL
>+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK                                                           0x000F0000L
>+#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK                                                           0x03000000L
>+//UVD_JRBC_IB_BUF_STATUS
>+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT                                                           0x0
>+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT                                                         0x10
>+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT                                                         0x18
>+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK                                                             0x0000FFFFL
>+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK                                                           0x000F0000L
>+#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK                                                           0x03000000L
>+//UVD_JRBC_IB_SIZE_UPDATE
>+#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT                                                        0x4
>+#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK                                                          0x007FFFF0L
>+//UVD_JRBC_IB_COND_RD_TIMER
>+#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT                                                     0x0
>+#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT                                                  0x10
>+#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT                                                  0x18
>+#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT                                                      0x19
>+#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK                                                       0x0000FFFFL
>+#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK                                                    0x00FF0000L
>+#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK                                                    0x01000000L
>+#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK                                                        0x02000000L
>+//UVD_JRBC_IB_REF_DATA
>+#define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT                                                                 0x0
>+#define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK                                                                   0xFFFFFFFFL
>+//UVD_JPEG_PREEMPT_CMD
>+#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT                                                               0x0
>+#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT                                                       0x1
>+#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT                                                        0x2
>+#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK                                                                 0x00000001L
>+#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK                                                         0x00000002L
>+#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK                                                          0x00000004L
>+//UVD_JPEG_PREEMPT_FENCE_DATA0
>+#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT                                              0x0
>+#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK                                                0xFFFFFFFFL
>+//UVD_JPEG_PREEMPT_FENCE_DATA1
>+#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT                                              0x0
>+#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK                                                0xFFFFFFFFL
>+//UVD_JRBC_RB_SIZE
>+#define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT                                                                      0x4
>+#define UVD_JRBC_RB_SIZE__RB_SIZE_MASK                                                                        0x00FFFFF0L
>+//UVD_JRBC_SCRATCH0
>+#define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT                                                                    0x0
>+#define UVD_JRBC_SCRATCH0__SCRATCH0_MASK                                                                      0xFFFFFFFFL
>+
>+
>+// addressBlock: uvd0_uvd_jrbc_enc_dec
>+//UVD_JRBC_ENC_RB_WPTR
>+#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT                                                                  0x4
>+#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK                                                                    0x007FFFF0L
>+//UVD_JRBC_ENC_RB_CNTL
>+#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT                                                              0x0
>+#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT                                                            0x1
>+#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT                                                       0x4
>+#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK                                                                0x00000001L
>+#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK                                                              0x00000002L
>+#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK                                                         0x0007FFF0L
>+//UVD_JRBC_ENC_IB_SIZE
>+#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT                                                                  0x4
>+#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK                                                                    0x007FFFF0L
>+//UVD_JRBC_ENC_URGENT_CNTL
>+#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT                                           0x0
>+#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK                                             0x00000003L
>+//UVD_JRBC_ENC_RB_REF_DATA
>+#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT                                                             0x0
>+#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK                                                               0xFFFFFFFFL
>+//UVD_JRBC_ENC_RB_COND_RD_TIMER
>+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT                                                 0x0
>+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT                                              0x10
>+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT                                              0x18
>+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT                                                  0x19
>+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK                                                   0x0000FFFFL
>+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK                                                0x00FF0000L
>+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK                                                0x01000000L
>+#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK                                                    0x02000000L
>+//UVD_JRBC_ENC_SOFT_RESET
>+#define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT                                                                 0x0
>+#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT                                                     0x11
>+#define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK                                                                   0x00000001L
>+#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK                                                       0x00020000L
>+//UVD_JRBC_ENC_STATUS
>+#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT                                                               0x0
>+#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT                                                               0x1
>+#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT                                                            0x2
>+#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT                                                    0x3
>+#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT                                                         0x4
>+#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT                                                         0x5
>+#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT                                                            0x6
>+#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT                                                    0x7
>+#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT                                                         0x8
>+#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT                                                         0x9
>+#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT                                                            0xa
>+#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT                                                            0xb
>+#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT                                                            0xc
>+#define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT                                                                    0x10
>+#define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT                                                                   0x11
>+#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK                                                                 0x00000001L
>+#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK                                                                 0x00000002L
>+#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK                                                              0x00000004L
>+#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK                                                      0x00000008L
>+#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK                                                           0x00000010L
>+#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK                                                           0x00000020L
>+#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK                                                              0x00000040L
>+#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK                                                      0x00000080L
>+#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK                                                           0x00000100L
>+#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK                                                           0x00000200L
>+#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK                                                              0x00000400L
>+#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK                                                              0x00000800L
>+#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK                                                              0x00001000L
>+#define UVD_JRBC_ENC_STATUS__INT_EN_MASK                                                                      0x00010000L
>+#define UVD_JRBC_ENC_STATUS__INT_ACK_MASK                                                                     0x00020000L
>+//UVD_JRBC_ENC_RB_RPTR
>+#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT                                                                  0x4
>+#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK                                                                    0x007FFFF0L
>+//UVD_JRBC_ENC_RB_BUF_STATUS
>+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT                                                       0x0
>+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT                                                     0x10
>+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT                                                     0x18
>+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK                                                         0x0000FFFFL
>+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK                                                       0x000F0000L
>+#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK                                                       0x03000000L
>+//UVD_JRBC_ENC_IB_BUF_STATUS
>+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT                                                       0x0
>+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT                                                     0x10
>+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT                                                     0x18
>+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK                                                         0x0000FFFFL
>+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK                                                       0x000F0000L
>+#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK                                                       0x03000000L
>+//UVD_JRBC_ENC_IB_SIZE_UPDATE
>+#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT                                                    0x4
>+#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK                                                      0x007FFFF0L
>+//UVD_JRBC_ENC_IB_COND_RD_TIMER
>+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT                                                 0x0
>+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT                                              0x10
>+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT                                              0x18
>+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT                                                  0x19
>+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK                                                   0x0000FFFFL
>+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK                                                0x00FF0000L
>+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK                                                0x01000000L
>+#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK                                                    0x02000000L
>+//UVD_JRBC_ENC_IB_REF_DATA
>+#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT                                                             0x0
>+#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK                                                               0xFFFFFFFFL
>+//UVD_JPEG_ENC_PREEMPT_CMD
>+#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT                                                           0x0
>+#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT                                                   0x1
>+#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT                                                    0x2
>+#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK                                                             0x00000001L
>+#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK                                                     0x00000002L
>+#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK                                                      0x00000004L
>+//UVD_JPEG_ENC_PREEMPT_FENCE_DATA0
>+#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT                                          0x0
>+#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK                                            0xFFFFFFFFL
>+//UVD_JPEG_ENC_PREEMPT_FENCE_DATA1
>+#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT                                          0x0
>+#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK                                            0xFFFFFFFFL
>+//UVD_JRBC_ENC_RB_SIZE
>+#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT                                                                  0x4
>+#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK                                                                    0x00FFFFF0L
>+//UVD_JRBC_ENC_SCRATCH0
>+#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT                                                                0x0
>+#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK                                                                  0xFFFFFFFFL
>+
>+
>+// addressBlock: uvd0_uvd_jmi_dec
>+//UVD_JMI_CTRL
>+#define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT                                                                     0x0
>+#define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT                                                                   0x1
>+#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT                                                                 0x2
>+#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT                                                             0x8
>+#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT                                                             0x10
>+#define UVD_JMI_CTRL__CRC_RESET__SHIFT                                                                        0x18
>+#define UVD_JMI_CTRL__CRC_SEL__SHIFT                                                                          0x19
>+#define UVD_JMI_CTRL__STALL_MC_ARB_MASK                                                                       0x00000001L
>+#define UVD_JMI_CTRL__MASK_MC_URGENT_MASK                                                                     0x00000002L
>+#define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK                                                                   0x00000004L
>+#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK                                                               0x0000FF00L
>+#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK                                                               0x00FF0000L
>+#define UVD_JMI_CTRL__CRC_RESET_MASK                                                                          0x01000000L
>+#define UVD_JMI_CTRL__CRC_SEL_MASK                                                                            0x1E000000L
>+//UVD_LMI_JRBC_CTRL
>+#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT                                                              0x0
>+#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT                                                              0x1
>+#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT                                                                0x4
>+#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT                                                                0x8
>+#define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT                                                                     0x14
>+#define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT                                                                     0x16
>+#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK                                                                0x00000001L
>+#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK                                                                0x00000002L
>+#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK                                                                  0x000000F0L
>+#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK                                                                  0x00000F00L
>+#define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK                                                                       0x00300000L
>+#define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK                                                                       0x00C00000L
>+//UVD_LMI_JPEG_CTRL
>+#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT                                                              0x0
>+#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT                                                              0x1
>+#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT                                                                0x4
>+#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT                                                                0x8
>+#define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT                                                                     0x14
>+#define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT                                                                     0x16
>+#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK                                                                0x00000001L
>+#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK                                                                0x00000002L
>+#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK                                                                  0x000000F0L
>+#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK                                                                  0x00000F00L
>+#define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK                                                                       0x00300000L
>+#define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK                                                                       0x00C00000L
>+//UVD_JMI_EJRBC_CTRL
>+#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT                                                             0x0
>+#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT                                                             0x1
>+#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT                                                               0x4
>+#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT                                                               0x8
>+#define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT                                                                    0x14
>+#define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT                                                                    0x16
>+#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK                                                               0x00000001L
>+#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK                                                               0x00000002L
>+#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK                                                                 0x000000F0L
>+#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK                                                                 0x00000F00L
>+#define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK                                                                      0x00300000L
>+#define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK                                                                      0x00C00000L
>+//UVD_LMI_EJPEG_CTRL
>+#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT                                                             0x0
>+#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT                                                             0x1
>+#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT                                                               0x4
>+#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT                                                               0x8
>+#define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT                                                                    0x14
>+#define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT                                                                    0x16
>+#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK                                                               0x00000001L
>+#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK                                                               0x00000002L
>+#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK                                                                 0x000000F0L
>+#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK                                                                 0x00000F00L
>+#define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK                                                                      0x00300000L
>+#define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK                                                                      0x00C00000L
>+//UVD_LMI_JRBC_IB_VMID
>+#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT                                                               0x0
>+#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT                                                               0x4
>+#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT                                                              0x8
>+#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK                                                                 0x0000000FL
>+#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK                                                                 0x000000F0L
>+#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK                                                                0x00000F00L
>+//UVD_LMI_JRBC_RB_VMID
>+#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT                                                               0x0
>+#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT                                                               0x4
>+#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT                                                              0x8
>+#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK                                                                 0x0000000FL
>+#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK                                                                 0x000000F0L
>+#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK                                                                0x00000F00L
>+//UVD_LMI_JPEG_VMID
>+#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT                                                                0x0
>+#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT                                                                0x4
>+#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT                                                        0x8
>+#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK                                                                  0x0000000FL
>+#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK                                                                  0x000000F0L
>+#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK                                                          0x00000F00L
>+//UVD_JMI_ENC_JRBC_IB_VMID
>+#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT                                                           0x0
>+#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT                                                           0x4
>+#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT                                                          0x8
>+#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK                                                             0x0000000FL
>+#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK                                                             0x000000F0L
>+#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK                                                            0x00000F00L
>+//UVD_JMI_ENC_JRBC_RB_VMID
>+#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT                                                           0x0
>+#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT                                                           0x4
>+#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT                                                          0x8
>+#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK                                                             0x0000000FL
>+#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK                                                             0x000000F0L
>+#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK                                                            0x00000F00L
>+//UVD_JMI_ENC_JPEG_VMID
>+#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT                                                             0x0
>+#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT                                                              0x5
>+#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT                                                          0xa
>+#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT                                                          0xf
>+#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT                                                         0x13
>+#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT                                                    0x17
>+#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK                                                               0x0000000FL
>+#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK                                                                0x000001E0L
>+#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK                                                            0x00003C00L
>+#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK                                                            0x00078000L
>+#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK                                                           0x00780000L
>+#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK                                                      0x07800000L
>+//UVD_JMI_PERFMON_CTRL
>+#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT                                                            0x0
>+#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT                                                              0x8
>+#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK                                                              0x00000003L
>+#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK                                                                0x00000F00L
>+//UVD_JMI_PERFMON_COUNT_LO
>+#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT                                                        0x0
>+#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK                                                          0xFFFFFFFFL
>+//UVD_JMI_PERFMON_COUNT_HI
>+#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT                                                        0x0
>+#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK                                                          0x0000FFFFL
>+//UVD_LMI_JPEG_READ_64BIT_BAR_LOW
>+#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                     0x0
>+#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK                                                       0xFFFFFFFFL
>+//UVD_LMI_JPEG_READ_64BIT_BAR_HIGH
>+#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                   0x0
>+#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW
>+#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                    0x0
>+#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK                                                      0xFFFFFFFFL
>+//UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH
>+#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                  0x0
>+#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK                                                    0xFFFFFFFFL
>+//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW
>+#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT                                            0x0
>+#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK                                              0xFFFFFFFFL
>+//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH
>+#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                          0x0
>+#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK                                            0xFFFFFFFFL
>+//UVD_LMI_JRBC_RB_64BIT_BAR_LOW
>+#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                       0x0
>+#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK                                                         0xFFFFFFFFL
>+//UVD_LMI_JRBC_RB_64BIT_BAR_HIGH
>+#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                     0x0
>+#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                       0xFFFFFFFFL
>+//UVD_LMI_JRBC_IB_64BIT_BAR_LOW
>+#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                       0x0
>+#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK                                                         0xFFFFFFFFL
>+//UVD_LMI_JRBC_IB_64BIT_BAR_HIGH
>+#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                     0x0
>+#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                       0xFFFFFFFFL
>+//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW
>+#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                0x0
>+#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK                                                  0xFFFFFFFFL
>+//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH
>+#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                              0x0
>+#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK                                                0xFFFFFFFFL
>+//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
>+#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                0x0
>+#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK                                                  0xFFFFFFFFL
>+//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
>+#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                              0x0
>+#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK                                                0xFFFFFFFFL
>+//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW
>+#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                0x0
>+#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK                                                  0xFFFFFFFFL
>+//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH
>+#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                              0x0
>+#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK                                                0xFFFFFFFFL
>+//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW
>+#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                0x0
>+#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK                                                  0xFFFFFFFFL
>+//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH
>+#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                              0x0
>+#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK                                                0xFFFFFFFFL
>+//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW
>+#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT                                           0x0
>+#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK                                             0xFFFFFFFFL
>+//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH
>+#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                         0x0
>+#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK                                           0xFFFFFFFFL
>+//UVD_LMI_EJRBC_RB_64BIT_BAR_LOW
>+#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                      0x0
>+#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK                                                        0xFFFFFFFFL
>+//UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH
>+#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                    0x0
>+#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                      0xFFFFFFFFL
>+//UVD_LMI_EJRBC_IB_64BIT_BAR_LOW
>+#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                      0x0
>+#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK                                                        0xFFFFFFFFL
>+//UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH
>+#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                    0x0
>+#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                      0xFFFFFFFFL
>+//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW
>+#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT                                               0x0
>+#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK                                                 0xFFFFFFFFL
>+//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH
>+#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                             0x0
>+#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK                                               0xFFFFFFFFL
>+//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW
>+#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT                                               0x0
>+#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK                                                 0xFFFFFFFFL
>+//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH
>+#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                             0x0
>+#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK                                               0xFFFFFFFFL
>+//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW
>+#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT                                               0x0
>+#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK                                                 0xFFFFFFFFL
>+//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH
>+#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                             0x0
>+#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK                                               0xFFFFFFFFL
>+//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW
>+#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT                                               0x0
>+#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK                                                 0xFFFFFFFFL
>+//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH
>+#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                             0x0
>+#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK                                               0xFFFFFFFFL
>+//UVD_LMI_JPEG_PREEMPT_VMID
>+#define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT                                                                0x0
>+#define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK                                                                  0x0000000FL
>+//UVD_LMI_ENC_JPEG_PREEMPT_VMID
>+#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT                                                            0x0
>+#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK                                                              0x0000000FL
>+//UVD_LMI_JPEG2_VMID
>+#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT                                                              0x0
>+#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT                                                              0x4
>+#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK                                                                0x0000000FL
>+#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK                                                                0x000000F0L
>+//UVD_LMI_JPEG2_READ_64BIT_BAR_LOW
>+#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                    0x0
>+#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK                                                      0xFFFFFFFFL
>+//UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH
>+#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                  0x0
>+#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK                                                    0xFFFFFFFFL
>+//UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW
>+#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
>+#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH
>+#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
>+#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
>+//UVD_LMI_JPEG_CTRL2
>+#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT                                                             0x0
>+#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT                                                             0x1
>+#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT                                                               0x4
>+#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT                                                               0x8
>+#define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT                                                                    0x14
>+#define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT                                                                    0x16
>+#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK                                                               0x00000001L
>+#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK                                                               0x00000002L
>+#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK                                                                 0x000000F0L
>+#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK                                                                 0x00000F00L
>+#define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK                                                                      0x00300000L
>+#define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK                                                                      0x00C00000L
>+//UVD_JMI_DEC_SWAP_CNTL
>+#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT                                                              0x0
>+#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT                                                              0x2
>+#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT                                                       0x4
>+#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT                                                       0x6
>+#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT                                                       0x8
>+#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT                                                       0xa
>+#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT                                                      0xc
>+#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT                                                         0xe
>+#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT                                                         0x10
>+#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK                                                                0x00000003L
>+#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK                                                                0x0000000CL
>+#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK                                                         0x00000030L
>+#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK                                                         0x000000C0L
>+#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK                                                         0x00000300L
>+#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK                                                         0x00000C00L
>+#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK                                                        0x00003000L
>+#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK                                                           0x0000C000L
>+#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK                                                           0x00030000L
>+//UVD_JMI_ENC_SWAP_CNTL
>+#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT                                                              0x0
>+#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT                                                              0x2
>+#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT                                                       0x4
>+#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT                                                       0x6
>+#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT                                                       0x8
>+#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT                                                       0xa
>+#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT                                                      0xc
>+#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT                                                          0xe
>+#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT                                                           0x10
>+#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT                                                       0x12
>+#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT                                                       0x14
>+#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT                                                      0x16
>+#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK                                                                0x00000003L
>+#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK                                                                0x0000000CL
>+#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK                                                         0x00000030L
>+#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK                                                         0x000000C0L
>+#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK                                                         0x00000300L
>+#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK                                                         0x00000C00L
>+#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK                                                        0x00003000L
>+#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK                                                            0x0000C000L
>+#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK                                                             0x00030000L
>+#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK                                                         0x000C0000L
>+#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK                                                         0x00300000L
>+#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK                                                        0x00C00000L
>+//UVD_JMI_CNTL
>+#define UVD_JMI_CNTL__SOFT_RESET__SHIFT                                                                       0x0
>+#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT                                                                0x8
>+#define UVD_JMI_CNTL__SOFT_RESET_MASK                                                                         0x00000001L
>+#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK                                                                  0x0003FF00L
>+//UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW
>+#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                    0x0
>+#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK                                                      0xFFFFFFFFL
>+//UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH
>+#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                  0x0
>+#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK                                                    0xFFFFFFFFL
>+//UVD_JMI_DEC_SWAP_CNTL2
>+#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT                                                       0x0
>+#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT                                                       0x2
>+#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK                                                         0x00000003L
>+#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK                                                         0x0000000CL
>+
>+
>+// addressBlock: uvd0_uvd_jpeg_common_dec
>+//JPEG_SOFT_RESET_STATUS
>+#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT                                                  0x0
>+#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT                                                 0x1
>+#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT                                                     0x2
>+#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT                                                  0x3
>+#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT                                                     0x4
>+#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT                                                     0x5
>+#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK                                                    0x00000001L
>+#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK                                                   0x00000002L
>+#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK                                                       0x00000004L
>+#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK                                                    0x00000008L
>+#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK                                                       0x00000010L
>+#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK                                                       0x00000020L
>+//JPEG_SYS_INT_EN
>+#define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT                                                                    0x0
>+#define JPEG_SYS_INT_EN__DJRBC__SHIFT                                                                         0x1
>+#define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT                                                                  0x2
>+#define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT                                                                  0x3
>+#define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT                                                                    0x4
>+#define JPEG_SYS_INT_EN__EJRBC__SHIFT                                                                         0x5
>+#define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT                                                                   0x6
>+#define JPEG_SYS_INT_EN__DJPEG_CORE_MASK                                                                      0x00000001L
>+#define JPEG_SYS_INT_EN__DJRBC_MASK                                                                           0x00000002L
>+#define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK                                                                    0x00000004L
>+#define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK                                                                    0x00000008L
>+#define JPEG_SYS_INT_EN__EJPEG_CORE_MASK                                                                      0x00000010L
>+#define JPEG_SYS_INT_EN__EJRBC_MASK                                                                           0x00000020L
>+#define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK                                                                     0x00000040L
>+//JPEG_SYS_INT_STATUS
>+#define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT                                                                0x0
>+#define JPEG_SYS_INT_STATUS__DJRBC__SHIFT                                                                     0x1
>+#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT                                                              0x2
>+#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT                                                              0x3
>+#define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT                                                                0x4
>+#define JPEG_SYS_INT_STATUS__EJRBC__SHIFT                                                                     0x5
>+#define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT                                                               0x6
>+#define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK                                                                  0x00000001L
>+#define JPEG_SYS_INT_STATUS__DJRBC_MASK                                                                       0x00000002L
>+#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK                                                                0x00000004L
>+#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK                                                                0x00000008L
>+#define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK                                                                  0x00000010L
>+#define JPEG_SYS_INT_STATUS__EJRBC_MASK                                                                       0x00000020L
>+#define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK                                                                 0x00000040L
>+//JPEG_SYS_INT_ACK
>+#define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT                                                                   0x0
>+#define JPEG_SYS_INT_ACK__DJRBC__SHIFT                                                                        0x1
>+#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT                                                                 0x2
>+#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT                                                                 0x3
>+#define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT                                                                   0x4
>+#define JPEG_SYS_INT_ACK__EJRBC__SHIFT                                                                        0x5
>+#define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT                                                                  0x6
>+#define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK                                                                     0x00000001L
>+#define JPEG_SYS_INT_ACK__DJRBC_MASK                                                                          0x00000002L
>+#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK                                                                   0x00000004L
>+#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK                                                                   0x00000008L
>+#define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK                                                                     0x00000010L
>+#define JPEG_SYS_INT_ACK__EJRBC_MASK                                                                          0x00000020L
>+#define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK                                                                    0x00000040L
>+//JPEG_MASTINT_EN
>+#define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT                                                                   0x0
>+#define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT                                                                   0x4
>+#define JPEG_MASTINT_EN__OVERRUN_RST_MASK                                                                     0x00000001L
>+#define JPEG_MASTINT_EN__INT_OVERRUN_MASK                                                                     0x007FFFF0L
>+//JPEG_IH_CTRL
>+#define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT                                                                    0x0
>+#define JPEG_IH_CTRL__IH_STALL_EN__SHIFT                                                                      0x1
>+#define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT                                                                  0x2
>+#define JPEG_IH_CTRL__IH_VMID__SHIFT                                                                          0x3
>+#define JPEG_IH_CTRL__IH_USER_DATA__SHIFT                                                                     0x7
>+#define JPEG_IH_CTRL__IH_RINGID__SHIFT                                                                        0x13
>+#define JPEG_IH_CTRL__IH_SOFT_RESET_MASK                                                                      0x00000001L
>+#define JPEG_IH_CTRL__IH_STALL_EN_MASK                                                                        0x00000002L
>+#define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK                                                                    0x00000004L
>+#define JPEG_IH_CTRL__IH_VMID_MASK                                                                            0x00000078L
>+#define JPEG_IH_CTRL__IH_USER_DATA_MASK                                                                       0x0007FF80L
>+#define JPEG_IH_CTRL__IH_RINGID_MASK                                                                          0x07F80000L
>+//JRBBM_ARB_CTRL
>+#define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT                                                                     0x0
>+#define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT                                                                     0x1
>+#define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT                                                                      0x2
>+#define JRBBM_ARB_CTRL__DJRBC_DROP_MASK                                                                       0x00000001L
>+#define JRBBM_ARB_CTRL__EJRBC_DROP_MASK                                                                       0x00000002L
>+#define JRBBM_ARB_CTRL__SRBM_DROP_MASK                                                                        0x00000004L
>+
>+
>+// addressBlock: uvd0_uvd_jpeg_common_sclk_dec
>+//JPEG_CGC_GATE
>+#define JPEG_CGC_GATE__JPEG_DEC__SHIFT                                                                        0x0
>+#define JPEG_CGC_GATE__JPEG2_DEC__SHIFT                                                                       0x1
>+#define JPEG_CGC_GATE__JPEG_ENC__SHIFT                                                                        0x2
>+#define JPEG_CGC_GATE__JMCIF__SHIFT                                                                           0x3
>+#define JPEG_CGC_GATE__JRBBM__SHIFT                                                                           0x4
>+#define JPEG_CGC_GATE__JPEG_DEC_MASK                                                                          0x00000001L
>+#define JPEG_CGC_GATE__JPEG2_DEC_MASK                                                                         0x00000002L
>+#define JPEG_CGC_GATE__JPEG_ENC_MASK                                                                          0x00000004L
>+#define JPEG_CGC_GATE__JMCIF_MASK                                                                             0x00000008L
>+#define JPEG_CGC_GATE__JRBBM_MASK                                                                             0x00000010L
>+//JPEG_CGC_CTRL
>+#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT                                                                  0x0
>+#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT                                                              0x1
>+#define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT                                                                   0x5
>+#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT                                                                0xa
>+#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT                                                                0xb
>+#define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT                                                                    0xc
>+#define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT                                                                   0x10
>+#define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT                                                                  0x11
>+#define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT                                                                   0x12
>+#define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT                                                                      0x13
>+#define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT                                                                      0x14
>+#define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK                                                                    0x00000001L
>+#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK                                                                0x0000001EL
>+#define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK                                                                     0x000003E0L
>+#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK                                                                  0x00000400L
>+#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK                                                                  0x00000800L
>+#define JPEG_CGC_CTRL__GATER_DIV_ID_MASK                                                                      0x00007000L
>+#define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK                                                                     0x00010000L
>+#define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK                                                                    0x00020000L
>+#define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK                                                                     0x00040000L
>+#define JPEG_CGC_CTRL__JMCIF_MODE_MASK                                                                        0x00080000L
>+#define JPEG_CGC_CTRL__JRBBM_MODE_MASK                                                                        0x00100000L
>+//JPEG_CGC_STATUS
>+#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT                                                          0x0
>+#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT                                                          0x1
>+#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT                                                         0x2
>+#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT                                                         0x3
>+#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT                                                          0x4
>+#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT                                                          0x5
>+#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT                                                             0x6
>+#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT                                                             0x7
>+#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT                                                             0x8
>+#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK                                                            0x00000001L
>+#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK                                                            0x00000002L
>+#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK                                                           0x00000004L
>+#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK                                                           0x00000008L
>+#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK                                                            0x00000010L
>+#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK                                                            0x00000020L
>+#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK                                                               0x00000040L
>+#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK                                                               0x00000080L
>+#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK                                                               0x00000100L
>+//JPEG_COMN_CGC_MEM_CTRL
>+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT                                                            0x0
>+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT                                                            0x1
>+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT                                                            0x2
>+#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT                                                           0x10
>+#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT                                                         0x14
>+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK                                                              0x00000001L
>+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK                                                              0x00000002L
>+#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK                                                              0x00000004L
>+#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK                                                             0x000F0000L
>+#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK                                                           0x00F00000L
>+//JPEG_DEC_CGC_MEM_CTRL
>+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT                                                          0x0
>+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT                                                          0x1
>+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT                                                          0x2
>+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK                                                            0x00000001L
>+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK                                                            0x00000002L
>+#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK                                                            0x00000004L
>+//JPEG2_DEC_CGC_MEM_CTRL
>+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT                                                        0x0
>+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT                                                        0x1
>+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT                                                        0x2
>+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK                                                          0x00000001L
>+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK                                                          0x00000002L
>+#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK                                                          0x00000004L
>+//JPEG_ENC_CGC_MEM_CTRL
>+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT                                                          0x0
>+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT                                                          0x1
>+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT                                                          0x2
>+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK                                                            0x00000001L
>+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK                                                            0x00000002L
>+#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK                                                            0x00000004L
>+//JPEG_SOFT_RESET2
>+#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT                                                            0x0
>+#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK                                                              0x00000001L
>+//JPEG_PERF_BANK_CONF
>+#define JPEG_PERF_BANK_CONF__RESET__SHIFT                                                                     0x0
>+#define JPEG_PERF_BANK_CONF__PEEK__SHIFT                                                                      0x8
>+#define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT                                                               0x10
>+#define JPEG_PERF_BANK_CONF__RESET_MASK                                                                       0x0000000FL
>+#define JPEG_PERF_BANK_CONF__PEEK_MASK                                                                        0x00000F00L
>+#define JPEG_PERF_BANK_CONF__CONCATENATE_MASK                                                                 0x00030000L
>+//JPEG_PERF_BANK_EVENT_SEL
>+#define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT                                                                 0x0
>+#define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT                                                                 0x8
>+#define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT                                                                 0x10
>+#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT                                                                 0x18
>+#define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK                                                                   0x000000FFL
>+#define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK                                                                   0x0000FF00L
>+#define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK                                                                   0x00FF0000L
>+#define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK                                                                   0xFF000000L
>+//JPEG_PERF_BANK_COUNT0
>+#define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT                                                                   0x0
>+#define JPEG_PERF_BANK_COUNT0__COUNT_MASK                                                                     0xFFFFFFFFL
>+//JPEG_PERF_BANK_COUNT1
>+#define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT                                                                   0x0
>+#define JPEG_PERF_BANK_COUNT1__COUNT_MASK                                                                     0xFFFFFFFFL
>+//JPEG_PERF_BANK_COUNT2
>+#define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT                                                                   0x0
>+#define JPEG_PERF_BANK_COUNT2__COUNT_MASK                                                                     0xFFFFFFFFL
>+//JPEG_PERF_BANK_COUNT3
>+#define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT                                                                   0x0
>+#define JPEG_PERF_BANK_COUNT3__COUNT_MASK                                                                     0xFFFFFFFFL
>+
>+
>+// addressBlock: uvd0_uvd_pg_dec
>+//UVD_PGFSM_CONFIG
>+#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT                                                              0x0
>+#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT                                                              0x2
>+#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT                                                              0x4
>+#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT                                                              0x6
>+#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT                                                              0x8
>+#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT                                                             0xa
>+#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT                                                             0xc
>+#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT                                                             0xe
>+#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT                                                             0x10
>+#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT                                                              0x12
>+#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT                                                              0x14
>+#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT                                                              0x16
>+#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK                                                                0x00000003L
>+#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK                                                                0x0000000CL
>+#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK                                                                0x00000030L
>+#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK                                                                0x000000C0L
>+#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK                                                                0x00000300L
>+#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK                                                               0x00000C00L
>+#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK                                                               0x00003000L
>+#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK                                                               0x0000C000L
>+#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK                                                               0x00030000L
>+#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK                                                                0x000C0000L
>+#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK                                                                0x00300000L
>+#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK                                                                0x00C00000L
>+//UVD_PGFSM_STATUS
>+#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT                                                              0x0
>+#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT                                                              0x2
>+#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT                                                              0x4
>+#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT                                                              0x6
>+#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT                                                              0x8
>+#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT                                                             0xa
>+#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT                                                             0xc
>+#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT                                                             0xe
>+#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT                                                             0x10
>+#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT                                                              0x12
>+#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT                                                              0x14
>+#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT                                                              0x16
>+#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK                                                                0x00000003L
>+#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK                                                                0x0000000CL
>+#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK                                                                0x00000030L
>+#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK                                                                0x000000C0L
>+#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK                                                                0x00000300L
>+#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK                                                               0x00000C00L
>+#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK                                                               0x00003000L
>+#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK                                                               0x0000C000L
>+#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK                                                               0x00030000L
>+#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK                                                                0x000C0000L
>+#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK                                                                0x00300000L
>+#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK                                                                0x00C00000L
>+//UVD_POWER_STATUS
>+#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT                                                             0x0
>+#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT                                                                  0x2
>+#define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT                                                                  0x4
>+#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT                                                                    0x8
>+#define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT                                                                0x9
>+#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT                                                              0xb
>+#define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT                                                           0x1f
>+#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK                                                               0x00000003L
>+#define UVD_POWER_STATUS__UVD_PG_MODE_MASK                                                                    0x00000004L
>+#define UVD_POWER_STATUS__UVD_CG_MODE_MASK                                                                    0x00000030L
>+#define UVD_POWER_STATUS__UVD_PG_EN_MASK                                                                      0x00000100L
>+#define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK                                                                  0x00000200L
>+#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK                                                                0x00000800L
>+#define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK                                                             0x80000000L
>+//UVD_PG_IND_INDEX
>+#define UVD_PG_IND_INDEX__INDEX__SHIFT                                                                        0x0
>+#define UVD_PG_IND_INDEX__INDEX_MASK                                                                          0x0000003FL
>+//UVD_PG_IND_DATA
>+#define UVD_PG_IND_DATA__DATA__SHIFT                                                                          0x0
>+#define UVD_PG_IND_DATA__DATA_MASK                                                                            0xFFFFFFFFL
>+//CC_UVD_HARVESTING
>+#define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT                                                               0x0
>+#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT                                                                 0x1
>+#define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK                                                                 0x00000001L
>+#define CC_UVD_HARVESTING__UVD_DISABLE_MASK                                                                   0x00000002L
>+//UVD_JPEG_POWER_STATUS
>+#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT                                                       0x0
>+#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT                                                            0x4
>+#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT                                                      0x8
>+#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT                                                      0x9
>+#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT                                                     0x1f
>+#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK                                                         0x00000001L
>+#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK                                                              0x00000010L
>+#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK                                                        0x00000100L
>+#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK                                                        0x00000200L
>+#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK                                                       0x80000000L
>+//UVD_DPG_LMA_CTL
>+#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT                                                                    0x0
>+#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT                                                                       0x1
>+#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT                                                           0x2
>+#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT                                                                      0x4
>+#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT                                                               0x10
>+#define UVD_DPG_LMA_CTL__READ_WRITE_MASK                                                                      0x00000001L
>+#define UVD_DPG_LMA_CTL__MASK_EN_MASK                                                                         0x00000002L
>+#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK                                                             0x00000004L
>+#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK                                                                        0x00000010L
>+#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK                                                                 0xFFFF0000L
>+//UVD_DPG_LMA_DATA
>+#define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT                                                                     0x0
>+#define UVD_DPG_LMA_DATA__LMA_DATA_MASK                                                                       0xFFFFFFFFL
>+//UVD_DPG_LMA_MASK
>+#define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT                                                                     0x0
>+#define UVD_DPG_LMA_MASK__LMA_MASK_MASK                                                                       0xFFFFFFFFL
>+//UVD_DPG_PAUSE
>+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT                                                              0x0
>+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT                                                              0x1
>+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT                                                                0x2
>+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT                                                                0x3
>+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK                                                                0x00000001L
>+#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK                                                                0x00000002L
>+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK                                                                  0x00000004L
>+#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK                                                                  0x00000008L
>+//UVD_SCRATCH1
>+#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT                                                                    0x0
>+#define UVD_SCRATCH1__SCRATCH1_DATA_MASK                                                                      0xFFFFFFFFL
>+//UVD_SCRATCH2
>+#define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT                                                                    0x0
>+#define UVD_SCRATCH2__SCRATCH2_DATA_MASK                                                                      0xFFFFFFFFL
>+//UVD_SCRATCH3
>+#define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT                                                                    0x0
>+#define UVD_SCRATCH3__SCRATCH3_DATA_MASK                                                                      0xFFFFFFFFL
>+//UVD_SCRATCH4
>+#define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT                                                                    0x0
>+#define UVD_SCRATCH4__SCRATCH4_DATA_MASK                                                                      0xFFFFFFFFL
>+//UVD_SCRATCH5
>+#define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT                                                                    0x0
>+#define UVD_SCRATCH5__SCRATCH5_DATA_MASK                                                                      0xFFFFFFFFL
>+//UVD_SCRATCH6
>+#define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT                                                                    0x0
>+#define UVD_SCRATCH6__SCRATCH6_DATA_MASK                                                                      0xFFFFFFFFL
>+//UVD_SCRATCH7
>+#define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT                                                                    0x0
>+#define UVD_SCRATCH7__SCRATCH7_DATA_MASK                                                                      0xFFFFFFFFL
>+//UVD_SCRATCH8
>+#define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT                                                                    0x0
>+#define UVD_SCRATCH8__SCRATCH8_DATA_MASK                                                                      0xFFFFFFFFL
>+//UVD_SCRATCH9
>+#define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT                                                                    0x0
>+#define UVD_SCRATCH9__SCRATCH9_DATA_MASK                                                                      0xFFFFFFFFL
>+//UVD_SCRATCH10
>+#define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT                                                                  0x0
>+#define UVD_SCRATCH10__SCRATCH10_DATA_MASK                                                                    0xFFFFFFFFL
>+//UVD_SCRATCH11
>+#define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT                                                                  0x0
>+#define UVD_SCRATCH11__SCRATCH11_DATA_MASK                                                                    0xFFFFFFFFL
>+//UVD_SCRATCH12
>+#define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT                                                                  0x0
>+#define UVD_SCRATCH12__SCRATCH12_DATA_MASK                                                                    0xFFFFFFFFL
>+//UVD_SCRATCH13
>+#define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT                                                                  0x0
>+#define UVD_SCRATCH13__SCRATCH13_DATA_MASK                                                                    0xFFFFFFFFL
>+//UVD_SCRATCH14
>+#define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT                                                                  0x0
>+#define UVD_SCRATCH14__SCRATCH14_DATA_MASK                                                                    0xFFFFFFFFL
>+//UVD_FREE_COUNTER_REG
>+#define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT                                                             0x0
>+#define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK                                                               0xFFFFFFFFL
>+//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW
>+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                0x0
>+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK                                                  0xFFFFFFFFL
>+//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH
>+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                              0x0
>+#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK                                                0xFFFFFFFFL
>+//UVD_DPG_VCPU_CACHE_OFFSET0
>+#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT                                                      0x0
>+#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK                                                        0x01FFFFFFL
>+//UVD_DPG_LMI_VCPU_CACHE_VMID
>+#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT                                                   0x0
>+#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK                                                     0x0000000FL
>+//UVD_PF_STATUS
>+#define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT                                                                 0x0
>+#define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT                                                                   0x1
>+#define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT                                                             0x2
>+#define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT                                                             0x3
>+#define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT                                                             0x4
>+#define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT                                                             0x5
>+#define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT                                                             0x6
>+#define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT                                                                0x7
>+#define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT                                                                   0x8
>+#define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT                                                                     0x9
>+#define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT                                                               0xa
>+#define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT                                                               0xb
>+#define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT                                                               0xc
>+#define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT                                                               0xd
>+#define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT                                                               0xe
>+#define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT                                                                  0xf
>+#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT                                                               0x10
>+#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT                                                               0x11
>+#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT                                                               0x12
>+#define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK                                                                   0x00000001L
>+#define UVD_PF_STATUS__NJ_PF_OCCURED_MASK                                                                     0x00000002L
>+#define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK                                                               0x00000004L
>+#define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK                                                               0x00000008L
>+#define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK                                                               0x00000010L
>+#define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK                                                               0x00000020L
>+#define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK                                                               0x00000040L
>+#define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK                                                                  0x00000080L
>+#define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK                                                                     0x00000100L
>+#define UVD_PF_STATUS__NJ_PF_CLEAR_MASK                                                                       0x00000200L
>+#define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK                                                                 0x00000400L
>+#define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK                                                                 0x00000800L
>+#define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK                                                                 0x00001000L
>+#define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK                                                                 0x00002000L
>+#define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK                                                                 0x00004000L
>+#define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK                                                                    0x00008000L
>+#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK                                                                 0x00010000L
>+#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK                                                                 0x00020000L
>+#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK                                                                 0x00040000L
>+//UVD_DPG_CLK_EN_VCPU_REPORT
>+#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT                                                             0x0
>+#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT                                                        0x1
>+#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK                                                               0x00000001L
>+#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK                                                          0x000000FEL
>+//UVD_GFX8_ADDR_CONFIG
>+#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                     0x4
>+#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                       0x00000070L
>+//UVD_GFX10_ADDR_CONFIG
>+#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT                                                               0x0
>+#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT                                                    0x3
>+#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT                                                               0xc
>+#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT                                                      0x13
>+#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK                                                                 0x00000007L
>+#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK                                                      0x00000038L
>+#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK                                                                 0x00007000L
>+#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK                                                        0x00180000L
>+//UVD_GPCNT2_CNTL
>+#define UVD_GPCNT2_CNTL__CLR__SHIFT                                                                           0x0
>+#define UVD_GPCNT2_CNTL__START__SHIFT                                                                         0x1
>+#define UVD_GPCNT2_CNTL__COUNTUP__SHIFT                                                                       0x2
>+#define UVD_GPCNT2_CNTL__CLR_MASK                                                                             0x00000001L
>+#define UVD_GPCNT2_CNTL__START_MASK                                                                           0x00000002L
>+#define UVD_GPCNT2_CNTL__COUNTUP_MASK                                                                         0x00000004L
>+//UVD_GPCNT2_TARGET_LOWER
>+#define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT                                                                0x0
>+#define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK                                                                  0xFFFFFFFFL
>+//UVD_GPCNT2_STATUS_LOWER
>+#define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT                                                                 0x0
>+#define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK                                                                   0xFFFFFFFFL
>+//UVD_GPCNT2_TARGET_UPPER
>+#define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT                                                                0x0
>+#define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK                                                                  0x0000FFFFL
>+//UVD_GPCNT2_STATUS_UPPER
>+#define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT                                                                 0x0
>+#define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK                                                                   0x0000FFFFL
>+//UVD_GPCNT3_CNTL
>+#define UVD_GPCNT3_CNTL__CLR__SHIFT                                                                           0x0
>+#define UVD_GPCNT3_CNTL__START__SHIFT                                                                         0x1
>+#define UVD_GPCNT3_CNTL__COUNTUP__SHIFT                                                                       0x2
>+#define UVD_GPCNT3_CNTL__FREQ__SHIFT                                                                          0x3
>+#define UVD_GPCNT3_CNTL__DIV__SHIFT                                                                           0xa
>+#define UVD_GPCNT3_CNTL__CLR_MASK                                                                             0x00000001L
>+#define UVD_GPCNT3_CNTL__START_MASK                                                                           0x00000002L
>+#define UVD_GPCNT3_CNTL__COUNTUP_MASK                                                                         0x00000004L
>+#define UVD_GPCNT3_CNTL__FREQ_MASK                                                                            0x000003F8L
>+#define UVD_GPCNT3_CNTL__DIV_MASK                                                                             0x0001FC00L
>+//UVD_GPCNT3_TARGET_LOWER
>+#define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT                                                                0x0
>+#define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK                                                                  0xFFFFFFFFL
>+//UVD_GPCNT3_STATUS_LOWER
>+#define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT                                                                 0x0
>+#define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK                                                                   0xFFFFFFFFL
>+//UVD_GPCNT3_TARGET_UPPER
>+#define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT                                                                0x0
>+#define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK                                                                  0x0000FFFFL
>+//UVD_GPCNT3_STATUS_UPPER
>+#define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT                                                                 0x0
>+#define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK                                                                   0x0000FFFFL
>+
>+
>+// addressBlock: uvd0_uvddec
>+//UVD_STATUS
>+#define UVD_STATUS__RBC_BUSY__SHIFT                                                                           0x0
>+#define UVD_STATUS__VCPU_REPORT__SHIFT                                                                        0x1
>+#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT                                                                   0x10
>+#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT                                                                      0x1f
>+#define UVD_STATUS__RBC_BUSY_MASK                                                                             0x00000001L
>+#define UVD_STATUS__VCPU_REPORT_MASK                                                                          0x000000FEL
>+#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK                                                                     0x00010000L
>+#define UVD_STATUS__SYS_GPCOM_REQ_MASK                                                                        0x80000000L
>+//UVD_ENC_PIPE_BUSY
>+#define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT                                                                    0x0
>+#define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT                                                                    0x1
>+#define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT                                                                    0x2
>+#define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT                                                                    0x3
>+#define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT                                                                    0x4
>+#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT                                                             0x5
>+#define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT                                                                    0x6
>+#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT                                                             0x7
>+#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT                                                             0x8
>+#define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT                                                             0x9
>+#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT                                                           0xa
>+#define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT                                                             0xb
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT                                                             0x10
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT                                                            0x11
>+#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT                                                            0x12
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT                                                            0x13
>+#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT                                                            0x14
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT                                                            0x15
>+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT                                                            0x16
>+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT                                                            0x17
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT                                                            0x18
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT                                                            0x19
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT                                                            0x1a
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT                                                            0x1b
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT                                                            0x1c
>+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT                                                            0x1d
>+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT                                                            0x1e
>+#define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK                                                                      0x00000001L
>+#define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK                                                                      0x00000002L
>+#define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK                                                                      0x00000004L
>+#define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK                                                                      0x00000008L
>+#define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK                                                                      0x00000010L
>+#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK                                                               0x00000020L
>+#define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK                                                                      0x00000040L
>+#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK                                                               0x00000080L
>+#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK                                                               0x00000100L
>+#define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK                                                               0x00000200L
>+#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK                                                             0x00000400L
>+#define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK                                                               0x00000800L
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK                                                               0x00010000L
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK                                                              0x00020000L
>+#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK                                                              0x00040000L
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK                                                              0x00080000L
>+#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK                                                              0x00100000L
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK                                                              0x00200000L
>+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK                                                              0x00400000L
>+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK                                                              0x00800000L
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK                                                              0x01000000L
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK                                                              0x02000000L
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK                                                              0x04000000L
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK                                                              0x08000000L
>+#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK                                                              0x10000000L
>+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK                                                              0x20000000L
>+#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK                                                              0x40000000L
>+//UVD_SOFT_RESET
>+#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT                                                                 0x0
>+#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT                                                                0x1
>+#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT                                                                 0x2
>+#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT                                                                0x3
>+#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT                                                                0x4
>+#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT                                                                 0x6
>+#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT                                                                 0x7
>+#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x8
>+#define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT                                                                 0x9
>+#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT                                                                  0xa
>+#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT                                                                0xb
>+#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT                                                                0xc
>+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT                                                             0xd
>+#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT                                                                 0xe
>+#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT                                                                 0xf
>+#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT                                                                 0x10
>+#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT                                                                0x11
>+#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT                                                         0x12
>+#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT                                                         0x13
>+#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT                                                         0x14
>+#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT                                                         0x15
>+#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT                                                          0x16
>+#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT                                                         0x17
>+#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT                                                         0x18
>+#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT                                                         0x19
>+#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT                                                          0x1a
>+#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT                                                          0x1b
>+#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT                                                         0x1c
>+#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT                                                         0x1d
>+#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT                                                           0x1e
>+#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT                                                          0x1f
>+#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK                                                                   0x00000001L
>+#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK                                                                  0x00000002L
>+#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK                                                                   0x00000004L
>+#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK                                                                  0x00000008L
>+#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK                                                                  0x00000010L
>+#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK                                                                   0x00000040L
>+#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK                                                                   0x00000080L
>+#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x00000100L
>+#define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK                                                                   0x00000200L
>+#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK                                                                    0x00000400L
>+#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK                                                                  0x00000800L
>+#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK                                                                  0x00001000L
>+#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK                                                               0x00002000L
>+#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK                                                                   0x00004000L
>+#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK                                                                   0x00008000L
>+#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK                                                                   0x00010000L
>+#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK                                                                  0x00020000L
>+#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK                                                           0x00040000L
>+#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK                                                           0x00080000L
>+#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK                                                           0x00100000L
>+#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK                                                           0x00200000L
>+#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK                                                            0x00400000L
>+#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK                                                           0x00800000L
>+#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK                                                           0x01000000L
>+#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK                                                           0x02000000L
>+#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK                                                            0x04000000L
>+#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK                                                            0x08000000L
>+#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK                                                           0x10000000L
>+#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK                                                           0x20000000L
>+#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK                                                             0x40000000L
>+#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK                                                            0x80000000L
>+//UVD_SOFT_RESET2
>+#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT                                                             0x0
>+#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT                                                       0x10
>+#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT                                                       0x11
>+#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK                                                               0x00000001L
>+#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK                                                         0x00010000L
>+#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK                                                         0x00020000L
>+//UVD_MMSCH_SOFT_RESET
>+#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT                                                              0x0
>+#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT                                                           0x1
>+#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT                                                               0x1f
>+#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK                                                                0x00000001L
>+#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK                                                             0x00000002L
>+#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK                                                                 0x80000000L
>+//UVD_CGC_GATE
>+#define UVD_CGC_GATE__SYS__SHIFT                                                                              0x0
>+#define UVD_CGC_GATE__UDEC__SHIFT                                                                             0x1
>+#define UVD_CGC_GATE__MPEG2__SHIFT                                                                            0x2
>+#define UVD_CGC_GATE__REGS__SHIFT                                                                             0x3
>+#define UVD_CGC_GATE__RBC__SHIFT                                                                              0x4
>+#define UVD_CGC_GATE__LMI_MC__SHIFT                                                                           0x5
>+#define UVD_CGC_GATE__LMI_UMC__SHIFT                                                                          0x6
>+#define UVD_CGC_GATE__IDCT__SHIFT                                                                             0x7
>+#define UVD_CGC_GATE__MPRD__SHIFT                                                                             0x8
>+#define UVD_CGC_GATE__MPC__SHIFT                                                                              0x9
>+#define UVD_CGC_GATE__LBSI__SHIFT                                                                             0xa
>+#define UVD_CGC_GATE__LRBBM__SHIFT                                                                            0xb
>+#define UVD_CGC_GATE__UDEC_RE__SHIFT                                                                          0xc
>+#define UVD_CGC_GATE__UDEC_CM__SHIFT                                                                          0xd
>+#define UVD_CGC_GATE__UDEC_IT__SHIFT                                                                          0xe
>+#define UVD_CGC_GATE__UDEC_DB__SHIFT                                                                          0xf
>+#define UVD_CGC_GATE__UDEC_MP__SHIFT                                                                          0x10
>+#define UVD_CGC_GATE__WCB__SHIFT                                                                              0x11
>+#define UVD_CGC_GATE__VCPU__SHIFT                                                                             0x12
>+#define UVD_CGC_GATE__MMSCH__SHIFT                                                                            0x14
>+#define UVD_CGC_GATE__SYS_MASK                                                                                0x00000001L
>+#define UVD_CGC_GATE__UDEC_MASK                                                                               0x00000002L
>+#define UVD_CGC_GATE__MPEG2_MASK                                                                              0x00000004L
>+#define UVD_CGC_GATE__REGS_MASK                                                                               0x00000008L
>+#define UVD_CGC_GATE__RBC_MASK                                                                                0x00000010L
>+#define UVD_CGC_GATE__LMI_MC_MASK                                                                             0x00000020L
>+#define UVD_CGC_GATE__LMI_UMC_MASK                                                                            0x00000040L
>+#define UVD_CGC_GATE__IDCT_MASK                                                                               0x00000080L
>+#define UVD_CGC_GATE__MPRD_MASK                                                                               0x00000100L
>+#define UVD_CGC_GATE__MPC_MASK                                                                                0x00000200L
>+#define UVD_CGC_GATE__LBSI_MASK                                                                               0x00000400L
>+#define UVD_CGC_GATE__LRBBM_MASK                                                                              0x00000800L
>+#define UVD_CGC_GATE__UDEC_RE_MASK                                                                            0x00001000L
>+#define UVD_CGC_GATE__UDEC_CM_MASK                                                                            0x00002000L
>+#define UVD_CGC_GATE__UDEC_IT_MASK                                                                            0x00004000L
>+#define UVD_CGC_GATE__UDEC_DB_MASK                                                                            0x00008000L
>+#define UVD_CGC_GATE__UDEC_MP_MASK                                                                            0x00010000L
>+#define UVD_CGC_GATE__WCB_MASK                                                                                0x00020000L
>+#define UVD_CGC_GATE__VCPU_MASK                                                                               0x00040000L
>+#define UVD_CGC_GATE__MMSCH_MASK                                                                              0x00100000L
>+//UVD_CGC_STATUS
>+#define UVD_CGC_STATUS__SYS_SCLK__SHIFT                                                                       0x0
>+#define UVD_CGC_STATUS__SYS_DCLK__SHIFT                                                                       0x1
>+#define UVD_CGC_STATUS__SYS_VCLK__SHIFT                                                                       0x2
>+#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT                                                                      0x3
>+#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT                                                                      0x4
>+#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT                                                                      0x5
>+#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT                                                                     0x6
>+#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT                                                                     0x7
>+#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT                                                                     0x8
>+#define UVD_CGC_STATUS__REGS_SCLK__SHIFT                                                                      0x9
>+#define UVD_CGC_STATUS__REGS_VCLK__SHIFT                                                                      0xa
>+#define UVD_CGC_STATUS__RBC_SCLK__SHIFT                                                                       0xb
>+#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT                                                                    0xc
>+#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT                                                                   0xd
>+#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT                                                                      0xe
>+#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT                                                                      0xf
>+#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT                                                                      0x10
>+#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT                                                                      0x11
>+#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT                                                                      0x12
>+#define UVD_CGC_STATUS__MPC_SCLK__SHIFT                                                                       0x13
>+#define UVD_CGC_STATUS__MPC_DCLK__SHIFT                                                                       0x14
>+#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT                                                                      0x15
>+#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT                                                                      0x16
>+#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT                                                                     0x17
>+#define UVD_CGC_STATUS__WCB_SCLK__SHIFT                                                                       0x18
>+#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT                                                                      0x19
>+#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT                                                                      0x1a
>+#define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT                                                                     0x1b
>+#define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT                                                                     0x1c
>+#define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT                                                                 0x1d
>+#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT                                                                 0x1f
>+#define UVD_CGC_STATUS__SYS_SCLK_MASK                                                                         0x00000001L
>+#define UVD_CGC_STATUS__SYS_DCLK_MASK                                                                         0x00000002L
>+#define UVD_CGC_STATUS__SYS_VCLK_MASK                                                                         0x00000004L
>+#define UVD_CGC_STATUS__UDEC_SCLK_MASK                                                                        0x00000008L
>+#define UVD_CGC_STATUS__UDEC_DCLK_MASK                                                                        0x00000010L
>+#define UVD_CGC_STATUS__UDEC_VCLK_MASK                                                                        0x00000020L
>+#define UVD_CGC_STATUS__MPEG2_SCLK_MASK                                                                       0x00000040L
>+#define UVD_CGC_STATUS__MPEG2_DCLK_MASK                                                                       0x00000080L
>+#define UVD_CGC_STATUS__MPEG2_VCLK_MASK                                                                       0x00000100L
>+#define UVD_CGC_STATUS__REGS_SCLK_MASK                                                                        0x00000200L
>+#define UVD_CGC_STATUS__REGS_VCLK_MASK                                                                        0x00000400L
>+#define UVD_CGC_STATUS__RBC_SCLK_MASK                                                                         0x00000800L
>+#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK                                                                      0x00001000L
>+#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK                                                                     0x00002000L
>+#define UVD_CGC_STATUS__IDCT_SCLK_MASK                                                                        0x00004000L
>+#define UVD_CGC_STATUS__IDCT_VCLK_MASK                                                                        0x00008000L
>+#define UVD_CGC_STATUS__MPRD_SCLK_MASK                                                                        0x00010000L
>+#define UVD_CGC_STATUS__MPRD_DCLK_MASK                                                                        0x00020000L
>+#define UVD_CGC_STATUS__MPRD_VCLK_MASK                                                                        0x00040000L
>+#define UVD_CGC_STATUS__MPC_SCLK_MASK                                                                         0x00080000L
>+#define UVD_CGC_STATUS__MPC_DCLK_MASK                                                                         0x00100000L
>+#define UVD_CGC_STATUS__LBSI_SCLK_MASK                                                                        0x00200000L
>+#define UVD_CGC_STATUS__LBSI_VCLK_MASK                                                                        0x00400000L
>+#define UVD_CGC_STATUS__LRBBM_SCLK_MASK                                                                       0x00800000L
>+#define UVD_CGC_STATUS__WCB_SCLK_MASK                                                                         0x01000000L
>+#define UVD_CGC_STATUS__VCPU_SCLK_MASK                                                                        0x02000000L
>+#define UVD_CGC_STATUS__VCPU_VCLK_MASK                                                                        0x04000000L
>+#define UVD_CGC_STATUS__MMSCH_SCLK_MASK                                                                       0x08000000L
>+#define UVD_CGC_STATUS__MMSCH_VCLK_MASK                                                                       0x10000000L
>+#define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK                                                                   0x20000000L
>+#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK                                                                   0x80000000L
>+//UVD_CGC_CTRL
>+#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT                                                                   0x0
>+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT                                                               0x2
>+#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT                                                                    0x6
>+#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT                                                                     0xb
>+#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT                                                                     0xc
>+#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT                                                                     0xd
>+#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT                                                                     0xe
>+#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT                                                                     0xf
>+#define UVD_CGC_CTRL__SYS_MODE__SHIFT                                                                         0x10
>+#define UVD_CGC_CTRL__UDEC_MODE__SHIFT                                                                        0x11
>+#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT                                                                       0x12
>+#define UVD_CGC_CTRL__REGS_MODE__SHIFT                                                                        0x13
>+#define UVD_CGC_CTRL__RBC_MODE__SHIFT                                                                         0x14
>+#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT                                                                      0x15
>+#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT                                                                     0x16
>+#define UVD_CGC_CTRL__IDCT_MODE__SHIFT                                                                        0x17
>+#define UVD_CGC_CTRL__MPRD_MODE__SHIFT                                                                        0x18
>+#define UVD_CGC_CTRL__MPC_MODE__SHIFT                                                                         0x19
>+#define UVD_CGC_CTRL__LBSI_MODE__SHIFT                                                                        0x1a
>+#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT                                                                       0x1b
>+#define UVD_CGC_CTRL__WCB_MODE__SHIFT                                                                         0x1c
>+#define UVD_CGC_CTRL__VCPU_MODE__SHIFT                                                                        0x1d
>+#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT                                                                       0x1f
>+#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK                                                                     0x00000001L
>+#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK                                                                 0x0000003CL
>+#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK                                                                      0x000007C0L
>+#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK                                                                       0x00000800L
>+#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK                                                                       0x00001000L
>+#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK                                                                       0x00002000L
>+#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK                                                                       0x00004000L
>+#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK                                                                       0x00008000L
>+#define UVD_CGC_CTRL__SYS_MODE_MASK                                                                           0x00010000L
>+#define UVD_CGC_CTRL__UDEC_MODE_MASK                                                                          0x00020000L
>+#define UVD_CGC_CTRL__MPEG2_MODE_MASK                                                                         0x00040000L
>+#define UVD_CGC_CTRL__REGS_MODE_MASK                                                                          0x00080000L
>+#define UVD_CGC_CTRL__RBC_MODE_MASK                                                                           0x00100000L
>+#define UVD_CGC_CTRL__LMI_MC_MODE_MASK                                                                        0x00200000L
>+#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK                                                                       0x00400000L
>+#define UVD_CGC_CTRL__IDCT_MODE_MASK                                                                          0x00800000L
>+#define UVD_CGC_CTRL__MPRD_MODE_MASK                                                                          0x01000000L
>+#define UVD_CGC_CTRL__MPC_MODE_MASK                                                                           0x02000000L
>+#define UVD_CGC_CTRL__LBSI_MODE_MASK                                                                          0x04000000L
>+#define UVD_CGC_CTRL__LRBBM_MODE_MASK                                                                         0x08000000L
>+#define UVD_CGC_CTRL__WCB_MODE_MASK                                                                           0x10000000L
>+#define UVD_CGC_CTRL__VCPU_MODE_MASK                                                                          0x20000000L
>+#define UVD_CGC_CTRL__MMSCH_MODE_MASK                                                                         0x80000000L
>+//UVD_CGC_UDEC_STATUS
>+#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT                                                                   0x0
>+#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT                                                                   0x1
>+#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT                                                                   0x2
>+#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT                                                                   0x3
>+#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT                                                                   0x4
>+#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT                                                                   0x5
>+#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT                                                                   0x6
>+#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT                                                                   0x7
>+#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT                                                                   0x8
>+#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT                                                                   0x9
>+#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT                                                                   0xa
>+#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT                                                                   0xb
>+#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT                                                                   0xc
>+#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT                                                                   0xd
>+#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT                                                                   0xe
>+#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK                                                                     0x00000001L
>+#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK                                                                     0x00000002L
>+#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK                                                                     0x00000004L
>+#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK                                                                     0x00000008L
>+#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK                                                                     0x00000010L
>+#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK                                                                     0x00000020L
>+#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK                                                                     0x00000040L
>+#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK                                                                     0x00000080L
>+#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK                                                                     0x00000100L
>+#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK                                                                     0x00000200L
>+#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK                                                                     0x00000400L
>+#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK                                                                     0x00000800L
>+#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK                                                                     0x00001000L
>+#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK                                                                     0x00002000L
>+#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK                                                                     0x00004000L
>+//UVD_SUVD_CGC_GATE
>+#define UVD_SUVD_CGC_GATE__SRE__SHIFT                                                                         0x0
>+#define UVD_SUVD_CGC_GATE__SIT__SHIFT                                                                         0x1
>+#define UVD_SUVD_CGC_GATE__SMP__SHIFT                                                                         0x2
>+#define UVD_SUVD_CGC_GATE__SCM__SHIFT                                                                         0x3
>+#define UVD_SUVD_CGC_GATE__SDB__SHIFT                                                                         0x4
>+#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT                                                                    0x5
>+#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT                                                                    0x6
>+#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT                                                                    0x7
>+#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT                                                                    0x8
>+#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT                                                                    0x9
>+#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT                                                                    0xa
>+#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT                                                                    0xb
>+#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT                                                                    0xc
>+#define UVD_SUVD_CGC_GATE__SCLR__SHIFT                                                                        0xd
>+#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT                                                                      0xe
>+#define UVD_SUVD_CGC_GATE__ENT__SHIFT                                                                         0xf
>+#define UVD_SUVD_CGC_GATE__IME__SHIFT                                                                         0x10
>+#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT                                                                0x11
>+#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT                                                                0x12
>+#define UVD_SUVD_CGC_GATE__SITE__SHIFT                                                                        0x13
>+#define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT                                                                     0x14
>+#define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT                                                                     0x15
>+#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT                                                                 0x16
>+#define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT                                                                     0x17
>+#define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT                                                                    0x18
>+#define UVD_SUVD_CGC_GATE__EFC__SHIFT                                                                         0x19
>+#define UVD_SUVD_CGC_GATE__SRE_MASK                                                                           0x00000001L
>+#define UVD_SUVD_CGC_GATE__SIT_MASK                                                                           0x00000002L
>+#define UVD_SUVD_CGC_GATE__SMP_MASK                                                                           0x00000004L
>+#define UVD_SUVD_CGC_GATE__SCM_MASK                                                                           0x00000008L
>+#define UVD_SUVD_CGC_GATE__SDB_MASK                                                                           0x00000010L
>+#define UVD_SUVD_CGC_GATE__SRE_H264_MASK                                                                      0x00000020L
>+#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK                                                                      0x00000040L
>+#define UVD_SUVD_CGC_GATE__SIT_H264_MASK                                                                      0x00000080L
>+#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK                                                                      0x00000100L
>+#define UVD_SUVD_CGC_GATE__SCM_H264_MASK                                                                      0x00000200L
>+#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK                                                                      0x00000400L
>+#define UVD_SUVD_CGC_GATE__SDB_H264_MASK                                                                      0x00000800L
>+#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK                                                                      0x00001000L
>+#define UVD_SUVD_CGC_GATE__SCLR_MASK                                                                          0x00002000L
>+#define UVD_SUVD_CGC_GATE__UVD_SC_MASK                                                                        0x00004000L
>+#define UVD_SUVD_CGC_GATE__ENT_MASK                                                                           0x00008000L
>+#define UVD_SUVD_CGC_GATE__IME_MASK                                                                           0x00010000L
>+#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK                                                                  0x00020000L
>+#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK                                                                  0x00040000L
>+#define UVD_SUVD_CGC_GATE__SITE_MASK                                                                          0x00080000L
>+#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK                                                                       0x00100000L
>+#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK                                                                       0x00200000L
>+#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK                                                                   0x00400000L
>+#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK                                                                       0x00800000L
>+#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK                                                                      0x01000000L
>+#define UVD_SUVD_CGC_GATE__EFC_MASK                                                                           0x02000000L
>+//UVD_SUVD_CGC_STATUS
>+#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT                                                                  0x0
>+#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT                                                                  0x1
>+#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT                                                                  0x2
>+#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT                                                                  0x3
>+#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT                                                                  0x4
>+#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT                                                                  0x5
>+#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT                                                             0x6
>+#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT                                                             0x7
>+#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT                                                             0x8
>+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT                                                             0x9
>+#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT                                                             0xa
>+#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT                                                             0xb
>+#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT                                                             0xc
>+#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT                                                             0xd
>+#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT                                                                 0xe
>+#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT                                                                    0xf
>+#define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT                                                                  0x10
>+#define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT                                                                  0x11
>+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT                                                         0x12
>+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT                                                         0x13
>+#define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT                                                                 0x14
>+#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT                                                            0x15
>+#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT                                                        0x16
>+#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT                                                              0x17
>+#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT                                                              0x18
>+#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT                                                          0x19
>+#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT                                                              0x1a
>+#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT                                                             0x1b
>+#define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT                                                                  0x1c
>+#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK                                                                    0x00000001L
>+#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK                                                                    0x00000002L
>+#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK                                                                    0x00000004L
>+#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK                                                                    0x00000008L
>+#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK                                                                    0x00000010L
>+#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK                                                                    0x00000020L
>+#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK                                                               0x00000040L
>+#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK                                                               0x00000080L
>+#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK                                                               0x00000100L
>+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK                                                               0x00000200L
>+#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK                                                               0x00000400L
>+#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK                                                               0x00000800L
>+#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK                                                               0x00001000L
>+#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK                                                               0x00002000L
>+#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK                                                                   0x00004000L
>+#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK                                                                      0x00008000L
>+#define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK                                                                    0x00010000L
>+#define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK                                                                    0x00020000L
>+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK                                                           0x00040000L
>+#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK                                                           0x00080000L
>+#define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK                                                                   0x00100000L
>+#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK                                                              0x00200000L
>+#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK                                                          0x00400000L
>+#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK                                                                0x00800000L
>+#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK                                                                0x01000000L
>+#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK                                                            0x02000000L
>+#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK                                                                0x04000000L
>+#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK                                                               0x08000000L
>+#define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK                                                                    0x10000000L
>+//UVD_SUVD_CGC_CTRL
>+#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT                                                                    0x0
>+#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT                                                                    0x1
>+#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT                                                                    0x2
>+#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT                                                                    0x3
>+#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT                                                                    0x4
>+#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT                                                                   0x5
>+#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT                                                                 0x6
>+#define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT                                                                    0x7
>+#define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT                                                                    0x8
>+#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT                                                                   0x9
>+#define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT                                                                    0xa
>+#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK                                                                      0x00000001L
>+#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK                                                                      0x00000002L
>+#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK                                                                      0x00000004L
>+#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK                                                                      0x00000008L
>+#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK                                                                      0x00000010L
>+#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK                                                                     0x00000020L
>+#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK                                                                   0x00000040L
>+#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK                                                                      0x00000080L
>+#define UVD_SUVD_CGC_CTRL__IME_MODE_MASK                                                                      0x00000100L
>+#define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK                                                                     0x00000200L
>+#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK                                                                      0x00000400L
>+//UVD_GPCOM_VCPU_CMD
>+#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT                                                                   0x0
>+#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT                                                                        0x1
>+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT                                                                 0x1f
>+#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK                                                                     0x00000001L
>+#define UVD_GPCOM_VCPU_CMD__CMD_MASK                                                                          0x7FFFFFFEL
>+#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK                                                                   0x80000000L
>+//UVD_GPCOM_VCPU_DATA0
>+#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT                                                                    0x0
>+#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK                                                                      0xFFFFFFFFL
>+//UVD_GPCOM_VCPU_DATA1
>+#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT                                                                    0x0
>+#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK                                                                      0xFFFFFFFFL
>+//UVD_GPCOM_SYS_CMD
>+#define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT                                                                    0x0
>+#define UVD_GPCOM_SYS_CMD__CMD__SHIFT                                                                         0x1
>+#define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT                                                                  0x1f
>+#define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK                                                                      0x00000001L
>+#define UVD_GPCOM_SYS_CMD__CMD_MASK                                                                           0x7FFFFFFEL
>+#define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK                                                                    0x80000000L
>+//UVD_GPCOM_SYS_DATA0
>+#define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT                                                                     0x0
>+#define UVD_GPCOM_SYS_DATA0__DATA0_MASK                                                                       0xFFFFFFFFL
>+//UVD_GPCOM_SYS_DATA1
>+#define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT                                                                     0x0
>+#define UVD_GPCOM_SYS_DATA1__DATA1_MASK                                                                       0xFFFFFFFFL
>+//UVD_VCPU_INT_EN
>+#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT                                                               0x0
>+#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT                                                    0x1
>+#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT                                             0x2
>+#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT                                                                  0x3
>+#define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT                                                                 0x4
>+#define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT                                                                 0x5
>+#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT                                                         0x6
>+#define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT                                                                 0x7
>+#define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT                                                                 0x9
>+#define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT                                                                 0xa
>+#define UVD_VCPU_INT_EN__LBSI_EN__SHIFT                                                                       0xb
>+#define UVD_VCPU_INT_EN__UDEC_EN__SHIFT                                                                       0xc
>+#define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT                                                                    0x10
>+#define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT                                                                  0x11
>+#define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT                                                                      0x12
>+#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT                                                         0x17
>+#define UVD_VCPU_INT_EN__IDCT_EN__SHIFT                                                                       0x18
>+#define UVD_VCPU_INT_EN__MPRD_EN__SHIFT                                                                       0x19
>+#define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT                                                                    0x1a
>+#define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT                                                                    0x1b
>+#define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT                                                                  0x1c
>+#define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT                                                                   0x1d
>+#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT                                                                 0x1e
>+#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT                                                                 0x1f
>+#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK                                                                 0x00000001L
>+#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK                                                      0x00000002L
>+#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK                                               0x00000004L
>+#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK                                                                    0x00000008L
>+#define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK                                                                   0x00000010L
>+#define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK                                                                   0x00000020L
>+#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK                                                           0x00000040L
>+#define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK                                                                   0x00000080L
>+#define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK                                                                   0x00000200L
>+#define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK                                                                   0x00000400L
>+#define UVD_VCPU_INT_EN__LBSI_EN_MASK                                                                         0x00000800L
>+#define UVD_VCPU_INT_EN__UDEC_EN_MASK                                                                         0x00001000L
>+#define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK                                                                      0x00010000L
>+#define UVD_VCPU_INT_EN__JOB_START_EN_MASK                                                                    0x00020000L
>+#define UVD_VCPU_INT_EN__NJ_PF_EN_MASK                                                                        0x00040000L
>+#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK                                                           0x00800000L
>+#define UVD_VCPU_INT_EN__IDCT_EN_MASK                                                                         0x01000000L
>+#define UVD_VCPU_INT_EN__MPRD_EN_MASK                                                                         0x02000000L
>+#define UVD_VCPU_INT_EN__AVM_INT_EN_MASK                                                                      0x04000000L
>+#define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK                                                                      0x08000000L
>+#define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK                                                                    0x10000000L
>+#define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK                                                                     0x20000000L
>+#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK                                                                   0x40000000L
>+#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK                                                                   0x80000000L
>+//UVD_VCPU_INT_ACK
>+#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT                                                             0x0
>+#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT                                                  0x1
>+#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT                                           0x2
>+#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT                                                                0x3
>+#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT                                                               0x4
>+#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT                                                               0x5
>+#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT                                                       0x6
>+#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT                                                               0x7
>+#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT                                                               0x9
>+#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT                                                               0xa
>+#define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT                                                                     0xb
>+#define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT                                                                     0xc
>+#define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT                                                                  0x10
>+#define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT                                                                0x11
>+#define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT                                                                    0x12
>+#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT                                                       0x17
>+#define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT                                                                     0x18
>+#define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT                                                                     0x19
>+#define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT                                                                  0x1a
>+#define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT                                                                  0x1b
>+#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT                                                                0x1c
>+#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT                                                                 0x1d
>+#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT                                                               0x1e
>+#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT                                                               0x1f
>+#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK                                                               0x00000001L
>+#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK                                                    0x00000002L
>+#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK                                             0x00000004L
>+#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK                                                                  0x00000008L
>+#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK                                                                 0x00000010L
>+#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK                                                                 0x00000020L
>+#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK                                                         0x00000040L
>+#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK                                                                 0x00000080L
>+#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK                                                                 0x00000200L
>+#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK                                                                 0x00000400L
>+#define UVD_VCPU_INT_ACK__LBSI_ACK_MASK                                                                       0x00000800L
>+#define UVD_VCPU_INT_ACK__UDEC_ACK_MASK                                                                       0x00001000L
>+#define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK                                                                    0x00010000L
>+#define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK                                                                  0x00020000L
>+#define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK                                                                      0x00040000L
>+#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK                                                         0x00800000L
>+#define UVD_VCPU_INT_ACK__IDCT_ACK_MASK                                                                       0x01000000L
>+#define UVD_VCPU_INT_ACK__MPRD_ACK_MASK                                                                       0x02000000L
>+#define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK                                                                    0x04000000L
>+#define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK                                                                    0x08000000L
>+#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK                                                                  0x10000000L
>+#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK                                                                   0x20000000L
>+#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK                                                                 0x40000000L
>+#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK                                                                 0x80000000L
>+//UVD_VCPU_INT_ROUTE
>+#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT                                                                 0x0
>+#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT                                                             0x1
>+#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT                                                                 0x2
>+#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK                                                                   0x00000001L
>+#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK                                                               0x00000002L
>+#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK                                                                   0x00000004L
>+//UVD_ENC_VCPU_INT_EN
>+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT                                                 0x0
>+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT                                                0x1
>+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT                                                0x2
>+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK                                                   0x00000001L
>+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK                                                  0x00000002L
>+#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK                                                  0x00000004L
>+//UVD_ENC_VCPU_INT_ACK
>+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT                                               0x0
>+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT                                              0x1
>+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT                                              0x2
>+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK                                                 0x00000001L
>+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK                                                0x00000002L
>+#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK                                                0x00000004L
>+//UVD_MASTINT_EN
>+#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT                                                                    0x0
>+#define UVD_MASTINT_EN__VCPU_EN__SHIFT                                                                        0x1
>+#define UVD_MASTINT_EN__SYS_EN__SHIFT                                                                         0x2
>+#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT                                                                    0x4
>+#define UVD_MASTINT_EN__OVERRUN_RST_MASK                                                                      0x00000001L
>+#define UVD_MASTINT_EN__VCPU_EN_MASK                                                                          0x00000002L
>+#define UVD_MASTINT_EN__SYS_EN_MASK                                                                           0x00000004L
>+#define UVD_MASTINT_EN__INT_OVERRUN_MASK                                                                      0x007FFFF0L
>+//UVD_SYS_INT_EN
>+#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT                                                                0x0
>+#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT                                                     0x1
>+#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT                                              0x2
>+#define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT                                                                      0x3
>+#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT                                                          0x6
>+#define UVD_SYS_INT_EN__LBSI_EN__SHIFT                                                                        0xb
>+#define UVD_SYS_INT_EN__UDEC_EN__SHIFT                                                                        0xc
>+#define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT                                                                    0x10
>+#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT                                                          0x17
>+#define UVD_SYS_INT_EN__IDCT_EN__SHIFT                                                                        0x18
>+#define UVD_SYS_INT_EN__MPRD_EN__SHIFT                                                                        0x19
>+#define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT                                                                     0x1b
>+#define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT                                                                   0x1c
>+#define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT                                                                    0x1d
>+#define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT                                                                     0x1f
>+#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK                                                                  0x00000001L
>+#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK                                                       0x00000002L
>+#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK                                                0x00000004L
>+#define UVD_SYS_INT_EN__CXW_WR_EN_MASK                                                                        0x00000008L
>+#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK                                                            0x00000040L
>+#define UVD_SYS_INT_EN__LBSI_EN_MASK                                                                          0x00000800L
>+#define UVD_SYS_INT_EN__UDEC_EN_MASK                                                                          0x00001000L
>+#define UVD_SYS_INT_EN__JOB_DONE_EN_MASK                                                                      0x00010000L
>+#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK                                                            0x00800000L
>+#define UVD_SYS_INT_EN__IDCT_EN_MASK                                                                          0x01000000L
>+#define UVD_SYS_INT_EN__MPRD_EN_MASK                                                                          0x02000000L
>+#define UVD_SYS_INT_EN__CLK_SWT_EN_MASK                                                                       0x08000000L
>+#define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK                                                                     0x10000000L
>+#define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK                                                                      0x20000000L
>+#define UVD_SYS_INT_EN__AVM_INT_EN_MASK                                                                       0x80000000L
>+//UVD_SYS_INT_STATUS
>+#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT                                                           0x0
>+#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT                                                0x1
>+#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT                                         0x2
>+#define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT                                                                 0x3
>+#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT                                                     0x6
>+#define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT                                                                   0xb
>+#define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT                                                                   0xc
>+#define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT                                                               0x10
>+#define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT                                                                  0x12
>+#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT                                                     0x17
>+#define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT                                                                   0x18
>+#define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT                                                                   0x19
>+#define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT                                                                0x1b
>+#define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT                                                                  0x1c
>+#define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT                                                               0x1d
>+#define UVD_SYS_INT_STATUS__AVM_INT__SHIFT                                                                    0x1f
>+#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK                                                             0x00000001L
>+#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK                                                  0x00000002L
>+#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK                                           0x00000004L
>+#define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK                                                                   0x00000008L
>+#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK                                                       0x00000040L
>+#define UVD_SYS_INT_STATUS__LBSI_INT_MASK                                                                     0x00000800L
>+#define UVD_SYS_INT_STATUS__UDEC_INT_MASK                                                                     0x00001000L
>+#define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK                                                                 0x00010000L
>+#define UVD_SYS_INT_STATUS__GPCOM_INT_MASK                                                                    0x00040000L
>+#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK                                                       0x00800000L
>+#define UVD_SYS_INT_STATUS__IDCT_INT_MASK                                                                     0x01000000L
>+#define UVD_SYS_INT_STATUS__MPRD_INT_MASK                                                                     0x02000000L
>+#define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK                                                                  0x08000000L
>+#define UVD_SYS_INT_STATUS__MIF_HWINT_MASK                                                                    0x10000000L
>+#define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK                                                                 0x20000000L
>+#define UVD_SYS_INT_STATUS__AVM_INT_MASK                                                                      0x80000000L
>+//UVD_SYS_INT_ACK
>+#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT                                                              0x0
>+#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT                                                   0x1
>+#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT                                            0x2
>+#define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT                                                                    0x3
>+#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT                                                        0x6
>+#define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT                                                                      0xb
>+#define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT                                                                      0xc
>+#define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT                                                                  0x10
>+#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT                                                        0x17
>+#define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT                                                                      0x18
>+#define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT                                                                      0x19
>+#define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT                                                                   0x1b
>+#define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT                                                                 0x1c
>+#define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT                                                                  0x1d
>+#define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT                                                                   0x1f
>+#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK                                                                0x00000001L
>+#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK                                                     0x00000002L
>+#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK                                              0x00000004L
>+#define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK                                                                      0x00000008L
>+#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK                                                          0x00000040L
>+#define UVD_SYS_INT_ACK__LBSI_ACK_MASK                                                                        0x00000800L
>+#define UVD_SYS_INT_ACK__UDEC_ACK_MASK                                                                        0x00001000L
>+#define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK                                                                    0x00010000L
>+#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK                                                          0x00800000L
>+#define UVD_SYS_INT_ACK__IDCT_ACK_MASK                                                                        0x01000000L
>+#define UVD_SYS_INT_ACK__MPRD_ACK_MASK                                                                        0x02000000L
>+#define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK                                                                     0x08000000L
>+#define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK                                                                   0x10000000L
>+#define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK                                                                    0x20000000L
>+#define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK                                                                     0x80000000L
>+//UVD_JOB_DONE
>+#define UVD_JOB_DONE__JOB_DONE__SHIFT                                                                         0x0
>+#define UVD_JOB_DONE__JOB_DONE_MASK                                                                           0x00000003L
>+//UVD_CBUF_ID
>+#define UVD_CBUF_ID__CBUF_ID__SHIFT                                                                           0x0
>+#define UVD_CBUF_ID__CBUF_ID_MASK                                                                             0xFFFFFFFFL
>+//UVD_CONTEXT_ID
>+#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT                                                                     0x0
>+#define UVD_CONTEXT_ID__CONTEXT_ID_MASK                                                                       0xFFFFFFFFL
>+//UVD_CONTEXT_ID2
>+#define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT                                                                   0x0
>+#define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK                                                                     0xFFFFFFFFL
>+//UVD_NO_OP
>+#define UVD_NO_OP__NO_OP__SHIFT                                                                               0x0
>+#define UVD_NO_OP__NO_OP_MASK                                                                                 0xFFFFFFFFL
>+//UVD_RB_BASE_LO
>+#define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT                                                                     0x6
>+#define UVD_RB_BASE_LO__RB_BASE_LO_MASK                                                                       0xFFFFFFC0L
>+//UVD_RB_BASE_HI
>+#define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT                                                                     0x0
>+#define UVD_RB_BASE_HI__RB_BASE_HI_MASK                                                                       0xFFFFFFFFL
>+//UVD_RB_SIZE
>+#define UVD_RB_SIZE__RB_SIZE__SHIFT                                                                           0x4
>+#define UVD_RB_SIZE__RB_SIZE_MASK                                                                             0x007FFFF0L
>+//UVD_RB_RPTR
>+#define UVD_RB_RPTR__RB_RPTR__SHIFT                                                                           0x4
>+#define UVD_RB_RPTR__RB_RPTR_MASK                                                                             0x007FFFF0L
>+//UVD_RB_WPTR
>+#define UVD_RB_WPTR__RB_WPTR__SHIFT                                                                           0x4
>+#define UVD_RB_WPTR__RB_WPTR_MASK                                                                             0x007FFFF0L
>+//UVD_RB_BASE_LO2
>+#define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT                                                                    0x6
>+#define UVD_RB_BASE_LO2__RB_BASE_LO_MASK                                                                      0xFFFFFFC0L
>+//UVD_RB_BASE_HI2
>+#define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT                                                                    0x0
>+#define UVD_RB_BASE_HI2__RB_BASE_HI_MASK                                                                      0xFFFFFFFFL
>+//UVD_RB_SIZE2
>+#define UVD_RB_SIZE2__RB_SIZE__SHIFT                                                                          0x4
>+#define UVD_RB_SIZE2__RB_SIZE_MASK                                                                            0x007FFFF0L
>+//UVD_RB_RPTR2
>+#define UVD_RB_RPTR2__RB_RPTR__SHIFT                                                                          0x4
>+#define UVD_RB_RPTR2__RB_RPTR_MASK                                                                            0x007FFFF0L
>+//UVD_RB_WPTR2
>+#define UVD_RB_WPTR2__RB_WPTR__SHIFT                                                                          0x4
>+#define UVD_RB_WPTR2__RB_WPTR_MASK                                                                            0x007FFFF0L
>+//UVD_RB_BASE_LO3
>+#define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT                                                                    0x6
>+#define UVD_RB_BASE_LO3__RB_BASE_LO_MASK                                                                      0xFFFFFFC0L
>+//UVD_RB_BASE_HI3
>+#define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT                                                                    0x0
>+#define UVD_RB_BASE_HI3__RB_BASE_HI_MASK                                                                      0xFFFFFFFFL
>+//UVD_RB_SIZE3
>+#define UVD_RB_SIZE3__RB_SIZE__SHIFT                                                                          0x4
>+#define UVD_RB_SIZE3__RB_SIZE_MASK                                                                            0x007FFFF0L
>+//UVD_RB_RPTR3
>+#define UVD_RB_RPTR3__RB_RPTR__SHIFT                                                                          0x4
>+#define UVD_RB_RPTR3__RB_RPTR_MASK                                                                            0x007FFFF0L
>+//UVD_RB_WPTR3
>+#define UVD_RB_WPTR3__RB_WPTR__SHIFT                                                                          0x4
>+#define UVD_RB_WPTR3__RB_WPTR_MASK                                                                            0x007FFFF0L
>+//UVD_RB_BASE_LO4
>+#define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT                                                                    0x6
>+#define UVD_RB_BASE_LO4__RB_BASE_LO_MASK                                                                      0xFFFFFFC0L
>+//UVD_RB_BASE_HI4
>+#define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT                                                                    0x0
>+#define UVD_RB_BASE_HI4__RB_BASE_HI_MASK                                                                      0xFFFFFFFFL
>+//UVD_RB_SIZE4
>+#define UVD_RB_SIZE4__RB_SIZE__SHIFT                                                                          0x4
>+#define UVD_RB_SIZE4__RB_SIZE_MASK                                                                            0x007FFFF0L
>+//UVD_RB_RPTR4
>+#define UVD_RB_RPTR4__RB_RPTR__SHIFT                                                                          0x4
>+#define UVD_RB_RPTR4__RB_RPTR_MASK                                                                            0x007FFFF0L
>+//UVD_RB_WPTR4
>+#define UVD_RB_WPTR4__RB_WPTR__SHIFT                                                                          0x4
>+#define UVD_RB_WPTR4__RB_WPTR_MASK                                                                            0x007FFFF0L
>+//UVD_OUT_RB_BASE_LO
>+#define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT                                                                 0x6
>+#define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK                                                                   0xFFFFFFC0L
>+//UVD_OUT_RB_BASE_HI
>+#define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT                                                                 0x0
>+#define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK                                                                   0xFFFFFFFFL
>+//UVD_OUT_RB_SIZE
>+#define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT                                                                       0x4
>+#define UVD_OUT_RB_SIZE__RB_SIZE_MASK                                                                         0x007FFFF0L
>+//UVD_OUT_RB_RPTR
>+#define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT                                                                       0x4
>+#define UVD_OUT_RB_RPTR__RB_RPTR_MASK                                                                         0x007FFFF0L
>+//UVD_OUT_RB_WPTR
>+#define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT                                                                       0x4
>+#define UVD_OUT_RB_WPTR__RB_WPTR_MASK                                                                         0x007FFFF0L
>+//UVD_RB_ARB_CTRL
>+#define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT                                                                     0x0
>+#define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT                                                                      0x1
>+#define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT                                                                     0x2
>+#define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT                                                                      0x3
>+#define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT                                                                      0x4
>+#define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT                                                                       0x5
>+#define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT                                                                   0x6
>+#define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT                                                                    0x7
>+#define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT                                                                  0x8
>+#define UVD_RB_ARB_CTRL__SRBM_DROP_MASK                                                                       0x00000001L
>+#define UVD_RB_ARB_CTRL__SRBM_DIS_MASK                                                                        0x00000002L
>+#define UVD_RB_ARB_CTRL__VCPU_DROP_MASK                                                                       0x00000004L
>+#define UVD_RB_ARB_CTRL__VCPU_DIS_MASK                                                                        0x00000008L
>+#define UVD_RB_ARB_CTRL__RBC_DROP_MASK                                                                        0x00000010L
>+#define UVD_RB_ARB_CTRL__RBC_DIS_MASK                                                                         0x00000020L
>+#define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK                                                                     0x00000040L
>+#define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK                                                                      0x00000080L
>+#define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK                                                                    0x00000100L
>+//UVD_CTX_INDEX
>+#define UVD_CTX_INDEX__INDEX__SHIFT                                                                           0x0
>+#define UVD_CTX_INDEX__INDEX_MASK                                                                             0x000001FFL
>+//UVD_CTX_DATA
>+#define UVD_CTX_DATA__DATA__SHIFT                                                                             0x0
>+#define UVD_CTX_DATA__DATA_MASK                                                                               0xFFFFFFFFL
>+//UVD_CXW_WR
>+#define UVD_CXW_WR__DAT__SHIFT                                                                                0x0
>+#define UVD_CXW_WR__STAT__SHIFT                                                                               0x1f
>+#define UVD_CXW_WR__DAT_MASK                                                                                  0x0FFFFFFFL
>+#define UVD_CXW_WR__STAT_MASK                                                                                 0x80000000L
>+//UVD_CXW_WR_INT_ID
>+#define UVD_CXW_WR_INT_ID__ID__SHIFT                                                                          0x0
>+#define UVD_CXW_WR_INT_ID__ID_MASK                                                                            0x000000FFL
>+//UVD_CXW_WR_INT_CTX_ID
>+#define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT                                                                      0x0
>+#define UVD_CXW_WR_INT_CTX_ID__ID_MASK                                                                        0x0FFFFFFFL
>+//UVD_CXW_INT_ID
>+#define UVD_CXW_INT_ID__ID__SHIFT                                                                             0x0
>+#define UVD_CXW_INT_ID__ID_MASK                                                                               0x000000FFL
>+//UVD_TOP_CTRL
>+#define UVD_TOP_CTRL__STANDARD__SHIFT                                                                         0x0
>+#define UVD_TOP_CTRL__STD_VERSION__SHIFT                                                                      0x4
>+#define UVD_TOP_CTRL__STANDARD_MASK                                                                           0x0000000FL
>+#define UVD_TOP_CTRL__STD_VERSION_MASK                                                                        0x000000F0L
>+//UVD_YBASE
>+#define UVD_YBASE__DUM__SHIFT                                                                                 0x0
>+#define UVD_YBASE__DUM_MASK                                                                                   0xFFFFFFFFL
>+//UVD_UVBASE
>+#define UVD_UVBASE__DUM__SHIFT                                                                                0x0
>+#define UVD_UVBASE__DUM_MASK                                                                                  0xFFFFFFFFL
>+//UVD_PITCH
>+#define UVD_PITCH__DUM__SHIFT                                                                                 0x0
>+#define UVD_PITCH__DUM_MASK                                                                                   0xFFFFFFFFL
>+//UVD_WIDTH
>+#define UVD_WIDTH__DUM__SHIFT                                                                                 0x0
>+#define UVD_WIDTH__DUM_MASK                                                                                   0xFFFFFFFFL
>+//UVD_HEIGHT
>+#define UVD_HEIGHT__DUM__SHIFT                                                                                0x0
>+#define UVD_HEIGHT__DUM_MASK                                                                                  0xFFFFFFFFL
>+//UVD_PICCOUNT
>+#define UVD_PICCOUNT__DUM__SHIFT                                                                              0x0
>+#define UVD_PICCOUNT__DUM_MASK                                                                                0xFFFFFFFFL
>+//UVD_SCRATCH_NP
>+#define UVD_SCRATCH_NP__DATA__SHIFT                                                                           0x0
>+#define UVD_SCRATCH_NP__DATA_MASK                                                                             0xFFFFFFFFL
>+//UVD_VERSION
>+#define UVD_VERSION__MINOR_VERSION__SHIFT                                                                     0x0
>+#define UVD_VERSION__MAJOR_VERSION__SHIFT                                                                     0x10
>+#define UVD_VERSION__MINOR_VERSION_MASK                                                                       0x0000FFFFL
>+#define UVD_VERSION__MAJOR_VERSION_MASK                                                                       0x0FFF0000L
>+//UVD_GP_SCRATCH0
>+#define UVD_GP_SCRATCH0__DATA__SHIFT                                                                          0x0
>+#define UVD_GP_SCRATCH0__DATA_MASK                                                                            0xFFFFFFFFL
>+//UVD_GP_SCRATCH1
>+#define UVD_GP_SCRATCH1__DATA__SHIFT                                                                          0x0
>+#define UVD_GP_SCRATCH1__DATA_MASK                                                                            0xFFFFFFFFL
>+//UVD_GP_SCRATCH2
>+#define UVD_GP_SCRATCH2__DATA__SHIFT                                                                          0x0
>+#define UVD_GP_SCRATCH2__DATA_MASK                                                                            0xFFFFFFFFL
>+//UVD_GP_SCRATCH3
>+#define UVD_GP_SCRATCH3__DATA__SHIFT                                                                          0x0
>+#define UVD_GP_SCRATCH3__DATA_MASK                                                                            0xFFFFFFFFL
>+//UVD_GP_SCRATCH4
>+#define UVD_GP_SCRATCH4__DATA__SHIFT                                                                          0x0
>+#define UVD_GP_SCRATCH4__DATA_MASK                                                                            0xFFFFFFFFL
>+//UVD_GP_SCRATCH5
>+#define UVD_GP_SCRATCH5__DATA__SHIFT                                                                          0x0
>+#define UVD_GP_SCRATCH5__DATA_MASK                                                                            0xFFFFFFFFL
>+//UVD_GP_SCRATCH6
>+#define UVD_GP_SCRATCH6__DATA__SHIFT                                                                          0x0
>+#define UVD_GP_SCRATCH6__DATA_MASK                                                                            0xFFFFFFFFL
>+//UVD_GP_SCRATCH7
>+#define UVD_GP_SCRATCH7__DATA__SHIFT                                                                          0x0
>+#define UVD_GP_SCRATCH7__DATA_MASK                                                                            0xFFFFFFFFL
>+//UVD_GP_SCRATCH8
>+#define UVD_GP_SCRATCH8__DATA__SHIFT                                                                          0x0
>+#define UVD_GP_SCRATCH8__DATA_MASK                                                                            0xFFFFFFFFL
>+//UVD_GP_SCRATCH9
>+#define UVD_GP_SCRATCH9__DATA__SHIFT                                                                          0x0
>+#define UVD_GP_SCRATCH9__DATA_MASK                                                                            0xFFFFFFFFL
>+//UVD_GP_SCRATCH10
>+#define UVD_GP_SCRATCH10__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH10__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH11
>+#define UVD_GP_SCRATCH11__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH11__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH12
>+#define UVD_GP_SCRATCH12__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH12__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH13
>+#define UVD_GP_SCRATCH13__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH13__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH14
>+#define UVD_GP_SCRATCH14__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH14__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH15
>+#define UVD_GP_SCRATCH15__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH15__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH16
>+#define UVD_GP_SCRATCH16__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH16__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH17
>+#define UVD_GP_SCRATCH17__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH17__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH18
>+#define UVD_GP_SCRATCH18__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH18__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH19
>+#define UVD_GP_SCRATCH19__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH19__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH20
>+#define UVD_GP_SCRATCH20__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH20__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH21
>+#define UVD_GP_SCRATCH21__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH21__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH22
>+#define UVD_GP_SCRATCH22__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH22__DATA_MASK                                                                           0xFFFFFFFFL
>+//UVD_GP_SCRATCH23
>+#define UVD_GP_SCRATCH23__DATA__SHIFT                                                                         0x0
>+#define UVD_GP_SCRATCH23__DATA_MASK                                                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: uvd0_ecpudec
>+//UVD_VCPU_CACHE_OFFSET0
>+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT                                                          0x0
>+#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK                                                            0x001FFFFFL
>+//UVD_VCPU_CACHE_SIZE0
>+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT                                                              0x0
>+#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK                                                                0x001FFFFFL
>+//UVD_VCPU_CACHE_OFFSET1
>+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT                                                          0x0
>+#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK                                                            0x001FFFFFL
>+//UVD_VCPU_CACHE_SIZE1
>+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT                                                              0x0
>+#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK                                                                0x001FFFFFL
>+//UVD_VCPU_CACHE_OFFSET2
>+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT                                                          0x0
>+#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK                                                            0x001FFFFFL
>+//UVD_VCPU_CACHE_SIZE2
>+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT                                                              0x0
>+#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK                                                                0x001FFFFFL
>+//UVD_VCPU_CACHE_OFFSET3
>+#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT                                                          0x0
>+#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK                                                            0x001FFFFFL
>+//UVD_VCPU_CACHE_SIZE3
>+#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT                                                              0x0
>+#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK                                                                0x001FFFFFL
>+//UVD_VCPU_CACHE_OFFSET4
>+#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT                                                          0x0
>+#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK                                                            0x001FFFFFL
>+//UVD_VCPU_CACHE_SIZE4
>+#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT                                                              0x0
>+#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK                                                                0x001FFFFFL
>+//UVD_VCPU_CACHE_OFFSET5
>+#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT                                                          0x0
>+#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK                                                            0x001FFFFFL
>+//UVD_VCPU_CACHE_SIZE5
>+#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT                                                              0x0
>+#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK                                                                0x001FFFFFL
>+//UVD_VCPU_CACHE_OFFSET6
>+#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT                                                          0x0
>+#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK                                                            0x001FFFFFL
>+//UVD_VCPU_CACHE_SIZE6
>+#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT                                                              0x0
>+#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK                                                                0x001FFFFFL
>+//UVD_VCPU_CACHE_OFFSET7
>+#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT                                                          0x0
>+#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK                                                            0x001FFFFFL
>+//UVD_VCPU_CACHE_SIZE7
>+#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT                                                              0x0
>+#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK                                                                0x001FFFFFL
>+//UVD_VCPU_CACHE_OFFSET8
>+#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT                                                          0x0
>+#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK                                                            0x001FFFFFL
>+//UVD_VCPU_CACHE_SIZE8
>+#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT                                                              0x0
>+#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK                                                                0x001FFFFFL
>+//UVD_VCPU_NONCACHE_OFFSET0
>+#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT                                                    0x0
>+#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK                                                      0x01FFFFFFL
>+//UVD_VCPU_NONCACHE_SIZE0
>+#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT                                                        0x0
>+#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK                                                          0x001FFFFFL
>+//UVD_VCPU_NONCACHE_OFFSET1
>+#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT                                                    0x0
>+#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK                                                      0x01FFFFFFL
>+//UVD_VCPU_NONCACHE_SIZE1
>+#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT                                                        0x0
>+#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK                                                          0x001FFFFFL
>+//UVD_VCPU_CNTL
>+#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT                                                                         0x0
>+#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT                                                                   0x5
>+#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT                                                                  0x6
>+#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT                                                                 0x7
>+#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT                                                                       0x8
>+#define UVD_VCPU_CNTL__CLK_EN__SHIFT                                                                          0x9
>+#define UVD_VCPU_CNTL__TRCE_EN__SHIFT                                                                         0xa
>+#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT                                                                        0xb
>+#define UVD_VCPU_CNTL__JTAG_EN__SHIFT                                                                         0x10
>+#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT                                                                     0x12
>+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT                                                                 0x14
>+#define UVD_VCPU_CNTL__BLK_RST__SHIFT                                                                         0x1c
>+#define UVD_VCPU_CNTL__IRQ_ERR_MASK                                                                           0x0000000FL
>+#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK                                                                     0x00000020L
>+#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK                                                                    0x00000040L
>+#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK                                                                   0x00000080L
>+#define UVD_VCPU_CNTL__ABORT_REQ_MASK                                                                         0x00000100L
>+#define UVD_VCPU_CNTL__CLK_EN_MASK                                                                            0x00000200L
>+#define UVD_VCPU_CNTL__TRCE_EN_MASK                                                                           0x00000400L
>+#define UVD_VCPU_CNTL__TRCE_MUX_MASK                                                                          0x00001800L
>+#define UVD_VCPU_CNTL__JTAG_EN_MASK                                                                           0x00010000L
>+#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK                                                                       0x00040000L
>+#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK                                                                   0x0FF00000L
>+#define UVD_VCPU_CNTL__BLK_RST_MASK                                                                           0x10000000L
>+//UVD_VCPU_PRID
>+#define UVD_VCPU_PRID__PRID__SHIFT                                                                            0x0
>+#define UVD_VCPU_PRID__PRID_MASK                                                                              0x0000FFFFL
>+//UVD_VCPU_TRCE
>+#define UVD_VCPU_TRCE__PC__SHIFT                                                                              0x0
>+#define UVD_VCPU_TRCE__PC_MASK                                                                                0x0FFFFFFFL
>+//UVD_VCPU_TRCE_RD
>+#define UVD_VCPU_TRCE_RD__DATA__SHIFT                                                                         0x0
>+#define UVD_VCPU_TRCE_RD__DATA_MASK                                                                           0xFFFFFFFFL
>+
>+
>+// addressBlock: uvd0_uvd_mpcdec
>+//UVD_MP_SWAP_CNTL
>+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT                                                              0x0
>+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT                                                              0x2
>+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT                                                              0x4
>+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT                                                              0x6
>+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT                                                              0x8
>+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT                                                              0xa
>+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT                                                              0xc
>+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT                                                              0xe
>+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT                                                              0x10
>+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT                                                              0x12
>+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT                                                             0x14
>+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT                                                             0x16
>+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT                                                             0x18
>+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT                                                             0x1a
>+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT                                                             0x1c
>+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT                                                             0x1e
>+#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK                                                                0x00000003L
>+#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK                                                                0x0000000CL
>+#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK                                                                0x00000030L
>+#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK                                                                0x000000C0L
>+#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK                                                                0x00000300L
>+#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK                                                                0x00000C00L
>+#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK                                                                0x00003000L
>+#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK                                                                0x0000C000L
>+#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK                                                                0x00030000L
>+#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK                                                                0x000C0000L
>+#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK                                                               0x00300000L
>+#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK                                                               0x00C00000L
>+#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK                                                               0x03000000L
>+#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK                                                               0x0C000000L
>+#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK                                                               0x30000000L
>+#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK                                                               0xC0000000L
>+//UVD_MPC_LUMA_SRCH
>+#define UVD_MPC_LUMA_SRCH__CNTR__SHIFT                                                                        0x0
>+#define UVD_MPC_LUMA_SRCH__CNTR_MASK                                                                          0xFFFFFFFFL
>+//UVD_MPC_LUMA_HIT
>+#define UVD_MPC_LUMA_HIT__CNTR__SHIFT                                                                         0x0
>+#define UVD_MPC_LUMA_HIT__CNTR_MASK                                                                           0xFFFFFFFFL
>+//UVD_MPC_LUMA_HITPEND
>+#define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT                                                                     0x0
>+#define UVD_MPC_LUMA_HITPEND__CNTR_MASK                                                                       0xFFFFFFFFL
>+//UVD_MPC_CHROMA_SRCH
>+#define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT                                                                      0x0
>+#define UVD_MPC_CHROMA_SRCH__CNTR_MASK                                                                        0xFFFFFFFFL
>+//UVD_MPC_CHROMA_HIT
>+#define UVD_MPC_CHROMA_HIT__CNTR__SHIFT                                                                       0x0
>+#define UVD_MPC_CHROMA_HIT__CNTR_MASK                                                                         0xFFFFFFFFL
>+//UVD_MPC_CHROMA_HITPEND
>+#define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT                                                                   0x0
>+#define UVD_MPC_CHROMA_HITPEND__CNTR_MASK                                                                     0xFFFFFFFFL
>+//UVD_MPC_CNTL
>+#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT                                                                 0x3
>+#define UVD_MPC_CNTL__PERF_RST__SHIFT                                                                         0x6
>+#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT                                                                       0x10
>+#define UVD_MPC_CNTL__URGENT_EN__SHIFT                                                                        0x12
>+#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT                                                               0x13
>+#define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT                                                                     0x14
>+#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK                                                                   0x00000038L
>+#define UVD_MPC_CNTL__PERF_RST_MASK                                                                           0x00000040L
>+#define UVD_MPC_CNTL__AVE_WEIGHT_MASK                                                                         0x00030000L
>+#define UVD_MPC_CNTL__URGENT_EN_MASK                                                                          0x00040000L
>+#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK                                                                 0x00080000L
>+#define UVD_MPC_CNTL__TEST_MODE_EN_MASK                                                                       0x00100000L
>+//UVD_MPC_PITCH
>+#define UVD_MPC_PITCH__LUMA_PITCH__SHIFT                                                                      0x0
>+#define UVD_MPC_PITCH__LUMA_PITCH_MASK                                                                        0x000007FFL
>+//UVD_MPC_SET_MUXA0
>+#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT                                                                      0x0
>+#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT                                                                      0x6
>+#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT                                                                      0xc
>+#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT                                                                      0x12
>+#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT                                                                      0x18
>+#define UVD_MPC_SET_MUXA0__VARA_0_MASK                                                                        0x0000003FL
>+#define UVD_MPC_SET_MUXA0__VARA_1_MASK                                                                        0x00000FC0L
>+#define UVD_MPC_SET_MUXA0__VARA_2_MASK                                                                        0x0003F000L
>+#define UVD_MPC_SET_MUXA0__VARA_3_MASK                                                                        0x00FC0000L
>+#define UVD_MPC_SET_MUXA0__VARA_4_MASK                                                                        0x3F000000L
>+//UVD_MPC_SET_MUXA1
>+#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT                                                                      0x0
>+#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT                                                                      0x6
>+#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT                                                                      0xc
>+#define UVD_MPC_SET_MUXA1__VARA_5_MASK                                                                        0x0000003FL
>+#define UVD_MPC_SET_MUXA1__VARA_6_MASK                                                                        0x00000FC0L
>+#define UVD_MPC_SET_MUXA1__VARA_7_MASK                                                                        0x0003F000L
>+//UVD_MPC_SET_MUXB0
>+#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT                                                                      0x0
>+#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT                                                                      0x6
>+#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT                                                                      0xc
>+#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT                                                                      0x12
>+#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT                                                                      0x18
>+#define UVD_MPC_SET_MUXB0__VARB_0_MASK                                                                        0x0000003FL
>+#define UVD_MPC_SET_MUXB0__VARB_1_MASK                                                                        0x00000FC0L
>+#define UVD_MPC_SET_MUXB0__VARB_2_MASK                                                                        0x0003F000L
>+#define UVD_MPC_SET_MUXB0__VARB_3_MASK                                                                        0x00FC0000L
>+#define UVD_MPC_SET_MUXB0__VARB_4_MASK                                                                        0x3F000000L
>+//UVD_MPC_SET_MUXB1
>+#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT                                                                      0x0
>+#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT                                                                      0x6
>+#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT                                                                      0xc
>+#define UVD_MPC_SET_MUXB1__VARB_5_MASK                                                                        0x0000003FL
>+#define UVD_MPC_SET_MUXB1__VARB_6_MASK                                                                        0x00000FC0L
>+#define UVD_MPC_SET_MUXB1__VARB_7_MASK                                                                        0x0003F000L
>+//UVD_MPC_SET_MUX
>+#define UVD_MPC_SET_MUX__SET_0__SHIFT                                                                         0x0
>+#define UVD_MPC_SET_MUX__SET_1__SHIFT                                                                         0x3
>+#define UVD_MPC_SET_MUX__SET_2__SHIFT                                                                         0x6
>+#define UVD_MPC_SET_MUX__SET_0_MASK                                                                           0x00000007L
>+#define UVD_MPC_SET_MUX__SET_1_MASK                                                                           0x00000038L
>+#define UVD_MPC_SET_MUX__SET_2_MASK                                                                           0x000001C0L
>+//UVD_MPC_SET_ALU
>+#define UVD_MPC_SET_ALU__FUNCT__SHIFT                                                                         0x0
>+#define UVD_MPC_SET_ALU__OPERAND__SHIFT                                                                       0x4
>+#define UVD_MPC_SET_ALU__FUNCT_MASK                                                                           0x00000007L
>+#define UVD_MPC_SET_ALU__OPERAND_MASK                                                                         0x00000FF0L
>+//UVD_MPC_PERF0
>+#define UVD_MPC_PERF0__MAX_LAT__SHIFT                                                                         0x0
>+#define UVD_MPC_PERF0__MAX_LAT_MASK                                                                           0x000003FFL
>+//UVD_MPC_PERF1
>+#define UVD_MPC_PERF1__AVE_LAT__SHIFT                                                                         0x0
>+#define UVD_MPC_PERF1__AVE_LAT_MASK                                                                           0x000003FFL
>+
>+
>+// addressBlock: uvd0_uvd_rbcdec
>+//UVD_RBC_IB_SIZE
>+#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT                                                                       0x4
>+#define UVD_RBC_IB_SIZE__IB_SIZE_MASK                                                                         0x007FFFF0L
>+//UVD_RBC_IB_SIZE_UPDATE
>+#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT                                                         0x4
>+#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK                                                           0x007FFFF0L
>+//UVD_RBC_RB_CNTL
>+#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT                                                                      0x0
>+#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT                                                                      0x8
>+#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT                                                                   0x10
>+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT                                                               0x14
>+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT                                                                  0x18
>+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT                                                                 0x1c
>+#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK                                                                        0x0000001FL
>+#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK                                                                        0x00001F00L
>+#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK                                                                     0x00010000L
>+#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK                                                                 0x00100000L
>+#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK                                                                    0x01000000L
>+#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK                                                                   0x10000000L
>+//UVD_RBC_RB_RPTR_ADDR
>+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT                                                             0x0
>+#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK                                                               0xFFFFFFFFL
>+//UVD_RBC_RB_RPTR
>+#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT                                                                       0x4
>+#define UVD_RBC_RB_RPTR__RB_RPTR_MASK                                                                         0x007FFFF0L
>+//UVD_RBC_RB_WPTR
>+#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT                                                                       0x4
>+#define UVD_RBC_RB_WPTR__RB_WPTR_MASK                                                                         0x007FFFF0L
>+//UVD_RBC_VCPU_ACCESS
>+#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT                                                                0x0
>+#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK                                                                  0x00000001L
>+//UVD_RBC_READ_REQ_URGENT_CNTL
>+#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT                                       0x0
>+#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK                                         0x00000003L
>+//UVD_RBC_RB_WPTR_CNTL
>+#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT                                                       0x0
>+#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK                                                         0x00007FFFL
>+//UVD_RBC_WPTR_STATUS
>+#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT                                                            0x4
>+#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK                                                              0x007FFFF0L
>+//UVD_RBC_WPTR_POLL_CNTL
>+#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT                                                              0x0
>+#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT                                                        0x10
>+#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK                                                                0x0000FFFFL
>+#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK                                                          0xFFFF0000L
>+//UVD_RBC_WPTR_POLL_ADDR
>+#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT                                                              0x2
>+#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK                                                                0xFFFFFFFCL
>+//UVD_SEMA_CMD
>+#define UVD_SEMA_CMD__REQ_CMD__SHIFT                                                                          0x0
>+#define UVD_SEMA_CMD__WR_PHASE__SHIFT                                                                         0x4
>+#define UVD_SEMA_CMD__MODE__SHIFT                                                                             0x6
>+#define UVD_SEMA_CMD__VMID_EN__SHIFT                                                                          0x7
>+#define UVD_SEMA_CMD__VMID__SHIFT                                                                             0x8
>+#define UVD_SEMA_CMD__REQ_CMD_MASK                                                                            0x0000000FL
>+#define UVD_SEMA_CMD__WR_PHASE_MASK                                                                           0x00000030L
>+#define UVD_SEMA_CMD__MODE_MASK                                                                               0x00000040L
>+#define UVD_SEMA_CMD__VMID_EN_MASK                                                                            0x00000080L
>+#define UVD_SEMA_CMD__VMID_MASK                                                                               0x00000F00L
>+//UVD_SEMA_ADDR_LOW
>+#define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT                                                                   0x0
>+#define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK                                                                     0x00FFFFFFL
>+//UVD_SEMA_ADDR_HIGH
>+#define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT                                                                 0x0
>+#define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK                                                                   0x001FFFFFL
>+//UVD_ENGINE_CNTL
>+#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT                                                                  0x0
>+#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT                                                             0x1
>+#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT                                                          0x2
>+#define UVD_ENGINE_CNTL__ENGINE_START_MASK                                                                    0x00000001L
>+#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK                                                               0x00000002L
>+#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK                                                            0x00000004L
>+//UVD_SEMA_TIMEOUT_STATUS
>+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT                                0x0
>+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT                                     0x1
>+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT                              0x2
>+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT                                               0x3
>+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK                                  0x00000001L
>+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK                                       0x00000002L
>+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK                                0x00000004L
>+#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK                                                 0x00000008L
>+//UVD_SEMA_CNTL
>+#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT                                                                    0x0
>+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT                                                               0x1
>+#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK                                                                      0x00000001L
>+#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK                                                                 0x00000002L
>+//UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
>+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT                                  0x0
>+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT                               0x1
>+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT                                          0x18
>+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK                                    0x00000001L
>+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK                                 0x001FFFFEL
>+#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK                                            0x07000000L
>+//UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
>+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT                                                0x0
>+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT                                             0x1
>+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT                                                 0x18
>+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK                                                  0x00000001L
>+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK                                               0x001FFFFEL
>+#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK                                                   0x07000000L
>+//UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
>+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT                                      0x0
>+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT                                   0x1
>+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT                                            0x18
>+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK                                        0x00000001L
>+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK                                     0x001FFFFEL
>+#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK                                              0x07000000L
>+//UVD_JOB_START
>+#define UVD_JOB_START__JOB_START__SHIFT                                                                       0x0
>+#define UVD_JOB_START__JOB_START_MASK                                                                         0x00000001L
>+//UVD_RBC_BUF_STATUS
>+#define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT                                                               0x0
>+#define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT                                                               0x8
>+#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT                                                             0x10
>+#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT                                                             0x13
>+#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT                                                             0x16
>+#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT                                                             0x19
>+#define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK                                                                 0x000000FFL
>+#define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK                                                                 0x0000FF00L
>+#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK                                                               0x00070000L
>+#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK                                                               0x00380000L
>+#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK                                                               0x01C00000L
>+#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK                                                               0x0E000000L
>+
>+
>+// addressBlock: uvd0_uvdgendec
>+//UVD_LCM_CGC_CNTRL
>+#define UVD_LCM_CGC_CNTRL__FORCE_OFF__SHIFT                                                                   0x12
>+#define UVD_LCM_CGC_CNTRL__FORCE_ON__SHIFT                                                                    0x13
>+#define UVD_LCM_CGC_CNTRL__OFF_DELAY__SHIFT                                                                   0x14
>+#define UVD_LCM_CGC_CNTRL__ON_DELAY__SHIFT                                                                    0x1c
>+#define UVD_LCM_CGC_CNTRL__FORCE_OFF_MASK                                                                     0x00040000L
>+#define UVD_LCM_CGC_CNTRL__FORCE_ON_MASK                                                                      0x00080000L
>+#define UVD_LCM_CGC_CNTRL__OFF_DELAY_MASK                                                                     0x0FF00000L
>+#define UVD_LCM_CGC_CNTRL__ON_DELAY_MASK                                                                      0xF0000000L
>+
>+
>+// addressBlock: uvd0_lmi_adpdec
>+//UVD_LMI_RBC_RB_64BIT_BAR_LOW
>+#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                        0x0
>+#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK                                                          0xFFFFFFFFL
>+//UVD_LMI_RBC_RB_64BIT_BAR_HIGH
>+#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                      0x0
>+#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                        0xFFFFFFFFL
>+//UVD_LMI_RBC_IB_64BIT_BAR_LOW
>+#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                        0x0
>+#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK                                                          0xFFFFFFFFL
>+//UVD_LMI_RBC_IB_64BIT_BAR_HIGH
>+#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                      0x0
>+#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK                                                        0xFFFFFFFFL
>+//UVD_LMI_LBSI_64BIT_BAR_LOW
>+#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                          0x0
>+#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK                                                            0xFFFFFFFFL
>+//UVD_LMI_LBSI_64BIT_BAR_HIGH
>+#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                        0x0
>+#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK                                                          0xFFFFFFFFL
>+//UVD_LMI_VCPU_NC0_64BIT_BAR_LOW
>+#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                      0x0
>+#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK                                                        0xFFFFFFFFL
>+//UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH
>+#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                    0x0
>+#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK                                                      0xFFFFFFFFL
>+//UVD_LMI_VCPU_NC1_64BIT_BAR_LOW
>+#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                      0x0
>+#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK                                                        0xFFFFFFFFL
>+//UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH
>+#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                    0x0
>+#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK                                                      0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW
>+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                    0x0
>+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK                                                      0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
>+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                  0x0
>+#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK                                                    0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW
>+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
>+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH
>+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
>+#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW
>+#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
>+#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH
>+#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
>+#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW
>+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
>+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH
>+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
>+#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW
>+#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
>+#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH
>+#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
>+#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW
>+#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
>+#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH
>+#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
>+#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW
>+#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
>+#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH
>+#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
>+#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW
>+#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
>+#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH
>+#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
>+#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW
>+#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                   0x0
>+#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH
>+#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                 0x0
>+#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK                                                   0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW
>+#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                     0x0
>+#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK                                                       0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH
>+#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                   0x0
>+#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW
>+#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                     0x0
>+#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK                                                       0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH
>+#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                   0x0
>+#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW
>+#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                     0x0
>+#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK                                                       0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH
>+#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                   0x0
>+#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW
>+#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                     0x0
>+#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK                                                       0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH
>+#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                   0x0
>+#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW
>+#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                     0x0
>+#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK                                                       0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH
>+#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                   0x0
>+#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW
>+#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                     0x0
>+#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK                                                       0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH
>+#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                   0x0
>+#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW
>+#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                     0x0
>+#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK                                                       0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH
>+#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                   0x0
>+#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW
>+#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT                                                     0x0
>+#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK                                                       0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH
>+#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT                                                   0x0
>+#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK                                                     0xFFFFFFFFL
>+//UVD_LMI_MMSCH_NC_VMID
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT                                                          0x0
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT                                                          0x4
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT                                                          0x8
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT                                                          0xc
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT                                                          0x10
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT                                                          0x14
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT                                                          0x18
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT                                                          0x1c
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK                                                            0x0000000FL
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK                                                            0x000000F0L
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK                                                            0x00000F00L
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK                                                            0x0000F000L
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK                                                            0x000F0000L
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK                                                            0x00F00000L
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK                                                            0x0F000000L
>+#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK                                                            0xF0000000L
>+//UVD_LMI_MMSCH_CTRL
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT                                                    0x0
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT                                                                   0x1
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT                                                            0x3
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT                                                            0x5
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT                                                                   0x7
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT                                                                   0x9
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT                                                              0xb
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT                                                              0xc
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK                                                      0x00000001L
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK                                                                     0x00000002L
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK                                                              0x00000018L
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK                                                              0x00000060L
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK                                                                     0x00000180L
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK                                                                     0x00000600L
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK                                                                0x00000800L
>+#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK                                                                0x00001000L
>+//UVD_LMI_ARB_CTRL2
>+#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT                                                             0x0
>+#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT                                                           0x1
>+#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT                                                           0x2
>+#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT                                                         0x6
>+#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT                                                          0xa
>+#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT                                                          0x14
>+#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK                                                               0x00000001L
>+#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK                                                             0x00000002L
>+#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK                                                             0x0000003CL
>+#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK                                                           0x000003C0L
>+#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK                                                            0x000FFC00L
>+#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK                                                            0xFFF00000L
>+//UVD_LMI_VCPU_CACHE_VMIDS_MULTI
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT                                               0x0
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT                                               0x4
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT                                               0x8
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT                                               0xc
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT                                               0x10
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT                                               0x14
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT                                               0x18
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT                                               0x1c
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK                                                 0x0000000FL
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK                                                 0x000000F0L
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK                                                 0x00000F00L
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK                                                 0x0000F000L
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK                                                 0x000F0000L
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK                                                 0x00F00000L
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK                                                 0x0F000000L
>+#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK                                                 0xF0000000L
>+//UVD_LMI_VCPU_NC_VMIDS_MULTI
>+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT                                                     0x4
>+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT                                                     0x8
>+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT                                                     0xc
>+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT                                                     0x10
>+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT                                                     0x14
>+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT                                                     0x18
>+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK                                                       0x000000F0L
>+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK                                                       0x00000F00L
>+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK                                                       0x0000F000L
>+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK                                                       0x000F0000L
>+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK                                                       0x00F00000L
>+#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK                                                       0x0F000000L
>+//UVD_LMI_LAT_CTRL
>+#define UVD_LMI_LAT_CTRL__SCALE__SHIFT                                                                        0x0
>+#define UVD_LMI_LAT_CTRL__MAX_START__SHIFT                                                                    0x8
>+#define UVD_LMI_LAT_CTRL__MIN_START__SHIFT                                                                    0x9
>+#define UVD_LMI_LAT_CTRL__AVG_START__SHIFT                                                                    0xa
>+#define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT                                                                 0xb
>+#define UVD_LMI_LAT_CTRL__SKIP__SHIFT                                                                         0x10
>+#define UVD_LMI_LAT_CTRL__SCALE_MASK                                                                          0x000000FFL
>+#define UVD_LMI_LAT_CTRL__MAX_START_MASK                                                                      0x00000100L
>+#define UVD_LMI_LAT_CTRL__MIN_START_MASK                                                                      0x00000200L
>+#define UVD_LMI_LAT_CTRL__AVG_START_MASK                                                                      0x00000400L
>+#define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK                                                                   0x00000800L
>+#define UVD_LMI_LAT_CTRL__SKIP_MASK                                                                           0x000F0000L
>+//UVD_LMI_LAT_CNTR
>+#define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT                                                                      0x0
>+#define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT                                                                      0x8
>+#define UVD_LMI_LAT_CNTR__MAX_LAT_MASK                                                                        0x000000FFL
>+#define UVD_LMI_LAT_CNTR__MIN_LAT_MASK                                                                        0x0000FF00L
>+//UVD_LMI_AVG_LAT_CNTR
>+#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT                                                                  0x0
>+#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT                                                                 0x8
>+#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT                                                                  0x10
>+#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK                                                                    0x000000FFL
>+#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK                                                                   0x0000FF00L
>+#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK                                                                    0xFFFF0000L
>+//UVD_LMI_SPH
>+#define UVD_LMI_SPH__ADDR__SHIFT                                                                              0x0
>+#define UVD_LMI_SPH__STS__SHIFT                                                                               0x1c
>+#define UVD_LMI_SPH__STS_VALID__SHIFT                                                                         0x1e
>+#define UVD_LMI_SPH__STS_OVERFLOW__SHIFT                                                                      0x1f
>+#define UVD_LMI_SPH__ADDR_MASK                                                                                0x0FFFFFFFL
>+#define UVD_LMI_SPH__STS_MASK                                                                                 0x30000000L
>+#define UVD_LMI_SPH__STS_VALID_MASK                                                                           0x40000000L
>+#define UVD_LMI_SPH__STS_OVERFLOW_MASK                                                                        0x80000000L
>+//UVD_LMI_VCPU_CACHE_VMID
>+#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT                                                       0x0
>+#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK                                                         0x0000000FL
>+//UVD_LMI_CTRL2
>+#define UVD_LMI_CTRL2__SPH_DIS__SHIFT                                                                         0x0
>+#define UVD_LMI_CTRL2__STALL_ARB__SHIFT                                                                       0x1
>+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT                                                               0x2
>+#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT                                                                 0x3
>+#define UVD_LMI_CTRL2__CRC1_RESET__SHIFT                                                                      0x4
>+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT                                                           0x7
>+#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT                                                                   0x8
>+#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT                                                                  0x9
>+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT                                                                 0xb
>+#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT                                                                 0xd
>+#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT                                                                 0xe
>+#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT                                                                0xf
>+#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT                                                                   0x10
>+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT                                                          0x11
>+#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT                                                                  0x19
>+#define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT                                                                   0x1a
>+#define UVD_LMI_CTRL2__CRC1_SEL__SHIFT                                                                        0x1b
>+#define UVD_LMI_CTRL2__SPH_DIS_MASK                                                                           0x00000001L
>+#define UVD_LMI_CTRL2__STALL_ARB_MASK                                                                         0x00000002L
>+#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK                                                                 0x00000004L
>+#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK                                                                   0x00000008L
>+#define UVD_LMI_CTRL2__CRC1_RESET_MASK                                                                        0x00000010L
>+#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK                                                             0x00000080L
>+#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK                                                                     0x00000100L
>+#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK                                                                    0x00000600L
>+#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK                                                                   0x00001800L
>+#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK                                                                   0x00002000L
>+#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK                                                                   0x00004000L
>+#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK                                                                  0x00008000L
>+#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK                                                                     0x00010000L
>+#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK                                                            0x01FE0000L
>+#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK                                                                    0x02000000L
>+#define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK                                                                     0x04000000L
>+#define UVD_LMI_CTRL2__CRC1_SEL_MASK                                                                          0xF8000000L
>+//UVD_LMI_URGENT_CTRL
>+#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT                                                 0x0
>+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT                                                        0x1
>+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT                                                       0x2
>+#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT                                                 0x8
>+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT                                                        0x9
>+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT                                                       0xa
>+#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT                                                0x10
>+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT                                                       0x11
>+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT                                                      0x12
>+#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT                                                0x18
>+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT                                                       0x19
>+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT                                                      0x1a
>+#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK                                                   0x00000001L
>+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK                                                          0x00000002L
>+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK                                                         0x0000003CL
>+#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK                                                   0x00000100L
>+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK                                                          0x00000200L
>+#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK                                                         0x00003C00L
>+#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK                                                  0x00010000L
>+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK                                                         0x00020000L
>+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK                                                        0x003C0000L
>+#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK                                                  0x01000000L
>+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK                                                         0x02000000L
>+#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK                                                        0x3C000000L
>+//UVD_LMI_CTRL
>+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT                                                                0x0
>+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT                                                             0x8
>+#define UVD_LMI_CTRL__REQ_MODE__SHIFT                                                                         0x9
>+#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT                                                                 0xb
>+#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT                                                                   0xc
>+#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT                                                                0xd
>+#define UVD_LMI_CTRL__CRC_RESET__SHIFT                                                                        0xe
>+#define UVD_LMI_CTRL__CRC_SEL__SHIFT                                                                          0xf
>+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT                                                           0x15
>+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT                                                             0x16
>+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT                                                          0x17
>+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT                                                          0x18
>+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT                                                          0x19
>+#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT                                                        0x1a
>+#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT                                                      0x1b
>+#define UVD_LMI_CTRL__RFU__SHIFT                                                                              0x1e
>+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK                                                                  0x000000FFL
>+#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK                                                               0x00000100L
>+#define UVD_LMI_CTRL__REQ_MODE_MASK                                                                           0x00000200L
>+#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK                                                                   0x00000800L
>+#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK                                                                     0x00001000L
>+#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK                                                                  0x00002000L
>+#define UVD_LMI_CTRL__CRC_RESET_MASK                                                                          0x00004000L
>+#define UVD_LMI_CTRL__CRC_SEL_MASK                                                                            0x000F8000L
>+#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK                                                             0x00200000L
>+#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK                                                               0x00400000L
>+#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK                                                            0x00800000L
>+#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK                                                            0x01000000L
>+#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK                                                            0x02000000L
>+#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK                                                          0x04000000L
>+#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK                                                        0x08000000L
>+#define UVD_LMI_CTRL__RFU_MASK                                                                                0xC0000000L
>+//UVD_LMI_STATUS
>+#define UVD_LMI_STATUS__READ_CLEAN__SHIFT                                                                     0x0
>+#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT                                                                    0x1
>+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT                                                                0x2
>+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT                                                           0x3
>+#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT                                                                 0x4
>+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT                                                                0x5
>+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT                                                            0x6
>+#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT                                                           0x7
>+#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT                                                                 0x8
>+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT                                                             0x9
>+#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT                                                                   0xa
>+#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT                                                                   0xb
>+#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT                                                              0xc
>+#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT                                                             0xd
>+#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT                                                               0x12
>+#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT                                                               0x13
>+#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT                                                               0x14
>+#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT                                                               0x15
>+#define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT                                                                0x16
>+#define UVD_LMI_STATUS__READ_CLEAN_MASK                                                                       0x00000001L
>+#define UVD_LMI_STATUS__WRITE_CLEAN_MASK                                                                      0x00000002L
>+#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK                                                                  0x00000004L
>+#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK                                                             0x00000008L
>+#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK                                                                   0x00000010L
>+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK                                                                  0x00000020L
>+#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK                                                              0x00000040L
>+#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK                                                             0x00000080L
>+#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK                                                                   0x00000100L
>+#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK                                                               0x00000200L
>+#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK                                                                     0x00000400L
>+#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK                                                                     0x00000800L
>+#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK                                                                0x00001000L
>+#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK                                                               0x00002000L
>+#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK                                                                 0x00040000L
>+#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK                                                                 0x00080000L
>+#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK                                                                 0x00100000L
>+#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK                                                                 0x00200000L
>+#define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK                                                                  0x00400000L
>+//UVD_LMI_PERFMON_CTRL
>+#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT                                                            0x0
>+#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT                                                              0x8
>+#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK                                                              0x00000003L
>+#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK                                                                0x00001F00L
>+//UVD_LMI_PERFMON_COUNT_LO
>+#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT                                                        0x0
>+#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK                                                          0xFFFFFFFFL
>+//UVD_LMI_PERFMON_COUNT_HI
>+#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT                                                        0x0
>+#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK                                                          0x0000FFFFL
>+//UVD_LMI_RBC_RB_VMID
>+#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT                                                                   0x0
>+#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK                                                                     0x0000000FL
>+//UVD_LMI_RBC_IB_VMID
>+#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT                                                                   0x0
>+#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK                                                                     0x0000000FL
>+//UVD_LMI_MC_CREDITS
>+#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT                                                             0x0
>+#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT                                                             0x8
>+#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT                                                             0x10
>+#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT                                                             0x18
>+#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK                                                               0x0000003FL
>+#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK                                                               0x00003F00L
>+#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK                                                               0x003F0000L
>+#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK                                                               0x3F000000L
>+
>+
>+// addressBlock: uvd0_uvdnpdec
>+//MDM_DMA_CMD
>+#define MDM_DMA_CMD__MDM_DMA_CMD__SHIFT                                                                       0x0
>+#define MDM_DMA_CMD__MDM_DMA_CMD_MASK                                                                         0xFFFFFFFFL
>+//MDM_DMA_STATUS
>+#define MDM_DMA_STATUS__SDB_DMA_WR_BUSY__SHIFT                                                                0x0
>+#define MDM_DMA_STATUS__SCM_DMA_WR_BUSY__SHIFT                                                                0x1
>+#define MDM_DMA_STATUS__SCM_DMA_RD_BUSY__SHIFT                                                                0x2
>+#define MDM_DMA_STATUS__RB_DMA_WR_BUSY__SHIFT                                                                 0x3
>+#define MDM_DMA_STATUS__RB_DMA_RD_BUSY__SHIFT                                                                 0x4
>+#define MDM_DMA_STATUS__SDB_DMA_RD_BUSY__SHIFT                                                                0x5
>+#define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY__SHIFT                                                               0x6
>+#define MDM_DMA_STATUS__SDB_DMA_WR_BUSY_MASK                                                                  0x00000001L
>+#define MDM_DMA_STATUS__SCM_DMA_WR_BUSY_MASK                                                                  0x00000002L
>+#define MDM_DMA_STATUS__SCM_DMA_RD_BUSY_MASK                                                                  0x00000004L
>+#define MDM_DMA_STATUS__RB_DMA_WR_BUSY_MASK                                                                   0x00000008L
>+#define MDM_DMA_STATUS__RB_DMA_RD_BUSY_MASK                                                                   0x00000010L
>+#define MDM_DMA_STATUS__SDB_DMA_RD_BUSY_MASK                                                                  0x00000020L
>+#define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY_MASK                                                                 0x00000040L
>+//MDM_DMA_CTL
>+#define MDM_DMA_CTL__MDM_BYPASS__SHIFT                                                                        0x0
>+#define MDM_DMA_CTL__FOUR_CMD__SHIFT                                                                          0x1
>+#define MDM_DMA_CTL__ENCODE_MODE__SHIFT                                                                       0x2
>+#define MDM_DMA_CTL__VP9_DEC_MODE__SHIFT                                                                      0x3
>+#define MDM_DMA_CTL__SW_DRST__SHIFT                                                                           0x1f
>+#define MDM_DMA_CTL__MDM_BYPASS_MASK                                                                          0x00000001L
>+#define MDM_DMA_CTL__FOUR_CMD_MASK                                                                            0x00000002L
>+#define MDM_DMA_CTL__ENCODE_MODE_MASK                                                                         0x00000004L
>+#define MDM_DMA_CTL__VP9_DEC_MODE_MASK                                                                        0x00000008L
>+#define MDM_DMA_CTL__SW_DRST_MASK                                                                             0x80000000L
>+//MDM_ENC_PIPE_BUSY
>+#define MDM_ENC_PIPE_BUSY__IME_BUSY__SHIFT                                                                    0x0
>+#define MDM_ENC_PIPE_BUSY__SMP_BUSY__SHIFT                                                                    0x1
>+#define MDM_ENC_PIPE_BUSY__SIT_BUSY__SHIFT                                                                    0x2
>+#define MDM_ENC_PIPE_BUSY__SDB_BUSY__SHIFT                                                                    0x3
>+#define MDM_ENC_PIPE_BUSY__ENT_BUSY__SHIFT                                                                    0x4
>+#define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT                                                             0x5
>+#define MDM_ENC_PIPE_BUSY__LCM_BUSY__SHIFT                                                                    0x6
>+#define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT                                                             0x7
>+#define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT                                                             0x8
>+#define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT                                                             0x9
>+#define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT                                                           0xa
>+#define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT                                                             0xb
>+#define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY__SHIFT                                                                0xc
>+#define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY__SHIFT                                                        0xd
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT                                                             0x10
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT                                                            0x11
>+#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT                                                            0x12
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT                                                            0x13
>+#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT                                                            0x14
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT                                                            0x15
>+#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT                                                            0x16
>+#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT                                                            0x17
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT                                                            0x18
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT                                                            0x19
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT                                                            0x1a
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT                                                            0x1b
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT                                                            0x1c
>+#define MDM_ENC_PIPE_BUSY__IME_BUSY_MASK                                                                      0x00000001L
>+#define MDM_ENC_PIPE_BUSY__SMP_BUSY_MASK                                                                      0x00000002L
>+#define MDM_ENC_PIPE_BUSY__SIT_BUSY_MASK                                                                      0x00000004L
>+#define MDM_ENC_PIPE_BUSY__SDB_BUSY_MASK                                                                      0x00000008L
>+#define MDM_ENC_PIPE_BUSY__ENT_BUSY_MASK                                                                      0x00000010L
>+#define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK                                                               0x00000020L
>+#define MDM_ENC_PIPE_BUSY__LCM_BUSY_MASK                                                                      0x00000040L
>+#define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK                                                               0x00000080L
>+#define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK                                                               0x00000100L
>+#define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK                                                               0x00000200L
>+#define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK                                                             0x00000400L
>+#define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK                                                               0x00000800L
>+#define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY_MASK                                                                  0x00001000L
>+#define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY_MASK                                                          0x00002000L
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK                                                               0x00010000L
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK                                                              0x00020000L
>+#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK                                                              0x00040000L
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK                                                              0x00080000L
>+#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK                                                              0x00100000L
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK                                                              0x00200000L
>+#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK                                                              0x00400000L
>+#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK                                                              0x00800000L
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK                                                              0x01000000L
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK                                                              0x02000000L
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK                                                              0x04000000L
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK                                                              0x08000000L
>+#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK                                                              0x10000000L
>+//MDM_WIG_PIPE_BUSY
>+#define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY__SHIFT                                                                0x0
>+#define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY__SHIFT                                                                0x1
>+#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY__SHIFT                                                         0x2
>+#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL__SHIFT                                                    0x3
>+#define MDM_WIG_PIPE_BUSY__LCM_BUSY__SHIFT                                                                    0x4
>+#define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT                                                             0x5
>+#define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT                                                             0x6
>+#define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT                                                             0x7
>+#define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT                                                           0x8
>+#define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT                                                             0x9
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT                                                             0xa
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT                                                            0xb
>+#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT                                                            0xc
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT                                                            0xd
>+#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT                                                            0xe
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT                                                            0xf
>+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT                                                            0x10
>+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT                                                            0x11
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT                                                            0x12
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT                                                            0x13
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT                                                            0x14
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT                                                            0x15
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT                                                            0x16
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY__SHIFT                                                            0x17
>+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT                                                            0x18
>+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT                                                            0x19
>+#define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY__SHIFT                                                          0x1a
>+#define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY__SHIFT                                                          0x1b
>+#define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY__SHIFT                                                          0x1c
>+#define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY__SHIFT                                                          0x1d
>+#define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY_MASK                                                                  0x00000001L
>+#define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY_MASK                                                                  0x00000002L
>+#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY_MASK                                                           0x00000004L
>+#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL_MASK                                                      0x00000008L
>+#define MDM_WIG_PIPE_BUSY__LCM_BUSY_MASK                                                                      0x00000010L
>+#define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK                                                               0x00000020L
>+#define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY_MASK                                                               0x00000040L
>+#define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK                                                               0x00000080L
>+#define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK                                                             0x00000100L
>+#define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK                                                               0x00000200L
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK                                                               0x00000400L
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK                                                              0x00000800L
>+#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK                                                              0x00001000L
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK                                                              0x00002000L
>+#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK                                                              0x00004000L
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK                                                              0x00008000L
>+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK                                                              0x00010000L
>+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK                                                              0x00020000L
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK                                                              0x00040000L
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK                                                              0x00080000L
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK                                                              0x00100000L
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK                                                              0x00200000L
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK                                                              0x00400000L
>+#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY_MASK                                                              0x00800000L
>+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK                                                              0x01000000L
>+#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK                                                              0x02000000L
>+#define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY_MASK                                                            0x04000000L
>+#define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY_MASK                                                            0x08000000L
>+#define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY_MASK                                                            0x10000000L
>+#define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY_MASK                                                            0x20000000L
>+
>+
>+// addressBlock: lmi_adp_indirect
>+//UVD_LMI_CRC0
>+#define UVD_LMI_CRC0__CRC32__SHIFT                                                                            0x0
>+#define UVD_LMI_CRC0__CRC32_MASK                                                                              0xFFFFFFFFL
>+//UVD_LMI_CRC1
>+#define UVD_LMI_CRC1__CRC32__SHIFT                                                                            0x0
>+#define UVD_LMI_CRC1__CRC32_MASK                                                                              0xFFFFFFFFL
>+//UVD_LMI_CRC2
>+#define UVD_LMI_CRC2__CRC32__SHIFT                                                                            0x0
>+#define UVD_LMI_CRC2__CRC32_MASK                                                                              0xFFFFFFFFL
>+//UVD_LMI_CRC3
>+#define UVD_LMI_CRC3__CRC32__SHIFT                                                                            0x0
>+#define UVD_LMI_CRC3__CRC32_MASK                                                                              0xFFFFFFFFL
>+
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/atomfirmware.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/atomfirmware.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/atomfirmware.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/atomfirmware.h	2019-08-31 15:01:11.935736175 -0500
>@@ -1789,6 +1789,92 @@
> 
> };
> 
>+struct atom_smc_dpm_info_v4_6
>+{
>+  struct   atom_common_table_header  table_header;
>+  // section: board parameters
>+  uint32_t     i2c_padding[3];   // old i2c control are moved to new area
>+
>+  uint16_t     maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
>+  uint16_t     maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value.
>+
>+  uint8_t      vddgfxvrmapping;     // use vr_mapping* bitfields
>+  uint8_t      vddsocvrmapping;     // use vr_mapping* bitfields
>+  uint8_t      vddmemvrmapping;     // use vr_mapping* bitfields
>+  uint8_t      boardvrmapping;      // use vr_mapping* bitfields
>+
>+  uint8_t      gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
>+  uint8_t      externalsensorpresent; // external rdi connected to tmon (aka temp in)
>+  uint8_t      padding8_v[2];
>+
>+  // telemetry settings
>+  uint16_t     gfxmaxcurrent;   // in amps
>+  uint8_t      gfxoffset;       // in amps
>+  uint8_t      padding_telemetrygfx;
>+
>+  uint16_t     socmaxcurrent;   // in amps
>+  uint8_t      socoffset;       // in amps
>+  uint8_t      padding_telemetrysoc;
>+
>+  uint16_t     memmaxcurrent;   // in amps
>+  uint8_t      memoffset;       // in amps
>+  uint8_t      padding_telemetrymem;
>+
>+  uint16_t     boardmaxcurrent;   // in amps
>+  uint8_t      boardoffset;       // in amps
>+  uint8_t      padding_telemetryboardinput;
>+
>+  // gpio settings
>+  uint8_t      vr0hotgpio;      // gpio pin configured for vr0 hot event
>+  uint8_t      vr0hotpolarity;  // gpio polarity for vr0 hot event
>+  uint8_t      vr1hotgpio;      // gpio pin configured for vr1 hot event
>+  uint8_t      vr1hotpolarity;  // gpio polarity for vr1 hot event
>+
>+ // gfxclk pll spread spectrum
>+  uint8_t	   pllgfxclkspreadenabled;	// on or off
>+  uint8_t	   pllgfxclkspreadpercent;	// q4.4
>+  uint16_t	   pllgfxclkspreadfreq;		// khz
>+
>+ // uclk spread spectrum
>+  uint8_t	   uclkspreadenabled;   // on or off
>+  uint8_t	   uclkspreadpercent;   // q4.4
>+  uint16_t	   uclkspreadfreq;	   // khz
>+
>+ // fclk spread spectrum
>+  uint8_t	   fclkspreadenabled;   // on or off
>+  uint8_t	   fclkspreadpercent;   // q4.4
>+  uint16_t	   fclkspreadfreq;	   // khz
>+
>+
>+  // gfxclk fll spread spectrum
>+  uint8_t      fllgfxclkspreadenabled;   // on or off
>+  uint8_t      fllgfxclkspreadpercent;   // q4.4
>+  uint16_t     fllgfxclkspreadfreq;      // khz
>+
>+  // i2c controller structure
>+  struct smudpm_i2c_controller_config_v2 i2ccontrollers[8];
>+
>+  // memory section
>+  uint32_t	 memorychannelenabled; // for dram use only, max 32 channels enabled bit mask.
>+
>+  uint8_t 	 drambitwidth; // for dram use only.  see dram bit width type defines
>+  uint8_t 	 paddingmem[3];
>+
>+	// total board power
>+  uint16_t	 totalboardpower;	  //only needed for tcp estimated case, where tcp = tgp+total board power
>+  uint16_t	 boardpadding;
>+
>+	// section: xgmi training
>+  uint8_t 	 xgmilinkspeed[4];
>+  uint8_t 	 xgmilinkwidth[4];
>+
>+  uint16_t	 xgmifclkfreq[4];
>+  uint16_t	 xgmisocvoltage[4];
>+
>+  // reserved
>+  uint32_t   boardreserved[10];
>+};
>+
> /* 
>   ***************************************************************************
>     Data Table asic_profiling_info  structure
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/kgd_pp_interface.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/kgd_pp_interface.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/kgd_pp_interface.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/kgd_pp_interface.h	2019-08-31 15:01:11.935736175 -0500
>@@ -142,6 +142,7 @@
> 	PP_SMC_POWER_PROFILE_VR           = 0x4,
> 	PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
> 	PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
>+	PP_SMC_POWER_PROFILE_COUNT,
> };
> 
> enum {
>@@ -171,6 +172,13 @@
> 	PP_TEMP_MAX
> };
> 
>+enum pp_mp1_state {
>+	PP_MP1_STATE_NONE,
>+	PP_MP1_STATE_SHUTDOWN,
>+	PP_MP1_STATE_UNLOAD,
>+	PP_MP1_STATE_RESET,
>+};
>+
> #define PP_GROUP_MASK        0xF0000000
> #define PP_GROUP_SHIFT       28
> 
>@@ -266,6 +274,8 @@
> 	int (*get_power_profile_mode)(void *handle, char *buf);
> 	int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
> 	int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
>+	int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
>+	int (*smu_i2c_bus_access)(void *handle, bool acquire);
> /* export to DC */
> 	u32 (*get_sclk)(void *handle, bool low);
> 	u32 (*get_mclk)(void *handle, bool low);
>@@ -301,6 +311,7 @@
> 	int (*set_asic_baco_state)(void *handle, int state);
> 	int (*get_ppfeature_status)(void *handle, char *buf);
> 	int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
>+	int (*asic_reset_mode_2)(void *handle);
> };
> 
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/navi12_ip_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/navi12_ip_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/navi12_ip_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/navi12_ip_offset.h	2019-08-31 15:01:11.935736175 -0500
>@@ -0,0 +1,1119 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _navi12_ip_offset_HEADER
>+#define _navi12_ip_offset_HEADER
>+
>+#define MAX_INSTANCE                                       7
>+#define MAX_SEGMENT                                        5
>+
>+
>+struct IP_BASE_INSTANCE
>+{
>+    unsigned int segment[MAX_SEGMENT];
>+};
>+
>+struct IP_BASE
>+{
>+    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
>+};
>+
>+
>+static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
>+                                        { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
>+                                        { { 0x00017000, 0x02402000, 0, 0, 0 } },
>+                                        { { 0x00017200, 0x02402400, 0, 0, 0 } },
>+                                        { { 0x0001B000, 0x0242D800, 0, 0, 0 } },
>+                                        { { 0x00017E00, 0x0240BC00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
>+                                        { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
>+                                        { { 0x00054000, 0x02425C00, 0, 0, 0 } },
>+                                        { { 0x00094000, 0x02426000, 0, 0, 0 } },
>+                                        { { 0x000D4000, 0x02426400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+
>+
>+#define ATHUB_BASE__INST0_SEG0                     0x00000C00
>+#define ATHUB_BASE__INST0_SEG1                     0x02408C00
>+#define ATHUB_BASE__INST0_SEG2                     0
>+#define ATHUB_BASE__INST0_SEG3                     0
>+#define ATHUB_BASE__INST0_SEG4                     0
>+
>+#define ATHUB_BASE__INST1_SEG0                     0
>+#define ATHUB_BASE__INST1_SEG1                     0
>+#define ATHUB_BASE__INST1_SEG2                     0
>+#define ATHUB_BASE__INST1_SEG3                     0
>+#define ATHUB_BASE__INST1_SEG4                     0
>+
>+#define ATHUB_BASE__INST2_SEG0                     0
>+#define ATHUB_BASE__INST2_SEG1                     0
>+#define ATHUB_BASE__INST2_SEG2                     0
>+#define ATHUB_BASE__INST2_SEG3                     0
>+#define ATHUB_BASE__INST2_SEG4                     0
>+
>+#define ATHUB_BASE__INST3_SEG0                     0
>+#define ATHUB_BASE__INST3_SEG1                     0
>+#define ATHUB_BASE__INST3_SEG2                     0
>+#define ATHUB_BASE__INST3_SEG3                     0
>+#define ATHUB_BASE__INST3_SEG4                     0
>+
>+#define ATHUB_BASE__INST4_SEG0                     0
>+#define ATHUB_BASE__INST4_SEG1                     0
>+#define ATHUB_BASE__INST4_SEG2                     0
>+#define ATHUB_BASE__INST4_SEG3                     0
>+#define ATHUB_BASE__INST4_SEG4                     0
>+
>+#define ATHUB_BASE__INST5_SEG0                     0
>+#define ATHUB_BASE__INST5_SEG1                     0
>+#define ATHUB_BASE__INST5_SEG2                     0
>+#define ATHUB_BASE__INST5_SEG3                     0
>+#define ATHUB_BASE__INST5_SEG4                     0
>+
>+#define ATHUB_BASE__INST6_SEG0                     0
>+#define ATHUB_BASE__INST6_SEG1                     0
>+#define ATHUB_BASE__INST6_SEG2                     0
>+#define ATHUB_BASE__INST6_SEG3                     0
>+#define ATHUB_BASE__INST6_SEG4                     0
>+
>+#define CLK_BASE__INST0_SEG0                       0x00016C00
>+#define CLK_BASE__INST0_SEG1                       0x02401800
>+#define CLK_BASE__INST0_SEG2                       0
>+#define CLK_BASE__INST0_SEG3                       0
>+#define CLK_BASE__INST0_SEG4                       0
>+
>+#define CLK_BASE__INST1_SEG0                       0x00016E00
>+#define CLK_BASE__INST1_SEG1                       0x02401C00
>+#define CLK_BASE__INST1_SEG2                       0
>+#define CLK_BASE__INST1_SEG3                       0
>+#define CLK_BASE__INST1_SEG4                       0
>+
>+#define CLK_BASE__INST2_SEG0                       0x00017000
>+#define CLK_BASE__INST2_SEG1                       0x02402000
>+#define CLK_BASE__INST2_SEG2                       0
>+#define CLK_BASE__INST2_SEG3                       0
>+#define CLK_BASE__INST2_SEG4                       0
>+
>+#define CLK_BASE__INST3_SEG0                       0x00017200
>+#define CLK_BASE__INST3_SEG1                       0x02402400
>+#define CLK_BASE__INST3_SEG2                       0
>+#define CLK_BASE__INST3_SEG3                       0
>+#define CLK_BASE__INST3_SEG4                       0
>+
>+#define CLK_BASE__INST4_SEG0                       0x0001B000
>+#define CLK_BASE__INST4_SEG1                       0x0242D800
>+#define CLK_BASE__INST4_SEG2                       0
>+#define CLK_BASE__INST4_SEG3                       0
>+#define CLK_BASE__INST4_SEG4                       0
>+
>+#define CLK_BASE__INST5_SEG0                       0x00017E00
>+#define CLK_BASE__INST5_SEG1                       0x0240BC00
>+#define CLK_BASE__INST5_SEG2                       0
>+#define CLK_BASE__INST5_SEG3                       0
>+#define CLK_BASE__INST5_SEG4                       0
>+
>+#define CLK_BASE__INST6_SEG0                       0
>+#define CLK_BASE__INST6_SEG1                       0
>+#define CLK_BASE__INST6_SEG2                       0
>+#define CLK_BASE__INST6_SEG3                       0
>+#define CLK_BASE__INST6_SEG4                       0
>+
>+#define DF_BASE__INST0_SEG0                        0x00007000
>+#define DF_BASE__INST0_SEG1                        0x0240B800
>+#define DF_BASE__INST0_SEG2                        0
>+#define DF_BASE__INST0_SEG3                        0
>+#define DF_BASE__INST0_SEG4                        0
>+
>+#define DF_BASE__INST1_SEG0                        0
>+#define DF_BASE__INST1_SEG1                        0
>+#define DF_BASE__INST1_SEG2                        0
>+#define DF_BASE__INST1_SEG3                        0
>+#define DF_BASE__INST1_SEG4                        0
>+
>+#define DF_BASE__INST2_SEG0                        0
>+#define DF_BASE__INST2_SEG1                        0
>+#define DF_BASE__INST2_SEG2                        0
>+#define DF_BASE__INST2_SEG3                        0
>+#define DF_BASE__INST2_SEG4                        0
>+
>+#define DF_BASE__INST3_SEG0                        0
>+#define DF_BASE__INST3_SEG1                        0
>+#define DF_BASE__INST3_SEG2                        0
>+#define DF_BASE__INST3_SEG3                        0
>+#define DF_BASE__INST3_SEG4                        0
>+
>+#define DF_BASE__INST4_SEG0                        0
>+#define DF_BASE__INST4_SEG1                        0
>+#define DF_BASE__INST4_SEG2                        0
>+#define DF_BASE__INST4_SEG3                        0
>+#define DF_BASE__INST4_SEG4                        0
>+
>+#define DF_BASE__INST5_SEG0                        0
>+#define DF_BASE__INST5_SEG1                        0
>+#define DF_BASE__INST5_SEG2                        0
>+#define DF_BASE__INST5_SEG3                        0
>+#define DF_BASE__INST5_SEG4                        0
>+
>+#define DF_BASE__INST6_SEG0                        0
>+#define DF_BASE__INST6_SEG1                        0
>+#define DF_BASE__INST6_SEG2                        0
>+#define DF_BASE__INST6_SEG3                        0
>+#define DF_BASE__INST6_SEG4                        0
>+
>+#define DIO_BASE__INST0_SEG0                       0x02404000
>+#define DIO_BASE__INST0_SEG1                       0
>+#define DIO_BASE__INST0_SEG2                       0
>+#define DIO_BASE__INST0_SEG3                       0
>+#define DIO_BASE__INST0_SEG4                       0
>+
>+#define DIO_BASE__INST1_SEG0                       0
>+#define DIO_BASE__INST1_SEG1                       0
>+#define DIO_BASE__INST1_SEG2                       0
>+#define DIO_BASE__INST1_SEG3                       0
>+#define DIO_BASE__INST1_SEG4                       0
>+
>+#define DIO_BASE__INST2_SEG0                       0
>+#define DIO_BASE__INST2_SEG1                       0
>+#define DIO_BASE__INST2_SEG2                       0
>+#define DIO_BASE__INST2_SEG3                       0
>+#define DIO_BASE__INST2_SEG4                       0
>+
>+#define DIO_BASE__INST3_SEG0                       0
>+#define DIO_BASE__INST3_SEG1                       0
>+#define DIO_BASE__INST3_SEG2                       0
>+#define DIO_BASE__INST3_SEG3                       0
>+#define DIO_BASE__INST3_SEG4                       0
>+
>+#define DIO_BASE__INST4_SEG0                       0
>+#define DIO_BASE__INST4_SEG1                       0
>+#define DIO_BASE__INST4_SEG2                       0
>+#define DIO_BASE__INST4_SEG3                       0
>+#define DIO_BASE__INST4_SEG4                       0
>+
>+#define DIO_BASE__INST5_SEG0                       0
>+#define DIO_BASE__INST5_SEG1                       0
>+#define DIO_BASE__INST5_SEG2                       0
>+#define DIO_BASE__INST5_SEG3                       0
>+#define DIO_BASE__INST5_SEG4                       0
>+
>+#define DIO_BASE__INST6_SEG0                       0
>+#define DIO_BASE__INST6_SEG1                       0
>+#define DIO_BASE__INST6_SEG2                       0
>+#define DIO_BASE__INST6_SEG3                       0
>+#define DIO_BASE__INST6_SEG4                       0
>+
>+#define DMU_BASE__INST0_SEG0                       0x00000012
>+#define DMU_BASE__INST0_SEG1                       0x000000C0
>+#define DMU_BASE__INST0_SEG2                       0x000034C0
>+#define DMU_BASE__INST0_SEG3                       0x00009000
>+#define DMU_BASE__INST0_SEG4                       0x02403C00
>+
>+#define DMU_BASE__INST1_SEG0                       0
>+#define DMU_BASE__INST1_SEG1                       0
>+#define DMU_BASE__INST1_SEG2                       0
>+#define DMU_BASE__INST1_SEG3                       0
>+#define DMU_BASE__INST1_SEG4                       0
>+
>+#define DMU_BASE__INST2_SEG0                       0
>+#define DMU_BASE__INST2_SEG1                       0
>+#define DMU_BASE__INST2_SEG2                       0
>+#define DMU_BASE__INST2_SEG3                       0
>+#define DMU_BASE__INST2_SEG4                       0
>+
>+#define DMU_BASE__INST3_SEG0                       0
>+#define DMU_BASE__INST3_SEG1                       0
>+#define DMU_BASE__INST3_SEG2                       0
>+#define DMU_BASE__INST3_SEG3                       0
>+#define DMU_BASE__INST3_SEG4                       0
>+
>+#define DMU_BASE__INST4_SEG0                       0
>+#define DMU_BASE__INST4_SEG1                       0
>+#define DMU_BASE__INST4_SEG2                       0
>+#define DMU_BASE__INST4_SEG3                       0
>+#define DMU_BASE__INST4_SEG4                       0
>+
>+#define DMU_BASE__INST5_SEG0                       0
>+#define DMU_BASE__INST5_SEG1                       0
>+#define DMU_BASE__INST5_SEG2                       0
>+#define DMU_BASE__INST5_SEG3                       0
>+#define DMU_BASE__INST5_SEG4                       0
>+
>+#define DMU_BASE__INST6_SEG0                       0
>+#define DMU_BASE__INST6_SEG1                       0
>+#define DMU_BASE__INST6_SEG2                       0
>+#define DMU_BASE__INST6_SEG3                       0
>+#define DMU_BASE__INST6_SEG4                       0
>+
>+#define DPCS_BASE__INST0_SEG0                      0x00000012
>+#define DPCS_BASE__INST0_SEG1                      0x000000C0
>+#define DPCS_BASE__INST0_SEG2                      0x000034C0
>+#define DPCS_BASE__INST0_SEG3                      0x00009000
>+#define DPCS_BASE__INST0_SEG4                      0x02403C00
>+
>+#define DPCS_BASE__INST1_SEG0                      0
>+#define DPCS_BASE__INST1_SEG1                      0
>+#define DPCS_BASE__INST1_SEG2                      0
>+#define DPCS_BASE__INST1_SEG3                      0
>+#define DPCS_BASE__INST1_SEG4                      0
>+
>+#define DPCS_BASE__INST2_SEG0                      0
>+#define DPCS_BASE__INST2_SEG1                      0
>+#define DPCS_BASE__INST2_SEG2                      0
>+#define DPCS_BASE__INST2_SEG3                      0
>+#define DPCS_BASE__INST2_SEG4                      0
>+
>+#define DPCS_BASE__INST3_SEG0                      0
>+#define DPCS_BASE__INST3_SEG1                      0
>+#define DPCS_BASE__INST3_SEG2                      0
>+#define DPCS_BASE__INST3_SEG3                      0
>+#define DPCS_BASE__INST3_SEG4                      0
>+
>+#define DPCS_BASE__INST4_SEG0                      0
>+#define DPCS_BASE__INST4_SEG1                      0
>+#define DPCS_BASE__INST4_SEG2                      0
>+#define DPCS_BASE__INST4_SEG3                      0
>+#define DPCS_BASE__INST4_SEG4                      0
>+
>+#define DPCS_BASE__INST5_SEG0                      0
>+#define DPCS_BASE__INST5_SEG1                      0
>+#define DPCS_BASE__INST5_SEG2                      0
>+#define DPCS_BASE__INST5_SEG3                      0
>+#define DPCS_BASE__INST5_SEG4                      0
>+
>+#define DPCS_BASE__INST6_SEG0                      0
>+#define DPCS_BASE__INST6_SEG1                      0
>+#define DPCS_BASE__INST6_SEG2                      0
>+#define DPCS_BASE__INST6_SEG3                      0
>+#define DPCS_BASE__INST6_SEG4                      0
>+
>+#define FUSE_BASE__INST0_SEG0                      0x00017400
>+#define FUSE_BASE__INST0_SEG1                      0x02401400
>+#define FUSE_BASE__INST0_SEG2                      0
>+#define FUSE_BASE__INST0_SEG3                      0
>+#define FUSE_BASE__INST0_SEG4                      0
>+
>+#define FUSE_BASE__INST1_SEG0                      0
>+#define FUSE_BASE__INST1_SEG1                      0
>+#define FUSE_BASE__INST1_SEG2                      0
>+#define FUSE_BASE__INST1_SEG3                      0
>+#define FUSE_BASE__INST1_SEG4                      0
>+
>+#define FUSE_BASE__INST2_SEG0                      0
>+#define FUSE_BASE__INST2_SEG1                      0
>+#define FUSE_BASE__INST2_SEG2                      0
>+#define FUSE_BASE__INST2_SEG3                      0
>+#define FUSE_BASE__INST2_SEG4                      0
>+
>+#define FUSE_BASE__INST3_SEG0                      0
>+#define FUSE_BASE__INST3_SEG1                      0
>+#define FUSE_BASE__INST3_SEG2                      0
>+#define FUSE_BASE__INST3_SEG3                      0
>+#define FUSE_BASE__INST3_SEG4                      0
>+
>+#define FUSE_BASE__INST4_SEG0                      0
>+#define FUSE_BASE__INST4_SEG1                      0
>+#define FUSE_BASE__INST4_SEG2                      0
>+#define FUSE_BASE__INST4_SEG3                      0
>+#define FUSE_BASE__INST4_SEG4                      0
>+
>+#define FUSE_BASE__INST5_SEG0                      0
>+#define FUSE_BASE__INST5_SEG1                      0
>+#define FUSE_BASE__INST5_SEG2                      0
>+#define FUSE_BASE__INST5_SEG3                      0
>+#define FUSE_BASE__INST5_SEG4                      0
>+
>+#define FUSE_BASE__INST6_SEG0                      0
>+#define FUSE_BASE__INST6_SEG1                      0
>+#define FUSE_BASE__INST6_SEG2                      0
>+#define FUSE_BASE__INST6_SEG3                      0
>+#define FUSE_BASE__INST6_SEG4                      0
>+
>+#define GC_BASE__INST0_SEG0                        0x00001260
>+#define GC_BASE__INST0_SEG1                        0x0000A000
>+#define GC_BASE__INST0_SEG2                        0x02402C00
>+#define GC_BASE__INST0_SEG3                        0
>+#define GC_BASE__INST0_SEG4                        0
>+
>+#define GC_BASE__INST1_SEG0                        0
>+#define GC_BASE__INST1_SEG1                        0
>+#define GC_BASE__INST1_SEG2                        0
>+#define GC_BASE__INST1_SEG3                        0
>+#define GC_BASE__INST1_SEG4                        0
>+
>+#define GC_BASE__INST2_SEG0                        0
>+#define GC_BASE__INST2_SEG1                        0
>+#define GC_BASE__INST2_SEG2                        0
>+#define GC_BASE__INST2_SEG3                        0
>+#define GC_BASE__INST2_SEG4                        0
>+
>+#define GC_BASE__INST3_SEG0                        0
>+#define GC_BASE__INST3_SEG1                        0
>+#define GC_BASE__INST3_SEG2                        0
>+#define GC_BASE__INST3_SEG3                        0
>+#define GC_BASE__INST3_SEG4                        0
>+
>+#define GC_BASE__INST4_SEG0                        0
>+#define GC_BASE__INST4_SEG1                        0
>+#define GC_BASE__INST4_SEG2                        0
>+#define GC_BASE__INST4_SEG3                        0
>+#define GC_BASE__INST4_SEG4                        0
>+
>+#define GC_BASE__INST5_SEG0                        0
>+#define GC_BASE__INST5_SEG1                        0
>+#define GC_BASE__INST5_SEG2                        0
>+#define GC_BASE__INST5_SEG3                        0
>+#define GC_BASE__INST5_SEG4                        0
>+
>+#define GC_BASE__INST6_SEG0                        0
>+#define GC_BASE__INST6_SEG1                        0
>+#define GC_BASE__INST6_SEG2                        0
>+#define GC_BASE__INST6_SEG3                        0
>+#define GC_BASE__INST6_SEG4                        0
>+
>+#define HDA_BASE__INST0_SEG0                       0x004C0000
>+#define HDA_BASE__INST0_SEG1                       0x02404800
>+#define HDA_BASE__INST0_SEG2                       0
>+#define HDA_BASE__INST0_SEG3                       0
>+#define HDA_BASE__INST0_SEG4                       0
>+
>+#define HDA_BASE__INST1_SEG0                       0
>+#define HDA_BASE__INST1_SEG1                       0
>+#define HDA_BASE__INST1_SEG2                       0
>+#define HDA_BASE__INST1_SEG3                       0
>+#define HDA_BASE__INST1_SEG4                       0
>+
>+#define HDA_BASE__INST2_SEG0                       0
>+#define HDA_BASE__INST2_SEG1                       0
>+#define HDA_BASE__INST2_SEG2                       0
>+#define HDA_BASE__INST2_SEG3                       0
>+#define HDA_BASE__INST2_SEG4                       0
>+
>+#define HDA_BASE__INST3_SEG0                       0
>+#define HDA_BASE__INST3_SEG1                       0
>+#define HDA_BASE__INST3_SEG2                       0
>+#define HDA_BASE__INST3_SEG3                       0
>+#define HDA_BASE__INST3_SEG4                       0
>+
>+#define HDA_BASE__INST4_SEG0                       0
>+#define HDA_BASE__INST4_SEG1                       0
>+#define HDA_BASE__INST4_SEG2                       0
>+#define HDA_BASE__INST4_SEG3                       0
>+#define HDA_BASE__INST4_SEG4                       0
>+
>+#define HDA_BASE__INST5_SEG0                       0
>+#define HDA_BASE__INST5_SEG1                       0
>+#define HDA_BASE__INST5_SEG2                       0
>+#define HDA_BASE__INST5_SEG3                       0
>+#define HDA_BASE__INST5_SEG4                       0
>+
>+#define HDA_BASE__INST6_SEG0                       0
>+#define HDA_BASE__INST6_SEG1                       0
>+#define HDA_BASE__INST6_SEG2                       0
>+#define HDA_BASE__INST6_SEG3                       0
>+#define HDA_BASE__INST6_SEG4                       0
>+
>+#define HDP_BASE__INST0_SEG0                       0x00000F20
>+#define HDP_BASE__INST0_SEG1                       0x0240A400
>+#define HDP_BASE__INST0_SEG2                       0
>+#define HDP_BASE__INST0_SEG3                       0
>+#define HDP_BASE__INST0_SEG4                       0
>+
>+#define HDP_BASE__INST1_SEG0                       0
>+#define HDP_BASE__INST1_SEG1                       0
>+#define HDP_BASE__INST1_SEG2                       0
>+#define HDP_BASE__INST1_SEG3                       0
>+#define HDP_BASE__INST1_SEG4                       0
>+
>+#define HDP_BASE__INST2_SEG0                       0
>+#define HDP_BASE__INST2_SEG1                       0
>+#define HDP_BASE__INST2_SEG2                       0
>+#define HDP_BASE__INST2_SEG3                       0
>+#define HDP_BASE__INST2_SEG4                       0
>+
>+#define HDP_BASE__INST3_SEG0                       0
>+#define HDP_BASE__INST3_SEG1                       0
>+#define HDP_BASE__INST3_SEG2                       0
>+#define HDP_BASE__INST3_SEG3                       0
>+#define HDP_BASE__INST3_SEG4                       0
>+
>+#define HDP_BASE__INST4_SEG0                       0
>+#define HDP_BASE__INST4_SEG1                       0
>+#define HDP_BASE__INST4_SEG2                       0
>+#define HDP_BASE__INST4_SEG3                       0
>+#define HDP_BASE__INST4_SEG4                       0
>+
>+#define HDP_BASE__INST5_SEG0                       0
>+#define HDP_BASE__INST5_SEG1                       0
>+#define HDP_BASE__INST5_SEG2                       0
>+#define HDP_BASE__INST5_SEG3                       0
>+#define HDP_BASE__INST5_SEG4                       0
>+
>+#define HDP_BASE__INST6_SEG0                       0
>+#define HDP_BASE__INST6_SEG1                       0
>+#define HDP_BASE__INST6_SEG2                       0
>+#define HDP_BASE__INST6_SEG3                       0
>+#define HDP_BASE__INST6_SEG4                       0
>+
>+#define MMHUB_BASE__INST0_SEG0                     0x0001A000
>+#define MMHUB_BASE__INST0_SEG1                     0x02408800
>+#define MMHUB_BASE__INST0_SEG2                     0
>+#define MMHUB_BASE__INST0_SEG3                     0
>+#define MMHUB_BASE__INST0_SEG4                     0
>+
>+#define MMHUB_BASE__INST1_SEG0                     0
>+#define MMHUB_BASE__INST1_SEG1                     0
>+#define MMHUB_BASE__INST1_SEG2                     0
>+#define MMHUB_BASE__INST1_SEG3                     0
>+#define MMHUB_BASE__INST1_SEG4                     0
>+
>+#define MMHUB_BASE__INST2_SEG0                     0
>+#define MMHUB_BASE__INST2_SEG1                     0
>+#define MMHUB_BASE__INST2_SEG2                     0
>+#define MMHUB_BASE__INST2_SEG3                     0
>+#define MMHUB_BASE__INST2_SEG4                     0
>+
>+#define MMHUB_BASE__INST3_SEG0                     0
>+#define MMHUB_BASE__INST3_SEG1                     0
>+#define MMHUB_BASE__INST3_SEG2                     0
>+#define MMHUB_BASE__INST3_SEG3                     0
>+#define MMHUB_BASE__INST3_SEG4                     0
>+
>+#define MMHUB_BASE__INST4_SEG0                     0
>+#define MMHUB_BASE__INST4_SEG1                     0
>+#define MMHUB_BASE__INST4_SEG2                     0
>+#define MMHUB_BASE__INST4_SEG3                     0
>+#define MMHUB_BASE__INST4_SEG4                     0
>+
>+#define MMHUB_BASE__INST5_SEG0                     0
>+#define MMHUB_BASE__INST5_SEG1                     0
>+#define MMHUB_BASE__INST5_SEG2                     0
>+#define MMHUB_BASE__INST5_SEG3                     0
>+#define MMHUB_BASE__INST5_SEG4                     0
>+
>+#define MMHUB_BASE__INST6_SEG0                     0
>+#define MMHUB_BASE__INST6_SEG1                     0
>+#define MMHUB_BASE__INST6_SEG2                     0
>+#define MMHUB_BASE__INST6_SEG3                     0
>+#define MMHUB_BASE__INST6_SEG4                     0
>+
>+#define MP0_BASE__INST0_SEG0                       0x00016000
>+#define MP0_BASE__INST0_SEG1                       0x00DC0000
>+#define MP0_BASE__INST0_SEG2                       0x00E00000
>+#define MP0_BASE__INST0_SEG3                       0x00E40000
>+#define MP0_BASE__INST0_SEG4                       0x0243FC00
>+
>+#define MP0_BASE__INST1_SEG0                       0
>+#define MP0_BASE__INST1_SEG1                       0
>+#define MP0_BASE__INST1_SEG2                       0
>+#define MP0_BASE__INST1_SEG3                       0
>+#define MP0_BASE__INST1_SEG4                       0
>+
>+#define MP0_BASE__INST2_SEG0                       0
>+#define MP0_BASE__INST2_SEG1                       0
>+#define MP0_BASE__INST2_SEG2                       0
>+#define MP0_BASE__INST2_SEG3                       0
>+#define MP0_BASE__INST2_SEG4                       0
>+
>+#define MP0_BASE__INST3_SEG0                       0
>+#define MP0_BASE__INST3_SEG1                       0
>+#define MP0_BASE__INST3_SEG2                       0
>+#define MP0_BASE__INST3_SEG3                       0
>+#define MP0_BASE__INST3_SEG4                       0
>+
>+#define MP0_BASE__INST4_SEG0                       0
>+#define MP0_BASE__INST4_SEG1                       0
>+#define MP0_BASE__INST4_SEG2                       0
>+#define MP0_BASE__INST4_SEG3                       0
>+#define MP0_BASE__INST4_SEG4                       0
>+
>+#define MP0_BASE__INST5_SEG0                       0
>+#define MP0_BASE__INST5_SEG1                       0
>+#define MP0_BASE__INST5_SEG2                       0
>+#define MP0_BASE__INST5_SEG3                       0
>+#define MP0_BASE__INST5_SEG4                       0
>+
>+#define MP0_BASE__INST6_SEG0                       0
>+#define MP0_BASE__INST6_SEG1                       0
>+#define MP0_BASE__INST6_SEG2                       0
>+#define MP0_BASE__INST6_SEG3                       0
>+#define MP0_BASE__INST6_SEG4                       0
>+
>+#define MP1_BASE__INST0_SEG0                       0x00016200
>+#define MP1_BASE__INST0_SEG1                       0x00E80000
>+#define MP1_BASE__INST0_SEG2                       0x00EC0000
>+#define MP1_BASE__INST0_SEG3                       0x00F00000
>+#define MP1_BASE__INST0_SEG4                       0x02400400
>+
>+#define MP1_BASE__INST1_SEG0                       0
>+#define MP1_BASE__INST1_SEG1                       0
>+#define MP1_BASE__INST1_SEG2                       0
>+#define MP1_BASE__INST1_SEG3                       0
>+#define MP1_BASE__INST1_SEG4                       0
>+
>+#define MP1_BASE__INST2_SEG0                       0
>+#define MP1_BASE__INST2_SEG1                       0
>+#define MP1_BASE__INST2_SEG2                       0
>+#define MP1_BASE__INST2_SEG3                       0
>+#define MP1_BASE__INST2_SEG4                       0
>+
>+#define MP1_BASE__INST3_SEG0                       0
>+#define MP1_BASE__INST3_SEG1                       0
>+#define MP1_BASE__INST3_SEG2                       0
>+#define MP1_BASE__INST3_SEG3                       0
>+#define MP1_BASE__INST3_SEG4                       0
>+
>+#define MP1_BASE__INST4_SEG0                       0
>+#define MP1_BASE__INST4_SEG1                       0
>+#define MP1_BASE__INST4_SEG2                       0
>+#define MP1_BASE__INST4_SEG3                       0
>+#define MP1_BASE__INST4_SEG4                       0
>+
>+#define MP1_BASE__INST5_SEG0                       0
>+#define MP1_BASE__INST5_SEG1                       0
>+#define MP1_BASE__INST5_SEG2                       0
>+#define MP1_BASE__INST5_SEG3                       0
>+#define MP1_BASE__INST5_SEG4                       0
>+
>+#define MP1_BASE__INST6_SEG0                       0
>+#define MP1_BASE__INST6_SEG1                       0
>+#define MP1_BASE__INST6_SEG2                       0
>+#define MP1_BASE__INST6_SEG3                       0
>+#define MP1_BASE__INST6_SEG4                       0
>+
>+#define NBIF0_BASE__INST0_SEG0                     0x00000000
>+#define NBIF0_BASE__INST0_SEG1                     0x00000014
>+#define NBIF0_BASE__INST0_SEG2                     0x00000D20
>+#define NBIF0_BASE__INST0_SEG3                     0x00010400
>+#define NBIF0_BASE__INST0_SEG4                     0x0241B000
>+
>+#define NBIF0_BASE__INST1_SEG0                     0
>+#define NBIF0_BASE__INST1_SEG1                     0
>+#define NBIF0_BASE__INST1_SEG2                     0
>+#define NBIF0_BASE__INST1_SEG3                     0
>+#define NBIF0_BASE__INST1_SEG4                     0
>+
>+#define NBIF0_BASE__INST2_SEG0                     0
>+#define NBIF0_BASE__INST2_SEG1                     0
>+#define NBIF0_BASE__INST2_SEG2                     0
>+#define NBIF0_BASE__INST2_SEG3                     0
>+#define NBIF0_BASE__INST2_SEG4                     0
>+
>+#define NBIF0_BASE__INST3_SEG0                     0
>+#define NBIF0_BASE__INST3_SEG1                     0
>+#define NBIF0_BASE__INST3_SEG2                     0
>+#define NBIF0_BASE__INST3_SEG3                     0
>+#define NBIF0_BASE__INST3_SEG4                     0
>+
>+#define NBIF0_BASE__INST4_SEG0                     0
>+#define NBIF0_BASE__INST4_SEG1                     0
>+#define NBIF0_BASE__INST4_SEG2                     0
>+#define NBIF0_BASE__INST4_SEG3                     0
>+#define NBIF0_BASE__INST4_SEG4                     0
>+
>+#define NBIF0_BASE__INST5_SEG0                     0
>+#define NBIF0_BASE__INST5_SEG1                     0
>+#define NBIF0_BASE__INST5_SEG2                     0
>+#define NBIF0_BASE__INST5_SEG3                     0
>+#define NBIF0_BASE__INST5_SEG4                     0
>+
>+#define NBIF0_BASE__INST6_SEG0                     0
>+#define NBIF0_BASE__INST6_SEG1                     0
>+#define NBIF0_BASE__INST6_SEG2                     0
>+#define NBIF0_BASE__INST6_SEG3                     0
>+#define NBIF0_BASE__INST6_SEG4                     0
>+
>+#define OSSSYS_BASE__INST0_SEG0                    0x000010A0
>+#define OSSSYS_BASE__INST0_SEG1                    0x0240A000
>+#define OSSSYS_BASE__INST0_SEG2                    0
>+#define OSSSYS_BASE__INST0_SEG3                    0
>+#define OSSSYS_BASE__INST0_SEG4                    0
>+
>+#define OSSSYS_BASE__INST1_SEG0                    0
>+#define OSSSYS_BASE__INST1_SEG1                    0
>+#define OSSSYS_BASE__INST1_SEG2                    0
>+#define OSSSYS_BASE__INST1_SEG3                    0
>+#define OSSSYS_BASE__INST1_SEG4                    0
>+
>+#define OSSSYS_BASE__INST2_SEG0                    0
>+#define OSSSYS_BASE__INST2_SEG1                    0
>+#define OSSSYS_BASE__INST2_SEG2                    0
>+#define OSSSYS_BASE__INST2_SEG3                    0
>+#define OSSSYS_BASE__INST2_SEG4                    0
>+
>+#define OSSSYS_BASE__INST3_SEG0                    0
>+#define OSSSYS_BASE__INST3_SEG1                    0
>+#define OSSSYS_BASE__INST3_SEG2                    0
>+#define OSSSYS_BASE__INST3_SEG3                    0
>+#define OSSSYS_BASE__INST3_SEG4                    0
>+
>+#define OSSSYS_BASE__INST4_SEG0                    0
>+#define OSSSYS_BASE__INST4_SEG1                    0
>+#define OSSSYS_BASE__INST4_SEG2                    0
>+#define OSSSYS_BASE__INST4_SEG3                    0
>+#define OSSSYS_BASE__INST4_SEG4                    0
>+
>+#define OSSSYS_BASE__INST5_SEG0                    0
>+#define OSSSYS_BASE__INST5_SEG1                    0
>+#define OSSSYS_BASE__INST5_SEG2                    0
>+#define OSSSYS_BASE__INST5_SEG3                    0
>+#define OSSSYS_BASE__INST5_SEG4                    0
>+
>+#define OSSSYS_BASE__INST6_SEG0                    0
>+#define OSSSYS_BASE__INST6_SEG1                    0
>+#define OSSSYS_BASE__INST6_SEG2                    0
>+#define OSSSYS_BASE__INST6_SEG3                    0
>+#define OSSSYS_BASE__INST6_SEG4                    0
>+
>+#define PCIE0_BASE__INST0_SEG0                     0x02411800
>+#define PCIE0_BASE__INST0_SEG1                     0x04440000
>+#define PCIE0_BASE__INST0_SEG2                     0
>+#define PCIE0_BASE__INST0_SEG3                     0
>+#define PCIE0_BASE__INST0_SEG4                     0
>+
>+#define PCIE0_BASE__INST1_SEG0                     0
>+#define PCIE0_BASE__INST1_SEG1                     0
>+#define PCIE0_BASE__INST1_SEG2                     0
>+#define PCIE0_BASE__INST1_SEG3                     0
>+#define PCIE0_BASE__INST1_SEG4                     0
>+
>+#define PCIE0_BASE__INST2_SEG0                     0
>+#define PCIE0_BASE__INST2_SEG1                     0
>+#define PCIE0_BASE__INST2_SEG2                     0
>+#define PCIE0_BASE__INST2_SEG3                     0
>+#define PCIE0_BASE__INST2_SEG4                     0
>+
>+#define PCIE0_BASE__INST3_SEG0                     0
>+#define PCIE0_BASE__INST3_SEG1                     0
>+#define PCIE0_BASE__INST3_SEG2                     0
>+#define PCIE0_BASE__INST3_SEG3                     0
>+#define PCIE0_BASE__INST3_SEG4                     0
>+
>+#define PCIE0_BASE__INST4_SEG0                     0
>+#define PCIE0_BASE__INST4_SEG1                     0
>+#define PCIE0_BASE__INST4_SEG2                     0
>+#define PCIE0_BASE__INST4_SEG3                     0
>+#define PCIE0_BASE__INST4_SEG4                     0
>+
>+#define PCIE0_BASE__INST5_SEG0                     0
>+#define PCIE0_BASE__INST5_SEG1                     0
>+#define PCIE0_BASE__INST5_SEG2                     0
>+#define PCIE0_BASE__INST5_SEG3                     0
>+#define PCIE0_BASE__INST5_SEG4                     0
>+
>+#define PCIE0_BASE__INST6_SEG0                     0
>+#define PCIE0_BASE__INST6_SEG1                     0
>+#define PCIE0_BASE__INST6_SEG2                     0
>+#define PCIE0_BASE__INST6_SEG3                     0
>+#define PCIE0_BASE__INST6_SEG4                     0
>+
>+#define SDMA_BASE__INST0_SEG0                      0x00001260
>+#define SDMA_BASE__INST0_SEG1                      0x0000A000
>+#define SDMA_BASE__INST0_SEG2                      0x02402C00
>+#define SDMA_BASE__INST0_SEG3                      0
>+#define SDMA_BASE__INST0_SEG4                      0
>+
>+#define SDMA_BASE__INST1_SEG0                      0x00001260
>+#define SDMA_BASE__INST1_SEG1                      0x0000A000
>+#define SDMA_BASE__INST1_SEG2                      0x02402C00
>+#define SDMA_BASE__INST1_SEG3                      0
>+#define SDMA_BASE__INST1_SEG4                      0
>+
>+#define SDMA_BASE__INST2_SEG0                      0
>+#define SDMA_BASE__INST2_SEG1                      0
>+#define SDMA_BASE__INST2_SEG2                      0
>+#define SDMA_BASE__INST2_SEG3                      0
>+#define SDMA_BASE__INST2_SEG4                      0
>+
>+#define SDMA_BASE__INST3_SEG0                      0
>+#define SDMA_BASE__INST3_SEG1                      0
>+#define SDMA_BASE__INST3_SEG2                      0
>+#define SDMA_BASE__INST3_SEG3                      0
>+#define SDMA_BASE__INST3_SEG4                      0
>+
>+#define SDMA_BASE__INST4_SEG0                      0
>+#define SDMA_BASE__INST4_SEG1                      0
>+#define SDMA_BASE__INST4_SEG2                      0
>+#define SDMA_BASE__INST4_SEG3                      0
>+#define SDMA_BASE__INST4_SEG4                      0
>+
>+#define SDMA_BASE__INST5_SEG0                      0
>+#define SDMA_BASE__INST5_SEG1                      0
>+#define SDMA_BASE__INST5_SEG2                      0
>+#define SDMA_BASE__INST5_SEG3                      0
>+#define SDMA_BASE__INST5_SEG4                      0
>+
>+#define SDMA_BASE__INST6_SEG0                      0
>+#define SDMA_BASE__INST6_SEG1                      0
>+#define SDMA_BASE__INST6_SEG2                      0
>+#define SDMA_BASE__INST6_SEG3                      0
>+#define SDMA_BASE__INST6_SEG4                      0
>+
>+#define SMUIO_BASE__INST0_SEG0                     0x00016800
>+#define SMUIO_BASE__INST0_SEG1                     0x00016A00
>+#define SMUIO_BASE__INST0_SEG2                     0x00440000
>+#define SMUIO_BASE__INST0_SEG3                     0x02401000
>+#define SMUIO_BASE__INST0_SEG4                     0
>+
>+#define SMUIO_BASE__INST1_SEG0                     0
>+#define SMUIO_BASE__INST1_SEG1                     0
>+#define SMUIO_BASE__INST1_SEG2                     0
>+#define SMUIO_BASE__INST1_SEG3                     0
>+#define SMUIO_BASE__INST1_SEG4                     0
>+
>+#define SMUIO_BASE__INST2_SEG0                     0
>+#define SMUIO_BASE__INST2_SEG1                     0
>+#define SMUIO_BASE__INST2_SEG2                     0
>+#define SMUIO_BASE__INST2_SEG3                     0
>+#define SMUIO_BASE__INST2_SEG4                     0
>+
>+#define SMUIO_BASE__INST3_SEG0                     0
>+#define SMUIO_BASE__INST3_SEG1                     0
>+#define SMUIO_BASE__INST3_SEG2                     0
>+#define SMUIO_BASE__INST3_SEG3                     0
>+#define SMUIO_BASE__INST3_SEG4                     0
>+
>+#define SMUIO_BASE__INST4_SEG0                     0
>+#define SMUIO_BASE__INST4_SEG1                     0
>+#define SMUIO_BASE__INST4_SEG2                     0
>+#define SMUIO_BASE__INST4_SEG3                     0
>+#define SMUIO_BASE__INST4_SEG4                     0
>+
>+#define SMUIO_BASE__INST5_SEG0                     0
>+#define SMUIO_BASE__INST5_SEG1                     0
>+#define SMUIO_BASE__INST5_SEG2                     0
>+#define SMUIO_BASE__INST5_SEG3                     0
>+#define SMUIO_BASE__INST5_SEG4                     0
>+
>+#define SMUIO_BASE__INST6_SEG0                     0
>+#define SMUIO_BASE__INST6_SEG1                     0
>+#define SMUIO_BASE__INST6_SEG2                     0
>+#define SMUIO_BASE__INST6_SEG3                     0
>+#define SMUIO_BASE__INST6_SEG4                     0
>+
>+#define THM_BASE__INST0_SEG0                       0x00016600
>+#define THM_BASE__INST0_SEG1                       0x02400C00
>+#define THM_BASE__INST0_SEG2                       0
>+#define THM_BASE__INST0_SEG3                       0
>+#define THM_BASE__INST0_SEG4                       0
>+
>+#define THM_BASE__INST1_SEG0                       0
>+#define THM_BASE__INST1_SEG1                       0
>+#define THM_BASE__INST1_SEG2                       0
>+#define THM_BASE__INST1_SEG3                       0
>+#define THM_BASE__INST1_SEG4                       0
>+
>+#define THM_BASE__INST2_SEG0                       0
>+#define THM_BASE__INST2_SEG1                       0
>+#define THM_BASE__INST2_SEG2                       0
>+#define THM_BASE__INST2_SEG3                       0
>+#define THM_BASE__INST2_SEG4                       0
>+
>+#define THM_BASE__INST3_SEG0                       0
>+#define THM_BASE__INST3_SEG1                       0
>+#define THM_BASE__INST3_SEG2                       0
>+#define THM_BASE__INST3_SEG3                       0
>+#define THM_BASE__INST3_SEG4                       0
>+
>+#define THM_BASE__INST4_SEG0                       0
>+#define THM_BASE__INST4_SEG1                       0
>+#define THM_BASE__INST4_SEG2                       0
>+#define THM_BASE__INST4_SEG3                       0
>+#define THM_BASE__INST4_SEG4                       0
>+
>+#define THM_BASE__INST5_SEG0                       0
>+#define THM_BASE__INST5_SEG1                       0
>+#define THM_BASE__INST5_SEG2                       0
>+#define THM_BASE__INST5_SEG3                       0
>+#define THM_BASE__INST5_SEG4                       0
>+
>+#define THM_BASE__INST6_SEG0                       0
>+#define THM_BASE__INST6_SEG1                       0
>+#define THM_BASE__INST6_SEG2                       0
>+#define THM_BASE__INST6_SEG3                       0
>+#define THM_BASE__INST6_SEG4                       0
>+
>+#define UMC_BASE__INST0_SEG0                       0x00014000
>+#define UMC_BASE__INST0_SEG1                       0x02425800
>+#define UMC_BASE__INST0_SEG2                       0
>+#define UMC_BASE__INST0_SEG3                       0
>+#define UMC_BASE__INST0_SEG4                       0
>+
>+#define UMC_BASE__INST1_SEG0                       0x00054000
>+#define UMC_BASE__INST1_SEG1                       0x02425C00
>+#define UMC_BASE__INST1_SEG2                       0
>+#define UMC_BASE__INST1_SEG3                       0
>+#define UMC_BASE__INST1_SEG4                       0
>+
>+#define UMC_BASE__INST2_SEG0                       0x00094000
>+#define UMC_BASE__INST2_SEG1                       0x02426000
>+#define UMC_BASE__INST2_SEG2                       0
>+#define UMC_BASE__INST2_SEG3                       0
>+#define UMC_BASE__INST2_SEG4                       0
>+
>+#define UMC_BASE__INST3_SEG0                       0x000D4000
>+#define UMC_BASE__INST3_SEG1                       0x02426400
>+#define UMC_BASE__INST3_SEG2                       0
>+#define UMC_BASE__INST3_SEG3                       0
>+#define UMC_BASE__INST3_SEG4                       0
>+
>+#define UMC_BASE__INST4_SEG0                       0
>+#define UMC_BASE__INST4_SEG1                       0
>+#define UMC_BASE__INST4_SEG2                       0
>+#define UMC_BASE__INST4_SEG3                       0
>+#define UMC_BASE__INST4_SEG4                       0
>+
>+#define UMC_BASE__INST5_SEG0                       0
>+#define UMC_BASE__INST5_SEG1                       0
>+#define UMC_BASE__INST5_SEG2                       0
>+#define UMC_BASE__INST5_SEG3                       0
>+#define UMC_BASE__INST5_SEG4                       0
>+
>+#define UMC_BASE__INST6_SEG0                       0
>+#define UMC_BASE__INST6_SEG1                       0
>+#define UMC_BASE__INST6_SEG2                       0
>+#define UMC_BASE__INST6_SEG3                       0
>+#define UMC_BASE__INST6_SEG4                       0
>+
>+#define USB0_BASE__INST0_SEG0                      0x0242A800
>+#define USB0_BASE__INST0_SEG1                      0x05B00000
>+#define USB0_BASE__INST0_SEG2                      0
>+#define USB0_BASE__INST0_SEG3                      0
>+#define USB0_BASE__INST0_SEG4                      0
>+
>+#define USB0_BASE__INST1_SEG0                      0
>+#define USB0_BASE__INST1_SEG1                      0
>+#define USB0_BASE__INST1_SEG2                      0
>+#define USB0_BASE__INST1_SEG3                      0
>+#define USB0_BASE__INST1_SEG4                      0
>+
>+#define USB0_BASE__INST2_SEG0                      0
>+#define USB0_BASE__INST2_SEG1                      0
>+#define USB0_BASE__INST2_SEG2                      0
>+#define USB0_BASE__INST2_SEG3                      0
>+#define USB0_BASE__INST2_SEG4                      0
>+
>+#define USB0_BASE__INST3_SEG0                      0
>+#define USB0_BASE__INST3_SEG1                      0
>+#define USB0_BASE__INST3_SEG2                      0
>+#define USB0_BASE__INST3_SEG3                      0
>+#define USB0_BASE__INST3_SEG4                      0
>+
>+#define USB0_BASE__INST4_SEG0                      0
>+#define USB0_BASE__INST4_SEG1                      0
>+#define USB0_BASE__INST4_SEG2                      0
>+#define USB0_BASE__INST4_SEG3                      0
>+#define USB0_BASE__INST4_SEG4                      0
>+
>+#define USB0_BASE__INST5_SEG0                      0
>+#define USB0_BASE__INST5_SEG1                      0
>+#define USB0_BASE__INST5_SEG2                      0
>+#define USB0_BASE__INST5_SEG3                      0
>+#define USB0_BASE__INST5_SEG4                      0
>+
>+#define USB0_BASE__INST6_SEG0                      0
>+#define USB0_BASE__INST6_SEG1                      0
>+#define USB0_BASE__INST6_SEG2                      0
>+#define USB0_BASE__INST6_SEG3                      0
>+#define USB0_BASE__INST6_SEG4                      0
>+
>+#define UVD0_BASE__INST0_SEG0                      0x00007800
>+#define UVD0_BASE__INST0_SEG1                      0x00007E00
>+#define UVD0_BASE__INST0_SEG2                      0x02403000
>+#define UVD0_BASE__INST0_SEG3                      0
>+#define UVD0_BASE__INST0_SEG4                      0
>+
>+#define UVD0_BASE__INST1_SEG0                      0
>+#define UVD0_BASE__INST1_SEG1                      0
>+#define UVD0_BASE__INST1_SEG2                      0
>+#define UVD0_BASE__INST1_SEG3                      0
>+#define UVD0_BASE__INST1_SEG4                      0
>+
>+#define UVD0_BASE__INST2_SEG0                      0
>+#define UVD0_BASE__INST2_SEG1                      0
>+#define UVD0_BASE__INST2_SEG2                      0
>+#define UVD0_BASE__INST2_SEG3                      0
>+#define UVD0_BASE__INST2_SEG4                      0
>+
>+#define UVD0_BASE__INST3_SEG0                      0
>+#define UVD0_BASE__INST3_SEG1                      0
>+#define UVD0_BASE__INST3_SEG2                      0
>+#define UVD0_BASE__INST3_SEG3                      0
>+#define UVD0_BASE__INST3_SEG4                      0
>+
>+#define UVD0_BASE__INST4_SEG0                      0
>+#define UVD0_BASE__INST4_SEG1                      0
>+#define UVD0_BASE__INST4_SEG2                      0
>+#define UVD0_BASE__INST4_SEG3                      0
>+#define UVD0_BASE__INST4_SEG4                      0
>+
>+#define UVD0_BASE__INST5_SEG0                      0
>+#define UVD0_BASE__INST5_SEG1                      0
>+#define UVD0_BASE__INST5_SEG2                      0
>+#define UVD0_BASE__INST5_SEG3                      0
>+#define UVD0_BASE__INST5_SEG4                      0
>+
>+#define UVD0_BASE__INST6_SEG0                      0
>+#define UVD0_BASE__INST6_SEG1                      0
>+#define UVD0_BASE__INST6_SEG2                      0
>+#define UVD0_BASE__INST6_SEG3                      0
>+#define UVD0_BASE__INST6_SEG4                      0
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/navi14_ip_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/navi14_ip_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/navi14_ip_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/navi14_ip_offset.h	2019-08-31 15:01:11.935736175 -0500
>@@ -0,0 +1,1119 @@
>+/*
>+ * Copyright (C) 2018  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _navi14_ip_offset_HEADER
>+#define _navi14_ip_offset_HEADER
>+
>+#define MAX_INSTANCE                                       7
>+#define MAX_SEGMENT                                        5
>+
>+
>+struct IP_BASE_INSTANCE
>+{
>+    unsigned int segment[MAX_SEGMENT];
>+};
>+
>+struct IP_BASE
>+{
>+    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
>+};
>+
>+
>+static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C00, 0x02408C00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } },
>+                                        { { 0x00016E00, 0x02401C00, 0, 0, 0 } },
>+                                        { { 0x00017000, 0x02402000, 0, 0, 0 } },
>+                                        { { 0x00017200, 0x02402400, 0, 0, 0 } },
>+                                        { { 0x0001B000, 0x0242D800, 0, 0, 0 } },
>+                                        { { 0x00017E00, 0x0240BC00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE HDA_BASE ={ { { { 0x004C0000, 0x02404800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE PCIE0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SDMA_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
>+                                        { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
>+                                        { { 0x00054000, 0x02425C00, 0, 0, 0 } },
>+                                        { { 0x00094000, 0x02426000, 0, 0, 0 } },
>+                                        { { 0x000D4000, 0x02426400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+
>+
>+#define ATHUB_BASE__INST0_SEG0                     0x00000C00
>+#define ATHUB_BASE__INST0_SEG1                     0x02408C00
>+#define ATHUB_BASE__INST0_SEG2                     0
>+#define ATHUB_BASE__INST0_SEG3                     0
>+#define ATHUB_BASE__INST0_SEG4                     0
>+
>+#define ATHUB_BASE__INST1_SEG0                     0
>+#define ATHUB_BASE__INST1_SEG1                     0
>+#define ATHUB_BASE__INST1_SEG2                     0
>+#define ATHUB_BASE__INST1_SEG3                     0
>+#define ATHUB_BASE__INST1_SEG4                     0
>+
>+#define ATHUB_BASE__INST2_SEG0                     0
>+#define ATHUB_BASE__INST2_SEG1                     0
>+#define ATHUB_BASE__INST2_SEG2                     0
>+#define ATHUB_BASE__INST2_SEG3                     0
>+#define ATHUB_BASE__INST2_SEG4                     0
>+
>+#define ATHUB_BASE__INST3_SEG0                     0
>+#define ATHUB_BASE__INST3_SEG1                     0
>+#define ATHUB_BASE__INST3_SEG2                     0
>+#define ATHUB_BASE__INST3_SEG3                     0
>+#define ATHUB_BASE__INST3_SEG4                     0
>+
>+#define ATHUB_BASE__INST4_SEG0                     0
>+#define ATHUB_BASE__INST4_SEG1                     0
>+#define ATHUB_BASE__INST4_SEG2                     0
>+#define ATHUB_BASE__INST4_SEG3                     0
>+#define ATHUB_BASE__INST4_SEG4                     0
>+
>+#define ATHUB_BASE__INST5_SEG0                     0
>+#define ATHUB_BASE__INST5_SEG1                     0
>+#define ATHUB_BASE__INST5_SEG2                     0
>+#define ATHUB_BASE__INST5_SEG3                     0
>+#define ATHUB_BASE__INST5_SEG4                     0
>+
>+#define ATHUB_BASE__INST6_SEG0                     0
>+#define ATHUB_BASE__INST6_SEG1                     0
>+#define ATHUB_BASE__INST6_SEG2                     0
>+#define ATHUB_BASE__INST6_SEG3                     0
>+#define ATHUB_BASE__INST6_SEG4                     0
>+
>+#define CLK_BASE__INST0_SEG0                       0x00016C00
>+#define CLK_BASE__INST0_SEG1                       0x02401800
>+#define CLK_BASE__INST0_SEG2                       0
>+#define CLK_BASE__INST0_SEG3                       0
>+#define CLK_BASE__INST0_SEG4                       0
>+
>+#define CLK_BASE__INST1_SEG0                       0x00016E00
>+#define CLK_BASE__INST1_SEG1                       0x02401C00
>+#define CLK_BASE__INST1_SEG2                       0
>+#define CLK_BASE__INST1_SEG3                       0
>+#define CLK_BASE__INST1_SEG4                       0
>+
>+#define CLK_BASE__INST2_SEG0                       0x00017000
>+#define CLK_BASE__INST2_SEG1                       0x02402000
>+#define CLK_BASE__INST2_SEG2                       0
>+#define CLK_BASE__INST2_SEG3                       0
>+#define CLK_BASE__INST2_SEG4                       0
>+
>+#define CLK_BASE__INST3_SEG0                       0x00017200
>+#define CLK_BASE__INST3_SEG1                       0x02402400
>+#define CLK_BASE__INST3_SEG2                       0
>+#define CLK_BASE__INST3_SEG3                       0
>+#define CLK_BASE__INST3_SEG4                       0
>+
>+#define CLK_BASE__INST4_SEG0                       0x0001B000
>+#define CLK_BASE__INST4_SEG1                       0x0242D800
>+#define CLK_BASE__INST4_SEG2                       0
>+#define CLK_BASE__INST4_SEG3                       0
>+#define CLK_BASE__INST4_SEG4                       0
>+
>+#define CLK_BASE__INST5_SEG0                       0x00017E00
>+#define CLK_BASE__INST5_SEG1                       0x0240BC00
>+#define CLK_BASE__INST5_SEG2                       0
>+#define CLK_BASE__INST5_SEG3                       0
>+#define CLK_BASE__INST5_SEG4                       0
>+
>+#define CLK_BASE__INST6_SEG0                       0
>+#define CLK_BASE__INST6_SEG1                       0
>+#define CLK_BASE__INST6_SEG2                       0
>+#define CLK_BASE__INST6_SEG3                       0
>+#define CLK_BASE__INST6_SEG4                       0
>+
>+#define DF_BASE__INST0_SEG0                        0x00007000
>+#define DF_BASE__INST0_SEG1                        0x0240B800
>+#define DF_BASE__INST0_SEG2                        0
>+#define DF_BASE__INST0_SEG3                        0
>+#define DF_BASE__INST0_SEG4                        0
>+
>+#define DF_BASE__INST1_SEG0                        0
>+#define DF_BASE__INST1_SEG1                        0
>+#define DF_BASE__INST1_SEG2                        0
>+#define DF_BASE__INST1_SEG3                        0
>+#define DF_BASE__INST1_SEG4                        0
>+
>+#define DF_BASE__INST2_SEG0                        0
>+#define DF_BASE__INST2_SEG1                        0
>+#define DF_BASE__INST2_SEG2                        0
>+#define DF_BASE__INST2_SEG3                        0
>+#define DF_BASE__INST2_SEG4                        0
>+
>+#define DF_BASE__INST3_SEG0                        0
>+#define DF_BASE__INST3_SEG1                        0
>+#define DF_BASE__INST3_SEG2                        0
>+#define DF_BASE__INST3_SEG3                        0
>+#define DF_BASE__INST3_SEG4                        0
>+
>+#define DF_BASE__INST4_SEG0                        0
>+#define DF_BASE__INST4_SEG1                        0
>+#define DF_BASE__INST4_SEG2                        0
>+#define DF_BASE__INST4_SEG3                        0
>+#define DF_BASE__INST4_SEG4                        0
>+
>+#define DF_BASE__INST5_SEG0                        0
>+#define DF_BASE__INST5_SEG1                        0
>+#define DF_BASE__INST5_SEG2                        0
>+#define DF_BASE__INST5_SEG3                        0
>+#define DF_BASE__INST5_SEG4                        0
>+
>+#define DF_BASE__INST6_SEG0                        0
>+#define DF_BASE__INST6_SEG1                        0
>+#define DF_BASE__INST6_SEG2                        0
>+#define DF_BASE__INST6_SEG3                        0
>+#define DF_BASE__INST6_SEG4                        0
>+
>+#define DIO_BASE__INST0_SEG0                       0x02404000
>+#define DIO_BASE__INST0_SEG1                       0
>+#define DIO_BASE__INST0_SEG2                       0
>+#define DIO_BASE__INST0_SEG3                       0
>+#define DIO_BASE__INST0_SEG4                       0
>+
>+#define DIO_BASE__INST1_SEG0                       0
>+#define DIO_BASE__INST1_SEG1                       0
>+#define DIO_BASE__INST1_SEG2                       0
>+#define DIO_BASE__INST1_SEG3                       0
>+#define DIO_BASE__INST1_SEG4                       0
>+
>+#define DIO_BASE__INST2_SEG0                       0
>+#define DIO_BASE__INST2_SEG1                       0
>+#define DIO_BASE__INST2_SEG2                       0
>+#define DIO_BASE__INST2_SEG3                       0
>+#define DIO_BASE__INST2_SEG4                       0
>+
>+#define DIO_BASE__INST3_SEG0                       0
>+#define DIO_BASE__INST3_SEG1                       0
>+#define DIO_BASE__INST3_SEG2                       0
>+#define DIO_BASE__INST3_SEG3                       0
>+#define DIO_BASE__INST3_SEG4                       0
>+
>+#define DIO_BASE__INST4_SEG0                       0
>+#define DIO_BASE__INST4_SEG1                       0
>+#define DIO_BASE__INST4_SEG2                       0
>+#define DIO_BASE__INST4_SEG3                       0
>+#define DIO_BASE__INST4_SEG4                       0
>+
>+#define DIO_BASE__INST5_SEG0                       0
>+#define DIO_BASE__INST5_SEG1                       0
>+#define DIO_BASE__INST5_SEG2                       0
>+#define DIO_BASE__INST5_SEG3                       0
>+#define DIO_BASE__INST5_SEG4                       0
>+
>+#define DIO_BASE__INST6_SEG0                       0
>+#define DIO_BASE__INST6_SEG1                       0
>+#define DIO_BASE__INST6_SEG2                       0
>+#define DIO_BASE__INST6_SEG3                       0
>+#define DIO_BASE__INST6_SEG4                       0
>+
>+#define DMU_BASE__INST0_SEG0                       0x00000012
>+#define DMU_BASE__INST0_SEG1                       0x000000C0
>+#define DMU_BASE__INST0_SEG2                       0x000034C0
>+#define DMU_BASE__INST0_SEG3                       0x00009000
>+#define DMU_BASE__INST0_SEG4                       0x02403C00
>+
>+#define DMU_BASE__INST1_SEG0                       0
>+#define DMU_BASE__INST1_SEG1                       0
>+#define DMU_BASE__INST1_SEG2                       0
>+#define DMU_BASE__INST1_SEG3                       0
>+#define DMU_BASE__INST1_SEG4                       0
>+
>+#define DMU_BASE__INST2_SEG0                       0
>+#define DMU_BASE__INST2_SEG1                       0
>+#define DMU_BASE__INST2_SEG2                       0
>+#define DMU_BASE__INST2_SEG3                       0
>+#define DMU_BASE__INST2_SEG4                       0
>+
>+#define DMU_BASE__INST3_SEG0                       0
>+#define DMU_BASE__INST3_SEG1                       0
>+#define DMU_BASE__INST3_SEG2                       0
>+#define DMU_BASE__INST3_SEG3                       0
>+#define DMU_BASE__INST3_SEG4                       0
>+
>+#define DMU_BASE__INST4_SEG0                       0
>+#define DMU_BASE__INST4_SEG1                       0
>+#define DMU_BASE__INST4_SEG2                       0
>+#define DMU_BASE__INST4_SEG3                       0
>+#define DMU_BASE__INST4_SEG4                       0
>+
>+#define DMU_BASE__INST5_SEG0                       0
>+#define DMU_BASE__INST5_SEG1                       0
>+#define DMU_BASE__INST5_SEG2                       0
>+#define DMU_BASE__INST5_SEG3                       0
>+#define DMU_BASE__INST5_SEG4                       0
>+
>+#define DMU_BASE__INST6_SEG0                       0
>+#define DMU_BASE__INST6_SEG1                       0
>+#define DMU_BASE__INST6_SEG2                       0
>+#define DMU_BASE__INST6_SEG3                       0
>+#define DMU_BASE__INST6_SEG4                       0
>+
>+#define DPCS_BASE__INST0_SEG0                      0x00000012
>+#define DPCS_BASE__INST0_SEG1                      0x000000C0
>+#define DPCS_BASE__INST0_SEG2                      0x000034C0
>+#define DPCS_BASE__INST0_SEG3                      0x00009000
>+#define DPCS_BASE__INST0_SEG4                      0x02403C00
>+
>+#define DPCS_BASE__INST1_SEG0                      0
>+#define DPCS_BASE__INST1_SEG1                      0
>+#define DPCS_BASE__INST1_SEG2                      0
>+#define DPCS_BASE__INST1_SEG3                      0
>+#define DPCS_BASE__INST1_SEG4                      0
>+
>+#define DPCS_BASE__INST2_SEG0                      0
>+#define DPCS_BASE__INST2_SEG1                      0
>+#define DPCS_BASE__INST2_SEG2                      0
>+#define DPCS_BASE__INST2_SEG3                      0
>+#define DPCS_BASE__INST2_SEG4                      0
>+
>+#define DPCS_BASE__INST3_SEG0                      0
>+#define DPCS_BASE__INST3_SEG1                      0
>+#define DPCS_BASE__INST3_SEG2                      0
>+#define DPCS_BASE__INST3_SEG3                      0
>+#define DPCS_BASE__INST3_SEG4                      0
>+
>+#define DPCS_BASE__INST4_SEG0                      0
>+#define DPCS_BASE__INST4_SEG1                      0
>+#define DPCS_BASE__INST4_SEG2                      0
>+#define DPCS_BASE__INST4_SEG3                      0
>+#define DPCS_BASE__INST4_SEG4                      0
>+
>+#define DPCS_BASE__INST5_SEG0                      0
>+#define DPCS_BASE__INST5_SEG1                      0
>+#define DPCS_BASE__INST5_SEG2                      0
>+#define DPCS_BASE__INST5_SEG3                      0
>+#define DPCS_BASE__INST5_SEG4                      0
>+
>+#define DPCS_BASE__INST6_SEG0                      0
>+#define DPCS_BASE__INST6_SEG1                      0
>+#define DPCS_BASE__INST6_SEG2                      0
>+#define DPCS_BASE__INST6_SEG3                      0
>+#define DPCS_BASE__INST6_SEG4                      0
>+
>+#define FUSE_BASE__INST0_SEG0                      0x00017400
>+#define FUSE_BASE__INST0_SEG1                      0x02401400
>+#define FUSE_BASE__INST0_SEG2                      0
>+#define FUSE_BASE__INST0_SEG3                      0
>+#define FUSE_BASE__INST0_SEG4                      0
>+
>+#define FUSE_BASE__INST1_SEG0                      0
>+#define FUSE_BASE__INST1_SEG1                      0
>+#define FUSE_BASE__INST1_SEG2                      0
>+#define FUSE_BASE__INST1_SEG3                      0
>+#define FUSE_BASE__INST1_SEG4                      0
>+
>+#define FUSE_BASE__INST2_SEG0                      0
>+#define FUSE_BASE__INST2_SEG1                      0
>+#define FUSE_BASE__INST2_SEG2                      0
>+#define FUSE_BASE__INST2_SEG3                      0
>+#define FUSE_BASE__INST2_SEG4                      0
>+
>+#define FUSE_BASE__INST3_SEG0                      0
>+#define FUSE_BASE__INST3_SEG1                      0
>+#define FUSE_BASE__INST3_SEG2                      0
>+#define FUSE_BASE__INST3_SEG3                      0
>+#define FUSE_BASE__INST3_SEG4                      0
>+
>+#define FUSE_BASE__INST4_SEG0                      0
>+#define FUSE_BASE__INST4_SEG1                      0
>+#define FUSE_BASE__INST4_SEG2                      0
>+#define FUSE_BASE__INST4_SEG3                      0
>+#define FUSE_BASE__INST4_SEG4                      0
>+
>+#define FUSE_BASE__INST5_SEG0                      0
>+#define FUSE_BASE__INST5_SEG1                      0
>+#define FUSE_BASE__INST5_SEG2                      0
>+#define FUSE_BASE__INST5_SEG3                      0
>+#define FUSE_BASE__INST5_SEG4                      0
>+
>+#define FUSE_BASE__INST6_SEG0                      0
>+#define FUSE_BASE__INST6_SEG1                      0
>+#define FUSE_BASE__INST6_SEG2                      0
>+#define FUSE_BASE__INST6_SEG3                      0
>+#define FUSE_BASE__INST6_SEG4                      0
>+
>+#define GC_BASE__INST0_SEG0                        0x00001260
>+#define GC_BASE__INST0_SEG1                        0x0000A000
>+#define GC_BASE__INST0_SEG2                        0x02402C00
>+#define GC_BASE__INST0_SEG3                        0
>+#define GC_BASE__INST0_SEG4                        0
>+
>+#define GC_BASE__INST1_SEG0                        0
>+#define GC_BASE__INST1_SEG1                        0
>+#define GC_BASE__INST1_SEG2                        0
>+#define GC_BASE__INST1_SEG3                        0
>+#define GC_BASE__INST1_SEG4                        0
>+
>+#define GC_BASE__INST2_SEG0                        0
>+#define GC_BASE__INST2_SEG1                        0
>+#define GC_BASE__INST2_SEG2                        0
>+#define GC_BASE__INST2_SEG3                        0
>+#define GC_BASE__INST2_SEG4                        0
>+
>+#define GC_BASE__INST3_SEG0                        0
>+#define GC_BASE__INST3_SEG1                        0
>+#define GC_BASE__INST3_SEG2                        0
>+#define GC_BASE__INST3_SEG3                        0
>+#define GC_BASE__INST3_SEG4                        0
>+
>+#define GC_BASE__INST4_SEG0                        0
>+#define GC_BASE__INST4_SEG1                        0
>+#define GC_BASE__INST4_SEG2                        0
>+#define GC_BASE__INST4_SEG3                        0
>+#define GC_BASE__INST4_SEG4                        0
>+
>+#define GC_BASE__INST5_SEG0                        0
>+#define GC_BASE__INST5_SEG1                        0
>+#define GC_BASE__INST5_SEG2                        0
>+#define GC_BASE__INST5_SEG3                        0
>+#define GC_BASE__INST5_SEG4                        0
>+
>+#define GC_BASE__INST6_SEG0                        0
>+#define GC_BASE__INST6_SEG1                        0
>+#define GC_BASE__INST6_SEG2                        0
>+#define GC_BASE__INST6_SEG3                        0
>+#define GC_BASE__INST6_SEG4                        0
>+
>+#define HDA_BASE__INST0_SEG0                       0x004C0000
>+#define HDA_BASE__INST0_SEG1                       0x02404800
>+#define HDA_BASE__INST0_SEG2                       0
>+#define HDA_BASE__INST0_SEG3                       0
>+#define HDA_BASE__INST0_SEG4                       0
>+
>+#define HDA_BASE__INST1_SEG0                       0
>+#define HDA_BASE__INST1_SEG1                       0
>+#define HDA_BASE__INST1_SEG2                       0
>+#define HDA_BASE__INST1_SEG3                       0
>+#define HDA_BASE__INST1_SEG4                       0
>+
>+#define HDA_BASE__INST2_SEG0                       0
>+#define HDA_BASE__INST2_SEG1                       0
>+#define HDA_BASE__INST2_SEG2                       0
>+#define HDA_BASE__INST2_SEG3                       0
>+#define HDA_BASE__INST2_SEG4                       0
>+
>+#define HDA_BASE__INST3_SEG0                       0
>+#define HDA_BASE__INST3_SEG1                       0
>+#define HDA_BASE__INST3_SEG2                       0
>+#define HDA_BASE__INST3_SEG3                       0
>+#define HDA_BASE__INST3_SEG4                       0
>+
>+#define HDA_BASE__INST4_SEG0                       0
>+#define HDA_BASE__INST4_SEG1                       0
>+#define HDA_BASE__INST4_SEG2                       0
>+#define HDA_BASE__INST4_SEG3                       0
>+#define HDA_BASE__INST4_SEG4                       0
>+
>+#define HDA_BASE__INST5_SEG0                       0
>+#define HDA_BASE__INST5_SEG1                       0
>+#define HDA_BASE__INST5_SEG2                       0
>+#define HDA_BASE__INST5_SEG3                       0
>+#define HDA_BASE__INST5_SEG4                       0
>+
>+#define HDA_BASE__INST6_SEG0                       0
>+#define HDA_BASE__INST6_SEG1                       0
>+#define HDA_BASE__INST6_SEG2                       0
>+#define HDA_BASE__INST6_SEG3                       0
>+#define HDA_BASE__INST6_SEG4                       0
>+
>+#define HDP_BASE__INST0_SEG0                       0x00000F20
>+#define HDP_BASE__INST0_SEG1                       0x0240A400
>+#define HDP_BASE__INST0_SEG2                       0
>+#define HDP_BASE__INST0_SEG3                       0
>+#define HDP_BASE__INST0_SEG4                       0
>+
>+#define HDP_BASE__INST1_SEG0                       0
>+#define HDP_BASE__INST1_SEG1                       0
>+#define HDP_BASE__INST1_SEG2                       0
>+#define HDP_BASE__INST1_SEG3                       0
>+#define HDP_BASE__INST1_SEG4                       0
>+
>+#define HDP_BASE__INST2_SEG0                       0
>+#define HDP_BASE__INST2_SEG1                       0
>+#define HDP_BASE__INST2_SEG2                       0
>+#define HDP_BASE__INST2_SEG3                       0
>+#define HDP_BASE__INST2_SEG4                       0
>+
>+#define HDP_BASE__INST3_SEG0                       0
>+#define HDP_BASE__INST3_SEG1                       0
>+#define HDP_BASE__INST3_SEG2                       0
>+#define HDP_BASE__INST3_SEG3                       0
>+#define HDP_BASE__INST3_SEG4                       0
>+
>+#define HDP_BASE__INST4_SEG0                       0
>+#define HDP_BASE__INST4_SEG1                       0
>+#define HDP_BASE__INST4_SEG2                       0
>+#define HDP_BASE__INST4_SEG3                       0
>+#define HDP_BASE__INST4_SEG4                       0
>+
>+#define HDP_BASE__INST5_SEG0                       0
>+#define HDP_BASE__INST5_SEG1                       0
>+#define HDP_BASE__INST5_SEG2                       0
>+#define HDP_BASE__INST5_SEG3                       0
>+#define HDP_BASE__INST5_SEG4                       0
>+
>+#define HDP_BASE__INST6_SEG0                       0
>+#define HDP_BASE__INST6_SEG1                       0
>+#define HDP_BASE__INST6_SEG2                       0
>+#define HDP_BASE__INST6_SEG3                       0
>+#define HDP_BASE__INST6_SEG4                       0
>+
>+#define MMHUB_BASE__INST0_SEG0                     0x0001A000
>+#define MMHUB_BASE__INST0_SEG1                     0x02408800
>+#define MMHUB_BASE__INST0_SEG2                     0
>+#define MMHUB_BASE__INST0_SEG3                     0
>+#define MMHUB_BASE__INST0_SEG4                     0
>+
>+#define MMHUB_BASE__INST1_SEG0                     0
>+#define MMHUB_BASE__INST1_SEG1                     0
>+#define MMHUB_BASE__INST1_SEG2                     0
>+#define MMHUB_BASE__INST1_SEG3                     0
>+#define MMHUB_BASE__INST1_SEG4                     0
>+
>+#define MMHUB_BASE__INST2_SEG0                     0
>+#define MMHUB_BASE__INST2_SEG1                     0
>+#define MMHUB_BASE__INST2_SEG2                     0
>+#define MMHUB_BASE__INST2_SEG3                     0
>+#define MMHUB_BASE__INST2_SEG4                     0
>+
>+#define MMHUB_BASE__INST3_SEG0                     0
>+#define MMHUB_BASE__INST3_SEG1                     0
>+#define MMHUB_BASE__INST3_SEG2                     0
>+#define MMHUB_BASE__INST3_SEG3                     0
>+#define MMHUB_BASE__INST3_SEG4                     0
>+
>+#define MMHUB_BASE__INST4_SEG0                     0
>+#define MMHUB_BASE__INST4_SEG1                     0
>+#define MMHUB_BASE__INST4_SEG2                     0
>+#define MMHUB_BASE__INST4_SEG3                     0
>+#define MMHUB_BASE__INST4_SEG4                     0
>+
>+#define MMHUB_BASE__INST5_SEG0                     0
>+#define MMHUB_BASE__INST5_SEG1                     0
>+#define MMHUB_BASE__INST5_SEG2                     0
>+#define MMHUB_BASE__INST5_SEG3                     0
>+#define MMHUB_BASE__INST5_SEG4                     0
>+
>+#define MMHUB_BASE__INST6_SEG0                     0
>+#define MMHUB_BASE__INST6_SEG1                     0
>+#define MMHUB_BASE__INST6_SEG2                     0
>+#define MMHUB_BASE__INST6_SEG3                     0
>+#define MMHUB_BASE__INST6_SEG4                     0
>+
>+#define MP0_BASE__INST0_SEG0                       0x00016000
>+#define MP0_BASE__INST0_SEG1                       0x00DC0000
>+#define MP0_BASE__INST0_SEG2                       0x00E00000
>+#define MP0_BASE__INST0_SEG3                       0x00E40000
>+#define MP0_BASE__INST0_SEG4                       0x0243FC00
>+
>+#define MP0_BASE__INST1_SEG0                       0
>+#define MP0_BASE__INST1_SEG1                       0
>+#define MP0_BASE__INST1_SEG2                       0
>+#define MP0_BASE__INST1_SEG3                       0
>+#define MP0_BASE__INST1_SEG4                       0
>+
>+#define MP0_BASE__INST2_SEG0                       0
>+#define MP0_BASE__INST2_SEG1                       0
>+#define MP0_BASE__INST2_SEG2                       0
>+#define MP0_BASE__INST2_SEG3                       0
>+#define MP0_BASE__INST2_SEG4                       0
>+
>+#define MP0_BASE__INST3_SEG0                       0
>+#define MP0_BASE__INST3_SEG1                       0
>+#define MP0_BASE__INST3_SEG2                       0
>+#define MP0_BASE__INST3_SEG3                       0
>+#define MP0_BASE__INST3_SEG4                       0
>+
>+#define MP0_BASE__INST4_SEG0                       0
>+#define MP0_BASE__INST4_SEG1                       0
>+#define MP0_BASE__INST4_SEG2                       0
>+#define MP0_BASE__INST4_SEG3                       0
>+#define MP0_BASE__INST4_SEG4                       0
>+
>+#define MP0_BASE__INST5_SEG0                       0
>+#define MP0_BASE__INST5_SEG1                       0
>+#define MP0_BASE__INST5_SEG2                       0
>+#define MP0_BASE__INST5_SEG3                       0
>+#define MP0_BASE__INST5_SEG4                       0
>+
>+#define MP0_BASE__INST6_SEG0                       0
>+#define MP0_BASE__INST6_SEG1                       0
>+#define MP0_BASE__INST6_SEG2                       0
>+#define MP0_BASE__INST6_SEG3                       0
>+#define MP0_BASE__INST6_SEG4                       0
>+
>+#define MP1_BASE__INST0_SEG0                       0x00016000
>+#define MP1_BASE__INST0_SEG1                       0x00DC0000
>+#define MP1_BASE__INST0_SEG2                       0x00E00000
>+#define MP1_BASE__INST0_SEG3                       0x00E40000
>+#define MP1_BASE__INST0_SEG4                       0x0243FC00
>+
>+#define MP1_BASE__INST1_SEG0                       0
>+#define MP1_BASE__INST1_SEG1                       0
>+#define MP1_BASE__INST1_SEG2                       0
>+#define MP1_BASE__INST1_SEG3                       0
>+#define MP1_BASE__INST1_SEG4                       0
>+
>+#define MP1_BASE__INST2_SEG0                       0
>+#define MP1_BASE__INST2_SEG1                       0
>+#define MP1_BASE__INST2_SEG2                       0
>+#define MP1_BASE__INST2_SEG3                       0
>+#define MP1_BASE__INST2_SEG4                       0
>+
>+#define MP1_BASE__INST3_SEG0                       0
>+#define MP1_BASE__INST3_SEG1                       0
>+#define MP1_BASE__INST3_SEG2                       0
>+#define MP1_BASE__INST3_SEG3                       0
>+#define MP1_BASE__INST3_SEG4                       0
>+
>+#define MP1_BASE__INST4_SEG0                       0
>+#define MP1_BASE__INST4_SEG1                       0
>+#define MP1_BASE__INST4_SEG2                       0
>+#define MP1_BASE__INST4_SEG3                       0
>+#define MP1_BASE__INST4_SEG4                       0
>+
>+#define MP1_BASE__INST5_SEG0                       0
>+#define MP1_BASE__INST5_SEG1                       0
>+#define MP1_BASE__INST5_SEG2                       0
>+#define MP1_BASE__INST5_SEG3                       0
>+#define MP1_BASE__INST5_SEG4                       0
>+
>+#define MP1_BASE__INST6_SEG0                       0
>+#define MP1_BASE__INST6_SEG1                       0
>+#define MP1_BASE__INST6_SEG2                       0
>+#define MP1_BASE__INST6_SEG3                       0
>+#define MP1_BASE__INST6_SEG4                       0
>+
>+#define NBIF0_BASE__INST0_SEG0                     0x00000000
>+#define NBIF0_BASE__INST0_SEG1                     0x00000014
>+#define NBIF0_BASE__INST0_SEG2                     0x00000D20
>+#define NBIF0_BASE__INST0_SEG3                     0x00010400
>+#define NBIF0_BASE__INST0_SEG4                     0x0241B000
>+
>+#define NBIF0_BASE__INST1_SEG0                     0
>+#define NBIF0_BASE__INST1_SEG1                     0
>+#define NBIF0_BASE__INST1_SEG2                     0
>+#define NBIF0_BASE__INST1_SEG3                     0
>+#define NBIF0_BASE__INST1_SEG4                     0
>+
>+#define NBIF0_BASE__INST2_SEG0                     0
>+#define NBIF0_BASE__INST2_SEG1                     0
>+#define NBIF0_BASE__INST2_SEG2                     0
>+#define NBIF0_BASE__INST2_SEG3                     0
>+#define NBIF0_BASE__INST2_SEG4                     0
>+
>+#define NBIF0_BASE__INST3_SEG0                     0
>+#define NBIF0_BASE__INST3_SEG1                     0
>+#define NBIF0_BASE__INST3_SEG2                     0
>+#define NBIF0_BASE__INST3_SEG3                     0
>+#define NBIF0_BASE__INST3_SEG4                     0
>+
>+#define NBIF0_BASE__INST4_SEG0                     0
>+#define NBIF0_BASE__INST4_SEG1                     0
>+#define NBIF0_BASE__INST4_SEG2                     0
>+#define NBIF0_BASE__INST4_SEG3                     0
>+#define NBIF0_BASE__INST4_SEG4                     0
>+
>+#define NBIF0_BASE__INST5_SEG0                     0
>+#define NBIF0_BASE__INST5_SEG1                     0
>+#define NBIF0_BASE__INST5_SEG2                     0
>+#define NBIF0_BASE__INST5_SEG3                     0
>+#define NBIF0_BASE__INST5_SEG4                     0
>+
>+#define NBIF0_BASE__INST6_SEG0                     0
>+#define NBIF0_BASE__INST6_SEG1                     0
>+#define NBIF0_BASE__INST6_SEG2                     0
>+#define NBIF0_BASE__INST6_SEG3                     0
>+#define NBIF0_BASE__INST6_SEG4                     0
>+
>+#define OSSSYS_BASE__INST0_SEG0                    0x000010A0
>+#define OSSSYS_BASE__INST0_SEG1                    0x0240A000
>+#define OSSSYS_BASE__INST0_SEG2                    0
>+#define OSSSYS_BASE__INST0_SEG3                    0
>+#define OSSSYS_BASE__INST0_SEG4                    0
>+
>+#define OSSSYS_BASE__INST1_SEG0                    0
>+#define OSSSYS_BASE__INST1_SEG1                    0
>+#define OSSSYS_BASE__INST1_SEG2                    0
>+#define OSSSYS_BASE__INST1_SEG3                    0
>+#define OSSSYS_BASE__INST1_SEG4                    0
>+
>+#define OSSSYS_BASE__INST2_SEG0                    0
>+#define OSSSYS_BASE__INST2_SEG1                    0
>+#define OSSSYS_BASE__INST2_SEG2                    0
>+#define OSSSYS_BASE__INST2_SEG3                    0
>+#define OSSSYS_BASE__INST2_SEG4                    0
>+
>+#define OSSSYS_BASE__INST3_SEG0                    0
>+#define OSSSYS_BASE__INST3_SEG1                    0
>+#define OSSSYS_BASE__INST3_SEG2                    0
>+#define OSSSYS_BASE__INST3_SEG3                    0
>+#define OSSSYS_BASE__INST3_SEG4                    0
>+
>+#define OSSSYS_BASE__INST4_SEG0                    0
>+#define OSSSYS_BASE__INST4_SEG1                    0
>+#define OSSSYS_BASE__INST4_SEG2                    0
>+#define OSSSYS_BASE__INST4_SEG3                    0
>+#define OSSSYS_BASE__INST4_SEG4                    0
>+
>+#define OSSSYS_BASE__INST5_SEG0                    0
>+#define OSSSYS_BASE__INST5_SEG1                    0
>+#define OSSSYS_BASE__INST5_SEG2                    0
>+#define OSSSYS_BASE__INST5_SEG3                    0
>+#define OSSSYS_BASE__INST5_SEG4                    0
>+
>+#define OSSSYS_BASE__INST6_SEG0                    0
>+#define OSSSYS_BASE__INST6_SEG1                    0
>+#define OSSSYS_BASE__INST6_SEG2                    0
>+#define OSSSYS_BASE__INST6_SEG3                    0
>+#define OSSSYS_BASE__INST6_SEG4                    0
>+
>+#define PCIE0_BASE__INST0_SEG0                     0x00000000
>+#define PCIE0_BASE__INST0_SEG1                     0x00000014
>+#define PCIE0_BASE__INST0_SEG2                     0x00000D20
>+#define PCIE0_BASE__INST0_SEG3                     0x00010400
>+#define PCIE0_BASE__INST0_SEG4                     0x0241B000
>+
>+#define PCIE0_BASE__INST1_SEG0                     0
>+#define PCIE0_BASE__INST1_SEG1                     0
>+#define PCIE0_BASE__INST1_SEG2                     0
>+#define PCIE0_BASE__INST1_SEG3                     0
>+#define PCIE0_BASE__INST1_SEG4                     0
>+
>+#define PCIE0_BASE__INST2_SEG0                     0
>+#define PCIE0_BASE__INST2_SEG1                     0
>+#define PCIE0_BASE__INST2_SEG2                     0
>+#define PCIE0_BASE__INST2_SEG3                     0
>+#define PCIE0_BASE__INST2_SEG4                     0
>+
>+#define PCIE0_BASE__INST3_SEG0                     0
>+#define PCIE0_BASE__INST3_SEG1                     0
>+#define PCIE0_BASE__INST3_SEG2                     0
>+#define PCIE0_BASE__INST3_SEG3                     0
>+#define PCIE0_BASE__INST3_SEG4                     0
>+
>+#define PCIE0_BASE__INST4_SEG0                     0
>+#define PCIE0_BASE__INST4_SEG1                     0
>+#define PCIE0_BASE__INST4_SEG2                     0
>+#define PCIE0_BASE__INST4_SEG3                     0
>+#define PCIE0_BASE__INST4_SEG4                     0
>+
>+#define PCIE0_BASE__INST5_SEG0                     0
>+#define PCIE0_BASE__INST5_SEG1                     0
>+#define PCIE0_BASE__INST5_SEG2                     0
>+#define PCIE0_BASE__INST5_SEG3                     0
>+#define PCIE0_BASE__INST5_SEG4                     0
>+
>+#define PCIE0_BASE__INST6_SEG0                     0
>+#define PCIE0_BASE__INST6_SEG1                     0
>+#define PCIE0_BASE__INST6_SEG2                     0
>+#define PCIE0_BASE__INST6_SEG3                     0
>+#define PCIE0_BASE__INST6_SEG4                     0
>+
>+#define SDMA_BASE__INST0_SEG0                      0x00001260
>+#define SDMA_BASE__INST0_SEG1                      0x0000A000
>+#define SDMA_BASE__INST0_SEG2                      0x02402C00
>+#define SDMA_BASE__INST0_SEG3                      0
>+#define SDMA_BASE__INST0_SEG4                      0
>+
>+#define SDMA_BASE__INST1_SEG0                      0x00001260
>+#define SDMA_BASE__INST1_SEG1                      0x0000A000
>+#define SDMA_BASE__INST1_SEG2                      0x02402C00
>+#define SDMA_BASE__INST1_SEG3                      0
>+#define SDMA_BASE__INST1_SEG4                      0
>+
>+#define SDMA_BASE__INST2_SEG0                      0
>+#define SDMA_BASE__INST2_SEG1                      0
>+#define SDMA_BASE__INST2_SEG2                      0
>+#define SDMA_BASE__INST2_SEG3                      0
>+#define SDMA_BASE__INST2_SEG4                      0
>+
>+#define SDMA_BASE__INST3_SEG0                      0
>+#define SDMA_BASE__INST3_SEG1                      0
>+#define SDMA_BASE__INST3_SEG2                      0
>+#define SDMA_BASE__INST3_SEG3                      0
>+#define SDMA_BASE__INST3_SEG4                      0
>+
>+#define SDMA_BASE__INST4_SEG0                      0
>+#define SDMA_BASE__INST4_SEG1                      0
>+#define SDMA_BASE__INST4_SEG2                      0
>+#define SDMA_BASE__INST4_SEG3                      0
>+#define SDMA_BASE__INST4_SEG4                      0
>+
>+#define SDMA_BASE__INST5_SEG0                      0
>+#define SDMA_BASE__INST5_SEG1                      0
>+#define SDMA_BASE__INST5_SEG2                      0
>+#define SDMA_BASE__INST5_SEG3                      0
>+#define SDMA_BASE__INST5_SEG4                      0
>+
>+#define SDMA_BASE__INST6_SEG0                      0
>+#define SDMA_BASE__INST6_SEG1                      0
>+#define SDMA_BASE__INST6_SEG2                      0
>+#define SDMA_BASE__INST6_SEG3                      0
>+#define SDMA_BASE__INST6_SEG4                      0
>+
>+#define SMUIO_BASE__INST0_SEG0                     0x00016800
>+#define SMUIO_BASE__INST0_SEG1                     0x00016A00
>+#define SMUIO_BASE__INST0_SEG2                     0x00440000
>+#define SMUIO_BASE__INST0_SEG3                     0x02401000
>+#define SMUIO_BASE__INST0_SEG4                     0
>+
>+#define SMUIO_BASE__INST1_SEG0                     0
>+#define SMUIO_BASE__INST1_SEG1                     0
>+#define SMUIO_BASE__INST1_SEG2                     0
>+#define SMUIO_BASE__INST1_SEG3                     0
>+#define SMUIO_BASE__INST1_SEG4                     0
>+
>+#define SMUIO_BASE__INST2_SEG0                     0
>+#define SMUIO_BASE__INST2_SEG1                     0
>+#define SMUIO_BASE__INST2_SEG2                     0
>+#define SMUIO_BASE__INST2_SEG3                     0
>+#define SMUIO_BASE__INST2_SEG4                     0
>+
>+#define SMUIO_BASE__INST3_SEG0                     0
>+#define SMUIO_BASE__INST3_SEG1                     0
>+#define SMUIO_BASE__INST3_SEG2                     0
>+#define SMUIO_BASE__INST3_SEG3                     0
>+#define SMUIO_BASE__INST3_SEG4                     0
>+
>+#define SMUIO_BASE__INST4_SEG0                     0
>+#define SMUIO_BASE__INST4_SEG1                     0
>+#define SMUIO_BASE__INST4_SEG2                     0
>+#define SMUIO_BASE__INST4_SEG3                     0
>+#define SMUIO_BASE__INST4_SEG4                     0
>+
>+#define SMUIO_BASE__INST5_SEG0                     0
>+#define SMUIO_BASE__INST5_SEG1                     0
>+#define SMUIO_BASE__INST5_SEG2                     0
>+#define SMUIO_BASE__INST5_SEG3                     0
>+#define SMUIO_BASE__INST5_SEG4                     0
>+
>+#define SMUIO_BASE__INST6_SEG0                     0
>+#define SMUIO_BASE__INST6_SEG1                     0
>+#define SMUIO_BASE__INST6_SEG2                     0
>+#define SMUIO_BASE__INST6_SEG3                     0
>+#define SMUIO_BASE__INST6_SEG4                     0
>+
>+#define THM_BASE__INST0_SEG0                       0x00016600
>+#define THM_BASE__INST0_SEG1                       0x02400C00
>+#define THM_BASE__INST0_SEG2                       0
>+#define THM_BASE__INST0_SEG3                       0
>+#define THM_BASE__INST0_SEG4                       0
>+
>+#define THM_BASE__INST1_SEG0                       0
>+#define THM_BASE__INST1_SEG1                       0
>+#define THM_BASE__INST1_SEG2                       0
>+#define THM_BASE__INST1_SEG3                       0
>+#define THM_BASE__INST1_SEG4                       0
>+
>+#define THM_BASE__INST2_SEG0                       0
>+#define THM_BASE__INST2_SEG1                       0
>+#define THM_BASE__INST2_SEG2                       0
>+#define THM_BASE__INST2_SEG3                       0
>+#define THM_BASE__INST2_SEG4                       0
>+
>+#define THM_BASE__INST3_SEG0                       0
>+#define THM_BASE__INST3_SEG1                       0
>+#define THM_BASE__INST3_SEG2                       0
>+#define THM_BASE__INST3_SEG3                       0
>+#define THM_BASE__INST3_SEG4                       0
>+
>+#define THM_BASE__INST4_SEG0                       0
>+#define THM_BASE__INST4_SEG1                       0
>+#define THM_BASE__INST4_SEG2                       0
>+#define THM_BASE__INST4_SEG3                       0
>+#define THM_BASE__INST4_SEG4                       0
>+
>+#define THM_BASE__INST5_SEG0                       0
>+#define THM_BASE__INST5_SEG1                       0
>+#define THM_BASE__INST5_SEG2                       0
>+#define THM_BASE__INST5_SEG3                       0
>+#define THM_BASE__INST5_SEG4                       0
>+
>+#define THM_BASE__INST6_SEG0                       0
>+#define THM_BASE__INST6_SEG1                       0
>+#define THM_BASE__INST6_SEG2                       0
>+#define THM_BASE__INST6_SEG3                       0
>+#define THM_BASE__INST6_SEG4                       0
>+
>+#define UMC_BASE__INST0_SEG0                       0x00014000
>+#define UMC_BASE__INST0_SEG1                       0x02425800
>+#define UMC_BASE__INST0_SEG2                       0
>+#define UMC_BASE__INST0_SEG3                       0
>+#define UMC_BASE__INST0_SEG4                       0
>+
>+#define UMC_BASE__INST1_SEG0                       0x00054000
>+#define UMC_BASE__INST1_SEG1                       0x02425C00
>+#define UMC_BASE__INST1_SEG2                       0
>+#define UMC_BASE__INST1_SEG3                       0
>+#define UMC_BASE__INST1_SEG4                       0
>+
>+#define UMC_BASE__INST2_SEG0                       0x00094000
>+#define UMC_BASE__INST2_SEG1                       0x02426000
>+#define UMC_BASE__INST2_SEG2                       0
>+#define UMC_BASE__INST2_SEG3                       0
>+#define UMC_BASE__INST2_SEG4                       0
>+
>+#define UMC_BASE__INST3_SEG0                       0x000D4000
>+#define UMC_BASE__INST3_SEG1                       0x02426400
>+#define UMC_BASE__INST3_SEG2                       0
>+#define UMC_BASE__INST3_SEG3                       0
>+#define UMC_BASE__INST3_SEG4                       0
>+
>+#define UMC_BASE__INST4_SEG0                       0
>+#define UMC_BASE__INST4_SEG1                       0
>+#define UMC_BASE__INST4_SEG2                       0
>+#define UMC_BASE__INST4_SEG3                       0
>+#define UMC_BASE__INST4_SEG4                       0
>+
>+#define UMC_BASE__INST5_SEG0                       0
>+#define UMC_BASE__INST5_SEG1                       0
>+#define UMC_BASE__INST5_SEG2                       0
>+#define UMC_BASE__INST5_SEG3                       0
>+#define UMC_BASE__INST5_SEG4                       0
>+
>+#define UMC_BASE__INST6_SEG0                       0
>+#define UMC_BASE__INST6_SEG1                       0
>+#define UMC_BASE__INST6_SEG2                       0
>+#define UMC_BASE__INST6_SEG3                       0
>+#define UMC_BASE__INST6_SEG4                       0
>+
>+#define USB0_BASE__INST0_SEG0                      0x0242A800
>+#define USB0_BASE__INST0_SEG1                      0x05B00000
>+#define USB0_BASE__INST0_SEG2                      0
>+#define USB0_BASE__INST0_SEG3                      0
>+#define USB0_BASE__INST0_SEG4                      0
>+
>+#define USB0_BASE__INST1_SEG0                      0
>+#define USB0_BASE__INST1_SEG1                      0
>+#define USB0_BASE__INST1_SEG2                      0
>+#define USB0_BASE__INST1_SEG3                      0
>+#define USB0_BASE__INST1_SEG4                      0
>+
>+#define USB0_BASE__INST2_SEG0                      0
>+#define USB0_BASE__INST2_SEG1                      0
>+#define USB0_BASE__INST2_SEG2                      0
>+#define USB0_BASE__INST2_SEG3                      0
>+#define USB0_BASE__INST2_SEG4                      0
>+
>+#define USB0_BASE__INST3_SEG0                      0
>+#define USB0_BASE__INST3_SEG1                      0
>+#define USB0_BASE__INST3_SEG2                      0
>+#define USB0_BASE__INST3_SEG3                      0
>+#define USB0_BASE__INST3_SEG4                      0
>+
>+#define USB0_BASE__INST4_SEG0                      0
>+#define USB0_BASE__INST4_SEG1                      0
>+#define USB0_BASE__INST4_SEG2                      0
>+#define USB0_BASE__INST4_SEG3                      0
>+#define USB0_BASE__INST4_SEG4                      0
>+
>+#define USB0_BASE__INST5_SEG0                      0
>+#define USB0_BASE__INST5_SEG1                      0
>+#define USB0_BASE__INST5_SEG2                      0
>+#define USB0_BASE__INST5_SEG3                      0
>+#define USB0_BASE__INST5_SEG4                      0
>+
>+#define USB0_BASE__INST6_SEG0                      0
>+#define USB0_BASE__INST6_SEG1                      0
>+#define USB0_BASE__INST6_SEG2                      0
>+#define USB0_BASE__INST6_SEG3                      0
>+#define USB0_BASE__INST6_SEG4                      0
>+
>+#define UVD0_BASE__INST0_SEG0                      0x00007800
>+#define UVD0_BASE__INST0_SEG1                      0x00007E00
>+#define UVD0_BASE__INST0_SEG2                      0x02403000
>+#define UVD0_BASE__INST0_SEG3                      0
>+#define UVD0_BASE__INST0_SEG4                      0
>+
>+#define UVD0_BASE__INST1_SEG0                      0
>+#define UVD0_BASE__INST1_SEG1                      0
>+#define UVD0_BASE__INST1_SEG2                      0
>+#define UVD0_BASE__INST1_SEG3                      0
>+#define UVD0_BASE__INST1_SEG4                      0
>+
>+#define UVD0_BASE__INST2_SEG0                      0
>+#define UVD0_BASE__INST2_SEG1                      0
>+#define UVD0_BASE__INST2_SEG2                      0
>+#define UVD0_BASE__INST2_SEG3                      0
>+#define UVD0_BASE__INST2_SEG4                      0
>+
>+#define UVD0_BASE__INST3_SEG0                      0
>+#define UVD0_BASE__INST3_SEG1                      0
>+#define UVD0_BASE__INST3_SEG2                      0
>+#define UVD0_BASE__INST3_SEG3                      0
>+#define UVD0_BASE__INST3_SEG4                      0
>+
>+#define UVD0_BASE__INST4_SEG0                      0
>+#define UVD0_BASE__INST4_SEG1                      0
>+#define UVD0_BASE__INST4_SEG2                      0
>+#define UVD0_BASE__INST4_SEG3                      0
>+#define UVD0_BASE__INST4_SEG4                      0
>+
>+#define UVD0_BASE__INST5_SEG0                      0
>+#define UVD0_BASE__INST5_SEG1                      0
>+#define UVD0_BASE__INST5_SEG2                      0
>+#define UVD0_BASE__INST5_SEG3                      0
>+#define UVD0_BASE__INST5_SEG4                      0
>+
>+#define UVD0_BASE__INST6_SEG0                      0
>+#define UVD0_BASE__INST6_SEG1                      0
>+#define UVD0_BASE__INST6_SEG2                      0
>+#define UVD0_BASE__INST6_SEG3                      0
>+#define UVD0_BASE__INST6_SEG4                      0
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/renoir_ip_offset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/renoir_ip_offset.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/renoir_ip_offset.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/renoir_ip_offset.h	2019-08-31 15:01:11.935736175 -0500
>@@ -0,0 +1,1364 @@
>+/*
>+ * Copyright (C) 2019  Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included
>+ * in all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
>+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+#ifndef _renoir_ip_offset_HEADER
>+#define _renoir_ip_offset_HEADER
>+
>+#define MAX_INSTANCE                                       7
>+#define MAX_SEGMENT                                        5
>+
>+
>+struct IP_BASE_INSTANCE
>+{
>+    unsigned int segment[MAX_SEGMENT];
>+};
>+
>+struct IP_BASE
>+{
>+    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
>+};
>+
>+
>+static const struct IP_BASE ACP_BASE ={ { { { 0x02403800, 0x00480000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0x02408C00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DBGU_IO0_BASE ={ { { { 0x000001E0, 0x0240B400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DIO_BASE ={ { { { 0x02404000, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DMU_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE DPCS_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0x02401400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE HDA_BASE ={ { { { 0x02404800, 0x004C0000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE IOHC0_BASE ={ { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE ISP_BASE ={ { { { 0x00018000, 0x0240B000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE L2IMU0_BASE ={ { { { 0x00007DC0, 0x02407000, 0x00900000, 0x04FC0000, 0x055C0000 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0x02408800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE MP1_BASE ={ { { { 0x00016200, 0x02400400, 0x00E80000, 0x00EC0000, 0x00F00000 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE NBIF0_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0x0240A000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE PCIE0_BASE ={ { { { 0x02411800, 0x04440000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0x02400C00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0x02425800, 0, 0, 0 } },
>+                                        { { 0x00054000, 0x02425C00, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE USB0_BASE ={ { { { 0x0242A800, 0x05B00000, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+static const struct IP_BASE UVD0_BASE ={ { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } },
>+                                        { { 0, 0, 0, 0, 0 } } } };
>+
>+
>+#define ACP_BASE__INST0_SEG0                       0x02403800
>+#define ACP_BASE__INST0_SEG1                       0x00480000
>+#define ACP_BASE__INST0_SEG2                       0
>+#define ACP_BASE__INST0_SEG3                       0
>+#define ACP_BASE__INST0_SEG4                       0
>+
>+#define ACP_BASE__INST1_SEG0                       0
>+#define ACP_BASE__INST1_SEG1                       0
>+#define ACP_BASE__INST1_SEG2                       0
>+#define ACP_BASE__INST1_SEG3                       0
>+#define ACP_BASE__INST1_SEG4                       0
>+
>+#define ACP_BASE__INST2_SEG0                       0
>+#define ACP_BASE__INST2_SEG1                       0
>+#define ACP_BASE__INST2_SEG2                       0
>+#define ACP_BASE__INST2_SEG3                       0
>+#define ACP_BASE__INST2_SEG4                       0
>+
>+#define ACP_BASE__INST3_SEG0                       0
>+#define ACP_BASE__INST3_SEG1                       0
>+#define ACP_BASE__INST3_SEG2                       0
>+#define ACP_BASE__INST3_SEG3                       0
>+#define ACP_BASE__INST3_SEG4                       0
>+
>+#define ACP_BASE__INST4_SEG0                       0
>+#define ACP_BASE__INST4_SEG1                       0
>+#define ACP_BASE__INST4_SEG2                       0
>+#define ACP_BASE__INST4_SEG3                       0
>+#define ACP_BASE__INST4_SEG4                       0
>+
>+#define ACP_BASE__INST5_SEG0                       0
>+#define ACP_BASE__INST5_SEG1                       0
>+#define ACP_BASE__INST5_SEG2                       0
>+#define ACP_BASE__INST5_SEG3                       0
>+#define ACP_BASE__INST5_SEG4                       0
>+
>+#define ACP_BASE__INST6_SEG0                       0
>+#define ACP_BASE__INST6_SEG1                       0
>+#define ACP_BASE__INST6_SEG2                       0
>+#define ACP_BASE__INST6_SEG3                       0
>+#define ACP_BASE__INST6_SEG4                       0
>+
>+#define ATHUB_BASE__INST0_SEG0                     0x00000C20
>+#define ATHUB_BASE__INST0_SEG1                     0x02408C00
>+#define ATHUB_BASE__INST0_SEG2                     0
>+#define ATHUB_BASE__INST0_SEG3                     0
>+#define ATHUB_BASE__INST0_SEG4                     0
>+
>+#define ATHUB_BASE__INST1_SEG0                     0
>+#define ATHUB_BASE__INST1_SEG1                     0
>+#define ATHUB_BASE__INST1_SEG2                     0
>+#define ATHUB_BASE__INST1_SEG3                     0
>+#define ATHUB_BASE__INST1_SEG4                     0
>+
>+#define ATHUB_BASE__INST2_SEG0                     0
>+#define ATHUB_BASE__INST2_SEG1                     0
>+#define ATHUB_BASE__INST2_SEG2                     0
>+#define ATHUB_BASE__INST2_SEG3                     0
>+#define ATHUB_BASE__INST2_SEG4                     0
>+
>+#define ATHUB_BASE__INST3_SEG0                     0
>+#define ATHUB_BASE__INST3_SEG1                     0
>+#define ATHUB_BASE__INST3_SEG2                     0
>+#define ATHUB_BASE__INST3_SEG3                     0
>+#define ATHUB_BASE__INST3_SEG4                     0
>+
>+#define ATHUB_BASE__INST4_SEG0                     0
>+#define ATHUB_BASE__INST4_SEG1                     0
>+#define ATHUB_BASE__INST4_SEG2                     0
>+#define ATHUB_BASE__INST4_SEG3                     0
>+#define ATHUB_BASE__INST4_SEG4                     0
>+
>+#define ATHUB_BASE__INST5_SEG0                     0
>+#define ATHUB_BASE__INST5_SEG1                     0
>+#define ATHUB_BASE__INST5_SEG2                     0
>+#define ATHUB_BASE__INST5_SEG3                     0
>+#define ATHUB_BASE__INST5_SEG4                     0
>+
>+#define ATHUB_BASE__INST6_SEG0                     0
>+#define ATHUB_BASE__INST6_SEG1                     0
>+#define ATHUB_BASE__INST6_SEG2                     0
>+#define ATHUB_BASE__INST6_SEG3                     0
>+#define ATHUB_BASE__INST6_SEG4                     0
>+
>+#define CLK_BASE__INST0_SEG0                       0x00016C00
>+#define CLK_BASE__INST0_SEG1                       0x00016E00
>+#define CLK_BASE__INST0_SEG2                       0x00017000
>+#define CLK_BASE__INST0_SEG3                       0x00017E00
>+#define CLK_BASE__INST0_SEG4                       0
>+
>+#define CLK_BASE__INST1_SEG0                       0
>+#define CLK_BASE__INST1_SEG1                       0
>+#define CLK_BASE__INST1_SEG2                       0
>+#define CLK_BASE__INST1_SEG3                       0
>+#define CLK_BASE__INST1_SEG4                       0
>+
>+#define CLK_BASE__INST2_SEG0                       0
>+#define CLK_BASE__INST2_SEG1                       0
>+#define CLK_BASE__INST2_SEG2                       0
>+#define CLK_BASE__INST2_SEG3                       0
>+#define CLK_BASE__INST2_SEG4                       0
>+
>+#define CLK_BASE__INST3_SEG0                       0
>+#define CLK_BASE__INST3_SEG1                       0
>+#define CLK_BASE__INST3_SEG2                       0
>+#define CLK_BASE__INST3_SEG3                       0
>+#define CLK_BASE__INST3_SEG4                       0
>+
>+#define CLK_BASE__INST4_SEG0                       0
>+#define CLK_BASE__INST4_SEG1                       0
>+#define CLK_BASE__INST4_SEG2                       0
>+#define CLK_BASE__INST4_SEG3                       0
>+#define CLK_BASE__INST4_SEG4                       0
>+
>+#define CLK_BASE__INST5_SEG0                       0
>+#define CLK_BASE__INST5_SEG1                       0
>+#define CLK_BASE__INST5_SEG2                       0
>+#define CLK_BASE__INST5_SEG3                       0
>+#define CLK_BASE__INST5_SEG4                       0
>+
>+#define CLK_BASE__INST6_SEG0                       0
>+#define CLK_BASE__INST6_SEG1                       0
>+#define CLK_BASE__INST6_SEG2                       0
>+#define CLK_BASE__INST6_SEG3                       0
>+#define CLK_BASE__INST6_SEG4                       0
>+
>+#define DBGU_IO0_BASE__INST0_SEG0                  0x000001E0
>+#define DBGU_IO0_BASE__INST0_SEG1                  0x0240B400
>+#define DBGU_IO0_BASE__INST0_SEG2                  0
>+#define DBGU_IO0_BASE__INST0_SEG3                  0
>+#define DBGU_IO0_BASE__INST0_SEG4                  0
>+
>+#define DBGU_IO0_BASE__INST1_SEG0                  0
>+#define DBGU_IO0_BASE__INST1_SEG1                  0
>+#define DBGU_IO0_BASE__INST1_SEG2                  0
>+#define DBGU_IO0_BASE__INST1_SEG3                  0
>+#define DBGU_IO0_BASE__INST1_SEG4                  0
>+
>+#define DBGU_IO0_BASE__INST2_SEG0                  0
>+#define DBGU_IO0_BASE__INST2_SEG1                  0
>+#define DBGU_IO0_BASE__INST2_SEG2                  0
>+#define DBGU_IO0_BASE__INST2_SEG3                  0
>+#define DBGU_IO0_BASE__INST2_SEG4                  0
>+
>+#define DBGU_IO0_BASE__INST3_SEG0                  0
>+#define DBGU_IO0_BASE__INST3_SEG1                  0
>+#define DBGU_IO0_BASE__INST3_SEG2                  0
>+#define DBGU_IO0_BASE__INST3_SEG3                  0
>+#define DBGU_IO0_BASE__INST3_SEG4                  0
>+
>+#define DBGU_IO0_BASE__INST4_SEG0                  0
>+#define DBGU_IO0_BASE__INST4_SEG1                  0
>+#define DBGU_IO0_BASE__INST4_SEG2                  0
>+#define DBGU_IO0_BASE__INST4_SEG3                  0
>+#define DBGU_IO0_BASE__INST4_SEG4                  0
>+
>+#define DBGU_IO0_BASE__INST5_SEG0                  0
>+#define DBGU_IO0_BASE__INST5_SEG1                  0
>+#define DBGU_IO0_BASE__INST5_SEG2                  0
>+#define DBGU_IO0_BASE__INST5_SEG3                  0
>+#define DBGU_IO0_BASE__INST5_SEG4                  0
>+
>+#define DBGU_IO0_BASE__INST6_SEG0                  0
>+#define DBGU_IO0_BASE__INST6_SEG1                  0
>+#define DBGU_IO0_BASE__INST6_SEG2                  0
>+#define DBGU_IO0_BASE__INST6_SEG3                  0
>+#define DBGU_IO0_BASE__INST6_SEG4                  0
>+
>+#define DF_BASE__INST0_SEG0                        0x00007000
>+#define DF_BASE__INST0_SEG1                        0x0240B800
>+#define DF_BASE__INST0_SEG2                        0
>+#define DF_BASE__INST0_SEG3                        0
>+#define DF_BASE__INST0_SEG4                        0
>+
>+#define DF_BASE__INST1_SEG0                        0
>+#define DF_BASE__INST1_SEG1                        0
>+#define DF_BASE__INST1_SEG2                        0
>+#define DF_BASE__INST1_SEG3                        0
>+#define DF_BASE__INST1_SEG4                        0
>+
>+#define DF_BASE__INST2_SEG0                        0
>+#define DF_BASE__INST2_SEG1                        0
>+#define DF_BASE__INST2_SEG2                        0
>+#define DF_BASE__INST2_SEG3                        0
>+#define DF_BASE__INST2_SEG4                        0
>+
>+#define DF_BASE__INST3_SEG0                        0
>+#define DF_BASE__INST3_SEG1                        0
>+#define DF_BASE__INST3_SEG2                        0
>+#define DF_BASE__INST3_SEG3                        0
>+#define DF_BASE__INST3_SEG4                        0
>+
>+#define DF_BASE__INST4_SEG0                        0
>+#define DF_BASE__INST4_SEG1                        0
>+#define DF_BASE__INST4_SEG2                        0
>+#define DF_BASE__INST4_SEG3                        0
>+#define DF_BASE__INST4_SEG4                        0
>+
>+#define DF_BASE__INST5_SEG0                        0
>+#define DF_BASE__INST5_SEG1                        0
>+#define DF_BASE__INST5_SEG2                        0
>+#define DF_BASE__INST5_SEG3                        0
>+#define DF_BASE__INST5_SEG4                        0
>+
>+#define DF_BASE__INST6_SEG0                        0
>+#define DF_BASE__INST6_SEG1                        0
>+#define DF_BASE__INST6_SEG2                        0
>+#define DF_BASE__INST6_SEG3                        0
>+#define DF_BASE__INST6_SEG4                        0
>+
>+#define DIO_BASE__INST0_SEG0                       0x02404000
>+#define DIO_BASE__INST0_SEG1                       0
>+#define DIO_BASE__INST0_SEG2                       0
>+#define DIO_BASE__INST0_SEG3                       0
>+#define DIO_BASE__INST0_SEG4                       0
>+
>+#define DIO_BASE__INST1_SEG0                       0
>+#define DIO_BASE__INST1_SEG1                       0
>+#define DIO_BASE__INST1_SEG2                       0
>+#define DIO_BASE__INST1_SEG3                       0
>+#define DIO_BASE__INST1_SEG4                       0
>+
>+#define DIO_BASE__INST2_SEG0                       0
>+#define DIO_BASE__INST2_SEG1                       0
>+#define DIO_BASE__INST2_SEG2                       0
>+#define DIO_BASE__INST2_SEG3                       0
>+#define DIO_BASE__INST2_SEG4                       0
>+
>+#define DIO_BASE__INST3_SEG0                       0
>+#define DIO_BASE__INST3_SEG1                       0
>+#define DIO_BASE__INST3_SEG2                       0
>+#define DIO_BASE__INST3_SEG3                       0
>+#define DIO_BASE__INST3_SEG4                       0
>+
>+#define DIO_BASE__INST4_SEG0                       0
>+#define DIO_BASE__INST4_SEG1                       0
>+#define DIO_BASE__INST4_SEG2                       0
>+#define DIO_BASE__INST4_SEG3                       0
>+#define DIO_BASE__INST4_SEG4                       0
>+
>+#define DIO_BASE__INST5_SEG0                       0
>+#define DIO_BASE__INST5_SEG1                       0
>+#define DIO_BASE__INST5_SEG2                       0
>+#define DIO_BASE__INST5_SEG3                       0
>+#define DIO_BASE__INST5_SEG4                       0
>+
>+#define DIO_BASE__INST6_SEG0                       0
>+#define DIO_BASE__INST6_SEG1                       0
>+#define DIO_BASE__INST6_SEG2                       0
>+#define DIO_BASE__INST6_SEG3                       0
>+#define DIO_BASE__INST6_SEG4                       0
>+
>+#define DMU_BASE__INST0_SEG0                       0x00000012
>+#define DMU_BASE__INST0_SEG1                       0x000000C0
>+#define DMU_BASE__INST0_SEG2                       0x000034C0
>+#define DMU_BASE__INST0_SEG3                       0x00009000
>+#define DMU_BASE__INST0_SEG4                       0x02403C00
>+
>+#define DMU_BASE__INST1_SEG0                       0
>+#define DMU_BASE__INST1_SEG1                       0
>+#define DMU_BASE__INST1_SEG2                       0
>+#define DMU_BASE__INST1_SEG3                       0
>+#define DMU_BASE__INST1_SEG4                       0
>+
>+#define DMU_BASE__INST2_SEG0                       0
>+#define DMU_BASE__INST2_SEG1                       0
>+#define DMU_BASE__INST2_SEG2                       0
>+#define DMU_BASE__INST2_SEG3                       0
>+#define DMU_BASE__INST2_SEG4                       0
>+
>+#define DMU_BASE__INST3_SEG0                       0
>+#define DMU_BASE__INST3_SEG1                       0
>+#define DMU_BASE__INST3_SEG2                       0
>+#define DMU_BASE__INST3_SEG3                       0
>+#define DMU_BASE__INST3_SEG4                       0
>+
>+#define DMU_BASE__INST4_SEG0                       0
>+#define DMU_BASE__INST4_SEG1                       0
>+#define DMU_BASE__INST4_SEG2                       0
>+#define DMU_BASE__INST4_SEG3                       0
>+#define DMU_BASE__INST4_SEG4                       0
>+
>+#define DMU_BASE__INST5_SEG0                       0
>+#define DMU_BASE__INST5_SEG1                       0
>+#define DMU_BASE__INST5_SEG2                       0
>+#define DMU_BASE__INST5_SEG3                       0
>+#define DMU_BASE__INST5_SEG4                       0
>+
>+#define DMU_BASE__INST6_SEG0                       0
>+#define DMU_BASE__INST6_SEG1                       0
>+#define DMU_BASE__INST6_SEG2                       0
>+#define DMU_BASE__INST6_SEG3                       0
>+#define DMU_BASE__INST6_SEG4                       0
>+
>+#define DPCS_BASE__INST0_SEG0                      0x00000012
>+#define DPCS_BASE__INST0_SEG1                      0x000000C0
>+#define DPCS_BASE__INST0_SEG2                      0x000034C0
>+#define DPCS_BASE__INST0_SEG3                      0x00009000
>+#define DPCS_BASE__INST0_SEG4                      0x02403C00
>+
>+#define DPCS_BASE__INST1_SEG0                      0
>+#define DPCS_BASE__INST1_SEG1                      0
>+#define DPCS_BASE__INST1_SEG2                      0
>+#define DPCS_BASE__INST1_SEG3                      0
>+#define DPCS_BASE__INST1_SEG4                      0
>+
>+#define DPCS_BASE__INST2_SEG0                      0
>+#define DPCS_BASE__INST2_SEG1                      0
>+#define DPCS_BASE__INST2_SEG2                      0
>+#define DPCS_BASE__INST2_SEG3                      0
>+#define DPCS_BASE__INST2_SEG4                      0
>+
>+#define DPCS_BASE__INST3_SEG0                      0
>+#define DPCS_BASE__INST3_SEG1                      0
>+#define DPCS_BASE__INST3_SEG2                      0
>+#define DPCS_BASE__INST3_SEG3                      0
>+#define DPCS_BASE__INST3_SEG4                      0
>+
>+#define DPCS_BASE__INST4_SEG0                      0
>+#define DPCS_BASE__INST4_SEG1                      0
>+#define DPCS_BASE__INST4_SEG2                      0
>+#define DPCS_BASE__INST4_SEG3                      0
>+#define DPCS_BASE__INST4_SEG4                      0
>+
>+#define DPCS_BASE__INST5_SEG0                      0
>+#define DPCS_BASE__INST5_SEG1                      0
>+#define DPCS_BASE__INST5_SEG2                      0
>+#define DPCS_BASE__INST5_SEG3                      0
>+#define DPCS_BASE__INST5_SEG4                      0
>+
>+#define DPCS_BASE__INST6_SEG0                      0
>+#define DPCS_BASE__INST6_SEG1                      0
>+#define DPCS_BASE__INST6_SEG2                      0
>+#define DPCS_BASE__INST6_SEG3                      0
>+#define DPCS_BASE__INST6_SEG4                      0
>+
>+#define FUSE_BASE__INST0_SEG0                      0x00017400
>+#define FUSE_BASE__INST0_SEG1                      0x02401400
>+#define FUSE_BASE__INST0_SEG2                      0
>+#define FUSE_BASE__INST0_SEG3                      0
>+#define FUSE_BASE__INST0_SEG4                      0
>+
>+#define FUSE_BASE__INST1_SEG0                      0
>+#define FUSE_BASE__INST1_SEG1                      0
>+#define FUSE_BASE__INST1_SEG2                      0
>+#define FUSE_BASE__INST1_SEG3                      0
>+#define FUSE_BASE__INST1_SEG4                      0
>+
>+#define FUSE_BASE__INST2_SEG0                      0
>+#define FUSE_BASE__INST2_SEG1                      0
>+#define FUSE_BASE__INST2_SEG2                      0
>+#define FUSE_BASE__INST2_SEG3                      0
>+#define FUSE_BASE__INST2_SEG4                      0
>+
>+#define FUSE_BASE__INST3_SEG0                      0
>+#define FUSE_BASE__INST3_SEG1                      0
>+#define FUSE_BASE__INST3_SEG2                      0
>+#define FUSE_BASE__INST3_SEG3                      0
>+#define FUSE_BASE__INST3_SEG4                      0
>+
>+#define FUSE_BASE__INST4_SEG0                      0
>+#define FUSE_BASE__INST4_SEG1                      0
>+#define FUSE_BASE__INST4_SEG2                      0
>+#define FUSE_BASE__INST4_SEG3                      0
>+#define FUSE_BASE__INST4_SEG4                      0
>+
>+#define FUSE_BASE__INST5_SEG0                      0
>+#define FUSE_BASE__INST5_SEG1                      0
>+#define FUSE_BASE__INST5_SEG2                      0
>+#define FUSE_BASE__INST5_SEG3                      0
>+#define FUSE_BASE__INST5_SEG4                      0
>+
>+#define FUSE_BASE__INST6_SEG0                      0
>+#define FUSE_BASE__INST6_SEG1                      0
>+#define FUSE_BASE__INST6_SEG2                      0
>+#define FUSE_BASE__INST6_SEG3                      0
>+#define FUSE_BASE__INST6_SEG4                      0
>+
>+#define GC_BASE__INST0_SEG0                        0x00002000
>+#define GC_BASE__INST0_SEG1                        0x0000A000
>+#define GC_BASE__INST0_SEG2                        0x02402C00
>+#define GC_BASE__INST0_SEG3                        0
>+#define GC_BASE__INST0_SEG4                        0
>+
>+#define GC_BASE__INST1_SEG0                        0
>+#define GC_BASE__INST1_SEG1                        0
>+#define GC_BASE__INST1_SEG2                        0
>+#define GC_BASE__INST1_SEG3                        0
>+#define GC_BASE__INST1_SEG4                        0
>+
>+#define GC_BASE__INST2_SEG0                        0
>+#define GC_BASE__INST2_SEG1                        0
>+#define GC_BASE__INST2_SEG2                        0
>+#define GC_BASE__INST2_SEG3                        0
>+#define GC_BASE__INST2_SEG4                        0
>+
>+#define GC_BASE__INST3_SEG0                        0
>+#define GC_BASE__INST3_SEG1                        0
>+#define GC_BASE__INST3_SEG2                        0
>+#define GC_BASE__INST3_SEG3                        0
>+#define GC_BASE__INST3_SEG4                        0
>+
>+#define GC_BASE__INST4_SEG0                        0
>+#define GC_BASE__INST4_SEG1                        0
>+#define GC_BASE__INST4_SEG2                        0
>+#define GC_BASE__INST4_SEG3                        0
>+#define GC_BASE__INST4_SEG4                        0
>+
>+#define GC_BASE__INST5_SEG0                        0
>+#define GC_BASE__INST5_SEG1                        0
>+#define GC_BASE__INST5_SEG2                        0
>+#define GC_BASE__INST5_SEG3                        0
>+#define GC_BASE__INST5_SEG4                        0
>+
>+#define GC_BASE__INST6_SEG0                        0
>+#define GC_BASE__INST6_SEG1                        0
>+#define GC_BASE__INST6_SEG2                        0
>+#define GC_BASE__INST6_SEG3                        0
>+#define GC_BASE__INST6_SEG4                        0
>+
>+#define HDA_BASE__INST0_SEG0                       0x02404800
>+#define HDA_BASE__INST0_SEG1                       0x004C0000
>+#define HDA_BASE__INST0_SEG2                       0
>+#define HDA_BASE__INST0_SEG3                       0
>+#define HDA_BASE__INST0_SEG4                       0
>+
>+#define HDA_BASE__INST1_SEG0                       0
>+#define HDA_BASE__INST1_SEG1                       0
>+#define HDA_BASE__INST1_SEG2                       0
>+#define HDA_BASE__INST1_SEG3                       0
>+#define HDA_BASE__INST1_SEG4                       0
>+
>+#define HDA_BASE__INST2_SEG0                       0
>+#define HDA_BASE__INST2_SEG1                       0
>+#define HDA_BASE__INST2_SEG2                       0
>+#define HDA_BASE__INST2_SEG3                       0
>+#define HDA_BASE__INST2_SEG4                       0
>+
>+#define HDA_BASE__INST3_SEG0                       0
>+#define HDA_BASE__INST3_SEG1                       0
>+#define HDA_BASE__INST3_SEG2                       0
>+#define HDA_BASE__INST3_SEG3                       0
>+#define HDA_BASE__INST3_SEG4                       0
>+
>+#define HDA_BASE__INST4_SEG0                       0
>+#define HDA_BASE__INST4_SEG1                       0
>+#define HDA_BASE__INST4_SEG2                       0
>+#define HDA_BASE__INST4_SEG3                       0
>+#define HDA_BASE__INST4_SEG4                       0
>+
>+#define HDA_BASE__INST5_SEG0                       0
>+#define HDA_BASE__INST5_SEG1                       0
>+#define HDA_BASE__INST5_SEG2                       0
>+#define HDA_BASE__INST5_SEG3                       0
>+#define HDA_BASE__INST5_SEG4                       0
>+
>+#define HDA_BASE__INST6_SEG0                       0
>+#define HDA_BASE__INST6_SEG1                       0
>+#define HDA_BASE__INST6_SEG2                       0
>+#define HDA_BASE__INST6_SEG3                       0
>+#define HDA_BASE__INST6_SEG4                       0
>+
>+#define HDP_BASE__INST0_SEG0                       0x00000F20
>+#define HDP_BASE__INST0_SEG1                       0x0240A400
>+#define HDP_BASE__INST0_SEG2                       0
>+#define HDP_BASE__INST0_SEG3                       0
>+#define HDP_BASE__INST0_SEG4                       0
>+
>+#define HDP_BASE__INST1_SEG0                       0
>+#define HDP_BASE__INST1_SEG1                       0
>+#define HDP_BASE__INST1_SEG2                       0
>+#define HDP_BASE__INST1_SEG3                       0
>+#define HDP_BASE__INST1_SEG4                       0
>+
>+#define HDP_BASE__INST2_SEG0                       0
>+#define HDP_BASE__INST2_SEG1                       0
>+#define HDP_BASE__INST2_SEG2                       0
>+#define HDP_BASE__INST2_SEG3                       0
>+#define HDP_BASE__INST2_SEG4                       0
>+
>+#define HDP_BASE__INST3_SEG0                       0
>+#define HDP_BASE__INST3_SEG1                       0
>+#define HDP_BASE__INST3_SEG2                       0
>+#define HDP_BASE__INST3_SEG3                       0
>+#define HDP_BASE__INST3_SEG4                       0
>+
>+#define HDP_BASE__INST4_SEG0                       0
>+#define HDP_BASE__INST4_SEG1                       0
>+#define HDP_BASE__INST4_SEG2                       0
>+#define HDP_BASE__INST4_SEG3                       0
>+#define HDP_BASE__INST4_SEG4                       0
>+
>+#define HDP_BASE__INST5_SEG0                       0
>+#define HDP_BASE__INST5_SEG1                       0
>+#define HDP_BASE__INST5_SEG2                       0
>+#define HDP_BASE__INST5_SEG3                       0
>+#define HDP_BASE__INST5_SEG4                       0
>+
>+#define HDP_BASE__INST6_SEG0                       0
>+#define HDP_BASE__INST6_SEG1                       0
>+#define HDP_BASE__INST6_SEG2                       0
>+#define HDP_BASE__INST6_SEG3                       0
>+#define HDP_BASE__INST6_SEG4                       0
>+
>+#define IOHC0_BASE__INST0_SEG0                     0x00010000
>+#define IOHC0_BASE__INST0_SEG1                     0x02406000
>+#define IOHC0_BASE__INST0_SEG2                     0x04EC0000
>+#define IOHC0_BASE__INST0_SEG3                     0
>+#define IOHC0_BASE__INST0_SEG4                     0
>+
>+#define IOHC0_BASE__INST1_SEG0                     0
>+#define IOHC0_BASE__INST1_SEG1                     0
>+#define IOHC0_BASE__INST1_SEG2                     0
>+#define IOHC0_BASE__INST1_SEG3                     0
>+#define IOHC0_BASE__INST1_SEG4                     0
>+
>+#define IOHC0_BASE__INST2_SEG0                     0
>+#define IOHC0_BASE__INST2_SEG1                     0
>+#define IOHC0_BASE__INST2_SEG2                     0
>+#define IOHC0_BASE__INST2_SEG3                     0
>+#define IOHC0_BASE__INST2_SEG4                     0
>+
>+#define IOHC0_BASE__INST3_SEG0                     0
>+#define IOHC0_BASE__INST3_SEG1                     0
>+#define IOHC0_BASE__INST3_SEG2                     0
>+#define IOHC0_BASE__INST3_SEG3                     0
>+#define IOHC0_BASE__INST3_SEG4                     0
>+
>+#define IOHC0_BASE__INST4_SEG0                     0
>+#define IOHC0_BASE__INST4_SEG1                     0
>+#define IOHC0_BASE__INST4_SEG2                     0
>+#define IOHC0_BASE__INST4_SEG3                     0
>+#define IOHC0_BASE__INST4_SEG4                     0
>+
>+#define IOHC0_BASE__INST5_SEG0                     0
>+#define IOHC0_BASE__INST5_SEG1                     0
>+#define IOHC0_BASE__INST5_SEG2                     0
>+#define IOHC0_BASE__INST5_SEG3                     0
>+#define IOHC0_BASE__INST5_SEG4                     0
>+
>+#define IOHC0_BASE__INST6_SEG0                     0
>+#define IOHC0_BASE__INST6_SEG1                     0
>+#define IOHC0_BASE__INST6_SEG2                     0
>+#define IOHC0_BASE__INST6_SEG3                     0
>+#define IOHC0_BASE__INST6_SEG4                     0
>+
>+#define ISP_BASE__INST0_SEG0                       0x00018000
>+#define ISP_BASE__INST0_SEG1                       0x0240B000
>+#define ISP_BASE__INST0_SEG2                       0
>+#define ISP_BASE__INST0_SEG3                       0
>+#define ISP_BASE__INST0_SEG4                       0
>+
>+#define ISP_BASE__INST1_SEG0                       0
>+#define ISP_BASE__INST1_SEG1                       0
>+#define ISP_BASE__INST1_SEG2                       0
>+#define ISP_BASE__INST1_SEG3                       0
>+#define ISP_BASE__INST1_SEG4                       0
>+
>+#define ISP_BASE__INST2_SEG0                       0
>+#define ISP_BASE__INST2_SEG1                       0
>+#define ISP_BASE__INST2_SEG2                       0
>+#define ISP_BASE__INST2_SEG3                       0
>+#define ISP_BASE__INST2_SEG4                       0
>+
>+#define ISP_BASE__INST3_SEG0                       0
>+#define ISP_BASE__INST3_SEG1                       0
>+#define ISP_BASE__INST3_SEG2                       0
>+#define ISP_BASE__INST3_SEG3                       0
>+#define ISP_BASE__INST3_SEG4                       0
>+
>+#define ISP_BASE__INST4_SEG0                       0
>+#define ISP_BASE__INST4_SEG1                       0
>+#define ISP_BASE__INST4_SEG2                       0
>+#define ISP_BASE__INST4_SEG3                       0
>+#define ISP_BASE__INST4_SEG4                       0
>+
>+#define ISP_BASE__INST5_SEG0                       0
>+#define ISP_BASE__INST5_SEG1                       0
>+#define ISP_BASE__INST5_SEG2                       0
>+#define ISP_BASE__INST5_SEG3                       0
>+#define ISP_BASE__INST5_SEG4                       0
>+
>+#define ISP_BASE__INST6_SEG0                       0
>+#define ISP_BASE__INST6_SEG1                       0
>+#define ISP_BASE__INST6_SEG2                       0
>+#define ISP_BASE__INST6_SEG3                       0
>+#define ISP_BASE__INST6_SEG4                       0
>+
>+#define L2IMU0_BASE__INST0_SEG0                    0x00007DC0
>+#define L2IMU0_BASE__INST0_SEG1                    0x02407000
>+#define L2IMU0_BASE__INST0_SEG2                    0x00900000
>+#define L2IMU0_BASE__INST0_SEG3                    0x04FC0000
>+#define L2IMU0_BASE__INST0_SEG4                    0x055C0000
>+
>+#define L2IMU0_BASE__INST1_SEG0                    0
>+#define L2IMU0_BASE__INST1_SEG1                    0
>+#define L2IMU0_BASE__INST1_SEG2                    0
>+#define L2IMU0_BASE__INST1_SEG3                    0
>+#define L2IMU0_BASE__INST1_SEG4                    0
>+
>+#define L2IMU0_BASE__INST2_SEG0                    0
>+#define L2IMU0_BASE__INST2_SEG1                    0
>+#define L2IMU0_BASE__INST2_SEG2                    0
>+#define L2IMU0_BASE__INST2_SEG3                    0
>+#define L2IMU0_BASE__INST2_SEG4                    0
>+
>+#define L2IMU0_BASE__INST3_SEG0                    0
>+#define L2IMU0_BASE__INST3_SEG1                    0
>+#define L2IMU0_BASE__INST3_SEG2                    0
>+#define L2IMU0_BASE__INST3_SEG3                    0
>+#define L2IMU0_BASE__INST3_SEG4                    0
>+
>+#define L2IMU0_BASE__INST4_SEG0                    0
>+#define L2IMU0_BASE__INST4_SEG1                    0
>+#define L2IMU0_BASE__INST4_SEG2                    0
>+#define L2IMU0_BASE__INST4_SEG3                    0
>+#define L2IMU0_BASE__INST4_SEG4                    0
>+
>+#define L2IMU0_BASE__INST5_SEG0                    0
>+#define L2IMU0_BASE__INST5_SEG1                    0
>+#define L2IMU0_BASE__INST5_SEG2                    0
>+#define L2IMU0_BASE__INST5_SEG3                    0
>+#define L2IMU0_BASE__INST5_SEG4                    0
>+
>+#define L2IMU0_BASE__INST6_SEG0                    0
>+#define L2IMU0_BASE__INST6_SEG1                    0
>+#define L2IMU0_BASE__INST6_SEG2                    0
>+#define L2IMU0_BASE__INST6_SEG3                    0
>+#define L2IMU0_BASE__INST6_SEG4                    0
>+
>+#define MMHUB_BASE__INST0_SEG0                     0x0001A000
>+#define MMHUB_BASE__INST0_SEG1                     0x02408800
>+#define MMHUB_BASE__INST0_SEG2                     0
>+#define MMHUB_BASE__INST0_SEG3                     0
>+#define MMHUB_BASE__INST0_SEG4                     0
>+
>+#define MMHUB_BASE__INST1_SEG0                     0
>+#define MMHUB_BASE__INST1_SEG1                     0
>+#define MMHUB_BASE__INST1_SEG2                     0
>+#define MMHUB_BASE__INST1_SEG3                     0
>+#define MMHUB_BASE__INST1_SEG4                     0
>+
>+#define MMHUB_BASE__INST2_SEG0                     0
>+#define MMHUB_BASE__INST2_SEG1                     0
>+#define MMHUB_BASE__INST2_SEG2                     0
>+#define MMHUB_BASE__INST2_SEG3                     0
>+#define MMHUB_BASE__INST2_SEG4                     0
>+
>+#define MMHUB_BASE__INST3_SEG0                     0
>+#define MMHUB_BASE__INST3_SEG1                     0
>+#define MMHUB_BASE__INST3_SEG2                     0
>+#define MMHUB_BASE__INST3_SEG3                     0
>+#define MMHUB_BASE__INST3_SEG4                     0
>+
>+#define MMHUB_BASE__INST4_SEG0                     0
>+#define MMHUB_BASE__INST4_SEG1                     0
>+#define MMHUB_BASE__INST4_SEG2                     0
>+#define MMHUB_BASE__INST4_SEG3                     0
>+#define MMHUB_BASE__INST4_SEG4                     0
>+
>+#define MMHUB_BASE__INST5_SEG0                     0
>+#define MMHUB_BASE__INST5_SEG1                     0
>+#define MMHUB_BASE__INST5_SEG2                     0
>+#define MMHUB_BASE__INST5_SEG3                     0
>+#define MMHUB_BASE__INST5_SEG4                     0
>+
>+#define MMHUB_BASE__INST6_SEG0                     0
>+#define MMHUB_BASE__INST6_SEG1                     0
>+#define MMHUB_BASE__INST6_SEG2                     0
>+#define MMHUB_BASE__INST6_SEG3                     0
>+#define MMHUB_BASE__INST6_SEG4                     0
>+
>+#define MP0_BASE__INST0_SEG0                       0x00016000
>+#define MP0_BASE__INST0_SEG1                       0x0243FC00
>+#define MP0_BASE__INST0_SEG2                       0x00DC0000
>+#define MP0_BASE__INST0_SEG3                       0x00E00000
>+#define MP0_BASE__INST0_SEG4                       0x00E40000
>+
>+#define MP0_BASE__INST1_SEG0                       0
>+#define MP0_BASE__INST1_SEG1                       0
>+#define MP0_BASE__INST1_SEG2                       0
>+#define MP0_BASE__INST1_SEG3                       0
>+#define MP0_BASE__INST1_SEG4                       0
>+
>+#define MP0_BASE__INST2_SEG0                       0
>+#define MP0_BASE__INST2_SEG1                       0
>+#define MP0_BASE__INST2_SEG2                       0
>+#define MP0_BASE__INST2_SEG3                       0
>+#define MP0_BASE__INST2_SEG4                       0
>+
>+#define MP0_BASE__INST3_SEG0                       0
>+#define MP0_BASE__INST3_SEG1                       0
>+#define MP0_BASE__INST3_SEG2                       0
>+#define MP0_BASE__INST3_SEG3                       0
>+#define MP0_BASE__INST3_SEG4                       0
>+
>+#define MP0_BASE__INST4_SEG0                       0
>+#define MP0_BASE__INST4_SEG1                       0
>+#define MP0_BASE__INST4_SEG2                       0
>+#define MP0_BASE__INST4_SEG3                       0
>+#define MP0_BASE__INST4_SEG4                       0
>+
>+#define MP0_BASE__INST5_SEG0                       0
>+#define MP0_BASE__INST5_SEG1                       0
>+#define MP0_BASE__INST5_SEG2                       0
>+#define MP0_BASE__INST5_SEG3                       0
>+#define MP0_BASE__INST5_SEG4                       0
>+
>+#define MP0_BASE__INST6_SEG0                       0
>+#define MP0_BASE__INST6_SEG1                       0
>+#define MP0_BASE__INST6_SEG2                       0
>+#define MP0_BASE__INST6_SEG3                       0
>+#define MP0_BASE__INST6_SEG4                       0
>+
>+#define MP1_BASE__INST0_SEG0                       0x00016200
>+#define MP1_BASE__INST0_SEG1                       0x02400400
>+#define MP1_BASE__INST0_SEG2                       0x00E80000
>+#define MP1_BASE__INST0_SEG3                       0x00EC0000
>+#define MP1_BASE__INST0_SEG4                       0x00F00000
>+
>+#define MP1_BASE__INST1_SEG0                       0
>+#define MP1_BASE__INST1_SEG1                       0
>+#define MP1_BASE__INST1_SEG2                       0
>+#define MP1_BASE__INST1_SEG3                       0
>+#define MP1_BASE__INST1_SEG4                       0
>+
>+#define MP1_BASE__INST2_SEG0                       0
>+#define MP1_BASE__INST2_SEG1                       0
>+#define MP1_BASE__INST2_SEG2                       0
>+#define MP1_BASE__INST2_SEG3                       0
>+#define MP1_BASE__INST2_SEG4                       0
>+
>+#define MP1_BASE__INST3_SEG0                       0
>+#define MP1_BASE__INST3_SEG1                       0
>+#define MP1_BASE__INST3_SEG2                       0
>+#define MP1_BASE__INST3_SEG3                       0
>+#define MP1_BASE__INST3_SEG4                       0
>+
>+#define MP1_BASE__INST4_SEG0                       0
>+#define MP1_BASE__INST4_SEG1                       0
>+#define MP1_BASE__INST4_SEG2                       0
>+#define MP1_BASE__INST4_SEG3                       0
>+#define MP1_BASE__INST4_SEG4                       0
>+
>+#define MP1_BASE__INST5_SEG0                       0
>+#define MP1_BASE__INST5_SEG1                       0
>+#define MP1_BASE__INST5_SEG2                       0
>+#define MP1_BASE__INST5_SEG3                       0
>+#define MP1_BASE__INST5_SEG4                       0
>+
>+#define MP1_BASE__INST6_SEG0                       0
>+#define MP1_BASE__INST6_SEG1                       0
>+#define MP1_BASE__INST6_SEG2                       0
>+#define MP1_BASE__INST6_SEG3                       0
>+#define MP1_BASE__INST6_SEG4                       0
>+
>+#define NBIF0_BASE__INST0_SEG0                     0x00000000
>+#define NBIF0_BASE__INST0_SEG1                     0x00000014
>+#define NBIF0_BASE__INST0_SEG2                     0x00000D20
>+#define NBIF0_BASE__INST0_SEG3                     0x00010400
>+#define NBIF0_BASE__INST0_SEG4                     0x0241B000
>+
>+#define NBIF0_BASE__INST1_SEG0                     0
>+#define NBIF0_BASE__INST1_SEG1                     0
>+#define NBIF0_BASE__INST1_SEG2                     0
>+#define NBIF0_BASE__INST1_SEG3                     0
>+#define NBIF0_BASE__INST1_SEG4                     0
>+
>+#define NBIF0_BASE__INST2_SEG0                     0
>+#define NBIF0_BASE__INST2_SEG1                     0
>+#define NBIF0_BASE__INST2_SEG2                     0
>+#define NBIF0_BASE__INST2_SEG3                     0
>+#define NBIF0_BASE__INST2_SEG4                     0
>+
>+#define NBIF0_BASE__INST3_SEG0                     0
>+#define NBIF0_BASE__INST3_SEG1                     0
>+#define NBIF0_BASE__INST3_SEG2                     0
>+#define NBIF0_BASE__INST3_SEG3                     0
>+#define NBIF0_BASE__INST3_SEG4                     0
>+
>+#define NBIF0_BASE__INST4_SEG0                     0
>+#define NBIF0_BASE__INST4_SEG1                     0
>+#define NBIF0_BASE__INST4_SEG2                     0
>+#define NBIF0_BASE__INST4_SEG3                     0
>+#define NBIF0_BASE__INST4_SEG4                     0
>+
>+#define NBIF0_BASE__INST5_SEG0                     0
>+#define NBIF0_BASE__INST5_SEG1                     0
>+#define NBIF0_BASE__INST5_SEG2                     0
>+#define NBIF0_BASE__INST5_SEG3                     0
>+#define NBIF0_BASE__INST5_SEG4                     0
>+
>+#define NBIF0_BASE__INST6_SEG0                     0
>+#define NBIF0_BASE__INST6_SEG1                     0
>+#define NBIF0_BASE__INST6_SEG2                     0
>+#define NBIF0_BASE__INST6_SEG3                     0
>+#define NBIF0_BASE__INST6_SEG4                     0
>+
>+#define OSSSYS_BASE__INST0_SEG0                    0x000010A0
>+#define OSSSYS_BASE__INST0_SEG1                    0x0240A000
>+#define OSSSYS_BASE__INST0_SEG2                    0
>+#define OSSSYS_BASE__INST0_SEG3                    0
>+#define OSSSYS_BASE__INST0_SEG4                    0
>+
>+#define OSSSYS_BASE__INST1_SEG0                    0
>+#define OSSSYS_BASE__INST1_SEG1                    0
>+#define OSSSYS_BASE__INST1_SEG2                    0
>+#define OSSSYS_BASE__INST1_SEG3                    0
>+#define OSSSYS_BASE__INST1_SEG4                    0
>+
>+#define OSSSYS_BASE__INST2_SEG0                    0
>+#define OSSSYS_BASE__INST2_SEG1                    0
>+#define OSSSYS_BASE__INST2_SEG2                    0
>+#define OSSSYS_BASE__INST2_SEG3                    0
>+#define OSSSYS_BASE__INST2_SEG4                    0
>+
>+#define OSSSYS_BASE__INST3_SEG0                    0
>+#define OSSSYS_BASE__INST3_SEG1                    0
>+#define OSSSYS_BASE__INST3_SEG2                    0
>+#define OSSSYS_BASE__INST3_SEG3                    0
>+#define OSSSYS_BASE__INST3_SEG4                    0
>+
>+#define OSSSYS_BASE__INST4_SEG0                    0
>+#define OSSSYS_BASE__INST4_SEG1                    0
>+#define OSSSYS_BASE__INST4_SEG2                    0
>+#define OSSSYS_BASE__INST4_SEG3                    0
>+#define OSSSYS_BASE__INST4_SEG4                    0
>+
>+#define OSSSYS_BASE__INST5_SEG0                    0
>+#define OSSSYS_BASE__INST5_SEG1                    0
>+#define OSSSYS_BASE__INST5_SEG2                    0
>+#define OSSSYS_BASE__INST5_SEG3                    0
>+#define OSSSYS_BASE__INST5_SEG4                    0
>+
>+#define OSSSYS_BASE__INST6_SEG0                    0
>+#define OSSSYS_BASE__INST6_SEG1                    0
>+#define OSSSYS_BASE__INST6_SEG2                    0
>+#define OSSSYS_BASE__INST6_SEG3                    0
>+#define OSSSYS_BASE__INST6_SEG4                    0
>+
>+#define PCIE0_BASE__INST0_SEG0                     0x02411800
>+#define PCIE0_BASE__INST0_SEG1                     0x04440000
>+#define PCIE0_BASE__INST0_SEG2                     0
>+#define PCIE0_BASE__INST0_SEG3                     0
>+#define PCIE0_BASE__INST0_SEG4                     0
>+
>+#define PCIE0_BASE__INST1_SEG0                     0
>+#define PCIE0_BASE__INST1_SEG1                     0
>+#define PCIE0_BASE__INST1_SEG2                     0
>+#define PCIE0_BASE__INST1_SEG3                     0
>+#define PCIE0_BASE__INST1_SEG4                     0
>+
>+#define PCIE0_BASE__INST2_SEG0                     0
>+#define PCIE0_BASE__INST2_SEG1                     0
>+#define PCIE0_BASE__INST2_SEG2                     0
>+#define PCIE0_BASE__INST2_SEG3                     0
>+#define PCIE0_BASE__INST2_SEG4                     0
>+
>+#define PCIE0_BASE__INST3_SEG0                     0
>+#define PCIE0_BASE__INST3_SEG1                     0
>+#define PCIE0_BASE__INST3_SEG2                     0
>+#define PCIE0_BASE__INST3_SEG3                     0
>+#define PCIE0_BASE__INST3_SEG4                     0
>+
>+#define PCIE0_BASE__INST4_SEG0                     0
>+#define PCIE0_BASE__INST4_SEG1                     0
>+#define PCIE0_BASE__INST4_SEG2                     0
>+#define PCIE0_BASE__INST4_SEG3                     0
>+#define PCIE0_BASE__INST4_SEG4                     0
>+
>+#define PCIE0_BASE__INST5_SEG0                     0
>+#define PCIE0_BASE__INST5_SEG1                     0
>+#define PCIE0_BASE__INST5_SEG2                     0
>+#define PCIE0_BASE__INST5_SEG3                     0
>+#define PCIE0_BASE__INST5_SEG4                     0
>+
>+#define PCIE0_BASE__INST6_SEG0                     0
>+#define PCIE0_BASE__INST6_SEG1                     0
>+#define PCIE0_BASE__INST6_SEG2                     0
>+#define PCIE0_BASE__INST6_SEG3                     0
>+#define PCIE0_BASE__INST6_SEG4                     0
>+
>+#define SDMA0_BASE__INST0_SEG0                     0x00001260
>+#define SDMA0_BASE__INST0_SEG1                     0x0240A800
>+#define SDMA0_BASE__INST0_SEG2                     0
>+#define SDMA0_BASE__INST0_SEG3                     0
>+#define SDMA0_BASE__INST0_SEG4                     0
>+
>+#define SDMA0_BASE__INST1_SEG0                     0
>+#define SDMA0_BASE__INST1_SEG1                     0
>+#define SDMA0_BASE__INST1_SEG2                     0
>+#define SDMA0_BASE__INST1_SEG3                     0
>+#define SDMA0_BASE__INST1_SEG4                     0
>+
>+#define SDMA0_BASE__INST2_SEG0                     0
>+#define SDMA0_BASE__INST2_SEG1                     0
>+#define SDMA0_BASE__INST2_SEG2                     0
>+#define SDMA0_BASE__INST2_SEG3                     0
>+#define SDMA0_BASE__INST2_SEG4                     0
>+
>+#define SDMA0_BASE__INST3_SEG0                     0
>+#define SDMA0_BASE__INST3_SEG1                     0
>+#define SDMA0_BASE__INST3_SEG2                     0
>+#define SDMA0_BASE__INST3_SEG3                     0
>+#define SDMA0_BASE__INST3_SEG4                     0
>+
>+#define SDMA0_BASE__INST4_SEG0                     0
>+#define SDMA0_BASE__INST4_SEG1                     0
>+#define SDMA0_BASE__INST4_SEG2                     0
>+#define SDMA0_BASE__INST4_SEG3                     0
>+#define SDMA0_BASE__INST4_SEG4                     0
>+
>+#define SDMA0_BASE__INST5_SEG0                     0
>+#define SDMA0_BASE__INST5_SEG1                     0
>+#define SDMA0_BASE__INST5_SEG2                     0
>+#define SDMA0_BASE__INST5_SEG3                     0
>+#define SDMA0_BASE__INST5_SEG4                     0
>+
>+#define SDMA0_BASE__INST6_SEG0                     0
>+#define SDMA0_BASE__INST6_SEG1                     0
>+#define SDMA0_BASE__INST6_SEG2                     0
>+#define SDMA0_BASE__INST6_SEG3                     0
>+#define SDMA0_BASE__INST6_SEG4                     0
>+
>+#define SMUIO_BASE__INST0_SEG0                     0x00016800
>+#define SMUIO_BASE__INST0_SEG1                     0x00016A00
>+#define SMUIO_BASE__INST0_SEG2                     0x02401000
>+#define SMUIO_BASE__INST0_SEG3                     0x00440000
>+#define SMUIO_BASE__INST0_SEG4                     0
>+
>+#define SMUIO_BASE__INST1_SEG0                     0
>+#define SMUIO_BASE__INST1_SEG1                     0
>+#define SMUIO_BASE__INST1_SEG2                     0
>+#define SMUIO_BASE__INST1_SEG3                     0
>+#define SMUIO_BASE__INST1_SEG4                     0
>+
>+#define SMUIO_BASE__INST2_SEG0                     0
>+#define SMUIO_BASE__INST2_SEG1                     0
>+#define SMUIO_BASE__INST2_SEG2                     0
>+#define SMUIO_BASE__INST2_SEG3                     0
>+#define SMUIO_BASE__INST2_SEG4                     0
>+
>+#define SMUIO_BASE__INST3_SEG0                     0
>+#define SMUIO_BASE__INST3_SEG1                     0
>+#define SMUIO_BASE__INST3_SEG2                     0
>+#define SMUIO_BASE__INST3_SEG3                     0
>+#define SMUIO_BASE__INST3_SEG4                     0
>+
>+#define SMUIO_BASE__INST4_SEG0                     0
>+#define SMUIO_BASE__INST4_SEG1                     0
>+#define SMUIO_BASE__INST4_SEG2                     0
>+#define SMUIO_BASE__INST4_SEG3                     0
>+#define SMUIO_BASE__INST4_SEG4                     0
>+
>+#define SMUIO_BASE__INST5_SEG0                     0
>+#define SMUIO_BASE__INST5_SEG1                     0
>+#define SMUIO_BASE__INST5_SEG2                     0
>+#define SMUIO_BASE__INST5_SEG3                     0
>+#define SMUIO_BASE__INST5_SEG4                     0
>+
>+#define SMUIO_BASE__INST6_SEG0                     0
>+#define SMUIO_BASE__INST6_SEG1                     0
>+#define SMUIO_BASE__INST6_SEG2                     0
>+#define SMUIO_BASE__INST6_SEG3                     0
>+#define SMUIO_BASE__INST6_SEG4                     0
>+
>+#define THM_BASE__INST0_SEG0                       0x00016600
>+#define THM_BASE__INST0_SEG1                       0x02400C00
>+#define THM_BASE__INST0_SEG2                       0
>+#define THM_BASE__INST0_SEG3                       0
>+#define THM_BASE__INST0_SEG4                       0
>+
>+#define THM_BASE__INST1_SEG0                       0
>+#define THM_BASE__INST1_SEG1                       0
>+#define THM_BASE__INST1_SEG2                       0
>+#define THM_BASE__INST1_SEG3                       0
>+#define THM_BASE__INST1_SEG4                       0
>+
>+#define THM_BASE__INST2_SEG0                       0
>+#define THM_BASE__INST2_SEG1                       0
>+#define THM_BASE__INST2_SEG2                       0
>+#define THM_BASE__INST2_SEG3                       0
>+#define THM_BASE__INST2_SEG4                       0
>+
>+#define THM_BASE__INST3_SEG0                       0
>+#define THM_BASE__INST3_SEG1                       0
>+#define THM_BASE__INST3_SEG2                       0
>+#define THM_BASE__INST3_SEG3                       0
>+#define THM_BASE__INST3_SEG4                       0
>+
>+#define THM_BASE__INST4_SEG0                       0
>+#define THM_BASE__INST4_SEG1                       0
>+#define THM_BASE__INST4_SEG2                       0
>+#define THM_BASE__INST4_SEG3                       0
>+#define THM_BASE__INST4_SEG4                       0
>+
>+#define THM_BASE__INST5_SEG0                       0
>+#define THM_BASE__INST5_SEG1                       0
>+#define THM_BASE__INST5_SEG2                       0
>+#define THM_BASE__INST5_SEG3                       0
>+#define THM_BASE__INST5_SEG4                       0
>+
>+#define THM_BASE__INST6_SEG0                       0
>+#define THM_BASE__INST6_SEG1                       0
>+#define THM_BASE__INST6_SEG2                       0
>+#define THM_BASE__INST6_SEG3                       0
>+#define THM_BASE__INST6_SEG4                       0
>+
>+#define UMC_BASE__INST0_SEG0                       0x00014000
>+#define UMC_BASE__INST0_SEG1                       0x02425800
>+#define UMC_BASE__INST0_SEG2                       0
>+#define UMC_BASE__INST0_SEG3                       0
>+#define UMC_BASE__INST0_SEG4                       0
>+
>+#define UMC_BASE__INST1_SEG0                       0x00054000
>+#define UMC_BASE__INST1_SEG1                       0x02425C00
>+#define UMC_BASE__INST1_SEG2                       0
>+#define UMC_BASE__INST1_SEG3                       0
>+#define UMC_BASE__INST1_SEG4                       0
>+
>+#define UMC_BASE__INST2_SEG0                       0
>+#define UMC_BASE__INST2_SEG1                       0
>+#define UMC_BASE__INST2_SEG2                       0
>+#define UMC_BASE__INST2_SEG3                       0
>+#define UMC_BASE__INST2_SEG4                       0
>+
>+#define UMC_BASE__INST3_SEG0                       0
>+#define UMC_BASE__INST3_SEG1                       0
>+#define UMC_BASE__INST3_SEG2                       0
>+#define UMC_BASE__INST3_SEG3                       0
>+#define UMC_BASE__INST3_SEG4                       0
>+
>+#define UMC_BASE__INST4_SEG0                       0
>+#define UMC_BASE__INST4_SEG1                       0
>+#define UMC_BASE__INST4_SEG2                       0
>+#define UMC_BASE__INST4_SEG3                       0
>+#define UMC_BASE__INST4_SEG4                       0
>+
>+#define UMC_BASE__INST5_SEG0                       0
>+#define UMC_BASE__INST5_SEG1                       0
>+#define UMC_BASE__INST5_SEG2                       0
>+#define UMC_BASE__INST5_SEG3                       0
>+#define UMC_BASE__INST5_SEG4                       0
>+
>+#define UMC_BASE__INST6_SEG0                       0
>+#define UMC_BASE__INST6_SEG1                       0
>+#define UMC_BASE__INST6_SEG2                       0
>+#define UMC_BASE__INST6_SEG3                       0
>+#define UMC_BASE__INST6_SEG4                       0
>+
>+#define USB0_BASE__INST0_SEG0                      0x0242A800
>+#define USB0_BASE__INST0_SEG1                      0x05B00000
>+#define USB0_BASE__INST0_SEG2                      0
>+#define USB0_BASE__INST0_SEG3                      0
>+#define USB0_BASE__INST0_SEG4                      0
>+
>+#define USB0_BASE__INST1_SEG0                      0
>+#define USB0_BASE__INST1_SEG1                      0
>+#define USB0_BASE__INST1_SEG2                      0
>+#define USB0_BASE__INST1_SEG3                      0
>+#define USB0_BASE__INST1_SEG4                      0
>+
>+#define USB0_BASE__INST2_SEG0                      0
>+#define USB0_BASE__INST2_SEG1                      0
>+#define USB0_BASE__INST2_SEG2                      0
>+#define USB0_BASE__INST2_SEG3                      0
>+#define USB0_BASE__INST2_SEG4                      0
>+
>+#define USB0_BASE__INST3_SEG0                      0
>+#define USB0_BASE__INST3_SEG1                      0
>+#define USB0_BASE__INST3_SEG2                      0
>+#define USB0_BASE__INST3_SEG3                      0
>+#define USB0_BASE__INST3_SEG4                      0
>+
>+#define USB0_BASE__INST4_SEG0                      0
>+#define USB0_BASE__INST4_SEG1                      0
>+#define USB0_BASE__INST4_SEG2                      0
>+#define USB0_BASE__INST4_SEG3                      0
>+#define USB0_BASE__INST4_SEG4                      0
>+
>+#define USB0_BASE__INST5_SEG0                      0
>+#define USB0_BASE__INST5_SEG1                      0
>+#define USB0_BASE__INST5_SEG2                      0
>+#define USB0_BASE__INST5_SEG3                      0
>+#define USB0_BASE__INST5_SEG4                      0
>+
>+#define USB0_BASE__INST6_SEG0                      0
>+#define USB0_BASE__INST6_SEG1                      0
>+#define USB0_BASE__INST6_SEG2                      0
>+#define USB0_BASE__INST6_SEG3                      0
>+#define USB0_BASE__INST6_SEG4                      0
>+
>+#define UVD0_BASE__INST0_SEG0                      0x00007800
>+#define UVD0_BASE__INST0_SEG1                      0x00007E00
>+#define UVD0_BASE__INST0_SEG2                      0x02403000
>+#define UVD0_BASE__INST0_SEG3                      0
>+#define UVD0_BASE__INST0_SEG4                      0
>+
>+#define UVD0_BASE__INST1_SEG0                      0
>+#define UVD0_BASE__INST1_SEG1                      0
>+#define UVD0_BASE__INST1_SEG2                      0
>+#define UVD0_BASE__INST1_SEG3                      0
>+#define UVD0_BASE__INST1_SEG4                      0
>+
>+#define UVD0_BASE__INST2_SEG0                      0
>+#define UVD0_BASE__INST2_SEG1                      0
>+#define UVD0_BASE__INST2_SEG2                      0
>+#define UVD0_BASE__INST2_SEG3                      0
>+#define UVD0_BASE__INST2_SEG4                      0
>+
>+#define UVD0_BASE__INST3_SEG0                      0
>+#define UVD0_BASE__INST3_SEG1                      0
>+#define UVD0_BASE__INST3_SEG2                      0
>+#define UVD0_BASE__INST3_SEG3                      0
>+#define UVD0_BASE__INST3_SEG4                      0
>+
>+#define UVD0_BASE__INST4_SEG0                      0
>+#define UVD0_BASE__INST4_SEG1                      0
>+#define UVD0_BASE__INST4_SEG2                      0
>+#define UVD0_BASE__INST4_SEG3                      0
>+#define UVD0_BASE__INST4_SEG4                      0
>+
>+#define UVD0_BASE__INST5_SEG0                      0
>+#define UVD0_BASE__INST5_SEG1                      0
>+#define UVD0_BASE__INST5_SEG2                      0
>+#define UVD0_BASE__INST5_SEG3                      0
>+#define UVD0_BASE__INST5_SEG4                      0
>+
>+#define UVD0_BASE__INST6_SEG0                      0
>+#define UVD0_BASE__INST6_SEG1                      0
>+#define UVD0_BASE__INST6_SEG2                      0
>+#define UVD0_BASE__INST6_SEG3                      0
>+#define UVD0_BASE__INST6_SEG4                      0
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/soc15_ih_clientid.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/soc15_ih_clientid.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/soc15_ih_clientid.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/soc15_ih_clientid.h	2019-08-31 15:01:11.935736175 -0500
>@@ -42,7 +42,6 @@
> 	SOC15_IH_CLIENTID_SE1SH		= 0x0b,
> 	SOC15_IH_CLIENTID_SE2SH		= 0x0c,
> 	SOC15_IH_CLIENTID_SE3SH		= 0x0d,
>-	SOC15_IH_CLIENTID_SYSHUB	= 0x0e,
> 	SOC15_IH_CLIENTID_UVD1		= 0x0e,
> 	SOC15_IH_CLIENTID_THM		= 0x0f,
> 	SOC15_IH_CLIENTID_UVD		= 0x10,
>@@ -63,7 +62,15 @@
> 
> 	SOC15_IH_CLIENTID_MAX,
> 
>-	SOC15_IH_CLIENTID_VCN		= SOC15_IH_CLIENTID_UVD
>+	SOC15_IH_CLIENTID_VCN		= SOC15_IH_CLIENTID_UVD,
>+	SOC15_IH_CLIENTID_VCN1		= SOC15_IH_CLIENTID_UVD1,
>+	SOC15_IH_CLIENTID_SDMA2		= SOC15_IH_CLIENTID_ACP,
>+	SOC15_IH_CLIENTID_SDMA3		= SOC15_IH_CLIENTID_DCE,
>+	SOC15_IH_CLIENTID_SDMA4		= SOC15_IH_CLIENTID_ISP,
>+	SOC15_IH_CLIENTID_SDMA5		= SOC15_IH_CLIENTID_VCE0,
>+	SOC15_IH_CLIENTID_SDMA6		= SOC15_IH_CLIENTID_XDMA,
>+	SOC15_IH_CLIENTID_SDMA7		= SOC15_IH_CLIENTID_VCE1,
>+	SOC15_IH_CLIENTID_VMC1		= SOC15_IH_CLIENTID_PCIE0,
> };
> 
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/include/v9_structs.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/v9_structs.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/include/v9_structs.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/include/v9_structs.h	2019-08-31 15:01:11.935736175 -0500
>@@ -196,10 +196,10 @@
> 	uint32_t compute_wave_restore_addr_lo;
> 	uint32_t compute_wave_restore_addr_hi;
> 	uint32_t compute_wave_restore_control;
>-	uint32_t reserved_39;
>-	uint32_t reserved_40;
>-	uint32_t reserved_41;
>-	uint32_t reserved_42;
>+	uint32_t compute_static_thread_mgmt_se4;
>+	uint32_t compute_static_thread_mgmt_se5;
>+	uint32_t compute_static_thread_mgmt_se6;
>+	uint32_t compute_static_thread_mgmt_se7;
> 	uint32_t reserved_43;
> 	uint32_t reserved_44;
> 	uint32_t reserved_45;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c	2019-08-31 15:01:12.255736203 -0500
>@@ -27,9 +27,105 @@
> #include "amdgpu_smu.h"
> #include "soc15_common.h"
> #include "smu_v11_0.h"
>+#include "smu_v12_0.h"
> #include "atom.h"
> #include "amd_pcie.h"
> 
>+#undef __SMU_DUMMY_MAP
>+#define __SMU_DUMMY_MAP(type)	#type
>+static const char* __smu_message_names[] = {
>+	SMU_MESSAGE_TYPES
>+};
>+
>+const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
>+{
>+	if (type < 0 || type >= SMU_MSG_MAX_COUNT)
>+		return "unknown smu message";
>+	return __smu_message_names[type];
>+}
>+
>+#undef __SMU_DUMMY_MAP
>+#define __SMU_DUMMY_MAP(fea)	#fea
>+static const char* __smu_feature_names[] = {
>+	SMU_FEATURE_MASKS
>+};
>+
>+const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
>+{
>+	if (feature < 0 || feature >= SMU_FEATURE_COUNT)
>+		return "unknown smu feature";
>+	return __smu_feature_names[feature];
>+}
>+
>+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
>+{
>+	size_t size = 0;
>+	int ret = 0, i = 0;
>+	uint32_t feature_mask[2] = { 0 };
>+	int32_t feature_index = 0;
>+	uint32_t count = 0;
>+	uint32_t sort_feature[SMU_FEATURE_COUNT];
>+	uint64_t hw_feature_count = 0;
>+
>+	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
>+	if (ret)
>+		goto failed;
>+
>+	size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
>+			feature_mask[1], feature_mask[0]);
>+
>+	for (i = 0; i < SMU_FEATURE_COUNT; i++) {
>+		feature_index = smu_feature_get_index(smu, i);
>+		if (feature_index < 0)
>+			continue;
>+		sort_feature[feature_index] = i;
>+		hw_feature_count++;
>+	}
>+
>+	for (i = 0; i < hw_feature_count; i++) {
>+		size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
>+			       count++,
>+			       smu_get_feature_name(smu, sort_feature[i]),
>+			       i,
>+			       !!smu_feature_is_enabled(smu, sort_feature[i]) ?
>+			       "enabled" : "disabled");
>+	}
>+
>+failed:
>+	return size;
>+}
>+
>+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
>+{
>+	int ret = 0;
>+	uint32_t feature_mask[2] = { 0 };
>+	uint64_t feature_2_enabled = 0;
>+	uint64_t feature_2_disabled = 0;
>+	uint64_t feature_enables = 0;
>+
>+	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
>+	if (ret)
>+		return ret;
>+
>+	feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
>+
>+	feature_2_enabled  = ~feature_enables & new_mask;
>+	feature_2_disabled = feature_enables & ~new_mask;
>+
>+	if (feature_2_enabled) {
>+		ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
>+		if (ret)
>+			return ret;
>+	}
>+	if (feature_2_disabled) {
>+		ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
>+		if (ret)
>+			return ret;
>+	}
>+
>+	return ret;
>+}
>+
> int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
> {
> 	int ret = 0;
>@@ -135,9 +231,8 @@
> int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
> 			   uint32_t *min, uint32_t *max)
> {
>-	int ret = 0, clk_id = 0;
>-	uint32_t param = 0;
> 	uint32_t clock_limit;
>+	int ret = 0;
> 
> 	if (!min && !max)
> 		return -EINVAL;
>@@ -168,36 +263,11 @@
> 
> 		return 0;
> 	}
>-
>-	mutex_lock(&smu->mutex);
>-	clk_id = smu_clk_get_index(smu, clk_type);
>-	if (clk_id < 0) {
>-		ret = -EINVAL;
>-		goto failed;
>-	}
>-
>-	param = (clk_id & 0xffff) << 16;
>-
>-	if (max) {
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
>-		if (ret)
>-			goto failed;
>-		ret = smu_read_smc_arg(smu, max);
>-		if (ret)
>-			goto failed;
>-	}
>-
>-	if (min) {
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
>-		if (ret)
>-			goto failed;
>-		ret = smu_read_smc_arg(smu, min);
>-		if (ret)
>-			goto failed;
>-	}
>-
>-failed:
>-	mutex_unlock(&smu->mutex);
>+	/*
>+	 * Todo: Use each asic(ASIC_ppt funcs) control the callbacks exposed to the
>+	 * core driver and then have helpers for stuff that is common(SMU_v11_x | SMU_v12_x funcs).
>+	 */
>+	ret = smu_get_dpm_ultimate_freq(smu, clk_type, min, max);
> 	return ret;
> }
> 
>@@ -262,7 +332,6 @@
> 	}
> 
> 	if(!smu_feature_is_enabled(smu, feature_id)) {
>-		pr_warn("smu %d clk dpm feature %d is not enabled\n", clk_type, feature_id);
> 		return false;
> 	}
> 
>@@ -319,6 +388,9 @@
> 	struct smu_power_gate *power_gate = &smu_power->power_gate;
> 	int ret = 0;
> 
>+	if(!data || !size)
>+		return -EINVAL;
>+
> 	switch (sensor) {
> 	case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
> 		*((uint32_t *)data) = smu->pstate_sclk;
>@@ -359,11 +431,12 @@
> 		     void *table_data, bool drv2smu)
> {
> 	struct smu_table_context *smu_table = &smu->smu_table;
>+	struct amdgpu_device *adev = smu->adev;
> 	struct smu_table *table = NULL;
> 	int ret = 0;
> 	int table_id = smu_table_get_index(smu, table_index);
> 
>-	if (!table_data || table_id >= smu_table->table_count)
>+	if (!table_data || table_id >= smu_table->table_count || table_id < 0)
> 		return -EINVAL;
> 
> 	table = &smu_table->tables[table_index];
>@@ -386,6 +459,9 @@
> 	if (ret)
> 		return ret;
> 
>+	/* flush hdp cache */
>+	adev->nbio_funcs->hdp_flush(adev, NULL);
>+
> 	if (!drv2smu)
> 		memcpy(table_data, table->cpu_addr, table->size);
> 
>@@ -396,12 +472,23 @@
> {
> 	if (adev->asic_type == CHIP_VEGA20)
> 		return (amdgpu_dpm == 2) ? true : false;
>-	else if (adev->asic_type >= CHIP_NAVI10)
>+	else if (adev->asic_type >= CHIP_ARCTURUS)
> 		return true;
> 	else
> 		return false;
> }
> 
>+bool is_support_sw_smu_xgmi(struct amdgpu_device *adev)
>+{
>+	if (amdgpu_dpm != 1)
>+		return false;
>+
>+	if (adev->asic_type == CHIP_VEGA20)
>+		return true;
>+
>+	return false;
>+}
>+
> int smu_sys_get_pp_table(struct smu_context *smu, void **table)
> {
> 	struct smu_table_context *smu_table = &smu->smu_table;
>@@ -479,14 +566,55 @@
> 
> 	return ret;
> }
>+int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled)
>+{
>+	uint32_t feature_low = 0, feature_high = 0;
>+	int ret = 0;
>+
>+	if (!smu->pm_enabled)
>+		return ret;
>+
>+	feature_low = (feature_mask >> 0 ) & 0xffffffff;
>+	feature_high = (feature_mask >> 32) & 0xffffffff;
>+
>+	if (enabled) {
>+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
>+						  feature_low);
>+		if (ret)
>+			return ret;
>+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
>+						  feature_high);
>+		if (ret)
>+			return ret;
>+
>+	} else {
>+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
>+						  feature_low);
>+		if (ret)
>+			return ret;
>+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
>+						  feature_high);
>+		if (ret)
>+			return ret;
>+
>+	}
>+
>+	return ret;
>+}
> 
> int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
> {
>+	struct amdgpu_device *adev = smu->adev;
> 	struct smu_feature *feature = &smu->smu_feature;
>-	uint32_t feature_id;
>+	int feature_id;
> 	int ret = 0;
> 
>+	if (adev->flags & AMD_IS_APU)
>+		return 1;
>+
> 	feature_id = smu_feature_get_index(smu, mask);
>+	if (feature_id < 0)
>+		return 0;
> 
> 	WARN_ON(feature_id > feature->feature_num);
> 
>@@ -501,15 +629,20 @@
> 			    bool enable)
> {
> 	struct smu_feature *feature = &smu->smu_feature;
>-	uint32_t feature_id;
>+	int feature_id;
>+	uint64_t feature_mask = 0;
> 	int ret = 0;
> 
> 	feature_id = smu_feature_get_index(smu, mask);
>+	if (feature_id < 0)
>+		return -EINVAL;
> 
> 	WARN_ON(feature_id > feature->feature_num);
> 
>+	feature_mask = 1ULL << feature_id;
>+
> 	mutex_lock(&feature->mutex);
>-	ret = smu_feature_update_enable_state(smu, feature_id, enable);
>+	ret = smu_feature_update_enable_state(smu, feature_mask, enable);
> 	if (ret)
> 		goto failed;
> 
>@@ -527,10 +660,12 @@
> int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
> {
> 	struct smu_feature *feature = &smu->smu_feature;
>-	uint32_t feature_id;
>+	int feature_id;
> 	int ret = 0;
> 
> 	feature_id = smu_feature_get_index(smu, mask);
>+	if (feature_id < 0)
>+		return 0;
> 
> 	WARN_ON(feature_id > feature->feature_num);
> 
>@@ -546,10 +681,12 @@
> 			      bool enable)
> {
> 	struct smu_feature *feature = &smu->smu_feature;
>-	uint32_t feature_id;
>+	int feature_id;
> 	int ret = 0;
> 
> 	feature_id = smu_feature_get_index(smu, mask);
>+	if (feature_id < 0)
>+		return -EINVAL;
> 
> 	WARN_ON(feature_id > feature->feature_num);
> 
>@@ -570,10 +707,18 @@
> 	switch (adev->asic_type) {
> 	case CHIP_VEGA20:
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
>+	case CHIP_ARCTURUS:
> 		if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
> 			smu->od_enabled = true;
> 		smu_v11_0_set_smu_funcs(smu);
> 		break;
>+	case CHIP_RENOIR:
>+		if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
>+			smu->od_enabled = true;
>+		smu_v12_0_set_smu_funcs(smu);
>+		break;
> 	default:
> 		return -EINVAL;
> 	}
>@@ -600,6 +745,7 @@
> 
> 	if (!smu->pm_enabled)
> 		return 0;
>+
> 	mutex_lock(&smu->mutex);
> 	smu_handle_task(&adev->smu,
> 			smu->smu_dpm.dpm_level,
>@@ -829,6 +975,9 @@
> 	uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
> 	int ret;
> 
>+	if (adev->flags & AMD_IS_APU)
>+		return 0;
>+
> 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
> 		pcie_gen = 3;
> 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
>@@ -875,9 +1024,11 @@
> 		return 0;
> 	}
> 
>-	ret = smu_init_display_count(smu, 0);
>-	if (ret)
>-		return ret;
>+	if (adev->asic_type != CHIP_ARCTURUS) {
>+		ret = smu_init_display_count(smu, 0);
>+		if (ret)
>+			return ret;
>+	}
> 
> 	if (initialize) {
> 		/* get boot_values from vbios to set revision, gfxclk, and etc. */
>@@ -926,6 +1077,8 @@
> 			return ret;
> 	}
> 
>+	/* smu_dump_pptable(smu); */
>+
> 	/*
> 	 * Copy pptable bo in the vram to smc with SMU MSGs such as
> 	 * SetDriverDramAddr and TransferTableDram2Smu.
>@@ -947,21 +1100,23 @@
> 	if (ret)
> 		return ret;
> 
>-	ret = smu_override_pcie_parameters(smu);
>-	if (ret)
>-		return ret;
>+	if (adev->asic_type != CHIP_ARCTURUS) {
>+		ret = smu_override_pcie_parameters(smu);
>+		if (ret)
>+			return ret;
> 
>-	ret = smu_notify_display_change(smu);
>-	if (ret)
>-		return ret;
>+		ret = smu_notify_display_change(smu);
>+		if (ret)
>+			return ret;
> 
>-	/*
>-	 * Set min deep sleep dce fclk with bootup value from vbios via
>-	 * SetMinDeepSleepDcefclk MSG.
>-	 */
>-	ret = smu_set_min_dcef_deep_sleep(smu);
>-	if (ret)
>-		return ret;
>+		/*
>+		 * Set min deep sleep dce fclk with bootup value from vbios via
>+		 * SetMinDeepSleepDcefclk MSG.
>+		 */
>+		ret = smu_set_min_dcef_deep_sleep(smu);
>+		if (ret)
>+			return ret;
>+	}
> 
> 	/*
> 	 * Set initialized values (get from vbios) to dpm tables context such as
>@@ -969,7 +1124,7 @@
> 	 * type of clks.
> 	 */
> 	if (initialize) {
>-		ret = smu_populate_smc_pptable(smu);
>+		ret = smu_populate_smc_tables(smu);
> 		if (ret)
> 			return ret;
> 
>@@ -987,7 +1142,7 @@
> 		if (ret)
> 			return ret;
> 
>-		ret = smu_get_power_limit(smu, &smu->default_power_limit, false);
>+		ret = smu_get_power_limit(smu, &smu->default_power_limit, true);
> 		if (ret)
> 			return ret;
> 	}
>@@ -1072,14 +1227,28 @@
> 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> 	struct smu_context *smu = &adev->smu;
> 
>-	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>-		ret = smu_check_fw_status(smu);
>-		if (ret) {
>-			pr_err("SMC firmware status is not correct\n");
>-			return ret;
>+	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
>+		if (adev->asic_type < CHIP_NAVI10) {
>+			ret = smu_load_microcode(smu);
>+			if (ret)
>+				return ret;
> 		}
> 	}
> 
>+	ret = smu_check_fw_status(smu);
>+	if (ret) {
>+		pr_err("SMC firmware status is not correct\n");
>+		return ret;
>+	}
>+
>+	if (adev->flags & AMD_IS_APU) {
>+		smu_powergate_sdma(&adev->smu, false);
>+		smu_powergate_vcn(&adev->smu, false);
>+	}
>+
>+	if (!smu->pm_enabled)
>+		return 0;
>+
> 	ret = smu_feature_init_dpm(smu);
> 	if (ret)
> 		goto failed;
>@@ -1124,6 +1293,11 @@
> 	struct smu_table_context *table_context = &smu->smu_table;
> 	int ret = 0;
> 
>+	if (adev->flags & AMD_IS_APU) {
>+		smu_powergate_sdma(&adev->smu, true);
>+		smu_powergate_vcn(&adev->smu, true);
>+	}
>+
> 	kfree(table_context->driver_pptable);
> 	table_context->driver_pptable = NULL;
> 
>@@ -1431,6 +1605,7 @@
> 
> 	if (!smu->pm_enabled)
> 		return -EINVAL;
>+
> 	if (!skip_display_settings) {
> 		ret = smu_display_config_changed(smu);
> 		if (ret) {
>@@ -1439,8 +1614,6 @@
> 		}
> 	}
> 
>-	if (!smu->pm_enabled)
>-		return -EINVAL;
> 	ret = smu_apply_clocks_adjust_rules(smu);
> 	if (ret) {
> 		pr_err("Failed to apply clocks adjust rules!");
>@@ -1459,9 +1632,14 @@
> 		ret = smu_asic_set_performance_level(smu, level);
> 		if (ret) {
> 			ret = smu_default_set_performance_level(smu, level);
>+			if (ret) {
>+				pr_err("Failed to set performance level!");
>+				return ret;
>+			}
> 		}
>-		if (!ret)
>-			smu_dpm_ctx->dpm_level = level;
>+
>+		/* update the saved copy */
>+		smu_dpm_ctx->dpm_level = level;
> 	}
> 
> 	if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
>@@ -1503,6 +1681,42 @@
> 	return ret;
> }
> 
>+int smu_switch_power_profile(struct smu_context *smu,
>+			     enum PP_SMC_POWER_PROFILE type,
>+			     bool en)
>+{
>+	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
>+	long workload;
>+	uint32_t index;
>+
>+	if (!smu->pm_enabled)
>+		return -EINVAL;
>+
>+	if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
>+		return -EINVAL;
>+
>+	mutex_lock(&smu->mutex);
>+
>+	if (!en) {
>+		smu->workload_mask &= ~(1 << smu->workload_prority[type]);
>+		index = fls(smu->workload_mask);
>+		index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
>+		workload = smu->workload_setting[index];
>+	} else {
>+		smu->workload_mask |= (1 << smu->workload_prority[type]);
>+		index = fls(smu->workload_mask);
>+		index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
>+		workload = smu->workload_setting[index];
>+	}
>+
>+	if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
>+		smu_set_power_profile_mode(smu, &workload, 0);
>+
>+	mutex_unlock(&smu->mutex);
>+
>+	return 0;
>+}
>+
> enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
> {
> 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
>@@ -1520,28 +1734,18 @@
> 
> int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
> {
>-	int ret = 0;
>-	int i;
> 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
>+	int ret = 0;
> 
> 	if (!smu_dpm_ctx->dpm_context)
> 		return -EINVAL;
> 
>-	for (i = 0; i < smu->adev->num_ip_blocks; i++) {
>-		if (smu->adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)
>-			break;
>-	}
>-
>-
>-	smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
>-	ret = smu_handle_task(smu, level,
>-			      AMD_PP_TASK_READJUST_POWER_STATE);
>+	ret = smu_enable_umd_pstate(smu, &level);
> 	if (ret)
> 		return ret;
> 
>-	mutex_lock(&smu->mutex);
>-	smu_dpm_ctx->dpm_level = level;
>-	mutex_unlock(&smu->mutex);
>+	ret = smu_handle_task(smu, level,
>+			      AMD_PP_TASK_READJUST_POWER_STATE);
> 
> 	return ret;
> }
>@@ -1583,4 +1787,13 @@
> 	.minor = 0,
> 	.rev = 0,
> 	.funcs = &smu_ip_funcs,
>+};
>+
>+const struct amdgpu_ip_block_version smu_v12_0_ip_block =
>+{
>+	.type = AMD_IP_BLOCK_TYPE_SMC,
>+	.major = 12,
>+	.minor = 0,
>+	.rev = 0,
>+	.funcs = &smu_ip_funcs,
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/amd_powerplay.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/amd_powerplay.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/amd_powerplay.c	2019-08-31 15:01:11.935736175 -0500
>@@ -924,6 +924,19 @@
> 	return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
> }
> 
>+static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state)
>+{
>+	struct pp_hwmgr *hwmgr = handle;
>+
>+	if (!hwmgr || !hwmgr->pm_en)
>+		return -EINVAL;
>+
>+	if (hwmgr->hwmgr_func->set_mp1_state)
>+		return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state);
>+
>+	return 0;
>+}
>+
> static int pp_dpm_switch_power_profile(void *handle,
> 		enum PP_SMC_POWER_PROFILE type, bool en)
> {
>@@ -1495,6 +1508,41 @@
> 	return ret;
> }
> 
>+static int pp_asic_reset_mode_2(void *handle)
>+{
>+	struct pp_hwmgr *hwmgr = handle;
>+		int ret = 0;
>+
>+	if (!hwmgr || !hwmgr->pm_en)
>+		return -EINVAL;
>+
>+	if (hwmgr->hwmgr_func->asic_reset == NULL) {
>+		pr_info_ratelimited("%s was not implemented.\n", __func__);
>+		return -EINVAL;
>+	}
>+
>+	mutex_lock(&hwmgr->smu_lock);
>+	ret = hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2);
>+	mutex_unlock(&hwmgr->smu_lock);
>+
>+	return ret;
>+}
>+
>+static int pp_smu_i2c_bus_access(void *handle, bool acquire)
>+{
>+	struct pp_hwmgr *hwmgr = handle;
>+
>+	if (!hwmgr || !hwmgr->pm_en)
>+		return -EINVAL;
>+
>+	if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) {
>+		pr_info_ratelimited("%s was not implemented.\n", __func__);
>+		return -EINVAL;
>+	}
>+
>+	return hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire);
>+}
>+
> static const struct amd_pm_funcs pp_dpm_funcs = {
> 	.load_firmware = pp_dpm_load_fw,
> 	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
>@@ -1525,6 +1573,7 @@
> 	.get_power_profile_mode = pp_get_power_profile_mode,
> 	.set_power_profile_mode = pp_set_power_profile_mode,
> 	.odn_edit_dpm_table = pp_odn_edit_dpm_table,
>+	.set_mp1_state = pp_dpm_set_mp1_state,
> 	.set_power_limit = pp_set_power_limit,
> 	.get_power_limit = pp_get_power_limit,
> /* export to DC */
>@@ -1550,4 +1599,6 @@
> 	.set_asic_baco_state = pp_set_asic_baco_state,
> 	.get_ppfeature_status = pp_get_ppfeature_status,
> 	.set_ppfeature_status = pp_set_ppfeature_status,
>+	.asic_reset_mode_2 = pp_asic_reset_mode_2,
>+	.smu_i2c_bus_access = pp_smu_i2c_bus_access,
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c	2019-08-31 15:01:11.936736175 -0500
>@@ -0,0 +1,1938 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include "pp_debug.h"
>+#include <linux/firmware.h>
>+#include "amdgpu.h"
>+#include "amdgpu_smu.h"
>+#include "atomfirmware.h"
>+#include "amdgpu_atomfirmware.h"
>+#include "smu_v11_0.h"
>+#include "smu11_driver_if_arcturus.h"
>+#include "soc15_common.h"
>+#include "atom.h"
>+#include "power_state.h"
>+#include "arcturus_ppt.h"
>+#include "smu_v11_0_pptable.h"
>+#include "arcturus_ppsmc.h"
>+#include "nbio/nbio_7_4_sh_mask.h"
>+
>+#define CTF_OFFSET_EDGE			5
>+#define CTF_OFFSET_HOTSPOT		5
>+#define CTF_OFFSET_HBM			5
>+
>+#define MSG_MAP(msg, index) \
>+	[SMU_MSG_##msg] = {1, (index)}
>+#define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
>+	[smu_feature] = {1, (arcturus_feature)}
>+
>+#define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
>+#define SMU_FEATURES_LOW_SHIFT       0
>+#define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
>+#define SMU_FEATURES_HIGH_SHIFT      32
>+
>+#define SMC_DPM_FEATURE ( \
>+	FEATURE_DPM_PREFETCHER_MASK | \
>+	FEATURE_DPM_GFXCLK_MASK | \
>+	FEATURE_DPM_UCLK_MASK | \
>+	FEATURE_DPM_SOCCLK_MASK | \
>+	FEATURE_DPM_MP0CLK_MASK | \
>+	FEATURE_DPM_FCLK_MASK | \
>+	FEATURE_DPM_XGMI_MASK)
>+
>+/* possible frequency drift (1Mhz) */
>+#define EPSILON				1
>+
>+static struct smu_11_0_cmn2aisc_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
>+	MSG_MAP(TestMessage,			     PPSMC_MSG_TestMessage),
>+	MSG_MAP(GetSmuVersion,			     PPSMC_MSG_GetSmuVersion),
>+	MSG_MAP(GetDriverIfVersion,		     PPSMC_MSG_GetDriverIfVersion),
>+	MSG_MAP(SetAllowedFeaturesMaskLow,	     PPSMC_MSG_SetAllowedFeaturesMaskLow),
>+	MSG_MAP(SetAllowedFeaturesMaskHigh,	     PPSMC_MSG_SetAllowedFeaturesMaskHigh),
>+	MSG_MAP(EnableAllSmuFeatures,		     PPSMC_MSG_EnableAllSmuFeatures),
>+	MSG_MAP(DisableAllSmuFeatures,		     PPSMC_MSG_DisableAllSmuFeatures),
>+	MSG_MAP(EnableSmuFeaturesLow,		     PPSMC_MSG_EnableSmuFeaturesLow),
>+	MSG_MAP(EnableSmuFeaturesHigh,		     PPSMC_MSG_EnableSmuFeaturesHigh),
>+	MSG_MAP(DisableSmuFeaturesLow,		     PPSMC_MSG_DisableSmuFeaturesLow),
>+	MSG_MAP(DisableSmuFeaturesHigh,		     PPSMC_MSG_DisableSmuFeaturesHigh),
>+	MSG_MAP(GetEnabledSmuFeaturesLow,	     PPSMC_MSG_GetEnabledSmuFeaturesLow),
>+	MSG_MAP(GetEnabledSmuFeaturesHigh,	     PPSMC_MSG_GetEnabledSmuFeaturesHigh),
>+	MSG_MAP(SetDriverDramAddrHigh,		     PPSMC_MSG_SetDriverDramAddrHigh),
>+	MSG_MAP(SetDriverDramAddrLow,		     PPSMC_MSG_SetDriverDramAddrLow),
>+	MSG_MAP(SetToolsDramAddrHigh,		     PPSMC_MSG_SetToolsDramAddrHigh),
>+	MSG_MAP(SetToolsDramAddrLow,		     PPSMC_MSG_SetToolsDramAddrLow),
>+	MSG_MAP(TransferTableSmu2Dram,		     PPSMC_MSG_TransferTableSmu2Dram),
>+	MSG_MAP(TransferTableDram2Smu,		     PPSMC_MSG_TransferTableDram2Smu),
>+	MSG_MAP(UseDefaultPPTable,		     PPSMC_MSG_UseDefaultPPTable),
>+	MSG_MAP(UseBackupPPTable,		     PPSMC_MSG_UseBackupPPTable),
>+	MSG_MAP(SetSystemVirtualDramAddrHigh,	     PPSMC_MSG_SetSystemVirtualDramAddrHigh),
>+	MSG_MAP(SetSystemVirtualDramAddrLow,	     PPSMC_MSG_SetSystemVirtualDramAddrLow),
>+	MSG_MAP(EnterBaco,			     PPSMC_MSG_EnterBaco),
>+	MSG_MAP(ExitBaco,			     PPSMC_MSG_ExitBaco),
>+	MSG_MAP(ArmD3,				     PPSMC_MSG_ArmD3),
>+	MSG_MAP(SetSoftMinByFreq,		     PPSMC_MSG_SetSoftMinByFreq),
>+	MSG_MAP(SetSoftMaxByFreq,		     PPSMC_MSG_SetSoftMaxByFreq),
>+	MSG_MAP(SetHardMinByFreq,		     PPSMC_MSG_SetHardMinByFreq),
>+	MSG_MAP(SetHardMaxByFreq,		     PPSMC_MSG_SetHardMaxByFreq),
>+	MSG_MAP(GetMinDpmFreq,			     PPSMC_MSG_GetMinDpmFreq),
>+	MSG_MAP(GetMaxDpmFreq,			     PPSMC_MSG_GetMaxDpmFreq),
>+	MSG_MAP(GetDpmFreqByIndex,		     PPSMC_MSG_GetDpmFreqByIndex),
>+	MSG_MAP(SetWorkloadMask,		     PPSMC_MSG_SetWorkloadMask),
>+	MSG_MAP(SetDfSwitchType,		     PPSMC_MSG_SetDfSwitchType),
>+	MSG_MAP(GetVoltageByDpm,		     PPSMC_MSG_GetVoltageByDpm),
>+	MSG_MAP(GetVoltageByDpmOverdrive,	     PPSMC_MSG_GetVoltageByDpmOverdrive),
>+	MSG_MAP(SetPptLimit,			     PPSMC_MSG_SetPptLimit),
>+	MSG_MAP(GetPptLimit,			     PPSMC_MSG_GetPptLimit),
>+	MSG_MAP(PowerUpVcn0,			     PPSMC_MSG_PowerUpVcn0),
>+	MSG_MAP(PowerDownVcn0,			     PPSMC_MSG_PowerDownVcn0),
>+	MSG_MAP(PowerUpVcn1,			     PPSMC_MSG_PowerUpVcn1),
>+	MSG_MAP(PowerDownVcn1,			     PPSMC_MSG_PowerDownVcn1),
>+	MSG_MAP(PrepareMp1ForUnload,		     PPSMC_MSG_PrepareMp1ForUnload),
>+	MSG_MAP(PrepareMp1ForReset,		     PPSMC_MSG_PrepareMp1ForReset),
>+	MSG_MAP(PrepareMp1ForShutdown,		     PPSMC_MSG_PrepareMp1ForShutdown),
>+	MSG_MAP(SoftReset,			     PPSMC_MSG_SoftReset),
>+	MSG_MAP(RunAfllBtc,			     PPSMC_MSG_RunAfllBtc),
>+	MSG_MAP(RunGfxDcBtc,			     PPSMC_MSG_RunGfxDcBtc),
>+	MSG_MAP(RunSocDcBtc,			     PPSMC_MSG_RunSocDcBtc),
>+	MSG_MAP(DramLogSetDramAddrHigh,		     PPSMC_MSG_DramLogSetDramAddrHigh),
>+	MSG_MAP(DramLogSetDramAddrLow,		     PPSMC_MSG_DramLogSetDramAddrLow),
>+	MSG_MAP(DramLogSetDramSize,		     PPSMC_MSG_DramLogSetDramSize),
>+	MSG_MAP(GetDebugData,			     PPSMC_MSG_GetDebugData),
>+	MSG_MAP(WaflTest,			     PPSMC_MSG_WaflTest),
>+	MSG_MAP(SetXgmiMode,			     PPSMC_MSG_SetXgmiMode),
>+	MSG_MAP(SetMemoryChannelEnable,		     PPSMC_MSG_SetMemoryChannelEnable),
>+};
>+
>+static struct smu_11_0_cmn2aisc_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
>+	CLK_MAP(GFXCLK, PPCLK_GFXCLK),
>+	CLK_MAP(SCLK,	PPCLK_GFXCLK),
>+	CLK_MAP(SOCCLK, PPCLK_SOCCLK),
>+	CLK_MAP(FCLK, PPCLK_FCLK),
>+	CLK_MAP(UCLK, PPCLK_UCLK),
>+	CLK_MAP(MCLK, PPCLK_UCLK),
>+	CLK_MAP(DCLK, PPCLK_DCLK),
>+	CLK_MAP(VCLK, PPCLK_VCLK),
>+};
>+
>+static struct smu_11_0_cmn2aisc_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
>+	FEA_MAP(DPM_PREFETCHER),
>+	FEA_MAP(DPM_GFXCLK),
>+	FEA_MAP(DPM_UCLK),
>+	FEA_MAP(DPM_SOCCLK),
>+	FEA_MAP(DPM_FCLK),
>+	FEA_MAP(DPM_MP0CLK),
>+	ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
>+	FEA_MAP(DS_GFXCLK),
>+	FEA_MAP(DS_SOCCLK),
>+	FEA_MAP(DS_LCLK),
>+	FEA_MAP(DS_FCLK),
>+	FEA_MAP(DS_UCLK),
>+	FEA_MAP(GFX_ULV),
>+	ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
>+	FEA_MAP(RSMU_SMN_CG),
>+	FEA_MAP(WAFL_CG),
>+	FEA_MAP(PPT),
>+	FEA_MAP(TDC),
>+	FEA_MAP(APCC_PLUS),
>+	FEA_MAP(VR0HOT),
>+	FEA_MAP(VR1HOT),
>+	FEA_MAP(FW_CTF),
>+	FEA_MAP(FAN_CONTROL),
>+	FEA_MAP(THERMAL),
>+	FEA_MAP(OUT_OF_BAND_MONITOR),
>+	FEA_MAP(TEMP_DEPENDENT_VMIN),
>+};
>+
>+static struct smu_11_0_cmn2aisc_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
>+	TAB_MAP(PPTABLE),
>+	TAB_MAP(AVFS),
>+	TAB_MAP(AVFS_PSM_DEBUG),
>+	TAB_MAP(AVFS_FUSE_OVERRIDE),
>+	TAB_MAP(PMSTATUSLOG),
>+	TAB_MAP(SMU_METRICS),
>+	TAB_MAP(DRIVER_SMU_CONFIG),
>+	TAB_MAP(OVERDRIVE),
>+};
>+
>+static struct smu_11_0_cmn2aisc_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
>+	PWR_MAP(AC),
>+	PWR_MAP(DC),
>+};
>+
>+static struct smu_11_0_cmn2aisc_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
>+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,	WORKLOAD_PPLIB_DEFAULT_BIT),
>+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
>+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
>+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
>+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
>+};
>+
>+static int arcturus_get_smu_msg_index(struct smu_context *smc, uint32_t index)
>+{
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
>+	if (index >= SMU_MSG_MAX_COUNT)
>+		return -EINVAL;
>+
>+	mapping = arcturus_message_map[index];
>+	if (!(mapping.valid_mapping))
>+		return -EINVAL;
>+
>+	return mapping.map_to;
>+}
>+
>+static int arcturus_get_smu_clk_index(struct smu_context *smc, uint32_t index)
>+{
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
>+	if (index >= SMU_CLK_COUNT)
>+		return -EINVAL;
>+
>+	mapping = arcturus_clk_map[index];
>+	if (!(mapping.valid_mapping)) {
>+		pr_warn("Unsupported SMU clk: %d\n", index);
>+		return -EINVAL;
>+	}
>+
>+	return mapping.map_to;
>+}
>+
>+static int arcturus_get_smu_feature_index(struct smu_context *smc, uint32_t index)
>+{
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
>+	if (index >= SMU_FEATURE_COUNT)
>+		return -EINVAL;
>+
>+	mapping = arcturus_feature_mask_map[index];
>+	if (!(mapping.valid_mapping)) {
>+		return -EINVAL;
>+	}
>+
>+	return mapping.map_to;
>+}
>+
>+static int arcturus_get_smu_table_index(struct smu_context *smc, uint32_t index)
>+{
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
>+	if (index >= SMU_TABLE_COUNT)
>+		return -EINVAL;
>+
>+	mapping = arcturus_table_map[index];
>+	if (!(mapping.valid_mapping)) {
>+		pr_warn("Unsupported SMU table: %d\n", index);
>+		return -EINVAL;
>+	}
>+
>+	return mapping.map_to;
>+}
>+
>+static int arcturus_get_pwr_src_index(struct smu_context *smc, uint32_t index)
>+{
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
>+	if (index >= SMU_POWER_SOURCE_COUNT)
>+		return -EINVAL;
>+
>+	mapping = arcturus_pwr_src_map[index];
>+	if (!(mapping.valid_mapping)) {
>+		pr_warn("Unsupported SMU power source: %d\n", index);
>+		return -EINVAL;
>+	}
>+
>+	return mapping.map_to;
>+}
>+
>+
>+static int arcturus_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
>+{
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
>+	if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
>+		return -EINVAL;
>+
>+	mapping = arcturus_workload_map[profile];
>+	if (!(mapping.valid_mapping)) {
>+		pr_warn("Unsupported SMU power source: %d\n", profile);
>+		return -EINVAL;
>+	}
>+
>+	return mapping.map_to;
>+}
>+
>+static int arcturus_tables_init(struct smu_context *smu, struct smu_table *tables)
>+{
>+	struct smu_table_context *smu_table = &smu->smu_table;
>+
>+	SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
>+		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
>+
>+	SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
>+		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
>+
>+	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
>+		       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
>+
>+	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
>+	if (!smu_table->metrics_table)
>+		return -ENOMEM;
>+	smu_table->metrics_time = 0;
>+
>+	return 0;
>+}
>+
>+static int arcturus_allocate_dpm_context(struct smu_context *smu)
>+{
>+	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
>+
>+	if (smu_dpm->dpm_context)
>+		return -EINVAL;
>+
>+	smu_dpm->dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
>+				       GFP_KERNEL);
>+	if (!smu_dpm->dpm_context)
>+		return -ENOMEM;
>+
>+	if (smu_dpm->golden_dpm_context)
>+		return -EINVAL;
>+
>+	smu_dpm->golden_dpm_context = kzalloc(sizeof(struct arcturus_dpm_table),
>+					      GFP_KERNEL);
>+	if (!smu_dpm->golden_dpm_context)
>+		return -ENOMEM;
>+
>+	smu_dpm->dpm_context_size = sizeof(struct arcturus_dpm_table);
>+
>+	smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
>+				       GFP_KERNEL);
>+	if (!smu_dpm->dpm_current_power_state)
>+		return -ENOMEM;
>+
>+	smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
>+				       GFP_KERNEL);
>+	if (!smu_dpm->dpm_request_power_state)
>+		return -ENOMEM;
>+
>+	return 0;
>+}
>+
>+static int
>+arcturus_get_allowed_feature_mask(struct smu_context *smu,
>+				  uint32_t *feature_mask, uint32_t num)
>+{
>+	if (num > 2)
>+		return -EINVAL;
>+
>+	/* pptable will handle the features to enable */
>+	memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
>+
>+	return 0;
>+}
>+
>+static int
>+arcturus_set_single_dpm_table(struct smu_context *smu,
>+			    struct arcturus_single_dpm_table *single_dpm_table,
>+			    PPCLK_e clk_id)
>+{
>+	int ret = 0;
>+	uint32_t i, num_of_levels = 0, clk;
>+
>+	ret = smu_send_smc_msg_with_param(smu,
>+			SMU_MSG_GetDpmFreqByIndex,
>+			(clk_id << 16 | 0xFF));
>+	if (ret) {
>+		pr_err("[%s] failed to get dpm levels!\n", __func__);
>+		return ret;
>+	}
>+
>+	smu_read_smc_arg(smu, &num_of_levels);
>+	if (!num_of_levels) {
>+		pr_err("[%s] number of clk levels is invalid!\n", __func__);
>+		return -EINVAL;
>+	}
>+
>+	single_dpm_table->count = num_of_levels;
>+	for (i = 0; i < num_of_levels; i++) {
>+		ret = smu_send_smc_msg_with_param(smu,
>+				SMU_MSG_GetDpmFreqByIndex,
>+				(clk_id << 16 | i));
>+		if (ret) {
>+			pr_err("[%s] failed to get dpm freq by index!\n", __func__);
>+			return ret;
>+		}
>+		smu_read_smc_arg(smu, &clk);
>+		if (!clk) {
>+			pr_err("[%s] clk value is invalid!\n", __func__);
>+			return -EINVAL;
>+		}
>+		single_dpm_table->dpm_levels[i].value = clk;
>+		single_dpm_table->dpm_levels[i].enabled = true;
>+	}
>+	return 0;
>+}
>+
>+static void arcturus_init_single_dpm_state(struct arcturus_dpm_state *dpm_state)
>+{
>+	dpm_state->soft_min_level = 0x0;
>+	dpm_state->soft_max_level = 0xffff;
>+        dpm_state->hard_min_level = 0x0;
>+        dpm_state->hard_max_level = 0xffff;
>+}
>+
>+static int arcturus_set_default_dpm_table(struct smu_context *smu)
>+{
>+	int ret;
>+
>+	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
>+	struct arcturus_dpm_table *dpm_table = NULL;
>+	struct arcturus_single_dpm_table *single_dpm_table;
>+
>+	dpm_table = smu_dpm->dpm_context;
>+
>+	/* socclk */
>+	single_dpm_table = &(dpm_table->soc_table);
>+	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
>+		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
>+						  PPCLK_SOCCLK);
>+		if (ret) {
>+			pr_err("[%s] failed to get socclk dpm levels!\n", __func__);
>+			return ret;
>+		}
>+	} else {
>+		single_dpm_table->count = 1;
>+		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
>+	}
>+	arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
>+
>+	/* gfxclk */
>+	single_dpm_table = &(dpm_table->gfx_table);
>+	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
>+		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
>+						  PPCLK_GFXCLK);
>+		if (ret) {
>+			pr_err("[SetupDefaultDpmTable] failed to get gfxclk dpm levels!");
>+			return ret;
>+		}
>+	} else {
>+		single_dpm_table->count = 1;
>+		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
>+	}
>+	arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
>+
>+	/* memclk */
>+	single_dpm_table = &(dpm_table->mem_table);
>+	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
>+		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
>+						  PPCLK_UCLK);
>+		if (ret) {
>+			pr_err("[SetupDefaultDpmTable] failed to get memclk dpm levels!");
>+			return ret;
>+		}
>+	} else {
>+		single_dpm_table->count = 1;
>+		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
>+	}
>+	arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
>+
>+	/* fclk */
>+	single_dpm_table = &(dpm_table->fclk_table);
>+	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
>+		ret = arcturus_set_single_dpm_table(smu, single_dpm_table,
>+						  PPCLK_FCLK);
>+		if (ret) {
>+			pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
>+			return ret;
>+		}
>+	} else {
>+		single_dpm_table->count = 1;
>+		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
>+	}
>+	arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
>+
>+	memcpy(smu_dpm->golden_dpm_context, dpm_table,
>+	       sizeof(struct arcturus_dpm_table));
>+
>+	return 0;
>+}
>+
>+static int arcturus_check_powerplay_table(struct smu_context *smu)
>+{
>+	return 0;
>+}
>+
>+static int arcturus_store_powerplay_table(struct smu_context *smu)
>+{
>+	struct smu_11_0_powerplay_table *powerplay_table = NULL;
>+	struct smu_table_context *table_context = &smu->smu_table;
>+	int ret = 0;
>+
>+	if (!table_context->power_play_table)
>+		return -EINVAL;
>+
>+	powerplay_table = table_context->power_play_table;
>+
>+	memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
>+	       sizeof(PPTable_t));
>+
>+	table_context->thermal_controller_type = powerplay_table->thermal_controller_type;
>+
>+	return ret;
>+}
>+
>+static int arcturus_append_powerplay_table(struct smu_context *smu)
>+{
>+	struct smu_table_context *table_context = &smu->smu_table;
>+	PPTable_t *smc_pptable = table_context->driver_pptable;
>+	struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
>+	int index, ret;
>+
>+	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
>+					   smc_dpm_info);
>+
>+	ret = smu_get_atom_data_table(smu, index, NULL, NULL, NULL,
>+				      (uint8_t **)&smc_dpm_table);
>+	if (ret)
>+		return ret;
>+
>+	pr_info("smc_dpm_info table revision(format.content): %d.%d\n",
>+			smc_dpm_table->table_header.format_revision,
>+			smc_dpm_table->table_header.content_revision);
>+
>+	if ((smc_dpm_table->table_header.format_revision == 4) &&
>+	    (smc_dpm_table->table_header.content_revision == 6))
>+		memcpy(&smc_pptable->MaxVoltageStepGfx,
>+		       &smc_dpm_table->maxvoltagestepgfx,
>+		       sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
>+
>+	return 0;
>+}
>+
>+static int arcturus_run_btc_afll(struct smu_context *smu)
>+{
>+	return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
>+}
>+
>+static int arcturus_populate_umd_state_clk(struct smu_context *smu)
>+{
>+	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
>+	struct arcturus_dpm_table *dpm_table = NULL;
>+	struct arcturus_single_dpm_table *gfx_table = NULL;
>+	struct arcturus_single_dpm_table *mem_table = NULL;
>+
>+	dpm_table = smu_dpm->dpm_context;
>+	gfx_table = &(dpm_table->gfx_table);
>+	mem_table = &(dpm_table->mem_table);
>+
>+	smu->pstate_sclk = gfx_table->dpm_levels[0].value;
>+	smu->pstate_mclk = mem_table->dpm_levels[0].value;
>+
>+	if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
>+	    mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
>+		smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
>+		smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
>+	}
>+
>+	smu->pstate_sclk = smu->pstate_sclk * 100;
>+	smu->pstate_mclk = smu->pstate_mclk * 100;
>+
>+	return 0;
>+}
>+
>+static int arcturus_get_clk_table(struct smu_context *smu,
>+			struct pp_clock_levels_with_latency *clocks,
>+			struct arcturus_single_dpm_table *dpm_table)
>+{
>+	int i, count;
>+
>+	count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
>+	clocks->num_levels = count;
>+
>+	for (i = 0; i < count; i++) {
>+		clocks->data[i].clocks_in_khz =
>+			dpm_table->dpm_levels[i].value * 1000;
>+		clocks->data[i].latency_in_us = 0;
>+	}
>+
>+	return 0;
>+}
>+
>+static int arcturus_freqs_in_same_level(int32_t frequency1,
>+					int32_t frequency2)
>+{
>+	return (abs(frequency1 - frequency2) <= EPSILON);
>+}
>+
>+static int arcturus_print_clk_levels(struct smu_context *smu,
>+			enum smu_clk_type type, char *buf)
>+{
>+	int i, now, size = 0;
>+	int ret = 0;
>+	struct pp_clock_levels_with_latency clocks;
>+	struct arcturus_single_dpm_table *single_dpm_table;
>+	struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
>+	struct arcturus_dpm_table *dpm_table = NULL;
>+
>+	dpm_table = smu_dpm->dpm_context;
>+
>+	switch (type) {
>+	case SMU_SCLK:
>+		ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, &now);
>+		if (ret) {
>+			pr_err("Attempt to get current gfx clk Failed!");
>+			return ret;
>+		}
>+
>+		single_dpm_table = &(dpm_table->gfx_table);
>+		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
>+		if (ret) {
>+			pr_err("Attempt to get gfx clk levels Failed!");
>+			return ret;
>+		}
>+
>+		for (i = 0; i < clocks.num_levels; i++)
>+			size += sprintf(buf + size, "%d: %uMhz %s\n", i,
>+					clocks.data[i].clocks_in_khz / 1000,
>+					arcturus_freqs_in_same_level(
>+					clocks.data[i].clocks_in_khz / 1000,
>+					now / 100) ? "*" : "");
>+		break;
>+
>+	case SMU_MCLK:
>+		ret = smu_get_current_clk_freq(smu, SMU_UCLK, &now);
>+		if (ret) {
>+			pr_err("Attempt to get current mclk Failed!");
>+			return ret;
>+		}
>+
>+		single_dpm_table = &(dpm_table->mem_table);
>+		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
>+		if (ret) {
>+			pr_err("Attempt to get memory clk levels Failed!");
>+			return ret;
>+		}
>+
>+		for (i = 0; i < clocks.num_levels; i++)
>+			size += sprintf(buf + size, "%d: %uMhz %s\n",
>+				i, clocks.data[i].clocks_in_khz / 1000,
>+				arcturus_freqs_in_same_level(
>+				clocks.data[i].clocks_in_khz / 1000,
>+				now / 100) ? "*" : "");
>+		break;
>+
>+	case SMU_SOCCLK:
>+		ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
>+		if (ret) {
>+			pr_err("Attempt to get current socclk Failed!");
>+			return ret;
>+		}
>+
>+		single_dpm_table = &(dpm_table->soc_table);
>+		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
>+		if (ret) {
>+			pr_err("Attempt to get socclk levels Failed!");
>+			return ret;
>+		}
>+
>+		for (i = 0; i < clocks.num_levels; i++)
>+			size += sprintf(buf + size, "%d: %uMhz %s\n",
>+				i, clocks.data[i].clocks_in_khz / 1000,
>+				arcturus_freqs_in_same_level(
>+				clocks.data[i].clocks_in_khz / 1000,
>+				now / 100) ? "*" : "");
>+		break;
>+
>+	case SMU_FCLK:
>+		ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
>+		if (ret) {
>+			pr_err("Attempt to get current fclk Failed!");
>+			return ret;
>+		}
>+
>+		single_dpm_table = &(dpm_table->fclk_table);
>+		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
>+		if (ret) {
>+			pr_err("Attempt to get fclk levels Failed!");
>+			return ret;
>+		}
>+
>+		for (i = 0; i < single_dpm_table->count; i++)
>+			size += sprintf(buf + size, "%d: %uMhz %s\n",
>+				i, single_dpm_table->dpm_levels[i].value,
>+				arcturus_freqs_in_same_level(
>+				clocks.data[i].clocks_in_khz / 1000,
>+				now / 100) ? "*" : "");
>+		break;
>+
>+	default:
>+		break;
>+	}
>+
>+	return size;
>+}
>+
>+static int arcturus_upload_dpm_level(struct smu_context *smu, bool max,
>+				     uint32_t feature_mask)
>+{
>+	struct arcturus_single_dpm_table *single_dpm_table;
>+	struct arcturus_dpm_table *dpm_table =
>+			smu->smu_dpm.dpm_context;
>+	uint32_t freq;
>+	int ret = 0;
>+
>+	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
>+	    (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
>+		single_dpm_table = &(dpm_table->gfx_table);
>+		freq = max ? single_dpm_table->dpm_state.soft_max_level :
>+			single_dpm_table->dpm_state.soft_min_level;
>+		ret = smu_send_smc_msg_with_param(smu,
>+			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
>+			(PPCLK_GFXCLK << 16) | (freq & 0xffff));
>+		if (ret) {
>+			pr_err("Failed to set soft %s gfxclk !\n",
>+						max ? "max" : "min");
>+			return ret;
>+		}
>+	}
>+
>+	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
>+	    (feature_mask & FEATURE_DPM_UCLK_MASK)) {
>+		single_dpm_table = &(dpm_table->mem_table);
>+		freq = max ? single_dpm_table->dpm_state.soft_max_level :
>+			single_dpm_table->dpm_state.soft_min_level;
>+		ret = smu_send_smc_msg_with_param(smu,
>+			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
>+			(PPCLK_UCLK << 16) | (freq & 0xffff));
>+		if (ret) {
>+			pr_err("Failed to set soft %s memclk !\n",
>+						max ? "max" : "min");
>+			return ret;
>+		}
>+	}
>+
>+	if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
>+	    (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
>+		single_dpm_table = &(dpm_table->soc_table);
>+		freq = max ? single_dpm_table->dpm_state.soft_max_level :
>+			single_dpm_table->dpm_state.soft_min_level;
>+		ret = smu_send_smc_msg_with_param(smu,
>+			(max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
>+			(PPCLK_SOCCLK << 16) | (freq & 0xffff));
>+		if (ret) {
>+			pr_err("Failed to set soft %s socclk !\n",
>+						max ? "max" : "min");
>+			return ret;
>+		}
>+	}
>+
>+	return ret;
>+}
>+
>+static int arcturus_force_clk_levels(struct smu_context *smu,
>+			enum smu_clk_type type, uint32_t mask)
>+{
>+	struct arcturus_dpm_table *dpm_table;
>+	struct arcturus_single_dpm_table *single_dpm_table;
>+	uint32_t soft_min_level, soft_max_level;
>+	int ret = 0;
>+
>+	mutex_lock(&(smu->mutex));
>+
>+	soft_min_level = mask ? (ffs(mask) - 1) : 0;
>+	soft_max_level = mask ? (fls(mask) - 1) : 0;
>+
>+	dpm_table = smu->smu_dpm.dpm_context;
>+
>+	switch (type) {
>+	case SMU_SCLK:
>+		single_dpm_table = &(dpm_table->gfx_table);
>+
>+		if (soft_max_level >= single_dpm_table->count) {
>+			pr_err("Clock level specified %d is over max allowed %d\n",
>+					soft_max_level, single_dpm_table->count - 1);
>+			ret = -EINVAL;
>+			break;
>+		}
>+
>+		single_dpm_table->dpm_state.soft_min_level =
>+			single_dpm_table->dpm_levels[soft_min_level].value;
>+		single_dpm_table->dpm_state.soft_max_level =
>+			single_dpm_table->dpm_levels[soft_max_level].value;
>+
>+		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_GFXCLK_MASK);
>+		if (ret) {
>+			pr_err("Failed to upload boot level to lowest!\n");
>+			break;
>+		}
>+
>+		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_GFXCLK_MASK);
>+		if (ret)
>+			pr_err("Failed to upload dpm max level to highest!\n");
>+
>+		break;
>+
>+	case SMU_MCLK:
>+		single_dpm_table = &(dpm_table->mem_table);
>+
>+		if (soft_max_level >= single_dpm_table->count) {
>+			pr_err("Clock level specified %d is over max allowed %d\n",
>+					soft_max_level, single_dpm_table->count - 1);
>+			ret = -EINVAL;
>+			break;
>+		}
>+
>+		single_dpm_table->dpm_state.soft_min_level =
>+			single_dpm_table->dpm_levels[soft_min_level].value;
>+		single_dpm_table->dpm_state.soft_max_level =
>+			single_dpm_table->dpm_levels[soft_max_level].value;
>+
>+		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_UCLK_MASK);
>+		if (ret) {
>+			pr_err("Failed to upload boot level to lowest!\n");
>+			break;
>+		}
>+
>+		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_UCLK_MASK);
>+		if (ret)
>+			pr_err("Failed to upload dpm max level to highest!\n");
>+
>+		break;
>+
>+	case SMU_SOCCLK:
>+		single_dpm_table = &(dpm_table->soc_table);
>+
>+		if (soft_max_level >= single_dpm_table->count) {
>+			pr_err("Clock level specified %d is over max allowed %d\n",
>+					soft_max_level, single_dpm_table->count - 1);
>+			ret = -EINVAL;
>+			break;
>+		}
>+
>+		single_dpm_table->dpm_state.soft_min_level =
>+			single_dpm_table->dpm_levels[soft_min_level].value;
>+		single_dpm_table->dpm_state.soft_max_level =
>+			single_dpm_table->dpm_levels[soft_max_level].value;
>+
>+		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_SOCCLK_MASK);
>+		if (ret) {
>+			pr_err("Failed to upload boot level to lowest!\n");
>+			break;
>+		}
>+
>+		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_SOCCLK_MASK);
>+		if (ret)
>+			pr_err("Failed to upload dpm max level to highest!\n");
>+
>+		break;
>+
>+	case SMU_FCLK:
>+		single_dpm_table = &(dpm_table->fclk_table);
>+
>+		if (soft_max_level >= single_dpm_table->count) {
>+			pr_err("Clock level specified %d is over max allowed %d\n",
>+					soft_max_level, single_dpm_table->count - 1);
>+			ret = -EINVAL;
>+			break;
>+		}
>+
>+		single_dpm_table->dpm_state.soft_min_level =
>+			single_dpm_table->dpm_levels[soft_min_level].value;
>+		single_dpm_table->dpm_state.soft_max_level =
>+			single_dpm_table->dpm_levels[soft_max_level].value;
>+
>+		ret = arcturus_upload_dpm_level(smu, false, FEATURE_DPM_FCLK_MASK);
>+		if (ret) {
>+			pr_err("Failed to upload boot level to lowest!\n");
>+			break;
>+		}
>+
>+		ret = arcturus_upload_dpm_level(smu, true, FEATURE_DPM_FCLK_MASK);
>+		if (ret)
>+			pr_err("Failed to upload dpm max level to highest!\n");
>+
>+		break;
>+
>+	default:
>+		break;
>+	}
>+
>+	mutex_unlock(&(smu->mutex));
>+	return ret;
>+}
>+
>+static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
>+						struct smu_temperature_range *range)
>+{
>+	PPTable_t *pptable = smu->smu_table.driver_pptable;
>+
>+	if (!range)
>+		return -EINVAL;
>+
>+	range->max = pptable->TedgeLimit *
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+	range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+	range->hotspot_crit_max = pptable->ThotspotLimit *
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+	range->mem_crit_max = pptable->TmemLimit *
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+	range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)*
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+
>+	return 0;
>+}
>+
>+static int arcturus_get_metrics_table(struct smu_context *smu,
>+				      SmuMetrics_t *metrics_table)
>+{
>+	struct smu_table_context *smu_table= &smu->smu_table;
>+	int ret = 0;
>+
>+	if (!smu_table->metrics_time ||
>+	     time_after(jiffies, smu_table->metrics_time + HZ / 1000)) {
>+		ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
>+				(void *)smu_table->metrics_table, false);
>+		if (ret) {
>+			pr_info("Failed to export SMU metrics table!\n");
>+			return ret;
>+		}
>+		smu_table->metrics_time = jiffies;
>+	}
>+
>+	memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
>+
>+	return ret;
>+}
>+
>+static int arcturus_get_current_activity_percent(struct smu_context *smu,
>+						 enum amd_pp_sensors sensor,
>+						 uint32_t *value)
>+{
>+	SmuMetrics_t metrics;
>+	int ret = 0;
>+
>+	if (!value)
>+		return -EINVAL;
>+
>+	ret = arcturus_get_metrics_table(smu, &metrics);
>+	if (ret)
>+		return ret;
>+
>+	switch (sensor) {
>+	case AMDGPU_PP_SENSOR_GPU_LOAD:
>+		*value = metrics.AverageGfxActivity;
>+		break;
>+	case AMDGPU_PP_SENSOR_MEM_LOAD:
>+		*value = metrics.AverageUclkActivity;
>+		break;
>+	default:
>+		pr_err("Invalid sensor for retrieving clock activity\n");
>+		return -EINVAL;
>+	}
>+
>+	return 0;
>+}
>+
>+static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
>+{
>+	SmuMetrics_t metrics;
>+	int ret = 0;
>+
>+	if (!value)
>+		return -EINVAL;
>+
>+	ret = arcturus_get_metrics_table(smu, &metrics);
>+	if (ret)
>+		return ret;
>+
>+	*value = metrics.AverageSocketPower << 8;
>+
>+	return 0;
>+}
>+
>+static int arcturus_thermal_get_temperature(struct smu_context *smu,
>+					    enum amd_pp_sensors sensor,
>+					    uint32_t *value)
>+{
>+	SmuMetrics_t metrics;
>+	int ret = 0;
>+
>+	if (!value)
>+		return -EINVAL;
>+
>+	ret = arcturus_get_metrics_table(smu, &metrics);
>+	if (ret)
>+		return ret;
>+
>+	switch (sensor) {
>+	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
>+		*value = metrics.TemperatureHotspot *
>+			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+		break;
>+	case AMDGPU_PP_SENSOR_EDGE_TEMP:
>+		*value = metrics.TemperatureEdge *
>+			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+		break;
>+	case AMDGPU_PP_SENSOR_MEM_TEMP:
>+		*value = metrics.TemperatureHBM *
>+			SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+		break;
>+	default:
>+		pr_err("Invalid sensor for retrieving temp\n");
>+		return -EINVAL;
>+	}
>+
>+	return 0;
>+}
>+
>+static int arcturus_read_sensor(struct smu_context *smu,
>+				enum amd_pp_sensors sensor,
>+				void *data, uint32_t *size)
>+{
>+	struct smu_table_context *table_context = &smu->smu_table;
>+	PPTable_t *pptable = table_context->driver_pptable;
>+	int ret = 0;
>+
>+	if (!data || !size)
>+		return -EINVAL;
>+
>+	switch (sensor) {
>+	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
>+		*(uint32_t *)data = pptable->FanMaximumRpm;
>+		*size = 4;
>+		break;
>+	case AMDGPU_PP_SENSOR_MEM_LOAD:
>+	case AMDGPU_PP_SENSOR_GPU_LOAD:
>+		ret = arcturus_get_current_activity_percent(smu,
>+							    sensor,
>+						(uint32_t *)data);
>+		*size = 4;
>+		break;
>+	case AMDGPU_PP_SENSOR_GPU_POWER:
>+		ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
>+		*size = 4;
>+		break;
>+	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
>+	case AMDGPU_PP_SENSOR_EDGE_TEMP:
>+	case AMDGPU_PP_SENSOR_MEM_TEMP:
>+		ret = arcturus_thermal_get_temperature(smu, sensor,
>+						(uint32_t *)data);
>+		*size = 4;
>+		break;
>+	default:
>+		ret = smu_smc_read_sensor(smu, sensor, data, size);
>+	}
>+
>+	return ret;
>+}
>+
>+static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
>+				      uint32_t *speed)
>+{
>+	SmuMetrics_t metrics;
>+	int ret = 0;
>+
>+	if (!speed)
>+		return -EINVAL;
>+
>+	ret = arcturus_get_metrics_table(smu, &metrics);
>+	if (ret)
>+		return ret;
>+
>+	*speed = metrics.CurrFanSpeed;
>+
>+	return ret;
>+}
>+
>+static int arcturus_get_fan_speed_percent(struct smu_context *smu,
>+					  uint32_t *speed)
>+{
>+	PPTable_t *pptable = smu->smu_table.driver_pptable;
>+	uint32_t percent, current_rpm;
>+	int ret = 0;
>+
>+	if (!speed)
>+		return -EINVAL;
>+
>+	ret = arcturus_get_fan_speed_rpm(smu, &current_rpm);
>+	if (ret)
>+		return ret;
>+
>+	percent = current_rpm * 100 / pptable->FanMaximumRpm;
>+	*speed = percent > 100 ? 100 : percent;
>+
>+	return ret;
>+}
>+
>+static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
>+				       enum smu_clk_type clk_type,
>+				       uint32_t *value)
>+{
>+	static SmuMetrics_t metrics;
>+	int ret = 0, clk_id = 0;
>+
>+	if (!value)
>+		return -EINVAL;
>+
>+	clk_id = smu_clk_get_index(smu, clk_type);
>+	if (clk_id < 0)
>+		return -EINVAL;
>+
>+	ret = arcturus_get_metrics_table(smu, &metrics);
>+	if (ret)
>+		return ret;
>+
>+	switch (clk_id) {
>+	case PPCLK_GFXCLK:
>+		/*
>+		 * CurrClock[clk_id] can provide accurate
>+		 *   output only when the dpm feature is enabled.
>+		 * We can use Average_* for dpm disabled case.
>+		 *   But this is available for gfxclk/uclk/socclk.
>+		 */
>+		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
>+			*value = metrics.CurrClock[PPCLK_GFXCLK];
>+		else
>+			*value = metrics.AverageGfxclkFrequency;
>+		break;
>+	case PPCLK_UCLK:
>+		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
>+			*value = metrics.CurrClock[PPCLK_UCLK];
>+		else
>+			*value = metrics.AverageUclkFrequency;
>+		break;
>+	case PPCLK_SOCCLK:
>+		if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
>+			*value = metrics.CurrClock[PPCLK_SOCCLK];
>+		else
>+			*value = metrics.AverageSocclkFrequency;
>+		break;
>+	default:
>+		*value = metrics.CurrClock[clk_id];
>+		break;
>+	}
>+
>+	return ret;
>+}
>+
>+static uint32_t arcturus_find_lowest_dpm_level(struct arcturus_single_dpm_table *table)
>+{
>+	uint32_t i;
>+
>+	for (i = 0; i < table->count; i++) {
>+		if (table->dpm_levels[i].enabled)
>+			break;
>+	}
>+	if (i >= table->count) {
>+		i = 0;
>+		table->dpm_levels[i].enabled = true;
>+	}
>+
>+	return i;
>+}
>+
>+static uint32_t arcturus_find_highest_dpm_level(struct arcturus_single_dpm_table *table)
>+{
>+	int i = 0;
>+
>+	if (table->count <= 0) {
>+		pr_err("[%s] DPM Table has no entry!", __func__);
>+		return 0;
>+	}
>+	if (table->count > MAX_DPM_NUMBER) {
>+		pr_err("[%s] DPM Table has too many entries!", __func__);
>+		return MAX_DPM_NUMBER - 1;
>+	}
>+
>+	for (i = table->count - 1; i >= 0; i--) {
>+		if (table->dpm_levels[i].enabled)
>+			break;
>+	}
>+	if (i < 0) {
>+		i = 0;
>+		table->dpm_levels[i].enabled = true;
>+	}
>+
>+	return i;
>+}
>+
>+
>+
>+static int arcturus_force_dpm_limit_value(struct smu_context *smu, bool highest)
>+{
>+	struct arcturus_dpm_table *dpm_table =
>+		(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
>+	uint32_t soft_level;
>+	int ret = 0;
>+
>+	/* gfxclk */
>+	if (highest)
>+		soft_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
>+	else
>+		soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
>+
>+	dpm_table->gfx_table.dpm_state.soft_min_level =
>+		dpm_table->gfx_table.dpm_state.soft_max_level =
>+		dpm_table->gfx_table.dpm_levels[soft_level].value;
>+
>+	/* uclk */
>+	if (highest)
>+		soft_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
>+	else
>+		soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
>+
>+	dpm_table->mem_table.dpm_state.soft_min_level =
>+		dpm_table->mem_table.dpm_state.soft_max_level =
>+		dpm_table->mem_table.dpm_levels[soft_level].value;
>+
>+	/* socclk */
>+	if (highest)
>+		soft_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
>+	else
>+		soft_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
>+
>+	dpm_table->soc_table.dpm_state.soft_min_level =
>+		dpm_table->soc_table.dpm_state.soft_max_level =
>+		dpm_table->soc_table.dpm_levels[soft_level].value;
>+
>+	ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
>+	if (ret) {
>+		pr_err("Failed to upload boot level to %s!\n",
>+				highest ? "highest" : "lowest");
>+		return ret;
>+	}
>+
>+	ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
>+	if (ret) {
>+		pr_err("Failed to upload dpm max level to %s!\n!",
>+				highest ? "highest" : "lowest");
>+		return ret;
>+	}
>+
>+	return ret;
>+}
>+
>+static int arcturus_unforce_dpm_levels(struct smu_context *smu)
>+{
>+	struct arcturus_dpm_table *dpm_table =
>+		(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
>+	uint32_t soft_min_level, soft_max_level;
>+	int ret = 0;
>+
>+	/* gfxclk */
>+	soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->gfx_table));
>+	soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->gfx_table));
>+	dpm_table->gfx_table.dpm_state.soft_min_level =
>+		dpm_table->gfx_table.dpm_levels[soft_min_level].value;
>+	dpm_table->gfx_table.dpm_state.soft_max_level =
>+		dpm_table->gfx_table.dpm_levels[soft_max_level].value;
>+
>+	/* uclk */
>+	soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->mem_table));
>+	soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->mem_table));
>+	dpm_table->mem_table.dpm_state.soft_min_level =
>+		dpm_table->gfx_table.dpm_levels[soft_min_level].value;
>+	dpm_table->mem_table.dpm_state.soft_max_level =
>+		dpm_table->gfx_table.dpm_levels[soft_max_level].value;
>+
>+	/* socclk */
>+	soft_min_level = arcturus_find_lowest_dpm_level(&(dpm_table->soc_table));
>+	soft_max_level = arcturus_find_highest_dpm_level(&(dpm_table->soc_table));
>+	dpm_table->soc_table.dpm_state.soft_min_level =
>+		dpm_table->soc_table.dpm_levels[soft_min_level].value;
>+	dpm_table->soc_table.dpm_state.soft_max_level =
>+		dpm_table->soc_table.dpm_levels[soft_max_level].value;
>+
>+	ret = arcturus_upload_dpm_level(smu, false, 0xFFFFFFFF);
>+	if (ret) {
>+		pr_err("Failed to upload DPM Bootup Levels!");
>+		return ret;
>+	}
>+
>+	ret = arcturus_upload_dpm_level(smu, true, 0xFFFFFFFF);
>+	if (ret) {
>+		pr_err("Failed to upload DPM Max Levels!");
>+		return ret;
>+	}
>+
>+	return ret;
>+}
>+
>+static int
>+arcturus_get_profiling_clk_mask(struct smu_context *smu,
>+				enum amd_dpm_forced_level level,
>+				uint32_t *sclk_mask,
>+				uint32_t *mclk_mask,
>+				uint32_t *soc_mask)
>+{
>+	struct arcturus_dpm_table *dpm_table =
>+		(struct arcturus_dpm_table *)smu->smu_dpm.dpm_context;
>+	struct arcturus_single_dpm_table *gfx_dpm_table;
>+	struct arcturus_single_dpm_table *mem_dpm_table;
>+	struct arcturus_single_dpm_table *soc_dpm_table;
>+
>+	if (!smu->smu_dpm.dpm_context)
>+		return -EINVAL;
>+
>+	gfx_dpm_table = &dpm_table->gfx_table;
>+	mem_dpm_table = &dpm_table->mem_table;
>+	soc_dpm_table = &dpm_table->soc_table;
>+
>+	*sclk_mask = 0;
>+	*mclk_mask = 0;
>+	*soc_mask  = 0;
>+
>+	if (gfx_dpm_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
>+	    mem_dpm_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
>+	    soc_dpm_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
>+		*sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
>+		*mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL;
>+		*soc_mask  = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL;
>+	}
>+
>+	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
>+		*sclk_mask = 0;
>+	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
>+		*mclk_mask = 0;
>+	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
>+		*sclk_mask = gfx_dpm_table->count - 1;
>+		*mclk_mask = mem_dpm_table->count - 1;
>+		*soc_mask  = soc_dpm_table->count - 1;
>+	}
>+
>+	return 0;
>+}
>+
>+static int arcturus_get_power_limit(struct smu_context *smu,
>+				     uint32_t *limit,
>+				     bool asic_default)
>+{
>+	PPTable_t *pptable = smu->smu_table.driver_pptable;
>+	uint32_t asic_default_power_limit = 0;
>+	int ret = 0;
>+	int power_src;
>+
>+	if (!smu->default_power_limit ||
>+	    !smu->power_limit) {
>+		if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
>+			power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
>+			if (power_src < 0)
>+				return -EINVAL;
>+
>+			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
>+				power_src << 16);
>+			if (ret) {
>+				pr_err("[%s] get PPT limit failed!", __func__);
>+				return ret;
>+			}
>+			smu_read_smc_arg(smu, &asic_default_power_limit);
>+		} else {
>+			/* the last hope to figure out the ppt limit */
>+			if (!pptable) {
>+				pr_err("Cannot get PPT limit due to pptable missing!");
>+				return -EINVAL;
>+			}
>+			asic_default_power_limit =
>+				pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
>+		}
>+
>+		if (smu->od_enabled) {
>+			asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
>+			asic_default_power_limit /= 100;
>+		}
>+
>+		smu->default_power_limit = asic_default_power_limit;
>+		smu->power_limit = asic_default_power_limit;
>+	}
>+
>+	if (asic_default)
>+		*limit = smu->default_power_limit;
>+	else
>+		*limit = smu->power_limit;
>+
>+	return 0;
>+}
>+
>+static int arcturus_get_power_profile_mode(struct smu_context *smu,
>+					   char *buf)
>+{
>+	static const char *profile_name[] = {
>+					"BOOTUP_DEFAULT",
>+					"3D_FULL_SCREEN",
>+					"POWER_SAVING",
>+					"VIDEO",
>+					"VR",
>+					"COMPUTE",
>+					"CUSTOM"};
>+	uint32_t i, size = 0;
>+	int16_t workload_type = 0;
>+
>+	if (!smu->pm_enabled || !buf)
>+		return -EINVAL;
>+
>+	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
>+		/*
>+		 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
>+		 * Not all profile modes are supported on arcturus.
>+		 */
>+		workload_type = smu_workload_get_type(smu, i);
>+		if (workload_type < 0)
>+			continue;
>+
>+		size += sprintf(buf + size, "%2d %14s%s\n",
>+			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
>+	}
>+
>+	return size;
>+}
>+
>+static int arcturus_set_power_profile_mode(struct smu_context *smu,
>+					   long *input,
>+					   uint32_t size)
>+{
>+	int workload_type = 0;
>+	uint32_t profile_mode = input[size];
>+	int ret = 0;
>+
>+	if (!smu->pm_enabled)
>+		return -EINVAL;
>+
>+	if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
>+		pr_err("Invalid power profile mode %d\n", profile_mode);
>+		return -EINVAL;
>+	}
>+
>+	/*
>+	 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
>+	 * Not all profile modes are supported on arcturus.
>+	 */
>+	workload_type = smu_workload_get_type(smu, profile_mode);
>+	if (workload_type < 0) {
>+		pr_err("Unsupported power profile mode %d on arcturus\n", profile_mode);
>+		return -EINVAL;
>+	}
>+
>+	ret = smu_send_smc_msg_with_param(smu,
>+					  SMU_MSG_SetWorkloadMask,
>+					  1 << workload_type);
>+	if (ret) {
>+		pr_err("Fail to set workload type %d\n", workload_type);
>+		return ret;
>+	}
>+
>+	smu->power_profile_mode = profile_mode;
>+
>+	return 0;
>+}
>+
>+static void arcturus_dump_pptable(struct smu_context *smu)
>+{
>+	struct smu_table_context *table_context = &smu->smu_table;
>+	PPTable_t *pptable = table_context->driver_pptable;
>+	int i;
>+
>+	pr_info("Dumped PPTable:\n");
>+
>+	pr_info("Version = 0x%08x\n", pptable->Version);
>+
>+	pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
>+	pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
>+
>+	for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
>+		pr_info("SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
>+		pr_info("SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
>+	}
>+
>+	pr_info("TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
>+	pr_info("TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
>+	pr_info("TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
>+	pr_info("TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
>+
>+	pr_info("TedgeLimit = %d\n", pptable->TedgeLimit);
>+	pr_info("ThotspotLimit = %d\n", pptable->ThotspotLimit);
>+	pr_info("TmemLimit = %d\n", pptable->TmemLimit);
>+	pr_info("Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
>+	pr_info("Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
>+	pr_info("Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
>+	pr_info("FitLimit = %d\n", pptable->FitLimit);
>+
>+	pr_info("PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
>+	pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
>+
>+	pr_info("ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
>+
>+	pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
>+	pr_info("UlvPadding = 0x%08x\n", pptable->UlvPadding);
>+
>+	pr_info("UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
>+	pr_info("Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
>+	pr_info("Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
>+	pr_info("Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
>+
>+	pr_info("MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
>+	pr_info("MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
>+	pr_info("MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
>+	pr_info("MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
>+
>+	pr_info("LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
>+	pr_info("LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
>+
>+	pr_info("[PPCLK_GFXCLK]\n"
>+			"  .VoltageMode          = 0x%02x\n"
>+			"  .SnapToDiscrete       = 0x%02x\n"
>+			"  .NumDiscreteLevels    = 0x%02x\n"
>+			"  .padding              = 0x%02x\n"
>+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
>+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
>+			"  .SsFmin               = 0x%04x\n"
>+			"  .Padding_16           = 0x%04x\n",
>+			pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
>+			pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
>+			pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
>+			pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
>+			pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
>+			pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
>+			pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
>+			pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
>+			pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
>+			pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
>+			pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
>+
>+	pr_info("[PPCLK_VCLK]\n"
>+			"  .VoltageMode          = 0x%02x\n"
>+			"  .SnapToDiscrete       = 0x%02x\n"
>+			"  .NumDiscreteLevels    = 0x%02x\n"
>+			"  .padding              = 0x%02x\n"
>+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
>+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
>+			"  .SsFmin               = 0x%04x\n"
>+			"  .Padding_16           = 0x%04x\n",
>+			pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
>+			pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
>+			pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
>+			pptable->DpmDescriptor[PPCLK_VCLK].padding,
>+			pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
>+			pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
>+			pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
>+			pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
>+			pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
>+			pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
>+			pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
>+
>+	pr_info("[PPCLK_DCLK]\n"
>+			"  .VoltageMode          = 0x%02x\n"
>+			"  .SnapToDiscrete       = 0x%02x\n"
>+			"  .NumDiscreteLevels    = 0x%02x\n"
>+			"  .padding              = 0x%02x\n"
>+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
>+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
>+			"  .SsFmin               = 0x%04x\n"
>+			"  .Padding_16           = 0x%04x\n",
>+			pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
>+			pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
>+			pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
>+			pptable->DpmDescriptor[PPCLK_DCLK].padding,
>+			pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
>+			pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
>+			pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
>+			pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
>+			pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
>+			pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
>+			pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
>+
>+	pr_info("[PPCLK_SOCCLK]\n"
>+			"  .VoltageMode          = 0x%02x\n"
>+			"  .SnapToDiscrete       = 0x%02x\n"
>+			"  .NumDiscreteLevels    = 0x%02x\n"
>+			"  .padding              = 0x%02x\n"
>+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
>+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
>+			"  .SsFmin               = 0x%04x\n"
>+			"  .Padding_16           = 0x%04x\n",
>+			pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
>+			pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
>+			pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
>+			pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
>+			pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
>+			pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
>+			pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
>+			pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
>+			pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
>+			pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
>+			pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
>+
>+	pr_info("[PPCLK_UCLK]\n"
>+			"  .VoltageMode          = 0x%02x\n"
>+			"  .SnapToDiscrete       = 0x%02x\n"
>+			"  .NumDiscreteLevels    = 0x%02x\n"
>+			"  .padding              = 0x%02x\n"
>+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
>+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
>+			"  .SsFmin               = 0x%04x\n"
>+			"  .Padding_16           = 0x%04x\n",
>+			pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
>+			pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
>+			pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
>+			pptable->DpmDescriptor[PPCLK_UCLK].padding,
>+			pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
>+			pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
>+			pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
>+			pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
>+			pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
>+			pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
>+			pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
>+
>+	pr_info("[PPCLK_FCLK]\n"
>+			"  .VoltageMode          = 0x%02x\n"
>+			"  .SnapToDiscrete       = 0x%02x\n"
>+			"  .NumDiscreteLevels    = 0x%02x\n"
>+			"  .padding              = 0x%02x\n"
>+			"  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
>+			"  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
>+			"  .SsFmin               = 0x%04x\n"
>+			"  .Padding_16           = 0x%04x\n",
>+			pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
>+			pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
>+			pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
>+			pptable->DpmDescriptor[PPCLK_FCLK].padding,
>+			pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
>+			pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
>+			pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
>+			pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
>+			pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
>+			pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
>+			pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
>+
>+
>+	pr_info("FreqTableGfx\n");
>+	for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
>+		pr_info("  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
>+
>+	pr_info("FreqTableVclk\n");
>+	for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
>+		pr_info("  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
>+
>+	pr_info("FreqTableDclk\n");
>+	for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
>+		pr_info("  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
>+
>+	pr_info("FreqTableSocclk\n");
>+	for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
>+		pr_info("  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
>+
>+	pr_info("FreqTableUclk\n");
>+	for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
>+		pr_info("  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
>+
>+	pr_info("FreqTableFclk\n");
>+	for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
>+		pr_info("  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
>+
>+	pr_info("Mp0clkFreq\n");
>+	for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
>+		pr_info("  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
>+
>+	pr_info("Mp0DpmVoltage\n");
>+	for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
>+		pr_info("  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
>+
>+	pr_info("GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
>+	pr_info("GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
>+	pr_info("Padding567[0] = 0x%x\n", pptable->Padding567[0]);
>+	pr_info("Padding567[1] = 0x%x\n", pptable->Padding567[1]);
>+	pr_info("Padding567[2] = 0x%x\n", pptable->Padding567[2]);
>+	pr_info("Padding567[3] = 0x%x\n", pptable->Padding567[3]);
>+	pr_info("GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
>+	pr_info("GfxclkSource = 0x%x\n", pptable->GfxclkSource);
>+	pr_info("Padding456 = 0x%x\n", pptable->Padding456);
>+
>+	pr_info("EnableTdpm = %d\n", pptable->EnableTdpm);
>+	pr_info("TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
>+	pr_info("TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
>+	pr_info("GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
>+
>+	pr_info("FanStopTemp = %d\n", pptable->FanStopTemp);
>+	pr_info("FanStartTemp = %d\n", pptable->FanStartTemp);
>+
>+	pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
>+	pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
>+	pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
>+	pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
>+	pr_info("FanGainVrMem = %d\n", pptable->FanGainVrMem);
>+	pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
>+
>+	pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
>+	pr_info("FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
>+	pr_info("FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
>+	pr_info("FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
>+	pr_info("FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
>+	pr_info("FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
>+	pr_info("FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
>+	pr_info("FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
>+	pr_info("FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
>+
>+	pr_info("FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
>+	pr_info("FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
>+	pr_info("FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
>+	pr_info("FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
>+
>+	pr_info("OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
>+	pr_info("OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
>+	pr_info("Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
>+	pr_info("Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
>+
>+	pr_info("dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
>+			pptable->dBtcGbGfxPll.a,
>+			pptable->dBtcGbGfxPll.b,
>+			pptable->dBtcGbGfxPll.c);
>+	pr_info("dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
>+			pptable->dBtcGbGfxAfll.a,
>+			pptable->dBtcGbGfxAfll.b,
>+			pptable->dBtcGbGfxAfll.c);
>+	pr_info("dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
>+			pptable->dBtcGbSoc.a,
>+			pptable->dBtcGbSoc.b,
>+			pptable->dBtcGbSoc.c);
>+
>+	pr_info("qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
>+			pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
>+			pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
>+	pr_info("qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
>+			pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
>+			pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
>+
>+	pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
>+			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
>+			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
>+			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
>+	pr_info("qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
>+			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
>+			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
>+			pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
>+
>+	pr_info("DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
>+	pr_info("DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
>+
>+	pr_info("DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
>+	pr_info("DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
>+	pr_info("Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
>+	pr_info("Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
>+
>+	pr_info("DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
>+	pr_info("DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
>+	pr_info("DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
>+	pr_info("DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
>+
>+	pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
>+	pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
>+
>+	pr_info("XgmiDpmPstates\n");
>+	for (i = 0; i < NUM_XGMI_LEVELS; i++)
>+		pr_info("  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
>+	pr_info("XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
>+	pr_info("XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
>+
>+	pr_info("VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
>+	pr_info("VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
>+	pr_info("VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
>+	pr_info("VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
>+	pr_info("VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
>+	pr_info("VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
>+	pr_info("VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
>+	pr_info("VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
>+
>+	pr_info("DebugOverrides = 0x%x\n", pptable->DebugOverrides);
>+	pr_info("ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
>+			pptable->ReservedEquation0.a,
>+			pptable->ReservedEquation0.b,
>+			pptable->ReservedEquation0.c);
>+	pr_info("ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
>+			pptable->ReservedEquation1.a,
>+			pptable->ReservedEquation1.b,
>+			pptable->ReservedEquation1.c);
>+	pr_info("ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
>+			pptable->ReservedEquation2.a,
>+			pptable->ReservedEquation2.b,
>+			pptable->ReservedEquation2.c);
>+	pr_info("ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
>+			pptable->ReservedEquation3.a,
>+			pptable->ReservedEquation3.b,
>+			pptable->ReservedEquation3.c);
>+
>+	pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
>+	pr_info("PaddingUlv = %d\n", pptable->PaddingUlv);
>+
>+	pr_info("TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
>+	pr_info("TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
>+	pr_info("TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
>+
>+	pr_info("PccThresholdLow = %d\n", pptable->PccThresholdLow);
>+	pr_info("PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
>+
>+	pr_info("Board Parameters:\n");
>+	pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
>+	pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
>+
>+	pr_info("VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
>+	pr_info("VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
>+	pr_info("VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
>+	pr_info("BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
>+
>+	pr_info("GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
>+	pr_info("ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
>+
>+	pr_info("GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
>+	pr_info("GfxOffset = 0x%x\n", pptable->GfxOffset);
>+	pr_info("Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
>+
>+	pr_info("SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
>+	pr_info("SocOffset = 0x%x\n", pptable->SocOffset);
>+	pr_info("Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
>+
>+	pr_info("MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
>+	pr_info("MemOffset = 0x%x\n", pptable->MemOffset);
>+	pr_info("Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
>+
>+	pr_info("BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
>+	pr_info("BoardOffset = 0x%x\n", pptable->BoardOffset);
>+	pr_info("Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
>+
>+	pr_info("VR0HotGpio = %d\n", pptable->VR0HotGpio);
>+	pr_info("VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
>+	pr_info("VR1HotGpio = %d\n", pptable->VR1HotGpio);
>+	pr_info("VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
>+
>+	pr_info("PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
>+	pr_info("PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
>+	pr_info("PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
>+
>+	pr_info("UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
>+	pr_info("UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
>+	pr_info("UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
>+
>+	pr_info("FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
>+	pr_info("FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
>+	pr_info("FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
>+
>+	pr_info("FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
>+	pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
>+	pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
>+
>+	for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
>+		pr_info("I2cControllers[%d]:\n", i);
>+		pr_info("                   .Enabled = %d\n",
>+				pptable->I2cControllers[i].Enabled);
>+		pr_info("                   .SlaveAddress = 0x%x\n",
>+				pptable->I2cControllers[i].SlaveAddress);
>+		pr_info("                   .ControllerPort = %d\n",
>+				pptable->I2cControllers[i].ControllerPort);
>+		pr_info("                   .ControllerName = %d\n",
>+				pptable->I2cControllers[i].ControllerName);
>+		pr_info("                   .ThermalThrottler = %d\n",
>+				pptable->I2cControllers[i].ThermalThrotter);
>+		pr_info("                   .I2cProtocol = %d\n",
>+				pptable->I2cControllers[i].I2cProtocol);
>+		pr_info("                   .Speed = %d\n",
>+				pptable->I2cControllers[i].Speed);
>+	}
>+
>+	pr_info("MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
>+	pr_info("DramBitWidth = %d\n", pptable->DramBitWidth);
>+
>+	pr_info("TotalBoardPower = %d\n", pptable->TotalBoardPower);
>+
>+	pr_info("XgmiLinkSpeed\n");
>+	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
>+		pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
>+	pr_info("XgmiLinkWidth\n");
>+	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
>+		pr_info("  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
>+	pr_info("XgmiFclkFreq\n");
>+	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
>+		pr_info("  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
>+	pr_info("XgmiSocVoltage\n");
>+	for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
>+		pr_info("  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
>+
>+}
>+
>+static bool arcturus_is_dpm_running(struct smu_context *smu)
>+{
>+	int ret = 0;
>+	uint32_t feature_mask[2];
>+	unsigned long feature_enabled;
>+	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
>+	feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
>+			   ((uint64_t)feature_mask[1] << 32));
>+	return !!(feature_enabled & SMC_DPM_FEATURE);
>+}
>+
>+static const struct pptable_funcs arcturus_ppt_funcs = {
>+	/* translate smu index into arcturus specific index */
>+	.get_smu_msg_index = arcturus_get_smu_msg_index,
>+	.get_smu_clk_index = arcturus_get_smu_clk_index,
>+	.get_smu_feature_index = arcturus_get_smu_feature_index,
>+	.get_smu_table_index = arcturus_get_smu_table_index,
>+	.get_smu_power_index= arcturus_get_pwr_src_index,
>+	.get_workload_type = arcturus_get_workload_type,
>+	/* internal structurs allocations */
>+	.tables_init = arcturus_tables_init,
>+	.alloc_dpm_context = arcturus_allocate_dpm_context,
>+	/* pptable related */
>+	.check_powerplay_table = arcturus_check_powerplay_table,
>+	.store_powerplay_table = arcturus_store_powerplay_table,
>+	.append_powerplay_table = arcturus_append_powerplay_table,
>+	/* init dpm */
>+	.get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
>+	/* btc */
>+	.run_afll_btc = arcturus_run_btc_afll,
>+	/* dpm/clk tables */
>+	.set_default_dpm_table = arcturus_set_default_dpm_table,
>+	.populate_umd_state_clk = arcturus_populate_umd_state_clk,
>+	.get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
>+	.get_current_clk_freq_by_table = arcturus_get_current_clk_freq_by_table,
>+	.print_clk_levels = arcturus_print_clk_levels,
>+	.force_clk_levels = arcturus_force_clk_levels,
>+	.read_sensor = arcturus_read_sensor,
>+	.get_fan_speed_percent = arcturus_get_fan_speed_percent,
>+	.get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
>+	.force_dpm_limit_value = arcturus_force_dpm_limit_value,
>+	.unforce_dpm_levels = arcturus_unforce_dpm_levels,
>+	.get_profiling_clk_mask = arcturus_get_profiling_clk_mask,
>+	.get_power_profile_mode = arcturus_get_power_profile_mode,
>+	.set_power_profile_mode = arcturus_set_power_profile_mode,
>+	/* debug (internal used) */
>+	.dump_pptable = arcturus_dump_pptable,
>+	.get_power_limit = arcturus_get_power_limit,
>+	.is_dpm_running = arcturus_is_dpm_running,
>+};
>+
>+void arcturus_set_ppt_funcs(struct smu_context *smu)
>+{
>+	struct smu_table_context *smu_table = &smu->smu_table;
>+
>+	smu->ppt_funcs = &arcturus_ppt_funcs;
>+	smu_table->table_count = TABLE_COUNT;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/arcturus_ppt.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/arcturus_ppt.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/arcturus_ppt.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/arcturus_ppt.h	2019-08-31 15:01:11.936736175 -0500
>@@ -0,0 +1,72 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#ifndef __ARCTURUS_PPT_H__
>+#define __ARCTURUS_PPT_H__
>+
>+#define ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL         0x3
>+#define ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL         0x3
>+#define ARCTURUS_UMD_PSTATE_MCLK_LEVEL           0x2
>+
>+#define MAX_DPM_NUMBER 16
>+#define MAX_PCIE_CONF 2
>+
>+struct arcturus_dpm_level {
>+        bool            enabled;
>+        uint32_t        value;
>+        uint32_t        param1;
>+};
>+
>+struct arcturus_dpm_state {
>+        uint32_t  soft_min_level;
>+        uint32_t  soft_max_level;
>+        uint32_t  hard_min_level;
>+        uint32_t  hard_max_level;
>+};
>+
>+struct arcturus_single_dpm_table {
>+        uint32_t                count;
>+        struct arcturus_dpm_state dpm_state;
>+        struct arcturus_dpm_level dpm_levels[MAX_DPM_NUMBER];
>+};
>+
>+struct arcturus_pcie_table {
>+        uint16_t count;
>+        uint8_t  pcie_gen[MAX_PCIE_CONF];
>+        uint8_t  pcie_lane[MAX_PCIE_CONF];
>+        uint32_t lclk[MAX_PCIE_CONF];
>+};
>+
>+struct arcturus_dpm_table {
>+        struct arcturus_single_dpm_table  soc_table;
>+        struct arcturus_single_dpm_table  gfx_table;
>+        struct arcturus_single_dpm_table  mem_table;
>+        struct arcturus_single_dpm_table  eclk_table;
>+        struct arcturus_single_dpm_table  vclk_table;
>+        struct arcturus_single_dpm_table  dclk_table;
>+        struct arcturus_single_dpm_table  fclk_table;
>+        struct arcturus_pcie_table        pcie_table;
>+};
>+
>+extern void arcturus_set_ppt_funcs(struct smu_context *smu);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c	2019-08-31 15:01:11.936736175 -0500
>@@ -1311,6 +1311,12 @@
> 	return 0;
> }
> 
>+static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
>+{
>+	return smum_send_msg_to_smc_with_parameter(hwmgr,
>+						   PPSMC_MSG_DeviceDriverReset,
>+						   mode);
>+}
> 
> static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
> 	.backend_init = smu10_hwmgr_backend_init,
>@@ -1355,6 +1361,7 @@
> 	.set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
> 	.get_power_profile_mode = smu10_get_power_profile_mode,
> 	.set_power_profile_mode = smu10_set_power_profile_mode,
>+	.asic_reset = smu10_asic_reset,
> };
> 
> int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c	2019-08-31 15:01:11.936736175 -0500
>@@ -2956,9 +2956,10 @@
> 	if (hwmgr->display_config->num_display == 0)
> 		disable_mclk_switching = false;
> 	else
>-		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) ||
>-					  disable_mclk_switching_for_frame_lock ||
>-					  smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time));
>+		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
>+					  !hwmgr->display_config->multi_monitor_in_sync) ||
>+			disable_mclk_switching_for_frame_lock ||
>+			smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time);
> 
> 	sclk = smu7_ps->performance_levels[0].engine_clock;
> 	mclk = smu7_ps->performance_levels[0].memory_clock;
>@@ -4068,6 +4069,11 @@
> 
> 	data->frame_time_x2 = frame_time_in_us * 2 / 100;
> 
>+	if (data->frame_time_x2 < 280) {
>+		pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2);
>+		data->frame_time_x2 = 280;
>+	}
>+
> 	display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
> 
> 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c	2019-08-31 15:01:11.937736175 -0500
>@@ -3220,7 +3220,8 @@
> 	if (hwmgr->display_config->num_display == 0)
> 		disable_mclk_switching = false;
> 	else
>-		disable_mclk_switching = (hwmgr->display_config->num_display > 1) ||
>+		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
>+					  !hwmgr->display_config->multi_monitor_in_sync) ||
> 			disable_mclk_switching_for_frame_lock ||
> 			disable_mclk_switching_for_vr ||
> 			force_mclk_high;
>@@ -5219,6 +5220,30 @@
> 	return 0;
> }
> 
>+static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr,
>+				enum pp_mp1_state mp1_state)
>+{
>+	uint16_t msg;
>+	int ret;
>+
>+	switch (mp1_state) {
>+	case PP_MP1_STATE_UNLOAD:
>+		msg = PPSMC_MSG_PrepareMp1ForUnload;
>+		break;
>+	case PP_MP1_STATE_SHUTDOWN:
>+	case PP_MP1_STATE_RESET:
>+	case PP_MP1_STATE_NONE:
>+	default:
>+		return 0;
>+	}
>+
>+	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0,
>+			    "[PrepareMp1] Failed!",
>+			    return ret);
>+
>+	return 0;
>+}
>+
> static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
> 				PHM_PerformanceLevelDesignation designation, uint32_t index,
> 				PHM_PerformanceLevel *level)
>@@ -5308,6 +5333,7 @@
> 	.enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost,
> 	.get_ppfeature_status = vega10_get_ppfeature_status,
> 	.set_ppfeature_status = vega10_set_ppfeature_status,
>+	.set_mp1_state = vega10_set_mp1_state,
> };
> 
> int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c	2019-08-31 15:01:11.937736175 -0500
>@@ -2639,6 +2639,30 @@
> 	return 0;
> }
> 
>+static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr,
>+				enum pp_mp1_state mp1_state)
>+{
>+	uint16_t msg;
>+	int ret;
>+
>+	switch (mp1_state) {
>+	case PP_MP1_STATE_UNLOAD:
>+		msg = PPSMC_MSG_PrepareMp1ForUnload;
>+		break;
>+	case PP_MP1_STATE_SHUTDOWN:
>+	case PP_MP1_STATE_RESET:
>+	case PP_MP1_STATE_NONE:
>+	default:
>+		return 0;
>+	}
>+
>+	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0,
>+			    "[PrepareMp1] Failed!",
>+			    return ret);
>+
>+	return 0;
>+}
>+
> static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
> 	.backend_init = vega12_hwmgr_backend_init,
> 	.backend_fini = vega12_hwmgr_backend_fini,
>@@ -2695,7 +2719,7 @@
> 	.set_asic_baco_state = vega12_baco_set_state,
> 	.get_ppfeature_status = vega12_get_ppfeature_status,
> 	.set_ppfeature_status = vega12_set_ppfeature_status,
>-
>+	.set_mp1_state = vega12_set_mp1_state,
> };
> 
> int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c	2019-08-31 15:01:11.937736175 -0500
>@@ -2101,7 +2101,11 @@
> 	if (ret)
> 		return ret;
> 
>-	*query = metrics_table.CurrSocketPower << 8;
>+	/* For the 40.46 release, they changed the value name */
>+	if (hwmgr->smu_version == 0x282e00)
>+		*query = metrics_table.AverageSocketPower << 8;
>+	else
>+		*query = metrics_table.CurrSocketPower << 8;
> 
> 	return ret;
> }
>@@ -2349,12 +2353,16 @@
> 		data->dpm_table.soc_table.dpm_state.soft_max_level =
> 		data->dpm_table.soc_table.dpm_levels[soft_level].value;
> 
>-	ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
>+	ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
>+						 FEATURE_DPM_UCLK_MASK |
>+						 FEATURE_DPM_SOCCLK_MASK);
> 	PP_ASSERT_WITH_CODE(!ret,
> 			"Failed to upload boot level to highest!",
> 			return ret);
> 
>-	ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
>+	ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
>+						 FEATURE_DPM_UCLK_MASK |
>+						 FEATURE_DPM_SOCCLK_MASK);
> 	PP_ASSERT_WITH_CODE(!ret,
> 			"Failed to upload dpm max level to highest!",
> 			return ret);
>@@ -2387,12 +2395,16 @@
> 		data->dpm_table.soc_table.dpm_state.soft_max_level =
> 		data->dpm_table.soc_table.dpm_levels[soft_level].value;
> 
>-	ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
>+	ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
>+						 FEATURE_DPM_UCLK_MASK |
>+						 FEATURE_DPM_SOCCLK_MASK);
> 	PP_ASSERT_WITH_CODE(!ret,
> 			"Failed to upload boot level to highest!",
> 			return ret);
> 
>-	ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
>+	ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
>+						 FEATURE_DPM_UCLK_MASK |
>+						 FEATURE_DPM_SOCCLK_MASK);
> 	PP_ASSERT_WITH_CODE(!ret,
> 			"Failed to upload dpm max level to highest!",
> 			return ret);
>@@ -2403,14 +2415,54 @@
> 
> static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
> {
>+	struct vega20_hwmgr *data =
>+			(struct vega20_hwmgr *)(hwmgr->backend);
>+	uint32_t soft_min_level, soft_max_level;
> 	int ret = 0;
> 
>-	ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
>+	/* gfxclk soft min/max settings */
>+	soft_min_level =
>+		vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
>+	soft_max_level =
>+		vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
>+
>+	data->dpm_table.gfx_table.dpm_state.soft_min_level =
>+		data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
>+	data->dpm_table.gfx_table.dpm_state.soft_max_level =
>+		data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
>+
>+	/* uclk soft min/max settings */
>+	soft_min_level =
>+		vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
>+	soft_max_level =
>+		vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
>+
>+	data->dpm_table.mem_table.dpm_state.soft_min_level =
>+		data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
>+	data->dpm_table.mem_table.dpm_state.soft_max_level =
>+		data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
>+
>+	/* socclk soft min/max settings */
>+	soft_min_level =
>+		vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
>+	soft_max_level =
>+		vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
>+
>+	data->dpm_table.soc_table.dpm_state.soft_min_level =
>+		data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
>+	data->dpm_table.soc_table.dpm_state.soft_max_level =
>+		data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
>+
>+	ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
>+						 FEATURE_DPM_UCLK_MASK |
>+						 FEATURE_DPM_SOCCLK_MASK);
> 	PP_ASSERT_WITH_CODE(!ret,
> 			"Failed to upload DPM Bootup Levels!",
> 			return ret);
> 
>-	ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
>+	ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
>+						 FEATURE_DPM_UCLK_MASK |
>+						 FEATURE_DPM_SOCCLK_MASK);
> 	PP_ASSERT_WITH_CODE(!ret,
> 			"Failed to upload DPM Max Levels!",
> 			return ret);
>@@ -3063,6 +3115,34 @@
> 	return 0;
> }
> 
>+static int vega20_set_mp1_state(struct pp_hwmgr *hwmgr,
>+				enum pp_mp1_state mp1_state)
>+{
>+	uint16_t msg;
>+	int ret;
>+
>+	switch (mp1_state) {
>+	case PP_MP1_STATE_SHUTDOWN:
>+		msg = PPSMC_MSG_PrepareMp1ForShutdown;
>+		break;
>+	case PP_MP1_STATE_UNLOAD:
>+		msg = PPSMC_MSG_PrepareMp1ForUnload;
>+		break;
>+	case PP_MP1_STATE_RESET:
>+		msg = PPSMC_MSG_PrepareMp1ForReset;
>+		break;
>+	case PP_MP1_STATE_NONE:
>+	default:
>+		return 0;
>+	}
>+
>+	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0,
>+			    "[PrepareMp1] Failed!",
>+			    return ret);
>+
>+	return 0;
>+}
>+
> static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
> {
> 	static const char *ppfeature_name[] = {
>@@ -4057,6 +4137,24 @@
> 	return 0;
> }
> 
>+static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire)
>+{
>+	int res;
>+
>+	/* I2C bus access can happen very early, when SMU not loaded yet */
>+	if (!vega20_is_smc_ram_running(hwmgr))
>+		return 0;
>+
>+	res = smum_send_msg_to_smc_with_parameter(hwmgr,
>+						  (acquire ?
>+						  PPSMC_MSG_RequestI2CBus :
>+						  PPSMC_MSG_ReleaseI2CBus),
>+						  0);
>+
>+	PP_ASSERT_WITH_CODE(!res, "[SmuI2CAccessBus] Failed to access bus!", return res);
>+	return res;
>+}
>+
> static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
> 	/* init/fini related */
> 	.backend_init = vega20_hwmgr_backend_init,
>@@ -4123,6 +4221,8 @@
> 	.get_asic_baco_capability = vega20_baco_get_capability,
> 	.get_asic_baco_state = vega20_baco_get_state,
> 	.set_asic_baco_state = vega20_baco_set_state,
>+	.set_mp1_state = vega20_set_mp1_state,
>+	.smu_i2c_bus_access = vega20_smu_i2c_bus_access,
> };
> 
> int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h	2019-08-31 15:05:45.842760376 -0500
>@@ -26,6 +26,7 @@
> #include "kgd_pp_interface.h"
> #include "dm_pp_interface.h"
> #include "dm_pp_smu.h"
>+#include "smu_types.h"
> 
> #define SMU_THERMAL_MINIMUM_ALERT_TEMP		0
> #define SMU_THERMAL_MAXIMUM_ALERT_TEMP		255
>@@ -150,124 +151,6 @@
> 	struct smu_hw_power_state                     hardware;
> };
> 
>-enum smu_message_type
>-{
>-	SMU_MSG_TestMessage = 0,
>-	SMU_MSG_GetSmuVersion,
>-	SMU_MSG_GetDriverIfVersion,
>-	SMU_MSG_SetAllowedFeaturesMaskLow,
>-	SMU_MSG_SetAllowedFeaturesMaskHigh,
>-	SMU_MSG_EnableAllSmuFeatures,
>-	SMU_MSG_DisableAllSmuFeatures,
>-	SMU_MSG_EnableSmuFeaturesLow,
>-	SMU_MSG_EnableSmuFeaturesHigh,
>-	SMU_MSG_DisableSmuFeaturesLow,
>-	SMU_MSG_DisableSmuFeaturesHigh,
>-	SMU_MSG_GetEnabledSmuFeaturesLow,
>-	SMU_MSG_GetEnabledSmuFeaturesHigh,
>-	SMU_MSG_SetWorkloadMask,
>-	SMU_MSG_SetPptLimit,
>-	SMU_MSG_SetDriverDramAddrHigh,
>-	SMU_MSG_SetDriverDramAddrLow,
>-	SMU_MSG_SetToolsDramAddrHigh,
>-	SMU_MSG_SetToolsDramAddrLow,
>-	SMU_MSG_TransferTableSmu2Dram,
>-	SMU_MSG_TransferTableDram2Smu,
>-	SMU_MSG_UseDefaultPPTable,
>-	SMU_MSG_UseBackupPPTable,
>-	SMU_MSG_RunBtc,
>-	SMU_MSG_RequestI2CBus,
>-	SMU_MSG_ReleaseI2CBus,
>-	SMU_MSG_SetFloorSocVoltage,
>-	SMU_MSG_SoftReset,
>-	SMU_MSG_StartBacoMonitor,
>-	SMU_MSG_CancelBacoMonitor,
>-	SMU_MSG_EnterBaco,
>-	SMU_MSG_SetSoftMinByFreq,
>-	SMU_MSG_SetSoftMaxByFreq,
>-	SMU_MSG_SetHardMinByFreq,
>-	SMU_MSG_SetHardMaxByFreq,
>-	SMU_MSG_GetMinDpmFreq,
>-	SMU_MSG_GetMaxDpmFreq,
>-	SMU_MSG_GetDpmFreqByIndex,
>-	SMU_MSG_GetDpmClockFreq,
>-	SMU_MSG_GetSsVoltageByDpm,
>-	SMU_MSG_SetMemoryChannelConfig,
>-	SMU_MSG_SetGeminiMode,
>-	SMU_MSG_SetGeminiApertureHigh,
>-	SMU_MSG_SetGeminiApertureLow,
>-	SMU_MSG_SetMinLinkDpmByIndex,
>-	SMU_MSG_OverridePcieParameters,
>-	SMU_MSG_OverDriveSetPercentage,
>-	SMU_MSG_SetMinDeepSleepDcefclk,
>-	SMU_MSG_ReenableAcDcInterrupt,
>-	SMU_MSG_NotifyPowerSource,
>-	SMU_MSG_SetUclkFastSwitch,
>-	SMU_MSG_SetUclkDownHyst,
>-	SMU_MSG_GfxDeviceDriverReset,
>-	SMU_MSG_GetCurrentRpm,
>-	SMU_MSG_SetVideoFps,
>-	SMU_MSG_SetTjMax,
>-	SMU_MSG_SetFanTemperatureTarget,
>-	SMU_MSG_PrepareMp1ForUnload,
>-	SMU_MSG_DramLogSetDramAddrHigh,
>-	SMU_MSG_DramLogSetDramAddrLow,
>-	SMU_MSG_DramLogSetDramSize,
>-	SMU_MSG_SetFanMaxRpm,
>-	SMU_MSG_SetFanMinPwm,
>-	SMU_MSG_ConfigureGfxDidt,
>-	SMU_MSG_NumOfDisplays,
>-	SMU_MSG_RemoveMargins,
>-	SMU_MSG_ReadSerialNumTop32,
>-	SMU_MSG_ReadSerialNumBottom32,
>-	SMU_MSG_SetSystemVirtualDramAddrHigh,
>-	SMU_MSG_SetSystemVirtualDramAddrLow,
>-	SMU_MSG_WaflTest,
>-	SMU_MSG_SetFclkGfxClkRatio,
>-	SMU_MSG_AllowGfxOff,
>-	SMU_MSG_DisallowGfxOff,
>-	SMU_MSG_GetPptLimit,
>-	SMU_MSG_GetDcModeMaxDpmFreq,
>-	SMU_MSG_GetDebugData,
>-	SMU_MSG_SetXgmiMode,
>-	SMU_MSG_RunAfllBtc,
>-	SMU_MSG_ExitBaco,
>-	SMU_MSG_PrepareMp1ForReset,
>-	SMU_MSG_PrepareMp1ForShutdown,
>-	SMU_MSG_SetMGpuFanBoostLimitRpm,
>-	SMU_MSG_GetAVFSVoltageByDpm,
>-	SMU_MSG_PowerUpVcn,
>-	SMU_MSG_PowerDownVcn,
>-	SMU_MSG_PowerUpJpeg,
>-	SMU_MSG_PowerDownJpeg,
>-	SMU_MSG_BacoAudioD3PME,
>-	SMU_MSG_ArmD3,
>-	SMU_MSG_MAX_COUNT,
>-};
>-
>-enum smu_clk_type
>-{
>-	SMU_GFXCLK,
>-	SMU_VCLK,
>-	SMU_DCLK,
>-	SMU_ECLK,
>-	SMU_SOCCLK,
>-	SMU_UCLK,
>-	SMU_DCEFCLK,
>-	SMU_DISPCLK,
>-	SMU_PIXCLK,
>-	SMU_PHYCLK,
>-	SMU_FCLK,
>-	SMU_SCLK,
>-	SMU_MCLK,
>-	SMU_PCIE,
>-	SMU_OD_SCLK,
>-	SMU_OD_MCLK,
>-	SMU_OD_VDDC_CURVE,
>-	SMU_OD_RANGE,
>-	SMU_CLK_COUNT,
>-};
>-
> enum smu_power_src_type
> {
> 	SMU_POWER_SOURCE_AC,
>@@ -275,63 +158,6 @@
> 	SMU_POWER_SOURCE_COUNT,
> };
> 
>-enum smu_feature_mask
>-{
>-	SMU_FEATURE_DPM_PREFETCHER_BIT,
>-	SMU_FEATURE_DPM_GFXCLK_BIT,
>-	SMU_FEATURE_DPM_UCLK_BIT,
>-	SMU_FEATURE_DPM_SOCCLK_BIT,
>-	SMU_FEATURE_DPM_UVD_BIT,
>-	SMU_FEATURE_DPM_VCE_BIT,
>-	SMU_FEATURE_ULV_BIT,
>-	SMU_FEATURE_DPM_MP0CLK_BIT,
>-	SMU_FEATURE_DPM_LINK_BIT,
>-	SMU_FEATURE_DPM_DCEFCLK_BIT,
>-	SMU_FEATURE_DS_GFXCLK_BIT,
>-	SMU_FEATURE_DS_SOCCLK_BIT,
>-	SMU_FEATURE_DS_LCLK_BIT,
>-	SMU_FEATURE_PPT_BIT,
>-	SMU_FEATURE_TDC_BIT,
>-	SMU_FEATURE_THERMAL_BIT,
>-	SMU_FEATURE_GFX_PER_CU_CG_BIT,
>-	SMU_FEATURE_RM_BIT,
>-	SMU_FEATURE_DS_DCEFCLK_BIT,
>-	SMU_FEATURE_ACDC_BIT,
>-	SMU_FEATURE_VR0HOT_BIT,
>-	SMU_FEATURE_VR1HOT_BIT,
>-	SMU_FEATURE_FW_CTF_BIT,
>-	SMU_FEATURE_LED_DISPLAY_BIT,
>-	SMU_FEATURE_FAN_CONTROL_BIT,
>-	SMU_FEATURE_GFX_EDC_BIT,
>-	SMU_FEATURE_GFXOFF_BIT,
>-	SMU_FEATURE_CG_BIT,
>-	SMU_FEATURE_DPM_FCLK_BIT,
>-	SMU_FEATURE_DS_FCLK_BIT,
>-	SMU_FEATURE_DS_MP1CLK_BIT,
>-	SMU_FEATURE_DS_MP0CLK_BIT,
>-	SMU_FEATURE_XGMI_BIT,
>-	SMU_FEATURE_DPM_GFX_PACE_BIT,
>-	SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
>-	SMU_FEATURE_MEM_MVDD_SCALING_BIT,
>-	SMU_FEATURE_DS_UCLK_BIT,
>-	SMU_FEATURE_GFX_ULV_BIT,
>-	SMU_FEATURE_FW_DSTATE_BIT,
>-	SMU_FEATURE_BACO_BIT,
>-	SMU_FEATURE_VCN_PG_BIT,
>-	SMU_FEATURE_JPEG_PG_BIT,
>-	SMU_FEATURE_USB_PG_BIT,
>-	SMU_FEATURE_RSMU_SMN_CG_BIT,
>-	SMU_FEATURE_APCC_PLUS_BIT,
>-	SMU_FEATURE_GTHR_BIT,
>-	SMU_FEATURE_GFX_DCS_BIT,
>-	SMU_FEATURE_GFX_SS_BIT,
>-	SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
>-	SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
>-	SMU_FEATURE_MMHUB_PG_BIT,
>-	SMU_FEATURE_ATHUB_PG_BIT,
>-	SMU_FEATURE_COUNT,
>-};
>-
> enum smu_memory_pool_size
> {
>     SMU_MEMORY_POOL_SIZE_ZERO   = 0,
>@@ -396,12 +222,17 @@
> 	uint16_t			vdd_gfx;
> 	uint8_t				cooling_id;
> 	uint32_t			pp_table_id;
>+	uint32_t			format_revision;
>+	uint32_t			content_revision;
>+	uint32_t			fclk;
> };
> 
> enum smu_table_id
> {
> 	SMU_TABLE_PPTABLE = 0,
> 	SMU_TABLE_WATERMARKS,
>+	SMU_TABLE_CUSTOM_DPM,
>+	SMU_TABLE_DPMCLOCKS,
> 	SMU_TABLE_AVFS,
> 	SMU_TABLE_AVFS_PSM_DEBUG,
> 	SMU_TABLE_AVFS_FUSE_OVERRIDE,
>@@ -422,6 +253,7 @@
> 	void				*hardcode_pptable;
> 	unsigned long			metrics_time;
> 	void				*metrics_table;
>+	void				*clocks_table;
> 
> 	void				*max_sustainable_clocks;
> 	struct smu_bios_boot_up_values	boot_values;
>@@ -540,6 +372,8 @@
> #define WATERMARKS_EXIST	(1 << 0)
> #define WATERMARKS_LOADED	(1 << 1)
> 	uint32_t watermarks_bitmap;
>+	uint32_t hard_min_uclk_req_from_dal;
>+	bool disable_uclk_switch;
> 
> 	uint32_t workload_mask;
> 	uint32_t workload_prority[WORKLOAD_POLICY_MAX];
>@@ -607,8 +441,6 @@
> 				      uint32_t *mclk_mask,
> 				      uint32_t *soc_mask);
> 	int (*set_cpu_power_state)(struct smu_context *smu);
>-	int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
>-	int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
> 	bool (*is_dpm_running)(struct smu_context *smu);
> 	int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
> 	int (*set_thermal_fan_table)(struct smu_context *smu);
>@@ -623,6 +455,10 @@
> 	int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
> 	int (*set_default_od_settings)(struct smu_context *smu, bool initialize);
> 	int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
>+	int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
>+	void (*dump_pptable)(struct smu_context *smu);
>+	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool asic_default);
>+	int (*get_dpm_uclk_limited)(struct smu_context *smu, uint32_t *clock, bool max);
> };
> 
> struct smu_funcs
>@@ -639,8 +475,11 @@
> 	int (*get_clk_info_from_vbios)(struct smu_context *smu);
> 	int (*check_pptable)(struct smu_context *smu);
> 	int (*parse_pptable)(struct smu_context *smu);
>-	int (*populate_smc_pptable)(struct smu_context *smu);
>+	int (*populate_smc_tables)(struct smu_context *smu);
> 	int (*check_fw_version)(struct smu_context *smu);
>+	int (*powergate_sdma)(struct smu_context *smu, bool gate);
>+	int (*powergate_vcn)(struct smu_context *smu, bool gate);
>+	int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
> 	int (*write_pptable)(struct smu_context *smu);
> 	int (*set_min_dcef_deep_sleep)(struct smu_context *smu);
> 	int (*set_tool_table_location)(struct smu_context *smu);
>@@ -654,9 +493,7 @@
> 	int (*init_display_count)(struct smu_context *smu, uint32_t count);
> 	int (*set_allowed_mask)(struct smu_context *smu);
> 	int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
>-	int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
> 	int (*notify_display_change)(struct smu_context *smu);
>-	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
> 	int (*set_power_limit)(struct smu_context *smu, uint32_t n);
> 	int (*get_current_clk_freq)(struct smu_context *smu, enum smu_clk_type clk_id, uint32_t *value);
> 	int (*init_max_sustainable_clocks)(struct smu_context *smu);
>@@ -700,7 +537,7 @@
> 	enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
> 	int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
> 	int (*baco_reset)(struct smu_context *smu);
>-
>+	int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
> };
> 
> #define smu_init_microcode(smu) \
>@@ -719,6 +556,12 @@
> 	((smu)->funcs->check_fw_status ? (smu)->funcs->check_fw_status((smu)) : 0)
> #define smu_setup_pptable(smu) \
> 	((smu)->funcs->setup_pptable ? (smu)->funcs->setup_pptable((smu)) : 0)
>+#define smu_powergate_sdma(smu, gate) \
>+	((smu)->funcs->powergate_sdma ? (smu)->funcs->powergate_sdma((smu), (gate)) : 0)
>+#define smu_powergate_vcn(smu, gate) \
>+	((smu)->funcs->powergate_vcn ? (smu)->funcs->powergate_vcn((smu), (gate)) : 0)
>+#define smu_set_gfx_cgpg(smu, enabled) \
>+	((smu)->funcs->set_gfx_cgpg ? (smu)->funcs->set_gfx_cgpg((smu), (enabled)) : 0)
> #define smu_get_vbios_bootup_values(smu) \
> 	((smu)->funcs->get_vbios_bootup_values ? (smu)->funcs->get_vbios_bootup_values((smu)) : 0)
> #define smu_get_clk_info_from_vbios(smu) \
>@@ -727,8 +570,8 @@
> 	((smu)->funcs->check_pptable ? (smu)->funcs->check_pptable((smu)) : 0)
> #define smu_parse_pptable(smu) \
> 	((smu)->funcs->parse_pptable ? (smu)->funcs->parse_pptable((smu)) : 0)
>-#define smu_populate_smc_pptable(smu) \
>-	((smu)->funcs->populate_smc_pptable ? (smu)->funcs->populate_smc_pptable((smu)) : 0)
>+#define smu_populate_smc_tables(smu) \
>+	((smu)->funcs->populate_smc_tables ? (smu)->funcs->populate_smc_tables((smu)) : 0)
> #define smu_check_fw_version(smu) \
> 	((smu)->funcs->check_fw_version ? (smu)->funcs->check_fw_version((smu)) : 0)
> #define smu_write_pptable(smu) \
>@@ -770,8 +613,6 @@
> 	((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
> #define smu_is_dpm_running(smu) \
> 	((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
>-#define smu_feature_update_enable_state(smu, feature_id, enabled) \
>-	((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
> #define smu_notify_display_change(smu) \
> 	((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
> #define smu_store_powerplay_table(smu) \
>@@ -787,7 +628,7 @@
> #define smu_set_default_od8_settings(smu) \
> 	((smu)->ppt_funcs->set_default_od8_settings ? (smu)->ppt_funcs->set_default_od8_settings((smu)) : 0)
> #define smu_get_power_limit(smu, limit, def) \
>-	((smu)->funcs->get_power_limit ? (smu)->funcs->get_power_limit((smu), (limit), (def)) : 0)
>+	((smu)->ppt_funcs->get_power_limit ? (smu)->ppt_funcs->get_power_limit((smu), (limit), (def)) : 0)
> #define smu_set_power_limit(smu, limit) \
> 	((smu)->funcs->set_power_limit ? (smu)->funcs->set_power_limit((smu), (limit)) : 0)
> #define smu_get_current_clk_freq(smu, clk_id, value) \
>@@ -809,9 +650,9 @@
> #define smu_start_thermal_control(smu) \
> 	((smu)->funcs->start_thermal_control? (smu)->funcs->start_thermal_control((smu)) : 0)
> #define smu_read_sensor(smu, sensor, data, size) \
>-	((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
>-#define smu_asic_read_sensor(smu, sensor, data, size) \
> 	((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), (sensor), (data), (size)) : 0)
>+#define smu_smc_read_sensor(smu, sensor, data, size) \
>+	((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), (data), (size)) : -EINVAL)
> #define smu_get_power_profile_mode(smu, buf) \
> 	((smu)->ppt_funcs->get_power_profile_mode ? (smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
> #define smu_set_power_profile_mode(smu, param, param_size) \
>@@ -875,6 +716,8 @@
> 	((smu)->ppt_funcs->get_clock_by_type_with_voltage ? (smu)->ppt_funcs->get_clock_by_type_with_voltage((smu), (type), (clocks)) : 0)
> #define smu_display_clock_voltage_request(smu, clock_req) \
> 	((smu)->funcs->display_clock_voltage_request ? (smu)->funcs->display_clock_voltage_request((smu), (clock_req)) : 0)
>+#define smu_display_disable_memory_clock_switch(smu, disable_memory_clock_switch) \
>+	((smu)->ppt_funcs->display_disable_memory_clock_switch ? (smu)->ppt_funcs->display_disable_memory_clock_switch((smu), (disable_memory_clock_switch)) : -EINVAL)
> #define smu_get_dal_power_level(smu, clocks) \
> 	((smu)->funcs->get_dal_power_level ? (smu)->funcs->get_dal_power_level((smu), (clocks)) : 0)
> #define smu_get_perf_level(smu, designation, level) \
>@@ -891,10 +734,6 @@
> 	((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
> #define smu_set_xgmi_pstate(smu, pstate) \
> 		((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
>-#define smu_set_ppfeature_status(smu, ppfeatures) \
>-	((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
>-#define smu_get_ppfeature_status(smu, buf) \
>-	((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
> #define smu_set_watermarks_table(smu, tab, clock_ranges) \
> 	((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
> #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
>@@ -907,6 +746,10 @@
> 	((smu)->funcs->register_irq_handler ? (smu)->funcs->register_irq_handler(smu) : 0)
> #define smu_set_azalia_d3_pme(smu) \
> 	((smu)->funcs->set_azalia_d3_pme ? (smu)->funcs->set_azalia_d3_pme((smu)) : 0)
>+#define smu_get_dpm_ultimate_freq(smu, param, min, max) \
>+		((smu)->funcs->get_dpm_ultimate_freq ? (smu)->funcs->get_dpm_ultimate_freq((smu), (param), (min), (max)) : 0)
>+#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
>+	((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
> #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
> 	((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
> #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
>@@ -919,6 +762,10 @@
> 	((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)
> #define smu_asic_set_performance_level(smu, level) \
> 	((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL);
>+#define smu_dump_pptable(smu) \
>+	((smu)->ppt_funcs->dump_pptable ? (smu)->ppt_funcs->dump_pptable((smu)) : 0)
>+#define smu_get_dpm_uclk_limited(smu, clock, max) \
>+		((smu)->ppt_funcs->get_dpm_uclk_limited ? (smu)->ppt_funcs->get_dpm_uclk_limited((smu), (clock), (max)) : -EINVAL)
> 
> 
> extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
>@@ -928,6 +775,8 @@
> extern const struct amd_ip_funcs smu_ip_funcs;
> 
> extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
>+extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
>+
> extern int smu_feature_init_dpm(struct smu_context *smu);
> 
> extern int smu_feature_is_enabled(struct smu_context *smu,
>@@ -943,6 +792,7 @@
> 		     void *table_data, bool drv2smu);
> 
> bool is_support_sw_smu(struct amdgpu_device *adev);
>+bool is_support_sw_smu_xgmi(struct amdgpu_device *adev);
> int smu_reset(struct smu_context *smu);
> int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
> 			   void *data, uint32_t *size);
>@@ -961,6 +811,9 @@
> extern int smu_handle_task(struct smu_context *smu,
> 			   enum amd_dpm_forced_level level,
> 			   enum amd_pp_task task_id);
>+int smu_switch_power_profile(struct smu_context *smu,
>+			     enum PP_SMC_POWER_PROFILE type,
>+			     bool en);
> int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version);
> int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_type,
> 			      uint16_t level, uint32_t *value);
>@@ -976,5 +829,10 @@
> int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
> int smu_set_display_count(struct smu_context *smu, uint32_t count);
> bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
>+int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
>+const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
>+const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
>+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
>+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
> 
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/arcturus_ppsmc.h	2019-08-31 15:01:11.937736175 -0500
>@@ -0,0 +1,120 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef ARCTURUS_PP_SMC_H
>+#define ARCTURUS_PP_SMC_H
>+
>+#pragma pack(push, 1)
>+
>+// SMU Response Codes:
>+#define PPSMC_Result_OK                    0x1
>+#define PPSMC_Result_Failed                0xFF
>+#define PPSMC_Result_UnknownCmd            0xFE
>+#define PPSMC_Result_CmdRejectedPrereq     0xFD
>+#define PPSMC_Result_CmdRejectedBusy       0xFC
>+
>+// Message Definitions:
>+// BASIC
>+#define PPSMC_MSG_TestMessage                    0x1
>+#define PPSMC_MSG_GetSmuVersion                  0x2
>+#define PPSMC_MSG_GetDriverIfVersion             0x3
>+#define PPSMC_MSG_SetAllowedFeaturesMaskLow      0x4
>+#define PPSMC_MSG_SetAllowedFeaturesMaskHigh     0x5
>+#define PPSMC_MSG_EnableAllSmuFeatures           0x6
>+#define PPSMC_MSG_DisableAllSmuFeatures          0x7
>+#define PPSMC_MSG_EnableSmuFeaturesLow           0x8
>+#define PPSMC_MSG_EnableSmuFeaturesHigh          0x9
>+#define PPSMC_MSG_DisableSmuFeaturesLow          0xA
>+#define PPSMC_MSG_DisableSmuFeaturesHigh         0xB
>+#define PPSMC_MSG_GetEnabledSmuFeaturesLow       0xC
>+#define PPSMC_MSG_GetEnabledSmuFeaturesHigh      0xD
>+#define PPSMC_MSG_SetDriverDramAddrHigh          0xE
>+#define PPSMC_MSG_SetDriverDramAddrLow           0xF
>+#define PPSMC_MSG_SetToolsDramAddrHigh           0x10
>+#define PPSMC_MSG_SetToolsDramAddrLow            0x11
>+#define PPSMC_MSG_TransferTableSmu2Dram          0x12
>+#define PPSMC_MSG_TransferTableDram2Smu          0x13
>+#define PPSMC_MSG_UseDefaultPPTable              0x14
>+#define PPSMC_MSG_UseBackupPPTable               0x15
>+#define PPSMC_MSG_SetSystemVirtualDramAddrHigh   0x16
>+#define PPSMC_MSG_SetSystemVirtualDramAddrLow    0x17
>+
>+//BACO/BAMACO/BOMACO
>+#define PPSMC_MSG_EnterBaco                      0x18
>+#define PPSMC_MSG_ExitBaco                       0x19
>+#define PPSMC_MSG_ArmD3                          0x1A
>+
>+//DPM
>+#define PPSMC_MSG_SetSoftMinByFreq               0x1B
>+#define PPSMC_MSG_SetSoftMaxByFreq               0x1C
>+#define PPSMC_MSG_SetHardMinByFreq               0x1D
>+#define PPSMC_MSG_SetHardMaxByFreq               0x1E
>+#define PPSMC_MSG_GetMinDpmFreq                  0x1F
>+#define PPSMC_MSG_GetMaxDpmFreq                  0x20
>+#define PPSMC_MSG_GetDpmFreqByIndex              0x21
>+
>+#define PPSMC_MSG_SetWorkloadMask                0x22
>+#define PPSMC_MSG_SetDfSwitchType                0x23
>+#define PPSMC_MSG_GetVoltageByDpm                0x24
>+#define PPSMC_MSG_GetVoltageByDpmOverdrive       0x25
>+
>+#define PPSMC_MSG_SetPptLimit                    0x26
>+#define PPSMC_MSG_GetPptLimit                    0x27
>+
>+//Power Gating
>+#define PPSMC_MSG_PowerUpVcn0                    0x28
>+#define PPSMC_MSG_PowerDownVcn0                  0x29
>+#define PPSMC_MSG_PowerUpVcn1                    0x2A
>+#define PPSMC_MSG_PowerDownVcn1                  0x2B
>+
>+//Resets and reload
>+#define PPSMC_MSG_PrepareMp1ForUnload            0x2C
>+#define PPSMC_MSG_PrepareMp1ForReset             0x2D
>+#define PPSMC_MSG_PrepareMp1ForShutdown          0x2E
>+#define PPSMC_MSG_SoftReset                      0x2F
>+
>+//BTC
>+#define PPSMC_MSG_RunAfllBtc                     0x30
>+#define PPSMC_MSG_RunGfxDcBtc                    0x31
>+#define PPSMC_MSG_RunSocDcBtc                    0x32
>+
>+//Debug
>+#define PPSMC_MSG_DramLogSetDramAddrHigh         0x33
>+#define PPSMC_MSG_DramLogSetDramAddrLow          0x34
>+#define PPSMC_MSG_DramLogSetDramSize             0x35
>+#define PPSMC_MSG_GetDebugData                   0x36
>+
>+//WAFL and XGMI
>+#define PPSMC_MSG_WaflTest                       0x37
>+#define PPSMC_MSG_SetXgmiMode                    0x38
>+
>+//Others
>+#define PPSMC_MSG_SetMemoryChannelEnable         0x39
>+
>+#define PPSMC_Message_Count                      0x3A
>+
>+typedef uint32_t PPSMC_Result;
>+typedef uint32_t PPSMC_Msg;
>+#pragma pack(pop)
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h	2019-08-31 15:01:11.937736175 -0500
>@@ -189,6 +189,14 @@
> 	struct phm_vce_clock_voltage_dependency_record entries[1];
> };
> 
>+
>+enum SMU_ASIC_RESET_MODE
>+{
>+    SMU_ASIC_RESET_MODE_0,
>+    SMU_ASIC_RESET_MODE_1,
>+    SMU_ASIC_RESET_MODE_2,
>+};
>+
> struct pp_smumgr_func {
> 	char *name;
> 	int (*smu_init)(struct pp_hwmgr  *hwmgr);
>@@ -344,6 +352,9 @@
> 	int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
> 	int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
> 	int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
>+	int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
>+	int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
>+	int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
> };
> 
> struct pp_table_func {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h	2019-08-31 15:01:11.937736175 -0500
>@@ -59,7 +59,7 @@
> #define PPSMC_MSG_SetDriverDramAddrLow          0x1B
> #define PPSMC_MSG_TransferTableSmu2Dram         0x1C
> #define PPSMC_MSG_TransferTableDram2Smu         0x1D
>-#define PPSMC_MSG_ControlGfxRM                  0x1E
>+#define PPSMC_MSG_DeviceDriverReset             0x1E
> #define PPSMC_MSG_SetGfxclkOverdriveByFreqVid   0x1F
> #define PPSMC_MSG_SetHardMinDcefclkByFreq       0x20
> #define PPSMC_MSG_SetHardMinSocclkByFreq        0x21
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h	2019-08-31 15:01:11.938736175 -0500
>@@ -0,0 +1,891 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef SMU11_DRIVER_IF_ARCTURUS_H
>+#define SMU11_DRIVER_IF_ARCTURUS_H
>+
>+// *** IMPORTANT ***
>+// SMU TEAM: Always increment the interface version if
>+// any structure is changed in this file
>+//#define SMU11_DRIVER_IF_VERSION 0x09
>+
>+#define PPTABLE_ARCTURUS_SMU_VERSION 4
>+
>+#define NUM_GFXCLK_DPM_LEVELS  16
>+#define NUM_VCLK_DPM_LEVELS    8
>+#define NUM_DCLK_DPM_LEVELS    8
>+#define NUM_MP0CLK_DPM_LEVELS  2
>+#define NUM_SOCCLK_DPM_LEVELS  8
>+#define NUM_UCLK_DPM_LEVELS    4
>+#define NUM_FCLK_DPM_LEVELS    8
>+#define NUM_XGMI_LEVELS        2
>+#define NUM_XGMI_PSTATE_LEVELS 4
>+
>+#define MAX_GFXCLK_DPM_LEVEL  (NUM_GFXCLK_DPM_LEVELS  - 1)
>+#define MAX_VCLK_DPM_LEVEL    (NUM_VCLK_DPM_LEVELS    - 1)
>+#define MAX_DCLK_DPM_LEVEL    (NUM_DCLK_DPM_LEVELS    - 1)
>+#define MAX_MP0CLK_DPM_LEVEL  (NUM_MP0CLK_DPM_LEVELS  - 1)
>+#define MAX_SOCCLK_DPM_LEVEL  (NUM_SOCCLK_DPM_LEVELS  - 1)
>+#define MAX_UCLK_DPM_LEVEL    (NUM_UCLK_DPM_LEVELS    - 1)
>+#define MAX_FCLK_DPM_LEVEL    (NUM_FCLK_DPM_LEVELS    - 1)
>+#define MAX_XGMI_LEVEL        (NUM_XGMI_LEVELS        - 1)
>+#define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1)
>+
>+// Feature Control Defines
>+// DPM
>+#define FEATURE_DPM_PREFETCHER_BIT      0
>+#define FEATURE_DPM_GFXCLK_BIT          1
>+#define FEATURE_DPM_UCLK_BIT            2
>+#define FEATURE_DPM_SOCCLK_BIT          3
>+#define FEATURE_DPM_FCLK_BIT            4
>+#define FEATURE_DPM_MP0CLK_BIT          5
>+#define FEATURE_DPM_XGMI_BIT            6
>+// Idle
>+#define FEATURE_DS_GFXCLK_BIT           7
>+#define FEATURE_DS_SOCCLK_BIT           8
>+#define FEATURE_DS_LCLK_BIT             9
>+#define FEATURE_DS_FCLK_BIT             10
>+#define FEATURE_DS_UCLK_BIT             11
>+#define FEATURE_GFX_ULV_BIT             12
>+#define FEATURE_DPM_VCN_BIT             13
>+#define FEATURE_RSMU_SMN_CG_BIT         14
>+#define FEATURE_WAFL_CG_BIT             15
>+// Throttler/Response
>+#define FEATURE_PPT_BIT                 16
>+#define FEATURE_TDC_BIT                 17
>+#define FEATURE_APCC_PLUS_BIT           18
>+#define FEATURE_VR0HOT_BIT              19
>+#define FEATURE_VR1HOT_BIT              20
>+#define FEATURE_FW_CTF_BIT              21
>+#define FEATURE_FAN_CONTROL_BIT         22
>+#define FEATURE_THERMAL_BIT             23
>+// Other
>+#define FEATURE_OUT_OF_BAND_MONITOR_BIT 24
>+#define FEATURE_TEMP_DEPENDENT_VMIN_BIT 25
>+
>+#define FEATURE_SPARE_26_BIT            26
>+#define FEATURE_SPARE_27_BIT            27
>+#define FEATURE_SPARE_28_BIT            28
>+#define FEATURE_SPARE_29_BIT            29
>+#define FEATURE_SPARE_30_BIT            30
>+#define FEATURE_SPARE_31_BIT            31
>+#define FEATURE_SPARE_32_BIT            32
>+#define FEATURE_SPARE_33_BIT            33
>+#define FEATURE_SPARE_34_BIT            34
>+#define FEATURE_SPARE_35_BIT            35
>+#define FEATURE_SPARE_36_BIT            36
>+#define FEATURE_SPARE_37_BIT            37
>+#define FEATURE_SPARE_38_BIT            38
>+#define FEATURE_SPARE_39_BIT            39
>+#define FEATURE_SPARE_40_BIT            40
>+#define FEATURE_SPARE_41_BIT            41
>+#define FEATURE_SPARE_42_BIT            42
>+#define FEATURE_SPARE_43_BIT            43
>+#define FEATURE_SPARE_44_BIT            44
>+#define FEATURE_SPARE_45_BIT            45
>+#define FEATURE_SPARE_46_BIT            46
>+#define FEATURE_SPARE_47_BIT            47
>+#define FEATURE_SPARE_48_BIT            48
>+#define FEATURE_SPARE_49_BIT            49
>+#define FEATURE_SPARE_50_BIT            50
>+#define FEATURE_SPARE_51_BIT            51
>+#define FEATURE_SPARE_52_BIT            52
>+#define FEATURE_SPARE_53_BIT            53
>+#define FEATURE_SPARE_54_BIT            54
>+#define FEATURE_SPARE_55_BIT            55
>+#define FEATURE_SPARE_56_BIT            56
>+#define FEATURE_SPARE_57_BIT            57
>+#define FEATURE_SPARE_58_BIT            58
>+#define FEATURE_SPARE_59_BIT            59
>+#define FEATURE_SPARE_60_BIT            60
>+#define FEATURE_SPARE_61_BIT            61
>+#define FEATURE_SPARE_62_BIT            62
>+#define FEATURE_SPARE_63_BIT            63
>+
>+#define NUM_FEATURES                    64
>+
>+
>+#define FEATURE_DPM_PREFETCHER_MASK       (1 << FEATURE_DPM_PREFETCHER_BIT       )
>+#define FEATURE_DPM_GFXCLK_MASK           (1 << FEATURE_DPM_GFXCLK_BIT           )
>+#define FEATURE_DPM_UCLK_MASK             (1 << FEATURE_DPM_UCLK_BIT             )
>+#define FEATURE_DPM_SOCCLK_MASK           (1 << FEATURE_DPM_SOCCLK_BIT           )
>+#define FEATURE_DPM_FCLK_MASK             (1 << FEATURE_DPM_FCLK_BIT             )
>+#define FEATURE_DPM_MP0CLK_MASK           (1 << FEATURE_DPM_MP0CLK_BIT           )
>+#define FEATURE_DPM_XGMI_MASK             (1 << FEATURE_DPM_XGMI_BIT             )
>+
>+#define FEATURE_DS_GFXCLK_MASK            (1 << FEATURE_DS_GFXCLK_BIT            )
>+#define FEATURE_DS_SOCCLK_MASK            (1 << FEATURE_DS_SOCCLK_BIT            )
>+#define FEATURE_DS_LCLK_MASK              (1 << FEATURE_DS_LCLK_BIT              )
>+#define FEATURE_DS_FCLK_MASK              (1 << FEATURE_DS_FCLK_BIT              )
>+#define FEATURE_DS_LCLK_MASK              (1 << FEATURE_DS_LCLK_BIT              )
>+#define FEATURE_GFX_ULV_MASK              (1 << FEATURE_GFX_ULV_BIT              )
>+#define FEATURE_VCN_PG_MASK               (1 << FEATURE_VCN_PG_BIT               )
>+#define FEATURE_RSMU_SMN_CG_MASK          (1 << FEATURE_RSMU_SMN_CG_BIT          )
>+#define FEATURE_WAFL_CG_MASK              (1 << FEATURE_WAFL_CG_BIT              )
>+
>+#define FEATURE_PPT_MASK                  (1 << FEATURE_PPT_BIT                  )
>+#define FEATURE_TDC_MASK                  (1 << FEATURE_TDC_BIT                  )
>+#define FEATURE_APCC_MASK                 (1 << FEATURE_APCC_BIT                 )
>+#define FEATURE_VR0HOT_MASK               (1 << FEATURE_VR0HOT_BIT               )
>+#define FEATURE_VR1HOT_MASK               (1 << FEATURE_VR1HOT_BIT               )
>+#define FEATURE_FW_CTF_MASK               (1 << FEATURE_FW_CTF_BIT               )
>+#define FEATURE_FAN_CONTROL_MASK          (1 << FEATURE_FAN_CONTROL_BIT          )
>+#define FEATURE_THERMAL_MASK              (1 << FEATURE_THERMAL_BIT              )
>+
>+#define FEATURE_OUT_OF_BAND_MONITOR_MASK  (1 << EATURE_OUT_OF_BAND_MONITOR_BIT   )
>+#define FEATURE_TEMP_DEPENDENT_VMIN_MASK  (1 << FEATURE_TEMP_DEPENDENT_VMIN_MASK )
>+
>+
>+//FIXME need updating
>+// Debug Overrides Bitmask
>+#define DPM_OVERRIDE_DISABLE_UCLK_PID               0x00000001
>+#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCN_FCLK      0x00000002
>+
>+// I2C Config Bit Defines
>+#define I2C_CONTROLLER_ENABLED           1
>+#define I2C_CONTROLLER_DISABLED          0
>+
>+// VR Mapping Bit Defines
>+#define VR_MAPPING_VR_SELECT_MASK  0x01
>+#define VR_MAPPING_VR_SELECT_SHIFT 0x00
>+
>+#define VR_MAPPING_PLANE_SELECT_MASK  0x02
>+#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
>+
>+// PSI Bit Defines
>+#define PSI_SEL_VR0_PLANE0_PSI0  0x01
>+#define PSI_SEL_VR0_PLANE0_PSI1  0x02
>+#define PSI_SEL_VR0_PLANE1_PSI0  0x04
>+#define PSI_SEL_VR0_PLANE1_PSI1  0x08
>+#define PSI_SEL_VR1_PLANE0_PSI0  0x10
>+#define PSI_SEL_VR1_PLANE0_PSI1  0x20
>+#define PSI_SEL_VR1_PLANE1_PSI0  0x40
>+#define PSI_SEL_VR1_PLANE1_PSI1  0x80
>+
>+// Throttler Control/Status Bits
>+#define THROTTLER_PADDING_BIT      0
>+#define THROTTLER_TEMP_EDGE_BIT    1
>+#define THROTTLER_TEMP_HOTSPOT_BIT 2
>+#define THROTTLER_TEMP_MEM_BIT     3
>+#define THROTTLER_TEMP_VR_GFX_BIT  4
>+#define THROTTLER_TEMP_VR_MEM_BIT  5
>+#define THROTTLER_TEMP_VR_SOC_BIT  6
>+#define THROTTLER_TDC_GFX_BIT      7
>+#define THROTTLER_TDC_SOC_BIT      8
>+#define THROTTLER_PPT0_BIT         9
>+#define THROTTLER_PPT1_BIT         10
>+#define THROTTLER_PPT2_BIT         11
>+#define THROTTLER_PPT3_BIT         12
>+#define THROTTLER_PPM_BIT          13
>+#define THROTTLER_FIT_BIT          14
>+#define THROTTLER_APCC_BIT         15
>+
>+// Table transfer status
>+#define TABLE_TRANSFER_OK         0x0
>+#define TABLE_TRANSFER_FAILED     0xFF
>+#define TABLE_TRANSFER_PENDING    0xAB
>+
>+// Workload bits
>+#define WORKLOAD_PPLIB_DEFAULT_BIT        0
>+#define WORKLOAD_PPLIB_POWER_SAVING_BIT   1
>+#define WORKLOAD_PPLIB_VIDEO_BIT          2
>+#define WORKLOAD_PPLIB_COMPUTE_BIT        3
>+#define WORKLOAD_PPLIB_CUSTOM_BIT         4
>+#define WORKLOAD_PPLIB_COUNT              5
>+
>+//XGMI performance states
>+#define XGMI_STATE_D0 1
>+#define XGMI_STATE_D3 0
>+
>+#define NUM_I2C_CONTROLLERS                8
>+
>+#define I2C_CONTROLLER_ENABLED             1
>+#define I2C_CONTROLLER_DISABLED            0
>+
>+#define MAX_SW_I2C_COMMANDS                8
>+
>+typedef enum {
>+  I2C_CONTROLLER_PORT_0 = 0,  //CKSVII2C0
>+  I2C_CONTROLLER_PORT_1 = 1,  //CKSVII2C1
>+  I2C_CONTROLLER_PORT_COUNT,
>+} I2cControllerPort_e;
>+
>+typedef enum {
>+  I2C_CONTROLLER_NAME_VR_GFX = 0,
>+  I2C_CONTROLLER_NAME_VR_SOC,
>+  I2C_CONTROLLER_NAME_VR_MEM,
>+  I2C_CONTROLLER_NAME_SPARE,
>+  I2C_CONTROLLER_NAME_COUNT,
>+} I2cControllerName_e;
>+
>+typedef enum {
>+  I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
>+  I2C_CONTROLLER_THROTTLER_VR_GFX,
>+  I2C_CONTROLLER_THROTTLER_VR_SOC,
>+  I2C_CONTROLLER_THROTTLER_VR_MEM,
>+  I2C_CONTROLLER_THROTTLER_COUNT,
>+} I2cControllerThrottler_e;
>+
>+typedef enum {
>+  I2C_CONTROLLER_PROTOCOL_VR_0,
>+  I2C_CONTROLLER_PROTOCOL_VR_1,
>+  I2C_CONTROLLER_PROTOCOL_TMP_0,
>+  I2C_CONTROLLER_PROTOCOL_TMP_1,
>+  I2C_CONTROLLER_PROTOCOL_SPARE_0,
>+  I2C_CONTROLLER_PROTOCOL_SPARE_1,
>+  I2C_CONTROLLER_PROTOCOL_COUNT,
>+} I2cControllerProtocol_e;
>+
>+typedef struct {
>+  uint8_t   Enabled;
>+  uint8_t   Speed;
>+  uint8_t   Padding[2];
>+  uint32_t  SlaveAddress;
>+  uint8_t   ControllerPort;
>+  uint8_t   ControllerName;
>+  uint8_t   ThermalThrotter;
>+  uint8_t   I2cProtocol;
>+} I2cControllerConfig_t;
>+
>+typedef enum {
>+  I2C_PORT_SVD_SCL = 0,
>+  I2C_PORT_GPIO,
>+} I2cPort_e;
>+
>+typedef enum {
>+  I2C_SPEED_FAST_50K = 0,      //50  Kbits/s
>+  I2C_SPEED_FAST_100K,         //100 Kbits/s
>+  I2C_SPEED_FAST_400K,         //400 Kbits/s
>+  I2C_SPEED_FAST_PLUS_1M,      //1   Mbits/s (in fast mode)
>+  I2C_SPEED_HIGH_1M,           //1   Mbits/s (in high speed mode)
>+  I2C_SPEED_HIGH_2M,           //2.3 Mbits/s
>+  I2C_SPEED_COUNT,
>+} I2cSpeed_e;
>+
>+typedef enum {
>+  I2C_CMD_READ = 0,
>+  I2C_CMD_WRITE,
>+  I2C_CMD_COUNT,
>+} I2cCmdType_e;
>+
>+#define CMDCONFIG_STOP_BIT      0
>+#define CMDCONFIG_RESTART_BIT   1
>+
>+#define CMDCONFIG_STOP_MASK     (1 << CMDCONFIG_STOP_BIT)
>+#define CMDCONFIG_RESTART_MASK  (1 << CMDCONFIG_RESTART_BIT)
>+
>+typedef struct {
>+  uint8_t RegisterAddr; ////only valid for write, ignored for read
>+  uint8_t Cmd;  //Read(0) or Write(1)
>+  uint8_t Data;  //Return data for read. Data to send for write
>+  uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command
>+} SwI2cCmd_t; //SW I2C Command Table
>+
>+typedef struct {
>+  uint8_t     I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)
>+  uint8_t     I2CSpeed;          //Slow(0) or Fast(1)
>+  uint16_t    SlaveAddress;
>+  uint8_t     NumCmds;           //Number of commands
>+  uint8_t     Padding[3];
>+
>+  SwI2cCmd_t  SwI2cCmds[MAX_SW_I2C_COMMANDS];
>+
>+  uint32_t     MmHubPadding[8]; // SMU internal use
>+
>+} SwI2cRequest_t; // SW I2C Request Table
>+
>+//D3HOT sequences
>+typedef enum {
>+  BACO_SEQUENCE,
>+  MSR_SEQUENCE,
>+  BAMACO_SEQUENCE,
>+  ULPS_SEQUENCE,
>+  D3HOT_SEQUENCE_COUNT,
>+}D3HOTSequence_e;
>+
>+//THis is aligned with RSMU PGFSM Register Mapping
>+typedef enum {
>+  PG_DYNAMIC_MODE = 0,
>+  PG_STATIC_MODE,
>+} PowerGatingMode_e;
>+
>+//This is aligned with RSMU PGFSM Register Mapping
>+typedef enum {
>+  PG_POWER_DOWN = 0,
>+  PG_POWER_UP,
>+} PowerGatingSettings_e;
>+
>+typedef struct {
>+  uint32_t a;  // store in IEEE float format in this variable
>+  uint32_t b;  // store in IEEE float format in this variable
>+  uint32_t c;  // store in IEEE float format in this variable
>+} QuadraticInt_t;
>+
>+typedef struct {
>+  uint32_t m;  // store in IEEE float format in this variable
>+  uint32_t b;  // store in IEEE float format in this variable
>+} LinearInt_t;
>+
>+typedef struct {
>+  uint32_t a;  // store in IEEE float format in this variable
>+  uint32_t b;  // store in IEEE float format in this variable
>+  uint32_t c;  // store in IEEE float format in this variable
>+} DroopInt_t;
>+
>+typedef enum {
>+  GFXCLK_SOURCE_PLL = 0,
>+  GFXCLK_SOURCE_AFLL,
>+  GFXCLK_SOURCE_COUNT,
>+} GfxclkSrc_e;
>+
>+typedef enum {
>+  PPCLK_GFXCLK,
>+  PPCLK_VCLK,
>+  PPCLK_DCLK,
>+  PPCLK_SOCCLK,
>+  PPCLK_UCLK,
>+  PPCLK_FCLK,
>+  PPCLK_COUNT,
>+} PPCLK_e;
>+
>+typedef enum {
>+  POWER_SOURCE_AC,
>+  POWER_SOURCE_DC,
>+  POWER_SOURCE_COUNT,
>+} POWER_SOURCE_e;
>+
>+typedef enum {
>+  TEMP_EDGE,
>+  TEMP_HOTSPOT,
>+  TEMP_MEM,
>+  TEMP_VR_GFX,
>+  TEMP_VR_SOC,
>+  TEMP_VR_MEM,
>+  TEMP_COUNT
>+} TEMP_TYPE_e;
>+
>+typedef enum  {
>+  PPT_THROTTLER_PPT0,
>+  PPT_THROTTLER_PPT1,
>+  PPT_THROTTLER_PPT2,
>+  PPT_THROTTLER_PPT3,
>+  PPT_THROTTLER_COUNT
>+} PPT_THROTTLER_e;
>+
>+typedef enum {
>+  VOLTAGE_MODE_AVFS = 0,
>+  VOLTAGE_MODE_AVFS_SS,
>+  VOLTAGE_MODE_SS,
>+  VOLTAGE_MODE_COUNT,
>+} VOLTAGE_MODE_e;
>+
>+typedef enum {
>+  AVFS_VOLTAGE_GFX = 0,
>+  AVFS_VOLTAGE_SOC,
>+  AVFS_VOLTAGE_COUNT,
>+} AVFS_VOLTAGE_TYPE_e;
>+
>+typedef enum {
>+  GPIO_INT_POLARITY_ACTIVE_LOW = 0,
>+  GPIO_INT_POLARITY_ACTIVE_HIGH,
>+} GpioIntPolarity_e;
>+
>+typedef enum {
>+  MEMORY_TYPE_GDDR6 = 0,
>+  MEMORY_TYPE_HBM,
>+} MemoryType_e;
>+
>+typedef enum {
>+  PWR_CONFIG_TDP = 0,
>+  PWR_CONFIG_TGP,
>+  PWR_CONFIG_TCP_ESTIMATED,
>+  PWR_CONFIG_TCP_MEASURED,
>+} PwrConfig_e;
>+
>+typedef enum {
>+  XGMI_LINK_RATE_12 = 0,  // 12Gbps
>+  XGMI_LINK_RATE_16,      // 16Gbps
>+  XGMI_LINK_RATE_22,      // 22Gbps
>+  XGMI_LINK_RATE_25,      // 25Gbps
>+  XGMI_LINK_RATE_COUNT
>+} XGMI_LINK_RATE_e;
>+
>+typedef enum {
>+  XGMI_LINK_WIDTH_2 = 0, // x2
>+  XGMI_LINK_WIDTH_4,     // x4
>+  XGMI_LINK_WIDTH_8,     // x8
>+  XGMI_LINK_WIDTH_16,    // x16
>+  XGMI_LINK_WIDTH_COUNT
>+} XGMI_LINK_WIDTH_e;
>+
>+typedef struct {
>+  uint8_t        VoltageMode;         // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only
>+  uint8_t        SnapToDiscrete;      // 0 - Fine grained DPM, 1 - Discrete DPM
>+  uint8_t        NumDiscreteLevels;   // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used
>+  uint8_t        padding;
>+  LinearInt_t    ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
>+  QuadraticInt_t SsCurve;             // Slow-slow curve (GHz->V)
>+  uint16_t       SsFmin;              // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin
>+  uint16_t       Padding16;
>+} DpmDescriptor_t;
>+
>+typedef struct {
>+  uint32_t Version;
>+
>+  // SECTION: Feature Enablement
>+  uint32_t FeaturesToRun[2];
>+
>+  // SECTION: Infrastructure Limits
>+  uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT];
>+  uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT];
>+  uint16_t TdcLimitSoc;             // Amps
>+  uint16_t TdcLimitSocTau;          // Time constant of LPF in ms
>+  uint16_t TdcLimitGfx;             // Amps
>+  uint16_t TdcLimitGfxTau;          // Time constant of LPF in ms
>+
>+  uint16_t TedgeLimit;              // Celcius
>+  uint16_t ThotspotLimit;           // Celcius
>+  uint16_t TmemLimit;               // Celcius
>+  uint16_t Tvr_gfxLimit;            // Celcius
>+  uint16_t Tvr_memLimit;            // Celcius
>+  uint16_t Tvr_socLimit;            // Celcius
>+  uint32_t FitLimit;                // Failures in time (failures per million parts over the defined lifetime)
>+
>+  uint16_t PpmPowerLimit;           // Switch this this power limit when temperature is above PpmTempThreshold
>+  uint16_t PpmTemperatureThreshold;
>+
>+  // SECTION: Throttler settings
>+  uint32_t ThrottlerControlMask;   // See Throtter masks defines
>+
>+  // SECTION: ULV Settings
>+  uint16_t  UlvVoltageOffsetGfx; // In mV(Q2)
>+  uint16_t  UlvPadding;          // Padding
>+
>+  uint8_t  UlvGfxclkBypass;  // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV
>+  uint8_t  Padding234[3];
>+
>+  // SECTION: Voltage Control Parameters
>+  uint16_t     MinVoltageGfx;     // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX
>+  uint16_t     MinVoltageSoc;     // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC
>+  uint16_t     MaxVoltageGfx;     // In mV(Q2) Maximum Voltage allowable of VDD_GFX
>+  uint16_t     MaxVoltageSoc;     // In mV(Q2) Maximum Voltage allowable of VDD_SOC
>+
>+  uint16_t     LoadLineResistanceGfx;   // In mOhms with 8 fractional bits
>+  uint16_t     LoadLineResistanceSoc;   // In mOhms with 8 fractional bits
>+
>+  //SECTION: DPM Config 1
>+  DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
>+
>+  uint16_t       FreqTableGfx      [NUM_GFXCLK_DPM_LEVELS  ];     // In MHz
>+  uint16_t       FreqTableVclk     [NUM_VCLK_DPM_LEVELS    ];     // In MHz
>+  uint16_t       FreqTableDclk     [NUM_DCLK_DPM_LEVELS    ];     // In MHz
>+  uint16_t       FreqTableSocclk   [NUM_SOCCLK_DPM_LEVELS  ];     // In MHz
>+  uint16_t       FreqTableUclk     [NUM_UCLK_DPM_LEVELS    ];     // In MHz
>+  uint16_t       FreqTableFclk     [NUM_FCLK_DPM_LEVELS    ];     // In MHz
>+
>+  uint32_t       Paddingclks[16];
>+
>+  // SECTION: DPM Config 2
>+  uint16_t       Mp0clkFreq        [NUM_MP0CLK_DPM_LEVELS];       // in MHz
>+  uint16_t       Mp0DpmVoltage     [NUM_MP0CLK_DPM_LEVELS];       // mV(Q2)
>+
>+  // GFXCLK DPM
>+  uint16_t        GfxclkFidle;          // In MHz
>+  uint16_t        GfxclkSlewRate;       // for PLL babystepping???
>+  uint8_t         Padding567[4];
>+  uint16_t        GfxclkDsMaxFreq;      // In MHz
>+  uint8_t         GfxclkSource;         // 0 = PLL, 1 = AFLL
>+  uint8_t         Padding456;
>+
>+  // GFXCLK Thermal DPM (formerly 'Boost' Settings)
>+  uint16_t     EnableTdpm;
>+  uint16_t     TdpmHighHystTemperature;
>+  uint16_t     TdpmLowHystTemperature;
>+  uint16_t     GfxclkFreqHighTempLimit; // High limit on GFXCLK when temperature is high, for reliability.
>+
>+  // SECTION: Fan Control
>+  uint16_t     FanStopTemp;          //Celcius
>+  uint16_t     FanStartTemp;         //Celcius
>+
>+  uint16_t     FanGainEdge;
>+  uint16_t     FanGainHotspot;
>+  uint16_t     FanGainVrGfx;
>+  uint16_t     FanGainVrSoc;
>+  uint16_t     FanGainVrMem;
>+  uint16_t     FanGainHbm;
>+  uint16_t     FanPwmMin;
>+  uint16_t     FanAcousticLimitRpm;
>+  uint16_t     FanThrottlingRpm;
>+  uint16_t     FanMaximumRpm;
>+  uint16_t     FanTargetTemperature;
>+  uint16_t     FanTargetGfxclk;
>+  uint8_t      FanZeroRpmEnable;
>+  uint8_t      FanTachEdgePerRev;
>+  uint8_t      FanTempInputSelect;
>+  uint8_t      padding8_Fan;
>+
>+  // The following are AFC override parameters. Leave at 0 to use FW defaults.
>+  int16_t      FuzzyFan_ErrorSetDelta;
>+  int16_t      FuzzyFan_ErrorRateSetDelta;
>+  int16_t      FuzzyFan_PwmSetDelta;
>+  uint16_t     FuzzyFan_Reserved;
>+
>+
>+  // SECTION: AVFS
>+  // Overrides
>+  uint8_t           OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
>+  uint8_t           Padding8_Avfs[2];
>+
>+  QuadraticInt_t    qAvfsGb[AVFS_VOLTAGE_COUNT];              // GHz->V Override of fused curve
>+  DroopInt_t        dBtcGbGfxPll;       // GHz->V BtcGb
>+  DroopInt_t        dBtcGbGfxAfll;        // GHz->V BtcGb
>+  DroopInt_t        dBtcGbSoc;            // GHz->V BtcGb
>+  LinearInt_t       qAgingGb[AVFS_VOLTAGE_COUNT];          // GHz->V
>+
>+  QuadraticInt_t    qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V
>+
>+  uint16_t          DcTol[AVFS_VOLTAGE_COUNT];            // mV Q2
>+
>+  uint8_t           DcBtcEnabled[AVFS_VOLTAGE_COUNT];
>+  uint8_t           Padding8_GfxBtc[2];
>+
>+  uint16_t          DcBtcMin[AVFS_VOLTAGE_COUNT];       // mV Q2
>+  uint16_t          DcBtcMax[AVFS_VOLTAGE_COUNT];       // mV Q2
>+
>+  uint16_t          DcBtcGb[AVFS_VOLTAGE_COUNT];        // mV Q2
>+
>+  // SECTION: XGMI
>+  uint8_t           XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low.  0-P0, 1-P1, 2-P2, 3-P3.
>+  uint8_t           XgmiDpmSpare[2];
>+
>+  // Temperature Dependent Vmin
>+  uint16_t     VDDGFX_TVmin;       //Celcius
>+  uint16_t     VDDSOC_TVmin;       //Celcius
>+  uint16_t     VDDGFX_Vmin_HiTemp; // mV Q2
>+  uint16_t     VDDGFX_Vmin_LoTemp; // mV Q2
>+  uint16_t     VDDSOC_Vmin_HiTemp; // mV Q2
>+  uint16_t     VDDSOC_Vmin_LoTemp; // mV Q2
>+
>+  uint16_t     VDDGFX_TVminHystersis; // Celcius
>+  uint16_t     VDDSOC_TVminHystersis; // Celcius
>+
>+
>+  // SECTION: Advanced Options
>+  uint32_t          DebugOverrides;
>+  QuadraticInt_t    ReservedEquation0;
>+  QuadraticInt_t    ReservedEquation1;
>+  QuadraticInt_t    ReservedEquation2;
>+  QuadraticInt_t    ReservedEquation3;
>+
>+  uint16_t     MinVoltageUlvGfx; // In mV(Q2)  Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
>+  uint16_t     PaddingUlv;       // Padding
>+
>+  // Total Power configuration, use defines from PwrConfig_e
>+  uint8_t      TotalPowerConfig;    //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured
>+  uint8_t      TotalPowerSpare1;
>+  uint16_t     TotalPowerSpare2;
>+
>+  // APCC Settings
>+  uint16_t     PccThresholdLow;
>+  uint16_t     PccThresholdHigh;
>+  uint32_t     PaddingAPCC[6];  //FIXME pending SPEC
>+
>+  // SECTION: Reserved
>+  uint32_t     Reserved[11];
>+
>+  // SECTION: BOARD PARAMETERS
>+
>+  // SVI2 Board Parameters
>+  uint16_t     MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
>+  uint16_t     MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
>+
>+  uint8_t      VddGfxVrMapping;     // Use VR_MAPPING* bitfields
>+  uint8_t      VddSocVrMapping;     // Use VR_MAPPING* bitfields
>+  uint8_t      VddMemVrMapping;     // Use VR_MAPPING* bitfields
>+  uint8_t      BoardVrMapping;      // Use VR_MAPPING* bitfields
>+
>+  uint8_t      GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
>+  uint8_t      ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
>+  uint8_t      Padding8_V[2];
>+
>+  // Telemetry Settings
>+  uint16_t     GfxMaxCurrent;   // in Amps
>+  int8_t       GfxOffset;       // in Amps
>+  uint8_t      Padding_TelemetryGfx;
>+
>+  uint16_t     SocMaxCurrent;   // in Amps
>+  int8_t       SocOffset;       // in Amps
>+  uint8_t      Padding_TelemetrySoc;
>+
>+  uint16_t     MemMaxCurrent;   // in Amps
>+  int8_t       MemOffset;       // in Amps
>+  uint8_t      Padding_TelemetryMem;
>+
>+  uint16_t     BoardMaxCurrent;   // in Amps
>+  int8_t       BoardOffset;       // in Amps
>+  uint8_t      Padding_TelemetryBoardInput;
>+
>+  // GPIO Settings
>+  uint8_t      VR0HotGpio;      // GPIO pin configured for VR0 HOT event
>+  uint8_t      VR0HotPolarity;  // GPIO polarity for VR0 HOT event
>+  uint8_t      VR1HotGpio;      // GPIO pin configured for VR1 HOT event
>+  uint8_t      VR1HotPolarity;  // GPIO polarity for VR1 HOT event
>+
>+  // GFXCLK PLL Spread Spectrum
>+  uint8_t      PllGfxclkSpreadEnabled;   // on or off
>+  uint8_t      PllGfxclkSpreadPercent;   // Q4.4
>+  uint16_t     PllGfxclkSpreadFreq;      // kHz
>+
>+  // UCLK Spread Spectrum
>+  uint8_t      UclkSpreadEnabled;   // on or off
>+  uint8_t      UclkSpreadPercent;   // Q4.4
>+  uint16_t     UclkSpreadFreq;      // kHz
>+
>+  // FCLK Spread Spectrum
>+  uint8_t      FclkSpreadEnabled;   // on or off
>+  uint8_t      FclkSpreadPercent;   // Q4.4
>+  uint16_t     FclkSpreadFreq;      // kHz
>+
>+  // GFXCLK Fll Spread Spectrum
>+  uint8_t      FllGfxclkSpreadEnabled;   // on or off
>+  uint8_t      FllGfxclkSpreadPercent;   // Q4.4
>+  uint16_t     FllGfxclkSpreadFreq;      // kHz
>+
>+  // I2C Controller Structure
>+  I2cControllerConfig_t  I2cControllers[NUM_I2C_CONTROLLERS];
>+
>+  // Memory section
>+  uint32_t     MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
>+
>+  uint8_t      DramBitWidth; // For DRAM use only.  See Dram Bit width type defines
>+  uint8_t      PaddingMem[3];
>+
>+  // Total board power
>+  uint16_t     TotalBoardPower;     //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
>+  uint16_t     BoardPadding;
>+
>+  // SECTION: XGMI Training
>+  uint8_t           XgmiLinkSpeed   [NUM_XGMI_PSTATE_LEVELS];
>+  uint8_t           XgmiLinkWidth   [NUM_XGMI_PSTATE_LEVELS];
>+
>+  uint16_t          XgmiFclkFreq    [NUM_XGMI_PSTATE_LEVELS];
>+  uint16_t          XgmiSocVoltage  [NUM_XGMI_PSTATE_LEVELS];
>+
>+  // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
>+  uint8_t      GpioI2cScl;          // Serial Clock
>+  uint8_t      GpioI2cSda;          // Serial Data
>+  uint16_t     GpioPadding;
>+
>+  uint32_t     BoardReserved[9];
>+
>+  // Padding for MMHUB - do not modify this
>+  uint32_t     MmHubPadding[8]; // SMU internal use
>+
>+} PPTable_t;
>+
>+typedef struct {
>+  // Time constant parameters for clock averages in ms
>+  uint16_t     GfxclkAverageLpfTau;
>+  uint16_t     SocclkAverageLpfTau;
>+  uint16_t     UclkAverageLpfTau;
>+  uint16_t     GfxActivityLpfTau;
>+  uint16_t     UclkActivityLpfTau;
>+
>+  uint16_t     SocketPowerLpfTau;
>+
>+  // Padding - ignore
>+  uint32_t     MmHubPadding[8]; // SMU internal use
>+} DriverSmuConfig_t;
>+
>+typedef struct {
>+  uint16_t CurrClock[PPCLK_COUNT];
>+  uint16_t AverageGfxclkFrequency;
>+  uint16_t AverageSocclkFrequency;
>+  uint16_t AverageUclkFrequency  ;
>+  uint16_t AverageGfxActivity    ;
>+  uint16_t AverageUclkActivity   ;
>+  uint8_t  CurrSocVoltageOffset  ;
>+  uint8_t  CurrGfxVoltageOffset  ;
>+  uint8_t  CurrMemVidOffset      ;
>+  uint8_t  Padding8              ;
>+  uint16_t AverageSocketPower    ;
>+  uint16_t TemperatureEdge       ;
>+  uint16_t TemperatureHotspot    ;
>+  uint16_t TemperatureHBM        ;
>+  uint16_t TemperatureVrGfx      ;
>+  uint16_t TemperatureVrSoc      ;
>+  uint16_t TemperatureVrMem      ;
>+  uint32_t ThrottlerStatus       ;
>+
>+  uint16_t CurrFanSpeed          ;
>+  uint16_t Padding16;
>+
>+  uint32_t Padding[4];
>+
>+  // Padding - ignore
>+  uint32_t     MmHubPadding[8]; // SMU internal use
>+} SmuMetrics_t;
>+
>+
>+typedef struct {
>+  uint16_t avgPsmCount[75];
>+  uint16_t minPsmCount[75];
>+  float    avgPsmVoltage[75];
>+  float    minPsmVoltage[75];
>+
>+  uint32_t MmHubPadding[8]; // SMU internal use
>+} AvfsDebugTable_t;
>+
>+typedef struct {
>+  uint8_t  AvfsVersion;
>+  uint8_t  Padding;
>+  uint8_t  AvfsEn[AVFS_VOLTAGE_COUNT];
>+
>+  uint8_t  OverrideVFT[AVFS_VOLTAGE_COUNT];
>+  uint8_t  OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
>+
>+  uint8_t  OverrideTemperatures[AVFS_VOLTAGE_COUNT];
>+  uint8_t  OverrideVInversion[AVFS_VOLTAGE_COUNT];
>+  uint8_t  OverrideP2V[AVFS_VOLTAGE_COUNT];
>+  uint8_t  OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];
>+
>+  int32_t VFT0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
>+  int32_t VFT0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
>+  int32_t VFT0_b[AVFS_VOLTAGE_COUNT];  // Q32
>+
>+  int32_t VFT1_m1[AVFS_VOLTAGE_COUNT]; // Q8.16
>+  int32_t VFT1_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
>+  int32_t VFT1_b[AVFS_VOLTAGE_COUNT];  // Q32
>+
>+  int32_t VFT2_m1[AVFS_VOLTAGE_COUNT]; // Q8.16
>+  int32_t VFT2_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
>+  int32_t VFT2_b[AVFS_VOLTAGE_COUNT];  // Q32
>+
>+  int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
>+  int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
>+  int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT];  // Q32
>+
>+  int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
>+  int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
>+  int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT];  // Q32
>+
>+  uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];
>+  uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];
>+  uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];
>+
>+  uint32_t VInversion[AVFS_VOLTAGE_COUNT]; // in mV with 2 fractional bits
>+
>+
>+  int32_t P2V_m1[AVFS_VOLTAGE_COUNT]; // Q8.24
>+  int32_t P2V_m2[AVFS_VOLTAGE_COUNT]; // Q12.12
>+  int32_t P2V_b[AVFS_VOLTAGE_COUNT];  // Q32
>+
>+  uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units
>+
>+  uint32_t EnabledAvfsModules[2];
>+
>+  uint32_t MmHubPadding[8]; // SMU internal use
>+} AvfsFuseOverride_t;
>+
>+/* NOT CURRENTLY USED
>+typedef struct {
>+  uint8_t   Gfx_ActiveHystLimit;
>+  uint8_t   Gfx_IdleHystLimit;
>+  uint8_t   Gfx_FPS;
>+  uint8_t   Gfx_MinActiveFreqType;
>+  uint8_t   Gfx_BoosterFreqType;
>+  uint8_t   Gfx_MinFreqStep;                // Minimum delta between current and target frequeny in order for FW to change clock.
>+  uint8_t   Gfx_UseRlcBusy;
>+  uint8_t   PaddingGfx[3];
>+  uint16_t  Gfx_MinActiveFreq;              // MHz
>+  uint16_t  Gfx_BoosterFreq;                // MHz
>+  uint16_t  Gfx_PD_Data_time_constant;      // Time constant of PD controller in ms
>+  uint32_t  Gfx_PD_Data_limit_a;            // Q16
>+  uint32_t  Gfx_PD_Data_limit_b;            // Q16
>+  uint32_t  Gfx_PD_Data_limit_c;            // Q16
>+  uint32_t  Gfx_PD_Data_error_coeff;        // Q16
>+  uint32_t  Gfx_PD_Data_error_rate_coeff;   // Q16
>+
>+  uint8_t   Mem_ActiveHystLimit;
>+  uint8_t   Mem_IdleHystLimit;
>+  uint8_t   Mem_FPS;
>+  uint8_t   Mem_MinActiveFreqType;
>+  uint8_t   Mem_BoosterFreqType;
>+  uint8_t   Mem_MinFreqStep;                // Minimum delta between current and target frequeny in order for FW to change clock.
>+  uint8_t   Mem_UseRlcBusy;
>+  uint8_t   PaddingMem[3];
>+  uint16_t  Mem_MinActiveFreq;              // MHz
>+  uint16_t  Mem_BoosterFreq;                // MHz
>+  uint16_t  Mem_PD_Data_time_constant;      // Time constant of PD controller in ms
>+  uint32_t  Mem_PD_Data_limit_a;            // Q16
>+  uint32_t  Mem_PD_Data_limit_b;            // Q16
>+  uint32_t  Mem_PD_Data_limit_c;            // Q16
>+  uint32_t  Mem_PD_Data_error_coeff;        // Q16
>+  uint32_t  Mem_PD_Data_error_rate_coeff;   // Q16
>+
>+  uint32_t  Mem_UpThreshold_Limit;          // Q16
>+  uint8_t   Mem_UpHystLimit;
>+  uint8_t   Mem_DownHystLimit;
>+  uint16_t  Mem_Fps;
>+
>+  uint32_t  MmHubPadding[8]; // SMU internal use
>+} DpmActivityMonitorCoeffInt_t;
>+*/
>+
>+// These defines are used with the following messages:
>+// SMC_MSG_TransferTableDram2Smu
>+// SMC_MSG_TransferTableSmu2Dram
>+#define TABLE_PPTABLE                 0
>+#define TABLE_AVFS                    1
>+#define TABLE_AVFS_PSM_DEBUG          2
>+#define TABLE_AVFS_FUSE_OVERRIDE      3
>+#define TABLE_PMSTATUSLOG             4
>+#define TABLE_SMU_METRICS             5
>+#define TABLE_DRIVER_SMU_CONFIG       6
>+//#define TABLE_ACTIVITY_MONITOR_COEFF  7
>+#define TABLE_OVERDRIVE               7
>+#define TABLE_WAFL_XGMI_TOPOLOGY      8
>+#define TABLE_COUNT                   9
>+
>+// These defines are used with the SMC_MSG_SetUclkFastSwitch message.
>+typedef enum {
>+  DF_SWITCH_TYPE_FAST = 0,
>+  DF_SWITCH_TYPE_SLOW,
>+  DF_SWITCH_TYPE_COUNT,
>+} DF_SWITCH_TYPE_e;
>+
>+typedef enum {
>+  DRAM_BIT_WIDTH_DISABLED = 0,
>+  DRAM_BIT_WIDTH_X_8,
>+  DRAM_BIT_WIDTH_X_16,
>+  DRAM_BIT_WIDTH_X_32,
>+  DRAM_BIT_WIDTH_X_64, // NOT USED.
>+  DRAM_BIT_WIDTH_X_128,
>+  DRAM_BIT_WIDTH_COUNT,
>+} DRAM_BIT_WIDTH_TYPE_e;
>+
>+#define REMOVE_FMAX_MARGIN_BIT     0x0
>+#define REMOVE_DCTOL_MARGIN_BIT    0x1
>+#define REMOVE_PLATFORM_MARGIN_BIT 0x2
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h	2019-08-31 15:01:11.938736175 -0500
>@@ -27,7 +27,9 @@
> // *** IMPORTANT ***
> // SMU TEAM: Always increment the interface version if
> // any structure is changed in this file
>-#define SMU11_DRIVER_IF_VERSION 0x13
>+// Be aware of that the version should be updated in
>+// smu_v11_0.h, rename is also needed.
>+// #define SMU11_DRIVER_IF_VERSION 0x13
> 
> #define PPTABLE_V20_SMU_VERSION 3
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h	2019-08-31 15:01:11.938736175 -0500
>@@ -26,7 +26,9 @@
> // *** IMPORTANT ***
> // SMU TEAM: Always increment the interface version if 
> // any structure is changed in this file
>-#define SMU11_DRIVER_IF_VERSION 0x33
>+// Be aware of that the version should be updated in
>+// smu_v11_0.h, maybe rename is also needed.
>+// #define SMU11_DRIVER_IF_VERSION 0x33
> 
> #define PPTABLE_NV10_SMU_VERSION 8
> 
>@@ -504,10 +506,11 @@
>   uint32_t Status;
> 
>   uint16_t DieTemperature;
>-  uint16_t MemoryTemperature;
>+  uint16_t CurrentMemoryTemperature;
> 
>-  uint16_t SelectedCardPower;
>-  uint16_t Reserved4; 
>+  uint16_t MemoryTemperature;
>+  uint8_t MemoryHotspotPosition;
>+  uint8_t Reserved4;
> 
>   uint32_t BoardLevelEnergyAccumulator;  
> } OutOfBandMonitor_t;
>@@ -799,7 +802,12 @@
>   // Mvdd Svi2 Div Ratio Setting
>   uint32_t     MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
> 
>-  uint32_t     BoardReserved[9];
>+  uint8_t      RenesesLoadLineEnabled;
>+  uint8_t      GfxLoadlineResistance;
>+  uint8_t      SocLoadlineResistance;
>+  uint8_t      Padding8_Loadline;
>+
>+  uint32_t     BoardReserved[8];
> 
>   // Padding for MMHUB - do not modify this
>   uint32_t     MmHubPadding[8]; // SMU internal use
>@@ -903,13 +911,22 @@
> } Watermarks_t;
> 
> typedef struct {
>+  uint16_t avgPsmCount[28];
>+  uint16_t minPsmCount[28];
>+  float    avgPsmVoltage[28];
>+  float    minPsmVoltage[28];
>+
>+  uint32_t     MmHubPadding[32]; // SMU internal use
>+} AvfsDebugTable_t_NV14;
>+
>+typedef struct {
>   uint16_t avgPsmCount[36];
>   uint16_t minPsmCount[36];
>   float    avgPsmVoltage[36]; 
>   float    minPsmVoltage[36];
> 
>   uint32_t     MmHubPadding[8]; // SMU internal use
>-} AvfsDebugTable_t;
>+} AvfsDebugTable_t_NV10;
> 
> typedef struct {
>   uint8_t  AvfsVersion;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu12_driver_if.h	2019-08-31 15:01:11.938736175 -0500
>@@ -0,0 +1,217 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef SMU12_DRIVER_IF_H
>+#define SMU12_DRIVER_IF_H
>+
>+// *** IMPORTANT ***
>+// SMU TEAM: Always increment the interface version if 
>+// any structure is changed in this file
>+#define SMU12_DRIVER_IF_VERSION 10
>+
>+typedef struct {
>+  int32_t value;
>+  uint32_t numFractionalBits;
>+} FloatInIntFormat_t;
>+
>+typedef enum {
>+  DSPCLK_DCFCLK = 0,
>+  DSPCLK_DISPCLK,
>+  DSPCLK_PIXCLK,
>+  DSPCLK_PHYCLK,
>+  DSPCLK_COUNT,
>+} DSPCLK_e;
>+
>+typedef struct {
>+  uint16_t Freq; // in MHz
>+  uint16_t Vid;  // min voltage in SVI2 VID
>+} DisplayClockTable_t;
>+
>+typedef struct {
>+  uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
>+  uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
>+  uint16_t MinMclk;
>+  uint16_t MaxMclk;
>+
>+  uint8_t  WmSetting;
>+  uint8_t  WmType;  // Used for normal pstate change or memory retraining
>+  uint8_t  Padding[2];
>+} WatermarkRowGeneric_t;
>+
>+#define NUM_WM_RANGES 4
>+#define WM_PSTATE_CHG 0
>+#define WM_RETRAINING 1
>+
>+typedef enum {
>+  WM_SOCCLK = 0,
>+  WM_DCFCLK,
>+  WM_COUNT,
>+} WM_CLOCK_e;
>+
>+typedef struct {
>+  // Watermarks
>+  WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
>+
>+  uint32_t     MmHubPadding[7]; // SMU internal use
>+} Watermarks_t;
>+
>+typedef enum {
>+  CUSTOM_DPM_SETTING_GFXCLK,
>+  CUSTOM_DPM_SETTING_CCLK,
>+  CUSTOM_DPM_SETTING_FCLK_CCX,
>+  CUSTOM_DPM_SETTING_FCLK_GFX,
>+  CUSTOM_DPM_SETTING_FCLK_STALLS,
>+  CUSTOM_DPM_SETTING_LCLK,
>+  CUSTOM_DPM_SETTING_COUNT,
>+} CUSTOM_DPM_SETTING_e;
>+
>+typedef struct {
>+  uint8_t             ActiveHystLimit;
>+  uint8_t             IdleHystLimit;
>+  uint8_t             FPS;
>+  uint8_t             MinActiveFreqType;
>+  FloatInIntFormat_t  MinActiveFreq;
>+  FloatInIntFormat_t  PD_Data_limit;
>+  FloatInIntFormat_t  PD_Data_time_constant;
>+  FloatInIntFormat_t  PD_Data_error_coeff;
>+  FloatInIntFormat_t  PD_Data_error_rate_coeff;
>+} DpmActivityMonitorCoeffExt_t;
>+
>+typedef struct {
>+  DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
>+} CustomDpmSettings_t;
>+
>+
>+#define NUM_DCFCLK_DPM_LEVELS 8
>+#define NUM_SOCCLK_DPM_LEVELS 8
>+#define NUM_FCLK_DPM_LEVELS   4
>+#define NUM_MEMCLK_DPM_LEVELS 4
>+#define NUM_VCN_DPM_LEVELS    8
>+
>+typedef struct {
>+  uint32_t Freq;    // In MHz
>+  uint32_t Vol;     // Millivolts with 2 fractional bits
>+} DpmClock_t;
>+
>+typedef struct {
>+  DpmClock_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
>+  DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
>+  DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
>+  DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS];
>+  DpmClock_t VClocks[NUM_VCN_DPM_LEVELS];
>+  DpmClock_t DClocks[NUM_VCN_DPM_LEVELS];
>+
>+  uint8_t NumDcfClkDpmEnabled;
>+  uint8_t NumSocClkDpmEnabled;
>+  uint8_t NumFClkDpmEnabled;
>+  uint8_t NumMemClkDpmEnabled;
>+  uint8_t NumVClkDpmEnabled;
>+  uint8_t NumDClkDpmEnabled;
>+  uint8_t spare[2];
>+} DpmClocks_t;
>+
>+
>+typedef enum {
>+  CLOCK_SMNCLK = 0,
>+  CLOCK_SOCCLK,
>+  CLOCK_MP0CLK,
>+  CLOCK_MP1CLK,
>+  CLOCK_MP2CLK,
>+  CLOCK_VCLK,
>+  CLOCK_LCLK,
>+  CLOCK_DCLK,
>+  CLOCK_ACLK,
>+  CLOCK_ISPCLK,
>+  CLOCK_SHUBCLK,
>+  CLOCK_DISPCLK,
>+  CLOCK_DPPCLK,
>+  CLOCK_DPREFCLK,
>+  CLOCK_DCFCLK,
>+  CLOCK_FCLK,
>+  CLOCK_UMCCLK,
>+  CLOCK_GFXCLK,
>+  CLOCK_COUNT,
>+} CLOCK_IDs_e;
>+
>+// Throttler Status Bitmask
>+#define THROTTLER_STATUS_BIT_SPL        0
>+#define THROTTLER_STATUS_BIT_FPPT       1
>+#define THROTTLER_STATUS_BIT_SPPT       2
>+#define THROTTLER_STATUS_BIT_SPPT_APU   3
>+#define THROTTLER_STATUS_BIT_THM_CORE   4
>+#define THROTTLER_STATUS_BIT_THM_GFX    5
>+#define THROTTLER_STATUS_BIT_THM_SOC    6
>+#define THROTTLER_STATUS_BIT_TDC_VDD    7
>+#define THROTTLER_STATUS_BIT_TDC_SOC    8
>+
>+typedef struct {
>+  uint16_t ClockFrequency[CLOCK_COUNT]; //[MHz]
>+
>+  uint16_t AverageGfxclkFrequency;      //[MHz]
>+  uint16_t AverageSocclkFrequency;      //[MHz]
>+  uint16_t AverageVclkFrequency;        //[MHz]
>+  uint16_t AverageFclkFrequency;        //[MHz]
>+
>+  uint16_t AverageGfxActivity;          //[centi]
>+  uint16_t AverageUvdActivity;          //[centi]
>+
>+  uint16_t Voltage[2];                  //[mV] indices: VDDCR_VDD, VDDCR_SOC
>+  uint16_t Current[2];                  //[mA] indices: VDDCR_VDD, VDDCR_SOC
>+  uint16_t Power[2];                    //[mW] indices: VDDCR_VDD, VDDCR_SOC
>+
>+  uint16_t FanPwm;                      //[milli]
>+  uint16_t CurrentSocketPower;          //[mW]
>+
>+  uint16_t CoreFrequency[8];            //[MHz]
>+  uint16_t CorePower[8];                //[mW]
>+  uint16_t CoreTemperature[8];          //[centi-Celsius]
>+  uint16_t L3Frequency[2];              //[MHz]
>+  uint16_t L3Temperature[2];            //[centi-Celsius]
>+
>+  uint16_t GfxTemperature;              //[centi-Celsius]
>+  uint16_t SocTemperature;              //[centi-Celsius]
>+  uint16_t ThrottlerStatus;
>+  uint16_t spare;
>+} SmuMetrics_t;
>+
>+
>+// Workload bits
>+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
>+#define WORKLOAD_PPLIB_VIDEO_BIT          2
>+#define WORKLOAD_PPLIB_VR_BIT             3
>+#define WORKLOAD_PPLIB_COMPUTE_BIT        4
>+#define WORKLOAD_PPLIB_CUSTOM_BIT         5
>+#define WORKLOAD_PPLIB_COUNT              6
>+
>+#define TABLE_BIOS_IF            0 // Called by BIOS
>+#define TABLE_WATERMARKS         1 // Called by Driver
>+#define TABLE_CUSTOM_DPM         2 // Called by Driver
>+#define TABLE_SPARE1             3
>+#define TABLE_DPMCLOCKS          4 // Called by Driver
>+#define TABLE_MOMENTARY_PM       5 // Called by Tools
>+#define TABLE_MODERN_STDBY       6 // Called by Tools for Modern Standby Log
>+#define TABLE_SMU_METRICS        7 // Called by Driver
>+#define TABLE_COUNT              8
>+
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu_types.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu_types.h	2019-08-31 15:01:11.938736175 -0500
>@@ -0,0 +1,263 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+
>+#ifndef __SMU_TYPES_H__
>+#define __SMU_TYPES_H__
>+
>+#define SMU_MESSAGE_TYPES			      \
>+       __SMU_DUMMY_MAP(TestMessage),		      \
>+       __SMU_DUMMY_MAP(GetSmuVersion),                \
>+       __SMU_DUMMY_MAP(GetDriverIfVersion),           \
>+       __SMU_DUMMY_MAP(SetAllowedFeaturesMaskLow),    \
>+       __SMU_DUMMY_MAP(SetAllowedFeaturesMaskHigh),   \
>+       __SMU_DUMMY_MAP(EnableAllSmuFeatures),         \
>+       __SMU_DUMMY_MAP(DisableAllSmuFeatures),        \
>+       __SMU_DUMMY_MAP(EnableSmuFeaturesLow),         \
>+       __SMU_DUMMY_MAP(EnableSmuFeaturesHigh),        \
>+       __SMU_DUMMY_MAP(DisableSmuFeaturesLow),        \
>+       __SMU_DUMMY_MAP(DisableSmuFeaturesHigh),       \
>+       __SMU_DUMMY_MAP(GetEnabledSmuFeaturesLow),     \
>+       __SMU_DUMMY_MAP(GetEnabledSmuFeaturesHigh),    \
>+       __SMU_DUMMY_MAP(SetWorkloadMask),              \
>+       __SMU_DUMMY_MAP(SetPptLimit),                  \
>+       __SMU_DUMMY_MAP(SetDriverDramAddrHigh),        \
>+       __SMU_DUMMY_MAP(SetDriverDramAddrLow),         \
>+       __SMU_DUMMY_MAP(SetToolsDramAddrHigh),         \
>+       __SMU_DUMMY_MAP(SetToolsDramAddrLow),          \
>+       __SMU_DUMMY_MAP(TransferTableSmu2Dram),        \
>+       __SMU_DUMMY_MAP(TransferTableDram2Smu),        \
>+       __SMU_DUMMY_MAP(UseDefaultPPTable),            \
>+       __SMU_DUMMY_MAP(UseBackupPPTable),             \
>+       __SMU_DUMMY_MAP(RunBtc),                       \
>+       __SMU_DUMMY_MAP(RequestI2CBus),                \
>+       __SMU_DUMMY_MAP(ReleaseI2CBus),                \
>+       __SMU_DUMMY_MAP(SetFloorSocVoltage),           \
>+       __SMU_DUMMY_MAP(SoftReset),                    \
>+       __SMU_DUMMY_MAP(StartBacoMonitor),             \
>+       __SMU_DUMMY_MAP(CancelBacoMonitor),            \
>+       __SMU_DUMMY_MAP(EnterBaco),                    \
>+       __SMU_DUMMY_MAP(SetSoftMinByFreq),             \
>+       __SMU_DUMMY_MAP(SetSoftMaxByFreq),             \
>+       __SMU_DUMMY_MAP(SetHardMinByFreq),             \
>+       __SMU_DUMMY_MAP(SetHardMaxByFreq),             \
>+       __SMU_DUMMY_MAP(GetMinDpmFreq),                \
>+       __SMU_DUMMY_MAP(GetMaxDpmFreq),                \
>+       __SMU_DUMMY_MAP(GetDpmFreqByIndex),            \
>+       __SMU_DUMMY_MAP(GetDpmClockFreq),              \
>+       __SMU_DUMMY_MAP(GetSsVoltageByDpm),            \
>+       __SMU_DUMMY_MAP(SetMemoryChannelConfig),       \
>+       __SMU_DUMMY_MAP(SetGeminiMode),                \
>+       __SMU_DUMMY_MAP(SetGeminiApertureHigh),        \
>+       __SMU_DUMMY_MAP(SetGeminiApertureLow),         \
>+       __SMU_DUMMY_MAP(SetMinLinkDpmByIndex),         \
>+       __SMU_DUMMY_MAP(OverridePcieParameters),       \
>+       __SMU_DUMMY_MAP(OverDriveSetPercentage),       \
>+       __SMU_DUMMY_MAP(SetMinDeepSleepDcefclk),       \
>+       __SMU_DUMMY_MAP(ReenableAcDcInterrupt),        \
>+       __SMU_DUMMY_MAP(NotifyPowerSource),            \
>+       __SMU_DUMMY_MAP(SetUclkFastSwitch),            \
>+       __SMU_DUMMY_MAP(SetUclkDownHyst),              \
>+       __SMU_DUMMY_MAP(GfxDeviceDriverReset),         \
>+       __SMU_DUMMY_MAP(GetCurrentRpm),                \
>+       __SMU_DUMMY_MAP(SetVideoFps),                  \
>+       __SMU_DUMMY_MAP(SetTjMax),                     \
>+       __SMU_DUMMY_MAP(SetFanTemperatureTarget),      \
>+       __SMU_DUMMY_MAP(PrepareMp1ForUnload),          \
>+       __SMU_DUMMY_MAP(DramLogSetDramAddrHigh),       \
>+       __SMU_DUMMY_MAP(DramLogSetDramAddrLow),        \
>+       __SMU_DUMMY_MAP(DramLogSetDramSize),           \
>+       __SMU_DUMMY_MAP(SetFanMaxRpm),                 \
>+       __SMU_DUMMY_MAP(SetFanMinPwm),                 \
>+       __SMU_DUMMY_MAP(ConfigureGfxDidt),             \
>+       __SMU_DUMMY_MAP(NumOfDisplays),                \
>+       __SMU_DUMMY_MAP(RemoveMargins),                \
>+       __SMU_DUMMY_MAP(ReadSerialNumTop32),           \
>+       __SMU_DUMMY_MAP(ReadSerialNumBottom32),        \
>+       __SMU_DUMMY_MAP(SetSystemVirtualDramAddrHigh), \
>+       __SMU_DUMMY_MAP(SetSystemVirtualDramAddrLow),  \
>+       __SMU_DUMMY_MAP(WaflTest),                     \
>+       __SMU_DUMMY_MAP(SetFclkGfxClkRatio),           \
>+       __SMU_DUMMY_MAP(AllowGfxOff),                  \
>+       __SMU_DUMMY_MAP(DisallowGfxOff),               \
>+       __SMU_DUMMY_MAP(GetPptLimit),                  \
>+       __SMU_DUMMY_MAP(GetDcModeMaxDpmFreq),          \
>+       __SMU_DUMMY_MAP(GetDebugData),                 \
>+       __SMU_DUMMY_MAP(SetXgmiMode),                  \
>+       __SMU_DUMMY_MAP(RunAfllBtc),                   \
>+       __SMU_DUMMY_MAP(ExitBaco),                     \
>+       __SMU_DUMMY_MAP(PrepareMp1ForReset),           \
>+       __SMU_DUMMY_MAP(PrepareMp1ForShutdown),        \
>+       __SMU_DUMMY_MAP(SetMGpuFanBoostLimitRpm),      \
>+       __SMU_DUMMY_MAP(GetAVFSVoltageByDpm),          \
>+       __SMU_DUMMY_MAP(PowerUpVcn),                   \
>+       __SMU_DUMMY_MAP(PowerDownVcn),                 \
>+       __SMU_DUMMY_MAP(PowerUpJpeg),                  \
>+       __SMU_DUMMY_MAP(PowerDownJpeg),                \
>+       __SMU_DUMMY_MAP(BacoAudioD3PME),               \
>+       __SMU_DUMMY_MAP(ArmD3),                        \
>+       __SMU_DUMMY_MAP(RunGfxDcBtc),                  \
>+       __SMU_DUMMY_MAP(RunSocDcBtc),                  \
>+       __SMU_DUMMY_MAP(SetMemoryChannelEnable),       \
>+       __SMU_DUMMY_MAP(SetDfSwitchType),              \
>+       __SMU_DUMMY_MAP(GetVoltageByDpm),              \
>+       __SMU_DUMMY_MAP(GetVoltageByDpmOverdrive),     \
>+       __SMU_DUMMY_MAP(PowerUpVcn0),                  \
>+       __SMU_DUMMY_MAP(PowerDownVcn0),               \
>+       __SMU_DUMMY_MAP(PowerUpVcn1),                  \
>+       __SMU_DUMMY_MAP(PowerDownVcn1),                \
>+       __SMU_DUMMY_MAP(PowerUpGfx),                   \
>+       __SMU_DUMMY_MAP(PowerDownIspByTile),           \
>+       __SMU_DUMMY_MAP(PowerUpIspByTile),             \
>+       __SMU_DUMMY_MAP(PowerDownSdma),                \
>+	__SMU_DUMMY_MAP(PowerUpSdma),                 \
>+	__SMU_DUMMY_MAP(SetHardMinIspclkByFreq),      \
>+	__SMU_DUMMY_MAP(SetHardMinVcn),               \
>+	__SMU_DUMMY_MAP(Spare1),                      \
>+	__SMU_DUMMY_MAP(Spare2),           	      \
>+	__SMU_DUMMY_MAP(SetAllowFclkSwitch),          \
>+	__SMU_DUMMY_MAP(SetMinVideoGfxclkFreq),       \
>+	__SMU_DUMMY_MAP(ActiveProcessNotify),         \
>+	__SMU_DUMMY_MAP(SetCustomPolicy),             \
>+	__SMU_DUMMY_MAP(QueryPowerLimit),             \
>+	__SMU_DUMMY_MAP(SetGfxclkOverdriveByFreqVid), \
>+	__SMU_DUMMY_MAP(SetHardMinDcfclkByFreq),      \
>+	__SMU_DUMMY_MAP(SetHardMinSocclkByFreq),      \
>+	__SMU_DUMMY_MAP(ControlIgpuATS),              \
>+	__SMU_DUMMY_MAP(SetMinVideoFclkFreq),         \
>+	__SMU_DUMMY_MAP(SetMinDeepSleepDcfclk),       \
>+	__SMU_DUMMY_MAP(ForcePowerDownGfx),           \
>+	__SMU_DUMMY_MAP(SetPhyclkVoltageByFreq),      \
>+	__SMU_DUMMY_MAP(SetDppclkVoltageByFreq),      \
>+	__SMU_DUMMY_MAP(SetSoftMinVcn),               \
>+	__SMU_DUMMY_MAP(EnablePostCode),              \
>+	__SMU_DUMMY_MAP(GetGfxclkFrequency),          \
>+	__SMU_DUMMY_MAP(GetFclkFrequency),            \
>+	__SMU_DUMMY_MAP(GetMinGfxclkFrequency),       \
>+	__SMU_DUMMY_MAP(GetMaxGfxclkFrequency),       \
>+	__SMU_DUMMY_MAP(SetGfxCGPG),                  \
>+	__SMU_DUMMY_MAP(SetSoftMaxGfxClk),            \
>+	__SMU_DUMMY_MAP(SetHardMinGfxClk),            \
>+	__SMU_DUMMY_MAP(SetSoftMaxSocclkByFreq),      \
>+	__SMU_DUMMY_MAP(SetSoftMaxFclkByFreq),        \
>+	__SMU_DUMMY_MAP(SetSoftMaxVcn),               \
>+	__SMU_DUMMY_MAP(PowerGateMmHub),              \
>+	__SMU_DUMMY_MAP(UpdatePmeRestore),            \
>+	__SMU_DUMMY_MAP(GpuChangeState),              \
>+	__SMU_DUMMY_MAP(SetPowerLimitPercentage),     \
>+	__SMU_DUMMY_MAP(ForceGfxContentSave),         \
>+	__SMU_DUMMY_MAP(EnableTmdp48MHzRefclkPwrDown), \
>+	__SMU_DUMMY_MAP(PowerGateAtHub),              \
>+	__SMU_DUMMY_MAP(SetSoftMinJpeg),              \
>+	__SMU_DUMMY_MAP(SetHardMinFclkByFreq),        \
>+
>+#undef __SMU_DUMMY_MAP
>+#define __SMU_DUMMY_MAP(type)	SMU_MSG_##type
>+enum smu_message_type {
>+	SMU_MESSAGE_TYPES
>+	SMU_MSG_MAX_COUNT,
>+};
>+
>+enum smu_clk_type {
>+	SMU_GFXCLK,
>+	SMU_VCLK,
>+	SMU_DCLK,
>+	SMU_ECLK,
>+	SMU_SOCCLK,
>+	SMU_UCLK,
>+	SMU_DCEFCLK,
>+	SMU_DISPCLK,
>+	SMU_PIXCLK,
>+	SMU_PHYCLK,
>+	SMU_FCLK,
>+	SMU_SCLK,
>+	SMU_MCLK,
>+	SMU_PCIE,
>+	SMU_OD_SCLK,
>+	SMU_OD_MCLK,
>+	SMU_OD_VDDC_CURVE,
>+	SMU_OD_RANGE,
>+	SMU_CLK_COUNT,
>+};
>+
>+#define SMU_FEATURE_MASKS				\
>+       __SMU_DUMMY_MAP(DPM_PREFETCHER),			\
>+       __SMU_DUMMY_MAP(DPM_GFXCLK),                    	\
>+       __SMU_DUMMY_MAP(DPM_UCLK),                      	\
>+       __SMU_DUMMY_MAP(DPM_SOCCLK),                    	\
>+       __SMU_DUMMY_MAP(DPM_UVD),                       	\
>+       __SMU_DUMMY_MAP(DPM_VCE),                       	\
>+       __SMU_DUMMY_MAP(ULV),                           	\
>+       __SMU_DUMMY_MAP(DPM_MP0CLK),                    	\
>+       __SMU_DUMMY_MAP(DPM_LINK),                      	\
>+       __SMU_DUMMY_MAP(DPM_DCEFCLK),                   	\
>+       __SMU_DUMMY_MAP(DS_GFXCLK),                     	\
>+       __SMU_DUMMY_MAP(DS_SOCCLK),                     	\
>+       __SMU_DUMMY_MAP(DS_LCLK),                       	\
>+       __SMU_DUMMY_MAP(PPT),                           	\
>+       __SMU_DUMMY_MAP(TDC),                           	\
>+       __SMU_DUMMY_MAP(THERMAL),                       	\
>+       __SMU_DUMMY_MAP(GFX_PER_CU_CG),                 	\
>+       __SMU_DUMMY_MAP(RM),                            	\
>+       __SMU_DUMMY_MAP(DS_DCEFCLK),                    	\
>+       __SMU_DUMMY_MAP(ACDC),                          	\
>+       __SMU_DUMMY_MAP(VR0HOT),                        	\
>+       __SMU_DUMMY_MAP(VR1HOT),                        	\
>+       __SMU_DUMMY_MAP(FW_CTF),                        	\
>+       __SMU_DUMMY_MAP(LED_DISPLAY),                   	\
>+       __SMU_DUMMY_MAP(FAN_CONTROL),                   	\
>+       __SMU_DUMMY_MAP(GFX_EDC),                       	\
>+       __SMU_DUMMY_MAP(GFXOFF),                        	\
>+       __SMU_DUMMY_MAP(CG),                            	\
>+       __SMU_DUMMY_MAP(DPM_FCLK),                      	\
>+       __SMU_DUMMY_MAP(DS_FCLK),                       	\
>+       __SMU_DUMMY_MAP(DS_MP1CLK),                     	\
>+       __SMU_DUMMY_MAP(DS_MP0CLK),                     	\
>+       __SMU_DUMMY_MAP(XGMI),                          	\
>+       __SMU_DUMMY_MAP(DPM_GFX_PACE),                  	\
>+       __SMU_DUMMY_MAP(MEM_VDDCI_SCALING),             	\
>+       __SMU_DUMMY_MAP(MEM_MVDD_SCALING),              	\
>+       __SMU_DUMMY_MAP(DS_UCLK),                       	\
>+       __SMU_DUMMY_MAP(GFX_ULV),                       	\
>+       __SMU_DUMMY_MAP(FW_DSTATE),                     	\
>+       __SMU_DUMMY_MAP(BACO),                          	\
>+       __SMU_DUMMY_MAP(VCN_PG),                        	\
>+       __SMU_DUMMY_MAP(JPEG_PG),                       	\
>+       __SMU_DUMMY_MAP(USB_PG),                        	\
>+       __SMU_DUMMY_MAP(RSMU_SMN_CG),                   	\
>+       __SMU_DUMMY_MAP(APCC_PLUS),                     	\
>+       __SMU_DUMMY_MAP(GTHR),                          	\
>+       __SMU_DUMMY_MAP(GFX_DCS),                       	\
>+       __SMU_DUMMY_MAP(GFX_SS),                        	\
>+       __SMU_DUMMY_MAP(OUT_OF_BAND_MONITOR),           	\
>+       __SMU_DUMMY_MAP(TEMP_DEPENDENT_VMIN),           	\
>+       __SMU_DUMMY_MAP(MMHUB_PG),                      	\
>+       __SMU_DUMMY_MAP(ATHUB_PG),                      	\
>+       __SMU_DUMMY_MAP(WAFL_CG),
>+
>+#undef __SMU_DUMMY_MAP
>+#define __SMU_DUMMY_MAP(feature)	SMU_FEATURE_##feature##_BIT
>+enum smu_feature_mask {
>+	SMU_FEATURE_MASKS
>+	SMU_FEATURE_COUNT,
>+};
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h	2019-08-31 15:01:11.938736175 -0500
>@@ -25,6 +25,12 @@
> 
> #include "amdgpu_smu.h"
> 
>+#define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
>+#define SMU11_DRIVER_IF_VERSION_VG20 0x13
>+#define SMU11_DRIVER_IF_VERSION_ARCT 0x09
>+#define SMU11_DRIVER_IF_VERSION_NV10 0x33
>+#define SMU11_DRIVER_IF_VERSION_NV14 0x34
>+
> /* MP Apertures */
> #define MP0_Public			0x03800000
> #define MP0_SRAM			0x03900000
>@@ -43,19 +49,30 @@
> #define SMU11_TOOL_SIZE			0x19000
> 
> #define CLK_MAP(clk, index) \
>-	[SMU_##clk] = index
>+	[SMU_##clk] = {1, (index)}
> 
> #define FEA_MAP(fea) \
>-	[SMU_FEATURE_##fea##_BIT] = FEATURE_##fea##_BIT
>+	[SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
> 
> #define TAB_MAP(tab) \
>-	[SMU_TABLE_##tab] = TABLE_##tab
>+	[SMU_TABLE_##tab] = {1, TABLE_##tab}
> 
> #define PWR_MAP(tab) \
>-	[SMU_POWER_SOURCE_##tab] = POWER_SOURCE_##tab
>+	[SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
> 
> #define WORKLOAD_MAP(profile, workload) \
>-	[profile] = workload
>+	[profile] = {1, (workload)}
>+
>+static const struct smu_temperature_range smu11_thermal_policy[] =
>+{
>+	{-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
>+	{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
>+};
>+
>+struct smu_11_0_cmn2aisc_mapping {
>+	int	valid_mapping;
>+	int	map_to;
>+};
> 
> struct smu_11_0_max_sustainable_clocks {
> 	uint32_t display_clock;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h	2019-08-31 15:01:11.938736175 -0500
>@@ -0,0 +1,42 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#ifndef __SMU_V12_0_H__
>+#define __SMU_V12_0_H__
>+
>+#include "amdgpu_smu.h"
>+
>+/* MP Apertures */
>+#define MP0_Public			0x03800000
>+#define MP0_SRAM			0x03900000
>+#define MP1_Public			0x03b00000
>+#define MP1_SRAM			0x03c00004
>+
>+
>+struct smu_12_0_cmn2aisc_mapping {
>+	int	valid_mapping;
>+	int	map_to;
>+};
>+
>+void smu_v12_0_set_smu_funcs(struct smu_context *smu);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0_ppsmc.h	2019-08-31 15:01:11.938736175 -0500
>@@ -0,0 +1,106 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef SMU_12_0_PPSMC_H
>+#define SMU_12_0_PPSMC_H
>+
>+// SMU Response Codes:
>+#define PPSMC_Result_OK                    0x1
>+#define PPSMC_Result_Failed                0xFF
>+#define PPSMC_Result_UnknownCmd            0xFE
>+#define PPSMC_Result_CmdRejectedPrereq     0xFD
>+#define PPSMC_Result_CmdRejectedBusy       0xFC
>+
>+
>+// Message Definitions:
>+#define PPSMC_MSG_TestMessage                   0x1
>+#define PPSMC_MSG_GetSmuVersion                 0x2
>+#define PPSMC_MSG_GetDriverIfVersion            0x3
>+#define PPSMC_MSG_PowerUpGfx                    0x6
>+#define PPSMC_MSG_EnableGfxOff                  0x7
>+#define PPSMC_MSG_DisableGfxOff                 0x8
>+#define PPSMC_MSG_PowerDownIspByTile            0x9 // ISP is power gated by default
>+#define PPSMC_MSG_PowerUpIspByTile              0xA
>+#define PPSMC_MSG_PowerDownVcn                  0xB // VCN is power gated by default
>+#define PPSMC_MSG_PowerUpVcn                    0xC
>+#define PPSMC_MSG_PowerDownSdma                 0xD // SDMA is power gated by default
>+#define PPSMC_MSG_PowerUpSdma                   0xE
>+#define PPSMC_MSG_SetHardMinIspclkByFreq        0xF
>+#define PPSMC_MSG_SetHardMinVcn                 0x10 // For wireless display
>+#define PPSMC_MSG_spare1                        0x11
>+#define PPSMC_MSG_spare2                        0x12
>+#define PPSMC_MSG_SetAllowFclkSwitch            0x13
>+#define PPSMC_MSG_SetMinVideoGfxclkFreq         0x14
>+#define PPSMC_MSG_ActiveProcessNotify           0x15
>+#define PPSMC_MSG_SetCustomPolicy               0x16
>+#define PPSMC_MSG_SetVideoFps                   0x17
>+#define PPSMC_MSG_SetDisplayCount               0x18 // Moved to VBIOS
>+#define PPSMC_MSG_QueryPowerLimit               0x19 //Driver to look up sustainable clocks for VQ
>+#define PPSMC_MSG_SetDriverDramAddrHigh         0x1A
>+#define PPSMC_MSG_SetDriverDramAddrLow          0x1B
>+#define PPSMC_MSG_TransferTableSmu2Dram         0x1C
>+#define PPSMC_MSG_TransferTableDram2Smu         0x1D
>+#define PPSMC_MSG_GfxDeviceDriverReset          0x1E
>+#define PPSMC_MSG_SetGfxclkOverdriveByFreqVid   0x1F
>+#define PPSMC_MSG_SetHardMinDcfclkByFreq        0x20 // Moved to VBIOS
>+#define PPSMC_MSG_SetHardMinSocclkByFreq        0x21
>+#define PPSMC_MSG_ControlIgpuATS                0x22
>+#define PPSMC_MSG_SetMinVideoFclkFreq           0x23
>+#define PPSMC_MSG_SetMinDeepSleepDcfclk         0x24 // Moved to VBIOS
>+#define PPSMC_MSG_ForcePowerDownGfx             0x25
>+#define PPSMC_MSG_SetPhyclkVoltageByFreq        0x26 // Moved to VBIOS
>+#define PPSMC_MSG_SetDppclkVoltageByFreq        0x27 // Moved to VBIOS and is SetDppclkFreq
>+#define PPSMC_MSG_SetSoftMinVcn                 0x28
>+#define PPSMC_MSG_EnablePostCode                0x29
>+#define PPSMC_MSG_GetGfxclkFrequency            0x2A
>+#define PPSMC_MSG_GetFclkFrequency              0x2B
>+#define PPSMC_MSG_GetMinGfxclkFrequency         0x2C
>+#define PPSMC_MSG_GetMaxGfxclkFrequency         0x2D
>+#define PPSMC_MSG_SoftReset                     0x2E // Not supported
>+#define PPSMC_MSG_SetGfxCGPG                    0x2F
>+#define PPSMC_MSG_SetSoftMaxGfxClk              0x30
>+#define PPSMC_MSG_SetHardMinGfxClk              0x31
>+#define PPSMC_MSG_SetSoftMaxSocclkByFreq        0x32
>+#define PPSMC_MSG_SetSoftMaxFclkByFreq          0x33
>+#define PPSMC_MSG_SetSoftMaxVcn                 0x34
>+#define PPSMC_MSG_PowerGateMmHub                0x35
>+#define PPSMC_MSG_UpdatePmeRestore              0x36 // Moved to VBIOS
>+#define PPSMC_MSG_GpuChangeState                0x37
>+#define PPSMC_MSG_SetPowerLimitPercentage       0x38
>+#define PPSMC_MSG_ForceGfxContentSave           0x39
>+#define PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown  0x3A // Moved to VBIOS
>+#define PPSMC_MSG_PowerDownJpeg                 0x3B
>+#define PPSMC_MSG_PowerUpJpeg                   0x3C
>+#define PPSMC_MSG_PowerGateAtHub                0x3D
>+#define PPSMC_MSG_SetSoftMinJpeg                0x3E
>+#define PPSMC_MSG_SetHardMinFclkByFreq          0x3F
>+#define PPSMC_Message_Count                     0x40
>+
>+
>+//Argument for  PPSMC_MSG_GpuChangeState
>+enum {
>+  eGpuChangeState_D0Entry = 1,
>+  eGpuChangeState_D3Entry,
>+};
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/Makefile	2019-08-31 15:01:11.935736175 -0500
>@@ -35,7 +35,7 @@
> 
> include $(AMD_POWERPLAY)
> 
>-POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o vega20_ppt.o navi10_ppt.o
>+POWER_MGR = amd_powerplay.o amdgpu_smu.o smu_v11_0.o smu_v12_0.o vega20_ppt.o arcturus_ppt.o navi10_ppt.o renoir_ppt.o
> 
> AMD_PP_POWER = $(addprefix $(AMD_PP_PATH)/,$(POWER_MGR))
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/navi10_ppt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/navi10_ppt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/navi10_ppt.c	2019-08-31 15:04:50.098755451 -0500
>@@ -50,9 +50,9 @@
> 	FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
> 
> #define MSG_MAP(msg, index) \
>-	[SMU_MSG_##msg] = index
>+	[SMU_MSG_##msg] = {1, (index)}
> 
>-static int navi10_message_map[SMU_MSG_MAX_COUNT] = {
>+static struct smu_11_0_cmn2aisc_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
> 	MSG_MAP(TestMessage,			PPSMC_MSG_TestMessage),
> 	MSG_MAP(GetSmuVersion,			PPSMC_MSG_GetSmuVersion),
> 	MSG_MAP(GetDriverIfVersion,		PPSMC_MSG_GetDriverIfVersion),
>@@ -119,7 +119,7 @@
> 	MSG_MAP(ArmD3,			PPSMC_MSG_ArmD3),
> };
> 
>-static int navi10_clk_map[SMU_CLK_COUNT] = {
>+static struct smu_11_0_cmn2aisc_mapping navi10_clk_map[SMU_CLK_COUNT] = {
> 	CLK_MAP(GFXCLK, PPCLK_GFXCLK),
> 	CLK_MAP(SCLK,	PPCLK_GFXCLK),
> 	CLK_MAP(SOCCLK, PPCLK_SOCCLK),
>@@ -134,7 +134,7 @@
> 	CLK_MAP(PHYCLK, PPCLK_PHYCLK),
> };
> 
>-static int navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
>+static struct smu_11_0_cmn2aisc_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
> 	FEA_MAP(DPM_PREFETCHER),
> 	FEA_MAP(DPM_GFXCLK),
> 	FEA_MAP(DPM_GFX_PACE),
>@@ -179,7 +179,7 @@
> 	FEA_MAP(ATHUB_PG),
> };
> 
>-static int navi10_table_map[SMU_TABLE_COUNT] = {
>+static struct smu_11_0_cmn2aisc_mapping navi10_table_map[SMU_TABLE_COUNT] = {
> 	TAB_MAP(PPTABLE),
> 	TAB_MAP(WATERMARKS),
> 	TAB_MAP(AVFS),
>@@ -194,12 +194,12 @@
> 	TAB_MAP(PACE),
> };
> 
>-static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
>+static struct smu_11_0_cmn2aisc_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
> 	PWR_MAP(AC),
> 	PWR_MAP(DC),
> };
> 
>-static int navi10_workload_map[] = {
>+static struct smu_11_0_cmn2aisc_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
> 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,	WORKLOAD_PPLIB_DEFAULT_BIT),
> 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,		WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
> 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
>@@ -211,79 +211,93 @@
> 
> static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
> {
>-	int val;
>-	if (index > SMU_MSG_MAX_COUNT)
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
>+	if (index >= SMU_MSG_MAX_COUNT)
> 		return -EINVAL;
> 
>-	val = navi10_message_map[index];
>-	if (val > PPSMC_Message_Count)
>+	mapping = navi10_message_map[index];
>+	if (!(mapping.valid_mapping)) {
> 		return -EINVAL;
>+	}
> 
>-	return val;
>+	return mapping.map_to;
> }
> 
> static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index)
> {
>-	int val;
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
> 	if (index >= SMU_CLK_COUNT)
> 		return -EINVAL;
> 
>-	val = navi10_clk_map[index];
>-	if (val >= PPCLK_COUNT)
>+	mapping = navi10_clk_map[index];
>+	if (!(mapping.valid_mapping)) {
> 		return -EINVAL;
>+	}
> 
>-	return val;
>+	return mapping.map_to;
> }
> 
> static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index)
> {
>-	int val;
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
> 	if (index >= SMU_FEATURE_COUNT)
> 		return -EINVAL;
> 
>-	val = navi10_feature_mask_map[index];
>-	if (val > 64)
>+	mapping = navi10_feature_mask_map[index];
>+	if (!(mapping.valid_mapping)) {
> 		return -EINVAL;
>+	}
> 
>-	return val;
>+	return mapping.map_to;
> }
> 
> static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index)
> {
>-	int val;
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
> 	if (index >= SMU_TABLE_COUNT)
> 		return -EINVAL;
> 
>-	val = navi10_table_map[index];
>-	if (val >= TABLE_COUNT)
>+	mapping = navi10_table_map[index];
>+	if (!(mapping.valid_mapping)) {
> 		return -EINVAL;
>+	}
> 
>-	return val;
>+	return mapping.map_to;
> }
> 
> static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
> {
>-	int val;
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
> 	if (index >= SMU_POWER_SOURCE_COUNT)
> 		return -EINVAL;
> 
>-	val = navi10_pwr_src_map[index];
>-	if (val >= POWER_SOURCE_COUNT)
>+	mapping = navi10_pwr_src_map[index];
>+	if (!(mapping.valid_mapping)) {
> 		return -EINVAL;
>+	}
> 
>-	return val;
>+	return mapping.map_to;
> }
> 
> 
> static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
> {
>-	int val;
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
> 	if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
> 		return -EINVAL;
> 
>-	val = navi10_workload_map[profile];
>+	mapping = navi10_workload_map[profile];
>+	if (!(mapping.valid_mapping)) {
>+		return -EINVAL;
>+	}
> 
>-	return val;
>+	return mapping.map_to;
> }
> 
> static bool is_asic_secure(struct smu_context *smu)
>@@ -355,7 +369,8 @@
> 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
> 
> 	if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
>-		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
>+		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT)
>+				| FEATURE_MASK(FEATURE_JPEG_PG_BIT);
> 
> 	/* disable DPM UCLK and DS SOCCLK on navi10 A0 secure board */
> 	if (is_asic_secure(smu)) {
>@@ -927,8 +942,6 @@
> 	ret = navi10_get_metrics_table(smu, &metrics);
> 	if (ret)
> 		return ret;
>-	if (ret)
>-		return ret;
> 
> 	*value = metrics.AverageSocketPower << 8;
> 
>@@ -987,8 +1000,6 @@
> 	ret = navi10_get_metrics_table(smu, &metrics);
> 	if (ret)
> 		return ret;
>-	if (ret)
>-		return ret;
> 
> 	*speed = metrics.CurrFanSpeed;
> 
>@@ -1017,7 +1028,7 @@
> {
> 	DpmActivityMonitorCoeffInt_t activity_monitor;
> 	uint32_t i, size = 0;
>-	uint16_t workload_type = 0;
>+	int16_t workload_type = 0;
> 	static const char *profile_name[] = {
> 					"BOOTUP_DEFAULT",
> 					"3D_FULL_SCREEN",
>@@ -1050,6 +1061,9 @@
> 	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
> 		/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
> 		workload_type = smu_workload_get_type(smu, i);
>+		if (workload_type < 0)
>+			return -EINVAL;
>+
> 		result = smu_update_table(smu,
> 					  SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
> 					  (void *)(&activity_monitor), false);
>@@ -1178,6 +1192,8 @@
> 
> 	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
> 	workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
>+	if (workload_type < 0)
>+		return -EINVAL;
> 	smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
> 				    1 << workload_type);
> 
>@@ -1367,6 +1383,9 @@
> 	struct smu_table_context *table_context = &smu->smu_table;
> 	PPTable_t *pptable = table_context->driver_pptable;
> 
>+	if(!data || !size)
>+		return -EINVAL;
>+
> 	switch (sensor) {
> 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
> 		*(uint32_t *)data = pptable->FanMaximumRpm;
>@@ -1388,7 +1407,7 @@
> 		*size = 4;
> 		break;
> 	default:
>-		return -EINVAL;
>+		ret = smu_smc_read_sensor(smu, sensor, data, size);
> 	}
> 
> 	return ret;
>@@ -1423,169 +1442,6 @@
> 	return 0;
> }
> 
>-static int navi10_get_ppfeature_status(struct smu_context *smu,
>-				       char *buf)
>-{
>-	static const char *ppfeature_name[] = {
>-				"DPM_PREFETCHER",
>-				"DPM_GFXCLK",
>-				"DPM_GFX_PACE",
>-				"DPM_UCLK",
>-				"DPM_SOCCLK",
>-				"DPM_MP0CLK",
>-				"DPM_LINK",
>-				"DPM_DCEFCLK",
>-				"MEM_VDDCI_SCALING",
>-				"MEM_MVDD_SCALING",
>-				"DS_GFXCLK",
>-				"DS_SOCCLK",
>-				"DS_LCLK",
>-				"DS_DCEFCLK",
>-				"DS_UCLK",
>-				"GFX_ULV",
>-				"FW_DSTATE",
>-				"GFXOFF",
>-				"BACO",
>-				"VCN_PG",
>-				"JPEG_PG",
>-				"USB_PG",
>-				"RSMU_SMN_CG",
>-				"PPT",
>-				"TDC",
>-				"GFX_EDC",
>-				"APCC_PLUS",
>-				"GTHR",
>-				"ACDC",
>-				"VR0HOT",
>-				"VR1HOT",
>-				"FW_CTF",
>-				"FAN_CONTROL",
>-				"THERMAL",
>-				"GFX_DCS",
>-				"RM",
>-				"LED_DISPLAY",
>-				"GFX_SS",
>-				"OUT_OF_BAND_MONITOR",
>-				"TEMP_DEPENDENT_VMIN",
>-				"MMHUB_PG",
>-				"ATHUB_PG"};
>-	static const char *output_title[] = {
>-				"FEATURES",
>-				"BITMASK",
>-				"ENABLEMENT"};
>-	uint64_t features_enabled;
>-	uint32_t feature_mask[2];
>-	int i;
>-	int ret = 0;
>-	int size = 0;
>-
>-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
>-	PP_ASSERT_WITH_CODE(!ret,
>-			"[GetPPfeatureStatus] Failed to get enabled smc features!",
>-			return ret);
>-	features_enabled = (uint64_t)feature_mask[0] |
>-			   (uint64_t)feature_mask[1] << 32;
>-
>-	size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
>-	size += sprintf(buf + size, "%-19s %-22s %s\n",
>-				output_title[0],
>-				output_title[1],
>-				output_title[2]);
>-	for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
>-		size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
>-					ppfeature_name[i],
>-					1ULL << i,
>-					(features_enabled & (1ULL << i)) ? "Y" : "N");
>-	}
>-
>-	return size;
>-}
>-
>-static int navi10_enable_smc_features(struct smu_context *smu,
>-				      bool enabled,
>-				      uint64_t feature_masks)
>-{
>-	struct smu_feature *feature = &smu->smu_feature;
>-	uint32_t feature_low, feature_high;
>-	uint32_t feature_mask[2];
>-	int ret = 0;
>-
>-	feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
>-	feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
>-
>-	if (enabled) {
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
>-						  feature_low);
>-		if (ret)
>-			return ret;
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
>-						  feature_high);
>-		if (ret)
>-			return ret;
>-	} else {
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
>-						  feature_low);
>-		if (ret)
>-			return ret;
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
>-						  feature_high);
>-		if (ret)
>-			return ret;
>-	}
>-
>-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
>-	if (ret)
>-		return ret;
>-
>-	mutex_lock(&feature->mutex);
>-	bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
>-		    feature->feature_num);
>-	mutex_unlock(&feature->mutex);
>-
>-	return 0;
>-}
>-
>-static int navi10_set_ppfeature_status(struct smu_context *smu,
>-				       uint64_t new_ppfeature_masks)
>-{
>-	uint64_t features_enabled;
>-	uint32_t feature_mask[2];
>-	uint64_t features_to_enable;
>-	uint64_t features_to_disable;
>-	int ret = 0;
>-
>-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
>-	PP_ASSERT_WITH_CODE(!ret,
>-			"[SetPPfeatureStatus] Failed to get enabled smc features!",
>-			return ret);
>-	features_enabled = (uint64_t)feature_mask[0] |
>-			   (uint64_t)feature_mask[1] << 32;
>-
>-	features_to_disable =
>-		features_enabled & ~new_ppfeature_masks;
>-	features_to_enable =
>-		~features_enabled & new_ppfeature_masks;
>-
>-	pr_debug("features_to_disable 0x%llx\n", features_to_disable);
>-	pr_debug("features_to_enable 0x%llx\n", features_to_enable);
>-
>-	if (features_to_disable) {
>-		ret = navi10_enable_smc_features(smu, false, features_to_disable);
>-		PP_ASSERT_WITH_CODE(!ret,
>-				"[SetPPfeatureStatus] Failed to disable smc features!",
>-				return ret);
>-	}
>-
>-	if (features_to_enable) {
>-		ret = navi10_enable_smc_features(smu, true, features_to_enable);
>-		PP_ASSERT_WITH_CODE(!ret,
>-				"[SetPPfeatureStatus] Failed to enable smc features!",
>-				return ret);
>-	}
>-
>-	return 0;
>-}
>-
> static int navi10_set_peak_clock_by_device(struct smu_context *smu)
> {
> 	struct amdgpu_device *adev = smu->adev;
>@@ -1627,6 +1483,10 @@
> static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
> {
> 	int ret = 0;
>+	struct amdgpu_device *adev = smu->adev;
>+
>+	if (adev->asic_type != CHIP_NAVI10)
>+		return -EINVAL;
> 
> 	switch (level) {
> 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
>@@ -1649,9 +1509,82 @@
> 	if (!range || !powerplay_table)
> 		return -EINVAL;
> 
>-	/* The unit is temperature */
>-	range->min = 0;
>-	range->max = powerplay_table->software_shutdown_temp;
>+	range->max = powerplay_table->software_shutdown_temp *
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+
>+	return 0;
>+}
>+
>+static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
>+						bool disable_memory_clock_switch)
>+{
>+	int ret = 0;
>+	struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
>+		(struct smu_11_0_max_sustainable_clocks *)
>+			smu->smu_table.max_sustainable_clocks;
>+	uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
>+	uint32_t max_memory_clock = max_sustainable_clocks->uclock;
>+
>+	if(smu->disable_uclk_switch == disable_memory_clock_switch)
>+		return 0;
>+
>+	if(disable_memory_clock_switch)
>+		ret = smu_set_hard_freq_range(smu, SMU_UCLK, max_memory_clock, 0);
>+	else
>+		ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_memory_clock, 0);
>+
>+	if(!ret)
>+		smu->disable_uclk_switch = disable_memory_clock_switch;
>+
>+	return ret;
>+}
>+
>+static int navi10_get_power_limit(struct smu_context *smu,
>+				     uint32_t *limit,
>+				     bool asic_default)
>+{
>+	PPTable_t *pptable = smu->smu_table.driver_pptable;
>+	uint32_t asic_default_power_limit = 0;
>+	int ret = 0;
>+	int power_src;
>+
>+	if (!smu->default_power_limit ||
>+	    !smu->power_limit) {
>+		if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
>+			power_src = smu_power_get_index(smu, SMU_POWER_SOURCE_AC);
>+			if (power_src < 0)
>+				return -EINVAL;
>+
>+			ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
>+				power_src << 16);
>+			if (ret) {
>+				pr_err("[%s] get PPT limit failed!", __func__);
>+				return ret;
>+			}
>+			smu_read_smc_arg(smu, &asic_default_power_limit);
>+		} else {
>+			/* the last hope to figure out the ppt limit */
>+			if (!pptable) {
>+				pr_err("Cannot get PPT limit due to pptable missing!");
>+				return -EINVAL;
>+			}
>+			asic_default_power_limit =
>+				pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
>+		}
>+
>+		if (smu->od_enabled) {
>+			asic_default_power_limit *= (100 + smu->smu_table.TDPODLimit);
>+			asic_default_power_limit /= 100;
>+		}
>+
>+		smu->default_power_limit = asic_default_power_limit;
>+		smu->power_limit = asic_default_power_limit;
>+	}
>+
>+	if (asic_default)
>+		*limit = smu->default_power_limit;
>+	else
>+		*limit = smu->power_limit;
> 
> 	return 0;
> }
>@@ -1690,10 +1623,10 @@
> 	.set_watermarks_table = navi10_set_watermarks_table,
> 	.read_sensor = navi10_read_sensor,
> 	.get_uclk_dpm_states = navi10_get_uclk_dpm_states,
>-	.get_ppfeature_status = navi10_get_ppfeature_status,
>-	.set_ppfeature_status = navi10_set_ppfeature_status,
> 	.set_performance_level = navi10_set_performance_level,
> 	.get_thermal_temperature_range = navi10_get_thermal_temperature_range,
>+	.display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
>+	.get_power_limit = navi10_get_power_limit,
> };
> 
> void navi10_set_ppt_funcs(struct smu_context *smu)
>@@ -1701,6 +1634,5 @@
> 	struct smu_table_context *smu_table = &smu->smu_table;
> 
> 	smu->ppt_funcs = &navi10_ppt_funcs;
>-	smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
> 	smu_table->table_count = TABLE_COUNT;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/renoir_ppt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/renoir_ppt.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/renoir_ppt.c	2019-08-31 15:01:11.938736175 -0500
>@@ -0,0 +1,195 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include "amdgpu.h"
>+#include "amdgpu_smu.h"
>+#include "soc15_common.h"
>+#include "smu_v12_0_ppsmc.h"
>+#include "smu12_driver_if.h"
>+#include "smu_v12_0.h"
>+#include "renoir_ppt.h"
>+
>+
>+#define MSG_MAP(msg, index) \
>+	[SMU_MSG_##msg] = {1, (index)}
>+
>+#define TAB_MAP_VALID(tab) \
>+	[SMU_TABLE_##tab] = {1, TABLE_##tab}
>+
>+#define TAB_MAP_INVALID(tab) \
>+	[SMU_TABLE_##tab] = {0, TABLE_##tab}
>+
>+static struct smu_12_0_cmn2aisc_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
>+	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage),
>+	MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion),
>+	MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion),
>+	MSG_MAP(PowerUpGfx,                     PPSMC_MSG_PowerUpGfx),
>+	MSG_MAP(AllowGfxOff,                    PPSMC_MSG_EnableGfxOff),
>+	MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisableGfxOff),
>+	MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile),
>+	MSG_MAP(PowerUpIspByTile,               PPSMC_MSG_PowerUpIspByTile),
>+	MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn),
>+	MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn),
>+	MSG_MAP(PowerDownSdma,                  PPSMC_MSG_PowerDownSdma),
>+	MSG_MAP(PowerUpSdma,                    PPSMC_MSG_PowerUpSdma),
>+	MSG_MAP(SetHardMinIspclkByFreq,         PPSMC_MSG_SetHardMinIspclkByFreq),
>+	MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn),
>+	MSG_MAP(Spare1,                         PPSMC_MSG_spare1),
>+	MSG_MAP(Spare2,                         PPSMC_MSG_spare2),
>+	MSG_MAP(SetAllowFclkSwitch,             PPSMC_MSG_SetAllowFclkSwitch),
>+	MSG_MAP(SetMinVideoGfxclkFreq,          PPSMC_MSG_SetMinVideoGfxclkFreq),
>+	MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify),
>+	MSG_MAP(SetCustomPolicy,                PPSMC_MSG_SetCustomPolicy),
>+	MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps),
>+	MSG_MAP(NumOfDisplays,                  PPSMC_MSG_SetDisplayCount),
>+	MSG_MAP(QueryPowerLimit,                PPSMC_MSG_QueryPowerLimit),
>+	MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh),
>+	MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow),
>+	MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram),
>+	MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu),
>+	MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset),
>+	MSG_MAP(SetGfxclkOverdriveByFreqVid,    PPSMC_MSG_SetGfxclkOverdriveByFreqVid),
>+	MSG_MAP(SetHardMinDcfclkByFreq,         PPSMC_MSG_SetHardMinDcfclkByFreq),
>+	MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq),
>+	MSG_MAP(ControlIgpuATS,                 PPSMC_MSG_ControlIgpuATS),
>+	MSG_MAP(SetMinVideoFclkFreq,            PPSMC_MSG_SetMinVideoFclkFreq),
>+	MSG_MAP(SetMinDeepSleepDcfclk,          PPSMC_MSG_SetMinDeepSleepDcfclk),
>+	MSG_MAP(ForcePowerDownGfx,              PPSMC_MSG_ForcePowerDownGfx),
>+	MSG_MAP(SetPhyclkVoltageByFreq,         PPSMC_MSG_SetPhyclkVoltageByFreq),
>+	MSG_MAP(SetDppclkVoltageByFreq,         PPSMC_MSG_SetDppclkVoltageByFreq),
>+	MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn),
>+	MSG_MAP(EnablePostCode,                 PPSMC_MSG_EnablePostCode),
>+	MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency),
>+	MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency),
>+	MSG_MAP(GetMinGfxclkFrequency,          PPSMC_MSG_GetMinGfxclkFrequency),
>+	MSG_MAP(GetMaxGfxclkFrequency,          PPSMC_MSG_GetMaxGfxclkFrequency),
>+	MSG_MAP(SoftReset,                      PPSMC_MSG_SoftReset),
>+	MSG_MAP(SetGfxCGPG,                     PPSMC_MSG_SetGfxCGPG),
>+	MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk),
>+	MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk),
>+	MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq),
>+	MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq),
>+	MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn),
>+	MSG_MAP(PowerGateMmHub,                 PPSMC_MSG_PowerGateMmHub),
>+	MSG_MAP(UpdatePmeRestore,               PPSMC_MSG_UpdatePmeRestore),
>+	MSG_MAP(GpuChangeState,                 PPSMC_MSG_GpuChangeState),
>+	MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage),
>+	MSG_MAP(ForceGfxContentSave,            PPSMC_MSG_ForceGfxContentSave),
>+	MSG_MAP(EnableTmdp48MHzRefclkPwrDown,   PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown),
>+	MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg),
>+	MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg),
>+	MSG_MAP(PowerGateAtHub,                 PPSMC_MSG_PowerGateAtHub),
>+	MSG_MAP(SetSoftMinJpeg,                 PPSMC_MSG_SetSoftMinJpeg),
>+	MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq),
>+};
>+
>+static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {
>+	TAB_MAP_VALID(WATERMARKS),
>+	TAB_MAP_INVALID(CUSTOM_DPM),
>+	TAB_MAP_VALID(DPMCLOCKS),
>+	TAB_MAP_VALID(SMU_METRICS),
>+};
>+
>+static int renoir_get_smu_msg_index(struct smu_context *smc, uint32_t index)
>+{
>+	struct smu_12_0_cmn2aisc_mapping mapping;
>+
>+	if (index >= SMU_MSG_MAX_COUNT)
>+		return -EINVAL;
>+
>+	mapping = renoir_message_map[index];
>+	if (!(mapping.valid_mapping))
>+		return -EINVAL;
>+
>+	return mapping.map_to;
>+}
>+
>+static int renoir_get_smu_table_index(struct smu_context *smc, uint32_t index)
>+{
>+	struct smu_12_0_cmn2aisc_mapping mapping;
>+
>+	if (index >= SMU_TABLE_COUNT)
>+		return -EINVAL;
>+
>+	mapping = renoir_table_map[index];
>+	if (!(mapping.valid_mapping))
>+		return -EINVAL;
>+
>+	return mapping.map_to;
>+}
>+
>+static int renoir_tables_init(struct smu_context *smu, struct smu_table *tables)
>+{
>+	struct smu_table_context *smu_table = &smu->smu_table;
>+
>+	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
>+		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
>+	SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
>+		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
>+	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
>+		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
>+
>+	smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
>+	if (!smu_table->clocks_table)
>+		return -ENOMEM;
>+
>+	return 0;
>+}
>+
>+/**
>+ * This interface just for getting uclk ultimate freq and should't introduce
>+ * other likewise function result in overmuch callback.
>+ */
>+static int renoir_get_dpm_uclk_limited(struct smu_context *smu, uint32_t *clock, bool max)
>+{
>+
>+	DpmClocks_t *table = smu->smu_table.clocks_table;
>+
>+	if (!clock || !table)
>+		return -EINVAL;
>+
>+	if (max)
>+		*clock = table->FClocks[NUM_FCLK_DPM_LEVELS-1].Freq;
>+	else
>+		*clock = table->FClocks[0].Freq;
>+
>+	return 0;
>+
>+}
>+
>+static const struct pptable_funcs renoir_ppt_funcs = {
>+	.get_smu_msg_index = renoir_get_smu_msg_index,
>+	.get_smu_table_index = renoir_get_smu_table_index,
>+	.tables_init = renoir_tables_init,
>+	.set_power_state = NULL,
>+	.get_dpm_uclk_limited = renoir_get_dpm_uclk_limited,
>+};
>+
>+void renoir_set_ppt_funcs(struct smu_context *smu)
>+{
>+	struct smu_table_context *smu_table = &smu->smu_table;
>+
>+	smu->ppt_funcs = &renoir_ppt_funcs;
>+	smu->smc_if_version = SMU12_DRIVER_IF_VERSION;
>+	smu_table->table_count = TABLE_COUNT;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/renoir_ppt.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/renoir_ppt.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/renoir_ppt.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/renoir_ppt.h	2019-08-31 15:01:11.938736175 -0500
>@@ -0,0 +1,28 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ *
>+ */
>+#ifndef __RENOIR_PPT_H__
>+#define __RENOIR_PPT_H__
>+
>+extern void renoir_set_ppt_funcs(struct smu_context *smu);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c	2019-08-31 15:01:11.938736175 -0500
>@@ -118,6 +118,7 @@
> {
> 	struct smu10_smumgr *priv =
> 			(struct smu10_smumgr *)(hwmgr->smu_backend);
>+	struct amdgpu_device *adev = hwmgr->adev;
> 
> 	PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
> 			"Invalid SMU Table ID!", return -EINVAL;);
>@@ -135,6 +136,9 @@
> 			PPSMC_MSG_TransferTableSmu2Dram,
> 			priv->smu_tables.entry[table_id].table_id);
> 
>+	/* flush hdp cache */
>+	adev->nbio_funcs->hdp_flush(adev, NULL);
>+
> 	memcpy(table, (uint8_t *)priv->smu_tables.entry[table_id].table,
> 			priv->smu_tables.entry[table_id].size);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c	2019-08-31 15:01:11.938736175 -0500
>@@ -722,16 +722,17 @@
> 
> static int smu8_start_smu(struct pp_hwmgr *hwmgr)
> {
>-	struct amdgpu_device *adev = hwmgr->adev;
>+	struct amdgpu_device *adev;
> 
> 	uint32_t index = SMN_MP1_SRAM_START_ADDR +
> 			 SMU8_FIRMWARE_HEADER_LOCATION +
> 			 offsetof(struct SMU8_Firmware_Header, Version);
> 
>-
> 	if (hwmgr == NULL || hwmgr->device == NULL)
> 		return -EINVAL;
> 
>+	adev = hwmgr->adev;
>+
> 	cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
> 	hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
> 	pr_info("smu version %02d.%02d.%02d\n",
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c	2019-08-31 15:01:11.938736175 -0500
>@@ -39,6 +39,7 @@
> 		uint8_t *table, int16_t table_id)
> {
> 	struct vega10_smumgr *priv = hwmgr->smu_backend;
>+	struct amdgpu_device *adev = hwmgr->adev;
> 
> 	PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
> 			"Invalid SMU Table ID!", return -EINVAL);
>@@ -56,6 +57,9 @@
> 			PPSMC_MSG_TransferTableSmu2Dram,
> 			priv->smu_tables.entry[table_id].table_id);
> 
>+	/* flush hdp cache */
>+	adev->nbio_funcs->hdp_flush(adev, NULL);
>+
> 	memcpy(table, priv->smu_tables.entry[table_id].table,
> 			priv->smu_tables.entry[table_id].size);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c	2019-08-31 15:01:11.939736175 -0500
>@@ -42,6 +42,7 @@
> {
> 	struct vega12_smumgr *priv =
> 			(struct vega12_smumgr *)(hwmgr->smu_backend);
>+	struct amdgpu_device *adev = hwmgr->adev;
> 
> 	PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
> 			"Invalid SMU Table ID!", return -EINVAL);
>@@ -64,6 +65,9 @@
> 			"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
> 			return -EINVAL);
> 
>+	/* flush hdp cache */
>+	adev->nbio_funcs->hdp_flush(adev, NULL);
>+
> 	memcpy(table, priv->smu_tables.entry[table_id].table,
> 			priv->smu_tables.entry[table_id].size);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c	2019-08-31 15:01:11.939736175 -0500
>@@ -44,7 +44,7 @@
> #define smnMP0_FW_INTF			0x30101c0
> #define smnMP1_PUB_CTRL			0x3010b14
> 
>-static bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr)
>+bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr)
> {
> 	struct amdgpu_device *adev = hwmgr->adev;
> 	uint32_t mp1_fw_flags;
>@@ -163,6 +163,7 @@
> {
> 	struct vega20_smumgr *priv =
> 			(struct vega20_smumgr *)(hwmgr->smu_backend);
>+	struct amdgpu_device *adev = hwmgr->adev;
> 	int ret = 0;
> 
> 	PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
>@@ -187,6 +188,9 @@
> 			"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
> 			return ret);
> 
>+	/* flush hdp cache */
>+	adev->nbio_funcs->hdp_flush(adev, NULL);
>+
> 	memcpy(table, priv->smu_tables.entry[table_id].table,
> 			priv->smu_tables.entry[table_id].size);
> 
>@@ -266,6 +270,7 @@
> {
> 	struct vega20_smumgr *priv =
> 			(struct vega20_smumgr *)(hwmgr->smu_backend);
>+	struct amdgpu_device *adev = hwmgr->adev;
> 	int ret = 0;
> 
> 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
>@@ -284,6 +289,9 @@
> 			"[GetActivityMonitor] Attempt to Transfer Table From SMU Failed!",
> 			return ret);
> 
>+	/* flush hdp cache */
>+	adev->nbio_funcs->hdp_flush(adev, NULL);
>+
> 	memcpy(table, priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].table,
> 			priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].size);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h	2019-08-31 15:01:11.939736175 -0500
>@@ -57,5 +57,7 @@
> 		uint8_t *table, uint16_t workload_type);
> int vega20_set_pptable_driver_address(struct pp_hwmgr *hwmgr);
> 
>+bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr);
>+
> #endif
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smu_v11_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smu_v11_0.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smu_v11_0.c	2019-08-31 15:01:12.252736203 -0500
>@@ -33,6 +33,7 @@
> #include "soc15_common.h"
> #include "atom.h"
> #include "vega20_ppt.h"
>+#include "arcturus_ppt.h"
> #include "navi10_ppt.h"
> 
> #include "asic_reg/thm/thm_11_0_2_offset.h"
>@@ -45,7 +46,10 @@
> #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
> 
> MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
>+MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
> MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
>+MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
>+MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
> 
> #define SMU11_VOLTAGE_SCALE 4
> 
>@@ -102,8 +106,8 @@
> 	ret = smu_v11_0_wait_for_response(smu);
> 
> 	if (ret)
>-		pr_err("Failed to send message 0x%x, response 0x%x\n", index,
>-		       ret);
>+		pr_err("failed send message: %10s (%d) response %#x\n",
>+		       smu_get_message_name(smu, msg), index, ret);
> 
> 	return ret;
> 
>@@ -123,8 +127,8 @@
> 
> 	ret = smu_v11_0_wait_for_response(smu);
> 	if (ret)
>-		pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
>-		       index, ret, param);
>+		pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
>+		       smu_get_message_name(smu, msg), index, param, ret);
> 
> 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
> 
>@@ -134,8 +138,8 @@
> 
> 	ret = smu_v11_0_wait_for_response(smu);
> 	if (ret)
>-		pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
>-		       index, ret, param);
>+		pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
>+		       smu_get_message_name(smu, msg), index, param, ret);
> 
> 	return ret;
> }
>@@ -154,9 +158,18 @@
> 	case CHIP_VEGA20:
> 		chip_name = "vega20";
> 		break;
>+	case CHIP_ARCTURUS:
>+		chip_name = "arcturus";
>+		break;
> 	case CHIP_NAVI10:
> 		chip_name = "navi10";
> 		break;
>+	case CHIP_NAVI14:
>+		chip_name = "navi14";
>+		break;
>+	case CHIP_NAVI12:
>+		chip_name = "navi12";
>+		break;
> 	default:
> 		BUG();
> 	}
>@@ -202,7 +215,7 @@
> 	uint32_t i;
> 	uint32_t mp1_fw_flags;
> 
>-	hdr = (const struct smc_firmware_header_v1_0 *)	adev->pm.fw->data;
>+	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
> 	src = (const uint32_t *)(adev->pm.fw->data +
> 		le32_to_cpu(hdr->header.ucode_array_offset_bytes));
> 
>@@ -261,6 +274,25 @@
> 	smu_minor = (smu_version >> 8) & 0xff;
> 	smu_debug = (smu_version >> 0) & 0xff;
> 
>+	switch (smu->adev->asic_type) {
>+	case CHIP_VEGA20:
>+		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_VG20;
>+		break;
>+	case CHIP_ARCTURUS:
>+		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
>+		break;
>+	case CHIP_NAVI10:
>+		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV10;
>+		break;
>+	case CHIP_NAVI14:
>+		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_NV14;
>+		break;
>+	default:
>+		pr_err("smu unsupported asic type:%d.\n", smu->adev->asic_type);
>+		smu->smc_if_version = SMU11_DRIVER_IF_VERSION_INV;
>+		break;
>+	}
>+
> 	/*
> 	 * 1. if_version mismatch is not critical as our fw is designed
> 	 * to be backward compatible.
>@@ -295,7 +327,8 @@
> 	return 0;
> }
> 
>-static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, uint32_t *size, uint32_t pptable_id)
>+static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
>+				      uint32_t *size, uint32_t pptable_id)
> {
> 	struct amdgpu_device *adev = smu->adev;
> 	const struct smc_firmware_header_v2_1 *v2_1;
>@@ -537,6 +570,9 @@
> 		smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
> 	}
> 
>+	smu->smu_table.boot_values.format_revision = header->format_revision;
>+	smu->smu_table.boot_values.content_revision = header->content_revision;
>+
> 	return 0;
> }
> 
>@@ -616,6 +652,24 @@
> 	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
> 	smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
> 
>+	if ((smu->smu_table.boot_values.format_revision == 3) &&
>+	    (smu->smu_table.boot_values.content_revision >= 2)) {
>+		memset(&input, 0, sizeof(input));
>+		input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
>+		input.syspll_id = SMU11_SYSPLL1_2_ID;
>+		input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
>+		index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
>+						    getsmuclockinfo);
>+
>+		ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
>+						(uint32_t *)&input);
>+		if (ret)
>+			return -EINVAL;
>+
>+		output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
>+		smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
>+	}
>+
> 	return 0;
> }
> 
>@@ -724,8 +778,6 @@
> 	struct smu_table *table = NULL;
> 
> 	table = &smu_table->tables[SMU_TABLE_WATERMARKS];
>-	if (!table)
>-		return -EINVAL;
> 
> 	if (!table->cpu_addr)
> 		return -EINVAL;
>@@ -790,44 +842,6 @@
> 	return ret;
> }
> 
>-static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
>-{
>-	uint32_t feature_low = 0, feature_high = 0;
>-	int ret = 0;
>-
>-	if (!smu->pm_enabled)
>-		return ret;
>-	if (feature_id >= 0 && feature_id < 31)
>-		feature_low = (1 << feature_id);
>-	else if (feature_id > 31 && feature_id < 63)
>-		feature_high = (1 << feature_id);
>-	else
>-		return -EINVAL;
>-
>-	if (enabled) {
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
>-						  feature_low);
>-		if (ret)
>-			return ret;
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
>-						  feature_high);
>-		if (ret)
>-			return ret;
>-
>-	} else {
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
>-						  feature_low);
>-		if (ret)
>-			return ret;
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
>-						  feature_high);
>-		if (ret)
>-			return ret;
>-
>-	}
>-
>-	return ret;
>-}
> 
> static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
> {
>@@ -929,11 +943,21 @@
> 				    enum smu_clk_type clock_select)
> {
> 	int ret = 0;
>+	int clk_id;
> 
> 	if (!smu->pm_enabled)
> 		return ret;
>+
>+	if ((smu_msg_get_index(smu, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
>+	    (smu_msg_get_index(smu, SMU_MSG_GetMaxDpmFreq) < 0))
>+		return 0;
>+
>+	clk_id = smu_clk_get_index(smu, clock_select);
>+	if (clk_id < 0)
>+		return -EINVAL;
>+
> 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
>-					  smu_clk_get_index(smu, clock_select) << 16);
>+					  clk_id << 16);
> 	if (ret) {
> 		pr_err("[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
> 		return ret;
>@@ -948,7 +972,7 @@
> 
> 	/* if DC limit is zero, return AC limit */
> 	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
>-					  smu_clk_get_index(smu, clock_select) << 16);
>+					  clk_id << 16);
> 	if (ret) {
> 		pr_err("[GetMaxSustainableClock] failed to get max AC clock from SMC!");
> 		return ret;
>@@ -1039,57 +1063,32 @@
> 	return 0;
> }
> 
>-static int smu_v11_0_get_power_limit(struct smu_context *smu,
>-				     uint32_t *limit,
>-				     bool get_default)
>+static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
> {
> 	int ret = 0;
> 
>-	if (get_default) {
>-		mutex_lock(&smu->mutex);
>-		*limit = smu->default_power_limit;
>-		if (smu->od_enabled) {
>-			*limit *= (100 + smu->smu_table.TDPODLimit);
>-			*limit /= 100;
>-		}
>-		mutex_unlock(&smu->mutex);
>-	} else {
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit,
>-			smu_power_get_index(smu, SMU_POWER_SOURCE_AC) << 16);
>-		if (ret) {
>-			pr_err("[%s] get PPT limit failed!", __func__);
>-			return ret;
>-		}
>-		smu_read_smc_arg(smu, limit);
>-		smu->power_limit = *limit;
>+	if (n > smu->default_power_limit) {
>+		pr_err("New power limit is over the max allowed %d\n",
>+				smu->default_power_limit);
>+		return -EINVAL;
> 	}
> 
>-	return ret;
>-}
>-
>-static int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
>-{
>-	uint32_t max_power_limit;
>-	int ret = 0;
>-
> 	if (n == 0)
> 		n = smu->default_power_limit;
> 
>-	max_power_limit = smu->default_power_limit;
>-
>-	if (smu->od_enabled) {
>-		max_power_limit *= (100 + smu->smu_table.TDPODLimit);
>-		max_power_limit /= 100;
>+	if (!smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
>+		pr_err("Setting new power limit is not supported!\n");
>+		return -EOPNOTSUPP;
> 	}
> 
>-	if (smu_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
>+	ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n);
> 	if (ret) {
>-		pr_err("[%s] Set power limit Failed!", __func__);
>+		pr_err("[%s] Set power limit Failed!\n", __func__);
> 		return ret;
> 	}
>+	smu->power_limit = n;
> 
>-	return ret;
>+	return 0;
> }
> 
> static int smu_v11_0_get_current_clk_freq(struct smu_context *smu,
>@@ -1098,16 +1097,21 @@
> {
> 	int ret = 0;
> 	uint32_t freq = 0;
>+	int asic_clk_id;
> 
> 	if (clk_id >= SMU_CLK_COUNT || !value)
> 		return -EINVAL;
> 
>+	asic_clk_id = smu_clk_get_index(smu, clk_id);
>+	if (asic_clk_id < 0)
>+		return -EINVAL;
>+
> 	/* if don't has GetDpmClockFreq Message, try get current clock by SmuMetrics_t */
>-	if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) == 0)
>+	if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) < 0)
> 		ret =  smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
> 	else {
> 		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
>-						  (smu_clk_get_index(smu, clk_id) << 16));
>+						  (asic_clk_id << 16));
> 		if (ret)
> 			return ret;
> 
>@@ -1123,23 +1127,17 @@
> }
> 
> static int smu_v11_0_set_thermal_range(struct smu_context *smu,
>-				       struct smu_temperature_range *range)
>+				       struct smu_temperature_range range)
> {
> 	struct amdgpu_device *adev = smu->adev;
> 	int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
> 	int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
> 	uint32_t val;
> 
>-	if (!range)
>-		return -EINVAL;
>-
>-	if (low < range->min)
>-		low = range->min;
>-	if (high > range->max)
>-		high = range->max;
>-
>-	low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, range->min);
>-	high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, range->max);
>+	low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
>+			range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
>+	high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
>+			range.max / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
> 
> 	if (low > high)
> 		return -EINVAL;
>@@ -1175,27 +1173,20 @@
> static int smu_v11_0_start_thermal_control(struct smu_context *smu)
> {
> 	int ret = 0;
>-	struct smu_temperature_range range = {
>-		TEMP_RANGE_MIN,
>-		TEMP_RANGE_MAX,
>-		TEMP_RANGE_MAX,
>-		TEMP_RANGE_MIN,
>-		TEMP_RANGE_MAX,
>-		TEMP_RANGE_MAX,
>-		TEMP_RANGE_MIN,
>-		TEMP_RANGE_MAX,
>-		TEMP_RANGE_MAX};
>+	struct smu_temperature_range range;
> 	struct amdgpu_device *adev = smu->adev;
> 
> 	if (!smu->pm_enabled)
> 		return ret;
> 
>+	memcpy(&range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
>+
> 	ret = smu_get_thermal_temperature_range(smu, &range);
> 	if (ret)
> 		return ret;
> 
> 	if (smu->smu_table.thermal_controller_type) {
>-		ret = smu_v11_0_set_thermal_range(smu, &range);
>+		ret = smu_v11_0_set_thermal_range(smu, range);
> 		if (ret)
> 			return ret;
> 
>@@ -1208,17 +1199,15 @@
> 			return ret;
> 	}
> 
>-	adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>-	adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>-	adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>-	adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>-	adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>-	adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>-	adev->pm.dpm.thermal.min_mem_temp = range.mem_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>-	adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>-	adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>-	adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>-	adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+	adev->pm.dpm.thermal.min_temp = range.min;
>+	adev->pm.dpm.thermal.max_temp = range.max;
>+	adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
>+	adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
>+	adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
>+	adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max;
>+	adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
>+	adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
>+	adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
> 
> 	return ret;
> }
>@@ -1252,6 +1241,10 @@
> 				 void *data, uint32_t *size)
> {
> 	int ret = 0;
>+
>+	if(!data || !size)
>+		return -EINVAL;
>+
> 	switch (sensor) {
> 	case AMDGPU_PP_SENSOR_GFX_MCLK:
> 		ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
>@@ -1274,10 +1267,6 @@
> 		break;
> 	}
> 
>-	/* try get sensor data by asic */
>-	if (ret)
>-		ret = smu_asic_read_sensor(smu, sensor, data, size);
>-
> 	if (ret)
> 		*size = 0;
> 
>@@ -1324,10 +1313,15 @@
> 		if (ret)
> 			goto failed;
> 
>+		if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
>+			return 0;
>+
> 		mutex_lock(&smu->mutex);
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
>-			(smu_clk_get_index(smu, clk_select) << 16) | clk_freq);
>+		ret = smu_set_hard_freq_range(smu, clk_select, clk_freq, 0);
> 		mutex_unlock(&smu->mutex);
>+
>+		if(clk_select == SMU_UCLK)
>+			smu->hard_min_uclk_req_from_dal = clk_freq;
> 	}
> 
> failed:
>@@ -1363,6 +1357,8 @@
> 	case CHIP_VEGA20:
> 		break;
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
> 			return 0;
> 		mutex_lock(&smu->mutex);
>@@ -1389,17 +1385,17 @@
> }
> 
> static int
>-smu_v11_0_smc_fan_control(struct smu_context *smu, bool start)
>+smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
> {
> 	int ret = 0;
> 
> 	if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
> 		return 0;
> 
>-	ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start);
>+	ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
> 	if (ret)
> 		pr_err("[%s]%s smc FAN CONTROL feature failed!",
>-		       __func__, (start ? "Start" : "Stop"));
>+		       __func__, (auto_fan_control ? "Start" : "Stop"));
> 
> 	return ret;
> }
>@@ -1423,16 +1419,15 @@
> smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
> {
> 	struct amdgpu_device *adev = smu->adev;
>-	uint32_t duty100;
>-	uint32_t duty;
>+	uint32_t duty100, duty;
> 	uint64_t tmp64;
>-	bool stop = 0;
> 
> 	if (speed > 100)
> 		speed = 100;
> 
>-	if (smu_v11_0_smc_fan_control(smu, stop))
>+	if (smu_v11_0_auto_fan_control(smu, 0))
> 		return -EINVAL;
>+
> 	duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
> 				CG_FDO_CTRL1, FMAX_DUTY100);
> 	if (!duty100)
>@@ -1454,18 +1449,16 @@
> 			       uint32_t mode)
> {
> 	int ret = 0;
>-	bool start = 1;
>-	bool stop  = 0;
> 
> 	switch (mode) {
> 	case AMD_FAN_CTRL_NONE:
> 		ret = smu_v11_0_set_fan_speed_percent(smu, 100);
> 		break;
> 	case AMD_FAN_CTRL_MANUAL:
>-		ret = smu_v11_0_smc_fan_control(smu, stop);
>+		ret = smu_v11_0_auto_fan_control(smu, 0);
> 		break;
> 	case AMD_FAN_CTRL_AUTO:
>-		ret = smu_v11_0_smc_fan_control(smu, start);
>+		ret = smu_v11_0_auto_fan_control(smu, 1);
> 		break;
> 	default:
> 		break;
>@@ -1485,13 +1478,12 @@
> 	struct amdgpu_device *adev = smu->adev;
> 	int ret;
> 	uint32_t tach_period, crystal_clock_freq;
>-	bool stop = 0;
> 
> 	if (!speed)
> 		return -EINVAL;
> 
> 	mutex_lock(&(smu->mutex));
>-	ret = smu_v11_0_smc_fan_control(smu, stop);
>+	ret = smu_v11_0_auto_fan_control(smu, 0);
> 	if (ret)
> 		goto set_fan_speed_rpm_failed;
> 
>@@ -1672,7 +1664,7 @@
> static enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
> {
> 	struct smu_baco_context *smu_baco = &smu->smu_baco;
>-	enum smu_baco_state baco_state = SMU_BACO_STATE_EXIT;
>+	enum smu_baco_state baco_state;
> 
> 	mutex_lock(&smu_baco->mutex);
> 	baco_state = smu_baco->state;
>@@ -1726,6 +1718,43 @@
> 	return ret;
> }
> 
>+static int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
>+						 uint32_t *min, uint32_t *max)
>+{
>+	int ret = 0, clk_id = 0;
>+	uint32_t param = 0;
>+
>+	mutex_lock(&smu->mutex);
>+	clk_id = smu_clk_get_index(smu, clk_type);
>+	if (clk_id < 0) {
>+		ret = -EINVAL;
>+		goto failed;
>+	}
>+	param = (clk_id & 0xffff) << 16;
>+
>+	if (max) {
>+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param);
>+		if (ret)
>+			goto failed;
>+		ret = smu_read_smc_arg(smu, max);
>+		if (ret)
>+			goto failed;
>+	}
>+
>+	if (min) {
>+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param);
>+		if (ret)
>+			goto failed;
>+		ret = smu_read_smc_arg(smu, min);
>+		if (ret)
>+			goto failed;
>+	}
>+
>+failed:
>+	mutex_unlock(&smu->mutex);
>+	return ret;
>+}
>+
> static const struct smu_funcs smu_v11_0_funcs = {
> 	.init_microcode = smu_v11_0_init_microcode,
> 	.load_microcode = smu_v11_0_load_microcode,
>@@ -1744,7 +1773,7 @@
> 	.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
> 	.check_pptable = smu_v11_0_check_pptable,
> 	.parse_pptable = smu_v11_0_parse_pptable,
>-	.populate_smc_pptable = smu_v11_0_populate_smc_pptable,
>+	.populate_smc_tables = smu_v11_0_populate_smc_pptable,
> 	.write_pptable = smu_v11_0_write_pptable,
> 	.write_watermarks_table = smu_v11_0_write_watermarks_table,
> 	.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
>@@ -1753,9 +1782,7 @@
> 	.set_allowed_mask = smu_v11_0_set_allowed_mask,
> 	.get_enabled_mask = smu_v11_0_get_enabled_mask,
> 	.system_features_control = smu_v11_0_system_features_control,
>-	.update_feature_enable_state = smu_v11_0_update_feature_enable_state,
> 	.notify_display_change = smu_v11_0_notify_display_change,
>-	.get_power_limit = smu_v11_0_get_power_limit,
> 	.set_power_limit = smu_v11_0_set_power_limit,
> 	.get_current_clk_freq = smu_v11_0_get_current_clk_freq,
> 	.init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
>@@ -1777,6 +1804,7 @@
> 	.baco_get_state = smu_v11_0_baco_get_state,
> 	.baco_set_state = smu_v11_0_baco_set_state,
> 	.baco_reset = smu_v11_0_baco_reset,
>+	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
> };
> 
> void smu_v11_0_set_smu_funcs(struct smu_context *smu)
>@@ -1788,7 +1816,12 @@
> 	case CHIP_VEGA20:
> 		vega20_set_ppt_funcs(smu);
> 		break;
>+	case CHIP_ARCTURUS:
>+		arcturus_set_ppt_funcs(smu);
>+		break;
> 	case CHIP_NAVI10:
>+	case CHIP_NAVI14:
>+	case CHIP_NAVI12:
> 		navi10_set_ppt_funcs(smu);
> 		break;
> 	default:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smu_v12_0.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/smu_v12_0.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/smu_v12_0.c	2019-08-31 15:01:11.938736175 -0500
>@@ -0,0 +1,412 @@
>+/*
>+ * Copyright 2019 Advanced Micro Devices, Inc.
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice shall be included in
>+ * all copies or substantial portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>+ * OTHER DEALINGS IN THE SOFTWARE.
>+ */
>+
>+#include "pp_debug.h"
>+#include <linux/firmware.h>
>+#include "amdgpu.h"
>+#include "amdgpu_smu.h"
>+#include "atomfirmware.h"
>+#include "amdgpu_atomfirmware.h"
>+#include "smu_v12_0.h"
>+#include "soc15_common.h"
>+#include "atom.h"
>+#include "renoir_ppt.h"
>+
>+#include "asic_reg/mp/mp_12_0_0_offset.h"
>+#include "asic_reg/mp/mp_12_0_0_sh_mask.h"
>+
>+#define smnMP1_FIRMWARE_FLAGS                                0x3010024
>+
>+#define mmSMUIO_GFX_MISC_CNTL                                0x00c8
>+#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX                       0
>+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK          0x00000006L
>+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT        0x1
>+
>+static int smu_v12_0_send_msg_without_waiting(struct smu_context *smu,
>+					      uint16_t msg)
>+{
>+	struct amdgpu_device *adev = smu->adev;
>+
>+	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
>+	return 0;
>+}
>+
>+static int smu_v12_0_read_arg(struct smu_context *smu, uint32_t *arg)
>+{
>+	struct amdgpu_device *adev = smu->adev;
>+
>+	*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
>+	return 0;
>+}
>+
>+static int smu_v12_0_wait_for_response(struct smu_context *smu)
>+{
>+	struct amdgpu_device *adev = smu->adev;
>+	uint32_t cur_value, i;
>+
>+	for (i = 0; i < adev->usec_timeout; i++) {
>+		cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
>+		if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
>+			break;
>+		udelay(1);
>+	}
>+
>+	/* timeout means wrong logic */
>+	if (i == adev->usec_timeout)
>+		return -ETIME;
>+
>+	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
>+}
>+
>+static int smu_v12_0_send_msg(struct smu_context *smu, uint16_t msg)
>+{
>+	struct amdgpu_device *adev = smu->adev;
>+	int ret = 0, index = 0;
>+
>+	index = smu_msg_get_index(smu, msg);
>+	if (index < 0)
>+		return index;
>+
>+	smu_v12_0_wait_for_response(smu);
>+
>+	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
>+
>+	smu_v12_0_send_msg_without_waiting(smu, (uint16_t)index);
>+
>+	ret = smu_v12_0_wait_for_response(smu);
>+
>+	if (ret)
>+		pr_err("Failed to send message 0x%x, response 0x%x\n", index,
>+		       ret);
>+
>+	return ret;
>+
>+}
>+
>+static int
>+smu_v12_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
>+			      uint32_t param)
>+{
>+	struct amdgpu_device *adev = smu->adev;
>+	int ret = 0, index = 0;
>+
>+	index = smu_msg_get_index(smu, msg);
>+	if (index < 0)
>+		return index;
>+
>+	ret = smu_v12_0_wait_for_response(smu);
>+	if (ret)
>+		pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
>+		       index, ret, param);
>+
>+	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
>+
>+	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
>+
>+	smu_v12_0_send_msg_without_waiting(smu, (uint16_t)index);
>+
>+	ret = smu_v12_0_wait_for_response(smu);
>+	if (ret)
>+		pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
>+		       index, ret, param);
>+
>+	return ret;
>+}
>+
>+static int smu_v12_0_check_fw_status(struct smu_context *smu)
>+{
>+	struct amdgpu_device *adev = smu->adev;
>+	uint32_t mp1_fw_flags;
>+
>+	mp1_fw_flags = RREG32_PCIE(MP1_Public |
>+		(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
>+
>+	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
>+		MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
>+		return 0;
>+
>+	return -EIO;
>+}
>+
>+static int smu_v12_0_check_fw_version(struct smu_context *smu)
>+{
>+	uint32_t if_version = 0xff, smu_version = 0xff;
>+	uint16_t smu_major;
>+	uint8_t smu_minor, smu_debug;
>+	int ret = 0;
>+
>+	ret = smu_get_smc_version(smu, &if_version, &smu_version);
>+	if (ret)
>+		return ret;
>+
>+	smu_major = (smu_version >> 16) & 0xffff;
>+	smu_minor = (smu_version >> 8) & 0xff;
>+	smu_debug = (smu_version >> 0) & 0xff;
>+
>+	/*
>+	 * 1. if_version mismatch is not critical as our fw is designed
>+	 * to be backward compatible.
>+	 * 2. New fw usually brings some optimizations. But that's visible
>+	 * only on the paired driver.
>+	 * Considering above, we just leave user a warning message instead
>+	 * of halt driver loading.
>+	 */
>+	if (if_version != smu->smc_if_version) {
>+		pr_info("smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
>+			"smu fw version = 0x%08x (%d.%d.%d)\n",
>+			smu->smc_if_version, if_version,
>+			smu_version, smu_major, smu_minor, smu_debug);
>+		pr_warn("SMU driver if version not matched\n");
>+	}
>+
>+	return ret;
>+}
>+
>+static int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate)
>+{
>+	if (!(smu->adev->flags & AMD_IS_APU))
>+		return 0;
>+
>+	if (gate)
>+		return smu_send_smc_msg(smu, SMU_MSG_PowerDownSdma);
>+	else
>+		return smu_send_smc_msg(smu, SMU_MSG_PowerUpSdma);
>+}
>+
>+static int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate)
>+{
>+	if (!(smu->adev->flags & AMD_IS_APU))
>+		return 0;
>+
>+	if (gate)
>+		return smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
>+	else
>+		return smu_send_smc_msg(smu, SMU_MSG_PowerUpVcn);
>+}
>+
>+static int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable)
>+{
>+	if (!(smu->adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
>+		return 0;
>+
>+	return smu_v12_0_send_msg_with_param(smu,
>+		SMU_MSG_SetGfxCGPG, enable ? 1 : 0);
>+}
>+
>+/**
>+ * smu_v12_0_get_gfxoff_status - get gfxoff status
>+ *
>+ * @smu: amdgpu_device pointer
>+ *
>+ * This function will be used to get gfxoff status
>+ *
>+ * Returns 0=GFXOFF(default).
>+ * Returns 1=Transition out of GFX State.
>+ * Returns 2=Not in GFXOFF.
>+ * Returns 3=Transition into GFXOFF.
>+ */
>+static uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu)
>+{
>+	uint32_t reg;
>+	uint32_t gfxOff_Status = 0;
>+	struct amdgpu_device *adev = smu->adev;
>+
>+	reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
>+	gfxOff_Status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
>+		>> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
>+
>+	return gfxOff_Status;
>+}
>+
>+static int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable)
>+{
>+	int ret = 0, timeout = 500;
>+
>+	if (enable) {
>+		ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff);
>+
>+		/* confirm gfx is back to "off" state, timeout is 5 seconds */
>+		while (!(smu_v12_0_get_gfxoff_status(smu) == 0)) {
>+			msleep(10);
>+			timeout--;
>+			if (timeout == 0) {
>+				DRM_ERROR("enable gfxoff timeout and failed!\n");
>+				break;
>+			}
>+		}
>+	} else {
>+		ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff);
>+
>+		/* confirm gfx is back to "on" state, timeout is 0.5 second */
>+		while (!(smu_v12_0_get_gfxoff_status(smu) == 2)) {
>+			msleep(1);
>+			timeout--;
>+			if (timeout == 0) {
>+				DRM_ERROR("disable gfxoff timeout and failed!\n");
>+				break;
>+			}
>+		}
>+	}
>+
>+	return ret;
>+}
>+
>+static int smu_v12_0_init_smc_tables(struct smu_context *smu)
>+{
>+	struct smu_table_context *smu_table = &smu->smu_table;
>+	struct smu_table *tables = NULL;
>+
>+	if (smu_table->tables || smu_table->table_count == 0)
>+		return -EINVAL;
>+
>+	tables = kcalloc(SMU_TABLE_COUNT, sizeof(struct smu_table),
>+			 GFP_KERNEL);
>+	if (!tables)
>+		return -ENOMEM;
>+
>+	smu_table->tables = tables;
>+
>+	return smu_tables_init(smu, tables);
>+}
>+
>+static int smu_v12_0_fini_smc_tables(struct smu_context *smu)
>+{
>+	struct smu_table_context *smu_table = &smu->smu_table;
>+
>+	if (!smu_table->tables || smu_table->table_count == 0)
>+		return -EINVAL;
>+
>+	kfree(smu_table->clocks_table);
>+	kfree(smu_table->tables);
>+
>+	smu_table->clocks_table = NULL;
>+	smu_table->tables = NULL;
>+
>+	return 0;
>+}
>+
>+static int smu_v12_0_populate_smc_tables(struct smu_context *smu)
>+{
>+	struct smu_table_context *smu_table = &smu->smu_table;
>+	struct smu_table *table = NULL;
>+
>+	table = &smu_table->tables[SMU_TABLE_DPMCLOCKS];
>+	if (!table)
>+		return -EINVAL;
>+
>+	if (!table->cpu_addr)
>+		return -EINVAL;
>+
>+	return smu_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
>+}
>+
>+static int smu_v12_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
>+						 uint32_t *min, uint32_t *max)
>+{
>+	int ret = 0;
>+
>+	mutex_lock(&smu->mutex);
>+
>+	if (max) {
>+		switch (clk_type) {
>+		case SMU_GFXCLK:
>+		case SMU_SCLK:
>+			ret = smu_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency);
>+			if (ret) {
>+				pr_err("Attempt to get max GX frequency from SMC Failed !\n");
>+				goto failed;
>+			}
>+			ret = smu_read_smc_arg(smu, max);
>+			if (ret)
>+				goto failed;
>+			break;
>+		case SMU_UCLK:
>+			ret = smu_get_dpm_uclk_limited(smu, max, true);
>+			if (ret)
>+				goto failed;
>+			break;
>+		default:
>+			ret = -EINVAL;
>+			goto failed;
>+
>+		}
>+	}
>+
>+	if (min) {
>+		switch (clk_type) {
>+		case SMU_GFXCLK:
>+		case SMU_SCLK:
>+			ret = smu_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency);
>+			if (ret) {
>+				pr_err("Attempt to get min GX frequency from SMC Failed !\n");
>+				goto failed;
>+			}
>+			ret = smu_read_smc_arg(smu, min);
>+			if (ret)
>+				goto failed;
>+			break;
>+		case SMU_UCLK:
>+			ret = smu_get_dpm_uclk_limited(smu, min, false);
>+			if (ret)
>+				goto failed;
>+			break;
>+		default:
>+			ret = -EINVAL;
>+			goto failed;
>+		}
>+
>+	}
>+failed:
>+	mutex_unlock(&smu->mutex);
>+	return ret;
>+}
>+
>+static const struct smu_funcs smu_v12_0_funcs = {
>+	.check_fw_status = smu_v12_0_check_fw_status,
>+	.check_fw_version = smu_v12_0_check_fw_version,
>+	.powergate_sdma = smu_v12_0_powergate_sdma,
>+	.powergate_vcn = smu_v12_0_powergate_vcn,
>+	.send_smc_msg = smu_v12_0_send_msg,
>+	.send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
>+	.read_smc_arg = smu_v12_0_read_arg,
>+	.set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
>+	.gfx_off_control = smu_v12_0_gfx_off_control,
>+	.init_smc_tables = smu_v12_0_init_smc_tables,
>+	.fini_smc_tables = smu_v12_0_fini_smc_tables,
>+	.populate_smc_tables = smu_v12_0_populate_smc_tables,
>+	.get_dpm_ultimate_freq = smu_v12_0_get_dpm_ultimate_freq,
>+};
>+
>+void smu_v12_0_set_smu_funcs(struct smu_context *smu)
>+{
>+	struct amdgpu_device *adev = smu->adev;
>+
>+	smu->funcs = &smu_v12_0_funcs;
>+
>+	switch (adev->asic_type) {
>+	case CHIP_RENOIR:
>+		renoir_set_ppt_funcs(smu);
>+		break;
>+	default:
>+		pr_warn("Unknown asic for smu12\n");
>+	}
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/vega20_ppt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
>--- linux-5.3-rc6/drivers/gpu/drm/amd/powerplay/vega20_ppt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/amd/powerplay/vega20_ppt.c	2019-08-31 15:01:11.939736175 -0500
>@@ -47,7 +47,7 @@
> #define CTF_OFFSET_HBM			5
> 
> #define MSG_MAP(msg) \
>-	[SMU_MSG_##msg] = PPSMC_MSG_##msg
>+	[SMU_MSG_##msg] = {1, PPSMC_MSG_##msg}
> 
> #define SMC_DPM_FEATURE (FEATURE_DPM_PREFETCHER_MASK | \
> 			 FEATURE_DPM_GFXCLK_MASK | \
>@@ -59,7 +59,7 @@
> 			 FEATURE_DPM_LINK_MASK | \
> 			 FEATURE_DPM_DCEFCLK_MASK)
> 
>-static int vega20_message_map[SMU_MSG_MAX_COUNT] = {
>+static struct smu_11_0_cmn2aisc_mapping vega20_message_map[SMU_MSG_MAX_COUNT] = {
> 	MSG_MAP(TestMessage),
> 	MSG_MAP(GetSmuVersion),
> 	MSG_MAP(GetDriverIfVersion),
>@@ -145,7 +145,7 @@
> 	MSG_MAP(GetAVFSVoltageByDpm),
> };
> 
>-static int vega20_clk_map[SMU_CLK_COUNT] = {
>+static struct smu_11_0_cmn2aisc_mapping vega20_clk_map[SMU_CLK_COUNT] = {
> 	CLK_MAP(GFXCLK, PPCLK_GFXCLK),
> 	CLK_MAP(VCLK, PPCLK_VCLK),
> 	CLK_MAP(DCLK, PPCLK_DCLK),
>@@ -159,7 +159,7 @@
> 	CLK_MAP(FCLK, PPCLK_FCLK),
> };
> 
>-static int vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
>+static struct smu_11_0_cmn2aisc_mapping vega20_feature_mask_map[SMU_FEATURE_COUNT] = {
> 	FEA_MAP(DPM_PREFETCHER),
> 	FEA_MAP(DPM_GFXCLK),
> 	FEA_MAP(DPM_UCLK),
>@@ -195,7 +195,7 @@
> 	FEA_MAP(XGMI),
> };
> 
>-static int vega20_table_map[SMU_TABLE_COUNT] = {
>+static struct smu_11_0_cmn2aisc_mapping vega20_table_map[SMU_TABLE_COUNT] = {
> 	TAB_MAP(PPTABLE),
> 	TAB_MAP(WATERMARKS),
> 	TAB_MAP(AVFS),
>@@ -208,12 +208,12 @@
> 	TAB_MAP(OVERDRIVE),
> };
> 
>-static int vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
>+static struct smu_11_0_cmn2aisc_mapping vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
> 	PWR_MAP(AC),
> 	PWR_MAP(DC),
> };
> 
>-static int vega20_workload_map[] = {
>+static struct smu_11_0_cmn2aisc_mapping vega20_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
> 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,	WORKLOAD_DEFAULT_BIT),
> 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,		WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
> 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,		WORKLOAD_PPLIB_POWER_SAVING_BIT),
>@@ -225,79 +225,92 @@
> 
> static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
> {
>-	int val;
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
> 	if (index >= SMU_TABLE_COUNT)
> 		return -EINVAL;
> 
>-	val = vega20_table_map[index];
>-	if (val >= TABLE_COUNT)
>+	mapping = vega20_table_map[index];
>+	if (!(mapping.valid_mapping)) {
> 		return -EINVAL;
>+	}
> 
>-	return val;
>+	return mapping.map_to;
> }
> 
> static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index)
> {
>-	int val;
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
> 	if (index >= SMU_POWER_SOURCE_COUNT)
> 		return -EINVAL;
> 
>-	val = vega20_pwr_src_map[index];
>-	if (val >= POWER_SOURCE_COUNT)
>+	mapping = vega20_pwr_src_map[index];
>+	if (!(mapping.valid_mapping)) {
> 		return -EINVAL;
>+	}
> 
>-	return val;
>+	return mapping.map_to;
> }
> 
> static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index)
> {
>-	int val;
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
> 	if (index >= SMU_FEATURE_COUNT)
> 		return -EINVAL;
> 
>-	val = vega20_feature_mask_map[index];
>-	if (val > 64)
>+	mapping = vega20_feature_mask_map[index];
>+	if (!(mapping.valid_mapping)) {
> 		return -EINVAL;
>+	}
> 
>-	return val;
>+	return mapping.map_to;
> }
> 
> static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index)
> {
>-	int val;
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
> 	if (index >= SMU_CLK_COUNT)
> 		return -EINVAL;
> 
>-	val = vega20_clk_map[index];
>-	if (val >= PPCLK_COUNT)
>+	mapping = vega20_clk_map[index];
>+	if (!(mapping.valid_mapping)) {
> 		return -EINVAL;
>+	}
> 
>-	return val;
>+	return mapping.map_to;
> }
> 
> static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
> {
>-	int val;
>+	struct smu_11_0_cmn2aisc_mapping mapping;
> 
> 	if (index >= SMU_MSG_MAX_COUNT)
> 		return -EINVAL;
> 
>-	val = vega20_message_map[index];
>-	if (val > PPSMC_Message_Count)
>+	mapping = vega20_message_map[index];
>+	if (!(mapping.valid_mapping)) {
> 		return -EINVAL;
>+	}
> 
>-	return val;
>+	return mapping.map_to;
> }
> 
> static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
> {
>-	int val;
>+	struct smu_11_0_cmn2aisc_mapping mapping;
>+
> 	if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
> 		return -EINVAL;
> 
>-	val = vega20_workload_map[profile];
>+	mapping = vega20_workload_map[profile];
>+	if (!(mapping.valid_mapping)) {
>+		return -EINVAL;
>+	}
> 
>-	return val;
>+	return mapping.map_to;
> }
> 
> static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
>@@ -1770,7 +1783,7 @@
> {
> 	DpmActivityMonitorCoeffInt_t activity_monitor;
> 	uint32_t i, size = 0;
>-	uint16_t workload_type = 0;
>+	int16_t workload_type = 0;
> 	static const char *profile_name[] = {
> 					"BOOTUP_DEFAULT",
> 					"3D_FULL_SCREEN",
>@@ -1803,6 +1816,9 @@
> 	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
> 		/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
> 		workload_type = smu_workload_get_type(smu, i);
>+		if (workload_type < 0)
>+			return -EINVAL;
>+
> 		result = smu_update_table(smu,
> 					  SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
> 					  (void *)(&activity_monitor), false);
>@@ -1955,6 +1971,8 @@
> 
> 	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
> 	workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
>+	if (workload_type < 0)
>+		return -EINVAL;
> 	smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
> 				    1 << workload_type);
> 
>@@ -2840,157 +2858,6 @@
> 	return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
> }
> 
>-static int vega20_get_enabled_smc_features(struct smu_context *smu,
>-		uint64_t *features_enabled)
>-{
>-	uint32_t feature_mask[2] = {0, 0};
>-	int ret = 0;
>-
>-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
>-	if (ret)
>-		return ret;
>-
>-	*features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
>-			(((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
>-
>-	return ret;
>-}
>-
>-static int vega20_enable_smc_features(struct smu_context *smu,
>-		bool enable, uint64_t feature_mask)
>-{
>-	uint32_t smu_features_low, smu_features_high;
>-	int ret = 0;
>-
>-	smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
>-	smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
>-
>-	if (enable) {
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
>-						  smu_features_low);
>-		if (ret)
>-			return ret;
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
>-						  smu_features_high);
>-		if (ret)
>-			return ret;
>-	} else {
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
>-						  smu_features_low);
>-		if (ret)
>-			return ret;
>-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
>-						  smu_features_high);
>-		if (ret)
>-			return ret;
>-	}
>-
>-	return 0;
>-
>-}
>-
>-static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
>-{
>-	static const char *ppfeature_name[] = {
>-				"DPM_PREFETCHER",
>-				"GFXCLK_DPM",
>-				"UCLK_DPM",
>-				"SOCCLK_DPM",
>-				"UVD_DPM",
>-				"VCE_DPM",
>-				"ULV",
>-				"MP0CLK_DPM",
>-				"LINK_DPM",
>-				"DCEFCLK_DPM",
>-				"GFXCLK_DS",
>-				"SOCCLK_DS",
>-				"LCLK_DS",
>-				"PPT",
>-				"TDC",
>-				"THERMAL",
>-				"GFX_PER_CU_CG",
>-				"RM",
>-				"DCEFCLK_DS",
>-				"ACDC",
>-				"VR0HOT",
>-				"VR1HOT",
>-				"FW_CTF",
>-				"LED_DISPLAY",
>-				"FAN_CONTROL",
>-				"GFX_EDC",
>-				"GFXOFF",
>-				"CG",
>-				"FCLK_DPM",
>-				"FCLK_DS",
>-				"MP1CLK_DS",
>-				"MP0CLK_DS",
>-				"XGMI",
>-				"ECC"};
>-	static const char *output_title[] = {
>-				"FEATURES",
>-				"BITMASK",
>-				"ENABLEMENT"};
>-	uint64_t features_enabled;
>-	int i;
>-	int ret = 0;
>-	int size = 0;
>-
>-	ret = vega20_get_enabled_smc_features(smu, &features_enabled);
>-	if (ret)
>-		return ret;
>-
>-	size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
>-	size += sprintf(buf + size, "%-19s %-22s %s\n",
>-				output_title[0],
>-				output_title[1],
>-				output_title[2]);
>-	for (i = 0; i < GNLD_FEATURES_MAX; i++) {
>-		size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
>-					ppfeature_name[i],
>-					1ULL << i,
>-					(features_enabled & (1ULL << i)) ? "Y" : "N");
>-	}
>-
>-	return size;
>-}
>-
>-static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
>-{
>-	uint64_t features_enabled;
>-	uint64_t features_to_enable;
>-	uint64_t features_to_disable;
>-	int ret = 0;
>-
>-	if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
>-		return -EINVAL;
>-
>-	ret = vega20_get_enabled_smc_features(smu, &features_enabled);
>-	if (ret)
>-		return ret;
>-
>-	features_to_disable =
>-		features_enabled & ~new_ppfeature_masks;
>-	features_to_enable =
>-		~features_enabled & new_ppfeature_masks;
>-
>-	pr_debug("features_to_disable 0x%llx\n", features_to_disable);
>-	pr_debug("features_to_enable 0x%llx\n", features_to_enable);
>-
>-	if (features_to_disable) {
>-		ret = vega20_enable_smc_features(smu, false, features_to_disable);
>-		if (ret)
>-			return ret;
>-	}
>-
>-	if (features_to_enable) {
>-		ret = vega20_enable_smc_features(smu, true, features_to_enable);
>-		if (ret)
>-			return ret;
>-	}
>-
>-	return 0;
>-}
>-
> static bool vega20_is_dpm_running(struct smu_context *smu)
> {
> 	int ret = 0;
>@@ -3050,6 +2917,7 @@
> 
> static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
> {
>+	uint32_t smu_version;
> 	int ret = 0;
> 	SmuMetrics_t metrics;
> 
>@@ -3060,7 +2928,15 @@
> 	if (ret)
> 		return ret;
> 
>-	*value = metrics.CurrSocketPower << 8;
>+	ret = smu_get_smc_version(smu, NULL, &smu_version);
>+	if (ret)
>+		return ret;
>+
>+	/* For the 40.46 release, they changed the value name */
>+	if (smu_version == 0x282e00)
>+		*value = metrics.AverageSocketPower << 8;
>+	else
>+		*value = metrics.CurrSocketPower << 8;
> 
> 	return 0;
> }
>@@ -3144,6 +3020,9 @@
> 	struct smu_table_context *table_context = &smu->smu_table;
> 	PPTable_t *pptable = table_context->driver_pptable;
> 
>+	if(!data || !size)
>+		return -EINVAL;
>+
> 	switch (sensor) {
> 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
> 		*(uint32_t *)data = pptable->FanMaximumRpm;
>@@ -3167,7 +3046,7 @@
> 		*size = 4;
> 		break;
> 	default:
>-		return -EINVAL;
>+		ret = smu_smc_read_sensor(smu, sensor, data, size);
> 	}
> 
> 	return ret;
>@@ -3243,14 +3122,18 @@
> 	if (!range || !powerplay_table)
> 		return -EINVAL;
> 
>-	/* The unit is temperature */
>-	range->min = 0;
>-	range->max = powerplay_table->usSoftwareShutdownTemp;
>-	range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE);
>-	range->hotspot_crit_max = pptable->ThotspotLimit;
>-	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT);
>-	range->mem_crit_max = pptable->ThbmLimit;
>-	range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM);
>+	range->max = powerplay_table->usSoftwareShutdownTemp *
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+	range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+	range->hotspot_crit_max = pptable->ThotspotLimit *
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+	range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+	range->mem_crit_max = pptable->ThbmLimit *
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>+	range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM) *
>+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> 
> 
> 	return 0;
>@@ -3293,8 +3176,6 @@
> 	.force_dpm_limit_value = vega20_force_dpm_limit_value,
> 	.unforce_dpm_levels = vega20_unforce_dpm_levels,
> 	.get_profiling_clk_mask = vega20_get_profiling_clk_mask,
>-	.set_ppfeature_status = vega20_set_ppfeature_status,
>-	.get_ppfeature_status = vega20_get_ppfeature_status,
> 	.is_dpm_running = vega20_is_dpm_running,
> 	.set_thermal_fan_table = vega20_set_thermal_fan_table,
> 	.get_fan_speed_percent = vega20_get_fan_speed_percent,
>@@ -3308,6 +3189,5 @@
> 	struct smu_table_context *smu_table = &smu->smu_table;
> 
> 	smu->ppt_funcs = &vega20_ppt_funcs;
>-	smu->smc_if_version = SMU11_DRIVER_IF_VERSION;
> 	smu_table->table_count = TABLE_COUNT;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arc/arcpgu_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/arc/arcpgu_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/arc/arcpgu_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arc/arcpgu_drv.c	2019-08-31 15:01:11.939736175 -0500
>@@ -135,8 +135,7 @@
> #endif
> 
> static struct drm_driver arcpgu_drm_driver = {
>-	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
>-			   DRIVER_ATOMIC,
>+	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> 	.name = "arcpgu",
> 	.desc = "ARC PGU Controller",
> 	.date = "20160219",
>@@ -150,8 +149,6 @@
> 	.gem_free_object_unlocked = drm_gem_cma_free_object,
> 	.gem_print_info = drm_gem_cma_print_info,
> 	.gem_vm_ops = &drm_gem_cma_vm_ops,
>-	.gem_prime_export = drm_gem_prime_export,
>-	.gem_prime_import = drm_gem_prime_import,
> 	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap = drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
>--- linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c	2019-08-31 15:01:11.939736175 -0500
>@@ -4,8 +4,6 @@
>  * Author: James.Qian.Wang <james.qian.wang@arm.com>
>  *
>  */
>-
>-#include <drm/drm_print.h>
> #include "d71_dev.h"
> #include "komeda_kms.h"
> #include "malidp_io.h"
>@@ -804,7 +802,7 @@
> 		denominator = (mode->htotal - 1) * v_out -  2 * v_in;
> 	}
> 
>-	return aclk_rate * denominator >= mode->clock * 1000 * fraction ?
>+	return aclk_rate * denominator >= mode->crtc_clock * 1000 * fraction ?
> 	       0 : -EINVAL;
> }
> 
>@@ -1032,21 +1030,31 @@
> 				    struct komeda_component_state *state)
> {
> 	struct drm_crtc_state *crtc_st = state->crtc->state;
>+	struct drm_display_mode *mode = &crtc_st->adjusted_mode;
> 	u32 __iomem *reg = c->reg;
>-	struct videomode vm;
>+	u32 hactive, hfront_porch, hback_porch, hsync_len;
>+	u32 vactive, vfront_porch, vback_porch, vsync_len;
> 	u32 value;
> 
>-	drm_display_mode_to_videomode(&crtc_st->adjusted_mode, &vm);
>-
>-	malidp_write32(reg, BS_ACTIVESIZE, HV_SIZE(vm.hactive, vm.vactive));
>-	malidp_write32(reg, BS_HINTERVALS, BS_H_INTVALS(vm.hfront_porch,
>-							vm.hback_porch));
>-	malidp_write32(reg, BS_VINTERVALS, BS_V_INTVALS(vm.vfront_porch,
>-							vm.vback_porch));
>-
>-	value = BS_SYNC_VSW(vm.vsync_len) | BS_SYNC_HSW(vm.hsync_len);
>-	value |= vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? BS_SYNC_VSP : 0;
>-	value |= vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? BS_SYNC_HSP : 0;
>+	hactive = mode->crtc_hdisplay;
>+	hfront_porch = mode->crtc_hsync_start - mode->crtc_hdisplay;
>+	hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
>+	hback_porch = mode->crtc_htotal - mode->crtc_hsync_end;
>+
>+	vactive = mode->crtc_vdisplay;
>+	vfront_porch = mode->crtc_vsync_start - mode->crtc_vdisplay;
>+	vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
>+	vback_porch = mode->crtc_vtotal - mode->crtc_vsync_end;
>+
>+	malidp_write32(reg, BS_ACTIVESIZE, HV_SIZE(hactive, vactive));
>+	malidp_write32(reg, BS_HINTERVALS, BS_H_INTVALS(hfront_porch,
>+							hback_porch));
>+	malidp_write32(reg, BS_VINTERVALS, BS_V_INTVALS(vfront_porch,
>+							vback_porch));
>+
>+	value = BS_SYNC_VSW(vsync_len) | BS_SYNC_HSW(hsync_len);
>+	value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? BS_SYNC_VSP : 0;
>+	value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? BS_SYNC_HSP : 0;
> 	malidp_write32(reg, BS_SYNC, value);
> 
> 	malidp_write32(reg, BS_PROG_LINE, D71_DEFAULT_PREPRETCH_LINE - 1);
>@@ -1054,6 +1062,10 @@
> 
> 	/* configure bs control register */
> 	value = BS_CTRL_EN | BS_CTRL_VM;
>+	if (c->pipeline->dual_link) {
>+		malidp_write32(reg, BS_DRIFT_TO, hfront_porch + 16);
>+		value |= BS_CTRL_DL;
>+	}
> 
> 	malidp_write32(reg, BLK_CONTROL, value);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c	2019-08-31 15:01:11.939736175 -0500
>@@ -27,8 +27,8 @@
> 		return;
> 	}
> 
>-	pxlclk = kcrtc_st->base.adjusted_mode.clock * 1000;
>-	aclk = komeda_calc_aclk(kcrtc_st);
>+	pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000;
>+	aclk = komeda_crtc_get_aclk(kcrtc_st);
> 
> 	kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk);
> }
>@@ -74,14 +74,6 @@
> 	return 0;
> }
> 
>-unsigned long komeda_calc_aclk(struct komeda_crtc_state *kcrtc_st)
>-{
>-	struct komeda_dev *mdev = kcrtc_st->base.crtc->dev->dev_private;
>-	unsigned long pxlclk = kcrtc_st->base.adjusted_mode.clock;
>-
>-	return clk_round_rate(mdev->aclk, pxlclk * 1000);
>-}
>-
> /* For active a crtc, mainly need two parts of preparation
>  * 1. adjust display operation mode.
>  * 2. enable needed clk
>@@ -92,7 +84,7 @@
> 	struct komeda_dev *mdev = kcrtc->base.dev->dev_private;
> 	struct komeda_pipeline *master = kcrtc->master;
> 	struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(kcrtc->base.state);
>-	unsigned long pxlclk_rate = kcrtc_st->base.adjusted_mode.clock * 1000;
>+	struct drm_display_mode *mode = &kcrtc_st->base.adjusted_mode;
> 	u32 new_mode;
> 	int err;
> 
>@@ -118,7 +110,7 @@
> 	 * to enable it again.
> 	 */
> 	if (new_mode != KOMEDA_MODE_DUAL_DISP) {
>-		err = clk_set_rate(mdev->aclk, komeda_calc_aclk(kcrtc_st));
>+		err = clk_set_rate(mdev->aclk, komeda_crtc_get_aclk(kcrtc_st));
> 		if (err)
> 			DRM_ERROR("failed to set aclk.\n");
> 		err = clk_prepare_enable(mdev->aclk);
>@@ -126,7 +118,7 @@
> 			DRM_ERROR("failed to enable aclk.\n");
> 	}
> 
>-	err = clk_set_rate(master->pxlclk, pxlclk_rate);
>+	err = clk_set_rate(master->pxlclk, mode->crtc_clock * 1000);
> 	if (err)
> 		DRM_ERROR("failed to set pxlclk for pipe%d\n", master->id);
> 	err = clk_prepare_enable(master->pxlclk);
>@@ -342,29 +334,58 @@
> 	komeda_crtc_do_flush(crtc, old);
> }
> 
>+/* Returns the minimum frequency of the aclk rate (main engine clock) in Hz */
>+static unsigned long
>+komeda_calc_min_aclk_rate(struct komeda_crtc *kcrtc,
>+			  unsigned long pxlclk)
>+{
>+	/* Once dual-link one display pipeline drives two display outputs,
>+	 * the aclk needs run on the double rate of pxlclk
>+	 */
>+	if (kcrtc->master->dual_link)
>+		return pxlclk * 2;
>+	else
>+		return pxlclk;
>+}
>+
>+/* Get current aclk rate that specified by state */
>+unsigned long komeda_crtc_get_aclk(struct komeda_crtc_state *kcrtc_st)
>+{
>+	struct drm_crtc *crtc = kcrtc_st->base.crtc;
>+	struct komeda_dev *mdev = crtc->dev->dev_private;
>+	unsigned long pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000;
>+	unsigned long min_aclk;
>+
>+	min_aclk = komeda_calc_min_aclk_rate(to_kcrtc(crtc), pxlclk);
>+
>+	return clk_round_rate(mdev->aclk, min_aclk);
>+}
>+
> static enum drm_mode_status
> komeda_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *m)
> {
> 	struct komeda_dev *mdev = crtc->dev->dev_private;
> 	struct komeda_crtc *kcrtc = to_kcrtc(crtc);
> 	struct komeda_pipeline *master = kcrtc->master;
>-	long mode_clk, pxlclk;
>+	unsigned long min_pxlclk, min_aclk;
> 
> 	if (m->flags & DRM_MODE_FLAG_INTERLACE)
> 		return MODE_NO_INTERLACE;
> 
>-	mode_clk = m->clock * 1000;
>-	pxlclk = clk_round_rate(master->pxlclk, mode_clk);
>-	if (pxlclk != mode_clk) {
>-		DRM_DEBUG_ATOMIC("pxlclk doesn't support %ld Hz\n", mode_clk);
>+	min_pxlclk = m->clock * 1000;
>+	if (master->dual_link)
>+		min_pxlclk /= 2;
>+
>+	if (min_pxlclk != clk_round_rate(master->pxlclk, min_pxlclk)) {
>+		DRM_DEBUG_ATOMIC("pxlclk doesn't support %lu Hz\n", min_pxlclk);
> 
> 		return MODE_NOCLOCK;
> 	}
> 
>-	/* main engine clock must be faster than pxlclk*/
>-	if (clk_round_rate(mdev->aclk, mode_clk) < pxlclk) {
>-		DRM_DEBUG_ATOMIC("engine clk can't satisfy the requirement of %s-clk: %ld.\n",
>-				 m->name, pxlclk);
>+	min_aclk = komeda_calc_min_aclk_rate(to_kcrtc(crtc), min_pxlclk);
>+	if (clk_round_rate(mdev->aclk, min_aclk) < min_aclk) {
>+		DRM_DEBUG_ATOMIC("engine clk can't satisfy the requirement of %s-clk: %lu.\n",
>+				 m->name, min_pxlclk);
> 
> 		return MODE_CLOCK_HIGH;
> 	}
>@@ -377,10 +398,22 @@
> 				   struct drm_display_mode *adjusted_mode)
> {
> 	struct komeda_crtc *kcrtc = to_kcrtc(crtc);
>-	struct komeda_pipeline *master = kcrtc->master;
>-	long mode_clk = m->clock * 1000;
>+	unsigned long clk_rate;
> 
>-	adjusted_mode->clock = clk_round_rate(master->pxlclk, mode_clk) / 1000;
>+	drm_mode_set_crtcinfo(adjusted_mode, 0);
>+	/* In dual link half the horizontal settings */
>+	if (kcrtc->master->dual_link) {
>+		adjusted_mode->crtc_clock /= 2;
>+		adjusted_mode->crtc_hdisplay /= 2;
>+		adjusted_mode->crtc_hsync_start /= 2;
>+		adjusted_mode->crtc_hsync_end /= 2;
>+		adjusted_mode->crtc_htotal /= 2;
>+	}
>+
>+	clk_rate = adjusted_mode->crtc_clock * 1000;
>+	/* crtc_clock will be used as the komeda output pixel clock */
>+	adjusted_mode->crtc_clock = clk_round_rate(kcrtc->master->pxlclk,
>+						   clk_rate) / 1000;
> 
> 	return true;
> }
>@@ -488,10 +521,8 @@
> 		else
> 			sprintf(str, "None");
> 
>-		DRM_INFO("crtc%d: master(pipe-%d) slave(%s) output: %s.\n",
>-			 kms->n_crtcs, master->id, str,
>-			 master->of_output_dev ?
>-			 master->of_output_dev->full_name : "None");
>+		DRM_INFO("CRTC-%d: master(pipe-%d) slave(%s).\n",
>+			 kms->n_crtcs, master->id, str);
> 
> 		kms->n_crtcs++;
> 	}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_dev.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_dev.c
>--- linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_dev.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_dev.c	2019-08-31 15:01:12.251736203 -0500
>@@ -122,11 +122,14 @@
> 	pipe->pxlclk = clk;
> 
> 	/* enum ports */
>-	pipe->of_output_dev =
>+	pipe->of_output_links[0] =
> 		of_graph_get_remote_node(np, KOMEDA_OF_PORT_OUTPUT, 0);
>+	pipe->of_output_links[1] =
>+		of_graph_get_remote_node(np, KOMEDA_OF_PORT_OUTPUT, 1);
> 	pipe->of_output_port =
> 		of_graph_get_port_by_id(np, KOMEDA_OF_PORT_OUTPUT);
> 
>+	pipe->dual_link = pipe->of_output_links[0] && pipe->of_output_links[1];
> 	pipe->of_node = np;
> 
> 	return 0;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_drv.c	2019-08-31 15:01:11.939736175 -0500
>@@ -83,11 +83,12 @@
> 
> static void komeda_add_slave(struct device *master,
> 			     struct component_match **match,
>-			     struct device_node *np, int port)
>+			     struct device_node *np,
>+			     u32 port, u32 endpoint)
> {
> 	struct device_node *remote;
> 
>-	remote = of_graph_get_remote_node(np, port, 0);
>+	remote = of_graph_get_remote_node(np, port, endpoint);
> 	if (remote) {
> 		drm_of_component_match_add(master, match, compare_of, remote);
> 		of_node_put(remote);
>@@ -108,7 +109,8 @@
> 			continue;
> 
> 		/* add connector */
>-		komeda_add_slave(dev, &match, child, KOMEDA_OF_PORT_OUTPUT);
>+		komeda_add_slave(dev, &match, child, KOMEDA_OF_PORT_OUTPUT, 0);
>+		komeda_add_slave(dev, &match, child, KOMEDA_OF_PORT_OUTPUT, 1);
> 	}
> 
> 	return component_master_add_with_match(dev, &komeda_master_ops, match);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_kms.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_kms.c
>--- linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_kms.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_kms.c	2019-08-31 15:01:12.250736203 -0500
>@@ -56,16 +56,13 @@
> }
> 
> static struct drm_driver komeda_kms_driver = {
>-	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
>-			   DRIVER_PRIME | DRIVER_HAVE_IRQ,
>+	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.lastclose			= drm_fb_helper_lastclose,
> 	.gem_free_object_unlocked	= drm_gem_cma_free_object,
> 	.gem_vm_ops			= &drm_gem_cma_vm_ops,
> 	.dumb_create			= komeda_gem_cma_dumb_create,
> 	.prime_handle_to_fd		= drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle		= drm_gem_prime_fd_to_handle,
>-	.gem_prime_export		= drm_gem_prime_export,
>-	.gem_prime_import		= drm_gem_prime_import,
> 	.gem_prime_get_sg_table		= drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table	= drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap			= drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_kms.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
>--- linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_kms.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_kms.h	2019-08-31 15:01:11.939736175 -0500
>@@ -14,8 +14,6 @@
> #include <drm/drm_device.h>
> #include <drm/drm_writeback.h>
> #include <drm/drm_print.h>
>-#include <video/videomode.h>
>-#include <video/display_timing.h>
> 
> /**
>  * struct komeda_plane - komeda instance of drm_plane
>@@ -168,7 +166,7 @@
> 		return !!(rotation & DRM_MODE_REFLECT_X);
> }
> 
>-unsigned long komeda_calc_aclk(struct komeda_crtc_state *kcrtc_st);
>+unsigned long komeda_crtc_get_aclk(struct komeda_crtc_state *kcrtc_st);
> 
> int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms, struct komeda_dev *mdev);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c
>--- linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c	2019-08-31 15:01:11.939736175 -0500
>@@ -54,7 +54,8 @@
> 
> 	clk_put(pipe->pxlclk);
> 
>-	of_node_put(pipe->of_output_dev);
>+	of_node_put(pipe->of_output_links[0]);
>+	of_node_put(pipe->of_output_links[1]);
> 	of_node_put(pipe->of_output_port);
> 	of_node_put(pipe->of_node);
> 
>@@ -246,9 +247,15 @@
> 	struct komeda_component *c;
> 	int id;
> 
>-	DRM_INFO("Pipeline-%d: n_layers: %d, n_scalers: %d, output: %s\n",
>+	DRM_INFO("Pipeline-%d: n_layers: %d, n_scalers: %d, output: %s.\n",
> 		 pipe->id, pipe->n_layers, pipe->n_scalers,
>-		 pipe->of_output_dev ? pipe->of_output_dev->full_name : "none");
>+		 pipe->dual_link ? "dual-link" : "single-link");
>+	DRM_INFO("	output_link[0]: %s.\n",
>+		 pipe->of_output_links[0] ?
>+		 pipe->of_output_links[0]->full_name : "none");
>+	DRM_INFO("	output_link[1]: %s.\n",
>+		 pipe->of_output_links[1] ?
>+		 pipe->of_output_links[1]->full_name : "none");
> 
> 	dp_for_each_set_bit(id, pipe->avail_comps) {
> 		c = komeda_pipeline_get_component(pipe, id);
>@@ -305,6 +312,12 @@
> 
> 		layer->right = komeda_get_layer_split_right_layer(pipe, layer);
> 	}
>+
>+	if (pipe->dual_link && !pipe->ctrlr->supports_dual_link) {
>+		pipe->dual_link = false;
>+		DRM_WARN("PIPE-%d doesn't support dual-link, ignore DT dual-link configuration.\n",
>+			 pipe->id);
>+	}
> }
> 
> /* if pipeline_A accept another pipeline_B's component as input, treat
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
>--- linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h	2019-08-31 15:01:11.939736175 -0500
>@@ -416,8 +416,10 @@
> 	struct device_node *of_node;
> 	/** @of_output_port: pipeline output port */
> 	struct device_node *of_output_port;
>-	/** @of_output_dev: output connector device node */
>-	struct device_node *of_output_dev;
>+	/** @of_output_links: output connector device nodes */
>+	struct device_node *of_output_links[2];
>+	/** @dual_link: true if of_output_links[0] and [1] are both valid */
>+	bool dual_link;
> };
> 
> /**
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
>--- linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c	2019-08-31 15:01:11.940736175 -0500
>@@ -473,7 +473,7 @@
> 
> 		err = pipe->funcs->downscaling_clk_check(pipe,
> 					&kcrtc_st->base.adjusted_mode,
>-					komeda_calc_aclk(kcrtc_st), dflow);
>+					komeda_crtc_get_aclk(kcrtc_st), dflow);
> 		if (err) {
> 			DRM_DEBUG_ATOMIC("aclk can't satisfy the clock requirement of the downscaling\n");
> 			return err;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/arm/display/komeda/komeda_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/display/komeda/komeda_plane.c	2019-08-31 15:01:11.940736175 -0500
>@@ -158,7 +158,7 @@
> static struct drm_plane_state *
> komeda_plane_atomic_duplicate_state(struct drm_plane *plane)
> {
>-	struct komeda_plane_state *new, *old;
>+	struct komeda_plane_state *new;
> 
> 	if (WARN_ON(!plane->state))
> 		return NULL;
>@@ -169,8 +169,6 @@
> 
> 	__drm_atomic_helper_plane_duplicate_state(plane, &new->base);
> 
>-	old = to_kplane_st(plane->state);
>-
> 	return &new->base;
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/hdlcd_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/hdlcd_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/arm/hdlcd_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/hdlcd_drv.c	2019-08-31 15:01:11.940736175 -0500
>@@ -229,9 +229,7 @@
> DEFINE_DRM_GEM_CMA_FOPS(fops);
> 
> static struct drm_driver hdlcd_driver = {
>-	.driver_features = DRIVER_GEM |
>-			   DRIVER_MODESET | DRIVER_PRIME |
>-			   DRIVER_ATOMIC,
>+	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.irq_handler = hdlcd_irq,
> 	.irq_preinstall = hdlcd_irq_preinstall,
> 	.irq_postinstall = hdlcd_irq_postinstall,
>@@ -242,8 +240,6 @@
> 	.dumb_create = drm_gem_cma_dumb_create,
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_export = drm_gem_prime_export,
>-	.gem_prime_import = drm_gem_prime_import,
> 	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap = drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/malidp_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/malidp_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/arm/malidp_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/malidp_drv.c	2019-08-31 15:01:11.940736175 -0500
>@@ -561,15 +561,12 @@
> #endif //CONFIG_DEBUG_FS
> 
> static struct drm_driver malidp_driver = {
>-	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
>-			   DRIVER_PRIME,
>+	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.gem_free_object_unlocked = drm_gem_cma_free_object,
> 	.gem_vm_ops = &drm_gem_cma_vm_ops,
> 	.dumb_create = malidp_dumb_create,
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_export = drm_gem_prime_export,
>-	.gem_prime_import = drm_gem_prime_import,
> 	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap = drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/arm/malidp_hw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/malidp_hw.c
>--- linux-5.3-rc6/drivers/gpu/drm/arm/malidp_hw.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/arm/malidp_hw.c	2019-08-31 15:01:11.940736175 -0500
>@@ -385,6 +385,7 @@
> 		switch (fmt) {
> 		case DRM_FORMAT_VUY101010:
> 			bpp = 30;
>+			break;
> 		case DRM_FORMAT_YUV420_10BIT:
> 			bpp = 15;
> 			break;
>@@ -1309,7 +1310,7 @@
> 			break;
> 		case MW_RESTART:
> 			drm_writeback_signal_completion(&malidp->mw_connector, 0);
>-			/* fall through to a new start */
>+			/* fall through - to a new start */
> 		case MW_START:
> 			/* writeback started, need to emulate one-shot mode */
> 			hw->disable_memwrite(hwdev);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/armada/armada_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/armada/armada_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/armada/armada_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/armada/armada_drv.c	2019-08-31 15:01:11.940736175 -0500
>@@ -40,8 +40,7 @@
> 	.name			= "armada-drm",
> 	.desc			= "Armada SoC DRM",
> 	.date			= "20120730",
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET |
>-				  DRIVER_PRIME | DRIVER_ATOMIC,
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.ioctls			= armada_ioctls,
> 	.fops			= &armada_drm_fops,
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/armada/armada_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/armada/armada_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/armada/armada_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/armada/armada_gem.c	2019-08-31 15:01:11.940736175 -0500
>@@ -482,8 +482,7 @@
> };
> 
> struct dma_buf *
>-armada_gem_prime_export(struct drm_device *dev, struct drm_gem_object *obj,
>-	int flags)
>+armada_gem_prime_export(struct drm_gem_object *obj, int flags)
> {
> 	DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
> 
>@@ -492,7 +491,7 @@
> 	exp_info.flags = O_RDWR;
> 	exp_info.priv = obj;
> 
>-	return drm_gem_dmabuf_export(dev, &exp_info);
>+	return drm_gem_dmabuf_export(obj->dev, &exp_info);
> }
> 
> struct drm_gem_object *
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/armada/armada_gem.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/armada/armada_gem.h
>--- linux-5.3-rc6/drivers/gpu/drm/armada/armada_gem.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/armada/armada_gem.h	2019-08-31 15:01:11.940736175 -0500
>@@ -32,8 +32,7 @@
> 	size_t);
> int armada_gem_dumb_create(struct drm_file *, struct drm_device *,
> 	struct drm_mode_create_dumb *);
>-struct dma_buf *armada_gem_prime_export(struct drm_device *dev,
>-	struct drm_gem_object *obj, int flags);
>+struct dma_buf *armada_gem_prime_export(struct drm_gem_object *obj, int flags);
> struct drm_gem_object *armada_gem_prime_import(struct drm_device *,
> 	struct dma_buf *);
> int armada_gem_map_import(struct armada_gem_object *);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c	2019-08-31 15:01:11.940736175 -0500
>@@ -194,8 +194,7 @@
> DEFINE_DRM_GEM_CMA_FOPS(fops);
> 
> static struct drm_driver aspeed_gfx_driver = {
>-	.driver_features        = DRIVER_GEM | DRIVER_MODESET |
>-				DRIVER_PRIME | DRIVER_ATOMIC,
>+	.driver_features        = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.gem_create_object	= drm_cma_gem_create_object_default_funcs,
> 	.dumb_create		= drm_gem_cma_dumb_create,
> 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ast/ast_dp501.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_dp501.c
>--- linux-5.3-rc6/drivers/gpu/drm/ast/ast_dp501.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_dp501.c	2019-08-31 15:01:11.940736175 -0500
>@@ -1,8 +1,11 @@
> // SPDX-License-Identifier: GPL-2.0
> 
>+#include <linux/delay.h>
> #include <linux/firmware.h>
>-#include <drm/drmP.h>
>+#include <linux/module.h>
>+
> #include "ast_drv.h"
>+
> MODULE_FIRMWARE("ast_dp501_fw.bin");
> 
> static int ast_load_dp501_microcode(struct drm_device *dev)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ast/ast_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/ast/ast_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_drv.c	2019-08-31 15:01:11.940736175 -0500
>@@ -25,12 +25,17 @@
> /*
>  * Authors: Dave Airlie <airlied@redhat.com>
>  */
>-#include <linux/module.h>
>+
> #include <linux/console.h>
>+#include <linux/module.h>
>+#include <linux/pci.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_crtc_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_gem_vram_helper.h>
>+#include <drm/drm_pci.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vram_mm_helper.h>
> 
> #include "ast_drv.h"
> 
>@@ -100,28 +105,21 @@
> static int ast_drm_freeze(struct drm_device *dev)
> {
> 	drm_kms_helper_poll_disable(dev);
>-
> 	pci_save_state(dev->pdev);
>+	drm_fb_helper_set_suspend_unlocked(dev->fb_helper, true);
> 
>-	console_lock();
>-	ast_fbdev_set_suspend(dev, 1);
>-	console_unlock();
> 	return 0;
> }
> 
> static int ast_drm_thaw(struct drm_device *dev)
> {
>-	int error = 0;
>-
> 	ast_post_gpu(dev);
> 
> 	drm_mode_config_reset(dev);
> 	drm_helper_resume_force_mode(dev);
>+	drm_fb_helper_set_suspend_unlocked(dev->fb_helper, false);
> 
>-	console_lock();
>-	ast_fbdev_set_suspend(dev, 0);
>-	console_unlock();
>-	return error;
>+	return 0;
> }
> 
> static int ast_drm_resume(struct drm_device *dev)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ast/ast_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/ast/ast_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_drv.h	2019-08-31 15:01:11.941736176 -0500
>@@ -28,17 +28,18 @@
> #ifndef __AST_DRV_H__
> #define __AST_DRV_H__
> 
>-#include <drm/drm_encoder.h>
>-#include <drm/drm_fb_helper.h>
>-
>-#include <drm/drm_gem.h>
>-#include <drm/drm_gem_vram_helper.h>
>-
>-#include <drm/drm_vram_mm_helper.h>
>-
>+#include <linux/types.h>
>+#include <linux/io.h>
> #include <linux/i2c.h>
> #include <linux/i2c-algo-bit.h>
> 
>+#include <drm/drm_connector.h>
>+#include <drm/drm_crtc.h>
>+#include <drm/drm_encoder.h>
>+#include <drm/drm_mode.h>
>+#include <drm/drm_framebuffer.h>
>+#include <drm/drm_fb_helper.h>
>+
> #define DRIVER_AUTHOR		"Dave Airlie"
> 
> #define DRIVER_NAME		"ast"
>@@ -81,8 +82,6 @@
> #define AST_DRAM_4Gx16   7
> #define AST_DRAM_8Gx16   8
> 
>-struct ast_fbdev;
>-
> struct ast_private {
> 	struct drm_device *dev;
> 
>@@ -96,8 +95,6 @@
> 	uint32_t mclk;
> 	uint32_t vram_size;
> 
>-	struct ast_fbdev *fbdev;
>-
> 	int fb_mtrr;
> 
> 	struct drm_gem_object *cursor_cache;
>@@ -239,24 +236,9 @@
> 	struct drm_encoder base;
> };
> 
>-struct ast_framebuffer {
>-	struct drm_framebuffer base;
>-	struct drm_gem_object *obj;
>-};
>-
>-struct ast_fbdev {
>-	struct drm_fb_helper helper; /* must be first */
>-	struct ast_framebuffer afb;
>-	void *sysram;
>-	int size;
>-	int x1, y1, x2, y2; /* dirty rect */
>-	spinlock_t dirty_lock;
>-};
>-
> #define to_ast_crtc(x) container_of(x, struct ast_crtc, base)
> #define to_ast_connector(x) container_of(x, struct ast_connector, base)
> #define to_ast_encoder(x) container_of(x, struct ast_encoder, base)
>-#define to_ast_framebuffer(x) container_of(x, struct ast_framebuffer, base)
> 
> struct ast_vbios_stdtable {
> 	u8 misc;
>@@ -296,16 +278,6 @@
> extern int ast_mode_init(struct drm_device *dev);
> extern void ast_mode_fini(struct drm_device *dev);
> 
>-int ast_framebuffer_init(struct drm_device *dev,
>-			 struct ast_framebuffer *ast_fb,
>-			 const struct drm_mode_fb_cmd2 *mode_cmd,
>-			 struct drm_gem_object *obj);
>-
>-int ast_fbdev_init(struct drm_device *dev);
>-void ast_fbdev_fini(struct drm_device *dev);
>-void ast_fbdev_set_suspend(struct drm_device *dev, int state);
>-void ast_fbdev_set_base(struct ast_private *ast, unsigned long gpu_addr);
>-
> #define AST_MM_ALIGN_SHIFT 4
> #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ast/ast_fb.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_fb.c
>--- linux-5.3-rc6/drivers/gpu/drm/ast/ast_fb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_fb.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,346 +0,0 @@
>-/*
>- * Copyright 2012 Red Hat Inc.
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the
>- * "Software"), to deal in the Software without restriction, including
>- * without limitation the rights to use, copy, modify, merge, publish,
>- * distribute, sub license, and/or sell copies of the Software, and to
>- * permit persons to whom the Software is furnished to do so, subject to
>- * the following conditions:
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
>- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
>- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
>- * USE OR OTHER DEALINGS IN THE SOFTWARE.
>- *
>- * The above copyright notice and this permission notice (including the
>- * next paragraph) shall be included in all copies or substantial portions
>- * of the Software.
>- *
>- */
>-/*
>- * Authors: Dave Airlie <airlied@redhat.com>
>- */
>-#include <linux/module.h>
>-#include <linux/kernel.h>
>-#include <linux/errno.h>
>-#include <linux/string.h>
>-#include <linux/mm.h>
>-#include <linux/tty.h>
>-#include <linux/sysrq.h>
>-#include <linux/delay.h>
>-#include <linux/init.h>
>-
>-
>-#include <drm/drmP.h>
>-#include <drm/drm_crtc.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_util.h>
>-#include <drm/drm_crtc_helper.h>
>-
>-#include "ast_drv.h"
>-
>-static void ast_dirty_update(struct ast_fbdev *afbdev,
>-			     int x, int y, int width, int height)
>-{
>-	int i;
>-	struct drm_gem_vram_object *gbo;
>-	int src_offset, dst_offset;
>-	int bpp = afbdev->afb.base.format->cpp[0];
>-	int ret;
>-	u8 *dst;
>-	bool unmap = false;
>-	bool store_for_later = false;
>-	int x2, y2;
>-	unsigned long flags;
>-
>-	gbo = drm_gem_vram_of_gem(afbdev->afb.obj);
>-
>-	if (drm_can_sleep()) {
>-		/* We pin the BO so it won't be moved during the
>-		 * update. The actual location, video RAM or system
>-		 * memory, is not important.
>-		 */
>-		ret = drm_gem_vram_pin(gbo, 0);
>-		if (ret) {
>-			if (ret != -EBUSY)
>-				return;
>-			store_for_later = true;
>-		}
>-	} else {
>-		store_for_later = true;
>-	}
>-
>-	x2 = x + width - 1;
>-	y2 = y + height - 1;
>-	spin_lock_irqsave(&afbdev->dirty_lock, flags);
>-
>-	if (afbdev->y1 < y)
>-		y = afbdev->y1;
>-	if (afbdev->y2 > y2)
>-		y2 = afbdev->y2;
>-	if (afbdev->x1 < x)
>-		x = afbdev->x1;
>-	if (afbdev->x2 > x2)
>-		x2 = afbdev->x2;
>-
>-	if (store_for_later) {
>-		afbdev->x1 = x;
>-		afbdev->x2 = x2;
>-		afbdev->y1 = y;
>-		afbdev->y2 = y2;
>-		spin_unlock_irqrestore(&afbdev->dirty_lock, flags);
>-		return;
>-	}
>-
>-	afbdev->x1 = afbdev->y1 = INT_MAX;
>-	afbdev->x2 = afbdev->y2 = 0;
>-	spin_unlock_irqrestore(&afbdev->dirty_lock, flags);
>-
>-	dst = drm_gem_vram_kmap(gbo, false, NULL);
>-	if (IS_ERR(dst)) {
>-		DRM_ERROR("failed to kmap fb updates\n");
>-		goto out;
>-	} else if (!dst) {
>-		dst = drm_gem_vram_kmap(gbo, true, NULL);
>-		if (IS_ERR(dst)) {
>-			DRM_ERROR("failed to kmap fb updates\n");
>-			goto out;
>-		}
>-		unmap = true;
>-	}
>-
>-	for (i = y; i <= y2; i++) {
>-		/* assume equal stride for now */
>-		src_offset = dst_offset =
>-			i * afbdev->afb.base.pitches[0] + (x * bpp);
>-		memcpy_toio(dst + dst_offset, afbdev->sysram + src_offset,
>-			    (x2 - x + 1) * bpp);
>-	}
>-
>-	if (unmap)
>-		drm_gem_vram_kunmap(gbo);
>-
>-out:
>-	drm_gem_vram_unpin(gbo);
>-}
>-
>-static void ast_fillrect(struct fb_info *info,
>-			 const struct fb_fillrect *rect)
>-{
>-	struct ast_fbdev *afbdev = info->par;
>-	drm_fb_helper_sys_fillrect(info, rect);
>-	ast_dirty_update(afbdev, rect->dx, rect->dy, rect->width,
>-			 rect->height);
>-}
>-
>-static void ast_copyarea(struct fb_info *info,
>-			 const struct fb_copyarea *area)
>-{
>-	struct ast_fbdev *afbdev = info->par;
>-	drm_fb_helper_sys_copyarea(info, area);
>-	ast_dirty_update(afbdev, area->dx, area->dy, area->width,
>-			 area->height);
>-}
>-
>-static void ast_imageblit(struct fb_info *info,
>-			  const struct fb_image *image)
>-{
>-	struct ast_fbdev *afbdev = info->par;
>-	drm_fb_helper_sys_imageblit(info, image);
>-	ast_dirty_update(afbdev, image->dx, image->dy, image->width,
>-			 image->height);
>-}
>-
>-static struct fb_ops astfb_ops = {
>-	.owner = THIS_MODULE,
>-	.fb_check_var = drm_fb_helper_check_var,
>-	.fb_set_par = drm_fb_helper_set_par,
>-	.fb_fillrect = ast_fillrect,
>-	.fb_copyarea = ast_copyarea,
>-	.fb_imageblit = ast_imageblit,
>-	.fb_pan_display = drm_fb_helper_pan_display,
>-	.fb_blank = drm_fb_helper_blank,
>-	.fb_setcmap = drm_fb_helper_setcmap,
>-};
>-
>-static int astfb_create_object(struct ast_fbdev *afbdev,
>-			       const struct drm_mode_fb_cmd2 *mode_cmd,
>-			       struct drm_gem_object **gobj_p)
>-{
>-	struct drm_device *dev = afbdev->helper.dev;
>-	u32 size;
>-	struct drm_gem_object *gobj;
>-	int ret = 0;
>-
>-	size = mode_cmd->pitches[0] * mode_cmd->height;
>-	ret = ast_gem_create(dev, size, true, &gobj);
>-	if (ret)
>-		return ret;
>-
>-	*gobj_p = gobj;
>-	return ret;
>-}
>-
>-static int astfb_create(struct drm_fb_helper *helper,
>-			struct drm_fb_helper_surface_size *sizes)
>-{
>-	struct ast_fbdev *afbdev =
>-		container_of(helper, struct ast_fbdev, helper);
>-	struct drm_device *dev = afbdev->helper.dev;
>-	struct drm_mode_fb_cmd2 mode_cmd;
>-	struct drm_framebuffer *fb;
>-	struct fb_info *info;
>-	int size, ret;
>-	void *sysram;
>-	struct drm_gem_object *gobj = NULL;
>-	mode_cmd.width = sizes->surface_width;
>-	mode_cmd.height = sizes->surface_height;
>-	mode_cmd.pitches[0] = mode_cmd.width * ((sizes->surface_bpp + 7)/8);
>-
>-	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
>-							  sizes->surface_depth);
>-
>-	size = mode_cmd.pitches[0] * mode_cmd.height;
>-
>-	ret = astfb_create_object(afbdev, &mode_cmd, &gobj);
>-	if (ret) {
>-		DRM_ERROR("failed to create fbcon backing object %d\n", ret);
>-		return ret;
>-	}
>-
>-	sysram = vmalloc(size);
>-	if (!sysram)
>-		return -ENOMEM;
>-
>-	info = drm_fb_helper_alloc_fbi(helper);
>-	if (IS_ERR(info)) {
>-		ret = PTR_ERR(info);
>-		goto out;
>-	}
>-	ret = ast_framebuffer_init(dev, &afbdev->afb, &mode_cmd, gobj);
>-	if (ret)
>-		goto out;
>-
>-	afbdev->sysram = sysram;
>-	afbdev->size = size;
>-
>-	fb = &afbdev->afb.base;
>-	afbdev->helper.fb = fb;
>-
>-	info->fbops = &astfb_ops;
>-
>-	info->apertures->ranges[0].base = pci_resource_start(dev->pdev, 0);
>-	info->apertures->ranges[0].size = pci_resource_len(dev->pdev, 0);
>-
>-	drm_fb_helper_fill_info(info, &afbdev->helper, sizes);
>-
>-	info->screen_base = sysram;
>-	info->screen_size = size;
>-
>-	info->pixmap.flags = FB_PIXMAP_SYSTEM;
>-
>-	DRM_DEBUG_KMS("allocated %dx%d\n",
>-		      fb->width, fb->height);
>-
>-	return 0;
>-
>-out:
>-	vfree(sysram);
>-	return ret;
>-}
>-
>-static const struct drm_fb_helper_funcs ast_fb_helper_funcs = {
>-	.fb_probe = astfb_create,
>-};
>-
>-static void ast_fbdev_destroy(struct drm_device *dev,
>-			      struct ast_fbdev *afbdev)
>-{
>-	struct ast_framebuffer *afb = &afbdev->afb;
>-
>-	drm_helper_force_disable_all(dev);
>-	drm_fb_helper_unregister_fbi(&afbdev->helper);
>-
>-	if (afb->obj) {
>-		drm_gem_object_put_unlocked(afb->obj);
>-		afb->obj = NULL;
>-	}
>-	drm_fb_helper_fini(&afbdev->helper);
>-
>-	vfree(afbdev->sysram);
>-	drm_framebuffer_unregister_private(&afb->base);
>-	drm_framebuffer_cleanup(&afb->base);
>-}
>-
>-int ast_fbdev_init(struct drm_device *dev)
>-{
>-	struct ast_private *ast = dev->dev_private;
>-	struct ast_fbdev *afbdev;
>-	int ret;
>-
>-	afbdev = kzalloc(sizeof(struct ast_fbdev), GFP_KERNEL);
>-	if (!afbdev)
>-		return -ENOMEM;
>-
>-	ast->fbdev = afbdev;
>-	spin_lock_init(&afbdev->dirty_lock);
>-
>-	drm_fb_helper_prepare(dev, &afbdev->helper, &ast_fb_helper_funcs);
>-
>-	ret = drm_fb_helper_init(dev, &afbdev->helper, 1);
>-	if (ret)
>-		goto free;
>-
>-	ret = drm_fb_helper_single_add_all_connectors(&afbdev->helper);
>-	if (ret)
>-		goto fini;
>-
>-	/* disable all the possible outputs/crtcs before entering KMS mode */
>-	drm_helper_disable_unused_functions(dev);
>-
>-	ret = drm_fb_helper_initial_config(&afbdev->helper, 32);
>-	if (ret)
>-		goto fini;
>-
>-	return 0;
>-
>-fini:
>-	drm_fb_helper_fini(&afbdev->helper);
>-free:
>-	kfree(afbdev);
>-	return ret;
>-}
>-
>-void ast_fbdev_fini(struct drm_device *dev)
>-{
>-	struct ast_private *ast = dev->dev_private;
>-
>-	if (!ast->fbdev)
>-		return;
>-
>-	ast_fbdev_destroy(dev, ast->fbdev);
>-	kfree(ast->fbdev);
>-	ast->fbdev = NULL;
>-}
>-
>-void ast_fbdev_set_suspend(struct drm_device *dev, int state)
>-{
>-	struct ast_private *ast = dev->dev_private;
>-
>-	if (!ast->fbdev)
>-		return;
>-
>-	drm_fb_helper_set_suspend(&ast->fbdev->helper, state);
>-}
>-
>-void ast_fbdev_set_base(struct ast_private *ast, unsigned long gpu_addr)
>-{
>-	ast->fbdev->helper.fbdev->fix.smem_start =
>-		ast->fbdev->helper.fbdev->apertures->ranges[0].base + gpu_addr;
>-	ast->fbdev->helper.fbdev->fix.smem_len = ast->vram_size - gpu_addr;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ast/ast_main.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_main.c
>--- linux-5.3-rc6/drivers/gpu/drm/ast/ast_main.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_main.c	2019-08-31 15:01:12.250736203 -0500
>@@ -25,12 +25,17 @@
> /*
>  * Authors: Dave Airlie <airlied@redhat.com>
>  */
>-#include <drm/drmP.h>
>-#include "ast_drv.h"
> 
>+#include <linux/pci.h>
> 
>-#include <drm/drm_fb_helper.h>
> #include <drm/drm_crtc_helper.h>
>+#include <drm/drm_fb_helper.h>
>+#include <drm/drm_gem.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_gem_vram_helper.h>
>+#include <drm/drm_vram_mm_helper.h>
>+
>+#include "ast_drv.h"
> 
> void ast_set_index_reg_mask(struct ast_private *ast,
> 			    uint32_t base, uint8_t index,
>@@ -383,67 +388,8 @@
> 	return 0;
> }
> 
>-static void ast_user_framebuffer_destroy(struct drm_framebuffer *fb)
>-{
>-	struct ast_framebuffer *ast_fb = to_ast_framebuffer(fb);
>-
>-	drm_gem_object_put_unlocked(ast_fb->obj);
>-	drm_framebuffer_cleanup(fb);
>-	kfree(ast_fb);
>-}
>-
>-static const struct drm_framebuffer_funcs ast_fb_funcs = {
>-	.destroy = ast_user_framebuffer_destroy,
>-};
>-
>-
>-int ast_framebuffer_init(struct drm_device *dev,
>-			 struct ast_framebuffer *ast_fb,
>-			 const struct drm_mode_fb_cmd2 *mode_cmd,
>-			 struct drm_gem_object *obj)
>-{
>-	int ret;
>-
>-	drm_helper_mode_fill_fb_struct(dev, &ast_fb->base, mode_cmd);
>-	ast_fb->obj = obj;
>-	ret = drm_framebuffer_init(dev, &ast_fb->base, &ast_fb_funcs);
>-	if (ret) {
>-		DRM_ERROR("framebuffer init failed %d\n", ret);
>-		return ret;
>-	}
>-	return 0;
>-}
>-
>-static struct drm_framebuffer *
>-ast_user_framebuffer_create(struct drm_device *dev,
>-	       struct drm_file *filp,
>-	       const struct drm_mode_fb_cmd2 *mode_cmd)
>-{
>-	struct drm_gem_object *obj;
>-	struct ast_framebuffer *ast_fb;
>-	int ret;
>-
>-	obj = drm_gem_object_lookup(filp, mode_cmd->handles[0]);
>-	if (obj == NULL)
>-		return ERR_PTR(-ENOENT);
>-
>-	ast_fb = kzalloc(sizeof(*ast_fb), GFP_KERNEL);
>-	if (!ast_fb) {
>-		drm_gem_object_put_unlocked(obj);
>-		return ERR_PTR(-ENOMEM);
>-	}
>-
>-	ret = ast_framebuffer_init(dev, ast_fb, mode_cmd, obj);
>-	if (ret) {
>-		drm_gem_object_put_unlocked(obj);
>-		kfree(ast_fb);
>-		return ERR_PTR(ret);
>-	}
>-	return &ast_fb->base;
>-}
>-
> static const struct drm_mode_config_funcs ast_mode_funcs = {
>-	.fb_create = ast_user_framebuffer_create,
>+	.fb_create = drm_gem_fb_create
> };
> 
> static u32 ast_get_vram_info(struct drm_device *dev)
>@@ -561,7 +507,7 @@
> 	if (ret)
> 		goto out_free;
> 
>-	ret = ast_fbdev_init(dev);
>+	ret = drm_fbdev_generic_setup(dev, 32);
> 	if (ret)
> 		goto out_free;
> 
>@@ -582,7 +528,6 @@
> 	ast_release_firmware(dev);
> 	kfree(ast->dp501_fw_addr);
> 	ast_mode_fini(dev);
>-	ast_fbdev_fini(dev);
> 	drm_mode_config_cleanup(dev);
> 
> 	ast_mm_fini(ast);
>@@ -612,6 +557,6 @@
> 			DRM_ERROR("failed to allocate GEM object\n");
> 		return ret;
> 	}
>-	*obj = &gbo->gem;
>+	*obj = &gbo->bo.base;
> 	return 0;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ast/ast_mode.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_mode.c
>--- linux-5.3-rc6/drivers/gpu/drm/ast/ast_mode.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_mode.c	2019-08-31 15:01:12.250736203 -0500
>@@ -27,14 +27,18 @@
> /*
>  * Authors: Dave Airlie <airlied@redhat.com>
>  */
>+
> #include <linux/export.h>
>-#include <drm/drmP.h>
>+#include <linux/pci.h>
>+
> #include <drm/drm_crtc.h>
> #include <drm/drm_crtc_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_gem_vram_helper.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>-#include "ast_drv.h"
> 
>+#include "ast_drv.h"
> #include "ast_tables.h"
> 
> static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
>@@ -525,28 +529,16 @@
> 				struct drm_framebuffer *fb,
> 				int x, int y, int atomic)
> {
>-	struct ast_private *ast = crtc->dev->dev_private;
>-	struct drm_gem_object *obj;
>-	struct ast_framebuffer *ast_fb;
> 	struct drm_gem_vram_object *gbo;
> 	int ret;
> 	s64 gpu_addr;
>-	void *base;
> 
> 	if (!atomic && fb) {
>-		ast_fb = to_ast_framebuffer(fb);
>-		obj = ast_fb->obj;
>-		gbo = drm_gem_vram_of_gem(obj);
>-
>-		/* unmap if console */
>-		if (&ast->fbdev->afb == ast_fb)
>-			drm_gem_vram_kunmap(gbo);
>+		gbo = drm_gem_vram_of_gem(fb->obj[0]);
> 		drm_gem_vram_unpin(gbo);
> 	}
> 
>-	ast_fb = to_ast_framebuffer(crtc->primary->fb);
>-	obj = ast_fb->obj;
>-	gbo = drm_gem_vram_of_gem(obj);
>+	gbo = drm_gem_vram_of_gem(crtc->primary->fb->obj[0]);
> 
> 	ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM);
> 	if (ret)
>@@ -557,17 +549,6 @@
> 		goto err_drm_gem_vram_unpin;
> 	}
> 
>-	if (&ast->fbdev->afb == ast_fb) {
>-		/* if pushing console in kmap it */
>-		base = drm_gem_vram_kmap(gbo, true, NULL);
>-		if (IS_ERR(base)) {
>-			ret = PTR_ERR(base);
>-			DRM_ERROR("failed to kmap fbcon\n");
>-		} else {
>-			ast_fbdev_set_base(ast, gpu_addr);
>-		}
>-	}
>-
> 	ast_set_offset_reg(crtc);
> 	ast_set_start_address_crt1(crtc, (u32)gpu_addr);
> 
>@@ -624,14 +605,10 @@
> 	DRM_DEBUG_KMS("\n");
> 	ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
> 	if (crtc->primary->fb) {
>-		struct ast_private *ast = crtc->dev->dev_private;
>-		struct ast_framebuffer *ast_fb = to_ast_framebuffer(crtc->primary->fb);
>-		struct drm_gem_object *obj = ast_fb->obj;
>-		struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(obj);
>-
>-		/* unmap if console */
>-		if (&ast->fbdev->afb == ast_fb)
>-			drm_gem_vram_kunmap(gbo);
>+		struct drm_framebuffer *fb = crtc->primary->fb;
>+		struct drm_gem_vram_object *gbo =
>+			drm_gem_vram_of_gem(fb->obj[0]);
>+
> 		drm_gem_vram_unpin(gbo);
> 	}
> 	crtc->primary->fb = NULL;
>@@ -890,7 +867,14 @@
> 		return -ENOMEM;
> 
> 	connector = &ast_connector->base;
>-	drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA);
>+	ast_connector->i2c = ast_i2c_create(dev);
>+	if (!ast_connector->i2c)
>+		DRM_ERROR("failed to add ddc bus for connector\n");
>+
>+	drm_connector_init_with_ddc(dev, connector,
>+				    &ast_connector_funcs,
>+				    DRM_MODE_CONNECTOR_VGA,
>+				    &ast_connector->i2c->adapter);
> 
> 	drm_connector_helper_add(connector, &ast_connector_helper_funcs);
> 
>@@ -904,10 +888,6 @@
> 	encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head);
> 	drm_connector_attach_encoder(connector, encoder);
> 
>-	ast_connector->i2c = ast_i2c_create(dev);
>-	if (!ast_connector->i2c)
>-		DRM_ERROR("failed to add ddc bus for connector\n");
>-
> 	return 0;
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ast/ast_post.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_post.c
>--- linux-5.3-rc6/drivers/gpu/drm/ast/ast_post.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_post.c	2019-08-31 15:01:12.249736203 -0500
>@@ -26,10 +26,13 @@
>  * Authors: Dave Airlie <airlied@redhat.com>
>  */
> 
>-#include <drm/drmP.h>
>-#include "ast_drv.h"
>+#include <linux/delay.h>
>+#include <linux/pci.h>
>+
>+#include <drm/drm_print.h>
> 
> #include "ast_dram_tables.h"
>+#include "ast_drv.h"
> 
> static void ast_post_chip_2300(struct drm_device *dev);
> static void ast_post_chip_2500(struct drm_device *dev);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ast/ast_ttm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_ttm.c
>--- linux-5.3-rc6/drivers/gpu/drm/ast/ast_ttm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/ast_ttm.c	2019-08-31 15:01:11.941736176 -0500
>@@ -25,7 +25,12 @@
> /*
>  * Authors: Dave Airlie <airlied@redhat.com>
>  */
>-#include <drm/drmP.h>
>+
>+#include <linux/pci.h>
>+
>+#include <drm/drm_print.h>
>+#include <drm/drm_gem_vram_helper.h>
>+#include <drm/drm_vram_mm_helper.h>
> 
> #include "ast_drv.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ast/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/ast/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ast/Makefile	2019-08-31 15:01:11.940736175 -0500
>@@ -3,6 +3,6 @@
> # Makefile for the drm device driver.  This driver provides support for the
> # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
> 
>-ast-y := ast_drv.o ast_main.o ast_mode.o ast_fb.o ast_ttm.o ast_post.o ast_dp501.o
>+ast-y := ast_drv.o ast_main.o ast_mode.o ast_ttm.o ast_post.o ast_dp501.o
> 
> obj-$(CONFIG_DRM_AST) := ast.o
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ati_pcigart.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ati_pcigart.c
>--- linux-5.3-rc6/drivers/gpu/drm/ati_pcigart.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ati_pcigart.c	2019-08-31 15:01:11.941736176 -0500
>@@ -35,7 +35,6 @@
> 
> #include <drm/ati_pcigart.h>
> #include <drm/drm_device.h>
>-#include <drm/drm_os_linux.h>
> #include <drm/drm_pci.h>
> #include <drm/drm_print.h>
> 
>@@ -169,6 +168,7 @@
> 		page_base = (u32) entry->busaddr[i];
> 
> 		for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
>+			u32 offset;
> 			u32 val;
> 
> 			switch(gart_info->gart_reg_if) {
>@@ -184,10 +184,12 @@
> 				break;
> 			}
> 			if (gart_info->gart_table_location ==
>-			    DRM_ATI_GART_MAIN)
>+			    DRM_ATI_GART_MAIN) {
> 				pci_gart[gart_idx] = cpu_to_le32(val);
>-			else
>-				DRM_WRITE32(map, gart_idx * sizeof(u32), val);
>+			} else {
>+				offset = gart_idx * sizeof(u32);
>+				writel(val, (void __iomem *)map->handle + offset);
>+			}
> 			gart_idx++;
> 			page_base += ATI_PCIGART_PAGE_SIZE;
> 		}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c	2019-08-31 15:01:11.941736176 -0500
>@@ -8,15 +8,19 @@
>  */
> 
> #include <linux/clk.h>
>+#include <linux/mfd/atmel-hlcdc.h>
>+#include <linux/pinctrl/consumer.h>
> #include <linux/pm.h>
> #include <linux/pm_runtime.h>
>-#include <linux/pinctrl/consumer.h>
> 
>+#include <video/videomode.h>
>+
>+#include <drm/drm_atomic.h>
>+#include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
>+#include <drm/drm_modeset_helper_vtables.h>
> #include <drm/drm_probe_helper.h>
>-#include <drm/drmP.h>
>-
>-#include <video/videomode.h>
>+#include <drm/drm_vblank.h>
> 
> #include "atmel_hlcdc_dc.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
>--- linux-5.3-rc6/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c	2019-08-31 15:01:11.941736176 -0500
>@@ -11,8 +11,20 @@
> #include <linux/clk.h>
> #include <linux/irq.h>
> #include <linux/irqchip.h>
>+#include <linux/mfd/atmel-hlcdc.h>
> #include <linux/module.h>
> #include <linux/pm_runtime.h>
>+#include <linux/platform_device.h>
>+
>+#include <drm/drm_atomic.h>
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_fb_helper.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_irq.h>
>+#include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "atmel_hlcdc_dc.h"
> 
>@@ -823,9 +835,7 @@
> DEFINE_DRM_GEM_CMA_FOPS(fops);
> 
> static struct drm_driver atmel_hlcdc_dc_driver = {
>-	.driver_features = DRIVER_GEM |
>-			   DRIVER_MODESET | DRIVER_PRIME |
>-			   DRIVER_ATOMIC,
>+	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.irq_handler = atmel_hlcdc_dc_irq_handler,
> 	.irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
> 	.irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
>@@ -834,8 +844,6 @@
> 	.gem_vm_ops = &drm_gem_cma_vm_ops,
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_import = drm_gem_prime_import,
>-	.gem_prime_export = drm_gem_prime_export,
> 	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap = drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
>--- linux-5.3-rc6/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h	2019-08-31 15:01:11.941736176 -0500
>@@ -11,23 +11,9 @@
> #ifndef DRM_ATMEL_HLCDC_H
> #define DRM_ATMEL_HLCDC_H
> 
>-#include <linux/clk.h>
>-#include <linux/dmapool.h>
>-#include <linux/irqdomain.h>
>-#include <linux/mfd/atmel-hlcdc.h>
>-#include <linux/pwm.h>
>+#include <linux/regmap.h>
> 
>-#include <drm/drm_atomic.h>
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_crtc.h>
>-#include <drm/drm_probe_helper.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_fb_cma_helper.h>
>-#include <drm/drm_gem_cma_helper.h>
>-#include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_panel.h>
>-#include <drm/drm_plane_helper.h>
>-#include <drm/drmP.h>
>+#include <drm/drm_plane.h>
> 
> #define ATMEL_HLCDC_LAYER_CHER			0x0
> #define ATMEL_HLCDC_LAYER_CHDR			0x4
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c
>--- linux-5.3-rc6/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c	2019-08-31 15:01:11.941736176 -0500
>@@ -8,9 +8,10 @@
>  * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
>  */
> 
>+#include <linux/media-bus-format.h>
> #include <linux/of_graph.h>
> 
>-#include <drm/drmP.h>
>+#include <drm/drm_encoder.h>
> #include <drm/drm_of.h>
> #include <drm/drm_bridge.h>
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c	2019-08-31 15:01:11.941736176 -0500
>@@ -6,6 +6,16 @@
>  * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
>  */
> 
>+#include <linux/dmapool.h>
>+#include <linux/mfd/atmel-hlcdc.h>
>+
>+#include <drm/drm_atomic.h>
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_plane_helper.h>
>+
> #include "atmel_hlcdc_dc.h"
> 
> /**
>@@ -361,7 +371,7 @@
> 	atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG,
> 				    cfg);
> 
>-	cfg = ATMEL_HLCDC_LAYER_DMA;
>+	cfg = ATMEL_HLCDC_LAYER_DMA | ATMEL_HLCDC_LAYER_REP;
> 
> 	if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) {
> 		cfg |= ATMEL_HLCDC_LAYER_OVR | ATMEL_HLCDC_LAYER_ITER2BL |
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bochs/bochs_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bochs/bochs_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/bochs/bochs_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bochs/bochs_drv.c	2019-08-31 15:01:11.941736176 -0500
>@@ -2,11 +2,10 @@
> /*
>  */
> 
>-#include <linux/mm.h>
> #include <linux/module.h>
>-#include <linux/slab.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_probe_helper.h>
>+#include <linux/pci.h>
>+
>+#include <drm/drm_drv.h>
> #include <drm/drm_atomic_helper.h>
> 
> #include "bochs.h"
>@@ -65,8 +64,7 @@
> };
> 
> static struct drm_driver bochs_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC |
>-				  DRIVER_PRIME,
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.fops			= &bochs_fops,
> 	.name			= "bochs-drm",
> 	.desc			= "bochs dispi vga interface (qemu stdvga)",
>@@ -74,7 +72,6 @@
> 	.major			= 1,
> 	.minor			= 0,
> 	DRM_GEM_VRAM_DRIVER,
>-	DRM_GEM_VRAM_DRIVER_PRIME,
> };
> 
> /* ---------------------------------------------------------------------- */
>@@ -83,16 +80,14 @@
> #ifdef CONFIG_PM_SLEEP
> static int bochs_pm_suspend(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 
> 	return drm_mode_config_helper_suspend(drm_dev);
> }
> 
> static int bochs_pm_resume(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 
> 	return drm_mode_config_helper_resume(drm_dev);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bochs/bochs.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/bochs/bochs.h
>--- linux-5.3-rc6/drivers/gpu/drm/bochs/bochs.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bochs/bochs.h	2019-08-31 15:01:11.941736176 -0500
>@@ -1,17 +1,15 @@
> /* SPDX-License-Identifier: GPL-2.0 */
>+
> #include <linux/io.h>
> #include <linux/console.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_crtc_helper.h>
> #include <drm/drm_encoder.h>
> #include <drm/drm_fb_helper.h>
>-#include <drm/drm_simple_kms_helper.h>
>-
> #include <drm/drm_gem.h>
> #include <drm/drm_gem_vram_helper.h>
>-
>+#include <drm/drm_simple_kms_helper.h>
> #include <drm/drm_vram_mm_helper.h>
> 
> /* ---------------------------------------------------------------------- */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bochs/bochs_hw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bochs/bochs_hw.c
>--- linux-5.3-rc6/drivers/gpu/drm/bochs/bochs_hw.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bochs/bochs_hw.c	2019-08-31 15:01:11.941736176 -0500
>@@ -2,6 +2,10 @@
> /*
>  */
> 
>+#include <linux/pci.h>
>+
>+#include <drm/drm_fourcc.h>
>+
> #include "bochs.h"
> 
> /* ---------------------------------------------------------------------- */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bochs/bochs_kms.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bochs/bochs_kms.c
>--- linux-5.3-rc6/drivers/gpu/drm/bochs/bochs_kms.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bochs/bochs_kms.c	2019-08-31 15:01:11.941736176 -0500
>@@ -2,12 +2,14 @@
> /*
>  */
> 
>-#include "bochs.h"
>+#include <linux/moduleparam.h>
>+
> #include <drm/drm_atomic_helper.h>
>-#include <drm/drm_plane_helper.h>
>-#include <drm/drm_atomic_uapi.h>
> #include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
>+
>+#include "bochs.h"
> 
> static int defx = 1024;
> static int defy = 768;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c	2019-08-31 15:01:11.942736176 -0500
>@@ -874,9 +874,6 @@
> 				 &adv7511_connector_helper_funcs);
> 	drm_connector_attach_encoder(&adv->connector, bridge->encoder);
> 
>-	if (adv->type == ADV7533)
>-		ret = adv7533_attach_dsi(adv);
>-
> 	if (adv->i2c_main->irq)
> 		regmap_write(adv->regmap, ADV7511_REG_INT_ENABLE(0),
> 			     ADV7511_INT0_HPD);
>@@ -1222,8 +1219,17 @@
> 	drm_bridge_add(&adv7511->bridge);
> 
> 	adv7511_audio_init(dev, adv7511);
>+
>+	if (adv7511->type == ADV7533) {
>+		ret = adv7533_attach_dsi(adv7511);
>+		if (ret)
>+			goto err_remove_bridge;
>+	}
>+
> 	return 0;
> 
>+err_remove_bridge:
>+	drm_bridge_remove(&adv7511->bridge);
> err_unregister_cec:
> 	i2c_unregister_device(adv7511->i2c_cec);
> 	if (adv7511->cec_clk)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c	2019-08-31 15:01:11.942736176 -0500
>@@ -19,6 +19,7 @@
> #include <linux/platform_device.h>
> 
> #include <drm/bridge/analogix_dp.h>
>+#include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_device.h>
>@@ -101,63 +102,7 @@
> 	return 0;
> }
> 
>-int analogix_dp_psr_enabled(struct analogix_dp_device *dp)
>-{
>-
>-	return dp->psr_enable;
>-}
>-EXPORT_SYMBOL_GPL(analogix_dp_psr_enabled);
>-
>-int analogix_dp_enable_psr(struct analogix_dp_device *dp)
>-{
>-	struct dp_sdp psr_vsc;
>-
>-	if (!dp->psr_enable)
>-		return 0;
>-
>-	/* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
>-	memset(&psr_vsc, 0, sizeof(psr_vsc));
>-	psr_vsc.sdp_header.HB0 = 0;
>-	psr_vsc.sdp_header.HB1 = 0x7;
>-	psr_vsc.sdp_header.HB2 = 0x2;
>-	psr_vsc.sdp_header.HB3 = 0x8;
>-
>-	psr_vsc.db[0] = 0;
>-	psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
>-
>-	return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
>-}
>-EXPORT_SYMBOL_GPL(analogix_dp_enable_psr);
>-
>-int analogix_dp_disable_psr(struct analogix_dp_device *dp)
>-{
>-	struct dp_sdp psr_vsc;
>-	int ret;
>-
>-	if (!dp->psr_enable)
>-		return 0;
>-
>-	/* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
>-	memset(&psr_vsc, 0, sizeof(psr_vsc));
>-	psr_vsc.sdp_header.HB0 = 0;
>-	psr_vsc.sdp_header.HB1 = 0x7;
>-	psr_vsc.sdp_header.HB2 = 0x2;
>-	psr_vsc.sdp_header.HB3 = 0x8;
>-
>-	psr_vsc.db[0] = 0;
>-	psr_vsc.db[1] = 0;
>-
>-	ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
>-	if (ret != 1) {
>-		dev_err(dp->dev, "Failed to set DP Power0 %d\n", ret);
>-		return ret;
>-	}
>-
>-	return analogix_dp_send_psr_spd(dp, &psr_vsc, false);
>-}
>-EXPORT_SYMBOL_GPL(analogix_dp_disable_psr);
>-
>-static int analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
>+static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
> {
> 	unsigned char psr_version;
> 	int ret;
>@@ -165,14 +110,11 @@
> 	ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
> 	if (ret != 1) {
> 		dev_err(dp->dev, "failed to get PSR version, disable it\n");
>-		return ret;
>+		return false;
> 	}
> 
> 	dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
>-
>-	dp->psr_enable = (psr_version & DP_PSR_IS_SUPPORTED) ? true : false;
>-
>-	return 0;
>+	return psr_version & DP_PSR_IS_SUPPORTED;
> }
> 
> static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
>@@ -195,7 +137,7 @@
> 	}
> 
> 	/* Main-Link transmitter remains active during PSR active states */
>-	psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION;
>+	psr_en = DP_PSR_CRC_VERIFICATION;
> 	ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
> 	if (ret != 1) {
> 		dev_err(dp->dev, "failed to set panel psr\n");
>@@ -203,8 +145,7 @@
> 	}
> 
> 	/* Enable psr function */
>-	psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE |
>-		 DP_PSR_CRC_VERIFICATION;
>+	psr_en = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
> 	ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
> 	if (ret != 1) {
> 		dev_err(dp->dev, "failed to set panel psr\n");
>@@ -213,10 +154,11 @@
> 
> 	analogix_dp_enable_psr_crc(dp);
> 
>+	dp->psr_supported = true;
>+
> 	return 0;
> end:
> 	dev_err(dp->dev, "enable psr fail, force to disable psr\n");
>-	dp->psr_enable = false;
> 
> 	return ret;
> }
>@@ -1031,24 +973,90 @@
> 		}
> 	}
> 
>-	ret = analogix_dp_detect_sink_psr(dp);
>+	/* Check whether panel supports fast training */
>+	ret = analogix_dp_fast_link_train_detection(dp);
> 	if (ret)
> 		return ret;
> 
>-	if (dp->psr_enable) {
>+	if (analogix_dp_detect_sink_psr(dp)) {
> 		ret = analogix_dp_enable_sink_psr(dp);
> 		if (ret)
> 			return ret;
> 	}
> 
>-	/* Check whether panel supports fast training */
>-	ret =  analogix_dp_fast_link_train_detection(dp);
>-	if (ret)
>-		dp->psr_enable = false;
>+	return ret;
>+}
>+
>+static int analogix_dp_enable_psr(struct analogix_dp_device *dp)
>+{
>+	struct dp_sdp psr_vsc;
>+	int ret;
>+	u8 sink;
>+
>+	ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
>+	if (ret != 1)
>+		DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
>+	else if (sink == DP_PSR_SINK_ACTIVE_RFB)
>+		return 0;
>+
>+	/* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
>+	memset(&psr_vsc, 0, sizeof(psr_vsc));
>+	psr_vsc.sdp_header.HB0 = 0;
>+	psr_vsc.sdp_header.HB1 = 0x7;
>+	psr_vsc.sdp_header.HB2 = 0x2;
>+	psr_vsc.sdp_header.HB3 = 0x8;
>+	psr_vsc.db[0] = 0;
>+	psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
>+
>+	ret = analogix_dp_send_psr_spd(dp, &psr_vsc, true);
>+	if (!ret)
>+		analogix_dp_set_analog_power_down(dp, POWER_ALL, true);
> 
> 	return ret;
> }
> 
>+static int analogix_dp_disable_psr(struct analogix_dp_device *dp)
>+{
>+	struct dp_sdp psr_vsc;
>+	int ret;
>+	u8 sink;
>+
>+	analogix_dp_set_analog_power_down(dp, POWER_ALL, false);
>+
>+	ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
>+	if (ret != 1) {
>+		DRM_DEV_ERROR(dp->dev, "Failed to set DP Power0 %d\n", ret);
>+		return ret;
>+	}
>+
>+	ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
>+	if (ret != 1) {
>+		DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
>+		return ret;
>+	} else if (sink == DP_PSR_SINK_INACTIVE) {
>+		DRM_DEV_ERROR(dp->dev, "sink inactive, skip disable psr");
>+		return 0;
>+	}
>+
>+	ret = analogix_dp_train_link(dp);
>+	if (ret) {
>+		DRM_DEV_ERROR(dp->dev, "Failed to train the link %d\n", ret);
>+		return ret;
>+	}
>+
>+	/* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
>+	memset(&psr_vsc, 0, sizeof(psr_vsc));
>+	psr_vsc.sdp_header.HB0 = 0;
>+	psr_vsc.sdp_header.HB1 = 0x7;
>+	psr_vsc.sdp_header.HB2 = 0x2;
>+	psr_vsc.sdp_header.HB3 = 0x8;
>+
>+	psr_vsc.db[0] = 0;
>+	psr_vsc.db[1] = 0;
>+
>+	return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
>+}
>+
> /*
>  * This function is a bit of a catch-all for panel preparation, hopefully
>  * simplifying the logic of functions that need to prepare/unprepare the panel
>@@ -1139,9 +1147,37 @@
> 	return dp->encoder;
> }
> 
>+
>+static int analogix_dp_atomic_check(struct drm_connector *connector,
>+				    struct drm_atomic_state *state)
>+{
>+	struct analogix_dp_device *dp = to_dp(connector);
>+	struct drm_connector_state *conn_state;
>+	struct drm_crtc_state *crtc_state;
>+
>+	conn_state = drm_atomic_get_new_connector_state(state, connector);
>+	if (WARN_ON(!conn_state))
>+		return -ENODEV;
>+
>+	conn_state->self_refresh_aware = true;
>+
>+	if (!conn_state->crtc)
>+		return 0;
>+
>+	crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
>+	if (!crtc_state)
>+		return 0;
>+
>+	if (crtc_state->self_refresh_active && !dp->psr_supported)
>+		return -EINVAL;
>+
>+	return 0;
>+}
>+
> static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
> 	.get_modes = analogix_dp_get_modes,
> 	.best_encoder = analogix_dp_best_encoder,
>+	.atomic_check = analogix_dp_atomic_check,
> };
> 
> static enum drm_connector_status
>@@ -1233,11 +1269,42 @@
> 	return 0;
> }
> 
>-static void analogix_dp_bridge_pre_enable(struct drm_bridge *bridge)
>+static
>+struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp,
>+					  struct drm_atomic_state *state)
>+{
>+	struct drm_encoder *encoder = dp->encoder;
>+	struct drm_connector *connector;
>+	struct drm_connector_state *conn_state;
>+
>+	connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
>+	if (!connector)
>+		return NULL;
>+
>+	conn_state = drm_atomic_get_new_connector_state(state, connector);
>+	if (!conn_state)
>+		return NULL;
>+
>+	return conn_state->crtc;
>+}
>+
>+static void analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,
>+						 struct drm_atomic_state *state)
> {
> 	struct analogix_dp_device *dp = bridge->driver_private;
>+	struct drm_crtc *crtc;
>+	struct drm_crtc_state *old_crtc_state;
> 	int ret;
> 
>+	crtc = analogix_dp_get_new_crtc(dp, state);
>+	if (!crtc)
>+		return;
>+
>+	old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
>+	/* Don't touch the panel if we're coming back from PSR */
>+	if (old_crtc_state && old_crtc_state->self_refresh_active)
>+		return;
>+
> 	ret = analogix_dp_prepare_panel(dp, true, true);
> 	if (ret)
> 		DRM_ERROR("failed to setup the panel ret = %d\n", ret);
>@@ -1298,10 +1365,27 @@
> 	return ret;
> }
> 
>-static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
>+static void analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge,
>+					     struct drm_atomic_state *state)
> {
> 	struct analogix_dp_device *dp = bridge->driver_private;
>+	struct drm_crtc *crtc;
>+	struct drm_crtc_state *old_crtc_state;
> 	int timeout_loop = 0;
>+	int ret;
>+
>+	crtc = analogix_dp_get_new_crtc(dp, state);
>+	if (!crtc)
>+		return;
>+
>+	old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
>+	/* Not a full enable, just disable PSR and continue */
>+	if (old_crtc_state && old_crtc_state->self_refresh_active) {
>+		ret = analogix_dp_disable_psr(dp);
>+		if (ret)
>+			DRM_ERROR("Failed to disable psr %d\n", ret);
>+		return;
>+	}
> 
> 	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
> 		return;
>@@ -1350,11 +1434,56 @@
> 	if (ret)
> 		DRM_ERROR("failed to setup the panel ret = %d\n", ret);
> 
>-	dp->psr_enable = false;
> 	dp->fast_train_enable = false;
>+	dp->psr_supported = false;
> 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
> }
> 
>+static void analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge,
>+					      struct drm_atomic_state *state)
>+{
>+	struct analogix_dp_device *dp = bridge->driver_private;
>+	struct drm_crtc *crtc;
>+	struct drm_crtc_state *new_crtc_state = NULL;
>+
>+	crtc = analogix_dp_get_new_crtc(dp, state);
>+	if (!crtc)
>+		goto out;
>+
>+	new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
>+	if (!new_crtc_state)
>+		goto out;
>+
>+	/* Don't do a full disable on PSR transitions */
>+	if (new_crtc_state->self_refresh_active)
>+		return;
>+
>+out:
>+	analogix_dp_bridge_disable(bridge);
>+}
>+
>+static
>+void analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge,
>+					    struct drm_atomic_state *state)
>+{
>+	struct analogix_dp_device *dp = bridge->driver_private;
>+	struct drm_crtc *crtc;
>+	struct drm_crtc_state *new_crtc_state;
>+	int ret;
>+
>+	crtc = analogix_dp_get_new_crtc(dp, state);
>+	if (!crtc)
>+		return;
>+
>+	new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
>+	if (!new_crtc_state || !new_crtc_state->self_refresh_active)
>+		return;
>+
>+	ret = analogix_dp_enable_psr(dp);
>+	if (ret)
>+		DRM_ERROR("Failed to enable psr (%d)\n", ret);
>+}
>+
> static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
> 				const struct drm_display_mode *orig_mode,
> 				const struct drm_display_mode *mode)
>@@ -1432,16 +1561,11 @@
> 		video->interlaced = true;
> }
> 
>-static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
>-{
>-	/* do nothing */
>-}
>-
> static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
>-	.pre_enable = analogix_dp_bridge_pre_enable,
>-	.enable = analogix_dp_bridge_enable,
>-	.disable = analogix_dp_bridge_disable,
>-	.post_disable = analogix_dp_bridge_nop,
>+	.atomic_pre_enable = analogix_dp_bridge_atomic_pre_enable,
>+	.atomic_enable = analogix_dp_bridge_atomic_enable,
>+	.atomic_disable = analogix_dp_bridge_atomic_disable,
>+	.atomic_post_disable = analogix_dp_bridge_atomic_post_disable,
> 	.mode_set = analogix_dp_bridge_mode_set,
> 	.attach = analogix_dp_bridge_attach,
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h	2019-08-31 15:01:11.942736176 -0500
>@@ -171,8 +171,8 @@
> 	int			dpms_mode;
> 	struct gpio_desc	*hpd_gpiod;
> 	bool                    force_hpd;
>-	bool			psr_enable;
> 	bool			fast_train_enable;
>+	bool			psr_supported;
> 
> 	struct mutex		panel_lock;
> 	bool			panel_is_modeset;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/dumb-vga-dac.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/dumb-vga-dac.c
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/dumb-vga-dac.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/dumb-vga-dac.c	2019-08-31 15:01:11.942736176 -0500
>@@ -111,8 +111,10 @@
> 
> 	drm_connector_helper_add(&vga->connector,
> 				 &dumb_vga_con_helper_funcs);
>-	ret = drm_connector_init(bridge->dev, &vga->connector,
>-				 &dumb_vga_con_funcs, DRM_MODE_CONNECTOR_VGA);
>+	ret = drm_connector_init_with_ddc(bridge->dev, &vga->connector,
>+					  &dumb_vga_con_funcs,
>+					  DRM_MODE_CONNECTOR_VGA,
>+					  vga->ddc);
> 	if (ret) {
> 		DRM_ERROR("Failed to initialize connector\n");
> 		return ret;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/Kconfig linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/Kconfig
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/Kconfig	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/Kconfig	2019-08-31 15:01:11.941736176 -0500
>@@ -21,7 +21,7 @@
> 	select DRM_KMS_HELPER
> 	select REGMAP_I2C
> 	---help---
>-	  ANX78XX is an ultra-low Full-HD SlimPort transmitter
>+	  ANX78XX is an ultra-low power Full-HD SlimPort transmitter
> 	  designed for portable devices. The ANX78XX transforms
> 	  the HDMI output of an application processor to MyDP
> 	  or DisplayPort.
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c	2019-08-31 15:01:11.942736176 -0500
>@@ -19,7 +19,6 @@
>  *   Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
>  */
> 
>-#include <linux/gpio.h>
> #include <linux/i2c.h>
> #include <linux/module.h>
> #include <linux/of.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/nxp-ptn3460.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/nxp-ptn3460.c
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/nxp-ptn3460.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/nxp-ptn3460.c	2019-08-31 15:01:11.942736176 -0500
>@@ -6,13 +6,10 @@
>  */
> 
> #include <linux/delay.h>
>-#include <linux/gpio.h>
> #include <linux/gpio/consumer.h>
> #include <linux/i2c.h>
> #include <linux/module.h>
> #include <linux/of.h>
>-#include <linux/of_gpio.h>
>-
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_edid.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/parade-ps8622.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/parade-ps8622.c
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/parade-ps8622.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/parade-ps8622.c	2019-08-31 15:01:11.942736176 -0500
>@@ -8,7 +8,6 @@
> #include <linux/backlight.h>
> #include <linux/delay.h>
> #include <linux/err.h>
>-#include <linux/gpio.h>
> #include <linux/gpio/consumer.h>
> #include <linux/i2c.h>
> #include <linux/module.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/sii902x.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/sii902x.c
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/sii902x.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/sii902x.c	2019-08-31 15:01:11.942736176 -0500
>@@ -158,6 +158,8 @@
> 
> #define SII902X_I2C_BUS_ACQUISITION_TIMEOUT_MS	500
> 
>+#define SII902X_AUDIO_PORT_INDEX		3
>+
> struct sii902x {
> 	struct i2c_client *i2c;
> 	struct regmap *regmap;
>@@ -568,13 +570,14 @@
> 		return ret;
> 	}
> 
>-	mclk_rate = clk_get_rate(sii902x->audio.mclk);
>-
>-	ret = sii902x_select_mclk_div(&i2s_config_reg, params->sample_rate,
>-				      mclk_rate);
>-	if (mclk_rate != ret * params->sample_rate)
>-		dev_dbg(dev, "Inaccurate reference clock (%ld/%d != %u)\n",
>-			mclk_rate, ret, params->sample_rate);
>+	if (sii902x->audio.mclk) {
>+		mclk_rate = clk_get_rate(sii902x->audio.mclk);
>+		ret = sii902x_select_mclk_div(&i2s_config_reg,
>+					      params->sample_rate, mclk_rate);
>+		if (mclk_rate != ret * params->sample_rate)
>+			dev_dbg(dev, "Inaccurate reference clock (%ld/%d != %u)\n",
>+				mclk_rate, ret, params->sample_rate);
>+	}
> 
> 	mutex_lock(&sii902x->mutex);
> 
>@@ -662,7 +665,8 @@
> 	clk_disable_unprepare(sii902x->audio.mclk);
> }
> 
>-int sii902x_audio_digital_mute(struct device *dev, void *data, bool enable)
>+static int sii902x_audio_digital_mute(struct device *dev,
>+				      void *data, bool enable)
> {
> 	struct sii902x *sii902x = dev_get_drvdata(dev);
> 
>@@ -690,11 +694,32 @@
> 	return 0;
> }
> 
>+static int sii902x_audio_get_dai_id(struct snd_soc_component *component,
>+				    struct device_node *endpoint)
>+{
>+	struct of_endpoint of_ep;
>+	int ret;
>+
>+	ret = of_graph_parse_endpoint(endpoint, &of_ep);
>+	if (ret < 0)
>+		return ret;
>+
>+	/*
>+	 * HDMI sound should be located at reg = <3>
>+	 * Return expected DAI index 0.
>+	 */
>+	if (of_ep.port == SII902X_AUDIO_PORT_INDEX)
>+		return 0;
>+
>+	return -EINVAL;
>+}
>+
> static const struct hdmi_codec_ops sii902x_audio_codec_ops = {
> 	.hw_params = sii902x_audio_hw_params,
> 	.audio_shutdown = sii902x_audio_shutdown,
> 	.digital_mute = sii902x_audio_digital_mute,
> 	.get_eld = sii902x_audio_get_eld,
>+	.get_dai_id = sii902x_audio_get_dai_id,
> };
> 
> static int sii902x_audio_codec_init(struct sii902x *sii902x,
>@@ -750,10 +775,11 @@
> 		sii902x->audio.i2s_fifo_sequence[i] |= audio_fifo_id[i] |
> 			i2s_lane_id[lanes[i]] |	SII902X_TPI_I2S_FIFO_ENABLE;
> 
>+	sii902x->audio.mclk = devm_clk_get_optional(dev, "mclk");
> 	if (IS_ERR(sii902x->audio.mclk)) {
> 		dev_err(dev, "%s: No clock (audio mclk) found: %ld\n",
> 			__func__, PTR_ERR(sii902x->audio.mclk));
>-		return 0;
>+		return PTR_ERR(sii902x->audio.mclk);
> 	}
> 
> 	sii902x->audio.pdev = platform_device_register_data(
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c	2019-08-31 15:01:11.943736176 -0500
>@@ -508,8 +508,14 @@
> 	/* nshift factor = 0 */
> 	hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
> 
>-	hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
>-		    HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
>+	/* Use automatic CTS generation mode when CTS is not set */
>+	if (cts)
>+		hdmi_writeb(hdmi, ((cts >> 16) &
>+				   HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
>+				  HDMI_AUD_CTS3_CTS_MANUAL,
>+			    HDMI_AUD_CTS3);
>+	else
>+		hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
> 	hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
> 	hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
> 
>@@ -579,24 +585,33 @@
> {
> 	unsigned long ftdms = pixel_clk;
> 	unsigned int n, cts;
>+	u8 config3;
> 	u64 tmp;
> 
> 	n = hdmi_compute_n(sample_rate, pixel_clk);
> 
>-	/*
>-	 * Compute the CTS value from the N value.  Note that CTS and N
>-	 * can be up to 20 bits in total, so we need 64-bit math.  Also
>-	 * note that our TDMS clock is not fully accurate; it is accurate
>-	 * to kHz.  This can introduce an unnecessary remainder in the
>-	 * calculation below, so we don't try to warn about that.
>-	 */
>-	tmp = (u64)ftdms * n;
>-	do_div(tmp, 128 * sample_rate);
>-	cts = tmp;
>-
>-	dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
>-		__func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
>-		n, cts);
>+	config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
>+
>+	/* Only compute CTS when using internal AHB audio */
>+	if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
>+		/*
>+		 * Compute the CTS value from the N value.  Note that CTS and N
>+		 * can be up to 20 bits in total, so we need 64-bit math.  Also
>+		 * note that our TDMS clock is not fully accurate; it is
>+		 * accurate to kHz.  This can introduce an unnecessary remainder
>+		 * in the calculation below, so we don't try to warn about that.
>+		 */
>+		tmp = (u64)ftdms * n;
>+		do_div(tmp, 128 * sample_rate);
>+		cts = tmp;
>+
>+		dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
>+			__func__, sample_rate,
>+			ftdms / 1000000, (ftdms / 1000) % 1000,
>+			n, cts);
>+	} else {
>+		cts = 0;
>+	}
> 
> 	spin_lock_irq(&hdmi->audio_lock);
> 	hdmi->audio_n = n;
>@@ -2185,8 +2200,10 @@
> 
> 	drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
> 
>-	drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs,
>-			   DRM_MODE_CONNECTOR_HDMIA);
>+	drm_connector_init_with_ddc(bridge->dev, connector,
>+				    &dw_hdmi_connector_funcs,
>+				    DRM_MODE_CONNECTOR_HDMIA,
>+				    hdmi->ddc);
> 
> 	drm_connector_attach_encoder(connector, encoder);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c	2019-08-31 15:01:11.943736176 -0500
>@@ -10,6 +10,7 @@
> 
> #include <linux/clk.h>
> #include <linux/component.h>
>+#include <linux/debugfs.h>
> #include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
>@@ -89,6 +90,8 @@
> #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS	0x1
> #define VID_MODE_TYPE_BURST			0x2
> #define VID_MODE_TYPE_MASK			0x3
>+#define VID_MODE_VPG_ENABLE		BIT(16)
>+#define VID_MODE_VPG_HORIZONTAL		BIT(24)
> 
> #define DSI_VID_PKT_SIZE		0x3c
> #define VID_PKT_SIZE(p)			((p) & 0x3fff)
>@@ -233,6 +236,13 @@
> 	u32 format;
> 	unsigned long mode_flags;
> 
>+#ifdef CONFIG_DEBUG_FS
>+	struct dentry *debugfs;
>+
>+	bool vpg;
>+	bool vpg_horizontal;
>+#endif /* CONFIG_DEBUG_FS */
>+
> 	struct dw_mipi_dsi *master; /* dual-dsi master ptr */
> 	struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
> 
>@@ -518,6 +528,13 @@
> 	else
> 		val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
> 
>+#ifdef CONFIG_DEBUG_FS
>+	if (dsi->vpg) {
>+		val |= VID_MODE_VPG_ENABLE;
>+		val |= dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0;
>+	}
>+#endif /* CONFIG_DEBUG_FS */
>+
> 	dsi_write(dsi, DSI_VID_MODE_CFG, val);
> }
> 
>@@ -930,6 +947,33 @@
> 	.attach	      = dw_mipi_dsi_bridge_attach,
> };
> 
>+#ifdef CONFIG_DEBUG_FS
>+
>+static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi)
>+{
>+	dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL);
>+	if (IS_ERR(dsi->debugfs)) {
>+		dev_err(dsi->dev, "failed to create debugfs root\n");
>+		return;
>+	}
>+
>+	debugfs_create_bool("vpg", 0660, dsi->debugfs, &dsi->vpg);
>+	debugfs_create_bool("vpg_horizontal", 0660, dsi->debugfs,
>+			    &dsi->vpg_horizontal);
>+}
>+
>+static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi)
>+{
>+	debugfs_remove_recursive(dsi->debugfs);
>+}
>+
>+#else
>+
>+static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { }
>+static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
>+
>+#endif /* CONFIG_DEBUG_FS */
>+
> static struct dw_mipi_dsi *
> __dw_mipi_dsi_probe(struct platform_device *pdev,
> 		    const struct dw_mipi_dsi_plat_data *plat_data)
>@@ -1000,6 +1044,7 @@
> 		clk_disable_unprepare(dsi->pclk);
> 	}
> 
>+	dw_mipi_dsi_debugfs_init(dsi);
> 	pm_runtime_enable(dev);
> 
> 	dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
>@@ -1007,6 +1052,7 @@
> 	ret = mipi_dsi_host_register(&dsi->dsi_host);
> 	if (ret) {
> 		dev_err(dev, "Failed to register MIPI host: %d\n", ret);
>+		dw_mipi_dsi_debugfs_remove(dsi);
> 		return ERR_PTR(ret);
> 	}
> 
>@@ -1024,6 +1070,7 @@
> 	mipi_dsi_host_unregister(&dsi->dsi_host);
> 
> 	pm_runtime_disable(dsi->dev);
>+	dw_mipi_dsi_debugfs_remove(dsi);
> }
> 
> void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/tc358767.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/tc358767.c
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/tc358767.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/tc358767.c	2019-08-31 15:01:11.943736176 -0500
>@@ -15,6 +15,7 @@
>  * Author: Rob Clark <robdclark@gmail.com>
>  */
> 
>+#include <linux/bitfield.h>
> #include <linux/clk.h>
> #include <linux/device.h>
> #include <linux/gpio/consumer.h>
>@@ -47,6 +48,7 @@
> 
> /* Video Path */
> #define VPCTRL0			0x0450
>+#define VSDELAY			GENMASK(31, 20)
> #define OPXLFMT_RGB666			(0 << 8)
> #define OPXLFMT_RGB888			(1 << 8)
> #define FRMSYNC_DISABLED		(0 << 4) /* Video Timing Gen Disabled */
>@@ -54,9 +56,17 @@
> #define MSF_DISABLED			(0 << 0) /* Magic Square FRC disabled */
> #define MSF_ENABLED			(1 << 0) /* Magic Square FRC enabled */
> #define HTIM01			0x0454
>+#define HPW			GENMASK(8, 0)
>+#define HBPR			GENMASK(24, 16)
> #define HTIM02			0x0458
>+#define HDISPR			GENMASK(10, 0)
>+#define HFPR			GENMASK(24, 16)
> #define VTIM01			0x045c
>+#define VSPR			GENMASK(7, 0)
>+#define VBPR			GENMASK(23, 16)
> #define VTIM02			0x0460
>+#define VFPR			GENMASK(23, 16)
>+#define VDISPR			GENMASK(10, 0)
> #define VFUEN0			0x0464
> #define VFUEN				BIT(0)   /* Video Frame Timing Upload */
> 
>@@ -70,6 +80,13 @@
> #define DP0_VIDSRC_DSI_RX		(1 << 0)
> #define DP0_VIDSRC_DPI_RX		(2 << 0)
> #define DP0_VIDSRC_COLOR_BAR		(3 << 0)
>+#define SYSRSTENB		0x050c
>+#define ENBI2C				(1 << 0)
>+#define ENBLCD0				(1 << 2)
>+#define ENBBM				(1 << 3)
>+#define ENBDSIRX			(1 << 4)
>+#define ENBREG				(1 << 5)
>+#define ENBHDCP				(1 << 8)
> #define GPIOM			0x0540
> #define GPIOC			0x0544
> #define GPIOO			0x0548
>@@ -99,19 +116,35 @@
> /* Main Channel */
> #define DP0_SECSAMPLE		0x0640
> #define DP0_VIDSYNCDELAY	0x0644
>+#define VID_SYNC_DLY		GENMASK(15, 0)
>+#define THRESH_DLY		GENMASK(31, 16)
>+
> #define DP0_TOTALVAL		0x0648
>+#define H_TOTAL			GENMASK(15, 0)
>+#define V_TOTAL			GENMASK(31, 16)
> #define DP0_STARTVAL		0x064c
>+#define H_START			GENMASK(15, 0)
>+#define V_START			GENMASK(31, 16)
> #define DP0_ACTIVEVAL		0x0650
>+#define H_ACT			GENMASK(15, 0)
>+#define V_ACT			GENMASK(31, 16)
>+
> #define DP0_SYNCVAL		0x0654
>+#define VS_WIDTH		GENMASK(30, 16)
>+#define HS_WIDTH		GENMASK(14, 0)
> #define SYNCVAL_HS_POL_ACTIVE_LOW	(1 << 15)
> #define SYNCVAL_VS_POL_ACTIVE_LOW	(1 << 31)
> #define DP0_MISC		0x0658
> #define TU_SIZE_RECOMMENDED		(63) /* LSCLK cycles per TU */
>+#define MAX_TU_SYMBOL		GENMASK(28, 23)
>+#define TU_SIZE			GENMASK(21, 16)
> #define BPC_6				(0 << 5)
> #define BPC_8				(1 << 5)
> 
> /* AUX channel */
> #define DP0_AUXCFG0		0x0660
>+#define DP0_AUXCFG0_BSIZE	GENMASK(11, 8)
>+#define DP0_AUXCFG0_ADDR_ONLY	BIT(4)
> #define DP0_AUXCFG1		0x0664
> #define AUX_RX_FILTER_EN		BIT(16)
> 
>@@ -119,10 +152,10 @@
> #define DP0_AUXWDATA(i)		(0x066c + (i) * 4)
> #define DP0_AUXRDATA(i)		(0x067c + (i) * 4)
> #define DP0_AUXSTATUS		0x068c
>-#define AUX_STATUS_MASK			0xf0
>-#define AUX_STATUS_SHIFT		4
>-#define AUX_TIMEOUT			BIT(1)
>-#define AUX_BUSY			BIT(0)
>+#define AUX_BYTES		GENMASK(15, 8)
>+#define AUX_STATUS		GENMASK(7, 4)
>+#define AUX_TIMEOUT		BIT(1)
>+#define AUX_BUSY		BIT(0)
> #define DP0_AUXI2CADR		0x0698
> 
> /* Link Training */
>@@ -183,6 +216,12 @@
> 
> /* Test & Debug */
> #define TSTCTL			0x0a00
>+#define COLOR_R			GENMASK(31, 24)
>+#define COLOR_G			GENMASK(23, 16)
>+#define COLOR_B			GENMASK(15, 8)
>+#define ENI2CFILTER		BIT(4)
>+#define COLOR_BAR_MODE		GENMASK(1, 0)
>+#define COLOR_BAR_MODE_BARS	2
> #define PLL_DBG			0x0a04
> 
> static bool tc_test_pattern;
>@@ -241,137 +280,131 @@
> 	return container_of(c, struct tc_data, connector);
> }
> 
>-/* Simple macros to avoid repeated error checks */
>-#define tc_write(reg, var)					\
>-	do {							\
>-		ret = regmap_write(tc->regmap, reg, var);	\
>-		if (ret)					\
>-			goto err;				\
>-	} while (0)
>-#define tc_read(reg, var)					\
>-	do {							\
>-		ret = regmap_read(tc->regmap, reg, var);	\
>-		if (ret)					\
>-			goto err;				\
>-	} while (0)
>-
>-static inline int tc_poll_timeout(struct regmap *map, unsigned int addr,
>+static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
> 				  unsigned int cond_mask,
> 				  unsigned int cond_value,
> 				  unsigned long sleep_us, u64 timeout_us)
> {
>-	ktime_t timeout = ktime_add_us(ktime_get(), timeout_us);
> 	unsigned int val;
>-	int ret;
> 
>-	for (;;) {
>-		ret = regmap_read(map, addr, &val);
>-		if (ret)
>-			break;
>-		if ((val & cond_mask) == cond_value)
>-			break;
>-		if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) {
>-			ret = regmap_read(map, addr, &val);
>-			break;
>-		}
>-		if (sleep_us)
>-			usleep_range((sleep_us >> 2) + 1, sleep_us);
>-	}
>-	return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT);
>+	return regmap_read_poll_timeout(tc->regmap, addr, val,
>+					(val & cond_mask) == cond_value,
>+					sleep_us, timeout_us);
> }
> 
>-static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms)
>+static int tc_aux_wait_busy(struct tc_data *tc)
> {
>-	return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0,
>-			       1000, 1000 * timeout_ms);
>+	return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 1000, 100000);
> }
> 
>-static int tc_aux_get_status(struct tc_data *tc, u8 *reply)
>+static int tc_aux_write_data(struct tc_data *tc, const void *data,
>+			     size_t size)
> {
>-	int ret;
>-	u32 value;
>+	u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 };
>+	int ret, count = ALIGN(size, sizeof(u32));
> 
>-	ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value);
>-	if (ret < 0)
>+	memcpy(auxwdata, data, size);
>+
>+	ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
>+	if (ret)
> 		return ret;
> 
>-	if (value & AUX_BUSY) {
>-		dev_err(tc->dev, "aux busy!\n");
>-		return -EBUSY;
>-	}
>+	return size;
>+}
> 
>-	if (value & AUX_TIMEOUT) {
>-		dev_err(tc->dev, "aux access timeout!\n");
>-		return -ETIMEDOUT;
>-	}
>+static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
>+{
>+	u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)];
>+	int ret, count = ALIGN(size, sizeof(u32));
> 
>-	*reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT;
>-	return 0;
>+	ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
>+	if (ret)
>+		return ret;
>+
>+	memcpy(data, auxrdata, size);
>+
>+	return size;
>+}
>+
>+static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size)
>+{
>+	u32 auxcfg0 = msg->request;
>+
>+	if (size)
>+		auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1);
>+	else
>+		auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY;
>+
>+	return auxcfg0;
> }
> 
> static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
> 			       struct drm_dp_aux_msg *msg)
> {
> 	struct tc_data *tc = aux_to_tc(aux);
>-	size_t size = min_t(size_t, 8, msg->size);
>+	size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
> 	u8 request = msg->request & ~DP_AUX_I2C_MOT;
>-	u8 *buf = msg->buffer;
>-	u32 tmp = 0;
>-	int i = 0;
>+	u32 auxstatus;
> 	int ret;
> 
>-	if (size == 0)
>-		return 0;
>-
>-	ret = tc_aux_wait_busy(tc, 100);
>+	ret = tc_aux_wait_busy(tc);
> 	if (ret)
>-		goto err;
>+		return ret;
> 
>-	if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) {
>-		/* Store data */
>-		while (i < size) {
>-			if (request == DP_AUX_NATIVE_WRITE)
>-				tmp = tmp | (buf[i] << (8 * (i & 0x3)));
>-			else
>-				tmp = (tmp << 8) | buf[i];
>-			i++;
>-			if (((i % 4) == 0) || (i == size)) {
>-				tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp);
>-				tmp = 0;
>-			}
>+	switch (request) {
>+	case DP_AUX_NATIVE_READ:
>+	case DP_AUX_I2C_READ:
>+		break;
>+	case DP_AUX_NATIVE_WRITE:
>+	case DP_AUX_I2C_WRITE:
>+		if (size) {
>+			ret = tc_aux_write_data(tc, msg->buffer, size);
>+			if (ret < 0)
>+				return ret;
> 		}
>-	} else if (request != DP_AUX_I2C_READ &&
>-		   request != DP_AUX_NATIVE_READ) {
>+		break;
>+	default:
> 		return -EINVAL;
> 	}
> 
> 	/* Store address */
>-	tc_write(DP0_AUXADDR, msg->address);
>+	ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
>+	if (ret)
>+		return ret;
> 	/* Start transfer */
>-	tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request);
>+	ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
>+	if (ret)
>+		return ret;
> 
>-	ret = tc_aux_wait_busy(tc, 100);
>+	ret = tc_aux_wait_busy(tc);
> 	if (ret)
>-		goto err;
>+		return ret;
> 
>-	ret = tc_aux_get_status(tc, &msg->reply);
>+	ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
> 	if (ret)
>-		goto err;
>+		return ret;
> 
>-	if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) {
>-		/* Read data */
>-		while (i < size) {
>-			if ((i % 4) == 0)
>-				tc_read(DP0_AUXRDATA(i >> 2), &tmp);
>-			buf[i] = tmp & 0xff;
>-			tmp = tmp >> 8;
>-			i++;
>-		}
>+	if (auxstatus & AUX_TIMEOUT)
>+		return -ETIMEDOUT;
>+	/*
>+	 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still
>+	 * reports 1 byte transferred in its status. To deal we that
>+	 * we ignore aux_bytes field if we know that this was an
>+	 * address-only transfer
>+	 */
>+	if (size)
>+		size = FIELD_GET(AUX_BYTES, auxstatus);
>+	msg->reply = FIELD_GET(AUX_STATUS, auxstatus);
>+
>+	switch (request) {
>+	case DP_AUX_NATIVE_READ:
>+	case DP_AUX_I2C_READ:
>+		if (size)
>+			return tc_aux_read_data(tc, msg->buffer, size);
>+		break;
> 	}
> 
> 	return size;
>-err:
>-	return ret;
> }
> 
> static const char * const training_pattern1_errors[] = {
>@@ -411,10 +444,18 @@
> 	return reg;
> }
> 
>-static void tc_wait_pll_lock(struct tc_data *tc)
>+static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
> {
>+	int ret;
>+
>+	ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
>+	if (ret)
>+		return ret;
>+
> 	/* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
> 	usleep_range(3000, 6000);
>+
>+	return 0;
> }
> 
> static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
>@@ -428,6 +469,7 @@
> 	int ext_div[] = {1, 2, 3, 5, 7};
> 	int best_pixelclock = 0;
> 	int vco_hi = 0;
>+	u32 pxl_pllparam;
> 
> 	dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
> 		refclk);
>@@ -497,24 +539,23 @@
> 		best_mul = 0;
> 
> 	/* Power up PLL and switch to bypass */
>-	tc_write(PXL_PLLCTRL, PLLBYP | PLLEN);
>-
>-	tc_write(PXL_PLLPARAM,
>-		 (vco_hi << 24) |		/* For PLL VCO >= 300 MHz = 1 */
>-		 (ext_div[best_pre] << 20) |	/* External Pre-divider */
>-		 (ext_div[best_post] << 16) |	/* External Post-divider */
>-		 IN_SEL_REFCLK |		/* Use RefClk as PLL input */
>-		 (best_div << 8) |		/* Divider for PLL RefClk */
>-		 (best_mul << 0));		/* Multiplier for PLL */
>+	ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
>+	if (ret)
>+		return ret;
> 
>-	/* Force PLL parameter update and disable bypass */
>-	tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN);
>+	pxl_pllparam  = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
>+	pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
>+	pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
>+	pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
>+	pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
>+	pxl_pllparam |= best_mul; /* Multiplier for PLL */
> 
>-	tc_wait_pll_lock(tc);
>+	ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
>+	if (ret)
>+		return ret;
> 
>-	return 0;
>-err:
>-	return ret;
>+	/* Force PLL parameter update and disable bypass */
>+	return tc_pllupdate(tc, PXL_PLLCTRL);
> }
> 
> static int tc_pxl_pll_dis(struct tc_data *tc)
>@@ -525,7 +566,6 @@
> 
> static int tc_stream_clock_calc(struct tc_data *tc)
> {
>-	int ret;
> 	/*
> 	 * If the Stream clock and Link Symbol clock are
> 	 * asynchronous with each other, the value of M changes over
>@@ -541,56 +581,63 @@
> 	 * M/N = f_STRMCLK / f_LSCLK
> 	 *
> 	 */
>-	tc_write(DP0_VIDMNGEN1, 32768);
>-
>-	return 0;
>-err:
>-	return ret;
>+	return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
> }
> 
>-static int tc_aux_link_setup(struct tc_data *tc)
>+static int tc_set_syspllparam(struct tc_data *tc)
> {
> 	unsigned long rate;
>-	u32 value;
>-	int ret;
>+	u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
> 
> 	rate = clk_get_rate(tc->refclk);
> 	switch (rate) {
> 	case 38400000:
>-		value = REF_FREQ_38M4;
>+		pllparam |= REF_FREQ_38M4;
> 		break;
> 	case 26000000:
>-		value = REF_FREQ_26M;
>+		pllparam |= REF_FREQ_26M;
> 		break;
> 	case 19200000:
>-		value = REF_FREQ_19M2;
>+		pllparam |= REF_FREQ_19M2;
> 		break;
> 	case 13000000:
>-		value = REF_FREQ_13M;
>+		pllparam |= REF_FREQ_13M;
> 		break;
> 	default:
> 		dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
> 		return -EINVAL;
> 	}
> 
>-	/* Setup DP-PHY / PLL */
>-	value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
>-	tc_write(SYS_PLLPARAM, value);
>+	return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
>+}
> 
>-	tc_write(DP_PHY_CTRL, BGREN | PWR_SW_EN | PHY_A0_EN);
>+static int tc_aux_link_setup(struct tc_data *tc)
>+{
>+	int ret;
>+	u32 dp0_auxcfg1;
>+
>+	/* Setup DP-PHY / PLL */
>+	ret = tc_set_syspllparam(tc);
>+	if (ret)
>+		goto err;
> 
>+	ret = regmap_write(tc->regmap, DP_PHY_CTRL,
>+			   BGREN | PWR_SW_EN | PHY_A0_EN);
>+	if (ret)
>+		goto err;
> 	/*
> 	 * Initially PLLs are in bypass. Force PLL parameter update,
> 	 * disable PLL bypass, enable PLL
> 	 */
>-	tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
>-	tc_wait_pll_lock(tc);
>+	ret = tc_pllupdate(tc, DP0_PLLCTRL);
>+	if (ret)
>+		goto err;
> 
>-	tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
>-	tc_wait_pll_lock(tc);
>+	ret = tc_pllupdate(tc, DP1_PLLCTRL);
>+	if (ret)
>+		goto err;
> 
>-	ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1,
>-			      1000);
>+	ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000);
> 	if (ret == -ETIMEDOUT) {
> 		dev_err(tc->dev, "Timeout waiting for PHY to become ready");
> 		return ret;
>@@ -599,9 +646,13 @@
> 	}
> 
> 	/* Setup AUX link */
>-	tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN |
>-		 (0x06 << 8) |	/* Aux Bit Period Calculator Threshold */
>-		 (0x3f << 0));	/* Aux Response Timeout Timer */
>+	dp0_auxcfg1  = AUX_RX_FILTER_EN;
>+	dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */
>+	dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */
>+
>+	ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
>+	if (ret)
>+		goto err;
> 
> 	return 0;
> err:
>@@ -612,8 +663,7 @@
> static int tc_get_display_props(struct tc_data *tc)
> {
> 	int ret;
>-	/* temp buffer */
>-	u8 tmp[8];
>+	u8 reg;
> 
> 	/* Read DP Rx Link Capability */
> 	ret = drm_dp_link_probe(&tc->aux, &tc->link.base);
>@@ -629,21 +679,21 @@
> 		tc->link.base.num_lanes = 2;
> 	}
> 
>-	ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp);
>+	ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, &reg);
> 	if (ret < 0)
> 		goto err_dpcd_read;
>-	tc->link.spread = tmp[0] & DP_MAX_DOWNSPREAD_0_5;
>+	tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
> 
>-	ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp);
>+	ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, &reg);
> 	if (ret < 0)
> 		goto err_dpcd_read;
> 
> 	tc->link.scrambler_dis = false;
> 	/* read assr */
>-	ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp);
>+	ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, &reg);
> 	if (ret < 0)
> 		goto err_dpcd_read;
>-	tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
>+	tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
> 
> 	dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
> 		tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
>@@ -677,6 +727,7 @@
> 	int upper_margin = mode->vtotal - mode->vsync_end;
> 	int lower_margin = mode->vsync_start - mode->vdisplay;
> 	int vsync_len = mode->vsync_end - mode->vsync_start;
>+	u32 dp0_syncval;
> 
> 	/*
> 	 * Recommended maximum number of symbols transferred in a transfer unit:
>@@ -701,156 +752,193 @@
> 	 * assume we do not need any delay when DPI is a source of
> 	 * sync signals
> 	 */
>-	tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ |
>-		 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
>-	tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */
>-			 (ALIGN(hsync_len, 2) << 0));	 /* Hsync */
>-	tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) |  /* H front porch */
>-			 (ALIGN(mode->hdisplay, 2) << 0)); /* width */
>-	tc_write(VTIM01, (upper_margin << 16) |		/* V back porch */
>-			 (vsync_len << 0));		/* Vsync */
>-	tc_write(VTIM02, (lower_margin << 16) |		/* V front porch */
>-			 (mode->vdisplay << 0));	/* height */
>-	tc_write(VFUEN0, VFUEN);		/* update settings */
>+	ret = regmap_write(tc->regmap, VPCTRL0,
>+			   FIELD_PREP(VSDELAY, 0) |
>+			   OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
>+	if (ret)
>+		return ret;
>+
>+	ret = regmap_write(tc->regmap, HTIM01,
>+			   FIELD_PREP(HBPR, ALIGN(left_margin, 2)) |
>+			   FIELD_PREP(HPW, ALIGN(hsync_len, 2)));
>+	if (ret)
>+		return ret;
>+
>+	ret = regmap_write(tc->regmap, HTIM02,
>+			   FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) |
>+			   FIELD_PREP(HFPR, ALIGN(right_margin, 2)));
>+	if (ret)
>+		return ret;
>+
>+	ret = regmap_write(tc->regmap, VTIM01,
>+			   FIELD_PREP(VBPR, upper_margin) |
>+			   FIELD_PREP(VSPR, vsync_len));
>+	if (ret)
>+		return ret;
>+
>+	ret = regmap_write(tc->regmap, VTIM02,
>+			   FIELD_PREP(VFPR, lower_margin) |
>+			   FIELD_PREP(VDISPR, mode->vdisplay));
>+	if (ret)
>+		return ret;
>+
>+	ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
>+	if (ret)
>+		return ret;
> 
> 	/* Test pattern settings */
>-	tc_write(TSTCTL,
>-		 (120 << 24) |	/* Red Color component value */
>-		 (20 << 16) |	/* Green Color component value */
>-		 (99 << 8) |	/* Blue Color component value */
>-		 (1 << 4) |	/* Enable I2C Filter */
>-		 (2 << 0) |	/* Color bar Mode */
>-		 0);
>+	ret = regmap_write(tc->regmap, TSTCTL,
>+			   FIELD_PREP(COLOR_R, 120) |
>+			   FIELD_PREP(COLOR_G, 20) |
>+			   FIELD_PREP(COLOR_B, 99) |
>+			   ENI2CFILTER |
>+			   FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS));
>+	if (ret)
>+		return ret;
> 
> 	/* DP Main Stream Attributes */
> 	vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
>-	tc_write(DP0_VIDSYNCDELAY,
>-		 (max_tu_symbol << 16) |	/* thresh_dly */
>-		 (vid_sync_dly << 0));
>+	ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
>+		 FIELD_PREP(THRESH_DLY, max_tu_symbol) |
>+		 FIELD_PREP(VID_SYNC_DLY, vid_sync_dly));
>+
>+	ret = regmap_write(tc->regmap, DP0_TOTALVAL,
>+			   FIELD_PREP(H_TOTAL, mode->htotal) |
>+			   FIELD_PREP(V_TOTAL, mode->vtotal));
>+	if (ret)
>+		return ret;
>+
>+	ret = regmap_write(tc->regmap, DP0_STARTVAL,
>+			   FIELD_PREP(H_START, left_margin + hsync_len) |
>+			   FIELD_PREP(V_START, upper_margin + vsync_len));
>+	if (ret)
>+		return ret;
> 
>-	tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
>+	ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
>+			   FIELD_PREP(V_ACT, mode->vdisplay) |
>+			   FIELD_PREP(H_ACT, mode->hdisplay));
>+	if (ret)
>+		return ret;
> 
>-	tc_write(DP0_STARTVAL,
>-		 ((upper_margin + vsync_len) << 16) |
>-		 ((left_margin + hsync_len) << 0));
>+	dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) |
>+		      FIELD_PREP(HS_WIDTH, hsync_len);
> 
>-	tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
>+	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
>+		dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW;
> 
>-	tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) |
>-		 ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) |
>-		 ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0));
>+	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
>+		dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW;
> 
>-	tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
>-		 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
>+	ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
>+	if (ret)
>+		return ret;
> 
>-	tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) |
>+	ret = regmap_write(tc->regmap, DPIPXLFMT,
>+			   VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
>+			   DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 |
>+			   DPI_BPP_RGB888);
>+	if (ret)
>+		return ret;
>+
>+	ret = regmap_write(tc->regmap, DP0_MISC,
>+			   FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) |
>+			   FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) |
> 			   BPC_8);
>+	if (ret)
>+		return ret;
> 
> 	return 0;
>-err:
>-	return ret;
> }
> 
> static int tc_wait_link_training(struct tc_data *tc)
> {
>-	u32 timeout = 1000;
> 	u32 value;
> 	int ret;
> 
>-	do {
>-		udelay(1);
>-		tc_read(DP0_LTSTAT, &value);
>-	} while ((!(value & LT_LOOPDONE)) && (--timeout));
>-
>-	if (timeout == 0) {
>+	ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
>+			      LT_LOOPDONE, 1, 1000);
>+	if (ret) {
> 		dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
>-		return -ETIMEDOUT;
>+		return ret;
> 	}
> 
>-	return (value >> 8) & 0x7;
>+	ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
>+	if (ret)
>+		return ret;
> 
>-err:
>-	return ret;
>+	return (value >> 8) & 0x7;
> }
> 
> static int tc_main_link_enable(struct tc_data *tc)
> {
> 	struct drm_dp_aux *aux = &tc->aux;
> 	struct device *dev = tc->dev;
>-	unsigned int rate;
> 	u32 dp_phy_ctrl;
>-	int timeout;
> 	u32 value;
> 	int ret;
>-	u8 tmp[8];
>+	u8 tmp[DP_LINK_STATUS_SIZE];
> 
> 	dev_dbg(tc->dev, "link enable\n");
> 
>-	tc_read(DP0CTL, &value);
>-	if (WARN_ON(value & DP_EN))
>-		tc_write(DP0CTL, 0);
>+	ret = regmap_read(tc->regmap, DP0CTL, &value);
>+	if (ret)
>+		return ret;
>+
>+	if (WARN_ON(value & DP_EN)) {
>+		ret = regmap_write(tc->regmap, DP0CTL, 0);
>+		if (ret)
>+			return ret;
>+	}
> 
>-	tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
>+	ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
>+	if (ret)
>+		return ret;
> 	/* SSCG and BW27 on DP1 must be set to the same as on DP0 */
>-	tc_write(DP1_SRCCTRL,
>+	ret = regmap_write(tc->regmap, DP1_SRCCTRL,
> 		 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
> 		 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
>+	if (ret)
>+		return ret;
> 
>-	rate = clk_get_rate(tc->refclk);
>-	switch (rate) {
>-	case 38400000:
>-		value = REF_FREQ_38M4;
>-		break;
>-	case 26000000:
>-		value = REF_FREQ_26M;
>-		break;
>-	case 19200000:
>-		value = REF_FREQ_19M2;
>-		break;
>-	case 13000000:
>-		value = REF_FREQ_13M;
>-		break;
>-	default:
>-		return -EINVAL;
>-	}
>-	value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
>-	tc_write(SYS_PLLPARAM, value);
>+	ret = tc_set_syspllparam(tc);
>+	if (ret)
>+		return ret;
> 
> 	/* Setup Main Link */
> 	dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
> 	if (tc->link.base.num_lanes == 2)
> 		dp_phy_ctrl |= PHY_2LANE;
>-	tc_write(DP_PHY_CTRL, dp_phy_ctrl);
>+
>+	ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
>+	if (ret)
>+		return ret;
> 
> 	/* PLL setup */
>-	tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
>-	tc_wait_pll_lock(tc);
>+	ret = tc_pllupdate(tc, DP0_PLLCTRL);
>+	if (ret)
>+		return ret;
> 
>-	tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
>-	tc_wait_pll_lock(tc);
>+	ret = tc_pllupdate(tc, DP1_PLLCTRL);
>+	if (ret)
>+		return ret;
> 
> 	/* Reset/Enable Main Links */
> 	dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
>-	tc_write(DP_PHY_CTRL, dp_phy_ctrl);
>+	ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
> 	usleep_range(100, 200);
> 	dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
>-	tc_write(DP_PHY_CTRL, dp_phy_ctrl);
>-
>-	timeout = 1000;
>-	do {
>-		tc_read(DP_PHY_CTRL, &value);
>-		udelay(1);
>-	} while ((!(value & PHY_RDY)) && (--timeout));
>+	ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
> 
>-	if (timeout == 0) {
>+	ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1, 1000);
>+	if (ret) {
> 		dev_err(dev, "timeout waiting for phy become ready");
>-		return -ETIMEDOUT;
>+		return ret;
> 	}
> 
> 	/* Set misc: 8 bits per color */
> 	ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
> 	if (ret)
>-		goto err;
>+		return ret;
> 
> 	/*
> 	 * ASSR mode
>@@ -903,53 +991,71 @@
> 	/* Clock-Recovery */
> 
> 	/* Set DPCD 0x102 for Training Pattern 1 */
>-	tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE |
>-		 DP_TRAINING_PATTERN_1);
>+	ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
>+			   DP_LINK_SCRAMBLING_DISABLE |
>+			   DP_TRAINING_PATTERN_1);
>+	if (ret)
>+		return ret;
> 
>-	tc_write(DP0_LTLOOPCTRL,
>-		 (15 << 28) |	/* Defer Iteration Count */
>-		 (15 << 24) |	/* Loop Iteration Count */
>-		 (0xd << 0));	/* Loop Timer Delay */
>+	ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
>+			   (15 << 28) |	/* Defer Iteration Count */
>+			   (15 << 24) |	/* Loop Iteration Count */
>+			   (0xd << 0));	/* Loop Timer Delay */
>+	if (ret)
>+		return ret;
> 
>-	tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
>-		 DP0_SRCCTRL_AUTOCORRECT | DP0_SRCCTRL_TP1);
>+	ret = regmap_write(tc->regmap, DP0_SRCCTRL,
>+			   tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
>+			   DP0_SRCCTRL_AUTOCORRECT |
>+			   DP0_SRCCTRL_TP1);
>+	if (ret)
>+		return ret;
> 
> 	/* Enable DP0 to start Link Training */
>-	tc_write(DP0CTL,
>-		 ((tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? EF_EN : 0) |
>-		 DP_EN);
>+	ret = regmap_write(tc->regmap, DP0CTL,
>+			   ((tc->link.base.capabilities &
>+			     DP_LINK_CAP_ENHANCED_FRAMING) ? EF_EN : 0) |
>+			   DP_EN);
>+	if (ret)
>+		return ret;
> 
> 	/* wait */
>+
> 	ret = tc_wait_link_training(tc);
> 	if (ret < 0)
>-		goto err;
>+		return ret;
> 
> 	if (ret) {
> 		dev_err(tc->dev, "Link training phase 1 failed: %s\n",
> 			training_pattern1_errors[ret]);
>-		ret = -ENODEV;
>-		goto err;
>+		return -ENODEV;
> 	}
> 
> 	/* Channel Equalization */
> 
> 	/* Set DPCD 0x102 for Training Pattern 2 */
>-	tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE |
>-		 DP_TRAINING_PATTERN_2);
>+	ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
>+			   DP_LINK_SCRAMBLING_DISABLE |
>+			   DP_TRAINING_PATTERN_2);
>+	if (ret)
>+		return ret;
> 
>-	tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
>-		 DP0_SRCCTRL_AUTOCORRECT | DP0_SRCCTRL_TP2);
>+	ret = regmap_write(tc->regmap, DP0_SRCCTRL,
>+			   tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
>+			   DP0_SRCCTRL_AUTOCORRECT |
>+			   DP0_SRCCTRL_TP2);
>+	if (ret)
>+		return ret;
> 
> 	/* wait */
> 	ret = tc_wait_link_training(tc);
> 	if (ret < 0)
>-		goto err;
>+		return ret;
> 
> 	if (ret) {
> 		dev_err(tc->dev, "Link training phase 2 failed: %s\n",
> 			training_pattern2_errors[ret]);
>-		ret = -ENODEV;
>-		goto err;
>+		return -ENODEV;
> 	}
> 
> 	/*
>@@ -962,7 +1068,10 @@
> 	 */
> 
> 	/* Clear Training Pattern, set AutoCorrect Mode = 1 */
>-	tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
>+	ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
>+			   DP0_SRCCTRL_AUTOCORRECT);
>+	if (ret)
>+		return ret;
> 
> 	/* Clear DPCD 0x102 */
> 	/* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
>@@ -1006,7 +1115,7 @@
> 		dev_err(dev, "0x0205 SINK_STATUS:               0x%02x\n", tmp[3]);
> 		dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1:    0x%02x\n", tmp[4]);
> 		dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3:    0x%02x\n", tmp[5]);
>-		goto err;
>+		return ret;
> 	}
> 
> 	return 0;
>@@ -1015,7 +1124,6 @@
> 	return ret;
> err_dpcd_write:
> 	dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
>-err:
> 	return ret;
> }
> 
>@@ -1025,12 +1133,11 @@
> 
> 	dev_dbg(tc->dev, "link disable\n");
> 
>-	tc_write(DP0_SRCCTRL, 0);
>-	tc_write(DP0CTL, 0);
>+	ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
>+	if (ret)
>+		return ret;
> 
>-	return 0;
>-err:
>-	return ret;
>+	return regmap_write(tc->regmap, DP0CTL, 0);
> }
> 
> static int tc_stream_enable(struct tc_data *tc)
>@@ -1045,7 +1152,7 @@
> 		ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
> 				    1000 * tc->mode.clock);
> 		if (ret)
>-			goto err;
>+			return ret;
> 	}
> 
> 	ret = tc_set_video_mode(tc, &tc->mode);
>@@ -1060,7 +1167,9 @@
> 	value = VID_MN_GEN | DP_EN;
> 	if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
> 		value |= EF_EN;
>-	tc_write(DP0CTL, value);
>+	ret = regmap_write(tc->regmap, DP0CTL, value);
>+	if (ret)
>+		return ret;
> 	/*
> 	 * VID_EN assertion should be delayed by at least N * LSCLK
> 	 * cycles from the time VID_MN_GEN is enabled in order to
>@@ -1070,36 +1179,35 @@
> 	 */
> 	usleep_range(500, 1000);
> 	value |= VID_EN;
>-	tc_write(DP0CTL, value);
>+	ret = regmap_write(tc->regmap, DP0CTL, value);
>+	if (ret)
>+		return ret;
> 	/* Set input interface */
> 	value = DP0_AUDSRC_NO_INPUT;
> 	if (tc_test_pattern)
> 		value |= DP0_VIDSRC_COLOR_BAR;
> 	else
> 		value |= DP0_VIDSRC_DPI_RX;
>-	tc_write(SYSCTRL, value);
>+	ret = regmap_write(tc->regmap, SYSCTRL, value);
>+	if (ret)
>+		return ret;
> 
> 	return 0;
>-err:
>-	return ret;
> }
> 
> static int tc_stream_disable(struct tc_data *tc)
> {
> 	int ret;
>-	u32 val;
> 
> 	dev_dbg(tc->dev, "disable video stream\n");
> 
>-	tc_read(DP0CTL, &val);
>-	val &= ~VID_EN;
>-	tc_write(DP0CTL, val);
>+	ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
>+	if (ret)
>+		return ret;
> 
> 	tc_pxl_pll_dis(tc);
> 
> 	return 0;
>-err:
>-	return ret;
> }
> 
> static void tc_bridge_pre_enable(struct drm_bridge *bridge)
>@@ -1251,7 +1359,9 @@
> 			return connector_status_unknown;
> 	}
> 
>-	tc_read(GPIOI, &val);
>+	ret = regmap_read(tc->regmap, GPIOI, &val);
>+	if (ret)
>+		return connector_status_unknown;
> 
> 	conn = val & BIT(tc->hpd_pin);
> 
>@@ -1259,9 +1369,6 @@
> 		return connector_status_connected;
> 	else
> 		return connector_status_disconnected;
>-
>-err:
>-	return connector_status_unknown;
> }
> 
> static const struct drm_connector_funcs tc_connector_funcs = {
>@@ -1497,6 +1604,22 @@
> 
> 	tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
> 
>+	if (!tc->reset_gpio) {
>+		/*
>+		 * If the reset pin isn't present, do a software reset. It isn't
>+		 * as thorough as the hardware reset, as we can't reset the I2C
>+		 * communication block for obvious reasons, but it's getting the
>+		 * chip into a defined state.
>+		 */
>+		regmap_update_bits(tc->regmap, SYSRSTENB,
>+				ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
>+				0);
>+		regmap_update_bits(tc->regmap, SYSRSTENB,
>+				ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP,
>+				ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP);
>+		usleep_range(5000, 10000);
>+	}
>+
> 	if (tc->hpd_pin >= 0) {
> 		u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
> 		u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/ti-sn65dsi86.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/ti-sn65dsi86.c
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/ti-sn65dsi86.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/ti-sn65dsi86.c	2019-08-31 15:01:11.943736176 -0500
>@@ -1,9 +1,11 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
>  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>+ * datasheet: http://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
>  */
> 
> #include <linux/clk.h>
>+#include <linux/debugfs.h>
> #include <linux/gpio/consumer.h>
> #include <linux/i2c.h>
> #include <linux/iopoll.h>
>@@ -90,6 +92,7 @@
> 	struct drm_dp_aux		aux;
> 	struct drm_bridge		bridge;
> 	struct drm_connector		connector;
>+	struct dentry			*debugfs;
> 	struct device_node		*host_node;
> 	struct mipi_dsi_device		*dsi;
> 	struct clk			*refclk;
>@@ -155,6 +158,42 @@
> 	SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL)
> };
> 
>+static int status_show(struct seq_file *s, void *data)
>+{
>+	struct ti_sn_bridge *pdata = s->private;
>+	unsigned int reg, val;
>+
>+	seq_puts(s, "STATUS REGISTERS:\n");
>+
>+	pm_runtime_get_sync(pdata->dev);
>+
>+	/* IRQ Status Registers, see Table 31 in datasheet */
>+	for (reg = 0xf0; reg <= 0xf8; reg++) {
>+		regmap_read(pdata->regmap, reg, &val);
>+		seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
>+	}
>+
>+	pm_runtime_put(pdata->dev);
>+
>+	return 0;
>+}
>+
>+DEFINE_SHOW_ATTRIBUTE(status);
>+
>+static void ti_sn_debugfs_init(struct ti_sn_bridge *pdata)
>+{
>+	pdata->debugfs = debugfs_create_dir(dev_name(pdata->dev), NULL);
>+
>+	debugfs_create_file("status", 0600, pdata->debugfs, pdata,
>+			&status_fops);
>+}
>+
>+static void ti_sn_debugfs_remove(struct ti_sn_bridge *pdata)
>+{
>+	debugfs_remove_recursive(pdata->debugfs);
>+	pdata->debugfs = NULL;
>+}
>+
> /* Connector funcs */
> static struct ti_sn_bridge *
> connector_to_ti_sn_bridge(struct drm_connector *connector)
>@@ -275,8 +314,7 @@
> 	/* TODO: setting to 4 lanes always for now */
> 	dsi->lanes = 4;
> 	dsi->format = MIPI_DSI_FMT_RGB888;
>-	dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
>-			  MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE;
>+	dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
> 
> 	/* check if continuous dsi clock is required or not */
> 	pm_runtime_get_sync(pdata->dev);
>@@ -731,6 +769,8 @@
> 
> 	drm_bridge_add(&pdata->bridge);
> 
>+	ti_sn_debugfs_init(pdata);
>+
> 	return 0;
> }
> 
>@@ -741,6 +781,8 @@
> 	if (!pdata)
> 		return -EINVAL;
> 
>+	ti_sn_debugfs_remove(pdata);
>+
> 	of_node_put(pdata->host_node);
> 
> 	pm_runtime_disable(pdata->dev);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/bridge/ti-tfp410.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/ti-tfp410.c
>--- linux-5.3-rc6/drivers/gpu/drm/bridge/ti-tfp410.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/bridge/ti-tfp410.c	2019-08-31 15:01:11.943736176 -0500
>@@ -134,8 +134,10 @@
> 
> 	drm_connector_helper_add(&dvi->connector,
> 				 &tfp410_con_helper_funcs);
>-	ret = drm_connector_init(bridge->dev, &dvi->connector,
>-				 &tfp410_con_funcs, dvi->connector_type);
>+	ret = drm_connector_init_with_ddc(bridge->dev, &dvi->connector,
>+					  &tfp410_con_funcs,
>+					  dvi->connector_type,
>+					  dvi->ddc);
> 	if (ret) {
> 		dev_err(dvi->dev, "drm_connector_init() failed: %d\n", ret);
> 		return ret;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/cirrus/cirrus.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/cirrus/cirrus.c
>--- linux-5.3-rc6/drivers/gpu/drm/cirrus/cirrus.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/cirrus/cirrus.c	2019-08-31 15:01:11.943736176 -0500
>@@ -513,7 +513,7 @@
> DEFINE_DRM_GEM_SHMEM_FOPS(cirrus_fops);
> 
> static struct drm_driver cirrus_driver = {
>-	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC | DRIVER_PRIME,
>+	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> 
> 	.name		 = DRIVER_NAME,
> 	.desc		 = DRIVER_DESC,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_agpsupport.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_agpsupport.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_agpsupport.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_agpsupport.c	2019-08-31 15:01:11.943736176 -0500
>@@ -1,4 +1,4 @@
>-/**
>+/*
>  * \file drm_agpsupport.c
>  * DRM support for AGP/GART backend
>  *
>@@ -465,46 +465,3 @@
> 	dev->agp->acquired = 0;
> 	dev->agp->enabled = 0;
> }
>-
>-/**
>- * Binds a collection of pages into AGP memory at the given offset, returning
>- * the AGP memory structure containing them.
>- *
>- * No reference is held on the pages during this time -- it is up to the
>- * caller to handle that.
>- */
>-struct agp_memory *
>-drm_agp_bind_pages(struct drm_device *dev,
>-		   struct page **pages,
>-		   unsigned long num_pages,
>-		   uint32_t gtt_offset,
>-		   u32 type)
>-{
>-	struct agp_memory *mem;
>-	int ret, i;
>-
>-	DRM_DEBUG("\n");
>-
>-	mem = agp_allocate_memory(dev->agp->bridge, num_pages,
>-				      type);
>-	if (mem == NULL) {
>-		DRM_ERROR("Failed to allocate memory for %ld pages\n",
>-			  num_pages);
>-		return NULL;
>-	}
>-
>-	for (i = 0; i < num_pages; i++)
>-		mem->pages[i] = pages[i];
>-	mem->page_count = num_pages;
>-
>-	mem->is_flushed = true;
>-	ret = agp_bind_memory(mem, gtt_offset / PAGE_SIZE);
>-	if (ret != 0) {
>-		DRM_ERROR("Failed to bind AGP memory: %d\n", ret);
>-		agp_free_memory(mem);
>-		return NULL;
>-	}
>-
>-	return mem;
>-}
>-EXPORT_SYMBOL(drm_agp_bind_pages);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_atomic_uapi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_atomic_uapi.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_atomic_uapi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_atomic_uapi.c	2019-08-31 15:01:11.943736176 -0500
>@@ -747,6 +747,8 @@
> 			return -EINVAL;
> 		}
> 		state->content_protection = val;
>+	} else if (property == config->hdcp_content_type_property) {
>+		state->hdcp_content_type = val;
> 	} else if (property == connector->colorspace_property) {
> 		state->colorspace = val;
> 	} else if (property == config->writeback_fb_id_property) {
>@@ -831,6 +833,8 @@
> 			state->hdr_output_metadata->base.id : 0;
> 	} else if (property == config->content_protection_property) {
> 		*val = state->content_protection;
>+	} else if (property == config->hdcp_content_type_property) {
>+		*val = state->hdcp_content_type;
> 	} else if (property == config->writeback_fb_id_property) {
> 		/* Writeback framebuffer is one-shot, write and forget */
> 		*val = 0;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_client.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_client.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_client.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_client.c	2019-08-31 15:01:11.943736176 -0500
>@@ -59,7 +59,6 @@
> 
> 	drm_file_free(client->file);
> }
>-EXPORT_SYMBOL(drm_client_close);
> 
> /**
>  * drm_client_init - Initialise a DRM client
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_connector.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_connector.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_connector.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_connector.c	2019-08-31 15:01:11.944736176 -0500
>@@ -92,6 +92,7 @@
> 	{ DRM_MODE_CONNECTOR_DSI, "DSI" },
> 	{ DRM_MODE_CONNECTOR_DPI, "DPI" },
> 	{ DRM_MODE_CONNECTOR_WRITEBACK, "Writeback" },
>+	{ DRM_MODE_CONNECTOR_SPI, "SPI" },
> };
> 
> void drm_connector_ida_init(void)
>@@ -140,8 +141,7 @@
> 	}
> 
> 	DRM_DEBUG_KMS("cmdline mode for connector %s %s %dx%d@%dHz%s%s%s\n",
>-		      connector->name,
>-		      mode->name,
>+		      connector->name, mode->name,
> 		      mode->xres, mode->yres,
> 		      mode->refresh_specified ? mode->refresh : 60,
> 		      mode->rb ? " reduced blanking" : "",
>@@ -298,6 +298,41 @@
> EXPORT_SYMBOL(drm_connector_init);
> 
> /**
>+ * drm_connector_init_with_ddc - Init a preallocated connector
>+ * @dev: DRM device
>+ * @connector: the connector to init
>+ * @funcs: callbacks for this connector
>+ * @connector_type: user visible type of the connector
>+ * @ddc: pointer to the associated ddc adapter
>+ *
>+ * Initialises a preallocated connector. Connectors should be
>+ * subclassed as part of driver connector objects.
>+ *
>+ * Ensures that the ddc field of the connector is correctly set.
>+ *
>+ * Returns:
>+ * Zero on success, error code on failure.
>+ */
>+int drm_connector_init_with_ddc(struct drm_device *dev,
>+				struct drm_connector *connector,
>+				const struct drm_connector_funcs *funcs,
>+				int connector_type,
>+				struct i2c_adapter *ddc)
>+{
>+	int ret;
>+
>+	ret = drm_connector_init(dev, connector, funcs, connector_type);
>+	if (ret)
>+		return ret;
>+
>+	/* provide ddc symlink in sysfs */
>+	connector->ddc = ddc;
>+
>+	return ret;
>+}
>+EXPORT_SYMBOL(drm_connector_init_with_ddc);
>+
>+/**
>  * drm_connector_attach_edid_property - attach edid property.
>  * @connector: the connector
>  *
>@@ -948,10 +983,70 @@
>  *	- If the state is DESIRED, kernel should attempt to re-authenticate the
>  *	  link whenever possible. This includes across disable/enable, dpms,
>  *	  hotplug, downstream device changes, link status failures, etc..
>- *	- Userspace is responsible for polling the property to determine when
>- *	  the value transitions from ENABLED to DESIRED. This signifies the link
>- *	  is no longer protected and userspace should take appropriate action
>- *	  (whatever that might be).
>+ *	- Kernel sends uevent with the connector id and property id through
>+ *	  @drm_hdcp_update_content_protection, upon below kernel triggered
>+ *	  scenarios:
>+ *		DESIRED -> ENABLED	(authentication success)
>+ *		ENABLED -> DESIRED	(termination of authentication)
>+ *	- Please note no uevents for userspace triggered property state changes,
>+ *	  which can't fail such as
>+ *		DESIRED/ENABLED -> UNDESIRED
>+ *		UNDESIRED -> DESIRED
>+ *	- Userspace is responsible for polling the property or listen to uevents
>+ *	  to determine when the value transitions from ENABLED to DESIRED.
>+ *	  This signifies the link is no longer protected and userspace should
>+ *	  take appropriate action (whatever that might be).
>+ *
>+ * HDCP Content Type:
>+ *	This Enum property is used by the userspace to declare the content type
>+ *	of the display stream, to kernel. Here display stream stands for any
>+ *	display content that userspace intended to display through HDCP
>+ *	encryption.
>+ *
>+ *	Content Type of a stream is decided by the owner of the stream, as
>+ *	"HDCP Type0" or "HDCP Type1".
>+ *
>+ *	The value of the property can be one of the below:
>+ *	  - "HDCP Type0": DRM_MODE_HDCP_CONTENT_TYPE0 = 0
>+ *	  - "HDCP Type1": DRM_MODE_HDCP_CONTENT_TYPE1 = 1
>+ *
>+ *	When kernel starts the HDCP authentication (see "Content Protection"
>+ *	for details), it uses the content type in "HDCP Content Type"
>+ *	for performing the HDCP authentication with the display sink.
>+ *
>+ *	Please note in HDCP spec versions, a link can be authenticated with
>+ *	HDCP 2.2 for Content Type 0/Content Type 1. Where as a link can be
>+ *	authenticated with HDCP1.4 only for Content Type 0(though it is implicit
>+ *	in nature. As there is no reference for Content Type in HDCP1.4).
>+ *
>+ *	HDCP2.2 authentication protocol itself takes the "Content Type" as a
>+ *	parameter, which is a input for the DP HDCP2.2 encryption algo.
>+ *
>+ *	In case of Type 0 content protection request, kernel driver can choose
>+ *	either of HDCP spec versions 1.4 and 2.2. When HDCP2.2 is used for
>+ *	"HDCP Type 0", a HDCP 2.2 capable repeater in the downstream can send
>+ *	that content to a HDCP 1.4 authenticated HDCP sink (Type0 link).
>+ *	But if the content is classified as "HDCP Type 1", above mentioned
>+ *	HDCP 2.2 repeater wont send the content to the HDCP sink as it can't
>+ *	authenticate the HDCP1.4 capable sink for "HDCP Type 1".
>+ *
>+ *	Please note userspace can be ignorant of the HDCP versions used by the
>+ *	kernel driver to achieve the "HDCP Content Type".
>+ *
>+ *	At current scenario, classifying a content as Type 1 ensures that the
>+ *	content will be displayed only through the HDCP2.2 encrypted link.
>+ *
>+ *	Note that the HDCP Content Type property is introduced at HDCP 2.2, and
>+ *	defaults to type 0. It is only exposed by drivers supporting HDCP 2.2
>+ *	(hence supporting Type 0 and Type 1). Based on how next versions of
>+ *	HDCP specs are defined content Type could be used for higher versions
>+ *	too.
>+ *
>+ *	If content type is changed when "Content Protection" is not UNDESIRED,
>+ *	then kernel will disable the HDCP and re-enable with new type in the
>+ *	same atomic commit. And when "Content Protection" is ENABLED, it means
>+ *	that link is HDCP authenticated and encrypted, for the transmission of
>+ *	the Type of stream mentioned at "HDCP Content Type".
>  *
>  * HDR_OUTPUT_METADATA:
>  *	Connector property to enable userspace to send HDR Metadata to
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_debugfs_crc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_debugfs_crc.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_debugfs_crc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_debugfs_crc.c	2019-08-31 15:01:11.944736176 -0500
>@@ -66,9 +66,18 @@
>  * the reported CRCs of frames that should have the same contents.
>  *
>  * On the driver side the implementation effort is minimal, drivers only need to
>- * implement &drm_crtc_funcs.set_crc_source. The debugfs files are automatically
>- * set up if that vfunc is set. CRC samples need to be captured in the driver by
>- * calling drm_crtc_add_crc_entry().
>+ * implement &drm_crtc_funcs.set_crc_source and &drm_crtc_funcs.verify_crc_source.
>+ * The debugfs files are automatically set up if those vfuncs are set. CRC samples
>+ * need to be captured in the driver by calling drm_crtc_add_crc_entry().
>+ * Depending on the driver and HW requirements, &drm_crtc_funcs.set_crc_source
>+ * may result in a commit (even a full modeset).
>+ *
>+ * CRC results must be reliable across non-full-modeset atomic commits, so if a
>+ * commit via DRM_IOCTL_MODE_ATOMIC would disable or otherwise interfere with
>+ * CRC generation, then the driver must mark that commit as a full modeset
>+ * (drm_atomic_crtc_needs_modeset() should return true). As a result, to ensure
>+ * consistent results, generic userspace must re-setup CRC generation after a
>+ * legacy SETCRTC or an atomic commit with DRM_MODE_ATOMIC_ALLOW_MODESET.
>  */
> 
> static int crc_control_show(struct seq_file *m, void *data)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_dma.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_dma.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_dma.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_dma.c	2019-08-31 15:01:11.944736176 -0500
>@@ -1,4 +1,4 @@
>-/**
>+/*
>  * \file drm_dma.c
>  * DMA IOCTL and function support
>  *
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_dp_aux_dev.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_dp_aux_dev.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_dp_aux_dev.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_dp_aux_dev.c	2019-08-31 15:01:11.944736176 -0500
>@@ -37,6 +37,7 @@
> 
> #include <drm/drm_crtc.h>
> #include <drm/drm_dp_helper.h>
>+#include <drm/drm_dp_mst_helper.h>
> #include <drm/drm_print.h>
> 
> #include "drm_crtc_helper_internal.h"
>@@ -82,8 +83,7 @@
> 	kref_init(&aux_dev->refcount);
> 
> 	mutex_lock(&aux_idr_mutex);
>-	index = idr_alloc_cyclic(&aux_idr, aux_dev, 0, DRM_AUX_MINORS,
>-				 GFP_KERNEL);
>+	index = idr_alloc(&aux_idr, aux_dev, 0, DRM_AUX_MINORS, GFP_KERNEL);
> 	mutex_unlock(&aux_idr_mutex);
> 	if (index < 0) {
> 		kfree(aux_dev);
>@@ -163,7 +163,12 @@
> 			break;
> 		}
> 
>-		res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
>+		if (aux_dev->aux->is_remote)
>+			res = drm_dp_mst_dpcd_read(aux_dev->aux, pos, buf,
>+						   todo);
>+		else
>+			res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
>+
> 		if (res <= 0)
> 			break;
> 
>@@ -210,7 +215,12 @@
> 			break;
> 		}
> 
>-		res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
>+		if (aux_dev->aux->is_remote)
>+			res = drm_dp_mst_dpcd_write(aux_dev->aux, pos, buf,
>+						    todo);
>+		else
>+			res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
>+
> 		if (res <= 0)
> 			break;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_dp_helper.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_dp_helper.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_dp_helper.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_dp_helper.c	2019-08-31 15:01:11.944736176 -0500
>@@ -152,38 +152,15 @@
> 
> u8 drm_dp_link_rate_to_bw_code(int link_rate)
> {
>-	switch (link_rate) {
>-	default:
>-		WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
>-		     DP_LINK_BW_1_62);
>-		/* fall through */
>-	case 162000:
>-		return DP_LINK_BW_1_62;
>-	case 270000:
>-		return DP_LINK_BW_2_7;
>-	case 540000:
>-		return DP_LINK_BW_5_4;
>-	case 810000:
>-		return DP_LINK_BW_8_1;
>-	}
>+	/* Spec says link_bw = link_rate / 0.27Gbps */
>+	return link_rate / 27000;
> }
> EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
> 
> int drm_dp_bw_code_to_link_rate(u8 link_bw)
> {
>-	switch (link_bw) {
>-	default:
>-		WARN(1, "unknown DP link BW code %x, using 162000\n", link_bw);
>-		/* fall through */
>-	case DP_LINK_BW_1_62:
>-		return 162000;
>-	case DP_LINK_BW_2_7:
>-		return 270000;
>-	case DP_LINK_BW_5_4:
>-		return 540000;
>-	case DP_LINK_BW_8_1:
>-		return 810000;
>-	}
>+	/* Spec says link_rate = link_bw * 0.27Gbps */
>+	return link_bw * 27000;
> }
> EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_dp_mst_topology.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_dp_mst_topology.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_dp_mst_topology.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_dp_mst_topology.c	2019-08-31 15:01:11.944736176 -0500
>@@ -36,6 +36,8 @@
> #include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
> 
>+#include "drm_crtc_helper_internal.h"
>+
> /**
>  * DOC: dp mst helper
>  *
>@@ -53,6 +55,9 @@
> 				     int id,
> 				     struct drm_dp_payload *payload);
> 
>+static int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr,
>+				 struct drm_dp_mst_port *port,
>+				 int offset, int size, u8 *bytes);
> static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr,
> 				  struct drm_dp_mst_port *port,
> 				  int offset, int size, u8 *bytes);
>@@ -1483,6 +1488,52 @@
> 	return send_link;
> }
> 
>+/**
>+ * drm_dp_mst_dpcd_read() - read a series of bytes from the DPCD via sideband
>+ * @aux: Fake sideband AUX CH
>+ * @offset: address of the (first) register to read
>+ * @buffer: buffer to store the register values
>+ * @size: number of bytes in @buffer
>+ *
>+ * Performs the same functionality for remote devices via
>+ * sideband messaging as drm_dp_dpcd_read() does for local
>+ * devices via actual AUX CH.
>+ *
>+ * Return: Number of bytes read, or negative error code on failure.
>+ */
>+ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
>+			     unsigned int offset, void *buffer, size_t size)
>+{
>+	struct drm_dp_mst_port *port = container_of(aux, struct drm_dp_mst_port,
>+						    aux);
>+
>+	return drm_dp_send_dpcd_read(port->mgr, port,
>+				     offset, size, buffer);
>+}
>+
>+/**
>+ * drm_dp_mst_dpcd_write() - write a series of bytes to the DPCD via sideband
>+ * @aux: Fake sideband AUX CH
>+ * @offset: address of the (first) register to write
>+ * @buffer: buffer containing the values to write
>+ * @size: number of bytes in @buffer
>+ *
>+ * Performs the same functionality for remote devices via
>+ * sideband messaging as drm_dp_dpcd_write() does for local
>+ * devices via actual AUX CH.
>+ *
>+ * Return: 0 on success, negative error code on failure.
>+ */
>+ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
>+			      unsigned int offset, void *buffer, size_t size)
>+{
>+	struct drm_dp_mst_port *port = container_of(aux, struct drm_dp_mst_port,
>+						    aux);
>+
>+	return drm_dp_send_dpcd_write(port->mgr, port,
>+				      offset, size, buffer);
>+}
>+
> static void drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, u8 *guid)
> {
> 	int ret;
>@@ -1526,6 +1577,46 @@
> 	strlcat(proppath, temp, proppath_size);
> }
> 
>+/**
>+ * drm_dp_mst_connector_late_register() - Late MST connector registration
>+ * @connector: The MST connector
>+ * @port: The MST port for this connector
>+ *
>+ * Helper to register the remote aux device for this MST port. Drivers should
>+ * call this from their mst connector's late_register hook to enable MST aux
>+ * devices.
>+ *
>+ * Return: 0 on success, negative error code on failure.
>+ */
>+int drm_dp_mst_connector_late_register(struct drm_connector *connector,
>+				       struct drm_dp_mst_port *port)
>+{
>+	DRM_DEBUG_KMS("registering %s remote bus for %s\n",
>+		      port->aux.name, connector->kdev->kobj.name);
>+
>+	port->aux.dev = connector->kdev;
>+	return drm_dp_aux_register_devnode(&port->aux);
>+}
>+EXPORT_SYMBOL(drm_dp_mst_connector_late_register);
>+
>+/**
>+ * drm_dp_mst_connector_early_unregister() - Early MST connector unregistration
>+ * @connector: The MST connector
>+ * @port: The MST port for this connector
>+ *
>+ * Helper to unregister the remote aux device for this MST port, registered by
>+ * drm_dp_mst_connector_late_register(). Drivers should call this from their mst
>+ * connector's early_unregister hook.
>+ */
>+void drm_dp_mst_connector_early_unregister(struct drm_connector *connector,
>+					   struct drm_dp_mst_port *port)
>+{
>+	DRM_DEBUG_KMS("unregistering %s remote bus for %s\n",
>+		      port->aux.name, connector->kdev->kobj.name);
>+	drm_dp_aux_unregister_devnode(&port->aux);
>+}
>+EXPORT_SYMBOL(drm_dp_mst_connector_early_unregister);
>+
> static void drm_dp_add_port(struct drm_dp_mst_branch *mstb,
> 			    struct drm_device *dev,
> 			    struct drm_dp_link_addr_reply_port *port_msg)
>@@ -1548,6 +1639,7 @@
> 		port->mgr = mstb->mgr;
> 		port->aux.name = "DPMST";
> 		port->aux.dev = dev->dev;
>+		port->aux.is_remote = true;
> 
> 		/*
> 		 * Make sure the memory allocation for our parent branch stays
>@@ -1816,7 +1908,6 @@
> 	return false;
> }
> 
>-#if 0
> static int build_dpcd_read(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 offset, u8 num_bytes)
> {
> 	struct drm_dp_sideband_msg_req_body req;
>@@ -1829,7 +1920,6 @@
> 
> 	return 0;
> }
>-#endif
> 
> static int drm_dp_send_sideband_msg(struct drm_dp_mst_topology_mgr *mgr,
> 				    bool up, u8 *msg, int len)
>@@ -2441,26 +2531,58 @@
> }
> EXPORT_SYMBOL(drm_dp_update_payload_part2);
> 
>-#if 0 /* unused as of yet */
> static int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr,
> 				 struct drm_dp_mst_port *port,
>-				 int offset, int size)
>+				 int offset, int size, u8 *bytes)
> {
> 	int len;
>+	int ret = 0;
> 	struct drm_dp_sideband_msg_tx *txmsg;
>+	struct drm_dp_mst_branch *mstb;
>+
>+	mstb = drm_dp_mst_topology_get_mstb_validated(mgr, port->parent);
>+	if (!mstb)
>+		return -EINVAL;
> 
> 	txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
>-	if (!txmsg)
>-		return -ENOMEM;
>+	if (!txmsg) {
>+		ret = -ENOMEM;
>+		goto fail_put;
>+	}
> 
>-	len = build_dpcd_read(txmsg, port->port_num, 0, 8);
>+	len = build_dpcd_read(txmsg, port->port_num, offset, size);
> 	txmsg->dst = port->parent;
> 
> 	drm_dp_queue_down_tx(mgr, txmsg);
> 
>-	return 0;
>+	ret = drm_dp_mst_wait_tx_reply(mstb, txmsg);
>+	if (ret < 0)
>+		goto fail_free;
>+
>+	/* DPCD read should never be NACKed */
>+	if (txmsg->reply.reply_type == 1) {
>+		DRM_ERROR("mstb %p port %d: DPCD read on addr 0x%x for %d bytes NAKed\n",
>+			  mstb, port->port_num, offset, size);
>+		ret = -EIO;
>+		goto fail_free;
>+	}
>+
>+	if (txmsg->reply.u.remote_dpcd_read_ack.num_bytes != size) {
>+		ret = -EPROTO;
>+		goto fail_free;
>+	}
>+
>+	ret = min_t(size_t, txmsg->reply.u.remote_dpcd_read_ack.num_bytes,
>+		    size);
>+	memcpy(bytes, txmsg->reply.u.remote_dpcd_read_ack.bytes, ret);
>+
>+fail_free:
>+	kfree(txmsg);
>+fail_put:
>+	drm_dp_mst_topology_put_mstb(mstb);
>+
>+	return ret;
> }
>-#endif
> 
> static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr,
> 				  struct drm_dp_mst_port *port,
>@@ -2489,7 +2611,7 @@
> 	ret = drm_dp_mst_wait_tx_reply(mstb, txmsg);
> 	if (ret > 0) {
> 		if (txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK)
>-			ret = -EINVAL;
>+			ret = -EIO;
> 		else
> 			ret = 0;
> 	}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_drv.c	2019-08-31 15:01:11.945736176 -0500
>@@ -978,14 +978,14 @@
> 	if (ret)
> 		goto err_minors;
> 
>-	dev->registered = true;
>-
> 	if (dev->driver->load) {
> 		ret = dev->driver->load(dev, flags);
> 		if (ret)
> 			goto err_minors;
> 	}
> 
>+	dev->registered = true;
>+
> 	if (drm_core_check_feature(dev, DRIVER_MODESET))
> 		drm_modeset_register_all(dev);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_file.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_file.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_file.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_file.c	2019-08-31 15:01:11.945736176 -0500
>@@ -147,8 +147,7 @@
> 	if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
> 		drm_syncobj_open(file);
> 
>-	if (drm_core_check_feature(dev, DRIVER_PRIME))
>-		drm_prime_init_file_private(&file->prime);
>+	drm_prime_init_file_private(&file->prime);
> 
> 	if (dev->driver->open) {
> 		ret = dev->driver->open(dev, file);
>@@ -159,8 +158,7 @@
> 	return file;
> 
> out_prime_destroy:
>-	if (drm_core_check_feature(dev, DRIVER_PRIME))
>-		drm_prime_destroy_file_private(&file->prime);
>+	drm_prime_destroy_file_private(&file->prime);
> 	if (drm_core_check_feature(dev, DRIVER_SYNCOBJ))
> 		drm_syncobj_release(file);
> 	if (drm_core_check_feature(dev, DRIVER_GEM))
>@@ -253,8 +251,7 @@
> 	if (dev->driver->postclose)
> 		dev->driver->postclose(dev, file);
> 
>-	if (drm_core_check_feature(dev, DRIVER_PRIME))
>-		drm_prime_destroy_file_private(&file->prime);
>+	drm_prime_destroy_file_private(&file->prime);
> 
> 	WARN_ON(!list_empty(&file->event_list));
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_gem.c	2019-08-31 15:01:11.945736176 -0500
>@@ -39,6 +39,7 @@
> #include <linux/mem_encrypt.h>
> #include <linux/pagevec.h>
> 
>+#include <drm/drm.h>
> #include <drm/drm_device.h>
> #include <drm/drm_drv.h>
> #include <drm/drm_file.h>
>@@ -254,8 +255,7 @@
> 	else if (dev->driver->gem_close_object)
> 		dev->driver->gem_close_object(obj, file_priv);
> 
>-	if (drm_core_check_feature(dev, DRIVER_PRIME))
>-		drm_gem_remove_prime_handles(obj, file_priv);
>+	drm_gem_remove_prime_handles(obj, file_priv);
> 	drm_vma_node_revoke(&obj->vma_node, file_priv);
> 
> 	drm_gem_object_handle_put_unlocked(obj);
>@@ -1288,8 +1288,8 @@
> 	if (contended != -1) {
> 		struct drm_gem_object *obj = objs[contended];
> 
>-		ret = ww_mutex_lock_slow_interruptible(&obj->resv->lock,
>-						       acquire_ctx);
>+		ret = reservation_object_lock_slow_interruptible(obj->resv,
>+								 acquire_ctx);
> 		if (ret) {
> 			ww_acquire_done(acquire_ctx);
> 			return ret;
>@@ -1300,16 +1300,16 @@
> 		if (i == contended)
> 			continue;
> 
>-		ret = ww_mutex_lock_interruptible(&objs[i]->resv->lock,
>-						  acquire_ctx);
>+		ret = reservation_object_lock_interruptible(objs[i]->resv,
>+							    acquire_ctx);
> 		if (ret) {
> 			int j;
> 
> 			for (j = 0; j < i; j++)
>-				ww_mutex_unlock(&objs[j]->resv->lock);
>+				reservation_object_unlock(objs[j]->resv);
> 
> 			if (contended != -1 && contended >= i)
>-				ww_mutex_unlock(&objs[contended]->resv->lock);
>+				reservation_object_unlock(objs[contended]->resv);
> 
> 			if (ret == -EDEADLK) {
> 				contended = i;
>@@ -1334,7 +1334,7 @@
> 	int i;
> 
> 	for (i = 0; i < count; i++)
>-		ww_mutex_unlock(&objs[i]->resv->lock);
>+		reservation_object_unlock(objs[i]->resv);
> 
> 	ww_acquire_fini(acquire_ctx);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_gem_framebuffer_helper.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_gem_framebuffer_helper.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_gem_framebuffer_helper.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_gem_framebuffer_helper.c	2019-08-31 15:01:11.945736176 -0500
>@@ -271,11 +271,11 @@
>  * @plane: Plane
>  * @state: Plane state the fence will be attached to
>  *
>- * This function prepares a GEM backed framebuffer for scanout by checking if
>- * the plane framebuffer has a DMA-BUF attached. If it does, it extracts the
>- * exclusive fence and attaches it to the plane state for the atomic helper to
>- * wait on. This function can be used as the &drm_plane_helper_funcs.prepare_fb
>- * callback.
>+ * This function extracts the exclusive fence from &drm_gem_object.resv and
>+ * attaches it to plane state for the atomic helper to wait on. This is
>+ * necessary to correctly implement implicit synchronization for any buffers
>+ * shared as a struct &dma_buf. This function can be used as the
>+ * &drm_plane_helper_funcs.prepare_fb callback.
>  *
>  * There is no need for &drm_plane_helper_funcs.cleanup_fb hook for simple
>  * gem based framebuffer drivers which have their buffers always pinned in
>@@ -287,17 +287,15 @@
> int drm_gem_fb_prepare_fb(struct drm_plane *plane,
> 			  struct drm_plane_state *state)
> {
>-	struct dma_buf *dma_buf;
>+	struct drm_gem_object *obj;
> 	struct dma_fence *fence;
> 
> 	if (!state->fb)
> 		return 0;
> 
>-	dma_buf = drm_gem_fb_get_obj(state->fb, 0)->dma_buf;
>-	if (dma_buf) {
>-		fence = reservation_object_get_excl_rcu(dma_buf->resv);
>-		drm_atomic_set_fence_for_plane(state, fence);
>-	}
>+	obj = drm_gem_fb_get_obj(state->fb, 0);
>+	fence = reservation_object_get_excl_rcu(obj->resv);
>+	drm_atomic_set_fence_for_plane(state, fence);
> 
> 	return 0;
> }
>@@ -309,10 +307,11 @@
>  * @pipe: Simple display pipe
>  * @plane_state: Plane state
>  *
>- * This function uses drm_gem_fb_prepare_fb() to check if the plane FB has a
>- * &dma_buf attached, extracts the exclusive fence and attaches it to plane
>- * state for the atomic helper to wait on. Drivers can use this as their
>- * &drm_simple_display_pipe_funcs.prepare_fb callback.
>+ * This function uses drm_gem_fb_prepare_fb() to extract the exclusive fence
>+ * from &drm_gem_object.resv and attaches it to plane state for the atomic
>+ * helper to wait on. This is necessary to correctly implement implicit
>+ * synchronization for any buffers shared as a struct &dma_buf. Drivers can use
>+ * this as their &drm_simple_display_pipe_funcs.prepare_fb callback.
>  *
>  * See drm_atomic_set_fence_for_plane() for a discussion of implicit and
>  * explicit fencing in atomic modeset updates.
>@@ -323,46 +322,3 @@
> 	return drm_gem_fb_prepare_fb(&pipe->plane, plane_state);
> }
> EXPORT_SYMBOL(drm_gem_fb_simple_display_pipe_prepare_fb);
>-
>-/**
>- * drm_gem_fbdev_fb_create - Create a GEM backed &drm_framebuffer for fbdev
>- *                           emulation
>- * @dev: DRM device
>- * @sizes: fbdev size description
>- * @pitch_align: Optional pitch alignment
>- * @obj: GEM object backing the framebuffer
>- * @funcs: Optional vtable to be used for the new framebuffer object when the
>- *         dirty callback is needed.
>- *
>- * This function creates a framebuffer from a &drm_fb_helper_surface_size
>- * description for use in the &drm_fb_helper_funcs.fb_probe callback.
>- *
>- * Returns:
>- * Pointer to a &drm_framebuffer on success or an error pointer on failure.
>- */
>-struct drm_framebuffer *
>-drm_gem_fbdev_fb_create(struct drm_device *dev,
>-			struct drm_fb_helper_surface_size *sizes,
>-			unsigned int pitch_align, struct drm_gem_object *obj,
>-			const struct drm_framebuffer_funcs *funcs)
>-{
>-	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
>-
>-	mode_cmd.width = sizes->surface_width;
>-	mode_cmd.height = sizes->surface_height;
>-	mode_cmd.pitches[0] = sizes->surface_width *
>-			      DIV_ROUND_UP(sizes->surface_bpp, 8);
>-	if (pitch_align)
>-		mode_cmd.pitches[0] = roundup(mode_cmd.pitches[0],
>-					      pitch_align);
>-	mode_cmd.pixel_format = drm_driver_legacy_fb_format(dev, sizes->surface_bpp,
>-							    sizes->surface_depth);
>-	if (obj->size < mode_cmd.pitches[0] * mode_cmd.height)
>-		return ERR_PTR(-EINVAL);
>-
>-	if (!funcs)
>-		funcs = &drm_gem_fb_funcs;
>-
>-	return drm_gem_fb_alloc(dev, &mode_cmd, &obj, 1, funcs);
>-}
>-EXPORT_SYMBOL(drm_gem_fbdev_fb_create);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_gem_shmem_helper.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_gem_shmem_helper.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_gem_shmem_helper.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_gem_shmem_helper.c	2019-08-31 15:01:11.945736176 -0500
>@@ -10,6 +10,7 @@
> #include <linux/slab.h>
> #include <linux/vmalloc.h>
> 
>+#include <drm/drm.h>
> #include <drm/drm_device.h>
> #include <drm/drm_drv.h>
> #include <drm/drm_gem_shmem_helper.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_gem_vram_helper.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_gem_vram_helper.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_gem_vram_helper.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_gem_vram_helper.c	2019-08-31 15:01:11.945736176 -0500
>@@ -7,6 +7,8 @@
> #include <drm/drm_vram_mm_helper.h>
> #include <drm/ttm/ttm_page_alloc.h>
> 
>+static const struct drm_gem_object_funcs drm_gem_vram_object_funcs;
>+
> /**
>  * DOC: overview
>  *
>@@ -24,7 +26,7 @@
> 	 * TTM buffer object in 'bo' has already been cleaned
> 	 * up; only release the GEM object.
> 	 */
>-	drm_gem_object_release(&gbo->gem);
>+	drm_gem_object_release(&gbo->bo.base);
> }
> 
> static void drm_gem_vram_destroy(struct drm_gem_vram_object *gbo)
>@@ -80,7 +82,10 @@
> 	int ret;
> 	size_t acc_size;
> 
>-	ret = drm_gem_object_init(dev, &gbo->gem, size);
>+	if (!gbo->bo.base.funcs)
>+		gbo->bo.base.funcs = &drm_gem_vram_object_funcs;
>+
>+	ret = drm_gem_object_init(dev, &gbo->bo.base, size);
> 	if (ret)
> 		return ret;
> 
>@@ -98,7 +103,7 @@
> 	return 0;
> 
> err_drm_gem_object_release:
>-	drm_gem_object_release(&gbo->gem);
>+	drm_gem_object_release(&gbo->bo.base);
> 	return ret;
> }
> 
>@@ -163,7 +168,7 @@
>  */
> u64 drm_gem_vram_mmap_offset(struct drm_gem_vram_object *gbo)
> {
>-	return drm_vma_node_offset_addr(&gbo->bo.vma_node);
>+	return drm_vma_node_offset_addr(&gbo->bo.base.vma_node);
> }
> EXPORT_SYMBOL(drm_gem_vram_mmap_offset);
> 
>@@ -378,11 +383,11 @@
> 	if (IS_ERR(gbo))
> 		return PTR_ERR(gbo);
> 
>-	ret = drm_gem_handle_create(file, &gbo->gem, &handle);
>+	ret = drm_gem_handle_create(file, &gbo->bo.base, &handle);
> 	if (ret)
> 		goto err_drm_gem_object_put_unlocked;
> 
>-	drm_gem_object_put_unlocked(&gbo->gem);
>+	drm_gem_object_put_unlocked(&gbo->bo.base);
> 
> 	args->pitch = pitch;
> 	args->size = size;
>@@ -391,7 +396,7 @@
> 	return 0;
> 
> err_drm_gem_object_put_unlocked:
>-	drm_gem_object_put_unlocked(&gbo->gem);
>+	drm_gem_object_put_unlocked(&gbo->bo.base);
> 	return ret;
> }
> EXPORT_SYMBOL(drm_gem_vram_fill_create_dumb);
>@@ -441,7 +446,7 @@
> {
> 	struct drm_gem_vram_object *gbo = drm_gem_vram_of_bo(bo);
> 
>-	return drm_vma_node_verify_access(&gbo->gem.vma_node,
>+	return drm_vma_node_verify_access(&gbo->bo.base.vma_node,
> 					  filp->private_data);
> }
> EXPORT_SYMBOL(drm_gem_vram_bo_driver_verify_access);
>@@ -460,21 +465,24 @@
> EXPORT_SYMBOL(drm_gem_vram_mm_funcs);
> 
> /*
>- * Helpers for struct drm_driver
>+ * Helpers for struct drm_gem_object_funcs
>  */
> 
> /**
>- * drm_gem_vram_driver_gem_free_object_unlocked() - \
>-	Implements &struct drm_driver.gem_free_object_unlocked
>- * @gem:	GEM object. Refers to &struct drm_gem_vram_object.gem
>+ * drm_gem_vram_object_free() - \
>+	Implements &struct drm_gem_object_funcs.free
>+ * @gem:       GEM object. Refers to &struct drm_gem_vram_object.gem
>  */
>-void drm_gem_vram_driver_gem_free_object_unlocked(struct drm_gem_object *gem)
>+static void drm_gem_vram_object_free(struct drm_gem_object *gem)
> {
> 	struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(gem);
> 
> 	drm_gem_vram_put(gbo);
> }
>-EXPORT_SYMBOL(drm_gem_vram_driver_gem_free_object_unlocked);
>+
>+/*
>+ * Helpers for dump buffers
>+ */
> 
> /**
>  * drm_gem_vram_driver_create_dumb() - \
>@@ -536,19 +544,19 @@
> EXPORT_SYMBOL(drm_gem_vram_driver_dumb_mmap_offset);
> 
> /*
>- * PRIME helpers for struct drm_driver
>+ * PRIME helpers
>  */
> 
> /**
>- * drm_gem_vram_driver_gem_prime_pin() - \
>-	Implements &struct drm_driver.gem_prime_pin
>+ * drm_gem_vram_object_pin() - \
>+	Implements &struct drm_gem_object_funcs.pin
>  * @gem:	The GEM object to pin
>  *
>  * Returns:
>  * 0 on success, or
>  * a negative errno code otherwise.
>  */
>-int drm_gem_vram_driver_gem_prime_pin(struct drm_gem_object *gem)
>+static int drm_gem_vram_object_pin(struct drm_gem_object *gem)
> {
> 	struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(gem);
> 
>@@ -562,31 +570,29 @@
> 	 */
> 	return drm_gem_vram_pin(gbo, 0);
> }
>-EXPORT_SYMBOL(drm_gem_vram_driver_gem_prime_pin);
> 
> /**
>- * drm_gem_vram_driver_gem_prime_unpin() - \
>-	Implements &struct drm_driver.gem_prime_unpin
>+ * drm_gem_vram_object_unpin() - \
>+	Implements &struct drm_gem_object_funcs.unpin
>  * @gem:	The GEM object to unpin
>  */
>-void drm_gem_vram_driver_gem_prime_unpin(struct drm_gem_object *gem)
>+static void drm_gem_vram_object_unpin(struct drm_gem_object *gem)
> {
> 	struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(gem);
> 
> 	drm_gem_vram_unpin(gbo);
> }
>-EXPORT_SYMBOL(drm_gem_vram_driver_gem_prime_unpin);
> 
> /**
>- * drm_gem_vram_driver_gem_prime_vmap() - \
>-	Implements &struct drm_driver.gem_prime_vmap
>+ * drm_gem_vram_object_vmap() - \
>+	Implements &struct drm_gem_object_funcs.vmap
>  * @gem:	The GEM object to map
>  *
>  * Returns:
>  * The buffers virtual address on success, or
>  * NULL otherwise.
>  */
>-void *drm_gem_vram_driver_gem_prime_vmap(struct drm_gem_object *gem)
>+static void *drm_gem_vram_object_vmap(struct drm_gem_object *gem)
> {
> 	struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(gem);
> 	int ret;
>@@ -602,40 +608,30 @@
> 	}
> 	return base;
> }
>-EXPORT_SYMBOL(drm_gem_vram_driver_gem_prime_vmap);
> 
> /**
>- * drm_gem_vram_driver_gem_prime_vunmap() - \
>-	Implements &struct drm_driver.gem_prime_vunmap
>+ * drm_gem_vram_object_vunmap() - \
>+	Implements &struct drm_gem_object_funcs.vunmap
>  * @gem:	The GEM object to unmap
>  * @vaddr:	The mapping's base address
>  */
>-void drm_gem_vram_driver_gem_prime_vunmap(struct drm_gem_object *gem,
>-					  void *vaddr)
>+static void drm_gem_vram_object_vunmap(struct drm_gem_object *gem,
>+				       void *vaddr)
> {
> 	struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(gem);
> 
> 	drm_gem_vram_kunmap(gbo);
> 	drm_gem_vram_unpin(gbo);
> }
>-EXPORT_SYMBOL(drm_gem_vram_driver_gem_prime_vunmap);
> 
>-/**
>- * drm_gem_vram_driver_gem_prime_mmap() - \
>-	Implements &struct drm_driver.gem_prime_mmap
>- * @gem:	The GEM object to map
>- * @vma:	The VMA describing the mapping
>- *
>- * Returns:
>- * 0 on success, or
>- * a negative errno code otherwise.
>+/*
>+ * GEM object funcs
>  */
>-int drm_gem_vram_driver_gem_prime_mmap(struct drm_gem_object *gem,
>-				       struct vm_area_struct *vma)
>-{
>-	struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(gem);
> 
>-	gbo->gem.vma_node.vm_node.start = gbo->bo.vma_node.vm_node.start;
>-	return drm_gem_prime_mmap(gem, vma);
>-}
>-EXPORT_SYMBOL(drm_gem_vram_driver_gem_prime_mmap);
>+static const struct drm_gem_object_funcs drm_gem_vram_object_funcs = {
>+	.free	= drm_gem_vram_object_free,
>+	.pin	= drm_gem_vram_object_pin,
>+	.unpin	= drm_gem_vram_object_unpin,
>+	.vmap	= drm_gem_vram_object_vmap,
>+	.vunmap	= drm_gem_vram_object_vunmap
>+};
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_hdcp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_hdcp.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_hdcp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_hdcp.c	2019-08-31 15:01:11.945736176 -0500
>@@ -271,6 +271,13 @@
>  *
>  * SRM should be presented in the name of "display_hdcp_srm.bin".
>  *
>+ * Format of the SRM table, that userspace needs to write into the binary file,
>+ * is defined at:
>+ * 1. Renewability chapter on 55th page of HDCP 1.4 specification
>+ * https://www.digital-cp.com/sites/default/files/specifications/HDCP%20Specification%20Rev1_4_Secure.pdf
>+ * 2. Renewability chapter on 63rd page of HDCP 2.2 specification
>+ * https://www.digital-cp.com/sites/default/files/specifications/HDCP%20on%20HDMI%20Specification%20Rev2_2_Final1.pdf
>+ *
>  * Returns:
>  * TRUE on any of the KSV is revoked, else FALSE.
>  */
>@@ -344,23 +351,45 @@
> };
> DRM_ENUM_NAME_FN(drm_get_content_protection_name, drm_cp_enum_list)
> 
>+static struct drm_prop_enum_list drm_hdcp_content_type_enum_list[] = {
>+	{ DRM_MODE_HDCP_CONTENT_TYPE0, "HDCP Type0" },
>+	{ DRM_MODE_HDCP_CONTENT_TYPE1, "HDCP Type1" },
>+};
>+DRM_ENUM_NAME_FN(drm_get_hdcp_content_type_name,
>+		 drm_hdcp_content_type_enum_list)
>+
> /**
>  * drm_connector_attach_content_protection_property - attach content protection
>  * property
>  *
>  * @connector: connector to attach CP property on.
>+ * @hdcp_content_type: is HDCP Content Type property needed for connector
>  *
>  * This is used to add support for content protection on select connectors.
>  * Content Protection is intentionally vague to allow for different underlying
>  * technologies, however it is most implemented by HDCP.
>  *
>+ * When hdcp_content_type is true enum property called HDCP Content Type is
>+ * created (if it is not already) and attached to the connector.
>+ *
>+ * This property is used for sending the protected content's stream type
>+ * from userspace to kernel on selected connectors. Protected content provider
>+ * will decide their type of their content and declare the same to kernel.
>+ *
>+ * Content type will be used during the HDCP 2.2 authentication.
>+ * Content type will be set to &drm_connector_state.hdcp_content_type.
>+ *
>  * The content protection will be set to &drm_connector_state.content_protection
>  *
>+ * When kernel triggered content protection state change like DESIRED->ENABLED
>+ * and ENABLED->DESIRED, will use drm_hdcp_update_content_protection() to update
>+ * the content protection state of a connector.
>+ *
>  * Returns:
>  * Zero on success, negative errno on failure.
>  */
> int drm_connector_attach_content_protection_property(
>-		struct drm_connector *connector)
>+		struct drm_connector *connector, bool hdcp_content_type)
> {
> 	struct drm_device *dev = connector->dev;
> 	struct drm_property *prop =
>@@ -377,6 +406,52 @@
> 				   DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
> 	dev->mode_config.content_protection_property = prop;
> 
>+	if (!hdcp_content_type)
>+		return 0;
>+
>+	prop = dev->mode_config.hdcp_content_type_property;
>+	if (!prop)
>+		prop = drm_property_create_enum(dev, 0, "HDCP Content Type",
>+					drm_hdcp_content_type_enum_list,
>+					ARRAY_SIZE(
>+					drm_hdcp_content_type_enum_list));
>+	if (!prop)
>+		return -ENOMEM;
>+
>+	drm_object_attach_property(&connector->base, prop,
>+				   DRM_MODE_HDCP_CONTENT_TYPE0);
>+	dev->mode_config.hdcp_content_type_property = prop;
>+
> 	return 0;
> }
> EXPORT_SYMBOL(drm_connector_attach_content_protection_property);
>+
>+/**
>+ * drm_hdcp_update_content_protection - Updates the content protection state
>+ * of a connector
>+ *
>+ * @connector: drm_connector on which content protection state needs an update
>+ * @val: New state of the content protection property
>+ *
>+ * This function can be used by display drivers, to update the kernel triggered
>+ * content protection state changes of a drm_connector such as DESIRED->ENABLED
>+ * and ENABLED->DESIRED. No uevent for DESIRED->UNDESIRED or ENABLED->UNDESIRED,
>+ * as userspace is triggering such state change and kernel performs it without
>+ * fail.This function update the new state of the property into the connector's
>+ * state and generate an uevent to notify the userspace.
>+ */
>+void drm_hdcp_update_content_protection(struct drm_connector *connector,
>+					u64 val)
>+{
>+	struct drm_device *dev = connector->dev;
>+	struct drm_connector_state *state = connector->state;
>+
>+	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
>+	if (state->content_protection == val)
>+		return;
>+
>+	state->content_protection = val;
>+	drm_sysfs_connector_status_event(connector,
>+				 dev->mode_config.content_protection_property);
>+}
>+EXPORT_SYMBOL(drm_hdcp_update_content_protection);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_ioc32.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_ioc32.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_ioc32.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_ioc32.c	2019-08-31 15:01:11.945736176 -0500
>@@ -108,7 +108,7 @@
> 		.desc = compat_ptr(v32.desc),
> 	};
> 	err = drm_ioctl_kernel(file, drm_version, &v,
>-			       DRM_UNLOCKED|DRM_RENDER_ALLOW);
>+			       DRM_RENDER_ALLOW);
> 	if (err)
> 		return err;
> 
>@@ -142,7 +142,7 @@
> 		.unique = compat_ptr(uq32.unique),
> 	};
> 
>-	err = drm_ioctl_kernel(file, drm_getunique, &uq, DRM_UNLOCKED);
>+	err = drm_ioctl_kernel(file, drm_getunique, &uq, 0);
> 	if (err)
> 		return err;
> 
>@@ -181,7 +181,7 @@
> 		return -EFAULT;
> 
> 	map.offset = m32.offset;
>-	err = drm_ioctl_kernel(file, drm_legacy_getmap_ioctl, &map, DRM_UNLOCKED);
>+	err = drm_ioctl_kernel(file, drm_legacy_getmap_ioctl, &map, 0);
> 	if (err)
> 		return err;
> 
>@@ -267,7 +267,7 @@
> 
> 	client.idx = c32.idx;
> 
>-	err = drm_ioctl_kernel(file, drm_getclient, &client, DRM_UNLOCKED);
>+	err = drm_ioctl_kernel(file, drm_getclient, &client, 0);
> 	if (err)
> 		return err;
> 
>@@ -297,7 +297,7 @@
> 	drm_stats32_t __user *argp = (void __user *)arg;
> 	int err;
> 
>-	err = drm_ioctl_kernel(file, drm_noop, NULL, DRM_UNLOCKED);
>+	err = drm_ioctl_kernel(file, drm_noop, NULL, 0);
> 	if (err)
> 		return err;
> 
>@@ -895,8 +895,7 @@
> 			   sizeof(req64.modifier)))
> 		return -EFAULT;
> 
>-	err = drm_ioctl_kernel(file, drm_mode_addfb2, &req64,
>-			       DRM_UNLOCKED);
>+	err = drm_ioctl_kernel(file, drm_mode_addfb2, &req64, 0);
> 	if (err)
> 		return err;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_ioctl.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_ioctl.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_ioctl.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_ioctl.c	2019-08-31 15:01:11.945736176 -0500
>@@ -570,24 +570,23 @@
> 
> /* Ioctl table */
> static const struct drm_ioctl_desc drm_ioctls[] = {
>-	DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version,
>-		      DRM_UNLOCKED|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF(DRM_IOCTL_GET_UNIQUE, drm_getunique, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_GET_MAGIC, drm_getmagic, DRM_UNLOCKED),
>+	DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF(DRM_IOCTL_GET_UNIQUE, drm_getunique, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_GET_MAGIC, drm_getmagic, 0),
> 	DRM_IOCTL_DEF(DRM_IOCTL_IRQ_BUSID, drm_irq_by_busid, DRM_MASTER|DRM_ROOT_ONLY),
> 
>-	DRM_LEGACY_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_legacy_getmap_ioctl, DRM_UNLOCKED),
>+	DRM_LEGACY_IOCTL_DEF(DRM_IOCTL_GET_MAP, drm_legacy_getmap_ioctl, 0),
> 
>-	DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_GET_CAP, drm_getcap, DRM_UNLOCKED|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF(DRM_IOCTL_SET_CLIENT_CAP, drm_setclientcap, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_UNLOCKED | DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_GET_CLIENT, drm_getclient, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_GET_STATS, drm_getstats, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_GET_CAP, drm_getcap, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF(DRM_IOCTL_SET_CLIENT_CAP, drm_setclientcap, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER),
> 
> 	DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> 	DRM_IOCTL_DEF(DRM_IOCTL_BLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> 	DRM_IOCTL_DEF(DRM_IOCTL_UNBLOCK, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
>-	DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_UNLOCKED|DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_AUTH_MAGIC, drm_authmagic, DRM_MASTER),
> 
> 	DRM_LEGACY_IOCTL_DEF(DRM_IOCTL_ADD_MAP, drm_legacy_addmap_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> 	DRM_LEGACY_IOCTL_DEF(DRM_IOCTL_RM_MAP, drm_legacy_rmmap_ioctl, DRM_AUTH),
>@@ -595,8 +594,8 @@
> 	DRM_LEGACY_IOCTL_DEF(DRM_IOCTL_SET_SAREA_CTX, drm_legacy_setsareactx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> 	DRM_LEGACY_IOCTL_DEF(DRM_IOCTL_GET_SAREA_CTX, drm_legacy_getsareactx, DRM_AUTH),
> 
>-	DRM_IOCTL_DEF(DRM_IOCTL_SET_MASTER, drm_setmaster_ioctl, DRM_UNLOCKED|DRM_ROOT_ONLY),
>-	DRM_IOCTL_DEF(DRM_IOCTL_DROP_MASTER, drm_dropmaster_ioctl, DRM_UNLOCKED|DRM_ROOT_ONLY),
>+	DRM_IOCTL_DEF(DRM_IOCTL_SET_MASTER, drm_setmaster_ioctl, DRM_ROOT_ONLY),
>+	DRM_IOCTL_DEF(DRM_IOCTL_DROP_MASTER, drm_dropmaster_ioctl, DRM_ROOT_ONLY),
> 
> 	DRM_LEGACY_IOCTL_DEF(DRM_IOCTL_ADD_CTX, drm_legacy_addctx, DRM_AUTH|DRM_ROOT_ONLY),
> 	DRM_LEGACY_IOCTL_DEF(DRM_IOCTL_RM_CTX, drm_legacy_rmctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
>@@ -642,74 +641,74 @@
> 
> 	DRM_IOCTL_DEF(DRM_IOCTL_UPDATE_DRAW, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
> 
>-	DRM_IOCTL_DEF(DRM_IOCTL_GEM_CLOSE, drm_gem_close_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF(DRM_IOCTL_GEM_FLINK, drm_gem_flink_ioctl, DRM_AUTH|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_GEM_OPEN, drm_gem_open_ioctl, DRM_AUTH|DRM_UNLOCKED),
>-
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETRESOURCES, drm_mode_getresources, DRM_UNLOCKED),
>-
>-	DRM_IOCTL_DEF(DRM_IOCTL_PRIME_HANDLE_TO_FD, drm_prime_handle_to_fd_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF(DRM_IOCTL_PRIME_FD_TO_HANDLE, drm_prime_fd_to_handle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
>-
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPLANERESOURCES, drm_mode_getplane_res, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCRTC, drm_mode_getcrtc, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETCRTC, drm_mode_setcrtc, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPLANE, drm_mode_getplane, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPLANE, drm_mode_setplane, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR, drm_mode_cursor_ioctl, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETGAMMA, drm_mode_gamma_get_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETGAMMA, drm_mode_gamma_set_ioctl, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETENCODER, drm_mode_getencoder, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCONNECTOR, drm_mode_getconnector, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ATTACHMODE, drm_noop, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DETACHMODE, drm_noop, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPERTY, drm_mode_getproperty_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPROPERTY, drm_connector_property_set_ioctl, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPBLOB, drm_mode_getblob_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETFB, drm_mode_getfb, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB, drm_mode_addfb_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB2, drm_mode_addfb2_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_DUMB, drm_mode_create_dumb_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_MAP_DUMB, drm_mode_mmap_dumb_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROY_DUMB, drm_mode_destroy_dumb_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_GETPROPERTIES, drm_mode_obj_get_properties_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_SETPROPERTY, drm_mode_obj_set_property_ioctl, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR2, drm_mode_cursor2_ioctl, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ATOMIC, drm_mode_atomic_ioctl, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATEPROPBLOB, drm_mode_createblob_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROYPROPBLOB, drm_mode_destroyblob_ioctl, DRM_UNLOCKED),
>+	DRM_IOCTL_DEF(DRM_IOCTL_GEM_CLOSE, drm_gem_close_ioctl, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF(DRM_IOCTL_GEM_FLINK, drm_gem_flink_ioctl, DRM_AUTH),
>+	DRM_IOCTL_DEF(DRM_IOCTL_GEM_OPEN, drm_gem_open_ioctl, DRM_AUTH),
>+
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETRESOURCES, drm_mode_getresources, 0),
>+
>+	DRM_IOCTL_DEF(DRM_IOCTL_PRIME_HANDLE_TO_FD, drm_prime_handle_to_fd_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF(DRM_IOCTL_PRIME_FD_TO_HANDLE, drm_prime_fd_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>+
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPLANERESOURCES, drm_mode_getplane_res, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCRTC, drm_mode_getcrtc, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETCRTC, drm_mode_setcrtc, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPLANE, drm_mode_getplane, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPLANE, drm_mode_setplane, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR, drm_mode_cursor_ioctl, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETGAMMA, drm_mode_gamma_get_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETGAMMA, drm_mode_gamma_set_ioctl, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETENCODER, drm_mode_getencoder, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCONNECTOR, drm_mode_getconnector, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ATTACHMODE, drm_noop, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DETACHMODE, drm_noop, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPERTY, drm_mode_getproperty_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETPROPERTY, drm_connector_property_set_ioctl, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPROPBLOB, drm_mode_getblob_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETFB, drm_mode_getfb, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB, drm_mode_addfb_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ADDFB2, drm_mode_addfb2_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_DUMB, drm_mode_create_dumb_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_MAP_DUMB, drm_mode_mmap_dumb_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROY_DUMB, drm_mode_destroy_dumb_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_GETPROPERTIES, drm_mode_obj_get_properties_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_SETPROPERTY, drm_mode_obj_set_property_ioctl, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CURSOR2, drm_mode_cursor2_ioctl, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_ATOMIC, drm_mode_atomic_ioctl, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATEPROPBLOB, drm_mode_createblob_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROYPROPBLOB, drm_mode_destroyblob_ioctl, 0),
> 
> 	DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_CREATE, drm_syncobj_create_ioctl,
>-		      DRM_UNLOCKED|DRM_RENDER_ALLOW),
>+		      DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_DESTROY, drm_syncobj_destroy_ioctl,
>-		      DRM_UNLOCKED|DRM_RENDER_ALLOW),
>+		      DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD, drm_syncobj_handle_to_fd_ioctl,
>-		      DRM_UNLOCKED|DRM_RENDER_ALLOW),
>+		      DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE, drm_syncobj_fd_to_handle_ioctl,
>-		      DRM_UNLOCKED|DRM_RENDER_ALLOW),
>+		      DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_TRANSFER, drm_syncobj_transfer_ioctl,
>-		      DRM_UNLOCKED|DRM_RENDER_ALLOW),
>+		      DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_WAIT, drm_syncobj_wait_ioctl,
>-		      DRM_UNLOCKED|DRM_RENDER_ALLOW),
>+		      DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT, drm_syncobj_timeline_wait_ioctl,
>-		      DRM_UNLOCKED|DRM_RENDER_ALLOW),
>+		      DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_RESET, drm_syncobj_reset_ioctl,
>-		      DRM_UNLOCKED|DRM_RENDER_ALLOW),
>+		      DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_SIGNAL, drm_syncobj_signal_ioctl,
>-		      DRM_UNLOCKED|DRM_RENDER_ALLOW),
>+		      DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL, drm_syncobj_timeline_signal_ioctl,
>-		      DRM_UNLOCKED|DRM_RENDER_ALLOW),
>+		      DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF(DRM_IOCTL_SYNCOBJ_QUERY, drm_syncobj_query_ioctl,
>-		      DRM_UNLOCKED|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF(DRM_IOCTL_CRTC_GET_SEQUENCE, drm_crtc_get_sequence_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_CRTC_QUEUE_SEQUENCE, drm_crtc_queue_sequence_ioctl, DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_LEASE, drm_mode_create_lease_ioctl, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_LIST_LESSEES, drm_mode_list_lessees_ioctl, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GET_LEASE, drm_mode_get_lease_ioctl, DRM_MASTER|DRM_UNLOCKED),
>-	DRM_IOCTL_DEF(DRM_IOCTL_MODE_REVOKE_LEASE, drm_mode_revoke_lease_ioctl, DRM_MASTER|DRM_UNLOCKED),
>+		      DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF(DRM_IOCTL_CRTC_GET_SEQUENCE, drm_crtc_get_sequence_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_CRTC_QUEUE_SEQUENCE, drm_crtc_queue_sequence_ioctl, 0),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_LEASE, drm_mode_create_lease_ioctl, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_LIST_LESSEES, drm_mode_list_lessees_ioctl, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_GET_LEASE, drm_mode_get_lease_ioctl, DRM_MASTER),
>+	DRM_IOCTL_DEF(DRM_IOCTL_MODE_REVOKE_LEASE, drm_mode_revoke_lease_ioctl, DRM_MASTER),
> };
> 
> #define DRM_CORE_IOCTL_COUNT	ARRAY_SIZE( drm_ioctls )
>@@ -777,7 +776,7 @@
> 		return retcode;
> 
> 	/* Enforce sane locking for modern driver ioctls. */
>-	if (!drm_core_check_feature(dev, DRIVER_LEGACY) ||
>+	if (likely(!drm_core_check_feature(dev, DRIVER_LEGACY)) ||
> 	    (flags & DRM_UNLOCKED))
> 		retcode = func(dev, kdata, file_priv);
> 	else {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_legacy_misc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_legacy_misc.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_legacy_misc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_legacy_misc.c	2019-08-31 15:01:11.946736176 -0500
>@@ -1,4 +1,4 @@
>-/**
>+/*
>  * \file drm_legacy_misc.c
>  * Misc legacy support functions.
>  *
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_lock.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_lock.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_lock.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_lock.c	2019-08-31 15:01:11.946736176 -0500
>@@ -1,4 +1,4 @@
>-/**
>+/*
>  * \file drm_lock.c
>  * IOCTLs for locking
>  *
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_memory.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_memory.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_memory.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_memory.c	2019-08-31 15:01:11.946736176 -0500
>@@ -1,4 +1,4 @@
>-/**
>+/*
>  * \file drm_memory.c
>  * Memory management wrappers for DRM
>  *
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_mipi_dbi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_mipi_dbi.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_mipi_dbi.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_mipi_dbi.c	2019-08-31 15:01:12.248736203 -0500
>@@ -0,0 +1,1330 @@
>+// SPDX-License-Identifier: GPL-2.0-or-later
>+/*
>+ * MIPI Display Bus Interface (DBI) LCD controller support
>+ *
>+ * Copyright 2016 Noralf TrÃ¸nnes
>+ */
>+
>+#include <linux/debugfs.h>
>+#include <linux/delay.h>
>+#include <linux/dma-buf.h>
>+#include <linux/gpio/consumer.h>
>+#include <linux/module.h>
>+#include <linux/regulator/consumer.h>
>+#include <linux/spi/spi.h>
>+
>+#include <drm/drm_connector.h>
>+#include <drm/drm_damage_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_format_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_mipi_dbi.h>
>+#include <drm/drm_modes.h>
>+#include <drm/drm_probe_helper.h>
>+#include <drm/drm_rect.h>
>+#include <drm/drm_vblank.h>
>+#include <video/mipi_display.h>
>+
>+#define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
>+
>+#define DCS_POWER_MODE_DISPLAY			BIT(2)
>+#define DCS_POWER_MODE_DISPLAY_NORMAL_MODE	BIT(3)
>+#define DCS_POWER_MODE_SLEEP_MODE		BIT(4)
>+#define DCS_POWER_MODE_PARTIAL_MODE		BIT(5)
>+#define DCS_POWER_MODE_IDLE_MODE		BIT(6)
>+#define DCS_POWER_MODE_RESERVED_MASK		(BIT(0) | BIT(1) | BIT(7))
>+
>+/**
>+ * DOC: overview
>+ *
>+ * This library provides helpers for MIPI Display Bus Interface (DBI)
>+ * compatible display controllers.
>+ *
>+ * Many controllers for tiny lcd displays are MIPI compliant and can use this
>+ * library. If a controller uses registers 0x2A and 0x2B to set the area to
>+ * update and uses register 0x2C to write to frame memory, it is most likely
>+ * MIPI compliant.
>+ *
>+ * Only MIPI Type 1 displays are supported since a full frame memory is needed.
>+ *
>+ * There are 3 MIPI DBI implementation types:
>+ *
>+ * A. Motorola 6800 type parallel bus
>+ *
>+ * B. Intel 8080 type parallel bus
>+ *
>+ * C. SPI type with 3 options:
>+ *
>+ *    1. 9-bit with the Data/Command signal as the ninth bit
>+ *    2. Same as above except it's sent as 16 bits
>+ *    3. 8-bit with the Data/Command signal as a separate D/CX pin
>+ *
>+ * Currently mipi_dbi only supports Type C options 1 and 3 with
>+ * mipi_dbi_spi_init().
>+ */
>+
>+#define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
>+({ \
>+	if (!len) \
>+		DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
>+	else if (len <= 32) \
>+		DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
>+	else \
>+		DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
>+})
>+
>+static const u8 mipi_dbi_dcs_read_commands[] = {
>+	MIPI_DCS_GET_DISPLAY_ID,
>+	MIPI_DCS_GET_RED_CHANNEL,
>+	MIPI_DCS_GET_GREEN_CHANNEL,
>+	MIPI_DCS_GET_BLUE_CHANNEL,
>+	MIPI_DCS_GET_DISPLAY_STATUS,
>+	MIPI_DCS_GET_POWER_MODE,
>+	MIPI_DCS_GET_ADDRESS_MODE,
>+	MIPI_DCS_GET_PIXEL_FORMAT,
>+	MIPI_DCS_GET_DISPLAY_MODE,
>+	MIPI_DCS_GET_SIGNAL_MODE,
>+	MIPI_DCS_GET_DIAGNOSTIC_RESULT,
>+	MIPI_DCS_READ_MEMORY_START,
>+	MIPI_DCS_READ_MEMORY_CONTINUE,
>+	MIPI_DCS_GET_SCANLINE,
>+	MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
>+	MIPI_DCS_GET_CONTROL_DISPLAY,
>+	MIPI_DCS_GET_POWER_SAVE,
>+	MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
>+	MIPI_DCS_READ_DDB_START,
>+	MIPI_DCS_READ_DDB_CONTINUE,
>+	0, /* sentinel */
>+};
>+
>+static bool mipi_dbi_command_is_read(struct mipi_dbi *dbi, u8 cmd)
>+{
>+	unsigned int i;
>+
>+	if (!dbi->read_commands)
>+		return false;
>+
>+	for (i = 0; i < 0xff; i++) {
>+		if (!dbi->read_commands[i])
>+			return false;
>+		if (cmd == dbi->read_commands[i])
>+			return true;
>+	}
>+
>+	return false;
>+}
>+
>+/**
>+ * mipi_dbi_command_read - MIPI DCS read command
>+ * @dbi: MIPI DBI structure
>+ * @cmd: Command
>+ * @val: Value read
>+ *
>+ * Send MIPI DCS read command to the controller.
>+ *
>+ * Returns:
>+ * Zero on success, negative error code on failure.
>+ */
>+int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val)
>+{
>+	if (!dbi->read_commands)
>+		return -EACCES;
>+
>+	if (!mipi_dbi_command_is_read(dbi, cmd))
>+		return -EINVAL;
>+
>+	return mipi_dbi_command_buf(dbi, cmd, val, 1);
>+}
>+EXPORT_SYMBOL(mipi_dbi_command_read);
>+
>+/**
>+ * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
>+ * @dbi: MIPI DBI structure
>+ * @cmd: Command
>+ * @data: Parameter buffer
>+ * @len: Buffer length
>+ *
>+ * Returns:
>+ * Zero on success, negative error code on failure.
>+ */
>+int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
>+{
>+	u8 *cmdbuf;
>+	int ret;
>+
>+	/* SPI requires dma-safe buffers */
>+	cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
>+	if (!cmdbuf)
>+		return -ENOMEM;
>+
>+	mutex_lock(&dbi->cmdlock);
>+	ret = dbi->command(dbi, cmdbuf, data, len);
>+	mutex_unlock(&dbi->cmdlock);
>+
>+	kfree(cmdbuf);
>+
>+	return ret;
>+}
>+EXPORT_SYMBOL(mipi_dbi_command_buf);
>+
>+/* This should only be used by mipi_dbi_command() */
>+int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len)
>+{
>+	u8 *buf;
>+	int ret;
>+
>+	buf = kmemdup(data, len, GFP_KERNEL);
>+	if (!buf)
>+		return -ENOMEM;
>+
>+	ret = mipi_dbi_command_buf(dbi, cmd, buf, len);
>+
>+	kfree(buf);
>+
>+	return ret;
>+}
>+EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
>+
>+/**
>+ * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
>+ * @dst: The destination buffer
>+ * @fb: The source framebuffer
>+ * @clip: Clipping rectangle of the area to be copied
>+ * @swap: When true, swap MSB/LSB of 16-bit values
>+ *
>+ * Returns:
>+ * Zero on success, negative error code on failure.
>+ */
>+int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
>+		      struct drm_rect *clip, bool swap)
>+{
>+	struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
>+	struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem);
>+	struct dma_buf_attachment *import_attach = gem->import_attach;
>+	struct drm_format_name_buf format_name;
>+	void *src = cma_obj->vaddr;
>+	int ret = 0;
>+
>+	if (import_attach) {
>+		ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
>+					       DMA_FROM_DEVICE);
>+		if (ret)
>+			return ret;
>+	}
>+
>+	switch (fb->format->format) {
>+	case DRM_FORMAT_RGB565:
>+		if (swap)
>+			drm_fb_swab16(dst, src, fb, clip);
>+		else
>+			drm_fb_memcpy(dst, src, fb, clip);
>+		break;
>+	case DRM_FORMAT_XRGB8888:
>+		drm_fb_xrgb8888_to_rgb565(dst, src, fb, clip, swap);
>+		break;
>+	default:
>+		dev_err_once(fb->dev->dev, "Format is not supported: %s\n",
>+			     drm_get_format_name(fb->format->format,
>+						 &format_name));
>+		return -EINVAL;
>+	}
>+
>+	if (import_attach)
>+		ret = dma_buf_end_cpu_access(import_attach->dmabuf,
>+					     DMA_FROM_DEVICE);
>+	return ret;
>+}
>+EXPORT_SYMBOL(mipi_dbi_buf_copy);
>+
>+static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
>+{
>+	struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
>+	struct drm_gem_cma_object *cma_obj = to_drm_gem_cma_obj(gem);
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
>+	unsigned int height = rect->y2 - rect->y1;
>+	unsigned int width = rect->x2 - rect->x1;
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+	bool swap = dbi->swap_bytes;
>+	int idx, ret = 0;
>+	bool full;
>+	void *tr;
>+
>+	if (!dbidev->enabled)
>+		return;
>+
>+	if (!drm_dev_enter(fb->dev, &idx))
>+		return;
>+
>+	full = width == fb->width && height == fb->height;
>+
>+	DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
>+
>+	if (!dbi->dc || !full || swap ||
>+	    fb->format->format == DRM_FORMAT_XRGB8888) {
>+		tr = dbidev->tx_buf;
>+		ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap);
>+		if (ret)
>+			goto err_msg;
>+	} else {
>+		tr = cma_obj->vaddr;
>+	}
>+
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS,
>+			 (rect->x1 >> 8) & 0xff, rect->x1 & 0xff,
>+			 ((rect->x2 - 1) >> 8) & 0xff, (rect->x2 - 1) & 0xff);
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS,
>+			 (rect->y1 >> 8) & 0xff, rect->y1 & 0xff,
>+			 ((rect->y2 - 1) >> 8) & 0xff, (rect->y2 - 1) & 0xff);
>+
>+	ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr,
>+				   width * height * 2);
>+err_msg:
>+	if (ret)
>+		dev_err_once(fb->dev->dev, "Failed to update display %d\n", ret);
>+
>+	drm_dev_exit(idx);
>+}
>+
>+/**
>+ * mipi_dbi_pipe_update - Display pipe update helper
>+ * @pipe: Simple display pipe
>+ * @old_state: Old plane state
>+ *
>+ * This function handles framebuffer flushing and vblank events. Drivers can use
>+ * this as their &drm_simple_display_pipe_funcs->update callback.
>+ */
>+void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
>+			  struct drm_plane_state *old_state)
>+{
>+	struct drm_plane_state *state = pipe->plane.state;
>+	struct drm_crtc *crtc = &pipe->crtc;
>+	struct drm_rect rect;
>+
>+	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
>+		mipi_dbi_fb_dirty(state->fb, &rect);
>+
>+	if (crtc->state->event) {
>+		spin_lock_irq(&crtc->dev->event_lock);
>+		drm_crtc_send_vblank_event(crtc, crtc->state->event);
>+		spin_unlock_irq(&crtc->dev->event_lock);
>+		crtc->state->event = NULL;
>+	}
>+}
>+EXPORT_SYMBOL(mipi_dbi_pipe_update);
>+
>+/**
>+ * mipi_dbi_enable_flush - MIPI DBI enable helper
>+ * @dbidev: MIPI DBI device structure
>+ * @crtc_state: CRTC state
>+ * @plane_state: Plane state
>+ *
>+ * This function sets &mipi_dbi->enabled, flushes the whole framebuffer and
>+ * enables the backlight. Drivers can use this in their
>+ * &drm_simple_display_pipe_funcs->enable callback.
>+ *
>+ * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom
>+ * framebuffer flushing, can't use this function since they both use the same
>+ * flushing code.
>+ */
>+void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
>+			   struct drm_crtc_state *crtc_state,
>+			   struct drm_plane_state *plane_state)
>+{
>+	struct drm_framebuffer *fb = plane_state->fb;
>+	struct drm_rect rect = {
>+		.x1 = 0,
>+		.x2 = fb->width,
>+		.y1 = 0,
>+		.y2 = fb->height,
>+	};
>+	int idx;
>+
>+	if (!drm_dev_enter(&dbidev->drm, &idx))
>+		return;
>+
>+	dbidev->enabled = true;
>+	mipi_dbi_fb_dirty(fb, &rect);
>+	backlight_enable(dbidev->backlight);
>+
>+	drm_dev_exit(idx);
>+}
>+EXPORT_SYMBOL(mipi_dbi_enable_flush);
>+
>+static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
>+{
>+	struct drm_device *drm = &dbidev->drm;
>+	u16 height = drm->mode_config.min_height;
>+	u16 width = drm->mode_config.min_width;
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+	size_t len = width * height * 2;
>+	int idx;
>+
>+	if (!drm_dev_enter(drm, &idx))
>+		return;
>+
>+	memset(dbidev->tx_buf, 0, len);
>+
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, 0, 0,
>+			 (width >> 8) & 0xFF, (width - 1) & 0xFF);
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, 0, 0,
>+			 (height >> 8) & 0xFF, (height - 1) & 0xFF);
>+	mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
>+			     (u8 *)dbidev->tx_buf, len);
>+
>+	drm_dev_exit(idx);
>+}
>+
>+/**
>+ * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
>+ * @pipe: Display pipe
>+ *
>+ * This function disables backlight if present, if not the display memory is
>+ * blanked. The regulator is disabled if in use. Drivers can use this as their
>+ * &drm_simple_display_pipe_funcs->disable callback.
>+ */
>+void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
>+
>+	if (!dbidev->enabled)
>+		return;
>+
>+	DRM_DEBUG_KMS("\n");
>+
>+	dbidev->enabled = false;
>+
>+	if (dbidev->backlight)
>+		backlight_disable(dbidev->backlight);
>+	else
>+		mipi_dbi_blank(dbidev);
>+
>+	if (dbidev->regulator)
>+		regulator_disable(dbidev->regulator);
>+}
>+EXPORT_SYMBOL(mipi_dbi_pipe_disable);
>+
>+static int mipi_dbi_connector_get_modes(struct drm_connector *connector)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(connector->dev);
>+	struct drm_display_mode *mode;
>+
>+	mode = drm_mode_duplicate(connector->dev, &dbidev->mode);
>+	if (!mode) {
>+		DRM_ERROR("Failed to duplicate mode\n");
>+		return 0;
>+	}
>+
>+	if (mode->name[0] == '\0')
>+		drm_mode_set_name(mode);
>+
>+	mode->type |= DRM_MODE_TYPE_PREFERRED;
>+	drm_mode_probed_add(connector, mode);
>+
>+	if (mode->width_mm) {
>+		connector->display_info.width_mm = mode->width_mm;
>+		connector->display_info.height_mm = mode->height_mm;
>+	}
>+
>+	return 1;
>+}
>+
>+static const struct drm_connector_helper_funcs mipi_dbi_connector_hfuncs = {
>+	.get_modes = mipi_dbi_connector_get_modes,
>+};
>+
>+static const struct drm_connector_funcs mipi_dbi_connector_funcs = {
>+	.reset = drm_atomic_helper_connector_reset,
>+	.fill_modes = drm_helper_probe_single_connector_modes,
>+	.destroy = drm_connector_cleanup,
>+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
>+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>+};
>+
>+static int mipi_dbi_rotate_mode(struct drm_display_mode *mode,
>+				unsigned int rotation)
>+{
>+	if (rotation == 0 || rotation == 180) {
>+		return 0;
>+	} else if (rotation == 90 || rotation == 270) {
>+		swap(mode->hdisplay, mode->vdisplay);
>+		swap(mode->hsync_start, mode->vsync_start);
>+		swap(mode->hsync_end, mode->vsync_end);
>+		swap(mode->htotal, mode->vtotal);
>+		swap(mode->width_mm, mode->height_mm);
>+		return 0;
>+	} else {
>+		return -EINVAL;
>+	}
>+}
>+
>+static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
>+	.fb_create = drm_gem_fb_create_with_dirty,
>+	.atomic_check = drm_atomic_helper_check,
>+	.atomic_commit = drm_atomic_helper_commit,
>+};
>+
>+static const uint32_t mipi_dbi_formats[] = {
>+	DRM_FORMAT_RGB565,
>+	DRM_FORMAT_XRGB8888,
>+};
>+
>+/**
>+ * mipi_dbi_dev_init_with_formats - MIPI DBI device initialization with custom formats
>+ * @dbidev: MIPI DBI device structure to initialize
>+ * @funcs: Display pipe functions
>+ * @formats: Array of supported formats (DRM_FORMAT\_\*).
>+ * @format_count: Number of elements in @formats
>+ * @mode: Display mode
>+ * @rotation: Initial rotation in degrees Counter Clock Wise
>+ * @tx_buf_size: Allocate a transmit buffer of this size.
>+ *
>+ * This function sets up a &drm_simple_display_pipe with a &drm_connector that
>+ * has one fixed &drm_display_mode which is rotated according to @rotation.
>+ * This mode is used to set the mode config min/max width/height properties.
>+ *
>+ * Use mipi_dbi_dev_init() if you don't need custom formats.
>+ *
>+ * Note:
>+ * Some of the helper functions expects RGB565 to be the default format and the
>+ * transmit buffer sized to fit that.
>+ *
>+ * Returns:
>+ * Zero on success, negative error code on failure.
>+ */
>+int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
>+				   const struct drm_simple_display_pipe_funcs *funcs,
>+				   const uint32_t *formats, unsigned int format_count,
>+				   const struct drm_display_mode *mode,
>+				   unsigned int rotation, size_t tx_buf_size)
>+{
>+	static const uint64_t modifiers[] = {
>+		DRM_FORMAT_MOD_LINEAR,
>+		DRM_FORMAT_MOD_INVALID
>+	};
>+	struct drm_device *drm = &dbidev->drm;
>+	int ret;
>+
>+	if (!dbidev->dbi.command)
>+		return -EINVAL;
>+
>+	dbidev->tx_buf = devm_kmalloc(drm->dev, tx_buf_size, GFP_KERNEL);
>+	if (!dbidev->tx_buf)
>+		return -ENOMEM;
>+
>+	drm_mode_copy(&dbidev->mode, mode);
>+	ret = mipi_dbi_rotate_mode(&dbidev->mode, rotation);
>+	if (ret) {
>+		DRM_ERROR("Illegal rotation value %u\n", rotation);
>+		return -EINVAL;
>+	}
>+
>+	drm_connector_helper_add(&dbidev->connector, &mipi_dbi_connector_hfuncs);
>+	ret = drm_connector_init(drm, &dbidev->connector, &mipi_dbi_connector_funcs,
>+				 DRM_MODE_CONNECTOR_SPI);
>+	if (ret)
>+		return ret;
>+
>+	ret = drm_simple_display_pipe_init(drm, &dbidev->pipe, funcs, formats, format_count,
>+					   modifiers, &dbidev->connector);
>+	if (ret)
>+		return ret;
>+
>+	drm_plane_enable_fb_damage_clips(&dbidev->pipe.plane);
>+
>+	drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
>+	drm->mode_config.min_width = dbidev->mode.hdisplay;
>+	drm->mode_config.max_width = dbidev->mode.hdisplay;
>+	drm->mode_config.min_height = dbidev->mode.vdisplay;
>+	drm->mode_config.max_height = dbidev->mode.vdisplay;
>+	dbidev->rotation = rotation;
>+
>+	DRM_DEBUG_KMS("rotation = %u\n", rotation);
>+
>+	return 0;
>+}
>+EXPORT_SYMBOL(mipi_dbi_dev_init_with_formats);
>+
>+/**
>+ * mipi_dbi_dev_init - MIPI DBI device initialization
>+ * @dbidev: MIPI DBI device structure to initialize
>+ * @funcs: Display pipe functions
>+ * @mode: Display mode
>+ * @rotation: Initial rotation in degrees Counter Clock Wise
>+ *
>+ * This function sets up a &drm_simple_display_pipe with a &drm_connector that
>+ * has one fixed &drm_display_mode which is rotated according to @rotation.
>+ * This mode is used to set the mode config min/max width/height properties.
>+ * Additionally &mipi_dbi.tx_buf is allocated.
>+ *
>+ * Supported formats: Native RGB565 and emulated XRGB8888.
>+ *
>+ * Returns:
>+ * Zero on success, negative error code on failure.
>+ */
>+int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
>+		      const struct drm_simple_display_pipe_funcs *funcs,
>+		      const struct drm_display_mode *mode, unsigned int rotation)
>+{
>+	size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
>+
>+	dbidev->drm.mode_config.preferred_depth = 16;
>+
>+	return mipi_dbi_dev_init_with_formats(dbidev, funcs, mipi_dbi_formats,
>+					      ARRAY_SIZE(mipi_dbi_formats), mode,
>+					      rotation, bufsize);
>+}
>+EXPORT_SYMBOL(mipi_dbi_dev_init);
>+
>+/**
>+ * mipi_dbi_release - DRM driver release helper
>+ * @drm: DRM device
>+ *
>+ * This function finalizes and frees &mipi_dbi.
>+ *
>+ * Drivers can use this as their &drm_driver->release callback.
>+ */
>+void mipi_dbi_release(struct drm_device *drm)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(drm);
>+
>+	DRM_DEBUG_DRIVER("\n");
>+
>+	drm_mode_config_cleanup(drm);
>+	drm_dev_fini(drm);
>+	kfree(dbidev);
>+}
>+EXPORT_SYMBOL(mipi_dbi_release);
>+
>+/**
>+ * mipi_dbi_hw_reset - Hardware reset of controller
>+ * @dbi: MIPI DBI structure
>+ *
>+ * Reset controller if the &mipi_dbi->reset gpio is set.
>+ */
>+void mipi_dbi_hw_reset(struct mipi_dbi *dbi)
>+{
>+	if (!dbi->reset)
>+		return;
>+
>+	gpiod_set_value_cansleep(dbi->reset, 0);
>+	usleep_range(20, 1000);
>+	gpiod_set_value_cansleep(dbi->reset, 1);
>+	msleep(120);
>+}
>+EXPORT_SYMBOL(mipi_dbi_hw_reset);
>+
>+/**
>+ * mipi_dbi_display_is_on - Check if display is on
>+ * @dbi: MIPI DBI structure
>+ *
>+ * This function checks the Power Mode register (if readable) to see if
>+ * display output is turned on. This can be used to see if the bootloader
>+ * has already turned on the display avoiding flicker when the pipeline is
>+ * enabled.
>+ *
>+ * Returns:
>+ * true if the display can be verified to be on, false otherwise.
>+ */
>+bool mipi_dbi_display_is_on(struct mipi_dbi *dbi)
>+{
>+	u8 val;
>+
>+	if (mipi_dbi_command_read(dbi, MIPI_DCS_GET_POWER_MODE, &val))
>+		return false;
>+
>+	val &= ~DCS_POWER_MODE_RESERVED_MASK;
>+
>+	/* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */
>+	if (val != (DCS_POWER_MODE_DISPLAY |
>+	    DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
>+		return false;
>+
>+	DRM_DEBUG_DRIVER("Display is ON\n");
>+
>+	return true;
>+}
>+EXPORT_SYMBOL(mipi_dbi_display_is_on);
>+
>+static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi_dev *dbidev, bool cond)
>+{
>+	struct device *dev = dbidev->drm.dev;
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+	int ret;
>+
>+	if (dbidev->regulator) {
>+		ret = regulator_enable(dbidev->regulator);
>+		if (ret) {
>+			DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
>+			return ret;
>+		}
>+	}
>+
>+	if (cond && mipi_dbi_display_is_on(dbi))
>+		return 1;
>+
>+	mipi_dbi_hw_reset(dbi);
>+	ret = mipi_dbi_command(dbi, MIPI_DCS_SOFT_RESET);
>+	if (ret) {
>+		DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
>+		if (dbidev->regulator)
>+			regulator_disable(dbidev->regulator);
>+		return ret;
>+	}
>+
>+	/*
>+	 * If we did a hw reset, we know the controller is in Sleep mode and
>+	 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't,
>+	 * we assume worst case and wait 120ms.
>+	 */
>+	if (dbi->reset)
>+		usleep_range(5000, 20000);
>+	else
>+		msleep(120);
>+
>+	return 0;
>+}
>+
>+/**
>+ * mipi_dbi_poweron_reset - MIPI DBI poweron and reset
>+ * @dbidev: MIPI DBI device structure
>+ *
>+ * This function enables the regulator if used and does a hardware and software
>+ * reset.
>+ *
>+ * Returns:
>+ * Zero on success, or a negative error code.
>+ */
>+int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev)
>+{
>+	return mipi_dbi_poweron_reset_conditional(dbidev, false);
>+}
>+EXPORT_SYMBOL(mipi_dbi_poweron_reset);
>+
>+/**
>+ * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset
>+ * @dbidev: MIPI DBI device structure
>+ *
>+ * This function enables the regulator if used and if the display is off, it
>+ * does a hardware and software reset. If mipi_dbi_display_is_on() determines
>+ * that the display is on, no reset is performed.
>+ *
>+ * Returns:
>+ * Zero if the controller was reset, 1 if the display was already on, or a
>+ * negative error code.
>+ */
>+int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev)
>+{
>+	return mipi_dbi_poweron_reset_conditional(dbidev, true);
>+}
>+EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
>+
>+#if IS_ENABLED(CONFIG_SPI)
>+
>+/**
>+ * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
>+ * @spi: SPI device
>+ * @len: The transfer buffer length.
>+ *
>+ * Many controllers have a max speed of 10MHz, but can be pushed way beyond
>+ * that. Increase reliability by running pixel data at max speed and the rest
>+ * at 10MHz, preventing transfer glitches from messing up the init settings.
>+ */
>+u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
>+{
>+	if (len > 64)
>+		return 0; /* use default */
>+
>+	return min_t(u32, 10000000, spi->max_speed_hz);
>+}
>+EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
>+
>+static bool mipi_dbi_machine_little_endian(void)
>+{
>+#if defined(__LITTLE_ENDIAN)
>+	return true;
>+#else
>+	return false;
>+#endif
>+}
>+
>+/*
>+ * MIPI DBI Type C Option 1
>+ *
>+ * If the SPI controller doesn't have 9 bits per word support,
>+ * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
>+ * Pad partial blocks with MIPI_DCS_NOP (zero).
>+ * This is how the D/C bit (x) is added:
>+ *     x7654321
>+ *     0x765432
>+ *     10x76543
>+ *     210x7654
>+ *     3210x765
>+ *     43210x76
>+ *     543210x7
>+ *     6543210x
>+ *     76543210
>+ */
>+
>+static int mipi_dbi_spi1e_transfer(struct mipi_dbi *dbi, int dc,
>+				   const void *buf, size_t len,
>+				   unsigned int bpw)
>+{
>+	bool swap_bytes = (bpw == 16 && mipi_dbi_machine_little_endian());
>+	size_t chunk, max_chunk = dbi->tx_buf9_len;
>+	struct spi_device *spi = dbi->spi;
>+	struct spi_transfer tr = {
>+		.tx_buf = dbi->tx_buf9,
>+		.bits_per_word = 8,
>+	};
>+	struct spi_message m;
>+	const u8 *src = buf;
>+	int i, ret;
>+	u8 *dst;
>+
>+	if (drm_debug & DRM_UT_DRIVER)
>+		pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
>+			 __func__, dc, max_chunk);
>+
>+	tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
>+	spi_message_init_with_transfers(&m, &tr, 1);
>+
>+	if (!dc) {
>+		if (WARN_ON_ONCE(len != 1))
>+			return -EINVAL;
>+
>+		/* Command: pad no-op's (zeroes) at beginning of block */
>+		dst = dbi->tx_buf9;
>+		memset(dst, 0, 9);
>+		dst[8] = *src;
>+		tr.len = 9;
>+
>+		return spi_sync(spi, &m);
>+	}
>+
>+	/* max with room for adding one bit per byte */
>+	max_chunk = max_chunk / 9 * 8;
>+	/* but no bigger than len */
>+	max_chunk = min(max_chunk, len);
>+	/* 8 byte blocks */
>+	max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
>+
>+	while (len) {
>+		size_t added = 0;
>+
>+		chunk = min(len, max_chunk);
>+		len -= chunk;
>+		dst = dbi->tx_buf9;
>+
>+		if (chunk < 8) {
>+			u8 val, carry = 0;
>+
>+			/* Data: pad no-op's (zeroes) at end of block */
>+			memset(dst, 0, 9);
>+
>+			if (swap_bytes) {
>+				for (i = 1; i < (chunk + 1); i++) {
>+					val = src[1];
>+					*dst++ = carry | BIT(8 - i) | (val >> i);
>+					carry = val << (8 - i);
>+					i++;
>+					val = src[0];
>+					*dst++ = carry | BIT(8 - i) | (val >> i);
>+					carry = val << (8 - i);
>+					src += 2;
>+				}
>+				*dst++ = carry;
>+			} else {
>+				for (i = 1; i < (chunk + 1); i++) {
>+					val = *src++;
>+					*dst++ = carry | BIT(8 - i) | (val >> i);
>+					carry = val << (8 - i);
>+				}
>+				*dst++ = carry;
>+			}
>+
>+			chunk = 8;
>+			added = 1;
>+		} else {
>+			for (i = 0; i < chunk; i += 8) {
>+				if (swap_bytes) {
>+					*dst++ =                 BIT(7) | (src[1] >> 1);
>+					*dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
>+					*dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
>+					*dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
>+					*dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
>+					*dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
>+					*dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
>+					*dst++ = (src[7] << 1) | BIT(0);
>+					*dst++ = src[6];
>+				} else {
>+					*dst++ =                 BIT(7) | (src[0] >> 1);
>+					*dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
>+					*dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
>+					*dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
>+					*dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
>+					*dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
>+					*dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
>+					*dst++ = (src[6] << 1) | BIT(0);
>+					*dst++ = src[7];
>+				}
>+
>+				src += 8;
>+				added++;
>+			}
>+		}
>+
>+		tr.len = chunk + added;
>+
>+		ret = spi_sync(spi, &m);
>+		if (ret)
>+			return ret;
>+	}
>+
>+	return 0;
>+}
>+
>+static int mipi_dbi_spi1_transfer(struct mipi_dbi *dbi, int dc,
>+				  const void *buf, size_t len,
>+				  unsigned int bpw)
>+{
>+	struct spi_device *spi = dbi->spi;
>+	struct spi_transfer tr = {
>+		.bits_per_word = 9,
>+	};
>+	const u16 *src16 = buf;
>+	const u8 *src8 = buf;
>+	struct spi_message m;
>+	size_t max_chunk;
>+	u16 *dst16;
>+	int ret;
>+
>+	if (!spi_is_bpw_supported(spi, 9))
>+		return mipi_dbi_spi1e_transfer(dbi, dc, buf, len, bpw);
>+
>+	tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
>+	max_chunk = dbi->tx_buf9_len;
>+	dst16 = dbi->tx_buf9;
>+
>+	if (drm_debug & DRM_UT_DRIVER)
>+		pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
>+			 __func__, dc, max_chunk);
>+
>+	max_chunk = min(max_chunk / 2, len);
>+
>+	spi_message_init_with_transfers(&m, &tr, 1);
>+	tr.tx_buf = dst16;
>+
>+	while (len) {
>+		size_t chunk = min(len, max_chunk);
>+		unsigned int i;
>+
>+		if (bpw == 16 && mipi_dbi_machine_little_endian()) {
>+			for (i = 0; i < (chunk * 2); i += 2) {
>+				dst16[i]     = *src16 >> 8;
>+				dst16[i + 1] = *src16++ & 0xFF;
>+				if (dc) {
>+					dst16[i]     |= 0x0100;
>+					dst16[i + 1] |= 0x0100;
>+				}
>+			}
>+		} else {
>+			for (i = 0; i < chunk; i++) {
>+				dst16[i] = *src8++;
>+				if (dc)
>+					dst16[i] |= 0x0100;
>+			}
>+		}
>+
>+		tr.len = chunk;
>+		len -= chunk;
>+
>+		ret = spi_sync(spi, &m);
>+		if (ret)
>+			return ret;
>+	}
>+
>+	return 0;
>+}
>+
>+static int mipi_dbi_typec1_command(struct mipi_dbi *dbi, u8 *cmd,
>+				   u8 *parameters, size_t num)
>+{
>+	unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;
>+	int ret;
>+
>+	if (mipi_dbi_command_is_read(dbi, *cmd))
>+		return -ENOTSUPP;
>+
>+	MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
>+
>+	ret = mipi_dbi_spi1_transfer(dbi, 0, cmd, 1, 8);
>+	if (ret || !num)
>+		return ret;
>+
>+	return mipi_dbi_spi1_transfer(dbi, 1, parameters, num, bpw);
>+}
>+
>+/* MIPI DBI Type C Option 3 */
>+
>+static int mipi_dbi_typec3_command_read(struct mipi_dbi *dbi, u8 *cmd,
>+					u8 *data, size_t len)
>+{
>+	struct spi_device *spi = dbi->spi;
>+	u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
>+			     spi->max_speed_hz / 2);
>+	struct spi_transfer tr[2] = {
>+		{
>+			.speed_hz = speed_hz,
>+			.tx_buf = cmd,
>+			.len = 1,
>+		}, {
>+			.speed_hz = speed_hz,
>+			.len = len,
>+		},
>+	};
>+	struct spi_message m;
>+	u8 *buf;
>+	int ret;
>+
>+	if (!len)
>+		return -EINVAL;
>+
>+	/*
>+	 * Support non-standard 24-bit and 32-bit Nokia read commands which
>+	 * start with a dummy clock, so we need to read an extra byte.
>+	 */
>+	if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
>+	    *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
>+		if (!(len == 3 || len == 4))
>+			return -EINVAL;
>+
>+		tr[1].len = len + 1;
>+	}
>+
>+	buf = kmalloc(tr[1].len, GFP_KERNEL);
>+	if (!buf)
>+		return -ENOMEM;
>+
>+	tr[1].rx_buf = buf;
>+	gpiod_set_value_cansleep(dbi->dc, 0);
>+
>+	spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
>+	ret = spi_sync(spi, &m);
>+	if (ret)
>+		goto err_free;
>+
>+	if (tr[1].len == len) {
>+		memcpy(data, buf, len);
>+	} else {
>+		unsigned int i;
>+
>+		for (i = 0; i < len; i++)
>+			data[i] = (buf[i] << 1) | !!(buf[i + 1] & BIT(7));
>+	}
>+
>+	MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
>+
>+err_free:
>+	kfree(buf);
>+
>+	return ret;
>+}
>+
>+static int mipi_dbi_typec3_command(struct mipi_dbi *dbi, u8 *cmd,
>+				   u8 *par, size_t num)
>+{
>+	struct spi_device *spi = dbi->spi;
>+	unsigned int bpw = 8;
>+	u32 speed_hz;
>+	int ret;
>+
>+	if (mipi_dbi_command_is_read(dbi, *cmd))
>+		return mipi_dbi_typec3_command_read(dbi, cmd, par, num);
>+
>+	MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
>+
>+	gpiod_set_value_cansleep(dbi->dc, 0);
>+	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
>+	ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
>+	if (ret || !num)
>+		return ret;
>+
>+	if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !dbi->swap_bytes)
>+		bpw = 16;
>+
>+	gpiod_set_value_cansleep(dbi->dc, 1);
>+	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
>+
>+	return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
>+}
>+
>+/**
>+ * mipi_dbi_spi_init - Initialize MIPI DBI SPI interface
>+ * @spi: SPI device
>+ * @dbi: MIPI DBI structure to initialize
>+ * @dc: D/C gpio (optional)
>+ *
>+ * This function sets &mipi_dbi->command, enables &mipi_dbi->read_commands for the
>+ * usual read commands. It should be followed by a call to mipi_dbi_dev_init() or
>+ * a driver-specific init.
>+ *
>+ * If @dc is set, a Type C Option 3 interface is assumed, if not
>+ * Type C Option 1.
>+ *
>+ * If the SPI master driver doesn't support the necessary bits per word,
>+ * the following transformation is used:
>+ *
>+ * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command.
>+ * - 16-bit: if big endian send as 8-bit, if little endian swap bytes
>+ *
>+ * Returns:
>+ * Zero on success, negative error code on failure.
>+ */
>+int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
>+		      struct gpio_desc *dc)
>+{
>+	struct device *dev = &spi->dev;
>+	int ret;
>+
>+	/*
>+	 * Even though it's not the SPI device that does DMA (the master does),
>+	 * the dma mask is necessary for the dma_alloc_wc() in
>+	 * drm_gem_cma_create(). The dma_addr returned will be a physical
>+	 * address which might be different from the bus address, but this is
>+	 * not a problem since the address will not be used.
>+	 * The virtual address is used in the transfer and the SPI core
>+	 * re-maps it on the SPI master device using the DMA streaming API
>+	 * (spi_map_buf()).
>+	 */
>+	if (!dev->coherent_dma_mask) {
>+		ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
>+		if (ret) {
>+			dev_warn(dev, "Failed to set dma mask %d\n", ret);
>+			return ret;
>+		}
>+	}
>+
>+	dbi->spi = spi;
>+	dbi->read_commands = mipi_dbi_dcs_read_commands;
>+
>+	if (dc) {
>+		dbi->command = mipi_dbi_typec3_command;
>+		dbi->dc = dc;
>+		if (mipi_dbi_machine_little_endian() && !spi_is_bpw_supported(spi, 16))
>+			dbi->swap_bytes = true;
>+	} else {
>+		dbi->command = mipi_dbi_typec1_command;
>+		dbi->tx_buf9_len = SZ_16K;
>+		dbi->tx_buf9 = devm_kmalloc(dev, dbi->tx_buf9_len, GFP_KERNEL);
>+		if (!dbi->tx_buf9)
>+			return -ENOMEM;
>+	}
>+
>+	mutex_init(&dbi->cmdlock);
>+
>+	DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
>+
>+	return 0;
>+}
>+EXPORT_SYMBOL(mipi_dbi_spi_init);
>+
>+/**
>+ * mipi_dbi_spi_transfer - SPI transfer helper
>+ * @spi: SPI device
>+ * @speed_hz: Override speed (optional)
>+ * @bpw: Bits per word
>+ * @buf: Buffer to transfer
>+ * @len: Buffer length
>+ *
>+ * This SPI transfer helper breaks up the transfer of @buf into chunks which
>+ * the SPI controller driver can handle.
>+ *
>+ * Returns:
>+ * Zero on success, negative error code on failure.
>+ */
>+int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
>+			  u8 bpw, const void *buf, size_t len)
>+{
>+	size_t max_chunk = spi_max_transfer_size(spi);
>+	struct spi_transfer tr = {
>+		.bits_per_word = bpw,
>+		.speed_hz = speed_hz,
>+	};
>+	struct spi_message m;
>+	size_t chunk;
>+	int ret;
>+
>+	spi_message_init_with_transfers(&m, &tr, 1);
>+
>+	while (len) {
>+		chunk = min(len, max_chunk);
>+
>+		tr.tx_buf = buf;
>+		tr.len = chunk;
>+		buf += chunk;
>+		len -= chunk;
>+
>+		ret = spi_sync(spi, &m);
>+		if (ret)
>+			return ret;
>+	}
>+
>+	return 0;
>+}
>+EXPORT_SYMBOL(mipi_dbi_spi_transfer);
>+
>+#endif /* CONFIG_SPI */
>+
>+#ifdef CONFIG_DEBUG_FS
>+
>+static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
>+					      const char __user *ubuf,
>+					      size_t count, loff_t *ppos)
>+{
>+	struct seq_file *m = file->private_data;
>+	struct mipi_dbi_dev *dbidev = m->private;
>+	u8 val, cmd = 0, parameters[64];
>+	char *buf, *pos, *token;
>+	unsigned int i;
>+	int ret, idx;
>+
>+	if (!drm_dev_enter(&dbidev->drm, &idx))
>+		return -ENODEV;
>+
>+	buf = memdup_user_nul(ubuf, count);
>+	if (IS_ERR(buf)) {
>+		ret = PTR_ERR(buf);
>+		goto err_exit;
>+	}
>+
>+	/* strip trailing whitespace */
>+	for (i = count - 1; i > 0; i--)
>+		if (isspace(buf[i]))
>+			buf[i] = '\0';
>+		else
>+			break;
>+	i = 0;
>+	pos = buf;
>+	while (pos) {
>+		token = strsep(&pos, " ");
>+		if (!token) {
>+			ret = -EINVAL;
>+			goto err_free;
>+		}
>+
>+		ret = kstrtou8(token, 16, &val);
>+		if (ret < 0)
>+			goto err_free;
>+
>+		if (token == buf)
>+			cmd = val;
>+		else
>+			parameters[i++] = val;
>+
>+		if (i == 64) {
>+			ret = -E2BIG;
>+			goto err_free;
>+		}
>+	}
>+
>+	ret = mipi_dbi_command_buf(&dbidev->dbi, cmd, parameters, i);
>+
>+err_free:
>+	kfree(buf);
>+err_exit:
>+	drm_dev_exit(idx);
>+
>+	return ret < 0 ? ret : count;
>+}
>+
>+static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
>+{
>+	struct mipi_dbi_dev *dbidev = m->private;
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+	u8 cmd, val[4];
>+	int ret, idx;
>+	size_t len;
>+
>+	if (!drm_dev_enter(&dbidev->drm, &idx))
>+		return -ENODEV;
>+
>+	for (cmd = 0; cmd < 255; cmd++) {
>+		if (!mipi_dbi_command_is_read(dbi, cmd))
>+			continue;
>+
>+		switch (cmd) {
>+		case MIPI_DCS_READ_MEMORY_START:
>+		case MIPI_DCS_READ_MEMORY_CONTINUE:
>+			len = 2;
>+			break;
>+		case MIPI_DCS_GET_DISPLAY_ID:
>+			len = 3;
>+			break;
>+		case MIPI_DCS_GET_DISPLAY_STATUS:
>+			len = 4;
>+			break;
>+		default:
>+			len = 1;
>+			break;
>+		}
>+
>+		seq_printf(m, "%02x: ", cmd);
>+		ret = mipi_dbi_command_buf(dbi, cmd, val, len);
>+		if (ret) {
>+			seq_puts(m, "XX\n");
>+			continue;
>+		}
>+		seq_printf(m, "%*phN\n", (int)len, val);
>+	}
>+
>+	drm_dev_exit(idx);
>+
>+	return 0;
>+}
>+
>+static int mipi_dbi_debugfs_command_open(struct inode *inode,
>+					 struct file *file)
>+{
>+	return single_open(file, mipi_dbi_debugfs_command_show,
>+			   inode->i_private);
>+}
>+
>+static const struct file_operations mipi_dbi_debugfs_command_fops = {
>+	.owner = THIS_MODULE,
>+	.open = mipi_dbi_debugfs_command_open,
>+	.read = seq_read,
>+	.llseek = seq_lseek,
>+	.release = single_release,
>+	.write = mipi_dbi_debugfs_command_write,
>+};
>+
>+/**
>+ * mipi_dbi_debugfs_init - Create debugfs entries
>+ * @minor: DRM minor
>+ *
>+ * This function creates a 'command' debugfs file for sending commands to the
>+ * controller or getting the read command values.
>+ * Drivers can use this as their &drm_driver->debugfs_init callback.
>+ *
>+ * Returns:
>+ * Zero on success, negative error code on failure.
>+ */
>+int mipi_dbi_debugfs_init(struct drm_minor *minor)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(minor->dev);
>+	umode_t mode = S_IFREG | S_IWUSR;
>+
>+	if (dbidev->dbi.read_commands)
>+		mode |= S_IRUGO;
>+	debugfs_create_file("command", mode, minor->debugfs_root, dbidev,
>+			    &mipi_dbi_debugfs_command_fops);
>+
>+	return 0;
>+}
>+EXPORT_SYMBOL(mipi_dbi_debugfs_init);
>+
>+#endif
>+
>+MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_mm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_mm.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_mm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_mm.c	2019-08-31 15:01:11.946736176 -0500
>@@ -472,7 +472,7 @@
> 	u64 remainder_mask;
> 	bool once;
> 
>-	DRM_MM_BUG_ON(range_start >= range_end);
>+	DRM_MM_BUG_ON(range_start > range_end);
> 
> 	if (unlikely(size == 0 || range_end - range_start < size))
> 		return -ENOSPC;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_mode_object.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_mode_object.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_mode_object.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_mode_object.c	2019-08-31 15:01:11.946736176 -0500
>@@ -42,6 +42,8 @@
> {
> 	int ret;
> 
>+	WARN_ON(dev->registered && !obj_free_cb);
>+
> 	mutex_lock(&dev->mode_config.idr_mutex);
> 	ret = idr_alloc(&dev->mode_config.object_idr, register_obj ? obj : NULL,
> 			1, 0, GFP_KERNEL);
>@@ -102,6 +104,8 @@
> void drm_mode_object_unregister(struct drm_device *dev,
> 				struct drm_mode_object *object)
> {
>+	WARN_ON(dev->registered && !object->free_cb);
>+
> 	mutex_lock(&dev->mode_config.idr_mutex);
> 	if (object->id) {
> 		idr_remove(&dev->mode_config.object_idr, object->id);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_modes.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_modes.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_modes.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_modes.c	2019-08-31 15:01:12.248736203 -0500
>@@ -1914,8 +1914,11 @@
> 	case HDMI_PICTURE_ASPECT_256_135:
> 		out->flags |= DRM_MODE_FLAG_PIC_AR_256_135;
> 		break;
>-	case HDMI_PICTURE_ASPECT_RESERVED:
> 	default:
>+		WARN(1, "Invalid aspect ratio (0%x) on mode\n",
>+		     in->picture_aspect_ratio);
>+		/* fall through */
>+	case HDMI_PICTURE_ASPECT_NONE:
> 		out->flags |= DRM_MODE_FLAG_PIC_AR_NONE;
> 		break;
> 	}
>@@ -1974,20 +1977,22 @@
> 
> 	switch (in->flags & DRM_MODE_FLAG_PIC_AR_MASK) {
> 	case DRM_MODE_FLAG_PIC_AR_4_3:
>-		out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_4_3;
>+		out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
> 		break;
> 	case DRM_MODE_FLAG_PIC_AR_16_9:
>-		out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_16_9;
>+		out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
> 		break;
> 	case DRM_MODE_FLAG_PIC_AR_64_27:
>-		out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_64_27;
>+		out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27;
> 		break;
> 	case DRM_MODE_FLAG_PIC_AR_256_135:
>-		out->picture_aspect_ratio |= HDMI_PICTURE_ASPECT_256_135;
>+		out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135;
> 		break;
>-	default:
>+	case DRM_MODE_FLAG_PIC_AR_NONE:
> 		out->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
> 		break;
>+	default:
>+		return -EINVAL;
> 	}
> 
> 	out->status = drm_mode_validate_driver(dev, out);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_prime.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_prime.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_prime.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_prime.c	2019-08-31 15:01:11.946736176 -0500
>@@ -30,6 +30,7 @@
> #include <linux/dma-buf.h>
> #include <linux/rbtree.h>
> 
>+#include <drm/drm.h>
> #include <drm/drm_drv.h>
> #include <drm/drm_file.h>
> #include <drm/drm_framebuffer.h>
>@@ -38,47 +39,52 @@
> 
> #include "drm_internal.h"
> 
>-/*
>- * DMA-BUF/GEM Object references and lifetime overview:
>- *
>- * On the export the dma_buf holds a reference to the exporting GEM
>- * object. It takes this reference in handle_to_fd_ioctl, when it
>- * first calls .prime_export and stores the exporting GEM object in
>- * the dma_buf priv. This reference needs to be released when the
>- * final reference to the &dma_buf itself is dropped and its
>- * &dma_buf_ops.release function is called. For GEM-based drivers,
>- * the dma_buf should be exported using drm_gem_dmabuf_export() and
>- * then released by drm_gem_dmabuf_release().
>- *
>- * On the import the importing GEM object holds a reference to the
>- * dma_buf (which in turn holds a ref to the exporting GEM object).
>- * It takes that reference in the fd_to_handle ioctl.
>- * It calls dma_buf_get, creates an attachment to it and stores the
>- * attachment in the GEM object. When this attachment is destroyed
>- * when the imported object is destroyed, we remove the attachment
>- * and drop the reference to the dma_buf.
>- *
>- * When all the references to the &dma_buf are dropped, i.e. when
>- * userspace has closed both handles to the imported GEM object (through the
>- * FD_TO_HANDLE IOCTL) and closed the file descriptor of the exported
>- * (through the HANDLE_TO_FD IOCTL) dma_buf, and all kernel-internal references
>- * are also gone, then the dma_buf gets destroyed.  This can also happen as a
>- * part of the clean up procedure in the drm_release() function if userspace
>- * fails to properly clean up.  Note that both the kernel and userspace (by
>- * keeeping the PRIME file descriptors open) can hold references onto a
>- * &dma_buf.
>- *
>- * Thus the chain of references always flows in one direction
>- * (avoiding loops): importing_gem -> dmabuf -> exporting_gem
>- *
>- * Self-importing: if userspace is using PRIME as a replacement for flink
>- * then it will get a fd->handle request for a GEM object that it created.
>- * Drivers should detect this situation and return back the gem object
>- * from the dma-buf private.  Prime will do this automatically for drivers that
>- * use the drm_gem_prime_{import,export} helpers.
>+/**
>+ * DOC: overview and lifetime rules
>  *
>- * GEM struct &dma_buf_ops symbols are now exported. They can be resued by
>- * drivers which implement GEM interface.
>+ * Similar to GEM global names, PRIME file descriptors are also used to share
>+ * buffer objects across processes. They offer additional security: as file
>+ * descriptors must be explicitly sent over UNIX domain sockets to be shared
>+ * between applications, they can't be guessed like the globally unique GEM
>+ * names.
>+ *
>+ * Drivers that support the PRIME API implement the
>+ * &drm_driver.prime_handle_to_fd and &drm_driver.prime_fd_to_handle operations.
>+ * GEM based drivers must use drm_gem_prime_handle_to_fd() and
>+ * drm_gem_prime_fd_to_handle() to implement these. For GEM based drivers the
>+ * actual driver interfaces is provided through the &drm_gem_object_funcs.export
>+ * and &drm_driver.gem_prime_import hooks.
>+ *
>+ * &dma_buf_ops implementations for GEM drivers are all individually exported
>+ * for drivers which need to overwrite or reimplement some of them.
>+ *
>+ * Reference Counting for GEM Drivers
>+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>+ *
>+ * On the export the &dma_buf holds a reference to the exported buffer object,
>+ * usually a &drm_gem_object. It takes this reference in the PRIME_HANDLE_TO_FD
>+ * IOCTL, when it first calls &drm_gem_object_funcs.export
>+ * and stores the exporting GEM object in the &dma_buf.priv field. This
>+ * reference needs to be released when the final reference to the &dma_buf
>+ * itself is dropped and its &dma_buf_ops.release function is called.  For
>+ * GEM-based drivers, the &dma_buf should be exported using
>+ * drm_gem_dmabuf_export() and then released by drm_gem_dmabuf_release().
>+ *
>+ * Thus the chain of references always flows in one direction, avoiding loops:
>+ * importing GEM object -> dma-buf -> exported GEM bo. A further complication
>+ * are the lookup caches for import and export. These are required to guarantee
>+ * that any given object will always have only one uniqe userspace handle. This
>+ * is required to allow userspace to detect duplicated imports, since some GEM
>+ * drivers do fail command submissions if a given buffer object is listed more
>+ * than once. These import and export caches in &drm_prime_file_private only
>+ * retain a weak reference, which is cleaned up when the corresponding object is
>+ * released.
>+ *
>+ * Self-importing: If userspace is using PRIME as a replacement for flink then
>+ * it will get a fd->handle request for a GEM object that it created.  Drivers
>+ * should detect this situation and return back the underlying object from the
>+ * dma-buf private. For GEM based drivers this is handled in
>+ * drm_gem_prime_import() already.
>  */
> 
> struct drm_prime_member {
>@@ -181,42 +187,6 @@
> 	return -ENOENT;
> }
> 
>-/**
>- * drm_gem_map_attach - dma_buf attach implementation for GEM
>- * @dma_buf: buffer to attach device to
>- * @attach: buffer attachment data
>- *
>- * Calls &drm_driver.gem_prime_pin for device specific handling. This can be
>- * used as the &dma_buf_ops.attach callback.
>- *
>- * Returns 0 on success, negative error code on failure.
>- */
>-int drm_gem_map_attach(struct dma_buf *dma_buf,
>-		       struct dma_buf_attachment *attach)
>-{
>-	struct drm_gem_object *obj = dma_buf->priv;
>-
>-	return drm_gem_pin(obj);
>-}
>-EXPORT_SYMBOL(drm_gem_map_attach);
>-
>-/**
>- * drm_gem_map_detach - dma_buf detach implementation for GEM
>- * @dma_buf: buffer to detach from
>- * @attach: attachment to be detached
>- *
>- * Cleans up &dma_buf_attachment. This can be used as the &dma_buf_ops.detach
>- * callback.
>- */
>-void drm_gem_map_detach(struct dma_buf *dma_buf,
>-			struct dma_buf_attachment *attach)
>-{
>-	struct drm_gem_object *obj = dma_buf->priv;
>-
>-	drm_gem_unpin(obj);
>-}
>-EXPORT_SYMBOL(drm_gem_map_detach);
>-
> void drm_prime_remove_buf_handle_locked(struct drm_prime_file_private *prime_fpriv,
> 					struct dma_buf *dma_buf)
> {
>@@ -242,67 +212,21 @@
> 	}
> }
> 
>-/**
>- * drm_gem_map_dma_buf - map_dma_buf implementation for GEM
>- * @attach: attachment whose scatterlist is to be returned
>- * @dir: direction of DMA transfer
>- *
>- * Calls &drm_driver.gem_prime_get_sg_table and then maps the scatterlist. This
>- * can be used as the &dma_buf_ops.map_dma_buf callback.
>- *
>- * Returns sg_table containing the scatterlist to be returned; returns ERR_PTR
>- * on error. May return -EINTR if it is interrupted by a signal.
>- */
>-
>-struct sg_table *drm_gem_map_dma_buf(struct dma_buf_attachment *attach,
>-				     enum dma_data_direction dir)
>+void drm_prime_init_file_private(struct drm_prime_file_private *prime_fpriv)
> {
>-	struct drm_gem_object *obj = attach->dmabuf->priv;
>-	struct sg_table *sgt;
>-
>-	if (WARN_ON(dir == DMA_NONE))
>-		return ERR_PTR(-EINVAL);
>-
>-	if (obj->funcs)
>-		sgt = obj->funcs->get_sg_table(obj);
>-	else
>-		sgt = obj->dev->driver->gem_prime_get_sg_table(obj);
>-
>-	if (!dma_map_sg_attrs(attach->dev, sgt->sgl, sgt->nents, dir,
>-			      DMA_ATTR_SKIP_CPU_SYNC)) {
>-		sg_free_table(sgt);
>-		kfree(sgt);
>-		sgt = ERR_PTR(-ENOMEM);
>-	}
>-
>-	return sgt;
>+	mutex_init(&prime_fpriv->lock);
>+	prime_fpriv->dmabufs = RB_ROOT;
>+	prime_fpriv->handles = RB_ROOT;
> }
>-EXPORT_SYMBOL(drm_gem_map_dma_buf);
> 
>-/**
>- * drm_gem_unmap_dma_buf - unmap_dma_buf implementation for GEM
>- * @attach: attachment to unmap buffer from
>- * @sgt: scatterlist info of the buffer to unmap
>- * @dir: direction of DMA transfer
>- *
>- * This can be used as the &dma_buf_ops.unmap_dma_buf callback.
>- */
>-void drm_gem_unmap_dma_buf(struct dma_buf_attachment *attach,
>-			   struct sg_table *sgt,
>-			   enum dma_data_direction dir)
>+void drm_prime_destroy_file_private(struct drm_prime_file_private *prime_fpriv)
> {
>-	if (!sgt)
>-		return;
>-
>-	dma_unmap_sg_attrs(attach->dev, sgt->sgl, sgt->nents, dir,
>-			   DMA_ATTR_SKIP_CPU_SYNC);
>-	sg_free_table(sgt);
>-	kfree(sgt);
>+	/* by now drm_gem_release should've made sure the list is empty */
>+	WARN_ON(!RB_EMPTY_ROOT(&prime_fpriv->dmabufs));
> }
>-EXPORT_SYMBOL(drm_gem_unmap_dma_buf);
> 
> /**
>- * drm_gem_dmabuf_export - dma_buf export implementation for GEM
>+ * drm_gem_dmabuf_export - &dma_buf export implementation for GEM
>  * @dev: parent device for the exported dmabuf
>  * @exp_info: the export information used by dma_buf_export()
>  *
>@@ -330,11 +254,11 @@
> EXPORT_SYMBOL(drm_gem_dmabuf_export);
> 
> /**
>- * drm_gem_dmabuf_release - dma_buf release implementation for GEM
>+ * drm_gem_dmabuf_release - &dma_buf release implementation for GEM
>  * @dma_buf: buffer to be released
>  *
>  * Generic release function for dma_bufs exported as PRIME buffers. GEM drivers
>- * must use this in their dma_buf ops structure as the release callback.
>+ * must use this in their &dma_buf_ops structure as the release callback.
>  * drm_gem_dmabuf_release() should be used in conjunction with
>  * drm_gem_dmabuf_export().
>  */
>@@ -351,128 +275,100 @@
> EXPORT_SYMBOL(drm_gem_dmabuf_release);
> 
> /**
>- * drm_gem_dmabuf_vmap - dma_buf vmap implementation for GEM
>- * @dma_buf: buffer to be mapped
>+ * drm_gem_prime_fd_to_handle - PRIME import function for GEM drivers
>+ * @dev: dev to export the buffer from
>+ * @file_priv: drm file-private structure
>+ * @prime_fd: fd id of the dma-buf which should be imported
>+ * @handle: pointer to storage for the handle of the imported buffer object
>  *
>- * Sets up a kernel virtual mapping. This can be used as the &dma_buf_ops.vmap
>- * callback.
>+ * This is the PRIME import function which must be used mandatorily by GEM
>+ * drivers to ensure correct lifetime management of the underlying GEM object.
>+ * The actual importing of GEM object from the dma-buf is done through the
>+ * &drm_driver.gem_prime_import driver callback.
>  *
>- * Returns the kernel virtual address.
>+ * Returns 0 on success or a negative error code on failure.
>  */
>-void *drm_gem_dmabuf_vmap(struct dma_buf *dma_buf)
>+int drm_gem_prime_fd_to_handle(struct drm_device *dev,
>+			       struct drm_file *file_priv, int prime_fd,
>+			       uint32_t *handle)
> {
>-	struct drm_gem_object *obj = dma_buf->priv;
>-	void *vaddr;
>+	struct dma_buf *dma_buf;
>+	struct drm_gem_object *obj;
>+	int ret;
> 
>-	vaddr = drm_gem_vmap(obj);
>-	if (IS_ERR(vaddr))
>-		vaddr = NULL;
>+	dma_buf = dma_buf_get(prime_fd);
>+	if (IS_ERR(dma_buf))
>+		return PTR_ERR(dma_buf);
> 
>-	return vaddr;
>-}
>-EXPORT_SYMBOL(drm_gem_dmabuf_vmap);
>+	mutex_lock(&file_priv->prime.lock);
> 
>-/**
>- * drm_gem_dmabuf_vunmap - dma_buf vunmap implementation for GEM
>- * @dma_buf: buffer to be unmapped
>- * @vaddr: the virtual address of the buffer
>- *
>- * Releases a kernel virtual mapping. This can be used as the
>- * &dma_buf_ops.vunmap callback.
>- */
>-void drm_gem_dmabuf_vunmap(struct dma_buf *dma_buf, void *vaddr)
>-{
>-	struct drm_gem_object *obj = dma_buf->priv;
>+	ret = drm_prime_lookup_buf_handle(&file_priv->prime,
>+			dma_buf, handle);
>+	if (ret == 0)
>+		goto out_put;
> 
>-	drm_gem_vunmap(obj, vaddr);
>-}
>-EXPORT_SYMBOL(drm_gem_dmabuf_vunmap);
>+	/* never seen this one, need to import */
>+	mutex_lock(&dev->object_name_lock);
>+	if (dev->driver->gem_prime_import)
>+		obj = dev->driver->gem_prime_import(dev, dma_buf);
>+	else
>+		obj = drm_gem_prime_import(dev, dma_buf);
>+	if (IS_ERR(obj)) {
>+		ret = PTR_ERR(obj);
>+		goto out_unlock;
>+	}
> 
>-/**
>- * drm_gem_dmabuf_mmap - dma_buf mmap implementation for GEM
>- * @dma_buf: buffer to be mapped
>- * @vma: virtual address range
>- *
>- * Provides memory mapping for the buffer. This can be used as the
>- * &dma_buf_ops.mmap callback.
>- *
>- * Returns 0 on success or a negative error code on failure.
>- */
>-int drm_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma)
>-{
>-	struct drm_gem_object *obj = dma_buf->priv;
>-	struct drm_device *dev = obj->dev;
>+	if (obj->dma_buf) {
>+		WARN_ON(obj->dma_buf != dma_buf);
>+	} else {
>+		obj->dma_buf = dma_buf;
>+		get_dma_buf(dma_buf);
>+	}
> 
>-	if (!dev->driver->gem_prime_mmap)
>-		return -ENOSYS;
>+	/* _handle_create_tail unconditionally unlocks dev->object_name_lock. */
>+	ret = drm_gem_handle_create_tail(file_priv, obj, handle);
>+	drm_gem_object_put_unlocked(obj);
>+	if (ret)
>+		goto out_put;
> 
>-	return dev->driver->gem_prime_mmap(obj, vma);
>-}
>-EXPORT_SYMBOL(drm_gem_dmabuf_mmap);
>+	ret = drm_prime_add_buf_handle(&file_priv->prime,
>+			dma_buf, *handle);
>+	mutex_unlock(&file_priv->prime.lock);
>+	if (ret)
>+		goto fail;
> 
>-static const struct dma_buf_ops drm_gem_prime_dmabuf_ops =  {
>-	.cache_sgt_mapping = true,
>-	.attach = drm_gem_map_attach,
>-	.detach = drm_gem_map_detach,
>-	.map_dma_buf = drm_gem_map_dma_buf,
>-	.unmap_dma_buf = drm_gem_unmap_dma_buf,
>-	.release = drm_gem_dmabuf_release,
>-	.mmap = drm_gem_dmabuf_mmap,
>-	.vmap = drm_gem_dmabuf_vmap,
>-	.vunmap = drm_gem_dmabuf_vunmap,
>-};
>+	dma_buf_put(dma_buf);
> 
>-/**
>- * DOC: PRIME Helpers
>- *
>- * Drivers can implement @gem_prime_export and @gem_prime_import in terms of
>- * simpler APIs by using the helper functions @drm_gem_prime_export and
>- * @drm_gem_prime_import.  These functions implement dma-buf support in terms of
>- * six lower-level driver callbacks:
>- *
>- * Export callbacks:
>- *
>- *  * @gem_prime_pin (optional): prepare a GEM object for exporting
>- *  * @gem_prime_get_sg_table: provide a scatter/gather table of pinned pages
>- *  * @gem_prime_vmap: vmap a buffer exported by your driver
>- *  * @gem_prime_vunmap: vunmap a buffer exported by your driver
>- *  * @gem_prime_mmap (optional): mmap a buffer exported by your driver
>- *
>- * Import callback:
>- *
>- *  * @gem_prime_import_sg_table (import): produce a GEM object from another
>- *    driver's scatter/gather table
>- */
>+	return 0;
> 
>-/**
>- * drm_gem_prime_export - helper library implementation of the export callback
>- * @dev: drm_device to export from
>- * @obj: GEM object to export
>- * @flags: flags like DRM_CLOEXEC and DRM_RDWR
>- *
>- * This is the implementation of the gem_prime_export functions for GEM drivers
>- * using the PRIME helpers.
>- */
>-struct dma_buf *drm_gem_prime_export(struct drm_device *dev,
>-				     struct drm_gem_object *obj,
>-				     int flags)
>+fail:
>+	/* hmm, if driver attached, we are relying on the free-object path
>+	 * to detach.. which seems ok..
>+	 */
>+	drm_gem_handle_delete(file_priv, *handle);
>+	dma_buf_put(dma_buf);
>+	return ret;
>+
>+out_unlock:
>+	mutex_unlock(&dev->object_name_lock);
>+out_put:
>+	mutex_unlock(&file_priv->prime.lock);
>+	dma_buf_put(dma_buf);
>+	return ret;
>+}
>+EXPORT_SYMBOL(drm_gem_prime_fd_to_handle);
>+
>+int drm_prime_fd_to_handle_ioctl(struct drm_device *dev, void *data,
>+				 struct drm_file *file_priv)
> {
>-	struct dma_buf_export_info exp_info = {
>-		.exp_name = KBUILD_MODNAME, /* white lie for debug */
>-		.owner = dev->driver->fops->owner,
>-		.ops = &drm_gem_prime_dmabuf_ops,
>-		.size = obj->size,
>-		.flags = flags,
>-		.priv = obj,
>-		.resv = obj->resv,
>-	};
>+	struct drm_prime_handle *args = data;
> 
>-	if (dev->driver->gem_prime_res_obj)
>-		exp_info.resv = dev->driver->gem_prime_res_obj(obj);
>+	if (!dev->driver->prime_fd_to_handle)
>+		return -ENOSYS;
> 
>-	return drm_gem_dmabuf_export(dev, &exp_info);
>+	return dev->driver->prime_fd_to_handle(dev, file_priv,
>+			args->fd, &args->handle);
> }
>-EXPORT_SYMBOL(drm_gem_prime_export);
> 
> static struct dma_buf *export_and_register_object(struct drm_device *dev,
> 						  struct drm_gem_object *obj,
>@@ -489,9 +385,9 @@
> 	if (obj->funcs && obj->funcs->export)
> 		dmabuf = obj->funcs->export(obj, flags);
> 	else if (dev->driver->gem_prime_export)
>-		dmabuf = dev->driver->gem_prime_export(dev, obj, flags);
>+		dmabuf = dev->driver->gem_prime_export(obj, flags);
> 	else
>-		dmabuf = drm_gem_prime_export(dev, obj, flags);
>+		dmabuf = drm_gem_prime_export(obj, flags);
> 	if (IS_ERR(dmabuf)) {
> 		/* normally the created dma-buf takes ownership of the ref,
> 		 * but if that fails then drop the ref
>@@ -521,7 +417,7 @@
>  * This is the PRIME export function which must be used mandatorily by GEM
>  * drivers to ensure correct lifetime management of the underlying GEM object.
>  * The actual exporting from GEM object to a dma-buf is done through the
>- * gem_prime_export driver callback.
>+ * &drm_driver.gem_prime_export driver callback.
>  */
> int drm_gem_prime_handle_to_fd(struct drm_device *dev,
> 			       struct drm_file *file_priv, uint32_t handle,
>@@ -610,6 +506,195 @@
> }
> EXPORT_SYMBOL(drm_gem_prime_handle_to_fd);
> 
>+int drm_prime_handle_to_fd_ioctl(struct drm_device *dev, void *data,
>+				 struct drm_file *file_priv)
>+{
>+	struct drm_prime_handle *args = data;
>+
>+	if (!dev->driver->prime_handle_to_fd)
>+		return -ENOSYS;
>+
>+	/* check flags are valid */
>+	if (args->flags & ~(DRM_CLOEXEC | DRM_RDWR))
>+		return -EINVAL;
>+
>+	return dev->driver->prime_handle_to_fd(dev, file_priv,
>+			args->handle, args->flags, &args->fd);
>+}
>+
>+/**
>+ * DOC: PRIME Helpers
>+ *
>+ * Drivers can implement &drm_gem_object_funcs.export and
>+ * &drm_driver.gem_prime_import in terms of simpler APIs by using the helper
>+ * functions drm_gem_prime_export() and drm_gem_prime_import(). These functions
>+ * implement dma-buf support in terms of some lower-level helpers, which are
>+ * again exported for drivers to use individually:
>+ *
>+ * Exporting buffers
>+ * ~~~~~~~~~~~~~~~~~
>+ *
>+ * Optional pinning of buffers is handled at dma-buf attach and detach time in
>+ * drm_gem_map_attach() and drm_gem_map_detach(). Backing storage itself is
>+ * handled by drm_gem_map_dma_buf() and drm_gem_unmap_dma_buf(), which relies on
>+ * &drm_gem_object_funcs.get_sg_table.
>+ *
>+ * For kernel-internal access there's drm_gem_dmabuf_vmap() and
>+ * drm_gem_dmabuf_vunmap(). Userspace mmap support is provided by
>+ * drm_gem_dmabuf_mmap().
>+ *
>+ * Note that these export helpers can only be used if the underlying backing
>+ * storage is fully coherent and either permanently pinned, or it is safe to pin
>+ * it indefinitely.
>+ *
>+ * FIXME: The underlying helper functions are named rather inconsistently.
>+ *
>+ * Exporting buffers
>+ * ~~~~~~~~~~~~~~~~~
>+ *
>+ * Importing dma-bufs using drm_gem_prime_import() relies on
>+ * &drm_driver.gem_prime_import_sg_table.
>+ *
>+ * Note that similarly to the export helpers this permanently pins the
>+ * underlying backing storage. Which is ok for scanout, but is not the best
>+ * option for sharing lots of buffers for rendering.
>+ */
>+
>+/**
>+ * drm_gem_map_attach - dma_buf attach implementation for GEM
>+ * @dma_buf: buffer to attach device to
>+ * @attach: buffer attachment data
>+ *
>+ * Calls &drm_gem_object_funcs.pin for device specific handling. This can be
>+ * used as the &dma_buf_ops.attach callback. Must be used together with
>+ * drm_gem_map_detach().
>+ *
>+ * Returns 0 on success, negative error code on failure.
>+ */
>+int drm_gem_map_attach(struct dma_buf *dma_buf,
>+		       struct dma_buf_attachment *attach)
>+{
>+	struct drm_gem_object *obj = dma_buf->priv;
>+
>+	return drm_gem_pin(obj);
>+}
>+EXPORT_SYMBOL(drm_gem_map_attach);
>+
>+/**
>+ * drm_gem_map_detach - dma_buf detach implementation for GEM
>+ * @dma_buf: buffer to detach from
>+ * @attach: attachment to be detached
>+ *
>+ * Calls &drm_gem_object_funcs.pin for device specific handling.  Cleans up
>+ * &dma_buf_attachment from drm_gem_map_attach(). This can be used as the
>+ * &dma_buf_ops.detach callback.
>+ */
>+void drm_gem_map_detach(struct dma_buf *dma_buf,
>+			struct dma_buf_attachment *attach)
>+{
>+	struct drm_gem_object *obj = dma_buf->priv;
>+
>+	drm_gem_unpin(obj);
>+}
>+EXPORT_SYMBOL(drm_gem_map_detach);
>+
>+/**
>+ * drm_gem_map_dma_buf - map_dma_buf implementation for GEM
>+ * @attach: attachment whose scatterlist is to be returned
>+ * @dir: direction of DMA transfer
>+ *
>+ * Calls &drm_gem_object_funcs.get_sg_table and then maps the scatterlist. This
>+ * can be used as the &dma_buf_ops.map_dma_buf callback. Should be used together
>+ * with drm_gem_unmap_dma_buf().
>+ *
>+ * Returns:sg_table containing the scatterlist to be returned; returns ERR_PTR
>+ * on error. May return -EINTR if it is interrupted by a signal.
>+ */
>+struct sg_table *drm_gem_map_dma_buf(struct dma_buf_attachment *attach,
>+				     enum dma_data_direction dir)
>+{
>+	struct drm_gem_object *obj = attach->dmabuf->priv;
>+	struct sg_table *sgt;
>+
>+	if (WARN_ON(dir == DMA_NONE))
>+		return ERR_PTR(-EINVAL);
>+
>+	if (obj->funcs)
>+		sgt = obj->funcs->get_sg_table(obj);
>+	else
>+		sgt = obj->dev->driver->gem_prime_get_sg_table(obj);
>+
>+	if (!dma_map_sg_attrs(attach->dev, sgt->sgl, sgt->nents, dir,
>+			      DMA_ATTR_SKIP_CPU_SYNC)) {
>+		sg_free_table(sgt);
>+		kfree(sgt);
>+		sgt = ERR_PTR(-ENOMEM);
>+	}
>+
>+	return sgt;
>+}
>+EXPORT_SYMBOL(drm_gem_map_dma_buf);
>+
>+/**
>+ * drm_gem_unmap_dma_buf - unmap_dma_buf implementation for GEM
>+ * @attach: attachment to unmap buffer from
>+ * @sgt: scatterlist info of the buffer to unmap
>+ * @dir: direction of DMA transfer
>+ *
>+ * This can be used as the &dma_buf_ops.unmap_dma_buf callback.
>+ */
>+void drm_gem_unmap_dma_buf(struct dma_buf_attachment *attach,
>+			   struct sg_table *sgt,
>+			   enum dma_data_direction dir)
>+{
>+	if (!sgt)
>+		return;
>+
>+	dma_unmap_sg_attrs(attach->dev, sgt->sgl, sgt->nents, dir,
>+			   DMA_ATTR_SKIP_CPU_SYNC);
>+	sg_free_table(sgt);
>+	kfree(sgt);
>+}
>+EXPORT_SYMBOL(drm_gem_unmap_dma_buf);
>+
>+/**
>+ * drm_gem_dmabuf_vmap - dma_buf vmap implementation for GEM
>+ * @dma_buf: buffer to be mapped
>+ *
>+ * Sets up a kernel virtual mapping. This can be used as the &dma_buf_ops.vmap
>+ * callback. Calls into &drm_gem_object_funcs.vmap for device specific handling.
>+ *
>+ * Returns the kernel virtual address or NULL on failure.
>+ */
>+void *drm_gem_dmabuf_vmap(struct dma_buf *dma_buf)
>+{
>+	struct drm_gem_object *obj = dma_buf->priv;
>+	void *vaddr;
>+
>+	vaddr = drm_gem_vmap(obj);
>+	if (IS_ERR(vaddr))
>+		vaddr = NULL;
>+
>+	return vaddr;
>+}
>+EXPORT_SYMBOL(drm_gem_dmabuf_vmap);
>+
>+/**
>+ * drm_gem_dmabuf_vunmap - dma_buf vunmap implementation for GEM
>+ * @dma_buf: buffer to be unmapped
>+ * @vaddr: the virtual address of the buffer
>+ *
>+ * Releases a kernel virtual mapping. This can be used as the
>+ * &dma_buf_ops.vunmap callback. Calls into &drm_gem_object_funcs.vunmap for device specific handling.
>+ */
>+void drm_gem_dmabuf_vunmap(struct dma_buf *dma_buf, void *vaddr)
>+{
>+	struct drm_gem_object *obj = dma_buf->priv;
>+
>+	drm_gem_vunmap(obj, vaddr);
>+}
>+EXPORT_SYMBOL(drm_gem_dmabuf_vunmap);
>+
> /**
>  * drm_gem_prime_mmap - PRIME mmap function for GEM drivers
>  * @obj: GEM object
>@@ -657,14 +742,117 @@
> EXPORT_SYMBOL(drm_gem_prime_mmap);
> 
> /**
>+ * drm_gem_dmabuf_mmap - dma_buf mmap implementation for GEM
>+ * @dma_buf: buffer to be mapped
>+ * @vma: virtual address range
>+ *
>+ * Provides memory mapping for the buffer. This can be used as the
>+ * &dma_buf_ops.mmap callback. It just forwards to &drm_driver.gem_prime_mmap,
>+ * which should be set to drm_gem_prime_mmap().
>+ *
>+ * FIXME: There's really no point to this wrapper, drivers which need anything
>+ * else but drm_gem_prime_mmap can roll their own &dma_buf_ops.mmap callback.
>+ *
>+ * Returns 0 on success or a negative error code on failure.
>+ */
>+int drm_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma)
>+{
>+	struct drm_gem_object *obj = dma_buf->priv;
>+	struct drm_device *dev = obj->dev;
>+
>+	if (!dev->driver->gem_prime_mmap)
>+		return -ENOSYS;
>+
>+	return dev->driver->gem_prime_mmap(obj, vma);
>+}
>+EXPORT_SYMBOL(drm_gem_dmabuf_mmap);
>+
>+static const struct dma_buf_ops drm_gem_prime_dmabuf_ops =  {
>+	.cache_sgt_mapping = true,
>+	.attach = drm_gem_map_attach,
>+	.detach = drm_gem_map_detach,
>+	.map_dma_buf = drm_gem_map_dma_buf,
>+	.unmap_dma_buf = drm_gem_unmap_dma_buf,
>+	.release = drm_gem_dmabuf_release,
>+	.mmap = drm_gem_dmabuf_mmap,
>+	.vmap = drm_gem_dmabuf_vmap,
>+	.vunmap = drm_gem_dmabuf_vunmap,
>+};
>+
>+/**
>+ * drm_prime_pages_to_sg - converts a page array into an sg list
>+ * @pages: pointer to the array of page pointers to convert
>+ * @nr_pages: length of the page vector
>+ *
>+ * This helper creates an sg table object from a set of pages
>+ * the driver is responsible for mapping the pages into the
>+ * importers address space for use with dma_buf itself.
>+ *
>+ * This is useful for implementing &drm_gem_object_funcs.get_sg_table.
>+ */
>+struct sg_table *drm_prime_pages_to_sg(struct page **pages, unsigned int nr_pages)
>+{
>+	struct sg_table *sg = NULL;
>+	int ret;
>+
>+	sg = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
>+	if (!sg) {
>+		ret = -ENOMEM;
>+		goto out;
>+	}
>+
>+	ret = sg_alloc_table_from_pages(sg, pages, nr_pages, 0,
>+				nr_pages << PAGE_SHIFT, GFP_KERNEL);
>+	if (ret)
>+		goto out;
>+
>+	return sg;
>+out:
>+	kfree(sg);
>+	return ERR_PTR(ret);
>+}
>+EXPORT_SYMBOL(drm_prime_pages_to_sg);
>+
>+/**
>+ * drm_gem_prime_export - helper library implementation of the export callback
>+ * @obj: GEM object to export
>+ * @flags: flags like DRM_CLOEXEC and DRM_RDWR
>+ *
>+ * This is the implementation of the &drm_gem_object_funcs.export functions for GEM drivers
>+ * using the PRIME helpers. It is used as the default in
>+ * drm_gem_prime_handle_to_fd().
>+ */
>+struct dma_buf *drm_gem_prime_export(struct drm_gem_object *obj,
>+				     int flags)
>+{
>+	struct drm_device *dev = obj->dev;
>+	struct dma_buf_export_info exp_info = {
>+		.exp_name = KBUILD_MODNAME, /* white lie for debug */
>+		.owner = dev->driver->fops->owner,
>+		.ops = &drm_gem_prime_dmabuf_ops,
>+		.size = obj->size,
>+		.flags = flags,
>+		.priv = obj,
>+		.resv = obj->resv,
>+	};
>+
>+	return drm_gem_dmabuf_export(dev, &exp_info);
>+}
>+EXPORT_SYMBOL(drm_gem_prime_export);
>+
>+/**
>  * drm_gem_prime_import_dev - core implementation of the import callback
>  * @dev: drm_device to import into
>  * @dma_buf: dma-buf object to import
>  * @attach_dev: struct device to dma_buf attach
>  *
>- * This is the core of drm_gem_prime_import. It's designed to be called by
>- * drivers who want to use a different device structure than dev->dev for
>- * attaching via dma_buf.
>+ * This is the core of drm_gem_prime_import(). It's designed to be called by
>+ * drivers who want to use a different device structure than &drm_device.dev for
>+ * attaching via dma_buf. This function calls
>+ * &drm_driver.gem_prime_import_sg_table internally.
>+ *
>+ * Drivers must arrange to call drm_prime_gem_destroy() from their
>+ * &drm_gem_object_funcs.free hook when using this function.
>  */
> struct drm_gem_object *drm_gem_prime_import_dev(struct drm_device *dev,
> 					    struct dma_buf *dma_buf,
>@@ -709,6 +897,7 @@
> 	}
> 
> 	obj->import_attach = attach;
>+	obj->resv = dma_buf->resv;
> 
> 	return obj;
> 
>@@ -728,7 +917,12 @@
>  * @dma_buf: dma-buf object to import
>  *
>  * This is the implementation of the gem_prime_import functions for GEM drivers
>- * using the PRIME helpers.
>+ * using the PRIME helpers. Drivers can use this as their
>+ * &drm_driver.gem_prime_import implementation. It is used as the default
>+ * implementation in drm_gem_prime_fd_to_handle().
>+ *
>+ * Drivers must arrange to call drm_prime_gem_destroy() from their
>+ * &drm_gem_object_funcs.free hook when using this function.
>  */
> struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev,
> 					    struct dma_buf *dma_buf)
>@@ -738,154 +932,6 @@
> EXPORT_SYMBOL(drm_gem_prime_import);
> 
> /**
>- * drm_gem_prime_fd_to_handle - PRIME import function for GEM drivers
>- * @dev: dev to export the buffer from
>- * @file_priv: drm file-private structure
>- * @prime_fd: fd id of the dma-buf which should be imported
>- * @handle: pointer to storage for the handle of the imported buffer object
>- *
>- * This is the PRIME import function which must be used mandatorily by GEM
>- * drivers to ensure correct lifetime management of the underlying GEM object.
>- * The actual importing of GEM object from the dma-buf is done through the
>- * gem_import_export driver callback.
>- */
>-int drm_gem_prime_fd_to_handle(struct drm_device *dev,
>-			       struct drm_file *file_priv, int prime_fd,
>-			       uint32_t *handle)
>-{
>-	struct dma_buf *dma_buf;
>-	struct drm_gem_object *obj;
>-	int ret;
>-
>-	dma_buf = dma_buf_get(prime_fd);
>-	if (IS_ERR(dma_buf))
>-		return PTR_ERR(dma_buf);
>-
>-	mutex_lock(&file_priv->prime.lock);
>-
>-	ret = drm_prime_lookup_buf_handle(&file_priv->prime,
>-			dma_buf, handle);
>-	if (ret == 0)
>-		goto out_put;
>-
>-	/* never seen this one, need to import */
>-	mutex_lock(&dev->object_name_lock);
>-	if (dev->driver->gem_prime_import)
>-		obj = dev->driver->gem_prime_import(dev, dma_buf);
>-	else
>-		obj = drm_gem_prime_import(dev, dma_buf);
>-	if (IS_ERR(obj)) {
>-		ret = PTR_ERR(obj);
>-		goto out_unlock;
>-	}
>-
>-	if (obj->dma_buf) {
>-		WARN_ON(obj->dma_buf != dma_buf);
>-	} else {
>-		obj->dma_buf = dma_buf;
>-		get_dma_buf(dma_buf);
>-	}
>-
>-	/* _handle_create_tail unconditionally unlocks dev->object_name_lock. */
>-	ret = drm_gem_handle_create_tail(file_priv, obj, handle);
>-	drm_gem_object_put_unlocked(obj);
>-	if (ret)
>-		goto out_put;
>-
>-	ret = drm_prime_add_buf_handle(&file_priv->prime,
>-			dma_buf, *handle);
>-	mutex_unlock(&file_priv->prime.lock);
>-	if (ret)
>-		goto fail;
>-
>-	dma_buf_put(dma_buf);
>-
>-	return 0;
>-
>-fail:
>-	/* hmm, if driver attached, we are relying on the free-object path
>-	 * to detach.. which seems ok..
>-	 */
>-	drm_gem_handle_delete(file_priv, *handle);
>-	dma_buf_put(dma_buf);
>-	return ret;
>-
>-out_unlock:
>-	mutex_unlock(&dev->object_name_lock);
>-out_put:
>-	mutex_unlock(&file_priv->prime.lock);
>-	dma_buf_put(dma_buf);
>-	return ret;
>-}
>-EXPORT_SYMBOL(drm_gem_prime_fd_to_handle);
>-
>-int drm_prime_handle_to_fd_ioctl(struct drm_device *dev, void *data,
>-				 struct drm_file *file_priv)
>-{
>-	struct drm_prime_handle *args = data;
>-
>-	if (!drm_core_check_feature(dev, DRIVER_PRIME))
>-		return -EOPNOTSUPP;
>-
>-	if (!dev->driver->prime_handle_to_fd)
>-		return -ENOSYS;
>-
>-	/* check flags are valid */
>-	if (args->flags & ~(DRM_CLOEXEC | DRM_RDWR))
>-		return -EINVAL;
>-
>-	return dev->driver->prime_handle_to_fd(dev, file_priv,
>-			args->handle, args->flags, &args->fd);
>-}
>-
>-int drm_prime_fd_to_handle_ioctl(struct drm_device *dev, void *data,
>-				 struct drm_file *file_priv)
>-{
>-	struct drm_prime_handle *args = data;
>-
>-	if (!drm_core_check_feature(dev, DRIVER_PRIME))
>-		return -EOPNOTSUPP;
>-
>-	if (!dev->driver->prime_fd_to_handle)
>-		return -ENOSYS;
>-
>-	return dev->driver->prime_fd_to_handle(dev, file_priv,
>-			args->fd, &args->handle);
>-}
>-
>-/**
>- * drm_prime_pages_to_sg - converts a page array into an sg list
>- * @pages: pointer to the array of page pointers to convert
>- * @nr_pages: length of the page vector
>- *
>- * This helper creates an sg table object from a set of pages
>- * the driver is responsible for mapping the pages into the
>- * importers address space for use with dma_buf itself.
>- */
>-struct sg_table *drm_prime_pages_to_sg(struct page **pages, unsigned int nr_pages)
>-{
>-	struct sg_table *sg = NULL;
>-	int ret;
>-
>-	sg = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
>-	if (!sg) {
>-		ret = -ENOMEM;
>-		goto out;
>-	}
>-
>-	ret = sg_alloc_table_from_pages(sg, pages, nr_pages, 0,
>-				nr_pages << PAGE_SHIFT, GFP_KERNEL);
>-	if (ret)
>-		goto out;
>-
>-	return sg;
>-out:
>-	kfree(sg);
>-	return ERR_PTR(ret);
>-}
>-EXPORT_SYMBOL(drm_prime_pages_to_sg);
>-
>-/**
>  * drm_prime_sg_to_page_addr_arrays - convert an sg table into a page array
>  * @sgt: scatter-gather table to convert
>  * @pages: optional array of page pointers to store the page array in
>@@ -894,6 +940,9 @@
>  *
>  * Exports an sg table into an array of pages and addresses. This is currently
>  * required by the TTM driver in order to do correct fault handling.
>+ *
>+ * Drivers can use this in their &drm_driver.gem_prime_import_sg_table
>+ * implementation.
>  */
> int drm_prime_sg_to_page_addr_arrays(struct sg_table *sgt, struct page **pages,
> 				     dma_addr_t *addrs, int max_entries)
>@@ -934,7 +983,7 @@
>  * @sg: the sg-table which was pinned at import time
>  *
>  * This is the cleanup functions which GEM drivers need to call when they use
>- * @drm_gem_prime_import to import dma-bufs.
>+ * drm_gem_prime_import() or drm_gem_prime_import_dev() to import dma-bufs.
>  */
> void drm_prime_gem_destroy(struct drm_gem_object *obj, struct sg_table *sg)
> {
>@@ -949,16 +998,3 @@
> 	dma_buf_put(dma_buf);
> }
> EXPORT_SYMBOL(drm_prime_gem_destroy);
>-
>-void drm_prime_init_file_private(struct drm_prime_file_private *prime_fpriv)
>-{
>-	mutex_init(&prime_fpriv->lock);
>-	prime_fpriv->dmabufs = RB_ROOT;
>-	prime_fpriv->handles = RB_ROOT;
>-}
>-
>-void drm_prime_destroy_file_private(struct drm_prime_file_private *prime_fpriv)
>-{
>-	/* by now drm_gem_release should've made sure the list is empty */
>-	WARN_ON(!RB_EMPTY_ROOT(&prime_fpriv->dmabufs));
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_scatter.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_scatter.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_scatter.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_scatter.c	2019-08-31 15:01:11.946736176 -0500
>@@ -1,4 +1,4 @@
>-/**
>+/*
>  * \file drm_scatter.c
>  * IOCTLs to manage scatter/gather memory
>  *
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_syncobj.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_syncobj.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_syncobj.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_syncobj.c	2019-08-31 15:01:11.946736176 -0500
>@@ -53,6 +53,7 @@
> #include <linux/sync_file.h>
> #include <linux/uaccess.h>
> 
>+#include <drm/drm.h>
> #include <drm/drm_drv.h>
> #include <drm/drm_file.h>
> #include <drm/drm_gem.h>
>@@ -1297,14 +1298,14 @@
> 			struct dma_fence *iter, *last_signaled = NULL;
> 
> 			dma_fence_chain_for_each(iter, fence) {
>-				if (!iter)
>-					break;
>-				dma_fence_put(last_signaled);
>-				last_signaled = dma_fence_get(iter);
>-				if (!to_dma_fence_chain(last_signaled)->prev_seqno)
>+				if (iter->context != fence->context) {
>+					dma_fence_put(iter);
> 					/* It is most likely that timeline has
> 					 * unorder points. */
> 					break;
>+				}
>+				dma_fence_put(last_signaled);
>+				last_signaled = dma_fence_get(iter);
> 			}
> 			point = dma_fence_is_signaled(last_signaled) ?
> 				last_signaled->seqno :
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_sysfs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_sysfs.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_sysfs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_sysfs.c	2019-08-31 15:01:11.946736176 -0500
>@@ -14,6 +14,7 @@
> #include <linux/err.h>
> #include <linux/export.h>
> #include <linux/gfp.h>
>+#include <linux/i2c.h>
> #include <linux/kdev_t.h>
> #include <linux/slab.h>
> 
>@@ -26,6 +27,7 @@
> #include <drm/drm_sysfs.h>
> 
> #include "drm_internal.h"
>+#include "drm_crtc_internal.h"
> 
> #define to_drm_minor(d) dev_get_drvdata(d)
> #define to_drm_connector(d) dev_get_drvdata(d)
>@@ -294,6 +296,9 @@
> 	/* Let userspace know we have a new connector */
> 	drm_sysfs_hotplug_event(dev);
> 
>+	if (connector->ddc)
>+		return sysfs_create_link(&connector->kdev->kobj,
>+				 &connector->ddc->dev.kobj, "ddc");
> 	return 0;
> }
> 
>@@ -301,6 +306,10 @@
> {
> 	if (!connector->kdev)
> 		return;
>+
>+	if (connector->ddc)
>+		sysfs_remove_link(&connector->kdev->kobj, "ddc");
>+
> 	DRM_DEBUG("removing \"%s\" from sysfs\n",
> 		  connector->name);
> 
>@@ -325,6 +334,9 @@
>  * Send a uevent for the DRM device specified by @dev.  Currently we only
>  * set HOTPLUG=1 in the uevent environment, but this could be expanded to
>  * deal with other types of events.
>+ *
>+ * Any new uapi should be using the drm_sysfs_connector_status_event()
>+ * for uevents on connector status change.
>  */
> void drm_sysfs_hotplug_event(struct drm_device *dev)
> {
>@@ -337,6 +349,37 @@
> }
> EXPORT_SYMBOL(drm_sysfs_hotplug_event);
> 
>+/**
>+ * drm_sysfs_connector_status_event - generate a DRM uevent for connector
>+ * property status change
>+ * @connector: connector on which property status changed
>+ * @property: connector property whose status changed.
>+ *
>+ * Send a uevent for the DRM device specified by @dev.  Currently we
>+ * set HOTPLUG=1 and connector id along with the attached property id
>+ * related to the status change.
>+ */
>+void drm_sysfs_connector_status_event(struct drm_connector *connector,
>+				      struct drm_property *property)
>+{
>+	struct drm_device *dev = connector->dev;
>+	char hotplug_str[] = "HOTPLUG=1", conn_id[21], prop_id[21];
>+	char *envp[4] = { hotplug_str, conn_id, prop_id, NULL };
>+
>+	WARN_ON(!drm_mode_obj_find_prop_id(&connector->base,
>+					   property->base.id));
>+
>+	snprintf(conn_id, ARRAY_SIZE(conn_id),
>+		 "CONNECTOR=%u", connector->base.id);
>+	snprintf(prop_id, ARRAY_SIZE(prop_id),
>+		 "PROPERTY=%u", property->base.id);
>+
>+	DRM_DEBUG("generating connector status event\n");
>+
>+	kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp);
>+}
>+EXPORT_SYMBOL(drm_sysfs_connector_status_event);
>+
> static void drm_sysfs_release(struct device *dev)
> {
> 	kfree(dev);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_vblank.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_vblank.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_vblank.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_vblank.c	2019-08-31 15:01:11.947736176 -0500
>@@ -31,7 +31,6 @@
> #include <drm/drm_drv.h>
> #include <drm/drm_framebuffer.h>
> #include <drm/drm_print.h>
>-#include <drm/drm_os_linux.h>
> #include <drm/drm_vblank.h>
> 
> #include "drm_internal.h"
>@@ -1670,12 +1669,28 @@
> 	}
> 
> 	if (req_seq != seq) {
>+		int wait;
>+
> 		DRM_DEBUG("waiting on vblank count %llu, crtc %u\n",
> 			  req_seq, pipe);
>-		DRM_WAIT_ON(ret, vblank->queue, 3 * HZ,
>-			    vblank_passed(drm_vblank_count(dev, pipe),
>-					  req_seq) ||
>-			    !READ_ONCE(vblank->enabled));
>+		wait = wait_event_interruptible_timeout(vblank->queue,
>+			vblank_passed(drm_vblank_count(dev, pipe), req_seq) ||
>+				      !READ_ONCE(vblank->enabled),
>+			msecs_to_jiffies(3000));
>+
>+		switch (wait) {
>+		case 0:
>+			/* timeout */
>+			ret = -EBUSY;
>+			break;
>+		case -ERESTARTSYS:
>+			/* interrupted by signal */
>+			ret = -EINTR;
>+			break;
>+		default:
>+			ret = 0;
>+			break;
>+		}
> 	}
> 
> 	if (ret != -EINTR) {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/drm_vm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_vm.c
>--- linux-5.3-rc6/drivers/gpu/drm/drm_vm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/drm_vm.c	2019-08-31 15:01:11.947736176 -0500
>@@ -1,4 +1,4 @@
>-/**
>+/*
>  * \file drm_vm.c
>  * Memory mapping for DRM
>  *
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/etnaviv/etnaviv_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/etnaviv/etnaviv_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/etnaviv/etnaviv_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/etnaviv/etnaviv_drv.c	2019-08-31 15:01:11.947736176 -0500
>@@ -430,17 +430,17 @@
> static const struct drm_ioctl_desc etnaviv_ioctls[] = {
> #define ETNA_IOCTL(n, func, flags) \
> 	DRM_IOCTL_DEF_DRV(ETNAVIV_##n, etnaviv_ioctl_##func, flags)
>-	ETNA_IOCTL(GET_PARAM,    get_param,    DRM_AUTH|DRM_RENDER_ALLOW),
>-	ETNA_IOCTL(GEM_NEW,      gem_new,      DRM_AUTH|DRM_RENDER_ALLOW),
>-	ETNA_IOCTL(GEM_INFO,     gem_info,     DRM_AUTH|DRM_RENDER_ALLOW),
>-	ETNA_IOCTL(GEM_CPU_PREP, gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
>-	ETNA_IOCTL(GEM_CPU_FINI, gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
>-	ETNA_IOCTL(GEM_SUBMIT,   gem_submit,   DRM_AUTH|DRM_RENDER_ALLOW),
>-	ETNA_IOCTL(WAIT_FENCE,   wait_fence,   DRM_AUTH|DRM_RENDER_ALLOW),
>-	ETNA_IOCTL(GEM_USERPTR,  gem_userptr,  DRM_AUTH|DRM_RENDER_ALLOW),
>-	ETNA_IOCTL(GEM_WAIT,     gem_wait,     DRM_AUTH|DRM_RENDER_ALLOW),
>-	ETNA_IOCTL(PM_QUERY_DOM, pm_query_dom, DRM_AUTH|DRM_RENDER_ALLOW),
>-	ETNA_IOCTL(PM_QUERY_SIG, pm_query_sig, DRM_AUTH|DRM_RENDER_ALLOW),
>+	ETNA_IOCTL(GET_PARAM,    get_param,    DRM_RENDER_ALLOW),
>+	ETNA_IOCTL(GEM_NEW,      gem_new,      DRM_RENDER_ALLOW),
>+	ETNA_IOCTL(GEM_INFO,     gem_info,     DRM_RENDER_ALLOW),
>+	ETNA_IOCTL(GEM_CPU_PREP, gem_cpu_prep, DRM_RENDER_ALLOW),
>+	ETNA_IOCTL(GEM_CPU_FINI, gem_cpu_fini, DRM_RENDER_ALLOW),
>+	ETNA_IOCTL(GEM_SUBMIT,   gem_submit,   DRM_RENDER_ALLOW),
>+	ETNA_IOCTL(WAIT_FENCE,   wait_fence,   DRM_RENDER_ALLOW),
>+	ETNA_IOCTL(GEM_USERPTR,  gem_userptr,  DRM_RENDER_ALLOW),
>+	ETNA_IOCTL(GEM_WAIT,     gem_wait,     DRM_RENDER_ALLOW),
>+	ETNA_IOCTL(PM_QUERY_DOM, pm_query_dom, DRM_RENDER_ALLOW),
>+	ETNA_IOCTL(PM_QUERY_SIG, pm_query_sig, DRM_RENDER_ALLOW),
> };
> 
> static const struct vm_operations_struct vm_ops = {
>@@ -462,17 +462,13 @@
> };
> 
> static struct drm_driver etnaviv_drm_driver = {
>-	.driver_features    = DRIVER_GEM |
>-				DRIVER_PRIME |
>-				DRIVER_RENDER,
>+	.driver_features    = DRIVER_GEM | DRIVER_RENDER,
> 	.open               = etnaviv_open,
> 	.postclose           = etnaviv_postclose,
> 	.gem_free_object_unlocked = etnaviv_gem_free_object,
> 	.gem_vm_ops         = &vm_ops,
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_export   = drm_gem_prime_export,
>-	.gem_prime_import   = drm_gem_prime_import,
> 	.gem_prime_pin      = etnaviv_gem_prime_pin,
> 	.gem_prime_unpin    = etnaviv_gem_prime_unpin,
> 	.gem_prime_get_sg_table = etnaviv_gem_prime_get_sg_table,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/etnaviv/etnaviv_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/etnaviv/etnaviv_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/etnaviv/etnaviv_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/etnaviv/etnaviv_gem.c	2019-08-31 15:01:11.947736176 -0500
>@@ -565,8 +565,7 @@
> }
> 
> static int etnaviv_gem_new_impl(struct drm_device *dev, u32 size, u32 flags,
>-	struct reservation_object *robj, const struct etnaviv_gem_ops *ops,
>-	struct drm_gem_object **obj)
>+	const struct etnaviv_gem_ops *ops, struct drm_gem_object **obj)
> {
> 	struct etnaviv_gem_object *etnaviv_obj;
> 	unsigned sz = sizeof(*etnaviv_obj);
>@@ -594,8 +593,6 @@
> 
> 	etnaviv_obj->flags = flags;
> 	etnaviv_obj->ops = ops;
>-	if (robj)
>-		etnaviv_obj->base.resv = robj;
> 
> 	mutex_init(&etnaviv_obj->lock);
> 	INIT_LIST_HEAD(&etnaviv_obj->vram_list);
>@@ -614,7 +611,7 @@
> 
> 	size = PAGE_ALIGN(size);
> 
>-	ret = etnaviv_gem_new_impl(dev, size, flags, NULL,
>+	ret = etnaviv_gem_new_impl(dev, size, flags,
> 				   &etnaviv_gem_shmem_ops, &obj);
> 	if (ret)
> 		goto fail;
>@@ -646,13 +643,12 @@
> }
> 
> int etnaviv_gem_new_private(struct drm_device *dev, size_t size, u32 flags,
>-	struct reservation_object *robj, const struct etnaviv_gem_ops *ops,
>-	struct etnaviv_gem_object **res)
>+	const struct etnaviv_gem_ops *ops, struct etnaviv_gem_object **res)
> {
> 	struct drm_gem_object *obj;
> 	int ret;
> 
>-	ret = etnaviv_gem_new_impl(dev, size, flags, robj, ops, &obj);
>+	ret = etnaviv_gem_new_impl(dev, size, flags, ops, &obj);
> 	if (ret)
> 		return ret;
> 
>@@ -734,7 +730,7 @@
> 	struct etnaviv_gem_object *etnaviv_obj;
> 	int ret;
> 
>-	ret = etnaviv_gem_new_private(dev, size, ETNA_BO_CACHED, NULL,
>+	ret = etnaviv_gem_new_private(dev, size, ETNA_BO_CACHED,
> 				      &etnaviv_gem_userptr_ops, &etnaviv_obj);
> 	if (ret)
> 		return ret;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/etnaviv/etnaviv_gem.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/etnaviv/etnaviv_gem.h
>--- linux-5.3-rc6/drivers/gpu/drm/etnaviv/etnaviv_gem.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/etnaviv/etnaviv_gem.h	2019-08-31 15:01:11.947736176 -0500
>@@ -112,8 +112,7 @@
> int etnaviv_gem_wait_bo(struct etnaviv_gpu *gpu, struct drm_gem_object *obj,
> 	struct timespec *timeout);
> int etnaviv_gem_new_private(struct drm_device *dev, size_t size, u32 flags,
>-	struct reservation_object *robj, const struct etnaviv_gem_ops *ops,
>-	struct etnaviv_gem_object **res);
>+	const struct etnaviv_gem_ops *ops, struct etnaviv_gem_object **res);
> void etnaviv_gem_obj_add(struct drm_device *dev, struct drm_gem_object *obj);
> struct page **etnaviv_gem_get_pages(struct etnaviv_gem_object *obj);
> void etnaviv_gem_put_pages(struct etnaviv_gem_object *obj);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
>--- linux-5.3-rc6/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c	2019-08-31 15:01:11.947736176 -0500
>@@ -109,7 +109,6 @@
> 	int ret, npages;
> 
> 	ret = etnaviv_gem_new_private(dev, size, ETNA_BO_WC,
>-				      attach->dmabuf->resv,
> 				      &etnaviv_gem_prime_ops, &etnaviv_obj);
> 	if (ret < 0)
> 		return ERR_PTR(ret);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/exynos/exynos_drm_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/exynos/exynos_drm_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/exynos/exynos_drm_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/exynos/exynos_drm_drv.c	2019-08-31 15:01:11.947736176 -0500
>@@ -75,29 +75,29 @@
> 
> static const struct drm_ioctl_desc exynos_ioctls[] = {
> 	DRM_IOCTL_DEF_DRV(EXYNOS_GEM_CREATE, exynos_drm_gem_create_ioctl,
>-			DRM_AUTH | DRM_RENDER_ALLOW),
>+			DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(EXYNOS_GEM_MAP, exynos_drm_gem_map_ioctl,
>-			DRM_AUTH | DRM_RENDER_ALLOW),
>+			DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(EXYNOS_GEM_GET, exynos_drm_gem_get_ioctl,
> 			DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(EXYNOS_VIDI_CONNECTION, vidi_connection_ioctl,
> 			DRM_AUTH),
> 	DRM_IOCTL_DEF_DRV(EXYNOS_G2D_GET_VER, exynos_g2d_get_ver_ioctl,
>-			DRM_AUTH | DRM_RENDER_ALLOW),
>+			DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(EXYNOS_G2D_SET_CMDLIST, exynos_g2d_set_cmdlist_ioctl,
>-			DRM_AUTH | DRM_RENDER_ALLOW),
>+			DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(EXYNOS_G2D_EXEC, exynos_g2d_exec_ioctl,
>-			DRM_AUTH | DRM_RENDER_ALLOW),
>+			DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(EXYNOS_IPP_GET_RESOURCES,
> 			exynos_drm_ipp_get_res_ioctl,
>-			DRM_AUTH | DRM_RENDER_ALLOW),
>+			DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(EXYNOS_IPP_GET_CAPS, exynos_drm_ipp_get_caps_ioctl,
>-			DRM_AUTH | DRM_RENDER_ALLOW),
>+			DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(EXYNOS_IPP_GET_LIMITS,
> 			exynos_drm_ipp_get_limits_ioctl,
>-			DRM_AUTH | DRM_RENDER_ALLOW),
>+			DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(EXYNOS_IPP_COMMIT, exynos_drm_ipp_commit_ioctl,
>-			DRM_AUTH | DRM_RENDER_ALLOW),
>+			DRM_RENDER_ALLOW),
> };
> 
> static const struct file_operations exynos_drm_driver_fops = {
>@@ -112,7 +112,7 @@
> };
> 
> static struct drm_driver exynos_drm_driver = {
>-	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME
>+	.driver_features	= DRIVER_MODESET | DRIVER_GEM
> 				  | DRIVER_ATOMIC | DRIVER_RENDER,
> 	.open			= exynos_drm_open,
> 	.lastclose		= drm_fb_helper_lastclose,
>@@ -122,7 +122,6 @@
> 	.dumb_create		= exynos_drm_gem_dumb_create,
> 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
>-	.gem_prime_export	= drm_gem_prime_export,
> 	.gem_prime_import	= exynos_drm_gem_prime_import,
> 	.gem_prime_get_sg_table	= exynos_drm_gem_prime_get_sg_table,
> 	.gem_prime_import_sg_table	= exynos_drm_gem_prime_import_sg_table,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c	2019-08-31 15:01:11.991736180 -0500
>@@ -8,12 +8,13 @@
> #include <linux/clk.h>
> #include <linux/regmap.h>
> 
>-#include <drm/drmP.h>
>+#include <video/videomode.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_probe_helper.h>
>-#include <video/videomode.h>
>+#include <drm/drm_vblank.h>
> 
> #include "fsl_dcu_drm_crtc.h"
> #include "fsl_dcu_drm_drv.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c	2019-08-31 15:01:11.996736180 -0500
>@@ -18,13 +18,15 @@
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_fb_helper.h>
> #include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_irq.h>
> #include <drm/drm_modeset_helper.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "fsl_dcu_drm_crtc.h"
> #include "fsl_dcu_drm_drv.h"
>@@ -133,8 +135,7 @@
> DEFINE_DRM_GEM_CMA_FOPS(fsl_dcu_drm_fops);
> 
> static struct drm_driver fsl_dcu_drm_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET
>-				| DRIVER_PRIME | DRIVER_ATOMIC,
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.load			= fsl_dcu_load,
> 	.unload			= fsl_dcu_unload,
> 	.irq_handler		= fsl_dcu_drm_irq,
>@@ -144,8 +145,6 @@
> 	.gem_vm_ops		= &drm_gem_cma_vm_ops,
> 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
>-	.gem_prime_import	= drm_gem_prime_import,
>-	.gem_prime_export	= drm_gem_prime_export,
> 	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c
>--- linux-5.3-rc6/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c	2019-08-31 15:01:12.004736181 -0500
>@@ -5,7 +5,6 @@
>  * Freescale DCU drm device driver
>  */
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c	2019-08-31 15:01:12.009736182 -0500
>@@ -7,10 +7,10 @@
> 
> #include <linux/regmap.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c
>--- linux-5.3-rc6/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c	2019-08-31 15:01:12.013736182 -0500
>@@ -8,7 +8,6 @@
> #include <linux/backlight.h>
> #include <linux/of_graph.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_of.h>
> #include <drm/drm_panel.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
>--- linux-5.3-rc6/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c	2019-08-31 15:01:12.013736182 -0500
>@@ -11,10 +11,16 @@
>  *	Jianhua Li <lijianhua@huawei.com>
>  */
> 
>+#include <linux/delay.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_gem_vram_helper.h>
> #include <drm/drm_plane_helper.h>
>+#include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "hibmc_drm_drv.h"
> #include "hibmc_drm_regs.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c	2019-08-31 15:01:12.013736182 -0500
>@@ -13,9 +13,16 @@
> 
> #include <linux/console.h>
> #include <linux/module.h>
>+#include <linux/pci.h>
> 
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_gem_vram_helper.h>
>+#include <drm/drm_irq.h>
>+#include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
>+#include <drm/drm_vram_mm_helper.h>
> 
> #include "hibmc_drm_drv.h"
> #include "hibmc_drm_regs.h"
>@@ -51,10 +58,9 @@
> 	.desc			= "hibmc drm driver",
> 	.major			= 1,
> 	.minor			= 0,
>-	.gem_free_object_unlocked =
>-		drm_gem_vram_driver_gem_free_object_unlocked,
> 	.dumb_create            = hibmc_dumb_create,
> 	.dumb_map_offset        = drm_gem_vram_driver_dumb_mmap_offset,
>+	.gem_prime_mmap		= drm_gem_prime_mmap,
> 	.irq_handler		= hibmc_drm_interrupt,
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h	2019-08-31 15:01:12.013736182 -0500
>@@ -14,12 +14,11 @@
> #ifndef HIBMC_DRM_DRV_H
> #define HIBMC_DRM_DRV_H
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_atomic.h>
> #include <drm/drm_fb_helper.h>
>-#include <drm/drm_gem.h>
>-#include <drm/drm_gem_vram_helper.h>
>-#include <drm/drm_vram_mm_helper.h>
>+#include <drm/drm_framebuffer.h>
>+
>+struct drm_device;
>+struct drm_gem_object;
> 
> struct hibmc_framebuffer {
> 	struct drm_framebuffer fb;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c
>--- linux-5.3-rc6/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_fbdev.c	2019-08-31 15:01:12.013736182 -0500
>@@ -13,6 +13,8 @@
> 
> #include <drm/drm_crtc.h>
> #include <drm/drm_fb_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_gem_vram_helper.h>
> #include <drm/drm_probe_helper.h>
> 
> #include "hibmc_drm_drv.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c
>--- linux-5.3-rc6/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c	2019-08-31 15:01:12.013736182 -0500
>@@ -13,6 +13,7 @@
> 
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_print.h>
> 
> #include "hibmc_drm_drv.h"
> #include "hibmc_drm_regs.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c
>--- linux-5.3-rc6/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/hibmc/hibmc_ttm.c	2019-08-31 15:01:12.013736182 -0500
>@@ -11,7 +11,13 @@
>  *	Jianhua Li <lijianhua@huawei.com>
>  */
> 
>+#include <linux/pci.h>
>+
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_gem.h>
>+#include <drm/drm_gem_vram_helper.h>
>+#include <drm/drm_print.h>
>+#include <drm/drm_vram_mm_helper.h>
> 
> #include "hibmc_drm_drv.h"
> 
>@@ -60,7 +66,7 @@
> 			DRM_ERROR("failed to allocate GEM object: %d\n", ret);
> 		return ret;
> 	}
>-	*obj = &gbo->gem;
>+	*obj = &gbo->bo.base;
> 	return 0;
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
>--- linux-5.3-rc6/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c	2019-08-31 15:01:12.014736182 -0500
>@@ -13,19 +13,23 @@
> 
> #include <linux/bitops.h>
> #include <linux/clk.h>
>-#include <video/display_timing.h>
> #include <linux/mfd/syscon.h>
>+#include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/reset.h>
> 
>-#include <drm/drmP.h>
>+#include <video/display_timing.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "kirin_drm_drv.h"
> #include "kirin_ade_reg.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c	2019-08-31 15:01:12.014736182 -0500
>@@ -13,16 +13,19 @@
> 
> #include <linux/of_platform.h>
> #include <linux/component.h>
>+#include <linux/module.h>
> #include <linux/of_graph.h>
>+#include <linux/platform_device.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_fb_helper.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_of.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "kirin_drm_drv.h"
> 
>@@ -113,8 +116,7 @@
> }
> 
> static struct drm_driver kirin_drm_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
>-				  DRIVER_ATOMIC,
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.fops			= &kirin_drm_fops,
> 
> 	.gem_free_object_unlocked = drm_gem_cma_free_object,
>@@ -123,8 +125,6 @@
> 
> 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
>-	.gem_prime_export	= drm_gem_prime_export,
>-	.gem_prime_import	= drm_gem_prime_import,
> 	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i2c/ch7006_priv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i2c/ch7006_priv.h
>--- linux-5.3-rc6/drivers/gpu/drm/i2c/ch7006_priv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i2c/ch7006_priv.h	2019-08-31 15:01:12.014736182 -0500
>@@ -27,7 +27,6 @@
> #ifndef __DRM_I2C_CH7006_PRIV_H__
> #define __DRM_I2C_CH7006_PRIV_H__
> 
>-#include <drm/drmP.h>
> #include <drm/drm_crtc_helper.h>
> #include <drm/drm_encoder_slave.h>
> #include <drm/drm_probe_helper.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i2c/sil164_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i2c/sil164_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/i2c/sil164_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i2c/sil164_drv.c	2019-08-31 15:01:12.014736182 -0500
>@@ -26,8 +26,9 @@
> 
> #include <linux/module.h>
> 
>-#include <drm/drmP.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_encoder_slave.h>
>+#include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/i2c/sil164.h>
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i810/i810_dma.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i810/i810_dma.c
>--- linux-5.3-rc6/drivers/gpu/drm/i810/i810_dma.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i810/i810_dma.c	2019-08-31 15:01:12.014736182 -0500
>@@ -30,13 +30,20 @@
>  *
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/delay.h>
>+#include <linux/mman.h>
>+
>+#include <drm/drm_agpsupport.h>
>+#include <drm/drm_device.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_ioctl.h>
>+#include <drm/drm_irq.h>
>+#include <drm/drm_pci.h>
>+#include <drm/drm_print.h>
> #include <drm/i810_drm.h>
>+
> #include "i810_drv.h"
>-#include <linux/interrupt.h>	/* For task queue support */
>-#include <linux/delay.h>
>-#include <linux/slab.h>
>-#include <linux/pagemap.h>
> 
> #define I810_BUF_FREE		2
> #define I810_BUF_CLIENT		1
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i810/i810_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i810/i810_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/i810/i810_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i810/i810_drv.c	2019-08-31 15:01:12.014736182 -0500
>@@ -30,13 +30,15 @@
>  *    Gareth Hughes <gareth@valinux.com>
>  */
> 
>+#include "i810_drv.h"
> #include <linux/module.h>
> 
>-#include <drm/drmP.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_pci.h>
>+#include <drm/drm_pciids.h>
> #include <drm/i810_drm.h>
>-#include "i810_drv.h"
> 
>-#include <drm/drm_pciids.h>
> 
> static struct pci_device_id pciidlist[] = {
> 	i810_PCI_IDS
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i810/i810_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i810/i810_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/i810/i810_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i810/i810_drv.h	2019-08-31 15:01:12.014736182 -0500
>@@ -32,7 +32,9 @@
> #ifndef _I810_DRV_H_
> #define _I810_DRV_H_
> 
>+#include <drm/drm_ioctl.h>
> #include <drm/drm_legacy.h>
>+#include <drm/i810_drm.h>
> 
> /* General customization:
>  */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/icl_dsi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/icl_dsi.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/icl_dsi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/icl_dsi.c	2019-08-31 15:01:12.014736182 -0500
>@@ -202,63 +202,62 @@
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>-	enum port port;
>+	enum phy phy;
> 	u32 tmp;
> 	int lane;
> 
>-	for_each_dsi_port(port, intel_dsi->ports) {
>-
>+	for_each_dsi_phy(phy, intel_dsi->phys) {
> 		/*
> 		 * Program voltage swing and pre-emphasis level values as per
> 		 * table in BSPEC under DDI buffer programing
> 		 */
>-		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> 		tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
> 		tmp |= SCALING_MODE_SEL(0x2);
> 		tmp |= TAP2_DISABLE | TAP3_DISABLE;
> 		tmp |= RTERM_SELECT(0x6);
>-		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>+		I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
> 
>-		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
> 		tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
> 		tmp |= SCALING_MODE_SEL(0x2);
> 		tmp |= TAP2_DISABLE | TAP3_DISABLE;
> 		tmp |= RTERM_SELECT(0x6);
>-		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>+		I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
> 
>-		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>+		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
> 		tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> 			 RCOMP_SCALAR_MASK);
> 		tmp |= SWING_SEL_UPPER(0x2);
> 		tmp |= SWING_SEL_LOWER(0x2);
> 		tmp |= RCOMP_SCALAR(0x98);
>-		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
>+		I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
> 
>-		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
>+		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
> 		tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> 			 RCOMP_SCALAR_MASK);
> 		tmp |= SWING_SEL_UPPER(0x2);
> 		tmp |= SWING_SEL_LOWER(0x2);
> 		tmp |= RCOMP_SCALAR(0x98);
>-		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
>+		I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
> 
>-		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
>+		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
> 		tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> 			 CURSOR_COEFF_MASK);
> 		tmp |= POST_CURSOR_1(0x0);
> 		tmp |= POST_CURSOR_2(0x0);
> 		tmp |= CURSOR_COEFF(0x3f);
>-		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
>+		I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
> 
> 		for (lane = 0; lane <= 3; lane++) {
> 			/* Bspec: must not use GRP register for write */
>-			tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port));
>+			tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
> 			tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> 				 CURSOR_COEFF_MASK);
> 			tmp |= POST_CURSOR_1(0x0);
> 			tmp |= POST_CURSOR_2(0x0);
> 			tmp |= CURSOR_COEFF(0x3f);
>-			I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp);
>+			I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
> 		}
> 	}
> }
>@@ -364,10 +363,10 @@
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>-	enum port port;
>+	enum phy phy;
> 
>-	for_each_dsi_port(port, intel_dsi->ports)
>-		intel_combo_phy_power_up_lanes(dev_priv, port, true,
>+	for_each_dsi_phy(phy, intel_dsi->phys)
>+		intel_combo_phy_power_up_lanes(dev_priv, phy, true,
> 					       intel_dsi->lane_count, false);
> }
> 
>@@ -375,34 +374,47 @@
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>-	enum port port;
>+	enum phy phy;
> 	u32 tmp;
> 	int lane;
> 
> 	/* Step 4b(i) set loadgen select for transmit and aux lanes */
>-	for_each_dsi_port(port, intel_dsi->ports) {
>-		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
>+	for_each_dsi_phy(phy, intel_dsi->phys) {
>+		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
> 		tmp &= ~LOADGEN_SELECT;
>-		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
>+		I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
> 		for (lane = 0; lane <= 3; lane++) {
>-			tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port));
>+			tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
> 			tmp &= ~LOADGEN_SELECT;
> 			if (lane != 2)
> 				tmp |= LOADGEN_SELECT;
>-			I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp);
>+			I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
> 		}
> 	}
> 
> 	/* Step 4b(ii) set latency optimization for transmit and aux lanes */
>-	for_each_dsi_port(port, intel_dsi->ports) {
>-		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
>+	for_each_dsi_phy(phy, intel_dsi->phys) {
>+		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
> 		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> 		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
>-		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
>-		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>+		I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
>+		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
> 		tmp &= ~FRC_LATENCY_OPTIM_MASK;
> 		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
>-		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
>+		I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
>+
>+		/* For EHL set latency optimization for PCS_DW1 lanes */
>+		if (IS_ELKHARTLAKE(dev_priv)) {
>+			tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
>+			tmp &= ~LATENCY_OPTIM_MASK;
>+			tmp |= LATENCY_OPTIM_VAL(0);
>+			I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp);
>+
>+			tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
>+			tmp &= ~LATENCY_OPTIM_MASK;
>+			tmp |= LATENCY_OPTIM_VAL(0x1);
>+			I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp);
>+		}
> 	}
> 
> }
>@@ -412,16 +424,16 @@
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> 	u32 tmp;
>-	enum port port;
>+	enum phy phy;
> 
> 	/* clear common keeper enable bit */
>-	for_each_dsi_port(port, intel_dsi->ports) {
>-		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
>+	for_each_dsi_phy(phy, intel_dsi->phys) {
>+		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
> 		tmp &= ~COMMON_KEEPER_EN;
>-		I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
>-		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
>+		I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp);
>+		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
> 		tmp &= ~COMMON_KEEPER_EN;
>-		I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
>+		I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp);
> 	}
> 
> 	/*
>@@ -429,33 +441,33 @@
> 	 * Note: loadgen select program is done
> 	 * as part of lane phy sequence configuration
> 	 */
>-	for_each_dsi_port(port, intel_dsi->ports) {
>-		tmp = I915_READ(ICL_PORT_CL_DW5(port));
>+	for_each_dsi_phy(phy, intel_dsi->phys) {
>+		tmp = I915_READ(ICL_PORT_CL_DW5(phy));
> 		tmp |= SUS_CLOCK_CONFIG;
>-		I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
>+		I915_WRITE(ICL_PORT_CL_DW5(phy), tmp);
> 	}
> 
> 	/* Clear training enable to change swing values */
>-	for_each_dsi_port(port, intel_dsi->ports) {
>-		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>+	for_each_dsi_phy(phy, intel_dsi->phys) {
>+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> 		tmp &= ~TX_TRAINING_EN;
>-		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>-		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>+		I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
>+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
> 		tmp &= ~TX_TRAINING_EN;
>-		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>+		I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
> 	}
> 
> 	/* Program swing and de-emphasis */
> 	dsi_program_swing_and_deemphasis(encoder);
> 
> 	/* Set training enable to trigger update */
>-	for_each_dsi_port(port, intel_dsi->ports) {
>-		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>+	for_each_dsi_phy(phy, intel_dsi->phys) {
>+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> 		tmp |= TX_TRAINING_EN;
>-		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
>-		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
>+		I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
>+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
> 		tmp |= TX_TRAINING_EN;
>-		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
>+		I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
> 	}
> }
> 
>@@ -484,6 +496,7 @@
> 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> 	u32 tmp;
> 	enum port port;
>+	enum phy phy;
> 
> 	/* Program T-INIT master registers */
> 	for_each_dsi_port(port, intel_dsi->ports) {
>@@ -531,6 +544,14 @@
> 			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
> 		}
> 	}
>+
>+	if (IS_ELKHARTLAKE(dev_priv)) {
>+		for_each_dsi_phy(phy, intel_dsi->phys) {
>+			tmp = I915_READ(ICL_DPHY_CHKN(phy));
>+			tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
>+			I915_WRITE(ICL_DPHY_CHKN(phy), tmp);
>+		}
>+	}
> }
> 
> static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
>@@ -538,15 +559,14 @@
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> 	u32 tmp;
>-	enum port port;
>+	enum phy phy;
> 
> 	mutex_lock(&dev_priv->dpll_lock);
>-	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
>-	for_each_dsi_port(port, intel_dsi->ports) {
>-		tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
>-	}
>+	tmp = I915_READ(ICL_DPCLKA_CFGCR0);
>+	for_each_dsi_phy(phy, intel_dsi->phys)
>+		tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> 
>-	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
>+	I915_WRITE(ICL_DPCLKA_CFGCR0, tmp);
> 	mutex_unlock(&dev_priv->dpll_lock);
> }
> 
>@@ -555,15 +575,14 @@
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> 	u32 tmp;
>-	enum port port;
>+	enum phy phy;
> 
> 	mutex_lock(&dev_priv->dpll_lock);
>-	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
>-	for_each_dsi_port(port, intel_dsi->ports) {
>-		tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
>-	}
>+	tmp = I915_READ(ICL_DPCLKA_CFGCR0);
>+	for_each_dsi_phy(phy, intel_dsi->phys)
>+		tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> 
>-	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
>+	I915_WRITE(ICL_DPCLKA_CFGCR0, tmp);
> 	mutex_unlock(&dev_priv->dpll_lock);
> }
> 
>@@ -573,24 +592,24 @@
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>-	enum port port;
>+	enum phy phy;
> 	u32 val;
> 
> 	mutex_lock(&dev_priv->dpll_lock);
> 
>-	val = I915_READ(DPCLKA_CFGCR0_ICL);
>-	for_each_dsi_port(port, intel_dsi->ports) {
>-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
>+	val = I915_READ(ICL_DPCLKA_CFGCR0);
>+	for_each_dsi_phy(phy, intel_dsi->phys) {
>+		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
>+		val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> 	}
>-	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>+	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
> 
>-	for_each_dsi_port(port, intel_dsi->ports) {
>-		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
>+	for_each_dsi_phy(phy, intel_dsi->phys) {
>+		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> 	}
>-	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>+	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
> 
>-	POSTING_READ(DPCLKA_CFGCR0_ICL);
>+	POSTING_READ(ICL_DPCLKA_CFGCR0);
> 
> 	mutex_unlock(&dev_priv->dpll_lock);
> }
>@@ -744,7 +763,7 @@
> 	enum transcoder dsi_trans;
> 	/* horizontal timings */
> 	u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
>-	u16 hfront_porch, hback_porch;
>+	u16 hback_porch;
> 	/* vertical timings */
> 	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
> 
>@@ -753,8 +772,6 @@
> 	hsync_start = adjusted_mode->crtc_hsync_start;
> 	hsync_end = adjusted_mode->crtc_hsync_end;
> 	hsync_size  = hsync_end - hsync_start;
>-	hfront_porch = (adjusted_mode->crtc_hsync_start -
>-			adjusted_mode->crtc_hdisplay);
> 	hback_porch = (adjusted_mode->crtc_htotal -
> 		       adjusted_mode->crtc_hsync_end);
> 	vactive = adjusted_mode->crtc_vdisplay;
>@@ -1487,6 +1504,26 @@
> 	intel_dsi_log_params(intel_dsi);
> }
> 
>+static void icl_dsi_add_properties(struct intel_connector *connector)
>+{
>+	u32 allowed_scalers;
>+
>+	allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) |
>+			   BIT(DRM_MODE_SCALE_FULLSCREEN) |
>+			   BIT(DRM_MODE_SCALE_CENTER);
>+
>+	drm_connector_attach_scaling_mode_property(&connector->base,
>+						   allowed_scalers);
>+
>+	connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
>+
>+	connector->base.display_info.panel_orientation =
>+			intel_dsi_get_panel_orientation(connector);
>+	drm_connector_init_panel_orientation_property(&connector->base,
>+				connector->panel.fixed_mode->hdisplay,
>+				connector->panel.fixed_mode->vdisplay);
>+}
>+
> void icl_dsi_init(struct drm_i915_private *dev_priv)
> {
> 	struct drm_device *dev = &dev_priv->drm;
>@@ -1580,6 +1617,8 @@
> 	}
> 
> 	icl_dphy_param_init(intel_dsi);
>+
>+	icl_dsi_add_properties(intel_connector);
> 	return;
> 
> err:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_atomic_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_atomic_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_atomic_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_atomic_plane.c	2019-08-31 15:01:12.014736182 -0500
>@@ -176,33 +176,49 @@
> 	new_crtc_state->data_rate[plane->id] =
> 		intel_plane_data_rate(new_crtc_state, new_plane_state);
> 
>-	return intel_plane_atomic_calc_changes(old_crtc_state,
>-					       &new_crtc_state->base,
>-					       old_plane_state,
>-					       &new_plane_state->base);
>+	return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
>+					       old_plane_state, new_plane_state);
> }
> 
>-static int intel_plane_atomic_check(struct drm_plane *plane,
>-				    struct drm_plane_state *new_plane_state)
>+static struct intel_crtc *
>+get_crtc_from_states(const struct intel_plane_state *old_plane_state,
>+		     const struct intel_plane_state *new_plane_state)
> {
>-	struct drm_atomic_state *state = new_plane_state->state;
>-	const struct drm_plane_state *old_plane_state =
>-		drm_atomic_get_old_plane_state(state, plane);
>-	struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;
>-	const struct drm_crtc_state *old_crtc_state;
>-	struct drm_crtc_state *new_crtc_state;
>+	if (new_plane_state->base.crtc)
>+		return to_intel_crtc(new_plane_state->base.crtc);
> 
>-	new_plane_state->visible = false;
>+	if (old_plane_state->base.crtc)
>+		return to_intel_crtc(old_plane_state->base.crtc);
>+
>+	return NULL;
>+}
>+
>+static int intel_plane_atomic_check(struct drm_plane *_plane,
>+				    struct drm_plane_state *_new_plane_state)
>+{
>+	struct intel_plane *plane = to_intel_plane(_plane);
>+	struct intel_atomic_state *state =
>+		to_intel_atomic_state(_new_plane_state->state);
>+	struct intel_plane_state *new_plane_state =
>+		to_intel_plane_state(_new_plane_state);
>+	const struct intel_plane_state *old_plane_state =
>+		intel_atomic_get_old_plane_state(state, plane);
>+	struct intel_crtc *crtc =
>+		get_crtc_from_states(old_plane_state, new_plane_state);
>+	const struct intel_crtc_state *old_crtc_state;
>+	struct intel_crtc_state *new_crtc_state;
>+
>+	new_plane_state->base.visible = false;
> 	if (!crtc)
> 		return 0;
> 
>-	old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
>-	new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
>+	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
>+	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> 
>-	return intel_plane_atomic_check_with_state(to_intel_crtc_state(old_crtc_state),
>-						   to_intel_crtc_state(new_crtc_state),
>-						   to_intel_plane_state(old_plane_state),
>-						   to_intel_plane_state(new_plane_state));
>+	return intel_plane_atomic_check_with_state(old_crtc_state,
>+						   new_crtc_state,
>+						   old_plane_state,
>+						   new_plane_state);
> }
> 
> static struct intel_plane *
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_atomic_plane.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_atomic_plane.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_atomic_plane.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_atomic_plane.h	2019-08-31 15:01:12.015736182 -0500
>@@ -8,7 +8,6 @@
> 
> #include <linux/types.h>
> 
>-struct drm_crtc_state;
> struct drm_plane;
> struct drm_property;
> struct intel_atomic_state;
>@@ -43,8 +42,8 @@
> 					const struct intel_plane_state *old_plane_state,
> 					struct intel_plane_state *intel_state);
> int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
>-				    struct drm_crtc_state *crtc_state,
>+				    struct intel_crtc_state *crtc_state,
> 				    const struct intel_plane_state *old_plane_state,
>-				    struct drm_plane_state *plane_state);
>+				    struct intel_plane_state *plane_state);
> 
> #endif /* __INTEL_ATOMIC_PLANE_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_audio.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_audio.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_audio.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_audio.c	2019-08-31 15:01:12.015736182 -0500
>@@ -72,6 +72,13 @@
> 	u16 n;
> };
> 
>+struct hdmi_aud_ncts {
>+	int sample_rate;
>+	int clock;
>+	int n;
>+	int cts;
>+};
>+
> /* Values according to DP 1.4 Table 2-104 */
> static const struct dp_aud_n_m dp_aud_n_m[] = {
> 	{ 32000, LC_162M, 1024, 10125 },
>@@ -148,12 +155,7 @@
> #define TMDS_594M 594000
> #define TMDS_593M 593407
> 
>-static const struct {
>-	int sample_rate;
>-	int clock;
>-	int n;
>-	int cts;
>-} hdmi_aud_ncts[] = {
>+static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
> 	{ 32000, TMDS_296M, 5824, 421875 },
> 	{ 32000, TMDS_297M, 3072, 222750 },
> 	{ 32000, TMDS_593M, 5824, 843750 },
>@@ -184,6 +186,49 @@
> 	{ 192000, TMDS_594M, 24576, 594000 },
> };
> 
>+/* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
>+/* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
>+#define TMDS_371M 371250
>+#define TMDS_370M 370878
>+
>+static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
>+	{ 32000, TMDS_370M, 5824, 527344 },
>+	{ 32000, TMDS_371M, 6144, 556875 },
>+	{ 44100, TMDS_370M, 8918, 585938 },
>+	{ 44100, TMDS_371M, 4704, 309375 },
>+	{ 88200, TMDS_370M, 17836, 585938 },
>+	{ 88200, TMDS_371M, 9408, 309375 },
>+	{ 176400, TMDS_370M, 35672, 585938 },
>+	{ 176400, TMDS_371M, 18816, 309375 },
>+	{ 48000, TMDS_370M, 11648, 703125 },
>+	{ 48000, TMDS_371M, 5120, 309375 },
>+	{ 96000, TMDS_370M, 23296, 703125 },
>+	{ 96000, TMDS_371M, 10240, 309375 },
>+	{ 192000, TMDS_370M, 46592, 703125 },
>+	{ 192000, TMDS_371M, 20480, 309375 },
>+};
>+
>+/* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
>+#define TMDS_445_5M 445500
>+#define TMDS_445M 445054
>+
>+static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
>+	{ 32000, TMDS_445M, 5824, 632813 },
>+	{ 32000, TMDS_445_5M, 4096, 445500 },
>+	{ 44100, TMDS_445M, 8918, 703125 },
>+	{ 44100, TMDS_445_5M, 4704, 371250 },
>+	{ 88200, TMDS_445M, 17836, 703125 },
>+	{ 88200, TMDS_445_5M, 9408, 371250 },
>+	{ 176400, TMDS_445M, 35672, 703125 },
>+	{ 176400, TMDS_445_5M, 18816, 371250 },
>+	{ 48000, TMDS_445M, 5824, 421875 },
>+	{ 48000, TMDS_445_5M, 5120, 371250 },
>+	{ 96000, TMDS_445M, 11648, 421875 },
>+	{ 96000, TMDS_445_5M, 10240, 371250 },
>+	{ 192000, TMDS_445M, 23296, 421875 },
>+	{ 192000, TMDS_445_5M, 20480, 371250 },
>+};
>+
> /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
> static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
> {
>@@ -212,14 +257,24 @@
> static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
> 				   int rate)
> {
>-	const struct drm_display_mode *adjusted_mode =
>-		&crtc_state->base.adjusted_mode;
>-	int i;
>+	const struct hdmi_aud_ncts *hdmi_ncts_table;
>+	int i, size;
>+
>+	if (crtc_state->pipe_bpp == 36) {
>+		hdmi_ncts_table = hdmi_aud_ncts_36bpp;
>+		size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
>+	} else if (crtc_state->pipe_bpp == 30) {
>+		hdmi_ncts_table = hdmi_aud_ncts_30bpp;
>+		size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
>+	} else {
>+		hdmi_ncts_table = hdmi_aud_ncts_24bpp;
>+		size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
>+	}
> 
>-	for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {
>-		if (rate == hdmi_aud_ncts[i].sample_rate &&
>-		    adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {
>-			return hdmi_aud_ncts[i].n;
>+	for (i = 0; i < size; i++) {
>+		if (rate == hdmi_ncts_table[i].sample_rate &&
>+		    crtc_state->port_clock == hdmi_ncts_table[i].clock) {
>+			return hdmi_ncts_table[i].n;
> 		}
> 	}
> 	return 0;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_bios.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_bios.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_bios.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_bios.c	2019-08-31 15:01:12.015736182 -0500
>@@ -28,6 +28,7 @@
> #include <drm/drm_dp_helper.h>
> #include <drm/i915_drm.h>
> 
>+#include "display/intel_display.h"
> #include "display/intel_gmbus.h"
> 
> #include "i915_drv.h"
>@@ -1354,12 +1355,27 @@
> 	[MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
> };
> 
>+static const u8 tgp_ddc_pin_map[] = {
>+	[ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
>+	[ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
>+	[TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
>+	[ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
>+	[ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
>+	[ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
>+	[ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
>+	[TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
>+	[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
>+};
>+
> static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
> {
> 	const u8 *ddc_pin_map;
> 	int n_entries;
> 
>-	if (HAS_PCH_MCC(dev_priv)) {
>+	if (HAS_PCH_TGP(dev_priv)) {
>+		ddc_pin_map = tgp_ddc_pin_map;
>+		n_entries = ARRAY_SIZE(tgp_ddc_pin_map);
>+	} else if (HAS_PCH_MCC(dev_priv)) {
> 		ddc_pin_map = mcc_ddc_pin_map;
> 		n_entries = ARRAY_SIZE(mcc_ddc_pin_map);
> 	} else if (HAS_PCH_ICP(dev_priv)) {
>@@ -1668,6 +1684,9 @@
> 		if (!child->device_type)
> 			continue;
> 
>+		DRM_DEBUG_KMS("Found VBT child device with type 0x%x\n",
>+			      child->device_type);
>+
> 		/*
> 		 * Copy as much as we know (sizeof) and is available
> 		 * (child_dev_size) of the child device. Accessing the data must
>@@ -1730,12 +1749,13 @@
> 	for (port = PORT_A; port < I915_MAX_PORTS; port++) {
> 		struct ddi_vbt_port_info *info =
> 			&dev_priv->vbt.ddi_port_info[port];
>+		enum phy phy = intel_port_to_phy(dev_priv, port);
> 
> 		/*
> 		 * VBT has the TypeC mode (native,TBT/USB) and we don't want
> 		 * to detect it.
> 		 */
>-		if (intel_port_is_tc(dev_priv, port))
>+		if (intel_phy_is_tc(dev_priv, phy))
> 			continue;
> 
> 		info->supports_dvi = (port != PORT_A && port != PORT_E);
>@@ -1888,10 +1908,10 @@
> }
> 
> /**
>- * intel_bios_cleanup - Free any resources allocated by intel_bios_init()
>+ * intel_bios_driver_remove - Free any resources allocated by intel_bios_init()
>  * @dev_priv: i915 device instance
>  */
>-void intel_bios_cleanup(struct drm_i915_private *dev_priv)
>+void intel_bios_driver_remove(struct drm_i915_private *dev_priv)
> {
> 	kfree(dev_priv->vbt.child_dev);
> 	dev_priv->vbt.child_dev = NULL;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_bios.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_bios.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_bios.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_bios.h	2019-08-31 15:01:12.015736182 -0500
>@@ -42,6 +42,7 @@
> 	INTEL_BACKLIGHT_DISPLAY_DDI,
> 	INTEL_BACKLIGHT_DSI_DCS,
> 	INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE,
>+	INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE,
> };
> 
> struct edp_power_seq {
>@@ -227,7 +228,7 @@
> } __packed;
> 
> void intel_bios_init(struct drm_i915_private *dev_priv);
>-void intel_bios_cleanup(struct drm_i915_private *dev_priv);
>+void intel_bios_driver_remove(struct drm_i915_private *dev_priv);
> bool intel_bios_is_valid_vbt(const void *buf, size_t size);
> bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
> bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_bw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_bw.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_bw.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_bw.c	2019-08-31 15:01:12.015736182 -0500
>@@ -65,7 +65,7 @@
> 					 struct intel_qgv_point *sp,
> 					 int point)
> {
>-	u32 val = 0, val2;
>+	u32 val = 0, val2 = 0;
> 	int ret;
> 
> 	ret = sandybridge_pcode_read(dev_priv,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_cdclk.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_cdclk.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_cdclk.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_cdclk.c	2019-08-31 15:01:12.015736182 -0500
>@@ -545,10 +545,10 @@
> 	/* There are cases where we can end up here with power domains
> 	 * off and a CDCLK frequency other than the minimum, like when
> 	 * issuing a modeset without actually changing any display after
>-	 * a system suspend.  So grab the PIPE-A domain, which covers
>+	 * a system suspend.  So grab the display core domain, which covers
> 	 * the HW blocks needed for the following programming.
> 	 */
>-	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
>+	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
> 
> 	vlv_iosf_sb_get(dev_priv,
> 			BIT(VLV_IOSF_SB_CCK) |
>@@ -606,7 +606,7 @@
> 
> 	vlv_program_pfi_credits(dev_priv);
> 
>-	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
>+	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
> }
> 
> static void chv_set_cdclk(struct drm_i915_private *dev_priv,
>@@ -631,10 +631,10 @@
> 	/* There are cases where we can end up here with power domains
> 	 * off and a CDCLK frequency other than the minimum, like when
> 	 * issuing a modeset without actually changing any display after
>-	 * a system suspend.  So grab the PIPE-A domain, which covers
>+	 * a system suspend.  So grab the display core domain, which covers
> 	 * the HW blocks needed for the following programming.
> 	 */
>-	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
>+	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
> 
> 	vlv_punit_get(dev_priv);
> 	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
>@@ -653,7 +653,7 @@
> 
> 	vlv_program_pfi_credits(dev_priv);
> 
>-	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
>+	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
> }
> 
> static int bdw_calc_cdclk(int min_cdclk)
>@@ -1756,9 +1756,10 @@
> 
> static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> {
>-	int ranges_24[] = { 312000, 552000, 648000 };
>-	int ranges_19_38[] = { 307200, 556800, 652800 };
>-	int *ranges;
>+	static const int ranges_24[] = { 180000, 192000, 312000, 552000, 648000 };
>+	static const int ranges_19_38[] = { 172800, 192000, 307200, 556800, 652800 };
>+	const int *ranges;
>+	int len, i;
> 
> 	switch (ref) {
> 	default:
>@@ -1766,19 +1767,22 @@
> 		/* fall through */
> 	case 24000:
> 		ranges = ranges_24;
>+		len = ARRAY_SIZE(ranges_24);
> 		break;
> 	case 19200:
> 	case 38400:
> 		ranges = ranges_19_38;
>+		len = ARRAY_SIZE(ranges_19_38);
> 		break;
> 	}
> 
>-	if (min_cdclk > ranges[1])
>-		return ranges[2];
>-	else if (min_cdclk > ranges[0])
>-		return ranges[1];
>-	else
>-		return ranges[0];
>+	for (i = 0; i < len; i++) {
>+		if (min_cdclk <= ranges[i])
>+			return ranges[i];
>+	}
>+
>+	WARN_ON(min_cdclk > ranges[len - 1]);
>+	return ranges[len - 1];
> }
> 
> static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
>@@ -1792,16 +1796,24 @@
> 	default:
> 		MISSING_CASE(cdclk);
> 		/* fall through */
>+	case 172800:
> 	case 307200:
> 	case 556800:
> 	case 652800:
> 		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> 			dev_priv->cdclk.hw.ref != 38400);
> 		break;
>+	case 180000:
> 	case 312000:
> 	case 552000:
> 	case 648000:
> 		WARN_ON(dev_priv->cdclk.hw.ref != 24000);
>+		break;
>+	case 192000:
>+		WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
>+			dev_priv->cdclk.hw.ref != 38400 &&
>+			dev_priv->cdclk.hw.ref != 24000);
>+		break;
> 	}
> 
> 	ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
>@@ -1854,14 +1866,23 @@
> 	dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
> }
> 
>-static u8 icl_calc_voltage_level(int cdclk)
>+static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
> {
>-	if (cdclk > 556800)
>-		return 2;
>-	else if (cdclk > 312000)
>-		return 1;
>-	else
>-		return 0;
>+	if (IS_ELKHARTLAKE(dev_priv)) {
>+		if (cdclk > 312000)
>+			return 2;
>+		else if (cdclk > 180000)
>+			return 1;
>+		else
>+			return 0;
>+	} else {
>+		if (cdclk > 556800)
>+			return 2;
>+		else if (cdclk > 312000)
>+			return 1;
>+		else
>+			return 0;
>+	}
> }
> 
> static void icl_get_cdclk(struct drm_i915_private *dev_priv,
>@@ -1912,7 +1933,7 @@
> 	 * at least what the CDCLK frequency requires.
> 	 */
> 	cdclk_state->voltage_level =
>-		icl_calc_voltage_level(cdclk_state->cdclk);
>+		icl_calc_voltage_level(dev_priv, cdclk_state->cdclk);
> }
> 
> static void icl_init_cdclk(struct drm_i915_private *dev_priv)
>@@ -1947,7 +1968,8 @@
> 	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> 						     sanitized_state.cdclk);
> 	sanitized_state.voltage_level =
>-				icl_calc_voltage_level(sanitized_state.cdclk);
>+				icl_calc_voltage_level(dev_priv,
>+						       sanitized_state.cdclk);
> 
> 	icl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
> }
>@@ -1958,7 +1980,8 @@
> 
> 	cdclk_state.cdclk = cdclk_state.bypass;
> 	cdclk_state.vco = 0;
>-	cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);
>+	cdclk_state.voltage_level = icl_calc_voltage_level(dev_priv,
>+							   cdclk_state.cdclk);
> 
> 	icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> }
>@@ -2560,7 +2583,7 @@
> 	state->cdclk.logical.vco = vco;
> 	state->cdclk.logical.cdclk = cdclk;
> 	state->cdclk.logical.voltage_level =
>-		max(icl_calc_voltage_level(cdclk),
>+		max(icl_calc_voltage_level(dev_priv, cdclk),
> 		    cnl_compute_min_voltage_level(state));
> 
> 	if (!state->active_crtcs) {
>@@ -2570,7 +2593,7 @@
> 		state->cdclk.actual.vco = vco;
> 		state->cdclk.actual.cdclk = cdclk;
> 		state->cdclk.actual.voltage_level =
>-			icl_calc_voltage_level(cdclk);
>+			icl_calc_voltage_level(dev_priv, cdclk);
> 	} else {
> 		state->cdclk.actual = state->cdclk.logical;
> 	}
>@@ -2605,7 +2628,12 @@
>  */
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> {
>-	if (INTEL_GEN(dev_priv) >= 11) {
>+	if (IS_ELKHARTLAKE(dev_priv)) {
>+		if (dev_priv->cdclk.hw.ref == 24000)
>+			dev_priv->max_cdclk_freq = 552000;
>+		else
>+			dev_priv->max_cdclk_freq = 556800;
>+	} else if (INTEL_GEN(dev_priv) >= 11) {
> 		if (dev_priv->cdclk.hw.ref == 24000)
> 			dev_priv->max_cdclk_freq = 648000;
> 		else
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_combo_phy.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_combo_phy.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_combo_phy.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_combo_phy.c	2019-08-31 15:01:12.015736182 -0500
>@@ -6,13 +6,13 @@
> #include "intel_combo_phy.h"
> #include "intel_drv.h"
> 
>-#define for_each_combo_port(__dev_priv, __port) \
>-	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
>-		for_each_if(intel_port_is_combophy(__dev_priv, __port))
>-
>-#define for_each_combo_port_reverse(__dev_priv, __port) \
>-	for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
>-		for_each_if(intel_port_is_combophy(__dev_priv, __port))
>+#define for_each_combo_phy(__dev_priv, __phy) \
>+	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
>+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
>+
>+#define for_each_combo_phy_reverse(__dev_priv, __phy) \
>+	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
>+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
> 
> enum {
> 	PROCMON_0_85V_DOT_0,
>@@ -38,18 +38,17 @@
> };
> 
> /*
>- * CNL has just one set of registers, while ICL has two sets: one for port A and
>- * the other for port B. The CNL registers are equivalent to the ICL port A
>- * registers, that's why we call the ICL macros even though the function has CNL
>- * on its name.
>+ * CNL has just one set of registers, while gen11 has a set for each combo PHY.
>+ * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
>+ * call the ICL macros even though the function has CNL on its name.
>  */
> static const struct cnl_procmon *
>-cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port)
>+cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
> {
> 	const struct cnl_procmon *procmon;
> 	u32 val;
> 
>-	val = I915_READ(ICL_PORT_COMP_DW3(port));
>+	val = I915_READ(ICL_PORT_COMP_DW3(phy));
> 	switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
> 	default:
> 		MISSING_CASE(val);
>@@ -75,32 +74,32 @@
> }
> 
> static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
>-				       enum port port)
>+				       enum phy phy)
> {
> 	const struct cnl_procmon *procmon;
> 	u32 val;
> 
>-	procmon = cnl_get_procmon_ref_values(dev_priv, port);
>+	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
> 
>-	val = I915_READ(ICL_PORT_COMP_DW1(port));
>+	val = I915_READ(ICL_PORT_COMP_DW1(phy));
> 	val &= ~((0xff << 16) | 0xff);
> 	val |= procmon->dw1;
>-	I915_WRITE(ICL_PORT_COMP_DW1(port), val);
>+	I915_WRITE(ICL_PORT_COMP_DW1(phy), val);
> 
>-	I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
>-	I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
>+	I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);
>+	I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10);
> }
> 
> static bool check_phy_reg(struct drm_i915_private *dev_priv,
>-			  enum port port, i915_reg_t reg, u32 mask,
>+			  enum phy phy, i915_reg_t reg, u32 mask,
> 			  u32 expected_val)
> {
> 	u32 val = I915_READ(reg);
> 
> 	if ((val & mask) != expected_val) {
>-		DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state mismatch: "
>+		DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: "
> 				 "current %08x mask %08x expected %08x\n",
>-				 port_name(port),
>+				 phy_name(phy),
> 				 reg.reg, val, mask, expected_val);
> 		return false;
> 	}
>@@ -109,18 +108,18 @@
> }
> 
> static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
>-					  enum port port)
>+					  enum phy phy)
> {
> 	const struct cnl_procmon *procmon;
> 	bool ret;
> 
>-	procmon = cnl_get_procmon_ref_values(dev_priv, port);
>+	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
> 
>-	ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port),
>+	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
> 			    (0xff << 16) | 0xff, procmon->dw1);
>-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port),
>+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
> 			     -1U, procmon->dw9);
>-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port),
>+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
> 			     -1U, procmon->dw10);
> 
> 	return ret;
>@@ -134,15 +133,15 @@
> 
> static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
> {
>-	enum port port = PORT_A;
>+	enum phy phy = PHY_A;
> 	bool ret;
> 
> 	if (!cnl_combo_phy_enabled(dev_priv))
> 		return false;
> 
>-	ret = cnl_verify_procmon_ref_values(dev_priv, port);
>+	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
> 
>-	ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5,
>+	ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
> 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
> 
> 	return ret;
>@@ -157,7 +156,7 @@
> 	I915_WRITE(CHICKEN_MISC_2, val);
> 
> 	/* Dummy PORT_A to get the correct CNL register from the ICL macro */
>-	cnl_set_procmon_ref_values(dev_priv, PORT_A);
>+	cnl_set_procmon_ref_values(dev_priv, PHY_A);
> 
> 	val = I915_READ(CNL_PORT_COMP_DW0);
> 	val |= COMP_INIT;
>@@ -181,35 +180,39 @@
> }
> 
> static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
>-				  enum port port)
>+				  enum phy phy)
> {
>-	return !(I915_READ(ICL_PHY_MISC(port)) &
>-		 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
>-		(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
>+	/* The PHY C added by EHL has no PHY_MISC register */
>+	if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
>+		return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
>+	else
>+		return !(I915_READ(ICL_PHY_MISC(phy)) &
>+			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
>+			(I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
> }
> 
> static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
>-				       enum port port)
>+				       enum phy phy)
> {
> 	bool ret;
> 
>-	if (!icl_combo_phy_enabled(dev_priv, port))
>+	if (!icl_combo_phy_enabled(dev_priv, phy))
> 		return false;
> 
>-	ret = cnl_verify_procmon_ref_values(dev_priv, port);
>+	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
> 
>-	if (port == PORT_A)
>-		ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW8(port),
>+	if (phy == PHY_A)
>+		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
> 				     IREFGEN, IREFGEN);
> 
>-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port),
>+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
> 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
> 
> 	return ret;
> }
> 
> void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
>-				    enum port port, bool is_dsi,
>+				    enum phy phy, bool is_dsi,
> 				    int lane_count, bool lane_reversal)
> {
> 	u8 lane_mask;
>@@ -254,66 +257,120 @@
> 		}
> 	}
> 
>-	val = I915_READ(ICL_PORT_CL_DW10(port));
>+	val = I915_READ(ICL_PORT_CL_DW10(phy));
> 	val &= ~PWR_DOWN_LN_MASK;
> 	val |= lane_mask << PWR_DOWN_LN_SHIFT;
>-	I915_WRITE(ICL_PORT_CL_DW10(port), val);
>+	I915_WRITE(ICL_PORT_CL_DW10(phy), val);
>+}
>+
>+static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val)
>+{
>+	bool ddi_a_present = i915->vbt.ddi_port_info[PORT_A].child != NULL;
>+	bool ddi_d_present = i915->vbt.ddi_port_info[PORT_D].child != NULL;
>+	bool dsi_present = intel_bios_is_dsi_present(i915, NULL);
>+
>+	/*
>+	 * VBT's 'dvo port' field for child devices references the DDI, not
>+	 * the PHY.  So if combo PHY A is wired up to drive an external
>+	 * display, we should see a child device present on PORT_D and
>+	 * nothing on PORT_A and no DSI.
>+	 */
>+	if (ddi_d_present && !ddi_a_present && !dsi_present)
>+		return val | ICL_PHY_MISC_MUX_DDID;
>+
>+	/*
>+	 * If we encounter a VBT that claims to have an external display on
>+	 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message
>+	 * in the log and let the internal display win.
>+	 */
>+	if (ddi_d_present)
>+		DRM_ERROR("VBT claims to have both internal and external displays on PHY A.  Configuring for internal.\n");
>+
>+	return val & ~ICL_PHY_MISC_MUX_DDID;
> }
> 
> static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
> {
>-	enum port port;
>+	enum phy phy;
> 
>-	for_each_combo_port(dev_priv, port) {
>+	for_each_combo_phy(dev_priv, phy) {
> 		u32 val;
> 
>-		if (icl_combo_phy_verify_state(dev_priv, port)) {
>-			DRM_DEBUG_DRIVER("Port %c combo PHY already enabled, won't reprogram it.\n",
>-					 port_name(port));
>+		if (icl_combo_phy_verify_state(dev_priv, phy)) {
>+			DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n",
>+					 phy_name(phy));
> 			continue;
> 		}
> 
>-		val = I915_READ(ICL_PHY_MISC(port));
>+		/*
>+		 * Although EHL adds a combo PHY C, there's no PHY_MISC
>+		 * register for it and no need to program the
>+		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
>+		 */
>+		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
>+			goto skip_phy_misc;
>+
>+		/*
>+		 * EHL's combo PHY A can be hooked up to either an external
>+		 * display (via DDI-D) or an internal display (via DDI-A or
>+		 * the DSI DPHY).  This is a motherboard design decision that
>+		 * can't be changed on the fly, so initialize the PHY's mux
>+		 * based on whether our VBT indicates the presence of any
>+		 * "internal" child devices.
>+		 */
>+		val = I915_READ(ICL_PHY_MISC(phy));
>+		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A)
>+			val = ehl_combo_phy_a_mux(dev_priv, val);
> 		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
>-		I915_WRITE(ICL_PHY_MISC(port), val);
>+		I915_WRITE(ICL_PHY_MISC(phy), val);
> 
>-		cnl_set_procmon_ref_values(dev_priv, port);
>+skip_phy_misc:
>+		cnl_set_procmon_ref_values(dev_priv, phy);
> 
>-		if (port == PORT_A) {
>-			val = I915_READ(ICL_PORT_COMP_DW8(port));
>+		if (phy == PHY_A) {
>+			val = I915_READ(ICL_PORT_COMP_DW8(phy));
> 			val |= IREFGEN;
>-			I915_WRITE(ICL_PORT_COMP_DW8(port), val);
>+			I915_WRITE(ICL_PORT_COMP_DW8(phy), val);
> 		}
> 
>-		val = I915_READ(ICL_PORT_COMP_DW0(port));
>+		val = I915_READ(ICL_PORT_COMP_DW0(phy));
> 		val |= COMP_INIT;
>-		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
>+		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
> 
>-		val = I915_READ(ICL_PORT_CL_DW5(port));
>+		val = I915_READ(ICL_PORT_CL_DW5(phy));
> 		val |= CL_POWER_DOWN_ENABLE;
>-		I915_WRITE(ICL_PORT_CL_DW5(port), val);
>+		I915_WRITE(ICL_PORT_CL_DW5(phy), val);
> 	}
> }
> 
> static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
> {
>-	enum port port;
>+	enum phy phy;
> 
>-	for_each_combo_port_reverse(dev_priv, port) {
>+	for_each_combo_phy_reverse(dev_priv, phy) {
> 		u32 val;
> 
>-		if (port == PORT_A &&
>-		    !icl_combo_phy_verify_state(dev_priv, port))
>-			DRM_WARN("Port %c combo PHY HW state changed unexpectedly\n",
>-				 port_name(port));
>+		if (phy == PHY_A &&
>+		    !icl_combo_phy_verify_state(dev_priv, phy))
>+			DRM_WARN("Combo PHY %c HW state changed unexpectedly\n",
>+				 phy_name(phy));
>+
>+		/*
>+		 * Although EHL adds a combo PHY C, there's no PHY_MISC
>+		 * register for it and no need to program the
>+		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
>+		 */
>+		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
>+			goto skip_phy_misc;
> 
>-		val = I915_READ(ICL_PHY_MISC(port));
>+		val = I915_READ(ICL_PHY_MISC(phy));
> 		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
>-		I915_WRITE(ICL_PHY_MISC(port), val);
>+		I915_WRITE(ICL_PHY_MISC(phy), val);
> 
>-		val = I915_READ(ICL_PORT_COMP_DW0(port));
>+skip_phy_misc:
>+		val = I915_READ(ICL_PORT_COMP_DW0(phy));
> 		val &= ~COMP_INIT;
>-		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
>+		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
> 	}
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_combo_phy.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_combo_phy.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_combo_phy.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_combo_phy.h	2019-08-31 15:01:12.015736182 -0500
>@@ -7,14 +7,14 @@
> #define __INTEL_COMBO_PHY_H__
> 
> #include <linux/types.h>
>-#include <drm/i915_drm.h>
> 
> struct drm_i915_private;
>+enum phy;
> 
> void intel_combo_phy_init(struct drm_i915_private *dev_priv);
> void intel_combo_phy_uninit(struct drm_i915_private *dev_priv);
> void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
>-				    enum port port, bool is_dsi,
>+				    enum phy phy, bool is_dsi,
> 				    int lane_count, bool lane_reversal);
> 
> #endif /* __INTEL_COMBO_PHY_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_connector.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_connector.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_connector.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_connector.c	2019-08-31 15:01:12.015736182 -0500
>@@ -118,7 +118,7 @@
> 	if (ret)
> 		goto err;
> 
>-	if (i915_inject_load_failure()) {
>+	if (i915_inject_probe_failure()) {
> 		ret = -EFAULT;
> 		goto err_backlight;
> 	}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_ddi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_ddi.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_ddi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_ddi.c	2019-08-31 15:01:12.247736203 -0500
>@@ -45,6 +45,7 @@
> #include "intel_lspcon.h"
> #include "intel_panel.h"
> #include "intel_psr.h"
>+#include "intel_tc.h"
> #include "intel_vdsc.h"
> 
> struct ddi_buf_trans {
>@@ -846,8 +847,8 @@
> }
> 
> static const struct cnl_ddi_buf_trans *
>-icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
>-			int type, int rate, int *n_entries)
>+icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
>+			int *n_entries)
> {
> 	if (type == INTEL_OUTPUT_HDMI) {
> 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
>@@ -867,12 +868,13 @@
> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
> {
> 	int n_entries, level, default_entry;
>+	enum phy phy = intel_port_to_phy(dev_priv, port);
> 
> 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
> 
> 	if (INTEL_GEN(dev_priv) >= 11) {
>-		if (intel_port_is_combophy(dev_priv, port))
>-			icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
>+		if (intel_phy_is_combo(dev_priv, phy))
>+			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
> 						0, &n_entries);
> 		else
> 			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
>@@ -1486,9 +1488,10 @@
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
> 	enum port port = encoder->port;
>+	enum phy phy = intel_port_to_phy(dev_priv, port);
> 	int link_clock;
> 
>-	if (intel_port_is_combophy(dev_priv, port)) {
>+	if (intel_phy_is_combo(dev_priv, phy)) {
> 		link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
> 	} else {
> 		enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
>@@ -1770,7 +1773,10 @@
> 
> 	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
> 	temp = TRANS_DDI_FUNC_ENABLE;
>-	temp |= TRANS_DDI_SELECT_PORT(port);
>+	if (INTEL_GEN(dev_priv) >= 12)
>+		temp |= TGL_TRANS_DDI_SELECT_PORT(port);
>+	else
>+		temp |= TRANS_DDI_SELECT_PORT(port);
> 
> 	switch (crtc_state->pipe_bpp) {
> 	case 18:
>@@ -1850,8 +1856,13 @@
> 	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> 	u32 val = I915_READ(reg);
> 
>-	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
>-	val |= TRANS_DDI_PORT_NONE;
>+	if (INTEL_GEN(dev_priv) >= 12) {
>+		val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
>+			 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
>+	} else {
>+		val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
>+			 TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
>+	}
> 	I915_WRITE(reg, val);
> 
> 	if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
>@@ -2003,10 +2014,19 @@
> 	mst_pipe_mask = 0;
> 	for_each_pipe(dev_priv, p) {
> 		enum transcoder cpu_transcoder = (enum transcoder)p;
>+		unsigned int port_mask, ddi_select;
>+
>+		if (INTEL_GEN(dev_priv) >= 12) {
>+			port_mask = TGL_TRANS_DDI_PORT_MASK;
>+			ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
>+		} else {
>+			port_mask = TRANS_DDI_PORT_MASK;
>+			ddi_select = TRANS_DDI_SELECT_PORT(port);
>+		}
> 
> 		tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> 
>-		if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))
>+		if ((tmp & port_mask) != ddi_select)
> 			continue;
> 
> 		if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
>@@ -2085,6 +2105,7 @@
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_digital_port *dig_port;
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> 
> 	/*
> 	 * TODO: Add support for MST encoders. Atm, the following should never
>@@ -2102,7 +2123,7 @@
> 	 * ports.
> 	 */
> 	if (intel_crtc_has_dp_encoder(crtc_state) ||
>-	    intel_port_is_tc(dev_priv, encoder->port))
>+	    intel_phy_is_tc(dev_priv, phy))
> 		intel_display_power_get(dev_priv,
> 					intel_ddi_main_link_aux_domain(dig_port));
> 
>@@ -2122,9 +2143,14 @@
> 	enum port port = encoder->port;
> 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> 
>-	if (cpu_transcoder != TRANSCODER_EDP)
>-		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>-			   TRANS_CLK_SEL_PORT(port));
>+	if (cpu_transcoder != TRANSCODER_EDP) {
>+		if (INTEL_GEN(dev_priv) >= 12)
>+			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>+				   TGL_TRANS_CLK_SEL_PORT(port));
>+		else
>+			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>+				   TRANS_CLK_SEL_PORT(port));
>+	}
> }
> 
> void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
>@@ -2132,9 +2158,14 @@
> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> 
>-	if (cpu_transcoder != TRANSCODER_EDP)
>-		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>-			   TRANS_CLK_SEL_DISABLED);
>+	if (cpu_transcoder != TRANSCODER_EDP) {
>+		if (INTEL_GEN(dev_priv) >= 12)
>+			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>+				   TGL_TRANS_CLK_SEL_DISABLED);
>+		else
>+			I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
>+				   TRANS_CLK_SEL_DISABLED);
>+	}
> }
> 
> static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
>@@ -2227,11 +2258,12 @@
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> 	enum port port = encoder->port;
>+	enum phy phy = intel_port_to_phy(dev_priv, port);
> 	int n_entries;
> 
> 	if (INTEL_GEN(dev_priv) >= 11) {
>-		if (intel_port_is_combophy(dev_priv, port))
>-			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
>+		if (intel_phy_is_combo(dev_priv, phy))
>+			icl_get_combo_buf_trans(dev_priv, encoder->type,
> 						intel_dp->link_rate, &n_entries);
> 		else
> 			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
>@@ -2413,15 +2445,15 @@
> }
> 
> static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
>-					u32 level, enum port port, int type,
>+					u32 level, enum phy phy, int type,
> 					int rate)
> {
> 	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> 	u32 n_entries, val;
> 	int ln;
> 
>-	ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
>-						   rate, &n_entries);
>+	ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
>+						   &n_entries);
> 	if (!ddi_translations)
> 		return;
> 
>@@ -2431,41 +2463,41 @@
> 	}
> 
> 	/* Set PORT_TX_DW5 */
>-	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>+	val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> 	val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> 		  TAP2_DISABLE | TAP3_DISABLE);
> 	val |= SCALING_MODE_SEL(0x2);
> 	val |= RTERM_SELECT(0x6);
> 	val |= TAP3_DISABLE;
>-	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>+	I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
> 
> 	/* Program PORT_TX_DW2 */
>-	val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
>+	val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
> 	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> 		 RCOMP_SCALAR_MASK);
> 	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> 	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> 	/* Program Rcomp scalar for every table entry */
> 	val |= RCOMP_SCALAR(0x98);
>-	I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
>+	I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
> 
> 	/* Program PORT_TX_DW4 */
> 	/* We cannot write to GRP. It would overwrite individual loadgen. */
> 	for (ln = 0; ln <= 3; ln++) {
>-		val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
>+		val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
> 		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> 			 CURSOR_COEFF_MASK);
> 		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> 		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> 		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
>-		I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
>+		I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
> 	}
> 
> 	/* Program PORT_TX_DW7 */
>-	val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
>+	val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
> 	val &= ~N_SCALAR_MASK;
> 	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
>-	I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
>+	I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
> }
> 
> static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>@@ -2473,7 +2505,7 @@
> 					      enum intel_output_type type)
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>-	enum port port = encoder->port;
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> 	int width = 0;
> 	int rate = 0;
> 	u32 val;
>@@ -2494,12 +2526,12 @@
> 	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
> 	 * else clear to 0b.
> 	 */
>-	val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
>+	val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
> 	if (type == INTEL_OUTPUT_HDMI)
> 		val &= ~COMMON_KEEPER_EN;
> 	else
> 		val |= COMMON_KEEPER_EN;
>-	I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
>+	I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
> 
> 	/* 2. Program loadgen select */
> 	/*
>@@ -2509,33 +2541,33 @@
> 	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
> 	 */
> 	for (ln = 0; ln <= 3; ln++) {
>-		val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
>+		val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
> 		val &= ~LOADGEN_SELECT;
> 
> 		if ((rate <= 600000 && width == 4 && ln >= 1) ||
> 		    (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
> 			val |= LOADGEN_SELECT;
> 		}
>-		I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
>+		I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
> 	}
> 
> 	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
>-	val = I915_READ(ICL_PORT_CL_DW5(port));
>+	val = I915_READ(ICL_PORT_CL_DW5(phy));
> 	val |= SUS_CLOCK_CONFIG;
>-	I915_WRITE(ICL_PORT_CL_DW5(port), val);
>+	I915_WRITE(ICL_PORT_CL_DW5(phy), val);
> 
> 	/* 4. Clear training enable to change swing values */
>-	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>+	val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> 	val &= ~TX_TRAINING_EN;
>-	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>+	I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
> 
> 	/* 5. Program swing and de-emphasis */
>-	icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
>+	icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
> 
> 	/* 6. Set training enable to trigger update */
>-	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
>+	val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> 	val |= TX_TRAINING_EN;
>-	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
>+	I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
> }
> 
> static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>@@ -2663,9 +2695,9 @@
> 				    enum intel_output_type type)
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>-	enum port port = encoder->port;
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> 
>-	if (intel_port_is_combophy(dev_priv, port))
>+	if (intel_phy_is_combo(dev_priv, phy))
> 		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
> 	else
> 		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
>@@ -2728,12 +2760,13 @@
> 
> static inline
> u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
>-			      enum port port)
>+			      enum phy phy)
> {
>-	if (intel_port_is_combophy(dev_priv, port)) {
>-		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
>-	} else if (intel_port_is_tc(dev_priv, port)) {
>-		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>+	if (intel_phy_is_combo(dev_priv, phy)) {
>+		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
>+	} else if (intel_phy_is_tc(dev_priv, phy)) {
>+		enum tc_port tc_port = intel_port_to_tc(dev_priv,
>+							(enum port)phy);
> 
> 		return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
> 	}
>@@ -2746,23 +2779,33 @@
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>-	enum port port = encoder->port;
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> 	u32 val;
> 
> 	mutex_lock(&dev_priv->dpll_lock);
> 
>-	val = I915_READ(DPCLKA_CFGCR0_ICL);
>-	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
>+	val = I915_READ(ICL_DPCLKA_CFGCR0);
>+	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
> 
>-	if (intel_port_is_combophy(dev_priv, port)) {
>-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
>-		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>-		POSTING_READ(DPCLKA_CFGCR0_ICL);
>+	if (intel_phy_is_combo(dev_priv, phy)) {
>+		/*
>+		 * Even though this register references DDIs, note that we
>+		 * want to pass the PHY rather than the port (DDI).  For
>+		 * ICL, port=phy in all cases so it doesn't matter, but for
>+		 * EHL the bspec notes the following:
>+		 *
>+		 *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
>+		 *   Clock Select chooses the PLL for both DDIA and DDID and
>+		 *   drives port A in all cases."
>+		 */
>+		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
>+		val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
>+		I915_WRITE(ICL_DPCLKA_CFGCR0, val);
>+		POSTING_READ(ICL_DPCLKA_CFGCR0);
> 	}
> 
>-	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
>-	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>+	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
>+	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
> 
> 	mutex_unlock(&dev_priv->dpll_lock);
> }
>@@ -2770,14 +2813,14 @@
> static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>-	enum port port = encoder->port;
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> 	u32 val;
> 
> 	mutex_lock(&dev_priv->dpll_lock);
> 
>-	val = I915_READ(DPCLKA_CFGCR0_ICL);
>-	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
>-	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>+	val = I915_READ(ICL_DPCLKA_CFGCR0);
>+	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
>+	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
> 
> 	mutex_unlock(&dev_priv->dpll_lock);
> }
>@@ -2835,11 +2878,13 @@
> 		ddi_clk_needed = false;
> 	}
> 
>-	val = I915_READ(DPCLKA_CFGCR0_ICL);
>+	val = I915_READ(ICL_DPCLKA_CFGCR0);
> 	for_each_port_masked(port, port_mask) {
>+		enum phy phy = intel_port_to_phy(dev_priv, port);
>+
> 		bool ddi_clk_ungated = !(val &
> 					 icl_dpclka_cfgcr0_clk_off(dev_priv,
>-								   port));
>+								   phy));
> 
> 		if (ddi_clk_needed == ddi_clk_ungated)
> 			continue;
>@@ -2851,10 +2896,10 @@
> 		if (WARN_ON(ddi_clk_needed))
> 			continue;
> 
>-		DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
>-			 port_name(port));
>-		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
>-		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>+		DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
>+			 phy_name(port));
>+		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
>+		I915_WRITE(ICL_DPCLKA_CFGCR0, val);
> 	}
> }
> 
>@@ -2863,6 +2908,7 @@
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	enum port port = encoder->port;
>+	enum phy phy = intel_port_to_phy(dev_priv, port);
> 	u32 val;
> 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> 
>@@ -2872,7 +2918,7 @@
> 	mutex_lock(&dev_priv->dpll_lock);
> 
> 	if (INTEL_GEN(dev_priv) >= 11) {
>-		if (!intel_port_is_combophy(dev_priv, port))
>+		if (!intel_phy_is_combo(dev_priv, phy))
> 			I915_WRITE(DDI_CLK_SEL(port),
> 				   icl_pll_to_ddi_clk_sel(encoder, crtc_state));
> 	} else if (IS_CANNONLAKE(dev_priv)) {
>@@ -2912,9 +2958,10 @@
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	enum port port = encoder->port;
>+	enum phy phy = intel_port_to_phy(dev_priv, port);
> 
> 	if (INTEL_GEN(dev_priv) >= 11) {
>-		if (!intel_port_is_combophy(dev_priv, port))
>+		if (!intel_phy_is_combo(dev_priv, phy))
> 			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
> 	} else if (IS_CANNONLAKE(dev_priv)) {
> 		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
>@@ -2995,25 +3042,22 @@
> {
> 	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
> 	enum port port = intel_dig_port->base.port;
>-	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>-	u32 ln0, ln1, lane_info;
>+	u32 ln0, ln1, lane_mask;
> 
>-	if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
>+	if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
> 		return;
> 
> 	ln0 = I915_READ(MG_DP_MODE(0, port));
> 	ln1 = I915_READ(MG_DP_MODE(1, port));
> 
>-	switch (intel_dig_port->tc_type) {
>-	case TC_PORT_TYPEC:
>+	switch (intel_dig_port->tc_mode) {
>+	case TC_PORT_DP_ALT:
> 		ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
> 		ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
> 
>-		lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
>-			     DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
>-			    DP_LANE_ASSIGNMENT_SHIFT(tc_port);
>+		lane_mask = intel_tc_port_get_lane_mask(intel_dig_port);
> 
>-		switch (lane_info) {
>+		switch (lane_mask) {
> 		case 0x1:
> 		case 0x4:
> 			break;
>@@ -3038,7 +3082,7 @@
> 			       MG_DP_MODE_CFG_DP_X2_MODE;
> 			break;
> 		default:
>-			MISSING_CASE(lane_info);
>+			MISSING_CASE(lane_mask);
> 		}
> 		break;
> 
>@@ -3048,7 +3092,7 @@
> 		break;
> 
> 	default:
>-		MISSING_CASE(intel_dig_port->tc_type);
>+		MISSING_CASE(intel_dig_port->tc_mode);
> 		return;
> 	}
> 
>@@ -3110,6 +3154,7 @@
> 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	enum port port = encoder->port;
>+	enum phy phy = intel_port_to_phy(dev_priv, port);
> 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> 	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> 	int level = intel_ddi_dp_level(intel_dp);
>@@ -3123,7 +3168,10 @@
> 
> 	intel_ddi_clk_select(encoder, crtc_state);
> 
>-	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
>+	if (!intel_phy_is_tc(dev_priv, phy) ||
>+	    dig_port->tc_mode != TC_PORT_TBT_ALT)
>+		intel_display_power_get(dev_priv,
>+					dig_port->ddi_io_power_domain);
> 
> 	icl_program_mg_dp_mode(dig_port);
> 	icl_disable_phy_clock_gating(dig_port);
>@@ -3138,11 +3186,11 @@
> 	else
> 		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
> 
>-	if (intel_port_is_combophy(dev_priv, port)) {
>+	if (intel_phy_is_combo(dev_priv, phy)) {
> 		bool lane_reversal =
> 			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> 
>-		intel_combo_phy_power_up_lanes(dev_priv, port, false,
>+		intel_combo_phy_power_up_lanes(dev_priv, phy, false,
> 					       crtc_state->lane_count,
> 					       lane_reversal);
> 	}
>@@ -3290,6 +3338,7 @@
> 	struct intel_dp *intel_dp = &dig_port->dp;
> 	bool is_mst = intel_crtc_has_type(old_crtc_state,
> 					  INTEL_OUTPUT_DP_MST);
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> 
> 	if (!is_mst) {
> 		intel_ddi_disable_pipe_clock(old_crtc_state);
>@@ -3305,8 +3354,10 @@
> 	intel_edp_panel_vdd_on(intel_dp);
> 	intel_edp_panel_off(intel_dp);
> 
>-	intel_display_power_put_unchecked(dev_priv,
>-					  dig_port->ddi_io_power_domain);
>+	if (!intel_phy_is_tc(dev_priv, phy) ||
>+	    dig_port->tc_mode != TC_PORT_TBT_ALT)
>+		intel_display_power_put_unchecked(dev_priv,
>+						  dig_port->ddi_io_power_domain);
> 
> 	intel_ddi_clk_disable(encoder);
> }
>@@ -3511,7 +3562,8 @@
> 	/* Enable hdcp if it's desired */
> 	if (conn_state->content_protection ==
> 	    DRM_MODE_CONTENT_PROTECTION_DESIRED)
>-		intel_hdcp_enable(to_intel_connector(conn_state->connector));
>+		intel_hdcp_enable(to_intel_connector(conn_state->connector),
>+				  (u8)conn_state->hdcp_content_type);
> }
> 
> static void intel_disable_ddi_dp(struct intel_encoder *encoder,
>@@ -3580,44 +3632,65 @@
> 				  const struct intel_crtc_state *crtc_state,
> 				  const struct drm_connector_state *conn_state)
> {
>+	struct intel_connector *connector =
>+				to_intel_connector(conn_state->connector);
>+	struct intel_hdcp *hdcp = &connector->hdcp;
>+	bool content_protection_type_changed =
>+			(conn_state->hdcp_content_type != hdcp->content_type &&
>+			 conn_state->content_protection !=
>+			 DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
>+
> 	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> 		intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
> 
>+	/*
>+	 * During the HDCP encryption session if Type change is requested,
>+	 * disable the HDCP and reenable it with new TYPE value.
>+	 */
> 	if (conn_state->content_protection ==
>-	    DRM_MODE_CONTENT_PROTECTION_DESIRED)
>-		intel_hdcp_enable(to_intel_connector(conn_state->connector));
>-	else if (conn_state->content_protection ==
>-		 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
>-		intel_hdcp_disable(to_intel_connector(conn_state->connector));
>+	    DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
>+	    content_protection_type_changed)
>+		intel_hdcp_disable(connector);
>+
>+	/*
>+	 * Mark the hdcp state as DESIRED after the hdcp disable of type
>+	 * change procedure.
>+	 */
>+	if (content_protection_type_changed) {
>+		mutex_lock(&hdcp->mutex);
>+		hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
>+		schedule_work(&hdcp->prop_work);
>+		mutex_unlock(&hdcp->mutex);
>+	}
>+
>+	if (conn_state->content_protection ==
>+	    DRM_MODE_CONTENT_PROTECTION_DESIRED ||
>+	    content_protection_type_changed)
>+		intel_hdcp_enable(connector, (u8)conn_state->hdcp_content_type);
> }
> 
>-static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
>-					 const struct intel_crtc_state *pipe_config,
>-					 enum port port)
>-{
>-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>-	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
>-	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>-	u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
>-	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
>+static void
>+intel_ddi_update_prepare(struct intel_atomic_state *state,
>+			 struct intel_encoder *encoder,
>+			 struct intel_crtc *crtc)
>+{
>+	struct intel_crtc_state *crtc_state =
>+		crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
>+	int required_lanes = crtc_state ? crtc_state->lane_count : 1;
>+
>+	WARN_ON(crtc && crtc->active);
>+
>+	intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
>+	if (crtc_state && crtc_state->base.active)
>+		intel_update_active_dpll(state, crtc, encoder);
>+}
> 
>-	val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
>-	switch (pipe_config->lane_count) {
>-	case 1:
>-		val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
>-		DFLEXDPMLE1_DPMLETC_ML0(tc_port);
>-		break;
>-	case 2:
>-		val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
>-		DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
>-		break;
>-	case 4:
>-		val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
>-		break;
>-	default:
>-		MISSING_CASE(pipe_config->lane_count);
>-	}
>-	I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
>+static void
>+intel_ddi_update_complete(struct intel_atomic_state *state,
>+			  struct intel_encoder *encoder,
>+			  struct intel_crtc *crtc)
>+{
>+	intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
> }
> 
> static void
>@@ -3627,26 +3700,25 @@
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
>-	enum port port = encoder->port;
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+	bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
> 
>-	if (intel_crtc_has_dp_encoder(crtc_state) ||
>-	    intel_port_is_tc(dev_priv, encoder->port))
>+	if (is_tc_port)
>+		intel_tc_port_get_link(dig_port, crtc_state->lane_count);
>+
>+	if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
> 		intel_display_power_get(dev_priv,
> 					intel_ddi_main_link_aux_domain(dig_port));
> 
>-	if (IS_GEN9_LP(dev_priv))
>+	if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
>+		/*
>+		 * Program the lane count for static/dynamic connections on
>+		 * Type-C ports.  Skip this step for TBT.
>+		 */
>+		intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
>+	else if (IS_GEN9_LP(dev_priv))
> 		bxt_ddi_phy_set_lane_optim_mask(encoder,
> 						crtc_state->lane_lat_optim_mask);
>-
>-	/*
>-	 * Program the lane count for static/dynamic connections on Type-C ports.
>-	 * Skip this step for TBT.
>-	 */
>-	if (dig_port->tc_type == TC_PORT_UNKNOWN ||
>-	    dig_port->tc_type == TC_PORT_TBT)
>-		return;
>-
>-	intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
> }
> 
> static void
>@@ -3656,11 +3728,15 @@
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+	bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
> 
>-	if (intel_crtc_has_dp_encoder(crtc_state) ||
>-	    intel_port_is_tc(dev_priv, encoder->port))
>+	if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
> 		intel_display_power_put_unchecked(dev_priv,
> 						  intel_ddi_main_link_aux_domain(dig_port));
>+
>+	if (is_tc_port)
>+		intel_tc_port_put_link(dig_port);
> }
> 
> static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
>@@ -3737,7 +3813,6 @@
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
> 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
>-	struct intel_digital_port *intel_dig_port;
> 	u32 temp, flags = 0;
> 
> 	/* XXX: DSI transcoder paranoia */
>@@ -3776,7 +3851,6 @@
> 	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
> 	case TRANS_DDI_MODE_SELECT_HDMI:
> 		pipe_config->has_hdmi_sink = true;
>-		intel_dig_port = enc_to_dig_port(&encoder->base);
> 
> 		pipe_config->infoframes.enable |=
> 			intel_hdmi_infoframes_enabled(encoder, pipe_config);
>@@ -3914,49 +3988,18 @@
> 	return 0;
> }
> 
>-static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
>-{
>-	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
>-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>-
>-	intel_dp_encoder_suspend(encoder);
>-
>-	/*
>-	 * TODO: disconnect also from USB DP alternate mode once we have a
>-	 * way to handle the modeset restore in that mode during resume
>-	 * even if the sink has disappeared while being suspended.
>-	 */
>-	if (dig_port->tc_legacy_port)
>-		icl_tc_phy_disconnect(i915, dig_port);
>-}
>-
>-static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
>-{
>-	struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
>-	struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
>-
>-	if (intel_port_is_tc(i915, dig_port->base.port))
>-		intel_digital_port_connected(&dig_port->base);
>-
>-	intel_dp_encoder_reset(drm_encoder);
>-}
>-
> static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
> {
> 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>-	struct drm_i915_private *i915 = to_i915(encoder->dev);
> 
> 	intel_dp_encoder_flush_work(encoder);
> 
>-	if (intel_port_is_tc(i915, dig_port->base.port))
>-		icl_tc_phy_disconnect(i915, dig_port);
>-
> 	drm_encoder_cleanup(encoder);
> 	kfree(dig_port);
> }
> 
> static const struct drm_encoder_funcs intel_ddi_funcs = {
>-	.reset = intel_ddi_encoder_reset,
>+	.reset = intel_dp_encoder_reset,
> 	.destroy = intel_ddi_encoder_destroy,
> };
> 
>@@ -4081,14 +4124,17 @@
> 	return modeset_pipe(&crtc->base, ctx);
> }
> 
>-static bool intel_ddi_hotplug(struct intel_encoder *encoder,
>-			      struct intel_connector *connector)
>+static enum intel_hotplug_state
>+intel_ddi_hotplug(struct intel_encoder *encoder,
>+		  struct intel_connector *connector,
>+		  bool irq_received)
> {
>+	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> 	struct drm_modeset_acquire_ctx ctx;
>-	bool changed;
>+	enum intel_hotplug_state state;
> 	int ret;
> 
>-	changed = intel_encoder_hotplug(encoder, connector);
>+	state = intel_encoder_hotplug(encoder, connector, irq_received);
> 
> 	drm_modeset_acquire_init(&ctx, 0);
> 
>@@ -4110,7 +4156,27 @@
> 	drm_modeset_acquire_fini(&ctx);
> 	WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
> 
>-	return changed;
>+	/*
>+	 * Unpowered type-c dongles can take some time to boot and be
>+	 * responsible, so here giving some time to those dongles to power up
>+	 * and then retrying the probe.
>+	 *
>+	 * On many platforms the HDMI live state signal is known to be
>+	 * unreliable, so we can't use it to detect if a sink is connected or
>+	 * not. Instead we detect if it's connected based on whether we can
>+	 * read the EDID or not. That in turn has a problem during disconnect,
>+	 * since the HPD interrupt may be raised before the DDC lines get
>+	 * disconnected (due to how the required length of DDC vs. HPD
>+	 * connector pins are specified) and so we'll still be able to get a
>+	 * valid EDID. To solve this schedule another detection cycle if this
>+	 * time around we didn't detect any change in the sink's connection
>+	 * status.
>+	 */
>+	if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
>+	    !dig_port->dp.is_mst)
>+		state = INTEL_HOTPLUG_RETRY;
>+
>+	return state;
> }
> 
> static struct intel_connector *
>@@ -4198,6 +4264,7 @@
> 	struct drm_encoder *encoder;
> 	bool init_hdmi, init_dp, init_lspcon = false;
> 	enum pipe pipe;
>+	enum phy phy = intel_port_to_phy(dev_priv, port);
> 
> 	init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
> 	init_dp = port_info->supports_dp;
>@@ -4242,7 +4309,7 @@
> 	intel_encoder->update_pipe = intel_ddi_update_pipe;
> 	intel_encoder->get_hw_state = intel_ddi_get_hw_state;
> 	intel_encoder->get_config = intel_ddi_get_config;
>-	intel_encoder->suspend = intel_ddi_encoder_suspend;
>+	intel_encoder->suspend = intel_dp_encoder_suspend;
> 	intel_encoder->get_power_domains = intel_ddi_get_power_domains;
> 	intel_encoder->type = INTEL_OUTPUT_DDI;
> 	intel_encoder->power_domain = intel_port_to_power_domain(port);
>@@ -4261,9 +4328,15 @@
> 	intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
> 	intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
> 
>-	intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
>-					 !port_info->supports_typec_usb &&
>-					 !port_info->supports_tbt;
>+	if (intel_phy_is_tc(dev_priv, phy)) {
>+		bool is_legacy = !port_info->supports_typec_usb &&
>+				 !port_info->supports_tbt;
>+
>+		intel_tc_port_init(intel_dig_port, is_legacy);
>+
>+		intel_encoder->update_prepare = intel_ddi_update_prepare;
>+		intel_encoder->update_complete = intel_ddi_update_complete;
>+	}
> 
> 	switch (port) {
> 	case PORT_A:
>@@ -4290,6 +4363,18 @@
> 		intel_dig_port->ddi_io_power_domain =
> 			POWER_DOMAIN_PORT_DDI_F_IO;
> 		break;
>+	case PORT_G:
>+		intel_dig_port->ddi_io_power_domain =
>+			POWER_DOMAIN_PORT_DDI_G_IO;
>+		break;
>+	case PORT_H:
>+		intel_dig_port->ddi_io_power_domain =
>+			POWER_DOMAIN_PORT_DDI_H_IO;
>+		break;
>+	case PORT_I:
>+		intel_dig_port->ddi_io_power_domain =
>+			POWER_DOMAIN_PORT_DDI_I_IO;
>+		break;
> 	default:
> 		MISSING_CASE(port);
> 	}
>@@ -4324,9 +4409,6 @@
> 
> 	intel_infoframe_init(intel_dig_port);
> 
>-	if (intel_port_is_tc(dev_priv, port))
>-		intel_digital_port_connected(intel_encoder);
>-
> 	return;
> 
> err:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_display.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_display.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_display.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_display.c	2019-08-31 15:01:12.017736182 -0500
>@@ -78,6 +78,7 @@
> #include "intel_quirks.h"
> #include "intel_sideband.h"
> #include "intel_sprite.h"
>+#include "intel_tc.h"
> 
> /* Primary plane formats for gen <= 3 */
> static const u32 i8xx_primary_formats[] = {
>@@ -515,9 +516,9 @@
> }
> 
> static bool
>-needs_modeset(const struct drm_crtc_state *state)
>+needs_modeset(const struct intel_crtc_state *state)
> {
>-	return drm_atomic_crtc_needs_modeset(state);
>+	return drm_atomic_crtc_needs_modeset(&state->base);
> }
> 
> /*
>@@ -3715,10 +3716,27 @@
> 	return 0;
> }
> 
>+static bool i9xx_plane_has_windowing(struct intel_plane *plane)
>+{
>+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>+	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
>+
>+	if (IS_CHERRYVIEW(dev_priv))
>+		return i9xx_plane == PLANE_B;
>+	else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
>+		return false;
>+	else if (IS_GEN(dev_priv, 4))
>+		return i9xx_plane == PLANE_C;
>+	else
>+		return i9xx_plane == PLANE_B ||
>+			i9xx_plane == PLANE_C;
>+}
>+
> static int
> i9xx_plane_check(struct intel_crtc_state *crtc_state,
> 		 struct intel_plane_state *plane_state)
> {
>+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> 	int ret;
> 
> 	ret = chv_plane_check_rotation(plane_state);
>@@ -3729,7 +3747,8 @@
> 						  &crtc_state->base,
> 						  DRM_PLANE_HELPER_NO_SCALING,
> 						  DRM_PLANE_HELPER_NO_SCALING,
>-						  false, true);
>+						  i9xx_plane_has_windowing(plane),
>+						  true);
> 	if (ret)
> 		return ret;
> 
>@@ -3758,6 +3777,10 @@
> 	u32 linear_offset;
> 	int x = plane_state->color_plane[0].x;
> 	int y = plane_state->color_plane[0].y;
>+	int crtc_x = plane_state->base.dst.x1;
>+	int crtc_y = plane_state->base.dst.y1;
>+	int crtc_w = drm_rect_width(&plane_state->base.dst);
>+	int crtc_h = drm_rect_height(&plane_state->base.dst);
> 	unsigned long irqflags;
> 	u32 dspaddr_offset;
> 	u32 dspcntr;
>@@ -3776,18 +3799,18 @@
> 	I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
> 
> 	if (INTEL_GEN(dev_priv) < 4) {
>-		/* pipesrc and dspsize control the size that is scaled from,
>-		 * which should always be the user's requested size.
>+		/*
>+		 * PLANE_A doesn't actually have a full window
>+		 * generator but let's assume we still need to
>+		 * program whatever is there.
> 		 */
>-		I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
>+		I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
> 		I915_WRITE_FW(DSPSIZE(i9xx_plane),
>-			      ((crtc_state->pipe_src_h - 1) << 16) |
>-			      (crtc_state->pipe_src_w - 1));
>+			      ((crtc_h - 1) << 16) | (crtc_w - 1));
> 	} else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
>-		I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);
>+		I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x);
> 		I915_WRITE_FW(PRIMSIZE(i9xx_plane),
>-			      ((crtc_state->pipe_src_h - 1) << 16) |
>-			      (crtc_state->pipe_src_w - 1));
>+			      ((crtc_h - 1) << 16) | (crtc_w - 1));
> 		I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
> 	}
> 
>@@ -3950,10 +3973,10 @@
> 	case DRM_FORMAT_XRGB8888:
> 	case DRM_FORMAT_ARGB8888:
> 		return PLANE_CTL_FORMAT_XRGB_8888;
>+	case DRM_FORMAT_XBGR2101010:
>+		return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
> 	case DRM_FORMAT_XRGB2101010:
> 		return PLANE_CTL_FORMAT_XRGB_2101010;
>-	case DRM_FORMAT_XBGR2101010:
>-		return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> 	case DRM_FORMAT_XBGR16161616F:
> 	case DRM_FORMAT_ABGR16161616F:
> 		return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
>@@ -4248,12 +4271,13 @@
> 		return;
> 
> 	/* We have a modeset vs reset deadlock, defensively unbreak it. */
>-	set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
>-	wake_up_all(&dev_priv->gpu_error.wait_queue);
>+	set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
>+	smp_mb__after_atomic();
>+	wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
> 
> 	if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
> 		DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
>-		i915_gem_set_wedged(dev_priv);
>+		intel_gt_set_wedged(&dev_priv->gt);
> 	}
> 
> 	/*
>@@ -4299,7 +4323,7 @@
> 	int ret;
> 
> 	/* reset doesn't touch the display */
>-	if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
>+	if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
> 		return;
> 
> 	state = fetch_and_zero(&dev_priv->modeset_restore_state);
>@@ -4339,7 +4363,7 @@
> 	drm_modeset_acquire_fini(ctx);
> 	mutex_unlock(&dev->mode_config.mutex);
> 
>-	clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);
>+	clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
> }
> 
> static void icl_set_pipe_chicken(struct intel_crtc *crtc)
>@@ -5796,7 +5820,7 @@
> 	if (!old_crtc_state->ips_enabled)
> 		return false;
> 
>-	if (needs_modeset(&new_crtc_state->base))
>+	if (needs_modeset(new_crtc_state))
> 		return true;
> 
> 	/*
>@@ -5823,7 +5847,7 @@
> 	if (!new_crtc_state->ips_enabled)
> 		return false;
> 
>-	if (needs_modeset(&new_crtc_state->base))
>+	if (needs_modeset(new_crtc_state))
> 		return true;
> 
> 	/*
>@@ -5877,13 +5901,13 @@
> 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> 	struct drm_device *dev = crtc->base.dev;
> 	struct drm_i915_private *dev_priv = to_i915(dev);
>-	struct drm_atomic_state *old_state = old_crtc_state->base.state;
>+	struct drm_atomic_state *state = old_crtc_state->base.state;
> 	struct intel_crtc_state *pipe_config =
>-		intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),
>+		intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
> 						crtc);
> 	struct drm_plane *primary = crtc->base.primary;
> 	struct drm_plane_state *old_primary_state =
>-		drm_atomic_get_old_plane_state(old_state, primary);
>+		drm_atomic_get_old_plane_state(state, primary);
> 
> 	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
> 
>@@ -5895,12 +5919,12 @@
> 
> 	if (old_primary_state) {
> 		struct drm_plane_state *new_primary_state =
>-			drm_atomic_get_new_plane_state(old_state, primary);
>+			drm_atomic_get_new_plane_state(state, primary);
> 
> 		intel_fbc_post_update(crtc);
> 
> 		if (new_primary_state->visible &&
>-		    (needs_modeset(&pipe_config->base) ||
>+		    (needs_modeset(pipe_config) ||
> 		     !old_primary_state->visible))
> 			intel_post_enable_primary(&crtc->base, pipe_config);
> 	}
>@@ -5920,20 +5944,20 @@
> 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
> 	struct drm_device *dev = crtc->base.dev;
> 	struct drm_i915_private *dev_priv = to_i915(dev);
>-	struct drm_atomic_state *old_state = old_crtc_state->base.state;
>+	struct drm_atomic_state *state = old_crtc_state->base.state;
> 	struct drm_plane *primary = crtc->base.primary;
> 	struct drm_plane_state *old_primary_state =
>-		drm_atomic_get_old_plane_state(old_state, primary);
>-	bool modeset = needs_modeset(&pipe_config->base);
>-	struct intel_atomic_state *old_intel_state =
>-		to_intel_atomic_state(old_state);
>+		drm_atomic_get_old_plane_state(state, primary);
>+	bool modeset = needs_modeset(pipe_config);
>+	struct intel_atomic_state *intel_state =
>+		to_intel_atomic_state(state);
> 
> 	if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
> 		hsw_disable_ips(old_crtc_state);
> 
> 	if (old_primary_state) {
> 		struct intel_plane_state *new_primary_state =
>-			intel_atomic_get_new_plane_state(old_intel_state,
>+			intel_atomic_get_new_plane_state(intel_state,
> 							 to_intel_plane(primary));
> 
> 		intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
>@@ -5984,7 +6008,7 @@
> 	 * If we're doing a modeset, we're done.  No need to do any pre-vblank
> 	 * watermark programming here.
> 	 */
>-	if (needs_modeset(&pipe_config->base))
>+	if (needs_modeset(pipe_config))
> 		return;
> 
> 	/*
>@@ -6002,7 +6026,7 @@
> 	 * us to.
> 	 */
> 	if (dev_priv->display.initial_watermarks != NULL)
>-		dev_priv->display.initial_watermarks(old_intel_state,
>+		dev_priv->display.initial_watermarks(intel_state,
> 						     pipe_config);
> 	else if (pipe_config->update_wm_pre)
> 		intel_update_watermarks(crtc);
>@@ -6036,19 +6060,111 @@
> 	intel_frontbuffer_flip(dev_priv, fb_bits);
> }
> 
>-static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
>+/*
>+ * intel_connector_primary_encoder - get the primary encoder for a connector
>+ * @connector: connector for which to return the encoder
>+ *
>+ * Returns the primary encoder for a connector. There is a 1:1 mapping from
>+ * all connectors to their encoder, except for DP-MST connectors which have
>+ * both a virtual and a primary encoder. These DP-MST primary encoders can be
>+ * pointed to by as many DP-MST connectors as there are pipes.
>+ */
>+static struct intel_encoder *
>+intel_connector_primary_encoder(struct intel_connector *connector)
>+{
>+	struct intel_encoder *encoder;
>+
>+	if (connector->mst_port)
>+		return &dp_to_dig_port(connector->mst_port)->base;
>+
>+	encoder = intel_attached_encoder(&connector->base);
>+	WARN_ON(!encoder);
>+
>+	return encoder;
>+}
>+
>+static bool
>+intel_connector_needs_modeset(struct intel_atomic_state *state,
>+			      const struct drm_connector_state *old_conn_state,
>+			      const struct drm_connector_state *new_conn_state)
>+{
>+	struct intel_crtc *old_crtc = old_conn_state->crtc ?
>+				      to_intel_crtc(old_conn_state->crtc) : NULL;
>+	struct intel_crtc *new_crtc = new_conn_state->crtc ?
>+				      to_intel_crtc(new_conn_state->crtc) : NULL;
>+
>+	return new_crtc != old_crtc ||
>+	       (new_crtc &&
>+		needs_modeset(intel_atomic_get_new_crtc_state(state, new_crtc)));
>+}
>+
>+static void intel_encoders_update_prepare(struct intel_atomic_state *state)
>+{
>+	struct drm_connector_state *old_conn_state;
>+	struct drm_connector_state *new_conn_state;
>+	struct drm_connector *conn;
>+	int i;
>+
>+	for_each_oldnew_connector_in_state(&state->base, conn,
>+					   old_conn_state, new_conn_state, i) {
>+		struct intel_encoder *encoder;
>+		struct intel_crtc *crtc;
>+
>+		if (!intel_connector_needs_modeset(state,
>+						   old_conn_state,
>+						   new_conn_state))
>+			continue;
>+
>+		encoder = intel_connector_primary_encoder(to_intel_connector(conn));
>+		if (!encoder->update_prepare)
>+			continue;
>+
>+		crtc = new_conn_state->crtc ?
>+			to_intel_crtc(new_conn_state->crtc) : NULL;
>+		encoder->update_prepare(state, encoder, crtc);
>+	}
>+}
>+
>+static void intel_encoders_update_complete(struct intel_atomic_state *state)
>+{
>+	struct drm_connector_state *old_conn_state;
>+	struct drm_connector_state *new_conn_state;
>+	struct drm_connector *conn;
>+	int i;
>+
>+	for_each_oldnew_connector_in_state(&state->base, conn,
>+					   old_conn_state, new_conn_state, i) {
>+		struct intel_encoder *encoder;
>+		struct intel_crtc *crtc;
>+
>+		if (!intel_connector_needs_modeset(state,
>+						   old_conn_state,
>+						   new_conn_state))
>+			continue;
>+
>+		encoder = intel_connector_primary_encoder(to_intel_connector(conn));
>+		if (!encoder->update_complete)
>+			continue;
>+
>+		crtc = new_conn_state->crtc ?
>+			to_intel_crtc(new_conn_state->crtc) : NULL;
>+		encoder->update_complete(state, encoder, crtc);
>+	}
>+}
>+
>+static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
> 					  struct intel_crtc_state *crtc_state,
>-					  struct drm_atomic_state *old_state)
>+					  struct intel_atomic_state *state)
> {
> 	struct drm_connector_state *conn_state;
> 	struct drm_connector *conn;
> 	int i;
> 
>-	for_each_new_connector_in_state(old_state, conn, conn_state, i) {
>+	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
> 		struct intel_encoder *encoder =
> 			to_intel_encoder(conn_state->best_encoder);
> 
>-		if (conn_state->crtc != crtc)
>+		if (conn_state->crtc != &crtc->base)
> 			continue;
> 
> 		if (encoder->pre_pll_enable)
>@@ -6056,19 +6172,19 @@
> 	}
> }
> 
>-static void intel_encoders_pre_enable(struct drm_crtc *crtc,
>+static void intel_encoders_pre_enable(struct intel_crtc *crtc,
> 				      struct intel_crtc_state *crtc_state,
>-				      struct drm_atomic_state *old_state)
>+				      struct intel_atomic_state *state)
> {
> 	struct drm_connector_state *conn_state;
> 	struct drm_connector *conn;
> 	int i;
> 
>-	for_each_new_connector_in_state(old_state, conn, conn_state, i) {
>+	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
> 		struct intel_encoder *encoder =
> 			to_intel_encoder(conn_state->best_encoder);
> 
>-		if (conn_state->crtc != crtc)
>+		if (conn_state->crtc != &crtc->base)
> 			continue;
> 
> 		if (encoder->pre_enable)
>@@ -6076,19 +6192,19 @@
> 	}
> }
> 
>-static void intel_encoders_enable(struct drm_crtc *crtc,
>+static void intel_encoders_enable(struct intel_crtc *crtc,
> 				  struct intel_crtc_state *crtc_state,
>-				  struct drm_atomic_state *old_state)
>+				  struct intel_atomic_state *state)
> {
> 	struct drm_connector_state *conn_state;
> 	struct drm_connector *conn;
> 	int i;
> 
>-	for_each_new_connector_in_state(old_state, conn, conn_state, i) {
>+	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
> 		struct intel_encoder *encoder =
> 			to_intel_encoder(conn_state->best_encoder);
> 
>-		if (conn_state->crtc != crtc)
>+		if (conn_state->crtc != &crtc->base)
> 			continue;
> 
> 		if (encoder->enable)
>@@ -6097,19 +6213,19 @@
> 	}
> }
> 
>-static void intel_encoders_disable(struct drm_crtc *crtc,
>+static void intel_encoders_disable(struct intel_crtc *crtc,
> 				   struct intel_crtc_state *old_crtc_state,
>-				   struct drm_atomic_state *old_state)
>+				   struct intel_atomic_state *state)
> {
> 	struct drm_connector_state *old_conn_state;
> 	struct drm_connector *conn;
> 	int i;
> 
>-	for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
>+	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
> 		struct intel_encoder *encoder =
> 			to_intel_encoder(old_conn_state->best_encoder);
> 
>-		if (old_conn_state->crtc != crtc)
>+		if (old_conn_state->crtc != &crtc->base)
> 			continue;
> 
> 		intel_opregion_notify_encoder(encoder, false);
>@@ -6118,19 +6234,19 @@
> 	}
> }
> 
>-static void intel_encoders_post_disable(struct drm_crtc *crtc,
>+static void intel_encoders_post_disable(struct intel_crtc *crtc,
> 					struct intel_crtc_state *old_crtc_state,
>-					struct drm_atomic_state *old_state)
>+					struct intel_atomic_state *state)
> {
> 	struct drm_connector_state *old_conn_state;
> 	struct drm_connector *conn;
> 	int i;
> 
>-	for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
>+	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
> 		struct intel_encoder *encoder =
> 			to_intel_encoder(old_conn_state->best_encoder);
> 
>-		if (old_conn_state->crtc != crtc)
>+		if (old_conn_state->crtc != &crtc->base)
> 			continue;
> 
> 		if (encoder->post_disable)
>@@ -6138,19 +6254,19 @@
> 	}
> }
> 
>-static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
>+static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
> 					    struct intel_crtc_state *old_crtc_state,
>-					    struct drm_atomic_state *old_state)
>+					    struct intel_atomic_state *state)
> {
> 	struct drm_connector_state *old_conn_state;
> 	struct drm_connector *conn;
> 	int i;
> 
>-	for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
>+	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
> 		struct intel_encoder *encoder =
> 			to_intel_encoder(old_conn_state->best_encoder);
> 
>-		if (old_conn_state->crtc != crtc)
>+		if (old_conn_state->crtc != &crtc->base)
> 			continue;
> 
> 		if (encoder->post_pll_disable)
>@@ -6158,19 +6274,19 @@
> 	}
> }
> 
>-static void intel_encoders_update_pipe(struct drm_crtc *crtc,
>+static void intel_encoders_update_pipe(struct intel_crtc *crtc,
> 				       struct intel_crtc_state *crtc_state,
>-				       struct drm_atomic_state *old_state)
>+				       struct intel_atomic_state *state)
> {
> 	struct drm_connector_state *conn_state;
> 	struct drm_connector *conn;
> 	int i;
> 
>-	for_each_new_connector_in_state(old_state, conn, conn_state, i) {
>+	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
> 		struct intel_encoder *encoder =
> 			to_intel_encoder(conn_state->best_encoder);
> 
>-		if (conn_state->crtc != crtc)
>+		if (conn_state->crtc != &crtc->base)
> 			continue;
> 
> 		if (encoder->update_pipe)
>@@ -6187,15 +6303,13 @@
> }
> 
> static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>-				 struct drm_atomic_state *old_state)
>+				 struct intel_atomic_state *state)
> {
> 	struct drm_crtc *crtc = pipe_config->base.crtc;
> 	struct drm_device *dev = crtc->dev;
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> 	int pipe = intel_crtc->pipe;
>-	struct intel_atomic_state *old_intel_state =
>-		to_intel_atomic_state(old_state);
> 
> 	if (WARN_ON(intel_crtc->active))
> 		return;
>@@ -6231,7 +6345,7 @@
> 
> 	intel_crtc->active = true;
> 
>-	intel_encoders_pre_enable(crtc, pipe_config, old_state);
>+	intel_encoders_pre_enable(intel_crtc, pipe_config, state);
> 
> 	if (pipe_config->has_pch_encoder) {
> 		/* Note: FDI PLL enabling _must_ be done before we enable the
>@@ -6255,16 +6369,16 @@
> 	intel_disable_primary_plane(pipe_config);
> 
> 	if (dev_priv->display.initial_watermarks != NULL)
>-		dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
>+		dev_priv->display.initial_watermarks(state, pipe_config);
> 	intel_enable_pipe(pipe_config);
> 
> 	if (pipe_config->has_pch_encoder)
>-		ironlake_pch_enable(old_intel_state, pipe_config);
>+		ironlake_pch_enable(state, pipe_config);
> 
> 	assert_vblank_disabled(crtc);
> 	intel_crtc_vblank_on(pipe_config);
> 
>-	intel_encoders_enable(crtc, pipe_config, old_state);
>+	intel_encoders_enable(intel_crtc, pipe_config, state);
> 
> 	if (HAS_PCH_CPT(dev_priv))
> 		cpt_verify_modeset(dev, intel_crtc->pipe);
>@@ -6310,33 +6424,37 @@
> 	u32 val;
> 
> 	val = MBUS_DBOX_A_CREDIT(2);
>-	val |= MBUS_DBOX_BW_CREDIT(1);
>-	val |= MBUS_DBOX_B_CREDIT(8);
>+
>+	if (INTEL_GEN(dev_priv) >= 12) {
>+		val |= MBUS_DBOX_BW_CREDIT(2);
>+		val |= MBUS_DBOX_B_CREDIT(12);
>+	} else {
>+		val |= MBUS_DBOX_BW_CREDIT(1);
>+		val |= MBUS_DBOX_B_CREDIT(8);
>+	}
> 
> 	I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> }
> 
> static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>-				struct drm_atomic_state *old_state)
>+				struct intel_atomic_state *state)
> {
> 	struct drm_crtc *crtc = pipe_config->base.crtc;
> 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> 	int pipe = intel_crtc->pipe, hsw_workaround_pipe;
> 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
>-	struct intel_atomic_state *old_intel_state =
>-		to_intel_atomic_state(old_state);
> 	bool psl_clkgate_wa;
> 
> 	if (WARN_ON(intel_crtc->active))
> 		return;
> 
>-	intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
>+	intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
> 
> 	if (pipe_config->shared_dpll)
> 		intel_enable_shared_dpll(pipe_config);
> 
>-	intel_encoders_pre_enable(crtc, pipe_config, old_state);
>+	intel_encoders_pre_enable(intel_crtc, pipe_config, state);
> 
> 	if (intel_crtc_has_dp_encoder(pipe_config))
> 		intel_dp_set_m_n(pipe_config, M1_N1);
>@@ -6394,7 +6512,7 @@
> 		intel_ddi_enable_transcoder_func(pipe_config);
> 
> 	if (dev_priv->display.initial_watermarks != NULL)
>-		dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
>+		dev_priv->display.initial_watermarks(state, pipe_config);
> 
> 	if (INTEL_GEN(dev_priv) >= 11)
> 		icl_pipe_mbus_enable(intel_crtc);
>@@ -6404,7 +6522,7 @@
> 		intel_enable_pipe(pipe_config);
> 
> 	if (pipe_config->has_pch_encoder)
>-		lpt_pch_enable(old_intel_state, pipe_config);
>+		lpt_pch_enable(state, pipe_config);
> 
> 	if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
> 		intel_ddi_set_vc_payload_alloc(pipe_config, true);
>@@ -6412,7 +6530,7 @@
> 	assert_vblank_disabled(crtc);
> 	intel_crtc_vblank_on(pipe_config);
> 
>-	intel_encoders_enable(crtc, pipe_config, old_state);
>+	intel_encoders_enable(intel_crtc, pipe_config, state);
> 
> 	if (psl_clkgate_wa) {
> 		intel_wait_for_vblank(dev_priv, pipe);
>@@ -6444,7 +6562,7 @@
> }
> 
> static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
>-				  struct drm_atomic_state *old_state)
>+				  struct intel_atomic_state *state)
> {
> 	struct drm_crtc *crtc = old_crtc_state->base.crtc;
> 	struct drm_device *dev = crtc->dev;
>@@ -6460,7 +6578,7 @@
> 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> 	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
> 
>-	intel_encoders_disable(crtc, old_crtc_state, old_state);
>+	intel_encoders_disable(intel_crtc, old_crtc_state, state);
> 
> 	drm_crtc_vblank_off(crtc);
> 	assert_vblank_disabled(crtc);
>@@ -6472,7 +6590,7 @@
> 	if (old_crtc_state->has_pch_encoder)
> 		ironlake_fdi_disable(crtc);
> 
>-	intel_encoders_post_disable(crtc, old_crtc_state, old_state);
>+	intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
> 
> 	if (old_crtc_state->has_pch_encoder) {
> 		ironlake_disable_pch_transcoder(dev_priv, pipe);
>@@ -6503,14 +6621,14 @@
> }
> 
> static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
>-				 struct drm_atomic_state *old_state)
>+				 struct intel_atomic_state *state)
> {
> 	struct drm_crtc *crtc = old_crtc_state->base.crtc;
> 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> 
>-	intel_encoders_disable(crtc, old_crtc_state, old_state);
>+	intel_encoders_disable(intel_crtc, old_crtc_state, state);
> 
> 	drm_crtc_vblank_off(crtc);
> 	assert_vblank_disabled(crtc);
>@@ -6532,9 +6650,9 @@
> 	else
> 		ironlake_pfit_disable(old_crtc_state);
> 
>-	intel_encoders_post_disable(crtc, old_crtc_state, old_state);
>+	intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
> 
>-	intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
>+	intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
> }
> 
> static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
>@@ -6560,33 +6678,47 @@
> 	I915_WRITE(BCLRPAT(crtc->pipe), 0);
> }
> 
>-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
>+bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
> {
>-	if (port == PORT_NONE)
>+	if (phy == PHY_NONE)
> 		return false;
> 
>-	if (IS_ELKHARTLAKE(dev_priv))
>-		return port <= PORT_C;
>+	if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
>+		return phy <= PHY_C;
> 
> 	if (INTEL_GEN(dev_priv) >= 11)
>-		return port <= PORT_B;
>+		return phy <= PHY_B;
> 
> 	return false;
> }
> 
>-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
>+bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> {
>+	if (INTEL_GEN(dev_priv) >= 12)
>+		return phy >= PHY_D && phy <= PHY_I;
>+
> 	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
>-		return port >= PORT_C && port <= PORT_F;
>+		return phy >= PHY_C && phy <= PHY_F;
> 
> 	return false;
> }
> 
>+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
>+{
>+	if (IS_ELKHARTLAKE(i915) && port == PORT_D)
>+		return PHY_A;
>+
>+	return (enum phy)port;
>+}
>+
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
> {
>-	if (!intel_port_is_tc(dev_priv, port))
>+	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
> 		return PORT_TC_NONE;
> 
>+	if (INTEL_GEN(dev_priv) >= 12)
>+		return port - PORT_D;
>+
> 	return port - PORT_C;
> }
> 
>@@ -6614,6 +6746,26 @@
> enum intel_display_power_domain
> intel_aux_power_domain(struct intel_digital_port *dig_port)
> {
>+	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>+	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
>+
>+	if (intel_phy_is_tc(dev_priv, phy) &&
>+	    dig_port->tc_mode == TC_PORT_TBT_ALT) {
>+		switch (dig_port->aux_ch) {
>+		case AUX_CH_C:
>+			return POWER_DOMAIN_AUX_TBT1;
>+		case AUX_CH_D:
>+			return POWER_DOMAIN_AUX_TBT2;
>+		case AUX_CH_E:
>+			return POWER_DOMAIN_AUX_TBT3;
>+		case AUX_CH_F:
>+			return POWER_DOMAIN_AUX_TBT4;
>+		default:
>+			MISSING_CASE(dig_port->aux_ch);
>+			return POWER_DOMAIN_AUX_TBT1;
>+		}
>+	}
>+
> 	switch (dig_port->aux_ch) {
> 	case AUX_CH_A:
> 		return POWER_DOMAIN_AUX_A;
>@@ -6633,14 +6785,12 @@
> 	}
> }
> 
>-static u64 get_crtc_power_domains(struct drm_crtc *crtc,
>-				  struct intel_crtc_state *crtc_state)
>+static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> {
>-	struct drm_device *dev = crtc->dev;
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 	struct drm_encoder *encoder;
>-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>-	enum pipe pipe = intel_crtc->pipe;
>+	enum pipe pipe = crtc->pipe;
> 	u64 mask;
> 	enum transcoder transcoder = crtc_state->cpu_transcoder;
> 
>@@ -6653,7 +6803,8 @@
> 	    crtc_state->pch_pfit.force_thru)
> 		mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
> 
>-	drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
>+	drm_for_each_encoder_mask(encoder, &dev_priv->drm,
>+				  crtc_state->base.encoder_mask) {
> 		struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
> 
> 		mask |= BIT_ULL(intel_encoder->power_domain);
>@@ -6669,17 +6820,16 @@
> }
> 
> static u64
>-modeset_get_crtc_power_domains(struct drm_crtc *crtc,
>-			       struct intel_crtc_state *crtc_state)
>+modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
> {
>-	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 	enum intel_display_power_domain domain;
> 	u64 domains, new_domains, old_domains;
> 
>-	old_domains = intel_crtc->enabled_power_domains;
>-	intel_crtc->enabled_power_domains = new_domains =
>-		get_crtc_power_domains(crtc, crtc_state);
>+	old_domains = crtc->enabled_power_domains;
>+	crtc->enabled_power_domains = new_domains =
>+		get_crtc_power_domains(crtc_state);
> 
> 	domains = new_domains & ~old_domains;
> 
>@@ -6699,10 +6849,8 @@
> }
> 
> static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>-				   struct drm_atomic_state *old_state)
>+				   struct intel_atomic_state *state)
> {
>-	struct intel_atomic_state *old_intel_state =
>-		to_intel_atomic_state(old_state);
> 	struct drm_crtc *crtc = pipe_config->base.crtc;
> 	struct drm_device *dev = crtc->dev;
> 	struct drm_i915_private *dev_priv = to_i915(dev);
>@@ -6729,7 +6877,7 @@
> 
> 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> 
>-	intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
>+	intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
> 
> 	if (IS_CHERRYVIEW(dev_priv)) {
> 		chv_prepare_pll(intel_crtc, pipe_config);
>@@ -6739,7 +6887,7 @@
> 		vlv_enable_pll(intel_crtc, pipe_config);
> 	}
> 
>-	intel_encoders_pre_enable(crtc, pipe_config, old_state);
>+	intel_encoders_pre_enable(intel_crtc, pipe_config, state);
> 
> 	i9xx_pfit_enable(pipe_config);
> 
>@@ -6748,14 +6896,13 @@
> 	/* update DSPCNTR to configure gamma for pipe bottom color */
> 	intel_disable_primary_plane(pipe_config);
> 
>-	dev_priv->display.initial_watermarks(old_intel_state,
>-					     pipe_config);
>+	dev_priv->display.initial_watermarks(state, pipe_config);
> 	intel_enable_pipe(pipe_config);
> 
> 	assert_vblank_disabled(crtc);
> 	intel_crtc_vblank_on(pipe_config);
> 
>-	intel_encoders_enable(crtc, pipe_config, old_state);
>+	intel_encoders_enable(intel_crtc, pipe_config, state);
> }
> 
> static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
>@@ -6768,10 +6915,8 @@
> }
> 
> static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>-			     struct drm_atomic_state *old_state)
>+			     struct intel_atomic_state *state)
> {
>-	struct intel_atomic_state *old_intel_state =
>-		to_intel_atomic_state(old_state);
> 	struct drm_crtc *crtc = pipe_config->base.crtc;
> 	struct drm_device *dev = crtc->dev;
> 	struct drm_i915_private *dev_priv = to_i915(dev);
>@@ -6796,7 +6941,7 @@
> 	if (!IS_GEN(dev_priv, 2))
> 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> 
>-	intel_encoders_pre_enable(crtc, pipe_config, old_state);
>+	intel_encoders_pre_enable(intel_crtc, pipe_config, state);
> 
> 	i9xx_enable_pll(intel_crtc, pipe_config);
> 
>@@ -6808,7 +6953,7 @@
> 	intel_disable_primary_plane(pipe_config);
> 
> 	if (dev_priv->display.initial_watermarks != NULL)
>-		dev_priv->display.initial_watermarks(old_intel_state,
>+		dev_priv->display.initial_watermarks(state,
> 						     pipe_config);
> 	else
> 		intel_update_watermarks(intel_crtc);
>@@ -6817,7 +6962,7 @@
> 	assert_vblank_disabled(crtc);
> 	intel_crtc_vblank_on(pipe_config);
> 
>-	intel_encoders_enable(crtc, pipe_config, old_state);
>+	intel_encoders_enable(intel_crtc, pipe_config, state);
> }
> 
> static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
>@@ -6836,7 +6981,7 @@
> }
> 
> static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
>-			      struct drm_atomic_state *old_state)
>+			      struct intel_atomic_state *state)
> {
> 	struct drm_crtc *crtc = old_crtc_state->base.crtc;
> 	struct drm_device *dev = crtc->dev;
>@@ -6851,7 +6996,7 @@
> 	if (IS_GEN(dev_priv, 2))
> 		intel_wait_for_vblank(dev_priv, pipe);
> 
>-	intel_encoders_disable(crtc, old_crtc_state, old_state);
>+	intel_encoders_disable(intel_crtc, old_crtc_state, state);
> 
> 	drm_crtc_vblank_off(crtc);
> 	assert_vblank_disabled(crtc);
>@@ -6860,7 +7005,7 @@
> 
> 	i9xx_pfit_disable(old_crtc_state);
> 
>-	intel_encoders_post_disable(crtc, old_crtc_state, old_state);
>+	intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
> 
> 	if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
> 		if (IS_CHERRYVIEW(dev_priv))
>@@ -6871,7 +7016,7 @@
> 			i9xx_disable_pll(old_crtc_state);
> 	}
> 
>-	intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
>+	intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
> 
> 	if (!IS_GEN(dev_priv, 2))
> 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>@@ -6925,7 +7070,7 @@
> 
> 	WARN_ON(IS_ERR(crtc_state) || ret);
> 
>-	dev_priv->display.crtc_disable(crtc_state, state);
>+	dev_priv->display.crtc_disable(crtc_state, to_intel_atomic_state(state));
> 
> 	drm_atomic_state_put(state);
> 
>@@ -6988,7 +7133,7 @@
> 
> /* Cross check the actual hw state with our own modeset state tracking (and it's
>  * internal consistency). */
>-static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,
>+static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
> 					 struct drm_connector_state *conn_state)
> {
> 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
>@@ -7006,7 +7151,7 @@
> 		if (!crtc_state)
> 			return;
> 
>-		I915_STATE_WARN(!crtc_state->active,
>+		I915_STATE_WARN(!crtc_state->base.active,
> 		      "connector is active, but attached crtc isn't\n");
> 
> 		if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
>@@ -7018,7 +7163,7 @@
> 		I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
> 			"attached encoder crtc differs from connector crtc\n");
> 	} else {
>-		I915_STATE_WARN(crtc_state && crtc_state->active,
>+		I915_STATE_WARN(crtc_state && crtc_state->base.active,
> 			"attached crtc is active, but connector isn't\n");
> 		I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
> 			"best encoder set without crtc!\n");
>@@ -9484,6 +9629,8 @@
> 				       struct intel_crtc_state *crtc_state)
> {
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>+	struct intel_atomic_state *state =
>+		to_intel_atomic_state(crtc_state->base.state);
> 	const struct intel_limit *limit;
> 	int refclk = 120000;
> 
>@@ -9525,7 +9672,7 @@
> 
> 	ironlake_compute_dpll(crtc, crtc_state, NULL);
> 
>-	if (!intel_get_shared_dpll(crtc_state, NULL)) {
>+	if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
> 		DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
> 			      pipe_name(crtc->pipe));
> 		return -EINVAL;
>@@ -9906,7 +10053,7 @@
> 		struct intel_encoder *encoder =
> 			intel_get_crtc_new_encoder(state, crtc_state);
> 
>-		if (!intel_get_shared_dpll(crtc_state, encoder)) {
>+		if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
> 			DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
> 				      pipe_name(crtc->pipe));
> 			return -EINVAL;
>@@ -9936,22 +10083,37 @@
> 				enum port port,
> 				struct intel_crtc_state *pipe_config)
> {
>+	enum phy phy = intel_port_to_phy(dev_priv, port);
>+	enum icl_port_dpll_id port_dpll_id;
> 	enum intel_dpll_id id;
> 	u32 temp;
> 
>-	/* TODO: TBT pll not implemented. */
>-	if (intel_port_is_combophy(dev_priv, port)) {
>-		temp = I915_READ(DPCLKA_CFGCR0_ICL) &
>-		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
>-		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
>-	} else if (intel_port_is_tc(dev_priv, port)) {
>-		id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
>+	if (intel_phy_is_combo(dev_priv, phy)) {
>+		temp = I915_READ(ICL_DPCLKA_CFGCR0) &
>+			ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
>+		id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
>+		port_dpll_id = ICL_PORT_DPLL_DEFAULT;
>+	} else if (intel_phy_is_tc(dev_priv, phy)) {
>+		u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
>+
>+		if (clk_sel == DDI_CLK_SEL_MG) {
>+			id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
>+								    port));
>+			port_dpll_id = ICL_PORT_DPLL_MG_PHY;
>+		} else {
>+			WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
>+			id = DPLL_ID_ICL_TBTPLL;
>+			port_dpll_id = ICL_PORT_DPLL_DEFAULT;
>+		}
> 	} else {
> 		WARN(1, "Invalid port %x\n", port);
> 		return;
> 	}
> 
>-	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
>+	pipe_config->icl_port_dplls[port_dpll_id].pll =
>+		intel_get_shared_dpll_by_id(dev_priv, id);
>+
>+	icl_set_active_port_dpll(pipe_config, port_dpll_id);
> }
> 
> static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
>@@ -10191,7 +10353,11 @@
> 
> 	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
> 
>-	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
>+	if (INTEL_GEN(dev_priv) >= 12)
>+		port = (tmp & TGL_TRANS_DDI_PORT_MASK) >>
>+			TGL_TRANS_DDI_PORT_SHIFT;
>+	else
>+		port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
> 
> 	if (INTEL_GEN(dev_priv) >= 11)
> 		icelake_get_ddi_pll(dev_priv, port, pipe_config);
>@@ -11297,7 +11463,7 @@
>  *
>  * Returns true or false.
>  */
>-static bool intel_wm_need_update(struct intel_plane_state *cur,
>+static bool intel_wm_need_update(const struct intel_plane_state *cur,
> 				 struct intel_plane_state *new)
> {
> 	/* Update watermarks on tiling or size changes. */
>@@ -11329,33 +11495,28 @@
> }
> 
> int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
>-				    struct drm_crtc_state *crtc_state,
>+				    struct intel_crtc_state *crtc_state,
> 				    const struct intel_plane_state *old_plane_state,
>-				    struct drm_plane_state *plane_state)
>+				    struct intel_plane_state *plane_state)
> {
>-	struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
>-	struct drm_crtc *crtc = crtc_state->crtc;
>-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>-	struct intel_plane *plane = to_intel_plane(plane_state->plane);
>-	struct drm_device *dev = crtc->dev;
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 	bool mode_changed = needs_modeset(crtc_state);
> 	bool was_crtc_enabled = old_crtc_state->base.active;
>-	bool is_crtc_enabled = crtc_state->active;
>+	bool is_crtc_enabled = crtc_state->base.active;
> 	bool turn_off, turn_on, visible, was_visible;
>-	struct drm_framebuffer *fb = plane_state->fb;
>+	struct drm_framebuffer *fb = plane_state->base.fb;
> 	int ret;
> 
> 	if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
>-		ret = skl_update_scaler_plane(
>-			to_intel_crtc_state(crtc_state),
>-			to_intel_plane_state(plane_state));
>+		ret = skl_update_scaler_plane(crtc_state, plane_state);
> 		if (ret)
> 			return ret;
> 	}
> 
> 	was_visible = old_plane_state->base.visible;
>-	visible = plane_state->visible;
>+	visible = plane_state->base.visible;
> 
> 	if (!was_crtc_enabled && WARN_ON(was_visible))
> 		was_visible = false;
>@@ -11371,22 +11532,22 @@
> 	 * only combine the results from all planes in the current place?
> 	 */
> 	if (!is_crtc_enabled) {
>-		plane_state->visible = visible = false;
>-		to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
>-		to_intel_crtc_state(crtc_state)->data_rate[plane->id] = 0;
>+		plane_state->base.visible = visible = false;
>+		crtc_state->active_planes &= ~BIT(plane->id);
>+		crtc_state->data_rate[plane->id] = 0;
> 	}
> 
> 	if (!was_visible && !visible)
> 		return 0;
> 
> 	if (fb != old_plane_state->base.fb)
>-		pipe_config->fb_changed = true;
>+		crtc_state->fb_changed = true;
> 
> 	turn_off = was_visible && (!visible || mode_changed);
> 	turn_on = visible && (!was_visible || mode_changed);
> 
> 	DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
>-			 intel_crtc->base.base.id, intel_crtc->base.name,
>+			 crtc->base.base.id, crtc->base.name,
> 			 plane->base.base.id, plane->base.name,
> 			 fb ? fb->base.id : -1);
> 
>@@ -11397,29 +11558,28 @@
> 
> 	if (turn_on) {
> 		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
>-			pipe_config->update_wm_pre = true;
>+			crtc_state->update_wm_pre = true;
> 
> 		/* must disable cxsr around plane enable/disable */
> 		if (plane->id != PLANE_CURSOR)
>-			pipe_config->disable_cxsr = true;
>+			crtc_state->disable_cxsr = true;
> 	} else if (turn_off) {
> 		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
>-			pipe_config->update_wm_post = true;
>+			crtc_state->update_wm_post = true;
> 
> 		/* must disable cxsr around plane enable/disable */
> 		if (plane->id != PLANE_CURSOR)
>-			pipe_config->disable_cxsr = true;
>-	} else if (intel_wm_need_update(to_intel_plane_state(plane->base.state),
>-					to_intel_plane_state(plane_state))) {
>+			crtc_state->disable_cxsr = true;
>+	} else if (intel_wm_need_update(old_plane_state, plane_state)) {
> 		if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
> 			/* FIXME bollocks */
>-			pipe_config->update_wm_pre = true;
>-			pipe_config->update_wm_post = true;
>+			crtc_state->update_wm_pre = true;
>+			crtc_state->update_wm_post = true;
> 		}
> 	}
> 
> 	if (visible || was_visible)
>-		pipe_config->fb_bits |= plane->frontbuffer_bit;
>+		crtc_state->fb_bits |= plane->frontbuffer_bit;
> 
> 	/*
> 	 * ILK/SNB DVSACNTR/Sprite Enable
>@@ -11458,8 +11618,8 @@
> 	    (IS_GEN_RANGE(dev_priv, 5, 6) ||
> 	     IS_IVYBRIDGE(dev_priv)) &&
> 	    (turn_on || (!needs_scaling(old_plane_state) &&
>-			 needs_scaling(to_intel_plane_state(plane_state)))))
>-		pipe_config->disable_lp_wm = true;
>+			 needs_scaling(plane_state))))
>+		crtc_state->disable_lp_wm = true;
> 
> 	return 0;
> }
>@@ -11608,7 +11768,7 @@
> 	struct intel_crtc_state *pipe_config =
> 		to_intel_crtc_state(crtc_state);
> 	int ret;
>-	bool mode_changed = needs_modeset(crtc_state);
>+	bool mode_changed = needs_modeset(pipe_config);
> 
> 	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
> 	    mode_changed && !crtc_state->active)
>@@ -12090,6 +12250,8 @@
> 	saved_state->scaler_state = crtc_state->scaler_state;
> 	saved_state->shared_dpll = crtc_state->shared_dpll;
> 	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
>+	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
>+	       sizeof(saved_state->icl_port_dplls));
> 	saved_state->crc_enabled = crtc_state->crc_enabled;
> 	if (IS_G4X(dev_priv) ||
> 	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
>@@ -12706,10 +12868,10 @@
> 	}
> }
> 
>-static void verify_wm_state(struct drm_crtc *crtc,
>-			    struct drm_crtc_state *new_state)
>+static void verify_wm_state(struct intel_crtc *crtc,
>+			    struct intel_crtc_state *new_crtc_state)
> {
>-	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 	struct skl_hw_state {
> 		struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
> 		struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
>@@ -12719,21 +12881,20 @@
> 	struct skl_ddb_allocation *sw_ddb;
> 	struct skl_pipe_wm *sw_wm;
> 	struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
>-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>-	const enum pipe pipe = intel_crtc->pipe;
>+	const enum pipe pipe = crtc->pipe;
> 	int plane, level, max_level = ilk_wm_max_level(dev_priv);
> 
>-	if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
>+	if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->base.active)
> 		return;
> 
> 	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
> 	if (!hw)
> 		return;
> 
>-	skl_pipe_wm_get_hw_state(intel_crtc, &hw->wm);
>-	sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
>+	skl_pipe_wm_get_hw_state(crtc, &hw->wm);
>+	sw_wm = &new_crtc_state->wm.skl.optimal;
> 
>-	skl_pipe_ddb_get_hw_state(intel_crtc, hw->ddb_y, hw->ddb_uv);
>+	skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
> 
> 	skl_ddb_get_hw_state(dev_priv, &hw->ddb);
> 	sw_ddb = &dev_priv->wm.skl_hw.ddb;
>@@ -12781,7 +12942,7 @@
> 
> 		/* DDB */
> 		hw_ddb_entry = &hw->ddb_y[plane];
>-		sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[plane];
>+		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
> 
> 		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
> 			DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
>@@ -12833,7 +12994,7 @@
> 
> 		/* DDB */
> 		hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
>-		sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[PLANE_CURSOR];
>+		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
> 
> 		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
> 			DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
>@@ -12847,23 +13008,22 @@
> }
> 
> static void
>-verify_connector_state(struct drm_device *dev,
>-		       struct drm_atomic_state *state,
>-		       struct drm_crtc *crtc)
>+verify_connector_state(struct intel_atomic_state *state,
>+		       struct intel_crtc *crtc)
> {
> 	struct drm_connector *connector;
> 	struct drm_connector_state *new_conn_state;
> 	int i;
> 
>-	for_each_new_connector_in_state(state, connector, new_conn_state, i) {
>+	for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
> 		struct drm_encoder *encoder = connector->encoder;
>-		struct drm_crtc_state *crtc_state = NULL;
>+		struct intel_crtc_state *crtc_state = NULL;
> 
>-		if (new_conn_state->crtc != crtc)
>+		if (new_conn_state->crtc != &crtc->base)
> 			continue;
> 
> 		if (crtc)
>-			crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
>+			crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> 
> 		intel_connector_verify_state(crtc_state, new_conn_state);
> 
>@@ -12873,14 +13033,14 @@
> }
> 
> static void
>-verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
>+verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
> {
> 	struct intel_encoder *encoder;
> 	struct drm_connector *connector;
> 	struct drm_connector_state *old_conn_state, *new_conn_state;
> 	int i;
> 
>-	for_each_intel_encoder(dev, encoder) {
>+	for_each_intel_encoder(&dev_priv->drm, encoder) {
> 		bool enabled = false, found = false;
> 		enum pipe pipe;
> 
>@@ -12888,7 +13048,7 @@
> 			      encoder->base.base.id,
> 			      encoder->base.name);
> 
>-		for_each_oldnew_connector_in_state(state, connector, old_conn_state,
>+		for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
> 						   new_conn_state, i) {
> 			if (old_conn_state->best_encoder == &encoder->base)
> 				found = true;
>@@ -12922,50 +13082,49 @@
> }
> 
> static void
>-verify_crtc_state(struct drm_crtc *crtc,
>-		  struct drm_crtc_state *old_crtc_state,
>-		  struct drm_crtc_state *new_crtc_state)
>+verify_crtc_state(struct intel_crtc *crtc,
>+		  struct intel_crtc_state *old_crtc_state,
>+		  struct intel_crtc_state *new_crtc_state)
> {
>-	struct drm_device *dev = crtc->dev;
>+	struct drm_device *dev = crtc->base.dev;
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_encoder *encoder;
>-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>-	struct intel_crtc_state *pipe_config, *sw_config;
>-	struct drm_atomic_state *old_state;
>+	struct intel_crtc_state *pipe_config;
>+	struct drm_atomic_state *state;
> 	bool active;
> 
>-	old_state = old_crtc_state->state;
>-	__drm_atomic_helper_crtc_destroy_state(old_crtc_state);
>-	pipe_config = to_intel_crtc_state(old_crtc_state);
>+	state = old_crtc_state->base.state;
>+	__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->base);
>+	pipe_config = old_crtc_state;
> 	memset(pipe_config, 0, sizeof(*pipe_config));
>-	pipe_config->base.crtc = crtc;
>-	pipe_config->base.state = old_state;
>+	pipe_config->base.crtc = &crtc->base;
>+	pipe_config->base.state = state;
> 
>-	DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
>+	DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
> 
>-	active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
>+	active = dev_priv->display.get_pipe_config(crtc, pipe_config);
> 
> 	/* we keep both pipes enabled on 830 */
> 	if (IS_I830(dev_priv))
>-		active = new_crtc_state->active;
>+		active = new_crtc_state->base.active;
> 
>-	I915_STATE_WARN(new_crtc_state->active != active,
>+	I915_STATE_WARN(new_crtc_state->base.active != active,
> 	     "crtc active state doesn't match with hw state "
>-	     "(expected %i, found %i)\n", new_crtc_state->active, active);
>+	     "(expected %i, found %i)\n", new_crtc_state->base.active, active);
> 
>-	I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
>+	I915_STATE_WARN(crtc->active != new_crtc_state->base.active,
> 	     "transitional active state does not match atomic hw state "
>-	     "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
>+	     "(expected %i, found %i)\n", new_crtc_state->base.active, crtc->active);
> 
>-	for_each_encoder_on_crtc(dev, crtc, encoder) {
>+	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
> 		enum pipe pipe;
> 
> 		active = encoder->get_hw_state(encoder, &pipe);
>-		I915_STATE_WARN(active != new_crtc_state->active,
>+		I915_STATE_WARN(active != new_crtc_state->base.active,
> 			"[ENCODER:%i] active %i with crtc active %i\n",
>-			encoder->base.base.id, active, new_crtc_state->active);
>+			encoder->base.base.id, active, new_crtc_state->base.active);
> 
>-		I915_STATE_WARN(active && intel_crtc->pipe != pipe,
>+		I915_STATE_WARN(active && crtc->pipe != pipe,
> 				"Encoder connected to wrong pipe %c\n",
> 				pipe_name(pipe));
> 
>@@ -12975,16 +13134,16 @@
> 
> 	intel_crtc_compute_pixel_rate(pipe_config);
> 
>-	if (!new_crtc_state->active)
>+	if (!new_crtc_state->base.active)
> 		return;
> 
> 	intel_pipe_config_sanity_check(dev_priv, pipe_config);
> 
>-	sw_config = to_intel_crtc_state(new_crtc_state);
>-	if (!intel_pipe_config_compare(sw_config, pipe_config, false)) {
>+	if (!intel_pipe_config_compare(new_crtc_state,
>+				       pipe_config, false)) {
> 		I915_STATE_WARN(1, "pipe state doesn't match!\n");
> 		intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
>-		intel_dump_pipe_config(sw_config, NULL, "[sw state]");
>+		intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
> 	}
> }
> 
>@@ -13004,8 +13163,8 @@
> static void
> verify_single_dpll_state(struct drm_i915_private *dev_priv,
> 			 struct intel_shared_dpll *pll,
>-			 struct drm_crtc *crtc,
>-			 struct drm_crtc_state *new_state)
>+			 struct intel_crtc *crtc,
>+			 struct intel_crtc_state *new_crtc_state)
> {
> 	struct intel_dpll_hw_state dpll_hw_state;
> 	unsigned int crtc_mask;
>@@ -13035,16 +13194,16 @@
> 		return;
> 	}
> 
>-	crtc_mask = drm_crtc_mask(crtc);
>+	crtc_mask = drm_crtc_mask(&crtc->base);
> 
>-	if (new_state->active)
>+	if (new_crtc_state->base.active)
> 		I915_STATE_WARN(!(pll->active_mask & crtc_mask),
> 				"pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
>-				pipe_name(drm_crtc_index(crtc)), pll->active_mask);
>+				pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
> 	else
> 		I915_STATE_WARN(pll->active_mask & crtc_mask,
> 				"pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
>-				pipe_name(drm_crtc_index(crtc)), pll->active_mask);
>+				pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
> 
> 	I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
> 			"pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
>@@ -13057,51 +13216,47 @@
> }
> 
> static void
>-verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
>-			 struct drm_crtc_state *old_crtc_state,
>-			 struct drm_crtc_state *new_crtc_state)
>+verify_shared_dpll_state(struct intel_crtc *crtc,
>+			 struct intel_crtc_state *old_crtc_state,
>+			 struct intel_crtc_state *new_crtc_state)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>-	struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
>-	struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 
>-	if (new_state->shared_dpll)
>-		verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
>+	if (new_crtc_state->shared_dpll)
>+		verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
> 
>-	if (old_state->shared_dpll &&
>-	    old_state->shared_dpll != new_state->shared_dpll) {
>-		unsigned int crtc_mask = drm_crtc_mask(crtc);
>-		struct intel_shared_dpll *pll = old_state->shared_dpll;
>+	if (old_crtc_state->shared_dpll &&
>+	    old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
>+		unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
>+		struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
> 
> 		I915_STATE_WARN(pll->active_mask & crtc_mask,
> 				"pll active mismatch (didn't expect pipe %c in active mask)\n",
>-				pipe_name(drm_crtc_index(crtc)));
>+				pipe_name(drm_crtc_index(&crtc->base)));
> 		I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
> 				"pll enabled crtcs mismatch (found %x in enabled mask)\n",
>-				pipe_name(drm_crtc_index(crtc)));
>+				pipe_name(drm_crtc_index(&crtc->base)));
> 	}
> }
> 
> static void
>-intel_modeset_verify_crtc(struct drm_crtc *crtc,
>-			  struct drm_atomic_state *state,
>-			  struct drm_crtc_state *old_state,
>-			  struct drm_crtc_state *new_state)
>+intel_modeset_verify_crtc(struct intel_crtc *crtc,
>+			  struct intel_atomic_state *state,
>+			  struct intel_crtc_state *old_crtc_state,
>+			  struct intel_crtc_state *new_crtc_state)
> {
>-	if (!needs_modeset(new_state) &&
>-	    !to_intel_crtc_state(new_state)->update_pipe)
>+	if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
> 		return;
> 
>-	verify_wm_state(crtc, new_state);
>-	verify_connector_state(crtc->dev, state, crtc);
>-	verify_crtc_state(crtc, old_state, new_state);
>-	verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
>+	verify_wm_state(crtc, new_crtc_state);
>+	verify_connector_state(state, crtc);
>+	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
>+	verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
> }
> 
> static void
>-verify_disabled_dpll_state(struct drm_device *dev)
>+verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	int i;
> 
> 	for (i = 0; i < dev_priv->num_shared_dpll; i++)
>@@ -13109,12 +13264,12 @@
> }
> 
> static void
>-intel_modeset_verify_disabled(struct drm_device *dev,
>-			      struct drm_atomic_state *state)
>+intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
>+			      struct intel_atomic_state *state)
> {
>-	verify_encoder_state(dev, state);
>-	verify_connector_state(dev, state, NULL);
>-	verify_disabled_dpll_state(dev);
>+	verify_encoder_state(dev_priv, state);
>+	verify_connector_state(state, NULL);
>+	verify_disabled_dpll_state(dev_priv);
> }
> 
> static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
>@@ -13168,27 +13323,18 @@
> static void intel_modeset_clear_plls(struct intel_atomic_state *state)
> {
> 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>-	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
>+	struct intel_crtc_state *new_crtc_state;
> 	struct intel_crtc *crtc;
> 	int i;
> 
> 	if (!dev_priv->display.crtc_compute_clock)
> 		return;
> 
>-	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>-					    new_crtc_state, i) {
>-		struct intel_shared_dpll *old_dpll =
>-			old_crtc_state->shared_dpll;
>-
>-		if (!needs_modeset(&new_crtc_state->base))
>-			continue;
>-
>-		new_crtc_state->shared_dpll = NULL;
>-
>-		if (!old_dpll)
>+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>+		if (!needs_modeset(new_crtc_state))
> 			continue;
> 
>-		intel_release_shared_dpll(old_dpll, crtc, &state->base);
>+		intel_release_shared_dplls(state, crtc);
> 	}
> }
> 
>@@ -13210,7 +13356,7 @@
> 	/* look at all crtc's that are going to be enabled in during modeset */
> 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> 		if (!crtc_state->base.active ||
>-		    !needs_modeset(&crtc_state->base))
>+		    !needs_modeset(crtc_state))
> 			continue;
> 
> 		if (first_crtc_state) {
>@@ -13235,7 +13381,7 @@
> 		crtc_state->hsw_workaround_pipe = INVALID_PIPE;
> 
> 		if (!crtc_state->base.active ||
>-		    needs_modeset(&crtc_state->base))
>+		    needs_modeset(crtc_state))
> 			continue;
> 
> 		/* 2 or more enabled crtcs means no need for w/a */
>@@ -13253,15 +13399,16 @@
> 	return 0;
> }
> 
>-static int intel_lock_all_pipes(struct drm_atomic_state *state)
>+static int intel_lock_all_pipes(struct intel_atomic_state *state)
> {
>-	struct drm_crtc *crtc;
>+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>+	struct intel_crtc *crtc;
> 
> 	/* Add all pipes to the state */
>-	for_each_crtc(state->dev, crtc) {
>-		struct drm_crtc_state *crtc_state;
>+	for_each_intel_crtc(&dev_priv->drm, crtc) {
>+		struct intel_crtc_state *crtc_state;
> 
>-		crtc_state = drm_atomic_get_crtc_state(state, crtc);
>+		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
> 		if (IS_ERR(crtc_state))
> 			return PTR_ERR(crtc_state);
> 	}
>@@ -13269,32 +13416,35 @@
> 	return 0;
> }
> 
>-static int intel_modeset_all_pipes(struct drm_atomic_state *state)
>+static int intel_modeset_all_pipes(struct intel_atomic_state *state)
> {
>-	struct drm_crtc *crtc;
>+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>+	struct intel_crtc *crtc;
> 
> 	/*
> 	 * Add all pipes to the state, and force
> 	 * a modeset on all the active ones.
> 	 */
>-	for_each_crtc(state->dev, crtc) {
>-		struct drm_crtc_state *crtc_state;
>+	for_each_intel_crtc(&dev_priv->drm, crtc) {
>+		struct intel_crtc_state *crtc_state;
> 		int ret;
> 
>-		crtc_state = drm_atomic_get_crtc_state(state, crtc);
>+		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
> 		if (IS_ERR(crtc_state))
> 			return PTR_ERR(crtc_state);
> 
>-		if (!crtc_state->active || needs_modeset(crtc_state))
>+		if (!crtc_state->base.active || needs_modeset(crtc_state))
> 			continue;
> 
>-		crtc_state->mode_changed = true;
>+		crtc_state->base.mode_changed = true;
> 
>-		ret = drm_atomic_add_affected_connectors(state, crtc);
>+		ret = drm_atomic_add_affected_connectors(&state->base,
>+							 &crtc->base);
> 		if (ret)
> 			return ret;
> 
>-		ret = drm_atomic_add_affected_planes(state, crtc);
>+		ret = drm_atomic_add_affected_planes(&state->base,
>+						     &crtc->base);
> 		if (ret)
> 			return ret;
> 	}
>@@ -13356,18 +13506,18 @@
> 		 */
> 		if (intel_cdclk_changed(&dev_priv->cdclk.logical,
> 					&state->cdclk.logical)) {
>-			ret = intel_lock_all_pipes(&state->base);
>+			ret = intel_lock_all_pipes(state);
> 			if (ret < 0)
> 				return ret;
> 		}
> 
> 		if (is_power_of_2(state->active_crtcs)) {
>-			struct drm_crtc *crtc;
>-			struct drm_crtc_state *crtc_state;
>+			struct intel_crtc *crtc;
>+			struct intel_crtc_state *crtc_state;
> 
> 			pipe = ilog2(state->active_crtcs);
>-			crtc = &intel_get_crtc_for_pipe(dev_priv, pipe)->base;
>-			crtc_state = drm_atomic_get_new_crtc_state(&state->base, crtc);
>+			crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>+			crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> 			if (crtc_state && needs_modeset(crtc_state))
> 				pipe = INVALID_PIPE;
> 		} else {
>@@ -13379,14 +13529,14 @@
> 		    intel_cdclk_needs_cd2x_update(dev_priv,
> 						  &dev_priv->cdclk.actual,
> 						  &state->cdclk.actual)) {
>-			ret = intel_lock_all_pipes(&state->base);
>+			ret = intel_lock_all_pipes(state);
> 			if (ret < 0)
> 				return ret;
> 
> 			state->cdclk.pipe = pipe;
> 		} else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
> 						     &state->cdclk.actual)) {
>-			ret = intel_modeset_all_pipes(&state->base);
>+			ret = intel_modeset_all_pipes(state);
> 			if (ret < 0)
> 				return ret;
> 
>@@ -13478,7 +13628,7 @@
> 
> 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> 					    new_crtc_state, i) {
>-		if (!needs_modeset(&new_crtc_state->base))
>+		if (!needs_modeset(new_crtc_state))
> 			continue;
> 
> 		if (!new_crtc_state->base.enable) {
>@@ -13492,7 +13642,7 @@
> 
> 		intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
> 
>-		if (needs_modeset(&new_crtc_state->base))
>+		if (needs_modeset(new_crtc_state))
> 			any_ms = true;
> 	}
> 
>@@ -13527,12 +13677,12 @@
> 
> 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> 					    new_crtc_state, i) {
>-		if (!needs_modeset(&new_crtc_state->base) &&
>+		if (!needs_modeset(new_crtc_state) &&
> 		    !new_crtc_state->update_pipe)
> 			continue;
> 
> 		intel_dump_pipe_config(new_crtc_state, state,
>-				       needs_modeset(&new_crtc_state->base) ?
>+				       needs_modeset(new_crtc_state) ?
> 				       "[modeset]" : "[fastset]");
> 	}
> 
>@@ -13553,10 +13703,10 @@
> 	return ret;
> }
> 
>-static int intel_atomic_prepare_commit(struct drm_device *dev,
>-				       struct drm_atomic_state *state)
>+static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
> {
>-	return drm_atomic_helper_prepare_planes(dev, state);
>+	return drm_atomic_helper_prepare_planes(state->base.dev,
>+						&state->base);
> }
> 
> u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
>@@ -13567,60 +13717,57 @@
> 	if (!vblank->max_vblank_count)
> 		return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
> 
>-	return dev->driver->get_vblank_counter(dev, crtc->pipe);
>+	return crtc->base.funcs->get_vblank_counter(&crtc->base);
> }
> 
>-static void intel_update_crtc(struct drm_crtc *crtc,
>-			      struct drm_atomic_state *state,
>-			      struct drm_crtc_state *old_crtc_state,
>-			      struct drm_crtc_state *new_crtc_state)
>+static void intel_update_crtc(struct intel_crtc *crtc,
>+			      struct intel_atomic_state *state,
>+			      struct intel_crtc_state *old_crtc_state,
>+			      struct intel_crtc_state *new_crtc_state)
> {
>-	struct drm_device *dev = crtc->dev;
>+	struct drm_device *dev = state->base.dev;
> 	struct drm_i915_private *dev_priv = to_i915(dev);
>-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>-	struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
> 	bool modeset = needs_modeset(new_crtc_state);
> 	struct intel_plane_state *new_plane_state =
>-		intel_atomic_get_new_plane_state(to_intel_atomic_state(state),
>-						 to_intel_plane(crtc->primary));
>+		intel_atomic_get_new_plane_state(state,
>+						 to_intel_plane(crtc->base.primary));
> 
> 	if (modeset) {
>-		update_scanline_offset(pipe_config);
>-		dev_priv->display.crtc_enable(pipe_config, state);
>+		update_scanline_offset(new_crtc_state);
>+		dev_priv->display.crtc_enable(new_crtc_state, state);
> 
> 		/* vblanks work again, re-enable pipe CRC. */
>-		intel_crtc_enable_pipe_crc(intel_crtc);
>+		intel_crtc_enable_pipe_crc(crtc);
> 	} else {
>-		intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
>-				       pipe_config);
>+		intel_pre_plane_update(old_crtc_state, new_crtc_state);
> 
>-		if (pipe_config->update_pipe)
>-			intel_encoders_update_pipe(crtc, pipe_config, state);
>+		if (new_crtc_state->update_pipe)
>+			intel_encoders_update_pipe(crtc, new_crtc_state, state);
> 	}
> 
>-	if (pipe_config->update_pipe && !pipe_config->enable_fbc)
>-		intel_fbc_disable(intel_crtc);
>+	if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
>+		intel_fbc_disable(crtc);
> 	else if (new_plane_state)
>-		intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
>+		intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
> 
>-	intel_begin_crtc_commit(to_intel_atomic_state(state), intel_crtc);
>+	intel_begin_crtc_commit(state, crtc);
> 
> 	if (INTEL_GEN(dev_priv) >= 9)
>-		skl_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
>+		skl_update_planes_on_crtc(state, crtc);
> 	else
>-		i9xx_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);
>+		i9xx_update_planes_on_crtc(state, crtc);
> 
>-	intel_finish_crtc_commit(to_intel_atomic_state(state), intel_crtc);
>+	intel_finish_crtc_commit(state, crtc);
> }
> 
>-static void intel_update_crtcs(struct drm_atomic_state *state)
>+static void intel_update_crtcs(struct intel_atomic_state *state)
> {
>-	struct drm_crtc *crtc;
>-	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
>+	struct intel_crtc *crtc;
>+	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> 	int i;
> 
>-	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
>-		if (!new_crtc_state->active)
>+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
>+		if (!new_crtc_state->base.active)
> 			continue;
> 
> 		intel_update_crtc(crtc, state, old_crtc_state,
>@@ -13628,26 +13775,23 @@
> 	}
> }
> 
>-static void skl_update_crtcs(struct drm_atomic_state *state)
>+static void skl_update_crtcs(struct intel_atomic_state *state)
> {
>-	struct drm_i915_private *dev_priv = to_i915(state->dev);
>-	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>-	struct drm_crtc *crtc;
>-	struct intel_crtc *intel_crtc;
>-	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
>-	struct intel_crtc_state *cstate;
>+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>+	struct intel_crtc *crtc;
>+	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> 	unsigned int updated = 0;
> 	bool progress;
> 	enum pipe pipe;
> 	int i;
> 	u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
>-	u8 required_slices = intel_state->wm_results.ddb.enabled_slices;
>+	u8 required_slices = state->wm_results.ddb.enabled_slices;
> 	struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
> 
>-	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
>+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
> 		/* ignore allocations for crtc's that have been turned off. */
>-		if (new_crtc_state->active)
>-			entries[i] = to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
>+		if (new_crtc_state->base.active)
>+			entries[i] = old_crtc_state->wm.skl.ddb;
> 
> 	/* If 2nd DBuf slice required, enable it here */
> 	if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
>@@ -13662,24 +13806,22 @@
> 	do {
> 		progress = false;
> 
>-		for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
>+		for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> 			bool vbl_wait = false;
>-			unsigned int cmask = drm_crtc_mask(crtc);
>+			unsigned int cmask = drm_crtc_mask(&crtc->base);
> 
>-			intel_crtc = to_intel_crtc(crtc);
>-			cstate = to_intel_crtc_state(new_crtc_state);
>-			pipe = intel_crtc->pipe;
>+			pipe = crtc->pipe;
> 
>-			if (updated & cmask || !cstate->base.active)
>+			if (updated & cmask || !new_crtc_state->base.active)
> 				continue;
> 
>-			if (skl_ddb_allocation_overlaps(&cstate->wm.skl.ddb,
>+			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
> 							entries,
> 							INTEL_INFO(dev_priv)->num_pipes, i))
> 				continue;
> 
> 			updated |= cmask;
>-			entries[i] = cstate->wm.skl.ddb;
>+			entries[i] = new_crtc_state->wm.skl.ddb;
> 
> 			/*
> 			 * If this is an already active pipe, it's DDB changed,
>@@ -13687,10 +13829,10 @@
> 			 * then we need to wait for a vblank to pass for the
> 			 * new ddb allocation to take effect.
> 			 */
>-			if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
>-						 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
>-			    !new_crtc_state->active_changed &&
>-			    intel_state->wm_results.dirty_pipes != updated)
>+			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
>+						 &old_crtc_state->wm.skl.ddb) &&
>+			    !new_crtc_state->base.active_changed &&
>+			    state->wm_results.dirty_pipes != updated)
> 				vbl_wait = true;
> 
> 			intel_update_crtc(crtc, state, old_crtc_state,
>@@ -13736,18 +13878,21 @@
> 	for (;;) {
> 		prepare_to_wait(&intel_state->commit_ready.wait,
> 				&wait_fence, TASK_UNINTERRUPTIBLE);
>-		prepare_to_wait(&dev_priv->gpu_error.wait_queue,
>+		prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
>+					      I915_RESET_MODESET),
> 				&wait_reset, TASK_UNINTERRUPTIBLE);
> 
> 
>-		if (i915_sw_fence_done(&intel_state->commit_ready)
>-		    || test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))
>+		if (i915_sw_fence_done(&intel_state->commit_ready) ||
>+		    test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
> 			break;
> 
> 		schedule();
> 	}
> 	finish_wait(&intel_state->commit_ready.wait, &wait_fence);
>-	finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);
>+	finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
>+				  I915_RESET_MODESET),
>+		    &wait_reset);
> }
> 
> static void intel_atomic_cleanup_work(struct work_struct *work)
>@@ -13763,57 +13908,49 @@
> 	intel_atomic_helper_free_state(i915);
> }
> 
>-static void intel_atomic_commit_tail(struct drm_atomic_state *state)
>+static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> {
>-	struct drm_device *dev = state->dev;
>-	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>+	struct drm_device *dev = state->base.dev;
> 	struct drm_i915_private *dev_priv = to_i915(dev);
>-	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
>-	struct intel_crtc_state *new_intel_crtc_state, *old_intel_crtc_state;
>-	struct drm_crtc *crtc;
>-	struct intel_crtc *intel_crtc;
>+	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
>+	struct intel_crtc *crtc;
> 	u64 put_domains[I915_MAX_PIPES] = {};
> 	intel_wakeref_t wakeref = 0;
> 	int i;
> 
>-	intel_atomic_commit_fence_wait(intel_state);
>+	intel_atomic_commit_fence_wait(state);
> 
>-	drm_atomic_helper_wait_for_dependencies(state);
>+	drm_atomic_helper_wait_for_dependencies(&state->base);
> 
>-	if (intel_state->modeset)
>+	if (state->modeset)
> 		wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
> 
>-	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
>-		old_intel_crtc_state = to_intel_crtc_state(old_crtc_state);
>-		new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
>-		intel_crtc = to_intel_crtc(crtc);
>-
>+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> 		if (needs_modeset(new_crtc_state) ||
>-		    to_intel_crtc_state(new_crtc_state)->update_pipe) {
>+		    new_crtc_state->update_pipe) {
> 
>-			put_domains[intel_crtc->pipe] =
>-				modeset_get_crtc_power_domains(crtc,
>-					new_intel_crtc_state);
>+			put_domains[crtc->pipe] =
>+				modeset_get_crtc_power_domains(new_crtc_state);
> 		}
> 
> 		if (!needs_modeset(new_crtc_state))
> 			continue;
> 
>-		intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state);
>+		intel_pre_plane_update(old_crtc_state, new_crtc_state);
> 
>-		if (old_crtc_state->active) {
>-			intel_crtc_disable_planes(intel_state, intel_crtc);
>+		if (old_crtc_state->base.active) {
>+			intel_crtc_disable_planes(state, crtc);
> 
> 			/*
> 			 * We need to disable pipe CRC before disabling the pipe,
> 			 * or we race against vblank off.
> 			 */
>-			intel_crtc_disable_pipe_crc(intel_crtc);
>+			intel_crtc_disable_pipe_crc(crtc);
> 
>-			dev_priv->display.crtc_disable(old_intel_crtc_state, state);
>-			intel_crtc->active = false;
>-			intel_fbc_disable(intel_crtc);
>-			intel_disable_shared_dpll(old_intel_crtc_state);
>+			dev_priv->display.crtc_disable(old_crtc_state, state);
>+			crtc->active = false;
>+			intel_fbc_disable(crtc);
>+			intel_disable_shared_dpll(old_crtc_state);
> 
> 			/*
> 			 * Underruns don't always raise
>@@ -13823,25 +13960,25 @@
> 			intel_check_pch_fifo_underruns(dev_priv);
> 
> 			/* FIXME unify this for all platforms */
>-			if (!new_crtc_state->active &&
>+			if (!new_crtc_state->base.active &&
> 			    !HAS_GMCH(dev_priv) &&
> 			    dev_priv->display.initial_watermarks)
>-				dev_priv->display.initial_watermarks(intel_state,
>-								     new_intel_crtc_state);
>+				dev_priv->display.initial_watermarks(state,
>+								     new_crtc_state);
> 		}
> 	}
> 
>-	/* FIXME: Eventually get rid of our intel_crtc->config pointer */
>-	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)
>-		to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
>+	/* FIXME: Eventually get rid of our crtc->config pointer */
>+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
>+		crtc->config = new_crtc_state;
> 
>-	if (intel_state->modeset) {
>-		drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
>+	if (state->modeset) {
>+		drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
> 
> 		intel_set_cdclk_pre_plane_update(dev_priv,
>-						 &intel_state->cdclk.actual,
>+						 &state->cdclk.actual,
> 						 &dev_priv->cdclk.actual,
>-						 intel_state->cdclk.pipe);
>+						 state->cdclk.pipe);
> 
> 		/*
> 		 * SKL workaround: bspec recommends we disable the SAGV when we
>@@ -13850,31 +13987,37 @@
> 		if (!intel_can_enable_sagv(state))
> 			intel_disable_sagv(dev_priv);
> 
>-		intel_modeset_verify_disabled(dev, state);
>+		intel_modeset_verify_disabled(dev_priv, state);
> 	}
> 
> 	/* Complete the events for pipes that have now been disabled */
>-	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
>+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> 		bool modeset = needs_modeset(new_crtc_state);
> 
> 		/* Complete events for now disable pipes here. */
>-		if (modeset && !new_crtc_state->active && new_crtc_state->event) {
>+		if (modeset && !new_crtc_state->base.active && new_crtc_state->base.event) {
> 			spin_lock_irq(&dev->event_lock);
>-			drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
>+			drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
> 			spin_unlock_irq(&dev->event_lock);
> 
>-			new_crtc_state->event = NULL;
>+			new_crtc_state->base.event = NULL;
> 		}
> 	}
> 
>+	if (state->modeset)
>+		intel_encoders_update_prepare(state);
>+
> 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
> 	dev_priv->display.update_crtcs(state);
> 
>-	if (intel_state->modeset)
>+	if (state->modeset) {
>+		intel_encoders_update_complete(state);
>+
> 		intel_set_cdclk_post_plane_update(dev_priv,
>-						  &intel_state->cdclk.actual,
>+						  &state->cdclk.actual,
> 						  &dev_priv->cdclk.actual,
>-						  intel_state->cdclk.pipe);
>+						  state->cdclk.pipe);
>+	}
> 
> 	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
> 	 * already, but still need the state for the delayed optimization. To
>@@ -13885,16 +14028,14 @@
> 	 * - switch over to the vblank wait helper in the core after that since
> 	 *   we don't need out special handling any more.
> 	 */
>-	drm_atomic_helper_wait_for_flip_done(dev, state);
>+	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
> 
>-	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
>-		new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
>-
>-		if (new_crtc_state->active &&
>+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>+		if (new_crtc_state->base.active &&
> 		    !needs_modeset(new_crtc_state) &&
>-		    (new_intel_crtc_state->base.color_mgmt_changed ||
>-		     new_intel_crtc_state->update_pipe))
>-			intel_color_load_luts(new_intel_crtc_state);
>+		    (new_crtc_state->base.color_mgmt_changed ||
>+		     new_crtc_state->update_pipe))
>+			intel_color_load_luts(new_crtc_state);
> 	}
> 
> 	/*
>@@ -13904,16 +14045,14 @@
> 	 *
> 	 * TODO: Move this (and other cleanup) to an async worker eventually.
> 	 */
>-	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
>-		new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
>-
>+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> 		if (dev_priv->display.optimize_watermarks)
>-			dev_priv->display.optimize_watermarks(intel_state,
>-							      new_intel_crtc_state);
>+			dev_priv->display.optimize_watermarks(state,
>+							      new_crtc_state);
> 	}
> 
>-	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
>-		intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
>+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
>+		intel_post_plane_update(old_crtc_state);
> 
> 		if (put_domains[i])
> 			modeset_put_power_domains(dev_priv, put_domains[i]);
>@@ -13921,15 +14060,15 @@
> 		intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
> 	}
> 
>-	if (intel_state->modeset)
>-		intel_verify_planes(intel_state);
>+	if (state->modeset)
>+		intel_verify_planes(state);
> 
>-	if (intel_state->modeset && intel_can_enable_sagv(state))
>+	if (state->modeset && intel_can_enable_sagv(state))
> 		intel_enable_sagv(dev_priv);
> 
>-	drm_atomic_helper_commit_hw_done(state);
>+	drm_atomic_helper_commit_hw_done(&state->base);
> 
>-	if (intel_state->modeset) {
>+	if (state->modeset) {
> 		/* As one of the primary mmio accessors, KMS has a high
> 		 * likelihood of triggering bugs in unclaimed access. After we
> 		 * finish modesetting, see if an error has been flagged, and if
>@@ -13939,7 +14078,7 @@
> 		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
> 		intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
> 	}
>-	intel_runtime_pm_put(&dev_priv->runtime_pm, intel_state->wakeref);
>+	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
> 
> 	/*
> 	 * Defer the cleanup of the old state to a separate worker to not
>@@ -13949,14 +14088,14 @@
> 	 * schedule point (cond_resched()) here anyway to keep latencies
> 	 * down.
> 	 */
>-	INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);
>-	queue_work(system_highpri_wq, &state->commit_work);
>+	INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
>+	queue_work(system_highpri_wq, &state->base.commit_work);
> }
> 
> static void intel_atomic_commit_work(struct work_struct *work)
> {
>-	struct drm_atomic_state *state =
>-		container_of(work, struct drm_atomic_state, commit_work);
>+	struct intel_atomic_state *state =
>+		container_of(work, struct intel_atomic_state, base.commit_work);
> 
> 	intel_atomic_commit_tail(state);
> }
>@@ -13986,42 +14125,31 @@
> 	return NOTIFY_DONE;
> }
> 
>-static void intel_atomic_track_fbs(struct drm_atomic_state *state)
>+static void intel_atomic_track_fbs(struct intel_atomic_state *state)
> {
>-	struct drm_plane_state *old_plane_state, *new_plane_state;
>-	struct drm_plane *plane;
>+	struct intel_plane_state *old_plane_state, *new_plane_state;
>+	struct intel_plane *plane;
> 	int i;
> 
>-	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
>-		i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
>-				  intel_fb_obj(new_plane_state->fb),
>-				  to_intel_plane(plane)->frontbuffer_bit);
>+	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
>+					     new_plane_state, i)
>+		i915_gem_track_fb(intel_fb_obj(old_plane_state->base.fb),
>+				  intel_fb_obj(new_plane_state->base.fb),
>+				  plane->frontbuffer_bit);
> }
> 
>-/**
>- * intel_atomic_commit - commit validated state object
>- * @dev: DRM device
>- * @state: the top-level driver state object
>- * @nonblock: nonblocking commit
>- *
>- * This function commits a top-level state object that has been validated
>- * with drm_atomic_helper_check().
>- *
>- * RETURNS
>- * Zero for success or -errno.
>- */
> static int intel_atomic_commit(struct drm_device *dev,
>-			       struct drm_atomic_state *state,
>+			       struct drm_atomic_state *_state,
> 			       bool nonblock)
> {
>-	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>+	struct intel_atomic_state *state = to_intel_atomic_state(_state);
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 	int ret = 0;
> 
>-	intel_state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>+	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> 
>-	drm_atomic_state_get(state);
>-	i915_sw_fence_init(&intel_state->commit_ready,
>+	drm_atomic_state_get(&state->base);
>+	i915_sw_fence_init(&state->commit_ready,
> 			   intel_atomic_commit_ready);
> 
> 	/*
>@@ -14041,63 +14169,61 @@
> 	 * FIXME doing watermarks and fb cleanup from a vblank worker
> 	 * (assuming we had any) would solve these problems.
> 	 */
>-	if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {
>+	if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
> 		struct intel_crtc_state *new_crtc_state;
> 		struct intel_crtc *crtc;
> 		int i;
> 
>-		for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)
>+		for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> 			if (new_crtc_state->wm.need_postvbl_update ||
> 			    new_crtc_state->update_wm_post)
>-				state->legacy_cursor_update = false;
>+				state->base.legacy_cursor_update = false;
> 	}
> 
>-	ret = intel_atomic_prepare_commit(dev, state);
>+	ret = intel_atomic_prepare_commit(state);
> 	if (ret) {
> 		DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
>-		i915_sw_fence_commit(&intel_state->commit_ready);
>-		intel_runtime_pm_put(&dev_priv->runtime_pm, intel_state->wakeref);
>+		i915_sw_fence_commit(&state->commit_ready);
>+		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
> 		return ret;
> 	}
> 
>-	ret = drm_atomic_helper_setup_commit(state, nonblock);
>+	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
> 	if (!ret)
>-		ret = drm_atomic_helper_swap_state(state, true);
>+		ret = drm_atomic_helper_swap_state(&state->base, true);
> 
> 	if (ret) {
>-		i915_sw_fence_commit(&intel_state->commit_ready);
>+		i915_sw_fence_commit(&state->commit_ready);
> 
>-		drm_atomic_helper_cleanup_planes(dev, state);
>-		intel_runtime_pm_put(&dev_priv->runtime_pm, intel_state->wakeref);
>+		drm_atomic_helper_cleanup_planes(dev, &state->base);
>+		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
> 		return ret;
> 	}
> 	dev_priv->wm.distrust_bios_wm = false;
> 	intel_shared_dpll_swap_state(state);
> 	intel_atomic_track_fbs(state);
> 
>-	if (intel_state->modeset) {
>-		memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,
>-		       sizeof(intel_state->min_cdclk));
>-		memcpy(dev_priv->min_voltage_level,
>-		       intel_state->min_voltage_level,
>-		       sizeof(intel_state->min_voltage_level));
>-		dev_priv->active_crtcs = intel_state->active_crtcs;
>-		dev_priv->cdclk.force_min_cdclk =
>-			intel_state->cdclk.force_min_cdclk;
>-
>-		intel_cdclk_swap_state(intel_state);
>-	}
>-
>-	drm_atomic_state_get(state);
>-	INIT_WORK(&state->commit_work, intel_atomic_commit_work);
>-
>-	i915_sw_fence_commit(&intel_state->commit_ready);
>-	if (nonblock && intel_state->modeset) {
>-		queue_work(dev_priv->modeset_wq, &state->commit_work);
>+	if (state->modeset) {
>+		memcpy(dev_priv->min_cdclk, state->min_cdclk,
>+		       sizeof(state->min_cdclk));
>+		memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
>+		       sizeof(state->min_voltage_level));
>+		dev_priv->active_crtcs = state->active_crtcs;
>+		dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
>+
>+		intel_cdclk_swap_state(state);
>+	}
>+
>+	drm_atomic_state_get(&state->base);
>+	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
>+
>+	i915_sw_fence_commit(&state->commit_ready);
>+	if (nonblock && state->modeset) {
>+		queue_work(dev_priv->modeset_wq, &state->base.commit_work);
> 	} else if (nonblock) {
>-		queue_work(system_unbound_wq, &state->commit_work);
>+		queue_work(system_unbound_wq, &state->base.commit_work);
> 	} else {
>-		if (intel_state->modeset)
>+		if (state->modeset)
> 			flush_workqueue(dev_priv->modeset_wq);
> 		intel_atomic_commit_tail(state);
> 	}
>@@ -14105,18 +14231,6 @@
> 	return 0;
> }
> 
>-static const struct drm_crtc_funcs intel_crtc_funcs = {
>-	.gamma_set = drm_atomic_helper_legacy_gamma_set,
>-	.set_config = drm_atomic_helper_set_config,
>-	.destroy = intel_crtc_destroy,
>-	.page_flip = drm_atomic_helper_page_flip,
>-	.atomic_duplicate_state = intel_crtc_duplicate_state,
>-	.atomic_destroy_state = intel_crtc_destroy_state,
>-	.set_crc_source = intel_crtc_set_crc_source,
>-	.verify_crc_source = intel_crtc_verify_crc_source,
>-	.get_crc_sources = intel_crtc_get_crc_sources,
>-};
>-
> struct wait_rps_boost {
> 	struct wait_queue_entry wait;
> 
>@@ -14250,9 +14364,9 @@
> 	int ret;
> 
> 	if (old_obj) {
>-		struct drm_crtc_state *crtc_state =
>-			drm_atomic_get_new_crtc_state(new_state->state,
>-						      plane->state->crtc);
>+		struct intel_crtc_state *crtc_state =
>+			intel_atomic_get_new_crtc_state(intel_state,
>+							to_intel_crtc(plane->state->crtc));
> 
> 		/* Big Hammer, we also need to ensure that any pending
> 		 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
>@@ -14413,7 +14527,7 @@
> 		intel_atomic_get_old_crtc_state(state, crtc);
> 	struct intel_crtc_state *new_crtc_state =
> 		intel_atomic_get_new_crtc_state(state, crtc);
>-	bool modeset = needs_modeset(&new_crtc_state->base);
>+	bool modeset = needs_modeset(new_crtc_state);
> 
> 	/* Perform vblank evasion around commit operation */
> 	intel_pipe_update_start(new_crtc_state);
>@@ -14466,7 +14580,7 @@
> 	intel_pipe_update_end(new_crtc_state);
> 
> 	if (new_crtc_state->update_pipe &&
>-	    !needs_modeset(&new_crtc_state->base) &&
>+	    !needs_modeset(new_crtc_state) &&
> 	    old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
> 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
> }
>@@ -14580,7 +14694,7 @@
> 	 * When crtc is inactive or there is a modeset pending,
> 	 * wait for it to complete in the slowpath
> 	 */
>-	if (!crtc_state->base.active || needs_modeset(&crtc_state->base) ||
>+	if (!crtc_state->base.active || needs_modeset(crtc_state) ||
> 	    crtc_state->update_pipe)
> 		goto slow;
> 
>@@ -14910,8 +15024,76 @@
> 	scaler_state->scaler_id = -1;
> }
> 
>+#define INTEL_CRTC_FUNCS \
>+	.gamma_set = drm_atomic_helper_legacy_gamma_set, \
>+	.set_config = drm_atomic_helper_set_config, \
>+	.destroy = intel_crtc_destroy, \
>+	.page_flip = drm_atomic_helper_page_flip, \
>+	.atomic_duplicate_state = intel_crtc_duplicate_state, \
>+	.atomic_destroy_state = intel_crtc_destroy_state, \
>+	.set_crc_source = intel_crtc_set_crc_source, \
>+	.verify_crc_source = intel_crtc_verify_crc_source, \
>+	.get_crc_sources = intel_crtc_get_crc_sources
>+
>+static const struct drm_crtc_funcs bdw_crtc_funcs = {
>+	INTEL_CRTC_FUNCS,
>+
>+	.get_vblank_counter = g4x_get_vblank_counter,
>+	.enable_vblank = bdw_enable_vblank,
>+	.disable_vblank = bdw_disable_vblank,
>+};
>+
>+static const struct drm_crtc_funcs ilk_crtc_funcs = {
>+	INTEL_CRTC_FUNCS,
>+
>+	.get_vblank_counter = g4x_get_vblank_counter,
>+	.enable_vblank = ilk_enable_vblank,
>+	.disable_vblank = ilk_disable_vblank,
>+};
>+
>+static const struct drm_crtc_funcs g4x_crtc_funcs = {
>+	INTEL_CRTC_FUNCS,
>+
>+	.get_vblank_counter = g4x_get_vblank_counter,
>+	.enable_vblank = i965_enable_vblank,
>+	.disable_vblank = i965_disable_vblank,
>+};
>+
>+static const struct drm_crtc_funcs i965_crtc_funcs = {
>+	INTEL_CRTC_FUNCS,
>+
>+	.get_vblank_counter = i915_get_vblank_counter,
>+	.enable_vblank = i965_enable_vblank,
>+	.disable_vblank = i965_disable_vblank,
>+};
>+
>+static const struct drm_crtc_funcs i945gm_crtc_funcs = {
>+	INTEL_CRTC_FUNCS,
>+
>+	.get_vblank_counter = i915_get_vblank_counter,
>+	.enable_vblank = i945gm_enable_vblank,
>+	.disable_vblank = i945gm_disable_vblank,
>+};
>+
>+static const struct drm_crtc_funcs i915_crtc_funcs = {
>+	INTEL_CRTC_FUNCS,
>+
>+	.get_vblank_counter = i915_get_vblank_counter,
>+	.enable_vblank = i8xx_enable_vblank,
>+	.disable_vblank = i8xx_disable_vblank,
>+};
>+
>+static const struct drm_crtc_funcs i8xx_crtc_funcs = {
>+	INTEL_CRTC_FUNCS,
>+
>+	/* no hw vblank counter */
>+	.enable_vblank = i8xx_enable_vblank,
>+	.disable_vblank = i8xx_disable_vblank,
>+};
>+
> static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
> {
>+	const struct drm_crtc_funcs *funcs;
> 	struct intel_crtc *intel_crtc;
> 	struct intel_crtc_state *crtc_state = NULL;
> 	struct intel_plane *primary = NULL;
>@@ -14955,10 +15137,28 @@
> 	}
> 	intel_crtc->plane_ids_mask |= BIT(cursor->id);
> 
>+	if (HAS_GMCH(dev_priv)) {
>+		if (IS_CHERRYVIEW(dev_priv) ||
>+		    IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv))
>+			funcs = &g4x_crtc_funcs;
>+		else if (IS_GEN(dev_priv, 4))
>+			funcs = &i965_crtc_funcs;
>+		else if (IS_I945GM(dev_priv))
>+			funcs = &i945gm_crtc_funcs;
>+		else if (IS_GEN(dev_priv, 3))
>+			funcs = &i915_crtc_funcs;
>+		else
>+			funcs = &i8xx_crtc_funcs;
>+	} else {
>+		if (INTEL_GEN(dev_priv) >= 8)
>+			funcs = &bdw_crtc_funcs;
>+		else
>+			funcs = &ilk_crtc_funcs;
>+	}
>+
> 	ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
> 					&primary->base, &cursor->base,
>-					&intel_crtc_funcs,
>-					"pipe %c", pipe_name(pipe));
>+					funcs, "pipe %c", pipe_name(pipe));
> 	if (ret)
> 		goto fail;
> 
>@@ -15114,12 +15314,18 @@
> 	if (!HAS_DISPLAY(dev_priv))
> 		return;
> 
>-	if (IS_ELKHARTLAKE(dev_priv)) {
>+	if (INTEL_GEN(dev_priv) >= 12) {
>+		/* TODO: initialize TC ports as well */
>+		intel_ddi_init(dev_priv, PORT_A);
>+		intel_ddi_init(dev_priv, PORT_B);
>+		intel_ddi_init(dev_priv, PORT_C);
>+	} else if (IS_ELKHARTLAKE(dev_priv)) {
> 		intel_ddi_init(dev_priv, PORT_A);
> 		intel_ddi_init(dev_priv, PORT_B);
> 		intel_ddi_init(dev_priv, PORT_C);
>+		intel_ddi_init(dev_priv, PORT_D);
> 		icl_dsi_init(dev_priv);
>-	} else if (INTEL_GEN(dev_priv) >= 11) {
>+	} else if (IS_GEN(dev_priv, 11)) {
> 		intel_ddi_init(dev_priv, PORT_A);
> 		intel_ddi_init(dev_priv, PORT_B);
> 		intel_ddi_init(dev_priv, PORT_C);
>@@ -15775,8 +15981,8 @@
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct drm_atomic_state *state;
> 	struct intel_atomic_state *intel_state;
>-	struct drm_crtc *crtc;
>-	struct drm_crtc_state *cstate;
>+	struct intel_crtc *crtc;
>+	struct intel_crtc_state *crtc_state;
> 	struct drm_modeset_acquire_ctx ctx;
> 	int ret;
> 	int i;
>@@ -15831,13 +16037,11 @@
> 	}
> 
> 	/* Write calculated watermark values back */
>-	for_each_new_crtc_in_state(state, crtc, cstate, i) {
>-		struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
>-
>-		cs->wm.need_postvbl_update = true;
>-		dev_priv->display.optimize_watermarks(intel_state, cs);
>+	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
>+		crtc_state->wm.need_postvbl_update = true;
>+		dev_priv->display.optimize_watermarks(intel_state, crtc_state);
> 
>-		to_intel_crtc_state(crtc->state)->wm = cs->wm;
>+		to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
> 	}
> 
> put_state:
>@@ -16495,6 +16699,13 @@
> 
> 		pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
> 							&pll->state.hw_state);
>+
>+		if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
>+		    pll->info->id == DPLL_ID_EHL_DPLL4) {
>+			pll->wakeref = intel_display_power_get(dev_priv,
>+							       POWER_DOMAIN_DPLL_DC_OFF);
>+		}
>+
> 		pll->state.crtc_mask = 0;
> 		for_each_intel_crtc(dev, crtc) {
> 			struct intel_crtc_state *crtc_state =
>@@ -16744,6 +16955,17 @@
> 	intel_modeset_readout_hw_state(dev);
> 
> 	/* HW state is read out, now we need to sanitize this mess. */
>+
>+	/* Sanitize the TypeC port mode upfront, encoders depend on this */
>+	for_each_intel_encoder(dev, encoder) {
>+		enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+
>+		/* We need to sanitize only the MST primary port. */
>+		if (encoder->type != INTEL_OUTPUT_DP_MST &&
>+		    intel_phy_is_tc(dev_priv, phy))
>+			intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
>+	}
>+
> 	get_encoder_power_domains(dev_priv);
> 
> 	if (HAS_PCH_IBX(dev_priv))
>@@ -16804,7 +17026,7 @@
> 		u64 put_domains;
> 
> 		crtc_state = to_intel_crtc_state(crtc->base.state);
>-		put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc_state);
>+		put_domains = modeset_get_crtc_power_domains(crtc_state);
> 		if (WARN_ON(put_domains))
> 			modeset_put_power_domains(dev_priv, put_domains);
> 	}
>@@ -16866,7 +17088,7 @@
> 	drm_connector_list_iter_end(&conn_iter);
> }
> 
>-void intel_modeset_cleanup(struct drm_device *dev)
>+void intel_modeset_driver_remove(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 
>@@ -16982,7 +17204,7 @@
> 		u32 vtotal;
> 		u32 vblank;
> 		u32 vsync;
>-	} transcoder[4];
>+	} transcoder[5];
> };
> 
> struct intel_display_error_state *
>@@ -16993,6 +17215,7 @@
> 		TRANSCODER_A,
> 		TRANSCODER_B,
> 		TRANSCODER_C,
>+		TRANSCODER_D,
> 		TRANSCODER_EDP,
> 	};
> 	int i;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_display.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_display.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_display.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_display.h	2019-08-31 15:01:12.017736182 -0500
>@@ -45,6 +45,8 @@
> 	GPIOK,
> 	GPIOL,
> 	GPIOM,
>+	GPION,
>+	GPIOO,
> };
> 
> /*
>@@ -58,6 +60,7 @@
> 	PIPE_A = 0,
> 	PIPE_B,
> 	PIPE_C,
>+	PIPE_D,
> 	_PIPE_EDP,
> 
> 	I915_MAX_PIPES = _PIPE_EDP
>@@ -75,6 +78,7 @@
> 	TRANSCODER_A = PIPE_A,
> 	TRANSCODER_B = PIPE_B,
> 	TRANSCODER_C = PIPE_C,
>+	TRANSCODER_D = PIPE_D,
> 
> 	/*
> 	 * The following transcoders can map to any pipe, their enum value
>@@ -98,6 +102,8 @@
> 		return "B";
> 	case TRANSCODER_C:
> 		return "C";
>+	case TRANSCODER_D:
>+		return "D";
> 	case TRANSCODER_EDP:
> 		return "EDP";
> 	case TRANSCODER_DSI_A:
>@@ -173,6 +179,12 @@
> 		return "Port E";
> 	case PORT_F:
> 		return "Port F";
>+	case PORT_G:
>+		return "Port G";
>+	case PORT_H:
>+		return "Port H";
>+	case PORT_I:
>+		return "Port I";
> 	default:
> 		return "<invalid>";
> 	}
>@@ -185,14 +197,15 @@
> 	PORT_TC2,
> 	PORT_TC3,
> 	PORT_TC4,
>+	PORT_TC5,
>+	PORT_TC6,
> 
> 	I915_MAX_TC_PORTS
> };
> 
>-enum tc_port_type {
>-	TC_PORT_UNKNOWN = 0,
>-	TC_PORT_TYPEC,
>-	TC_PORT_TBT,
>+enum tc_port_mode {
>+	TC_PORT_TBT_ALT,
>+	TC_PORT_DP_ALT,
> 	TC_PORT_LEGACY,
> };
> 
>@@ -229,6 +242,30 @@
> 	u32 link_n;
> };
> 
>+enum phy {
>+	PHY_NONE = -1,
>+
>+	PHY_A = 0,
>+	PHY_B,
>+	PHY_C,
>+	PHY_D,
>+	PHY_E,
>+	PHY_F,
>+	PHY_G,
>+	PHY_H,
>+	PHY_I,
>+
>+	I915_MAX_PHYS
>+};
>+
>+#define phy_name(a) ((a) + 'A')
>+
>+enum phy_fia {
>+	FIA1,
>+	FIA2,
>+	FIA3,
>+};
>+
> #define for_each_pipe(__dev_priv, __p) \
> 	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
> 
>@@ -254,6 +291,10 @@
> 	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
> 		for_each_if((__ports_mask) & BIT(__port))
> 
>+#define for_each_phy_masked(__phy, __phys_mask) \
>+	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
>+		for_each_if((__phys_mask) & BIT(__phy))
>+
> #define for_each_crtc(dev, crtc) \
> 	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
> 
>@@ -357,5 +398,6 @@
> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> 			      u32 pixel_format, u64 modifier);
> bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
>+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> 
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_display_power.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_display_power.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_display_power.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_display_power.c	2019-08-31 15:01:12.017736182 -0500
>@@ -17,13 +17,17 @@
> #include "intel_drv.h"
> #include "intel_hotplug.h"
> #include "intel_sideband.h"
>+#include "intel_tc.h"
> 
> bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> 					 enum i915_power_well_id power_well_id);
> 
> const char *
>-intel_display_power_domain_str(enum intel_display_power_domain domain)
>+intel_display_power_domain_str(struct drm_i915_private *i915,
>+			       enum intel_display_power_domain domain)
> {
>+	bool ddi_tc_ports = IS_GEN(i915, 12);
>+
> 	switch (domain) {
> 	case POWER_DOMAIN_DISPLAY_CORE:
> 		return "DISPLAY_CORE";
>@@ -33,22 +37,28 @@
> 		return "PIPE_B";
> 	case POWER_DOMAIN_PIPE_C:
> 		return "PIPE_C";
>+	case POWER_DOMAIN_PIPE_D:
>+		return "PIPE_D";
> 	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
> 		return "PIPE_A_PANEL_FITTER";
> 	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
> 		return "PIPE_B_PANEL_FITTER";
> 	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
> 		return "PIPE_C_PANEL_FITTER";
>+	case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
>+		return "PIPE_D_PANEL_FITTER";
> 	case POWER_DOMAIN_TRANSCODER_A:
> 		return "TRANSCODER_A";
> 	case POWER_DOMAIN_TRANSCODER_B:
> 		return "TRANSCODER_B";
> 	case POWER_DOMAIN_TRANSCODER_C:
> 		return "TRANSCODER_C";
>+	case POWER_DOMAIN_TRANSCODER_D:
>+		return "TRANSCODER_D";
> 	case POWER_DOMAIN_TRANSCODER_EDP:
> 		return "TRANSCODER_EDP";
>-	case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
>-		return "TRANSCODER_EDP_VDSC";
>+	case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
>+		return "TRANSCODER_VDSC_PW2";
> 	case POWER_DOMAIN_TRANSCODER_DSI_A:
> 		return "TRANSCODER_DSI_A";
> 	case POWER_DOMAIN_TRANSCODER_DSI_C:
>@@ -60,11 +70,23 @@
> 	case POWER_DOMAIN_PORT_DDI_C_LANES:
> 		return "PORT_DDI_C_LANES";
> 	case POWER_DOMAIN_PORT_DDI_D_LANES:
>-		return "PORT_DDI_D_LANES";
>+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
>+			     POWER_DOMAIN_PORT_DDI_TC1_LANES);
>+		return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
> 	case POWER_DOMAIN_PORT_DDI_E_LANES:
>-		return "PORT_DDI_E_LANES";
>+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
>+			     POWER_DOMAIN_PORT_DDI_TC2_LANES);
>+		return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
> 	case POWER_DOMAIN_PORT_DDI_F_LANES:
>-		return "PORT_DDI_F_LANES";
>+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
>+			     POWER_DOMAIN_PORT_DDI_TC3_LANES);
>+		return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
>+	case POWER_DOMAIN_PORT_DDI_TC4_LANES:
>+		return "PORT_DDI_TC4_LANES";
>+	case POWER_DOMAIN_PORT_DDI_TC5_LANES:
>+		return "PORT_DDI_TC5_LANES";
>+	case POWER_DOMAIN_PORT_DDI_TC6_LANES:
>+		return "PORT_DDI_TC6_LANES";
> 	case POWER_DOMAIN_PORT_DDI_A_IO:
> 		return "PORT_DDI_A_IO";
> 	case POWER_DOMAIN_PORT_DDI_B_IO:
>@@ -72,11 +94,23 @@
> 	case POWER_DOMAIN_PORT_DDI_C_IO:
> 		return "PORT_DDI_C_IO";
> 	case POWER_DOMAIN_PORT_DDI_D_IO:
>-		return "PORT_DDI_D_IO";
>+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
>+			     POWER_DOMAIN_PORT_DDI_TC1_IO);
>+		return ddi_tc_ports ? "PORT_DDI_TC1_IO" : "PORT_DDI_D_IO";
> 	case POWER_DOMAIN_PORT_DDI_E_IO:
>-		return "PORT_DDI_E_IO";
>+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
>+			     POWER_DOMAIN_PORT_DDI_TC2_IO);
>+		return ddi_tc_ports ? "PORT_DDI_TC2_IO" : "PORT_DDI_E_IO";
> 	case POWER_DOMAIN_PORT_DDI_F_IO:
>-		return "PORT_DDI_F_IO";
>+		BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
>+			     POWER_DOMAIN_PORT_DDI_TC3_IO);
>+		return ddi_tc_ports ? "PORT_DDI_TC3_IO" : "PORT_DDI_F_IO";
>+	case POWER_DOMAIN_PORT_DDI_TC4_IO:
>+		return "PORT_DDI_TC4_IO";
>+	case POWER_DOMAIN_PORT_DDI_TC5_IO:
>+		return "PORT_DDI_TC5_IO";
>+	case POWER_DOMAIN_PORT_DDI_TC6_IO:
>+		return "PORT_DDI_TC6_IO";
> 	case POWER_DOMAIN_PORT_DSI:
> 		return "PORT_DSI";
> 	case POWER_DOMAIN_PORT_CRT:
>@@ -94,11 +128,20 @@
> 	case POWER_DOMAIN_AUX_C:
> 		return "AUX_C";
> 	case POWER_DOMAIN_AUX_D:
>-		return "AUX_D";
>+		BUILD_BUG_ON(POWER_DOMAIN_AUX_D != POWER_DOMAIN_AUX_TC1);
>+		return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
> 	case POWER_DOMAIN_AUX_E:
>-		return "AUX_E";
>+		BUILD_BUG_ON(POWER_DOMAIN_AUX_E != POWER_DOMAIN_AUX_TC2);
>+		return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
> 	case POWER_DOMAIN_AUX_F:
>-		return "AUX_F";
>+		BUILD_BUG_ON(POWER_DOMAIN_AUX_F != POWER_DOMAIN_AUX_TC3);
>+		return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
>+	case POWER_DOMAIN_AUX_TC4:
>+		return "AUX_TC4";
>+	case POWER_DOMAIN_AUX_TC5:
>+		return "AUX_TC5";
>+	case POWER_DOMAIN_AUX_TC6:
>+		return "AUX_TC6";
> 	case POWER_DOMAIN_AUX_IO_A:
> 		return "AUX_IO_A";
> 	case POWER_DOMAIN_AUX_TBT1:
>@@ -109,6 +152,10 @@
> 		return "AUX_TBT3";
> 	case POWER_DOMAIN_AUX_TBT4:
> 		return "AUX_TBT4";
>+	case POWER_DOMAIN_AUX_TBT5:
>+		return "AUX_TBT5";
>+	case POWER_DOMAIN_AUX_TBT6:
>+		return "AUX_TBT6";
> 	case POWER_DOMAIN_GMBUS:
> 		return "GMBUS";
> 	case POWER_DOMAIN_INIT:
>@@ -117,6 +164,8 @@
> 		return "MODESET";
> 	case POWER_DOMAIN_GT_IRQ:
> 		return "GT_IRQ";
>+	case POWER_DOMAIN_DPLL_DC_OFF:
>+		return "DPLL_DC_OFF";
> 	default:
> 		MISSING_CASE(domain);
> 		return "?";
>@@ -269,11 +318,17 @@
> 	int pw_idx = power_well->desc->hsw.idx;
> 
> 	/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
>-	WARN_ON(intel_wait_for_register(&dev_priv->uncore,
>-					regs->driver,
>-					HSW_PWR_WELL_CTL_STATE(pw_idx),
>-					HSW_PWR_WELL_CTL_STATE(pw_idx),
>-					1));
>+	if (intel_wait_for_register(&dev_priv->uncore,
>+				    regs->driver,
>+				    HSW_PWR_WELL_CTL_STATE(pw_idx),
>+				    HSW_PWR_WELL_CTL_STATE(pw_idx),
>+				    1)) {
>+		DRM_DEBUG_KMS("%s power well enable timeout\n",
>+			      power_well->desc->name);
>+
>+		/* An AUX timeout is expected if the TBT DP tunnel is down. */
>+		WARN_ON(!power_well->desc->hsw.is_tc_tbt);
>+	}
> }
> 
> static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
>@@ -388,7 +443,7 @@
> 	hsw_wait_for_power_well_disable(dev_priv, power_well);
> }
> 
>-#define ICL_AUX_PW_TO_PORT(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
>+#define ICL_AUX_PW_TO_PHY(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
> 
> static void
> icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
>@@ -396,21 +451,29 @@
> {
> 	const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> 	int pw_idx = power_well->desc->hsw.idx;
>-	enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
>+	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> 	u32 val;
>+	int wa_idx_max;
> 
> 	val = I915_READ(regs->driver);
> 	I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> 
>-	val = I915_READ(ICL_PORT_CL_DW12(port));
>-	I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
>+	if (INTEL_GEN(dev_priv) < 12) {
>+		val = I915_READ(ICL_PORT_CL_DW12(phy));
>+		I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
>+	}
> 
> 	hsw_wait_for_power_well_enable(dev_priv, power_well);
> 
>-	/* Display WA #1178: icl */
>-	if (IS_ICELAKE(dev_priv) &&
>-	    pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
>-	    !intel_bios_is_port_edp(dev_priv, port)) {
>+	/* Display WA #1178: icl, tgl */
>+	if (IS_TIGERLAKE(dev_priv))
>+		wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
>+	else
>+		wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
>+
>+	if (!IS_ELKHARTLAKE(dev_priv) &&
>+	    pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
>+	    !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
> 		val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
> 		val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
> 		I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val);
>@@ -423,11 +486,13 @@
> {
> 	const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> 	int pw_idx = power_well->desc->hsw.idx;
>-	enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
>+	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> 	u32 val;
> 
>-	val = I915_READ(ICL_PORT_CL_DW12(port));
>-	I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
>+	if (INTEL_GEN(dev_priv) < 12) {
>+		val = I915_READ(ICL_PORT_CL_DW12(phy));
>+		I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
>+	}
> 
> 	val = I915_READ(regs->driver);
> 	I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
>@@ -441,26 +506,108 @@
> #define ICL_TBT_AUX_PW_TO_CH(pw_idx)	\
> 	((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
> 
>+static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
>+				     struct i915_power_well *power_well)
>+{
>+	int pw_idx = power_well->desc->hsw.idx;
>+
>+	return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
>+						 ICL_AUX_PW_TO_CH(pw_idx);
>+}
>+
>+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
>+
>+static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
>+
>+static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
>+				      struct i915_power_well *power_well)
>+{
>+	int refs = hweight64(power_well->desc->domains &
>+			     async_put_domains_mask(&dev_priv->power_domains));
>+
>+	WARN_ON(refs > power_well->count);
>+
>+	return refs;
>+}
>+
>+static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
>+					struct i915_power_well *power_well)
>+{
>+	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
>+	struct intel_digital_port *dig_port = NULL;
>+	struct intel_encoder *encoder;
>+
>+	/* Bypass the check if all references are released asynchronously */
>+	if (power_well_async_ref_count(dev_priv, power_well) ==
>+	    power_well->count)
>+		return;
>+
>+	aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
>+
>+	for_each_intel_encoder(&dev_priv->drm, encoder) {
>+		enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+
>+		if (!intel_phy_is_tc(dev_priv, phy))
>+			continue;
>+
>+		/* We'll check the MST primary port */
>+		if (encoder->type == INTEL_OUTPUT_DP_MST)
>+			continue;
>+
>+		dig_port = enc_to_dig_port(&encoder->base);
>+		if (WARN_ON(!dig_port))
>+			continue;
>+
>+		if (dig_port->aux_ch != aux_ch) {
>+			dig_port = NULL;
>+			continue;
>+		}
>+
>+		break;
>+	}
>+
>+	if (WARN_ON(!dig_port))
>+		return;
>+
>+	WARN_ON(!intel_tc_port_ref_held(dig_port));
>+}
>+
>+#else
>+
>+static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
>+					struct i915_power_well *power_well)
>+{
>+}
>+
>+#endif
>+
> static void
> icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> 				 struct i915_power_well *power_well)
> {
>-	int pw_idx = power_well->desc->hsw.idx;
>-	bool is_tbt = power_well->desc->hsw.is_tc_tbt;
>-	enum aux_ch aux_ch;
>+	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
> 	u32 val;
> 
>-	aux_ch = is_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
>-			  ICL_AUX_PW_TO_CH(pw_idx);
>+	icl_tc_port_assert_ref_held(dev_priv, power_well);
>+
> 	val = I915_READ(DP_AUX_CH_CTL(aux_ch));
> 	val &= ~DP_AUX_CH_CTL_TBT_IO;
>-	if (is_tbt)
>+	if (power_well->desc->hsw.is_tc_tbt)
> 		val |= DP_AUX_CH_CTL_TBT_IO;
> 	I915_WRITE(DP_AUX_CH_CTL(aux_ch), val);
> 
> 	hsw_power_well_enable(dev_priv, power_well);
> }
> 
>+static void
>+icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
>+				  struct i915_power_well *power_well)
>+{
>+	icl_tc_port_assert_ref_held(dev_priv, power_well);
>+
>+	hsw_power_well_disable(dev_priv, power_well);
>+}
>+
> /*
>  * We should only use the power well if we explicitly asked the hardware to
>  * enable it, so check if it's enabled and also check if we've requested it to
>@@ -1071,7 +1218,7 @@
> 	spin_unlock_irq(&dev_priv->irq_lock);
> 
> 	/* make sure we're done processing display irqs */
>-	synchronize_irq(dev_priv->drm.irq);
>+	intel_synchronize_irq(dev_priv);
> 
> 	intel_power_sequencer_reset(dev_priv);
> 
>@@ -1575,12 +1722,15 @@
> static void print_power_domains(struct i915_power_domains *power_domains,
> 				const char *prefix, u64 mask)
> {
>+	struct drm_i915_private *i915 =
>+		container_of(power_domains, struct drm_i915_private,
>+			     power_domains);
> 	enum intel_display_power_domain domain;
> 
> 	DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
> 	for_each_power_domain(domain, mask)
> 		DRM_DEBUG_DRIVER("%s use_count %d\n",
>-				 intel_display_power_domain_str(domain),
>+				 intel_display_power_domain_str(i915, domain),
> 				 power_domains->domain_use_count[domain]);
> }
> 
>@@ -1750,7 +1900,7 @@
> {
> 	struct i915_power_domains *power_domains;
> 	struct i915_power_well *power_well;
>-	const char *name = intel_display_power_domain_str(domain);
>+	const char *name = intel_display_power_domain_str(dev_priv, domain);
> 
> 	power_domains = &dev_priv->power_domains;
> 
>@@ -2359,7 +2509,7 @@
> 	 */
> #define ICL_PW_2_POWER_DOMAINS (			\
> 	ICL_PW_3_POWER_DOMAINS |			\
>-	BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) |		\
>+	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) |		\
> 	BIT_ULL(POWER_DOMAIN_INIT))
> 	/*
> 	 * - KVMR (HW control)
>@@ -2368,6 +2518,7 @@
> 	ICL_PW_2_POWER_DOMAINS |			\
> 	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> 	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
>+	BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) |			\
> 	BIT_ULL(POWER_DOMAIN_INIT))
> 
> #define ICL_DDI_IO_A_POWER_DOMAINS (			\
>@@ -2405,6 +2556,93 @@
> #define ICL_AUX_TBT4_IO_POWER_DOMAINS (			\
> 	BIT_ULL(POWER_DOMAIN_AUX_TBT4))
> 
>+#define TGL_PW_5_POWER_DOMAINS (			\
>+	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
>+	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
>+	BIT_ULL(POWER_DOMAIN_INIT))
>+
>+#define TGL_PW_4_POWER_DOMAINS (			\
>+	TGL_PW_5_POWER_DOMAINS |			\
>+	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
>+	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
>+	BIT_ULL(POWER_DOMAIN_INIT))
>+
>+#define TGL_PW_3_POWER_DOMAINS (			\
>+	TGL_PW_4_POWER_DOMAINS |			\
>+	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
>+	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
>+	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
>+	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
>+	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) |	\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) |		\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) |	\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) |		\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) |	\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) |		\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) |	\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) |		\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) |	\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) |		\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) |	\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) |		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TC1) |		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TC2) |		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TC3) |		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TC4) |		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TC5) |		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TC6) |		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TBT1) |		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TBT2) |		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TBT3) |		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TBT4) |		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TBT5) |		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TBT6) |		\
>+	BIT_ULL(POWER_DOMAIN_VGA) |			\
>+	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
>+	BIT_ULL(POWER_DOMAIN_INIT))
>+
>+#define TGL_PW_2_POWER_DOMAINS (			\
>+	TGL_PW_3_POWER_DOMAINS |			\
>+	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) |	\
>+	BIT_ULL(POWER_DOMAIN_INIT))
>+
>+#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
>+	TGL_PW_2_POWER_DOMAINS |			\
>+	BIT_ULL(POWER_DOMAIN_MODESET) |			\
>+	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
>+	BIT_ULL(POWER_DOMAIN_INIT))
>+
>+#define TGL_DDI_IO_TC1_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
>+#define TGL_DDI_IO_TC2_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
>+#define TGL_DDI_IO_TC3_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
>+#define TGL_DDI_IO_TC4_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
>+#define TGL_DDI_IO_TC5_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
>+#define TGL_DDI_IO_TC6_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
>+
>+#define TGL_AUX_TC1_IO_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TC1))
>+#define TGL_AUX_TC2_IO_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TC2))
>+#define TGL_AUX_TC3_IO_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TC3))
>+#define TGL_AUX_TC4_IO_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TC4))
>+#define TGL_AUX_TC5_IO_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TC5))
>+#define TGL_AUX_TC6_IO_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TC6))
>+#define TGL_AUX_TBT5_IO_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TBT5))
>+#define TGL_AUX_TBT6_IO_POWER_DOMAINS (		\
>+	BIT_ULL(POWER_DOMAIN_AUX_TBT6))
>+
> static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> 	.sync_hw = i9xx_power_well_sync_hw_noop,
> 	.enable = i9xx_always_on_power_well_noop,
>@@ -3113,7 +3351,7 @@
> static const struct i915_power_well_ops icl_tc_phy_aux_power_well_ops = {
> 	.sync_hw = hsw_power_well_sync_hw,
> 	.enable = icl_tc_phy_aux_power_well_enable,
>-	.disable = hsw_power_well_disable,
>+	.disable = icl_tc_phy_aux_power_well_disable,
> 	.is_enabled = hsw_power_well_enabled,
> };
> 
>@@ -3362,6 +3600,335 @@
> 	},
> };
> 
>+static const struct i915_power_well_desc tgl_power_wells[] = {
>+	{
>+		.name = "always-on",
>+		.always_on = true,
>+		.domains = POWER_DOMAIN_MASK,
>+		.ops = &i9xx_always_on_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+	},
>+	{
>+		.name = "power well 1",
>+		/* Handled by the DMC firmware */
>+		.always_on = true,
>+		.domains = 0,
>+		.ops = &hsw_power_well_ops,
>+		.id = SKL_DISP_PW_1,
>+		{
>+			.hsw.regs = &hsw_power_well_regs,
>+			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
>+			.hsw.has_fuses = true,
>+		},
>+	},
>+	{
>+		.name = "DC off",
>+		.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
>+		.ops = &gen9_dc_off_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+	},
>+	{
>+		.name = "power well 2",
>+		.domains = TGL_PW_2_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = SKL_DISP_PW_2,
>+		{
>+			.hsw.regs = &hsw_power_well_regs,
>+			.hsw.idx = ICL_PW_CTL_IDX_PW_2,
>+			.hsw.has_fuses = true,
>+		},
>+	},
>+	{
>+		.name = "power well 3",
>+		.domains = TGL_PW_3_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &hsw_power_well_regs,
>+			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
>+			.hsw.irq_pipe_mask = BIT(PIPE_B),
>+			.hsw.has_vga = true,
>+			.hsw.has_fuses = true,
>+		},
>+	},
>+	{
>+		.name = "DDI A IO",
>+		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_ddi_power_well_regs,
>+			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
>+		}
>+	},
>+	{
>+		.name = "DDI B IO",
>+		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_ddi_power_well_regs,
>+			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
>+		}
>+	},
>+	{
>+		.name = "DDI C IO",
>+		.domains = ICL_DDI_IO_C_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_ddi_power_well_regs,
>+			.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
>+		}
>+	},
>+	{
>+		.name = "DDI TC1 IO",
>+		.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_ddi_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
>+		},
>+	},
>+	{
>+		.name = "DDI TC2 IO",
>+		.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_ddi_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
>+		},
>+	},
>+	{
>+		.name = "DDI TC3 IO",
>+		.domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_ddi_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
>+		},
>+	},
>+	{
>+		.name = "DDI TC4 IO",
>+		.domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_ddi_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
>+		},
>+	},
>+	{
>+		.name = "DDI TC5 IO",
>+		.domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_ddi_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
>+		},
>+	},
>+	{
>+		.name = "DDI TC6 IO",
>+		.domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_ddi_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
>+		},
>+	},
>+	{
>+		.name = "AUX A",
>+		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
>+		.ops = &icl_combo_phy_aux_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
>+		},
>+	},
>+	{
>+		.name = "AUX B",
>+		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
>+		.ops = &icl_combo_phy_aux_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
>+		},
>+	},
>+	{
>+		.name = "AUX C",
>+		.domains = ICL_AUX_C_IO_POWER_DOMAINS,
>+		.ops = &icl_combo_phy_aux_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
>+		},
>+	},
>+	{
>+		.name = "AUX TC1",
>+		.domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
>+		.ops = &icl_tc_phy_aux_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
>+			.hsw.is_tc_tbt = false,
>+		},
>+	},
>+	{
>+		.name = "AUX TC2",
>+		.domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
>+		.ops = &icl_tc_phy_aux_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
>+			.hsw.is_tc_tbt = false,
>+		},
>+	},
>+	{
>+		.name = "AUX TC3",
>+		.domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
>+		.ops = &icl_tc_phy_aux_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
>+			.hsw.is_tc_tbt = false,
>+		},
>+	},
>+	{
>+		.name = "AUX TC4",
>+		.domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
>+		.ops = &icl_tc_phy_aux_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
>+			.hsw.is_tc_tbt = false,
>+		},
>+	},
>+	{
>+		.name = "AUX TC5",
>+		.domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
>+		.ops = &icl_tc_phy_aux_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
>+			.hsw.is_tc_tbt = false,
>+		},
>+	},
>+	{
>+		.name = "AUX TC6",
>+		.domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
>+		.ops = &icl_tc_phy_aux_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
>+			.hsw.is_tc_tbt = false,
>+		},
>+	},
>+	{
>+		.name = "AUX TBT1",
>+		.domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
>+			.hsw.is_tc_tbt = true,
>+		},
>+	},
>+	{
>+		.name = "AUX TBT2",
>+		.domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
>+			.hsw.is_tc_tbt = true,
>+		},
>+	},
>+	{
>+		.name = "AUX TBT3",
>+		.domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
>+			.hsw.is_tc_tbt = true,
>+		},
>+	},
>+	{
>+		.name = "AUX TBT4",
>+		.domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
>+			.hsw.is_tc_tbt = true,
>+		},
>+	},
>+	{
>+		.name = "AUX TBT5",
>+		.domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
>+			.hsw.is_tc_tbt = true,
>+		},
>+	},
>+	{
>+		.name = "AUX TBT6",
>+		.domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &icl_aux_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
>+			.hsw.is_tc_tbt = true,
>+		},
>+	},
>+	{
>+		.name = "power well 4",
>+		.domains = TGL_PW_4_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &hsw_power_well_regs,
>+			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
>+			.hsw.has_fuses = true,
>+			.hsw.irq_pipe_mask = BIT(PIPE_C),
>+		}
>+	},
>+	{
>+		.name = "power well 5",
>+		.domains = TGL_PW_5_POWER_DOMAINS,
>+		.ops = &hsw_power_well_ops,
>+		.id = DISP_PW_ID_NONE,
>+		{
>+			.hsw.regs = &hsw_power_well_regs,
>+			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
>+			.hsw.has_fuses = true,
>+			.hsw.irq_pipe_mask = BIT(PIPE_D),
>+		},
>+	},
>+};
>+
> static int
> sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
> 				   int disable_power_well)
>@@ -3489,7 +4056,9 @@
> 	 * The enabling order will be from lower to higher indexed wells,
> 	 * the disabling order is reversed.
> 	 */
>-	if (IS_GEN(dev_priv, 11)) {
>+	if (IS_GEN(dev_priv, 12)) {
>+		err = set_power_wells(power_domains, tgl_power_wells);
>+	} else if (IS_GEN(dev_priv, 11)) {
> 		err = set_power_wells(power_domains, icl_power_wells);
> 	} else if (IS_CANNONLAKE(dev_priv)) {
> 		err = set_power_wells(power_domains, cnl_power_wells);
>@@ -4337,7 +4906,7 @@
>  *
>  * It will return with power domains disabled (to be enabled later by
>  * intel_power_domains_enable()) and must be paired with
>- * intel_power_domains_fini_hw().
>+ * intel_power_domains_driver_remove().
>  */
> void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
> {
>@@ -4389,7 +4958,7 @@
> }
> 
> /**
>- * intel_power_domains_fini_hw - deinitialize hw power domain state
>+ * intel_power_domains_driver_remove - deinitialize hw power domain state
>  * @i915: i915 device instance
>  *
>  * De-initializes the display power domain HW state. It also ensures that the
>@@ -4399,7 +4968,7 @@
>  * intel_power_domains_disable()) and must be paired with
>  * intel_power_domains_init_hw().
>  */
>-void intel_power_domains_fini_hw(struct drm_i915_private *i915)
>+void intel_power_domains_driver_remove(struct drm_i915_private *i915)
> {
> 	intel_wakeref_t wakeref __maybe_unused =
> 		fetch_and_zero(&i915->power_domains.wakeref);
>@@ -4553,7 +5122,8 @@
> 
> 		for_each_power_domain(domain, power_well->desc->domains)
> 			DRM_DEBUG_DRIVER("  %-23s %d\n",
>-					 intel_display_power_domain_str(domain),
>+					 intel_display_power_domain_str(i915,
>+									domain),
> 					 power_domains->domain_use_count[domain]);
> 	}
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_display_power.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_display_power.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_display_power.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_display_power.h	2019-08-31 15:01:12.017736182 -0500
>@@ -18,28 +18,47 @@
> 	POWER_DOMAIN_PIPE_A,
> 	POWER_DOMAIN_PIPE_B,
> 	POWER_DOMAIN_PIPE_C,
>+	POWER_DOMAIN_PIPE_D,
> 	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
> 	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
> 	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
>+	POWER_DOMAIN_PIPE_D_PANEL_FITTER,
> 	POWER_DOMAIN_TRANSCODER_A,
> 	POWER_DOMAIN_TRANSCODER_B,
> 	POWER_DOMAIN_TRANSCODER_C,
>+	POWER_DOMAIN_TRANSCODER_D,
> 	POWER_DOMAIN_TRANSCODER_EDP,
>-	POWER_DOMAIN_TRANSCODER_EDP_VDSC,
>+	/* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
>+	POWER_DOMAIN_TRANSCODER_VDSC_PW2,
> 	POWER_DOMAIN_TRANSCODER_DSI_A,
> 	POWER_DOMAIN_TRANSCODER_DSI_C,
> 	POWER_DOMAIN_PORT_DDI_A_LANES,
> 	POWER_DOMAIN_PORT_DDI_B_LANES,
> 	POWER_DOMAIN_PORT_DDI_C_LANES,
> 	POWER_DOMAIN_PORT_DDI_D_LANES,
>+	POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES,
> 	POWER_DOMAIN_PORT_DDI_E_LANES,
>+	POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES,
> 	POWER_DOMAIN_PORT_DDI_F_LANES,
>+	POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES,
>+	POWER_DOMAIN_PORT_DDI_TC4_LANES,
>+	POWER_DOMAIN_PORT_DDI_TC5_LANES,
>+	POWER_DOMAIN_PORT_DDI_TC6_LANES,
> 	POWER_DOMAIN_PORT_DDI_A_IO,
> 	POWER_DOMAIN_PORT_DDI_B_IO,
> 	POWER_DOMAIN_PORT_DDI_C_IO,
> 	POWER_DOMAIN_PORT_DDI_D_IO,
>+	POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
> 	POWER_DOMAIN_PORT_DDI_E_IO,
>+	POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
> 	POWER_DOMAIN_PORT_DDI_F_IO,
>+	POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
>+	POWER_DOMAIN_PORT_DDI_G_IO,
>+	POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
>+	POWER_DOMAIN_PORT_DDI_H_IO,
>+	POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
>+	POWER_DOMAIN_PORT_DDI_I_IO,
>+	POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
> 	POWER_DOMAIN_PORT_DSI,
> 	POWER_DOMAIN_PORT_CRT,
> 	POWER_DOMAIN_PORT_OTHER,
>@@ -49,16 +68,25 @@
> 	POWER_DOMAIN_AUX_B,
> 	POWER_DOMAIN_AUX_C,
> 	POWER_DOMAIN_AUX_D,
>+	POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
> 	POWER_DOMAIN_AUX_E,
>+	POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
> 	POWER_DOMAIN_AUX_F,
>+	POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
>+	POWER_DOMAIN_AUX_TC4,
>+	POWER_DOMAIN_AUX_TC5,
>+	POWER_DOMAIN_AUX_TC6,
> 	POWER_DOMAIN_AUX_IO_A,
> 	POWER_DOMAIN_AUX_TBT1,
> 	POWER_DOMAIN_AUX_TBT2,
> 	POWER_DOMAIN_AUX_TBT3,
> 	POWER_DOMAIN_AUX_TBT4,
>+	POWER_DOMAIN_AUX_TBT5,
>+	POWER_DOMAIN_AUX_TBT6,
> 	POWER_DOMAIN_GMBUS,
> 	POWER_DOMAIN_MODESET,
> 	POWER_DOMAIN_GT_IRQ,
>+	POWER_DOMAIN_DPLL_DC_OFF,
> 	POWER_DOMAIN_INIT,
> 
> 	POWER_DOMAIN_NUM,
>@@ -213,7 +241,7 @@
> int intel_power_domains_init(struct drm_i915_private *dev_priv);
> void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
> void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
>-void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
>+void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
> void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
> void icl_display_core_uninit(struct drm_i915_private *dev_priv);
> void intel_power_domains_enable(struct drm_i915_private *dev_priv);
>@@ -227,7 +255,8 @@
> void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
> 
> const char *
>-intel_display_power_domain_str(enum intel_display_power_domain domain);
>+intel_display_power_domain_str(struct drm_i915_private *i915,
>+			       enum intel_display_power_domain domain);
> 
> bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
> 				    enum intel_display_power_domain domain);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c	2019-08-31 15:01:12.018736182 -0500
>@@ -264,8 +264,11 @@
> int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
> {
> 	struct intel_panel *panel = &intel_connector->panel;
>+	struct drm_i915_private *dev_priv = to_i915(intel_connector->base.dev);
> 
>-	if (!i915_modparams.enable_dpcd_backlight)
>+	if (i915_modparams.enable_dpcd_backlight == 0 ||
>+	    (i915_modparams.enable_dpcd_backlight == -1 &&
>+	    dev_priv->vbt.backlight.type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE))
> 		return -ENODEV;
> 
> 	if (!intel_dp_aux_display_control_capable(intel_connector))
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dp.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dp.c	2019-08-31 15:01:12.018736182 -0500
>@@ -62,6 +62,7 @@
> #include "intel_panel.h"
> #include "intel_psr.h"
> #include "intel_sideband.h"
>+#include "intel_tc.h"
> #include "intel_vdsc.h"
> 
> #define DP_DPRX_ESI_LEN 14
>@@ -211,47 +212,13 @@
> 	return intel_dp->common_rates[intel_dp->num_common_rates - 1];
> }
> 
>-static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
>-{
>-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>-	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>-	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
>-	intel_wakeref_t wakeref;
>-	u32 lane_info;
>-
>-	if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
>-		return 4;
>-
>-	lane_info = 0;
>-	with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
>-		lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
>-			     DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
>-				DP_LANE_ASSIGNMENT_SHIFT(tc_port);
>-
>-	switch (lane_info) {
>-	default:
>-		MISSING_CASE(lane_info);
>-		/* fall through */
>-	case 1:
>-	case 2:
>-	case 4:
>-	case 8:
>-		return 1;
>-	case 3:
>-	case 12:
>-		return 2;
>-	case 15:
>-		return 4;
>-	}
>-}
>-
> /* Theoretical max between source and sink */
> static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
> {
> 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> 	int source_max = intel_dig_port->max_lanes;
> 	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
>-	int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
>+	int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
> 
> 	return min3(source_max, sink_max, fia_max);
> }
>@@ -330,9 +297,9 @@
> {
> 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>-	enum port port = dig_port->base.port;
>+	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
> 
>-	if (intel_port_is_combophy(dev_priv, port) &&
>+	if (intel_phy_is_combo(dev_priv, phy) &&
> 	    !IS_ELKHARTLAKE(dev_priv) &&
> 	    !intel_dp_is_edp(intel_dp))
> 		return 540000;
>@@ -1209,7 +1176,7 @@
> 	      DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
> 	      DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
> 
>-	if (intel_dig_port->tc_type == TC_PORT_TBT)
>+	if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
> 		ret |= DP_AUX_CH_CTL_TBT_IO;
> 
> 	return ret;
>@@ -1225,6 +1192,8 @@
> 	struct drm_i915_private *i915 =
> 			to_i915(intel_dig_port->base.base.dev);
> 	struct intel_uncore *uncore = &i915->uncore;
>+	enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
>+	bool is_tc_port = intel_phy_is_tc(i915, phy);
> 	i915_reg_t ch_ctl, ch_data[5];
> 	u32 aux_clock_divider;
> 	enum intel_display_power_domain aux_domain =
>@@ -1240,6 +1209,9 @@
> 	for (i = 0; i < ARRAY_SIZE(ch_data); i++)
> 		ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
> 
>+	if (is_tc_port)
>+		intel_tc_port_lock(intel_dig_port);
>+
> 	aux_wakeref = intel_display_power_get(i915, aux_domain);
> 	pps_wakeref = pps_lock(intel_dp);
> 
>@@ -1392,6 +1364,9 @@
> 	pps_unlock(intel_dp, pps_wakeref);
> 	intel_display_power_put_async(i915, aux_domain, aux_wakeref);
> 
>+	if (is_tc_port)
>+		intel_tc_port_unlock(intel_dig_port);
>+
> 	return ret;
> }
> 
>@@ -1879,8 +1854,10 @@
> 	int mode_rate, link_clock, link_avail;
> 
> 	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
>+		int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
>+
> 		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
>-						   bpp);
>+						   output_bpp);
> 
> 		for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
> 			for (lane_count = limits->min_lane_count;
>@@ -4244,8 +4221,14 @@
> 	if (!intel_dp_read_dpcd(intel_dp))
> 		return false;
> 
>-	/* Don't clobber cached eDP rates. */
>+	/*
>+	 * Don't clobber cached eDP rates. Also skip re-reading
>+	 * the OUI/ID since we know it won't change.
>+	 */
> 	if (!intel_dp_is_edp(intel_dp)) {
>+		drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
>+				 drm_dp_is_branch(intel_dp->dpcd));
>+
> 		intel_dp_set_sink_rates(intel_dp);
> 		intel_dp_set_common_rates(intel_dp);
> 	}
>@@ -4254,7 +4237,8 @@
> 	 * Some eDP panels do not set a valid value for sink count, that is why
> 	 * it don't care about read it here and in intel_edp_init_dpcd().
> 	 */
>-	if (!intel_dp_is_edp(intel_dp)) {
>+	if (!intel_dp_is_edp(intel_dp) &&
>+	    !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) {
> 		u8 count;
> 		ssize_t r;
> 
>@@ -4879,14 +4863,16 @@
>  * retrain the link to get a picture. That's in case no
>  * userspace component reacted to intermittent HPD dip.
>  */
>-static bool intel_dp_hotplug(struct intel_encoder *encoder,
>-			     struct intel_connector *connector)
>+static enum intel_hotplug_state
>+intel_dp_hotplug(struct intel_encoder *encoder,
>+		 struct intel_connector *connector,
>+		 bool irq_received)
> {
> 	struct drm_modeset_acquire_ctx ctx;
>-	bool changed;
>+	enum intel_hotplug_state state;
> 	int ret;
> 
>-	changed = intel_encoder_hotplug(encoder, connector);
>+	state = intel_encoder_hotplug(encoder, connector, irq_received);
> 
> 	drm_modeset_acquire_init(&ctx, 0);
> 
>@@ -4905,7 +4891,14 @@
> 	drm_modeset_acquire_fini(&ctx);
> 	WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
> 
>-	return changed;
>+	/*
>+	 * Keeping it consistent with intel_ddi_hotplug() and
>+	 * intel_hdmi_hotplug().
>+	 */
>+	if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
>+		state = INTEL_HOTPLUG_RETRY;
>+
>+	return state;
> }
> 
> static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
>@@ -5233,204 +5226,16 @@
> 	return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
> }
> 
>-static const char *tc_type_name(enum tc_port_type type)
>-{
>-	static const char * const names[] = {
>-		[TC_PORT_UNKNOWN] = "unknown",
>-		[TC_PORT_LEGACY] = "legacy",
>-		[TC_PORT_TYPEC] = "typec",
>-		[TC_PORT_TBT] = "tbt",
>-	};
>-
>-	if (WARN_ON(type >= ARRAY_SIZE(names)))
>-		type = TC_PORT_UNKNOWN;
>-
>-	return names[type];
>-}
>-
>-static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
>-				    struct intel_digital_port *intel_dig_port,
>-				    bool is_legacy, bool is_typec, bool is_tbt)
>-{
>-	enum port port = intel_dig_port->base.port;
>-	enum tc_port_type old_type = intel_dig_port->tc_type;
>-
>-	WARN_ON(is_legacy + is_typec + is_tbt != 1);
>-
>-	if (is_legacy)
>-		intel_dig_port->tc_type = TC_PORT_LEGACY;
>-	else if (is_typec)
>-		intel_dig_port->tc_type = TC_PORT_TYPEC;
>-	else if (is_tbt)
>-		intel_dig_port->tc_type = TC_PORT_TBT;
>-	else
>-		return;
>-
>-	/* Types are not supposed to be changed at runtime. */
>-	WARN_ON(old_type != TC_PORT_UNKNOWN &&
>-		old_type != intel_dig_port->tc_type);
>-
>-	if (old_type != intel_dig_port->tc_type)
>-		DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
>-			      tc_type_name(intel_dig_port->tc_type));
>-}
>-
>-/*
>- * This function implements the first part of the Connect Flow described by our
>- * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
>- * lanes, EDID, etc) is done as needed in the typical places.
>- *
>- * Unlike the other ports, type-C ports are not available to use as soon as we
>- * get a hotplug. The type-C PHYs can be shared between multiple controllers:
>- * display, USB, etc. As a result, handshaking through FIA is required around
>- * connect and disconnect to cleanly transfer ownership with the controller and
>- * set the type-C power state.
>- *
>- * We could opt to only do the connect flow when we actually try to use the AUX
>- * channels or do a modeset, then immediately run the disconnect flow after
>- * usage, but there are some implications on this for a dynamic environment:
>- * things may go away or change behind our backs. So for now our driver is
>- * always trying to acquire ownership of the controller as soon as it gets an
>- * interrupt (or polls state and sees a port is connected) and only gives it
>- * back when it sees a disconnect. Implementation of a more fine-grained model
>- * will require a lot of coordination with user space and thorough testing for
>- * the extra possible cases.
>- */
>-static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
>-			       struct intel_digital_port *dig_port)
>-{
>-	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
>-	u32 val;
>-
>-	if (dig_port->tc_type != TC_PORT_LEGACY &&
>-	    dig_port->tc_type != TC_PORT_TYPEC)
>-		return true;
>-
>-	val = I915_READ(PORT_TX_DFLEXDPPMS);
>-	if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
>-		DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
>-		WARN_ON(dig_port->tc_legacy_port);
>-		return false;
>-	}
>-
>-	/*
>-	 * This function may be called many times in a row without an HPD event
>-	 * in between, so try to avoid the write when we can.
>-	 */
>-	val = I915_READ(PORT_TX_DFLEXDPCSSS);
>-	if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
>-		val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
>-		I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
>-	}
>-
>-	/*
>-	 * Now we have to re-check the live state, in case the port recently
>-	 * became disconnected. Not necessary for legacy mode.
>-	 */
>-	if (dig_port->tc_type == TC_PORT_TYPEC &&
>-	    !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
>-		DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
>-		icl_tc_phy_disconnect(dev_priv, dig_port);
>-		return false;
>-	}
>-
>-	return true;
>-}
>-
>-/*
>- * See the comment at the connect function. This implements the Disconnect
>- * Flow.
>- */
>-void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
>-			   struct intel_digital_port *dig_port)
>-{
>-	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
>-
>-	if (dig_port->tc_type == TC_PORT_UNKNOWN)
>-		return;
>-
>-	/*
>-	 * TBT disconnection flow is read the live status, what was done in
>-	 * caller.
>-	 */
>-	if (dig_port->tc_type == TC_PORT_TYPEC ||
>-	    dig_port->tc_type == TC_PORT_LEGACY) {
>-		u32 val;
>-
>-		val = I915_READ(PORT_TX_DFLEXDPCSSS);
>-		val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
>-		I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
>-	}
>-
>-	DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
>-		      port_name(dig_port->base.port),
>-		      tc_type_name(dig_port->tc_type));
>-
>-	dig_port->tc_type = TC_PORT_UNKNOWN;
>-}
>-
>-/*
>- * The type-C ports are different because even when they are connected, they may
>- * not be available/usable by the graphics driver: see the comment on
>- * icl_tc_phy_connect(). So in our driver instead of adding the additional
>- * concept of "usable" and make everything check for "connected and usable" we
>- * define a port as "connected" when it is not only connected, but also when it
>- * is usable by the rest of the driver. That maintains the old assumption that
>- * connected ports are usable, and avoids exposing to the users objects they
>- * can't really use.
>- */
>-static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
>-				  struct intel_digital_port *intel_dig_port)
>-{
>-	enum port port = intel_dig_port->base.port;
>-	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
>-	bool is_legacy, is_typec, is_tbt;
>-	u32 dpsp;
>-
>-	/*
>-	 * Complain if we got a legacy port HPD, but VBT didn't mark the port as
>-	 * legacy. Treat the port as legacy from now on.
>-	 */
>-	if (!intel_dig_port->tc_legacy_port &&
>-	    I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port)) {
>-		DRM_ERROR("VBT incorrectly claims port %c is not TypeC legacy\n",
>-			  port_name(port));
>-		intel_dig_port->tc_legacy_port = true;
>-	}
>-	is_legacy = intel_dig_port->tc_legacy_port;
>-
>-	/*
>-	 * The spec says we shouldn't be using the ISR bits for detecting
>-	 * between TC and TBT. We should use DFLEXDPSP.
>-	 */
>-	dpsp = I915_READ(PORT_TX_DFLEXDPSP);
>-	is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
>-	is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
>-
>-	if (!is_legacy && !is_typec && !is_tbt) {
>-		icl_tc_phy_disconnect(dev_priv, intel_dig_port);
>-
>-		return false;
>-	}
>-
>-	icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
>-				is_tbt);
>-
>-	if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
>-		return false;
>-
>-	return true;
>-}
>-
> static bool icl_digital_port_connected(struct intel_encoder *encoder)
> {
> 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> 
>-	if (intel_port_is_combophy(dev_priv, encoder->port))
>+	if (intel_phy_is_combo(dev_priv, phy))
> 		return icl_combo_port_connected(dev_priv, dig_port);
>-	else if (intel_port_is_tc(dev_priv, encoder->port))
>-		return icl_tc_port_connected(dev_priv, dig_port);
>+	else if (intel_phy_is_tc(dev_priv, phy))
>+		return intel_tc_port_connected(dig_port);
> 	else
> 		MISSING_CASE(encoder->hpd_pin);
> 
>@@ -5588,9 +5393,6 @@
> 	if (INTEL_GEN(dev_priv) >= 11)
> 		intel_dp_get_dsc_sink_cap(intel_dp);
> 
>-	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
>-			 drm_dp_is_branch(intel_dp->dpcd));
>-
> 	intel_dp_configure_mst(intel_dp);
> 
> 	if (intel_dp->is_mst) {
>@@ -6835,8 +6637,6 @@
> 				    const struct intel_crtc_state *crtc_state,
> 				    int refresh_rate)
> {
>-	struct intel_encoder *encoder;
>-	struct intel_digital_port *dig_port = NULL;
> 	struct intel_dp *intel_dp = dev_priv->drrs.dp;
> 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> 	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
>@@ -6851,9 +6651,6 @@
> 		return;
> 	}
> 
>-	dig_port = dp_to_dig_port(intel_dp);
>-	encoder = &dig_port->base;
>-
> 	if (!intel_crtc) {
> 		DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
> 		return;
>@@ -7333,6 +7130,7 @@
> 	struct drm_device *dev = intel_encoder->base.dev;
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 	enum port port = intel_encoder->port;
>+	enum phy phy = intel_port_to_phy(dev_priv, port);
> 	int type;
> 
> 	/* Initialize the work for modeset in case of link train failure */
>@@ -7359,7 +7157,7 @@
> 		 * Currently we don't support eDP on TypeC ports, although in
> 		 * theory it could work on TypeC legacy ports.
> 		 */
>-		WARN_ON(intel_port_is_tc(dev_priv, port));
>+		WARN_ON(intel_phy_is_tc(dev_priv, phy));
> 		type = DRM_MODE_CONNECTOR_eDP;
> 	} else {
> 		type = DRM_MODE_CONNECTOR_DisplayPort;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dp.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dp.h	2019-08-31 15:01:12.018736182 -0500
>@@ -112,8 +112,6 @@
> int intel_dp_link_required(int pixel_clock, int bpp);
> int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
> bool intel_digital_port_connected(struct intel_encoder *encoder);
>-void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
>-			   struct intel_digital_port *dig_port);
> 
> static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
> {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dpll_mgr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dpll_mgr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dpll_mgr.c	2019-08-31 15:01:12.019736182 -0500
>@@ -36,9 +36,10 @@
>  * This file provides an abstraction over display PLLs. The function
>  * intel_shared_dpll_init() initializes the PLLs for the given platform.  The
>  * users of a PLL are tracked and that tracking is integrated with the atomic
>- * modest interface. During an atomic operation, a PLL can be requested for a
>- * given CRTC and encoder configuration by calling intel_get_shared_dpll() and
>- * a previously used PLL can be released with intel_release_shared_dpll().
>+ * modset interface. During an atomic operation, required PLLs can be reserved
>+ * for a given CRTC and encoder configuration by calling
>+ * intel_reserve_shared_dplls() and previously reserved PLLs can be released
>+ * with intel_release_shared_dplls().
>  * Changes to the users are first staged in the atomic state, and then made
>  * effective by calling intel_shared_dpll_swap_state() during the atomic
>  * commit phase.
>@@ -243,17 +244,18 @@
> }
> 
> static struct intel_shared_dpll *
>-intel_find_shared_dpll(struct intel_crtc_state *crtc_state,
>+intel_find_shared_dpll(struct intel_atomic_state *state,
>+		       const struct intel_crtc *crtc,
>+		       const struct intel_dpll_hw_state *pll_state,
> 		       enum intel_dpll_id range_min,
> 		       enum intel_dpll_id range_max)
> {
>-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 	struct intel_shared_dpll *pll, *unused_pll = NULL;
> 	struct intel_shared_dpll_state *shared_dpll;
> 	enum intel_dpll_id i;
> 
>-	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
>+	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
> 
> 	for (i = range_min; i <= range_max; i++) {
> 		pll = &dev_priv->shared_dplls[i];
>@@ -265,9 +267,9 @@
> 			continue;
> 		}
> 
>-		if (memcmp(&crtc_state->dpll_hw_state,
>+		if (memcmp(pll_state,
> 			   &shared_dpll[i].hw_state,
>-			   sizeof(crtc_state->dpll_hw_state)) == 0) {
>+			   sizeof(*pll_state)) == 0) {
> 			DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
> 				      crtc->base.base.id, crtc->base.name,
> 				      pll->info->name,
>@@ -289,26 +291,51 @@
> }
> 
> static void
>-intel_reference_shared_dpll(struct intel_shared_dpll *pll,
>-			    struct intel_crtc_state *crtc_state)
>+intel_reference_shared_dpll(struct intel_atomic_state *state,
>+			    const struct intel_crtc *crtc,
>+			    const struct intel_shared_dpll *pll,
>+			    const struct intel_dpll_hw_state *pll_state)
> {
> 	struct intel_shared_dpll_state *shared_dpll;
>-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> 	const enum intel_dpll_id id = pll->info->id;
> 
>-	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
>+	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
> 
> 	if (shared_dpll[id].crtc_mask == 0)
>-		shared_dpll[id].hw_state =
>-			crtc_state->dpll_hw_state;
>+		shared_dpll[id].hw_state = *pll_state;
> 
>-	crtc_state->shared_dpll = pll;
> 	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,
> 			 pipe_name(crtc->pipe));
> 
> 	shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
> }
> 
>+static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
>+					  const struct intel_crtc *crtc,
>+					  const struct intel_shared_dpll *pll)
>+{
>+	struct intel_shared_dpll_state *shared_dpll;
>+
>+	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
>+	shared_dpll[pll->info->id].crtc_mask &= ~(1 << crtc->pipe);
>+}
>+
>+static void intel_put_dpll(struct intel_atomic_state *state,
>+			   struct intel_crtc *crtc)
>+{
>+	const struct intel_crtc_state *old_crtc_state =
>+		intel_atomic_get_old_crtc_state(state, crtc);
>+	struct intel_crtc_state *new_crtc_state =
>+		intel_atomic_get_new_crtc_state(state, crtc);
>+
>+	new_crtc_state->shared_dpll = NULL;
>+
>+	if (!old_crtc_state->shared_dpll)
>+		return;
>+
>+	intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
>+}
>+
> /**
>  * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
>  * @state: atomic state
>@@ -320,25 +347,20 @@
>  * i.e. it also puts the current state into @state, even though there is no
>  * need for that at this moment.
>  */
>-void intel_shared_dpll_swap_state(struct drm_atomic_state *state)
>+void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
> {
>-	struct drm_i915_private *dev_priv = to_i915(state->dev);
>-	struct intel_shared_dpll_state *shared_dpll;
>-	struct intel_shared_dpll *pll;
>+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>+	struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
> 	enum intel_dpll_id i;
> 
>-	if (!to_intel_atomic_state(state)->dpll_set)
>+	if (!state->dpll_set)
> 		return;
> 
>-	shared_dpll = to_intel_atomic_state(state)->shared_dpll;
> 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
>-		struct intel_shared_dpll_state tmp;
>-
>-		pll = &dev_priv->shared_dplls[i];
>+		struct intel_shared_dpll *pll =
>+			&dev_priv->shared_dplls[i];
> 
>-		tmp = pll->state;
>-		pll->state = shared_dpll[i];
>-		shared_dpll[i] = tmp;
>+		swap(pll->state, shared_dpll[i]);
> 	}
> }
> 
>@@ -421,11 +443,12 @@
> 	udelay(200);
> }
> 
>-static struct intel_shared_dpll *
>-ibx_get_dpll(struct intel_crtc_state *crtc_state,
>-	     struct intel_encoder *encoder)
>+static bool ibx_get_dpll(struct intel_atomic_state *state,
>+			 struct intel_crtc *crtc,
>+			 struct intel_encoder *encoder)
> {
>-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>+	struct intel_crtc_state *crtc_state =
>+		intel_atomic_get_new_crtc_state(state, crtc);
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 	struct intel_shared_dpll *pll;
> 	enum intel_dpll_id i;
>@@ -439,18 +462,22 @@
> 			      crtc->base.base.id, crtc->base.name,
> 			      pll->info->name);
> 	} else {
>-		pll = intel_find_shared_dpll(crtc_state,
>+		pll = intel_find_shared_dpll(state, crtc,
>+					     &crtc_state->dpll_hw_state,
> 					     DPLL_ID_PCH_PLL_A,
> 					     DPLL_ID_PCH_PLL_B);
> 	}
> 
> 	if (!pll)
>-		return NULL;
>+		return false;
> 
> 	/* reference the pll */
>-	intel_reference_shared_dpll(pll, crtc_state);
>+	intel_reference_shared_dpll(state, crtc,
>+				    pll, &crtc_state->dpll_hw_state);
> 
>-	return pll;
>+	crtc_state->shared_dpll = pll;
>+
>+	return true;
> }
> 
> static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
>@@ -767,8 +794,12 @@
> 	*r2_out = best.r2;
> }
> 
>-static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(struct intel_crtc_state *crtc_state)
>+static struct intel_shared_dpll *
>+hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
>+		      struct intel_crtc *crtc)
> {
>+	struct intel_crtc_state *crtc_state =
>+		intel_atomic_get_new_crtc_state(state, crtc);
> 	struct intel_shared_dpll *pll;
> 	u32 val;
> 	unsigned int p, n2, r2;
>@@ -781,7 +812,8 @@
> 
> 	crtc_state->dpll_hw_state.wrpll = val;
> 
>-	pll = intel_find_shared_dpll(crtc_state,
>+	pll = intel_find_shared_dpll(state, crtc,
>+				     &crtc_state->dpll_hw_state,
> 				     DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
> 
> 	if (!pll)
>@@ -821,38 +853,44 @@
> 	return pll;
> }
> 
>-static struct intel_shared_dpll *
>-hsw_get_dpll(struct intel_crtc_state *crtc_state,
>-	     struct intel_encoder *encoder)
>+static bool hsw_get_dpll(struct intel_atomic_state *state,
>+			 struct intel_crtc *crtc,
>+			 struct intel_encoder *encoder)
> {
>+	struct intel_crtc_state *crtc_state =
>+		intel_atomic_get_new_crtc_state(state, crtc);
> 	struct intel_shared_dpll *pll;
> 
> 	memset(&crtc_state->dpll_hw_state, 0,
> 	       sizeof(crtc_state->dpll_hw_state));
> 
> 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
>-		pll = hsw_ddi_hdmi_get_dpll(crtc_state);
>+		pll = hsw_ddi_hdmi_get_dpll(state, crtc);
> 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
> 		pll = hsw_ddi_dp_get_dpll(crtc_state);
> 	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
> 		if (WARN_ON(crtc_state->port_clock / 2 != 135000))
>-			return NULL;
>+			return false;
> 
> 		crtc_state->dpll_hw_state.spll =
> 			SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
> 
>-		pll = intel_find_shared_dpll(crtc_state,
>+		pll = intel_find_shared_dpll(state, crtc,
>+					     &crtc_state->dpll_hw_state,
> 					     DPLL_ID_SPLL, DPLL_ID_SPLL);
> 	} else {
>-		return NULL;
>+		return false;
> 	}
> 
> 	if (!pll)
>-		return NULL;
>+		return false;
> 
>-	intel_reference_shared_dpll(pll, crtc_state);
>+	intel_reference_shared_dpll(state, crtc,
>+				    pll, &crtc_state->dpll_hw_state);
> 
>-	return pll;
>+	crtc_state->shared_dpll = pll;
>+
>+	return true;
> }
> 
> static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
>@@ -1385,10 +1423,12 @@
> 	return true;
> }
> 
>-static struct intel_shared_dpll *
>-skl_get_dpll(struct intel_crtc_state *crtc_state,
>-	     struct intel_encoder *encoder)
>+static bool skl_get_dpll(struct intel_atomic_state *state,
>+			 struct intel_crtc *crtc,
>+			 struct intel_encoder *encoder)
> {
>+	struct intel_crtc_state *crtc_state =
>+		intel_atomic_get_new_crtc_state(state, crtc);
> 	struct intel_shared_dpll *pll;
> 	bool bret;
> 
>@@ -1396,32 +1436,37 @@
> 		bret = skl_ddi_hdmi_pll_dividers(crtc_state);
> 		if (!bret) {
> 			DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
>-			return NULL;
>+			return false;
> 		}
> 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
> 		bret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
> 		if (!bret) {
> 			DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
>-			return NULL;
>+			return false;
> 		}
> 	} else {
>-		return NULL;
>+		return false;
> 	}
> 
> 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
>-		pll = intel_find_shared_dpll(crtc_state,
>+		pll = intel_find_shared_dpll(state, crtc,
>+					     &crtc_state->dpll_hw_state,
> 					     DPLL_ID_SKL_DPLL0,
> 					     DPLL_ID_SKL_DPLL0);
> 	else
>-		pll = intel_find_shared_dpll(crtc_state,
>+		pll = intel_find_shared_dpll(state, crtc,
>+					     &crtc_state->dpll_hw_state,
> 					     DPLL_ID_SKL_DPLL1,
> 					     DPLL_ID_SKL_DPLL3);
> 	if (!pll)
>-		return NULL;
>+		return false;
> 
>-	intel_reference_shared_dpll(pll, crtc_state);
>+	intel_reference_shared_dpll(state, crtc,
>+				    pll, &crtc_state->dpll_hw_state);
> 
>-	return pll;
>+	crtc_state->shared_dpll = pll;
>+
>+	return true;
> }
> 
> static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
>@@ -1827,22 +1872,23 @@
> 	return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
> }
> 
>-static struct intel_shared_dpll *
>-bxt_get_dpll(struct intel_crtc_state *crtc_state,
>-	     struct intel_encoder *encoder)
>+static bool bxt_get_dpll(struct intel_atomic_state *state,
>+			 struct intel_crtc *crtc,
>+			 struct intel_encoder *encoder)
> {
>-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>+	struct intel_crtc_state *crtc_state =
>+		intel_atomic_get_new_crtc_state(state, crtc);
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 	struct intel_shared_dpll *pll;
> 	enum intel_dpll_id id;
> 
> 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> 	    !bxt_ddi_hdmi_set_dpll_hw_state(crtc_state))
>-		return NULL;
>+		return false;
> 
> 	if (intel_crtc_has_dp_encoder(crtc_state) &&
> 	    !bxt_ddi_dp_set_dpll_hw_state(crtc_state))
>-		return NULL;
>+		return false;
> 
> 	/* 1:1 mapping between ports and PLLs */
> 	id = (enum intel_dpll_id) encoder->port;
>@@ -1851,9 +1897,12 @@
> 	DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
> 		      crtc->base.base.id, crtc->base.name, pll->info->name);
> 
>-	intel_reference_shared_dpll(pll, crtc_state);
>+	intel_reference_shared_dpll(state, crtc,
>+				    pll, &crtc_state->dpll_hw_state);
> 
>-	return pll;
>+	crtc_state->shared_dpll = pll;
>+
>+	return true;
> }
> 
> static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
>@@ -1884,9 +1933,14 @@
> struct intel_dpll_mgr {
> 	const struct dpll_info *dpll_info;
> 
>-	struct intel_shared_dpll *(*get_dpll)(struct intel_crtc_state *crtc_state,
>-					      struct intel_encoder *encoder);
>-
>+	bool (*get_dplls)(struct intel_atomic_state *state,
>+			  struct intel_crtc *crtc,
>+			  struct intel_encoder *encoder);
>+	void (*put_dplls)(struct intel_atomic_state *state,
>+			  struct intel_crtc *crtc);
>+	void (*update_active_dpll)(struct intel_atomic_state *state,
>+				   struct intel_crtc *crtc,
>+				   struct intel_encoder *encoder);
> 	void (*dump_hw_state)(struct drm_i915_private *dev_priv,
> 			      const struct intel_dpll_hw_state *hw_state);
> };
>@@ -1899,7 +1953,8 @@
> 
> static const struct intel_dpll_mgr pch_pll_mgr = {
> 	.dpll_info = pch_plls,
>-	.get_dpll = ibx_get_dpll,
>+	.get_dplls = ibx_get_dpll,
>+	.put_dplls = intel_put_dpll,
> 	.dump_hw_state = ibx_dump_hw_state,
> };
> 
>@@ -1915,7 +1970,8 @@
> 
> static const struct intel_dpll_mgr hsw_pll_mgr = {
> 	.dpll_info = hsw_plls,
>-	.get_dpll = hsw_get_dpll,
>+	.get_dplls = hsw_get_dpll,
>+	.put_dplls = intel_put_dpll,
> 	.dump_hw_state = hsw_dump_hw_state,
> };
> 
>@@ -1929,7 +1985,8 @@
> 
> static const struct intel_dpll_mgr skl_pll_mgr = {
> 	.dpll_info = skl_plls,
>-	.get_dpll = skl_get_dpll,
>+	.get_dplls = skl_get_dpll,
>+	.put_dplls = intel_put_dpll,
> 	.dump_hw_state = skl_dump_hw_state,
> };
> 
>@@ -1942,7 +1999,8 @@
> 
> static const struct intel_dpll_mgr bxt_pll_mgr = {
> 	.dpll_info = bxt_plls,
>-	.get_dpll = bxt_get_dpll,
>+	.get_dplls = bxt_get_dpll,
>+	.put_dplls = intel_put_dpll,
> 	.dump_hw_state = bxt_dump_hw_state,
> };
> 
>@@ -2332,10 +2390,12 @@
> 	return true;
> }
> 
>-static struct intel_shared_dpll *
>-cnl_get_dpll(struct intel_crtc_state *crtc_state,
>-	     struct intel_encoder *encoder)
>+static bool cnl_get_dpll(struct intel_atomic_state *state,
>+			 struct intel_crtc *crtc,
>+			 struct intel_encoder *encoder)
> {
>+	struct intel_crtc_state *crtc_state =
>+		intel_atomic_get_new_crtc_state(state, crtc);
> 	struct intel_shared_dpll *pll;
> 	bool bret;
> 
>@@ -2343,31 +2403,35 @@
> 		bret = cnl_ddi_hdmi_pll_dividers(crtc_state);
> 		if (!bret) {
> 			DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
>-			return NULL;
>+			return false;
> 		}
> 	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
> 		bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state);
> 		if (!bret) {
> 			DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
>-			return NULL;
>+			return false;
> 		}
> 	} else {
> 		DRM_DEBUG_KMS("Skip DPLL setup for output_types 0x%x\n",
> 			      crtc_state->output_types);
>-		return NULL;
>+		return false;
> 	}
> 
>-	pll = intel_find_shared_dpll(crtc_state,
>+	pll = intel_find_shared_dpll(state, crtc,
>+				     &crtc_state->dpll_hw_state,
> 				     DPLL_ID_SKL_DPLL0,
> 				     DPLL_ID_SKL_DPLL2);
> 	if (!pll) {
> 		DRM_DEBUG_KMS("No PLL selected\n");
>-		return NULL;
>+		return false;
> 	}
> 
>-	intel_reference_shared_dpll(pll, crtc_state);
>+	intel_reference_shared_dpll(state, crtc,
>+				    pll, &crtc_state->dpll_hw_state);
> 
>-	return pll;
>+	crtc_state->shared_dpll = pll;
>+
>+	return true;
> }
> 
> static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
>@@ -2394,7 +2458,8 @@
> 
> static const struct intel_dpll_mgr cnl_pll_mgr = {
> 	.dpll_info = cnl_plls,
>-	.get_dpll = cnl_get_dpll,
>+	.get_dplls = cnl_get_dpll,
>+	.put_dplls = intel_put_dpll,
> 	.dump_hw_state = cnl_dump_hw_state,
> };
> 
>@@ -2506,14 +2571,16 @@
> }
> 
> static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
>-				struct intel_encoder *encoder)
>+				struct intel_encoder *encoder,
>+				struct intel_dpll_hw_state *pll_state)
> {
> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> 	u32 cfgcr0, cfgcr1;
> 	struct skl_wrpll_params pll_params = { 0 };
> 	bool ret;
> 
>-	if (intel_port_is_tc(dev_priv, encoder->port))
>+	if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
>+							encoder->port)))
> 		ret = icl_calc_tbt_pll(crtc_state, &pll_params);
> 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
> 		 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
>@@ -2530,14 +2597,17 @@
> 	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
> 		 DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
> 		 DPLL_CFGCR1_KDIV(pll_params.kdiv) |
>-		 DPLL_CFGCR1_PDIV(pll_params.pdiv) |
>-		 DPLL_CFGCR1_CENTRAL_FREQ_8400;
>+		 DPLL_CFGCR1_PDIV(pll_params.pdiv);
> 
>-	memset(&crtc_state->dpll_hw_state, 0,
>-	       sizeof(crtc_state->dpll_hw_state));
>+	if (INTEL_GEN(dev_priv) >= 12)
>+		cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
>+	else
>+		cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
> 
>-	crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;
>-	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
>+	memset(pll_state, 0, sizeof(*pll_state));
>+
>+	pll_state->cfgcr0 = cfgcr0;
>+	pll_state->cfgcr1 = cfgcr1;
> 
> 	return true;
> }
>@@ -2627,10 +2697,10 @@
>  * The specification for this function uses real numbers, so the math had to be
>  * adapted to integer-only calculation, that's why it looks so different.
>  */
>-static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state)
>+static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
>+				  struct intel_dpll_hw_state *pll_state)
> {
> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>-	struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
> 	int refclk_khz = dev_priv->cdclk.hw.ref;
> 	int clock = crtc_state->port_clock;
> 	u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
>@@ -2792,63 +2862,184 @@
> 	return true;
> }
> 
>-static struct intel_shared_dpll *
>-icl_get_dpll(struct intel_crtc_state *crtc_state,
>-	     struct intel_encoder *encoder)
>+/**
>+ * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
>+ * @crtc_state: state for the CRTC to select the DPLL for
>+ * @port_dpll_id: the active @port_dpll_id to select
>+ *
>+ * Select the given @port_dpll_id instance from the DPLLs reserved for the
>+ * CRTC.
>+ */
>+void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
>+			      enum icl_port_dpll_id port_dpll_id)
> {
>-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>-	struct intel_digital_port *intel_dig_port;
>-	struct intel_shared_dpll *pll;
>+	struct icl_port_dpll *port_dpll =
>+		&crtc_state->icl_port_dplls[port_dpll_id];
>+
>+	crtc_state->shared_dpll = port_dpll->pll;
>+	crtc_state->dpll_hw_state = port_dpll->hw_state;
>+}
>+
>+static void icl_update_active_dpll(struct intel_atomic_state *state,
>+				   struct intel_crtc *crtc,
>+				   struct intel_encoder *encoder)
>+{
>+	struct intel_crtc_state *crtc_state =
>+		intel_atomic_get_new_crtc_state(state, crtc);
>+	struct intel_digital_port *primary_port;
>+	enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
>+
>+	primary_port = encoder->type == INTEL_OUTPUT_DP_MST ?
>+		enc_to_mst(&encoder->base)->primary :
>+		enc_to_dig_port(&encoder->base);
>+
>+	if (primary_port &&
>+	    (primary_port->tc_mode == TC_PORT_DP_ALT ||
>+	     primary_port->tc_mode == TC_PORT_LEGACY))
>+		port_dpll_id = ICL_PORT_DPLL_MG_PHY;
>+
>+	icl_set_active_port_dpll(crtc_state, port_dpll_id);
>+}
>+
>+static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>+				   struct intel_crtc *crtc,
>+				   struct intel_encoder *encoder)
>+{
>+	struct intel_crtc_state *crtc_state =
>+		intel_atomic_get_new_crtc_state(state, crtc);
>+	struct icl_port_dpll *port_dpll =
>+		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
>+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 	enum port port = encoder->port;
>-	enum intel_dpll_id min, max;
>-	bool ret;
>+	bool has_dpll4 = false;
> 
>-	if (intel_port_is_combophy(dev_priv, port)) {
>-		min = DPLL_ID_ICL_DPLL0;
>-		max = DPLL_ID_ICL_DPLL1;
>-		ret = icl_calc_dpll_state(crtc_state, encoder);
>-	} else if (intel_port_is_tc(dev_priv, port)) {
>-		if (encoder->type == INTEL_OUTPUT_DP_MST) {
>-			struct intel_dp_mst_encoder *mst_encoder;
>+	if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) {
>+		DRM_DEBUG_KMS("Could not calculate combo PHY PLL state.\n");
> 
>-			mst_encoder = enc_to_mst(&encoder->base);
>-			intel_dig_port = mst_encoder->primary;
>-		} else {
>-			intel_dig_port = enc_to_dig_port(&encoder->base);
>-		}
>+		return false;
>+	}
> 
>-		if (intel_dig_port->tc_type == TC_PORT_TBT) {
>-			min = DPLL_ID_ICL_TBTPLL;
>-			max = min;
>-			ret = icl_calc_dpll_state(crtc_state, encoder);
>-		} else {
>-			enum tc_port tc_port;
>+	if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
>+		has_dpll4 = true;
> 
>-			tc_port = intel_port_to_tc(dev_priv, port);
>-			min = icl_tc_port_to_pll_id(tc_port);
>-			max = min;
>-			ret = icl_calc_mg_pll_state(crtc_state);
>-		}
>-	} else {
>-		MISSING_CASE(port);
>-		return NULL;
>+	port_dpll->pll = intel_find_shared_dpll(state, crtc,
>+						&port_dpll->hw_state,
>+						DPLL_ID_ICL_DPLL0,
>+						has_dpll4 ? DPLL_ID_EHL_DPLL4
>+							  : DPLL_ID_ICL_DPLL1);
>+	if (!port_dpll->pll) {
>+		DRM_DEBUG_KMS("No combo PHY PLL found for port %c\n",
>+			      port_name(encoder->port));
>+		return false;
> 	}
> 
>-	if (!ret) {
>-		DRM_DEBUG_KMS("Could not calculate PLL state.\n");
>-		return NULL;
>+	intel_reference_shared_dpll(state, crtc,
>+				    port_dpll->pll, &port_dpll->hw_state);
>+
>+	icl_update_active_dpll(state, crtc, encoder);
>+
>+	return true;
>+}
>+
>+static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
>+				 struct intel_crtc *crtc,
>+				 struct intel_encoder *encoder)
>+{
>+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>+	struct intel_crtc_state *crtc_state =
>+		intel_atomic_get_new_crtc_state(state, crtc);
>+	struct icl_port_dpll *port_dpll;
>+	enum intel_dpll_id dpll_id;
>+
>+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
>+	if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) {
>+		DRM_DEBUG_KMS("Could not calculate TBT PLL state.\n");
>+		return false;
> 	}
> 
>+	port_dpll->pll = intel_find_shared_dpll(state, crtc,
>+						&port_dpll->hw_state,
>+						DPLL_ID_ICL_TBTPLL,
>+						DPLL_ID_ICL_TBTPLL);
>+	if (!port_dpll->pll) {
>+		DRM_DEBUG_KMS("No TBT-ALT PLL found\n");
>+		return false;
>+	}
>+	intel_reference_shared_dpll(state, crtc,
>+				    port_dpll->pll, &port_dpll->hw_state);
> 
>-	pll = intel_find_shared_dpll(crtc_state, min, max);
>-	if (!pll) {
>-		DRM_DEBUG_KMS("No PLL selected\n");
>-		return NULL;
>+
>+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
>+	if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) {
>+		DRM_DEBUG_KMS("Could not calculate MG PHY PLL state.\n");
>+		goto err_unreference_tbt_pll;
>+	}
>+
>+	dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
>+							 encoder->port));
>+	port_dpll->pll = intel_find_shared_dpll(state, crtc,
>+						&port_dpll->hw_state,
>+						dpll_id,
>+						dpll_id);
>+	if (!port_dpll->pll) {
>+		DRM_DEBUG_KMS("No MG PHY PLL found\n");
>+		goto err_unreference_tbt_pll;
> 	}
>+	intel_reference_shared_dpll(state, crtc,
>+				    port_dpll->pll, &port_dpll->hw_state);
> 
>-	intel_reference_shared_dpll(pll, crtc_state);
>+	icl_update_active_dpll(state, crtc, encoder);
> 
>-	return pll;
>+	return true;
>+
>+err_unreference_tbt_pll:
>+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
>+	intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
>+
>+	return false;
>+}
>+
>+static bool icl_get_dplls(struct intel_atomic_state *state,
>+			  struct intel_crtc *crtc,
>+			  struct intel_encoder *encoder)
>+{
>+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>+
>+	if (intel_phy_is_combo(dev_priv, phy))
>+		return icl_get_combo_phy_dpll(state, crtc, encoder);
>+	else if (intel_phy_is_tc(dev_priv, phy))
>+		return icl_get_tc_phy_dplls(state, crtc, encoder);
>+
>+	MISSING_CASE(phy);
>+
>+	return false;
>+}
>+
>+static void icl_put_dplls(struct intel_atomic_state *state,
>+			  struct intel_crtc *crtc)
>+{
>+	const struct intel_crtc_state *old_crtc_state =
>+		intel_atomic_get_old_crtc_state(state, crtc);
>+	struct intel_crtc_state *new_crtc_state =
>+		intel_atomic_get_new_crtc_state(state, crtc);
>+	enum icl_port_dpll_id id;
>+
>+	new_crtc_state->shared_dpll = NULL;
>+
>+	for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
>+		const struct icl_port_dpll *old_port_dpll =
>+			&old_crtc_state->icl_port_dplls[id];
>+		struct icl_port_dpll *new_port_dpll =
>+			&new_crtc_state->icl_port_dplls[id];
>+
>+		new_port_dpll->pll = NULL;
>+
>+		if (!old_port_dpll->pll)
>+			continue;
>+
>+		intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
>+	}
> }
> 
> static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
>@@ -2932,8 +3123,18 @@
> 	if (!(val & PLL_ENABLE))
> 		goto out;
> 
>-	hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
>-	hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
>+	if (INTEL_GEN(dev_priv) >= 12) {
>+		hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
>+		hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
>+	} else {
>+		if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
>+			hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(4));
>+			hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(4));
>+		} else {
>+			hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
>+			hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
>+		}
>+	}
> 
> 	ret = true;
> out:
>@@ -2945,8 +3146,14 @@
> 				   struct intel_shared_dpll *pll,
> 				   struct intel_dpll_hw_state *hw_state)
> {
>-	return icl_pll_get_hw_state(dev_priv, pll, hw_state,
>-				    CNL_DPLL_ENABLE(pll->info->id));
>+	i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
>+
>+	if (IS_ELKHARTLAKE(dev_priv) &&
>+	    pll->info->id == DPLL_ID_EHL_DPLL4) {
>+		enable_reg = MG_PLL_ENABLE(0);
>+	}
>+
>+	return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
> }
> 
> static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
>@@ -2961,10 +3168,24 @@
> {
> 	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
> 	const enum intel_dpll_id id = pll->info->id;
>+	i915_reg_t cfgcr0_reg, cfgcr1_reg;
> 
>-	I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
>-	I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
>-	POSTING_READ(ICL_DPLL_CFGCR1(id));
>+	if (INTEL_GEN(dev_priv) >= 12) {
>+		cfgcr0_reg = TGL_DPLL_CFGCR0(id);
>+		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
>+	} else {
>+		if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
>+			cfgcr0_reg = ICL_DPLL_CFGCR0(4);
>+			cfgcr1_reg = ICL_DPLL_CFGCR1(4);
>+		} else {
>+			cfgcr0_reg = ICL_DPLL_CFGCR0(id);
>+			cfgcr1_reg = ICL_DPLL_CFGCR1(id);
>+		}
>+	}
>+
>+	I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
>+	I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
>+	POSTING_READ(cfgcr1_reg);
> }
> 
> static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
>@@ -3057,6 +3278,19 @@
> {
> 	i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> 
>+	if (IS_ELKHARTLAKE(dev_priv) &&
>+	    pll->info->id == DPLL_ID_EHL_DPLL4) {
>+		enable_reg = MG_PLL_ENABLE(0);
>+
>+		/*
>+		 * We need to disable DC states when this DPLL is enabled.
>+		 * This can be done by taking a reference on DPLL4 power
>+		 * domain.
>+		 */
>+		pll->wakeref = intel_display_power_get(dev_priv,
>+						       POWER_DOMAIN_DPLL_DC_OFF);
>+	}
>+
> 	icl_pll_power_enable(dev_priv, pll, enable_reg);
> 
> 	icl_dpll_write(dev_priv, pll);
>@@ -3152,7 +3386,19 @@
> static void combo_pll_disable(struct drm_i915_private *dev_priv,
> 			      struct intel_shared_dpll *pll)
> {
>-	icl_pll_disable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id));
>+	i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
>+
>+	if (IS_ELKHARTLAKE(dev_priv) &&
>+	    pll->info->id == DPLL_ID_EHL_DPLL4) {
>+		enable_reg = MG_PLL_ENABLE(0);
>+		icl_pll_disable(dev_priv, pll, enable_reg);
>+
>+		intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
>+					pll->wakeref);
>+		return;
>+	}
>+
>+	icl_pll_disable(dev_priv, pll, enable_reg);
> }
> 
> static void tbt_pll_disable(struct drm_i915_private *dev_priv,
>@@ -3223,19 +3469,38 @@
> 
> static const struct intel_dpll_mgr icl_pll_mgr = {
> 	.dpll_info = icl_plls,
>-	.get_dpll = icl_get_dpll,
>+	.get_dplls = icl_get_dplls,
>+	.put_dplls = icl_put_dplls,
>+	.update_active_dpll = icl_update_active_dpll,
> 	.dump_hw_state = icl_dump_hw_state,
> };
> 
> static const struct dpll_info ehl_plls[] = {
> 	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> 	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
>+	{ "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
> 	{ },
> };
> 
> static const struct intel_dpll_mgr ehl_pll_mgr = {
> 	.dpll_info = ehl_plls,
>-	.get_dpll = icl_get_dpll,
>+	.get_dplls = icl_get_dplls,
>+	.put_dplls = icl_put_dplls,
>+	.dump_hw_state = icl_dump_hw_state,
>+};
>+
>+static const struct dpll_info tgl_plls[] = {
>+	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
>+	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
>+	{ "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
>+	/* TODO: Add typeC plls */
>+	{ },
>+};
>+
>+static const struct intel_dpll_mgr tgl_pll_mgr = {
>+	.dpll_info = tgl_plls,
>+	.get_dplls = icl_get_dplls,
>+	.put_dplls = icl_put_dplls,
> 	.dump_hw_state = icl_dump_hw_state,
> };
> 
>@@ -3252,7 +3517,9 @@
> 	const struct dpll_info *dpll_info;
> 	int i;
> 
>-	if (IS_ELKHARTLAKE(dev_priv))
>+	if (INTEL_GEN(dev_priv) >= 12)
>+		dpll_mgr = &tgl_pll_mgr;
>+	else if (IS_ELKHARTLAKE(dev_priv))
> 		dpll_mgr = &ehl_pll_mgr;
> 	else if (INTEL_GEN(dev_priv) >= 11)
> 		dpll_mgr = &icl_pll_mgr;
>@@ -3287,50 +3554,87 @@
> }
> 
> /**
>- * intel_get_shared_dpll - get a shared DPLL for CRTC and encoder combination
>- * @crtc_state: atomic state for the crtc
>+ * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
>+ * @state: atomic state
>+ * @crtc: CRTC to reserve DPLLs for
>  * @encoder: encoder
>  *
>- * Find an appropriate DPLL for the given CRTC and encoder combination. A
>- * reference from the @crtc_state to the returned pll is registered in the
>- * atomic state. That configuration is made effective by calling
>- * intel_shared_dpll_swap_state(). The reference should be released by calling
>- * intel_release_shared_dpll().
>+ * This function reserves all required DPLLs for the given CRTC and encoder
>+ * combination in the current atomic commit @state and the new @crtc atomic
>+ * state.
>+ *
>+ * The new configuration in the atomic commit @state is made effective by
>+ * calling intel_shared_dpll_swap_state().
>+ *
>+ * The reserved DPLLs should be released by calling
>+ * intel_release_shared_dplls().
>  *
>  * Returns:
>- * A shared DPLL to be used by @crtc_state and @encoder.
>+ * True if all required DPLLs were successfully reserved.
>  */
>-struct intel_shared_dpll *
>-intel_get_shared_dpll(struct intel_crtc_state *crtc_state,
>-		      struct intel_encoder *encoder)
>+bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
>+				struct intel_crtc *crtc,
>+				struct intel_encoder *encoder)
> {
>-	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> 	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
> 
> 	if (WARN_ON(!dpll_mgr))
>-		return NULL;
>+		return false;
>+
>+	return dpll_mgr->get_dplls(state, crtc, encoder);
>+}
>+
>+/**
>+ * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
>+ * @state: atomic state
>+ * @crtc: crtc from which the DPLLs are to be released
>+ *
>+ * This function releases all DPLLs reserved by intel_reserve_shared_dplls()
>+ * from the current atomic commit @state and the old @crtc atomic state.
>+ *
>+ * The new configuration in the atomic commit @state is made effective by
>+ * calling intel_shared_dpll_swap_state().
>+ */
>+void intel_release_shared_dplls(struct intel_atomic_state *state,
>+				struct intel_crtc *crtc)
>+{
>+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>+	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
>+
>+	/*
>+	 * FIXME: this function is called for every platform having a
>+	 * compute_clock hook, even though the platform doesn't yet support
>+	 * the shared DPLL framework and intel_reserve_shared_dplls() is not
>+	 * called on those.
>+	 */
>+	if (!dpll_mgr)
>+		return;
> 
>-	return dpll_mgr->get_dpll(crtc_state, encoder);
>+	dpll_mgr->put_dplls(state, crtc);
> }
> 
> /**
>- * intel_release_shared_dpll - end use of DPLL by CRTC in atomic state
>- * @dpll: dpll in use by @crtc
>- * @crtc: crtc
>+ * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
>  * @state: atomic state
>+ * @crtc: the CRTC for which to update the active DPLL
>+ * @encoder: encoder determining the type of port DPLL
>  *
>- * This function releases the reference from @crtc to @dpll from the
>- * atomic @state. The new configuration is made effective by calling
>- * intel_shared_dpll_swap_state().
>+ * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
>+ * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
>+ * DPLL selected will be based on the current mode of the encoder's port.
>  */
>-void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
>-			       struct intel_crtc *crtc,
>-			       struct drm_atomic_state *state)
>+void intel_update_active_dpll(struct intel_atomic_state *state,
>+			      struct intel_crtc *crtc,
>+			      struct intel_encoder *encoder)
> {
>-	struct intel_shared_dpll_state *shared_dpll_state;
>+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>+	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
>+
>+	if (WARN_ON(!dpll_mgr))
>+		return;
> 
>-	shared_dpll_state = intel_atomic_get_shared_dpll_state(state);
>-	shared_dpll_state[dpll->info->id].crtc_mask &= ~(1 << crtc->pipe);
>+	dpll_mgr->update_active_dpll(state, crtc, encoder);
> }
> 
> /**
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dpll_mgr.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dpll_mgr.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dpll_mgr.h	2019-08-31 15:01:12.019736182 -0500
>@@ -28,6 +28,7 @@
> #include <linux/types.h>
> 
> #include "intel_display.h"
>+#include "intel_wakeref.h"
> 
> /*FIXME: Move this to a more appropriate place. */
> #define abs_diff(a, b) ({			\
>@@ -36,9 +37,9 @@
> 	(void) (&__a == &__b);			\
> 	__a > __b ? (__a - __b) : (__b - __a); })
> 
>-struct drm_atomic_state;
> struct drm_device;
> struct drm_i915_private;
>+struct intel_atomic_state;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_encoder;
>@@ -110,35 +111,59 @@
> 
> 
> 	/**
>-	 * @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0
>+	 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
> 	 */
> 	DPLL_ID_ICL_DPLL0 = 0,
> 	/**
>-	 * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
>+	 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
> 	 */
> 	DPLL_ID_ICL_DPLL1 = 1,
> 	/**
>-	 * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
>+	 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
>+	 */
>+	DPLL_ID_EHL_DPLL4 = 2,
>+	/**
>+	 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
> 	 */
> 	DPLL_ID_ICL_TBTPLL = 2,
> 	/**
>-	 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
>+	 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
>+	 *                      TGL TC PLL 1 port 1 (TC1)
> 	 */
> 	DPLL_ID_ICL_MGPLL1 = 3,
> 	/**
> 	 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
>+	 *                      TGL TC PLL 1 port 2 (TC2)
> 	 */
> 	DPLL_ID_ICL_MGPLL2 = 4,
> 	/**
> 	 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
>+	 *                      TGL TC PLL 1 port 3 (TC3)
> 	 */
> 	DPLL_ID_ICL_MGPLL3 = 5,
> 	/**
> 	 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
>+	 *                      TGL TC PLL 1 port 4 (TC4)
> 	 */
> 	DPLL_ID_ICL_MGPLL4 = 6,
>+	/**
>+	 * @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5)
>+	 */
>+	DPLL_ID_TGL_MGPLL5 = 7,
>+	/**
>+	 * @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6)
>+	 */
>+	DPLL_ID_TGL_MGPLL6 = 8,
>+};
>+
>+#define I915_NUM_PLLS 9
>+
>+enum icl_port_dpll_id {
>+	ICL_PORT_DPLL_DEFAULT,
>+	ICL_PORT_DPLL_MG_PHY,
>+
>+	ICL_PORT_DPLL_COUNT,
> };
>-#define I915_NUM_PLLS 7
> 
> struct intel_dpll_hw_state {
> 	/* i9xx, pch plls */
>@@ -195,7 +220,7 @@
>  * future state which would be applied by an atomic mode set (stored in
>  * a struct &intel_atomic_state).
>  *
>- * See also intel_get_shared_dpll() and intel_release_shared_dpll().
>+ * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
>  */
> struct intel_shared_dpll_state {
> 	/**
>@@ -312,6 +337,7 @@
> 	 * @info: platform specific info
> 	 */
> 	const struct dpll_info *info;
>+	intel_wakeref_t wakeref;
> };
> 
> #define SKL_DPLL0 0
>@@ -331,15 +357,20 @@
> 			bool state);
> #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
>-struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc_state *state,
>-						struct intel_encoder *encoder);
>-void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
>-			       struct intel_crtc *crtc,
>-			       struct drm_atomic_state *state);
>+bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
>+				struct intel_crtc *crtc,
>+				struct intel_encoder *encoder);
>+void intel_release_shared_dplls(struct intel_atomic_state *state,
>+				struct intel_crtc *crtc);
>+void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
>+			      enum icl_port_dpll_id port_dpll_id);
>+void intel_update_active_dpll(struct intel_atomic_state *state,
>+			      struct intel_crtc *crtc,
>+			      struct intel_encoder *encoder);
> void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
> void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
> void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
>-void intel_shared_dpll_swap_state(struct drm_atomic_state *state);
>+void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
> void intel_shared_dpll_init(struct drm_device *dev);
> 
> void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dp_mst.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dp_mst.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dp_mst.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dp_mst.h	2019-08-31 15:01:12.018736182 -0500
>@@ -6,9 +6,15 @@
> #ifndef __INTEL_DP_MST_H__
> #define __INTEL_DP_MST_H__
> 
>-struct intel_digital_port;
>+#include "intel_drv.h"
> 
> int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
> void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
>+static inline int
>+intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port)
>+{
>+	return intel_dig_port->dp.active_mst_links;
>+}
>+
> 
> #endif /* __INTEL_DP_MST_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dsi.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dsi.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_dsi.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_dsi.h	2019-08-31 15:01:12.019736182 -0500
>@@ -49,8 +49,11 @@
> 
> 	struct intel_connector *attached_connector;
> 
>-	/* bit mask of ports being driven */
>-	u16 ports;
>+	/* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */
>+	union {
>+		u16 ports;	/* VLV DSI */
>+		u16 phys;	/* ICL DSI */
>+	};
> 
> 	/* if true, use HS mode, otherwise LP */
> 	bool hs;
>@@ -132,7 +135,10 @@
> 	return container_of(h, struct intel_dsi_host, base);
> }
> 
>-#define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask)
>+#define for_each_dsi_port(__port, __ports_mask) \
>+	for_each_port_masked(__port, __ports_mask)
>+#define for_each_dsi_phy(__phy, __phys_mask) \
>+	for_each_phy_masked(__phy, __phys_mask)
> 
> static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
> {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_gmbus.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_gmbus.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_gmbus.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_gmbus.c	2019-08-31 15:01:12.019736182 -0500
>@@ -94,11 +94,25 @@
> 	[GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
> };
> 
>+static const struct gmbus_pin gmbus_pins_tgp[] = {
>+	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
>+	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
>+	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
>+	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
>+	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
>+	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
>+	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
>+	[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
>+	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
>+};
>+
> /* pin is expected to be valid */
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
> 					     unsigned int pin)
> {
>-	if (HAS_PCH_MCC(dev_priv))
>+	if (HAS_PCH_TGP(dev_priv))
>+		return &gmbus_pins_tgp[pin];
>+	else if (HAS_PCH_MCC(dev_priv))
> 		return &gmbus_pins_mcc[pin];
> 	else if (HAS_PCH_ICP(dev_priv))
> 		return &gmbus_pins_icp[pin];
>@@ -119,7 +133,9 @@
> {
> 	unsigned int size;
> 
>-	if (HAS_PCH_MCC(dev_priv))
>+	if (HAS_PCH_TGP(dev_priv))
>+		size = ARRAY_SIZE(gmbus_pins_tgp);
>+	else if (HAS_PCH_MCC(dev_priv))
> 		size = ARRAY_SIZE(gmbus_pins_mcc);
> 	else if (HAS_PCH_ICP(dev_priv))
> 		size = ARRAY_SIZE(gmbus_pins_icp);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_hdcp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_hdcp.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_hdcp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_hdcp.c	2019-08-31 15:01:12.244736202 -0500
>@@ -523,12 +523,16 @@
> 	 * authentication.
> 	 */
> 	num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
>-	if (num_downstream == 0)
>+	if (num_downstream == 0) {
>+		DRM_DEBUG_KMS("Repeater with zero downstream devices\n");
> 		return -EINVAL;
>+	}
> 
> 	ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL);
>-	if (!ksv_fifo)
>+	if (!ksv_fifo) {
>+		DRM_DEBUG_KMS("Out of mem: ksv_fifo\n");
> 		return -ENOMEM;
>+	}
> 
> 	ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
> 	if (ret)
>@@ -866,7 +870,6 @@
> 					       prop_work);
> 	struct intel_connector *connector = intel_hdcp_to_connector(hdcp);
> 	struct drm_device *dev = connector->base.dev;
>-	struct drm_connector_state *state;
> 
> 	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
> 	mutex_lock(&hdcp->mutex);
>@@ -876,10 +879,9 @@
> 	 * those to UNDESIRED is handled by core. If value == UNDESIRED,
> 	 * we're running just after hdcp has been disabled, so just exit
> 	 */
>-	if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
>-		state = connector->base.state;
>-		state->content_protection = hdcp->value;
>-	}
>+	if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
>+		drm_hdcp_update_content_protection(&connector->base,
>+						   hdcp->value);
> 
> 	mutex_unlock(&hdcp->mutex);
> 	drm_modeset_unlock(&dev->mode_config.connection_mutex);
>@@ -1207,8 +1209,10 @@
> 	if (ret < 0)
> 		return ret;
> 
>-	if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL)
>+	if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) {
>+		DRM_DEBUG_KMS("cert.rx_caps dont claim HDCP2.2\n");
> 		return -EINVAL;
>+	}
> 
> 	hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]);
> 
>@@ -1749,14 +1753,15 @@
> 	.unbind = i915_hdcp_component_unbind,
> };
> 
>-static inline int initialize_hdcp_port_data(struct intel_connector *connector)
>+static inline int initialize_hdcp_port_data(struct intel_connector *connector,
>+					    const struct intel_hdcp_shim *shim)
> {
> 	struct intel_hdcp *hdcp = &connector->hdcp;
> 	struct hdcp_port_data *data = &hdcp->port_data;
> 
> 	data->port = connector->encoder->port;
> 	data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
>-	data->protocol = (u8)hdcp->shim->protocol;
>+	data->protocol = (u8)shim->protocol;
> 
> 	data->k = 1;
> 	if (!data->streams)
>@@ -1806,12 +1811,13 @@
> 	}
> }
> 
>-static void intel_hdcp2_init(struct intel_connector *connector)
>+static void intel_hdcp2_init(struct intel_connector *connector,
>+			     const struct intel_hdcp_shim *shim)
> {
> 	struct intel_hdcp *hdcp = &connector->hdcp;
> 	int ret;
> 
>-	ret = initialize_hdcp_port_data(connector);
>+	ret = initialize_hdcp_port_data(connector, shim);
> 	if (ret) {
> 		DRM_DEBUG_KMS("Mei hdcp data init failed\n");
> 		return;
>@@ -1830,23 +1836,28 @@
> 	if (!shim)
> 		return -EINVAL;
> 
>-	ret = drm_connector_attach_content_protection_property(&connector->base);
>-	if (ret)
>+	if (is_hdcp2_supported(dev_priv))
>+		intel_hdcp2_init(connector, shim);
>+
>+	ret =
>+	drm_connector_attach_content_protection_property(&connector->base,
>+							 hdcp->hdcp2_supported);
>+	if (ret) {
>+		hdcp->hdcp2_supported = false;
>+		kfree(hdcp->port_data.streams);
> 		return ret;
>+	}
> 
> 	hdcp->shim = shim;
> 	mutex_init(&hdcp->mutex);
> 	INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work);
> 	INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work);
>-
>-	if (is_hdcp2_supported(dev_priv))
>-		intel_hdcp2_init(connector);
> 	init_waitqueue_head(&hdcp->cp_irq_queue);
> 
> 	return 0;
> }
> 
>-int intel_hdcp_enable(struct intel_connector *connector)
>+int intel_hdcp_enable(struct intel_connector *connector, u8 content_type)
> {
> 	struct intel_hdcp *hdcp = &connector->hdcp;
> 	unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS;
>@@ -1857,6 +1868,7 @@
> 
> 	mutex_lock(&hdcp->mutex);
> 	WARN_ON(hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
>+	hdcp->content_type = content_type;
> 
> 	/*
> 	 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
>@@ -1868,8 +1880,12 @@
> 			check_link_interval = DRM_HDCP2_CHECK_PERIOD_MS;
> 	}
> 
>-	/* When HDCP2.2 fails, HDCP1.4 will be attempted */
>-	if (ret && intel_hdcp_capable(connector)) {
>+	/*
>+	 * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will
>+	 * be attempted.
>+	 */
>+	if (ret && intel_hdcp_capable(connector) &&
>+	    hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) {
> 		ret = _intel_hdcp_enable(connector);
> 	}
> 
>@@ -1951,12 +1967,15 @@
> 
> 	/*
> 	 * Nothing to do if the state didn't change, or HDCP was activated since
>-	 * the last commit
>+	 * the last commit. And also no change in hdcp content type.
> 	 */
> 	if (old_cp == new_cp ||
> 	    (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
>-	     new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED))
>-		return;
>+	     new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) {
>+		if (old_state->hdcp_content_type ==
>+				new_state->hdcp_content_type)
>+			return;
>+	}
> 
> 	crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
> 						   new_state->crtc);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_hdcp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_hdcp.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_hdcp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_hdcp.h	2019-08-31 15:01:12.019736182 -0500
>@@ -21,7 +21,7 @@
> 			     struct drm_connector_state *new_state);
> int intel_hdcp_init(struct intel_connector *connector,
> 		    const struct intel_hdcp_shim *hdcp_shim);
>-int intel_hdcp_enable(struct intel_connector *connector);
>+int intel_hdcp_enable(struct intel_connector *connector, u8 content_type);
> int intel_hdcp_disable(struct intel_connector *connector);
> bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
> bool intel_hdcp_capable(struct intel_connector *connector);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_hdmi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_hdmi.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_hdmi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_hdmi.c	2019-08-31 15:01:12.019736182 -0500
>@@ -2930,51 +2930,34 @@
> 
> static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
> {
>-	u8 ddc_pin;
>+	enum phy phy = intel_port_to_phy(dev_priv, port);
> 
>-	switch (port) {
>-	case PORT_A:
>-		ddc_pin = GMBUS_PIN_1_BXT;
>-		break;
>-	case PORT_B:
>-		ddc_pin = GMBUS_PIN_2_BXT;
>-		break;
>-	case PORT_C:
>-		ddc_pin = GMBUS_PIN_9_TC1_ICP;
>-		break;
>-	case PORT_D:
>-		ddc_pin = GMBUS_PIN_10_TC2_ICP;
>-		break;
>-	case PORT_E:
>-		ddc_pin = GMBUS_PIN_11_TC3_ICP;
>-		break;
>-	case PORT_F:
>-		ddc_pin = GMBUS_PIN_12_TC4_ICP;
>-		break;
>-	default:
>-		MISSING_CASE(port);
>-		ddc_pin = GMBUS_PIN_2_BXT;
>-		break;
>-	}
>-	return ddc_pin;
>+	if (intel_phy_is_combo(dev_priv, phy))
>+		return GMBUS_PIN_1_BXT + port;
>+	else if (intel_phy_is_tc(dev_priv, phy))
>+		return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
>+
>+	WARN(1, "Unknown port:%c\n", port_name(port));
>+	return GMBUS_PIN_2_BXT;
> }
> 
> static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
> {
>+	enum phy phy = intel_port_to_phy(dev_priv, port);
> 	u8 ddc_pin;
> 
>-	switch (port) {
>-	case PORT_A:
>+	switch (phy) {
>+	case PHY_A:
> 		ddc_pin = GMBUS_PIN_1_BXT;
> 		break;
>-	case PORT_B:
>+	case PHY_B:
> 		ddc_pin = GMBUS_PIN_2_BXT;
> 		break;
>-	case PORT_C:
>+	case PHY_C:
> 		ddc_pin = GMBUS_PIN_9_TC1_ICP;
> 		break;
> 	default:
>-		MISSING_CASE(port);
>+		MISSING_CASE(phy);
> 		ddc_pin = GMBUS_PIN_1_BXT;
> 		break;
> 	}
>@@ -3019,7 +3002,7 @@
> 
> 	if (HAS_PCH_MCC(dev_priv))
> 		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
>-	else if (HAS_PCH_ICP(dev_priv))
>+	else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_ICP(dev_priv))
> 		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
> 	else if (HAS_PCH_CNP(dev_priv))
> 		ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
>@@ -3143,6 +3126,32 @@
> 		DRM_DEBUG_KMS("CEC notifier get failed\n");
> }
> 
>+static enum intel_hotplug_state
>+intel_hdmi_hotplug(struct intel_encoder *encoder,
>+		   struct intel_connector *connector, bool irq_received)
>+{
>+	enum intel_hotplug_state state;
>+
>+	state = intel_encoder_hotplug(encoder, connector, irq_received);
>+
>+	/*
>+	 * On many platforms the HDMI live state signal is known to be
>+	 * unreliable, so we can't use it to detect if a sink is connected or
>+	 * not. Instead we detect if it's connected based on whether we can
>+	 * read the EDID or not. That in turn has a problem during disconnect,
>+	 * since the HPD interrupt may be raised before the DDC lines get
>+	 * disconnected (due to how the required length of DDC vs. HPD
>+	 * connector pins are specified) and so we'll still be able to get a
>+	 * valid EDID. To solve this schedule another detection cycle if this
>+	 * time around we didn't detect any change in the sink's connection
>+	 * status.
>+	 */
>+	if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
>+		state = INTEL_HOTPLUG_RETRY;
>+
>+	return state;
>+}
>+
> void intel_hdmi_init(struct drm_i915_private *dev_priv,
> 		     i915_reg_t hdmi_reg, enum port port)
> {
>@@ -3166,7 +3175,7 @@
> 			 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
> 			 "HDMI %c", port_name(port));
> 
>-	intel_encoder->hotplug = intel_encoder_hotplug;
>+	intel_encoder->hotplug = intel_hdmi_hotplug;
> 	intel_encoder->compute_config = intel_hdmi_compute_config;
> 	if (HAS_PCH_SPLIT(dev_priv)) {
> 		intel_encoder->disable = pch_disable_hdmi;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_hotplug.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_hotplug.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_hotplug.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_hotplug.c	2019-08-31 15:01:12.019736182 -0500
>@@ -112,6 +112,7 @@
> 
> #define HPD_STORM_DETECT_PERIOD		1000
> #define HPD_STORM_REENABLE_DELAY	(2 * 60 * 1000)
>+#define HPD_RETRY_DELAY			1000
> 
> /**
>  * intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ storm on a pin
>@@ -266,8 +267,10 @@
> 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> }
> 
>-bool intel_encoder_hotplug(struct intel_encoder *encoder,
>-			   struct intel_connector *connector)
>+enum intel_hotplug_state
>+intel_encoder_hotplug(struct intel_encoder *encoder,
>+		      struct intel_connector *connector,
>+		      bool irq_received)
> {
> 	struct drm_device *dev = connector->base.dev;
> 	enum drm_connector_status old_status;
>@@ -279,7 +282,7 @@
> 		drm_helper_probe_detect(&connector->base, NULL, false);
> 
> 	if (old_status == connector->base.status)
>-		return false;
>+		return INTEL_HOTPLUG_UNCHANGED;
> 
> 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
> 		      connector->base.base.id,
>@@ -287,7 +290,7 @@
> 		      drm_get_connector_status_name(old_status),
> 		      drm_get_connector_status_name(connector->base.status));
> 
>-	return true;
>+	return INTEL_HOTPLUG_CHANGED;
> }
> 
> static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder)
>@@ -339,7 +342,7 @@
> 		spin_lock_irq(&dev_priv->irq_lock);
> 		dev_priv->hotplug.event_bits |= old_bits;
> 		spin_unlock_irq(&dev_priv->irq_lock);
>-		schedule_work(&dev_priv->hotplug.hotplug_work);
>+		queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
> 	}
> }
> 
>@@ -349,14 +352,16 @@
> static void i915_hotplug_work_func(struct work_struct *work)
> {
> 	struct drm_i915_private *dev_priv =
>-		container_of(work, struct drm_i915_private, hotplug.hotplug_work);
>+		container_of(work, struct drm_i915_private,
>+			     hotplug.hotplug_work.work);
> 	struct drm_device *dev = &dev_priv->drm;
> 	struct intel_connector *intel_connector;
> 	struct intel_encoder *intel_encoder;
> 	struct drm_connector *connector;
> 	struct drm_connector_list_iter conn_iter;
>-	bool changed = false;
>+	u32 changed = 0, retry = 0;
> 	u32 hpd_event_bits;
>+	u32 hpd_retry_bits;
> 
> 	mutex_lock(&dev->mode_config.mutex);
> 	DRM_DEBUG_KMS("running encoder hotplug functions\n");
>@@ -365,6 +370,8 @@
> 
> 	hpd_event_bits = dev_priv->hotplug.event_bits;
> 	dev_priv->hotplug.event_bits = 0;
>+	hpd_retry_bits = dev_priv->hotplug.retry_bits;
>+	dev_priv->hotplug.retry_bits = 0;
> 
> 	/* Enable polling for connectors which had HPD IRQ storms */
> 	intel_hpd_irq_storm_switch_to_polling(dev_priv);
>@@ -373,16 +380,29 @@
> 
> 	drm_connector_list_iter_begin(dev, &conn_iter);
> 	drm_for_each_connector_iter(connector, &conn_iter) {
>+		u32 hpd_bit;
>+
> 		intel_connector = to_intel_connector(connector);
> 		if (!intel_connector->encoder)
> 			continue;
> 		intel_encoder = intel_connector->encoder;
>-		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
>+		hpd_bit = BIT(intel_encoder->hpd_pin);
>+		if ((hpd_event_bits | hpd_retry_bits) & hpd_bit) {
> 			DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
> 				      connector->name, intel_encoder->hpd_pin);
> 
>-			changed |= intel_encoder->hotplug(intel_encoder,
>-							  intel_connector);
>+			switch (intel_encoder->hotplug(intel_encoder,
>+						       intel_connector,
>+						       hpd_event_bits & hpd_bit)) {
>+			case INTEL_HOTPLUG_UNCHANGED:
>+				break;
>+			case INTEL_HOTPLUG_CHANGED:
>+				changed |= hpd_bit;
>+				break;
>+			case INTEL_HOTPLUG_RETRY:
>+				retry |= hpd_bit;
>+				break;
>+			}
> 		}
> 	}
> 	drm_connector_list_iter_end(&conn_iter);
>@@ -390,6 +410,17 @@
> 
> 	if (changed)
> 		drm_kms_helper_hotplug_event(dev);
>+
>+	/* Remove shared HPD pins that have changed */
>+	retry &= ~changed;
>+	if (retry) {
>+		spin_lock_irq(&dev_priv->irq_lock);
>+		dev_priv->hotplug.retry_bits |= retry;
>+		spin_unlock_irq(&dev_priv->irq_lock);
>+
>+		mod_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work,
>+				 msecs_to_jiffies(HPD_RETRY_DELAY));
>+	}
> }
> 
> 
>@@ -516,7 +547,7 @@
> 	if (queue_dig)
> 		queue_work(dev_priv->hotplug.dp_wq, &dev_priv->hotplug.dig_port_work);
> 	if (queue_hp)
>-		schedule_work(&dev_priv->hotplug.hotplug_work);
>+		queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
> }
> 
> /**
>@@ -636,7 +667,8 @@
> 
> void intel_hpd_init_work(struct drm_i915_private *dev_priv)
> {
>-	INIT_WORK(&dev_priv->hotplug.hotplug_work, i915_hotplug_work_func);
>+	INIT_DELAYED_WORK(&dev_priv->hotplug.hotplug_work,
>+			  i915_hotplug_work_func);
> 	INIT_WORK(&dev_priv->hotplug.dig_port_work, i915_digport_work_func);
> 	INIT_WORK(&dev_priv->hotplug.poll_init_work, i915_hpd_poll_init_work);
> 	INIT_DELAYED_WORK(&dev_priv->hotplug.reenable_work,
>@@ -650,11 +682,12 @@
> 	dev_priv->hotplug.long_port_mask = 0;
> 	dev_priv->hotplug.short_port_mask = 0;
> 	dev_priv->hotplug.event_bits = 0;
>+	dev_priv->hotplug.retry_bits = 0;
> 
> 	spin_unlock_irq(&dev_priv->irq_lock);
> 
> 	cancel_work_sync(&dev_priv->hotplug.dig_port_work);
>-	cancel_work_sync(&dev_priv->hotplug.hotplug_work);
>+	cancel_delayed_work_sync(&dev_priv->hotplug.hotplug_work);
> 	cancel_work_sync(&dev_priv->hotplug.poll_init_work);
> 	cancel_delayed_work_sync(&dev_priv->hotplug.reenable_work);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_hotplug.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_hotplug.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_hotplug.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_hotplug.h	2019-08-31 15:01:12.019736182 -0500
>@@ -15,8 +15,9 @@
> struct intel_encoder;
> 
> void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
>-bool intel_encoder_hotplug(struct intel_encoder *encoder,
>-			   struct intel_connector *connector);
>+enum intel_hotplug_state intel_encoder_hotplug(struct intel_encoder *encoder,
>+					       struct intel_connector *connector,
>+					       bool irq_received);
> void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> 			   u32 pin_mask, u32 long_mask);
> void intel_hpd_init(struct drm_i915_private *dev_priv);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_overlay.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_overlay.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_overlay.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_overlay.c	2019-08-31 15:01:12.020736183 -0500
>@@ -175,6 +175,7 @@
> 
> struct intel_overlay {
> 	struct drm_i915_private *i915;
>+	struct intel_context *context;
> 	struct intel_crtc *crtc;
> 	struct i915_vma *vma;
> 	struct i915_vma *old_vma;
>@@ -239,9 +240,7 @@
> 
> static struct i915_request *alloc_request(struct intel_overlay *overlay)
> {
>-	struct intel_engine_cs *engine = overlay->i915->engine[RCS0];
>-
>-	return i915_request_create(engine->kernel_context);
>+	return i915_request_create(overlay->context);
> }
> 
> /* overlay needs to be disable in OCMD reg */
>@@ -1359,11 +1358,16 @@
> 	if (!HAS_OVERLAY(dev_priv))
> 		return;
> 
>+	if (!HAS_ENGINE(dev_priv, RCS0))
>+		return;
>+
> 	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
> 	if (!overlay)
> 		return;
> 
> 	overlay->i915 = dev_priv;
>+	overlay->context = dev_priv->engine[RCS0]->kernel_context;
>+	GEM_BUG_ON(!overlay->context);
> 
> 	overlay->color_key = 0x0101fe;
> 	overlay->color_key_enabled = true;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_pipe_crc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_pipe_crc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_pipe_crc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_pipe_crc.c	2019-08-31 15:01:12.020736183 -0500
>@@ -667,5 +667,5 @@
> 
> 	I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);
> 	POSTING_READ(PIPE_CRC_CTL(crtc->index));
>-	synchronize_irq(dev_priv->drm.irq);
>+	intel_synchronize_irq(dev_priv);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_sdvo.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_sdvo.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_sdvo.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_sdvo.c	2019-08-31 15:01:12.020736183 -0500
>@@ -274,130 +274,145 @@
> 	return false;
> }
> 
>-#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
>+#define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ }
>+
> /** Mapping of command numbers to names, for debug output */
>-static const struct _sdvo_cmd_name {
>+static const struct {
> 	u8 cmd;
> 	const char *name;
> } __attribute__ ((packed)) sdvo_cmd_names[] = {
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
>+	SDVO_CMD_NAME_ENTRY(RESET),
>+	SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS),
>+	SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV),
>+	SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS),
>+	SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS),
>+	SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS),
>+	SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP),
>+	SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP),
>+	SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS),
>+	SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT),
>+	SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG),
>+	SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG),
>+	SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE),
>+	SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT),
>+	SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT),
>+	SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1),
>+	SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2),
>+	SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1),
>+	SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2),
>+	SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1),
>+	SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2),
>+	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1),
>+	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2),
>+	SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING),
>+	SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1),
>+	SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2),
>+	SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE),
>+	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE),
>+	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS),
>+	SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT),
>+	SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT),
>+	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS),
>+	SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT),
>+	SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT),
>+	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES),
>+	SDVO_CMD_NAME_ENTRY(GET_POWER_STATE),
>+	SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE),
>+	SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE),
>+	SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH),
>+	SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT),
>+	SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT),
>+	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS),
> 
> 	/* Add the op code for SDVO enhancements */
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS),
>+	SDVO_CMD_NAME_ENTRY(GET_HPOS),
>+	SDVO_CMD_NAME_ENTRY(SET_HPOS),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS),
>+	SDVO_CMD_NAME_ENTRY(GET_VPOS),
>+	SDVO_CMD_NAME_ENTRY(SET_VPOS),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION),
>+	SDVO_CMD_NAME_ENTRY(GET_SATURATION),
>+	SDVO_CMD_NAME_ENTRY(SET_SATURATION),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_HUE),
>+	SDVO_CMD_NAME_ENTRY(GET_HUE),
>+	SDVO_CMD_NAME_ENTRY(SET_HUE),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST),
>+	SDVO_CMD_NAME_ENTRY(GET_CONTRAST),
>+	SDVO_CMD_NAME_ENTRY(SET_CONTRAST),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS),
>+	SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS),
>+	SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H),
>+	SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H),
>+	SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V),
>+	SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V),
>+	SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER),
>+	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER),
>+	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE),
>+	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE),
>+	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D),
>+	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D),
>+	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS),
>+	SDVO_CMD_NAME_ENTRY(GET_SHARPNESS),
>+	SDVO_CMD_NAME_ENTRY(SET_SHARPNESS),
>+	SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL),
>+	SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER),
>+	SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER),
>+	SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER),
>+	SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER),
>+	SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER),
>+	SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER),
> 
> 	/* HDMI op code */
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
>-	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
>+	SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE),
>+	SDVO_CMD_NAME_ENTRY(GET_ENCODE),
>+	SDVO_CMD_NAME_ENTRY(SET_ENCODE),
>+	SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI),
>+	SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI),
>+	SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP),
>+	SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY),
>+	SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY),
>+	SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER),
>+	SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT),
>+	SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT),
>+	SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX),
>+	SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX),
>+	SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO),
>+	SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT),
>+	SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT),
>+	SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE),
>+	SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE),
>+	SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA),
>+	SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA),
> };
> 
>+#undef SDVO_CMD_NAME_ENTRY
>+
>+static const char *sdvo_cmd_name(u8 cmd)
>+{
>+	int i;
>+
>+	for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
>+		if (cmd == sdvo_cmd_names[i].cmd)
>+			return sdvo_cmd_names[i].name;
>+	}
>+
>+	return NULL;
>+}
>+
> #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
> 
> static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
> 				   const void *args, int args_len)
> {
>+	const char *cmd_name;
> 	int i, pos = 0;
> #define BUF_LEN 256
> 	char buffer[BUF_LEN];
>@@ -412,15 +427,12 @@
> 	for (; i < 8; i++) {
> 		BUF_PRINT("   ");
> 	}
>-	for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
>-		if (cmd == sdvo_cmd_names[i].cmd) {
>-			BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
>-			break;
>-		}
>-	}
>-	if (i == ARRAY_SIZE(sdvo_cmd_names)) {
>+
>+	cmd_name = sdvo_cmd_name(cmd);
>+	if (cmd_name)
>+		BUF_PRINT("(%s)", cmd_name);
>+	else
> 		BUF_PRINT("(%02X)", cmd);
>-	}
> 	BUG_ON(pos >= BUF_LEN - 1);
> #undef BUF_PRINT
> #undef BUF_LEN
>@@ -429,15 +441,23 @@
> }
> 
> static const char * const cmd_status_names[] = {
>-	"Power on",
>-	"Success",
>-	"Not supported",
>-	"Invalid arg",
>-	"Pending",
>-	"Target not specified",
>-	"Scaling not supported"
>+	[SDVO_CMD_STATUS_POWER_ON] = "Power on",
>+	[SDVO_CMD_STATUS_SUCCESS] = "Success",
>+	[SDVO_CMD_STATUS_NOTSUPP] = "Not supported",
>+	[SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg",
>+	[SDVO_CMD_STATUS_PENDING] = "Pending",
>+	[SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified",
>+	[SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported",
> };
> 
>+static const char *sdvo_cmd_status(u8 status)
>+{
>+	if (status < ARRAY_SIZE(cmd_status_names))
>+		return cmd_status_names[status];
>+	else
>+		return NULL;
>+}
>+
> static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
> 				   const void *args, int args_len,
> 				   bool unlocked)
>@@ -516,6 +536,7 @@
> static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
> 				     void *response, int response_len)
> {
>+	const char *cmd_status;
> 	u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
> 	u8 status;
> 	int i, pos = 0;
>@@ -562,8 +583,9 @@
> #define BUF_PRINT(args...) \
> 	pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
> 
>-	if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
>-		BUF_PRINT("(%s)", cmd_status_names[status]);
>+	cmd_status = sdvo_cmd_status(status);
>+	if (cmd_status)
>+		BUF_PRINT("(%s)", cmd_status);
> 	else
> 		BUF_PRINT("(??? %d)", status);
> 
>@@ -929,6 +951,20 @@
> 				    &audio_state, 1);
> }
> 
>+static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo,
>+				     u8 *hbuf_size)
>+{
>+	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
>+				  hbuf_size, 1))
>+		return false;
>+
>+	/* Buffer size is 0 based, hooray! However zero means zero. */
>+	if (*hbuf_size)
>+		(*hbuf_size)++;
>+
>+	return true;
>+}
>+
> #if 0
> static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
> {
>@@ -972,14 +1008,10 @@
> 				  set_buf_index, 2))
> 		return false;
> 
>-	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
>-				  &hbuf_size, 1))
>+	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
> 		return false;
> 
>-	/* Buffer size is 0 based, hooray! */
>-	hbuf_size++;
>-
>-	DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
>+	DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",
> 		      if_index, length, hbuf_size);
> 
> 	if (hbuf_size < length)
>@@ -1030,14 +1062,10 @@
> 	if (tx_rate == SDVO_HBUF_TX_DISABLED)
> 		return 0;
> 
>-	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
>-				  &hbuf_size, 1))
>-		return -ENXIO;
>-
>-	/* Buffer size is 0 based, hooray! */
>-	hbuf_size++;
>+	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
>+		return false;
> 
>-	DRM_DEBUG_KMS("reading sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
>+	DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",
> 		      if_index, length, hbuf_size);
> 
> 	hbuf_size = min_t(unsigned int, length, hbuf_size);
>@@ -1893,12 +1921,14 @@
> 			     &intel_sdvo->hotplug_active, 2);
> }
> 
>-static bool intel_sdvo_hotplug(struct intel_encoder *encoder,
>-			       struct intel_connector *connector)
>+static enum intel_hotplug_state
>+intel_sdvo_hotplug(struct intel_encoder *encoder,
>+		   struct intel_connector *connector,
>+		   bool irq_received)
> {
> 	intel_sdvo_enable_hotplug(encoder);
> 
>-	return intel_encoder_hotplug(encoder, connector);
>+	return intel_encoder_hotplug(encoder, connector, irq_received);
> }
> 
> static bool
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_sprite.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_sprite.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_sprite.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_sprite.c	2019-08-31 15:01:12.020736183 -0500
>@@ -441,9 +441,21 @@
> 		 */
> 		[DRM_COLOR_YCBCR_BT709] = {
> 			0x7C98, 0x7800, 0x0,
>-			0x9EF8, 0x7800, 0xABF8,
>+			0x9EF8, 0x7800, 0xAC00,
> 			0x0, 0x7800,  0x7ED8,
> 		},
>+		/*
>+		 * BT.2020 full range YCbCr -> full range RGB
>+		 * The matrix required is :
>+		 * [1.000, 0.000, 1.474,
>+		 *  1.000, -0.1645, -0.5713,
>+		 *  1.000, 1.8814, 0.0000]
>+		 */
>+		[DRM_COLOR_YCBCR_BT2020] = {
>+			0x7BC8, 0x7800, 0x0,
>+			0x8928, 0x7800, 0xAA88,
>+			0x0, 0x7800, 0x7F10,
>+		},
> 	};
> 
> 	/* Matrix for Limited Range to Full Range Conversion */
>@@ -451,26 +463,38 @@
> 		/*
> 		 * BT.601 Limted range YCbCr -> full range RGB
> 		 * The matrix required is :
>-		 * [1.164384, 0.000, 1.596370,
>-		 *  1.138393, -0.382500, -0.794598,
>-		 *  1.138393, 1.971696, 0.0000]
>+		 * [1.164384, 0.000, 1.596027,
>+		 *  1.164384, -0.39175, -0.812813,
>+		 *  1.164384, 2.017232, 0.0000]
> 		 */
> 		[DRM_COLOR_YCBCR_BT601] = {
> 			0x7CC8, 0x7950, 0x0,
>-			0x8CB8, 0x7918, 0x9C40,
>-			0x0, 0x7918, 0x7FC8,
>+			0x8D00, 0x7950, 0x9C88,
>+			0x0, 0x7950, 0x6810,
> 		},
> 		/*
> 		 * BT.709 Limited range YCbCr -> full range RGB
> 		 * The matrix required is :
>-		 * [1.164, 0.000, 1.833671,
>-		 *  1.138393, -0.213249, -0.532909,
>-		 *  1.138393, 2.112402, 0.0000]
>+		 * [1.164384, 0.000, 1.792741,
>+		 *  1.164384, -0.213249, -0.532909,
>+		 *  1.164384, 2.112402, 0.0000]
> 		 */
> 		[DRM_COLOR_YCBCR_BT709] = {
>-			0x7EA8, 0x7950, 0x0,
>-			0x8888, 0x7918, 0xADA8,
>-			0x0, 0x7918,  0x6870,
>+			0x7E58, 0x7950, 0x0,
>+			0x8888, 0x7950, 0xADA8,
>+			0x0, 0x7950,  0x6870,
>+		},
>+		/*
>+		 * BT.2020 Limited range YCbCr -> full range RGB
>+		 * The matrix required is :
>+		 * [1.164, 0.000, 1.678,
>+		 *  1.164, -0.1873, -0.6504,
>+		 *  1.164, 2.1417, 0.0000]
>+		 */
>+		[DRM_COLOR_YCBCR_BT2020] = {
>+			0x7D70, 0x7950, 0x0,
>+			0x8A68, 0x7950, 0xAC00,
>+			0x0, 0x7950, 0x6890,
> 		},
> 	};
> 	const u16 *csc;
>@@ -492,8 +516,11 @@
> 
> 	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
> 		      PREOFF_YUV_TO_RGB_HI);
>-	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
>-		      PREOFF_YUV_TO_RGB_ME);
>+	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
>+		I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0);
>+	else
>+		I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
>+			      PREOFF_YUV_TO_RGB_ME);
> 	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
> 		      PREOFF_YUV_TO_RGB_LO);
> 	I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
>@@ -683,6 +710,16 @@
> 	return ret;
> }
> 
>+static void i9xx_plane_linear_gamma(u16 gamma[8])
>+{
>+	/* The points are not evenly spaced. */
>+	static const u8 in[8] = { 0, 1, 2, 4, 8, 16, 24, 32 };
>+	int i;
>+
>+	for (i = 0; i < 8; i++)
>+		gamma[i] = (in[i] << 8) / 32;
>+}
>+
> static void
> chv_update_csc(const struct intel_plane_state *plane_state)
> {
>@@ -858,6 +895,31 @@
> 	return sprctl;
> }
> 
>+static void vlv_update_gamma(const struct intel_plane_state *plane_state)
>+{
>+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>+	const struct drm_framebuffer *fb = plane_state->base.fb;
>+	enum pipe pipe = plane->pipe;
>+	enum plane_id plane_id = plane->id;
>+	u16 gamma[8];
>+	int i;
>+
>+	/* Seems RGB data bypasses the gamma always */
>+	if (!fb->format->is_yuv)
>+		return;
>+
>+	i9xx_plane_linear_gamma(gamma);
>+
>+	/* FIXME these register are single buffered :( */
>+	/* The two end points are implicit (0.0 and 1.0) */
>+	for (i = 1; i < 8 - 1; i++)
>+		I915_WRITE_FW(SPGAMC(pipe, plane_id, i - 1),
>+			      gamma[i] << 16 |
>+			      gamma[i] << 8 |
>+			      gamma[i]);
>+}
>+
> static void
> vlv_update_plane(struct intel_plane *plane,
> 		 const struct intel_crtc_state *crtc_state,
>@@ -916,6 +978,7 @@
> 		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
> 
> 	vlv_update_clrc(plane_state);
>+	vlv_update_gamma(plane_state);
> 
> 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
>@@ -1013,6 +1076,8 @@
> 		return 0;
> 	}
> 
>+	sprctl |= SPRITE_INT_GAMMA_DISABLE;
>+
> 	if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
> 		sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
> 
>@@ -1033,6 +1098,45 @@
> 	return sprctl;
> }
> 
>+static void ivb_sprite_linear_gamma(u16 gamma[18])
>+{
>+	int i;
>+
>+	for (i = 0; i < 17; i++)
>+		gamma[i] = (i << 10) / 16;
>+
>+	gamma[i] = 3 << 10;
>+	i++;
>+}
>+
>+static void ivb_update_gamma(const struct intel_plane_state *plane_state)
>+{
>+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>+	enum pipe pipe = plane->pipe;
>+	u16 gamma[18];
>+	int i;
>+
>+	ivb_sprite_linear_gamma(gamma);
>+
>+	/* FIXME these register are single buffered :( */
>+	for (i = 0; i < 16; i++)
>+		I915_WRITE_FW(SPRGAMC(pipe, i),
>+			      gamma[i] << 20 |
>+			      gamma[i] << 10 |
>+			      gamma[i]);
>+
>+	I915_WRITE_FW(SPRGAMC16(pipe, 0), gamma[i]);
>+	I915_WRITE_FW(SPRGAMC16(pipe, 1), gamma[i]);
>+	I915_WRITE_FW(SPRGAMC16(pipe, 2), gamma[i]);
>+	i++;
>+
>+	I915_WRITE_FW(SPRGAMC17(pipe, 0), gamma[i]);
>+	I915_WRITE_FW(SPRGAMC17(pipe, 1), gamma[i]);
>+	I915_WRITE_FW(SPRGAMC17(pipe, 2), gamma[i]);
>+	i++;
>+}
>+
> static void
> ivb_update_plane(struct intel_plane *plane,
> 		 const struct intel_crtc_state *crtc_state,
>@@ -1099,6 +1203,8 @@
> 	I915_WRITE_FW(SPRSURF(pipe),
> 		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
> 
>+	ivb_update_gamma(plane_state);
>+
> 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
> 
>@@ -1224,6 +1330,66 @@
> 	return dvscntr;
> }
> 
>+static void g4x_update_gamma(const struct intel_plane_state *plane_state)
>+{
>+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>+	const struct drm_framebuffer *fb = plane_state->base.fb;
>+	enum pipe pipe = plane->pipe;
>+	u16 gamma[8];
>+	int i;
>+
>+	/* Seems RGB data bypasses the gamma always */
>+	if (!fb->format->is_yuv)
>+		return;
>+
>+	i9xx_plane_linear_gamma(gamma);
>+
>+	/* FIXME these register are single buffered :( */
>+	/* The two end points are implicit (0.0 and 1.0) */
>+	for (i = 1; i < 8 - 1; i++)
>+		I915_WRITE_FW(DVSGAMC_G4X(pipe, i - 1),
>+			      gamma[i] << 16 |
>+			      gamma[i] << 8 |
>+			      gamma[i]);
>+}
>+
>+static void ilk_sprite_linear_gamma(u16 gamma[17])
>+{
>+	int i;
>+
>+	for (i = 0; i < 17; i++)
>+		gamma[i] = (i << 10) / 16;
>+}
>+
>+static void ilk_update_gamma(const struct intel_plane_state *plane_state)
>+{
>+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>+	const struct drm_framebuffer *fb = plane_state->base.fb;
>+	enum pipe pipe = plane->pipe;
>+	u16 gamma[17];
>+	int i;
>+
>+	/* Seems RGB data bypasses the gamma always */
>+	if (!fb->format->is_yuv)
>+		return;
>+
>+	ilk_sprite_linear_gamma(gamma);
>+
>+	/* FIXME these register are single buffered :( */
>+	for (i = 0; i < 16; i++)
>+		I915_WRITE_FW(DVSGAMC_ILK(pipe, i),
>+			      gamma[i] << 20 |
>+			      gamma[i] << 10 |
>+			      gamma[i]);
>+
>+	I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
>+	I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
>+	I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
>+	i++;
>+}
>+
> static void
> g4x_update_plane(struct intel_plane *plane,
> 		 const struct intel_crtc_state *crtc_state,
>@@ -1283,6 +1449,11 @@
> 	I915_WRITE_FW(DVSSURF(pipe),
> 		      intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
> 
>+	if (IS_G4X(dev_priv))
>+		g4x_update_gamma(plane_state);
>+	else
>+		ilk_update_gamma(plane_state);
>+
> 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> }
> 
>@@ -1347,7 +1518,7 @@
> 	const struct drm_framebuffer *fb = plane_state->base.fb;
> 	const struct drm_rect *src = &plane_state->base.src;
> 	const struct drm_rect *dst = &plane_state->base.dst;
>-	int src_x, src_y, src_w, src_h, crtc_w, crtc_h;
>+	int src_x, src_w, src_h, crtc_w, crtc_h;
> 	const struct drm_display_mode *adjusted_mode =
> 		&crtc_state->base.adjusted_mode;
> 	unsigned int cpp = fb->format->cpp[0];
>@@ -1358,7 +1529,6 @@
> 	crtc_h = drm_rect_height(dst);
> 
> 	src_x = src->x1 >> 16;
>-	src_y = src->y1 >> 16;
> 	src_w = drm_rect_width(src) >> 16;
> 	src_h = drm_rect_height(src) >> 16;
> 
>@@ -1852,28 +2022,7 @@
> 	DRM_FORMAT_VYUY,
> };
> 
>-static const u32 icl_plane_formats[] = {
>-	DRM_FORMAT_C8,
>-	DRM_FORMAT_RGB565,
>-	DRM_FORMAT_XRGB8888,
>-	DRM_FORMAT_XBGR8888,
>-	DRM_FORMAT_ARGB8888,
>-	DRM_FORMAT_ABGR8888,
>-	DRM_FORMAT_XRGB2101010,
>-	DRM_FORMAT_XBGR2101010,
>-	DRM_FORMAT_YUYV,
>-	DRM_FORMAT_YVYU,
>-	DRM_FORMAT_UYVY,
>-	DRM_FORMAT_VYUY,
>-	DRM_FORMAT_Y210,
>-	DRM_FORMAT_Y212,
>-	DRM_FORMAT_Y216,
>-	DRM_FORMAT_XVYU2101010,
>-	DRM_FORMAT_XVYU12_16161616,
>-	DRM_FORMAT_XVYU16161616,
>-};
>-
>-static const u32 icl_hdr_plane_formats[] = {
>+static const u32 skl_planar_formats[] = {
> 	DRM_FORMAT_C8,
> 	DRM_FORMAT_RGB565,
> 	DRM_FORMAT_XRGB8888,
>@@ -1882,23 +2031,14 @@
> 	DRM_FORMAT_ABGR8888,
> 	DRM_FORMAT_XRGB2101010,
> 	DRM_FORMAT_XBGR2101010,
>-	DRM_FORMAT_XRGB16161616F,
>-	DRM_FORMAT_XBGR16161616F,
>-	DRM_FORMAT_ARGB16161616F,
>-	DRM_FORMAT_ABGR16161616F,
> 	DRM_FORMAT_YUYV,
> 	DRM_FORMAT_YVYU,
> 	DRM_FORMAT_UYVY,
> 	DRM_FORMAT_VYUY,
>-	DRM_FORMAT_Y210,
>-	DRM_FORMAT_Y212,
>-	DRM_FORMAT_Y216,
>-	DRM_FORMAT_XVYU2101010,
>-	DRM_FORMAT_XVYU12_16161616,
>-	DRM_FORMAT_XVYU16161616,
>+	DRM_FORMAT_NV12,
> };
> 
>-static const u32 skl_planar_formats[] = {
>+static const u32 glk_planar_formats[] = {
> 	DRM_FORMAT_C8,
> 	DRM_FORMAT_RGB565,
> 	DRM_FORMAT_XRGB8888,
>@@ -1912,9 +2052,12 @@
> 	DRM_FORMAT_UYVY,
> 	DRM_FORMAT_VYUY,
> 	DRM_FORMAT_NV12,
>+	DRM_FORMAT_P010,
>+	DRM_FORMAT_P012,
>+	DRM_FORMAT_P016,
> };
> 
>-static const u32 glk_planar_formats[] = {
>+static const u32 icl_sdr_y_plane_formats[] = {
> 	DRM_FORMAT_C8,
> 	DRM_FORMAT_RGB565,
> 	DRM_FORMAT_XRGB8888,
>@@ -1927,13 +2070,15 @@
> 	DRM_FORMAT_YVYU,
> 	DRM_FORMAT_UYVY,
> 	DRM_FORMAT_VYUY,
>-	DRM_FORMAT_NV12,
>-	DRM_FORMAT_P010,
>-	DRM_FORMAT_P012,
>-	DRM_FORMAT_P016,
>+	DRM_FORMAT_Y210,
>+	DRM_FORMAT_Y212,
>+	DRM_FORMAT_Y216,
>+	DRM_FORMAT_XVYU2101010,
>+	DRM_FORMAT_XVYU12_16161616,
>+	DRM_FORMAT_XVYU16161616,
> };
> 
>-static const u32 icl_planar_formats[] = {
>+static const u32 icl_sdr_uv_plane_formats[] = {
> 	DRM_FORMAT_C8,
> 	DRM_FORMAT_RGB565,
> 	DRM_FORMAT_XRGB8888,
>@@ -1958,7 +2103,7 @@
> 	DRM_FORMAT_XVYU16161616,
> };
> 
>-static const u32 icl_hdr_planar_formats[] = {
>+static const u32 icl_hdr_plane_formats[] = {
> 	DRM_FORMAT_C8,
> 	DRM_FORMAT_RGB565,
> 	DRM_FORMAT_XRGB8888,
>@@ -2201,9 +2346,6 @@
> static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> 				 enum pipe pipe, enum plane_id plane_id)
> {
>-	if (INTEL_GEN(dev_priv) >= 11)
>-		return plane_id <= PLANE_SPRITE3;
>-
> 	/* Display WA #0870: skl, bxt */
> 	if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
> 		return false;
>@@ -2217,6 +2359,48 @@
> 	return true;
> }
> 
>+static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv,
>+					enum pipe pipe, enum plane_id plane_id,
>+					int *num_formats)
>+{
>+	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
>+		*num_formats = ARRAY_SIZE(skl_planar_formats);
>+		return skl_planar_formats;
>+	} else {
>+		*num_formats = ARRAY_SIZE(skl_plane_formats);
>+		return skl_plane_formats;
>+	}
>+}
>+
>+static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv,
>+					enum pipe pipe, enum plane_id plane_id,
>+					int *num_formats)
>+{
>+	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
>+		*num_formats = ARRAY_SIZE(glk_planar_formats);
>+		return glk_planar_formats;
>+	} else {
>+		*num_formats = ARRAY_SIZE(skl_plane_formats);
>+		return skl_plane_formats;
>+	}
>+}
>+
>+static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
>+					enum pipe pipe, enum plane_id plane_id,
>+					int *num_formats)
>+{
>+	if (icl_is_hdr_plane(dev_priv, plane_id)) {
>+		*num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
>+		return icl_hdr_plane_formats;
>+	} else if (icl_is_nv12_y_plane(plane_id)) {
>+		*num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
>+		return icl_sdr_y_plane_formats;
>+	} else {
>+		*num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats);
>+		return icl_sdr_uv_plane_formats;
>+	}
>+}
>+
> static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
> 			      enum pipe pipe, enum plane_id plane_id)
> {
>@@ -2270,30 +2454,15 @@
> 	if (icl_is_nv12_y_plane(plane_id))
> 		plane->update_slave = icl_update_slave;
> 
>-	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
>-		if (icl_is_hdr_plane(dev_priv, plane_id)) {
>-			formats = icl_hdr_planar_formats;
>-			num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
>-		} else if (INTEL_GEN(dev_priv) >= 11) {
>-			formats = icl_planar_formats;
>-			num_formats = ARRAY_SIZE(icl_planar_formats);
>-		} else if (INTEL_GEN(dev_priv) == 10 || IS_GEMINILAKE(dev_priv)) {
>-			formats = glk_planar_formats;
>-			num_formats = ARRAY_SIZE(glk_planar_formats);
>-		} else {
>-			formats = skl_planar_formats;
>-			num_formats = ARRAY_SIZE(skl_planar_formats);
>-		}
>-	} else if (icl_is_hdr_plane(dev_priv, plane_id)) {
>-		formats = icl_hdr_plane_formats;
>-		num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
>-	} else if (INTEL_GEN(dev_priv) >= 11) {
>-		formats = icl_plane_formats;
>-		num_formats = ARRAY_SIZE(icl_plane_formats);
>-	} else {
>-		formats = skl_plane_formats;
>-		num_formats = ARRAY_SIZE(skl_plane_formats);
>-	}
>+	if (INTEL_GEN(dev_priv) >= 11)
>+		formats = icl_get_plane_formats(dev_priv, pipe,
>+						plane_id, &num_formats);
>+	else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>+		formats = glk_get_plane_formats(dev_priv, pipe,
>+						plane_id, &num_formats);
>+	else
>+		formats = skl_get_plane_formats(dev_priv, pipe,
>+						plane_id, &num_formats);
> 
> 	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
> 	if (plane->has_ccs)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_tc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_tc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_tc.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_tc.c	2019-08-31 15:01:12.020736183 -0500
>@@ -0,0 +1,537 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright Â© 2019 Intel Corporation
>+ */
>+
>+#include "i915_drv.h"
>+#include "intel_display.h"
>+#include "intel_dp_mst.h"
>+#include "intel_tc.h"
>+
>+static const char *tc_port_mode_name(enum tc_port_mode mode)
>+{
>+	static const char * const names[] = {
>+		[TC_PORT_TBT_ALT] = "tbt-alt",
>+		[TC_PORT_DP_ALT] = "dp-alt",
>+		[TC_PORT_LEGACY] = "legacy",
>+	};
>+
>+	if (WARN_ON(mode >= ARRAY_SIZE(names)))
>+		mode = TC_PORT_TBT_ALT;
>+
>+	return names[mode];
>+}
>+
>+static bool has_modular_fia(struct drm_i915_private *i915)
>+{
>+	if (!INTEL_INFO(i915)->display.has_modular_fia)
>+		return false;
>+
>+	return intel_uncore_read(&i915->uncore,
>+				 PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
>+}
>+
>+static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
>+				   enum tc_port tc_port)
>+{
>+	if (!has_modular_fia(i915))
>+		return FIA1;
>+
>+	/*
>+	 * Each Modular FIA instance houses 2 TC ports. In SOC that has more
>+	 * than two TC ports, there are multiple instances of Modular FIA.
>+	 */
>+	return tc_port / 2;
>+}
>+
>+u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
>+{
>+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>+	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
>+	struct intel_uncore *uncore = &i915->uncore;
>+	u32 lane_mask;
>+
>+	lane_mask = intel_uncore_read(uncore,
>+				      PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
>+
>+	WARN_ON(lane_mask == 0xffffffff);
>+
>+	return (lane_mask & DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
>+	       DP_LANE_ASSIGNMENT_SHIFT(tc_port);
>+}
>+
>+int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
>+{
>+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>+	intel_wakeref_t wakeref;
>+	u32 lane_mask;
>+
>+	if (dig_port->tc_mode != TC_PORT_DP_ALT)
>+		return 4;
>+
>+	lane_mask = 0;
>+	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
>+		lane_mask = intel_tc_port_get_lane_mask(dig_port);
>+
>+	switch (lane_mask) {
>+	default:
>+		MISSING_CASE(lane_mask);
>+		/* fall-through */
>+	case 0x1:
>+	case 0x2:
>+	case 0x4:
>+	case 0x8:
>+		return 1;
>+	case 0x3:
>+	case 0xc:
>+		return 2;
>+	case 0xf:
>+		return 4;
>+	}
>+}
>+
>+void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>+				      int required_lanes)
>+{
>+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>+	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
>+	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
>+	struct intel_uncore *uncore = &i915->uncore;
>+	u32 val;
>+
>+	WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
>+
>+	val = intel_uncore_read(uncore,
>+				PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
>+	val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
>+
>+	switch (required_lanes) {
>+	case 1:
>+		val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
>+			DFLEXDPMLE1_DPMLETC_ML0(tc_port);
>+		break;
>+	case 2:
>+		val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
>+			DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
>+		break;
>+	case 4:
>+		val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
>+		break;
>+	default:
>+		MISSING_CASE(required_lanes);
>+	}
>+
>+	intel_uncore_write(uncore,
>+			   PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
>+}
>+
>+static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
>+				      u32 live_status_mask)
>+{
>+	u32 valid_hpd_mask;
>+
>+	if (dig_port->tc_legacy_port)
>+		valid_hpd_mask = BIT(TC_PORT_LEGACY);
>+	else
>+		valid_hpd_mask = BIT(TC_PORT_DP_ALT) |
>+				 BIT(TC_PORT_TBT_ALT);
>+
>+	if (!(live_status_mask & ~valid_hpd_mask))
>+		return;
>+
>+	/* If live status mismatches the VBT flag, trust the live status. */
>+	DRM_ERROR("Port %s: live status %08x mismatches the legacy port flag, fix flag\n",
>+		  dig_port->tc_port_name, live_status_mask);
>+
>+	dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
>+}
>+
>+static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
>+{
>+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>+	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
>+	struct intel_uncore *uncore = &i915->uncore;
>+	u32 mask = 0;
>+	u32 val;
>+
>+	val = intel_uncore_read(uncore,
>+				PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
>+
>+	if (val == 0xffffffff) {
>+		DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
>+			      dig_port->tc_port_name);
>+		return mask;
>+	}
>+
>+	if (val & TC_LIVE_STATE_TBT(tc_port))
>+		mask |= BIT(TC_PORT_TBT_ALT);
>+	if (val & TC_LIVE_STATE_TC(tc_port))
>+		mask |= BIT(TC_PORT_DP_ALT);
>+
>+	if (intel_uncore_read(uncore, SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port))
>+		mask |= BIT(TC_PORT_LEGACY);
>+
>+	/* The sink can be connected only in a single mode. */
>+	if (!WARN_ON(hweight32(mask) > 1))
>+		tc_port_fixup_legacy_flag(dig_port, mask);
>+
>+	return mask;
>+}
>+
>+static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
>+{
>+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>+	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
>+	struct intel_uncore *uncore = &i915->uncore;
>+	u32 val;
>+
>+	val = intel_uncore_read(uncore,
>+				PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
>+	if (val == 0xffffffff) {
>+		DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
>+			      dig_port->tc_port_name);
>+		return false;
>+	}
>+
>+	return val & DP_PHY_MODE_STATUS_COMPLETED(tc_port);
>+}
>+
>+static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
>+				     bool enable)
>+{
>+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>+	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
>+	struct intel_uncore *uncore = &i915->uncore;
>+	u32 val;
>+
>+	val = intel_uncore_read(uncore,
>+				PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
>+	if (val == 0xffffffff) {
>+		DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
>+			      dig_port->tc_port_name,
>+			      enableddisabled(enable));
>+
>+		return false;
>+	}
>+
>+	val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
>+	if (!enable)
>+		val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
>+
>+	intel_uncore_write(uncore,
>+			   PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
>+
>+	if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
>+		DRM_DEBUG_KMS("Port %s: PHY complete clear timed out\n",
>+			      dig_port->tc_port_name);
>+
>+	return true;
>+}
>+
>+static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
>+{
>+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>+	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
>+	struct intel_uncore *uncore = &i915->uncore;
>+	u32 val;
>+
>+	val = intel_uncore_read(uncore,
>+				PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
>+	if (val == 0xffffffff) {
>+		DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assume safe mode\n",
>+			      dig_port->tc_port_name);
>+		return true;
>+	}
>+
>+	return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port));
>+}
>+
>+/*
>+ * This function implements the first part of the Connect Flow described by our
>+ * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
>+ * lanes, EDID, etc) is done as needed in the typical places.
>+ *
>+ * Unlike the other ports, type-C ports are not available to use as soon as we
>+ * get a hotplug. The type-C PHYs can be shared between multiple controllers:
>+ * display, USB, etc. As a result, handshaking through FIA is required around
>+ * connect and disconnect to cleanly transfer ownership with the controller and
>+ * set the type-C power state.
>+ */
>+static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
>+			       int required_lanes)
>+{
>+	int max_lanes;
>+
>+	if (!icl_tc_phy_status_complete(dig_port)) {
>+		DRM_DEBUG_KMS("Port %s: PHY not ready\n",
>+			      dig_port->tc_port_name);
>+		goto out_set_tbt_alt_mode;
>+	}
>+
>+	if (!icl_tc_phy_set_safe_mode(dig_port, false) &&
>+	    !WARN_ON(dig_port->tc_legacy_port))
>+		goto out_set_tbt_alt_mode;
>+
>+	max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
>+	if (dig_port->tc_legacy_port) {
>+		WARN_ON(max_lanes != 4);
>+		dig_port->tc_mode = TC_PORT_LEGACY;
>+
>+		return;
>+	}
>+
>+	/*
>+	 * Now we have to re-check the live state, in case the port recently
>+	 * became disconnected. Not necessary for legacy mode.
>+	 */
>+	if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) {
>+		DRM_DEBUG_KMS("Port %s: PHY sudden disconnect\n",
>+			      dig_port->tc_port_name);
>+		goto out_set_safe_mode;
>+	}
>+
>+	if (max_lanes < required_lanes) {
>+		DRM_DEBUG_KMS("Port %s: PHY max lanes %d < required lanes %d\n",
>+			      dig_port->tc_port_name,
>+			      max_lanes, required_lanes);
>+		goto out_set_safe_mode;
>+	}
>+
>+	dig_port->tc_mode = TC_PORT_DP_ALT;
>+
>+	return;
>+
>+out_set_safe_mode:
>+	icl_tc_phy_set_safe_mode(dig_port, true);
>+out_set_tbt_alt_mode:
>+	dig_port->tc_mode = TC_PORT_TBT_ALT;
>+}
>+
>+/*
>+ * See the comment at the connect function. This implements the Disconnect
>+ * Flow.
>+ */
>+static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
>+{
>+	switch (dig_port->tc_mode) {
>+	case TC_PORT_LEGACY:
>+		/* Nothing to do, we never disconnect from legacy mode */
>+		break;
>+	case TC_PORT_DP_ALT:
>+		icl_tc_phy_set_safe_mode(dig_port, true);
>+		dig_port->tc_mode = TC_PORT_TBT_ALT;
>+		break;
>+	case TC_PORT_TBT_ALT:
>+		/* Nothing to do, we stay in TBT-alt mode */
>+		break;
>+	default:
>+		MISSING_CASE(dig_port->tc_mode);
>+	}
>+}
>+
>+static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
>+{
>+	if (!icl_tc_phy_status_complete(dig_port)) {
>+		DRM_DEBUG_KMS("Port %s: PHY status not complete\n",
>+			      dig_port->tc_port_name);
>+		return dig_port->tc_mode == TC_PORT_TBT_ALT;
>+	}
>+
>+	if (icl_tc_phy_is_in_safe_mode(dig_port)) {
>+		DRM_DEBUG_KMS("Port %s: PHY still in safe mode\n",
>+			      dig_port->tc_port_name);
>+
>+		return false;
>+	}
>+
>+	return dig_port->tc_mode == TC_PORT_DP_ALT ||
>+	       dig_port->tc_mode == TC_PORT_LEGACY;
>+}
>+
>+static enum tc_port_mode
>+intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
>+{
>+	u32 live_status_mask = tc_port_live_status_mask(dig_port);
>+	bool in_safe_mode = icl_tc_phy_is_in_safe_mode(dig_port);
>+	enum tc_port_mode mode;
>+
>+	if (in_safe_mode || WARN_ON(!icl_tc_phy_status_complete(dig_port)))
>+		return TC_PORT_TBT_ALT;
>+
>+	mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT;
>+	if (live_status_mask) {
>+		enum tc_port_mode live_mode = fls(live_status_mask) - 1;
>+
>+		if (!WARN_ON(live_mode == TC_PORT_TBT_ALT))
>+			mode = live_mode;
>+	}
>+
>+	return mode;
>+}
>+
>+static enum tc_port_mode
>+intel_tc_port_get_target_mode(struct intel_digital_port *dig_port)
>+{
>+	u32 live_status_mask = tc_port_live_status_mask(dig_port);
>+
>+	if (live_status_mask)
>+		return fls(live_status_mask) - 1;
>+
>+	return icl_tc_phy_status_complete(dig_port) &&
>+	       dig_port->tc_legacy_port ? TC_PORT_LEGACY :
>+					  TC_PORT_TBT_ALT;
>+}
>+
>+static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
>+				     int required_lanes)
>+{
>+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>+	enum tc_port_mode old_tc_mode = dig_port->tc_mode;
>+
>+	intel_display_power_flush_work(i915);
>+	WARN_ON(intel_display_power_is_enabled(i915,
>+					       intel_aux_power_domain(dig_port)));
>+
>+	icl_tc_phy_disconnect(dig_port);
>+	icl_tc_phy_connect(dig_port, required_lanes);
>+
>+	DRM_DEBUG_KMS("Port %s: TC port mode reset (%s -> %s)\n",
>+		      dig_port->tc_port_name,
>+		      tc_port_mode_name(old_tc_mode),
>+		      tc_port_mode_name(dig_port->tc_mode));
>+}
>+
>+static void
>+intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
>+				 int refcount)
>+{
>+	WARN_ON(dig_port->tc_link_refcount);
>+	dig_port->tc_link_refcount = refcount;
>+}
>+
>+void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
>+{
>+	struct intel_encoder *encoder = &dig_port->base;
>+	int active_links = 0;
>+
>+	mutex_lock(&dig_port->tc_lock);
>+
>+	dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
>+	if (dig_port->dp.is_mst)
>+		active_links = intel_dp_mst_encoder_active_links(dig_port);
>+	else if (encoder->base.crtc)
>+		active_links = to_intel_crtc(encoder->base.crtc)->active;
>+
>+	if (active_links) {
>+		if (!icl_tc_phy_is_connected(dig_port))
>+			DRM_DEBUG_KMS("Port %s: PHY disconnected with %d active link(s)\n",
>+				      dig_port->tc_port_name, active_links);
>+		intel_tc_port_link_init_refcount(dig_port, active_links);
>+
>+		goto out;
>+	}
>+
>+	if (dig_port->tc_legacy_port)
>+		icl_tc_phy_connect(dig_port, 1);
>+
>+out:
>+	DRM_DEBUG_KMS("Port %s: sanitize mode (%s)\n",
>+		      dig_port->tc_port_name,
>+		      tc_port_mode_name(dig_port->tc_mode));
>+
>+	mutex_unlock(&dig_port->tc_lock);
>+}
>+
>+static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port)
>+{
>+	return intel_tc_port_get_target_mode(dig_port) != dig_port->tc_mode;
>+}
>+
>+/*
>+ * The type-C ports are different because even when they are connected, they may
>+ * not be available/usable by the graphics driver: see the comment on
>+ * icl_tc_phy_connect(). So in our driver instead of adding the additional
>+ * concept of "usable" and make everything check for "connected and usable" we
>+ * define a port as "connected" when it is not only connected, but also when it
>+ * is usable by the rest of the driver. That maintains the old assumption that
>+ * connected ports are usable, and avoids exposing to the users objects they
>+ * can't really use.
>+ */
>+bool intel_tc_port_connected(struct intel_digital_port *dig_port)
>+{
>+	bool is_connected;
>+
>+	intel_tc_port_lock(dig_port);
>+	is_connected = tc_port_live_status_mask(dig_port) &
>+		       BIT(dig_port->tc_mode);
>+	intel_tc_port_unlock(dig_port);
>+
>+	return is_connected;
>+}
>+
>+static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
>+				 int required_lanes)
>+{
>+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>+	intel_wakeref_t wakeref;
>+
>+	wakeref = intel_display_power_get(i915, POWER_DOMAIN_DISPLAY_CORE);
>+
>+	mutex_lock(&dig_port->tc_lock);
>+
>+	if (!dig_port->tc_link_refcount &&
>+	    intel_tc_port_needs_reset(dig_port))
>+		intel_tc_port_reset_mode(dig_port, required_lanes);
>+
>+	WARN_ON(dig_port->tc_lock_wakeref);
>+	dig_port->tc_lock_wakeref = wakeref;
>+}
>+
>+void intel_tc_port_lock(struct intel_digital_port *dig_port)
>+{
>+	__intel_tc_port_lock(dig_port, 1);
>+}
>+
>+void intel_tc_port_unlock(struct intel_digital_port *dig_port)
>+{
>+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>+	intel_wakeref_t wakeref = fetch_and_zero(&dig_port->tc_lock_wakeref);
>+
>+	mutex_unlock(&dig_port->tc_lock);
>+
>+	intel_display_power_put_async(i915, POWER_DOMAIN_DISPLAY_CORE,
>+				      wakeref);
>+}
>+
>+void intel_tc_port_get_link(struct intel_digital_port *dig_port,
>+			    int required_lanes)
>+{
>+	__intel_tc_port_lock(dig_port, required_lanes);
>+	dig_port->tc_link_refcount++;
>+	intel_tc_port_unlock(dig_port);
>+}
>+
>+void intel_tc_port_put_link(struct intel_digital_port *dig_port)
>+{
>+	mutex_lock(&dig_port->tc_lock);
>+	dig_port->tc_link_refcount--;
>+	mutex_unlock(&dig_port->tc_lock);
>+}
>+
>+void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
>+{
>+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>+	enum port port = dig_port->base.port;
>+	enum tc_port tc_port = intel_port_to_tc(i915, port);
>+
>+	if (WARN_ON(tc_port == PORT_TC_NONE))
>+		return;
>+
>+	snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
>+		 "%c/TC#%d", port_name(port), tc_port + 1);
>+
>+	mutex_init(&dig_port->tc_lock);
>+	dig_port->tc_legacy_port = is_legacy;
>+	dig_port->tc_link_refcount = 0;
>+	dig_port->tc_phy_fia = tc_port_to_fia(i915, tc_port);
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_tc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_tc.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_tc.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_tc.h	2019-08-31 15:01:12.020736183 -0500
>@@ -0,0 +1,35 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright Â© 2019 Intel Corporation
>+ */
>+
>+#ifndef __INTEL_TC_H__
>+#define __INTEL_TC_H__
>+
>+#include <linux/mutex.h>
>+#include <linux/types.h>
>+
>+#include "intel_drv.h"
>+
>+bool intel_tc_port_connected(struct intel_digital_port *dig_port);
>+u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
>+int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
>+void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
>+				      int required_lanes);
>+
>+void intel_tc_port_sanitize(struct intel_digital_port *dig_port);
>+void intel_tc_port_lock(struct intel_digital_port *dig_port);
>+void intel_tc_port_unlock(struct intel_digital_port *dig_port);
>+void intel_tc_port_get_link(struct intel_digital_port *dig_port,
>+			    int required_lanes);
>+void intel_tc_port_put_link(struct intel_digital_port *dig_port);
>+
>+static inline int intel_tc_port_ref_held(struct intel_digital_port *dig_port)
>+{
>+	return mutex_is_locked(&dig_port->tc_lock) ||
>+	       dig_port->tc_link_refcount;
>+}
>+
>+void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy);
>+
>+#endif /* __INTEL_TC_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_vbt_defs.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_vbt_defs.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_vbt_defs.h	2019-08-31 15:01:12.021736183 -0500
>@@ -310,10 +310,13 @@
> 	DDC_BUS_DDI_F,
> 	ICL_DDC_BUS_DDI_A = 0x1,
> 	ICL_DDC_BUS_DDI_B,
>+	TGL_DDC_BUS_DDI_C,
> 	ICL_DDC_BUS_PORT_1 = 0x4,
> 	ICL_DDC_BUS_PORT_2,
> 	ICL_DDC_BUS_PORT_3,
> 	ICL_DDC_BUS_PORT_4,
>+	TGL_DDC_BUS_PORT_5,
>+	TGL_DDC_BUS_PORT_6,
> 	MCC_DDC_BUS_DDI_A = 0x1,
> 	MCC_DDC_BUS_DDI_B,
> 	MCC_DDC_BUS_DDI_C = 0x4,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_vdsc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_vdsc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/intel_vdsc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/intel_vdsc.c	2019-08-31 15:01:12.021736183 -0500
>@@ -459,17 +459,23 @@
> enum intel_display_power_domain
> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> {
>+	struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
> 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> 
> 	/*
>-	 * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
>-	 * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
>+	 * On ICL VDSC/joining for eDP transcoder uses a separate power well,
>+	 * PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain.
> 	 * For any other transcoder, VDSC/joining uses the power well associated
> 	 * with the pipe/transcoder in use. Hence another reference on the
> 	 * transcoder power domain will suffice.
>+	 *
>+	 * On TGL we have the same mapping, but for transcoder A (the special
>+	 * TRANSCODER_EDP is gone).
> 	 */
>-	if (cpu_transcoder == TRANSCODER_EDP)
>-		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
>+	if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
>+		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
>+	else if (cpu_transcoder == TRANSCODER_EDP)
>+		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> 	else
> 		return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/Makefile	2019-08-31 15:01:12.014736182 -0500
>@@ -1,2 +1,6 @@
>+# For building individual subdir files on the command line
>+subdir-ccflags-y += -I$(srctree)/$(src)/..
>+
> # Extra header tests
>-include $(src)/Makefile.header-test
>+header-test-pattern-$(CONFIG_DRM_I915_WERROR) := *.h
>+header-test- := intel_vbt_defs.h
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/Makefile.header-test linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/Makefile.header-test
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/Makefile.header-test	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/Makefile.header-test	1969-12-31 18:00:00.000000000 -0600
>@@ -1,16 +0,0 @@
>-# SPDX-License-Identifier: MIT
>-# Copyright Â© 2019 Intel Corporation
>-
>-# Test the headers are compilable as standalone units
>-header_test := $(notdir $(filter-out %/intel_vbt_defs.h,$(wildcard $(src)/*.h)))
>-
>-quiet_cmd_header_test = HDRTEST $@
>-      cmd_header_test = echo "\#include \"$(<F)\"" > $@
>-
>-header_test_%.c: %.h
>-	$(call cmd,header_test)
>-
>-extra-$(CONFIG_DRM_I915_WERROR) += \
>-	$(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h)))
>-
>-clean-files += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.c,$(h)))
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/display/vlv_dsi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/vlv_dsi.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/display/vlv_dsi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/display/vlv_dsi.c	2019-08-31 15:01:12.021736183 -0500
>@@ -1644,7 +1644,7 @@
> 	return intel_dsi_get_panel_orientation(connector);
> }
> 
>-static void intel_dsi_add_properties(struct intel_connector *connector)
>+static void vlv_dsi_add_properties(struct intel_connector *connector)
> {
> 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> 
>@@ -1983,7 +1983,7 @@
> 	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
> 	intel_panel_setup_backlight(connector, INVALID_PIPE);
> 
>-	intel_dsi_add_properties(intel_connector);
>+	vlv_dsi_add_properties(intel_connector);
> 
> 	return;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_client_blt.c	2019-08-31 15:01:12.021736183 -0500
>@@ -72,7 +72,6 @@
> 	vma->ops = &proxy_vma_ops;
> 
> 	sleeve->vma = vma;
>-	sleeve->obj = i915_gem_object_get(obj);
> 	sleeve->pages = pages;
> 	sleeve->page_sizes = *page_sizes;
> 
>@@ -85,7 +84,6 @@
> 
> static void destroy_sleeve(struct i915_sleeve *sleeve)
> {
>-	i915_gem_object_put(sleeve->obj);
> 	kfree(sleeve);
> }
> 
>@@ -155,7 +153,7 @@
> {
> 	struct clear_pages_work *w = container_of(work, typeof(*w), work);
> 	struct drm_i915_private *i915 = w->ce->gem_context->i915;
>-	struct drm_i915_gem_object *obj = w->sleeve->obj;
>+	struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
> 	struct i915_vma *vma = w->sleeve->vma;
> 	struct i915_request *rq;
> 	int err = w->dma.error;
>@@ -164,11 +162,12 @@
> 		goto out_signal;
> 
> 	if (obj->cache_dirty) {
>-		obj->write_domain = 0;
> 		if (i915_gem_object_has_struct_page(obj))
> 			drm_clflush_sg(w->sleeve->pages);
> 		obj->cache_dirty = false;
> 	}
>+	obj->read_domains = I915_GEM_GPU_DOMAINS;
>+	obj->write_domain = 0;
> 
> 	/* XXX: we need to kill this */
> 	mutex_lock(&i915->drm.struct_mutex);
>@@ -193,10 +192,12 @@
> 			goto out_request;
> 	}
> 
>-	/* XXX: more feverish nightmares await */
>-	i915_vma_lock(vma);
>-	err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
>-	i915_vma_unlock(vma);
>+	/*
>+	 * w->dma is already exported via (vma|obj)->resv we need only
>+	 * keep track of the GPU activity within this vma/request, and
>+	 * propagate the signal from the request to w->dma.
>+	 */
>+	err = i915_active_ref(&vma->active, rq->fence.context, rq);
> 	if (err)
> 		goto out_request;
> 
>@@ -249,13 +250,11 @@
> 				     u32 value)
> {
> 	struct drm_i915_private *i915 = to_i915(obj->base.dev);
>-	struct i915_gem_context *ctx = ce->gem_context;
>-	struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
> 	struct clear_pages_work *work;
> 	struct i915_sleeve *sleeve;
> 	int err;
> 
>-	sleeve = create_sleeve(vm, obj, pages, page_sizes);
>+	sleeve = create_sleeve(ce->vm, obj, pages, page_sizes);
> 	if (IS_ERR(sleeve))
> 		return PTR_ERR(sleeve);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_context.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_context.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_context.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_context.c	2019-08-31 15:01:12.021736183 -0500
>@@ -316,7 +316,7 @@
> 	mutex_destroy(&ctx->engines_mutex);
> 
> 	if (ctx->timeline)
>-		i915_timeline_put(ctx->timeline);
>+		intel_timeline_put(ctx->timeline);
> 
> 	kfree(ctx->name);
> 	put_pid(ctx->pid);
>@@ -459,8 +459,7 @@
> 	i915_gem_context_set_recoverable(ctx);
> 
> 	ctx->ring_size = 4 * PAGE_SIZE;
>-	ctx->desc_template =
>-		default_desc_template(i915, &i915->mm.aliasing_ppgtt->vm);
>+	ctx->desc_template = default_desc_template(i915, NULL);
> 
> 	for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
> 		ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
>@@ -476,10 +475,18 @@
> __set_ppgtt(struct i915_gem_context *ctx, struct i915_address_space *vm)
> {
> 	struct i915_address_space *old = ctx->vm;
>+	struct i915_gem_engines_iter it;
>+	struct intel_context *ce;
> 
> 	ctx->vm = i915_vm_get(vm);
> 	ctx->desc_template = default_desc_template(ctx->i915, vm);
> 
>+	for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
>+		i915_vm_put(ce->vm);
>+		ce->vm = i915_vm_get(vm);
>+	}
>+	i915_gem_context_unlock_engines(ctx);
>+
> 	return old;
> }
> 
>@@ -528,9 +535,9 @@
> 	}
> 
> 	if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
>-		struct i915_timeline *timeline;
>+		struct intel_timeline *timeline;
> 
>-		timeline = i915_timeline_create(dev_priv, NULL);
>+		timeline = intel_timeline_create(&dev_priv->gt, NULL);
> 		if (IS_ERR(timeline)) {
> 			context_close(ctx);
> 			return ERR_CAST(timeline);
>@@ -644,20 +651,13 @@
> 	init_llist_head(&i915->contexts.free_list);
> }
> 
>-static bool needs_preempt_context(struct drm_i915_private *i915)
>-{
>-	return HAS_EXECLISTS(i915);
>-}
>-
> int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
> {
> 	struct i915_gem_context *ctx;
> 
> 	/* Reassure ourselves we are only called once */
> 	GEM_BUG_ON(dev_priv->kernel_context);
>-	GEM_BUG_ON(dev_priv->preempt_context);
> 
>-	intel_engine_init_ctx_wa(dev_priv->engine[RCS0]);
> 	init_contexts(dev_priv);
> 
> 	/* lowest priority; idle task */
>@@ -677,15 +677,6 @@
> 	GEM_BUG_ON(!atomic_read(&ctx->hw_id_pin_count));
> 	dev_priv->kernel_context = ctx;
> 
>-	/* highest priority; preempting task */
>-	if (needs_preempt_context(dev_priv)) {
>-		ctx = i915_gem_context_create_kernel(dev_priv, INT_MAX);
>-		if (!IS_ERR(ctx))
>-			dev_priv->preempt_context = ctx;
>-		else
>-			DRM_ERROR("Failed to create preempt context; disabling preemption\n");
>-	}
>-
> 	DRM_DEBUG_DRIVER("%s context support initialized\n",
> 			 DRIVER_CAPS(dev_priv)->has_logical_contexts ?
> 			 "logical" : "fake");
>@@ -696,8 +687,6 @@
> {
> 	lockdep_assert_held(&i915->drm.struct_mutex);
> 
>-	if (i915->preempt_context)
>-		destroy_kernel_context(&i915->preempt_context);
> 	destroy_kernel_context(&i915->kernel_context);
> 
> 	/* Must free all deferred contexts (via flush_workqueue) first */
>@@ -923,8 +912,12 @@
> 	if (!cb)
> 		return -ENOMEM;
> 
>-	i915_active_init(i915, &cb->base, cb_retire);
>-	i915_active_acquire(&cb->base);
>+	i915_active_init(i915, &cb->base, NULL, cb_retire);
>+	err = i915_active_acquire(&cb->base);
>+	if (err) {
>+		kfree(cb);
>+		return err;
>+	}
> 
> 	for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> 		struct i915_request *rq;
>@@ -1019,7 +1012,7 @@
> 
> static int emit_ppgtt_update(struct i915_request *rq, void *data)
> {
>-	struct i915_address_space *vm = rq->gem_context->vm;
>+	struct i915_address_space *vm = rq->hw_context->vm;
> 	struct intel_engine_cs *engine = rq->engine;
> 	u32 base = engine->mmio_base;
> 	u32 *cs;
>@@ -1128,9 +1121,8 @@
> 				   set_ppgtt_barrier,
> 				   old);
> 	if (err) {
>-		ctx->vm = old;
>-		ctx->desc_template = default_desc_template(ctx->i915, old);
>-		i915_vm_put(vm);
>+		i915_vm_put(__set_ppgtt(ctx, old));
>+		i915_vm_put(old);
> 	}
> 
> unlock:
>@@ -1187,26 +1179,11 @@
> 	if (IS_ERR(rq))
> 		return PTR_ERR(rq);
> 
>-	/* Queue this switch after all other activity by this context. */
>-	ret = i915_active_request_set(&ce->ring->timeline->last_request, rq);
>-	if (ret)
>-		goto out_add;
>-
>-	/*
>-	 * Guarantee context image and the timeline remains pinned until the
>-	 * modifying request is retired by setting the ce activity tracker.
>-	 *
>-	 * But we only need to take one pin on the account of it. Or in other
>-	 * words transfer the pinned ce object to tracked active request.
>-	 */
>-	GEM_BUG_ON(i915_active_is_idle(&ce->active));
>-	ret = i915_active_ref(&ce->active, rq->fence.context, rq);
>-	if (ret)
>-		goto out_add;
>-
>-	ret = gen8_emit_rpcs_config(rq, ce, sseu);
>+	/* Serialise with the remote context */
>+	ret = intel_context_prepare_remote_request(ce, rq);
>+	if (ret == 0)
>+		ret = gen8_emit_rpcs_config(rq, ce, sseu);
> 
>-out_add:
> 	i915_request_add(rq);
> 	return ret;
> }
>@@ -2015,8 +1992,8 @@
> 		GEM_BUG_ON(src->timeline == dst->timeline);
> 
> 		if (dst->timeline)
>-			i915_timeline_put(dst->timeline);
>-		dst->timeline = i915_timeline_get(src->timeline);
>+			intel_timeline_put(dst->timeline);
>+		dst->timeline = intel_timeline_get(src->timeline);
> 	}
> 
> 	return 0;
>@@ -2141,7 +2118,7 @@
> 	if (args->flags & I915_CONTEXT_CREATE_FLAGS_UNKNOWN)
> 		return -EINVAL;
> 
>-	ret = i915_terminally_wedged(i915);
>+	ret = intel_gt_terminally_wedged(&i915->gt);
> 	if (ret)
> 		return ret;
> 
>@@ -2287,8 +2264,8 @@
> 		args->size = 0;
> 		if (ctx->vm)
> 			args->value = ctx->vm->total;
>-		else if (to_i915(dev)->mm.aliasing_ppgtt)
>-			args->value = to_i915(dev)->mm.aliasing_ppgtt->vm.total;
>+		else if (to_i915(dev)->ggtt.alias)
>+			args->value = to_i915(dev)->ggtt.alias->vm.total;
> 		else
> 			args->value = to_i915(dev)->ggtt.vm.total;
> 		break;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_context.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_context.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_context.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_context.h	2019-08-31 15:01:12.021736183 -0500
>@@ -198,12 +198,6 @@
> }
> 
> static inline struct intel_context *
>-i915_gem_context_lookup_engine(struct i915_gem_context *ctx, unsigned int idx)
>-{
>-	return i915_gem_context_engines(ctx)->engines[idx];
>-}
>-
>-static inline struct intel_context *
> i915_gem_context_get_engine(struct i915_gem_context *ctx, unsigned int idx)
> {
> 	struct intel_context *ce = ERR_PTR(-EINVAL);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_context_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_context_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_context_types.h	2019-08-31 15:01:12.021736183 -0500
>@@ -26,7 +26,7 @@
> struct drm_i915_private;
> struct drm_i915_file_private;
> struct i915_address_space;
>-struct i915_timeline;
>+struct intel_timeline;
> struct intel_ring;
> 
> struct i915_gem_engines {
>@@ -77,7 +77,7 @@
> 	struct i915_gem_engines __rcu *engines;
> 	struct mutex engines_mutex; /* guards writes to engines */
> 
>-	struct i915_timeline *timeline;
>+	struct intel_timeline *timeline;
> 
> 	/**
> 	 * @vm: unique address space (GTT)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c	2019-08-31 15:01:12.021736183 -0500
>@@ -204,8 +204,7 @@
> 	.end_cpu_access = i915_gem_end_cpu_access,
> };
> 
>-struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
>-				      struct drm_gem_object *gem_obj, int flags)
>+struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags)
> {
> 	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
> 	DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
>@@ -222,7 +221,7 @@
> 			return ERR_PTR(ret);
> 	}
> 
>-	return drm_gem_dmabuf_export(dev, &exp_info);
>+	return drm_gem_dmabuf_export(gem_obj->dev, &exp_info);
> }
> 
> static int i915_gem_object_get_pages_dmabuf(struct drm_i915_gem_object *obj)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c	2019-08-31 15:01:12.243736202 -0500
>@@ -16,6 +16,7 @@
> 
> #include "gem/i915_gem_ioctls.h"
> #include "gt/intel_context.h"
>+#include "gt/intel_gt.h"
> #include "gt/intel_gt_pm.h"
> 
> #include "i915_gem_ioctls.h"
>@@ -222,7 +223,6 @@
> 	struct intel_engine_cs *engine; /** engine to queue the request to */
> 	struct intel_context *context; /* logical state for the request */
> 	struct i915_gem_context *gem_context; /** caller's context */
>-	struct i915_address_space *vm; /** GTT and vma for the request */
> 
> 	struct i915_request *request; /** our request to build */
> 	struct i915_vma *batch; /** identity of the batch obj/vma */
>@@ -696,7 +696,7 @@
> 
> 		case 1:
> 			/* Too fragmented, unbind everything and retry */
>-			err = i915_gem_evict_vm(eb->vm);
>+			err = i915_gem_evict_vm(eb->context->vm);
> 			if (err)
> 				return err;
> 			break;
>@@ -724,12 +724,8 @@
> 		return -ENOENT;
> 
> 	eb->gem_context = ctx;
>-	if (ctx->vm) {
>-		eb->vm = ctx->vm;
>+	if (ctx->vm)
> 		eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
>-	} else {
>-		eb->vm = &eb->i915->ggtt.vm;
>-	}
> 
> 	eb->context_flags = 0;
> 	if (test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags))
>@@ -831,7 +827,7 @@
> 			goto err_vma;
> 		}
> 
>-		vma = i915_vma_instance(obj, eb->vm, NULL);
>+		vma = i915_vma_instance(obj, eb->context->vm, NULL);
> 		if (IS_ERR(vma)) {
> 			err = PTR_ERR(vma);
> 			goto err_obj;
>@@ -994,7 +990,7 @@
> 	__i915_gem_object_flush_map(cache->rq->batch->obj, 0, cache->rq_size);
> 	i915_gem_object_unpin_map(cache->rq->batch->obj);
> 
>-	i915_gem_chipset_flush(cache->rq->i915);
>+	intel_gt_chipset_flush(cache->rq->engine->gt);
> 
> 	i915_request_add(cache->rq);
> 	cache->rq = NULL;
>@@ -1952,7 +1948,7 @@
> 	eb->exec = NULL;
> 
> 	/* Unconditionally flush any chipset caches (for streaming writes). */
>-	i915_gem_chipset_flush(eb->i915);
>+	intel_gt_chipset_flush(eb->engine->gt);
> 	return 0;
> 
> err_skip:
>@@ -2127,7 +2123,7 @@
> 	 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report
> 	 * EIO if the GPU is already wedged.
> 	 */
>-	err = i915_terminally_wedged(eb->i915);
>+	err = intel_gt_terminally_wedged(ce->engine->gt);
> 	if (err)
> 		return err;
> 
>@@ -2434,7 +2430,7 @@
> 	 * wakeref that we hold until the GPU has been idle for at least
> 	 * 100ms.
> 	 */
>-	intel_gt_pm_get(eb.i915);
>+	intel_gt_pm_get(&eb.i915->gt);
> 
> 	err = i915_mutex_lock_interruptible(dev);
> 	if (err)
>@@ -2604,7 +2600,7 @@
> err_unlock:
> 	mutex_unlock(&dev->struct_mutex);
> err_rpm:
>-	intel_gt_pm_put(eb.i915);
>+	intel_gt_pm_put(&eb.i915->gt);
> 	i915_gem_context_put(eb.gem_context);
> err_destroy:
> 	eb_destroy(&eb);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_mman.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_mman.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_mman.c	2019-08-31 15:01:12.022736183 -0500
>@@ -7,6 +7,8 @@
> #include <linux/mman.h>
> #include <linux/sizes.h>
> 
>+#include "gt/intel_gt.h"
>+
> #include "i915_drv.h"
> #include "i915_gem_gtt.h"
> #include "i915_gem_ioctls.h"
>@@ -246,7 +248,7 @@
> 
> 	wakeref = intel_runtime_pm_get(rpm);
> 
>-	srcu = i915_reset_trylock(i915);
>+	srcu = intel_gt_reset_trylock(ggtt->vm.gt);
> 	if (srcu < 0) {
> 		ret = srcu;
> 		goto err_rpm;
>@@ -326,7 +328,7 @@
> err_unlock:
> 	mutex_unlock(&dev->struct_mutex);
> err_reset:
>-	i915_reset_unlock(i915, srcu);
>+	intel_gt_reset_unlock(ggtt->vm.gt, srcu);
> err_rpm:
> 	intel_runtime_pm_put(rpm, wakeref);
> 	i915_gem_object_unpin_pages(obj);
>@@ -339,7 +341,7 @@
> 		 * fail). But any other -EIO isn't ours (e.g. swap in failure)
> 		 * and so needs to be reported.
> 		 */
>-		if (!i915_terminally_wedged(i915))
>+		if (!intel_gt_is_wedged(ggtt->vm.gt))
> 			return VM_FAULT_SIGBUS;
> 		/* else, fall through */
> 	case -EAGAIN:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_object_blt.c	2019-08-31 15:01:12.022736183 -0500
>@@ -47,15 +47,11 @@
> 			     struct intel_context *ce,
> 			     u32 value)
> {
>-	struct drm_i915_private *i915 = to_i915(obj->base.dev);
>-	struct i915_gem_context *ctx = ce->gem_context;
>-	struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
> 	struct i915_request *rq;
> 	struct i915_vma *vma;
> 	int err;
> 
>-	/* XXX: ce->vm please */
>-	vma = i915_vma_instance(obj, vm, NULL);
>+	vma = i915_vma_instance(obj, ce->vm, NULL);
> 	if (IS_ERR(vma))
> 		return PTR_ERR(vma);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_object.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_object.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_object.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_object.c	2019-08-31 15:01:12.022736183 -0500
>@@ -23,7 +23,7 @@
>  */
> 
> #include "display/intel_frontbuffer.h"
>-
>+#include "gt/intel_gt.h"
> #include "i915_drv.h"
> #include "i915_gem_clflush.h"
> #include "i915_gem_context.h"
>@@ -146,6 +146,19 @@
> 	}
> }
> 
>+static void __i915_gem_free_object_rcu(struct rcu_head *head)
>+{
>+	struct drm_i915_gem_object *obj =
>+		container_of(head, typeof(*obj), rcu);
>+	struct drm_i915_private *i915 = to_i915(obj->base.dev);
>+
>+	reservation_object_fini(&obj->base._resv);
>+	i915_gem_object_free(obj);
>+
>+	GEM_BUG_ON(!atomic_read(&i915->mm.free_count));
>+	atomic_dec(&i915->mm.free_count);
>+}
>+
> static void __i915_gem_free_objects(struct drm_i915_private *i915,
> 				    struct llist_node *freed)
> {
>@@ -160,7 +173,6 @@
> 
> 		mutex_lock(&i915->drm.struct_mutex);
> 
>-		GEM_BUG_ON(i915_gem_object_is_active(obj));
> 		list_for_each_entry_safe(vma, vn, &obj->vma.list, obj_link) {
> 			GEM_BUG_ON(i915_vma_is_active(vma));
> 			vma->flags &= ~I915_VMA_PIN_MASK;
>@@ -169,22 +181,6 @@
> 		GEM_BUG_ON(!list_empty(&obj->vma.list));
> 		GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma.tree));
> 
>-		/*
>-		 * This serializes freeing with the shrinker. Since the free
>-		 * is delayed, first by RCU then by the workqueue, we want the
>-		 * shrinker to be able to free pages of unreferenced objects,
>-		 * or else we may oom whilst there are plenty of deferred
>-		 * freed objects.
>-		 */
>-		if (i915_gem_object_has_pages(obj) &&
>-		    i915_gem_object_is_shrinkable(obj)) {
>-			unsigned long flags;
>-
>-			spin_lock_irqsave(&i915->mm.obj_lock, flags);
>-			list_del_init(&obj->mm.link);
>-			spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
>-		}
>-
> 		mutex_unlock(&i915->drm.struct_mutex);
> 
> 		GEM_BUG_ON(atomic_read(&obj->bind_count));
>@@ -192,25 +188,21 @@
> 		GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
> 		GEM_BUG_ON(!list_empty(&obj->lut_list));
> 
>-		if (obj->ops->release)
>-			obj->ops->release(obj);
>-
> 		atomic_set(&obj->mm.pages_pin_count, 0);
> 		__i915_gem_object_put_pages(obj, I915_MM_NORMAL);
> 		GEM_BUG_ON(i915_gem_object_has_pages(obj));
>+		bitmap_free(obj->bit_17);
> 
> 		if (obj->base.import_attach)
> 			drm_prime_gem_destroy(&obj->base, NULL);
> 
>-		drm_gem_object_release(&obj->base);
>+		drm_gem_free_mmap_offset(&obj->base);
> 
>-		bitmap_free(obj->bit_17);
>-		i915_gem_object_free(obj);
>-
>-		GEM_BUG_ON(!atomic_read(&i915->mm.free_count));
>-		atomic_dec(&i915->mm.free_count);
>+		if (obj->ops->release)
>+			obj->ops->release(obj);
> 
>-		cond_resched();
>+		/* But keep the pointer alive for RCU-protected lookups */
>+		call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
> 	}
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> }
>@@ -261,18 +253,34 @@
> 	spin_unlock(&i915->mm.free_lock);
> }
> 
>-static void __i915_gem_free_object_rcu(struct rcu_head *head)
>+void i915_gem_free_object(struct drm_gem_object *gem_obj)
> {
>-	struct drm_i915_gem_object *obj =
>-		container_of(head, typeof(*obj), rcu);
>+	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
> 	struct drm_i915_private *i915 = to_i915(obj->base.dev);
> 
> 	/*
>-	 * We reuse obj->rcu for the freed list, so we had better not treat
>-	 * it like a rcu_head from this point forwards. And we expect all
>-	 * objects to be freed via this path.
>+	 * Before we free the object, make sure any pure RCU-only
>+	 * read-side critical sections are complete, e.g.
>+	 * i915_gem_busy_ioctl(). For the corresponding synchronized
>+	 * lookup see i915_gem_object_lookup_rcu().
>+	 */
>+	atomic_inc(&i915->mm.free_count);
>+
>+	/*
>+	 * This serializes freeing with the shrinker. Since the free
>+	 * is delayed, first by RCU then by the workqueue, we want the
>+	 * shrinker to be able to free pages of unreferenced objects,
>+	 * or else we may oom whilst there are plenty of deferred
>+	 * freed objects.
> 	 */
>-	destroy_rcu_head(&obj->rcu);
>+	if (i915_gem_object_has_pages(obj) &&
>+	    i915_gem_object_is_shrinkable(obj)) {
>+		unsigned long flags;
>+
>+		spin_lock_irqsave(&i915->mm.obj_lock, flags);
>+		list_del_init(&obj->mm.link);
>+		spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
>+	}
> 
> 	/*
> 	 * Since we require blocking on struct_mutex to unbind the freed
>@@ -288,20 +296,6 @@
> 		queue_work(i915->wq, &i915->mm.free_work);
> }
> 
>-void i915_gem_free_object(struct drm_gem_object *gem_obj)
>-{
>-	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
>-
>-	/*
>-	 * Before we free the object, make sure any pure RCU-only
>-	 * read-side critical sections are complete, e.g.
>-	 * i915_gem_busy_ioctl(). For the corresponding synchronized
>-	 * lookup see i915_gem_object_lookup_rcu().
>-	 */
>-	atomic_inc(&to_i915(obj->base.dev)->mm.free_count);
>-	call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
>-}
>-
> static inline enum fb_op_origin
> fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain)
> {
>@@ -319,7 +313,6 @@
> i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
> 				   unsigned int flush_domains)
> {
>-	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
> 	struct i915_vma *vma;
> 
> 	assert_object_held(obj);
>@@ -329,7 +322,8 @@
> 
> 	switch (obj->write_domain) {
> 	case I915_GEM_DOMAIN_GTT:
>-		i915_gem_flush_ggtt_writes(dev_priv);
>+		for_each_ggtt_vma(vma, obj)
>+			intel_gt_flush_ggtt_writes(vma->vm->gt);
> 
> 		intel_fb_obj_flush(obj,
> 				   fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
>@@ -340,6 +334,7 @@
> 
> 			i915_vma_unset_ggtt_write(vma);
> 		}
>+
> 		break;
> 
> 	case I915_GEM_DOMAIN_WC:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_object.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_object.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_object.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_object.h	2019-08-31 15:01:12.022736183 -0500
>@@ -81,7 +81,7 @@
> }
> 
> __deprecated
>-extern struct drm_gem_object *
>+struct drm_gem_object *
> drm_gem_object_lookup(struct drm_file *file, u32 handle);
> 
> __attribute__((nonnull))
>@@ -159,12 +159,6 @@
> }
> 
> static inline bool
>-i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
>-{
>-	return READ_ONCE(obj->active_count);
>-}
>-
>-static inline bool
> i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj)
> {
> 	return READ_ONCE(obj->framebuffer_references);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_object_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_object_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_object_types.h	2019-08-31 15:01:12.022736183 -0500
>@@ -154,7 +154,6 @@
> 
> 	/** Count of VMA actually bound by this object */
> 	atomic_t bind_count;
>-	unsigned int active_count;
> 	/** Count of how many global VMA are currently pinned for use by HW */
> 	unsigned int pin_global;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_phys.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_phys.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_phys.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_phys.c	2019-08-31 15:01:12.022736183 -0500
>@@ -13,6 +13,7 @@
> #include <drm/drm_legacy.h> /* for drm_pci.h! */
> #include <drm/drm_pci.h>
> 
>+#include "gt/intel_gt.h"
> #include "i915_drv.h"
> #include "i915_gem_object.h"
> #include "i915_scatterlist.h"
>@@ -60,7 +61,7 @@
> 		vaddr += PAGE_SIZE;
> 	}
> 
>-	i915_gem_chipset_flush(to_i915(obj->base.dev));
>+	intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
> 
> 	st = kmalloc(sizeof(*st), GFP_KERNEL);
> 	if (!st) {
>@@ -132,16 +133,9 @@
> 	drm_pci_free(obj->base.dev, obj->phys_handle);
> }
> 
>-static void
>-i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
>-{
>-	i915_gem_object_unpin_pages(obj);
>-}
>-
> static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
> 	.get_pages = i915_gem_object_get_pages_phys,
> 	.put_pages = i915_gem_object_put_pages_phys,
>-	.release = i915_gem_object_release_phys,
> };
> 
> int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
>@@ -158,7 +152,7 @@
> 	if (obj->ops != &i915_gem_shmem_ops)
> 		return -EINVAL;
> 
>-	err = i915_gem_object_unbind(obj);
>+	err = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
> 	if (err)
> 		return err;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_pm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_pm.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_pm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_pm.c	2019-08-31 15:01:12.022736183 -0500
>@@ -5,6 +5,7 @@
>  */
> 
> #include "gem/i915_gem_pm.h"
>+#include "gt/intel_gt.h"
> #include "gt/intel_gt_pm.h"
> 
> #include "i915_drv.h"
>@@ -38,7 +39,7 @@
> 		i915_gem_batch_pool_fini(&engine->batch_pool);
> 	}
> 
>-	i915_timelines_park(i915);
>+	intel_timelines_park(i915);
> 	i915_vma_parked(i915);
> 
> 	i915_globals_park();
>@@ -54,7 +55,8 @@
> 	mutex_lock(&i915->drm.struct_mutex);
> 
> 	intel_wakeref_lock(&i915->gt.wakeref);
>-	park = !intel_wakeref_active(&i915->gt.wakeref) && !work_pending(work);
>+	park = (!intel_wakeref_is_active(&i915->gt.wakeref) &&
>+		!work_pending(work));
> 	intel_wakeref_unlock(&i915->gt.wakeref);
> 	if (park)
> 		i915_gem_park(i915);
>@@ -105,18 +107,18 @@
> 	return NOTIFY_OK;
> }
> 
>-static bool switch_to_kernel_context_sync(struct drm_i915_private *i915)
>+static bool switch_to_kernel_context_sync(struct intel_gt *gt)
> {
>-	bool result = !i915_terminally_wedged(i915);
>+	bool result = !intel_gt_is_wedged(gt);
> 
> 	do {
>-		if (i915_gem_wait_for_idle(i915,
>+		if (i915_gem_wait_for_idle(gt->i915,
> 					   I915_WAIT_LOCKED |
> 					   I915_WAIT_FOR_IDLE_BOOST,
> 					   I915_GEM_IDLE_TIMEOUT) == -ETIME) {
> 			/* XXX hide warning from gem_eio */
> 			if (i915_modparams.reset) {
>-				dev_err(i915->drm.dev,
>+				dev_err(gt->i915->drm.dev,
> 					"Failed to idle engines, declaring wedged!\n");
> 				GEM_TRACE_DUMP();
> 			}
>@@ -125,18 +127,18 @@
> 			 * Forcibly cancel outstanding work and leave
> 			 * the gpu quiet.
> 			 */
>-			i915_gem_set_wedged(i915);
>+			intel_gt_set_wedged(gt);
> 			result = false;
> 		}
>-	} while (i915_retire_requests(i915) && result);
>+	} while (i915_retire_requests(gt->i915) && result);
> 
>-	GEM_BUG_ON(i915->gt.awake);
>+	GEM_BUG_ON(gt->awake);
> 	return result;
> }
> 
> bool i915_gem_load_power_context(struct drm_i915_private *i915)
> {
>-	return switch_to_kernel_context_sync(i915);
>+	return switch_to_kernel_context_sync(&i915->gt);
> }
> 
> void i915_gem_suspend(struct drm_i915_private *i915)
>@@ -157,7 +159,7 @@
> 	 * state. Fortunately, the kernel_context is disposable and we do
> 	 * not rely on its state.
> 	 */
>-	switch_to_kernel_context_sync(i915);
>+	switch_to_kernel_context_sync(&i915->gt);
> 
> 	mutex_unlock(&i915->drm.struct_mutex);
> 
>@@ -168,11 +170,11 @@
> 	GEM_BUG_ON(i915->gt.awake);
> 	flush_work(&i915->gem.idle_work);
> 
>-	cancel_delayed_work_sync(&i915->gpu_error.hangcheck_work);
>+	cancel_delayed_work_sync(&i915->gt.hangcheck.work);
> 
> 	i915_gem_drain_freed_objects(i915);
> 
>-	intel_uc_suspend(i915);
>+	intel_uc_suspend(&i915->gt.uc);
> }
> 
> static struct drm_i915_gem_object *first_mm_object(struct list_head *list)
>@@ -237,7 +239,6 @@
> 	}
> 	spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
> 
>-	intel_uc_sanitize(i915);
> 	i915_gem_sanitize(i915);
> }
> 
>@@ -261,10 +262,10 @@
> 	 * guarantee that the context image is complete. So let's just reset
> 	 * it and start again.
> 	 */
>-	if (intel_gt_resume(i915))
>+	if (intel_gt_resume(&i915->gt))
> 		goto err_wedged;
> 
>-	intel_uc_resume(i915);
>+	intel_uc_resume(&i915->gt.uc);
> 
> 	/* Always reload a context for powersaving. */
> 	if (!i915_gem_load_power_context(i915))
>@@ -276,10 +277,10 @@
> 	return;
> 
> err_wedged:
>-	if (!i915_reset_failed(i915)) {
>+	if (!intel_gt_is_wedged(&i915->gt)) {
> 		dev_err(i915->drm.dev,
> 			"Failed to re-initialize GPU, declaring it wedged!\n");
>-		i915_gem_set_wedged(i915);
>+		intel_gt_set_wedged(&i915->gt);
> 	}
> 	goto out_unlock;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_shmem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_shmem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_shmem.c	2019-08-31 15:01:12.022736183 -0500
>@@ -414,6 +414,11 @@
> 	return 0;
> }
> 
>+static void shmem_release(struct drm_i915_gem_object *obj)
>+{
>+	fput(obj->base.filp);
>+}
>+
> const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
> 	.flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
> 		 I915_GEM_OBJECT_IS_SHRINKABLE,
>@@ -424,6 +429,8 @@
> 	.writeback = shmem_writeback,
> 
> 	.pwrite = shmem_pwrite,
>+
>+	.release = shmem_release,
> };
> 
> static int create_shmem(struct drm_i915_private *i915,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c	2019-08-31 15:01:12.022736183 -0500
>@@ -88,10 +88,18 @@
> 	return swap_available() || obj->mm.madv == I915_MADV_DONTNEED;
> }
> 
>-static bool unsafe_drop_pages(struct drm_i915_gem_object *obj)
>+static bool unsafe_drop_pages(struct drm_i915_gem_object *obj,
>+			      unsigned long shrink)
> {
>-	if (i915_gem_object_unbind(obj) == 0)
>+	unsigned long flags;
>+
>+	flags = 0;
>+	if (shrink & I915_SHRINK_ACTIVE)
>+		flags = I915_GEM_OBJECT_UNBIND_ACTIVE;
>+
>+	if (i915_gem_object_unbind(obj, flags) == 0)
> 		__i915_gem_object_put_pages(obj, I915_MM_SHRINKER);
>+
> 	return !i915_gem_object_has_pages(obj);
> }
> 
>@@ -169,7 +177,6 @@
> 	 */
> 
> 	trace_i915_gem_shrink(i915, target, shrink);
>-	i915_retire_requests(i915);
> 
> 	/*
> 	 * Unbinding of objects will require HW access; Let us not wake the
>@@ -230,8 +237,7 @@
> 				continue;
> 
> 			if (!(shrink & I915_SHRINK_ACTIVE) &&
>-			    (i915_gem_object_is_active(obj) ||
>-			     i915_gem_object_is_framebuffer(obj)))
>+			    i915_gem_object_is_framebuffer(obj))
> 				continue;
> 
> 			if (!(shrink & I915_SHRINK_BOUND) &&
>@@ -246,7 +252,7 @@
> 
> 			spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
> 
>-			if (unsafe_drop_pages(obj)) {
>+			if (unsafe_drop_pages(obj, shrink)) {
> 				/* May arrive from get_pages on another bo */
> 				mutex_lock_nested(&obj->mm.lock,
> 						  I915_MM_SHRINKER);
>@@ -269,8 +275,6 @@
> 	if (shrink & I915_SHRINK_BOUND)
> 		intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> 
>-	i915_retire_requests(i915);
>-
> 	shrinker_unlock(i915, unlock);
> 
> 	if (nr_scanned)
>@@ -427,12 +431,6 @@
> 	if (!shrinker_lock(i915, 0, &unlock))
> 		return NOTIFY_DONE;
> 
>-	/* Force everything onto the inactive lists */
>-	if (i915_gem_wait_for_idle(i915,
>-				   I915_WAIT_LOCKED,
>-				   MAX_SCHEDULE_TIMEOUT))
>-		goto out;
>-
> 	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
> 		freed_pages += i915_gem_shrink(i915, -1UL, NULL,
> 					       I915_SHRINK_BOUND |
>@@ -455,7 +453,6 @@
> 	}
> 	mutex_unlock(&i915->ggtt.vm.mutex);
> 
>-out:
> 	shrinker_unlock(i915, unlock);
> 
> 	*(unsigned long *)ptr += freed_pages;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_stolen.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_stolen.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_stolen.c	2019-08-31 15:01:12.022736183 -0500
>@@ -529,8 +529,6 @@
> 
> 	GEM_BUG_ON(!stolen);
> 
>-	__i915_gem_object_unpin_pages(obj);
>-
> 	i915_gem_stolen_remove_node(dev_priv, stolen);
> 	kfree(stolen);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_throttle.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_throttle.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_throttle.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_throttle.c	2019-08-31 15:01:12.022736183 -0500
>@@ -41,7 +41,7 @@
> 	long ret;
> 
> 	/* ABI: return -EIO if already wedged */
>-	ret = i915_terminally_wedged(to_i915(dev));
>+	ret = intel_gt_terminally_wedged(&to_i915(dev)->gt);
> 	if (ret)
> 		return ret;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_userptr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_userptr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_userptr.c	2019-08-31 15:01:12.023736183 -0500
>@@ -150,7 +150,8 @@
> 			}
> 		}
> 
>-		ret = i915_gem_object_unbind(obj);
>+		ret = i915_gem_object_unbind(obj,
>+					     I915_GEM_OBJECT_UNBIND_ACTIVE);
> 		if (ret == 0)
> 			ret = __i915_gem_object_put_pages(obj, I915_MM_SHRINKER);
> 		i915_gem_object_put(obj);
>@@ -662,6 +663,14 @@
> 	__i915_gem_object_release_shmem(obj, pages, true);
> 	i915_gem_gtt_finish_pages(obj, pages);
> 
>+	/*
>+	 * We always mark objects as dirty when they are used by the GPU,
>+	 * just in case. However, if we set the vma as being read-only we know
>+	 * that the object will never have been written to.
>+	 */
>+	if (i915_gem_object_is_readonly(obj))
>+		obj->mm.dirty = false;
>+
> 	for_each_sgt_page(page, sgt_iter, pages) {
> 		if (obj->mm.dirty)
> 			/*
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_wait.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_wait.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/i915_gem_wait.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/i915_gem_wait.c	2019-08-31 15:01:12.023736183 -0500
>@@ -35,7 +35,6 @@
> 				 unsigned int flags,
> 				 long timeout)
> {
>-	unsigned int seq = __read_seqcount_begin(&resv->seq);
> 	struct dma_fence *excl;
> 	bool prune_fences = false;
> 
>@@ -83,15 +82,12 @@
> 
> 	/*
> 	 * Opportunistically prune the fences iff we know they have *all* been
>-	 * signaled and that the reservation object has not been changed (i.e.
>-	 * no new fences have been added).
>+	 * signaled.
> 	 */
>-	if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) {
>-		if (reservation_object_trylock(resv)) {
>-			if (!__read_seqcount_retry(&resv->seq, seq))
>-				reservation_object_add_excl_fence(resv, NULL);
>-			reservation_object_unlock(resv);
>-		}
>+	if (prune_fences && reservation_object_trylock(resv)) {
>+		if (reservation_object_test_signaled_rcu(resv, true))
>+			reservation_object_add_excl_fence(resv, NULL);
>+		reservation_object_unlock(resv);
> 	}
> 
> 	return timeout;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/Makefile	2019-08-31 15:01:12.021736183 -0500
>@@ -1 +1,5 @@
>-include $(src)/Makefile.header-test # Extra header tests
>+# For building individual subdir files on the command line
>+subdir-ccflags-y += -I$(srctree)/$(src)/..
>+
>+# Extra header tests
>+header-test-pattern-$(CONFIG_DRM_I915_WERROR) := *.h
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/Makefile.header-test linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/Makefile.header-test
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/Makefile.header-test	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/Makefile.header-test	1969-12-31 18:00:00.000000000 -0600
>@@ -1,16 +0,0 @@
>-# SPDX-License-Identifier: MIT
>-# Copyright Â© 2019 Intel Corporation
>-
>-# Test the headers are compilable as standalone units
>-header_test := $(notdir $(wildcard $(src)/*.h))
>-
>-quiet_cmd_header_test = HDRTEST $@
>-      cmd_header_test = echo "\#include \"$(<F)\"" > $@
>-
>-header_test_%.c: %.h
>-	$(call cmd,header_test)
>-
>-extra-$(CONFIG_DRM_I915_WERROR) += \
>-	$(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h)))
>-
>-clean-files += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.c,$(h)))
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/huge_pages.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/huge_pages.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/huge_pages.c	2019-08-31 15:01:12.023736183 -0500
>@@ -10,6 +10,8 @@
> 
> #include "gem/i915_gem_pm.h"
> 
>+#include "gt/intel_gt.h"
>+
> #include "igt_gem_utils.h"
> #include "mock_context.h"
> 
>@@ -926,7 +928,7 @@
> 	}
> 
> 	*cmd = MI_BATCH_BUFFER_END;
>-	i915_gem_chipset_flush(i915);
>+	intel_gt_chipset_flush(vma->vm->gt);
> 
> 	i915_gem_object_unpin_map(obj);
> 
>@@ -1037,8 +1039,7 @@
> 			    u64 size, u64 offset,
> 			    u32 dword, u32 val)
> {
>-	struct drm_i915_private *i915 = to_i915(obj->base.dev);
>-	struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
>+	struct i915_address_space *vm = ctx->vm ?: &engine->gt->ggtt->vm;
> 	unsigned int flags = PIN_USER | PIN_OFFSET_FIXED;
> 	struct i915_vma *vma;
> 	int err;
>@@ -1421,6 +1422,9 @@
> 	struct drm_i915_gem_object *obj;
> 	struct i915_vma *vma;
> 	unsigned int flags = PIN_USER | PIN_OFFSET_FIXED;
>+	struct intel_engine_cs *engine;
>+	enum intel_engine_id id;
>+	unsigned int n;
> 	int first, last;
> 	int err;
> 
>@@ -1518,11 +1522,20 @@
> 	 * land in the now stale 2M page.
> 	 */
> 
>-	err = gpu_write(vma, ctx, dev_priv->engine[RCS0], 0, 0xdeadbeaf);
>-	if (err)
>-		goto out_unpin;
>+	n = 0;
>+	for_each_engine(engine, dev_priv, id) {
>+		if (!intel_engine_can_store_dword(engine))
>+			continue;
> 
>-	err = cpu_check(obj, 0, 0xdeadbeaf);
>+		err = gpu_write(vma, ctx, engine, n++, 0xdeadbeaf);
>+		if (err)
>+			goto out_unpin;
>+	}
>+	while (n--) {
>+		err = cpu_check(obj, n, 0xdeadbeaf);
>+		if (err)
>+			goto out_unpin;
>+	}
> 
> out_unpin:
> 	i915_vma_unpin(vma);
>@@ -1598,8 +1611,11 @@
> 	struct drm_i915_private *i915 = ctx->i915;
> 	struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
> 	struct drm_i915_gem_object *obj;
>+	struct intel_engine_cs *engine;
>+	enum intel_engine_id id;
> 	struct i915_vma *vma;
> 	unsigned int flags = PIN_USER;
>+	unsigned int n;
> 	int err;
> 
> 	/*
>@@ -1635,9 +1651,15 @@
> 	if (err)
> 		goto out_unpin;
> 
>-	err = gpu_write(vma, ctx, i915->engine[RCS0], 0, 0xdeadbeaf);
>-	if (err)
>-		goto out_unpin;
>+	n = 0;
>+	for_each_engine(engine, i915, id) {
>+		if (!intel_engine_can_store_dword(engine))
>+			continue;
>+
>+		err = gpu_write(vma, ctx, engine, n++, 0xdeadbeaf);
>+		if (err)
>+			goto out_unpin;
>+	}
> 
> 	i915_vma_unpin(vma);
> 
>@@ -1662,7 +1684,12 @@
> 	if (err)
> 		goto out_close;
> 
>-	err = cpu_check(obj, 0, 0xdeadbeaf);
>+	while (n--) {
>+		err = cpu_check(obj, n, 0xdeadbeaf);
>+		if (err)
>+			goto out_unpin;
>+	}
>+
> 
> out_unpin:
> 	i915_vma_unpin(vma);
>@@ -1726,7 +1753,7 @@
> 	return err;
> }
> 
>-int i915_gem_huge_page_live_selftests(struct drm_i915_private *dev_priv)
>+int i915_gem_huge_page_live_selftests(struct drm_i915_private *i915)
> {
> 	static const struct i915_subtest tests[] = {
> 		SUBTEST(igt_shrink_thp),
>@@ -1741,22 +1768,22 @@
> 	intel_wakeref_t wakeref;
> 	int err;
> 
>-	if (!HAS_PPGTT(dev_priv)) {
>+	if (!HAS_PPGTT(i915)) {
> 		pr_info("PPGTT not supported, skipping live-selftests\n");
> 		return 0;
> 	}
> 
>-	if (i915_terminally_wedged(dev_priv))
>+	if (intel_gt_is_wedged(&i915->gt))
> 		return 0;
> 
>-	file = mock_file(dev_priv);
>+	file = mock_file(i915);
> 	if (IS_ERR(file))
> 		return PTR_ERR(file);
> 
>-	mutex_lock(&dev_priv->drm.struct_mutex);
>-	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>+	mutex_lock(&i915->drm.struct_mutex);
>+	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> 
>-	ctx = live_context(dev_priv, file);
>+	ctx = live_context(i915, file);
> 	if (IS_ERR(ctx)) {
> 		err = PTR_ERR(ctx);
> 		goto out_unlock;
>@@ -1768,10 +1795,10 @@
> 	err = i915_subtests(tests, ctx);
> 
> out_unlock:
>-	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>-	mutex_unlock(&dev_priv->drm.struct_mutex);
>+	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>+	mutex_unlock(&i915->drm.struct_mutex);
> 
>-	mock_file_free(dev_priv, file);
>+	mock_file_free(i915, file);
> 
> 	return err;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c	2019-08-31 15:01:12.023736183 -0500
>@@ -5,14 +5,16 @@
> 
> #include "i915_selftest.h"
> 
>+#include "gt/intel_gt.h"
>+
> #include "selftests/igt_flush_test.h"
> #include "selftests/mock_drm.h"
> #include "mock_context.h"
> 
> static int igt_client_fill(void *arg)
> {
>-	struct intel_context *ce = arg;
>-	struct drm_i915_private *i915 = ce->gem_context->i915;
>+	struct drm_i915_private *i915 = arg;
>+	struct intel_context *ce = i915->engine[BCS0]->kernel_context;
> 	struct drm_i915_gem_object *obj;
> 	struct rnd_state prng;
> 	IGT_TIMEOUT(end);
>@@ -63,17 +65,6 @@
> 		if (err)
> 			goto err_unpin;
> 
>-		/*
>-		 * XXX: For now do the wait without the object resv lock to
>-		 * ensure we don't deadlock.
>-		 */
>-		err = i915_gem_object_wait(obj,
>-					   I915_WAIT_INTERRUPTIBLE |
>-					   I915_WAIT_ALL,
>-					   MAX_SCHEDULE_TIMEOUT);
>-		if (err)
>-			goto err_unpin;
>-
> 		i915_gem_object_lock(obj);
> 		err = i915_gem_object_set_to_cpu_domain(obj, false);
> 		i915_gem_object_unlock(obj);
>@@ -100,11 +91,6 @@
> err_put:
> 	i915_gem_object_put(obj);
> err_flush:
>-	mutex_lock(&i915->drm.struct_mutex);
>-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>-		err = -EIO;
>-	mutex_unlock(&i915->drm.struct_mutex);
>-
> 	if (err == -ENOMEM)
> 		err = 0;
> 
>@@ -117,11 +103,11 @@
> 		SUBTEST(igt_client_fill),
> 	};
> 
>-	if (i915_terminally_wedged(i915))
>+	if (intel_gt_is_wedged(&i915->gt))
> 		return 0;
> 
> 	if (!HAS_ENGINE(i915, BCS0))
> 		return 0;
> 
>-	return i915_subtests(tests, i915->engine[BCS0]->kernel_context);
>+	return i915_live_subtests(tests, i915);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c	2019-08-31 15:01:12.023736183 -0500
>@@ -6,6 +6,8 @@
> 
> #include <linux/prime_numbers.h>
> 
>+#include "gt/intel_gt.h"
>+
> #include "i915_selftest.h"
> #include "selftests/i915_random.h"
> 
>@@ -242,12 +244,15 @@
> 
> static bool needs_fence_registers(struct drm_i915_private *i915)
> {
>-	return !i915_terminally_wedged(i915);
>+	return !intel_gt_is_wedged(&i915->gt);
> }
> 
> static bool needs_mi_store_dword(struct drm_i915_private *i915)
> {
>-	if (i915_terminally_wedged(i915))
>+	if (intel_gt_is_wedged(&i915->gt))
>+		return false;
>+
>+	if (!HAS_ENGINE(i915, RCS0))
> 		return false;
> 
> 	return intel_engine_can_store_dword(i915->engine[RCS0]);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c	2019-08-31 15:01:12.023736183 -0500
>@@ -7,6 +7,7 @@
> #include <linux/prime_numbers.h>
> 
> #include "gem/i915_gem_pm.h"
>+#include "gt/intel_gt.h"
> #include "gt/intel_reset.h"
> #include "i915_selftest.h"
> 
>@@ -31,7 +32,6 @@
> 	struct intel_engine_cs *engine;
> 	struct i915_gem_context **ctx;
> 	enum intel_engine_id id;
>-	intel_wakeref_t wakeref;
> 	struct igt_live_test t;
> 	struct drm_file *file;
> 	unsigned long n;
>@@ -53,7 +53,6 @@
> 		return PTR_ERR(file);
> 
> 	mutex_lock(&i915->drm.struct_mutex);
>-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> 
> 	ctx = kcalloc(nctx, sizeof(*ctx), GFP_KERNEL);
> 	if (!ctx) {
>@@ -85,7 +84,7 @@
> 		}
> 		if (i915_request_wait(rq, 0, HZ / 5) < 0) {
> 			pr_err("Failed to populated %d contexts\n", nctx);
>-			i915_gem_set_wedged(i915);
>+			intel_gt_set_wedged(&i915->gt);
> 			err = -EIO;
> 			goto out_unlock;
> 		}
>@@ -129,7 +128,7 @@
> 			if (i915_request_wait(rq, 0, HZ / 5) < 0) {
> 				pr_err("Switching between %ld contexts timed out\n",
> 				       prime);
>-				i915_gem_set_wedged(i915);
>+				intel_gt_set_wedged(&i915->gt);
> 				break;
> 			}
> 
>@@ -152,7 +151,6 @@
> 	}
> 
> out_unlock:
>-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> 	mutex_unlock(&i915->drm.struct_mutex);
> 	mock_file_free(i915, file);
> 	return err;
>@@ -237,8 +235,7 @@
> 		    struct intel_engine_cs *engine,
> 		    unsigned int dw)
> {
>-	struct drm_i915_private *i915 = to_i915(obj->base.dev);
>-	struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
>+	struct i915_address_space *vm = ctx->vm ?: &engine->gt->ggtt->vm;
> 	struct i915_request *rq;
> 	struct i915_vma *vma;
> 	struct i915_vma *batch;
>@@ -431,6 +428,9 @@
> 	u64 size;
> 	int err;
> 
>+	/* Keep in GEM's good graces */
>+	i915_retire_requests(ctx->i915);
>+
> 	size = min(vm->total / 2, 1024ull * DW_PER_PAGE * PAGE_SIZE);
> 	size = round_down(size, DW_PER_PAGE * PAGE_SIZE);
> 
>@@ -507,7 +507,6 @@
> 		dw = 0;
> 		while (!time_after(jiffies, end_time)) {
> 			struct i915_gem_context *ctx;
>-			intel_wakeref_t wakeref;
> 
> 			ctx = live_context(i915, file);
> 			if (IS_ERR(ctx)) {
>@@ -523,8 +522,7 @@
> 				}
> 			}
> 
>-			with_intel_runtime_pm(&i915->runtime_pm, wakeref)
>-				err = gpu_fill(obj, ctx, engine, dw);
>+			err = gpu_fill(obj, ctx, engine, dw);
> 			if (err) {
> 				pr_err("Failed to fill dword %lu [%lu/%lu] with gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
> 				       ndwords, dw, max_dwords(obj),
>@@ -565,6 +563,8 @@
> 		mock_file_free(i915, file);
> 		if (err)
> 			return err;
>+
>+		i915_gem_drain_freed_objects(i915);
> 	}
> 
> 	return 0;
>@@ -623,7 +623,6 @@
> 		ncontexts = 0;
> 		while (!time_after(jiffies, end_time)) {
> 			struct i915_gem_context *ctx;
>-			intel_wakeref_t wakeref;
> 
> 			ctx = kernel_context(i915);
> 			if (IS_ERR(ctx)) {
>@@ -642,9 +641,7 @@
> 				}
> 			}
> 
>-			err = 0;
>-			with_intel_runtime_pm(&i915->runtime_pm, wakeref)
>-				err = gpu_fill(obj, ctx, engine, dw);
>+			err = gpu_fill(obj, ctx, engine, dw);
> 			if (err) {
> 				pr_err("Failed to fill dword %lu [%lu/%lu] with gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
> 				       ndwords, dw, max_dwords(obj),
>@@ -678,6 +675,10 @@
> 
> 			dw += rem;
> 		}
>+
>+		mutex_unlock(&i915->drm.struct_mutex);
>+		i915_gem_drain_freed_objects(i915);
>+		mutex_lock(&i915->drm.struct_mutex);
> 	}
> out_test:
> 	if (igt_live_test_end(&t))
>@@ -746,7 +747,7 @@
> 
> 	GEM_BUG_ON(!intel_engine_can_store_dword(ce->engine));
> 
>-	vma = i915_vma_instance(obj, ce->gem_context->vm, NULL);
>+	vma = i915_vma_instance(obj, ce->vm, NULL);
> 	if (IS_ERR(vma))
> 		return PTR_ERR(vma);
> 
>@@ -956,7 +957,7 @@
> 	int ret = 0;
> 
> 	if (flags & TEST_RESET) {
>-		ret = i915_reset_engine(ce->engine, "sseu");
>+		ret = intel_engine_reset(ce->engine, "sseu");
> 		if (ret)
> 			goto out;
> 	}
>@@ -1025,35 +1026,33 @@
> 	       unsigned int flags)
> {
> 	struct intel_engine_cs *engine = i915->engine[RCS0];
>-	struct intel_sseu default_sseu = engine->sseu;
> 	struct drm_i915_gem_object *obj;
> 	struct i915_gem_context *ctx;
> 	struct intel_context *ce;
> 	struct intel_sseu pg_sseu;
>-	intel_wakeref_t wakeref;
> 	struct drm_file *file;
> 	int ret;
> 
>-	if (INTEL_GEN(i915) < 9)
>+	if (INTEL_GEN(i915) < 9 || !engine)
> 		return 0;
> 
> 	if (!RUNTIME_INFO(i915)->sseu.has_slice_pg)
> 		return 0;
> 
>-	if (hweight32(default_sseu.slice_mask) < 2)
>+	if (hweight32(engine->sseu.slice_mask) < 2)
> 		return 0;
> 
> 	/*
> 	 * Gen11 VME friendly power-gated configuration with half enabled
> 	 * sub-slices.
> 	 */
>-	pg_sseu = default_sseu;
>+	pg_sseu = engine->sseu;
> 	pg_sseu.slice_mask = 1;
> 	pg_sseu.subslice_mask =
>-		~(~0 << (hweight32(default_sseu.subslice_mask) / 2));
>+		~(~0 << (hweight32(engine->sseu.subslice_mask) / 2));
> 
> 	pr_info("SSEU subtest '%s', flags=%x, def_slices=%u, pg_slices=%u\n",
>-		name, flags, hweight32(default_sseu.slice_mask),
>+		name, flags, hweight32(engine->sseu.slice_mask),
> 		hweight32(pg_sseu.slice_mask));
> 
> 	file = mock_file(i915);
>@@ -1061,7 +1060,7 @@
> 		return PTR_ERR(file);
> 
> 	if (flags & TEST_RESET)
>-		igt_global_reset_lock(i915);
>+		igt_global_reset_lock(&i915->gt);
> 
> 	mutex_lock(&i915->drm.struct_mutex);
> 
>@@ -1078,12 +1077,10 @@
> 		goto out_unlock;
> 	}
> 
>-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>-
> 	ce = i915_gem_context_get_engine(ctx, RCS0);
> 	if (IS_ERR(ce)) {
> 		ret = PTR_ERR(ce);
>-		goto out_rpm;
>+		goto out_put;
> 	}
> 
> 	ret = intel_context_pin(ce);
>@@ -1091,7 +1088,7 @@
> 		goto out_context;
> 
> 	/* First set the default mask. */
>-	ret = __sseu_test(i915, name, flags, ce, obj, default_sseu);
>+	ret = __sseu_test(i915, name, flags, ce, obj, engine->sseu);
> 	if (ret)
> 		goto out_fail;
> 
>@@ -1101,7 +1098,7 @@
> 		goto out_fail;
> 
> 	/* Back to defaults. */
>-	ret = __sseu_test(i915, name, flags, ce, obj, default_sseu);
>+	ret = __sseu_test(i915, name, flags, ce, obj, engine->sseu);
> 	if (ret)
> 		goto out_fail;
> 
>@@ -1117,15 +1114,14 @@
> 	intel_context_unpin(ce);
> out_context:
> 	intel_context_put(ce);
>-out_rpm:
>-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>+out_put:
> 	i915_gem_object_put(obj);
> 
> out_unlock:
> 	mutex_unlock(&i915->drm.struct_mutex);
> 
> 	if (flags & TEST_RESET)
>-		igt_global_reset_unlock(i915);
>+		igt_global_reset_unlock(&i915->gt);
> 
> 	mock_file_free(i915, file);
> 
>@@ -1194,7 +1190,7 @@
> 		goto out_unlock;
> 	}
> 
>-	vm = ctx->vm ?: &i915->mm.aliasing_ppgtt->vm;
>+	vm = ctx->vm ?: &i915->ggtt.alias->vm;
> 	if (!vm || !vm->has_read_only) {
> 		err = 0;
> 		goto out_unlock;
>@@ -1207,8 +1203,6 @@
> 		unsigned int id;
> 
> 		for_each_engine(engine, i915, id) {
>-			intel_wakeref_t wakeref;
>-
> 			if (!intel_engine_can_store_dword(engine))
> 				continue;
> 
>@@ -1223,9 +1217,7 @@
> 					i915_gem_object_set_readonly(obj);
> 			}
> 
>-			err = 0;
>-			with_intel_runtime_pm(&i915->runtime_pm, wakeref)
>-				err = gpu_fill(obj, ctx, engine, dw);
>+			err = gpu_fill(obj, ctx, engine, dw);
> 			if (err) {
> 				pr_err("Failed to fill dword %lu [%lu/%lu] with gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
> 				       ndwords, dw, max_dwords(obj),
>@@ -1488,7 +1480,6 @@
> 	struct drm_i915_private *i915 = arg;
> 	struct i915_gem_context *ctx_a, *ctx_b;
> 	struct intel_engine_cs *engine;
>-	intel_wakeref_t wakeref;
> 	struct igt_live_test t;
> 	struct drm_file *file;
> 	I915_RND_STATE(prng);
>@@ -1535,8 +1526,6 @@
> 	GEM_BUG_ON(ctx_b->vm->total != vm_total);
> 	vm_total -= I915_GTT_PAGE_SIZE;
> 
>-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>-
> 	count = 0;
> 	for_each_engine(engine, i915, id) {
> 		IGT_TIMEOUT(end_time);
>@@ -1551,7 +1540,7 @@
> 
> 			div64_u64_rem(i915_prandom_u64_state(&prng),
> 				      vm_total, &offset);
>-			offset &= -sizeof(u32);
>+			offset = round_down(offset, alignof_dword);
> 			offset += I915_GTT_PAGE_SIZE;
> 
> 			err = write_to_scratch(ctx_a, engine,
>@@ -1560,7 +1549,7 @@
> 				err = read_from_scratch(ctx_b, engine,
> 							offset, &value);
> 			if (err)
>-				goto out_rpm;
>+				goto out_unlock;
> 
> 			if (value) {
> 				pr_err("%s: Read %08x from scratch (offset 0x%08x_%08x), after %lu reads!\n",
>@@ -1569,7 +1558,7 @@
> 				       lower_32_bits(offset),
> 				       this);
> 				err = -EINVAL;
>-				goto out_rpm;
>+				goto out_unlock;
> 			}
> 
> 			this++;
>@@ -1579,8 +1568,6 @@
> 	pr_info("Checked %lu scratch offsets across %d engines\n",
> 		count, RUNTIME_INFO(i915)->num_engines);
> 
>-out_rpm:
>-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> out_unlock:
> 	if (igt_live_test_end(&t))
> 		err = -EIO;
>@@ -1736,7 +1723,7 @@
> 	return err;
> }
> 
>-int i915_gem_context_live_selftests(struct drm_i915_private *dev_priv)
>+int i915_gem_context_live_selftests(struct drm_i915_private *i915)
> {
> 	static const struct i915_subtest tests[] = {
> 		SUBTEST(live_nop_switch),
>@@ -1747,8 +1734,8 @@
> 		SUBTEST(igt_vm_isolation),
> 	};
> 
>-	if (i915_terminally_wedged(dev_priv))
>+	if (intel_gt_is_wedged(&i915->gt))
> 		return 0;
> 
>-	return i915_subtests(tests, dev_priv);
>+	return i915_live_subtests(tests, i915);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c	2019-08-31 15:01:12.023736183 -0500
>@@ -20,7 +20,7 @@
> 	if (IS_ERR(obj))
> 		return PTR_ERR(obj);
> 
>-	dmabuf = i915_gem_prime_export(&i915->drm, &obj->base, 0);
>+	dmabuf = i915_gem_prime_export(&obj->base, 0);
> 	i915_gem_object_put(obj);
> 	if (IS_ERR(dmabuf)) {
> 		pr_err("i915_gem_prime_export failed with err=%d\n",
>@@ -44,7 +44,7 @@
> 	if (IS_ERR(obj))
> 		return PTR_ERR(obj);
> 
>-	dmabuf = i915_gem_prime_export(&i915->drm, &obj->base, 0);
>+	dmabuf = i915_gem_prime_export(&obj->base, 0);
> 	if (IS_ERR(dmabuf)) {
> 		pr_err("i915_gem_prime_export failed with err=%d\n",
> 		       (int)PTR_ERR(dmabuf));
>@@ -219,7 +219,7 @@
> 	if (IS_ERR(obj))
> 		return PTR_ERR(obj);
> 
>-	dmabuf = i915_gem_prime_export(&i915->drm, &obj->base, 0);
>+	dmabuf = i915_gem_prime_export(&obj->base, 0);
> 	if (IS_ERR(dmabuf)) {
> 		pr_err("i915_gem_prime_export failed with err=%d\n",
> 		       (int)PTR_ERR(dmabuf));
>@@ -266,7 +266,7 @@
> 	if (IS_ERR(obj))
> 		return PTR_ERR(obj);
> 
>-	dmabuf = i915_gem_prime_export(&i915->drm, &obj->base, 0);
>+	dmabuf = i915_gem_prime_export(&obj->base, 0);
> 	i915_gem_object_put(obj);
> 	if (IS_ERR(dmabuf)) {
> 		err = PTR_ERR(dmabuf);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c	2019-08-31 15:01:12.023736183 -0500
>@@ -6,6 +6,7 @@
> 
> #include <linux/prime_numbers.h>
> 
>+#include "gt/intel_gt.h"
> #include "gt/intel_gt_pm.h"
> #include "huge_gem_object.h"
> #include "i915_selftest.h"
>@@ -143,7 +144,7 @@
> 		if (offset >= obj->base.size)
> 			continue;
> 
>-		i915_gem_flush_ggtt_writes(to_i915(obj->base.dev));
>+		intel_gt_flush_ggtt_writes(&to_i915(obj->base.dev)->gt);
> 
> 		p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
> 		cpu = kmap(p) + offset_in_page(offset);
>@@ -327,7 +328,8 @@
> static int make_obj_busy(struct drm_i915_gem_object *obj)
> {
> 	struct drm_i915_private *i915 = to_i915(obj->base.dev);
>-	struct i915_request *rq;
>+	struct intel_engine_cs *engine;
>+	enum intel_engine_id id;
> 	struct i915_vma *vma;
> 	int err;
> 
>@@ -339,17 +341,21 @@
> 	if (err)
> 		return err;
> 
>-	rq = i915_request_create(i915->engine[RCS0]->kernel_context);
>-	if (IS_ERR(rq)) {
>-		i915_vma_unpin(vma);
>-		return PTR_ERR(rq);
>-	}
>+	for_each_engine(engine, i915, id) {
>+		struct i915_request *rq;
>+
>+		rq = i915_request_create(engine->kernel_context);
>+		if (IS_ERR(rq)) {
>+			i915_vma_unpin(vma);
>+			return PTR_ERR(rq);
>+		}
> 
>-	i915_vma_lock(vma);
>-	err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
>-	i915_vma_unlock(vma);
>+		i915_vma_lock(vma);
>+		err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
>+		i915_vma_unlock(vma);
> 
>-	i915_request_add(rq);
>+		i915_request_add(rq);
>+	}
> 
> 	i915_vma_unpin(vma);
> 	i915_gem_object_put(obj); /* leave it only alive via its active ref */
>@@ -378,7 +384,7 @@
> {
> 	i915_gem_shrinker_unregister(i915);
> 
>-	intel_gt_pm_get(i915);
>+	intel_gt_pm_get(&i915->gt);
> 
> 	cancel_delayed_work_sync(&i915->gem.retire_work);
> 	flush_work(&i915->gem.idle_work);
>@@ -386,7 +392,7 @@
> 
> static void restore_retire_worker(struct drm_i915_private *i915)
> {
>-	intel_gt_pm_put(i915);
>+	intel_gt_pm_put(&i915->gt);
> 
> 	mutex_lock(&i915->drm.struct_mutex);
> 	igt_flush_test(i915, I915_WAIT_LOCKED);
>@@ -395,6 +401,18 @@
> 	i915_gem_shrinker_register(i915);
> }
> 
>+static void mmap_offset_lock(struct drm_i915_private *i915)
>+	__acquires(&i915->drm.vma_offset_manager->vm_lock)
>+{
>+	write_lock(&i915->drm.vma_offset_manager->vm_lock);
>+}
>+
>+static void mmap_offset_unlock(struct drm_i915_private *i915)
>+	__releases(&i915->drm.vma_offset_manager->vm_lock)
>+{
>+	write_unlock(&i915->drm.vma_offset_manager->vm_lock);
>+}
>+
> static int igt_mmap_offset_exhaustion(void *arg)
> {
> 	struct drm_i915_private *i915 = arg;
>@@ -413,7 +431,9 @@
> 	drm_mm_for_each_hole(hole, mm, hole_start, hole_end) {
> 		resv.start = hole_start;
> 		resv.size = hole_end - hole_start - 1; /* PAGE_SIZE units */
>+		mmap_offset_lock(i915);
> 		err = drm_mm_reserve_node(mm, &resv);
>+		mmap_offset_unlock(i915);
> 		if (err) {
> 			pr_err("Failed to trim VMA manager, err=%d\n", err);
> 			goto out_park;
>@@ -458,7 +478,7 @@
> 
> 	/* Now fill with busy dead objects that we expect to reap */
> 	for (loop = 0; loop < 3; loop++) {
>-		if (i915_terminally_wedged(i915))
>+		if (intel_gt_is_wedged(&i915->gt))
> 			break;
> 
> 		obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
>@@ -474,19 +494,12 @@
> 			pr_err("[loop %d] Failed to busy the object\n", loop);
> 			goto err_obj;
> 		}
>-
>-		/* NB we rely on the _active_ reference to access obj now */
>-		GEM_BUG_ON(!i915_gem_object_is_active(obj));
>-		err = create_mmap_offset(obj);
>-		if (err) {
>-			pr_err("[loop %d] create_mmap_offset failed with err=%d\n",
>-			       loop, err);
>-			goto out;
>-		}
> 	}
> 
> out:
>+	mmap_offset_lock(i915);
> 	drm_mm_remove_node(&resv);
>+	mmap_offset_unlock(i915);
> out_park:
> 	restore_retire_worker(i915);
> 	return err;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c	2019-08-31 15:01:12.023736183 -0500
>@@ -3,6 +3,8 @@
>  * Copyright Â© 2019 Intel Corporation
>  */
> 
>+#include "gt/intel_gt.h"
>+
> #include "i915_selftest.h"
> 
> #include "selftests/igt_flush_test.h"
>@@ -11,8 +13,8 @@
> 
> static int igt_fill_blt(void *arg)
> {
>-	struct intel_context *ce = arg;
>-	struct drm_i915_private *i915 = ce->gem_context->i915;
>+	struct drm_i915_private *i915 = arg;
>+	struct intel_context *ce = i915->engine[BCS0]->kernel_context;
> 	struct drm_i915_gem_object *obj;
> 	struct rnd_state prng;
> 	IGT_TIMEOUT(end);
>@@ -83,11 +85,6 @@
> err_put:
> 	i915_gem_object_put(obj);
> err_flush:
>-	mutex_lock(&i915->drm.struct_mutex);
>-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>-		err = -EIO;
>-	mutex_unlock(&i915->drm.struct_mutex);
>-
> 	if (err == -ENOMEM)
> 		err = 0;
> 
>@@ -100,11 +97,11 @@
> 		SUBTEST(igt_fill_blt),
> 	};
> 
>-	if (i915_terminally_wedged(i915))
>+	if (intel_gt_is_wedged(&i915->gt))
> 		return 0;
> 
> 	if (!HAS_ENGINE(i915, BCS0))
> 		return 0;
> 
>-	return i915_subtests(tests, i915->engine[BCS0]->kernel_context);
>+	return i915_live_subtests(tests, i915);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/gen6_renderstate.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/gen6_renderstate.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/gen6_renderstate.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/gen6_renderstate.c	2019-08-31 15:01:12.242736202 -0500
>@@ -0,0 +1,315 @@
>+/*
>+ * Copyright Â© 2014 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>+ * DEALINGS IN THE SOFTWARE.
>+ *
>+ * Generated by: intel-gpu-tools-1.8-220-g01153e7
>+ */
>+
>+#include "intel_renderstate.h"
>+
>+static const u32 gen6_null_state_relocs[] = {
>+	0x00000020,
>+	0x00000024,
>+	0x0000002c,
>+	0x000001e0,
>+	0x000001e4,
>+	-1,
>+};
>+
>+static const u32 gen6_null_state_batch[] = {
>+	0x69040000,
>+	0x790d0001,
>+	0x00000000,
>+	0x00000000,
>+	0x78180000,
>+	0x00000001,
>+	0x61010008,
>+	0x00000000,
>+	0x00000001,	 /* reloc */
>+	0x00000001,	 /* reloc */
>+	0x00000000,
>+	0x00000001,	 /* reloc */
>+	0x00000000,
>+	0x00000001,
>+	0x00000000,
>+	0x00000001,
>+	0x61020000,
>+	0x00000000,
>+	0x78050001,
>+	0x00000018,
>+	0x00000000,
>+	0x780d1002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000420,
>+	0x78150003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78100004,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78160003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78110005,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78120002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78170003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79050005,
>+	0xe0040000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79100000,
>+	0x00000000,
>+	0x79000002,
>+	0xffffffff,
>+	0x00000000,
>+	0x00000000,
>+	0x780e0002,
>+	0x00000441,
>+	0x00000401,
>+	0x00000401,
>+	0x78021002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000400,
>+	0x78130012,
>+	0x00400810,
>+	0x00000000,
>+	0x20000000,
>+	0x04000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78140007,
>+	0x00000280,
>+	0x08080000,
>+	0x00000000,
>+	0x00060000,
>+	0x4e080002,
>+	0x00100400,
>+	0x00000000,
>+	0x00000000,
>+	0x78090005,
>+	0x02000000,
>+	0x22220000,
>+	0x02f60000,
>+	0x11330000,
>+	0x02850004,
>+	0x11220000,
>+	0x78011002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000200,
>+	0x78080003,
>+	0x00002000,
>+	0x00000448,	 /* reloc */
>+	0x00000448,	 /* reloc */
>+	0x00000000,
>+	0x05000000,	 /* cmds end */
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000220,	 /* state start */
>+	0x00000240,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x0060005a,
>+	0x204077be,
>+	0x000000c0,
>+	0x008d0040,
>+	0x0060005a,
>+	0x206077be,
>+	0x000000c0,
>+	0x008d0080,
>+	0x0060005a,
>+	0x208077be,
>+	0x000000d0,
>+	0x008d0040,
>+	0x0060005a,
>+	0x20a077be,
>+	0x000000d0,
>+	0x008d0080,
>+	0x00000201,
>+	0x20080061,
>+	0x00000000,
>+	0x00000000,
>+	0x00600001,
>+	0x20200022,
>+	0x008d0000,
>+	0x00000000,
>+	0x02800031,
>+	0x21c01cc9,
>+	0x00000020,
>+	0x0a8a0001,
>+	0x00600001,
>+	0x204003be,
>+	0x008d01c0,
>+	0x00000000,
>+	0x00600001,
>+	0x206003be,
>+	0x008d01e0,
>+	0x00000000,
>+	0x00600001,
>+	0x208003be,
>+	0x008d0200,
>+	0x00000000,
>+	0x00600001,
>+	0x20a003be,
>+	0x008d0220,
>+	0x00000000,
>+	0x00600001,
>+	0x20c003be,
>+	0x008d0240,
>+	0x00000000,
>+	0x00600001,
>+	0x20e003be,
>+	0x008d0260,
>+	0x00000000,
>+	0x00600001,
>+	0x210003be,
>+	0x008d0280,
>+	0x00000000,
>+	0x00600001,
>+	0x212003be,
>+	0x008d02a0,
>+	0x00000000,
>+	0x05800031,
>+	0x24001cc8,
>+	0x00000040,
>+	0x90019000,
>+	0x0000007e,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x0000007e,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x0000007e,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x0000007e,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x0000007e,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x0000007e,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x0000007e,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x0000007e,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x30000000,
>+	0x00000124,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0xf99a130c,
>+	0x799a130c,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x80000031,
>+	0x00000003,
>+	0x00000000,	 /* state end */
>+};
>+
>+RO_RENDERSTATE(6);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/gen7_renderstate.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/gen7_renderstate.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/gen7_renderstate.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/gen7_renderstate.c	2019-08-31 15:01:12.242736202 -0500
>@@ -0,0 +1,279 @@
>+/*
>+ * Copyright Â© 2014 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>+ * DEALINGS IN THE SOFTWARE.
>+ *
>+ * Generated by: intel-gpu-tools-1.8-220-g01153e7
>+ */
>+
>+#include "intel_renderstate.h"
>+
>+static const u32 gen7_null_state_relocs[] = {
>+	0x0000000c,
>+	0x00000010,
>+	0x00000018,
>+	0x000001ec,
>+	-1,
>+};
>+
>+static const u32 gen7_null_state_batch[] = {
>+	0x69040000,
>+	0x61010008,
>+	0x00000000,
>+	0x00000001,	 /* reloc */
>+	0x00000001,	 /* reloc */
>+	0x00000000,
>+	0x00000001,	 /* reloc */
>+	0x00000000,
>+	0x00000001,
>+	0x00000000,
>+	0x00000001,
>+	0x790d0002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78180000,
>+	0x00000001,
>+	0x79160000,
>+	0x00000008,
>+	0x78300000,
>+	0x02010040,
>+	0x78310000,
>+	0x04000000,
>+	0x78320000,
>+	0x04000000,
>+	0x78330000,
>+	0x02000000,
>+	0x78100004,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781b0005,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781c0002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781d0004,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78110005,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78120002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78210000,
>+	0x00000000,
>+	0x78130005,
>+	0x00000000,
>+	0x20000000,
>+	0x04000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78140001,
>+	0x20000800,
>+	0x00000000,
>+	0x781e0001,
>+	0x00000000,
>+	0x00000000,
>+	0x78050005,
>+	0xe0040000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78040001,
>+	0x00000000,
>+	0x00000000,
>+	0x78240000,
>+	0x00000240,
>+	0x78230000,
>+	0x00000260,
>+	0x782f0000,
>+	0x00000280,
>+	0x781f000c,
>+	0x00400810,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78200006,
>+	0x000002c0,
>+	0x08080000,
>+	0x00000000,
>+	0x28000402,
>+	0x00060000,
>+	0x00000000,
>+	0x00000000,
>+	0x78090005,
>+	0x02000000,
>+	0x22220000,
>+	0x02f60000,
>+	0x11230000,
>+	0x02f60004,
>+	0x11230000,
>+	0x78080003,
>+	0x00006008,
>+	0x00000340,	 /* reloc */
>+	0xffffffff,
>+	0x00000000,
>+	0x782a0000,
>+	0x00000360,
>+	0x79000002,
>+	0xffffffff,
>+	0x00000000,
>+	0x00000000,
>+	0x7b000005,
>+	0x0000000f,
>+	0x00000003,
>+	0x00000000,
>+	0x00000001,
>+	0x00000000,
>+	0x00000000,
>+	0x05000000,	 /* cmds end */
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000031,	 /* state start */
>+	0x00000003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0xf99a130c,
>+	0x799a130c,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000492,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x0080005a,
>+	0x2e2077bd,
>+	0x000000c0,
>+	0x008d0040,
>+	0x0080005a,
>+	0x2e6077bd,
>+	0x000000d0,
>+	0x008d0040,
>+	0x02800031,
>+	0x21801fa9,
>+	0x008d0e20,
>+	0x08840001,
>+	0x00800001,
>+	0x2e2003bd,
>+	0x008d0180,
>+	0x00000000,
>+	0x00800001,
>+	0x2e6003bd,
>+	0x008d01c0,
>+	0x00000000,
>+	0x00800001,
>+	0x2ea003bd,
>+	0x008d0200,
>+	0x00000000,
>+	0x00800001,
>+	0x2ee003bd,
>+	0x008d0240,
>+	0x00000000,
>+	0x05800031,
>+	0x20001fa8,
>+	0x008d0e20,
>+	0x90031000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000380,
>+	0x000003a0,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,	 /* state end */
>+};
>+
>+RO_RENDERSTATE(7);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/gen8_renderstate.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/gen8_renderstate.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/gen8_renderstate.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/gen8_renderstate.c	2019-08-31 15:01:12.242736202 -0500
>@@ -0,0 +1,983 @@
>+/*
>+ * Copyright Â© 2014 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>+ * DEALINGS IN THE SOFTWARE.
>+ *
>+ * Generated by: intel-gpu-tools-1.8-220-g01153e7
>+ */
>+
>+#include "intel_renderstate.h"
>+
>+static const u32 gen8_null_state_relocs[] = {
>+	0x00000798,
>+	0x000007a4,
>+	0x000007ac,
>+	0x000007bc,
>+	-1,
>+};
>+
>+static const u32 gen8_null_state_batch[] = {
>+	0x7a000004,
>+	0x01000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x69040000,
>+	0x78140000,
>+	0x04000000,
>+	0x7820000a,
>+	0x00000000,
>+	0x00000000,
>+	0x80000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78130002,
>+	0x00000000,
>+	0x00000000,
>+	0x02001808,
>+	0x781f0002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78510009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78100007,
>+	0x00000000,
>+	0x00000000,
>+	0x00010000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781b0007,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000800,
>+	0x00000000,
>+	0x78110008,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781e0003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781d0007,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78120002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78500003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781c0002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x780c0000,
>+	0x00000000,
>+	0x78520003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78300000,
>+	0x08010040,
>+	0x78310000,
>+	0x1e000000,
>+	0x78320000,
>+	0x1e000000,
>+	0x78330000,
>+	0x1e000000,
>+	0x79190002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x791a0002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x791b0002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79120000,
>+	0x00000000,
>+	0x79130000,
>+	0x00000000,
>+	0x79140000,
>+	0x00000000,
>+	0x79150000,
>+	0x00000000,
>+	0x79160000,
>+	0x00000000,
>+	0x78150009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78190009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781a0009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78160009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78170009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78490001,
>+	0x00000000,
>+	0x00000000,
>+	0x784a0000,
>+	0x00000000,
>+	0x784b0000,
>+	0x00000004,
>+	0x79170101,
>+	0x00000000,
>+	0x00000080,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79180006,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79180006,
>+	0x20000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79180006,
>+	0x40000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79180006,
>+	0x60000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x6101000e,
>+	0x00000001,	 /* reloc */
>+	0x00000000,
>+	0x00000000,
>+	0x00000001,	 /* reloc */
>+	0x00000000,
>+	0x00000001,	 /* reloc */
>+	0x00000000,
>+	0x00000001,
>+	0x00000000,
>+	0x00000001,	 /* reloc */
>+	0x00000000,
>+	0x00001001,
>+	0x00001001,
>+	0x00000001,
>+	0x00001001,
>+	0x61020001,
>+	0x00000000,
>+	0x00000000,
>+	0x79000002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78050006,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79040002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79040002,
>+	0x40000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79040002,
>+	0x80000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79040002,
>+	0xc0000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79080001,
>+	0x00000000,
>+	0x00000000,
>+	0x790a0001,
>+	0x00000000,
>+	0x00000000,
>+	0x78060003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78070003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78040001,
>+	0x00000000,
>+	0x00000000,
>+	0x79110000,
>+	0x00000000,
>+	0x780d0000,
>+	0x00000000,
>+	0x79060000,
>+	0x00000000,
>+	0x7907001f,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x7902000f,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x790c000f,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x780a0003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78080083,
>+	0x00004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x04004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x08004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x0c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x10004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x14004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x18004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x1c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x20004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x24004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x28004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x2c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x30004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x34004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x38004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x3c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x40004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x44004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x48004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x4c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x50004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x54004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x58004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x5c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x60004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x64004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x68004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x6c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x70004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x74004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x7c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x80004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78090043,
>+	0x02000000,
>+	0x22220000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x680b0001,
>+	0x78260000,
>+	0x00000000,
>+	0x78270000,
>+	0x00000000,
>+	0x78280000,
>+	0x00000000,
>+	0x78290000,
>+	0x00000000,
>+	0x782a0000,
>+	0x00000000,
>+	0x780e0000,
>+	0x00000dc1,
>+	0x78240000,
>+	0x00000e01,
>+	0x784f0000,
>+	0x80000100,
>+	0x784d0000,
>+	0x40000000,
>+	0x782b0000,
>+	0x00000000,
>+	0x782c0000,
>+	0x00000000,
>+	0x782d0000,
>+	0x00000000,
>+	0x782e0000,
>+	0x00000000,
>+	0x782f0000,
>+	0x00000000,
>+	0x780f0000,
>+	0x00000000,
>+	0x78230000,
>+	0x00000e60,
>+	0x78210000,
>+	0x00000e80,
>+	0x7b000005,
>+	0x00000004,
>+	0x00000001,
>+	0x00000000,
>+	0x00000001,
>+	0x00000000,
>+	0x00000000,
>+	0x05000000,	 /* cmds end */
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,	 /* state start */
>+	0x00000000,
>+	0x3f800000,
>+	0x3f800000,
>+	0x3f800000,
>+	0x3f800000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,	 /* state end */
>+};
>+
>+RO_RENDERSTATE(8);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/gen9_renderstate.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/gen9_renderstate.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/gen9_renderstate.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/gen9_renderstate.c	2019-08-31 15:01:12.242736202 -0500
>@@ -0,0 +1,999 @@
>+/*
>+ * Copyright Â© 2014 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>+ * DEALINGS IN THE SOFTWARE.
>+ *
>+ * Generated by: intel-gpu-tools-1.19-177-g68e2eab2
>+ */
>+
>+#include "intel_renderstate.h"
>+
>+static const u32 gen9_null_state_relocs[] = {
>+	0x000007a8,
>+	0x000007b4,
>+	0x000007bc,
>+	0x000007cc,
>+	-1,
>+};
>+
>+static const u32 gen9_null_state_batch[] = {
>+	0x7a000004,
>+	0x01000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x69040300,
>+	0x78140000,
>+	0x04000000,
>+	0x7820000a,
>+	0x00000000,
>+	0x00000000,
>+	0x80000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78130002,
>+	0x00000000,
>+	0x00000000,
>+	0x02001808,
>+	0x781f0004,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78510009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78100007,
>+	0x00000000,
>+	0x00000000,
>+	0x00010000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781b0007,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000800,
>+	0x00000000,
>+	0x78110008,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781e0003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781d0009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78120002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78500003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781c0002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x780c0000,
>+	0x00000000,
>+	0x78520003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78300000,
>+	0x08010040,
>+	0x78310000,
>+	0x1e000000,
>+	0x78320000,
>+	0x1e000000,
>+	0x78330000,
>+	0x1e000000,
>+	0x79190002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x791a0002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x791b0002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79120000,
>+	0x00000000,
>+	0x79130000,
>+	0x00000000,
>+	0x79140000,
>+	0x00000000,
>+	0x79150000,
>+	0x00000000,
>+	0x79160000,
>+	0x00000000,
>+	0x78150009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78190009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x781a0009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78160009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78170009,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78490001,
>+	0x00000000,
>+	0x00000000,
>+	0x784a0000,
>+	0x00000000,
>+	0x784b0000,
>+	0x00000004,
>+	0x79170101,
>+	0x00000000,
>+	0x00000080,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
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>+	0x00000000,
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>+	0x00000000,
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>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79180006,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79180006,
>+	0x20000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79180006,
>+	0x40000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79180006,
>+	0x60000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x61010011,
>+	0x00000001,	 /* reloc */
>+	0x00000000,
>+	0x00000000,
>+	0x00000001,	 /* reloc */
>+	0x00000000,
>+	0x00000001,	 /* reloc */
>+	0x00000000,
>+	0x00000001,
>+	0x00000000,
>+	0x00000001,	 /* reloc */
>+	0x00000000,
>+	0x00001001,
>+	0x00001001,
>+	0x00000001,
>+	0x00001001,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x61020001,
>+	0x00000000,
>+	0x00000000,
>+	0x79000002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78050006,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79040002,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79040002,
>+	0x40000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79040002,
>+	0x80000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79040002,
>+	0xc0000000,
>+	0x00000000,
>+	0x00000000,
>+	0x79080001,
>+	0x00000000,
>+	0x00000000,
>+	0x790a0001,
>+	0x00000000,
>+	0x00000000,
>+	0x78060003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78070003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78040001,
>+	0x00000000,
>+	0x00000000,
>+	0x79110000,
>+	0x00000000,
>+	0x780d0000,
>+	0x00000000,
>+	0x79060000,
>+	0x00000000,
>+	0x7907001f,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x7902000f,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x790c000f,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x780a0003,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78080083,
>+	0x00004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x04004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x08004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x0c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x10004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x14004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x18004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x1c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x20004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x24004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x28004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x2c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x30004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x34004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x38004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x3c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x40004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x44004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x48004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x4c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x50004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x54004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x58004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x5c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x60004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x64004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x68004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x6c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x70004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x74004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x7c004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x80004000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78090043,
>+	0x02000000,
>+	0x22220000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x78550003,
>+	0x0000000f,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x680b0001,
>+	0x780e0000,
>+	0x00000e01,
>+	0x78240000,
>+	0x00000e41,
>+	0x784f0000,
>+	0x80000100,
>+	0x784d0000,
>+	0x40000000,
>+	0x782b0000,
>+	0x00000000,
>+	0x782c0000,
>+	0x00000000,
>+	0x782d0000,
>+	0x00000000,
>+	0x782e0000,
>+	0x00000000,
>+	0x782f0000,
>+	0x00000000,
>+	0x780f0000,
>+	0x00000000,
>+	0x78230000,
>+	0x00000ea0,
>+	0x78210000,
>+	0x00000ec0,
>+	0x78260000,
>+	0x00000000,
>+	0x78270000,
>+	0x00000000,
>+	0x78280000,
>+	0x00000000,
>+	0x78290000,
>+	0x00000000,
>+	0x782a0000,
>+	0x00000000,
>+	0x7b000005,
>+	0x00000004,
>+	0x00000001,
>+	0x00000000,
>+	0x00000001,
>+	0x00000000,
>+	0x00000000,
>+	0x05000000,	 /* cmds end */
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,	 /* state start */
>+	0x00000000,
>+	0x3f800000,
>+	0x3f800000,
>+	0x3f800000,
>+	0x3f800000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,
>+	0x00000000,	 /* state end */
>+};
>+
>+RO_RENDERSTATE(9);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_context.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_context.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_context.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_context.c	2019-08-31 15:01:12.024736183 -0500
>@@ -59,6 +59,10 @@
> 		if (err)
> 			goto err;
> 
>+		GEM_TRACE("%s context:%llx pin ring:{head:%04x, tail:%04x}\n",
>+			  ce->engine->name, ce->ring->timeline->fence_context,
>+			  ce->ring->head, ce->ring->tail);
>+
> 		i915_gem_context_get(ce->gem_context); /* for ctx->ppgtt */
> 
> 		smp_mb__before_atomic(); /* flush pin before it is visible */
>@@ -85,6 +89,9 @@
> 	mutex_lock_nested(&ce->pin_mutex, SINGLE_DEPTH_NESTING);
> 
> 	if (likely(atomic_dec_and_test(&ce->pin_count))) {
>+		GEM_TRACE("%s context:%llx retire\n",
>+			  ce->engine->name, ce->ring->timeline->fence_context);
>+
> 		ce->ops->unpin(ce);
> 
> 		i915_gem_context_put(ce->gem_context);
>@@ -95,11 +102,15 @@
> 	intel_context_put(ce);
> }
> 
>-static int __context_pin_state(struct i915_vma *vma, unsigned long flags)
>+static int __context_pin_state(struct i915_vma *vma)
> {
>+	u64 flags;
> 	int err;
> 
>-	err = i915_vma_pin(vma, 0, 0, flags | PIN_GLOBAL);
>+	flags = i915_ggtt_pin_bias(vma) | PIN_OFFSET_BIAS;
>+	flags |= PIN_HIGH | PIN_GLOBAL;
>+
>+	err = i915_vma_pin(vma, 0, 0, flags);
> 	if (err)
> 		return err;
> 
>@@ -119,10 +130,13 @@
> 	__i915_vma_unpin(vma);
> }
> 
>-static void intel_context_retire(struct i915_active *active)
>+static void __intel_context_retire(struct i915_active *active)
> {
> 	struct intel_context *ce = container_of(active, typeof(*ce), active);
> 
>+	GEM_TRACE("%s context:%llx retire\n",
>+		  ce->engine->name, ce->ring->timeline->fence_context);
>+
> 	if (ce->state)
> 		__context_unpin_state(ce->state);
> 
>@@ -130,35 +144,11 @@
> 	intel_context_put(ce);
> }
> 
>-void
>-intel_context_init(struct intel_context *ce,
>-		   struct i915_gem_context *ctx,
>-		   struct intel_engine_cs *engine)
>-{
>-	GEM_BUG_ON(!engine->cops);
>-
>-	kref_init(&ce->ref);
>-
>-	ce->gem_context = ctx;
>-	ce->engine = engine;
>-	ce->ops = engine->cops;
>-	ce->sseu = engine->sseu;
>-
>-	INIT_LIST_HEAD(&ce->signal_link);
>-	INIT_LIST_HEAD(&ce->signals);
>-
>-	mutex_init(&ce->pin_mutex);
>-
>-	i915_active_init(ctx->i915, &ce->active, intel_context_retire);
>-}
>-
>-int intel_context_active_acquire(struct intel_context *ce, unsigned long flags)
>+static int __intel_context_active(struct i915_active *active)
> {
>+	struct intel_context *ce = container_of(active, typeof(*ce), active);
> 	int err;
> 
>-	if (!i915_active_acquire(&ce->active))
>-		return 0;
>-
> 	intel_context_get(ce);
> 
> 	err = intel_ring_pin(ce->ring);
>@@ -168,7 +158,7 @@
> 	if (!ce->state)
> 		return 0;
> 
>-	err = __context_pin_state(ce->state, flags);
>+	err = __context_pin_state(ce->state);
> 	if (err)
> 		goto err_ring;
> 
>@@ -188,15 +178,40 @@
> 	intel_ring_unpin(ce->ring);
> err_put:
> 	intel_context_put(ce);
>-	i915_active_cancel(&ce->active);
> 	return err;
> }
> 
>-void intel_context_active_release(struct intel_context *ce)
>+void
>+intel_context_init(struct intel_context *ce,
>+		   struct i915_gem_context *ctx,
>+		   struct intel_engine_cs *engine)
>+{
>+	GEM_BUG_ON(!engine->cops);
>+
>+	kref_init(&ce->ref);
>+
>+	ce->gem_context = ctx;
>+	ce->vm = i915_vm_get(ctx->vm ?: &engine->gt->ggtt->vm);
>+
>+	ce->engine = engine;
>+	ce->ops = engine->cops;
>+	ce->sseu = engine->sseu;
>+
>+	INIT_LIST_HEAD(&ce->signal_link);
>+	INIT_LIST_HEAD(&ce->signals);
>+
>+	mutex_init(&ce->pin_mutex);
>+
>+	i915_active_init(ctx->i915, &ce->active,
>+			 __intel_context_active, __intel_context_retire);
>+}
>+
>+void intel_context_fini(struct intel_context *ce)
> {
>-	/* Nodes preallocated in intel_context_active() */
>-	i915_active_acquire_barrier(&ce->active);
>-	i915_active_release(&ce->active);
>+	i915_vm_put(ce->vm);
>+
>+	mutex_destroy(&ce->pin_mutex);
>+	i915_active_fini(&ce->active);
> }
> 
> static void i915_global_context_shrink(void)
>@@ -234,6 +249,44 @@
> 	intel_engine_pm_put(ce->engine);
> }
> 
>+int intel_context_prepare_remote_request(struct intel_context *ce,
>+					 struct i915_request *rq)
>+{
>+	struct intel_timeline *tl = ce->ring->timeline;
>+	int err;
>+
>+	/* Only suitable for use in remotely modifying this context */
>+	GEM_BUG_ON(rq->hw_context == ce);
>+
>+	if (rq->timeline != tl) { /* beware timeline sharing */
>+		err = mutex_lock_interruptible_nested(&tl->mutex,
>+						      SINGLE_DEPTH_NESTING);
>+		if (err)
>+			return err;
>+
>+		/* Queue this switch after current activity by this context. */
>+		err = i915_active_request_set(&tl->last_request, rq);
>+		if (err)
>+			goto unlock;
>+	}
>+	lockdep_assert_held(&tl->mutex);
>+
>+	/*
>+	 * Guarantee context image and the timeline remains pinned until the
>+	 * modifying request is retired by setting the ce activity tracker.
>+	 *
>+	 * But we only need to take one pin on the account of it. Or in other
>+	 * words transfer the pinned ce object to tracked active request.
>+	 */
>+	GEM_BUG_ON(i915_active_is_idle(&ce->active));
>+	err = i915_active_ref(&ce->active, rq->fence.context, rq);
>+
>+unlock:
>+	if (rq->timeline != tl)
>+		mutex_unlock(&tl->mutex);
>+	return err;
>+}
>+
> struct i915_request *intel_context_create_request(struct intel_context *ce)
> {
> 	struct i915_request *rq;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_context.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_context.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_context.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_context.h	2019-08-31 15:01:12.024736183 -0500
>@@ -9,12 +9,14 @@
> 
> #include <linux/lockdep.h>
> 
>+#include "i915_active.h"
> #include "intel_context_types.h"
> #include "intel_engine_types.h"
> 
> void intel_context_init(struct intel_context *ce,
> 			struct i915_gem_context *ctx,
> 			struct intel_engine_cs *engine);
>+void intel_context_fini(struct intel_context *ce);
> 
> struct intel_context *
> intel_context_create(struct i915_gem_context *ctx,
>@@ -102,8 +104,17 @@
> 		ce->ops->exit(ce);
> }
> 
>-int intel_context_active_acquire(struct intel_context *ce, unsigned long flags);
>-void intel_context_active_release(struct intel_context *ce);
>+static inline int intel_context_active_acquire(struct intel_context *ce)
>+{
>+	return i915_active_acquire(&ce->active);
>+}
>+
>+static inline void intel_context_active_release(struct intel_context *ce)
>+{
>+	/* Nodes preallocated in intel_context_active() */
>+	i915_active_acquire_barrier(&ce->active);
>+	i915_active_release(&ce->active);
>+}
> 
> static inline struct intel_context *intel_context_get(struct intel_context *ce)
> {
>@@ -129,6 +140,9 @@
> 	mutex_unlock(&ce->ring->timeline->mutex);
> }
> 
>+int intel_context_prepare_remote_request(struct intel_context *ce,
>+					 struct i915_request *rq);
>+
> struct i915_request *intel_context_create_request(struct intel_context *ce);
> 
> #endif /* __INTEL_CONTEXT_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_context_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_context_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_context_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_context_types.h	2019-08-31 15:01:12.024736183 -0500
>@@ -13,6 +13,7 @@
> #include <linux/types.h>
> 
> #include "i915_active_types.h"
>+#include "i915_utils.h"
> #include "intel_engine_types.h"
> #include "intel_sseu.h"
> 
>@@ -35,9 +36,15 @@
> struct intel_context {
> 	struct kref ref;
> 
>-	struct i915_gem_context *gem_context;
> 	struct intel_engine_cs *engine;
> 	struct intel_engine_cs *inflight;
>+#define intel_context_inflight(ce) ptr_mask_bits((ce)->inflight, 2)
>+#define intel_context_inflight_count(ce)  ptr_unmask_bits((ce)->inflight, 2)
>+#define intel_context_inflight_inc(ce) ptr_count_inc(&(ce)->inflight)
>+#define intel_context_inflight_dec(ce) ptr_count_dec(&(ce)->inflight)
>+
>+	struct i915_address_space *vm;
>+	struct i915_gem_context *gem_context;
> 
> 	struct list_head signal_link;
> 	struct list_head signals;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_engine_cs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_engine_cs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_engine_cs.c	2019-08-31 15:01:12.024736183 -0500
>@@ -28,6 +28,8 @@
> 
> #include "i915_drv.h"
> 
>+#include "gt/intel_gt.h"
>+
> #include "intel_engine.h"
> #include "intel_engine_pm.h"
> #include "intel_context.h"
>@@ -314,6 +316,7 @@
> 	engine->id = id;
> 	engine->mask = BIT(id);
> 	engine->i915 = dev_priv;
>+	engine->gt = &dev_priv->gt;
> 	engine->uncore = &dev_priv->uncore;
> 	__sprint_engine_name(engine->name, info);
> 	engine->hw_id = engine->guc_id = info->hw_id;
>@@ -423,7 +426,7 @@
> 	WARN_ON(engine_mask &
> 		GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
> 
>-	if (i915_inject_load_failure())
>+	if (i915_inject_probe_failure())
> 		return -ENODEV;
> 
> 	for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
>@@ -445,15 +448,9 @@
> 	if (WARN_ON(mask != engine_mask))
> 		device_info->engine_mask = mask;
> 
>-	/* We always presume we have at least RCS available for later probing */
>-	if (WARN_ON(!HAS_ENGINE(i915, RCS0))) {
>-		err = -ENODEV;
>-		goto cleanup;
>-	}
>-
> 	RUNTIME_INFO(i915)->num_engines = hweight32(mask);
> 
>-	i915_check_and_clear_faults(i915);
>+	intel_gt_check_and_clear_faults(&i915->gt);
> 
> 	intel_setup_engine_capabilities(i915);
> 
>@@ -508,6 +505,10 @@
> 	GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
> 	GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
> 
>+	memset(execlists->pending, 0, sizeof(execlists->pending));
>+	execlists->active =
>+		memset(execlists->inflight, 0, sizeof(execlists->inflight));
>+
> 	execlists->queue_priority_hint = INT_MIN;
> 	execlists->queue = RB_ROOT_CACHED;
> }
>@@ -577,7 +578,7 @@
> 
> 	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
> 
>-	vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
>+	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
> 	if (IS_ERR(vma)) {
> 		ret = PTR_ERR(vma);
> 		goto err;
>@@ -629,6 +630,10 @@
> 	engine->sseu =
> 		intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu);
> 
>+	intel_engine_init_workarounds(engine);
>+	intel_engine_init_whitelist(engine);
>+	intel_engine_init_ctx_wa(engine);
>+
> 	return 0;
> }
> 
>@@ -681,9 +686,10 @@
> 		u8 engine;
> 		u8 sched;
> 	} map[] = {
>-#define MAP(x, y) { ilog2(I915_ENGINE_HAS_##x), ilog2(I915_SCHEDULER_CAP_##y) }
>-		MAP(PREEMPTION, PREEMPTION),
>-		MAP(SEMAPHORES, SEMAPHORES),
>+#define MAP(x, y) { ilog2(I915_ENGINE_##x), ilog2(I915_SCHEDULER_CAP_##y) }
>+		MAP(HAS_PREEMPTION, PREEMPTION),
>+		MAP(HAS_SEMAPHORES, SEMAPHORES),
>+		MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS),
> #undef MAP
> 	};
> 	struct intel_engine_cs *engine;
>@@ -717,7 +723,7 @@
> 
> struct measure_breadcrumb {
> 	struct i915_request rq;
>-	struct i915_timeline timeline;
>+	struct intel_timeline timeline;
> 	struct intel_ring ring;
> 	u32 cs[1024];
> };
>@@ -727,15 +733,15 @@
> 	struct measure_breadcrumb *frame;
> 	int dw = -ENOMEM;
> 
>-	GEM_BUG_ON(!engine->i915->gt.scratch);
>+	GEM_BUG_ON(!engine->gt->scratch);
> 
> 	frame = kzalloc(sizeof(*frame), GFP_KERNEL);
> 	if (!frame)
> 		return -ENOMEM;
> 
>-	if (i915_timeline_init(engine->i915,
>-			       &frame->timeline,
>-			       engine->status_page.vma))
>+	if (intel_timeline_init(&frame->timeline,
>+				engine->gt,
>+				engine->status_page.vma))
> 		goto out_frame;
> 
> 	INIT_LIST_HEAD(&frame->ring.request_list);
>@@ -750,17 +756,17 @@
> 	frame->rq.ring = &frame->ring;
> 	frame->rq.timeline = &frame->timeline;
> 
>-	dw = i915_timeline_pin(&frame->timeline);
>+	dw = intel_timeline_pin(&frame->timeline);
> 	if (dw < 0)
> 		goto out_timeline;
> 
> 	dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
> 	GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
> 
>-	i915_timeline_unpin(&frame->timeline);
>+	intel_timeline_unpin(&frame->timeline);
> 
> out_timeline:
>-	i915_timeline_fini(&frame->timeline);
>+	intel_timeline_fini(&frame->timeline);
> out_frame:
> 	kfree(frame);
> 	return dw;
>@@ -823,6 +829,8 @@
> 	struct drm_i915_private *i915 = engine->i915;
> 	int ret;
> 
>+	engine->set_default_submission(engine);
>+
> 	/* We may need to do things with the shrinker which
> 	 * require us to immediately switch back to the default
> 	 * context. This can cause a problem as pinning the
>@@ -835,28 +843,15 @@
> 	if (ret)
> 		return ret;
> 
>-	/*
>-	 * Similarly the preempt context must always be available so that
>-	 * we can interrupt the engine at any time. However, as preemption
>-	 * is optional, we allow it to fail.
>-	 */
>-	if (i915->preempt_context)
>-		pin_context(i915->preempt_context, engine,
>-			    &engine->preempt_context);
>-
> 	ret = measure_breadcrumb_dw(engine);
> 	if (ret < 0)
> 		goto err_unpin;
> 
> 	engine->emit_fini_breadcrumb_dw = ret;
> 
>-	engine->set_default_submission(engine);
>-
> 	return 0;
> 
> err_unpin:
>-	if (engine->preempt_context)
>-		intel_context_unpin(engine->preempt_context);
> 	intel_context_unpin(engine->kernel_context);
> 	return ret;
> }
>@@ -881,8 +876,6 @@
> 	if (engine->default_state)
> 		i915_gem_object_put(engine->default_state);
> 
>-	if (engine->preempt_context)
>-		intel_context_unpin(engine->preempt_context);
> 	intel_context_unpin(engine->kernel_context);
> 	GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
> 
>@@ -966,57 +959,23 @@
> 	}
> }
> 
>-u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
>-{
>-	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
>-	unsigned int slice = fls(sseu->slice_mask) - 1;
>-	unsigned int subslice;
>-	u32 mcr_s_ss_select;
>-
>-	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
>-	subslice = fls(sseu->subslice_mask[slice]);
>-	GEM_BUG_ON(!subslice);
>-	subslice--;
>-
>-	if (IS_GEN(dev_priv, 10))
>-		mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
>-				  GEN8_MCR_SUBSLICE(subslice);
>-	else if (INTEL_GEN(dev_priv) >= 11)
>-		mcr_s_ss_select = GEN11_MCR_SLICE(slice) |
>-				  GEN11_MCR_SUBSLICE(subslice);
>-	else
>-		mcr_s_ss_select = 0;
>-
>-	return mcr_s_ss_select;
>-}
>-
> static u32
> read_subslice_reg(struct intel_engine_cs *engine, int slice, int subslice,
> 		  i915_reg_t reg)
> {
> 	struct drm_i915_private *i915 = engine->i915;
> 	struct intel_uncore *uncore = engine->uncore;
>-	u32 mcr_slice_subslice_mask;
>-	u32 mcr_slice_subslice_select;
>-	u32 default_mcr_s_ss_select;
>-	u32 mcr;
>-	u32 ret;
>+	u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
> 	enum forcewake_domains fw_domains;
> 
> 	if (INTEL_GEN(i915) >= 11) {
>-		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
>-					  GEN11_MCR_SUBSLICE_MASK;
>-		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
>-					    GEN11_MCR_SUBSLICE(subslice);
>+		mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
>+		mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
> 	} else {
>-		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
>-					  GEN8_MCR_SUBSLICE_MASK;
>-		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
>-					    GEN8_MCR_SUBSLICE(subslice);
>+		mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
>+		mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
> 	}
> 
>-	default_mcr_s_ss_select = intel_calculate_mcr_s_ss_select(i915);
>-
> 	fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
> 						    FW_REG_READ);
> 	fw_domains |= intel_uncore_forcewake_for_reg(uncore,
>@@ -1026,26 +985,23 @@
> 	spin_lock_irq(&uncore->lock);
> 	intel_uncore_forcewake_get__locked(uncore, fw_domains);
> 
>-	mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
>+	old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
> 
>-	WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
>-		     default_mcr_s_ss_select);
>-
>-	mcr &= ~mcr_slice_subslice_mask;
>-	mcr |= mcr_slice_subslice_select;
>+	mcr &= ~mcr_mask;
>+	mcr |= mcr_ss;
> 	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
> 
>-	ret = intel_uncore_read_fw(uncore, reg);
>+	val = intel_uncore_read_fw(uncore, reg);
> 
>-	mcr &= ~mcr_slice_subslice_mask;
>-	mcr |= default_mcr_s_ss_select;
>+	mcr &= ~mcr_mask;
>+	mcr |= old_mcr & mcr_mask;
> 
> 	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
> 
> 	intel_uncore_forcewake_put__locked(uncore, fw_domains);
> 	spin_unlock_irq(&uncore->lock);
> 
>-	return ret;
>+	return val;
> }
> 
> /* NB: please notice the memset */
>@@ -1150,17 +1106,17 @@
> bool intel_engine_is_idle(struct intel_engine_cs *engine)
> {
> 	/* More white lies, if wedged, hw state is inconsistent */
>-	if (i915_reset_failed(engine->i915))
>+	if (intel_gt_is_wedged(engine->gt))
> 		return true;
> 
>-	if (!intel_wakeref_active(&engine->wakeref))
>+	if (!intel_engine_pm_is_awake(engine))
> 		return true;
> 
> 	/* Waiting to drain ELSP? */
>-	if (READ_ONCE(engine->execlists.active)) {
>+	if (execlists_active(&engine->execlists)) {
> 		struct tasklet_struct *t = &engine->execlists.tasklet;
> 
>-		synchronize_hardirq(engine->i915->drm.irq);
>+		synchronize_hardirq(engine->i915->drm.pdev->irq);
> 
> 		local_bh_disable();
> 		if (tasklet_trylock(t)) {
>@@ -1174,7 +1130,7 @@
> 		/* Otherwise flush the tasklet if it was on another cpu */
> 		tasklet_unlock_wait(t);
> 
>-		if (READ_ONCE(engine->execlists.active))
>+		if (execlists_active(&engine->execlists))
> 			return false;
> 	}
> 
>@@ -1186,7 +1142,7 @@
> 	return ring_is_idle(engine);
> }
> 
>-bool intel_engines_are_idle(struct drm_i915_private *i915)
>+bool intel_engines_are_idle(struct intel_gt *gt)
> {
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
>@@ -1195,14 +1151,14 @@
> 	 * If the driver is wedged, HW state may be very inconsistent and
> 	 * report that it is still busy, even though we have stopped using it.
> 	 */
>-	if (i915_reset_failed(i915))
>+	if (intel_gt_is_wedged(gt))
> 		return true;
> 
> 	/* Already parked (and passed an idleness test); must still be idle */
>-	if (!READ_ONCE(i915->gt.awake))
>+	if (!READ_ONCE(gt->awake))
> 		return true;
> 
>-	for_each_engine(engine, i915, id) {
>+	for_each_engine(engine, gt->i915, id) {
> 		if (!intel_engine_is_idle(engine))
> 			return false;
> 	}
>@@ -1210,12 +1166,12 @@
> 	return true;
> }
> 
>-void intel_engines_reset_default_submission(struct drm_i915_private *i915)
>+void intel_engines_reset_default_submission(struct intel_gt *gt)
> {
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
> 
>-	for_each_engine(engine, i915, id)
>+	for_each_engine(engine, gt->i915, id)
> 		engine->set_default_submission(engine);
> }
> 
>@@ -1372,6 +1328,7 @@
> 	}
> 
> 	if (HAS_EXECLISTS(dev_priv)) {
>+		struct i915_request * const *port, *rq;
> 		const u32 *hws =
> 			&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
> 		const u8 num_entries = execlists->csb_size;
>@@ -1404,27 +1361,33 @@
> 		}
> 
> 		spin_lock_irqsave(&engine->active.lock, flags);
>-		for (idx = 0; idx < execlists_num_ports(execlists); idx++) {
>-			struct i915_request *rq;
>-			unsigned int count;
>+		for (port = execlists->active; (rq = *port); port++) {
> 			char hdr[80];
>+			int len;
> 
>-			rq = port_unpack(&execlists->port[idx], &count);
>-			if (!rq) {
>-				drm_printf(m, "\t\tELSP[%d] idle\n", idx);
>-			} else if (!i915_request_signaled(rq)) {
>-				snprintf(hdr, sizeof(hdr),
>-					 "\t\tELSP[%d] count=%d, ring:{start:%08x, hwsp:%08x, seqno:%08x}, rq: ",
>-					 idx, count,
>-					 i915_ggtt_offset(rq->ring->vma),
>-					 rq->timeline->hwsp_offset,
>-					 hwsp_seqno(rq));
>-				print_request(m, rq, hdr);
>-			} else {
>-				print_request(m, rq, "\t\tELSP[%d] rq: ");
>-			}
>+			len = snprintf(hdr, sizeof(hdr),
>+				       "\t\tActive[%d: ",
>+				       (int)(port - execlists->active));
>+			if (!i915_request_signaled(rq))
>+				len += snprintf(hdr + len, sizeof(hdr) - len,
>+						"ring:{start:%08x, hwsp:%08x, seqno:%08x}, ",
>+						i915_ggtt_offset(rq->ring->vma),
>+						rq->timeline->hwsp_offset,
>+						hwsp_seqno(rq));
>+			snprintf(hdr + len, sizeof(hdr) - len, "rq: ");
>+			print_request(m, rq, hdr);
>+		}
>+		for (port = execlists->pending; (rq = *port); port++) {
>+			char hdr[80];
>+
>+			snprintf(hdr, sizeof(hdr),
>+				 "\t\tPending[%d] ring:{start:%08x, hwsp:%08x, seqno:%08x}, rq: ",
>+				 (int)(port - execlists->pending),
>+				 i915_ggtt_offset(rq->ring->vma),
>+				 rq->timeline->hwsp_offset,
>+				 hwsp_seqno(rq));
>+			print_request(m, rq, hdr);
> 		}
>-		drm_printf(m, "\t\tHW active? 0x%x\n", execlists->active);
> 		spin_unlock_irqrestore(&engine->active.lock, flags);
> 	} else if (INTEL_GEN(dev_priv) > 6) {
> 		drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
>@@ -1486,7 +1449,7 @@
> 		va_end(ap);
> 	}
> 
>-	if (i915_reset_failed(engine->i915))
>+	if (intel_gt_is_wedged(engine->gt))
> 		drm_printf(m, "*** WEDGED ***\n");
> 
> 	drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
>@@ -1587,15 +1550,19 @@
> 	}
> 
> 	if (engine->stats.enabled++ == 0) {
>-		const struct execlist_port *port = execlists->port;
>-		unsigned int num_ports = execlists_num_ports(execlists);
>+		struct i915_request * const *port;
>+		struct i915_request *rq;
> 
> 		engine->stats.enabled_at = ktime_get();
> 
> 		/* XXX submission method oblivious? */
>-		while (num_ports-- && port_isset(port)) {
>+		for (port = execlists->active; (rq = *port); port++)
> 			engine->stats.active++;
>-			port++;
>+
>+		for (port = execlists->pending; (rq = *port); port++) {
>+			/* Exclude any contexts already counted in active */
>+			if (intel_context_inflight_count(rq->hw_context) == 1)
>+				engine->stats.active++;
> 		}
> 
> 		if (engine->stats.active)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_engine.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_engine.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_engine.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_engine.h	2019-08-31 15:01:12.024736183 -0500
>@@ -14,7 +14,7 @@
> #include "i915_reg.h"
> #include "i915_request.h"
> #include "i915_selftest.h"
>-#include "i915_timeline.h"
>+#include "gt/intel_timeline.h"
> #include "intel_engine_types.h"
> #include "intel_gpu_commands.h"
> #include "intel_workarounds.h"
>@@ -51,7 +51,7 @@
> #define ENGINE_READ16(...)	__ENGINE_READ_OP(read16, __VA_ARGS__)
> #define ENGINE_READ(...)	__ENGINE_READ_OP(read, __VA_ARGS__)
> #define ENGINE_READ_FW(...)	__ENGINE_READ_OP(read_fw, __VA_ARGS__)
>-#define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read, __VA_ARGS__)
>+#define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__)
> #define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__)
> 
> #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
>@@ -125,71 +125,26 @@
> 
> void intel_engines_set_scheduler_caps(struct drm_i915_private *i915);
> 
>-static inline void
>-execlists_set_active(struct intel_engine_execlists *execlists,
>-		     unsigned int bit)
>-{
>-	__set_bit(bit, (unsigned long *)&execlists->active);
>-}
>-
>-static inline bool
>-execlists_set_active_once(struct intel_engine_execlists *execlists,
>-			  unsigned int bit)
>-{
>-	return !__test_and_set_bit(bit, (unsigned long *)&execlists->active);
>-}
>-
>-static inline void
>-execlists_clear_active(struct intel_engine_execlists *execlists,
>-		       unsigned int bit)
>-{
>-	__clear_bit(bit, (unsigned long *)&execlists->active);
>-}
>-
>-static inline void
>-execlists_clear_all_active(struct intel_engine_execlists *execlists)
>+static inline unsigned int
>+execlists_num_ports(const struct intel_engine_execlists * const execlists)
> {
>-	execlists->active = 0;
>+	return execlists->port_mask + 1;
> }
> 
>-static inline bool
>-execlists_is_active(const struct intel_engine_execlists *execlists,
>-		    unsigned int bit)
>+static inline struct i915_request *
>+execlists_active(const struct intel_engine_execlists *execlists)
> {
>-	return test_bit(bit, (unsigned long *)&execlists->active);
>+	GEM_BUG_ON(execlists->active - execlists->inflight >
>+		   execlists_num_ports(execlists));
>+	return READ_ONCE(*execlists->active);
> }
> 
>-void execlists_user_begin(struct intel_engine_execlists *execlists,
>-			  const struct execlist_port *port);
>-void execlists_user_end(struct intel_engine_execlists *execlists);
>-
> void
> execlists_cancel_port_requests(struct intel_engine_execlists * const execlists);
> 
> struct i915_request *
> execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
> 
>-static inline unsigned int
>-execlists_num_ports(const struct intel_engine_execlists * const execlists)
>-{
>-	return execlists->port_mask + 1;
>-}
>-
>-static inline struct execlist_port *
>-execlists_port_complete(struct intel_engine_execlists * const execlists,
>-			struct execlist_port * const port)
>-{
>-	const unsigned int m = execlists->port_mask;
>-
>-	GEM_BUG_ON(port_index(port, execlists) != 0);
>-	GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
>-
>-	memmove(port, port + 1, m * sizeof(struct execlist_port));
>-	memset(port + m, 0, sizeof(struct execlist_port));
>-
>-	return port;
>-}
>-
> static inline u32
> intel_read_status_page(const struct intel_engine_cs *engine, int reg)
> {
>@@ -245,7 +200,7 @@
> 
> struct intel_ring *
> intel_engine_create_ring(struct intel_engine_cs *engine,
>-			 struct i915_timeline *timeline,
>+			 struct intel_timeline *timeline,
> 			 int size);
> int intel_ring_pin(struct intel_ring *ring);
> void intel_ring_reset(struct intel_ring *ring, u32 tail);
>@@ -456,8 +411,8 @@
> 	return cs;
> }
> 
>-static inline void intel_engine_reset(struct intel_engine_cs *engine,
>-				      bool stalled)
>+static inline void __intel_engine_reset(struct intel_engine_cs *engine,
>+					bool stalled)
> {
> 	if (engine->reset.reset)
> 		engine->reset.reset(engine, stalled);
>@@ -465,9 +420,9 @@
> }
> 
> bool intel_engine_is_idle(struct intel_engine_cs *engine);
>-bool intel_engines_are_idle(struct drm_i915_private *dev_priv);
>+bool intel_engines_are_idle(struct intel_gt *gt);
> 
>-void intel_engines_reset_default_submission(struct drm_i915_private *i915);
>+void intel_engines_reset_default_submission(struct intel_gt *gt);
> unsigned int intel_engines_has_context_isolation(struct drm_i915_private *i915);
> 
> bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_engine_pm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_engine_pm.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_engine_pm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_engine_pm.c	2019-08-31 15:01:12.025736183 -0500
>@@ -8,6 +8,7 @@
> 
> #include "intel_engine.h"
> #include "intel_engine_pm.h"
>+#include "intel_gt.h"
> #include "intel_gt_pm.h"
> 
> static int __engine_unpark(struct intel_wakeref *wf)
>@@ -18,7 +19,7 @@
> 
> 	GEM_TRACE("%s\n", engine->name);
> 
>-	intel_gt_pm_get(engine->i915);
>+	intel_gt_pm_get(engine->gt);
> 
> 	/* Pin the default state for fast resets from atomic context. */
> 	map = NULL;
>@@ -66,7 +67,7 @@
> 		return true;
> 
> 	/* GPU is pointing to the void, as good as in the kernel context. */
>-	if (i915_reset_failed(engine->i915))
>+	if (intel_gt_is_wedged(engine->gt))
> 		return true;
> 
> 	/*
>@@ -129,7 +130,7 @@
> 
> 	engine->execlists.no_priolist = false;
> 
>-	intel_gt_pm_put(engine->i915);
>+	intel_gt_pm_put(engine->gt);
> 	return 0;
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_engine_pm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_engine_pm.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_engine_pm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_engine_pm.h	2019-08-31 15:01:12.025736183 -0500
>@@ -16,6 +16,12 @@
> void intel_engine_pm_put(struct intel_engine_cs *engine);
> 
> static inline bool
>+intel_engine_pm_is_awake(const struct intel_engine_cs *engine)
>+{
>+	return intel_wakeref_is_active(&engine->wakeref);
>+}
>+
>+static inline bool
> intel_engine_pm_get_if_awake(struct intel_engine_cs *engine)
> {
> 	return intel_wakeref_get_if_active(&engine->wakeref);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_engine_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_engine_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_engine_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_engine_types.h	2019-08-31 15:01:12.025736183 -0500
>@@ -12,6 +12,7 @@
> #include <linux/kref.h>
> #include <linux/list.h>
> #include <linux/llist.h>
>+#include <linux/timer.h>
> #include <linux/types.h>
> 
> #include "i915_gem.h"
>@@ -19,7 +20,7 @@
> #include "i915_pmu.h"
> #include "i915_priolist_types.h"
> #include "i915_selftest.h"
>-#include "i915_timeline_types.h"
>+#include "gt/intel_timeline_types.h"
> #include "intel_sseu.h"
> #include "intel_wakeref.h"
> #include "intel_workarounds_types.h"
>@@ -35,6 +36,7 @@
> struct i915_gem_context;
> struct i915_request;
> struct i915_sched_attr;
>+struct intel_gt;
> struct intel_uncore;
> 
> typedef u8 intel_engine_mask_t;
>@@ -66,7 +68,7 @@
> 	struct i915_vma *vma;
> 	void *vaddr;
> 
>-	struct i915_timeline *timeline;
>+	struct intel_timeline *timeline;
> 	struct list_head request_list;
> 	struct list_head active_link;
> 
>@@ -150,6 +152,11 @@
> 	struct tasklet_struct tasklet;
> 
> 	/**
>+	 * @timer: kick the current context if its timeslice expires
>+	 */
>+	struct timer_list timer;
>+
>+	/**
> 	 * @default_priolist: priority list for I915_PRIORITY_NORMAL
> 	 */
> 	struct i915_priolist default_priolist;
>@@ -172,51 +179,28 @@
> 	 */
> 	u32 __iomem *ctrl_reg;
> 
>+#define EXECLIST_MAX_PORTS 2
> 	/**
>-	 * @port: execlist port states
>+	 * @active: the currently known context executing on HW
>+	 */
>+	struct i915_request * const *active;
>+	/**
>+	 * @inflight: the set of contexts submitted and acknowleged by HW
> 	 *
>-	 * For each hardware ELSP (ExecList Submission Port) we keep
>-	 * track of the last request and the number of times we submitted
>-	 * that port to hw. We then count the number of times the hw reports
>-	 * a context completion or preemption. As only one context can
>-	 * be active on hw, we limit resubmission of context to port[0]. This
>-	 * is called Lite Restore, of the context.
>+	 * The set of inflight contexts is managed by reading CS events
>+	 * from the HW. On a context-switch event (not preemption), we
>+	 * know the HW has transitioned from port0 to port1, and we
>+	 * advance our inflight/active tracking accordingly.
> 	 */
>-	struct execlist_port {
>-		/**
>-		 * @request_count: combined request and submission count
>-		 */
>-		struct i915_request *request_count;
>-#define EXECLIST_COUNT_BITS 2
>-#define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
>-#define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
>-#define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
>-#define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
>-#define port_set(p, packed) ((p)->request_count = (packed))
>-#define port_isset(p) ((p)->request_count)
>-#define port_index(p, execlists) ((p) - (execlists)->port)
>-
>-		/**
>-		 * @context_id: context ID for port
>-		 */
>-		GEM_DEBUG_DECL(u32 context_id);
>-
>-#define EXECLIST_MAX_PORTS 2
>-	} port[EXECLIST_MAX_PORTS];
>-
>+	struct i915_request *inflight[EXECLIST_MAX_PORTS + 1 /* sentinel */];
> 	/**
>-	 * @active: is the HW active? We consider the HW as active after
>-	 * submitting any context for execution and until we have seen the
>-	 * last context completion event. After that, we do not expect any
>-	 * more events until we submit, and so can park the HW.
>+	 * @pending: the next set of contexts submitted to ELSP
> 	 *
>-	 * As we have a small number of different sources from which we feed
>-	 * the HW, we track the state of each inside a single bitfield.
>+	 * We store the array of contexts that we submit to HW (via ELSP) and
>+	 * promote them to the inflight array once HW has signaled the
>+	 * preemption or idle-to-active event.
> 	 */
>-	unsigned int active;
>-#define EXECLISTS_ACTIVE_USER 0
>-#define EXECLISTS_ACTIVE_PREEMPT 1
>-#define EXECLISTS_ACTIVE_HWACK 2
>+	struct i915_request *pending[EXECLIST_MAX_PORTS + 1];
> 
> 	/**
> 	 * @port_mask: number of execlist ports - 1
>@@ -258,11 +242,6 @@
> 	u32 *csb_status;
> 
> 	/**
>-	 * @preempt_complete_status: expected CSB upon completing preemption
>-	 */
>-	u32 preempt_complete_status;
>-
>-	/**
> 	 * @csb_size: context status buffer FIFO size
> 	 */
> 	u8 csb_size;
>@@ -279,6 +258,7 @@
> 
> struct intel_engine_cs {
> 	struct drm_i915_private *i915;
>+	struct intel_gt *gt;
> 	struct intel_uncore *uncore;
> 	char name[INTEL_ENGINE_CS_MAX_NAME];
> 
>@@ -308,7 +288,6 @@
> 	struct llist_head barrier_tasks;
> 
> 	struct intel_context *kernel_context; /* pinned */
>-	struct intel_context *preempt_context; /* pinned; optional */
> 
> 	intel_engine_mask_t saturated; /* submitting semaphores too late? */
> 
>@@ -404,7 +383,6 @@
> 	const struct intel_context_ops *cops;
> 
> 	int		(*request_alloc)(struct i915_request *rq);
>-	int		(*init_context)(struct i915_request *rq);
> 
> 	int		(*emit_flush)(struct i915_request *request, u32 mode);
> #define EMIT_INVALIDATE	BIT(0)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_gpu_commands.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_gpu_commands.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_gpu_commands.h	2019-08-31 15:01:12.025736183 -0500
>@@ -8,6 +8,13 @@
> #define _INTEL_GPU_COMMANDS_H_
> 
> /*
>+ * Target address alignments required for GPU access e.g.
>+ * MI_STORE_DWORD_IMM.
>+ */
>+#define alignof_dword 4
>+#define alignof_qword 8
>+
>+/*
>  * Instruction field definitions used by the command parser
>  */
> #define INSTR_CLIENT_SHIFT      29
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_gt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_gt.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_gt.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_gt.c	2019-08-31 15:01:12.025736183 -0500
>@@ -0,0 +1,250 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright Â© 2019 Intel Corporation
>+ */
>+
>+#include "i915_drv.h"
>+
>+#include "intel_gt.h"
>+#include "intel_gt_pm.h"
>+#include "intel_uncore.h"
>+
>+void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
>+{
>+	gt->i915 = i915;
>+	gt->uncore = &i915->uncore;
>+
>+	INIT_LIST_HEAD(&gt->active_rings);
>+	INIT_LIST_HEAD(&gt->closed_vma);
>+
>+	spin_lock_init(&gt->closed_lock);
>+
>+	intel_gt_init_hangcheck(gt);
>+	intel_gt_init_reset(gt);
>+	intel_gt_pm_init_early(gt);
>+}
>+
>+void intel_gt_init_hw(struct drm_i915_private *i915)
>+{
>+	i915->gt.ggtt = &i915->ggtt;
>+}
>+
>+static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
>+{
>+	intel_uncore_rmw(uncore, reg, 0, set);
>+}
>+
>+static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
>+{
>+	intel_uncore_rmw(uncore, reg, clr, 0);
>+}
>+
>+static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
>+{
>+	intel_uncore_rmw(uncore, reg, 0, 0);
>+}
>+
>+static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
>+{
>+	GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
>+	GEN6_RING_FAULT_REG_POSTING_READ(engine);
>+}
>+
>+void
>+intel_gt_clear_error_registers(struct intel_gt *gt,
>+			       intel_engine_mask_t engine_mask)
>+{
>+	struct drm_i915_private *i915 = gt->i915;
>+	struct intel_uncore *uncore = gt->uncore;
>+	u32 eir;
>+
>+	if (!IS_GEN(i915, 2))
>+		clear_register(uncore, PGTBL_ER);
>+
>+	if (INTEL_GEN(i915) < 4)
>+		clear_register(uncore, IPEIR(RENDER_RING_BASE));
>+	else
>+		clear_register(uncore, IPEIR_I965);
>+
>+	clear_register(uncore, EIR);
>+	eir = intel_uncore_read(uncore, EIR);
>+	if (eir) {
>+		/*
>+		 * some errors might have become stuck,
>+		 * mask them.
>+		 */
>+		DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
>+		rmw_set(uncore, EMR, eir);
>+		intel_uncore_write(uncore, GEN2_IIR,
>+				   I915_MASTER_ERROR_INTERRUPT);
>+	}
>+
>+	if (INTEL_GEN(i915) >= 8) {
>+		rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
>+		intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
>+	} else if (INTEL_GEN(i915) >= 6) {
>+		struct intel_engine_cs *engine;
>+		enum intel_engine_id id;
>+
>+		for_each_engine_masked(engine, i915, engine_mask, id)
>+			gen8_clear_engine_error_register(engine);
>+	}
>+}
>+
>+static void gen6_check_faults(struct intel_gt *gt)
>+{
>+	struct intel_engine_cs *engine;
>+	enum intel_engine_id id;
>+	u32 fault;
>+
>+	for_each_engine(engine, gt->i915, id) {
>+		fault = GEN6_RING_FAULT_REG_READ(engine);
>+		if (fault & RING_FAULT_VALID) {
>+			DRM_DEBUG_DRIVER("Unexpected fault\n"
>+					 "\tAddr: 0x%08lx\n"
>+					 "\tAddress space: %s\n"
>+					 "\tSource ID: %d\n"
>+					 "\tType: %d\n",
>+					 fault & PAGE_MASK,
>+					 fault & RING_FAULT_GTTSEL_MASK ?
>+					 "GGTT" : "PPGTT",
>+					 RING_FAULT_SRCID(fault),
>+					 RING_FAULT_FAULT_TYPE(fault));
>+		}
>+	}
>+}
>+
>+static void gen8_check_faults(struct intel_gt *gt)
>+{
>+	struct intel_uncore *uncore = gt->uncore;
>+	u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);
>+
>+	if (fault & RING_FAULT_VALID) {
>+		u32 fault_data0, fault_data1;
>+		u64 fault_addr;
>+
>+		fault_data0 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA0);
>+		fault_data1 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA1);
>+		fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
>+			     ((u64)fault_data0 << 12);
>+
>+		DRM_DEBUG_DRIVER("Unexpected fault\n"
>+				 "\tAddr: 0x%08x_%08x\n"
>+				 "\tAddress space: %s\n"
>+				 "\tEngine ID: %d\n"
>+				 "\tSource ID: %d\n"
>+				 "\tType: %d\n",
>+				 upper_32_bits(fault_addr),
>+				 lower_32_bits(fault_addr),
>+				 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
>+				 GEN8_RING_FAULT_ENGINE_ID(fault),
>+				 RING_FAULT_SRCID(fault),
>+				 RING_FAULT_FAULT_TYPE(fault));
>+	}
>+}
>+
>+void intel_gt_check_and_clear_faults(struct intel_gt *gt)
>+{
>+	struct drm_i915_private *i915 = gt->i915;
>+
>+	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
>+	if (INTEL_GEN(i915) >= 8)
>+		gen8_check_faults(gt);
>+	else if (INTEL_GEN(i915) >= 6)
>+		gen6_check_faults(gt);
>+	else
>+		return;
>+
>+	intel_gt_clear_error_registers(gt, ALL_ENGINES);
>+}
>+
>+void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
>+{
>+	struct drm_i915_private *i915 = gt->i915;
>+	intel_wakeref_t wakeref;
>+
>+	/*
>+	 * No actual flushing is required for the GTT write domain for reads
>+	 * from the GTT domain. Writes to it "immediately" go to main memory
>+	 * as far as we know, so there's no chipset flush. It also doesn't
>+	 * land in the GPU render cache.
>+	 *
>+	 * However, we do have to enforce the order so that all writes through
>+	 * the GTT land before any writes to the device, such as updates to
>+	 * the GATT itself.
>+	 *
>+	 * We also have to wait a bit for the writes to land from the GTT.
>+	 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
>+	 * timing. This issue has only been observed when switching quickly
>+	 * between GTT writes and CPU reads from inside the kernel on recent hw,
>+	 * and it appears to only affect discrete GTT blocks (i.e. on LLC
>+	 * system agents we cannot reproduce this behaviour, until Cannonlake
>+	 * that was!).
>+	 */
>+
>+	wmb();
>+
>+	if (INTEL_INFO(i915)->has_coherent_ggtt)
>+		return;
>+
>+	intel_gt_chipset_flush(gt);
>+
>+	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
>+		struct intel_uncore *uncore = gt->uncore;
>+
>+		spin_lock_irq(&uncore->lock);
>+		intel_uncore_posting_read_fw(uncore,
>+					     RING_HEAD(RENDER_RING_BASE));
>+		spin_unlock_irq(&uncore->lock);
>+	}
>+}
>+
>+void intel_gt_chipset_flush(struct intel_gt *gt)
>+{
>+	wmb();
>+	if (INTEL_GEN(gt->i915) < 6)
>+		intel_gtt_chipset_flush();
>+}
>+
>+int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
>+{
>+	struct drm_i915_private *i915 = gt->i915;
>+	struct drm_i915_gem_object *obj;
>+	struct i915_vma *vma;
>+	int ret;
>+
>+	obj = i915_gem_object_create_stolen(i915, size);
>+	if (!obj)
>+		obj = i915_gem_object_create_internal(i915, size);
>+	if (IS_ERR(obj)) {
>+		DRM_ERROR("Failed to allocate scratch page\n");
>+		return PTR_ERR(obj);
>+	}
>+
>+	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
>+	if (IS_ERR(vma)) {
>+		ret = PTR_ERR(vma);
>+		goto err_unref;
>+	}
>+
>+	ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
>+	if (ret)
>+		goto err_unref;
>+
>+	gt->scratch = vma;
>+	return 0;
>+
>+err_unref:
>+	i915_gem_object_put(obj);
>+	return ret;
>+}
>+
>+void intel_gt_fini_scratch(struct intel_gt *gt)
>+{
>+	i915_vma_unpin_and_release(&gt->scratch, 0);
>+}
>+
>+void intel_gt_cleanup_early(struct intel_gt *gt)
>+{
>+	intel_gt_fini_reset(gt);
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_gt.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_gt.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_gt.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_gt.h	2019-08-31 15:01:12.025736183 -0500
>@@ -0,0 +1,60 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright Â© 2019 Intel Corporation
>+ */
>+
>+#ifndef __INTEL_GT__
>+#define __INTEL_GT__
>+
>+#include "intel_engine_types.h"
>+#include "intel_gt_types.h"
>+#include "intel_reset.h"
>+
>+struct drm_i915_private;
>+
>+static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
>+{
>+	return container_of(uc, struct intel_gt, uc);
>+}
>+
>+static inline struct intel_gt *guc_to_gt(struct intel_guc *guc)
>+{
>+	return container_of(guc, struct intel_gt, uc.guc);
>+}
>+
>+static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
>+{
>+	return container_of(huc, struct intel_gt, uc.huc);
>+}
>+
>+void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
>+void intel_gt_init_hw(struct drm_i915_private *i915);
>+
>+void intel_gt_cleanup_early(struct intel_gt *gt);
>+
>+void intel_gt_check_and_clear_faults(struct intel_gt *gt);
>+void intel_gt_clear_error_registers(struct intel_gt *gt,
>+				    intel_engine_mask_t engine_mask);
>+
>+void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
>+void intel_gt_chipset_flush(struct intel_gt *gt);
>+
>+void intel_gt_init_hangcheck(struct intel_gt *gt);
>+
>+int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size);
>+void intel_gt_fini_scratch(struct intel_gt *gt);
>+
>+static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt,
>+					  enum intel_gt_scratch_field field)
>+{
>+	return i915_ggtt_offset(gt->scratch) + field;
>+}
>+
>+static inline bool intel_gt_is_wedged(struct intel_gt *gt)
>+{
>+	return __intel_reset_failed(&gt->reset);
>+}
>+
>+void intel_gt_queue_hangcheck(struct intel_gt *gt);
>+
>+#endif /* __INTEL_GT_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_gt_pm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_gt_pm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_gt_pm.c	2019-08-31 15:01:12.025736183 -0500
>@@ -5,7 +5,9 @@
>  */
> 
> #include "i915_drv.h"
>+#include "i915_params.h"
> #include "intel_engine_pm.h"
>+#include "intel_gt.h"
> #include "intel_gt_pm.h"
> #include "intel_pm.h"
> #include "intel_wakeref.h"
>@@ -17,8 +19,8 @@
> 
> static int intel_gt_unpark(struct intel_wakeref *wf)
> {
>-	struct drm_i915_private *i915 =
>-		container_of(wf, typeof(*i915), gt.wakeref);
>+	struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
>+	struct drm_i915_private *i915 = gt->i915;
> 
> 	GEM_TRACE("\n");
> 
>@@ -33,8 +35,8 @@
> 	 * Work around it by grabbing a GT IRQ power domain whilst there is any
> 	 * GT activity, preventing any DC state transitions.
> 	 */
>-	i915->gt.awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
>-	GEM_BUG_ON(!i915->gt.awake);
>+	gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
>+	GEM_BUG_ON(!gt->awake);
> 
> 	intel_enable_gt_powersave(i915);
> 
>@@ -44,16 +46,18 @@
> 
> 	i915_pmu_gt_unparked(i915);
> 
>-	i915_queue_hangcheck(i915);
>+	intel_gt_queue_hangcheck(gt);
> 
> 	pm_notify(i915, INTEL_GT_UNPARK);
> 
> 	return 0;
> }
> 
>-void intel_gt_pm_get(struct drm_i915_private *i915)
>+void intel_gt_pm_get(struct intel_gt *gt)
> {
>-	intel_wakeref_get(&i915->runtime_pm, &i915->gt.wakeref, intel_gt_unpark);
>+	struct intel_runtime_pm *rpm = &gt->i915->runtime_pm;
>+
>+	intel_wakeref_get(rpm, &gt->wakeref, intel_gt_unpark);
> }
> 
> static int intel_gt_park(struct intel_wakeref *wf)
>@@ -76,28 +80,30 @@
> 	return 0;
> }
> 
>-void intel_gt_pm_put(struct drm_i915_private *i915)
>+void intel_gt_pm_put(struct intel_gt *gt)
> {
>-	intel_wakeref_put(&i915->runtime_pm, &i915->gt.wakeref, intel_gt_park);
>+	struct intel_runtime_pm *rpm = &gt->i915->runtime_pm;
>+
>+	intel_wakeref_put(rpm, &gt->wakeref, intel_gt_park);
> }
> 
>-void intel_gt_pm_init(struct drm_i915_private *i915)
>+void intel_gt_pm_init_early(struct intel_gt *gt)
> {
>-	intel_wakeref_init(&i915->gt.wakeref);
>-	BLOCKING_INIT_NOTIFIER_HEAD(&i915->gt.pm_notifications);
>+	intel_wakeref_init(&gt->wakeref);
>+	BLOCKING_INIT_NOTIFIER_HEAD(&gt->pm_notifications);
> }
> 
>-static bool reset_engines(struct drm_i915_private *i915)
>+static bool reset_engines(struct intel_gt *gt)
> {
>-	if (INTEL_INFO(i915)->gpu_reset_clobbers_display)
>+	if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
> 		return false;
> 
>-	return intel_gpu_reset(i915, ALL_ENGINES) == 0;
>+	return __intel_gt_reset(gt, ALL_ENGINES) == 0;
> }
> 
> /**
>  * intel_gt_sanitize: called after the GPU has lost power
>- * @i915: the i915 device
>+ * @gt: the i915 GT container
>  * @force: ignore a failed reset and sanitize engine state anyway
>  *
>  * Anytime we reset the GPU, either with an explicit GPU reset or through a
>@@ -105,21 +111,23 @@
>  * to match. Note that calling intel_gt_sanitize() if the GPU has not
>  * been reset results in much confusion!
>  */
>-void intel_gt_sanitize(struct drm_i915_private *i915, bool force)
>+void intel_gt_sanitize(struct intel_gt *gt, bool force)
> {
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
> 
> 	GEM_TRACE("\n");
> 
>-	if (!reset_engines(i915) && !force)
>+	intel_uc_sanitize(&gt->uc);
>+
>+	if (!reset_engines(gt) && !force)
> 		return;
> 
>-	for_each_engine(engine, i915, id)
>-		intel_engine_reset(engine, false);
>+	for_each_engine(engine, gt->i915, id)
>+		__intel_engine_reset(engine, false);
> }
> 
>-int intel_gt_resume(struct drm_i915_private *i915)
>+int intel_gt_resume(struct intel_gt *gt)
> {
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
>@@ -131,8 +139,8 @@
> 	 * Only the kernel contexts should remain pinned over suspend,
> 	 * allowing us to fixup the user contexts on their first pin.
> 	 */
>-	intel_gt_pm_get(i915);
>-	for_each_engine(engine, i915, id) {
>+	intel_gt_pm_get(gt);
>+	for_each_engine(engine, gt->i915, id) {
> 		struct intel_context *ce;
> 
> 		intel_engine_pm_get(engine);
>@@ -141,22 +149,18 @@
> 		if (ce)
> 			ce->ops->reset(ce);
> 
>-		ce = engine->preempt_context;
>-		if (ce)
>-			ce->ops->reset(ce);
>-
> 		engine->serial++; /* kernel context lost */
> 		err = engine->resume(engine);
> 
> 		intel_engine_pm_put(engine);
> 		if (err) {
>-			dev_err(i915->drm.dev,
>+			dev_err(gt->i915->drm.dev,
> 				"Failed to restart %s (%d)\n",
> 				engine->name, err);
> 			break;
> 		}
> 	}
>-	intel_gt_pm_put(i915);
>+	intel_gt_pm_put(gt);
> 
> 	return err;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_gt_pm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_gt_pm.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_gt_pm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_gt_pm.h	2019-08-31 15:01:12.025736183 -0500
>@@ -9,19 +9,19 @@
> 
> #include <linux/types.h>
> 
>-struct drm_i915_private;
>+struct intel_gt;
> 
> enum {
> 	INTEL_GT_UNPARK,
> 	INTEL_GT_PARK,
> };
> 
>-void intel_gt_pm_get(struct drm_i915_private *i915);
>-void intel_gt_pm_put(struct drm_i915_private *i915);
>+void intel_gt_pm_get(struct intel_gt *gt);
>+void intel_gt_pm_put(struct intel_gt *gt);
> 
>-void intel_gt_pm_init(struct drm_i915_private *i915);
>+void intel_gt_pm_init_early(struct intel_gt *gt);
> 
>-void intel_gt_sanitize(struct drm_i915_private *i915, bool force);
>-int intel_gt_resume(struct drm_i915_private *i915);
>+void intel_gt_sanitize(struct intel_gt *gt, bool force);
>+int intel_gt_resume(struct intel_gt *gt);
> 
> #endif /* INTEL_GT_PM_H */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_gt_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_gt_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_gt_types.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_gt_types.h	2019-08-31 15:01:12.025736183 -0500
>@@ -0,0 +1,96 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright Â© 2019 Intel Corporation
>+ */
>+
>+#ifndef __INTEL_GT_TYPES__
>+#define __INTEL_GT_TYPES__
>+
>+#include <linux/ktime.h>
>+#include <linux/list.h>
>+#include <linux/mutex.h>
>+#include <linux/notifier.h>
>+#include <linux/spinlock.h>
>+#include <linux/types.h>
>+
>+#include "uc/intel_uc.h"
>+
>+#include "i915_vma.h"
>+#include "intel_reset_types.h"
>+#include "intel_wakeref.h"
>+
>+struct drm_i915_private;
>+struct i915_ggtt;
>+struct intel_uncore;
>+
>+struct intel_hangcheck {
>+	/* For hangcheck timer */
>+#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
>+#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
>+
>+	struct delayed_work work;
>+};
>+
>+struct intel_gt {
>+	struct drm_i915_private *i915;
>+	struct intel_uncore *uncore;
>+	struct i915_ggtt *ggtt;
>+
>+	struct intel_uc uc;
>+
>+	struct intel_gt_timelines {
>+		struct mutex mutex; /* protects list */
>+		struct list_head active_list;
>+
>+		/* Pack multiple timelines' seqnos into the same page */
>+		spinlock_t hwsp_lock;
>+		struct list_head hwsp_free_list;
>+	} timelines;
>+
>+	struct list_head active_rings;
>+
>+	struct intel_wakeref wakeref;
>+
>+	struct list_head closed_vma;
>+	spinlock_t closed_lock; /* guards the list of closed_vma */
>+
>+	struct intel_hangcheck hangcheck;
>+	struct intel_reset reset;
>+
>+	/**
>+	 * Is the GPU currently considered idle, or busy executing
>+	 * userspace requests? Whilst idle, we allow runtime power
>+	 * management to power down the hardware and display clocks.
>+	 * In order to reduce the effect on performance, there
>+	 * is a slight delay before we do so.
>+	 */
>+	intel_wakeref_t awake;
>+
>+	struct blocking_notifier_head pm_notifications;
>+
>+	ktime_t last_init_time;
>+
>+	struct i915_vma *scratch;
>+
>+	u32 pm_imr;
>+	u32 pm_ier;
>+
>+	u32 pm_guc_events;
>+};
>+
>+enum intel_gt_scratch_field {
>+	/* 8 bytes */
>+	INTEL_GT_SCRATCH_FIELD_DEFAULT = 0,
>+
>+	/* 8 bytes */
>+	INTEL_GT_SCRATCH_FIELD_CLEAR_SLM_WA = 128,
>+
>+	/* 8 bytes */
>+	INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128,
>+
>+	/* 8 bytes */
>+	INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
>+
>+};
>+
>+#endif /* __INTEL_GT_TYPES_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_hangcheck.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_hangcheck.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_hangcheck.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_hangcheck.c	2019-08-31 15:01:12.025736183 -0500
>@@ -22,8 +22,10 @@
>  *
>  */
> 
>-#include "intel_reset.h"
> #include "i915_drv.h"
>+#include "intel_engine.h"
>+#include "intel_gt.h"
>+#include "intel_reset.h"
> 
> struct hangcheck {
> 	u64 acthd;
>@@ -57,9 +59,6 @@
> 	int slice;
> 	int subslice;
> 
>-	if (engine->id != RCS0)
>-		return true;
>-
> 	intel_engine_get_instdone(engine, &instdone);
> 
> 	/* There might be unstable subunit states even when
>@@ -103,7 +102,6 @@
> static enum intel_engine_hangcheck_action
> engine_stuck(struct intel_engine_cs *engine, u64 acthd)
> {
>-	struct drm_i915_private *dev_priv = engine->i915;
> 	enum intel_engine_hangcheck_action ha;
> 	u32 tmp;
> 
>@@ -111,7 +109,7 @@
> 	if (ha != ENGINE_DEAD)
> 		return ha;
> 
>-	if (IS_GEN(dev_priv, 2))
>+	if (IS_GEN(engine->i915, 2))
> 		return ENGINE_DEAD;
> 
> 	/* Is the chip hanging on a WAIT_FOR_EVENT?
>@@ -121,8 +119,8 @@
> 	 */
> 	tmp = ENGINE_READ(engine, RING_CTL);
> 	if (tmp & RING_WAIT) {
>-		i915_handle_error(dev_priv, engine->mask, 0,
>-				  "stuck wait on %s", engine->name);
>+		intel_gt_handle_error(engine->gt, engine->mask, 0,
>+				      "stuck wait on %s", engine->name);
> 		ENGINE_WRITE(engine, RING_CTL, tmp);
> 		return ENGINE_WAIT_KICK;
> 	}
>@@ -222,7 +220,7 @@
> 				 I915_ENGINE_WEDGED_TIMEOUT);
> }
> 
>-static void hangcheck_declare_hang(struct drm_i915_private *i915,
>+static void hangcheck_declare_hang(struct intel_gt *gt,
> 				   intel_engine_mask_t hung,
> 				   intel_engine_mask_t stuck)
> {
>@@ -238,12 +236,12 @@
> 		hung &= ~stuck;
> 	len = scnprintf(msg, sizeof(msg),
> 			"%s on ", stuck == hung ? "no progress" : "hang");
>-	for_each_engine_masked(engine, i915, hung, tmp)
>+	for_each_engine_masked(engine, gt->i915, hung, tmp)
> 		len += scnprintf(msg + len, sizeof(msg) - len,
> 				 "%s, ", engine->name);
> 	msg[len-2] = '\0';
> 
>-	return i915_handle_error(i915, hung, I915_ERROR_CAPTURE, "%s", msg);
>+	return intel_gt_handle_error(gt, hung, I915_ERROR_CAPTURE, "%s", msg);
> }
> 
> /*
>@@ -254,11 +252,10 @@
>  * we kick the ring. If we see no progress on three subsequent calls
>  * we assume chip is wedged and try to fix it by resetting the chip.
>  */
>-static void i915_hangcheck_elapsed(struct work_struct *work)
>+static void hangcheck_elapsed(struct work_struct *work)
> {
>-	struct drm_i915_private *dev_priv =
>-		container_of(work, typeof(*dev_priv),
>-			     gpu_error.hangcheck_work.work);
>+	struct intel_gt *gt =
>+		container_of(work, typeof(*gt), hangcheck.work.work);
> 	intel_engine_mask_t hung = 0, stuck = 0, wedged = 0;
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
>@@ -267,13 +264,13 @@
> 	if (!i915_modparams.enable_hangcheck)
> 		return;
> 
>-	if (!READ_ONCE(dev_priv->gt.awake))
>+	if (!READ_ONCE(gt->awake))
> 		return;
> 
>-	if (i915_terminally_wedged(dev_priv))
>+	if (intel_gt_is_wedged(gt))
> 		return;
> 
>-	wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm);
>+	wakeref = intel_runtime_pm_get_if_in_use(&gt->i915->runtime_pm);
> 	if (!wakeref)
> 		return;
> 
>@@ -281,9 +278,9 @@
> 	 * periodically arm the mmio checker to see if we are triggering
> 	 * any invalid access.
> 	 */
>-	intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
>+	intel_uncore_arm_unclaimed_mmio_detection(gt->uncore);
> 
>-	for_each_engine(engine, dev_priv, id) {
>+	for_each_engine(engine, gt->i915, id) {
> 		struct hangcheck hc;
> 
> 		intel_engine_signal_breadcrumbs(engine);
>@@ -305,7 +302,7 @@
> 	if (GEM_SHOW_DEBUG() && (hung | stuck)) {
> 		struct drm_printer p = drm_debug_printer("hangcheck");
> 
>-		for_each_engine(engine, dev_priv, id) {
>+		for_each_engine(engine, gt->i915, id) {
> 			if (intel_engine_is_idle(engine))
> 				continue;
> 
>@@ -314,20 +311,37 @@
> 	}
> 
> 	if (wedged) {
>-		dev_err(dev_priv->drm.dev,
>+		dev_err(gt->i915->drm.dev,
> 			"GPU recovery timed out,"
> 			" cancelling all in-flight rendering.\n");
> 		GEM_TRACE_DUMP();
>-		i915_gem_set_wedged(dev_priv);
>+		intel_gt_set_wedged(gt);
> 	}
> 
> 	if (hung)
>-		hangcheck_declare_hang(dev_priv, hung, stuck);
>+		hangcheck_declare_hang(gt, hung, stuck);
> 
>-	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>+	intel_runtime_pm_put(&gt->i915->runtime_pm, wakeref);
> 
> 	/* Reset timer in case GPU hangs without another request being added */
>-	i915_queue_hangcheck(dev_priv);
>+	intel_gt_queue_hangcheck(gt);
>+}
>+
>+void intel_gt_queue_hangcheck(struct intel_gt *gt)
>+{
>+	unsigned long delay;
>+
>+	if (unlikely(!i915_modparams.enable_hangcheck))
>+		return;
>+
>+	/*
>+	 * Don't continually defer the hangcheck so that it is always run at
>+	 * least once after work has been scheduled on any ring. Otherwise,
>+	 * we will ignore a hung ring if a second ring is kept busy.
>+	 */
>+
>+	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
>+	queue_delayed_work(system_long_wq, &gt->hangcheck.work, delay);
> }
> 
> void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
>@@ -336,10 +350,9 @@
> 	engine->hangcheck.action_timestamp = jiffies;
> }
> 
>-void intel_hangcheck_init(struct drm_i915_private *i915)
>+void intel_gt_init_hangcheck(struct intel_gt *gt)
> {
>-	INIT_DELAYED_WORK(&i915->gpu_error.hangcheck_work,
>-			  i915_hangcheck_elapsed);
>+	INIT_DELAYED_WORK(&gt->hangcheck.work, hangcheck_elapsed);
> }
> 
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_lrc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_lrc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_lrc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_lrc.c	2019-08-31 15:01:12.026736183 -0500
>@@ -136,9 +136,9 @@
> #include "gem/i915_gem_context.h"
> 
> #include "i915_drv.h"
>-#include "i915_gem_render_state.h"
> #include "i915_vgpu.h"
> #include "intel_engine_pm.h"
>+#include "intel_gt.h"
> #include "intel_lrc_reg.h"
> #include "intel_mocs.h"
> #include "intel_reset.h"
>@@ -161,6 +161,8 @@
> #define GEN8_CTX_STATUS_COMPLETED_MASK \
> 	 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
> 
>+#define CTX_DESC_FORCE_RESTORE BIT_ULL(2)
>+
> /* Typical size of the average request (2 pipecontrols and a MI_BB) */
> #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
> #define WA_TAIL_DWORDS 2
>@@ -221,6 +223,26 @@
> 				     struct intel_engine_cs *engine,
> 				     struct intel_ring *ring);
> 
>+static inline u32 intel_hws_preempt_address(struct intel_engine_cs *engine)
>+{
>+	return (i915_ggtt_offset(engine->status_page.vma) +
>+		I915_GEM_HWS_PREEMPT_ADDR);
>+}
>+
>+static inline void
>+ring_set_paused(const struct intel_engine_cs *engine, int state)
>+{
>+	/*
>+	 * We inspect HWS_PREEMPT with a semaphore inside
>+	 * engine->emit_fini_breadcrumb. If the dword is true,
>+	 * the ring is paused as the semaphore will busywait
>+	 * until the dword is false.
>+	 */
>+	engine->status_page.addr[I915_GEM_HWS_PREEMPT] = state;
>+	if (state)
>+		wmb();
>+}
>+
> static inline struct i915_priolist *to_priolist(struct rb_node *rb)
> {
> 	return rb_entry(rb, struct i915_priolist, node);
>@@ -236,6 +258,17 @@
> 	int prio = rq_prio(rq);
> 
> 	/*
>+	 * If this request is special and must not be interrupted at any
>+	 * cost, so be it. Note we are only checking the most recent request
>+	 * in the context and so may be masking an earlier vip request. It
>+	 * is hoped that under the conditions where nopreempt is used, this
>+	 * will not matter (i.e. all requests to that context will be
>+	 * nopreempt for as long as desired).
>+	 */
>+	if (i915_request_has_nopreempt(rq))
>+		prio = I915_PRIORITY_UNPREEMPTABLE;
>+
>+	/*
> 	 * On unwinding the active request, we give it a priority bump
> 	 * if it has completed waiting on any semaphore. If we know that
> 	 * the request has already started, we can prevent an unwanted
>@@ -245,6 +278,7 @@
> 		prio |= I915_PRIORITY_NOSEMAPHORE;
> 
> 	/* Restrict mere WAIT boosts from triggering preemption */
>+	BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK); /* only internal */
> 	return prio | __NO_PREEMPTION;
> }
> 
>@@ -271,10 +305,7 @@
> {
> 	int last_prio;
> 
>-	if (!engine->preempt_context)
>-		return false;
>-
>-	if (i915_request_completed(rq))
>+	if (!intel_engine_has_semaphores(engine))
> 		return false;
> 
> 	/*
>@@ -338,9 +369,6 @@
> assert_priority_queue(const struct i915_request *prev,
> 		      const struct i915_request *next)
> {
>-	const struct intel_engine_execlists *execlists =
>-		&prev->engine->execlists;
>-
> 	/*
> 	 * Without preemption, the prev may refer to the still active element
> 	 * which we refuse to let go.
>@@ -348,7 +376,7 @@
> 	 * Even with preemption, there are times when we think it is better not
> 	 * to preempt and leave an ostensibly lower priority request in flight.
> 	 */
>-	if (port_request(execlists->port) == prev)
>+	if (i915_request_is_active(prev))
> 		return true;
> 
> 	return rq_prio(prev) >= rq_prio(next);
>@@ -442,13 +470,11 @@
> 		struct intel_engine_cs *owner;
> 
> 		if (i915_request_completed(rq))
>-			break;
>+			continue; /* XXX */
> 
> 		__i915_request_unsubmit(rq);
> 		unwind_wa_tail(rq);
> 
>-		GEM_BUG_ON(rq->hw_context->inflight);
>-
> 		/*
> 		 * Push the request back into the queue for later resubmission.
> 		 * If this request is not native to this physical engine (i.e.
>@@ -468,6 +494,19 @@
> 			list_move(&rq->sched.link, pl);
> 			active = rq;
> 		} else {
>+			/*
>+			 * Decouple the virtual breadcrumb before moving it
>+			 * back to the virtual engine -- we don't want the
>+			 * request to complete in the background and try
>+			 * and cancel the breadcrumb on the virtual engine
>+			 * (instead of the old engine where it is linked)!
>+			 */
>+			if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
>+				     &rq->fence.flags)) {
>+				spin_lock(&rq->lock);
>+				i915_request_cancel_breadcrumb(rq);
>+				spin_unlock(&rq->lock);
>+			}
> 			rq->engine = owner;
> 			owner->submit_request(rq);
> 			active = NULL;
>@@ -500,32 +539,32 @@
> 				   status, rq);
> }
> 
>-inline void
>-execlists_user_begin(struct intel_engine_execlists *execlists,
>-		     const struct execlist_port *port)
>+static inline struct i915_request *
>+execlists_schedule_in(struct i915_request *rq, int idx)
> {
>-	execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER);
>-}
>+	struct intel_context *ce = rq->hw_context;
>+	int count;
> 
>-inline void
>-execlists_user_end(struct intel_engine_execlists *execlists)
>-{
>-	execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
>-}
>+	trace_i915_request_in(rq, idx);
> 
>-static inline void
>-execlists_context_schedule_in(struct i915_request *rq)
>-{
>-	GEM_BUG_ON(rq->hw_context->inflight);
>+	count = intel_context_inflight_count(ce);
>+	if (!count) {
>+		intel_context_get(ce);
>+		ce->inflight = rq->engine;
>+
>+		execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
>+		intel_engine_context_in(ce->inflight);
>+	}
>+
>+	intel_context_inflight_inc(ce);
>+	GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
> 
>-	execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
>-	intel_engine_context_in(rq->engine);
>-	rq->hw_context->inflight = rq->engine;
>+	return i915_request_get(rq);
> }
> 
>-static void kick_siblings(struct i915_request *rq)
>+static void kick_siblings(struct i915_request *rq, struct intel_context *ce)
> {
>-	struct virtual_engine *ve = to_virtual_engine(rq->hw_context->engine);
>+	struct virtual_engine *ve = container_of(ce, typeof(*ve), context);
> 	struct i915_request *next = READ_ONCE(ve->request);
> 
> 	if (next && next->execution_mask & ~rq->execution_mask)
>@@ -533,29 +572,42 @@
> }
> 
> static inline void
>-execlists_context_schedule_out(struct i915_request *rq, unsigned long status)
>+execlists_schedule_out(struct i915_request *rq)
> {
>-	rq->hw_context->inflight = NULL;
>-	intel_engine_context_out(rq->engine);
>-	execlists_context_status_change(rq, status);
>+	struct intel_context *ce = rq->hw_context;
>+
>+	GEM_BUG_ON(!intel_context_inflight_count(ce));
>+
> 	trace_i915_request_out(rq);
> 
>-	/*
>-	 * If this is part of a virtual engine, its next request may have
>-	 * been blocked waiting for access to the active context. We have
>-	 * to kick all the siblings again in case we need to switch (e.g.
>-	 * the next request is not runnable on this engine). Hopefully,
>-	 * we will already have submitted the next request before the
>-	 * tasklet runs and do not need to rebuild each virtual tree
>-	 * and kick everyone again.
>-	 */
>-	if (rq->engine != rq->hw_context->engine)
>-		kick_siblings(rq);
>+	intel_context_inflight_dec(ce);
>+	if (!intel_context_inflight_count(ce)) {
>+		intel_engine_context_out(ce->inflight);
>+		execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
>+
>+		/*
>+		 * If this is part of a virtual engine, its next request may
>+		 * have been blocked waiting for access to the active context.
>+		 * We have to kick all the siblings again in case we need to
>+		 * switch (e.g. the next request is not runnable on this
>+		 * engine). Hopefully, we will already have submitted the next
>+		 * request before the tasklet runs and do not need to rebuild
>+		 * each virtual tree and kick everyone again.
>+		 */
>+		ce->inflight = NULL;
>+		if (rq->engine != ce->engine)
>+			kick_siblings(rq, ce);
>+
>+		intel_context_put(ce);
>+	}
>+
>+	i915_request_put(rq);
> }
> 
>-static u64 execlists_update_context(struct i915_request *rq)
>+static u64 execlists_update_context(const struct i915_request *rq)
> {
> 	struct intel_context *ce = rq->hw_context;
>+	u64 desc;
> 
> 	ce->lrc_reg_state[CTX_RING_TAIL + 1] =
> 		intel_ring_set_tail(rq->ring, rq->tail);
>@@ -576,7 +628,11 @@
> 	 * wmb).
> 	 */
> 	mb();
>-	return ce->lrc_desc;
>+
>+	desc = ce->lrc_desc;
>+	ce->lrc_desc &= ~CTX_DESC_FORCE_RESTORE;
>+
>+	return desc;
> }
> 
> static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
>@@ -590,12 +646,62 @@
> 	}
> }
> 
>+static __maybe_unused void
>+trace_ports(const struct intel_engine_execlists *execlists,
>+	    const char *msg,
>+	    struct i915_request * const *ports)
>+{
>+	const struct intel_engine_cs *engine =
>+		container_of(execlists, typeof(*engine), execlists);
>+
>+	GEM_TRACE("%s: %s { %llx:%lld%s, %llx:%lld }\n",
>+		  engine->name, msg,
>+		  ports[0]->fence.context,
>+		  ports[0]->fence.seqno,
>+		  i915_request_completed(ports[0]) ? "!" :
>+		  i915_request_started(ports[0]) ? "*" :
>+		  "",
>+		  ports[1] ? ports[1]->fence.context : 0,
>+		  ports[1] ? ports[1]->fence.seqno : 0);
>+}
>+
>+static __maybe_unused bool
>+assert_pending_valid(const struct intel_engine_execlists *execlists,
>+		     const char *msg)
>+{
>+	struct i915_request * const *port, *rq;
>+	struct intel_context *ce = NULL;
>+
>+	trace_ports(execlists, msg, execlists->pending);
>+
>+	if (execlists->pending[execlists_num_ports(execlists)])
>+		return false;
>+
>+	for (port = execlists->pending; (rq = *port); port++) {
>+		if (ce == rq->hw_context)
>+			return false;
>+
>+		ce = rq->hw_context;
>+		if (i915_request_completed(rq))
>+			continue;
>+
>+		if (i915_active_is_idle(&ce->active))
>+			return false;
>+
>+		if (!i915_vma_is_pinned(ce->state))
>+			return false;
>+	}
>+
>+	return ce;
>+}
>+
> static void execlists_submit_ports(struct intel_engine_cs *engine)
> {
> 	struct intel_engine_execlists *execlists = &engine->execlists;
>-	struct execlist_port *port = execlists->port;
> 	unsigned int n;
> 
>+	GEM_BUG_ON(!assert_pending_valid(execlists, "submit"));
>+
> 	/*
> 	 * We can skip acquiring intel_runtime_pm_get() here as it was taken
> 	 * on our behalf by the request (see i915_gem_mark_busy()) and it will
>@@ -604,7 +710,7 @@
> 	 * that all ELSP are drained i.e. we have processed the CSB,
> 	 * before allowing ourselves to idle and calling intel_runtime_pm_put().
> 	 */
>-	GEM_BUG_ON(!intel_wakeref_active(&engine->wakeref));
>+	GEM_BUG_ON(!intel_engine_pm_is_awake(engine));
> 
> 	/*
> 	 * ELSQ note: the submit queue is not cleared after being submitted
>@@ -613,38 +719,16 @@
> 	 * of elsq entries, keep this in mind before changing the loop below.
> 	 */
> 	for (n = execlists_num_ports(execlists); n--; ) {
>-		struct i915_request *rq;
>-		unsigned int count;
>-		u64 desc;
>+		struct i915_request *rq = execlists->pending[n];
> 
>-		rq = port_unpack(&port[n], &count);
>-		if (rq) {
>-			GEM_BUG_ON(count > !n);
>-			if (!count++)
>-				execlists_context_schedule_in(rq);
>-			port_set(&port[n], port_pack(rq, count));
>-			desc = execlists_update_context(rq);
>-			GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
>-
>-			GEM_TRACE("%s in[%d]:  ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n",
>-				  engine->name, n,
>-				  port[n].context_id, count,
>-				  rq->fence.context, rq->fence.seqno,
>-				  hwsp_seqno(rq),
>-				  rq_prio(rq));
>-		} else {
>-			GEM_BUG_ON(!n);
>-			desc = 0;
>-		}
>-
>-		write_desc(execlists, desc, n);
>+		write_desc(execlists,
>+			   rq ? execlists_update_context(rq) : 0,
>+			   n);
> 	}
> 
> 	/* we need to manually load the submit queue */
> 	if (execlists->ctrl_reg)
> 		writel(EL_CTRL_LOAD, execlists->ctrl_reg);
>-
>-	execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
> }
> 
> static bool ctx_single_port_submission(const struct intel_context *ce)
>@@ -668,6 +752,7 @@
> static bool can_merge_rq(const struct i915_request *prev,
> 			 const struct i915_request *next)
> {
>+	GEM_BUG_ON(prev == next);
> 	GEM_BUG_ON(!assert_priority_queue(prev, next));
> 
> 	if (!can_merge_ctx(prev->hw_context, next->hw_context))
>@@ -676,58 +761,6 @@
> 	return true;
> }
> 
>-static void port_assign(struct execlist_port *port, struct i915_request *rq)
>-{
>-	GEM_BUG_ON(rq == port_request(port));
>-
>-	if (port_isset(port))
>-		i915_request_put(port_request(port));
>-
>-	port_set(port, port_pack(i915_request_get(rq), port_count(port)));
>-}
>-
>-static void inject_preempt_context(struct intel_engine_cs *engine)
>-{
>-	struct intel_engine_execlists *execlists = &engine->execlists;
>-	struct intel_context *ce = engine->preempt_context;
>-	unsigned int n;
>-
>-	GEM_BUG_ON(execlists->preempt_complete_status !=
>-		   upper_32_bits(ce->lrc_desc));
>-
>-	/*
>-	 * Switch to our empty preempt context so
>-	 * the state of the GPU is known (idle).
>-	 */
>-	GEM_TRACE("%s\n", engine->name);
>-	for (n = execlists_num_ports(execlists); --n; )
>-		write_desc(execlists, 0, n);
>-
>-	write_desc(execlists, ce->lrc_desc, n);
>-
>-	/* we need to manually load the submit queue */
>-	if (execlists->ctrl_reg)
>-		writel(EL_CTRL_LOAD, execlists->ctrl_reg);
>-
>-	execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
>-	execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
>-
>-	(void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
>-}
>-
>-static void complete_preempt_context(struct intel_engine_execlists *execlists)
>-{
>-	GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
>-
>-	if (inject_preempt_hang(execlists))
>-		return;
>-
>-	execlists_cancel_port_requests(execlists);
>-	__unwind_incomplete_requests(container_of(execlists,
>-						  struct intel_engine_cs,
>-						  execlists));
>-}
>-
> static void virtual_update_register_offsets(u32 *regs,
> 					    struct intel_engine_cs *engine)
> {
>@@ -792,7 +825,7 @@
> 	 * we reuse the register offsets). This is a very small
> 	 * hystersis on the greedy seelction algorithm.
> 	 */
>-	inflight = READ_ONCE(ve->context.inflight);
>+	inflight = intel_context_inflight(&ve->context);
> 	if (inflight && inflight != engine)
> 		return false;
> 
>@@ -815,13 +848,108 @@
> 	spin_unlock(&old->breadcrumbs.irq_lock);
> }
> 
>+static struct i915_request *
>+last_active(const struct intel_engine_execlists *execlists)
>+{
>+	struct i915_request * const *last = execlists->active;
>+
>+	while (*last && i915_request_completed(*last))
>+		last++;
>+
>+	return *last;
>+}
>+
>+static void defer_request(struct i915_request *rq, struct list_head * const pl)
>+{
>+	LIST_HEAD(list);
>+
>+	/*
>+	 * We want to move the interrupted request to the back of
>+	 * the round-robin list (i.e. its priority level), but
>+	 * in doing so, we must then move all requests that were in
>+	 * flight and were waiting for the interrupted request to
>+	 * be run after it again.
>+	 */
>+	do {
>+		struct i915_dependency *p;
>+
>+		GEM_BUG_ON(i915_request_is_active(rq));
>+		list_move_tail(&rq->sched.link, pl);
>+
>+		list_for_each_entry(p, &rq->sched.waiters_list, wait_link) {
>+			struct i915_request *w =
>+				container_of(p->waiter, typeof(*w), sched);
>+
>+			/* Leave semaphores spinning on the other engines */
>+			if (w->engine != rq->engine)
>+				continue;
>+
>+			/* No waiter should start before its signaler */
>+			GEM_BUG_ON(i915_request_started(w) &&
>+				   !i915_request_completed(rq));
>+
>+			GEM_BUG_ON(i915_request_is_active(w));
>+			if (list_empty(&w->sched.link))
>+				continue; /* Not yet submitted; unready */
>+
>+			if (rq_prio(w) < rq_prio(rq))
>+				continue;
>+
>+			GEM_BUG_ON(rq_prio(w) > rq_prio(rq));
>+			list_move_tail(&w->sched.link, &list);
>+		}
>+
>+		rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
>+	} while (rq);
>+}
>+
>+static void defer_active(struct intel_engine_cs *engine)
>+{
>+	struct i915_request *rq;
>+
>+	rq = __unwind_incomplete_requests(engine);
>+	if (!rq)
>+		return;
>+
>+	defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq)));
>+}
>+
>+static bool
>+need_timeslice(struct intel_engine_cs *engine, const struct i915_request *rq)
>+{
>+	int hint;
>+
>+	if (!intel_engine_has_semaphores(engine))
>+		return false;
>+
>+	if (list_is_last(&rq->sched.link, &engine->active.requests))
>+		return false;
>+
>+	hint = max(rq_prio(list_next_entry(rq, sched.link)),
>+		   engine->execlists.queue_priority_hint);
>+
>+	return hint >= effective_prio(rq);
>+}
>+
>+static bool
>+enable_timeslice(struct intel_engine_cs *engine)
>+{
>+	struct i915_request *last = last_active(&engine->execlists);
>+
>+	return last && need_timeslice(engine, last);
>+}
>+
>+static void record_preemption(struct intel_engine_execlists *execlists)
>+{
>+	(void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
>+}
>+
> static void execlists_dequeue(struct intel_engine_cs *engine)
> {
> 	struct intel_engine_execlists * const execlists = &engine->execlists;
>-	struct execlist_port *port = execlists->port;
>-	const struct execlist_port * const last_port =
>-		&execlists->port[execlists->port_mask];
>-	struct i915_request *last = port_request(port);
>+	struct i915_request **port = execlists->pending;
>+	struct i915_request ** const last_port = port + execlists->port_mask;
>+	struct i915_request *last;
> 	struct rb_node *rb;
> 	bool submit = false;
> 
>@@ -867,65 +995,100 @@
> 		break;
> 	}
> 
>+	/*
>+	 * If the queue is higher priority than the last
>+	 * request in the currently active context, submit afresh.
>+	 * We will resubmit again afterwards in case we need to split
>+	 * the active context to interject the preemption request,
>+	 * i.e. we will retrigger preemption following the ack in case
>+	 * of trouble.
>+	 */
>+	last = last_active(execlists);
> 	if (last) {
>-		/*
>-		 * Don't resubmit or switch until all outstanding
>-		 * preemptions (lite-restore) are seen. Then we
>-		 * know the next preemption status we see corresponds
>-		 * to this ELSP update.
>-		 */
>-		GEM_BUG_ON(!execlists_is_active(execlists,
>-						EXECLISTS_ACTIVE_USER));
>-		GEM_BUG_ON(!port_count(&port[0]));
>+		if (need_preempt(engine, last, rb)) {
>+			GEM_TRACE("%s: preempting last=%llx:%lld, prio=%d, hint=%d\n",
>+				  engine->name,
>+				  last->fence.context,
>+				  last->fence.seqno,
>+				  last->sched.attr.priority,
>+				  execlists->queue_priority_hint);
>+			record_preemption(execlists);
> 
>-		/*
>-		 * If we write to ELSP a second time before the HW has had
>-		 * a chance to respond to the previous write, we can confuse
>-		 * the HW and hit "undefined behaviour". After writing to ELSP,
>-		 * we must then wait until we see a context-switch event from
>-		 * the HW to indicate that it has had a chance to respond.
>-		 */
>-		if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
>-			return;
>+			/*
>+			 * Don't let the RING_HEAD advance past the breadcrumb
>+			 * as we unwind (and until we resubmit) so that we do
>+			 * not accidentally tell it to go backwards.
>+			 */
>+			ring_set_paused(engine, 1);
> 
>-		if (need_preempt(engine, last, rb)) {
>-			inject_preempt_context(engine);
>-			return;
>-		}
>+			/*
>+			 * Note that we have not stopped the GPU at this point,
>+			 * so we are unwinding the incomplete requests as they
>+			 * remain inflight and so by the time we do complete
>+			 * the preemption, some of the unwound requests may
>+			 * complete!
>+			 */
>+			__unwind_incomplete_requests(engine);
> 
>-		/*
>-		 * In theory, we could coalesce more requests onto
>-		 * the second port (the first port is active, with
>-		 * no preemptions pending). However, that means we
>-		 * then have to deal with the possible lite-restore
>-		 * of the second port (as we submit the ELSP, there
>-		 * may be a context-switch) but also we may complete
>-		 * the resubmission before the context-switch. Ergo,
>-		 * coalescing onto the second port will cause a
>-		 * preemption event, but we cannot predict whether
>-		 * that will affect port[0] or port[1].
>-		 *
>-		 * If the second port is already active, we can wait
>-		 * until the next context-switch before contemplating
>-		 * new requests. The GPU will be busy and we should be
>-		 * able to resubmit the new ELSP before it idles,
>-		 * avoiding pipeline bubbles (momentary pauses where
>-		 * the driver is unable to keep up the supply of new
>-		 * work). However, we have to double check that the
>-		 * priorities of the ports haven't been switch.
>-		 */
>-		if (port_count(&port[1]))
>-			return;
>+			/*
>+			 * If we need to return to the preempted context, we
>+			 * need to skip the lite-restore and force it to
>+			 * reload the RING_TAIL. Otherwise, the HW has a
>+			 * tendency to ignore us rewinding the TAIL to the
>+			 * end of an earlier request.
>+			 */
>+			last->hw_context->lrc_desc |= CTX_DESC_FORCE_RESTORE;
>+			last = NULL;
>+		} else if (need_timeslice(engine, last) &&
>+			   !timer_pending(&engine->execlists.timer)) {
>+			GEM_TRACE("%s: expired last=%llx:%lld, prio=%d, hint=%d\n",
>+				  engine->name,
>+				  last->fence.context,
>+				  last->fence.seqno,
>+				  last->sched.attr.priority,
>+				  execlists->queue_priority_hint);
> 
>-		/*
>-		 * WaIdleLiteRestore:bdw,skl
>-		 * Apply the wa NOOPs to prevent
>-		 * ring:HEAD == rq:TAIL as we resubmit the
>-		 * request. See gen8_emit_fini_breadcrumb() for
>-		 * where we prepare the padding after the
>-		 * end of the request.
>-		 */
>-		last->tail = last->wa_tail;
>+			ring_set_paused(engine, 1);
>+			defer_active(engine);
>+
>+			/*
>+			 * Unlike for preemption, if we rewind and continue
>+			 * executing the same context as previously active,
>+			 * the order of execution will remain the same and
>+			 * the tail will only advance. We do not need to
>+			 * force a full context restore, as a lite-restore
>+			 * is sufficient to resample the monotonic TAIL.
>+			 *
>+			 * If we switch to any other context, similarly we
>+			 * will not rewind TAIL of current context, and
>+			 * normal save/restore will preserve state and allow
>+			 * us to later continue executing the same request.
>+			 */
>+			last = NULL;
>+		} else {
>+			/*
>+			 * Otherwise if we already have a request pending
>+			 * for execution after the current one, we can
>+			 * just wait until the next CS event before
>+			 * queuing more. In either case we will force a
>+			 * lite-restore preemption event, but if we wait
>+			 * we hopefully coalesce several updates into a single
>+			 * submission.
>+			 */
>+			if (!list_is_last(&last->sched.link,
>+					  &engine->active.requests))
>+				return;
>+
>+			/*
>+			 * WaIdleLiteRestore:bdw,skl
>+			 * Apply the wa NOOPs to prevent
>+			 * ring:HEAD == rq:TAIL as we resubmit the
>+			 * request. See gen8_emit_fini_breadcrumb() for
>+			 * where we prepare the padding after the
>+			 * end of the request.
>+			 */
>+			last->tail = last->wa_tail;
>+		}
> 	}
> 
> 	while (rb) { /* XXX virtual is always taking precedence */
>@@ -955,9 +1118,24 @@
> 				continue;
> 			}
> 
>+			if (i915_request_completed(rq)) {
>+				ve->request = NULL;
>+				ve->base.execlists.queue_priority_hint = INT_MIN;
>+				rb_erase_cached(rb, &execlists->virtual);
>+				RB_CLEAR_NODE(rb);
>+
>+				rq->engine = engine;
>+				__i915_request_submit(rq);
>+
>+				spin_unlock(&ve->base.active.lock);
>+
>+				rb = rb_first_cached(&execlists->virtual);
>+				continue;
>+			}
>+
> 			if (last && !can_merge_rq(last, rq)) {
> 				spin_unlock(&ve->base.active.lock);
>-				return; /* leave this rq for another engine */
>+				return; /* leave this for another */
> 			}
> 
> 			GEM_TRACE("%s: virtual rq=%llx:%lld%s, new engine? %s\n",
>@@ -1006,9 +1184,10 @@
> 			}
> 
> 			__i915_request_submit(rq);
>-			trace_i915_request_in(rq, port_index(port, execlists));
>-			submit = true;
>-			last = rq;
>+			if (!i915_request_completed(rq)) {
>+				submit = true;
>+				last = rq;
>+			}
> 		}
> 
> 		spin_unlock(&ve->base.active.lock);
>@@ -1021,6 +1200,9 @@
> 		int i;
> 
> 		priolist_for_each_request_consume(rq, rn, p, i) {
>+			if (i915_request_completed(rq))
>+				goto skip;
>+
> 			/*
> 			 * Can we combine this request with the current port?
> 			 * It has to be the same context/ringbuffer and not
>@@ -1060,19 +1242,14 @@
> 				    ctx_single_port_submission(rq->hw_context))
> 					goto done;
> 
>-
>-				if (submit)
>-					port_assign(port, last);
>+				*port = execlists_schedule_in(last, port - execlists->pending);
> 				port++;
>-
>-				GEM_BUG_ON(port_isset(port));
> 			}
> 
>-			__i915_request_submit(rq);
>-			trace_i915_request_in(rq, port_index(port, execlists));
>-
> 			last = rq;
> 			submit = true;
>+skip:
>+			__i915_request_submit(rq);
> 		}
> 
> 		rb_erase_cached(&p->node, &execlists->queue);
>@@ -1097,54 +1274,32 @@
> 	 * interrupt for secondary ports).
> 	 */
> 	execlists->queue_priority_hint = queue_prio(execlists);
>+	GEM_TRACE("%s: queue_priority_hint:%d, submit:%s\n",
>+		  engine->name, execlists->queue_priority_hint,
>+		  yesno(submit));
> 
> 	if (submit) {
>-		port_assign(port, last);
>+		*port = execlists_schedule_in(last, port - execlists->pending);
>+		memset(port + 1, 0, (last_port - port) * sizeof(*port));
> 		execlists_submit_ports(engine);
>+	} else {
>+		ring_set_paused(engine, 0);
> 	}
>-
>-	/* We must always keep the beast fed if we have work piled up */
>-	GEM_BUG_ON(rb_first_cached(&execlists->queue) &&
>-		   !port_isset(execlists->port));
>-
>-	/* Re-evaluate the executing context setup after each preemptive kick */
>-	if (last)
>-		execlists_user_begin(execlists, execlists->port);
>-
>-	/* If the engine is now idle, so should be the flag; and vice versa. */
>-	GEM_BUG_ON(execlists_is_active(&engine->execlists,
>-				       EXECLISTS_ACTIVE_USER) ==
>-		   !port_isset(engine->execlists.port));
> }
> 
> void
> execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
> {
>-	struct execlist_port *port = execlists->port;
>-	unsigned int num_ports = execlists_num_ports(execlists);
>-
>-	while (num_ports-- && port_isset(port)) {
>-		struct i915_request *rq = port_request(port);
>-
>-		GEM_TRACE("%s:port%u fence %llx:%lld, (current %d)\n",
>-			  rq->engine->name,
>-			  (unsigned int)(port - execlists->port),
>-			  rq->fence.context, rq->fence.seqno,
>-			  hwsp_seqno(rq));
>-
>-		GEM_BUG_ON(!execlists->active);
>-		execlists_context_schedule_out(rq,
>-					       i915_request_completed(rq) ?
>-					       INTEL_CONTEXT_SCHEDULE_OUT :
>-					       INTEL_CONTEXT_SCHEDULE_PREEMPTED);
>-
>-		i915_request_put(rq);
>-
>-		memset(port, 0, sizeof(*port));
>-		port++;
>-	}
>+	struct i915_request * const *port, *rq;
> 
>-	execlists_clear_all_active(execlists);
>+	for (port = execlists->pending; (rq = *port); port++)
>+		execlists_schedule_out(rq);
>+	memset(execlists->pending, 0, sizeof(execlists->pending));
>+
>+	for (port = execlists->active; (rq = *port); port++)
>+		execlists_schedule_out(rq);
>+	execlists->active =
>+		memset(execlists->inflight, 0, sizeof(execlists->inflight));
> }
> 
> static inline void
>@@ -1160,10 +1315,33 @@
> 	return unlikely(!__tasklet_is_enabled(&execlists->tasklet));
> }
> 
>+enum csb_step {
>+	CSB_NOP,
>+	CSB_PROMOTE,
>+	CSB_PREEMPT,
>+	CSB_COMPLETE,
>+};
>+
>+static inline enum csb_step
>+csb_parse(const struct intel_engine_execlists *execlists, const u32 *csb)
>+{
>+	unsigned int status = *csb;
>+
>+	if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
>+		return CSB_PROMOTE;
>+
>+	if (status & GEN8_CTX_STATUS_PREEMPTED)
>+		return CSB_PREEMPT;
>+
>+	if (*execlists->active)
>+		return CSB_COMPLETE;
>+
>+	return CSB_NOP;
>+}
>+
> static void process_csb(struct intel_engine_cs *engine)
> {
> 	struct intel_engine_execlists * const execlists = &engine->execlists;
>-	struct execlist_port *port = execlists->port;
> 	const u32 * const buf = execlists->csb_status;
> 	const u8 num_entries = execlists->csb_size;
> 	u8 head, tail;
>@@ -1198,10 +1376,6 @@
> 	rmb();
> 
> 	do {
>-		struct i915_request *rq;
>-		unsigned int status;
>-		unsigned int count;
>-
> 		if (++head == num_entries)
> 			head = 0;
> 
>@@ -1223,68 +1397,39 @@
> 		 * status notifier.
> 		 */
> 
>-		GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n",
>+		GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x\n",
> 			  engine->name, head,
>-			  buf[2 * head + 0], buf[2 * head + 1],
>-			  execlists->active);
>-
>-		status = buf[2 * head];
>-		if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
>-			      GEN8_CTX_STATUS_PREEMPTED))
>-			execlists_set_active(execlists,
>-					     EXECLISTS_ACTIVE_HWACK);
>-		if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
>-			execlists_clear_active(execlists,
>-					       EXECLISTS_ACTIVE_HWACK);
>-
>-		if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
>-			continue;
>-
>-		/* We should never get a COMPLETED | IDLE_ACTIVE! */
>-		GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);
>+			  buf[2 * head + 0], buf[2 * head + 1]);
> 
>-		if (status & GEN8_CTX_STATUS_COMPLETE &&
>-		    buf[2*head + 1] == execlists->preempt_complete_status) {
>-			GEM_TRACE("%s preempt-idle\n", engine->name);
>-			complete_preempt_context(execlists);
>-			continue;
>-		}
>+		switch (csb_parse(execlists, buf + 2 * head)) {
>+		case CSB_PREEMPT: /* cancel old inflight, prepare for switch */
>+			trace_ports(execlists, "preempted", execlists->active);
>+
>+			while (*execlists->active)
>+				execlists_schedule_out(*execlists->active++);
>+
>+			/* fallthrough */
>+		case CSB_PROMOTE: /* switch pending to inflight */
>+			GEM_BUG_ON(*execlists->active);
>+			GEM_BUG_ON(!assert_pending_valid(execlists, "promote"));
>+			execlists->active =
>+				memcpy(execlists->inflight,
>+				       execlists->pending,
>+				       execlists_num_ports(execlists) *
>+				       sizeof(*execlists->pending));
>+			execlists->pending[0] = NULL;
> 
>-		if (status & GEN8_CTX_STATUS_PREEMPTED &&
>-		    execlists_is_active(execlists,
>-					EXECLISTS_ACTIVE_PREEMPT))
>-			continue;
>+			trace_ports(execlists, "promoted", execlists->active);
> 
>-		GEM_BUG_ON(!execlists_is_active(execlists,
>-						EXECLISTS_ACTIVE_USER));
>+			if (enable_timeslice(engine))
>+				mod_timer(&execlists->timer, jiffies + 1);
> 
>-		rq = port_unpack(port, &count);
>-		GEM_TRACE("%s out[0]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n",
>-			  engine->name,
>-			  port->context_id, count,
>-			  rq ? rq->fence.context : 0,
>-			  rq ? rq->fence.seqno : 0,
>-			  rq ? hwsp_seqno(rq) : 0,
>-			  rq ? rq_prio(rq) : 0);
>+			if (!inject_preempt_hang(execlists))
>+				ring_set_paused(engine, 0);
>+			break;
> 
>-		/* Check the context/desc id for this event matches */
>-		GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
>-
>-		GEM_BUG_ON(count == 0);
>-		if (--count == 0) {
>-			/*
>-			 * On the final event corresponding to the
>-			 * submission of this context, we expect either
>-			 * an element-switch event or a completion
>-			 * event (and on completion, the active-idle
>-			 * marker). No more preemptions, lite-restore
>-			 * or otherwise.
>-			 */
>-			GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
>-			GEM_BUG_ON(port_isset(&port[1]) &&
>-				   !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH));
>-			GEM_BUG_ON(!port_isset(&port[1]) &&
>-				   !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
>+		case CSB_COMPLETE: /* port0 completed, advanced to port1 */
>+			trace_ports(execlists, "completed", execlists->active);
> 
> 			/*
> 			 * We rely on the hardware being strongly
>@@ -1292,22 +1437,16 @@
> 			 * coherent (visible from the CPU) before the
> 			 * user interrupt and CSB is processed.
> 			 */
>-			GEM_BUG_ON(!i915_request_completed(rq));
>+			GEM_BUG_ON(!i915_request_completed(*execlists->active) &&
>+				   !reset_in_progress(execlists));
>+			execlists_schedule_out(*execlists->active++);
> 
>-			execlists_context_schedule_out(rq,
>-						       INTEL_CONTEXT_SCHEDULE_OUT);
>-			i915_request_put(rq);
>-
>-			GEM_TRACE("%s completed ctx=%d\n",
>-				  engine->name, port->context_id);
>-
>-			port = execlists_port_complete(execlists, port);
>-			if (port_isset(port))
>-				execlists_user_begin(execlists, port);
>-			else
>-				execlists_user_end(execlists);
>-		} else {
>-			port_set(port, port_pack(rq, count));
>+			GEM_BUG_ON(execlists->active - execlists->inflight >
>+				   execlists_num_ports(execlists));
>+			break;
>+
>+		case CSB_NOP:
>+			break;
> 		}
> 	} while (head != tail);
> 
>@@ -1332,7 +1471,7 @@
> 	lockdep_assert_held(&engine->active.lock);
> 
> 	process_csb(engine);
>-	if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT))
>+	if (!engine->execlists.pending[0])
> 		execlists_dequeue(engine);
> }
> 
>@@ -1345,16 +1484,20 @@
> 	struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
> 	unsigned long flags;
> 
>-	GEM_TRACE("%s awake?=%d, active=%x\n",
>-		  engine->name,
>-		  !!intel_wakeref_active(&engine->wakeref),
>-		  engine->execlists.active);
>-
> 	spin_lock_irqsave(&engine->active.lock, flags);
> 	__execlists_submission_tasklet(engine);
> 	spin_unlock_irqrestore(&engine->active.lock, flags);
> }
> 
>+static void execlists_submission_timer(struct timer_list *timer)
>+{
>+	struct intel_engine_cs *engine =
>+		from_timer(engine, timer, execlists.timer);
>+
>+	/* Kick the tasklet for some interrupt coalescing and reset handling */
>+	tasklet_hi_schedule(&engine->execlists.tasklet);
>+}
>+
> static void queue_request(struct intel_engine_cs *engine,
> 			  struct i915_sched_node *node,
> 			  int prio)
>@@ -1376,12 +1519,16 @@
> 		tasklet_hi_schedule(&execlists->tasklet);
> }
> 
>-static void submit_queue(struct intel_engine_cs *engine, int prio)
>+static void submit_queue(struct intel_engine_cs *engine,
>+			 const struct i915_request *rq)
> {
>-	if (prio > engine->execlists.queue_priority_hint) {
>-		engine->execlists.queue_priority_hint = prio;
>-		__submit_queue_imm(engine);
>-	}
>+	struct intel_engine_execlists *execlists = &engine->execlists;
>+
>+	if (rq_prio(rq) <= execlists->queue_priority_hint)
>+		return;
>+
>+	execlists->queue_priority_hint = rq_prio(rq);
>+	__submit_queue_imm(engine);
> }
> 
> static void execlists_submit_request(struct i915_request *request)
>@@ -1397,7 +1544,7 @@
> 	GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
> 	GEM_BUG_ON(list_empty(&request->sched.link));
> 
>-	submit_queue(engine, rq_prio(request));
>+	submit_queue(engine, request);
> 
> 	spin_unlock_irqrestore(&engine->active.lock, flags);
> }
>@@ -1405,9 +1552,7 @@
> static void __execlists_context_fini(struct intel_context *ce)
> {
> 	intel_ring_put(ce->ring);
>-
>-	GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
>-	i915_gem_object_put(ce->state->obj);
>+	i915_vma_put(ce->state);
> }
> 
> static void execlists_context_destroy(struct kref *kref)
>@@ -1420,6 +1565,7 @@
> 	if (ce->state)
> 		__execlists_context_fini(ce);
> 
>+	intel_context_fini(ce);
> 	intel_context_free(ce);
> }
> 
>@@ -1444,9 +1590,12 @@
> 	regs[CTX_RING_TAIL + 1] = ring->tail;
> 
> 	/* RPCS */
>-	if (engine->class == RENDER_CLASS)
>+	if (engine->class == RENDER_CLASS) {
> 		regs[CTX_R_PWR_CLK_STATE + 1] =
> 			intel_sseu_make_rpcs(engine->i915, &ce->sseu);
>+
>+		i915_oa_init_reg_state(engine, ce, regs);
>+	}
> }
> 
> static int
>@@ -1456,19 +1605,15 @@
> 	void *vaddr;
> 	int ret;
> 
>-	GEM_BUG_ON(!ce->gem_context->vm);
>-
> 	ret = execlists_context_deferred_alloc(ce, engine);
> 	if (ret)
> 		goto err;
> 	GEM_BUG_ON(!ce->state);
> 
>-	ret = intel_context_active_acquire(ce,
>-					   engine->i915->ggtt.pin_bias |
>-					   PIN_OFFSET_BIAS |
>-					   PIN_HIGH);
>+	ret = intel_context_active_acquire(ce);
> 	if (ret)
> 		goto err;
>+	GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
> 
> 	vaddr = i915_gem_object_pin_map(ce->state->obj,
> 					i915_coherent_map_type(engine->i915) |
>@@ -1569,8 +1714,7 @@
> static int emit_pdps(struct i915_request *rq)
> {
> 	const struct intel_engine_cs * const engine = rq->engine;
>-	struct i915_ppgtt * const ppgtt =
>-		i915_vm_to_ppgtt(rq->gem_context->vm);
>+	struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(rq->hw_context->vm);
> 	int err, i;
> 	u32 *cs;
> 
>@@ -1643,7 +1787,7 @@
> 	 */
> 
> 	/* Unconditionally invalidate GPU caches and TLBs. */
>-	if (i915_vm_is_4lvl(request->gem_context->vm))
>+	if (i915_vm_is_4lvl(request->hw_context->vm))
> 		ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
> 	else
> 		ret = emit_pdps(request);
>@@ -1676,7 +1820,8 @@
> 	/* NB no one else is allowed to scribble over scratch + 256! */
> 	*batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
> 	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
>-	*batch++ = i915_scratch_offset(engine->i915) + 256;
>+	*batch++ = intel_gt_scratch_offset(engine->gt,
>+					   INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
> 	*batch++ = 0;
> 
> 	*batch++ = MI_LOAD_REGISTER_IMM(1);
>@@ -1690,12 +1835,19 @@
> 
> 	*batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
> 	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
>-	*batch++ = i915_scratch_offset(engine->i915) + 256;
>+	*batch++ = intel_gt_scratch_offset(engine->gt,
>+					   INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
> 	*batch++ = 0;
> 
> 	return batch;
> }
> 
>+static u32 slm_offset(struct intel_engine_cs *engine)
>+{
>+	return intel_gt_scratch_offset(engine->gt,
>+				       INTEL_GT_SCRATCH_FIELD_CLEAR_SLM_WA);
>+}
>+
> /*
>  * Typically we only have one indirect_ctx and per_ctx batch buffer which are
>  * initialized at the beginning and shared across all contexts but this field
>@@ -1727,8 +1879,7 @@
> 				       PIPE_CONTROL_GLOBAL_GTT_IVB |
> 				       PIPE_CONTROL_CS_STALL |
> 				       PIPE_CONTROL_QW_WRITE,
>-				       i915_scratch_offset(engine->i915) +
>-				       2 * CACHELINE_BYTES);
>+				       slm_offset(engine));
> 
> 	*batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
> 
>@@ -1874,7 +2025,7 @@
> 	if (IS_ERR(obj))
> 		return PTR_ERR(obj);
> 
>-	vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
>+	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
> 	if (IS_ERR(vma)) {
> 		err = PTR_ERR(vma);
> 		goto err;
>@@ -1970,22 +2121,23 @@
> 
> static void enable_execlists(struct intel_engine_cs *engine)
> {
>+	u32 mode;
>+
>+	assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
>+
> 	intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
> 
> 	if (INTEL_GEN(engine->i915) >= 11)
>-		ENGINE_WRITE(engine,
>-			     RING_MODE_GEN7,
>-			     _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
>+		mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
> 	else
>-		ENGINE_WRITE(engine,
>-			     RING_MODE_GEN7,
>-			     _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
>-
>-	ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
>-
>-	ENGINE_WRITE(engine,
>-		     RING_HWS_PGA,
>-		     i915_ggtt_offset(engine->status_page.vma));
>+		mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
>+	ENGINE_WRITE_FW(engine, RING_MODE_GEN7, mode);
>+
>+	ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
>+
>+	ENGINE_WRITE_FW(engine,
>+			RING_HWS_PGA,
>+			i915_ggtt_offset(engine->status_page.vma));
> 	ENGINE_POSTING_READ(engine, RING_HWS_PGA);
> }
> 
>@@ -1993,7 +2145,7 @@
> {
> 	bool unexpected = false;
> 
>-	if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) {
>+	if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) {
> 		DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
> 		unexpected = true;
> 	}
>@@ -2041,34 +2193,32 @@
> 	__tasklet_disable_sync_once(&execlists->tasklet);
> 	GEM_BUG_ON(!reset_in_progress(execlists));
> 
>-	intel_engine_stop_cs(engine);
>-
> 	/* And flush any current direct submission. */
> 	spin_lock_irqsave(&engine->active.lock, flags);
> 	spin_unlock_irqrestore(&engine->active.lock, flags);
>-}
>-
>-static bool lrc_regs_ok(const struct i915_request *rq)
>-{
>-	const struct intel_ring *ring = rq->ring;
>-	const u32 *regs = rq->hw_context->lrc_reg_state;
>-
>-	/* Quick spot check for the common signs of context corruption */
> 
>-	if (regs[CTX_RING_BUFFER_CONTROL + 1] !=
>-	    (RING_CTL_SIZE(ring->size) | RING_VALID))
>-		return false;
>-
>-	if (regs[CTX_RING_BUFFER_START + 1] != i915_ggtt_offset(ring->vma))
>-		return false;
>-
>-	return true;
>+	/*
>+	 * We stop engines, otherwise we might get failed reset and a
>+	 * dead gpu (on elk). Also as modern gpu as kbl can suffer
>+	 * from system hang if batchbuffer is progressing when
>+	 * the reset is issued, regardless of READY_TO_RESET ack.
>+	 * Thus assume it is best to stop engines on all gens
>+	 * where we have a gpu reset.
>+	 *
>+	 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
>+	 *
>+	 * FIXME: Wa for more modern gens needs to be validated
>+	 */
>+	intel_engine_stop_cs(engine);
> }
> 
>-static void reset_csb_pointers(struct intel_engine_execlists *execlists)
>+static void reset_csb_pointers(struct intel_engine_cs *engine)
> {
>+	struct intel_engine_execlists * const execlists = &engine->execlists;
> 	const unsigned int reset_value = execlists->csb_size - 1;
> 
>+	ring_set_paused(engine, 0);
>+
> 	/*
> 	 * After a reset, the HW starts writing into CSB entry [0]. We
> 	 * therefore have to set our HEAD pointer back one entry so that
>@@ -2115,18 +2265,21 @@
> 	process_csb(engine); /* drain preemption events */
> 
> 	/* Following the reset, we need to reload the CSB read/write pointers */
>-	reset_csb_pointers(&engine->execlists);
>+	reset_csb_pointers(engine);
> 
> 	/*
> 	 * Save the currently executing context, even if we completed
> 	 * its request, it was still running at the time of the
> 	 * reset and will have been clobbered.
> 	 */
>-	if (!port_isset(execlists->port))
>-		goto out_clear;
>+	rq = execlists_active(execlists);
>+	if (!rq)
>+		goto unwind;
> 
>-	rq = port_request(execlists->port);
> 	ce = rq->hw_context;
>+	GEM_BUG_ON(i915_active_is_idle(&ce->active));
>+	GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
>+	rq = active_request(rq);
> 
> 	/*
> 	 * Catch up with any missed context-switch interrupts.
>@@ -2139,9 +2292,12 @@
> 	 */
> 	execlists_cancel_port_requests(execlists);
> 
>-	rq = active_request(rq);
>-	if (!rq)
>+	if (!rq) {
>+		ce->ring->head = ce->ring->tail;
> 		goto out_replay;
>+	}
>+
>+	ce->ring->head = intel_ring_wrap(ce->ring, rq->head);
> 
> 	/*
> 	 * If this request hasn't started yet, e.g. it is waiting on a
>@@ -2155,7 +2311,7 @@
> 	 * Otherwise, if we have not started yet, the request should replay
> 	 * perfectly and we do not need to flag the result as being erroneous.
> 	 */
>-	if (!i915_request_started(rq) && lrc_regs_ok(rq))
>+	if (!i915_request_started(rq))
> 		goto out_replay;
> 
> 	/*
>@@ -2169,8 +2325,8 @@
> 	 * and have to at least restore the RING register in the context
> 	 * image back to the expected values to skip over the guilty request.
> 	 */
>-	i915_reset_request(rq, stalled);
>-	if (!stalled && lrc_regs_ok(rq))
>+	__i915_request_reset(rq, stalled);
>+	if (!stalled)
> 		goto out_replay;
> 
> 	/*
>@@ -2190,17 +2346,14 @@
> 	execlists_init_reg_state(regs, ce, engine, ce->ring);
> 
> out_replay:
>-	/* Rerun the request; its payload has been neutered (if guilty). */
>-	ce->ring->head =
>-		rq ? intel_ring_wrap(ce->ring, rq->head) : ce->ring->tail;
>+	GEM_TRACE("%s replay {head:%04x, tail:%04x\n",
>+		  engine->name, ce->ring->head, ce->ring->tail);
> 	intel_ring_update_space(ce->ring);
> 	__execlists_update_reg_state(ce, engine);
> 
>+unwind:
> 	/* Push back any incomplete requests for replay after the reset. */
> 	__unwind_incomplete_requests(engine);
>-
>-out_clear:
>-	execlists_clear_all_active(execlists);
> }
> 
> static void execlists_reset(struct intel_engine_cs *engine, bool stalled)
>@@ -2296,7 +2449,6 @@
> 
> 	execlists->queue_priority_hint = INT_MIN;
> 	execlists->queue = RB_ROOT_CACHED;
>-	GEM_BUG_ON(port_isset(execlists->port));
> 
> 	GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));
> 	execlists->tasklet.func = nop_submission_tasklet;
>@@ -2434,7 +2586,8 @@
> {
> 	struct intel_engine_cs *engine = request->engine;
> 	u32 scratch_addr =
>-		i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES;
>+		intel_gt_scratch_offset(engine->gt,
>+					INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
> 	bool vf_flush_wa = false, dc_flush_wa = false;
> 	u32 *cs, flags = 0;
> 	int len;
>@@ -2514,15 +2667,30 @@
> 	return cs;
> }
> 
>+static u32 *emit_preempt_busywait(struct i915_request *request, u32 *cs)
>+{
>+	*cs++ = MI_SEMAPHORE_WAIT |
>+		MI_SEMAPHORE_GLOBAL_GTT |
>+		MI_SEMAPHORE_POLL |
>+		MI_SEMAPHORE_SAD_EQ_SDD;
>+	*cs++ = 0;
>+	*cs++ = intel_hws_preempt_address(request->engine);
>+	*cs++ = 0;
>+
>+	return cs;
>+}
>+
> static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs)
> {
> 	cs = gen8_emit_ggtt_write(cs,
> 				  request->fence.seqno,
> 				  request->timeline->hwsp_offset,
> 				  0);
>-
> 	*cs++ = MI_USER_INTERRUPT;
>+
> 	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
>+	if (intel_engine_has_semaphores(request->engine))
>+		cs = emit_preempt_busywait(request, cs);
> 
> 	request->tail = intel_ring_offset(request, cs);
> 	assert_ring_tail_valid(request->ring, request->tail);
>@@ -2543,9 +2711,11 @@
> 				    PIPE_CONTROL_FLUSH_ENABLE |
> 				    PIPE_CONTROL_CS_STALL,
> 				    0);
>-
> 	*cs++ = MI_USER_INTERRUPT;
>+
> 	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
>+	if (intel_engine_has_semaphores(request->engine))
>+		cs = emit_preempt_busywait(request, cs);
> 
> 	request->tail = intel_ring_offset(request, cs);
> 	assert_ring_tail_valid(request->ring, request->tail);
>@@ -2553,27 +2723,9 @@
> 	return gen8_emit_wa_tail(request, cs);
> }
> 
>-static int gen8_init_rcs_context(struct i915_request *rq)
>-{
>-	int ret;
>-
>-	ret = intel_engine_emit_ctx_wa(rq);
>-	if (ret)
>-		return ret;
>-
>-	ret = intel_rcs_context_init_mocs(rq);
>-	/*
>-	 * Failing to program the MOCS is non-fatal.The system will not
>-	 * run at peak performance. So generate an error and carry on.
>-	 */
>-	if (ret)
>-		DRM_ERROR("MOCS failed to program: expect performance issues.\n");
>-
>-	return i915_gem_render_state_emit(rq);
>-}
>-
> static void execlists_park(struct intel_engine_cs *engine)
> {
>+	del_timer_sync(&engine->execlists.timer);
> 	intel_engine_park(engine);
> }
> 
>@@ -2592,11 +2744,11 @@
> 	engine->unpark = NULL;
> 
> 	engine->flags |= I915_ENGINE_SUPPORTS_STATS;
>-	if (!intel_vgpu_active(engine->i915))
>+	if (!intel_vgpu_active(engine->i915)) {
> 		engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
>-	if (engine->preempt_context &&
>-	    HAS_LOGICAL_RING_PREEMPTION(engine->i915))
>-		engine->flags |= I915_ENGINE_HAS_PREEMPTION;
>+		if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
>+			engine->flags |= I915_ENGINE_HAS_PREEMPTION;
>+	}
> }
> 
> static void execlists_destroy(struct intel_engine_cs *engine)
>@@ -2672,12 +2824,12 @@
> 
> 	tasklet_init(&engine->execlists.tasklet,
> 		     execlists_submission_tasklet, (unsigned long)engine);
>+	timer_setup(&engine->execlists.timer, execlists_submission_timer, 0);
> 
> 	logical_ring_default_vfuncs(engine);
> 	logical_ring_default_irqs(engine);
> 
> 	if (engine->class == RENDER_CLASS) {
>-		engine->init_context = gen8_init_rcs_context;
> 		engine->emit_flush = gen8_emit_flush_render;
> 		engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
> 	}
>@@ -2697,9 +2849,6 @@
> 	if (ret)
> 		return ret;
> 
>-	intel_engine_init_workarounds(engine);
>-	intel_engine_init_whitelist(engine);
>-
> 	if (intel_init_workaround_bb(engine))
> 		/*
> 		 * We continue even if we fail to initialize WA batch
>@@ -2718,11 +2867,6 @@
> 			i915_mmio_reg_offset(RING_ELSP(base));
> 	}
> 
>-	execlists->preempt_complete_status = ~0u;
>-	if (engine->preempt_context)
>-		execlists->preempt_complete_status =
>-			upper_32_bits(engine->preempt_context->lrc_desc);
>-
> 	execlists->csb_status =
> 		&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
> 
>@@ -2734,7 +2878,7 @@
> 	else
> 		execlists->csb_size = GEN11_CSB_ENTRIES;
> 
>-	reset_csb_pointers(execlists);
>+	reset_csb_pointers(engine);
> 
> 	return 0;
> }
>@@ -2773,7 +2917,7 @@
> 				     struct intel_engine_cs *engine,
> 				     struct intel_ring *ring)
> {
>-	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->gem_context->vm);
>+	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
> 	bool rcs = engine->class == RENDER_CLASS;
> 	u32 base = engine->mmio_base;
> 
>@@ -2864,8 +3008,6 @@
> 	if (rcs) {
> 		regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
> 		CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
>-
>-		i915_oa_init_reg_state(engine, ce, regs);
> 	}
> 
> 	regs[CTX_END] = MI_BATCH_BUFFER_END;
>@@ -2917,11 +3059,6 @@
> 	if (!engine->default_state)
> 		regs[CTX_CONTEXT_CONTROL + 1] |=
> 			_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
>-	if (ce->gem_context == engine->i915->preempt_context &&
>-	    INTEL_GEN(engine->i915) < 11)
>-		regs[CTX_CONTEXT_CONTROL + 1] |=
>-			_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
>-					   CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
> 
> 	ret = 0;
> err_unpin_ctx:
>@@ -2932,12 +3069,13 @@
> 	return ret;
> }
> 
>-static struct i915_timeline *get_timeline(struct i915_gem_context *ctx)
>+static struct intel_timeline *
>+get_timeline(struct i915_gem_context *ctx, struct intel_gt *gt)
> {
> 	if (ctx->timeline)
>-		return i915_timeline_get(ctx->timeline);
>+		return intel_timeline_get(ctx->timeline);
> 	else
>-		return i915_timeline_create(ctx->i915, NULL);
>+		return intel_timeline_create(gt, NULL);
> }
> 
> static int execlists_context_deferred_alloc(struct intel_context *ce,
>@@ -2947,7 +3085,7 @@
> 	struct i915_vma *vma;
> 	u32 context_size;
> 	struct intel_ring *ring;
>-	struct i915_timeline *timeline;
>+	struct intel_timeline *timeline;
> 	int ret;
> 
> 	if (ce->state)
>@@ -2965,13 +3103,13 @@
> 	if (IS_ERR(ctx_obj))
> 		return PTR_ERR(ctx_obj);
> 
>-	vma = i915_vma_instance(ctx_obj, &engine->i915->ggtt.vm, NULL);
>+	vma = i915_vma_instance(ctx_obj, &engine->gt->ggtt->vm, NULL);
> 	if (IS_ERR(vma)) {
> 		ret = PTR_ERR(vma);
> 		goto error_deref_obj;
> 	}
> 
>-	timeline = get_timeline(ce->gem_context);
>+	timeline = get_timeline(ce->gem_context, engine->gt);
> 	if (IS_ERR(timeline)) {
> 		ret = PTR_ERR(timeline);
> 		goto error_deref_obj;
>@@ -2980,7 +3118,7 @@
> 	ring = intel_engine_create_ring(engine,
> 					timeline,
> 					ce->gem_context->ring_size);
>-	i915_timeline_put(timeline);
>+	intel_timeline_put(timeline);
> 	if (IS_ERR(ring)) {
> 		ret = PTR_ERR(ring);
> 		goto error_deref_obj;
>@@ -3038,6 +3176,7 @@
> 
> 	if (ve->context.state)
> 		__execlists_context_fini(&ve->context);
>+	intel_context_fini(&ve->context);
> 
> 	kfree(ve->bonds);
> 	kfree(ve);
>@@ -3290,11 +3429,11 @@
> 		return ERR_PTR(-ENOMEM);
> 
> 	ve->base.i915 = ctx->i915;
>+	ve->base.gt = siblings[0]->gt;
> 	ve->base.id = -1;
> 	ve->base.class = OTHER_CLASS;
> 	ve->base.uabi_class = I915_ENGINE_CLASS_INVALID;
> 	ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
>-	ve->base.flags = I915_ENGINE_IS_VIRTUAL;
> 
> 	/*
> 	 * The decision on whether to submit a request using semaphores
>@@ -3391,8 +3530,12 @@
> 		ve->base.emit_fini_breadcrumb = sibling->emit_fini_breadcrumb;
> 		ve->base.emit_fini_breadcrumb_dw =
> 			sibling->emit_fini_breadcrumb_dw;
>+
>+		ve->base.flags = sibling->flags;
> 	}
> 
>+	ve->base.flags |= I915_ENGINE_IS_VIRTUAL;
>+
> 	return &ve->context;
> 
> err_put:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_mocs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_mocs.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_mocs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_mocs.c	2019-08-31 15:01:12.026736183 -0500
>@@ -23,6 +23,7 @@
> #include "i915_drv.h"
> 
> #include "intel_engine.h"
>+#include "intel_gt.h"
> #include "intel_mocs.h"
> #include "intel_lrc.h"
> 
>@@ -247,7 +248,7 @@
> 
> /**
>  * get_mocs_settings()
>- * @dev_priv:	i915 device.
>+ * @gt:		gt device
>  * @table:      Output table that will be made to point at appropriate
>  *	      MOCS values for the device.
>  *
>@@ -257,33 +258,34 @@
>  *
>  * Return: true if there are applicable MOCS settings for the device.
>  */
>-static bool get_mocs_settings(struct drm_i915_private *dev_priv,
>+static bool get_mocs_settings(struct intel_gt *gt,
> 			      struct drm_i915_mocs_table *table)
> {
>+	struct drm_i915_private *i915 = gt->i915;
> 	bool result = false;
> 
>-	if (INTEL_GEN(dev_priv) >= 11) {
>+	if (INTEL_GEN(i915) >= 11) {
> 		table->size  = ARRAY_SIZE(icelake_mocs_table);
> 		table->table = icelake_mocs_table;
> 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> 		result = true;
>-	} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>+	} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
> 		table->size  = ARRAY_SIZE(skylake_mocs_table);
> 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> 		table->table = skylake_mocs_table;
> 		result = true;
>-	} else if (IS_GEN9_LP(dev_priv)) {
>+	} else if (IS_GEN9_LP(i915)) {
> 		table->size  = ARRAY_SIZE(broxton_mocs_table);
> 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> 		table->table = broxton_mocs_table;
> 		result = true;
> 	} else {
>-		WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
>+		WARN_ONCE(INTEL_GEN(i915) >= 9,
> 			  "Platform that should have a MOCS table does not.\n");
> 	}
> 
> 	/* WaDisableSkipCaching:skl,bxt,kbl,glk */
>-	if (IS_GEN(dev_priv, 9)) {
>+	if (IS_GEN(i915, 9)) {
> 		int i;
> 
> 		for (i = 0; i < table->size; i++)
>@@ -338,12 +340,16 @@
>  */
> void intel_mocs_init_engine(struct intel_engine_cs *engine)
> {
>-	struct drm_i915_private *dev_priv = engine->i915;
>+	struct intel_gt *gt = engine->gt;
>+	struct intel_uncore *uncore = gt->uncore;
> 	struct drm_i915_mocs_table table;
> 	unsigned int index;
> 	u32 unused_value;
> 
>-	if (!get_mocs_settings(dev_priv, &table))
>+	/* Called under a blanket forcewake */
>+	assert_forcewakes_active(uncore, FORCEWAKE_ALL);
>+
>+	if (!get_mocs_settings(gt, &table))
> 		return;
> 
> 	/* Set unused values to PTE */
>@@ -352,12 +358,16 @@
> 	for (index = 0; index < table.size; index++) {
> 		u32 value = get_entry_control(&table, index);
> 
>-		I915_WRITE(mocs_register(engine->id, index), value);
>+		intel_uncore_write_fw(uncore,
>+				      mocs_register(engine->id, index),
>+				      value);
> 	}
> 
> 	/* All remaining entries are also unused */
> 	for (; index < table.n_entries; index++)
>-		I915_WRITE(mocs_register(engine->id, index), unused_value);
>+		intel_uncore_write_fw(uncore,
>+				      mocs_register(engine->id, index),
>+				      unused_value);
> }
> 
> /**
>@@ -490,7 +500,7 @@
> 
> /**
>  * intel_mocs_init_l3cc_table() - program the mocs control table
>- * @dev_priv:      i915 device private
>+ * @gt: the intel_gt container
>  *
>  * This function simply programs the mocs registers for the given table
>  * starting at the given address. This register set is  programmed in pairs.
>@@ -502,13 +512,14 @@
>  *
>  * Return: Nothing.
>  */
>-void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
>+void intel_mocs_init_l3cc_table(struct intel_gt *gt)
> {
>+	struct intel_uncore *uncore = gt->uncore;
> 	struct drm_i915_mocs_table table;
> 	unsigned int i;
> 	u16 unused_value;
> 
>-	if (!get_mocs_settings(dev_priv, &table))
>+	if (!get_mocs_settings(gt, &table))
> 		return;
> 
> 	/* Set unused values to PTE */
>@@ -518,23 +529,27 @@
> 		u16 low = get_entry_l3cc(&table, 2 * i);
> 		u16 high = get_entry_l3cc(&table, 2 * i + 1);
> 
>-		I915_WRITE(GEN9_LNCFCMOCS(i),
>-			   l3cc_combine(&table, low, high));
>+		intel_uncore_write(uncore,
>+				   GEN9_LNCFCMOCS(i),
>+				   l3cc_combine(&table, low, high));
> 	}
> 
> 	/* Odd table size - 1 left over */
> 	if (table.size & 0x01) {
> 		u16 low = get_entry_l3cc(&table, 2 * i);
> 
>-		I915_WRITE(GEN9_LNCFCMOCS(i),
>-			   l3cc_combine(&table, low, unused_value));
>+		intel_uncore_write(uncore,
>+				   GEN9_LNCFCMOCS(i),
>+				   l3cc_combine(&table, low, unused_value));
> 		i++;
> 	}
> 
> 	/* All remaining entries are also unused */
> 	for (; i < table.n_entries / 2; i++)
>-		I915_WRITE(GEN9_LNCFCMOCS(i),
>-			   l3cc_combine(&table, unused_value, unused_value));
>+		intel_uncore_write(uncore,
>+				   GEN9_LNCFCMOCS(i),
>+				   l3cc_combine(&table, unused_value,
>+						unused_value));
> }
> 
> /**
>@@ -553,12 +568,15 @@
>  *
>  * Return: 0 on success, otherwise the error status.
>  */
>-int intel_rcs_context_init_mocs(struct i915_request *rq)
>+int intel_mocs_emit(struct i915_request *rq)
> {
> 	struct drm_i915_mocs_table t;
> 	int ret;
> 
>-	if (get_mocs_settings(rq->i915, &t)) {
>+	if (rq->engine->class != RENDER_CLASS)
>+		return 0;
>+
>+	if (get_mocs_settings(rq->engine->gt, &t)) {
> 		/* Program the RCS control registers */
> 		ret = emit_mocs_control_table(rq, &t);
> 		if (ret)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_mocs.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_mocs.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_mocs.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_mocs.h	2019-08-31 15:01:12.026736183 -0500
>@@ -52,9 +52,11 @@
> struct drm_i915_private;
> struct i915_request;
> struct intel_engine_cs;
>+struct intel_gt;
> 
>-int intel_rcs_context_init_mocs(struct i915_request *rq);
>-void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv);
>+void intel_mocs_init_l3cc_table(struct intel_gt *gt);
> void intel_mocs_init_engine(struct intel_engine_cs *engine);
> 
>+int intel_mocs_emit(struct i915_request *rq);
>+
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_renderstate.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_renderstate.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_renderstate.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_renderstate.c	2019-08-31 15:01:12.242736202 -0500
>@@ -0,0 +1,234 @@
>+/*
>+ * Copyright Â© 2014 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ * Authors:
>+ *    Mika Kuoppala <mika.kuoppala@intel.com>
>+ *
>+ */
>+
>+#include "i915_drv.h"
>+#include "intel_renderstate.h"
>+
>+struct intel_renderstate {
>+	const struct intel_renderstate_rodata *rodata;
>+	struct drm_i915_gem_object *obj;
>+	struct i915_vma *vma;
>+	u32 batch_offset;
>+	u32 batch_size;
>+	u32 aux_offset;
>+	u32 aux_size;
>+};
>+
>+static const struct intel_renderstate_rodata *
>+render_state_get_rodata(const struct intel_engine_cs *engine)
>+{
>+	if (engine->class != RENDER_CLASS)
>+		return NULL;
>+
>+	switch (INTEL_GEN(engine->i915)) {
>+	case 6:
>+		return &gen6_null_state;
>+	case 7:
>+		return &gen7_null_state;
>+	case 8:
>+		return &gen8_null_state;
>+	case 9:
>+		return &gen9_null_state;
>+	}
>+
>+	return NULL;
>+}
>+
>+/*
>+ * Macro to add commands to auxiliary batch.
>+ * This macro only checks for page overflow before inserting the commands,
>+ * this is sufficient as the null state generator makes the final batch
>+ * with two passes to build command and state separately. At this point
>+ * the size of both are known and it compacts them by relocating the state
>+ * right after the commands taking care of alignment so we should sufficient
>+ * space below them for adding new commands.
>+ */
>+#define OUT_BATCH(batch, i, val)				\
>+	do {							\
>+		if ((i) >= PAGE_SIZE / sizeof(u32))		\
>+			goto err;				\
>+		(batch)[(i)++] = (val);				\
>+	} while(0)
>+
>+static int render_state_setup(struct intel_renderstate *so,
>+			      struct drm_i915_private *i915)
>+{
>+	const struct intel_renderstate_rodata *rodata = so->rodata;
>+	unsigned int i = 0, reloc_index = 0;
>+	unsigned int needs_clflush;
>+	u32 *d;
>+	int ret;
>+
>+	ret = i915_gem_object_prepare_write(so->obj, &needs_clflush);
>+	if (ret)
>+		return ret;
>+
>+	d = kmap_atomic(i915_gem_object_get_dirty_page(so->obj, 0));
>+
>+	while (i < rodata->batch_items) {
>+		u32 s = rodata->batch[i];
>+
>+		if (i * 4  == rodata->reloc[reloc_index]) {
>+			u64 r = s + so->vma->node.start;
>+			s = lower_32_bits(r);
>+			if (HAS_64BIT_RELOC(i915)) {
>+				if (i + 1 >= rodata->batch_items ||
>+				    rodata->batch[i + 1] != 0)
>+					goto err;
>+
>+				d[i++] = s;
>+				s = upper_32_bits(r);
>+			}
>+
>+			reloc_index++;
>+		}
>+
>+		d[i++] = s;
>+	}
>+
>+	if (rodata->reloc[reloc_index] != -1) {
>+		DRM_ERROR("only %d relocs resolved\n", reloc_index);
>+		goto err;
>+	}
>+
>+	so->batch_offset = i915_ggtt_offset(so->vma);
>+	so->batch_size = rodata->batch_items * sizeof(u32);
>+
>+	while (i % CACHELINE_DWORDS)
>+		OUT_BATCH(d, i, MI_NOOP);
>+
>+	so->aux_offset = i * sizeof(u32);
>+
>+	if (HAS_POOLED_EU(i915)) {
>+		/*
>+		 * We always program 3x6 pool config but depending upon which
>+		 * subslice is disabled HW drops down to appropriate config
>+		 * shown below.
>+		 *
>+		 * In the below table 2x6 config always refers to
>+		 * fused-down version, native 2x6 is not available and can
>+		 * be ignored
>+		 *
>+		 * SNo  subslices config                eu pool configuration
>+		 * -----------------------------------------------------------
>+		 * 1    3 subslices enabled (3x6)  -    0x00777000  (9+9)
>+		 * 2    ss0 disabled (2x6)         -    0x00777000  (3+9)
>+		 * 3    ss1 disabled (2x6)         -    0x00770000  (6+6)
>+		 * 4    ss2 disabled (2x6)         -    0x00007000  (9+3)
>+		 */
>+		u32 eu_pool_config = 0x00777000;
>+
>+		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
>+		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
>+		OUT_BATCH(d, i, eu_pool_config);
>+		OUT_BATCH(d, i, 0);
>+		OUT_BATCH(d, i, 0);
>+		OUT_BATCH(d, i, 0);
>+	}
>+
>+	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
>+	so->aux_size = i * sizeof(u32) - so->aux_offset;
>+	so->aux_offset += so->batch_offset;
>+	/*
>+	 * Since we are sending length, we need to strictly conform to
>+	 * all requirements. For Gen2 this must be a multiple of 8.
>+	 */
>+	so->aux_size = ALIGN(so->aux_size, 8);
>+
>+	if (needs_clflush)
>+		drm_clflush_virt_range(d, i * sizeof(u32));
>+	kunmap_atomic(d);
>+
>+	ret = 0;
>+out:
>+	i915_gem_object_finish_access(so->obj);
>+	return ret;
>+
>+err:
>+	kunmap_atomic(d);
>+	ret = -EINVAL;
>+	goto out;
>+}
>+
>+#undef OUT_BATCH
>+
>+int intel_renderstate_emit(struct i915_request *rq)
>+{
>+	struct intel_engine_cs *engine = rq->engine;
>+	struct intel_renderstate so = {}; /* keep the compiler happy */
>+	int err;
>+
>+	so.rodata = render_state_get_rodata(engine);
>+	if (!so.rodata)
>+		return 0;
>+
>+	if (so.rodata->batch_items * 4 > PAGE_SIZE)
>+		return -EINVAL;
>+
>+	so.obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
>+	if (IS_ERR(so.obj))
>+		return PTR_ERR(so.obj);
>+
>+	so.vma = i915_vma_instance(so.obj, &engine->gt->ggtt->vm, NULL);
>+	if (IS_ERR(so.vma)) {
>+		err = PTR_ERR(so.vma);
>+		goto err_obj;
>+	}
>+
>+	err = i915_vma_pin(so.vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
>+	if (err)
>+		goto err_vma;
>+
>+	err = render_state_setup(&so, rq->i915);
>+	if (err)
>+		goto err_unpin;
>+
>+	err = engine->emit_bb_start(rq,
>+				    so.batch_offset, so.batch_size,
>+				    I915_DISPATCH_SECURE);
>+	if (err)
>+		goto err_unpin;
>+
>+	if (so.aux_size > 8) {
>+		err = engine->emit_bb_start(rq,
>+					    so.aux_offset, so.aux_size,
>+					    I915_DISPATCH_SECURE);
>+		if (err)
>+			goto err_unpin;
>+	}
>+
>+	i915_vma_lock(so.vma);
>+	err = i915_vma_move_to_active(so.vma, rq, 0);
>+	i915_vma_unlock(so.vma);
>+err_unpin:
>+	i915_vma_unpin(so.vma);
>+err_vma:
>+	i915_vma_close(so.vma);
>+err_obj:
>+	i915_gem_object_put(so.obj);
>+	return err;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_renderstate.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_renderstate.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_renderstate.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_renderstate.h	2019-08-31 15:01:12.242736202 -0500
>@@ -0,0 +1,51 @@
>+/*
>+ * Copyright Â© 2014 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>+ * DEALINGS IN THE SOFTWARE.
>+ */
>+
>+#ifndef _INTEL_RENDERSTATE_H_
>+#define _INTEL_RENDERSTATE_H_
>+
>+#include <linux/types.h>
>+
>+struct i915_request;
>+
>+struct intel_renderstate_rodata {
>+	const u32 *reloc;
>+	const u32 *batch;
>+	const u32 batch_items;
>+};
>+
>+#define RO_RENDERSTATE(_g)						\
>+	const struct intel_renderstate_rodata gen ## _g ## _null_state = { \
>+		.reloc = gen ## _g ## _null_state_relocs,		\
>+		.batch = gen ## _g ## _null_state_batch,		\
>+		.batch_items = sizeof(gen ## _g ## _null_state_batch)/4, \
>+	}
>+
>+extern const struct intel_renderstate_rodata gen6_null_state;
>+extern const struct intel_renderstate_rodata gen7_null_state;
>+extern const struct intel_renderstate_rodata gen8_null_state;
>+extern const struct intel_renderstate_rodata gen9_null_state;
>+
>+int intel_renderstate_emit(struct i915_request *rq);
>+
>+#endif /* _INTEL_RENDERSTATE_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_reset.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_reset.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_reset.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_reset.c	2019-08-31 15:01:12.027736183 -0500
>@@ -15,26 +15,17 @@
> #include "i915_gpu_error.h"
> #include "i915_irq.h"
> #include "intel_engine_pm.h"
>+#include "intel_gt.h"
> #include "intel_gt_pm.h"
> #include "intel_reset.h"
> 
>-#include "intel_guc.h"
>+#include "uc/intel_guc.h"
> 
> #define RESET_MAX_RETRIES 3
> 
> /* XXX How to handle concurrent GGTT updates using tiling registers? */
> #define RESET_UNDER_STOP_MACHINE 0
> 
>-static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
>-{
>-	intel_uncore_rmw(uncore, reg, 0, set);
>-}
>-
>-static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
>-{
>-	intel_uncore_rmw(uncore, reg, clr, 0);
>-}
>-
> static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
> {
> 	intel_uncore_rmw_fw(uncore, reg, 0, set);
>@@ -123,7 +114,7 @@
> 	atomic_inc(&ctx->active_count);
> }
> 
>-void i915_reset_request(struct i915_request *rq, bool guilty)
>+void __i915_request_reset(struct i915_request *rq, bool guilty)
> {
> 	GEM_TRACE("%s rq=%llx:%lld, guilty? %s\n",
> 		  rq->engine->name,
>@@ -144,48 +135,6 @@
> 	}
> }
> 
>-static void gen3_stop_engine(struct intel_engine_cs *engine)
>-{
>-	struct intel_uncore *uncore = engine->uncore;
>-	const u32 base = engine->mmio_base;
>-
>-	GEM_TRACE("%s\n", engine->name);
>-
>-	if (intel_engine_stop_cs(engine))
>-		GEM_TRACE("%s: timed out on STOP_RING\n", engine->name);
>-
>-	intel_uncore_write_fw(uncore,
>-			      RING_HEAD(base),
>-			      intel_uncore_read_fw(uncore, RING_TAIL(base)));
>-	intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */
>-
>-	intel_uncore_write_fw(uncore, RING_HEAD(base), 0);
>-	intel_uncore_write_fw(uncore, RING_TAIL(base), 0);
>-	intel_uncore_posting_read_fw(uncore, RING_TAIL(base));
>-
>-	/* The ring must be empty before it is disabled */
>-	intel_uncore_write_fw(uncore, RING_CTL(base), 0);
>-
>-	/* Check acts as a post */
>-	if (intel_uncore_read_fw(uncore, RING_HEAD(base)))
>-		GEM_TRACE("%s: ring head [%x] not parked\n",
>-			  engine->name,
>-			  intel_uncore_read_fw(uncore, RING_HEAD(base)));
>-}
>-
>-static void i915_stop_engines(struct drm_i915_private *i915,
>-			      intel_engine_mask_t engine_mask)
>-{
>-	struct intel_engine_cs *engine;
>-	intel_engine_mask_t tmp;
>-
>-	if (INTEL_GEN(i915) < 3)
>-		return;
>-
>-	for_each_engine_masked(engine, i915, engine_mask, tmp)
>-		gen3_stop_engine(engine);
>-}
>-
> static bool i915_in_reset(struct pci_dev *pdev)
> {
> 	u8 gdrst;
>@@ -194,11 +143,11 @@
> 	return gdrst & GRDOM_RESET_STATUS;
> }
> 
>-static int i915_do_reset(struct drm_i915_private *i915,
>+static int i915_do_reset(struct intel_gt *gt,
> 			 intel_engine_mask_t engine_mask,
> 			 unsigned int retry)
> {
>-	struct pci_dev *pdev = i915->drm.pdev;
>+	struct pci_dev *pdev = gt->i915->drm.pdev;
> 	int err;
> 
> 	/* Assert reset for at least 20 usec, and wait for acknowledgement. */
>@@ -223,22 +172,22 @@
> 	return (gdrst & GRDOM_RESET_ENABLE) == 0;
> }
> 
>-static int g33_do_reset(struct drm_i915_private *i915,
>+static int g33_do_reset(struct intel_gt *gt,
> 			intel_engine_mask_t engine_mask,
> 			unsigned int retry)
> {
>-	struct pci_dev *pdev = i915->drm.pdev;
>+	struct pci_dev *pdev = gt->i915->drm.pdev;
> 
> 	pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
> 	return wait_for_atomic(g4x_reset_complete(pdev), 50);
> }
> 
>-static int g4x_do_reset(struct drm_i915_private *i915,
>+static int g4x_do_reset(struct intel_gt *gt,
> 			intel_engine_mask_t engine_mask,
> 			unsigned int retry)
> {
>-	struct pci_dev *pdev = i915->drm.pdev;
>-	struct intel_uncore *uncore = &i915->uncore;
>+	struct pci_dev *pdev = gt->i915->drm.pdev;
>+	struct intel_uncore *uncore = gt->uncore;
> 	int ret;
> 
> 	/* WaVcpClkGateDisableForMediaReset:ctg,elk */
>@@ -270,11 +219,11 @@
> 	return ret;
> }
> 
>-static int ironlake_do_reset(struct drm_i915_private *i915,
>+static int ironlake_do_reset(struct intel_gt *gt,
> 			     intel_engine_mask_t engine_mask,
> 			     unsigned int retry)
> {
>-	struct intel_uncore *uncore = &i915->uncore;
>+	struct intel_uncore *uncore = gt->uncore;
> 	int ret;
> 
> 	intel_uncore_write_fw(uncore, ILK_GDSR,
>@@ -306,10 +255,9 @@
> }
> 
> /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
>-static int gen6_hw_domain_reset(struct drm_i915_private *i915,
>-				u32 hw_domain_mask)
>+static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
> {
>-	struct intel_uncore *uncore = &i915->uncore;
>+	struct intel_uncore *uncore = gt->uncore;
> 	int err;
> 
> 	/*
>@@ -331,7 +279,7 @@
> 	return err;
> }
> 
>-static int gen6_reset_engines(struct drm_i915_private *i915,
>+static int gen6_reset_engines(struct intel_gt *gt,
> 			      intel_engine_mask_t engine_mask,
> 			      unsigned int retry)
> {
>@@ -351,13 +299,13 @@
> 		intel_engine_mask_t tmp;
> 
> 		hw_mask = 0;
>-		for_each_engine_masked(engine, i915, engine_mask, tmp) {
>+		for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
> 			GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
> 			hw_mask |= hw_engine_mask[engine->id];
> 		}
> 	}
> 
>-	return gen6_hw_domain_reset(i915, hw_mask);
>+	return gen6_hw_domain_reset(gt, hw_mask);
> }
> 
> static u32 gen11_lock_sfc(struct intel_engine_cs *engine)
>@@ -455,7 +403,7 @@
> 	rmw_clear_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
> }
> 
>-static int gen11_reset_engines(struct drm_i915_private *i915,
>+static int gen11_reset_engines(struct intel_gt *gt,
> 			       intel_engine_mask_t engine_mask,
> 			       unsigned int retry)
> {
>@@ -478,17 +426,17 @@
> 		hw_mask = GEN11_GRDOM_FULL;
> 	} else {
> 		hw_mask = 0;
>-		for_each_engine_masked(engine, i915, engine_mask, tmp) {
>+		for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
> 			GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
> 			hw_mask |= hw_engine_mask[engine->id];
> 			hw_mask |= gen11_lock_sfc(engine);
> 		}
> 	}
> 
>-	ret = gen6_hw_domain_reset(i915, hw_mask);
>+	ret = gen6_hw_domain_reset(gt, hw_mask);
> 
> 	if (engine_mask != ALL_ENGINES)
>-		for_each_engine_masked(engine, i915, engine_mask, tmp)
>+		for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
> 			gen11_unlock_sfc(engine);
> 
> 	return ret;
>@@ -538,7 +486,7 @@
> 			      _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
> }
> 
>-static int gen8_reset_engines(struct drm_i915_private *i915,
>+static int gen8_reset_engines(struct intel_gt *gt,
> 			      intel_engine_mask_t engine_mask,
> 			      unsigned int retry)
> {
>@@ -547,7 +495,7 @@
> 	intel_engine_mask_t tmp;
> 	int ret;
> 
>-	for_each_engine_masked(engine, i915, engine_mask, tmp) {
>+	for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
> 		ret = gen8_engine_reset_prepare(engine);
> 		if (ret && !reset_non_ready)
> 			goto skip_reset;
>@@ -563,23 +511,23 @@
> 		 * We rather take context corruption instead of
> 		 * failed reset with a wedged driver/gpu. And
> 		 * active bb execution case should be covered by
>-		 * i915_stop_engines we have before the reset.
>+		 * stop_engines() we have before the reset.
> 		 */
> 	}
> 
>-	if (INTEL_GEN(i915) >= 11)
>-		ret = gen11_reset_engines(i915, engine_mask, retry);
>+	if (INTEL_GEN(gt->i915) >= 11)
>+		ret = gen11_reset_engines(gt, engine_mask, retry);
> 	else
>-		ret = gen6_reset_engines(i915, engine_mask, retry);
>+		ret = gen6_reset_engines(gt, engine_mask, retry);
> 
> skip_reset:
>-	for_each_engine_masked(engine, i915, engine_mask, tmp)
>+	for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
> 		gen8_engine_reset_cancel(engine);
> 
> 	return ret;
> }
> 
>-typedef int (*reset_func)(struct drm_i915_private *,
>+typedef int (*reset_func)(struct intel_gt *,
> 			  intel_engine_mask_t engine_mask,
> 			  unsigned int retry);
> 
>@@ -601,15 +549,14 @@
> 		return NULL;
> }
> 
>-int intel_gpu_reset(struct drm_i915_private *i915,
>-		    intel_engine_mask_t engine_mask)
>+int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
> {
> 	const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
> 	reset_func reset;
> 	int ret = -ETIMEDOUT;
> 	int retry;
> 
>-	reset = intel_get_gpu_reset(i915);
>+	reset = intel_get_gpu_reset(gt->i915);
> 	if (!reset)
> 		return -ENODEV;
> 
>@@ -617,31 +564,14 @@
> 	 * If the power well sleeps during the reset, the reset
> 	 * request may be dropped and never completes (causing -EIO).
> 	 */
>-	intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
>+	intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
> 	for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
>-		/*
>-		 * We stop engines, otherwise we might get failed reset and a
>-		 * dead gpu (on elk). Also as modern gpu as kbl can suffer
>-		 * from system hang if batchbuffer is progressing when
>-		 * the reset is issued, regardless of READY_TO_RESET ack.
>-		 * Thus assume it is best to stop engines on all gens
>-		 * where we have a gpu reset.
>-		 *
>-		 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
>-		 *
>-		 * WaMediaResetMainRingCleanup:ctg,elk (presumably)
>-		 *
>-		 * FIXME: Wa for more modern gens needs to be validated
>-		 */
>-		if (retry)
>-			i915_stop_engines(i915, engine_mask);
>-
> 		GEM_TRACE("engine_mask=%x\n", engine_mask);
> 		preempt_disable();
>-		ret = reset(i915, engine_mask, retry);
>+		ret = reset(gt, engine_mask, retry);
> 		preempt_enable();
> 	}
>-	intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
>+	intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
> 
> 	return ret;
> }
>@@ -659,17 +589,17 @@
> 	return INTEL_INFO(i915)->has_reset_engine && i915_modparams.reset >= 2;
> }
> 
>-int intel_reset_guc(struct drm_i915_private *i915)
>+int intel_reset_guc(struct intel_gt *gt)
> {
> 	u32 guc_domain =
>-		INTEL_GEN(i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
>+		INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
> 	int ret;
> 
>-	GEM_BUG_ON(!HAS_GUC(i915));
>+	GEM_BUG_ON(!HAS_GT_UC(gt->i915));
> 
>-	intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
>-	ret = gen6_hw_domain_reset(i915, guc_domain);
>-	intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
>+	intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
>+	ret = gen6_hw_domain_reset(gt, guc_domain);
>+	intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
> 
> 	return ret;
> }
>@@ -691,56 +621,55 @@
> 	engine->reset.prepare(engine);
> }
> 
>-static void revoke_mmaps(struct drm_i915_private *i915)
>+static void revoke_mmaps(struct intel_gt *gt)
> {
> 	int i;
> 
>-	for (i = 0; i < i915->ggtt.num_fences; i++) {
>+	for (i = 0; i < gt->ggtt->num_fences; i++) {
> 		struct drm_vma_offset_node *node;
> 		struct i915_vma *vma;
> 		u64 vma_offset;
> 
>-		vma = READ_ONCE(i915->ggtt.fence_regs[i].vma);
>+		vma = READ_ONCE(gt->ggtt->fence_regs[i].vma);
> 		if (!vma)
> 			continue;
> 
> 		if (!i915_vma_has_userfault(vma))
> 			continue;
> 
>-		GEM_BUG_ON(vma->fence != &i915->ggtt.fence_regs[i]);
>+		GEM_BUG_ON(vma->fence != &gt->ggtt->fence_regs[i]);
> 		node = &vma->obj->base.vma_node;
> 		vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;
>-		unmap_mapping_range(i915->drm.anon_inode->i_mapping,
>+		unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
> 				    drm_vma_node_offset_addr(node) + vma_offset,
> 				    vma->size,
> 				    1);
> 	}
> }
> 
>-static intel_engine_mask_t reset_prepare(struct drm_i915_private *i915)
>+static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
> {
> 	struct intel_engine_cs *engine;
> 	intel_engine_mask_t awake = 0;
> 	enum intel_engine_id id;
> 
>-	for_each_engine(engine, i915, id) {
>+	for_each_engine(engine, gt->i915, id) {
> 		if (intel_engine_pm_get_if_awake(engine))
> 			awake |= engine->mask;
> 		reset_prepare_engine(engine);
> 	}
> 
>-	intel_uc_reset_prepare(i915);
>+	intel_uc_reset_prepare(&gt->uc);
> 
> 	return awake;
> }
> 
>-static void gt_revoke(struct drm_i915_private *i915)
>+static void gt_revoke(struct intel_gt *gt)
> {
>-	revoke_mmaps(i915);
>+	revoke_mmaps(gt);
> }
> 
>-static int gt_reset(struct drm_i915_private *i915,
>-		    intel_engine_mask_t stalled_mask)
>+static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
> {
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
>@@ -750,14 +679,14 @@
> 	 * Everything depends on having the GTT running, so we need to start
> 	 * there.
> 	 */
>-	err = i915_ggtt_enable_hw(i915);
>+	err = i915_ggtt_enable_hw(gt->i915);
> 	if (err)
> 		return err;
> 
>-	for_each_engine(engine, i915, id)
>-		intel_engine_reset(engine, stalled_mask & engine->mask);
>+	for_each_engine(engine, gt->i915, id)
>+		__intel_engine_reset(engine, stalled_mask & engine->mask);
> 
>-	i915_gem_restore_fences(i915);
>+	i915_gem_restore_fences(gt->i915);
> 
> 	return err;
> }
>@@ -770,13 +699,12 @@
> 	intel_engine_signal_breadcrumbs(engine);
> }
> 
>-static void reset_finish(struct drm_i915_private *i915,
>-			 intel_engine_mask_t awake)
>+static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
> {
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
> 
>-	for_each_engine(engine, i915, id) {
>+	for_each_engine(engine, gt->i915, id) {
> 		reset_finish_engine(engine);
> 		if (awake & engine->mask)
> 			intel_engine_pm_put(engine);
>@@ -800,20 +728,19 @@
> 	intel_engine_queue_breadcrumbs(engine);
> }
> 
>-static void __i915_gem_set_wedged(struct drm_i915_private *i915)
>+static void __intel_gt_set_wedged(struct intel_gt *gt)
> {
>-	struct i915_gpu_error *error = &i915->gpu_error;
> 	struct intel_engine_cs *engine;
> 	intel_engine_mask_t awake;
> 	enum intel_engine_id id;
> 
>-	if (test_bit(I915_WEDGED, &error->flags))
>+	if (test_bit(I915_WEDGED, &gt->reset.flags))
> 		return;
> 
>-	if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(i915)) {
>+	if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
> 		struct drm_printer p = drm_debug_printer(__func__);
> 
>-		for_each_engine(engine, i915, id)
>+		for_each_engine(engine, gt->i915, id)
> 			intel_engine_dump(engine, &p, "%s\n", engine->name);
> 	}
> 
>@@ -824,17 +751,17 @@
> 	 * rolling the global seqno forward (since this would complete requests
> 	 * for which we haven't set the fence error to EIO yet).
> 	 */
>-	awake = reset_prepare(i915);
>+	awake = reset_prepare(gt);
> 
> 	/* Even if the GPU reset fails, it should still stop the engines */
>-	if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
>-		intel_gpu_reset(i915, ALL_ENGINES);
>+	if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
>+		__intel_gt_reset(gt, ALL_ENGINES);
> 
>-	for_each_engine(engine, i915, id) {
>+	for_each_engine(engine, gt->i915, id) {
> 		engine->submit_request = nop_submit_request;
> 		engine->schedule = NULL;
> 	}
>-	i915->caps.scheduler = 0;
>+	gt->i915->caps.scheduler = 0;
> 
> 	/*
> 	 * Make sure no request can slip through without getting completed by
>@@ -842,37 +769,36 @@
> 	 * in nop_submit_request.
> 	 */
> 	synchronize_rcu_expedited();
>-	set_bit(I915_WEDGED, &error->flags);
>+	set_bit(I915_WEDGED, &gt->reset.flags);
> 
> 	/* Mark all executing requests as skipped */
>-	for_each_engine(engine, i915, id)
>+	for_each_engine(engine, gt->i915, id)
> 		engine->cancel_requests(engine);
> 
>-	reset_finish(i915, awake);
>+	reset_finish(gt, awake);
> 
> 	GEM_TRACE("end\n");
> }
> 
>-void i915_gem_set_wedged(struct drm_i915_private *i915)
>+void intel_gt_set_wedged(struct intel_gt *gt)
> {
>-	struct i915_gpu_error *error = &i915->gpu_error;
> 	intel_wakeref_t wakeref;
> 
>-	mutex_lock(&error->wedge_mutex);
>-	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
>-		__i915_gem_set_wedged(i915);
>-	mutex_unlock(&error->wedge_mutex);
>+	mutex_lock(&gt->reset.mutex);
>+	with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref)
>+		__intel_gt_set_wedged(gt);
>+	mutex_unlock(&gt->reset.mutex);
> }
> 
>-static bool __i915_gem_unset_wedged(struct drm_i915_private *i915)
>+static bool __intel_gt_unset_wedged(struct intel_gt *gt)
> {
>-	struct i915_gpu_error *error = &i915->gpu_error;
>-	struct i915_timeline *tl;
>+	struct intel_gt_timelines *timelines = &gt->timelines;
>+	struct intel_timeline *tl;
> 
>-	if (!test_bit(I915_WEDGED, &error->flags))
>+	if (!test_bit(I915_WEDGED, &gt->reset.flags))
> 		return true;
> 
>-	if (!i915->gt.scratch) /* Never full initialised, recovery impossible */
>+	if (!gt->scratch) /* Never full initialised, recovery impossible */
> 		return false;
> 
> 	GEM_TRACE("start\n");
>@@ -887,8 +813,8 @@
> 	 *
> 	 * No more can be submitted until we reset the wedged bit.
> 	 */
>-	mutex_lock(&i915->gt.timelines.mutex);
>-	list_for_each_entry(tl, &i915->gt.timelines.active_list, link) {
>+	mutex_lock(&timelines->mutex);
>+	list_for_each_entry(tl, &timelines->active_list, link) {
> 		struct i915_request *rq;
> 
> 		rq = i915_active_request_get_unlocked(&tl->last_request);
>@@ -905,9 +831,9 @@
> 		dma_fence_default_wait(&rq->fence, false, MAX_SCHEDULE_TIMEOUT);
> 		i915_request_put(rq);
> 	}
>-	mutex_unlock(&i915->gt.timelines.mutex);
>+	mutex_unlock(&timelines->mutex);
> 
>-	intel_gt_sanitize(i915, false);
>+	intel_gt_sanitize(gt, false);
> 
> 	/*
> 	 * Undo nop_submit_request. We prevent all new i915 requests from
>@@ -918,53 +844,51 @@
> 	 * the nop_submit_request on reset, we can do this from normal
> 	 * context and do not require stop_machine().
> 	 */
>-	intel_engines_reset_default_submission(i915);
>+	intel_engines_reset_default_submission(gt);
> 
> 	GEM_TRACE("end\n");
> 
> 	smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
>-	clear_bit(I915_WEDGED, &i915->gpu_error.flags);
>+	clear_bit(I915_WEDGED, &gt->reset.flags);
> 
> 	return true;
> }
> 
>-bool i915_gem_unset_wedged(struct drm_i915_private *i915)
>+bool intel_gt_unset_wedged(struct intel_gt *gt)
> {
>-	struct i915_gpu_error *error = &i915->gpu_error;
> 	bool result;
> 
>-	mutex_lock(&error->wedge_mutex);
>-	result = __i915_gem_unset_wedged(i915);
>-	mutex_unlock(&error->wedge_mutex);
>+	mutex_lock(&gt->reset.mutex);
>+	result = __intel_gt_unset_wedged(gt);
>+	mutex_unlock(&gt->reset.mutex);
> 
> 	return result;
> }
> 
>-static int do_reset(struct drm_i915_private *i915,
>-		    intel_engine_mask_t stalled_mask)
>+static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
> {
> 	int err, i;
> 
>-	gt_revoke(i915);
>+	gt_revoke(gt);
> 
>-	err = intel_gpu_reset(i915, ALL_ENGINES);
>+	err = __intel_gt_reset(gt, ALL_ENGINES);
> 	for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
> 		msleep(10 * (i + 1));
>-		err = intel_gpu_reset(i915, ALL_ENGINES);
>+		err = __intel_gt_reset(gt, ALL_ENGINES);
> 	}
> 	if (err)
> 		return err;
> 
>-	return gt_reset(i915, stalled_mask);
>+	return gt_reset(gt, stalled_mask);
> }
> 
>-static int resume(struct drm_i915_private *i915)
>+static int resume(struct intel_gt *gt)
> {
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
> 	int ret;
> 
>-	for_each_engine(engine, i915, id) {
>+	for_each_engine(engine, gt->i915, id) {
> 		ret = engine->resume(engine);
> 		if (ret)
> 			return ret;
>@@ -974,8 +898,8 @@
> }
> 
> /**
>- * i915_reset - reset chip after a hang
>- * @i915: #drm_i915_private to reset
>+ * intel_gt_reset - reset chip after a hang
>+ * @gt: #intel_gt to reset
>  * @stalled_mask: mask of the stalled engines with the guilty requests
>  * @reason: user error message for why we are resetting
>  *
>@@ -990,50 +914,50 @@
>  *   - re-init interrupt state
>  *   - re-init display
>  */
>-void i915_reset(struct drm_i915_private *i915,
>-		intel_engine_mask_t stalled_mask,
>-		const char *reason)
>+void intel_gt_reset(struct intel_gt *gt,
>+		    intel_engine_mask_t stalled_mask,
>+		    const char *reason)
> {
>-	struct i915_gpu_error *error = &i915->gpu_error;
> 	intel_engine_mask_t awake;
> 	int ret;
> 
>-	GEM_TRACE("flags=%lx\n", error->flags);
>+	GEM_TRACE("flags=%lx\n", gt->reset.flags);
> 
> 	might_sleep();
>-	GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));
>-	mutex_lock(&error->wedge_mutex);
>+	GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
>+	mutex_lock(&gt->reset.mutex);
> 
> 	/* Clear any previous failed attempts at recovery. Time to try again. */
>-	if (!__i915_gem_unset_wedged(i915))
>+	if (!__intel_gt_unset_wedged(gt))
> 		goto unlock;
> 
> 	if (reason)
>-		dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
>-	error->reset_count++;
>+		dev_notice(gt->i915->drm.dev,
>+			   "Resetting chip for %s\n", reason);
>+	atomic_inc(&gt->i915->gpu_error.reset_count);
> 
>-	awake = reset_prepare(i915);
>+	awake = reset_prepare(gt);
> 
>-	if (!intel_has_gpu_reset(i915)) {
>+	if (!intel_has_gpu_reset(gt->i915)) {
> 		if (i915_modparams.reset)
>-			dev_err(i915->drm.dev, "GPU reset not supported\n");
>+			dev_err(gt->i915->drm.dev, "GPU reset not supported\n");
> 		else
> 			DRM_DEBUG_DRIVER("GPU reset disabled\n");
> 		goto error;
> 	}
> 
>-	if (INTEL_INFO(i915)->gpu_reset_clobbers_display)
>-		intel_runtime_pm_disable_interrupts(i915);
>+	if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
>+		intel_runtime_pm_disable_interrupts(gt->i915);
> 
>-	if (do_reset(i915, stalled_mask)) {
>-		dev_err(i915->drm.dev, "Failed to reset chip\n");
>+	if (do_reset(gt, stalled_mask)) {
>+		dev_err(gt->i915->drm.dev, "Failed to reset chip\n");
> 		goto taint;
> 	}
> 
>-	if (INTEL_INFO(i915)->gpu_reset_clobbers_display)
>-		intel_runtime_pm_enable_interrupts(i915);
>+	if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
>+		intel_runtime_pm_enable_interrupts(gt->i915);
> 
>-	intel_overlay_reset(i915);
>+	intel_overlay_reset(gt->i915);
> 
> 	/*
> 	 * Next we need to restore the context, but we don't use those
>@@ -1043,23 +967,23 @@
> 	 * was running at the time of the reset (i.e. we weren't VT
> 	 * switched away).
> 	 */
>-	ret = i915_gem_init_hw(i915);
>+	ret = i915_gem_init_hw(gt->i915);
> 	if (ret) {
> 		DRM_ERROR("Failed to initialise HW following reset (%d)\n",
> 			  ret);
> 		goto taint;
> 	}
> 
>-	ret = resume(i915);
>+	ret = resume(gt);
> 	if (ret)
> 		goto taint;
> 
>-	i915_queue_hangcheck(i915);
>+	intel_gt_queue_hangcheck(gt);
> 
> finish:
>-	reset_finish(i915, awake);
>+	reset_finish(gt, awake);
> unlock:
>-	mutex_unlock(&error->wedge_mutex);
>+	mutex_unlock(&gt->reset.mutex);
> 	return;
> 
> taint:
>@@ -1077,18 +1001,17 @@
> 	 */
> 	add_taint_for_CI(TAINT_WARN);
> error:
>-	__i915_gem_set_wedged(i915);
>+	__intel_gt_set_wedged(gt);
> 	goto finish;
> }
> 
>-static inline int intel_gt_reset_engine(struct drm_i915_private *i915,
>-					struct intel_engine_cs *engine)
>+static inline int intel_gt_reset_engine(struct intel_engine_cs *engine)
> {
>-	return intel_gpu_reset(i915, engine->mask);
>+	return __intel_gt_reset(engine->gt, engine->mask);
> }
> 
> /**
>- * i915_reset_engine - reset GPU engine to recover from a hang
>+ * intel_engine_reset - reset GPU engine to recover from a hang
>  * @engine: engine to reset
>  * @msg: reason for GPU reset; or NULL for no dev_notice()
>  *
>@@ -1100,13 +1023,13 @@
>  *  - reset engine (which will force the engine to idle)
>  *  - re-init/configure engine
>  */
>-int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
>+int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
> {
>-	struct i915_gpu_error *error = &engine->i915->gpu_error;
>+	struct intel_gt *gt = engine->gt;
> 	int ret;
> 
>-	GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
>-	GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
>+	GEM_TRACE("%s flags=%lx\n", engine->name, gt->reset.flags);
>+	GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &gt->reset.flags));
> 
> 	if (!intel_engine_pm_get_if_awake(engine))
> 		return 0;
>@@ -1116,16 +1039,16 @@
> 	if (msg)
> 		dev_notice(engine->i915->drm.dev,
> 			   "Resetting %s for %s\n", engine->name, msg);
>-	error->reset_engine_count[engine->id]++;
>+	atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
> 
>-	if (!engine->i915->guc.execbuf_client)
>-		ret = intel_gt_reset_engine(engine->i915, engine);
>+	if (!engine->gt->uc.guc.execbuf_client)
>+		ret = intel_gt_reset_engine(engine);
> 	else
>-		ret = intel_guc_reset_engine(&engine->i915->guc, engine);
>+		ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
> 	if (ret) {
> 		/* If we fail here, we expect to fallback to a global reset */
> 		DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
>-				 engine->i915->guc.execbuf_client ? "GuC " : "",
>+				 engine->gt->uc.guc.execbuf_client ? "GuC " : "",
> 				 engine->name, ret);
> 		goto out;
> 	}
>@@ -1135,7 +1058,7 @@
> 	 * active request and can drop it, adjust head to skip the offending
> 	 * request to resume executing remaining requests in the queue.
> 	 */
>-	intel_engine_reset(engine, true);
>+	__intel_engine_reset(engine, true);
> 
> 	/*
> 	 * The engine and its registers (and workarounds in case of render)
>@@ -1151,16 +1074,15 @@
> 	return ret;
> }
> 
>-static void i915_reset_device(struct drm_i915_private *i915,
>-			      u32 engine_mask,
>-			      const char *reason)
>+static void intel_gt_reset_global(struct intel_gt *gt,
>+				  u32 engine_mask,
>+				  const char *reason)
> {
>-	struct i915_gpu_error *error = &i915->gpu_error;
>-	struct kobject *kobj = &i915->drm.primary->kdev->kobj;
>+	struct kobject *kobj = &gt->i915->drm.primary->kdev->kobj;
> 	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
> 	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
> 	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
>-	struct i915_wedge_me w;
>+	struct intel_wedge_me w;
> 
> 	kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
> 
>@@ -1168,137 +1090,24 @@
> 	kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
> 
> 	/* Use a watchdog to ensure that our reset completes */
>-	i915_wedge_on_timeout(&w, i915, 5 * HZ) {
>-		intel_prepare_reset(i915);
>+	intel_wedge_on_timeout(&w, gt, 5 * HZ) {
>+		intel_prepare_reset(gt->i915);
> 
> 		/* Flush everyone using a resource about to be clobbered */
>-		synchronize_srcu_expedited(&error->reset_backoff_srcu);
>+		synchronize_srcu_expedited(&gt->reset.backoff_srcu);
> 
>-		i915_reset(i915, engine_mask, reason);
>+		intel_gt_reset(gt, engine_mask, reason);
> 
>-		intel_finish_reset(i915);
>+		intel_finish_reset(gt->i915);
> 	}
> 
>-	if (!test_bit(I915_WEDGED, &error->flags))
>+	if (!test_bit(I915_WEDGED, &gt->reset.flags))
> 		kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
> }
> 
>-static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
>-{
>-	intel_uncore_rmw(uncore, reg, 0, 0);
>-}
>-
>-static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
>-{
>-	GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
>-	GEN6_RING_FAULT_REG_POSTING_READ(engine);
>-}
>-
>-static void clear_error_registers(struct drm_i915_private *i915,
>-				  intel_engine_mask_t engine_mask)
>-{
>-	struct intel_uncore *uncore = &i915->uncore;
>-	u32 eir;
>-
>-	if (!IS_GEN(i915, 2))
>-		clear_register(uncore, PGTBL_ER);
>-
>-	if (INTEL_GEN(i915) < 4)
>-		clear_register(uncore, IPEIR(RENDER_RING_BASE));
>-	else
>-		clear_register(uncore, IPEIR_I965);
>-
>-	clear_register(uncore, EIR);
>-	eir = intel_uncore_read(uncore, EIR);
>-	if (eir) {
>-		/*
>-		 * some errors might have become stuck,
>-		 * mask them.
>-		 */
>-		DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
>-		rmw_set(uncore, EMR, eir);
>-		intel_uncore_write(uncore, GEN2_IIR,
>-				   I915_MASTER_ERROR_INTERRUPT);
>-	}
>-
>-	if (INTEL_GEN(i915) >= 8) {
>-		rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
>-		intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
>-	} else if (INTEL_GEN(i915) >= 6) {
>-		struct intel_engine_cs *engine;
>-		enum intel_engine_id id;
>-
>-		for_each_engine_masked(engine, i915, engine_mask, id)
>-			gen8_clear_engine_error_register(engine);
>-	}
>-}
>-
>-static void gen6_check_faults(struct drm_i915_private *dev_priv)
>-{
>-	struct intel_engine_cs *engine;
>-	enum intel_engine_id id;
>-	u32 fault;
>-
>-	for_each_engine(engine, dev_priv, id) {
>-		fault = GEN6_RING_FAULT_REG_READ(engine);
>-		if (fault & RING_FAULT_VALID) {
>-			DRM_DEBUG_DRIVER("Unexpected fault\n"
>-					 "\tAddr: 0x%08lx\n"
>-					 "\tAddress space: %s\n"
>-					 "\tSource ID: %d\n"
>-					 "\tType: %d\n",
>-					 fault & PAGE_MASK,
>-					 fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
>-					 RING_FAULT_SRCID(fault),
>-					 RING_FAULT_FAULT_TYPE(fault));
>-		}
>-	}
>-}
>-
>-static void gen8_check_faults(struct drm_i915_private *dev_priv)
>-{
>-	u32 fault = I915_READ(GEN8_RING_FAULT_REG);
>-
>-	if (fault & RING_FAULT_VALID) {
>-		u32 fault_data0, fault_data1;
>-		u64 fault_addr;
>-
>-		fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
>-		fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
>-		fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
>-			     ((u64)fault_data0 << 12);
>-
>-		DRM_DEBUG_DRIVER("Unexpected fault\n"
>-				 "\tAddr: 0x%08x_%08x\n"
>-				 "\tAddress space: %s\n"
>-				 "\tEngine ID: %d\n"
>-				 "\tSource ID: %d\n"
>-				 "\tType: %d\n",
>-				 upper_32_bits(fault_addr),
>-				 lower_32_bits(fault_addr),
>-				 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
>-				 GEN8_RING_FAULT_ENGINE_ID(fault),
>-				 RING_FAULT_SRCID(fault),
>-				 RING_FAULT_FAULT_TYPE(fault));
>-	}
>-}
>-
>-void i915_check_and_clear_faults(struct drm_i915_private *i915)
>-{
>-	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
>-	if (INTEL_GEN(i915) >= 8)
>-		gen8_check_faults(i915);
>-	else if (INTEL_GEN(i915) >= 6)
>-		gen6_check_faults(i915);
>-	else
>-		return;
>-
>-	clear_error_registers(i915, ALL_ENGINES);
>-}
>-
> /**
>- * i915_handle_error - handle a gpu error
>- * @i915: i915 device private
>+ * intel_gt_handle_error - handle a gpu error
>+ * @gt: the intel_gt
>  * @engine_mask: mask representing engines that are hung
>  * @flags: control flags
>  * @fmt: Error message format string
>@@ -1309,12 +1118,11 @@
>  * so userspace knows something bad happened (should trigger collection
>  * of a ring dump etc.).
>  */
>-void i915_handle_error(struct drm_i915_private *i915,
>-		       intel_engine_mask_t engine_mask,
>-		       unsigned long flags,
>-		       const char *fmt, ...)
>+void intel_gt_handle_error(struct intel_gt *gt,
>+			   intel_engine_mask_t engine_mask,
>+			   unsigned long flags,
>+			   const char *fmt, ...)
> {
>-	struct i915_gpu_error *error = &i915->gpu_error;
> 	struct intel_engine_cs *engine;
> 	intel_wakeref_t wakeref;
> 	intel_engine_mask_t tmp;
>@@ -1338,33 +1146,31 @@
> 	 * isn't the case at least when we get here by doing a
> 	 * simulated reset via debugfs, so get an RPM reference.
> 	 */
>-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>+	wakeref = intel_runtime_pm_get(&gt->i915->runtime_pm);
> 
>-	engine_mask &= INTEL_INFO(i915)->engine_mask;
>+	engine_mask &= INTEL_INFO(gt->i915)->engine_mask;
> 
> 	if (flags & I915_ERROR_CAPTURE) {
>-		i915_capture_error_state(i915, engine_mask, msg);
>-		clear_error_registers(i915, engine_mask);
>+		i915_capture_error_state(gt->i915, engine_mask, msg);
>+		intel_gt_clear_error_registers(gt, engine_mask);
> 	}
> 
> 	/*
> 	 * Try engine reset when available. We fall back to full reset if
> 	 * single reset fails.
> 	 */
>-	if (intel_has_reset_engine(i915) && !__i915_wedged(error)) {
>-		for_each_engine_masked(engine, i915, engine_mask, tmp) {
>+	if (intel_has_reset_engine(gt->i915) && !intel_gt_is_wedged(gt)) {
>+		for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
> 			BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
> 			if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
>-					     &error->flags))
>+					     &gt->reset.flags))
> 				continue;
> 
>-			if (i915_reset_engine(engine, msg) == 0)
>+			if (intel_engine_reset(engine, msg) == 0)
> 				engine_mask &= ~engine->mask;
> 
>-			clear_bit(I915_RESET_ENGINE + engine->id,
>-				  &error->flags);
>-			wake_up_bit(&error->flags,
>-				    I915_RESET_ENGINE + engine->id);
>+			clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
>+					      &gt->reset.flags);
> 		}
> 	}
> 
>@@ -1372,9 +1178,9 @@
> 		goto out;
> 
> 	/* Full reset needs the mutex, stop any other user trying to do so. */
>-	if (test_and_set_bit(I915_RESET_BACKOFF, &error->flags)) {
>-		wait_event(error->reset_queue,
>-			   !test_bit(I915_RESET_BACKOFF, &error->flags));
>+	if (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
>+		wait_event(gt->reset.queue,
>+			   !test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
> 		goto out; /* piggy-back on the other reset */
> 	}
> 
>@@ -1382,113 +1188,119 @@
> 	synchronize_rcu_expedited();
> 
> 	/* Prevent any other reset-engine attempt. */
>-	for_each_engine(engine, i915, tmp) {
>+	for_each_engine(engine, gt->i915, tmp) {
> 		while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
>-					&error->flags))
>-			wait_on_bit(&error->flags,
>+					&gt->reset.flags))
>+			wait_on_bit(&gt->reset.flags,
> 				    I915_RESET_ENGINE + engine->id,
> 				    TASK_UNINTERRUPTIBLE);
> 	}
> 
>-	i915_reset_device(i915, engine_mask, msg);
>+	intel_gt_reset_global(gt, engine_mask, msg);
> 
>-	for_each_engine(engine, i915, tmp) {
>-		clear_bit(I915_RESET_ENGINE + engine->id,
>-			  &error->flags);
>-	}
>-
>-	clear_bit(I915_RESET_BACKOFF, &error->flags);
>-	wake_up_all(&error->reset_queue);
>+	for_each_engine(engine, gt->i915, tmp)
>+		clear_bit_unlock(I915_RESET_ENGINE + engine->id,
>+				 &gt->reset.flags);
>+	clear_bit_unlock(I915_RESET_BACKOFF, &gt->reset.flags);
>+	smp_mb__after_atomic();
>+	wake_up_all(&gt->reset.queue);
> 
> out:
>-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>+	intel_runtime_pm_put(&gt->i915->runtime_pm, wakeref);
> }
> 
>-int i915_reset_trylock(struct drm_i915_private *i915)
>+int intel_gt_reset_trylock(struct intel_gt *gt)
> {
>-	struct i915_gpu_error *error = &i915->gpu_error;
> 	int srcu;
> 
>-	might_lock(&error->reset_backoff_srcu);
>+	might_lock(&gt->reset.backoff_srcu);
> 	might_sleep();
> 
> 	rcu_read_lock();
>-	while (test_bit(I915_RESET_BACKOFF, &error->flags)) {
>+	while (test_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
> 		rcu_read_unlock();
> 
>-		if (wait_event_interruptible(error->reset_queue,
>+		if (wait_event_interruptible(gt->reset.queue,
> 					     !test_bit(I915_RESET_BACKOFF,
>-						       &error->flags)))
>+						       &gt->reset.flags)))
> 			return -EINTR;
> 
> 		rcu_read_lock();
> 	}
>-	srcu = srcu_read_lock(&error->reset_backoff_srcu);
>+	srcu = srcu_read_lock(&gt->reset.backoff_srcu);
> 	rcu_read_unlock();
> 
> 	return srcu;
> }
> 
>-void i915_reset_unlock(struct drm_i915_private *i915, int tag)
>-__releases(&i915->gpu_error.reset_backoff_srcu)
>+void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
>+__releases(&gt->reset.backoff_srcu)
> {
>-	struct i915_gpu_error *error = &i915->gpu_error;
>-
>-	srcu_read_unlock(&error->reset_backoff_srcu, tag);
>+	srcu_read_unlock(&gt->reset.backoff_srcu, tag);
> }
> 
>-int i915_terminally_wedged(struct drm_i915_private *i915)
>+int intel_gt_terminally_wedged(struct intel_gt *gt)
> {
>-	struct i915_gpu_error *error = &i915->gpu_error;
>-
> 	might_sleep();
> 
>-	if (!__i915_wedged(error))
>+	if (!intel_gt_is_wedged(gt))
> 		return 0;
> 
> 	/* Reset still in progress? Maybe we will recover? */
>-	if (!test_bit(I915_RESET_BACKOFF, &error->flags))
>+	if (!test_bit(I915_RESET_BACKOFF, &gt->reset.flags))
> 		return -EIO;
> 
> 	/* XXX intel_reset_finish() still takes struct_mutex!!! */
>-	if (mutex_is_locked(&i915->drm.struct_mutex))
>+	if (mutex_is_locked(&gt->i915->drm.struct_mutex))
> 		return -EAGAIN;
> 
>-	if (wait_event_interruptible(error->reset_queue,
>+	if (wait_event_interruptible(gt->reset.queue,
> 				     !test_bit(I915_RESET_BACKOFF,
>-					       &error->flags)))
>+					       &gt->reset.flags)))
> 		return -EINTR;
> 
>-	return __i915_wedged(error) ? -EIO : 0;
>+	return intel_gt_is_wedged(gt) ? -EIO : 0;
>+}
>+
>+void intel_gt_init_reset(struct intel_gt *gt)
>+{
>+	init_waitqueue_head(&gt->reset.queue);
>+	mutex_init(&gt->reset.mutex);
>+	init_srcu_struct(&gt->reset.backoff_srcu);
>+}
>+
>+void intel_gt_fini_reset(struct intel_gt *gt)
>+{
>+	cleanup_srcu_struct(&gt->reset.backoff_srcu);
> }
> 
>-static void i915_wedge_me(struct work_struct *work)
>+static void intel_wedge_me(struct work_struct *work)
> {
>-	struct i915_wedge_me *w = container_of(work, typeof(*w), work.work);
>+	struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
> 
>-	dev_err(w->i915->drm.dev,
>+	dev_err(w->gt->i915->drm.dev,
> 		"%s timed out, cancelling all in-flight rendering.\n",
> 		w->name);
>-	i915_gem_set_wedged(w->i915);
>+	intel_gt_set_wedged(w->gt);
> }
> 
>-void __i915_init_wedge(struct i915_wedge_me *w,
>-		       struct drm_i915_private *i915,
>-		       long timeout,
>-		       const char *name)
>+void __intel_init_wedge(struct intel_wedge_me *w,
>+			struct intel_gt *gt,
>+			long timeout,
>+			const char *name)
> {
>-	w->i915 = i915;
>+	w->gt = gt;
> 	w->name = name;
> 
>-	INIT_DELAYED_WORK_ONSTACK(&w->work, i915_wedge_me);
>+	INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me);
> 	schedule_delayed_work(&w->work, timeout);
> }
> 
>-void __i915_fini_wedge(struct i915_wedge_me *w)
>+void __intel_fini_wedge(struct intel_wedge_me *w)
> {
> 	cancel_delayed_work_sync(&w->work);
> 	destroy_delayed_work_on_stack(&w->work);
>-	w->i915 = NULL;
>+	w->gt = NULL;
> }
> 
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_reset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_reset.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_reset.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_reset.h	2019-08-31 15:01:12.027736183 -0500
>@@ -11,58 +11,67 @@
> #include <linux/types.h>
> #include <linux/srcu.h>
> 
>-#include "gt/intel_engine_types.h"
>+#include "intel_engine_types.h"
>+#include "intel_reset_types.h"
> 
> struct drm_i915_private;
> struct i915_request;
> struct intel_engine_cs;
>+struct intel_gt;
> struct intel_guc;
> 
>+void intel_gt_init_reset(struct intel_gt *gt);
>+void intel_gt_fini_reset(struct intel_gt *gt);
>+
> __printf(4, 5)
>-void i915_handle_error(struct drm_i915_private *i915,
>-		       intel_engine_mask_t engine_mask,
>-		       unsigned long flags,
>-		       const char *fmt, ...);
>+void intel_gt_handle_error(struct intel_gt *gt,
>+			   intel_engine_mask_t engine_mask,
>+			   unsigned long flags,
>+			   const char *fmt, ...);
> #define I915_ERROR_CAPTURE BIT(0)
> 
>-void i915_check_and_clear_faults(struct drm_i915_private *i915);
>-
>-void i915_reset(struct drm_i915_private *i915,
>-		intel_engine_mask_t stalled_mask,
>-		const char *reason);
>-int i915_reset_engine(struct intel_engine_cs *engine,
>-		      const char *reason);
>+void intel_gt_reset(struct intel_gt *gt,
>+		    intel_engine_mask_t stalled_mask,
>+		    const char *reason);
>+int intel_engine_reset(struct intel_engine_cs *engine,
>+		       const char *reason);
> 
>-void i915_reset_request(struct i915_request *rq, bool guilty);
>+void __i915_request_reset(struct i915_request *rq, bool guilty);
> 
>-int __must_check i915_reset_trylock(struct drm_i915_private *i915);
>-void i915_reset_unlock(struct drm_i915_private *i915, int tag);
>+int __must_check intel_gt_reset_trylock(struct intel_gt *gt);
>+void intel_gt_reset_unlock(struct intel_gt *gt, int tag);
> 
>-int i915_terminally_wedged(struct drm_i915_private *i915);
>-
>-bool intel_has_gpu_reset(struct drm_i915_private *i915);
>-bool intel_has_reset_engine(struct drm_i915_private *i915);
>+void intel_gt_set_wedged(struct intel_gt *gt);
>+bool intel_gt_unset_wedged(struct intel_gt *gt);
>+int intel_gt_terminally_wedged(struct intel_gt *gt);
> 
>-int intel_gpu_reset(struct drm_i915_private *i915,
>-		    intel_engine_mask_t engine_mask);
>+int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask);
> 
>-int intel_reset_guc(struct drm_i915_private *i915);
>+int intel_reset_guc(struct intel_gt *gt);
> 
>-struct i915_wedge_me {
>+struct intel_wedge_me {
> 	struct delayed_work work;
>-	struct drm_i915_private *i915;
>+	struct intel_gt *gt;
> 	const char *name;
> };
> 
>-void __i915_init_wedge(struct i915_wedge_me *w,
>-		       struct drm_i915_private *i915,
>-		       long timeout,
>-		       const char *name);
>-void __i915_fini_wedge(struct i915_wedge_me *w);
>-
>-#define i915_wedge_on_timeout(W, DEV, TIMEOUT)				\
>-	for (__i915_init_wedge((W), (DEV), (TIMEOUT), __func__);	\
>-	     (W)->i915;							\
>-	     __i915_fini_wedge((W)))
>+void __intel_init_wedge(struct intel_wedge_me *w,
>+			struct intel_gt *gt,
>+			long timeout,
>+			const char *name);
>+void __intel_fini_wedge(struct intel_wedge_me *w);
>+
>+#define intel_wedge_on_timeout(W, GT, TIMEOUT)				\
>+	for (__intel_init_wedge((W), (GT), (TIMEOUT), __func__);	\
>+	     (W)->gt;							\
>+	     __intel_fini_wedge((W)))
>+
>+static inline bool __intel_reset_failed(const struct intel_reset *reset)
>+{
>+	return unlikely(test_bit(I915_WEDGED, &reset->flags));
>+}
>+
>+bool intel_has_gpu_reset(struct drm_i915_private *i915);
>+bool intel_has_reset_engine(struct drm_i915_private *i915);
> 
> #endif /* I915_RESET_H */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_reset_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_reset_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_reset_types.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_reset_types.h	2019-08-31 15:01:12.027736183 -0500
>@@ -0,0 +1,50 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright Â© 2019 Intel Corporation
>+ */
>+
>+#ifndef __INTEL_RESET_TYPES_H_
>+#define __INTEL_RESET_TYPES_H_
>+
>+#include <linux/mutex.h>
>+#include <linux/wait.h>
>+#include <linux/srcu.h>
>+
>+struct intel_reset {
>+	/**
>+	 * flags: Control various stages of the GPU reset
>+	 *
>+	 * #I915_RESET_BACKOFF - When we start a global reset, we need to
>+	 * serialise with any other users attempting to do the same, and
>+	 * any global resources that may be clobber by the reset (such as
>+	 * FENCE registers).
>+	 *
>+	 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
>+	 * acquire the struct_mutex to reset an engine, we need an explicit
>+	 * flag to prevent two concurrent reset attempts in the same engine.
>+	 * As the number of engines continues to grow, allocate the flags from
>+	 * the most significant bits.
>+	 *
>+	 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
>+	 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
>+	 * i915_request_alloc(), this bit is checked and the sequence
>+	 * aborted (with -EIO reported to userspace) if set.
>+	 */
>+	unsigned long flags;
>+#define I915_RESET_BACKOFF	0
>+#define I915_RESET_MODESET	1
>+#define I915_RESET_ENGINE	2
>+#define I915_WEDGED		(BITS_PER_LONG - 1)
>+
>+	struct mutex mutex; /* serialises wedging/unwedging */
>+
>+	/**
>+	 * Waitqueue to signal when the reset has completed. Used by clients
>+	 * that wait for dev_priv->mm.wedged to settle.
>+	 */
>+	wait_queue_head_t queue;
>+
>+	struct srcu_struct backoff_srcu;
>+};
>+
>+#endif /* _INTEL_RESET_TYPES_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_ringbuffer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_ringbuffer.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_ringbuffer.c	2019-08-31 15:01:12.027736183 -0500
>@@ -34,9 +34,9 @@
> #include "gem/i915_gem_context.h"
> 
> #include "i915_drv.h"
>-#include "i915_gem_render_state.h"
> #include "i915_trace.h"
> #include "intel_context.h"
>+#include "intel_gt.h"
> #include "intel_reset.h"
> #include "intel_workarounds.h"
> 
>@@ -75,7 +75,8 @@
> 	*cs++ = cmd;
> 	while (num_store_dw--) {
> 		*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
>-		*cs++ = i915_scratch_offset(rq->i915);
>+		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
>+						INTEL_GT_SCRATCH_FIELD_DEFAULT);
> 		*cs++ = 0;
> 	}
> 	*cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
>@@ -148,7 +149,9 @@
> 	 */
> 	if (mode & EMIT_INVALIDATE) {
> 		*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
>-		*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
>+		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
>+						INTEL_GT_SCRATCH_FIELD_DEFAULT) |
>+			PIPE_CONTROL_GLOBAL_GTT;
> 		*cs++ = 0;
> 		*cs++ = 0;
> 
>@@ -156,7 +159,9 @@
> 			*cs++ = MI_FLUSH;
> 
> 		*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
>-		*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
>+		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
>+						INTEL_GT_SCRATCH_FIELD_DEFAULT) |
>+			PIPE_CONTROL_GLOBAL_GTT;
> 		*cs++ = 0;
> 		*cs++ = 0;
> 	}
>@@ -208,7 +213,9 @@
> static int
> gen6_emit_post_sync_nonzero_flush(struct i915_request *rq)
> {
>-	u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
>+	u32 scratch_addr =
>+		intel_gt_scratch_offset(rq->engine->gt,
>+					INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
> 	u32 *cs;
> 
> 	cs = intel_ring_begin(rq, 6);
>@@ -241,7 +248,9 @@
> static int
> gen6_render_ring_flush(struct i915_request *rq, u32 mode)
> {
>-	u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
>+	u32 scratch_addr =
>+		intel_gt_scratch_offset(rq->engine->gt,
>+					INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
> 	u32 *cs, flags = 0;
> 	int ret;
> 
>@@ -299,7 +308,9 @@
> 
> 	*cs++ = GFX_OP_PIPE_CONTROL(4);
> 	*cs++ = PIPE_CONTROL_QW_WRITE;
>-	*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
>+	*cs++ = intel_gt_scratch_offset(rq->engine->gt,
>+					INTEL_GT_SCRATCH_FIELD_DEFAULT) |
>+		PIPE_CONTROL_GLOBAL_GTT;
> 	*cs++ = 0;
> 
> 	/* Finally we can flush and with it emit the breadcrumb */
>@@ -342,7 +353,9 @@
> static int
> gen7_render_ring_flush(struct i915_request *rq, u32 mode)
> {
>-	u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
>+	u32 scratch_addr =
>+		intel_gt_scratch_offset(rq->engine->gt,
>+					INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
> 	u32 *cs, flags = 0;
> 
> 	/*
>@@ -725,7 +738,45 @@
> 
> static void reset_prepare(struct intel_engine_cs *engine)
> {
>-	intel_engine_stop_cs(engine);
>+	struct intel_uncore *uncore = engine->uncore;
>+	const u32 base = engine->mmio_base;
>+
>+	/*
>+	 * We stop engines, otherwise we might get failed reset and a
>+	 * dead gpu (on elk). Also as modern gpu as kbl can suffer
>+	 * from system hang if batchbuffer is progressing when
>+	 * the reset is issued, regardless of READY_TO_RESET ack.
>+	 * Thus assume it is best to stop engines on all gens
>+	 * where we have a gpu reset.
>+	 *
>+	 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
>+	 *
>+	 * WaMediaResetMainRingCleanup:ctg,elk (presumably)
>+	 *
>+	 * FIXME: Wa for more modern gens needs to be validated
>+	 */
>+	GEM_TRACE("%s\n", engine->name);
>+
>+	if (intel_engine_stop_cs(engine))
>+		GEM_TRACE("%s: timed out on STOP_RING\n", engine->name);
>+
>+	intel_uncore_write_fw(uncore,
>+			      RING_HEAD(base),
>+			      intel_uncore_read_fw(uncore, RING_TAIL(base)));
>+	intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */
>+
>+	intel_uncore_write_fw(uncore, RING_HEAD(base), 0);
>+	intel_uncore_write_fw(uncore, RING_TAIL(base), 0);
>+	intel_uncore_posting_read_fw(uncore, RING_TAIL(base));
>+
>+	/* The ring must be empty before it is disabled */
>+	intel_uncore_write_fw(uncore, RING_CTL(base), 0);
>+
>+	/* Check acts as a post */
>+	if (intel_uncore_read_fw(uncore, RING_HEAD(base)))
>+		GEM_TRACE("%s: ring head [%x] not parked\n",
>+			  engine->name,
>+			  intel_uncore_read_fw(uncore, RING_HEAD(base)));
> }
> 
> static void reset_ring(struct intel_engine_cs *engine, bool stalled)
>@@ -781,7 +832,7 @@
> 		 * If the request was innocent, we try to replay the request
> 		 * with the restored context.
> 		 */
>-		i915_reset_request(rq, stalled);
>+		__i915_request_reset(rq, stalled);
> 
> 		GEM_BUG_ON(rq->ring != engine->buffer);
> 		head = rq->head;
>@@ -797,21 +848,6 @@
> {
> }
> 
>-static int intel_rcs_ctx_init(struct i915_request *rq)
>-{
>-	int ret;
>-
>-	ret = intel_engine_emit_ctx_wa(rq);
>-	if (ret != 0)
>-		return ret;
>-
>-	ret = i915_gem_render_state_emit(rq);
>-	if (ret)
>-		return ret;
>-
>-	return 0;
>-}
>-
> static int rcs_resume(struct intel_engine_cs *engine)
> {
> 	struct drm_i915_private *dev_priv = engine->i915;
>@@ -1033,14 +1069,14 @@
> 	/* Flush/delay to ensure the RING_IMR is active before the GT IMR */
> 	ENGINE_POSTING_READ(engine, RING_IMR);
> 
>-	gen6_unmask_pm_irq(engine->i915, engine->irq_enable_mask);
>+	gen6_unmask_pm_irq(engine->gt, engine->irq_enable_mask);
> }
> 
> static void
> hsw_vebox_irq_disable(struct intel_engine_cs *engine)
> {
> 	ENGINE_WRITE(engine, RING_IMR, ~0);
>-	gen6_mask_pm_irq(engine->i915, engine->irq_enable_mask);
>+	gen6_mask_pm_irq(engine->gt, engine->irq_enable_mask);
> }
> 
> static int
>@@ -1071,9 +1107,11 @@
> 		   u64 offset, u32 len,
> 		   unsigned int dispatch_flags)
> {
>-	u32 *cs, cs_offset = i915_scratch_offset(rq->i915);
>+	u32 *cs, cs_offset =
>+		intel_gt_scratch_offset(rq->engine->gt,
>+					INTEL_GT_SCRATCH_FIELD_DEFAULT);
> 
>-	GEM_BUG_ON(rq->i915->gt.scratch->size < I830_WA_SIZE);
>+	GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE);
> 
> 	cs = intel_ring_begin(rq, 6);
> 	if (IS_ERR(cs))
>@@ -1156,7 +1194,7 @@
> 	if (atomic_fetch_inc(&ring->pin_count))
> 		return 0;
> 
>-	ret = i915_timeline_pin(ring->timeline);
>+	ret = intel_timeline_pin(ring->timeline);
> 	if (ret)
> 		goto err_unpin;
> 
>@@ -1189,12 +1227,13 @@
> 	GEM_BUG_ON(ring->vaddr);
> 	ring->vaddr = addr;
> 
>+	GEM_TRACE("ring:%llx pin\n", ring->timeline->fence_context);
> 	return 0;
> 
> err_ring:
> 	i915_vma_unpin(vma);
> err_timeline:
>-	i915_timeline_unpin(ring->timeline);
>+	intel_timeline_unpin(ring->timeline);
> err_unpin:
> 	atomic_dec(&ring->pin_count);
> 	return ret;
>@@ -1215,10 +1254,13 @@
> 	if (!atomic_dec_and_test(&ring->pin_count))
> 		return;
> 
>+	GEM_TRACE("ring:%llx unpin\n", ring->timeline->fence_context);
>+
> 	/* Discard any unused bytes beyond that submitted to hw. */
> 	intel_ring_reset(ring, ring->tail);
> 
> 	GEM_BUG_ON(!ring->vma);
>+	i915_vma_unset_ggtt_write(ring->vma);
> 	if (i915_vma_is_map_and_fenceable(ring->vma))
> 		i915_vma_unpin_iomap(ring->vma);
> 	else
>@@ -1230,19 +1272,19 @@
> 	ring->vma->obj->pin_global--;
> 	i915_vma_unpin(ring->vma);
> 
>-	i915_timeline_unpin(ring->timeline);
>+	intel_timeline_unpin(ring->timeline);
> }
> 
>-static struct i915_vma *
>-intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
>+static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
> {
>-	struct i915_address_space *vm = &dev_priv->ggtt.vm;
>+	struct i915_address_space *vm = &ggtt->vm;
>+	struct drm_i915_private *i915 = vm->i915;
> 	struct drm_i915_gem_object *obj;
> 	struct i915_vma *vma;
> 
>-	obj = i915_gem_object_create_stolen(dev_priv, size);
>+	obj = i915_gem_object_create_stolen(i915, size);
> 	if (!obj)
>-		obj = i915_gem_object_create_internal(dev_priv, size);
>+		obj = i915_gem_object_create_internal(i915, size);
> 	if (IS_ERR(obj))
> 		return ERR_CAST(obj);
> 
>@@ -1266,9 +1308,10 @@
> 
> struct intel_ring *
> intel_engine_create_ring(struct intel_engine_cs *engine,
>-			 struct i915_timeline *timeline,
>+			 struct intel_timeline *timeline,
> 			 int size)
> {
>+	struct drm_i915_private *i915 = engine->i915;
> 	struct intel_ring *ring;
> 	struct i915_vma *vma;
> 
>@@ -1281,7 +1324,7 @@
> 
> 	kref_init(&ring->ref);
> 	INIT_LIST_HEAD(&ring->request_list);
>-	ring->timeline = i915_timeline_get(timeline);
>+	ring->timeline = intel_timeline_get(timeline);
> 
> 	ring->size = size;
> 	/* Workaround an erratum on the i830 which causes a hang if
>@@ -1289,12 +1332,12 @@
> 	 * of the buffer.
> 	 */
> 	ring->effective_size = size;
>-	if (IS_I830(engine->i915) || IS_I845G(engine->i915))
>+	if (IS_I830(i915) || IS_I845G(i915))
> 		ring->effective_size -= 2 * CACHELINE_BYTES;
> 
> 	intel_ring_update_space(ring);
> 
>-	vma = intel_ring_create_vma(engine->i915, size);
>+	vma = create_ring_vma(engine->gt->ggtt, size);
> 	if (IS_ERR(vma)) {
> 		kfree(ring);
> 		return ERR_CAST(vma);
>@@ -1311,13 +1354,12 @@
> 	i915_vma_close(ring->vma);
> 	i915_vma_put(ring->vma);
> 
>-	i915_timeline_put(ring->timeline);
>+	intel_timeline_put(ring->timeline);
> 	kfree(ring);
> }
> 
> static void __ring_context_fini(struct intel_context *ce)
> {
>-	GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
> 	i915_gem_object_put(ce->state->obj);
> }
> 
>@@ -1330,33 +1372,45 @@
> 	if (ce->state)
> 		__ring_context_fini(ce);
> 
>+	intel_context_fini(ce);
> 	intel_context_free(ce);
> }
> 
>-static int __context_pin_ppgtt(struct i915_gem_context *ctx)
>+static struct i915_address_space *vm_alias(struct intel_context *ce)
>+{
>+	struct i915_address_space *vm;
>+
>+	vm = ce->vm;
>+	if (i915_is_ggtt(vm))
>+		vm = &i915_vm_to_ggtt(vm)->alias->vm;
>+
>+	return vm;
>+}
>+
>+static int __context_pin_ppgtt(struct intel_context *ce)
> {
> 	struct i915_address_space *vm;
> 	int err = 0;
> 
>-	vm = ctx->vm ?: &ctx->i915->mm.aliasing_ppgtt->vm;
>+	vm = vm_alias(ce);
> 	if (vm)
> 		err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)));
> 
> 	return err;
> }
> 
>-static void __context_unpin_ppgtt(struct i915_gem_context *ctx)
>+static void __context_unpin_ppgtt(struct intel_context *ce)
> {
> 	struct i915_address_space *vm;
> 
>-	vm = ctx->vm ?: &ctx->i915->mm.aliasing_ppgtt->vm;
>+	vm = vm_alias(ce);
> 	if (vm)
> 		gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm));
> }
> 
> static void ring_context_unpin(struct intel_context *ce)
> {
>-	__context_unpin_ppgtt(ce->gem_context);
>+	__context_unpin_ppgtt(ce);
> }
> 
> static struct i915_vma *
>@@ -1412,7 +1466,7 @@
> 		i915_gem_object_unpin_map(obj);
> 	}
> 
>-	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
>+	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
> 	if (IS_ERR(vma)) {
> 		err = PTR_ERR(vma);
> 		goto err_obj;
>@@ -1446,11 +1500,11 @@
> 		ce->state = vma;
> 	}
> 
>-	err = intel_context_active_acquire(ce, PIN_HIGH);
>+	err = intel_context_active_acquire(ce);
> 	if (err)
> 		return err;
> 
>-	err = __context_pin_ppgtt(ce->gem_context);
>+	err = __context_pin_ppgtt(ce);
> 	if (err)
> 		goto err_active;
> 
>@@ -1492,7 +1546,7 @@
> 
> 	*cs++ = MI_LOAD_REGISTER_IMM(1);
> 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
>-	*cs++ = ppgtt->pd->base.ggtt_offset << 10;
>+	*cs++ = px_base(ppgtt->pd)->ggtt_offset << 10;
> 
> 	intel_ring_advance(rq, cs);
> 
>@@ -1511,7 +1565,8 @@
> 	/* Stall until the page table load is complete */
> 	*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
> 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
>-	*cs++ = i915_scratch_offset(rq->i915);
>+	*cs++ = intel_gt_scratch_offset(rq->engine->gt,
>+					INTEL_GT_SCRATCH_FIELD_DEFAULT);
> 	*cs++ = MI_NOOP;
> 
> 	intel_ring_advance(rq, cs);
>@@ -1627,7 +1682,8 @@
> 			/* Insert a delay before the next switch! */
> 			*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
> 			*cs++ = i915_mmio_reg_offset(last_reg);
>-			*cs++ = i915_scratch_offset(rq->i915);
>+			*cs++ = intel_gt_scratch_offset(rq->engine->gt,
>+							INTEL_GT_SCRATCH_FIELD_DEFAULT);
> 			*cs++ = MI_NOOP;
> 		}
> 		*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
>@@ -1640,7 +1696,7 @@
> 	return 0;
> }
> 
>-static int remap_l3(struct i915_request *rq, int slice)
>+static int remap_l3_slice(struct i915_request *rq, int slice)
> {
> 	u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
> 	int i;
>@@ -1668,15 +1724,34 @@
> 	return 0;
> }
> 
>+static int remap_l3(struct i915_request *rq)
>+{
>+	struct i915_gem_context *ctx = rq->gem_context;
>+	int i, err;
>+
>+	if (!ctx->remap_slice)
>+		return 0;
>+
>+	for (i = 0; i < MAX_L3_SLICES; i++) {
>+		if (!(ctx->remap_slice & BIT(i)))
>+			continue;
>+
>+		err = remap_l3_slice(rq, i);
>+		if (err)
>+			return err;
>+	}
>+
>+	ctx->remap_slice = 0;
>+	return 0;
>+}
>+
> static int switch_context(struct i915_request *rq)
> {
> 	struct intel_engine_cs *engine = rq->engine;
>-	struct i915_gem_context *ctx = rq->gem_context;
>-	struct i915_address_space *vm =
>-		ctx->vm ?: &rq->i915->mm.aliasing_ppgtt->vm;
>+	struct i915_address_space *vm = vm_alias(rq->hw_context);
> 	unsigned int unwind_mm = 0;
> 	u32 hw_flags = 0;
>-	int ret, i;
>+	int ret;
> 
> 	GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
> 
>@@ -1720,7 +1795,7 @@
> 		 * as nothing actually executes using the kernel context; it
> 		 * is purely used for flushing user contexts.
> 		 */
>-		if (i915_gem_context_is_kernel(ctx))
>+		if (i915_gem_context_is_kernel(rq->gem_context))
> 			hw_flags = MI_RESTORE_INHIBIT;
> 
> 		ret = mi_set_context(rq, hw_flags);
>@@ -1754,18 +1829,9 @@
> 			goto err_mm;
> 	}
> 
>-	if (ctx->remap_slice) {
>-		for (i = 0; i < MAX_L3_SLICES; i++) {
>-			if (!(ctx->remap_slice & BIT(i)))
>-				continue;
>-
>-			ret = remap_l3(rq, i);
>-			if (ret)
>-				goto err_mm;
>-		}
>-
>-		ctx->remap_slice = 0;
>-	}
>+	ret = remap_l3(rq);
>+	if (ret)
>+		goto err_mm;
> 
> 	return 0;
> 
>@@ -2166,11 +2232,9 @@
> 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> 
> 	if (INTEL_GEN(i915) >= 7) {
>-		engine->init_context = intel_rcs_ctx_init;
> 		engine->emit_flush = gen7_render_ring_flush;
> 		engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb;
> 	} else if (IS_GEN(i915, 6)) {
>-		engine->init_context = intel_rcs_ctx_init;
> 		engine->emit_flush = gen6_render_ring_flush;
> 		engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb;
> 	} else if (IS_GEN(i915, 5)) {
>@@ -2267,11 +2331,11 @@
> 
> int intel_ring_submission_init(struct intel_engine_cs *engine)
> {
>-	struct i915_timeline *timeline;
>+	struct intel_timeline *timeline;
> 	struct intel_ring *ring;
> 	int err;
> 
>-	timeline = i915_timeline_create(engine->i915, engine->status_page.vma);
>+	timeline = intel_timeline_create(engine->gt, engine->status_page.vma);
> 	if (IS_ERR(timeline)) {
> 		err = PTR_ERR(timeline);
> 		goto err;
>@@ -2279,7 +2343,7 @@
> 	GEM_BUG_ON(timeline->has_initial_breadcrumb);
> 
> 	ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE);
>-	i915_timeline_put(timeline);
>+	intel_timeline_put(timeline);
> 	if (IS_ERR(ring)) {
> 		err = PTR_ERR(ring);
> 		goto err;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_timeline.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_timeline.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_timeline.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_timeline.c	2019-08-31 15:01:12.242736202 -0500
>@@ -0,0 +1,589 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2016-2018 Intel Corporation
>+ */
>+
>+#include "gt/intel_gt_types.h"
>+
>+#include "i915_drv.h"
>+
>+#include "i915_active.h"
>+#include "i915_syncmap.h"
>+#include "gt/intel_timeline.h"
>+
>+#define ptr_set_bit(ptr, bit) ((typeof(ptr))((unsigned long)(ptr) | BIT(bit)))
>+#define ptr_test_bit(ptr, bit) ((unsigned long)(ptr) & BIT(bit))
>+
>+struct intel_timeline_hwsp {
>+	struct intel_gt *gt;
>+	struct intel_gt_timelines *gt_timelines;
>+	struct list_head free_link;
>+	struct i915_vma *vma;
>+	u64 free_bitmap;
>+};
>+
>+struct intel_timeline_cacheline {
>+	struct i915_active active;
>+	struct intel_timeline_hwsp *hwsp;
>+	void *vaddr;
>+#define CACHELINE_BITS 6
>+#define CACHELINE_FREE CACHELINE_BITS
>+};
>+
>+static struct i915_vma *__hwsp_alloc(struct intel_gt *gt)
>+{
>+	struct drm_i915_private *i915 = gt->i915;
>+	struct drm_i915_gem_object *obj;
>+	struct i915_vma *vma;
>+
>+	obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
>+	if (IS_ERR(obj))
>+		return ERR_CAST(obj);
>+
>+	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
>+
>+	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
>+	if (IS_ERR(vma))
>+		i915_gem_object_put(obj);
>+
>+	return vma;
>+}
>+
>+static struct i915_vma *
>+hwsp_alloc(struct intel_timeline *timeline, unsigned int *cacheline)
>+{
>+	struct intel_gt_timelines *gt = &timeline->gt->timelines;
>+	struct intel_timeline_hwsp *hwsp;
>+
>+	BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
>+
>+	spin_lock_irq(&gt->hwsp_lock);
>+
>+	/* hwsp_free_list only contains HWSP that have available cachelines */
>+	hwsp = list_first_entry_or_null(&gt->hwsp_free_list,
>+					typeof(*hwsp), free_link);
>+	if (!hwsp) {
>+		struct i915_vma *vma;
>+
>+		spin_unlock_irq(&gt->hwsp_lock);
>+
>+		hwsp = kmalloc(sizeof(*hwsp), GFP_KERNEL);
>+		if (!hwsp)
>+			return ERR_PTR(-ENOMEM);
>+
>+		vma = __hwsp_alloc(timeline->gt);
>+		if (IS_ERR(vma)) {
>+			kfree(hwsp);
>+			return vma;
>+		}
>+
>+		vma->private = hwsp;
>+		hwsp->gt = timeline->gt;
>+		hwsp->vma = vma;
>+		hwsp->free_bitmap = ~0ull;
>+		hwsp->gt_timelines = gt;
>+
>+		spin_lock_irq(&gt->hwsp_lock);
>+		list_add(&hwsp->free_link, &gt->hwsp_free_list);
>+	}
>+
>+	GEM_BUG_ON(!hwsp->free_bitmap);
>+	*cacheline = __ffs64(hwsp->free_bitmap);
>+	hwsp->free_bitmap &= ~BIT_ULL(*cacheline);
>+	if (!hwsp->free_bitmap)
>+		list_del(&hwsp->free_link);
>+
>+	spin_unlock_irq(&gt->hwsp_lock);
>+
>+	GEM_BUG_ON(hwsp->vma->private != hwsp);
>+	return hwsp->vma;
>+}
>+
>+static void __idle_hwsp_free(struct intel_timeline_hwsp *hwsp, int cacheline)
>+{
>+	struct intel_gt_timelines *gt = hwsp->gt_timelines;
>+	unsigned long flags;
>+
>+	spin_lock_irqsave(&gt->hwsp_lock, flags);
>+
>+	/* As a cacheline becomes available, publish the HWSP on the freelist */
>+	if (!hwsp->free_bitmap)
>+		list_add_tail(&hwsp->free_link, &gt->hwsp_free_list);
>+
>+	GEM_BUG_ON(cacheline >= BITS_PER_TYPE(hwsp->free_bitmap));
>+	hwsp->free_bitmap |= BIT_ULL(cacheline);
>+
>+	/* And if no one is left using it, give the page back to the system */
>+	if (hwsp->free_bitmap == ~0ull) {
>+		i915_vma_put(hwsp->vma);
>+		list_del(&hwsp->free_link);
>+		kfree(hwsp);
>+	}
>+
>+	spin_unlock_irqrestore(&gt->hwsp_lock, flags);
>+}
>+
>+static void __idle_cacheline_free(struct intel_timeline_cacheline *cl)
>+{
>+	GEM_BUG_ON(!i915_active_is_idle(&cl->active));
>+
>+	i915_gem_object_unpin_map(cl->hwsp->vma->obj);
>+	i915_vma_put(cl->hwsp->vma);
>+	__idle_hwsp_free(cl->hwsp, ptr_unmask_bits(cl->vaddr, CACHELINE_BITS));
>+
>+	i915_active_fini(&cl->active);
>+	kfree(cl);
>+}
>+
>+static void __cacheline_retire(struct i915_active *active)
>+{
>+	struct intel_timeline_cacheline *cl =
>+		container_of(active, typeof(*cl), active);
>+
>+	i915_vma_unpin(cl->hwsp->vma);
>+	if (ptr_test_bit(cl->vaddr, CACHELINE_FREE))
>+		__idle_cacheline_free(cl);
>+}
>+
>+static int __cacheline_active(struct i915_active *active)
>+{
>+	struct intel_timeline_cacheline *cl =
>+		container_of(active, typeof(*cl), active);
>+
>+	__i915_vma_pin(cl->hwsp->vma);
>+	return 0;
>+}
>+
>+static struct intel_timeline_cacheline *
>+cacheline_alloc(struct intel_timeline_hwsp *hwsp, unsigned int cacheline)
>+{
>+	struct intel_timeline_cacheline *cl;
>+	void *vaddr;
>+
>+	GEM_BUG_ON(cacheline >= BIT(CACHELINE_BITS));
>+
>+	cl = kmalloc(sizeof(*cl), GFP_KERNEL);
>+	if (!cl)
>+		return ERR_PTR(-ENOMEM);
>+
>+	vaddr = i915_gem_object_pin_map(hwsp->vma->obj, I915_MAP_WB);
>+	if (IS_ERR(vaddr)) {
>+		kfree(cl);
>+		return ERR_CAST(vaddr);
>+	}
>+
>+	i915_vma_get(hwsp->vma);
>+	cl->hwsp = hwsp;
>+	cl->vaddr = page_pack_bits(vaddr, cacheline);
>+
>+	i915_active_init(hwsp->gt->i915, &cl->active,
>+			 __cacheline_active, __cacheline_retire);
>+
>+	return cl;
>+}
>+
>+static void cacheline_acquire(struct intel_timeline_cacheline *cl)
>+{
>+	if (cl)
>+		i915_active_acquire(&cl->active);
>+}
>+
>+static void cacheline_release(struct intel_timeline_cacheline *cl)
>+{
>+	if (cl)
>+		i915_active_release(&cl->active);
>+}
>+
>+static void cacheline_free(struct intel_timeline_cacheline *cl)
>+{
>+	GEM_BUG_ON(ptr_test_bit(cl->vaddr, CACHELINE_FREE));
>+	cl->vaddr = ptr_set_bit(cl->vaddr, CACHELINE_FREE);
>+
>+	if (i915_active_is_idle(&cl->active))
>+		__idle_cacheline_free(cl);
>+}
>+
>+int intel_timeline_init(struct intel_timeline *timeline,
>+			struct intel_gt *gt,
>+			struct i915_vma *hwsp)
>+{
>+	void *vaddr;
>+
>+	kref_init(&timeline->kref);
>+
>+	timeline->gt = gt;
>+	timeline->pin_count = 0;
>+
>+	timeline->has_initial_breadcrumb = !hwsp;
>+	timeline->hwsp_cacheline = NULL;
>+
>+	if (!hwsp) {
>+		struct intel_timeline_cacheline *cl;
>+		unsigned int cacheline;
>+
>+		hwsp = hwsp_alloc(timeline, &cacheline);
>+		if (IS_ERR(hwsp))
>+			return PTR_ERR(hwsp);
>+
>+		cl = cacheline_alloc(hwsp->private, cacheline);
>+		if (IS_ERR(cl)) {
>+			__idle_hwsp_free(hwsp->private, cacheline);
>+			return PTR_ERR(cl);
>+		}
>+
>+		timeline->hwsp_cacheline = cl;
>+		timeline->hwsp_offset = cacheline * CACHELINE_BYTES;
>+
>+		vaddr = page_mask_bits(cl->vaddr);
>+	} else {
>+		timeline->hwsp_offset = I915_GEM_HWS_SEQNO_ADDR;
>+
>+		vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WB);
>+		if (IS_ERR(vaddr))
>+			return PTR_ERR(vaddr);
>+	}
>+
>+	timeline->hwsp_seqno =
>+		memset(vaddr + timeline->hwsp_offset, 0, CACHELINE_BYTES);
>+
>+	timeline->hwsp_ggtt = i915_vma_get(hwsp);
>+	GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size);
>+
>+	timeline->fence_context = dma_fence_context_alloc(1);
>+
>+	mutex_init(&timeline->mutex);
>+
>+	INIT_ACTIVE_REQUEST(&timeline->last_request);
>+	INIT_LIST_HEAD(&timeline->requests);
>+
>+	i915_syncmap_init(&timeline->sync);
>+
>+	return 0;
>+}
>+
>+static void timelines_init(struct intel_gt *gt)
>+{
>+	struct intel_gt_timelines *timelines = &gt->timelines;
>+
>+	mutex_init(&timelines->mutex);
>+	INIT_LIST_HEAD(&timelines->active_list);
>+
>+	spin_lock_init(&timelines->hwsp_lock);
>+	INIT_LIST_HEAD(&timelines->hwsp_free_list);
>+}
>+
>+void intel_timelines_init(struct drm_i915_private *i915)
>+{
>+	timelines_init(&i915->gt);
>+}
>+
>+static void timeline_add_to_active(struct intel_timeline *tl)
>+{
>+	struct intel_gt_timelines *gt = &tl->gt->timelines;
>+
>+	mutex_lock(&gt->mutex);
>+	list_add(&tl->link, &gt->active_list);
>+	mutex_unlock(&gt->mutex);
>+}
>+
>+static void timeline_remove_from_active(struct intel_timeline *tl)
>+{
>+	struct intel_gt_timelines *gt = &tl->gt->timelines;
>+
>+	mutex_lock(&gt->mutex);
>+	list_del(&tl->link);
>+	mutex_unlock(&gt->mutex);
>+}
>+
>+static void timelines_park(struct intel_gt *gt)
>+{
>+	struct intel_gt_timelines *timelines = &gt->timelines;
>+	struct intel_timeline *timeline;
>+
>+	mutex_lock(&timelines->mutex);
>+	list_for_each_entry(timeline, &timelines->active_list, link) {
>+		/*
>+		 * All known fences are completed so we can scrap
>+		 * the current sync point tracking and start afresh,
>+		 * any attempt to wait upon a previous sync point
>+		 * will be skipped as the fence was signaled.
>+		 */
>+		i915_syncmap_free(&timeline->sync);
>+	}
>+	mutex_unlock(&timelines->mutex);
>+}
>+
>+/**
>+ * intel_timelines_park - called when the driver idles
>+ * @i915: the drm_i915_private device
>+ *
>+ * When the driver is completely idle, we know that all of our sync points
>+ * have been signaled and our tracking is then entirely redundant. Any request
>+ * to wait upon an older sync point will be completed instantly as we know
>+ * the fence is signaled and therefore we will not even look them up in the
>+ * sync point map.
>+ */
>+void intel_timelines_park(struct drm_i915_private *i915)
>+{
>+	timelines_park(&i915->gt);
>+}
>+
>+void intel_timeline_fini(struct intel_timeline *timeline)
>+{
>+	GEM_BUG_ON(timeline->pin_count);
>+	GEM_BUG_ON(!list_empty(&timeline->requests));
>+
>+	i915_syncmap_free(&timeline->sync);
>+
>+	if (timeline->hwsp_cacheline)
>+		cacheline_free(timeline->hwsp_cacheline);
>+	else
>+		i915_gem_object_unpin_map(timeline->hwsp_ggtt->obj);
>+
>+	i915_vma_put(timeline->hwsp_ggtt);
>+}
>+
>+struct intel_timeline *
>+intel_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp)
>+{
>+	struct intel_timeline *timeline;
>+	int err;
>+
>+	timeline = kzalloc(sizeof(*timeline), GFP_KERNEL);
>+	if (!timeline)
>+		return ERR_PTR(-ENOMEM);
>+
>+	err = intel_timeline_init(timeline, gt, global_hwsp);
>+	if (err) {
>+		kfree(timeline);
>+		return ERR_PTR(err);
>+	}
>+
>+	return timeline;
>+}
>+
>+int intel_timeline_pin(struct intel_timeline *tl)
>+{
>+	int err;
>+
>+	if (tl->pin_count++)
>+		return 0;
>+	GEM_BUG_ON(!tl->pin_count);
>+
>+	err = i915_vma_pin(tl->hwsp_ggtt, 0, 0, PIN_GLOBAL | PIN_HIGH);
>+	if (err)
>+		goto unpin;
>+
>+	tl->hwsp_offset =
>+		i915_ggtt_offset(tl->hwsp_ggtt) +
>+		offset_in_page(tl->hwsp_offset);
>+
>+	cacheline_acquire(tl->hwsp_cacheline);
>+	timeline_add_to_active(tl);
>+
>+	return 0;
>+
>+unpin:
>+	tl->pin_count = 0;
>+	return err;
>+}
>+
>+static u32 timeline_advance(struct intel_timeline *tl)
>+{
>+	GEM_BUG_ON(!tl->pin_count);
>+	GEM_BUG_ON(tl->seqno & tl->has_initial_breadcrumb);
>+
>+	return tl->seqno += 1 + tl->has_initial_breadcrumb;
>+}
>+
>+static void timeline_rollback(struct intel_timeline *tl)
>+{
>+	tl->seqno -= 1 + tl->has_initial_breadcrumb;
>+}
>+
>+static noinline int
>+__intel_timeline_get_seqno(struct intel_timeline *tl,
>+			   struct i915_request *rq,
>+			   u32 *seqno)
>+{
>+	struct intel_timeline_cacheline *cl;
>+	unsigned int cacheline;
>+	struct i915_vma *vma;
>+	void *vaddr;
>+	int err;
>+
>+	/*
>+	 * If there is an outstanding GPU reference to this cacheline,
>+	 * such as it being sampled by a HW semaphore on another timeline,
>+	 * we cannot wraparound our seqno value (the HW semaphore does
>+	 * a strict greater-than-or-equals compare, not i915_seqno_passed).
>+	 * So if the cacheline is still busy, we must detach ourselves
>+	 * from it and leave it inflight alongside its users.
>+	 *
>+	 * However, if nobody is watching and we can guarantee that nobody
>+	 * will, we could simply reuse the same cacheline.
>+	 *
>+	 * if (i915_active_request_is_signaled(&tl->last_request) &&
>+	 *     i915_active_is_signaled(&tl->hwsp_cacheline->active))
>+	 *	return 0;
>+	 *
>+	 * That seems unlikely for a busy timeline that needed to wrap in
>+	 * the first place, so just replace the cacheline.
>+	 */
>+
>+	vma = hwsp_alloc(tl, &cacheline);
>+	if (IS_ERR(vma)) {
>+		err = PTR_ERR(vma);
>+		goto err_rollback;
>+	}
>+
>+	err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
>+	if (err) {
>+		__idle_hwsp_free(vma->private, cacheline);
>+		goto err_rollback;
>+	}
>+
>+	cl = cacheline_alloc(vma->private, cacheline);
>+	if (IS_ERR(cl)) {
>+		err = PTR_ERR(cl);
>+		__idle_hwsp_free(vma->private, cacheline);
>+		goto err_unpin;
>+	}
>+	GEM_BUG_ON(cl->hwsp->vma != vma);
>+
>+	/*
>+	 * Attach the old cacheline to the current request, so that we only
>+	 * free it after the current request is retired, which ensures that
>+	 * all writes into the cacheline from previous requests are complete.
>+	 */
>+	err = i915_active_ref(&tl->hwsp_cacheline->active,
>+			      tl->fence_context, rq);
>+	if (err)
>+		goto err_cacheline;
>+
>+	cacheline_release(tl->hwsp_cacheline); /* ownership now xfered to rq */
>+	cacheline_free(tl->hwsp_cacheline);
>+
>+	i915_vma_unpin(tl->hwsp_ggtt); /* binding kept alive by old cacheline */
>+	i915_vma_put(tl->hwsp_ggtt);
>+
>+	tl->hwsp_ggtt = i915_vma_get(vma);
>+
>+	vaddr = page_mask_bits(cl->vaddr);
>+	tl->hwsp_offset = cacheline * CACHELINE_BYTES;
>+	tl->hwsp_seqno =
>+		memset(vaddr + tl->hwsp_offset, 0, CACHELINE_BYTES);
>+
>+	tl->hwsp_offset += i915_ggtt_offset(vma);
>+
>+	cacheline_acquire(cl);
>+	tl->hwsp_cacheline = cl;
>+
>+	*seqno = timeline_advance(tl);
>+	GEM_BUG_ON(i915_seqno_passed(*tl->hwsp_seqno, *seqno));
>+	return 0;
>+
>+err_cacheline:
>+	cacheline_free(cl);
>+err_unpin:
>+	i915_vma_unpin(vma);
>+err_rollback:
>+	timeline_rollback(tl);
>+	return err;
>+}
>+
>+int intel_timeline_get_seqno(struct intel_timeline *tl,
>+			     struct i915_request *rq,
>+			     u32 *seqno)
>+{
>+	*seqno = timeline_advance(tl);
>+
>+	/* Replace the HWSP on wraparound for HW semaphores */
>+	if (unlikely(!*seqno && tl->hwsp_cacheline))
>+		return __intel_timeline_get_seqno(tl, rq, seqno);
>+
>+	return 0;
>+}
>+
>+static int cacheline_ref(struct intel_timeline_cacheline *cl,
>+			 struct i915_request *rq)
>+{
>+	return i915_active_ref(&cl->active, rq->fence.context, rq);
>+}
>+
>+int intel_timeline_read_hwsp(struct i915_request *from,
>+			     struct i915_request *to,
>+			     u32 *hwsp)
>+{
>+	struct intel_timeline_cacheline *cl = from->hwsp_cacheline;
>+	struct intel_timeline *tl = from->timeline;
>+	int err;
>+
>+	GEM_BUG_ON(to->timeline == tl);
>+
>+	mutex_lock_nested(&tl->mutex, SINGLE_DEPTH_NESTING);
>+	err = i915_request_completed(from);
>+	if (!err)
>+		err = cacheline_ref(cl, to);
>+	if (!err) {
>+		if (likely(cl == tl->hwsp_cacheline)) {
>+			*hwsp = tl->hwsp_offset;
>+		} else { /* across a seqno wrap, recover the original offset */
>+			*hwsp = i915_ggtt_offset(cl->hwsp->vma) +
>+				ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) *
>+				CACHELINE_BYTES;
>+		}
>+	}
>+	mutex_unlock(&tl->mutex);
>+
>+	return err;
>+}
>+
>+void intel_timeline_unpin(struct intel_timeline *tl)
>+{
>+	GEM_BUG_ON(!tl->pin_count);
>+	if (--tl->pin_count)
>+		return;
>+
>+	timeline_remove_from_active(tl);
>+	cacheline_release(tl->hwsp_cacheline);
>+
>+	/*
>+	 * Since this timeline is idle, all bariers upon which we were waiting
>+	 * must also be complete and so we can discard the last used barriers
>+	 * without loss of information.
>+	 */
>+	i915_syncmap_free(&tl->sync);
>+
>+	__i915_vma_unpin(tl->hwsp_ggtt);
>+}
>+
>+void __intel_timeline_free(struct kref *kref)
>+{
>+	struct intel_timeline *timeline =
>+		container_of(kref, typeof(*timeline), kref);
>+
>+	intel_timeline_fini(timeline);
>+	kfree(timeline);
>+}
>+
>+static void timelines_fini(struct intel_gt *gt)
>+{
>+	struct intel_gt_timelines *timelines = &gt->timelines;
>+
>+	GEM_BUG_ON(!list_empty(&timelines->active_list));
>+	GEM_BUG_ON(!list_empty(&timelines->hwsp_free_list));
>+
>+	mutex_destroy(&timelines->mutex);
>+}
>+
>+void intel_timelines_fini(struct drm_i915_private *i915)
>+{
>+	timelines_fini(&i915->gt);
>+}
>+
>+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
>+#include "gt/selftests/mock_timeline.c"
>+#include "gt/selftest_timeline.c"
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_timeline.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_timeline.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_timeline.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_timeline.h	2019-08-31 15:01:12.027736183 -0500
>@@ -0,0 +1,93 @@
>+/*
>+ * Copyright Â© 2016 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef I915_TIMELINE_H
>+#define I915_TIMELINE_H
>+
>+#include <linux/lockdep.h>
>+
>+#include "i915_active.h"
>+#include "i915_syncmap.h"
>+#include "gt/intel_timeline_types.h"
>+
>+int intel_timeline_init(struct intel_timeline *tl,
>+			struct intel_gt *gt,
>+			struct i915_vma *hwsp);
>+void intel_timeline_fini(struct intel_timeline *tl);
>+
>+struct intel_timeline *
>+intel_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp);
>+
>+static inline struct intel_timeline *
>+intel_timeline_get(struct intel_timeline *timeline)
>+{
>+	kref_get(&timeline->kref);
>+	return timeline;
>+}
>+
>+void __intel_timeline_free(struct kref *kref);
>+static inline void intel_timeline_put(struct intel_timeline *timeline)
>+{
>+	kref_put(&timeline->kref, __intel_timeline_free);
>+}
>+
>+static inline int __intel_timeline_sync_set(struct intel_timeline *tl,
>+					    u64 context, u32 seqno)
>+{
>+	return i915_syncmap_set(&tl->sync, context, seqno);
>+}
>+
>+static inline int intel_timeline_sync_set(struct intel_timeline *tl,
>+					  const struct dma_fence *fence)
>+{
>+	return __intel_timeline_sync_set(tl, fence->context, fence->seqno);
>+}
>+
>+static inline bool __intel_timeline_sync_is_later(struct intel_timeline *tl,
>+						  u64 context, u32 seqno)
>+{
>+	return i915_syncmap_is_later(&tl->sync, context, seqno);
>+}
>+
>+static inline bool intel_timeline_sync_is_later(struct intel_timeline *tl,
>+						const struct dma_fence *fence)
>+{
>+	return __intel_timeline_sync_is_later(tl, fence->context, fence->seqno);
>+}
>+
>+int intel_timeline_pin(struct intel_timeline *tl);
>+int intel_timeline_get_seqno(struct intel_timeline *tl,
>+			     struct i915_request *rq,
>+			     u32 *seqno);
>+void intel_timeline_unpin(struct intel_timeline *tl);
>+
>+int intel_timeline_read_hwsp(struct i915_request *from,
>+			     struct i915_request *until,
>+			     u32 *hwsp_offset);
>+
>+void intel_timelines_init(struct drm_i915_private *i915);
>+void intel_timelines_park(struct drm_i915_private *i915);
>+void intel_timelines_fini(struct drm_i915_private *i915);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_timeline_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_timeline_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_timeline_types.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_timeline_types.h	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,67 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2016 Intel Corporation
>+ */
>+
>+#ifndef __I915_TIMELINE_TYPES_H__
>+#define __I915_TIMELINE_TYPES_H__
>+
>+#include <linux/list.h>
>+#include <linux/kref.h>
>+#include <linux/mutex.h>
>+#include <linux/types.h>
>+
>+#include "i915_active_types.h"
>+
>+struct drm_i915_private;
>+struct i915_vma;
>+struct intel_timeline_cacheline;
>+struct i915_syncmap;
>+
>+struct intel_timeline {
>+	u64 fence_context;
>+	u32 seqno;
>+
>+	struct mutex mutex; /* protects the flow of requests */
>+
>+	unsigned int pin_count;
>+	const u32 *hwsp_seqno;
>+	struct i915_vma *hwsp_ggtt;
>+	u32 hwsp_offset;
>+
>+	struct intel_timeline_cacheline *hwsp_cacheline;
>+
>+	bool has_initial_breadcrumb;
>+
>+	/**
>+	 * List of breadcrumbs associated with GPU requests currently
>+	 * outstanding.
>+	 */
>+	struct list_head requests;
>+
>+	/* Contains an RCU guarded pointer to the last request. No reference is
>+	 * held to the request, users must carefully acquire a reference to
>+	 * the request using i915_active_request_get_request_rcu(), or hold the
>+	 * struct_mutex.
>+	 */
>+	struct i915_active_request last_request;
>+
>+	/**
>+	 * We track the most recent seqno that we wait on in every context so
>+	 * that we only have to emit a new await and dependency on a more
>+	 * recent sync point. As the contexts may be executed out-of-order, we
>+	 * have to track each individually and can not rely on an absolute
>+	 * global_seqno. When we know that all tracked fences are completed
>+	 * (i.e. when the driver is idle), we know that the syncmap is
>+	 * redundant and we can discard it without loss of generality.
>+	 */
>+	struct i915_syncmap *sync;
>+
>+	struct list_head link;
>+	struct intel_gt *gt;
>+
>+	struct kref kref;
>+};
>+
>+#endif /* __I915_TIMELINE_TYPES_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_workarounds.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_workarounds.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_workarounds.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_workarounds.c	2019-08-31 15:01:12.027736183 -0500
>@@ -6,6 +6,7 @@
> 
> #include "i915_drv.h"
> #include "intel_context.h"
>+#include "intel_gt.h"
> #include "intel_workarounds.h"
> 
> /**
>@@ -49,9 +50,10 @@
>  * - Public functions to init or apply the given workaround type.
>  */
> 
>-static void wa_init_start(struct i915_wa_list *wal, const char *name)
>+static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name)
> {
> 	wal->name = name;
>+	wal->engine_name = engine_name;
> }
> 
> #define WA_LIST_CHUNK (1 << 4)
>@@ -73,8 +75,8 @@
> 	if (!wal->count)
> 		return;
> 
>-	DRM_DEBUG_DRIVER("Initialized %u %s workarounds\n",
>-			 wal->wa_count, wal->name);
>+	DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n",
>+			 wal->wa_count, wal->name, wal->engine_name);
> }
> 
> static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
>@@ -175,19 +177,6 @@
> 	wa_write_masked_or(wal, reg, val, val);
> }
> 
>-static void
>-ignore_wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val)
>-{
>-	struct i915_wa wa = {
>-		.reg  = reg,
>-		.mask = mask,
>-		.val  = val,
>-		/* Bonkers HW, skip verifying */
>-	};
>-
>-	_wa_add(wal, &wa);
>-}
>-
> #define WA_SET_BIT_MASKED(addr, mask) \
> 	wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
> 
>@@ -536,12 +525,6 @@
> 		 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
> 		 GEN8_ERRDETBCTRL);
> 
>-	/* WaDisableBankHangMode:icl */
>-	wa_write(wal,
>-		 GEN8_L3CNTLREG,
>-		 intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
>-		 GEN8_ERRDETBCTRL);
>-
> 	/* Wa_1604370585:icl (pre-prod)
> 	 * Formerly known as WaPushConstantDereferenceHoldDisable
> 	 */
>@@ -596,7 +579,7 @@
> 	if (engine->class != RENDER_CLASS)
> 		return;
> 
>-	wa_init_start(wal, name);
>+	wa_init_start(wal, name, engine->name);
> 
> 	if (IS_GEN(i915, 11))
> 		icl_ctx_workarounds_init(engine, wal);
>@@ -766,7 +749,10 @@
> wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> 	const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
>-	u32 mcr_slice_subslice_mask;
>+	unsigned int slice, subslice;
>+	u32 l3_en, mcr, mcr_mask;
>+
>+	GEM_BUG_ON(INTEL_GEN(i915) < 10);
> 
> 	/*
> 	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
>@@ -774,42 +760,7 @@
> 	 * the case, we might need to program MCR select to a valid L3Bank
> 	 * by default, to make sure we correctly read certain registers
> 	 * later on (in the range 0xB100 - 0xB3FF).
>-	 * This might be incompatible with
>-	 * WaProgramMgsrForCorrectSliceSpecificMmioReads.
>-	 * Fortunately, this should not happen in production hardware, so
>-	 * we only assert that this is the case (instead of implementing
>-	 * something more complex that requires checking the range of every
>-	 * MMIO read).
>-	 */
>-	if (INTEL_GEN(i915) >= 10 &&
>-	    is_power_of_2(sseu->slice_mask)) {
>-		/*
>-		 * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
>-		 * enabled subslice, no need to redirect MCR packet
>-		 */
>-		u32 slice = fls(sseu->slice_mask);
>-		u32 fuse3 =
>-			intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
>-		u8 ss_mask = sseu->subslice_mask[slice];
>-
>-		u8 enabled_mask = (ss_mask | ss_mask >>
>-				   GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
>-		u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
>-
>-		/*
>-		 * Production silicon should have matched L3Bank and
>-		 * subslice enabled
>-		 */
>-		WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
>-	}
>-
>-	if (INTEL_GEN(i915) >= 11)
>-		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
>-					  GEN11_MCR_SUBSLICE_MASK;
>-	else
>-		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
>-					  GEN8_MCR_SUBSLICE_MASK;
>-	/*
>+	 *
> 	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
> 	 * Before any MMIO read into slice/subslice specific registers, MCR
> 	 * packet control register needs to be programmed to point to any
>@@ -819,11 +770,51 @@
> 	 * are consistent across s/ss in almost all cases. In the rare
> 	 * occasions, such as INSTDONE, where this value is dependent
> 	 * on s/ss combo, the read should be done with read_subslice_reg.
>+	 *
>+	 * Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both
>+	 * to which subslice, or to which L3 bank, the respective mmio reads
>+	 * will go, we have to find a common index which works for both
>+	 * accesses.
>+	 *
>+	 * Case where we cannot find a common index fortunately should not
>+	 * happen in production hardware, so we only emit a warning instead of
>+	 * implementing something more complex that requires checking the range
>+	 * of every MMIO read.
> 	 */
>-	wa_write_masked_or(wal,
>-			   GEN8_MCR_SELECTOR,
>-			   mcr_slice_subslice_mask,
>-			   intel_calculate_mcr_s_ss_select(i915));
>+
>+	if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
>+		u32 l3_fuse =
>+			intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
>+			GEN10_L3BANK_MASK;
>+
>+		DRM_DEBUG_DRIVER("L3 fuse = %x\n", l3_fuse);
>+		l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse);
>+	} else {
>+		l3_en = ~0;
>+	}
>+
>+	slice = fls(sseu->slice_mask) - 1;
>+	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
>+	subslice = fls(l3_en & sseu->subslice_mask[slice]);
>+	if (!subslice) {
>+		DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n",
>+			 sseu->subslice_mask[slice], l3_en);
>+		subslice = fls(l3_en);
>+		WARN_ON(!subslice);
>+	}
>+	subslice--;
>+
>+	if (INTEL_GEN(i915) >= 11) {
>+		mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
>+		mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
>+	} else {
>+		mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
>+		mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
>+	}
>+
>+	DRM_DEBUG_DRIVER("MCR slice/subslice = %x\n", mcr);
>+
>+	wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
> }
> 
> static void
>@@ -926,7 +917,7 @@
> {
> 	struct i915_wa_list *wal = &i915->gt_wa_list;
> 
>-	wa_init_start(wal, "GT");
>+	wa_init_start(wal, "GT", "global");
> 	gt_init_workarounds(i915, wal);
> 	wa_init_finish(wal);
> }
>@@ -990,9 +981,9 @@
> 	spin_unlock_irqrestore(&uncore->lock, flags);
> }
> 
>-void intel_gt_apply_workarounds(struct drm_i915_private *i915)
>+void intel_gt_apply_workarounds(struct intel_gt *gt)
> {
>-	wa_list_apply(&i915->uncore, &i915->gt_wa_list);
>+	wa_list_apply(gt->uncore, &gt->i915->gt_wa_list);
> }
> 
> static bool wa_list_verify(struct intel_uncore *uncore,
>@@ -1011,10 +1002,23 @@
> 	return ok;
> }
> 
>-bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
>-				 const char *from)
>+bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from)
> {
>-	return wa_list_verify(&i915->uncore, &i915->gt_wa_list, from);
>+	return wa_list_verify(gt->uncore, &gt->i915->gt_wa_list, from);
>+}
>+
>+static inline bool is_nonpriv_flags_valid(u32 flags)
>+{
>+	/* Check only valid flag bits are set */
>+	if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID)
>+		return false;
>+
>+	/* NB: Only 3 out of 4 enum values are valid for access field */
>+	if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
>+	    RING_FORCE_TO_NONPRIV_ACCESS_INVALID)
>+		return false;
>+
>+	return true;
> }
> 
> static void
>@@ -1027,6 +1031,9 @@
> 	if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
> 		return;
> 
>+	if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
>+		return;
>+
> 	wa.reg.reg |= flags;
> 	_wa_add(wal, &wa);
> }
>@@ -1034,7 +1041,7 @@
> static void
> whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
> {
>-	whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_RW);
>+	whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
> }
> 
> static void gen9_whitelist_build(struct i915_wa_list *w)
>@@ -1115,7 +1122,7 @@
> 	 *   - PS_DEPTH_COUNT_UDW
> 	 */
> 	whitelist_reg_ext(w, PS_INVOCATION_COUNT,
>-			  RING_FORCE_TO_NONPRIV_RD |
>+			  RING_FORCE_TO_NONPRIV_ACCESS_RD |
> 			  RING_FORCE_TO_NONPRIV_RANGE_4);
> }
> 
>@@ -1155,20 +1162,20 @@
> 		 *   - PS_DEPTH_COUNT_UDW
> 		 */
> 		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
>-				  RING_FORCE_TO_NONPRIV_RD |
>+				  RING_FORCE_TO_NONPRIV_ACCESS_RD |
> 				  RING_FORCE_TO_NONPRIV_RANGE_4);
> 		break;
> 
> 	case VIDEO_DECODE_CLASS:
> 		/* hucStatusRegOffset */
> 		whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
>-				  RING_FORCE_TO_NONPRIV_RD);
>+				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
> 		/* hucUKernelHdrInfoRegOffset */
> 		whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
>-				  RING_FORCE_TO_NONPRIV_RD);
>+				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
> 		/* hucStatus2RegOffset */
> 		whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
>-				  RING_FORCE_TO_NONPRIV_RD);
>+				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
> 		break;
> 
> 	default:
>@@ -1181,7 +1188,7 @@
> 	struct drm_i915_private *i915 = engine->i915;
> 	struct i915_wa_list *w = &engine->whitelist;
> 
>-	wa_init_start(w, "whitelist");
>+	wa_init_start(w, "whitelist", engine->name);
> 
> 	if (IS_GEN(i915, 11))
> 		icl_whitelist_build(engine);
>@@ -1240,10 +1247,9 @@
> 			     _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
> 
> 		/* WaPipelineFlushCoherentLines:icl */
>-		ignore_wa_write_or(wal,
>-				   GEN8_L3SQCREG4,
>-				   GEN8_LQSC_FLUSH_COHERENT_LINES,
>-				   GEN8_LQSC_FLUSH_COHERENT_LINES);
>+		wa_write_or(wal,
>+			    GEN8_L3SQCREG4,
>+			    GEN8_LQSC_FLUSH_COHERENT_LINES);
> 
> 		/*
> 		 * Wa_1405543622:icl
>@@ -1270,10 +1276,9 @@
> 		 * Wa_1405733216:icl
> 		 * Formerly known as WaDisableCleanEvicts
> 		 */
>-		ignore_wa_write_or(wal,
>-				   GEN8_L3SQCREG4,
>-				   GEN11_LQSC_CLEAN_EVICT_DISABLE,
>-				   GEN11_LQSC_CLEAN_EVICT_DISABLE);
>+		wa_write_or(wal,
>+			    GEN8_L3SQCREG4,
>+			    GEN11_LQSC_CLEAN_EVICT_DISABLE);
> 
> 		/* WaForwardProgressSoftReset:icl */
> 		wa_write_or(wal,
>@@ -1292,6 +1297,12 @@
> 		wa_write_or(wal,
> 			    GEN7_SARCHKMD,
> 			    GEN7_DISABLE_SAMPLER_PREFETCH);
>+
>+		/* Wa_1409178092:icl */
>+		wa_write_masked_or(wal,
>+				   GEN11_SCRATCH2,
>+				   GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
>+				   0);
> 	}
> 
> 	if (IS_GEN_RANGE(i915, 9, 11)) {
>@@ -1360,7 +1371,7 @@
> 	if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))
> 		return;
> 
>-	if (engine->id == RCS0)
>+	if (engine->class == RENDER_CLASS)
> 		rcs_engine_wa_init(engine, wal);
> 	else
> 		xcs_engine_wa_init(engine, wal);
>@@ -1370,10 +1381,10 @@
> {
> 	struct i915_wa_list *wal = &engine->wa_list;
> 
>-	if (GEM_WARN_ON(INTEL_GEN(engine->i915) < 8))
>+	if (INTEL_GEN(engine->i915) < 8)
> 		return;
> 
>-	wa_init_start(wal, engine->name);
>+	wa_init_start(wal, "engine", engine->name);
> 	engine_init_workarounds(engine, wal);
> 	wa_init_finish(wal);
> }
>@@ -1416,26 +1427,50 @@
> 	return ERR_PTR(err);
> }
> 
>+static bool mcr_range(struct drm_i915_private *i915, u32 offset)
>+{
>+	/*
>+	 * Registers in this range are affected by the MCR selector
>+	 * which only controls CPU initiated MMIO. Routing does not
>+	 * work for CS access so we cannot verify them on this path.
>+	 */
>+	if (INTEL_GEN(i915) >= 8 && (offset >= 0xb100 && offset <= 0xb3ff))
>+		return true;
>+
>+	return false;
>+}
>+
> static int
> wa_list_srm(struct i915_request *rq,
> 	    const struct i915_wa_list *wal,
> 	    struct i915_vma *vma)
> {
>+	struct drm_i915_private *i915 = rq->i915;
>+	unsigned int i, count = 0;
> 	const struct i915_wa *wa;
>-	unsigned int i;
> 	u32 srm, *cs;
> 
> 	srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
>-	if (INTEL_GEN(rq->i915) >= 8)
>+	if (INTEL_GEN(i915) >= 8)
> 		srm++;
> 
>-	cs = intel_ring_begin(rq, 4 * wal->count);
>+	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
>+		if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))
>+			count++;
>+	}
>+
>+	cs = intel_ring_begin(rq, 4 * count);
> 	if (IS_ERR(cs))
> 		return PTR_ERR(cs);
> 
> 	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
>+		u32 offset = i915_mmio_reg_offset(wa->reg);
>+
>+		if (mcr_range(i915, offset))
>+			continue;
>+
> 		*cs++ = srm;
>-		*cs++ = i915_mmio_reg_offset(wa->reg);
>+		*cs++ = offset;
> 		*cs++ = i915_ggtt_offset(vma) + sizeof(u32) * i;
> 		*cs++ = 0;
> 	}
>@@ -1458,7 +1493,7 @@
> 	if (!wal->count)
> 		return 0;
> 
>-	vma = create_scratch(&ce->engine->i915->ggtt.vm, wal->count);
>+	vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count);
> 	if (IS_ERR(vma))
> 		return PTR_ERR(vma);
> 
>@@ -1485,9 +1520,13 @@
> 	}
> 
> 	err = 0;
>-	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
>+	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
>+		if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
>+			continue;
>+
> 		if (!wa_verify(wa, results[i], wal->name, from))
> 			err = -ENXIO;
>+	}
> 
> 	i915_gem_object_unpin_map(vma->obj);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_workarounds.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_workarounds.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_workarounds.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_workarounds.h	2019-08-31 15:01:12.027736183 -0500
>@@ -14,6 +14,7 @@
> struct drm_i915_private;
> struct i915_request;
> struct intel_engine_cs;
>+struct intel_gt;
> 
> static inline void intel_wa_list_free(struct i915_wa_list *wal)
> {
>@@ -25,9 +26,8 @@
> int intel_engine_emit_ctx_wa(struct i915_request *rq);
> 
> void intel_gt_init_workarounds(struct drm_i915_private *i915);
>-void intel_gt_apply_workarounds(struct drm_i915_private *i915);
>-bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
>-				 const char *from);
>+void intel_gt_apply_workarounds(struct intel_gt *gt);
>+bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from);
> 
> void intel_engine_init_whitelist(struct intel_engine_cs *engine);
> void intel_engine_apply_whitelist(struct intel_engine_cs *engine);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_workarounds_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/intel_workarounds_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/intel_workarounds_types.h	2019-08-31 15:01:12.027736183 -0500
>@@ -20,6 +20,7 @@
> 
> struct i915_wa_list {
> 	const char	*name;
>+	const char	*engine_name;
> 	struct i915_wa	*list;
> 	unsigned int	count;
> 	unsigned int	wa_count;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/Makefile	2019-08-31 15:01:12.023736183 -0500
>@@ -1,2 +1,5 @@
>+# For building individual subdir files on the command line
>+subdir-ccflags-y += -I$(srctree)/$(src)/..
>+
> # Extra header tests
>-include $(src)/Makefile.header-test
>+header-test-pattern-$(CONFIG_DRM_I915_WERROR) := *.h
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/Makefile.header-test linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/Makefile.header-test
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/Makefile.header-test	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/Makefile.header-test	1969-12-31 18:00:00.000000000 -0600
>@@ -1,16 +0,0 @@
>-# SPDX-License-Identifier: MIT
>-# Copyright Â© 2019 Intel Corporation
>-
>-# Test the headers are compilable as standalone units
>-header_test := $(notdir $(wildcard $(src)/*.h))
>-
>-quiet_cmd_header_test = HDRTEST $@
>-      cmd_header_test = echo "\#include \"$(<F)\"" > $@
>-
>-header_test_%.c: %.h
>-	$(call cmd,header_test)
>-
>-extra-$(CONFIG_DRM_I915_WERROR) += \
>-	$(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h)))
>-
>-clean-files += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.c,$(h)))
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/mock_engine.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/mock_engine.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/mock_engine.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/mock_engine.c	2019-08-31 15:01:12.027736183 -0500
>@@ -33,15 +33,15 @@
> 
> struct mock_ring {
> 	struct intel_ring base;
>-	struct i915_timeline timeline;
>+	struct intel_timeline timeline;
> };
> 
>-static void mock_timeline_pin(struct i915_timeline *tl)
>+static void mock_timeline_pin(struct intel_timeline *tl)
> {
> 	tl->pin_count++;
> }
> 
>-static void mock_timeline_unpin(struct i915_timeline *tl)
>+static void mock_timeline_unpin(struct intel_timeline *tl)
> {
> 	GEM_BUG_ON(!tl->pin_count);
> 	tl->pin_count--;
>@@ -56,7 +56,7 @@
> 	if (!ring)
> 		return NULL;
> 
>-	if (i915_timeline_init(engine->i915, &ring->timeline, NULL)) {
>+	if (intel_timeline_init(&ring->timeline, engine->gt, NULL)) {
> 		kfree(ring);
> 		return NULL;
> 	}
>@@ -78,7 +78,7 @@
> {
> 	struct mock_ring *ring = container_of(base, typeof(*ring), base);
> 
>-	i915_timeline_fini(&ring->timeline);
>+	intel_timeline_fini(&ring->timeline);
> 	kfree(ring);
> }
> 
>@@ -142,6 +142,7 @@
> 	if (ce->ring)
> 		mock_ring_free(ce->ring);
> 
>+	intel_context_fini(ce);
> 	intel_context_free(ce);
> }
> 
>@@ -155,7 +156,7 @@
> 			return -ENOMEM;
> 	}
> 
>-	ret = intel_context_active_acquire(ce, PIN_HIGH);
>+	ret = intel_context_active_acquire(ce);
> 	if (ret)
> 		return ret;
> 
>@@ -257,6 +258,7 @@
> 
> 	/* minimal engine setup for requests */
> 	engine->base.i915 = i915;
>+	engine->base.gt = &i915->gt;
> 	snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
> 	engine->base.id = id;
> 	engine->base.mask = BIT(id);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftest_hangcheck.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftest_hangcheck.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftest_hangcheck.c	2019-08-31 15:01:12.028736183 -0500
>@@ -25,13 +25,13 @@
> #include <linux/kthread.h>
> 
> #include "gem/i915_gem_context.h"
>+#include "gt/intel_gt.h"
> #include "intel_engine_pm.h"
> 
> #include "i915_selftest.h"
> #include "selftests/i915_random.h"
> #include "selftests/igt_flush_test.h"
> #include "selftests/igt_reset.h"
>-#include "selftests/igt_wedge_me.h"
> #include "selftests/igt_atomic.h"
> 
> #include "selftests/mock_drm.h"
>@@ -42,7 +42,7 @@
> #define IGT_IDLE_TIMEOUT 50 /* ms; time to wait after flushing between tests */
> 
> struct hang {
>-	struct drm_i915_private *i915;
>+	struct intel_gt *gt;
> 	struct drm_i915_gem_object *hws;
> 	struct drm_i915_gem_object *obj;
> 	struct i915_gem_context *ctx;
>@@ -50,27 +50,27 @@
> 	u32 *batch;
> };
> 
>-static int hang_init(struct hang *h, struct drm_i915_private *i915)
>+static int hang_init(struct hang *h, struct intel_gt *gt)
> {
> 	void *vaddr;
> 	int err;
> 
> 	memset(h, 0, sizeof(*h));
>-	h->i915 = i915;
>+	h->gt = gt;
> 
>-	h->ctx = kernel_context(i915);
>+	h->ctx = kernel_context(gt->i915);
> 	if (IS_ERR(h->ctx))
> 		return PTR_ERR(h->ctx);
> 
> 	GEM_BUG_ON(i915_gem_context_is_bannable(h->ctx));
> 
>-	h->hws = i915_gem_object_create_internal(i915, PAGE_SIZE);
>+	h->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
> 	if (IS_ERR(h->hws)) {
> 		err = PTR_ERR(h->hws);
> 		goto err_ctx;
> 	}
> 
>-	h->obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
>+	h->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
> 	if (IS_ERR(h->obj)) {
> 		err = PTR_ERR(h->obj);
> 		goto err_hws;
>@@ -85,7 +85,7 @@
> 	h->seqno = memset(vaddr, 0xff, PAGE_SIZE);
> 
> 	vaddr = i915_gem_object_pin_map(h->obj,
>-					i915_coherent_map_type(i915));
>+					i915_coherent_map_type(gt->i915));
> 	if (IS_ERR(vaddr)) {
> 		err = PTR_ERR(vaddr);
> 		goto err_unpin_hws;
>@@ -127,36 +127,32 @@
> static struct i915_request *
> hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> {
>-	struct drm_i915_private *i915 = h->i915;
>-	struct i915_address_space *vm = h->ctx->vm ?: &i915->ggtt.vm;
>+	struct intel_gt *gt = h->gt;
>+	struct i915_address_space *vm = h->ctx->vm ?: &engine->gt->ggtt->vm;
>+	struct drm_i915_gem_object *obj;
> 	struct i915_request *rq = NULL;
> 	struct i915_vma *hws, *vma;
> 	unsigned int flags;
>+	void *vaddr;
> 	u32 *batch;
> 	int err;
> 
>-	if (i915_gem_object_is_active(h->obj)) {
>-		struct drm_i915_gem_object *obj;
>-		void *vaddr;
>-
>-		obj = i915_gem_object_create_internal(h->i915, PAGE_SIZE);
>-		if (IS_ERR(obj))
>-			return ERR_CAST(obj);
>-
>-		vaddr = i915_gem_object_pin_map(obj,
>-						i915_coherent_map_type(h->i915));
>-		if (IS_ERR(vaddr)) {
>-			i915_gem_object_put(obj);
>-			return ERR_CAST(vaddr);
>-		}
>-
>-		i915_gem_object_unpin_map(h->obj);
>-		i915_gem_object_put(h->obj);
>+	obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
>+	if (IS_ERR(obj))
>+		return ERR_CAST(obj);
> 
>-		h->obj = obj;
>-		h->batch = vaddr;
>+	vaddr = i915_gem_object_pin_map(obj, i915_coherent_map_type(gt->i915));
>+	if (IS_ERR(vaddr)) {
>+		i915_gem_object_put(obj);
>+		return ERR_CAST(vaddr);
> 	}
> 
>+	i915_gem_object_unpin_map(h->obj);
>+	i915_gem_object_put(h->obj);
>+
>+	h->obj = obj;
>+	h->batch = vaddr;
>+
> 	vma = i915_vma_instance(h->obj, vm, NULL);
> 	if (IS_ERR(vma))
> 		return ERR_CAST(vma);
>@@ -188,7 +184,7 @@
> 		goto cancel_rq;
> 
> 	batch = h->batch;
>-	if (INTEL_GEN(i915) >= 8) {
>+	if (INTEL_GEN(gt->i915) >= 8) {
> 		*batch++ = MI_STORE_DWORD_IMM_GEN4;
> 		*batch++ = lower_32_bits(hws_address(hws, rq));
> 		*batch++ = upper_32_bits(hws_address(hws, rq));
>@@ -202,7 +198,7 @@
> 		*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
> 		*batch++ = lower_32_bits(vma->node.start);
> 		*batch++ = upper_32_bits(vma->node.start);
>-	} else if (INTEL_GEN(i915) >= 6) {
>+	} else if (INTEL_GEN(gt->i915) >= 6) {
> 		*batch++ = MI_STORE_DWORD_IMM_GEN4;
> 		*batch++ = 0;
> 		*batch++ = lower_32_bits(hws_address(hws, rq));
>@@ -215,7 +211,7 @@
> 		*batch++ = MI_ARB_CHECK;
> 		*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
> 		*batch++ = lower_32_bits(vma->node.start);
>-	} else if (INTEL_GEN(i915) >= 4) {
>+	} else if (INTEL_GEN(gt->i915) >= 4) {
> 		*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> 		*batch++ = 0;
> 		*batch++ = lower_32_bits(hws_address(hws, rq));
>@@ -242,7 +238,7 @@
> 		*batch++ = lower_32_bits(vma->node.start);
> 	}
> 	*batch++ = MI_BATCH_BUFFER_END; /* not reached */
>-	i915_gem_chipset_flush(h->i915);
>+	intel_gt_chipset_flush(engine->gt);
> 
> 	if (rq->engine->emit_init_breadcrumb) {
> 		err = rq->engine->emit_init_breadcrumb(rq);
>@@ -251,7 +247,7 @@
> 	}
> 
> 	flags = 0;
>-	if (INTEL_GEN(vm->i915) <= 5)
>+	if (INTEL_GEN(gt->i915) <= 5)
> 		flags |= I915_DISPATCH_SECURE;
> 
> 	err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
>@@ -276,7 +272,7 @@
> static void hang_fini(struct hang *h)
> {
> 	*h->batch = MI_BATCH_BUFFER_END;
>-	i915_gem_chipset_flush(h->i915);
>+	intel_gt_chipset_flush(h->gt);
> 
> 	i915_gem_object_unpin_map(h->obj);
> 	i915_gem_object_put(h->obj);
>@@ -286,7 +282,7 @@
> 
> 	kernel_context_close(h->ctx);
> 
>-	igt_flush_test(h->i915, I915_WAIT_LOCKED);
>+	igt_flush_test(h->gt->i915, I915_WAIT_LOCKED);
> }
> 
> static bool wait_until_running(struct hang *h, struct i915_request *rq)
>@@ -301,7 +297,7 @@
> 
> static int igt_hang_sanitycheck(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
> 	struct i915_request *rq;
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
>@@ -310,13 +306,13 @@
> 
> 	/* Basic check that we can execute our hanging batch */
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>-	err = hang_init(&h, i915);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
>+	err = hang_init(&h, gt);
> 	if (err)
> 		goto unlock;
> 
>-	for_each_engine(engine, i915, id) {
>-		struct igt_wedge_me w;
>+	for_each_engine(engine, gt->i915, id) {
>+		struct intel_wedge_me w;
> 		long timeout;
> 
> 		if (!intel_engine_can_store_dword(engine))
>@@ -333,15 +329,15 @@
> 		i915_request_get(rq);
> 
> 		*h.batch = MI_BATCH_BUFFER_END;
>-		i915_gem_chipset_flush(i915);
>+		intel_gt_chipset_flush(engine->gt);
> 
> 		i915_request_add(rq);
> 
> 		timeout = 0;
>-		igt_wedge_on_timeout(&w, i915, HZ / 10 /* 100ms timeout*/)
>+		intel_wedge_on_timeout(&w, gt, HZ / 10 /* 100ms */)
> 			timeout = i915_request_wait(rq, 0,
> 						    MAX_SCHEDULE_TIMEOUT);
>-		if (i915_reset_failed(i915))
>+		if (intel_gt_is_wedged(gt))
> 			timeout = -EIO;
> 
> 		i915_request_put(rq);
>@@ -357,7 +353,7 @@
> fini:
> 	hang_fini(&h);
> unlock:
>-	mutex_unlock(&i915->drm.struct_mutex);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
> 	return err;
> }
> 
>@@ -368,37 +364,37 @@
> 
> static int igt_reset_nop(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
>+	struct i915_gpu_error *global = &gt->i915->gpu_error;
> 	struct intel_engine_cs *engine;
> 	struct i915_gem_context *ctx;
> 	unsigned int reset_count, count;
> 	enum intel_engine_id id;
>-	intel_wakeref_t wakeref;
> 	struct drm_file *file;
> 	IGT_TIMEOUT(end_time);
> 	int err = 0;
> 
> 	/* Check that we can reset during non-user portions of requests */
> 
>-	file = mock_file(i915);
>+	file = mock_file(gt->i915);
> 	if (IS_ERR(file))
> 		return PTR_ERR(file);
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>-	ctx = live_context(i915, file);
>-	mutex_unlock(&i915->drm.struct_mutex);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
>+	ctx = live_context(gt->i915, file);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
> 	if (IS_ERR(ctx)) {
> 		err = PTR_ERR(ctx);
> 		goto out;
> 	}
> 
> 	i915_gem_context_clear_bannable(ctx);
>-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>-	reset_count = i915_reset_count(&i915->gpu_error);
>+	reset_count = i915_reset_count(global);
> 	count = 0;
> 	do {
>-		mutex_lock(&i915->drm.struct_mutex);
>-		for_each_engine(engine, i915, id) {
>+		mutex_lock(&gt->i915->drm.struct_mutex);
>+
>+		for_each_engine(engine, gt->i915, id) {
> 			int i;
> 
> 			for (i = 0; i < 16; i++) {
>@@ -413,82 +409,78 @@
> 				i915_request_add(rq);
> 			}
> 		}
>-		mutex_unlock(&i915->drm.struct_mutex);
> 
>-		igt_global_reset_lock(i915);
>-		i915_reset(i915, ALL_ENGINES, NULL);
>-		igt_global_reset_unlock(i915);
>-		if (i915_reset_failed(i915)) {
>+		igt_global_reset_lock(gt);
>+		intel_gt_reset(gt, ALL_ENGINES, NULL);
>+		igt_global_reset_unlock(gt);
>+
>+		mutex_unlock(&gt->i915->drm.struct_mutex);
>+		if (intel_gt_is_wedged(gt)) {
> 			err = -EIO;
> 			break;
> 		}
> 
>-		if (i915_reset_count(&i915->gpu_error) !=
>-		    reset_count + ++count) {
>+		if (i915_reset_count(global) != reset_count + ++count) {
> 			pr_err("Full GPU reset not recorded!\n");
> 			err = -EINVAL;
> 			break;
> 		}
> 
>-		err = igt_flush_test(i915, 0);
>+		err = igt_flush_test(gt->i915, 0);
> 		if (err)
> 			break;
> 	} while (time_before(jiffies, end_time));
> 	pr_info("%s: %d resets\n", __func__, count);
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>-	err = igt_flush_test(i915, I915_WAIT_LOCKED);
>-	mutex_unlock(&i915->drm.struct_mutex);
>-
>-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
>+	err = igt_flush_test(gt->i915, I915_WAIT_LOCKED);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
> 
> out:
>-	mock_file_free(i915, file);
>-	if (i915_reset_failed(i915))
>+	mock_file_free(gt->i915, file);
>+	if (intel_gt_is_wedged(gt))
> 		err = -EIO;
> 	return err;
> }
> 
> static int igt_reset_nop_engine(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
>+	struct i915_gpu_error *global = &gt->i915->gpu_error;
> 	struct intel_engine_cs *engine;
> 	struct i915_gem_context *ctx;
> 	enum intel_engine_id id;
>-	intel_wakeref_t wakeref;
> 	struct drm_file *file;
> 	int err = 0;
> 
> 	/* Check that we can engine-reset during non-user portions */
> 
>-	if (!intel_has_reset_engine(i915))
>+	if (!intel_has_reset_engine(gt->i915))
> 		return 0;
> 
>-	file = mock_file(i915);
>+	file = mock_file(gt->i915);
> 	if (IS_ERR(file))
> 		return PTR_ERR(file);
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>-	ctx = live_context(i915, file);
>-	mutex_unlock(&i915->drm.struct_mutex);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
>+	ctx = live_context(gt->i915, file);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
> 	if (IS_ERR(ctx)) {
> 		err = PTR_ERR(ctx);
> 		goto out;
> 	}
> 
> 	i915_gem_context_clear_bannable(ctx);
>-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>-	for_each_engine(engine, i915, id) {
>+	for_each_engine(engine, gt->i915, id) {
> 		unsigned int reset_count, reset_engine_count;
> 		unsigned int count;
> 		IGT_TIMEOUT(end_time);
> 
>-		reset_count = i915_reset_count(&i915->gpu_error);
>-		reset_engine_count = i915_reset_engine_count(&i915->gpu_error,
>-							     engine);
>+		reset_count = i915_reset_count(global);
>+		reset_engine_count = i915_reset_engine_count(global, engine);
> 		count = 0;
> 
>-		set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>+		set_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
> 		do {
> 			int i;
> 
>@@ -499,7 +491,7 @@
> 				break;
> 			}
> 
>-			mutex_lock(&i915->drm.struct_mutex);
>+			mutex_lock(&gt->i915->drm.struct_mutex);
> 			for (i = 0; i < 16; i++) {
> 				struct i915_request *rq;
> 
>@@ -511,21 +503,20 @@
> 
> 				i915_request_add(rq);
> 			}
>-			mutex_unlock(&i915->drm.struct_mutex);
>-
>-			err = i915_reset_engine(engine, NULL);
>+			err = intel_engine_reset(engine, NULL);
>+			mutex_unlock(&gt->i915->drm.struct_mutex);
> 			if (err) {
> 				pr_err("i915_reset_engine failed\n");
> 				break;
> 			}
> 
>-			if (i915_reset_count(&i915->gpu_error) != reset_count) {
>+			if (i915_reset_count(global) != reset_count) {
> 				pr_err("Full GPU reset recorded! (engine reset expected)\n");
> 				err = -EINVAL;
> 				break;
> 			}
> 
>-			if (i915_reset_engine_count(&i915->gpu_error, engine) !=
>+			if (i915_reset_engine_count(global, engine) !=
> 			    reset_engine_count + ++count) {
> 				pr_err("%s engine reset not recorded!\n",
> 				       engine->name);
>@@ -533,31 +524,31 @@
> 				break;
> 			}
> 		} while (time_before(jiffies, end_time));
>-		clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>+		clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
> 		pr_info("%s(%s): %d resets\n", __func__, engine->name, count);
> 
> 		if (err)
> 			break;
> 
>-		err = igt_flush_test(i915, 0);
>+		err = igt_flush_test(gt->i915, 0);
> 		if (err)
> 			break;
> 	}
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>-	err = igt_flush_test(i915, I915_WAIT_LOCKED);
>-	mutex_unlock(&i915->drm.struct_mutex);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
>+	err = igt_flush_test(gt->i915, I915_WAIT_LOCKED);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
> 
>-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> out:
>-	mock_file_free(i915, file);
>-	if (i915_reset_failed(i915))
>+	mock_file_free(gt->i915, file);
>+	if (intel_gt_is_wedged(gt))
> 		err = -EIO;
> 	return err;
> }
> 
>-static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
>+static int __igt_reset_engine(struct intel_gt *gt, bool active)
> {
>+	struct i915_gpu_error *global = &gt->i915->gpu_error;
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
> 	struct hang h;
>@@ -565,18 +556,18 @@
> 
> 	/* Check that we can issue an engine reset on an idle engine (no-op) */
> 
>-	if (!intel_has_reset_engine(i915))
>+	if (!intel_has_reset_engine(gt->i915))
> 		return 0;
> 
> 	if (active) {
>-		mutex_lock(&i915->drm.struct_mutex);
>-		err = hang_init(&h, i915);
>-		mutex_unlock(&i915->drm.struct_mutex);
>+		mutex_lock(&gt->i915->drm.struct_mutex);
>+		err = hang_init(&h, gt);
>+		mutex_unlock(&gt->i915->drm.struct_mutex);
> 		if (err)
> 			return err;
> 	}
> 
>-	for_each_engine(engine, i915, id) {
>+	for_each_engine(engine, gt->i915, id) {
> 		unsigned int reset_count, reset_engine_count;
> 		IGT_TIMEOUT(end_time);
> 
>@@ -590,30 +581,29 @@
> 			break;
> 		}
> 
>-		reset_count = i915_reset_count(&i915->gpu_error);
>-		reset_engine_count = i915_reset_engine_count(&i915->gpu_error,
>-							     engine);
>+		reset_count = i915_reset_count(global);
>+		reset_engine_count = i915_reset_engine_count(global, engine);
> 
> 		intel_engine_pm_get(engine);
>-		set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>+		set_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
> 		do {
> 			if (active) {
> 				struct i915_request *rq;
> 
>-				mutex_lock(&i915->drm.struct_mutex);
>+				mutex_lock(&gt->i915->drm.struct_mutex);
> 				rq = hang_create_request(&h, engine);
> 				if (IS_ERR(rq)) {
> 					err = PTR_ERR(rq);
>-					mutex_unlock(&i915->drm.struct_mutex);
>+					mutex_unlock(&gt->i915->drm.struct_mutex);
> 					break;
> 				}
> 
> 				i915_request_get(rq);
> 				i915_request_add(rq);
>-				mutex_unlock(&i915->drm.struct_mutex);
>+				mutex_unlock(&gt->i915->drm.struct_mutex);
> 
> 				if (!wait_until_running(&h, rq)) {
>-					struct drm_printer p = drm_info_printer(i915->drm.dev);
>+					struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
> 
> 					pr_err("%s: Failed to start request %llx, at %x\n",
> 					       __func__, rq->fence.seqno, hws_seqno(&h, rq));
>@@ -628,19 +618,19 @@
> 				i915_request_put(rq);
> 			}
> 
>-			err = i915_reset_engine(engine, NULL);
>+			err = intel_engine_reset(engine, NULL);
> 			if (err) {
> 				pr_err("i915_reset_engine failed\n");
> 				break;
> 			}
> 
>-			if (i915_reset_count(&i915->gpu_error) != reset_count) {
>+			if (i915_reset_count(global) != reset_count) {
> 				pr_err("Full GPU reset recorded! (engine reset expected)\n");
> 				err = -EINVAL;
> 				break;
> 			}
> 
>-			if (i915_reset_engine_count(&i915->gpu_error, engine) !=
>+			if (i915_reset_engine_count(global, engine) !=
> 			    ++reset_engine_count) {
> 				pr_err("%s engine reset not recorded!\n",
> 				       engine->name);
>@@ -648,24 +638,24 @@
> 				break;
> 			}
> 		} while (time_before(jiffies, end_time));
>-		clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>+		clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
> 		intel_engine_pm_put(engine);
> 
> 		if (err)
> 			break;
> 
>-		err = igt_flush_test(i915, 0);
>+		err = igt_flush_test(gt->i915, 0);
> 		if (err)
> 			break;
> 	}
> 
>-	if (i915_reset_failed(i915))
>+	if (intel_gt_is_wedged(gt))
> 		err = -EIO;
> 
> 	if (active) {
>-		mutex_lock(&i915->drm.struct_mutex);
>+		mutex_lock(&gt->i915->drm.struct_mutex);
> 		hang_fini(&h);
>-		mutex_unlock(&i915->drm.struct_mutex);
>+		mutex_unlock(&gt->i915->drm.struct_mutex);
> 	}
> 
> 	return err;
>@@ -707,7 +697,7 @@
> 			  rq->fence.seqno);
> 		GEM_TRACE_DUMP();
> 
>-		i915_gem_set_wedged(rq->i915);
>+		intel_gt_set_wedged(rq->engine->gt);
> 		err = -EIO;
> 	}
> 
>@@ -784,10 +774,11 @@
> 	return err;
> }
> 
>-static int __igt_reset_engines(struct drm_i915_private *i915,
>+static int __igt_reset_engines(struct intel_gt *gt,
> 			       const char *test_name,
> 			       unsigned int flags)
> {
>+	struct i915_gpu_error *global = &gt->i915->gpu_error;
> 	struct intel_engine_cs *engine, *other;
> 	enum intel_engine_id id, tmp;
> 	struct hang h;
>@@ -797,13 +788,13 @@
> 	 * with any other engine.
> 	 */
> 
>-	if (!intel_has_reset_engine(i915))
>+	if (!intel_has_reset_engine(gt->i915))
> 		return 0;
> 
> 	if (flags & TEST_ACTIVE) {
>-		mutex_lock(&i915->drm.struct_mutex);
>-		err = hang_init(&h, i915);
>-		mutex_unlock(&i915->drm.struct_mutex);
>+		mutex_lock(&gt->i915->drm.struct_mutex);
>+		err = hang_init(&h, gt);
>+		mutex_unlock(&gt->i915->drm.struct_mutex);
> 		if (err)
> 			return err;
> 
>@@ -811,9 +802,9 @@
> 			h.ctx->sched.priority = 1024;
> 	}
> 
>-	for_each_engine(engine, i915, id) {
>+	for_each_engine(engine, gt->i915, id) {
> 		struct active_engine threads[I915_NUM_ENGINES] = {};
>-		unsigned long global = i915_reset_count(&i915->gpu_error);
>+		unsigned long device = i915_reset_count(global);
> 		unsigned long count = 0, reported;
> 		IGT_TIMEOUT(end_time);
> 
>@@ -829,12 +820,11 @@
> 		}
> 
> 		memset(threads, 0, sizeof(threads));
>-		for_each_engine(other, i915, tmp) {
>+		for_each_engine(other, gt->i915, tmp) {
> 			struct task_struct *tsk;
> 
> 			threads[tmp].resets =
>-				i915_reset_engine_count(&i915->gpu_error,
>-							other);
>+				i915_reset_engine_count(global, other);
> 
> 			if (!(flags & TEST_OTHERS))
> 				continue;
>@@ -857,25 +847,25 @@
> 		}
> 
> 		intel_engine_pm_get(engine);
>-		set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>+		set_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
> 		do {
> 			struct i915_request *rq = NULL;
> 
> 			if (flags & TEST_ACTIVE) {
>-				mutex_lock(&i915->drm.struct_mutex);
>+				mutex_lock(&gt->i915->drm.struct_mutex);
> 				rq = hang_create_request(&h, engine);
> 				if (IS_ERR(rq)) {
> 					err = PTR_ERR(rq);
>-					mutex_unlock(&i915->drm.struct_mutex);
>+					mutex_unlock(&gt->i915->drm.struct_mutex);
> 					break;
> 				}
> 
> 				i915_request_get(rq);
> 				i915_request_add(rq);
>-				mutex_unlock(&i915->drm.struct_mutex);
>+				mutex_unlock(&gt->i915->drm.struct_mutex);
> 
> 				if (!wait_until_running(&h, rq)) {
>-					struct drm_printer p = drm_info_printer(i915->drm.dev);
>+					struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
> 
> 					pr_err("%s: Failed to start request %llx, at %x\n",
> 					       __func__, rq->fence.seqno, hws_seqno(&h, rq));
>@@ -888,7 +878,7 @@
> 				}
> 			}
> 
>-			err = i915_reset_engine(engine, NULL);
>+			err = intel_engine_reset(engine, NULL);
> 			if (err) {
> 				pr_err("i915_reset_engine(%s:%s): failed, err=%d\n",
> 				       engine->name, test_name, err);
>@@ -900,7 +890,7 @@
> 			if (rq) {
> 				if (i915_request_wait(rq, 0, HZ / 5) < 0) {
> 					struct drm_printer p =
>-						drm_info_printer(i915->drm.dev);
>+						drm_info_printer(gt->i915->drm.dev);
> 
> 					pr_err("i915_reset_engine(%s:%s):"
> 					       " failed to complete request after reset\n",
>@@ -910,7 +900,7 @@
> 					i915_request_put(rq);
> 
> 					GEM_TRACE_DUMP();
>-					i915_gem_set_wedged(i915);
>+					intel_gt_set_wedged(gt);
> 					err = -EIO;
> 					break;
> 				}
>@@ -920,7 +910,7 @@
> 
> 			if (!(flags & TEST_SELF) && !wait_for_idle(engine)) {
> 				struct drm_printer p =
>-					drm_info_printer(i915->drm.dev);
>+					drm_info_printer(gt->i915->drm.dev);
> 
> 				pr_err("i915_reset_engine(%s:%s):"
> 				       " failed to idle after reset\n",
>@@ -932,12 +922,12 @@
> 				break;
> 			}
> 		} while (time_before(jiffies, end_time));
>-		clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>+		clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
> 		intel_engine_pm_put(engine);
> 		pr_info("i915_reset_engine(%s:%s): %lu resets\n",
> 			engine->name, test_name, count);
> 
>-		reported = i915_reset_engine_count(&i915->gpu_error, engine);
>+		reported = i915_reset_engine_count(global, engine);
> 		reported -= threads[engine->id].resets;
> 		if (reported != count) {
> 			pr_err("i915_reset_engine(%s:%s): reset %lu times, but reported %lu\n",
>@@ -947,7 +937,7 @@
> 		}
> 
> unwind:
>-		for_each_engine(other, i915, tmp) {
>+		for_each_engine(other, gt->i915, tmp) {
> 			int ret;
> 
> 			if (!threads[tmp].task)
>@@ -962,22 +952,21 @@
> 			}
> 			put_task_struct(threads[tmp].task);
> 
>-			if (other != engine &&
>+			if (other->uabi_class != engine->uabi_class &&
> 			    threads[tmp].resets !=
>-			    i915_reset_engine_count(&i915->gpu_error, other)) {
>+			    i915_reset_engine_count(global, other)) {
> 				pr_err("Innocent engine %s was reset (count=%ld)\n",
> 				       other->name,
>-				       i915_reset_engine_count(&i915->gpu_error,
>-							       other) -
>+				       i915_reset_engine_count(global, other) -
> 				       threads[tmp].resets);
> 				if (!err)
> 					err = -EINVAL;
> 			}
> 		}
> 
>-		if (global != i915_reset_count(&i915->gpu_error)) {
>+		if (device != i915_reset_count(global)) {
> 			pr_err("Global reset (count=%ld)!\n",
>-			       i915_reset_count(&i915->gpu_error) - global);
>+			       i915_reset_count(global) - device);
> 			if (!err)
> 				err = -EINVAL;
> 		}
>@@ -985,20 +974,20 @@
> 		if (err)
> 			break;
> 
>-		mutex_lock(&i915->drm.struct_mutex);
>-		err = igt_flush_test(i915, I915_WAIT_LOCKED);
>-		mutex_unlock(&i915->drm.struct_mutex);
>+		mutex_lock(&gt->i915->drm.struct_mutex);
>+		err = igt_flush_test(gt->i915, I915_WAIT_LOCKED);
>+		mutex_unlock(&gt->i915->drm.struct_mutex);
> 		if (err)
> 			break;
> 	}
> 
>-	if (i915_reset_failed(i915))
>+	if (intel_gt_is_wedged(gt))
> 		err = -EIO;
> 
> 	if (flags & TEST_ACTIVE) {
>-		mutex_lock(&i915->drm.struct_mutex);
>+		mutex_lock(&gt->i915->drm.struct_mutex);
> 		hang_fini(&h);
>-		mutex_unlock(&i915->drm.struct_mutex);
>+		mutex_unlock(&gt->i915->drm.struct_mutex);
> 	}
> 
> 	return err;
>@@ -1024,13 +1013,13 @@
> 		},
> 		{ }
> 	};
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
> 	typeof(*phases) *p;
> 	int err;
> 
> 	for (p = phases; p->name; p++) {
> 		if (p->flags & TEST_PRIORITY) {
>-			if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
>+			if (!(gt->i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
> 				continue;
> 		}
> 
>@@ -1042,38 +1031,39 @@
> 	return 0;
> }
> 
>-static u32 fake_hangcheck(struct drm_i915_private *i915,
>-			  intel_engine_mask_t mask)
>+static u32 fake_hangcheck(struct intel_gt *gt, intel_engine_mask_t mask)
> {
>-	u32 count = i915_reset_count(&i915->gpu_error);
>+	u32 count = i915_reset_count(&gt->i915->gpu_error);
> 
>-	i915_reset(i915, mask, NULL);
>+	intel_gt_reset(gt, mask, NULL);
> 
> 	return count;
> }
> 
> static int igt_reset_wait(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
>+	struct i915_gpu_error *global = &gt->i915->gpu_error;
>+	struct intel_engine_cs *engine = gt->i915->engine[RCS0];
> 	struct i915_request *rq;
> 	unsigned int reset_count;
> 	struct hang h;
> 	long timeout;
> 	int err;
> 
>-	if (!intel_engine_can_store_dword(i915->engine[RCS0]))
>+	if (!engine || !intel_engine_can_store_dword(engine))
> 		return 0;
> 
> 	/* Check that we detect a stuck waiter and issue a reset */
> 
>-	igt_global_reset_lock(i915);
>+	igt_global_reset_lock(gt);
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>-	err = hang_init(&h, i915);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
>+	err = hang_init(&h, gt);
> 	if (err)
> 		goto unlock;
> 
>-	rq = hang_create_request(&h, i915->engine[RCS0]);
>+	rq = hang_create_request(&h, engine);
> 	if (IS_ERR(rq)) {
> 		err = PTR_ERR(rq);
> 		goto fini;
>@@ -1083,19 +1073,19 @@
> 	i915_request_add(rq);
> 
> 	if (!wait_until_running(&h, rq)) {
>-		struct drm_printer p = drm_info_printer(i915->drm.dev);
>+		struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
> 
> 		pr_err("%s: Failed to start request %llx, at %x\n",
> 		       __func__, rq->fence.seqno, hws_seqno(&h, rq));
> 		intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
> 
>-		i915_gem_set_wedged(i915);
>+		intel_gt_set_wedged(gt);
> 
> 		err = -EIO;
> 		goto out_rq;
> 	}
> 
>-	reset_count = fake_hangcheck(i915, ALL_ENGINES);
>+	reset_count = fake_hangcheck(gt, ALL_ENGINES);
> 
> 	timeout = i915_request_wait(rq, 0, 10);
> 	if (timeout < 0) {
>@@ -1105,7 +1095,7 @@
> 		goto out_rq;
> 	}
> 
>-	if (i915_reset_count(&i915->gpu_error) == reset_count) {
>+	if (i915_reset_count(global) == reset_count) {
> 		pr_err("No GPU reset recorded!\n");
> 		err = -EINVAL;
> 		goto out_rq;
>@@ -1116,10 +1106,10 @@
> fini:
> 	hang_fini(&h);
> unlock:
>-	mutex_unlock(&i915->drm.struct_mutex);
>-	igt_global_reset_unlock(i915);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
>+	igt_global_reset_unlock(gt);
> 
>-	if (i915_reset_failed(i915))
>+	if (intel_gt_is_wedged(gt))
> 		return -EIO;
> 
> 	return err;
>@@ -1178,11 +1168,12 @@
> 	return err;
> }
> 
>-static int __igt_reset_evict_vma(struct drm_i915_private *i915,
>+static int __igt_reset_evict_vma(struct intel_gt *gt,
> 				 struct i915_address_space *vm,
> 				 int (*fn)(void *),
> 				 unsigned int flags)
> {
>+	struct intel_engine_cs *engine = gt->i915->engine[RCS0];
> 	struct drm_i915_gem_object *obj;
> 	struct task_struct *tsk = NULL;
> 	struct i915_request *rq;
>@@ -1190,17 +1181,17 @@
> 	struct hang h;
> 	int err;
> 
>-	if (!intel_engine_can_store_dword(i915->engine[RCS0]))
>+	if (!engine || !intel_engine_can_store_dword(engine))
> 		return 0;
> 
> 	/* Check that we can recover an unbind stuck on a hanging request */
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>-	err = hang_init(&h, i915);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
>+	err = hang_init(&h, gt);
> 	if (err)
> 		goto unlock;
> 
>-	obj = i915_gem_object_create_internal(i915, SZ_1M);
>+	obj = i915_gem_object_create_internal(gt->i915, SZ_1M);
> 	if (IS_ERR(obj)) {
> 		err = PTR_ERR(obj);
> 		goto fini;
>@@ -1220,7 +1211,7 @@
> 		goto out_obj;
> 	}
> 
>-	rq = hang_create_request(&h, i915->engine[RCS0]);
>+	rq = hang_create_request(&h, engine);
> 	if (IS_ERR(rq)) {
> 		err = PTR_ERR(rq);
> 		goto out_obj;
>@@ -1258,16 +1249,16 @@
> 	if (err)
> 		goto out_rq;
> 
>-	mutex_unlock(&i915->drm.struct_mutex);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
> 
> 	if (!wait_until_running(&h, rq)) {
>-		struct drm_printer p = drm_info_printer(i915->drm.dev);
>+		struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
> 
> 		pr_err("%s: Failed to start request %llx, at %x\n",
> 		       __func__, rq->fence.seqno, hws_seqno(&h, rq));
> 		intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
> 
>-		i915_gem_set_wedged(i915);
>+		intel_gt_set_wedged(gt);
> 		goto out_reset;
> 	}
> 
>@@ -1284,31 +1275,31 @@
> 	wait_for_completion(&arg.completion);
> 
> 	if (wait_for(!list_empty(&rq->fence.cb_list), 10)) {
>-		struct drm_printer p = drm_info_printer(i915->drm.dev);
>+		struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
> 
> 		pr_err("igt/evict_vma kthread did not wait\n");
> 		intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
> 
>-		i915_gem_set_wedged(i915);
>+		intel_gt_set_wedged(gt);
> 		goto out_reset;
> 	}
> 
> out_reset:
>-	igt_global_reset_lock(i915);
>-	fake_hangcheck(rq->i915, rq->engine->mask);
>-	igt_global_reset_unlock(i915);
>+	igt_global_reset_lock(gt);
>+	fake_hangcheck(gt, rq->engine->mask);
>+	igt_global_reset_unlock(gt);
> 
> 	if (tsk) {
>-		struct igt_wedge_me w;
>+		struct intel_wedge_me w;
> 
> 		/* The reset, even indirectly, should take less than 10ms. */
>-		igt_wedge_on_timeout(&w, i915, HZ / 10 /* 100ms timeout*/)
>+		intel_wedge_on_timeout(&w, gt, HZ / 10 /* 100ms */)
> 			err = kthread_stop(tsk);
> 
> 		put_task_struct(tsk);
> 	}
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
> out_rq:
> 	i915_request_put(rq);
> out_obj:
>@@ -1316,9 +1307,9 @@
> fini:
> 	hang_fini(&h);
> unlock:
>-	mutex_unlock(&i915->drm.struct_mutex);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
> 
>-	if (i915_reset_failed(i915))
>+	if (intel_gt_is_wedged(gt))
> 		return -EIO;
> 
> 	return err;
>@@ -1326,26 +1317,26 @@
> 
> static int igt_reset_evict_ggtt(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
> 
>-	return __igt_reset_evict_vma(i915, &i915->ggtt.vm,
>+	return __igt_reset_evict_vma(gt, &gt->ggtt->vm,
> 				     evict_vma, EXEC_OBJECT_WRITE);
> }
> 
> static int igt_reset_evict_ppgtt(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
> 	struct i915_gem_context *ctx;
> 	struct drm_file *file;
> 	int err;
> 
>-	file = mock_file(i915);
>+	file = mock_file(gt->i915);
> 	if (IS_ERR(file))
> 		return PTR_ERR(file);
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>-	ctx = live_context(i915, file);
>-	mutex_unlock(&i915->drm.struct_mutex);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
>+	ctx = live_context(gt->i915, file);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
> 	if (IS_ERR(ctx)) {
> 		err = PTR_ERR(ctx);
> 		goto out;
>@@ -1353,29 +1344,29 @@
> 
> 	err = 0;
> 	if (ctx->vm) /* aliasing == global gtt locking, covered above */
>-		err = __igt_reset_evict_vma(i915, ctx->vm,
>+		err = __igt_reset_evict_vma(gt, ctx->vm,
> 					    evict_vma, EXEC_OBJECT_WRITE);
> 
> out:
>-	mock_file_free(i915, file);
>+	mock_file_free(gt->i915, file);
> 	return err;
> }
> 
> static int igt_reset_evict_fence(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
> 
>-	return __igt_reset_evict_vma(i915, &i915->ggtt.vm,
>+	return __igt_reset_evict_vma(gt, &gt->ggtt->vm,
> 				     evict_fence, EXEC_OBJECT_NEEDS_FENCE);
> }
> 
>-static int wait_for_others(struct drm_i915_private *i915,
>+static int wait_for_others(struct intel_gt *gt,
> 			   struct intel_engine_cs *exclude)
> {
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
> 
>-	for_each_engine(engine, i915, id) {
>+	for_each_engine(engine, gt->i915, id) {
> 		if (engine == exclude)
> 			continue;
> 
>@@ -1388,7 +1379,8 @@
> 
> static int igt_reset_queue(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
>+	struct i915_gpu_error *global = &gt->i915->gpu_error;
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
> 	struct hang h;
>@@ -1396,14 +1388,14 @@
> 
> 	/* Check that we replay pending requests following a hang */
> 
>-	igt_global_reset_lock(i915);
>+	igt_global_reset_lock(gt);
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>-	err = hang_init(&h, i915);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
>+	err = hang_init(&h, gt);
> 	if (err)
> 		goto unlock;
> 
>-	for_each_engine(engine, i915, id) {
>+	for_each_engine(engine, gt->i915, id) {
> 		struct i915_request *prev;
> 		IGT_TIMEOUT(end_time);
> 		unsigned int count;
>@@ -1444,7 +1436,7 @@
> 			 * (hangcheck), or we focus on resetting just one
> 			 * engine and so avoid repeatedly resetting innocents.
> 			 */
>-			err = wait_for_others(i915, engine);
>+			err = wait_for_others(gt, engine);
> 			if (err) {
> 				pr_err("%s(%s): Failed to idle other inactive engines after device reset\n",
> 				       __func__, engine->name);
>@@ -1452,12 +1444,12 @@
> 				i915_request_put(prev);
> 
> 				GEM_TRACE_DUMP();
>-				i915_gem_set_wedged(i915);
>+				intel_gt_set_wedged(gt);
> 				goto fini;
> 			}
> 
> 			if (!wait_until_running(&h, prev)) {
>-				struct drm_printer p = drm_info_printer(i915->drm.dev);
>+				struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
> 
> 				pr_err("%s(%s): Failed to start request %llx, at %x\n",
> 				       __func__, engine->name,
>@@ -1468,13 +1460,13 @@
> 				i915_request_put(rq);
> 				i915_request_put(prev);
> 
>-				i915_gem_set_wedged(i915);
>+				intel_gt_set_wedged(gt);
> 
> 				err = -EIO;
> 				goto fini;
> 			}
> 
>-			reset_count = fake_hangcheck(i915, BIT(id));
>+			reset_count = fake_hangcheck(gt, BIT(id));
> 
> 			if (prev->fence.error != -EIO) {
> 				pr_err("GPU reset not recorded on hanging request [fence.error=%d]!\n",
>@@ -1494,7 +1486,7 @@
> 				goto fini;
> 			}
> 
>-			if (i915_reset_count(&i915->gpu_error) == reset_count) {
>+			if (i915_reset_count(global) == reset_count) {
> 				pr_err("No GPU reset recorded!\n");
> 				i915_request_put(rq);
> 				i915_request_put(prev);
>@@ -1509,11 +1501,11 @@
> 		pr_info("%s: Completed %d resets\n", engine->name, count);
> 
> 		*h.batch = MI_BATCH_BUFFER_END;
>-		i915_gem_chipset_flush(i915);
>+		intel_gt_chipset_flush(engine->gt);
> 
> 		i915_request_put(prev);
> 
>-		err = igt_flush_test(i915, I915_WAIT_LOCKED);
>+		err = igt_flush_test(gt->i915, I915_WAIT_LOCKED);
> 		if (err)
> 			break;
> 	}
>@@ -1521,10 +1513,10 @@
> fini:
> 	hang_fini(&h);
> unlock:
>-	mutex_unlock(&i915->drm.struct_mutex);
>-	igt_global_reset_unlock(i915);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
>+	igt_global_reset_unlock(gt);
> 
>-	if (i915_reset_failed(i915))
>+	if (intel_gt_is_wedged(gt))
> 		return -EIO;
> 
> 	return err;
>@@ -1532,8 +1524,9 @@
> 
> static int igt_handle_error(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>-	struct intel_engine_cs *engine = i915->engine[RCS0];
>+	struct intel_gt *gt = arg;
>+	struct i915_gpu_error *global = &gt->i915->gpu_error;
>+	struct intel_engine_cs *engine = gt->i915->engine[RCS0];
> 	struct hang h;
> 	struct i915_request *rq;
> 	struct i915_gpu_state *error;
>@@ -1541,15 +1534,15 @@
> 
> 	/* Check that we can issue a global GPU and engine reset */
> 
>-	if (!intel_has_reset_engine(i915))
>+	if (!intel_has_reset_engine(gt->i915))
> 		return 0;
> 
> 	if (!engine || !intel_engine_can_store_dword(engine))
> 		return 0;
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
> 
>-	err = hang_init(&h, i915);
>+	err = hang_init(&h, gt);
> 	if (err)
> 		goto err_unlock;
> 
>@@ -1563,28 +1556,28 @@
> 	i915_request_add(rq);
> 
> 	if (!wait_until_running(&h, rq)) {
>-		struct drm_printer p = drm_info_printer(i915->drm.dev);
>+		struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
> 
> 		pr_err("%s: Failed to start request %llx, at %x\n",
> 		       __func__, rq->fence.seqno, hws_seqno(&h, rq));
> 		intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
> 
>-		i915_gem_set_wedged(i915);
>+		intel_gt_set_wedged(gt);
> 
> 		err = -EIO;
> 		goto err_request;
> 	}
> 
>-	mutex_unlock(&i915->drm.struct_mutex);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
> 
> 	/* Temporarily disable error capture */
>-	error = xchg(&i915->gpu_error.first_error, (void *)-1);
>+	error = xchg(&global->first_error, (void *)-1);
> 
>-	i915_handle_error(i915, engine->mask, 0, NULL);
>+	intel_gt_handle_error(gt, engine->mask, 0, NULL);
> 
>-	xchg(&i915->gpu_error.first_error, error);
>+	xchg(&global->first_error, error);
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
> 
> 	if (rq->fence.error != -EIO) {
> 		pr_err("Guilty request not identified!\n");
>@@ -1597,7 +1590,7 @@
> err_fini:
> 	hang_fini(&h);
> err_unlock:
>-	mutex_unlock(&i915->drm.struct_mutex);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
> 	return err;
> }
> 
>@@ -1614,7 +1607,7 @@
> 	tasklet_disable_nosync(t);
> 	p->critical_section_begin();
> 
>-	err = i915_reset_engine(engine, NULL);
>+	err = intel_engine_reset(engine, NULL);
> 
> 	p->critical_section_end();
> 	tasklet_enable(t);
>@@ -1629,7 +1622,6 @@
> static int igt_atomic_reset_engine(struct intel_engine_cs *engine,
> 				   const struct igt_atomic_section *p)
> {
>-	struct drm_i915_private *i915 = engine->i915;
> 	struct i915_request *rq;
> 	struct hang h;
> 	int err;
>@@ -1638,7 +1630,7 @@
> 	if (err)
> 		return err;
> 
>-	err = hang_init(&h, i915);
>+	err = hang_init(&h, engine->gt);
> 	if (err)
> 		return err;
> 
>@@ -1657,16 +1649,16 @@
> 		pr_err("%s(%s): Failed to start request %llx, at %x\n",
> 		       __func__, engine->name,
> 		       rq->fence.seqno, hws_seqno(&h, rq));
>-		i915_gem_set_wedged(i915);
>+		intel_gt_set_wedged(engine->gt);
> 		err = -EIO;
> 	}
> 
> 	if (err == 0) {
>-		struct igt_wedge_me w;
>+		struct intel_wedge_me w;
> 
>-		igt_wedge_on_timeout(&w, i915, HZ / 20 /* 50ms timeout*/)
>+		intel_wedge_on_timeout(&w, engine->gt, HZ / 20 /* 50ms */)
> 			i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
>-		if (i915_reset_failed(i915))
>+		if (intel_gt_is_wedged(engine->gt))
> 			err = -EIO;
> 	}
> 
>@@ -1678,30 +1670,30 @@
> 
> static int igt_reset_engines_atomic(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
> 	const typeof(*igt_atomic_phases) *p;
> 	int err = 0;
> 
> 	/* Check that the engines resets are usable from atomic context */
> 
>-	if (!intel_has_reset_engine(i915))
>+	if (!intel_has_reset_engine(gt->i915))
> 		return 0;
> 
>-	if (USES_GUC_SUBMISSION(i915))
>+	if (USES_GUC_SUBMISSION(gt->i915))
> 		return 0;
> 
>-	igt_global_reset_lock(i915);
>-	mutex_lock(&i915->drm.struct_mutex);
>+	igt_global_reset_lock(gt);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
> 
> 	/* Flush any requests before we get started and check basics */
>-	if (!igt_force_reset(i915))
>+	if (!igt_force_reset(gt))
> 		goto unlock;
> 
> 	for (p = igt_atomic_phases; p->name; p++) {
> 		struct intel_engine_cs *engine;
> 		enum intel_engine_id id;
> 
>-		for_each_engine(engine, i915, id) {
>+		for_each_engine(engine, gt->i915, id) {
> 			err = igt_atomic_reset_engine(engine, p);
> 			if (err)
> 				goto out;
>@@ -1710,11 +1702,11 @@
> 
> out:
> 	/* As we poke around the guts, do a full reset before continuing. */
>-	igt_force_reset(i915);
>+	igt_force_reset(gt);
> 
> unlock:
>-	mutex_unlock(&i915->drm.struct_mutex);
>-	igt_global_reset_unlock(i915);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
>+	igt_global_reset_unlock(gt);
> 
> 	return err;
> }
>@@ -1736,28 +1728,29 @@
> 		SUBTEST(igt_reset_evict_fence),
> 		SUBTEST(igt_handle_error),
> 	};
>+	struct intel_gt *gt = &i915->gt;
> 	intel_wakeref_t wakeref;
> 	bool saved_hangcheck;
> 	int err;
> 
>-	if (!intel_has_gpu_reset(i915))
>+	if (!intel_has_gpu_reset(gt->i915))
> 		return 0;
> 
>-	if (i915_terminally_wedged(i915))
>+	if (intel_gt_is_wedged(gt))
> 		return -EIO; /* we're long past hope of a successful reset */
> 
>-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>+	wakeref = intel_runtime_pm_get(&gt->i915->runtime_pm);
> 	saved_hangcheck = fetch_and_zero(&i915_modparams.enable_hangcheck);
>-	drain_delayed_work(&i915->gpu_error.hangcheck_work); /* flush param */
>+	drain_delayed_work(&gt->hangcheck.work); /* flush param */
> 
>-	err = i915_subtests(tests, i915);
>+	err = intel_gt_live_subtests(tests, gt);
> 
>-	mutex_lock(&i915->drm.struct_mutex);
>-	igt_flush_test(i915, I915_WAIT_LOCKED);
>-	mutex_unlock(&i915->drm.struct_mutex);
>+	mutex_lock(&gt->i915->drm.struct_mutex);
>+	igt_flush_test(gt->i915, I915_WAIT_LOCKED);
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
> 
> 	i915_modparams.enable_hangcheck = saved_hangcheck;
>-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>+	intel_runtime_pm_put(&gt->i915->runtime_pm, wakeref);
> 
> 	return err;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftest_lrc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftest_lrc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftest_lrc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftest_lrc.c	2019-08-31 15:01:12.028736183 -0500
>@@ -55,7 +55,7 @@
> 		if (!igt_wait_for_spinner(&spin, rq)) {
> 			GEM_TRACE("spinner failed to start\n");
> 			GEM_TRACE_DUMP();
>-			i915_gem_set_wedged(i915);
>+			intel_gt_set_wedged(&i915->gt);
> 			err = -EIO;
> 			goto err_ctx;
> 		}
>@@ -73,12 +73,231 @@
> err_spin:
> 	igt_spinner_fini(&spin);
> err_unlock:
>-	igt_flush_test(i915, I915_WAIT_LOCKED);
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> 	mutex_unlock(&i915->drm.struct_mutex);
> 	return err;
> }
> 
>+static int
>+emit_semaphore_chain(struct i915_request *rq, struct i915_vma *vma, int idx)
>+{
>+	u32 *cs;
>+
>+	cs = intel_ring_begin(rq, 10);
>+	if (IS_ERR(cs))
>+		return PTR_ERR(cs);
>+
>+	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
>+
>+	*cs++ = MI_SEMAPHORE_WAIT |
>+		MI_SEMAPHORE_GLOBAL_GTT |
>+		MI_SEMAPHORE_POLL |
>+		MI_SEMAPHORE_SAD_NEQ_SDD;
>+	*cs++ = 0;
>+	*cs++ = i915_ggtt_offset(vma) + 4 * idx;
>+	*cs++ = 0;
>+
>+	if (idx > 0) {
>+		*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>+		*cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1);
>+		*cs++ = 0;
>+		*cs++ = 1;
>+	} else {
>+		*cs++ = MI_NOOP;
>+		*cs++ = MI_NOOP;
>+		*cs++ = MI_NOOP;
>+		*cs++ = MI_NOOP;
>+	}
>+
>+	*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
>+
>+	intel_ring_advance(rq, cs);
>+	return 0;
>+}
>+
>+static struct i915_request *
>+semaphore_queue(struct intel_engine_cs *engine, struct i915_vma *vma, int idx)
>+{
>+	struct i915_gem_context *ctx;
>+	struct i915_request *rq;
>+	int err;
>+
>+	ctx = kernel_context(engine->i915);
>+	if (!ctx)
>+		return ERR_PTR(-ENOMEM);
>+
>+	rq = igt_request_alloc(ctx, engine);
>+	if (IS_ERR(rq))
>+		goto out_ctx;
>+
>+	err = emit_semaphore_chain(rq, vma, idx);
>+	i915_request_add(rq);
>+	if (err)
>+		rq = ERR_PTR(err);
>+
>+out_ctx:
>+	kernel_context_close(ctx);
>+	return rq;
>+}
>+
>+static int
>+release_queue(struct intel_engine_cs *engine,
>+	      struct i915_vma *vma,
>+	      int idx)
>+{
>+	struct i915_sched_attr attr = {
>+		.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX),
>+	};
>+	struct i915_request *rq;
>+	u32 *cs;
>+
>+	rq = i915_request_create(engine->kernel_context);
>+	if (IS_ERR(rq))
>+		return PTR_ERR(rq);
>+
>+	cs = intel_ring_begin(rq, 4);
>+	if (IS_ERR(cs)) {
>+		i915_request_add(rq);
>+		return PTR_ERR(cs);
>+	}
>+
>+	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>+	*cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1);
>+	*cs++ = 0;
>+	*cs++ = 1;
>+
>+	intel_ring_advance(rq, cs);
>+	i915_request_add(rq);
>+
>+	engine->schedule(rq, &attr);
>+
>+	return 0;
>+}
>+
>+static int
>+slice_semaphore_queue(struct intel_engine_cs *outer,
>+		      struct i915_vma *vma,
>+		      int count)
>+{
>+	struct intel_engine_cs *engine;
>+	struct i915_request *head;
>+	enum intel_engine_id id;
>+	int err, i, n = 0;
>+
>+	head = semaphore_queue(outer, vma, n++);
>+	if (IS_ERR(head))
>+		return PTR_ERR(head);
>+
>+	i915_request_get(head);
>+	for_each_engine(engine, outer->i915, id) {
>+		for (i = 0; i < count; i++) {
>+			struct i915_request *rq;
>+
>+			rq = semaphore_queue(engine, vma, n++);
>+			if (IS_ERR(rq)) {
>+				err = PTR_ERR(rq);
>+				goto out;
>+			}
>+		}
>+	}
>+
>+	err = release_queue(outer, vma, n);
>+	if (err)
>+		goto out;
>+
>+	if (i915_request_wait(head,
>+			      I915_WAIT_LOCKED,
>+			      2 * RUNTIME_INFO(outer->i915)->num_engines * (count + 2) * (count + 3)) < 0) {
>+		pr_err("Failed to slice along semaphore chain of length (%d, %d)!\n",
>+		       count, n);
>+		GEM_TRACE_DUMP();
>+		intel_gt_set_wedged(outer->gt);
>+		err = -EIO;
>+	}
>+
>+out:
>+	i915_request_put(head);
>+	return err;
>+}
>+
>+static int live_timeslice_preempt(void *arg)
>+{
>+	struct drm_i915_private *i915 = arg;
>+	struct drm_i915_gem_object *obj;
>+	intel_wakeref_t wakeref;
>+	struct i915_vma *vma;
>+	void *vaddr;
>+	int err = 0;
>+	int count;
>+
>+	/*
>+	 * If a request takes too long, we would like to give other users
>+	 * a fair go on the GPU. In particular, users may create batches
>+	 * that wait upon external input, where that input may even be
>+	 * supplied by another GPU job. To avoid blocking forever, we
>+	 * need to preempt the current task and replace it with another
>+	 * ready task.
>+	 */
>+
>+	mutex_lock(&i915->drm.struct_mutex);
>+	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>+
>+	obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
>+	if (IS_ERR(obj)) {
>+		err = PTR_ERR(obj);
>+		goto err_unlock;
>+	}
>+
>+	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
>+	if (IS_ERR(vma)) {
>+		err = PTR_ERR(vma);
>+		goto err_obj;
>+	}
>+
>+	vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
>+	if (IS_ERR(vaddr)) {
>+		err = PTR_ERR(vaddr);
>+		goto err_obj;
>+	}
>+
>+	err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
>+	if (err)
>+		goto err_map;
>+
>+	for_each_prime_number_from(count, 1, 16) {
>+		struct intel_engine_cs *engine;
>+		enum intel_engine_id id;
>+
>+		for_each_engine(engine, i915, id) {
>+			if (!intel_engine_has_preemption(engine))
>+				continue;
>+
>+			memset(vaddr, 0, PAGE_SIZE);
>+
>+			err = slice_semaphore_queue(engine, vma, count);
>+			if (err)
>+				goto err_pin;
>+
>+			if (igt_flush_test(i915, I915_WAIT_LOCKED)) {
>+				err = -EIO;
>+				goto err_pin;
>+			}
>+		}
>+	}
>+
>+err_pin:
>+	i915_vma_unpin(vma);
>+err_map:
>+	i915_gem_object_unpin_map(obj);
>+err_obj:
>+	i915_gem_object_put(obj);
>+err_unlock:
>+	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>+	mutex_unlock(&i915->drm.struct_mutex);
>+
>+	return err;
>+}
>+
> static int live_busywait_preempt(void *arg)
> {
> 	struct drm_i915_private *i915 = arg;
>@@ -138,6 +357,9 @@
> 		struct igt_live_test t;
> 		u32 *cs;
> 
>+		if (!intel_engine_has_preemption(engine))
>+			continue;
>+
> 		if (!intel_engine_can_store_dword(engine))
> 			continue;
> 
>@@ -229,7 +451,7 @@
> 			intel_engine_dump(engine, &p, "%s\n", engine->name);
> 			GEM_TRACE_DUMP();
> 
>-			i915_gem_set_wedged(i915);
>+			intel_gt_set_wedged(&i915->gt);
> 			err = -EIO;
> 			goto err_vma;
> 		}
>@@ -253,8 +475,6 @@
> err_ctx_hi:
> 	kernel_context_close(ctx_hi);
> err_unlock:
>-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>-		err = -EIO;
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> 	mutex_unlock(&i915->drm.struct_mutex);
> 	return err;
>@@ -320,7 +540,7 @@
> 		if (!igt_wait_for_spinner(&spin_lo, rq)) {
> 			GEM_TRACE("lo spinner failed to start\n");
> 			GEM_TRACE_DUMP();
>-			i915_gem_set_wedged(i915);
>+			intel_gt_set_wedged(&i915->gt);
> 			err = -EIO;
> 			goto err_ctx_lo;
> 		}
>@@ -337,7 +557,7 @@
> 		if (!igt_wait_for_spinner(&spin_hi, rq)) {
> 			GEM_TRACE("hi spinner failed to start\n");
> 			GEM_TRACE_DUMP();
>-			i915_gem_set_wedged(i915);
>+			intel_gt_set_wedged(&i915->gt);
> 			err = -EIO;
> 			goto err_ctx_lo;
> 		}
>@@ -361,7 +581,6 @@
> err_spin_hi:
> 	igt_spinner_fini(&spin_hi);
> err_unlock:
>-	igt_flush_test(i915, I915_WAIT_LOCKED);
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> 	mutex_unlock(&i915->drm.struct_mutex);
> 	return err;
>@@ -398,6 +617,9 @@
> 	if (!ctx_lo)
> 		goto err_ctx_hi;
> 
>+	/* Make sure ctx_lo stays before ctx_hi until we trigger preemption. */
>+	ctx_lo->sched.priority = I915_USER_PRIORITY(1);
>+
> 	for_each_engine(engine, i915, id) {
> 		struct igt_live_test t;
> 		struct i915_request *rq;
>@@ -465,7 +687,6 @@
> err_spin_hi:
> 	igt_spinner_fini(&spin_hi);
> err_unlock:
>-	igt_flush_test(i915, I915_WAIT_LOCKED);
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> 	mutex_unlock(&i915->drm.struct_mutex);
> 	return err;
>@@ -473,7 +694,7 @@
> err_wedged:
> 	igt_spinner_end(&spin_hi);
> 	igt_spinner_end(&spin_lo);
>-	i915_gem_set_wedged(i915);
>+	intel_gt_set_wedged(&i915->gt);
> 	err = -EIO;
> 	goto err_ctx_lo;
> }
>@@ -506,6 +727,114 @@
> 	kernel_context_close(c->ctx);
> }
> 
>+static int live_nopreempt(void *arg)
>+{
>+	struct drm_i915_private *i915 = arg;
>+	struct intel_engine_cs *engine;
>+	struct preempt_client a, b;
>+	enum intel_engine_id id;
>+	intel_wakeref_t wakeref;
>+	int err = -ENOMEM;
>+
>+	/*
>+	 * Verify that we can disable preemption for an individual request
>+	 * that may be being observed and not want to be interrupted.
>+	 */
>+
>+	if (!HAS_LOGICAL_RING_PREEMPTION(i915))
>+		return 0;
>+
>+	mutex_lock(&i915->drm.struct_mutex);
>+	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>+
>+	if (preempt_client_init(i915, &a))
>+		goto err_unlock;
>+	if (preempt_client_init(i915, &b))
>+		goto err_client_a;
>+	b.ctx->sched.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX);
>+
>+	for_each_engine(engine, i915, id) {
>+		struct i915_request *rq_a, *rq_b;
>+
>+		if (!intel_engine_has_preemption(engine))
>+			continue;
>+
>+		engine->execlists.preempt_hang.count = 0;
>+
>+		rq_a = igt_spinner_create_request(&a.spin,
>+						  a.ctx, engine,
>+						  MI_ARB_CHECK);
>+		if (IS_ERR(rq_a)) {
>+			err = PTR_ERR(rq_a);
>+			goto err_client_b;
>+		}
>+
>+		/* Low priority client, but unpreemptable! */
>+		rq_a->flags |= I915_REQUEST_NOPREEMPT;
>+
>+		i915_request_add(rq_a);
>+		if (!igt_wait_for_spinner(&a.spin, rq_a)) {
>+			pr_err("First client failed to start\n");
>+			goto err_wedged;
>+		}
>+
>+		rq_b = igt_spinner_create_request(&b.spin,
>+						  b.ctx, engine,
>+						  MI_ARB_CHECK);
>+		if (IS_ERR(rq_b)) {
>+			err = PTR_ERR(rq_b);
>+			goto err_client_b;
>+		}
>+
>+		i915_request_add(rq_b);
>+
>+		/* B is much more important than A! (But A is unpreemptable.) */
>+		GEM_BUG_ON(rq_prio(rq_b) <= rq_prio(rq_a));
>+
>+		/* Wait long enough for preemption and timeslicing */
>+		if (igt_wait_for_spinner(&b.spin, rq_b)) {
>+			pr_err("Second client started too early!\n");
>+			goto err_wedged;
>+		}
>+
>+		igt_spinner_end(&a.spin);
>+
>+		if (!igt_wait_for_spinner(&b.spin, rq_b)) {
>+			pr_err("Second client failed to start\n");
>+			goto err_wedged;
>+		}
>+
>+		igt_spinner_end(&b.spin);
>+
>+		if (engine->execlists.preempt_hang.count) {
>+			pr_err("Preemption recorded x%d; should have been suppressed!\n",
>+			       engine->execlists.preempt_hang.count);
>+			err = -EINVAL;
>+			goto err_wedged;
>+		}
>+
>+		if (igt_flush_test(i915, I915_WAIT_LOCKED))
>+			goto err_wedged;
>+	}
>+
>+	err = 0;
>+err_client_b:
>+	preempt_client_fini(&b);
>+err_client_a:
>+	preempt_client_fini(&a);
>+err_unlock:
>+	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>+	mutex_unlock(&i915->drm.struct_mutex);
>+	return err;
>+
>+err_wedged:
>+	igt_spinner_end(&b.spin);
>+	igt_spinner_end(&a.spin);
>+	intel_gt_set_wedged(&i915->gt);
>+	err = -EIO;
>+	goto err_client_b;
>+}
>+
> static int live_suppress_self_preempt(void *arg)
> {
> 	struct drm_i915_private *i915 = arg;
>@@ -531,6 +860,9 @@
> 	if (USES_GUC_SUBMISSION(i915))
> 		return 0; /* presume black blox */
> 
>+	if (intel_vgpu_active(i915))
>+		return 0; /* GVT forces single port & request submission */
>+
> 	mutex_lock(&i915->drm.struct_mutex);
> 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> 
>@@ -604,8 +936,6 @@
> err_client_a:
> 	preempt_client_fini(&a);
> err_unlock:
>-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>-		err = -EIO;
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> 	mutex_unlock(&i915->drm.struct_mutex);
> 	return err;
>@@ -613,7 +943,7 @@
> err_wedged:
> 	igt_spinner_end(&b.spin);
> 	igt_spinner_end(&a.spin);
>-	i915_gem_set_wedged(i915);
>+	intel_gt_set_wedged(&i915->gt);
> 	err = -EIO;
> 	goto err_client_b;
> }
>@@ -646,6 +976,10 @@
> 	i915_sw_fence_init(&rq->submit, dummy_notify);
> 	set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
> 
>+	spin_lock_init(&rq->lock);
>+	rq->fence.lock = &rq->lock;
>+	INIT_LIST_HEAD(&rq->fence.cb_list);
>+
> 	return rq;
> }
> 
>@@ -773,8 +1107,6 @@
> err_client_0:
> 	preempt_client_fini(&client[0]);
> err_unlock:
>-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>-		err = -EIO;
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> 	mutex_unlock(&i915->drm.struct_mutex);
> 	return err;
>@@ -782,7 +1114,7 @@
> err_wedged:
> 	for (i = 0; i < ARRAY_SIZE(client); i++)
> 		igt_spinner_end(&client[i].spin);
>-	i915_gem_set_wedged(i915);
>+	intel_gt_set_wedged(&i915->gt);
> 	err = -EIO;
> 	goto err_client_3;
> }
>@@ -921,8 +1253,6 @@
> err_client_hi:
> 	preempt_client_fini(&hi);
> err_unlock:
>-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>-		err = -EIO;
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> 	mutex_unlock(&i915->drm.struct_mutex);
> 	return err;
>@@ -930,7 +1260,7 @@
> err_wedged:
> 	igt_spinner_end(&hi.spin);
> 	igt_spinner_end(&lo.spin);
>-	i915_gem_set_wedged(i915);
>+	intel_gt_set_wedged(&i915->gt);
> 	err = -EIO;
> 	goto err_client_lo;
> }
>@@ -989,7 +1319,7 @@
> 		if (!igt_wait_for_spinner(&spin_lo, rq)) {
> 			GEM_TRACE("lo spinner failed to start\n");
> 			GEM_TRACE_DUMP();
>-			i915_gem_set_wedged(i915);
>+			intel_gt_set_wedged(&i915->gt);
> 			err = -EIO;
> 			goto err_ctx_lo;
> 		}
>@@ -1011,21 +1341,21 @@
> 						 HZ / 10)) {
> 			pr_err("Preemption did not occur within timeout!");
> 			GEM_TRACE_DUMP();
>-			i915_gem_set_wedged(i915);
>+			intel_gt_set_wedged(&i915->gt);
> 			err = -EIO;
> 			goto err_ctx_lo;
> 		}
> 
>-		set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>-		i915_reset_engine(engine, NULL);
>-		clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>+		set_bit(I915_RESET_ENGINE + id, &i915->gt.reset.flags);
>+		intel_engine_reset(engine, NULL);
>+		clear_bit(I915_RESET_ENGINE + id, &i915->gt.reset.flags);
> 
> 		engine->execlists.preempt_hang.inject_hang = false;
> 
> 		if (!igt_wait_for_spinner(&spin_hi, rq)) {
> 			GEM_TRACE("hi spinner failed to start\n");
> 			GEM_TRACE_DUMP();
>-			i915_gem_set_wedged(i915);
>+			intel_gt_set_wedged(&i915->gt);
> 			err = -EIO;
> 			goto err_ctx_lo;
> 		}
>@@ -1048,7 +1378,6 @@
> err_spin_hi:
> 	igt_spinner_fini(&spin_hi);
> err_unlock:
>-	igt_flush_test(i915, I915_WAIT_LOCKED);
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> 	mutex_unlock(&i915->drm.struct_mutex);
> 	return err;
>@@ -1406,7 +1735,7 @@
> 					  request[nc]->fence.context,
> 					  request[nc]->fence.seqno);
> 				GEM_TRACE_DUMP();
>-				i915_gem_set_wedged(i915);
>+				intel_gt_set_wedged(&i915->gt);
> 				break;
> 			}
> 		}
>@@ -1553,7 +1882,7 @@
> 				  request[n]->fence.context,
> 				  request[n]->fence.seqno);
> 			GEM_TRACE_DUMP();
>-			i915_gem_set_wedged(i915);
>+			intel_gt_set_wedged(&i915->gt);
> 			err = -EIO;
> 			goto out;
> 		}
>@@ -1812,9 +2141,11 @@
> {
> 	static const struct i915_subtest tests[] = {
> 		SUBTEST(live_sanitycheck),
>+		SUBTEST(live_timeslice_preempt),
> 		SUBTEST(live_busywait_preempt),
> 		SUBTEST(live_preempt),
> 		SUBTEST(live_late_preempt),
>+		SUBTEST(live_nopreempt),
> 		SUBTEST(live_suppress_self_preempt),
> 		SUBTEST(live_suppress_wait_preempt),
> 		SUBTEST(live_chain_preempt),
>@@ -1828,8 +2159,8 @@
> 	if (!HAS_EXECLISTS(i915))
> 		return 0;
> 
>-	if (i915_terminally_wedged(i915))
>+	if (intel_gt_is_wedged(&i915->gt))
> 		return 0;
> 
>-	return i915_subtests(tests, i915);
>+	return i915_live_subtests(tests, i915);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftest_reset.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftest_reset.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftest_reset.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftest_reset.c	2019-08-31 15:01:12.028736183 -0500
>@@ -9,26 +9,29 @@
> 
> static int igt_global_reset(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
> 	unsigned int reset_count;
>+	intel_wakeref_t wakeref;
> 	int err = 0;
> 
> 	/* Check that we can issue a global GPU reset */
> 
>-	igt_global_reset_lock(i915);
>+	igt_global_reset_lock(gt);
>+	wakeref = intel_runtime_pm_get(&gt->i915->runtime_pm);
> 
>-	reset_count = i915_reset_count(&i915->gpu_error);
>+	reset_count = i915_reset_count(&gt->i915->gpu_error);
> 
>-	i915_reset(i915, ALL_ENGINES, NULL);
>+	intel_gt_reset(gt, ALL_ENGINES, NULL);
> 
>-	if (i915_reset_count(&i915->gpu_error) == reset_count) {
>+	if (i915_reset_count(&gt->i915->gpu_error) == reset_count) {
> 		pr_err("No GPU reset recorded!\n");
> 		err = -EINVAL;
> 	}
> 
>-	igt_global_reset_unlock(i915);
>+	intel_runtime_pm_put(&gt->i915->runtime_pm, wakeref);
>+	igt_global_reset_unlock(gt);
> 
>-	if (i915_reset_failed(i915))
>+	if (intel_gt_is_wedged(gt))
> 		err = -EIO;
> 
> 	return err;
>@@ -36,64 +39,123 @@
> 
> static int igt_wedged_reset(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
> 	intel_wakeref_t wakeref;
> 
> 	/* Check that we can recover a wedged device with a GPU reset */
> 
>-	igt_global_reset_lock(i915);
>-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>+	igt_global_reset_lock(gt);
>+	wakeref = intel_runtime_pm_get(&gt->i915->runtime_pm);
> 
>-	i915_gem_set_wedged(i915);
>+	intel_gt_set_wedged(gt);
> 
>-	GEM_BUG_ON(!i915_reset_failed(i915));
>-	i915_reset(i915, ALL_ENGINES, NULL);
>+	GEM_BUG_ON(!intel_gt_is_wedged(gt));
>+	intel_gt_reset(gt, ALL_ENGINES, NULL);
> 
>-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>-	igt_global_reset_unlock(i915);
>+	intel_runtime_pm_put(&gt->i915->runtime_pm, wakeref);
>+	igt_global_reset_unlock(gt);
> 
>-	return i915_reset_failed(i915) ? -EIO : 0;
>+	return intel_gt_is_wedged(gt) ? -EIO : 0;
> }
> 
> static int igt_atomic_reset(void *arg)
> {
>-	struct drm_i915_private *i915 = arg;
>+	struct intel_gt *gt = arg;
> 	const typeof(*igt_atomic_phases) *p;
> 	int err = 0;
> 
> 	/* Check that the resets are usable from atomic context */
> 
>-	igt_global_reset_lock(i915);
>-	mutex_lock(&i915->drm.struct_mutex);
>+	intel_gt_pm_get(gt);
>+	igt_global_reset_lock(gt);
> 
> 	/* Flush any requests before we get started and check basics */
>-	if (!igt_force_reset(i915))
>+	if (!igt_force_reset(gt))
> 		goto unlock;
> 
> 	for (p = igt_atomic_phases; p->name; p++) {
> 		intel_engine_mask_t awake;
> 
>-		GEM_TRACE("intel_gpu_reset under %s\n", p->name);
>+		GEM_TRACE("__intel_gt_reset under %s\n", p->name);
> 
>-		awake = reset_prepare(i915);
>+		awake = reset_prepare(gt);
> 		p->critical_section_begin();
>-		reset_prepare(i915);
>-		err = intel_gpu_reset(i915, ALL_ENGINES);
>+
>+		err = __intel_gt_reset(gt, ALL_ENGINES);
>+
> 		p->critical_section_end();
>-		reset_finish(i915, awake);
>+		reset_finish(gt, awake);
> 
> 		if (err) {
>-			pr_err("intel_gpu_reset failed under %s\n", p->name);
>+			pr_err("__intel_gt_reset failed under %s\n", p->name);
> 			break;
> 		}
> 	}
> 
> 	/* As we poke around the guts, do a full reset before continuing. */
>-	igt_force_reset(i915);
>+	igt_force_reset(gt);
> 
> unlock:
>-	mutex_unlock(&i915->drm.struct_mutex);
>-	igt_global_reset_unlock(i915);
>+	igt_global_reset_unlock(gt);
>+	intel_gt_pm_put(gt);
>+
>+	return err;
>+}
>+
>+static int igt_atomic_engine_reset(void *arg)
>+{
>+	struct intel_gt *gt = arg;
>+	const typeof(*igt_atomic_phases) *p;
>+	struct intel_engine_cs *engine;
>+	enum intel_engine_id id;
>+	int err = 0;
>+
>+	/* Check that the resets are usable from atomic context */
>+
>+	if (!intel_has_reset_engine(gt->i915))
>+		return 0;
>+
>+	if (USES_GUC_SUBMISSION(gt->i915))
>+		return 0;
>+
>+	intel_gt_pm_get(gt);
>+	igt_global_reset_lock(gt);
>+
>+	/* Flush any requests before we get started and check basics */
>+	if (!igt_force_reset(gt))
>+		goto out_unlock;
>+
>+	for_each_engine(engine, gt->i915, id) {
>+		tasklet_disable_nosync(&engine->execlists.tasklet);
>+		intel_engine_pm_get(engine);
>+
>+		for (p = igt_atomic_phases; p->name; p++) {
>+			GEM_TRACE("intel_engine_reset(%s) under %s\n",
>+				  engine->name, p->name);
>+
>+			p->critical_section_begin();
>+			err = intel_engine_reset(engine, NULL);
>+			p->critical_section_end();
>+
>+			if (err) {
>+				pr_err("intel_engine_reset(%s) failed under %s\n",
>+				       engine->name, p->name);
>+				break;
>+			}
>+		}
>+
>+		intel_engine_pm_put(engine);
>+		tasklet_enable(&engine->execlists.tasklet);
>+		if (err)
>+			break;
>+	}
>+
>+	/* As we poke around the guts, do a full reset before continuing. */
>+	igt_force_reset(gt);
>+
>+out_unlock:
>+	igt_global_reset_unlock(gt);
>+	intel_gt_pm_put(gt);
> 
> 	return err;
> }
>@@ -104,18 +166,15 @@
> 		SUBTEST(igt_global_reset), /* attempt to recover GPU first */
> 		SUBTEST(igt_wedged_reset),
> 		SUBTEST(igt_atomic_reset),
>+		SUBTEST(igt_atomic_engine_reset),
> 	};
>-	intel_wakeref_t wakeref;
>-	int err = 0;
>+	struct intel_gt *gt = &i915->gt;
> 
>-	if (!intel_has_gpu_reset(i915))
>+	if (!intel_has_gpu_reset(gt->i915))
> 		return 0;
> 
>-	if (i915_terminally_wedged(i915))
>+	if (intel_gt_is_wedged(gt))
> 		return -EIO; /* we're long past hope of a successful reset */
> 
>-	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
>-		err = i915_subtests(tests, i915);
>-
>-	return err;
>+	return intel_gt_live_subtests(tests, gt);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftests/mock_timeline.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftests/mock_timeline.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftests/mock_timeline.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftests/mock_timeline.c	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,29 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2017-2018 Intel Corporation
>+ */
>+
>+#include "../intel_timeline.h"
>+
>+#include "mock_timeline.h"
>+
>+void mock_timeline_init(struct intel_timeline *timeline, u64 context)
>+{
>+	timeline->gt = NULL;
>+	timeline->fence_context = context;
>+
>+	mutex_init(&timeline->mutex);
>+
>+	INIT_ACTIVE_REQUEST(&timeline->last_request);
>+	INIT_LIST_HEAD(&timeline->requests);
>+
>+	i915_syncmap_init(&timeline->sync);
>+
>+	INIT_LIST_HEAD(&timeline->link);
>+}
>+
>+void mock_timeline_fini(struct intel_timeline *timeline)
>+{
>+	i915_syncmap_free(&timeline->sync);
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftests/mock_timeline.h	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2017-2018 Intel Corporation
>+ */
>+
>+#ifndef __MOCK_TIMELINE__
>+#define __MOCK_TIMELINE__
>+
>+struct intel_timeline;
>+
>+void mock_timeline_init(struct intel_timeline *timeline, u64 context);
>+void mock_timeline_fini(struct intel_timeline *timeline);
>+
>+#endif /* !__MOCK_TIMELINE__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftest_timeline.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftest_timeline.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftest_timeline.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftest_timeline.c	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,844 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2017-2018 Intel Corporation
>+ */
>+
>+#include <linux/prime_numbers.h>
>+
>+#include "gem/i915_gem_pm.h"
>+#include "intel_gt.h"
>+
>+#include "../selftests/i915_random.h"
>+#include "../i915_selftest.h"
>+
>+#include "../selftests/igt_flush_test.h"
>+#include "../selftests/mock_gem_device.h"
>+#include "selftests/mock_timeline.h"
>+
>+static struct page *hwsp_page(struct intel_timeline *tl)
>+{
>+	struct drm_i915_gem_object *obj = tl->hwsp_ggtt->obj;
>+
>+	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
>+	return sg_page(obj->mm.pages->sgl);
>+}
>+
>+static unsigned long hwsp_cacheline(struct intel_timeline *tl)
>+{
>+	unsigned long address = (unsigned long)page_address(hwsp_page(tl));
>+
>+	return (address + tl->hwsp_offset) / CACHELINE_BYTES;
>+}
>+
>+#define CACHELINES_PER_PAGE (PAGE_SIZE / CACHELINE_BYTES)
>+
>+struct mock_hwsp_freelist {
>+	struct drm_i915_private *i915;
>+	struct radix_tree_root cachelines;
>+	struct intel_timeline **history;
>+	unsigned long count, max;
>+	struct rnd_state prng;
>+};
>+
>+enum {
>+	SHUFFLE = BIT(0),
>+};
>+
>+static void __mock_hwsp_record(struct mock_hwsp_freelist *state,
>+			       unsigned int idx,
>+			       struct intel_timeline *tl)
>+{
>+	tl = xchg(&state->history[idx], tl);
>+	if (tl) {
>+		radix_tree_delete(&state->cachelines, hwsp_cacheline(tl));
>+		intel_timeline_put(tl);
>+	}
>+}
>+
>+static int __mock_hwsp_timeline(struct mock_hwsp_freelist *state,
>+				unsigned int count,
>+				unsigned int flags)
>+{
>+	struct intel_timeline *tl;
>+	unsigned int idx;
>+
>+	while (count--) {
>+		unsigned long cacheline;
>+		int err;
>+
>+		tl = intel_timeline_create(&state->i915->gt, NULL);
>+		if (IS_ERR(tl))
>+			return PTR_ERR(tl);
>+
>+		cacheline = hwsp_cacheline(tl);
>+		err = radix_tree_insert(&state->cachelines, cacheline, tl);
>+		if (err) {
>+			if (err == -EEXIST) {
>+				pr_err("HWSP cacheline %lu already used; duplicate allocation!\n",
>+				       cacheline);
>+			}
>+			intel_timeline_put(tl);
>+			return err;
>+		}
>+
>+		idx = state->count++ % state->max;
>+		__mock_hwsp_record(state, idx, tl);
>+	}
>+
>+	if (flags & SHUFFLE)
>+		i915_prandom_shuffle(state->history,
>+				     sizeof(*state->history),
>+				     min(state->count, state->max),
>+				     &state->prng);
>+
>+	count = i915_prandom_u32_max_state(min(state->count, state->max),
>+					   &state->prng);
>+	while (count--) {
>+		idx = --state->count % state->max;
>+		__mock_hwsp_record(state, idx, NULL);
>+	}
>+
>+	return 0;
>+}
>+
>+static int mock_hwsp_freelist(void *arg)
>+{
>+	struct mock_hwsp_freelist state;
>+	const struct {
>+		const char *name;
>+		unsigned int flags;
>+	} phases[] = {
>+		{ "linear", 0 },
>+		{ "shuffled", SHUFFLE },
>+		{ },
>+	}, *p;
>+	unsigned int na;
>+	int err = 0;
>+
>+	INIT_RADIX_TREE(&state.cachelines, GFP_KERNEL);
>+	state.prng = I915_RND_STATE_INITIALIZER(i915_selftest.random_seed);
>+
>+	state.i915 = mock_gem_device();
>+	if (!state.i915)
>+		return -ENOMEM;
>+
>+	/*
>+	 * Create a bunch of timelines and check that their HWSP do not overlap.
>+	 * Free some, and try again.
>+	 */
>+
>+	state.max = PAGE_SIZE / sizeof(*state.history);
>+	state.count = 0;
>+	state.history = kcalloc(state.max, sizeof(*state.history), GFP_KERNEL);
>+	if (!state.history) {
>+		err = -ENOMEM;
>+		goto err_put;
>+	}
>+
>+	mutex_lock(&state.i915->drm.struct_mutex);
>+	for (p = phases; p->name; p++) {
>+		pr_debug("%s(%s)\n", __func__, p->name);
>+		for_each_prime_number_from(na, 1, 2 * CACHELINES_PER_PAGE) {
>+			err = __mock_hwsp_timeline(&state, na, p->flags);
>+			if (err)
>+				goto out;
>+		}
>+	}
>+
>+out:
>+	for (na = 0; na < state.max; na++)
>+		__mock_hwsp_record(&state, na, NULL);
>+	mutex_unlock(&state.i915->drm.struct_mutex);
>+	kfree(state.history);
>+err_put:
>+	drm_dev_put(&state.i915->drm);
>+	return err;
>+}
>+
>+struct __igt_sync {
>+	const char *name;
>+	u32 seqno;
>+	bool expected;
>+	bool set;
>+};
>+
>+static int __igt_sync(struct intel_timeline *tl,
>+		      u64 ctx,
>+		      const struct __igt_sync *p,
>+		      const char *name)
>+{
>+	int ret;
>+
>+	if (__intel_timeline_sync_is_later(tl, ctx, p->seqno) != p->expected) {
>+		pr_err("%s: %s(ctx=%llu, seqno=%u) expected passed %s but failed\n",
>+		       name, p->name, ctx, p->seqno, yesno(p->expected));
>+		return -EINVAL;
>+	}
>+
>+	if (p->set) {
>+		ret = __intel_timeline_sync_set(tl, ctx, p->seqno);
>+		if (ret)
>+			return ret;
>+	}
>+
>+	return 0;
>+}
>+
>+static int igt_sync(void *arg)
>+{
>+	const struct __igt_sync pass[] = {
>+		{ "unset", 0, false, false },
>+		{ "new", 0, false, true },
>+		{ "0a", 0, true, true },
>+		{ "1a", 1, false, true },
>+		{ "1b", 1, true, true },
>+		{ "0b", 0, true, false },
>+		{ "2a", 2, false, true },
>+		{ "4", 4, false, true },
>+		{ "INT_MAX", INT_MAX, false, true },
>+		{ "INT_MAX-1", INT_MAX-1, true, false },
>+		{ "INT_MAX+1", (u32)INT_MAX+1, false, true },
>+		{ "INT_MAX", INT_MAX, true, false },
>+		{ "UINT_MAX", UINT_MAX, false, true },
>+		{ "wrap", 0, false, true },
>+		{ "unwrap", UINT_MAX, true, false },
>+		{},
>+	}, *p;
>+	struct intel_timeline tl;
>+	int order, offset;
>+	int ret = -ENODEV;
>+
>+	mock_timeline_init(&tl, 0);
>+	for (p = pass; p->name; p++) {
>+		for (order = 1; order < 64; order++) {
>+			for (offset = -1; offset <= (order > 1); offset++) {
>+				u64 ctx = BIT_ULL(order) + offset;
>+
>+				ret = __igt_sync(&tl, ctx, p, "1");
>+				if (ret)
>+					goto out;
>+			}
>+		}
>+	}
>+	mock_timeline_fini(&tl);
>+
>+	mock_timeline_init(&tl, 0);
>+	for (order = 1; order < 64; order++) {
>+		for (offset = -1; offset <= (order > 1); offset++) {
>+			u64 ctx = BIT_ULL(order) + offset;
>+
>+			for (p = pass; p->name; p++) {
>+				ret = __igt_sync(&tl, ctx, p, "2");
>+				if (ret)
>+					goto out;
>+			}
>+		}
>+	}
>+
>+out:
>+	mock_timeline_fini(&tl);
>+	return ret;
>+}
>+
>+static unsigned int random_engine(struct rnd_state *rnd)
>+{
>+	return i915_prandom_u32_max_state(I915_NUM_ENGINES, rnd);
>+}
>+
>+static int bench_sync(void *arg)
>+{
>+	struct rnd_state prng;
>+	struct intel_timeline tl;
>+	unsigned long end_time, count;
>+	u64 prng32_1M;
>+	ktime_t kt;
>+	int order, last_order;
>+
>+	mock_timeline_init(&tl, 0);
>+
>+	/* Lookups from cache are very fast and so the random number generation
>+	 * and the loop itself becomes a significant factor in the per-iteration
>+	 * timings. We try to compensate the results by measuring the overhead
>+	 * of the prng and subtract it from the reported results.
>+	 */
>+	prandom_seed_state(&prng, i915_selftest.random_seed);
>+	count = 0;
>+	kt = ktime_get();
>+	end_time = jiffies + HZ/10;
>+	do {
>+		u32 x;
>+
>+		/* Make sure the compiler doesn't optimise away the prng call */
>+		WRITE_ONCE(x, prandom_u32_state(&prng));
>+
>+		count++;
>+	} while (!time_after(jiffies, end_time));
>+	kt = ktime_sub(ktime_get(), kt);
>+	pr_debug("%s: %lu random evaluations, %lluns/prng\n",
>+		 __func__, count, (long long)div64_ul(ktime_to_ns(kt), count));
>+	prng32_1M = div64_ul(ktime_to_ns(kt) << 20, count);
>+
>+	/* Benchmark (only) setting random context ids */
>+	prandom_seed_state(&prng, i915_selftest.random_seed);
>+	count = 0;
>+	kt = ktime_get();
>+	end_time = jiffies + HZ/10;
>+	do {
>+		u64 id = i915_prandom_u64_state(&prng);
>+
>+		__intel_timeline_sync_set(&tl, id, 0);
>+		count++;
>+	} while (!time_after(jiffies, end_time));
>+	kt = ktime_sub(ktime_get(), kt);
>+	kt = ktime_sub_ns(kt, (count * prng32_1M * 2) >> 20);
>+	pr_info("%s: %lu random insertions, %lluns/insert\n",
>+		__func__, count, (long long)div64_ul(ktime_to_ns(kt), count));
>+
>+	/* Benchmark looking up the exact same context ids as we just set */
>+	prandom_seed_state(&prng, i915_selftest.random_seed);
>+	end_time = count;
>+	kt = ktime_get();
>+	while (end_time--) {
>+		u64 id = i915_prandom_u64_state(&prng);
>+
>+		if (!__intel_timeline_sync_is_later(&tl, id, 0)) {
>+			mock_timeline_fini(&tl);
>+			pr_err("Lookup of %llu failed\n", id);
>+			return -EINVAL;
>+		}
>+	}
>+	kt = ktime_sub(ktime_get(), kt);
>+	kt = ktime_sub_ns(kt, (count * prng32_1M * 2) >> 20);
>+	pr_info("%s: %lu random lookups, %lluns/lookup\n",
>+		__func__, count, (long long)div64_ul(ktime_to_ns(kt), count));
>+
>+	mock_timeline_fini(&tl);
>+	cond_resched();
>+
>+	mock_timeline_init(&tl, 0);
>+
>+	/* Benchmark setting the first N (in order) contexts */
>+	count = 0;
>+	kt = ktime_get();
>+	end_time = jiffies + HZ/10;
>+	do {
>+		__intel_timeline_sync_set(&tl, count++, 0);
>+	} while (!time_after(jiffies, end_time));
>+	kt = ktime_sub(ktime_get(), kt);
>+	pr_info("%s: %lu in-order insertions, %lluns/insert\n",
>+		__func__, count, (long long)div64_ul(ktime_to_ns(kt), count));
>+
>+	/* Benchmark looking up the exact same context ids as we just set */
>+	end_time = count;
>+	kt = ktime_get();
>+	while (end_time--) {
>+		if (!__intel_timeline_sync_is_later(&tl, end_time, 0)) {
>+			pr_err("Lookup of %lu failed\n", end_time);
>+			mock_timeline_fini(&tl);
>+			return -EINVAL;
>+		}
>+	}
>+	kt = ktime_sub(ktime_get(), kt);
>+	pr_info("%s: %lu in-order lookups, %lluns/lookup\n",
>+		__func__, count, (long long)div64_ul(ktime_to_ns(kt), count));
>+
>+	mock_timeline_fini(&tl);
>+	cond_resched();
>+
>+	mock_timeline_init(&tl, 0);
>+
>+	/* Benchmark searching for a random context id and maybe changing it */
>+	prandom_seed_state(&prng, i915_selftest.random_seed);
>+	count = 0;
>+	kt = ktime_get();
>+	end_time = jiffies + HZ/10;
>+	do {
>+		u32 id = random_engine(&prng);
>+		u32 seqno = prandom_u32_state(&prng);
>+
>+		if (!__intel_timeline_sync_is_later(&tl, id, seqno))
>+			__intel_timeline_sync_set(&tl, id, seqno);
>+
>+		count++;
>+	} while (!time_after(jiffies, end_time));
>+	kt = ktime_sub(ktime_get(), kt);
>+	kt = ktime_sub_ns(kt, (count * prng32_1M * 2) >> 20);
>+	pr_info("%s: %lu repeated insert/lookups, %lluns/op\n",
>+		__func__, count, (long long)div64_ul(ktime_to_ns(kt), count));
>+	mock_timeline_fini(&tl);
>+	cond_resched();
>+
>+	/* Benchmark searching for a known context id and changing the seqno */
>+	for (last_order = 1, order = 1; order < 32;
>+	     ({ int tmp = last_order; last_order = order; order += tmp; })) {
>+		unsigned int mask = BIT(order) - 1;
>+
>+		mock_timeline_init(&tl, 0);
>+
>+		count = 0;
>+		kt = ktime_get();
>+		end_time = jiffies + HZ/10;
>+		do {
>+			/* Without assuming too many details of the underlying
>+			 * implementation, try to identify its phase-changes
>+			 * (if any)!
>+			 */
>+			u64 id = (u64)(count & mask) << order;
>+
>+			__intel_timeline_sync_is_later(&tl, id, 0);
>+			__intel_timeline_sync_set(&tl, id, 0);
>+
>+			count++;
>+		} while (!time_after(jiffies, end_time));
>+		kt = ktime_sub(ktime_get(), kt);
>+		pr_info("%s: %lu cyclic/%d insert/lookups, %lluns/op\n",
>+			__func__, count, order,
>+			(long long)div64_ul(ktime_to_ns(kt), count));
>+		mock_timeline_fini(&tl);
>+		cond_resched();
>+	}
>+
>+	return 0;
>+}
>+
>+int intel_timeline_mock_selftests(void)
>+{
>+	static const struct i915_subtest tests[] = {
>+		SUBTEST(mock_hwsp_freelist),
>+		SUBTEST(igt_sync),
>+		SUBTEST(bench_sync),
>+	};
>+
>+	return i915_subtests(tests, NULL);
>+}
>+
>+static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
>+{
>+	u32 *cs;
>+
>+	cs = intel_ring_begin(rq, 4);
>+	if (IS_ERR(cs))
>+		return PTR_ERR(cs);
>+
>+	if (INTEL_GEN(rq->i915) >= 8) {
>+		*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>+		*cs++ = addr;
>+		*cs++ = 0;
>+		*cs++ = value;
>+	} else if (INTEL_GEN(rq->i915) >= 4) {
>+		*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>+		*cs++ = 0;
>+		*cs++ = addr;
>+		*cs++ = value;
>+	} else {
>+		*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
>+		*cs++ = addr;
>+		*cs++ = value;
>+		*cs++ = MI_NOOP;
>+	}
>+
>+	intel_ring_advance(rq, cs);
>+
>+	return 0;
>+}
>+
>+static struct i915_request *
>+tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value)
>+{
>+	struct i915_request *rq;
>+	int err;
>+
>+	lockdep_assert_held(&tl->gt->i915->drm.struct_mutex); /* lazy rq refs */
>+
>+	err = intel_timeline_pin(tl);
>+	if (err) {
>+		rq = ERR_PTR(err);
>+		goto out;
>+	}
>+
>+	rq = i915_request_create(engine->kernel_context);
>+	if (IS_ERR(rq))
>+		goto out_unpin;
>+
>+	err = emit_ggtt_store_dw(rq, tl->hwsp_offset, value);
>+	i915_request_add(rq);
>+	if (err)
>+		rq = ERR_PTR(err);
>+
>+out_unpin:
>+	intel_timeline_unpin(tl);
>+out:
>+	if (IS_ERR(rq))
>+		pr_err("Failed to write to timeline!\n");
>+	return rq;
>+}
>+
>+static struct intel_timeline *
>+checked_intel_timeline_create(struct drm_i915_private *i915)
>+{
>+	struct intel_timeline *tl;
>+
>+	tl = intel_timeline_create(&i915->gt, NULL);
>+	if (IS_ERR(tl))
>+		return tl;
>+
>+	if (*tl->hwsp_seqno != tl->seqno) {
>+		pr_err("Timeline created with incorrect breadcrumb, found %x, expected %x\n",
>+		       *tl->hwsp_seqno, tl->seqno);
>+		intel_timeline_put(tl);
>+		return ERR_PTR(-EINVAL);
>+	}
>+
>+	return tl;
>+}
>+
>+static int live_hwsp_engine(void *arg)
>+{
>+#define NUM_TIMELINES 4096
>+	struct drm_i915_private *i915 = arg;
>+	struct intel_timeline **timelines;
>+	struct intel_engine_cs *engine;
>+	enum intel_engine_id id;
>+	intel_wakeref_t wakeref;
>+	unsigned long count, n;
>+	int err = 0;
>+
>+	/*
>+	 * Create a bunch of timelines and check we can write
>+	 * independently to each of their breadcrumb slots.
>+	 */
>+
>+	timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES,
>+				   sizeof(*timelines),
>+				   GFP_KERNEL);
>+	if (!timelines)
>+		return -ENOMEM;
>+
>+	mutex_lock(&i915->drm.struct_mutex);
>+	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>+
>+	count = 0;
>+	for_each_engine(engine, i915, id) {
>+		if (!intel_engine_can_store_dword(engine))
>+			continue;
>+
>+		for (n = 0; n < NUM_TIMELINES; n++) {
>+			struct intel_timeline *tl;
>+			struct i915_request *rq;
>+
>+			tl = checked_intel_timeline_create(i915);
>+			if (IS_ERR(tl)) {
>+				err = PTR_ERR(tl);
>+				goto out;
>+			}
>+
>+			rq = tl_write(tl, engine, count);
>+			if (IS_ERR(rq)) {
>+				intel_timeline_put(tl);
>+				err = PTR_ERR(rq);
>+				goto out;
>+			}
>+
>+			timelines[count++] = tl;
>+		}
>+	}
>+
>+out:
>+	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>+		err = -EIO;
>+
>+	for (n = 0; n < count; n++) {
>+		struct intel_timeline *tl = timelines[n];
>+
>+		if (!err && *tl->hwsp_seqno != n) {
>+			pr_err("Invalid seqno stored in timeline %lu, found 0x%x\n",
>+			       n, *tl->hwsp_seqno);
>+			err = -EINVAL;
>+		}
>+		intel_timeline_put(tl);
>+	}
>+
>+	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>+	mutex_unlock(&i915->drm.struct_mutex);
>+
>+	kvfree(timelines);
>+
>+	return err;
>+#undef NUM_TIMELINES
>+}
>+
>+static int live_hwsp_alternate(void *arg)
>+{
>+#define NUM_TIMELINES 4096
>+	struct drm_i915_private *i915 = arg;
>+	struct intel_timeline **timelines;
>+	struct intel_engine_cs *engine;
>+	enum intel_engine_id id;
>+	intel_wakeref_t wakeref;
>+	unsigned long count, n;
>+	int err = 0;
>+
>+	/*
>+	 * Create a bunch of timelines and check we can write
>+	 * independently to each of their breadcrumb slots with adjacent
>+	 * engines.
>+	 */
>+
>+	timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES,
>+				   sizeof(*timelines),
>+				   GFP_KERNEL);
>+	if (!timelines)
>+		return -ENOMEM;
>+
>+	mutex_lock(&i915->drm.struct_mutex);
>+	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>+
>+	count = 0;
>+	for (n = 0; n < NUM_TIMELINES; n++) {
>+		for_each_engine(engine, i915, id) {
>+			struct intel_timeline *tl;
>+			struct i915_request *rq;
>+
>+			if (!intel_engine_can_store_dword(engine))
>+				continue;
>+
>+			tl = checked_intel_timeline_create(i915);
>+			if (IS_ERR(tl)) {
>+				err = PTR_ERR(tl);
>+				goto out;
>+			}
>+
>+			rq = tl_write(tl, engine, count);
>+			if (IS_ERR(rq)) {
>+				intel_timeline_put(tl);
>+				err = PTR_ERR(rq);
>+				goto out;
>+			}
>+
>+			timelines[count++] = tl;
>+		}
>+	}
>+
>+out:
>+	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>+		err = -EIO;
>+
>+	for (n = 0; n < count; n++) {
>+		struct intel_timeline *tl = timelines[n];
>+
>+		if (!err && *tl->hwsp_seqno != n) {
>+			pr_err("Invalid seqno stored in timeline %lu, found 0x%x\n",
>+			       n, *tl->hwsp_seqno);
>+			err = -EINVAL;
>+		}
>+		intel_timeline_put(tl);
>+	}
>+
>+	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>+	mutex_unlock(&i915->drm.struct_mutex);
>+
>+	kvfree(timelines);
>+
>+	return err;
>+#undef NUM_TIMELINES
>+}
>+
>+static int live_hwsp_wrap(void *arg)
>+{
>+	struct drm_i915_private *i915 = arg;
>+	struct intel_engine_cs *engine;
>+	struct intel_timeline *tl;
>+	enum intel_engine_id id;
>+	intel_wakeref_t wakeref;
>+	int err = 0;
>+
>+	/*
>+	 * Across a seqno wrap, we need to keep the old cacheline alive for
>+	 * foreign GPU references.
>+	 */
>+
>+	mutex_lock(&i915->drm.struct_mutex);
>+	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>+
>+	tl = intel_timeline_create(&i915->gt, NULL);
>+	if (IS_ERR(tl)) {
>+		err = PTR_ERR(tl);
>+		goto out_rpm;
>+	}
>+	if (!tl->has_initial_breadcrumb || !tl->hwsp_cacheline)
>+		goto out_free;
>+
>+	err = intel_timeline_pin(tl);
>+	if (err)
>+		goto out_free;
>+
>+	for_each_engine(engine, i915, id) {
>+		const u32 *hwsp_seqno[2];
>+		struct i915_request *rq;
>+		u32 seqno[2];
>+
>+		if (!intel_engine_can_store_dword(engine))
>+			continue;
>+
>+		rq = i915_request_create(engine->kernel_context);
>+		if (IS_ERR(rq)) {
>+			err = PTR_ERR(rq);
>+			goto out;
>+		}
>+
>+		tl->seqno = -4u;
>+
>+		err = intel_timeline_get_seqno(tl, rq, &seqno[0]);
>+		if (err) {
>+			i915_request_add(rq);
>+			goto out;
>+		}
>+		pr_debug("seqno[0]:%08x, hwsp_offset:%08x\n",
>+			 seqno[0], tl->hwsp_offset);
>+
>+		err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[0]);
>+		if (err) {
>+			i915_request_add(rq);
>+			goto out;
>+		}
>+		hwsp_seqno[0] = tl->hwsp_seqno;
>+
>+		err = intel_timeline_get_seqno(tl, rq, &seqno[1]);
>+		if (err) {
>+			i915_request_add(rq);
>+			goto out;
>+		}
>+		pr_debug("seqno[1]:%08x, hwsp_offset:%08x\n",
>+			 seqno[1], tl->hwsp_offset);
>+
>+		err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[1]);
>+		if (err) {
>+			i915_request_add(rq);
>+			goto out;
>+		}
>+		hwsp_seqno[1] = tl->hwsp_seqno;
>+
>+		/* With wrap should come a new hwsp */
>+		GEM_BUG_ON(seqno[1] >= seqno[0]);
>+		GEM_BUG_ON(hwsp_seqno[0] == hwsp_seqno[1]);
>+
>+		i915_request_add(rq);
>+
>+		if (i915_request_wait(rq, 0, HZ / 5) < 0) {
>+			pr_err("Wait for timeline writes timed out!\n");
>+			err = -EIO;
>+			goto out;
>+		}
>+
>+		if (*hwsp_seqno[0] != seqno[0] || *hwsp_seqno[1] != seqno[1]) {
>+			pr_err("Bad timeline values: found (%x, %x), expected (%x, %x)\n",
>+			       *hwsp_seqno[0], *hwsp_seqno[1],
>+			       seqno[0], seqno[1]);
>+			err = -EINVAL;
>+			goto out;
>+		}
>+
>+		i915_retire_requests(i915); /* recycle HWSP */
>+	}
>+
>+out:
>+	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>+		err = -EIO;
>+
>+	intel_timeline_unpin(tl);
>+out_free:
>+	intel_timeline_put(tl);
>+out_rpm:
>+	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>+	mutex_unlock(&i915->drm.struct_mutex);
>+
>+	return err;
>+}
>+
>+static int live_hwsp_recycle(void *arg)
>+{
>+	struct drm_i915_private *i915 = arg;
>+	struct intel_engine_cs *engine;
>+	enum intel_engine_id id;
>+	intel_wakeref_t wakeref;
>+	unsigned long count;
>+	int err = 0;
>+
>+	/*
>+	 * Check seqno writes into one timeline at a time. We expect to
>+	 * recycle the breadcrumb slot between iterations and neither
>+	 * want to confuse ourselves or the GPU.
>+	 */
>+
>+	mutex_lock(&i915->drm.struct_mutex);
>+	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>+
>+	count = 0;
>+	for_each_engine(engine, i915, id) {
>+		IGT_TIMEOUT(end_time);
>+
>+		if (!intel_engine_can_store_dword(engine))
>+			continue;
>+
>+		do {
>+			struct intel_timeline *tl;
>+			struct i915_request *rq;
>+
>+			tl = checked_intel_timeline_create(i915);
>+			if (IS_ERR(tl)) {
>+				err = PTR_ERR(tl);
>+				goto out;
>+			}
>+
>+			rq = tl_write(tl, engine, count);
>+			if (IS_ERR(rq)) {
>+				intel_timeline_put(tl);
>+				err = PTR_ERR(rq);
>+				goto out;
>+			}
>+
>+			if (i915_request_wait(rq, 0, HZ / 5) < 0) {
>+				pr_err("Wait for timeline writes timed out!\n");
>+				intel_timeline_put(tl);
>+				err = -EIO;
>+				goto out;
>+			}
>+
>+			if (*tl->hwsp_seqno != count) {
>+				pr_err("Invalid seqno stored in timeline %lu, found 0x%x\n",
>+				       count, *tl->hwsp_seqno);
>+				err = -EINVAL;
>+			}
>+
>+			intel_timeline_put(tl);
>+			count++;
>+
>+			if (err)
>+				goto out;
>+
>+			intel_timelines_park(i915); /* Encourage recycling! */
>+		} while (!__igt_timeout(end_time, NULL));
>+	}
>+
>+out:
>+	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>+	mutex_unlock(&i915->drm.struct_mutex);
>+
>+	return err;
>+}
>+
>+int intel_timeline_live_selftests(struct drm_i915_private *i915)
>+{
>+	static const struct i915_subtest tests[] = {
>+		SUBTEST(live_hwsp_recycle),
>+		SUBTEST(live_hwsp_engine),
>+		SUBTEST(live_hwsp_alternate),
>+		SUBTEST(live_hwsp_wrap),
>+	};
>+
>+	if (intel_gt_is_wedged(&i915->gt))
>+		return 0;
>+
>+	return i915_live_subtests(tests, i915);
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftest_workarounds.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftest_workarounds.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/selftest_workarounds.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/selftest_workarounds.c	2019-08-31 15:01:12.028736183 -0500
>@@ -5,13 +5,13 @@
>  */
> 
> #include "gem/i915_gem_pm.h"
>+#include "gt/intel_gt.h"
> #include "i915_selftest.h"
> #include "intel_reset.h"
> 
> #include "selftests/igt_flush_test.h"
> #include "selftests/igt_reset.h"
> #include "selftests/igt_spinner.h"
>-#include "selftests/igt_wedge_me.h"
> #include "selftests/mock_drm.h"
> 
> #include "gem/selftests/igt_gem_utils.h"
>@@ -24,11 +24,9 @@
> 	{ INTEL_GEMINILAKE, 0x731c }
> };
> 
>-#define REF_NAME_MAX (INTEL_ENGINE_CS_MAX_NAME + 8)
> struct wa_lists {
> 	struct i915_wa_list gt_wa_list;
> 	struct {
>-		char name[REF_NAME_MAX];
> 		struct i915_wa_list wa_list;
> 		struct i915_wa_list ctx_wa_list;
> 	} engine[I915_NUM_ENGINES];
>@@ -42,25 +40,20 @@
> 
> 	memset(lists, 0, sizeof(*lists));
> 
>-	wa_init_start(&lists->gt_wa_list, "GT_REF");
>+	wa_init_start(&lists->gt_wa_list, "GT_REF", "global");
> 	gt_init_workarounds(i915, &lists->gt_wa_list);
> 	wa_init_finish(&lists->gt_wa_list);
> 
> 	for_each_engine(engine, i915, id) {
> 		struct i915_wa_list *wal = &lists->engine[id].wa_list;
>-		char *name = lists->engine[id].name;
> 
>-		snprintf(name, REF_NAME_MAX, "%s_REF", engine->name);
>-
>-		wa_init_start(wal, name);
>+		wa_init_start(wal, "REF", engine->name);
> 		engine_init_workarounds(engine, wal);
> 		wa_init_finish(wal);
> 
>-		snprintf(name, REF_NAME_MAX, "%s_CTX_REF", engine->name);
>-
> 		__intel_engine_init_ctx_wa(engine,
> 					   &lists->engine[id].ctx_wa_list,
>-					   name);
>+					   "CTX_REF");
> 	}
> }
> 
>@@ -102,7 +95,7 @@
> 	i915_gem_object_flush_map(result);
> 	i915_gem_object_unpin_map(result);
> 
>-	vma = i915_vma_instance(result, &engine->i915->ggtt.vm, NULL);
>+	vma = i915_vma_instance(result, &engine->gt->ggtt->vm, NULL);
> 	if (IS_ERR(vma)) {
> 		err = PTR_ERR(vma);
> 		goto err_obj;
>@@ -184,7 +177,7 @@
> 			   struct intel_engine_cs *engine)
> {
> 	struct drm_i915_gem_object *results;
>-	struct igt_wedge_me wedge;
>+	struct intel_wedge_me wedge;
> 	u32 *vaddr;
> 	int err;
> 	int i;
>@@ -195,10 +188,10 @@
> 
> 	err = 0;
> 	i915_gem_object_lock(results);
>-	igt_wedge_on_timeout(&wedge, ctx->i915, HZ / 5) /* a safety net! */
>+	intel_wedge_on_timeout(&wedge, &ctx->i915->gt, HZ / 5) /* safety net! */
> 		err = i915_gem_object_set_to_cpu_domain(results, false);
> 	i915_gem_object_unlock(results);
>-	if (i915_terminally_wedged(ctx->i915))
>+	if (intel_gt_is_wedged(&ctx->i915->gt))
> 		err = -EIO;
> 	if (err)
> 		goto out_put;
>@@ -231,13 +224,13 @@
> 
> static int do_device_reset(struct intel_engine_cs *engine)
> {
>-	i915_reset(engine->i915, engine->mask, "live_workarounds");
>+	intel_gt_reset(engine->gt, engine->mask, "live_workarounds");
> 	return 0;
> }
> 
> static int do_engine_reset(struct intel_engine_cs *engine)
> {
>-	return i915_reset_engine(engine, "live_workarounds");
>+	return intel_engine_reset(engine, "live_workarounds");
> }
> 
> static int
>@@ -286,64 +279,67 @@
> 					const char *name)
> {
> 	struct drm_i915_private *i915 = engine->i915;
>-	struct i915_gem_context *ctx;
>+	struct i915_gem_context *ctx, *tmp;
> 	struct igt_spinner spin;
> 	intel_wakeref_t wakeref;
> 	int err;
> 
>-	pr_info("Checking %d whitelisted registers (RING_NONPRIV) [%s]\n",
>-		engine->whitelist.count, name);
>-
>-	err = igt_spinner_init(&spin, i915);
>-	if (err)
>-		return err;
>+	pr_info("Checking %d whitelisted registers on %s (RING_NONPRIV) [%s]\n",
>+		engine->whitelist.count, engine->name, name);
> 
> 	ctx = kernel_context(i915);
> 	if (IS_ERR(ctx))
> 		return PTR_ERR(ctx);
> 
>+	err = igt_spinner_init(&spin, i915);
>+	if (err)
>+		goto out_ctx;
>+
> 	err = check_whitelist(ctx, engine);
> 	if (err) {
> 		pr_err("Invalid whitelist *before* %s reset!\n", name);
>-		goto out;
>+		goto out_spin;
> 	}
> 
> 	err = switch_to_scratch_context(engine, &spin);
> 	if (err)
>-		goto out;
>+		goto out_spin;
> 
> 	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
> 		err = reset(engine);
> 
> 	igt_spinner_end(&spin);
>-	igt_spinner_fini(&spin);
> 
> 	if (err) {
> 		pr_err("%s reset failed\n", name);
>-		goto out;
>+		goto out_spin;
> 	}
> 
> 	err = check_whitelist(ctx, engine);
> 	if (err) {
> 		pr_err("Whitelist not preserved in context across %s reset!\n",
> 		       name);
>-		goto out;
>+		goto out_spin;
> 	}
> 
>+	tmp = kernel_context(i915);
>+	if (IS_ERR(tmp)) {
>+		err = PTR_ERR(tmp);
>+		goto out_spin;
>+	}
> 	kernel_context_close(ctx);
>-
>-	ctx = kernel_context(i915);
>-	if (IS_ERR(ctx))
>-		return PTR_ERR(ctx);
>+	ctx = tmp;
> 
> 	err = check_whitelist(ctx, engine);
> 	if (err) {
> 		pr_err("Invalid whitelist *after* %s reset in fresh context!\n",
> 		       name);
>-		goto out;
>+		goto out_spin;
> 	}
> 
>-out:
>+out_spin:
>+	igt_spinner_fini(&spin);
>+out_ctx:
> 	kernel_context_close(ctx);
> 	return err;
> }
>@@ -393,6 +389,10 @@
> 	enum intel_platform platform = INTEL_INFO(engine->i915)->platform;
> 	int i;
> 
>+	if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
>+	     RING_FORCE_TO_NONPRIV_ACCESS_WR)
>+		return true;
>+
> 	for (i = 0; i < ARRAY_SIZE(wo_registers); i++) {
> 		if (wo_registers[i].platform == platform &&
> 		    wo_registers[i].reg == reg)
>@@ -404,7 +404,8 @@
> 
> static bool ro_register(u32 reg)
> {
>-	if (reg & RING_FORCE_TO_NONPRIV_RD)
>+	if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
>+	     RING_FORCE_TO_NONPRIV_ACCESS_RD)
> 		return true;
> 
> 	return false;
>@@ -476,12 +477,12 @@
> 		u32 srm, lrm, rsvd;
> 		u32 expect;
> 		int idx;
>+		bool ro_reg;
> 
> 		if (wo_register(engine, reg))
> 			continue;
> 
>-		if (ro_register(reg))
>-			continue;
>+		ro_reg = ro_register(reg);
> 
> 		srm = MI_STORE_REGISTER_MEM;
> 		lrm = MI_LOAD_REGISTER_MEM;
>@@ -542,7 +543,7 @@
> 
> 		i915_gem_object_flush_map(batch->obj);
> 		i915_gem_object_unpin_map(batch->obj);
>-		i915_gem_chipset_flush(ctx->i915);
>+		intel_gt_chipset_flush(engine->gt);
> 
> 		rq = igt_request_alloc(ctx, engine);
> 		if (IS_ERR(rq)) {
>@@ -570,7 +571,7 @@
> 		if (i915_request_wait(rq, 0, HZ / 5) < 0) {
> 			pr_err("%s: Futzing %x timedout; cancelling test\n",
> 			       engine->name, reg);
>-			i915_gem_set_wedged(ctx->i915);
>+			intel_gt_set_wedged(&ctx->i915->gt);
> 			err = -EIO;
> 			goto out_batch;
> 		}
>@@ -582,24 +583,35 @@
> 		}
> 
> 		GEM_BUG_ON(values[ARRAY_SIZE(values) - 1] != 0xffffffff);
>-		rsvd = results[ARRAY_SIZE(values)]; /* detect write masking */
>-		if (!rsvd) {
>-			pr_err("%s: Unable to write to whitelisted register %x\n",
>-			       engine->name, reg);
>-			err = -EINVAL;
>-			goto out_unpin;
>+		if (!ro_reg) {
>+			/* detect write masking */
>+			rsvd = results[ARRAY_SIZE(values)];
>+			if (!rsvd) {
>+				pr_err("%s: Unable to write to whitelisted register %x\n",
>+				       engine->name, reg);
>+				err = -EINVAL;
>+				goto out_unpin;
>+			}
> 		}
> 
> 		expect = results[0];
> 		idx = 1;
> 		for (v = 0; v < ARRAY_SIZE(values); v++) {
>-			expect = reg_write(expect, values[v], rsvd);
>+			if (ro_reg)
>+				expect = results[0];
>+			else
>+				expect = reg_write(expect, values[v], rsvd);
>+
> 			if (results[idx] != expect)
> 				err++;
> 			idx++;
> 		}
> 		for (v = 0; v < ARRAY_SIZE(values); v++) {
>-			expect = reg_write(expect, ~values[v], rsvd);
>+			if (ro_reg)
>+				expect = results[0];
>+			else
>+				expect = reg_write(expect, ~values[v], rsvd);
>+
> 			if (results[idx] != expect)
> 				err++;
> 			idx++;
>@@ -608,15 +620,22 @@
> 			pr_err("%s: %d mismatch between values written to whitelisted register [%x], and values read back!\n",
> 			       engine->name, err, reg);
> 
>-			pr_info("%s: Whitelisted register: %x, original value %08x, rsvd %08x\n",
>-				engine->name, reg, results[0], rsvd);
>+			if (ro_reg)
>+				pr_info("%s: Whitelisted read-only register: %x, original value %08x\n",
>+					engine->name, reg, results[0]);
>+			else
>+				pr_info("%s: Whitelisted register: %x, original value %08x, rsvd %08x\n",
>+					engine->name, reg, results[0], rsvd);
> 
> 			expect = results[0];
> 			idx = 1;
> 			for (v = 0; v < ARRAY_SIZE(values); v++) {
> 				u32 w = values[v];
> 
>-				expect = reg_write(expect, w, rsvd);
>+				if (ro_reg)
>+					expect = results[0];
>+				else
>+					expect = reg_write(expect, w, rsvd);
> 				pr_info("Wrote %08x, read %08x, expect %08x\n",
> 					w, results[idx], expect);
> 				idx++;
>@@ -624,7 +643,10 @@
> 			for (v = 0; v < ARRAY_SIZE(values); v++) {
> 				u32 w = ~values[v];
> 
>-				expect = reg_write(expect, w, rsvd);
>+				if (ro_reg)
>+					expect = results[0];
>+				else
>+					expect = reg_write(expect, w, rsvd);
> 				pr_info("Wrote %08x, read %08x, expect %08x\n",
> 					w, results[idx], expect);
> 				idx++;
>@@ -707,7 +729,7 @@
> 	if (!engine || engine->whitelist.count == 0)
> 		return 0;
> 
>-	igt_global_reset_lock(i915);
>+	igt_global_reset_lock(&i915->gt);
> 
> 	if (intel_has_reset_engine(i915)) {
> 		err = check_whitelist_across_reset(engine,
>@@ -726,7 +748,7 @@
> 	}
> 
> out:
>-	igt_global_reset_unlock(i915);
>+	igt_global_reset_unlock(&i915->gt);
> 	return err;
> }
> 
>@@ -756,8 +778,8 @@
> 		u64 offset = results->node.start + sizeof(u32) * i;
> 		u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
> 
>-		/* Clear RD only and WR only flags */
>-		reg &= ~(RING_FORCE_TO_NONPRIV_RD | RING_FORCE_TO_NONPRIV_WR);
>+		/* Clear access permission field */
>+		reg &= ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;
> 
> 		*cs++ = srm;
> 		*cs++ = reg;
>@@ -806,7 +828,7 @@
> 	*cs++ = MI_BATCH_BUFFER_END;
> 
> 	i915_gem_object_flush_map(batch->obj);
>-	i915_gem_chipset_flush(ctx->i915);
>+	intel_gt_chipset_flush(engine->gt);
> 
> 	rq = igt_request_alloc(ctx, engine);
> 	if (IS_ERR(rq)) {
>@@ -927,7 +949,8 @@
> 	for (i = 0; i < engine->whitelist.count; i++) {
> 		const struct i915_wa *wa = &engine->whitelist.list[i];
> 
>-		if (i915_mmio_reg_offset(wa->reg) & RING_FORCE_TO_NONPRIV_RD)
>+		if (i915_mmio_reg_offset(wa->reg) &
>+		    RING_FORCE_TO_NONPRIV_ACCESS_RD)
> 			continue;
> 
> 		if (!fn(engine, a[i], b[i], wa->reg))
>@@ -1094,7 +1117,7 @@
> 
> 	pr_info("Verifying after GPU reset...\n");
> 
>-	igt_global_reset_lock(i915);
>+	igt_global_reset_lock(&i915->gt);
> 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> 
> 	reference_lists_init(i915, &lists);
>@@ -1103,7 +1126,7 @@
> 	if (!ok)
> 		goto out;
> 
>-	i915_reset(i915, ALL_ENGINES, "live_workarounds");
>+	intel_gt_reset(&i915->gt, ALL_ENGINES, "live_workarounds");
> 
> 	ok = verify_wa_lists(ctx, &lists, "after reset");
> 
>@@ -1111,7 +1134,7 @@
> 	kernel_context_close(ctx);
> 	reference_lists_fini(i915, &lists);
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>-	igt_global_reset_unlock(i915);
>+	igt_global_reset_unlock(&i915->gt);
> 
> 	return ok ? 0 : -ESRCH;
> }
>@@ -1136,7 +1159,7 @@
> 	if (IS_ERR(ctx))
> 		return PTR_ERR(ctx);
> 
>-	igt_global_reset_lock(i915);
>+	igt_global_reset_lock(&i915->gt);
> 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> 
> 	reference_lists_init(i915, &lists);
>@@ -1152,7 +1175,7 @@
> 			goto err;
> 		}
> 
>-		i915_reset_engine(engine, "live_workarounds");
>+		intel_engine_reset(engine, "live_workarounds");
> 
> 		ok = verify_wa_lists(ctx, &lists, "after idle reset");
> 		if (!ok) {
>@@ -1180,7 +1203,7 @@
> 			goto err;
> 		}
> 
>-		i915_reset_engine(engine, "live_workarounds");
>+		intel_engine_reset(engine, "live_workarounds");
> 
> 		igt_spinner_end(&spin);
> 		igt_spinner_fini(&spin);
>@@ -1195,7 +1218,7 @@
> err:
> 	reference_lists_fini(i915, &lists);
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>-	igt_global_reset_unlock(i915);
>+	igt_global_reset_unlock(&i915->gt);
> 	kernel_context_close(ctx);
> 
> 	igt_flush_test(i915, I915_WAIT_LOCKED);
>@@ -1214,7 +1237,7 @@
> 	};
> 	int err;
> 
>-	if (i915_terminally_wedged(i915))
>+	if (intel_gt_is_wedged(&i915->gt))
> 		return 0;
> 
> 	mutex_lock(&i915->drm.struct_mutex);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,203 @@
>+/*
>+ * Copyright Â© 2014-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include "gt/intel_gt.h"
>+#include "intel_guc_ads.h"
>+#include "intel_uc.h"
>+#include "i915_drv.h"
>+
>+/*
>+ * The Additional Data Struct (ADS) has pointers for different buffers used by
>+ * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
>+ * scheduling policies (guc_policies), a structure describing a collection of
>+ * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
>+ * its internal state for sleep.
>+ */
>+
>+static void guc_policy_init(struct guc_policy *policy)
>+{
>+	policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
>+	policy->preemption_time = POLICY_DEFAULT_PREEMPTION_TIME_US;
>+	policy->fault_time = POLICY_DEFAULT_FAULT_TIME_US;
>+	policy->policy_flags = 0;
>+}
>+
>+static void guc_policies_init(struct guc_policies *policies)
>+{
>+	struct guc_policy *policy;
>+	u32 p, i;
>+
>+	policies->dpc_promote_time = POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
>+	policies->max_num_work_items = POLICY_MAX_NUM_WI;
>+
>+	for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
>+		for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++) {
>+			policy = &policies->policy[p][i];
>+
>+			guc_policy_init(policy);
>+		}
>+	}
>+
>+	policies->is_valid = 1;
>+}
>+
>+static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
>+{
>+	memset(pool, 0, num * sizeof(*pool));
>+}
>+
>+/*
>+ * The first 80 dwords of the register state context, containing the
>+ * execlists and ppgtt registers.
>+ */
>+#define LR_HW_CONTEXT_SIZE	(80 * sizeof(u32))
>+
>+/* The ads obj includes the struct itself and buffers passed to GuC */
>+struct __guc_ads_blob {
>+	struct guc_ads ads;
>+	struct guc_policies policies;
>+	struct guc_mmio_reg_state reg_state;
>+	struct guc_gt_system_info system_info;
>+	struct guc_clients_info clients_info;
>+	struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
>+	u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
>+} __packed;
>+
>+static void __guc_ads_init(struct intel_guc *guc)
>+{
>+	struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
>+	struct __guc_ads_blob *blob = guc->ads_blob;
>+	const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
>+	u32 base;
>+	u8 engine_class;
>+
>+	/* GuC scheduling policies */
>+	guc_policies_init(&blob->policies);
>+
>+	/*
>+	 * GuC expects a per-engine-class context image and size
>+	 * (minus hwsp and ring context). The context image will be
>+	 * used to reinitialize engines after a reset. It must exist
>+	 * and be pinned in the GGTT, so that the address won't change after
>+	 * we have told GuC where to find it. The context size will be used
>+	 * to validate that the LRC base + size fall within allowed GGTT.
>+	 */
>+	for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
>+		if (engine_class == OTHER_CLASS)
>+			continue;
>+		/*
>+		 * TODO: Set context pointer to default state to allow
>+		 * GuC to re-init guilty contexts after internal reset.
>+		 */
>+		blob->ads.golden_context_lrca[engine_class] = 0;
>+		blob->ads.eng_state_size[engine_class] =
>+			intel_engine_context_size(dev_priv, engine_class) -
>+			skipped_size;
>+	}
>+
>+	/* System info */
>+	blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
>+	blob->system_info.rcs_enabled = 1;
>+	blob->system_info.bcs_enabled = 1;
>+
>+	blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv);
>+	blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
>+	blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
>+
>+	base = intel_guc_ggtt_offset(guc, guc->ads_vma);
>+
>+	/* Clients info  */
>+	guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
>+
>+	blob->clients_info.clients_num = 1;
>+	blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool);
>+	blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool);
>+
>+	/* ADS */
>+	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
>+	blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
>+	blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
>+	blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
>+	blob->ads.clients_info = base + ptr_offset(blob, clients_info);
>+
>+	i915_gem_object_flush_map(guc->ads_vma->obj);
>+}
>+
>+/**
>+ * intel_guc_ads_create() - allocates and initializes GuC ADS.
>+ * @guc: intel_guc struct
>+ *
>+ * GuC needs memory block (Additional Data Struct), where it will store
>+ * some data. Allocate and initialize such memory block for GuC use.
>+ */
>+int intel_guc_ads_create(struct intel_guc *guc)
>+{
>+	const u32 size = PAGE_ALIGN(sizeof(struct __guc_ads_blob));
>+	struct i915_vma *vma;
>+	void *blob;
>+	int ret;
>+
>+	GEM_BUG_ON(guc->ads_vma);
>+
>+	vma = intel_guc_allocate_vma(guc, size);
>+	if (IS_ERR(vma))
>+		return PTR_ERR(vma);
>+
>+	blob = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
>+	if (IS_ERR(blob)) {
>+		ret = PTR_ERR(blob);
>+		goto err_vma;
>+	}
>+
>+	guc->ads_vma = vma;
>+	guc->ads_blob = blob;
>+
>+	__guc_ads_init(guc);
>+
>+	return 0;
>+
>+err_vma:
>+	i915_vma_unpin_and_release(&guc->ads_vma, 0);
>+	return ret;
>+}
>+
>+void intel_guc_ads_destroy(struct intel_guc *guc)
>+{
>+	i915_vma_unpin_and_release(&guc->ads_vma, I915_VMA_RELEASE_MAP);
>+}
>+
>+/**
>+ * intel_guc_ads_reset() - prepares GuC Additional Data Struct for reuse
>+ * @guc: intel_guc struct
>+ *
>+ * GuC stores some data in ADS, which might be stale after a reset.
>+ * Reinitialize whole ADS in case any part of it was corrupted during
>+ * previous GuC run.
>+ */
>+void intel_guc_ads_reset(struct intel_guc *guc)
>+{
>+	if (!guc->ads_vma)
>+		return;
>+	__guc_ads_init(guc);
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,34 @@
>+/*
>+ * Copyright Â© 2014-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef _INTEL_GUC_ADS_H_
>+#define _INTEL_GUC_ADS_H_
>+
>+struct intel_guc;
>+
>+int intel_guc_ads_create(struct intel_guc *guc);
>+void intel_guc_ads_destroy(struct intel_guc *guc);
>+void intel_guc_ads_reset(struct intel_guc *guc);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc.c	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,633 @@
>+/*
>+ * Copyright Â© 2014-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include "gt/intel_gt.h"
>+#include "intel_guc.h"
>+#include "intel_guc_ads.h"
>+#include "intel_guc_submission.h"
>+#include "i915_drv.h"
>+
>+static void gen8_guc_raise_irq(struct intel_guc *guc)
>+{
>+	struct intel_gt *gt = guc_to_gt(guc);
>+
>+	intel_uncore_write(gt->uncore, GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
>+}
>+
>+static void gen11_guc_raise_irq(struct intel_guc *guc)
>+{
>+	struct intel_gt *gt = guc_to_gt(guc);
>+
>+	intel_uncore_write(gt->uncore, GEN11_GUC_HOST_INTERRUPT, 0);
>+}
>+
>+static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
>+{
>+	GEM_BUG_ON(!guc->send_regs.base);
>+	GEM_BUG_ON(!guc->send_regs.count);
>+	GEM_BUG_ON(i >= guc->send_regs.count);
>+
>+	return _MMIO(guc->send_regs.base + 4 * i);
>+}
>+
>+void intel_guc_init_send_regs(struct intel_guc *guc)
>+{
>+	struct intel_gt *gt = guc_to_gt(guc);
>+	enum forcewake_domains fw_domains = 0;
>+	unsigned int i;
>+
>+	if (INTEL_GEN(gt->i915) >= 11) {
>+		guc->send_regs.base =
>+				i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
>+		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
>+	} else {
>+		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
>+		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
>+		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
>+	}
>+
>+	for (i = 0; i < guc->send_regs.count; i++) {
>+		fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore,
>+					guc_send_reg(guc, i),
>+					FW_REG_READ | FW_REG_WRITE);
>+	}
>+	guc->send_regs.fw_domains = fw_domains;
>+}
>+
>+void intel_guc_init_early(struct intel_guc *guc)
>+{
>+	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>+
>+	intel_guc_fw_init_early(guc);
>+	intel_guc_ct_init_early(&guc->ct);
>+	intel_guc_log_init_early(&guc->log);
>+
>+	mutex_init(&guc->send_mutex);
>+	spin_lock_init(&guc->irq_lock);
>+	guc->send = intel_guc_send_nop;
>+	guc->handler = intel_guc_to_host_event_handler_nop;
>+	if (INTEL_GEN(i915) >= 11) {
>+		guc->notify = gen11_guc_raise_irq;
>+		guc->interrupts.reset = gen11_reset_guc_interrupts;
>+		guc->interrupts.enable = gen11_enable_guc_interrupts;
>+		guc->interrupts.disable = gen11_disable_guc_interrupts;
>+	} else {
>+		guc->notify = gen8_guc_raise_irq;
>+		guc->interrupts.reset = gen9_reset_guc_interrupts;
>+		guc->interrupts.enable = gen9_enable_guc_interrupts;
>+		guc->interrupts.disable = gen9_disable_guc_interrupts;
>+	}
>+}
>+
>+static int guc_shared_data_create(struct intel_guc *guc)
>+{
>+	struct i915_vma *vma;
>+	void *vaddr;
>+
>+	vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
>+	if (IS_ERR(vma))
>+		return PTR_ERR(vma);
>+
>+	vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
>+	if (IS_ERR(vaddr)) {
>+		i915_vma_unpin_and_release(&vma, 0);
>+		return PTR_ERR(vaddr);
>+	}
>+
>+	guc->shared_data = vma;
>+	guc->shared_data_vaddr = vaddr;
>+
>+	return 0;
>+}
>+
>+static void guc_shared_data_destroy(struct intel_guc *guc)
>+{
>+	i915_vma_unpin_and_release(&guc->shared_data, I915_VMA_RELEASE_MAP);
>+}
>+
>+static u32 guc_ctl_debug_flags(struct intel_guc *guc)
>+{
>+	u32 level = intel_guc_log_get_level(&guc->log);
>+	u32 flags = 0;
>+
>+	if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
>+		flags |= GUC_LOG_DISABLED;
>+	else
>+		flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
>+			 GUC_LOG_VERBOSITY_SHIFT;
>+
>+	return flags;
>+}
>+
>+static u32 guc_ctl_feature_flags(struct intel_guc *guc)
>+{
>+	u32 flags = 0;
>+
>+	if (!intel_uc_is_using_guc_submission(&guc_to_gt(guc)->uc))
>+		flags |= GUC_CTL_DISABLE_SCHEDULER;
>+
>+	return flags;
>+}
>+
>+static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
>+{
>+	u32 flags = 0;
>+
>+	if (intel_uc_is_using_guc_submission(&guc_to_gt(guc)->uc)) {
>+		u32 ctxnum, base;
>+
>+		base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
>+		ctxnum = GUC_MAX_STAGE_DESCRIPTORS / 16;
>+
>+		base >>= PAGE_SHIFT;
>+		flags |= (base << GUC_CTL_BASE_ADDR_SHIFT) |
>+			(ctxnum << GUC_CTL_CTXNUM_IN16_SHIFT);
>+	}
>+	return flags;
>+}
>+
>+static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
>+{
>+	u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT;
>+	u32 flags;
>+
>+	#if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0)
>+	#define UNIT SZ_1M
>+	#define FLAG GUC_LOG_ALLOC_IN_MEGABYTE
>+	#else
>+	#define UNIT SZ_4K
>+	#define FLAG 0
>+	#endif
>+
>+	BUILD_BUG_ON(!CRASH_BUFFER_SIZE);
>+	BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT));
>+	BUILD_BUG_ON(!DPC_BUFFER_SIZE);
>+	BUILD_BUG_ON(!IS_ALIGNED(DPC_BUFFER_SIZE, UNIT));
>+	BUILD_BUG_ON(!ISR_BUFFER_SIZE);
>+	BUILD_BUG_ON(!IS_ALIGNED(ISR_BUFFER_SIZE, UNIT));
>+
>+	BUILD_BUG_ON((CRASH_BUFFER_SIZE / UNIT - 1) >
>+			(GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT));
>+	BUILD_BUG_ON((DPC_BUFFER_SIZE / UNIT - 1) >
>+			(GUC_LOG_DPC_MASK >> GUC_LOG_DPC_SHIFT));
>+	BUILD_BUG_ON((ISR_BUFFER_SIZE / UNIT - 1) >
>+			(GUC_LOG_ISR_MASK >> GUC_LOG_ISR_SHIFT));
>+
>+	flags = GUC_LOG_VALID |
>+		GUC_LOG_NOTIFY_ON_HALF_FULL |
>+		FLAG |
>+		((CRASH_BUFFER_SIZE / UNIT - 1) << GUC_LOG_CRASH_SHIFT) |
>+		((DPC_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DPC_SHIFT) |
>+		((ISR_BUFFER_SIZE / UNIT - 1) << GUC_LOG_ISR_SHIFT) |
>+		(offset << GUC_LOG_BUF_ADDR_SHIFT);
>+
>+	#undef UNIT
>+	#undef FLAG
>+
>+	return flags;
>+}
>+
>+static u32 guc_ctl_ads_flags(struct intel_guc *guc)
>+{
>+	u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
>+	u32 flags = ads << GUC_ADS_ADDR_SHIFT;
>+
>+	return flags;
>+}
>+
>+/*
>+ * Initialise the GuC parameter block before starting the firmware
>+ * transfer. These parameters are read by the firmware on startup
>+ * and cannot be changed thereafter.
>+ */
>+static void guc_init_params(struct intel_guc *guc)
>+{
>+	u32 *params = guc->params;
>+	int i;
>+
>+	BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32));
>+
>+	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
>+	params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
>+	params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
>+	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
>+	params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
>+
>+	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
>+		DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
>+}
>+
>+/*
>+ * Initialise the GuC parameter block before starting the firmware
>+ * transfer. These parameters are read by the firmware on startup
>+ * and cannot be changed thereafter.
>+ */
>+void intel_guc_write_params(struct intel_guc *guc)
>+{
>+	struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
>+	int i;
>+
>+	/*
>+	 * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
>+	 * they are power context saved so it's ok to release forcewake
>+	 * when we are done here and take it again at xfer time.
>+	 */
>+	intel_uncore_forcewake_get(uncore, FORCEWAKE_BLITTER);
>+
>+	intel_uncore_write(uncore, SOFT_SCRATCH(0), 0);
>+
>+	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
>+		intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]);
>+
>+	intel_uncore_forcewake_put(uncore, FORCEWAKE_BLITTER);
>+}
>+
>+int intel_guc_init(struct intel_guc *guc)
>+{
>+	struct intel_gt *gt = guc_to_gt(guc);
>+	int ret;
>+
>+	ret = intel_uc_fw_init(&guc->fw);
>+	if (ret)
>+		goto err_fetch;
>+
>+	ret = guc_shared_data_create(guc);
>+	if (ret)
>+		goto err_fw;
>+	GEM_BUG_ON(!guc->shared_data);
>+
>+	ret = intel_guc_log_create(&guc->log);
>+	if (ret)
>+		goto err_shared;
>+
>+	ret = intel_guc_ads_create(guc);
>+	if (ret)
>+		goto err_log;
>+	GEM_BUG_ON(!guc->ads_vma);
>+
>+	ret = intel_guc_ct_init(&guc->ct);
>+	if (ret)
>+		goto err_ads;
>+
>+	if (intel_uc_is_using_guc_submission(&gt->uc)) {
>+		/*
>+		 * This is stuff we need to have available at fw load time
>+		 * if we are planning to enable submission later
>+		 */
>+		ret = intel_guc_submission_init(guc);
>+		if (ret)
>+			goto err_ct;
>+	}
>+
>+	/* now that everything is perma-pinned, initialize the parameters */
>+	guc_init_params(guc);
>+
>+	/* We need to notify the guc whenever we change the GGTT */
>+	i915_ggtt_enable_guc(gt->ggtt);
>+
>+	return 0;
>+
>+err_ct:
>+	intel_guc_ct_fini(&guc->ct);
>+err_ads:
>+	intel_guc_ads_destroy(guc);
>+err_log:
>+	intel_guc_log_destroy(&guc->log);
>+err_shared:
>+	guc_shared_data_destroy(guc);
>+err_fw:
>+	intel_uc_fw_fini(&guc->fw);
>+err_fetch:
>+	intel_uc_fw_cleanup_fetch(&guc->fw);
>+	return ret;
>+}
>+
>+void intel_guc_fini(struct intel_guc *guc)
>+{
>+	struct intel_gt *gt = guc_to_gt(guc);
>+
>+	i915_ggtt_disable_guc(gt->ggtt);
>+
>+	if (intel_uc_is_using_guc_submission(&gt->uc))
>+		intel_guc_submission_fini(guc);
>+
>+	intel_guc_ct_fini(&guc->ct);
>+
>+	intel_guc_ads_destroy(guc);
>+	intel_guc_log_destroy(&guc->log);
>+	guc_shared_data_destroy(guc);
>+	intel_uc_fw_fini(&guc->fw);
>+	intel_uc_fw_cleanup_fetch(&guc->fw);
>+}
>+
>+int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
>+		       u32 *response_buf, u32 response_buf_size)
>+{
>+	WARN(1, "Unexpected send: action=%#x\n", *action);
>+	return -ENODEV;
>+}
>+
>+void intel_guc_to_host_event_handler_nop(struct intel_guc *guc)
>+{
>+	WARN(1, "Unexpected event: no suitable handler\n");
>+}
>+
>+/*
>+ * This function implements the MMIO based host to GuC interface.
>+ */
>+int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
>+			u32 *response_buf, u32 response_buf_size)
>+{
>+	struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
>+	u32 status;
>+	int i;
>+	int ret;
>+
>+	GEM_BUG_ON(!len);
>+	GEM_BUG_ON(len > guc->send_regs.count);
>+
>+	/* We expect only action code */
>+	GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK);
>+
>+	/* If CT is available, we expect to use MMIO only during init/fini */
>+	GEM_BUG_ON(*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
>+		   *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
>+
>+	mutex_lock(&guc->send_mutex);
>+	intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);
>+
>+	for (i = 0; i < len; i++)
>+		intel_uncore_write(uncore, guc_send_reg(guc, i), action[i]);
>+
>+	intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1));
>+
>+	intel_guc_notify(guc);
>+
>+	/*
>+	 * No GuC command should ever take longer than 10ms.
>+	 * Fast commands should still complete in 10us.
>+	 */
>+	ret = __intel_wait_for_register_fw(uncore,
>+					   guc_send_reg(guc, 0),
>+					   INTEL_GUC_MSG_TYPE_MASK,
>+					   INTEL_GUC_MSG_TYPE_RESPONSE <<
>+					   INTEL_GUC_MSG_TYPE_SHIFT,
>+					   10, 10, &status);
>+	/* If GuC explicitly returned an error, convert it to -EIO */
>+	if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status))
>+		ret = -EIO;
>+
>+	if (ret) {
>+		DRM_ERROR("MMIO: GuC action %#x failed with error %d %#x\n",
>+			  action[0], ret, status);
>+		goto out;
>+	}
>+
>+	if (response_buf) {
>+		int count = min(response_buf_size, guc->send_regs.count - 1);
>+
>+		for (i = 0; i < count; i++)
>+			response_buf[i] = intel_uncore_read(uncore,
>+							    guc_send_reg(guc, i + 1));
>+	}
>+
>+	/* Use data from the GuC response as our return value */
>+	ret = INTEL_GUC_MSG_TO_DATA(status);
>+
>+out:
>+	intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains);
>+	mutex_unlock(&guc->send_mutex);
>+
>+	return ret;
>+}
>+
>+int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
>+				       const u32 *payload, u32 len)
>+{
>+	u32 msg;
>+
>+	if (unlikely(!len))
>+		return -EPROTO;
>+
>+	/* Make sure to handle only enabled messages */
>+	msg = payload[0] & guc->msg_enabled_mask;
>+
>+	if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
>+		   INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
>+		intel_guc_log_handle_flush_event(&guc->log);
>+
>+	return 0;
>+}
>+
>+int intel_guc_sample_forcewake(struct intel_guc *guc)
>+{
>+	struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
>+	u32 action[2];
>+
>+	action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
>+	/* WaRsDisableCoarsePowerGating:skl,cnl */
>+	if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
>+		action[1] = 0;
>+	else
>+		/* bit 0 and 1 are for Render and Media domain separately */
>+		action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
>+
>+	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>+}
>+
>+/**
>+ * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
>+ * @guc: intel_guc structure
>+ * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
>+ *
>+ * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
>+ * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
>+ * intel_huc_auth().
>+ *
>+ * Return:	non-zero code on error
>+ */
>+int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
>+{
>+	u32 action[] = {
>+		INTEL_GUC_ACTION_AUTHENTICATE_HUC,
>+		rsa_offset
>+	};
>+
>+	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>+}
>+
>+/**
>+ * intel_guc_suspend() - notify GuC entering suspend state
>+ * @guc:	the guc
>+ */
>+int intel_guc_suspend(struct intel_guc *guc)
>+{
>+	struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
>+	int ret;
>+	u32 status;
>+	u32 action[] = {
>+		INTEL_GUC_ACTION_ENTER_S_STATE,
>+		GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
>+	};
>+
>+	/*
>+	 * The ENTER_S_STATE action queues the save/restore operation in GuC FW
>+	 * and then returns, so waiting on the H2G is not enough to guarantee
>+	 * GuC is done. When all the processing is done, GuC writes
>+	 * INTEL_GUC_SLEEP_STATE_SUCCESS to scratch register 14, so we can poll
>+	 * on that. Note that GuC does not ensure that the value in the register
>+	 * is different from INTEL_GUC_SLEEP_STATE_SUCCESS while the action is
>+	 * in progress so we need to take care of that ourselves as well.
>+	 */
>+
>+	intel_uncore_write(uncore, SOFT_SCRATCH(14),
>+			   INTEL_GUC_SLEEP_STATE_INVALID_MASK);
>+
>+	ret = intel_guc_send(guc, action, ARRAY_SIZE(action));
>+	if (ret)
>+		return ret;
>+
>+	ret = __intel_wait_for_register(uncore, SOFT_SCRATCH(14),
>+					INTEL_GUC_SLEEP_STATE_INVALID_MASK,
>+					0, 0, 10, &status);
>+	if (ret)
>+		return ret;
>+
>+	if (status != INTEL_GUC_SLEEP_STATE_SUCCESS) {
>+		DRM_ERROR("GuC failed to change sleep state. "
>+			  "action=0x%x, err=%u\n",
>+			  action[0], status);
>+		return -EIO;
>+	}
>+
>+	return 0;
>+}
>+
>+/**
>+ * intel_guc_reset_engine() - ask GuC to reset an engine
>+ * @guc:	intel_guc structure
>+ * @engine:	engine to be reset
>+ */
>+int intel_guc_reset_engine(struct intel_guc *guc,
>+			   struct intel_engine_cs *engine)
>+{
>+	u32 data[7];
>+
>+	GEM_BUG_ON(!guc->execbuf_client);
>+
>+	data[0] = INTEL_GUC_ACTION_REQUEST_ENGINE_RESET;
>+	data[1] = engine->guc_id;
>+	data[2] = 0;
>+	data[3] = 0;
>+	data[4] = 0;
>+	data[5] = guc->execbuf_client->stage_id;
>+	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
>+
>+	return intel_guc_send(guc, data, ARRAY_SIZE(data));
>+}
>+
>+/**
>+ * intel_guc_resume() - notify GuC resuming from suspend state
>+ * @guc:	the guc
>+ */
>+int intel_guc_resume(struct intel_guc *guc)
>+{
>+	u32 action[] = {
>+		INTEL_GUC_ACTION_EXIT_S_STATE,
>+		GUC_POWER_D0,
>+	};
>+
>+	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>+}
>+
>+/**
>+ * DOC: GuC Address Space
>+ *
>+ * The layout of GuC address space is shown below:
>+ *
>+ * ::
>+ *
>+ *     +===========> +====================+ <== FFFF_FFFF
>+ *     ^             |      Reserved      |
>+ *     |             +====================+ <== GUC_GGTT_TOP
>+ *     |             |                    |
>+ *     |             |        DRAM        |
>+ *    GuC            |                    |
>+ *  Address    +===> +====================+ <== GuC ggtt_pin_bias
>+ *   Space     ^     |                    |
>+ *     |       |     |                    |
>+ *     |      GuC    |        GuC         |
>+ *     |     WOPCM   |       WOPCM        |
>+ *     |      Size   |                    |
>+ *     |       |     |                    |
>+ *     v       v     |                    |
>+ *     +=======+===> +====================+ <== 0000_0000
>+ *
>+ * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM
>+ * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
>+ * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
>+ */
>+
>+/**
>+ * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
>+ * @guc:	the guc
>+ * @size:	size of area to allocate (both virtual space and memory)
>+ *
>+ * This is a wrapper to create an object for use with the GuC. In order to
>+ * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
>+ * both some backing storage and a range inside the Global GTT. We must pin
>+ * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
>+ * range is reserved inside GuC.
>+ *
>+ * Return:	A i915_vma if successful, otherwise an ERR_PTR.
>+ */
>+struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
>+{
>+	struct intel_gt *gt = guc_to_gt(guc);
>+	struct drm_i915_gem_object *obj;
>+	struct i915_vma *vma;
>+	u64 flags;
>+	int ret;
>+
>+	obj = i915_gem_object_create_shmem(gt->i915, size);
>+	if (IS_ERR(obj))
>+		return ERR_CAST(obj);
>+
>+	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
>+	if (IS_ERR(vma))
>+		goto err;
>+
>+	flags = PIN_GLOBAL | PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
>+	ret = i915_vma_pin(vma, 0, 0, flags);
>+	if (ret) {
>+		vma = ERR_PTR(ret);
>+		goto err;
>+	}
>+
>+	return vma;
>+
>+err:
>+	i915_gem_object_put(obj);
>+	return vma;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,915 @@
>+/*
>+ * Copyright Â© 2016-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ */
>+
>+#include "i915_drv.h"
>+#include "intel_guc_ct.h"
>+
>+#ifdef CONFIG_DRM_I915_DEBUG_GUC
>+#define CT_DEBUG_DRIVER(...)	DRM_DEBUG_DRIVER(__VA_ARGS__)
>+#else
>+#define CT_DEBUG_DRIVER(...)	do { } while (0)
>+#endif
>+
>+struct ct_request {
>+	struct list_head link;
>+	u32 fence;
>+	u32 status;
>+	u32 response_len;
>+	u32 *response_buf;
>+};
>+
>+struct ct_incoming_request {
>+	struct list_head link;
>+	u32 msg[];
>+};
>+
>+enum { CTB_SEND = 0, CTB_RECV = 1 };
>+
>+enum { CTB_OWNER_HOST = 0 };
>+
>+static void ct_incoming_request_worker_func(struct work_struct *w);
>+
>+/**
>+ * intel_guc_ct_init_early - Initialize CT state without requiring device access
>+ * @ct: pointer to CT struct
>+ */
>+void intel_guc_ct_init_early(struct intel_guc_ct *ct)
>+{
>+	/* we're using static channel owners */
>+	ct->host_channel.owner = CTB_OWNER_HOST;
>+
>+	spin_lock_init(&ct->lock);
>+	INIT_LIST_HEAD(&ct->pending_requests);
>+	INIT_LIST_HEAD(&ct->incoming_requests);
>+	INIT_WORK(&ct->worker, ct_incoming_request_worker_func);
>+}
>+
>+static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
>+{
>+	return container_of(ct, struct intel_guc, ct);
>+}
>+
>+static inline const char *guc_ct_buffer_type_to_str(u32 type)
>+{
>+	switch (type) {
>+	case INTEL_GUC_CT_BUFFER_TYPE_SEND:
>+		return "SEND";
>+	case INTEL_GUC_CT_BUFFER_TYPE_RECV:
>+		return "RECV";
>+	default:
>+		return "<invalid>";
>+	}
>+}
>+
>+static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc,
>+				    u32 cmds_addr, u32 size, u32 owner)
>+{
>+	CT_DEBUG_DRIVER("CT: desc %p init addr=%#x size=%u owner=%u\n",
>+			desc, cmds_addr, size, owner);
>+	memset(desc, 0, sizeof(*desc));
>+	desc->addr = cmds_addr;
>+	desc->size = size;
>+	desc->owner = owner;
>+}
>+
>+static void guc_ct_buffer_desc_reset(struct guc_ct_buffer_desc *desc)
>+{
>+	CT_DEBUG_DRIVER("CT: desc %p reset head=%u tail=%u\n",
>+			desc, desc->head, desc->tail);
>+	desc->head = 0;
>+	desc->tail = 0;
>+	desc->is_in_error = 0;
>+}
>+
>+static int guc_action_register_ct_buffer(struct intel_guc *guc,
>+					 u32 desc_addr,
>+					 u32 type)
>+{
>+	u32 action[] = {
>+		INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER,
>+		desc_addr,
>+		sizeof(struct guc_ct_buffer_desc),
>+		type
>+	};
>+	int err;
>+
>+	/* Can't use generic send(), CT registration must go over MMIO */
>+	err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
>+	if (err)
>+		DRM_ERROR("CT: register %s buffer failed; err=%d\n",
>+			  guc_ct_buffer_type_to_str(type), err);
>+	return err;
>+}
>+
>+static int guc_action_deregister_ct_buffer(struct intel_guc *guc,
>+					   u32 owner,
>+					   u32 type)
>+{
>+	u32 action[] = {
>+		INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER,
>+		owner,
>+		type
>+	};
>+	int err;
>+
>+	/* Can't use generic send(), CT deregistration must go over MMIO */
>+	err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
>+	if (err)
>+		DRM_ERROR("CT: deregister %s buffer failed; owner=%d err=%d\n",
>+			  guc_ct_buffer_type_to_str(type), owner, err);
>+	return err;
>+}
>+
>+static int ctch_init(struct intel_guc *guc,
>+		     struct intel_guc_ct_channel *ctch)
>+{
>+	struct i915_vma *vma;
>+	void *blob;
>+	int err;
>+	int i;
>+
>+	GEM_BUG_ON(ctch->vma);
>+
>+	/* We allocate 1 page to hold both descriptors and both buffers.
>+	 *       ___________.....................
>+	 *      |desc (SEND)|                   :
>+	 *      |___________|                   PAGE/4
>+	 *      :___________....................:
>+	 *      |desc (RECV)|                   :
>+	 *      |___________|                   PAGE/4
>+	 *      :_______________________________:
>+	 *      |cmds (SEND)                    |
>+	 *      |                               PAGE/4
>+	 *      |_______________________________|
>+	 *      |cmds (RECV)                    |
>+	 *      |                               PAGE/4
>+	 *      |_______________________________|
>+	 *
>+	 * Each message can use a maximum of 32 dwords and we don't expect to
>+	 * have more than 1 in flight at any time, so we have enough space.
>+	 * Some logic further ahead will rely on the fact that there is only 1
>+	 * page and that it is always mapped, so if the size is changed the
>+	 * other code will need updating as well.
>+	 */
>+
>+	/* allocate vma */
>+	vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
>+	if (IS_ERR(vma)) {
>+		err = PTR_ERR(vma);
>+		goto err_out;
>+	}
>+	ctch->vma = vma;
>+
>+	/* map first page */
>+	blob = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
>+	if (IS_ERR(blob)) {
>+		err = PTR_ERR(blob);
>+		goto err_vma;
>+	}
>+	CT_DEBUG_DRIVER("CT: vma base=%#x\n",
>+			intel_guc_ggtt_offset(guc, ctch->vma));
>+
>+	/* store pointers to desc and cmds */
>+	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
>+		GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
>+		ctch->ctbs[i].desc = blob + PAGE_SIZE/4 * i;
>+		ctch->ctbs[i].cmds = blob + PAGE_SIZE/4 * i + PAGE_SIZE/2;
>+	}
>+
>+	return 0;
>+
>+err_vma:
>+	i915_vma_unpin_and_release(&ctch->vma, 0);
>+err_out:
>+	CT_DEBUG_DRIVER("CT: channel %d initialization failed; err=%d\n",
>+			ctch->owner, err);
>+	return err;
>+}
>+
>+static void ctch_fini(struct intel_guc *guc,
>+		      struct intel_guc_ct_channel *ctch)
>+{
>+	GEM_BUG_ON(ctch->enabled);
>+
>+	i915_vma_unpin_and_release(&ctch->vma, I915_VMA_RELEASE_MAP);
>+}
>+
>+static int ctch_enable(struct intel_guc *guc,
>+		       struct intel_guc_ct_channel *ctch)
>+{
>+	u32 base;
>+	int err;
>+	int i;
>+
>+	GEM_BUG_ON(!ctch->vma);
>+
>+	GEM_BUG_ON(ctch->enabled);
>+
>+	/* vma should be already allocated and map'ed */
>+	base = intel_guc_ggtt_offset(guc, ctch->vma);
>+
>+	/* (re)initialize descriptors
>+	 * cmds buffers are in the second half of the blob page
>+	 */
>+	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
>+		GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
>+		guc_ct_buffer_desc_init(ctch->ctbs[i].desc,
>+					base + PAGE_SIZE/4 * i + PAGE_SIZE/2,
>+					PAGE_SIZE/4,
>+					ctch->owner);
>+	}
>+
>+	/* register buffers, starting wirh RECV buffer
>+	 * descriptors are in first half of the blob
>+	 */
>+	err = guc_action_register_ct_buffer(guc,
>+					    base + PAGE_SIZE/4 * CTB_RECV,
>+					    INTEL_GUC_CT_BUFFER_TYPE_RECV);
>+	if (unlikely(err))
>+		goto err_out;
>+
>+	err = guc_action_register_ct_buffer(guc,
>+					    base + PAGE_SIZE/4 * CTB_SEND,
>+					    INTEL_GUC_CT_BUFFER_TYPE_SEND);
>+	if (unlikely(err))
>+		goto err_deregister;
>+
>+	ctch->enabled = true;
>+
>+	return 0;
>+
>+err_deregister:
>+	guc_action_deregister_ct_buffer(guc,
>+					ctch->owner,
>+					INTEL_GUC_CT_BUFFER_TYPE_RECV);
>+err_out:
>+	DRM_ERROR("CT: can't open channel %d; err=%d\n", ctch->owner, err);
>+	return err;
>+}
>+
>+static void ctch_disable(struct intel_guc *guc,
>+			 struct intel_guc_ct_channel *ctch)
>+{
>+	GEM_BUG_ON(!ctch->enabled);
>+
>+	ctch->enabled = false;
>+
>+	guc_action_deregister_ct_buffer(guc,
>+					ctch->owner,
>+					INTEL_GUC_CT_BUFFER_TYPE_SEND);
>+	guc_action_deregister_ct_buffer(guc,
>+					ctch->owner,
>+					INTEL_GUC_CT_BUFFER_TYPE_RECV);
>+}
>+
>+static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)
>+{
>+	/* For now it's trivial */
>+	return ++ctch->next_fence;
>+}
>+
>+/**
>+ * DOC: CTB Host to GuC request
>+ *
>+ * Format of the CTB Host to GuC request message is as follows::
>+ *
>+ *      +------------+---------+---------+---------+---------+
>+ *      |   msg[0]   |   [1]   |   [2]   |   ...   |  [n-1]  |
>+ *      +------------+---------+---------+---------+---------+
>+ *      |   MESSAGE  |       MESSAGE PAYLOAD                 |
>+ *      +   HEADER   +---------+---------+---------+---------+
>+ *      |            |    0    |    1    |   ...   |    n    |
>+ *      +============+=========+=========+=========+=========+
>+ *      |  len >= 1  |  FENCE  |     request specific data   |
>+ *      +------+-----+---------+---------+---------+---------+
>+ *
>+ *                   ^-----------------len-------------------^
>+ */
>+
>+static int ctb_write(struct intel_guc_ct_buffer *ctb,
>+		     const u32 *action,
>+		     u32 len /* in dwords */,
>+		     u32 fence,
>+		     bool want_response)
>+{
>+	struct guc_ct_buffer_desc *desc = ctb->desc;
>+	u32 head = desc->head / 4;	/* in dwords */
>+	u32 tail = desc->tail / 4;	/* in dwords */
>+	u32 size = desc->size / 4;	/* in dwords */
>+	u32 used;			/* in dwords */
>+	u32 header;
>+	u32 *cmds = ctb->cmds;
>+	unsigned int i;
>+
>+	GEM_BUG_ON(desc->size % 4);
>+	GEM_BUG_ON(desc->head % 4);
>+	GEM_BUG_ON(desc->tail % 4);
>+	GEM_BUG_ON(tail >= size);
>+
>+	/*
>+	 * tail == head condition indicates empty. GuC FW does not support
>+	 * using up the entire buffer to get tail == head meaning full.
>+	 */
>+	if (tail < head)
>+		used = (size - head) + tail;
>+	else
>+		used = tail - head;
>+
>+	/* make sure there is a space including extra dw for the fence */
>+	if (unlikely(used + len + 1 >= size))
>+		return -ENOSPC;
>+
>+	/*
>+	 * Write the message. The format is the following:
>+	 * DW0: header (including action code)
>+	 * DW1: fence
>+	 * DW2+: action data
>+	 */
>+	header = (len << GUC_CT_MSG_LEN_SHIFT) |
>+		 (GUC_CT_MSG_WRITE_FENCE_TO_DESC) |
>+		 (want_response ? GUC_CT_MSG_SEND_STATUS : 0) |
>+		 (action[0] << GUC_CT_MSG_ACTION_SHIFT);
>+
>+	CT_DEBUG_DRIVER("CT: writing %*ph %*ph %*ph\n",
>+			4, &header, 4, &fence,
>+			4 * (len - 1), &action[1]);
>+
>+	cmds[tail] = header;
>+	tail = (tail + 1) % size;
>+
>+	cmds[tail] = fence;
>+	tail = (tail + 1) % size;
>+
>+	for (i = 1; i < len; i++) {
>+		cmds[tail] = action[i];
>+		tail = (tail + 1) % size;
>+	}
>+
>+	/* now update desc tail (back in bytes) */
>+	desc->tail = tail * 4;
>+	GEM_BUG_ON(desc->tail > desc->size);
>+
>+	return 0;
>+}
>+
>+/**
>+ * wait_for_ctb_desc_update - Wait for the CT buffer descriptor update.
>+ * @desc:	buffer descriptor
>+ * @fence:	response fence
>+ * @status:	placeholder for status
>+ *
>+ * Guc will update CT buffer descriptor with new fence and status
>+ * after processing the command identified by the fence. Wait for
>+ * specified fence and then read from the descriptor status of the
>+ * command.
>+ *
>+ * Return:
>+ * *	0 response received (status is valid)
>+ * *	-ETIMEDOUT no response within hardcoded timeout
>+ * *	-EPROTO no response, CT buffer is in error
>+ */
>+static int wait_for_ctb_desc_update(struct guc_ct_buffer_desc *desc,
>+				    u32 fence,
>+				    u32 *status)
>+{
>+	int err;
>+
>+	/*
>+	 * Fast commands should complete in less than 10us, so sample quickly
>+	 * up to that length of time, then switch to a slower sleep-wait loop.
>+	 * No GuC command should ever take longer than 10ms.
>+	 */
>+#define done (READ_ONCE(desc->fence) == fence)
>+	err = wait_for_us(done, 10);
>+	if (err)
>+		err = wait_for(done, 10);
>+#undef done
>+
>+	if (unlikely(err)) {
>+		DRM_ERROR("CT: fence %u failed; reported fence=%u\n",
>+			  fence, desc->fence);
>+
>+		if (WARN_ON(desc->is_in_error)) {
>+			/* Something went wrong with the messaging, try to reset
>+			 * the buffer and hope for the best
>+			 */
>+			guc_ct_buffer_desc_reset(desc);
>+			err = -EPROTO;
>+		}
>+	}
>+
>+	*status = desc->status;
>+	return err;
>+}
>+
>+/**
>+ * wait_for_ct_request_update - Wait for CT request state update.
>+ * @req:	pointer to pending request
>+ * @status:	placeholder for status
>+ *
>+ * For each sent request, Guc shall send bac CT response message.
>+ * Our message handler will update status of tracked request once
>+ * response message with given fence is received. Wait here and
>+ * check for valid response status value.
>+ *
>+ * Return:
>+ * *	0 response received (status is valid)
>+ * *	-ETIMEDOUT no response within hardcoded timeout
>+ */
>+static int wait_for_ct_request_update(struct ct_request *req, u32 *status)
>+{
>+	int err;
>+
>+	/*
>+	 * Fast commands should complete in less than 10us, so sample quickly
>+	 * up to that length of time, then switch to a slower sleep-wait loop.
>+	 * No GuC command should ever take longer than 10ms.
>+	 */
>+#define done INTEL_GUC_MSG_IS_RESPONSE(READ_ONCE(req->status))
>+	err = wait_for_us(done, 10);
>+	if (err)
>+		err = wait_for(done, 10);
>+#undef done
>+
>+	if (unlikely(err))
>+		DRM_ERROR("CT: fence %u err %d\n", req->fence, err);
>+
>+	*status = req->status;
>+	return err;
>+}
>+
>+static int ctch_send(struct intel_guc_ct *ct,
>+		     struct intel_guc_ct_channel *ctch,
>+		     const u32 *action,
>+		     u32 len,
>+		     u32 *response_buf,
>+		     u32 response_buf_size,
>+		     u32 *status)
>+{
>+	struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_SEND];
>+	struct guc_ct_buffer_desc *desc = ctb->desc;
>+	struct ct_request request;
>+	unsigned long flags;
>+	u32 fence;
>+	int err;
>+
>+	GEM_BUG_ON(!ctch->enabled);
>+	GEM_BUG_ON(!len);
>+	GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
>+	GEM_BUG_ON(!response_buf && response_buf_size);
>+
>+	fence = ctch_get_next_fence(ctch);
>+	request.fence = fence;
>+	request.status = 0;
>+	request.response_len = response_buf_size;
>+	request.response_buf = response_buf;
>+
>+	spin_lock_irqsave(&ct->lock, flags);
>+	list_add_tail(&request.link, &ct->pending_requests);
>+	spin_unlock_irqrestore(&ct->lock, flags);
>+
>+	err = ctb_write(ctb, action, len, fence, !!response_buf);
>+	if (unlikely(err))
>+		goto unlink;
>+
>+	intel_guc_notify(ct_to_guc(ct));
>+
>+	if (response_buf)
>+		err = wait_for_ct_request_update(&request, status);
>+	else
>+		err = wait_for_ctb_desc_update(desc, fence, status);
>+	if (unlikely(err))
>+		goto unlink;
>+
>+	if (!INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(*status)) {
>+		err = -EIO;
>+		goto unlink;
>+	}
>+
>+	if (response_buf) {
>+		/* There shall be no data in the status */
>+		WARN_ON(INTEL_GUC_MSG_TO_DATA(request.status));
>+		/* Return actual response len */
>+		err = request.response_len;
>+	} else {
>+		/* There shall be no response payload */
>+		WARN_ON(request.response_len);
>+		/* Return data decoded from the status dword */
>+		err = INTEL_GUC_MSG_TO_DATA(*status);
>+	}
>+
>+unlink:
>+	spin_lock_irqsave(&ct->lock, flags);
>+	list_del(&request.link);
>+	spin_unlock_irqrestore(&ct->lock, flags);
>+
>+	return err;
>+}
>+
>+/*
>+ * Command Transport (CT) buffer based GuC send function.
>+ */
>+int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
>+		      u32 *response_buf, u32 response_buf_size)
>+{
>+	struct intel_guc_ct *ct = &guc->ct;
>+	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>+	u32 status = ~0; /* undefined */
>+	int ret;
>+
>+	mutex_lock(&guc->send_mutex);
>+
>+	ret = ctch_send(ct, ctch, action, len, response_buf, response_buf_size,
>+			&status);
>+	if (unlikely(ret < 0)) {
>+		DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n",
>+			  action[0], ret, status);
>+	} else if (unlikely(ret)) {
>+		CT_DEBUG_DRIVER("CT: send action %#x returned %d (%#x)\n",
>+				action[0], ret, ret);
>+	}
>+
>+	mutex_unlock(&guc->send_mutex);
>+	return ret;
>+}
>+
>+static inline unsigned int ct_header_get_len(u32 header)
>+{
>+	return (header >> GUC_CT_MSG_LEN_SHIFT) & GUC_CT_MSG_LEN_MASK;
>+}
>+
>+static inline unsigned int ct_header_get_action(u32 header)
>+{
>+	return (header >> GUC_CT_MSG_ACTION_SHIFT) & GUC_CT_MSG_ACTION_MASK;
>+}
>+
>+static inline bool ct_header_is_response(u32 header)
>+{
>+	return !!(header & GUC_CT_MSG_IS_RESPONSE);
>+}
>+
>+static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data)
>+{
>+	struct guc_ct_buffer_desc *desc = ctb->desc;
>+	u32 head = desc->head / 4;	/* in dwords */
>+	u32 tail = desc->tail / 4;	/* in dwords */
>+	u32 size = desc->size / 4;	/* in dwords */
>+	u32 *cmds = ctb->cmds;
>+	s32 available;			/* in dwords */
>+	unsigned int len;
>+	unsigned int i;
>+
>+	GEM_BUG_ON(desc->size % 4);
>+	GEM_BUG_ON(desc->head % 4);
>+	GEM_BUG_ON(desc->tail % 4);
>+	GEM_BUG_ON(tail >= size);
>+	GEM_BUG_ON(head >= size);
>+
>+	/* tail == head condition indicates empty */
>+	available = tail - head;
>+	if (unlikely(available == 0))
>+		return -ENODATA;
>+
>+	/* beware of buffer wrap case */
>+	if (unlikely(available < 0))
>+		available += size;
>+	CT_DEBUG_DRIVER("CT: available %d (%u:%u)\n", available, head, tail);
>+	GEM_BUG_ON(available < 0);
>+
>+	data[0] = cmds[head];
>+	head = (head + 1) % size;
>+
>+	/* message len with header */
>+	len = ct_header_get_len(data[0]) + 1;
>+	if (unlikely(len > (u32)available)) {
>+		DRM_ERROR("CT: incomplete message %*ph %*ph %*ph\n",
>+			  4, data,
>+			  4 * (head + available - 1 > size ?
>+			       size - head : available - 1), &cmds[head],
>+			  4 * (head + available - 1 > size ?
>+			       available - 1 - size + head : 0), &cmds[0]);
>+		return -EPROTO;
>+	}
>+
>+	for (i = 1; i < len; i++) {
>+		data[i] = cmds[head];
>+		head = (head + 1) % size;
>+	}
>+	CT_DEBUG_DRIVER("CT: received %*ph\n", 4 * len, data);
>+
>+	desc->head = head * 4;
>+	return 0;
>+}
>+
>+/**
>+ * DOC: CTB GuC to Host response
>+ *
>+ * Format of the CTB GuC to Host response message is as follows::
>+ *
>+ *      +------------+---------+---------+---------+---------+---------+
>+ *      |   msg[0]   |   [1]   |   [2]   |   [3]   |   ...   |  [n-1]  |
>+ *      +------------+---------+---------+---------+---------+---------+
>+ *      |   MESSAGE  |       MESSAGE PAYLOAD                           |
>+ *      +   HEADER   +---------+---------+---------+---------+---------+
>+ *      |            |    0    |    1    |    2    |   ...   |    n    |
>+ *      +============+=========+=========+=========+=========+=========+
>+ *      |  len >= 2  |  FENCE  |  STATUS |   response specific data    |
>+ *      +------+-----+---------+---------+---------+---------+---------+
>+ *
>+ *                   ^-----------------------len-----------------------^
>+ */
>+
>+static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>+{
>+	u32 header = msg[0];
>+	u32 len = ct_header_get_len(header);
>+	u32 msglen = len + 1; /* total message length including header */
>+	u32 fence;
>+	u32 status;
>+	u32 datalen;
>+	struct ct_request *req;
>+	bool found = false;
>+
>+	GEM_BUG_ON(!ct_header_is_response(header));
>+	GEM_BUG_ON(!in_irq());
>+
>+	/* Response payload shall at least include fence and status */
>+	if (unlikely(len < 2)) {
>+		DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
>+		return -EPROTO;
>+	}
>+
>+	fence = msg[1];
>+	status = msg[2];
>+	datalen = len - 2;
>+
>+	/* Format of the status follows RESPONSE message */
>+	if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
>+		DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
>+		return -EPROTO;
>+	}
>+
>+	CT_DEBUG_DRIVER("CT: response fence %u status %#x\n", fence, status);
>+
>+	spin_lock(&ct->lock);
>+	list_for_each_entry(req, &ct->pending_requests, link) {
>+		if (unlikely(fence != req->fence)) {
>+			CT_DEBUG_DRIVER("CT: request %u awaits response\n",
>+					req->fence);
>+			continue;
>+		}
>+		if (unlikely(datalen > req->response_len)) {
>+			DRM_ERROR("CT: response %u too long %*ph\n",
>+				  req->fence, 4 * msglen, msg);
>+			datalen = 0;
>+		}
>+		if (datalen)
>+			memcpy(req->response_buf, msg + 3, 4 * datalen);
>+		req->response_len = datalen;
>+		WRITE_ONCE(req->status, status);
>+		found = true;
>+		break;
>+	}
>+	spin_unlock(&ct->lock);
>+
>+	if (!found)
>+		DRM_ERROR("CT: unsolicited response %*ph\n", 4 * msglen, msg);
>+	return 0;
>+}
>+
>+static void ct_process_request(struct intel_guc_ct *ct,
>+			       u32 action, u32 len, const u32 *payload)
>+{
>+	struct intel_guc *guc = ct_to_guc(ct);
>+	int ret;
>+
>+	CT_DEBUG_DRIVER("CT: request %x %*ph\n", action, 4 * len, payload);
>+
>+	switch (action) {
>+	case INTEL_GUC_ACTION_DEFAULT:
>+		ret = intel_guc_to_host_process_recv_msg(guc, payload, len);
>+		if (unlikely(ret))
>+			goto fail_unexpected;
>+		break;
>+
>+	default:
>+fail_unexpected:
>+		DRM_ERROR("CT: unexpected request %x %*ph\n",
>+			  action, 4 * len, payload);
>+		break;
>+	}
>+}
>+
>+static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
>+{
>+	unsigned long flags;
>+	struct ct_incoming_request *request;
>+	u32 header;
>+	u32 *payload;
>+	bool done;
>+
>+	spin_lock_irqsave(&ct->lock, flags);
>+	request = list_first_entry_or_null(&ct->incoming_requests,
>+					   struct ct_incoming_request, link);
>+	if (request)
>+		list_del(&request->link);
>+	done = !!list_empty(&ct->incoming_requests);
>+	spin_unlock_irqrestore(&ct->lock, flags);
>+
>+	if (!request)
>+		return true;
>+
>+	header = request->msg[0];
>+	payload = &request->msg[1];
>+	ct_process_request(ct,
>+			   ct_header_get_action(header),
>+			   ct_header_get_len(header),
>+			   payload);
>+
>+	kfree(request);
>+	return done;
>+}
>+
>+static void ct_incoming_request_worker_func(struct work_struct *w)
>+{
>+	struct intel_guc_ct *ct = container_of(w, struct intel_guc_ct, worker);
>+	bool done;
>+
>+	done = ct_process_incoming_requests(ct);
>+	if (!done)
>+		queue_work(system_unbound_wq, &ct->worker);
>+}
>+
>+/**
>+ * DOC: CTB GuC to Host request
>+ *
>+ * Format of the CTB GuC to Host request message is as follows::
>+ *
>+ *      +------------+---------+---------+---------+---------+---------+
>+ *      |   msg[0]   |   [1]   |   [2]   |   [3]   |   ...   |  [n-1]  |
>+ *      +------------+---------+---------+---------+---------+---------+
>+ *      |   MESSAGE  |       MESSAGE PAYLOAD                           |
>+ *      +   HEADER   +---------+---------+---------+---------+---------+
>+ *      |            |    0    |    1    |    2    |   ...   |    n    |
>+ *      +============+=========+=========+=========+=========+=========+
>+ *      |     len    |            request specific data                |
>+ *      +------+-----+---------+---------+---------+---------+---------+
>+ *
>+ *                   ^-----------------------len-----------------------^
>+ */
>+
>+static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
>+{
>+	u32 header = msg[0];
>+	u32 len = ct_header_get_len(header);
>+	u32 msglen = len + 1; /* total message length including header */
>+	struct ct_incoming_request *request;
>+	unsigned long flags;
>+
>+	GEM_BUG_ON(ct_header_is_response(header));
>+
>+	request = kmalloc(sizeof(*request) + 4 * msglen, GFP_ATOMIC);
>+	if (unlikely(!request)) {
>+		DRM_ERROR("CT: dropping request %*ph\n", 4 * msglen, msg);
>+		return 0; /* XXX: -ENOMEM ? */
>+	}
>+	memcpy(request->msg, msg, 4 * msglen);
>+
>+	spin_lock_irqsave(&ct->lock, flags);
>+	list_add_tail(&request->link, &ct->incoming_requests);
>+	spin_unlock_irqrestore(&ct->lock, flags);
>+
>+	queue_work(system_unbound_wq, &ct->worker);
>+	return 0;
>+}
>+
>+static void ct_process_host_channel(struct intel_guc_ct *ct)
>+{
>+	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>+	struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_RECV];
>+	u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */
>+	int err = 0;
>+
>+	if (!ctch->enabled)
>+		return;
>+
>+	do {
>+		err = ctb_read(ctb, msg);
>+		if (err)
>+			break;
>+
>+		if (ct_header_is_response(msg[0]))
>+			err = ct_handle_response(ct, msg);
>+		else
>+			err = ct_handle_request(ct, msg);
>+	} while (!err);
>+
>+	if (GEM_WARN_ON(err == -EPROTO)) {
>+		DRM_ERROR("CT: corrupted message detected!\n");
>+		ctb->desc->is_in_error = 1;
>+	}
>+}
>+
>+/*
>+ * When we're communicating with the GuC over CT, GuC uses events
>+ * to notify us about new messages being posted on the RECV buffer.
>+ */
>+void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
>+{
>+	struct intel_guc_ct *ct = &guc->ct;
>+
>+	ct_process_host_channel(ct);
>+}
>+
>+/**
>+ * intel_guc_ct_init - Init CT communication
>+ * @ct: pointer to CT struct
>+ *
>+ * Allocate memory required for communication via
>+ * the CT channel.
>+ *
>+ * Return: 0 on success, a negative errno code on failure.
>+ */
>+int intel_guc_ct_init(struct intel_guc_ct *ct)
>+{
>+	struct intel_guc *guc = ct_to_guc(ct);
>+	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>+	int err;
>+
>+	err = ctch_init(guc, ctch);
>+	if (unlikely(err)) {
>+		DRM_ERROR("CT: can't open channel %d; err=%d\n",
>+			  ctch->owner, err);
>+		return err;
>+	}
>+
>+	GEM_BUG_ON(!ctch->vma);
>+	return 0;
>+}
>+
>+/**
>+ * intel_guc_ct_fini - Fini CT communication
>+ * @ct: pointer to CT struct
>+ *
>+ * Deallocate memory required for communication via
>+ * the CT channel.
>+ */
>+void intel_guc_ct_fini(struct intel_guc_ct *ct)
>+{
>+	struct intel_guc *guc = ct_to_guc(ct);
>+	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>+
>+	ctch_fini(guc, ctch);
>+}
>+
>+/**
>+ * intel_guc_ct_enable - Enable buffer based command transport.
>+ * @ct: pointer to CT struct
>+ *
>+ * Return: 0 on success, a negative errno code on failure.
>+ */
>+int intel_guc_ct_enable(struct intel_guc_ct *ct)
>+{
>+	struct intel_guc *guc = ct_to_guc(ct);
>+	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>+
>+	if (ctch->enabled)
>+		return 0;
>+
>+	return ctch_enable(guc, ctch);
>+}
>+
>+/**
>+ * intel_guc_ct_disable - Disable buffer based command transport.
>+ * @ct: pointer to CT struct
>+ */
>+void intel_guc_ct_disable(struct intel_guc_ct *ct)
>+{
>+	struct intel_guc *guc = ct_to_guc(ct);
>+	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>+
>+	if (!ctch->enabled)
>+		return;
>+
>+	ctch_disable(guc, ctch);
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,111 @@
>+/*
>+ * Copyright Â© 2016-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ */
>+
>+#ifndef _INTEL_GUC_CT_H_
>+#define _INTEL_GUC_CT_H_
>+
>+#include <linux/spinlock.h>
>+#include <linux/workqueue.h>
>+
>+#include "intel_guc_fwif.h"
>+
>+struct i915_vma;
>+struct intel_guc;
>+
>+/**
>+ * DOC: Command Transport (CT).
>+ *
>+ * Buffer based command transport is a replacement for MMIO based mechanism.
>+ * It can be used to perform both host-2-guc and guc-to-host communication.
>+ */
>+
>+/** Represents single command transport buffer.
>+ *
>+ * A single command transport buffer consists of two parts, the header
>+ * record (command transport buffer descriptor) and the actual buffer which
>+ * holds the commands.
>+ *
>+ * @desc: pointer to the buffer descriptor
>+ * @cmds: pointer to the commands buffer
>+ */
>+struct intel_guc_ct_buffer {
>+	struct guc_ct_buffer_desc *desc;
>+	u32 *cmds;
>+};
>+
>+/** Represents pair of command transport buffers.
>+ *
>+ * Buffers go in pairs to allow bi-directional communication.
>+ * To simplify the code we place both of them in the same vma.
>+ * Buffers from the same pair must share unique owner id.
>+ *
>+ * @vma: pointer to the vma with pair of CT buffers
>+ * @ctbs: buffers for sending(0) and receiving(1) commands
>+ * @owner: unique identifier
>+ * @next_fence: fence to be used with next send command
>+ */
>+struct intel_guc_ct_channel {
>+	struct i915_vma *vma;
>+	struct intel_guc_ct_buffer ctbs[2];
>+	u32 owner;
>+	u32 next_fence;
>+	bool enabled;
>+};
>+
>+/** Holds all command transport channels.
>+ *
>+ * @host_channel: main channel used by the host
>+ */
>+struct intel_guc_ct {
>+	struct intel_guc_ct_channel host_channel;
>+	/* other channels are tbd */
>+
>+	/** @lock: protects pending requests list */
>+	spinlock_t lock;
>+
>+	/** @pending_requests: list of requests waiting for response */
>+	struct list_head pending_requests;
>+
>+	/** @incoming_requests: list of incoming requests */
>+	struct list_head incoming_requests;
>+
>+	/** @worker: worker for handling incoming requests */
>+	struct work_struct worker;
>+};
>+
>+void intel_guc_ct_init_early(struct intel_guc_ct *ct);
>+int intel_guc_ct_init(struct intel_guc_ct *ct);
>+void intel_guc_ct_fini(struct intel_guc_ct *ct);
>+int intel_guc_ct_enable(struct intel_guc_ct *ct);
>+void intel_guc_ct_disable(struct intel_guc_ct *ct);
>+
>+static inline void intel_guc_ct_stop(struct intel_guc_ct *ct)
>+{
>+	ct->host_channel.enabled = false;
>+}
>+
>+int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
>+		      u32 *response_buf, u32 response_buf_size);
>+void intel_guc_to_host_event_handler_ct(struct intel_guc *guc);
>+
>+#endif /* _INTEL_GUC_CT_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c	2019-08-31 15:01:12.029736183 -0500
>@@ -0,0 +1,181 @@
>+/*
>+ * Copyright Â© 2014 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ * Authors:
>+ *    Vinit Azad <vinit.azad@intel.com>
>+ *    Ben Widawsky <ben@bwidawsk.net>
>+ *    Dave Gordon <david.s.gordon@intel.com>
>+ *    Alex Dai <yu.dai@intel.com>
>+ */
>+
>+#include "gt/intel_gt.h"
>+#include "intel_guc_fw.h"
>+#include "i915_drv.h"
>+
>+/**
>+ * intel_guc_fw_init_early() - initializes GuC firmware struct
>+ * @guc: intel_guc struct
>+ *
>+ * On platforms with GuC selects firmware for uploading
>+ */
>+void intel_guc_fw_init_early(struct intel_guc *guc)
>+{
>+	intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, guc_to_gt(guc)->i915);
>+}
>+
>+static void guc_prepare_xfer(struct intel_uncore *uncore)
>+{
>+	u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
>+			 GUC_ENABLE_READ_CACHE_LOGIC |
>+			 GUC_ENABLE_MIA_CACHING |
>+			 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
>+			 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
>+			 GUC_ENABLE_MIA_CLOCK_GATING;
>+
>+	/* Must program this register before loading the ucode with DMA */
>+	intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
>+
>+	if (IS_GEN9_LP(uncore->i915))
>+		intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>+	else
>+		intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>+
>+	if (IS_GEN(uncore->i915, 9)) {
>+		/* DOP Clock Gating Enable for GuC clocks */
>+		intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
>+				 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
>+
>+		/* allows for 5us (in 10ns units) before GT can go to RC6 */
>+		intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
>+	}
>+}
>+
>+/* Copy RSA signature from the fw image to HW for verification */
>+static void guc_xfer_rsa(struct intel_uc_fw *guc_fw,
>+			 struct intel_uncore *uncore)
>+{
>+	u32 rsa[UOS_RSA_SCRATCH_COUNT];
>+	size_t copied;
>+	int i;
>+
>+	copied = intel_uc_fw_copy_rsa(guc_fw, rsa, sizeof(rsa));
>+	GEM_BUG_ON(copied < sizeof(rsa));
>+
>+	for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
>+		intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
>+}
>+
>+/*
>+ * Read the GuC status register (GUC_STATUS) and store it in the
>+ * specified location; then return a boolean indicating whether
>+ * the value matches either of two values representing completion
>+ * of the GuC boot process.
>+ *
>+ * This is used for polling the GuC status in a wait_for()
>+ * loop below.
>+ */
>+static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
>+{
>+	u32 val = intel_uncore_read(uncore, GUC_STATUS);
>+	u32 uk_val = val & GS_UKERNEL_MASK;
>+
>+	*status = val;
>+	return (uk_val == GS_UKERNEL_READY) ||
>+		((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
>+}
>+
>+static int guc_wait_ucode(struct intel_uncore *uncore)
>+{
>+	u32 status;
>+	int ret;
>+
>+	/*
>+	 * Wait for the GuC to start up.
>+	 * NB: Docs recommend not using the interrupt for completion.
>+	 * Measurements indicate this should take no more than 20ms, so a
>+	 * timeout here indicates that the GuC has failed and is unusable.
>+	 * (Higher levels of the driver may decide to reset the GuC and
>+	 * attempt the ucode load again if this happens.)
>+	 */
>+	ret = wait_for(guc_ready(uncore, &status), 100);
>+	DRM_DEBUG_DRIVER("GuC status %#x\n", status);
>+
>+	if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
>+		DRM_ERROR("GuC firmware signature verification failed\n");
>+		ret = -ENOEXEC;
>+	}
>+
>+	if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
>+		DRM_ERROR("GuC firmware exception. EIP: %#x\n",
>+			  intel_uncore_read(uncore, SOFT_SCRATCH(13)));
>+		ret = -ENXIO;
>+	}
>+
>+	return ret;
>+}
>+
>+/**
>+ * intel_guc_fw_upload() - load GuC uCode to device
>+ * @guc: intel_guc structure
>+ *
>+ * Called from intel_uc_init_hw() during driver load, resume from sleep and
>+ * after a GPU reset.
>+ *
>+ * The firmware image should have already been fetched into memory, so only
>+ * check that fetch succeeded, and then transfer the image to the h/w.
>+ *
>+ * Return:	non-zero code on error
>+ */
>+int intel_guc_fw_upload(struct intel_guc *guc)
>+{
>+	struct intel_gt *gt = guc_to_gt(guc);
>+	struct intel_uncore *uncore = gt->uncore;
>+	int ret;
>+
>+	guc_prepare_xfer(uncore);
>+
>+	/*
>+	 * Note that GuC needs the CSS header plus uKernel code to be copied
>+	 * by the DMA engine in one operation, whereas the RSA signature is
>+	 * loaded via MMIO.
>+	 */
>+	guc_xfer_rsa(&guc->fw, uncore);
>+
>+	/*
>+	 * Current uCode expects the code to be loaded at 8k; locations below
>+	 * this are used for the stack.
>+	 */
>+	ret = intel_uc_fw_upload(&guc->fw, gt, 0x2000, UOS_MOVE);
>+	if (ret)
>+		goto out;
>+
>+	ret = guc_wait_ucode(uncore);
>+	if (ret)
>+		goto out;
>+
>+	guc->fw.status = INTEL_UC_FIRMWARE_RUNNING;
>+	return 0;
>+
>+out:
>+	guc->fw.status = INTEL_UC_FIRMWARE_FAIL;
>+	return ret;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,33 @@
>+/*
>+ * Copyright Â© 2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef _INTEL_GUC_FW_H_
>+#define _INTEL_GUC_FW_H_
>+
>+struct intel_guc;
>+
>+void intel_guc_fw_init_early(struct intel_guc *guc);
>+int intel_guc_fw_upload(struct intel_guc *guc);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,621 @@
>+/*
>+ * Copyright Â© 2014 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ */
>+#ifndef _INTEL_GUC_FWIF_H
>+#define _INTEL_GUC_FWIF_H
>+
>+#include <linux/bits.h>
>+#include <linux/compiler.h>
>+#include <linux/types.h>
>+
>+#define GUC_CLIENT_PRIORITY_KMD_HIGH	0
>+#define GUC_CLIENT_PRIORITY_HIGH	1
>+#define GUC_CLIENT_PRIORITY_KMD_NORMAL	2
>+#define GUC_CLIENT_PRIORITY_NORMAL	3
>+#define GUC_CLIENT_PRIORITY_NUM		4
>+
>+#define GUC_MAX_STAGE_DESCRIPTORS	1024
>+#define	GUC_INVALID_STAGE_ID		GUC_MAX_STAGE_DESCRIPTORS
>+
>+#define GUC_RENDER_ENGINE		0
>+#define GUC_VIDEO_ENGINE		1
>+#define GUC_BLITTER_ENGINE		2
>+#define GUC_VIDEOENHANCE_ENGINE		3
>+#define GUC_VIDEO_ENGINE2		4
>+#define GUC_MAX_ENGINES_NUM		(GUC_VIDEO_ENGINE2 + 1)
>+
>+#define GUC_MAX_ENGINE_CLASSES		5
>+#define GUC_MAX_INSTANCES_PER_CLASS	16
>+
>+#define GUC_DOORBELL_INVALID		256
>+
>+#define GUC_DB_SIZE			(PAGE_SIZE)
>+#define GUC_WQ_SIZE			(PAGE_SIZE * 2)
>+
>+/* Work queue item header definitions */
>+#define WQ_STATUS_ACTIVE		1
>+#define WQ_STATUS_SUSPENDED		2
>+#define WQ_STATUS_CMD_ERROR		3
>+#define WQ_STATUS_ENGINE_ID_NOT_USED	4
>+#define WQ_STATUS_SUSPENDED_FROM_RESET	5
>+#define WQ_TYPE_SHIFT			0
>+#define   WQ_TYPE_BATCH_BUF		(0x1 << WQ_TYPE_SHIFT)
>+#define   WQ_TYPE_PSEUDO		(0x2 << WQ_TYPE_SHIFT)
>+#define   WQ_TYPE_INORDER		(0x3 << WQ_TYPE_SHIFT)
>+#define   WQ_TYPE_NOOP			(0x4 << WQ_TYPE_SHIFT)
>+#define WQ_TARGET_SHIFT			10
>+#define WQ_LEN_SHIFT			16
>+#define WQ_NO_WCFLUSH_WAIT		(1 << 27)
>+#define WQ_PRESENT_WORKLOAD		(1 << 28)
>+
>+#define WQ_RING_TAIL_SHIFT		20
>+#define WQ_RING_TAIL_MAX		0x7FF	/* 2^11 QWords */
>+#define WQ_RING_TAIL_MASK		(WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT)
>+
>+#define GUC_STAGE_DESC_ATTR_ACTIVE	BIT(0)
>+#define GUC_STAGE_DESC_ATTR_PENDING_DB	BIT(1)
>+#define GUC_STAGE_DESC_ATTR_KERNEL	BIT(2)
>+#define GUC_STAGE_DESC_ATTR_PREEMPT	BIT(3)
>+#define GUC_STAGE_DESC_ATTR_RESET	BIT(4)
>+#define GUC_STAGE_DESC_ATTR_WQLOCKED	BIT(5)
>+#define GUC_STAGE_DESC_ATTR_PCH		BIT(6)
>+#define GUC_STAGE_DESC_ATTR_TERMINATED	BIT(7)
>+
>+/* New GuC control data */
>+#define GUC_CTL_CTXINFO			0
>+#define   GUC_CTL_CTXNUM_IN16_SHIFT	0
>+#define   GUC_CTL_BASE_ADDR_SHIFT	12
>+
>+#define GUC_CTL_LOG_PARAMS		1
>+#define   GUC_LOG_VALID			(1 << 0)
>+#define   GUC_LOG_NOTIFY_ON_HALF_FULL	(1 << 1)
>+#define   GUC_LOG_ALLOC_IN_MEGABYTE	(1 << 3)
>+#define   GUC_LOG_CRASH_SHIFT		4
>+#define   GUC_LOG_CRASH_MASK		(0x3 << GUC_LOG_CRASH_SHIFT)
>+#define   GUC_LOG_DPC_SHIFT		6
>+#define   GUC_LOG_DPC_MASK	        (0x7 << GUC_LOG_DPC_SHIFT)
>+#define   GUC_LOG_ISR_SHIFT		9
>+#define   GUC_LOG_ISR_MASK	        (0x7 << GUC_LOG_ISR_SHIFT)
>+#define   GUC_LOG_BUF_ADDR_SHIFT	12
>+
>+#define GUC_CTL_WA			2
>+#define GUC_CTL_FEATURE			3
>+#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 14)
>+
>+#define GUC_CTL_DEBUG			4
>+#define   GUC_LOG_VERBOSITY_SHIFT	0
>+#define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
>+#define   GUC_LOG_VERBOSITY_MED		(1 << GUC_LOG_VERBOSITY_SHIFT)
>+#define   GUC_LOG_VERBOSITY_HIGH	(2 << GUC_LOG_VERBOSITY_SHIFT)
>+#define   GUC_LOG_VERBOSITY_ULTRA	(3 << GUC_LOG_VERBOSITY_SHIFT)
>+/* Verbosity range-check limits, without the shift */
>+#define	  GUC_LOG_VERBOSITY_MIN		0
>+#define	  GUC_LOG_VERBOSITY_MAX		3
>+#define	  GUC_LOG_VERBOSITY_MASK	0x0000000f
>+#define	  GUC_LOG_DESTINATION_MASK	(3 << 4)
>+#define   GUC_LOG_DISABLED		(1 << 6)
>+#define   GUC_PROFILE_ENABLED		(1 << 7)
>+
>+#define GUC_CTL_ADS			5
>+#define   GUC_ADS_ADDR_SHIFT		1
>+#define   GUC_ADS_ADDR_MASK		(0xFFFFF << GUC_ADS_ADDR_SHIFT)
>+
>+#define GUC_CTL_MAX_DWORDS		(SOFT_SCRATCH_COUNT - 2) /* [1..14] */
>+
>+/* Work item for submitting workloads into work queue of GuC. */
>+struct guc_wq_item {
>+	u32 header;
>+	u32 context_desc;
>+	u32 submit_element_info;
>+	u32 fence_id;
>+} __packed;
>+
>+struct guc_process_desc {
>+	u32 stage_id;
>+	u64 db_base_addr;
>+	u32 head;
>+	u32 tail;
>+	u32 error_offset;
>+	u64 wq_base_addr;
>+	u32 wq_size_bytes;
>+	u32 wq_status;
>+	u32 engine_presence;
>+	u32 priority;
>+	u32 reserved[30];
>+} __packed;
>+
>+/* engine id and context id is packed into guc_execlist_context.context_id*/
>+#define GUC_ELC_CTXID_OFFSET		0
>+#define GUC_ELC_ENGINE_OFFSET		29
>+
>+/* The execlist context including software and HW information */
>+struct guc_execlist_context {
>+	u32 context_desc;
>+	u32 context_id;
>+	u32 ring_status;
>+	u32 ring_lrca;
>+	u32 ring_begin;
>+	u32 ring_end;
>+	u32 ring_next_free_location;
>+	u32 ring_current_tail_pointer_value;
>+	u8 engine_state_submit_value;
>+	u8 engine_state_wait_value;
>+	u16 pagefault_count;
>+	u16 engine_submit_queue_count;
>+} __packed;
>+
>+/*
>+ * This structure describes a stage set arranged for a particular communication
>+ * between uKernel (GuC) and Driver (KMD). Technically, this is known as a
>+ * "GuC Context descriptor" in the specs, but we use the term "stage descriptor"
>+ * to avoid confusion with all the other things already named "context" in the
>+ * driver. A static pool of these descriptors are stored inside a GEM object
>+ * (stage_desc_pool) which is held for the entire lifetime of our interaction
>+ * with the GuC, being allocated before the GuC is loaded with its firmware.
>+ */
>+struct guc_stage_desc {
>+	u32 sched_common_area;
>+	u32 stage_id;
>+	u32 pas_id;
>+	u8 engines_used;
>+	u64 db_trigger_cpu;
>+	u32 db_trigger_uk;
>+	u64 db_trigger_phy;
>+	u16 db_id;
>+
>+	struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];
>+
>+	u8 attribute;
>+
>+	u32 priority;
>+
>+	u32 wq_sampled_tail_offset;
>+	u32 wq_total_submit_enqueues;
>+
>+	u32 process_desc;
>+	u32 wq_addr;
>+	u32 wq_size;
>+
>+	u32 engine_presence;
>+
>+	u8 engine_suspended;
>+
>+	u8 reserved0[3];
>+	u64 reserved1[1];
>+
>+	u64 desc_private;
>+} __packed;
>+
>+/**
>+ * DOC: CTB based communication
>+ *
>+ * The CTB (command transport buffer) communication between Host and GuC
>+ * is based on u32 data stream written to the shared buffer. One buffer can
>+ * be used to transmit data only in one direction (one-directional channel).
>+ *
>+ * Current status of the each buffer is stored in the buffer descriptor.
>+ * Buffer descriptor holds tail and head fields that represents active data
>+ * stream. The tail field is updated by the data producer (sender), and head
>+ * field is updated by the data consumer (receiver)::
>+ *
>+ *      +------------+
>+ *      | DESCRIPTOR |          +=================+============+========+
>+ *      +============+          |                 | MESSAGE(s) |        |
>+ *      | address    |--------->+=================+============+========+
>+ *      +------------+
>+ *      | head       |          ^-----head--------^
>+ *      +------------+
>+ *      | tail       |          ^---------tail-----------------^
>+ *      +------------+
>+ *      | size       |          ^---------------size--------------------^
>+ *      +------------+
>+ *
>+ * Each message in data stream starts with the single u32 treated as a header,
>+ * followed by optional set of u32 data that makes message specific payload::
>+ *
>+ *      +------------+---------+---------+---------+
>+ *      |         MESSAGE                          |
>+ *      +------------+---------+---------+---------+
>+ *      |   msg[0]   |   [1]   |   ...   |  [n-1]  |
>+ *      +------------+---------+---------+---------+
>+ *      |   MESSAGE  |       MESSAGE PAYLOAD       |
>+ *      +   HEADER   +---------+---------+---------+
>+ *      |            |    0    |   ...   |    n    |
>+ *      +======+=====+=========+=========+=========+
>+ *      | 31:16| code|         |         |         |
>+ *      +------+-----+         |         |         |
>+ *      |  15:5|flags|         |         |         |
>+ *      +------+-----+         |         |         |
>+ *      |   4:0|  len|         |         |         |
>+ *      +------+-----+---------+---------+---------+
>+ *
>+ *                   ^-------------len-------------^
>+ *
>+ * The message header consists of:
>+ *
>+ * - **len**, indicates length of the message payload (in u32)
>+ * - **code**, indicates message code
>+ * - **flags**, holds various bits to control message handling
>+ */
>+
>+/*
>+ * Describes single command transport buffer.
>+ * Used by both guc-master and clients.
>+ */
>+struct guc_ct_buffer_desc {
>+	u32 addr;		/* gfx address */
>+	u64 host_private;	/* host private data */
>+	u32 size;		/* size in bytes */
>+	u32 head;		/* offset updated by GuC*/
>+	u32 tail;		/* offset updated by owner */
>+	u32 is_in_error;	/* error indicator */
>+	u32 fence;		/* fence updated by GuC */
>+	u32 status;		/* status updated by GuC */
>+	u32 owner;		/* id of the channel owner */
>+	u32 owner_sub_id;	/* owner-defined field for extra tracking */
>+	u32 reserved[5];
>+} __packed;
>+
>+/* Type of command transport buffer */
>+#define INTEL_GUC_CT_BUFFER_TYPE_SEND	0x0u
>+#define INTEL_GUC_CT_BUFFER_TYPE_RECV	0x1u
>+
>+/*
>+ * Definition of the command transport message header (DW0)
>+ *
>+ * bit[4..0]	message len (in dwords)
>+ * bit[7..5]	reserved
>+ * bit[8]	response (G2H only)
>+ * bit[8]	write fence to desc (H2G only)
>+ * bit[9]	write status to H2G buff (H2G only)
>+ * bit[10]	send status back via G2H (H2G only)
>+ * bit[15..11]	reserved
>+ * bit[31..16]	action code
>+ */
>+#define GUC_CT_MSG_LEN_SHIFT			0
>+#define GUC_CT_MSG_LEN_MASK			0x1F
>+#define GUC_CT_MSG_IS_RESPONSE			(1 << 8)
>+#define GUC_CT_MSG_WRITE_FENCE_TO_DESC		(1 << 8)
>+#define GUC_CT_MSG_WRITE_STATUS_TO_BUFF		(1 << 9)
>+#define GUC_CT_MSG_SEND_STATUS			(1 << 10)
>+#define GUC_CT_MSG_ACTION_SHIFT			16
>+#define GUC_CT_MSG_ACTION_MASK			0xFFFF
>+
>+#define GUC_FORCEWAKE_RENDER	(1 << 0)
>+#define GUC_FORCEWAKE_MEDIA	(1 << 1)
>+
>+#define GUC_POWER_UNSPECIFIED	0
>+#define GUC_POWER_D0		1
>+#define GUC_POWER_D1		2
>+#define GUC_POWER_D2		3
>+#define GUC_POWER_D3		4
>+
>+/* Scheduling policy settings */
>+
>+/* Reset engine upon preempt failure */
>+#define POLICY_RESET_ENGINE		(1<<0)
>+/* Preempt to idle on quantum expiry */
>+#define POLICY_PREEMPT_TO_IDLE		(1<<1)
>+
>+#define POLICY_MAX_NUM_WI 15
>+#define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
>+#define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
>+#define POLICY_DEFAULT_PREEMPTION_TIME_US 500000
>+#define POLICY_DEFAULT_FAULT_TIME_US 250000
>+
>+struct guc_policy {
>+	/* Time for one workload to execute. (in micro seconds) */
>+	u32 execution_quantum;
>+	/* Time to wait for a preemption request to completed before issuing a
>+	 * reset. (in micro seconds). */
>+	u32 preemption_time;
>+	/* How much time to allow to run after the first fault is observed.
>+	 * Then preempt afterwards. (in micro seconds) */
>+	u32 fault_time;
>+	u32 policy_flags;
>+	u32 reserved[8];
>+} __packed;
>+
>+struct guc_policies {
>+	struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES];
>+	u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
>+	/* In micro seconds. How much time to allow before DPC processing is
>+	 * called back via interrupt (to prevent DPC queue drain starving).
>+	 * Typically 1000s of micro seconds (example only, not granularity). */
>+	u32 dpc_promote_time;
>+
>+	/* Must be set to take these new values. */
>+	u32 is_valid;
>+
>+	/* Max number of WIs to process per call. A large value may keep CS
>+	 * idle. */
>+	u32 max_num_work_items;
>+
>+	u32 reserved[4];
>+} __packed;
>+
>+/* GuC MMIO reg state struct */
>+
>+
>+#define GUC_REGSET_MAX_REGISTERS	64
>+#define GUC_S3_SAVE_SPACE_PAGES		10
>+
>+struct guc_mmio_reg {
>+	u32 offset;
>+	u32 value;
>+	u32 flags;
>+#define GUC_REGSET_MASKED		(1 << 0)
>+} __packed;
>+
>+struct guc_mmio_regset {
>+	struct guc_mmio_reg registers[GUC_REGSET_MAX_REGISTERS];
>+	u32 values_valid;
>+	u32 number_of_registers;
>+} __packed;
>+
>+/* GuC register sets */
>+struct guc_mmio_reg_state {
>+	struct guc_mmio_regset engine_reg[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>+	u32 reserved[98];
>+} __packed;
>+
>+/* HW info */
>+struct guc_gt_system_info {
>+	u32 slice_enabled;
>+	u32 rcs_enabled;
>+	u32 reserved0;
>+	u32 bcs_enabled;
>+	u32 vdbox_enable_mask;
>+	u32 vdbox_sfc_support_mask;
>+	u32 vebox_enable_mask;
>+	u32 reserved[9];
>+} __packed;
>+
>+/* Clients info */
>+struct guc_ct_pool_entry {
>+	struct guc_ct_buffer_desc desc;
>+	u32 reserved[7];
>+} __packed;
>+
>+#define GUC_CT_POOL_SIZE	2
>+
>+struct guc_clients_info {
>+	u32 clients_num;
>+	u32 reserved0[13];
>+	u32 ct_pool_addr;
>+	u32 ct_pool_count;
>+	u32 reserved[4];
>+} __packed;
>+
>+/* GuC Additional Data Struct */
>+struct guc_ads {
>+	u32 reg_state_addr;
>+	u32 reg_state_buffer;
>+	u32 scheduler_policies;
>+	u32 gt_system_info;
>+	u32 clients_info;
>+	u32 control_data;
>+	u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
>+	u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
>+	u32 reserved[16];
>+} __packed;
>+
>+/* GuC logging structures */
>+
>+enum guc_log_buffer_type {
>+	GUC_ISR_LOG_BUFFER,
>+	GUC_DPC_LOG_BUFFER,
>+	GUC_CRASH_DUMP_LOG_BUFFER,
>+	GUC_MAX_LOG_BUFFER
>+};
>+
>+/**
>+ * struct guc_log_buffer_state - GuC log buffer state
>+ *
>+ * Below state structure is used for coordination of retrieval of GuC firmware
>+ * logs. Separate state is maintained for each log buffer type.
>+ * read_ptr points to the location where i915 read last in log buffer and
>+ * is read only for GuC firmware. write_ptr is incremented by GuC with number
>+ * of bytes written for each log entry and is read only for i915.
>+ * When any type of log buffer becomes half full, GuC sends a flush interrupt.
>+ * GuC firmware expects that while it is writing to 2nd half of the buffer,
>+ * first half would get consumed by Host and then get a flush completed
>+ * acknowledgment from Host, so that it does not end up doing any overwrite
>+ * causing loss of logs. So when buffer gets half filled & i915 has requested
>+ * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr
>+ * to the value of write_ptr and raise the interrupt.
>+ * On receiving the interrupt i915 should read the buffer, clear flush_to_file
>+ * field and also update read_ptr with the value of sample_write_ptr, before
>+ * sending an acknowledgment to GuC. marker & version fields are for internal
>+ * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every
>+ * time GuC detects the log buffer overflow.
>+ */
>+struct guc_log_buffer_state {
>+	u32 marker[2];
>+	u32 read_ptr;
>+	u32 write_ptr;
>+	u32 size;
>+	u32 sampled_write_ptr;
>+	union {
>+		struct {
>+			u32 flush_to_file:1;
>+			u32 buffer_full_cnt:4;
>+			u32 reserved:27;
>+		};
>+		u32 flags;
>+	};
>+	u32 version;
>+} __packed;
>+
>+struct guc_ctx_report {
>+	u32 report_return_status;
>+	u32 reserved1[64];
>+	u32 affected_count;
>+	u32 reserved2[2];
>+} __packed;
>+
>+/* GuC Shared Context Data Struct */
>+struct guc_shared_ctx_data {
>+	u32 addr_of_last_preempted_data_low;
>+	u32 addr_of_last_preempted_data_high;
>+	u32 addr_of_last_preempted_data_high_tmp;
>+	u32 padding;
>+	u32 is_mapped_to_proxy;
>+	u32 proxy_ctx_id;
>+	u32 engine_reset_ctx_id;
>+	u32 media_reset_count;
>+	u32 reserved1[8];
>+	u32 uk_last_ctx_switch_reason;
>+	u32 was_reset;
>+	u32 lrca_gpu_addr;
>+	u64 execlist_ctx;
>+	u32 reserved2[66];
>+	struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
>+} __packed;
>+
>+/**
>+ * DOC: MMIO based communication
>+ *
>+ * The MMIO based communication between Host and GuC uses software scratch
>+ * registers, where first register holds data treated as message header,
>+ * and other registers are used to hold message payload.
>+ *
>+ * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8,
>+ * but no H2G command takes more than 8 parameters and the GuC FW
>+ * itself uses an 8-element array to store the H2G message.
>+ *
>+ *      +-----------+---------+---------+---------+
>+ *      |  MMIO[0]  | MMIO[1] |   ...   | MMIO[n] |
>+ *      +-----------+---------+---------+---------+
>+ *      | header    |      optional payload       |
>+ *      +======+====+=========+=========+=========+
>+ *      | 31:28|type|         |         |         |
>+ *      +------+----+         |         |         |
>+ *      | 27:16|data|         |         |         |
>+ *      +------+----+         |         |         |
>+ *      |  15:0|code|         |         |         |
>+ *      +------+----+---------+---------+---------+
>+ *
>+ * The message header consists of:
>+ *
>+ * - **type**, indicates message type
>+ * - **code**, indicates message code, is specific for **type**
>+ * - **data**, indicates message data, optional, depends on **code**
>+ *
>+ * The following message **types** are supported:
>+ *
>+ * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code
>+ *   must be priovided in **code** field. Optional action specific parameters
>+ *   can be provided in remaining payload registers or **data** field.
>+ *
>+ * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request,
>+ *   action response status will be provided in **code** field. Optional
>+ *   response data can be returned in remaining payload registers or **data**
>+ *   field.
>+ */
>+
>+#define GUC_MAX_MMIO_MSG_LEN		8
>+
>+#define INTEL_GUC_MSG_TYPE_SHIFT	28
>+#define INTEL_GUC_MSG_TYPE_MASK		(0xF << INTEL_GUC_MSG_TYPE_SHIFT)
>+#define INTEL_GUC_MSG_DATA_SHIFT	16
>+#define INTEL_GUC_MSG_DATA_MASK		(0xFFF << INTEL_GUC_MSG_DATA_SHIFT)
>+#define INTEL_GUC_MSG_CODE_SHIFT	0
>+#define INTEL_GUC_MSG_CODE_MASK		(0xFFFF << INTEL_GUC_MSG_CODE_SHIFT)
>+
>+#define __INTEL_GUC_MSG_GET(T, m) \
>+	(((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT)
>+#define INTEL_GUC_MSG_TO_TYPE(m)	__INTEL_GUC_MSG_GET(TYPE, m)
>+#define INTEL_GUC_MSG_TO_DATA(m)	__INTEL_GUC_MSG_GET(DATA, m)
>+#define INTEL_GUC_MSG_TO_CODE(m)	__INTEL_GUC_MSG_GET(CODE, m)
>+
>+enum intel_guc_msg_type {
>+	INTEL_GUC_MSG_TYPE_REQUEST = 0x0,
>+	INTEL_GUC_MSG_TYPE_RESPONSE = 0xF,
>+};
>+
>+#define __INTEL_GUC_MSG_TYPE_IS(T, m) \
>+	(INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T)
>+#define INTEL_GUC_MSG_IS_REQUEST(m)	__INTEL_GUC_MSG_TYPE_IS(REQUEST, m)
>+#define INTEL_GUC_MSG_IS_RESPONSE(m)	__INTEL_GUC_MSG_TYPE_IS(RESPONSE, m)
>+
>+enum intel_guc_action {
>+	INTEL_GUC_ACTION_DEFAULT = 0x0,
>+	INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
>+	INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
>+	INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
>+	INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
>+	INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
>+	INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
>+	INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
>+	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>+	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
>+	INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005,
>+	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>+	INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
>+	INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
>+	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
>+	INTEL_GUC_ACTION_LIMIT
>+};
>+
>+enum intel_guc_preempt_options {
>+	INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
>+	INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
>+};
>+
>+enum intel_guc_report_status {
>+	INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0,
>+	INTEL_GUC_REPORT_STATUS_ACKED = 0x1,
>+	INTEL_GUC_REPORT_STATUS_ERROR = 0x2,
>+	INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
>+};
>+
>+enum intel_guc_sleep_state_status {
>+	INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
>+	INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
>+	INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
>+#define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
>+};
>+
>+#define GUC_LOG_CONTROL_LOGGING_ENABLED	(1 << 0)
>+#define GUC_LOG_CONTROL_VERBOSITY_SHIFT	4
>+#define GUC_LOG_CONTROL_VERBOSITY_MASK	(0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
>+#define GUC_LOG_CONTROL_DEFAULT_LOGGING	(1 << 8)
>+
>+enum intel_guc_response_status {
>+	INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
>+	INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
>+};
>+
>+#define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \
>+	 (typecheck(u32, (m)) && \
>+	  ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \
>+	  ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \
>+	   (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT)))
>+
>+/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
>+enum intel_guc_recv_message {
>+	INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
>+	INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)
>+};
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc.h	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,205 @@
>+/*
>+ * Copyright Â© 2014-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef _INTEL_GUC_H_
>+#define _INTEL_GUC_H_
>+
>+#include "intel_uncore.h"
>+#include "intel_guc_fw.h"
>+#include "intel_guc_fwif.h"
>+#include "intel_guc_ct.h"
>+#include "intel_guc_log.h"
>+#include "intel_guc_reg.h"
>+#include "intel_uc_fw.h"
>+#include "i915_utils.h"
>+#include "i915_vma.h"
>+
>+struct __guc_ads_blob;
>+
>+/*
>+ * Top level structure of GuC. It handles firmware loading and manages client
>+ * pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy
>+ * ExecList submission.
>+ */
>+struct intel_guc {
>+	struct intel_uc_fw fw;
>+	struct intel_guc_log log;
>+	struct intel_guc_ct ct;
>+
>+	/* Log snapshot if GuC errors during load */
>+	struct drm_i915_gem_object *load_err_log;
>+
>+	/* intel_guc_recv interrupt related state */
>+	spinlock_t irq_lock;
>+	unsigned int msg_enabled_mask;
>+
>+	struct {
>+		bool enabled;
>+		void (*reset)(struct intel_guc *guc);
>+		void (*enable)(struct intel_guc *guc);
>+		void (*disable)(struct intel_guc *guc);
>+	} interrupts;
>+
>+	struct i915_vma *ads_vma;
>+	struct __guc_ads_blob *ads_blob;
>+
>+	struct i915_vma *stage_desc_pool;
>+	void *stage_desc_pool_vaddr;
>+	struct ida stage_ids;
>+	struct i915_vma *shared_data;
>+	void *shared_data_vaddr;
>+
>+	struct intel_guc_client *execbuf_client;
>+
>+	DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
>+	/* Cyclic counter mod pagesize	*/
>+	u32 db_cacheline;
>+
>+	/* Control params for fw initialization */
>+	u32 params[GUC_CTL_MAX_DWORDS];
>+
>+	/* GuC's FW specific registers used in MMIO send */
>+	struct {
>+		u32 base;
>+		unsigned int count;
>+		enum forcewake_domains fw_domains;
>+	} send_regs;
>+
>+	/* Store msg (e.g. log flush) that we see while CTBs are disabled */
>+	u32 mmio_msg;
>+
>+	/* To serialize the intel_guc_send actions */
>+	struct mutex send_mutex;
>+
>+	/* GuC's FW specific send function */
>+	int (*send)(struct intel_guc *guc, const u32 *data, u32 len,
>+		    u32 *response_buf, u32 response_buf_size);
>+
>+	/* GuC's FW specific event handler function */
>+	void (*handler)(struct intel_guc *guc);
>+
>+	/* GuC's FW specific notify function */
>+	void (*notify)(struct intel_guc *guc);
>+};
>+
>+static
>+inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
>+{
>+	return guc->send(guc, action, len, NULL, 0);
>+}
>+
>+static inline int
>+intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
>+			   u32 *response_buf, u32 response_buf_size)
>+{
>+	return guc->send(guc, action, len, response_buf, response_buf_size);
>+}
>+
>+static inline void intel_guc_notify(struct intel_guc *guc)
>+{
>+	guc->notify(guc);
>+}
>+
>+static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
>+{
>+	guc->handler(guc);
>+}
>+
>+/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
>+#define GUC_GGTT_TOP	0xFEE00000
>+
>+/**
>+ * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
>+ * @guc: intel_guc structure.
>+ * @vma: i915 graphics virtual memory area.
>+ *
>+ * GuC does not allow any gfx GGTT address that falls into range
>+ * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
>+ * Currently, in order to exclude [0, ggtt.pin_bias) address space from
>+ * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
>+ * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
>+ *
>+ * Return: GGTT offset of the @vma.
>+ */
>+static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
>+					struct i915_vma *vma)
>+{
>+	u32 offset = i915_ggtt_offset(vma);
>+
>+	GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
>+	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
>+
>+	return offset;
>+}
>+
>+void intel_guc_init_early(struct intel_guc *guc);
>+void intel_guc_init_send_regs(struct intel_guc *guc);
>+void intel_guc_write_params(struct intel_guc *guc);
>+int intel_guc_init(struct intel_guc *guc);
>+void intel_guc_fini(struct intel_guc *guc);
>+int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
>+		       u32 *response_buf, u32 response_buf_size);
>+int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
>+			u32 *response_buf, u32 response_buf_size);
>+void intel_guc_to_host_event_handler(struct intel_guc *guc);
>+void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
>+int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
>+				       const u32 *payload, u32 len);
>+int intel_guc_sample_forcewake(struct intel_guc *guc);
>+int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
>+int intel_guc_suspend(struct intel_guc *guc);
>+int intel_guc_resume(struct intel_guc *guc);
>+struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
>+
>+static inline bool intel_guc_is_running(struct intel_guc *guc)
>+{
>+	return intel_uc_fw_is_running(&guc->fw);
>+}
>+
>+static inline int intel_guc_sanitize(struct intel_guc *guc)
>+{
>+	intel_uc_fw_sanitize(&guc->fw);
>+	guc->mmio_msg = 0;
>+
>+	return 0;
>+}
>+
>+static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
>+{
>+	spin_lock_irq(&guc->irq_lock);
>+	guc->msg_enabled_mask |= mask;
>+	spin_unlock_irq(&guc->irq_lock);
>+}
>+
>+static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
>+{
>+	spin_lock_irq(&guc->irq_lock);
>+	guc->msg_enabled_mask &= ~mask;
>+	spin_unlock_irq(&guc->irq_lock);
>+}
>+
>+int intel_guc_reset_engine(struct intel_guc *guc,
>+			   struct intel_engine_cs *engine);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,660 @@
>+/*
>+ * Copyright Â© 2014-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include <linux/debugfs.h>
>+
>+#include "gt/intel_gt.h"
>+#include "intel_guc_log.h"
>+#include "i915_drv.h"
>+
>+static void guc_log_capture_logs(struct intel_guc_log *log);
>+
>+/**
>+ * DOC: GuC firmware log
>+ *
>+ * Firmware log is enabled by setting i915.guc_log_level to the positive level.
>+ * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
>+ * i915_guc_load_status will print out firmware loading status and scratch
>+ * registers value.
>+ */
>+
>+static int guc_action_flush_log_complete(struct intel_guc *guc)
>+{
>+	u32 action[] = {
>+		INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE
>+	};
>+
>+	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>+}
>+
>+static int guc_action_flush_log(struct intel_guc *guc)
>+{
>+	u32 action[] = {
>+		INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH,
>+		0
>+	};
>+
>+	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>+}
>+
>+static int guc_action_control_log(struct intel_guc *guc, bool enable,
>+				  bool default_logging, u32 verbosity)
>+{
>+	u32 action[] = {
>+		INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING,
>+		(enable ? GUC_LOG_CONTROL_LOGGING_ENABLED : 0) |
>+		(verbosity << GUC_LOG_CONTROL_VERBOSITY_SHIFT) |
>+		(default_logging ? GUC_LOG_CONTROL_DEFAULT_LOGGING : 0)
>+	};
>+
>+	GEM_BUG_ON(verbosity > GUC_LOG_VERBOSITY_MAX);
>+
>+	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>+}
>+
>+static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
>+{
>+	return container_of(log, struct intel_guc, log);
>+}
>+
>+static void guc_log_enable_flush_events(struct intel_guc_log *log)
>+{
>+	intel_guc_enable_msg(log_to_guc(log),
>+			     INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
>+			     INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
>+}
>+
>+static void guc_log_disable_flush_events(struct intel_guc_log *log)
>+{
>+	intel_guc_disable_msg(log_to_guc(log),
>+			      INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
>+			      INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
>+}
>+
>+/*
>+ * Sub buffer switch callback. Called whenever relay has to switch to a new
>+ * sub buffer, relay stays on the same sub buffer if 0 is returned.
>+ */
>+static int subbuf_start_callback(struct rchan_buf *buf,
>+				 void *subbuf,
>+				 void *prev_subbuf,
>+				 size_t prev_padding)
>+{
>+	/*
>+	 * Use no-overwrite mode by default, where relay will stop accepting
>+	 * new data if there are no empty sub buffers left.
>+	 * There is no strict synchronization enforced by relay between Consumer
>+	 * and Producer. In overwrite mode, there is a possibility of getting
>+	 * inconsistent/garbled data, the producer could be writing on to the
>+	 * same sub buffer from which Consumer is reading. This can't be avoided
>+	 * unless Consumer is fast enough and can always run in tandem with
>+	 * Producer.
>+	 */
>+	if (relay_buf_full(buf))
>+		return 0;
>+
>+	return 1;
>+}
>+
>+/*
>+ * file_create() callback. Creates relay file in debugfs.
>+ */
>+static struct dentry *create_buf_file_callback(const char *filename,
>+					       struct dentry *parent,
>+					       umode_t mode,
>+					       struct rchan_buf *buf,
>+					       int *is_global)
>+{
>+	struct dentry *buf_file;
>+
>+	/*
>+	 * This to enable the use of a single buffer for the relay channel and
>+	 * correspondingly have a single file exposed to User, through which
>+	 * it can collect the logs in order without any post-processing.
>+	 * Need to set 'is_global' even if parent is NULL for early logging.
>+	 */
>+	*is_global = 1;
>+
>+	if (!parent)
>+		return NULL;
>+
>+	buf_file = debugfs_create_file(filename, mode,
>+				       parent, buf, &relay_file_operations);
>+	if (IS_ERR(buf_file))
>+		return NULL;
>+
>+	return buf_file;
>+}
>+
>+/*
>+ * file_remove() default callback. Removes relay file in debugfs.
>+ */
>+static int remove_buf_file_callback(struct dentry *dentry)
>+{
>+	debugfs_remove(dentry);
>+	return 0;
>+}
>+
>+/* relay channel callbacks */
>+static struct rchan_callbacks relay_callbacks = {
>+	.subbuf_start = subbuf_start_callback,
>+	.create_buf_file = create_buf_file_callback,
>+	.remove_buf_file = remove_buf_file_callback,
>+};
>+
>+static void guc_move_to_next_buf(struct intel_guc_log *log)
>+{
>+	/*
>+	 * Make sure the updates made in the sub buffer are visible when
>+	 * Consumer sees the following update to offset inside the sub buffer.
>+	 */
>+	smp_wmb();
>+
>+	/* All data has been written, so now move the offset of sub buffer. */
>+	relay_reserve(log->relay.channel, log->vma->obj->base.size);
>+
>+	/* Switch to the next sub buffer */
>+	relay_flush(log->relay.channel);
>+}
>+
>+static void *guc_get_write_buffer(struct intel_guc_log *log)
>+{
>+	/*
>+	 * Just get the base address of a new sub buffer and copy data into it
>+	 * ourselves. NULL will be returned in no-overwrite mode, if all sub
>+	 * buffers are full. Could have used the relay_write() to indirectly
>+	 * copy the data, but that would have been bit convoluted, as we need to
>+	 * write to only certain locations inside a sub buffer which cannot be
>+	 * done without using relay_reserve() along with relay_write(). So its
>+	 * better to use relay_reserve() alone.
>+	 */
>+	return relay_reserve(log->relay.channel, 0);
>+}
>+
>+static bool guc_check_log_buf_overflow(struct intel_guc_log *log,
>+				       enum guc_log_buffer_type type,
>+				       unsigned int full_cnt)
>+{
>+	unsigned int prev_full_cnt = log->stats[type].sampled_overflow;
>+	bool overflow = false;
>+
>+	if (full_cnt != prev_full_cnt) {
>+		overflow = true;
>+
>+		log->stats[type].overflow = full_cnt;
>+		log->stats[type].sampled_overflow += full_cnt - prev_full_cnt;
>+
>+		if (full_cnt < prev_full_cnt) {
>+			/* buffer_full_cnt is a 4 bit counter */
>+			log->stats[type].sampled_overflow += 16;
>+		}
>+
>+		dev_notice_ratelimited(guc_to_gt(log_to_guc(log))->i915->drm.dev,
>+				       "GuC log buffer overflow\n");
>+	}
>+
>+	return overflow;
>+}
>+
>+static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type)
>+{
>+	switch (type) {
>+	case GUC_ISR_LOG_BUFFER:
>+		return ISR_BUFFER_SIZE;
>+	case GUC_DPC_LOG_BUFFER:
>+		return DPC_BUFFER_SIZE;
>+	case GUC_CRASH_DUMP_LOG_BUFFER:
>+		return CRASH_BUFFER_SIZE;
>+	default:
>+		MISSING_CASE(type);
>+	}
>+
>+	return 0;
>+}
>+
>+static void guc_read_update_log_buffer(struct intel_guc_log *log)
>+{
>+	unsigned int buffer_size, read_offset, write_offset, bytes_to_copy, full_cnt;
>+	struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
>+	struct guc_log_buffer_state log_buf_state_local;
>+	enum guc_log_buffer_type type;
>+	void *src_data, *dst_data;
>+	bool new_overflow;
>+
>+	mutex_lock(&log->relay.lock);
>+
>+	if (WARN_ON(!intel_guc_log_relay_enabled(log)))
>+		goto out_unlock;
>+
>+	/* Get the pointer to shared GuC log buffer */
>+	log_buf_state = src_data = log->relay.buf_addr;
>+
>+	/* Get the pointer to local buffer to store the logs */
>+	log_buf_snapshot_state = dst_data = guc_get_write_buffer(log);
>+
>+	if (unlikely(!log_buf_snapshot_state)) {
>+		/*
>+		 * Used rate limited to avoid deluge of messages, logs might be
>+		 * getting consumed by User at a slow rate.
>+		 */
>+		DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
>+		log->relay.full_count++;
>+
>+		goto out_unlock;
>+	}
>+
>+	/* Actual logs are present from the 2nd page */
>+	src_data += PAGE_SIZE;
>+	dst_data += PAGE_SIZE;
>+
>+	for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
>+		/*
>+		 * Make a copy of the state structure, inside GuC log buffer
>+		 * (which is uncached mapped), on the stack to avoid reading
>+		 * from it multiple times.
>+		 */
>+		memcpy(&log_buf_state_local, log_buf_state,
>+		       sizeof(struct guc_log_buffer_state));
>+		buffer_size = guc_get_log_buffer_size(type);
>+		read_offset = log_buf_state_local.read_ptr;
>+		write_offset = log_buf_state_local.sampled_write_ptr;
>+		full_cnt = log_buf_state_local.buffer_full_cnt;
>+
>+		/* Bookkeeping stuff */
>+		log->stats[type].flush += log_buf_state_local.flush_to_file;
>+		new_overflow = guc_check_log_buf_overflow(log, type, full_cnt);
>+
>+		/* Update the state of shared log buffer */
>+		log_buf_state->read_ptr = write_offset;
>+		log_buf_state->flush_to_file = 0;
>+		log_buf_state++;
>+
>+		/* First copy the state structure in snapshot buffer */
>+		memcpy(log_buf_snapshot_state, &log_buf_state_local,
>+		       sizeof(struct guc_log_buffer_state));
>+
>+		/*
>+		 * The write pointer could have been updated by GuC firmware,
>+		 * after sending the flush interrupt to Host, for consistency
>+		 * set write pointer value to same value of sampled_write_ptr
>+		 * in the snapshot buffer.
>+		 */
>+		log_buf_snapshot_state->write_ptr = write_offset;
>+		log_buf_snapshot_state++;
>+
>+		/* Now copy the actual logs. */
>+		if (unlikely(new_overflow)) {
>+			/* copy the whole buffer in case of overflow */
>+			read_offset = 0;
>+			write_offset = buffer_size;
>+		} else if (unlikely((read_offset > buffer_size) ||
>+				    (write_offset > buffer_size))) {
>+			DRM_ERROR("invalid log buffer state\n");
>+			/* copy whole buffer as offsets are unreliable */
>+			read_offset = 0;
>+			write_offset = buffer_size;
>+		}
>+
>+		/* Just copy the newly written data */
>+		if (read_offset > write_offset) {
>+			i915_memcpy_from_wc(dst_data, src_data, write_offset);
>+			bytes_to_copy = buffer_size - read_offset;
>+		} else {
>+			bytes_to_copy = write_offset - read_offset;
>+		}
>+		i915_memcpy_from_wc(dst_data + read_offset,
>+				    src_data + read_offset, bytes_to_copy);
>+
>+		src_data += buffer_size;
>+		dst_data += buffer_size;
>+	}
>+
>+	guc_move_to_next_buf(log);
>+
>+out_unlock:
>+	mutex_unlock(&log->relay.lock);
>+}
>+
>+static void capture_logs_work(struct work_struct *work)
>+{
>+	struct intel_guc_log *log =
>+		container_of(work, struct intel_guc_log, relay.flush_work);
>+
>+	guc_log_capture_logs(log);
>+}
>+
>+static int guc_log_map(struct intel_guc_log *log)
>+{
>+	void *vaddr;
>+
>+	lockdep_assert_held(&log->relay.lock);
>+
>+	if (!log->vma)
>+		return -ENODEV;
>+
>+	/*
>+	 * Create a WC (Uncached for read) vmalloc mapping of log
>+	 * buffer pages, so that we can directly get the data
>+	 * (up-to-date) from memory.
>+	 */
>+	vaddr = i915_gem_object_pin_map(log->vma->obj, I915_MAP_WC);
>+	if (IS_ERR(vaddr))
>+		return PTR_ERR(vaddr);
>+
>+	log->relay.buf_addr = vaddr;
>+
>+	return 0;
>+}
>+
>+static void guc_log_unmap(struct intel_guc_log *log)
>+{
>+	lockdep_assert_held(&log->relay.lock);
>+
>+	i915_gem_object_unpin_map(log->vma->obj);
>+	log->relay.buf_addr = NULL;
>+}
>+
>+void intel_guc_log_init_early(struct intel_guc_log *log)
>+{
>+	mutex_init(&log->relay.lock);
>+	INIT_WORK(&log->relay.flush_work, capture_logs_work);
>+}
>+
>+static int guc_log_relay_create(struct intel_guc_log *log)
>+{
>+	struct intel_guc *guc = log_to_guc(log);
>+	struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
>+	struct rchan *guc_log_relay_chan;
>+	size_t n_subbufs, subbuf_size;
>+	int ret;
>+
>+	lockdep_assert_held(&log->relay.lock);
>+
>+	 /* Keep the size of sub buffers same as shared log buffer */
>+	subbuf_size = log->vma->size;
>+
>+	/*
>+	 * Store up to 8 snapshots, which is large enough to buffer sufficient
>+	 * boot time logs and provides enough leeway to User, in terms of
>+	 * latency, for consuming the logs from relay. Also doesn't take
>+	 * up too much memory.
>+	 */
>+	n_subbufs = 8;
>+
>+	guc_log_relay_chan = relay_open("guc_log",
>+					dev_priv->drm.primary->debugfs_root,
>+					subbuf_size, n_subbufs,
>+					&relay_callbacks, dev_priv);
>+	if (!guc_log_relay_chan) {
>+		DRM_ERROR("Couldn't create relay chan for GuC logging\n");
>+
>+		ret = -ENOMEM;
>+		return ret;
>+	}
>+
>+	GEM_BUG_ON(guc_log_relay_chan->subbuf_size < subbuf_size);
>+	log->relay.channel = guc_log_relay_chan;
>+
>+	return 0;
>+}
>+
>+static void guc_log_relay_destroy(struct intel_guc_log *log)
>+{
>+	lockdep_assert_held(&log->relay.lock);
>+
>+	relay_close(log->relay.channel);
>+	log->relay.channel = NULL;
>+}
>+
>+static void guc_log_capture_logs(struct intel_guc_log *log)
>+{
>+	struct intel_guc *guc = log_to_guc(log);
>+	struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
>+	intel_wakeref_t wakeref;
>+
>+	guc_read_update_log_buffer(log);
>+
>+	/*
>+	 * Generally device is expected to be active only at this
>+	 * time, so get/put should be really quick.
>+	 */
>+	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
>+		guc_action_flush_log_complete(guc);
>+}
>+
>+static u32 __get_default_log_level(struct intel_guc_log *log)
>+{
>+	/* A negative value means "use platform/config default" */
>+	if (i915_modparams.guc_log_level < 0) {
>+		return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
>+			IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) ?
>+			GUC_LOG_LEVEL_MAX : GUC_LOG_LEVEL_NON_VERBOSE;
>+	}
>+
>+	if (i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX) {
>+		DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
>+			 "guc_log_level", i915_modparams.guc_log_level,
>+			 "verbosity too high");
>+		return (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
>+			IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) ?
>+			GUC_LOG_LEVEL_MAX : GUC_LOG_LEVEL_DISABLED;
>+	}
>+
>+	GEM_BUG_ON(i915_modparams.guc_log_level < GUC_LOG_LEVEL_DISABLED);
>+	GEM_BUG_ON(i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX);
>+	return i915_modparams.guc_log_level;
>+}
>+
>+int intel_guc_log_create(struct intel_guc_log *log)
>+{
>+	struct intel_guc *guc = log_to_guc(log);
>+	struct i915_vma *vma;
>+	u32 guc_log_size;
>+	int ret;
>+
>+	GEM_BUG_ON(log->vma);
>+
>+	/*
>+	 *  GuC Log buffer Layout
>+	 *
>+	 *  +===============================+ 00B
>+	 *  |    Crash dump state header    |
>+	 *  +-------------------------------+ 32B
>+	 *  |       DPC state header        |
>+	 *  +-------------------------------+ 64B
>+	 *  |       ISR state header        |
>+	 *  +-------------------------------+ 96B
>+	 *  |                               |
>+	 *  +===============================+ PAGE_SIZE (4KB)
>+	 *  |        Crash Dump logs        |
>+	 *  +===============================+ + CRASH_SIZE
>+	 *  |           DPC logs            |
>+	 *  +===============================+ + DPC_SIZE
>+	 *  |           ISR logs            |
>+	 *  +===============================+ + ISR_SIZE
>+	 */
>+	guc_log_size = PAGE_SIZE + CRASH_BUFFER_SIZE + DPC_BUFFER_SIZE +
>+			ISR_BUFFER_SIZE;
>+
>+	vma = intel_guc_allocate_vma(guc, guc_log_size);
>+	if (IS_ERR(vma)) {
>+		ret = PTR_ERR(vma);
>+		goto err;
>+	}
>+
>+	log->vma = vma;
>+
>+	log->level = __get_default_log_level(log);
>+	DRM_DEBUG_DRIVER("guc_log_level=%d (%s, verbose:%s, verbosity:%d)\n",
>+			 log->level, enableddisabled(log->level),
>+			 yesno(GUC_LOG_LEVEL_IS_VERBOSE(log->level)),
>+			 GUC_LOG_LEVEL_TO_VERBOSITY(log->level));
>+
>+	return 0;
>+
>+err:
>+	DRM_ERROR("Failed to allocate GuC log buffer. %d\n", ret);
>+	return ret;
>+}
>+
>+void intel_guc_log_destroy(struct intel_guc_log *log)
>+{
>+	i915_vma_unpin_and_release(&log->vma, 0);
>+}
>+
>+int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)
>+{
>+	struct intel_guc *guc = log_to_guc(log);
>+	struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
>+	intel_wakeref_t wakeref;
>+	int ret = 0;
>+
>+	BUILD_BUG_ON(GUC_LOG_VERBOSITY_MIN != 0);
>+	GEM_BUG_ON(!log->vma);
>+
>+	/*
>+	 * GuC is recognizing log levels starting from 0 to max, we're using 0
>+	 * as indication that logging should be disabled.
>+	 */
>+	if (level < GUC_LOG_LEVEL_DISABLED || level > GUC_LOG_LEVEL_MAX)
>+		return -EINVAL;
>+
>+	mutex_lock(&dev_priv->drm.struct_mutex);
>+
>+	if (log->level == level)
>+		goto out_unlock;
>+
>+	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
>+		ret = guc_action_control_log(guc,
>+					     GUC_LOG_LEVEL_IS_VERBOSE(level),
>+					     GUC_LOG_LEVEL_IS_ENABLED(level),
>+					     GUC_LOG_LEVEL_TO_VERBOSITY(level));
>+	if (ret) {
>+		DRM_DEBUG_DRIVER("guc_log_control action failed %d\n", ret);
>+		goto out_unlock;
>+	}
>+
>+	log->level = level;
>+
>+out_unlock:
>+	mutex_unlock(&dev_priv->drm.struct_mutex);
>+
>+	return ret;
>+}
>+
>+bool intel_guc_log_relay_enabled(const struct intel_guc_log *log)
>+{
>+	return log->relay.buf_addr;
>+}
>+
>+int intel_guc_log_relay_open(struct intel_guc_log *log)
>+{
>+	int ret;
>+
>+	mutex_lock(&log->relay.lock);
>+
>+	if (intel_guc_log_relay_enabled(log)) {
>+		ret = -EEXIST;
>+		goto out_unlock;
>+	}
>+
>+	/*
>+	 * We require SSE 4.1 for fast reads from the GuC log buffer and
>+	 * it should be present on the chipsets supporting GuC based
>+	 * submisssions.
>+	 */
>+	if (!i915_has_memcpy_from_wc()) {
>+		ret = -ENXIO;
>+		goto out_unlock;
>+	}
>+
>+	ret = guc_log_relay_create(log);
>+	if (ret)
>+		goto out_unlock;
>+
>+	ret = guc_log_map(log);
>+	if (ret)
>+		goto out_relay;
>+
>+	mutex_unlock(&log->relay.lock);
>+
>+	guc_log_enable_flush_events(log);
>+
>+	/*
>+	 * When GuC is logging without us relaying to userspace, we're ignoring
>+	 * the flush notification. This means that we need to unconditionally
>+	 * flush on relay enabling, since GuC only notifies us once.
>+	 */
>+	queue_work(system_highpri_wq, &log->relay.flush_work);
>+
>+	return 0;
>+
>+out_relay:
>+	guc_log_relay_destroy(log);
>+out_unlock:
>+	mutex_unlock(&log->relay.lock);
>+
>+	return ret;
>+}
>+
>+void intel_guc_log_relay_flush(struct intel_guc_log *log)
>+{
>+	struct intel_guc *guc = log_to_guc(log);
>+	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>+	intel_wakeref_t wakeref;
>+
>+	/*
>+	 * Before initiating the forceful flush, wait for any pending/ongoing
>+	 * flush to complete otherwise forceful flush may not actually happen.
>+	 */
>+	flush_work(&log->relay.flush_work);
>+
>+	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
>+		guc_action_flush_log(guc);
>+
>+	/* GuC would have updated log buffer by now, so capture it */
>+	guc_log_capture_logs(log);
>+}
>+
>+void intel_guc_log_relay_close(struct intel_guc_log *log)
>+{
>+	struct intel_guc *guc = log_to_guc(log);
>+	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>+
>+	guc_log_disable_flush_events(log);
>+	intel_synchronize_irq(i915);
>+
>+	flush_work(&log->relay.flush_work);
>+
>+	mutex_lock(&log->relay.lock);
>+	GEM_BUG_ON(!intel_guc_log_relay_enabled(log));
>+	guc_log_unmap(log);
>+	guc_log_relay_destroy(log);
>+	mutex_unlock(&log->relay.lock);
>+}
>+
>+void intel_guc_log_handle_flush_event(struct intel_guc_log *log)
>+{
>+	queue_work(system_highpri_wq, &log->relay.flush_work);
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,99 @@
>+/*
>+ * Copyright Â© 2014-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef _INTEL_GUC_LOG_H_
>+#define _INTEL_GUC_LOG_H_
>+
>+#include <linux/mutex.h>
>+#include <linux/relay.h>
>+#include <linux/workqueue.h>
>+
>+#include "intel_guc_fwif.h"
>+#include "i915_gem.h"
>+
>+struct intel_guc;
>+
>+#ifdef CONFIG_DRM_I915_DEBUG_GUC
>+#define CRASH_BUFFER_SIZE	SZ_2M
>+#define DPC_BUFFER_SIZE		SZ_8M
>+#define ISR_BUFFER_SIZE		SZ_8M
>+#else
>+#define CRASH_BUFFER_SIZE	SZ_8K
>+#define DPC_BUFFER_SIZE		SZ_32K
>+#define ISR_BUFFER_SIZE		SZ_32K
>+#endif
>+
>+/*
>+ * While we're using plain log level in i915, GuC controls are much more...
>+ * "elaborate"? We have a couple of bits for verbosity, separate bit for actual
>+ * log enabling, and separate bit for default logging - which "conveniently"
>+ * ignores the enable bit.
>+ */
>+#define GUC_LOG_LEVEL_DISABLED		0
>+#define GUC_LOG_LEVEL_NON_VERBOSE	1
>+#define GUC_LOG_LEVEL_IS_ENABLED(x)	((x) > GUC_LOG_LEVEL_DISABLED)
>+#define GUC_LOG_LEVEL_IS_VERBOSE(x)	((x) > GUC_LOG_LEVEL_NON_VERBOSE)
>+#define GUC_LOG_LEVEL_TO_VERBOSITY(x) ({		\
>+	typeof(x) _x = (x);				\
>+	GUC_LOG_LEVEL_IS_VERBOSE(_x) ? _x - 2 : 0;	\
>+})
>+#define GUC_VERBOSITY_TO_LOG_LEVEL(x)	((x) + 2)
>+#define GUC_LOG_LEVEL_MAX GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX)
>+
>+struct intel_guc_log {
>+	u32 level;
>+	struct i915_vma *vma;
>+	struct {
>+		void *buf_addr;
>+		struct work_struct flush_work;
>+		struct rchan *channel;
>+		struct mutex lock;
>+		u32 full_count;
>+	} relay;
>+	/* logging related stats */
>+	struct {
>+		u32 sampled_overflow;
>+		u32 overflow;
>+		u32 flush;
>+	} stats[GUC_MAX_LOG_BUFFER];
>+};
>+
>+void intel_guc_log_init_early(struct intel_guc_log *log);
>+int intel_guc_log_create(struct intel_guc_log *log);
>+void intel_guc_log_destroy(struct intel_guc_log *log);
>+
>+int intel_guc_log_set_level(struct intel_guc_log *log, u32 level);
>+bool intel_guc_log_relay_enabled(const struct intel_guc_log *log);
>+int intel_guc_log_relay_open(struct intel_guc_log *log);
>+void intel_guc_log_relay_flush(struct intel_guc_log *log);
>+void intel_guc_log_relay_close(struct intel_guc_log *log);
>+
>+void intel_guc_log_handle_flush_event(struct intel_guc_log *log);
>+
>+static inline u32 intel_guc_log_get_level(struct intel_guc_log *log)
>+{
>+	return log->level;
>+}
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h	2019-08-31 15:01:12.241736202 -0500
>@@ -0,0 +1,161 @@
>+/*
>+ * Copyright Â© 2014 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+#ifndef _INTEL_GUC_REG_H_
>+#define _INTEL_GUC_REG_H_
>+
>+#include <linux/compiler.h>
>+#include <linux/types.h>
>+
>+#include "i915_reg.h"
>+
>+/* Definitions of GuC H/W registers, bits, etc */
>+
>+#define GUC_STATUS			_MMIO(0xc000)
>+#define   GS_RESET_SHIFT		0
>+#define   GS_MIA_IN_RESET		  (0x01 << GS_RESET_SHIFT)
>+#define   GS_BOOTROM_SHIFT		1
>+#define   GS_BOOTROM_MASK		  (0x7F << GS_BOOTROM_SHIFT)
>+#define   GS_BOOTROM_RSA_FAILED		  (0x50 << GS_BOOTROM_SHIFT)
>+#define   GS_BOOTROM_JUMP_PASSED	  (0x76 << GS_BOOTROM_SHIFT)
>+#define   GS_UKERNEL_SHIFT		8
>+#define   GS_UKERNEL_MASK		  (0xFF << GS_UKERNEL_SHIFT)
>+#define   GS_UKERNEL_LAPIC_DONE		  (0x30 << GS_UKERNEL_SHIFT)
>+#define   GS_UKERNEL_DPC_ERROR		  (0x60 << GS_UKERNEL_SHIFT)
>+#define   GS_UKERNEL_EXCEPTION		  (0x70 << GS_UKERNEL_SHIFT)
>+#define   GS_UKERNEL_READY		  (0xF0 << GS_UKERNEL_SHIFT)
>+#define   GS_MIA_SHIFT			16
>+#define   GS_MIA_MASK			  (0x07 << GS_MIA_SHIFT)
>+#define   GS_MIA_CORE_STATE		  (0x01 << GS_MIA_SHIFT)
>+#define   GS_MIA_HALT_REQUESTED		  (0x02 << GS_MIA_SHIFT)
>+#define   GS_MIA_ISR_ENTRY		  (0x04 << GS_MIA_SHIFT)
>+#define   GS_AUTH_STATUS_SHIFT		30
>+#define   GS_AUTH_STATUS_MASK		  (0x03 << GS_AUTH_STATUS_SHIFT)
>+#define   GS_AUTH_STATUS_BAD		  (0x01 << GS_AUTH_STATUS_SHIFT)
>+#define   GS_AUTH_STATUS_GOOD		  (0x02 << GS_AUTH_STATUS_SHIFT)
>+
>+#define SOFT_SCRATCH(n)			_MMIO(0xc180 + (n) * 4)
>+#define SOFT_SCRATCH_COUNT		16
>+
>+#define GEN11_SOFT_SCRATCH(n)		_MMIO(0x190240 + (n) * 4)
>+#define GEN11_SOFT_SCRATCH_COUNT	4
>+
>+#define UOS_RSA_SCRATCH(i)		_MMIO(0xc200 + (i) * 4)
>+#define UOS_RSA_SCRATCH_COUNT		64
>+
>+#define DMA_ADDR_0_LOW			_MMIO(0xc300)
>+#define DMA_ADDR_0_HIGH			_MMIO(0xc304)
>+#define DMA_ADDR_1_LOW			_MMIO(0xc308)
>+#define DMA_ADDR_1_HIGH			_MMIO(0xc30c)
>+#define   DMA_ADDRESS_SPACE_WOPCM	  (7 << 16)
>+#define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
>+#define DMA_COPY_SIZE			_MMIO(0xc310)
>+#define DMA_CTRL			_MMIO(0xc314)
>+#define   HUC_UKERNEL			  (1<<9)
>+#define   UOS_MOVE			  (1<<4)
>+#define   START_DMA			  (1<<0)
>+#define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
>+#define   GUC_WOPCM_OFFSET_VALID	  (1<<0)
>+#define   HUC_LOADING_AGENT_VCR		  (0<<1)
>+#define   HUC_LOADING_AGENT_GUC		  (1<<1)
>+#define   GUC_WOPCM_OFFSET_SHIFT	14
>+#define   GUC_WOPCM_OFFSET_MASK		  (0x3ffff << GUC_WOPCM_OFFSET_SHIFT)
>+#define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>+
>+#define HUC_STATUS2             _MMIO(0xD3B0)
>+#define   HUC_FW_VERIFIED       (1<<7)
>+
>+#define GEN11_HUC_KERNEL_LOAD_INFO	_MMIO(0xC1DC)
>+#define   HUC_LOAD_SUCCESSFUL		  (1 << 0)
>+
>+#define GUC_WOPCM_SIZE			_MMIO(0xc050)
>+#define   GUC_WOPCM_SIZE_LOCKED		  (1<<0)
>+#define   GUC_WOPCM_SIZE_SHIFT		12
>+#define   GUC_WOPCM_SIZE_MASK		  (0xfffff << GUC_WOPCM_SIZE_SHIFT)
>+
>+#define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>+#define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
>+#define GEN9_GT_PM_CONFIG		_MMIO(0x13816c)
>+#define   GT_DOORBELL_ENABLE		  (1<<0)
>+
>+#define GEN8_GTCR			_MMIO(0x4274)
>+#define   GEN8_GTCR_INVALIDATE		  (1<<0)
>+
>+#define GUC_ARAT_C6DIS			_MMIO(0xA178)
>+
>+#define GUC_SHIM_CONTROL		_MMIO(0xc064)
>+#define   GUC_DISABLE_SRAM_INIT_TO_ZEROES	(1<<0)
>+#define   GUC_ENABLE_READ_CACHE_LOGIC		(1<<1)
>+#define   GUC_ENABLE_MIA_CACHING		(1<<2)
>+#define   GUC_GEN10_MSGCH_ENABLE		(1<<4)
>+#define   GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA	(1<<9)
>+#define   GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	(1<<10)
>+#define   GUC_ENABLE_MIA_CLOCK_GATING		(1<<15)
>+#define   GUC_GEN10_SHIM_WC_ENABLE		(1<<21)
>+
>+#define GUC_SEND_INTERRUPT		_MMIO(0xc4c8)
>+#define   GUC_SEND_TRIGGER		  (1<<0)
>+#define GEN11_GUC_HOST_INTERRUPT	_MMIO(0x1901f0)
>+
>+#define GUC_NUM_DOORBELLS		256
>+
>+/* format of the HW-monitored doorbell cacheline */
>+struct guc_doorbell_info {
>+	u32 db_status;
>+#define GUC_DOORBELL_DISABLED		0
>+#define GUC_DOORBELL_ENABLED		1
>+
>+	u32 cookie;
>+	u32 reserved[14];
>+} __packed;
>+
>+#define GEN8_DRBREGL(x)			_MMIO(0x1000 + (x) * 8)
>+#define   GEN8_DRB_VALID		  (1<<0)
>+#define GEN8_DRBREGU(x)			_MMIO(0x1000 + (x) * 8 + 4)
>+
>+#define DE_GUCRMR			_MMIO(0x44054)
>+
>+#define GUC_BCS_RCS_IER			_MMIO(0xC550)
>+#define GUC_VCS2_VCS1_IER		_MMIO(0xC554)
>+#define GUC_WD_VECS_IER			_MMIO(0xC558)
>+#define GUC_PM_P24C_IER			_MMIO(0xC55C)
>+
>+/* GuC Interrupt Vector */
>+#define GUC_INTR_GUC2HOST		BIT(15)
>+#define GUC_INTR_EXEC_ERROR		BIT(14)
>+#define GUC_INTR_DISPLAY_EVENT		BIT(13)
>+#define GUC_INTR_SEM_SIG		BIT(12)
>+#define GUC_INTR_IOMMU2GUC		BIT(11)
>+#define GUC_INTR_DOORBELL_RANG		BIT(10)
>+#define GUC_INTR_DMA_DONE		BIT(9)
>+#define GUC_INTR_FATAL_ERROR		BIT(8)
>+#define GUC_INTR_NOTIF_ERROR		BIT(7)
>+#define GUC_INTR_SW_INT_6		BIT(6)
>+#define GUC_INTR_SW_INT_5		BIT(5)
>+#define GUC_INTR_SW_INT_4		BIT(4)
>+#define GUC_INTR_SW_INT_3		BIT(3)
>+#define GUC_INTR_SW_INT_2		BIT(2)
>+#define GUC_INTR_SW_INT_1		BIT(1)
>+#define GUC_INTR_SW_INT_0		BIT(0)
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c	2019-08-31 15:01:12.240736202 -0500
>@@ -0,0 +1,1168 @@
>+/*
>+ * Copyright Â© 2014 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include <linux/circ_buf.h>
>+
>+#include "gem/i915_gem_context.h"
>+
>+#include "gt/intel_context.h"
>+#include "gt/intel_engine_pm.h"
>+#include "gt/intel_gt.h"
>+#include "gt/intel_lrc_reg.h"
>+#include "intel_guc_submission.h"
>+
>+#include "i915_drv.h"
>+
>+enum {
>+	GUC_PREEMPT_NONE = 0,
>+	GUC_PREEMPT_INPROGRESS,
>+	GUC_PREEMPT_FINISHED,
>+};
>+#define GUC_PREEMPT_BREADCRUMB_DWORDS	0x8
>+#define GUC_PREEMPT_BREADCRUMB_BYTES	\
>+	(sizeof(u32) * GUC_PREEMPT_BREADCRUMB_DWORDS)
>+
>+/**
>+ * DOC: GuC-based command submission
>+ *
>+ * GuC client:
>+ * A intel_guc_client refers to a submission path through GuC. Currently, there
>+ * is only one client, which is charged with all submissions to the GuC. This
>+ * struct is the owner of a doorbell, a process descriptor and a workqueue (all
>+ * of them inside a single gem object that contains all required pages for these
>+ * elements).
>+ *
>+ * GuC stage descriptor:
>+ * During initialization, the driver allocates a static pool of 1024 such
>+ * descriptors, and shares them with the GuC.
>+ * Currently, there exists a 1:1 mapping between a intel_guc_client and a
>+ * guc_stage_desc (via the client's stage_id), so effectively only one
>+ * gets used. This stage descriptor lets the GuC know about the doorbell,
>+ * workqueue and process descriptor. Theoretically, it also lets the GuC
>+ * know about our HW contexts (context ID, etc...), but we actually
>+ * employ a kind of submission where the GuC uses the LRCA sent via the work
>+ * item instead (the single guc_stage_desc associated to execbuf client
>+ * contains information about the default kernel context only, but this is
>+ * essentially unused). This is called a "proxy" submission.
>+ *
>+ * The Scratch registers:
>+ * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
>+ * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
>+ * triggers an interrupt on the GuC via another register write (0xC4C8).
>+ * Firmware writes a success/fail code back to the action register after
>+ * processes the request. The kernel driver polls waiting for this update and
>+ * then proceeds.
>+ * See intel_guc_send()
>+ *
>+ * Doorbells:
>+ * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
>+ * mapped into process space.
>+ *
>+ * Work Items:
>+ * There are several types of work items that the host may place into a
>+ * workqueue, each with its own requirements and limitations. Currently only
>+ * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
>+ * represents in-order queue. The kernel driver packs ring tail pointer and an
>+ * ELSP context descriptor dword into Work Item.
>+ * See guc_add_request()
>+ *
>+ */
>+
>+static inline struct i915_priolist *to_priolist(struct rb_node *rb)
>+{
>+	return rb_entry(rb, struct i915_priolist, node);
>+}
>+
>+static inline bool is_high_priority(struct intel_guc_client *client)
>+{
>+	return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH ||
>+		client->priority == GUC_CLIENT_PRIORITY_HIGH);
>+}
>+
>+static int reserve_doorbell(struct intel_guc_client *client)
>+{
>+	unsigned long offset;
>+	unsigned long end;
>+	u16 id;
>+
>+	GEM_BUG_ON(client->doorbell_id != GUC_DOORBELL_INVALID);
>+
>+	/*
>+	 * The bitmap tracks which doorbell registers are currently in use.
>+	 * It is split into two halves; the first half is used for normal
>+	 * priority contexts, the second half for high-priority ones.
>+	 */
>+	offset = 0;
>+	end = GUC_NUM_DOORBELLS / 2;
>+	if (is_high_priority(client)) {
>+		offset = end;
>+		end += offset;
>+	}
>+
>+	id = find_next_zero_bit(client->guc->doorbell_bitmap, end, offset);
>+	if (id == end)
>+		return -ENOSPC;
>+
>+	__set_bit(id, client->guc->doorbell_bitmap);
>+	client->doorbell_id = id;
>+	DRM_DEBUG_DRIVER("client %u (high prio=%s) reserved doorbell: %d\n",
>+			 client->stage_id, yesno(is_high_priority(client)),
>+			 id);
>+	return 0;
>+}
>+
>+static bool has_doorbell(struct intel_guc_client *client)
>+{
>+	if (client->doorbell_id == GUC_DOORBELL_INVALID)
>+		return false;
>+
>+	return test_bit(client->doorbell_id, client->guc->doorbell_bitmap);
>+}
>+
>+static void unreserve_doorbell(struct intel_guc_client *client)
>+{
>+	GEM_BUG_ON(!has_doorbell(client));
>+
>+	__clear_bit(client->doorbell_id, client->guc->doorbell_bitmap);
>+	client->doorbell_id = GUC_DOORBELL_INVALID;
>+}
>+
>+/*
>+ * Tell the GuC to allocate or deallocate a specific doorbell
>+ */
>+
>+static int __guc_allocate_doorbell(struct intel_guc *guc, u32 stage_id)
>+{
>+	u32 action[] = {
>+		INTEL_GUC_ACTION_ALLOCATE_DOORBELL,
>+		stage_id
>+	};
>+
>+	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>+}
>+
>+static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 stage_id)
>+{
>+	u32 action[] = {
>+		INTEL_GUC_ACTION_DEALLOCATE_DOORBELL,
>+		stage_id
>+	};
>+
>+	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>+}
>+
>+static struct guc_stage_desc *__get_stage_desc(struct intel_guc_client *client)
>+{
>+	struct guc_stage_desc *base = client->guc->stage_desc_pool_vaddr;
>+
>+	return &base[client->stage_id];
>+}
>+
>+/*
>+ * Initialise, update, or clear doorbell data shared with the GuC
>+ *
>+ * These functions modify shared data and so need access to the mapped
>+ * client object which contains the page being used for the doorbell
>+ */
>+
>+static void __update_doorbell_desc(struct intel_guc_client *client, u16 new_id)
>+{
>+	struct guc_stage_desc *desc;
>+
>+	/* Update the GuC's idea of the doorbell ID */
>+	desc = __get_stage_desc(client);
>+	desc->db_id = new_id;
>+}
>+
>+static struct guc_doorbell_info *__get_doorbell(struct intel_guc_client *client)
>+{
>+	return client->vaddr + client->doorbell_offset;
>+}
>+
>+static bool __doorbell_valid(struct intel_guc *guc, u16 db_id)
>+{
>+	struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
>+
>+	GEM_BUG_ON(db_id >= GUC_NUM_DOORBELLS);
>+	return intel_uncore_read(uncore, GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID;
>+}
>+
>+static void __init_doorbell(struct intel_guc_client *client)
>+{
>+	struct guc_doorbell_info *doorbell;
>+
>+	doorbell = __get_doorbell(client);
>+	doorbell->db_status = GUC_DOORBELL_ENABLED;
>+	doorbell->cookie = 0;
>+}
>+
>+static void __fini_doorbell(struct intel_guc_client *client)
>+{
>+	struct guc_doorbell_info *doorbell;
>+	u16 db_id = client->doorbell_id;
>+
>+	doorbell = __get_doorbell(client);
>+	doorbell->db_status = GUC_DOORBELL_DISABLED;
>+
>+	/* Doorbell release flow requires that we wait for GEN8_DRB_VALID bit
>+	 * to go to zero after updating db_status before we call the GuC to
>+	 * release the doorbell
>+	 */
>+	if (wait_for_us(!__doorbell_valid(client->guc, db_id), 10))
>+		WARN_ONCE(true, "Doorbell never became invalid after disable\n");
>+}
>+
>+static int create_doorbell(struct intel_guc_client *client)
>+{
>+	int ret;
>+
>+	if (WARN_ON(!has_doorbell(client)))
>+		return -ENODEV; /* internal setup error, should never happen */
>+
>+	__update_doorbell_desc(client, client->doorbell_id);
>+	__init_doorbell(client);
>+
>+	ret = __guc_allocate_doorbell(client->guc, client->stage_id);
>+	if (ret) {
>+		__fini_doorbell(client);
>+		__update_doorbell_desc(client, GUC_DOORBELL_INVALID);
>+		DRM_DEBUG_DRIVER("Couldn't create client %u doorbell: %d\n",
>+				 client->stage_id, ret);
>+		return ret;
>+	}
>+
>+	return 0;
>+}
>+
>+static int destroy_doorbell(struct intel_guc_client *client)
>+{
>+	int ret;
>+
>+	GEM_BUG_ON(!has_doorbell(client));
>+
>+	__fini_doorbell(client);
>+	ret = __guc_deallocate_doorbell(client->guc, client->stage_id);
>+	if (ret)
>+		DRM_ERROR("Couldn't destroy client %u doorbell: %d\n",
>+			  client->stage_id, ret);
>+
>+	__update_doorbell_desc(client, GUC_DOORBELL_INVALID);
>+
>+	return ret;
>+}
>+
>+static unsigned long __select_cacheline(struct intel_guc *guc)
>+{
>+	unsigned long offset;
>+
>+	/* Doorbell uses a single cache line within a page */
>+	offset = offset_in_page(guc->db_cacheline);
>+
>+	/* Moving to next cache line to reduce contention */
>+	guc->db_cacheline += cache_line_size();
>+
>+	DRM_DEBUG_DRIVER("reserved cacheline 0x%lx, next 0x%x, linesize %u\n",
>+			 offset, guc->db_cacheline, cache_line_size());
>+	return offset;
>+}
>+
>+static inline struct guc_process_desc *
>+__get_process_desc(struct intel_guc_client *client)
>+{
>+	return client->vaddr + client->proc_desc_offset;
>+}
>+
>+/*
>+ * Initialise the process descriptor shared with the GuC firmware.
>+ */
>+static void guc_proc_desc_init(struct intel_guc_client *client)
>+{
>+	struct guc_process_desc *desc;
>+
>+	desc = memset(__get_process_desc(client), 0, sizeof(*desc));
>+
>+	/*
>+	 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
>+	 * space for ring3 clients (set them as in mmap_ioctl) or kernel
>+	 * space for kernel clients (map on demand instead? May make debug
>+	 * easier to have it mapped).
>+	 */
>+	desc->wq_base_addr = 0;
>+	desc->db_base_addr = 0;
>+
>+	desc->stage_id = client->stage_id;
>+	desc->wq_size_bytes = GUC_WQ_SIZE;
>+	desc->wq_status = WQ_STATUS_ACTIVE;
>+	desc->priority = client->priority;
>+}
>+
>+static void guc_proc_desc_fini(struct intel_guc_client *client)
>+{
>+	struct guc_process_desc *desc;
>+
>+	desc = __get_process_desc(client);
>+	memset(desc, 0, sizeof(*desc));
>+}
>+
>+static int guc_stage_desc_pool_create(struct intel_guc *guc)
>+{
>+	struct i915_vma *vma;
>+	void *vaddr;
>+
>+	vma = intel_guc_allocate_vma(guc,
>+				     PAGE_ALIGN(sizeof(struct guc_stage_desc) *
>+				     GUC_MAX_STAGE_DESCRIPTORS));
>+	if (IS_ERR(vma))
>+		return PTR_ERR(vma);
>+
>+	vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
>+	if (IS_ERR(vaddr)) {
>+		i915_vma_unpin_and_release(&vma, 0);
>+		return PTR_ERR(vaddr);
>+	}
>+
>+	guc->stage_desc_pool = vma;
>+	guc->stage_desc_pool_vaddr = vaddr;
>+	ida_init(&guc->stage_ids);
>+
>+	return 0;
>+}
>+
>+static void guc_stage_desc_pool_destroy(struct intel_guc *guc)
>+{
>+	ida_destroy(&guc->stage_ids);
>+	i915_vma_unpin_and_release(&guc->stage_desc_pool, I915_VMA_RELEASE_MAP);
>+}
>+
>+/*
>+ * Initialise/clear the stage descriptor shared with the GuC firmware.
>+ *
>+ * This descriptor tells the GuC where (in GGTT space) to find the important
>+ * data structures relating to this client (doorbell, process descriptor,
>+ * write queue, etc).
>+ */
>+static void guc_stage_desc_init(struct intel_guc_client *client)
>+{
>+	struct intel_guc *guc = client->guc;
>+	struct guc_stage_desc *desc;
>+	u32 gfx_addr;
>+
>+	desc = __get_stage_desc(client);
>+	memset(desc, 0, sizeof(*desc));
>+
>+	desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE |
>+			  GUC_STAGE_DESC_ATTR_KERNEL;
>+	if (is_high_priority(client))
>+		desc->attribute |= GUC_STAGE_DESC_ATTR_PREEMPT;
>+	desc->stage_id = client->stage_id;
>+	desc->priority = client->priority;
>+	desc->db_id = client->doorbell_id;
>+
>+	/*
>+	 * The doorbell, process descriptor, and workqueue are all parts
>+	 * of the client object, which the GuC will reference via the GGTT
>+	 */
>+	gfx_addr = intel_guc_ggtt_offset(guc, client->vma);
>+	desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
>+				client->doorbell_offset;
>+	desc->db_trigger_cpu = ptr_to_u64(__get_doorbell(client));
>+	desc->db_trigger_uk = gfx_addr + client->doorbell_offset;
>+	desc->process_desc = gfx_addr + client->proc_desc_offset;
>+	desc->wq_addr = gfx_addr + GUC_DB_SIZE;
>+	desc->wq_size = GUC_WQ_SIZE;
>+
>+	desc->desc_private = ptr_to_u64(client);
>+}
>+
>+static void guc_stage_desc_fini(struct intel_guc_client *client)
>+{
>+	struct guc_stage_desc *desc;
>+
>+	desc = __get_stage_desc(client);
>+	memset(desc, 0, sizeof(*desc));
>+}
>+
>+/* Construct a Work Item and append it to the GuC's Work Queue */
>+static void guc_wq_item_append(struct intel_guc_client *client,
>+			       u32 target_engine, u32 context_desc,
>+			       u32 ring_tail, u32 fence_id)
>+{
>+	/* wqi_len is in DWords, and does not include the one-word header */
>+	const size_t wqi_size = sizeof(struct guc_wq_item);
>+	const u32 wqi_len = wqi_size / sizeof(u32) - 1;
>+	struct guc_process_desc *desc = __get_process_desc(client);
>+	struct guc_wq_item *wqi;
>+	u32 wq_off;
>+
>+	lockdep_assert_held(&client->wq_lock);
>+
>+	/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
>+	 * should not have the case where structure wqi is across page, neither
>+	 * wrapped to the beginning. This simplifies the implementation below.
>+	 *
>+	 * XXX: if not the case, we need save data to a temp wqi and copy it to
>+	 * workqueue buffer dw by dw.
>+	 */
>+	BUILD_BUG_ON(wqi_size != 16);
>+
>+	/* We expect the WQ to be active if we're appending items to it */
>+	GEM_BUG_ON(desc->wq_status != WQ_STATUS_ACTIVE);
>+
>+	/* Free space is guaranteed. */
>+	wq_off = READ_ONCE(desc->tail);
>+	GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
>+			      GUC_WQ_SIZE) < wqi_size);
>+	GEM_BUG_ON(wq_off & (wqi_size - 1));
>+
>+	/* WQ starts from the page after doorbell / process_desc */
>+	wqi = client->vaddr + wq_off + GUC_DB_SIZE;
>+
>+	if (I915_SELFTEST_ONLY(client->use_nop_wqi)) {
>+		wqi->header = WQ_TYPE_NOOP | (wqi_len << WQ_LEN_SHIFT);
>+	} else {
>+		/* Now fill in the 4-word work queue item */
>+		wqi->header = WQ_TYPE_INORDER |
>+			      (wqi_len << WQ_LEN_SHIFT) |
>+			      (target_engine << WQ_TARGET_SHIFT) |
>+			      WQ_NO_WCFLUSH_WAIT;
>+		wqi->context_desc = context_desc;
>+		wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
>+		GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
>+		wqi->fence_id = fence_id;
>+	}
>+
>+	/* Make the update visible to GuC */
>+	WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
>+}
>+
>+static void guc_ring_doorbell(struct intel_guc_client *client)
>+{
>+	struct guc_doorbell_info *db;
>+	u32 cookie;
>+
>+	lockdep_assert_held(&client->wq_lock);
>+
>+	/* pointer of current doorbell cacheline */
>+	db = __get_doorbell(client);
>+
>+	/*
>+	 * We're not expecting the doorbell cookie to change behind our back,
>+	 * we also need to treat 0 as a reserved value.
>+	 */
>+	cookie = READ_ONCE(db->cookie);
>+	WARN_ON_ONCE(xchg(&db->cookie, cookie + 1 ?: cookie + 2) != cookie);
>+
>+	/* XXX: doorbell was lost and need to acquire it again */
>+	GEM_BUG_ON(db->db_status != GUC_DOORBELL_ENABLED);
>+}
>+
>+static void guc_add_request(struct intel_guc *guc, struct i915_request *rq)
>+{
>+	struct intel_guc_client *client = guc->execbuf_client;
>+	struct intel_engine_cs *engine = rq->engine;
>+	u32 ctx_desc = lower_32_bits(rq->hw_context->lrc_desc);
>+	u32 ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
>+
>+	guc_wq_item_append(client, engine->guc_id, ctx_desc,
>+			   ring_tail, rq->fence.seqno);
>+	guc_ring_doorbell(client);
>+
>+	client->submissions[engine->id] += 1;
>+}
>+
>+/*
>+ * When we're doing submissions using regular execlists backend, writing to
>+ * ELSP from CPU side is enough to make sure that writes to ringbuffer pages
>+ * pinned in mappable aperture portion of GGTT are visible to command streamer.
>+ * Writes done by GuC on our behalf are not guaranteeing such ordering,
>+ * therefore, to ensure the flush, we're issuing a POSTING READ.
>+ */
>+static void flush_ggtt_writes(struct i915_vma *vma)
>+{
>+	struct drm_i915_private *i915 = vma->vm->i915;
>+
>+	if (i915_vma_is_map_and_fenceable(vma))
>+		intel_uncore_posting_read_fw(&i915->uncore, GUC_STATUS);
>+}
>+
>+static void guc_submit(struct intel_engine_cs *engine,
>+		       struct i915_request **out,
>+		       struct i915_request **end)
>+{
>+	struct intel_guc *guc = &engine->gt->uc.guc;
>+	struct intel_guc_client *client = guc->execbuf_client;
>+
>+	spin_lock(&client->wq_lock);
>+
>+	do {
>+		struct i915_request *rq = *out++;
>+
>+		flush_ggtt_writes(rq->ring->vma);
>+		guc_add_request(guc, rq);
>+	} while (out != end);
>+
>+	spin_unlock(&client->wq_lock);
>+}
>+
>+static inline int rq_prio(const struct i915_request *rq)
>+{
>+	return rq->sched.attr.priority | __NO_PREEMPTION;
>+}
>+
>+static struct i915_request *schedule_in(struct i915_request *rq, int idx)
>+{
>+	trace_i915_request_in(rq, idx);
>+
>+	if (!rq->hw_context->inflight)
>+		rq->hw_context->inflight = rq->engine;
>+	intel_context_inflight_inc(rq->hw_context);
>+
>+	return i915_request_get(rq);
>+}
>+
>+static void schedule_out(struct i915_request *rq)
>+{
>+	trace_i915_request_out(rq);
>+
>+	intel_context_inflight_dec(rq->hw_context);
>+	if (!intel_context_inflight_count(rq->hw_context))
>+		rq->hw_context->inflight = NULL;
>+
>+	i915_request_put(rq);
>+}
>+
>+static void __guc_dequeue(struct intel_engine_cs *engine)
>+{
>+	struct intel_engine_execlists * const execlists = &engine->execlists;
>+	struct i915_request **first = execlists->inflight;
>+	struct i915_request ** const last_port = first + execlists->port_mask;
>+	struct i915_request *last = first[0];
>+	struct i915_request **port;
>+	bool submit = false;
>+	struct rb_node *rb;
>+
>+	lockdep_assert_held(&engine->active.lock);
>+
>+	if (last) {
>+		if (*++first)
>+			return;
>+
>+		last = NULL;
>+	}
>+
>+	port = first;
>+	while ((rb = rb_first_cached(&execlists->queue))) {
>+		struct i915_priolist *p = to_priolist(rb);
>+		struct i915_request *rq, *rn;
>+		int i;
>+
>+		priolist_for_each_request_consume(rq, rn, p, i) {
>+			if (last && rq->hw_context != last->hw_context) {
>+				if (port == last_port)
>+					goto done;
>+
>+				*port = schedule_in(last,
>+						    port - execlists->inflight);
>+				port++;
>+			}
>+
>+			list_del_init(&rq->sched.link);
>+			__i915_request_submit(rq);
>+			submit = true;
>+			last = rq;
>+		}
>+
>+		rb_erase_cached(&p->node, &execlists->queue);
>+		i915_priolist_free(p);
>+	}
>+done:
>+	execlists->queue_priority_hint =
>+		rb ? to_priolist(rb)->priority : INT_MIN;
>+	if (submit) {
>+		*port = schedule_in(last, port - execlists->inflight);
>+		*++port = NULL;
>+		guc_submit(engine, first, port);
>+	}
>+	execlists->active = execlists->inflight;
>+}
>+
>+static void guc_submission_tasklet(unsigned long data)
>+{
>+	struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
>+	struct intel_engine_execlists * const execlists = &engine->execlists;
>+	struct i915_request **port, *rq;
>+	unsigned long flags;
>+
>+	spin_lock_irqsave(&engine->active.lock, flags);
>+
>+	for (port = execlists->inflight; (rq = *port); port++) {
>+		if (!i915_request_completed(rq))
>+			break;
>+
>+		schedule_out(rq);
>+	}
>+	if (port != execlists->inflight) {
>+		int idx = port - execlists->inflight;
>+		int rem = ARRAY_SIZE(execlists->inflight) - idx;
>+		memmove(execlists->inflight, port, rem * sizeof(*port));
>+	}
>+
>+	__guc_dequeue(engine);
>+
>+	spin_unlock_irqrestore(&engine->active.lock, flags);
>+}
>+
>+static void guc_reset_prepare(struct intel_engine_cs *engine)
>+{
>+	struct intel_engine_execlists * const execlists = &engine->execlists;
>+
>+	GEM_TRACE("%s\n", engine->name);
>+
>+	/*
>+	 * Prevent request submission to the hardware until we have
>+	 * completed the reset in i915_gem_reset_finish(). If a request
>+	 * is completed by one engine, it may then queue a request
>+	 * to a second via its execlists->tasklet *just* as we are
>+	 * calling engine->init_hw() and also writing the ELSP.
>+	 * Turning off the execlists->tasklet until the reset is over
>+	 * prevents the race.
>+	 */
>+	__tasklet_disable_sync_once(&execlists->tasklet);
>+}
>+
>+static void guc_reset(struct intel_engine_cs *engine, bool stalled)
>+{
>+	struct intel_engine_execlists * const execlists = &engine->execlists;
>+	struct i915_request *rq;
>+	unsigned long flags;
>+
>+	spin_lock_irqsave(&engine->active.lock, flags);
>+
>+	execlists_cancel_port_requests(execlists);
>+
>+	/* Push back any incomplete requests for replay after the reset. */
>+	rq = execlists_unwind_incomplete_requests(execlists);
>+	if (!rq)
>+		goto out_unlock;
>+
>+	if (!i915_request_started(rq))
>+		stalled = false;
>+
>+	__i915_request_reset(rq, stalled);
>+	intel_lr_context_reset(engine, rq->hw_context, rq->head, stalled);
>+
>+out_unlock:
>+	spin_unlock_irqrestore(&engine->active.lock, flags);
>+}
>+
>+static void guc_cancel_requests(struct intel_engine_cs *engine)
>+{
>+	struct intel_engine_execlists * const execlists = &engine->execlists;
>+	struct i915_request *rq, *rn;
>+	struct rb_node *rb;
>+	unsigned long flags;
>+
>+	GEM_TRACE("%s\n", engine->name);
>+
>+	/*
>+	 * Before we call engine->cancel_requests(), we should have exclusive
>+	 * access to the submission state. This is arranged for us by the
>+	 * caller disabling the interrupt generation, the tasklet and other
>+	 * threads that may then access the same state, giving us a free hand
>+	 * to reset state. However, we still need to let lockdep be aware that
>+	 * we know this state may be accessed in hardirq context, so we
>+	 * disable the irq around this manipulation and we want to keep
>+	 * the spinlock focused on its duties and not accidentally conflate
>+	 * coverage to the submission's irq state. (Similarly, although we
>+	 * shouldn't need to disable irq around the manipulation of the
>+	 * submission's irq state, we also wish to remind ourselves that
>+	 * it is irq state.)
>+	 */
>+	spin_lock_irqsave(&engine->active.lock, flags);
>+
>+	/* Cancel the requests on the HW and clear the ELSP tracker. */
>+	execlists_cancel_port_requests(execlists);
>+
>+	/* Mark all executing requests as skipped. */
>+	list_for_each_entry(rq, &engine->active.requests, sched.link) {
>+		if (!i915_request_signaled(rq))
>+			dma_fence_set_error(&rq->fence, -EIO);
>+
>+		i915_request_mark_complete(rq);
>+	}
>+
>+	/* Flush the queued requests to the timeline list (for retiring). */
>+	while ((rb = rb_first_cached(&execlists->queue))) {
>+		struct i915_priolist *p = to_priolist(rb);
>+		int i;
>+
>+		priolist_for_each_request_consume(rq, rn, p, i) {
>+			list_del_init(&rq->sched.link);
>+			__i915_request_submit(rq);
>+			dma_fence_set_error(&rq->fence, -EIO);
>+			i915_request_mark_complete(rq);
>+		}
>+
>+		rb_erase_cached(&p->node, &execlists->queue);
>+		i915_priolist_free(p);
>+	}
>+
>+	/* Remaining _unready_ requests will be nop'ed when submitted */
>+
>+	execlists->queue_priority_hint = INT_MIN;
>+	execlists->queue = RB_ROOT_CACHED;
>+
>+	spin_unlock_irqrestore(&engine->active.lock, flags);
>+}
>+
>+static void guc_reset_finish(struct intel_engine_cs *engine)
>+{
>+	struct intel_engine_execlists * const execlists = &engine->execlists;
>+
>+	if (__tasklet_enable(&execlists->tasklet))
>+		/* And kick in case we missed a new request submission. */
>+		tasklet_hi_schedule(&execlists->tasklet);
>+
>+	GEM_TRACE("%s: depth->%d\n", engine->name,
>+		  atomic_read(&execlists->tasklet.count));
>+}
>+
>+/*
>+ * Everything below here is concerned with setup & teardown, and is
>+ * therefore not part of the somewhat time-critical batch-submission
>+ * path of guc_submit() above.
>+ */
>+
>+/* Check that a doorbell register is in the expected state */
>+static bool doorbell_ok(struct intel_guc *guc, u16 db_id)
>+{
>+	bool valid;
>+
>+	GEM_BUG_ON(db_id >= GUC_NUM_DOORBELLS);
>+
>+	valid = __doorbell_valid(guc, db_id);
>+
>+	if (test_bit(db_id, guc->doorbell_bitmap) == valid)
>+		return true;
>+
>+	DRM_DEBUG_DRIVER("Doorbell %u has unexpected state: valid=%s\n",
>+			 db_id, yesno(valid));
>+
>+	return false;
>+}
>+
>+static bool guc_verify_doorbells(struct intel_guc *guc)
>+{
>+	bool doorbells_ok = true;
>+	u16 db_id;
>+
>+	for (db_id = 0; db_id < GUC_NUM_DOORBELLS; ++db_id)
>+		if (!doorbell_ok(guc, db_id))
>+			doorbells_ok = false;
>+
>+	return doorbells_ok;
>+}
>+
>+/**
>+ * guc_client_alloc() - Allocate an intel_guc_client
>+ * @guc:	the intel_guc structure
>+ * @priority:	four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
>+ *		The kernel client to replace ExecList submission is created with
>+ *		NORMAL priority. Priority of a client for scheduler can be HIGH,
>+ *		while a preemption context can use CRITICAL.
>+ *
>+ * Return:	An intel_guc_client object if success, else NULL.
>+ */
>+static struct intel_guc_client *
>+guc_client_alloc(struct intel_guc *guc, u32 priority)
>+{
>+	struct intel_guc_client *client;
>+	struct i915_vma *vma;
>+	void *vaddr;
>+	int ret;
>+
>+	client = kzalloc(sizeof(*client), GFP_KERNEL);
>+	if (!client)
>+		return ERR_PTR(-ENOMEM);
>+
>+	client->guc = guc;
>+	client->priority = priority;
>+	client->doorbell_id = GUC_DOORBELL_INVALID;
>+	spin_lock_init(&client->wq_lock);
>+
>+	ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS,
>+			     GFP_KERNEL);
>+	if (ret < 0)
>+		goto err_client;
>+
>+	client->stage_id = ret;
>+
>+	/* The first page is doorbell/proc_desc. Two followed pages are wq. */
>+	vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
>+	if (IS_ERR(vma)) {
>+		ret = PTR_ERR(vma);
>+		goto err_id;
>+	}
>+
>+	/* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
>+	client->vma = vma;
>+
>+	vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
>+	if (IS_ERR(vaddr)) {
>+		ret = PTR_ERR(vaddr);
>+		goto err_vma;
>+	}
>+	client->vaddr = vaddr;
>+
>+	ret = reserve_doorbell(client);
>+	if (ret)
>+		goto err_vaddr;
>+
>+	client->doorbell_offset = __select_cacheline(guc);
>+
>+	/*
>+	 * Since the doorbell only requires a single cacheline, we can save
>+	 * space by putting the application process descriptor in the same
>+	 * page. Use the half of the page that doesn't include the doorbell.
>+	 */
>+	if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
>+		client->proc_desc_offset = 0;
>+	else
>+		client->proc_desc_offset = (GUC_DB_SIZE / 2);
>+
>+	DRM_DEBUG_DRIVER("new priority %u client %p: stage_id %u\n",
>+			 priority, client, client->stage_id);
>+	DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%lx\n",
>+			 client->doorbell_id, client->doorbell_offset);
>+
>+	return client;
>+
>+err_vaddr:
>+	i915_gem_object_unpin_map(client->vma->obj);
>+err_vma:
>+	i915_vma_unpin_and_release(&client->vma, 0);
>+err_id:
>+	ida_simple_remove(&guc->stage_ids, client->stage_id);
>+err_client:
>+	kfree(client);
>+	return ERR_PTR(ret);
>+}
>+
>+static void guc_client_free(struct intel_guc_client *client)
>+{
>+	unreserve_doorbell(client);
>+	i915_vma_unpin_and_release(&client->vma, I915_VMA_RELEASE_MAP);
>+	ida_simple_remove(&client->guc->stage_ids, client->stage_id);
>+	kfree(client);
>+}
>+
>+static inline bool ctx_save_restore_disabled(struct intel_context *ce)
>+{
>+	u32 sr = ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1];
>+
>+#define SR_DISABLED \
>+	_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | \
>+			   CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT)
>+
>+	return (sr & SR_DISABLED) == SR_DISABLED;
>+
>+#undef SR_DISABLED
>+}
>+
>+static int guc_clients_create(struct intel_guc *guc)
>+{
>+	struct intel_guc_client *client;
>+
>+	GEM_BUG_ON(guc->execbuf_client);
>+
>+	client = guc_client_alloc(guc, GUC_CLIENT_PRIORITY_KMD_NORMAL);
>+	if (IS_ERR(client)) {
>+		DRM_ERROR("Failed to create GuC client for submission!\n");
>+		return PTR_ERR(client);
>+	}
>+	guc->execbuf_client = client;
>+
>+	return 0;
>+}
>+
>+static void guc_clients_destroy(struct intel_guc *guc)
>+{
>+	struct intel_guc_client *client;
>+
>+	client = fetch_and_zero(&guc->execbuf_client);
>+	if (client)
>+		guc_client_free(client);
>+}
>+
>+static int __guc_client_enable(struct intel_guc_client *client)
>+{
>+	int ret;
>+
>+	guc_proc_desc_init(client);
>+	guc_stage_desc_init(client);
>+
>+	ret = create_doorbell(client);
>+	if (ret)
>+		goto fail;
>+
>+	return 0;
>+
>+fail:
>+	guc_stage_desc_fini(client);
>+	guc_proc_desc_fini(client);
>+	return ret;
>+}
>+
>+static void __guc_client_disable(struct intel_guc_client *client)
>+{
>+	/*
>+	 * By the time we're here, GuC may have already been reset. if that is
>+	 * the case, instead of trying (in vain) to communicate with it, let's
>+	 * just cleanup the doorbell HW and our internal state.
>+	 */
>+	if (intel_guc_is_running(client->guc))
>+		destroy_doorbell(client);
>+	else
>+		__fini_doorbell(client);
>+
>+	guc_stage_desc_fini(client);
>+	guc_proc_desc_fini(client);
>+}
>+
>+static int guc_clients_enable(struct intel_guc *guc)
>+{
>+	return __guc_client_enable(guc->execbuf_client);
>+}
>+
>+static void guc_clients_disable(struct intel_guc *guc)
>+{
>+	if (guc->execbuf_client)
>+		__guc_client_disable(guc->execbuf_client);
>+}
>+
>+/*
>+ * Set up the memory resources to be shared with the GuC (via the GGTT)
>+ * at firmware loading time.
>+ */
>+int intel_guc_submission_init(struct intel_guc *guc)
>+{
>+	int ret;
>+
>+	if (guc->stage_desc_pool)
>+		return 0;
>+
>+	ret = guc_stage_desc_pool_create(guc);
>+	if (ret)
>+		return ret;
>+	/*
>+	 * Keep static analysers happy, let them know that we allocated the
>+	 * vma after testing that it didn't exist earlier.
>+	 */
>+	GEM_BUG_ON(!guc->stage_desc_pool);
>+
>+	WARN_ON(!guc_verify_doorbells(guc));
>+	ret = guc_clients_create(guc);
>+	if (ret)
>+		goto err_pool;
>+
>+	return 0;
>+
>+err_pool:
>+	guc_stage_desc_pool_destroy(guc);
>+	return ret;
>+}
>+
>+void intel_guc_submission_fini(struct intel_guc *guc)
>+{
>+	guc_clients_destroy(guc);
>+	WARN_ON(!guc_verify_doorbells(guc));
>+
>+	if (guc->stage_desc_pool)
>+		guc_stage_desc_pool_destroy(guc);
>+}
>+
>+static void guc_interrupts_capture(struct intel_gt *gt)
>+{
>+	struct intel_rps *rps = &gt->i915->gt_pm.rps;
>+	struct intel_uncore *uncore = gt->uncore;
>+	struct intel_engine_cs *engine;
>+	enum intel_engine_id id;
>+	int irqs;
>+
>+	/* tell all command streamers to forward interrupts (but not vblank)
>+	 * to GuC
>+	 */
>+	irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
>+	for_each_engine(engine, gt->i915, id)
>+		ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
>+
>+	/* route USER_INTERRUPT to Host, all others are sent to GuC. */
>+	irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
>+	       GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
>+	/* These three registers have the same bit definitions */
>+	intel_uncore_write(uncore, GUC_BCS_RCS_IER, ~irqs);
>+	intel_uncore_write(uncore, GUC_VCS2_VCS1_IER, ~irqs);
>+	intel_uncore_write(uncore, GUC_WD_VECS_IER, ~irqs);
>+
>+	/*
>+	 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
>+	 * (unmasked) PM interrupts to the GuC. All other bits of this
>+	 * register *disable* generation of a specific interrupt.
>+	 *
>+	 * 'pm_intrmsk_mbz' indicates bits that are NOT to be set when
>+	 * writing to the PM interrupt mask register, i.e. interrupts
>+	 * that must not be disabled.
>+	 *
>+	 * If the GuC is handling these interrupts, then we must not let
>+	 * the PM code disable ANY interrupt that the GuC is expecting.
>+	 * So for each ENABLED (0) bit in this register, we must SET the
>+	 * bit in pm_intrmsk_mbz so that it's left enabled for the GuC.
>+	 * GuC needs ARAT expired interrupt unmasked hence it is set in
>+	 * pm_intrmsk_mbz.
>+	 *
>+	 * Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will
>+	 * result in the register bit being left SET!
>+	 */
>+	rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
>+	rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
>+}
>+
>+static void guc_interrupts_release(struct intel_gt *gt)
>+{
>+	struct intel_rps *rps = &gt->i915->gt_pm.rps;
>+	struct intel_uncore *uncore = gt->uncore;
>+	struct intel_engine_cs *engine;
>+	enum intel_engine_id id;
>+	int irqs;
>+
>+	/*
>+	 * tell all command streamers NOT to forward interrupts or vblank
>+	 * to GuC.
>+	 */
>+	irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
>+	irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
>+	for_each_engine(engine, gt->i915, id)
>+		ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
>+
>+	/* route all GT interrupts to the host */
>+	intel_uncore_write(uncore, GUC_BCS_RCS_IER, 0);
>+	intel_uncore_write(uncore, GUC_VCS2_VCS1_IER, 0);
>+	intel_uncore_write(uncore, GUC_WD_VECS_IER, 0);
>+
>+	rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
>+	rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
>+}
>+
>+static void guc_submission_park(struct intel_engine_cs *engine)
>+{
>+	intel_engine_park(engine);
>+	intel_engine_unpin_breadcrumbs_irq(engine);
>+	engine->flags &= ~I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
>+}
>+
>+static void guc_submission_unpark(struct intel_engine_cs *engine)
>+{
>+	engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
>+	intel_engine_pin_breadcrumbs_irq(engine);
>+}
>+
>+static void guc_set_default_submission(struct intel_engine_cs *engine)
>+{
>+	/*
>+	 * We inherit a bunch of functions from execlists that we'd like
>+	 * to keep using:
>+	 *
>+	 *    engine->submit_request = execlists_submit_request;
>+	 *    engine->cancel_requests = execlists_cancel_requests;
>+	 *    engine->schedule = execlists_schedule;
>+	 *
>+	 * But we need to override the actual submission backend in order
>+	 * to talk to the GuC.
>+	 */
>+	intel_execlists_set_default_submission(engine);
>+
>+	engine->execlists.tasklet.func = guc_submission_tasklet;
>+
>+	engine->park = guc_submission_park;
>+	engine->unpark = guc_submission_unpark;
>+
>+	engine->reset.prepare = guc_reset_prepare;
>+	engine->reset.reset = guc_reset;
>+	engine->reset.finish = guc_reset_finish;
>+
>+	engine->cancel_requests = guc_cancel_requests;
>+
>+	engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
>+}
>+
>+int intel_guc_submission_enable(struct intel_guc *guc)
>+{
>+	struct intel_gt *gt = guc_to_gt(guc);
>+	struct intel_engine_cs *engine;
>+	enum intel_engine_id id;
>+	int err;
>+
>+	/*
>+	 * We're using GuC work items for submitting work through GuC. Since
>+	 * we're coalescing multiple requests from a single context into a
>+	 * single work item prior to assigning it to execlist_port, we can
>+	 * never have more work items than the total number of ports (for all
>+	 * engines). The GuC firmware is controlling the HEAD of work queue,
>+	 * and it is guaranteed that it will remove the work item from the
>+	 * queue before our request is completed.
>+	 */
>+	BUILD_BUG_ON(ARRAY_SIZE(engine->execlists.inflight) *
>+		     sizeof(struct guc_wq_item) *
>+		     I915_NUM_ENGINES > GUC_WQ_SIZE);
>+
>+	GEM_BUG_ON(!guc->execbuf_client);
>+
>+	err = guc_clients_enable(guc);
>+	if (err)
>+		return err;
>+
>+	/* Take over from manual control of ELSP (execlists) */
>+	guc_interrupts_capture(gt);
>+
>+	for_each_engine(engine, gt->i915, id) {
>+		engine->set_default_submission = guc_set_default_submission;
>+		engine->set_default_submission(engine);
>+	}
>+
>+	return 0;
>+}
>+
>+void intel_guc_submission_disable(struct intel_guc *guc)
>+{
>+	struct intel_gt *gt = guc_to_gt(guc);
>+
>+	GEM_BUG_ON(gt->awake); /* GT should be parked first */
>+
>+	guc_interrupts_release(gt);
>+	guc_clients_disable(guc);
>+}
>+
>+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
>+#include "selftest_guc.c"
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h	2019-08-31 15:01:12.240736202 -0500
>@@ -0,0 +1,87 @@
>+/*
>+ * Copyright Â© 2014-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef _INTEL_GUC_SUBMISSION_H_
>+#define _INTEL_GUC_SUBMISSION_H_
>+
>+#include <linux/spinlock.h>
>+
>+#include "gt/intel_engine_types.h"
>+
>+#include "i915_gem.h"
>+#include "i915_selftest.h"
>+
>+struct drm_i915_private;
>+
>+/*
>+ * This structure primarily describes the GEM object shared with the GuC.
>+ * The specs sometimes refer to this object as a "GuC context", but we use
>+ * the term "client" to avoid confusion with hardware contexts. This
>+ * GEM object is held for the entire lifetime of our interaction with
>+ * the GuC, being allocated before the GuC is loaded with its firmware.
>+ * Because there's no way to update the address used by the GuC after
>+ * initialisation, the shared object must stay pinned into the GGTT as
>+ * long as the GuC is in use. We also keep the first page (only) mapped
>+ * into kernel address space, as it includes shared data that must be
>+ * updated on every request submission.
>+ *
>+ * The single GEM object described here is actually made up of several
>+ * separate areas, as far as the GuC is concerned. The first page (kept
>+ * kmap'd) includes the "process descriptor" which holds sequence data for
>+ * the doorbell, and one cacheline which actually *is* the doorbell; a
>+ * write to this will "ring the doorbell" (i.e. send an interrupt to the
>+ * GuC). The subsequent  pages of the client object constitute the work
>+ * queue (a circular array of work items), again described in the process
>+ * descriptor. Work queue pages are mapped momentarily as required.
>+ */
>+struct intel_guc_client {
>+	struct i915_vma *vma;
>+	void *vaddr;
>+	struct intel_guc *guc;
>+
>+	/* bitmap of (host) engine ids */
>+	u32 priority;
>+	u32 stage_id;
>+	u32 proc_desc_offset;
>+
>+	u16 doorbell_id;
>+	unsigned long doorbell_offset;
>+
>+	/* Protects GuC client's WQ access */
>+	spinlock_t wq_lock;
>+	/* Per-engine counts of GuC submissions */
>+	u64 submissions[I915_NUM_ENGINES];
>+
>+	/* For testing purposes, use nop WQ items instead of real ones */
>+	I915_SELFTEST_DECLARE(bool use_nop_wqi);
>+};
>+
>+int intel_guc_submission_init(struct intel_guc *guc);
>+int intel_guc_submission_enable(struct intel_guc *guc);
>+void intel_guc_submission_disable(struct intel_guc *guc);
>+void intel_guc_submission_fini(struct intel_guc *guc);
>+int intel_guc_preempt_work_create(struct intel_guc *guc);
>+void intel_guc_preempt_work_destroy(struct intel_guc *guc);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_huc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_huc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_huc.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_huc.c	2019-08-31 15:01:12.240736202 -0500
>@@ -0,0 +1,195 @@
>+/*
>+ * Copyright Â© 2016-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include <linux/types.h>
>+
>+#include "gt/intel_gt.h"
>+#include "intel_huc.h"
>+#include "i915_drv.h"
>+
>+void intel_huc_init_early(struct intel_huc *huc)
>+{
>+	struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
>+
>+	intel_huc_fw_init_early(huc);
>+
>+	if (INTEL_GEN(i915) >= 11) {
>+		huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
>+		huc->status.mask = HUC_LOAD_SUCCESSFUL;
>+		huc->status.value = HUC_LOAD_SUCCESSFUL;
>+	} else {
>+		huc->status.reg = HUC_STATUS2;
>+		huc->status.mask = HUC_FW_VERIFIED;
>+		huc->status.value = HUC_FW_VERIFIED;
>+	}
>+}
>+
>+static int intel_huc_rsa_data_create(struct intel_huc *huc)
>+{
>+	struct intel_gt *gt = huc_to_gt(huc);
>+	struct intel_guc *guc = &gt->uc.guc;
>+	struct i915_vma *vma;
>+	size_t copied;
>+	void *vaddr;
>+
>+	/*
>+	 * HuC firmware will sit above GUC_GGTT_TOP and will not map
>+	 * through GTT. Unfortunately, this means GuC cannot perform
>+	 * the HuC auth. as the rsa offset now falls within the GuC
>+	 * inaccessible range. We resort to perma-pinning an additional
>+	 * vma within the accessible range that only contains the rsa
>+	 * signature. The GuC can use this extra pinning to perform
>+	 * the authentication since its GGTT offset will be GuC
>+	 * accessible.
>+	 */
>+	GEM_BUG_ON(huc->fw.rsa_size > PAGE_SIZE);
>+	vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
>+	if (IS_ERR(vma))
>+		return PTR_ERR(vma);
>+
>+	vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
>+	if (IS_ERR(vaddr)) {
>+		i915_vma_unpin_and_release(&vma, 0);
>+		return PTR_ERR(vaddr);
>+	}
>+
>+	copied = intel_uc_fw_copy_rsa(&huc->fw, vaddr, vma->size);
>+	GEM_BUG_ON(copied < huc->fw.rsa_size);
>+
>+	i915_gem_object_unpin_map(vma->obj);
>+
>+	huc->rsa_data = vma;
>+
>+	return 0;
>+}
>+
>+static void intel_huc_rsa_data_destroy(struct intel_huc *huc)
>+{
>+	i915_vma_unpin_and_release(&huc->rsa_data, 0);
>+}
>+
>+int intel_huc_init(struct intel_huc *huc)
>+{
>+	int err;
>+
>+	err = intel_uc_fw_init(&huc->fw);
>+	if (err)
>+		return err;
>+
>+	/*
>+	 * HuC firmware image is outside GuC accessible range.
>+	 * Copy the RSA signature out of the image into
>+	 * a perma-pinned region set aside for it
>+	 */
>+	err = intel_huc_rsa_data_create(huc);
>+	if (err)
>+		goto out_fini;
>+
>+	return 0;
>+
>+out_fini:
>+	intel_uc_fw_fini(&huc->fw);
>+	return err;
>+}
>+
>+void intel_huc_fini(struct intel_huc *huc)
>+{
>+	intel_uc_fw_fini(&huc->fw);
>+	intel_huc_rsa_data_destroy(huc);
>+}
>+
>+/**
>+ * intel_huc_auth() - Authenticate HuC uCode
>+ * @huc: intel_huc structure
>+ *
>+ * Called after HuC and GuC firmware loading during intel_uc_init_hw().
>+ *
>+ * This function pins HuC firmware image object into GGTT.
>+ * Then it invokes GuC action to authenticate passing the offset to RSA
>+ * signature through intel_guc_auth_huc(). It then waits for 50ms for
>+ * firmware verification ACK and unpins the object.
>+ */
>+int intel_huc_auth(struct intel_huc *huc)
>+{
>+	struct intel_gt *gt = huc_to_gt(huc);
>+	struct intel_guc *guc = &gt->uc.guc;
>+	int ret;
>+
>+	GEM_BUG_ON(!intel_uc_fw_is_loaded(&huc->fw));
>+	GEM_BUG_ON(intel_huc_is_authenticated(huc));
>+
>+	ret = intel_guc_auth_huc(guc,
>+				 intel_guc_ggtt_offset(guc, huc->rsa_data));
>+	if (ret) {
>+		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
>+		goto fail;
>+	}
>+
>+	/* Check authentication status, it should be done by now */
>+	ret = __intel_wait_for_register(gt->uncore,
>+					huc->status.reg,
>+					huc->status.mask,
>+					huc->status.value,
>+					2, 50, NULL);
>+	if (ret) {
>+		DRM_ERROR("HuC: Firmware not verified %d\n", ret);
>+		goto fail;
>+	}
>+
>+	huc->fw.status = INTEL_UC_FIRMWARE_RUNNING;
>+
>+	return 0;
>+
>+fail:
>+	huc->fw.status = INTEL_UC_FIRMWARE_FAIL;
>+
>+	DRM_ERROR("HuC: Authentication failed %d\n", ret);
>+	return ret;
>+}
>+
>+/**
>+ * intel_huc_check_status() - check HuC status
>+ * @huc: intel_huc structure
>+ *
>+ * This function reads status register to verify if HuC
>+ * firmware was successfully loaded.
>+ *
>+ * Returns: 1 if HuC firmware is loaded and verified,
>+ * 0 if HuC firmware is not loaded and -ENODEV if HuC
>+ * is not present on this platform.
>+ */
>+int intel_huc_check_status(struct intel_huc *huc)
>+{
>+	struct intel_gt *gt = huc_to_gt(huc);
>+	intel_wakeref_t wakeref;
>+	u32 status = 0;
>+
>+	if (!intel_uc_is_using_huc(&gt->uc))
>+		return -ENODEV;
>+
>+	with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref)
>+		status = intel_uncore_read(gt->uncore, huc->status.reg);
>+
>+	return (status & huc->status.mask) == huc->status.value;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c	2019-08-31 15:01:12.029736183 -0500
>@@ -0,0 +1,53 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2014-2018 Intel Corporation
>+ */
>+
>+#include "gt/intel_gt.h"
>+#include "intel_huc_fw.h"
>+#include "i915_drv.h"
>+
>+/**
>+ * DOC: HuC Firmware
>+ *
>+ * Motivation:
>+ * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
>+ * Efficiency Video Coding) operations. Userspace can use the firmware
>+ * capabilities by adding HuC specific commands to batch buffers.
>+ *
>+ * Implementation:
>+ * The same firmware loader is used as the GuC. However, the actual
>+ * loading to HW is deferred until GEM initialization is done.
>+ *
>+ * Note that HuC firmware loading must be done before GuC loading.
>+ */
>+
>+/**
>+ * intel_huc_fw_init_early() - initializes HuC firmware struct
>+ * @huc: intel_huc struct
>+ *
>+ * On platforms with HuC selects firmware for uploading
>+ */
>+void intel_huc_fw_init_early(struct intel_huc *huc)
>+{
>+	intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC, huc_to_gt(huc)->i915);
>+}
>+
>+/**
>+ * intel_huc_fw_upload() - load HuC uCode to device
>+ * @huc: intel_huc structure
>+ *
>+ * Called from intel_uc_init_hw() during driver load, resume from sleep and
>+ * after a GPU reset. Note that HuC must be loaded before GuC.
>+ *
>+ * The firmware image should have already been fetched into memory, so only
>+ * check that fetch succeeded, and then transfer the image to the h/w.
>+ *
>+ * Return:	non-zero code on error
>+ */
>+int intel_huc_fw_upload(struct intel_huc *huc)
>+{
>+	/* HW doesn't look at destination address for HuC, so set it to 0 */
>+	return intel_uc_fw_upload(&huc->fw, huc_to_gt(huc), 0, HUC_UKERNEL);
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h	2019-08-31 15:01:12.240736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2014-2018 Intel Corporation
>+ */
>+
>+#ifndef _INTEL_HUC_FW_H_
>+#define _INTEL_HUC_FW_H_
>+
>+struct intel_huc;
>+
>+void intel_huc_fw_init_early(struct intel_huc *huc);
>+int intel_huc_fw_upload(struct intel_huc *huc);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_huc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_huc.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_huc.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_huc.h	2019-08-31 15:01:12.240736202 -0500
>@@ -0,0 +1,63 @@
>+/*
>+ * Copyright Â© 2014-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef _INTEL_HUC_H_
>+#define _INTEL_HUC_H_
>+
>+#include "i915_reg.h"
>+#include "intel_uc_fw.h"
>+#include "intel_huc_fw.h"
>+
>+struct intel_huc {
>+	/* Generic uC firmware management */
>+	struct intel_uc_fw fw;
>+
>+	/* HuC-specific additions */
>+	struct i915_vma *rsa_data;
>+
>+	struct {
>+		i915_reg_t reg;
>+		u32 mask;
>+		u32 value;
>+	} status;
>+};
>+
>+void intel_huc_init_early(struct intel_huc *huc);
>+int intel_huc_init(struct intel_huc *huc);
>+void intel_huc_fini(struct intel_huc *huc);
>+int intel_huc_auth(struct intel_huc *huc);
>+int intel_huc_check_status(struct intel_huc *huc);
>+
>+static inline int intel_huc_sanitize(struct intel_huc *huc)
>+{
>+	intel_uc_fw_sanitize(&huc->fw);
>+	return 0;
>+}
>+
>+static inline bool intel_huc_is_authenticated(struct intel_huc *huc)
>+{
>+	return intel_uc_fw_is_running(&huc->fw);
>+}
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_uc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_uc.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_uc.c	2019-08-31 15:01:12.030736183 -0500
>@@ -0,0 +1,570 @@
>+/*
>+ * Copyright Â© 2016 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include "gt/intel_gt.h"
>+#include "gt/intel_reset.h"
>+#include "intel_guc.h"
>+#include "intel_guc_ads.h"
>+#include "intel_guc_submission.h"
>+#include "intel_uc.h"
>+
>+#include "i915_drv.h"
>+
>+static void guc_free_load_err_log(struct intel_guc *guc);
>+
>+/* Reset GuC providing us with fresh state for both GuC and HuC.
>+ */
>+static int __intel_uc_reset_hw(struct intel_uc *uc)
>+{
>+	struct intel_gt *gt = uc_to_gt(uc);
>+	int ret;
>+	u32 guc_status;
>+
>+	ret = intel_reset_guc(gt);
>+	if (ret) {
>+		DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
>+		return ret;
>+	}
>+
>+	guc_status = intel_uncore_read(gt->uncore, GUC_STATUS);
>+	WARN(!(guc_status & GS_MIA_IN_RESET),
>+	     "GuC status: 0x%x, MIA core expected to be in reset\n",
>+	     guc_status);
>+
>+	return ret;
>+}
>+
>+static int __get_platform_enable_guc(struct intel_uc *uc)
>+{
>+	struct intel_uc_fw *guc_fw = &uc->guc.fw;
>+	struct intel_uc_fw *huc_fw = &uc->huc.fw;
>+	int enable_guc = 0;
>+
>+	if (!HAS_GT_UC(uc_to_gt(uc)->i915))
>+		return 0;
>+
>+	/* We don't want to enable GuC/HuC on pre-Gen11 by default */
>+	if (INTEL_GEN(uc_to_gt(uc)->i915) < 11)
>+		return 0;
>+
>+	if (intel_uc_fw_supported(guc_fw) && intel_uc_fw_supported(huc_fw))
>+		enable_guc |= ENABLE_GUC_LOAD_HUC;
>+
>+	return enable_guc;
>+}
>+
>+/**
>+ * sanitize_options_early - sanitize uC related modparam options
>+ * @uc: the intel_uc structure
>+ *
>+ * In case of "enable_guc" option this function will attempt to modify
>+ * it only if it was initially set to "auto(-1)". Default value for this
>+ * modparam varies between platforms and it is hardcoded in driver code.
>+ * Any other modparam value is only monitored against availability of the
>+ * related hardware or firmware definitions.
>+ */
>+static void sanitize_options_early(struct intel_uc *uc)
>+{
>+	struct intel_uc_fw *guc_fw = &uc->guc.fw;
>+	struct intel_uc_fw *huc_fw = &uc->huc.fw;
>+
>+	/* A negative value means "use platform default" */
>+	if (i915_modparams.enable_guc < 0)
>+		i915_modparams.enable_guc = __get_platform_enable_guc(uc);
>+
>+	DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
>+			 i915_modparams.enable_guc,
>+			 yesno(intel_uc_is_using_guc_submission(uc)),
>+			 yesno(intel_uc_is_using_huc(uc)));
>+
>+	/* Verify GuC firmware availability */
>+	if (intel_uc_is_using_guc(uc) && !intel_uc_fw_supported(guc_fw)) {
>+		DRM_WARN("Incompatible option detected: enable_guc=%d, "
>+			 "but GuC is not supported!\n",
>+			 i915_modparams.enable_guc);
>+		DRM_INFO("Disabling GuC/HuC loading!\n");
>+		i915_modparams.enable_guc = 0;
>+	}
>+
>+	/* Verify HuC firmware availability */
>+	if (intel_uc_is_using_huc(uc) && !intel_uc_fw_supported(huc_fw)) {
>+		DRM_WARN("Incompatible option detected: enable_guc=%d, "
>+			 "but HuC is not supported!\n",
>+			 i915_modparams.enable_guc);
>+		DRM_INFO("Disabling HuC loading!\n");
>+		i915_modparams.enable_guc &= ~ENABLE_GUC_LOAD_HUC;
>+	}
>+
>+	/* XXX: GuC submission is unavailable for now */
>+	if (intel_uc_is_using_guc_submission(uc)) {
>+		DRM_INFO("Incompatible option detected: enable_guc=%d, "
>+			 "but GuC submission is not supported!\n",
>+			 i915_modparams.enable_guc);
>+		DRM_INFO("Switching to non-GuC submission mode!\n");
>+		i915_modparams.enable_guc &= ~ENABLE_GUC_SUBMISSION;
>+	}
>+
>+	/* Make sure that sanitization was done */
>+	GEM_BUG_ON(i915_modparams.enable_guc < 0);
>+}
>+
>+void intel_uc_init_early(struct intel_uc *uc)
>+{
>+	intel_guc_init_early(&uc->guc);
>+	intel_huc_init_early(&uc->huc);
>+
>+	sanitize_options_early(uc);
>+}
>+
>+void intel_uc_cleanup_early(struct intel_uc *uc)
>+{
>+	guc_free_load_err_log(&uc->guc);
>+}
>+
>+/**
>+ * intel_uc_init_mmio - setup uC MMIO access
>+ * @uc: the intel_uc structure
>+ *
>+ * Setup minimal state necessary for MMIO accesses later in the
>+ * initialization sequence.
>+ */
>+void intel_uc_init_mmio(struct intel_uc *uc)
>+{
>+	intel_guc_init_send_regs(&uc->guc);
>+}
>+
>+static void guc_capture_load_err_log(struct intel_guc *guc)
>+{
>+	if (!guc->log.vma || !intel_guc_log_get_level(&guc->log))
>+		return;
>+
>+	if (!guc->load_err_log)
>+		guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
>+
>+	return;
>+}
>+
>+static void guc_free_load_err_log(struct intel_guc *guc)
>+{
>+	if (guc->load_err_log)
>+		i915_gem_object_put(guc->load_err_log);
>+}
>+
>+/*
>+ * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
>+ * register using the same bits used in the CT message payload. Since our
>+ * communication channel with guc is turned off at this point, we can save the
>+ * message and handle it after we turn it back on.
>+ */
>+static void guc_clear_mmio_msg(struct intel_guc *guc)
>+{
>+	intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0);
>+}
>+
>+static void guc_get_mmio_msg(struct intel_guc *guc)
>+{
>+	u32 val;
>+
>+	spin_lock_irq(&guc->irq_lock);
>+
>+	val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
>+	guc->mmio_msg |= val & guc->msg_enabled_mask;
>+
>+	/*
>+	 * clear all events, including the ones we're not currently servicing,
>+	 * to make sure we don't try to process a stale message if we enable
>+	 * handling of more events later.
>+	 */
>+	guc_clear_mmio_msg(guc);
>+
>+	spin_unlock_irq(&guc->irq_lock);
>+}
>+
>+static void guc_handle_mmio_msg(struct intel_guc *guc)
>+{
>+	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>+
>+	/* we need communication to be enabled to reply to GuC */
>+	GEM_BUG_ON(guc->handler == intel_guc_to_host_event_handler_nop);
>+
>+	if (!guc->mmio_msg)
>+		return;
>+
>+	spin_lock_irq(&i915->irq_lock);
>+	intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
>+	spin_unlock_irq(&i915->irq_lock);
>+
>+	guc->mmio_msg = 0;
>+}
>+
>+static void guc_reset_interrupts(struct intel_guc *guc)
>+{
>+	guc->interrupts.reset(guc);
>+}
>+
>+static void guc_enable_interrupts(struct intel_guc *guc)
>+{
>+	guc->interrupts.enable(guc);
>+}
>+
>+static void guc_disable_interrupts(struct intel_guc *guc)
>+{
>+	guc->interrupts.disable(guc);
>+}
>+
>+static int guc_enable_communication(struct intel_guc *guc)
>+{
>+	struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
>+	int ret;
>+
>+	ret = intel_guc_ct_enable(&guc->ct);
>+	if (ret)
>+		return ret;
>+
>+	guc->send = intel_guc_send_ct;
>+	guc->handler = intel_guc_to_host_event_handler_ct;
>+
>+	/* check for mmio messages received before/during the CT enable */
>+	guc_get_mmio_msg(guc);
>+	guc_handle_mmio_msg(guc);
>+
>+	guc_enable_interrupts(guc);
>+
>+	/* check for CT messages received before we enabled interrupts */
>+	spin_lock_irq(&i915->irq_lock);
>+	intel_guc_to_host_event_handler_ct(guc);
>+	spin_unlock_irq(&i915->irq_lock);
>+
>+	DRM_INFO("GuC communication enabled\n");
>+
>+	return 0;
>+}
>+
>+static void guc_stop_communication(struct intel_guc *guc)
>+{
>+	intel_guc_ct_stop(&guc->ct);
>+
>+	guc->send = intel_guc_send_nop;
>+	guc->handler = intel_guc_to_host_event_handler_nop;
>+
>+	guc_clear_mmio_msg(guc);
>+}
>+
>+static void guc_disable_communication(struct intel_guc *guc)
>+{
>+	/*
>+	 * Events generated during or after CT disable are logged by guc in
>+	 * via mmio. Make sure the register is clear before disabling CT since
>+	 * all events we cared about have already been processed via CT.
>+	 */
>+	guc_clear_mmio_msg(guc);
>+
>+	guc_disable_interrupts(guc);
>+
>+	guc->send = intel_guc_send_nop;
>+	guc->handler = intel_guc_to_host_event_handler_nop;
>+
>+	intel_guc_ct_disable(&guc->ct);
>+
>+	/*
>+	 * Check for messages received during/after the CT disable. We do not
>+	 * expect any messages to have arrived via CT between the interrupt
>+	 * disable and the CT disable because GuC should've been idle until we
>+	 * triggered the CT disable protocol.
>+	 */
>+	guc_get_mmio_msg(guc);
>+
>+	DRM_INFO("GuC communication disabled\n");
>+}
>+
>+void intel_uc_fetch_firmwares(struct intel_uc *uc)
>+{
>+	struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
>+
>+	if (!intel_uc_is_using_guc(uc))
>+		return;
>+
>+	intel_uc_fw_fetch(&uc->guc.fw, i915);
>+
>+	if (intel_uc_is_using_huc(uc))
>+		intel_uc_fw_fetch(&uc->huc.fw, i915);
>+}
>+
>+void intel_uc_cleanup_firmwares(struct intel_uc *uc)
>+{
>+	if (!intel_uc_is_using_guc(uc))
>+		return;
>+
>+	if (intel_uc_is_using_huc(uc))
>+		intel_uc_fw_cleanup_fetch(&uc->huc.fw);
>+
>+	intel_uc_fw_cleanup_fetch(&uc->guc.fw);
>+}
>+
>+int intel_uc_init(struct intel_uc *uc)
>+{
>+	struct intel_guc *guc = &uc->guc;
>+	struct intel_huc *huc = &uc->huc;
>+	int ret;
>+
>+	if (!intel_uc_is_using_guc(uc))
>+		return 0;
>+
>+	if (!intel_uc_fw_supported(&guc->fw))
>+		return -ENODEV;
>+
>+	/* XXX: GuC submission is unavailable for now */
>+	GEM_BUG_ON(intel_uc_is_using_guc_submission(uc));
>+
>+	ret = intel_guc_init(guc);
>+	if (ret)
>+		return ret;
>+
>+	if (intel_uc_is_using_huc(uc)) {
>+		ret = intel_huc_init(huc);
>+		if (ret)
>+			goto err_guc;
>+	}
>+
>+	return 0;
>+
>+err_guc:
>+	intel_guc_fini(guc);
>+	return ret;
>+}
>+
>+void intel_uc_fini(struct intel_uc *uc)
>+{
>+	struct intel_guc *guc = &uc->guc;
>+
>+	if (!intel_uc_is_using_guc(uc))
>+		return;
>+
>+	GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
>+
>+	if (intel_uc_is_using_huc(uc))
>+		intel_huc_fini(&uc->huc);
>+
>+	intel_guc_fini(guc);
>+}
>+
>+static void __uc_sanitize(struct intel_uc *uc)
>+{
>+	struct intel_guc *guc = &uc->guc;
>+	struct intel_huc *huc = &uc->huc;
>+
>+	GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
>+
>+	intel_huc_sanitize(huc);
>+	intel_guc_sanitize(guc);
>+
>+	__intel_uc_reset_hw(uc);
>+}
>+
>+void intel_uc_sanitize(struct intel_uc *uc)
>+{
>+	if (!intel_uc_is_using_guc(uc))
>+		return;
>+
>+	__uc_sanitize(uc);
>+}
>+
>+int intel_uc_init_hw(struct intel_uc *uc)
>+{
>+	struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
>+	struct intel_guc *guc = &uc->guc;
>+	struct intel_huc *huc = &uc->huc;
>+	int ret, attempts;
>+
>+	if (!intel_uc_is_using_guc(uc))
>+		return 0;
>+
>+	GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
>+
>+	guc_reset_interrupts(guc);
>+
>+	/* WaEnableuKernelHeaderValidFix:skl */
>+	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
>+	if (IS_GEN(i915, 9))
>+		attempts = 3;
>+	else
>+		attempts = 1;
>+
>+	while (attempts--) {
>+		/*
>+		 * Always reset the GuC just before (re)loading, so
>+		 * that the state and timing are fairly predictable
>+		 */
>+		ret = __intel_uc_reset_hw(uc);
>+		if (ret)
>+			goto err_out;
>+
>+		if (intel_uc_is_using_huc(uc)) {
>+			ret = intel_huc_fw_upload(huc);
>+			if (ret && intel_uc_fw_is_overridden(&huc->fw))
>+				goto err_out;
>+		}
>+
>+		intel_guc_ads_reset(guc);
>+		intel_guc_write_params(guc);
>+		ret = intel_guc_fw_upload(guc);
>+		if (ret == 0)
>+			break;
>+
>+		DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
>+				 "retry %d more time(s)\n", ret, attempts);
>+	}
>+
>+	/* Did we succeded or run out of retries? */
>+	if (ret)
>+		goto err_log_capture;
>+
>+	ret = guc_enable_communication(guc);
>+	if (ret)
>+		goto err_log_capture;
>+
>+	if (intel_uc_fw_is_loaded(&huc->fw)) {
>+		ret = intel_huc_auth(huc);
>+		if (ret && intel_uc_fw_is_overridden(&huc->fw))
>+			goto err_communication;
>+	}
>+
>+	ret = intel_guc_sample_forcewake(guc);
>+	if (ret)
>+		goto err_communication;
>+
>+	if (intel_uc_is_using_guc_submission(uc)) {
>+		ret = intel_guc_submission_enable(guc);
>+		if (ret)
>+			goto err_communication;
>+	}
>+
>+	dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
>+		 guc->fw.major_ver_found, guc->fw.minor_ver_found);
>+	dev_info(i915->drm.dev, "GuC submission %s\n",
>+		 enableddisabled(intel_uc_is_using_guc_submission(uc)));
>+	dev_info(i915->drm.dev, "HuC %s\n",
>+		 enableddisabled(intel_huc_is_authenticated(huc)));
>+
>+	return 0;
>+
>+	/*
>+	 * We've failed to load the firmware :(
>+	 */
>+err_communication:
>+	guc_disable_communication(guc);
>+err_log_capture:
>+	guc_capture_load_err_log(guc);
>+err_out:
>+	__uc_sanitize(uc);
>+
>+	/*
>+	 * Note that there is no fallback as either user explicitly asked for
>+	 * the GuC or driver default option was to run with the GuC enabled.
>+	 */
>+	if (GEM_WARN_ON(ret == -EIO))
>+		ret = -EINVAL;
>+
>+	dev_err(i915->drm.dev, "GuC initialization failed %d\n", ret);
>+	return ret;
>+}
>+
>+void intel_uc_fini_hw(struct intel_uc *uc)
>+{
>+	struct intel_guc *guc = &uc->guc;
>+
>+	if (!intel_guc_is_running(guc))
>+		return;
>+
>+	GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
>+
>+	if (intel_uc_is_using_guc_submission(uc))
>+		intel_guc_submission_disable(guc);
>+
>+	guc_disable_communication(guc);
>+	__uc_sanitize(uc);
>+}
>+
>+/**
>+ * intel_uc_reset_prepare - Prepare for reset
>+ * @uc: the intel_uc structure
>+ *
>+ * Preparing for full gpu reset.
>+ */
>+void intel_uc_reset_prepare(struct intel_uc *uc)
>+{
>+	struct intel_guc *guc = &uc->guc;
>+
>+	if (!intel_guc_is_running(guc))
>+		return;
>+
>+	guc_stop_communication(guc);
>+	__uc_sanitize(uc);
>+}
>+
>+void intel_uc_runtime_suspend(struct intel_uc *uc)
>+{
>+	struct intel_guc *guc = &uc->guc;
>+	int err;
>+
>+	if (!intel_guc_is_running(guc))
>+		return;
>+
>+	err = intel_guc_suspend(guc);
>+	if (err)
>+		DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
>+
>+	guc_disable_communication(guc);
>+}
>+
>+void intel_uc_suspend(struct intel_uc *uc)
>+{
>+	struct intel_guc *guc = &uc->guc;
>+	intel_wakeref_t wakeref;
>+
>+	if (!intel_guc_is_running(guc))
>+		return;
>+
>+	with_intel_runtime_pm(&uc_to_gt(uc)->i915->runtime_pm, wakeref)
>+		intel_uc_runtime_suspend(uc);
>+}
>+
>+int intel_uc_resume(struct intel_uc *uc)
>+{
>+	struct intel_guc *guc = &uc->guc;
>+	int err;
>+
>+	if (!intel_guc_is_running(guc))
>+		return 0;
>+
>+	guc_enable_communication(guc);
>+
>+	err = intel_guc_resume(guc);
>+	if (err) {
>+		DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
>+		return err;
>+	}
>+
>+	return 0;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h	2019-08-31 15:01:12.030736183 -0500
>@@ -0,0 +1,82 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright Â© 2019 Intel Corporation
>+ */
>+
>+#ifndef _INTEL_UC_FW_ABI_H
>+#define _INTEL_UC_FW_ABI_H
>+
>+#include <linux/types.h>
>+#include <linux/build_bug.h>
>+
>+/**
>+ * DOC: Firmware Layout
>+ *
>+ * The GuC/HuC firmware layout looks like this::
>+ *
>+ *      +======================================================================+
>+ *      |  Firmware blob                                                       |
>+ *      +===============+===============+============+============+============+
>+ *      |  CSS header   |     uCode     |  RSA key   |  modulus   |  exponent  |
>+ *      +===============+===============+============+============+============+
>+ *       <-header size->                 <---header size continued ----------->
>+ *       <--- size ----------------------------------------------------------->
>+ *                                       <-key size->
>+ *                                                    <-mod size->
>+ *                                                                 <-exp size->
>+ *
>+ * The firmware may or may not have modulus key and exponent data. The header,
>+ * uCode and RSA signature are must-have components that will be used by driver.
>+ * Length of each components, which is all in dwords, can be found in header.
>+ * In the case that modulus and exponent are not present in fw, a.k.a truncated
>+ * image, the length value still appears in header.
>+ *
>+ * Driver will do some basic fw size validation based on the following rules:
>+ *
>+ * 1. Header, uCode and RSA are must-have components.
>+ * 2. All firmware components, if they present, are in the sequence illustrated
>+ *    in the layout table above.
>+ * 3. Length info of each component can be found in header, in dwords.
>+ * 4. Modulus and exponent key are not required by driver. They may not appear
>+ *    in fw. So driver will load a truncated firmware in this case.
>+ *
>+ * The only difference between GuC and HuC firmwares is how the version
>+ * information is saved.
>+ */
>+
>+struct uc_css_header {
>+	u32 module_type;
>+	/*
>+	 * header_size includes all non-uCode bits, including css_header, rsa
>+	 * key, modulus key and exponent data.
>+	 */
>+	u32 header_size_dw;
>+	u32 header_version;
>+	u32 module_id;
>+	u32 module_vendor;
>+	u32 date;
>+#define CSS_DATE_DAY			(0xFF << 0)
>+#define CSS_DATE_MONTH			(0xFF << 8)
>+#define CSS_DATE_YEAR			(0xFFFF << 16)
>+	u32 size_dw; /* uCode plus header_size_dw */
>+	u32 key_size_dw;
>+	u32 modulus_size_dw;
>+	u32 exponent_size_dw;
>+	u32 time;
>+#define CSS_TIME_HOUR			(0xFF << 0)
>+#define CSS_DATE_MIN			(0xFF << 8)
>+#define CSS_DATE_SEC			(0xFFFF << 16)
>+	char username[8];
>+	char buildnumber[12];
>+	u32 sw_version;
>+#define CSS_SW_VERSION_GUC_MAJOR	(0xFF << 16)
>+#define CSS_SW_VERSION_GUC_MINOR	(0xFF << 8)
>+#define CSS_SW_VERSION_GUC_PATCH	(0xFF << 0)
>+#define CSS_SW_VERSION_HUC_MAJOR	(0xFFFF << 16)
>+#define CSS_SW_VERSION_HUC_MINOR	(0xFFFF << 0)
>+	u32 reserved[14];
>+	u32 header_info;
>+} __packed;
>+static_assert(sizeof(struct uc_css_header) == 128);
>+
>+#endif /* _INTEL_UC_FW_ABI_H */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c	2019-08-31 15:01:12.030736183 -0500
>@@ -0,0 +1,540 @@
>+/*
>+ * Copyright Â© 2016-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include <linux/bitfield.h>
>+#include <linux/firmware.h>
>+#include <drm/drm_print.h>
>+
>+#include "intel_uc_fw.h"
>+#include "intel_uc_fw_abi.h"
>+#include "i915_drv.h"
>+
>+/*
>+ * List of required GuC and HuC binaries per-platform.
>+ * Must be ordered based on platform + revid, from newer to older.
>+ */
>+#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
>+	fw_def(ICELAKE,    0, guc_def(icl, 33, 0, 0), huc_def(icl,  8,  4, 3238)) \
>+	fw_def(COFFEELAKE, 0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \
>+	fw_def(GEMINILAKE, 0, guc_def(glk, 33, 0, 0), huc_def(glk, 03, 01, 2893)) \
>+	fw_def(KABYLAKE,   0, guc_def(kbl, 33, 0, 0), huc_def(kbl, 02, 00, 1810)) \
>+	fw_def(BROXTON,    0, guc_def(bxt, 33, 0, 0), huc_def(bxt, 01,  8, 2893)) \
>+	fw_def(SKYLAKE,    0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 1398))
>+
>+#define __MAKE_UC_FW_PATH(prefix_, name_, separator_, major_, minor_, patch_) \
>+	"i915/" \
>+	__stringify(prefix_) name_ \
>+	__stringify(major_) separator_ \
>+	__stringify(minor_) separator_ \
>+	__stringify(patch_) ".bin"
>+
>+#define MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_) \
>+	__MAKE_UC_FW_PATH(prefix_, "_guc_", ".", major_, minor_, patch_)
>+
>+#define MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_) \
>+	__MAKE_UC_FW_PATH(prefix_, "_huc_ver", "_", major_, minor_, bld_num_)
>+
>+/* All blobs need to be declared via MODULE_FIRMWARE() */
>+#define INTEL_UC_MODULE_FW(platform_, revid_, guc_, huc_) \
>+	MODULE_FIRMWARE(guc_); \
>+	MODULE_FIRMWARE(huc_);
>+
>+INTEL_UC_FIRMWARE_DEFS(INTEL_UC_MODULE_FW, MAKE_GUC_FW_PATH, MAKE_HUC_FW_PATH)
>+
>+/* The below structs and macros are used to iterate across the list of blobs */
>+struct __packed uc_fw_blob {
>+	u8 major;
>+	u8 minor;
>+	const char *path;
>+};
>+
>+#define UC_FW_BLOB(major_, minor_, path_) \
>+	{ .major = major_, .minor = minor_, .path = path_ }
>+
>+#define GUC_FW_BLOB(prefix_, major_, minor_, patch_) \
>+	UC_FW_BLOB(major_, minor_, \
>+		   MAKE_GUC_FW_PATH(prefix_, major_, minor_, patch_))
>+
>+#define HUC_FW_BLOB(prefix_, major_, minor_, bld_num_) \
>+	UC_FW_BLOB(major_, minor_, \
>+		   MAKE_HUC_FW_PATH(prefix_, major_, minor_, bld_num_))
>+
>+struct __packed uc_fw_platform_requirement {
>+	enum intel_platform p;
>+	u8 rev; /* first platform rev using this FW */
>+	const struct uc_fw_blob blobs[INTEL_UC_FW_NUM_TYPES];
>+};
>+
>+#define MAKE_FW_LIST(platform_, revid_, guc_, huc_) \
>+{ \
>+	.p = INTEL_##platform_, \
>+	.rev = revid_, \
>+	.blobs[INTEL_UC_FW_TYPE_GUC] = guc_, \
>+	.blobs[INTEL_UC_FW_TYPE_HUC] = huc_, \
>+},
>+
>+static void
>+__uc_fw_auto_select(struct intel_uc_fw *uc_fw, enum intel_platform p, u8 rev)
>+{
>+	static const struct uc_fw_platform_requirement fw_blobs[] = {
>+		INTEL_UC_FIRMWARE_DEFS(MAKE_FW_LIST, GUC_FW_BLOB, HUC_FW_BLOB)
>+	};
>+	int i;
>+
>+	for (i = 0; i < ARRAY_SIZE(fw_blobs) && p <= fw_blobs[i].p; i++) {
>+		if (p == fw_blobs[i].p && rev >= fw_blobs[i].rev) {
>+			const struct uc_fw_blob *blob =
>+					&fw_blobs[i].blobs[uc_fw->type];
>+			uc_fw->path = blob->path;
>+			uc_fw->major_ver_wanted = blob->major;
>+			uc_fw->minor_ver_wanted = blob->minor;
>+			break;
>+		}
>+	}
>+
>+	/* make sure the list is ordered as expected */
>+	if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST)) {
>+		for (i = 1; i < ARRAY_SIZE(fw_blobs); i++) {
>+			if (fw_blobs[i].p < fw_blobs[i - 1].p)
>+				continue;
>+
>+			if (fw_blobs[i].p == fw_blobs[i - 1].p &&
>+			    fw_blobs[i].rev < fw_blobs[i - 1].rev)
>+				continue;
>+
>+			pr_err("invalid FW blob order: %s r%u comes before %s r%u\n",
>+			       intel_platform_name(fw_blobs[i - 1].p),
>+			       fw_blobs[i - 1].rev,
>+			       intel_platform_name(fw_blobs[i].p),
>+			       fw_blobs[i].rev);
>+
>+			uc_fw->path = NULL;
>+		}
>+	}
>+}
>+
>+static bool
>+__uc_fw_override(struct intel_uc_fw *uc_fw)
>+{
>+	switch (uc_fw->type) {
>+	case INTEL_UC_FW_TYPE_GUC:
>+		uc_fw->path = i915_modparams.guc_firmware_path;
>+		break;
>+	case INTEL_UC_FW_TYPE_HUC:
>+		uc_fw->path = i915_modparams.huc_firmware_path;
>+		break;
>+	}
>+
>+	uc_fw->user_overridden = uc_fw->path;
>+	return uc_fw->user_overridden;
>+}
>+
>+/**
>+ * intel_uc_fw_init_early - initialize the uC object and select the firmware
>+ * @i915: device private
>+ * @uc_fw: uC firmware
>+ * @type: type of uC
>+ *
>+ * Initialize the state of our uC object and relevant tracking and select the
>+ * firmware to fetch and load.
>+ */
>+void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
>+			    enum intel_uc_fw_type type,
>+			    struct drm_i915_private *i915)
>+{
>+	/*
>+	 * we use FIRMWARE_UNINITIALIZED to detect checks against uc_fw->status
>+	 * before we're looked at the HW caps to see if we have uc support
>+	 */
>+	BUILD_BUG_ON(INTEL_UC_FIRMWARE_UNINITIALIZED);
>+	GEM_BUG_ON(uc_fw->status);
>+	GEM_BUG_ON(uc_fw->path);
>+
>+	uc_fw->type = type;
>+
>+	if (HAS_GT_UC(i915) && likely(!__uc_fw_override(uc_fw)))
>+		__uc_fw_auto_select(uc_fw, INTEL_INFO(i915)->platform,
>+				    INTEL_REVID(i915));
>+
>+	if (uc_fw->path && *uc_fw->path)
>+		uc_fw->status = INTEL_UC_FIRMWARE_SELECTED;
>+	else
>+		uc_fw->status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
>+}
>+
>+/**
>+ * intel_uc_fw_fetch - fetch uC firmware
>+ *
>+ * @uc_fw: uC firmware
>+ * @i915: device private
>+ *
>+ * Fetch uC firmware into GEM obj.
>+ */
>+void intel_uc_fw_fetch(struct intel_uc_fw *uc_fw, struct drm_i915_private *i915)
>+{
>+	struct drm_i915_gem_object *obj;
>+	const struct firmware *fw = NULL;
>+	struct uc_css_header *css;
>+	size_t size;
>+	int err;
>+
>+	GEM_BUG_ON(!intel_uc_fw_supported(uc_fw));
>+
>+	err = request_firmware(&fw, uc_fw->path, i915->drm.dev);
>+	if (err)
>+		goto fail;
>+
>+	DRM_DEBUG_DRIVER("%s fw size %zu ptr %p\n",
>+			 intel_uc_fw_type_repr(uc_fw->type), fw->size, fw);
>+
>+	/* Check the size of the blob before examining buffer contents */
>+	if (fw->size < sizeof(struct uc_css_header)) {
>+		DRM_WARN("%s: Unexpected firmware size (%zu, min %zu)\n",
>+			 intel_uc_fw_type_repr(uc_fw->type),
>+			 fw->size, sizeof(struct uc_css_header));
>+		err = -ENODATA;
>+		goto fail;
>+	}
>+
>+	css = (struct uc_css_header *)fw->data;
>+
>+	/* Check integrity of size values inside CSS header */
>+	size = (css->header_size_dw - css->key_size_dw - css->modulus_size_dw -
>+		css->exponent_size_dw) * sizeof(u32);
>+	if (size != sizeof(struct uc_css_header)) {
>+		DRM_WARN("%s: Mismatched firmware header definition\n",
>+			 intel_uc_fw_type_repr(uc_fw->type));
>+		err = -ENOEXEC;
>+		goto fail;
>+	}
>+
>+	/* uCode size must calculated from other sizes */
>+	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
>+
>+	/* now RSA */
>+	if (css->key_size_dw != UOS_RSA_SCRATCH_COUNT) {
>+		DRM_WARN("%s: Mismatched firmware RSA key size (%u)\n",
>+			 intel_uc_fw_type_repr(uc_fw->type), css->key_size_dw);
>+		err = -ENOEXEC;
>+		goto fail;
>+	}
>+	uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>+
>+	/* At least, it should have header, uCode and RSA. Size of all three. */
>+	size = sizeof(struct uc_css_header) + uc_fw->ucode_size + uc_fw->rsa_size;
>+	if (fw->size < size) {
>+		DRM_WARN("%s: Truncated firmware (%zu, expected %zu)\n",
>+			 intel_uc_fw_type_repr(uc_fw->type), fw->size, size);
>+		err = -ENOEXEC;
>+		goto fail;
>+	}
>+
>+	/* Get version numbers from the CSS header */
>+	switch (uc_fw->type) {
>+	case INTEL_UC_FW_TYPE_GUC:
>+		uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MAJOR,
>+						   css->sw_version);
>+		uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MINOR,
>+						   css->sw_version);
>+		break;
>+
>+	case INTEL_UC_FW_TYPE_HUC:
>+		uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MAJOR,
>+						   css->sw_version);
>+		uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MINOR,
>+						   css->sw_version);
>+		break;
>+
>+	default:
>+		MISSING_CASE(uc_fw->type);
>+		break;
>+	}
>+
>+	DRM_DEBUG_DRIVER("%s fw version %u.%u (wanted %u.%u)\n",
>+			 intel_uc_fw_type_repr(uc_fw->type),
>+			 uc_fw->major_ver_found, uc_fw->minor_ver_found,
>+			 uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
>+
>+	if (uc_fw->major_ver_wanted == 0 && uc_fw->minor_ver_wanted == 0) {
>+		DRM_NOTE("%s: Skipping firmware version check\n",
>+			 intel_uc_fw_type_repr(uc_fw->type));
>+	} else if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
>+		   uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
>+		DRM_NOTE("%s: Wrong firmware version (%u.%u, required %u.%u)\n",
>+			 intel_uc_fw_type_repr(uc_fw->type),
>+			 uc_fw->major_ver_found, uc_fw->minor_ver_found,
>+			 uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
>+		err = -ENOEXEC;
>+		goto fail;
>+	}
>+
>+	obj = i915_gem_object_create_shmem_from_data(i915, fw->data, fw->size);
>+	if (IS_ERR(obj)) {
>+		err = PTR_ERR(obj);
>+		DRM_DEBUG_DRIVER("%s fw object_create err=%d\n",
>+				 intel_uc_fw_type_repr(uc_fw->type), err);
>+		goto fail;
>+	}
>+
>+	uc_fw->obj = obj;
>+	uc_fw->size = fw->size;
>+	uc_fw->status = INTEL_UC_FIRMWARE_AVAILABLE;
>+
>+	release_firmware(fw);
>+	return;
>+
>+fail:
>+	uc_fw->status = INTEL_UC_FIRMWARE_MISSING;
>+
>+	DRM_WARN("%s: Failed to fetch firmware %s (error %d)\n",
>+		 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, err);
>+	DRM_INFO("%s: Firmware can be downloaded from %s\n",
>+		 intel_uc_fw_type_repr(uc_fw->type), INTEL_UC_FIRMWARE_URL);
>+
>+	release_firmware(fw);		/* OK even if fw is NULL */
>+}
>+
>+static u32 uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw, struct i915_ggtt *ggtt)
>+{
>+	struct drm_mm_node *node = &ggtt->uc_fw;
>+
>+	GEM_BUG_ON(!node->allocated);
>+	GEM_BUG_ON(upper_32_bits(node->start));
>+	GEM_BUG_ON(upper_32_bits(node->start + node->size - 1));
>+
>+	return lower_32_bits(node->start);
>+}
>+
>+static void intel_uc_fw_ggtt_bind(struct intel_uc_fw *uc_fw,
>+				  struct intel_gt *gt)
>+{
>+	struct drm_i915_gem_object *obj = uc_fw->obj;
>+	struct i915_ggtt *ggtt = gt->ggtt;
>+	struct i915_vma dummy = {
>+		.node.start = uc_fw_ggtt_offset(uc_fw, ggtt),
>+		.node.size = obj->base.size,
>+		.pages = obj->mm.pages,
>+		.vm = &ggtt->vm,
>+	};
>+
>+	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
>+	GEM_BUG_ON(dummy.node.size > ggtt->uc_fw.size);
>+
>+	/* uc_fw->obj cache domains were not controlled across suspend */
>+	drm_clflush_sg(dummy.pages);
>+
>+	ggtt->vm.insert_entries(&ggtt->vm, &dummy, I915_CACHE_NONE, 0);
>+}
>+
>+static void intel_uc_fw_ggtt_unbind(struct intel_uc_fw *uc_fw,
>+				    struct intel_gt *gt)
>+{
>+	struct drm_i915_gem_object *obj = uc_fw->obj;
>+	struct i915_ggtt *ggtt = gt->ggtt;
>+	u64 start = uc_fw_ggtt_offset(uc_fw, ggtt);
>+
>+	ggtt->vm.clear_range(&ggtt->vm, start, obj->base.size);
>+}
>+
>+static int uc_fw_xfer(struct intel_uc_fw *uc_fw, struct intel_gt *gt,
>+		      u32 wopcm_offset, u32 dma_flags)
>+{
>+	struct intel_uncore *uncore = gt->uncore;
>+	u64 offset;
>+	int ret;
>+
>+	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>+
>+	/* Set the source address for the uCode */
>+	offset = uc_fw_ggtt_offset(uc_fw, gt->ggtt);
>+	GEM_BUG_ON(upper_32_bits(offset) & 0xFFFF0000);
>+	intel_uncore_write_fw(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset));
>+	intel_uncore_write_fw(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset));
>+
>+	/* Set the DMA destination */
>+	intel_uncore_write_fw(uncore, DMA_ADDR_1_LOW, wopcm_offset);
>+	intel_uncore_write_fw(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>+
>+	/*
>+	 * Set the transfer size. The header plus uCode will be copied to WOPCM
>+	 * via DMA, excluding any other components
>+	 */
>+	intel_uncore_write_fw(uncore, DMA_COPY_SIZE,
>+			      sizeof(struct uc_css_header) + uc_fw->ucode_size);
>+
>+	/* Start the DMA */
>+	intel_uncore_write_fw(uncore, DMA_CTRL,
>+			      _MASKED_BIT_ENABLE(dma_flags | START_DMA));
>+
>+	/* Wait for DMA to finish */
>+	ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100);
>+	if (ret)
>+		dev_err(gt->i915->drm.dev, "DMA for %s fw failed, DMA_CTRL=%u\n",
>+			intel_uc_fw_type_repr(uc_fw->type),
>+			intel_uncore_read_fw(uncore, DMA_CTRL));
>+
>+	/* Disable the bits once DMA is over */
>+	intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags));
>+
>+	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>+
>+	return ret;
>+}
>+
>+/**
>+ * intel_uc_fw_upload - load uC firmware using custom loader
>+ * @uc_fw: uC firmware
>+ * @gt: the intel_gt structure
>+ * @wopcm_offset: destination offset in wopcm
>+ * @dma_flags: flags for flags for dma ctrl
>+ *
>+ * Loads uC firmware and updates internal flags.
>+ *
>+ * Return: 0 on success, non-zero on failure.
>+ */
>+int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, struct intel_gt *gt,
>+		       u32 wopcm_offset, u32 dma_flags)
>+{
>+	int err;
>+
>+	DRM_DEBUG_DRIVER("%s fw load %s\n",
>+			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path);
>+
>+	/* make sure the status was cleared the last time we reset the uc */
>+	GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw));
>+
>+	if (!intel_uc_fw_is_available(uc_fw))
>+		return -ENOEXEC;
>+	/* Call custom loader */
>+	intel_uc_fw_ggtt_bind(uc_fw, gt);
>+	err = uc_fw_xfer(uc_fw, gt, wopcm_offset, dma_flags);
>+	intel_uc_fw_ggtt_unbind(uc_fw, gt);
>+	if (err)
>+		goto fail;
>+
>+	uc_fw->status = INTEL_UC_FIRMWARE_TRANSFERRED;
>+	DRM_DEBUG_DRIVER("%s fw xfer completed\n",
>+			 intel_uc_fw_type_repr(uc_fw->type));
>+
>+	DRM_INFO("%s: Loaded firmware %s (version %u.%u)\n",
>+		 intel_uc_fw_type_repr(uc_fw->type),
>+		 uc_fw->path,
>+		 uc_fw->major_ver_found, uc_fw->minor_ver_found);
>+
>+	return 0;
>+
>+fail:
>+	uc_fw->status = INTEL_UC_FIRMWARE_FAIL;
>+	DRM_DEBUG_DRIVER("%s fw load failed\n",
>+			 intel_uc_fw_type_repr(uc_fw->type));
>+
>+	DRM_WARN("%s: Failed to load firmware %s (error %d)\n",
>+		 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, err);
>+
>+	return err;
>+}
>+
>+int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
>+{
>+	int err;
>+
>+	/* this should happen before the load! */
>+	GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw));
>+
>+	if (!intel_uc_fw_is_available(uc_fw))
>+		return -ENOEXEC;
>+
>+	err = i915_gem_object_pin_pages(uc_fw->obj);
>+	if (err)
>+		DRM_DEBUG_DRIVER("%s fw pin-pages err=%d\n",
>+				 intel_uc_fw_type_repr(uc_fw->type), err);
>+
>+	return err;
>+}
>+
>+void intel_uc_fw_fini(struct intel_uc_fw *uc_fw)
>+{
>+	if (!intel_uc_fw_is_available(uc_fw))
>+		return;
>+
>+	i915_gem_object_unpin_pages(uc_fw->obj);
>+}
>+
>+/**
>+ * intel_uc_fw_cleanup_fetch - cleanup uC firmware
>+ *
>+ * @uc_fw: uC firmware
>+ *
>+ * Cleans up uC firmware by releasing the firmware GEM obj.
>+ */
>+void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw)
>+{
>+	struct drm_i915_gem_object *obj;
>+
>+	obj = fetch_and_zero(&uc_fw->obj);
>+	if (obj)
>+		i915_gem_object_put(obj);
>+
>+	uc_fw->status = INTEL_UC_FIRMWARE_SELECTED;
>+}
>+
>+/**
>+ * intel_uc_fw_copy_rsa - copy fw RSA to buffer
>+ *
>+ * @uc_fw: uC firmware
>+ * @dst: dst buffer
>+ * @max_len: max number of bytes to copy
>+ *
>+ * Return: number of copied bytes.
>+ */
>+size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len)
>+{
>+	struct sg_table *pages = uc_fw->obj->mm.pages;
>+	u32 size = min_t(u32, uc_fw->rsa_size, max_len);
>+	u32 offset = sizeof(struct uc_css_header) + uc_fw->ucode_size;
>+
>+	GEM_BUG_ON(!intel_uc_fw_is_available(uc_fw));
>+
>+	return sg_pcopy_to_buffer(pages->sgl, pages->nents, dst, size, offset);
>+}
>+
>+/**
>+ * intel_uc_fw_dump - dump information about uC firmware
>+ * @uc_fw: uC firmware
>+ * @p: the &drm_printer
>+ *
>+ * Pretty printer for uC firmware.
>+ */
>+void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p)
>+{
>+	drm_printf(p, "%s firmware: %s\n",
>+		   intel_uc_fw_type_repr(uc_fw->type), uc_fw->path);
>+	drm_printf(p, "\tstatus: %s\n",
>+		   intel_uc_fw_status_repr(uc_fw->status));
>+	drm_printf(p, "\tversion: wanted %u.%u, found %u.%u\n",
>+		   uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted,
>+		   uc_fw->major_ver_found, uc_fw->minor_ver_found);
>+	drm_printf(p, "\tuCode: %u bytes\n", uc_fw->ucode_size);
>+	drm_printf(p, "\tRSA: %u bytes\n", uc_fw->rsa_size);
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h	2019-08-31 15:01:12.240736202 -0500
>@@ -0,0 +1,185 @@
>+/*
>+ * Copyright Â© 2014-2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#ifndef _INTEL_UC_FW_H_
>+#define _INTEL_UC_FW_H_
>+
>+#include <linux/types.h>
>+#include "intel_uc_fw_abi.h"
>+#include "i915_gem.h"
>+
>+struct drm_printer;
>+struct drm_i915_private;
>+struct intel_gt;
>+
>+/* Home of GuC, HuC and DMC firmwares */
>+#define INTEL_UC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915"
>+
>+enum intel_uc_fw_status {
>+	INTEL_UC_FIRMWARE_FAIL = -3, /* failed to xfer or init/auth the fw */
>+	INTEL_UC_FIRMWARE_MISSING = -2, /* blob not found on the system */
>+	INTEL_UC_FIRMWARE_NOT_SUPPORTED = -1, /* no uc HW */
>+	INTEL_UC_FIRMWARE_UNINITIALIZED = 0, /* used to catch checks done too early */
>+	INTEL_UC_FIRMWARE_SELECTED, /* selected the blob we want to load */
>+	INTEL_UC_FIRMWARE_AVAILABLE, /* blob found and copied in mem */
>+	INTEL_UC_FIRMWARE_TRANSFERRED, /* dma xfer done */
>+	INTEL_UC_FIRMWARE_RUNNING /* init/auth done */
>+};
>+
>+enum intel_uc_fw_type {
>+	INTEL_UC_FW_TYPE_GUC = 0,
>+	INTEL_UC_FW_TYPE_HUC
>+};
>+#define INTEL_UC_FW_NUM_TYPES 2
>+
>+/*
>+ * This structure encapsulates all the data needed during the process
>+ * of fetching, caching, and loading the firmware image into the uC.
>+ */
>+struct intel_uc_fw {
>+	enum intel_uc_fw_type type;
>+	enum intel_uc_fw_status status;
>+	const char *path;
>+	bool user_overridden;
>+	size_t size;
>+	struct drm_i915_gem_object *obj;
>+
>+	/*
>+	 * The firmware build process will generate a version header file with major and
>+	 * minor version defined. The versions are built into CSS header of firmware.
>+	 * i915 kernel driver set the minimal firmware version required per platform.
>+	 */
>+	u16 major_ver_wanted;
>+	u16 minor_ver_wanted;
>+	u16 major_ver_found;
>+	u16 minor_ver_found;
>+
>+	u32 rsa_size;
>+	u32 ucode_size;
>+};
>+
>+static inline
>+const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
>+{
>+	switch (status) {
>+	case INTEL_UC_FIRMWARE_FAIL:
>+		return "FAIL";
>+	case INTEL_UC_FIRMWARE_MISSING:
>+		return "MISSING";
>+	case INTEL_UC_FIRMWARE_NOT_SUPPORTED:
>+		return "N/A";
>+	case INTEL_UC_FIRMWARE_UNINITIALIZED:
>+		return "UNINITIALIZED";
>+	case INTEL_UC_FIRMWARE_SELECTED:
>+		return "SELECTED";
>+	case INTEL_UC_FIRMWARE_AVAILABLE:
>+		return "AVAILABLE";
>+	case INTEL_UC_FIRMWARE_TRANSFERRED:
>+		return "TRANSFERRED";
>+	case INTEL_UC_FIRMWARE_RUNNING:
>+		return "RUNNING";
>+	}
>+	return "<invalid>";
>+}
>+
>+static inline const char *intel_uc_fw_type_repr(enum intel_uc_fw_type type)
>+{
>+	switch (type) {
>+	case INTEL_UC_FW_TYPE_GUC:
>+		return "GuC";
>+	case INTEL_UC_FW_TYPE_HUC:
>+		return "HuC";
>+	}
>+	return "uC";
>+}
>+
>+static inline enum intel_uc_fw_status
>+__intel_uc_fw_status(struct intel_uc_fw *uc_fw)
>+{
>+	/* shouldn't call this before checking hw/blob availability */
>+	GEM_BUG_ON(uc_fw->status == INTEL_UC_FIRMWARE_UNINITIALIZED);
>+	return uc_fw->status;
>+}
>+
>+static inline bool intel_uc_fw_is_available(struct intel_uc_fw *uc_fw)
>+{
>+	return __intel_uc_fw_status(uc_fw) >= INTEL_UC_FIRMWARE_AVAILABLE;
>+}
>+
>+static inline bool intel_uc_fw_is_loaded(struct intel_uc_fw *uc_fw)
>+{
>+	return __intel_uc_fw_status(uc_fw) >= INTEL_UC_FIRMWARE_TRANSFERRED;
>+}
>+
>+static inline bool intel_uc_fw_is_running(struct intel_uc_fw *uc_fw)
>+{
>+	return __intel_uc_fw_status(uc_fw) == INTEL_UC_FIRMWARE_RUNNING;
>+}
>+
>+static inline bool intel_uc_fw_supported(struct intel_uc_fw *uc_fw)
>+{
>+	return __intel_uc_fw_status(uc_fw) != INTEL_UC_FIRMWARE_NOT_SUPPORTED;
>+}
>+
>+static inline bool intel_uc_fw_is_overridden(const struct intel_uc_fw *uc_fw)
>+{
>+	return uc_fw->user_overridden;
>+}
>+
>+static inline void intel_uc_fw_sanitize(struct intel_uc_fw *uc_fw)
>+{
>+	if (intel_uc_fw_is_loaded(uc_fw))
>+		uc_fw->status = INTEL_UC_FIRMWARE_AVAILABLE;
>+}
>+
>+/**
>+ * intel_uc_fw_get_upload_size() - Get size of firmware needed to be uploaded.
>+ * @uc_fw: uC firmware.
>+ *
>+ * Get the size of the firmware and header that will be uploaded to WOPCM.
>+ *
>+ * Return: Upload firmware size, or zero on firmware fetch failure.
>+ */
>+static inline u32 intel_uc_fw_get_upload_size(struct intel_uc_fw *uc_fw)
>+{
>+	if (!intel_uc_fw_is_available(uc_fw))
>+		return 0;
>+
>+	return sizeof(struct uc_css_header) + uc_fw->ucode_size;
>+}
>+
>+void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
>+			    enum intel_uc_fw_type type,
>+			    struct drm_i915_private *i915);
>+void intel_uc_fw_fetch(struct intel_uc_fw *uc_fw,
>+		       struct drm_i915_private *i915);
>+void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw);
>+int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, struct intel_gt *gt,
>+		       u32 wopcm_offset, u32 dma_flags);
>+int intel_uc_fw_init(struct intel_uc_fw *uc_fw);
>+void intel_uc_fw_fini(struct intel_uc_fw *uc_fw);
>+size_t intel_uc_fw_copy_rsa(struct intel_uc_fw *uc_fw, void *dst, u32 max_len);
>+void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_uc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_uc.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/intel_uc.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/intel_uc.h	2019-08-31 15:01:12.240736202 -0500
>@@ -0,0 +1,69 @@
>+/*
>+ * Copyright Â© 2014 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+#ifndef _INTEL_UC_H_
>+#define _INTEL_UC_H_
>+
>+#include "intel_guc.h"
>+#include "intel_huc.h"
>+#include "i915_params.h"
>+
>+struct intel_uc {
>+	struct intel_guc guc;
>+	struct intel_huc huc;
>+};
>+
>+void intel_uc_init_early(struct intel_uc *uc);
>+void intel_uc_cleanup_early(struct intel_uc *uc);
>+void intel_uc_init_mmio(struct intel_uc *uc);
>+void intel_uc_fetch_firmwares(struct intel_uc *uc);
>+void intel_uc_cleanup_firmwares(struct intel_uc *uc);
>+void intel_uc_sanitize(struct intel_uc *uc);
>+int intel_uc_init_hw(struct intel_uc *uc);
>+void intel_uc_fini_hw(struct intel_uc *uc);
>+int intel_uc_init(struct intel_uc *uc);
>+void intel_uc_fini(struct intel_uc *uc);
>+void intel_uc_reset_prepare(struct intel_uc *uc);
>+void intel_uc_suspend(struct intel_uc *uc);
>+void intel_uc_runtime_suspend(struct intel_uc *uc);
>+int intel_uc_resume(struct intel_uc *uc);
>+
>+static inline bool intel_uc_is_using_guc(struct intel_uc *uc)
>+{
>+	GEM_BUG_ON(i915_modparams.enable_guc < 0);
>+	return i915_modparams.enable_guc > 0;
>+}
>+
>+static inline bool intel_uc_is_using_guc_submission(struct intel_uc *uc)
>+{
>+	GEM_BUG_ON(i915_modparams.enable_guc < 0);
>+	return i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION;
>+}
>+
>+static inline bool intel_uc_is_using_huc(struct intel_uc *uc)
>+{
>+	GEM_BUG_ON(i915_modparams.enable_guc < 0);
>+	return i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC;
>+}
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/Makefile	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/Makefile	2019-08-31 15:01:12.028736183 -0500
>@@ -0,0 +1,5 @@
>+# For building individual subdir files on the command line
>+subdir-ccflags-y += -I$(srctree)/$(src)/../..
>+
>+# Extra header tests
>+header-test-pattern-$(CONFIG_DRM_I915_WERROR) := *.h
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/selftest_guc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gt/uc/selftest_guc.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gt/uc/selftest_guc.c	2019-08-31 15:01:12.240736202 -0500
>@@ -0,0 +1,336 @@
>+/*
>+ * Copyright Â© 2017 Intel Corporation
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining a
>+ * copy of this software and associated documentation files (the "Software"),
>+ * to deal in the Software without restriction, including without limitation
>+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>+ * and/or sell copies of the Software, and to permit persons to whom the
>+ * Software is furnished to do so, subject to the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the next
>+ * paragraph) shall be included in all copies or substantial portions of the
>+ * Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>+ * IN THE SOFTWARE.
>+ *
>+ */
>+
>+#include "i915_selftest.h"
>+#include "gem/i915_gem_pm.h"
>+
>+/* max doorbell number + negative test for each client type */
>+#define ATTEMPTS (GUC_NUM_DOORBELLS + GUC_CLIENT_PRIORITY_NUM)
>+
>+static struct intel_guc_client *clients[ATTEMPTS];
>+
>+static bool available_dbs(struct intel_guc *guc, u32 priority)
>+{
>+	unsigned long offset;
>+	unsigned long end;
>+	u16 id;
>+
>+	/* first half is used for normal priority, second half for high */
>+	offset = 0;
>+	end = GUC_NUM_DOORBELLS / 2;
>+	if (priority <= GUC_CLIENT_PRIORITY_HIGH) {
>+		offset = end;
>+		end += offset;
>+	}
>+
>+	id = find_next_zero_bit(guc->doorbell_bitmap, end, offset);
>+	if (id < end)
>+		return true;
>+
>+	return false;
>+}
>+
>+static int check_all_doorbells(struct intel_guc *guc)
>+{
>+	u16 db_id;
>+
>+	pr_info_once("Max number of doorbells: %d", GUC_NUM_DOORBELLS);
>+	for (db_id = 0; db_id < GUC_NUM_DOORBELLS; ++db_id) {
>+		if (!doorbell_ok(guc, db_id)) {
>+			pr_err("doorbell %d, not ok\n", db_id);
>+			return -EIO;
>+		}
>+	}
>+
>+	return 0;
>+}
>+
>+static int ring_doorbell_nop(struct intel_guc_client *client)
>+{
>+	struct guc_process_desc *desc = __get_process_desc(client);
>+	int err;
>+
>+	client->use_nop_wqi = true;
>+
>+	spin_lock_irq(&client->wq_lock);
>+
>+	guc_wq_item_append(client, 0, 0, 0, 0);
>+	guc_ring_doorbell(client);
>+
>+	spin_unlock_irq(&client->wq_lock);
>+
>+	client->use_nop_wqi = false;
>+
>+	/* if there are no issues GuC will update the WQ head and keep the
>+	 * WQ in active status
>+	 */
>+	err = wait_for(READ_ONCE(desc->head) == READ_ONCE(desc->tail), 10);
>+	if (err) {
>+		pr_err("doorbell %u ring failed!\n", client->doorbell_id);
>+		return -EIO;
>+	}
>+
>+	if (desc->wq_status != WQ_STATUS_ACTIVE) {
>+		pr_err("doorbell %u ring put WQ in bad state (%u)!\n",
>+		       client->doorbell_id, desc->wq_status);
>+		return -EIO;
>+	}
>+
>+	return 0;
>+}
>+
>+/*
>+ * Basic client sanity check, handy to validate create_clients.
>+ */
>+static int validate_client(struct intel_guc_client *client, int client_priority)
>+{
>+	if (client->priority != client_priority ||
>+	    client->doorbell_id == GUC_DOORBELL_INVALID)
>+		return -EINVAL;
>+	else
>+		return 0;
>+}
>+
>+static bool client_doorbell_in_sync(struct intel_guc_client *client)
>+{
>+	return !client || doorbell_ok(client->guc, client->doorbell_id);
>+}
>+
>+/*
>+ * Check that we're able to synchronize guc_clients with their doorbells
>+ *
>+ * We're creating clients and reserving doorbells once, at module load. During
>+ * module lifetime, GuC, doorbell HW, and i915 state may go out of sync due to
>+ * GuC being reset. In other words - GuC clients are still around, but the
>+ * status of their doorbells may be incorrect. This is the reason behind
>+ * validating that the doorbells status expected by the driver matches what the
>+ * GuC/HW have.
>+ */
>+static int igt_guc_clients(void *args)
>+{
>+	struct drm_i915_private *dev_priv = args;
>+	intel_wakeref_t wakeref;
>+	struct intel_guc *guc;
>+	int err = 0;
>+
>+	GEM_BUG_ON(!HAS_GT_UC(dev_priv));
>+	mutex_lock(&dev_priv->drm.struct_mutex);
>+	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>+
>+	guc = &dev_priv->gt.uc.guc;
>+	if (!guc) {
>+		pr_err("No guc object!\n");
>+		err = -EINVAL;
>+		goto unlock;
>+	}
>+
>+	err = check_all_doorbells(guc);
>+	if (err)
>+		goto unlock;
>+
>+	/*
>+	 * Get rid of clients created during driver load because the test will
>+	 * recreate them.
>+	 */
>+	guc_clients_disable(guc);
>+	guc_clients_destroy(guc);
>+	if (guc->execbuf_client) {
>+		pr_err("guc_clients_destroy lied!\n");
>+		err = -EINVAL;
>+		goto unlock;
>+	}
>+
>+	err = guc_clients_create(guc);
>+	if (err) {
>+		pr_err("Failed to create clients\n");
>+		goto unlock;
>+	}
>+	GEM_BUG_ON(!guc->execbuf_client);
>+
>+	err = validate_client(guc->execbuf_client,
>+			      GUC_CLIENT_PRIORITY_KMD_NORMAL);
>+	if (err) {
>+		pr_err("execbug client validation failed\n");
>+		goto out;
>+	}
>+
>+	/* the client should now have reserved a doorbell */
>+	if (!has_doorbell(guc->execbuf_client)) {
>+		pr_err("guc_clients_create didn't reserve doorbells\n");
>+		err = -EINVAL;
>+		goto out;
>+	}
>+
>+	/* Now enable the clients */
>+	guc_clients_enable(guc);
>+
>+	/* each client should now have received a doorbell */
>+	if (!client_doorbell_in_sync(guc->execbuf_client)) {
>+		pr_err("failed to initialize the doorbells\n");
>+		err = -EINVAL;
>+		goto out;
>+	}
>+
>+	/*
>+	 * Basic test - an attempt to reallocate a valid doorbell to the
>+	 * client it is currently assigned should not cause a failure.
>+	 */
>+	err = create_doorbell(guc->execbuf_client);
>+
>+out:
>+	/*
>+	 * Leave clean state for other test, plus the driver always destroy the
>+	 * clients during unload.
>+	 */
>+	guc_clients_disable(guc);
>+	guc_clients_destroy(guc);
>+	guc_clients_create(guc);
>+	guc_clients_enable(guc);
>+unlock:
>+	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>+	mutex_unlock(&dev_priv->drm.struct_mutex);
>+	return err;
>+}
>+
>+/*
>+ * Create as many clients as number of doorbells. Note that there's already
>+ * client(s)/doorbell(s) created during driver load, but this test creates
>+ * its own and do not interact with the existing ones.
>+ */
>+static int igt_guc_doorbells(void *arg)
>+{
>+	struct drm_i915_private *dev_priv = arg;
>+	intel_wakeref_t wakeref;
>+	struct intel_guc *guc;
>+	int i, err = 0;
>+	u16 db_id;
>+
>+	GEM_BUG_ON(!HAS_GT_UC(dev_priv));
>+	mutex_lock(&dev_priv->drm.struct_mutex);
>+	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>+
>+	guc = &dev_priv->gt.uc.guc;
>+	if (!guc) {
>+		pr_err("No guc object!\n");
>+		err = -EINVAL;
>+		goto unlock;
>+	}
>+
>+	err = check_all_doorbells(guc);
>+	if (err)
>+		goto unlock;
>+
>+	for (i = 0; i < ATTEMPTS; i++) {
>+		clients[i] = guc_client_alloc(guc, i % GUC_CLIENT_PRIORITY_NUM);
>+
>+		if (!clients[i]) {
>+			pr_err("[%d] No guc client\n", i);
>+			err = -EINVAL;
>+			goto out;
>+		}
>+
>+		if (IS_ERR(clients[i])) {
>+			if (PTR_ERR(clients[i]) != -ENOSPC) {
>+				pr_err("[%d] unexpected error\n", i);
>+				err = PTR_ERR(clients[i]);
>+				goto out;
>+			}
>+
>+			if (available_dbs(guc, i % GUC_CLIENT_PRIORITY_NUM)) {
>+				pr_err("[%d] non-db related alloc fail\n", i);
>+				err = -EINVAL;
>+				goto out;
>+			}
>+
>+			/* expected, ran out of dbs for this client type */
>+			continue;
>+		}
>+
>+		/*
>+		 * The check below is only valid because we keep a doorbell
>+		 * assigned during the whole life of the client.
>+		 */
>+		if (clients[i]->stage_id >= GUC_NUM_DOORBELLS) {
>+			pr_err("[%d] more clients than doorbells (%d >= %d)\n",
>+			       i, clients[i]->stage_id, GUC_NUM_DOORBELLS);
>+			err = -EINVAL;
>+			goto out;
>+		}
>+
>+		err = validate_client(clients[i], i % GUC_CLIENT_PRIORITY_NUM);
>+		if (err) {
>+			pr_err("[%d] client_alloc sanity check failed!\n", i);
>+			err = -EINVAL;
>+			goto out;
>+		}
>+
>+		db_id = clients[i]->doorbell_id;
>+
>+		err = __guc_client_enable(clients[i]);
>+		if (err) {
>+			pr_err("[%d] Failed to create a doorbell\n", i);
>+			goto out;
>+		}
>+
>+		/* doorbell id shouldn't change, we are holding the mutex */
>+		if (db_id != clients[i]->doorbell_id) {
>+			pr_err("[%d] doorbell id changed (%d != %d)\n",
>+			       i, db_id, clients[i]->doorbell_id);
>+			err = -EINVAL;
>+			goto out;
>+		}
>+
>+		err = check_all_doorbells(guc);
>+		if (err)
>+			goto out;
>+
>+		err = ring_doorbell_nop(clients[i]);
>+		if (err)
>+			goto out;
>+	}
>+
>+out:
>+	for (i = 0; i < ATTEMPTS; i++)
>+		if (!IS_ERR_OR_NULL(clients[i])) {
>+			__guc_client_disable(clients[i]);
>+			guc_client_free(clients[i]);
>+		}
>+unlock:
>+	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>+	mutex_unlock(&dev_priv->drm.struct_mutex);
>+	return err;
>+}
>+
>+int intel_guc_live_selftest(struct drm_i915_private *dev_priv)
>+{
>+	static const struct i915_subtest tests[] = {
>+		SUBTEST(igt_guc_clients),
>+		SUBTEST(igt_guc_doorbells),
>+	};
>+
>+	if (!USES_GUC_SUBMISSION(dev_priv))
>+		return 0;
>+
>+	return i915_subtests(tests, dev_priv);
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gvt/dmabuf.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gvt/dmabuf.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gvt/dmabuf.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gvt/dmabuf.c	2019-08-31 15:01:12.030736183 -0500
>@@ -491,7 +491,7 @@
> 
> 	obj->gvt_info = dmabuf_obj->info;
> 
>-	dmabuf = i915_gem_prime_export(dev, &obj->base, DRM_CLOEXEC | DRM_RDWR);
>+	dmabuf = i915_gem_prime_export(&obj->base, DRM_CLOEXEC | DRM_RDWR);
> 	if (IS_ERR(dmabuf)) {
> 		gvt_vgpu_err("export dma-buf failed\n");
> 		ret = PTR_ERR(dmabuf);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gvt/gtt.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gvt/gtt.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gvt/gtt.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gvt/gtt.h	2019-08-31 15:01:12.030736183 -0500
>@@ -205,17 +205,18 @@
> 	struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
> };
> 
>-extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
>-extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu);
>+int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
>+void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu);
> void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old);
> void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu);
> 
>-extern int intel_gvt_init_gtt(struct intel_gvt *gvt);
>+int intel_gvt_init_gtt(struct intel_gvt *gvt);
> void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu);
>-extern void intel_gvt_clean_gtt(struct intel_gvt *gvt);
>+void intel_gvt_clean_gtt(struct intel_gvt *gvt);
> 
>-extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
>-		int page_table_level, void *root_entry);
>+struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
>+					      int page_table_level,
>+					      void *root_entry);
> 
> struct intel_vgpu_oos_page {
> 	struct intel_vgpu_ppgtt_spt *spt;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/gvt/scheduler.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gvt/scheduler.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/gvt/scheduler.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/gvt/scheduler.c	2019-08-31 15:01:12.240736202 -0500
>@@ -1157,7 +1157,7 @@
> 
> 	intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
> 
>-	i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->gem_context->vm));
>+	i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm));
> 	for_each_engine(engine, vgpu->gvt->dev_priv, id)
> 		intel_context_unpin(s->shadow[id]);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_active.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_active.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_active.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_active.c	2019-08-31 15:01:12.030736183 -0500
>@@ -4,6 +4,8 @@
>  * Copyright Â© 2019 Intel Corporation
>  */
> 
>+#include <linux/debugobjects.h>
>+
> #include "gt/intel_engine_pm.h"
> 
> #include "i915_drv.h"
>@@ -31,49 +33,108 @@
> 	u64 timeline;
> };
> 
>-static void
>-__active_park(struct i915_active *ref)
>+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) && IS_ENABLED(CONFIG_DEBUG_OBJECTS)
>+
>+static void *active_debug_hint(void *addr)
> {
>-	struct active_node *it, *n;
>+	struct i915_active *ref = addr;
> 
>-	rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node) {
>-		GEM_BUG_ON(i915_active_request_isset(&it->base));
>-		kmem_cache_free(global.slab_cache, it);
>-	}
>-	ref->tree = RB_ROOT;
>+	return (void *)ref->active ?: (void *)ref->retire ?: (void *)ref;
>+}
>+
>+static struct debug_obj_descr active_debug_desc = {
>+	.name = "i915_active",
>+	.debug_hint = active_debug_hint,
>+};
>+
>+static void debug_active_init(struct i915_active *ref)
>+{
>+	debug_object_init(ref, &active_debug_desc);
> }
> 
>+static void debug_active_activate(struct i915_active *ref)
>+{
>+	debug_object_activate(ref, &active_debug_desc);
>+}
>+
>+static void debug_active_deactivate(struct i915_active *ref)
>+{
>+	debug_object_deactivate(ref, &active_debug_desc);
>+}
>+
>+static void debug_active_fini(struct i915_active *ref)
>+{
>+	debug_object_free(ref, &active_debug_desc);
>+}
>+
>+static void debug_active_assert(struct i915_active *ref)
>+{
>+	debug_object_assert_init(ref, &active_debug_desc);
>+}
>+
>+#else
>+
>+static inline void debug_active_init(struct i915_active *ref) { }
>+static inline void debug_active_activate(struct i915_active *ref) { }
>+static inline void debug_active_deactivate(struct i915_active *ref) { }
>+static inline void debug_active_fini(struct i915_active *ref) { }
>+static inline void debug_active_assert(struct i915_active *ref) { }
>+
>+#endif
>+
> static void
> __active_retire(struct i915_active *ref)
> {
>-	GEM_BUG_ON(!ref->count);
>-	if (--ref->count)
>-		return;
>+	struct active_node *it, *n;
>+	struct rb_root root;
>+	bool retire = false;
>+
>+	lockdep_assert_held(&ref->mutex);
> 
>-	/* return the unused nodes to our slabcache */
>-	__active_park(ref);
>+	/* return the unused nodes to our slabcache -- flushing the allocator */
>+	if (atomic_dec_and_test(&ref->count)) {
>+		debug_active_deactivate(ref);
>+		root = ref->tree;
>+		ref->tree = RB_ROOT;
>+		ref->cache = NULL;
>+		retire = true;
>+	}
>+
>+	mutex_unlock(&ref->mutex);
>+	if (!retire)
>+		return;
> 
> 	ref->retire(ref);
>+
>+	rbtree_postorder_for_each_entry_safe(it, n, &root, node) {
>+		GEM_BUG_ON(i915_active_request_isset(&it->base));
>+		kmem_cache_free(global.slab_cache, it);
>+	}
> }
> 
> static void
>-node_retire(struct i915_active_request *base, struct i915_request *rq)
>+active_retire(struct i915_active *ref)
> {
>-	__active_retire(container_of(base, struct active_node, base)->ref);
>+	GEM_BUG_ON(!atomic_read(&ref->count));
>+	if (atomic_add_unless(&ref->count, -1, 1))
>+		return;
>+
>+	/* One active may be flushed from inside the acquire of another */
>+	mutex_lock_nested(&ref->mutex, SINGLE_DEPTH_NESTING);
>+	__active_retire(ref);
> }
> 
> static void
>-last_retire(struct i915_active_request *base, struct i915_request *rq)
>+node_retire(struct i915_active_request *base, struct i915_request *rq)
> {
>-	__active_retire(container_of(base, struct i915_active, last));
>+	active_retire(container_of(base, struct active_node, base)->ref);
> }
> 
> static struct i915_active_request *
> active_instance(struct i915_active *ref, u64 idx)
> {
>-	struct active_node *node;
>+	struct active_node *node, *prealloc;
> 	struct rb_node **p, *parent;
>-	struct i915_request *old;
> 
> 	/*
> 	 * We track the most recently used timeline to skip a rbtree search
>@@ -81,20 +142,18 @@
> 	 * at all. We can reuse the last slot if it is empty, that is
> 	 * after the previous activity has been retired, or if it matches the
> 	 * current timeline.
>-	 *
>-	 * Note that we allow the timeline to be active simultaneously in
>-	 * the rbtree and the last cache. We do this to avoid having
>-	 * to search and replace the rbtree element for a new timeline, with
>-	 * the cost being that we must be aware that the ref may be retired
>-	 * twice for the same timeline (as the older rbtree element will be
>-	 * retired before the new request added to last).
> 	 */
>-	old = i915_active_request_raw(&ref->last, BKL(ref));
>-	if (!old || old->fence.context == idx)
>-		goto out;
>+	node = READ_ONCE(ref->cache);
>+	if (node && node->timeline == idx)
>+		return &node->base;
>+
>+	/* Preallocate a replacement, just in case */
>+	prealloc = kmem_cache_alloc(global.slab_cache, GFP_KERNEL);
>+	if (!prealloc)
>+		return NULL;
> 
>-	/* Move the currently active fence into the rbtree */
>-	idx = old->fence.context;
>+	mutex_lock(&ref->mutex);
>+	GEM_BUG_ON(i915_active_is_idle(ref));
> 
> 	parent = NULL;
> 	p = &ref->tree.rb_node;
>@@ -102,8 +161,10 @@
> 		parent = *p;
> 
> 		node = rb_entry(parent, struct active_node, node);
>-		if (node->timeline == idx)
>-			goto replace;
>+		if (node->timeline == idx) {
>+			kmem_cache_free(global.slab_cache, prealloc);
>+			goto out;
>+		}
> 
> 		if (node->timeline < idx)
> 			p = &parent->rb_right;
>@@ -111,17 +172,7 @@
> 			p = &parent->rb_left;
> 	}
> 
>-	node = kmem_cache_alloc(global.slab_cache, GFP_KERNEL);
>-
>-	/* kmalloc may retire the ref->last (thanks shrinker)! */
>-	if (unlikely(!i915_active_request_raw(&ref->last, BKL(ref)))) {
>-		kmem_cache_free(global.slab_cache, node);
>-		goto out;
>-	}
>-
>-	if (unlikely(!node))
>-		return ERR_PTR(-ENOMEM);
>-
>+	node = prealloc;
> 	i915_active_request_init(&node->base, NULL, node_retire);
> 	node->ref = ref;
> 	node->timeline = idx;
>@@ -129,38 +180,30 @@
> 	rb_link_node(&node->node, parent, p);
> 	rb_insert_color(&node->node, &ref->tree);
> 
>-replace:
>-	/*
>-	 * Overwrite the previous active slot in the rbtree with last,
>-	 * leaving last zeroed. If the previous slot is still active,
>-	 * we must be careful as we now only expect to receive one retire
>-	 * callback not two, and so much undo the active counting for the
>-	 * overwritten slot.
>-	 */
>-	if (i915_active_request_isset(&node->base)) {
>-		/* Retire ourselves from the old rq->active_list */
>-		__list_del_entry(&node->base.link);
>-		ref->count--;
>-		GEM_BUG_ON(!ref->count);
>-	}
>-	GEM_BUG_ON(list_empty(&ref->last.link));
>-	list_replace_init(&ref->last.link, &node->base.link);
>-	node->base.request = fetch_and_zero(&ref->last.request);
>-
> out:
>-	return &ref->last;
>+	ref->cache = node;
>+	mutex_unlock(&ref->mutex);
>+
>+	return &node->base;
> }
> 
>-void i915_active_init(struct drm_i915_private *i915,
>-		      struct i915_active *ref,
>-		      void (*retire)(struct i915_active *ref))
>+void __i915_active_init(struct drm_i915_private *i915,
>+			struct i915_active *ref,
>+			int (*active)(struct i915_active *ref),
>+			void (*retire)(struct i915_active *ref),
>+			struct lock_class_key *key)
> {
>+	debug_active_init(ref);
>+
> 	ref->i915 = i915;
>+	ref->flags = 0;
>+	ref->active = active;
> 	ref->retire = retire;
> 	ref->tree = RB_ROOT;
>-	i915_active_request_init(&ref->last, NULL, last_retire);
>+	ref->cache = NULL;
> 	init_llist_head(&ref->barriers);
>-	ref->count = 0;
>+	atomic_set(&ref->count, 0);
>+	__mutex_init(&ref->mutex, "i915_active", key);
> }
> 
> int i915_active_ref(struct i915_active *ref,
>@@ -168,60 +211,123 @@
> 		    struct i915_request *rq)
> {
> 	struct i915_active_request *active;
>-	int err = 0;
>+	int err;
> 
> 	/* Prevent reaping in case we malloc/wait while building the tree */
>-	i915_active_acquire(ref);
>+	err = i915_active_acquire(ref);
>+	if (err)
>+		return err;
> 
> 	active = active_instance(ref, timeline);
>-	if (IS_ERR(active)) {
>-		err = PTR_ERR(active);
>+	if (!active) {
>+		err = -ENOMEM;
> 		goto out;
> 	}
> 
> 	if (!i915_active_request_isset(active))
>-		ref->count++;
>+		atomic_inc(&ref->count);
> 	__i915_active_request_set(active, rq);
> 
>-	GEM_BUG_ON(!ref->count);
> out:
> 	i915_active_release(ref);
> 	return err;
> }
> 
>-bool i915_active_acquire(struct i915_active *ref)
>+int i915_active_acquire(struct i915_active *ref)
> {
>-	lockdep_assert_held(BKL(ref));
>-	return !ref->count++;
>+	int err;
>+
>+	debug_active_assert(ref);
>+	if (atomic_add_unless(&ref->count, 1, 0))
>+		return 0;
>+
>+	err = mutex_lock_interruptible(&ref->mutex);
>+	if (err)
>+		return err;
>+
>+	if (!atomic_read(&ref->count) && ref->active)
>+		err = ref->active(ref);
>+	if (!err) {
>+		debug_active_activate(ref);
>+		atomic_inc(&ref->count);
>+	}
>+
>+	mutex_unlock(&ref->mutex);
>+
>+	return err;
> }
> 
> void i915_active_release(struct i915_active *ref)
> {
>-	lockdep_assert_held(BKL(ref));
>-	__active_retire(ref);
>+	debug_active_assert(ref);
>+	active_retire(ref);
>+}
>+
>+static void __active_ungrab(struct i915_active *ref)
>+{
>+	clear_and_wake_up_bit(I915_ACTIVE_GRAB_BIT, &ref->flags);
>+}
>+
>+bool i915_active_trygrab(struct i915_active *ref)
>+{
>+	debug_active_assert(ref);
>+
>+	if (test_and_set_bit(I915_ACTIVE_GRAB_BIT, &ref->flags))
>+		return false;
>+
>+	if (!atomic_add_unless(&ref->count, 1, 0)) {
>+		__active_ungrab(ref);
>+		return false;
>+	}
>+
>+	return true;
>+}
>+
>+void i915_active_ungrab(struct i915_active *ref)
>+{
>+	GEM_BUG_ON(!test_bit(I915_ACTIVE_GRAB_BIT, &ref->flags));
>+
>+	active_retire(ref);
>+	__active_ungrab(ref);
> }
> 
> int i915_active_wait(struct i915_active *ref)
> {
> 	struct active_node *it, *n;
>-	int ret = 0;
>+	int err;
> 
>-	if (i915_active_acquire(ref))
>-		goto out_release;
>+	might_sleep();
>+	might_lock(&ref->mutex);
> 
>-	ret = i915_active_request_retire(&ref->last, BKL(ref));
>-	if (ret)
>-		goto out_release;
>+	if (i915_active_is_idle(ref))
>+		return 0;
>+
>+	err = mutex_lock_interruptible(&ref->mutex);
>+	if (err)
>+		return err;
>+
>+	if (!atomic_add_unless(&ref->count, 1, 0)) {
>+		mutex_unlock(&ref->mutex);
>+		return 0;
>+	}
> 
> 	rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node) {
>-		ret = i915_active_request_retire(&it->base, BKL(ref));
>-		if (ret)
>+		err = i915_active_request_retire(&it->base, BKL(ref));
>+		if (err)
> 			break;
> 	}
> 
>-out_release:
>-	i915_active_release(ref);
>-	return ret;
>+	__active_retire(ref);
>+	if (err)
>+		return err;
>+
>+	if (wait_on_bit(&ref->flags, I915_ACTIVE_GRAB_BIT, TASK_KILLABLE))
>+		return -EINTR;
>+
>+	if (!i915_active_is_idle(ref))
>+		return -EBUSY;
>+
>+	return 0;
> }
> 
> int i915_request_await_active_request(struct i915_request *rq,
>@@ -236,23 +342,24 @@
> int i915_request_await_active(struct i915_request *rq, struct i915_active *ref)
> {
> 	struct active_node *it, *n;
>-	int err = 0;
>+	int err;
> 
>-	/* await allocates and so we need to avoid hitting the shrinker */
>-	if (i915_active_acquire(ref))
>-		goto out; /* was idle */
>+	if (RB_EMPTY_ROOT(&ref->tree))
>+		return 0;
> 
>-	err = i915_request_await_active_request(rq, &ref->last);
>+	/* await allocates and so we need to avoid hitting the shrinker */
>+	err = i915_active_acquire(ref);
> 	if (err)
>-		goto out;
>+		return err;
> 
>+	mutex_lock(&ref->mutex);
> 	rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node) {
> 		err = i915_request_await_active_request(rq, &it->base);
> 		if (err)
>-			goto out;
>+			break;
> 	}
>+	mutex_unlock(&ref->mutex);
> 
>-out:
> 	i915_active_release(ref);
> 	return err;
> }
>@@ -260,9 +367,10 @@
> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
> void i915_active_fini(struct i915_active *ref)
> {
>-	GEM_BUG_ON(i915_active_request_isset(&ref->last));
>+	debug_active_fini(ref);
> 	GEM_BUG_ON(!RB_EMPTY_ROOT(&ref->tree));
>-	GEM_BUG_ON(ref->count);
>+	GEM_BUG_ON(atomic_read(&ref->count));
>+	mutex_destroy(&ref->mutex);
> }
> #endif
> 
>@@ -270,12 +378,12 @@
> 					    struct intel_engine_cs *engine)
> {
> 	struct drm_i915_private *i915 = engine->i915;
>+	intel_engine_mask_t tmp, mask = engine->mask;
> 	struct llist_node *pos, *next;
>-	unsigned long tmp;
> 	int err;
> 
>-	GEM_BUG_ON(!engine->mask);
>-	for_each_engine_masked(engine, i915, engine->mask, tmp) {
>+	GEM_BUG_ON(!mask);
>+	for_each_engine_masked(engine, i915, mask, tmp) {
> 		struct intel_context *kctx = engine->kernel_context;
> 		struct active_node *node;
> 
>@@ -289,7 +397,7 @@
> 					 (void *)engine, node_retire);
> 		node->timeline = kctx->ring->timeline->fence_context;
> 		node->ref = ref;
>-		ref->count++;
>+		atomic_inc(&ref->count);
> 
> 		intel_engine_pm_get(engine);
> 		llist_add((struct llist_node *)&node->base.link,
>@@ -316,8 +424,9 @@
> {
> 	struct llist_node *pos, *next;
> 
>-	i915_active_acquire(ref);
>+	GEM_BUG_ON(i915_active_is_idle(ref));
> 
>+	mutex_lock_nested(&ref->mutex, SINGLE_DEPTH_NESTING);
> 	llist_for_each_safe(pos, next, llist_del_all(&ref->barriers)) {
> 		struct intel_engine_cs *engine;
> 		struct active_node *node;
>@@ -347,7 +456,7 @@
> 			  &engine->barrier_tasks);
> 		intel_engine_pm_put(engine);
> 	}
>-	i915_active_release(ref);
>+	mutex_unlock(&ref->mutex);
> }
> 
> void i915_request_add_barriers(struct i915_request *rq)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_active.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_active.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_active.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_active.h	2019-08-31 15:01:12.030736183 -0500
>@@ -369,9 +369,16 @@
>  * synchronisation.
>  */
> 
>-void i915_active_init(struct drm_i915_private *i915,
>-		      struct i915_active *ref,
>-		      void (*retire)(struct i915_active *ref));
>+void __i915_active_init(struct drm_i915_private *i915,
>+			struct i915_active *ref,
>+			int (*active)(struct i915_active *ref),
>+			void (*retire)(struct i915_active *ref),
>+			struct lock_class_key *key);
>+#define i915_active_init(i915, ref, active, retire) do {		\
>+	static struct lock_class_key __key;				\
>+									\
>+	__i915_active_init(i915, ref, active, retire, &__key);		\
>+} while (0)
> 
> int i915_active_ref(struct i915_active *ref,
> 		    u64 timeline,
>@@ -384,20 +391,17 @@
> int i915_request_await_active_request(struct i915_request *rq,
> 				      struct i915_active_request *active);
> 
>-bool i915_active_acquire(struct i915_active *ref);
>-
>-static inline void i915_active_cancel(struct i915_active *ref)
>-{
>-	GEM_BUG_ON(ref->count != 1);
>-	ref->count = 0;
>-}
>-
>+int i915_active_acquire(struct i915_active *ref);
> void i915_active_release(struct i915_active *ref);
>+void __i915_active_release_nested(struct i915_active *ref, int subclass);
>+
>+bool i915_active_trygrab(struct i915_active *ref);
>+void i915_active_ungrab(struct i915_active *ref);
> 
> static inline bool
> i915_active_is_idle(const struct i915_active *ref)
> {
>-	return !ref->count;
>+	return !atomic_read(&ref->count);
> }
> 
> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_active_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_active_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_active_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_active_types.h	2019-08-31 15:01:12.030736183 -0500
>@@ -7,7 +7,9 @@
> #ifndef _I915_ACTIVE_TYPES_H_
> #define _I915_ACTIVE_TYPES_H_
> 
>+#include <linux/atomic.h>
> #include <linux/llist.h>
>+#include <linux/mutex.h>
> #include <linux/rbtree.h>
> #include <linux/rcupdate.h>
> 
>@@ -24,13 +26,20 @@
> 	i915_active_retire_fn retire;
> };
> 
>+struct active_node;
>+
> struct i915_active {
> 	struct drm_i915_private *i915;
> 
>+	struct active_node *cache;
> 	struct rb_root tree;
>-	struct i915_active_request last;
>-	unsigned int count;
>+	struct mutex mutex;
>+	atomic_t count;
>+
>+	unsigned long flags;
>+#define I915_ACTIVE_GRAB_BIT 0
> 
>+	int (*active)(struct i915_active *ref);
> 	void (*retire)(struct i915_active *ref);
> 
> 	struct llist_head barriers;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_debugfs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_debugfs.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_debugfs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_debugfs.c	2019-08-31 15:01:12.031736183 -0500
>@@ -40,12 +40,12 @@
> 
> #include "gem/i915_gem_context.h"
> #include "gt/intel_reset.h"
>+#include "gt/uc/intel_guc_submission.h"
> 
> #include "i915_debugfs.h"
> #include "i915_irq.h"
> #include "intel_csr.h"
> #include "intel_drv.h"
>-#include "intel_guc_submission.h"
> #include "intel_pm.h"
> #include "intel_sideband.h"
> 
>@@ -75,11 +75,6 @@
> 	return 0;
> }
> 
>-static char get_active_flag(struct drm_i915_gem_object *obj)
>-{
>-	return i915_gem_object_is_active(obj) ? '*' : ' ';
>-}
>-
> static char get_pin_flag(struct drm_i915_gem_object *obj)
> {
> 	return obj->pin_global ? 'p' : ' ';
>@@ -144,9 +139,8 @@
> 	unsigned int frontbuffer_bits;
> 	int pin_count = 0;
> 
>-	seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
>+	seq_printf(m, "%pK: %c%c%c%c %8zdKiB %02x %02x %s%s%s",
> 		   &obj->base,
>-		   get_active_flag(obj),
> 		   get_pin_flag(obj),
> 		   get_tiling_flag(obj),
> 		   get_global_flag(obj),
>@@ -1080,17 +1074,16 @@
> 
> static int i915_hangcheck_info(struct seq_file *m, void *unused)
> {
>-	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>+	struct drm_i915_private *i915 = node_to_i915(m->private);
>+	struct intel_gt *gt = &i915->gt;
> 	struct intel_engine_cs *engine;
>-	u64 acthd[I915_NUM_ENGINES];
>-	struct intel_instdone instdone;
> 	intel_wakeref_t wakeref;
> 	enum intel_engine_id id;
> 
>-	seq_printf(m, "Reset flags: %lx\n", dev_priv->gpu_error.flags);
>-	if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
>+	seq_printf(m, "Reset flags: %lx\n", gt->reset.flags);
>+	if (test_bit(I915_WEDGED, &gt->reset.flags))
> 		seq_puts(m, "\tWedged\n");
>-	if (test_bit(I915_RESET_BACKOFF, &dev_priv->gpu_error.flags))
>+	if (test_bit(I915_RESET_BACKOFF, &gt->reset.flags))
> 		seq_puts(m, "\tDevice (global) reset in progress\n");
> 
> 	if (!i915_modparams.enable_hangcheck) {
>@@ -1098,42 +1091,37 @@
> 		return 0;
> 	}
> 
>-	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
>-		for_each_engine(engine, dev_priv, id)
>-			acthd[id] = intel_engine_get_active_head(engine);
>-
>-		intel_engine_get_instdone(dev_priv->engine[RCS0], &instdone);
>-	}
>-
>-	if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
>+	if (timer_pending(&gt->hangcheck.work.timer))
> 		seq_printf(m, "Hangcheck active, timer fires in %dms\n",
>-			   jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
>+			   jiffies_to_msecs(gt->hangcheck.work.timer.expires -
> 					    jiffies));
>-	else if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work))
>+	else if (delayed_work_pending(&gt->hangcheck.work))
> 		seq_puts(m, "Hangcheck active, work pending\n");
> 	else
> 		seq_puts(m, "Hangcheck inactive\n");
> 
>-	seq_printf(m, "GT active? %s\n", yesno(dev_priv->gt.awake));
>+	seq_printf(m, "GT active? %s\n", yesno(gt->awake));
> 
>-	for_each_engine(engine, dev_priv, id) {
>-		seq_printf(m, "%s: %d ms ago\n",
>-			   engine->name,
>-			   jiffies_to_msecs(jiffies -
>-					    engine->hangcheck.action_timestamp));
>-
>-		seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
>-			   (long long)engine->hangcheck.acthd,
>-			   (long long)acthd[id]);
>+	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
>+		for_each_engine(engine, i915, id) {
>+			struct intel_instdone instdone;
> 
>-		if (engine->id == RCS0) {
>-			seq_puts(m, "\tinstdone read =\n");
>+			seq_printf(m, "%s: %d ms ago\n",
>+				   engine->name,
>+				   jiffies_to_msecs(jiffies -
>+						    engine->hangcheck.action_timestamp));
>+
>+			seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
>+				   (long long)engine->hangcheck.acthd,
>+				   intel_engine_get_active_head(engine));
> 
>-			i915_instdone_info(dev_priv, m, &instdone);
>+			intel_engine_get_instdone(engine, &instdone);
> 
>-			seq_puts(m, "\tinstdone accu =\n");
>+			seq_puts(m, "\tinstdone read =\n");
>+			i915_instdone_info(i915, m, &instdone);
> 
>-			i915_instdone_info(dev_priv, m,
>+			seq_puts(m, "\tinstdone accu =\n");
>+			i915_instdone_info(i915, m,
> 					   &engine->hangcheck.instdone);
> 		}
> 	}
>@@ -1141,23 +1129,6 @@
> 	return 0;
> }
> 
>-static int i915_reset_info(struct seq_file *m, void *unused)
>-{
>-	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>-	struct i915_gpu_error *error = &dev_priv->gpu_error;
>-	struct intel_engine_cs *engine;
>-	enum intel_engine_id id;
>-
>-	seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
>-
>-	for_each_engine(engine, dev_priv, id) {
>-		seq_printf(m, "%s = %u\n", engine->name,
>-			   i915_reset_engine_count(error, engine));
>-	}
>-
>-	return 0;
>-}
>-
> static int ironlake_drpc_info(struct seq_file *m)
> {
> 	struct drm_i915_private *i915 = node_to_i915(m->private);
>@@ -1894,11 +1865,11 @@
> 	intel_wakeref_t wakeref;
> 	struct drm_printer p;
> 
>-	if (!HAS_HUC(dev_priv))
>+	if (!HAS_GT_UC(dev_priv))
> 		return -ENODEV;
> 
> 	p = drm_seq_file_printer(m);
>-	intel_uc_fw_dump(&dev_priv->huc.fw, &p);
>+	intel_uc_fw_dump(&dev_priv->gt.uc.huc.fw, &p);
> 
> 	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
> 		seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
>@@ -1912,11 +1883,11 @@
> 	intel_wakeref_t wakeref;
> 	struct drm_printer p;
> 
>-	if (!HAS_GUC(dev_priv))
>+	if (!HAS_GT_UC(dev_priv))
> 		return -ENODEV;
> 
> 	p = drm_seq_file_printer(m);
>-	intel_uc_fw_dump(&dev_priv->guc.fw, &p);
>+	intel_uc_fw_dump(&dev_priv->gt.uc.guc.fw, &p);
> 
> 	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
> 		u32 tmp = I915_READ(GUC_STATUS);
>@@ -1959,7 +1930,7 @@
> static void i915_guc_log_info(struct seq_file *m,
> 			      struct drm_i915_private *dev_priv)
> {
>-	struct intel_guc_log *log = &dev_priv->guc.log;
>+	struct intel_guc_log *log = &dev_priv->gt.uc.guc.log;
> 	enum guc_log_buffer_type type;
> 
> 	if (!intel_guc_log_relay_enabled(log)) {
>@@ -2005,7 +1976,7 @@
> static int i915_guc_info(struct seq_file *m, void *data)
> {
> 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>-	const struct intel_guc *guc = &dev_priv->guc;
>+	const struct intel_guc *guc = &dev_priv->gt.uc.guc;
> 
> 	if (!USES_GUC(dev_priv))
> 		return -ENODEV;
>@@ -2023,11 +1994,6 @@
> 
> 	seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
> 	i915_guc_client_info(m, dev_priv, guc->execbuf_client);
>-	if (guc->preempt_client) {
>-		seq_printf(m, "\nGuC preempt client @ %p:\n",
>-			   guc->preempt_client);
>-		i915_guc_client_info(m, dev_priv, guc->preempt_client);
>-	}
> 
> 	/* Add more as required ... */
> 
>@@ -2037,9 +2003,8 @@
> static int i915_guc_stage_pool(struct seq_file *m, void *data)
> {
> 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>-	const struct intel_guc *guc = &dev_priv->guc;
>+	const struct intel_guc *guc = &dev_priv->gt.uc.guc;
> 	struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
>-	struct intel_guc_client *client = guc->execbuf_client;
> 	intel_engine_mask_t tmp;
> 	int index;
> 
>@@ -2069,7 +2034,7 @@
> 			   desc->wq_addr, desc->wq_size);
> 		seq_putc(m, '\n');
> 
>-		for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
>+		for_each_engine(engine, dev_priv, tmp) {
> 			u32 guc_engine_id = engine->guc_id;
> 			struct guc_execlist_context *lrc =
> 						&desc->lrc[guc_engine_id];
>@@ -2097,13 +2062,13 @@
> 	u32 *log;
> 	int i = 0;
> 
>-	if (!HAS_GUC(dev_priv))
>+	if (!HAS_GT_UC(dev_priv))
> 		return -ENODEV;
> 
> 	if (dump_load_err)
>-		obj = dev_priv->guc.load_err_log;
>-	else if (dev_priv->guc.log.vma)
>-		obj = dev_priv->guc.log.vma->obj;
>+		obj = dev_priv->gt.uc.guc.load_err_log;
>+	else if (dev_priv->gt.uc.guc.log.vma)
>+		obj = dev_priv->gt.uc.guc.log.vma->obj;
> 
> 	if (!obj)
> 		return 0;
>@@ -2134,7 +2099,7 @@
> 	if (!USES_GUC(dev_priv))
> 		return -ENODEV;
> 
>-	*val = intel_guc_log_get_level(&dev_priv->guc.log);
>+	*val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log);
> 
> 	return 0;
> }
>@@ -2146,7 +2111,7 @@
> 	if (!USES_GUC(dev_priv))
> 		return -ENODEV;
> 
>-	return intel_guc_log_set_level(&dev_priv->guc.log, val);
>+	return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val);
> }
> 
> DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops,
>@@ -2160,9 +2125,9 @@
> 	if (!USES_GUC(dev_priv))
> 		return -ENODEV;
> 
>-	file->private_data = &dev_priv->guc.log;
>+	file->private_data = &dev_priv->gt.uc.guc.log;
> 
>-	return intel_guc_log_relay_open(&dev_priv->guc.log);
>+	return intel_guc_log_relay_open(&dev_priv->gt.uc.guc.log);
> }
> 
> static ssize_t
>@@ -2182,7 +2147,7 @@
> {
> 	struct drm_i915_private *dev_priv = inode->i_private;
> 
>-	intel_guc_log_relay_close(&dev_priv->guc.log);
>+	intel_guc_log_relay_close(&dev_priv->gt.uc.guc.log);
> 
> 	return 0;
> }
>@@ -2485,7 +2450,8 @@
> 
> 		for_each_power_domain(power_domain, power_well->desc->domains)
> 			seq_printf(m, "  %-23s %d\n",
>-				 intel_display_power_domain_str(power_domain),
>+				 intel_display_power_domain_str(dev_priv,
>+								power_domain),
> 				 power_domains->domain_use_count[power_domain]);
> 	}
> 
>@@ -2603,6 +2569,25 @@
> 	intel_seq_print_mode(m, 2, mode);
> }
> 
>+static void intel_hdcp_info(struct seq_file *m,
>+			    struct intel_connector *intel_connector)
>+{
>+	bool hdcp_cap, hdcp2_cap;
>+
>+	hdcp_cap = intel_hdcp_capable(intel_connector);
>+	hdcp2_cap = intel_hdcp2_capable(intel_connector);
>+
>+	if (hdcp_cap)
>+		seq_puts(m, "HDCP1.4 ");
>+	if (hdcp2_cap)
>+		seq_puts(m, "HDCP2.2 ");
>+
>+	if (!hdcp_cap && !hdcp2_cap)
>+		seq_puts(m, "None");
>+
>+	seq_puts(m, "\n");
>+}
>+
> static void intel_dp_info(struct seq_file *m,
> 			  struct intel_connector *intel_connector)
> {
>@@ -2616,6 +2601,10 @@
> 
> 	drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
> 				&intel_dp->aux);
>+	if (intel_connector->hdcp.shim) {
>+		seq_puts(m, "\tHDCP version: ");
>+		intel_hdcp_info(m, intel_connector);
>+	}
> }
> 
> static void intel_dp_mst_info(struct seq_file *m,
>@@ -2639,6 +2628,10 @@
> 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
> 
> 	seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
>+	if (intel_connector->hdcp.shim) {
>+		seq_puts(m, "\tHDCP version: ");
>+		intel_hdcp_info(m, intel_connector);
>+	}
> }
> 
> static void intel_lvds_info(struct seq_file *m,
>@@ -2966,14 +2959,28 @@
> static int i915_wa_registers(struct seq_file *m, void *unused)
> {
> 	struct drm_i915_private *i915 = node_to_i915(m->private);
>-	const struct i915_wa_list *wal = &i915->engine[RCS0]->ctx_wa_list;
>-	struct i915_wa *wa;
>-	unsigned int i;
>+	struct intel_engine_cs *engine;
>+	enum intel_engine_id id;
> 
>-	seq_printf(m, "Workarounds applied: %u\n", wal->count);
>-	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
>-		seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
>-			   i915_mmio_reg_offset(wa->reg), wa->val, wa->mask);
>+	for_each_engine(engine, i915, id) {
>+		const struct i915_wa_list *wal = &engine->ctx_wa_list;
>+		const struct i915_wa *wa;
>+		unsigned int count;
>+
>+		count = wal->count;
>+		if (!count)
>+			continue;
>+
>+		seq_printf(m, "%s: Workarounds applied: %u\n",
>+			   engine->name, count);
>+
>+		for (wa = wal->list; count--; wa++)
>+			seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
>+				   i915_mmio_reg_offset(wa->reg),
>+				   wa->val, wa->mask);
>+
>+		seq_printf(m, "\n");
>+	}
> 
> 	return 0;
> }
>@@ -3620,7 +3627,8 @@
> static int
> i915_wedged_get(void *data, u64 *val)
> {
>-	int ret = i915_terminally_wedged(data);
>+	struct drm_i915_private *i915 = data;
>+	int ret = intel_gt_terminally_wedged(&i915->gt);
> 
> 	switch (ret) {
> 	case -EIO:
>@@ -3640,11 +3648,11 @@
> 	struct drm_i915_private *i915 = data;
> 
> 	/* Flush any previous reset before applying for a new one */
>-	wait_event(i915->gpu_error.reset_queue,
>-		   !test_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags));
>+	wait_event(i915->gt.reset.queue,
>+		   !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags));
> 
>-	i915_handle_error(i915, val, I915_ERROR_CAPTURE,
>-			  "Manually set wedged engine mask = %llx", val);
>+	intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE,
>+			      "Manually set wedged engine mask = %llx", val);
> 	return 0;
> }
> 
>@@ -3687,8 +3695,9 @@
> 		  val, val & DROP_ALL);
> 
> 	if (val & DROP_RESET_ACTIVE &&
>-	    wait_for(intel_engines_are_idle(i915), I915_IDLE_ENGINES_TIMEOUT))
>-		i915_gem_set_wedged(i915);
>+	    wait_for(intel_engines_are_idle(&i915->gt),
>+		     I915_IDLE_ENGINES_TIMEOUT))
>+		intel_gt_set_wedged(&i915->gt);
> 
> 	/* No need to check and wait for gpu resets, only libdrm auto-restarts
> 	 * on ioctls on -EAGAIN. */
>@@ -3723,8 +3732,8 @@
> 		mutex_unlock(&i915->drm.struct_mutex);
> 	}
> 
>-	if (val & DROP_RESET_ACTIVE && i915_terminally_wedged(i915))
>-		i915_handle_error(i915, ALL_ENGINES, 0, NULL);
>+	if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(&i915->gt))
>+		intel_gt_handle_error(&i915->gt, ALL_ENGINES, 0, NULL);
> 
> 	fs_reclaim_acquire(GFP_KERNEL);
> 	if (val & DROP_BOUND)
>@@ -4087,9 +4096,9 @@
> 	/* Synchronize with everything first in case there's been an HPD
> 	 * storm, but we haven't finished handling it in the kernel yet
> 	 */
>-	synchronize_irq(dev_priv->drm.irq);
>+	intel_synchronize_irq(dev_priv);
> 	flush_work(&dev_priv->hotplug.dig_port_work);
>-	flush_work(&dev_priv->hotplug.hotplug_work);
>+	flush_delayed_work(&dev_priv->hotplug.hotplug_work);
> 
> 	seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
> 	seq_printf(m, "Detected: %s\n",
>@@ -4379,7 +4388,6 @@
> 	{"i915_huc_load_status", i915_huc_load_status_info, 0},
> 	{"i915_frequency_info", i915_frequency_info, 0},
> 	{"i915_hangcheck_info", i915_hangcheck_info, 0},
>-	{"i915_reset_info", i915_reset_info, 0},
> 	{"i915_drpc_info", i915_drpc_info, 0},
> 	{"i915_emon_status", i915_emon_status, 0},
> 	{"i915_ring_freq_table", i915_ring_freq_table, 0},
>@@ -4547,7 +4555,6 @@
> {
> 	struct drm_connector *connector = m->private;
> 	struct intel_connector *intel_connector = to_intel_connector(connector);
>-	bool hdcp_cap, hdcp2_cap;
> 
> 	if (connector->status != connector_status_connected)
> 		return -ENODEV;
>@@ -4558,17 +4565,7 @@
> 
> 	seq_printf(m, "%s:%d HDCP version: ", connector->name,
> 		   connector->base.id);
>-	hdcp_cap = intel_hdcp_capable(intel_connector);
>-	hdcp2_cap = intel_hdcp2_capable(intel_connector);
>-
>-	if (hdcp_cap)
>-		seq_puts(m, "HDCP1.4 ");
>-	if (hdcp2_cap)
>-		seq_puts(m, "HDCP2.2 ");
>-
>-	if (!hdcp_cap && !hdcp2_cap)
>-		seq_puts(m, "None");
>-	seq_puts(m, "\n");
>+	intel_hdcp_info(m, intel_connector);
> 
> 	return 0;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_drv.c	2019-08-31 15:01:12.031736183 -0500
>@@ -61,9 +61,11 @@
> 
> #include "gem/i915_gem_context.h"
> #include "gem/i915_gem_ioctls.h"
>+#include "gt/intel_gt.h"
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_reset.h"
> #include "gt/intel_workarounds.h"
>+#include "gt/uc/intel_uc.h"
> 
> #include "i915_debugfs.h"
> #include "i915_drv.h"
>@@ -75,19 +77,18 @@
> #include "intel_csr.h"
> #include "intel_drv.h"
> #include "intel_pm.h"
>-#include "intel_uc.h"
> 
> static struct drm_driver driver;
> 
> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
>-static unsigned int i915_load_fail_count;
>+static unsigned int i915_probe_fail_count;
> 
>-bool __i915_inject_load_failure(const char *func, int line)
>+bool __i915_inject_probe_failure(const char *func, int line)
> {
>-	if (i915_load_fail_count >= i915_modparams.inject_load_failure)
>+	if (i915_probe_fail_count >= i915_modparams.inject_load_failure)
> 		return false;
> 
>-	if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
>+	if (++i915_probe_fail_count == i915_modparams.inject_load_failure) {
> 		DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
> 			 i915_modparams.inject_load_failure, func, line);
> 		i915_modparams.inject_load_failure = 0;
>@@ -99,7 +100,7 @@
> 
> bool i915_error_injected(void)
> {
>-	return i915_load_fail_count && !i915_modparams.inject_load_failure;
>+	return i915_probe_fail_count && !i915_modparams.inject_load_failure;
> }
> 
> #endif
>@@ -219,9 +220,14 @@
> 		WARN_ON(!IS_ICELAKE(dev_priv));
> 		return PCH_ICP;
> 	case INTEL_PCH_MCC_DEVICE_ID_TYPE:
>+	case INTEL_PCH_MCC2_DEVICE_ID_TYPE:
> 		DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
> 		WARN_ON(!IS_ELKHARTLAKE(dev_priv));
> 		return PCH_MCC;
>+	case INTEL_PCH_TGP_DEVICE_ID_TYPE:
>+		DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
>+		WARN_ON(!IS_TIGERLAKE(dev_priv));
>+		return PCH_TGP;
> 	default:
> 		return PCH_NONE;
> 	}
>@@ -249,7 +255,9 @@
> 	 * make an educated guess as to which PCH is really there.
> 	 */
> 
>-	if (IS_ELKHARTLAKE(dev_priv))
>+	if (IS_TIGERLAKE(dev_priv))
>+		id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
>+	else if (IS_ELKHARTLAKE(dev_priv))
> 		id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
> 	else if (IS_ICELAKE(dev_priv))
> 		id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
>@@ -418,7 +426,7 @@
> 		value = sseu->min_eu_in_pool;
> 		break;
> 	case I915_PARAM_HUC_STATUS:
>-		value = intel_huc_check_status(&dev_priv->huc);
>+		value = intel_huc_check_status(&dev_priv->gt.uc.huc);
> 		if (value < 0)
> 			return value;
> 		break;
>@@ -673,13 +681,13 @@
> 	.can_switch = i915_switcheroo_can_switch,
> };
> 
>-static int i915_load_modeset_init(struct drm_device *dev)
>+static int i915_driver_modeset_probe(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct pci_dev *pdev = dev_priv->drm.pdev;
> 	int ret;
> 
>-	if (i915_inject_load_failure())
>+	if (i915_inject_probe_failure())
> 		return -ENODEV;
> 
> 	if (HAS_DISPLAY(dev_priv)) {
>@@ -749,16 +757,16 @@
> 
> cleanup_gem:
> 	i915_gem_suspend(dev_priv);
>-	i915_gem_fini_hw(dev_priv);
>-	i915_gem_fini(dev_priv);
>+	i915_gem_driver_remove(dev_priv);
>+	i915_gem_driver_release(dev_priv);
> cleanup_modeset:
>-	intel_modeset_cleanup(dev);
>+	intel_modeset_driver_remove(dev);
> cleanup_irq:
>-	drm_irq_uninstall(dev);
>+	intel_irq_uninstall(dev_priv);
> 	intel_gmbus_teardown(dev_priv);
> cleanup_csr:
> 	intel_csr_ucode_fini(dev_priv);
>-	intel_power_domains_fini_hw(dev_priv);
>+	intel_power_domains_driver_remove(dev_priv);
> 	vga_switcheroo_unregister_client(pdev);
> cleanup_vga_client:
> 	vga_client_register(pdev, NULL, NULL, NULL);
>@@ -840,15 +848,6 @@
> 	return -ENOMEM;
> }
> 
>-static void i915_engines_cleanup(struct drm_i915_private *i915)
>-{
>-	struct intel_engine_cs *engine;
>-	enum intel_engine_id id;
>-
>-	for_each_engine(engine, i915, id)
>-		kfree(engine);
>-}
>-
> static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
> {
> 	destroy_workqueue(dev_priv->hotplug.dp_wq);
>@@ -882,7 +881,7 @@
> }
> 
> /**
>- * i915_driver_init_early - setup state not requiring device access
>+ * i915_driver_early_probe - setup state not requiring device access
>  * @dev_priv: device private
>  *
>  * Initialize everything that is a "SW-only" state, that is state not
>@@ -891,16 +890,16 @@
>  * system memory allocation, setting up device specific attributes and
>  * function hooks not requiring accessing the device.
>  */
>-static int i915_driver_init_early(struct drm_i915_private *dev_priv)
>+static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> {
> 	int ret = 0;
> 
>-	if (i915_inject_load_failure())
>+	if (i915_inject_probe_failure())
> 		return -ENODEV;
> 
> 	intel_device_info_subplatform_init(dev_priv);
> 
>-	intel_uncore_init_early(&dev_priv->uncore);
>+	intel_uncore_init_early(&dev_priv->uncore, dev_priv);
> 
> 	spin_lock_init(&dev_priv->irq_lock);
> 	spin_lock_init(&dev_priv->gpu_error.lock);
>@@ -920,7 +919,9 @@
> 
> 	ret = i915_workqueues_init(dev_priv);
> 	if (ret < 0)
>-		goto err_engines;
>+		return ret;
>+
>+	intel_gt_init_early(&dev_priv->gt, dev_priv);
> 
> 	ret = i915_gem_init_early(dev_priv);
> 	if (ret < 0)
>@@ -930,14 +931,13 @@
> 	intel_detect_pch(dev_priv);
> 
> 	intel_wopcm_init_early(&dev_priv->wopcm);
>-	intel_uc_init_early(dev_priv);
>+	intel_uc_init_early(&dev_priv->gt.uc);
> 	intel_pm_setup(dev_priv);
> 	intel_init_dpio(dev_priv);
> 	ret = intel_power_domains_init(dev_priv);
> 	if (ret < 0)
> 		goto err_uc;
> 	intel_irq_init(dev_priv);
>-	intel_hangcheck_init(dev_priv);
> 	intel_init_display_hooks(dev_priv);
> 	intel_init_clock_gating_hooks(dev_priv);
> 	intel_init_audio_hooks(dev_priv);
>@@ -948,34 +948,32 @@
> 	return 0;
> 
> err_uc:
>-	intel_uc_cleanup_early(dev_priv);
>+	intel_uc_cleanup_early(&dev_priv->gt.uc);
> 	i915_gem_cleanup_early(dev_priv);
> err_workqueues:
> 	i915_workqueues_cleanup(dev_priv);
>-err_engines:
>-	i915_engines_cleanup(dev_priv);
> 	return ret;
> }
> 
> /**
>- * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
>+ * i915_driver_late_release - cleanup the setup done in
>+ *			       i915_driver_early_probe()
>  * @dev_priv: device private
>  */
>-static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
>+static void i915_driver_late_release(struct drm_i915_private *dev_priv)
> {
> 	intel_irq_fini(dev_priv);
> 	intel_power_domains_cleanup(dev_priv);
>-	intel_uc_cleanup_early(dev_priv);
>+	intel_uc_cleanup_early(&dev_priv->gt.uc);
> 	i915_gem_cleanup_early(dev_priv);
> 	i915_workqueues_cleanup(dev_priv);
>-	i915_engines_cleanup(dev_priv);
> 
> 	pm_qos_remove_request(&dev_priv->sb_qos);
> 	mutex_destroy(&dev_priv->sb_lock);
> }
> 
> /**
>- * i915_driver_init_mmio - setup device MMIO
>+ * i915_driver_mmio_probe - setup device MMIO
>  * @dev_priv: device private
>  *
>  * Setup minimal device state necessary for MMIO accesses later in the
>@@ -983,11 +981,11 @@
>  * side effects or exposing the driver via kernel internal or user space
>  * interfaces.
>  */
>-static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
>+static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
> {
> 	int ret;
> 
>-	if (i915_inject_load_failure())
>+	if (i915_inject_probe_failure())
> 		return -ENODEV;
> 
> 	if (i915_get_bridge_dev(dev_priv))
>@@ -1004,7 +1002,7 @@
> 
> 	intel_uncore_prune_mmio_domains(&dev_priv->uncore);
> 
>-	intel_uc_init_mmio(dev_priv);
>+	intel_uc_init_mmio(&dev_priv->gt.uc);
> 
> 	ret = intel_engines_init_mmio(dev_priv);
> 	if (ret)
>@@ -1024,11 +1022,12 @@
> }
> 
> /**
>- * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
>+ * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
>  * @dev_priv: device private
>  */
>-static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
>+static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
> {
>+	intel_engines_cleanup(dev_priv);
> 	intel_teardown_mchbar(dev_priv);
> 	intel_uncore_fini_mmio(&dev_priv->uncore);
> 	pci_dev_put(dev_priv->bridge_dev);
>@@ -1520,18 +1519,18 @@
> }
> 
> /**
>- * i915_driver_init_hw - setup state requiring device access
>+ * i915_driver_hw_probe - setup state requiring device access
>  * @dev_priv: device private
>  *
>  * Setup state that requires accessing the device, but doesn't require
>  * exposing the driver via kernel internal or userspace interfaces.
>  */
>-static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
>+static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
> {
> 	struct pci_dev *pdev = dev_priv->drm.pdev;
> 	int ret;
> 
>-	if (i915_inject_load_failure())
>+	if (i915_inject_probe_failure())
> 		return -ENODEV;
> 
> 	intel_device_info_runtime_init(dev_priv);
>@@ -1590,6 +1589,8 @@
> 	if (ret)
> 		goto err_ggtt;
> 
>+	intel_gt_init_hw(dev_priv);
>+
> 	ret = i915_ggtt_enable_hw(dev_priv);
> 	if (ret) {
> 		DRM_ERROR("failed to enable GGTT\n");
>@@ -1629,7 +1630,8 @@
> 	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
> 			   PM_QOS_DEFAULT_VALUE);
> 
>-	intel_uncore_sanitize(dev_priv);
>+	/* BIOS often leaves RC6 enabled, but disable it for hw init */
>+	intel_sanitize_gt_powersave(dev_priv);
> 
> 	intel_gt_init_workarounds(dev_priv);
> 
>@@ -1677,17 +1679,17 @@
> 		pci_disable_msi(pdev);
> 	pm_qos_remove_request(&dev_priv->pm_qos);
> err_ggtt:
>-	i915_ggtt_cleanup_hw(dev_priv);
>+	i915_ggtt_driver_release(dev_priv);
> err_perf:
> 	i915_perf_fini(dev_priv);
> 	return ret;
> }
> 
> /**
>- * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
>+ * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
>  * @dev_priv: device private
>  */
>-static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
>+static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
> {
> 	struct pci_dev *pdev = dev_priv->drm.pdev;
> 
>@@ -1863,17 +1865,17 @@
> }
> 
> /**
>- * i915_driver_load - setup chip and create an initial config
>+ * i915_driver_probe - setup chip and create an initial config
>  * @pdev: PCI device
>  * @ent: matching PCI ID entry
>  *
>- * The driver load routine has to do several things:
>+ * The driver probe routine has to do several things:
>  *   - drive output discovery via intel_modeset_init()
>  *   - initialize the memory manager
>  *   - allocate initial config memory
>  *   - setup the DRM framebuffer with the allocated memory
>  */
>-int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
>+int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> {
> 	const struct intel_device_info *match_info =
> 		(struct intel_device_info *)ent->driver_data;
>@@ -1892,21 +1894,23 @@
> 	if (ret)
> 		goto out_fini;
> 
>-	ret = i915_driver_init_early(dev_priv);
>+	ret = i915_driver_early_probe(dev_priv);
> 	if (ret < 0)
> 		goto out_pci_disable;
> 
> 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> 
>-	ret = i915_driver_init_mmio(dev_priv);
>+	i915_detect_vgpu(dev_priv);
>+
>+	ret = i915_driver_mmio_probe(dev_priv);
> 	if (ret < 0)
> 		goto out_runtime_pm_put;
> 
>-	ret = i915_driver_init_hw(dev_priv);
>+	ret = i915_driver_hw_probe(dev_priv);
> 	if (ret < 0)
> 		goto out_cleanup_mmio;
> 
>-	ret = i915_load_modeset_init(&dev_priv->drm);
>+	ret = i915_driver_modeset_probe(&dev_priv->drm);
> 	if (ret < 0)
> 		goto out_cleanup_hw;
> 
>@@ -1919,22 +1923,25 @@
> 	return 0;
> 
> out_cleanup_hw:
>-	i915_driver_cleanup_hw(dev_priv);
>-	i915_ggtt_cleanup_hw(dev_priv);
>+	i915_driver_hw_remove(dev_priv);
>+	i915_ggtt_driver_release(dev_priv);
>+
>+	/* Paranoia: make sure we have disabled everything before we exit. */
>+	intel_sanitize_gt_powersave(dev_priv);
> out_cleanup_mmio:
>-	i915_driver_cleanup_mmio(dev_priv);
>+	i915_driver_mmio_release(dev_priv);
> out_runtime_pm_put:
> 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>-	i915_driver_cleanup_early(dev_priv);
>+	i915_driver_late_release(dev_priv);
> out_pci_disable:
> 	pci_disable_device(pdev);
> out_fini:
>-	i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
>+	i915_probe_error(dev_priv, "Device initialization failed (%d)\n", ret);
> 	i915_driver_destroy(dev_priv);
> 	return ret;
> }
> 
>-void i915_driver_unload(struct drm_device *dev)
>+void i915_driver_remove(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct pci_dev *pdev = dev_priv->drm.pdev;
>@@ -1948,7 +1955,7 @@
> 	 * all in-flight requests so that we can quickly unbind the active
> 	 * resources.
> 	 */
>-	i915_gem_set_wedged(dev_priv);
>+	intel_gt_set_wedged(&dev_priv->gt);
> 
> 	/* Flush any external code that still may be under the RCU lock */
> 	synchronize_rcu();
>@@ -1957,11 +1964,11 @@
> 
> 	drm_atomic_helper_shutdown(dev);
> 
>-	intel_gvt_cleanup(dev_priv);
>+	intel_gvt_driver_remove(dev_priv);
> 
>-	intel_modeset_cleanup(dev);
>+	intel_modeset_driver_remove(dev);
> 
>-	intel_bios_cleanup(dev_priv);
>+	intel_bios_driver_remove(dev_priv);
> 
> 	vga_switcheroo_unregister_client(pdev);
> 	vga_client_register(pdev, NULL, NULL, NULL);
>@@ -1969,14 +1976,14 @@
> 	intel_csr_ucode_fini(dev_priv);
> 
> 	/* Free error state after interrupts are fully disabled. */
>-	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
>+	cancel_delayed_work_sync(&dev_priv->gt.hangcheck.work);
> 	i915_reset_error_state(dev_priv);
> 
>-	i915_gem_fini_hw(dev_priv);
>+	i915_gem_driver_remove(dev_priv);
> 
>-	intel_power_domains_fini_hw(dev_priv);
>+	intel_power_domains_driver_remove(dev_priv);
> 
>-	i915_driver_cleanup_hw(dev_priv);
>+	i915_driver_hw_remove(dev_priv);
> 
> 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> }
>@@ -1988,15 +1995,19 @@
> 
> 	disable_rpm_wakeref_asserts(rpm);
> 
>-	i915_gem_fini(dev_priv);
>+	i915_gem_driver_release(dev_priv);
>+
>+	i915_ggtt_driver_release(dev_priv);
> 
>-	i915_ggtt_cleanup_hw(dev_priv);
>-	i915_driver_cleanup_mmio(dev_priv);
>+	/* Paranoia: make sure we have disabled everything before we exit. */
>+	intel_sanitize_gt_powersave(dev_priv);
>+
>+	i915_driver_mmio_release(dev_priv);
> 
> 	enable_rpm_wakeref_asserts(rpm);
>-	intel_runtime_pm_cleanup(rpm);
>+	intel_runtime_pm_driver_release(rpm);
> 
>-	i915_driver_cleanup_early(dev_priv);
>+	i915_driver_late_release(dev_priv);
> 	i915_driver_destroy(dev_priv);
> }
> 
>@@ -2189,7 +2200,7 @@
> out:
> 	enable_rpm_wakeref_asserts(rpm);
> 	if (!dev_priv->uncore.user_forcewake.count)
>-		intel_runtime_pm_cleanup(rpm);
>+		intel_runtime_pm_driver_release(rpm);
> 
> 	return ret;
> }
>@@ -2348,7 +2359,7 @@
> 
> 	intel_uncore_resume_early(&dev_priv->uncore);
> 
>-	i915_check_and_clear_faults(dev_priv);
>+	intel_gt_check_and_clear_faults(&dev_priv->gt);
> 
> 	if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
> 		gen9_sanitize_dc_state(dev_priv);
>@@ -2357,11 +2368,11 @@
> 		hsw_disable_pc8(dev_priv);
> 	}
> 
>-	intel_uncore_sanitize(dev_priv);
>+	intel_sanitize_gt_powersave(dev_priv);
> 
> 	intel_power_domains_resume(dev_priv);
> 
>-	intel_gt_sanitize(dev_priv, true);
>+	intel_gt_sanitize(&dev_priv->gt, true);
> 
> 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> 
>@@ -2384,8 +2395,7 @@
> 
> static int i915_pm_prepare(struct device *kdev)
> {
>-	struct pci_dev *pdev = to_pci_dev(kdev);
>-	struct drm_device *dev = pci_get_drvdata(pdev);
>+	struct drm_device *dev = dev_get_drvdata(kdev);
> 
> 	if (!dev) {
> 		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
>@@ -2400,8 +2410,7 @@
> 
> static int i915_pm_suspend(struct device *kdev)
> {
>-	struct pci_dev *pdev = to_pci_dev(kdev);
>-	struct drm_device *dev = pci_get_drvdata(pdev);
>+	struct drm_device *dev = dev_get_drvdata(kdev);
> 
> 	if (!dev) {
> 		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
>@@ -2895,8 +2904,7 @@
> 
> static int intel_runtime_suspend(struct device *kdev)
> {
>-	struct pci_dev *pdev = to_pci_dev(kdev);
>-	struct drm_device *dev = pci_get_drvdata(pdev);
>+	struct drm_device *dev = dev_get_drvdata(kdev);
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
> 	int ret;
>@@ -2917,7 +2925,7 @@
> 	 */
> 	i915_gem_runtime_suspend(dev_priv);
> 
>-	intel_uc_runtime_suspend(dev_priv);
>+	intel_uc_runtime_suspend(&dev_priv->gt.uc);
> 
> 	intel_runtime_pm_disable_interrupts(dev_priv);
> 
>@@ -2942,9 +2950,9 @@
> 
> 		intel_runtime_pm_enable_interrupts(dev_priv);
> 
>-		intel_uc_resume(dev_priv);
>+		intel_uc_resume(&dev_priv->gt.uc);
> 
>-		i915_gem_init_swizzling(dev_priv);
>+		intel_gt_init_swizzling(&dev_priv->gt);
> 		i915_gem_restore_fences(dev_priv);
> 
> 		enable_rpm_wakeref_asserts(rpm);
>@@ -2953,7 +2961,7 @@
> 	}
> 
> 	enable_rpm_wakeref_asserts(rpm);
>-	intel_runtime_pm_cleanup(rpm);
>+	intel_runtime_pm_driver_release(rpm);
> 
> 	if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
> 		DRM_ERROR("Unclaimed access detected prior to suspending\n");
>@@ -2994,8 +3002,7 @@
> 
> static int intel_runtime_resume(struct device *kdev)
> {
>-	struct pci_dev *pdev = to_pci_dev(kdev);
>-	struct drm_device *dev = pci_get_drvdata(pdev);
>+	struct drm_device *dev = dev_get_drvdata(kdev);
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
> 	int ret = 0;
>@@ -3040,13 +3047,13 @@
> 
> 	intel_runtime_pm_enable_interrupts(dev_priv);
> 
>-	intel_uc_resume(dev_priv);
>+	intel_uc_resume(&dev_priv->gt.uc);
> 
> 	/*
> 	 * No point of rolling back things in case of an error, as the best
> 	 * we can do is to hope that things will still work (and disable RPM).
> 	 */
>-	i915_gem_init_swizzling(dev_priv);
>+	intel_gt_init_swizzling(&dev_priv->gt);
> 	i915_gem_restore_fences(dev_priv);
> 
> 	/*
>@@ -3188,9 +3195,9 @@
> 	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
> };
>@@ -3200,7 +3207,7 @@
> 	 * deal with them for Intel hardware.
> 	 */
> 	.driver_features =
>-	    DRIVER_GEM | DRIVER_PRIME |
>+	    DRIVER_GEM |
> 	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
> 	.release = i915_driver_release,
> 	.open = i915_driver_open,
>@@ -3216,6 +3223,9 @@
> 	.gem_prime_export = i915_gem_prime_export,
> 	.gem_prime_import = i915_gem_prime_import,
> 
>+	.get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
>+	.get_scanout_position = i915_get_crtc_scanoutpos,
>+
> 	.dumb_create = i915_gem_dumb_create,
> 	.dumb_map_offset = i915_gem_mmap_gtt,
> 	.ioctls = i915_ioctls,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_drv.h	2019-08-31 15:01:12.032736184 -0500
>@@ -72,11 +72,12 @@
> 
> #include "gt/intel_lrc.h"
> #include "gt/intel_engine.h"
>+#include "gt/intel_gt_types.h"
> #include "gt/intel_workarounds.h"
>+#include "gt/uc/intel_uc.h"
> 
> #include "intel_device_info.h"
> #include "intel_runtime_pm.h"
>-#include "intel_uc.h"
> #include "intel_uncore.h"
> #include "intel_wakeref.h"
> #include "intel_wopcm.h"
>@@ -88,7 +89,7 @@
> #include "i915_gpu_error.h"
> #include "i915_request.h"
> #include "i915_scheduler.h"
>-#include "i915_timeline.h"
>+#include "gt/intel_timeline.h"
> #include "i915_vma.h"
> 
> #include "intel_gvt.h"
>@@ -98,8 +99,8 @@
> 
> #define DRIVER_NAME		"i915"
> #define DRIVER_DESC		"Intel Graphics"
>-#define DRIVER_DATE		"20190619"
>-#define DRIVER_TIMESTAMP	1560947544
>+#define DRIVER_DATE		"20190730"
>+#define DRIVER_TIMESTAMP	1564512624
> 
> /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
>  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
>@@ -121,20 +122,20 @@
> 
> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
> 
>-bool __i915_inject_load_failure(const char *func, int line);
>-#define i915_inject_load_failure() \
>-	__i915_inject_load_failure(__func__, __LINE__)
>+bool __i915_inject_probe_failure(const char *func, int line);
>+#define i915_inject_probe_failure() \
>+	__i915_inject_probe_failure(__func__, __LINE__)
> 
> bool i915_error_injected(void);
> 
> #else
> 
>-#define i915_inject_load_failure() false
>+#define i915_inject_probe_failure() false
> #define i915_error_injected() false
> 
> #endif
> 
>-#define i915_load_error(i915, fmt, ...)					 \
>+#define i915_probe_error(i915, fmt, ...)				   \
> 	__i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
> 		      fmt, ##__VA_ARGS__)
> 
>@@ -162,7 +163,7 @@
> #define HPD_STORM_DEFAULT_THRESHOLD 50
> 
> struct i915_hotplug {
>-	struct work_struct hotplug_work;
>+	struct delayed_work hotplug_work;
> 
> 	struct {
> 		unsigned long last_jiffies;
>@@ -174,6 +175,7 @@
> 		} state;
> 	} stats[HPD_NUM_PINS];
> 	u32 event_bits;
>+	u32 retry_bits;
> 	struct delayed_work reenable_work;
> 
> 	u32 long_port_mask;
>@@ -286,14 +288,14 @@
> 			  enum pipe pipe);
> 	int (*get_fifo_size)(struct drm_i915_private *dev_priv,
> 			     enum i9xx_plane_id i9xx_plane);
>-	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
>-	int (*compute_intermediate_wm)(struct intel_crtc_state *newstate);
>+	int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
>+	int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
> 	void (*initial_watermarks)(struct intel_atomic_state *state,
>-				   struct intel_crtc_state *cstate);
>+				   struct intel_crtc_state *crtc_state);
> 	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
>-					 struct intel_crtc_state *cstate);
>+					 struct intel_crtc_state *crtc_state);
> 	void (*optimize_watermarks)(struct intel_atomic_state *state,
>-				    struct intel_crtc_state *cstate);
>+				    struct intel_crtc_state *crtc_state);
> 	int (*compute_global_watermarks)(struct intel_atomic_state *state);
> 	void (*update_wm)(struct intel_crtc *crtc);
> 	int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
>@@ -306,10 +308,10 @@
> 	int (*crtc_compute_clock)(struct intel_crtc *crtc,
> 				  struct intel_crtc_state *crtc_state);
> 	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
>-			    struct drm_atomic_state *old_state);
>+			    struct intel_atomic_state *old_state);
> 	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
>-			     struct drm_atomic_state *old_state);
>-	void (*update_crtcs)(struct drm_atomic_state *state);
>+			     struct intel_atomic_state *old_state);
>+	void (*update_crtcs)(struct intel_atomic_state *state);
> 	void (*audio_codec_enable)(struct intel_encoder *encoder,
> 				   const struct intel_crtc_state *crtc_state,
> 				   const struct drm_connector_state *conn_state);
>@@ -535,6 +537,7 @@
> 	PCH_CNP,        /* Cannon/Comet Lake PCH */
> 	PCH_ICP,	/* Ice Lake PCH */
> 	PCH_MCC,        /* Mule Creek Canyon PCH */
>+	PCH_TGP,	/* Tiger Lake PCH */
> };
> 
> #define QUIRK_LVDS_SSC_DISABLE (1<<1)
>@@ -781,9 +784,6 @@
> 	 */
> 	struct vfsmount *gemfs;
> 
>-	/** PPGTT used for aliasing the PPGTT with the GTT */
>-	struct i915_ppgtt *aliasing_ppgtt;
>-
> 	struct notifier_block oom_notifier;
> 	struct notifier_block vmap_notifier;
> 	struct shrinker shrinker;
>@@ -1347,9 +1347,6 @@
> 
> 	struct intel_wopcm wopcm;
> 
>-	struct intel_huc huc;
>-	struct intel_guc guc;
>-
> 	struct intel_csr csr;
> 
> 	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
>@@ -1377,8 +1374,6 @@
> 	struct intel_engine_cs *engine[I915_NUM_ENGINES];
> 	/* Context used internally to idle the GPU and setup initial state */
> 	struct i915_gem_context *kernel_context;
>-	/* Context only to be used for injecting preemption commands */
>-	struct i915_gem_context *preempt_context;
> 	struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
> 					    [MAX_ENGINE_INSTANCE + 1];
> 
>@@ -1402,10 +1397,7 @@
> 		u32 de_irq_mask[I915_MAX_PIPES];
> 	};
> 	u32 gt_irq_mask;
>-	u32 pm_imr;
>-	u32 pm_ier;
> 	u32 pm_rps_events;
>-	u32 pm_guc_events;
> 	u32 pipestat_irq_mask[I915_MAX_PIPES];
> 
> 	struct i915_hotplug hotplug;
>@@ -1488,8 +1480,6 @@
> 	DECLARE_HASHTABLE(mm_structs, 7);
> 	struct mutex mm_lock;
> 
>-	struct intel_ppat ppat;
>-
> 	/* Kernel Modesetting */
> 
> 	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
>@@ -1645,7 +1635,7 @@
> 		/*
> 		 * Should be held around atomic WM register writing; also
> 		 * protects * intel_crtc->wm.active and
>-		 * cstate->wm.need_postvbl_update.
>+		 * crtc_state->wm.need_postvbl_update.
> 		 */
> 		struct mutex wm_mutex;
> 
>@@ -1825,38 +1815,7 @@
> 	} perf;
> 
> 	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
>-	struct {
>-		struct i915_gt_timelines {
>-			struct mutex mutex; /* protects list, tainted by GPU */
>-			struct list_head active_list;
>-
>-			/* Pack multiple timelines' seqnos into the same page */
>-			spinlock_t hwsp_lock;
>-			struct list_head hwsp_free_list;
>-		} timelines;
>-
>-		struct list_head active_rings;
>-
>-		struct intel_wakeref wakeref;
>-
>-		struct list_head closed_vma;
>-		spinlock_t closed_lock; /* guards the list of closed_vma */
>-
>-		/**
>-		 * Is the GPU currently considered idle, or busy executing
>-		 * userspace requests? Whilst idle, we allow runtime power
>-		 * management to power down the hardware and display clocks.
>-		 * In order to reduce the effect on performance, there
>-		 * is a slight delay before we do so.
>-		 */
>-		intel_wakeref_t awake;
>-
>-		struct blocking_notifier_head pm_notifications;
>-
>-		ktime_t last_init_time;
>-
>-		struct i915_vma *scratch;
>-	} gt;
>+	struct intel_gt gt;
> 
> 	struct {
> 		struct notifier_block pm_notifier;
>@@ -1941,21 +1900,6 @@
> 	return container_of(wopcm, struct drm_i915_private, wopcm);
> }
> 
>-static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
>-{
>-	return container_of(guc, struct drm_i915_private, guc);
>-}
>-
>-static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
>-{
>-	return container_of(huc, struct drm_i915_private, huc);
>-}
>-
>-static inline struct drm_i915_private *uncore_to_i915(struct intel_uncore *uncore)
>-{
>-	return container_of(uncore, struct drm_i915_private, uncore);
>-}
>-
> /* Simple iterator over all initialised engines */
> #define for_each_engine(engine__, dev_priv__, id__) \
> 	for ((id__) = 0; \
>@@ -2127,6 +2071,7 @@
> #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> #define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
>+#define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
>@@ -2323,23 +2268,12 @@
> 
> #define HAS_IPC(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ipc)
> 
>-/*
>- * For now, anything with a GuC requires uCode loading, and then supports
>- * command submission once loaded. But these are logically independent
>- * properties, so we have separate macros to test them.
>- */
>-#define HAS_GUC(dev_priv)	(INTEL_INFO(dev_priv)->has_guc)
>-#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
>-#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
>-
>-/* For now, anything with a GuC has also HuC */
>-#define HAS_HUC(dev_priv)	(HAS_GUC(dev_priv))
>-#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
>-
>-/* Having a GuC is not the same as using a GuC */
>-#define USES_GUC(dev_priv)		intel_uc_is_using_guc(dev_priv)
>-#define USES_GUC_SUBMISSION(dev_priv)	intel_uc_is_using_guc_submission(dev_priv)
>-#define USES_HUC(dev_priv)		intel_uc_is_using_huc(dev_priv)
>+#define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
>+
>+/* Having GuC/HuC is not the same as using GuC/HuC */
>+#define USES_GUC(dev_priv)		intel_uc_is_using_guc(&(dev_priv)->gt.uc)
>+#define USES_GUC_SUBMISSION(dev_priv)	intel_uc_is_using_guc_submission(&(dev_priv)->gt.uc)
>+#define USES_HUC(dev_priv)		intel_uc_is_using_huc(&(dev_priv)->gt.uc)
> 
> #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
> 
>@@ -2359,6 +2293,8 @@
> #define INTEL_PCH_CMP_DEVICE_ID_TYPE		0x0280
> #define INTEL_PCH_ICP_DEVICE_ID_TYPE		0x3480
> #define INTEL_PCH_MCC_DEVICE_ID_TYPE		0x4B00
>+#define INTEL_PCH_MCC2_DEVICE_ID_TYPE		0x3880
>+#define INTEL_PCH_TGP_DEVICE_ID_TYPE		0xA080
> #define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
> #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
> #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
>@@ -2366,6 +2302,7 @@
> #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
> #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
>+#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
> #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
> #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
> #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
>@@ -2426,40 +2363,18 @@
> 	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
> 
> #ifdef CONFIG_COMPAT
>-extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
>-			      unsigned long arg);
>+long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
> #else
> #define i915_compat_ioctl NULL
> #endif
> extern const struct dev_pm_ops i915_pm_ops;
> 
>-extern int i915_driver_load(struct pci_dev *pdev,
>-			    const struct pci_device_id *ent);
>-extern void i915_driver_unload(struct drm_device *dev);
>+int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
>+void i915_driver_remove(struct drm_device *dev);
> 
>-extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
>-extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
>+void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
> int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
> 
>-u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
>-
>-static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
>-{
>-	unsigned long delay;
>-
>-	if (unlikely(!i915_modparams.enable_hangcheck))
>-		return;
>-
>-	/* Don't continually defer the hangcheck so that it is always run at
>-	 * least once after work has been scheduled on any ring. Otherwise,
>-	 * we will ignore a hung ring if a second ring is kept busy.
>-	 */
>-
>-	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
>-	queue_delayed_work(system_long_wq,
>-			   &dev_priv->gpu_error.hangcheck_work, delay);
>-}
>-
> static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
> {
> 	return dev_priv->gvt;
>@@ -2481,18 +2396,17 @@
> 
> static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
> {
>-	if (!atomic_read(&i915->mm.free_count))
>-		return;
>-
>-	/* A single pass should suffice to release all the freed objects (along
>+	/*
>+	 * A single pass should suffice to release all the freed objects (along
> 	 * most call paths) , but be a little more paranoid in that freeing
> 	 * the objects does take a little amount of time, during which the rcu
> 	 * callbacks could have added new objects into the freed list, and
> 	 * armed the work again.
> 	 */
>-	do {
>+	while (atomic_read(&i915->mm.free_count)) {
>+		flush_work(&i915->mm.free_work);
> 		rcu_barrier();
>-	} while (flush_work(&i915->mm.free_work));
>+	}
> }
> 
> static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
>@@ -2510,6 +2424,7 @@
> 	 */
> 	int pass = 3;
> 	do {
>+		flush_workqueue(i915->wq);
> 		rcu_barrier();
> 		i915_gem_drain_freed_objects(i915);
> 	} while (--pass);
>@@ -2523,7 +2438,9 @@
> 			 u64 alignment,
> 			 u64 flags);
> 
>-int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
>+int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
>+			   unsigned long flags);
>+#define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
> 
> void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
> 
>@@ -2546,36 +2463,22 @@
> 
> int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
> 
>-static inline bool __i915_wedged(struct i915_gpu_error *error)
>-{
>-	return unlikely(test_bit(I915_WEDGED, &error->flags));
>-}
>-
>-static inline bool i915_reset_failed(struct drm_i915_private *i915)
>-{
>-	return __i915_wedged(&i915->gpu_error);
>-}
>-
> static inline u32 i915_reset_count(struct i915_gpu_error *error)
> {
>-	return READ_ONCE(error->reset_count);
>+	return atomic_read(&error->reset_count);
> }
> 
> static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
> 					  struct intel_engine_cs *engine)
> {
>-	return READ_ONCE(error->reset_engine_count[engine->id]);
>+	return atomic_read(&error->reset_engine_count[engine->uabi_class]);
> }
> 
>-void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
>-bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
>-
> void i915_gem_init_mmio(struct drm_i915_private *i915);
> int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
> int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
>-void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
>-void i915_gem_fini_hw(struct drm_i915_private *dev_priv);
>-void i915_gem_fini(struct drm_i915_private *dev_priv);
>+void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
>+void i915_gem_driver_release(struct drm_i915_private *dev_priv);
> int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
> 			   unsigned int flags, long timeout);
> void i915_gem_suspend(struct drm_i915_private *dev_priv);
>@@ -2592,8 +2495,7 @@
> struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
> 				struct dma_buf *dma_buf);
> 
>-struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
>-				struct drm_gem_object *gem_obj, int flags);
>+struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
> 
> static inline struct i915_gem_context *
> __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
>@@ -2636,16 +2538,6 @@
> 					 unsigned int flags);
> int i915_gem_evict_vm(struct i915_address_space *vm);
> 
>-void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
>-
>-/* belongs in i915_gem_gtt.h */
>-static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
>-{
>-	wmb();
>-	if (INTEL_GEN(dev_priv) < 6)
>-		intel_gtt_chipset_flush();
>-}
>-
> /* i915_gem_stolen.c */
> int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
> 				struct drm_mm_node *node, u64 size,
>@@ -2717,14 +2609,14 @@
> 			    bool is_master);
> 
> /* i915_perf.c */
>-extern void i915_perf_init(struct drm_i915_private *dev_priv);
>-extern void i915_perf_fini(struct drm_i915_private *dev_priv);
>-extern void i915_perf_register(struct drm_i915_private *dev_priv);
>-extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
>+void i915_perf_init(struct drm_i915_private *dev_priv);
>+void i915_perf_fini(struct drm_i915_private *dev_priv);
>+void i915_perf_register(struct drm_i915_private *dev_priv);
>+void i915_perf_unregister(struct drm_i915_private *dev_priv);
> 
> /* i915_suspend.c */
>-extern int i915_save_state(struct drm_i915_private *dev_priv);
>-extern int i915_restore_state(struct drm_i915_private *dev_priv);
>+int i915_save_state(struct drm_i915_private *dev_priv);
>+int i915_restore_state(struct drm_i915_private *dev_priv);
> 
> /* i915_sysfs.c */
> void i915_setup_sysfs(struct drm_i915_private *dev_priv);
>@@ -2738,23 +2630,22 @@
> }
> 
> /* modesetting */
>-extern void intel_modeset_init_hw(struct drm_device *dev);
>-extern int intel_modeset_init(struct drm_device *dev);
>-extern void intel_modeset_cleanup(struct drm_device *dev);
>-extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
>-				       bool state);
>-extern void intel_display_resume(struct drm_device *dev);
>-extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
>-extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
>-extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
>+void intel_modeset_init_hw(struct drm_device *dev);
>+int intel_modeset_init(struct drm_device *dev);
>+void intel_modeset_driver_remove(struct drm_device *dev);
>+int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state);
>+void intel_display_resume(struct drm_device *dev);
>+void i915_redisable_vga(struct drm_i915_private *dev_priv);
>+void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
>+void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
> 
> int i915_reg_read_ioctl(struct drm_device *dev, void *data,
> 			struct drm_file *file);
> 
>-extern struct intel_display_error_state *
>+struct intel_display_error_state *
> intel_display_capture_error_state(struct drm_i915_private *dev_priv);
>-extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
>-					    struct intel_display_error_state *error);
>+void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
>+				     struct intel_display_error_state *error);
> 
> #define __I915_REG_OP(op__, dev_priv__, ...) \
> 	intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
>@@ -2830,11 +2721,6 @@
> 		return I915_HWS_CSB_WRITE_INDEX;
> }
> 
>-static inline u32 i915_scratch_offset(const struct drm_i915_private *i915)
>-{
>-	return i915_ggtt_offset(i915->gt.scratch);
>-}
>-
> static inline enum i915_map_type
> i915_coherent_map_type(struct drm_i915_private *i915)
> {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_fixed.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_fixed.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_fixed.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_fixed.h	2019-08-31 15:01:12.032736184 -0500
>@@ -6,6 +6,11 @@
> #ifndef _I915_FIXED_H_
> #define _I915_FIXED_H_
> 
>+#include <linux/bug.h>
>+#include <linux/kernel.h>
>+#include <linux/math64.h>
>+#include <linux/types.h>
>+
> typedef struct {
> 	u32 val;
> } uint_fixed_16_16_t;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_batch_pool.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_batch_pool.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_batch_pool.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_batch_pool.c	2019-08-31 15:01:12.032736184 -0500
>@@ -94,34 +94,26 @@
> 	list = &pool->cache_list[n];
> 
> 	list_for_each_entry(obj, list, batch_pool_link) {
>-		/* The batches are strictly LRU ordered */
>-		if (i915_gem_object_is_active(obj)) {
>-			struct reservation_object *resv = obj->base.resv;
>-
>-			if (!reservation_object_test_signaled_rcu(resv, true))
>-				break;
>+		struct reservation_object *resv = obj->base.resv;
> 
>-			i915_retire_requests(pool->engine->i915);
>-			GEM_BUG_ON(i915_gem_object_is_active(obj));
>+		/* The batches are strictly LRU ordered */
>+		if (!reservation_object_test_signaled_rcu(resv, true))
>+			break;
> 
>-			/*
>-			 * The object is now idle, clear the array of shared
>-			 * fences before we add a new request. Although, we
>-			 * remain on the same engine, we may be on a different
>-			 * timeline and so may continually grow the array,
>-			 * trapping a reference to all the old fences, rather
>-			 * than replace the existing fence.
>-			 */
>-			if (rcu_access_pointer(resv->fence)) {
>-				reservation_object_lock(resv, NULL);
>-				reservation_object_add_excl_fence(resv, NULL);
>-				reservation_object_unlock(resv);
>-			}
>+		/*
>+		 * The object is now idle, clear the array of shared
>+		 * fences before we add a new request. Although, we
>+		 * remain on the same engine, we may be on a different
>+		 * timeline and so may continually grow the array,
>+		 * trapping a reference to all the old fences, rather
>+		 * than replace the existing fence.
>+		 */
>+		if (rcu_access_pointer(resv->fence)) {
>+			reservation_object_lock(resv, NULL);
>+			reservation_object_add_excl_fence(resv, NULL);
>+			reservation_object_unlock(resv);
> 		}
> 
>-		GEM_BUG_ON(!reservation_object_test_signaled_rcu(obj->base.resv,
>-								 true));
>-
> 		if (obj->base.size >= size)
> 			goto found;
> 	}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem.c	2019-08-31 15:01:12.032736184 -0500
>@@ -46,9 +46,11 @@
> #include "gem/i915_gem_ioctls.h"
> #include "gem/i915_gem_pm.h"
> #include "gem/i915_gemfs.h"
>+#include "gt/intel_gt.h"
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_mocs.h"
> #include "gt/intel_reset.h"
>+#include "gt/intel_renderstate.h"
> #include "gt/intel_workarounds.h"
> 
> #include "i915_drv.h"
>@@ -100,7 +102,8 @@
> 	return 0;
> }
> 
>-int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
>+int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
>+			   unsigned long flags)
> {
> 	struct i915_vma *vma;
> 	LIST_HEAD(still_in_list);
>@@ -115,7 +118,10 @@
> 		list_move_tail(&vma->obj_link, &still_in_list);
> 		spin_unlock(&obj->vma.lock);
> 
>-		ret = i915_vma_unbind(vma);
>+		ret = -EBUSY;
>+		if (flags & I915_GEM_OBJECT_UNBIND_ACTIVE ||
>+		    !i915_vma_is_active(vma))
>+			ret = i915_vma_unbind(vma);
> 
> 		spin_lock(&obj->vma.lock);
> 	}
>@@ -141,7 +147,7 @@
> 		return -EFAULT;
> 
> 	drm_clflush_virt_range(vaddr, args->size);
>-	i915_gem_chipset_flush(to_i915(obj->base.dev));
>+	intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
> 
> 	intel_fb_obj_flush(obj, ORIGIN_CPU);
> 	return 0;
>@@ -232,46 +238,6 @@
> 			       &args->size, &args->handle);
> }
> 
>-void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv)
>-{
>-	intel_wakeref_t wakeref;
>-
>-	/*
>-	 * No actual flushing is required for the GTT write domain for reads
>-	 * from the GTT domain. Writes to it "immediately" go to main memory
>-	 * as far as we know, so there's no chipset flush. It also doesn't
>-	 * land in the GPU render cache.
>-	 *
>-	 * However, we do have to enforce the order so that all writes through
>-	 * the GTT land before any writes to the device, such as updates to
>-	 * the GATT itself.
>-	 *
>-	 * We also have to wait a bit for the writes to land from the GTT.
>-	 * An uncached read (i.e. mmio) seems to be ideal for the round-trip
>-	 * timing. This issue has only been observed when switching quickly
>-	 * between GTT writes and CPU reads from inside the kernel on recent hw,
>-	 * and it appears to only affect discrete GTT blocks (i.e. on LLC
>-	 * system agents we cannot reproduce this behaviour, until Cannonlake
>-	 * that was!).
>-	 */
>-
>-	wmb();
>-
>-	if (INTEL_INFO(dev_priv)->has_coherent_ggtt)
>-		return;
>-
>-	i915_gem_chipset_flush(dev_priv);
>-
>-	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
>-		struct intel_uncore *uncore = &dev_priv->uncore;
>-
>-		spin_lock_irq(&uncore->lock);
>-		intel_uncore_posting_read_fw(uncore,
>-					     RING_HEAD(RENDER_RING_BASE));
>-		spin_unlock_irq(&uncore->lock);
>-	}
>-}
>-
> static int
> shmem_pread(struct page *page, int offset, int len, char __user *user_data,
> 	    bool needs_clflush)
>@@ -430,11 +396,9 @@
> 		unsigned page_length = PAGE_SIZE - page_offset;
> 		page_length = remain < page_length ? remain : page_length;
> 		if (node.allocated) {
>-			wmb();
> 			ggtt->vm.insert_page(&ggtt->vm,
> 					     i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
> 					     node.start, I915_CACHE_NONE, 0);
>-			wmb();
> 		} else {
> 			page_base += offset & PAGE_MASK;
> 		}
>@@ -454,7 +418,6 @@
> out_unpin:
> 	mutex_lock(&i915->drm.struct_mutex);
> 	if (node.allocated) {
>-		wmb();
> 		ggtt->vm.clear_range(&ggtt->vm, node.start, node.size);
> 		remove_mappable_node(&node);
> 	} else {
>@@ -648,7 +611,8 @@
> 		unsigned int page_length = PAGE_SIZE - page_offset;
> 		page_length = remain < page_length ? remain : page_length;
> 		if (node.allocated) {
>-			wmb(); /* flush the write before we modify the GGTT */
>+			/* flush the write before we modify the GGTT */
>+			intel_gt_flush_ggtt_writes(ggtt->vm.gt);
> 			ggtt->vm.insert_page(&ggtt->vm,
> 					     i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
> 					     node.start, I915_CACHE_NONE, 0);
>@@ -677,8 +641,8 @@
> 	i915_gem_object_unlock_fence(obj, fence);
> out_unpin:
> 	mutex_lock(&i915->drm.struct_mutex);
>+	intel_gt_flush_ggtt_writes(ggtt->vm.gt);
> 	if (node.allocated) {
>-		wmb();
> 		ggtt->vm.clear_range(&ggtt->vm, node.start, node.size);
> 		remove_mappable_node(&node);
> 	} else {
>@@ -929,13 +893,13 @@
> 	}
> }
> 
>-static int wait_for_engines(struct drm_i915_private *i915)
>+static int wait_for_engines(struct intel_gt *gt)
> {
>-	if (wait_for(intel_engines_are_idle(i915), I915_IDLE_ENGINES_TIMEOUT)) {
>-		dev_err(i915->drm.dev,
>+	if (wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT)) {
>+		dev_err(gt->i915->drm.dev,
> 			"Failed to idle engines, declaring wedged!\n");
> 		GEM_TRACE_DUMP();
>-		i915_gem_set_wedged(i915);
>+		intel_gt_set_wedged(gt);
> 		return -EIO;
> 	}
> 
>@@ -946,8 +910,8 @@
> wait_for_timelines(struct drm_i915_private *i915,
> 		   unsigned int flags, long timeout)
> {
>-	struct i915_gt_timelines *gt = &i915->gt.timelines;
>-	struct i915_timeline *tl;
>+	struct intel_gt_timelines *gt = &i915->gt.timelines;
>+	struct intel_timeline *tl;
> 
> 	mutex_lock(&gt->mutex);
> 	list_for_each_entry(tl, &gt->active_list, link) {
>@@ -988,15 +952,15 @@
> int i915_gem_wait_for_idle(struct drm_i915_private *i915,
> 			   unsigned int flags, long timeout)
> {
>+	/* If the device is asleep, we have no requests outstanding */
>+	if (!READ_ONCE(i915->gt.awake))
>+		return 0;
>+
> 	GEM_TRACE("flags=%x (%s), timeout=%ld%s, awake?=%s\n",
> 		  flags, flags & I915_WAIT_LOCKED ? "locked" : "unlocked",
> 		  timeout, timeout == MAX_SCHEDULE_TIMEOUT ? " (forever)" : "",
> 		  yesno(i915->gt.awake));
> 
>-	/* If the device is asleep, we have no requests outstanding */
>-	if (!READ_ONCE(i915->gt.awake))
>-		return 0;
>-
> 	timeout = wait_for_timelines(i915, flags, timeout);
> 	if (timeout < 0)
> 		return timeout;
>@@ -1006,7 +970,7 @@
> 
> 		lockdep_assert_held(&i915->drm.struct_mutex);
> 
>-		err = wait_for_engines(i915);
>+		err = wait_for_engines(&i915->gt);
> 		if (err)
> 			return err;
> 
>@@ -1184,8 +1148,8 @@
> 	 * back to defaults, recovering from whatever wedged state we left it
> 	 * in and so worth trying to use the device once more.
> 	 */
>-	if (i915_terminally_wedged(i915))
>-		i915_gem_unset_wedged(i915);
>+	if (intel_gt_is_wedged(&i915->gt))
>+		intel_gt_unset_wedged(&i915->gt);
> 
> 	/*
> 	 * If we inherit context state from the BIOS or earlier occupants
>@@ -1195,82 +1159,72 @@
> 	 * it may impact the display and we are uncertain about the stability
> 	 * of the reset, so this could be applied to even earlier gen.
> 	 */
>-	intel_gt_sanitize(i915, false);
>+	intel_gt_sanitize(&i915->gt, false);
> 
> 	intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> }
> 
>-void i915_gem_init_swizzling(struct drm_i915_private *dev_priv)
>+static void init_unused_ring(struct intel_gt *gt, u32 base)
> {
>-	if (INTEL_GEN(dev_priv) < 5 ||
>-	    dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
>-		return;
>-
>-	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>-				 DISP_TILE_SURFACE_SWIZZLING);
>-
>-	if (IS_GEN(dev_priv, 5))
>-		return;
>+	struct intel_uncore *uncore = gt->uncore;
> 
>-	I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
>-	if (IS_GEN(dev_priv, 6))
>-		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
>-	else if (IS_GEN(dev_priv, 7))
>-		I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
>-	else if (IS_GEN(dev_priv, 8))
>-		I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
>-	else
>-		BUG();
>+	intel_uncore_write(uncore, RING_CTL(base), 0);
>+	intel_uncore_write(uncore, RING_HEAD(base), 0);
>+	intel_uncore_write(uncore, RING_TAIL(base), 0);
>+	intel_uncore_write(uncore, RING_START(base), 0);
> }
> 
>-static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)
>+static void init_unused_rings(struct intel_gt *gt)
> {
>-	I915_WRITE(RING_CTL(base), 0);
>-	I915_WRITE(RING_HEAD(base), 0);
>-	I915_WRITE(RING_TAIL(base), 0);
>-	I915_WRITE(RING_START(base), 0);
>-}
>+	struct drm_i915_private *i915 = gt->i915;
> 
>-static void init_unused_rings(struct drm_i915_private *dev_priv)
>-{
>-	if (IS_I830(dev_priv)) {
>-		init_unused_ring(dev_priv, PRB1_BASE);
>-		init_unused_ring(dev_priv, SRB0_BASE);
>-		init_unused_ring(dev_priv, SRB1_BASE);
>-		init_unused_ring(dev_priv, SRB2_BASE);
>-		init_unused_ring(dev_priv, SRB3_BASE);
>-	} else if (IS_GEN(dev_priv, 2)) {
>-		init_unused_ring(dev_priv, SRB0_BASE);
>-		init_unused_ring(dev_priv, SRB1_BASE);
>-	} else if (IS_GEN(dev_priv, 3)) {
>-		init_unused_ring(dev_priv, PRB1_BASE);
>-		init_unused_ring(dev_priv, PRB2_BASE);
>+	if (IS_I830(i915)) {
>+		init_unused_ring(gt, PRB1_BASE);
>+		init_unused_ring(gt, SRB0_BASE);
>+		init_unused_ring(gt, SRB1_BASE);
>+		init_unused_ring(gt, SRB2_BASE);
>+		init_unused_ring(gt, SRB3_BASE);
>+	} else if (IS_GEN(i915, 2)) {
>+		init_unused_ring(gt, SRB0_BASE);
>+		init_unused_ring(gt, SRB1_BASE);
>+	} else if (IS_GEN(i915, 3)) {
>+		init_unused_ring(gt, PRB1_BASE);
>+		init_unused_ring(gt, PRB2_BASE);
> 	}
> }
> 
>-int i915_gem_init_hw(struct drm_i915_private *dev_priv)
>+int i915_gem_init_hw(struct drm_i915_private *i915)
> {
>+	struct intel_uncore *uncore = &i915->uncore;
>+	struct intel_gt *gt = &i915->gt;
> 	int ret;
> 
>-	dev_priv->gt.last_init_time = ktime_get();
>+	BUG_ON(!i915->kernel_context);
>+	ret = intel_gt_terminally_wedged(gt);
>+	if (ret)
>+		return ret;
>+
>+	gt->last_init_time = ktime_get();
> 
> 	/* Double layer security blanket, see i915_gem_init() */
>-	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>+	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> 
>-	if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
>-		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
>+	if (HAS_EDRAM(i915) && INTEL_GEN(i915) < 9)
>+		intel_uncore_rmw(uncore, HSW_IDICR, 0, IDIHASHMSK(0xf));
> 
>-	if (IS_HASWELL(dev_priv))
>-		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
>-			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>+	if (IS_HASWELL(i915))
>+		intel_uncore_write(uncore,
>+				   MI_PREDICATE_RESULT_2,
>+				   IS_HSW_GT3(i915) ?
>+				   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
> 
> 	/* Apply the GT workarounds... */
>-	intel_gt_apply_workarounds(dev_priv);
>+	intel_gt_apply_workarounds(gt);
> 	/* ...and determine whether they are sticking. */
>-	intel_gt_verify_workarounds(dev_priv, "init");
>+	intel_gt_verify_workarounds(gt, "init");
> 
>-	i915_gem_init_swizzling(dev_priv);
>+	intel_gt_init_swizzling(gt);
> 
> 	/*
> 	 * At least 830 can leave some of the unused rings
>@@ -1278,41 +1232,33 @@
> 	 * will prevent c3 entry. Makes sure all unused rings
> 	 * are totally idle.
> 	 */
>-	init_unused_rings(dev_priv);
>-
>-	BUG_ON(!dev_priv->kernel_context);
>-	ret = i915_terminally_wedged(dev_priv);
>-	if (ret)
>-		goto out;
>+	init_unused_rings(gt);
> 
>-	ret = i915_ppgtt_init_hw(dev_priv);
>+	ret = i915_ppgtt_init_hw(gt);
> 	if (ret) {
> 		DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
> 		goto out;
> 	}
> 
>-	ret = intel_wopcm_init_hw(&dev_priv->wopcm);
>+	ret = intel_wopcm_init_hw(&i915->wopcm, gt);
> 	if (ret) {
> 		DRM_ERROR("Enabling WOPCM failed (%d)\n", ret);
> 		goto out;
> 	}
> 
> 	/* We can't enable contexts until all firmware is loaded */
>-	ret = intel_uc_init_hw(dev_priv);
>+	ret = intel_uc_init_hw(&i915->gt.uc);
> 	if (ret) {
> 		DRM_ERROR("Enabling uc failed (%d)\n", ret);
> 		goto out;
> 	}
> 
>-	intel_mocs_init_l3cc_table(dev_priv);
>+	intel_mocs_init_l3cc_table(gt);
> 
>-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>-
>-	intel_engines_set_scheduler_caps(dev_priv);
>-	return 0;
>+	intel_engines_set_scheduler_caps(i915);
> 
> out:
>-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>+	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> 	return ret;
> }
> 
>@@ -1349,10 +1295,24 @@
> 			goto err_active;
> 		}
> 
>-		err = 0;
>-		if (rq->engine->init_context)
>-			err = rq->engine->init_context(rq);
>+		err = intel_engine_emit_ctx_wa(rq);
>+		if (err)
>+			goto err_rq;
> 
>+		/*
>+		 * Failing to program the MOCS is non-fatal.The system will not
>+		 * run at peak performance. So warn the user and carry on.
>+		 */
>+		err = intel_mocs_emit(rq);
>+		if (err)
>+			dev_notice(i915->drm.dev,
>+				   "Failed to program MOCS registers; expect performance issues.\n");
>+
>+		err = intel_renderstate_emit(rq);
>+		if (err)
>+			goto err_rq;
>+
>+err_rq:
> 		i915_request_add(rq);
> 		if (err)
> 			goto err_active;
>@@ -1437,46 +1397,19 @@
> 	 * and ready to be torn-down. The quickest way we can accomplish
> 	 * this is by declaring ourselves wedged.
> 	 */
>-	i915_gem_set_wedged(i915);
>+	intel_gt_set_wedged(&i915->gt);
> 	goto out_ctx;
> }
> 
> static int
> i915_gem_init_scratch(struct drm_i915_private *i915, unsigned int size)
> {
>-	struct drm_i915_gem_object *obj;
>-	struct i915_vma *vma;
>-	int ret;
>-
>-	obj = i915_gem_object_create_stolen(i915, size);
>-	if (!obj)
>-		obj = i915_gem_object_create_internal(i915, size);
>-	if (IS_ERR(obj)) {
>-		DRM_ERROR("Failed to allocate scratch page\n");
>-		return PTR_ERR(obj);
>-	}
>-
>-	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
>-	if (IS_ERR(vma)) {
>-		ret = PTR_ERR(vma);
>-		goto err_unref;
>-	}
>-
>-	ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
>-	if (ret)
>-		goto err_unref;
>-
>-	i915->gt.scratch = vma;
>-	return 0;
>-
>-err_unref:
>-	i915_gem_object_put(obj);
>-	return ret;
>+	return intel_gt_init_scratch(&i915->gt, size);
> }
> 
> static void i915_gem_fini_scratch(struct drm_i915_private *i915)
> {
>-	i915_vma_unpin_and_release(&i915->gt.scratch, 0);
>+	intel_gt_fini_scratch(&i915->gt);
> }
> 
> static int intel_engines_verify_workarounds(struct drm_i915_private *i915)
>@@ -1507,19 +1440,17 @@
> 
> 	dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
> 
>-	i915_timelines_init(dev_priv);
>+	intel_timelines_init(dev_priv);
> 
> 	ret = i915_gem_init_userptr(dev_priv);
> 	if (ret)
> 		return ret;
> 
>-	ret = intel_uc_init_misc(dev_priv);
>-	if (ret)
>-		return ret;
>+	intel_uc_fetch_firmwares(&dev_priv->gt.uc);
> 
> 	ret = intel_wopcm_init(&dev_priv->wopcm);
> 	if (ret)
>-		goto err_uc_misc;
>+		goto err_uc_fw;
> 
> 	/* This is just a security blanket to placate dragons.
> 	 * On some systems, we very sporadically observe that the first TLBs
>@@ -1530,7 +1461,7 @@
> 	mutex_lock(&dev_priv->drm.struct_mutex);
> 	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> 
>-	ret = i915_gem_init_ggtt(dev_priv);
>+	ret = i915_init_ggtt(dev_priv);
> 	if (ret) {
> 		GEM_BUG_ON(ret == -EIO);
> 		goto err_unlock;
>@@ -1563,7 +1494,7 @@
> 
> 	intel_init_gt_powersave(dev_priv);
> 
>-	ret = intel_uc_init(dev_priv);
>+	ret = intel_uc_init(&dev_priv->gt.uc);
> 	if (ret)
> 		goto err_pm;
> 
>@@ -1572,7 +1503,7 @@
> 		goto err_uc_init;
> 
> 	/* Only when the HW is re-initialised, can we replay the requests */
>-	ret = intel_gt_resume(dev_priv);
>+	ret = intel_gt_resume(&dev_priv->gt);
> 	if (ret)
> 		goto err_init_hw;
> 
>@@ -1595,12 +1526,12 @@
> 	if (ret)
> 		goto err_gt;
> 
>-	if (i915_inject_load_failure()) {
>+	if (i915_inject_probe_failure()) {
> 		ret = -ENODEV;
> 		goto err_gt;
> 	}
> 
>-	if (i915_inject_load_failure()) {
>+	if (i915_inject_probe_failure()) {
> 		ret = -EIO;
> 		goto err_gt;
> 	}
>@@ -1619,7 +1550,7 @@
> err_gt:
> 	mutex_unlock(&dev_priv->drm.struct_mutex);
> 
>-	i915_gem_set_wedged(dev_priv);
>+	intel_gt_set_wedged(&dev_priv->gt);
> 	i915_gem_suspend(dev_priv);
> 	i915_gem_suspend_late(dev_priv);
> 
>@@ -1627,9 +1558,9 @@
> 
> 	mutex_lock(&dev_priv->drm.struct_mutex);
> err_init_hw:
>-	intel_uc_fini_hw(dev_priv);
>+	intel_uc_fini_hw(&dev_priv->gt.uc);
> err_uc_init:
>-	intel_uc_fini(dev_priv);
>+	intel_uc_fini(&dev_priv->gt.uc);
> err_pm:
> 	if (ret != -EIO) {
> 		intel_cleanup_gt_powersave(dev_priv);
>@@ -1645,12 +1576,12 @@
> 	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> 	mutex_unlock(&dev_priv->drm.struct_mutex);
> 
>-err_uc_misc:
>-	intel_uc_fini_misc(dev_priv);
>+err_uc_fw:
>+	intel_uc_cleanup_firmwares(&dev_priv->gt.uc);
> 
> 	if (ret != -EIO) {
> 		i915_gem_cleanup_userptr(dev_priv);
>-		i915_timelines_fini(dev_priv);
>+		intel_timelines_fini(dev_priv);
> 	}
> 
> 	if (ret == -EIO) {
>@@ -1661,10 +1592,10 @@
> 		 * wedged. But we only want to do this where the GPU is angry,
> 		 * for all other failure, such as an allocation failure, bail.
> 		 */
>-		if (!i915_reset_failed(dev_priv)) {
>-			i915_load_error(dev_priv,
>-					"Failed to initialize GPU, declaring it wedged!\n");
>-			i915_gem_set_wedged(dev_priv);
>+		if (!intel_gt_is_wedged(&dev_priv->gt)) {
>+			i915_probe_error(dev_priv,
>+					 "Failed to initialize GPU, declaring it wedged!\n");
>+			intel_gt_set_wedged(&dev_priv->gt);
> 		}
> 
> 		/* Minimal basic recovery for KMS */
>@@ -1680,7 +1611,7 @@
> 	return ret;
> }
> 
>-void i915_gem_fini_hw(struct drm_i915_private *dev_priv)
>+void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
> {
> 	GEM_BUG_ON(dev_priv->gt.awake);
> 
>@@ -1693,14 +1624,14 @@
> 	i915_gem_drain_workqueue(dev_priv);
> 
> 	mutex_lock(&dev_priv->drm.struct_mutex);
>-	intel_uc_fini_hw(dev_priv);
>-	intel_uc_fini(dev_priv);
>+	intel_uc_fini_hw(&dev_priv->gt.uc);
>+	intel_uc_fini(&dev_priv->gt.uc);
> 	mutex_unlock(&dev_priv->drm.struct_mutex);
> 
> 	i915_gem_drain_freed_objects(dev_priv);
> }
> 
>-void i915_gem_fini(struct drm_i915_private *dev_priv)
>+void i915_gem_driver_release(struct drm_i915_private *dev_priv)
> {
> 	mutex_lock(&dev_priv->drm.struct_mutex);
> 	intel_engines_cleanup(dev_priv);
>@@ -1712,9 +1643,9 @@
> 
> 	intel_cleanup_gt_powersave(dev_priv);
> 
>-	intel_uc_fini_misc(dev_priv);
>+	intel_uc_cleanup_firmwares(&dev_priv->gt.uc);
> 	i915_gem_cleanup_userptr(dev_priv);
>-	i915_timelines_fini(dev_priv);
>+	intel_timelines_fini(dev_priv);
> 
> 	i915_gem_drain_freed_objects(dev_priv);
> 
>@@ -1743,20 +1674,9 @@
> {
> 	int err;
> 
>-	intel_gt_pm_init(dev_priv);
>-
>-	INIT_LIST_HEAD(&dev_priv->gt.active_rings);
>-	INIT_LIST_HEAD(&dev_priv->gt.closed_vma);
>-	spin_lock_init(&dev_priv->gt.closed_lock);
>-
> 	i915_gem_init__mm(dev_priv);
> 	i915_gem_init__pm(dev_priv);
> 
>-	init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
>-	init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
>-	mutex_init(&dev_priv->gpu_error.wedge_mutex);
>-	init_srcu_struct(&dev_priv->gpu_error.reset_backoff_srcu);
>-
> 	atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
> 
> 	spin_lock_init(&dev_priv->fb_tracking.lock);
>@@ -1775,7 +1695,7 @@
> 	GEM_BUG_ON(atomic_read(&dev_priv->mm.free_count));
> 	WARN_ON(dev_priv->mm.shrink_count);
> 
>-	cleanup_srcu_struct(&dev_priv->gpu_error.reset_backoff_srcu);
>+	intel_gt_cleanup_early(&dev_priv->gt);
> 
> 	i915_gemfs_fini(dev_priv);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_fence_reg.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_fence_reg.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_fence_reg.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_fence_reg.c	2019-08-31 15:01:12.032736184 -0500
>@@ -834,3 +834,35 @@
> 
> 	i915_gem_restore_fences(i915);
> }
>+
>+void intel_gt_init_swizzling(struct intel_gt *gt)
>+{
>+	struct drm_i915_private *i915 = gt->i915;
>+	struct intel_uncore *uncore = gt->uncore;
>+
>+	if (INTEL_GEN(i915) < 5 ||
>+	    i915->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
>+		return;
>+
>+	intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
>+
>+	if (IS_GEN(i915, 5))
>+		return;
>+
>+	intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
>+
>+	if (IS_GEN(i915, 6))
>+		intel_uncore_write(uncore,
>+				   ARB_MODE,
>+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
>+	else if (IS_GEN(i915, 7))
>+		intel_uncore_write(uncore,
>+				   ARB_MODE,
>+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
>+	else if (IS_GEN(i915, 8))
>+		intel_uncore_write(uncore,
>+				   GAMTARBMODE,
>+				   _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
>+	else
>+		MISSING_CASE(INTEL_GEN(i915));
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_fence_reg.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_fence_reg.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_fence_reg.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_fence_reg.h	2019-08-31 15:01:12.032736184 -0500
>@@ -32,6 +32,7 @@
> struct drm_i915_private;
> struct i915_ggtt;
> struct i915_vma;
>+struct intel_gt;
> struct sg_table;
> 
> #define I965_FENCE_PAGE 4096UL
>@@ -66,4 +67,6 @@
> 
> void i915_ggtt_init_fences(struct i915_ggtt *ggtt);
> 
>+void intel_gt_init_swizzling(struct intel_gt *gt);
>+
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_gtt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_gtt.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_gtt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_gtt.c	2019-08-31 15:01:12.033736184 -0500
>@@ -36,6 +36,7 @@
> #include <drm/i915_drm.h>
> 
> #include "display/intel_frontbuffer.h"
>+#include "gt/intel_gt.h"
> 
> #include "i915_drv.h"
> #include "i915_scatterlist.h"
>@@ -45,6 +46,12 @@
> 
> #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
> 
>+#if IS_ENABLED(CONFIG_DRM_I915_TRACE_GTT)
>+#define DBG(...) trace_printk(__VA_ARGS__)
>+#else
>+#define DBG(...)
>+#endif
>+
> /**
>  * DOC: Global GTT views
>  *
>@@ -106,12 +113,14 @@
>  *
>  */
> 
>+#define as_pd(x) container_of((x), typeof(struct i915_page_directory), pt)
>+
> static int
> i915_get_ggtt_vma_pages(struct i915_vma *vma);
> 
>-static void gen6_ggtt_invalidate(struct drm_i915_private *i915)
>+static void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
> {
>-	struct intel_uncore *uncore = &i915->uncore;
>+	struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
> 
> 	/*
> 	 * Note that as an uncached mmio write, this will flush the
>@@ -120,24 +129,19 @@
> 	intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
> }
> 
>-static void guc_ggtt_invalidate(struct drm_i915_private *i915)
>+static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
> {
>-	struct intel_uncore *uncore = &i915->uncore;
>+	struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
> 
>-	gen6_ggtt_invalidate(i915);
>+	gen6_ggtt_invalidate(ggtt);
> 	intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
> }
> 
>-static void gmch_ggtt_invalidate(struct drm_i915_private *i915)
>+static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
> {
> 	intel_gtt_chipset_flush();
> }
> 
>-static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
>-{
>-	i915->ggtt.invalidate(i915);
>-}
>-
> static int ppgtt_bind_vma(struct i915_vma *vma,
> 			  enum i915_cache_level cache_level,
> 			  u32 unused)
>@@ -215,10 +219,10 @@
> 	return pte;
> }
> 
>-static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
>-				  const enum i915_cache_level level)
>+static u64 gen8_pde_encode(const dma_addr_t addr,
>+			   const enum i915_cache_level level)
> {
>-	gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
>+	u64 pde = _PAGE_PRESENT | _PAGE_RW;
> 	pde |= addr;
> 	if (level != I915_CACHE_NONE)
> 		pde |= PPAT_CACHED_PDE;
>@@ -227,9 +231,6 @@
> 	return pde;
> }
> 
>-#define gen8_pdpe_encode gen8_pde_encode
>-#define gen8_pml4e_encode gen8_pde_encode
>-
> static u64 snb_pte_encode(dma_addr_t addr,
> 			  enum i915_cache_level level,
> 			  u32 flags)
>@@ -482,9 +483,69 @@
> 	spin_unlock(&vm->free_pages.lock);
> }
> 
>+static void i915_address_space_fini(struct i915_address_space *vm)
>+{
>+	spin_lock(&vm->free_pages.lock);
>+	if (pagevec_count(&vm->free_pages.pvec))
>+		vm_free_pages_release(vm, true);
>+	GEM_BUG_ON(pagevec_count(&vm->free_pages.pvec));
>+	spin_unlock(&vm->free_pages.lock);
>+
>+	drm_mm_takedown(&vm->mm);
>+
>+	mutex_destroy(&vm->mutex);
>+}
>+
>+static void ppgtt_destroy_vma(struct i915_address_space *vm)
>+{
>+	struct list_head *phases[] = {
>+		&vm->bound_list,
>+		&vm->unbound_list,
>+		NULL,
>+	}, **phase;
>+
>+	mutex_lock(&vm->i915->drm.struct_mutex);
>+	for (phase = phases; *phase; phase++) {
>+		struct i915_vma *vma, *vn;
>+
>+		list_for_each_entry_safe(vma, vn, *phase, vm_link)
>+			i915_vma_destroy(vma);
>+	}
>+	mutex_unlock(&vm->i915->drm.struct_mutex);
>+}
>+
>+static void __i915_vm_release(struct work_struct *work)
>+{
>+	struct i915_address_space *vm =
>+		container_of(work, struct i915_address_space, rcu.work);
>+
>+	ppgtt_destroy_vma(vm);
>+
>+	GEM_BUG_ON(!list_empty(&vm->bound_list));
>+	GEM_BUG_ON(!list_empty(&vm->unbound_list));
>+
>+	vm->cleanup(vm);
>+	i915_address_space_fini(vm);
>+
>+	kfree(vm);
>+}
>+
>+void i915_vm_release(struct kref *kref)
>+{
>+	struct i915_address_space *vm =
>+		container_of(kref, struct i915_address_space, ref);
>+
>+	GEM_BUG_ON(i915_is_ggtt(vm));
>+	trace_i915_ppgtt_release(vm);
>+
>+	vm->closed = true;
>+	queue_rcu_work(vm->i915->wq, &vm->rcu);
>+}
>+
> static void i915_address_space_init(struct i915_address_space *vm, int subclass)
> {
> 	kref_init(&vm->ref);
>+	INIT_RCU_WORK(&vm->rcu, __i915_vm_release);
> 
> 	/*
> 	 * The vm->mutex must be reclaim safe (for use in the shrinker).
>@@ -505,19 +566,6 @@
> 	INIT_LIST_HEAD(&vm->bound_list);
> }
> 
>-static void i915_address_space_fini(struct i915_address_space *vm)
>-{
>-	spin_lock(&vm->free_pages.lock);
>-	if (pagevec_count(&vm->free_pages.pvec))
>-		vm_free_pages_release(vm, true);
>-	GEM_BUG_ON(pagevec_count(&vm->free_pages.pvec));
>-	spin_unlock(&vm->free_pages.lock);
>-
>-	drm_mm_takedown(&vm->mm);
>-
>-	mutex_destroy(&vm->mutex);
>-}
>-
> static int __setup_page_dma(struct i915_address_space *vm,
> 			    struct i915_page_dma *p,
> 			    gfp_t gfp)
>@@ -554,28 +602,17 @@
> 
> #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
> 
>-#define setup_px(vm, px) setup_page_dma((vm), px_base(px))
>-#define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px))
>-#define fill_px(vm, px, v) fill_page_dma((vm), px_base(px), (v))
>-#define fill32_px(vm, px, v) fill_page_dma_32((vm), px_base(px), (v))
>-
>-static void fill_page_dma(struct i915_address_space *vm,
>-			  struct i915_page_dma *p,
>-			  const u64 val)
>+static void
>+fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count)
> {
>-	u64 * const vaddr = kmap_atomic(p->page);
>-
>-	memset64(vaddr, val, PAGE_SIZE / sizeof(val));
>-
>-	kunmap_atomic(vaddr);
>+	kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
> }
> 
>-static void fill_page_dma_32(struct i915_address_space *vm,
>-			     struct i915_page_dma *p,
>-			     const u32 v)
>-{
>-	fill_page_dma(vm, p, (u64)v << 32 | v);
>-}
>+#define fill_px(px, v) fill_page_dma(px_base(px), (v), PAGE_SIZE / sizeof(u64))
>+#define fill32_px(px, v) do {						\
>+	u64 v__ = lower_32_bits(v);					\
>+	fill_px((px), v__ << 32 | v__);					\
>+} while (0)
> 
> static int
> setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
>@@ -602,7 +639,7 @@
> 	gfp |= __GFP_ZERO | __GFP_RETRY_MAYFAIL;
> 
> 	do {
>-		int order = get_order(size);
>+		unsigned int order = get_order(size);
> 		struct page *page;
> 		dma_addr_t addr;
> 
>@@ -621,8 +658,8 @@
> 		if (unlikely(!IS_ALIGNED(addr, size)))
> 			goto unmap_page;
> 
>-		vm->scratch_page.page = page;
>-		vm->scratch_page.daddr = addr;
>+		vm->scratch[0].base.page = page;
>+		vm->scratch[0].base.daddr = addr;
> 		vm->scratch_order = order;
> 		return 0;
> 
>@@ -641,14 +678,30 @@
> 
> static void cleanup_scratch_page(struct i915_address_space *vm)
> {
>-	struct i915_page_dma *p = &vm->scratch_page;
>-	int order = vm->scratch_order;
>+	struct i915_page_dma *p = px_base(&vm->scratch[0]);
>+	unsigned int order = vm->scratch_order;
> 
> 	dma_unmap_page(vm->dma, p->daddr, BIT(order) << PAGE_SHIFT,
> 		       PCI_DMA_BIDIRECTIONAL);
> 	__free_pages(p->page, order);
> }
> 
>+static void free_scratch(struct i915_address_space *vm)
>+{
>+	int i;
>+
>+	if (!px_dma(&vm->scratch[0])) /* set to 0 on clones */
>+		return;
>+
>+	for (i = 1; i <= vm->top; i++) {
>+		if (!px_dma(&vm->scratch[i]))
>+			break;
>+		cleanup_page_dma(vm, px_base(&vm->scratch[i]));
>+	}
>+
>+	cleanup_scratch_page(vm);
>+}
>+
> static struct i915_page_table *alloc_pt(struct i915_address_space *vm)
> {
> 	struct i915_page_table *pt;
>@@ -657,50 +710,24 @@
> 	if (unlikely(!pt))
> 		return ERR_PTR(-ENOMEM);
> 
>-	if (unlikely(setup_px(vm, pt))) {
>+	if (unlikely(setup_page_dma(vm, &pt->base))) {
> 		kfree(pt);
> 		return ERR_PTR(-ENOMEM);
> 	}
> 
> 	atomic_set(&pt->used, 0);
>-
> 	return pt;
> }
> 
>-static void free_pt(struct i915_address_space *vm, struct i915_page_table *pt)
>-{
>-	cleanup_px(vm, pt);
>-	kfree(pt);
>-}
>-
>-static void gen8_initialize_pt(struct i915_address_space *vm,
>-			       struct i915_page_table *pt)
>-{
>-	fill_px(vm, pt, vm->scratch_pte);
>-}
>-
>-static void gen6_initialize_pt(struct i915_address_space *vm,
>-			       struct i915_page_table *pt)
>-{
>-	fill32_px(vm, pt, vm->scratch_pte);
>-}
>-
>-static struct i915_page_directory *__alloc_pd(void)
>+static struct i915_page_directory *__alloc_pd(size_t sz)
> {
> 	struct i915_page_directory *pd;
> 
>-	pd = kmalloc(sizeof(*pd), I915_GFP_ALLOW_FAIL);
>-
>+	pd = kzalloc(sz, I915_GFP_ALLOW_FAIL);
> 	if (unlikely(!pd))
> 		return NULL;
> 
>-	memset(&pd->base, 0, sizeof(pd->base));
>-	atomic_set(&pd->used, 0);
> 	spin_lock_init(&pd->lock);
>-
>-	/* for safety */
>-	pd->entry[0] = NULL;
>-
> 	return pd;
> }
> 
>@@ -708,11 +735,11 @@
> {
> 	struct i915_page_directory *pd;
> 
>-	pd = __alloc_pd();
>+	pd = __alloc_pd(sizeof(*pd));
> 	if (unlikely(!pd))
> 		return ERR_PTR(-ENOMEM);
> 
>-	if (unlikely(setup_px(vm, pd))) {
>+	if (unlikely(setup_page_dma(vm, px_base(pd)))) {
> 		kfree(pd);
> 		return ERR_PTR(-ENOMEM);
> 	}
>@@ -720,36 +747,72 @@
> 	return pd;
> }
> 
>-static inline bool pd_has_phys_page(const struct i915_page_directory * const pd)
>+static void free_pd(struct i915_address_space *vm, struct i915_page_dma *pd)
> {
>-	return pd->base.page;
>+	cleanup_page_dma(vm, pd);
>+	kfree(pd);
> }
> 
>-static void free_pd(struct i915_address_space *vm,
>-		    struct i915_page_directory *pd)
>+#define free_px(vm, px) free_pd(vm, px_base(px))
>+
>+static inline void
>+write_dma_entry(struct i915_page_dma * const pdma,
>+		const unsigned short idx,
>+		const u64 encoded_entry)
> {
>-	if (likely(pd_has_phys_page(pd)))
>-		cleanup_px(vm, pd);
>+	u64 * const vaddr = kmap_atomic(pdma->page);
> 
>-	kfree(pd);
>+	vaddr[idx] = encoded_entry;
>+	kunmap_atomic(vaddr);
> }
> 
>-static void init_pd_with_page(struct i915_address_space *vm,
>-			      struct i915_page_directory * const pd,
>-			      struct i915_page_table *pt)
>+static inline void
>+__set_pd_entry(struct i915_page_directory * const pd,
>+	       const unsigned short idx,
>+	       struct i915_page_dma * const to,
>+	       u64 (*encode)(const dma_addr_t, const enum i915_cache_level))
> {
>-	fill_px(vm, pd, gen8_pde_encode(px_dma(pt), I915_CACHE_LLC));
>-	memset_p(pd->entry, pt, 512);
>+	GEM_BUG_ON(atomic_read(px_used(pd)) > ARRAY_SIZE(pd->entry));
>+
>+	atomic_inc(px_used(pd));
>+	pd->entry[idx] = to;
>+	write_dma_entry(px_base(pd), idx, encode(to->daddr, I915_CACHE_LLC));
> }
> 
>-static void init_pd(struct i915_address_space *vm,
>-		    struct i915_page_directory * const pd,
>-		    struct i915_page_directory * const to)
>+#define set_pd_entry(pd, idx, to) \
>+	__set_pd_entry((pd), (idx), px_base(to), gen8_pde_encode)
>+
>+static inline void
>+clear_pd_entry(struct i915_page_directory * const pd,
>+	       const unsigned short idx,
>+	       const struct i915_page_scratch * const scratch)
> {
>-	GEM_DEBUG_BUG_ON(!pd_has_phys_page(pd));
>+	GEM_BUG_ON(atomic_read(px_used(pd)) == 0);
> 
>-	fill_px(vm, pd, gen8_pdpe_encode(px_dma(to), I915_CACHE_LLC));
>-	memset_p(pd->entry, to, 512);
>+	write_dma_entry(px_base(pd), idx, scratch->encode);
>+	pd->entry[idx] = NULL;
>+	atomic_dec(px_used(pd));
>+}
>+
>+static bool
>+release_pd_entry(struct i915_page_directory * const pd,
>+		 const unsigned short idx,
>+		 struct i915_page_table * const pt,
>+		 const struct i915_page_scratch * const scratch)
>+{
>+	bool free = false;
>+
>+	if (atomic_add_unless(&pt->used, -1, 1))
>+		return false;
>+
>+	spin_lock(&pd->lock);
>+	if (atomic_dec_and_test(&pt->used)) {
>+		clear_pd_entry(pd, idx, scratch);
>+		free = true;
>+	}
>+	spin_unlock(&pd->lock);
>+
>+	return free;
> }
> 
> /*
>@@ -763,165 +826,305 @@
> 	ppgtt->pd_dirty_engines = ALL_ENGINES;
> }
> 
>-/* Removes entries from a single page table, releasing it if it's empty.
>- * Caller can use the return value to update higher-level entries.
>- */
>-static bool gen8_ppgtt_clear_pt(const struct i915_address_space *vm,
>-				struct i915_page_table *pt,
>-				u64 start, u64 length)
>+static int gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
> {
>-	unsigned int num_entries = gen8_pte_count(start, length);
>-	gen8_pte_t *vaddr;
>+	struct i915_address_space *vm = &ppgtt->vm;
>+	struct drm_i915_private *dev_priv = vm->i915;
>+	enum vgt_g2v_type msg;
>+	int i;
> 
>-	vaddr = kmap_atomic_px(pt);
>-	memset64(vaddr + gen8_pte_index(start), vm->scratch_pte, num_entries);
>-	kunmap_atomic(vaddr);
>+	if (create)
>+		atomic_inc(px_used(ppgtt->pd)); /* never remove */
>+	else
>+		atomic_dec(px_used(ppgtt->pd));
>+
>+	if (i915_vm_is_4lvl(vm)) {
>+		const u64 daddr = px_dma(ppgtt->pd);
>+
>+		I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
>+		I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
>+
>+		msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
>+				VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
>+	} else {
>+		for (i = 0; i < GEN8_3LVL_PDPES; i++) {
>+			const u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
>+
>+			I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
>+			I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
>+		}
>+
>+		msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
>+				VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
>+	}
> 
>-	GEM_BUG_ON(num_entries > atomic_read(&pt->used));
>-	return !atomic_sub_return(num_entries, &pt->used);
>+	I915_WRITE(vgtif_reg(g2v_notify), msg);
>+
>+	return 0;
> }
> 
>-static void gen8_ppgtt_set_pde(struct i915_address_space *vm,
>-			       struct i915_page_directory *pd,
>-			       struct i915_page_table *pt,
>-			       unsigned int pde)
>+/* Index shifts into the pagetable are offset by GEN8_PTE_SHIFT [12] */
>+#define GEN8_PAGE_SIZE (SZ_4K) /* page and page-directory sizes are the same */
>+#define GEN8_PTE_SHIFT (ilog2(GEN8_PAGE_SIZE))
>+#define GEN8_PDES (GEN8_PAGE_SIZE / sizeof(u64))
>+#define gen8_pd_shift(lvl) ((lvl) * ilog2(GEN8_PDES))
>+#define gen8_pd_index(i, lvl) i915_pde_index((i), gen8_pd_shift(lvl))
>+#define __gen8_pte_shift(lvl) (GEN8_PTE_SHIFT + gen8_pd_shift(lvl))
>+#define __gen8_pte_index(a, lvl) i915_pde_index((a), __gen8_pte_shift(lvl))
>+
>+static inline unsigned int
>+gen8_pd_range(u64 start, u64 end, int lvl, unsigned int *idx)
> {
>-	gen8_pde_t *vaddr;
>+	const int shift = gen8_pd_shift(lvl);
>+	const u64 mask = ~0ull << gen8_pd_shift(lvl + 1);
> 
>-	vaddr = kmap_atomic_px(pd);
>-	vaddr[pde] = gen8_pde_encode(px_dma(pt), I915_CACHE_LLC);
>-	kunmap_atomic(vaddr);
>+	GEM_BUG_ON(start >= end);
>+	end += ~mask >> gen8_pd_shift(1);
>+
>+	*idx = i915_pde_index(start, shift);
>+	if ((start ^ end) & mask)
>+		return GEN8_PDES - *idx;
>+	else
>+		return i915_pde_index(end, shift) - *idx;
> }
> 
>-static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
>-				struct i915_page_directory *pd,
>-				u64 start, u64 length)
>+static inline bool gen8_pd_contains(u64 start, u64 end, int lvl)
> {
>-	struct i915_page_table *pt;
>-	u32 pde;
>+	const u64 mask = ~0ull << gen8_pd_shift(lvl + 1);
> 
>-	gen8_for_each_pde(pt, pd, start, length, pde) {
>-		bool free = false;
>+	GEM_BUG_ON(start >= end);
>+	return (start ^ end) & mask && (start & ~mask) == 0;
>+}
> 
>-		GEM_BUG_ON(pt == vm->scratch_pt);
>+static inline unsigned int gen8_pt_count(u64 start, u64 end)
>+{
>+	GEM_BUG_ON(start >= end);
>+	if ((start ^ end) >> gen8_pd_shift(1))
>+		return GEN8_PDES - (start & (GEN8_PDES - 1));
>+	else
>+		return end - start;
>+}
> 
>-		if (!gen8_ppgtt_clear_pt(vm, pt, start, length))
>-			continue;
>+static inline unsigned int gen8_pd_top_count(const struct i915_address_space *vm)
>+{
>+	unsigned int shift = __gen8_pte_shift(vm->top);
>+	return (vm->total + (1ull << shift) - 1) >> shift;
>+}
> 
>-		spin_lock(&pd->lock);
>-		if (!atomic_read(&pt->used)) {
>-			gen8_ppgtt_set_pde(vm, pd, vm->scratch_pt, pde);
>-			pd->entry[pde] = vm->scratch_pt;
>+static void __gen8_ppgtt_cleanup(struct i915_address_space *vm,
>+				 struct i915_page_directory *pd,
>+				 int count, int lvl)
>+{
>+	if (lvl) {
>+		void **pde = pd->entry;
> 
>-			GEM_BUG_ON(!atomic_read(&pd->used));
>-			atomic_dec(&pd->used);
>-			free = true;
>-		}
>-		spin_unlock(&pd->lock);
>-		if (free)
>-			free_pt(vm, pt);
>+		do {
>+			if (!*pde)
>+				continue;
>+
>+			__gen8_ppgtt_cleanup(vm, *pde, GEN8_PDES, lvl - 1);
>+		} while (pde++, --count);
> 	}
> 
>-	return !atomic_read(&pd->used);
>+	free_px(vm, pd);
> }
> 
>-static void gen8_ppgtt_set_pdpe(struct i915_page_directory *pdp,
>-				struct i915_page_directory *pd,
>-				unsigned int pdpe)
>+static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
> {
>-	gen8_ppgtt_pdpe_t *vaddr;
>+	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> 
>-	if (!pd_has_phys_page(pdp))
>-		return;
>+	if (intel_vgpu_active(vm->i915))
>+		gen8_ppgtt_notify_vgt(ppgtt, false);
> 
>-	vaddr = kmap_atomic_px(pdp);
>-	vaddr[pdpe] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
>-	kunmap_atomic(vaddr);
>+	__gen8_ppgtt_cleanup(vm, ppgtt->pd, gen8_pd_top_count(vm), vm->top);
>+	free_scratch(vm);
> }
> 
>-/* Removes entries from a single page dir pointer, releasing it if it's empty.
>- * Caller can use the return value to update higher-level entries
>- */
>-static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
>-				 struct i915_page_directory * const pdp,
>-				 u64 start, u64 length)
>+static u64 __gen8_ppgtt_clear(struct i915_address_space * const vm,
>+			      struct i915_page_directory * const pd,
>+			      u64 start, const u64 end, int lvl)
> {
>-	struct i915_page_directory *pd;
>-	unsigned int pdpe;
>+	const struct i915_page_scratch * const scratch = &vm->scratch[lvl];
>+	unsigned int idx, len;
> 
>-	gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
>-		bool free = false;
>+	len = gen8_pd_range(start, end, lvl--, &idx);
>+	DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d}\n",
>+	    __func__, vm, lvl + 1, start, end,
>+	    idx, len, atomic_read(px_used(pd)));
>+	GEM_BUG_ON(!len || len >= atomic_read(px_used(pd)));
> 
>-		GEM_BUG_ON(pd == vm->scratch_pd);
>+	do {
>+		struct i915_page_table *pt = pd->entry[idx];
> 
>-		if (!gen8_ppgtt_clear_pd(vm, pd, start, length))
>+		if (atomic_fetch_inc(&pt->used) >> gen8_pd_shift(1) &&
>+		    gen8_pd_contains(start, end, lvl)) {
>+			DBG("%s(%p):{ lvl:%d, idx:%d, start:%llx, end:%llx } removing pd\n",
>+			    __func__, vm, lvl + 1, idx, start, end);
>+			clear_pd_entry(pd, idx, scratch);
>+			__gen8_ppgtt_cleanup(vm, as_pd(pt), I915_PDES, lvl);
>+			start += (u64)I915_PDES << gen8_pd_shift(lvl);
> 			continue;
>+		}
> 
>-		spin_lock(&pdp->lock);
>-		if (!atomic_read(&pd->used)) {
>-			gen8_ppgtt_set_pdpe(pdp, vm->scratch_pd, pdpe);
>-			pdp->entry[pdpe] = vm->scratch_pd;
>+		if (lvl) {
>+			start = __gen8_ppgtt_clear(vm, as_pd(pt),
>+						   start, end, lvl);
>+		} else {
>+			unsigned int count;
>+			u64 *vaddr;
>+
>+			count = gen8_pt_count(start, end);
>+			DBG("%s(%p):{ lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d} removing pte\n",
>+			    __func__, vm, lvl, start, end,
>+			    gen8_pd_index(start, 0), count,
>+			    atomic_read(&pt->used));
>+			GEM_BUG_ON(!count || count >= atomic_read(&pt->used));
>+
>+			vaddr = kmap_atomic_px(pt);
>+			memset64(vaddr + gen8_pd_index(start, 0),
>+				 vm->scratch[0].encode,
>+				 count);
>+			kunmap_atomic(vaddr);
> 
>-			GEM_BUG_ON(!atomic_read(&pdp->used));
>-			atomic_dec(&pdp->used);
>-			free = true;
>+			atomic_sub(count, &pt->used);
>+			start += count;
> 		}
>-		spin_unlock(&pdp->lock);
>-		if (free)
>-			free_pd(vm, pd);
>-	}
> 
>-	return !atomic_read(&pdp->used);
>+		if (release_pd_entry(pd, idx, pt, scratch))
>+			free_px(vm, pt);
>+	} while (idx++, --len);
>+
>+	return start;
> }
> 
>-static void gen8_ppgtt_clear_3lvl(struct i915_address_space *vm,
>-				  u64 start, u64 length)
>+static void gen8_ppgtt_clear(struct i915_address_space *vm,
>+			     u64 start, u64 length)
> {
>-	gen8_ppgtt_clear_pdp(vm, i915_vm_to_ppgtt(vm)->pd, start, length);
>+	GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT)));
>+	GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT)));
>+
>+	start >>= GEN8_PTE_SHIFT;
>+	length >>= GEN8_PTE_SHIFT;
>+	GEM_BUG_ON(length == 0);
>+
>+	__gen8_ppgtt_clear(vm, i915_vm_to_ppgtt(vm)->pd,
>+			   start, start + length, vm->top);
> }
> 
>-static void gen8_ppgtt_set_pml4e(struct i915_page_directory *pml4,
>-				 struct i915_page_directory *pdp,
>-				 unsigned int pml4e)
>+static int __gen8_ppgtt_alloc(struct i915_address_space * const vm,
>+			      struct i915_page_directory * const pd,
>+			      u64 * const start, u64 end, int lvl)
> {
>-	gen8_ppgtt_pml4e_t *vaddr;
>+	const struct i915_page_scratch * const scratch = &vm->scratch[lvl];
>+	struct i915_page_table *alloc = NULL;
>+	unsigned int idx, len;
>+	int ret = 0;
> 
>-	vaddr = kmap_atomic_px(pml4);
>-	vaddr[pml4e] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
>-	kunmap_atomic(vaddr);
>+	len = gen8_pd_range(*start, end, lvl--, &idx);
>+	DBG("%s(%p):{lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d}\n",
>+	    __func__, vm, lvl + 1, *start, end,
>+	    idx, len, atomic_read(px_used(pd)));
>+	GEM_BUG_ON(!len || (idx + len - 1) >> gen8_pd_shift(1));
>+
>+	spin_lock(&pd->lock);
>+	GEM_BUG_ON(!atomic_read(px_used(pd))); /* Must be pinned! */
>+	do {
>+		struct i915_page_table *pt = pd->entry[idx];
>+
>+		if (!pt) {
>+			spin_unlock(&pd->lock);
>+
>+			DBG("%s(%p):{ lvl:%d, idx:%d } allocating new tree\n",
>+			    __func__, vm, lvl + 1, idx);
>+
>+			pt = fetch_and_zero(&alloc);
>+			if (lvl) {
>+				if (!pt) {
>+					pt = &alloc_pd(vm)->pt;
>+					if (IS_ERR(pt)) {
>+						ret = PTR_ERR(pt);
>+						goto out;
>+					}
>+				}
>+
>+				fill_px(pt, vm->scratch[lvl].encode);
>+			} else {
>+				if (!pt) {
>+					pt = alloc_pt(vm);
>+					if (IS_ERR(pt)) {
>+						ret = PTR_ERR(pt);
>+						goto out;
>+					}
>+				}
>+
>+				if (intel_vgpu_active(vm->i915) ||
>+				    gen8_pt_count(*start, end) < I915_PDES)
>+					fill_px(pt, vm->scratch[lvl].encode);
>+			}
>+
>+			spin_lock(&pd->lock);
>+			if (likely(!pd->entry[idx]))
>+				set_pd_entry(pd, idx, pt);
>+			else
>+				alloc = pt, pt = pd->entry[idx];
>+		}
>+
>+		if (lvl) {
>+			atomic_inc(&pt->used);
>+			spin_unlock(&pd->lock);
>+
>+			ret = __gen8_ppgtt_alloc(vm, as_pd(pt),
>+						 start, end, lvl);
>+			if (unlikely(ret)) {
>+				if (release_pd_entry(pd, idx, pt, scratch))
>+					free_px(vm, pt);
>+				goto out;
>+			}
>+
>+			spin_lock(&pd->lock);
>+			atomic_dec(&pt->used);
>+			GEM_BUG_ON(!atomic_read(&pt->used));
>+		} else {
>+			unsigned int count = gen8_pt_count(*start, end);
>+
>+			DBG("%s(%p):{lvl:%d, start:%llx, end:%llx, idx:%d, len:%d, used:%d} inserting pte\n",
>+			    __func__, vm, lvl, *start, end,
>+			    gen8_pd_index(*start, 0), count,
>+			    atomic_read(&pt->used));
>+
>+			atomic_add(count, &pt->used);
>+			GEM_BUG_ON(atomic_read(&pt->used) > I915_PDES);
>+			*start += count;
>+		}
>+	} while (idx++, --len);
>+	spin_unlock(&pd->lock);
>+out:
>+	if (alloc)
>+		free_px(vm, alloc);
>+	return ret;
> }
> 
>-/* Removes entries from a single pml4.
>- * This is the top-level structure in 4-level page tables used on gen8+.
>- * Empty entries are always scratch pml4e.
>- */
>-static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
>-				  u64 start, u64 length)
>+static int gen8_ppgtt_alloc(struct i915_address_space *vm,
>+			    u64 start, u64 length)
> {
>-	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>-	struct i915_page_directory * const pml4 = ppgtt->pd;
>-	struct i915_page_directory *pdp;
>-	unsigned int pml4e;
>-
>-	GEM_BUG_ON(!i915_vm_is_4lvl(vm));
>+	u64 from;
>+	int err;
> 
>-	gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
>-		bool free = false;
>-		GEM_BUG_ON(pdp == vm->scratch_pdp);
>+	GEM_BUG_ON(!IS_ALIGNED(start, BIT_ULL(GEN8_PTE_SHIFT)));
>+	GEM_BUG_ON(!IS_ALIGNED(length, BIT_ULL(GEN8_PTE_SHIFT)));
> 
>-		if (!gen8_ppgtt_clear_pdp(vm, pdp, start, length))
>-			continue;
>+	start >>= GEN8_PTE_SHIFT;
>+	length >>= GEN8_PTE_SHIFT;
>+	GEM_BUG_ON(length == 0);
>+	from = start;
>+
>+	err = __gen8_ppgtt_alloc(vm, i915_vm_to_ppgtt(vm)->pd,
>+				 &start, start + length, vm->top);
>+	if (unlikely(err && from != start))
>+		__gen8_ppgtt_clear(vm, i915_vm_to_ppgtt(vm)->pd,
>+				   from, start, vm->top);
> 
>-		spin_lock(&pml4->lock);
>-		if (!atomic_read(&pdp->used)) {
>-			gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e);
>-			pml4->entry[pml4e] = vm->scratch_pdp;
>-			free = true;
>-		}
>-		spin_unlock(&pml4->lock);
>-		if (free)
>-			free_pd(vm, pdp);
>-	}
>+	return err;
> }
> 
> static inline struct sgt_dma {
>@@ -933,47 +1136,28 @@
> 	return (struct sgt_dma) { sg, addr, addr + sg->length };
> }
> 
>-struct gen8_insert_pte {
>-	u16 pml4e;
>-	u16 pdpe;
>-	u16 pde;
>-	u16 pte;
>-};
>-
>-static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start)
>-{
>-	return (struct gen8_insert_pte) {
>-		 gen8_pml4e_index(start),
>-		 gen8_pdpe_index(start),
>-		 gen8_pde_index(start),
>-		 gen8_pte_index(start),
>-	};
>-}
>-
>-static __always_inline bool
>+static __always_inline u64
> gen8_ppgtt_insert_pte_entries(struct i915_ppgtt *ppgtt,
> 			      struct i915_page_directory *pdp,
> 			      struct sgt_dma *iter,
>-			      struct gen8_insert_pte *idx,
>+			      u64 idx,
> 			      enum i915_cache_level cache_level,
> 			      u32 flags)
> {
> 	struct i915_page_directory *pd;
> 	const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
> 	gen8_pte_t *vaddr;
>-	bool ret;
> 
>-	GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm));
>-	pd = i915_pd_entry(pdp, idx->pdpe);
>-	vaddr = kmap_atomic_px(i915_pt_entry(pd, idx->pde));
>+	pd = i915_pd_entry(pdp, gen8_pd_index(idx, 2));
>+	vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
> 	do {
>-		vaddr[idx->pte] = pte_encode | iter->dma;
>+		vaddr[gen8_pd_index(idx, 0)] = pte_encode | iter->dma;
> 
> 		iter->dma += I915_GTT_PAGE_SIZE;
> 		if (iter->dma >= iter->max) {
> 			iter->sg = __sg_next(iter->sg);
> 			if (!iter->sg) {
>-				ret = false;
>+				idx = 0;
> 				break;
> 			}
> 
>@@ -981,30 +1165,22 @@
> 			iter->max = iter->dma + iter->sg->length;
> 		}
> 
>-		if (++idx->pte == GEN8_PTES) {
>-			idx->pte = 0;
>-
>-			if (++idx->pde == I915_PDES) {
>-				idx->pde = 0;
>-
>+		if (gen8_pd_index(++idx, 0) == 0) {
>+			if (gen8_pd_index(idx, 1) == 0) {
> 				/* Limited by sg length for 3lvl */
>-				if (++idx->pdpe == GEN8_PML4ES_PER_PML4) {
>-					idx->pdpe = 0;
>-					ret = true;
>+				if (gen8_pd_index(idx, 2) == 0)
> 					break;
>-				}
> 
>-				GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->vm));
>-				pd = pdp->entry[idx->pdpe];
>+				pd = pdp->entry[gen8_pd_index(idx, 2)];
> 			}
> 
> 			kunmap_atomic(vaddr);
>-			vaddr = kmap_atomic_px(i915_pt_entry(pd, idx->pde));
>+			vaddr = kmap_atomic_px(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
> 		}
> 	} while (1);
> 	kunmap_atomic(vaddr);
> 
>-	return ret;
>+	return idx;
> }
> 
> static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
>@@ -1014,9 +1190,9 @@
> {
> 	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> 	struct sgt_dma iter = sgt_dma(vma);
>-	struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
> 
>-	gen8_ppgtt_insert_pte_entries(ppgtt, ppgtt->pd, &iter, &idx,
>+	gen8_ppgtt_insert_pte_entries(ppgtt, ppgtt->pd, &iter,
>+				      vma->node.start >> GEN8_PTE_SHIFT,
> 				      cache_level, flags);
> 
> 	vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
>@@ -1033,39 +1209,38 @@
> 	dma_addr_t rem = iter->sg->length;
> 
> 	do {
>-		struct gen8_insert_pte idx = gen8_insert_pte(start);
> 		struct i915_page_directory *pdp =
>-			i915_pdp_entry(pml4, idx.pml4e);
>-		struct i915_page_directory *pd = i915_pd_entry(pdp, idx.pdpe);
>-		unsigned int page_size;
>-		bool maybe_64K = false;
>+			i915_pd_entry(pml4, __gen8_pte_index(start, 3));
>+		struct i915_page_directory *pd =
>+			i915_pd_entry(pdp, __gen8_pte_index(start, 2));
> 		gen8_pte_t encode = pte_encode;
>+		unsigned int maybe_64K = -1;
>+		unsigned int page_size;
> 		gen8_pte_t *vaddr;
>-		u16 index, max;
>+		u16 index;
> 
> 		if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_2M &&
> 		    IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_2M) &&
>-		    rem >= I915_GTT_PAGE_SIZE_2M && !idx.pte) {
>-			index = idx.pde;
>-			max = I915_PDES;
>-			page_size = I915_GTT_PAGE_SIZE_2M;
>-
>+		    rem >= I915_GTT_PAGE_SIZE_2M &&
>+		    !__gen8_pte_index(start, 0)) {
>+			index = __gen8_pte_index(start, 1);
> 			encode |= GEN8_PDE_PS_2M;
>+			page_size = I915_GTT_PAGE_SIZE_2M;
> 
> 			vaddr = kmap_atomic_px(pd);
> 		} else {
>-			struct i915_page_table *pt = i915_pt_entry(pd, idx.pde);
>+			struct i915_page_table *pt =
>+				i915_pt_entry(pd, __gen8_pte_index(start, 1));
> 
>-			index = idx.pte;
>-			max = GEN8_PTES;
>+			index = __gen8_pte_index(start, 0);
> 			page_size = I915_GTT_PAGE_SIZE;
> 
> 			if (!index &&
> 			    vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K &&
> 			    IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
> 			    (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
>-			     rem >= (max - index) * I915_GTT_PAGE_SIZE))
>-				maybe_64K = true;
>+			     rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE))
>+				maybe_64K = __gen8_pte_index(start, 1);
> 
> 			vaddr = kmap_atomic_px(pt);
> 		}
>@@ -1086,16 +1261,16 @@
> 				iter->dma = sg_dma_address(iter->sg);
> 				iter->max = iter->dma + rem;
> 
>-				if (maybe_64K && index < max &&
>+				if (maybe_64K != -1 && index < I915_PDES &&
> 				    !(IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) &&
> 				      (IS_ALIGNED(rem, I915_GTT_PAGE_SIZE_64K) ||
>-				       rem >= (max - index) * I915_GTT_PAGE_SIZE)))
>-					maybe_64K = false;
>+				       rem >= (I915_PDES - index) * I915_GTT_PAGE_SIZE)))
>+					maybe_64K = -1;
> 
> 				if (unlikely(!IS_ALIGNED(iter->dma, page_size)))
> 					break;
> 			}
>-		} while (rem >= page_size && index < max);
>+		} while (rem >= page_size && index < I915_PDES);
> 
> 		kunmap_atomic(vaddr);
> 
>@@ -1105,14 +1280,14 @@
> 		 * it and have reached the end of the sg table and we have
> 		 * enough padding.
> 		 */
>-		if (maybe_64K &&
>-		    (index == max ||
>+		if (maybe_64K != -1 &&
>+		    (index == I915_PDES ||
> 		     (i915_vm_has_scratch_64K(vma->vm) &&
> 		      !iter->sg && IS_ALIGNED(vma->node.start +
> 					      vma->node.size,
> 					      I915_GTT_PAGE_SIZE_2M)))) {
> 			vaddr = kmap_atomic_px(pd);
>-			vaddr[idx.pde] |= GEN8_PDE_IPS_64K;
>+			vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
> 			kunmap_atomic(vaddr);
> 			page_size = I915_GTT_PAGE_SIZE_64K;
> 
>@@ -1128,9 +1303,8 @@
> 			if (I915_SELFTEST_ONLY(vma->vm->scrub_64K)) {
> 				u16 i;
> 
>-				encode = vma->vm->scratch_pte;
>-				vaddr = kmap_atomic_px(i915_pt_entry(pd,
>-								     idx.pde));
>+				encode = vma->vm->scratch[0].encode;
>+				vaddr = kmap_atomic_px(i915_pt_entry(pd, maybe_64K));
> 
> 				for (i = 1; i < index; i += 16)
> 					memset64(vaddr + i, encode, 15);
>@@ -1156,32 +1330,22 @@
> 		gen8_ppgtt_insert_huge_entries(vma, pml4, &iter, cache_level,
> 					       flags);
> 	} else {
>-		struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
>+		u64 idx = vma->node.start >> GEN8_PTE_SHIFT;
> 
>-		while (gen8_ppgtt_insert_pte_entries(ppgtt,
>-						     i915_pdp_entry(pml4, idx.pml4e++),
>-						     &iter, &idx, cache_level,
>-						     flags))
>-			GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
>+		while ((idx = gen8_ppgtt_insert_pte_entries(ppgtt,
>+							    i915_pd_entry(pml4, gen8_pd_index(idx, 3)),
>+							    &iter, idx, cache_level,
>+							    flags)))
>+			;
> 
> 		vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
> 	}
> }
> 
>-static void gen8_free_page_tables(struct i915_address_space *vm,
>-				  struct i915_page_directory *pd)
>-{
>-	int i;
>-
>-	for (i = 0; i < I915_PDES; i++) {
>-		if (pd->entry[i] != vm->scratch_pt)
>-			free_pt(vm, pd->entry[i]);
>-	}
>-}
>-
> static int gen8_init_scratch(struct i915_address_space *vm)
> {
> 	int ret;
>+	int i;
> 
> 	/*
> 	 * If everybody agrees to not to write into the scratch page,
>@@ -1195,10 +1359,8 @@
> 		GEM_BUG_ON(!clone->has_read_only);
> 
> 		vm->scratch_order = clone->scratch_order;
>-		vm->scratch_pte = clone->scratch_pte;
>-		vm->scratch_pt  = clone->scratch_pt;
>-		vm->scratch_pd  = clone->scratch_pd;
>-		vm->scratch_pdp = clone->scratch_pdp;
>+		memcpy(vm->scratch, clone->scratch, sizeof(vm->scratch));
>+		px_dma(&vm->scratch[0]) = 0; /* no xfer of ownership */
> 		return 0;
> 	}
> 
>@@ -1206,377 +1368,88 @@
> 	if (ret)
> 		return ret;
> 
>-	vm->scratch_pte =
>-		gen8_pte_encode(vm->scratch_page.daddr,
>-				I915_CACHE_LLC,
>-				vm->has_read_only);
>-
>-	vm->scratch_pt = alloc_pt(vm);
>-	if (IS_ERR(vm->scratch_pt)) {
>-		ret = PTR_ERR(vm->scratch_pt);
>-		goto free_scratch_page;
>-	}
>+	vm->scratch[0].encode =
>+		gen8_pte_encode(px_dma(&vm->scratch[0]),
>+				I915_CACHE_LLC, vm->has_read_only);
> 
>-	vm->scratch_pd = alloc_pd(vm);
>-	if (IS_ERR(vm->scratch_pd)) {
>-		ret = PTR_ERR(vm->scratch_pd);
>-		goto free_pt;
>-	}
>+	for (i = 1; i <= vm->top; i++) {
>+		if (unlikely(setup_page_dma(vm, px_base(&vm->scratch[i]))))
>+			goto free_scratch;
> 
>-	if (i915_vm_is_4lvl(vm)) {
>-		vm->scratch_pdp = alloc_pd(vm);
>-		if (IS_ERR(vm->scratch_pdp)) {
>-			ret = PTR_ERR(vm->scratch_pdp);
>-			goto free_pd;
>-		}
>+		fill_px(&vm->scratch[i], vm->scratch[i - 1].encode);
>+		vm->scratch[i].encode =
>+			gen8_pde_encode(px_dma(&vm->scratch[i]),
>+					I915_CACHE_LLC);
> 	}
> 
>-	gen8_initialize_pt(vm, vm->scratch_pt);
>-	init_pd_with_page(vm, vm->scratch_pd, vm->scratch_pt);
>-	if (i915_vm_is_4lvl(vm))
>-		init_pd(vm, vm->scratch_pdp, vm->scratch_pd);
>-
> 	return 0;
> 
>-free_pd:
>-	free_pd(vm, vm->scratch_pd);
>-free_pt:
>-	free_pt(vm, vm->scratch_pt);
>-free_scratch_page:
>-	cleanup_scratch_page(vm);
>-
>-	return ret;
>+free_scratch:
>+	free_scratch(vm);
>+	return -ENOMEM;
> }
> 
>-static int gen8_ppgtt_notify_vgt(struct i915_ppgtt *ppgtt, bool create)
>+static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt)
> {
> 	struct i915_address_space *vm = &ppgtt->vm;
>-	struct drm_i915_private *dev_priv = vm->i915;
>-	enum vgt_g2v_type msg;
>-	int i;
>-
>-	if (i915_vm_is_4lvl(vm)) {
>-		const u64 daddr = px_dma(ppgtt->pd);
>+	struct i915_page_directory *pd = ppgtt->pd;
>+	unsigned int idx;
> 
>-		I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
>-		I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
>+	GEM_BUG_ON(vm->top != 2);
>+	GEM_BUG_ON(gen8_pd_top_count(vm) != GEN8_3LVL_PDPES);
> 
>-		msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
>-				VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
>-	} else {
>-		for (i = 0; i < GEN8_3LVL_PDPES; i++) {
>-			const u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
>+	for (idx = 0; idx < GEN8_3LVL_PDPES; idx++) {
>+		struct i915_page_directory *pde;
> 
>-			I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
>-			I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
>-		}
>+		pde = alloc_pd(vm);
>+		if (IS_ERR(pde))
>+			return PTR_ERR(pde);
> 
>-		msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
>-				VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
>+		fill_px(pde, vm->scratch[1].encode);
>+		set_pd_entry(pd, idx, pde);
>+		atomic_inc(px_used(pde)); /* keep pinned */
> 	}
> 
>-	I915_WRITE(vgtif_reg(g2v_notify), msg);
>-
> 	return 0;
> }
> 
>-static void gen8_free_scratch(struct i915_address_space *vm)
>-{
>-	if (!vm->scratch_page.daddr)
>-		return;
>-
>-	if (i915_vm_is_4lvl(vm))
>-		free_pd(vm, vm->scratch_pdp);
>-	free_pd(vm, vm->scratch_pd);
>-	free_pt(vm, vm->scratch_pt);
>-	cleanup_scratch_page(vm);
>-}
>-
>-static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space *vm,
>-				    struct i915_page_directory *pdp)
>-{
>-	const unsigned int pdpes = i915_pdpes_per_pdp(vm);
>-	int i;
>-
>-	for (i = 0; i < pdpes; i++) {
>-		if (pdp->entry[i] == vm->scratch_pd)
>-			continue;
>-
>-		gen8_free_page_tables(vm, pdp->entry[i]);
>-		free_pd(vm, pdp->entry[i]);
>-	}
>-
>-	free_pd(vm, pdp);
>-}
>-
>-static void gen8_ppgtt_cleanup_4lvl(struct i915_ppgtt *ppgtt)
>-{
>-	struct i915_page_directory * const pml4 = ppgtt->pd;
>-	int i;
>-
>-	for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) {
>-		struct i915_page_directory *pdp = i915_pdp_entry(pml4, i);
>-
>-		if (pdp == ppgtt->vm.scratch_pdp)
>-			continue;
>-
>-		gen8_ppgtt_cleanup_3lvl(&ppgtt->vm, pdp);
>-	}
>-
>-	free_pd(&ppgtt->vm, pml4);
>-}
>-
>-static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
>-{
>-	struct drm_i915_private *i915 = vm->i915;
>-	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>-
>-	if (intel_vgpu_active(i915))
>-		gen8_ppgtt_notify_vgt(ppgtt, false);
>-
>-	if (i915_vm_is_4lvl(vm))
>-		gen8_ppgtt_cleanup_4lvl(ppgtt);
>-	else
>-		gen8_ppgtt_cleanup_3lvl(&ppgtt->vm, ppgtt->pd);
>-
>-	gen8_free_scratch(vm);
>-}
>-
>-static int gen8_ppgtt_alloc_pd(struct i915_address_space *vm,
>-			       struct i915_page_directory *pd,
>-			       u64 start, u64 length)
>+static void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
> {
>-	struct i915_page_table *pt, *alloc = NULL;
>-	u64 from = start;
>-	unsigned int pde;
>-	int ret = 0;
>-
>-	spin_lock(&pd->lock);
>-	gen8_for_each_pde(pt, pd, start, length, pde) {
>-		const int count = gen8_pte_count(start, length);
>+	struct drm_i915_private *i915 = gt->i915;
> 
>-		if (pt == vm->scratch_pt) {
>-			spin_unlock(&pd->lock);
>-
>-			pt = fetch_and_zero(&alloc);
>-			if (!pt)
>-				pt = alloc_pt(vm);
>-			if (IS_ERR(pt)) {
>-				ret = PTR_ERR(pt);
>-				goto unwind;
>-			}
>-
>-			if (count < GEN8_PTES || intel_vgpu_active(vm->i915))
>-				gen8_initialize_pt(vm, pt);
>-
>-			spin_lock(&pd->lock);
>-			if (pd->entry[pde] == vm->scratch_pt) {
>-				gen8_ppgtt_set_pde(vm, pd, pt, pde);
>-				pd->entry[pde] = pt;
>-				atomic_inc(&pd->used);
>-			} else {
>-				alloc = pt;
>-				pt = pd->entry[pde];
>-			}
>-		}
>-
>-		atomic_add(count, &pt->used);
>-	}
>-	spin_unlock(&pd->lock);
>-	goto out;
>-
>-unwind:
>-	gen8_ppgtt_clear_pd(vm, pd, from, start - from);
>-out:
>-	if (alloc)
>-		free_pt(vm, alloc);
>-	return ret;
>-}
>-
>-static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm,
>-				struct i915_page_directory *pdp,
>-				u64 start, u64 length)
>-{
>-	struct i915_page_directory *pd, *alloc = NULL;
>-	u64 from = start;
>-	unsigned int pdpe;
>-	int ret = 0;
>-
>-	spin_lock(&pdp->lock);
>-	gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
>-		if (pd == vm->scratch_pd) {
>-			spin_unlock(&pdp->lock);
>-
>-			pd = fetch_and_zero(&alloc);
>-			if (!pd)
>-				pd = alloc_pd(vm);
>-			if (IS_ERR(pd)) {
>-				ret = PTR_ERR(pd);
>-				goto unwind;
>-			}
>-
>-			init_pd_with_page(vm, pd, vm->scratch_pt);
>-
>-			spin_lock(&pdp->lock);
>-			if (pdp->entry[pdpe] == vm->scratch_pd) {
>-				gen8_ppgtt_set_pdpe(pdp, pd, pdpe);
>-				pdp->entry[pdpe] = pd;
>-				atomic_inc(&pdp->used);
>-			} else {
>-				alloc = pd;
>-				pd = pdp->entry[pdpe];
>-			}
>-		}
>-		atomic_inc(&pd->used);
>-		spin_unlock(&pdp->lock);
>-
>-		ret = gen8_ppgtt_alloc_pd(vm, pd, start, length);
>-		if (unlikely(ret))
>-			goto unwind_pd;
>-
>-		spin_lock(&pdp->lock);
>-		atomic_dec(&pd->used);
>-	}
>-	spin_unlock(&pdp->lock);
>-	goto out;
>-
>-unwind_pd:
>-	spin_lock(&pdp->lock);
>-	if (atomic_dec_and_test(&pd->used)) {
>-		gen8_ppgtt_set_pdpe(pdp, vm->scratch_pd, pdpe);
>-		pdp->entry[pdpe] = vm->scratch_pd;
>-		GEM_BUG_ON(!atomic_read(&pdp->used));
>-		atomic_dec(&pdp->used);
>-		GEM_BUG_ON(alloc);
>-		alloc = pd; /* defer the free to after the lock */
>-	}
>-	spin_unlock(&pdp->lock);
>-unwind:
>-	gen8_ppgtt_clear_pdp(vm, pdp, from, start - from);
>-out:
>-	if (alloc)
>-		free_pd(vm, alloc);
>-	return ret;
>-}
>-
>-static int gen8_ppgtt_alloc_3lvl(struct i915_address_space *vm,
>-				 u64 start, u64 length)
>-{
>-	return gen8_ppgtt_alloc_pdp(vm,
>-				    i915_vm_to_ppgtt(vm)->pd, start, length);
>-}
>-
>-static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
>-				 u64 start, u64 length)
>-{
>-	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
>-	struct i915_page_directory * const pml4 = ppgtt->pd;
>-	struct i915_page_directory *pdp, *alloc = NULL;
>-	u64 from = start;
>-	int ret = 0;
>-	u32 pml4e;
>-
>-	spin_lock(&pml4->lock);
>-	gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
>-		if (pdp == vm->scratch_pdp) {
>-			spin_unlock(&pml4->lock);
>-
>-			pdp = fetch_and_zero(&alloc);
>-			if (!pdp)
>-				pdp = alloc_pd(vm);
>-			if (IS_ERR(pdp)) {
>-				ret = PTR_ERR(pdp);
>-				goto unwind;
>-			}
>-
>-			init_pd(vm, pdp, vm->scratch_pd);
>-
>-			spin_lock(&pml4->lock);
>-			if (pml4->entry[pml4e] == vm->scratch_pdp) {
>-				gen8_ppgtt_set_pml4e(pml4, pdp, pml4e);
>-				pml4->entry[pml4e] = pdp;
>-			} else {
>-				alloc = pdp;
>-				pdp = pml4->entry[pml4e];
>-			}
>-		}
>-		atomic_inc(&pdp->used);
>-		spin_unlock(&pml4->lock);
>-
>-		ret = gen8_ppgtt_alloc_pdp(vm, pdp, start, length);
>-		if (unlikely(ret))
>-			goto unwind_pdp;
>+	ppgtt->vm.gt = gt;
>+	ppgtt->vm.i915 = i915;
>+	ppgtt->vm.dma = &i915->drm.pdev->dev;
>+	ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
> 
>-		spin_lock(&pml4->lock);
>-		atomic_dec(&pdp->used);
>-	}
>-	spin_unlock(&pml4->lock);
>-	goto out;
>+	i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
> 
>-unwind_pdp:
>-	spin_lock(&pml4->lock);
>-	if (atomic_dec_and_test(&pdp->used)) {
>-		gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e);
>-		pml4->entry[pml4e] = vm->scratch_pdp;
>-		GEM_BUG_ON(alloc);
>-		alloc = pdp; /* defer the free until after the lock */
>-	}
>-	spin_unlock(&pml4->lock);
>-unwind:
>-	gen8_ppgtt_clear_4lvl(vm, from, start - from);
>-out:
>-	if (alloc)
>-		free_pd(vm, alloc);
>-	return ret;
>+	ppgtt->vm.vma_ops.bind_vma    = ppgtt_bind_vma;
>+	ppgtt->vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
>+	ppgtt->vm.vma_ops.set_pages   = ppgtt_set_pages;
>+	ppgtt->vm.vma_ops.clear_pages = clear_pages;
> }
> 
>-static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt)
>+static struct i915_page_directory *
>+gen8_alloc_top_pd(struct i915_address_space *vm)
> {
>-	struct i915_address_space *vm = &ppgtt->vm;
>-	struct i915_page_directory *pdp = ppgtt->pd;
>+	const unsigned int count = gen8_pd_top_count(vm);
> 	struct i915_page_directory *pd;
>-	u64 start = 0, length = ppgtt->vm.total;
>-	u64 from = start;
>-	unsigned int pdpe;
>-
>-	gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
>-		pd = alloc_pd(vm);
>-		if (IS_ERR(pd))
>-			goto unwind;
> 
>-		init_pd_with_page(vm, pd, vm->scratch_pt);
>-		gen8_ppgtt_set_pdpe(pdp, pd, pdpe);
>+	GEM_BUG_ON(count > ARRAY_SIZE(pd->entry));
> 
>-		atomic_inc(&pdp->used);
>-	}
>-
>-	atomic_inc(&pdp->used); /* never remove */
>-
>-	return 0;
>+	pd = __alloc_pd(offsetof(typeof(*pd), entry[count]));
>+	if (unlikely(!pd))
>+		return ERR_PTR(-ENOMEM);
> 
>-unwind:
>-	start -= from;
>-	gen8_for_each_pdpe(pd, pdp, from, start, pdpe) {
>-		gen8_ppgtt_set_pdpe(pdp, vm->scratch_pd, pdpe);
>-		free_pd(vm, pd);
>+	if (unlikely(setup_page_dma(vm, px_base(pd)))) {
>+		kfree(pd);
>+		return ERR_PTR(-ENOMEM);
> 	}
>-	atomic_set(&pdp->used, 0);
>-	return -ENOMEM;
>-}
>-
>-static void ppgtt_init(struct drm_i915_private *i915,
>-		       struct i915_ppgtt *ppgtt)
>-{
>-	ppgtt->vm.i915 = i915;
>-	ppgtt->vm.dma = &i915->drm.pdev->dev;
>-	ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
>-
>-	i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
> 
>-	ppgtt->vm.vma_ops.bind_vma    = ppgtt_bind_vma;
>-	ppgtt->vm.vma_ops.unbind_vma  = ppgtt_unbind_vma;
>-	ppgtt->vm.vma_ops.set_pages   = ppgtt_set_pages;
>-	ppgtt->vm.vma_ops.clear_pages = clear_pages;
>+	fill_page_dma(px_base(pd), vm->scratch[vm->top].encode, count);
>+	atomic_inc(px_used(pd)); /* mark as pinned */
>+	return pd;
> }
> 
> /*
>@@ -1595,7 +1468,8 @@
> 	if (!ppgtt)
> 		return ERR_PTR(-ENOMEM);
> 
>-	ppgtt_init(i915, ppgtt);
>+	ppgtt_init(ppgtt, &i915->gt);
>+	ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
> 
> 	/*
> 	 * From bdw, there is hw support for read-only pages in the PPGTT.
>@@ -1615,41 +1489,27 @@
> 	if (err)
> 		goto err_free;
> 
>-	ppgtt->pd = __alloc_pd();
>-	if (!ppgtt->pd) {
>-		err = -ENOMEM;
>+	ppgtt->pd = gen8_alloc_top_pd(&ppgtt->vm);
>+	if (IS_ERR(ppgtt->pd)) {
>+		err = PTR_ERR(ppgtt->pd);
> 		goto err_free_scratch;
> 	}
> 
> 	if (i915_vm_is_4lvl(&ppgtt->vm)) {
>-		err = setup_px(&ppgtt->vm, ppgtt->pd);
>-		if (err)
>-			goto err_free_pdp;
>-
>-		init_pd(&ppgtt->vm, ppgtt->pd, ppgtt->vm.scratch_pdp);
>-
>-		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
> 		ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
>-		ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
> 	} else {
>-		/*
>-		 * We don't need to setup dma for top level pdp, only
>-		 * for entries. So point entries to scratch.
>-		 */
>-		memset_p(ppgtt->pd->entry, ppgtt->vm.scratch_pd,
>-			 GEN8_3LVL_PDPES);
>-
> 		if (intel_vgpu_active(i915)) {
> 			err = gen8_preallocate_top_level_pdp(ppgtt);
> 			if (err)
>-				goto err_free_pdp;
>+				goto err_free_pd;
> 		}
> 
>-		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_3lvl;
> 		ppgtt->vm.insert_entries = gen8_ppgtt_insert_3lvl;
>-		ppgtt->vm.clear_range = gen8_ppgtt_clear_3lvl;
> 	}
> 
>+	ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
>+	ppgtt->vm.clear_range = gen8_ppgtt_clear;
>+
> 	if (intel_vgpu_active(i915))
> 		gen8_ppgtt_notify_vgt(ppgtt, true);
> 
>@@ -1657,10 +1517,11 @@
> 
> 	return ppgtt;
> 
>-err_free_pdp:
>-	free_pd(&ppgtt->vm, ppgtt->pd);
>+err_free_pd:
>+	__gen8_ppgtt_cleanup(&ppgtt->vm, ppgtt->pd,
>+			     gen8_pd_top_count(&ppgtt->vm), ppgtt->vm.top);
> err_free_scratch:
>-	gen8_free_scratch(&ppgtt->vm);
>+	free_scratch(&ppgtt->vm);
> err_free:
> 	kfree(ppgtt);
> 	return ERR_PTR(err);
>@@ -1676,25 +1537,26 @@
> 		  ppgtt->pd_addr + pde);
> }
> 
>-static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
>+static void gen7_ppgtt_enable(struct intel_gt *gt)
> {
>+	struct drm_i915_private *i915 = gt->i915;
>+	struct intel_uncore *uncore = gt->uncore;
> 	struct intel_engine_cs *engine;
>-	u32 ecochk, ecobits;
> 	enum intel_engine_id id;
>+	u32 ecochk;
> 
>-	ecobits = I915_READ(GAC_ECO_BITS);
>-	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
>+	intel_uncore_rmw(uncore, GAC_ECO_BITS, 0, ECOBITS_PPGTT_CACHE64B);
> 
>-	ecochk = I915_READ(GAM_ECOCHK);
>-	if (IS_HASWELL(dev_priv)) {
>+	ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
>+	if (IS_HASWELL(i915)) {
> 		ecochk |= ECOCHK_PPGTT_WB_HSW;
> 	} else {
> 		ecochk |= ECOCHK_PPGTT_LLC_IVB;
> 		ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
> 	}
>-	I915_WRITE(GAM_ECOCHK, ecochk);
>+	intel_uncore_write(uncore, GAM_ECOCHK, ecochk);
> 
>-	for_each_engine(engine, dev_priv, id) {
>+	for_each_engine(engine, i915, id) {
> 		/* GFX_MODE is per-ring on gen7+ */
> 		ENGINE_WRITE(engine,
> 			     RING_MODE_GEN7,
>@@ -1702,22 +1564,29 @@
> 	}
> }
> 
>-static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
>+static void gen6_ppgtt_enable(struct intel_gt *gt)
> {
>-	u32 ecochk, gab_ctl, ecobits;
>-
>-	ecobits = I915_READ(GAC_ECO_BITS);
>-	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
>-		   ECOBITS_PPGTT_CACHE64B);
>+	struct intel_uncore *uncore = gt->uncore;
> 
>-	gab_ctl = I915_READ(GAB_CTL);
>-	I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
>-
>-	ecochk = I915_READ(GAM_ECOCHK);
>-	I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
>-
>-	if (HAS_PPGTT(dev_priv)) /* may be disabled for VT-d */
>-		I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
>+	intel_uncore_rmw(uncore,
>+			 GAC_ECO_BITS,
>+			 0,
>+			 ECOBITS_SNB_BIT | ECOBITS_PPGTT_CACHE64B);
>+
>+	intel_uncore_rmw(uncore,
>+			 GAB_CTL,
>+			 0,
>+			 GAB_CTL_CONT_AFTER_PAGEFAULT);
>+
>+	intel_uncore_rmw(uncore,
>+			 GAM_ECOCHK,
>+			 0,
>+			 ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
>+
>+	if (HAS_PPGTT(uncore->i915)) /* may be disabled for VT-d */
>+		intel_uncore_write(uncore,
>+				   GFX_MODE,
>+				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
> }
> 
> /* PPGTT support for Sandybdrige/Gen6 and later */
>@@ -1726,7 +1595,7 @@
> {
> 	struct gen6_ppgtt * const ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
> 	const unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
>-	const gen6_pte_t scratch_pte = vm->scratch_pte;
>+	const gen6_pte_t scratch_pte = vm->scratch[0].encode;
> 	unsigned int pde = first_entry / GEN6_PTES;
> 	unsigned int pte = first_entry % GEN6_PTES;
> 	unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
>@@ -1737,7 +1606,7 @@
> 		const unsigned int count = min(num_entries, GEN6_PTES - pte);
> 		gen6_pte_t *vaddr;
> 
>-		GEM_BUG_ON(pt == vm->scratch_pt);
>+		GEM_BUG_ON(px_base(pt) == px_base(&vm->scratch[1]));
> 
> 		num_entries -= count;
> 
>@@ -1774,7 +1643,7 @@
> 	struct sgt_dma iter = sgt_dma(vma);
> 	gen6_pte_t *vaddr;
> 
>-	GEM_BUG_ON(i915_pt_entry(pd, act_pt) == vm->scratch_pt);
>+	GEM_BUG_ON(pd->entry[act_pt] == &vm->scratch[1]);
> 
> 	vaddr = kmap_atomic_px(i915_pt_entry(pd, act_pt));
> 	do {
>@@ -1819,7 +1688,7 @@
> 	gen6_for_each_pde(pt, pd, start, length, pde) {
> 		const unsigned int count = gen6_pte_count(start, length);
> 
>-		if (pt == vm->scratch_pt) {
>+		if (px_base(pt) == px_base(&vm->scratch[1])) {
> 			spin_unlock(&pd->lock);
> 
> 			pt = fetch_and_zero(&alloc);
>@@ -1830,10 +1699,10 @@
> 				goto unwind_out;
> 			}
> 
>-			gen6_initialize_pt(vm, pt);
>+			fill32_px(pt, vm->scratch[0].encode);
> 
> 			spin_lock(&pd->lock);
>-			if (pd->entry[pde] == vm->scratch_pt) {
>+			if (pd->entry[pde] == &vm->scratch[1]) {
> 				pd->entry[pde] = pt;
> 				if (i915_vma_is_bound(ppgtt->vma,
> 						      I915_VMA_GLOBAL_BIND)) {
>@@ -1852,7 +1721,7 @@
> 
> 	if (flush) {
> 		mark_tlbs_dirty(&ppgtt->base);
>-		gen6_ggtt_invalidate(vm->i915);
>+		gen6_ggtt_invalidate(vm->gt->ggtt);
> 	}
> 
> 	goto out;
>@@ -1861,7 +1730,7 @@
> 	gen6_ppgtt_clear_range(vm, from, start - from);
> out:
> 	if (alloc)
>-		free_pt(vm, alloc);
>+		free_px(vm, alloc);
> 	intel_runtime_pm_put(&vm->i915->runtime_pm, wakeref);
> 	return ret;
> }
>@@ -1870,108 +1739,52 @@
> {
> 	struct i915_address_space * const vm = &ppgtt->base.vm;
> 	struct i915_page_directory * const pd = ppgtt->base.pd;
>-	struct i915_page_table *unused;
>-	u32 pde;
> 	int ret;
> 
> 	ret = setup_scratch_page(vm, __GFP_HIGHMEM);
> 	if (ret)
> 		return ret;
> 
>-	vm->scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
>-					 I915_CACHE_NONE,
>-					 PTE_READ_ONLY);
>+	vm->scratch[0].encode =
>+		vm->pte_encode(px_dma(&vm->scratch[0]),
>+			       I915_CACHE_NONE, PTE_READ_ONLY);
> 
>-	vm->scratch_pt = alloc_pt(vm);
>-	if (IS_ERR(vm->scratch_pt)) {
>+	if (unlikely(setup_page_dma(vm, px_base(&vm->scratch[1])))) {
> 		cleanup_scratch_page(vm);
>-		return PTR_ERR(vm->scratch_pt);
>+		return -ENOMEM;
> 	}
> 
>-	gen6_initialize_pt(vm, vm->scratch_pt);
>-
>-	gen6_for_all_pdes(unused, pd, pde)
>-		pd->entry[pde] = vm->scratch_pt;
>+	fill32_px(&vm->scratch[1], vm->scratch[0].encode);
>+	memset_p(pd->entry, &vm->scratch[1], I915_PDES);
> 
> 	return 0;
> }
> 
>-static void gen6_ppgtt_free_scratch(struct i915_address_space *vm)
>-{
>-	free_pt(vm, vm->scratch_pt);
>-	cleanup_scratch_page(vm);
>-}
>-
> static void gen6_ppgtt_free_pd(struct gen6_ppgtt *ppgtt)
> {
> 	struct i915_page_directory * const pd = ppgtt->base.pd;
>+	struct i915_page_dma * const scratch =
>+		px_base(&ppgtt->base.vm.scratch[1]);
> 	struct i915_page_table *pt;
> 	u32 pde;
> 
> 	gen6_for_all_pdes(pt, pd, pde)
>-		if (pt != ppgtt->base.vm.scratch_pt)
>-			free_pt(&ppgtt->base.vm, pt);
>-}
>-
>-struct gen6_ppgtt_cleanup_work {
>-	struct work_struct base;
>-	struct i915_vma *vma;
>-};
>-
>-static void gen6_ppgtt_cleanup_work(struct work_struct *wrk)
>-{
>-	struct gen6_ppgtt_cleanup_work *work =
>-		container_of(wrk, typeof(*work), base);
>-	/* Side note, vma->vm is the GGTT not the ppgtt we just destroyed! */
>-	struct drm_i915_private *i915 = work->vma->vm->i915;
>-
>-	mutex_lock(&i915->drm.struct_mutex);
>-	i915_vma_destroy(work->vma);
>-	mutex_unlock(&i915->drm.struct_mutex);
>-
>-	kfree(work);
>-}
>-
>-static int nop_set_pages(struct i915_vma *vma)
>-{
>-	return -ENODEV;
>-}
>-
>-static void nop_clear_pages(struct i915_vma *vma)
>-{
>-}
>-
>-static int nop_bind(struct i915_vma *vma,
>-		    enum i915_cache_level cache_level,
>-		    u32 unused)
>-{
>-	return -ENODEV;
>-}
>-
>-static void nop_unbind(struct i915_vma *vma)
>-{
>+		if (px_base(pt) != scratch)
>+			free_px(&ppgtt->base.vm, pt);
> }
> 
>-static const struct i915_vma_ops nop_vma_ops = {
>-	.set_pages = nop_set_pages,
>-	.clear_pages = nop_clear_pages,
>-	.bind_vma = nop_bind,
>-	.unbind_vma = nop_unbind,
>-};
>-
> static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
> {
> 	struct gen6_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
>-	struct gen6_ppgtt_cleanup_work *work = ppgtt->work;
>+	struct drm_i915_private *i915 = vm->i915;
> 
> 	/* FIXME remove the struct_mutex to bring the locking under control */
>-	INIT_WORK(&work->base, gen6_ppgtt_cleanup_work);
>-	work->vma = ppgtt->vma;
>-	work->vma->ops = &nop_vma_ops;
>-	schedule_work(&work->base);
>+	mutex_lock(&i915->drm.struct_mutex);
>+	i915_vma_destroy(ppgtt->vma);
>+	mutex_unlock(&i915->drm.struct_mutex);
> 
> 	gen6_ppgtt_free_pd(ppgtt);
>-	gen6_ppgtt_free_scratch(vm);
>+	free_scratch(vm);
> 	kfree(ppgtt->base.pd);
> }
> 
>@@ -1998,14 +1811,14 @@
> 	struct i915_page_table *pt;
> 	unsigned int pde;
> 
>-	ppgtt->base.pd->base.ggtt_offset = ggtt_offset * sizeof(gen6_pte_t);
>+	px_base(ppgtt->base.pd)->ggtt_offset = ggtt_offset * sizeof(gen6_pte_t);
> 	ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + ggtt_offset;
> 
> 	gen6_for_all_pdes(pt, ppgtt->base.pd, pde)
> 		gen6_write_pde(ppgtt, pde, pt);
> 
> 	mark_tlbs_dirty(&ppgtt->base);
>-	gen6_ggtt_invalidate(ppgtt->base.vm.i915);
>+	gen6_ggtt_invalidate(ggtt);
> 
> 	return 0;
> }
>@@ -2014,7 +1827,8 @@
> {
> 	struct gen6_ppgtt *ppgtt = vma->private;
> 	struct i915_page_directory * const pd = ppgtt->base.pd;
>-	struct i915_page_table * const scratch_pt = ppgtt->base.vm.scratch_pt;
>+	struct i915_page_dma * const scratch =
>+		px_base(&ppgtt->base.vm.scratch[1]);
> 	struct i915_page_table *pt;
> 	unsigned int pde;
> 
>@@ -2023,11 +1837,11 @@
> 
> 	/* Free all no longer used page tables */
> 	gen6_for_all_pdes(pt, ppgtt->base.pd, pde) {
>-		if (atomic_read(&pt->used) || pt == scratch_pt)
>+		if (px_base(pt) == scratch || atomic_read(&pt->used))
> 			continue;
> 
>-		free_pt(&ppgtt->base.vm, pt);
>-		pd->entry[pde] = scratch_pt;
>+		free_px(&ppgtt->base.vm, pt);
>+		pd->entry[pde] = scratch;
> 	}
> 
> 	ppgtt->scan_for_unused_pt = false;
>@@ -2043,7 +1857,7 @@
> static struct i915_vma *pd_vma_create(struct gen6_ppgtt *ppgtt, int size)
> {
> 	struct drm_i915_private *i915 = ppgtt->base.vm.i915;
>-	struct i915_ggtt *ggtt = &i915->ggtt;
>+	struct i915_ggtt *ggtt = ppgtt->base.vm.gt->ggtt;
> 	struct i915_vma *vma;
> 
> 	GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
>@@ -2053,7 +1867,7 @@
> 	if (!vma)
> 		return ERR_PTR(-ENOMEM);
> 
>-	i915_active_init(i915, &vma->active, NULL);
>+	i915_active_init(i915, &vma->active, NULL, NULL);
> 	INIT_ACTIVE_REQUEST(&vma->last_fence);
> 
> 	vma->vm = &ggtt->vm;
>@@ -2141,7 +1955,8 @@
> 	if (!ppgtt)
> 		return ERR_PTR(-ENOMEM);
> 
>-	ppgtt_init(i915, &ppgtt->base);
>+	ppgtt_init(&ppgtt->base, &i915->gt);
>+	ppgtt->base.vm.top = 1;
> 
> 	ppgtt->base.vm.allocate_va_range = gen6_alloc_va_range;
> 	ppgtt->base.vm.clear_range = gen6_ppgtt_clear_range;
>@@ -2150,16 +1965,10 @@
> 
> 	ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;
> 
>-	ppgtt->work = kmalloc(sizeof(*ppgtt->work), GFP_KERNEL);
>-	if (!ppgtt->work) {
>-		err = -ENOMEM;
>-		goto err_free;
>-	}
>-
>-	ppgtt->base.pd = __alloc_pd();
>+	ppgtt->base.pd = __alloc_pd(sizeof(*ppgtt->base.pd));
> 	if (!ppgtt->base.pd) {
> 		err = -ENOMEM;
>-		goto err_work;
>+		goto err_free;
> 	}
> 
> 	err = gen6_ppgtt_init_scratch(ppgtt);
>@@ -2175,31 +1984,40 @@
> 	return &ppgtt->base;
> 
> err_scratch:
>-	gen6_ppgtt_free_scratch(&ppgtt->base.vm);
>+	free_scratch(&ppgtt->base.vm);
> err_pd:
> 	kfree(ppgtt->base.pd);
>-err_work:
>-	kfree(ppgtt->work);
> err_free:
> 	kfree(ppgtt);
> 	return ERR_PTR(err);
> }
> 
>-static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
>+static void gtt_write_workarounds(struct intel_gt *gt)
> {
>+	struct drm_i915_private *i915 = gt->i915;
>+	struct intel_uncore *uncore = gt->uncore;
>+
> 	/* This function is for gtt related workarounds. This function is
> 	 * called on driver load and after a GPU reset, so you can place
> 	 * workarounds here even if they get overwritten by GPU reset.
> 	 */
> 	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
>-	if (IS_BROADWELL(dev_priv))
>-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>-	else if (IS_CHERRYVIEW(dev_priv))
>-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
>-	else if (IS_GEN9_LP(dev_priv))
>-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
>-	else if (INTEL_GEN(dev_priv) >= 9)
>-		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
>+	if (IS_BROADWELL(i915))
>+		intel_uncore_write(uncore,
>+				   GEN8_L3_LRA_1_GPGPU,
>+				   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>+	else if (IS_CHERRYVIEW(i915))
>+		intel_uncore_write(uncore,
>+				   GEN8_L3_LRA_1_GPGPU,
>+				   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
>+	else if (IS_GEN9_LP(i915))
>+		intel_uncore_write(uncore,
>+				   GEN8_L3_LRA_1_GPGPU,
>+				   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
>+	else if (INTEL_GEN(i915) >= 9)
>+		intel_uncore_write(uncore,
>+				   GEN8_L3_LRA_1_GPGPU,
>+				   GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> 
> 	/*
> 	 * To support 64K PTEs we need to first enable the use of the
>@@ -2212,21 +2030,24 @@
> 	 * 32K pages, but we don't currently have any support for it in our
> 	 * driver.
> 	 */
>-	if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) &&
>-	    INTEL_GEN(dev_priv) <= 10)
>-		I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA,
>-			   I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) |
>-			   GAMW_ECO_ENABLE_64K_IPS_FIELD);
>+	if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) &&
>+	    INTEL_GEN(i915) <= 10)
>+		intel_uncore_rmw(uncore,
>+				 GEN8_GAMW_ECO_DEV_RW_IA,
>+				 0,
>+				 GAMW_ECO_ENABLE_64K_IPS_FIELD);
> }
> 
>-int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
>+int i915_ppgtt_init_hw(struct intel_gt *gt)
> {
>-	gtt_write_workarounds(dev_priv);
>+	struct drm_i915_private *i915 = gt->i915;
> 
>-	if (IS_GEN(dev_priv, 6))
>-		gen6_ppgtt_enable(dev_priv);
>-	else if (IS_GEN(dev_priv, 7))
>-		gen7_ppgtt_enable(dev_priv);
>+	gtt_write_workarounds(gt);
>+
>+	if (IS_GEN(i915, 6))
>+		gen6_ppgtt_enable(gt);
>+	else if (IS_GEN(i915, 7))
>+		gen7_ppgtt_enable(gt);
> 
> 	return 0;
> }
>@@ -2254,42 +2075,6 @@
> 	return ppgtt;
> }
> 
>-static void ppgtt_destroy_vma(struct i915_address_space *vm)
>-{
>-	struct list_head *phases[] = {
>-		&vm->bound_list,
>-		&vm->unbound_list,
>-		NULL,
>-	}, **phase;
>-
>-	vm->closed = true;
>-	for (phase = phases; *phase; phase++) {
>-		struct i915_vma *vma, *vn;
>-
>-		list_for_each_entry_safe(vma, vn, *phase, vm_link)
>-			i915_vma_destroy(vma);
>-	}
>-}
>-
>-void i915_vm_release(struct kref *kref)
>-{
>-	struct i915_address_space *vm =
>-		container_of(kref, struct i915_address_space, ref);
>-
>-	GEM_BUG_ON(i915_is_ggtt(vm));
>-	trace_i915_ppgtt_release(vm);
>-
>-	ppgtt_destroy_vma(vm);
>-
>-	GEM_BUG_ON(!list_empty(&vm->bound_list));
>-	GEM_BUG_ON(!list_empty(&vm->unbound_list));
>-
>-	vm->cleanup(vm);
>-	i915_address_space_fini(vm);
>-
>-	kfree(vm);
>-}
>-
> /* Certain Gen5 chipsets require require idling the GPU before
>  * unmapping anything from the GTT when VT-d is enabled.
>  */
>@@ -2301,21 +2086,26 @@
> 	return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active();
> }
> 
>-void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
>+static void ggtt_suspend_mappings(struct i915_ggtt *ggtt)
> {
>-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
>+	struct drm_i915_private *i915 = ggtt->vm.i915;
> 
> 	/* Don't bother messing with faults pre GEN6 as we have little
> 	 * documentation supporting that it's a good idea.
> 	 */
>-	if (INTEL_GEN(dev_priv) < 6)
>+	if (INTEL_GEN(i915) < 6)
> 		return;
> 
>-	i915_check_and_clear_faults(dev_priv);
>+	intel_gt_check_and_clear_faults(ggtt->vm.gt);
> 
> 	ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
> 
>-	i915_ggtt_invalidate(dev_priv);
>+	ggtt->invalidate(ggtt);
>+}
>+
>+void i915_gem_suspend_gtt_mappings(struct drm_i915_private *i915)
>+{
>+	ggtt_suspend_mappings(&i915->ggtt);
> }
> 
> int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
>@@ -2361,7 +2151,7 @@
> 
> 	gen8_set_pte(pte, gen8_pte_encode(addr, level, 0));
> 
>-	ggtt->invalidate(vm->i915);
>+	ggtt->invalidate(ggtt);
> }
> 
> static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
>@@ -2389,7 +2179,7 @@
> 	 * We want to flush the TLBs only after we're certain all the PTE
> 	 * updates have finished.
> 	 */
>-	ggtt->invalidate(vm->i915);
>+	ggtt->invalidate(ggtt);
> }
> 
> static void gen6_ggtt_insert_page(struct i915_address_space *vm,
>@@ -2404,7 +2194,7 @@
> 
> 	iowrite32(vm->pte_encode(addr, level, flags), pte);
> 
>-	ggtt->invalidate(vm->i915);
>+	ggtt->invalidate(ggtt);
> }
> 
> /*
>@@ -2430,7 +2220,7 @@
> 	 * We want to flush the TLBs only after we're certain all the PTE
> 	 * updates have finished.
> 	 */
>-	ggtt->invalidate(vm->i915);
>+	ggtt->invalidate(ggtt);
> }
> 
> static void nop_clear_range(struct i915_address_space *vm,
>@@ -2444,7 +2234,7 @@
> 	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
> 	unsigned first_entry = start / I915_GTT_PAGE_SIZE;
> 	unsigned num_entries = length / I915_GTT_PAGE_SIZE;
>-	const gen8_pte_t scratch_pte = vm->scratch_pte;
>+	const gen8_pte_t scratch_pte = vm->scratch[0].encode;
> 	gen8_pte_t __iomem *gtt_base =
> 		(gen8_pte_t __iomem *)ggtt->gsm + first_entry;
> 	const int max_entries = ggtt_total_entries(ggtt) - first_entry;
>@@ -2569,8 +2359,7 @@
> 		 first_entry, num_entries, max_entries))
> 		num_entries = max_entries;
> 
>-	scratch_pte = vm->scratch_pte;
>-
>+	scratch_pte = vm->scratch[0].encode;
> 	for (i = 0; i < num_entries; i++)
> 		iowrite32(scratch_pte, &gtt_base[i]);
> }
>@@ -2657,18 +2446,18 @@
> 		pte_flags |= PTE_READ_ONLY;
> 
> 	if (flags & I915_VMA_LOCAL_BIND) {
>-		struct i915_ppgtt *appgtt = i915->mm.aliasing_ppgtt;
>+		struct i915_ppgtt *alias = i915_vm_to_ggtt(vma->vm)->alias;
> 
> 		if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
>-			ret = appgtt->vm.allocate_va_range(&appgtt->vm,
>-							   vma->node.start,
>-							   vma->size);
>+			ret = alias->vm.allocate_va_range(&alias->vm,
>+							  vma->node.start,
>+							  vma->size);
> 			if (ret)
> 				return ret;
> 		}
> 
>-		appgtt->vm.insert_entries(&appgtt->vm, vma, cache_level,
>-					  pte_flags);
>+		alias->vm.insert_entries(&alias->vm, vma,
>+					 cache_level, pte_flags);
> 	}
> 
> 	if (flags & I915_VMA_GLOBAL_BIND) {
>@@ -2696,7 +2485,8 @@
> 	}
> 
> 	if (vma->flags & I915_VMA_LOCAL_BIND) {
>-		struct i915_address_space *vm = &i915->mm.aliasing_ppgtt->vm;
>+		struct i915_address_space *vm =
>+			&i915_vm_to_ggtt(vma->vm)->alias->vm;
> 
> 		vm->clear_range(vm, vma->node.start, vma->size);
> 	}
>@@ -2753,13 +2543,12 @@
> 		*end -= I915_GTT_PAGE_SIZE;
> }
> 
>-static int init_aliasing_ppgtt(struct drm_i915_private *i915)
>+static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
> {
>-	struct i915_ggtt *ggtt = &i915->ggtt;
> 	struct i915_ppgtt *ppgtt;
> 	int err;
> 
>-	ppgtt = i915_ppgtt_create(i915);
>+	ppgtt = i915_ppgtt_create(ggtt->vm.i915);
> 	if (IS_ERR(ppgtt))
> 		return PTR_ERR(ppgtt);
> 
>@@ -2778,7 +2567,7 @@
> 	if (err)
> 		goto err_ppgtt;
> 
>-	i915->mm.aliasing_ppgtt = ppgtt;
>+	ggtt->alias = ppgtt;
> 
> 	GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != ggtt_bind_vma);
> 	ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma;
>@@ -2793,19 +2582,24 @@
> 	return err;
> }
> 
>-static void fini_aliasing_ppgtt(struct drm_i915_private *i915)
>+static void fini_aliasing_ppgtt(struct i915_ggtt *ggtt)
> {
>-	struct i915_ggtt *ggtt = &i915->ggtt;
>+	struct drm_i915_private *i915 = ggtt->vm.i915;
> 	struct i915_ppgtt *ppgtt;
> 
>-	ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt);
>+	mutex_lock(&i915->drm.struct_mutex);
>+
>+	ppgtt = fetch_and_zero(&ggtt->alias);
> 	if (!ppgtt)
>-		return;
>+		goto out;
> 
> 	i915_vm_put(&ppgtt->vm);
> 
> 	ggtt->vm.vma_ops.bind_vma   = ggtt_bind_vma;
> 	ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
>+
>+out:
>+	mutex_unlock(&i915->drm.struct_mutex);
> }
> 
> static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
>@@ -2834,7 +2628,13 @@
> 		drm_mm_remove_node(&ggtt->uc_fw);
> }
> 
>-int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
>+static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
>+{
>+	ggtt_release_guc_top(ggtt);
>+	drm_mm_remove_node(&ggtt->error_capture);
>+}
>+
>+static int init_ggtt(struct i915_ggtt *ggtt)
> {
> 	/* Let GEM Manage all of the aperture.
> 	 *
>@@ -2845,7 +2645,6 @@
> 	 * aperture.  One page should be enough to keep any prefetching inside
> 	 * of the aperture.
> 	 */
>-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
> 	unsigned long hole_start, hole_end;
> 	struct drm_mm_node *entry;
> 	int ret;
>@@ -2857,9 +2656,9 @@
> 	 * why.
> 	 */
> 	ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
>-			       intel_wopcm_guc_size(&dev_priv->wopcm));
>+			       intel_wopcm_guc_size(&ggtt->vm.i915->wopcm));
> 
>-	ret = intel_vgt_balloon(dev_priv);
>+	ret = intel_vgt_balloon(ggtt);
> 	if (ret)
> 		return ret;
> 
>@@ -2878,7 +2677,7 @@
> 	 */
> 	ret = ggtt_reserve_guc_top(ggtt);
> 	if (ret)
>-		goto err_reserve;
>+		goto err;
> 
> 	/* Clear any non-preallocated blocks */
> 	drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
>@@ -2891,35 +2690,41 @@
> 	/* And finally clear the reserved guard page */
> 	ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
> 
>-	if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
>-		ret = init_aliasing_ppgtt(dev_priv);
>+	return 0;
>+
>+err:
>+	cleanup_init_ggtt(ggtt);
>+	return ret;
>+}
>+
>+int i915_init_ggtt(struct drm_i915_private *i915)
>+{
>+	int ret;
>+
>+	ret = init_ggtt(&i915->ggtt);
>+	if (ret)
>+		return ret;
>+
>+	if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
>+		ret = init_aliasing_ppgtt(&i915->ggtt);
> 		if (ret)
>-			goto err_appgtt;
>+			cleanup_init_ggtt(&i915->ggtt);
> 	}
> 
> 	return 0;
>-
>-err_appgtt:
>-	ggtt_release_guc_top(ggtt);
>-err_reserve:
>-	drm_mm_remove_node(&ggtt->error_capture);
>-	return ret;
> }
> 
>-/**
>- * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
>- * @dev_priv: i915 device
>- */
>-void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
>+static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
> {
>-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
>+	struct drm_i915_private *i915 = ggtt->vm.i915;
> 	struct i915_vma *vma, *vn;
>-	struct pagevec *pvec;
> 
> 	ggtt->vm.closed = true;
> 
>-	mutex_lock(&dev_priv->drm.struct_mutex);
>-	fini_aliasing_ppgtt(dev_priv);
>+	rcu_barrier(); /* flush the RCU'ed__i915_vm_release */
>+	flush_workqueue(i915->wq);
>+
>+	mutex_lock(&i915->drm.struct_mutex);
> 
> 	list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link)
> 		WARN_ON(i915_vma_unbind(vma));
>@@ -2930,24 +2735,37 @@
> 	ggtt_release_guc_top(ggtt);
> 
> 	if (drm_mm_initialized(&ggtt->vm.mm)) {
>-		intel_vgt_deballoon(dev_priv);
>+		intel_vgt_deballoon(ggtt);
> 		i915_address_space_fini(&ggtt->vm);
> 	}
> 
> 	ggtt->vm.cleanup(&ggtt->vm);
> 
>-	pvec = &dev_priv->mm.wc_stash.pvec;
>+	mutex_unlock(&i915->drm.struct_mutex);
>+
>+	arch_phys_wc_del(ggtt->mtrr);
>+	io_mapping_fini(&ggtt->iomap);
>+}
>+
>+/**
>+ * i915_ggtt_driver_release - Clean up GGTT hardware initialization
>+ * @i915: i915 device
>+ */
>+void i915_ggtt_driver_release(struct drm_i915_private *i915)
>+{
>+	struct pagevec *pvec;
>+
>+	fini_aliasing_ppgtt(&i915->ggtt);
>+
>+	ggtt_cleanup_hw(&i915->ggtt);
>+
>+	pvec = &i915->mm.wc_stash.pvec;
> 	if (pvec->nr) {
> 		set_pages_array_wb(pvec->pages, pvec->nr);
> 		__pagevec_release(pvec);
> 	}
> 
>-	mutex_unlock(&dev_priv->drm.struct_mutex);
>-
>-	arch_phys_wc_del(ggtt->mtrr);
>-	io_mapping_fini(&ggtt->iomap);
>-
>-	i915_gem_cleanup_stolen(dev_priv);
>+	i915_gem_cleanup_stolen(i915);
> }
> 
> static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
>@@ -3018,243 +2836,48 @@
> 		return ret;
> 	}
> 
>-	ggtt->vm.scratch_pte =
>-		ggtt->vm.pte_encode(ggtt->vm.scratch_page.daddr,
>+	ggtt->vm.scratch[0].encode =
>+		ggtt->vm.pte_encode(px_dma(&ggtt->vm.scratch[0]),
> 				    I915_CACHE_NONE, 0);
> 
> 	return 0;
> }
> 
>-static struct intel_ppat_entry *
>-__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value)
>-{
>-	struct intel_ppat_entry *entry = &ppat->entries[index];
>-
>-	GEM_BUG_ON(index >= ppat->max_entries);
>-	GEM_BUG_ON(test_bit(index, ppat->used));
>-
>-	entry->ppat = ppat;
>-	entry->value = value;
>-	kref_init(&entry->ref);
>-	set_bit(index, ppat->used);
>-	set_bit(index, ppat->dirty);
>-
>-	return entry;
>-}
>-
>-static void __free_ppat_entry(struct intel_ppat_entry *entry)
>-{
>-	struct intel_ppat *ppat = entry->ppat;
>-	unsigned int index = entry - ppat->entries;
>-
>-	GEM_BUG_ON(index >= ppat->max_entries);
>-	GEM_BUG_ON(!test_bit(index, ppat->used));
>-
>-	entry->value = ppat->clear_value;
>-	clear_bit(index, ppat->used);
>-	set_bit(index, ppat->dirty);
>-}
>-
>-/**
>- * intel_ppat_get - get a usable PPAT entry
>- * @i915: i915 device instance
>- * @value: the PPAT value required by the caller
>- *
>- * The function tries to search if there is an existing PPAT entry which
>- * matches with the required value. If perfectly matched, the existing PPAT
>- * entry will be used. If only partially matched, it will try to check if
>- * there is any available PPAT index. If yes, it will allocate a new PPAT
>- * index for the required entry and update the HW. If not, the partially
>- * matched entry will be used.
>- */
>-const struct intel_ppat_entry *
>-intel_ppat_get(struct drm_i915_private *i915, u8 value)
>+static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
> {
>-	struct intel_ppat *ppat = &i915->ppat;
>-	struct intel_ppat_entry *entry = NULL;
>-	unsigned int scanned, best_score;
>-	int i;
>-
>-	GEM_BUG_ON(!ppat->max_entries);
>-
>-	scanned = best_score = 0;
>-	for_each_set_bit(i, ppat->used, ppat->max_entries) {
>-		unsigned int score;
>-
>-		score = ppat->match(ppat->entries[i].value, value);
>-		if (score > best_score) {
>-			entry = &ppat->entries[i];
>-			if (score == INTEL_PPAT_PERFECT_MATCH) {
>-				kref_get(&entry->ref);
>-				return entry;
>-			}
>-			best_score = score;
>-		}
>-		scanned++;
>-	}
>-
>-	if (scanned == ppat->max_entries) {
>-		if (!entry)
>-			return ERR_PTR(-ENOSPC);
>-
>-		kref_get(&entry->ref);
>-		return entry;
>-	}
>-
>-	i = find_first_zero_bit(ppat->used, ppat->max_entries);
>-	entry = __alloc_ppat_entry(ppat, i, value);
>-	ppat->update_hw(i915);
>-	return entry;
>+	I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
>+	I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
>+	I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
>+	I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
>+	I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
>+	I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
>+	I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
>+	I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
> }
> 
>-static void release_ppat(struct kref *kref)
>-{
>-	struct intel_ppat_entry *entry =
>-		container_of(kref, struct intel_ppat_entry, ref);
>-	struct drm_i915_private *i915 = entry->ppat->i915;
>-
>-	__free_ppat_entry(entry);
>-	entry->ppat->update_hw(i915);
>-}
>-
>-/**
>- * intel_ppat_put - put back the PPAT entry got from intel_ppat_get()
>- * @entry: an intel PPAT entry
>- *
>- * Put back the PPAT entry got from intel_ppat_get(). If the PPAT index of the
>- * entry is dynamically allocated, its reference count will be decreased. Once
>- * the reference count becomes into zero, the PPAT index becomes free again.
>- */
>-void intel_ppat_put(const struct intel_ppat_entry *entry)
>-{
>-	struct intel_ppat *ppat = entry->ppat;
>-	unsigned int index = entry - ppat->entries;
>-
>-	GEM_BUG_ON(!ppat->max_entries);
>-
>-	kref_put(&ppat->entries[index].ref, release_ppat);
>-}
>-
>-static void cnl_private_pat_update_hw(struct drm_i915_private *dev_priv)
>-{
>-	struct intel_ppat *ppat = &dev_priv->ppat;
>-	int i;
>-
>-	for_each_set_bit(i, ppat->dirty, ppat->max_entries) {
>-		I915_WRITE(GEN10_PAT_INDEX(i), ppat->entries[i].value);
>-		clear_bit(i, ppat->dirty);
>-	}
>-}
>-
>-static void bdw_private_pat_update_hw(struct drm_i915_private *dev_priv)
>+/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
>+ * bits. When using advanced contexts each context stores its own PAT, but
>+ * writing this data shouldn't be harmful even in those cases. */
>+static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
> {
>-	struct intel_ppat *ppat = &dev_priv->ppat;
>-	u64 pat = 0;
>-	int i;
>+	u64 pat;
> 
>-	for (i = 0; i < ppat->max_entries; i++)
>-		pat |= GEN8_PPAT(i, ppat->entries[i].value);
>-
>-	bitmap_clear(ppat->dirty, 0, ppat->max_entries);
>+	pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) |	/* for normal objects, no eLLC */
>+	      GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) |	/* for something pointing to ptes? */
>+	      GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) |	/* for scanout with eLLC */
>+	      GEN8_PPAT(3, GEN8_PPAT_UC) |			/* Uncached objects, mostly for scanout */
>+	      GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
>+	      GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
>+	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
>+	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
> 
> 	I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
> 	I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
> }
> 
>-static unsigned int bdw_private_pat_match(u8 src, u8 dst)
>-{
>-	unsigned int score = 0;
>-	enum {
>-		AGE_MATCH = BIT(0),
>-		TC_MATCH = BIT(1),
>-		CA_MATCH = BIT(2),
>-	};
>-
>-	/* Cache attribute has to be matched. */
>-	if (GEN8_PPAT_GET_CA(src) != GEN8_PPAT_GET_CA(dst))
>-		return 0;
>-
>-	score |= CA_MATCH;
>-
>-	if (GEN8_PPAT_GET_TC(src) == GEN8_PPAT_GET_TC(dst))
>-		score |= TC_MATCH;
>-
>-	if (GEN8_PPAT_GET_AGE(src) == GEN8_PPAT_GET_AGE(dst))
>-		score |= AGE_MATCH;
>-
>-	if (score == (AGE_MATCH | TC_MATCH | CA_MATCH))
>-		return INTEL_PPAT_PERFECT_MATCH;
>-
>-	return score;
>-}
>-
>-static unsigned int chv_private_pat_match(u8 src, u8 dst)
>-{
>-	return (CHV_PPAT_GET_SNOOP(src) == CHV_PPAT_GET_SNOOP(dst)) ?
>-		INTEL_PPAT_PERFECT_MATCH : 0;
>-}
>-
>-static void cnl_setup_private_ppat(struct intel_ppat *ppat)
>+static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
> {
>-	ppat->max_entries = 8;
>-	ppat->update_hw = cnl_private_pat_update_hw;
>-	ppat->match = bdw_private_pat_match;
>-	ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
>-
>-	__alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
>-	__alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
>-	__alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
>-	__alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);
>-	__alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
>-	__alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
>-	__alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
>-	__alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
>-}
>-
>-/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
>- * bits. When using advanced contexts each context stores its own PAT, but
>- * writing this data shouldn't be harmful even in those cases. */
>-static void bdw_setup_private_ppat(struct intel_ppat *ppat)
>-{
>-	ppat->max_entries = 8;
>-	ppat->update_hw = bdw_private_pat_update_hw;
>-	ppat->match = bdw_private_pat_match;
>-	ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
>-
>-	if (!HAS_PPGTT(ppat->i915)) {
>-		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
>-		 * so RTL will always use the value corresponding to
>-		 * pat_sel = 000".
>-		 * So let's disable cache for GGTT to avoid screen corruptions.
>-		 * MOCS still can be used though.
>-		 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
>-		 * before this patch, i.e. the same uncached + snooping access
>-		 * like on gen6/7 seems to be in effect.
>-		 * - So this just fixes blitter/render access. Again it looks
>-		 * like it's not just uncached access, but uncached + snooping.
>-		 * So we can still hold onto all our assumptions wrt cpu
>-		 * clflushing on LLC machines.
>-		 */
>-		__alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
>-		return;
>-	}
>-
>-	__alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);      /* for normal objects, no eLLC */
>-	__alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);  /* for something pointing to ptes? */
>-	__alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);  /* for scanout with eLLC */
>-	__alloc_ppat_entry(ppat, 3, GEN8_PPAT_UC);                      /* Uncached objects, mostly for scanout */
>-	__alloc_ppat_entry(ppat, 4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
>-	__alloc_ppat_entry(ppat, 5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
>-	__alloc_ppat_entry(ppat, 6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
>-	__alloc_ppat_entry(ppat, 7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
>-}
>-
>-static void chv_setup_private_ppat(struct intel_ppat *ppat)
>-{
>-	ppat->max_entries = 8;
>-	ppat->update_hw = bdw_private_pat_update_hw;
>-	ppat->match = chv_private_pat_match;
>-	ppat->clear_value = CHV_PPAT_SNOOP;
>+	u64 pat;
> 
> 	/*
> 	 * Map WB on BDW to snooped on CHV.
>@@ -3275,14 +2898,17 @@
> 	 * in order to keep the global status page working.
> 	 */
> 
>-	__alloc_ppat_entry(ppat, 0, CHV_PPAT_SNOOP);
>-	__alloc_ppat_entry(ppat, 1, 0);
>-	__alloc_ppat_entry(ppat, 2, 0);
>-	__alloc_ppat_entry(ppat, 3, 0);
>-	__alloc_ppat_entry(ppat, 4, CHV_PPAT_SNOOP);
>-	__alloc_ppat_entry(ppat, 5, CHV_PPAT_SNOOP);
>-	__alloc_ppat_entry(ppat, 6, CHV_PPAT_SNOOP);
>-	__alloc_ppat_entry(ppat, 7, CHV_PPAT_SNOOP);
>+	pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
>+	      GEN8_PPAT(1, 0) |
>+	      GEN8_PPAT(2, 0) |
>+	      GEN8_PPAT(3, 0) |
>+	      GEN8_PPAT(4, CHV_PPAT_SNOOP) |
>+	      GEN8_PPAT(5, CHV_PPAT_SNOOP) |
>+	      GEN8_PPAT(6, CHV_PPAT_SNOOP) |
>+	      GEN8_PPAT(7, CHV_PPAT_SNOOP);
>+
>+	I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));
>+	I915_WRITE(GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
> }
> 
> static void gen6_gmch_remove(struct i915_address_space *vm)
>@@ -3295,27 +2921,14 @@
> 
> static void setup_private_pat(struct drm_i915_private *dev_priv)
> {
>-	struct intel_ppat *ppat = &dev_priv->ppat;
>-	int i;
>-
>-	ppat->i915 = dev_priv;
>+	GEM_BUG_ON(INTEL_GEN(dev_priv) < 8);
> 
> 	if (INTEL_GEN(dev_priv) >= 10)
>-		cnl_setup_private_ppat(ppat);
>+		cnl_setup_private_ppat(dev_priv);
> 	else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
>-		chv_setup_private_ppat(ppat);
>+		chv_setup_private_ppat(dev_priv);
> 	else
>-		bdw_setup_private_ppat(ppat);
>-
>-	GEM_BUG_ON(ppat->max_entries > INTEL_MAX_PPAT_ENTRIES);
>-
>-	for_each_clear_bit(i, ppat->used, ppat->max_entries) {
>-		ppat->entries[i].value = ppat->clear_value;
>-		ppat->entries[i].ppat = ppat;
>-		set_bit(i, ppat->dirty);
>-	}
>-
>-	ppat->update_hw(dev_priv);
>+		bdw_setup_private_ppat(dev_priv);
> }
> 
> static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>@@ -3360,11 +2973,6 @@
> 		ggtt->vm.insert_page    = bxt_vtd_ggtt_insert_page__BKL;
> 		if (ggtt->vm.clear_range != nop_clear_range)
> 			ggtt->vm.clear_range = bxt_vtd_ggtt_clear_range__BKL;
>-
>-		/* Prevent recursively calling stop_machine() and deadlocks. */
>-		dev_info(dev_priv->drm.dev,
>-			 "Disabling error capture for VT-d workaround\n");
>-		i915_disable_error_state(dev_priv, -ENODEV);
> 	}
> 
> 	ggtt->invalidate = gen6_ggtt_invalidate;
>@@ -3482,21 +3090,18 @@
> 	return 0;
> }
> 
>-/**
>- * i915_ggtt_probe_hw - Probe GGTT hardware location
>- * @dev_priv: i915 device
>- */
>-int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
>+static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
> {
>-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
>+	struct drm_i915_private *i915 = gt->i915;
> 	int ret;
> 
>-	ggtt->vm.i915 = dev_priv;
>-	ggtt->vm.dma = &dev_priv->drm.pdev->dev;
>+	ggtt->vm.gt = gt;
>+	ggtt->vm.i915 = i915;
>+	ggtt->vm.dma = &i915->drm.pdev->dev;
> 
>-	if (INTEL_GEN(dev_priv) <= 5)
>+	if (INTEL_GEN(i915) <= 5)
> 		ret = i915_gmch_probe(ggtt);
>-	else if (INTEL_GEN(dev_priv) < 8)
>+	else if (INTEL_GEN(i915) < 8)
> 		ret = gen6_gmch_probe(ggtt);
> 	else
> 		ret = gen8_gmch_probe(ggtt);
>@@ -3524,51 +3129,82 @@
> 	DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20);
> 	DRM_DEBUG_DRIVER("DSM size = %lluM\n",
> 			 (u64)resource_size(&intel_graphics_stolen_res) >> 20);
>-	if (intel_vtd_active())
>-		DRM_INFO("VT-d active for gfx access\n");
> 
> 	return 0;
> }
> 
> /**
>- * i915_ggtt_init_hw - Initialize GGTT hardware
>- * @dev_priv: i915 device
>+ * i915_ggtt_probe_hw - Probe GGTT hardware location
>+ * @i915: i915 device
>  */
>-int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
>+int i915_ggtt_probe_hw(struct drm_i915_private *i915)
> {
>-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
> 	int ret;
> 
>-	stash_init(&dev_priv->mm.wc_stash);
>+	ret = ggtt_probe_hw(&i915->ggtt, &i915->gt);
>+	if (ret)
>+		return ret;
>+
>+	if (intel_vtd_active())
>+		DRM_INFO("VT-d active for gfx access\n");
>+
>+	return 0;
>+}
>+
>+static int ggtt_init_hw(struct i915_ggtt *ggtt)
>+{
>+	struct drm_i915_private *i915 = ggtt->vm.i915;
>+	int ret = 0;
>+
>+	mutex_lock(&i915->drm.struct_mutex);
> 
>-	/* Note that we use page colouring to enforce a guard page at the
>-	 * end of the address space. This is required as the CS may prefetch
>-	 * beyond the end of the batch buffer, across the page boundary,
>-	 * and beyond the end of the GTT if we do not provide a guard.
>-	 */
>-	mutex_lock(&dev_priv->drm.struct_mutex);
> 	i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
> 
> 	ggtt->vm.is_ggtt = true;
> 
> 	/* Only VLV supports read-only GGTT mappings */
>-	ggtt->vm.has_read_only = IS_VALLEYVIEW(dev_priv);
>+	ggtt->vm.has_read_only = IS_VALLEYVIEW(i915);
> 
>-	if (!HAS_LLC(dev_priv) && !HAS_PPGTT(dev_priv))
>+	if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
> 		ggtt->vm.mm.color_adjust = i915_gtt_color_adjust;
>-	mutex_unlock(&dev_priv->drm.struct_mutex);
> 
>-	if (!io_mapping_init_wc(&dev_priv->ggtt.iomap,
>-				dev_priv->ggtt.gmadr.start,
>-				dev_priv->ggtt.mappable_end)) {
>+	if (!io_mapping_init_wc(&ggtt->iomap,
>+				ggtt->gmadr.start,
>+				ggtt->mappable_end)) {
>+		ggtt->vm.cleanup(&ggtt->vm);
> 		ret = -EIO;
>-		goto out_gtt_cleanup;
>+		goto out;
> 	}
> 
> 	ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start, ggtt->mappable_end);
> 
> 	i915_ggtt_init_fences(ggtt);
> 
>+out:
>+	mutex_unlock(&i915->drm.struct_mutex);
>+
>+	return ret;
>+}
>+
>+/**
>+ * i915_ggtt_init_hw - Initialize GGTT hardware
>+ * @dev_priv: i915 device
>+ */
>+int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
>+{
>+	int ret;
>+
>+	stash_init(&dev_priv->mm.wc_stash);
>+
>+	/* Note that we use page colouring to enforce a guard page at the
>+	 * end of the address space. This is required as the CS may prefetch
>+	 * beyond the end of the batch buffer, across the page boundary,
>+	 * and beyond the end of the GTT if we do not provide a guard.
>+	 */
>+	ret = ggtt_init_hw(&dev_priv->ggtt);
>+	if (ret)
>+		return ret;
>+
> 	/*
> 	 * Initialise stolen early so that we may reserve preallocated
> 	 * objects for the BIOS to KMS transition.
>@@ -3580,7 +3216,7 @@
> 	return 0;
> 
> out_gtt_cleanup:
>-	ggtt->vm.cleanup(&ggtt->vm);
>+	dev_priv->ggtt.vm.cleanup(&dev_priv->ggtt.vm);
> 	return ret;
> }
> 
>@@ -3592,35 +3228,34 @@
> 	return 0;
> }
> 
>-void i915_ggtt_enable_guc(struct drm_i915_private *i915)
>+void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
> {
>-	GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
>+	GEM_BUG_ON(ggtt->invalidate != gen6_ggtt_invalidate);
> 
>-	i915->ggtt.invalidate = guc_ggtt_invalidate;
>+	ggtt->invalidate = guc_ggtt_invalidate;
> 
>-	i915_ggtt_invalidate(i915);
>+	ggtt->invalidate(ggtt);
> }
> 
>-void i915_ggtt_disable_guc(struct drm_i915_private *i915)
>+void i915_ggtt_disable_guc(struct i915_ggtt *ggtt)
> {
> 	/* XXX Temporary pardon for error unload */
>-	if (i915->ggtt.invalidate == gen6_ggtt_invalidate)
>+	if (ggtt->invalidate == gen6_ggtt_invalidate)
> 		return;
> 
> 	/* We should only be called after i915_ggtt_enable_guc() */
>-	GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
>+	GEM_BUG_ON(ggtt->invalidate != guc_ggtt_invalidate);
> 
>-	i915->ggtt.invalidate = gen6_ggtt_invalidate;
>+	ggtt->invalidate = gen6_ggtt_invalidate;
> 
>-	i915_ggtt_invalidate(i915);
>+	ggtt->invalidate(ggtt);
> }
> 
>-void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
>+static void ggtt_restore_mappings(struct i915_ggtt *ggtt)
> {
>-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
> 	struct i915_vma *vma, *vn;
> 
>-	i915_check_and_clear_faults(dev_priv);
>+	intel_gt_check_and_clear_faults(ggtt->vm.gt);
> 
> 	mutex_lock(&ggtt->vm.mutex);
> 
>@@ -3654,17 +3289,17 @@
> 	}
> 
> 	ggtt->vm.closed = false;
>-	i915_ggtt_invalidate(dev_priv);
>+	ggtt->invalidate(ggtt);
> 
> 	mutex_unlock(&ggtt->vm.mutex);
>+}
> 
>-	if (INTEL_GEN(dev_priv) >= 8) {
>-		struct intel_ppat *ppat = &dev_priv->ppat;
>+void i915_gem_restore_gtt_mappings(struct drm_i915_private *i915)
>+{
>+	ggtt_restore_mappings(&i915->ggtt);
> 
>-		bitmap_set(ppat->dirty, 0, ppat->max_entries);
>-		dev_priv->ppat.update_hw(dev_priv);
>-		return;
>-	}
>+	if (INTEL_GEN(i915) >= 8)
>+		setup_private_pat(i915);
> }
> 
> static struct scatterlist *
>@@ -3953,7 +3588,7 @@
> 	GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
> 	GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT));
> 	GEM_BUG_ON(range_overflows(offset, size, vm->total));
>-	GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->vm);
>+	GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
> 	GEM_BUG_ON(drm_mm_node_allocated(node));
> 
> 	node->size = size;
>@@ -4050,7 +3685,7 @@
> 	GEM_BUG_ON(start >= end);
> 	GEM_BUG_ON(start > 0  && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
> 	GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
>-	GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->vm);
>+	GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
> 	GEM_BUG_ON(drm_mm_node_allocated(node));
> 
> 	if (unlikely(range_overflows(start, size, end)))
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_gtt.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_gtt.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_gtt.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_gtt.h	2019-08-31 15:01:12.033736184 -0500
>@@ -35,15 +35,19 @@
> #define __I915_GEM_GTT_H__
> 
> #include <linux/io-mapping.h>
>+#include <linux/kref.h>
> #include <linux/mm.h>
> #include <linux/pagevec.h>
>+#include <linux/workqueue.h>
>+
>+#include <drm/drm_mm.h>
> 
> #include "gt/intel_reset.h"
> #include "i915_gem_fence_reg.h"
> #include "i915_request.h"
> #include "i915_scatterlist.h"
> #include "i915_selftest.h"
>-#include "i915_timeline.h"
>+#include "gt/intel_timeline.h"
> 
> #define I915_GTT_PAGE_SIZE_4K	BIT_ULL(12)
> #define I915_GTT_PAGE_SIZE_64K	BIT_ULL(16)
>@@ -64,12 +68,10 @@
> struct drm_i915_file_private;
> struct drm_i915_gem_object;
> struct i915_vma;
>+struct intel_gt;
> 
> typedef u32 gen6_pte_t;
> typedef u64 gen8_pte_t;
>-typedef u64 gen8_pde_t;
>-typedef u64 gen8_ppgtt_pdpe_t;
>-typedef u64 gen8_ppgtt_pml4e_t;
> 
> #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT)
> 
>@@ -113,30 +115,18 @@
> #define HSW_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0x7f0))
> #define HSW_PTE_ADDR_ENCODE(addr)	HSW_GTT_ADDR_ENCODE(addr)
> 
>-/* GEN8 32b style address is defined as a 3 level page table:
>+/*
>+ * GEN8 32b style address is defined as a 3 level page table:
>  * 31:30 | 29:21 | 20:12 |  11:0
>  * PDPE  |  PDE  |  PTE  | offset
>  * The difference as compared to normal x86 3 level page table is the PDPEs are
>  * programmed via register.
>- */
>-#define GEN8_3LVL_PDPES			4
>-#define GEN8_PDE_SHIFT			21
>-#define GEN8_PDE_MASK			0x1ff
>-#define GEN8_PTE_SHIFT			12
>-#define GEN8_PTE_MASK			0x1ff
>-#define GEN8_PTES			I915_PTES(sizeof(gen8_pte_t))
>-
>-/* GEN8 48b style address is defined as a 4 level page table:
>+ *
>+ * GEN8 48b style address is defined as a 4 level page table:
>  * 47:39 | 38:30 | 29:21 | 20:12 |  11:0
>  * PML4E | PDPE  |  PDE  |  PTE  | offset
>  */
>-#define GEN8_PML4ES_PER_PML4		512
>-#define GEN8_PML4E_SHIFT		39
>-#define GEN8_PML4E_MASK			(GEN8_PML4ES_PER_PML4 - 1)
>-#define GEN8_PDPE_SHIFT			30
>-/* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
>- * tables */
>-#define GEN8_PDPE_MASK			0x1ff
>+#define GEN8_3LVL_PDPES			4
> 
> #define PPAT_UNCACHED			(_PAGE_PWT | _PAGE_PCD)
> #define PPAT_CACHED_PDE			0 /* WB LLC */
>@@ -155,11 +145,6 @@
> #define GEN8_PPAT_ELLC_OVERRIDE		(0<<2)
> #define GEN8_PPAT(i, x)			((u64)(x) << ((i) * 8))
> 
>-#define GEN8_PPAT_GET_CA(x) ((x) & 3)
>-#define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2))
>-#define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))
>-#define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))
>-
> #define GEN8_PDE_IPS_64K BIT(11)
> #define GEN8_PDE_PS_2M   BIT(7)
> 
>@@ -243,8 +228,10 @@
> 	};
> };
> 
>-#define px_base(px) (&(px)->base)
>-#define px_dma(px) (px_base(px)->daddr)
>+struct i915_page_scratch {
>+	struct i915_page_dma base;
>+	u64 encode;
>+};
> 
> struct i915_page_table {
> 	struct i915_page_dma base;
>@@ -252,12 +239,32 @@
> };
> 
> struct i915_page_directory {
>-	struct i915_page_dma base;
>-	atomic_t used;
>+	struct i915_page_table pt;
> 	spinlock_t lock;
> 	void *entry[512];
> };
> 
>+#define __px_choose_expr(x, type, expr, other) \
>+	__builtin_choose_expr( \
>+	__builtin_types_compatible_p(typeof(x), type) || \
>+	__builtin_types_compatible_p(typeof(x), const type), \
>+	({ type __x = (type)(x); expr; }), \
>+	other)
>+
>+#define px_base(px) \
>+	__px_choose_expr(px, struct i915_page_dma *, __x, \
>+	__px_choose_expr(px, struct i915_page_scratch *, &__x->base, \
>+	__px_choose_expr(px, struct i915_page_table *, &__x->base, \
>+	__px_choose_expr(px, struct i915_page_directory *, &__x->pt.base, \
>+	(void)0))))
>+#define px_dma(px) (px_base(px)->daddr)
>+
>+#define px_pt(px) \
>+	__px_choose_expr(px, struct i915_page_table *, __x, \
>+	__px_choose_expr(px, struct i915_page_directory *, &__x->pt, \
>+	(void)0))
>+#define px_used(px) (&px_pt(px)->used)
>+
> struct i915_vma_ops {
> 	/* Map an object into an address space with the given cache flags. */
> 	int (*bind_vma)(struct i915_vma *vma,
>@@ -280,8 +287,10 @@
> 
> struct i915_address_space {
> 	struct kref ref;
>+	struct rcu_work rcu;
> 
> 	struct drm_mm mm;
>+	struct intel_gt *gt;
> 	struct drm_i915_private *i915;
> 	struct device *dma;
> 	/* Every address space belongs to a struct file - except for the global
>@@ -302,12 +311,9 @@
> #define VM_CLASS_GGTT 0
> #define VM_CLASS_PPGTT 1
> 
>-	u64 scratch_pte;
>-	int scratch_order;
>-	struct i915_page_dma scratch_page;
>-	struct i915_page_table *scratch_pt;
>-	struct i915_page_directory *scratch_pd;
>-	struct i915_page_directory *scratch_pdp; /* GEN8+ & 48b PPGTT */
>+	struct i915_page_scratch scratch[4];
>+	unsigned int scratch_order;
>+	unsigned int top;
> 
> 	/**
> 	 * List of vma currently bound.
>@@ -386,7 +392,10 @@
> 
> 	/** "Graphics Stolen Memory" holds the global PTEs */
> 	void __iomem *gsm;
>-	void (*invalidate)(struct drm_i915_private *dev_priv);
>+	void (*invalidate)(struct i915_ggtt *ggtt);
>+
>+	/** PPGTT used for aliasing the PPGTT with the GTT */
>+	struct i915_ppgtt *alias;
> 
> 	bool do_idle_maps;
> 
>@@ -425,8 +434,6 @@
> 
> 	unsigned int pin_count;
> 	bool scan_for_unused_pt;
>-
>-	struct gen6_ppgtt_cleanup_work *work;
> };
> 
> #define __to_gen6_ppgtt(base) container_of(base, struct gen6_ppgtt, base)
>@@ -506,15 +513,6 @@
> 	return i915_pde_index(addr, GEN6_PDE_SHIFT);
> }
> 
>-static inline unsigned int
>-i915_pdpes_per_pdp(const struct i915_address_space *vm)
>-{
>-	if (i915_vm_is_4lvl(vm))
>-		return GEN8_PML4ES_PER_PML4;
>-
>-	return GEN8_3LVL_PDPES;
>-}
>-
> static inline struct i915_page_table *
> i915_pt_entry(const struct i915_page_directory * const pd,
> 	      const unsigned short n)
>@@ -529,73 +527,12 @@
> 	return pdp->entry[n];
> }
> 
>-static inline struct i915_page_directory *
>-i915_pdp_entry(const struct i915_page_directory * const pml4,
>-	       const unsigned short n)
>-{
>-	return pml4->entry[n];
>-}
>-
>-/* Equivalent to the gen6 version, For each pde iterates over every pde
>- * between from start until start + length. On gen8+ it simply iterates
>- * over every page directory entry in a page directory.
>- */
>-#define gen8_for_each_pde(pt, pd, start, length, iter)			\
>-	for (iter = gen8_pde_index(start);				\
>-	     length > 0 && iter < I915_PDES &&				\
>-		     (pt = i915_pt_entry(pd, iter), true);		\
>-	     ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT);		\
>-		    temp = min(temp - start, length);			\
>-		    start += temp, length -= temp; }), ++iter)
>-
>-#define gen8_for_each_pdpe(pd, pdp, start, length, iter)		\
>-	for (iter = gen8_pdpe_index(start);				\
>-	     length > 0 && iter < i915_pdpes_per_pdp(vm) &&		\
>-		     (pd = i915_pd_entry(pdp, iter), true);		\
>-	     ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT);	\
>-		    temp = min(temp - start, length);			\
>-		    start += temp, length -= temp; }), ++iter)
>-
>-#define gen8_for_each_pml4e(pdp, pml4, start, length, iter)		\
>-	for (iter = gen8_pml4e_index(start);				\
>-	     length > 0 && iter < GEN8_PML4ES_PER_PML4 &&		\
>-		     (pdp = i915_pdp_entry(pml4, iter), true);		\
>-	     ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT);	\
>-		    temp = min(temp - start, length);			\
>-		    start += temp, length -= temp; }), ++iter)
>-
>-static inline u32 gen8_pte_index(u64 address)
>-{
>-	return i915_pte_index(address, GEN8_PDE_SHIFT);
>-}
>-
>-static inline u32 gen8_pde_index(u64 address)
>-{
>-	return i915_pde_index(address, GEN8_PDE_SHIFT);
>-}
>-
>-static inline u32 gen8_pdpe_index(u64 address)
>-{
>-	return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
>-}
>-
>-static inline u32 gen8_pml4e_index(u64 address)
>-{
>-	return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK;
>-}
>-
>-static inline u64 gen8_pte_count(u64 address, u64 length)
>-{
>-	return i915_pte_count(address, length, GEN8_PDE_SHIFT);
>-}
>-
> static inline dma_addr_t
> i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
> {
>-	struct i915_page_directory *pd;
>+	struct i915_page_dma *pt = ppgtt->pd->entry[n];
> 
>-	pd = i915_pdp_entry(ppgtt->pd, n);
>-	return px_dma(pd);
>+	return px_dma(pt ?: px_base(&ppgtt->vm.scratch[ppgtt->vm.top]));
> }
> 
> static inline struct i915_ggtt *
>@@ -614,46 +551,15 @@
> 	return container_of(vm, struct i915_ppgtt, vm);
> }
> 
>-#define INTEL_MAX_PPAT_ENTRIES 8
>-#define INTEL_PPAT_PERFECT_MATCH (~0U)
>-
>-struct intel_ppat;
>-
>-struct intel_ppat_entry {
>-	struct intel_ppat *ppat;
>-	struct kref ref;
>-	u8 value;
>-};
>-
>-struct intel_ppat {
>-	struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES];
>-	DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES);
>-	DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES);
>-	unsigned int max_entries;
>-	u8 clear_value;
>-	/*
>-	 * Return a score to show how two PPAT values match,
>-	 * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match
>-	 */
>-	unsigned int (*match)(u8 src, u8 dst);
>-	void (*update_hw)(struct drm_i915_private *i915);
>-
>-	struct drm_i915_private *i915;
>-};
>-
>-const struct intel_ppat_entry *
>-intel_ppat_get(struct drm_i915_private *i915, u8 value);
>-void intel_ppat_put(const struct intel_ppat_entry *entry);
>-
> int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
> int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
> int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
>-void i915_ggtt_enable_guc(struct drm_i915_private *i915);
>-void i915_ggtt_disable_guc(struct drm_i915_private *i915);
>-int i915_gem_init_ggtt(struct drm_i915_private *dev_priv);
>-void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
>+void i915_ggtt_enable_guc(struct i915_ggtt *ggtt);
>+void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
>+int i915_init_ggtt(struct drm_i915_private *dev_priv);
>+void i915_ggtt_driver_release(struct drm_i915_private *dev_priv);
> 
>-int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv);
>+int i915_ppgtt_init_hw(struct intel_gt *gt);
> 
> struct i915_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_render_state.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_render_state.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_render_state.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_render_state.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,235 +0,0 @@
>-/*
>- * Copyright Â© 2014 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- * Authors:
>- *    Mika Kuoppala <mika.kuoppala@intel.com>
>- *
>- */
>-
>-#include "i915_drv.h"
>-#include "i915_gem_render_state.h"
>-#include "intel_renderstate.h"
>-
>-struct intel_render_state {
>-	const struct intel_renderstate_rodata *rodata;
>-	struct drm_i915_gem_object *obj;
>-	struct i915_vma *vma;
>-	u32 batch_offset;
>-	u32 batch_size;
>-	u32 aux_offset;
>-	u32 aux_size;
>-};
>-
>-static const struct intel_renderstate_rodata *
>-render_state_get_rodata(const struct intel_engine_cs *engine)
>-{
>-	if (engine->id != RCS0)
>-		return NULL;
>-
>-	switch (INTEL_GEN(engine->i915)) {
>-	case 6:
>-		return &gen6_null_state;
>-	case 7:
>-		return &gen7_null_state;
>-	case 8:
>-		return &gen8_null_state;
>-	case 9:
>-		return &gen9_null_state;
>-	}
>-
>-	return NULL;
>-}
>-
>-/*
>- * Macro to add commands to auxiliary batch.
>- * This macro only checks for page overflow before inserting the commands,
>- * this is sufficient as the null state generator makes the final batch
>- * with two passes to build command and state separately. At this point
>- * the size of both are known and it compacts them by relocating the state
>- * right after the commands taking care of alignment so we should sufficient
>- * space below them for adding new commands.
>- */
>-#define OUT_BATCH(batch, i, val)				\
>-	do {							\
>-		if ((i) >= PAGE_SIZE / sizeof(u32))		\
>-			goto err;				\
>-		(batch)[(i)++] = (val);				\
>-	} while(0)
>-
>-static int render_state_setup(struct intel_render_state *so,
>-			      struct drm_i915_private *i915)
>-{
>-	const struct intel_renderstate_rodata *rodata = so->rodata;
>-	unsigned int i = 0, reloc_index = 0;
>-	unsigned int needs_clflush;
>-	u32 *d;
>-	int ret;
>-
>-	ret = i915_gem_object_prepare_write(so->obj, &needs_clflush);
>-	if (ret)
>-		return ret;
>-
>-	d = kmap_atomic(i915_gem_object_get_dirty_page(so->obj, 0));
>-
>-	while (i < rodata->batch_items) {
>-		u32 s = rodata->batch[i];
>-
>-		if (i * 4  == rodata->reloc[reloc_index]) {
>-			u64 r = s + so->vma->node.start;
>-			s = lower_32_bits(r);
>-			if (HAS_64BIT_RELOC(i915)) {
>-				if (i + 1 >= rodata->batch_items ||
>-				    rodata->batch[i + 1] != 0)
>-					goto err;
>-
>-				d[i++] = s;
>-				s = upper_32_bits(r);
>-			}
>-
>-			reloc_index++;
>-		}
>-
>-		d[i++] = s;
>-	}
>-
>-	if (rodata->reloc[reloc_index] != -1) {
>-		DRM_ERROR("only %d relocs resolved\n", reloc_index);
>-		goto err;
>-	}
>-
>-	so->batch_offset = i915_ggtt_offset(so->vma);
>-	so->batch_size = rodata->batch_items * sizeof(u32);
>-
>-	while (i % CACHELINE_DWORDS)
>-		OUT_BATCH(d, i, MI_NOOP);
>-
>-	so->aux_offset = i * sizeof(u32);
>-
>-	if (HAS_POOLED_EU(i915)) {
>-		/*
>-		 * We always program 3x6 pool config but depending upon which
>-		 * subslice is disabled HW drops down to appropriate config
>-		 * shown below.
>-		 *
>-		 * In the below table 2x6 config always refers to
>-		 * fused-down version, native 2x6 is not available and can
>-		 * be ignored
>-		 *
>-		 * SNo  subslices config                eu pool configuration
>-		 * -----------------------------------------------------------
>-		 * 1    3 subslices enabled (3x6)  -    0x00777000  (9+9)
>-		 * 2    ss0 disabled (2x6)         -    0x00777000  (3+9)
>-		 * 3    ss1 disabled (2x6)         -    0x00770000  (6+6)
>-		 * 4    ss2 disabled (2x6)         -    0x00007000  (9+3)
>-		 */
>-		u32 eu_pool_config = 0x00777000;
>-
>-		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
>-		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
>-		OUT_BATCH(d, i, eu_pool_config);
>-		OUT_BATCH(d, i, 0);
>-		OUT_BATCH(d, i, 0);
>-		OUT_BATCH(d, i, 0);
>-	}
>-
>-	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
>-	so->aux_size = i * sizeof(u32) - so->aux_offset;
>-	so->aux_offset += so->batch_offset;
>-	/*
>-	 * Since we are sending length, we need to strictly conform to
>-	 * all requirements. For Gen2 this must be a multiple of 8.
>-	 */
>-	so->aux_size = ALIGN(so->aux_size, 8);
>-
>-	if (needs_clflush)
>-		drm_clflush_virt_range(d, i * sizeof(u32));
>-	kunmap_atomic(d);
>-
>-	ret = 0;
>-out:
>-	i915_gem_object_finish_access(so->obj);
>-	return ret;
>-
>-err:
>-	kunmap_atomic(d);
>-	ret = -EINVAL;
>-	goto out;
>-}
>-
>-#undef OUT_BATCH
>-
>-int i915_gem_render_state_emit(struct i915_request *rq)
>-{
>-	struct intel_engine_cs *engine = rq->engine;
>-	struct intel_render_state so = {}; /* keep the compiler happy */
>-	int err;
>-
>-	so.rodata = render_state_get_rodata(engine);
>-	if (!so.rodata)
>-		return 0;
>-
>-	if (so.rodata->batch_items * 4 > PAGE_SIZE)
>-		return -EINVAL;
>-
>-	so.obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
>-	if (IS_ERR(so.obj))
>-		return PTR_ERR(so.obj);
>-
>-	so.vma = i915_vma_instance(so.obj, &engine->i915->ggtt.vm, NULL);
>-	if (IS_ERR(so.vma)) {
>-		err = PTR_ERR(so.vma);
>-		goto err_obj;
>-	}
>-
>-	err = i915_vma_pin(so.vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
>-	if (err)
>-		goto err_vma;
>-
>-	err = render_state_setup(&so, rq->i915);
>-	if (err)
>-		goto err_unpin;
>-
>-	err = engine->emit_bb_start(rq,
>-				    so.batch_offset, so.batch_size,
>-				    I915_DISPATCH_SECURE);
>-	if (err)
>-		goto err_unpin;
>-
>-	if (so.aux_size > 8) {
>-		err = engine->emit_bb_start(rq,
>-					    so.aux_offset, so.aux_size,
>-					    I915_DISPATCH_SECURE);
>-		if (err)
>-			goto err_unpin;
>-	}
>-
>-	i915_vma_lock(so.vma);
>-	err = i915_vma_move_to_active(so.vma, rq, 0);
>-	i915_vma_unlock(so.vma);
>-err_unpin:
>-	i915_vma_unpin(so.vma);
>-err_vma:
>-	i915_vma_close(so.vma);
>-err_obj:
>-	i915_gem_object_put(so.obj);
>-	return err;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_render_state.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_render_state.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_gem_render_state.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gem_render_state.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,31 +0,0 @@
>-/*
>- * Copyright Â© 2014 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>- * DEALINGS IN THE SOFTWARE.
>- */
>-
>-#ifndef _I915_GEM_RENDER_STATE_H_
>-#define _I915_GEM_RENDER_STATE_H_
>-
>-struct i915_request;
>-
>-int i915_gem_render_state_emit(struct i915_request *rq);
>-
>-#endif /* _I915_GEM_RENDER_STATE_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_globals.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_globals.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_globals.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_globals.h	2019-08-31 15:01:12.033736184 -0500
>@@ -7,6 +7,8 @@
> #ifndef _I915_GLOBALS_H_
> #define _I915_GLOBALS_H_
> 
>+#include <linux/types.h>
>+
> typedef void (*i915_global_func_t)(void);
> 
> struct i915_global {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_gpu_error.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gpu_error.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_gpu_error.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gpu_error.c	2019-08-31 15:01:12.033736184 -0500
>@@ -29,8 +29,8 @@
> 
> #include <linux/ascii85.h>
> #include <linux/nmi.h>
>+#include <linux/pagevec.h>
> #include <linux/scatterlist.h>
>-#include <linux/stop_machine.h>
> #include <linux/utsname.h>
> #include <linux/zlib.h>
> 
>@@ -46,6 +46,9 @@
> #include "i915_scatterlist.h"
> #include "intel_csr.h"
> 
>+#define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
>+#define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
>+
> static inline const struct intel_engine_cs *
> engine_lookup(const struct drm_i915_private *i915, unsigned int id)
> {
>@@ -67,26 +70,6 @@
> 	return __engine_name(engine_lookup(i915, id));
> }
> 
>-static const char *tiling_flag(int tiling)
>-{
>-	switch (tiling) {
>-	default:
>-	case I915_TILING_NONE: return "";
>-	case I915_TILING_X: return " X";
>-	case I915_TILING_Y: return " Y";
>-	}
>-}
>-
>-static const char *dirty_flag(int dirty)
>-{
>-	return dirty ? " dirty" : "";
>-}
>-
>-static const char *purgeable_flag(int purgeable)
>-{
>-	return purgeable ? " purgeable" : "";
>-}
>-
> static void __sg_set_buf(struct scatterlist *sg,
> 			 void *addr, unsigned int len, loff_t it)
> {
>@@ -114,7 +97,7 @@
> 	if (e->cur == e->end) {
> 		struct scatterlist *sgl;
> 
>-		sgl = (typeof(sgl))__get_free_page(GFP_KERNEL);
>+		sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
> 		if (!sgl) {
> 			e->err = -ENOMEM;
> 			return false;
>@@ -134,7 +117,7 @@
> 	}
> 
> 	e->size = ALIGN(len + 1, SZ_64K);
>-	e->buf = kmalloc(e->size, GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
>+	e->buf = kmalloc(e->size, ALLOW_FAIL);
> 	if (!e->buf) {
> 		e->size = PAGE_ALIGN(len + 1);
> 		e->buf = kmalloc(e->size, GFP_KERNEL);
>@@ -211,47 +194,115 @@
> 	return p;
> }
> 
>+/* single threaded page allocator with a reserved stash for emergencies */
>+static void pool_fini(struct pagevec *pv)
>+{
>+	pagevec_release(pv);
>+}
>+
>+static int pool_refill(struct pagevec *pv, gfp_t gfp)
>+{
>+	while (pagevec_space(pv)) {
>+		struct page *p;
>+
>+		p = alloc_page(gfp);
>+		if (!p)
>+			return -ENOMEM;
>+
>+		pagevec_add(pv, p);
>+	}
>+
>+	return 0;
>+}
>+
>+static int pool_init(struct pagevec *pv, gfp_t gfp)
>+{
>+	int err;
>+
>+	pagevec_init(pv);
>+
>+	err = pool_refill(pv, gfp);
>+	if (err)
>+		pool_fini(pv);
>+
>+	return err;
>+}
>+
>+static void *pool_alloc(struct pagevec *pv, gfp_t gfp)
>+{
>+	struct page *p;
>+
>+	p = alloc_page(gfp);
>+	if (!p && pagevec_count(pv))
>+		p = pv->pages[--pv->nr];
>+
>+	return p ? page_address(p) : NULL;
>+}
>+
>+static void pool_free(struct pagevec *pv, void *addr)
>+{
>+	struct page *p = virt_to_page(addr);
>+
>+	if (pagevec_space(pv))
>+		pagevec_add(pv, p);
>+	else
>+		__free_page(p);
>+}
>+
> #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
> 
> struct compress {
>+	struct pagevec pool;
> 	struct z_stream_s zstream;
> 	void *tmp;
> };
> 
> static bool compress_init(struct compress *c)
> {
>-	struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream));
>+	struct z_stream_s *zstream = &c->zstream;
> 
>-	zstream->workspace =
>-		kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
>-			GFP_ATOMIC | __GFP_NOWARN);
>-	if (!zstream->workspace)
>+	if (pool_init(&c->pool, ALLOW_FAIL))
> 		return false;
> 
>-	if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
>-		kfree(zstream->workspace);
>+	zstream->workspace =
>+		kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
>+			ALLOW_FAIL);
>+	if (!zstream->workspace) {
>+		pool_fini(&c->pool);
> 		return false;
> 	}
> 
> 	c->tmp = NULL;
> 	if (i915_has_memcpy_from_wc())
>-		c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
>+		c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
> 
> 	return true;
> }
> 
>-static void *compress_next_page(struct drm_i915_error_object *dst)
>+static bool compress_start(struct compress *c)
>+{
>+	struct z_stream_s *zstream = &c->zstream;
>+	void *workspace = zstream->workspace;
>+
>+	memset(zstream, 0, sizeof(*zstream));
>+	zstream->workspace = workspace;
>+
>+	return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;
>+}
>+
>+static void *compress_next_page(struct compress *c,
>+				struct drm_i915_error_object *dst)
> {
>-	unsigned long page;
>+	void *page;
> 
> 	if (dst->page_count >= dst->num_pages)
> 		return ERR_PTR(-ENOSPC);
> 
>-	page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
>+	page = pool_alloc(&c->pool, ALLOW_FAIL);
> 	if (!page)
> 		return ERR_PTR(-ENOMEM);
> 
>-	return dst->pages[dst->page_count++] = (void *)page;
>+	return dst->pages[dst->page_count++] = page;
> }
> 
> static int compress_page(struct compress *c,
>@@ -267,7 +318,7 @@
> 
> 	do {
> 		if (zstream->avail_out == 0) {
>-			zstream->next_out = compress_next_page(dst);
>+			zstream->next_out = compress_next_page(c, dst);
> 			if (IS_ERR(zstream->next_out))
> 				return PTR_ERR(zstream->next_out);
> 
>@@ -276,8 +327,6 @@
> 
> 		if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
> 			return -EIO;
>-
>-		touch_nmi_watchdog();
> 	} while (zstream->avail_in);
> 
> 	/* Fallback to uncompressed if we increase size? */
>@@ -295,7 +344,7 @@
> 	do {
> 		switch (zlib_deflate(zstream, Z_FINISH)) {
> 		case Z_OK: /* more space requested */
>-			zstream->next_out = compress_next_page(dst);
>+			zstream->next_out = compress_next_page(c, dst);
> 			if (IS_ERR(zstream->next_out))
> 				return PTR_ERR(zstream->next_out);
> 
>@@ -316,15 +365,17 @@
> 	return 0;
> }
> 
>-static void compress_fini(struct compress *c,
>-			  struct drm_i915_error_object *dst)
>+static void compress_finish(struct compress *c)
> {
>-	struct z_stream_s *zstream = &c->zstream;
>+	zlib_deflateEnd(&c->zstream);
>+}
> 
>-	zlib_deflateEnd(zstream);
>-	kfree(zstream->workspace);
>+static void compress_fini(struct compress *c)
>+{
>+	kfree(c->zstream.workspace);
> 	if (c->tmp)
>-		free_page((unsigned long)c->tmp);
>+		pool_free(&c->pool, c->tmp);
>+	pool_fini(&c->pool);
> }
> 
> static void err_compression_marker(struct drm_i915_error_state_buf *m)
>@@ -335,10 +386,16 @@
> #else
> 
> struct compress {
>+	struct pagevec pool;
> };
> 
> static bool compress_init(struct compress *c)
> {
>+	return pool_init(&c->pool, ALLOW_FAIL) == 0;
>+}
>+
>+static bool compress_start(struct compress *c)
>+{
> 	return true;
> }
> 
>@@ -346,14 +403,12 @@
> 			 void *src,
> 			 struct drm_i915_error_object *dst)
> {
>-	unsigned long page;
> 	void *ptr;
> 
>-	page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
>-	if (!page)
>+	ptr = pool_alloc(&c->pool, ALLOW_FAIL);
>+	if (!ptr)
> 		return -ENOMEM;
> 
>-	ptr = (void *)page;
> 	if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
> 		memcpy(ptr, src, PAGE_SIZE);
> 	dst->pages[dst->page_count++] = ptr;
>@@ -367,11 +422,15 @@
> 	return 0;
> }
> 
>-static void compress_fini(struct compress *c,
>-			  struct drm_i915_error_object *dst)
>+static void compress_finish(struct compress *c)
> {
> }
> 
>+static void compress_fini(struct compress *c)
>+{
>+	pool_fini(&c->pool);
>+}
>+
> static void err_compression_marker(struct drm_i915_error_state_buf *m)
> {
> 	err_puts(m, "~");
>@@ -379,36 +438,6 @@
> 
> #endif
> 
>-static void print_error_buffers(struct drm_i915_error_state_buf *m,
>-				const char *name,
>-				struct drm_i915_error_buffer *err,
>-				int count)
>-{
>-	err_printf(m, "%s [%d]:\n", name, count);
>-
>-	while (count--) {
>-		err_printf(m, "    %08x_%08x %8u %02x %02x",
>-			   upper_32_bits(err->gtt_offset),
>-			   lower_32_bits(err->gtt_offset),
>-			   err->size,
>-			   err->read_domains,
>-			   err->write_domain);
>-		err_puts(m, tiling_flag(err->tiling));
>-		err_puts(m, dirty_flag(err->dirty));
>-		err_puts(m, purgeable_flag(err->purgeable));
>-		err_puts(m, err->userptr ? " userptr" : "");
>-		err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
>-
>-		if (err->name)
>-			err_printf(m, " (name: %d)", err->name);
>-		if (err->fence_reg != I915_FENCE_REG_NONE)
>-			err_printf(m, " (fence: %d)", err->fence_reg);
>-
>-		err_puts(m, "\n");
>-		err++;
>-	}
>-}
>-
> static void error_print_instdone(struct drm_i915_error_state_buf *m,
> 				 const struct drm_i915_error_engine *ee)
> {
>@@ -620,7 +649,7 @@
> 	const struct i915_gpu_state *error =
> 		container_of(error_uc, typeof(*error), uc);
> 
>-	if (!error->device_info.has_guc)
>+	if (!error->device_info.has_gt_uc)
> 		return;
> 
> 	intel_uc_fw_dump(&error_uc->guc_fw, &p);
>@@ -734,33 +763,6 @@
> 			error_print_engine(m, &error->engine[i], error->epoch);
> 	}
> 
>-	for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
>-		char buf[128];
>-		int len, first = 1;
>-
>-		if (!error->active_vm[i])
>-			break;
>-
>-		len = scnprintf(buf, sizeof(buf), "Active (");
>-		for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
>-			if (error->engine[j].vm != error->active_vm[i])
>-				continue;
>-
>-			len += scnprintf(buf + len, sizeof(buf), "%s%s",
>-					 first ? "" : ", ",
>-					 m->i915->engine[j]->name);
>-			first = 0;
>-		}
>-		scnprintf(buf + len, sizeof(buf), ")");
>-		print_error_buffers(m, buf,
>-				    error->active_bo[i],
>-				    error->active_bo_count[i]);
>-	}
>-
>-	print_error_buffers(m, "Pinned (global)",
>-			    error->pinned_bo,
>-			    error->pinned_bo_count);
>-
> 	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
> 		const struct drm_i915_error_engine *ee = &error->engine[i];
> 
>@@ -974,10 +976,6 @@
> 		kfree(ee->requests);
> 	}
> 
>-	for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
>-		kfree(error->active_bo[i]);
>-	kfree(error->pinned_bo);
>-
> 	kfree(error->overlay);
> 	kfree(error->display);
> 
>@@ -990,108 +988,63 @@
> 
> static struct drm_i915_error_object *
> i915_error_object_create(struct drm_i915_private *i915,
>-			 struct i915_vma *vma)
>+			 struct i915_vma *vma,
>+			 struct compress *compress)
> {
> 	struct i915_ggtt *ggtt = &i915->ggtt;
> 	const u64 slot = ggtt->error_capture.start;
> 	struct drm_i915_error_object *dst;
>-	struct compress compress;
> 	unsigned long num_pages;
> 	struct sgt_iter iter;
> 	dma_addr_t dma;
> 	int ret;
> 
>+	might_sleep();
>+
> 	if (!vma || !vma->pages)
> 		return NULL;
> 
> 	num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
> 	num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
>-	dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
>-		      GFP_ATOMIC | __GFP_NOWARN);
>+	dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL);
> 	if (!dst)
> 		return NULL;
> 
>+	if (!compress_start(compress)) {
>+		kfree(dst);
>+		return NULL;
>+	}
>+
> 	dst->gtt_offset = vma->node.start;
> 	dst->gtt_size = vma->node.size;
> 	dst->num_pages = num_pages;
> 	dst->page_count = 0;
> 	dst->unused = 0;
> 
>-	if (!compress_init(&compress)) {
>-		kfree(dst);
>-		return NULL;
>-	}
>-
> 	ret = -EINVAL;
> 	for_each_sgt_dma(dma, iter, vma->pages) {
> 		void __iomem *s;
> 
> 		ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
> 
>-		s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
>-		ret = compress_page(&compress, (void  __force *)s, dst);
>-		io_mapping_unmap_atomic(s);
>+		s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
>+		ret = compress_page(compress, (void  __force *)s, dst);
>+		io_mapping_unmap(s);
> 		if (ret)
> 			break;
> 	}
> 
>-	if (ret || compress_flush(&compress, dst)) {
>+	if (ret || compress_flush(compress, dst)) {
> 		while (dst->page_count--)
>-			free_page((unsigned long)dst->pages[dst->page_count]);
>+			pool_free(&compress->pool, dst->pages[dst->page_count]);
> 		kfree(dst);
> 		dst = NULL;
> 	}
>+	compress_finish(compress);
> 
>-	compress_fini(&compress, dst);
> 	return dst;
> }
> 
>-static void capture_bo(struct drm_i915_error_buffer *err,
>-		       struct i915_vma *vma)
>-{
>-	struct drm_i915_gem_object *obj = vma->obj;
>-
>-	err->size = obj->base.size;
>-	err->name = obj->base.name;
>-
>-	err->gtt_offset = vma->node.start;
>-	err->read_domains = obj->read_domains;
>-	err->write_domain = obj->write_domain;
>-	err->fence_reg = vma->fence ? vma->fence->id : -1;
>-	err->tiling = i915_gem_object_get_tiling(obj);
>-	err->dirty = obj->mm.dirty;
>-	err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
>-	err->userptr = obj->userptr.mm != NULL;
>-	err->cache_level = obj->cache_level;
>-}
>-
>-static u32 capture_error_bo(struct drm_i915_error_buffer *err,
>-			    int count, struct list_head *head,
>-			    unsigned int flags)
>-#define ACTIVE_ONLY BIT(0)
>-#define PINNED_ONLY BIT(1)
>-{
>-	struct i915_vma *vma;
>-	int i = 0;
>-
>-	list_for_each_entry(vma, head, vm_link) {
>-		if (!vma->obj)
>-			continue;
>-
>-		if (flags & ACTIVE_ONLY && !i915_vma_is_active(vma))
>-			continue;
>-
>-		if (flags & PINNED_ONLY && !i915_vma_is_pinned(vma))
>-			continue;
>-
>-		capture_bo(err++, vma);
>-		if (++i == count)
>-			break;
>-	}
>-
>-	return i;
>-}
>-
> /*
>  * Generate a semi-unique error code. The code is not meant to have meaning, The
>  * code's only purpose is to try to prevent false duplicated bug reports by
>@@ -1249,10 +1202,10 @@
> 	}
> }
> 
>-static void record_request(struct i915_request *request,
>+static void record_request(const struct i915_request *request,
> 			   struct drm_i915_error_request *erq)
> {
>-	struct i915_gem_context *ctx = request->gem_context;
>+	const struct i915_gem_context *ctx = request->gem_context;
> 
> 	erq->flags = request->fence.flags;
> 	erq->context = request->fence.context;
>@@ -1282,7 +1235,7 @@
> 	if (!count)
> 		return;
> 
>-	ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
>+	ee->requests = kcalloc(count, sizeof(*ee->requests), ATOMIC_MAYFAIL);
> 	if (!ee->requests)
> 		return;
> 
>@@ -1316,20 +1269,15 @@
> 	ee->num_requests = count;
> }
> 
>-static void error_record_engine_execlists(struct intel_engine_cs *engine,
>+static void error_record_engine_execlists(const struct intel_engine_cs *engine,
> 					  struct drm_i915_error_engine *ee)
> {
> 	const struct intel_engine_execlists * const execlists = &engine->execlists;
>-	unsigned int n;
>-
>-	for (n = 0; n < execlists_num_ports(execlists); n++) {
>-		struct i915_request *rq = port_request(&execlists->port[n]);
>+	struct i915_request * const *port = execlists->active;
>+	unsigned int n = 0;
> 
>-		if (!rq)
>-			break;
>-
>-		record_request(rq, &ee->execlist[n]);
>-	}
>+	while (*port)
>+		record_request(*port++, &ee->execlist[n++]);
> 
> 	ee->num_ports = n;
> }
>@@ -1355,8 +1303,42 @@
> 	e->active = atomic_read(&ctx->active_count);
> }
> 
>-static void request_record_user_bo(struct i915_request *request,
>-				   struct drm_i915_error_engine *ee)
>+struct capture_vma {
>+	struct capture_vma *next;
>+	void **slot;
>+};
>+
>+static struct capture_vma *
>+capture_vma(struct capture_vma *next,
>+	    struct i915_vma *vma,
>+	    struct drm_i915_error_object **out)
>+{
>+	struct capture_vma *c;
>+
>+	*out = NULL;
>+	if (!vma)
>+		return next;
>+
>+	c = kmalloc(sizeof(*c), ATOMIC_MAYFAIL);
>+	if (!c)
>+		return next;
>+
>+	if (!i915_active_trygrab(&vma->active)) {
>+		kfree(c);
>+		return next;
>+	}
>+
>+	c->slot = (void **)out;
>+	*c->slot = i915_vma_get(vma);
>+
>+	c->next = next;
>+	return c;
>+}
>+
>+static struct capture_vma *
>+request_record_user_bo(struct i915_request *request,
>+		       struct drm_i915_error_engine *ee,
>+		       struct capture_vma *capture)
> {
> 	struct i915_capture_list *c;
> 	struct drm_i915_error_object **bo;
>@@ -1366,33 +1348,34 @@
> 	for (c = request->capture_list; c; c = c->next)
> 		max++;
> 	if (!max)
>-		return;
>+		return capture;
> 
>-	bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);
>+	bo = kmalloc_array(max, sizeof(*bo), ATOMIC_MAYFAIL);
> 	if (!bo) {
> 		/* If we can't capture everything, try to capture something. */
> 		max = min_t(long, max, PAGE_SIZE / sizeof(*bo));
>-		bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);
>+		bo = kmalloc_array(max, sizeof(*bo), ATOMIC_MAYFAIL);
> 	}
> 	if (!bo)
>-		return;
>+		return capture;
> 
> 	count = 0;
> 	for (c = request->capture_list; c; c = c->next) {
>-		bo[count] = i915_error_object_create(request->i915, c->vma);
>-		if (!bo[count])
>-			break;
>+		capture = capture_vma(capture, c->vma, &bo[count]);
> 		if (++count == max)
> 			break;
> 	}
> 
> 	ee->user_bo = bo;
> 	ee->user_bo_count = count;
>+
>+	return capture;
> }
> 
> static struct drm_i915_error_object *
> capture_object(struct drm_i915_private *dev_priv,
>-	       struct drm_i915_gem_object *obj)
>+	       struct drm_i915_gem_object *obj,
>+	       struct compress *compress)
> {
> 	if (obj && i915_gem_object_has_pages(obj)) {
> 		struct i915_vma fake = {
>@@ -1402,21 +1385,22 @@
> 			.obj = obj,
> 		};
> 
>-		return i915_error_object_create(dev_priv, &fake);
>+		return i915_error_object_create(dev_priv, &fake, compress);
> 	} else {
> 		return NULL;
> 	}
> }
> 
>-static void gem_record_rings(struct i915_gpu_state *error)
>+static void
>+gem_record_rings(struct i915_gpu_state *error, struct compress *compress)
> {
> 	struct drm_i915_private *i915 = error->i915;
>-	struct i915_ggtt *ggtt = &i915->ggtt;
> 	int i;
> 
> 	for (i = 0; i < I915_NUM_ENGINES; i++) {
> 		struct intel_engine_cs *engine = i915->engine[i];
> 		struct drm_i915_error_engine *ee = &error->engine[i];
>+		struct capture_vma *capture = NULL;
> 		struct i915_request *request;
> 		unsigned long flags;
> 
>@@ -1427,6 +1411,9 @@
> 
> 		ee->engine_id = i;
> 
>+		/* Refill our page pool before entering atomic section */
>+		pool_refill(&compress->pool, ALLOW_FAIL);
>+
> 		error_record_engine_registers(error, engine, ee);
> 		error_record_engine_execlists(engine, ee);
> 
>@@ -1436,26 +1423,31 @@
> 			struct i915_gem_context *ctx = request->gem_context;
> 			struct intel_ring *ring = request->ring;
> 
>-			ee->vm = ctx->vm ?: &ggtt->vm;
>-
> 			record_context(&ee->context, ctx);
> 
>-			/* We need to copy these to an anonymous buffer
>+			/*
>+			 * We need to copy these to an anonymous buffer
> 			 * as the simplest method to avoid being overwritten
> 			 * by userspace.
> 			 */
>-			ee->batchbuffer =
>-				i915_error_object_create(i915, request->batch);
>+			capture = capture_vma(capture,
>+					      request->batch,
>+					      &ee->batchbuffer);
> 
> 			if (HAS_BROKEN_CS_TLB(i915))
>-				ee->wa_batchbuffer =
>-					i915_error_object_create(i915,
>-								 i915->gt.scratch);
>-			request_record_user_bo(request, ee);
>-
>-			ee->ctx =
>-				i915_error_object_create(i915,
>-							 request->hw_context->state);
>+				capture = capture_vma(capture,
>+						      engine->gt->scratch,
>+						      &ee->wa_batchbuffer);
>+
>+			capture = request_record_user_bo(request, ee, capture);
>+
>+			capture = capture_vma(capture,
>+					      request->hw_context->state,
>+					      &ee->ctx);
>+
>+			capture = capture_vma(capture,
>+					      ring->vma,
>+					      &ee->ringbuffer);
> 
> 			error->simulated |=
> 				i915_gem_context_no_error_capture(ctx);
>@@ -1466,116 +1458,63 @@
> 
> 			ee->cpu_ring_head = ring->head;
> 			ee->cpu_ring_tail = ring->tail;
>-			ee->ringbuffer =
>-				i915_error_object_create(i915, ring->vma);
> 
> 			engine_record_requests(engine, request, ee);
> 		}
> 		spin_unlock_irqrestore(&engine->active.lock, flags);
> 
>-		ee->hws_page =
>-			i915_error_object_create(i915,
>-						 engine->status_page.vma);
>-
>-		ee->wa_ctx = i915_error_object_create(i915, engine->wa_ctx.vma);
>-
>-		ee->default_state = capture_object(i915, engine->default_state);
>-	}
>-}
>-
>-static void gem_capture_vm(struct i915_gpu_state *error,
>-			   struct i915_address_space *vm,
>-			   int idx)
>-{
>-	struct drm_i915_error_buffer *active_bo;
>-	struct i915_vma *vma;
>-	int count;
>-
>-	count = 0;
>-	list_for_each_entry(vma, &vm->bound_list, vm_link)
>-		if (i915_vma_is_active(vma))
>-			count++;
>-
>-	active_bo = NULL;
>-	if (count)
>-		active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
>-	if (active_bo)
>-		count = capture_error_bo(active_bo,
>-					 count, &vm->bound_list,
>-					 ACTIVE_ONLY);
>-	else
>-		count = 0;
>+		while (capture) {
>+			struct capture_vma *this = capture;
>+			struct i915_vma *vma = *this->slot;
> 
>-	error->active_vm[idx] = vm;
>-	error->active_bo[idx] = active_bo;
>-	error->active_bo_count[idx] = count;
>-}
>+			*this->slot =
>+				i915_error_object_create(i915, vma, compress);
> 
>-static void capture_active_buffers(struct i915_gpu_state *error)
>-{
>-	int cnt = 0, i, j;
>+			i915_active_ungrab(&vma->active);
>+			i915_vma_put(vma);
> 
>-	BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
>-	BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
>-	BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
>+			capture = this->next;
>+			kfree(this);
>+		}
> 
>-	/* Scan each engine looking for unique active contexts/vm */
>-	for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
>-		struct drm_i915_error_engine *ee = &error->engine[i];
>-		bool found;
>+		ee->hws_page =
>+			i915_error_object_create(i915,
>+						 engine->status_page.vma,
>+						 compress);
> 
>-		if (!ee->vm)
>-			continue;
>+		ee->wa_ctx =
>+			i915_error_object_create(i915,
>+						 engine->wa_ctx.vma,
>+						 compress);
> 
>-		found = false;
>-		for (j = 0; j < i && !found; j++)
>-			found = error->engine[j].vm == ee->vm;
>-		if (!found)
>-			gem_capture_vm(error, ee->vm, cnt++);
>+		ee->default_state =
>+			capture_object(i915, engine->default_state, compress);
> 	}
> }
> 
>-static void capture_pinned_buffers(struct i915_gpu_state *error)
>-{
>-	struct i915_address_space *vm = &error->i915->ggtt.vm;
>-	struct drm_i915_error_buffer *bo;
>-	struct i915_vma *vma;
>-	int count;
>-
>-	count = 0;
>-	list_for_each_entry(vma, &vm->bound_list, vm_link)
>-		count++;
>-
>-	bo = NULL;
>-	if (count)
>-		bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC);
>-	if (!bo)
>-		return;
>-
>-	error->pinned_bo_count =
>-		capture_error_bo(bo, count, &vm->bound_list, PINNED_ONLY);
>-	error->pinned_bo = bo;
>-}
>-
>-static void capture_uc_state(struct i915_gpu_state *error)
>+static void
>+capture_uc_state(struct i915_gpu_state *error, struct compress *compress)
> {
> 	struct drm_i915_private *i915 = error->i915;
> 	struct i915_error_uc *error_uc = &error->uc;
>+	struct intel_uc *uc = &i915->gt.uc;
> 
> 	/* Capturing uC state won't be useful if there is no GuC */
>-	if (!error->device_info.has_guc)
>+	if (!error->device_info.has_gt_uc)
> 		return;
> 
>-	error_uc->guc_fw = i915->guc.fw;
>-	error_uc->huc_fw = i915->huc.fw;
>+	error_uc->guc_fw = uc->guc.fw;
>+	error_uc->huc_fw = uc->huc.fw;
> 
> 	/* Non-default firmware paths will be specified by the modparam.
> 	 * As modparams are generally accesible from the userspace make
> 	 * explicit copies of the firmware paths.
> 	 */
>-	error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC);
>-	error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC);
>-	error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma);
>+	error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL);
>+	error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL);
>+	error_uc->guc_log = i915_error_object_create(i915,
>+						     uc->guc.log.vma,
>+						     compress);
> }
> 
> /* Capture all registers which don't fit into another category. */
>@@ -1759,56 +1698,53 @@
> 	ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
> }
> 
>-static int capture(void *data)
>-{
>-	struct i915_gpu_state *error = data;
>-
>-	error->time = ktime_get_real();
>-	error->boottime = ktime_get_boottime();
>-	error->uptime = ktime_sub(ktime_get(),
>-				  error->i915->gt.last_init_time);
>-	error->capture = jiffies;
>-
>-	capture_params(error);
>-	capture_gen_state(error);
>-	capture_uc_state(error);
>-	capture_reg_state(error);
>-	gem_record_fences(error);
>-	gem_record_rings(error);
>-	capture_active_buffers(error);
>-	capture_pinned_buffers(error);
>-
>-	error->overlay = intel_overlay_capture_error_state(error->i915);
>-	error->display = intel_display_capture_error_state(error->i915);
>-
>-	error->epoch = capture_find_epoch(error);
>-
>-	capture_finish(error);
>-	return 0;
>-}
>-
> #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
> 
> struct i915_gpu_state *
> i915_capture_gpu_state(struct drm_i915_private *i915)
> {
> 	struct i915_gpu_state *error;
>+	struct compress compress;
> 
> 	/* Check if GPU capture has been disabled */
> 	error = READ_ONCE(i915->gpu_error.first_error);
> 	if (IS_ERR(error))
> 		return error;
> 
>-	error = kzalloc(sizeof(*error), GFP_ATOMIC);
>+	error = kzalloc(sizeof(*error), ALLOW_FAIL);
> 	if (!error) {
> 		i915_disable_error_state(i915, -ENOMEM);
> 		return ERR_PTR(-ENOMEM);
> 	}
> 
>+	if (!compress_init(&compress)) {
>+		kfree(error);
>+		i915_disable_error_state(i915, -ENOMEM);
>+		return ERR_PTR(-ENOMEM);
>+	}
>+
> 	kref_init(&error->ref);
> 	error->i915 = i915;
> 
>-	stop_machine(capture, error, NULL);
>+	error->time = ktime_get_real();
>+	error->boottime = ktime_get_boottime();
>+	error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time);
>+	error->capture = jiffies;
>+
>+	capture_params(error);
>+	capture_gen_state(error);
>+	capture_uc_state(error, &compress);
>+	capture_reg_state(error);
>+	gem_record_fences(error);
>+	gem_record_rings(error, &compress);
>+
>+	error->overlay = intel_overlay_capture_error_state(i915);
>+	error->display = intel_display_capture_error_state(i915);
>+
>+	error->epoch = capture_find_epoch(error);
>+
>+	capture_finish(error);
>+	compress_fini(&compress);
> 
> 	return error;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_gpu_error.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gpu_error.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_gpu_error.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_gpu_error.h	2019-08-31 15:01:12.033736184 -0500
>@@ -7,6 +7,7 @@
> #ifndef _I915_GPU_ERROR_H_
> #define _I915_GPU_ERROR_H_
> 
>+#include <linux/atomic.h>
> #include <linux/kref.h>
> #include <linux/ktime.h>
> #include <linux/sched.h>
>@@ -14,9 +15,9 @@
> #include <drm/drm_mm.h>
> 
> #include "gt/intel_engine.h"
>+#include "gt/uc/intel_uc_fw.h"
> 
> #include "intel_device_info.h"
>-#include "intel_uc_fw.h"
> 
> #include "i915_gem.h"
> #include "i915_gem_gtt.h"
>@@ -84,7 +85,6 @@
> 		/* Software tracked state */
> 		bool idle;
> 		unsigned long hangcheck_timestamp;
>-		struct i915_address_space *vm;
> 		int num_requests;
> 		u32 reset_count;
> 
>@@ -160,32 +160,10 @@
> 		} vm_info;
> 	} engine[I915_NUM_ENGINES];
> 
>-	struct drm_i915_error_buffer {
>-		u32 size;
>-		u32 name;
>-		u64 gtt_offset;
>-		u32 read_domains;
>-		u32 write_domain;
>-		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
>-		u32 tiling:2;
>-		u32 dirty:1;
>-		u32 purgeable:1;
>-		u32 userptr:1;
>-		u32 cache_level:3;
>-	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
>-	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
>-	struct i915_address_space *active_vm[I915_NUM_ENGINES];
>-
> 	struct scatterlist *sgl, *fit;
> };
> 
> struct i915_gpu_error {
>-	/* For hangcheck timer */
>-#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
>-#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
>-
>-	struct delayed_work hangcheck_work;
>-
> 	/* For reset and error_state handling. */
> 	spinlock_t lock;
> 	/* Protected by the above dev->gpu_error.lock. */
>@@ -193,52 +171,11 @@
> 
> 	atomic_t pending_fb_pin;
> 
>-	/**
>-	 * flags: Control various stages of the GPU reset
>-	 *
>-	 * #I915_RESET_BACKOFF - When we start a global reset, we need to
>-	 * serialise with any other users attempting to do the same, and
>-	 * any global resources that may be clobber by the reset (such as
>-	 * FENCE registers).
>-	 *
>-	 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
>-	 * acquire the struct_mutex to reset an engine, we need an explicit
>-	 * flag to prevent two concurrent reset attempts in the same engine.
>-	 * As the number of engines continues to grow, allocate the flags from
>-	 * the most significant bits.
>-	 *
>-	 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
>-	 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
>-	 * i915_request_alloc(), this bit is checked and the sequence
>-	 * aborted (with -EIO reported to userspace) if set.
>-	 */
>-	unsigned long flags;
>-#define I915_RESET_BACKOFF	0
>-#define I915_RESET_MODESET	1
>-#define I915_RESET_ENGINE	2
>-#define I915_WEDGED		(BITS_PER_LONG - 1)
>-
> 	/** Number of times the device has been reset (global) */
>-	u32 reset_count;
>+	atomic_t reset_count;
> 
> 	/** Number of times an engine has been reset */
>-	u32 reset_engine_count[I915_NUM_ENGINES];
>-
>-	struct mutex wedge_mutex; /* serialises wedging/unwedging */
>-
>-	/**
>-	 * Waitqueue to signal when a hang is detected. Used to for waiters
>-	 * to release the struct_mutex for the reset to procede.
>-	 */
>-	wait_queue_head_t wait_queue;
>-
>-	/**
>-	 * Waitqueue to signal when the reset has completed. Used by clients
>-	 * that wait for dev_priv->mm.wedged to settle.
>-	 */
>-	wait_queue_head_t reset_queue;
>-
>-	struct srcu_struct reset_backoff_srcu;
>+	atomic_t reset_engine_count[I915_NUM_ENGINES];
> };
> 
> struct drm_i915_error_state_buf {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_irq.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_irq.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_irq.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_irq.c	2019-08-31 15:01:12.034736184 -0500
>@@ -42,6 +42,8 @@
> #include "display/intel_lpe_audio.h"
> #include "display/intel_psr.h"
> 
>+#include "gt/intel_gt.h"
>+
> #include "i915_drv.h"
> #include "i915_irq.h"
> #include "i915_trace.h"
>@@ -264,7 +266,7 @@
> 	gen2_irq_init((uncore), imr_val, ier_val)
> 
> static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
>-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
>+static void guc_irq_handler(struct intel_guc *guc, u16 guc_iir);
> 
> /* For display hotplug interrupt */
> static inline void
>@@ -305,17 +307,17 @@
> }
> 
> static u32
>-gen11_gt_engine_identity(struct drm_i915_private * const i915,
>+gen11_gt_engine_identity(struct intel_gt *gt,
> 			 const unsigned int bank, const unsigned int bit);
> 
>-static bool gen11_reset_one_iir(struct drm_i915_private * const i915,
>+static bool gen11_reset_one_iir(struct intel_gt *gt,
> 				const unsigned int bank,
> 				const unsigned int bit)
> {
>-	void __iomem * const regs = i915->uncore.regs;
>+	void __iomem * const regs = gt->uncore->regs;
> 	u32 dw;
> 
>-	lockdep_assert_held(&i915->irq_lock);
>+	lockdep_assert_held(&gt->i915->irq_lock);
> 
> 	dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
> 	if (dw & BIT(bit)) {
>@@ -323,7 +325,7 @@
> 		 * According to the BSpec, DW_IIR bits cannot be cleared without
> 		 * first servicing the Selector & Shared IIR registers.
> 		 */
>-		gen11_gt_engine_identity(i915, bank, bit);
>+		gen11_gt_engine_identity(gt, bank, bit);
> 
> 		/*
> 		 * We locked GT INT DW by reading it. If we want to (try
>@@ -409,50 +411,54 @@
> 	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
> }
> 
>-static void write_pm_imr(struct drm_i915_private *dev_priv)
>+static void write_pm_imr(struct intel_gt *gt)
> {
>+	struct drm_i915_private *i915 = gt->i915;
>+	struct intel_uncore *uncore = gt->uncore;
>+	u32 mask = gt->pm_imr;
> 	i915_reg_t reg;
>-	u32 mask = dev_priv->pm_imr;
> 
>-	if (INTEL_GEN(dev_priv) >= 11) {
>+	if (INTEL_GEN(i915) >= 11) {
> 		reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
> 		/* pm is in upper half */
> 		mask = mask << 16;
>-	} else if (INTEL_GEN(dev_priv) >= 8) {
>+	} else if (INTEL_GEN(i915) >= 8) {
> 		reg = GEN8_GT_IMR(2);
> 	} else {
> 		reg = GEN6_PMIMR;
> 	}
> 
>-	I915_WRITE(reg, mask);
>-	POSTING_READ(reg);
>+	intel_uncore_write(uncore, reg, mask);
>+	intel_uncore_posting_read(uncore, reg);
> }
> 
>-static void write_pm_ier(struct drm_i915_private *dev_priv)
>+static void write_pm_ier(struct intel_gt *gt)
> {
>+	struct drm_i915_private *i915 = gt->i915;
>+	struct intel_uncore *uncore = gt->uncore;
>+	u32 mask = gt->pm_ier;
> 	i915_reg_t reg;
>-	u32 mask = dev_priv->pm_ier;
> 
>-	if (INTEL_GEN(dev_priv) >= 11) {
>+	if (INTEL_GEN(i915) >= 11) {
> 		reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
> 		/* pm is in upper half */
> 		mask = mask << 16;
>-	} else if (INTEL_GEN(dev_priv) >= 8) {
>+	} else if (INTEL_GEN(i915) >= 8) {
> 		reg = GEN8_GT_IER(2);
> 	} else {
> 		reg = GEN6_PMIER;
> 	}
> 
>-	I915_WRITE(reg, mask);
>+	intel_uncore_write(uncore, reg, mask);
> }
> 
> /**
>  * snb_update_pm_irq - update GEN6_PMIMR
>- * @dev_priv: driver private
>+ * @gt: gt for the interrupts
>  * @interrupt_mask: mask of interrupt bits to update
>  * @enabled_irq_mask: mask of interrupt bits to enable
>  */
>-static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
>+static void snb_update_pm_irq(struct intel_gt *gt,
> 			      u32 interrupt_mask,
> 			      u32 enabled_irq_mask)
> {
>@@ -460,37 +466,37 @@
> 
> 	WARN_ON(enabled_irq_mask & ~interrupt_mask);
> 
>-	lockdep_assert_held(&dev_priv->irq_lock);
>+	lockdep_assert_held(&gt->i915->irq_lock);
> 
>-	new_val = dev_priv->pm_imr;
>+	new_val = gt->pm_imr;
> 	new_val &= ~interrupt_mask;
> 	new_val |= (~enabled_irq_mask & interrupt_mask);
> 
>-	if (new_val != dev_priv->pm_imr) {
>-		dev_priv->pm_imr = new_val;
>-		write_pm_imr(dev_priv);
>+	if (new_val != gt->pm_imr) {
>+		gt->pm_imr = new_val;
>+		write_pm_imr(gt);
> 	}
> }
> 
>-void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
>+void gen6_unmask_pm_irq(struct intel_gt *gt, u32 mask)
> {
>-	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
>+	if (WARN_ON(!intel_irqs_enabled(gt->i915)))
> 		return;
> 
>-	snb_update_pm_irq(dev_priv, mask, mask);
>+	snb_update_pm_irq(gt, mask, mask);
> }
> 
>-static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
>+static void __gen6_mask_pm_irq(struct intel_gt *gt, u32 mask)
> {
>-	snb_update_pm_irq(dev_priv, mask, 0);
>+	snb_update_pm_irq(gt, mask, 0);
> }
> 
>-void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
>+void gen6_mask_pm_irq(struct intel_gt *gt, u32 mask)
> {
>-	if (WARN_ON(!intel_irqs_enabled(dev_priv)))
>+	if (WARN_ON(!intel_irqs_enabled(gt->i915)))
> 		return;
> 
>-	__gen6_mask_pm_irq(dev_priv, mask);
>+	__gen6_mask_pm_irq(gt, mask);
> }
> 
> static void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
>@@ -504,23 +510,23 @@
> 	POSTING_READ(reg);
> }
> 
>-static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
>+static void gen6_enable_pm_irq(struct intel_gt *gt, u32 enable_mask)
> {
>-	lockdep_assert_held(&dev_priv->irq_lock);
>+	lockdep_assert_held(&gt->i915->irq_lock);
> 
>-	dev_priv->pm_ier |= enable_mask;
>-	write_pm_ier(dev_priv);
>-	gen6_unmask_pm_irq(dev_priv, enable_mask);
>+	gt->pm_ier |= enable_mask;
>+	write_pm_ier(gt);
>+	gen6_unmask_pm_irq(gt, enable_mask);
> 	/* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
> }
> 
>-static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
>+static void gen6_disable_pm_irq(struct intel_gt *gt, u32 disable_mask)
> {
>-	lockdep_assert_held(&dev_priv->irq_lock);
>+	lockdep_assert_held(&gt->i915->irq_lock);
> 
>-	dev_priv->pm_ier &= ~disable_mask;
>-	__gen6_mask_pm_irq(dev_priv, disable_mask);
>-	write_pm_ier(dev_priv);
>+	gt->pm_ier &= ~disable_mask;
>+	__gen6_mask_pm_irq(gt, disable_mask);
>+	write_pm_ier(gt);
> 	/* though a barrier is missing here, but don't really need a one */
> }
> 
>@@ -528,7 +534,7 @@
> {
> 	spin_lock_irq(&dev_priv->irq_lock);
> 
>-	while (gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM))
>+	while (gen11_reset_one_iir(&dev_priv->gt, 0, GEN11_GTPM))
> 		;
> 
> 	dev_priv->gt_pm.rps.pm_iir = 0;
>@@ -546,6 +552,7 @@
> 
> void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
> {
>+	struct intel_gt *gt = &dev_priv->gt;
> 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
> 
> 	if (READ_ONCE(rps->interrupts_enabled))
>@@ -555,12 +562,12 @@
> 	WARN_ON_ONCE(rps->pm_iir);
> 
> 	if (INTEL_GEN(dev_priv) >= 11)
>-		WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM));
>+		WARN_ON_ONCE(gen11_reset_one_iir(gt, 0, GEN11_GTPM));
> 	else
> 		WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
> 
> 	rps->interrupts_enabled = true;
>-	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
>+	gen6_enable_pm_irq(gt, dev_priv->pm_rps_events);
> 
> 	spin_unlock_irq(&dev_priv->irq_lock);
> }
>@@ -577,10 +584,10 @@
> 
> 	I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
> 
>-	gen6_disable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
>+	gen6_disable_pm_irq(&dev_priv->gt, GEN6_PM_RPS_EVENTS);
> 
> 	spin_unlock_irq(&dev_priv->irq_lock);
>-	synchronize_irq(dev_priv->drm.irq);
>+	intel_synchronize_irq(dev_priv);
> 
> 	/* Now that we will not be generating any more work, flush any
> 	 * outstanding tasks. As we are called on the RPS idle path,
>@@ -594,78 +601,94 @@
> 		gen6_reset_rps_interrupts(dev_priv);
> }
> 
>-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
>+void gen9_reset_guc_interrupts(struct intel_guc *guc)
> {
>-	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
>+	struct intel_gt *gt = guc_to_gt(guc);
>+	struct drm_i915_private *i915 = gt->i915;
> 
>-	spin_lock_irq(&dev_priv->irq_lock);
>-	gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
>-	spin_unlock_irq(&dev_priv->irq_lock);
>+	assert_rpm_wakelock_held(&i915->runtime_pm);
>+
>+	spin_lock_irq(&i915->irq_lock);
>+	gen6_reset_pm_iir(i915, gt->pm_guc_events);
>+	spin_unlock_irq(&i915->irq_lock);
> }
> 
>-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
>+void gen9_enable_guc_interrupts(struct intel_guc *guc)
> {
>-	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
>+	struct intel_gt *gt = guc_to_gt(guc);
>+	struct drm_i915_private *i915 = gt->i915;
> 
>-	spin_lock_irq(&dev_priv->irq_lock);
>-	if (!dev_priv->guc.interrupts.enabled) {
>-		WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
>-				       dev_priv->pm_guc_events);
>-		dev_priv->guc.interrupts.enabled = true;
>-		gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
>+	assert_rpm_wakelock_held(&i915->runtime_pm);
>+
>+	spin_lock_irq(&i915->irq_lock);
>+	if (!guc->interrupts.enabled) {
>+		WARN_ON_ONCE(intel_uncore_read(gt->uncore, gen6_pm_iir(i915)) &
>+			     gt->pm_guc_events);
>+		guc->interrupts.enabled = true;
>+		gen6_enable_pm_irq(gt, gt->pm_guc_events);
> 	}
>-	spin_unlock_irq(&dev_priv->irq_lock);
>+	spin_unlock_irq(&i915->irq_lock);
> }
> 
>-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
>+void gen9_disable_guc_interrupts(struct intel_guc *guc)
> {
>-	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
>+	struct intel_gt *gt = guc_to_gt(guc);
>+	struct drm_i915_private *i915 = gt->i915;
> 
>-	spin_lock_irq(&dev_priv->irq_lock);
>-	dev_priv->guc.interrupts.enabled = false;
>+	assert_rpm_wakelock_held(&i915->runtime_pm);
> 
>-	gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
>+	spin_lock_irq(&i915->irq_lock);
>+	guc->interrupts.enabled = false;
> 
>-	spin_unlock_irq(&dev_priv->irq_lock);
>-	synchronize_irq(dev_priv->drm.irq);
>+	gen6_disable_pm_irq(gt, gt->pm_guc_events);
> 
>-	gen9_reset_guc_interrupts(dev_priv);
>+	spin_unlock_irq(&i915->irq_lock);
>+	intel_synchronize_irq(i915);
>+
>+	gen9_reset_guc_interrupts(guc);
> }
> 
>-void gen11_reset_guc_interrupts(struct drm_i915_private *i915)
>+void gen11_reset_guc_interrupts(struct intel_guc *guc)
> {
>+	struct intel_gt *gt = guc_to_gt(guc);
>+	struct drm_i915_private *i915 = gt->i915;
>+
> 	spin_lock_irq(&i915->irq_lock);
>-	gen11_reset_one_iir(i915, 0, GEN11_GUC);
>+	gen11_reset_one_iir(gt, 0, GEN11_GUC);
> 	spin_unlock_irq(&i915->irq_lock);
> }
> 
>-void gen11_enable_guc_interrupts(struct drm_i915_private *dev_priv)
>+void gen11_enable_guc_interrupts(struct intel_guc *guc)
> {
>-	spin_lock_irq(&dev_priv->irq_lock);
>-	if (!dev_priv->guc.interrupts.enabled) {
>-		u32 events = REG_FIELD_PREP(ENGINE1_MASK,
>-					    GEN11_GUC_INTR_GUC2HOST);
>-
>-		WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GUC));
>-		I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, events);
>-		I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~events);
>-		dev_priv->guc.interrupts.enabled = true;
>+	struct intel_gt *gt = guc_to_gt(guc);
>+
>+	spin_lock_irq(&gt->i915->irq_lock);
>+	if (!guc->interrupts.enabled) {
>+		u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
>+
>+		WARN_ON_ONCE(gen11_reset_one_iir(gt, 0, GEN11_GUC));
>+		intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, events);
>+		intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~events);
>+		guc->interrupts.enabled = true;
> 	}
>-	spin_unlock_irq(&dev_priv->irq_lock);
>+	spin_unlock_irq(&gt->i915->irq_lock);
> }
> 
>-void gen11_disable_guc_interrupts(struct drm_i915_private *dev_priv)
>+void gen11_disable_guc_interrupts(struct intel_guc *guc)
> {
>-	spin_lock_irq(&dev_priv->irq_lock);
>-	dev_priv->guc.interrupts.enabled = false;
>+	struct intel_gt *gt = guc_to_gt(guc);
>+	struct drm_i915_private *i915 = gt->i915;
> 
>-	I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
>-	I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
>+	spin_lock_irq(&i915->irq_lock);
>+	guc->interrupts.enabled = false;
> 
>-	spin_unlock_irq(&dev_priv->irq_lock);
>-	synchronize_irq(dev_priv->drm.irq);
>+	intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);
>+	intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
> 
>-	gen11_reset_guc_interrupts(dev_priv);
>+	spin_unlock_irq(&i915->irq_lock);
>+	intel_synchronize_irq(i915);
>+
>+	gen11_reset_guc_interrupts(guc);
> }
> 
> /**
>@@ -924,11 +947,12 @@
> /* Called from drm generic code, passed a 'crtc', which
>  * we use as a pipe index
>  */
>-static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
>+u32 i915_get_vblank_counter(struct drm_crtc *crtc)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>-	struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
>+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>+	struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
> 	const struct drm_display_mode *mode = &vblank->hwmode;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> 	i915_reg_t high_frame, low_frame;
> 	u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
> 	unsigned long irqflags;
>@@ -989,9 +1013,10 @@
> 	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
> }
> 
>-static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
>+u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> 
> 	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
> }
>@@ -1107,10 +1132,10 @@
> 	return (position + crtc->scanline_offset) % vtotal;
> }
> 
>-static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
>-				     bool in_vblank_irq, int *vpos, int *hpos,
>-				     ktime_t *stime, ktime_t *etime,
>-				     const struct drm_display_mode *mode)
>+bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
>+			      bool in_vblank_irq, int *vpos, int *hpos,
>+			      ktime_t *stime, ktime_t *etime,
>+			      const struct drm_display_mode *mode)
> {
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
>@@ -1424,7 +1449,7 @@
> 	/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
> 	spin_lock_irq(&dev_priv->irq_lock);
> 	if (rps->interrupts_enabled)
>-		gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
>+		gen6_unmask_pm_irq(&dev_priv->gt, dev_priv->pm_rps_events);
> 	spin_unlock_irq(&dev_priv->irq_lock);
> }
> 
>@@ -1637,7 +1662,7 @@
> 
> 	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> 		gen6_rps_irq_handler(i915, gt_iir[2]);
>-		gen9_guc_irq_handler(i915, gt_iir[2]);
>+		guc_irq_handler(&i915->gt.uc.guc, gt_iir[2] >> 16);
> 	}
> }
> 
>@@ -1891,8 +1916,9 @@
> /* The RPS events need forcewake, so we add them to a work queue and mask their
>  * IMR bits until the work is done. Other interrupts can be processed without
>  * the work queue. */
>-static void gen11_rps_irq_handler(struct drm_i915_private *i915, u32 pm_iir)
>+static void gen11_rps_irq_handler(struct intel_gt *gt, u32 pm_iir)
> {
>+	struct drm_i915_private *i915 = gt->i915;
> 	struct intel_rps *rps = &i915->gt_pm.rps;
> 	const u32 events = i915->pm_rps_events & pm_iir;
> 
>@@ -1901,7 +1927,7 @@
> 	if (unlikely(!events))
> 		return;
> 
>-	gen6_mask_pm_irq(i915, events);
>+	gen6_mask_pm_irq(gt, events);
> 
> 	if (!rps->interrupts_enabled)
> 		return;
>@@ -1916,7 +1942,8 @@
> 
> 	if (pm_iir & dev_priv->pm_rps_events) {
> 		spin_lock(&dev_priv->irq_lock);
>-		gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
>+		gen6_mask_pm_irq(&dev_priv->gt,
>+				 pm_iir & dev_priv->pm_rps_events);
> 		if (rps->interrupts_enabled) {
> 			rps->pm_iir |= pm_iir & dev_priv->pm_rps_events;
> 			schedule_work(&rps->work);
>@@ -1934,16 +1961,10 @@
> 		DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
> }
> 
>-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
>-{
>-	if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
>-		intel_guc_to_host_event_handler(&dev_priv->guc);
>-}
>-
>-static void gen11_guc_irq_handler(struct drm_i915_private *i915, u16 iir)
>+static void guc_irq_handler(struct intel_guc *guc, u16 iir)
> {
>-	if (iir & GEN11_GUC_INTR_GUC2HOST)
>-		intel_guc_to_host_event_handler(&i915->guc);
>+	if (iir & GUC_INTR_GUC2HOST)
>+		intel_guc_to_host_event_handler(guc);
> }
> 
> static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
>@@ -2185,8 +2206,7 @@
> 
> static irqreturn_t valleyview_irq_handler(int irq, void *arg)
> {
>-	struct drm_device *dev = arg;
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = arg;
> 	irqreturn_t ret = IRQ_NONE;
> 
> 	if (!intel_irqs_enabled(dev_priv))
>@@ -2271,8 +2291,7 @@
> 
> static irqreturn_t cherryview_irq_handler(int irq, void *arg)
> {
>-	struct drm_device *dev = arg;
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = arg;
> 	irqreturn_t ret = IRQ_NONE;
> 
> 	if (!intel_irqs_enabled(dev_priv))
>@@ -2691,8 +2710,7 @@
>  */
> static irqreturn_t ironlake_irq_handler(int irq, void *arg)
> {
>-	struct drm_device *dev = arg;
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = arg;
> 	u32 de_iir, gt_iir, de_ier, sde_ier = 0;
> 	irqreturn_t ret = IRQ_NONE;
> 
>@@ -2826,6 +2844,14 @@
> 	return mask;
> }
> 
>+static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
>+{
>+	if (INTEL_GEN(dev_priv) >= 9)
>+		return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
>+	else
>+		return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
>+}
>+
> static irqreturn_t
> gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> {
>@@ -2938,12 +2964,7 @@
> 		if (iir & GEN8_PIPE_FIFO_UNDERRUN)
> 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
> 
>-		fault_errors = iir;
>-		if (INTEL_GEN(dev_priv) >= 9)
>-			fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
>-		else
>-			fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
>-
>+		fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
> 		if (fault_errors)
> 			DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
> 				  pipe_name(pipe),
>@@ -3002,7 +3023,7 @@
> 
> static irqreturn_t gen8_irq_handler(int irq, void *arg)
> {
>-	struct drm_i915_private *dev_priv = to_i915(arg);
>+	struct drm_i915_private *dev_priv = arg;
> 	void __iomem * const regs = dev_priv->uncore.regs;
> 	u32 master_ctl;
> 	u32 gt_iir[4];
>@@ -3034,14 +3055,14 @@
> }
> 
> static u32
>-gen11_gt_engine_identity(struct drm_i915_private * const i915,
>+gen11_gt_engine_identity(struct intel_gt *gt,
> 			 const unsigned int bank, const unsigned int bit)
> {
>-	void __iomem * const regs = i915->uncore.regs;
>+	void __iomem * const regs = gt->uncore->regs;
> 	u32 timeout_ts;
> 	u32 ident;
> 
>-	lockdep_assert_held(&i915->irq_lock);
>+	lockdep_assert_held(&gt->i915->irq_lock);
> 
> 	raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
> 
>@@ -3068,27 +3089,27 @@
> }
> 
> static void
>-gen11_other_irq_handler(struct drm_i915_private * const i915,
>-			const u8 instance, const u16 iir)
>+gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
>+			const u16 iir)
> {
> 	if (instance == OTHER_GUC_INSTANCE)
>-		return gen11_guc_irq_handler(i915, iir);
>+		return guc_irq_handler(&gt->uc.guc, iir);
> 
> 	if (instance == OTHER_GTPM_INSTANCE)
>-		return gen11_rps_irq_handler(i915, iir);
>+		return gen11_rps_irq_handler(gt, iir);
> 
> 	WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
> 		  instance, iir);
> }
> 
> static void
>-gen11_engine_irq_handler(struct drm_i915_private * const i915,
>-			 const u8 class, const u8 instance, const u16 iir)
>+gen11_engine_irq_handler(struct intel_gt *gt, const u8 class,
>+			 const u8 instance, const u16 iir)
> {
> 	struct intel_engine_cs *engine;
> 
> 	if (instance <= MAX_ENGINE_INSTANCE)
>-		engine = i915->engine_class[class][instance];
>+		engine = gt->i915->engine_class[class][instance];
> 	else
> 		engine = NULL;
> 
>@@ -3100,8 +3121,7 @@
> }
> 
> static void
>-gen11_gt_identity_handler(struct drm_i915_private * const i915,
>-			  const u32 identity)
>+gen11_gt_identity_handler(struct intel_gt *gt, const u32 identity)
> {
> 	const u8 class = GEN11_INTR_ENGINE_CLASS(identity);
> 	const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);
>@@ -3111,31 +3131,30 @@
> 		return;
> 
> 	if (class <= COPY_ENGINE_CLASS)
>-		return gen11_engine_irq_handler(i915, class, instance, intr);
>+		return gen11_engine_irq_handler(gt, class, instance, intr);
> 
> 	if (class == OTHER_CLASS)
>-		return gen11_other_irq_handler(i915, instance, intr);
>+		return gen11_other_irq_handler(gt, instance, intr);
> 
> 	WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
> 		  class, instance, intr);
> }
> 
> static void
>-gen11_gt_bank_handler(struct drm_i915_private * const i915,
>-		      const unsigned int bank)
>+gen11_gt_bank_handler(struct intel_gt *gt, const unsigned int bank)
> {
>-	void __iomem * const regs = i915->uncore.regs;
>+	void __iomem * const regs = gt->uncore->regs;
> 	unsigned long intr_dw;
> 	unsigned int bit;
> 
>-	lockdep_assert_held(&i915->irq_lock);
>+	lockdep_assert_held(&gt->i915->irq_lock);
> 
> 	intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
> 
> 	for_each_set_bit(bit, &intr_dw, 32) {
>-		const u32 ident = gen11_gt_engine_identity(i915, bank, bit);
>+		const u32 ident = gen11_gt_engine_identity(gt, bank, bit);
> 
>-		gen11_gt_identity_handler(i915, ident);
>+		gen11_gt_identity_handler(gt, ident);
> 	}
> 
> 	/* Clear must be after shared has been served for engine */
>@@ -3143,25 +3162,25 @@
> }
> 
> static void
>-gen11_gt_irq_handler(struct drm_i915_private * const i915,
>-		     const u32 master_ctl)
>+gen11_gt_irq_handler(struct intel_gt *gt, const u32 master_ctl)
> {
>+	struct drm_i915_private *i915 = gt->i915;
> 	unsigned int bank;
> 
> 	spin_lock(&i915->irq_lock);
> 
> 	for (bank = 0; bank < 2; bank++) {
> 		if (master_ctl & GEN11_GT_DW_IRQ(bank))
>-			gen11_gt_bank_handler(i915, bank);
>+			gen11_gt_bank_handler(gt, bank);
> 	}
> 
> 	spin_unlock(&i915->irq_lock);
> }
> 
> static u32
>-gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl)
>+gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
> {
>-	void __iomem * const regs = dev_priv->uncore.regs;
>+	void __iomem * const regs = gt->uncore->regs;
> 	u32 iir;
> 
> 	if (!(master_ctl & GEN11_GU_MISC_IRQ))
>@@ -3175,10 +3194,10 @@
> }
> 
> static void
>-gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, const u32 iir)
>+gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
> {
> 	if (iir & GEN11_GU_MISC_GSE)
>-		intel_opregion_asle_intr(dev_priv);
>+		intel_opregion_asle_intr(gt->i915);
> }
> 
> static inline u32 gen11_master_intr_disable(void __iomem * const regs)
>@@ -3201,8 +3220,9 @@
> 
> static irqreturn_t gen11_irq_handler(int irq, void *arg)
> {
>-	struct drm_i915_private * const i915 = to_i915(arg);
>+	struct drm_i915_private * const i915 = arg;
> 	void __iomem * const regs = i915->uncore.regs;
>+	struct intel_gt *gt = &i915->gt;
> 	u32 master_ctl;
> 	u32 gu_misc_iir;
> 
>@@ -3216,7 +3236,7 @@
> 	}
> 
> 	/* Find, clear, then process each source of interrupt. */
>-	gen11_gt_irq_handler(i915, master_ctl);
>+	gen11_gt_irq_handler(gt, master_ctl);
> 
> 	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
> 	if (master_ctl & GEN11_DISPLAY_IRQ) {
>@@ -3231,11 +3251,11 @@
> 		enable_rpm_wakeref_asserts(&i915->runtime_pm);
> 	}
> 
>-	gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
>+	gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
> 
> 	gen11_master_intr_enable(regs);
> 
>-	gen11_gu_misc_irq_handler(i915, gu_misc_iir);
>+	gen11_gu_misc_irq_handler(gt, gu_misc_iir);
> 
> 	return IRQ_HANDLED;
> }
>@@ -3243,9 +3263,10 @@
> /* Called from drm generic code, passed 'crtc' which
>  * we use as a pipe index
>  */
>-static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
>+int i8xx_enable_vblank(struct drm_crtc *crtc)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> 	unsigned long irqflags;
> 
> 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>@@ -3255,19 +3276,20 @@
> 	return 0;
> }
> 
>-static int i945gm_enable_vblank(struct drm_device *dev, unsigned int pipe)
>+int i945gm_enable_vblank(struct drm_crtc *crtc)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> 
> 	if (dev_priv->i945gm_vblank.enabled++ == 0)
> 		schedule_work(&dev_priv->i945gm_vblank.work);
> 
>-	return i8xx_enable_vblank(dev, pipe);
>+	return i8xx_enable_vblank(crtc);
> }
> 
>-static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
>+int i965_enable_vblank(struct drm_crtc *crtc)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> 	unsigned long irqflags;
> 
> 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>@@ -3278,9 +3300,10 @@
> 	return 0;
> }
> 
>-static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
>+int ilk_enable_vblank(struct drm_crtc *crtc)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> 	unsigned long irqflags;
> 	u32 bit = INTEL_GEN(dev_priv) >= 7 ?
> 		DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
>@@ -3293,14 +3316,15 @@
> 	 * PSR is active as no frames are generated.
> 	 */
> 	if (HAS_PSR(dev_priv))
>-		drm_vblank_restore(dev, pipe);
>+		drm_crtc_vblank_restore(crtc);
> 
> 	return 0;
> }
> 
>-static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
>+int bdw_enable_vblank(struct drm_crtc *crtc)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> 	unsigned long irqflags;
> 
> 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>@@ -3311,7 +3335,7 @@
> 	 * PSR is active as no frames are generated, so check only for PSR.
> 	 */
> 	if (HAS_PSR(dev_priv))
>-		drm_vblank_restore(dev, pipe);
>+		drm_crtc_vblank_restore(crtc);
> 
> 	return 0;
> }
>@@ -3319,9 +3343,10 @@
> /* Called from drm generic code, passed 'crtc' which
>  * we use as a pipe index
>  */
>-static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
>+void i8xx_disable_vblank(struct drm_crtc *crtc)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> 	unsigned long irqflags;
> 
> 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>@@ -3329,19 +3354,20 @@
> 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> }
> 
>-static void i945gm_disable_vblank(struct drm_device *dev, unsigned int pipe)
>+void i945gm_disable_vblank(struct drm_crtc *crtc)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> 
>-	i8xx_disable_vblank(dev, pipe);
>+	i8xx_disable_vblank(crtc);
> 
> 	if (--dev_priv->i945gm_vblank.enabled == 0)
> 		schedule_work(&dev_priv->i945gm_vblank.work);
> }
> 
>-static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
>+void i965_disable_vblank(struct drm_crtc *crtc)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> 	unsigned long irqflags;
> 
> 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>@@ -3350,9 +3376,10 @@
> 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> }
> 
>-static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
>+void ilk_disable_vblank(struct drm_crtc *crtc)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> 	unsigned long irqflags;
> 	u32 bit = INTEL_GEN(dev_priv) >= 7 ?
> 		DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
>@@ -3362,9 +3389,10 @@
> 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> }
> 
>-static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
>+void bdw_disable_vblank(struct drm_crtc *crtc)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> 	unsigned long irqflags;
> 
> 	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>@@ -3447,10 +3475,8 @@
>  *
>  * This function needs to be called before interrupts are enabled.
>  */
>-static void ibx_irq_pre_postinstall(struct drm_device *dev)
>+static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>-
> 	if (HAS_PCH_NOP(dev_priv))
> 		return;
> 
>@@ -3473,12 +3499,12 @@
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 
> 	if (IS_CHERRYVIEW(dev_priv))
>-		I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
>+		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
> 	else
>-		I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
>+		intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
> 
> 	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
>-	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>+	intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> 
> 	i9xx_pipestat_irq_reset(dev_priv);
> 
>@@ -3519,18 +3545,17 @@
> 
> /* drm_dma.h hooks
> */
>-static void ironlake_irq_reset(struct drm_device *dev)
>+static void ironlake_irq_reset(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 
> 	GEN3_IRQ_RESET(uncore, DE);
> 	if (IS_GEN(dev_priv, 7))
>-		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
>+		intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
> 
> 	if (IS_HASWELL(dev_priv)) {
>-		I915_WRITE(EDP_PSR_IMR, 0xffffffff);
>-		I915_WRITE(EDP_PSR_IIR, 0xffffffff);
>+		intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
>+		intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
> 	}
> 
> 	gen5_gt_irq_reset(dev_priv);
>@@ -3538,10 +3563,8 @@
> 	ibx_irq_reset(dev_priv);
> }
> 
>-static void valleyview_irq_reset(struct drm_device *dev)
>+static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>-
> 	I915_WRITE(VLV_MASTER_IER, 0);
> 	POSTING_READ(VLV_MASTER_IER);
> 
>@@ -3563,9 +3586,8 @@
> 	GEN8_IRQ_RESET_NDX(uncore, GT, 3);
> }
> 
>-static void gen8_irq_reset(struct drm_device *dev)
>+static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 	int pipe;
> 
>@@ -3573,8 +3595,8 @@
> 
> 	gen8_gt_irq_reset(dev_priv);
> 
>-	I915_WRITE(EDP_PSR_IMR, 0xffffffff);
>-	I915_WRITE(EDP_PSR_IIR, 0xffffffff);
>+	intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
>+	intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
> 
> 	for_each_pipe(dev_priv, pipe)
> 		if (intel_display_power_is_enabled(dev_priv,
>@@ -3589,39 +3611,40 @@
> 		ibx_irq_reset(dev_priv);
> }
> 
>-static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
>+static void gen11_gt_irq_reset(struct intel_gt *gt)
> {
>+	struct intel_uncore *uncore = gt->uncore;
>+
> 	/* Disable RCS, BCS, VCS and VECS class engines. */
>-	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
>-	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  0);
>+	intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0);
>+	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE,	  0);
> 
> 	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
>-	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~0);
>-	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~0);
>-	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~0);
>-	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~0);
>-	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~0);
>-
>-	I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
>-	I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
>-	I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
>-	I915_WRITE(GEN11_GUC_SG_INTR_MASK,  ~0);
>+	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK,	~0);
>+	intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK,	~0);
>+	intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK,	~0);
>+	intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK,	~0);
>+	intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK,	~0);
>+
>+	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
>+	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
>+	intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
>+	intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK,  ~0);
> }
> 
>-static void gen11_irq_reset(struct drm_device *dev)
>+static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = dev->dev_private;
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 	int pipe;
> 
> 	gen11_master_intr_disable(dev_priv->uncore.regs);
> 
>-	gen11_gt_irq_reset(dev_priv);
>+	gen11_gt_irq_reset(&dev_priv->gt);
> 
>-	I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
>+	intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
> 
>-	I915_WRITE(EDP_PSR_IMR, 0xffffffff);
>-	I915_WRITE(EDP_PSR_IIR, 0xffffffff);
>+	intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
>+	intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
> 
> 	for_each_pipe(dev_priv, pipe)
> 		if (intel_display_power_is_enabled(dev_priv,
>@@ -3680,12 +3703,11 @@
> 	spin_unlock_irq(&dev_priv->irq_lock);
> 
> 	/* make sure we're done processing display irqs */
>-	synchronize_irq(dev_priv->drm.irq);
>+	intel_synchronize_irq(dev_priv);
> }
> 
>-static void cherryview_irq_reset(struct drm_device *dev)
>+static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 
> 	I915_WRITE(GEN8_MASTER_IRQ, 0);
>@@ -3950,9 +3972,8 @@
> 	__bxt_hpd_detection_setup(dev_priv, enabled_irqs);
> }
> 
>-static void ibx_irq_postinstall(struct drm_device *dev)
>+static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	u32 mask;
> 
> 	if (HAS_PCH_NOP(dev_priv))
>@@ -3975,9 +3996,8 @@
> 		spt_hpd_detection_setup(dev_priv);
> }
> 
>-static void gen5_gt_irq_postinstall(struct drm_device *dev)
>+static void gen5_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 	u32 pm_irqs, gt_irqs;
> 
>@@ -4006,17 +4026,16 @@
> 		 */
> 		if (HAS_ENGINE(dev_priv, VECS0)) {
> 			pm_irqs |= PM_VEBOX_USER_INTERRUPT;
>-			dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
>+			dev_priv->gt.pm_ier |= PM_VEBOX_USER_INTERRUPT;
> 		}
> 
>-		dev_priv->pm_imr = 0xffffffff;
>-		GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->pm_imr, pm_irqs);
>+		dev_priv->gt.pm_imr = 0xffffffff;
>+		GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->gt.pm_imr, pm_irqs);
> 	}
> }
> 
>-static int ironlake_irq_postinstall(struct drm_device *dev)
>+static void ironlake_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 	u32 display_mask, extra_mask;
> 
>@@ -4043,16 +4062,16 @@
> 
> 	dev_priv->irq_mask = ~display_mask;
> 
>-	ibx_irq_pre_postinstall(dev);
>+	ibx_irq_pre_postinstall(dev_priv);
> 
> 	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
> 		      display_mask | extra_mask);
> 
>-	gen5_gt_irq_postinstall(dev);
>+	gen5_gt_irq_postinstall(dev_priv);
> 
> 	ilk_hpd_detection_setup(dev_priv);
> 
>-	ibx_irq_postinstall(dev);
>+	ibx_irq_postinstall(dev_priv);
> 
> 	if (IS_IRONLAKE_M(dev_priv)) {
> 		/* Enable PCU event interrupts
>@@ -4064,8 +4083,6 @@
> 		ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
> 		spin_unlock_irq(&dev_priv->irq_lock);
> 	}
>-
>-	return 0;
> }
> 
> void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
>@@ -4097,11 +4114,9 @@
> }
> 
> 
>-static int valleyview_irq_postinstall(struct drm_device *dev)
>+static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>-
>-	gen5_gt_irq_postinstall(dev);
>+	gen5_gt_irq_postinstall(dev_priv);
> 
> 	spin_lock_irq(&dev_priv->irq_lock);
> 	if (dev_priv->display_irqs_enabled)
>@@ -4110,13 +4125,12 @@
> 
> 	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
> 	POSTING_READ(VLV_MASTER_IER);
>-
>-	return 0;
> }
> 
>-static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
>+static void gen8_gt_irq_postinstall(struct drm_i915_private *i915)
> {
>-	struct intel_uncore *uncore = &dev_priv->uncore;
>+	struct intel_gt *gt = &i915->gt;
>+	struct intel_uncore *uncore = gt->uncore;
> 
> 	/* These are interrupts we'll toggle with the ring mask register */
> 	u32 gt_interrupts[] = {
>@@ -4136,15 +4150,15 @@
> 		 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)
> 	};
> 
>-	dev_priv->pm_ier = 0x0;
>-	dev_priv->pm_imr = ~dev_priv->pm_ier;
>+	gt->pm_ier = 0x0;
>+	gt->pm_imr = ~gt->pm_ier;
> 	GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
> 	GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
> 	/*
> 	 * RPS interrupts will get enabled/disabled on demand when RPS itself
> 	 * is enabled/disabled. Same wil be the case for GuC interrupts.
> 	 */
>-	GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
>+	GEN8_IRQ_INIT_NDX(uncore, GT, 2, gt->pm_imr, gt->pm_ier);
> 	GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
> }
> 
>@@ -4218,58 +4232,56 @@
> 	}
> }
> 
>-static int gen8_irq_postinstall(struct drm_device *dev)
>+static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>-
> 	if (HAS_PCH_SPLIT(dev_priv))
>-		ibx_irq_pre_postinstall(dev);
>+		ibx_irq_pre_postinstall(dev_priv);
> 
> 	gen8_gt_irq_postinstall(dev_priv);
> 	gen8_de_irq_postinstall(dev_priv);
> 
> 	if (HAS_PCH_SPLIT(dev_priv))
>-		ibx_irq_postinstall(dev);
>+		ibx_irq_postinstall(dev_priv);
> 
> 	gen8_master_intr_enable(dev_priv->uncore.regs);
>-
>-	return 0;
> }
> 
>-static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
>+static void gen11_gt_irq_postinstall(struct intel_gt *gt)
> {
> 	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
>+	struct intel_uncore *uncore = gt->uncore;
>+	const u32 dmask = irqs << 16 | irqs;
>+	const u32 smask = irqs << 16;
> 
> 	BUILD_BUG_ON(irqs & 0xffff0000);
> 
> 	/* Enable RCS, BCS, VCS and VECS class interrupts. */
>-	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
>-	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  irqs << 16 | irqs);
>+	intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask);
>+	intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
> 
> 	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
>-	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~(irqs << 16));
>-	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~(irqs << 16));
>-	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~(irqs | irqs << 16));
>-	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~(irqs | irqs << 16));
>-	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~(irqs | irqs << 16));
>+	intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
>+	intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
>+	intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
>+	intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
>+	intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK, ~dmask);
> 
> 	/*
> 	 * RPS interrupts will get enabled/disabled on demand when RPS itself
> 	 * is enabled/disabled.
> 	 */
>-	dev_priv->pm_ier = 0x0;
>-	dev_priv->pm_imr = ~dev_priv->pm_ier;
>-	I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
>-	I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
>+	gt->pm_ier = 0x0;
>+	gt->pm_imr = ~gt->pm_ier;
>+	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
>+	intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
> 
> 	/* Same thing for GuC interrupts */
>-	I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
>-	I915_WRITE(GEN11_GUC_SG_INTR_MASK,  ~0);
>+	intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
>+	intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK,  ~0);
> }
> 
>-static void icp_irq_postinstall(struct drm_device *dev)
>+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	u32 mask = SDE_GMBUS_ICP;
> 
> 	WARN_ON(I915_READ(SDEIER) != 0);
>@@ -4282,32 +4294,27 @@
> 	icp_hpd_detection_setup(dev_priv);
> }
> 
>-static int gen11_irq_postinstall(struct drm_device *dev)
>+static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = dev->dev_private;
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
> 
> 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>-		icp_irq_postinstall(dev);
>+		icp_irq_postinstall(dev_priv);
> 
>-	gen11_gt_irq_postinstall(dev_priv);
>+	gen11_gt_irq_postinstall(&dev_priv->gt);
> 	gen8_de_irq_postinstall(dev_priv);
> 
> 	GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
> 
> 	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
> 
>-	gen11_master_intr_enable(dev_priv->uncore.regs);
>+	gen11_master_intr_enable(uncore->regs);
> 	POSTING_READ(GEN11_GFX_MSTR_IRQ);
>-
>-	return 0;
> }
> 
>-static int cherryview_irq_postinstall(struct drm_device *dev)
>+static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>-
> 	gen8_gt_irq_postinstall(dev_priv);
> 
> 	spin_lock_irq(&dev_priv->irq_lock);
>@@ -4317,13 +4324,10 @@
> 
> 	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> 	POSTING_READ(GEN8_MASTER_IRQ);
>-
>-	return 0;
> }
> 
>-static void i8xx_irq_reset(struct drm_device *dev)
>+static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 
> 	i9xx_pipestat_irq_reset(dev_priv);
>@@ -4331,9 +4335,8 @@
> 	GEN2_IRQ_RESET(uncore);
> }
> 
>-static int i8xx_irq_postinstall(struct drm_device *dev)
>+static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 	u16 enable_mask;
> 
>@@ -4362,8 +4365,6 @@
> 	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
> 	i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
> 	spin_unlock_irq(&dev_priv->irq_lock);
>-
>-	return 0;
> }
> 
> static void i8xx_error_irq_ack(struct drm_i915_private *i915,
>@@ -4444,8 +4445,7 @@
> 
> static irqreturn_t i8xx_irq_handler(int irq, void *arg)
> {
>-	struct drm_device *dev = arg;
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = arg;
> 	irqreturn_t ret = IRQ_NONE;
> 
> 	if (!intel_irqs_enabled(dev_priv))
>@@ -4488,9 +4488,8 @@
> 	return ret;
> }
> 
>-static void i915_irq_reset(struct drm_device *dev)
>+static void i915_irq_reset(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 
> 	if (I915_HAS_HOTPLUG(dev_priv)) {
>@@ -4503,9 +4502,8 @@
> 	GEN3_IRQ_RESET(uncore, GEN2_);
> }
> 
>-static int i915_irq_postinstall(struct drm_device *dev)
>+static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 	u32 enable_mask;
> 
>@@ -4543,14 +4541,11 @@
> 	spin_unlock_irq(&dev_priv->irq_lock);
> 
> 	i915_enable_asle_pipestat(dev_priv);
>-
>-	return 0;
> }
> 
> static irqreturn_t i915_irq_handler(int irq, void *arg)
> {
>-	struct drm_device *dev = arg;
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = arg;
> 	irqreturn_t ret = IRQ_NONE;
> 
> 	if (!intel_irqs_enabled(dev_priv))
>@@ -4601,9 +4596,8 @@
> 	return ret;
> }
> 
>-static void i965_irq_reset(struct drm_device *dev)
>+static void i965_irq_reset(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 
> 	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
>@@ -4614,9 +4608,8 @@
> 	GEN3_IRQ_RESET(uncore, GEN2_);
> }
> 
>-static int i965_irq_postinstall(struct drm_device *dev)
>+static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>-	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct intel_uncore *uncore = &dev_priv->uncore;
> 	u32 enable_mask;
> 	u32 error_mask;
>@@ -4666,8 +4659,6 @@
> 	spin_unlock_irq(&dev_priv->irq_lock);
> 
> 	i915_enable_asle_pipestat(dev_priv);
>-
>-	return 0;
> }
> 
> static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
>@@ -4697,8 +4688,7 @@
> 
> static irqreturn_t i965_irq_handler(int irq, void *arg)
> {
>-	struct drm_device *dev = arg;
>-	struct drm_i915_private *dev_priv = to_i915(dev);
>+	struct drm_i915_private *dev_priv = arg;
> 	irqreturn_t ret = IRQ_NONE;
> 
> 	if (!intel_irqs_enabled(dev_priv))
>@@ -4775,8 +4765,9 @@
> 	for (i = 0; i < MAX_L3_SLICES; ++i)
> 		dev_priv->l3_parity.remap_info[i] = NULL;
> 
>-	if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)
>-		dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
>+	/* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
>+	if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
>+		dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
> 
> 	/* Let's track the enabled rps events */
> 	if (IS_VALLEYVIEW(dev_priv))
>@@ -4805,11 +4796,6 @@
> 	if (INTEL_GEN(dev_priv) >= 8)
> 		rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
> 
>-	if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
>-		dev->driver->get_vblank_counter = g4x_get_vblank_counter;
>-	else if (INTEL_GEN(dev_priv) >= 3)
>-		dev->driver->get_vblank_counter = i915_get_vblank_counter;
>-
> 	dev->vblank_disable_immediate = true;
> 
> 	/* Most platforms treat the display irq block as an always-on
>@@ -4831,86 +4817,18 @@
> 	 */
> 	dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
> 
>-	dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos;
>-	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
>-
>-	if (IS_CHERRYVIEW(dev_priv)) {
>-		dev->driver->irq_handler = cherryview_irq_handler;
>-		dev->driver->irq_preinstall = cherryview_irq_reset;
>-		dev->driver->irq_postinstall = cherryview_irq_postinstall;
>-		dev->driver->irq_uninstall = cherryview_irq_reset;
>-		dev->driver->enable_vblank = i965_enable_vblank;
>-		dev->driver->disable_vblank = i965_disable_vblank;
>-		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
>-	} else if (IS_VALLEYVIEW(dev_priv)) {
>-		dev->driver->irq_handler = valleyview_irq_handler;
>-		dev->driver->irq_preinstall = valleyview_irq_reset;
>-		dev->driver->irq_postinstall = valleyview_irq_postinstall;
>-		dev->driver->irq_uninstall = valleyview_irq_reset;
>-		dev->driver->enable_vblank = i965_enable_vblank;
>-		dev->driver->disable_vblank = i965_disable_vblank;
>-		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
>-	} else if (INTEL_GEN(dev_priv) >= 11) {
>-		dev->driver->irq_handler = gen11_irq_handler;
>-		dev->driver->irq_preinstall = gen11_irq_reset;
>-		dev->driver->irq_postinstall = gen11_irq_postinstall;
>-		dev->driver->irq_uninstall = gen11_irq_reset;
>-		dev->driver->enable_vblank = gen8_enable_vblank;
>-		dev->driver->disable_vblank = gen8_disable_vblank;
>-		dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
>-	} else if (INTEL_GEN(dev_priv) >= 8) {
>-		dev->driver->irq_handler = gen8_irq_handler;
>-		dev->driver->irq_preinstall = gen8_irq_reset;
>-		dev->driver->irq_postinstall = gen8_irq_postinstall;
>-		dev->driver->irq_uninstall = gen8_irq_reset;
>-		dev->driver->enable_vblank = gen8_enable_vblank;
>-		dev->driver->disable_vblank = gen8_disable_vblank;
>-		if (IS_GEN9_LP(dev_priv))
>+	if (HAS_GMCH(dev_priv)) {
>+		if (I915_HAS_HOTPLUG(dev_priv))
>+			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
>+	} else {
>+		if (INTEL_GEN(dev_priv) >= 11)
>+			dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
>+		else if (IS_GEN9_LP(dev_priv))
> 			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> 		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> 			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> 		else
> 			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
>-	} else if (HAS_PCH_SPLIT(dev_priv)) {
>-		dev->driver->irq_handler = ironlake_irq_handler;
>-		dev->driver->irq_preinstall = ironlake_irq_reset;
>-		dev->driver->irq_postinstall = ironlake_irq_postinstall;
>-		dev->driver->irq_uninstall = ironlake_irq_reset;
>-		dev->driver->enable_vblank = ironlake_enable_vblank;
>-		dev->driver->disable_vblank = ironlake_disable_vblank;
>-		dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
>-	} else {
>-		if (IS_GEN(dev_priv, 2)) {
>-			dev->driver->irq_preinstall = i8xx_irq_reset;
>-			dev->driver->irq_postinstall = i8xx_irq_postinstall;
>-			dev->driver->irq_handler = i8xx_irq_handler;
>-			dev->driver->irq_uninstall = i8xx_irq_reset;
>-			dev->driver->enable_vblank = i8xx_enable_vblank;
>-			dev->driver->disable_vblank = i8xx_disable_vblank;
>-		} else if (IS_I945GM(dev_priv)) {
>-			dev->driver->irq_preinstall = i915_irq_reset;
>-			dev->driver->irq_postinstall = i915_irq_postinstall;
>-			dev->driver->irq_uninstall = i915_irq_reset;
>-			dev->driver->irq_handler = i915_irq_handler;
>-			dev->driver->enable_vblank = i945gm_enable_vblank;
>-			dev->driver->disable_vblank = i945gm_disable_vblank;
>-		} else if (IS_GEN(dev_priv, 3)) {
>-			dev->driver->irq_preinstall = i915_irq_reset;
>-			dev->driver->irq_postinstall = i915_irq_postinstall;
>-			dev->driver->irq_uninstall = i915_irq_reset;
>-			dev->driver->irq_handler = i915_irq_handler;
>-			dev->driver->enable_vblank = i8xx_enable_vblank;
>-			dev->driver->disable_vblank = i8xx_disable_vblank;
>-		} else {
>-			dev->driver->irq_preinstall = i965_irq_reset;
>-			dev->driver->irq_postinstall = i965_irq_postinstall;
>-			dev->driver->irq_uninstall = i965_irq_reset;
>-			dev->driver->irq_handler = i965_irq_handler;
>-			dev->driver->enable_vblank = i965_enable_vblank;
>-			dev->driver->disable_vblank = i965_disable_vblank;
>-		}
>-		if (I915_HAS_HOTPLUG(dev_priv))
>-			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> 	}
> }
> 
>@@ -4931,6 +4849,75 @@
> 		kfree(i915->l3_parity.remap_info[i]);
> }
> 
>+static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
>+{
>+	if (HAS_GMCH(dev_priv)) {
>+		if (IS_CHERRYVIEW(dev_priv))
>+			return cherryview_irq_handler;
>+		else if (IS_VALLEYVIEW(dev_priv))
>+			return valleyview_irq_handler;
>+		else if (IS_GEN(dev_priv, 4))
>+			return i965_irq_handler;
>+		else if (IS_GEN(dev_priv, 3))
>+			return i915_irq_handler;
>+		else
>+			return i8xx_irq_handler;
>+	} else {
>+		if (INTEL_GEN(dev_priv) >= 11)
>+			return gen11_irq_handler;
>+		else if (INTEL_GEN(dev_priv) >= 8)
>+			return gen8_irq_handler;
>+		else
>+			return ironlake_irq_handler;
>+	}
>+}
>+
>+static void intel_irq_reset(struct drm_i915_private *dev_priv)
>+{
>+	if (HAS_GMCH(dev_priv)) {
>+		if (IS_CHERRYVIEW(dev_priv))
>+			cherryview_irq_reset(dev_priv);
>+		else if (IS_VALLEYVIEW(dev_priv))
>+			valleyview_irq_reset(dev_priv);
>+		else if (IS_GEN(dev_priv, 4))
>+			i965_irq_reset(dev_priv);
>+		else if (IS_GEN(dev_priv, 3))
>+			i915_irq_reset(dev_priv);
>+		else
>+			i8xx_irq_reset(dev_priv);
>+	} else {
>+		if (INTEL_GEN(dev_priv) >= 11)
>+			gen11_irq_reset(dev_priv);
>+		else if (INTEL_GEN(dev_priv) >= 8)
>+			gen8_irq_reset(dev_priv);
>+		else
>+			ironlake_irq_reset(dev_priv);
>+	}
>+}
>+
>+static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
>+{
>+	if (HAS_GMCH(dev_priv)) {
>+		if (IS_CHERRYVIEW(dev_priv))
>+			cherryview_irq_postinstall(dev_priv);
>+		else if (IS_VALLEYVIEW(dev_priv))
>+			valleyview_irq_postinstall(dev_priv);
>+		else if (IS_GEN(dev_priv, 4))
>+			i965_irq_postinstall(dev_priv);
>+		else if (IS_GEN(dev_priv, 3))
>+			i915_irq_postinstall(dev_priv);
>+		else
>+			i8xx_irq_postinstall(dev_priv);
>+	} else {
>+		if (INTEL_GEN(dev_priv) >= 11)
>+			gen11_irq_postinstall(dev_priv);
>+		else if (INTEL_GEN(dev_priv) >= 8)
>+			gen8_irq_postinstall(dev_priv);
>+		else
>+			ironlake_irq_postinstall(dev_priv);
>+	}
>+}
>+
> /**
>  * intel_irq_install - enables the hardware interrupt
>  * @dev_priv: i915 device instance
>@@ -4944,6 +4931,9 @@
>  */
> int intel_irq_install(struct drm_i915_private *dev_priv)
> {
>+	int irq = dev_priv->drm.pdev->irq;
>+	int ret;
>+
> 	/*
> 	 * We enable some interrupt sources in our postinstall hooks, so mark
> 	 * interrupts as enabled _before_ actually enabling them to avoid
>@@ -4951,7 +4941,20 @@
> 	 */
> 	dev_priv->runtime_pm.irqs_enabled = true;
> 
>-	return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
>+	dev_priv->drm.irq_enabled = true;
>+
>+	intel_irq_reset(dev_priv);
>+
>+	ret = request_irq(irq, intel_irq_handler(dev_priv),
>+			  IRQF_SHARED, DRIVER_NAME, dev_priv);
>+	if (ret < 0) {
>+		dev_priv->drm.irq_enabled = false;
>+		return ret;
>+	}
>+
>+	intel_irq_postinstall(dev_priv);
>+
>+	return ret;
> }
> 
> /**
>@@ -4963,7 +4966,23 @@
>  */
> void intel_irq_uninstall(struct drm_i915_private *dev_priv)
> {
>-	drm_irq_uninstall(&dev_priv->drm);
>+	int irq = dev_priv->drm.pdev->irq;
>+
>+	/*
>+	 * FIXME we can get called twice during driver load
>+	 * error handling due to intel_modeset_cleanup()
>+	 * calling us out of sequence. Would be nice if
>+	 * it didn't do that...
>+	 */
>+	if (!dev_priv->drm.irq_enabled)
>+		return;
>+
>+	dev_priv->drm.irq_enabled = false;
>+
>+	intel_irq_reset(dev_priv);
>+
>+	free_irq(irq, dev_priv);
>+
> 	intel_hpd_cancel_work(dev_priv);
> 	dev_priv->runtime_pm.irqs_enabled = false;
> }
>@@ -4977,9 +4996,9 @@
>  */
> void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
> {
>-	dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
>+	intel_irq_reset(dev_priv);
> 	dev_priv->runtime_pm.irqs_enabled = false;
>-	synchronize_irq(dev_priv->drm.irq);
>+	intel_synchronize_irq(dev_priv);
> }
> 
> /**
>@@ -4992,6 +5011,6 @@
> void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
> {
> 	dev_priv->runtime_pm.irqs_enabled = true;
>-	dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
>-	dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
>+	intel_irq_reset(dev_priv);
>+	intel_irq_postinstall(dev_priv);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_irq.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_irq.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_irq.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_irq.h	2019-08-31 15:01:12.034736184 -0500
>@@ -12,9 +12,10 @@
> 
> struct drm_i915_private;
> struct intel_crtc;
>+struct intel_guc;
> 
>-extern void intel_irq_init(struct drm_i915_private *dev_priv);
>-extern void intel_irq_fini(struct drm_i915_private *dev_priv);
>+void intel_irq_init(struct drm_i915_private *dev_priv);
>+void intel_irq_fini(struct drm_i915_private *dev_priv);
> int intel_irq_install(struct drm_i915_private *dev_priv);
> void intel_irq_uninstall(struct drm_i915_private *dev_priv);
> 
>@@ -77,8 +78,8 @@
> 
> void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
> void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
>-void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
>-void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
>+void gen6_mask_pm_irq(struct intel_gt *gt, u32 mask);
>+void gen6_unmask_pm_irq(struct intel_gt *gt, u32 mask);
> void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
> void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
> void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
>@@ -102,16 +103,40 @@
> 	return dev_priv->runtime_pm.irqs_enabled;
> }
> 
>+static inline void intel_synchronize_irq(struct drm_i915_private *i915)
>+{
>+	synchronize_irq(i915->drm.pdev->irq);
>+}
>+
> int intel_get_crtc_scanline(struct intel_crtc *crtc);
> void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> 				     u8 pipe_mask);
> void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
> 				     u8 pipe_mask);
>-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
>-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
>-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
>-void gen11_reset_guc_interrupts(struct drm_i915_private *i915);
>-void gen11_enable_guc_interrupts(struct drm_i915_private *i915);
>-void gen11_disable_guc_interrupts(struct drm_i915_private *i915);
>+void gen9_reset_guc_interrupts(struct intel_guc *guc);
>+void gen9_enable_guc_interrupts(struct intel_guc *guc);
>+void gen9_disable_guc_interrupts(struct intel_guc *guc);
>+void gen11_reset_guc_interrupts(struct intel_guc *guc);
>+void gen11_enable_guc_interrupts(struct intel_guc *guc);
>+void gen11_disable_guc_interrupts(struct intel_guc *guc);
>+
>+bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
>+			      bool in_vblank_irq, int *vpos, int *hpos,
>+			      ktime_t *stime, ktime_t *etime,
>+			      const struct drm_display_mode *mode);
>+
>+u32 i915_get_vblank_counter(struct drm_crtc *crtc);
>+u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
>+
>+int i8xx_enable_vblank(struct drm_crtc *crtc);
>+int i945gm_enable_vblank(struct drm_crtc *crtc);
>+int i965_enable_vblank(struct drm_crtc *crtc);
>+int ilk_enable_vblank(struct drm_crtc *crtc);
>+int bdw_enable_vblank(struct drm_crtc *crtc);
>+void i8xx_disable_vblank(struct drm_crtc *crtc);
>+void i945gm_disable_vblank(struct drm_crtc *crtc);
>+void i965_disable_vblank(struct drm_crtc *crtc);
>+void ilk_disable_vblank(struct drm_crtc *crtc);
>+void bdw_disable_vblank(struct drm_crtc *crtc);
> 
> #endif /* __I915_IRQ_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_bdw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_bdw.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_bdw.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_bdw.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,91 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_bdw.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2744), 0x00800000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x00000000 },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x00000000 },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x00000000 },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0x9840), 0x000000a0 },
>-	{ _MMIO(0x9888), 0x198b0000 },
>-	{ _MMIO(0x9888), 0x078b0066 },
>-	{ _MMIO(0x9888), 0x118b0000 },
>-	{ _MMIO(0x9888), 0x258b0000 },
>-	{ _MMIO(0x9888), 0x21850008 },
>-	{ _MMIO(0x9888), 0x0d834000 },
>-	{ _MMIO(0x9888), 0x07844000 },
>-	{ _MMIO(0x9888), 0x17804000 },
>-	{ _MMIO(0x9888), 0x21800000 },
>-	{ _MMIO(0x9888), 0x4f800000 },
>-	{ _MMIO(0x9888), 0x41800000 },
>-	{ _MMIO(0x9888), 0x31800000 },
>-	{ _MMIO(0x9840), 0x00000080 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"d6de6f55-e526-4f79-a6a6-d7315c09044e",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "d6de6f55-e526-4f79-a6a6-d7315c09044e";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_bdw.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_bdw.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_bdw.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_bdw.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_BDW_H__
>-#define __I915_OA_BDW_H__
>-
>-extern void i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_bxt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_bxt.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_bxt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_bxt.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,89 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_bxt.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2744), 0x00800000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x00000000 },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x00000000 },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x00000000 },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0x9840), 0x00000080 },
>-	{ _MMIO(0x9888), 0x19800000 },
>-	{ _MMIO(0x9888), 0x07800063 },
>-	{ _MMIO(0x9888), 0x11800000 },
>-	{ _MMIO(0x9888), 0x23810008 },
>-	{ _MMIO(0x9888), 0x1d950400 },
>-	{ _MMIO(0x9888), 0x0f922000 },
>-	{ _MMIO(0x9888), 0x1f908000 },
>-	{ _MMIO(0x9888), 0x37900000 },
>-	{ _MMIO(0x9888), 0x55900000 },
>-	{ _MMIO(0x9888), 0x47900000 },
>-	{ _MMIO(0x9888), 0x33900000 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"5ee72f5c-092f-421e-8b70-225f7c3e9612",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "5ee72f5c-092f-421e-8b70-225f7c3e9612";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_bxt.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_bxt.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_bxt.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_bxt.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_BXT_H__
>-#define __I915_OA_BXT_H__
>-
>-extern void i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_cflgt2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_cflgt2.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_cflgt2.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_cflgt2.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,90 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_cflgt2.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2744), 0x00800000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x00000000 },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x00000000 },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x00000000 },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0x9840), 0x00000080 },
>-	{ _MMIO(0x9888), 0x11810000 },
>-	{ _MMIO(0x9888), 0x07810013 },
>-	{ _MMIO(0x9888), 0x1f810000 },
>-	{ _MMIO(0x9888), 0x1d810000 },
>-	{ _MMIO(0x9888), 0x1b930040 },
>-	{ _MMIO(0x9888), 0x07e54000 },
>-	{ _MMIO(0x9888), 0x1f908000 },
>-	{ _MMIO(0x9888), 0x11900000 },
>-	{ _MMIO(0x9888), 0x37900000 },
>-	{ _MMIO(0x9888), 0x53900000 },
>-	{ _MMIO(0x9888), 0x45900000 },
>-	{ _MMIO(0x9888), 0x33900000 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_cflgt2(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"74fb4902-d3d3-4237-9e90-cbdc68d0a446",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "74fb4902-d3d3-4237-9e90-cbdc68d0a446";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_cflgt2.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_cflgt2.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_cflgt2.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_cflgt2.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_CFLGT2_H__
>-#define __I915_OA_CFLGT2_H__
>-
>-extern void i915_perf_load_test_config_cflgt2(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_cflgt3.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_cflgt3.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_cflgt3.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_cflgt3.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,90 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_cflgt3.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2744), 0x00800000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x00000000 },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x00000000 },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x00000000 },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0x9840), 0x00000080 },
>-	{ _MMIO(0x9888), 0x11810000 },
>-	{ _MMIO(0x9888), 0x07810013 },
>-	{ _MMIO(0x9888), 0x1f810000 },
>-	{ _MMIO(0x9888), 0x1d810000 },
>-	{ _MMIO(0x9888), 0x1b930040 },
>-	{ _MMIO(0x9888), 0x07e54000 },
>-	{ _MMIO(0x9888), 0x1f908000 },
>-	{ _MMIO(0x9888), 0x11900000 },
>-	{ _MMIO(0x9888), 0x37900000 },
>-	{ _MMIO(0x9888), 0x53900000 },
>-	{ _MMIO(0x9888), 0x45900000 },
>-	{ _MMIO(0x9888), 0x33900000 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_cflgt3(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"577e8e2c-3fa0-4875-8743-3538d585e3b0",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "577e8e2c-3fa0-4875-8743-3538d585e3b0";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_cflgt3.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_cflgt3.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_cflgt3.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_cflgt3.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_CFLGT3_H__
>-#define __I915_OA_CFLGT3_H__
>-
>-extern void i915_perf_load_test_config_cflgt3(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_chv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_chv.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_chv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_chv.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,90 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_chv.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2744), 0x00800000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x00000000 },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x00000000 },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x00000000 },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0x9840), 0x000000a0 },
>-	{ _MMIO(0x9888), 0x59800000 },
>-	{ _MMIO(0x9888), 0x59800001 },
>-	{ _MMIO(0x9888), 0x338b0000 },
>-	{ _MMIO(0x9888), 0x258b0066 },
>-	{ _MMIO(0x9888), 0x058b0000 },
>-	{ _MMIO(0x9888), 0x038b0000 },
>-	{ _MMIO(0x9888), 0x03844000 },
>-	{ _MMIO(0x9888), 0x47800080 },
>-	{ _MMIO(0x9888), 0x57800000 },
>-	{ _MMIO(0x1823a4), 0x00000000 },
>-	{ _MMIO(0x9888), 0x59800000 },
>-	{ _MMIO(0x9840), 0x00000080 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"4a534b07-cba3-414d-8d60-874830e883aa",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "4a534b07-cba3-414d-8d60-874830e883aa";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_chv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_chv.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_chv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_chv.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_CHV_H__
>-#define __I915_OA_CHV_H__
>-
>-extern void i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_cnl.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_cnl.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_cnl.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_cnl.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,102 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_cnl.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x0000ffff },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x0000ffff },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x0000ffff },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0xd04), 0x00000200 },
>-	{ _MMIO(0x9884), 0x00000007 },
>-	{ _MMIO(0x9888), 0x17060000 },
>-	{ _MMIO(0x9840), 0x00000000 },
>-	{ _MMIO(0x9884), 0x00000007 },
>-	{ _MMIO(0x9888), 0x13034000 },
>-	{ _MMIO(0x9884), 0x00000007 },
>-	{ _MMIO(0x9888), 0x07060066 },
>-	{ _MMIO(0x9884), 0x00000007 },
>-	{ _MMIO(0x9888), 0x05060000 },
>-	{ _MMIO(0x9884), 0x00000007 },
>-	{ _MMIO(0x9888), 0x0f080040 },
>-	{ _MMIO(0x9884), 0x00000007 },
>-	{ _MMIO(0x9888), 0x07091000 },
>-	{ _MMIO(0x9884), 0x00000007 },
>-	{ _MMIO(0x9888), 0x0f041000 },
>-	{ _MMIO(0x9884), 0x00000007 },
>-	{ _MMIO(0x9888), 0x1d004000 },
>-	{ _MMIO(0x9884), 0x00000007 },
>-	{ _MMIO(0x9888), 0x35000000 },
>-	{ _MMIO(0x9884), 0x00000007 },
>-	{ _MMIO(0x9888), 0x49000000 },
>-	{ _MMIO(0x9884), 0x00000007 },
>-	{ _MMIO(0x9888), 0x3d000000 },
>-	{ _MMIO(0x9884), 0x00000007 },
>-	{ _MMIO(0x9888), 0x31000000 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"db41edd4-d8e7-4730-ad11-b9a2d6833503",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "db41edd4-d8e7-4730-ad11-b9a2d6833503";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_cnl.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_cnl.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_cnl.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_cnl.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_CNL_H__
>-#define __I915_OA_CNL_H__
>-
>-extern void i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_glk.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_glk.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_glk.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_glk.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,89 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_glk.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2744), 0x00800000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x00000000 },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x00000000 },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x00000000 },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0x9840), 0x00000080 },
>-	{ _MMIO(0x9888), 0x19800000 },
>-	{ _MMIO(0x9888), 0x07800063 },
>-	{ _MMIO(0x9888), 0x11800000 },
>-	{ _MMIO(0x9888), 0x23810008 },
>-	{ _MMIO(0x9888), 0x1d950400 },
>-	{ _MMIO(0x9888), 0x0f922000 },
>-	{ _MMIO(0x9888), 0x1f908000 },
>-	{ _MMIO(0x9888), 0x37900000 },
>-	{ _MMIO(0x9888), 0x55900000 },
>-	{ _MMIO(0x9888), 0x47900000 },
>-	{ _MMIO(0x9888), 0x33900000 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"dd3fd789-e783-4204-8cd0-b671bbccb0cf",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "dd3fd789-e783-4204-8cd0-b671bbccb0cf";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_glk.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_glk.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_glk.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_glk.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_GLK_H__
>-#define __I915_OA_GLK_H__
>-
>-extern void i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_hsw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_hsw.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_hsw.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_hsw.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,119 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_hsw.h"
>-
>-static const struct i915_oa_reg b_counter_config_render_basic[] = {
>-	{ _MMIO(0x2724), 0x00800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2714), 0x00800000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_render_basic[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_render_basic[] = {
>-	{ _MMIO(0x9840), 0x00000080 },
>-	{ _MMIO(0x253a4), 0x01600000 },
>-	{ _MMIO(0x25440), 0x00100000 },
>-	{ _MMIO(0x25128), 0x00000000 },
>-	{ _MMIO(0x2691c), 0x00000800 },
>-	{ _MMIO(0x26aa0), 0x01500000 },
>-	{ _MMIO(0x26b9c), 0x00006000 },
>-	{ _MMIO(0x2791c), 0x00000800 },
>-	{ _MMIO(0x27aa0), 0x01500000 },
>-	{ _MMIO(0x27b9c), 0x00006000 },
>-	{ _MMIO(0x2641c), 0x00000400 },
>-	{ _MMIO(0x25380), 0x00000010 },
>-	{ _MMIO(0x2538c), 0x00000000 },
>-	{ _MMIO(0x25384), 0x0800aaaa },
>-	{ _MMIO(0x25400), 0x00000004 },
>-	{ _MMIO(0x2540c), 0x06029000 },
>-	{ _MMIO(0x25410), 0x00000002 },
>-	{ _MMIO(0x25404), 0x5c30ffff },
>-	{ _MMIO(0x25100), 0x00000016 },
>-	{ _MMIO(0x25110), 0x00000400 },
>-	{ _MMIO(0x25104), 0x00000000 },
>-	{ _MMIO(0x26804), 0x00001211 },
>-	{ _MMIO(0x26884), 0x00000100 },
>-	{ _MMIO(0x26900), 0x00000002 },
>-	{ _MMIO(0x26908), 0x00700000 },
>-	{ _MMIO(0x26904), 0x00000000 },
>-	{ _MMIO(0x26984), 0x00001022 },
>-	{ _MMIO(0x26a04), 0x00000011 },
>-	{ _MMIO(0x26a80), 0x00000006 },
>-	{ _MMIO(0x26a88), 0x00000c02 },
>-	{ _MMIO(0x26a84), 0x00000000 },
>-	{ _MMIO(0x26b04), 0x00001000 },
>-	{ _MMIO(0x26b80), 0x00000002 },
>-	{ _MMIO(0x26b8c), 0x00000007 },
>-	{ _MMIO(0x26b84), 0x00000000 },
>-	{ _MMIO(0x27804), 0x00004844 },
>-	{ _MMIO(0x27884), 0x00000400 },
>-	{ _MMIO(0x27900), 0x00000002 },
>-	{ _MMIO(0x27908), 0x0e000000 },
>-	{ _MMIO(0x27904), 0x00000000 },
>-	{ _MMIO(0x27984), 0x00004088 },
>-	{ _MMIO(0x27a04), 0x00000044 },
>-	{ _MMIO(0x27a80), 0x00000006 },
>-	{ _MMIO(0x27a88), 0x00018040 },
>-	{ _MMIO(0x27a84), 0x00000000 },
>-	{ _MMIO(0x27b04), 0x00004000 },
>-	{ _MMIO(0x27b80), 0x00000002 },
>-	{ _MMIO(0x27b8c), 0x000000e0 },
>-	{ _MMIO(0x27b84), 0x00000000 },
>-	{ _MMIO(0x26104), 0x00002222 },
>-	{ _MMIO(0x26184), 0x0c006666 },
>-	{ _MMIO(0x26284), 0x04000000 },
>-	{ _MMIO(0x26304), 0x04000000 },
>-	{ _MMIO(0x26400), 0x00000002 },
>-	{ _MMIO(0x26410), 0x000000a0 },
>-	{ _MMIO(0x26404), 0x00000000 },
>-	{ _MMIO(0x25420), 0x04108020 },
>-	{ _MMIO(0x25424), 0x1284a420 },
>-	{ _MMIO(0x2541c), 0x00000000 },
>-	{ _MMIO(0x25428), 0x00042049 },
>-};
>-
>-static ssize_t
>-show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"403d8832-1a27-4aa6-a64e-f5389ce7b212",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_render_basic;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_render_basic);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_render_basic;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_render_basic);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_render_basic;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_render_basic);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "403d8832-1a27-4aa6-a64e-f5389ce7b212";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_render_basic_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_hsw.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_hsw.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_hsw.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_hsw.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_HSW_H__
>-#define __I915_OA_HSW_H__
>-
>-extern void i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_icl.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_icl.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_icl.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_icl.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,99 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_icl.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x0000ffff },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x0000ffff },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x0000ffff },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0xd04), 0x00000200 },
>-	{ _MMIO(0x9840), 0x00000000 },
>-	{ _MMIO(0x9884), 0x00000000 },
>-	{ _MMIO(0x9888), 0x10060000 },
>-	{ _MMIO(0x9888), 0x22060000 },
>-	{ _MMIO(0x9888), 0x16060000 },
>-	{ _MMIO(0x9888), 0x24060000 },
>-	{ _MMIO(0x9888), 0x18060000 },
>-	{ _MMIO(0x9888), 0x1a060000 },
>-	{ _MMIO(0x9888), 0x12060000 },
>-	{ _MMIO(0x9888), 0x14060000 },
>-	{ _MMIO(0x9888), 0x10060000 },
>-	{ _MMIO(0x9888), 0x22060000 },
>-	{ _MMIO(0x9884), 0x00000003 },
>-	{ _MMIO(0x9888), 0x16130000 },
>-	{ _MMIO(0x9888), 0x24000001 },
>-	{ _MMIO(0x9888), 0x0e130056 },
>-	{ _MMIO(0x9888), 0x10130000 },
>-	{ _MMIO(0x9888), 0x1a130000 },
>-	{ _MMIO(0x9888), 0x541f0001 },
>-	{ _MMIO(0x9888), 0x181f0000 },
>-	{ _MMIO(0x9888), 0x4c1f0000 },
>-	{ _MMIO(0x9888), 0x301f0000 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_icl(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"a291665e-244b-4b76-9b9a-01de9d3c8068",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "a291665e-244b-4b76-9b9a-01de9d3c8068";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_icl.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_icl.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_icl.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_icl.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_ICL_H__
>-#define __I915_OA_ICL_H__
>-
>-extern void i915_perf_load_test_config_icl(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_kblgt2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_kblgt2.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_kblgt2.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_kblgt2.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,90 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_kblgt2.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2744), 0x00800000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x00000000 },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x00000000 },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x00000000 },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0x9840), 0x00000080 },
>-	{ _MMIO(0x9888), 0x11810000 },
>-	{ _MMIO(0x9888), 0x07810013 },
>-	{ _MMIO(0x9888), 0x1f810000 },
>-	{ _MMIO(0x9888), 0x1d810000 },
>-	{ _MMIO(0x9888), 0x1b930040 },
>-	{ _MMIO(0x9888), 0x07e54000 },
>-	{ _MMIO(0x9888), 0x1f908000 },
>-	{ _MMIO(0x9888), 0x11900000 },
>-	{ _MMIO(0x9888), 0x37900000 },
>-	{ _MMIO(0x9888), 0x53900000 },
>-	{ _MMIO(0x9888), 0x45900000 },
>-	{ _MMIO(0x9888), 0x33900000 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"baa3c7e4-52b6-4b85-801e-465a94b746dd",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "baa3c7e4-52b6-4b85-801e-465a94b746dd";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_kblgt2.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_kblgt2.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_kblgt2.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_kblgt2.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_KBLGT2_H__
>-#define __I915_OA_KBLGT2_H__
>-
>-extern void i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_kblgt3.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_kblgt3.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_kblgt3.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_kblgt3.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,90 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_kblgt3.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2744), 0x00800000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x00000000 },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x00000000 },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x00000000 },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0x9840), 0x00000080 },
>-	{ _MMIO(0x9888), 0x11810000 },
>-	{ _MMIO(0x9888), 0x07810013 },
>-	{ _MMIO(0x9888), 0x1f810000 },
>-	{ _MMIO(0x9888), 0x1d810000 },
>-	{ _MMIO(0x9888), 0x1b930040 },
>-	{ _MMIO(0x9888), 0x07e54000 },
>-	{ _MMIO(0x9888), 0x1f908000 },
>-	{ _MMIO(0x9888), 0x11900000 },
>-	{ _MMIO(0x9888), 0x37900000 },
>-	{ _MMIO(0x9888), 0x53900000 },
>-	{ _MMIO(0x9888), 0x45900000 },
>-	{ _MMIO(0x9888), 0x33900000 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"f1792f32-6db2-4b50-b4b2-557128f1688d",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "f1792f32-6db2-4b50-b4b2-557128f1688d";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_kblgt3.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_kblgt3.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_kblgt3.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_kblgt3.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_KBLGT3_H__
>-#define __I915_OA_KBLGT3_H__
>-
>-extern void i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_sklgt2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_sklgt2.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_sklgt2.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_sklgt2.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,89 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_sklgt2.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x00000000 },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x00000000 },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x00000000 },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0x9840), 0x00000080 },
>-	{ _MMIO(0x9888), 0x11810000 },
>-	{ _MMIO(0x9888), 0x07810016 },
>-	{ _MMIO(0x9888), 0x1f810000 },
>-	{ _MMIO(0x9888), 0x1d810000 },
>-	{ _MMIO(0x9888), 0x1b930040 },
>-	{ _MMIO(0x9888), 0x07e54000 },
>-	{ _MMIO(0x9888), 0x1f908000 },
>-	{ _MMIO(0x9888), 0x11900000 },
>-	{ _MMIO(0x9888), 0x37900000 },
>-	{ _MMIO(0x9888), 0x53900000 },
>-	{ _MMIO(0x9888), 0x45900000 },
>-	{ _MMIO(0x9888), 0x33900000 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"1651949f-0ac0-4cb1-a06f-dafd74a407d1",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "1651949f-0ac0-4cb1-a06f-dafd74a407d1";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_sklgt2.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_sklgt2.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_sklgt2.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_sklgt2.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_SKLGT2_H__
>-#define __I915_OA_SKLGT2_H__
>-
>-extern void i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_sklgt3.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_sklgt3.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_sklgt3.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_sklgt3.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,90 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_sklgt3.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2744), 0x00800000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x00000000 },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x00000000 },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x00000000 },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0x9840), 0x00000080 },
>-	{ _MMIO(0x9888), 0x11810000 },
>-	{ _MMIO(0x9888), 0x07810013 },
>-	{ _MMIO(0x9888), 0x1f810000 },
>-	{ _MMIO(0x9888), 0x1d810000 },
>-	{ _MMIO(0x9888), 0x1b930040 },
>-	{ _MMIO(0x9888), 0x07e54000 },
>-	{ _MMIO(0x9888), 0x1f908000 },
>-	{ _MMIO(0x9888), 0x11900000 },
>-	{ _MMIO(0x9888), 0x37900000 },
>-	{ _MMIO(0x9888), 0x53900000 },
>-	{ _MMIO(0x9888), 0x45900000 },
>-	{ _MMIO(0x9888), 0x33900000 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"2b985803-d3c9-4629-8a4f-634bfecba0e8",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "2b985803-d3c9-4629-8a4f-634bfecba0e8";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_sklgt3.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_sklgt3.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_sklgt3.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_sklgt3.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_SKLGT3_H__
>-#define __I915_OA_SKLGT3_H__
>-
>-extern void i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_sklgt4.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_sklgt4.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_sklgt4.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_sklgt4.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,90 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#include <linux/sysfs.h>
>-
>-#include "i915_drv.h"
>-#include "i915_oa_sklgt4.h"
>-
>-static const struct i915_oa_reg b_counter_config_test_oa[] = {
>-	{ _MMIO(0x2740), 0x00000000 },
>-	{ _MMIO(0x2744), 0x00800000 },
>-	{ _MMIO(0x2714), 0xf0800000 },
>-	{ _MMIO(0x2710), 0x00000000 },
>-	{ _MMIO(0x2724), 0xf0800000 },
>-	{ _MMIO(0x2720), 0x00000000 },
>-	{ _MMIO(0x2770), 0x00000004 },
>-	{ _MMIO(0x2774), 0x00000000 },
>-	{ _MMIO(0x2778), 0x00000003 },
>-	{ _MMIO(0x277c), 0x00000000 },
>-	{ _MMIO(0x2780), 0x00000007 },
>-	{ _MMIO(0x2784), 0x00000000 },
>-	{ _MMIO(0x2788), 0x00100002 },
>-	{ _MMIO(0x278c), 0x0000fff7 },
>-	{ _MMIO(0x2790), 0x00100002 },
>-	{ _MMIO(0x2794), 0x0000ffcf },
>-	{ _MMIO(0x2798), 0x00100082 },
>-	{ _MMIO(0x279c), 0x0000ffef },
>-	{ _MMIO(0x27a0), 0x001000c2 },
>-	{ _MMIO(0x27a4), 0x0000ffe7 },
>-	{ _MMIO(0x27a8), 0x00100001 },
>-	{ _MMIO(0x27ac), 0x0000ffe7 },
>-};
>-
>-static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>-};
>-
>-static const struct i915_oa_reg mux_config_test_oa[] = {
>-	{ _MMIO(0x9840), 0x00000080 },
>-	{ _MMIO(0x9888), 0x11810000 },
>-	{ _MMIO(0x9888), 0x07810013 },
>-	{ _MMIO(0x9888), 0x1f810000 },
>-	{ _MMIO(0x9888), 0x1d810000 },
>-	{ _MMIO(0x9888), 0x1b930040 },
>-	{ _MMIO(0x9888), 0x07e54000 },
>-	{ _MMIO(0x9888), 0x1f908000 },
>-	{ _MMIO(0x9888), 0x11900000 },
>-	{ _MMIO(0x9888), 0x37900000 },
>-	{ _MMIO(0x9888), 0x53900000 },
>-	{ _MMIO(0x9888), 0x45900000 },
>-	{ _MMIO(0x9888), 0x33900000 },
>-};
>-
>-static ssize_t
>-show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>-{
>-	return sprintf(buf, "1\n");
>-}
>-
>-void
>-i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv)
>-{
>-	strlcpy(dev_priv->perf.oa.test_config.uuid,
>-		"882fa433-1f4a-4a67-a962-c741888fe5f5",
>-		sizeof(dev_priv->perf.oa.test_config.uuid));
>-	dev_priv->perf.oa.test_config.id = 1;
>-
>-	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>-	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>-	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>-	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric.name = "882fa433-1f4a-4a67-a962-c741888fe5f5";
>-	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>-
>-	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>-
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>-	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_sklgt4.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_sklgt4.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_oa_sklgt4.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_oa_sklgt4.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- *
>- * Autogenerated file by GPU Top : https://github.com/rib/gputop
>- * DO NOT EDIT manually!
>- */
>-
>-#ifndef __I915_OA_SKLGT4_H__
>-#define __I915_OA_SKLGT4_H__
>-
>-extern void i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_params.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_params.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_params.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_params.c	2019-08-31 15:01:12.034736184 -0500
>@@ -169,8 +169,9 @@
> 	"Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)");
> #endif
> 
>-i915_param_named(enable_dpcd_backlight, bool, 0600,
>-	"Enable support for DPCD backlight control (default:false)");
>+i915_param_named(enable_dpcd_backlight, int, 0600,
>+	"Enable support for DPCD backlight control"
>+	"(-1=use per-VBT LFP backlight type setting, 0=disabled [default], 1=enabled)");
> 
> #if IS_ENABLED(CONFIG_DRM_I915_GVT)
> i915_param_named(enable_gvt, bool, 0400,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_params.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_params.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_params.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_params.h	2019-08-31 15:01:12.034736184 -0500
>@@ -64,6 +64,7 @@
> 	param(int, reset, 2) \
> 	param(unsigned int, inject_load_failure, 0) \
> 	param(int, fastboot, -1) \
>+	param(int, enable_dpcd_backlight, 0) \
> 	param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE) \
> 	/* leave bools at the end to not create holes */ \
> 	param(bool, alpha_support, IS_ENABLED(CONFIG_DRM_I915_ALPHA_SUPPORT)) \
>@@ -76,7 +77,6 @@
> 	param(bool, verbose_state_checks, true) \
> 	param(bool, nuclear_pageflip, false) \
> 	param(bool, enable_dp_mst, true) \
>-	param(bool, enable_dpcd_backlight, false) \
> 	param(bool, enable_gvt, false)
> 
> #define MEMBER(T, member, ...) T member;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_pci.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_pci.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_pci.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_pci.c	2019-08-31 15:01:12.034736184 -0500
>@@ -595,7 +595,7 @@
> 	GEN9_DEFAULT_PAGE_SIZES, \
> 	.has_logical_ring_preemption = 1, \
> 	.display.has_csr = 1, \
>-	.has_guc = 1, \
>+	.has_gt_uc = 1, \
> 	.display.has_ipc = 1, \
> 	.ddb_size = 896
> 
>@@ -647,7 +647,7 @@
> 	.display.has_dp_mst = 1, \
> 	.has_logical_ring_contexts = 1, \
> 	.has_logical_ring_preemption = 1, \
>-	.has_guc = 1, \
>+	.has_gt_uc = 1, \
> 	.ppgtt_type = INTEL_PPGTT_FULL, \
> 	.ppgtt_size = 48, \
> 	.has_reset_engine = 1, \
>@@ -761,10 +761,40 @@
> 	GEN11_FEATURES,
> 	PLATFORM(INTEL_ELKHARTLAKE),
> 	.require_force_probe = 1,
>-	.engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
>+	.engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> 	.ppgtt_size = 36,
> };
> 
>+#define GEN12_FEATURES \
>+	GEN11_FEATURES, \
>+	GEN(12), \
>+	.pipe_offsets = { \
>+		[TRANSCODER_A] = PIPE_A_OFFSET, \
>+		[TRANSCODER_B] = PIPE_B_OFFSET, \
>+		[TRANSCODER_C] = PIPE_C_OFFSET, \
>+		[TRANSCODER_D] = PIPE_D_OFFSET, \
>+		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
>+		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
>+	}, \
>+	.trans_offsets = { \
>+		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
>+		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
>+		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
>+		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
>+		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
>+		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
>+	}
>+
>+static const struct intel_device_info intel_tigerlake_12_info = {
>+	GEN12_FEATURES,
>+	PLATFORM(INTEL_TIGERLAKE),
>+	.num_pipes = 4,
>+	.require_force_probe = 1,
>+	.display.has_modular_fia = 1,
>+	.engine_mask =
>+		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
>+};
>+
> #undef GEN
> #undef PLATFORM
> 
>@@ -836,6 +866,7 @@
> 	INTEL_CNL_IDS(&intel_cannonlake_info),
> 	INTEL_ICL_11_IDS(&intel_icelake_11_info),
> 	INTEL_EHL_IDS(&intel_elkhartlake_info),
>+	INTEL_TGL_12_IDS(&intel_tigerlake_12_info),
> 	{0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
>@@ -848,7 +879,7 @@
> 	if (!dev) /* driver load aborted, nothing to cleanup */
> 		return;
> 
>-	i915_driver_unload(dev);
>+	i915_driver_remove(dev);
> 	drm_dev_put(dev);
> 
> 	pci_set_drvdata(pdev, NULL);
>@@ -923,11 +954,11 @@
> 	if (vga_switcheroo_client_probe_defer(pdev))
> 		return -EPROBE_DEFER;
> 
>-	err = i915_driver_load(pdev, ent);
>+	err = i915_driver_probe(pdev, ent);
> 	if (err)
> 		return err;
> 
>-	if (i915_inject_load_failure()) {
>+	if (i915_inject_probe_failure()) {
> 		i915_pci_remove(pdev);
> 		return -ENODEV;
> 	}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_perf.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_perf.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_perf.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_perf.c	2019-08-31 15:01:12.034736184 -0500
>@@ -200,20 +200,20 @@
> #include "gt/intel_lrc_reg.h"
> 
> #include "i915_drv.h"
>-#include "i915_oa_hsw.h"
>-#include "i915_oa_bdw.h"
>-#include "i915_oa_chv.h"
>-#include "i915_oa_sklgt2.h"
>-#include "i915_oa_sklgt3.h"
>-#include "i915_oa_sklgt4.h"
>-#include "i915_oa_bxt.h"
>-#include "i915_oa_kblgt2.h"
>-#include "i915_oa_kblgt3.h"
>-#include "i915_oa_glk.h"
>-#include "i915_oa_cflgt2.h"
>-#include "i915_oa_cflgt3.h"
>-#include "i915_oa_cnl.h"
>-#include "i915_oa_icl.h"
>+#include "oa/i915_oa_hsw.h"
>+#include "oa/i915_oa_bdw.h"
>+#include "oa/i915_oa_chv.h"
>+#include "oa/i915_oa_sklgt2.h"
>+#include "oa/i915_oa_sklgt3.h"
>+#include "oa/i915_oa_sklgt4.h"
>+#include "oa/i915_oa_bxt.h"
>+#include "oa/i915_oa_kblgt2.h"
>+#include "oa/i915_oa_kblgt3.h"
>+#include "oa/i915_oa_glk.h"
>+#include "oa/i915_oa_cflgt2.h"
>+#include "oa/i915_oa_cflgt3.h"
>+#include "oa/i915_oa_cnl.h"
>+#include "oa/i915_oa_icl.h"
> 
> /* HW requires this to be a power of two, between 128k and 16M, though driver
>  * is currently generally designed assuming the largest 16M size is used such
>@@ -1634,6 +1634,27 @@
> 				      ~GT_NOA_ENABLE));
> }
> 
>+static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,
>+			      i915_reg_t reg)
>+{
>+	u32 mmio = i915_mmio_reg_offset(reg);
>+	int i;
>+
>+	/*
>+	 * This arbitrary default will select the 'EU FPU0 Pipeline
>+	 * Active' event. In the future it's anticipated that there
>+	 * will be an explicit 'No Event' we can select, but not yet...
>+	 */
>+	if (!oa_config)
>+		return 0;
>+
>+	for (i = 0; i < oa_config->flex_regs_len; i++) {
>+		if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
>+			return oa_config->flex_regs[i].value;
>+	}
>+
>+	return 0;
>+}
> /*
>  * NB: It must always remain pointer safe to run this even if the OA unit
>  * has been disabled.
>@@ -1667,33 +1688,138 @@
> 		GEN8_OA_COUNTER_RESUME);
> 
> 	for (i = 0; i < ARRAY_SIZE(flex_regs); i++) {
>-		u32 state_offset = ctx_flexeu0 + i * 2;
>-		u32 mmio = i915_mmio_reg_offset(flex_regs[i]);
>+		CTX_REG(reg_state, ctx_flexeu0 + i * 2, flex_regs[i],
>+			oa_config_flex_reg(oa_config, flex_regs[i]));
>+	}
> 
>-		/*
>-		 * This arbitrary default will select the 'EU FPU0 Pipeline
>-		 * Active' event. In the future it's anticipated that there
>-		 * will be an explicit 'No Event' we can select, but not yet...
>-		 */
>-		u32 value = 0;
>+	CTX_REG(reg_state,
>+		CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
>+		intel_sseu_make_rpcs(i915, &ce->sseu));
>+}
> 
>-		if (oa_config) {
>-			u32 j;
>+struct flex {
>+	i915_reg_t reg;
>+	u32 offset;
>+	u32 value;
>+};
> 
>-			for (j = 0; j < oa_config->flex_regs_len; j++) {
>-				if (i915_mmio_reg_offset(oa_config->flex_regs[j].addr) == mmio) {
>-					value = oa_config->flex_regs[j].value;
>-					break;
>-				}
>-			}
>-		}
>+static int
>+gen8_store_flex(struct i915_request *rq,
>+		struct intel_context *ce,
>+		const struct flex *flex, unsigned int count)
>+{
>+	u32 offset;
>+	u32 *cs;
>+
>+	cs = intel_ring_begin(rq, 4 * count);
>+	if (IS_ERR(cs))
>+		return PTR_ERR(cs);
>+
>+	offset = i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE;
>+	do {
>+		*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>+		*cs++ = offset + (flex->offset + 1) * sizeof(u32);
>+		*cs++ = 0;
>+		*cs++ = flex->value;
>+	} while (flex++, --count);
>+
>+	intel_ring_advance(rq, cs);
>+
>+	return 0;
>+}
>+
>+static int
>+gen8_load_flex(struct i915_request *rq,
>+	       struct intel_context *ce,
>+	       const struct flex *flex, unsigned int count)
>+{
>+	u32 *cs;
>+
>+	GEM_BUG_ON(!count || count > 63);
>+
>+	cs = intel_ring_begin(rq, 2 * count + 2);
>+	if (IS_ERR(cs))
>+		return PTR_ERR(cs);
>+
>+	*cs++ = MI_LOAD_REGISTER_IMM(count);
>+	do {
>+		*cs++ = i915_mmio_reg_offset(flex->reg);
>+		*cs++ = flex->value;
>+	} while (flex++, --count);
>+	*cs++ = MI_NOOP;
>+
>+	intel_ring_advance(rq, cs);
>+
>+	return 0;
>+}
>+
>+static int gen8_modify_context(struct intel_context *ce,
>+			       const struct flex *flex, unsigned int count)
>+{
>+	struct i915_request *rq;
>+	int err;
>+
>+	lockdep_assert_held(&ce->pin_mutex);
>+
>+	rq = i915_request_create(ce->engine->kernel_context);
>+	if (IS_ERR(rq))
>+		return PTR_ERR(rq);
>+
>+	/* Serialise with the remote context */
>+	err = intel_context_prepare_remote_request(ce, rq);
>+	if (err == 0)
>+		err = gen8_store_flex(rq, ce, flex, count);
>+
>+	i915_request_add(rq);
>+	return err;
>+}
>+
>+static int gen8_modify_self(struct intel_context *ce,
>+			    const struct flex *flex, unsigned int count)
>+{
>+	struct i915_request *rq;
>+	int err;
> 
>-		CTX_REG(reg_state, state_offset, flex_regs[i], value);
>+	rq = i915_request_create(ce);
>+	if (IS_ERR(rq))
>+		return PTR_ERR(rq);
>+
>+	err = gen8_load_flex(rq, ce, flex, count);
>+
>+	i915_request_add(rq);
>+	return err;
>+}
>+
>+static int gen8_configure_context(struct i915_gem_context *ctx,
>+				  struct flex *flex, unsigned int count)
>+{
>+	struct i915_gem_engines_iter it;
>+	struct intel_context *ce;
>+	int err = 0;
>+
>+	for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
>+		GEM_BUG_ON(ce == ce->engine->kernel_context);
>+
>+		if (ce->engine->class != RENDER_CLASS)
>+			continue;
>+
>+		err = intel_context_lock_pinned(ce);
>+		if (err)
>+			break;
>+
>+		flex->value = intel_sseu_make_rpcs(ctx->i915, &ce->sseu);
>+
>+		/* Otherwise OA settings will be set upon first use */
>+		if (intel_context_is_pinned(ce))
>+			err = gen8_modify_context(ce, flex, count);
>+
>+		intel_context_unlock_pinned(ce);
>+		if (err)
>+			break;
> 	}
>+	i915_gem_context_unlock_engines(ctx);
> 
>-	CTX_REG(reg_state,
>-		CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
>-		intel_sseu_make_rpcs(i915, &ce->sseu));
>+	return err;
> }
> 
> /*
>@@ -1720,15 +1846,42 @@
>  *
>  * Note: it's only the RCS/Render context that has any OA state.
>  */
>-static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
>+static int gen8_configure_all_contexts(struct drm_i915_private *i915,
> 				       const struct i915_oa_config *oa_config)
> {
>-	unsigned int map_type = i915_coherent_map_type(dev_priv);
>+	/* The MMIO offsets for Flex EU registers aren't contiguous */
>+	const u32 ctx_flexeu0 = i915->perf.oa.ctx_flexeu0_offset;
>+#define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N))
>+	struct flex regs[] = {
>+		{
>+			GEN8_R_PWR_CLK_STATE,
>+			CTX_R_PWR_CLK_STATE,
>+		},
>+		{
>+			GEN8_OACTXCONTROL,
>+			i915->perf.oa.ctx_oactxctrl_offset,
>+			((i915->perf.oa.period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
>+			 (i915->perf.oa.periodic ? GEN8_OA_TIMER_ENABLE : 0) |
>+			 GEN8_OA_COUNTER_RESUME)
>+		},
>+		{ EU_PERF_CNTL0, ctx_flexeuN(0) },
>+		{ EU_PERF_CNTL1, ctx_flexeuN(1) },
>+		{ EU_PERF_CNTL2, ctx_flexeuN(2) },
>+		{ EU_PERF_CNTL3, ctx_flexeuN(3) },
>+		{ EU_PERF_CNTL4, ctx_flexeuN(4) },
>+		{ EU_PERF_CNTL5, ctx_flexeuN(5) },
>+		{ EU_PERF_CNTL6, ctx_flexeuN(6) },
>+	};
>+#undef ctx_flexeuN
>+	struct intel_engine_cs *engine;
> 	struct i915_gem_context *ctx;
>-	struct i915_request *rq;
>-	int ret;
>+	enum intel_engine_id id;
>+	int i;
>+
>+	for (i = 2; i < ARRAY_SIZE(regs); i++)
>+		regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
> 
>-	lockdep_assert_held(&dev_priv->drm.struct_mutex);
>+	lockdep_assert_held(&i915->drm.struct_mutex);
> 
> 	/*
> 	 * The OA register config is setup through the context image. This image
>@@ -1740,58 +1893,41 @@
> 	 * this might leave small interval of time where the OA unit is
> 	 * configured at an invalid sampling period.
> 	 *
>-	 * So far the best way to work around this issue seems to be draining
>-	 * the GPU from any submitted work.
>+	 * Note that since we emit all requests from a single ring, there
>+	 * is still an implicit global barrier here that may cause a high
>+	 * priority context to wait for an otherwise independent low priority
>+	 * context. Contexts idle at the time of reconfiguration are not
>+	 * trapped behind the barrier.
> 	 */
>-	ret = i915_gem_wait_for_idle(dev_priv,
>-				     I915_WAIT_LOCKED,
>-				     MAX_SCHEDULE_TIMEOUT);
>-	if (ret)
>-		return ret;
>-
>-	/* Update all contexts now that we've stalled the submission. */
>-	list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
>-		struct i915_gem_engines_iter it;
>-		struct intel_context *ce;
>-
>-		for_each_gem_engine(ce,
>-				    i915_gem_context_lock_engines(ctx),
>-				    it) {
>-			u32 *regs;
>-
>-			if (ce->engine->class != RENDER_CLASS)
>-				continue;
>-
>-			/* OA settings will be set upon first use */
>-			if (!ce->state)
>-				continue;
>-
>-			regs = i915_gem_object_pin_map(ce->state->obj,
>-						       map_type);
>-			if (IS_ERR(regs)) {
>-				i915_gem_context_unlock_engines(ctx);
>-				return PTR_ERR(regs);
>-			}
>+	list_for_each_entry(ctx, &i915->contexts.list, link) {
>+		int err;
> 
>-			ce->state->obj->mm.dirty = true;
>-			regs += LRC_STATE_PN * PAGE_SIZE / sizeof(*regs);
>-
>-			gen8_update_reg_state_unlocked(ce, regs, oa_config);
>+		if (ctx == i915->kernel_context)
>+			continue;
> 
>-			i915_gem_object_unpin_map(ce->state->obj);
>-		}
>-		i915_gem_context_unlock_engines(ctx);
>+		err = gen8_configure_context(ctx, regs, ARRAY_SIZE(regs));
>+		if (err)
>+			return err;
> 	}
> 
> 	/*
>-	 * Apply the configuration by doing one context restore of the edited
>-	 * context image.
>-	 */
>-	rq = i915_request_create(dev_priv->engine[RCS0]->kernel_context);
>-	if (IS_ERR(rq))
>-		return PTR_ERR(rq);
>+	 * After updating all other contexts, we need to modify ourselves.
>+	 * If we don't modify the kernel_context, we do not get events while
>+	 * idle.
>+	 */
>+	for_each_engine(engine, i915, id) {
>+		struct intel_context *ce = engine->kernel_context;
>+		int err;
> 
>-	i915_request_add(rq);
>+		if (engine->class != RENDER_CLASS)
>+			continue;
>+
>+		regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu);
>+
>+		err = gen8_modify_self(ce, regs, ARRAY_SIZE(regs));
>+		if (err)
>+			return err;
>+	}
> 
> 	return 0;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_pmu.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_pmu.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_pmu.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_pmu.c	2019-08-31 15:01:12.035736184 -0500
>@@ -102,10 +102,8 @@
> 	/*
> 	 * Also there is software busyness tracking available we do not
> 	 * need the timer for I915_SAMPLE_BUSY counter.
>-	 *
>-	 * Use RCS as proxy for all engines.
> 	 */
>-	else if (intel_engine_supports_stats(i915->engine[RCS0]))
>+	else if (i915->caps.scheduler & I915_SCHEDULER_CAP_ENGINE_BUSY_STATS)
> 		enable &= ~BIT(I915_SAMPLE_BUSY);
> 
> 	/*
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_priolist_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_priolist_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_priolist_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_priolist_types.h	2019-08-31 15:01:12.035736184 -0500
>@@ -17,6 +17,16 @@
> 	I915_PRIORITY_NORMAL = I915_CONTEXT_DEFAULT_PRIORITY,
> 	I915_PRIORITY_MAX = I915_CONTEXT_MAX_USER_PRIORITY + 1,
> 
>+	/*
>+	 * Requests containing performance queries must not be preempted by
>+	 * another context. They get scheduled with their default priority and
>+	 * once they reach the execlist ports we ensure that they stick on the
>+	 * HW until finished by pretending that they have maximum priority,
>+	 * i.e. nothing can have higher priority and force us to usurp the
>+	 * active request.
>+	 */
>+	I915_PRIORITY_UNPREEMPTABLE = INT_MAX,
>+
> 	I915_PRIORITY_INVALID = INT_MIN
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_pvinfo.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_pvinfo.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_pvinfo.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_pvinfo.h	2019-08-31 15:01:12.035736184 -0500
>@@ -24,6 +24,8 @@
> #ifndef _I915_PVINFO_H_
> #define _I915_PVINFO_H_
> 
>+#include <linux/types.h>
>+
> /* The MMIO offset of the shared info between guest and host emulator */
> #define VGT_PVINFO_PAGE	0x78000
> #define VGT_PVINFO_SIZE	0x1000
>@@ -110,8 +112,9 @@
> 	u32  rsv7[0x200 - 24];    /* pad to one page */
> } __packed;
> 
>-#define vgtif_reg(x) \
>-	_MMIO((VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)))
>+#define vgtif_offset(x) (offsetof(struct vgt_if, x))
>+
>+#define vgtif_reg(x) _MMIO(VGT_PVINFO_PAGE + vgtif_offset(x))
> 
> /* vGPU display status to be used by the host side */
> #define VGT_DRV_DISPLAY_NOT_READY 0
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_reg.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_reg.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_reg.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_reg.h	2019-08-31 15:01:12.036736184 -0500
>@@ -242,6 +242,7 @@
> #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
> #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
> #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
>+#define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
> 
> /*
>  * Device info offset array based helpers for groups of registers with unevenly
>@@ -1793,19 +1794,21 @@
>  */
> #define _ICL_COMBOPHY_A			0x162000
> #define _ICL_COMBOPHY_B			0x6C000
>-#define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
>-					      _ICL_COMBOPHY_B)
>+#define _EHL_COMBOPHY_C			0x160000
>+#define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
>+					      _ICL_COMBOPHY_B, \
>+					      _EHL_COMBOPHY_C)
> 
> /* CNL/ICL Port CL_DW registers */
>-#define _ICL_PORT_CL_DW(dw, port)	(_ICL_COMBOPHY(port) + \
>+#define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
> 					 4 * (dw))
> 
> #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
>-#define ICL_PORT_CL_DW5(port)		_MMIO(_ICL_PORT_CL_DW(5, port))
>+#define ICL_PORT_CL_DW5(phy)		_MMIO(_ICL_PORT_CL_DW(5, phy))
> #define   CL_POWER_DOWN_ENABLE		(1 << 4)
> #define   SUS_CLOCK_CONFIG		(3 << 0)
> 
>-#define ICL_PORT_CL_DW10(port)		_MMIO(_ICL_PORT_CL_DW(10, port))
>+#define ICL_PORT_CL_DW10(phy)		_MMIO(_ICL_PORT_CL_DW(10, phy))
> #define  PG_SEQ_DELAY_OVERRIDE_MASK	(3 << 25)
> #define  PG_SEQ_DELAY_OVERRIDE_SHIFT	25
> #define  PG_SEQ_DELAY_OVERRIDE_ENABLE	(1 << 24)
>@@ -1820,23 +1823,23 @@
> #define  PWR_DOWN_LN_MASK		(0xf << 4)
> #define  PWR_DOWN_LN_SHIFT		4
> 
>-#define ICL_PORT_CL_DW12(port)		_MMIO(_ICL_PORT_CL_DW(12, port))
>+#define ICL_PORT_CL_DW12(phy)		_MMIO(_ICL_PORT_CL_DW(12, phy))
> #define   ICL_LANE_ENABLE_AUX		(1 << 0)
> 
> /* CNL/ICL Port COMP_DW registers */
> #define _ICL_PORT_COMP			0x100
>-#define _ICL_PORT_COMP_DW(dw, port)	(_ICL_COMBOPHY(port) + \
>+#define _ICL_PORT_COMP_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
> 					 _ICL_PORT_COMP + 4 * (dw))
> 
> #define CNL_PORT_COMP_DW0		_MMIO(0x162100)
>-#define ICL_PORT_COMP_DW0(port)		_MMIO(_ICL_PORT_COMP_DW(0, port))
>+#define ICL_PORT_COMP_DW0(phy)		_MMIO(_ICL_PORT_COMP_DW(0, phy))
> #define   COMP_INIT			(1 << 31)
> 
> #define CNL_PORT_COMP_DW1		_MMIO(0x162104)
>-#define ICL_PORT_COMP_DW1(port)		_MMIO(_ICL_PORT_COMP_DW(1, port))
>+#define ICL_PORT_COMP_DW1(phy)		_MMIO(_ICL_PORT_COMP_DW(1, phy))
> 
> #define CNL_PORT_COMP_DW3		_MMIO(0x16210c)
>-#define ICL_PORT_COMP_DW3(port)		_MMIO(_ICL_PORT_COMP_DW(3, port))
>+#define ICL_PORT_COMP_DW3(phy)		_MMIO(_ICL_PORT_COMP_DW(3, phy))
> #define   PROCESS_INFO_DOT_0		(0 << 26)
> #define   PROCESS_INFO_DOT_1		(1 << 26)
> #define   PROCESS_INFO_DOT_4		(2 << 26)
>@@ -1848,14 +1851,14 @@
> #define   VOLTAGE_INFO_MASK		(3 << 24)
> #define   VOLTAGE_INFO_SHIFT		24
> 
>-#define ICL_PORT_COMP_DW8(port)		_MMIO(_ICL_PORT_COMP_DW(8, port))
>+#define ICL_PORT_COMP_DW8(phy)		_MMIO(_ICL_PORT_COMP_DW(8, phy))
> #define   IREFGEN			(1 << 24)
> 
> #define CNL_PORT_COMP_DW9		_MMIO(0x162124)
>-#define ICL_PORT_COMP_DW9(port)		_MMIO(_ICL_PORT_COMP_DW(9, port))
>+#define ICL_PORT_COMP_DW9(phy)		_MMIO(_ICL_PORT_COMP_DW(9, phy))
> 
> #define CNL_PORT_COMP_DW10		_MMIO(0x162128)
>-#define ICL_PORT_COMP_DW10(port)	_MMIO(_ICL_PORT_COMP_DW(10, port))
>+#define ICL_PORT_COMP_DW10(phy)		_MMIO(_ICL_PORT_COMP_DW(10, phy))
> 
> /* CNL/ICL Port PCS registers */
> #define _CNL_PORT_PCS_DW1_GRP_AE	0x162304
>@@ -1868,14 +1871,14 @@
> #define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
> #define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
> #define _CNL_PORT_PCS_DW1_LN0_F		0x162804
>-#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO(_PICK(port, \
>+#define CNL_PORT_PCS_DW1_GRP(phy)	_MMIO(_PICK(phy, \
> 						    _CNL_PORT_PCS_DW1_GRP_AE, \
> 						    _CNL_PORT_PCS_DW1_GRP_B, \
> 						    _CNL_PORT_PCS_DW1_GRP_C, \
> 						    _CNL_PORT_PCS_DW1_GRP_D, \
> 						    _CNL_PORT_PCS_DW1_GRP_AE, \
> 						    _CNL_PORT_PCS_DW1_GRP_F))
>-#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \
>+#define CNL_PORT_PCS_DW1_LN0(phy)	_MMIO(_PICK(phy, \
> 						    _CNL_PORT_PCS_DW1_LN0_AE, \
> 						    _CNL_PORT_PCS_DW1_LN0_B, \
> 						    _CNL_PORT_PCS_DW1_LN0_C, \
>@@ -1886,16 +1889,18 @@
> #define _ICL_PORT_PCS_AUX		0x300
> #define _ICL_PORT_PCS_GRP		0x600
> #define _ICL_PORT_PCS_LN(ln)		(0x800 + (ln) * 0x100)
>-#define _ICL_PORT_PCS_DW_AUX(dw, port)	(_ICL_COMBOPHY(port) + \
>+#define _ICL_PORT_PCS_DW_AUX(dw, phy)	(_ICL_COMBOPHY(phy) + \
> 					 _ICL_PORT_PCS_AUX + 4 * (dw))
>-#define _ICL_PORT_PCS_DW_GRP(dw, port)	(_ICL_COMBOPHY(port) + \
>+#define _ICL_PORT_PCS_DW_GRP(dw, phy)	(_ICL_COMBOPHY(phy) + \
> 					 _ICL_PORT_PCS_GRP + 4 * (dw))
>-#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
>+#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
> 					  _ICL_PORT_PCS_LN(ln) + 4 * (dw))
>-#define ICL_PORT_PCS_DW1_AUX(port)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, port))
>-#define ICL_PORT_PCS_DW1_GRP(port)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
>-#define ICL_PORT_PCS_DW1_LN0(port)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
>+#define ICL_PORT_PCS_DW1_AUX(phy)	_MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
>+#define ICL_PORT_PCS_DW1_GRP(phy)	_MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
>+#define ICL_PORT_PCS_DW1_LN0(phy)	_MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
> #define   COMMON_KEEPER_EN		(1 << 26)
>+#define   LATENCY_OPTIM_MASK		(0x3 << 2)
>+#define   LATENCY_OPTIM_VAL(x)		((x) << 2)
> 
> /* CNL/ICL Port TX registers */
> #define _CNL_PORT_TX_AE_GRP_OFFSET		0x162340
>@@ -1929,18 +1934,18 @@
> #define _ICL_PORT_TX_GRP		0x680
> #define _ICL_PORT_TX_LN(ln)		(0x880 + (ln) * 0x100)
> 
>-#define _ICL_PORT_TX_DW_AUX(dw, port)	(_ICL_COMBOPHY(port) + \
>+#define _ICL_PORT_TX_DW_AUX(dw, phy)	(_ICL_COMBOPHY(phy) + \
> 					 _ICL_PORT_TX_AUX + 4 * (dw))
>-#define _ICL_PORT_TX_DW_GRP(dw, port)	(_ICL_COMBOPHY(port) + \
>+#define _ICL_PORT_TX_DW_GRP(dw, phy)	(_ICL_COMBOPHY(phy) + \
> 					 _ICL_PORT_TX_GRP + 4 * (dw))
>-#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
>+#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
> 					  _ICL_PORT_TX_LN(ln) + 4 * (dw))
> 
> #define CNL_PORT_TX_DW2_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(2, port))
> #define CNL_PORT_TX_DW2_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(2, port))
>-#define ICL_PORT_TX_DW2_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(2, port))
>-#define ICL_PORT_TX_DW2_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(2, port))
>-#define ICL_PORT_TX_DW2_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
>+#define ICL_PORT_TX_DW2_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
>+#define ICL_PORT_TX_DW2_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
>+#define ICL_PORT_TX_DW2_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
> #define   SWING_SEL_UPPER(x)		(((x) >> 3) << 15)
> #define   SWING_SEL_UPPER_MASK		(1 << 15)
> #define   SWING_SEL_LOWER(x)		(((x) & 0x7) << 11)
>@@ -1957,10 +1962,10 @@
> #define CNL_PORT_TX_DW4_LN(ln, port)   _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
> 					   ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
> 						    _CNL_PORT_TX_DW4_LN0_AE)))
>-#define ICL_PORT_TX_DW4_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(4, port))
>-#define ICL_PORT_TX_DW4_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(4, port))
>-#define ICL_PORT_TX_DW4_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, port))
>-#define ICL_PORT_TX_DW4_LN(ln, port)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, port))
>+#define ICL_PORT_TX_DW4_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
>+#define ICL_PORT_TX_DW4_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
>+#define ICL_PORT_TX_DW4_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
>+#define ICL_PORT_TX_DW4_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
> #define   LOADGEN_SELECT		(1 << 31)
> #define   POST_CURSOR_1(x)		((x) << 12)
> #define   POST_CURSOR_1_MASK		(0x3F << 12)
>@@ -1971,9 +1976,9 @@
> 
> #define CNL_PORT_TX_DW5_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(5, port))
> #define CNL_PORT_TX_DW5_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(5, port))
>-#define ICL_PORT_TX_DW5_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(5, port))
>-#define ICL_PORT_TX_DW5_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(5, port))
>-#define ICL_PORT_TX_DW5_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
>+#define ICL_PORT_TX_DW5_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
>+#define ICL_PORT_TX_DW5_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
>+#define ICL_PORT_TX_DW5_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
> #define   TX_TRAINING_EN		(1 << 31)
> #define   TAP2_DISABLE			(1 << 30)
> #define   TAP3_DISABLE			(1 << 29)
>@@ -1984,13 +1989,17 @@
> 
> #define CNL_PORT_TX_DW7_GRP(port)	_MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
> #define CNL_PORT_TX_DW7_LN0(port)	_MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
>-#define ICL_PORT_TX_DW7_AUX(port)	_MMIO(_ICL_PORT_TX_DW_AUX(7, port))
>-#define ICL_PORT_TX_DW7_GRP(port)	_MMIO(_ICL_PORT_TX_DW_GRP(7, port))
>-#define ICL_PORT_TX_DW7_LN0(port)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
>-#define ICL_PORT_TX_DW7_LN(ln, port)	_MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
>+#define ICL_PORT_TX_DW7_AUX(phy)	_MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
>+#define ICL_PORT_TX_DW7_GRP(phy)	_MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
>+#define ICL_PORT_TX_DW7_LN0(phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
>+#define ICL_PORT_TX_DW7_LN(ln, phy)	_MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
> #define   N_SCALAR(x)			((x) << 24)
> #define   N_SCALAR_MASK			(0x7F << 24)
> 
>+#define _ICL_DPHY_CHKN_REG			0x194
>+#define ICL_DPHY_CHKN(port)			_MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
>+#define   ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP	REG_BIT(7)
>+
> #define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \
> 	_MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
> 
>@@ -2195,9 +2204,13 @@
> #define   DW6_OLDO_DYN_PWR_DOWN_EN	(1 << 28)
> 
> #define FIA1_BASE			0x163000
>+#define FIA2_BASE			0x16E000
>+#define FIA3_BASE			0x16F000
>+#define _FIA(fia)			_PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE)
>+#define _MMIO_FIA(fia, off)		_MMIO(_FIA(fia) + (off))
> 
> /* ICL PHY DFLEX registers */
>-#define PORT_TX_DFLEXDPMLE1		_MMIO(FIA1_BASE + 0x008C0)
>+#define PORT_TX_DFLEXDPMLE1(fia)	_MMIO_FIA((fia),  0x008C0)
> #define   DFLEXDPMLE1_DPMLETC_MASK(tc_port)	(0xf << (4 * (tc_port)))
> #define   DFLEXDPMLE1_DPMLETC_ML0(tc_port)	(1 << (4 * (tc_port)))
> #define   DFLEXDPMLE1_DPMLETC_ML1_0(tc_port)	(3 << (4 * (tc_port)))
>@@ -2513,13 +2526,19 @@
> #define   RING_WAIT_SEMAPHORE	(1 << 10) /* gen6+ */
> 
> #define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)
>-#define   RING_FORCE_TO_NONPRIV_RW		(0 << 28)    /* CFL+ & Gen11+ */
>-#define   RING_FORCE_TO_NONPRIV_RD		(1 << 28)
>-#define   RING_FORCE_TO_NONPRIV_WR		(2 << 28)
>+#define   RING_FORCE_TO_NONPRIV_ACCESS_RW	(0 << 28)    /* CFL+ & Gen11+ */
>+#define   RING_FORCE_TO_NONPRIV_ACCESS_RD	(1 << 28)
>+#define   RING_FORCE_TO_NONPRIV_ACCESS_WR	(2 << 28)
>+#define   RING_FORCE_TO_NONPRIV_ACCESS_INVALID	(3 << 28)
>+#define   RING_FORCE_TO_NONPRIV_ACCESS_MASK	(3 << 28)
> #define   RING_FORCE_TO_NONPRIV_RANGE_1		(0 << 0)     /* CFL+ & Gen11+ */
> #define   RING_FORCE_TO_NONPRIV_RANGE_4		(1 << 0)
> #define   RING_FORCE_TO_NONPRIV_RANGE_16	(2 << 0)
> #define   RING_FORCE_TO_NONPRIV_RANGE_64	(3 << 0)
>+#define   RING_FORCE_TO_NONPRIV_RANGE_MASK	(3 << 0)
>+#define   RING_FORCE_TO_NONPRIV_MASK_VALID	\
>+					(RING_FORCE_TO_NONPRIV_RANGE_MASK \
>+					| RING_FORCE_TO_NONPRIV_ACCESS_MASK)
> #define   RING_MAX_NONPRIV_SLOTS  12
> 
> #define GEN7_TLB_RD_ADDR	_MMIO(0x4700)
>@@ -3246,8 +3265,10 @@
> #define   GMBUS_PIN_10_TC2_ICP	10
> #define   GMBUS_PIN_11_TC3_ICP	11
> #define   GMBUS_PIN_12_TC4_ICP	12
>+#define   GMBUS_PIN_13_TC5_TGP	13
>+#define   GMBUS_PIN_14_TC6_TGP	14
> 
>-#define   GMBUS_NUM_PINS	13 /* including 0 */
>+#define   GMBUS_NUM_PINS	15 /* including 0 */
> #define GMBUS1			_MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
> #define   GMBUS_SW_CLR_INT	(1 << 31)
> #define   GMBUS_SW_RDY		(1 << 30)
>@@ -4209,6 +4230,7 @@
> #define TRANSCODER_B_OFFSET 0x61000
> #define TRANSCODER_C_OFFSET 0x62000
> #define CHV_TRANSCODER_C_OFFSET 0x63000
>+#define TRANSCODER_D_OFFSET 0x63000
> #define TRANSCODER_EDP_OFFSET 0x6f000
> #define TRANSCODER_DSI0_OFFSET	0x6b000
> #define TRANSCODER_DSI1_OFFSET	0x6b800
>@@ -5755,6 +5777,7 @@
> #define PIPE_A_OFFSET		0x70000
> #define PIPE_B_OFFSET		0x71000
> #define PIPE_C_OFFSET		0x72000
>+#define PIPE_D_OFFSET		0x73000
> #define CHV_PIPE_C_OFFSET	0x74000
> /*
>  * There's actually no pipe EDP. Some pipe registers have
>@@ -6284,6 +6307,7 @@
> #define _DSPATILEOFF				0x701A4 /* 965+ only */
> #define _DSPAOFFSET				0x701A4 /* HSW */
> #define _DSPASURFLIVE				0x701AC
>+#define _DSPAGAMC				0x701E0
> 
> #define DSPCNTR(plane)		_MMIO_PIPE2(plane, _DSPACNTR)
> #define DSPADDR(plane)		_MMIO_PIPE2(plane, _DSPAADDR)
>@@ -6295,6 +6319,7 @@
> #define DSPLINOFF(plane)	DSPADDR(plane)
> #define DSPOFFSET(plane)	_MMIO_PIPE2(plane, _DSPAOFFSET)
> #define DSPSURFLIVE(plane)	_MMIO_PIPE2(plane, _DSPASURFLIVE)
>+#define DSPGAMC(plane, i)	_MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
> 
> /* CHV pipe B blender and primary plane */
> #define _CHV_BLEND_A		0x60a00
>@@ -6397,6 +6422,7 @@
> #define _DVSAKEYMAXVAL		0x721a0
> #define _DVSATILEOFF		0x721a4
> #define _DVSASURFLIVE		0x721ac
>+#define _DVSAGAMC_G4X		0x721e0 /* g4x */
> #define _DVSASCALE		0x72204
> #define   DVS_SCALE_ENABLE	(1 << 31)
> #define   DVS_FILTER_MASK	(3 << 29)
>@@ -6405,7 +6431,8 @@
> #define   DVS_FILTER_SOFTENING	(2 << 29)
> #define   DVS_VERTICAL_OFFSET_HALF (1 << 28) /* must be enabled below */
> #define   DVS_VERTICAL_OFFSET_ENABLE (1 << 27)
>-#define _DVSAGAMC		0x72300
>+#define _DVSAGAMC_ILK		0x72300 /* ilk/snb */
>+#define _DVSAGAMCMAX_ILK	0x72340 /* ilk/snb */
> 
> #define _DVSBCNTR		0x73180
> #define _DVSBLINOFF		0x73184
>@@ -6418,8 +6445,10 @@
> #define _DVSBKEYMAXVAL		0x731a0
> #define _DVSBTILEOFF		0x731a4
> #define _DVSBSURFLIVE		0x731ac
>+#define _DVSBGAMC_G4X		0x731e0 /* g4x */
> #define _DVSBSCALE		0x73204
>-#define _DVSBGAMC		0x73300
>+#define _DVSBGAMC_ILK		0x73300 /* ilk/snb */
>+#define _DVSBGAMCMAX_ILK	0x73340 /* ilk/snb */
> 
> #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
> #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
>@@ -6433,6 +6462,9 @@
> #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
> #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
> #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
>+#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
>+#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
>+#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
> 
> #define _SPRA_CTL		0x70280
> #define   SPRITE_ENABLE			(1 << 31)
>@@ -6457,7 +6489,7 @@
> #define   SPRITE_YUV_ORDER_VYUY		(3 << 16)
> #define   SPRITE_ROTATE_180		(1 << 15)
> #define   SPRITE_TRICKLE_FEED_DISABLE	(1 << 14)
>-#define   SPRITE_INT_GAMMA_ENABLE	(1 << 13)
>+#define   SPRITE_INT_GAMMA_DISABLE	(1 << 13)
> #define   SPRITE_TILED			(1 << 10)
> #define   SPRITE_DEST_KEY		(1 << 2)
> #define _SPRA_LINOFF		0x70284
>@@ -6480,6 +6512,8 @@
> #define   SPRITE_VERTICAL_OFFSET_HALF	(1 << 28) /* must be enabled below */
> #define   SPRITE_VERTICAL_OFFSET_ENABLE	(1 << 27)
> #define _SPRA_GAMC		0x70400
>+#define _SPRA_GAMC16		0x70440
>+#define _SPRA_GAMC17		0x7044c
> 
> #define _SPRB_CTL		0x71280
> #define _SPRB_LINOFF		0x71284
>@@ -6495,6 +6529,8 @@
> #define _SPRB_SURFLIVE		0x712ac
> #define _SPRB_SCALE		0x71304
> #define _SPRB_GAMC		0x71400
>+#define _SPRB_GAMC16		0x71440
>+#define _SPRB_GAMC17		0x7144c
> 
> #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
> #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
>@@ -6508,7 +6544,9 @@
> #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
> #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
> #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
>-#define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
>+#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
>+#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
>+#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
> #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
> 
> #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
>@@ -6551,7 +6589,7 @@
> #define _SPACLRC1		(VLV_DISPLAY_BASE + 0x721d4)
> #define   SP_SH_SIN(x)			(((x) & 0x7ff) << 16) /* s4.7 */
> #define   SP_SH_COS(x)			(x) /* u3.7 */
>-#define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721f4)
>+#define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721e0)
> 
> #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
> #define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
>@@ -6566,10 +6604,12 @@
> #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
> #define _SPBCLRC0		(VLV_DISPLAY_BASE + 0x722d0)
> #define _SPBCLRC1		(VLV_DISPLAY_BASE + 0x722d4)
>-#define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722f4)
>+#define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722e0)
> 
>+#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
>+	_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
> #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
>-	_MMIO_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
>+	_MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
> 
> #define SPCNTR(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
> #define SPLINOFF(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
>@@ -6584,7 +6624,7 @@
> #define SPCONSTALPHA(pipe, plane_id)	_MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
> #define SPCLRC0(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
> #define SPCLRC1(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
>-#define SPGAMC(pipe, plane_id)		_MMIO_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC)
>+#define SPGAMC(pipe, plane_id, i)	_MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
> 
> /*
>  * CHV pipe B sprite CSC
>@@ -7317,16 +7357,6 @@
> #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
> #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
> 
>-#define GEN9_GUC_TO_HOST_INT_EVENT	(1 << 31)
>-#define GEN9_GUC_EXEC_ERROR_EVENT	(1 << 30)
>-#define GEN9_GUC_DISPLAY_EVENT		(1 << 29)
>-#define GEN9_GUC_SEMA_SIGNAL_EVENT	(1 << 28)
>-#define GEN9_GUC_IOMMU_MSG_EVENT	(1 << 27)
>-#define GEN9_GUC_DB_RING_EVENT		(1 << 26)
>-#define GEN9_GUC_DMA_DONE_EVENT		(1 << 25)
>-#define GEN9_GUC_FATAL_ERROR_EVENT	(1 << 24)
>-#define GEN9_GUC_NOTIFICATION_EVENT	(1 << 23)
>-
> #define GEN8_RCS_IRQ_SHIFT 0
> #define GEN8_BCS_IRQ_SHIFT 16
> #define GEN8_VCS0_IRQ_SHIFT 0  /* NB: VCS1 in bspec! */
>@@ -7606,6 +7636,7 @@
> #define SKL_DFSM_PIPE_A_DISABLE		(1 << 30)
> #define SKL_DFSM_PIPE_B_DISABLE		(1 << 21)
> #define SKL_DFSM_PIPE_C_DISABLE		(1 << 28)
>+#define TGL_DFSM_PIPE_D_DISABLE		(1 << 22)
> 
> #define SKL_DSSM				_MMIO(0x51004)
> #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz		(1 << 31)
>@@ -7690,6 +7721,9 @@
> #define GEN7_L3SQCREG4				_MMIO(0xb034)
> #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1 << 27)
> 
>+#define GEN11_SCRATCH2					_MMIO(0xb140)
>+#define  GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE	(1 << 19)
>+
> #define GEN8_L3SQCREG4				_MMIO(0xb118)
> #define  GEN11_LQSC_CLEAN_EVICT_DISABLE		(1 << 6)
> #define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
>@@ -9119,7 +9153,8 @@
> #define   GLK_PW_CTL_IDX_DDI_A			1
> #define   SKL_PW_CTL_IDX_MISC_IO		0
> 
>-/* ICL - power wells */
>+/* ICL/TGL - power wells */
>+#define   TGL_PW_CTL_IDX_PW_5			4
> #define   ICL_PW_CTL_IDX_PW_4			3
> #define   ICL_PW_CTL_IDX_PW_3			2
> #define   ICL_PW_CTL_IDX_PW_2			1
>@@ -9128,13 +9163,25 @@
> #define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)
> #define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)
> #define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
>+#define   TGL_PW_CTL_IDX_AUX_TBT6		14
>+#define   TGL_PW_CTL_IDX_AUX_TBT5		13
>+#define   TGL_PW_CTL_IDX_AUX_TBT4		12
> #define   ICL_PW_CTL_IDX_AUX_TBT4		11
>+#define   TGL_PW_CTL_IDX_AUX_TBT3		11
> #define   ICL_PW_CTL_IDX_AUX_TBT3		10
>+#define   TGL_PW_CTL_IDX_AUX_TBT2		10
> #define   ICL_PW_CTL_IDX_AUX_TBT2		9
>+#define   TGL_PW_CTL_IDX_AUX_TBT1		9
> #define   ICL_PW_CTL_IDX_AUX_TBT1		8
>+#define   TGL_PW_CTL_IDX_AUX_TC6		8
>+#define   TGL_PW_CTL_IDX_AUX_TC5		7
>+#define   TGL_PW_CTL_IDX_AUX_TC4		6
> #define   ICL_PW_CTL_IDX_AUX_F			5
>+#define   TGL_PW_CTL_IDX_AUX_TC3		5
> #define   ICL_PW_CTL_IDX_AUX_E			4
>+#define   TGL_PW_CTL_IDX_AUX_TC2		4
> #define   ICL_PW_CTL_IDX_AUX_D			3
>+#define   TGL_PW_CTL_IDX_AUX_TC1		3
> #define   ICL_PW_CTL_IDX_AUX_C			2
> #define   ICL_PW_CTL_IDX_AUX_B			1
> #define   ICL_PW_CTL_IDX_AUX_A			0
>@@ -9142,9 +9189,15 @@
> #define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)
> #define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)
> #define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)
>+#define   TGL_PW_CTL_IDX_DDI_TC6		8
>+#define   TGL_PW_CTL_IDX_DDI_TC5		7
>+#define   TGL_PW_CTL_IDX_DDI_TC4		6
> #define   ICL_PW_CTL_IDX_DDI_F			5
>+#define   TGL_PW_CTL_IDX_DDI_TC3		5
> #define   ICL_PW_CTL_IDX_DDI_E			4
>+#define   TGL_PW_CTL_IDX_DDI_TC2		4
> #define   ICL_PW_CTL_IDX_DDI_D			3
>+#define   TGL_PW_CTL_IDX_DDI_TC1		3
> #define   ICL_PW_CTL_IDX_DDI_C			2
> #define   ICL_PW_CTL_IDX_DDI_B			1
> #define   ICL_PW_CTL_IDX_DDI_A			0
>@@ -9197,9 +9250,11 @@
> #define _ICL_AUX_REG_IDX(pw_idx)	((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
> #define _ICL_AUX_ANAOVRD1_A		0x162398
> #define _ICL_AUX_ANAOVRD1_B		0x6C398
>+#define _TGL_AUX_ANAOVRD1_C		0x160398
> #define ICL_AUX_ANAOVRD1(pw_idx)	_MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
> 						    _ICL_AUX_ANAOVRD1_A, \
>-						    _ICL_AUX_ANAOVRD1_B))
>+						    _ICL_AUX_ANAOVRD1_B, \
>+						    _TGL_AUX_ANAOVRD1_C))
> #define   ICL_AUX_ANAOVRD1_LDO_BYPASS	(1 << 7)
> #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
> 
>@@ -9321,6 +9376,7 @@
> #define _TRANS_DDI_FUNC_CTL_A		0x60400
> #define _TRANS_DDI_FUNC_CTL_B		0x61400
> #define _TRANS_DDI_FUNC_CTL_C		0x62400
>+#define _TRANS_DDI_FUNC_CTL_D		0x63400
> #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
> #define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
> #define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
>@@ -9328,10 +9384,12 @@
> 
> #define  TRANS_DDI_FUNC_ENABLE		(1 << 31)
> /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
>-#define  TRANS_DDI_PORT_MASK		(7 << 28)
> #define  TRANS_DDI_PORT_SHIFT		28
>-#define  TRANS_DDI_SELECT_PORT(x)	((x) << 28)
>-#define  TRANS_DDI_PORT_NONE		(0 << 28)
>+#define  TGL_TRANS_DDI_PORT_SHIFT	27
>+#define  TRANS_DDI_PORT_MASK		(7 << TRANS_DDI_PORT_SHIFT)
>+#define  TGL_TRANS_DDI_PORT_MASK	(0xf << TGL_TRANS_DDI_PORT_SHIFT)
>+#define  TRANS_DDI_SELECT_PORT(x)	((x) << TRANS_DDI_PORT_SHIFT)
>+#define  TGL_TRANS_DDI_SELECT_PORT(x)	(((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
> #define  TRANS_DDI_MODE_SELECT_MASK	(7 << 24)
> #define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)
> #define  TRANS_DDI_MODE_SELECT_DVI	(1 << 24)
>@@ -9541,6 +9599,9 @@
> /* For each transcoder, we need to select the corresponding port clock */
> #define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)
> #define  TRANS_CLK_SEL_PORT(x)		(((x) + 1) << 29)
>+#define  TGL_TRANS_CLK_SEL_DISABLED	(0x0 << 28)
>+#define  TGL_TRANS_CLK_SEL_PORT(x)	(((x) + 1) << 28)
>+
> 
> #define CDCLK_FREQ			_MMIO(0x46200)
> 
>@@ -9672,17 +9733,22 @@
>  * CNL Clocks
>  */
> #define DPCLKA_CFGCR0				_MMIO(0x6C200)
>-#define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
> #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
> 						      (port) + 10))
>-#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))
>-#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
>-						      21 : (tc_port) + 12))
> #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
> 						(port) * 2)
> #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> #define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> 
>+#define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
>+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
>+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
>+						       (tc_port) + 12 : \
>+						       (tc_port) - PORT_TC4 + 21))
>+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
>+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
>+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
>+
> /* CNL PLL */
> #define DPLL0_ENABLE		0x46010
> #define DPLL1_ENABLE		0x46014
>@@ -9887,6 +9953,7 @@
> #define  DPLL_CFGCR1_PDIV_7		(8 << 2)
> #define  DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
> #define  DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
>+#define  TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
> #define CNL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
> 
> #define _ICL_DPLL0_CFGCR0		0x164000
>@@ -9899,6 +9966,22 @@
> #define ICL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
> 						  _ICL_DPLL1_CFGCR1)
> 
>+#define _TGL_DPLL0_CFGCR0		0x164284
>+#define _TGL_DPLL1_CFGCR0		0x16428C
>+/* TODO: add DPLL4 */
>+#define _TGL_TBTPLL_CFGCR0		0x16429C
>+#define TGL_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
>+						  _TGL_DPLL1_CFGCR0, \
>+						  _TGL_TBTPLL_CFGCR0)
>+
>+#define _TGL_DPLL0_CFGCR1		0x164288
>+#define _TGL_DPLL1_CFGCR1		0x164290
>+/* TODO: add DPLL4 */
>+#define _TGL_TBTPLL_CFGCR1		0x1642A0
>+#define TGL_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
>+						   _TGL_DPLL1_CFGCR1, \
>+						   _TGL_TBTPLL_CFGCR1)
>+
> /* BXT display engine PLL */
> #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
> #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
>@@ -11145,6 +11228,7 @@
> #define _ICL_PHY_MISC_B		0x64C04
> #define ICL_PHY_MISC(port)	_MMIO_PORT(port, _ICL_PHY_MISC_A, \
> 						 _ICL_PHY_MISC_B)
>+#define  ICL_PHY_MISC_MUX_DDID			(1 << 28)
> #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
> 
> /* Icelake Display Stream Compression Registers */
>@@ -11454,17 +11538,18 @@
> 						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> 						_ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
> 
>-#define PORT_TX_DFLEXDPSP			_MMIO(FIA1_BASE + 0x008A0)
>+#define PORT_TX_DFLEXDPSP(fia)			_MMIO_FIA((fia), 0x008A0)
>+#define   MODULAR_FIA_MASK			(1 << 4)
> #define   TC_LIVE_STATE_TBT(tc_port)		(1 << ((tc_port) * 8 + 6))
> #define   TC_LIVE_STATE_TC(tc_port)		(1 << ((tc_port) * 8 + 5))
> #define   DP_LANE_ASSIGNMENT_SHIFT(tc_port)	((tc_port) * 8)
> #define   DP_LANE_ASSIGNMENT_MASK(tc_port)	(0xf << ((tc_port) * 8))
> #define   DP_LANE_ASSIGNMENT(tc_port, x)	((x) << ((tc_port) * 8))
> 
>-#define PORT_TX_DFLEXDPPMS				_MMIO(FIA1_BASE + 0x00890)
>+#define PORT_TX_DFLEXDPPMS(fia)			_MMIO_FIA((fia), 0x00890)
> #define   DP_PHY_MODE_STATUS_COMPLETED(tc_port)		(1 << (tc_port))
> 
>-#define PORT_TX_DFLEXDPCSSS			_MMIO(FIA1_BASE + 0x00894)
>+#define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia), 0x00894)
> #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)		(1 << (tc_port))
> 
> #endif /* _I915_REG_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_request.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_request.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_request.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_request.c	2019-08-31 15:01:12.036736184 -0500
>@@ -119,6 +119,50 @@
> 	.release = i915_fence_release,
> };
> 
>+static void irq_execute_cb(struct irq_work *wrk)
>+{
>+	struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
>+
>+	i915_sw_fence_complete(cb->fence);
>+	kmem_cache_free(global.slab_execute_cbs, cb);
>+}
>+
>+static void irq_execute_cb_hook(struct irq_work *wrk)
>+{
>+	struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
>+
>+	cb->hook(container_of(cb->fence, struct i915_request, submit),
>+		 &cb->signal->fence);
>+	i915_request_put(cb->signal);
>+
>+	irq_execute_cb(wrk);
>+}
>+
>+static void __notify_execute_cb(struct i915_request *rq)
>+{
>+	struct execute_cb *cb;
>+
>+	lockdep_assert_held(&rq->lock);
>+
>+	if (list_empty(&rq->execute_cb))
>+		return;
>+
>+	list_for_each_entry(cb, &rq->execute_cb, link)
>+		irq_work_queue(&cb->work);
>+
>+	/*
>+	 * XXX Rollback on __i915_request_unsubmit()
>+	 *
>+	 * In the future, perhaps when we have an active time-slicing scheduler,
>+	 * it will be interesting to unsubmit parallel execution and remove
>+	 * busywaits from the GPU until their master is restarted. This is
>+	 * quite hairy, we have to carefully rollback the fence and do a
>+	 * preempt-to-idle cycle on the target engine, all the while the
>+	 * master execute_cb may refire.
>+	 */
>+	INIT_LIST_HEAD(&rq->execute_cb);
>+}
>+
> static inline void
> i915_request_remove_from_client(struct i915_request *request)
> {
>@@ -232,6 +276,12 @@
> 
> 	local_irq_disable();
> 
>+	/*
>+	 * We only loosely track inflight requests across preemption,
>+	 * and so we may find ourselves attempting to retire a _completed_
>+	 * request that we have removed from the HW and put back on a run
>+	 * queue.
>+	 */
> 	spin_lock(&rq->engine->active.lock);
> 	list_del(&rq->sched.link);
> 	spin_unlock(&rq->engine->active.lock);
>@@ -242,10 +292,15 @@
> 		dma_fence_signal_locked(&rq->fence);
> 	if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
> 		i915_request_cancel_breadcrumb(rq);
>-	if (rq->waitboost) {
>+	if (i915_request_has_waitboost(rq)) {
> 		GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters));
> 		atomic_dec(&rq->i915->gt_pm.rps.num_waiters);
> 	}
>+	if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags)) {
>+		set_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags);
>+		__notify_execute_cb(rq);
>+	}
>+	GEM_BUG_ON(!list_empty(&rq->execute_cb));
> 	spin_unlock(&rq->lock);
> 
> 	local_irq_enable();
>@@ -285,50 +340,6 @@
> 	} while (i915_request_retire(tmp) && tmp != rq);
> }
> 
>-static void irq_execute_cb(struct irq_work *wrk)
>-{
>-	struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
>-
>-	i915_sw_fence_complete(cb->fence);
>-	kmem_cache_free(global.slab_execute_cbs, cb);
>-}
>-
>-static void irq_execute_cb_hook(struct irq_work *wrk)
>-{
>-	struct execute_cb *cb = container_of(wrk, typeof(*cb), work);
>-
>-	cb->hook(container_of(cb->fence, struct i915_request, submit),
>-		 &cb->signal->fence);
>-	i915_request_put(cb->signal);
>-
>-	irq_execute_cb(wrk);
>-}
>-
>-static void __notify_execute_cb(struct i915_request *rq)
>-{
>-	struct execute_cb *cb;
>-
>-	lockdep_assert_held(&rq->lock);
>-
>-	if (list_empty(&rq->execute_cb))
>-		return;
>-
>-	list_for_each_entry(cb, &rq->execute_cb, link)
>-		irq_work_queue(&cb->work);
>-
>-	/*
>-	 * XXX Rollback on __i915_request_unsubmit()
>-	 *
>-	 * In the future, perhaps when we have an active time-slicing scheduler,
>-	 * it will be interesting to unsubmit parallel execution and remove
>-	 * busywaits from the GPU until their master is restarted. This is
>-	 * quite hairy, we have to carefully rollback the fence and do a
>-	 * preempt-to-idle cycle on the target engine, all the while the
>-	 * master execute_cb may refire.
>-	 */
>-	INIT_LIST_HEAD(&rq->execute_cb);
>-}
>-
> static int
> __i915_request_await_execution(struct i915_request *rq,
> 			       struct i915_request *signal,
>@@ -596,7 +607,7 @@
> struct i915_request *
> __i915_request_create(struct intel_context *ce, gfp_t gfp)
> {
>-	struct i915_timeline *tl = ce->ring->timeline;
>+	struct intel_timeline *tl = ce->ring->timeline;
> 	struct i915_request *rq;
> 	u32 seqno;
> 	int ret;
>@@ -645,7 +656,7 @@
> 		}
> 	}
> 
>-	ret = i915_timeline_get_seqno(tl, rq, &seqno);
>+	ret = intel_timeline_get_seqno(tl, rq, &seqno);
> 	if (ret)
> 		goto err_free;
> 
>@@ -673,7 +684,7 @@
> 	rq->file_priv = NULL;
> 	rq->batch = NULL;
> 	rq->capture_list = NULL;
>-	rq->waitboost = false;
>+	rq->flags = 0;
> 	rq->execution_mask = ALL_ENGINES;
> 
> 	INIT_LIST_HEAD(&rq->active_list);
>@@ -764,7 +775,7 @@
> 		return 0;
> 
> 	signal = list_prev_entry(signal, ring_link);
>-	if (i915_timeline_sync_is_later(rq->timeline, &signal->fence))
>+	if (intel_timeline_sync_is_later(rq->timeline, &signal->fence))
> 		return 0;
> 
> 	return i915_sw_fence_await_dma_fence(&rq->submit,
>@@ -818,7 +829,7 @@
> 		return err;
> 
> 	/* We need to pin the signaler's HWSP until we are finished reading. */
>-	err = i915_timeline_read_hwsp(from, to, &hwsp_offset);
>+	err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
> 	if (err)
> 		return err;
> 
>@@ -929,7 +940,7 @@
> 
> 		/* Squash repeated waits to the same timelines */
> 		if (fence->context != rq->i915->mm.unordered_timeline &&
>-		    i915_timeline_sync_is_later(rq->timeline, fence))
>+		    intel_timeline_sync_is_later(rq->timeline, fence))
> 			continue;
> 
> 		if (dma_fence_is_i915(fence))
>@@ -943,7 +954,7 @@
> 
> 		/* Record the latest fence used against each timeline */
> 		if (fence->context != rq->i915->mm.unordered_timeline)
>-			i915_timeline_sync_set(rq->timeline, fence);
>+			intel_timeline_sync_set(rq->timeline, fence);
> 	} while (--nchild);
> 
> 	return 0;
>@@ -1081,7 +1092,7 @@
> static struct i915_request *
> __i915_request_add_to_timeline(struct i915_request *rq)
> {
>-	struct i915_timeline *timeline = rq->timeline;
>+	struct intel_timeline *timeline = rq->timeline;
> 	struct i915_request *prev;
> 
> 	/*
>@@ -1390,8 +1401,7 @@
> 	 * serialise wait/reset with an explicit lock, we do want
> 	 * lockdep to detect potential dependency cycles.
> 	 */
>-	mutex_acquire(&rq->i915->gpu_error.wedge_mutex.dep_map,
>-		      0, 0, _THIS_IP_);
>+	mutex_acquire(&rq->engine->gt->reset.mutex.dep_map, 0, 0, _THIS_IP_);
> 
> 	/*
> 	 * Optimistic spin before touching IRQs.
>@@ -1447,8 +1457,10 @@
> 	for (;;) {
> 		set_current_state(state);
> 
>-		if (i915_request_completed(rq))
>+		if (i915_request_completed(rq)) {
>+			dma_fence_signal(&rq->fence);
> 			break;
>+		}
> 
> 		if (signal_pending_state(state, current)) {
> 			timeout = -ERESTARTSYS;
>@@ -1467,7 +1479,7 @@
> 	dma_fence_remove_callback(&rq->fence, &wait.cb);
> 
> out:
>-	mutex_release(&rq->i915->gpu_error.wedge_mutex.dep_map, 0, _THIS_IP_);
>+	mutex_release(&rq->engine->gt->reset.mutex.dep_map, 0, _THIS_IP_);
> 	trace_i915_request_wait_end(rq);
> 	return timeout;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_request.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_request.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_request.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_request.h	2019-08-31 15:01:12.037736184 -0500
>@@ -28,6 +28,7 @@
> #include <linux/dma-fence.h>
> #include <linux/lockdep.h>
> 
>+#include "gt/intel_context_types.h"
> #include "gt/intel_engine_types.h"
> 
> #include "i915_gem.h"
>@@ -40,8 +41,8 @@
> struct drm_file;
> struct drm_i915_gem_object;
> struct i915_request;
>-struct i915_timeline;
>-struct i915_timeline_cacheline;
>+struct intel_timeline;
>+struct intel_timeline_cacheline;
> 
> struct i915_capture_list {
> 	struct i915_capture_list *next;
>@@ -112,7 +113,7 @@
> 	struct intel_engine_cs *engine;
> 	struct intel_context *hw_context;
> 	struct intel_ring *ring;
>-	struct i915_timeline *timeline;
>+	struct intel_timeline *timeline;
> 	struct list_head signal_link;
> 
> 	/*
>@@ -175,7 +176,7 @@
> 	 * inside the timeline's HWSP vma, but it is only valid while this
> 	 * request has not completed and guarded by the timeline mutex.
> 	 */
>-	struct i915_timeline_cacheline *hwsp_cacheline;
>+	struct intel_timeline_cacheline *hwsp_cacheline;
> 
> 	/** Position in the ring of the start of the request */
> 	u32 head;
>@@ -215,7 +216,9 @@
> 	/** Time at which this request was emitted, in jiffies. */
> 	unsigned long emitted_jiffies;
> 
>-	bool waitboost;
>+	unsigned long flags;
>+#define I915_REQUEST_WAITBOOST BIT(0)
>+#define I915_REQUEST_NOPREEMPT BIT(1)
> 
> 	/** timeline->request entry for this request */
> 	struct list_head link;
>@@ -429,6 +432,17 @@
> 	rq->hwsp_seqno = (u32 *)&rq->fence.seqno; /* decouple from HWSP */
> }
> 
>+static inline bool i915_request_has_waitboost(const struct i915_request *rq)
>+{
>+	return rq->flags & I915_REQUEST_WAITBOOST;
>+}
>+
>+static inline bool i915_request_has_nopreempt(const struct i915_request *rq)
>+{
>+	/* Preemption should only be disabled very rarely */
>+	return unlikely(rq->flags & I915_REQUEST_NOPREEMPT);
>+}
>+
> bool i915_retire_requests(struct drm_i915_private *i915);
> 
> #endif /* I915_REQUEST_H */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_scheduler.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_scheduler.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_scheduler.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_scheduler.c	2019-08-31 15:01:12.037736184 -0500
>@@ -179,8 +179,7 @@
> 
> static void kick_submission(struct intel_engine_cs *engine, int prio)
> {
>-	const struct i915_request *inflight =
>-		port_request(engine->execlists.port);
>+	const struct i915_request *inflight = *engine->execlists.active;
> 
> 	/*
> 	 * If we are already the currently executing context, don't
>@@ -395,6 +394,7 @@
> 		list_add(&dep->wait_link, &signal->waiters_list);
> 		list_add(&dep->signal_link, &node->signalers_list);
> 		dep->signaler = signal;
>+		dep->waiter = node;
> 		dep->flags = flags;
> 
> 		/* Keep track of whether anyone on this chain has a semaphore */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_scheduler_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_scheduler_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_scheduler_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_scheduler_types.h	2019-08-31 15:01:12.037736184 -0500
>@@ -62,6 +62,7 @@
> 
> struct i915_dependency {
> 	struct i915_sched_node *signaler;
>+	struct i915_sched_node *waiter;
> 	struct list_head signal_link;
> 	struct list_head wait_link;
> 	struct list_head dfs_link;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_selftest.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_selftest.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_selftest.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_selftest.h	2019-08-31 15:01:12.037736184 -0500
>@@ -66,12 +66,37 @@
> 	const char *name;
> };
> 
>+int __i915_nop_setup(void *data);
>+int __i915_nop_teardown(int err, void *data);
>+
>+int __i915_live_setup(void *data);
>+int __i915_live_teardown(int err, void *data);
>+
>+int __intel_gt_live_setup(void *data);
>+int __intel_gt_live_teardown(int err, void *data);
>+
> int __i915_subtests(const char *caller,
>+		    int (*setup)(void *data),
>+		    int (*teardown)(int err, void *data),
> 		    const struct i915_subtest *st,
> 		    unsigned int count,
> 		    void *data);
> #define i915_subtests(T, data) \
>-	__i915_subtests(__func__, T, ARRAY_SIZE(T), data)
>+	__i915_subtests(__func__, \
>+			__i915_nop_setup, __i915_nop_teardown, \
>+			T, ARRAY_SIZE(T), data)
>+#define i915_live_subtests(T, data) ({ \
>+	typecheck(struct drm_i915_private *, data); \
>+	__i915_subtests(__func__, \
>+			__i915_live_setup, __i915_live_teardown, \
>+			T, ARRAY_SIZE(T), data); \
>+})
>+#define intel_gt_live_subtests(T, data) ({ \
>+	typecheck(struct intel_gt *, data); \
>+	__i915_subtests(__func__, \
>+			__intel_gt_live_setup, __intel_gt_live_teardown, \
>+			T, ARRAY_SIZE(T), data); \
>+})
> 
> #define SUBTEST(x) { x, #x }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_timeline.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_timeline.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_timeline.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_timeline.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,579 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2016-2018 Intel Corporation
>- */
>-
>-#include "i915_drv.h"
>-
>-#include "i915_active.h"
>-#include "i915_syncmap.h"
>-#include "i915_timeline.h"
>-
>-#define ptr_set_bit(ptr, bit) ((typeof(ptr))((unsigned long)(ptr) | BIT(bit)))
>-#define ptr_test_bit(ptr, bit) ((unsigned long)(ptr) & BIT(bit))
>-
>-struct i915_timeline_hwsp {
>-	struct i915_gt_timelines *gt;
>-	struct list_head free_link;
>-	struct i915_vma *vma;
>-	u64 free_bitmap;
>-};
>-
>-struct i915_timeline_cacheline {
>-	struct i915_active active;
>-	struct i915_timeline_hwsp *hwsp;
>-	void *vaddr;
>-#define CACHELINE_BITS 6
>-#define CACHELINE_FREE CACHELINE_BITS
>-};
>-
>-static inline struct drm_i915_private *
>-hwsp_to_i915(struct i915_timeline_hwsp *hwsp)
>-{
>-	return container_of(hwsp->gt, struct drm_i915_private, gt.timelines);
>-}
>-
>-static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
>-{
>-	struct drm_i915_gem_object *obj;
>-	struct i915_vma *vma;
>-
>-	obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
>-	if (IS_ERR(obj))
>-		return ERR_CAST(obj);
>-
>-	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
>-
>-	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
>-	if (IS_ERR(vma))
>-		i915_gem_object_put(obj);
>-
>-	return vma;
>-}
>-
>-static struct i915_vma *
>-hwsp_alloc(struct i915_timeline *timeline, unsigned int *cacheline)
>-{
>-	struct drm_i915_private *i915 = timeline->i915;
>-	struct i915_gt_timelines *gt = &i915->gt.timelines;
>-	struct i915_timeline_hwsp *hwsp;
>-
>-	BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
>-
>-	spin_lock_irq(&gt->hwsp_lock);
>-
>-	/* hwsp_free_list only contains HWSP that have available cachelines */
>-	hwsp = list_first_entry_or_null(&gt->hwsp_free_list,
>-					typeof(*hwsp), free_link);
>-	if (!hwsp) {
>-		struct i915_vma *vma;
>-
>-		spin_unlock_irq(&gt->hwsp_lock);
>-
>-		hwsp = kmalloc(sizeof(*hwsp), GFP_KERNEL);
>-		if (!hwsp)
>-			return ERR_PTR(-ENOMEM);
>-
>-		vma = __hwsp_alloc(i915);
>-		if (IS_ERR(vma)) {
>-			kfree(hwsp);
>-			return vma;
>-		}
>-
>-		vma->private = hwsp;
>-		hwsp->vma = vma;
>-		hwsp->free_bitmap = ~0ull;
>-		hwsp->gt = gt;
>-
>-		spin_lock_irq(&gt->hwsp_lock);
>-		list_add(&hwsp->free_link, &gt->hwsp_free_list);
>-	}
>-
>-	GEM_BUG_ON(!hwsp->free_bitmap);
>-	*cacheline = __ffs64(hwsp->free_bitmap);
>-	hwsp->free_bitmap &= ~BIT_ULL(*cacheline);
>-	if (!hwsp->free_bitmap)
>-		list_del(&hwsp->free_link);
>-
>-	spin_unlock_irq(&gt->hwsp_lock);
>-
>-	GEM_BUG_ON(hwsp->vma->private != hwsp);
>-	return hwsp->vma;
>-}
>-
>-static void __idle_hwsp_free(struct i915_timeline_hwsp *hwsp, int cacheline)
>-{
>-	struct i915_gt_timelines *gt = hwsp->gt;
>-	unsigned long flags;
>-
>-	spin_lock_irqsave(&gt->hwsp_lock, flags);
>-
>-	/* As a cacheline becomes available, publish the HWSP on the freelist */
>-	if (!hwsp->free_bitmap)
>-		list_add_tail(&hwsp->free_link, &gt->hwsp_free_list);
>-
>-	GEM_BUG_ON(cacheline >= BITS_PER_TYPE(hwsp->free_bitmap));
>-	hwsp->free_bitmap |= BIT_ULL(cacheline);
>-
>-	/* And if no one is left using it, give the page back to the system */
>-	if (hwsp->free_bitmap == ~0ull) {
>-		i915_vma_put(hwsp->vma);
>-		list_del(&hwsp->free_link);
>-		kfree(hwsp);
>-	}
>-
>-	spin_unlock_irqrestore(&gt->hwsp_lock, flags);
>-}
>-
>-static void __idle_cacheline_free(struct i915_timeline_cacheline *cl)
>-{
>-	GEM_BUG_ON(!i915_active_is_idle(&cl->active));
>-
>-	i915_gem_object_unpin_map(cl->hwsp->vma->obj);
>-	i915_vma_put(cl->hwsp->vma);
>-	__idle_hwsp_free(cl->hwsp, ptr_unmask_bits(cl->vaddr, CACHELINE_BITS));
>-
>-	i915_active_fini(&cl->active);
>-	kfree(cl);
>-}
>-
>-static void __cacheline_retire(struct i915_active *active)
>-{
>-	struct i915_timeline_cacheline *cl =
>-		container_of(active, typeof(*cl), active);
>-
>-	i915_vma_unpin(cl->hwsp->vma);
>-	if (ptr_test_bit(cl->vaddr, CACHELINE_FREE))
>-		__idle_cacheline_free(cl);
>-}
>-
>-static struct i915_timeline_cacheline *
>-cacheline_alloc(struct i915_timeline_hwsp *hwsp, unsigned int cacheline)
>-{
>-	struct i915_timeline_cacheline *cl;
>-	void *vaddr;
>-
>-	GEM_BUG_ON(cacheline >= BIT(CACHELINE_BITS));
>-
>-	cl = kmalloc(sizeof(*cl), GFP_KERNEL);
>-	if (!cl)
>-		return ERR_PTR(-ENOMEM);
>-
>-	vaddr = i915_gem_object_pin_map(hwsp->vma->obj, I915_MAP_WB);
>-	if (IS_ERR(vaddr)) {
>-		kfree(cl);
>-		return ERR_CAST(vaddr);
>-	}
>-
>-	i915_vma_get(hwsp->vma);
>-	cl->hwsp = hwsp;
>-	cl->vaddr = page_pack_bits(vaddr, cacheline);
>-
>-	i915_active_init(hwsp_to_i915(hwsp), &cl->active, __cacheline_retire);
>-
>-	return cl;
>-}
>-
>-static void cacheline_acquire(struct i915_timeline_cacheline *cl)
>-{
>-	if (cl && i915_active_acquire(&cl->active))
>-		__i915_vma_pin(cl->hwsp->vma);
>-}
>-
>-static void cacheline_release(struct i915_timeline_cacheline *cl)
>-{
>-	if (cl)
>-		i915_active_release(&cl->active);
>-}
>-
>-static void cacheline_free(struct i915_timeline_cacheline *cl)
>-{
>-	GEM_BUG_ON(ptr_test_bit(cl->vaddr, CACHELINE_FREE));
>-	cl->vaddr = ptr_set_bit(cl->vaddr, CACHELINE_FREE);
>-
>-	if (i915_active_is_idle(&cl->active))
>-		__idle_cacheline_free(cl);
>-}
>-
>-int i915_timeline_init(struct drm_i915_private *i915,
>-		       struct i915_timeline *timeline,
>-		       struct i915_vma *hwsp)
>-{
>-	void *vaddr;
>-
>-	/*
>-	 * Ideally we want a set of engines on a single leaf as we expect
>-	 * to mostly be tracking synchronisation between engines. It is not
>-	 * a huge issue if this is not the case, but we may want to mitigate
>-	 * any page crossing penalties if they become an issue.
>-	 *
>-	 * Called during early_init before we know how many engines there are.
>-	 */
>-	BUILD_BUG_ON(KSYNCMAP < I915_NUM_ENGINES);
>-
>-	timeline->i915 = i915;
>-	timeline->pin_count = 0;
>-	timeline->has_initial_breadcrumb = !hwsp;
>-	timeline->hwsp_cacheline = NULL;
>-
>-	if (!hwsp) {
>-		struct i915_timeline_cacheline *cl;
>-		unsigned int cacheline;
>-
>-		hwsp = hwsp_alloc(timeline, &cacheline);
>-		if (IS_ERR(hwsp))
>-			return PTR_ERR(hwsp);
>-
>-		cl = cacheline_alloc(hwsp->private, cacheline);
>-		if (IS_ERR(cl)) {
>-			__idle_hwsp_free(hwsp->private, cacheline);
>-			return PTR_ERR(cl);
>-		}
>-
>-		timeline->hwsp_cacheline = cl;
>-		timeline->hwsp_offset = cacheline * CACHELINE_BYTES;
>-
>-		vaddr = page_mask_bits(cl->vaddr);
>-	} else {
>-		timeline->hwsp_offset = I915_GEM_HWS_SEQNO_ADDR;
>-
>-		vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WB);
>-		if (IS_ERR(vaddr))
>-			return PTR_ERR(vaddr);
>-	}
>-
>-	timeline->hwsp_seqno =
>-		memset(vaddr + timeline->hwsp_offset, 0, CACHELINE_BYTES);
>-
>-	timeline->hwsp_ggtt = i915_vma_get(hwsp);
>-	GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size);
>-
>-	timeline->fence_context = dma_fence_context_alloc(1);
>-
>-	mutex_init(&timeline->mutex);
>-
>-	INIT_ACTIVE_REQUEST(&timeline->last_request);
>-	INIT_LIST_HEAD(&timeline->requests);
>-
>-	i915_syncmap_init(&timeline->sync);
>-
>-	return 0;
>-}
>-
>-void i915_timelines_init(struct drm_i915_private *i915)
>-{
>-	struct i915_gt_timelines *gt = &i915->gt.timelines;
>-
>-	mutex_init(&gt->mutex);
>-	INIT_LIST_HEAD(&gt->active_list);
>-
>-	spin_lock_init(&gt->hwsp_lock);
>-	INIT_LIST_HEAD(&gt->hwsp_free_list);
>-
>-	/* via i915_gem_wait_for_idle() */
>-	i915_gem_shrinker_taints_mutex(i915, &gt->mutex);
>-}
>-
>-static void timeline_add_to_active(struct i915_timeline *tl)
>-{
>-	struct i915_gt_timelines *gt = &tl->i915->gt.timelines;
>-
>-	mutex_lock(&gt->mutex);
>-	list_add(&tl->link, &gt->active_list);
>-	mutex_unlock(&gt->mutex);
>-}
>-
>-static void timeline_remove_from_active(struct i915_timeline *tl)
>-{
>-	struct i915_gt_timelines *gt = &tl->i915->gt.timelines;
>-
>-	mutex_lock(&gt->mutex);
>-	list_del(&tl->link);
>-	mutex_unlock(&gt->mutex);
>-}
>-
>-/**
>- * i915_timelines_park - called when the driver idles
>- * @i915: the drm_i915_private device
>- *
>- * When the driver is completely idle, we know that all of our sync points
>- * have been signaled and our tracking is then entirely redundant. Any request
>- * to wait upon an older sync point will be completed instantly as we know
>- * the fence is signaled and therefore we will not even look them up in the
>- * sync point map.
>- */
>-void i915_timelines_park(struct drm_i915_private *i915)
>-{
>-	struct i915_gt_timelines *gt = &i915->gt.timelines;
>-	struct i915_timeline *timeline;
>-
>-	mutex_lock(&gt->mutex);
>-	list_for_each_entry(timeline, &gt->active_list, link) {
>-		/*
>-		 * All known fences are completed so we can scrap
>-		 * the current sync point tracking and start afresh,
>-		 * any attempt to wait upon a previous sync point
>-		 * will be skipped as the fence was signaled.
>-		 */
>-		i915_syncmap_free(&timeline->sync);
>-	}
>-	mutex_unlock(&gt->mutex);
>-}
>-
>-void i915_timeline_fini(struct i915_timeline *timeline)
>-{
>-	GEM_BUG_ON(timeline->pin_count);
>-	GEM_BUG_ON(!list_empty(&timeline->requests));
>-
>-	i915_syncmap_free(&timeline->sync);
>-
>-	if (timeline->hwsp_cacheline)
>-		cacheline_free(timeline->hwsp_cacheline);
>-	else
>-		i915_gem_object_unpin_map(timeline->hwsp_ggtt->obj);
>-
>-	i915_vma_put(timeline->hwsp_ggtt);
>-}
>-
>-struct i915_timeline *
>-i915_timeline_create(struct drm_i915_private *i915,
>-		     struct i915_vma *global_hwsp)
>-{
>-	struct i915_timeline *timeline;
>-	int err;
>-
>-	timeline = kzalloc(sizeof(*timeline), GFP_KERNEL);
>-	if (!timeline)
>-		return ERR_PTR(-ENOMEM);
>-
>-	err = i915_timeline_init(i915, timeline, global_hwsp);
>-	if (err) {
>-		kfree(timeline);
>-		return ERR_PTR(err);
>-	}
>-
>-	kref_init(&timeline->kref);
>-
>-	return timeline;
>-}
>-
>-int i915_timeline_pin(struct i915_timeline *tl)
>-{
>-	int err;
>-
>-	if (tl->pin_count++)
>-		return 0;
>-	GEM_BUG_ON(!tl->pin_count);
>-
>-	err = i915_vma_pin(tl->hwsp_ggtt, 0, 0, PIN_GLOBAL | PIN_HIGH);
>-	if (err)
>-		goto unpin;
>-
>-	tl->hwsp_offset =
>-		i915_ggtt_offset(tl->hwsp_ggtt) +
>-		offset_in_page(tl->hwsp_offset);
>-
>-	cacheline_acquire(tl->hwsp_cacheline);
>-	timeline_add_to_active(tl);
>-
>-	return 0;
>-
>-unpin:
>-	tl->pin_count = 0;
>-	return err;
>-}
>-
>-static u32 timeline_advance(struct i915_timeline *tl)
>-{
>-	GEM_BUG_ON(!tl->pin_count);
>-	GEM_BUG_ON(tl->seqno & tl->has_initial_breadcrumb);
>-
>-	return tl->seqno += 1 + tl->has_initial_breadcrumb;
>-}
>-
>-static void timeline_rollback(struct i915_timeline *tl)
>-{
>-	tl->seqno -= 1 + tl->has_initial_breadcrumb;
>-}
>-
>-static noinline int
>-__i915_timeline_get_seqno(struct i915_timeline *tl,
>-			  struct i915_request *rq,
>-			  u32 *seqno)
>-{
>-	struct i915_timeline_cacheline *cl;
>-	unsigned int cacheline;
>-	struct i915_vma *vma;
>-	void *vaddr;
>-	int err;
>-
>-	/*
>-	 * If there is an outstanding GPU reference to this cacheline,
>-	 * such as it being sampled by a HW semaphore on another timeline,
>-	 * we cannot wraparound our seqno value (the HW semaphore does
>-	 * a strict greater-than-or-equals compare, not i915_seqno_passed).
>-	 * So if the cacheline is still busy, we must detach ourselves
>-	 * from it and leave it inflight alongside its users.
>-	 *
>-	 * However, if nobody is watching and we can guarantee that nobody
>-	 * will, we could simply reuse the same cacheline.
>-	 *
>-	 * if (i915_active_request_is_signaled(&tl->last_request) &&
>-	 *     i915_active_is_signaled(&tl->hwsp_cacheline->active))
>-	 *	return 0;
>-	 *
>-	 * That seems unlikely for a busy timeline that needed to wrap in
>-	 * the first place, so just replace the cacheline.
>-	 */
>-
>-	vma = hwsp_alloc(tl, &cacheline);
>-	if (IS_ERR(vma)) {
>-		err = PTR_ERR(vma);
>-		goto err_rollback;
>-	}
>-
>-	err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
>-	if (err) {
>-		__idle_hwsp_free(vma->private, cacheline);
>-		goto err_rollback;
>-	}
>-
>-	cl = cacheline_alloc(vma->private, cacheline);
>-	if (IS_ERR(cl)) {
>-		err = PTR_ERR(cl);
>-		__idle_hwsp_free(vma->private, cacheline);
>-		goto err_unpin;
>-	}
>-	GEM_BUG_ON(cl->hwsp->vma != vma);
>-
>-	/*
>-	 * Attach the old cacheline to the current request, so that we only
>-	 * free it after the current request is retired, which ensures that
>-	 * all writes into the cacheline from previous requests are complete.
>-	 */
>-	err = i915_active_ref(&tl->hwsp_cacheline->active,
>-			      tl->fence_context, rq);
>-	if (err)
>-		goto err_cacheline;
>-
>-	cacheline_release(tl->hwsp_cacheline); /* ownership now xfered to rq */
>-	cacheline_free(tl->hwsp_cacheline);
>-
>-	i915_vma_unpin(tl->hwsp_ggtt); /* binding kept alive by old cacheline */
>-	i915_vma_put(tl->hwsp_ggtt);
>-
>-	tl->hwsp_ggtt = i915_vma_get(vma);
>-
>-	vaddr = page_mask_bits(cl->vaddr);
>-	tl->hwsp_offset = cacheline * CACHELINE_BYTES;
>-	tl->hwsp_seqno =
>-		memset(vaddr + tl->hwsp_offset, 0, CACHELINE_BYTES);
>-
>-	tl->hwsp_offset += i915_ggtt_offset(vma);
>-
>-	cacheline_acquire(cl);
>-	tl->hwsp_cacheline = cl;
>-
>-	*seqno = timeline_advance(tl);
>-	GEM_BUG_ON(i915_seqno_passed(*tl->hwsp_seqno, *seqno));
>-	return 0;
>-
>-err_cacheline:
>-	cacheline_free(cl);
>-err_unpin:
>-	i915_vma_unpin(vma);
>-err_rollback:
>-	timeline_rollback(tl);
>-	return err;
>-}
>-
>-int i915_timeline_get_seqno(struct i915_timeline *tl,
>-			    struct i915_request *rq,
>-			    u32 *seqno)
>-{
>-	*seqno = timeline_advance(tl);
>-
>-	/* Replace the HWSP on wraparound for HW semaphores */
>-	if (unlikely(!*seqno && tl->hwsp_cacheline))
>-		return __i915_timeline_get_seqno(tl, rq, seqno);
>-
>-	return 0;
>-}
>-
>-static int cacheline_ref(struct i915_timeline_cacheline *cl,
>-			 struct i915_request *rq)
>-{
>-	return i915_active_ref(&cl->active, rq->fence.context, rq);
>-}
>-
>-int i915_timeline_read_hwsp(struct i915_request *from,
>-			    struct i915_request *to,
>-			    u32 *hwsp)
>-{
>-	struct i915_timeline_cacheline *cl = from->hwsp_cacheline;
>-	struct i915_timeline *tl = from->timeline;
>-	int err;
>-
>-	GEM_BUG_ON(to->timeline == tl);
>-
>-	mutex_lock_nested(&tl->mutex, SINGLE_DEPTH_NESTING);
>-	err = i915_request_completed(from);
>-	if (!err)
>-		err = cacheline_ref(cl, to);
>-	if (!err) {
>-		if (likely(cl == tl->hwsp_cacheline)) {
>-			*hwsp = tl->hwsp_offset;
>-		} else { /* across a seqno wrap, recover the original offset */
>-			*hwsp = i915_ggtt_offset(cl->hwsp->vma) +
>-				ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) *
>-				CACHELINE_BYTES;
>-		}
>-	}
>-	mutex_unlock(&tl->mutex);
>-
>-	return err;
>-}
>-
>-void i915_timeline_unpin(struct i915_timeline *tl)
>-{
>-	GEM_BUG_ON(!tl->pin_count);
>-	if (--tl->pin_count)
>-		return;
>-
>-	timeline_remove_from_active(tl);
>-	cacheline_release(tl->hwsp_cacheline);
>-
>-	/*
>-	 * Since this timeline is idle, all bariers upon which we were waiting
>-	 * must also be complete and so we can discard the last used barriers
>-	 * without loss of information.
>-	 */
>-	i915_syncmap_free(&tl->sync);
>-
>-	__i915_vma_unpin(tl->hwsp_ggtt);
>-}
>-
>-void __i915_timeline_free(struct kref *kref)
>-{
>-	struct i915_timeline *timeline =
>-		container_of(kref, typeof(*timeline), kref);
>-
>-	i915_timeline_fini(timeline);
>-	kfree(timeline);
>-}
>-
>-void i915_timelines_fini(struct drm_i915_private *i915)
>-{
>-	struct i915_gt_timelines *gt = &i915->gt.timelines;
>-
>-	GEM_BUG_ON(!list_empty(&gt->active_list));
>-	GEM_BUG_ON(!list_empty(&gt->hwsp_free_list));
>-
>-	mutex_destroy(&gt->mutex);
>-}
>-
>-#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
>-#include "selftests/mock_timeline.c"
>-#include "selftests/i915_timeline.c"
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_timeline.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_timeline.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_timeline.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_timeline.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,94 +0,0 @@
>-/*
>- * Copyright Â© 2016 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#ifndef I915_TIMELINE_H
>-#define I915_TIMELINE_H
>-
>-#include <linux/lockdep.h>
>-
>-#include "i915_active.h"
>-#include "i915_syncmap.h"
>-#include "i915_timeline_types.h"
>-
>-int i915_timeline_init(struct drm_i915_private *i915,
>-		       struct i915_timeline *tl,
>-		       struct i915_vma *hwsp);
>-void i915_timeline_fini(struct i915_timeline *tl);
>-
>-struct i915_timeline *
>-i915_timeline_create(struct drm_i915_private *i915,
>-		     struct i915_vma *global_hwsp);
>-
>-static inline struct i915_timeline *
>-i915_timeline_get(struct i915_timeline *timeline)
>-{
>-	kref_get(&timeline->kref);
>-	return timeline;
>-}
>-
>-void __i915_timeline_free(struct kref *kref);
>-static inline void i915_timeline_put(struct i915_timeline *timeline)
>-{
>-	kref_put(&timeline->kref, __i915_timeline_free);
>-}
>-
>-static inline int __i915_timeline_sync_set(struct i915_timeline *tl,
>-					   u64 context, u32 seqno)
>-{
>-	return i915_syncmap_set(&tl->sync, context, seqno);
>-}
>-
>-static inline int i915_timeline_sync_set(struct i915_timeline *tl,
>-					 const struct dma_fence *fence)
>-{
>-	return __i915_timeline_sync_set(tl, fence->context, fence->seqno);
>-}
>-
>-static inline bool __i915_timeline_sync_is_later(struct i915_timeline *tl,
>-						 u64 context, u32 seqno)
>-{
>-	return i915_syncmap_is_later(&tl->sync, context, seqno);
>-}
>-
>-static inline bool i915_timeline_sync_is_later(struct i915_timeline *tl,
>-					       const struct dma_fence *fence)
>-{
>-	return __i915_timeline_sync_is_later(tl, fence->context, fence->seqno);
>-}
>-
>-int i915_timeline_pin(struct i915_timeline *tl);
>-int i915_timeline_get_seqno(struct i915_timeline *tl,
>-			    struct i915_request *rq,
>-			    u32 *seqno);
>-void i915_timeline_unpin(struct i915_timeline *tl);
>-
>-int i915_timeline_read_hwsp(struct i915_request *from,
>-			    struct i915_request *until,
>-			    u32 *hwsp_offset);
>-
>-void i915_timelines_init(struct drm_i915_private *i915);
>-void i915_timelines_park(struct drm_i915_private *i915);
>-void i915_timelines_fini(struct drm_i915_private *i915);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_timeline_types.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_timeline_types.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_timeline_types.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_timeline_types.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,67 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2016 Intel Corporation
>- */
>-
>-#ifndef __I915_TIMELINE_TYPES_H__
>-#define __I915_TIMELINE_TYPES_H__
>-
>-#include <linux/list.h>
>-#include <linux/kref.h>
>-#include <linux/mutex.h>
>-#include <linux/types.h>
>-
>-#include "i915_active_types.h"
>-
>-struct drm_i915_private;
>-struct i915_vma;
>-struct i915_timeline_cacheline;
>-struct i915_syncmap;
>-
>-struct i915_timeline {
>-	u64 fence_context;
>-	u32 seqno;
>-
>-	struct mutex mutex; /* protects the flow of requests */
>-
>-	unsigned int pin_count;
>-	const u32 *hwsp_seqno;
>-	struct i915_vma *hwsp_ggtt;
>-	u32 hwsp_offset;
>-
>-	struct i915_timeline_cacheline *hwsp_cacheline;
>-
>-	bool has_initial_breadcrumb;
>-
>-	/**
>-	 * List of breadcrumbs associated with GPU requests currently
>-	 * outstanding.
>-	 */
>-	struct list_head requests;
>-
>-	/* Contains an RCU guarded pointer to the last request. No reference is
>-	 * held to the request, users must carefully acquire a reference to
>-	 * the request using i915_active_request_get_request_rcu(), or hold the
>-	 * struct_mutex.
>-	 */
>-	struct i915_active_request last_request;
>-
>-	/**
>-	 * We track the most recent seqno that we wait on in every context so
>-	 * that we only have to emit a new await and dependency on a more
>-	 * recent sync point. As the contexts may be executed out-of-order, we
>-	 * have to track each individually and can not rely on an absolute
>-	 * global_seqno. When we know that all tracked fences are completed
>-	 * (i.e. when the driver is idle), we know that the syncmap is
>-	 * redundant and we can discard it without loss of generality.
>-	 */
>-	struct i915_syncmap *sync;
>-
>-	struct list_head link;
>-	struct drm_i915_private *i915;
>-
>-	struct kref kref;
>-};
>-
>-#endif /* __I915_TIMELINE_TYPES_H__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_trace.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_trace.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_trace.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_trace.h	2019-08-31 15:01:12.037736184 -0500
>@@ -293,16 +293,16 @@
> 
> 	    TP_STRUCT__entry(
> 			     __field(enum pipe, pipe)
>-			     __field(const char *, name)
> 			     __field(u32, frame)
> 			     __field(u32, scanline)
> 			     __array(int, src, 4)
> 			     __array(int, dst, 4)
>+			     __string(name, plane->name)
> 			     ),
> 
> 	    TP_fast_assign(
>+			   __assign_str(name, plane->name);
> 			   __entry->pipe = crtc->pipe;
>-			   __entry->name = plane->name;
> 			   __entry->frame = intel_crtc_get_vblank_counter(crtc);
> 			   __entry->scanline = intel_get_crtc_scanline(crtc);
> 			   memcpy(__entry->src, &plane->state->src, sizeof(__entry->src));
>@@ -310,7 +310,7 @@
> 			   ),
> 
> 	    TP_printk("pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT,
>-		      pipe_name(__entry->pipe), __entry->name,
>+		      pipe_name(__entry->pipe), __get_str(name),
> 		      __entry->frame, __entry->scanline,
> 		      DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src),
> 		      DRM_RECT_ARG((const struct drm_rect *)__entry->dst))
>@@ -322,20 +322,20 @@
> 
> 	    TP_STRUCT__entry(
> 			     __field(enum pipe, pipe)
>-			     __field(const char *, name)
> 			     __field(u32, frame)
> 			     __field(u32, scanline)
>+			     __string(name, plane->name)
> 			     ),
> 
> 	    TP_fast_assign(
>+			   __assign_str(name, plane->name);
> 			   __entry->pipe = crtc->pipe;
>-			   __entry->name = plane->name;
> 			   __entry->frame = intel_crtc_get_vblank_counter(crtc);
> 			   __entry->scanline = intel_get_crtc_scanline(crtc);
> 			   ),
> 
> 	    TP_printk("pipe %c, plane %s, frame=%u, scanline=%u",
>-		      pipe_name(__entry->pipe), __entry->name,
>+		      pipe_name(__entry->pipe), __get_str(name),
> 		      __entry->frame, __entry->scanline)
> );
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_utils.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_utils.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_utils.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_utils.h	2019-08-31 15:01:12.037736184 -0500
>@@ -131,6 +131,18 @@
> 	((typeof(ptr))((unsigned long)(ptr) | __bits));			\
> })
> 
>+#define ptr_count_dec(p_ptr) do {					\
>+	typeof(p_ptr) __p = (p_ptr);					\
>+	unsigned long __v = (unsigned long)(*__p);			\
>+	*__p = (typeof(*p_ptr))(--__v);					\
>+} while (0)
>+
>+#define ptr_count_inc(p_ptr) do {					\
>+	typeof(p_ptr) __p = (p_ptr);					\
>+	unsigned long __v = (unsigned long)(*__p);			\
>+	*__p = (typeof(*p_ptr))(++__v);					\
>+} while (0)
>+
> #define page_mask_bits(ptr) ptr_mask_bits(ptr, PAGE_SHIFT)
> #define page_unmask_bits(ptr) ptr_unmask_bits(ptr, PAGE_SHIFT)
> #define page_pack_bits(ptr, bits) ptr_pack_bits(ptr, bits, PAGE_SHIFT)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_vgpu.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_vgpu.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_vgpu.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_vgpu.c	2019-08-31 15:01:12.037736184 -0500
>@@ -52,34 +52,53 @@
>  */
> 
> /**
>- * i915_check_vgpu - detect virtual GPU
>+ * i915_detect_vgpu - detect virtual GPU
>  * @dev_priv: i915 device private
>  *
>  * This function is called at the initialization stage, to detect whether
>  * running on a vGPU.
>  */
>-void i915_check_vgpu(struct drm_i915_private *dev_priv)
>+void i915_detect_vgpu(struct drm_i915_private *dev_priv)
> {
>-	struct intel_uncore *uncore = &dev_priv->uncore;
>+	struct pci_dev *pdev = dev_priv->drm.pdev;
> 	u64 magic;
> 	u16 version_major;
>+	void __iomem *shared_area;
> 
> 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
> 
>-	magic = __raw_uncore_read64(uncore, vgtif_reg(magic));
>-	if (magic != VGT_MAGIC)
>+	/*
>+	 * This is called before we setup the main MMIO BAR mappings used via
>+	 * the uncore structure, so we need to access the BAR directly. Since
>+	 * we do not support VGT on older gens, return early so we don't have
>+	 * to consider differently numbered or sized MMIO bars
>+	 */
>+	if (INTEL_GEN(dev_priv) < 6)
>+		return;
>+
>+	shared_area = pci_iomap_range(pdev, 0, VGT_PVINFO_PAGE, VGT_PVINFO_SIZE);
>+	if (!shared_area) {
>+		DRM_ERROR("failed to map MMIO bar to check for VGT\n");
> 		return;
>+	}
>+
>+	magic = readq(shared_area + vgtif_offset(magic));
>+	if (magic != VGT_MAGIC)
>+		goto out;
> 
>-	version_major = __raw_uncore_read16(uncore, vgtif_reg(version_major));
>+	version_major = readw(shared_area + vgtif_offset(version_major));
> 	if (version_major < VGT_VERSION_MAJOR) {
> 		DRM_INFO("VGT interface version mismatch!\n");
>-		return;
>+		goto out;
> 	}
> 
>-	dev_priv->vgpu.caps = __raw_uncore_read32(uncore, vgtif_reg(vgt_caps));
>+	dev_priv->vgpu.caps = readl(shared_area + vgtif_offset(vgt_caps));
> 
> 	dev_priv->vgpu.active = true;
> 	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
>+
>+out:
>+	pci_iounmap(pdev, shared_area);
> }
> 
> bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv)
>@@ -112,22 +131,22 @@
> 
> /**
>  * intel_vgt_deballoon - deballoon reserved graphics address trunks
>- * @dev_priv: i915 device private data
>+ * @ggtt: the global GGTT from which we reserved earlier
>  *
>  * This function is called to deallocate the ballooned-out graphic memory, when
>  * driver is unloaded or when ballooning fails.
>  */
>-void intel_vgt_deballoon(struct drm_i915_private *dev_priv)
>+void intel_vgt_deballoon(struct i915_ggtt *ggtt)
> {
> 	int i;
> 
>-	if (!intel_vgpu_active(dev_priv))
>+	if (!intel_vgpu_active(ggtt->vm.i915))
> 		return;
> 
> 	DRM_DEBUG("VGT deballoon.\n");
> 
> 	for (i = 0; i < 4; i++)
>-		vgt_deballoon_space(&dev_priv->ggtt, &bl_info.space[i]);
>+		vgt_deballoon_space(ggtt, &bl_info.space[i]);
> }
> 
> static int vgt_balloon_space(struct i915_ggtt *ggtt,
>@@ -153,7 +172,7 @@
> 
> /**
>  * intel_vgt_balloon - balloon out reserved graphics address trunks
>- * @dev_priv: i915 device private data
>+ * @ggtt: the global GGTT from which to reserve
>  *
>  * This function is called at the initialization stage, to balloon out the
>  * graphic address space allocated to other vGPUs, by marking these spaces as
>@@ -195,22 +214,26 @@
>  * Returns:
>  * zero on success, non-zero if configuration invalid or ballooning failed
>  */
>-int intel_vgt_balloon(struct drm_i915_private *dev_priv)
>+int intel_vgt_balloon(struct i915_ggtt *ggtt)
> {
>-	struct i915_ggtt *ggtt = &dev_priv->ggtt;
>+	struct intel_uncore *uncore = &ggtt->vm.i915->uncore;
> 	unsigned long ggtt_end = ggtt->vm.total;
> 
> 	unsigned long mappable_base, mappable_size, mappable_end;
> 	unsigned long unmappable_base, unmappable_size, unmappable_end;
> 	int ret;
> 
>-	if (!intel_vgpu_active(dev_priv))
>+	if (!intel_vgpu_active(ggtt->vm.i915))
> 		return 0;
> 
>-	mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
>-	mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
>-	unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
>-	unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
>+	mappable_base =
>+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base));
>+	mappable_size =
>+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size));
>+	unmappable_base =
>+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base));
>+	unmappable_size =
>+	  intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size));
> 
> 	mappable_end = mappable_base + mappable_size;
> 	unmappable_end = unmappable_base + unmappable_size;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_vgpu.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_vgpu.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_vgpu.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_vgpu.h	2019-08-31 15:01:12.037736184 -0500
>@@ -24,9 +24,10 @@
> #ifndef _I915_VGPU_H_
> #define _I915_VGPU_H_
> 
>+#include "i915_drv.h"
> #include "i915_pvinfo.h"
> 
>-void i915_check_vgpu(struct drm_i915_private *dev_priv);
>+void i915_detect_vgpu(struct drm_i915_private *dev_priv);
> 
> bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv);
> 
>@@ -42,7 +43,7 @@
> 	return dev_priv->vgpu.caps & VGT_CAPS_HUGE_GTT;
> }
> 
>-int intel_vgt_balloon(struct drm_i915_private *dev_priv);
>-void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
>+int intel_vgt_balloon(struct i915_ggtt *ggtt);
>+void intel_vgt_deballoon(struct i915_ggtt *ggtt);
> 
> #endif /* _I915_VGPU_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/i915_vma.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_vma.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/i915_vma.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/i915_vma.c	2019-08-31 15:01:12.037736184 -0500
>@@ -22,11 +22,13 @@
>  *
>  */
> 
>+#include <linux/sched/mm.h>
> #include <drm/drm_gem.h>
> 
> #include "display/intel_frontbuffer.h"
> 
> #include "gt/intel_engine.h"
>+#include "gt/intel_gt.h"
> 
> #include "i915_drv.h"
> #include "i915_globals.h"
>@@ -77,43 +79,20 @@
> 
> #endif
> 
>-static void obj_bump_mru(struct drm_i915_gem_object *obj)
>+static inline struct i915_vma *active_to_vma(struct i915_active *ref)
> {
>-	struct drm_i915_private *i915 = to_i915(obj->base.dev);
>-	unsigned long flags;
>-
>-	spin_lock_irqsave(&i915->mm.obj_lock, flags);
>-	list_move_tail(&obj->mm.link, &i915->mm.shrink_list);
>-	spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
>+	return container_of(ref, typeof(struct i915_vma), active);
>+}
> 
>-	obj->mm.dirty = true; /* be paranoid  */
>+static int __i915_vma_active(struct i915_active *ref)
>+{
>+	i915_vma_get(active_to_vma(ref));
>+	return 0;
> }
> 
> static void __i915_vma_retire(struct i915_active *ref)
> {
>-	struct i915_vma *vma = container_of(ref, typeof(*vma), active);
>-	struct drm_i915_gem_object *obj = vma->obj;
>-
>-	GEM_BUG_ON(!i915_gem_object_is_active(obj));
>-	if (--obj->active_count)
>-		return;
>-
>-	/* Prune the shared fence arrays iff completely idle (inc. external) */
>-	if (reservation_object_trylock(obj->base.resv)) {
>-		if (reservation_object_test_signaled_rcu(obj->base.resv, true))
>-			reservation_object_add_excl_fence(obj->base.resv, NULL);
>-		reservation_object_unlock(obj->base.resv);
>-	}
>-
>-	/*
>-	 * Bump our place on the bound list to keep it roughly in LRU order
>-	 * so that we don't steal from recently used but inactive objects
>-	 * (unless we are forced to ofc!)
>-	 */
>-	if (i915_gem_object_is_shrinkable(obj))
>-		obj_bump_mru(obj);
>-
>-	i915_gem_object_put(obj); /* and drop the active reference */
>+	i915_vma_put(active_to_vma(ref));
> }
> 
> static struct i915_vma *
>@@ -125,7 +104,7 @@
> 	struct rb_node *rb, **p;
> 
> 	/* The aliasing_ppgtt should never be used directly! */
>-	GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->vm);
>+	GEM_BUG_ON(vm == &vm->i915->ggtt.alias->vm);
> 
> 	vma = i915_vma_alloc();
> 	if (vma == NULL)
>@@ -138,9 +117,17 @@
> 	vma->size = obj->base.size;
> 	vma->display_alignment = I915_GTT_MIN_ALIGNMENT;
> 
>-	i915_active_init(vm->i915, &vma->active, __i915_vma_retire);
>+	i915_active_init(vm->i915, &vma->active,
>+			 __i915_vma_active, __i915_vma_retire);
> 	INIT_ACTIVE_REQUEST(&vma->last_fence);
> 
>+	/* Declare ourselves safe for use inside shrinkers */
>+	if (IS_ENABLED(CONFIG_LOCKDEP)) {
>+		fs_reclaim_acquire(GFP_KERNEL);
>+		might_lock(&vma->active.mutex);
>+		fs_reclaim_release(GFP_KERNEL);
>+	}
>+
> 	INIT_LIST_HEAD(&vma->closed_link);
> 
> 	if (view && view->type != I915_GGTT_VIEW_NORMAL) {
>@@ -408,7 +395,7 @@
> 	if (!i915_vma_has_ggtt_write(vma))
> 		return;
> 
>-	i915_gem_flush_ggtt_writes(vma->vm->i915);
>+	intel_gt_flush_ggtt_writes(vma->vm->gt);
> 
> 	i915_vma_unset_ggtt_write(vma);
> }
>@@ -921,6 +908,7 @@
> 			    unsigned int flags)
> {
> 	struct drm_i915_gem_object *obj = vma->obj;
>+	int err;
> 
> 	assert_vma_held(vma);
> 	assert_object_held(obj);
>@@ -934,17 +922,9 @@
> 	 * add the active reference first and queue for it to be dropped
> 	 * *last*.
> 	 */
>-	if (!vma->active.count && !obj->active_count++)
>-		i915_gem_object_get(obj); /* once more for the active ref */
>-
>-	if (unlikely(i915_active_ref(&vma->active, rq->fence.context, rq))) {
>-		if (!vma->active.count && !--obj->active_count)
>-			i915_gem_object_put(obj);
>-		return -ENOMEM;
>-	}
>-
>-	GEM_BUG_ON(!i915_vma_is_active(vma));
>-	GEM_BUG_ON(!obj->active_count);
>+	err = i915_active_ref(&vma->active, rq->fence.context, rq);
>+	if (unlikely(err))
>+		return err;
> 
> 	obj->write_domain = 0;
> 	if (flags & EXEC_OBJECT_WRITE) {
>@@ -956,11 +936,14 @@
> 		obj->read_domains = 0;
> 	}
> 	obj->read_domains |= I915_GEM_GPU_DOMAINS;
>+	obj->mm.dirty = true;
> 
> 	if (flags & EXEC_OBJECT_NEEDS_FENCE)
> 		__i915_active_request_set(&vma->last_fence, rq);
> 
> 	export_fence(vma, rq, flags);
>+
>+	GEM_BUG_ON(!i915_vma_is_active(vma));
> 	return 0;
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_device_info.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_device_info.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_device_info.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_device_info.c	2019-08-31 15:01:12.038736184 -0500
>@@ -58,6 +58,7 @@
> 	PLATFORM_NAME(CANNONLAKE),
> 	PLATFORM_NAME(ICELAKE),
> 	PLATFORM_NAME(ELKHARTLAKE),
>+	PLATFORM_NAME(TIGERLAKE),
> };
> #undef PLATFORM_NAME
> 
>@@ -929,35 +930,28 @@
> 		}
> 	} else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
> 		u32 dfsm = I915_READ(SKL_DFSM);
>-		u8 disabled_mask = 0;
>-		bool invalid;
>-		int num_bits;
>+		u8 enabled_mask = BIT(info->num_pipes) - 1;
> 
> 		if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
>-			disabled_mask |= BIT(PIPE_A);
>+			enabled_mask &= ~BIT(PIPE_A);
> 		if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
>-			disabled_mask |= BIT(PIPE_B);
>+			enabled_mask &= ~BIT(PIPE_B);
> 		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
>-			disabled_mask |= BIT(PIPE_C);
>+			enabled_mask &= ~BIT(PIPE_C);
>+		if (INTEL_GEN(dev_priv) >= 12 &&
>+		    (dfsm & TGL_DFSM_PIPE_D_DISABLE))
>+			enabled_mask &= ~BIT(PIPE_D);
> 
>-		num_bits = hweight8(disabled_mask);
>-
>-		switch (disabled_mask) {
>-		case BIT(PIPE_A):
>-		case BIT(PIPE_B):
>-		case BIT(PIPE_A) | BIT(PIPE_B):
>-		case BIT(PIPE_A) | BIT(PIPE_C):
>-			invalid = true;
>-			break;
>-		default:
>-			invalid = false;
>-		}
>-
>-		if (num_bits > info->num_pipes || invalid)
>-			DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
>-				  disabled_mask);
>+		/*
>+		 * At least one pipe should be enabled and if there are
>+		 * disabled pipes, they should be the last ones, with no holes
>+		 * in the mask.
>+		 */
>+		if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
>+			DRM_ERROR("invalid pipe fuse configuration: enabled_mask=0x%x\n",
>+				  enabled_mask);
> 		else
>-			info->num_pipes -= num_bits;
>+			info->num_pipes = hweight8(enabled_mask);
> 	}
> 
> 	/* Initialize slice/subslice/EU info */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_device_info.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_device_info.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_device_info.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_device_info.h	2019-08-31 15:01:12.038736184 -0500
>@@ -78,6 +78,8 @@
> 	/* gen11 */
> 	INTEL_ICELAKE,
> 	INTEL_ELKHARTLAKE,
>+	/* gen12 */
>+	INTEL_TIGERLAKE,
> 	INTEL_MAX_PLATFORMS
> };
> 
>@@ -110,7 +112,7 @@
> 	func(gpu_reset_clobbers_display); \
> 	func(has_reset_engine); \
> 	func(has_fpga_dbg); \
>-	func(has_guc); \
>+	func(has_gt_uc); \
> 	func(has_l3_dpf); \
> 	func(has_llc); \
> 	func(has_logical_ring_contexts); \
>@@ -136,6 +138,7 @@
> 	func(has_gmch); \
> 	func(has_hotplug); \
> 	func(has_ipc); \
>+	func(has_modular_fia); \
> 	func(has_overlay); \
> 	func(has_psr); \
> 	func(overlay_needs_physical); \
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_drv.h	2019-08-31 15:01:12.239736202 -0500
>@@ -101,20 +101,30 @@
> 	struct mutex hpd_lock;
> };
> 
>+enum intel_hotplug_state {
>+	INTEL_HOTPLUG_UNCHANGED,
>+	INTEL_HOTPLUG_CHANGED,
>+	INTEL_HOTPLUG_RETRY,
>+};
>+
> struct intel_encoder {
> 	struct drm_encoder base;
> 
> 	enum intel_output_type type;
> 	enum port port;
> 	unsigned int cloneable;
>-	bool (*hotplug)(struct intel_encoder *encoder,
>-			struct intel_connector *connector);
>+	enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
>+					    struct intel_connector *connector,
>+					    bool irq_received);
> 	enum intel_output_type (*compute_output_type)(struct intel_encoder *,
> 						      struct intel_crtc_state *,
> 						      struct drm_connector_state *);
> 	int (*compute_config)(struct intel_encoder *,
> 			      struct intel_crtc_state *,
> 			      struct drm_connector_state *);
>+	void (*update_prepare)(struct intel_atomic_state *,
>+			       struct intel_encoder *,
>+			       struct intel_crtc *);
> 	void (*pre_pll_enable)(struct intel_encoder *,
> 			       const struct intel_crtc_state *,
> 			       const struct drm_connector_state *);
>@@ -124,6 +134,9 @@
> 	void (*enable)(struct intel_encoder *,
> 		       const struct intel_crtc_state *,
> 		       const struct drm_connector_state *);
>+	void (*update_complete)(struct intel_atomic_state *,
>+				struct intel_encoder *,
>+				struct intel_crtc *);
> 	void (*disable)(struct intel_encoder *,
> 			const struct intel_crtc_state *,
> 			const struct drm_connector_state *);
>@@ -812,6 +825,15 @@
> 	/* Actual register state of the dpll, for shared dpll cross-checking. */
> 	struct intel_dpll_hw_state dpll_hw_state;
> 
>+	/*
>+	 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
>+	 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
>+	 */
>+	struct icl_port_dpll {
>+		struct intel_shared_dpll *pll;
>+		struct intel_dpll_hw_state hw_state;
>+	} icl_port_dplls[ICL_PORT_DPLL_COUNT];
>+
> 	/* DSI PLL registers */
> 	struct {
> 		u32 ctrl, div;
>@@ -1224,8 +1246,13 @@
> 	/* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
> 	enum aux_ch aux_ch;
> 	enum intel_display_power_domain ddi_io_power_domain;
>+	struct mutex tc_lock;	/* protects the TypeC port mode */
>+	intel_wakeref_t tc_lock_wakeref;
>+	int tc_link_refcount;
> 	bool tc_legacy_port:1;
>-	enum tc_port_type tc_type;
>+	char tc_port_name[8];
>+	enum tc_port_mode tc_mode;
>+	enum phy_fia tc_phy_fia;
> 
> 	void (*write_infoframe)(struct intel_encoder *encoder,
> 				const struct intel_crtc_state *crtc_state,
>@@ -1473,8 +1500,8 @@
> void intel_encoder_destroy(struct drm_encoder *encoder);
> struct drm_display_mode *
> intel_encoder_current_mode(struct intel_encoder *encoder);
>-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
>-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
>+bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
>+bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> 			      enum port port);
> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_ads.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_ads.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_ads.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_ads.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,202 +0,0 @@
>-/*
>- * Copyright Â© 2014-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#include "intel_guc_ads.h"
>-#include "intel_uc.h"
>-#include "i915_drv.h"
>-
>-/*
>- * The Additional Data Struct (ADS) has pointers for different buffers used by
>- * the GuC. One single gem object contains the ADS struct itself (guc_ads), the
>- * scheduling policies (guc_policies), a structure describing a collection of
>- * register sets (guc_mmio_reg_state) and some extra pages for the GuC to save
>- * its internal state for sleep.
>- */
>-
>-static void guc_policy_init(struct guc_policy *policy)
>-{
>-	policy->execution_quantum = POLICY_DEFAULT_EXECUTION_QUANTUM_US;
>-	policy->preemption_time = POLICY_DEFAULT_PREEMPTION_TIME_US;
>-	policy->fault_time = POLICY_DEFAULT_FAULT_TIME_US;
>-	policy->policy_flags = 0;
>-}
>-
>-static void guc_policies_init(struct guc_policies *policies)
>-{
>-	struct guc_policy *policy;
>-	u32 p, i;
>-
>-	policies->dpc_promote_time = POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
>-	policies->max_num_work_items = POLICY_MAX_NUM_WI;
>-
>-	for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) {
>-		for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++) {
>-			policy = &policies->policy[p][i];
>-
>-			guc_policy_init(policy);
>-		}
>-	}
>-
>-	policies->is_valid = 1;
>-}
>-
>-static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num)
>-{
>-	memset(pool, 0, num * sizeof(*pool));
>-}
>-
>-/*
>- * The first 80 dwords of the register state context, containing the
>- * execlists and ppgtt registers.
>- */
>-#define LR_HW_CONTEXT_SIZE	(80 * sizeof(u32))
>-
>-/* The ads obj includes the struct itself and buffers passed to GuC */
>-struct __guc_ads_blob {
>-	struct guc_ads ads;
>-	struct guc_policies policies;
>-	struct guc_mmio_reg_state reg_state;
>-	struct guc_gt_system_info system_info;
>-	struct guc_clients_info clients_info;
>-	struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE];
>-	u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];
>-} __packed;
>-
>-static int __guc_ads_init(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	struct __guc_ads_blob *blob;
>-	const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
>-	u32 base;
>-	u8 engine_class;
>-
>-	blob = i915_gem_object_pin_map(guc->ads_vma->obj, I915_MAP_WB);
>-	if (IS_ERR(blob))
>-		return PTR_ERR(blob);
>-
>-	/* GuC scheduling policies */
>-	guc_policies_init(&blob->policies);
>-
>-	/*
>-	 * GuC expects a per-engine-class context image and size
>-	 * (minus hwsp and ring context). The context image will be
>-	 * used to reinitialize engines after a reset. It must exist
>-	 * and be pinned in the GGTT, so that the address won't change after
>-	 * we have told GuC where to find it. The context size will be used
>-	 * to validate that the LRC base + size fall within allowed GGTT.
>-	 */
>-	for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) {
>-		if (engine_class == OTHER_CLASS)
>-			continue;
>-		/*
>-		 * TODO: Set context pointer to default state to allow
>-		 * GuC to re-init guilty contexts after internal reset.
>-		 */
>-		blob->ads.golden_context_lrca[engine_class] = 0;
>-		blob->ads.eng_state_size[engine_class] =
>-			intel_engine_context_size(dev_priv, engine_class) -
>-			skipped_size;
>-	}
>-
>-	/* System info */
>-	blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask);
>-	blob->system_info.rcs_enabled = 1;
>-	blob->system_info.bcs_enabled = 1;
>-
>-	blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv);
>-	blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv);
>-	blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access;
>-
>-	base = intel_guc_ggtt_offset(guc, guc->ads_vma);
>-
>-	/* Clients info  */
>-	guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool));
>-
>-	blob->clients_info.clients_num = 1;
>-	blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool);
>-	blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool);
>-
>-	/* ADS */
>-	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
>-	blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer);
>-	blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state);
>-	blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
>-	blob->ads.clients_info = base + ptr_offset(blob, clients_info);
>-
>-	i915_gem_object_unpin_map(guc->ads_vma->obj);
>-
>-	return 0;
>-}
>-
>-/**
>- * intel_guc_ads_create() - allocates and initializes GuC ADS.
>- * @guc: intel_guc struct
>- *
>- * GuC needs memory block (Additional Data Struct), where it will store
>- * some data. Allocate and initialize such memory block for GuC use.
>- */
>-int intel_guc_ads_create(struct intel_guc *guc)
>-{
>-	const u32 size = PAGE_ALIGN(sizeof(struct __guc_ads_blob));
>-	struct i915_vma *vma;
>-	int ret;
>-
>-	GEM_BUG_ON(guc->ads_vma);
>-
>-	vma = intel_guc_allocate_vma(guc, size);
>-	if (IS_ERR(vma))
>-		return PTR_ERR(vma);
>-
>-	guc->ads_vma = vma;
>-
>-	ret = __guc_ads_init(guc);
>-	if (ret)
>-		goto err_vma;
>-
>-	return 0;
>-
>-err_vma:
>-	i915_vma_unpin_and_release(&guc->ads_vma, 0);
>-	return ret;
>-}
>-
>-void intel_guc_ads_destroy(struct intel_guc *guc)
>-{
>-	i915_vma_unpin_and_release(&guc->ads_vma, 0);
>-}
>-
>-/**
>- * intel_guc_ads_reset() - prepares GuC Additional Data Struct for reuse
>- * @guc: intel_guc struct
>- *
>- * GuC stores some data in ADS, which might be stale after a reset.
>- * Reinitialize whole ADS in case any part of it was corrupted during
>- * previous GuC run.
>- */
>-void intel_guc_ads_reset(struct intel_guc *guc)
>-{
>-	if (!guc->ads_vma)
>-		return;
>-	__guc_ads_init(guc);
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_ads.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_ads.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_ads.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_ads.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,34 +0,0 @@
>-/*
>- * Copyright Â© 2014-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#ifndef _INTEL_GUC_ADS_H_
>-#define _INTEL_GUC_ADS_H_
>-
>-struct intel_guc;
>-
>-int intel_guc_ads_create(struct intel_guc *guc);
>-void intel_guc_ads_destroy(struct intel_guc *guc);
>-void intel_guc_ads_reset(struct intel_guc *guc);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,687 +0,0 @@
>-/*
>- * Copyright Â© 2014-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#include "intel_guc.h"
>-#include "intel_guc_ads.h"
>-#include "intel_guc_submission.h"
>-#include "i915_drv.h"
>-
>-static void gen8_guc_raise_irq(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-
>-	I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
>-}
>-
>-static void gen11_guc_raise_irq(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-
>-	I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
>-}
>-
>-static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
>-{
>-	GEM_BUG_ON(!guc->send_regs.base);
>-	GEM_BUG_ON(!guc->send_regs.count);
>-	GEM_BUG_ON(i >= guc->send_regs.count);
>-
>-	return _MMIO(guc->send_regs.base + 4 * i);
>-}
>-
>-void intel_guc_init_send_regs(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	enum forcewake_domains fw_domains = 0;
>-	unsigned int i;
>-
>-	if (INTEL_GEN(dev_priv) >= 11) {
>-		guc->send_regs.base =
>-				i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
>-		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
>-	} else {
>-		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
>-		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
>-		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
>-	}
>-
>-	for (i = 0; i < guc->send_regs.count; i++) {
>-		fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
>-					guc_send_reg(guc, i),
>-					FW_REG_READ | FW_REG_WRITE);
>-	}
>-	guc->send_regs.fw_domains = fw_domains;
>-}
>-
>-void intel_guc_init_early(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *i915 = guc_to_i915(guc);
>-
>-	intel_guc_fw_init_early(guc);
>-	intel_guc_ct_init_early(&guc->ct);
>-	intel_guc_log_init_early(&guc->log);
>-
>-	mutex_init(&guc->send_mutex);
>-	spin_lock_init(&guc->irq_lock);
>-	guc->send = intel_guc_send_nop;
>-	guc->handler = intel_guc_to_host_event_handler_nop;
>-	if (INTEL_GEN(i915) >= 11) {
>-		guc->notify = gen11_guc_raise_irq;
>-		guc->interrupts.reset = gen11_reset_guc_interrupts;
>-		guc->interrupts.enable = gen11_enable_guc_interrupts;
>-		guc->interrupts.disable = gen11_disable_guc_interrupts;
>-	} else {
>-		guc->notify = gen8_guc_raise_irq;
>-		guc->interrupts.reset = gen9_reset_guc_interrupts;
>-		guc->interrupts.enable = gen9_enable_guc_interrupts;
>-		guc->interrupts.disable = gen9_disable_guc_interrupts;
>-	}
>-}
>-
>-static int guc_init_wq(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-
>-	/*
>-	 * GuC log buffer flush work item has to do register access to
>-	 * send the ack to GuC and this work item, if not synced before
>-	 * suspend, can potentially get executed after the GFX device is
>-	 * suspended.
>-	 * By marking the WQ as freezable, we don't have to bother about
>-	 * flushing of this work item from the suspend hooks, the pending
>-	 * work item if any will be either executed before the suspend
>-	 * or scheduled later on resume. This way the handling of work
>-	 * item can be kept same between system suspend & rpm suspend.
>-	 */
>-	guc->log.relay.flush_wq =
>-		alloc_ordered_workqueue("i915-guc_log",
>-					WQ_HIGHPRI | WQ_FREEZABLE);
>-	if (!guc->log.relay.flush_wq) {
>-		DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
>-		return -ENOMEM;
>-	}
>-
>-	/*
>-	 * Even though both sending GuC action, and adding a new workitem to
>-	 * GuC workqueue are serialized (each with its own locking), since
>-	 * we're using mutliple engines, it's possible that we're going to
>-	 * issue a preempt request with two (or more - each for different
>-	 * engine) workitems in GuC queue. In this situation, GuC may submit
>-	 * all of them, which will make us very confused.
>-	 * Our preemption contexts may even already be complete - before we
>-	 * even had the chance to sent the preempt action to GuC!. Rather
>-	 * than introducing yet another lock, we can just use ordered workqueue
>-	 * to make sure we're always sending a single preemption request with a
>-	 * single workitem.
>-	 */
>-	if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
>-	    USES_GUC_SUBMISSION(dev_priv)) {
>-		guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt",
>-							  WQ_HIGHPRI);
>-		if (!guc->preempt_wq) {
>-			destroy_workqueue(guc->log.relay.flush_wq);
>-			DRM_ERROR("Couldn't allocate workqueue for GuC "
>-				  "preemption\n");
>-			return -ENOMEM;
>-		}
>-	}
>-
>-	return 0;
>-}
>-
>-static void guc_fini_wq(struct intel_guc *guc)
>-{
>-	struct workqueue_struct *wq;
>-
>-	wq = fetch_and_zero(&guc->preempt_wq);
>-	if (wq)
>-		destroy_workqueue(wq);
>-
>-	wq = fetch_and_zero(&guc->log.relay.flush_wq);
>-	if (wq)
>-		destroy_workqueue(wq);
>-}
>-
>-int intel_guc_init_misc(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *i915 = guc_to_i915(guc);
>-	int ret;
>-
>-	ret = guc_init_wq(guc);
>-	if (ret)
>-		return ret;
>-
>-	intel_uc_fw_fetch(i915, &guc->fw);
>-
>-	return 0;
>-}
>-
>-void intel_guc_fini_misc(struct intel_guc *guc)
>-{
>-	intel_uc_fw_cleanup_fetch(&guc->fw);
>-	guc_fini_wq(guc);
>-}
>-
>-static int guc_shared_data_create(struct intel_guc *guc)
>-{
>-	struct i915_vma *vma;
>-	void *vaddr;
>-
>-	vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
>-	if (IS_ERR(vma))
>-		return PTR_ERR(vma);
>-
>-	vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
>-	if (IS_ERR(vaddr)) {
>-		i915_vma_unpin_and_release(&vma, 0);
>-		return PTR_ERR(vaddr);
>-	}
>-
>-	guc->shared_data = vma;
>-	guc->shared_data_vaddr = vaddr;
>-
>-	return 0;
>-}
>-
>-static void guc_shared_data_destroy(struct intel_guc *guc)
>-{
>-	i915_vma_unpin_and_release(&guc->shared_data, I915_VMA_RELEASE_MAP);
>-}
>-
>-int intel_guc_init(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	int ret;
>-
>-	ret = intel_uc_fw_init(&guc->fw);
>-	if (ret)
>-		goto err_fetch;
>-
>-	ret = guc_shared_data_create(guc);
>-	if (ret)
>-		goto err_fw;
>-	GEM_BUG_ON(!guc->shared_data);
>-
>-	ret = intel_guc_log_create(&guc->log);
>-	if (ret)
>-		goto err_shared;
>-
>-	ret = intel_guc_ads_create(guc);
>-	if (ret)
>-		goto err_log;
>-	GEM_BUG_ON(!guc->ads_vma);
>-
>-	ret = intel_guc_ct_init(&guc->ct);
>-	if (ret)
>-		goto err_ads;
>-
>-	/* We need to notify the guc whenever we change the GGTT */
>-	i915_ggtt_enable_guc(dev_priv);
>-
>-	return 0;
>-
>-err_ads:
>-	intel_guc_ads_destroy(guc);
>-err_log:
>-	intel_guc_log_destroy(&guc->log);
>-err_shared:
>-	guc_shared_data_destroy(guc);
>-err_fw:
>-	intel_uc_fw_fini(&guc->fw);
>-err_fetch:
>-	intel_uc_fw_cleanup_fetch(&guc->fw);
>-	return ret;
>-}
>-
>-void intel_guc_fini(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-
>-	i915_ggtt_disable_guc(dev_priv);
>-
>-	intel_guc_ct_fini(&guc->ct);
>-
>-	intel_guc_ads_destroy(guc);
>-	intel_guc_log_destroy(&guc->log);
>-	guc_shared_data_destroy(guc);
>-	intel_uc_fw_fini(&guc->fw);
>-	intel_uc_fw_cleanup_fetch(&guc->fw);
>-}
>-
>-static u32 guc_ctl_debug_flags(struct intel_guc *guc)
>-{
>-	u32 level = intel_guc_log_get_level(&guc->log);
>-	u32 flags = 0;
>-
>-	if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
>-		flags |= GUC_LOG_DISABLED;
>-	else
>-		flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
>-			 GUC_LOG_VERBOSITY_SHIFT;
>-
>-	return flags;
>-}
>-
>-static u32 guc_ctl_feature_flags(struct intel_guc *guc)
>-{
>-	u32 flags = 0;
>-
>-	if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
>-		flags |= GUC_CTL_DISABLE_SCHEDULER;
>-
>-	return flags;
>-}
>-
>-static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
>-{
>-	u32 flags = 0;
>-
>-	if (USES_GUC_SUBMISSION(guc_to_i915(guc))) {
>-		u32 ctxnum, base;
>-
>-		base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
>-		ctxnum = GUC_MAX_STAGE_DESCRIPTORS / 16;
>-
>-		base >>= PAGE_SHIFT;
>-		flags |= (base << GUC_CTL_BASE_ADDR_SHIFT) |
>-			(ctxnum << GUC_CTL_CTXNUM_IN16_SHIFT);
>-	}
>-	return flags;
>-}
>-
>-static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
>-{
>-	u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT;
>-	u32 flags;
>-
>-	#if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0)
>-	#define UNIT SZ_1M
>-	#define FLAG GUC_LOG_ALLOC_IN_MEGABYTE
>-	#else
>-	#define UNIT SZ_4K
>-	#define FLAG 0
>-	#endif
>-
>-	BUILD_BUG_ON(!CRASH_BUFFER_SIZE);
>-	BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT));
>-	BUILD_BUG_ON(!DPC_BUFFER_SIZE);
>-	BUILD_BUG_ON(!IS_ALIGNED(DPC_BUFFER_SIZE, UNIT));
>-	BUILD_BUG_ON(!ISR_BUFFER_SIZE);
>-	BUILD_BUG_ON(!IS_ALIGNED(ISR_BUFFER_SIZE, UNIT));
>-
>-	BUILD_BUG_ON((CRASH_BUFFER_SIZE / UNIT - 1) >
>-			(GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT));
>-	BUILD_BUG_ON((DPC_BUFFER_SIZE / UNIT - 1) >
>-			(GUC_LOG_DPC_MASK >> GUC_LOG_DPC_SHIFT));
>-	BUILD_BUG_ON((ISR_BUFFER_SIZE / UNIT - 1) >
>-			(GUC_LOG_ISR_MASK >> GUC_LOG_ISR_SHIFT));
>-
>-	flags = GUC_LOG_VALID |
>-		GUC_LOG_NOTIFY_ON_HALF_FULL |
>-		FLAG |
>-		((CRASH_BUFFER_SIZE / UNIT - 1) << GUC_LOG_CRASH_SHIFT) |
>-		((DPC_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DPC_SHIFT) |
>-		((ISR_BUFFER_SIZE / UNIT - 1) << GUC_LOG_ISR_SHIFT) |
>-		(offset << GUC_LOG_BUF_ADDR_SHIFT);
>-
>-	#undef UNIT
>-	#undef FLAG
>-
>-	return flags;
>-}
>-
>-static u32 guc_ctl_ads_flags(struct intel_guc *guc)
>-{
>-	u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
>-	u32 flags = ads << GUC_ADS_ADDR_SHIFT;
>-
>-	return flags;
>-}
>-
>-/*
>- * Initialise the GuC parameter block before starting the firmware
>- * transfer. These parameters are read by the firmware on startup
>- * and cannot be changed thereafter.
>- */
>-void intel_guc_init_params(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	u32 params[GUC_CTL_MAX_DWORDS];
>-	int i;
>-
>-	memset(params, 0, sizeof(params));
>-
>-	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
>-	params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
>-	params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
>-	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
>-	params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
>-
>-	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
>-		DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
>-
>-	/*
>-	 * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
>-	 * they are power context saved so it's ok to release forcewake
>-	 * when we are done here and take it again at xfer time.
>-	 */
>-	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_BLITTER);
>-
>-	I915_WRITE(SOFT_SCRATCH(0), 0);
>-
>-	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
>-		I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
>-
>-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_BLITTER);
>-}
>-
>-int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
>-		       u32 *response_buf, u32 response_buf_size)
>-{
>-	WARN(1, "Unexpected send: action=%#x\n", *action);
>-	return -ENODEV;
>-}
>-
>-void intel_guc_to_host_event_handler_nop(struct intel_guc *guc)
>-{
>-	WARN(1, "Unexpected event: no suitable handler\n");
>-}
>-
>-/*
>- * This function implements the MMIO based host to GuC interface.
>- */
>-int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
>-			u32 *response_buf, u32 response_buf_size)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	struct intel_uncore *uncore = &dev_priv->uncore;
>-	u32 status;
>-	int i;
>-	int ret;
>-
>-	GEM_BUG_ON(!len);
>-	GEM_BUG_ON(len > guc->send_regs.count);
>-
>-	/* We expect only action code */
>-	GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK);
>-
>-	/* If CT is available, we expect to use MMIO only during init/fini */
>-	GEM_BUG_ON(*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
>-		   *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
>-
>-	mutex_lock(&guc->send_mutex);
>-	intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);
>-
>-	for (i = 0; i < len; i++)
>-		intel_uncore_write(uncore, guc_send_reg(guc, i), action[i]);
>-
>-	intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1));
>-
>-	intel_guc_notify(guc);
>-
>-	/*
>-	 * No GuC command should ever take longer than 10ms.
>-	 * Fast commands should still complete in 10us.
>-	 */
>-	ret = __intel_wait_for_register_fw(uncore,
>-					   guc_send_reg(guc, 0),
>-					   INTEL_GUC_MSG_TYPE_MASK,
>-					   INTEL_GUC_MSG_TYPE_RESPONSE <<
>-					   INTEL_GUC_MSG_TYPE_SHIFT,
>-					   10, 10, &status);
>-	/* If GuC explicitly returned an error, convert it to -EIO */
>-	if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status))
>-		ret = -EIO;
>-
>-	if (ret) {
>-		DRM_ERROR("MMIO: GuC action %#x failed with error %d %#x\n",
>-			  action[0], ret, status);
>-		goto out;
>-	}
>-
>-	if (response_buf) {
>-		int count = min(response_buf_size, guc->send_regs.count - 1);
>-
>-		for (i = 0; i < count; i++)
>-			response_buf[i] = I915_READ(guc_send_reg(guc, i + 1));
>-	}
>-
>-	/* Use data from the GuC response as our return value */
>-	ret = INTEL_GUC_MSG_TO_DATA(status);
>-
>-out:
>-	intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains);
>-	mutex_unlock(&guc->send_mutex);
>-
>-	return ret;
>-}
>-
>-int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
>-				       const u32 *payload, u32 len)
>-{
>-	u32 msg;
>-
>-	if (unlikely(!len))
>-		return -EPROTO;
>-
>-	/* Make sure to handle only enabled messages */
>-	msg = payload[0] & guc->msg_enabled_mask;
>-
>-	if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
>-		   INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
>-		intel_guc_log_handle_flush_event(&guc->log);
>-
>-	return 0;
>-}
>-
>-int intel_guc_sample_forcewake(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	u32 action[2];
>-
>-	action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
>-	/* WaRsDisableCoarsePowerGating:skl,cnl */
>-	if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
>-		action[1] = 0;
>-	else
>-		/* bit 0 and 1 are for Render and Media domain separately */
>-		action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
>-
>-	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>-}
>-
>-/**
>- * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
>- * @guc: intel_guc structure
>- * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
>- *
>- * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
>- * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
>- * intel_huc_auth().
>- *
>- * Return:	non-zero code on error
>- */
>-int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
>-{
>-	u32 action[] = {
>-		INTEL_GUC_ACTION_AUTHENTICATE_HUC,
>-		rsa_offset
>-	};
>-
>-	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>-}
>-
>-/**
>- * intel_guc_suspend() - notify GuC entering suspend state
>- * @guc:	the guc
>- */
>-int intel_guc_suspend(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	int ret;
>-	u32 status;
>-	u32 action[] = {
>-		INTEL_GUC_ACTION_ENTER_S_STATE,
>-		GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
>-	};
>-
>-	/*
>-	 * The ENTER_S_STATE action queues the save/restore operation in GuC FW
>-	 * and then returns, so waiting on the H2G is not enough to guarantee
>-	 * GuC is done. When all the processing is done, GuC writes
>-	 * INTEL_GUC_SLEEP_STATE_SUCCESS to scratch register 14, so we can poll
>-	 * on that. Note that GuC does not ensure that the value in the register
>-	 * is different from INTEL_GUC_SLEEP_STATE_SUCCESS while the action is
>-	 * in progress so we need to take care of that ourselves as well.
>-	 */
>-
>-	I915_WRITE(SOFT_SCRATCH(14), INTEL_GUC_SLEEP_STATE_INVALID_MASK);
>-
>-	ret = intel_guc_send(guc, action, ARRAY_SIZE(action));
>-	if (ret)
>-		return ret;
>-
>-	ret = __intel_wait_for_register(&dev_priv->uncore, SOFT_SCRATCH(14),
>-					INTEL_GUC_SLEEP_STATE_INVALID_MASK,
>-					0, 0, 10, &status);
>-	if (ret)
>-		return ret;
>-
>-	if (status != INTEL_GUC_SLEEP_STATE_SUCCESS) {
>-		DRM_ERROR("GuC failed to change sleep state. "
>-			  "action=0x%x, err=%u\n",
>-			  action[0], status);
>-		return -EIO;
>-	}
>-
>-	return 0;
>-}
>-
>-/**
>- * intel_guc_reset_engine() - ask GuC to reset an engine
>- * @guc:	intel_guc structure
>- * @engine:	engine to be reset
>- */
>-int intel_guc_reset_engine(struct intel_guc *guc,
>-			   struct intel_engine_cs *engine)
>-{
>-	u32 data[7];
>-
>-	GEM_BUG_ON(!guc->execbuf_client);
>-
>-	data[0] = INTEL_GUC_ACTION_REQUEST_ENGINE_RESET;
>-	data[1] = engine->guc_id;
>-	data[2] = 0;
>-	data[3] = 0;
>-	data[4] = 0;
>-	data[5] = guc->execbuf_client->stage_id;
>-	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
>-
>-	return intel_guc_send(guc, data, ARRAY_SIZE(data));
>-}
>-
>-/**
>- * intel_guc_resume() - notify GuC resuming from suspend state
>- * @guc:	the guc
>- */
>-int intel_guc_resume(struct intel_guc *guc)
>-{
>-	u32 action[] = {
>-		INTEL_GUC_ACTION_EXIT_S_STATE,
>-		GUC_POWER_D0,
>-	};
>-
>-	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>-}
>-
>-/**
>- * DOC: GuC Address Space
>- *
>- * The layout of GuC address space is shown below:
>- *
>- * ::
>- *
>- *     +===========> +====================+ <== FFFF_FFFF
>- *     ^             |      Reserved      |
>- *     |             +====================+ <== GUC_GGTT_TOP
>- *     |             |                    |
>- *     |             |        DRAM        |
>- *    GuC            |                    |
>- *  Address    +===> +====================+ <== GuC ggtt_pin_bias
>- *   Space     ^     |                    |
>- *     |       |     |                    |
>- *     |      GuC    |        GuC         |
>- *     |     WOPCM   |       WOPCM        |
>- *     |      Size   |                    |
>- *     |       |     |                    |
>- *     v       v     |                    |
>- *     +=======+===> +====================+ <== 0000_0000
>- *
>- * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM
>- * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
>- * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
>- */
>-
>-/**
>- * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
>- * @guc:	the guc
>- * @size:	size of area to allocate (both virtual space and memory)
>- *
>- * This is a wrapper to create an object for use with the GuC. In order to
>- * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
>- * both some backing storage and a range inside the Global GTT. We must pin
>- * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
>- * range is reserved inside GuC.
>- *
>- * Return:	A i915_vma if successful, otherwise an ERR_PTR.
>- */
>-struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	struct drm_i915_gem_object *obj;
>-	struct i915_vma *vma;
>-	u64 flags;
>-	int ret;
>-
>-	obj = i915_gem_object_create_shmem(dev_priv, size);
>-	if (IS_ERR(obj))
>-		return ERR_CAST(obj);
>-
>-	vma = i915_vma_instance(obj, &dev_priv->ggtt.vm, NULL);
>-	if (IS_ERR(vma))
>-		goto err;
>-
>-	flags = PIN_GLOBAL | PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
>-	ret = i915_vma_pin(vma, 0, 0, flags);
>-	if (ret) {
>-		vma = ERR_PTR(ret);
>-		goto err;
>-	}
>-
>-	return vma;
>-
>-err:
>-	i915_gem_object_put(obj);
>-	return vma;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_ct.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_ct.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_ct.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_ct.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,929 +0,0 @@
>-/*
>- * Copyright Â© 2016-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- */
>-
>-#include "i915_drv.h"
>-#include "intel_guc_ct.h"
>-
>-#ifdef CONFIG_DRM_I915_DEBUG_GUC
>-#define CT_DEBUG_DRIVER(...)	DRM_DEBUG_DRIVER(__VA_ARGS__)
>-#else
>-#define CT_DEBUG_DRIVER(...)	do { } while (0)
>-#endif
>-
>-struct ct_request {
>-	struct list_head link;
>-	u32 fence;
>-	u32 status;
>-	u32 response_len;
>-	u32 *response_buf;
>-};
>-
>-struct ct_incoming_request {
>-	struct list_head link;
>-	u32 msg[];
>-};
>-
>-enum { CTB_SEND = 0, CTB_RECV = 1 };
>-
>-enum { CTB_OWNER_HOST = 0 };
>-
>-static void ct_incoming_request_worker_func(struct work_struct *w);
>-
>-/**
>- * intel_guc_ct_init_early - Initialize CT state without requiring device access
>- * @ct: pointer to CT struct
>- */
>-void intel_guc_ct_init_early(struct intel_guc_ct *ct)
>-{
>-	/* we're using static channel owners */
>-	ct->host_channel.owner = CTB_OWNER_HOST;
>-
>-	spin_lock_init(&ct->lock);
>-	INIT_LIST_HEAD(&ct->pending_requests);
>-	INIT_LIST_HEAD(&ct->incoming_requests);
>-	INIT_WORK(&ct->worker, ct_incoming_request_worker_func);
>-}
>-
>-static inline struct intel_guc *ct_to_guc(struct intel_guc_ct *ct)
>-{
>-	return container_of(ct, struct intel_guc, ct);
>-}
>-
>-static inline const char *guc_ct_buffer_type_to_str(u32 type)
>-{
>-	switch (type) {
>-	case INTEL_GUC_CT_BUFFER_TYPE_SEND:
>-		return "SEND";
>-	case INTEL_GUC_CT_BUFFER_TYPE_RECV:
>-		return "RECV";
>-	default:
>-		return "<invalid>";
>-	}
>-}
>-
>-static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc,
>-				    u32 cmds_addr, u32 size, u32 owner)
>-{
>-	CT_DEBUG_DRIVER("CT: desc %p init addr=%#x size=%u owner=%u\n",
>-			desc, cmds_addr, size, owner);
>-	memset(desc, 0, sizeof(*desc));
>-	desc->addr = cmds_addr;
>-	desc->size = size;
>-	desc->owner = owner;
>-}
>-
>-static void guc_ct_buffer_desc_reset(struct guc_ct_buffer_desc *desc)
>-{
>-	CT_DEBUG_DRIVER("CT: desc %p reset head=%u tail=%u\n",
>-			desc, desc->head, desc->tail);
>-	desc->head = 0;
>-	desc->tail = 0;
>-	desc->is_in_error = 0;
>-}
>-
>-static int guc_action_register_ct_buffer(struct intel_guc *guc,
>-					 u32 desc_addr,
>-					 u32 type)
>-{
>-	u32 action[] = {
>-		INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER,
>-		desc_addr,
>-		sizeof(struct guc_ct_buffer_desc),
>-		type
>-	};
>-	int err;
>-
>-	/* Can't use generic send(), CT registration must go over MMIO */
>-	err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
>-	if (err)
>-		DRM_ERROR("CT: register %s buffer failed; err=%d\n",
>-			  guc_ct_buffer_type_to_str(type), err);
>-	return err;
>-}
>-
>-static int guc_action_deregister_ct_buffer(struct intel_guc *guc,
>-					   u32 owner,
>-					   u32 type)
>-{
>-	u32 action[] = {
>-		INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER,
>-		owner,
>-		type
>-	};
>-	int err;
>-
>-	/* Can't use generic send(), CT deregistration must go over MMIO */
>-	err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
>-	if (err)
>-		DRM_ERROR("CT: deregister %s buffer failed; owner=%d err=%d\n",
>-			  guc_ct_buffer_type_to_str(type), owner, err);
>-	return err;
>-}
>-
>-static int ctch_init(struct intel_guc *guc,
>-		     struct intel_guc_ct_channel *ctch)
>-{
>-	struct i915_vma *vma;
>-	void *blob;
>-	int err;
>-	int i;
>-
>-	GEM_BUG_ON(ctch->vma);
>-
>-	/* We allocate 1 page to hold both descriptors and both buffers.
>-	 *       ___________.....................
>-	 *      |desc (SEND)|                   :
>-	 *      |___________|                   PAGE/4
>-	 *      :___________....................:
>-	 *      |desc (RECV)|                   :
>-	 *      |___________|                   PAGE/4
>-	 *      :_______________________________:
>-	 *      |cmds (SEND)                    |
>-	 *      |                               PAGE/4
>-	 *      |_______________________________|
>-	 *      |cmds (RECV)                    |
>-	 *      |                               PAGE/4
>-	 *      |_______________________________|
>-	 *
>-	 * Each message can use a maximum of 32 dwords and we don't expect to
>-	 * have more than 1 in flight at any time, so we have enough space.
>-	 * Some logic further ahead will rely on the fact that there is only 1
>-	 * page and that it is always mapped, so if the size is changed the
>-	 * other code will need updating as well.
>-	 */
>-
>-	/* allocate vma */
>-	vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
>-	if (IS_ERR(vma)) {
>-		err = PTR_ERR(vma);
>-		goto err_out;
>-	}
>-	ctch->vma = vma;
>-
>-	/* map first page */
>-	blob = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
>-	if (IS_ERR(blob)) {
>-		err = PTR_ERR(blob);
>-		goto err_vma;
>-	}
>-	CT_DEBUG_DRIVER("CT: vma base=%#x\n",
>-			intel_guc_ggtt_offset(guc, ctch->vma));
>-
>-	/* store pointers to desc and cmds */
>-	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
>-		GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
>-		ctch->ctbs[i].desc = blob + PAGE_SIZE/4 * i;
>-		ctch->ctbs[i].cmds = blob + PAGE_SIZE/4 * i + PAGE_SIZE/2;
>-	}
>-
>-	return 0;
>-
>-err_vma:
>-	i915_vma_unpin_and_release(&ctch->vma, 0);
>-err_out:
>-	CT_DEBUG_DRIVER("CT: channel %d initialization failed; err=%d\n",
>-			ctch->owner, err);
>-	return err;
>-}
>-
>-static void ctch_fini(struct intel_guc *guc,
>-		      struct intel_guc_ct_channel *ctch)
>-{
>-	GEM_BUG_ON(ctch->enabled);
>-
>-	i915_vma_unpin_and_release(&ctch->vma, I915_VMA_RELEASE_MAP);
>-}
>-
>-static int ctch_enable(struct intel_guc *guc,
>-		       struct intel_guc_ct_channel *ctch)
>-{
>-	u32 base;
>-	int err;
>-	int i;
>-
>-	GEM_BUG_ON(!ctch->vma);
>-
>-	GEM_BUG_ON(ctch->enabled);
>-
>-	/* vma should be already allocated and map'ed */
>-	base = intel_guc_ggtt_offset(guc, ctch->vma);
>-
>-	/* (re)initialize descriptors
>-	 * cmds buffers are in the second half of the blob page
>-	 */
>-	for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) {
>-		GEM_BUG_ON((i != CTB_SEND) && (i != CTB_RECV));
>-		guc_ct_buffer_desc_init(ctch->ctbs[i].desc,
>-					base + PAGE_SIZE/4 * i + PAGE_SIZE/2,
>-					PAGE_SIZE/4,
>-					ctch->owner);
>-	}
>-
>-	/* register buffers, starting wirh RECV buffer
>-	 * descriptors are in first half of the blob
>-	 */
>-	err = guc_action_register_ct_buffer(guc,
>-					    base + PAGE_SIZE/4 * CTB_RECV,
>-					    INTEL_GUC_CT_BUFFER_TYPE_RECV);
>-	if (unlikely(err))
>-		goto err_out;
>-
>-	err = guc_action_register_ct_buffer(guc,
>-					    base + PAGE_SIZE/4 * CTB_SEND,
>-					    INTEL_GUC_CT_BUFFER_TYPE_SEND);
>-	if (unlikely(err))
>-		goto err_deregister;
>-
>-	ctch->enabled = true;
>-
>-	return 0;
>-
>-err_deregister:
>-	guc_action_deregister_ct_buffer(guc,
>-					ctch->owner,
>-					INTEL_GUC_CT_BUFFER_TYPE_RECV);
>-err_out:
>-	DRM_ERROR("CT: can't open channel %d; err=%d\n", ctch->owner, err);
>-	return err;
>-}
>-
>-static void ctch_disable(struct intel_guc *guc,
>-			 struct intel_guc_ct_channel *ctch)
>-{
>-	GEM_BUG_ON(!ctch->enabled);
>-
>-	ctch->enabled = false;
>-
>-	guc_action_deregister_ct_buffer(guc,
>-					ctch->owner,
>-					INTEL_GUC_CT_BUFFER_TYPE_SEND);
>-	guc_action_deregister_ct_buffer(guc,
>-					ctch->owner,
>-					INTEL_GUC_CT_BUFFER_TYPE_RECV);
>-}
>-
>-static u32 ctch_get_next_fence(struct intel_guc_ct_channel *ctch)
>-{
>-	/* For now it's trivial */
>-	return ++ctch->next_fence;
>-}
>-
>-/**
>- * DOC: CTB Host to GuC request
>- *
>- * Format of the CTB Host to GuC request message is as follows::
>- *
>- *      +------------+---------+---------+---------+---------+
>- *      |   msg[0]   |   [1]   |   [2]   |   ...   |  [n-1]  |
>- *      +------------+---------+---------+---------+---------+
>- *      |   MESSAGE  |       MESSAGE PAYLOAD                 |
>- *      +   HEADER   +---------+---------+---------+---------+
>- *      |            |    0    |    1    |   ...   |    n    |
>- *      +============+=========+=========+=========+=========+
>- *      |  len >= 1  |  FENCE  |     request specific data   |
>- *      +------+-----+---------+---------+---------+---------+
>- *
>- *                   ^-----------------len-------------------^
>- */
>-
>-static int ctb_write(struct intel_guc_ct_buffer *ctb,
>-		     const u32 *action,
>-		     u32 len /* in dwords */,
>-		     u32 fence,
>-		     bool want_response)
>-{
>-	struct guc_ct_buffer_desc *desc = ctb->desc;
>-	u32 head = desc->head / 4;	/* in dwords */
>-	u32 tail = desc->tail / 4;	/* in dwords */
>-	u32 size = desc->size / 4;	/* in dwords */
>-	u32 used;			/* in dwords */
>-	u32 header;
>-	u32 *cmds = ctb->cmds;
>-	unsigned int i;
>-
>-	GEM_BUG_ON(desc->size % 4);
>-	GEM_BUG_ON(desc->head % 4);
>-	GEM_BUG_ON(desc->tail % 4);
>-	GEM_BUG_ON(tail >= size);
>-
>-	/*
>-	 * tail == head condition indicates empty. GuC FW does not support
>-	 * using up the entire buffer to get tail == head meaning full.
>-	 */
>-	if (tail < head)
>-		used = (size - head) + tail;
>-	else
>-		used = tail - head;
>-
>-	/* make sure there is a space including extra dw for the fence */
>-	if (unlikely(used + len + 1 >= size))
>-		return -ENOSPC;
>-
>-	/*
>-	 * Write the message. The format is the following:
>-	 * DW0: header (including action code)
>-	 * DW1: fence
>-	 * DW2+: action data
>-	 */
>-	header = (len << GUC_CT_MSG_LEN_SHIFT) |
>-		 (GUC_CT_MSG_WRITE_FENCE_TO_DESC) |
>-		 (want_response ? GUC_CT_MSG_SEND_STATUS : 0) |
>-		 (action[0] << GUC_CT_MSG_ACTION_SHIFT);
>-
>-	CT_DEBUG_DRIVER("CT: writing %*ph %*ph %*ph\n",
>-			4, &header, 4, &fence,
>-			4 * (len - 1), &action[1]);
>-
>-	cmds[tail] = header;
>-	tail = (tail + 1) % size;
>-
>-	cmds[tail] = fence;
>-	tail = (tail + 1) % size;
>-
>-	for (i = 1; i < len; i++) {
>-		cmds[tail] = action[i];
>-		tail = (tail + 1) % size;
>-	}
>-
>-	/* now update desc tail (back in bytes) */
>-	desc->tail = tail * 4;
>-	GEM_BUG_ON(desc->tail > desc->size);
>-
>-	return 0;
>-}
>-
>-/**
>- * wait_for_ctb_desc_update - Wait for the CT buffer descriptor update.
>- * @desc:	buffer descriptor
>- * @fence:	response fence
>- * @status:	placeholder for status
>- *
>- * Guc will update CT buffer descriptor with new fence and status
>- * after processing the command identified by the fence. Wait for
>- * specified fence and then read from the descriptor status of the
>- * command.
>- *
>- * Return:
>- * *	0 response received (status is valid)
>- * *	-ETIMEDOUT no response within hardcoded timeout
>- * *	-EPROTO no response, CT buffer is in error
>- */
>-static int wait_for_ctb_desc_update(struct guc_ct_buffer_desc *desc,
>-				    u32 fence,
>-				    u32 *status)
>-{
>-	int err;
>-
>-	/*
>-	 * Fast commands should complete in less than 10us, so sample quickly
>-	 * up to that length of time, then switch to a slower sleep-wait loop.
>-	 * No GuC command should ever take longer than 10ms.
>-	 */
>-#define done (READ_ONCE(desc->fence) == fence)
>-	err = wait_for_us(done, 10);
>-	if (err)
>-		err = wait_for(done, 10);
>-#undef done
>-
>-	if (unlikely(err)) {
>-		DRM_ERROR("CT: fence %u failed; reported fence=%u\n",
>-			  fence, desc->fence);
>-
>-		if (WARN_ON(desc->is_in_error)) {
>-			/* Something went wrong with the messaging, try to reset
>-			 * the buffer and hope for the best
>-			 */
>-			guc_ct_buffer_desc_reset(desc);
>-			err = -EPROTO;
>-		}
>-	}
>-
>-	*status = desc->status;
>-	return err;
>-}
>-
>-/**
>- * wait_for_ct_request_update - Wait for CT request state update.
>- * @req:	pointer to pending request
>- * @status:	placeholder for status
>- *
>- * For each sent request, Guc shall send bac CT response message.
>- * Our message handler will update status of tracked request once
>- * response message with given fence is received. Wait here and
>- * check for valid response status value.
>- *
>- * Return:
>- * *	0 response received (status is valid)
>- * *	-ETIMEDOUT no response within hardcoded timeout
>- */
>-static int wait_for_ct_request_update(struct ct_request *req, u32 *status)
>-{
>-	int err;
>-
>-	/*
>-	 * Fast commands should complete in less than 10us, so sample quickly
>-	 * up to that length of time, then switch to a slower sleep-wait loop.
>-	 * No GuC command should ever take longer than 10ms.
>-	 */
>-#define done INTEL_GUC_MSG_IS_RESPONSE(READ_ONCE(req->status))
>-	err = wait_for_us(done, 10);
>-	if (err)
>-		err = wait_for(done, 10);
>-#undef done
>-
>-	if (unlikely(err))
>-		DRM_ERROR("CT: fence %u err %d\n", req->fence, err);
>-
>-	*status = req->status;
>-	return err;
>-}
>-
>-static int ctch_send(struct intel_guc_ct *ct,
>-		     struct intel_guc_ct_channel *ctch,
>-		     const u32 *action,
>-		     u32 len,
>-		     u32 *response_buf,
>-		     u32 response_buf_size,
>-		     u32 *status)
>-{
>-	struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_SEND];
>-	struct guc_ct_buffer_desc *desc = ctb->desc;
>-	struct ct_request request;
>-	unsigned long flags;
>-	u32 fence;
>-	int err;
>-
>-	GEM_BUG_ON(!ctch->enabled);
>-	GEM_BUG_ON(!len);
>-	GEM_BUG_ON(len & ~GUC_CT_MSG_LEN_MASK);
>-	GEM_BUG_ON(!response_buf && response_buf_size);
>-
>-	fence = ctch_get_next_fence(ctch);
>-	request.fence = fence;
>-	request.status = 0;
>-	request.response_len = response_buf_size;
>-	request.response_buf = response_buf;
>-
>-	spin_lock_irqsave(&ct->lock, flags);
>-	list_add_tail(&request.link, &ct->pending_requests);
>-	spin_unlock_irqrestore(&ct->lock, flags);
>-
>-	err = ctb_write(ctb, action, len, fence, !!response_buf);
>-	if (unlikely(err))
>-		goto unlink;
>-
>-	intel_guc_notify(ct_to_guc(ct));
>-
>-	if (response_buf)
>-		err = wait_for_ct_request_update(&request, status);
>-	else
>-		err = wait_for_ctb_desc_update(desc, fence, status);
>-	if (unlikely(err))
>-		goto unlink;
>-
>-	if (!INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(*status)) {
>-		err = -EIO;
>-		goto unlink;
>-	}
>-
>-	if (response_buf) {
>-		/* There shall be no data in the status */
>-		WARN_ON(INTEL_GUC_MSG_TO_DATA(request.status));
>-		/* Return actual response len */
>-		err = request.response_len;
>-	} else {
>-		/* There shall be no response payload */
>-		WARN_ON(request.response_len);
>-		/* Return data decoded from the status dword */
>-		err = INTEL_GUC_MSG_TO_DATA(*status);
>-	}
>-
>-unlink:
>-	spin_lock_irqsave(&ct->lock, flags);
>-	list_del(&request.link);
>-	spin_unlock_irqrestore(&ct->lock, flags);
>-
>-	return err;
>-}
>-
>-/*
>- * Command Transport (CT) buffer based GuC send function.
>- */
>-static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
>-			     u32 *response_buf, u32 response_buf_size)
>-{
>-	struct intel_guc_ct *ct = &guc->ct;
>-	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>-	u32 status = ~0; /* undefined */
>-	int ret;
>-
>-	mutex_lock(&guc->send_mutex);
>-
>-	ret = ctch_send(ct, ctch, action, len, response_buf, response_buf_size,
>-			&status);
>-	if (unlikely(ret < 0)) {
>-		DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n",
>-			  action[0], ret, status);
>-	} else if (unlikely(ret)) {
>-		CT_DEBUG_DRIVER("CT: send action %#x returned %d (%#x)\n",
>-				action[0], ret, ret);
>-	}
>-
>-	mutex_unlock(&guc->send_mutex);
>-	return ret;
>-}
>-
>-static inline unsigned int ct_header_get_len(u32 header)
>-{
>-	return (header >> GUC_CT_MSG_LEN_SHIFT) & GUC_CT_MSG_LEN_MASK;
>-}
>-
>-static inline unsigned int ct_header_get_action(u32 header)
>-{
>-	return (header >> GUC_CT_MSG_ACTION_SHIFT) & GUC_CT_MSG_ACTION_MASK;
>-}
>-
>-static inline bool ct_header_is_response(u32 header)
>-{
>-	return !!(header & GUC_CT_MSG_IS_RESPONSE);
>-}
>-
>-static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data)
>-{
>-	struct guc_ct_buffer_desc *desc = ctb->desc;
>-	u32 head = desc->head / 4;	/* in dwords */
>-	u32 tail = desc->tail / 4;	/* in dwords */
>-	u32 size = desc->size / 4;	/* in dwords */
>-	u32 *cmds = ctb->cmds;
>-	s32 available;			/* in dwords */
>-	unsigned int len;
>-	unsigned int i;
>-
>-	GEM_BUG_ON(desc->size % 4);
>-	GEM_BUG_ON(desc->head % 4);
>-	GEM_BUG_ON(desc->tail % 4);
>-	GEM_BUG_ON(tail >= size);
>-	GEM_BUG_ON(head >= size);
>-
>-	/* tail == head condition indicates empty */
>-	available = tail - head;
>-	if (unlikely(available == 0))
>-		return -ENODATA;
>-
>-	/* beware of buffer wrap case */
>-	if (unlikely(available < 0))
>-		available += size;
>-	CT_DEBUG_DRIVER("CT: available %d (%u:%u)\n", available, head, tail);
>-	GEM_BUG_ON(available < 0);
>-
>-	data[0] = cmds[head];
>-	head = (head + 1) % size;
>-
>-	/* message len with header */
>-	len = ct_header_get_len(data[0]) + 1;
>-	if (unlikely(len > (u32)available)) {
>-		DRM_ERROR("CT: incomplete message %*ph %*ph %*ph\n",
>-			  4, data,
>-			  4 * (head + available - 1 > size ?
>-			       size - head : available - 1), &cmds[head],
>-			  4 * (head + available - 1 > size ?
>-			       available - 1 - size + head : 0), &cmds[0]);
>-		return -EPROTO;
>-	}
>-
>-	for (i = 1; i < len; i++) {
>-		data[i] = cmds[head];
>-		head = (head + 1) % size;
>-	}
>-	CT_DEBUG_DRIVER("CT: received %*ph\n", 4 * len, data);
>-
>-	desc->head = head * 4;
>-	return 0;
>-}
>-
>-/**
>- * DOC: CTB GuC to Host response
>- *
>- * Format of the CTB GuC to Host response message is as follows::
>- *
>- *      +------------+---------+---------+---------+---------+---------+
>- *      |   msg[0]   |   [1]   |   [2]   |   [3]   |   ...   |  [n-1]  |
>- *      +------------+---------+---------+---------+---------+---------+
>- *      |   MESSAGE  |       MESSAGE PAYLOAD                           |
>- *      +   HEADER   +---------+---------+---------+---------+---------+
>- *      |            |    0    |    1    |    2    |   ...   |    n    |
>- *      +============+=========+=========+=========+=========+=========+
>- *      |  len >= 2  |  FENCE  |  STATUS |   response specific data    |
>- *      +------+-----+---------+---------+---------+---------+---------+
>- *
>- *                   ^-----------------------len-----------------------^
>- */
>-
>-static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg)
>-{
>-	u32 header = msg[0];
>-	u32 len = ct_header_get_len(header);
>-	u32 msglen = len + 1; /* total message length including header */
>-	u32 fence;
>-	u32 status;
>-	u32 datalen;
>-	struct ct_request *req;
>-	bool found = false;
>-
>-	GEM_BUG_ON(!ct_header_is_response(header));
>-	GEM_BUG_ON(!in_irq());
>-
>-	/* Response payload shall at least include fence and status */
>-	if (unlikely(len < 2)) {
>-		DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
>-		return -EPROTO;
>-	}
>-
>-	fence = msg[1];
>-	status = msg[2];
>-	datalen = len - 2;
>-
>-	/* Format of the status follows RESPONSE message */
>-	if (unlikely(!INTEL_GUC_MSG_IS_RESPONSE(status))) {
>-		DRM_ERROR("CT: corrupted response %*ph\n", 4 * msglen, msg);
>-		return -EPROTO;
>-	}
>-
>-	CT_DEBUG_DRIVER("CT: response fence %u status %#x\n", fence, status);
>-
>-	spin_lock(&ct->lock);
>-	list_for_each_entry(req, &ct->pending_requests, link) {
>-		if (unlikely(fence != req->fence)) {
>-			CT_DEBUG_DRIVER("CT: request %u awaits response\n",
>-					req->fence);
>-			continue;
>-		}
>-		if (unlikely(datalen > req->response_len)) {
>-			DRM_ERROR("CT: response %u too long %*ph\n",
>-				  req->fence, 4 * msglen, msg);
>-			datalen = 0;
>-		}
>-		if (datalen)
>-			memcpy(req->response_buf, msg + 3, 4 * datalen);
>-		req->response_len = datalen;
>-		WRITE_ONCE(req->status, status);
>-		found = true;
>-		break;
>-	}
>-	spin_unlock(&ct->lock);
>-
>-	if (!found)
>-		DRM_ERROR("CT: unsolicited response %*ph\n", 4 * msglen, msg);
>-	return 0;
>-}
>-
>-static void ct_process_request(struct intel_guc_ct *ct,
>-			       u32 action, u32 len, const u32 *payload)
>-{
>-	struct intel_guc *guc = ct_to_guc(ct);
>-	int ret;
>-
>-	CT_DEBUG_DRIVER("CT: request %x %*ph\n", action, 4 * len, payload);
>-
>-	switch (action) {
>-	case INTEL_GUC_ACTION_DEFAULT:
>-		ret = intel_guc_to_host_process_recv_msg(guc, payload, len);
>-		if (unlikely(ret))
>-			goto fail_unexpected;
>-		break;
>-
>-	default:
>-fail_unexpected:
>-		DRM_ERROR("CT: unexpected request %x %*ph\n",
>-			  action, 4 * len, payload);
>-		break;
>-	}
>-}
>-
>-static bool ct_process_incoming_requests(struct intel_guc_ct *ct)
>-{
>-	unsigned long flags;
>-	struct ct_incoming_request *request;
>-	u32 header;
>-	u32 *payload;
>-	bool done;
>-
>-	spin_lock_irqsave(&ct->lock, flags);
>-	request = list_first_entry_or_null(&ct->incoming_requests,
>-					   struct ct_incoming_request, link);
>-	if (request)
>-		list_del(&request->link);
>-	done = !!list_empty(&ct->incoming_requests);
>-	spin_unlock_irqrestore(&ct->lock, flags);
>-
>-	if (!request)
>-		return true;
>-
>-	header = request->msg[0];
>-	payload = &request->msg[1];
>-	ct_process_request(ct,
>-			   ct_header_get_action(header),
>-			   ct_header_get_len(header),
>-			   payload);
>-
>-	kfree(request);
>-	return done;
>-}
>-
>-static void ct_incoming_request_worker_func(struct work_struct *w)
>-{
>-	struct intel_guc_ct *ct = container_of(w, struct intel_guc_ct, worker);
>-	bool done;
>-
>-	done = ct_process_incoming_requests(ct);
>-	if (!done)
>-		queue_work(system_unbound_wq, &ct->worker);
>-}
>-
>-/**
>- * DOC: CTB GuC to Host request
>- *
>- * Format of the CTB GuC to Host request message is as follows::
>- *
>- *      +------------+---------+---------+---------+---------+---------+
>- *      |   msg[0]   |   [1]   |   [2]   |   [3]   |   ...   |  [n-1]  |
>- *      +------------+---------+---------+---------+---------+---------+
>- *      |   MESSAGE  |       MESSAGE PAYLOAD                           |
>- *      +   HEADER   +---------+---------+---------+---------+---------+
>- *      |            |    0    |    1    |    2    |   ...   |    n    |
>- *      +============+=========+=========+=========+=========+=========+
>- *      |     len    |            request specific data                |
>- *      +------+-----+---------+---------+---------+---------+---------+
>- *
>- *                   ^-----------------------len-----------------------^
>- */
>-
>-static int ct_handle_request(struct intel_guc_ct *ct, const u32 *msg)
>-{
>-	u32 header = msg[0];
>-	u32 len = ct_header_get_len(header);
>-	u32 msglen = len + 1; /* total message length including header */
>-	struct ct_incoming_request *request;
>-	unsigned long flags;
>-
>-	GEM_BUG_ON(ct_header_is_response(header));
>-
>-	request = kmalloc(sizeof(*request) + 4 * msglen, GFP_ATOMIC);
>-	if (unlikely(!request)) {
>-		DRM_ERROR("CT: dropping request %*ph\n", 4 * msglen, msg);
>-		return 0; /* XXX: -ENOMEM ? */
>-	}
>-	memcpy(request->msg, msg, 4 * msglen);
>-
>-	spin_lock_irqsave(&ct->lock, flags);
>-	list_add_tail(&request->link, &ct->incoming_requests);
>-	spin_unlock_irqrestore(&ct->lock, flags);
>-
>-	queue_work(system_unbound_wq, &ct->worker);
>-	return 0;
>-}
>-
>-static void ct_process_host_channel(struct intel_guc_ct *ct)
>-{
>-	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>-	struct intel_guc_ct_buffer *ctb = &ctch->ctbs[CTB_RECV];
>-	u32 msg[GUC_CT_MSG_LEN_MASK + 1]; /* one extra dw for the header */
>-	int err = 0;
>-
>-	if (!ctch->enabled)
>-		return;
>-
>-	do {
>-		err = ctb_read(ctb, msg);
>-		if (err)
>-			break;
>-
>-		if (ct_header_is_response(msg[0]))
>-			err = ct_handle_response(ct, msg);
>-		else
>-			err = ct_handle_request(ct, msg);
>-	} while (!err);
>-
>-	if (GEM_WARN_ON(err == -EPROTO)) {
>-		DRM_ERROR("CT: corrupted message detected!\n");
>-		ctb->desc->is_in_error = 1;
>-	}
>-}
>-
>-/*
>- * When we're communicating with the GuC over CT, GuC uses events
>- * to notify us about new messages being posted on the RECV buffer.
>- */
>-static void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
>-{
>-	struct intel_guc_ct *ct = &guc->ct;
>-
>-	ct_process_host_channel(ct);
>-}
>-
>-/**
>- * intel_guc_ct_init - Init CT communication
>- * @ct: pointer to CT struct
>- *
>- * Allocate memory required for communication via
>- * the CT channel.
>- *
>- * Return: 0 on success, a negative errno code on failure.
>- */
>-int intel_guc_ct_init(struct intel_guc_ct *ct)
>-{
>-	struct intel_guc *guc = ct_to_guc(ct);
>-	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>-	int err;
>-
>-	err = ctch_init(guc, ctch);
>-	if (unlikely(err)) {
>-		DRM_ERROR("CT: can't open channel %d; err=%d\n",
>-			  ctch->owner, err);
>-		return err;
>-	}
>-
>-	GEM_BUG_ON(!ctch->vma);
>-	return 0;
>-}
>-
>-/**
>- * intel_guc_ct_fini - Fini CT communication
>- * @ct: pointer to CT struct
>- *
>- * Deallocate memory required for communication via
>- * the CT channel.
>- */
>-void intel_guc_ct_fini(struct intel_guc_ct *ct)
>-{
>-	struct intel_guc *guc = ct_to_guc(ct);
>-	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>-
>-	ctch_fini(guc, ctch);
>-}
>-
>-/**
>- * intel_guc_ct_enable - Enable buffer based command transport.
>- * @ct: pointer to CT struct
>- *
>- * Return: 0 on success, a negative errno code on failure.
>- */
>-int intel_guc_ct_enable(struct intel_guc_ct *ct)
>-{
>-	struct intel_guc *guc = ct_to_guc(ct);
>-	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>-	int err;
>-
>-	if (ctch->enabled)
>-		return 0;
>-
>-	err = ctch_enable(guc, ctch);
>-	if (unlikely(err))
>-		return err;
>-
>-	/* Switch into cmd transport buffer based send() */
>-	guc->send = intel_guc_send_ct;
>-	guc->handler = intel_guc_to_host_event_handler_ct;
>-	DRM_INFO("CT: %s\n", enableddisabled(true));
>-	return 0;
>-}
>-
>-/**
>- * intel_guc_ct_disable - Disable buffer based command transport.
>- * @ct: pointer to CT struct
>- */
>-void intel_guc_ct_disable(struct intel_guc_ct *ct)
>-{
>-	struct intel_guc *guc = ct_to_guc(ct);
>-	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>-
>-	if (!ctch->enabled)
>-		return;
>-
>-	ctch_disable(guc, ctch);
>-
>-	/* Disable send */
>-	guc->send = intel_guc_send_nop;
>-	guc->handler = intel_guc_to_host_event_handler_nop;
>-	DRM_INFO("CT: %s\n", enableddisabled(false));
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_ct.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_ct.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_ct.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_ct.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,104 +0,0 @@
>-/*
>- * Copyright Â© 2016-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- */
>-
>-#ifndef _INTEL_GUC_CT_H_
>-#define _INTEL_GUC_CT_H_
>-
>-struct intel_guc;
>-struct i915_vma;
>-
>-#include "intel_guc_fwif.h"
>-
>-/**
>- * DOC: Command Transport (CT).
>- *
>- * Buffer based command transport is a replacement for MMIO based mechanism.
>- * It can be used to perform both host-2-guc and guc-to-host communication.
>- */
>-
>-/** Represents single command transport buffer.
>- *
>- * A single command transport buffer consists of two parts, the header
>- * record (command transport buffer descriptor) and the actual buffer which
>- * holds the commands.
>- *
>- * @desc: pointer to the buffer descriptor
>- * @cmds: pointer to the commands buffer
>- */
>-struct intel_guc_ct_buffer {
>-	struct guc_ct_buffer_desc *desc;
>-	u32 *cmds;
>-};
>-
>-/** Represents pair of command transport buffers.
>- *
>- * Buffers go in pairs to allow bi-directional communication.
>- * To simplify the code we place both of them in the same vma.
>- * Buffers from the same pair must share unique owner id.
>- *
>- * @vma: pointer to the vma with pair of CT buffers
>- * @ctbs: buffers for sending(0) and receiving(1) commands
>- * @owner: unique identifier
>- * @next_fence: fence to be used with next send command
>- */
>-struct intel_guc_ct_channel {
>-	struct i915_vma *vma;
>-	struct intel_guc_ct_buffer ctbs[2];
>-	u32 owner;
>-	u32 next_fence;
>-	bool enabled;
>-};
>-
>-/** Holds all command transport channels.
>- *
>- * @host_channel: main channel used by the host
>- */
>-struct intel_guc_ct {
>-	struct intel_guc_ct_channel host_channel;
>-	/* other channels are tbd */
>-
>-	/** @lock: protects pending requests list */
>-	spinlock_t lock;
>-
>-	/** @pending_requests: list of requests waiting for response */
>-	struct list_head pending_requests;
>-
>-	/** @incoming_requests: list of incoming requests */
>-	struct list_head incoming_requests;
>-
>-	/** @worker: worker for handling incoming requests */
>-	struct work_struct worker;
>-};
>-
>-void intel_guc_ct_init_early(struct intel_guc_ct *ct);
>-int intel_guc_ct_init(struct intel_guc_ct *ct);
>-void intel_guc_ct_fini(struct intel_guc_ct *ct);
>-int intel_guc_ct_enable(struct intel_guc_ct *ct);
>-void intel_guc_ct_disable(struct intel_guc_ct *ct);
>-
>-static inline void intel_guc_ct_stop(struct intel_guc_ct *ct)
>-{
>-	ct->host_channel.enabled = false;
>-}
>-
>-#endif /* _INTEL_GUC_CT_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_fw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_fw.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_fw.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_fw.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,308 +0,0 @@
>-/*
>- * Copyright Â© 2014 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- * Authors:
>- *    Vinit Azad <vinit.azad@intel.com>
>- *    Ben Widawsky <ben@bwidawsk.net>
>- *    Dave Gordon <david.s.gordon@intel.com>
>- *    Alex Dai <yu.dai@intel.com>
>- */
>-
>-#include "intel_guc_fw.h"
>-#include "i915_drv.h"
>-
>-#define __MAKE_GUC_FW_PATH(KEY) \
>-	"i915/" \
>-	__stringify(KEY##_GUC_FW_PREFIX) "_guc_" \
>-	__stringify(KEY##_GUC_FW_MAJOR) "." \
>-	__stringify(KEY##_GUC_FW_MINOR) "." \
>-	__stringify(KEY##_GUC_FW_PATCH) ".bin"
>-
>-#define SKL_GUC_FW_PREFIX skl
>-#define SKL_GUC_FW_MAJOR 32
>-#define SKL_GUC_FW_MINOR 0
>-#define SKL_GUC_FW_PATCH 3
>-#define SKL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(SKL)
>-MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH);
>-
>-#define BXT_GUC_FW_PREFIX bxt
>-#define BXT_GUC_FW_MAJOR 32
>-#define BXT_GUC_FW_MINOR 0
>-#define BXT_GUC_FW_PATCH 3
>-#define BXT_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(BXT)
>-MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH);
>-
>-#define KBL_GUC_FW_PREFIX kbl
>-#define KBL_GUC_FW_MAJOR 32
>-#define KBL_GUC_FW_MINOR 0
>-#define KBL_GUC_FW_PATCH 3
>-#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL)
>-MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH);
>-
>-#define GLK_GUC_FW_PREFIX glk
>-#define GLK_GUC_FW_MAJOR 32
>-#define GLK_GUC_FW_MINOR 0
>-#define GLK_GUC_FW_PATCH 3
>-#define GLK_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(GLK)
>-MODULE_FIRMWARE(GLK_GUC_FIRMWARE_PATH);
>-
>-#define ICL_GUC_FW_PREFIX icl
>-#define ICL_GUC_FW_MAJOR 32
>-#define ICL_GUC_FW_MINOR 0
>-#define ICL_GUC_FW_PATCH 3
>-#define ICL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(ICL)
>-MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
>-
>-static void guc_fw_select(struct intel_uc_fw *guc_fw)
>-{
>-	struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
>-	struct drm_i915_private *i915 = guc_to_i915(guc);
>-
>-	GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
>-
>-	if (!HAS_GUC(i915))
>-		return;
>-
>-	if (i915_modparams.guc_firmware_path) {
>-		guc_fw->path = i915_modparams.guc_firmware_path;
>-		guc_fw->major_ver_wanted = 0;
>-		guc_fw->minor_ver_wanted = 0;
>-	} else if (IS_ICELAKE(i915)) {
>-		guc_fw->path = ICL_GUC_FIRMWARE_PATH;
>-		guc_fw->major_ver_wanted = ICL_GUC_FW_MAJOR;
>-		guc_fw->minor_ver_wanted = ICL_GUC_FW_MINOR;
>-	} else if (IS_GEMINILAKE(i915)) {
>-		guc_fw->path = GLK_GUC_FIRMWARE_PATH;
>-		guc_fw->major_ver_wanted = GLK_GUC_FW_MAJOR;
>-		guc_fw->minor_ver_wanted = GLK_GUC_FW_MINOR;
>-	} else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) {
>-		guc_fw->path = KBL_GUC_FIRMWARE_PATH;
>-		guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR;
>-		guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR;
>-	} else if (IS_BROXTON(i915)) {
>-		guc_fw->path = BXT_GUC_FIRMWARE_PATH;
>-		guc_fw->major_ver_wanted = BXT_GUC_FW_MAJOR;
>-		guc_fw->minor_ver_wanted = BXT_GUC_FW_MINOR;
>-	} else if (IS_SKYLAKE(i915)) {
>-		guc_fw->path = SKL_GUC_FIRMWARE_PATH;
>-		guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR;
>-		guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR;
>-	}
>-}
>-
>-/**
>- * intel_guc_fw_init_early() - initializes GuC firmware struct
>- * @guc: intel_guc struct
>- *
>- * On platforms with GuC selects firmware for uploading
>- */
>-void intel_guc_fw_init_early(struct intel_guc *guc)
>-{
>-	struct intel_uc_fw *guc_fw = &guc->fw;
>-
>-	intel_uc_fw_init_early(guc_fw, INTEL_UC_FW_TYPE_GUC);
>-	guc_fw_select(guc_fw);
>-}
>-
>-static void guc_prepare_xfer(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-
>-	/* Must program this register before loading the ucode with DMA */
>-	I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES |
>-				     GUC_ENABLE_READ_CACHE_LOGIC |
>-				     GUC_ENABLE_MIA_CACHING |
>-				     GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
>-				     GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
>-				     GUC_ENABLE_MIA_CLOCK_GATING);
>-
>-	if (IS_GEN9_LP(dev_priv))
>-		I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>-	else
>-		I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>-
>-	if (IS_GEN(dev_priv, 9)) {
>-		/* DOP Clock Gating Enable for GuC clocks */
>-		I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
>-					    I915_READ(GEN7_MISCCPCTL)));
>-
>-		/* allows for 5us (in 10ns units) before GT can go to RC6 */
>-		I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
>-	}
>-}
>-
>-/* Copy RSA signature from the fw image to HW for verification */
>-static void guc_xfer_rsa(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	struct intel_uc_fw *fw = &guc->fw;
>-	struct sg_table *pages = fw->obj->mm.pages;
>-	u32 rsa[UOS_RSA_SCRATCH_COUNT];
>-	int i;
>-
>-	sg_pcopy_to_buffer(pages->sgl, pages->nents,
>-			   rsa, sizeof(rsa), fw->rsa_offset);
>-
>-	for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
>-		I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
>-}
>-
>-static bool guc_xfer_completed(struct intel_guc *guc, u32 *status)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-
>-	/* Did we complete the xfer? */
>-	*status = I915_READ(DMA_CTRL);
>-	return !(*status & START_DMA);
>-}
>-
>-/*
>- * Read the GuC status register (GUC_STATUS) and store it in the
>- * specified location; then return a boolean indicating whether
>- * the value matches either of two values representing completion
>- * of the GuC boot process.
>- *
>- * This is used for polling the GuC status in a wait_for()
>- * loop below.
>- */
>-static inline bool guc_ready(struct intel_guc *guc, u32 *status)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	u32 val = I915_READ(GUC_STATUS);
>-	u32 uk_val = val & GS_UKERNEL_MASK;
>-
>-	*status = val;
>-	return (uk_val == GS_UKERNEL_READY) ||
>-		((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
>-}
>-
>-static int guc_wait_ucode(struct intel_guc *guc)
>-{
>-	u32 status;
>-	int ret;
>-
>-	/*
>-	 * Wait for the GuC to start up.
>-	 * NB: Docs recommend not using the interrupt for completion.
>-	 * Measurements indicate this should take no more than 20ms, so a
>-	 * timeout here indicates that the GuC has failed and is unusable.
>-	 * (Higher levels of the driver may decide to reset the GuC and
>-	 * attempt the ucode load again if this happens.)
>-	 */
>-	ret = wait_for(guc_ready(guc, &status), 100);
>-	DRM_DEBUG_DRIVER("GuC status %#x\n", status);
>-
>-	if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
>-		DRM_ERROR("GuC firmware signature verification failed\n");
>-		ret = -ENOEXEC;
>-	}
>-
>-	if (ret == 0 && !guc_xfer_completed(guc, &status)) {
>-		DRM_ERROR("GuC is ready, but the xfer %08x is incomplete\n",
>-			  status);
>-		ret = -ENXIO;
>-	}
>-
>-	return ret;
>-}
>-
>-/*
>- * Transfer the firmware image to RAM for execution by the microcontroller.
>- *
>- * Architecturally, the DMA engine is bidirectional, and can potentially even
>- * transfer between GTT locations. This functionality is left out of the API
>- * for now as there is no need for it.
>- */
>-static int guc_xfer_ucode(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	struct intel_uc_fw *guc_fw = &guc->fw;
>-	unsigned long offset;
>-
>-	/*
>-	 * The header plus uCode will be copied to WOPCM via DMA, excluding any
>-	 * other components
>-	 */
>-	I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
>-
>-	/* Set the source address for the new blob */
>-	offset = intel_uc_fw_ggtt_offset(guc_fw) + guc_fw->header_offset;
>-	I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
>-	I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
>-
>-	/*
>-	 * Set the DMA destination. Current uCode expects the code to be
>-	 * loaded at 8k; locations below this are used for the stack.
>-	 */
>-	I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
>-	I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>-
>-	/* Finally start the DMA */
>-	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
>-
>-	return guc_wait_ucode(guc);
>-}
>-/*
>- * Load the GuC firmware blob into the MinuteIA.
>- */
>-static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
>-{
>-	struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	int ret;
>-
>-	GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
>-
>-	intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
>-
>-	guc_prepare_xfer(guc);
>-
>-	/*
>-	 * Note that GuC needs the CSS header plus uKernel code to be copied
>-	 * by the DMA engine in one operation, whereas the RSA signature is
>-	 * loaded via MMIO.
>-	 */
>-	guc_xfer_rsa(guc);
>-
>-	ret = guc_xfer_ucode(guc);
>-
>-	intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
>-
>-	return ret;
>-}
>-
>-/**
>- * intel_guc_fw_upload() - load GuC uCode to device
>- * @guc: intel_guc structure
>- *
>- * Called from intel_uc_init_hw() during driver load, resume from sleep and
>- * after a GPU reset.
>- *
>- * The firmware image should have already been fetched into memory, so only
>- * check that fetch succeeded, and then transfer the image to the h/w.
>- *
>- * Return:	non-zero code on error
>- */
>-int intel_guc_fw_upload(struct intel_guc *guc)
>-{
>-	return intel_uc_fw_upload(&guc->fw, guc_fw_xfer);
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_fw.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_fw.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_fw.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_fw.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,33 +0,0 @@
>-/*
>- * Copyright Â© 2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#ifndef _INTEL_GUC_FW_H_
>-#define _INTEL_GUC_FW_H_
>-
>-struct intel_guc;
>-
>-void intel_guc_fw_init_early(struct intel_guc *guc);
>-int intel_guc_fw_upload(struct intel_guc *guc);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_fwif.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_fwif.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_fwif.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_fwif.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,692 +0,0 @@
>-/*
>- * Copyright Â© 2014 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- */
>-#ifndef _INTEL_GUC_FWIF_H
>-#define _INTEL_GUC_FWIF_H
>-
>-#define GUC_CLIENT_PRIORITY_KMD_HIGH	0
>-#define GUC_CLIENT_PRIORITY_HIGH	1
>-#define GUC_CLIENT_PRIORITY_KMD_NORMAL	2
>-#define GUC_CLIENT_PRIORITY_NORMAL	3
>-#define GUC_CLIENT_PRIORITY_NUM		4
>-
>-#define GUC_MAX_STAGE_DESCRIPTORS	1024
>-#define	GUC_INVALID_STAGE_ID		GUC_MAX_STAGE_DESCRIPTORS
>-
>-#define GUC_RENDER_ENGINE		0
>-#define GUC_VIDEO_ENGINE		1
>-#define GUC_BLITTER_ENGINE		2
>-#define GUC_VIDEOENHANCE_ENGINE		3
>-#define GUC_VIDEO_ENGINE2		4
>-#define GUC_MAX_ENGINES_NUM		(GUC_VIDEO_ENGINE2 + 1)
>-
>-/*
>- * XXX: Beware that Gen9 firmware 32.x uses wrong definition for
>- * GUC_MAX_INSTANCES_PER_CLASS (1) but this is harmless for us now
>- * as we are not enabling GuC submission mode where this will be used
>- */
>-#define GUC_MAX_ENGINE_CLASSES		5
>-#define GUC_MAX_INSTANCES_PER_CLASS	4
>-
>-#define GUC_DOORBELL_INVALID		256
>-
>-#define GUC_DB_SIZE			(PAGE_SIZE)
>-#define GUC_WQ_SIZE			(PAGE_SIZE * 2)
>-
>-/* Work queue item header definitions */
>-#define WQ_STATUS_ACTIVE		1
>-#define WQ_STATUS_SUSPENDED		2
>-#define WQ_STATUS_CMD_ERROR		3
>-#define WQ_STATUS_ENGINE_ID_NOT_USED	4
>-#define WQ_STATUS_SUSPENDED_FROM_RESET	5
>-#define WQ_TYPE_SHIFT			0
>-#define   WQ_TYPE_BATCH_BUF		(0x1 << WQ_TYPE_SHIFT)
>-#define   WQ_TYPE_PSEUDO		(0x2 << WQ_TYPE_SHIFT)
>-#define   WQ_TYPE_INORDER		(0x3 << WQ_TYPE_SHIFT)
>-#define   WQ_TYPE_NOOP			(0x4 << WQ_TYPE_SHIFT)
>-#define WQ_TARGET_SHIFT			10
>-#define WQ_LEN_SHIFT			16
>-#define WQ_NO_WCFLUSH_WAIT		(1 << 27)
>-#define WQ_PRESENT_WORKLOAD		(1 << 28)
>-
>-#define WQ_RING_TAIL_SHIFT		20
>-#define WQ_RING_TAIL_MAX		0x7FF	/* 2^11 QWords */
>-#define WQ_RING_TAIL_MASK		(WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT)
>-
>-#define GUC_STAGE_DESC_ATTR_ACTIVE	BIT(0)
>-#define GUC_STAGE_DESC_ATTR_PENDING_DB	BIT(1)
>-#define GUC_STAGE_DESC_ATTR_KERNEL	BIT(2)
>-#define GUC_STAGE_DESC_ATTR_PREEMPT	BIT(3)
>-#define GUC_STAGE_DESC_ATTR_RESET	BIT(4)
>-#define GUC_STAGE_DESC_ATTR_WQLOCKED	BIT(5)
>-#define GUC_STAGE_DESC_ATTR_PCH		BIT(6)
>-#define GUC_STAGE_DESC_ATTR_TERMINATED	BIT(7)
>-
>-/* New GuC control data */
>-#define GUC_CTL_CTXINFO			0
>-#define   GUC_CTL_CTXNUM_IN16_SHIFT	0
>-#define   GUC_CTL_BASE_ADDR_SHIFT	12
>-
>-#define GUC_CTL_LOG_PARAMS		1
>-#define   GUC_LOG_VALID			(1 << 0)
>-#define   GUC_LOG_NOTIFY_ON_HALF_FULL	(1 << 1)
>-#define   GUC_LOG_ALLOC_IN_MEGABYTE	(1 << 3)
>-#define   GUC_LOG_CRASH_SHIFT		4
>-#define   GUC_LOG_CRASH_MASK		(0x3 << GUC_LOG_CRASH_SHIFT)
>-#define   GUC_LOG_DPC_SHIFT		6
>-#define   GUC_LOG_DPC_MASK	        (0x7 << GUC_LOG_DPC_SHIFT)
>-#define   GUC_LOG_ISR_SHIFT		9
>-#define   GUC_LOG_ISR_MASK	        (0x7 << GUC_LOG_ISR_SHIFT)
>-#define   GUC_LOG_BUF_ADDR_SHIFT	12
>-
>-#define GUC_CTL_WA			2
>-#define GUC_CTL_FEATURE			3
>-#define   GUC_CTL_DISABLE_SCHEDULER	(1 << 14)
>-
>-#define GUC_CTL_DEBUG			4
>-#define   GUC_LOG_VERBOSITY_SHIFT	0
>-#define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
>-#define   GUC_LOG_VERBOSITY_MED		(1 << GUC_LOG_VERBOSITY_SHIFT)
>-#define   GUC_LOG_VERBOSITY_HIGH	(2 << GUC_LOG_VERBOSITY_SHIFT)
>-#define   GUC_LOG_VERBOSITY_ULTRA	(3 << GUC_LOG_VERBOSITY_SHIFT)
>-/* Verbosity range-check limits, without the shift */
>-#define	  GUC_LOG_VERBOSITY_MIN		0
>-#define	  GUC_LOG_VERBOSITY_MAX		3
>-#define	  GUC_LOG_VERBOSITY_MASK	0x0000000f
>-#define	  GUC_LOG_DESTINATION_MASK	(3 << 4)
>-#define   GUC_LOG_DISABLED		(1 << 6)
>-#define   GUC_PROFILE_ENABLED		(1 << 7)
>-
>-#define GUC_CTL_ADS			5
>-#define   GUC_ADS_ADDR_SHIFT		1
>-#define   GUC_ADS_ADDR_MASK		(0xFFFFF << GUC_ADS_ADDR_SHIFT)
>-
>-#define GUC_CTL_MAX_DWORDS		(SOFT_SCRATCH_COUNT - 2) /* [1..14] */
>-
>-/**
>- * DOC: GuC Firmware Layout
>- *
>- * The GuC firmware layout looks like this:
>- *
>- *     +-------------------------------+
>- *     |         uc_css_header         |
>- *     |                               |
>- *     | contains major/minor version  |
>- *     +-------------------------------+
>- *     |             uCode             |
>- *     +-------------------------------+
>- *     |         RSA signature         |
>- *     +-------------------------------+
>- *     |          modulus key          |
>- *     +-------------------------------+
>- *     |          exponent val         |
>- *     +-------------------------------+
>- *
>- * The firmware may or may not have modulus key and exponent data. The header,
>- * uCode and RSA signature are must-have components that will be used by driver.
>- * Length of each components, which is all in dwords, can be found in header.
>- * In the case that modulus and exponent are not present in fw, a.k.a truncated
>- * image, the length value still appears in header.
>- *
>- * Driver will do some basic fw size validation based on the following rules:
>- *
>- * 1. Header, uCode and RSA are must-have components.
>- * 2. All firmware components, if they present, are in the sequence illustrated
>- *    in the layout table above.
>- * 3. Length info of each component can be found in header, in dwords.
>- * 4. Modulus and exponent key are not required by driver. They may not appear
>- *    in fw. So driver will load a truncated firmware in this case.
>- *
>- * HuC firmware layout is same as GuC firmware.
>- * Only HuC version information is saved in a different way.
>- */
>-
>-struct uc_css_header {
>-	u32 module_type;
>-	/* header_size includes all non-uCode bits, including css_header, rsa
>-	 * key, modulus key and exponent data. */
>-	u32 header_size_dw;
>-	u32 header_version;
>-	u32 module_id;
>-	u32 module_vendor;
>-	u32 date;
>-#define CSS_DATE_DAY			(0xFF << 0)
>-#define CSS_DATE_MONTH			(0xFF << 8)
>-#define CSS_DATE_YEAR			(0xFFFF << 16)
>-	u32 size_dw; /* uCode plus header_size_dw */
>-	u32 key_size_dw;
>-	u32 modulus_size_dw;
>-	u32 exponent_size_dw;
>-	u32 time;
>-#define CSS_TIME_HOUR			(0xFF << 0)
>-#define CSS_DATE_MIN			(0xFF << 8)
>-#define CSS_DATE_SEC			(0xFFFF << 16)
>-	char username[8];
>-	char buildnumber[12];
>-	u32 sw_version;
>-#define CSS_SW_VERSION_GUC_MAJOR	(0xFF << 16)
>-#define CSS_SW_VERSION_GUC_MINOR	(0xFF << 8)
>-#define CSS_SW_VERSION_GUC_PATCH	(0xFF << 0)
>-#define CSS_SW_VERSION_HUC_MAJOR	(0xFFFF << 16)
>-#define CSS_SW_VERSION_HUC_MINOR	(0xFFFF << 0)
>-	u32 reserved[14];
>-	u32 header_info;
>-} __packed;
>-
>-/* Work item for submitting workloads into work queue of GuC. */
>-struct guc_wq_item {
>-	u32 header;
>-	u32 context_desc;
>-	u32 submit_element_info;
>-	u32 fence_id;
>-} __packed;
>-
>-struct guc_process_desc {
>-	u32 stage_id;
>-	u64 db_base_addr;
>-	u32 head;
>-	u32 tail;
>-	u32 error_offset;
>-	u64 wq_base_addr;
>-	u32 wq_size_bytes;
>-	u32 wq_status;
>-	u32 engine_presence;
>-	u32 priority;
>-	u32 reserved[30];
>-} __packed;
>-
>-/* engine id and context id is packed into guc_execlist_context.context_id*/
>-#define GUC_ELC_CTXID_OFFSET		0
>-#define GUC_ELC_ENGINE_OFFSET		29
>-
>-/* The execlist context including software and HW information */
>-struct guc_execlist_context {
>-	u32 context_desc;
>-	u32 context_id;
>-	u32 ring_status;
>-	u32 ring_lrca;
>-	u32 ring_begin;
>-	u32 ring_end;
>-	u32 ring_next_free_location;
>-	u32 ring_current_tail_pointer_value;
>-	u8 engine_state_submit_value;
>-	u8 engine_state_wait_value;
>-	u16 pagefault_count;
>-	u16 engine_submit_queue_count;
>-} __packed;
>-
>-/*
>- * This structure describes a stage set arranged for a particular communication
>- * between uKernel (GuC) and Driver (KMD). Technically, this is known as a
>- * "GuC Context descriptor" in the specs, but we use the term "stage descriptor"
>- * to avoid confusion with all the other things already named "context" in the
>- * driver. A static pool of these descriptors are stored inside a GEM object
>- * (stage_desc_pool) which is held for the entire lifetime of our interaction
>- * with the GuC, being allocated before the GuC is loaded with its firmware.
>- */
>-struct guc_stage_desc {
>-	u32 sched_common_area;
>-	u32 stage_id;
>-	u32 pas_id;
>-	u8 engines_used;
>-	u64 db_trigger_cpu;
>-	u32 db_trigger_uk;
>-	u64 db_trigger_phy;
>-	u16 db_id;
>-
>-	struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];
>-
>-	u8 attribute;
>-
>-	u32 priority;
>-
>-	u32 wq_sampled_tail_offset;
>-	u32 wq_total_submit_enqueues;
>-
>-	u32 process_desc;
>-	u32 wq_addr;
>-	u32 wq_size;
>-
>-	u32 engine_presence;
>-
>-	u8 engine_suspended;
>-
>-	u8 reserved0[3];
>-	u64 reserved1[1];
>-
>-	u64 desc_private;
>-} __packed;
>-
>-/**
>- * DOC: CTB based communication
>- *
>- * The CTB (command transport buffer) communication between Host and GuC
>- * is based on u32 data stream written to the shared buffer. One buffer can
>- * be used to transmit data only in one direction (one-directional channel).
>- *
>- * Current status of the each buffer is stored in the buffer descriptor.
>- * Buffer descriptor holds tail and head fields that represents active data
>- * stream. The tail field is updated by the data producer (sender), and head
>- * field is updated by the data consumer (receiver)::
>- *
>- *      +------------+
>- *      | DESCRIPTOR |          +=================+============+========+
>- *      +============+          |                 | MESSAGE(s) |        |
>- *      | address    |--------->+=================+============+========+
>- *      +------------+
>- *      | head       |          ^-----head--------^
>- *      +------------+
>- *      | tail       |          ^---------tail-----------------^
>- *      +------------+
>- *      | size       |          ^---------------size--------------------^
>- *      +------------+
>- *
>- * Each message in data stream starts with the single u32 treated as a header,
>- * followed by optional set of u32 data that makes message specific payload::
>- *
>- *      +------------+---------+---------+---------+
>- *      |         MESSAGE                          |
>- *      +------------+---------+---------+---------+
>- *      |   msg[0]   |   [1]   |   ...   |  [n-1]  |
>- *      +------------+---------+---------+---------+
>- *      |   MESSAGE  |       MESSAGE PAYLOAD       |
>- *      +   HEADER   +---------+---------+---------+
>- *      |            |    0    |   ...   |    n    |
>- *      +======+=====+=========+=========+=========+
>- *      | 31:16| code|         |         |         |
>- *      +------+-----+         |         |         |
>- *      |  15:5|flags|         |         |         |
>- *      +------+-----+         |         |         |
>- *      |   4:0|  len|         |         |         |
>- *      +------+-----+---------+---------+---------+
>- *
>- *                   ^-------------len-------------^
>- *
>- * The message header consists of:
>- *
>- * - **len**, indicates length of the message payload (in u32)
>- * - **code**, indicates message code
>- * - **flags**, holds various bits to control message handling
>- */
>-
>-/*
>- * Describes single command transport buffer.
>- * Used by both guc-master and clients.
>- */
>-struct guc_ct_buffer_desc {
>-	u32 addr;		/* gfx address */
>-	u64 host_private;	/* host private data */
>-	u32 size;		/* size in bytes */
>-	u32 head;		/* offset updated by GuC*/
>-	u32 tail;		/* offset updated by owner */
>-	u32 is_in_error;	/* error indicator */
>-	u32 fence;		/* fence updated by GuC */
>-	u32 status;		/* status updated by GuC */
>-	u32 owner;		/* id of the channel owner */
>-	u32 owner_sub_id;	/* owner-defined field for extra tracking */
>-	u32 reserved[5];
>-} __packed;
>-
>-/* Type of command transport buffer */
>-#define INTEL_GUC_CT_BUFFER_TYPE_SEND	0x0u
>-#define INTEL_GUC_CT_BUFFER_TYPE_RECV	0x1u
>-
>-/*
>- * Definition of the command transport message header (DW0)
>- *
>- * bit[4..0]	message len (in dwords)
>- * bit[7..5]	reserved
>- * bit[8]	response (G2H only)
>- * bit[8]	write fence to desc (H2G only)
>- * bit[9]	write status to H2G buff (H2G only)
>- * bit[10]	send status back via G2H (H2G only)
>- * bit[15..11]	reserved
>- * bit[31..16]	action code
>- */
>-#define GUC_CT_MSG_LEN_SHIFT			0
>-#define GUC_CT_MSG_LEN_MASK			0x1F
>-#define GUC_CT_MSG_IS_RESPONSE			(1 << 8)
>-#define GUC_CT_MSG_WRITE_FENCE_TO_DESC		(1 << 8)
>-#define GUC_CT_MSG_WRITE_STATUS_TO_BUFF		(1 << 9)
>-#define GUC_CT_MSG_SEND_STATUS			(1 << 10)
>-#define GUC_CT_MSG_ACTION_SHIFT			16
>-#define GUC_CT_MSG_ACTION_MASK			0xFFFF
>-
>-#define GUC_FORCEWAKE_RENDER	(1 << 0)
>-#define GUC_FORCEWAKE_MEDIA	(1 << 1)
>-
>-#define GUC_POWER_UNSPECIFIED	0
>-#define GUC_POWER_D0		1
>-#define GUC_POWER_D1		2
>-#define GUC_POWER_D2		3
>-#define GUC_POWER_D3		4
>-
>-/* Scheduling policy settings */
>-
>-/* Reset engine upon preempt failure */
>-#define POLICY_RESET_ENGINE		(1<<0)
>-/* Preempt to idle on quantum expiry */
>-#define POLICY_PREEMPT_TO_IDLE		(1<<1)
>-
>-#define POLICY_MAX_NUM_WI 15
>-#define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
>-#define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
>-#define POLICY_DEFAULT_PREEMPTION_TIME_US 500000
>-#define POLICY_DEFAULT_FAULT_TIME_US 250000
>-
>-struct guc_policy {
>-	/* Time for one workload to execute. (in micro seconds) */
>-	u32 execution_quantum;
>-	/* Time to wait for a preemption request to completed before issuing a
>-	 * reset. (in micro seconds). */
>-	u32 preemption_time;
>-	/* How much time to allow to run after the first fault is observed.
>-	 * Then preempt afterwards. (in micro seconds) */
>-	u32 fault_time;
>-	u32 policy_flags;
>-	u32 reserved[8];
>-} __packed;
>-
>-struct guc_policies {
>-	struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES];
>-	u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
>-	/* In micro seconds. How much time to allow before DPC processing is
>-	 * called back via interrupt (to prevent DPC queue drain starving).
>-	 * Typically 1000s of micro seconds (example only, not granularity). */
>-	u32 dpc_promote_time;
>-
>-	/* Must be set to take these new values. */
>-	u32 is_valid;
>-
>-	/* Max number of WIs to process per call. A large value may keep CS
>-	 * idle. */
>-	u32 max_num_work_items;
>-
>-	u32 reserved[4];
>-} __packed;
>-
>-/* GuC MMIO reg state struct */
>-
>-
>-#define GUC_REGSET_MAX_REGISTERS	64
>-#define GUC_S3_SAVE_SPACE_PAGES		10
>-
>-struct guc_mmio_reg {
>-	u32 offset;
>-	u32 value;
>-	u32 flags;
>-#define GUC_REGSET_MASKED		(1 << 0)
>-} __packed;
>-
>-struct guc_mmio_regset {
>-	struct guc_mmio_reg registers[GUC_REGSET_MAX_REGISTERS];
>-	u32 values_valid;
>-	u32 number_of_registers;
>-} __packed;
>-
>-/* GuC register sets */
>-struct guc_mmio_reg_state {
>-	struct guc_mmio_regset engine_reg[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>-	u32 reserved[98];
>-} __packed;
>-
>-/* HW info */
>-struct guc_gt_system_info {
>-	u32 slice_enabled;
>-	u32 rcs_enabled;
>-	u32 reserved0;
>-	u32 bcs_enabled;
>-	u32 vdbox_enable_mask;
>-	u32 vdbox_sfc_support_mask;
>-	u32 vebox_enable_mask;
>-	u32 reserved[9];
>-} __packed;
>-
>-/* Clients info */
>-struct guc_ct_pool_entry {
>-	struct guc_ct_buffer_desc desc;
>-	u32 reserved[7];
>-} __packed;
>-
>-#define GUC_CT_POOL_SIZE	2
>-
>-struct guc_clients_info {
>-	u32 clients_num;
>-	u32 reserved0[13];
>-	u32 ct_pool_addr;
>-	u32 ct_pool_count;
>-	u32 reserved[4];
>-} __packed;
>-
>-/* GuC Additional Data Struct */
>-struct guc_ads {
>-	u32 reg_state_addr;
>-	u32 reg_state_buffer;
>-	u32 scheduler_policies;
>-	u32 gt_system_info;
>-	u32 clients_info;
>-	u32 control_data;
>-	u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
>-	u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
>-	u32 reserved[16];
>-} __packed;
>-
>-/* GuC logging structures */
>-
>-enum guc_log_buffer_type {
>-	GUC_ISR_LOG_BUFFER,
>-	GUC_DPC_LOG_BUFFER,
>-	GUC_CRASH_DUMP_LOG_BUFFER,
>-	GUC_MAX_LOG_BUFFER
>-};
>-
>-/**
>- * struct guc_log_buffer_state - GuC log buffer state
>- *
>- * Below state structure is used for coordination of retrieval of GuC firmware
>- * logs. Separate state is maintained for each log buffer type.
>- * read_ptr points to the location where i915 read last in log buffer and
>- * is read only for GuC firmware. write_ptr is incremented by GuC with number
>- * of bytes written for each log entry and is read only for i915.
>- * When any type of log buffer becomes half full, GuC sends a flush interrupt.
>- * GuC firmware expects that while it is writing to 2nd half of the buffer,
>- * first half would get consumed by Host and then get a flush completed
>- * acknowledgment from Host, so that it does not end up doing any overwrite
>- * causing loss of logs. So when buffer gets half filled & i915 has requested
>- * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr
>- * to the value of write_ptr and raise the interrupt.
>- * On receiving the interrupt i915 should read the buffer, clear flush_to_file
>- * field and also update read_ptr with the value of sample_write_ptr, before
>- * sending an acknowledgment to GuC. marker & version fields are for internal
>- * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every
>- * time GuC detects the log buffer overflow.
>- */
>-struct guc_log_buffer_state {
>-	u32 marker[2];
>-	u32 read_ptr;
>-	u32 write_ptr;
>-	u32 size;
>-	u32 sampled_write_ptr;
>-	union {
>-		struct {
>-			u32 flush_to_file:1;
>-			u32 buffer_full_cnt:4;
>-			u32 reserved:27;
>-		};
>-		u32 flags;
>-	};
>-	u32 version;
>-} __packed;
>-
>-struct guc_ctx_report {
>-	u32 report_return_status;
>-	u32 reserved1[64];
>-	u32 affected_count;
>-	u32 reserved2[2];
>-} __packed;
>-
>-/* GuC Shared Context Data Struct */
>-struct guc_shared_ctx_data {
>-	u32 addr_of_last_preempted_data_low;
>-	u32 addr_of_last_preempted_data_high;
>-	u32 addr_of_last_preempted_data_high_tmp;
>-	u32 padding;
>-	u32 is_mapped_to_proxy;
>-	u32 proxy_ctx_id;
>-	u32 engine_reset_ctx_id;
>-	u32 media_reset_count;
>-	u32 reserved1[8];
>-	u32 uk_last_ctx_switch_reason;
>-	u32 was_reset;
>-	u32 lrca_gpu_addr;
>-	u64 execlist_ctx;
>-	u32 reserved2[66];
>-	struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
>-} __packed;
>-
>-/**
>- * DOC: MMIO based communication
>- *
>- * The MMIO based communication between Host and GuC uses software scratch
>- * registers, where first register holds data treated as message header,
>- * and other registers are used to hold message payload.
>- *
>- * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8,
>- * but no H2G command takes more than 8 parameters and the GuC FW
>- * itself uses an 8-element array to store the H2G message.
>- *
>- *      +-----------+---------+---------+---------+
>- *      |  MMIO[0]  | MMIO[1] |   ...   | MMIO[n] |
>- *      +-----------+---------+---------+---------+
>- *      | header    |      optional payload       |
>- *      +======+====+=========+=========+=========+
>- *      | 31:28|type|         |         |         |
>- *      +------+----+         |         |         |
>- *      | 27:16|data|         |         |         |
>- *      +------+----+         |         |         |
>- *      |  15:0|code|         |         |         |
>- *      +------+----+---------+---------+---------+
>- *
>- * The message header consists of:
>- *
>- * - **type**, indicates message type
>- * - **code**, indicates message code, is specific for **type**
>- * - **data**, indicates message data, optional, depends on **code**
>- *
>- * The following message **types** are supported:
>- *
>- * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code
>- *   must be priovided in **code** field. Optional action specific parameters
>- *   can be provided in remaining payload registers or **data** field.
>- *
>- * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request,
>- *   action response status will be provided in **code** field. Optional
>- *   response data can be returned in remaining payload registers or **data**
>- *   field.
>- */
>-
>-#define GUC_MAX_MMIO_MSG_LEN		8
>-
>-#define INTEL_GUC_MSG_TYPE_SHIFT	28
>-#define INTEL_GUC_MSG_TYPE_MASK		(0xF << INTEL_GUC_MSG_TYPE_SHIFT)
>-#define INTEL_GUC_MSG_DATA_SHIFT	16
>-#define INTEL_GUC_MSG_DATA_MASK		(0xFFF << INTEL_GUC_MSG_DATA_SHIFT)
>-#define INTEL_GUC_MSG_CODE_SHIFT	0
>-#define INTEL_GUC_MSG_CODE_MASK		(0xFFFF << INTEL_GUC_MSG_CODE_SHIFT)
>-
>-#define __INTEL_GUC_MSG_GET(T, m) \
>-	(((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT)
>-#define INTEL_GUC_MSG_TO_TYPE(m)	__INTEL_GUC_MSG_GET(TYPE, m)
>-#define INTEL_GUC_MSG_TO_DATA(m)	__INTEL_GUC_MSG_GET(DATA, m)
>-#define INTEL_GUC_MSG_TO_CODE(m)	__INTEL_GUC_MSG_GET(CODE, m)
>-
>-enum intel_guc_msg_type {
>-	INTEL_GUC_MSG_TYPE_REQUEST = 0x0,
>-	INTEL_GUC_MSG_TYPE_RESPONSE = 0xF,
>-};
>-
>-#define __INTEL_GUC_MSG_TYPE_IS(T, m) \
>-	(INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T)
>-#define INTEL_GUC_MSG_IS_REQUEST(m)	__INTEL_GUC_MSG_TYPE_IS(REQUEST, m)
>-#define INTEL_GUC_MSG_IS_RESPONSE(m)	__INTEL_GUC_MSG_TYPE_IS(RESPONSE, m)
>-
>-enum intel_guc_action {
>-	INTEL_GUC_ACTION_DEFAULT = 0x0,
>-	INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
>-	INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
>-	INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
>-	INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
>-	INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
>-	INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
>-	INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
>-	INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
>-	INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
>-	INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005,
>-	INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
>-	INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
>-	INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
>-	INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
>-	INTEL_GUC_ACTION_LIMIT
>-};
>-
>-enum intel_guc_preempt_options {
>-	INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
>-	INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
>-};
>-
>-enum intel_guc_report_status {
>-	INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0,
>-	INTEL_GUC_REPORT_STATUS_ACKED = 0x1,
>-	INTEL_GUC_REPORT_STATUS_ERROR = 0x2,
>-	INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
>-};
>-
>-enum intel_guc_sleep_state_status {
>-	INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1,
>-	INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2,
>-	INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3
>-#define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
>-};
>-
>-#define GUC_LOG_CONTROL_LOGGING_ENABLED	(1 << 0)
>-#define GUC_LOG_CONTROL_VERBOSITY_SHIFT	4
>-#define GUC_LOG_CONTROL_VERBOSITY_MASK	(0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
>-#define GUC_LOG_CONTROL_DEFAULT_LOGGING	(1 << 8)
>-
>-enum intel_guc_response_status {
>-	INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
>-	INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
>-};
>-
>-#define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \
>-	 (typecheck(u32, (m)) && \
>-	  ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \
>-	  ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \
>-	   (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT)))
>-
>-/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
>-enum intel_guc_recv_message {
>-	INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
>-	INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)
>-};
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,204 +0,0 @@
>-/*
>- * Copyright Â© 2014-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#ifndef _INTEL_GUC_H_
>-#define _INTEL_GUC_H_
>-
>-#include "intel_uncore.h"
>-#include "intel_guc_fw.h"
>-#include "intel_guc_fwif.h"
>-#include "intel_guc_ct.h"
>-#include "intel_guc_log.h"
>-#include "intel_guc_reg.h"
>-#include "intel_uc_fw.h"
>-#include "i915_utils.h"
>-#include "i915_vma.h"
>-
>-struct guc_preempt_work {
>-	struct work_struct work;
>-	struct intel_engine_cs *engine;
>-};
>-
>-/*
>- * Top level structure of GuC. It handles firmware loading and manages client
>- * pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy
>- * ExecList submission.
>- */
>-struct intel_guc {
>-	struct intel_uc_fw fw;
>-	struct intel_guc_log log;
>-	struct intel_guc_ct ct;
>-
>-	/* Log snapshot if GuC errors during load */
>-	struct drm_i915_gem_object *load_err_log;
>-
>-	/* intel_guc_recv interrupt related state */
>-	spinlock_t irq_lock;
>-	unsigned int msg_enabled_mask;
>-
>-	struct {
>-		bool enabled;
>-		void (*reset)(struct drm_i915_private *i915);
>-		void (*enable)(struct drm_i915_private *i915);
>-		void (*disable)(struct drm_i915_private *i915);
>-	} interrupts;
>-
>-	struct i915_vma *ads_vma;
>-	struct i915_vma *stage_desc_pool;
>-	void *stage_desc_pool_vaddr;
>-	struct ida stage_ids;
>-	struct i915_vma *shared_data;
>-	void *shared_data_vaddr;
>-
>-	struct intel_guc_client *execbuf_client;
>-	struct intel_guc_client *preempt_client;
>-
>-	struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
>-	struct workqueue_struct *preempt_wq;
>-
>-	DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
>-	/* Cyclic counter mod pagesize	*/
>-	u32 db_cacheline;
>-
>-	/* GuC's FW specific registers used in MMIO send */
>-	struct {
>-		u32 base;
>-		unsigned int count;
>-		enum forcewake_domains fw_domains;
>-	} send_regs;
>-
>-	/* To serialize the intel_guc_send actions */
>-	struct mutex send_mutex;
>-
>-	/* GuC's FW specific send function */
>-	int (*send)(struct intel_guc *guc, const u32 *data, u32 len,
>-		    u32 *response_buf, u32 response_buf_size);
>-
>-	/* GuC's FW specific event handler function */
>-	void (*handler)(struct intel_guc *guc);
>-
>-	/* GuC's FW specific notify function */
>-	void (*notify)(struct intel_guc *guc);
>-};
>-
>-static
>-inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
>-{
>-	return guc->send(guc, action, len, NULL, 0);
>-}
>-
>-static inline int
>-intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
>-			   u32 *response_buf, u32 response_buf_size)
>-{
>-	return guc->send(guc, action, len, response_buf, response_buf_size);
>-}
>-
>-static inline void intel_guc_notify(struct intel_guc *guc)
>-{
>-	guc->notify(guc);
>-}
>-
>-static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
>-{
>-	guc->handler(guc);
>-}
>-
>-/* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
>-#define GUC_GGTT_TOP	0xFEE00000
>-
>-/**
>- * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
>- * @guc: intel_guc structure.
>- * @vma: i915 graphics virtual memory area.
>- *
>- * GuC does not allow any gfx GGTT address that falls into range
>- * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
>- * Currently, in order to exclude [0, ggtt.pin_bias) address space from
>- * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
>- * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
>- *
>- * Return: GGTT offset of the @vma.
>- */
>-static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
>-					struct i915_vma *vma)
>-{
>-	u32 offset = i915_ggtt_offset(vma);
>-
>-	GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
>-	GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
>-
>-	return offset;
>-}
>-
>-void intel_guc_init_early(struct intel_guc *guc);
>-void intel_guc_init_send_regs(struct intel_guc *guc);
>-void intel_guc_init_params(struct intel_guc *guc);
>-int intel_guc_init_misc(struct intel_guc *guc);
>-int intel_guc_init(struct intel_guc *guc);
>-void intel_guc_fini(struct intel_guc *guc);
>-void intel_guc_fini_misc(struct intel_guc *guc);
>-int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
>-		       u32 *response_buf, u32 response_buf_size);
>-int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
>-			u32 *response_buf, u32 response_buf_size);
>-void intel_guc_to_host_event_handler(struct intel_guc *guc);
>-void intel_guc_to_host_event_handler_nop(struct intel_guc *guc);
>-int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
>-				       const u32 *payload, u32 len);
>-int intel_guc_sample_forcewake(struct intel_guc *guc);
>-int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
>-int intel_guc_suspend(struct intel_guc *guc);
>-int intel_guc_resume(struct intel_guc *guc);
>-struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
>-
>-static inline bool intel_guc_is_loaded(struct intel_guc *guc)
>-{
>-	return intel_uc_fw_is_loaded(&guc->fw);
>-}
>-
>-static inline int intel_guc_sanitize(struct intel_guc *guc)
>-{
>-	intel_uc_fw_sanitize(&guc->fw);
>-	return 0;
>-}
>-
>-static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
>-{
>-	spin_lock_irq(&guc->irq_lock);
>-	guc->msg_enabled_mask |= mask;
>-	spin_unlock_irq(&guc->irq_lock);
>-}
>-
>-static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
>-{
>-	spin_lock_irq(&guc->irq_lock);
>-	guc->msg_enabled_mask &= ~mask;
>-	spin_unlock_irq(&guc->irq_lock);
>-}
>-
>-int intel_guc_reset_engine(struct intel_guc *guc,
>-			   struct intel_engine_cs *engine);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_log.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_log.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_log.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_log.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,632 +0,0 @@
>-/*
>- * Copyright Â© 2014-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#include <linux/debugfs.h>
>-
>-#include "intel_guc_log.h"
>-#include "i915_drv.h"
>-
>-static void guc_log_capture_logs(struct intel_guc_log *log);
>-
>-/**
>- * DOC: GuC firmware log
>- *
>- * Firmware log is enabled by setting i915.guc_log_level to the positive level.
>- * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
>- * i915_guc_load_status will print out firmware loading status and scratch
>- * registers value.
>- */
>-
>-static int guc_action_flush_log_complete(struct intel_guc *guc)
>-{
>-	u32 action[] = {
>-		INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE
>-	};
>-
>-	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>-}
>-
>-static int guc_action_flush_log(struct intel_guc *guc)
>-{
>-	u32 action[] = {
>-		INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH,
>-		0
>-	};
>-
>-	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>-}
>-
>-static int guc_action_control_log(struct intel_guc *guc, bool enable,
>-				  bool default_logging, u32 verbosity)
>-{
>-	u32 action[] = {
>-		INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING,
>-		(enable ? GUC_LOG_CONTROL_LOGGING_ENABLED : 0) |
>-		(verbosity << GUC_LOG_CONTROL_VERBOSITY_SHIFT) |
>-		(default_logging ? GUC_LOG_CONTROL_DEFAULT_LOGGING : 0)
>-	};
>-
>-	GEM_BUG_ON(verbosity > GUC_LOG_VERBOSITY_MAX);
>-
>-	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>-}
>-
>-static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
>-{
>-	return container_of(log, struct intel_guc, log);
>-}
>-
>-static void guc_log_enable_flush_events(struct intel_guc_log *log)
>-{
>-	intel_guc_enable_msg(log_to_guc(log),
>-			     INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
>-			     INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
>-}
>-
>-static void guc_log_disable_flush_events(struct intel_guc_log *log)
>-{
>-	intel_guc_disable_msg(log_to_guc(log),
>-			      INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
>-			      INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
>-}
>-
>-/*
>- * Sub buffer switch callback. Called whenever relay has to switch to a new
>- * sub buffer, relay stays on the same sub buffer if 0 is returned.
>- */
>-static int subbuf_start_callback(struct rchan_buf *buf,
>-				 void *subbuf,
>-				 void *prev_subbuf,
>-				 size_t prev_padding)
>-{
>-	/*
>-	 * Use no-overwrite mode by default, where relay will stop accepting
>-	 * new data if there are no empty sub buffers left.
>-	 * There is no strict synchronization enforced by relay between Consumer
>-	 * and Producer. In overwrite mode, there is a possibility of getting
>-	 * inconsistent/garbled data, the producer could be writing on to the
>-	 * same sub buffer from which Consumer is reading. This can't be avoided
>-	 * unless Consumer is fast enough and can always run in tandem with
>-	 * Producer.
>-	 */
>-	if (relay_buf_full(buf))
>-		return 0;
>-
>-	return 1;
>-}
>-
>-/*
>- * file_create() callback. Creates relay file in debugfs.
>- */
>-static struct dentry *create_buf_file_callback(const char *filename,
>-					       struct dentry *parent,
>-					       umode_t mode,
>-					       struct rchan_buf *buf,
>-					       int *is_global)
>-{
>-	struct dentry *buf_file;
>-
>-	/*
>-	 * This to enable the use of a single buffer for the relay channel and
>-	 * correspondingly have a single file exposed to User, through which
>-	 * it can collect the logs in order without any post-processing.
>-	 * Need to set 'is_global' even if parent is NULL for early logging.
>-	 */
>-	*is_global = 1;
>-
>-	if (!parent)
>-		return NULL;
>-
>-	buf_file = debugfs_create_file(filename, mode,
>-				       parent, buf, &relay_file_operations);
>-	if (IS_ERR(buf_file))
>-		return NULL;
>-
>-	return buf_file;
>-}
>-
>-/*
>- * file_remove() default callback. Removes relay file in debugfs.
>- */
>-static int remove_buf_file_callback(struct dentry *dentry)
>-{
>-	debugfs_remove(dentry);
>-	return 0;
>-}
>-
>-/* relay channel callbacks */
>-static struct rchan_callbacks relay_callbacks = {
>-	.subbuf_start = subbuf_start_callback,
>-	.create_buf_file = create_buf_file_callback,
>-	.remove_buf_file = remove_buf_file_callback,
>-};
>-
>-static void guc_move_to_next_buf(struct intel_guc_log *log)
>-{
>-	/*
>-	 * Make sure the updates made in the sub buffer are visible when
>-	 * Consumer sees the following update to offset inside the sub buffer.
>-	 */
>-	smp_wmb();
>-
>-	/* All data has been written, so now move the offset of sub buffer. */
>-	relay_reserve(log->relay.channel, log->vma->obj->base.size);
>-
>-	/* Switch to the next sub buffer */
>-	relay_flush(log->relay.channel);
>-}
>-
>-static void *guc_get_write_buffer(struct intel_guc_log *log)
>-{
>-	/*
>-	 * Just get the base address of a new sub buffer and copy data into it
>-	 * ourselves. NULL will be returned in no-overwrite mode, if all sub
>-	 * buffers are full. Could have used the relay_write() to indirectly
>-	 * copy the data, but that would have been bit convoluted, as we need to
>-	 * write to only certain locations inside a sub buffer which cannot be
>-	 * done without using relay_reserve() along with relay_write(). So its
>-	 * better to use relay_reserve() alone.
>-	 */
>-	return relay_reserve(log->relay.channel, 0);
>-}
>-
>-static bool guc_check_log_buf_overflow(struct intel_guc_log *log,
>-				       enum guc_log_buffer_type type,
>-				       unsigned int full_cnt)
>-{
>-	unsigned int prev_full_cnt = log->stats[type].sampled_overflow;
>-	bool overflow = false;
>-
>-	if (full_cnt != prev_full_cnt) {
>-		overflow = true;
>-
>-		log->stats[type].overflow = full_cnt;
>-		log->stats[type].sampled_overflow += full_cnt - prev_full_cnt;
>-
>-		if (full_cnt < prev_full_cnt) {
>-			/* buffer_full_cnt is a 4 bit counter */
>-			log->stats[type].sampled_overflow += 16;
>-		}
>-
>-		dev_notice_ratelimited(guc_to_i915(log_to_guc(log))->drm.dev,
>-				       "GuC log buffer overflow\n");
>-	}
>-
>-	return overflow;
>-}
>-
>-static unsigned int guc_get_log_buffer_size(enum guc_log_buffer_type type)
>-{
>-	switch (type) {
>-	case GUC_ISR_LOG_BUFFER:
>-		return ISR_BUFFER_SIZE;
>-	case GUC_DPC_LOG_BUFFER:
>-		return DPC_BUFFER_SIZE;
>-	case GUC_CRASH_DUMP_LOG_BUFFER:
>-		return CRASH_BUFFER_SIZE;
>-	default:
>-		MISSING_CASE(type);
>-	}
>-
>-	return 0;
>-}
>-
>-static void guc_read_update_log_buffer(struct intel_guc_log *log)
>-{
>-	unsigned int buffer_size, read_offset, write_offset, bytes_to_copy, full_cnt;
>-	struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
>-	struct guc_log_buffer_state log_buf_state_local;
>-	enum guc_log_buffer_type type;
>-	void *src_data, *dst_data;
>-	bool new_overflow;
>-
>-	mutex_lock(&log->relay.lock);
>-
>-	if (WARN_ON(!intel_guc_log_relay_enabled(log)))
>-		goto out_unlock;
>-
>-	/* Get the pointer to shared GuC log buffer */
>-	log_buf_state = src_data = log->relay.buf_addr;
>-
>-	/* Get the pointer to local buffer to store the logs */
>-	log_buf_snapshot_state = dst_data = guc_get_write_buffer(log);
>-
>-	if (unlikely(!log_buf_snapshot_state)) {
>-		/*
>-		 * Used rate limited to avoid deluge of messages, logs might be
>-		 * getting consumed by User at a slow rate.
>-		 */
>-		DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
>-		log->relay.full_count++;
>-
>-		goto out_unlock;
>-	}
>-
>-	/* Actual logs are present from the 2nd page */
>-	src_data += PAGE_SIZE;
>-	dst_data += PAGE_SIZE;
>-
>-	for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
>-		/*
>-		 * Make a copy of the state structure, inside GuC log buffer
>-		 * (which is uncached mapped), on the stack to avoid reading
>-		 * from it multiple times.
>-		 */
>-		memcpy(&log_buf_state_local, log_buf_state,
>-		       sizeof(struct guc_log_buffer_state));
>-		buffer_size = guc_get_log_buffer_size(type);
>-		read_offset = log_buf_state_local.read_ptr;
>-		write_offset = log_buf_state_local.sampled_write_ptr;
>-		full_cnt = log_buf_state_local.buffer_full_cnt;
>-
>-		/* Bookkeeping stuff */
>-		log->stats[type].flush += log_buf_state_local.flush_to_file;
>-		new_overflow = guc_check_log_buf_overflow(log, type, full_cnt);
>-
>-		/* Update the state of shared log buffer */
>-		log_buf_state->read_ptr = write_offset;
>-		log_buf_state->flush_to_file = 0;
>-		log_buf_state++;
>-
>-		/* First copy the state structure in snapshot buffer */
>-		memcpy(log_buf_snapshot_state, &log_buf_state_local,
>-		       sizeof(struct guc_log_buffer_state));
>-
>-		/*
>-		 * The write pointer could have been updated by GuC firmware,
>-		 * after sending the flush interrupt to Host, for consistency
>-		 * set write pointer value to same value of sampled_write_ptr
>-		 * in the snapshot buffer.
>-		 */
>-		log_buf_snapshot_state->write_ptr = write_offset;
>-		log_buf_snapshot_state++;
>-
>-		/* Now copy the actual logs. */
>-		if (unlikely(new_overflow)) {
>-			/* copy the whole buffer in case of overflow */
>-			read_offset = 0;
>-			write_offset = buffer_size;
>-		} else if (unlikely((read_offset > buffer_size) ||
>-				    (write_offset > buffer_size))) {
>-			DRM_ERROR("invalid log buffer state\n");
>-			/* copy whole buffer as offsets are unreliable */
>-			read_offset = 0;
>-			write_offset = buffer_size;
>-		}
>-
>-		/* Just copy the newly written data */
>-		if (read_offset > write_offset) {
>-			i915_memcpy_from_wc(dst_data, src_data, write_offset);
>-			bytes_to_copy = buffer_size - read_offset;
>-		} else {
>-			bytes_to_copy = write_offset - read_offset;
>-		}
>-		i915_memcpy_from_wc(dst_data + read_offset,
>-				    src_data + read_offset, bytes_to_copy);
>-
>-		src_data += buffer_size;
>-		dst_data += buffer_size;
>-	}
>-
>-	guc_move_to_next_buf(log);
>-
>-out_unlock:
>-	mutex_unlock(&log->relay.lock);
>-}
>-
>-static void capture_logs_work(struct work_struct *work)
>-{
>-	struct intel_guc_log *log =
>-		container_of(work, struct intel_guc_log, relay.flush_work);
>-
>-	guc_log_capture_logs(log);
>-}
>-
>-static int guc_log_map(struct intel_guc_log *log)
>-{
>-	void *vaddr;
>-
>-	lockdep_assert_held(&log->relay.lock);
>-
>-	if (!log->vma)
>-		return -ENODEV;
>-
>-	/*
>-	 * Create a WC (Uncached for read) vmalloc mapping of log
>-	 * buffer pages, so that we can directly get the data
>-	 * (up-to-date) from memory.
>-	 */
>-	vaddr = i915_gem_object_pin_map(log->vma->obj, I915_MAP_WC);
>-	if (IS_ERR(vaddr))
>-		return PTR_ERR(vaddr);
>-
>-	log->relay.buf_addr = vaddr;
>-
>-	return 0;
>-}
>-
>-static void guc_log_unmap(struct intel_guc_log *log)
>-{
>-	lockdep_assert_held(&log->relay.lock);
>-
>-	i915_gem_object_unpin_map(log->vma->obj);
>-	log->relay.buf_addr = NULL;
>-}
>-
>-void intel_guc_log_init_early(struct intel_guc_log *log)
>-{
>-	mutex_init(&log->relay.lock);
>-	INIT_WORK(&log->relay.flush_work, capture_logs_work);
>-}
>-
>-static int guc_log_relay_create(struct intel_guc_log *log)
>-{
>-	struct intel_guc *guc = log_to_guc(log);
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	struct rchan *guc_log_relay_chan;
>-	size_t n_subbufs, subbuf_size;
>-	int ret;
>-
>-	lockdep_assert_held(&log->relay.lock);
>-
>-	 /* Keep the size of sub buffers same as shared log buffer */
>-	subbuf_size = log->vma->size;
>-
>-	/*
>-	 * Store up to 8 snapshots, which is large enough to buffer sufficient
>-	 * boot time logs and provides enough leeway to User, in terms of
>-	 * latency, for consuming the logs from relay. Also doesn't take
>-	 * up too much memory.
>-	 */
>-	n_subbufs = 8;
>-
>-	guc_log_relay_chan = relay_open("guc_log",
>-					dev_priv->drm.primary->debugfs_root,
>-					subbuf_size, n_subbufs,
>-					&relay_callbacks, dev_priv);
>-	if (!guc_log_relay_chan) {
>-		DRM_ERROR("Couldn't create relay chan for GuC logging\n");
>-
>-		ret = -ENOMEM;
>-		return ret;
>-	}
>-
>-	GEM_BUG_ON(guc_log_relay_chan->subbuf_size < subbuf_size);
>-	log->relay.channel = guc_log_relay_chan;
>-
>-	return 0;
>-}
>-
>-static void guc_log_relay_destroy(struct intel_guc_log *log)
>-{
>-	lockdep_assert_held(&log->relay.lock);
>-
>-	relay_close(log->relay.channel);
>-	log->relay.channel = NULL;
>-}
>-
>-static void guc_log_capture_logs(struct intel_guc_log *log)
>-{
>-	struct intel_guc *guc = log_to_guc(log);
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	intel_wakeref_t wakeref;
>-
>-	guc_read_update_log_buffer(log);
>-
>-	/*
>-	 * Generally device is expected to be active only at this
>-	 * time, so get/put should be really quick.
>-	 */
>-	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
>-		guc_action_flush_log_complete(guc);
>-}
>-
>-int intel_guc_log_create(struct intel_guc_log *log)
>-{
>-	struct intel_guc *guc = log_to_guc(log);
>-	struct i915_vma *vma;
>-	u32 guc_log_size;
>-	int ret;
>-
>-	GEM_BUG_ON(log->vma);
>-
>-	/*
>-	 *  GuC Log buffer Layout
>-	 *
>-	 *  +===============================+ 00B
>-	 *  |    Crash dump state header    |
>-	 *  +-------------------------------+ 32B
>-	 *  |       DPC state header        |
>-	 *  +-------------------------------+ 64B
>-	 *  |       ISR state header        |
>-	 *  +-------------------------------+ 96B
>-	 *  |                               |
>-	 *  +===============================+ PAGE_SIZE (4KB)
>-	 *  |        Crash Dump logs        |
>-	 *  +===============================+ + CRASH_SIZE
>-	 *  |           DPC logs            |
>-	 *  +===============================+ + DPC_SIZE
>-	 *  |           ISR logs            |
>-	 *  +===============================+ + ISR_SIZE
>-	 */
>-	guc_log_size = PAGE_SIZE + CRASH_BUFFER_SIZE + DPC_BUFFER_SIZE +
>-			ISR_BUFFER_SIZE;
>-
>-	vma = intel_guc_allocate_vma(guc, guc_log_size);
>-	if (IS_ERR(vma)) {
>-		ret = PTR_ERR(vma);
>-		goto err;
>-	}
>-
>-	log->vma = vma;
>-
>-	log->level = i915_modparams.guc_log_level;
>-
>-	return 0;
>-
>-err:
>-	DRM_ERROR("Failed to allocate GuC log buffer. %d\n", ret);
>-	return ret;
>-}
>-
>-void intel_guc_log_destroy(struct intel_guc_log *log)
>-{
>-	i915_vma_unpin_and_release(&log->vma, 0);
>-}
>-
>-int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)
>-{
>-	struct intel_guc *guc = log_to_guc(log);
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	intel_wakeref_t wakeref;
>-	int ret = 0;
>-
>-	BUILD_BUG_ON(GUC_LOG_VERBOSITY_MIN != 0);
>-	GEM_BUG_ON(!log->vma);
>-
>-	/*
>-	 * GuC is recognizing log levels starting from 0 to max, we're using 0
>-	 * as indication that logging should be disabled.
>-	 */
>-	if (level < GUC_LOG_LEVEL_DISABLED || level > GUC_LOG_LEVEL_MAX)
>-		return -EINVAL;
>-
>-	mutex_lock(&dev_priv->drm.struct_mutex);
>-
>-	if (log->level == level)
>-		goto out_unlock;
>-
>-	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
>-		ret = guc_action_control_log(guc,
>-					     GUC_LOG_LEVEL_IS_VERBOSE(level),
>-					     GUC_LOG_LEVEL_IS_ENABLED(level),
>-					     GUC_LOG_LEVEL_TO_VERBOSITY(level));
>-	if (ret) {
>-		DRM_DEBUG_DRIVER("guc_log_control action failed %d\n", ret);
>-		goto out_unlock;
>-	}
>-
>-	log->level = level;
>-
>-out_unlock:
>-	mutex_unlock(&dev_priv->drm.struct_mutex);
>-
>-	return ret;
>-}
>-
>-bool intel_guc_log_relay_enabled(const struct intel_guc_log *log)
>-{
>-	return log->relay.buf_addr;
>-}
>-
>-int intel_guc_log_relay_open(struct intel_guc_log *log)
>-{
>-	int ret;
>-
>-	mutex_lock(&log->relay.lock);
>-
>-	if (intel_guc_log_relay_enabled(log)) {
>-		ret = -EEXIST;
>-		goto out_unlock;
>-	}
>-
>-	/*
>-	 * We require SSE 4.1 for fast reads from the GuC log buffer and
>-	 * it should be present on the chipsets supporting GuC based
>-	 * submisssions.
>-	 */
>-	if (!i915_has_memcpy_from_wc()) {
>-		ret = -ENXIO;
>-		goto out_unlock;
>-	}
>-
>-	ret = guc_log_relay_create(log);
>-	if (ret)
>-		goto out_unlock;
>-
>-	ret = guc_log_map(log);
>-	if (ret)
>-		goto out_relay;
>-
>-	mutex_unlock(&log->relay.lock);
>-
>-	guc_log_enable_flush_events(log);
>-
>-	/*
>-	 * When GuC is logging without us relaying to userspace, we're ignoring
>-	 * the flush notification. This means that we need to unconditionally
>-	 * flush on relay enabling, since GuC only notifies us once.
>-	 */
>-	queue_work(log->relay.flush_wq, &log->relay.flush_work);
>-
>-	return 0;
>-
>-out_relay:
>-	guc_log_relay_destroy(log);
>-out_unlock:
>-	mutex_unlock(&log->relay.lock);
>-
>-	return ret;
>-}
>-
>-void intel_guc_log_relay_flush(struct intel_guc_log *log)
>-{
>-	struct intel_guc *guc = log_to_guc(log);
>-	struct drm_i915_private *i915 = guc_to_i915(guc);
>-	intel_wakeref_t wakeref;
>-
>-	/*
>-	 * Before initiating the forceful flush, wait for any pending/ongoing
>-	 * flush to complete otherwise forceful flush may not actually happen.
>-	 */
>-	flush_work(&log->relay.flush_work);
>-
>-	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
>-		guc_action_flush_log(guc);
>-
>-	/* GuC would have updated log buffer by now, so capture it */
>-	guc_log_capture_logs(log);
>-}
>-
>-void intel_guc_log_relay_close(struct intel_guc_log *log)
>-{
>-	struct intel_guc *guc = log_to_guc(log);
>-	struct drm_i915_private *i915 = guc_to_i915(guc);
>-
>-	guc_log_disable_flush_events(log);
>-	synchronize_irq(i915->drm.irq);
>-
>-	flush_work(&log->relay.flush_work);
>-
>-	mutex_lock(&log->relay.lock);
>-	GEM_BUG_ON(!intel_guc_log_relay_enabled(log));
>-	guc_log_unmap(log);
>-	guc_log_relay_destroy(log);
>-	mutex_unlock(&log->relay.lock);
>-}
>-
>-void intel_guc_log_handle_flush_event(struct intel_guc_log *log)
>-{
>-	queue_work(log->relay.flush_wq, &log->relay.flush_work);
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_log.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_log.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_log.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_log.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,100 +0,0 @@
>-/*
>- * Copyright Â© 2014-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#ifndef _INTEL_GUC_LOG_H_
>-#define _INTEL_GUC_LOG_H_
>-
>-#include <linux/mutex.h>
>-#include <linux/relay.h>
>-#include <linux/workqueue.h>
>-
>-#include "intel_guc_fwif.h"
>-#include "i915_gem.h"
>-
>-struct intel_guc;
>-
>-#ifdef CONFIG_DRM_I915_DEBUG_GUC
>-#define CRASH_BUFFER_SIZE	SZ_2M
>-#define DPC_BUFFER_SIZE		SZ_8M
>-#define ISR_BUFFER_SIZE		SZ_8M
>-#else
>-#define CRASH_BUFFER_SIZE	SZ_8K
>-#define DPC_BUFFER_SIZE		SZ_32K
>-#define ISR_BUFFER_SIZE		SZ_32K
>-#endif
>-
>-/*
>- * While we're using plain log level in i915, GuC controls are much more...
>- * "elaborate"? We have a couple of bits for verbosity, separate bit for actual
>- * log enabling, and separate bit for default logging - which "conveniently"
>- * ignores the enable bit.
>- */
>-#define GUC_LOG_LEVEL_DISABLED		0
>-#define GUC_LOG_LEVEL_NON_VERBOSE	1
>-#define GUC_LOG_LEVEL_IS_ENABLED(x)	((x) > GUC_LOG_LEVEL_DISABLED)
>-#define GUC_LOG_LEVEL_IS_VERBOSE(x)	((x) > GUC_LOG_LEVEL_NON_VERBOSE)
>-#define GUC_LOG_LEVEL_TO_VERBOSITY(x) ({		\
>-	typeof(x) _x = (x);				\
>-	GUC_LOG_LEVEL_IS_VERBOSE(_x) ? _x - 2 : 0;	\
>-})
>-#define GUC_VERBOSITY_TO_LOG_LEVEL(x)	((x) + 2)
>-#define GUC_LOG_LEVEL_MAX GUC_VERBOSITY_TO_LOG_LEVEL(GUC_LOG_VERBOSITY_MAX)
>-
>-struct intel_guc_log {
>-	u32 level;
>-	struct i915_vma *vma;
>-	struct {
>-		void *buf_addr;
>-		struct workqueue_struct *flush_wq;
>-		struct work_struct flush_work;
>-		struct rchan *channel;
>-		struct mutex lock;
>-		u32 full_count;
>-	} relay;
>-	/* logging related stats */
>-	struct {
>-		u32 sampled_overflow;
>-		u32 overflow;
>-		u32 flush;
>-	} stats[GUC_MAX_LOG_BUFFER];
>-};
>-
>-void intel_guc_log_init_early(struct intel_guc_log *log);
>-int intel_guc_log_create(struct intel_guc_log *log);
>-void intel_guc_log_destroy(struct intel_guc_log *log);
>-
>-int intel_guc_log_set_level(struct intel_guc_log *log, u32 level);
>-bool intel_guc_log_relay_enabled(const struct intel_guc_log *log);
>-int intel_guc_log_relay_open(struct intel_guc_log *log);
>-void intel_guc_log_relay_flush(struct intel_guc_log *log);
>-void intel_guc_log_relay_close(struct intel_guc_log *log);
>-
>-void intel_guc_log_handle_flush_event(struct intel_guc_log *log);
>-
>-static inline u32 intel_guc_log_get_level(struct intel_guc_log *log)
>-{
>-	return log->level;
>-}
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_reg.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_reg.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_reg.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_reg.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,155 +0,0 @@
>-/*
>- * Copyright Â© 2014 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-#ifndef _INTEL_GUC_REG_H_
>-#define _INTEL_GUC_REG_H_
>-
>-/* Definitions of GuC H/W registers, bits, etc */
>-
>-#define GUC_STATUS			_MMIO(0xc000)
>-#define   GS_RESET_SHIFT		0
>-#define   GS_MIA_IN_RESET		  (0x01 << GS_RESET_SHIFT)
>-#define   GS_BOOTROM_SHIFT		1
>-#define   GS_BOOTROM_MASK		  (0x7F << GS_BOOTROM_SHIFT)
>-#define   GS_BOOTROM_RSA_FAILED		  (0x50 << GS_BOOTROM_SHIFT)
>-#define   GS_BOOTROM_JUMP_PASSED	  (0x76 << GS_BOOTROM_SHIFT)
>-#define   GS_UKERNEL_SHIFT		8
>-#define   GS_UKERNEL_MASK		  (0xFF << GS_UKERNEL_SHIFT)
>-#define   GS_UKERNEL_LAPIC_DONE		  (0x30 << GS_UKERNEL_SHIFT)
>-#define   GS_UKERNEL_DPC_ERROR		  (0x60 << GS_UKERNEL_SHIFT)
>-#define   GS_UKERNEL_READY		  (0xF0 << GS_UKERNEL_SHIFT)
>-#define   GS_MIA_SHIFT			16
>-#define   GS_MIA_MASK			  (0x07 << GS_MIA_SHIFT)
>-#define   GS_MIA_CORE_STATE		  (0x01 << GS_MIA_SHIFT)
>-#define   GS_MIA_HALT_REQUESTED		  (0x02 << GS_MIA_SHIFT)
>-#define   GS_MIA_ISR_ENTRY		  (0x04 << GS_MIA_SHIFT)
>-#define   GS_AUTH_STATUS_SHIFT		30
>-#define   GS_AUTH_STATUS_MASK		  (0x03 << GS_AUTH_STATUS_SHIFT)
>-#define   GS_AUTH_STATUS_BAD		  (0x01 << GS_AUTH_STATUS_SHIFT)
>-#define   GS_AUTH_STATUS_GOOD		  (0x02 << GS_AUTH_STATUS_SHIFT)
>-
>-#define SOFT_SCRATCH(n)			_MMIO(0xc180 + (n) * 4)
>-#define SOFT_SCRATCH_COUNT		16
>-
>-#define GEN11_SOFT_SCRATCH(n)		_MMIO(0x190240 + (n) * 4)
>-#define GEN11_SOFT_SCRATCH_COUNT	4
>-
>-#define UOS_RSA_SCRATCH(i)		_MMIO(0xc200 + (i) * 4)
>-#define UOS_RSA_SCRATCH_COUNT		64
>-
>-#define DMA_ADDR_0_LOW			_MMIO(0xc300)
>-#define DMA_ADDR_0_HIGH			_MMIO(0xc304)
>-#define DMA_ADDR_1_LOW			_MMIO(0xc308)
>-#define DMA_ADDR_1_HIGH			_MMIO(0xc30c)
>-#define   DMA_ADDRESS_SPACE_WOPCM	  (7 << 16)
>-#define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
>-#define DMA_COPY_SIZE			_MMIO(0xc310)
>-#define DMA_CTRL			_MMIO(0xc314)
>-#define   HUC_UKERNEL			  (1<<9)
>-#define   UOS_MOVE			  (1<<4)
>-#define   START_DMA			  (1<<0)
>-#define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
>-#define   GUC_WOPCM_OFFSET_VALID	  (1<<0)
>-#define   HUC_LOADING_AGENT_VCR		  (0<<1)
>-#define   HUC_LOADING_AGENT_GUC		  (1<<1)
>-#define   GUC_WOPCM_OFFSET_SHIFT	14
>-#define   GUC_WOPCM_OFFSET_MASK		  (0x3ffff << GUC_WOPCM_OFFSET_SHIFT)
>-#define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>-
>-#define HUC_STATUS2             _MMIO(0xD3B0)
>-#define   HUC_FW_VERIFIED       (1<<7)
>-
>-#define GEN11_HUC_KERNEL_LOAD_INFO	_MMIO(0xC1DC)
>-#define   HUC_LOAD_SUCCESSFUL		  (1 << 0)
>-
>-#define GUC_WOPCM_SIZE			_MMIO(0xc050)
>-#define   GUC_WOPCM_SIZE_LOCKED		  (1<<0)
>-#define   GUC_WOPCM_SIZE_SHIFT		12
>-#define   GUC_WOPCM_SIZE_MASK		  (0xfffff << GUC_WOPCM_SIZE_SHIFT)
>-
>-#define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>-#define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
>-#define GEN9_GT_PM_CONFIG		_MMIO(0x13816c)
>-#define   GT_DOORBELL_ENABLE		  (1<<0)
>-
>-#define GEN8_GTCR			_MMIO(0x4274)
>-#define   GEN8_GTCR_INVALIDATE		  (1<<0)
>-
>-#define GUC_ARAT_C6DIS			_MMIO(0xA178)
>-
>-#define GUC_SHIM_CONTROL		_MMIO(0xc064)
>-#define   GUC_DISABLE_SRAM_INIT_TO_ZEROES	(1<<0)
>-#define   GUC_ENABLE_READ_CACHE_LOGIC		(1<<1)
>-#define   GUC_ENABLE_MIA_CACHING		(1<<2)
>-#define   GUC_GEN10_MSGCH_ENABLE		(1<<4)
>-#define   GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA	(1<<9)
>-#define   GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	(1<<10)
>-#define   GUC_ENABLE_MIA_CLOCK_GATING		(1<<15)
>-#define   GUC_GEN10_SHIM_WC_ENABLE		(1<<21)
>-
>-#define GUC_SEND_INTERRUPT		_MMIO(0xc4c8)
>-#define   GUC_SEND_TRIGGER		  (1<<0)
>-#define GEN11_GUC_HOST_INTERRUPT	_MMIO(0x1901f0)
>-
>-#define GUC_NUM_DOORBELLS		256
>-
>-/* format of the HW-monitored doorbell cacheline */
>-struct guc_doorbell_info {
>-	u32 db_status;
>-#define GUC_DOORBELL_DISABLED		0
>-#define GUC_DOORBELL_ENABLED		1
>-
>-	u32 cookie;
>-	u32 reserved[14];
>-} __packed;
>-
>-#define GEN8_DRBREGL(x)			_MMIO(0x1000 + (x) * 8)
>-#define   GEN8_DRB_VALID		  (1<<0)
>-#define GEN8_DRBREGU(x)			_MMIO(0x1000 + (x) * 8 + 4)
>-
>-#define DE_GUCRMR			_MMIO(0x44054)
>-
>-#define GUC_BCS_RCS_IER			_MMIO(0xC550)
>-#define GUC_VCS2_VCS1_IER		_MMIO(0xC554)
>-#define GUC_WD_VECS_IER			_MMIO(0xC558)
>-#define GUC_PM_P24C_IER			_MMIO(0xC55C)
>-
>-/* GuC Interrupt Vector */
>-#define GEN11_GUC_INTR_GUC2HOST		(1 << 15)
>-#define GEN11_GUC_INTR_EXEC_ERROR	(1 << 14)
>-#define GEN11_GUC_INTR_DISPLAY_EVENT	(1 << 13)
>-#define GEN11_GUC_INTR_SEM_SIG		(1 << 12)
>-#define GEN11_GUC_INTR_IOMMU2GUC	(1 << 11)
>-#define GEN11_GUC_INTR_DOORBELL_RANG	(1 << 10)
>-#define GEN11_GUC_INTR_DMA_DONE		(1 <<  9)
>-#define GEN11_GUC_INTR_FATAL_ERROR	(1 <<  8)
>-#define GEN11_GUC_INTR_NOTIF_ERROR	(1 <<  7)
>-#define GEN11_GUC_INTR_SW_INT_6		(1 <<  6)
>-#define GEN11_GUC_INTR_SW_INT_5		(1 <<  5)
>-#define GEN11_GUC_INTR_SW_INT_4		(1 <<  4)
>-#define GEN11_GUC_INTR_SW_INT_3		(1 <<  3)
>-#define GEN11_GUC_INTR_SW_INT_2		(1 <<  2)
>-#define GEN11_GUC_INTR_SW_INT_1		(1 <<  1)
>-#define GEN11_GUC_INTR_SW_INT_0		(1 <<  0)
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_submission.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_submission.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_submission.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_submission.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,1458 +0,0 @@
>-/*
>- * Copyright Â© 2014 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#include <linux/circ_buf.h>
>-
>-#include "gt/intel_engine_pm.h"
>-#include "gt/intel_lrc_reg.h"
>-#include "gt/intel_context.h"
>-#include "gem/i915_gem_context.h"
>-
>-#include "intel_guc_submission.h"
>-#include "i915_drv.h"
>-
>-#define GUC_PREEMPT_FINISHED		0x1
>-#define GUC_PREEMPT_BREADCRUMB_DWORDS	0x8
>-#define GUC_PREEMPT_BREADCRUMB_BYTES	\
>-	(sizeof(u32) * GUC_PREEMPT_BREADCRUMB_DWORDS)
>-
>-/**
>- * DOC: GuC-based command submission
>- *
>- * GuC client:
>- * A intel_guc_client refers to a submission path through GuC. Currently, there
>- * are two clients. One of them (the execbuf_client) is charged with all
>- * submissions to the GuC, the other one (preempt_client) is responsible for
>- * preempting the execbuf_client. This struct is the owner of a doorbell, a
>- * process descriptor and a workqueue (all of them inside a single gem object
>- * that contains all required pages for these elements).
>- *
>- * GuC stage descriptor:
>- * During initialization, the driver allocates a static pool of 1024 such
>- * descriptors, and shares them with the GuC.
>- * Currently, there exists a 1:1 mapping between a intel_guc_client and a
>- * guc_stage_desc (via the client's stage_id), so effectively only one
>- * gets used. This stage descriptor lets the GuC know about the doorbell,
>- * workqueue and process descriptor. Theoretically, it also lets the GuC
>- * know about our HW contexts (context ID, etc...), but we actually
>- * employ a kind of submission where the GuC uses the LRCA sent via the work
>- * item instead (the single guc_stage_desc associated to execbuf client
>- * contains information about the default kernel context only, but this is
>- * essentially unused). This is called a "proxy" submission.
>- *
>- * The Scratch registers:
>- * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
>- * a value to the action register (SOFT_SCRATCH_0) along with any data. It then
>- * triggers an interrupt on the GuC via another register write (0xC4C8).
>- * Firmware writes a success/fail code back to the action register after
>- * processes the request. The kernel driver polls waiting for this update and
>- * then proceeds.
>- * See intel_guc_send()
>- *
>- * Doorbells:
>- * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
>- * mapped into process space.
>- *
>- * Work Items:
>- * There are several types of work items that the host may place into a
>- * workqueue, each with its own requirements and limitations. Currently only
>- * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
>- * represents in-order queue. The kernel driver packs ring tail pointer and an
>- * ELSP context descriptor dword into Work Item.
>- * See guc_add_request()
>- *
>- */
>-
>-static inline u32 intel_hws_preempt_done_address(struct intel_engine_cs *engine)
>-{
>-	return (i915_ggtt_offset(engine->status_page.vma) +
>-		I915_GEM_HWS_PREEMPT_ADDR);
>-}
>-
>-static inline struct i915_priolist *to_priolist(struct rb_node *rb)
>-{
>-	return rb_entry(rb, struct i915_priolist, node);
>-}
>-
>-static inline bool is_high_priority(struct intel_guc_client *client)
>-{
>-	return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH ||
>-		client->priority == GUC_CLIENT_PRIORITY_HIGH);
>-}
>-
>-static int reserve_doorbell(struct intel_guc_client *client)
>-{
>-	unsigned long offset;
>-	unsigned long end;
>-	u16 id;
>-
>-	GEM_BUG_ON(client->doorbell_id != GUC_DOORBELL_INVALID);
>-
>-	/*
>-	 * The bitmap tracks which doorbell registers are currently in use.
>-	 * It is split into two halves; the first half is used for normal
>-	 * priority contexts, the second half for high-priority ones.
>-	 */
>-	offset = 0;
>-	end = GUC_NUM_DOORBELLS / 2;
>-	if (is_high_priority(client)) {
>-		offset = end;
>-		end += offset;
>-	}
>-
>-	id = find_next_zero_bit(client->guc->doorbell_bitmap, end, offset);
>-	if (id == end)
>-		return -ENOSPC;
>-
>-	__set_bit(id, client->guc->doorbell_bitmap);
>-	client->doorbell_id = id;
>-	DRM_DEBUG_DRIVER("client %u (high prio=%s) reserved doorbell: %d\n",
>-			 client->stage_id, yesno(is_high_priority(client)),
>-			 id);
>-	return 0;
>-}
>-
>-static bool has_doorbell(struct intel_guc_client *client)
>-{
>-	if (client->doorbell_id == GUC_DOORBELL_INVALID)
>-		return false;
>-
>-	return test_bit(client->doorbell_id, client->guc->doorbell_bitmap);
>-}
>-
>-static void unreserve_doorbell(struct intel_guc_client *client)
>-{
>-	GEM_BUG_ON(!has_doorbell(client));
>-
>-	__clear_bit(client->doorbell_id, client->guc->doorbell_bitmap);
>-	client->doorbell_id = GUC_DOORBELL_INVALID;
>-}
>-
>-/*
>- * Tell the GuC to allocate or deallocate a specific doorbell
>- */
>-
>-static int __guc_allocate_doorbell(struct intel_guc *guc, u32 stage_id)
>-{
>-	u32 action[] = {
>-		INTEL_GUC_ACTION_ALLOCATE_DOORBELL,
>-		stage_id
>-	};
>-
>-	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>-}
>-
>-static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 stage_id)
>-{
>-	u32 action[] = {
>-		INTEL_GUC_ACTION_DEALLOCATE_DOORBELL,
>-		stage_id
>-	};
>-
>-	return intel_guc_send(guc, action, ARRAY_SIZE(action));
>-}
>-
>-static struct guc_stage_desc *__get_stage_desc(struct intel_guc_client *client)
>-{
>-	struct guc_stage_desc *base = client->guc->stage_desc_pool_vaddr;
>-
>-	return &base[client->stage_id];
>-}
>-
>-/*
>- * Initialise, update, or clear doorbell data shared with the GuC
>- *
>- * These functions modify shared data and so need access to the mapped
>- * client object which contains the page being used for the doorbell
>- */
>-
>-static void __update_doorbell_desc(struct intel_guc_client *client, u16 new_id)
>-{
>-	struct guc_stage_desc *desc;
>-
>-	/* Update the GuC's idea of the doorbell ID */
>-	desc = __get_stage_desc(client);
>-	desc->db_id = new_id;
>-}
>-
>-static struct guc_doorbell_info *__get_doorbell(struct intel_guc_client *client)
>-{
>-	return client->vaddr + client->doorbell_offset;
>-}
>-
>-static bool __doorbell_valid(struct intel_guc *guc, u16 db_id)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-
>-	GEM_BUG_ON(db_id >= GUC_NUM_DOORBELLS);
>-	return I915_READ(GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID;
>-}
>-
>-static void __init_doorbell(struct intel_guc_client *client)
>-{
>-	struct guc_doorbell_info *doorbell;
>-
>-	doorbell = __get_doorbell(client);
>-	doorbell->db_status = GUC_DOORBELL_ENABLED;
>-	doorbell->cookie = 0;
>-}
>-
>-static void __fini_doorbell(struct intel_guc_client *client)
>-{
>-	struct guc_doorbell_info *doorbell;
>-	u16 db_id = client->doorbell_id;
>-
>-	doorbell = __get_doorbell(client);
>-	doorbell->db_status = GUC_DOORBELL_DISABLED;
>-
>-	/* Doorbell release flow requires that we wait for GEN8_DRB_VALID bit
>-	 * to go to zero after updating db_status before we call the GuC to
>-	 * release the doorbell
>-	 */
>-	if (wait_for_us(!__doorbell_valid(client->guc, db_id), 10))
>-		WARN_ONCE(true, "Doorbell never became invalid after disable\n");
>-}
>-
>-static int create_doorbell(struct intel_guc_client *client)
>-{
>-	int ret;
>-
>-	if (WARN_ON(!has_doorbell(client)))
>-		return -ENODEV; /* internal setup error, should never happen */
>-
>-	__update_doorbell_desc(client, client->doorbell_id);
>-	__init_doorbell(client);
>-
>-	ret = __guc_allocate_doorbell(client->guc, client->stage_id);
>-	if (ret) {
>-		__fini_doorbell(client);
>-		__update_doorbell_desc(client, GUC_DOORBELL_INVALID);
>-		DRM_DEBUG_DRIVER("Couldn't create client %u doorbell: %d\n",
>-				 client->stage_id, ret);
>-		return ret;
>-	}
>-
>-	return 0;
>-}
>-
>-static int destroy_doorbell(struct intel_guc_client *client)
>-{
>-	int ret;
>-
>-	GEM_BUG_ON(!has_doorbell(client));
>-
>-	__fini_doorbell(client);
>-	ret = __guc_deallocate_doorbell(client->guc, client->stage_id);
>-	if (ret)
>-		DRM_ERROR("Couldn't destroy client %u doorbell: %d\n",
>-			  client->stage_id, ret);
>-
>-	__update_doorbell_desc(client, GUC_DOORBELL_INVALID);
>-
>-	return ret;
>-}
>-
>-static unsigned long __select_cacheline(struct intel_guc *guc)
>-{
>-	unsigned long offset;
>-
>-	/* Doorbell uses a single cache line within a page */
>-	offset = offset_in_page(guc->db_cacheline);
>-
>-	/* Moving to next cache line to reduce contention */
>-	guc->db_cacheline += cache_line_size();
>-
>-	DRM_DEBUG_DRIVER("reserved cacheline 0x%lx, next 0x%x, linesize %u\n",
>-			 offset, guc->db_cacheline, cache_line_size());
>-	return offset;
>-}
>-
>-static inline struct guc_process_desc *
>-__get_process_desc(struct intel_guc_client *client)
>-{
>-	return client->vaddr + client->proc_desc_offset;
>-}
>-
>-/*
>- * Initialise the process descriptor shared with the GuC firmware.
>- */
>-static void guc_proc_desc_init(struct intel_guc_client *client)
>-{
>-	struct guc_process_desc *desc;
>-
>-	desc = memset(__get_process_desc(client), 0, sizeof(*desc));
>-
>-	/*
>-	 * XXX: pDoorbell and WQVBaseAddress are pointers in process address
>-	 * space for ring3 clients (set them as in mmap_ioctl) or kernel
>-	 * space for kernel clients (map on demand instead? May make debug
>-	 * easier to have it mapped).
>-	 */
>-	desc->wq_base_addr = 0;
>-	desc->db_base_addr = 0;
>-
>-	desc->stage_id = client->stage_id;
>-	desc->wq_size_bytes = GUC_WQ_SIZE;
>-	desc->wq_status = WQ_STATUS_ACTIVE;
>-	desc->priority = client->priority;
>-}
>-
>-static void guc_proc_desc_fini(struct intel_guc_client *client)
>-{
>-	struct guc_process_desc *desc;
>-
>-	desc = __get_process_desc(client);
>-	memset(desc, 0, sizeof(*desc));
>-}
>-
>-static int guc_stage_desc_pool_create(struct intel_guc *guc)
>-{
>-	struct i915_vma *vma;
>-	void *vaddr;
>-
>-	vma = intel_guc_allocate_vma(guc,
>-				     PAGE_ALIGN(sizeof(struct guc_stage_desc) *
>-				     GUC_MAX_STAGE_DESCRIPTORS));
>-	if (IS_ERR(vma))
>-		return PTR_ERR(vma);
>-
>-	vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
>-	if (IS_ERR(vaddr)) {
>-		i915_vma_unpin_and_release(&vma, 0);
>-		return PTR_ERR(vaddr);
>-	}
>-
>-	guc->stage_desc_pool = vma;
>-	guc->stage_desc_pool_vaddr = vaddr;
>-	ida_init(&guc->stage_ids);
>-
>-	return 0;
>-}
>-
>-static void guc_stage_desc_pool_destroy(struct intel_guc *guc)
>-{
>-	ida_destroy(&guc->stage_ids);
>-	i915_vma_unpin_and_release(&guc->stage_desc_pool, I915_VMA_RELEASE_MAP);
>-}
>-
>-/*
>- * Initialise/clear the stage descriptor shared with the GuC firmware.
>- *
>- * This descriptor tells the GuC where (in GGTT space) to find the important
>- * data structures relating to this client (doorbell, process descriptor,
>- * write queue, etc).
>- */
>-static void guc_stage_desc_init(struct intel_guc_client *client)
>-{
>-	struct intel_guc *guc = client->guc;
>-	struct i915_gem_context *ctx = client->owner;
>-	struct i915_gem_engines_iter it;
>-	struct guc_stage_desc *desc;
>-	struct intel_context *ce;
>-	u32 gfx_addr;
>-
>-	desc = __get_stage_desc(client);
>-	memset(desc, 0, sizeof(*desc));
>-
>-	desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE |
>-			  GUC_STAGE_DESC_ATTR_KERNEL;
>-	if (is_high_priority(client))
>-		desc->attribute |= GUC_STAGE_DESC_ATTR_PREEMPT;
>-	desc->stage_id = client->stage_id;
>-	desc->priority = client->priority;
>-	desc->db_id = client->doorbell_id;
>-
>-	for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
>-		struct guc_execlist_context *lrc;
>-
>-		if (!(ce->engine->mask & client->engines))
>-			continue;
>-
>-		/* TODO: We have a design issue to be solved here. Only when we
>-		 * receive the first batch, we know which engine is used by the
>-		 * user. But here GuC expects the lrc and ring to be pinned. It
>-		 * is not an issue for default context, which is the only one
>-		 * for now who owns a GuC client. But for future owner of GuC
>-		 * client, need to make sure lrc is pinned prior to enter here.
>-		 */
>-		if (!ce->state)
>-			break;	/* XXX: continue? */
>-
>-		/*
>-		 * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
>-		 * submission or, in other words, not using a direct submission
>-		 * model) the KMD's LRCA is not used for any work submission.
>-		 * Instead, the GuC uses the LRCA of the user mode context (see
>-		 * guc_add_request below).
>-		 */
>-		lrc = &desc->lrc[ce->engine->guc_id];
>-		lrc->context_desc = lower_32_bits(ce->lrc_desc);
>-
>-		/* The state page is after PPHWSP */
>-		lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
>-				 LRC_STATE_PN * PAGE_SIZE;
>-
>-		/* XXX: In direct submission, the GuC wants the HW context id
>-		 * here. In proxy submission, it wants the stage id
>-		 */
>-		lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
>-				(ce->engine->guc_id << GUC_ELC_ENGINE_OFFSET);
>-
>-		lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
>-		lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
>-		lrc->ring_next_free_location = lrc->ring_begin;
>-		lrc->ring_current_tail_pointer_value = 0;
>-
>-		desc->engines_used |= BIT(ce->engine->guc_id);
>-	}
>-	i915_gem_context_unlock_engines(ctx);
>-
>-	DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
>-			 client->engines, desc->engines_used);
>-	WARN_ON(desc->engines_used == 0);
>-
>-	/*
>-	 * The doorbell, process descriptor, and workqueue are all parts
>-	 * of the client object, which the GuC will reference via the GGTT
>-	 */
>-	gfx_addr = intel_guc_ggtt_offset(guc, client->vma);
>-	desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) +
>-				client->doorbell_offset;
>-	desc->db_trigger_cpu = ptr_to_u64(__get_doorbell(client));
>-	desc->db_trigger_uk = gfx_addr + client->doorbell_offset;
>-	desc->process_desc = gfx_addr + client->proc_desc_offset;
>-	desc->wq_addr = gfx_addr + GUC_DB_SIZE;
>-	desc->wq_size = GUC_WQ_SIZE;
>-
>-	desc->desc_private = ptr_to_u64(client);
>-}
>-
>-static void guc_stage_desc_fini(struct intel_guc_client *client)
>-{
>-	struct guc_stage_desc *desc;
>-
>-	desc = __get_stage_desc(client);
>-	memset(desc, 0, sizeof(*desc));
>-}
>-
>-/* Construct a Work Item and append it to the GuC's Work Queue */
>-static void guc_wq_item_append(struct intel_guc_client *client,
>-			       u32 target_engine, u32 context_desc,
>-			       u32 ring_tail, u32 fence_id)
>-{
>-	/* wqi_len is in DWords, and does not include the one-word header */
>-	const size_t wqi_size = sizeof(struct guc_wq_item);
>-	const u32 wqi_len = wqi_size / sizeof(u32) - 1;
>-	struct guc_process_desc *desc = __get_process_desc(client);
>-	struct guc_wq_item *wqi;
>-	u32 wq_off;
>-
>-	lockdep_assert_held(&client->wq_lock);
>-
>-	/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
>-	 * should not have the case where structure wqi is across page, neither
>-	 * wrapped to the beginning. This simplifies the implementation below.
>-	 *
>-	 * XXX: if not the case, we need save data to a temp wqi and copy it to
>-	 * workqueue buffer dw by dw.
>-	 */
>-	BUILD_BUG_ON(wqi_size != 16);
>-
>-	/* We expect the WQ to be active if we're appending items to it */
>-	GEM_BUG_ON(desc->wq_status != WQ_STATUS_ACTIVE);
>-
>-	/* Free space is guaranteed. */
>-	wq_off = READ_ONCE(desc->tail);
>-	GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head),
>-			      GUC_WQ_SIZE) < wqi_size);
>-	GEM_BUG_ON(wq_off & (wqi_size - 1));
>-
>-	/* WQ starts from the page after doorbell / process_desc */
>-	wqi = client->vaddr + wq_off + GUC_DB_SIZE;
>-
>-	if (I915_SELFTEST_ONLY(client->use_nop_wqi)) {
>-		wqi->header = WQ_TYPE_NOOP | (wqi_len << WQ_LEN_SHIFT);
>-	} else {
>-		/* Now fill in the 4-word work queue item */
>-		wqi->header = WQ_TYPE_INORDER |
>-			      (wqi_len << WQ_LEN_SHIFT) |
>-			      (target_engine << WQ_TARGET_SHIFT) |
>-			      WQ_NO_WCFLUSH_WAIT;
>-		wqi->context_desc = context_desc;
>-		wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT;
>-		GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX);
>-		wqi->fence_id = fence_id;
>-	}
>-
>-	/* Make the update visible to GuC */
>-	WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1));
>-}
>-
>-static void guc_ring_doorbell(struct intel_guc_client *client)
>-{
>-	struct guc_doorbell_info *db;
>-	u32 cookie;
>-
>-	lockdep_assert_held(&client->wq_lock);
>-
>-	/* pointer of current doorbell cacheline */
>-	db = __get_doorbell(client);
>-
>-	/*
>-	 * We're not expecting the doorbell cookie to change behind our back,
>-	 * we also need to treat 0 as a reserved value.
>-	 */
>-	cookie = READ_ONCE(db->cookie);
>-	WARN_ON_ONCE(xchg(&db->cookie, cookie + 1 ?: cookie + 2) != cookie);
>-
>-	/* XXX: doorbell was lost and need to acquire it again */
>-	GEM_BUG_ON(db->db_status != GUC_DOORBELL_ENABLED);
>-}
>-
>-static void guc_add_request(struct intel_guc *guc, struct i915_request *rq)
>-{
>-	struct intel_guc_client *client = guc->execbuf_client;
>-	struct intel_engine_cs *engine = rq->engine;
>-	u32 ctx_desc = lower_32_bits(rq->hw_context->lrc_desc);
>-	u32 ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64);
>-
>-	spin_lock(&client->wq_lock);
>-
>-	guc_wq_item_append(client, engine->guc_id, ctx_desc,
>-			   ring_tail, rq->fence.seqno);
>-	guc_ring_doorbell(client);
>-
>-	client->submissions[engine->id] += 1;
>-
>-	spin_unlock(&client->wq_lock);
>-}
>-
>-/*
>- * When we're doing submissions using regular execlists backend, writing to
>- * ELSP from CPU side is enough to make sure that writes to ringbuffer pages
>- * pinned in mappable aperture portion of GGTT are visible to command streamer.
>- * Writes done by GuC on our behalf are not guaranteeing such ordering,
>- * therefore, to ensure the flush, we're issuing a POSTING READ.
>- */
>-static void flush_ggtt_writes(struct i915_vma *vma)
>-{
>-	struct drm_i915_private *i915 = vma->vm->i915;
>-
>-	if (i915_vma_is_map_and_fenceable(vma))
>-		intel_uncore_posting_read_fw(&i915->uncore, GUC_STATUS);
>-}
>-
>-static void inject_preempt_context(struct work_struct *work)
>-{
>-	struct guc_preempt_work *preempt_work =
>-		container_of(work, typeof(*preempt_work), work);
>-	struct intel_engine_cs *engine = preempt_work->engine;
>-	struct intel_guc *guc = container_of(preempt_work, typeof(*guc),
>-					     preempt_work[engine->id]);
>-	struct intel_guc_client *client = guc->preempt_client;
>-	struct guc_stage_desc *stage_desc = __get_stage_desc(client);
>-	struct intel_context *ce = engine->preempt_context;
>-	u32 data[7];
>-
>-	if (!ce->ring->emit) { /* recreate upon load/resume */
>-		u32 addr = intel_hws_preempt_done_address(engine);
>-		u32 *cs;
>-
>-		cs = ce->ring->vaddr;
>-		if (engine->class == RENDER_CLASS) {
>-			cs = gen8_emit_ggtt_write_rcs(cs,
>-						      GUC_PREEMPT_FINISHED,
>-						      addr,
>-						      PIPE_CONTROL_CS_STALL);
>-		} else {
>-			cs = gen8_emit_ggtt_write(cs,
>-						  GUC_PREEMPT_FINISHED,
>-						  addr,
>-						  0);
>-			*cs++ = MI_NOOP;
>-			*cs++ = MI_NOOP;
>-		}
>-		*cs++ = MI_USER_INTERRUPT;
>-		*cs++ = MI_NOOP;
>-
>-		ce->ring->emit = GUC_PREEMPT_BREADCRUMB_BYTES;
>-		GEM_BUG_ON((void *)cs - ce->ring->vaddr != ce->ring->emit);
>-
>-		flush_ggtt_writes(ce->ring->vma);
>-	}
>-
>-	spin_lock_irq(&client->wq_lock);
>-	guc_wq_item_append(client, engine->guc_id, lower_32_bits(ce->lrc_desc),
>-			   GUC_PREEMPT_BREADCRUMB_BYTES / sizeof(u64), 0);
>-	spin_unlock_irq(&client->wq_lock);
>-
>-	/*
>-	 * If GuC firmware performs an engine reset while that engine had
>-	 * a preemption pending, it will set the terminated attribute bit
>-	 * on our preemption stage descriptor. GuC firmware retains all
>-	 * pending work items for a high-priority GuC client, unlike the
>-	 * normal-priority GuC client where work items are dropped. It
>-	 * wants to make sure the preempt-to-idle work doesn't run when
>-	 * scheduling resumes, and uses this bit to inform its scheduler
>-	 * and presumably us as well. Our job is to clear it for the next
>-	 * preemption after reset, otherwise that and future preemptions
>-	 * will never complete. We'll just clear it every time.
>-	 */
>-	stage_desc->attribute &= ~GUC_STAGE_DESC_ATTR_TERMINATED;
>-
>-	data[0] = INTEL_GUC_ACTION_REQUEST_PREEMPTION;
>-	data[1] = client->stage_id;
>-	data[2] = INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q |
>-		  INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q;
>-	data[3] = engine->guc_id;
>-	data[4] = guc->execbuf_client->priority;
>-	data[5] = guc->execbuf_client->stage_id;
>-	data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
>-
>-	if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {
>-		execlists_clear_active(&engine->execlists,
>-				       EXECLISTS_ACTIVE_PREEMPT);
>-		tasklet_schedule(&engine->execlists.tasklet);
>-	}
>-
>-	(void)I915_SELFTEST_ONLY(engine->execlists.preempt_hang.count++);
>-}
>-
>-/*
>- * We're using user interrupt and HWSP value to mark that preemption has
>- * finished and GPU is idle. Normally, we could unwind and continue similar to
>- * execlists submission path. Unfortunately, with GuC we also need to wait for
>- * it to finish its own postprocessing, before attempting to submit. Otherwise
>- * GuC may silently ignore our submissions, and thus we risk losing request at
>- * best, executing out-of-order and causing kernel panic at worst.
>- */
>-#define GUC_PREEMPT_POSTPROCESS_DELAY_MS 10
>-static void wait_for_guc_preempt_report(struct intel_engine_cs *engine)
>-{
>-	struct intel_guc *guc = &engine->i915->guc;
>-	struct guc_shared_ctx_data *data = guc->shared_data_vaddr;
>-	struct guc_ctx_report *report =
>-		&data->preempt_ctx_report[engine->guc_id];
>-
>-	if (wait_for_atomic(report->report_return_status ==
>-			    INTEL_GUC_REPORT_STATUS_COMPLETE,
>-			    GUC_PREEMPT_POSTPROCESS_DELAY_MS))
>-		DRM_ERROR("Timed out waiting for GuC preemption report\n");
>-	/*
>-	 * GuC is expecting that we're also going to clear the affected context
>-	 * counter, let's also reset the return status to not depend on GuC
>-	 * resetting it after recieving another preempt action
>-	 */
>-	report->affected_count = 0;
>-	report->report_return_status = INTEL_GUC_REPORT_STATUS_UNKNOWN;
>-}
>-
>-static void complete_preempt_context(struct intel_engine_cs *engine)
>-{
>-	struct intel_engine_execlists *execlists = &engine->execlists;
>-
>-	GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
>-
>-	if (inject_preempt_hang(execlists))
>-		return;
>-
>-	execlists_cancel_port_requests(execlists);
>-	execlists_unwind_incomplete_requests(execlists);
>-
>-	wait_for_guc_preempt_report(engine);
>-	intel_write_status_page(engine, I915_GEM_HWS_PREEMPT, 0);
>-}
>-
>-/**
>- * guc_submit() - Submit commands through GuC
>- * @engine: engine associated with the commands
>- *
>- * The only error here arises if the doorbell hardware isn't functioning
>- * as expected, which really shouln't happen.
>- */
>-static void guc_submit(struct intel_engine_cs *engine)
>-{
>-	struct intel_guc *guc = &engine->i915->guc;
>-	struct intel_engine_execlists * const execlists = &engine->execlists;
>-	struct execlist_port *port = execlists->port;
>-	unsigned int n;
>-
>-	for (n = 0; n < execlists_num_ports(execlists); n++) {
>-		struct i915_request *rq;
>-		unsigned int count;
>-
>-		rq = port_unpack(&port[n], &count);
>-		if (rq && count == 0) {
>-			port_set(&port[n], port_pack(rq, ++count));
>-
>-			flush_ggtt_writes(rq->ring->vma);
>-
>-			guc_add_request(guc, rq);
>-		}
>-	}
>-}
>-
>-static void port_assign(struct execlist_port *port, struct i915_request *rq)
>-{
>-	GEM_BUG_ON(port_isset(port));
>-
>-	port_set(port, i915_request_get(rq));
>-}
>-
>-static inline int rq_prio(const struct i915_request *rq)
>-{
>-	return rq->sched.attr.priority;
>-}
>-
>-static inline int port_prio(const struct execlist_port *port)
>-{
>-	return rq_prio(port_request(port)) | __NO_PREEMPTION;
>-}
>-
>-static bool __guc_dequeue(struct intel_engine_cs *engine)
>-{
>-	struct intel_engine_execlists * const execlists = &engine->execlists;
>-	struct execlist_port *port = execlists->port;
>-	struct i915_request *last = NULL;
>-	const struct execlist_port * const last_port =
>-		&execlists->port[execlists->port_mask];
>-	bool submit = false;
>-	struct rb_node *rb;
>-
>-	lockdep_assert_held(&engine->active.lock);
>-
>-	if (port_isset(port)) {
>-		if (intel_engine_has_preemption(engine)) {
>-			struct guc_preempt_work *preempt_work =
>-				&engine->i915->guc.preempt_work[engine->id];
>-			int prio = execlists->queue_priority_hint;
>-
>-			if (i915_scheduler_need_preempt(prio,
>-							port_prio(port))) {
>-				execlists_set_active(execlists,
>-						     EXECLISTS_ACTIVE_PREEMPT);
>-				queue_work(engine->i915->guc.preempt_wq,
>-					   &preempt_work->work);
>-				return false;
>-			}
>-		}
>-
>-		port++;
>-		if (port_isset(port))
>-			return false;
>-	}
>-	GEM_BUG_ON(port_isset(port));
>-
>-	while ((rb = rb_first_cached(&execlists->queue))) {
>-		struct i915_priolist *p = to_priolist(rb);
>-		struct i915_request *rq, *rn;
>-		int i;
>-
>-		priolist_for_each_request_consume(rq, rn, p, i) {
>-			if (last && rq->hw_context != last->hw_context) {
>-				if (port == last_port)
>-					goto done;
>-
>-				if (submit)
>-					port_assign(port, last);
>-				port++;
>-			}
>-
>-			list_del_init(&rq->sched.link);
>-
>-			__i915_request_submit(rq);
>-			trace_i915_request_in(rq, port_index(port, execlists));
>-
>-			last = rq;
>-			submit = true;
>-		}
>-
>-		rb_erase_cached(&p->node, &execlists->queue);
>-		i915_priolist_free(p);
>-	}
>-done:
>-	execlists->queue_priority_hint =
>-		rb ? to_priolist(rb)->priority : INT_MIN;
>-	if (submit)
>-		port_assign(port, last);
>-	if (last)
>-		execlists_user_begin(execlists, execlists->port);
>-
>-	/* We must always keep the beast fed if we have work piled up */
>-	GEM_BUG_ON(port_isset(execlists->port) &&
>-		   !execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
>-	GEM_BUG_ON(rb_first_cached(&execlists->queue) &&
>-		   !port_isset(execlists->port));
>-
>-	return submit;
>-}
>-
>-static void guc_dequeue(struct intel_engine_cs *engine)
>-{
>-	if (__guc_dequeue(engine))
>-		guc_submit(engine);
>-}
>-
>-static void guc_submission_tasklet(unsigned long data)
>-{
>-	struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
>-	struct intel_engine_execlists * const execlists = &engine->execlists;
>-	struct execlist_port *port = execlists->port;
>-	struct i915_request *rq;
>-	unsigned long flags;
>-
>-	spin_lock_irqsave(&engine->active.lock, flags);
>-
>-	rq = port_request(port);
>-	while (rq && i915_request_completed(rq)) {
>-		trace_i915_request_out(rq);
>-		i915_request_put(rq);
>-
>-		port = execlists_port_complete(execlists, port);
>-		if (port_isset(port)) {
>-			execlists_user_begin(execlists, port);
>-			rq = port_request(port);
>-		} else {
>-			execlists_user_end(execlists);
>-			rq = NULL;
>-		}
>-	}
>-
>-	if (execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT) &&
>-	    intel_read_status_page(engine, I915_GEM_HWS_PREEMPT) ==
>-	    GUC_PREEMPT_FINISHED)
>-		complete_preempt_context(engine);
>-
>-	if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT))
>-		guc_dequeue(engine);
>-
>-	spin_unlock_irqrestore(&engine->active.lock, flags);
>-}
>-
>-static void guc_reset_prepare(struct intel_engine_cs *engine)
>-{
>-	struct intel_engine_execlists * const execlists = &engine->execlists;
>-
>-	GEM_TRACE("%s\n", engine->name);
>-
>-	/*
>-	 * Prevent request submission to the hardware until we have
>-	 * completed the reset in i915_gem_reset_finish(). If a request
>-	 * is completed by one engine, it may then queue a request
>-	 * to a second via its execlists->tasklet *just* as we are
>-	 * calling engine->init_hw() and also writing the ELSP.
>-	 * Turning off the execlists->tasklet until the reset is over
>-	 * prevents the race.
>-	 */
>-	__tasklet_disable_sync_once(&execlists->tasklet);
>-
>-	/*
>-	 * We're using worker to queue preemption requests from the tasklet in
>-	 * GuC submission mode.
>-	 * Even though tasklet was disabled, we may still have a worker queued.
>-	 * Let's make sure that all workers scheduled before disabling the
>-	 * tasklet are completed before continuing with the reset.
>-	 */
>-	if (engine->i915->guc.preempt_wq)
>-		flush_workqueue(engine->i915->guc.preempt_wq);
>-}
>-
>-static void guc_reset(struct intel_engine_cs *engine, bool stalled)
>-{
>-	struct intel_engine_execlists * const execlists = &engine->execlists;
>-	struct i915_request *rq;
>-	unsigned long flags;
>-
>-	spin_lock_irqsave(&engine->active.lock, flags);
>-
>-	execlists_cancel_port_requests(execlists);
>-
>-	/* Push back any incomplete requests for replay after the reset. */
>-	rq = execlists_unwind_incomplete_requests(execlists);
>-	if (!rq)
>-		goto out_unlock;
>-
>-	if (!i915_request_started(rq))
>-		stalled = false;
>-
>-	i915_reset_request(rq, stalled);
>-	intel_lr_context_reset(engine, rq->hw_context, rq->head, stalled);
>-
>-out_unlock:
>-	spin_unlock_irqrestore(&engine->active.lock, flags);
>-}
>-
>-static void guc_cancel_requests(struct intel_engine_cs *engine)
>-{
>-	struct intel_engine_execlists * const execlists = &engine->execlists;
>-	struct i915_request *rq, *rn;
>-	struct rb_node *rb;
>-	unsigned long flags;
>-
>-	GEM_TRACE("%s\n", engine->name);
>-
>-	/*
>-	 * Before we call engine->cancel_requests(), we should have exclusive
>-	 * access to the submission state. This is arranged for us by the
>-	 * caller disabling the interrupt generation, the tasklet and other
>-	 * threads that may then access the same state, giving us a free hand
>-	 * to reset state. However, we still need to let lockdep be aware that
>-	 * we know this state may be accessed in hardirq context, so we
>-	 * disable the irq around this manipulation and we want to keep
>-	 * the spinlock focused on its duties and not accidentally conflate
>-	 * coverage to the submission's irq state. (Similarly, although we
>-	 * shouldn't need to disable irq around the manipulation of the
>-	 * submission's irq state, we also wish to remind ourselves that
>-	 * it is irq state.)
>-	 */
>-	spin_lock_irqsave(&engine->active.lock, flags);
>-
>-	/* Cancel the requests on the HW and clear the ELSP tracker. */
>-	execlists_cancel_port_requests(execlists);
>-
>-	/* Mark all executing requests as skipped. */
>-	list_for_each_entry(rq, &engine->active.requests, sched.link) {
>-		if (!i915_request_signaled(rq))
>-			dma_fence_set_error(&rq->fence, -EIO);
>-
>-		i915_request_mark_complete(rq);
>-	}
>-
>-	/* Flush the queued requests to the timeline list (for retiring). */
>-	while ((rb = rb_first_cached(&execlists->queue))) {
>-		struct i915_priolist *p = to_priolist(rb);
>-		int i;
>-
>-		priolist_for_each_request_consume(rq, rn, p, i) {
>-			list_del_init(&rq->sched.link);
>-			__i915_request_submit(rq);
>-			dma_fence_set_error(&rq->fence, -EIO);
>-			i915_request_mark_complete(rq);
>-		}
>-
>-		rb_erase_cached(&p->node, &execlists->queue);
>-		i915_priolist_free(p);
>-	}
>-
>-	/* Remaining _unready_ requests will be nop'ed when submitted */
>-
>-	execlists->queue_priority_hint = INT_MIN;
>-	execlists->queue = RB_ROOT_CACHED;
>-	GEM_BUG_ON(port_isset(execlists->port));
>-
>-	spin_unlock_irqrestore(&engine->active.lock, flags);
>-}
>-
>-static void guc_reset_finish(struct intel_engine_cs *engine)
>-{
>-	struct intel_engine_execlists * const execlists = &engine->execlists;
>-
>-	if (__tasklet_enable(&execlists->tasklet))
>-		/* And kick in case we missed a new request submission. */
>-		tasklet_hi_schedule(&execlists->tasklet);
>-
>-	GEM_TRACE("%s: depth->%d\n", engine->name,
>-		  atomic_read(&execlists->tasklet.count));
>-}
>-
>-/*
>- * Everything below here is concerned with setup & teardown, and is
>- * therefore not part of the somewhat time-critical batch-submission
>- * path of guc_submit() above.
>- */
>-
>-/* Check that a doorbell register is in the expected state */
>-static bool doorbell_ok(struct intel_guc *guc, u16 db_id)
>-{
>-	bool valid;
>-
>-	GEM_BUG_ON(db_id >= GUC_NUM_DOORBELLS);
>-
>-	valid = __doorbell_valid(guc, db_id);
>-
>-	if (test_bit(db_id, guc->doorbell_bitmap) == valid)
>-		return true;
>-
>-	DRM_DEBUG_DRIVER("Doorbell %u has unexpected state: valid=%s\n",
>-			 db_id, yesno(valid));
>-
>-	return false;
>-}
>-
>-static bool guc_verify_doorbells(struct intel_guc *guc)
>-{
>-	bool doorbells_ok = true;
>-	u16 db_id;
>-
>-	for (db_id = 0; db_id < GUC_NUM_DOORBELLS; ++db_id)
>-		if (!doorbell_ok(guc, db_id))
>-			doorbells_ok = false;
>-
>-	return doorbells_ok;
>-}
>-
>-/**
>- * guc_client_alloc() - Allocate an intel_guc_client
>- * @dev_priv:	driver private data structure
>- * @engines:	The set of engines to enable for this client
>- * @priority:	four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
>- *		The kernel client to replace ExecList submission is created with
>- *		NORMAL priority. Priority of a client for scheduler can be HIGH,
>- *		while a preemption context can use CRITICAL.
>- * @ctx:	the context that owns the client (we use the default render
>- *		context)
>- *
>- * Return:	An intel_guc_client object if success, else NULL.
>- */
>-static struct intel_guc_client *
>-guc_client_alloc(struct drm_i915_private *dev_priv,
>-		 u32 engines,
>-		 u32 priority,
>-		 struct i915_gem_context *ctx)
>-{
>-	struct intel_guc_client *client;
>-	struct intel_guc *guc = &dev_priv->guc;
>-	struct i915_vma *vma;
>-	void *vaddr;
>-	int ret;
>-
>-	client = kzalloc(sizeof(*client), GFP_KERNEL);
>-	if (!client)
>-		return ERR_PTR(-ENOMEM);
>-
>-	client->guc = guc;
>-	client->owner = ctx;
>-	client->engines = engines;
>-	client->priority = priority;
>-	client->doorbell_id = GUC_DOORBELL_INVALID;
>-	spin_lock_init(&client->wq_lock);
>-
>-	ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS,
>-			     GFP_KERNEL);
>-	if (ret < 0)
>-		goto err_client;
>-
>-	client->stage_id = ret;
>-
>-	/* The first page is doorbell/proc_desc. Two followed pages are wq. */
>-	vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE);
>-	if (IS_ERR(vma)) {
>-		ret = PTR_ERR(vma);
>-		goto err_id;
>-	}
>-
>-	/* We'll keep just the first (doorbell/proc) page permanently kmap'd. */
>-	client->vma = vma;
>-
>-	vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
>-	if (IS_ERR(vaddr)) {
>-		ret = PTR_ERR(vaddr);
>-		goto err_vma;
>-	}
>-	client->vaddr = vaddr;
>-
>-	ret = reserve_doorbell(client);
>-	if (ret)
>-		goto err_vaddr;
>-
>-	client->doorbell_offset = __select_cacheline(guc);
>-
>-	/*
>-	 * Since the doorbell only requires a single cacheline, we can save
>-	 * space by putting the application process descriptor in the same
>-	 * page. Use the half of the page that doesn't include the doorbell.
>-	 */
>-	if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
>-		client->proc_desc_offset = 0;
>-	else
>-		client->proc_desc_offset = (GUC_DB_SIZE / 2);
>-
>-	DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: stage_id %u\n",
>-			 priority, client, client->engines, client->stage_id);
>-	DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%lx\n",
>-			 client->doorbell_id, client->doorbell_offset);
>-
>-	return client;
>-
>-err_vaddr:
>-	i915_gem_object_unpin_map(client->vma->obj);
>-err_vma:
>-	i915_vma_unpin_and_release(&client->vma, 0);
>-err_id:
>-	ida_simple_remove(&guc->stage_ids, client->stage_id);
>-err_client:
>-	kfree(client);
>-	return ERR_PTR(ret);
>-}
>-
>-static void guc_client_free(struct intel_guc_client *client)
>-{
>-	unreserve_doorbell(client);
>-	i915_vma_unpin_and_release(&client->vma, I915_VMA_RELEASE_MAP);
>-	ida_simple_remove(&client->guc->stage_ids, client->stage_id);
>-	kfree(client);
>-}
>-
>-static inline bool ctx_save_restore_disabled(struct intel_context *ce)
>-{
>-	u32 sr = ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1];
>-
>-#define SR_DISABLED \
>-	_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | \
>-			   CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT)
>-
>-	return (sr & SR_DISABLED) == SR_DISABLED;
>-
>-#undef SR_DISABLED
>-}
>-
>-static int guc_clients_create(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	struct intel_guc_client *client;
>-
>-	GEM_BUG_ON(guc->execbuf_client);
>-	GEM_BUG_ON(guc->preempt_client);
>-
>-	client = guc_client_alloc(dev_priv,
>-				  INTEL_INFO(dev_priv)->engine_mask,
>-				  GUC_CLIENT_PRIORITY_KMD_NORMAL,
>-				  dev_priv->kernel_context);
>-	if (IS_ERR(client)) {
>-		DRM_ERROR("Failed to create GuC client for submission!\n");
>-		return PTR_ERR(client);
>-	}
>-	guc->execbuf_client = client;
>-
>-	if (dev_priv->preempt_context) {
>-		client = guc_client_alloc(dev_priv,
>-					  INTEL_INFO(dev_priv)->engine_mask,
>-					  GUC_CLIENT_PRIORITY_KMD_HIGH,
>-					  dev_priv->preempt_context);
>-		if (IS_ERR(client)) {
>-			DRM_ERROR("Failed to create GuC client for preemption!\n");
>-			guc_client_free(guc->execbuf_client);
>-			guc->execbuf_client = NULL;
>-			return PTR_ERR(client);
>-		}
>-		guc->preempt_client = client;
>-	}
>-
>-	return 0;
>-}
>-
>-static void guc_clients_destroy(struct intel_guc *guc)
>-{
>-	struct intel_guc_client *client;
>-
>-	client = fetch_and_zero(&guc->preempt_client);
>-	if (client)
>-		guc_client_free(client);
>-
>-	client = fetch_and_zero(&guc->execbuf_client);
>-	if (client)
>-		guc_client_free(client);
>-}
>-
>-static int __guc_client_enable(struct intel_guc_client *client)
>-{
>-	int ret;
>-
>-	guc_proc_desc_init(client);
>-	guc_stage_desc_init(client);
>-
>-	ret = create_doorbell(client);
>-	if (ret)
>-		goto fail;
>-
>-	return 0;
>-
>-fail:
>-	guc_stage_desc_fini(client);
>-	guc_proc_desc_fini(client);
>-	return ret;
>-}
>-
>-static void __guc_client_disable(struct intel_guc_client *client)
>-{
>-	/*
>-	 * By the time we're here, GuC may have already been reset. if that is
>-	 * the case, instead of trying (in vain) to communicate with it, let's
>-	 * just cleanup the doorbell HW and our internal state.
>-	 */
>-	if (intel_guc_is_loaded(client->guc))
>-		destroy_doorbell(client);
>-	else
>-		__fini_doorbell(client);
>-
>-	guc_stage_desc_fini(client);
>-	guc_proc_desc_fini(client);
>-}
>-
>-static int guc_clients_enable(struct intel_guc *guc)
>-{
>-	int ret;
>-
>-	ret = __guc_client_enable(guc->execbuf_client);
>-	if (ret)
>-		return ret;
>-
>-	if (guc->preempt_client) {
>-		ret = __guc_client_enable(guc->preempt_client);
>-		if (ret) {
>-			__guc_client_disable(guc->execbuf_client);
>-			return ret;
>-		}
>-	}
>-
>-	return 0;
>-}
>-
>-static void guc_clients_disable(struct intel_guc *guc)
>-{
>-	if (guc->preempt_client)
>-		__guc_client_disable(guc->preempt_client);
>-
>-	if (guc->execbuf_client)
>-		__guc_client_disable(guc->execbuf_client);
>-}
>-
>-/*
>- * Set up the memory resources to be shared with the GuC (via the GGTT)
>- * at firmware loading time.
>- */
>-int intel_guc_submission_init(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	struct intel_engine_cs *engine;
>-	enum intel_engine_id id;
>-	int ret;
>-
>-	if (guc->stage_desc_pool)
>-		return 0;
>-
>-	ret = guc_stage_desc_pool_create(guc);
>-	if (ret)
>-		return ret;
>-	/*
>-	 * Keep static analysers happy, let them know that we allocated the
>-	 * vma after testing that it didn't exist earlier.
>-	 */
>-	GEM_BUG_ON(!guc->stage_desc_pool);
>-
>-	WARN_ON(!guc_verify_doorbells(guc));
>-	ret = guc_clients_create(guc);
>-	if (ret)
>-		goto err_pool;
>-
>-	for_each_engine(engine, dev_priv, id) {
>-		guc->preempt_work[id].engine = engine;
>-		INIT_WORK(&guc->preempt_work[id].work, inject_preempt_context);
>-	}
>-
>-	return 0;
>-
>-err_pool:
>-	guc_stage_desc_pool_destroy(guc);
>-	return ret;
>-}
>-
>-void intel_guc_submission_fini(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	struct intel_engine_cs *engine;
>-	enum intel_engine_id id;
>-
>-	for_each_engine(engine, dev_priv, id)
>-		cancel_work_sync(&guc->preempt_work[id].work);
>-
>-	guc_clients_destroy(guc);
>-	WARN_ON(!guc_verify_doorbells(guc));
>-
>-	if (guc->stage_desc_pool)
>-		guc_stage_desc_pool_destroy(guc);
>-}
>-
>-static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
>-{
>-	struct intel_rps *rps = &dev_priv->gt_pm.rps;
>-	struct intel_engine_cs *engine;
>-	enum intel_engine_id id;
>-	int irqs;
>-
>-	/* tell all command streamers to forward interrupts (but not vblank)
>-	 * to GuC
>-	 */
>-	irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
>-	for_each_engine(engine, dev_priv, id)
>-		ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
>-
>-	/* route USER_INTERRUPT to Host, all others are sent to GuC. */
>-	irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
>-	       GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
>-	/* These three registers have the same bit definitions */
>-	I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
>-	I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
>-	I915_WRITE(GUC_WD_VECS_IER, ~irqs);
>-
>-	/*
>-	 * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
>-	 * (unmasked) PM interrupts to the GuC. All other bits of this
>-	 * register *disable* generation of a specific interrupt.
>-	 *
>-	 * 'pm_intrmsk_mbz' indicates bits that are NOT to be set when
>-	 * writing to the PM interrupt mask register, i.e. interrupts
>-	 * that must not be disabled.
>-	 *
>-	 * If the GuC is handling these interrupts, then we must not let
>-	 * the PM code disable ANY interrupt that the GuC is expecting.
>-	 * So for each ENABLED (0) bit in this register, we must SET the
>-	 * bit in pm_intrmsk_mbz so that it's left enabled for the GuC.
>-	 * GuC needs ARAT expired interrupt unmasked hence it is set in
>-	 * pm_intrmsk_mbz.
>-	 *
>-	 * Here we CLEAR REDIRECT_TO_GUC bit in pm_intrmsk_mbz, which will
>-	 * result in the register bit being left SET!
>-	 */
>-	rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK;
>-	rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
>-}
>-
>-static void guc_interrupts_release(struct drm_i915_private *dev_priv)
>-{
>-	struct intel_rps *rps = &dev_priv->gt_pm.rps;
>-	struct intel_engine_cs *engine;
>-	enum intel_engine_id id;
>-	int irqs;
>-
>-	/*
>-	 * tell all command streamers NOT to forward interrupts or vblank
>-	 * to GuC.
>-	 */
>-	irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
>-	irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
>-	for_each_engine(engine, dev_priv, id)
>-		ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
>-
>-	/* route all GT interrupts to the host */
>-	I915_WRITE(GUC_BCS_RCS_IER, 0);
>-	I915_WRITE(GUC_VCS2_VCS1_IER, 0);
>-	I915_WRITE(GUC_WD_VECS_IER, 0);
>-
>-	rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
>-	rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
>-}
>-
>-static void guc_submission_park(struct intel_engine_cs *engine)
>-{
>-	intel_engine_park(engine);
>-	intel_engine_unpin_breadcrumbs_irq(engine);
>-	engine->flags &= ~I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
>-}
>-
>-static void guc_submission_unpark(struct intel_engine_cs *engine)
>-{
>-	engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
>-	intel_engine_pin_breadcrumbs_irq(engine);
>-}
>-
>-static void guc_set_default_submission(struct intel_engine_cs *engine)
>-{
>-	/*
>-	 * We inherit a bunch of functions from execlists that we'd like
>-	 * to keep using:
>-	 *
>-	 *    engine->submit_request = execlists_submit_request;
>-	 *    engine->cancel_requests = execlists_cancel_requests;
>-	 *    engine->schedule = execlists_schedule;
>-	 *
>-	 * But we need to override the actual submission backend in order
>-	 * to talk to the GuC.
>-	 */
>-	intel_execlists_set_default_submission(engine);
>-
>-	engine->execlists.tasklet.func = guc_submission_tasklet;
>-
>-	engine->park = guc_submission_park;
>-	engine->unpark = guc_submission_unpark;
>-
>-	engine->reset.prepare = guc_reset_prepare;
>-	engine->reset.reset = guc_reset;
>-	engine->reset.finish = guc_reset_finish;
>-
>-	engine->cancel_requests = guc_cancel_requests;
>-
>-	engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
>-}
>-
>-int intel_guc_submission_enable(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-	struct intel_engine_cs *engine;
>-	enum intel_engine_id id;
>-	int err;
>-
>-	/*
>-	 * We're using GuC work items for submitting work through GuC. Since
>-	 * we're coalescing multiple requests from a single context into a
>-	 * single work item prior to assigning it to execlist_port, we can
>-	 * never have more work items than the total number of ports (for all
>-	 * engines). The GuC firmware is controlling the HEAD of work queue,
>-	 * and it is guaranteed that it will remove the work item from the
>-	 * queue before our request is completed.
>-	 */
>-	BUILD_BUG_ON(ARRAY_SIZE(engine->execlists.port) *
>-		     sizeof(struct guc_wq_item) *
>-		     I915_NUM_ENGINES > GUC_WQ_SIZE);
>-
>-	GEM_BUG_ON(!guc->execbuf_client);
>-
>-	err = guc_clients_enable(guc);
>-	if (err)
>-		return err;
>-
>-	/* Take over from manual control of ELSP (execlists) */
>-	guc_interrupts_capture(dev_priv);
>-
>-	for_each_engine(engine, dev_priv, id) {
>-		engine->set_default_submission = guc_set_default_submission;
>-		engine->set_default_submission(engine);
>-	}
>-
>-	return 0;
>-}
>-
>-void intel_guc_submission_disable(struct intel_guc *guc)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(guc);
>-
>-	GEM_BUG_ON(dev_priv->gt.awake); /* GT should be parked first */
>-
>-	guc_interrupts_release(dev_priv);
>-	guc_clients_disable(guc);
>-}
>-
>-#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
>-#include "selftests/intel_guc.c"
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_submission.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_submission.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_guc_submission.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_guc_submission.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,89 +0,0 @@
>-/*
>- * Copyright Â© 2014-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#ifndef _INTEL_GUC_SUBMISSION_H_
>-#define _INTEL_GUC_SUBMISSION_H_
>-
>-#include <linux/spinlock.h>
>-
>-#include "gt/intel_engine_types.h"
>-
>-#include "i915_gem.h"
>-#include "i915_selftest.h"
>-
>-struct drm_i915_private;
>-
>-/*
>- * This structure primarily describes the GEM object shared with the GuC.
>- * The specs sometimes refer to this object as a "GuC context", but we use
>- * the term "client" to avoid confusion with hardware contexts. This
>- * GEM object is held for the entire lifetime of our interaction with
>- * the GuC, being allocated before the GuC is loaded with its firmware.
>- * Because there's no way to update the address used by the GuC after
>- * initialisation, the shared object must stay pinned into the GGTT as
>- * long as the GuC is in use. We also keep the first page (only) mapped
>- * into kernel address space, as it includes shared data that must be
>- * updated on every request submission.
>- *
>- * The single GEM object described here is actually made up of several
>- * separate areas, as far as the GuC is concerned. The first page (kept
>- * kmap'd) includes the "process descriptor" which holds sequence data for
>- * the doorbell, and one cacheline which actually *is* the doorbell; a
>- * write to this will "ring the doorbell" (i.e. send an interrupt to the
>- * GuC). The subsequent  pages of the client object constitute the work
>- * queue (a circular array of work items), again described in the process
>- * descriptor. Work queue pages are mapped momentarily as required.
>- */
>-struct intel_guc_client {
>-	struct i915_vma *vma;
>-	void *vaddr;
>-	struct i915_gem_context *owner;
>-	struct intel_guc *guc;
>-
>-	/* bitmap of (host) engine ids */
>-	u32 engines;
>-	u32 priority;
>-	u32 stage_id;
>-	u32 proc_desc_offset;
>-
>-	u16 doorbell_id;
>-	unsigned long doorbell_offset;
>-
>-	/* Protects GuC client's WQ access */
>-	spinlock_t wq_lock;
>-	/* Per-engine counts of GuC submissions */
>-	u64 submissions[I915_NUM_ENGINES];
>-
>-	/* For testing purposes, use nop WQ items instead of real ones */
>-	I915_SELFTEST_DECLARE(bool use_nop_wqi);
>-};
>-
>-int intel_guc_submission_init(struct intel_guc *guc);
>-int intel_guc_submission_enable(struct intel_guc *guc);
>-void intel_guc_submission_disable(struct intel_guc *guc);
>-void intel_guc_submission_fini(struct intel_guc *guc);
>-int intel_guc_preempt_work_create(struct intel_guc *guc);
>-void intel_guc_preempt_work_destroy(struct intel_guc *guc);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_gvt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_gvt.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_gvt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_gvt.c	2019-08-31 15:01:12.038736184 -0500
>@@ -95,7 +95,7 @@
> {
> 	int ret;
> 
>-	if (i915_inject_load_failure())
>+	if (i915_inject_probe_failure())
> 		return -ENODEV;
> 
> 	if (!i915_modparams.enable_gvt) {
>@@ -122,13 +122,14 @@
> }
> 
> /**
>- * intel_gvt_cleanup - cleanup GVT components when i915 driver is unloading
>+ * intel_gvt_driver_remove - cleanup GVT components when i915 driver is
>+ *			     unbinding
>  * @dev_priv: drm i915 private *
>  *
>  * This function is called at the i915 driver unloading stage, to shutdown
>  * GVT components and release the related resources.
>  */
>-void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
>+void intel_gvt_driver_remove(struct drm_i915_private *dev_priv)
> {
> 	if (!intel_gvt_active(dev_priv))
> 		return;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_gvt.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_gvt.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_gvt.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_gvt.h	2019-08-31 15:01:12.038736184 -0500
>@@ -24,11 +24,11 @@
> #ifndef _INTEL_GVT_H_
> #define _INTEL_GVT_H_
> 
>-struct intel_gvt;
>+struct drm_i915_private;
> 
> #ifdef CONFIG_DRM_I915_GVT
> int intel_gvt_init(struct drm_i915_private *dev_priv);
>-void intel_gvt_cleanup(struct drm_i915_private *dev_priv);
>+void intel_gvt_driver_remove(struct drm_i915_private *dev_priv);
> int intel_gvt_init_device(struct drm_i915_private *dev_priv);
> void intel_gvt_clean_device(struct drm_i915_private *dev_priv);
> int intel_gvt_init_host(void);
>@@ -38,7 +38,8 @@
> {
> 	return 0;
> }
>-static inline void intel_gvt_cleanup(struct drm_i915_private *dev_priv)
>+
>+static inline void intel_gvt_driver_remove(struct drm_i915_private *dev_priv)
> {
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_huc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_huc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_huc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_huc.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,182 +0,0 @@
>-/*
>- * Copyright Â© 2016-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#include <linux/types.h>
>-
>-#include "intel_huc.h"
>-#include "i915_drv.h"
>-
>-void intel_huc_init_early(struct intel_huc *huc)
>-{
>-	struct drm_i915_private *i915 = huc_to_i915(huc);
>-
>-	intel_huc_fw_init_early(huc);
>-
>-	if (INTEL_GEN(i915) >= 11) {
>-		huc->status.reg = GEN11_HUC_KERNEL_LOAD_INFO;
>-		huc->status.mask = HUC_LOAD_SUCCESSFUL;
>-		huc->status.value = HUC_LOAD_SUCCESSFUL;
>-	} else {
>-		huc->status.reg = HUC_STATUS2;
>-		huc->status.mask = HUC_FW_VERIFIED;
>-		huc->status.value = HUC_FW_VERIFIED;
>-	}
>-}
>-
>-int intel_huc_init_misc(struct intel_huc *huc)
>-{
>-	struct drm_i915_private *i915 = huc_to_i915(huc);
>-
>-	intel_uc_fw_fetch(i915, &huc->fw);
>-	return 0;
>-}
>-
>-static int intel_huc_rsa_data_create(struct intel_huc *huc)
>-{
>-	struct drm_i915_private *i915 = huc_to_i915(huc);
>-	struct intel_guc *guc = &i915->guc;
>-	struct i915_vma *vma;
>-	void *vaddr;
>-
>-	/*
>-	 * HuC firmware will sit above GUC_GGTT_TOP and will not map
>-	 * through GTT. Unfortunately, this means GuC cannot perform
>-	 * the HuC auth. as the rsa offset now falls within the GuC
>-	 * inaccessible range. We resort to perma-pinning an additional
>-	 * vma within the accessible range that only contains the rsa
>-	 * signature. The GuC can use this extra pinning to perform
>-	 * the authentication since its GGTT offset will be GuC
>-	 * accessible.
>-	 */
>-	vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
>-	if (IS_ERR(vma))
>-		return PTR_ERR(vma);
>-
>-	vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
>-	if (IS_ERR(vaddr)) {
>-		i915_vma_unpin_and_release(&vma, 0);
>-		return PTR_ERR(vaddr);
>-	}
>-
>-	huc->rsa_data = vma;
>-	huc->rsa_data_vaddr = vaddr;
>-
>-	return 0;
>-}
>-
>-static void intel_huc_rsa_data_destroy(struct intel_huc *huc)
>-{
>-	i915_vma_unpin_and_release(&huc->rsa_data, I915_VMA_RELEASE_MAP);
>-}
>-
>-int intel_huc_init(struct intel_huc *huc)
>-{
>-	int err;
>-
>-	err = intel_huc_rsa_data_create(huc);
>-	if (err)
>-		return err;
>-
>-	return intel_uc_fw_init(&huc->fw);
>-}
>-
>-void intel_huc_fini(struct intel_huc *huc)
>-{
>-	intel_uc_fw_fini(&huc->fw);
>-	intel_huc_rsa_data_destroy(huc);
>-}
>-
>-/**
>- * intel_huc_auth() - Authenticate HuC uCode
>- * @huc: intel_huc structure
>- *
>- * Called after HuC and GuC firmware loading during intel_uc_init_hw().
>- *
>- * This function pins HuC firmware image object into GGTT.
>- * Then it invokes GuC action to authenticate passing the offset to RSA
>- * signature through intel_guc_auth_huc(). It then waits for 50ms for
>- * firmware verification ACK and unpins the object.
>- */
>-int intel_huc_auth(struct intel_huc *huc)
>-{
>-	struct drm_i915_private *i915 = huc_to_i915(huc);
>-	struct intel_guc *guc = &i915->guc;
>-	int ret;
>-
>-	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
>-		return -ENOEXEC;
>-
>-	ret = intel_guc_auth_huc(guc,
>-				 intel_guc_ggtt_offset(guc, huc->rsa_data));
>-	if (ret) {
>-		DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
>-		goto fail;
>-	}
>-
>-	/* Check authentication status, it should be done by now */
>-	ret = __intel_wait_for_register(&i915->uncore,
>-					huc->status.reg,
>-					huc->status.mask,
>-					huc->status.value,
>-					2, 50, NULL);
>-	if (ret) {
>-		DRM_ERROR("HuC: Firmware not verified %d\n", ret);
>-		goto fail;
>-	}
>-
>-	return 0;
>-
>-fail:
>-	huc->fw.load_status = INTEL_UC_FIRMWARE_FAIL;
>-
>-	DRM_ERROR("HuC: Authentication failed %d\n", ret);
>-	return ret;
>-}
>-
>-/**
>- * intel_huc_check_status() - check HuC status
>- * @huc: intel_huc structure
>- *
>- * This function reads status register to verify if HuC
>- * firmware was successfully loaded.
>- *
>- * Returns: 1 if HuC firmware is loaded and verified,
>- * 0 if HuC firmware is not loaded and -ENODEV if HuC
>- * is not present on this platform.
>- */
>-int intel_huc_check_status(struct intel_huc *huc)
>-{
>-	struct drm_i915_private *dev_priv = huc_to_i915(huc);
>-	intel_wakeref_t wakeref;
>-	bool status = false;
>-
>-	if (!HAS_HUC(dev_priv))
>-		return -ENODEV;
>-
>-	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
>-		status = (I915_READ(huc->status.reg) & huc->status.mask) ==
>-			  huc->status.value;
>-
>-	return status;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_huc_fw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_huc_fw.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_huc_fw.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_huc_fw.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,215 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2014-2018 Intel Corporation
>- */
>-
>-#include "intel_huc_fw.h"
>-#include "i915_drv.h"
>-
>-/**
>- * DOC: HuC Firmware
>- *
>- * Motivation:
>- * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
>- * Efficiency Video Coding) operations. Userspace can use the firmware
>- * capabilities by adding HuC specific commands to batch buffers.
>- *
>- * Implementation:
>- * The same firmware loader is used as the GuC. However, the actual
>- * loading to HW is deferred until GEM initialization is done.
>- *
>- * Note that HuC firmware loading must be done before GuC loading.
>- */
>-
>-#define BXT_HUC_FW_MAJOR 01
>-#define BXT_HUC_FW_MINOR 8
>-#define BXT_BLD_NUM 2893
>-
>-#define SKL_HUC_FW_MAJOR 01
>-#define SKL_HUC_FW_MINOR 07
>-#define SKL_BLD_NUM 1398
>-
>-#define KBL_HUC_FW_MAJOR 02
>-#define KBL_HUC_FW_MINOR 00
>-#define KBL_BLD_NUM 1810
>-
>-#define GLK_HUC_FW_MAJOR 03
>-#define GLK_HUC_FW_MINOR 01
>-#define GLK_BLD_NUM 2893
>-
>-#define ICL_HUC_FW_MAJOR 8
>-#define ICL_HUC_FW_MINOR 4
>-#define ICL_BLD_NUM 3238
>-
>-#define HUC_FW_PATH(platform, major, minor, bld_num) \
>-	"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
>-	__stringify(minor) "_" __stringify(bld_num) ".bin"
>-
>-#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
>-	SKL_HUC_FW_MINOR, SKL_BLD_NUM)
>-MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
>-
>-#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
>-	BXT_HUC_FW_MINOR, BXT_BLD_NUM)
>-MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
>-
>-#define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
>-	KBL_HUC_FW_MINOR, KBL_BLD_NUM)
>-MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
>-
>-#define I915_GLK_HUC_UCODE HUC_FW_PATH(glk, GLK_HUC_FW_MAJOR, \
>-	GLK_HUC_FW_MINOR, GLK_BLD_NUM)
>-MODULE_FIRMWARE(I915_GLK_HUC_UCODE);
>-
>-#define I915_ICL_HUC_UCODE HUC_FW_PATH(icl, ICL_HUC_FW_MAJOR, \
>-	ICL_HUC_FW_MINOR, ICL_BLD_NUM)
>-MODULE_FIRMWARE(I915_ICL_HUC_UCODE);
>-
>-static void huc_fw_select(struct intel_uc_fw *huc_fw)
>-{
>-	struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
>-	struct drm_i915_private *dev_priv = huc_to_i915(huc);
>-
>-	GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
>-
>-	if (!HAS_HUC(dev_priv))
>-		return;
>-
>-	if (i915_modparams.huc_firmware_path) {
>-		huc_fw->path = i915_modparams.huc_firmware_path;
>-		huc_fw->major_ver_wanted = 0;
>-		huc_fw->minor_ver_wanted = 0;
>-	} else if (IS_SKYLAKE(dev_priv)) {
>-		huc_fw->path = I915_SKL_HUC_UCODE;
>-		huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
>-		huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
>-	} else if (IS_BROXTON(dev_priv)) {
>-		huc_fw->path = I915_BXT_HUC_UCODE;
>-		huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
>-		huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
>-	} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
>-		huc_fw->path = I915_KBL_HUC_UCODE;
>-		huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
>-		huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
>-	} else if (IS_GEMINILAKE(dev_priv)) {
>-		huc_fw->path = I915_GLK_HUC_UCODE;
>-		huc_fw->major_ver_wanted = GLK_HUC_FW_MAJOR;
>-		huc_fw->minor_ver_wanted = GLK_HUC_FW_MINOR;
>-	} else if (IS_ICELAKE(dev_priv)) {
>-		huc_fw->path = I915_ICL_HUC_UCODE;
>-		huc_fw->major_ver_wanted = ICL_HUC_FW_MAJOR;
>-		huc_fw->minor_ver_wanted = ICL_HUC_FW_MINOR;
>-	}
>-}
>-
>-/**
>- * intel_huc_fw_init_early() - initializes HuC firmware struct
>- * @huc: intel_huc struct
>- *
>- * On platforms with HuC selects firmware for uploading
>- */
>-void intel_huc_fw_init_early(struct intel_huc *huc)
>-{
>-	struct intel_uc_fw *huc_fw = &huc->fw;
>-
>-	intel_uc_fw_init_early(huc_fw, INTEL_UC_FW_TYPE_HUC);
>-	huc_fw_select(huc_fw);
>-}
>-
>-static void huc_xfer_rsa(struct intel_huc *huc)
>-{
>-	struct intel_uc_fw *fw = &huc->fw;
>-	struct sg_table *pages = fw->obj->mm.pages;
>-
>-	/*
>-	 * HuC firmware image is outside GuC accessible range.
>-	 * Copy the RSA signature out of the image into
>-	 * the perma-pinned region set aside for it
>-	 */
>-	sg_pcopy_to_buffer(pages->sgl, pages->nents,
>-			   huc->rsa_data_vaddr, fw->rsa_size,
>-			   fw->rsa_offset);
>-}
>-
>-static int huc_xfer_ucode(struct intel_huc *huc)
>-{
>-	struct intel_uc_fw *huc_fw = &huc->fw;
>-	struct drm_i915_private *dev_priv = huc_to_i915(huc);
>-	struct intel_uncore *uncore = &dev_priv->uncore;
>-	unsigned long offset = 0;
>-	u32 size;
>-	int ret;
>-
>-	GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
>-
>-	intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>-
>-	/* Set the source address for the uCode */
>-	offset = intel_uc_fw_ggtt_offset(huc_fw) +
>-		 huc_fw->header_offset;
>-	intel_uncore_write(uncore, DMA_ADDR_0_LOW,
>-			   lower_32_bits(offset));
>-	intel_uncore_write(uncore, DMA_ADDR_0_HIGH,
>-			   upper_32_bits(offset) & 0xFFFF);
>-
>-	/*
>-	 * Hardware doesn't look at destination address for HuC. Set it to 0,
>-	 * but still program the correct address space.
>-	 */
>-	intel_uncore_write(uncore, DMA_ADDR_1_LOW, 0);
>-	intel_uncore_write(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
>-
>-	size = huc_fw->header_size + huc_fw->ucode_size;
>-	intel_uncore_write(uncore, DMA_COPY_SIZE, size);
>-
>-	/* Start the DMA */
>-	intel_uncore_write(uncore, DMA_CTRL,
>-			   _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
>-
>-	/* Wait for DMA to finish */
>-	ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100);
>-
>-	DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
>-
>-	/* Disable the bits once DMA is over */
>-	intel_uncore_write(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
>-
>-	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>-
>-	return ret;
>-}
>-
>-/**
>- * huc_fw_xfer() - DMA's the firmware
>- * @huc_fw: the firmware descriptor
>- *
>- * Transfer the firmware image to RAM for execution by the microcontroller.
>- *
>- * Return: 0 on success, non-zero on failure
>- */
>-static int huc_fw_xfer(struct intel_uc_fw *huc_fw)
>-{
>-	struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
>-
>-	huc_xfer_rsa(huc);
>-
>-	return huc_xfer_ucode(huc);
>-}
>-
>-/**
>- * intel_huc_fw_upload() - load HuC uCode to device
>- * @huc: intel_huc structure
>- *
>- * Called from intel_uc_init_hw() during driver load, resume from sleep and
>- * after a GPU reset. Note that HuC must be loaded before GuC.
>- *
>- * The firmware image should have already been fetched into memory, so only
>- * check that fetch succeeded, and then transfer the image to the h/w.
>- *
>- * Return:	non-zero code on error
>- */
>-int intel_huc_fw_upload(struct intel_huc *huc)
>-{
>-	return intel_uc_fw_upload(&huc->fw, huc_fw_xfer);
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_huc_fw.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_huc_fw.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_huc_fw.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_huc_fw.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2014-2018 Intel Corporation
>- */
>-
>-#ifndef _INTEL_HUC_FW_H_
>-#define _INTEL_HUC_FW_H_
>-
>-struct intel_huc;
>-
>-void intel_huc_fw_init_early(struct intel_huc *huc);
>-int intel_huc_fw_upload(struct intel_huc *huc);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_huc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_huc.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_huc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_huc.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,65 +0,0 @@
>-/*
>- * Copyright Â© 2014-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#ifndef _INTEL_HUC_H_
>-#define _INTEL_HUC_H_
>-
>-#include "i915_reg.h"
>-#include "intel_uc_fw.h"
>-#include "intel_huc_fw.h"
>-
>-struct intel_huc {
>-	/* Generic uC firmware management */
>-	struct intel_uc_fw fw;
>-
>-	/* HuC-specific additions */
>-	struct i915_vma *rsa_data;
>-	void *rsa_data_vaddr;
>-
>-	struct {
>-		i915_reg_t reg;
>-		u32 mask;
>-		u32 value;
>-	} status;
>-};
>-
>-void intel_huc_init_early(struct intel_huc *huc);
>-int intel_huc_init_misc(struct intel_huc *huc);
>-int intel_huc_init(struct intel_huc *huc);
>-void intel_huc_fini(struct intel_huc *huc);
>-int intel_huc_auth(struct intel_huc *huc);
>-int intel_huc_check_status(struct intel_huc *huc);
>-
>-static inline void intel_huc_fini_misc(struct intel_huc *huc)
>-{
>-	intel_uc_fw_cleanup_fetch(&huc->fw);
>-}
>-
>-static inline int intel_huc_sanitize(struct intel_huc *huc)
>-{
>-	intel_uc_fw_sanitize(&huc->fw);
>-	return 0;
>-}
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_pm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_pm.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_pm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_pm.c	2019-08-31 15:01:12.039736184 -0500
>@@ -1116,6 +1116,8 @@
> 	if (!intel_wm_plane_visible(crtc_state, plane_state))
> 		return 0;
> 
>+	cpp = plane_state->base.fb->format->cpp[0];
>+
> 	/*
> 	 * Not 100% sure which way ELK should go here as the
> 	 * spec only says CL/CTG should assume 32bpp and BW
>@@ -1129,9 +1131,7 @@
> 	 */
> 	if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
> 	    level != G4X_WM_LEVEL_NORMAL)
>-		cpp = 4;
>-	else
>-		cpp = plane_state->base.fb->format->cpp[0];
>+		cpp = max(cpp, 4u);
> 
> 	clock = adjusted_mode->crtc_clock;
> 	htotal = adjusted_mode->crtc_htotal;
>@@ -1198,8 +1198,8 @@
> 	return dirty;
> }
> 
>-static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
>-			      const struct intel_plane_state *pstate,
>+static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
>+			      const struct intel_plane_state *plane_state,
> 			      u32 pri_val);
> 
> static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
>@@ -1566,13 +1566,13 @@
> 				    struct intel_crtc_state *crtc_state)
> {
> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
>+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> 
> 	if (!crtc_state->wm.need_postvbl_update)
> 		return;
> 
> 	mutex_lock(&dev_priv->wm.wm_mutex);
>-	intel_crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
>+	crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
> 	g4x_program_watermarks(dev_priv);
> 	mutex_unlock(&dev_priv->wm.wm_mutex);
> }
>@@ -2185,13 +2185,13 @@
> 				    struct intel_crtc_state *crtc_state)
> {
> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
>+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> 
> 	if (!crtc_state->wm.need_postvbl_update)
> 		return;
> 
> 	mutex_lock(&dev_priv->wm.wm_mutex);
>-	intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
>+	crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
> 	vlv_program_watermarks(dev_priv);
> 	mutex_unlock(&dev_priv->wm.wm_mutex);
> }
>@@ -2493,8 +2493,8 @@
>  * For both WM_PIPE and WM_LP.
>  * mem_value must be in 0.1us units.
>  */
>-static u32 ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
>-			      const struct intel_plane_state *pstate,
>+static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
>+			      const struct intel_plane_state *plane_state,
> 			      u32 mem_value, bool is_lp)
> {
> 	u32 method1, method2;
>@@ -2503,19 +2503,19 @@
> 	if (mem_value == 0)
> 		return U32_MAX;
> 
>-	if (!intel_wm_plane_visible(cstate, pstate))
>+	if (!intel_wm_plane_visible(crtc_state, plane_state))
> 		return 0;
> 
>-	cpp = pstate->base.fb->format->cpp[0];
>+	cpp = plane_state->base.fb->format->cpp[0];
> 
>-	method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
>+	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
> 
> 	if (!is_lp)
> 		return method1;
> 
>-	method2 = ilk_wm_method2(cstate->pixel_rate,
>-				 cstate->base.adjusted_mode.crtc_htotal,
>-				 drm_rect_width(&pstate->base.dst),
>+	method2 = ilk_wm_method2(crtc_state->pixel_rate,
>+				 crtc_state->base.adjusted_mode.crtc_htotal,
>+				 drm_rect_width(&plane_state->base.dst),
> 				 cpp, mem_value);
> 
> 	return min(method1, method2);
>@@ -2525,8 +2525,8 @@
>  * For both WM_PIPE and WM_LP.
>  * mem_value must be in 0.1us units.
>  */
>-static u32 ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
>-			      const struct intel_plane_state *pstate,
>+static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
>+			      const struct intel_plane_state *plane_state,
> 			      u32 mem_value)
> {
> 	u32 method1, method2;
>@@ -2535,15 +2535,15 @@
> 	if (mem_value == 0)
> 		return U32_MAX;
> 
>-	if (!intel_wm_plane_visible(cstate, pstate))
>+	if (!intel_wm_plane_visible(crtc_state, plane_state))
> 		return 0;
> 
>-	cpp = pstate->base.fb->format->cpp[0];
>+	cpp = plane_state->base.fb->format->cpp[0];
> 
>-	method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);
>-	method2 = ilk_wm_method2(cstate->pixel_rate,
>-				 cstate->base.adjusted_mode.crtc_htotal,
>-				 drm_rect_width(&pstate->base.dst),
>+	method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
>+	method2 = ilk_wm_method2(crtc_state->pixel_rate,
>+				 crtc_state->base.adjusted_mode.crtc_htotal,
>+				 drm_rect_width(&plane_state->base.dst),
> 				 cpp, mem_value);
> 	return min(method1, method2);
> }
>@@ -2552,8 +2552,8 @@
>  * For both WM_PIPE and WM_LP.
>  * mem_value must be in 0.1us units.
>  */
>-static u32 ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
>-			      const struct intel_plane_state *pstate,
>+static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
>+			      const struct intel_plane_state *plane_state,
> 			      u32 mem_value)
> {
> 	int cpp;
>@@ -2561,29 +2561,29 @@
> 	if (mem_value == 0)
> 		return U32_MAX;
> 
>-	if (!intel_wm_plane_visible(cstate, pstate))
>+	if (!intel_wm_plane_visible(crtc_state, plane_state))
> 		return 0;
> 
>-	cpp = pstate->base.fb->format->cpp[0];
>+	cpp = plane_state->base.fb->format->cpp[0];
> 
>-	return ilk_wm_method2(cstate->pixel_rate,
>-			      cstate->base.adjusted_mode.crtc_htotal,
>-			      pstate->base.crtc_w, cpp, mem_value);
>+	return ilk_wm_method2(crtc_state->pixel_rate,
>+			      crtc_state->base.adjusted_mode.crtc_htotal,
>+			      plane_state->base.crtc_w, cpp, mem_value);
> }
> 
> /* Only for WM_LP. */
>-static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
>-			      const struct intel_plane_state *pstate,
>+static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
>+			      const struct intel_plane_state *plane_state,
> 			      u32 pri_val)
> {
> 	int cpp;
> 
>-	if (!intel_wm_plane_visible(cstate, pstate))
>+	if (!intel_wm_plane_visible(crtc_state, plane_state))
> 		return 0;
> 
>-	cpp = pstate->base.fb->format->cpp[0];
>+	cpp = plane_state->base.fb->format->cpp[0];
> 
>-	return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
>+	return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->base.dst), cpp);
> }
> 
> static unsigned int
>@@ -2752,7 +2752,7 @@
> static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
> 				 const struct intel_crtc *intel_crtc,
> 				 int level,
>-				 struct intel_crtc_state *cstate,
>+				 struct intel_crtc_state *crtc_state,
> 				 const struct intel_plane_state *pristate,
> 				 const struct intel_plane_state *sprstate,
> 				 const struct intel_plane_state *curstate,
>@@ -2770,30 +2770,30 @@
> 	}
> 
> 	if (pristate) {
>-		result->pri_val = ilk_compute_pri_wm(cstate, pristate,
>+		result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
> 						     pri_latency, level);
>-		result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
>+		result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
> 	}
> 
> 	if (sprstate)
>-		result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
>+		result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);
> 
> 	if (curstate)
>-		result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
>+		result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);
> 
> 	result->enable = true;
> }
> 
> static u32
>-hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
>+hsw_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
> {
> 	const struct intel_atomic_state *intel_state =
>-		to_intel_atomic_state(cstate->base.state);
>+		to_intel_atomic_state(crtc_state->base.state);
> 	const struct drm_display_mode *adjusted_mode =
>-		&cstate->base.adjusted_mode;
>+		&crtc_state->base.adjusted_mode;
> 	u32 linetime, ips_linetime;
> 
>-	if (!cstate->base.active)
>+	if (!crtc_state->base.active)
> 		return 0;
> 	if (WARN_ON(adjusted_mode->crtc_clock == 0))
> 		return 0;
>@@ -3101,10 +3101,10 @@
> }
> 
> /* Compute new watermarks for the pipe */
>-static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
>+static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
> {
>-	struct drm_atomic_state *state = cstate->base.state;
>-	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
>+	struct drm_atomic_state *state = crtc_state->base.state;
>+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> 	struct intel_pipe_wm *pipe_wm;
> 	struct drm_device *dev = state->dev;
> 	const struct drm_i915_private *dev_priv = to_i915(dev);
>@@ -3116,9 +3116,9 @@
> 	int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
> 	struct ilk_wm_maximums max;
> 
>-	pipe_wm = &cstate->wm.ilk.optimal;
>+	pipe_wm = &crtc_state->wm.ilk.optimal;
> 
>-	drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &cstate->base) {
>+	drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &crtc_state->base) {
> 		const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
> 
> 		if (plane->type == DRM_PLANE_TYPE_PRIMARY)
>@@ -3129,7 +3129,7 @@
> 			curstate = ps;
> 	}
> 
>-	pipe_wm->pipe_enabled = cstate->base.active;
>+	pipe_wm->pipe_enabled = crtc_state->base.active;
> 	if (sprstate) {
> 		pipe_wm->sprites_enabled = sprstate->base.visible;
> 		pipe_wm->sprites_scaled = sprstate->base.visible &&
>@@ -3148,11 +3148,11 @@
> 		usable_level = 0;
> 
> 	memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
>-	ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
>+	ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
> 			     pristate, sprstate, curstate, &pipe_wm->wm[0]);
> 
> 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>-		pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
>+		pipe_wm->linetime = hsw_compute_linetime_wm(crtc_state);
> 
> 	if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
> 		return -EINVAL;
>@@ -3162,7 +3162,7 @@
> 	for (level = 1; level <= usable_level; level++) {
> 		struct intel_wm_level *wm = &pipe_wm->wm[level];
> 
>-		ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
>+		ilk_compute_wm_level(dev_priv, intel_crtc, level, crtc_state,
> 				     pristate, sprstate, curstate, wm);
> 
> 		/*
>@@ -3736,14 +3736,13 @@
> 	return 0;
> }
> 
>-bool intel_can_enable_sagv(struct drm_atomic_state *state)
>+bool intel_can_enable_sagv(struct intel_atomic_state *state)
> {
>-	struct drm_device *dev = state->dev;
>+	struct drm_device *dev = state->base.dev;
> 	struct drm_i915_private *dev_priv = to_i915(dev);
>-	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> 	struct intel_crtc *crtc;
> 	struct intel_plane *plane;
>-	struct intel_crtc_state *cstate;
>+	struct intel_crtc_state *crtc_state;
> 	enum pipe pipe;
> 	int level, latency;
> 	int sagv_block_time_us;
>@@ -3761,27 +3760,27 @@
> 	/*
> 	 * If there are no active CRTCs, no additional checks need be performed
> 	 */
>-	if (hweight32(intel_state->active_crtcs) == 0)
>+	if (hweight32(state->active_crtcs) == 0)
> 		return true;
> 
> 	/*
> 	 * SKL+ workaround: bspec recommends we disable SAGV when we have
> 	 * more then one pipe enabled
> 	 */
>-	if (hweight32(intel_state->active_crtcs) > 1)
>+	if (hweight32(state->active_crtcs) > 1)
> 		return false;
> 
> 	/* Since we're now guaranteed to only have one active CRTC... */
>-	pipe = ffs(intel_state->active_crtcs) - 1;
>+	pipe = ffs(state->active_crtcs) - 1;
> 	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>-	cstate = to_intel_crtc_state(crtc->base.state);
>+	crtc_state = to_intel_crtc_state(crtc->base.state);
> 
> 	if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> 		return false;
> 
> 	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> 		struct skl_plane_wm *wm =
>-			&cstate->wm.skl.optimal.planes[plane->id];
>+			&crtc_state->wm.skl.optimal.planes[plane->id];
> 
> 		/* Skip this plane if it's not enabled */
> 		if (!wm->wm[0].plane_en)
>@@ -3812,7 +3811,7 @@
> }
> 
> static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
>-			      const struct intel_crtc_state *cstate,
>+			      const struct intel_crtc_state *crtc_state,
> 			      const u64 total_data_rate,
> 			      const int num_active,
> 			      struct skl_ddb_allocation *ddb)
>@@ -3826,7 +3825,7 @@
> 	if (INTEL_GEN(dev_priv) < 11)
> 		return ddb_size - 4; /* 4 blocks for bypass path allocation */
> 
>-	adjusted_mode = &cstate->base.adjusted_mode;
>+	adjusted_mode = &crtc_state->base.adjusted_mode;
> 	total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
> 
> 	/*
>@@ -3849,23 +3848,22 @@
> 
> static void
> skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
>-				   const struct intel_crtc_state *cstate,
>+				   const struct intel_crtc_state *crtc_state,
> 				   const u64 total_data_rate,
> 				   struct skl_ddb_allocation *ddb,
> 				   struct skl_ddb_entry *alloc, /* out */
> 				   int *num_active /* out */)
> {
>-	struct drm_atomic_state *state = cstate->base.state;
>+	struct drm_atomic_state *state = crtc_state->base.state;
> 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>-	struct drm_crtc *for_crtc = cstate->base.crtc;
>-	const struct drm_crtc_state *crtc_state;
>-	const struct drm_crtc *crtc;
>+	struct drm_crtc *for_crtc = crtc_state->base.crtc;
>+	const struct intel_crtc *crtc;
> 	u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
> 	enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
> 	u16 ddb_size;
> 	u32 i;
> 
>-	if (WARN_ON(!state) || !cstate->base.active) {
>+	if (WARN_ON(!state) || !crtc_state->base.active) {
> 		alloc->start = 0;
> 		alloc->end = 0;
> 		*num_active = hweight32(dev_priv->active_crtcs);
>@@ -3877,7 +3875,7 @@
> 	else
> 		*num_active = hweight32(dev_priv->active_crtcs);
> 
>-	ddb_size = intel_get_ddb_size(dev_priv, cstate, total_data_rate,
>+	ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
> 				      *num_active, ddb);
> 
> 	/*
>@@ -3902,16 +3900,15 @@
> 	 * framebuffer, So instead of allocating DDB equally among pipes
> 	 * distribute DDB based on resolution/width of the display.
> 	 */
>-	for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
>-		const struct drm_display_mode *adjusted_mode;
>+	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
>+		const struct drm_display_mode *adjusted_mode =
>+			&crtc_state->base.adjusted_mode;
>+		enum pipe pipe = crtc->pipe;
> 		int hdisplay, vdisplay;
>-		enum pipe pipe;
> 
>-		if (!crtc_state->enable)
>+		if (!crtc_state->base.enable)
> 			continue;
> 
>-		pipe = to_intel_crtc(crtc)->pipe;
>-		adjusted_mode = &crtc_state->adjusted_mode;
> 		drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
> 		total_width += hdisplay;
> 
>@@ -3930,7 +3927,7 @@
> 				 u64 modifier, unsigned int rotation,
> 				 u32 plane_pixel_rate, struct skl_wm_params *wp,
> 				 int color_plane);
>-static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
>+static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> 				 int level,
> 				 const struct skl_wm_params *wp,
> 				 const struct skl_wm_level *result_prev,
>@@ -4062,15 +4059,15 @@
>  * Caller should take care of dividing & rounding off the value.
>  */
> static uint_fixed_16_16_t
>-skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
>-			   const struct intel_plane_state *pstate)
>+skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
>+			   const struct intel_plane_state *plane_state)
> {
>-	struct intel_plane *plane = to_intel_plane(pstate->base.plane);
>+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
> 	u32 src_w, src_h, dst_w, dst_h;
> 	uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
> 	uint_fixed_16_16_t downscale_h, downscale_w;
> 
>-	if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
>+	if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
> 		return u32_to_fixed16(0);
> 
> 	/* n.b., src is 16.16 fixed point, dst is whole integer */
>@@ -4079,20 +4076,20 @@
> 		 * Cursors only support 0/180 degree rotation,
> 		 * hence no need to account for rotation here.
> 		 */
>-		src_w = pstate->base.src_w >> 16;
>-		src_h = pstate->base.src_h >> 16;
>-		dst_w = pstate->base.crtc_w;
>-		dst_h = pstate->base.crtc_h;
>+		src_w = plane_state->base.src_w >> 16;
>+		src_h = plane_state->base.src_h >> 16;
>+		dst_w = plane_state->base.crtc_w;
>+		dst_h = plane_state->base.crtc_h;
> 	} else {
> 		/*
> 		 * Src coordinates are already rotated by 270 degrees for
> 		 * the 90/270 degree plane rotation cases (to match the
> 		 * GTT mapping), hence no need to account for rotation here.
> 		 */
>-		src_w = drm_rect_width(&pstate->base.src) >> 16;
>-		src_h = drm_rect_height(&pstate->base.src) >> 16;
>-		dst_w = drm_rect_width(&pstate->base.dst);
>-		dst_h = drm_rect_height(&pstate->base.dst);
>+		src_w = drm_rect_width(&plane_state->base.src) >> 16;
>+		src_h = drm_rect_height(&plane_state->base.src) >> 16;
>+		dst_w = drm_rect_width(&plane_state->base.dst);
>+		dst_h = drm_rect_height(&plane_state->base.dst);
> 	}
> 
> 	fp_w_ratio = div_fixed16(src_w, dst_w);
>@@ -4137,49 +4134,46 @@
> }
> 
> int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
>-				  struct intel_crtc_state *cstate)
>+				  struct intel_crtc_state *crtc_state)
> {
> 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
>-	struct drm_crtc_state *crtc_state = &cstate->base;
>-	struct drm_atomic_state *state = crtc_state->state;
>+	struct drm_atomic_state *state = crtc_state->base.state;
> 	struct drm_plane *plane;
>-	const struct drm_plane_state *pstate;
>-	struct intel_plane_state *intel_pstate;
>+	const struct drm_plane_state *drm_plane_state;
> 	int crtc_clock, dotclk;
> 	u32 pipe_max_pixel_rate;
> 	uint_fixed_16_16_t pipe_downscale;
> 	uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
> 
>-	if (!cstate->base.enable)
>+	if (!crtc_state->base.enable)
> 		return 0;
> 
>-	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
>+	drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
> 		uint_fixed_16_16_t plane_downscale;
> 		uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
> 		int bpp;
>+		const struct intel_plane_state *plane_state =
>+			to_intel_plane_state(drm_plane_state);
> 
>-		if (!intel_wm_plane_visible(cstate,
>-					    to_intel_plane_state(pstate)))
>+		if (!intel_wm_plane_visible(crtc_state, plane_state))
> 			continue;
> 
>-		if (WARN_ON(!pstate->fb))
>+		if (WARN_ON(!plane_state->base.fb))
> 			return -EINVAL;
> 
>-		intel_pstate = to_intel_plane_state(pstate);
>-		plane_downscale = skl_plane_downscale_amount(cstate,
>-							     intel_pstate);
>-		bpp = pstate->fb->format->cpp[0] * 8;
>+		plane_downscale = skl_plane_downscale_amount(crtc_state, plane_state);
>+		bpp = plane_state->base.fb->format->cpp[0] * 8;
> 		if (bpp == 64)
> 			plane_downscale = mul_fixed16(plane_downscale,
> 						      fp_9_div_8);
> 
> 		max_downscale = max_fixed16(plane_downscale, max_downscale);
> 	}
>-	pipe_downscale = skl_pipe_downscale_amount(cstate);
>+	pipe_downscale = skl_pipe_downscale_amount(crtc_state);
> 
> 	pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
> 
>-	crtc_clock = crtc_state->adjusted_mode.crtc_clock;
>+	crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> 	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
> 
> 	if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
>@@ -4196,12 +4190,11 @@
> }
> 
> static u64
>-skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>-			     const struct intel_plane_state *intel_pstate,
>+skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
>+			     const struct intel_plane_state *plane_state,
> 			     const int plane)
> {
>-	struct intel_plane *intel_plane =
>-		to_intel_plane(intel_pstate->base.plane);
>+	struct intel_plane *intel_plane = to_intel_plane(plane_state->base.plane);
> 	u32 data_rate;
> 	u32 width = 0, height = 0;
> 	struct drm_framebuffer *fb;
>@@ -4209,10 +4202,10 @@
> 	uint_fixed_16_16_t down_scale_amount;
> 	u64 rate;
> 
>-	if (!intel_pstate->base.visible)
>+	if (!plane_state->base.visible)
> 		return 0;
> 
>-	fb = intel_pstate->base.fb;
>+	fb = plane_state->base.fb;
> 	format = fb->format->format;
> 
> 	if (intel_plane->id == PLANE_CURSOR)
>@@ -4225,8 +4218,8 @@
> 	 * the 90/270 degree plane rotation cases (to match the
> 	 * GTT mapping), hence no need to account for rotation here.
> 	 */
>-	width = drm_rect_width(&intel_pstate->base.src) >> 16;
>-	height = drm_rect_height(&intel_pstate->base.src) >> 16;
>+	width = drm_rect_width(&plane_state->base.src) >> 16;
>+	height = drm_rect_height(&plane_state->base.src) >> 16;
> 
> 	/* UV plane does 1/2 pixel sub-sampling */
> 	if (plane == 1 && is_planar_yuv_format(format)) {
>@@ -4236,7 +4229,7 @@
> 
> 	data_rate = width * height;
> 
>-	down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
>+	down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
> 
> 	rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
> 
>@@ -4245,35 +4238,32 @@
> }
> 
> static u64
>-skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
>+skl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> 				 u64 *plane_data_rate,
> 				 u64 *uv_plane_data_rate)
> {
>-	struct drm_crtc_state *cstate = &intel_cstate->base;
>-	struct drm_atomic_state *state = cstate->state;
>+	struct drm_atomic_state *state = crtc_state->base.state;
> 	struct drm_plane *plane;
>-	const struct drm_plane_state *pstate;
>+	const struct drm_plane_state *drm_plane_state;
> 	u64 total_data_rate = 0;
> 
> 	if (WARN_ON(!state))
> 		return 0;
> 
> 	/* Calculate and cache data rate for each plane */
>-	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
>+	drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
> 		enum plane_id plane_id = to_intel_plane(plane)->id;
>+		const struct intel_plane_state *plane_state =
>+			to_intel_plane_state(drm_plane_state);
> 		u64 rate;
>-		const struct intel_plane_state *intel_pstate =
>-			to_intel_plane_state(pstate);
> 
> 		/* packed/y */
>-		rate = skl_plane_relative_data_rate(intel_cstate,
>-						    intel_pstate, 0);
>+		rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
> 		plane_data_rate[plane_id] = rate;
> 		total_data_rate += rate;
> 
> 		/* uv-plane */
>-		rate = skl_plane_relative_data_rate(intel_cstate,
>-						    intel_pstate, 1);
>+		rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
> 		uv_plane_data_rate[plane_id] = rate;
> 		total_data_rate += rate;
> 	}
>@@ -4282,28 +4272,25 @@
> }
> 
> static u64
>-icl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
>+icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> 				 u64 *plane_data_rate)
> {
>-	struct drm_crtc_state *cstate = &intel_cstate->base;
>-	struct drm_atomic_state *state = cstate->state;
> 	struct drm_plane *plane;
>-	const struct drm_plane_state *pstate;
>+	const struct drm_plane_state *drm_plane_state;
> 	u64 total_data_rate = 0;
> 
>-	if (WARN_ON(!state))
>+	if (WARN_ON(!crtc_state->base.state))
> 		return 0;
> 
> 	/* Calculate and cache data rate for each plane */
>-	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
>-		const struct intel_plane_state *intel_pstate =
>-			to_intel_plane_state(pstate);
>+	drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state, &crtc_state->base) {
>+		const struct intel_plane_state *plane_state =
>+			to_intel_plane_state(drm_plane_state);
> 		enum plane_id plane_id = to_intel_plane(plane)->id;
> 		u64 rate;
> 
>-		if (!intel_pstate->linked_plane) {
>-			rate = skl_plane_relative_data_rate(intel_cstate,
>-							    intel_pstate, 0);
>+		if (!plane_state->linked_plane) {
>+			rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
> 			plane_data_rate[plane_id] = rate;
> 			total_data_rate += rate;
> 		} else {
>@@ -4316,18 +4303,16 @@
> 			 * NULL if we try get_new_plane_state(), so we
> 			 * always calculate from the master.
> 			 */
>-			if (intel_pstate->slave)
>+			if (plane_state->slave)
> 				continue;
> 
> 			/* Y plane rate is calculated on the slave */
>-			rate = skl_plane_relative_data_rate(intel_cstate,
>-							    intel_pstate, 0);
>-			y_plane_id = intel_pstate->linked_plane->id;
>+			rate = skl_plane_relative_data_rate(crtc_state, plane_state, 0);
>+			y_plane_id = plane_state->linked_plane->id;
> 			plane_data_rate[y_plane_id] = rate;
> 			total_data_rate += rate;
> 
>-			rate = skl_plane_relative_data_rate(intel_cstate,
>-							    intel_pstate, 1);
>+			rate = skl_plane_relative_data_rate(crtc_state, plane_state, 1);
> 			plane_data_rate[plane_id] = rate;
> 			total_data_rate += rate;
> 		}
>@@ -4337,14 +4322,14 @@
> }
> 
> static int
>-skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>+skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> 		      struct skl_ddb_allocation *ddb /* out */)
> {
>-	struct drm_atomic_state *state = cstate->base.state;
>-	struct drm_crtc *crtc = cstate->base.crtc;
>+	struct drm_atomic_state *state = crtc_state->base.state;
>+	struct drm_crtc *crtc = crtc_state->base.crtc;
> 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>-	struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
>+	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> 	u16 alloc_size, start = 0;
> 	u16 total[I915_MAX_PLANES] = {};
> 	u16 uv_total[I915_MAX_PLANES] = {};
>@@ -4357,40 +4342,40 @@
> 	int level;
> 
> 	/* Clear the partitioning for disabled planes. */
>-	memset(cstate->wm.skl.plane_ddb_y, 0, sizeof(cstate->wm.skl.plane_ddb_y));
>-	memset(cstate->wm.skl.plane_ddb_uv, 0, sizeof(cstate->wm.skl.plane_ddb_uv));
>+	memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
>+	memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
> 
> 	if (WARN_ON(!state))
> 		return 0;
> 
>-	if (!cstate->base.active) {
>+	if (!crtc_state->base.active) {
> 		alloc->start = alloc->end = 0;
> 		return 0;
> 	}
> 
> 	if (INTEL_GEN(dev_priv) >= 11)
> 		total_data_rate =
>-			icl_get_total_relative_data_rate(cstate,
>+			icl_get_total_relative_data_rate(crtc_state,
> 							 plane_data_rate);
> 	else
> 		total_data_rate =
>-			skl_get_total_relative_data_rate(cstate,
>+			skl_get_total_relative_data_rate(crtc_state,
> 							 plane_data_rate,
> 							 uv_plane_data_rate);
> 
> 
>-	skl_ddb_get_pipe_allocation_limits(dev_priv, cstate, total_data_rate,
>+	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
> 					   ddb, alloc, &num_active);
> 	alloc_size = skl_ddb_entry_size(alloc);
> 	if (alloc_size == 0)
> 		return 0;
> 
> 	/* Allocate fixed number of blocks for cursor. */
>-	total[PLANE_CURSOR] = skl_cursor_allocation(cstate, num_active);
>+	total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
> 	alloc_size -= total[PLANE_CURSOR];
>-	cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
>+	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> 		alloc->end - total[PLANE_CURSOR];
>-	cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
>+	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> 
> 	if (total_data_rate == 0)
> 		return 0;
>@@ -4403,7 +4388,7 @@
> 		blocks = 0;
> 		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> 			const struct skl_plane_wm *wm =
>-				&cstate->wm.skl.optimal.planes[plane_id];
>+				&crtc_state->wm.skl.optimal.planes[plane_id];
> 
> 			if (plane_id == PLANE_CURSOR) {
> 				if (WARN_ON(wm->wm[level].min_ddb_alloc >
>@@ -4438,7 +4423,7 @@
> 	 */
> 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> 		const struct skl_plane_wm *wm =
>-			&cstate->wm.skl.optimal.planes[plane_id];
>+			&crtc_state->wm.skl.optimal.planes[plane_id];
> 		u64 rate;
> 		u16 extra;
> 
>@@ -4477,9 +4462,9 @@
> 	start = alloc->start;
> 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> 		struct skl_ddb_entry *plane_alloc =
>-			&cstate->wm.skl.plane_ddb_y[plane_id];
>+			&crtc_state->wm.skl.plane_ddb_y[plane_id];
> 		struct skl_ddb_entry *uv_plane_alloc =
>-			&cstate->wm.skl.plane_ddb_uv[plane_id];
>+			&crtc_state->wm.skl.plane_ddb_uv[plane_id];
> 
> 		if (plane_id == PLANE_CURSOR)
> 			continue;
>@@ -4510,7 +4495,7 @@
> 	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
> 		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> 			struct skl_plane_wm *wm =
>-				&cstate->wm.skl.optimal.planes[plane_id];
>+				&crtc_state->wm.skl.optimal.planes[plane_id];
> 
> 			/*
> 			 * We only disable the watermarks for each plane if
>@@ -4547,7 +4532,7 @@
> 	 */
> 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> 		struct skl_plane_wm *wm =
>-			&cstate->wm.skl.optimal.planes[plane_id];
>+			&crtc_state->wm.skl.optimal.planes[plane_id];
> 
> 		if (wm->trans_wm.plane_res_b >= total[plane_id])
> 			memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
>@@ -4599,43 +4584,43 @@
> }
> 
> static uint_fixed_16_16_t
>-intel_get_linetime_us(const struct intel_crtc_state *cstate)
>+intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
> {
> 	u32 pixel_rate;
> 	u32 crtc_htotal;
> 	uint_fixed_16_16_t linetime_us;
> 
>-	if (!cstate->base.active)
>+	if (!crtc_state->base.active)
> 		return u32_to_fixed16(0);
> 
>-	pixel_rate = cstate->pixel_rate;
>+	pixel_rate = crtc_state->pixel_rate;
> 
> 	if (WARN_ON(pixel_rate == 0))
> 		return u32_to_fixed16(0);
> 
>-	crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
>+	crtc_htotal = crtc_state->base.adjusted_mode.crtc_htotal;
> 	linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
> 
> 	return linetime_us;
> }
> 
> static u32
>-skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
>-			      const struct intel_plane_state *pstate)
>+skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
>+			      const struct intel_plane_state *plane_state)
> {
> 	u64 adjusted_pixel_rate;
> 	uint_fixed_16_16_t downscale_amount;
> 
> 	/* Shouldn't reach here on disabled planes... */
>-	if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
>+	if (WARN_ON(!intel_wm_plane_visible(crtc_state, plane_state)))
> 		return 0;
> 
> 	/*
> 	 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
> 	 * with additional adjustments for plane-specific scaling.
> 	 */
>-	adjusted_pixel_rate = cstate->pixel_rate;
>-	downscale_amount = skl_plane_downscale_amount(cstate, pstate);
>+	adjusted_pixel_rate = crtc_state->pixel_rate;
>+	downscale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
> 
> 	return mul_round_up_u32_fixed16(adjusted_pixel_rate,
> 					    downscale_amount);
>@@ -4768,13 +4753,13 @@
> 	return level > 0;
> }
> 
>-static void skl_compute_plane_wm(const struct intel_crtc_state *cstate,
>+static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
> 				 int level,
> 				 const struct skl_wm_params *wp,
> 				 const struct skl_wm_level *result_prev,
> 				 struct skl_wm_level *result /* out */)
> {
>-	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> 	u32 latency = dev_priv->wm.skl_latency[level];
> 	uint_fixed_16_16_t method1, method2;
> 	uint_fixed_16_16_t selected_result;
>@@ -4800,14 +4785,14 @@
> 	method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
> 				 wp->cpp, latency, wp->dbuf_block_size);
> 	method2 = skl_wm_method2(wp->plane_pixel_rate,
>-				 cstate->base.adjusted_mode.crtc_htotal,
>+				 crtc_state->base.adjusted_mode.crtc_htotal,
> 				 latency,
> 				 wp->plane_blocks_per_line);
> 
> 	if (wp->y_tiled) {
> 		selected_result = max_fixed16(method2, wp->y_tile_minimum);
> 	} else {
>-		if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /
>+		if ((wp->cpp * crtc_state->base.adjusted_mode.crtc_htotal /
> 		     wp->dbuf_block_size < 1) &&
> 		     (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
> 			selected_result = method2;
>@@ -4894,18 +4879,18 @@
> }
> 
> static void
>-skl_compute_wm_levels(const struct intel_crtc_state *cstate,
>+skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> 		      const struct skl_wm_params *wm_params,
> 		      struct skl_wm_level *levels)
> {
>-	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
>+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> 	int level, max_level = ilk_wm_max_level(dev_priv);
> 	struct skl_wm_level *result_prev = &levels[0];
> 
> 	for (level = 0; level <= max_level; level++) {
> 		struct skl_wm_level *result = &levels[level];
> 
>-		skl_compute_plane_wm(cstate, level, wm_params,
>+		skl_compute_plane_wm(crtc_state, level, wm_params,
> 				     result_prev, result);
> 
> 		result_prev = result;
>@@ -4913,14 +4898,14 @@
> }
> 
> static u32
>-skl_compute_linetime_wm(const struct intel_crtc_state *cstate)
>+skl_compute_linetime_wm(const struct intel_crtc_state *crtc_state)
> {
>-	struct drm_atomic_state *state = cstate->base.state;
>+	struct drm_atomic_state *state = crtc_state->base.state;
> 	struct drm_i915_private *dev_priv = to_i915(state->dev);
> 	uint_fixed_16_16_t linetime_us;
> 	u32 linetime_wm;
> 
>-	linetime_us = intel_get_linetime_us(cstate);
>+	linetime_us = intel_get_linetime_us(crtc_state);
> 	linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us));
> 
> 	/* Display WA #1135: BXT:ALL GLK:ALL */
>@@ -4930,11 +4915,11 @@
> 	return linetime_wm;
> }
> 
>-static void skl_compute_transition_wm(const struct intel_crtc_state *cstate,
>+static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
> 				      const struct skl_wm_params *wp,
> 				      struct skl_plane_wm *wm)
> {
>-	struct drm_device *dev = cstate->base.crtc->dev;
>+	struct drm_device *dev = crtc_state->base.crtc->dev;
> 	const struct drm_i915_private *dev_priv = to_i915(dev);
> 	u16 trans_min, trans_y_tile_min;
> 	const u16 trans_amount = 10; /* This is configurable amount */
>@@ -5092,13 +5077,12 @@
> 	return 0;
> }
> 
>-static int skl_build_pipe_wm(struct intel_crtc_state *cstate)
>+static int skl_build_pipe_wm(struct intel_crtc_state *crtc_state)
> {
>-	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
>-	struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
>-	struct drm_crtc_state *crtc_state = &cstate->base;
>+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>+	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> 	struct drm_plane *plane;
>-	const struct drm_plane_state *pstate;
>+	const struct drm_plane_state *drm_plane_state;
> 	int ret;
> 
> 	/*
>@@ -5107,19 +5091,20 @@
> 	 */
> 	memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
> 
>-	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
>-		const struct intel_plane_state *intel_pstate =
>-						to_intel_plane_state(pstate);
>+	drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state,
>+						   &crtc_state->base) {
>+		const struct intel_plane_state *plane_state =
>+			to_intel_plane_state(drm_plane_state);
> 
> 		if (INTEL_GEN(dev_priv) >= 11)
>-			ret = icl_build_plane_wm(cstate, intel_pstate);
>+			ret = icl_build_plane_wm(crtc_state, plane_state);
> 		else
>-			ret = skl_build_plane_wm(cstate, intel_pstate);
>+			ret = skl_build_plane_wm(crtc_state, plane_state);
> 		if (ret)
> 			return ret;
> 	}
> 
>-	pipe_wm->linetime = skl_compute_linetime_wm(cstate);
>+	pipe_wm->linetime = skl_compute_linetime_wm(crtc_state);
> 
> 	return 0;
> }
>@@ -5273,10 +5258,10 @@
> pipes_modified(struct intel_atomic_state *state)
> {
> 	struct intel_crtc *crtc;
>-	struct intel_crtc_state *cstate;
>+	struct intel_crtc_state *crtc_state;
> 	u32 i, ret = 0;
> 
>-	for_each_new_intel_crtc_in_state(state, crtc, cstate, i)
>+	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
> 		ret |= drm_crtc_mask(&crtc->base);
> 
> 	return ret;
>@@ -5652,11 +5637,11 @@
> }
> 
> static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
>-				      struct intel_crtc_state *cstate)
>+				      struct intel_crtc_state *crtc_state)
> {
>-	struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
>+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>-	struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
>+	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
> 	enum pipe pipe = crtc->pipe;
> 
> 	if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
>@@ -5666,9 +5651,9 @@
> }
> 
> static void skl_initial_wm(struct intel_atomic_state *state,
>-			   struct intel_crtc_state *cstate)
>+			   struct intel_crtc_state *crtc_state)
> {
>-	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
>+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> 	struct drm_device *dev = intel_crtc->base.dev;
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct skl_ddb_values *results = &state->wm_results;
>@@ -5678,8 +5663,8 @@
> 
> 	mutex_lock(&dev_priv->wm.wm_mutex);
> 
>-	if (cstate->base.active_changed)
>-		skl_atomic_update_crtc_wm(state, cstate);
>+	if (crtc_state->base.active_changed)
>+		skl_atomic_update_crtc_wm(state, crtc_state);
> 
> 	mutex_unlock(&dev_priv->wm.wm_mutex);
> }
>@@ -5735,28 +5720,29 @@
> }
> 
> static void ilk_initial_watermarks(struct intel_atomic_state *state,
>-				   struct intel_crtc_state *cstate)
>+				   struct intel_crtc_state *crtc_state)
> {
>-	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
>-	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
>+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> 
> 	mutex_lock(&dev_priv->wm.wm_mutex);
>-	intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
>+	crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> 	ilk_program_watermarks(dev_priv);
> 	mutex_unlock(&dev_priv->wm.wm_mutex);
> }
> 
> static void ilk_optimize_watermarks(struct intel_atomic_state *state,
>-				    struct intel_crtc_state *cstate)
>+				    struct intel_crtc_state *crtc_state)
> {
>-	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
>-	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
>+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>+
>+	if (!crtc_state->wm.need_postvbl_update)
>+		return;
> 
> 	mutex_lock(&dev_priv->wm.wm_mutex);
>-	if (cstate->wm.need_postvbl_update) {
>-		intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
>-		ilk_program_watermarks(dev_priv);
>-	}
>+	crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
>+	ilk_program_watermarks(dev_priv);
> 	mutex_unlock(&dev_priv->wm.wm_mutex);
> }
> 
>@@ -5812,13 +5798,13 @@
> 	struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
> 	struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
> 	struct intel_crtc *crtc;
>-	struct intel_crtc_state *cstate;
>+	struct intel_crtc_state *crtc_state;
> 
> 	skl_ddb_get_hw_state(dev_priv, ddb);
> 	for_each_intel_crtc(&dev_priv->drm, crtc) {
>-		cstate = to_intel_crtc_state(crtc->base.state);
>+		crtc_state = to_intel_crtc_state(crtc->base.state);
> 
>-		skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
>+		skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
> 
> 		if (crtc->active)
> 			hw->dirty_pipes |= drm_crtc_mask(&crtc->base);
>@@ -5835,8 +5821,8 @@
> 	struct drm_device *dev = crtc->base.dev;
> 	struct drm_i915_private *dev_priv = to_i915(dev);
> 	struct ilk_wm_values *hw = &dev_priv->wm.hw;
>-	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->base.state);
>-	struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
>+	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
>+	struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
> 	enum pipe pipe = crtc->pipe;
> 	static const i915_reg_t wm0_pipe_reg[] = {
> 		[PIPE_A] = WM0_PIPEA_ILK,
>@@ -6891,9 +6877,10 @@
> 	/* Serializes with i915_request_retire() */
> 	boost = false;
> 	spin_lock_irqsave(&rq->lock, flags);
>-	if (!rq->waitboost && !dma_fence_is_signaled_locked(&rq->fence)) {
>+	if (!i915_request_has_waitboost(rq) &&
>+	    !dma_fence_is_signaled_locked(&rq->fence)) {
> 		boost = !atomic_fetch_inc(&rps->num_waiters);
>-		rq->waitboost = true;
>+		rq->flags |= I915_REQUEST_WAITBOOST;
> 	}
> 	spin_unlock_irqrestore(&rq->lock, flags);
> 	if (!boost)
>@@ -7175,7 +7162,7 @@
> 	for_each_engine(engine, dev_priv, id)
> 		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
> 
>-	if (HAS_GUC(dev_priv))
>+	if (HAS_GT_UC(dev_priv))
> 		I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
> 
> 	I915_WRITE(GEN6_RC_SLEEP, 0);
>@@ -7192,7 +7179,7 @@
> 	 * next request to execute. If the idle hysteresis is less than that
> 	 * interrupt service latency, the hardware will automatically gate
> 	 * the power well and we will then incur the wake up cost on top of
>-	 * the service latency. A similar guide from intel_pstate is that we
>+	 * the service latency. A similar guide from plane_state is that we
> 	 * do not want the enable hysteresis to less than the wakeup latency.
> 	 *
> 	 * igt/gem_exec_nop/sequential provides a rough estimate for the
>@@ -7256,7 +7243,7 @@
> 	for_each_engine(engine, dev_priv, id)
> 		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
> 
>-	if (HAS_GUC(dev_priv))
>+	if (HAS_GT_UC(dev_priv))
> 		I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
> 
> 	I915_WRITE(GEN6_RC_SLEEP, 0);
>@@ -7271,7 +7258,7 @@
> 	 * next request to execute. If the idle hysteresis is less than that
> 	 * interrupt service latency, the hardware will automatically gate
> 	 * the power well and we will then incur the wake up cost on top of
>-	 * the service latency. A similar guide from intel_pstate is that we
>+	 * the service latency. A similar guide from plane_state is that we
> 	 * do not want the enable hysteresis to less than the wakeup latency.
> 	 *
> 	 * igt/gem_exec_nop/sequential provides a rough estimate for the
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_pm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_pm.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_pm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_pm.h	2019-08-31 15:01:12.039736184 -0500
>@@ -10,10 +10,10 @@
> 
> #include "i915_reg.h"
> 
>-struct drm_atomic_state;
> struct drm_device;
> struct drm_i915_private;
> struct i915_request;
>+struct intel_atomic_state;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_plane;
>@@ -52,7 +52,7 @@
> 			      struct skl_pipe_wm *out);
> void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
>-bool intel_can_enable_sagv(struct drm_atomic_state *state);
>+bool intel_can_enable_sagv(struct intel_atomic_state *state);
> int intel_enable_sagv(struct drm_i915_private *dev_priv);
> int intel_disable_sagv(struct drm_i915_private *dev_priv);
> bool skl_wm_level_equals(const struct skl_wm_level *l1,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_renderstate_gen6.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_renderstate_gen6.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_renderstate_gen6.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_renderstate_gen6.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,315 +0,0 @@
>-/*
>- * Copyright Â© 2014 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>- * DEALINGS IN THE SOFTWARE.
>- *
>- * Generated by: intel-gpu-tools-1.8-220-g01153e7
>- */
>-
>-#include "intel_renderstate.h"
>-
>-static const u32 gen6_null_state_relocs[] = {
>-	0x00000020,
>-	0x00000024,
>-	0x0000002c,
>-	0x000001e0,
>-	0x000001e4,
>-	-1,
>-};
>-
>-static const u32 gen6_null_state_batch[] = {
>-	0x69040000,
>-	0x790d0001,
>-	0x00000000,
>-	0x00000000,
>-	0x78180000,
>-	0x00000001,
>-	0x61010008,
>-	0x00000000,
>-	0x00000001,	 /* reloc */
>-	0x00000001,	 /* reloc */
>-	0x00000000,
>-	0x00000001,	 /* reloc */
>-	0x00000000,
>-	0x00000001,
>-	0x00000000,
>-	0x00000001,
>-	0x61020000,
>-	0x00000000,
>-	0x78050001,
>-	0x00000018,
>-	0x00000000,
>-	0x780d1002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000420,
>-	0x78150003,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78100004,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78160003,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78110005,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78120002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78170003,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79050005,
>-	0xe0040000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79100000,
>-	0x00000000,
>-	0x79000002,
>-	0xffffffff,
>-	0x00000000,
>-	0x00000000,
>-	0x780e0002,
>-	0x00000441,
>-	0x00000401,
>-	0x00000401,
>-	0x78021002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000400,
>-	0x78130012,
>-	0x00400810,
>-	0x00000000,
>-	0x20000000,
>-	0x04000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78140007,
>-	0x00000280,
>-	0x08080000,
>-	0x00000000,
>-	0x00060000,
>-	0x4e080002,
>-	0x00100400,
>-	0x00000000,
>-	0x00000000,
>-	0x78090005,
>-	0x02000000,
>-	0x22220000,
>-	0x02f60000,
>-	0x11330000,
>-	0x02850004,
>-	0x11220000,
>-	0x78011002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000200,
>-	0x78080003,
>-	0x00002000,
>-	0x00000448,	 /* reloc */
>-	0x00000448,	 /* reloc */
>-	0x00000000,
>-	0x05000000,	 /* cmds end */
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000220,	 /* state start */
>-	0x00000240,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x0060005a,
>-	0x204077be,
>-	0x000000c0,
>-	0x008d0040,
>-	0x0060005a,
>-	0x206077be,
>-	0x000000c0,
>-	0x008d0080,
>-	0x0060005a,
>-	0x208077be,
>-	0x000000d0,
>-	0x008d0040,
>-	0x0060005a,
>-	0x20a077be,
>-	0x000000d0,
>-	0x008d0080,
>-	0x00000201,
>-	0x20080061,
>-	0x00000000,
>-	0x00000000,
>-	0x00600001,
>-	0x20200022,
>-	0x008d0000,
>-	0x00000000,
>-	0x02800031,
>-	0x21c01cc9,
>-	0x00000020,
>-	0x0a8a0001,
>-	0x00600001,
>-	0x204003be,
>-	0x008d01c0,
>-	0x00000000,
>-	0x00600001,
>-	0x206003be,
>-	0x008d01e0,
>-	0x00000000,
>-	0x00600001,
>-	0x208003be,
>-	0x008d0200,
>-	0x00000000,
>-	0x00600001,
>-	0x20a003be,
>-	0x008d0220,
>-	0x00000000,
>-	0x00600001,
>-	0x20c003be,
>-	0x008d0240,
>-	0x00000000,
>-	0x00600001,
>-	0x20e003be,
>-	0x008d0260,
>-	0x00000000,
>-	0x00600001,
>-	0x210003be,
>-	0x008d0280,
>-	0x00000000,
>-	0x00600001,
>-	0x212003be,
>-	0x008d02a0,
>-	0x00000000,
>-	0x05800031,
>-	0x24001cc8,
>-	0x00000040,
>-	0x90019000,
>-	0x0000007e,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x0000007e,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x0000007e,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x0000007e,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x0000007e,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x0000007e,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x0000007e,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x0000007e,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x30000000,
>-	0x00000124,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0xf99a130c,
>-	0x799a130c,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x80000031,
>-	0x00000003,
>-	0x00000000,	 /* state end */
>-};
>-
>-RO_RENDERSTATE(6);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_renderstate_gen7.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_renderstate_gen7.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_renderstate_gen7.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_renderstate_gen7.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,279 +0,0 @@
>-/*
>- * Copyright Â© 2014 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>- * DEALINGS IN THE SOFTWARE.
>- *
>- * Generated by: intel-gpu-tools-1.8-220-g01153e7
>- */
>-
>-#include "intel_renderstate.h"
>-
>-static const u32 gen7_null_state_relocs[] = {
>-	0x0000000c,
>-	0x00000010,
>-	0x00000018,
>-	0x000001ec,
>-	-1,
>-};
>-
>-static const u32 gen7_null_state_batch[] = {
>-	0x69040000,
>-	0x61010008,
>-	0x00000000,
>-	0x00000001,	 /* reloc */
>-	0x00000001,	 /* reloc */
>-	0x00000000,
>-	0x00000001,	 /* reloc */
>-	0x00000000,
>-	0x00000001,
>-	0x00000000,
>-	0x00000001,
>-	0x790d0002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78180000,
>-	0x00000001,
>-	0x79160000,
>-	0x00000008,
>-	0x78300000,
>-	0x02010040,
>-	0x78310000,
>-	0x04000000,
>-	0x78320000,
>-	0x04000000,
>-	0x78330000,
>-	0x02000000,
>-	0x78100004,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x781b0005,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x781c0002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x781d0004,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78110005,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78120002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78210000,
>-	0x00000000,
>-	0x78130005,
>-	0x00000000,
>-	0x20000000,
>-	0x04000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78140001,
>-	0x20000800,
>-	0x00000000,
>-	0x781e0001,
>-	0x00000000,
>-	0x00000000,
>-	0x78050005,
>-	0xe0040000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78040001,
>-	0x00000000,
>-	0x00000000,
>-	0x78240000,
>-	0x00000240,
>-	0x78230000,
>-	0x00000260,
>-	0x782f0000,
>-	0x00000280,
>-	0x781f000c,
>-	0x00400810,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78200006,
>-	0x000002c0,
>-	0x08080000,
>-	0x00000000,
>-	0x28000402,
>-	0x00060000,
>-	0x00000000,
>-	0x00000000,
>-	0x78090005,
>-	0x02000000,
>-	0x22220000,
>-	0x02f60000,
>-	0x11230000,
>-	0x02f60004,
>-	0x11230000,
>-	0x78080003,
>-	0x00006008,
>-	0x00000340,	 /* reloc */
>-	0xffffffff,
>-	0x00000000,
>-	0x782a0000,
>-	0x00000360,
>-	0x79000002,
>-	0xffffffff,
>-	0x00000000,
>-	0x00000000,
>-	0x7b000005,
>-	0x0000000f,
>-	0x00000003,
>-	0x00000000,
>-	0x00000001,
>-	0x00000000,
>-	0x00000000,
>-	0x05000000,	 /* cmds end */
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000031,	 /* state start */
>-	0x00000003,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0xf99a130c,
>-	0x799a130c,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000492,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x0080005a,
>-	0x2e2077bd,
>-	0x000000c0,
>-	0x008d0040,
>-	0x0080005a,
>-	0x2e6077bd,
>-	0x000000d0,
>-	0x008d0040,
>-	0x02800031,
>-	0x21801fa9,
>-	0x008d0e20,
>-	0x08840001,
>-	0x00800001,
>-	0x2e2003bd,
>-	0x008d0180,
>-	0x00000000,
>-	0x00800001,
>-	0x2e6003bd,
>-	0x008d01c0,
>-	0x00000000,
>-	0x00800001,
>-	0x2ea003bd,
>-	0x008d0200,
>-	0x00000000,
>-	0x00800001,
>-	0x2ee003bd,
>-	0x008d0240,
>-	0x00000000,
>-	0x05800031,
>-	0x20001fa8,
>-	0x008d0e20,
>-	0x90031000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000380,
>-	0x000003a0,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,	 /* state end */
>-};
>-
>-RO_RENDERSTATE(7);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_renderstate_gen8.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_renderstate_gen8.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_renderstate_gen8.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_renderstate_gen8.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,983 +0,0 @@
>-/*
>- * Copyright Â© 2014 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>- * DEALINGS IN THE SOFTWARE.
>- *
>- * Generated by: intel-gpu-tools-1.8-220-g01153e7
>- */
>-
>-#include "intel_renderstate.h"
>-
>-static const u32 gen8_null_state_relocs[] = {
>-	0x00000798,
>-	0x000007a4,
>-	0x000007ac,
>-	0x000007bc,
>-	-1,
>-};
>-
>-static const u32 gen8_null_state_batch[] = {
>-	0x7a000004,
>-	0x01000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x69040000,
>-	0x78140000,
>-	0x04000000,
>-	0x7820000a,
>-	0x00000000,
>-	0x00000000,
>-	0x80000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78130002,
>-	0x00000000,
>-	0x00000000,
>-	0x02001808,
>-	0x781f0002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78510009,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78100007,
>-	0x00000000,
>-	0x00000000,
>-	0x00010000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x781b0007,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000800,
>-	0x00000000,
>-	0x78110008,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x781e0003,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x781d0007,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78120002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78500003,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x781c0002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x780c0000,
>-	0x00000000,
>-	0x78520003,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78300000,
>-	0x08010040,
>-	0x78310000,
>-	0x1e000000,
>-	0x78320000,
>-	0x1e000000,
>-	0x78330000,
>-	0x1e000000,
>-	0x79190002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x791a0002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x791b0002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79120000,
>-	0x00000000,
>-	0x79130000,
>-	0x00000000,
>-	0x79140000,
>-	0x00000000,
>-	0x79150000,
>-	0x00000000,
>-	0x79160000,
>-	0x00000000,
>-	0x78150009,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78190009,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x781a0009,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78160009,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78170009,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78490001,
>-	0x00000000,
>-	0x00000000,
>-	0x784a0000,
>-	0x00000000,
>-	0x784b0000,
>-	0x00000004,
>-	0x79170101,
>-	0x00000000,
>-	0x00000080,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
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>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
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>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
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>-	0x00000000,
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>-	0x00000000,
>-	0x00000000,
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>-	0x00000000,
>-	0x00000000,
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>-	0x00000000,
>-	0x79180006,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79180006,
>-	0x20000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
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>-	0x00000000,
>-	0x79180006,
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>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x6101000e,
>-	0x00000001,	 /* reloc */
>-	0x00000000,
>-	0x00000000,
>-	0x00000001,	 /* reloc */
>-	0x00000000,
>-	0x00000001,	 /* reloc */
>-	0x00000000,
>-	0x00000001,
>-	0x00000000,
>-	0x00000001,	 /* reloc */
>-	0x00000000,
>-	0x00001001,
>-	0x00001001,
>-	0x00000001,
>-	0x00001001,
>-	0x61020001,
>-	0x00000000,
>-	0x00000000,
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>-	0x680b0001,
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>-	0x00000000,
>-	0x78270000,
>-	0x00000000,
>-	0x78280000,
>-	0x00000000,
>-	0x78290000,
>-	0x00000000,
>-	0x782a0000,
>-	0x00000000,
>-	0x780e0000,
>-	0x00000dc1,
>-	0x78240000,
>-	0x00000e01,
>-	0x784f0000,
>-	0x80000100,
>-	0x784d0000,
>-	0x40000000,
>-	0x782b0000,
>-	0x00000000,
>-	0x782c0000,
>-	0x00000000,
>-	0x782d0000,
>-	0x00000000,
>-	0x782e0000,
>-	0x00000000,
>-	0x782f0000,
>-	0x00000000,
>-	0x780f0000,
>-	0x00000000,
>-	0x78230000,
>-	0x00000e60,
>-	0x78210000,
>-	0x00000e80,
>-	0x7b000005,
>-	0x00000004,
>-	0x00000001,
>-	0x00000000,
>-	0x00000001,
>-	0x00000000,
>-	0x00000000,
>-	0x05000000,	 /* cmds end */
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,	 /* state start */
>-	0x00000000,
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>-	0x3f800000,
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>-	0x00000000,
>-	0x00000000,
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>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,	 /* state end */
>-};
>-
>-RO_RENDERSTATE(8);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_renderstate_gen9.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_renderstate_gen9.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_renderstate_gen9.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_renderstate_gen9.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,999 +0,0 @@
>-/*
>- * Copyright Â© 2014 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>- * DEALINGS IN THE SOFTWARE.
>- *
>- * Generated by: intel-gpu-tools-1.19-177-g68e2eab2
>- */
>-
>-#include "intel_renderstate.h"
>-
>-static const u32 gen9_null_state_relocs[] = {
>-	0x000007a8,
>-	0x000007b4,
>-	0x000007bc,
>-	0x000007cc,
>-	-1,
>-};
>-
>-static const u32 gen9_null_state_batch[] = {
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>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79180006,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79180006,
>-	0x20000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79180006,
>-	0x40000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79180006,
>-	0x60000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x61010011,
>-	0x00000001,	 /* reloc */
>-	0x00000000,
>-	0x00000000,
>-	0x00000001,	 /* reloc */
>-	0x00000000,
>-	0x00000001,	 /* reloc */
>-	0x00000000,
>-	0x00000001,
>-	0x00000000,
>-	0x00000001,	 /* reloc */
>-	0x00000000,
>-	0x00001001,
>-	0x00001001,
>-	0x00000001,
>-	0x00001001,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x61020001,
>-	0x00000000,
>-	0x00000000,
>-	0x79000002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78050006,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79040002,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79040002,
>-	0x40000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79040002,
>-	0x80000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79040002,
>-	0xc0000000,
>-	0x00000000,
>-	0x00000000,
>-	0x79080001,
>-	0x00000000,
>-	0x00000000,
>-	0x790a0001,
>-	0x00000000,
>-	0x00000000,
>-	0x78060003,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78070003,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78040001,
>-	0x00000000,
>-	0x00000000,
>-	0x79110000,
>-	0x00000000,
>-	0x780d0000,
>-	0x00000000,
>-	0x79060000,
>-	0x00000000,
>-	0x7907001f,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x7902000f,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x790c000f,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x780a0003,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78080083,
>-	0x00004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x04004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x08004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x0c004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x10004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x14004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x18004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x1c004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x20004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x24004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x28004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x2c004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x30004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x34004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x38004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x3c004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x40004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x44004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x48004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x4c004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x50004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x54004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x58004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x5c004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x60004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x64004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x68004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x6c004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x70004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x74004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x7c004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x80004000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78090043,
>-	0x02000000,
>-	0x22220000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x78550003,
>-	0x0000000f,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x680b0001,
>-	0x780e0000,
>-	0x00000e01,
>-	0x78240000,
>-	0x00000e41,
>-	0x784f0000,
>-	0x80000100,
>-	0x784d0000,
>-	0x40000000,
>-	0x782b0000,
>-	0x00000000,
>-	0x782c0000,
>-	0x00000000,
>-	0x782d0000,
>-	0x00000000,
>-	0x782e0000,
>-	0x00000000,
>-	0x782f0000,
>-	0x00000000,
>-	0x780f0000,
>-	0x00000000,
>-	0x78230000,
>-	0x00000ea0,
>-	0x78210000,
>-	0x00000ec0,
>-	0x78260000,
>-	0x00000000,
>-	0x78270000,
>-	0x00000000,
>-	0x78280000,
>-	0x00000000,
>-	0x78290000,
>-	0x00000000,
>-	0x782a0000,
>-	0x00000000,
>-	0x7b000005,
>-	0x00000004,
>-	0x00000001,
>-	0x00000000,
>-	0x00000001,
>-	0x00000000,
>-	0x00000000,
>-	0x05000000,	 /* cmds end */
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,	 /* state start */
>-	0x00000000,
>-	0x3f800000,
>-	0x3f800000,
>-	0x3f800000,
>-	0x3f800000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,
>-	0x00000000,	 /* state end */
>-};
>-
>-RO_RENDERSTATE(9);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_renderstate.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_renderstate.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_renderstate.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_renderstate.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,47 +0,0 @@
>-/*
>- * Copyright Â© 2014 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>- * DEALINGS IN THE SOFTWARE.
>- */
>-
>-#ifndef _INTEL_RENDERSTATE_H
>-#define _INTEL_RENDERSTATE_H
>-
>-#include <linux/types.h>
>-
>-struct intel_renderstate_rodata {
>-	const u32 *reloc;
>-	const u32 *batch;
>-	const u32 batch_items;
>-};
>-
>-#define RO_RENDERSTATE(_g)						\
>-	const struct intel_renderstate_rodata gen ## _g ## _null_state = { \
>-		.reloc = gen ## _g ## _null_state_relocs,		\
>-		.batch = gen ## _g ## _null_state_batch,		\
>-		.batch_items = sizeof(gen ## _g ## _null_state_batch)/4, \
>-	}
>-
>-extern const struct intel_renderstate_rodata gen6_null_state;
>-extern const struct intel_renderstate_rodata gen7_null_state;
>-extern const struct intel_renderstate_rodata gen8_null_state;
>-extern const struct intel_renderstate_rodata gen9_null_state;
>-
>-#endif /* INTEL_RENDERSTATE_H */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_runtime_pm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_runtime_pm.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_runtime_pm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_runtime_pm.c	2019-08-31 15:01:12.039736184 -0500
>@@ -592,7 +592,7 @@
> 		pm_runtime_put(kdev);
> }
> 
>-void intel_runtime_pm_cleanup(struct intel_runtime_pm *rpm)
>+void intel_runtime_pm_driver_release(struct intel_runtime_pm *rpm)
> {
> 	int count = atomic_read(&rpm->wakeref_count);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_runtime_pm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_runtime_pm.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_runtime_pm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_runtime_pm.h	2019-08-31 15:01:12.039736184 -0500
>@@ -173,7 +173,7 @@
> void intel_runtime_pm_init_early(struct intel_runtime_pm *rpm);
> void intel_runtime_pm_enable(struct intel_runtime_pm *rpm);
> void intel_runtime_pm_disable(struct intel_runtime_pm *rpm);
>-void intel_runtime_pm_cleanup(struct intel_runtime_pm *rpm);
>+void intel_runtime_pm_driver_release(struct intel_runtime_pm *rpm);
> 
> intel_wakeref_t intel_runtime_pm_get(struct intel_runtime_pm *rpm);
> intel_wakeref_t intel_runtime_pm_get_if_in_use(struct intel_runtime_pm *rpm);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_uc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_uc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_uc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_uc.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,561 +0,0 @@
>-/*
>- * Copyright Â© 2016 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#include "gt/intel_reset.h"
>-#include "intel_uc.h"
>-#include "intel_guc.h"
>-#include "intel_guc_ads.h"
>-#include "intel_guc_submission.h"
>-#include "i915_drv.h"
>-
>-static void guc_free_load_err_log(struct intel_guc *guc);
>-
>-/* Reset GuC providing us with fresh state for both GuC and HuC.
>- */
>-static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
>-{
>-	int ret;
>-	u32 guc_status;
>-
>-	ret = intel_reset_guc(dev_priv);
>-	if (ret) {
>-		DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
>-		return ret;
>-	}
>-
>-	guc_status = I915_READ(GUC_STATUS);
>-	WARN(!(guc_status & GS_MIA_IN_RESET),
>-	     "GuC status: 0x%x, MIA core expected to be in reset\n",
>-	     guc_status);
>-
>-	return ret;
>-}
>-
>-static int __get_platform_enable_guc(struct drm_i915_private *i915)
>-{
>-	struct intel_uc_fw *guc_fw = &i915->guc.fw;
>-	struct intel_uc_fw *huc_fw = &i915->huc.fw;
>-	int enable_guc = 0;
>-
>-	/* Default is to use HuC if we know GuC and HuC firmwares */
>-	if (intel_uc_fw_is_selected(guc_fw) && intel_uc_fw_is_selected(huc_fw))
>-		enable_guc |= ENABLE_GUC_LOAD_HUC;
>-
>-	/* Any platform specific fine-tuning can be done here */
>-
>-	return enable_guc;
>-}
>-
>-static int __get_default_guc_log_level(struct drm_i915_private *i915)
>-{
>-	int guc_log_level;
>-
>-	if (!HAS_GUC(i915) || !intel_uc_is_using_guc(i915))
>-		guc_log_level = GUC_LOG_LEVEL_DISABLED;
>-	else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
>-		 IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
>-		guc_log_level = GUC_LOG_LEVEL_MAX;
>-	else
>-		guc_log_level = GUC_LOG_LEVEL_NON_VERBOSE;
>-
>-	/* Any platform specific fine-tuning can be done here */
>-
>-	return guc_log_level;
>-}
>-
>-/**
>- * sanitize_options_early - sanitize uC related modparam options
>- * @i915: device private
>- *
>- * In case of "enable_guc" option this function will attempt to modify
>- * it only if it was initially set to "auto(-1)". Default value for this
>- * modparam varies between platforms and it is hardcoded in driver code.
>- * Any other modparam value is only monitored against availability of the
>- * related hardware or firmware definitions.
>- *
>- * In case of "guc_log_level" option this function will attempt to modify
>- * it only if it was initially set to "auto(-1)" or if initial value was
>- * "enable(1..4)" on platforms without the GuC. Default value for this
>- * modparam varies between platforms and is usually set to "disable(0)"
>- * unless GuC is enabled on given platform and the driver is compiled with
>- * debug config when this modparam will default to "enable(1..4)".
>- */
>-static void sanitize_options_early(struct drm_i915_private *i915)
>-{
>-	struct intel_uc_fw *guc_fw = &i915->guc.fw;
>-	struct intel_uc_fw *huc_fw = &i915->huc.fw;
>-
>-	/* A negative value means "use platform default" */
>-	if (i915_modparams.enable_guc < 0)
>-		i915_modparams.enable_guc = __get_platform_enable_guc(i915);
>-
>-	DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
>-			 i915_modparams.enable_guc,
>-			 yesno(intel_uc_is_using_guc_submission(i915)),
>-			 yesno(intel_uc_is_using_huc(i915)));
>-
>-	/* Verify GuC firmware availability */
>-	if (intel_uc_is_using_guc(i915) && !intel_uc_fw_is_selected(guc_fw)) {
>-		DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
>-			 "enable_guc", i915_modparams.enable_guc,
>-			 !HAS_GUC(i915) ? "no GuC hardware" :
>-					  "no GuC firmware");
>-	}
>-
>-	/* Verify HuC firmware availability */
>-	if (intel_uc_is_using_huc(i915) && !intel_uc_fw_is_selected(huc_fw)) {
>-		DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
>-			 "enable_guc", i915_modparams.enable_guc,
>-			 !HAS_HUC(i915) ? "no HuC hardware" :
>-					  "no HuC firmware");
>-	}
>-
>-	/* XXX: GuC submission is unavailable for now */
>-	if (intel_uc_is_using_guc_submission(i915)) {
>-		DRM_INFO("Incompatible option detected: %s=%d, %s!\n",
>-			 "enable_guc", i915_modparams.enable_guc,
>-			 "GuC submission not supported");
>-		DRM_INFO("Switching to non-GuC submission mode!\n");
>-		i915_modparams.enable_guc &= ~ENABLE_GUC_SUBMISSION;
>-	}
>-
>-	/* A negative value means "use platform/config default" */
>-	if (i915_modparams.guc_log_level < 0)
>-		i915_modparams.guc_log_level =
>-			__get_default_guc_log_level(i915);
>-
>-	if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc(i915)) {
>-		DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
>-			 "guc_log_level", i915_modparams.guc_log_level,
>-			 !HAS_GUC(i915) ? "no GuC hardware" :
>-					  "GuC not enabled");
>-		i915_modparams.guc_log_level = 0;
>-	}
>-
>-	if (i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX) {
>-		DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
>-			 "guc_log_level", i915_modparams.guc_log_level,
>-			 "verbosity too high");
>-		i915_modparams.guc_log_level = GUC_LOG_LEVEL_MAX;
>-	}
>-
>-	DRM_DEBUG_DRIVER("guc_log_level=%d (enabled:%s, verbose:%s, verbosity:%d)\n",
>-			 i915_modparams.guc_log_level,
>-			 yesno(i915_modparams.guc_log_level),
>-			 yesno(GUC_LOG_LEVEL_IS_VERBOSE(i915_modparams.guc_log_level)),
>-			 GUC_LOG_LEVEL_TO_VERBOSITY(i915_modparams.guc_log_level));
>-
>-	/* Make sure that sanitization was done */
>-	GEM_BUG_ON(i915_modparams.enable_guc < 0);
>-	GEM_BUG_ON(i915_modparams.guc_log_level < 0);
>-}
>-
>-void intel_uc_init_early(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-	struct intel_huc *huc = &i915->huc;
>-
>-	intel_guc_init_early(guc);
>-	intel_huc_init_early(huc);
>-
>-	sanitize_options_early(i915);
>-}
>-
>-void intel_uc_cleanup_early(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-
>-	guc_free_load_err_log(guc);
>-}
>-
>-/**
>- * intel_uc_init_mmio - setup uC MMIO access
>- * @i915: device private
>- *
>- * Setup minimal state necessary for MMIO accesses later in the
>- * initialization sequence.
>- */
>-void intel_uc_init_mmio(struct drm_i915_private *i915)
>-{
>-	intel_guc_init_send_regs(&i915->guc);
>-}
>-
>-static void guc_capture_load_err_log(struct intel_guc *guc)
>-{
>-	if (!guc->log.vma || !intel_guc_log_get_level(&guc->log))
>-		return;
>-
>-	if (!guc->load_err_log)
>-		guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
>-
>-	return;
>-}
>-
>-static void guc_free_load_err_log(struct intel_guc *guc)
>-{
>-	if (guc->load_err_log)
>-		i915_gem_object_put(guc->load_err_log);
>-}
>-
>-static void guc_reset_interrupts(struct intel_guc *guc)
>-{
>-	guc->interrupts.reset(guc_to_i915(guc));
>-}
>-
>-static void guc_enable_interrupts(struct intel_guc *guc)
>-{
>-	guc->interrupts.enable(guc_to_i915(guc));
>-}
>-
>-static void guc_disable_interrupts(struct intel_guc *guc)
>-{
>-	guc->interrupts.disable(guc_to_i915(guc));
>-}
>-
>-static int guc_enable_communication(struct intel_guc *guc)
>-{
>-	guc_enable_interrupts(guc);
>-
>-	return intel_guc_ct_enable(&guc->ct);
>-}
>-
>-static void guc_stop_communication(struct intel_guc *guc)
>-{
>-	intel_guc_ct_stop(&guc->ct);
>-
>-	guc->send = intel_guc_send_nop;
>-	guc->handler = intel_guc_to_host_event_handler_nop;
>-}
>-
>-static void guc_disable_communication(struct intel_guc *guc)
>-{
>-	intel_guc_ct_disable(&guc->ct);
>-
>-	guc_disable_interrupts(guc);
>-
>-	guc->send = intel_guc_send_nop;
>-	guc->handler = intel_guc_to_host_event_handler_nop;
>-}
>-
>-int intel_uc_init_misc(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-	struct intel_huc *huc = &i915->huc;
>-	int ret;
>-
>-	if (!USES_GUC(i915))
>-		return 0;
>-
>-	ret = intel_guc_init_misc(guc);
>-	if (ret)
>-		return ret;
>-
>-	if (USES_HUC(i915)) {
>-		ret = intel_huc_init_misc(huc);
>-		if (ret)
>-			goto err_guc;
>-	}
>-
>-	return 0;
>-
>-err_guc:
>-	intel_guc_fini_misc(guc);
>-	return ret;
>-}
>-
>-void intel_uc_fini_misc(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-	struct intel_huc *huc = &i915->huc;
>-
>-	if (!USES_GUC(i915))
>-		return;
>-
>-	if (USES_HUC(i915))
>-		intel_huc_fini_misc(huc);
>-
>-	intel_guc_fini_misc(guc);
>-}
>-
>-int intel_uc_init(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-	struct intel_huc *huc = &i915->huc;
>-	int ret;
>-
>-	if (!USES_GUC(i915))
>-		return 0;
>-
>-	if (!HAS_GUC(i915))
>-		return -ENODEV;
>-
>-	/* XXX: GuC submission is unavailable for now */
>-	GEM_BUG_ON(USES_GUC_SUBMISSION(i915));
>-
>-	ret = intel_guc_init(guc);
>-	if (ret)
>-		return ret;
>-
>-	if (USES_HUC(i915)) {
>-		ret = intel_huc_init(huc);
>-		if (ret)
>-			goto err_guc;
>-	}
>-
>-	if (USES_GUC_SUBMISSION(i915)) {
>-		/*
>-		 * This is stuff we need to have available at fw load time
>-		 * if we are planning to enable submission later
>-		 */
>-		ret = intel_guc_submission_init(guc);
>-		if (ret)
>-			goto err_huc;
>-	}
>-
>-	return 0;
>-
>-err_huc:
>-	if (USES_HUC(i915))
>-		intel_huc_fini(huc);
>-err_guc:
>-	intel_guc_fini(guc);
>-	return ret;
>-}
>-
>-void intel_uc_fini(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-
>-	if (!USES_GUC(i915))
>-		return;
>-
>-	GEM_BUG_ON(!HAS_GUC(i915));
>-
>-	if (USES_GUC_SUBMISSION(i915))
>-		intel_guc_submission_fini(guc);
>-
>-	if (USES_HUC(i915))
>-		intel_huc_fini(&i915->huc);
>-
>-	intel_guc_fini(guc);
>-}
>-
>-static void __uc_sanitize(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-	struct intel_huc *huc = &i915->huc;
>-
>-	GEM_BUG_ON(!HAS_GUC(i915));
>-
>-	intel_huc_sanitize(huc);
>-	intel_guc_sanitize(guc);
>-
>-	__intel_uc_reset_hw(i915);
>-}
>-
>-void intel_uc_sanitize(struct drm_i915_private *i915)
>-{
>-	if (!USES_GUC(i915))
>-		return;
>-
>-	__uc_sanitize(i915);
>-}
>-
>-int intel_uc_init_hw(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-	struct intel_huc *huc = &i915->huc;
>-	int ret, attempts;
>-
>-	if (!USES_GUC(i915))
>-		return 0;
>-
>-	GEM_BUG_ON(!HAS_GUC(i915));
>-
>-	guc_reset_interrupts(guc);
>-
>-	/* WaEnableuKernelHeaderValidFix:skl */
>-	/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
>-	if (IS_GEN(i915, 9))
>-		attempts = 3;
>-	else
>-		attempts = 1;
>-
>-	while (attempts--) {
>-		/*
>-		 * Always reset the GuC just before (re)loading, so
>-		 * that the state and timing are fairly predictable
>-		 */
>-		ret = __intel_uc_reset_hw(i915);
>-		if (ret)
>-			goto err_out;
>-
>-		if (USES_HUC(i915)) {
>-			ret = intel_huc_fw_upload(huc);
>-			if (ret)
>-				goto err_out;
>-		}
>-
>-		intel_guc_ads_reset(guc);
>-		intel_guc_init_params(guc);
>-		ret = intel_guc_fw_upload(guc);
>-		if (ret == 0)
>-			break;
>-
>-		DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
>-				 "retry %d more time(s)\n", ret, attempts);
>-	}
>-
>-	/* Did we succeded or run out of retries? */
>-	if (ret)
>-		goto err_log_capture;
>-
>-	ret = guc_enable_communication(guc);
>-	if (ret)
>-		goto err_log_capture;
>-
>-	if (USES_HUC(i915)) {
>-		ret = intel_huc_auth(huc);
>-		if (ret)
>-			goto err_communication;
>-	}
>-
>-	ret = intel_guc_sample_forcewake(guc);
>-	if (ret)
>-		goto err_communication;
>-
>-	if (USES_GUC_SUBMISSION(i915)) {
>-		ret = intel_guc_submission_enable(guc);
>-		if (ret)
>-			goto err_communication;
>-	}
>-
>-	dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
>-		 guc->fw.major_ver_found, guc->fw.minor_ver_found);
>-	dev_info(i915->drm.dev, "GuC submission %s\n",
>-		 enableddisabled(USES_GUC_SUBMISSION(i915)));
>-	dev_info(i915->drm.dev, "HuC %s\n",
>-		 enableddisabled(USES_HUC(i915)));
>-
>-	return 0;
>-
>-	/*
>-	 * We've failed to load the firmware :(
>-	 */
>-err_communication:
>-	guc_disable_communication(guc);
>-err_log_capture:
>-	guc_capture_load_err_log(guc);
>-err_out:
>-	__uc_sanitize(i915);
>-
>-	/*
>-	 * Note that there is no fallback as either user explicitly asked for
>-	 * the GuC or driver default option was to run with the GuC enabled.
>-	 */
>-	if (GEM_WARN_ON(ret == -EIO))
>-		ret = -EINVAL;
>-
>-	dev_err(i915->drm.dev, "GuC initialization failed %d\n", ret);
>-	return ret;
>-}
>-
>-void intel_uc_fini_hw(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-
>-	if (!intel_guc_is_loaded(guc))
>-		return;
>-
>-	GEM_BUG_ON(!HAS_GUC(i915));
>-
>-	if (USES_GUC_SUBMISSION(i915))
>-		intel_guc_submission_disable(guc);
>-
>-	guc_disable_communication(guc);
>-	__uc_sanitize(i915);
>-}
>-
>-/**
>- * intel_uc_reset_prepare - Prepare for reset
>- * @i915: device private
>- *
>- * Preparing for full gpu reset.
>- */
>-void intel_uc_reset_prepare(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-
>-	if (!intel_guc_is_loaded(guc))
>-		return;
>-
>-	guc_stop_communication(guc);
>-	__uc_sanitize(i915);
>-}
>-
>-void intel_uc_runtime_suspend(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-	int err;
>-
>-	if (!intel_guc_is_loaded(guc))
>-		return;
>-
>-	err = intel_guc_suspend(guc);
>-	if (err)
>-		DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
>-
>-	guc_disable_communication(guc);
>-}
>-
>-void intel_uc_suspend(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-	intel_wakeref_t wakeref;
>-
>-	if (!intel_guc_is_loaded(guc))
>-		return;
>-
>-	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
>-		intel_uc_runtime_suspend(i915);
>-}
>-
>-int intel_uc_resume(struct drm_i915_private *i915)
>-{
>-	struct intel_guc *guc = &i915->guc;
>-	int err;
>-
>-	if (!intel_guc_is_loaded(guc))
>-		return 0;
>-
>-	guc_enable_communication(guc);
>-
>-	err = intel_guc_resume(guc);
>-	if (err) {
>-		DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
>-		return err;
>-	}
>-
>-	return 0;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_uc_fw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_uc_fw.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_uc_fw.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_uc_fw.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,357 +0,0 @@
>-/*
>- * Copyright Â© 2016-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#include <linux/bitfield.h>
>-#include <linux/firmware.h>
>-#include <drm/drm_print.h>
>-
>-#include "intel_uc_fw.h"
>-#include "i915_drv.h"
>-
>-/**
>- * intel_uc_fw_fetch - fetch uC firmware
>- *
>- * @dev_priv: device private
>- * @uc_fw: uC firmware
>- *
>- * Fetch uC firmware into GEM obj.
>- */
>-void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>-		       struct intel_uc_fw *uc_fw)
>-{
>-	struct pci_dev *pdev = dev_priv->drm.pdev;
>-	struct drm_i915_gem_object *obj;
>-	const struct firmware *fw = NULL;
>-	struct uc_css_header *css;
>-	size_t size;
>-	int err;
>-
>-	if (!uc_fw->path) {
>-		dev_info(dev_priv->drm.dev,
>-			 "%s: No firmware was defined for %s!\n",
>-			 intel_uc_fw_type_repr(uc_fw->type),
>-			 intel_platform_name(INTEL_INFO(dev_priv)->platform));
>-		return;
>-	}
>-
>-	DRM_DEBUG_DRIVER("%s fw fetch %s\n",
>-			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path);
>-
>-	uc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING;
>-	DRM_DEBUG_DRIVER("%s fw fetch %s\n",
>-			 intel_uc_fw_type_repr(uc_fw->type),
>-			 intel_uc_fw_status_repr(uc_fw->fetch_status));
>-
>-	err = request_firmware(&fw, uc_fw->path, &pdev->dev);
>-	if (err) {
>-		DRM_DEBUG_DRIVER("%s fw request_firmware err=%d\n",
>-				 intel_uc_fw_type_repr(uc_fw->type), err);
>-		goto fail;
>-	}
>-
>-	DRM_DEBUG_DRIVER("%s fw size %zu ptr %p\n",
>-			 intel_uc_fw_type_repr(uc_fw->type), fw->size, fw);
>-
>-	/* Check the size of the blob before examining buffer contents */
>-	if (fw->size < sizeof(struct uc_css_header)) {
>-		DRM_WARN("%s: Unexpected firmware size (%zu, min %zu)\n",
>-			 intel_uc_fw_type_repr(uc_fw->type),
>-			 fw->size, sizeof(struct uc_css_header));
>-		err = -ENODATA;
>-		goto fail;
>-	}
>-
>-	css = (struct uc_css_header *)fw->data;
>-
>-	/* Firmware bits always start from header */
>-	uc_fw->header_offset = 0;
>-	uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
>-			      css->key_size_dw - css->exponent_size_dw) *
>-			     sizeof(u32);
>-
>-	if (uc_fw->header_size != sizeof(struct uc_css_header)) {
>-		DRM_WARN("%s: Mismatched firmware header definition\n",
>-			 intel_uc_fw_type_repr(uc_fw->type));
>-		err = -ENOEXEC;
>-		goto fail;
>-	}
>-
>-	/* then, uCode */
>-	uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
>-	uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
>-
>-	/* now RSA */
>-	if (css->key_size_dw != UOS_RSA_SCRATCH_COUNT) {
>-		DRM_WARN("%s: Mismatched firmware RSA key size (%u)\n",
>-			 intel_uc_fw_type_repr(uc_fw->type), css->key_size_dw);
>-		err = -ENOEXEC;
>-		goto fail;
>-	}
>-	uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
>-	uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
>-
>-	/* At least, it should have header, uCode and RSA. Size of all three. */
>-	size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
>-	if (fw->size < size) {
>-		DRM_WARN("%s: Truncated firmware (%zu, expected %zu)\n",
>-			 intel_uc_fw_type_repr(uc_fw->type), fw->size, size);
>-		err = -ENOEXEC;
>-		goto fail;
>-	}
>-
>-	/* Get version numbers from the CSS header */
>-	switch (uc_fw->type) {
>-	case INTEL_UC_FW_TYPE_GUC:
>-		uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MAJOR,
>-						   css->sw_version);
>-		uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MINOR,
>-						   css->sw_version);
>-		break;
>-
>-	case INTEL_UC_FW_TYPE_HUC:
>-		uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MAJOR,
>-						   css->sw_version);
>-		uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MINOR,
>-						   css->sw_version);
>-		break;
>-
>-	default:
>-		MISSING_CASE(uc_fw->type);
>-		break;
>-	}
>-
>-	DRM_DEBUG_DRIVER("%s fw version %u.%u (wanted %u.%u)\n",
>-			 intel_uc_fw_type_repr(uc_fw->type),
>-			 uc_fw->major_ver_found, uc_fw->minor_ver_found,
>-			 uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
>-
>-	if (uc_fw->major_ver_wanted == 0 && uc_fw->minor_ver_wanted == 0) {
>-		DRM_NOTE("%s: Skipping firmware version check\n",
>-			 intel_uc_fw_type_repr(uc_fw->type));
>-	} else if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
>-		   uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
>-		DRM_NOTE("%s: Wrong firmware version (%u.%u, required %u.%u)\n",
>-			 intel_uc_fw_type_repr(uc_fw->type),
>-			 uc_fw->major_ver_found, uc_fw->minor_ver_found,
>-			 uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted);
>-		err = -ENOEXEC;
>-		goto fail;
>-	}
>-
>-	obj = i915_gem_object_create_shmem_from_data(dev_priv,
>-						     fw->data, fw->size);
>-	if (IS_ERR(obj)) {
>-		err = PTR_ERR(obj);
>-		DRM_DEBUG_DRIVER("%s fw object_create err=%d\n",
>-				 intel_uc_fw_type_repr(uc_fw->type), err);
>-		goto fail;
>-	}
>-
>-	uc_fw->obj = obj;
>-	uc_fw->size = fw->size;
>-	uc_fw->fetch_status = INTEL_UC_FIRMWARE_SUCCESS;
>-	DRM_DEBUG_DRIVER("%s fw fetch %s\n",
>-			 intel_uc_fw_type_repr(uc_fw->type),
>-			 intel_uc_fw_status_repr(uc_fw->fetch_status));
>-
>-	release_firmware(fw);
>-	return;
>-
>-fail:
>-	uc_fw->fetch_status = INTEL_UC_FIRMWARE_FAIL;
>-	DRM_DEBUG_DRIVER("%s fw fetch %s\n",
>-			 intel_uc_fw_type_repr(uc_fw->type),
>-			 intel_uc_fw_status_repr(uc_fw->fetch_status));
>-
>-	DRM_WARN("%s: Failed to fetch firmware %s (error %d)\n",
>-		 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, err);
>-	DRM_INFO("%s: Firmware can be downloaded from %s\n",
>-		 intel_uc_fw_type_repr(uc_fw->type), INTEL_UC_FIRMWARE_URL);
>-
>-	release_firmware(fw);		/* OK even if fw is NULL */
>-}
>-
>-static void intel_uc_fw_ggtt_bind(struct intel_uc_fw *uc_fw)
>-{
>-	struct drm_i915_gem_object *obj = uc_fw->obj;
>-	struct i915_ggtt *ggtt = &to_i915(obj->base.dev)->ggtt;
>-	struct i915_vma dummy = {
>-		.node.start = intel_uc_fw_ggtt_offset(uc_fw),
>-		.node.size = obj->base.size,
>-		.pages = obj->mm.pages,
>-		.vm = &ggtt->vm,
>-	};
>-
>-	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
>-	GEM_BUG_ON(dummy.node.size > ggtt->uc_fw.size);
>-
>-	/* uc_fw->obj cache domains were not controlled across suspend */
>-	drm_clflush_sg(dummy.pages);
>-
>-	ggtt->vm.insert_entries(&ggtt->vm, &dummy, I915_CACHE_NONE, 0);
>-}
>-
>-static void intel_uc_fw_ggtt_unbind(struct intel_uc_fw *uc_fw)
>-{
>-	struct drm_i915_gem_object *obj = uc_fw->obj;
>-	struct i915_ggtt *ggtt = &to_i915(obj->base.dev)->ggtt;
>-	u64 start = intel_uc_fw_ggtt_offset(uc_fw);
>-
>-	ggtt->vm.clear_range(&ggtt->vm, start, obj->base.size);
>-}
>-
>-/**
>- * intel_uc_fw_upload - load uC firmware using custom loader
>- * @uc_fw: uC firmware
>- * @xfer: custom uC firmware loader function
>- *
>- * Loads uC firmware using custom loader and updates internal flags.
>- *
>- * Return: 0 on success, non-zero on failure.
>- */
>-int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
>-		       int (*xfer)(struct intel_uc_fw *uc_fw))
>-{
>-	int err;
>-
>-	DRM_DEBUG_DRIVER("%s fw load %s\n",
>-			 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path);
>-
>-	if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
>-		return -ENOEXEC;
>-
>-	uc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
>-	DRM_DEBUG_DRIVER("%s fw load %s\n",
>-			 intel_uc_fw_type_repr(uc_fw->type),
>-			 intel_uc_fw_status_repr(uc_fw->load_status));
>-
>-	/* Call custom loader */
>-	intel_uc_fw_ggtt_bind(uc_fw);
>-	err = xfer(uc_fw);
>-	intel_uc_fw_ggtt_unbind(uc_fw);
>-	if (err)
>-		goto fail;
>-
>-	uc_fw->load_status = INTEL_UC_FIRMWARE_SUCCESS;
>-	DRM_DEBUG_DRIVER("%s fw load %s\n",
>-			 intel_uc_fw_type_repr(uc_fw->type),
>-			 intel_uc_fw_status_repr(uc_fw->load_status));
>-
>-	DRM_INFO("%s: Loaded firmware %s (version %u.%u)\n",
>-		 intel_uc_fw_type_repr(uc_fw->type),
>-		 uc_fw->path,
>-		 uc_fw->major_ver_found, uc_fw->minor_ver_found);
>-
>-	return 0;
>-
>-fail:
>-	uc_fw->load_status = INTEL_UC_FIRMWARE_FAIL;
>-	DRM_DEBUG_DRIVER("%s fw load %s\n",
>-			 intel_uc_fw_type_repr(uc_fw->type),
>-			 intel_uc_fw_status_repr(uc_fw->load_status));
>-
>-	DRM_WARN("%s: Failed to load firmware %s (error %d)\n",
>-		 intel_uc_fw_type_repr(uc_fw->type), uc_fw->path, err);
>-
>-	return err;
>-}
>-
>-int intel_uc_fw_init(struct intel_uc_fw *uc_fw)
>-{
>-	int err;
>-
>-	if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
>-		return -ENOEXEC;
>-
>-	err = i915_gem_object_pin_pages(uc_fw->obj);
>-	if (err)
>-		DRM_DEBUG_DRIVER("%s fw pin-pages err=%d\n",
>-				 intel_uc_fw_type_repr(uc_fw->type), err);
>-
>-	return err;
>-}
>-
>-void intel_uc_fw_fini(struct intel_uc_fw *uc_fw)
>-{
>-	if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
>-		return;
>-
>-	i915_gem_object_unpin_pages(uc_fw->obj);
>-}
>-
>-u32 intel_uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw)
>-{
>-	struct drm_i915_private *i915 = to_i915(uc_fw->obj->base.dev);
>-	struct i915_ggtt *ggtt = &i915->ggtt;
>-	struct drm_mm_node *node = &ggtt->uc_fw;
>-
>-	GEM_BUG_ON(!node->allocated);
>-	GEM_BUG_ON(upper_32_bits(node->start));
>-	GEM_BUG_ON(upper_32_bits(node->start + node->size - 1));
>-
>-	return lower_32_bits(node->start);
>-}
>-
>-/**
>- * intel_uc_fw_cleanup_fetch - cleanup uC firmware
>- *
>- * @uc_fw: uC firmware
>- *
>- * Cleans up uC firmware by releasing the firmware GEM obj.
>- */
>-void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw)
>-{
>-	struct drm_i915_gem_object *obj;
>-
>-	obj = fetch_and_zero(&uc_fw->obj);
>-	if (obj)
>-		i915_gem_object_put(obj);
>-
>-	uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
>-}
>-
>-/**
>- * intel_uc_fw_dump - dump information about uC firmware
>- * @uc_fw: uC firmware
>- * @p: the &drm_printer
>- *
>- * Pretty printer for uC firmware.
>- */
>-void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p)
>-{
>-	drm_printf(p, "%s firmware: %s\n",
>-		   intel_uc_fw_type_repr(uc_fw->type), uc_fw->path);
>-	drm_printf(p, "\tstatus: fetch %s, load %s\n",
>-		   intel_uc_fw_status_repr(uc_fw->fetch_status),
>-		   intel_uc_fw_status_repr(uc_fw->load_status));
>-	drm_printf(p, "\tversion: wanted %u.%u, found %u.%u\n",
>-		   uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted,
>-		   uc_fw->major_ver_found, uc_fw->minor_ver_found);
>-	drm_printf(p, "\theader: offset %u, size %u\n",
>-		   uc_fw->header_offset, uc_fw->header_size);
>-	drm_printf(p, "\tuCode: offset %u, size %u\n",
>-		   uc_fw->ucode_offset, uc_fw->ucode_size);
>-	drm_printf(p, "\tRSA: offset %u, size %u\n",
>-		   uc_fw->rsa_offset, uc_fw->rsa_size);
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_uc_fw.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_uc_fw.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_uc_fw.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_uc_fw.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,155 +0,0 @@
>-/*
>- * Copyright Â© 2014-2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#ifndef _INTEL_UC_FW_H_
>-#define _INTEL_UC_FW_H_
>-
>-struct drm_printer;
>-struct drm_i915_private;
>-
>-/* Home of GuC, HuC and DMC firmwares */
>-#define INTEL_UC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915"
>-
>-enum intel_uc_fw_status {
>-	INTEL_UC_FIRMWARE_FAIL = -1,
>-	INTEL_UC_FIRMWARE_NONE = 0,
>-	INTEL_UC_FIRMWARE_PENDING,
>-	INTEL_UC_FIRMWARE_SUCCESS
>-};
>-
>-enum intel_uc_fw_type {
>-	INTEL_UC_FW_TYPE_GUC,
>-	INTEL_UC_FW_TYPE_HUC
>-};
>-
>-/*
>- * This structure encapsulates all the data needed during the process
>- * of fetching, caching, and loading the firmware image into the uC.
>- */
>-struct intel_uc_fw {
>-	const char *path;
>-	size_t size;
>-	struct drm_i915_gem_object *obj;
>-	enum intel_uc_fw_status fetch_status;
>-	enum intel_uc_fw_status load_status;
>-
>-	/*
>-	 * The firmware build process will generate a version header file with major and
>-	 * minor version defined. The versions are built into CSS header of firmware.
>-	 * i915 kernel driver set the minimal firmware version required per platform.
>-	 */
>-	u16 major_ver_wanted;
>-	u16 minor_ver_wanted;
>-	u16 major_ver_found;
>-	u16 minor_ver_found;
>-
>-	enum intel_uc_fw_type type;
>-	u32 header_size;
>-	u32 header_offset;
>-	u32 rsa_size;
>-	u32 rsa_offset;
>-	u32 ucode_size;
>-	u32 ucode_offset;
>-};
>-
>-static inline
>-const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
>-{
>-	switch (status) {
>-	case INTEL_UC_FIRMWARE_FAIL:
>-		return "FAIL";
>-	case INTEL_UC_FIRMWARE_NONE:
>-		return "NONE";
>-	case INTEL_UC_FIRMWARE_PENDING:
>-		return "PENDING";
>-	case INTEL_UC_FIRMWARE_SUCCESS:
>-		return "SUCCESS";
>-	}
>-	return "<invalid>";
>-}
>-
>-static inline const char *intel_uc_fw_type_repr(enum intel_uc_fw_type type)
>-{
>-	switch (type) {
>-	case INTEL_UC_FW_TYPE_GUC:
>-		return "GuC";
>-	case INTEL_UC_FW_TYPE_HUC:
>-		return "HuC";
>-	}
>-	return "uC";
>-}
>-
>-static inline
>-void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
>-			    enum intel_uc_fw_type type)
>-{
>-	uc_fw->path = NULL;
>-	uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
>-	uc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
>-	uc_fw->type = type;
>-}
>-
>-static inline bool intel_uc_fw_is_selected(struct intel_uc_fw *uc_fw)
>-{
>-	return uc_fw->path != NULL;
>-}
>-
>-static inline bool intel_uc_fw_is_loaded(struct intel_uc_fw *uc_fw)
>-{
>-	return uc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS;
>-}
>-
>-static inline void intel_uc_fw_sanitize(struct intel_uc_fw *uc_fw)
>-{
>-	if (intel_uc_fw_is_loaded(uc_fw))
>-		uc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
>-}
>-
>-/**
>- * intel_uc_fw_get_upload_size() - Get size of firmware needed to be uploaded.
>- * @uc_fw: uC firmware.
>- *
>- * Get the size of the firmware and header that will be uploaded to WOPCM.
>- *
>- * Return: Upload firmware size, or zero on firmware fetch failure.
>- */
>-static inline u32 intel_uc_fw_get_upload_size(struct intel_uc_fw *uc_fw)
>-{
>-	if (uc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS)
>-		return 0;
>-
>-	return uc_fw->header_size + uc_fw->ucode_size;
>-}
>-
>-void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>-		       struct intel_uc_fw *uc_fw);
>-void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw);
>-int intel_uc_fw_upload(struct intel_uc_fw *uc_fw,
>-		       int (*xfer)(struct intel_uc_fw *uc_fw));
>-int intel_uc_fw_init(struct intel_uc_fw *uc_fw);
>-void intel_uc_fw_fini(struct intel_uc_fw *uc_fw);
>-u32 intel_uc_fw_ggtt_offset(struct intel_uc_fw *uc_fw);
>-void intel_uc_fw_dump(const struct intel_uc_fw *uc_fw, struct drm_printer *p);
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_uc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_uc.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_uc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_uc.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,64 +0,0 @@
>-/*
>- * Copyright Â© 2014 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-#ifndef _INTEL_UC_H_
>-#define _INTEL_UC_H_
>-
>-#include "intel_guc.h"
>-#include "intel_huc.h"
>-#include "i915_params.h"
>-
>-void intel_uc_init_early(struct drm_i915_private *dev_priv);
>-void intel_uc_cleanup_early(struct drm_i915_private *dev_priv);
>-void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
>-int intel_uc_init_misc(struct drm_i915_private *dev_priv);
>-void intel_uc_fini_misc(struct drm_i915_private *dev_priv);
>-void intel_uc_sanitize(struct drm_i915_private *dev_priv);
>-int intel_uc_init_hw(struct drm_i915_private *dev_priv);
>-void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
>-int intel_uc_init(struct drm_i915_private *dev_priv);
>-void intel_uc_fini(struct drm_i915_private *dev_priv);
>-void intel_uc_reset_prepare(struct drm_i915_private *i915);
>-void intel_uc_suspend(struct drm_i915_private *i915);
>-void intel_uc_runtime_suspend(struct drm_i915_private *i915);
>-int intel_uc_resume(struct drm_i915_private *dev_priv);
>-
>-static inline bool intel_uc_is_using_guc(struct drm_i915_private *i915)
>-{
>-	GEM_BUG_ON(i915_modparams.enable_guc < 0);
>-	return i915_modparams.enable_guc > 0;
>-}
>-
>-static inline bool intel_uc_is_using_guc_submission(struct drm_i915_private *i915)
>-{
>-	GEM_BUG_ON(i915_modparams.enable_guc < 0);
>-	return i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION;
>-}
>-
>-static inline bool intel_uc_is_using_huc(struct drm_i915_private *i915)
>-{
>-	GEM_BUG_ON(i915_modparams.enable_guc < 0);
>-	return i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC;
>-}
>-
>-#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_uncore.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_uncore.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_uncore.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_uncore.c	2019-08-31 15:01:12.039736184 -0500
>@@ -78,6 +78,8 @@
> static inline void
> fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
> {
>+	GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask);
>+	d->uncore->fw_domains_timer |= d->mask;
> 	d->wake_count++;
> 	hrtimer_start_range_ns(&d->timer,
> 			       NSEC_PER_MSEC,
>@@ -322,7 +324,7 @@
> 
> 	/* On VLV, FIFO will be shared by both SW and HW.
> 	 * So, we need to read the FREE_ENTRIES everytime */
>-	if (IS_VALLEYVIEW(uncore_to_i915(uncore)))
>+	if (IS_VALLEYVIEW(uncore->i915))
> 		n = fifo_free_entries(uncore);
> 	else
> 		n = uncore->fifo_count;
>@@ -344,7 +346,7 @@
> {
> 	struct intel_uncore_forcewake_domain *domain =
> 	       container_of(timer, struct intel_uncore_forcewake_domain, timer);
>-	struct intel_uncore *uncore = forcewake_domain_to_uncore(domain);
>+	struct intel_uncore *uncore = domain->uncore;
> 	unsigned long irqflags;
> 
> 	assert_rpm_device_not_suspended(uncore->rpm);
>@@ -353,9 +355,10 @@
> 		return HRTIMER_RESTART;
> 
> 	spin_lock_irqsave(&uncore->lock, irqflags);
>-	if (WARN_ON(domain->wake_count == 0))
>-		domain->wake_count++;
> 
>+	uncore->fw_domains_timer &= ~domain->mask;
>+
>+	GEM_BUG_ON(!domain->wake_count);
> 	if (--domain->wake_count == 0)
> 		uncore->funcs.force_wake_put(uncore, domain->mask);
> 
>@@ -485,15 +488,13 @@
> 	return ret;
> }
> 
>-static void __intel_uncore_early_sanitize(struct intel_uncore *uncore,
>-					  unsigned int restore_forcewake)
>+static void forcewake_early_sanitize(struct intel_uncore *uncore,
>+				     unsigned int restore_forcewake)
> {
>-	/* clear out unclaimed reg detection bit */
>-	if (check_for_unclaimed_mmio(uncore))
>-		DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
>+	GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
> 
> 	/* WaDisableShadowRegForCpd:chv */
>-	if (IS_CHERRYVIEW(uncore_to_i915(uncore))) {
>+	if (IS_CHERRYVIEW(uncore->i915)) {
> 		__raw_uncore_write32(uncore, GTFIFOCTL,
> 				     __raw_uncore_read32(uncore, GTFIFOCTL) |
> 				     GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
>@@ -515,6 +516,9 @@
> 
> void intel_uncore_suspend(struct intel_uncore *uncore)
> {
>+	if (!intel_uncore_has_forcewake(uncore))
>+		return;
>+
> 	iosf_mbi_punit_acquire();
> 	iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
> 		&uncore->pmic_bus_access_nb);
>@@ -526,21 +530,24 @@
> {
> 	unsigned int restore_forcewake;
> 
>+	if (intel_uncore_unclaimed_mmio(uncore))
>+		DRM_DEBUG("unclaimed mmio detected on resume, clearing\n");
>+
>+	if (!intel_uncore_has_forcewake(uncore))
>+		return;
>+
> 	restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved);
>-	__intel_uncore_early_sanitize(uncore, restore_forcewake);
>+	forcewake_early_sanitize(uncore, restore_forcewake);
> 
> 	iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
> }
> 
> void intel_uncore_runtime_resume(struct intel_uncore *uncore)
> {
>-	iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
>-}
>+	if (!intel_uncore_has_forcewake(uncore))
>+		return;
> 
>-void intel_uncore_sanitize(struct drm_i915_private *dev_priv)
>-{
>-	/* BIOS often leaves RC6 enabled, but disable it for hw init */
>-	intel_sanitize_gt_powersave(dev_priv);
>+	iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
> }
> 
> static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,
>@@ -628,7 +635,7 @@
> 	spin_lock_irq(&uncore->lock);
> 	if (!--uncore->user_forcewake.count) {
> 		if (intel_uncore_unclaimed_mmio(uncore))
>-			dev_info(uncore_to_i915(uncore)->drm.dev,
>+			dev_info(uncore->i915->drm.dev,
> 				 "Invalid mmio detected during user access\n");
> 
> 		uncore->unclaimed_mmio_check =
>@@ -669,8 +676,7 @@
> 	fw_domains &= uncore->fw_domains;
> 
> 	for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
>-		if (WARN_ON(domain->wake_count == 0))
>-			continue;
>+		GEM_BUG_ON(!domain->wake_count);
> 
> 		if (--domain->wake_count) {
> 			domain->active = true;
>@@ -734,15 +740,42 @@
> void assert_forcewakes_active(struct intel_uncore *uncore,
> 			      enum forcewake_domains fw_domains)
> {
>+	struct intel_uncore_forcewake_domain *domain;
>+	unsigned int tmp;
>+
>+	if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
>+		return;
>+
> 	if (!uncore->funcs.force_wake_get)
> 		return;
> 
>+	spin_lock_irq(&uncore->lock);
>+
> 	assert_rpm_wakelock_held(uncore->rpm);
> 
> 	fw_domains &= uncore->fw_domains;
> 	WARN(fw_domains & ~uncore->fw_domains_active,
> 	     "Expected %08x fw_domains to be active, but %08x are off\n",
> 	     fw_domains, fw_domains & ~uncore->fw_domains_active);
>+
>+	/*
>+	 * Check that the caller has an explicit wakeref and we don't mistake
>+	 * it for the auto wakeref.
>+	 */
>+	for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
>+		unsigned int actual = READ_ONCE(domain->wake_count);
>+		unsigned int expect = 1;
>+
>+		if (uncore->fw_domains_timer & domain->mask)
>+			expect++; /* pending automatic release */
>+
>+		if (WARN(actual < expect,
>+			 "Expected domain %d to be held awake by caller, count=%d\n",
>+			 domain->id, actual))
>+			break;
>+	}
>+
>+	spin_unlock_irq(&uncore->lock);
> }
> 
> /* We give fast paths for the really cool registers */
>@@ -901,6 +934,12 @@
> __is_genX_shadowed(8)
> __is_genX_shadowed(11)
> 
>+static enum forcewake_domains
>+gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
>+{
>+	return FORCEWAKE_RENDER;
>+}
>+
> #define __gen8_reg_write_fw_domains(uncore, offset) \
> ({ \
> 	enum forcewake_domains __fwd; \
>@@ -1123,8 +1162,7 @@
> static inline void __force_wake_auto(struct intel_uncore *uncore,
> 				     enum forcewake_domains fw_domains)
> {
>-	if (WARN_ON(!fw_domains))
>-		return;
>+	GEM_BUG_ON(!fw_domains);
> 
> 	/* Turn on all requested but inactive supported forcewake domains. */
> 	fw_domains &= uncore->fw_domains;
>@@ -1145,26 +1183,23 @@
> 	val = __raw_uncore_read##x(uncore, reg); \
> 	GEN6_READ_FOOTER; \
> }
>-#define __gen6_read(x) __gen_read(gen6, x)
>-#define __fwtable_read(x) __gen_read(fwtable, x)
>-#define __gen11_fwtable_read(x) __gen_read(gen11_fwtable, x)
>-
>-__gen11_fwtable_read(8)
>-__gen11_fwtable_read(16)
>-__gen11_fwtable_read(32)
>-__gen11_fwtable_read(64)
>-__fwtable_read(8)
>-__fwtable_read(16)
>-__fwtable_read(32)
>-__fwtable_read(64)
>-__gen6_read(8)
>-__gen6_read(16)
>-__gen6_read(32)
>-__gen6_read(64)
>-
>-#undef __gen11_fwtable_read
>-#undef __fwtable_read
>-#undef __gen6_read
>+
>+#define __gen_reg_read_funcs(func) \
>+static enum forcewake_domains \
>+func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
>+	return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
>+} \
>+\
>+__gen_read(func, 8) \
>+__gen_read(func, 16) \
>+__gen_read(func, 32) \
>+__gen_read(func, 64)
>+
>+__gen_reg_read_funcs(gen11_fwtable);
>+__gen_reg_read_funcs(fwtable);
>+__gen_reg_read_funcs(gen6);
>+
>+#undef __gen_reg_read_funcs
> #undef GEN6_READ_FOOTER
> #undef GEN6_READ_HEADER
> 
>@@ -1225,6 +1260,9 @@
> 	__raw_uncore_write##x(uncore, reg, val); \
> 	GEN6_WRITE_FOOTER; \
> }
>+__gen6_write(8)
>+__gen6_write(16)
>+__gen6_write(32)
> 
> #define __gen_write(func, x) \
> static void \
>@@ -1237,38 +1275,33 @@
> 	__raw_uncore_write##x(uncore, reg, val); \
> 	GEN6_WRITE_FOOTER; \
> }
>-#define __gen8_write(x) __gen_write(gen8, x)
>-#define __fwtable_write(x) __gen_write(fwtable, x)
>-#define __gen11_fwtable_write(x) __gen_write(gen11_fwtable, x)
>-
>-__gen11_fwtable_write(8)
>-__gen11_fwtable_write(16)
>-__gen11_fwtable_write(32)
>-__fwtable_write(8)
>-__fwtable_write(16)
>-__fwtable_write(32)
>-__gen8_write(8)
>-__gen8_write(16)
>-__gen8_write(32)
>-__gen6_write(8)
>-__gen6_write(16)
>-__gen6_write(32)
> 
>-#undef __gen11_fwtable_write
>-#undef __fwtable_write
>-#undef __gen8_write
>-#undef __gen6_write
>+#define __gen_reg_write_funcs(func) \
>+static enum forcewake_domains \
>+func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \
>+	return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \
>+} \
>+\
>+__gen_write(func, 8) \
>+__gen_write(func, 16) \
>+__gen_write(func, 32)
>+
>+__gen_reg_write_funcs(gen11_fwtable);
>+__gen_reg_write_funcs(fwtable);
>+__gen_reg_write_funcs(gen8);
>+
>+#undef __gen_reg_write_funcs
> #undef GEN6_WRITE_FOOTER
> #undef GEN6_WRITE_HEADER
> 
>-#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
>+#define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
> do { \
> 	(uncore)->funcs.mmio_writeb = x##_write8; \
> 	(uncore)->funcs.mmio_writew = x##_write16; \
> 	(uncore)->funcs.mmio_writel = x##_write32; \
> } while (0)
> 
>-#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
>+#define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
> do { \
> 	(uncore)->funcs.mmio_readb = x##_read8; \
> 	(uncore)->funcs.mmio_readw = x##_read16; \
>@@ -1276,24 +1309,39 @@
> 	(uncore)->funcs.mmio_readq = x##_read64; \
> } while (0)
> 
>+#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
>+do { \
>+	ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
>+	(uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
>+} while (0)
>+
>+#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
>+do { \
>+	ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
>+	(uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
>+} while (0)
> 
>-static void fw_domain_init(struct intel_uncore *uncore,
>-			   enum forcewake_domain_id domain_id,
>-			   i915_reg_t reg_set,
>-			   i915_reg_t reg_ack)
>+static int __fw_domain_init(struct intel_uncore *uncore,
>+			    enum forcewake_domain_id domain_id,
>+			    i915_reg_t reg_set,
>+			    i915_reg_t reg_ack)
> {
> 	struct intel_uncore_forcewake_domain *d;
> 
>-	if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
>-		return;
>+	GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
>+	GEM_BUG_ON(uncore->fw_domain[domain_id]);
> 
>-	d = &uncore->fw_domain[domain_id];
>+	if (i915_inject_probe_failure())
>+		return -ENOMEM;
> 
>-	WARN_ON(d->wake_count);
>+	d = kzalloc(sizeof(*d), GFP_KERNEL);
>+	if (!d)
>+		return -ENOMEM;
> 
> 	WARN_ON(!i915_mmio_reg_valid(reg_set));
> 	WARN_ON(!i915_mmio_reg_valid(reg_ack));
> 
>+	d->uncore = uncore;
> 	d->wake_count = 0;
> 	d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set);
> 	d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack);
>@@ -1310,7 +1358,6 @@
> 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
> 	BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
> 
>-
> 	d->mask = BIT(domain_id);
> 
> 	hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
>@@ -1319,6 +1366,10 @@
> 	uncore->fw_domains |= BIT(domain_id);
> 
> 	fw_domain_reset(d);
>+
>+	uncore->fw_domain[domain_id] = d;
>+
>+	return 0;
> }
> 
> static void fw_domain_fini(struct intel_uncore *uncore,
>@@ -1326,30 +1377,41 @@
> {
> 	struct intel_uncore_forcewake_domain *d;
> 
>-	if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
>-		return;
>+	GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT);
> 
>-	d = &uncore->fw_domain[domain_id];
>+	d = fetch_and_zero(&uncore->fw_domain[domain_id]);
>+	if (!d)
>+		return;
> 
>+	uncore->fw_domains &= ~BIT(domain_id);
> 	WARN_ON(d->wake_count);
> 	WARN_ON(hrtimer_cancel(&d->timer));
>-	memset(d, 0, sizeof(*d));
>+	kfree(d);
>+}
> 
>-	uncore->fw_domains &= ~BIT(domain_id);
>+static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore)
>+{
>+	struct intel_uncore_forcewake_domain *d;
>+	int tmp;
>+
>+	for_each_fw_domain(d, uncore, tmp)
>+		fw_domain_fini(uncore, d->id);
> }
> 
>-static void intel_uncore_fw_domains_init(struct intel_uncore *uncore)
>+static int intel_uncore_fw_domains_init(struct intel_uncore *uncore)
> {
>-	struct drm_i915_private *i915 = uncore_to_i915(uncore);
>+	struct drm_i915_private *i915 = uncore->i915;
>+	int ret = 0;
> 
>-	if (!intel_uncore_has_forcewake(uncore))
>-		return;
>+	GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
>+
>+#define fw_domain_init(uncore__, id__, set__, ack__) \
>+	(ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__))))
> 
> 	if (INTEL_GEN(i915) >= 11) {
> 		int i;
> 
>-		uncore->funcs.force_wake_get =
>-			fw_domains_get_with_fallback;
>+		uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
> 		uncore->funcs.force_wake_put = fw_domains_put;
> 		fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
> 			       FORCEWAKE_RENDER_GEN9,
>@@ -1357,6 +1419,7 @@
> 		fw_domain_init(uncore, FW_DOMAIN_ID_BLITTER,
> 			       FORCEWAKE_BLITTER_GEN9,
> 			       FORCEWAKE_ACK_BLITTER_GEN9);
>+
> 		for (i = 0; i < I915_MAX_VCS; i++) {
> 			if (!HAS_ENGINE(i915, _VCS(i)))
> 				continue;
>@@ -1374,8 +1437,7 @@
> 				       FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
> 		}
> 	} else if (IS_GEN_RANGE(i915, 9, 10)) {
>-		uncore->funcs.force_wake_get =
>-			fw_domains_get_with_fallback;
>+		uncore->funcs.force_wake_get = fw_domains_get_with_fallback;
> 		uncore->funcs.force_wake_put = fw_domains_put;
> 		fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
> 			       FORCEWAKE_RENDER_GEN9,
>@@ -1424,8 +1486,10 @@
> 		__raw_uncore_write32(uncore, FORCEWAKE, 0);
> 		__raw_posting_read(uncore, ECOBUS);
> 
>-		fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
>-			       FORCEWAKE_MT, FORCEWAKE_MT_ACK);
>+		ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
>+				       FORCEWAKE_MT, FORCEWAKE_MT_ACK);
>+		if (ret)
>+			goto out;
> 
> 		spin_lock_irq(&uncore->lock);
> 		fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER);
>@@ -1436,6 +1500,7 @@
> 		if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
> 			DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
> 			DRM_INFO("when using vblank-synced partial screen updates.\n");
>+			fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER);
> 			fw_domain_init(uncore, FW_DOMAIN_ID_RENDER,
> 				       FORCEWAKE, FORCEWAKE_ACK);
> 		}
>@@ -1447,8 +1512,16 @@
> 			       FORCEWAKE, FORCEWAKE_ACK);
> 	}
> 
>+#undef fw_domain_init
>+
> 	/* All future platforms are expected to require complex power gating */
>-	WARN_ON(uncore->fw_domains == 0);
>+	WARN_ON(!ret && uncore->fw_domains == 0);
>+
>+out:
>+	if (ret)
>+		intel_uncore_fw_domains_fini(uncore);
>+
>+	return ret;
> }
> 
> #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \
>@@ -1493,7 +1566,7 @@
> 
> static int uncore_mmio_setup(struct intel_uncore *uncore)
> {
>-	struct drm_i915_private *i915 = uncore_to_i915(uncore);
>+	struct drm_i915_private *i915 = uncore->i915;
> 	struct pci_dev *pdev = i915->drm.pdev;
> 	int mmio_bar;
> 	int mmio_size;
>@@ -1523,49 +1596,46 @@
> 
> static void uncore_mmio_cleanup(struct intel_uncore *uncore)
> {
>-	struct drm_i915_private *i915 = uncore_to_i915(uncore);
>-	struct pci_dev *pdev = i915->drm.pdev;
>+	struct pci_dev *pdev = uncore->i915->drm.pdev;
> 
> 	pci_iounmap(pdev, uncore->regs);
> }
> 
>-void intel_uncore_init_early(struct intel_uncore *uncore)
>+void intel_uncore_init_early(struct intel_uncore *uncore,
>+			     struct drm_i915_private *i915)
> {
> 	spin_lock_init(&uncore->lock);
>+	uncore->i915 = i915;
>+	uncore->rpm = &i915->runtime_pm;
> }
> 
>-int intel_uncore_init_mmio(struct intel_uncore *uncore)
>+static void uncore_raw_init(struct intel_uncore *uncore)
> {
>-	struct drm_i915_private *i915 = uncore_to_i915(uncore);
>-	int ret;
>-
>-	ret = uncore_mmio_setup(uncore);
>-	if (ret)
>-		return ret;
>+	GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
> 
>-	i915_check_vgpu(i915);
>+	if (IS_GEN(uncore->i915, 5)) {
>+		ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
>+		ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
>+	} else {
>+		ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
>+		ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
>+	}
>+}
> 
>-	if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
>-		uncore->flags |= UNCORE_HAS_FORCEWAKE;
>+static int uncore_forcewake_init(struct intel_uncore *uncore)
>+{
>+	struct drm_i915_private *i915 = uncore->i915;
>+	int ret;
> 
>-	intel_uncore_fw_domains_init(uncore);
>-	__intel_uncore_early_sanitize(uncore, 0);
>+	GEM_BUG_ON(!intel_uncore_has_forcewake(uncore));
> 
>-	uncore->unclaimed_mmio_check = 1;
>-	uncore->pmic_bus_access_nb.notifier_call =
>-		i915_pmic_bus_access_notifier;
>+	ret = intel_uncore_fw_domains_init(uncore);
>+	if (ret)
>+		return ret;
> 
>-	uncore->rpm = &i915->runtime_pm;
>+	forcewake_early_sanitize(uncore, 0);
> 
>-	if (!intel_uncore_has_forcewake(uncore)) {
>-		if (IS_GEN(i915, 5)) {
>-			ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen5);
>-			ASSIGN_READ_MMIO_VFUNCS(uncore, gen5);
>-		} else {
>-			ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen2);
>-			ASSIGN_READ_MMIO_VFUNCS(uncore, gen2);
>-		}
>-	} else if (IS_GEN_RANGE(i915, 6, 7)) {
>+	if (IS_GEN_RANGE(i915, 6, 7)) {
> 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
> 
> 		if (IS_VALLEYVIEW(i915)) {
>@@ -1579,7 +1649,6 @@
> 			ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges);
> 			ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
> 			ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
>-
> 		} else {
> 			ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
> 			ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
>@@ -1594,6 +1663,40 @@
> 		ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
> 	}
> 
>+	uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
>+	iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
>+
>+	return 0;
>+}
>+
>+int intel_uncore_init_mmio(struct intel_uncore *uncore)
>+{
>+	struct drm_i915_private *i915 = uncore->i915;
>+	int ret;
>+
>+	ret = uncore_mmio_setup(uncore);
>+	if (ret)
>+		return ret;
>+
>+	if (INTEL_GEN(i915) > 5 && !intel_vgpu_active(i915))
>+		uncore->flags |= UNCORE_HAS_FORCEWAKE;
>+
>+	uncore->unclaimed_mmio_check = 1;
>+
>+	if (!intel_uncore_has_forcewake(uncore)) {
>+		uncore_raw_init(uncore);
>+	} else {
>+		ret = uncore_forcewake_init(uncore);
>+		if (ret)
>+			goto out_mmio_cleanup;
>+	}
>+
>+	/* make sure fw funcs are set if and only if we have fw*/
>+	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get);
>+	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put);
>+	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains);
>+	GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains);
>+
> 	if (HAS_FPGA_DBG_UNCLAIMED(i915))
> 		uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED;
> 
>@@ -1603,9 +1706,16 @@
> 	if (IS_GEN_RANGE(i915, 6, 7))
> 		uncore->flags |= UNCORE_HAS_FIFO;
> 
>-	iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb);
>+	/* clear out unclaimed reg detection bit */
>+	if (check_for_unclaimed_mmio(uncore))
>+		DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
> 
> 	return 0;
>+
>+out_mmio_cleanup:
>+	uncore_mmio_cleanup(uncore);
>+
>+	return ret;
> }
> 
> /*
>@@ -1615,45 +1725,46 @@
>  */
> void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore)
> {
>-	struct drm_i915_private *i915 = uncore_to_i915(uncore);
>+	struct drm_i915_private *i915 = uncore->i915;
>+	enum forcewake_domains fw_domains = uncore->fw_domains;
>+	enum forcewake_domain_id domain_id;
>+	int i;
> 
>-	if (INTEL_GEN(i915) >= 11) {
>-		enum forcewake_domains fw_domains = uncore->fw_domains;
>-		enum forcewake_domain_id domain_id;
>-		int i;
>+	if (!intel_uncore_has_forcewake(uncore) || INTEL_GEN(i915) < 11)
>+		return;
> 
>-		for (i = 0; i < I915_MAX_VCS; i++) {
>-			domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
>+	for (i = 0; i < I915_MAX_VCS; i++) {
>+		domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
> 
>-			if (HAS_ENGINE(i915, _VCS(i)))
>-				continue;
>+		if (HAS_ENGINE(i915, _VCS(i)))
>+			continue;
> 
>-			if (fw_domains & BIT(domain_id))
>-				fw_domain_fini(uncore, domain_id);
>-		}
>+		if (fw_domains & BIT(domain_id))
>+			fw_domain_fini(uncore, domain_id);
>+	}
> 
>-		for (i = 0; i < I915_MAX_VECS; i++) {
>-			domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
>+	for (i = 0; i < I915_MAX_VECS; i++) {
>+		domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
> 
>-			if (HAS_ENGINE(i915, _VECS(i)))
>-				continue;
>+		if (HAS_ENGINE(i915, _VECS(i)))
>+			continue;
> 
>-			if (fw_domains & BIT(domain_id))
>-				fw_domain_fini(uncore, domain_id);
>-		}
>+		if (fw_domains & BIT(domain_id))
>+			fw_domain_fini(uncore, domain_id);
> 	}
> }
> 
> void intel_uncore_fini_mmio(struct intel_uncore *uncore)
> {
>-	/* Paranoia: make sure we have disabled everything before we exit. */
>-	intel_uncore_sanitize(uncore_to_i915(uncore));
>+	if (intel_uncore_has_forcewake(uncore)) {
>+		iosf_mbi_punit_acquire();
>+		iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
>+			&uncore->pmic_bus_access_nb);
>+		intel_uncore_forcewake_reset(uncore);
>+		intel_uncore_fw_domains_fini(uncore);
>+		iosf_mbi_punit_release();
>+	}
> 
>-	iosf_mbi_punit_acquire();
>-	iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(
>-		&uncore->pmic_bus_access_nb);
>-	intel_uncore_forcewake_reset(uncore);
>-	iosf_mbi_punit_release();
> 	uncore_mmio_cleanup(uncore);
> }
> 
>@@ -1871,62 +1982,6 @@
> 	return ret;
> }
> 
>-static enum forcewake_domains
>-intel_uncore_forcewake_for_read(struct intel_uncore *uncore,
>-				i915_reg_t reg)
>-{
>-	struct drm_i915_private *i915 = uncore_to_i915(uncore);
>-	u32 offset = i915_mmio_reg_offset(reg);
>-	enum forcewake_domains fw_domains;
>-
>-	if (INTEL_GEN(i915) >= 11) {
>-		fw_domains = __gen11_fwtable_reg_read_fw_domains(uncore, offset);
>-	} else if (HAS_FWTABLE(i915)) {
>-		fw_domains = __fwtable_reg_read_fw_domains(uncore, offset);
>-	} else if (INTEL_GEN(i915) >= 6) {
>-		fw_domains = __gen6_reg_read_fw_domains(uncore, offset);
>-	} else {
>-		/* on devices with FW we expect to hit one of the above cases */
>-		if (intel_uncore_has_forcewake(uncore))
>-			MISSING_CASE(INTEL_GEN(i915));
>-
>-		fw_domains = 0;
>-	}
>-
>-	WARN_ON(fw_domains & ~uncore->fw_domains);
>-
>-	return fw_domains;
>-}
>-
>-static enum forcewake_domains
>-intel_uncore_forcewake_for_write(struct intel_uncore *uncore,
>-				 i915_reg_t reg)
>-{
>-	struct drm_i915_private *i915 = uncore_to_i915(uncore);
>-	u32 offset = i915_mmio_reg_offset(reg);
>-	enum forcewake_domains fw_domains;
>-
>-	if (INTEL_GEN(i915) >= 11) {
>-		fw_domains = __gen11_fwtable_reg_write_fw_domains(uncore, offset);
>-	} else if (HAS_FWTABLE(i915) && !IS_VALLEYVIEW(i915)) {
>-		fw_domains = __fwtable_reg_write_fw_domains(uncore, offset);
>-	} else if (IS_GEN(i915, 8)) {
>-		fw_domains = __gen8_reg_write_fw_domains(uncore, offset);
>-	} else if (IS_GEN_RANGE(i915, 6, 7)) {
>-		fw_domains = FORCEWAKE_RENDER;
>-	} else {
>-		/* on devices with FW we expect to hit one of the above cases */
>-		if (intel_uncore_has_forcewake(uncore))
>-			MISSING_CASE(INTEL_GEN(i915));
>-
>-		fw_domains = 0;
>-	}
>-
>-	WARN_ON(fw_domains & ~uncore->fw_domains);
>-
>-	return fw_domains;
>-}
>-
> /**
>  * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
>  * 				    a register
>@@ -1953,10 +2008,12 @@
> 		return 0;
> 
> 	if (op & FW_REG_READ)
>-		fw_domains = intel_uncore_forcewake_for_read(uncore, reg);
>+		fw_domains = uncore->funcs.read_fw_domains(uncore, reg);
> 
> 	if (op & FW_REG_WRITE)
>-		fw_domains |= intel_uncore_forcewake_for_write(uncore, reg);
>+		fw_domains |= uncore->funcs.write_fw_domains(uncore, reg);
>+
>+	WARN_ON(fw_domains & ~uncore->fw_domains);
> 
> 	return fw_domains;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_uncore.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_uncore.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_uncore.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_uncore.h	2019-08-31 15:01:12.039736184 -0500
>@@ -70,6 +70,11 @@
> 	void (*force_wake_put)(struct intel_uncore *uncore,
> 			       enum forcewake_domains domains);
> 
>+	enum forcewake_domains (*read_fw_domains)(struct intel_uncore *uncore,
>+						  i915_reg_t r);
>+	enum forcewake_domains (*write_fw_domains)(struct intel_uncore *uncore,
>+						   i915_reg_t r);
>+
> 	u8 (*mmio_readb)(struct intel_uncore *uncore,
> 			 i915_reg_t r, bool trace);
> 	u16 (*mmio_readw)(struct intel_uncore *uncore,
>@@ -97,6 +102,7 @@
> struct intel_uncore {
> 	void __iomem *regs;
> 
>+	struct drm_i915_private *i915;
> 	struct intel_runtime_pm *rpm;
> 
> 	spinlock_t lock; /** lock is also taken in irq contexts. */
>@@ -117,9 +123,11 @@
> 
> 	enum forcewake_domains fw_domains;
> 	enum forcewake_domains fw_domains_active;
>+	enum forcewake_domains fw_domains_timer;
> 	enum forcewake_domains fw_domains_saved; /* user domains saved for S3 */
> 
> 	struct intel_uncore_forcewake_domain {
>+		struct intel_uncore *uncore;
> 		enum forcewake_domain_id id;
> 		enum forcewake_domains mask;
> 		unsigned int wake_count;
>@@ -127,7 +135,7 @@
> 		struct hrtimer timer;
> 		u32 __iomem *reg_set;
> 		u32 __iomem *reg_ack;
>-	} fw_domain[FW_DOMAIN_ID_COUNT];
>+	} *fw_domain[FW_DOMAIN_ID_COUNT];
> 
> 	struct {
> 		unsigned int count;
>@@ -141,18 +149,12 @@
> 
> /* Iterate over initialised fw domains */
> #define for_each_fw_domain_masked(domain__, mask__, uncore__, tmp__) \
>-	for (tmp__ = (mask__); \
>-	     tmp__ ? (domain__ = &(uncore__)->fw_domain[__mask_next_bit(tmp__)]), 1 : 0;)
>+	for (tmp__ = (mask__); tmp__ ;) \
>+		for_each_if(domain__ = (uncore__)->fw_domain[__mask_next_bit(tmp__)])
> 
> #define for_each_fw_domain(domain__, uncore__, tmp__) \
> 	for_each_fw_domain_masked(domain__, (uncore__)->fw_domains, uncore__, tmp__)
> 
>-static inline struct intel_uncore *
>-forcewake_domain_to_uncore(const struct intel_uncore_forcewake_domain *d)
>-{
>-	return container_of(d, struct intel_uncore, fw_domain[d->id]);
>-}
>-
> static inline bool
> intel_uncore_has_forcewake(const struct intel_uncore *uncore)
> {
>@@ -177,8 +179,8 @@
> 	return uncore->flags & UNCORE_HAS_FIFO;
> }
> 
>-void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
>-void intel_uncore_init_early(struct intel_uncore *uncore);
>+void intel_uncore_init_early(struct intel_uncore *uncore,
>+			     struct drm_i915_private *i915);
> int intel_uncore_init_mmio(struct intel_uncore *uncore);
> void intel_uncore_prune_mmio_domains(struct intel_uncore *uncore);
> bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_wakeref.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_wakeref.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_wakeref.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_wakeref.c	2019-08-31 15:01:12.040736184 -0500
>@@ -5,7 +5,7 @@
>  */
> 
> #include "intel_runtime_pm.h"
>-#include "i915_gem.h"
>+#include "intel_wakeref.h"
> 
> static void rpm_get(struct intel_runtime_pm *rpm, struct intel_wakeref *wf)
> {
>@@ -17,7 +17,7 @@
> 	intel_wakeref_t wakeref = fetch_and_zero(&wf->wakeref);
> 
> 	intel_runtime_pm_put(rpm, wakeref);
>-	GEM_BUG_ON(!wakeref);
>+	INTEL_WAKEREF_BUG_ON(!wakeref);
> }
> 
> int __intel_wakeref_get_first(struct intel_runtime_pm *rpm,
>@@ -48,6 +48,7 @@
> 	atomic_inc(&wf->count);
> 	mutex_unlock(&wf->mutex);
> 
>+	INTEL_WAKEREF_BUG_ON(atomic_read(&wf->count) <= 0);
> 	return 0;
> }
> 
>@@ -115,7 +116,7 @@
> 	if (!refcount_inc_not_zero(&wf->count)) {
> 		spin_lock_irqsave(&wf->lock, flags);
> 		if (!refcount_inc_not_zero(&wf->count)) {
>-			GEM_BUG_ON(wf->wakeref);
>+			INTEL_WAKEREF_BUG_ON(wf->wakeref);
> 			wf->wakeref = intel_runtime_pm_get_if_in_use(wf->rpm);
> 			refcount_set(&wf->count, 1);
> 		}
>@@ -134,5 +135,5 @@
> void intel_wakeref_auto_fini(struct intel_wakeref_auto *wf)
> {
> 	intel_wakeref_auto(wf, 0);
>-	GEM_BUG_ON(wf->wakeref);
>+	INTEL_WAKEREF_BUG_ON(wf->wakeref);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_wakeref.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_wakeref.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_wakeref.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_wakeref.h	2019-08-31 15:01:12.040736184 -0500
>@@ -13,6 +13,12 @@
> #include <linux/stackdepot.h>
> #include <linux/timer.h>
> 
>+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
>+#define INTEL_WAKEREF_BUG_ON(expr) BUG_ON(expr)
>+#else
>+#define INTEL_WAKEREF_BUG_ON(expr) BUILD_BUG_ON_INVALID(expr)
>+#endif
>+
> struct intel_runtime_pm;
> 
> typedef depot_stack_handle_t intel_wakeref_t;
>@@ -101,6 +107,7 @@
> 		  struct intel_wakeref *wf,
> 		  int (*fn)(struct intel_wakeref *wf))
> {
>+	INTEL_WAKEREF_BUG_ON(atomic_read(&wf->count) <= 0);
> 	if (atomic_dec_and_mutex_lock(&wf->count, &wf->mutex))
> 		return __intel_wakeref_put_last(rpm, wf, fn);
> 
>@@ -136,13 +143,13 @@
> }
> 
> /**
>- * intel_wakeref_active: Query whether the wakeref is currently held
>+ * intel_wakeref_is_active: Query whether the wakeref is currently held
>  * @wf: the wakeref
>  *
>  * Returns: true if the wakeref is currently held.
>  */
> static inline bool
>-intel_wakeref_active(struct intel_wakeref *wf)
>+intel_wakeref_is_active(const struct intel_wakeref *wf)
> {
> 	return READ_ONCE(wf->wakeref);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_wopcm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_wopcm.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_wopcm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_wopcm.c	2019-08-31 15:01:12.040736184 -0500
>@@ -74,7 +74,7 @@
> {
> 	struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
> 
>-	if (!HAS_GUC(i915))
>+	if (!HAS_GT_UC(i915))
> 		return;
> 
> 	if (INTEL_GEN(i915) >= 11)
>@@ -164,8 +164,8 @@
> int intel_wopcm_init(struct intel_wopcm *wopcm)
> {
> 	struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
>-	u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->guc.fw);
>-	u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->huc.fw);
>+	u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.guc.fw);
>+	u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.huc.fw);
> 	u32 ctx_rsvd = context_reserved_size(i915);
> 	u32 guc_wopcm_base;
> 	u32 guc_wopcm_size;
>@@ -177,7 +177,7 @@
> 
> 	GEM_BUG_ON(!wopcm->size);
> 
>-	if (i915_inject_load_failure())
>+	if (i915_inject_probe_failure())
> 		return -E2BIG;
> 
> 	if (guc_fw_size >= wopcm->size) {
>@@ -225,17 +225,18 @@
> 	return 0;
> }
> 
>-static inline int write_and_verify(struct drm_i915_private *dev_priv,
>-				   i915_reg_t reg, u32 val, u32 mask,
>-				   u32 locked_bit)
>+static int
>+write_and_verify(struct intel_gt *gt,
>+		 i915_reg_t reg, u32 val, u32 mask, u32 locked_bit)
> {
>+	struct intel_uncore *uncore = gt->uncore;
> 	u32 reg_val;
> 
> 	GEM_BUG_ON(val & ~mask);
> 
>-	I915_WRITE(reg, val);
>+	intel_uncore_write(uncore, reg, val);
> 
>-	reg_val = I915_READ(reg);
>+	reg_val = intel_uncore_read(uncore, reg);
> 
> 	return (reg_val & mask) != (val | locked_bit) ? -EIO : 0;
> }
>@@ -243,6 +244,7 @@
> /**
>  * intel_wopcm_init_hw() - Setup GuC WOPCM registers.
>  * @wopcm: pointer to intel_wopcm.
>+ * @gt: pointer to the containing GT
>  *
>  * Setup the GuC WOPCM size and offset registers with the calculated values. It
>  * will verify the register values to make sure the registers are locked with
>@@ -250,29 +252,30 @@
>  *
>  * Return: 0 on success. -EIO if registers were locked with incorrect values.
>  */
>-int intel_wopcm_init_hw(struct intel_wopcm *wopcm)
>+int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt)
> {
>-	struct drm_i915_private *dev_priv = wopcm_to_i915(wopcm);
>+	struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
>+	struct intel_uncore *uncore = gt->uncore;
> 	u32 huc_agent;
> 	u32 mask;
> 	int err;
> 
>-	if (!USES_GUC(dev_priv))
>+	if (!USES_GUC(i915))
> 		return 0;
> 
>-	GEM_BUG_ON(!HAS_GUC(dev_priv));
>+	GEM_BUG_ON(!HAS_GT_UC(i915));
> 	GEM_BUG_ON(!wopcm->guc.size);
> 	GEM_BUG_ON(!wopcm->guc.base);
> 
>-	err = write_and_verify(dev_priv, GUC_WOPCM_SIZE, wopcm->guc.size,
>+	err = write_and_verify(gt, GUC_WOPCM_SIZE, wopcm->guc.size,
> 			       GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED,
> 			       GUC_WOPCM_SIZE_LOCKED);
> 	if (err)
> 		goto err_out;
> 
>-	huc_agent = USES_HUC(dev_priv) ? HUC_LOADING_AGENT_GUC : 0;
>+	huc_agent = USES_HUC(i915) ? HUC_LOADING_AGENT_GUC : 0;
> 	mask = GUC_WOPCM_OFFSET_MASK | GUC_WOPCM_OFFSET_VALID | huc_agent;
>-	err = write_and_verify(dev_priv, DMA_GUC_WOPCM_OFFSET,
>+	err = write_and_verify(gt, DMA_GUC_WOPCM_OFFSET,
> 			       wopcm->guc.base | huc_agent, mask,
> 			       GUC_WOPCM_OFFSET_VALID);
> 	if (err)
>@@ -283,8 +286,9 @@
> err_out:
> 	DRM_ERROR("Failed to init WOPCM registers:\n");
> 	DRM_ERROR("DMA_GUC_WOPCM_OFFSET=%#x\n",
>-		  I915_READ(DMA_GUC_WOPCM_OFFSET));
>-	DRM_ERROR("GUC_WOPCM_SIZE=%#x\n", I915_READ(GUC_WOPCM_SIZE));
>+		  intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET));
>+	DRM_ERROR("GUC_WOPCM_SIZE=%#x\n",
>+		  intel_uncore_read(uncore, GUC_WOPCM_SIZE));
> 
> 	return err;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/intel_wopcm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_wopcm.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/intel_wopcm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/intel_wopcm.h	2019-08-31 15:01:12.040736184 -0500
>@@ -9,6 +9,8 @@
> 
> #include <linux/types.h>
> 
>+struct intel_gt;
>+
> /**
>  * struct intel_wopcm - Overall WOPCM info and WOPCM regions.
>  * @size: Size of overall WOPCM.
>@@ -41,6 +43,6 @@
> 
> void intel_wopcm_init_early(struct intel_wopcm *wopcm);
> int intel_wopcm_init(struct intel_wopcm *wopcm);
>-int intel_wopcm_init_hw(struct intel_wopcm *wopcm);
>+int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt);
> 
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/Kconfig.debug linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/Kconfig.debug
>--- linux-5.3-rc6/drivers/gpu/drm/i915/Kconfig.debug	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/Kconfig.debug	2019-08-31 15:01:12.014736182 -0500
>@@ -7,6 +7,7 @@
>         # We use the dependency on !COMPILE_TEST to not be enabled in
>         # allmodconfig or allyesconfig configurations
>         depends on !COMPILE_TEST
>+	select HEADER_TEST
>         default n
>         help
>           Add -Werror to the build flags for (and only for) i915.ko.
>@@ -85,6 +86,20 @@
> 	depends on DRM_I915_DEBUG_GEM
> 	select TRACING
> 	default n
>+	help
>+	  Enable additional and verbose debugging output that will spam
>+	  ordinary tests, but may be vital for post-mortem debugging when
>+	  used with /proc/sys/kernel/ftrace_dump_on_oops
>+
>+	  Recommended for driver developers only.
>+
>+	  If in doubt, say "N".
>+
>+config DRM_I915_TRACE_GTT
>+	bool "Insert extra ftrace output from the GTT internals"
>+	depends on DRM_I915_DEBUG_GEM
>+	select TRACING
>+	default n
> 	help
> 	  Enable additional and verbose debugging output that will spam
> 	  ordinary tests, but may be vital for post-mortem debugging when
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/i915/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/Makefile	2019-08-31 15:01:12.014736182 -0500
>@@ -32,9 +32,9 @@
> 	$(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)
> 
> # Extra header tests
>-include $(src)/Makefile.header-test
>+header-test-pattern-$(CONFIG_DRM_I915_WERROR) := *.h
> 
>-subdir-ccflags-y += -I$(src)
>+subdir-ccflags-y += -I$(srctree)/$(src)
> 
> # Please keep these build lists sorted!
> 
>@@ -73,14 +73,23 @@
> 	gt/intel_context.o \
> 	gt/intel_engine_cs.o \
> 	gt/intel_engine_pm.o \
>+	gt/intel_gt.o \
> 	gt/intel_gt_pm.o \
> 	gt/intel_hangcheck.o \
> 	gt/intel_lrc.o \
>+	gt/intel_renderstate.o \
> 	gt/intel_reset.o \
> 	gt/intel_ringbuffer.o \
> 	gt/intel_mocs.o \
> 	gt/intel_sseu.o \
>+	gt/intel_timeline.o \
> 	gt/intel_workarounds.o
>+# autogenerated null render state
>+gt-y += \
>+	gt/gen6_renderstate.o \
>+	gt/gen7_renderstate.o \
>+	gt/gen8_renderstate.o \
>+	gt/gen9_renderstate.o
> gt-$(CONFIG_DRM_I915_SELFTEST) += \
> 	gt/mock_engine.o
> i915-y += $(gt-y)
>@@ -120,33 +129,26 @@
> 	  i915_gem_fence_reg.o \
> 	  i915_gem_gtt.o \
> 	  i915_gem.o \
>-	  i915_gem_render_state.o \
> 	  i915_globals.o \
> 	  i915_query.o \
> 	  i915_request.o \
> 	  i915_scheduler.o \
>-	  i915_timeline.o \
> 	  i915_trace_points.o \
> 	  i915_vma.o \
> 	  intel_wopcm.o
> 
> # general-purpose microcontroller (GuC) support
>-i915-y += intel_uc.o \
>-	  intel_uc_fw.o \
>-	  intel_guc.o \
>-	  intel_guc_ads.o \
>-	  intel_guc_ct.o \
>-	  intel_guc_fw.o \
>-	  intel_guc_log.o \
>-	  intel_guc_submission.o \
>-	  intel_huc.o \
>-	  intel_huc_fw.o
>-
>-# autogenerated null render state
>-i915-y += intel_renderstate_gen6.o \
>-	  intel_renderstate_gen7.o \
>-	  intel_renderstate_gen8.o \
>-	  intel_renderstate_gen9.o
>+obj-y += gt/uc/
>+i915-y += gt/uc/intel_uc.o \
>+	  gt/uc/intel_uc_fw.o \
>+	  gt/uc/intel_guc.o \
>+	  gt/uc/intel_guc_ads.o \
>+	  gt/uc/intel_guc_ct.o \
>+	  gt/uc/intel_guc_fw.o \
>+	  gt/uc/intel_guc_log.o \
>+	  gt/uc/intel_guc_submission.o \
>+	  gt/uc/intel_huc.o \
>+	  gt/uc/intel_huc_fw.o
> 
> # modesetting core code
> obj-y += display/
>@@ -173,7 +175,8 @@
> 	display/intel_overlay.o \
> 	display/intel_psr.o \
> 	display/intel_quirks.o \
>-	display/intel_sprite.o
>+	display/intel_sprite.o \
>+	display/intel_tc.o
> i915-$(CONFIG_ACPI) += \
> 	display/intel_acpi.o \
> 	display/intel_opregion.o
>@@ -210,6 +213,25 @@
> 	display/vlv_dsi.o \
> 	display/vlv_dsi_pll.o
> 
>+# perf code
>+obj-y += oa/
>+i915-y += \
>+	oa/i915_oa_hsw.o \
>+	oa/i915_oa_bdw.o \
>+	oa/i915_oa_chv.o \
>+	oa/i915_oa_sklgt2.o \
>+	oa/i915_oa_sklgt3.o \
>+	oa/i915_oa_sklgt4.o \
>+	oa/i915_oa_bxt.o \
>+	oa/i915_oa_kblgt2.o \
>+	oa/i915_oa_kblgt3.o \
>+	oa/i915_oa_glk.o \
>+	oa/i915_oa_cflgt2.o \
>+	oa/i915_oa_cflgt3.o \
>+	oa/i915_oa_cnl.o \
>+	oa/i915_oa_icl.o
>+i915-y += i915_perf.o
>+
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> i915-$(CONFIG_DRM_I915_SELFTEST) += \
>@@ -224,23 +246,6 @@
> # virtual gpu code
> i915-y += i915_vgpu.o
> 
>-# perf code
>-i915-y += i915_perf.o \
>-	  i915_oa_hsw.o \
>-	  i915_oa_bdw.o \
>-	  i915_oa_chv.o \
>-	  i915_oa_sklgt2.o \
>-	  i915_oa_sklgt3.o \
>-	  i915_oa_sklgt4.o \
>-	  i915_oa_bxt.o \
>-	  i915_oa_kblgt2.o \
>-	  i915_oa_kblgt3.o \
>-	  i915_oa_glk.o \
>-	  i915_oa_cflgt2.o \
>-	  i915_oa_cflgt3.o \
>-	  i915_oa_cnl.o \
>-	  i915_oa_icl.o
>-
> ifeq ($(CONFIG_DRM_I915_GVT),y)
> i915-y += intel_gvt.o
> include $(src)/gvt/Makefile
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/Makefile.header-test linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/Makefile.header-test
>--- linux-5.3-rc6/drivers/gpu/drm/i915/Makefile.header-test	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/Makefile.header-test	1969-12-31 18:00:00.000000000 -0600
>@@ -1,22 +0,0 @@
>-# SPDX-License-Identifier: MIT
>-# Copyright Â© 2019 Intel Corporation
>-
>-# Test the headers are compilable as standalone units
>-header-test-$(CONFIG_DRM_I915_WERROR) := \
>-	i915_active_types.h \
>-	i915_debugfs.h \
>-	i915_drv.h \
>-	i915_irq.h \
>-	i915_params.h \
>-	i915_priolist_types.h \
>-	i915_reg.h \
>-	i915_scheduler_types.h \
>-	i915_timeline_types.h \
>-	i915_utils.h \
>-	intel_csr.h \
>-	intel_drv.h \
>-	intel_pm.h \
>-	intel_runtime_pm.h \
>-	intel_sideband.h \
>-	intel_uncore.h \
>-	intel_wakeref.h
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_bdw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_bdw.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_bdw.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_bdw.c	2019-08-31 15:01:12.238736202 -0500
>@@ -0,0 +1,91 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_bdw.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2744), 0x00800000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x00000000 },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x00000000 },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x00000000 },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0x9840), 0x000000a0 },
>+	{ _MMIO(0x9888), 0x198b0000 },
>+	{ _MMIO(0x9888), 0x078b0066 },
>+	{ _MMIO(0x9888), 0x118b0000 },
>+	{ _MMIO(0x9888), 0x258b0000 },
>+	{ _MMIO(0x9888), 0x21850008 },
>+	{ _MMIO(0x9888), 0x0d834000 },
>+	{ _MMIO(0x9888), 0x07844000 },
>+	{ _MMIO(0x9888), 0x17804000 },
>+	{ _MMIO(0x9888), 0x21800000 },
>+	{ _MMIO(0x9888), 0x4f800000 },
>+	{ _MMIO(0x9888), 0x41800000 },
>+	{ _MMIO(0x9888), 0x31800000 },
>+	{ _MMIO(0x9840), 0x00000080 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"d6de6f55-e526-4f79-a6a6-d7315c09044e",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "d6de6f55-e526-4f79-a6a6-d7315c09044e";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_bdw.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_bdw.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_bdw.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_bdw.h	2019-08-31 15:01:12.238736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_BDW_H__
>+#define __I915_OA_BDW_H__
>+
>+void i915_perf_load_test_config_bdw(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_bxt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_bxt.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_bxt.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_bxt.c	2019-08-31 15:01:12.238736202 -0500
>@@ -0,0 +1,89 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_bxt.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2744), 0x00800000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x00000000 },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x00000000 },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x00000000 },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0x9840), 0x00000080 },
>+	{ _MMIO(0x9888), 0x19800000 },
>+	{ _MMIO(0x9888), 0x07800063 },
>+	{ _MMIO(0x9888), 0x11800000 },
>+	{ _MMIO(0x9888), 0x23810008 },
>+	{ _MMIO(0x9888), 0x1d950400 },
>+	{ _MMIO(0x9888), 0x0f922000 },
>+	{ _MMIO(0x9888), 0x1f908000 },
>+	{ _MMIO(0x9888), 0x37900000 },
>+	{ _MMIO(0x9888), 0x55900000 },
>+	{ _MMIO(0x9888), 0x47900000 },
>+	{ _MMIO(0x9888), 0x33900000 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"5ee72f5c-092f-421e-8b70-225f7c3e9612",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "5ee72f5c-092f-421e-8b70-225f7c3e9612";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_bxt.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_bxt.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_bxt.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_bxt.h	2019-08-31 15:01:12.238736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_BXT_H__
>+#define __I915_OA_BXT_H__
>+
>+void i915_perf_load_test_config_bxt(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_cflgt2.c	2019-08-31 15:01:12.238736202 -0500
>@@ -0,0 +1,90 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_cflgt2.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2744), 0x00800000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x00000000 },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x00000000 },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x00000000 },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0x9840), 0x00000080 },
>+	{ _MMIO(0x9888), 0x11810000 },
>+	{ _MMIO(0x9888), 0x07810013 },
>+	{ _MMIO(0x9888), 0x1f810000 },
>+	{ _MMIO(0x9888), 0x1d810000 },
>+	{ _MMIO(0x9888), 0x1b930040 },
>+	{ _MMIO(0x9888), 0x07e54000 },
>+	{ _MMIO(0x9888), 0x1f908000 },
>+	{ _MMIO(0x9888), 0x11900000 },
>+	{ _MMIO(0x9888), 0x37900000 },
>+	{ _MMIO(0x9888), 0x53900000 },
>+	{ _MMIO(0x9888), 0x45900000 },
>+	{ _MMIO(0x9888), 0x33900000 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_cflgt2(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"74fb4902-d3d3-4237-9e90-cbdc68d0a446",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "74fb4902-d3d3-4237-9e90-cbdc68d0a446";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_cflgt2.h	2019-08-31 15:01:12.238736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_CFLGT2_H__
>+#define __I915_OA_CFLGT2_H__
>+
>+void i915_perf_load_test_config_cflgt2(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_cflgt3.c	2019-08-31 15:01:12.238736202 -0500
>@@ -0,0 +1,90 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_cflgt3.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2744), 0x00800000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x00000000 },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x00000000 },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x00000000 },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0x9840), 0x00000080 },
>+	{ _MMIO(0x9888), 0x11810000 },
>+	{ _MMIO(0x9888), 0x07810013 },
>+	{ _MMIO(0x9888), 0x1f810000 },
>+	{ _MMIO(0x9888), 0x1d810000 },
>+	{ _MMIO(0x9888), 0x1b930040 },
>+	{ _MMIO(0x9888), 0x07e54000 },
>+	{ _MMIO(0x9888), 0x1f908000 },
>+	{ _MMIO(0x9888), 0x11900000 },
>+	{ _MMIO(0x9888), 0x37900000 },
>+	{ _MMIO(0x9888), 0x53900000 },
>+	{ _MMIO(0x9888), 0x45900000 },
>+	{ _MMIO(0x9888), 0x33900000 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_cflgt3(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"577e8e2c-3fa0-4875-8743-3538d585e3b0",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "577e8e2c-3fa0-4875-8743-3538d585e3b0";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_cflgt3.h	2019-08-31 15:01:12.238736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_CFLGT3_H__
>+#define __I915_OA_CFLGT3_H__
>+
>+void i915_perf_load_test_config_cflgt3(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_chv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_chv.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_chv.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_chv.c	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,90 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_chv.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2744), 0x00800000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x00000000 },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x00000000 },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x00000000 },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0x9840), 0x000000a0 },
>+	{ _MMIO(0x9888), 0x59800000 },
>+	{ _MMIO(0x9888), 0x59800001 },
>+	{ _MMIO(0x9888), 0x338b0000 },
>+	{ _MMIO(0x9888), 0x258b0066 },
>+	{ _MMIO(0x9888), 0x058b0000 },
>+	{ _MMIO(0x9888), 0x038b0000 },
>+	{ _MMIO(0x9888), 0x03844000 },
>+	{ _MMIO(0x9888), 0x47800080 },
>+	{ _MMIO(0x9888), 0x57800000 },
>+	{ _MMIO(0x1823a4), 0x00000000 },
>+	{ _MMIO(0x9888), 0x59800000 },
>+	{ _MMIO(0x9840), 0x00000080 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"4a534b07-cba3-414d-8d60-874830e883aa",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "4a534b07-cba3-414d-8d60-874830e883aa";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_chv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_chv.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_chv.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_chv.h	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_CHV_H__
>+#define __I915_OA_CHV_H__
>+
>+void i915_perf_load_test_config_chv(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_cnl.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_cnl.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_cnl.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_cnl.c	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,102 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_cnl.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x0000ffff },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x0000ffff },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x0000ffff },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0xd04), 0x00000200 },
>+	{ _MMIO(0x9884), 0x00000007 },
>+	{ _MMIO(0x9888), 0x17060000 },
>+	{ _MMIO(0x9840), 0x00000000 },
>+	{ _MMIO(0x9884), 0x00000007 },
>+	{ _MMIO(0x9888), 0x13034000 },
>+	{ _MMIO(0x9884), 0x00000007 },
>+	{ _MMIO(0x9888), 0x07060066 },
>+	{ _MMIO(0x9884), 0x00000007 },
>+	{ _MMIO(0x9888), 0x05060000 },
>+	{ _MMIO(0x9884), 0x00000007 },
>+	{ _MMIO(0x9888), 0x0f080040 },
>+	{ _MMIO(0x9884), 0x00000007 },
>+	{ _MMIO(0x9888), 0x07091000 },
>+	{ _MMIO(0x9884), 0x00000007 },
>+	{ _MMIO(0x9888), 0x0f041000 },
>+	{ _MMIO(0x9884), 0x00000007 },
>+	{ _MMIO(0x9888), 0x1d004000 },
>+	{ _MMIO(0x9884), 0x00000007 },
>+	{ _MMIO(0x9888), 0x35000000 },
>+	{ _MMIO(0x9884), 0x00000007 },
>+	{ _MMIO(0x9888), 0x49000000 },
>+	{ _MMIO(0x9884), 0x00000007 },
>+	{ _MMIO(0x9888), 0x3d000000 },
>+	{ _MMIO(0x9884), 0x00000007 },
>+	{ _MMIO(0x9888), 0x31000000 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"db41edd4-d8e7-4730-ad11-b9a2d6833503",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "db41edd4-d8e7-4730-ad11-b9a2d6833503";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_cnl.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_cnl.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_cnl.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_cnl.h	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_CNL_H__
>+#define __I915_OA_CNL_H__
>+
>+void i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_glk.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_glk.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_glk.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_glk.c	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,89 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_glk.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2744), 0x00800000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x00000000 },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x00000000 },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x00000000 },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0x9840), 0x00000080 },
>+	{ _MMIO(0x9888), 0x19800000 },
>+	{ _MMIO(0x9888), 0x07800063 },
>+	{ _MMIO(0x9888), 0x11800000 },
>+	{ _MMIO(0x9888), 0x23810008 },
>+	{ _MMIO(0x9888), 0x1d950400 },
>+	{ _MMIO(0x9888), 0x0f922000 },
>+	{ _MMIO(0x9888), 0x1f908000 },
>+	{ _MMIO(0x9888), 0x37900000 },
>+	{ _MMIO(0x9888), 0x55900000 },
>+	{ _MMIO(0x9888), 0x47900000 },
>+	{ _MMIO(0x9888), 0x33900000 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"dd3fd789-e783-4204-8cd0-b671bbccb0cf",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "dd3fd789-e783-4204-8cd0-b671bbccb0cf";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_glk.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_glk.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_glk.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_glk.h	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_GLK_H__
>+#define __I915_OA_GLK_H__
>+
>+void i915_perf_load_test_config_glk(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_hsw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_hsw.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_hsw.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_hsw.c	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,119 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_hsw.h"
>+
>+static const struct i915_oa_reg b_counter_config_render_basic[] = {
>+	{ _MMIO(0x2724), 0x00800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2714), 0x00800000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_render_basic[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_render_basic[] = {
>+	{ _MMIO(0x9840), 0x00000080 },
>+	{ _MMIO(0x253a4), 0x01600000 },
>+	{ _MMIO(0x25440), 0x00100000 },
>+	{ _MMIO(0x25128), 0x00000000 },
>+	{ _MMIO(0x2691c), 0x00000800 },
>+	{ _MMIO(0x26aa0), 0x01500000 },
>+	{ _MMIO(0x26b9c), 0x00006000 },
>+	{ _MMIO(0x2791c), 0x00000800 },
>+	{ _MMIO(0x27aa0), 0x01500000 },
>+	{ _MMIO(0x27b9c), 0x00006000 },
>+	{ _MMIO(0x2641c), 0x00000400 },
>+	{ _MMIO(0x25380), 0x00000010 },
>+	{ _MMIO(0x2538c), 0x00000000 },
>+	{ _MMIO(0x25384), 0x0800aaaa },
>+	{ _MMIO(0x25400), 0x00000004 },
>+	{ _MMIO(0x2540c), 0x06029000 },
>+	{ _MMIO(0x25410), 0x00000002 },
>+	{ _MMIO(0x25404), 0x5c30ffff },
>+	{ _MMIO(0x25100), 0x00000016 },
>+	{ _MMIO(0x25110), 0x00000400 },
>+	{ _MMIO(0x25104), 0x00000000 },
>+	{ _MMIO(0x26804), 0x00001211 },
>+	{ _MMIO(0x26884), 0x00000100 },
>+	{ _MMIO(0x26900), 0x00000002 },
>+	{ _MMIO(0x26908), 0x00700000 },
>+	{ _MMIO(0x26904), 0x00000000 },
>+	{ _MMIO(0x26984), 0x00001022 },
>+	{ _MMIO(0x26a04), 0x00000011 },
>+	{ _MMIO(0x26a80), 0x00000006 },
>+	{ _MMIO(0x26a88), 0x00000c02 },
>+	{ _MMIO(0x26a84), 0x00000000 },
>+	{ _MMIO(0x26b04), 0x00001000 },
>+	{ _MMIO(0x26b80), 0x00000002 },
>+	{ _MMIO(0x26b8c), 0x00000007 },
>+	{ _MMIO(0x26b84), 0x00000000 },
>+	{ _MMIO(0x27804), 0x00004844 },
>+	{ _MMIO(0x27884), 0x00000400 },
>+	{ _MMIO(0x27900), 0x00000002 },
>+	{ _MMIO(0x27908), 0x0e000000 },
>+	{ _MMIO(0x27904), 0x00000000 },
>+	{ _MMIO(0x27984), 0x00004088 },
>+	{ _MMIO(0x27a04), 0x00000044 },
>+	{ _MMIO(0x27a80), 0x00000006 },
>+	{ _MMIO(0x27a88), 0x00018040 },
>+	{ _MMIO(0x27a84), 0x00000000 },
>+	{ _MMIO(0x27b04), 0x00004000 },
>+	{ _MMIO(0x27b80), 0x00000002 },
>+	{ _MMIO(0x27b8c), 0x000000e0 },
>+	{ _MMIO(0x27b84), 0x00000000 },
>+	{ _MMIO(0x26104), 0x00002222 },
>+	{ _MMIO(0x26184), 0x0c006666 },
>+	{ _MMIO(0x26284), 0x04000000 },
>+	{ _MMIO(0x26304), 0x04000000 },
>+	{ _MMIO(0x26400), 0x00000002 },
>+	{ _MMIO(0x26410), 0x000000a0 },
>+	{ _MMIO(0x26404), 0x00000000 },
>+	{ _MMIO(0x25420), 0x04108020 },
>+	{ _MMIO(0x25424), 0x1284a420 },
>+	{ _MMIO(0x2541c), 0x00000000 },
>+	{ _MMIO(0x25428), 0x00042049 },
>+};
>+
>+static ssize_t
>+show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"403d8832-1a27-4aa6-a64e-f5389ce7b212",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_render_basic;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_render_basic);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_render_basic;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_render_basic);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_render_basic;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_render_basic);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "403d8832-1a27-4aa6-a64e-f5389ce7b212";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_render_basic_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_hsw.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_hsw.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_hsw.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_hsw.h	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_HSW_H__
>+#define __I915_OA_HSW_H__
>+
>+void i915_perf_load_test_config_hsw(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_icl.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_icl.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_icl.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_icl.c	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,99 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_icl.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x0000ffff },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x0000ffff },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x0000ffff },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0xd04), 0x00000200 },
>+	{ _MMIO(0x9840), 0x00000000 },
>+	{ _MMIO(0x9884), 0x00000000 },
>+	{ _MMIO(0x9888), 0x10060000 },
>+	{ _MMIO(0x9888), 0x22060000 },
>+	{ _MMIO(0x9888), 0x16060000 },
>+	{ _MMIO(0x9888), 0x24060000 },
>+	{ _MMIO(0x9888), 0x18060000 },
>+	{ _MMIO(0x9888), 0x1a060000 },
>+	{ _MMIO(0x9888), 0x12060000 },
>+	{ _MMIO(0x9888), 0x14060000 },
>+	{ _MMIO(0x9888), 0x10060000 },
>+	{ _MMIO(0x9888), 0x22060000 },
>+	{ _MMIO(0x9884), 0x00000003 },
>+	{ _MMIO(0x9888), 0x16130000 },
>+	{ _MMIO(0x9888), 0x24000001 },
>+	{ _MMIO(0x9888), 0x0e130056 },
>+	{ _MMIO(0x9888), 0x10130000 },
>+	{ _MMIO(0x9888), 0x1a130000 },
>+	{ _MMIO(0x9888), 0x541f0001 },
>+	{ _MMIO(0x9888), 0x181f0000 },
>+	{ _MMIO(0x9888), 0x4c1f0000 },
>+	{ _MMIO(0x9888), 0x301f0000 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_icl(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"a291665e-244b-4b76-9b9a-01de9d3c8068",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "a291665e-244b-4b76-9b9a-01de9d3c8068";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_icl.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_icl.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_icl.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_icl.h	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_ICL_H__
>+#define __I915_OA_ICL_H__
>+
>+void i915_perf_load_test_config_icl(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_kblgt2.c	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,90 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_kblgt2.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2744), 0x00800000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x00000000 },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x00000000 },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x00000000 },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0x9840), 0x00000080 },
>+	{ _MMIO(0x9888), 0x11810000 },
>+	{ _MMIO(0x9888), 0x07810013 },
>+	{ _MMIO(0x9888), 0x1f810000 },
>+	{ _MMIO(0x9888), 0x1d810000 },
>+	{ _MMIO(0x9888), 0x1b930040 },
>+	{ _MMIO(0x9888), 0x07e54000 },
>+	{ _MMIO(0x9888), 0x1f908000 },
>+	{ _MMIO(0x9888), 0x11900000 },
>+	{ _MMIO(0x9888), 0x37900000 },
>+	{ _MMIO(0x9888), 0x53900000 },
>+	{ _MMIO(0x9888), 0x45900000 },
>+	{ _MMIO(0x9888), 0x33900000 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"baa3c7e4-52b6-4b85-801e-465a94b746dd",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "baa3c7e4-52b6-4b85-801e-465a94b746dd";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_kblgt2.h	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_KBLGT2_H__
>+#define __I915_OA_KBLGT2_H__
>+
>+void i915_perf_load_test_config_kblgt2(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_kblgt3.c	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,90 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_kblgt3.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2744), 0x00800000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x00000000 },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x00000000 },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x00000000 },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0x9840), 0x00000080 },
>+	{ _MMIO(0x9888), 0x11810000 },
>+	{ _MMIO(0x9888), 0x07810013 },
>+	{ _MMIO(0x9888), 0x1f810000 },
>+	{ _MMIO(0x9888), 0x1d810000 },
>+	{ _MMIO(0x9888), 0x1b930040 },
>+	{ _MMIO(0x9888), 0x07e54000 },
>+	{ _MMIO(0x9888), 0x1f908000 },
>+	{ _MMIO(0x9888), 0x11900000 },
>+	{ _MMIO(0x9888), 0x37900000 },
>+	{ _MMIO(0x9888), 0x53900000 },
>+	{ _MMIO(0x9888), 0x45900000 },
>+	{ _MMIO(0x9888), 0x33900000 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"f1792f32-6db2-4b50-b4b2-557128f1688d",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "f1792f32-6db2-4b50-b4b2-557128f1688d";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_kblgt3.h	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_KBLGT3_H__
>+#define __I915_OA_KBLGT3_H__
>+
>+void i915_perf_load_test_config_kblgt3(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_sklgt2.c	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,89 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_sklgt2.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x00000000 },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x00000000 },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x00000000 },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0x9840), 0x00000080 },
>+	{ _MMIO(0x9888), 0x11810000 },
>+	{ _MMIO(0x9888), 0x07810016 },
>+	{ _MMIO(0x9888), 0x1f810000 },
>+	{ _MMIO(0x9888), 0x1d810000 },
>+	{ _MMIO(0x9888), 0x1b930040 },
>+	{ _MMIO(0x9888), 0x07e54000 },
>+	{ _MMIO(0x9888), 0x1f908000 },
>+	{ _MMIO(0x9888), 0x11900000 },
>+	{ _MMIO(0x9888), 0x37900000 },
>+	{ _MMIO(0x9888), 0x53900000 },
>+	{ _MMIO(0x9888), 0x45900000 },
>+	{ _MMIO(0x9888), 0x33900000 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"1651949f-0ac0-4cb1-a06f-dafd74a407d1",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "1651949f-0ac0-4cb1-a06f-dafd74a407d1";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_sklgt2.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_sklgt2.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_sklgt2.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_sklgt2.h	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_SKLGT2_H__
>+#define __I915_OA_SKLGT2_H__
>+
>+void i915_perf_load_test_config_sklgt2(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_sklgt3.c	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,90 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_sklgt3.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2744), 0x00800000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x00000000 },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x00000000 },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x00000000 },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0x9840), 0x00000080 },
>+	{ _MMIO(0x9888), 0x11810000 },
>+	{ _MMIO(0x9888), 0x07810013 },
>+	{ _MMIO(0x9888), 0x1f810000 },
>+	{ _MMIO(0x9888), 0x1d810000 },
>+	{ _MMIO(0x9888), 0x1b930040 },
>+	{ _MMIO(0x9888), 0x07e54000 },
>+	{ _MMIO(0x9888), 0x1f908000 },
>+	{ _MMIO(0x9888), 0x11900000 },
>+	{ _MMIO(0x9888), 0x37900000 },
>+	{ _MMIO(0x9888), 0x53900000 },
>+	{ _MMIO(0x9888), 0x45900000 },
>+	{ _MMIO(0x9888), 0x33900000 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"2b985803-d3c9-4629-8a4f-634bfecba0e8",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "2b985803-d3c9-4629-8a4f-634bfecba0e8";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_sklgt3.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_sklgt3.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_sklgt3.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_sklgt3.h	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_SKLGT3_H__
>+#define __I915_OA_SKLGT3_H__
>+
>+void i915_perf_load_test_config_sklgt3(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_sklgt4.c	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,90 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#include <linux/sysfs.h>
>+
>+#include "i915_drv.h"
>+#include "i915_oa_sklgt4.h"
>+
>+static const struct i915_oa_reg b_counter_config_test_oa[] = {
>+	{ _MMIO(0x2740), 0x00000000 },
>+	{ _MMIO(0x2744), 0x00800000 },
>+	{ _MMIO(0x2714), 0xf0800000 },
>+	{ _MMIO(0x2710), 0x00000000 },
>+	{ _MMIO(0x2724), 0xf0800000 },
>+	{ _MMIO(0x2720), 0x00000000 },
>+	{ _MMIO(0x2770), 0x00000004 },
>+	{ _MMIO(0x2774), 0x00000000 },
>+	{ _MMIO(0x2778), 0x00000003 },
>+	{ _MMIO(0x277c), 0x00000000 },
>+	{ _MMIO(0x2780), 0x00000007 },
>+	{ _MMIO(0x2784), 0x00000000 },
>+	{ _MMIO(0x2788), 0x00100002 },
>+	{ _MMIO(0x278c), 0x0000fff7 },
>+	{ _MMIO(0x2790), 0x00100002 },
>+	{ _MMIO(0x2794), 0x0000ffcf },
>+	{ _MMIO(0x2798), 0x00100082 },
>+	{ _MMIO(0x279c), 0x0000ffef },
>+	{ _MMIO(0x27a0), 0x001000c2 },
>+	{ _MMIO(0x27a4), 0x0000ffe7 },
>+	{ _MMIO(0x27a8), 0x00100001 },
>+	{ _MMIO(0x27ac), 0x0000ffe7 },
>+};
>+
>+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
>+};
>+
>+static const struct i915_oa_reg mux_config_test_oa[] = {
>+	{ _MMIO(0x9840), 0x00000080 },
>+	{ _MMIO(0x9888), 0x11810000 },
>+	{ _MMIO(0x9888), 0x07810013 },
>+	{ _MMIO(0x9888), 0x1f810000 },
>+	{ _MMIO(0x9888), 0x1d810000 },
>+	{ _MMIO(0x9888), 0x1b930040 },
>+	{ _MMIO(0x9888), 0x07e54000 },
>+	{ _MMIO(0x9888), 0x1f908000 },
>+	{ _MMIO(0x9888), 0x11900000 },
>+	{ _MMIO(0x9888), 0x37900000 },
>+	{ _MMIO(0x9888), 0x53900000 },
>+	{ _MMIO(0x9888), 0x45900000 },
>+	{ _MMIO(0x9888), 0x33900000 },
>+};
>+
>+static ssize_t
>+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
>+{
>+	return sprintf(buf, "1\n");
>+}
>+
>+void
>+i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv)
>+{
>+	strlcpy(dev_priv->perf.oa.test_config.uuid,
>+		"882fa433-1f4a-4a67-a962-c741888fe5f5",
>+		sizeof(dev_priv->perf.oa.test_config.uuid));
>+	dev_priv->perf.oa.test_config.id = 1;
>+
>+	dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
>+	dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
>+	dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
>+	dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric.name = "882fa433-1f4a-4a67-a962-c741888fe5f5";
>+	dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;
>+
>+	dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;
>+
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
>+	dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_sklgt4.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_sklgt4.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/oa/i915_oa_sklgt4.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/oa/i915_oa_sklgt4.h	2019-08-31 15:01:12.237736202 -0500
>@@ -0,0 +1,15 @@
>+/*
>+ * SPDX-License-Identifier: MIT
>+ *
>+ * Copyright Â© 2018 Intel Corporation
>+ *
>+ * Autogenerated file by GPU Top : https://github.com/rib/gputop
>+ * DO NOT EDIT manually!
>+ */
>+
>+#ifndef __I915_OA_SKLGT4_H__
>+#define __I915_OA_SKLGT4_H__
>+
>+void i915_perf_load_test_config_sklgt4(struct drm_i915_private *dev_priv);
>+
>+#endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_active.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_active.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_active.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_active.c	2019-08-31 15:01:12.042736184 -0500
>@@ -4,7 +4,10 @@
>  * Copyright Â© 2018 Intel Corporation
>  */
> 
>+#include <linux/kref.h>
>+
> #include "gem/i915_gem_pm.h"
>+#include "gt/intel_gt.h"
> 
> #include "i915_selftest.h"
> 
>@@ -13,37 +16,86 @@
> 
> struct live_active {
> 	struct i915_active base;
>+	struct kref ref;
> 	bool retired;
> };
> 
>-static void __live_active_retire(struct i915_active *base)
>+static void __live_get(struct live_active *active)
>+{
>+	kref_get(&active->ref);
>+}
>+
>+static void __live_free(struct live_active *active)
>+{
>+	i915_active_fini(&active->base);
>+	kfree(active);
>+}
>+
>+static void __live_release(struct kref *ref)
>+{
>+	struct live_active *active = container_of(ref, typeof(*active), ref);
>+
>+	__live_free(active);
>+}
>+
>+static void __live_put(struct live_active *active)
>+{
>+	kref_put(&active->ref, __live_release);
>+}
>+
>+static int __live_active(struct i915_active *base)
>+{
>+	struct live_active *active = container_of(base, typeof(*active), base);
>+
>+	__live_get(active);
>+	return 0;
>+}
>+
>+static void __live_retire(struct i915_active *base)
> {
> 	struct live_active *active = container_of(base, typeof(*active), base);
> 
> 	active->retired = true;
>+	__live_put(active);
>+}
>+
>+static struct live_active *__live_alloc(struct drm_i915_private *i915)
>+{
>+	struct live_active *active;
>+
>+	active = kzalloc(sizeof(*active), GFP_KERNEL);
>+	if (!active)
>+		return NULL;
>+
>+	kref_init(&active->ref);
>+	i915_active_init(i915, &active->base, __live_active, __live_retire);
>+
>+	return active;
> }
> 
>-static int __live_active_setup(struct drm_i915_private *i915,
>-			       struct live_active *active)
>+static struct live_active *
>+__live_active_setup(struct drm_i915_private *i915)
> {
> 	struct intel_engine_cs *engine;
> 	struct i915_sw_fence *submit;
>+	struct live_active *active;
> 	enum intel_engine_id id;
> 	unsigned int count = 0;
> 	int err = 0;
> 
>-	submit = heap_fence_create(GFP_KERNEL);
>-	if (!submit)
>-		return -ENOMEM;
>+	active = __live_alloc(i915);
>+	if (!active)
>+		return ERR_PTR(-ENOMEM);
> 
>-	i915_active_init(i915, &active->base, __live_active_retire);
>-	active->retired = false;
>+	submit = heap_fence_create(GFP_KERNEL);
>+	if (!submit) {
>+		kfree(active);
>+		return ERR_PTR(-ENOMEM);
>+	}
> 
>-	if (!i915_active_acquire(&active->base)) {
>-		pr_err("First i915_active_acquire should report being idle\n");
>-		err = -EINVAL;
>+	err = i915_active_acquire(&active->base);
>+	if (err)
> 		goto out;
>-	}
> 
> 	for_each_engine(engine, i915, id) {
> 		struct i915_request *rq;
>@@ -74,74 +126,92 @@
> 		pr_err("i915_active retired before submission!\n");
> 		err = -EINVAL;
> 	}
>-	if (active->base.count != count) {
>+	if (atomic_read(&active->base.count) != count) {
> 		pr_err("i915_active not tracking all requests, found %d, expected %d\n",
>-		       active->base.count, count);
>+		       atomic_read(&active->base.count), count);
> 		err = -EINVAL;
> 	}
> 
> out:
> 	i915_sw_fence_commit(submit);
> 	heap_fence_put(submit);
>+	if (err) {
>+		__live_put(active);
>+		active = ERR_PTR(err);
>+	}
> 
>-	return err;
>+	return active;
> }
> 
> static int live_active_wait(void *arg)
> {
> 	struct drm_i915_private *i915 = arg;
>-	struct live_active active;
>+	struct live_active *active;
> 	intel_wakeref_t wakeref;
>-	int err;
>+	int err = 0;
> 
> 	/* Check that we get a callback when requests retire upon waiting */
> 
> 	mutex_lock(&i915->drm.struct_mutex);
> 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> 
>-	err = __live_active_setup(i915, &active);
>+	active = __live_active_setup(i915);
>+	if (IS_ERR(active)) {
>+		err = PTR_ERR(active);
>+		goto err;
>+	}
> 
>-	i915_active_wait(&active.base);
>-	if (!active.retired) {
>+	i915_active_wait(&active->base);
>+	if (!active->retired) {
> 		pr_err("i915_active not retired after waiting!\n");
> 		err = -EINVAL;
> 	}
> 
>-	i915_active_fini(&active.base);
>+	__live_put(active);
>+
> 	if (igt_flush_test(i915, I915_WAIT_LOCKED))
> 		err = -EIO;
> 
>+err:
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> 	mutex_unlock(&i915->drm.struct_mutex);
>+
> 	return err;
> }
> 
> static int live_active_retire(void *arg)
> {
> 	struct drm_i915_private *i915 = arg;
>-	struct live_active active;
>+	struct live_active *active;
> 	intel_wakeref_t wakeref;
>-	int err;
>+	int err = 0;
> 
> 	/* Check that we get a callback when requests are indirectly retired */
> 
> 	mutex_lock(&i915->drm.struct_mutex);
> 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> 
>-	err = __live_active_setup(i915, &active);
>+	active = __live_active_setup(i915);
>+	if (IS_ERR(active)) {
>+		err = PTR_ERR(active);
>+		goto err;
>+	}
> 
> 	/* waits for & retires all requests */
> 	if (igt_flush_test(i915, I915_WAIT_LOCKED))
> 		err = -EIO;
> 
>-	if (!active.retired) {
>+	if (!active->retired) {
> 		pr_err("i915_active not retired after flushing!\n");
> 		err = -EINVAL;
> 	}
> 
>-	i915_active_fini(&active.base);
>+	__live_put(active);
>+
>+err:
> 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> 	mutex_unlock(&i915->drm.struct_mutex);
>+
> 	return err;
> }
> 
>@@ -152,7 +222,7 @@
> 		SUBTEST(live_active_retire),
> 	};
> 
>-	if (i915_terminally_wedged(i915))
>+	if (intel_gt_is_wedged(&i915->gt))
> 		return 0;
> 
> 	return i915_subtests(tests, i915);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_gem.c	2019-08-31 15:01:12.042736184 -0500
>@@ -8,6 +8,7 @@
> 
> #include "gem/selftests/igt_gem_utils.h"
> #include "gem/selftests/mock_context.h"
>+#include "gt/intel_gt.h"
> 
> #include "i915_selftest.h"
> 
>@@ -115,7 +116,7 @@
> 	 * that runtime-pm just works.
> 	 */
> 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
>-		intel_gt_sanitize(i915, false);
>+		intel_gt_sanitize(&i915->gt, false);
> 		i915_gem_sanitize(i915);
> 		i915_gem_resume(i915);
> 	}
>@@ -154,8 +155,6 @@
> 
> 	mutex_lock(&i915->drm.struct_mutex);
> 	err = switch_to_context(i915, ctx);
>-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>-		err = -EIO;
> 	mutex_unlock(&i915->drm.struct_mutex);
> out:
> 	mock_file_free(i915, file);
>@@ -195,8 +194,6 @@
> 
> 	mutex_lock(&i915->drm.struct_mutex);
> 	err = switch_to_context(i915, ctx);
>-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>-		err = -EIO;
> 	mutex_unlock(&i915->drm.struct_mutex);
> out:
> 	mock_file_free(i915, file);
>@@ -210,8 +207,8 @@
> 		SUBTEST(igt_gem_hibernate),
> 	};
> 
>-	if (i915_terminally_wedged(i915))
>+	if (intel_gt_is_wedged(&i915->gt))
> 		return 0;
> 
>-	return i915_subtests(tests, i915);
>+	return i915_live_subtests(tests, i915);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_gem_evict.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_gem_evict.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_gem_evict.c	2019-08-31 15:01:12.042736184 -0500
>@@ -25,6 +25,7 @@
> #include "gem/i915_gem_pm.h"
> #include "gem/selftests/igt_gem_utils.h"
> #include "gem/selftests/mock_context.h"
>+#include "gt/intel_gt.h"
> 
> #include "i915_selftest.h"
> 
>@@ -557,7 +558,7 @@
> 		SUBTEST(igt_evict_contexts),
> 	};
> 
>-	if (i915_terminally_wedged(i915))
>+	if (intel_gt_is_wedged(&i915->gt))
> 		return 0;
> 
> 	return i915_subtests(tests, i915);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c	2019-08-31 15:01:12.042736184 -0500
>@@ -208,9 +208,7 @@
> 	}
> 
> err_ppgtt_cleanup:
>-	mutex_lock(&dev_priv->drm.struct_mutex);
> 	i915_vm_put(&ppgtt->vm);
>-	mutex_unlock(&dev_priv->drm.struct_mutex);
> 	return err;
> }
> 
>@@ -1195,7 +1193,7 @@
> 		iowrite32(n, vaddr + n);
> 		io_mapping_unmap_atomic(vaddr);
> 	}
>-	i915_gem_flush_ggtt_writes(i915);
>+	intel_gt_flush_ggtt_writes(ggtt->vm.gt);
> 
> 	i915_random_reorder(order, count, &prng);
> 	for (n = 0; n < count; n++) {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_live_selftests.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_live_selftests.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_live_selftests.h	2019-08-31 15:01:12.042736184 -0500
>@@ -12,7 +12,7 @@
> selftest(sanitycheck, i915_live_sanitycheck) /* keep first (igt selfcheck) */
> selftest(uncore, intel_uncore_live_selftests)
> selftest(workarounds, intel_workarounds_live_selftests)
>-selftest(timelines, i915_timeline_live_selftests)
>+selftest(timelines, intel_timeline_live_selftests)
> selftest(requests, i915_request_live_selftests)
> selftest(active, i915_active_live_selftests)
> selftest(objects, i915_gem_object_live_selftests)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h	2019-08-31 15:01:12.042736184 -0500
>@@ -15,7 +15,7 @@
> selftest(syncmap, i915_syncmap_mock_selftests)
> selftest(uncore, intel_uncore_mock_selftests)
> selftest(engine, intel_engine_cs_mock_selftests)
>-selftest(timelines, i915_timeline_mock_selftests)
>+selftest(timelines, intel_timeline_mock_selftests)
> selftest(requests, i915_request_mock_selftests)
> selftest(objects, i915_gem_object_mock_selftests)
> selftest(phys, i915_gem_phys_mock_selftests)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_request.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_request.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_request.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_request.c	2019-08-31 15:01:12.042736184 -0500
>@@ -27,6 +27,8 @@
> #include "gem/i915_gem_pm.h"
> #include "gem/selftests/mock_context.h"
> 
>+#include "gt/intel_gt.h"
>+
> #include "i915_random.h"
> #include "i915_selftest.h"
> #include "igt_live_test.h"
>@@ -73,55 +75,58 @@
> 		err = -ENOMEM;
> 		goto out_unlock;
> 	}
>+	i915_request_get(request);
> 
> 	if (i915_request_wait(request, 0, 0) != -ETIME) {
> 		pr_err("request wait (busy query) succeeded (expected timeout before submit!)\n");
>-		goto out_unlock;
>+		goto out_request;
> 	}
> 
> 	if (i915_request_wait(request, 0, T) != -ETIME) {
> 		pr_err("request wait succeeded (expected timeout before submit!)\n");
>-		goto out_unlock;
>+		goto out_request;
> 	}
> 
> 	if (i915_request_completed(request)) {
> 		pr_err("request completed before submit!!\n");
>-		goto out_unlock;
>+		goto out_request;
> 	}
> 
> 	i915_request_add(request);
> 
> 	if (i915_request_wait(request, 0, 0) != -ETIME) {
> 		pr_err("request wait (busy query) succeeded (expected timeout after submit!)\n");
>-		goto out_unlock;
>+		goto out_request;
> 	}
> 
> 	if (i915_request_completed(request)) {
> 		pr_err("request completed immediately!\n");
>-		goto out_unlock;
>+		goto out_request;
> 	}
> 
> 	if (i915_request_wait(request, 0, T / 2) != -ETIME) {
> 		pr_err("request wait succeeded (expected timeout!)\n");
>-		goto out_unlock;
>+		goto out_request;
> 	}
> 
> 	if (i915_request_wait(request, 0, T) == -ETIME) {
> 		pr_err("request wait timed out!\n");
>-		goto out_unlock;
>+		goto out_request;
> 	}
> 
> 	if (!i915_request_completed(request)) {
> 		pr_err("request not complete after waiting!\n");
>-		goto out_unlock;
>+		goto out_request;
> 	}
> 
> 	if (i915_request_wait(request, 0, T) == -ETIME) {
> 		pr_err("request wait timed out when already complete!\n");
>-		goto out_unlock;
>+		goto out_request;
> 	}
> 
> 	err = 0;
>+out_request:
>+	i915_request_put(request);
> out_unlock:
> 	mock_device_flush(i915);
> 	mutex_unlock(&i915->drm.struct_mutex);
>@@ -366,14 +371,16 @@
> 
> 		if (!wait_event_timeout(wait->wait,
> 					i915_sw_fence_done(wait),
>-					HZ / 2)) {
>+					5 * HZ)) {
> 			struct i915_request *rq = requests[count - 1];
> 
>-			pr_err("waiting for %d fences (last %llx:%lld) on %s timed out!\n",
>-			       count,
>+			pr_err("waiting for %d/%d fences (last %llx:%lld) on %s timed out!\n",
>+			       atomic_read(&wait->pending), count,
> 			       rq->fence.context, rq->fence.seqno,
> 			       t->engine->name);
>-			i915_gem_set_wedged(t->engine->i915);
>+			GEM_TRACE_DUMP();
>+
>+			intel_gt_set_wedged(t->engine->gt);
> 			GEM_BUG_ON(!i915_request_completed(rq));
> 			i915_sw_fence_wait(wait);
> 			err = -EIO;
>@@ -622,7 +629,7 @@
> 	__i915_gem_object_flush_map(obj, 0, 64);
> 	i915_gem_object_unpin_map(obj);
> 
>-	i915_gem_chipset_flush(i915);
>+	intel_gt_chipset_flush(&i915->gt);
> 
> 	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
> 	if (IS_ERR(vma)) {
>@@ -791,7 +798,7 @@
> 	__i915_gem_object_flush_map(obj, 0, 64);
> 	i915_gem_object_unpin_map(obj);
> 
>-	i915_gem_chipset_flush(i915);
>+	intel_gt_chipset_flush(&i915->gt);
> 
> 	return vma;
> 
>@@ -809,7 +816,7 @@
> 		return PTR_ERR(cmd);
> 
> 	*cmd = MI_BATCH_BUFFER_END;
>-	i915_gem_chipset_flush(batch->vm->i915);
>+	intel_gt_chipset_flush(batch->vm->gt);
> 
> 	i915_gem_object_unpin_map(batch->obj);
> 
>@@ -1031,7 +1038,7 @@
> 					      I915_MAP_WC);
> 		if (!IS_ERR(cmd)) {
> 			*cmd = MI_BATCH_BUFFER_END;
>-			i915_gem_chipset_flush(i915);
>+			intel_gt_chipset_flush(engine->gt);
> 
> 			i915_gem_object_unpin_map(request[id]->batch->obj);
> 		}
>@@ -1227,7 +1234,7 @@
> 		SUBTEST(live_breadcrumbs_smoketest),
> 	};
> 
>-	if (i915_terminally_wedged(i915))
>+	if (intel_gt_is_wedged(&i915->gt))
> 		return 0;
> 
> 	return i915_subtests(tests, i915);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_selftest.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_selftest.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_selftest.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_selftest.c	2019-08-31 15:01:12.042736184 -0500
>@@ -26,6 +26,8 @@
> #include "../i915_drv.h"
> #include "../i915_selftest.h"
> 
>+#include "igt_flush_test.h"
>+
> struct i915_selftest i915_selftest __read_mostly = {
> 	.timeout_ms = 1000,
> };
>@@ -240,7 +242,61 @@
> 	return result;
> }
> 
>+int __i915_nop_setup(void *data)
>+{
>+	return 0;
>+}
>+
>+int __i915_nop_teardown(int err, void *data)
>+{
>+	return err;
>+}
>+
>+int __i915_live_setup(void *data)
>+{
>+	struct drm_i915_private *i915 = data;
>+
>+	return intel_gt_terminally_wedged(&i915->gt);
>+}
>+
>+int __i915_live_teardown(int err, void *data)
>+{
>+	struct drm_i915_private *i915 = data;
>+
>+	mutex_lock(&i915->drm.struct_mutex);
>+	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>+		err = -EIO;
>+	mutex_unlock(&i915->drm.struct_mutex);
>+
>+	i915_gem_drain_freed_objects(i915);
>+
>+	return err;
>+}
>+
>+int __intel_gt_live_setup(void *data)
>+{
>+	struct intel_gt *gt = data;
>+
>+	return intel_gt_terminally_wedged(gt);
>+}
>+
>+int __intel_gt_live_teardown(int err, void *data)
>+{
>+	struct intel_gt *gt = data;
>+
>+	mutex_lock(&gt->i915->drm.struct_mutex);
>+	if (igt_flush_test(gt->i915, I915_WAIT_LOCKED))
>+		err = -EIO;
>+	mutex_unlock(&gt->i915->drm.struct_mutex);
>+
>+	i915_gem_drain_freed_objects(gt->i915);
>+
>+	return err;
>+}
>+
> int __i915_subtests(const char *caller,
>+		    int (*setup)(void *data),
>+		    int (*teardown)(int err, void *data),
> 		    const struct i915_subtest *st,
> 		    unsigned int count,
> 		    void *data)
>@@ -255,10 +311,17 @@
> 		if (!apply_subtest_filter(caller, st->name))
> 			continue;
> 
>+		err = setup(data);
>+		if (err) {
>+			pr_err(DRIVER_NAME "/%s: setup failed for %s\n",
>+			       caller, st->name);
>+			return err;
>+		}
>+
> 		pr_info(DRIVER_NAME ": Running %s/%s\n", caller, st->name);
> 		GEM_TRACE("Running %s/%s\n", caller, st->name);
> 
>-		err = st->func(data);
>+		err = teardown(st->func(data), data);
> 		if (err && err != -EINTR) {
> 			pr_err(DRIVER_NAME "/%s: %s failed with error %d\n",
> 			       caller, st->name, err);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_timeline.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_timeline.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_timeline.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_timeline.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,845 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2017-2018 Intel Corporation
>- */
>-
>-#include <linux/prime_numbers.h>
>-
>-#include "gem/i915_gem_pm.h"
>-
>-#include "i915_random.h"
>-#include "i915_selftest.h"
>-
>-#include "igt_flush_test.h"
>-#include "mock_gem_device.h"
>-#include "mock_timeline.h"
>-
>-static struct page *hwsp_page(struct i915_timeline *tl)
>-{
>-	struct drm_i915_gem_object *obj = tl->hwsp_ggtt->obj;
>-
>-	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
>-	return sg_page(obj->mm.pages->sgl);
>-}
>-
>-static unsigned long hwsp_cacheline(struct i915_timeline *tl)
>-{
>-	unsigned long address = (unsigned long)page_address(hwsp_page(tl));
>-
>-	return (address + tl->hwsp_offset) / CACHELINE_BYTES;
>-}
>-
>-#define CACHELINES_PER_PAGE (PAGE_SIZE / CACHELINE_BYTES)
>-
>-struct mock_hwsp_freelist {
>-	struct drm_i915_private *i915;
>-	struct radix_tree_root cachelines;
>-	struct i915_timeline **history;
>-	unsigned long count, max;
>-	struct rnd_state prng;
>-};
>-
>-enum {
>-	SHUFFLE = BIT(0),
>-};
>-
>-static void __mock_hwsp_record(struct mock_hwsp_freelist *state,
>-			       unsigned int idx,
>-			       struct i915_timeline *tl)
>-{
>-	tl = xchg(&state->history[idx], tl);
>-	if (tl) {
>-		radix_tree_delete(&state->cachelines, hwsp_cacheline(tl));
>-		i915_timeline_put(tl);
>-	}
>-}
>-
>-static int __mock_hwsp_timeline(struct mock_hwsp_freelist *state,
>-				unsigned int count,
>-				unsigned int flags)
>-{
>-	struct i915_timeline *tl;
>-	unsigned int idx;
>-
>-	while (count--) {
>-		unsigned long cacheline;
>-		int err;
>-
>-		tl = i915_timeline_create(state->i915, NULL);
>-		if (IS_ERR(tl))
>-			return PTR_ERR(tl);
>-
>-		cacheline = hwsp_cacheline(tl);
>-		err = radix_tree_insert(&state->cachelines, cacheline, tl);
>-		if (err) {
>-			if (err == -EEXIST) {
>-				pr_err("HWSP cacheline %lu already used; duplicate allocation!\n",
>-				       cacheline);
>-			}
>-			i915_timeline_put(tl);
>-			return err;
>-		}
>-
>-		idx = state->count++ % state->max;
>-		__mock_hwsp_record(state, idx, tl);
>-	}
>-
>-	if (flags & SHUFFLE)
>-		i915_prandom_shuffle(state->history,
>-				     sizeof(*state->history),
>-				     min(state->count, state->max),
>-				     &state->prng);
>-
>-	count = i915_prandom_u32_max_state(min(state->count, state->max),
>-					   &state->prng);
>-	while (count--) {
>-		idx = --state->count % state->max;
>-		__mock_hwsp_record(state, idx, NULL);
>-	}
>-
>-	return 0;
>-}
>-
>-static int mock_hwsp_freelist(void *arg)
>-{
>-	struct mock_hwsp_freelist state;
>-	const struct {
>-		const char *name;
>-		unsigned int flags;
>-	} phases[] = {
>-		{ "linear", 0 },
>-		{ "shuffled", SHUFFLE },
>-		{ },
>-	}, *p;
>-	unsigned int na;
>-	int err = 0;
>-
>-	INIT_RADIX_TREE(&state.cachelines, GFP_KERNEL);
>-	state.prng = I915_RND_STATE_INITIALIZER(i915_selftest.random_seed);
>-
>-	state.i915 = mock_gem_device();
>-	if (!state.i915)
>-		return -ENOMEM;
>-
>-	/*
>-	 * Create a bunch of timelines and check that their HWSP do not overlap.
>-	 * Free some, and try again.
>-	 */
>-
>-	state.max = PAGE_SIZE / sizeof(*state.history);
>-	state.count = 0;
>-	state.history = kcalloc(state.max, sizeof(*state.history), GFP_KERNEL);
>-	if (!state.history) {
>-		err = -ENOMEM;
>-		goto err_put;
>-	}
>-
>-	mutex_lock(&state.i915->drm.struct_mutex);
>-	for (p = phases; p->name; p++) {
>-		pr_debug("%s(%s)\n", __func__, p->name);
>-		for_each_prime_number_from(na, 1, 2 * CACHELINES_PER_PAGE) {
>-			err = __mock_hwsp_timeline(&state, na, p->flags);
>-			if (err)
>-				goto out;
>-		}
>-	}
>-
>-out:
>-	for (na = 0; na < state.max; na++)
>-		__mock_hwsp_record(&state, na, NULL);
>-	mutex_unlock(&state.i915->drm.struct_mutex);
>-	kfree(state.history);
>-err_put:
>-	drm_dev_put(&state.i915->drm);
>-	return err;
>-}
>-
>-struct __igt_sync {
>-	const char *name;
>-	u32 seqno;
>-	bool expected;
>-	bool set;
>-};
>-
>-static int __igt_sync(struct i915_timeline *tl,
>-		      u64 ctx,
>-		      const struct __igt_sync *p,
>-		      const char *name)
>-{
>-	int ret;
>-
>-	if (__i915_timeline_sync_is_later(tl, ctx, p->seqno) != p->expected) {
>-		pr_err("%s: %s(ctx=%llu, seqno=%u) expected passed %s but failed\n",
>-		       name, p->name, ctx, p->seqno, yesno(p->expected));
>-		return -EINVAL;
>-	}
>-
>-	if (p->set) {
>-		ret = __i915_timeline_sync_set(tl, ctx, p->seqno);
>-		if (ret)
>-			return ret;
>-	}
>-
>-	return 0;
>-}
>-
>-static int igt_sync(void *arg)
>-{
>-	const struct __igt_sync pass[] = {
>-		{ "unset", 0, false, false },
>-		{ "new", 0, false, true },
>-		{ "0a", 0, true, true },
>-		{ "1a", 1, false, true },
>-		{ "1b", 1, true, true },
>-		{ "0b", 0, true, false },
>-		{ "2a", 2, false, true },
>-		{ "4", 4, false, true },
>-		{ "INT_MAX", INT_MAX, false, true },
>-		{ "INT_MAX-1", INT_MAX-1, true, false },
>-		{ "INT_MAX+1", (u32)INT_MAX+1, false, true },
>-		{ "INT_MAX", INT_MAX, true, false },
>-		{ "UINT_MAX", UINT_MAX, false, true },
>-		{ "wrap", 0, false, true },
>-		{ "unwrap", UINT_MAX, true, false },
>-		{},
>-	}, *p;
>-	struct i915_timeline tl;
>-	int order, offset;
>-	int ret = -ENODEV;
>-
>-	mock_timeline_init(&tl, 0);
>-	for (p = pass; p->name; p++) {
>-		for (order = 1; order < 64; order++) {
>-			for (offset = -1; offset <= (order > 1); offset++) {
>-				u64 ctx = BIT_ULL(order) + offset;
>-
>-				ret = __igt_sync(&tl, ctx, p, "1");
>-				if (ret)
>-					goto out;
>-			}
>-		}
>-	}
>-	mock_timeline_fini(&tl);
>-
>-	mock_timeline_init(&tl, 0);
>-	for (order = 1; order < 64; order++) {
>-		for (offset = -1; offset <= (order > 1); offset++) {
>-			u64 ctx = BIT_ULL(order) + offset;
>-
>-			for (p = pass; p->name; p++) {
>-				ret = __igt_sync(&tl, ctx, p, "2");
>-				if (ret)
>-					goto out;
>-			}
>-		}
>-	}
>-
>-out:
>-	mock_timeline_fini(&tl);
>-	return ret;
>-}
>-
>-static unsigned int random_engine(struct rnd_state *rnd)
>-{
>-	return i915_prandom_u32_max_state(I915_NUM_ENGINES, rnd);
>-}
>-
>-static int bench_sync(void *arg)
>-{
>-	struct rnd_state prng;
>-	struct i915_timeline tl;
>-	unsigned long end_time, count;
>-	u64 prng32_1M;
>-	ktime_t kt;
>-	int order, last_order;
>-
>-	mock_timeline_init(&tl, 0);
>-
>-	/* Lookups from cache are very fast and so the random number generation
>-	 * and the loop itself becomes a significant factor in the per-iteration
>-	 * timings. We try to compensate the results by measuring the overhead
>-	 * of the prng and subtract it from the reported results.
>-	 */
>-	prandom_seed_state(&prng, i915_selftest.random_seed);
>-	count = 0;
>-	kt = ktime_get();
>-	end_time = jiffies + HZ/10;
>-	do {
>-		u32 x;
>-
>-		/* Make sure the compiler doesn't optimise away the prng call */
>-		WRITE_ONCE(x, prandom_u32_state(&prng));
>-
>-		count++;
>-	} while (!time_after(jiffies, end_time));
>-	kt = ktime_sub(ktime_get(), kt);
>-	pr_debug("%s: %lu random evaluations, %lluns/prng\n",
>-		 __func__, count, (long long)div64_ul(ktime_to_ns(kt), count));
>-	prng32_1M = div64_ul(ktime_to_ns(kt) << 20, count);
>-
>-	/* Benchmark (only) setting random context ids */
>-	prandom_seed_state(&prng, i915_selftest.random_seed);
>-	count = 0;
>-	kt = ktime_get();
>-	end_time = jiffies + HZ/10;
>-	do {
>-		u64 id = i915_prandom_u64_state(&prng);
>-
>-		__i915_timeline_sync_set(&tl, id, 0);
>-		count++;
>-	} while (!time_after(jiffies, end_time));
>-	kt = ktime_sub(ktime_get(), kt);
>-	kt = ktime_sub_ns(kt, (count * prng32_1M * 2) >> 20);
>-	pr_info("%s: %lu random insertions, %lluns/insert\n",
>-		__func__, count, (long long)div64_ul(ktime_to_ns(kt), count));
>-
>-	/* Benchmark looking up the exact same context ids as we just set */
>-	prandom_seed_state(&prng, i915_selftest.random_seed);
>-	end_time = count;
>-	kt = ktime_get();
>-	while (end_time--) {
>-		u64 id = i915_prandom_u64_state(&prng);
>-
>-		if (!__i915_timeline_sync_is_later(&tl, id, 0)) {
>-			mock_timeline_fini(&tl);
>-			pr_err("Lookup of %llu failed\n", id);
>-			return -EINVAL;
>-		}
>-	}
>-	kt = ktime_sub(ktime_get(), kt);
>-	kt = ktime_sub_ns(kt, (count * prng32_1M * 2) >> 20);
>-	pr_info("%s: %lu random lookups, %lluns/lookup\n",
>-		__func__, count, (long long)div64_ul(ktime_to_ns(kt), count));
>-
>-	mock_timeline_fini(&tl);
>-	cond_resched();
>-
>-	mock_timeline_init(&tl, 0);
>-
>-	/* Benchmark setting the first N (in order) contexts */
>-	count = 0;
>-	kt = ktime_get();
>-	end_time = jiffies + HZ/10;
>-	do {
>-		__i915_timeline_sync_set(&tl, count++, 0);
>-	} while (!time_after(jiffies, end_time));
>-	kt = ktime_sub(ktime_get(), kt);
>-	pr_info("%s: %lu in-order insertions, %lluns/insert\n",
>-		__func__, count, (long long)div64_ul(ktime_to_ns(kt), count));
>-
>-	/* Benchmark looking up the exact same context ids as we just set */
>-	end_time = count;
>-	kt = ktime_get();
>-	while (end_time--) {
>-		if (!__i915_timeline_sync_is_later(&tl, end_time, 0)) {
>-			pr_err("Lookup of %lu failed\n", end_time);
>-			mock_timeline_fini(&tl);
>-			return -EINVAL;
>-		}
>-	}
>-	kt = ktime_sub(ktime_get(), kt);
>-	pr_info("%s: %lu in-order lookups, %lluns/lookup\n",
>-		__func__, count, (long long)div64_ul(ktime_to_ns(kt), count));
>-
>-	mock_timeline_fini(&tl);
>-	cond_resched();
>-
>-	mock_timeline_init(&tl, 0);
>-
>-	/* Benchmark searching for a random context id and maybe changing it */
>-	prandom_seed_state(&prng, i915_selftest.random_seed);
>-	count = 0;
>-	kt = ktime_get();
>-	end_time = jiffies + HZ/10;
>-	do {
>-		u32 id = random_engine(&prng);
>-		u32 seqno = prandom_u32_state(&prng);
>-
>-		if (!__i915_timeline_sync_is_later(&tl, id, seqno))
>-			__i915_timeline_sync_set(&tl, id, seqno);
>-
>-		count++;
>-	} while (!time_after(jiffies, end_time));
>-	kt = ktime_sub(ktime_get(), kt);
>-	kt = ktime_sub_ns(kt, (count * prng32_1M * 2) >> 20);
>-	pr_info("%s: %lu repeated insert/lookups, %lluns/op\n",
>-		__func__, count, (long long)div64_ul(ktime_to_ns(kt), count));
>-	mock_timeline_fini(&tl);
>-	cond_resched();
>-
>-	/* Benchmark searching for a known context id and changing the seqno */
>-	for (last_order = 1, order = 1; order < 32;
>-	     ({ int tmp = last_order; last_order = order; order += tmp; })) {
>-		unsigned int mask = BIT(order) - 1;
>-
>-		mock_timeline_init(&tl, 0);
>-
>-		count = 0;
>-		kt = ktime_get();
>-		end_time = jiffies + HZ/10;
>-		do {
>-			/* Without assuming too many details of the underlying
>-			 * implementation, try to identify its phase-changes
>-			 * (if any)!
>-			 */
>-			u64 id = (u64)(count & mask) << order;
>-
>-			__i915_timeline_sync_is_later(&tl, id, 0);
>-			__i915_timeline_sync_set(&tl, id, 0);
>-
>-			count++;
>-		} while (!time_after(jiffies, end_time));
>-		kt = ktime_sub(ktime_get(), kt);
>-		pr_info("%s: %lu cyclic/%d insert/lookups, %lluns/op\n",
>-			__func__, count, order,
>-			(long long)div64_ul(ktime_to_ns(kt), count));
>-		mock_timeline_fini(&tl);
>-		cond_resched();
>-	}
>-
>-	return 0;
>-}
>-
>-int i915_timeline_mock_selftests(void)
>-{
>-	static const struct i915_subtest tests[] = {
>-		SUBTEST(mock_hwsp_freelist),
>-		SUBTEST(igt_sync),
>-		SUBTEST(bench_sync),
>-	};
>-
>-	return i915_subtests(tests, NULL);
>-}
>-
>-static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
>-{
>-	u32 *cs;
>-
>-	cs = intel_ring_begin(rq, 4);
>-	if (IS_ERR(cs))
>-		return PTR_ERR(cs);
>-
>-	if (INTEL_GEN(rq->i915) >= 8) {
>-		*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>-		*cs++ = addr;
>-		*cs++ = 0;
>-		*cs++ = value;
>-	} else if (INTEL_GEN(rq->i915) >= 4) {
>-		*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>-		*cs++ = 0;
>-		*cs++ = addr;
>-		*cs++ = value;
>-	} else {
>-		*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
>-		*cs++ = addr;
>-		*cs++ = value;
>-		*cs++ = MI_NOOP;
>-	}
>-
>-	intel_ring_advance(rq, cs);
>-
>-	return 0;
>-}
>-
>-static struct i915_request *
>-tl_write(struct i915_timeline *tl, struct intel_engine_cs *engine, u32 value)
>-{
>-	struct i915_request *rq;
>-	int err;
>-
>-	lockdep_assert_held(&tl->i915->drm.struct_mutex); /* lazy rq refs */
>-
>-	err = i915_timeline_pin(tl);
>-	if (err) {
>-		rq = ERR_PTR(err);
>-		goto out;
>-	}
>-
>-	rq = i915_request_create(engine->kernel_context);
>-	if (IS_ERR(rq))
>-		goto out_unpin;
>-
>-	err = emit_ggtt_store_dw(rq, tl->hwsp_offset, value);
>-	i915_request_add(rq);
>-	if (err)
>-		rq = ERR_PTR(err);
>-
>-out_unpin:
>-	i915_timeline_unpin(tl);
>-out:
>-	if (IS_ERR(rq))
>-		pr_err("Failed to write to timeline!\n");
>-	return rq;
>-}
>-
>-static struct i915_timeline *
>-checked_i915_timeline_create(struct drm_i915_private *i915)
>-{
>-	struct i915_timeline *tl;
>-
>-	tl = i915_timeline_create(i915, NULL);
>-	if (IS_ERR(tl))
>-		return tl;
>-
>-	if (*tl->hwsp_seqno != tl->seqno) {
>-		pr_err("Timeline created with incorrect breadcrumb, found %x, expected %x\n",
>-		       *tl->hwsp_seqno, tl->seqno);
>-		i915_timeline_put(tl);
>-		return ERR_PTR(-EINVAL);
>-	}
>-
>-	return tl;
>-}
>-
>-static int live_hwsp_engine(void *arg)
>-{
>-#define NUM_TIMELINES 4096
>-	struct drm_i915_private *i915 = arg;
>-	struct i915_timeline **timelines;
>-	struct intel_engine_cs *engine;
>-	enum intel_engine_id id;
>-	intel_wakeref_t wakeref;
>-	unsigned long count, n;
>-	int err = 0;
>-
>-	/*
>-	 * Create a bunch of timelines and check we can write
>-	 * independently to each of their breadcrumb slots.
>-	 */
>-
>-	timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES,
>-				   sizeof(*timelines),
>-				   GFP_KERNEL);
>-	if (!timelines)
>-		return -ENOMEM;
>-
>-	mutex_lock(&i915->drm.struct_mutex);
>-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>-
>-	count = 0;
>-	for_each_engine(engine, i915, id) {
>-		if (!intel_engine_can_store_dword(engine))
>-			continue;
>-
>-		for (n = 0; n < NUM_TIMELINES; n++) {
>-			struct i915_timeline *tl;
>-			struct i915_request *rq;
>-
>-			tl = checked_i915_timeline_create(i915);
>-			if (IS_ERR(tl)) {
>-				err = PTR_ERR(tl);
>-				goto out;
>-			}
>-
>-			rq = tl_write(tl, engine, count);
>-			if (IS_ERR(rq)) {
>-				i915_timeline_put(tl);
>-				err = PTR_ERR(rq);
>-				goto out;
>-			}
>-
>-			timelines[count++] = tl;
>-		}
>-	}
>-
>-out:
>-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>-		err = -EIO;
>-
>-	for (n = 0; n < count; n++) {
>-		struct i915_timeline *tl = timelines[n];
>-
>-		if (!err && *tl->hwsp_seqno != n) {
>-			pr_err("Invalid seqno stored in timeline %lu, found 0x%x\n",
>-			       n, *tl->hwsp_seqno);
>-			err = -EINVAL;
>-		}
>-		i915_timeline_put(tl);
>-	}
>-
>-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>-	mutex_unlock(&i915->drm.struct_mutex);
>-
>-	kvfree(timelines);
>-
>-	return err;
>-#undef NUM_TIMELINES
>-}
>-
>-static int live_hwsp_alternate(void *arg)
>-{
>-#define NUM_TIMELINES 4096
>-	struct drm_i915_private *i915 = arg;
>-	struct i915_timeline **timelines;
>-	struct intel_engine_cs *engine;
>-	enum intel_engine_id id;
>-	intel_wakeref_t wakeref;
>-	unsigned long count, n;
>-	int err = 0;
>-
>-	/*
>-	 * Create a bunch of timelines and check we can write
>-	 * independently to each of their breadcrumb slots with adjacent
>-	 * engines.
>-	 */
>-
>-	timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES,
>-				   sizeof(*timelines),
>-				   GFP_KERNEL);
>-	if (!timelines)
>-		return -ENOMEM;
>-
>-	mutex_lock(&i915->drm.struct_mutex);
>-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>-
>-	count = 0;
>-	for (n = 0; n < NUM_TIMELINES; n++) {
>-		for_each_engine(engine, i915, id) {
>-			struct i915_timeline *tl;
>-			struct i915_request *rq;
>-
>-			if (!intel_engine_can_store_dword(engine))
>-				continue;
>-
>-			tl = checked_i915_timeline_create(i915);
>-			if (IS_ERR(tl)) {
>-				err = PTR_ERR(tl);
>-				goto out;
>-			}
>-
>-			rq = tl_write(tl, engine, count);
>-			if (IS_ERR(rq)) {
>-				i915_timeline_put(tl);
>-				err = PTR_ERR(rq);
>-				goto out;
>-			}
>-
>-			timelines[count++] = tl;
>-		}
>-	}
>-
>-out:
>-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>-		err = -EIO;
>-
>-	for (n = 0; n < count; n++) {
>-		struct i915_timeline *tl = timelines[n];
>-
>-		if (!err && *tl->hwsp_seqno != n) {
>-			pr_err("Invalid seqno stored in timeline %lu, found 0x%x\n",
>-			       n, *tl->hwsp_seqno);
>-			err = -EINVAL;
>-		}
>-		i915_timeline_put(tl);
>-	}
>-
>-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>-	mutex_unlock(&i915->drm.struct_mutex);
>-
>-	kvfree(timelines);
>-
>-	return err;
>-#undef NUM_TIMELINES
>-}
>-
>-static int live_hwsp_wrap(void *arg)
>-{
>-	struct drm_i915_private *i915 = arg;
>-	struct intel_engine_cs *engine;
>-	struct i915_timeline *tl;
>-	enum intel_engine_id id;
>-	intel_wakeref_t wakeref;
>-	int err = 0;
>-
>-	/*
>-	 * Across a seqno wrap, we need to keep the old cacheline alive for
>-	 * foreign GPU references.
>-	 */
>-
>-	mutex_lock(&i915->drm.struct_mutex);
>-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>-
>-	tl = i915_timeline_create(i915, NULL);
>-	if (IS_ERR(tl)) {
>-		err = PTR_ERR(tl);
>-		goto out_rpm;
>-	}
>-	if (!tl->has_initial_breadcrumb || !tl->hwsp_cacheline)
>-		goto out_free;
>-
>-	err = i915_timeline_pin(tl);
>-	if (err)
>-		goto out_free;
>-
>-	for_each_engine(engine, i915, id) {
>-		const u32 *hwsp_seqno[2];
>-		struct i915_request *rq;
>-		u32 seqno[2];
>-
>-		if (!intel_engine_can_store_dword(engine))
>-			continue;
>-
>-		rq = i915_request_create(engine->kernel_context);
>-		if (IS_ERR(rq)) {
>-			err = PTR_ERR(rq);
>-			goto out;
>-		}
>-
>-		tl->seqno = -4u;
>-
>-		err = i915_timeline_get_seqno(tl, rq, &seqno[0]);
>-		if (err) {
>-			i915_request_add(rq);
>-			goto out;
>-		}
>-		pr_debug("seqno[0]:%08x, hwsp_offset:%08x\n",
>-			 seqno[0], tl->hwsp_offset);
>-
>-		err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[0]);
>-		if (err) {
>-			i915_request_add(rq);
>-			goto out;
>-		}
>-		hwsp_seqno[0] = tl->hwsp_seqno;
>-
>-		err = i915_timeline_get_seqno(tl, rq, &seqno[1]);
>-		if (err) {
>-			i915_request_add(rq);
>-			goto out;
>-		}
>-		pr_debug("seqno[1]:%08x, hwsp_offset:%08x\n",
>-			 seqno[1], tl->hwsp_offset);
>-
>-		err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[1]);
>-		if (err) {
>-			i915_request_add(rq);
>-			goto out;
>-		}
>-		hwsp_seqno[1] = tl->hwsp_seqno;
>-
>-		/* With wrap should come a new hwsp */
>-		GEM_BUG_ON(seqno[1] >= seqno[0]);
>-		GEM_BUG_ON(hwsp_seqno[0] == hwsp_seqno[1]);
>-
>-		i915_request_add(rq);
>-
>-		if (i915_request_wait(rq, 0, HZ / 5) < 0) {
>-			pr_err("Wait for timeline writes timed out!\n");
>-			err = -EIO;
>-			goto out;
>-		}
>-
>-		if (*hwsp_seqno[0] != seqno[0] || *hwsp_seqno[1] != seqno[1]) {
>-			pr_err("Bad timeline values: found (%x, %x), expected (%x, %x)\n",
>-			       *hwsp_seqno[0], *hwsp_seqno[1],
>-			       seqno[0], seqno[1]);
>-			err = -EINVAL;
>-			goto out;
>-		}
>-
>-		i915_retire_requests(i915); /* recycle HWSP */
>-	}
>-
>-out:
>-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>-		err = -EIO;
>-
>-	i915_timeline_unpin(tl);
>-out_free:
>-	i915_timeline_put(tl);
>-out_rpm:
>-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>-	mutex_unlock(&i915->drm.struct_mutex);
>-
>-	return err;
>-}
>-
>-static int live_hwsp_recycle(void *arg)
>-{
>-	struct drm_i915_private *i915 = arg;
>-	struct intel_engine_cs *engine;
>-	enum intel_engine_id id;
>-	intel_wakeref_t wakeref;
>-	unsigned long count;
>-	int err = 0;
>-
>-	/*
>-	 * Check seqno writes into one timeline at a time. We expect to
>-	 * recycle the breadcrumb slot between iterations and neither
>-	 * want to confuse ourselves or the GPU.
>-	 */
>-
>-	mutex_lock(&i915->drm.struct_mutex);
>-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>-
>-	count = 0;
>-	for_each_engine(engine, i915, id) {
>-		IGT_TIMEOUT(end_time);
>-
>-		if (!intel_engine_can_store_dword(engine))
>-			continue;
>-
>-		do {
>-			struct i915_timeline *tl;
>-			struct i915_request *rq;
>-
>-			tl = checked_i915_timeline_create(i915);
>-			if (IS_ERR(tl)) {
>-				err = PTR_ERR(tl);
>-				goto out;
>-			}
>-
>-			rq = tl_write(tl, engine, count);
>-			if (IS_ERR(rq)) {
>-				i915_timeline_put(tl);
>-				err = PTR_ERR(rq);
>-				goto out;
>-			}
>-
>-			if (i915_request_wait(rq, 0, HZ / 5) < 0) {
>-				pr_err("Wait for timeline writes timed out!\n");
>-				i915_timeline_put(tl);
>-				err = -EIO;
>-				goto out;
>-			}
>-
>-			if (*tl->hwsp_seqno != count) {
>-				pr_err("Invalid seqno stored in timeline %lu, found 0x%x\n",
>-				       count, *tl->hwsp_seqno);
>-				err = -EINVAL;
>-			}
>-
>-			i915_timeline_put(tl);
>-			count++;
>-
>-			if (err)
>-				goto out;
>-
>-			i915_timelines_park(i915); /* Encourage recycling! */
>-		} while (!__igt_timeout(end_time, NULL));
>-	}
>-
>-out:
>-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
>-		err = -EIO;
>-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>-	mutex_unlock(&i915->drm.struct_mutex);
>-
>-	return err;
>-}
>-
>-int i915_timeline_live_selftests(struct drm_i915_private *i915)
>-{
>-	static const struct i915_subtest tests[] = {
>-		SUBTEST(live_hwsp_recycle),
>-		SUBTEST(live_hwsp_engine),
>-		SUBTEST(live_hwsp_alternate),
>-		SUBTEST(live_hwsp_wrap),
>-	};
>-
>-	if (i915_terminally_wedged(i915))
>-		return 0;
>-
>-	return i915_subtests(tests, i915);
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_vma.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_vma.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/i915_vma.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/i915_vma.c	2019-08-31 15:01:12.042736184 -0500
>@@ -193,6 +193,8 @@
> 			list_del_init(&ctx->link);
> 			mock_context_close(ctx);
> 		}
>+
>+		cond_resched();
> 	}
> 
> end:
>@@ -341,6 +343,8 @@
> 				goto out;
> 			}
> 		}
>+
>+		cond_resched();
> 	}
> 
> 	err = 0;
>@@ -597,6 +601,8 @@
> 					}
> 
> 					i915_vma_unpin(vma);
>+
>+					cond_resched();
> 				}
> 			}
> 		}
>@@ -752,6 +758,8 @@
> 
> 				i915_vma_unpin(vma);
> 				nvma++;
>+
>+				cond_resched();
> 			}
> 		}
> 
>@@ -961,6 +969,8 @@
> 				}
> 			}
> 			i915_vma_unpin_iomap(vma);
>+
>+			cond_resched();
> 		}
> 	}
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/igt_flush_test.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/igt_flush_test.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/igt_flush_test.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/igt_flush_test.c	2019-08-31 15:01:12.042736184 -0500
>@@ -5,6 +5,7 @@
>  */
> 
> #include "gem/i915_gem_context.h"
>+#include "gt/intel_gt.h"
> 
> #include "i915_drv.h"
> #include "i915_selftest.h"
>@@ -13,7 +14,7 @@
> 
> int igt_flush_test(struct drm_i915_private *i915, unsigned int flags)
> {
>-	int ret = i915_terminally_wedged(i915) ? -EIO : 0;
>+	int ret = intel_gt_is_wedged(&i915->gt) ? -EIO : 0;
> 	int repeat = !!(flags & I915_WAIT_LOCKED);
> 
> 	cond_resched();
>@@ -27,7 +28,7 @@
> 				  __builtin_return_address(0));
> 			GEM_TRACE_DUMP();
> 
>-			i915_gem_set_wedged(i915);
>+			intel_gt_set_wedged(&i915->gt);
> 			repeat = 0;
> 			ret = -EIO;
> 		}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/igt_reset.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/igt_reset.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/igt_reset.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/igt_reset.c	2019-08-31 15:01:12.042736184 -0500
>@@ -7,47 +7,45 @@
> #include "igt_reset.h"
> 
> #include "gt/intel_engine.h"
>+#include "gt/intel_gt.h"
> 
> #include "../i915_drv.h"
> 
>-void igt_global_reset_lock(struct drm_i915_private *i915)
>+void igt_global_reset_lock(struct intel_gt *gt)
> {
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
> 
>-	pr_debug("%s: current gpu_error=%08lx\n",
>-		 __func__, i915->gpu_error.flags);
>+	pr_debug("%s: current gpu_error=%08lx\n", __func__, gt->reset.flags);
> 
>-	while (test_and_set_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags))
>-		wait_event(i915->gpu_error.reset_queue,
>-			   !test_bit(I915_RESET_BACKOFF,
>-				     &i915->gpu_error.flags));
>+	while (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags))
>+		wait_event(gt->reset.queue,
>+			   !test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
> 
>-	for_each_engine(engine, i915, id) {
>+	for_each_engine(engine, gt->i915, id) {
> 		while (test_and_set_bit(I915_RESET_ENGINE + id,
>-					&i915->gpu_error.flags))
>-			wait_on_bit(&i915->gpu_error.flags,
>-				    I915_RESET_ENGINE + id,
>+					&gt->reset.flags))
>+			wait_on_bit(&gt->reset.flags, I915_RESET_ENGINE + id,
> 				    TASK_UNINTERRUPTIBLE);
> 	}
> }
> 
>-void igt_global_reset_unlock(struct drm_i915_private *i915)
>+void igt_global_reset_unlock(struct intel_gt *gt)
> {
> 	struct intel_engine_cs *engine;
> 	enum intel_engine_id id;
> 
>-	for_each_engine(engine, i915, id)
>-		clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>+	for_each_engine(engine, gt->i915, id)
>+		clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
> 
>-	clear_bit(I915_RESET_BACKOFF, &i915->gpu_error.flags);
>-	wake_up_all(&i915->gpu_error.reset_queue);
>+	clear_bit(I915_RESET_BACKOFF, &gt->reset.flags);
>+	wake_up_all(&gt->reset.queue);
> }
> 
>-bool igt_force_reset(struct drm_i915_private *i915)
>+bool igt_force_reset(struct intel_gt *gt)
> {
>-	i915_gem_set_wedged(i915);
>-	i915_reset(i915, 0, NULL);
>+	intel_gt_set_wedged(gt);
>+	intel_gt_reset(gt, 0, NULL);
> 
>-	return !i915_reset_failed(i915);
>+	return !intel_gt_is_wedged(gt);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/igt_reset.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/igt_reset.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/igt_reset.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/igt_reset.h	2019-08-31 15:01:12.042736184 -0500
>@@ -7,10 +7,12 @@
> #ifndef __I915_SELFTESTS_IGT_RESET_H__
> #define __I915_SELFTESTS_IGT_RESET_H__
> 
>-#include "../i915_drv.h"
>+#include <linux/types.h>
> 
>-void igt_global_reset_lock(struct drm_i915_private *i915);
>-void igt_global_reset_unlock(struct drm_i915_private *i915);
>-bool igt_force_reset(struct drm_i915_private *i915);
>+struct intel_gt;
>+
>+void igt_global_reset_lock(struct intel_gt *gt);
>+void igt_global_reset_unlock(struct intel_gt *gt);
>+bool igt_force_reset(struct intel_gt *gt);
> 
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/igt_spinner.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/igt_spinner.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/igt_spinner.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/igt_spinner.c	2019-08-31 15:01:12.042736184 -0500
>@@ -3,6 +3,7 @@
>  *
>  * Copyright Â© 2018 Intel Corporation
>  */
>+#include "gt/intel_gt.h"
> 
> #include "gem/selftests/igt_gem_utils.h"
> 
>@@ -18,6 +19,7 @@
> 
> 	memset(spin, 0, sizeof(*spin));
> 	spin->i915 = i915;
>+	spin->gt = &i915->gt;
> 
> 	spin->hws = i915_gem_object_create_internal(i915, PAGE_SIZE);
> 	if (IS_ERR(spin->hws)) {
>@@ -94,6 +96,8 @@
> 	u32 *batch;
> 	int err;
> 
>+	spin->gt = engine->gt;
>+
> 	vma = i915_vma_instance(spin->obj, ctx->vm, NULL);
> 	if (IS_ERR(vma))
> 		return ERR_CAST(vma);
>@@ -138,7 +142,7 @@
> 	*batch++ = upper_32_bits(vma->node.start);
> 	*batch++ = MI_BATCH_BUFFER_END; /* not reached */
> 
>-	i915_gem_chipset_flush(spin->i915);
>+	intel_gt_chipset_flush(engine->gt);
> 
> 	if (engine->emit_init_breadcrumb &&
> 	    rq->timeline->has_initial_breadcrumb) {
>@@ -172,7 +176,7 @@
> void igt_spinner_end(struct igt_spinner *spin)
> {
> 	*spin->batch = MI_BATCH_BUFFER_END;
>-	i915_gem_chipset_flush(spin->i915);
>+	intel_gt_chipset_flush(spin->gt);
> }
> 
> void igt_spinner_fini(struct igt_spinner *spin)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/igt_spinner.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/igt_spinner.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/igt_spinner.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/igt_spinner.h	2019-08-31 15:01:12.043736185 -0500
>@@ -14,8 +14,11 @@
> #include "i915_request.h"
> #include "i915_selftest.h"
> 
>+struct intel_gt;
>+
> struct igt_spinner {
> 	struct drm_i915_private *i915;
>+	struct intel_gt *gt;
> 	struct drm_i915_gem_object *hws;
> 	struct drm_i915_gem_object *obj;
> 	u32 *batch;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/igt_wedge_me.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/igt_wedge_me.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/igt_wedge_me.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/igt_wedge_me.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,58 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2018 Intel Corporation
>- */
>-
>-#ifndef IGT_WEDGE_ME_H
>-#define IGT_WEDGE_ME_H
>-
>-#include <linux/workqueue.h>
>-
>-#include "../i915_gem.h"
>-
>-struct drm_i915_private;
>-
>-struct igt_wedge_me {
>-	struct delayed_work work;
>-	struct drm_i915_private *i915;
>-	const char *name;
>-};
>-
>-static void __igt_wedge_me(struct work_struct *work)
>-{
>-	struct igt_wedge_me *w = container_of(work, typeof(*w), work.work);
>-
>-	pr_err("%s timed out, cancelling test.\n", w->name);
>-
>-	GEM_TRACE("%s timed out.\n", w->name);
>-	GEM_TRACE_DUMP();
>-
>-	i915_gem_set_wedged(w->i915);
>-}
>-
>-static void __igt_init_wedge(struct igt_wedge_me *w,
>-			     struct drm_i915_private *i915,
>-			     long timeout,
>-			     const char *name)
>-{
>-	w->i915 = i915;
>-	w->name = name;
>-
>-	INIT_DELAYED_WORK_ONSTACK(&w->work, __igt_wedge_me);
>-	schedule_delayed_work(&w->work, timeout);
>-}
>-
>-static void __igt_fini_wedge(struct igt_wedge_me *w)
>-{
>-	cancel_delayed_work_sync(&w->work);
>-	destroy_delayed_work_on_stack(&w->work);
>-	w->i915 = NULL;
>-}
>-
>-#define igt_wedge_on_timeout(W, DEV, TIMEOUT)				\
>-	for (__igt_init_wedge((W), (DEV), (TIMEOUT), __func__);		\
>-	     (W)->i915;							\
>-	     __igt_fini_wedge((W)))
>-
>-#endif /* IGT_WEDGE_ME_H */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/intel_guc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/intel_guc.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/intel_guc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/intel_guc.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,359 +0,0 @@
>-/*
>- * Copyright Â© 2017 Intel Corporation
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining a
>- * copy of this software and associated documentation files (the "Software"),
>- * to deal in the Software without restriction, including without limitation
>- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>- * and/or sell copies of the Software, and to permit persons to whom the
>- * Software is furnished to do so, subject to the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the next
>- * paragraph) shall be included in all copies or substantial portions of the
>- * Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>- * IN THE SOFTWARE.
>- *
>- */
>-
>-#include "i915_selftest.h"
>-#include "gem/i915_gem_pm.h"
>-
>-/* max doorbell number + negative test for each client type */
>-#define ATTEMPTS (GUC_NUM_DOORBELLS + GUC_CLIENT_PRIORITY_NUM)
>-
>-static struct intel_guc_client *clients[ATTEMPTS];
>-
>-static bool available_dbs(struct intel_guc *guc, u32 priority)
>-{
>-	unsigned long offset;
>-	unsigned long end;
>-	u16 id;
>-
>-	/* first half is used for normal priority, second half for high */
>-	offset = 0;
>-	end = GUC_NUM_DOORBELLS / 2;
>-	if (priority <= GUC_CLIENT_PRIORITY_HIGH) {
>-		offset = end;
>-		end += offset;
>-	}
>-
>-	id = find_next_zero_bit(guc->doorbell_bitmap, end, offset);
>-	if (id < end)
>-		return true;
>-
>-	return false;
>-}
>-
>-static int check_all_doorbells(struct intel_guc *guc)
>-{
>-	u16 db_id;
>-
>-	pr_info_once("Max number of doorbells: %d", GUC_NUM_DOORBELLS);
>-	for (db_id = 0; db_id < GUC_NUM_DOORBELLS; ++db_id) {
>-		if (!doorbell_ok(guc, db_id)) {
>-			pr_err("doorbell %d, not ok\n", db_id);
>-			return -EIO;
>-		}
>-	}
>-
>-	return 0;
>-}
>-
>-static int ring_doorbell_nop(struct intel_guc_client *client)
>-{
>-	struct guc_process_desc *desc = __get_process_desc(client);
>-	int err;
>-
>-	client->use_nop_wqi = true;
>-
>-	spin_lock_irq(&client->wq_lock);
>-
>-	guc_wq_item_append(client, 0, 0, 0, 0);
>-	guc_ring_doorbell(client);
>-
>-	spin_unlock_irq(&client->wq_lock);
>-
>-	client->use_nop_wqi = false;
>-
>-	/* if there are no issues GuC will update the WQ head and keep the
>-	 * WQ in active status
>-	 */
>-	err = wait_for(READ_ONCE(desc->head) == READ_ONCE(desc->tail), 10);
>-	if (err) {
>-		pr_err("doorbell %u ring failed!\n", client->doorbell_id);
>-		return -EIO;
>-	}
>-
>-	if (desc->wq_status != WQ_STATUS_ACTIVE) {
>-		pr_err("doorbell %u ring put WQ in bad state (%u)!\n",
>-		       client->doorbell_id, desc->wq_status);
>-		return -EIO;
>-	}
>-
>-	return 0;
>-}
>-
>-/*
>- * Basic client sanity check, handy to validate create_clients.
>- */
>-static int validate_client(struct intel_guc_client *client,
>-			   int client_priority,
>-			   bool is_preempt_client)
>-{
>-	struct drm_i915_private *dev_priv = guc_to_i915(client->guc);
>-	struct i915_gem_context *ctx_owner = is_preempt_client ?
>-			dev_priv->preempt_context : dev_priv->kernel_context;
>-
>-	if (client->owner != ctx_owner ||
>-	    client->engines != INTEL_INFO(dev_priv)->engine_mask ||
>-	    client->priority != client_priority ||
>-	    client->doorbell_id == GUC_DOORBELL_INVALID)
>-		return -EINVAL;
>-	else
>-		return 0;
>-}
>-
>-static bool client_doorbell_in_sync(struct intel_guc_client *client)
>-{
>-	return !client || doorbell_ok(client->guc, client->doorbell_id);
>-}
>-
>-/*
>- * Check that we're able to synchronize guc_clients with their doorbells
>- *
>- * We're creating clients and reserving doorbells once, at module load. During
>- * module lifetime, GuC, doorbell HW, and i915 state may go out of sync due to
>- * GuC being reset. In other words - GuC clients are still around, but the
>- * status of their doorbells may be incorrect. This is the reason behind
>- * validating that the doorbells status expected by the driver matches what the
>- * GuC/HW have.
>- */
>-static int igt_guc_clients(void *args)
>-{
>-	struct drm_i915_private *dev_priv = args;
>-	intel_wakeref_t wakeref;
>-	struct intel_guc *guc;
>-	int err = 0;
>-
>-	GEM_BUG_ON(!HAS_GUC(dev_priv));
>-	mutex_lock(&dev_priv->drm.struct_mutex);
>-	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>-
>-	guc = &dev_priv->guc;
>-	if (!guc) {
>-		pr_err("No guc object!\n");
>-		err = -EINVAL;
>-		goto unlock;
>-	}
>-
>-	err = check_all_doorbells(guc);
>-	if (err)
>-		goto unlock;
>-
>-	/*
>-	 * Get rid of clients created during driver load because the test will
>-	 * recreate them.
>-	 */
>-	guc_clients_disable(guc);
>-	guc_clients_destroy(guc);
>-	if (guc->execbuf_client || guc->preempt_client) {
>-		pr_err("guc_clients_destroy lied!\n");
>-		err = -EINVAL;
>-		goto unlock;
>-	}
>-
>-	err = guc_clients_create(guc);
>-	if (err) {
>-		pr_err("Failed to create clients\n");
>-		goto unlock;
>-	}
>-	GEM_BUG_ON(!guc->execbuf_client);
>-
>-	err = validate_client(guc->execbuf_client,
>-			      GUC_CLIENT_PRIORITY_KMD_NORMAL, false);
>-	if (err) {
>-		pr_err("execbug client validation failed\n");
>-		goto out;
>-	}
>-
>-	if (guc->preempt_client) {
>-		err = validate_client(guc->preempt_client,
>-				      GUC_CLIENT_PRIORITY_KMD_HIGH, true);
>-		if (err) {
>-			pr_err("preempt client validation failed\n");
>-			goto out;
>-		}
>-	}
>-
>-	/* each client should now have reserved a doorbell */
>-	if (!has_doorbell(guc->execbuf_client) ||
>-	    (guc->preempt_client && !has_doorbell(guc->preempt_client))) {
>-		pr_err("guc_clients_create didn't reserve doorbells\n");
>-		err = -EINVAL;
>-		goto out;
>-	}
>-
>-	/* Now enable the clients */
>-	guc_clients_enable(guc);
>-
>-	/* each client should now have received a doorbell */
>-	if (!client_doorbell_in_sync(guc->execbuf_client) ||
>-	    !client_doorbell_in_sync(guc->preempt_client)) {
>-		pr_err("failed to initialize the doorbells\n");
>-		err = -EINVAL;
>-		goto out;
>-	}
>-
>-	/*
>-	 * Basic test - an attempt to reallocate a valid doorbell to the
>-	 * client it is currently assigned should not cause a failure.
>-	 */
>-	err = create_doorbell(guc->execbuf_client);
>-
>-out:
>-	/*
>-	 * Leave clean state for other test, plus the driver always destroy the
>-	 * clients during unload.
>-	 */
>-	guc_clients_disable(guc);
>-	guc_clients_destroy(guc);
>-	guc_clients_create(guc);
>-	guc_clients_enable(guc);
>-unlock:
>-	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>-	mutex_unlock(&dev_priv->drm.struct_mutex);
>-	return err;
>-}
>-
>-/*
>- * Create as many clients as number of doorbells. Note that there's already
>- * client(s)/doorbell(s) created during driver load, but this test creates
>- * its own and do not interact with the existing ones.
>- */
>-static int igt_guc_doorbells(void *arg)
>-{
>-	struct drm_i915_private *dev_priv = arg;
>-	intel_wakeref_t wakeref;
>-	struct intel_guc *guc;
>-	int i, err = 0;
>-	u16 db_id;
>-
>-	GEM_BUG_ON(!HAS_GUC(dev_priv));
>-	mutex_lock(&dev_priv->drm.struct_mutex);
>-	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>-
>-	guc = &dev_priv->guc;
>-	if (!guc) {
>-		pr_err("No guc object!\n");
>-		err = -EINVAL;
>-		goto unlock;
>-	}
>-
>-	err = check_all_doorbells(guc);
>-	if (err)
>-		goto unlock;
>-
>-	for (i = 0; i < ATTEMPTS; i++) {
>-		clients[i] = guc_client_alloc(dev_priv,
>-					      INTEL_INFO(dev_priv)->engine_mask,
>-					      i % GUC_CLIENT_PRIORITY_NUM,
>-					      dev_priv->kernel_context);
>-
>-		if (!clients[i]) {
>-			pr_err("[%d] No guc client\n", i);
>-			err = -EINVAL;
>-			goto out;
>-		}
>-
>-		if (IS_ERR(clients[i])) {
>-			if (PTR_ERR(clients[i]) != -ENOSPC) {
>-				pr_err("[%d] unexpected error\n", i);
>-				err = PTR_ERR(clients[i]);
>-				goto out;
>-			}
>-
>-			if (available_dbs(guc, i % GUC_CLIENT_PRIORITY_NUM)) {
>-				pr_err("[%d] non-db related alloc fail\n", i);
>-				err = -EINVAL;
>-				goto out;
>-			}
>-
>-			/* expected, ran out of dbs for this client type */
>-			continue;
>-		}
>-
>-		/*
>-		 * The check below is only valid because we keep a doorbell
>-		 * assigned during the whole life of the client.
>-		 */
>-		if (clients[i]->stage_id >= GUC_NUM_DOORBELLS) {
>-			pr_err("[%d] more clients than doorbells (%d >= %d)\n",
>-			       i, clients[i]->stage_id, GUC_NUM_DOORBELLS);
>-			err = -EINVAL;
>-			goto out;
>-		}
>-
>-		err = validate_client(clients[i],
>-				      i % GUC_CLIENT_PRIORITY_NUM, false);
>-		if (err) {
>-			pr_err("[%d] client_alloc sanity check failed!\n", i);
>-			err = -EINVAL;
>-			goto out;
>-		}
>-
>-		db_id = clients[i]->doorbell_id;
>-
>-		err = __guc_client_enable(clients[i]);
>-		if (err) {
>-			pr_err("[%d] Failed to create a doorbell\n", i);
>-			goto out;
>-		}
>-
>-		/* doorbell id shouldn't change, we are holding the mutex */
>-		if (db_id != clients[i]->doorbell_id) {
>-			pr_err("[%d] doorbell id changed (%d != %d)\n",
>-			       i, db_id, clients[i]->doorbell_id);
>-			err = -EINVAL;
>-			goto out;
>-		}
>-
>-		err = check_all_doorbells(guc);
>-		if (err)
>-			goto out;
>-
>-		err = ring_doorbell_nop(clients[i]);
>-		if (err)
>-			goto out;
>-	}
>-
>-out:
>-	for (i = 0; i < ATTEMPTS; i++)
>-		if (!IS_ERR_OR_NULL(clients[i])) {
>-			__guc_client_disable(clients[i]);
>-			guc_client_free(clients[i]);
>-		}
>-unlock:
>-	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>-	mutex_unlock(&dev_priv->drm.struct_mutex);
>-	return err;
>-}
>-
>-int intel_guc_live_selftest(struct drm_i915_private *dev_priv)
>-{
>-	static const struct i915_subtest tests[] = {
>-		SUBTEST(igt_guc_clients),
>-		SUBTEST(igt_guc_doorbells),
>-	};
>-
>-	if (!USES_GUC_SUBMISSION(dev_priv))
>-		return 0;
>-
>-	return i915_subtests(tests, dev_priv);
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/mock_gem_device.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/mock_gem_device.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/mock_gem_device.c	2019-08-31 15:01:12.043736185 -0500
>@@ -25,6 +25,7 @@
> #include <linux/pm_domain.h>
> #include <linux/pm_runtime.h>
> 
>+#include "gt/intel_gt.h"
> #include "gt/mock_engine.h"
> 
> #include "mock_request.h"
>@@ -67,7 +68,7 @@
> 	i915_gem_contexts_fini(i915);
> 	mutex_unlock(&i915->drm.struct_mutex);
> 
>-	i915_timelines_fini(i915);
>+	intel_timelines_fini(i915);
> 
> 	drain_workqueue(i915->wq);
> 	i915_gem_drain_freed_objects(i915);
>@@ -179,14 +180,9 @@
> 
> 	mock_uncore_init(&i915->uncore);
> 	i915_gem_init__mm(i915);
>-	intel_gt_pm_init(i915);
>+	intel_gt_init_early(&i915->gt, i915);
> 	atomic_inc(&i915->gt.wakeref.count); /* disable; no hw support */
> 
>-	init_waitqueue_head(&i915->gpu_error.wait_queue);
>-	init_waitqueue_head(&i915->gpu_error.reset_queue);
>-	init_srcu_struct(&i915->gpu_error.reset_backoff_srcu);
>-	mutex_init(&i915->gpu_error.wedge_mutex);
>-
> 	i915->wq = alloc_ordered_workqueue("mock", 0);
> 	if (!i915->wq)
> 		goto err_drv;
>@@ -198,11 +194,7 @@
> 
> 	i915->gt.awake = true;
> 
>-	i915_timelines_init(i915);
>-
>-	INIT_LIST_HEAD(&i915->gt.active_rings);
>-	INIT_LIST_HEAD(&i915->gt.closed_vma);
>-	spin_lock_init(&i915->gt.closed_lock);
>+	intel_timelines_init(i915);
> 
> 	mutex_lock(&i915->drm.struct_mutex);
> 
>@@ -233,7 +225,7 @@
> 	mock_engine_free(i915->engine[RCS0]);
> err_unlock:
> 	mutex_unlock(&i915->drm.struct_mutex);
>-	i915_timelines_fini(i915);
>+	intel_timelines_fini(i915);
> 	destroy_workqueue(i915->wq);
> err_drv:
> 	drm_mode_config_cleanup(&i915->drm);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/mock_gtt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/mock_gtt.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/mock_gtt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/mock_gtt.c	2019-08-31 15:01:12.043736185 -0500
>@@ -98,6 +98,7 @@
> {
> 	memset(ggtt, 0, sizeof(*ggtt));
> 
>+	ggtt->vm.gt = &i915->gt;
> 	ggtt->vm.i915 = i915;
> 	ggtt->vm.is_ggtt = true;
> 
>@@ -116,6 +117,8 @@
> 	ggtt->vm.vma_ops.clear_pages = clear_pages;
> 
> 	i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
>+
>+	intel_gt_init_hw(i915);
> }
> 
> void mock_fini_ggtt(struct i915_ggtt *ggtt)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/mock_timeline.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/mock_timeline.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/mock_timeline.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/mock_timeline.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,29 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2017-2018 Intel Corporation
>- */
>-
>-#include "../i915_timeline.h"
>-
>-#include "mock_timeline.h"
>-
>-void mock_timeline_init(struct i915_timeline *timeline, u64 context)
>-{
>-	timeline->i915 = NULL;
>-	timeline->fence_context = context;
>-
>-	mutex_init(&timeline->mutex);
>-
>-	INIT_ACTIVE_REQUEST(&timeline->last_request);
>-	INIT_LIST_HEAD(&timeline->requests);
>-
>-	i915_syncmap_init(&timeline->sync);
>-
>-	INIT_LIST_HEAD(&timeline->link);
>-}
>-
>-void mock_timeline_fini(struct i915_timeline *timeline)
>-{
>-	i915_syncmap_free(&timeline->sync);
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/mock_timeline.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/mock_timeline.h
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/mock_timeline.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/mock_timeline.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,15 +0,0 @@
>-/*
>- * SPDX-License-Identifier: MIT
>- *
>- * Copyright Â© 2017-2018 Intel Corporation
>- */
>-
>-#ifndef __MOCK_TIMELINE__
>-#define __MOCK_TIMELINE__
>-
>-struct i915_timeline;
>-
>-void mock_timeline_init(struct i915_timeline *timeline, u64 context);
>-void mock_timeline_fini(struct i915_timeline *timeline);
>-
>-#endif /* !__MOCK_TIMELINE__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/i915/selftests/mock_uncore.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/mock_uncore.c
>--- linux-5.3-rc6/drivers/gpu/drm/i915/selftests/mock_uncore.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/i915/selftests/mock_uncore.c	2019-08-31 15:01:12.043736185 -0500
>@@ -41,6 +41,6 @@
> 
> void mock_uncore_init(struct intel_uncore *uncore)
> {
>-	ASSIGN_WRITE_MMIO_VFUNCS(uncore, nop);
>-	ASSIGN_READ_MMIO_VFUNCS(uncore, nop);
>+	ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, nop);
>+	ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, nop);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/imx/dw_hdmi-imx.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/dw_hdmi-imx.c
>--- linux-5.3-rc6/drivers/gpu/drm/imx/dw_hdmi-imx.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/dw_hdmi-imx.c	2019-08-31 15:01:12.043736185 -0500
>@@ -3,19 +3,21 @@
>  *
>  * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
>  */
>-#include <linux/module.h>
>-#include <linux/platform_device.h>
>+
> #include <linux/component.h>
> #include <linux/mfd/syscon.h>
> #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
>-#include <drm/bridge/dw_hdmi.h>
>-#include <video/imx-ipu-v3.h>
>+#include <linux/module.h>
>+#include <linux/platform_device.h>
> #include <linux/regmap.h>
>-#include <drm/drm_of.h>
>-#include <drm/drmP.h>
>+
>+#include <video/imx-ipu-v3.h>
>+
>+#include <drm/bridge/dw_hdmi.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_edid.h>
> #include <drm/drm_encoder_slave.h>
>+#include <drm/drm_of.h>
> 
> #include "imx-drm.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/imx/imx-drm-core.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/imx-drm-core.c
>--- linux-5.3-rc6/drivers/gpu/drm/imx/imx-drm-core.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/imx-drm-core.c	2019-08-31 15:01:12.043736185 -0500
>@@ -4,14 +4,18 @@
>  *
>  * Copyright (C) 2011 Sascha Hauer, Pengutronix
>  */
>+
> #include <linux/component.h>
> #include <linux/device.h>
> #include <linux/dma-buf.h>
> #include <linux/module.h>
> #include <linux/platform_device.h>
>-#include <drm/drmP.h>
>+
>+#include <video/imx-ipu-v3.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_fb_helper.h>
> #include <drm/drm_gem_cma_helper.h>
>@@ -19,7 +23,7 @@
> #include <drm/drm_of.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>-#include <video/imx-ipu-v3.h>
>+#include <drm/drm_vblank.h>
> 
> #include "imx-drm.h"
> #include "ipuv3-plane.h"
>@@ -147,16 +151,13 @@
> };
> 
> static struct drm_driver imx_drm_driver = {
>-	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
>-				  DRIVER_ATOMIC,
>+	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> 	.gem_free_object_unlocked = drm_gem_cma_free_object,
> 	.gem_vm_ops		= &drm_gem_cma_vm_ops,
> 	.dumb_create		= drm_gem_cma_dumb_create,
> 
> 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
>-	.gem_prime_import	= drm_gem_prime_import,
>-	.gem_prime_export	= drm_gem_prime_export,
> 	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/imx/imx-ldb.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/imx-ldb.c
>--- linux-5.3-rc6/drivers/gpu/drm/imx/imx-ldb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/imx-ldb.c	2019-08-31 15:01:12.043736185 -0500
>@@ -5,25 +5,27 @@
>  * Copyright (C) 2012 Sascha Hauer, Pengutronix
>  */
> 
>-#include <linux/module.h>
> #include <linux/clk.h>
> #include <linux/component.h>
>-#include <drm/drmP.h>
>-#include <drm/drm_atomic.h>
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_of.h>
>-#include <drm/drm_panel.h>
>-#include <drm/drm_probe_helper.h>
> #include <linux/mfd/syscon.h>
> #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
>+#include <linux/module.h>
> #include <linux/of_device.h>
> #include <linux/of_graph.h>
>-#include <video/of_display_timing.h>
>-#include <video/of_videomode.h>
> #include <linux/regmap.h>
> #include <linux/videodev2.h>
> 
>+#include <video/of_display_timing.h>
>+#include <video/of_videomode.h>
>+
>+#include <drm/drm_atomic.h>
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_fb_helper.h>
>+#include <drm/drm_of.h>
>+#include <drm/drm_panel.h>
>+#include <drm/drm_print.h>
>+#include <drm/drm_probe_helper.h>
>+
> #include "imx-drm.h"
> 
> #define DRIVER_NAME "imx-ldb"
>@@ -460,9 +462,10 @@
> 		 */
> 		drm_connector_helper_add(&imx_ldb_ch->connector,
> 				&imx_ldb_connector_helper_funcs);
>-		drm_connector_init(drm, &imx_ldb_ch->connector,
>-				&imx_ldb_connector_funcs,
>-				DRM_MODE_CONNECTOR_LVDS);
>+		drm_connector_init_with_ddc(drm, &imx_ldb_ch->connector,
>+					    &imx_ldb_connector_funcs,
>+					    DRM_MODE_CONNECTOR_LVDS,
>+					    imx_ldb_ch->ddc);
> 		drm_connector_attach_encoder(&imx_ldb_ch->connector, encoder);
> 	}
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/imx/imx-tve.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/imx-tve.c
>--- linux-5.3-rc6/drivers/gpu/drm/imx/imx-tve.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/imx-tve.c	2019-08-31 15:01:12.043736185 -0500
>@@ -5,20 +5,22 @@
>  * Copyright (C) 2013 Philipp Zabel, Pengutronix
>  */
> 
>-#include <linux/clk.h>
> #include <linux/clk-provider.h>
>+#include <linux/clk.h>
> #include <linux/component.h>
>-#include <linux/module.h>
> #include <linux/i2c.h>
>+#include <linux/module.h>
>+#include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/regulator/consumer.h>
> #include <linux/spinlock.h>
> #include <linux/videodev2.h>
>-#include <drm/drmP.h>
>+
>+#include <video/imx-ipu-v3.h>
>+
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_fb_helper.h>
> #include <drm/drm_probe_helper.h>
>-#include <video/imx-ipu-v3.h>
> 
> #include "imx-drm.h"
> 
>@@ -482,8 +484,10 @@
> 
> 	drm_connector_helper_add(&tve->connector,
> 			&imx_tve_connector_helper_funcs);
>-	drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
>-			   DRM_MODE_CONNECTOR_VGA);
>+	drm_connector_init_with_ddc(drm, &tve->connector,
>+				    &imx_tve_connector_funcs,
>+				    DRM_MODE_CONNECTOR_VGA,
>+				    tve->ddc);
> 
> 	drm_connector_attach_encoder(&tve->connector, &tve->encoder);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/imx/ipuv3-crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/ipuv3-crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/imx/ipuv3-crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/ipuv3-crtc.c	2019-08-31 15:01:12.043736185 -0500
>@@ -4,21 +4,25 @@
>  *
>  * Copyright (C) 2011 Sascha Hauer, Pengutronix
>  */
>+
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/device.h>
>+#include <linux/dma-mapping.h>
> #include <linux/errno.h>
> #include <linux/export.h>
> #include <linux/module.h>
> #include <linux/platform_device.h>
>-#include <drm/drmP.h>
>+
>+#include <video/imx-ipu-v3.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
>-#include <video/imx-ipu-v3.h>
> #include "imx-drm.h"
> #include "ipuv3-plane.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/imx/ipuv3-plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/ipuv3-plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/imx/ipuv3-plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/ipuv3-plane.c	2019-08-31 15:01:12.043736185 -0500
>@@ -5,15 +5,16 @@
>  * Copyright (C) 2013 Philipp Zabel, Pengutronix
>  */
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_plane_helper.h>
> 
>-#include "video/imx-ipu-v3.h"
>+#include <video/imx-ipu-v3.h>
>+
> #include "imx-drm.h"
> #include "ipuv3-plane.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/imx/parallel-display.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/parallel-display.c
>--- linux-5.3-rc6/drivers/gpu/drm/imx/parallel-display.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/imx/parallel-display.c	2019-08-31 15:01:12.043736185 -0500
>@@ -7,14 +7,16 @@
> 
> #include <linux/component.h>
> #include <linux/module.h>
>-#include <drm/drmP.h>
>+#include <linux/platform_device.h>
>+#include <linux/videodev2.h>
>+
>+#include <video/of_display_timing.h>
>+
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_fb_helper.h>
> #include <drm/drm_of.h>
> #include <drm/drm_panel.h>
> #include <drm/drm_probe_helper.h>
>-#include <linux/videodev2.h>
>-#include <video/of_display_timing.h>
> 
> #include "imx-drm.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ingenic/ingenic-drm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ingenic/ingenic-drm.c
>--- linux-5.3-rc6/drivers/gpu/drm/ingenic/ingenic-drm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ingenic/ingenic-drm.c	2019-08-31 15:01:12.043736185 -0500
>@@ -166,6 +166,8 @@
> 
> 	struct ingenic_dma_hwdesc *dma_hwdesc;
> 	dma_addr_t dma_hwdesc_phys;
>+
>+	bool panel_is_sharp;
> };
> 
> static const u32 ingenic_drm_primary_formats[] = {
>@@ -283,6 +285,13 @@
> 	regmap_write(priv->map, JZ_REG_LCD_DAV,
> 		     vds << JZ_LCD_DAV_VDS_OFFSET |
> 		     vde << JZ_LCD_DAV_VDE_OFFSET);
>+
>+	if (priv->panel_is_sharp) {
>+		regmap_write(priv->map, JZ_REG_LCD_PS, hde << 16 | (hde + 1));
>+		regmap_write(priv->map, JZ_REG_LCD_CLS, hde << 16 | (hde + 1));
>+		regmap_write(priv->map, JZ_REG_LCD_SPL, hpe << 16 | (hpe + 1));
>+		regmap_write(priv->map, JZ_REG_LCD_REV, mode->htotal << 16);
>+	}
> }
> 
> static void ingenic_drm_crtc_update_ctrl(struct ingenic_drm *priv,
>@@ -378,11 +387,18 @@
> {
> 	struct ingenic_drm *priv = drm_encoder_get_priv(encoder);
> 	struct drm_display_mode *mode = &crtc_state->adjusted_mode;
>-	struct drm_display_info *info = &conn_state->connector->display_info;
>-	unsigned int cfg = JZ_LCD_CFG_PS_DISABLE
>-			 | JZ_LCD_CFG_CLS_DISABLE
>-			 | JZ_LCD_CFG_SPL_DISABLE
>-			 | JZ_LCD_CFG_REV_DISABLE;
>+	struct drm_connector *conn = conn_state->connector;
>+	struct drm_display_info *info = &conn->display_info;
>+	unsigned int cfg;
>+
>+	priv->panel_is_sharp = info->bus_flags & DRM_BUS_FLAG_SHARP_SIGNALS;
>+
>+	if (priv->panel_is_sharp) {
>+		cfg = JZ_LCD_CFG_MODE_SPECIAL_TFT_1 | JZ_LCD_CFG_REV_POLARITY;
>+	} else {
>+		cfg = JZ_LCD_CFG_PS_DISABLE | JZ_LCD_CFG_CLS_DISABLE
>+		    | JZ_LCD_CFG_SPL_DISABLE | JZ_LCD_CFG_REV_DISABLE;
>+	}
> 
> 	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
> 		cfg |= JZ_LCD_CFG_HSYNC_ACTIVE_LOW;
>@@ -393,24 +409,29 @@
> 	if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
> 		cfg |= JZ_LCD_CFG_PCLK_FALLING_EDGE;
> 
>-	if (conn_state->connector->connector_type == DRM_MODE_CONNECTOR_TV) {
>-		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
>-			cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
>-		else
>-			cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
>-	} else {
>-		switch (*info->bus_formats) {
>-		case MEDIA_BUS_FMT_RGB565_1X16:
>-			cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
>-			break;
>-		case MEDIA_BUS_FMT_RGB666_1X18:
>-			cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
>-			break;
>-		case MEDIA_BUS_FMT_RGB888_1X24:
>-			cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
>-			break;
>-		default:
>-			break;
>+	if (!priv->panel_is_sharp) {
>+		if (conn->connector_type == DRM_MODE_CONNECTOR_TV) {
>+			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
>+				cfg |= JZ_LCD_CFG_MODE_TV_OUT_I;
>+			else
>+				cfg |= JZ_LCD_CFG_MODE_TV_OUT_P;
>+		} else {
>+			switch (*info->bus_formats) {
>+			case MEDIA_BUS_FMT_RGB565_1X16:
>+				cfg |= JZ_LCD_CFG_MODE_GENERIC_16BIT;
>+				break;
>+			case MEDIA_BUS_FMT_RGB666_1X18:
>+				cfg |= JZ_LCD_CFG_MODE_GENERIC_18BIT;
>+				break;
>+			case MEDIA_BUS_FMT_RGB888_1X24:
>+				cfg |= JZ_LCD_CFG_MODE_GENERIC_24BIT;
>+				break;
>+			case MEDIA_BUS_FMT_RGB888_3X8:
>+				cfg |= JZ_LCD_CFG_MODE_8BIT_SERIAL;
>+				break;
>+			default:
>+				break;
>+			}
> 		}
> 	}
> 
>@@ -433,6 +454,7 @@
> 	case MEDIA_BUS_FMT_RGB565_1X16:
> 	case MEDIA_BUS_FMT_RGB666_1X18:
> 	case MEDIA_BUS_FMT_RGB888_1X24:
>+	case MEDIA_BUS_FMT_RGB888_3X8:
> 		return 0;
> 	default:
> 		return -EINVAL;
>@@ -484,8 +506,7 @@
> DEFINE_DRM_GEM_CMA_FOPS(ingenic_drm_fops);
> 
> static struct drm_driver ingenic_drm_driver_data = {
>-	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME
>-				| DRIVER_ATOMIC,
>+	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> 	.name			= "ingenic-drm",
> 	.desc			= "DRM module for Ingenic SoCs",
> 	.date			= "20190422",
>@@ -581,7 +602,6 @@
> 	struct drm_bridge *bridge;
> 	struct drm_panel *panel;
> 	struct drm_device *drm;
>-	struct resource *mem;
> 	void __iomem *base;
> 	long parent_rate;
> 	int ret, irq;
>@@ -615,8 +635,7 @@
> 	drm->mode_config.max_height = 600;
> 	drm->mode_config.funcs = &ingenic_drm_mode_config_funcs;
> 
>-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>-	base = devm_ioremap_resource(dev, mem);
>+	base = devm_platform_ioremap_resource(pdev, 0);
> 	if (IS_ERR(base)) {
> 		dev_err(dev, "Failed to get memory resource");
> 		return PTR_ERR(base);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/Kconfig linux-5.3-rc6-agd5fed/drivers/gpu/drm/Kconfig
>--- linux-5.3-rc6/drivers/gpu/drm/Kconfig	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/Kconfig	2019-08-31 15:01:11.838736166 -0500
>@@ -24,6 +24,10 @@
> 	  details.  You should also select and configure AGP
> 	  (/dev/agpgart) support if it is available for your platform.
> 
>+config DRM_MIPI_DBI
>+	tristate
>+	depends on DRM
>+
> config DRM_MIPI_DSI
> 	bool
> 	depends on DRM
>@@ -336,7 +340,7 @@
> 
> source "drivers/gpu/drm/meson/Kconfig"
> 
>-source "drivers/gpu/drm/tinydrm/Kconfig"
>+source "drivers/gpu/drm/tiny/Kconfig"
> 
> source "drivers/gpu/drm/pl111/Kconfig"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/lima/lima_device.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_device.c
>--- linux-5.3-rc6/drivers/gpu/drm/lima/lima_device.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_device.c	2019-08-31 15:01:12.043736185 -0500
>@@ -80,26 +80,23 @@
> static int lima_clk_init(struct lima_device *dev)
> {
> 	int err;
>-	unsigned long bus_rate, gpu_rate;
> 
> 	dev->clk_bus = devm_clk_get(dev->dev, "bus");
> 	if (IS_ERR(dev->clk_bus)) {
>-		dev_err(dev->dev, "get bus clk failed %ld\n", PTR_ERR(dev->clk_bus));
>-		return PTR_ERR(dev->clk_bus);
>+		err = PTR_ERR(dev->clk_bus);
>+		if (err != -EPROBE_DEFER)
>+			dev_err(dev->dev, "get bus clk failed %d\n", err);
>+		return err;
> 	}
> 
> 	dev->clk_gpu = devm_clk_get(dev->dev, "core");
> 	if (IS_ERR(dev->clk_gpu)) {
>-		dev_err(dev->dev, "get core clk failed %ld\n", PTR_ERR(dev->clk_gpu));
>-		return PTR_ERR(dev->clk_gpu);
>+		err = PTR_ERR(dev->clk_gpu);
>+		if (err != -EPROBE_DEFER)
>+			dev_err(dev->dev, "get core clk failed %d\n", err);
>+		return err;
> 	}
> 
>-	bus_rate = clk_get_rate(dev->clk_bus);
>-	dev_info(dev->dev, "bus rate = %lu\n", bus_rate);
>-
>-	gpu_rate = clk_get_rate(dev->clk_gpu);
>-	dev_info(dev->dev, "mod rate = %lu", gpu_rate);
>-
> 	err = clk_prepare_enable(dev->clk_bus);
> 	if (err)
> 		return err;
>@@ -111,11 +108,17 @@
> 	dev->reset = devm_reset_control_get_optional(dev->dev, NULL);
> 	if (IS_ERR(dev->reset)) {
> 		err = PTR_ERR(dev->reset);
>+		if (err != -EPROBE_DEFER)
>+			dev_err(dev->dev, "get reset controller failed %d\n",
>+				err);
> 		goto error_out1;
> 	} else if (dev->reset != NULL) {
> 		err = reset_control_deassert(dev->reset);
>-		if (err)
>+		if (err) {
>+			dev_err(dev->dev,
>+				"reset controller deassert failed %d\n", err);
> 			goto error_out1;
>+		}
> 	}
> 
> 	return 0;
>@@ -145,7 +148,8 @@
> 		dev->regulator = NULL;
> 		if (ret == -ENODEV)
> 			return 0;
>-		dev_err(dev->dev, "failed to get regulator: %d\n", ret);
>+		if (ret != -EPROBE_DEFER)
>+			dev_err(dev->dev, "failed to get regulator: %d\n", ret);
> 		return ret;
> 	}
> 
>@@ -291,16 +295,12 @@
> 	dma_set_coherent_mask(ldev->dev, DMA_BIT_MASK(32));
> 
> 	err = lima_clk_init(ldev);
>-	if (err) {
>-		dev_err(ldev->dev, "clk init fail %d\n", err);
>+	if (err)
> 		return err;
>-	}
> 
> 	err = lima_regulator_init(ldev);
>-	if (err) {
>-		dev_err(ldev->dev, "regulator init fail %d\n", err);
>+	if (err)
> 		goto err_out0;
>-	}
> 
> 	ldev->empty_vm = lima_vm_create(ldev);
> 	if (!ldev->empty_vm) {
>@@ -343,6 +343,9 @@
> 	if (err)
> 		goto err_out5;
> 
>+	dev_info(ldev->dev, "bus rate = %lu\n", clk_get_rate(ldev->clk_bus));
>+	dev_info(ldev->dev, "mod rate = %lu", clk_get_rate(ldev->clk_gpu));
>+
> 	return 0;
> 
> err_out5:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/lima/lima_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/lima/lima_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_drv.c	2019-08-31 15:01:12.044736185 -0500
>@@ -231,13 +231,13 @@
> }
> 
> static const struct drm_ioctl_desc lima_drm_driver_ioctls[] = {
>-	DRM_IOCTL_DEF_DRV(LIMA_GET_PARAM, lima_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(LIMA_GEM_CREATE, lima_ioctl_gem_create, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(LIMA_GEM_INFO, lima_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(LIMA_GEM_SUBMIT, lima_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(LIMA_GEM_WAIT, lima_ioctl_gem_wait, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(LIMA_CTX_CREATE, lima_ioctl_ctx_create, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(LIMA_CTX_FREE, lima_ioctl_ctx_free, DRM_AUTH|DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(LIMA_GET_PARAM, lima_ioctl_get_param, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(LIMA_GEM_CREATE, lima_ioctl_gem_create, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(LIMA_GEM_INFO, lima_ioctl_gem_info, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(LIMA_GEM_SUBMIT, lima_ioctl_gem_submit, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(LIMA_GEM_WAIT, lima_ioctl_gem_wait, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(LIMA_CTX_CREATE, lima_ioctl_ctx_create, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(LIMA_CTX_FREE, lima_ioctl_ctx_free, DRM_RENDER_ALLOW),
> };
> 
> static const struct file_operations lima_drm_driver_fops = {
>@@ -252,7 +252,7 @@
> };
> 
> static struct drm_driver lima_drm_driver = {
>-	.driver_features    = DRIVER_RENDER | DRIVER_GEM | DRIVER_PRIME | DRIVER_SYNCOBJ,
>+	.driver_features    = DRIVER_RENDER | DRIVER_GEM | DRIVER_SYNCOBJ,
> 	.open               = lima_drm_driver_open,
> 	.postclose          = lima_drm_driver_postclose,
> 	.ioctls             = lima_drm_driver_ioctls,
>@@ -307,10 +307,8 @@
> 	ldev->ddev = ddev;
> 
> 	err = lima_device_init(ldev);
>-	if (err) {
>-		dev_err(&pdev->dev, "Fatal error during GPU init\n");
>+	if (err)
> 		goto err_out1;
>-	}
> 
> 	/*
> 	 * Register the DRM device with the core and the connectors with
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/lima/lima_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/lima/lima_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_gem.c	2019-08-31 15:01:12.044736185 -0500
>@@ -24,7 +24,7 @@
> 	struct lima_bo *bo;
> 	struct lima_device *ldev = to_lima_dev(dev);
> 
>-	bo = lima_bo_create(ldev, size, flags, NULL, NULL);
>+	bo = lima_bo_create(ldev, size, flags, NULL);
> 	if (IS_ERR(bo))
> 		return PTR_ERR(bo);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/lima/lima_gem_prime.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_gem_prime.c
>--- linux-5.3-rc6/drivers/gpu/drm/lima/lima_gem_prime.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_gem_prime.c	2019-08-31 15:01:12.044736185 -0500
>@@ -18,8 +18,7 @@
> 	struct lima_device *ldev = to_lima_dev(dev);
> 	struct lima_bo *bo;
> 
>-	bo = lima_bo_create(ldev, attach->dmabuf->size, 0, sgt,
>-			    attach->dmabuf->resv);
>+	bo = lima_bo_create(ldev, attach->dmabuf->size, 0, sgt);
> 	if (IS_ERR(bo))
> 		return ERR_CAST(bo);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/lima/lima_object.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_object.c
>--- linux-5.3-rc6/drivers/gpu/drm/lima/lima_object.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_object.c	2019-08-31 15:01:12.044736185 -0500
>@@ -33,8 +33,7 @@
> 	kfree(bo);
> }
> 
>-static struct lima_bo *lima_bo_create_struct(struct lima_device *dev, u32 size, u32 flags,
>-					     struct reservation_object *resv)
>+static struct lima_bo *lima_bo_create_struct(struct lima_device *dev, u32 size, u32 flags)
> {
> 	struct lima_bo *bo;
> 	int err;
>@@ -47,7 +46,6 @@
> 
> 	mutex_init(&bo->lock);
> 	INIT_LIST_HEAD(&bo->va);
>-	bo->gem.resv = resv;
> 
> 	err = drm_gem_object_init(dev->ddev, &bo->gem, size);
> 	if (err) {
>@@ -59,14 +57,13 @@
> }
> 
> struct lima_bo *lima_bo_create(struct lima_device *dev, u32 size,
>-			       u32 flags, struct sg_table *sgt,
>-			       struct reservation_object *resv)
>+			       u32 flags, struct sg_table *sgt)
> {
> 	int i, err;
> 	size_t npages;
> 	struct lima_bo *bo, *ret;
> 
>-	bo = lima_bo_create_struct(dev, size, flags, resv);
>+	bo = lima_bo_create_struct(dev, size, flags);
> 	if (IS_ERR(bo))
> 		return bo;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/lima/lima_object.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_object.h
>--- linux-5.3-rc6/drivers/gpu/drm/lima/lima_object.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_object.h	2019-08-31 15:01:12.044736185 -0500
>@@ -27,8 +27,7 @@
> }
> 
> struct lima_bo *lima_bo_create(struct lima_device *dev, u32 size,
>-			       u32 flags, struct sg_table *sgt,
>-			       struct reservation_object *resv);
>+			       u32 flags, struct sg_table *sgt);
> void lima_bo_destroy(struct lima_bo *bo);
> void *lima_bo_vmap(struct lima_bo *bo);
> void lima_bo_vunmap(struct lima_bo *bo);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/lima/lima_vm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_vm.h
>--- linux-5.3-rc6/drivers/gpu/drm/lima/lima_vm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/lima/lima_vm.h	2019-08-31 15:01:12.044736185 -0500
>@@ -15,9 +15,9 @@
> #define LIMA_VM_NUM_PT_PER_BT (1 << LIMA_VM_NUM_PT_PER_BT_SHIFT)
> #define LIMA_VM_NUM_BT (LIMA_PAGE_ENT_NUM >> LIMA_VM_NUM_PT_PER_BT_SHIFT)
> 
>-#define LIMA_VA_RESERVE_START  0xFFF00000
>+#define LIMA_VA_RESERVE_START  0x0FFF00000ULL
> #define LIMA_VA_RESERVE_DLBU   LIMA_VA_RESERVE_START
>-#define LIMA_VA_RESERVE_END    0x100000000
>+#define LIMA_VA_RESERVE_END    0x100000000ULL
> 
> struct lima_device;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/Makefile	2019-08-31 15:01:11.838736166 -0500
>@@ -55,6 +55,7 @@
> obj-$(CONFIG_DRM_DEBUG_SELFTEST) += selftests/
> 
> obj-$(CONFIG_DRM)	+= drm.o
>+obj-$(CONFIG_DRM_MIPI_DBI) += drm_mipi_dbi.o
> obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o
> obj-$(CONFIG_DRM_PANEL_ORIENTATION_QUIRKS) += drm_panel_orientation_quirks.o
> obj-y			+= arm/
>@@ -62,7 +63,6 @@
> obj-$(CONFIG_DRM_SCHED)	+= scheduler/
> obj-$(CONFIG_DRM_TDFX)	+= tdfx/
> obj-$(CONFIG_DRM_R128)	+= r128/
>-obj-$(CONFIG_HSA_AMD) += amd/amdkfd/
> obj-$(CONFIG_DRM_RADEON)+= radeon/
> obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
> obj-$(CONFIG_DRM_MGA)	+= mga/
>@@ -111,7 +111,7 @@
> obj-y			+= hisilicon/
> obj-$(CONFIG_DRM_ZTE)	+= zte/
> obj-$(CONFIG_DRM_MXSFB)	+= mxsfb/
>-obj-$(CONFIG_DRM_TINYDRM) += tinydrm/
>+obj-y			+= tiny/
> obj-$(CONFIG_DRM_PL111) += pl111/
> obj-$(CONFIG_DRM_TVE200) += tve200/
> obj-$(CONFIG_DRM_XEN) += xen/
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mcde/mcde_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mcde/mcde_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/mcde/mcde_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mcde/mcde_drv.c	2019-08-31 15:01:12.044736185 -0500
>@@ -237,7 +237,7 @@
> 
> static struct drm_driver mcde_drm_driver = {
> 	.driver_features =
>-		DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | DRIVER_ATOMIC,
>+		DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> 	.release = mcde_release,
> 	.lastclose = drm_fb_helper_lastclose,
> 	.ioctls = NULL,
>@@ -254,8 +254,6 @@
> 
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_import = drm_gem_prime_import,
>-	.gem_prime_export = drm_gem_prime_export,
> 	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap = drm_gem_cma_prime_vmap,
>@@ -319,7 +317,7 @@
> 	struct device *dev = &pdev->dev;
> 	struct drm_device *drm;
> 	struct mcde *mcde;
>-	struct component_match *match;
>+	struct component_match *match = NULL;
> 	struct resource *res;
> 	u32 pid;
> 	u32 val;
>@@ -485,6 +483,10 @@
> 		}
> 		put_device(p);
> 	}
>+	if (!match) {
>+		dev_err(dev, "no matching components\n");
>+		return -ENODEV;
>+	}
> 	if (IS_ERR(match)) {
> 		dev_err(dev, "could not create component match\n");
> 		ret = PTR_ERR(match);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_disp_color.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_disp_color.c
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_disp_color.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_disp_color.c	2019-08-31 15:01:12.044736185 -0500
>@@ -3,9 +3,9 @@
>  * Copyright (c) 2017 MediaTek Inc.
>  */
> 
>-#include <drm/drmP.h>
> #include <linux/clk.h>
> #include <linux/component.h>
>+#include <linux/module.h>
> #include <linux/of_device.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_disp_ovl.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_disp_ovl.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_disp_ovl.c	2019-08-31 15:01:12.044736185 -0500
>@@ -3,9 +3,9 @@
>  * Copyright (c) 2015 MediaTek Inc.
>  */
> 
>-#include <drm/drmP.h>
> #include <linux/clk.h>
> #include <linux/component.h>
>+#include <linux/module.h>
> #include <linux/of_device.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_disp_rdma.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_disp_rdma.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_disp_rdma.c	2019-08-31 15:01:12.044736185 -0500
>@@ -3,9 +3,9 @@
>  * Copyright (c) 2015 MediaTek Inc.
>  */
> 
>-#include <drm/drmP.h>
> #include <linux/clk.h>
> #include <linux/component.h>
>+#include <linux/module.h>
> #include <linux/of_device.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_dpi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_dpi.c
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_dpi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_dpi.c	2019-08-31 15:01:12.044736185 -0500
>@@ -3,21 +3,23 @@
>  * Copyright (c) 2014 MediaTek Inc.
>  * Author: Jie Qiu <jie.qiu@mediatek.com>
>  */
>-#include <drm/drmP.h>
>-#include <drm/drm_crtc.h>
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_of.h>
>-#include <linux/kernel.h>
>+
>+#include <linux/clk.h>
> #include <linux/component.h>
>-#include <linux/platform_device.h>
>+#include <linux/interrupt.h>
>+#include <linux/kernel.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> #include <linux/of_graph.h>
>-#include <linux/interrupt.h>
>+#include <linux/platform_device.h>
> #include <linux/types.h>
>-#include <linux/clk.h>
>+
> #include <video/videomode.h>
> 
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_crtc.h>
>+#include <drm/drm_of.h>
>+
> #include "mtk_dpi_regs.h"
> #include "mtk_drm_ddp_comp.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_crtc.c	2019-08-31 15:01:12.044736185 -0500
>@@ -3,14 +3,16 @@
>  * Copyright (c) 2015 MediaTek Inc.
>  */
> 
>+#include <linux/clk.h>
>+#include <linux/pm_runtime.h>
>+
> #include <asm/barrier.h>
>-#include <drm/drmP.h>
>+#include <soc/mediatek/smi.h>
>+
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>-#include <linux/clk.h>
>-#include <linux/pm_runtime.h>
>-#include <soc/mediatek/smi.h>
>+#include <drm/drm_vblank.h>
> 
> #include "mtk_drm_drv.h"
> #include "mtk_drm_crtc.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c	2019-08-31 15:01:12.044736185 -0500
>@@ -12,7 +12,7 @@
> #include <linux/of_irq.h>
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
>-#include <drm/drmP.h>
>+
> #include "mtk_drm_drv.h"
> #include "mtk_drm_plane.h"
> #include "mtk_drm_ddp_comp.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_drv.c	2019-08-31 15:03:58.538750895 -0500
>@@ -4,23 +4,27 @@
>  * Author: YT SHEN <yt.shen@mediatek.com>
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/component.h>
>+#include <linux/iommu.h>
>+#include <linux/module.h>
>+#include <linux/of_address.h>
>+#include <linux/of_platform.h>
>+#include <linux/pm_runtime.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_helper.h>
> #include <drm/drm_gem.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_of.h>
> #include <drm/drm_probe_helper.h>
>-#include <linux/component.h>
>-#include <linux/iommu.h>
>-#include <linux/of_address.h>
>-#include <linux/of_platform.h>
>-#include <linux/pm_runtime.h>
> #include <linux/dma-mapping.h>
>+#include <drm/drm_vblank.h>
> 
> #include "mtk_drm_crtc.h"
> #include "mtk_drm_ddp.h"
>+#include "mtk_drm_ddp.h"
> #include "mtk_drm_ddp_comp.h"
> #include "mtk_drm_drv.h"
> #include "mtk_drm_fb.h"
>@@ -39,22 +43,12 @@
> 	schedule_work(&private->commit.work);
> }
> 
>-static void mtk_atomic_wait_for_fences(struct drm_atomic_state *state)
>-{
>-	struct drm_plane *plane;
>-	struct drm_plane_state *new_plane_state;
>-	int i;
>-
>-	for_each_new_plane_in_state(state, plane, new_plane_state, i)
>-		mtk_fb_wait(new_plane_state->fb);
>-}
>-
> static void mtk_atomic_complete(struct mtk_drm_private *private,
> 				struct drm_atomic_state *state)
> {
> 	struct drm_device *drm = private->drm;
> 
>-	mtk_atomic_wait_for_fences(state);
>+	drm_atomic_helper_wait_for_fences(drm, state, false);
> 
> 	/*
> 	 * Mediatek drm supports runtime PM, so plane registers cannot be
>@@ -365,8 +359,7 @@
> }
> 
> static struct drm_driver mtk_drm_driver = {
>-	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
>-			   DRIVER_ATOMIC,
>+	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> 
> 	.gem_free_object_unlocked = mtk_drm_gem_free_object,
> 	.gem_vm_ops = &drm_gem_cma_vm_ops,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_fb.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_fb.c
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_fb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_fb.c	2019-08-31 15:01:12.044736185 -0500
>@@ -3,13 +3,14 @@
>  * Copyright (c) 2015 MediaTek Inc.
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/dma-buf.h>
>+#include <linux/reservation.h>
>+
> #include <drm/drm_modeset_helper.h>
> #include <drm/drm_fb_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem.h>
> #include <drm/drm_gem_framebuffer_helper.h>
>-#include <linux/dma-buf.h>
>-#include <linux/reservation.h>
> 
> #include "mtk_drm_drv.h"
> #include "mtk_drm_fb.h"
>@@ -49,34 +50,6 @@
> 	return fb;
> }
> 
>-/*
>- * Wait for any exclusive fence in fb's gem object's reservation object.
>- *
>- * Returns -ERESTARTSYS if interrupted, else 0.
>- */
>-int mtk_fb_wait(struct drm_framebuffer *fb)
>-{
>-	struct drm_gem_object *gem;
>-	struct reservation_object *resv;
>-	long ret;
>-
>-	if (!fb)
>-		return 0;
>-
>-	gem = fb->obj[0];
>-	if (!gem || !gem->dma_buf || !gem->dma_buf->resv)
>-		return 0;
>-
>-	resv = gem->dma_buf->resv;
>-	ret = reservation_object_wait_timeout_rcu(resv, false, true,
>-						  MAX_SCHEDULE_TIMEOUT);
>-	/* MAX_SCHEDULE_TIMEOUT on success, -ERESTARTSYS if interrupted */
>-	if (WARN_ON(ret < 0))
>-		return ret;
>-
>-	return 0;
>-}
>-
> struct drm_framebuffer *mtk_drm_mode_fb_create(struct drm_device *dev,
> 					       struct drm_file *file,
> 					       const struct drm_mode_fb_cmd2 *cmd)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_fb.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_fb.h
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_fb.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_fb.h	2019-08-31 15:01:12.044736185 -0500
>@@ -6,7 +6,6 @@
> #ifndef MTK_DRM_FB_H
> #define MTK_DRM_FB_H
> 
>-int mtk_fb_wait(struct drm_framebuffer *fb);
> struct drm_framebuffer *mtk_drm_mode_fb_create(struct drm_device *dev,
> 					       struct drm_file *file,
> 					       const struct drm_mode_fb_cmd2 *cmd);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_gem.c	2019-08-31 15:01:12.044736185 -0500
>@@ -3,10 +3,13 @@
>  * Copyright (c) 2015 MediaTek Inc.
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_gem.h>
> #include <linux/dma-buf.h>
> 
>+#include <drm/drm.h>
>+#include <drm/drm_device.h>
>+#include <drm/drm_gem.h>
>+#include <drm/drm_prime.h>
>+
> #include "mtk_drm_drv.h"
> #include "mtk_drm_gem.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_drm_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_drm_plane.c	2019-08-31 15:01:12.045736185 -0500
>@@ -4,10 +4,11 @@
>  * Author: CK Hu <ck.hu@mediatek.com>
>  */
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_plane_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
> 
> #include "mtk_drm_crtc.h"
> #include "mtk_drm_ddp_comp.h"
>@@ -146,6 +147,7 @@
> }
> 
> static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = {
>+	.prepare_fb = drm_gem_fb_prepare_fb,
> 	.atomic_check = mtk_plane_atomic_check,
> 	.atomic_update = mtk_plane_atomic_update,
> 	.atomic_disable = mtk_plane_atomic_disable,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_dsi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_dsi.c
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_dsi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_dsi.c	2019-08-31 15:01:12.045736185 -0500
>@@ -3,12 +3,6 @@
>  * Copyright (c) 2015 MediaTek Inc.
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_mipi_dsi.h>
>-#include <drm/drm_panel.h>
>-#include <drm/drm_of.h>
>-#include <drm/drm_probe_helper.h>
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/iopoll.h>
>@@ -17,9 +11,17 @@
> #include <linux/of_platform.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
>+
> #include <video/mipi_display.h>
> #include <video/videomode.h>
> 
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_mipi_dsi.h>
>+#include <drm/drm_of.h>
>+#include <drm/drm_panel.h>
>+#include <drm/drm_print.h>
>+#include <drm/drm_probe_helper.h>
>+
> #include "mtk_drm_ddp_comp.h"
> 
> #define DSI_START		0x00
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_hdmi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_hdmi.c
>--- linux-5.3-rc6/drivers/gpu/drm/mediatek/mtk_hdmi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mediatek/mtk_hdmi.c	2019-08-31 15:01:12.045736185 -0500
>@@ -3,11 +3,7 @@
>  * Copyright (c) 2014 MediaTek Inc.
>  * Author: Jie Qiu <jie.qiu@mediatek.com>
>  */
>-#include <drm/drmP.h>
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_crtc.h>
>-#include <drm/drm_probe_helper.h>
>-#include <drm/drm_edid.h>
>+
> #include <linux/arm-smccc.h>
> #include <linux/clk.h>
> #include <linux/delay.h>
>@@ -23,7 +19,15 @@
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
>+
> #include <sound/hdmi-codec.h>
>+
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_crtc.h>
>+#include <drm/drm_edid.h>
>+#include <drm/drm_print.h>
>+#include <drm/drm_probe_helper.h>
>+
> #include "mtk_cec.h"
> #include "mtk_hdmi.h"
> #include "mtk_hdmi_regs.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_crtc.c	2019-08-31 15:01:12.045736185 -0500
>@@ -9,23 +9,21 @@
>  *     Jasper St. Pierre <jstpierre@mecheye.net>
>  */
> 
>-#include <linux/kernel.h>
>-#include <linux/module.h>
>-#include <linux/mutex.h>
>-#include <linux/platform_device.h>
> #include <linux/bitfield.h>
>-#include <drm/drmP.h>
>-#include <drm/drm_atomic.h>
>+#include <linux/soc/amlogic/meson-canvas.h>
>+
> #include <drm/drm_atomic_helper.h>
>-#include <drm/drm_flip_work.h>
>+#include <drm/drm_device.h>
>+#include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "meson_crtc.h"
> #include "meson_plane.h"
>+#include "meson_registers.h"
> #include "meson_venc.h"
>-#include "meson_vpp.h"
> #include "meson_viu.h"
>-#include "meson_registers.h"
>+#include "meson_vpp.h"
> 
> #define MESON_G12A_VIU_OFFSET	0x5ec0
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_drv.c	2019-08-31 15:01:12.045736185 -0500
>@@ -8,35 +8,30 @@
>  *     Jasper St. Pierre <jstpierre@mecheye.net>
>  */
> 
>-#include <linux/kernel.h>
>-#include <linux/module.h>
>-#include <linux/mutex.h>
>-#include <linux/platform_device.h>
> #include <linux/component.h>
>+#include <linux/module.h>
> #include <linux/of_graph.h>
>+#include <linux/platform_device.h>
>+#include <linux/soc/amlogic/meson-canvas.h>
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>-#include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_helper.h>
>-#include <drm/drm_flip_work.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_plane_helper.h>
>+#include <drm/drm_irq.h>
>+#include <drm/drm_modeset_helper_vtables.h>
> #include <drm/drm_probe_helper.h>
>-#include <drm/drm_rect.h>
>+#include <drm/drm_vblank.h>
> 
>+#include "meson_crtc.h"
> #include "meson_drv.h"
>-#include "meson_plane.h"
> #include "meson_overlay.h"
>-#include "meson_crtc.h"
>+#include "meson_plane.h"
>+#include "meson_registers.h"
> #include "meson_venc_cvbs.h"
>-
>-#include "meson_vpp.h"
> #include "meson_viu.h"
>-#include "meson_venc.h"
>-#include "meson_registers.h"
>+#include "meson_vpp.h"
> 
> #define DRIVER_NAME "meson"
> #define DRIVER_DESC "Amlogic Meson DRM driver"
>@@ -93,9 +88,7 @@
> DEFINE_DRM_GEM_CMA_FOPS(fops);
> 
> static struct drm_driver meson_driver = {
>-	.driver_features	= DRIVER_GEM |
>-				  DRIVER_MODESET | DRIVER_PRIME |
>-				  DRIVER_ATOMIC,
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 
> 	/* IRQ */
> 	.irq_handler		= meson_irq,
>@@ -103,8 +96,6 @@
> 	/* PRIME Ops */
> 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
>-	.gem_prime_import	= drm_gem_prime_import,
>-	.gem_prime_export	= drm_gem_prime_export,
> 	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_drv.h	2019-08-31 15:01:12.045736185 -0500
>@@ -7,11 +7,14 @@
> #ifndef __MESON_DRV_H
> #define __MESON_DRV_H
> 
>-#include <linux/platform_device.h>
>-#include <linux/regmap.h>
>+#include <linux/device.h>
> #include <linux/of.h>
>-#include <linux/soc/amlogic/meson-canvas.h>
>-#include <drm/drmP.h>
>+#include <linux/regmap.h>
>+
>+struct drm_crtc;
>+struct drm_device;
>+struct drm_plane;
>+struct meson_drm;
> 
> struct meson_drm {
> 	struct device *dev;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_dw_hdmi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_dw_hdmi.c
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_dw_hdmi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_dw_hdmi.c	2019-08-31 15:01:12.045736185 -0500
>@@ -5,29 +5,30 @@
>  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
>  */
> 
>+#include <linux/clk.h>
>+#include <linux/component.h>
> #include <linux/kernel.h>
> #include <linux/module.h>
>-#include <linux/component.h>
> #include <linux/of_device.h>
> #include <linux/of_graph.h>
>-#include <linux/reset.h>
>-#include <linux/clk.h>
> #include <linux/regulator/consumer.h>
>+#include <linux/reset.h>
> 
>-#include <drm/drmP.h>
>+#include <drm/bridge/dw_hdmi.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_device.h>
> #include <drm/drm_edid.h>
> #include <drm/drm_probe_helper.h>
>-#include <drm/bridge/dw_hdmi.h>
>+#include <drm/drm_print.h>
> 
>-#include <uapi/linux/media-bus-format.h>
>-#include <uapi/linux/videodev2.h>
>+#include <linux/media-bus-format.h>
>+#include <linux/videodev2.h>
> 
> #include "meson_drv.h"
>-#include "meson_venc.h"
>-#include "meson_vclk.h"
> #include "meson_dw_hdmi.h"
> #include "meson_registers.h"
>+#include "meson_vclk.h"
>+#include "meson_venc.h"
> 
> #define DRIVER_NAME "meson-dw-hdmi"
> #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_overlay.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_overlay.c
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_overlay.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_overlay.c	2019-08-31 15:01:12.045736185 -0500
>@@ -5,24 +5,21 @@
>  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
>  */
> 
>-#include <linux/kernel.h>
>-#include <linux/module.h>
>-#include <linux/mutex.h>
> #include <linux/bitfield.h>
>-#include <linux/platform_device.h>
>-#include <drm/drmP.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_device.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_rect.h>
> 
> #include "meson_overlay.h"
>-#include "meson_vpp.h"
>-#include "meson_viu.h"
> #include "meson_registers.h"
>+#include "meson_viu.h"
>+#include "meson_vpp.h"
> 
> /* VD1_IF0_GEN_REG */
> #define VD_URGENT_CHROMA		BIT(28)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_plane.c	2019-08-31 15:01:12.045736185 -0500
>@@ -9,24 +9,20 @@
>  *     Jasper St. Pierre <jstpierre@mecheye.net>
>  */
> 
>-#include <linux/kernel.h>
>-#include <linux/module.h>
>-#include <linux/mutex.h>
> #include <linux/bitfield.h>
>-#include <linux/platform_device.h>
>-#include <drm/drmP.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>-#include <drm/drm_plane_helper.h>
>-#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_device.h>
> #include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_rect.h>
>+#include <drm/drm_plane_helper.h>
> 
> #include "meson_plane.h"
>-#include "meson_vpp.h"
>-#include "meson_viu.h"
> #include "meson_registers.h"
>+#include "meson_viu.h"
> 
> /* OSD_SCI_WH_M1 */
> #define SCI_WH_M1_W(w)			FIELD_PREP(GENMASK(28, 16), w)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_registers.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_registers.h
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_registers.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_registers.h	2019-08-31 15:01:12.046736185 -0500
>@@ -6,6 +6,8 @@
> #ifndef __MESON_REGISTERS_H
> #define __MESON_REGISTERS_H
> 
>+#include <linux/io.h>
>+
> /* Shift all registers by 2 */
> #define _REG(reg)	((reg) << 2)
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_vclk.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_vclk.c
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_vclk.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_vclk.c	2019-08-31 15:01:12.046736185 -0500
>@@ -5,9 +5,10 @@
>  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
>  */
> 
>-#include <linux/kernel.h>
>-#include <linux/module.h>
>-#include <drm/drmP.h>
>+#include <linux/export.h>
>+
>+#include <drm/drm_print.h>
>+
> #include "meson_drv.h"
> #include "meson_vclk.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_vclk.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_vclk.h
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_vclk.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_vclk.h	2019-08-31 15:01:12.046736185 -0500
>@@ -9,6 +9,10 @@
> #ifndef __MESON_VCLK_H
> #define __MESON_VCLK_H
> 
>+#include <drm/drm_modes.h>
>+
>+struct meson_drm;
>+
> enum {
> 	MESON_VCLK_TARGET_CVBS = 0,
> 	MESON_VCLK_TARGET_HDMI = 1,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_venc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_venc.c
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_venc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_venc.c	2019-08-31 15:01:12.046736185 -0500
>@@ -5,14 +5,14 @@
>  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
>  */
> 
>-#include <linux/kernel.h>
>-#include <linux/module.h>
>-#include <drm/drmP.h>
>+#include <linux/export.h>
>+
>+#include <drm/drm_modes.h>
>+
> #include "meson_drv.h"
>+#include "meson_registers.h"
> #include "meson_venc.h"
> #include "meson_vpp.h"
>-#include "meson_vclk.h"
>-#include "meson_registers.h"
> 
> /**
>  * DOC: Video Encoder
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_venc_cvbs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_venc_cvbs.c
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_venc_cvbs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_venc_cvbs.c	2019-08-31 15:01:12.046736185 -0500
>@@ -9,19 +9,18 @@
>  *     Jasper St. Pierre <jstpierre@mecheye.net>
>  */
> 
>-#include <linux/kernel.h>
>-#include <linux/module.h>
>+#include <linux/export.h>
> #include <linux/of_graph.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_device.h>
> #include <drm/drm_edid.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_print.h>
> 
>-#include "meson_venc_cvbs.h"
>-#include "meson_venc.h"
>-#include "meson_vclk.h"
> #include "meson_registers.h"
>+#include "meson_vclk.h"
>+#include "meson_venc_cvbs.h"
> 
> /* HHI VDAC Registers */
> #define HHI_VDAC_CNTL0		0x2F4 /* 0xbd offset in data sheet */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_venc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_venc.h
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_venc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_venc.h	2019-08-31 15:01:12.046736185 -0500
>@@ -14,6 +14,8 @@
> #ifndef __MESON_VENC_H
> #define __MESON_VENC_H
> 
>+struct drm_display_mode;
>+
> enum {
> 	MESON_VENC_MODE_NONE = 0,
> 	MESON_VENC_MODE_CVBS_PAL,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_viu.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_viu.c
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_viu.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_viu.c	2019-08-31 15:01:12.046736185 -0500
>@@ -6,13 +6,10 @@
>  * Copyright (C) 2014 Endless Mobile
>  */
> 
>-#include <linux/kernel.h>
>-#include <linux/module.h>
>-#include <drm/drmP.h>
>+#include <linux/export.h>
>+
> #include "meson_drv.h"
> #include "meson_viu.h"
>-#include "meson_vpp.h"
>-#include "meson_venc.h"
> #include "meson_registers.h"
> 
> /**
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_vpp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_vpp.c
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_vpp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_vpp.c	2019-08-31 15:01:12.046736185 -0500
>@@ -6,12 +6,11 @@
>  * Copyright (C) 2014 Endless Mobile
>  */
> 
>-#include <linux/kernel.h>
>-#include <linux/module.h>
>-#include <drm/drmP.h>
>+#include <linux/export.h>
>+
> #include "meson_drv.h"
>-#include "meson_vpp.h"
> #include "meson_registers.h"
>+#include "meson_vpp.h"
> 
> /**
>  * DOC: Video Post Processing
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/meson/meson_vpp.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_vpp.h
>--- linux-5.3-rc6/drivers/gpu/drm/meson/meson_vpp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/meson/meson_vpp.h	2019-08-31 15:01:12.046736185 -0500
>@@ -9,6 +9,9 @@
> #ifndef __MESON_VPP_H
> #define __MESON_VPP_H
> 
>+struct drm_rect;
>+struct meson_drm;
>+
> /* Mux VIU/VPP to ENCI */
> #define MESON_VIU_VPP_MUX_ENCI	0x5
> /* Mux VIU/VPP to ENCP */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mga/mga_dma.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_dma.c
>--- linux-5.3-rc6/drivers/gpu/drm/mga/mga_dma.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_dma.c	2019-08-31 15:01:12.046736185 -0500
>@@ -35,8 +35,8 @@
>  * \author Gareth Hughes <gareth@valinux.com>
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/mga_drm.h>
>+#include <linux/delay.h>
>+
> #include "mga_drv.h"
> 
> #define MGA_DEFAULT_USEC_TIMEOUT	10000
>@@ -62,7 +62,7 @@
> 			MGA_WRITE8(MGA_CRTC_INDEX, 0);
> 			return 0;
> 		}
>-		DRM_UDELAY(1);
>+		udelay(1);
> 	}
> 
> #if MGA_DMA_DEBUG
>@@ -114,7 +114,7 @@
> 		status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
> 		if (status == MGA_ENDPRDMASTS)
> 			break;
>-		DRM_UDELAY(1);
>+		udelay(1);
> 	}
> 
> 	if (primary->tail == primary->last_flush) {
>@@ -1120,7 +1120,7 @@
> 	 */
> 	if (d->send_count != 0) {
> 		DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
>-			  DRM_CURRENTPID, d->send_count);
>+			  task_pid_nr(current), d->send_count);
> 		return -EINVAL;
> 	}
> 
>@@ -1128,7 +1128,8 @@
> 	 */
> 	if (d->request_count < 0 || d->request_count > dma->buf_count) {
> 		DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
>-			  DRM_CURRENTPID, d->request_count, dma->buf_count);
>+			  task_pid_nr(current), d->request_count,
>+			  dma->buf_count);
> 		return -EINVAL;
> 	}
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mga/mga_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/mga/mga_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_drv.c	2019-08-31 15:01:12.046736185 -0500
>@@ -31,12 +31,11 @@
> 
> #include <linux/module.h>
> 
>-#include <drm/drmP.h>
>-#include <drm/mga_drm.h>
>-#include "mga_drv.h"
>-
>+#include <drm/drm_drv.h>
> #include <drm/drm_pciids.h>
> 
>+#include "mga_drv.h"
>+
> static struct pci_device_id pciidlist[] = {
> 	mga_PCI_IDS
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mga/mga_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/mga/mga_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_drv.h	2019-08-31 15:01:12.046736185 -0500
>@@ -31,7 +31,20 @@
> #ifndef __MGA_DRV_H__
> #define __MGA_DRV_H__
> 
>+#include <linux/irqreturn.h>
>+#include <linux/slab.h>
>+
>+#include <drm/drm_agpsupport.h>
>+#include <drm/drm_device.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_ioctl.h>
>+#include <drm/drm_irq.h>
> #include <drm/drm_legacy.h>
>+#include <drm/drm_pci.h>
>+#include <drm/drm_print.h>
>+#include <drm/drm_sarea.h>
>+#include <drm/drm_vblank.h>
>+#include <drm/mga_drm.h>
> 
> /* General customization:
>  */
>@@ -188,7 +201,7 @@
> extern int mga_enable_vblank(struct drm_device *dev, unsigned int pipe);
> extern void mga_disable_vblank(struct drm_device *dev, unsigned int pipe);
> extern u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
>-extern int mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence);
>+extern void mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence);
> extern int mga_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
> extern irqreturn_t mga_driver_irq_handler(int irq, void *arg);
> extern void mga_driver_irq_preinstall(struct drm_device *dev);
>@@ -199,10 +212,14 @@
> 
> #define mga_flush_write_combine()	wmb()
> 
>-#define MGA_READ8(reg)		DRM_READ8(dev_priv->mmio, (reg))
>-#define MGA_READ(reg)		DRM_READ32(dev_priv->mmio, (reg))
>-#define MGA_WRITE8(reg, val)	DRM_WRITE8(dev_priv->mmio, (reg), (val))
>-#define MGA_WRITE(reg, val)	DRM_WRITE32(dev_priv->mmio, (reg), (val))
>+#define MGA_READ8(reg) \
>+	readb(((void __iomem *)dev_priv->mmio->handle) + (reg))
>+#define MGA_READ(reg) \
>+	readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
>+#define MGA_WRITE8(reg, val) \
>+	writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
>+#define MGA_WRITE(reg, val) \
>+	writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
> 
> #define DWGREG0		0x1c00
> #define DWGREG0_END	0x1dff
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mga/mga_ioc32.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_ioc32.c
>--- linux-5.3-rc6/drivers/gpu/drm/mga/mga_ioc32.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_ioc32.c	2019-08-31 15:01:12.046736185 -0500
>@@ -30,10 +30,9 @@
>  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>  * IN THE SOFTWARE.
>  */
>+
> #include <linux/compat.h>
> 
>-#include <drm/drmP.h>
>-#include <drm/mga_drm.h>
> #include "mga_drv.h"
> 
> typedef struct drm32_mga_init {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mga/mga_irq.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_irq.c
>--- linux-5.3-rc6/drivers/gpu/drm/mga/mga_irq.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_irq.c	2019-08-31 15:01:12.047736185 -0500
>@@ -31,8 +31,6 @@
>  *    Eric Anholt <anholt@FreeBSD.org>
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/mga_drm.h>
> #include "mga_drv.h"
> 
> u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
>@@ -118,23 +116,21 @@
> 	/* MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN); */
> }
> 
>-int mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence)
>+void mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence)
> {
> 	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
> 	unsigned int cur_fence;
>-	int ret = 0;
> 
> 	/* Assume that the user has missed the current sequence number
> 	 * by about a day rather than she wants to wait for years
> 	 * using fences.
> 	 */
>-	DRM_WAIT_ON(ret, dev_priv->fence_queue, 3 * HZ,
>+	wait_event_timeout(dev_priv->fence_queue,
> 		    (((cur_fence = atomic_read(&dev_priv->last_fence_retired))
>-		      - *sequence) <= (1 << 23)));
>+		      - *sequence) <= (1 << 23)),
>+		    msecs_to_jiffies(3000));
> 
> 	*sequence = cur_fence;
>-
>-	return ret;
> }
> 
> void mga_driver_irq_preinstall(struct drm_device *dev)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mga/mga_state.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_state.c
>--- linux-5.3-rc6/drivers/gpu/drm/mga/mga_state.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_state.c	2019-08-31 15:01:12.047736185 -0500
>@@ -32,8 +32,6 @@
>  *    Gareth Hughes <gareth@valinux.com>
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/mga_drm.h>
> #include "mga_drv.h"
> 
> /* ================================================================
>@@ -1016,7 +1014,7 @@
> 		return -EINVAL;
> 	}
> 
>-	DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
>+	DRM_DEBUG("pid=%d\n", task_pid_nr(current));
> 
> 	switch (param->param) {
> 	case MGA_PARAM_IRQ_NR:
>@@ -1048,7 +1046,7 @@
> 		return -EINVAL;
> 	}
> 
>-	DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
>+	DRM_DEBUG("pid=%d\n", task_pid_nr(current));
> 
> 	/* I would normal do this assignment in the declaration of fence,
> 	 * but dev_priv may be NULL.
>@@ -1077,7 +1075,7 @@
> 		return -EINVAL;
> 	}
> 
>-	DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
>+	DRM_DEBUG("pid=%d\n", task_pid_nr(current));
> 
> 	mga_driver_fence_wait(dev, fence);
> 	return 0;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mga/mga_warp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_warp.c
>--- linux-5.3-rc6/drivers/gpu/drm/mga/mga_warp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mga/mga_warp.c	2019-08-31 15:01:12.047736185 -0500
>@@ -29,11 +29,9 @@
> 
> #include <linux/firmware.h>
> #include <linux/ihex.h>
>-#include <linux/platform_device.h>
> #include <linux/module.h>
>+#include <linux/platform_device.h>
> 
>-#include <drm/drmP.h>
>-#include <drm/mga_drm.h>
> #include "mga_drv.h"
> 
> #define FIRMWARE_G200 "matrox/g200_warp.fw"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mgag200/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/mgag200/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/Makefile	2019-08-31 15:01:12.047736185 -0500
>@@ -1,5 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
> mgag200-y   := mgag200_main.o mgag200_mode.o mgag200_cursor.o \
>-	mgag200_drv.o mgag200_fb.o mgag200_i2c.o mgag200_ttm.o
>+	mgag200_drv.o mgag200_i2c.o mgag200_ttm.o
> 
> obj-$(CONFIG_DRM_MGAG200) += mgag200.o
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_cursor.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_cursor.c
>--- linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_cursor.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_cursor.c	2019-08-31 15:01:12.047736185 -0500
>@@ -5,7 +5,8 @@
>  * Author: Christopher Harvey <charvey@matrox.com>
>  */
> 
>-#include <drm/drmP.h>
>+#include <drm/drm_pci.h>
>+
> #include "mgag200_drv.h"
> 
> static bool warn_transparent = true;
>@@ -98,11 +99,12 @@
> 	}
> 
> 	/* Pin and map up-coming buffer to write colour indices */
>-	ret = drm_gem_vram_pin(pixels_next, 0);
>-	if (ret)
>+	ret = drm_gem_vram_pin(pixels_next, DRM_GEM_VRAM_PL_FLAG_VRAM);
>+	if (ret) {
> 		dev_err(&dev->pdev->dev,
> 			"failed to pin cursor buffer: %d\n", ret);
> 		goto err_drm_gem_vram_kunmap_src;
>+	}
> 	dst = drm_gem_vram_kmap(pixels_next, true, NULL);
> 	if (IS_ERR(dst)) {
> 		ret = PTR_ERR(dst);
>@@ -110,7 +112,7 @@
> 			"failed to kmap cursor updates: %d\n", ret);
> 		goto err_drm_gem_vram_unpin_dst;
> 	}
>-	gpu_addr = drm_gem_vram_offset(pixels_2);
>+	gpu_addr = drm_gem_vram_offset(pixels_next);
> 	if (gpu_addr < 0) {
> 		ret = (int)gpu_addr;
> 		dev_err(&dev->pdev->dev,
>@@ -211,7 +213,6 @@
> 	mdev->cursor.pixels_current = pixels_next;
> 
> 	drm_gem_vram_kunmap(pixels_next);
>-	drm_gem_vram_unpin(pixels_next);
> 	drm_gem_vram_kunmap(gbo);
> 	drm_gem_vram_unpin(gbo);
> 	drm_gem_object_put_unlocked(obj);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_drv.c	2019-08-31 15:01:12.047736185 -0500
>@@ -5,14 +5,18 @@
>  * Authors: Matthew Garrett
>  *          Dave Airlie
>  */
>+
> #include <linux/module.h>
> #include <linux/console.h>
>-#include <drm/drmP.h>
>-
>-#include "mgag200_drv.h"
> 
>+#include <drm/drm_drv.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_ioctl.h>
>+#include <drm/drm_pci.h>
> #include <drm/drm_pciids.h>
> 
>+#include "mgag200_drv.h"
>+
> /*
>  * This is the generic driver code. This binds the driver to the drm core,
>  * which then performs further device association and calls our graphics init
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_drv.h	2019-08-31 15:01:12.047736185 -0500
>@@ -10,19 +10,17 @@
> #ifndef __MGAG200_DRV_H__
> #define __MGAG200_DRV_H__
> 
>+#include <linux/i2c-algo-bit.h>
>+#include <linux/i2c.h>
>+
> #include <video/vga.h>
> 
> #include <drm/drm_encoder.h>
> #include <drm/drm_fb_helper.h>
>-
> #include <drm/drm_gem.h>
> #include <drm/drm_gem_vram_helper.h>
>-
> #include <drm/drm_vram_mm_helper.h>
> 
>-#include <linux/i2c.h>
>-#include <linux/i2c-algo-bit.h>
>-
> #include "mgag200_reg.h"
> 
> #define DRIVER_AUTHOR		"Matthew Garrett"
>@@ -100,21 +98,6 @@
> #define to_mga_crtc(x) container_of(x, struct mga_crtc, base)
> #define to_mga_encoder(x) container_of(x, struct mga_encoder, base)
> #define to_mga_connector(x) container_of(x, struct mga_connector, base)
>-#define to_mga_framebuffer(x) container_of(x, struct mga_framebuffer, base)
>-
>-struct mga_framebuffer {
>-	struct drm_framebuffer base;
>-	struct drm_gem_object *obj;
>-};
>-
>-struct mga_fbdev {
>-	struct drm_fb_helper helper; /* must be first */
>-	struct mga_framebuffer mfb;
>-	void *sysram;
>-	int size;
>-	int x1, y1, x2, y2; /* dirty rect */
>-	spinlock_t dirty_lock;
>-};
> 
> struct mga_crtc {
> 	struct drm_crtc base;
>@@ -189,7 +172,6 @@
> 	struct mga_mc			mc;
> 	struct mga_mode_info		mode_info;
> 
>-	struct mga_fbdev *mfbdev;
> 	struct mga_cursor cursor;
> 
> 	bool				suspended;
>@@ -210,25 +192,9 @@
> int mgag200_modeset_init(struct mga_device *mdev);
> void mgag200_modeset_fini(struct mga_device *mdev);
> 
>-				/* mgag200_fb.c */
>-int mgag200_fbdev_init(struct mga_device *mdev);
>-void mgag200_fbdev_fini(struct mga_device *mdev);
>-
> 				/* mgag200_main.c */
>-int mgag200_framebuffer_init(struct drm_device *dev,
>-			     struct mga_framebuffer *mfb,
>-			     const struct drm_mode_fb_cmd2 *mode_cmd,
>-			     struct drm_gem_object *obj);
>-
>-
> int mgag200_driver_load(struct drm_device *dev, unsigned long flags);
> void mgag200_driver_unload(struct drm_device *dev);
>-int mgag200_gem_create(struct drm_device *dev,
>-		   u32 size, bool iskernel,
>-		       struct drm_gem_object **obj);
>-int mgag200_dumb_create(struct drm_file *file,
>-			struct drm_device *dev,
>-			struct drm_mode_create_dumb *args);
> 
> 				/* mgag200_i2c.c */
> struct mga_i2c_chan *mgag200_i2c_create(struct drm_device *dev);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_fb.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_fb.c
>--- linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_fb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_fb.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,315 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0-only
>-/*
>- * Copyright 2010 Matt Turner.
>- * Copyright 2012 Red Hat
>- *
>- * Authors: Matthew Garrett
>- *          Matt Turner
>- *          Dave Airlie
>- */
>-#include <linux/module.h>
>-#include <drm/drmP.h>
>-#include <drm/drm_util.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_crtc_helper.h>
>-
>-#include "mgag200_drv.h"
>-
>-static void mga_dirty_update(struct mga_fbdev *mfbdev,
>-			     int x, int y, int width, int height)
>-{
>-	int i;
>-	struct drm_gem_object *obj;
>-	struct drm_gem_vram_object *gbo;
>-	int src_offset, dst_offset;
>-	int bpp = mfbdev->mfb.base.format->cpp[0];
>-	int ret;
>-	u8 *dst;
>-	bool unmap = false;
>-	bool store_for_later = false;
>-	int x2, y2;
>-	unsigned long flags;
>-
>-	obj = mfbdev->mfb.obj;
>-	gbo = drm_gem_vram_of_gem(obj);
>-
>-	if (drm_can_sleep()) {
>-		/* We pin the BO so it won't be moved during the
>-		 * update. The actual location, video RAM or system
>-		 * memory, is not important.
>-		 */
>-		ret = drm_gem_vram_pin(gbo, 0);
>-		if (ret) {
>-			if (ret != -EBUSY)
>-				return;
>-			store_for_later = true;
>-		}
>-	} else {
>-		store_for_later = true;
>-	}
>-
>-	x2 = x + width - 1;
>-	y2 = y + height - 1;
>-	spin_lock_irqsave(&mfbdev->dirty_lock, flags);
>-
>-	if (mfbdev->y1 < y)
>-		y = mfbdev->y1;
>-	if (mfbdev->y2 > y2)
>-		y2 = mfbdev->y2;
>-	if (mfbdev->x1 < x)
>-		x = mfbdev->x1;
>-	if (mfbdev->x2 > x2)
>-		x2 = mfbdev->x2;
>-
>-	if (store_for_later) {
>-		mfbdev->x1 = x;
>-		mfbdev->x2 = x2;
>-		mfbdev->y1 = y;
>-		mfbdev->y2 = y2;
>-		spin_unlock_irqrestore(&mfbdev->dirty_lock, flags);
>-		return;
>-	}
>-
>-	mfbdev->x1 = mfbdev->y1 = INT_MAX;
>-	mfbdev->x2 = mfbdev->y2 = 0;
>-	spin_unlock_irqrestore(&mfbdev->dirty_lock, flags);
>-
>-	dst = drm_gem_vram_kmap(gbo, false, NULL);
>-	if (IS_ERR(dst)) {
>-		DRM_ERROR("failed to kmap fb updates\n");
>-		goto out;
>-	} else if (!dst) {
>-		dst = drm_gem_vram_kmap(gbo, true, NULL);
>-		if (IS_ERR(dst)) {
>-			DRM_ERROR("failed to kmap fb updates\n");
>-			goto out;
>-		}
>-		unmap = true;
>-	}
>-
>-	for (i = y; i <= y2; i++) {
>-		/* assume equal stride for now */
>-		src_offset = dst_offset =
>-			i * mfbdev->mfb.base.pitches[0] + (x * bpp);
>-		memcpy_toio(dst + dst_offset, mfbdev->sysram + src_offset,
>-			    (x2 - x + 1) * bpp);
>-	}
>-
>-	if (unmap)
>-		drm_gem_vram_kunmap(gbo);
>-
>-out:
>-	drm_gem_vram_unpin(gbo);
>-}
>-
>-static void mga_fillrect(struct fb_info *info,
>-			 const struct fb_fillrect *rect)
>-{
>-	struct mga_fbdev *mfbdev = info->par;
>-	drm_fb_helper_sys_fillrect(info, rect);
>-	mga_dirty_update(mfbdev, rect->dx, rect->dy, rect->width,
>-			 rect->height);
>-}
>-
>-static void mga_copyarea(struct fb_info *info,
>-			 const struct fb_copyarea *area)
>-{
>-	struct mga_fbdev *mfbdev = info->par;
>-	drm_fb_helper_sys_copyarea(info, area);
>-	mga_dirty_update(mfbdev, area->dx, area->dy, area->width,
>-			 area->height);
>-}
>-
>-static void mga_imageblit(struct fb_info *info,
>-			  const struct fb_image *image)
>-{
>-	struct mga_fbdev *mfbdev = info->par;
>-	drm_fb_helper_sys_imageblit(info, image);
>-	mga_dirty_update(mfbdev, image->dx, image->dy, image->width,
>-			 image->height);
>-}
>-
>-
>-static struct fb_ops mgag200fb_ops = {
>-	.owner = THIS_MODULE,
>-	.fb_check_var = drm_fb_helper_check_var,
>-	.fb_set_par = drm_fb_helper_set_par,
>-	.fb_fillrect = mga_fillrect,
>-	.fb_copyarea = mga_copyarea,
>-	.fb_imageblit = mga_imageblit,
>-	.fb_pan_display = drm_fb_helper_pan_display,
>-	.fb_blank = drm_fb_helper_blank,
>-	.fb_setcmap = drm_fb_helper_setcmap,
>-};
>-
>-static int mgag200fb_create_object(struct mga_fbdev *afbdev,
>-				   const struct drm_mode_fb_cmd2 *mode_cmd,
>-				   struct drm_gem_object **gobj_p)
>-{
>-	struct drm_device *dev = afbdev->helper.dev;
>-	u32 size;
>-	struct drm_gem_object *gobj;
>-	int ret = 0;
>-
>-	size = mode_cmd->pitches[0] * mode_cmd->height;
>-	ret = mgag200_gem_create(dev, size, true, &gobj);
>-	if (ret)
>-		return ret;
>-
>-	*gobj_p = gobj;
>-	return ret;
>-}
>-
>-static int mgag200fb_create(struct drm_fb_helper *helper,
>-			   struct drm_fb_helper_surface_size *sizes)
>-{
>-	struct mga_fbdev *mfbdev =
>-		container_of(helper, struct mga_fbdev, helper);
>-	struct drm_device *dev = mfbdev->helper.dev;
>-	struct drm_mode_fb_cmd2 mode_cmd;
>-	struct mga_device *mdev = dev->dev_private;
>-	struct fb_info *info;
>-	struct drm_framebuffer *fb;
>-	struct drm_gem_object *gobj = NULL;
>-	int ret;
>-	void *sysram;
>-	int size;
>-
>-	mode_cmd.width = sizes->surface_width;
>-	mode_cmd.height = sizes->surface_height;
>-	mode_cmd.pitches[0] = mode_cmd.width * ((sizes->surface_bpp + 7) / 8);
>-
>-	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
>-							  sizes->surface_depth);
>-	size = mode_cmd.pitches[0] * mode_cmd.height;
>-
>-	ret = mgag200fb_create_object(mfbdev, &mode_cmd, &gobj);
>-	if (ret) {
>-		DRM_ERROR("failed to create fbcon backing object %d\n", ret);
>-		return ret;
>-	}
>-
>-	sysram = vmalloc(size);
>-	if (!sysram) {
>-		ret = -ENOMEM;
>-		goto err_sysram;
>-	}
>-
>-	info = drm_fb_helper_alloc_fbi(helper);
>-	if (IS_ERR(info)) {
>-		ret = PTR_ERR(info);
>-		goto err_alloc_fbi;
>-	}
>-
>-	ret = mgag200_framebuffer_init(dev, &mfbdev->mfb, &mode_cmd, gobj);
>-	if (ret)
>-		goto err_alloc_fbi;
>-
>-	mfbdev->sysram = sysram;
>-	mfbdev->size = size;
>-
>-	fb = &mfbdev->mfb.base;
>-
>-	/* setup helper */
>-	mfbdev->helper.fb = fb;
>-
>-	info->fbops = &mgag200fb_ops;
>-
>-	/* setup aperture base/size for vesafb takeover */
>-	info->apertures->ranges[0].base = mdev->dev->mode_config.fb_base;
>-	info->apertures->ranges[0].size = mdev->mc.vram_size;
>-
>-	drm_fb_helper_fill_info(info, &mfbdev->helper, sizes);
>-
>-	info->screen_base = sysram;
>-	info->screen_size = size;
>-	info->pixmap.flags = FB_PIXMAP_SYSTEM;
>-
>-	DRM_DEBUG_KMS("allocated %dx%d\n",
>-		      fb->width, fb->height);
>-
>-	return 0;
>-
>-err_alloc_fbi:
>-	vfree(sysram);
>-err_sysram:
>-	drm_gem_object_put_unlocked(gobj);
>-
>-	return ret;
>-}
>-
>-static int mga_fbdev_destroy(struct drm_device *dev,
>-				struct mga_fbdev *mfbdev)
>-{
>-	struct mga_framebuffer *mfb = &mfbdev->mfb;
>-
>-	drm_fb_helper_unregister_fbi(&mfbdev->helper);
>-
>-	if (mfb->obj) {
>-		drm_gem_object_put_unlocked(mfb->obj);
>-		mfb->obj = NULL;
>-	}
>-	drm_fb_helper_fini(&mfbdev->helper);
>-	vfree(mfbdev->sysram);
>-	drm_framebuffer_unregister_private(&mfb->base);
>-	drm_framebuffer_cleanup(&mfb->base);
>-
>-	return 0;
>-}
>-
>-static const struct drm_fb_helper_funcs mga_fb_helper_funcs = {
>-	.fb_probe = mgag200fb_create,
>-};
>-
>-int mgag200_fbdev_init(struct mga_device *mdev)
>-{
>-	struct mga_fbdev *mfbdev;
>-	int ret;
>-	int bpp_sel = 32;
>-
>-	/* prefer 16bpp on low end gpus with limited VRAM */
>-	if (IS_G200_SE(mdev) && mdev->mc.vram_size < (2048*1024))
>-		bpp_sel = 16;
>-
>-	mfbdev = devm_kzalloc(mdev->dev->dev, sizeof(struct mga_fbdev), GFP_KERNEL);
>-	if (!mfbdev)
>-		return -ENOMEM;
>-
>-	mdev->mfbdev = mfbdev;
>-	spin_lock_init(&mfbdev->dirty_lock);
>-
>-	drm_fb_helper_prepare(mdev->dev, &mfbdev->helper, &mga_fb_helper_funcs);
>-
>-	ret = drm_fb_helper_init(mdev->dev, &mfbdev->helper,
>-				 MGAG200FB_CONN_LIMIT);
>-	if (ret)
>-		goto err_fb_helper;
>-
>-	ret = drm_fb_helper_single_add_all_connectors(&mfbdev->helper);
>-	if (ret)
>-		goto err_fb_setup;
>-
>-	/* disable all the possible outputs/crtcs before entering KMS mode */
>-	drm_helper_disable_unused_functions(mdev->dev);
>-
>-	ret = drm_fb_helper_initial_config(&mfbdev->helper, bpp_sel);
>-	if (ret)
>-		goto err_fb_setup;
>-
>-	return 0;
>-
>-err_fb_setup:
>-	drm_fb_helper_fini(&mfbdev->helper);
>-err_fb_helper:
>-	mdev->mfbdev = NULL;
>-
>-	return ret;
>-}
>-
>-void mgag200_fbdev_fini(struct mga_device *mdev)
>-{
>-	if (!mdev->mfbdev)
>-		return;
>-
>-	mga_fbdev_destroy(mdev->dev, mdev->mfbdev);
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_i2c.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_i2c.c
>--- linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_i2c.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_i2c.c	2019-08-31 15:01:12.047736185 -0500
>@@ -25,10 +25,12 @@
> /*
>  * Authors: Dave Airlie <airlied@redhat.com>
>  */
>+
> #include <linux/export.h>
>-#include <linux/i2c.h>
> #include <linux/i2c-algo-bit.h>
>-#include <drm/drmP.h>
>+#include <linux/i2c.h>
>+
>+#include <drm/drm_pci.h>
> 
> #include "mgag200_drv.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_main.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_main.c
>--- linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_main.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_main.c	2019-08-31 15:01:12.047736185 -0500
>@@ -7,70 +7,15 @@
>  *          Matt Turner
>  *          Dave Airlie
>  */
>-#include <drm/drmP.h>
>-#include <drm/drm_crtc_helper.h>
>-#include "mgag200_drv.h"
>-
>-static void mga_user_framebuffer_destroy(struct drm_framebuffer *fb)
>-{
>-	struct mga_framebuffer *mga_fb = to_mga_framebuffer(fb);
>-
>-	drm_gem_object_put_unlocked(mga_fb->obj);
>-	drm_framebuffer_cleanup(fb);
>-	kfree(fb);
>-}
>-
>-static const struct drm_framebuffer_funcs mga_fb_funcs = {
>-	.destroy = mga_user_framebuffer_destroy,
>-};
> 
>-int mgag200_framebuffer_init(struct drm_device *dev,
>-			     struct mga_framebuffer *gfb,
>-			     const struct drm_mode_fb_cmd2 *mode_cmd,
>-			     struct drm_gem_object *obj)
>-{
>-	int ret;
>-
>-	drm_helper_mode_fill_fb_struct(dev, &gfb->base, mode_cmd);
>-	gfb->obj = obj;
>-	ret = drm_framebuffer_init(dev, &gfb->base, &mga_fb_funcs);
>-	if (ret) {
>-		DRM_ERROR("drm_framebuffer_init failed: %d\n", ret);
>-		return ret;
>-	}
>-	return 0;
>-}
>-
>-static struct drm_framebuffer *
>-mgag200_user_framebuffer_create(struct drm_device *dev,
>-				struct drm_file *filp,
>-				const struct drm_mode_fb_cmd2 *mode_cmd)
>-{
>-	struct drm_gem_object *obj;
>-	struct mga_framebuffer *mga_fb;
>-	int ret;
>-
>-	obj = drm_gem_object_lookup(filp, mode_cmd->handles[0]);
>-	if (obj == NULL)
>-		return ERR_PTR(-ENOENT);
>-
>-	mga_fb = kzalloc(sizeof(*mga_fb), GFP_KERNEL);
>-	if (!mga_fb) {
>-		drm_gem_object_put_unlocked(obj);
>-		return ERR_PTR(-ENOMEM);
>-	}
>+#include <drm/drm_crtc_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_pci.h>
> 
>-	ret = mgag200_framebuffer_init(dev, mga_fb, mode_cmd, obj);
>-	if (ret) {
>-		drm_gem_object_put_unlocked(obj);
>-		kfree(mga_fb);
>-		return ERR_PTR(ret);
>-	}
>-	return &mga_fb->base;
>-}
>+#include "mgag200_drv.h"
> 
> static const struct drm_mode_config_funcs mga_mode_funcs = {
>-	.fb_create = mgag200_user_framebuffer_create,
>+	.fb_create = drm_gem_fb_create
> };
> 
> static int mga_probe_vram(struct mga_device *mdev, void __iomem *mem)
>@@ -217,7 +162,7 @@
> 	if (IS_G200_SE(mdev) && mdev->mc.vram_size < (2048*1024))
> 		dev->mode_config.preferred_depth = 16;
> 	else
>-		dev->mode_config.preferred_depth = 24;
>+		dev->mode_config.preferred_depth = 32;
> 	dev->mode_config.prefer_shadow = 1;
> 
> 	r = mgag200_modeset_init(mdev);
>@@ -241,6 +186,10 @@
> 	}
> 	mdev->cursor.pixels_current = NULL;
> 
>+	r = drm_fbdev_generic_setup(mdev->dev, 0);
>+	if (r)
>+		goto err_modeset;
>+
> 	return 0;
> 
> err_modeset:
>@@ -259,32 +208,7 @@
> 	if (mdev == NULL)
> 		return;
> 	mgag200_modeset_fini(mdev);
>-	mgag200_fbdev_fini(mdev);
> 	drm_mode_config_cleanup(dev);
> 	mgag200_mm_fini(mdev);
> 	dev->dev_private = NULL;
> }
>-
>-int mgag200_gem_create(struct drm_device *dev,
>-		   u32 size, bool iskernel,
>-		   struct drm_gem_object **obj)
>-{
>-	struct drm_gem_vram_object *gbo;
>-	int ret;
>-
>-	*obj = NULL;
>-
>-	size = roundup(size, PAGE_SIZE);
>-	if (size == 0)
>-		return -EINVAL;
>-
>-	gbo = drm_gem_vram_create(dev, &dev->vram_mm->bdev, size, 0, false);
>-	if (IS_ERR(gbo)) {
>-		ret = PTR_ERR(gbo);
>-		if (ret != -ERESTARTSYS)
>-			DRM_ERROR("failed to allocate GEM object\n");
>-		return ret;
>-	}
>-	*obj = &gbo->gem;
>-	return 0;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_mode.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_mode.c
>--- linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_mode.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_mode.c	2019-08-31 15:01:12.047736185 -0500
>@@ -10,8 +10,9 @@
> 
> #include <linux/delay.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_crtc_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_pci.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> 
>@@ -859,28 +860,16 @@
> 				struct drm_framebuffer *fb,
> 				int x, int y, int atomic)
> {
>-	struct mga_device *mdev = crtc->dev->dev_private;
>-	struct drm_gem_object *obj;
>-	struct mga_framebuffer *mga_fb;
> 	struct drm_gem_vram_object *gbo;
> 	int ret;
> 	s64 gpu_addr;
>-	void *base;
> 
> 	if (!atomic && fb) {
>-		mga_fb = to_mga_framebuffer(fb);
>-		obj = mga_fb->obj;
>-		gbo = drm_gem_vram_of_gem(obj);
>-
>-		/* unmap if console */
>-		if (&mdev->mfbdev->mfb == mga_fb)
>-			drm_gem_vram_kunmap(gbo);
>+		gbo = drm_gem_vram_of_gem(fb->obj[0]);
> 		drm_gem_vram_unpin(gbo);
> 	}
> 
>-	mga_fb = to_mga_framebuffer(crtc->primary->fb);
>-	obj = mga_fb->obj;
>-	gbo = drm_gem_vram_of_gem(obj);
>+	gbo = drm_gem_vram_of_gem(crtc->primary->fb->obj[0]);
> 
> 	ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM);
> 	if (ret)
>@@ -891,15 +880,6 @@
> 		goto err_drm_gem_vram_unpin;
> 	}
> 
>-	if (&mdev->mfbdev->mfb == mga_fb) {
>-		/* if pushing console in kmap it */
>-		base = drm_gem_vram_kmap(gbo, true, NULL);
>-		if (IS_ERR(base)) {
>-			ret = PTR_ERR(base);
>-			DRM_ERROR("failed to kmap fbcon\n");
>-		}
>-	}
>-
> 	mga_set_start_address(crtc, (u32)gpu_addr);
> 
> 	return 0;
>@@ -1423,14 +1403,9 @@
> 	DRM_DEBUG_KMS("\n");
> 	mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
> 	if (crtc->primary->fb) {
>-		struct mga_device *mdev = crtc->dev->dev_private;
>-		struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb);
>-		struct drm_gem_object *obj = mga_fb->obj;
>-		struct drm_gem_vram_object *gbo = drm_gem_vram_of_gem(obj);
>-
>-		/* unmap if console */
>-		if (&mdev->mfbdev->mfb == mga_fb)
>-			drm_gem_vram_kunmap(gbo);
>+		struct drm_framebuffer *fb = crtc->primary->fb;
>+		struct drm_gem_vram_object *gbo =
>+			drm_gem_vram_of_gem(fb->obj[0]);
> 		drm_gem_vram_unpin(gbo);
> 	}
> 	crtc->primary->fb = NULL;
>@@ -1703,18 +1678,19 @@
> 		return NULL;
> 
> 	connector = &mga_connector->base;
>+	mga_connector->i2c = mgag200_i2c_create(dev);
>+	if (!mga_connector->i2c)
>+		DRM_ERROR("failed to add ddc bus\n");
> 
>-	drm_connector_init(dev, connector,
>-			   &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
>+	drm_connector_init_with_ddc(dev, connector,
>+				    &mga_vga_connector_funcs,
>+				    DRM_MODE_CONNECTOR_VGA,
>+				    &mga_connector->i2c->adapter);
> 
> 	drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
> 
> 	drm_connector_register(connector);
> 
>-	mga_connector->i2c = mgag200_i2c_create(dev);
>-	if (!mga_connector->i2c)
>-		DRM_ERROR("failed to add ddc bus\n");
>-
> 	return connector;
> }
> 
>@@ -1723,7 +1699,6 @@
> {
> 	struct drm_encoder *encoder;
> 	struct drm_connector *connector;
>-	int ret;
> 
> 	mdev->mode_info.mode_config_initialized = true;
> 
>@@ -1748,12 +1723,6 @@
> 
> 	drm_connector_attach_encoder(connector, encoder);
> 
>-	ret = mgag200_fbdev_init(mdev);
>-	if (ret) {
>-		DRM_ERROR("mga_fbdev_init failed\n");
>-		return ret;
>-	}
>-
> 	return 0;
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_ttm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_ttm.c
>--- linux-5.3-rc6/drivers/gpu/drm/mgag200/mgag200_ttm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mgag200/mgag200_ttm.c	2019-08-31 15:01:12.047736185 -0500
>@@ -25,7 +25,8 @@
> /*
>  * Authors: Dave Airlie <airlied@redhat.com>
>  */
>-#include <drm/drmP.h>
>+
>+#include <drm/drm_pci.h>
> 
> #include "mgag200_drv.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c	2019-08-31 15:01:12.047736185 -0500
>@@ -12,6 +12,7 @@
> 
> #include <drm/drm_damage_helper.h>
> #include <drm/drm_atomic_uapi.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
> 
> #include "msm_drv.h"
> #include "dpu_kms.h"
>@@ -764,8 +765,6 @@
> 	struct dpu_plane *pdpu = to_dpu_plane(plane);
> 	struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
> 	struct dpu_hw_fmt_layout layout;
>-	struct drm_gem_object *obj;
>-	struct dma_fence *fence;
> 	struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
> 	int ret;
> 
>@@ -782,10 +781,7 @@
> 	 *       we can use msm_atomic_prepare_fb() instead of doing the
> 	 *       implicit fence and fb prepare by hand here.
> 	 */
>-	obj = msm_framebuffer_bo(new_state->fb, 0);
>-	fence = reservation_object_get_excl_rcu(obj->resv);
>-	if (fence)
>-		drm_atomic_set_fence_for_plane(new_state, fence);
>+	drm_gem_fb_prepare_fb(plane, new_state);
> 
> 	if (pstate->aspace) {
> 		ret = msm_framebuffer_prepare(new_state->fb,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/msm/msm_atomic.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/msm/msm_atomic.c
>--- linux-5.3-rc6/drivers/gpu/drm/msm/msm_atomic.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/msm/msm_atomic.c	2019-08-31 15:01:12.047736185 -0500
>@@ -5,6 +5,7 @@
>  */
> 
> #include <drm/drm_atomic_uapi.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
> 
> #include "msm_drv.h"
> #include "msm_gem.h"
>@@ -37,16 +38,11 @@
> {
> 	struct msm_drm_private *priv = plane->dev->dev_private;
> 	struct msm_kms *kms = priv->kms;
>-	struct drm_gem_object *obj;
>-	struct dma_fence *fence;
> 
> 	if (!new_state->fb)
> 		return 0;
> 
>-	obj = msm_framebuffer_bo(new_state->fb, 0);
>-	fence = reservation_object_get_excl_rcu(obj->resv);
>-
>-	drm_atomic_set_fence_for_plane(new_state, fence);
>+	drm_gem_fb_prepare_fb(plane, new_state);
> 
> 	return msm_framebuffer_prepare(new_state->fb, kms->aspace);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/msm/msm_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/msm/msm_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/msm/msm_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/msm/msm_drv.c	2019-08-31 15:01:12.048736185 -0500
>@@ -984,17 +984,17 @@
> }
> 
> static const struct drm_ioctl_desc msm_ioctls[] = {
>-	DRM_IOCTL_DEF_DRV(MSM_GET_PARAM,    msm_ioctl_get_param,    DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(MSM_GEM_NEW,      msm_ioctl_gem_new,      DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(MSM_GEM_INFO,     msm_ioctl_gem_info,     DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT,   msm_ioctl_gem_submit,   DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE,   msm_ioctl_wait_fence,   DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE,  msm_ioctl_gem_madvise,  DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW,   msm_ioctl_submitqueue_new,   DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_AUTH|DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(MSM_GET_PARAM,    msm_ioctl_get_param,    DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(MSM_GEM_NEW,      msm_ioctl_gem_new,      DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(MSM_GEM_INFO,     msm_ioctl_gem_info,     DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT,   msm_ioctl_gem_submit,   DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE,   msm_ioctl_wait_fence,   DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE,  msm_ioctl_gem_madvise,  DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW,   msm_ioctl_submitqueue_new,   DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
> };
> 
> static const struct vm_operations_struct vm_ops = {
>@@ -1017,7 +1017,6 @@
> 
> static struct drm_driver msm_driver = {
> 	.driver_features    = DRIVER_GEM |
>-				DRIVER_PRIME |
> 				DRIVER_RENDER |
> 				DRIVER_ATOMIC |
> 				DRIVER_MODESET,
>@@ -1036,8 +1035,6 @@
> 	.dumb_map_offset    = msm_gem_dumb_map_offset,
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_export   = drm_gem_prime_export,
>-	.gem_prime_import   = drm_gem_prime_import,
> 	.gem_prime_pin      = msm_gem_prime_pin,
> 	.gem_prime_unpin    = msm_gem_prime_unpin,
> 	.gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/msm/msm_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/msm/msm_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/msm/msm_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/msm/msm_gem.c	2019-08-31 15:01:12.048736185 -0500
>@@ -975,7 +975,6 @@
> 
> static int msm_gem_new_impl(struct drm_device *dev,
> 		uint32_t size, uint32_t flags,
>-		struct reservation_object *resv,
> 		struct drm_gem_object **obj,
> 		bool struct_mutex_locked)
> {
>@@ -1002,9 +1001,6 @@
> 	msm_obj->flags = flags;
> 	msm_obj->madv = MSM_MADV_WILLNEED;
> 
>-	if (resv)
>-		msm_obj->base.resv = resv;
>-
> 	INIT_LIST_HEAD(&msm_obj->submit_entry);
> 	INIT_LIST_HEAD(&msm_obj->vmas);
> 
>@@ -1046,7 +1042,7 @@
> 	if (size == 0)
> 		return ERR_PTR(-EINVAL);
> 
>-	ret = msm_gem_new_impl(dev, size, flags, NULL, &obj, struct_mutex_locked);
>+	ret = msm_gem_new_impl(dev, size, flags, &obj, struct_mutex_locked);
> 	if (ret)
> 		goto fail;
> 
>@@ -1123,7 +1119,7 @@
> 
> 	size = PAGE_ALIGN(dmabuf->size);
> 
>-	ret = msm_gem_new_impl(dev, size, MSM_BO_WC, dmabuf->resv, &obj, false);
>+	ret = msm_gem_new_impl(dev, size, MSM_BO_WC, &obj, false);
> 	if (ret)
> 		goto fail;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/msm/msm_gpu.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/msm/msm_gpu.c
>--- linux-5.3-rc6/drivers/gpu/drm/msm/msm_gpu.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/msm/msm_gpu.c	2019-08-31 15:01:12.048736185 -0500
>@@ -95,7 +95,8 @@
> 	 */
> 
> 	gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev,
>-			&msm_devfreq_profile, "simple_ondemand", NULL);
>+			&msm_devfreq_profile, DEVFREQ_GOV_SIMPLE_ONDEMAND,
>+			NULL);
> 
> 	if (IS_ERR(gpu->devfreq.devfreq)) {
> 		DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mxsfb/mxsfb_crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/mxsfb/mxsfb_crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mxsfb/mxsfb_crtc.c	2019-08-31 15:01:12.048736185 -0500
>@@ -8,21 +8,23 @@
>  * Copyright (C) 2008 Embedded Alley Solutions, Inc All Rights Reserved.
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/clk.h>
>+#include <linux/iopoll.h>
>+#include <linux/of_graph.h>
>+#include <linux/platform_data/simplefb.h>
>+
>+#include <video/videomode.h>
>+
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
>-#include <drm/drm_fb_helper.h>
> #include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fb_helper.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_of.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/drm_simple_kms_helper.h>
>-#include <linux/clk.h>
>-#include <linux/iopoll.h>
>-#include <linux/of_graph.h>
>-#include <linux/platform_data/simplefb.h>
>-#include <video/videomode.h>
>+#include <drm/drm_vblank.h>
> 
> #include "mxsfb_drv.h"
> #include "mxsfb_regs.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mxsfb/mxsfb_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mxsfb/mxsfb_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/mxsfb/mxsfb_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mxsfb/mxsfb_drv.c	2019-08-31 15:01:12.048736185 -0500
>@@ -8,29 +8,32 @@
>  * Copyright (C) 2008 Embedded Alley Solutions, Inc All Rights Reserved.
>  */
> 
>-#include <linux/module.h>
>-#include <linux/spinlock.h>
> #include <linux/clk.h>
> #include <linux/component.h>
>+#include <linux/dma-mapping.h>
> #include <linux/list.h>
>+#include <linux/module.h>
> #include <linux/of_device.h>
> #include <linux/of_graph.h>
> #include <linux/of_reserved_mem.h>
> #include <linux/pm_runtime.h>
> #include <linux/reservation.h>
>+#include <linux/spinlock.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
>-#include <drm/drm_fb_helper.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fb_helper.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_irq.h>
> #include <drm/drm_of.h>
> #include <drm/drm_panel.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/drm_simple_kms_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "mxsfb_drv.h"
> #include "mxsfb_regs.h"
>@@ -313,8 +316,7 @@
> DEFINE_DRM_GEM_CMA_FOPS(fops);
> 
> static struct drm_driver mxsfb_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET |
>-				  DRIVER_PRIME | DRIVER_ATOMIC,
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.irq_handler		= mxsfb_irq_handler,
> 	.irq_preinstall		= mxsfb_irq_preinstall,
> 	.irq_uninstall		= mxsfb_irq_preinstall,
>@@ -323,8 +325,6 @@
> 	.dumb_create		= drm_gem_cma_dumb_create,
> 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
>-	.gem_prime_export	= drm_gem_prime_export,
>-	.gem_prime_import	= drm_gem_prime_import,
> 	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/mxsfb/mxsfb_out.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/mxsfb/mxsfb_out.c
>--- linux-5.3-rc6/drivers/gpu/drm/mxsfb/mxsfb_out.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/mxsfb/mxsfb_out.c	2019-08-31 15:01:12.048736185 -0500
>@@ -15,7 +15,6 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/drm_simple_kms_helper.h>
>-#include <drm/drmP.h>
> 
> #include "mxsfb_drv.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/nouveau/dispnv50/wndw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/dispnv50/wndw.c
>--- linux-5.3-rc6/drivers/gpu/drm/nouveau/dispnv50/wndw.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/dispnv50/wndw.c	2019-08-31 15:01:12.048736185 -0500
>@@ -457,7 +457,7 @@
> 		asyw->image.handle[0] = ctxdma->object.handle;
> 	}
> 
>-	asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv);
>+	asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.base.resv);
> 	asyw->image.offset[0] = fb->nvbo->bo.offset;
> 
> 	if (wndw->func->prepare) {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_abi16.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_abi16.c
>--- linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_abi16.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_abi16.c	2019-08-31 15:01:12.048736185 -0500
>@@ -139,7 +139,7 @@
> 	if (chan->ntfy) {
> 		nouveau_vma_del(&chan->ntfy_vma);
> 		nouveau_bo_unpin(chan->ntfy);
>-		drm_gem_object_put_unlocked(&chan->ntfy->gem);
>+		drm_gem_object_put_unlocked(&chan->ntfy->bo.base);
> 	}
> 
> 	if (chan->heap.block_size)
>@@ -245,12 +245,6 @@
> }
> 
> int
>-nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS)
>-{
>-	return -EINVAL;
>-}
>-
>-int
> nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
> {
> 	struct drm_nouveau_channel_alloc *init = data;
>@@ -345,7 +339,7 @@
> 			goto done;
> 	}
> 
>-	ret = drm_gem_handle_create(file_priv, &chan->ntfy->gem,
>+	ret = drm_gem_handle_create(file_priv, &chan->ntfy->bo.base,
> 				    &init->notifier_handle);
> 	if (ret)
> 		goto done;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_abi16.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_abi16.h
>--- linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_abi16.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_abi16.h	2019-08-31 15:01:12.048736185 -0500
>@@ -6,7 +6,6 @@
> 	struct drm_device *dev, void *data, struct drm_file *file_priv
> 
> int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS);
>-int nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS);
> int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS);
> int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS);
> int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_bo.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_bo.c
>--- linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_bo.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_bo.c	2019-08-31 15:01:12.049736185 -0500
>@@ -136,7 +136,7 @@
> 	struct drm_device *dev = drm->dev;
> 	struct nouveau_bo *nvbo = nouveau_bo(bo);
> 
>-	if (unlikely(nvbo->gem.filp))
>+	if (unlikely(nvbo->bo.base.filp))
> 		DRM_ERROR("bo %p still attached to GEM object\n", bo);
> 	WARN_ON(nvbo->pin_refcnt > 0);
> 	nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
>@@ -299,6 +299,7 @@
> 			  type, &nvbo->placement,
> 			  align >> PAGE_SHIFT, false, acc_size, sg,
> 			  robj, nouveau_bo_del_ttm);
>+
> 	if (ret) {
> 		/* ttm will call nouveau_bo_del_ttm if it fails.. */
> 		return ret;
>@@ -1323,7 +1324,7 @@
> {
> 	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
> 	struct drm_device *dev = drm->dev;
>-	struct dma_fence *fence = reservation_object_get_excl(bo->resv);
>+	struct dma_fence *fence = reservation_object_get_excl(bo->base.resv);
> 
> 	nv10_bo_put_tile_region(dev, *old_tile, fence);
> 	*old_tile = new_tile;
>@@ -1400,7 +1401,7 @@
> {
> 	struct nouveau_bo *nvbo = nouveau_bo(bo);
> 
>-	return drm_vma_node_verify_access(&nvbo->gem.vma_node,
>+	return drm_vma_node_verify_access(&nvbo->bo.base.vma_node,
> 					  filp->private_data);
> }
> 
>@@ -1654,7 +1655,7 @@
> void
> nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
> {
>-	struct reservation_object *resv = nvbo->bo.resv;
>+	struct reservation_object *resv = nvbo->bo.base.resv;
> 
> 	if (exclusive)
> 		reservation_object_add_excl_fence(resv, &fence->base);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_bo.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_bo.h
>--- linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_bo.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_bo.h	2019-08-31 15:01:12.049736185 -0500
>@@ -35,11 +35,6 @@
> 
> 	struct nouveau_drm_tile *tile;
> 
>-	/* Only valid if allocated via nouveau_gem_new() and iff you hold a
>-	 * gem reference to it! For debugging, use gem.filp != NULL to test
>-	 * whether it is valid. */
>-	struct drm_gem_object gem;
>-
> 	/* protect by the ttm reservation lock */
> 	int pin_refcnt;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_connector.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_connector.c
>--- linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_connector.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_connector.c	2019-08-31 15:01:12.049736185 -0500
>@@ -1349,7 +1349,7 @@
> 		break;
> 	case DRM_MODE_CONNECTOR_DisplayPort:
> 	case DRM_MODE_CONNECTOR_eDP:
>-		nv_connector->aux.dev = dev->dev;
>+		nv_connector->aux.dev = connector->kdev;
> 		nv_connector->aux.transfer = nouveau_connector_aux_xfer;
> 		snprintf(aux_name, sizeof(aux_name), "sor-%04x-%04x",
> 			 dcbe->hasht, dcbe->hashm);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_display.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_display.c
>--- linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_display.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_display.c	2019-08-31 15:01:12.049736185 -0500
>@@ -201,7 +201,7 @@
> 	struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
> 
> 	if (fb->nvbo)
>-		drm_gem_object_put_unlocked(&fb->nvbo->gem);
>+		drm_gem_object_put_unlocked(&fb->nvbo->bo.base);
> 
> 	drm_framebuffer_cleanup(drm_fb);
> 	kfree(fb);
>@@ -214,7 +214,7 @@
> {
> 	struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
> 
>-	return drm_gem_handle_create(file_priv, &fb->nvbo->gem, handle);
>+	return drm_gem_handle_create(file_priv, &fb->nvbo->bo.base, handle);
> }
> 
> static const struct drm_framebuffer_funcs nouveau_framebuffer_funcs = {
>@@ -660,8 +660,8 @@
> 	if (ret)
> 		return ret;
> 
>-	ret = drm_gem_handle_create(file_priv, &bo->gem, &args->handle);
>-	drm_gem_object_put_unlocked(&bo->gem);
>+	ret = drm_gem_handle_create(file_priv, &bo->bo.base, &args->handle);
>+	drm_gem_object_put_unlocked(&bo->bo.base);
> 	return ret;
> }
> 
>@@ -675,7 +675,7 @@
> 	gem = drm_gem_object_lookup(file_priv, handle);
> 	if (gem) {
> 		struct nouveau_bo *bo = nouveau_gem_object(gem);
>-		*poffset = drm_vma_node_offset_addr(&bo->bo.vma_node);
>+		*poffset = drm_vma_node_offset_addr(&bo->bo.base.vma_node);
> 		drm_gem_object_put_unlocked(gem);
> 		return 0;
> 	}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_drm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_drm.c
>--- linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_drm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_drm.c	2019-08-31 15:01:12.049736185 -0500
>@@ -1046,20 +1046,20 @@
> 
> static const struct drm_ioctl_desc
> nouveau_ioctls[] = {
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_INIT, nouveau_svmm_init, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_SVM_BIND, nouveau_svmm_bind, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_RENDER_ALLOW),
> };
> 
> long
>@@ -1105,7 +1105,7 @@
> static struct drm_driver
> driver_stub = {
> 	.driver_features =
>-		DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER
>+		DRIVER_GEM | DRIVER_MODESET | DRIVER_RENDER
> #if defined(CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT)
> 		| DRIVER_KMS_LEGACY_CONTEXT
> #endif
>@@ -1130,10 +1130,7 @@
> 
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_export = drm_gem_prime_export,
>-	.gem_prime_import = drm_gem_prime_import,
> 	.gem_prime_pin = nouveau_gem_prime_pin,
>-	.gem_prime_res_obj = nouveau_gem_prime_res_obj,
> 	.gem_prime_unpin = nouveau_gem_prime_unpin,
> 	.gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
> 	.gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_fence.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_fence.c
>--- linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_fence.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_fence.c	2019-08-31 15:01:12.049736185 -0500
>@@ -335,7 +335,7 @@
> {
> 	struct nouveau_fence_chan *fctx = chan->fence;
> 	struct dma_fence *fence;
>-	struct reservation_object *resv = nvbo->bo.resv;
>+	struct reservation_object *resv = nvbo->bo.base.resv;
> 	struct reservation_object_list *fobj;
> 	struct nouveau_fence *f;
> 	int ret = 0, i;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_gem.c	2019-08-31 15:01:12.049736185 -0500
>@@ -205,13 +205,13 @@
> 
> 	/* Initialize the embedded gem-object. We return a single gem-reference
> 	 * to the caller, instead of a normal nouveau_bo ttm reference. */
>-	ret = drm_gem_object_init(drm->dev, &nvbo->gem, nvbo->bo.mem.size);
>+	ret = drm_gem_object_init(drm->dev, &nvbo->bo.base, nvbo->bo.mem.size);
> 	if (ret) {
> 		nouveau_bo_ref(NULL, pnvbo);
> 		return -ENOMEM;
> 	}
> 
>-	nvbo->bo.persistent_swap_storage = nvbo->gem.filp;
>+	nvbo->bo.persistent_swap_storage = nvbo->bo.base.filp;
> 	return 0;
> }
> 
>@@ -240,7 +240,7 @@
> 	}
> 
> 	rep->size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
>-	rep->map_handle = drm_vma_node_offset_addr(&nvbo->bo.vma_node);
>+	rep->map_handle = drm_vma_node_offset_addr(&nvbo->bo.base.vma_node);
> 	rep->tile_mode = nvbo->mode;
> 	rep->tile_flags = nvbo->contig ? 0 : NOUVEAU_GEM_TILE_NONCONTIG;
> 	if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI)
>@@ -268,15 +268,16 @@
> 	if (ret)
> 		return ret;
> 
>-	ret = drm_gem_handle_create(file_priv, &nvbo->gem, &req->info.handle);
>+	ret = drm_gem_handle_create(file_priv, &nvbo->bo.base,
>+				    &req->info.handle);
> 	if (ret == 0) {
>-		ret = nouveau_gem_info(file_priv, &nvbo->gem, &req->info);
>+		ret = nouveau_gem_info(file_priv, &nvbo->bo.base, &req->info);
> 		if (ret)
> 			drm_gem_handle_delete(file_priv, req->info.handle);
> 	}
> 
> 	/* drop reference from allocate - handle holds it now */
>-	drm_gem_object_put_unlocked(&nvbo->gem);
>+	drm_gem_object_put_unlocked(&nvbo->bo.base);
> 	return ret;
> }
> 
>@@ -355,7 +356,7 @@
> 		list_del(&nvbo->entry);
> 		nvbo->reserved_by = NULL;
> 		ttm_bo_unreserve(&nvbo->bo);
>-		drm_gem_object_put_unlocked(&nvbo->gem);
>+		drm_gem_object_put_unlocked(&nvbo->bo.base);
> 	}
> }
> 
>@@ -493,7 +494,7 @@
> 	list_for_each_entry(nvbo, list, entry) {
> 		struct drm_nouveau_gem_pushbuf_bo *b = &pbbo[nvbo->pbbo_index];
> 
>-		ret = nouveau_gem_set_domain(&nvbo->gem, b->read_domains,
>+		ret = nouveau_gem_set_domain(&nvbo->bo.base, b->read_domains,
> 					     b->write_domains,
> 					     b->valid_domains);
> 		if (unlikely(ret)) {
>@@ -886,7 +887,7 @@
> 		return -ENOENT;
> 	nvbo = nouveau_gem_object(gem);
> 
>-	lret = reservation_object_wait_timeout_rcu(nvbo->bo.resv, write, true,
>+	lret = reservation_object_wait_timeout_rcu(nvbo->bo.base.resv, write, true,
> 						   no_wait ? 0 : 30 * HZ);
> 	if (!lret)
> 		ret = -EBUSY;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_gem.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_gem.h
>--- linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_gem.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_gem.h	2019-08-31 15:01:12.049736185 -0500
>@@ -10,7 +10,7 @@
> static inline struct nouveau_bo *
> nouveau_gem_object(struct drm_gem_object *gem)
> {
>-	return gem ? container_of(gem, struct nouveau_bo, gem) : NULL;
>+	return gem ? container_of(gem, struct nouveau_bo, bo.base) : NULL;
> }
> 
> /* nouveau_gem.c */
>@@ -33,7 +33,6 @@
> 				  struct drm_file *);
> 
> extern int nouveau_gem_prime_pin(struct drm_gem_object *);
>-struct reservation_object *nouveau_gem_prime_res_obj(struct drm_gem_object *);
> extern void nouveau_gem_prime_unpin(struct drm_gem_object *);
> extern struct sg_table *nouveau_gem_prime_get_sg_table(struct drm_gem_object *);
> extern struct drm_gem_object *nouveau_gem_prime_import_sg_table(
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_prime.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_prime.c
>--- linux-5.3-rc6/drivers/gpu/drm/nouveau/nouveau_prime.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/nouveau/nouveau_prime.c	2019-08-31 15:01:12.049736185 -0500
>@@ -68,10 +68,10 @@
> 
> 	flags = TTM_PL_FLAG_TT;
> 
>-	ww_mutex_lock(&robj->lock, NULL);
>+	reservation_object_lock(robj, NULL);
> 	ret = nouveau_bo_new(&drm->client, attach->dmabuf->size, 0, flags, 0, 0,
> 			     sg, robj, &nvbo);
>-	ww_mutex_unlock(&robj->lock);
>+	reservation_object_unlock(robj);
> 	if (ret)
> 		return ERR_PTR(ret);
> 
>@@ -79,13 +79,13 @@
> 
> 	/* Initialize the embedded gem-object. We return a single gem-reference
> 	 * to the caller, instead of a normal nouveau_bo ttm reference. */
>-	ret = drm_gem_object_init(dev, &nvbo->gem, nvbo->bo.mem.size);
>+	ret = drm_gem_object_init(dev, &nvbo->bo.base, nvbo->bo.mem.size);
> 	if (ret) {
> 		nouveau_bo_ref(NULL, &nvbo);
> 		return ERR_PTR(-ENOMEM);
> 	}
> 
>-	return &nvbo->gem;
>+	return &nvbo->bo.base;
> }
> 
> int nouveau_gem_prime_pin(struct drm_gem_object *obj)
>@@ -107,10 +107,3 @@
> 
> 	nouveau_bo_unpin(nvbo);
> }
>-
>-struct reservation_object *nouveau_gem_prime_res_obj(struct drm_gem_object *obj)
>-{
>-	struct nouveau_bo *nvbo = nouveau_gem_object(obj);
>-
>-	return nvbo->bo.resv;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_crtc.c	2019-08-31 15:01:12.049736185 -0500
>@@ -4,12 +4,14 @@
>  * Author: Rob Clark <rob@ti.com>
>  */
> 
>+#include <linux/math64.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_mode.h>
> #include <drm/drm_plane_helper.h>
>-#include <linux/math64.h>
>+#include <drm/drm_vblank.h>
> 
> #include "omap_drv.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_debugfs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_debugfs.c
>--- linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_debugfs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_debugfs.c	2019-08-31 15:01:12.049736185 -0500
>@@ -7,6 +7,8 @@
> #include <linux/seq_file.h>
> 
> #include <drm/drm_crtc.h>
>+#include <drm/drm_debugfs.h>
>+#include <drm/drm_file.h>
> #include <drm/drm_fb_helper.h>
> 
> #include "omap_drv.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_drv.c	2019-08-31 15:01:12.236736202 -0500
>@@ -4,15 +4,21 @@
>  * Author: Rob Clark <rob@ti.com>
>  */
> 
>-#include <linux/of.h>
>+#include <linux/dma-mapping.h>
>+#include <linux/platform_device.h>
> #include <linux/sort.h>
> #include <linux/sys_soc.h>
> 
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_helper.h>
>-#include <drm/drm_probe_helper.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_ioctl.h>
> #include <drm/drm_panel.h>
>+#include <drm/drm_prime.h>
>+#include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "omap_dmm_tiler.h"
> #include "omap_drv.h"
>@@ -466,19 +472,19 @@
> 
> static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
> 	DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, drm_invalid_op,
> 			  DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
> 	DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	/* Deprecated, to be removed. */
> 	DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	/* Deprecated, to be removed. */
> 	DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> };
> 
> /*
>@@ -513,7 +519,7 @@
> };
> 
> static struct drm_driver omap_drm_driver = {
>-	.driver_features = DRIVER_MODESET | DRIVER_GEM  | DRIVER_PRIME |
>+	.driver_features = DRIVER_MODESET | DRIVER_GEM  |
> 		DRIVER_ATOMIC | DRIVER_RENDER,
> 	.open = dev_open,
> 	.lastclose = drm_fb_helper_lastclose,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_drv.h	2019-08-31 15:01:12.050736185 -0500
>@@ -11,12 +11,11 @@
> #include <linux/types.h>
> #include <linux/workqueue.h>
> 
>-#include <drm/drmP.h>
>+#include "dss/omapdss.h"
>+
> #include <drm/drm_gem.h>
> #include <drm/omap_drm.h>
> 
>-#include "dss/omapdss.h"
>-
> #include "omap_connector.h"
> #include "omap_crtc.h"
> #include "omap_encoder.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_fb.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_fb.c
>--- linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_fb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_fb.c	2019-08-31 15:01:12.050736185 -0500
>@@ -4,10 +4,10 @@
>  * Author: Rob Clark <rob@ti.com>
>  */
> 
>-#include <linux/seq_file.h>
>+#include <linux/dma-mapping.h>
> 
>-#include <drm/drm_crtc.h>
> #include <drm/drm_modeset_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_framebuffer_helper.h>
> 
> #include "omap_dmm_tiler.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_fbdev.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_fbdev.c
>--- linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_fbdev.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_fbdev.c	2019-08-31 15:01:12.050736185 -0500
>@@ -7,6 +7,8 @@
> #include <drm/drm_crtc.h>
> #include <drm/drm_util.h>
> #include <drm/drm_fb_helper.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_fourcc.h>
> 
> #include "omap_drv.h"
> 
>@@ -76,8 +78,6 @@
> 	.fb_setcmap	= drm_fb_helper_setcmap,
> 	.fb_blank	= drm_fb_helper_blank,
> 	.fb_pan_display = omap_fbdev_pan_display,
>-	.fb_debug_enter = drm_fb_helper_debug_enter,
>-	.fb_debug_leave = drm_fb_helper_debug_leave,
> 	.fb_ioctl	= drm_fb_helper_ioctl,
> 
> 	.fb_read = drm_fb_helper_sys_read,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_gem.c	2019-08-31 15:01:12.050736185 -0500
>@@ -4,11 +4,13 @@
>  * Author: Rob Clark <rob.clark@linaro.org>
>  */
> 
>+#include <linux/dma-mapping.h>
> #include <linux/seq_file.h>
> #include <linux/shmem_fs.h>
> #include <linux/spinlock.h>
> #include <linux/pfn_t.h>
> 
>+#include <drm/drm_prime.h>
> #include <drm/drm_vma_manager.h>
> 
> #include "omap_drv.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c
>--- linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c	2019-08-31 15:01:12.050736185 -0500
>@@ -5,6 +5,9 @@
>  */
> 
> #include <linux/dma-buf.h>
>+#include <linux/highmem.h>
>+
>+#include <drm/drm_prime.h>
> 
> #include "omap_drv.h"
> 
>@@ -125,8 +128,7 @@
> 	.mmap = omap_gem_dmabuf_mmap,
> };
> 
>-struct dma_buf *omap_gem_prime_export(struct drm_device *dev,
>-		struct drm_gem_object *obj, int flags)
>+struct dma_buf *omap_gem_prime_export(struct drm_gem_object *obj, int flags)
> {
> 	DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
> 
>@@ -135,7 +137,7 @@
> 	exp_info.flags = flags;
> 	exp_info.priv = obj;
> 
>-	return drm_gem_dmabuf_export(dev, &exp_info);
>+	return drm_gem_dmabuf_export(obj->dev, &exp_info);
> }
> 
> /* -----------------------------------------------------------------------------
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_gem.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_gem.h
>--- linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_gem.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_gem.h	2019-08-31 15:01:12.050736185 -0500
>@@ -65,8 +65,7 @@
> size_t omap_gem_mmap_size(struct drm_gem_object *obj);
> 
> /* PRIME Interface */
>-struct dma_buf *omap_gem_prime_export(struct drm_device *dev,
>-		struct drm_gem_object *obj, int flags);
>+struct dma_buf *omap_gem_prime_export(struct drm_gem_object *obj, int flags);
> struct drm_gem_object *omap_gem_prime_import(struct drm_device *dev,
> 		struct dma_buf *buffer);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_irq.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_irq.c
>--- linux-5.3-rc6/drivers/gpu/drm/omapdrm/omap_irq.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/omapdrm/omap_irq.c	2019-08-31 15:01:12.050736185 -0500
>@@ -4,6 +4,8 @@
>  * Author: Rob Clark <rob.clark@linaro.org>
>  */
> 
>+#include <drm/drm_vblank.h>
>+
> #include "omap_drv.h"
> 
> struct omap_irq_wait {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panel/Kconfig linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/Kconfig
>--- linux-5.3-rc6/drivers/gpu/drm/panel/Kconfig	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/Kconfig	2019-08-31 15:01:12.050736185 -0500
>@@ -111,6 +111,15 @@
> 	  Say Y here if you want to enable support for LG4573 RGB panel.
> 	  To compile this driver as a module, choose M here.
> 
>+config DRM_PANEL_NOVATEK_NT39016
>+	tristate "Novatek NT39016 RGB/SPI panel"
>+	depends on OF && SPI
>+	depends on BACKLIGHT_CLASS_DEVICE
>+	select REGMAP_SPI
>+	help
>+	  Say Y here if you want to enable support for the panels built
>+	  around the Novatek NT39016 display controller.
>+
> config DRM_PANEL_OLIMEX_LCD_OLINUXINO
> 	tristate "Olimex LCD-OLinuXino panel"
> 	depends on OF
>@@ -159,6 +168,15 @@
> 	  Pi 7" Touchscreen.  To compile this driver as a module,
> 	  choose M here.
> 
>+config DRM_PANEL_RAYDIUM_RM67191
>+	tristate "Raydium RM67191 FHD 1080x1920 DSI video mode panel"
>+	depends on OF
>+	depends on DRM_MIPI_DSI
>+	depends on BACKLIGHT_CLASS_DEVICE
>+	help
>+	  Say Y here if you want to enable support for Raydium RM67191 FHD
>+	  (1080x1920) DSI panel.
>+
> config DRM_PANEL_RAYDIUM_RM68200
> 	tristate "Raydium RM68200 720x1280 DSI video mode panel"
> 	depends on OF
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panel/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/panel/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/Makefile	2019-08-31 15:01:12.050736185 -0500
>@@ -9,11 +9,13 @@
> obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
> obj-$(CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04) += panel-kingdisplay-kd097d04.o
> obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o
>+obj-$(CONFIG_DRM_PANEL_NOVATEK_NT39016) += panel-novatek-nt39016.o
> obj-$(CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO) += panel-olimex-lcd-olinuxino.o
> obj-$(CONFIG_DRM_PANEL_ORISETECH_OTM8009A) += panel-orisetech-otm8009a.o
> obj-$(CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS) += panel-osd-osd101t2587-53ts.o
> obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += panel-panasonic-vvx10f034n00.o
> obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) += panel-raspberrypi-touchscreen.o
>+obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM67191) += panel-raydium-rm67191.o
> obj-$(CONFIG_DRM_PANEL_RAYDIUM_RM68200) += panel-raydium-rm68200.o
> obj-$(CONFIG_DRM_PANEL_ROCKTECH_JH057N00900) += panel-rocktech-jh057n00900.o
> obj-$(CONFIG_DRM_PANEL_RONBO_RB070D30) += panel-ronbo-rb070d30.o
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panel/panel-lvds.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/panel-lvds.c
>--- linux-5.3-rc6/drivers/gpu/drm/panel/panel-lvds.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/panel-lvds.c	2019-08-31 15:01:12.050736185 -0500
>@@ -147,8 +147,11 @@
> 	int ret;
> 
> 	ret = of_get_display_timing(np, "panel-timing", &timing);
>-	if (ret < 0)
>+	if (ret < 0) {
>+		dev_err(lvds->dev, "%pOF: problems parsing panel-timing (%d)\n",
>+			np, ret);
> 		return ret;
>+	}
> 
> 	videomode_from_timing(&timing, &lvds->video_mode);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panel/panel-novatek-nt39016.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/panel-novatek-nt39016.c
>--- linux-5.3-rc6/drivers/gpu/drm/panel/panel-novatek-nt39016.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/panel-novatek-nt39016.c	2019-08-31 15:01:12.050736185 -0500
>@@ -0,0 +1,359 @@
>+// SPDX-License-Identifier: GPL-2.0
>+/*
>+ * Novatek NT39016 TFT LCD panel driver
>+ *
>+ * Copyright (C) 2017, Maarten ter Huurne <maarten@treewalker.org>
>+ * Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net>
>+ */
>+
>+#include <linux/backlight.h>
>+#include <linux/delay.h>
>+#include <linux/device.h>
>+#include <linux/gpio/consumer.h>
>+#include <linux/media-bus-format.h>
>+#include <linux/module.h>
>+#include <linux/of.h>
>+#include <linux/of_device.h>
>+#include <linux/regmap.h>
>+#include <linux/regulator/consumer.h>
>+#include <linux/spi/spi.h>
>+
>+#include <drm/drm_modes.h>
>+#include <drm/drm_panel.h>
>+
>+enum nt39016_regs {
>+	NT39016_REG_SYSTEM,
>+	NT39016_REG_TIMING,
>+	NT39016_REG_OP,
>+	NT39016_REG_DATA_IN,
>+	NT39016_REG_SRC_TIMING_DELAY,
>+	NT39016_REG_GATE_TIMING_DELAY,
>+	NT39016_REG_RESERVED,
>+	NT39016_REG_INITIAL_FUNC,
>+	NT39016_REG_CONTRAST,
>+	NT39016_REG_BRIGHTNESS,
>+	NT39016_REG_HUE_SATURATION,
>+	NT39016_REG_RB_SUBCONTRAST,
>+	NT39016_REG_R_SUBBRIGHTNESS,
>+	NT39016_REG_B_SUBBRIGHTNESS,
>+	NT39016_REG_VCOMDC,
>+	NT39016_REG_VCOMAC,
>+	NT39016_REG_VGAM2,
>+	NT39016_REG_VGAM34,
>+	NT39016_REG_VGAM56,
>+	NT39016_REG_VCOMDC_TRIM = 0x1e,
>+	NT39016_REG_DISPLAY_MODE = 0x20,
>+};
>+
>+#define NT39016_SYSTEM_RESET_N	BIT(0)
>+#define NT39016_SYSTEM_STANDBY	BIT(1)
>+
>+struct nt39016_panel_info {
>+	struct drm_display_mode display_mode;
>+	u16 width_mm, height_mm;
>+	u32 bus_format, bus_flags;
>+};
>+
>+struct nt39016 {
>+	struct drm_panel drm_panel;
>+	struct device *dev;
>+	struct regmap *map;
>+	struct regulator *supply;
>+	const struct nt39016_panel_info *panel_info;
>+
>+	struct gpio_desc *reset_gpio;
>+
>+	struct backlight_device *backlight;
>+};
>+
>+static inline struct nt39016 *to_nt39016(struct drm_panel *panel)
>+{
>+	return container_of(panel, struct nt39016, drm_panel);
>+}
>+
>+#define RV(REG, VAL) { .reg = (REG), .def = (VAL), .delay_us = 2 }
>+static const struct reg_sequence nt39016_panel_regs[] = {
>+	RV(NT39016_REG_SYSTEM, 0x00),
>+	RV(NT39016_REG_TIMING, 0x00),
>+	RV(NT39016_REG_OP, 0x03),
>+	RV(NT39016_REG_DATA_IN, 0xCC),
>+	RV(NT39016_REG_SRC_TIMING_DELAY, 0x46),
>+	RV(NT39016_REG_GATE_TIMING_DELAY, 0x05),
>+	RV(NT39016_REG_RESERVED, 0x00),
>+	RV(NT39016_REG_INITIAL_FUNC, 0x00),
>+	RV(NT39016_REG_CONTRAST, 0x08),
>+	RV(NT39016_REG_BRIGHTNESS, 0x40),
>+	RV(NT39016_REG_HUE_SATURATION, 0x88),
>+	RV(NT39016_REG_RB_SUBCONTRAST, 0x88),
>+	RV(NT39016_REG_R_SUBBRIGHTNESS, 0x20),
>+	RV(NT39016_REG_B_SUBBRIGHTNESS, 0x20),
>+	RV(NT39016_REG_VCOMDC, 0x67),
>+	RV(NT39016_REG_VCOMAC, 0xA4),
>+	RV(NT39016_REG_VGAM2, 0x04),
>+	RV(NT39016_REG_VGAM34, 0x24),
>+	RV(NT39016_REG_VGAM56, 0x24),
>+	RV(NT39016_REG_DISPLAY_MODE, 0x00),
>+};
>+
>+#undef RV
>+
>+static const struct regmap_range nt39016_regmap_no_ranges[] = {
>+	regmap_reg_range(0x13, 0x1D),
>+	regmap_reg_range(0x1F, 0x1F),
>+};
>+
>+static const struct regmap_access_table nt39016_regmap_access_table = {
>+	.no_ranges = nt39016_regmap_no_ranges,
>+	.n_no_ranges = ARRAY_SIZE(nt39016_regmap_no_ranges),
>+};
>+
>+static const struct regmap_config nt39016_regmap_config = {
>+	.reg_bits = 6,
>+	.pad_bits = 2,
>+	.val_bits = 8,
>+
>+	.max_register = NT39016_REG_DISPLAY_MODE,
>+	.wr_table = &nt39016_regmap_access_table,
>+	.write_flag_mask = 0x02,
>+
>+	.cache_type = REGCACHE_FLAT,
>+};
>+
>+static int nt39016_prepare(struct drm_panel *drm_panel)
>+{
>+	struct nt39016 *panel = to_nt39016(drm_panel);
>+	int err;
>+
>+	err = regulator_enable(panel->supply);
>+	if (err) {
>+		dev_err(panel->dev, "Failed to enable power supply: %d", err);
>+		return err;
>+	}
>+
>+	/*
>+	 * Reset the NT39016.
>+	 * The documentation says the reset pulse should be at least 40 us to
>+	 * pass the glitch filter, but when testing I see some resets fail and
>+	 * some succeed when using a 70 us delay, so we use 100 us instead.
>+	 */
>+	gpiod_set_value_cansleep(panel->reset_gpio, 1);
>+	usleep_range(100, 1000);
>+	gpiod_set_value_cansleep(panel->reset_gpio, 0);
>+	udelay(2);
>+
>+	/* Init all registers. */
>+	err = regmap_multi_reg_write(panel->map, nt39016_panel_regs,
>+				     ARRAY_SIZE(nt39016_panel_regs));
>+	if (err) {
>+		dev_err(panel->dev, "Failed to init registers: %d", err);
>+		goto err_disable_regulator;
>+	}
>+
>+	return 0;
>+
>+err_disable_regulator:
>+	regulator_disable(panel->supply);
>+	return err;
>+}
>+
>+static int nt39016_unprepare(struct drm_panel *drm_panel)
>+{
>+	struct nt39016 *panel = to_nt39016(drm_panel);
>+
>+	gpiod_set_value_cansleep(panel->reset_gpio, 1);
>+
>+	regulator_disable(panel->supply);
>+
>+	return 0;
>+}
>+
>+static int nt39016_enable(struct drm_panel *drm_panel)
>+{
>+	struct nt39016 *panel = to_nt39016(drm_panel);
>+	int ret;
>+
>+	ret = regmap_write(panel->map, NT39016_REG_SYSTEM,
>+			   NT39016_SYSTEM_RESET_N | NT39016_SYSTEM_STANDBY);
>+	if (ret) {
>+		dev_err(panel->dev, "Unable to enable panel: %d", ret);
>+		return ret;
>+	}
>+
>+	if (panel->backlight) {
>+		/* Wait for the picture to be ready before enabling backlight */
>+		msleep(150);
>+
>+		ret = backlight_enable(panel->backlight);
>+	}
>+
>+	return ret;
>+}
>+
>+static int nt39016_disable(struct drm_panel *drm_panel)
>+{
>+	struct nt39016 *panel = to_nt39016(drm_panel);
>+	int err;
>+
>+	backlight_disable(panel->backlight);
>+
>+	err = regmap_write(panel->map, NT39016_REG_SYSTEM,
>+			   NT39016_SYSTEM_RESET_N);
>+	if (err) {
>+		dev_err(panel->dev, "Unable to disable panel: %d", err);
>+		return err;
>+	}
>+
>+	return 0;
>+}
>+
>+static int nt39016_get_modes(struct drm_panel *drm_panel)
>+{
>+	struct nt39016 *panel = to_nt39016(drm_panel);
>+	const struct nt39016_panel_info *panel_info = panel->panel_info;
>+	struct drm_connector *connector = drm_panel->connector;
>+	struct drm_display_mode *mode;
>+
>+	mode = drm_mode_duplicate(drm_panel->drm, &panel_info->display_mode);
>+	if (!mode)
>+		return -ENOMEM;
>+
>+	drm_mode_set_name(mode);
>+
>+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
>+	drm_mode_probed_add(connector, mode);
>+
>+	connector->display_info.bpc = 8;
>+	connector->display_info.width_mm = panel_info->width_mm;
>+	connector->display_info.height_mm = panel_info->height_mm;
>+
>+	drm_display_info_set_bus_formats(&connector->display_info,
>+					 &panel_info->bus_format, 1);
>+	connector->display_info.bus_flags = panel_info->bus_flags;
>+
>+	return 1;
>+}
>+
>+static const struct drm_panel_funcs nt39016_funcs = {
>+	.prepare	= nt39016_prepare,
>+	.unprepare	= nt39016_unprepare,
>+	.enable		= nt39016_enable,
>+	.disable	= nt39016_disable,
>+	.get_modes	= nt39016_get_modes,
>+};
>+
>+static int nt39016_probe(struct spi_device *spi)
>+{
>+	struct device *dev = &spi->dev;
>+	struct nt39016 *panel;
>+	int err;
>+
>+	panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
>+	if (!panel)
>+		return -ENOMEM;
>+
>+	panel->dev = dev;
>+	spi_set_drvdata(spi, panel);
>+
>+	panel->panel_info = of_device_get_match_data(dev);
>+	if (!panel->panel_info)
>+		return -EINVAL;
>+
>+	panel->supply = devm_regulator_get(dev, "power");
>+	if (IS_ERR(panel->supply)) {
>+		dev_err(dev, "Failed to get power supply");
>+		return PTR_ERR(panel->supply);
>+	}
>+
>+	panel->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
>+	if (IS_ERR(panel->reset_gpio)) {
>+		dev_err(dev, "Failed to get reset GPIO");
>+		return PTR_ERR(panel->reset_gpio);
>+	}
>+
>+	spi->bits_per_word = 8;
>+	spi->mode = SPI_MODE_3 | SPI_3WIRE;
>+	err = spi_setup(spi);
>+	if (err) {
>+		dev_err(dev, "Failed to setup SPI");
>+		return err;
>+	}
>+
>+	panel->map = devm_regmap_init_spi(spi, &nt39016_regmap_config);
>+	if (IS_ERR(panel->map)) {
>+		dev_err(dev, "Failed to init regmap");
>+		return PTR_ERR(panel->map);
>+	}
>+
>+	panel->backlight = devm_of_find_backlight(dev);
>+	if (IS_ERR(panel->backlight)) {
>+		err = PTR_ERR(panel->backlight);
>+		if (err != -EPROBE_DEFER)
>+			dev_err(dev, "Failed to get backlight handle");
>+		return err;
>+	}
>+
>+	drm_panel_init(&panel->drm_panel);
>+	panel->drm_panel.dev = dev;
>+	panel->drm_panel.funcs = &nt39016_funcs;
>+
>+	err = drm_panel_add(&panel->drm_panel);
>+	if (err < 0) {
>+		dev_err(dev, "Failed to register panel");
>+		return err;
>+	}
>+
>+	return 0;
>+}
>+
>+static int nt39016_remove(struct spi_device *spi)
>+{
>+	struct nt39016 *panel = spi_get_drvdata(spi);
>+
>+	drm_panel_remove(&panel->drm_panel);
>+
>+	nt39016_disable(&panel->drm_panel);
>+	nt39016_unprepare(&panel->drm_panel);
>+
>+	return 0;
>+}
>+
>+static const struct nt39016_panel_info kd035g6_info = {
>+	.display_mode = {
>+		.clock = 6000,
>+		.hdisplay = 320,
>+		.hsync_start = 320 + 10,
>+		.hsync_end = 320 + 10 + 50,
>+		.htotal = 320 + 10 + 50 + 20,
>+		.vdisplay = 240,
>+		.vsync_start = 240 + 5,
>+		.vsync_end = 240 + 5 + 1,
>+		.vtotal = 240 + 5 + 1 + 4,
>+		.vrefresh = 60,
>+		.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
>+	},
>+	.width_mm = 71,
>+	.height_mm = 53,
>+	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
>+	.bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
>+};
>+
>+static const struct of_device_id nt39016_of_match[] = {
>+	{ .compatible = "kingdisplay,kd035g6-54nt", .data = &kd035g6_info },
>+	{ /* sentinel */ }
>+};
>+MODULE_DEVICE_TABLE(of, nt39016_of_match);
>+
>+static struct spi_driver nt39016_driver = {
>+	.driver = {
>+		.name = "nt39016",
>+		.of_match_table = nt39016_of_match,
>+	},
>+	.probe = nt39016_probe,
>+	.remove = nt39016_remove,
>+};
>+
>+module_spi_driver(nt39016_driver);
>+
>+MODULE_AUTHOR("Maarten ter Huurne <maarten@treewalker.org>");
>+MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
>+MODULE_LICENSE("GPL v2");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c
>--- linux-5.3-rc6/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c	2019-08-31 15:01:12.050736185 -0500
>@@ -399,7 +399,13 @@
> 
> 	/* Look up the DSI host.  It needs to probe before we do. */
> 	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
>+	if (!endpoint)
>+		return -ENODEV;
>+
> 	dsi_host_node = of_graph_get_remote_port_parent(endpoint);
>+	if (!dsi_host_node)
>+		goto error;
>+
> 	host = of_find_mipi_dsi_host_by_node(dsi_host_node);
> 	of_node_put(dsi_host_node);
> 	if (!host) {
>@@ -408,6 +414,9 @@
> 	}
> 
> 	info.node = of_graph_get_remote_port(endpoint);
>+	if (!info.node)
>+		goto error;
>+
> 	of_node_put(endpoint);
> 
> 	ts->dsi = mipi_dsi_device_register_full(host, &info);
>@@ -428,6 +437,10 @@
> 		return ret;
> 
> 	return 0;
>+
>+error:
>+	of_node_put(endpoint);
>+	return -ENODEV;
> }
> 
> static int rpi_touchscreen_remove(struct i2c_client *i2c)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panel/panel-raydium-rm67191.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/panel-raydium-rm67191.c
>--- linux-5.3-rc6/drivers/gpu/drm/panel/panel-raydium-rm67191.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/panel-raydium-rm67191.c	2019-08-31 15:01:12.050736185 -0500
>@@ -0,0 +1,668 @@
>+// SPDX-License-Identifier: GPL-2.0
>+/*
>+ * Raydium RM67191 MIPI-DSI panel driver
>+ *
>+ * Copyright 2019 NXP
>+ */
>+
>+#include <linux/backlight.h>
>+#include <linux/delay.h>
>+#include <linux/gpio/consumer.h>
>+#include <linux/module.h>
>+#include <linux/of.h>
>+#include <linux/regulator/consumer.h>
>+
>+#include <video/mipi_display.h>
>+#include <video/of_videomode.h>
>+#include <video/videomode.h>
>+
>+#include <drm/drm_crtc.h>
>+#include <drm/drm_mipi_dsi.h>
>+#include <drm/drm_panel.h>
>+#include <drm/drm_print.h>
>+
>+/* Panel specific color-format bits */
>+#define COL_FMT_16BPP 0x55
>+#define COL_FMT_18BPP 0x66
>+#define COL_FMT_24BPP 0x77
>+
>+/* Write Manufacture Command Set Control */
>+#define WRMAUCCTR 0xFE
>+
>+/* Manufacturer Command Set pages (CMD2) */
>+struct cmd_set_entry {
>+	u8 cmd;
>+	u8 param;
>+};
>+
>+/*
>+ * There is no description in the Reference Manual about these commands.
>+ * We received them from vendor, so just use them as is.
>+ */
>+static const struct cmd_set_entry manufacturer_cmd_set[] = {
>+	{0xFE, 0x0B},
>+	{0x28, 0x40},
>+	{0x29, 0x4F},
>+	{0xFE, 0x0E},
>+	{0x4B, 0x00},
>+	{0x4C, 0x0F},
>+	{0x4D, 0x20},
>+	{0x4E, 0x40},
>+	{0x4F, 0x60},
>+	{0x50, 0xA0},
>+	{0x51, 0xC0},
>+	{0x52, 0xE0},
>+	{0x53, 0xFF},
>+	{0xFE, 0x0D},
>+	{0x18, 0x08},
>+	{0x42, 0x00},
>+	{0x08, 0x41},
>+	{0x46, 0x02},
>+	{0x72, 0x09},
>+	{0xFE, 0x0A},
>+	{0x24, 0x17},
>+	{0x04, 0x07},
>+	{0x1A, 0x0C},
>+	{0x0F, 0x44},
>+	{0xFE, 0x04},
>+	{0x00, 0x0C},
>+	{0x05, 0x08},
>+	{0x06, 0x08},
>+	{0x08, 0x08},
>+	{0x09, 0x08},
>+	{0x0A, 0xE6},
>+	{0x0B, 0x8C},
>+	{0x1A, 0x12},
>+	{0x1E, 0xE0},
>+	{0x29, 0x93},
>+	{0x2A, 0x93},
>+	{0x2F, 0x02},
>+	{0x31, 0x02},
>+	{0x33, 0x05},
>+	{0x37, 0x2D},
>+	{0x38, 0x2D},
>+	{0x3A, 0x1E},
>+	{0x3B, 0x1E},
>+	{0x3D, 0x27},
>+	{0x3F, 0x80},
>+	{0x40, 0x40},
>+	{0x41, 0xE0},
>+	{0x4F, 0x2F},
>+	{0x50, 0x1E},
>+	{0xFE, 0x06},
>+	{0x00, 0xCC},
>+	{0x05, 0x05},
>+	{0x07, 0xA2},
>+	{0x08, 0xCC},
>+	{0x0D, 0x03},
>+	{0x0F, 0xA2},
>+	{0x32, 0xCC},
>+	{0x37, 0x05},
>+	{0x39, 0x83},
>+	{0x3A, 0xCC},
>+	{0x41, 0x04},
>+	{0x43, 0x83},
>+	{0x44, 0xCC},
>+	{0x49, 0x05},
>+	{0x4B, 0xA2},
>+	{0x4C, 0xCC},
>+	{0x51, 0x03},
>+	{0x53, 0xA2},
>+	{0x75, 0xCC},
>+	{0x7A, 0x03},
>+	{0x7C, 0x83},
>+	{0x7D, 0xCC},
>+	{0x82, 0x02},
>+	{0x84, 0x83},
>+	{0x85, 0xEC},
>+	{0x86, 0x0F},
>+	{0x87, 0xFF},
>+	{0x88, 0x00},
>+	{0x8A, 0x02},
>+	{0x8C, 0xA2},
>+	{0x8D, 0xEA},
>+	{0x8E, 0x01},
>+	{0x8F, 0xE8},
>+	{0xFE, 0x06},
>+	{0x90, 0x0A},
>+	{0x92, 0x06},
>+	{0x93, 0xA0},
>+	{0x94, 0xA8},
>+	{0x95, 0xEC},
>+	{0x96, 0x0F},
>+	{0x97, 0xFF},
>+	{0x98, 0x00},
>+	{0x9A, 0x02},
>+	{0x9C, 0xA2},
>+	{0xAC, 0x04},
>+	{0xFE, 0x06},
>+	{0xB1, 0x12},
>+	{0xB2, 0x17},
>+	{0xB3, 0x17},
>+	{0xB4, 0x17},
>+	{0xB5, 0x17},
>+	{0xB6, 0x11},
>+	{0xB7, 0x08},
>+	{0xB8, 0x09},
>+	{0xB9, 0x06},
>+	{0xBA, 0x07},
>+	{0xBB, 0x17},
>+	{0xBC, 0x17},
>+	{0xBD, 0x17},
>+	{0xBE, 0x17},
>+	{0xBF, 0x17},
>+	{0xC0, 0x17},
>+	{0xC1, 0x17},
>+	{0xC2, 0x17},
>+	{0xC3, 0x17},
>+	{0xC4, 0x0F},
>+	{0xC5, 0x0E},
>+	{0xC6, 0x00},
>+	{0xC7, 0x01},
>+	{0xC8, 0x10},
>+	{0xFE, 0x06},
>+	{0x95, 0xEC},
>+	{0x8D, 0xEE},
>+	{0x44, 0xEC},
>+	{0x4C, 0xEC},
>+	{0x32, 0xEC},
>+	{0x3A, 0xEC},
>+	{0x7D, 0xEC},
>+	{0x75, 0xEC},
>+	{0x00, 0xEC},
>+	{0x08, 0xEC},
>+	{0x85, 0xEC},
>+	{0xA6, 0x21},
>+	{0xA7, 0x05},
>+	{0xA9, 0x06},
>+	{0x82, 0x06},
>+	{0x41, 0x06},
>+	{0x7A, 0x07},
>+	{0x37, 0x07},
>+	{0x05, 0x06},
>+	{0x49, 0x06},
>+	{0x0D, 0x04},
>+	{0x51, 0x04},
>+};
>+
>+static const u32 rad_bus_formats[] = {
>+	MEDIA_BUS_FMT_RGB888_1X24,
>+	MEDIA_BUS_FMT_RGB666_1X18,
>+	MEDIA_BUS_FMT_RGB565_1X16,
>+};
>+
>+static const u32 rad_bus_flags = DRM_BUS_FLAG_DE_LOW |
>+				 DRM_BUS_FLAG_PIXDATA_NEGEDGE;
>+
>+struct rad_panel {
>+	struct drm_panel panel;
>+	struct mipi_dsi_device *dsi;
>+
>+	struct gpio_desc *reset;
>+	struct backlight_device *backlight;
>+
>+	struct regulator_bulk_data *supplies;
>+	unsigned int num_supplies;
>+
>+	bool prepared;
>+	bool enabled;
>+};
>+
>+static const struct drm_display_mode default_mode = {
>+	.clock = 132000,
>+	.hdisplay = 1080,
>+	.hsync_start = 1080 + 20,
>+	.hsync_end = 1080 + 20 + 2,
>+	.htotal = 1080 + 20 + 2 + 34,
>+	.vdisplay = 1920,
>+	.vsync_start = 1920 + 10,
>+	.vsync_end = 1920 + 10 + 2,
>+	.vtotal = 1920 + 10 + 2 + 4,
>+	.vrefresh = 60,
>+	.width_mm = 68,
>+	.height_mm = 121,
>+	.flags = DRM_MODE_FLAG_NHSYNC |
>+		 DRM_MODE_FLAG_NVSYNC,
>+};
>+
>+static inline struct rad_panel *to_rad_panel(struct drm_panel *panel)
>+{
>+	return container_of(panel, struct rad_panel, panel);
>+}
>+
>+static int rad_panel_push_cmd_list(struct mipi_dsi_device *dsi)
>+{
>+	size_t i;
>+	size_t count = ARRAY_SIZE(manufacturer_cmd_set);
>+	int ret = 0;
>+
>+	for (i = 0; i < count; i++) {
>+		const struct cmd_set_entry *entry = &manufacturer_cmd_set[i];
>+		u8 buffer[2] = { entry->cmd, entry->param };
>+
>+		ret = mipi_dsi_generic_write(dsi, &buffer, sizeof(buffer));
>+		if (ret < 0)
>+			return ret;
>+	}
>+
>+	return ret;
>+};
>+
>+static int color_format_from_dsi_format(enum mipi_dsi_pixel_format format)
>+{
>+	switch (format) {
>+	case MIPI_DSI_FMT_RGB565:
>+		return COL_FMT_16BPP;
>+	case MIPI_DSI_FMT_RGB666:
>+	case MIPI_DSI_FMT_RGB666_PACKED:
>+		return COL_FMT_18BPP;
>+	case MIPI_DSI_FMT_RGB888:
>+		return COL_FMT_24BPP;
>+	default:
>+		return COL_FMT_24BPP; /* for backward compatibility */
>+	}
>+};
>+
>+static int rad_panel_prepare(struct drm_panel *panel)
>+{
>+	struct rad_panel *rad = to_rad_panel(panel);
>+	int ret;
>+
>+	if (rad->prepared)
>+		return 0;
>+
>+	ret = regulator_bulk_enable(rad->num_supplies, rad->supplies);
>+	if (ret)
>+		return ret;
>+
>+	if (rad->reset) {
>+		gpiod_set_value_cansleep(rad->reset, 1);
>+		usleep_range(3000, 5000);
>+		gpiod_set_value_cansleep(rad->reset, 0);
>+		usleep_range(18000, 20000);
>+	}
>+
>+	rad->prepared = true;
>+
>+	return 0;
>+}
>+
>+static int rad_panel_unprepare(struct drm_panel *panel)
>+{
>+	struct rad_panel *rad = to_rad_panel(panel);
>+	int ret;
>+
>+	if (!rad->prepared)
>+		return 0;
>+
>+	/*
>+	 * Right after asserting the reset, we need to release it, so that the
>+	 * touch driver can have an active connection with the touch controller
>+	 * even after the display is turned off.
>+	 */
>+	if (rad->reset) {
>+		gpiod_set_value_cansleep(rad->reset, 1);
>+		usleep_range(15000, 17000);
>+		gpiod_set_value_cansleep(rad->reset, 0);
>+	}
>+
>+	ret = regulator_bulk_disable(rad->num_supplies, rad->supplies);
>+	if (ret)
>+		return ret;
>+
>+	rad->prepared = false;
>+
>+	return 0;
>+}
>+
>+static int rad_panel_enable(struct drm_panel *panel)
>+{
>+	struct rad_panel *rad = to_rad_panel(panel);
>+	struct mipi_dsi_device *dsi = rad->dsi;
>+	struct device *dev = &dsi->dev;
>+	int color_format = color_format_from_dsi_format(dsi->format);
>+	int ret;
>+
>+	if (rad->enabled)
>+		return 0;
>+
>+	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
>+
>+	ret = rad_panel_push_cmd_list(dsi);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(dev, "Failed to send MCS (%d)\n", ret);
>+		goto fail;
>+	}
>+
>+	/* Select User Command Set table (CMD1) */
>+	ret = mipi_dsi_generic_write(dsi, (u8[]){ WRMAUCCTR, 0x00 }, 2);
>+	if (ret < 0)
>+		goto fail;
>+
>+	/* Software reset */
>+	ret = mipi_dsi_dcs_soft_reset(dsi);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(dev, "Failed to do Software Reset (%d)\n", ret);
>+		goto fail;
>+	}
>+
>+	usleep_range(15000, 17000);
>+
>+	/* Set DSI mode */
>+	ret = mipi_dsi_generic_write(dsi, (u8[]){ 0xC2, 0x0B }, 2);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(dev, "Failed to set DSI mode (%d)\n", ret);
>+		goto fail;
>+	}
>+	/* Set tear ON */
>+	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(dev, "Failed to set tear ON (%d)\n", ret);
>+		goto fail;
>+	}
>+	/* Set tear scanline */
>+	ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0x380);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(dev, "Failed to set tear scanline (%d)\n", ret);
>+		goto fail;
>+	}
>+	/* Set pixel format */
>+	ret = mipi_dsi_dcs_set_pixel_format(dsi, color_format);
>+	DRM_DEV_DEBUG_DRIVER(dev, "Interface color format set to 0x%x\n",
>+			     color_format);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(dev, "Failed to set pixel format (%d)\n", ret);
>+		goto fail;
>+	}
>+	/* Exit sleep mode */
>+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(dev, "Failed to exit sleep mode (%d)\n", ret);
>+		goto fail;
>+	}
>+
>+	usleep_range(5000, 7000);
>+
>+	ret = mipi_dsi_dcs_set_display_on(dsi);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(dev, "Failed to set display ON (%d)\n", ret);
>+		goto fail;
>+	}
>+
>+	backlight_enable(rad->backlight);
>+
>+	rad->enabled = true;
>+
>+	return 0;
>+
>+fail:
>+	gpiod_set_value_cansleep(rad->reset, 1);
>+
>+	return ret;
>+}
>+
>+static int rad_panel_disable(struct drm_panel *panel)
>+{
>+	struct rad_panel *rad = to_rad_panel(panel);
>+	struct mipi_dsi_device *dsi = rad->dsi;
>+	struct device *dev = &dsi->dev;
>+	int ret;
>+
>+	if (!rad->enabled)
>+		return 0;
>+
>+	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
>+
>+	backlight_disable(rad->backlight);
>+
>+	usleep_range(10000, 12000);
>+
>+	ret = mipi_dsi_dcs_set_display_off(dsi);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(dev, "Failed to set display OFF (%d)\n", ret);
>+		return ret;
>+	}
>+
>+	usleep_range(5000, 10000);
>+
>+	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(dev, "Failed to enter sleep mode (%d)\n", ret);
>+		return ret;
>+	}
>+
>+	rad->enabled = false;
>+
>+	return 0;
>+}
>+
>+static int rad_panel_get_modes(struct drm_panel *panel)
>+{
>+	struct drm_connector *connector = panel->connector;
>+	struct drm_display_mode *mode;
>+
>+	mode = drm_mode_duplicate(panel->drm, &default_mode);
>+	if (!mode) {
>+		DRM_DEV_ERROR(panel->dev, "failed to add mode %ux%ux@%u\n",
>+			      default_mode.hdisplay, default_mode.vdisplay,
>+			      default_mode.vrefresh);
>+		return -ENOMEM;
>+	}
>+
>+	drm_mode_set_name(mode);
>+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
>+	drm_mode_probed_add(panel->connector, mode);
>+
>+	connector->display_info.width_mm = mode->width_mm;
>+	connector->display_info.height_mm = mode->height_mm;
>+	connector->display_info.bus_flags = rad_bus_flags;
>+
>+	drm_display_info_set_bus_formats(&connector->display_info,
>+					 rad_bus_formats,
>+					 ARRAY_SIZE(rad_bus_formats));
>+	return 1;
>+}
>+
>+static int rad_bl_get_brightness(struct backlight_device *bl)
>+{
>+	struct mipi_dsi_device *dsi = bl_get_data(bl);
>+	struct rad_panel *rad = mipi_dsi_get_drvdata(dsi);
>+	u16 brightness;
>+	int ret;
>+
>+	if (!rad->prepared)
>+		return 0;
>+
>+	dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
>+
>+	ret = mipi_dsi_dcs_get_display_brightness(dsi, &brightness);
>+	if (ret < 0)
>+		return ret;
>+
>+	bl->props.brightness = brightness;
>+
>+	return brightness & 0xff;
>+}
>+
>+static int rad_bl_update_status(struct backlight_device *bl)
>+{
>+	struct mipi_dsi_device *dsi = bl_get_data(bl);
>+	struct rad_panel *rad = mipi_dsi_get_drvdata(dsi);
>+	int ret = 0;
>+
>+	if (!rad->prepared)
>+		return 0;
>+
>+	dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
>+
>+	ret = mipi_dsi_dcs_set_display_brightness(dsi, bl->props.brightness);
>+	if (ret < 0)
>+		return ret;
>+
>+	return 0;
>+}
>+
>+static const struct backlight_ops rad_bl_ops = {
>+	.update_status = rad_bl_update_status,
>+	.get_brightness = rad_bl_get_brightness,
>+};
>+
>+static const struct drm_panel_funcs rad_panel_funcs = {
>+	.prepare = rad_panel_prepare,
>+	.unprepare = rad_panel_unprepare,
>+	.enable = rad_panel_enable,
>+	.disable = rad_panel_disable,
>+	.get_modes = rad_panel_get_modes,
>+};
>+
>+static const char * const rad_supply_names[] = {
>+	"v3p3",
>+	"v1p8",
>+};
>+
>+static int rad_init_regulators(struct rad_panel *rad)
>+{
>+	struct device *dev = &rad->dsi->dev;
>+	int i;
>+
>+	rad->num_supplies = ARRAY_SIZE(rad_supply_names);
>+	rad->supplies = devm_kcalloc(dev, rad->num_supplies,
>+				     sizeof(*rad->supplies), GFP_KERNEL);
>+	if (!rad->supplies)
>+		return -ENOMEM;
>+
>+	for (i = 0; i < rad->num_supplies; i++)
>+		rad->supplies[i].supply = rad_supply_names[i];
>+
>+	return devm_regulator_bulk_get(dev, rad->num_supplies, rad->supplies);
>+};
>+
>+static int rad_panel_probe(struct mipi_dsi_device *dsi)
>+{
>+	struct device *dev = &dsi->dev;
>+	struct device_node *np = dev->of_node;
>+	struct rad_panel *panel;
>+	struct backlight_properties bl_props;
>+	int ret;
>+	u32 video_mode;
>+
>+	panel = devm_kzalloc(&dsi->dev, sizeof(*panel), GFP_KERNEL);
>+	if (!panel)
>+		return -ENOMEM;
>+
>+	mipi_dsi_set_drvdata(dsi, panel);
>+
>+	panel->dsi = dsi;
>+
>+	dsi->format = MIPI_DSI_FMT_RGB888;
>+	dsi->mode_flags =  MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
>+			   MIPI_DSI_CLOCK_NON_CONTINUOUS;
>+
>+	ret = of_property_read_u32(np, "video-mode", &video_mode);
>+	if (!ret) {
>+		switch (video_mode) {
>+		case 0:
>+			/* burst mode */
>+			dsi->mode_flags |= MIPI_DSI_MODE_VIDEO_BURST;
>+			break;
>+		case 1:
>+			/* non-burst mode with sync event */
>+			break;
>+		case 2:
>+			/* non-burst mode with sync pulse */
>+			dsi->mode_flags |= MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
>+			break;
>+		default:
>+			dev_warn(dev, "invalid video mode %d\n", video_mode);
>+			break;
>+		}
>+	}
>+
>+	ret = of_property_read_u32(np, "dsi-lanes", &dsi->lanes);
>+	if (ret) {
>+		dev_err(dev, "Failed to get dsi-lanes property (%d)\n", ret);
>+		return ret;
>+	}
>+
>+	panel->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
>+	if (IS_ERR(panel->reset))
>+		return PTR_ERR(panel->reset);
>+
>+	memset(&bl_props, 0, sizeof(bl_props));
>+	bl_props.type = BACKLIGHT_RAW;
>+	bl_props.brightness = 255;
>+	bl_props.max_brightness = 255;
>+
>+	panel->backlight = devm_backlight_device_register(dev, dev_name(dev),
>+							  dev, dsi, &rad_bl_ops,
>+							  &bl_props);
>+	if (IS_ERR(panel->backlight)) {
>+		ret = PTR_ERR(panel->backlight);
>+		dev_err(dev, "Failed to register backlight (%d)\n", ret);
>+		return ret;
>+	}
>+
>+	ret = rad_init_regulators(panel);
>+	if (ret)
>+		return ret;
>+
>+	drm_panel_init(&panel->panel);
>+	panel->panel.funcs = &rad_panel_funcs;
>+	panel->panel.dev = dev;
>+	dev_set_drvdata(dev, panel);
>+
>+	ret = drm_panel_add(&panel->panel);
>+	if (ret)
>+		return ret;
>+
>+	ret = mipi_dsi_attach(dsi);
>+	if (ret)
>+		drm_panel_remove(&panel->panel);
>+
>+	return ret;
>+}
>+
>+static int rad_panel_remove(struct mipi_dsi_device *dsi)
>+{
>+	struct rad_panel *rad = mipi_dsi_get_drvdata(dsi);
>+	struct device *dev = &dsi->dev;
>+	int ret;
>+
>+	ret = mipi_dsi_detach(dsi);
>+	if (ret)
>+		DRM_DEV_ERROR(dev, "Failed to detach from host (%d)\n",
>+			      ret);
>+
>+	drm_panel_remove(&rad->panel);
>+
>+	return 0;
>+}
>+
>+static void rad_panel_shutdown(struct mipi_dsi_device *dsi)
>+{
>+	struct rad_panel *rad = mipi_dsi_get_drvdata(dsi);
>+
>+	rad_panel_disable(&rad->panel);
>+	rad_panel_unprepare(&rad->panel);
>+}
>+
>+static const struct of_device_id rad_of_match[] = {
>+	{ .compatible = "raydium,rm67191", },
>+	{ /* sentinel */ }
>+};
>+MODULE_DEVICE_TABLE(of, rad_of_match);
>+
>+static struct mipi_dsi_driver rad_panel_driver = {
>+	.driver = {
>+		.name = "panel-raydium-rm67191",
>+		.of_match_table = rad_of_match,
>+	},
>+	.probe = rad_panel_probe,
>+	.remove = rad_panel_remove,
>+	.shutdown = rad_panel_shutdown,
>+};
>+module_mipi_dsi_driver(rad_panel_driver);
>+
>+MODULE_AUTHOR("Robert Chiras <robert.chiras@nxp.com>");
>+MODULE_DESCRIPTION("DRM Driver for Raydium RM67191 MIPI DSI panel");
>+MODULE_LICENSE("GPL v2");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c
>--- linux-5.3-rc6/drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c	2019-08-31 15:01:12.051736185 -0500
>@@ -15,6 +15,7 @@
> #include <linux/gpio/consumer.h>
> #include <linux/media-bus-format.h>
> #include <linux/module.h>
>+#include <linux/regulator/consumer.h>
> #include <video/display_timing.h>
> #include <video/mipi_display.h>
> 
>@@ -33,6 +34,7 @@
> #define ST7703_CMD_SETEXTC	 0xB9
> #define ST7703_CMD_SETMIPI	 0xBA
> #define ST7703_CMD_SETVDC	 0xBC
>+#define ST7703_CMD_UNKNOWN0	 0xBF
> #define ST7703_CMD_SETSCR	 0xC0
> #define ST7703_CMD_SETPOWER	 0xC1
> #define ST7703_CMD_SETPANEL	 0xCC
>@@ -46,6 +48,8 @@
> 	struct drm_panel panel;
> 	struct gpio_desc *reset_gpio;
> 	struct backlight_device *backlight;
>+	struct regulator *vcc;
>+	struct regulator *iovcc;
> 	bool prepared;
> 
> 	struct dentry *debugfs;
>@@ -94,7 +98,7 @@
> 	msleep(20);
> 
> 	dsi_generic_write_seq(dsi, ST7703_CMD_SETVCOM, 0x3F, 0x3F);
>-	dsi_generic_write_seq(dsi, 0xBF, 0x02, 0x11, 0x00);
>+	dsi_generic_write_seq(dsi, ST7703_CMD_UNKNOWN0, 0x02, 0x11, 0x00);
> 	dsi_generic_write_seq(dsi, ST7703_CMD_SETGIP1,
> 			      0x82, 0x10, 0x06, 0x05, 0x9E, 0x0A, 0xA5, 0x12,
> 			      0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38,
>@@ -123,7 +127,7 @@
> 
> 	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
> 	if (ret < 0) {
>-		DRM_DEV_ERROR(dev, "Failed to exit sleep mode\n");
>+		DRM_DEV_ERROR(dev, "Failed to exit sleep mode: %d\n", ret);
> 		return ret;
> 	}
> 	/* Panel is operational 120 msec after reset */
>@@ -139,6 +143,14 @@
> static int jh057n_enable(struct drm_panel *panel)
> {
> 	struct jh057n *ctx = panel_to_jh057n(panel);
>+	int ret;
>+
>+	ret = jh057n_init_sequence(ctx);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(ctx->dev, "Panel init sequence failed: %d\n",
>+			      ret);
>+		return ret;
>+	}
> 
> 	return backlight_enable(ctx->backlight);
> }
>@@ -146,19 +158,21 @@
> static int jh057n_disable(struct drm_panel *panel)
> {
> 	struct jh057n *ctx = panel_to_jh057n(panel);
>+	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> 
>-	return backlight_disable(ctx->backlight);
>+	backlight_disable(ctx->backlight);
>+	return mipi_dsi_dcs_set_display_off(dsi);
> }
> 
> static int jh057n_unprepare(struct drm_panel *panel)
> {
> 	struct jh057n *ctx = panel_to_jh057n(panel);
>-	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> 
> 	if (!ctx->prepared)
> 		return 0;
> 
>-	mipi_dsi_dcs_set_display_off(dsi);
>+	regulator_disable(ctx->iovcc);
>+	regulator_disable(ctx->vcc);
> 	ctx->prepared = false;
> 
> 	return 0;
>@@ -173,21 +187,31 @@
> 		return 0;
> 
> 	DRM_DEV_DEBUG_DRIVER(ctx->dev, "Resetting the panel\n");
>+	ret = regulator_enable(ctx->vcc);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(ctx->dev,
>+			      "Failed to enable vcc supply: %d\n", ret);
>+		return ret;
>+	}
>+	ret = regulator_enable(ctx->iovcc);
>+	if (ret < 0) {
>+		DRM_DEV_ERROR(ctx->dev,
>+			      "Failed to enable iovcc supply: %d\n", ret);
>+		goto disable_vcc;
>+	}
>+
> 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
> 	usleep_range(20, 40);
> 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
> 	msleep(20);
> 
>-	ret = jh057n_init_sequence(ctx);
>-	if (ret < 0) {
>-		DRM_DEV_ERROR(ctx->dev, "Panel init sequence failed: %d\n",
>-			      ret);
>-		return ret;
>-	}
>-
> 	ctx->prepared = true;
> 
> 	return 0;
>+
>+disable_vcc:
>+	regulator_disable(ctx->vcc);
>+	return ret;
> }
> 
> static const struct drm_display_mode default_mode = {
>@@ -300,6 +324,25 @@
> 	if (IS_ERR(ctx->backlight))
> 		return PTR_ERR(ctx->backlight);
> 
>+	ctx->vcc = devm_regulator_get(dev, "vcc");
>+	if (IS_ERR(ctx->vcc)) {
>+		ret = PTR_ERR(ctx->vcc);
>+		if (ret != -EPROBE_DEFER)
>+			DRM_DEV_ERROR(dev,
>+				      "Failed to request vcc regulator: %d\n",
>+				      ret);
>+		return ret;
>+	}
>+	ctx->iovcc = devm_regulator_get(dev, "iovcc");
>+	if (IS_ERR(ctx->iovcc)) {
>+		ret = PTR_ERR(ctx->iovcc);
>+		if (ret != -EPROBE_DEFER)
>+			DRM_DEV_ERROR(dev,
>+				      "Failed to request iovcc regulator: %d\n",
>+				      ret);
>+		return ret;
>+	}
>+
> 	drm_panel_init(&ctx->panel);
> 	ctx->panel.dev = dev;
> 	ctx->panel.funcs = &jh057n_drm_funcs;
>@@ -308,7 +351,9 @@
> 
> 	ret = mipi_dsi_attach(dsi);
> 	if (ret < 0) {
>-		DRM_DEV_ERROR(dev, "mipi_dsi_attach failed. Is host ready?\n");
>+		DRM_DEV_ERROR(dev,
>+			      "mipi_dsi_attach failed (%d). Is host ready?\n",
>+			      ret);
> 		drm_panel_remove(&ctx->panel);
> 		return ret;
> 	}
>@@ -327,12 +372,12 @@
> 	struct jh057n *ctx = mipi_dsi_get_drvdata(dsi);
> 	int ret;
> 
>-	ret = jh057n_unprepare(&ctx->panel);
>+	ret = drm_panel_unprepare(&ctx->panel);
> 	if (ret < 0)
> 		DRM_DEV_ERROR(&dsi->dev, "Failed to unprepare panel: %d\n",
> 			      ret);
> 
>-	ret = jh057n_disable(&ctx->panel);
>+	ret = drm_panel_disable(&ctx->panel);
> 	if (ret < 0)
> 		DRM_DEV_ERROR(&dsi->dev, "Failed to disable panel: %d\n",
> 			      ret);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panel/panel-simple.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/panel-simple.c
>--- linux-5.3-rc6/drivers/gpu/drm/panel/panel-simple.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panel/panel-simple.c	2019-08-31 15:01:12.051736185 -0500
>@@ -30,6 +30,7 @@
> #include <linux/regulator/consumer.h>
> 
> #include <video/display_timing.h>
>+#include <video/of_display_timing.h>
> #include <video/videomode.h>
> 
> #include <drm/drm_crtc.h>
>@@ -37,6 +38,22 @@
> #include <drm/drm_mipi_dsi.h>
> #include <drm/drm_panel.h>
> 
>+/**
>+ * @modes: Pointer to array of fixed modes appropriate for this panel.  If
>+ *         only one mode then this can just be the address of this the mode.
>+ *         NOTE: cannot be used with "timings" and also if this is specified
>+ *         then you cannot override the mode in the device tree.
>+ * @num_modes: Number of elements in modes array.
>+ * @timings: Pointer to array of display timings.  NOTE: cannot be used with
>+ *           "modes" and also these will be used to validate a device tree
>+ *           override if one is present.
>+ * @num_timings: Number of elements in timings array.
>+ * @bpc: Bits per color.
>+ * @size: Structure containing the physical size of this panel.
>+ * @delay: Structure containing various delay values for this panel.
>+ * @bus_format: See MEDIA_BUS_FMT_... defines.
>+ * @bus_flags: See DRM_BUS_FLAG_... defines.
>+ */
> struct panel_desc {
> 	const struct drm_display_mode *modes;
> 	unsigned int num_modes;
>@@ -92,6 +109,8 @@
> 	struct i2c_adapter *ddc;
> 
> 	struct gpio_desc *enable_gpio;
>+
>+	struct drm_display_mode override_mode;
> };
> 
> static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
>@@ -99,16 +118,13 @@
> 	return container_of(panel, struct panel_simple, base);
> }
> 
>-static int panel_simple_get_fixed_modes(struct panel_simple *panel)
>+static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel)
> {
> 	struct drm_connector *connector = panel->base.connector;
> 	struct drm_device *drm = panel->base.drm;
> 	struct drm_display_mode *mode;
> 	unsigned int i, num = 0;
> 
>-	if (!panel->desc)
>-		return 0;
>-
> 	for (i = 0; i < panel->desc->num_timings; i++) {
> 		const struct display_timing *dt = &panel->desc->timings[i];
> 		struct videomode vm;
>@@ -132,6 +148,16 @@
> 		num++;
> 	}
> 
>+	return num;
>+}
>+
>+static unsigned int panel_simple_get_display_modes(struct panel_simple *panel)
>+{
>+	struct drm_connector *connector = panel->base.connector;
>+	struct drm_device *drm = panel->base.drm;
>+	struct drm_display_mode *mode;
>+	unsigned int i, num = 0;
>+
> 	for (i = 0; i < panel->desc->num_modes; i++) {
> 		const struct drm_display_mode *m = &panel->desc->modes[i];
> 
>@@ -153,6 +179,44 @@
> 		num++;
> 	}
> 
>+	return num;
>+}
>+
>+static int panel_simple_get_non_edid_modes(struct panel_simple *panel)
>+{
>+	struct drm_connector *connector = panel->base.connector;
>+	struct drm_device *drm = panel->base.drm;
>+	struct drm_display_mode *mode;
>+	bool has_override = panel->override_mode.type;
>+	unsigned int num = 0;
>+
>+	if (!panel->desc)
>+		return 0;
>+
>+	if (has_override) {
>+		mode = drm_mode_duplicate(drm, &panel->override_mode);
>+		if (mode) {
>+			drm_mode_probed_add(connector, mode);
>+			num = 1;
>+		} else {
>+			dev_err(drm->dev, "failed to add override mode\n");
>+		}
>+	}
>+
>+	/* Only add timings if override was not there or failed to validate */
>+	if (num == 0 && panel->desc->num_timings)
>+		num = panel_simple_get_timings_modes(panel);
>+
>+	/*
>+	 * Only add fixed modes if timings/override added no mode.
>+	 *
>+	 * We should only ever have either the display timings specified
>+	 * or a fixed mode. Anything else is rather bogus.
>+	 */
>+	WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
>+	if (num == 0)
>+		num = panel_simple_get_display_modes(panel);
>+
> 	connector->display_info.bpc = panel->desc->bpc;
> 	connector->display_info.width_mm = panel->desc->size.width;
> 	connector->display_info.height_mm = panel->desc->size.height;
>@@ -269,7 +333,7 @@
> 	}
> 
> 	/* add hard-coded panel modes */
>-	num += panel_simple_get_fixed_modes(p);
>+	num += panel_simple_get_non_edid_modes(p);
> 
> 	return num;
> }
>@@ -300,10 +364,58 @@
> 	.get_timings = panel_simple_get_timings,
> };
> 
>+#define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
>+	(to_check->field.typ >= bounds->field.min && \
>+	 to_check->field.typ <= bounds->field.max)
>+static void panel_simple_parse_panel_timing_node(struct device *dev,
>+						 struct panel_simple *panel,
>+						 const struct display_timing *ot)
>+{
>+	const struct panel_desc *desc = panel->desc;
>+	struct videomode vm;
>+	unsigned int i;
>+
>+	if (WARN_ON(desc->num_modes)) {
>+		dev_err(dev, "Reject override mode: panel has a fixed mode\n");
>+		return;
>+	}
>+	if (WARN_ON(!desc->num_timings)) {
>+		dev_err(dev, "Reject override mode: no timings specified\n");
>+		return;
>+	}
>+
>+	for (i = 0; i < panel->desc->num_timings; i++) {
>+		const struct display_timing *dt = &panel->desc->timings[i];
>+
>+		if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
>+		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
>+		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
>+		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
>+		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
>+		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
>+		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
>+		    !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
>+			continue;
>+
>+		if (ot->flags != dt->flags)
>+			continue;
>+
>+		videomode_from_timing(ot, &vm);
>+		drm_display_mode_from_videomode(&vm, &panel->override_mode);
>+		panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
>+					     DRM_MODE_TYPE_PREFERRED;
>+		break;
>+	}
>+
>+	if (WARN_ON(!panel->override_mode.type))
>+		dev_err(dev, "Reject override mode: No display_timing found\n");
>+}
>+
> static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
> {
> 	struct device_node *backlight, *ddc;
> 	struct panel_simple *panel;
>+	struct display_timing dt;
> 	int err;
> 
> 	panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
>@@ -349,6 +461,9 @@
> 		}
> 	}
> 
>+	if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
>+		panel_simple_parse_panel_timing_node(dev, panel, &dt);
>+
> 	drm_panel_init(&panel->base);
> 	panel->base.dev = dev;
> 	panel->base.funcs = &panel_simple_funcs;
>@@ -496,22 +611,21 @@
> 	},
> };
> 
>-static const struct drm_display_mode auo_b101ean01_mode = {
>-	.clock = 72500,
>-	.hdisplay = 1280,
>-	.hsync_start = 1280 + 119,
>-	.hsync_end = 1280 + 119 + 32,
>-	.htotal = 1280 + 119 + 32 + 21,
>-	.vdisplay = 800,
>-	.vsync_start = 800 + 4,
>-	.vsync_end = 800 + 4 + 20,
>-	.vtotal = 800 + 4 + 20 + 8,
>-	.vrefresh = 60,
>+static const struct display_timing auo_b101ean01_timing = {
>+	.pixelclock = { 65300000, 72500000, 75000000 },
>+	.hactive = { 1280, 1280, 1280 },
>+	.hfront_porch = { 18, 119, 119 },
>+	.hback_porch = { 21, 21, 21 },
>+	.hsync_len = { 32, 32, 32 },
>+	.vactive = { 800, 800, 800 },
>+	.vfront_porch = { 4, 4, 4 },
>+	.vback_porch = { 8, 8, 8 },
>+	.vsync_len = { 18, 20, 20 },
> };
> 
> static const struct panel_desc auo_b101ean01 = {
>-	.modes = &auo_b101ean01_mode,
>-	.num_modes = 1,
>+	.timings = &auo_b101ean01_timing,
>+	.num_timings = 1,
> 	.bpc = 6,
> 	.size = {
> 		.width = 217,
>@@ -724,9 +838,9 @@
> static const struct display_timing auo_g185han01_timings = {
> 	.pixelclock = { 120000000, 144000000, 175000000 },
> 	.hactive = { 1920, 1920, 1920 },
>-	.hfront_porch = { 18, 60, 74 },
>-	.hback_porch = { 12, 44, 54 },
>-	.hsync_len = { 10, 24, 32 },
>+	.hfront_porch = { 36, 120, 148 },
>+	.hback_porch = { 24, 88, 108 },
>+	.hsync_len = { 20, 48, 64 },
> 	.vactive = { 1080, 1080, 1080 },
> 	.vfront_porch = { 6, 10, 40 },
> 	.vback_porch = { 2, 5, 20 },
>@@ -1335,6 +1449,31 @@
> 	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
> };
> 
>+static const struct display_timing giantplus_gpm940b0_timing = {
>+	.pixelclock = { 13500000, 27000000, 27500000 },
>+	.hactive = { 320, 320, 320 },
>+	.hfront_porch = { 14, 686, 718 },
>+	.hback_porch = { 50, 70, 255 },
>+	.hsync_len = { 1, 1, 1 },
>+	.vactive = { 240, 240, 240 },
>+	.vfront_porch = { 1, 1, 179 },
>+	.vback_porch = { 1, 21, 31 },
>+	.vsync_len = { 1, 1, 6 },
>+	.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
>+};
>+
>+static const struct panel_desc giantplus_gpm940b0 = {
>+	.timings = &giantplus_gpm940b0_timing,
>+	.num_timings = 1,
>+	.bpc = 8,
>+	.size = {
>+		.width = 60,
>+		.height = 45,
>+	},
>+	.bus_format = MEDIA_BUS_FMT_RGB888_3X8,
>+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
>+};
>+
> static const struct display_timing hannstar_hsd070pww1_timing = {
> 	.pixelclock = { 64300000, 71100000, 82000000 },
> 	.hactive = { 1280, 1280, 1280 },
>@@ -1578,23 +1717,32 @@
> 	},
> };
> 
>-static const struct drm_display_mode innolux_n116bge_mode = {
>-	.clock = 76420,
>-	.hdisplay = 1366,
>-	.hsync_start = 1366 + 136,
>-	.hsync_end = 1366 + 136 + 30,
>-	.htotal = 1366 + 136 + 30 + 60,
>-	.vdisplay = 768,
>-	.vsync_start = 768 + 8,
>-	.vsync_end = 768 + 8 + 12,
>-	.vtotal = 768 + 8 + 12 + 12,
>-	.vrefresh = 60,
>-	.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
>+/*
>+ * Datasheet specifies that at 60 Hz refresh rate:
>+ * - total horizontal time: { 1506, 1592, 1716 }
>+ * - total vertical time: { 788, 800, 868 }
>+ *
>+ * ...but doesn't go into exactly how that should be split into a front
>+ * porch, back porch, or sync length.  For now we'll leave a single setting
>+ * here which allows a bit of tweaking of the pixel clock at the expense of
>+ * refresh rate.
>+ */
>+static const struct display_timing innolux_n116bge_timing = {
>+	.pixelclock = { 72600000, 76420000, 80240000 },
>+	.hactive = { 1366, 1366, 1366 },
>+	.hfront_porch = { 136, 136, 136 },
>+	.hback_porch = { 60, 60, 60 },
>+	.hsync_len = { 30, 30, 30 },
>+	.vactive = { 768, 768, 768 },
>+	.vfront_porch = { 8, 8, 8 },
>+	.vback_porch = { 12, 12, 12 },
>+	.vsync_len = { 12, 12, 12 },
>+	.flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
> };
> 
> static const struct panel_desc innolux_n116bge = {
>-	.modes = &innolux_n116bge_mode,
>-	.num_modes = 1,
>+	.timings = &innolux_n116bge_timing,
>+	.num_timings = 1,
> 	.bpc = 6,
> 	.size = {
> 		.width = 256,
>@@ -2157,6 +2305,33 @@
> 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
> };
> 
>+static const struct drm_display_mode ortustech_com37h3m_mode  = {
>+	.clock = 22153,
>+	.hdisplay = 480,
>+	.hsync_start = 480 + 8,
>+	.hsync_end = 480 + 8 + 10,
>+	.htotal = 480 + 8 + 10 + 10,
>+	.vdisplay = 640,
>+	.vsync_start = 640 + 4,
>+	.vsync_end = 640 + 4 + 3,
>+	.vtotal = 640 + 4 + 3 + 4,
>+	.vrefresh = 60,
>+	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
>+};
>+
>+static const struct panel_desc ortustech_com37h3m = {
>+	.modes = &ortustech_com37h3m_mode,
>+	.num_modes = 1,
>+	.bpc = 8,
>+	.size = {
>+		.width = 56,	/* 56.16mm */
>+		.height = 75,	/* 74.88mm */
>+	},
>+	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
>+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
>+		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
>+};
>+
> static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
> 	.clock = 25000,
> 	.hdisplay = 480,
>@@ -2354,6 +2529,59 @@
> 	},
> };
> 
>+static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
>+	.clock = 168480,
>+	.hdisplay = 1920,
>+	.hsync_start = 1920 + 48,
>+	.hsync_end = 1920 + 48 + 32,
>+	.htotal = 1920 + 48 + 32 + 80,
>+	.vdisplay = 1280,
>+	.vsync_start = 1280 + 3,
>+	.vsync_end = 1280 + 3 + 10,
>+	.vtotal = 1280 + 3 + 10 + 57,
>+	.vrefresh = 60,
>+	.flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
>+};
>+
>+static const struct panel_desc sharp_ld_d5116z01b = {
>+	.modes = &sharp_ld_d5116z01b_mode,
>+	.num_modes = 1,
>+	.bpc = 8,
>+	.size = {
>+		.width = 260,
>+		.height = 120,
>+	},
>+	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
>+	.bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
>+};
>+
>+static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
>+	.clock = 33260,
>+	.hdisplay = 800,
>+	.hsync_start = 800 + 64,
>+	.hsync_end = 800 + 64 + 128,
>+	.htotal = 800 + 64 + 128 + 64,
>+	.vdisplay = 480,
>+	.vsync_start = 480 + 8,
>+	.vsync_end = 480 + 8 + 2,
>+	.vtotal = 480 + 8 + 2 + 35,
>+	.vrefresh = 60,
>+	.flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
>+};
>+
>+static const struct panel_desc sharp_lq070y3dg3b = {
>+	.modes = &sharp_lq070y3dg3b_mode,
>+	.num_modes = 1,
>+	.bpc = 8,
>+	.size = {
>+		.width = 152,	/* 152.4mm */
>+		.height = 91,	/* 91.4mm */
>+	},
>+	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
>+	.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
>+		     DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
>+};
>+
> static const struct drm_display_mode sharp_lq035q7db03_mode = {
> 	.clock = 5500,
> 	.hdisplay = 240,
>@@ -2454,6 +2682,33 @@
> 	.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
> };
> 
>+static const struct display_timing sharp_ls020b1dd01d_timing = {
>+	.pixelclock = { 2000000, 4200000, 5000000 },
>+	.hactive = { 240, 240, 240 },
>+	.hfront_porch = { 66, 66, 66 },
>+	.hback_porch = { 1, 1, 1 },
>+	.hsync_len = { 1, 1, 1 },
>+	.vactive = { 160, 160, 160 },
>+	.vfront_porch = { 52, 52, 52 },
>+	.vback_porch = { 6, 6, 6 },
>+	.vsync_len = { 10, 10, 10 },
>+	.flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
>+};
>+
>+static const struct panel_desc sharp_ls020b1dd01d = {
>+	.timings = &sharp_ls020b1dd01d_timing,
>+	.num_timings = 1,
>+	.bpc = 6,
>+	.size = {
>+		.width = 42,
>+		.height = 28,
>+	},
>+	.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
>+	.bus_flags = DRM_BUS_FLAG_DE_HIGH
>+		   | DRM_BUS_FLAG_PIXDATA_NEGEDGE
>+		   | DRM_BUS_FLAG_SHARP_SIGNALS,
>+};
>+
> static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
> 	.clock = 33300,
> 	.hdisplay = 800,
>@@ -2883,6 +3138,9 @@
> 		.compatible = "giantplus,gpg482739qs5",
> 		.data = &giantplus_gpg482739qs5
> 	}, {
>+		.compatible = "giantplus,gpm940b0",
>+		.data = &giantplus_gpm940b0,
>+	}, {
> 		.compatible = "hannstar,hsd070pww1",
> 		.data = &hannstar_hsd070pww1,
> 	}, {
>@@ -2979,6 +3237,12 @@
> 		.compatible = "ontat,yx700wv03",
> 		.data = &ontat_yx700wv03,
> 	}, {
>+		.compatible = "ortustech,com37h3m05dtc",
>+		.data = &ortustech_com37h3m,
>+	}, {
>+		.compatible = "ortustech,com37h3m99dtc",
>+		.data = &ortustech_com37h3m,
>+	}, {
> 		.compatible = "ortustech,com43h4m85ulc",
> 		.data = &ortustech_com43h4m85ulc,
> 	}, {
>@@ -3003,9 +3267,15 @@
> 		.compatible = "samsung,ltn140at29-301",
> 		.data = &samsung_ltn140at29_301,
> 	}, {
>+		.compatible = "sharp,ld-d5116z01b",
>+		.data = &sharp_ld_d5116z01b,
>+	}, {
> 		.compatible = "sharp,lq035q7db03",
> 		.data = &sharp_lq035q7db03,
> 	}, {
>+		.compatible = "sharp,lq070y3dg3b",
>+		.data = &sharp_lq070y3dg3b,
>+	}, {
> 		.compatible = "sharp,lq101k1ly04",
> 		.data = &sharp_lq101k1ly04,
> 	}, {
>@@ -3015,6 +3285,9 @@
> 		.compatible = "sharp,lq150x1lg11",
> 		.data = &sharp_lq150x1lg11,
> 	}, {
>+		.compatible = "sharp,ls020b1dd01d",
>+		.data = &sharp_ls020b1dd01d,
>+	}, {
> 		.compatible = "shelly,sca07010-bfn-lnn",
> 		.data = &shelly_sca07010_bfn_lnn,
> 	}, {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panfrost/panfrost_devfreq.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/panfrost/panfrost_devfreq.c
>--- linux-5.3-rc6/drivers/gpu/drm/panfrost/panfrost_devfreq.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panfrost/panfrost_devfreq.c	2019-08-31 15:01:12.051736185 -0500
>@@ -157,7 +157,8 @@
> 	dev_pm_opp_put(opp);
> 
> 	pfdev->devfreq.devfreq = devm_devfreq_add_device(&pfdev->pdev->dev,
>-			&panfrost_devfreq_profile, "simple_ondemand", NULL);
>+			&panfrost_devfreq_profile, DEVFREQ_GOV_SIMPLE_ONDEMAND,
>+			NULL);
> 	if (IS_ERR(pfdev->devfreq.devfreq)) {
> 		DRM_DEV_ERROR(&pfdev->pdev->dev, "Couldn't initialize GPU devfreq\n");
> 		ret = PTR_ERR(pfdev->devfreq.devfreq);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panfrost/panfrost_device.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/panfrost/panfrost_device.h
>--- linux-5.3-rc6/drivers/gpu/drm/panfrost/panfrost_device.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panfrost/panfrost_device.h	2019-08-31 15:01:12.051736185 -0500
>@@ -43,6 +43,7 @@
> 	u32 js_features[16];
> 
> 	u32 nr_core_groups;
>+	u32 thread_tls_alloc;
> 
> 	unsigned long hw_features[64 / BITS_PER_LONG];
> 	unsigned long hw_issues[64 / BITS_PER_LONG];
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panfrost/panfrost_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/panfrost/panfrost_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/panfrost/panfrost_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panfrost/panfrost_drv.c	2019-08-31 15:01:12.051736185 -0500
>@@ -32,10 +32,42 @@
> 	if (param->pad != 0)
> 		return -EINVAL;
> 
>+#define PANFROST_FEATURE(name, member)			\
>+	case DRM_PANFROST_PARAM_ ## name:		\
>+		param->value = pfdev->features.member;	\
>+		break
>+#define PANFROST_FEATURE_ARRAY(name, member, max)			\
>+	case DRM_PANFROST_PARAM_ ## name ## 0 ...			\
>+		DRM_PANFROST_PARAM_ ## name ## max:			\
>+		param->value = pfdev->features.member[param->param -	\
>+			DRM_PANFROST_PARAM_ ## name ## 0];		\
>+		break
>+
> 	switch (param->param) {
>-	case DRM_PANFROST_PARAM_GPU_PROD_ID:
>-		param->value = pfdev->features.id;
>-		break;
>+		PANFROST_FEATURE(GPU_PROD_ID, id);
>+		PANFROST_FEATURE(GPU_REVISION, revision);
>+		PANFROST_FEATURE(SHADER_PRESENT, shader_present);
>+		PANFROST_FEATURE(TILER_PRESENT, tiler_present);
>+		PANFROST_FEATURE(L2_PRESENT, l2_present);
>+		PANFROST_FEATURE(STACK_PRESENT, stack_present);
>+		PANFROST_FEATURE(AS_PRESENT, as_present);
>+		PANFROST_FEATURE(JS_PRESENT, js_present);
>+		PANFROST_FEATURE(L2_FEATURES, l2_features);
>+		PANFROST_FEATURE(CORE_FEATURES, core_features);
>+		PANFROST_FEATURE(TILER_FEATURES, tiler_features);
>+		PANFROST_FEATURE(MEM_FEATURES, mem_features);
>+		PANFROST_FEATURE(MMU_FEATURES, mmu_features);
>+		PANFROST_FEATURE(THREAD_FEATURES, thread_features);
>+		PANFROST_FEATURE(MAX_THREADS, max_threads);
>+		PANFROST_FEATURE(THREAD_MAX_WORKGROUP_SZ,
>+				thread_max_workgroup_sz);
>+		PANFROST_FEATURE(THREAD_MAX_BARRIER_SZ,
>+				thread_max_barrier_sz);
>+		PANFROST_FEATURE(COHERENCY_FEATURES, coherency_features);
>+		PANFROST_FEATURE_ARRAY(TEXTURE_FEATURES, texture_features, 3);
>+		PANFROST_FEATURE_ARRAY(JS_FEATURES, js_features, 15);
>+		PANFROST_FEATURE(NR_CORE_GROUPS, nr_core_groups);
>+		PANFROST_FEATURE(THREAD_TLS_ALLOC, thread_tls_alloc);
> 	default:
> 		return -EINVAL;
> 	}
>@@ -357,8 +389,7 @@
> DEFINE_DRM_GEM_SHMEM_FOPS(panfrost_drm_driver_fops);
> 
> static struct drm_driver panfrost_drm_driver = {
>-	.driver_features	= DRIVER_RENDER | DRIVER_GEM | DRIVER_PRIME |
>-				  DRIVER_SYNCOBJ,
>+	.driver_features	= DRIVER_RENDER | DRIVER_GEM | DRIVER_SYNCOBJ,
> 	.open			= panfrost_open,
> 	.postclose		= panfrost_postclose,
> 	.ioctls			= panfrost_drm_driver_ioctls,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panfrost/panfrost_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/panfrost/panfrost_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/panfrost/panfrost_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panfrost/panfrost_gem.c	2019-08-31 15:01:12.051736185 -0500
>@@ -92,8 +92,6 @@
> 
> 	pobj = to_panfrost_bo(obj);
> 
>-	obj->resv = attach->dmabuf->resv;
>-
> 	panfrost_mmu_map(pobj);
> 
> 	return obj;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/panfrost/panfrost_gpu.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/panfrost/panfrost_gpu.c
>--- linux-5.3-rc6/drivers/gpu/drm/panfrost/panfrost_gpu.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/panfrost/panfrost_gpu.c	2019-08-31 15:01:12.051736185 -0500
>@@ -232,6 +232,8 @@
> 	pfdev->features.stack_present = gpu_read(pfdev, GPU_STACK_PRESENT_LO);
> 	pfdev->features.stack_present |= (u64)gpu_read(pfdev, GPU_STACK_PRESENT_HI) << 32;
> 
>+	pfdev->features.thread_tls_alloc = gpu_read(pfdev, GPU_THREAD_TLS_ALLOC);
>+
> 	gpu_id = gpu_read(pfdev, GPU_ID);
> 	pfdev->features.revision = gpu_id & 0xffff;
> 	pfdev->features.id = gpu_id >> 16;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_debugfs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_debugfs.c
>--- linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_debugfs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_debugfs.c	2019-08-31 15:01:12.051736185 -0500
>@@ -5,8 +5,10 @@
> 
> #include <linux/amba/clcd-regs.h>
> #include <linux/seq_file.h>
>+
> #include <drm/drm_debugfs.h>
>-#include <drm/drmP.h>
>+#include <drm/drm_file.h>
>+
> #include "pl111_drm.h"
> 
> #define REGDEF(reg) { reg, #reg }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_display.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_display.c
>--- linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_display.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_display.c	2019-08-31 15:01:12.051736185 -0500
>@@ -11,14 +11,16 @@
> 
> #include <linux/amba/clcd-regs.h>
> #include <linux/clk.h>
>+#include <linux/delay.h>
> #include <linux/version.h>
> #include <linux/dma-buf.h>
> #include <linux/of_graph.h>
> 
>-#include <drm/drmP.h>
>+#include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "pl111_drm.h"
> 
>@@ -546,25 +548,8 @@
> int pl111_display_init(struct drm_device *drm)
> {
> 	struct pl111_drm_dev_private *priv = drm->dev_private;
>-	struct device *dev = drm->dev;
>-	struct device_node *endpoint;
>-	u32 tft_r0b0g0[3];
> 	int ret;
> 
>-	endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
>-	if (!endpoint)
>-		return -ENODEV;
>-
>-	if (of_property_read_u32_array(endpoint,
>-				       "arm,pl11x,tft-r0g0b0-pads",
>-				       tft_r0b0g0,
>-				       ARRAY_SIZE(tft_r0b0g0)) != 0) {
>-		dev_err(dev, "arm,pl11x,tft-r0g0b0-pads should be 3 ints\n");
>-		of_node_put(endpoint);
>-		return -ENOENT;
>-	}
>-	of_node_put(endpoint);
>-
> 	ret = pl111_init_clock_divider(drm);
> 	if (ret)
> 		return ret;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_drm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_drm.h
>--- linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_drm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_drm.h	2019-08-31 15:01:12.051736185 -0500
>@@ -13,14 +13,15 @@
> #ifndef _PL111_DRM_H_
> #define _PL111_DRM_H_
> 
>-#include <drm/drm_gem.h>
>-#include <drm/drm_simple_kms_helper.h>
>+#include <linux/clk-provider.h>
>+#include <linux/interrupt.h>
>+
>+#include <drm/drm_bridge.h>
> #include <drm/drm_connector.h>
> #include <drm/drm_encoder.h>
>+#include <drm/drm_gem.h>
> #include <drm/drm_panel.h>
>-#include <drm/drm_bridge.h>
>-#include <linux/clk-provider.h>
>-#include <linux/interrupt.h>
>+#include <drm/drm_simple_kms_helper.h>
> 
> #define CLCD_IRQ_NEXTBASE_UPDATE BIT(2)
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_drv.c	2019-08-31 15:01:12.051736185 -0500
>@@ -48,18 +48,18 @@
> 
> #include <linux/amba/bus.h>
> #include <linux/amba/clcd-regs.h>
>-#include <linux/version.h>
>-#include <linux/shmem_fs.h>
> #include <linux/dma-buf.h>
> #include <linux/module.h>
>-#include <linux/slab.h>
> #include <linux/of.h>
> #include <linux/of_graph.h>
> #include <linux/of_reserved_mem.h>
>+#include <linux/shmem_fs.h>
>+#include <linux/slab.h>
>+#include <linux/version.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_bridge.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_fb_helper.h>
> #include <drm/drm_gem_cma_helper.h>
>@@ -67,6 +67,7 @@
> #include <drm/drm_of.h>
> #include <drm/drm_panel.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "pl111_drm.h"
> #include "pl111_versatile.h"
>@@ -224,7 +225,7 @@
> 
> static struct drm_driver pl111_drm_driver = {
> 	.driver_features =
>-		DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | DRIVER_ATOMIC,
>+		DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> 	.ioctls = NULL,
> 	.fops = &drm_fops,
> 	.name = "pl111",
>@@ -238,9 +239,7 @@
> 	.gem_vm_ops = &drm_gem_cma_vm_ops,
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_import = drm_gem_prime_import,
> 	.gem_prime_import_sg_table = pl111_gem_import_sg_table,
>-	.gem_prime_export = drm_gem_prime_export,
> 	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_mmap = drm_gem_cma_prime_mmap,
> 	.gem_prime_vmap = drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_nomadik.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_nomadik.h
>--- linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_nomadik.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_nomadik.h	2019-08-31 15:01:12.052736185 -0500
>@@ -1,10 +1,11 @@
> // SPDX-License-Identifier: GPL-2.0+
>-#include <linux/device.h>
> 
> #ifndef PL111_NOMADIK_H
> #define PL111_NOMADIK_H
> #endif
> 
>+struct device;
>+
> #ifdef CONFIG_ARCH_NOMADIK
> 
> void pl111_nomadik_init(struct device *dev);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_versatile.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_versatile.c
>--- linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_versatile.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_versatile.c	2019-08-31 15:01:12.052736185 -0500
>@@ -1,13 +1,14 @@
> // SPDX-License-Identifier: GPL-2.0-only
>+
> #include <linux/amba/clcd-regs.h>
>+#include <linux/bitops.h>
> #include <linux/device.h>
>+#include <linux/mfd/syscon.h>
>+#include <linux/module.h>
> #include <linux/of.h>
> #include <linux/of_platform.h>
> #include <linux/regmap.h>
>-#include <linux/mfd/syscon.h>
>-#include <linux/bitops.h>
>-#include <linux/module.h>
>-#include <drm/drmP.h>
>+
> #include "pl111_versatile.h"
> #include "pl111_vexpress.h"
> #include "pl111_drm.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_versatile.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_versatile.h
>--- linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_versatile.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_versatile.h	2019-08-31 15:01:12.052736185 -0500
>@@ -4,6 +4,9 @@
> #ifndef PL111_VERSATILE_H
> #define PL111_VERSATILE_H
> 
>+struct device;
>+struct pl111_drm_dev_private;
>+
> int pl111_versatile_init(struct device *dev, struct pl111_drm_dev_private *priv);
> 
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_vexpress.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_vexpress.c
>--- linux-5.3-rc6/drivers/gpu/drm/pl111/pl111_vexpress.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/pl111/pl111_vexpress.c	2019-08-31 15:01:12.052736185 -0500
>@@ -51,6 +51,7 @@
> 		}
> 		if (of_device_is_compatible(child, "arm,hdlcd")) {
> 			has_coretile_hdlcd = true;
>+			of_node_put(child);
> 			break;
> 		}
> 	}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_cmd.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_cmd.c
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_cmd.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_cmd.c	2019-08-31 15:01:12.052736185 -0500
>@@ -25,6 +25,8 @@
> 
> /* QXL cmd/ring handling */
> 
>+#include <linux/delay.h>
>+
> #include <drm/drm_util.h>
> 
> #include "qxl_drv.h"
>@@ -375,7 +377,7 @@
> {
> 	wait_for_io_cmd(qdev, 0, QXL_IO_DESTROY_PRIMARY_ASYNC);
> 	qdev->primary_bo->is_primary = false;
>-	drm_gem_object_put_unlocked(&qdev->primary_bo->gem_base);
>+	drm_gem_object_put_unlocked(&qdev->primary_bo->tbo.base);
> 	qdev->primary_bo = NULL;
> }
> 
>@@ -402,7 +404,7 @@
> 	wait_for_io_cmd(qdev, 0, QXL_IO_CREATE_PRIMARY_ASYNC);
> 	qdev->primary_bo = bo;
> 	qdev->primary_bo->is_primary = true;
>-	drm_gem_object_get(&qdev->primary_bo->gem_base);
>+	drm_gem_object_get(&qdev->primary_bo->tbo.base);
> }
> 
> void qxl_io_memslot_add(struct qxl_device *qdev, uint8_t id)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_debugfs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_debugfs.c
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_debugfs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_debugfs.c	2019-08-31 15:01:12.052736185 -0500
>@@ -28,9 +28,9 @@
>  *  Alon Levy <alevy@redhat.com>
>  */
> 
>-#include <linux/debugfs.h>
>+#include <drm/drm_debugfs.h>
>+#include <drm/drm_file.h>
> 
>-#include <drm/drmP.h>
> #include "qxl_drv.h"
> #include "qxl_object.h"
> 
>@@ -61,12 +61,12 @@
> 		int rel;
> 
> 		rcu_read_lock();
>-		fobj = rcu_dereference(bo->tbo.resv->fence);
>+		fobj = rcu_dereference(bo->tbo.base.resv->fence);
> 		rel = fobj ? fobj->shared_count : 0;
> 		rcu_read_unlock();
> 
> 		seq_printf(m, "size %ld, pc %d, num releases %d\n",
>-			   (unsigned long)bo->gem_base.size,
>+			   (unsigned long)bo->tbo.base.size,
> 			   bo->pin_count, rel);
> 	}
> 	return 0;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_display.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_display.c
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_display.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_display.c	2019-08-31 15:01:12.052736185 -0500
>@@ -24,11 +24,14 @@
>  */
> 
> #include <linux/crc32.h>
>+#include <linux/delay.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "qxl_drv.h"
> #include "qxl_object.h"
>@@ -794,7 +797,7 @@
> 		    qdev->dumb_shadow_bo->surf.height != surf.height) {
> 			if (qdev->dumb_shadow_bo) {
> 				drm_gem_object_put_unlocked
>-					(&qdev->dumb_shadow_bo->gem_base);
>+					(&qdev->dumb_shadow_bo->tbo.base);
> 				qdev->dumb_shadow_bo = NULL;
> 			}
> 			qxl_bo_create(qdev, surf.height * surf.stride,
>@@ -804,10 +807,10 @@
> 		if (user_bo->shadow != qdev->dumb_shadow_bo) {
> 			if (user_bo->shadow) {
> 				drm_gem_object_put_unlocked
>-					(&user_bo->shadow->gem_base);
>+					(&user_bo->shadow->tbo.base);
> 				user_bo->shadow = NULL;
> 			}
>-			drm_gem_object_get(&qdev->dumb_shadow_bo->gem_base);
>+			drm_gem_object_get(&qdev->dumb_shadow_bo->tbo.base);
> 			user_bo->shadow = qdev->dumb_shadow_bo;
> 		}
> 	}
>@@ -838,7 +841,7 @@
> 	qxl_bo_unpin(user_bo);
> 
> 	if (old_state->fb != plane->state->fb && user_bo->shadow) {
>-		drm_gem_object_put_unlocked(&user_bo->shadow->gem_base);
>+		drm_gem_object_put_unlocked(&user_bo->shadow->tbo.base);
> 		user_bo->shadow = NULL;
> 	}
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_draw.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_draw.c
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_draw.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_draw.c	2019-08-31 15:01:12.052736185 -0500
>@@ -20,6 +20,8 @@
>  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  */
> 
>+#include <drm/drm_fourcc.h>
>+
> #include "qxl_drv.h"
> #include "qxl_object.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_drv.c	2019-08-31 15:01:12.052736185 -0500
>@@ -28,14 +28,18 @@
>  *    Alon Levy <alevy@redhat.com>
>  */
> 
>-#include <linux/module.h>
>+#include "qxl_drv.h"
> #include <linux/console.h>
>+#include <linux/module.h>
>+#include <linux/pci.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_file.h>
> #include <drm/drm_modeset_helper.h>
>+#include <drm/drm_prime.h>
> #include <drm/drm_probe_helper.h>
>-#include "qxl_drv.h"
>+
> #include "qxl_object.h"
> 
> static const struct pci_device_id pciidlist[] = {
>@@ -206,16 +210,14 @@
> 
> static int qxl_pm_thaw(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 
> 	return qxl_drm_resume(drm_dev, true);
> }
> 
> static int qxl_pm_freeze(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 
> 	return qxl_drm_freeze(drm_dev);
> }
>@@ -247,8 +249,7 @@
> };
> 
> static struct drm_driver qxl_driver = {
>-	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
>-			   DRIVER_ATOMIC,
>+	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 
> 	.dumb_create = qxl_mode_dumb_create,
> 	.dumb_map_offset = qxl_mode_dumb_mmap,
>@@ -257,8 +258,6 @@
> #endif
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_export = drm_gem_prime_export,
>-	.gem_prime_import = drm_gem_prime_import,
> 	.gem_prime_pin = qxl_gem_prime_pin,
> 	.gem_prime_unpin = qxl_gem_prime_unpin,
> 	.gem_prime_get_sg_table = qxl_gem_prime_get_sg_table,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_drv.h	2019-08-31 15:01:12.052736185 -0500
>@@ -31,22 +31,21 @@
>  */
> 
> #include <linux/dma-fence.h>
>-#include <linux/workqueue.h>
> #include <linux/firmware.h>
> #include <linux/platform_device.h>
>+#include <linux/workqueue.h>
> 
> #include <drm/drm_crtc.h>
> #include <drm/drm_encoder.h>
> #include <drm/drm_fb_helper.h>
>+#include <drm/drm_ioctl.h>
> #include <drm/drm_gem.h>
>-#include <drm/drmP.h>
>+#include <drm/qxl_drm.h>
> #include <drm/ttm/ttm_bo_api.h>
> #include <drm/ttm/ttm_bo_driver.h>
>-/* just for ttm_validate_buffer */
> #include <drm/ttm/ttm_execbuf_util.h>
> #include <drm/ttm/ttm_module.h>
> #include <drm/ttm/ttm_placement.h>
>-#include <drm/qxl_drm.h>
> 
> #include "qxl_dev.h"
> 
>@@ -72,12 +71,13 @@
> 	QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)
> 
> struct qxl_bo {
>+	struct ttm_buffer_object	tbo;
>+
> 	/* Protected by gem.mutex */
> 	struct list_head		list;
> 	/* Protected by tbo.reserved */
> 	struct ttm_place		placements[3];
> 	struct ttm_placement		placement;
>-	struct ttm_buffer_object	tbo;
> 	struct ttm_bo_kmap_obj		kmap;
> 	unsigned int pin_count;
> 	void				*kptr;
>@@ -85,7 +85,6 @@
> 	int                             type;
> 
> 	/* Constant after initialization */
>-	struct drm_gem_object		gem_base;
> 	unsigned int is_primary:1; /* is this now a primary surface */
> 	unsigned int is_dumb:1;
> 	struct qxl_bo *shadow;
>@@ -94,7 +93,7 @@
> 	uint32_t surface_id;
> 	struct qxl_release *surf_create;
> };
>-#define gem_to_qxl_bo(gobj) container_of((gobj), struct qxl_bo, gem_base)
>+#define gem_to_qxl_bo(gobj) container_of((gobj), struct qxl_bo, tbo.base)
> #define to_qxl_bo(tobj) container_of((tobj), struct qxl_bo, tbo)
> 
> struct qxl_gem {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_gem.c	2019-08-31 15:01:12.052736185 -0500
>@@ -23,7 +23,6 @@
>  *          Alon Levy
>  */
> 
>-#include <drm/drmP.h>
> #include <drm/drm.h>
> 
> #include "qxl_drv.h"
>@@ -64,7 +63,7 @@
> 				  size, initial_domain, alignment, r);
> 		return r;
> 	}
>-	*obj = &qbo->gem_base;
>+	*obj = &qbo->tbo.base;
> 
> 	mutex_lock(&qdev->gem.mutex);
> 	list_add_tail(&qbo->list, &qdev->gem.objects);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_ioctl.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_ioctl.c
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_ioctl.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_ioctl.c	2019-08-31 15:01:12.052736185 -0500
>@@ -23,6 +23,9 @@
>  *          Alon Levy
>  */
> 
>+#include <linux/pci.h>
>+#include <linux/uaccess.h>
>+
> #include "qxl_drv.h"
> #include "qxl_object.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_irq.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_irq.c
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_irq.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_irq.c	2019-08-31 15:01:12.052736185 -0500
>@@ -23,6 +23,10 @@
>  *          Alon Levy
>  */
> 
>+#include <linux/pci.h>
>+
>+#include <drm/drm_irq.h>
>+
> #include "qxl_drv.h"
> 
> irqreturn_t qxl_irq_handler(int irq, void *arg)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_kms.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_kms.c
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_kms.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_kms.c	2019-08-31 15:01:12.053736185 -0500
>@@ -23,11 +23,14 @@
>  *          Alon Levy
>  */
> 
>-#include "qxl_drv.h"
>-#include "qxl_object.h"
>+#include <linux/io-mapping.h>
>+#include <linux/pci.h>
> 
>+#include <drm/drm_drv.h>
> #include <drm/drm_probe_helper.h>
>-#include <linux/io-mapping.h>
>+
>+#include "qxl_drv.h"
>+#include "qxl_object.h"
> 
> int qxl_log_level;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_object.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_object.c
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_object.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_object.c	2019-08-31 15:01:12.053736185 -0500
>@@ -33,14 +33,14 @@
> 	struct qxl_device *qdev;
> 
> 	bo = to_qxl_bo(tbo);
>-	qdev = (struct qxl_device *)bo->gem_base.dev->dev_private;
>+	qdev = (struct qxl_device *)bo->tbo.base.dev->dev_private;
> 
> 	qxl_surface_evict(qdev, bo, false);
> 	WARN_ON_ONCE(bo->map_count > 0);
> 	mutex_lock(&qdev->gem.mutex);
> 	list_del_init(&bo->list);
> 	mutex_unlock(&qdev->gem.mutex);
>-	drm_gem_object_release(&bo->gem_base);
>+	drm_gem_object_release(&bo->tbo.base);
> 	kfree(bo);
> }
> 
>@@ -95,7 +95,7 @@
> 	if (bo == NULL)
> 		return -ENOMEM;
> 	size = roundup(size, PAGE_SIZE);
>-	r = drm_gem_object_init(&qdev->ddev, &bo->gem_base, size);
>+	r = drm_gem_object_init(&qdev->ddev, &bo->tbo.base, size);
> 	if (unlikely(r)) {
> 		kfree(bo);
> 		return r;
>@@ -214,20 +214,20 @@
> 	if ((*bo) == NULL)
> 		return;
> 
>-	drm_gem_object_put_unlocked(&(*bo)->gem_base);
>+	drm_gem_object_put_unlocked(&(*bo)->tbo.base);
> 	*bo = NULL;
> }
> 
> struct qxl_bo *qxl_bo_ref(struct qxl_bo *bo)
> {
>-	drm_gem_object_get(&bo->gem_base);
>+	drm_gem_object_get(&bo->tbo.base);
> 	return bo;
> }
> 
> static int __qxl_bo_pin(struct qxl_bo *bo)
> {
> 	struct ttm_operation_ctx ctx = { false, false };
>-	struct drm_device *ddev = bo->gem_base.dev;
>+	struct drm_device *ddev = bo->tbo.base.dev;
> 	int r;
> 
> 	if (bo->pin_count) {
>@@ -247,7 +247,7 @@
> static int __qxl_bo_unpin(struct qxl_bo *bo)
> {
> 	struct ttm_operation_ctx ctx = { false, false };
>-	struct drm_device *ddev = bo->gem_base.dev;
>+	struct drm_device *ddev = bo->tbo.base.dev;
> 	int r, i;
> 
> 	if (!bo->pin_count) {
>@@ -310,13 +310,13 @@
> 	dev_err(qdev->ddev.dev, "Userspace still has active objects !\n");
> 	list_for_each_entry_safe(bo, n, &qdev->gem.objects, list) {
> 		dev_err(qdev->ddev.dev, "%p %p %lu %lu force free\n",
>-			&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
>-			*((unsigned long *)&bo->gem_base.refcount));
>+			&bo->tbo.base, bo, (unsigned long)bo->tbo.base.size,
>+			*((unsigned long *)&bo->tbo.base.refcount));
> 		mutex_lock(&qdev->gem.mutex);
> 		list_del_init(&bo->list);
> 		mutex_unlock(&qdev->gem.mutex);
> 		/* this should unref the ttm bo */
>-		drm_gem_object_put_unlocked(&bo->gem_base);
>+		drm_gem_object_put_unlocked(&bo->tbo.base);
> 	}
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_object.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_object.h
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_object.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_object.h	2019-08-31 15:01:12.053736185 -0500
>@@ -34,7 +34,7 @@
> 	r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL);
> 	if (unlikely(r != 0)) {
> 		if (r != -ERESTARTSYS) {
>-			struct drm_device *ddev = bo->gem_base.dev;
>+			struct drm_device *ddev = bo->tbo.base.dev;
> 
> 			dev_err(ddev->dev, "%p reserve failed\n", bo);
> 		}
>@@ -60,7 +60,7 @@
> 
> static inline u64 qxl_bo_mmap_offset(struct qxl_bo *bo)
> {
>-	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
>+	return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
> }
> 
> static inline int qxl_bo_wait(struct qxl_bo *bo, u32 *mem_type,
>@@ -71,7 +71,7 @@
> 	r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL);
> 	if (unlikely(r != 0)) {
> 		if (r != -ERESTARTSYS) {
>-			struct drm_device *ddev = bo->gem_base.dev;
>+			struct drm_device *ddev = bo->tbo.base.dev;
> 
> 			dev_err(ddev->dev, "%p reserve failed for wait\n",
> 				bo);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_release.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_release.c
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_release.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_release.c	2019-08-31 15:01:12.053736185 -0500
>@@ -19,9 +19,13 @@
>  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  */
>+
>+#include <linux/delay.h>
>+
>+#include <trace/events/dma_fence.h>
>+
> #include "qxl_drv.h"
> #include "qxl_object.h"
>-#include <trace/events/dma_fence.h>
> 
> /*
>  * drawable cmd cache - allocate a bunch of VRAM pages, suballocate
>@@ -234,12 +238,12 @@
> 			return ret;
> 	}
> 
>-	ret = reservation_object_reserve_shared(bo->tbo.resv, 1);
>+	ret = reservation_object_reserve_shared(bo->tbo.base.resv, 1);
> 	if (ret)
> 		return ret;
> 
> 	/* allocate a surface for reserved + validated buffers */
>-	ret = qxl_bo_check_id(bo->gem_base.dev->dev_private, bo);
>+	ret = qxl_bo_check_id(bo->tbo.base.dev->dev_private, bo);
> 	if (ret)
> 		return ret;
> 	return 0;
>@@ -454,9 +458,9 @@
> 	list_for_each_entry(entry, &release->bos, head) {
> 		bo = entry->bo;
> 
>-		reservation_object_add_shared_fence(bo->resv, &release->base);
>+		reservation_object_add_shared_fence(bo->base.resv, &release->base);
> 		ttm_bo_add_to_lru(bo);
>-		reservation_object_unlock(bo->resv);
>+		reservation_object_unlock(bo->base.resv);
> 	}
> 	spin_unlock(&glob->lru_lock);
> 	ww_acquire_fini(&release->ticket);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_ttm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_ttm.c
>--- linux-5.3-rc6/drivers/gpu/drm/qxl/qxl_ttm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/qxl/qxl_ttm.c	2019-08-31 15:01:12.053736185 -0500
>@@ -23,19 +23,21 @@
>  *          Alon Levy
>  */
> 
>+#include <linux/delay.h>
>+
>+#include <drm/drm.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_debugfs.h>
>+#include <drm/qxl_drm.h>
> #include <drm/ttm/ttm_bo_api.h>
> #include <drm/ttm/ttm_bo_driver.h>
>-#include <drm/ttm/ttm_placement.h>
>-#include <drm/ttm/ttm_page_alloc.h>
> #include <drm/ttm/ttm_module.h>
>-#include <drm/drmP.h>
>-#include <drm/drm.h>
>-#include <drm/qxl_drm.h>
>+#include <drm/ttm/ttm_page_alloc.h>
>+#include <drm/ttm/ttm_placement.h>
>+
> #include "qxl_drv.h"
> #include "qxl_object.h"
> 
>-#include <linux/delay.h>
>-
> static struct qxl_device *qxl_get_qdev(struct ttm_bo_device *bdev)
> {
> 	struct qxl_mman *mman;
>@@ -153,7 +155,7 @@
> {
> 	struct qxl_bo *qbo = to_qxl_bo(bo);
> 
>-	return drm_vma_node_verify_access(&qbo->gem_base.vma_node,
>+	return drm_vma_node_verify_access(&qbo->tbo.base.vma_node,
> 					  filp->private_data);
> }
> 
>@@ -295,7 +297,7 @@
> 	if (!qxl_ttm_bo_is_qxl_bo(bo))
> 		return;
> 	qbo = to_qxl_bo(bo);
>-	qdev = qbo->gem_base.dev->dev_private;
>+	qdev = qbo->tbo.base.dev->dev_private;
> 
> 	if (bo->mem.mem_type == TTM_PL_PRIV && qbo->surface_id)
> 		qxl_surface_evict(qdev, qbo, new_mem ? true : false);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/r128/r128_ioc32.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/r128/r128_ioc32.c
>--- linux-5.3-rc6/drivers/gpu/drm/r128/r128_ioc32.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/r128/r128_ioc32.c	2019-08-31 15:01:12.053736185 -0500
>@@ -29,10 +29,11 @@
>  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>  * IN THE SOFTWARE.
>  */
>+
> #include <linux/compat.h>
> 
>-#include <drm/drmP.h>
> #include <drm/r128_drm.h>
>+
> #include "r128_drv.h"
> 
> typedef struct drm_r128_init32 {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/r128/r128_irq.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/r128/r128_irq.c
>--- linux-5.3-rc6/drivers/gpu/drm/r128/r128_irq.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/r128/r128_irq.c	2019-08-31 15:01:12.053736185 -0500
>@@ -30,8 +30,11 @@
>  *    Eric Anholt <anholt@FreeBSD.org>
>  */
> 
>-#include <drm/drmP.h>
>+#include <drm/drm_device.h>
>+#include <drm/drm_print.h>
>+#include <drm/drm_vblank.h>
> #include <drm/r128_drm.h>
>+
> #include "r128_drv.h"
> 
> u32 r128_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_benchmark.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_benchmark.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_benchmark.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_benchmark.c	2019-08-31 15:01:12.053736185 -0500
>@@ -122,7 +122,7 @@
> 	if (rdev->asic->copy.dma) {
> 		time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
> 						RADEON_BENCHMARK_COPY_DMA, n,
>-						dobj->tbo.resv);
>+						dobj->tbo.base.resv);
> 		if (time < 0)
> 			goto out_cleanup;
> 		if (time > 0)
>@@ -133,7 +133,7 @@
> 	if (rdev->asic->copy.blit) {
> 		time = radeon_benchmark_do_move(rdev, size, saddr, daddr,
> 						RADEON_BENCHMARK_COPY_BLIT, n,
>-						dobj->tbo.resv);
>+						dobj->tbo.base.resv);
> 		if (time < 0)
> 			goto out_cleanup;
> 		if (time > 0)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_connectors.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_connectors.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_connectors.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_connectors.c	2019-08-31 15:01:12.054736186 -0500
>@@ -752,7 +752,7 @@
> 
> 		radeon_encoder->output_csc = val;
> 
>-		if (connector->encoder->crtc) {
>+		if (connector->encoder && connector->encoder->crtc) {
> 			struct drm_crtc *crtc  = connector->encoder->crtc;
> 			struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_cs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_cs.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_cs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_cs.c	2019-08-31 15:01:12.054736186 -0500
>@@ -257,7 +257,7 @@
> 	list_for_each_entry(reloc, &p->validated, tv.head) {
> 		struct reservation_object *resv;
> 
>-		resv = reloc->robj->tbo.resv;
>+		resv = reloc->robj->tbo.base.resv;
> 		r = radeon_sync_resv(p->rdev, &p->ib.sync, resv,
> 				     reloc->tv.num_shared);
> 		if (r)
>@@ -443,7 +443,7 @@
> 			if (bo == NULL)
> 				continue;
> 
>-			drm_gem_object_put_unlocked(&bo->gem_base);
>+			drm_gem_object_put_unlocked(&bo->tbo.base);
> 		}
> 	}
> 	kfree(parser->track);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_device.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_device.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_device.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_device.c	2019-08-31 15:01:12.054736186 -0500
>@@ -1365,34 +1365,27 @@
> 	else
> 		rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
> 
>-	/* set DMA mask + need_dma32 flags.
>+	/* set DMA mask.
> 	 * PCIE - can handle 40-bits.
> 	 * IGP - can handle 40-bits
> 	 * AGP - generally dma32 is safest
> 	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
> 	 */
>-	rdev->need_dma32 = false;
>+	dma_bits = 40;
> 	if (rdev->flags & RADEON_IS_AGP)
>-		rdev->need_dma32 = true;
>+		dma_bits = 32;
> 	if ((rdev->flags & RADEON_IS_PCI) &&
> 	    (rdev->family <= CHIP_RS740))
>-		rdev->need_dma32 = true;
>+		dma_bits = 32;
> #ifdef CONFIG_PPC64
> 	if (rdev->family == CHIP_CEDAR)
>-		rdev->need_dma32 = true;
>+		dma_bits = 32;
> #endif
> 
>-	dma_bits = rdev->need_dma32 ? 32 : 40;
>-	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
>+	r = dma_set_mask_and_coherent(&rdev->pdev->dev, DMA_BIT_MASK(dma_bits));
> 	if (r) {
>-		rdev->need_dma32 = true;
>-		dma_bits = 32;
> 		pr_warn("radeon: No suitable DMA available\n");
>-	}
>-	r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
>-	if (r) {
>-		pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
>-		pr_warn("radeon: No coherent DMA available\n");
>+		return r;
> 	}
> 	rdev->need_swiotlb = drm_need_swiotlb(dma_bits);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_display.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_display.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_display.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_display.c	2019-08-31 15:01:12.054736186 -0500
>@@ -275,7 +275,7 @@
> 	} else
> 		DRM_ERROR("failed to reserve buffer after flip\n");
> 
>-	drm_gem_object_put_unlocked(&work->old_rbo->gem_base);
>+	drm_gem_object_put_unlocked(&work->old_rbo->tbo.base);
> 	kfree(work);
> }
> 
>@@ -533,7 +533,7 @@
> 		DRM_ERROR("failed to pin new rbo buffer before flip\n");
> 		goto cleanup;
> 	}
>-	work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
>+	work->fence = dma_fence_get(reservation_object_get_excl(new_rbo->tbo.base.resv));
> 	radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL);
> 	radeon_bo_unreserve(new_rbo);
> 
>@@ -607,7 +607,7 @@
> 	radeon_bo_unreserve(new_rbo);
> 
> cleanup:
>-	drm_gem_object_put_unlocked(&work->old_rbo->gem_base);
>+	drm_gem_object_put_unlocked(&work->old_rbo->tbo.base);
> 	dma_fence_put(work->fence);
> 	kfree(work);
> 	return r;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_drv.c	2019-08-31 15:01:12.055736186 -0500
>@@ -130,8 +130,7 @@
> 				struct drm_file *file_priv);
> void radeon_gem_object_close(struct drm_gem_object *obj,
> 				struct drm_file *file_priv);
>-struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
>-					struct drm_gem_object *gobj,
>+struct dma_buf *radeon_gem_prime_export(struct drm_gem_object *gobj,
> 					int flags);
> extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
> 				      unsigned int flags, int *vpos, int *hpos,
>@@ -153,7 +152,6 @@
> 							struct sg_table *sg);
> int radeon_gem_prime_pin(struct drm_gem_object *obj);
> void radeon_gem_prime_unpin(struct drm_gem_object *obj);
>-struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
> void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
> void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
> 
>@@ -349,24 +347,30 @@
> static void
> radeon_pci_shutdown(struct pci_dev *pdev)
> {
>+	struct drm_device *ddev = pci_get_drvdata(pdev);
>+
> 	/* if we are running in a VM, make sure the device
> 	 * torn down properly on reboot/shutdown
> 	 */
> 	if (radeon_device_is_virtual())
> 		radeon_pci_remove(pdev);
>+
>+	/* Some adapters need to be suspended before a
>+	* shutdown occurs in order to prevent an error
>+	* during kexec.
>+	*/
>+	radeon_suspend_kms(ddev, true, true, false);
> }
> 
> static int radeon_pmops_suspend(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 	return radeon_suspend_kms(drm_dev, true, true, false);
> }
> 
> static int radeon_pmops_resume(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 
> 	/* GPU comes up enabled by the bios on resume */
> 	if (radeon_is_px(drm_dev)) {
>@@ -380,15 +384,13 @@
> 
> static int radeon_pmops_freeze(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 	return radeon_suspend_kms(drm_dev, false, true, true);
> }
> 
> static int radeon_pmops_thaw(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 	return radeon_resume_kms(drm_dev, false, true);
> }
> 
>@@ -447,8 +449,7 @@
> 
> static int radeon_pmops_runtime_idle(struct device *dev)
> {
>-	struct pci_dev *pdev = to_pci_dev(dev);
>-	struct drm_device *drm_dev = pci_get_drvdata(pdev);
>+	struct drm_device *drm_dev = dev_get_drvdata(dev);
> 	struct drm_crtc *crtc;
> 
> 	if (!radeon_is_px(drm_dev)) {
>@@ -539,7 +540,7 @@
> 
> static struct drm_driver kms_driver = {
> 	.driver_features =
>-	    DRIVER_USE_AGP | DRIVER_GEM | DRIVER_PRIME | DRIVER_RENDER,
>+	    DRIVER_USE_AGP | DRIVER_GEM | DRIVER_RENDER,
> 	.load = radeon_driver_load_kms,
> 	.open = radeon_driver_open_kms,
> 	.postclose = radeon_driver_postclose_kms,
>@@ -565,10 +566,8 @@
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> 	.gem_prime_export = radeon_gem_prime_export,
>-	.gem_prime_import = drm_gem_prime_import,
> 	.gem_prime_pin = radeon_gem_prime_pin,
> 	.gem_prime_unpin = radeon_gem_prime_unpin,
>-	.gem_prime_res_obj = radeon_gem_prime_res_obj,
> 	.gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
> 	.gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
> 	.gem_prime_vmap = radeon_gem_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_gem.c	2019-08-31 15:01:12.055736186 -0500
>@@ -83,7 +83,7 @@
> 		}
> 		return r;
> 	}
>-	*obj = &robj->gem_base;
>+	*obj = &robj->tbo.base;
> 	robj->pid = task_pid_nr(current);
> 
> 	mutex_lock(&rdev->gem.mutex);
>@@ -114,7 +114,7 @@
> 	}
> 	if (domain == RADEON_GEM_DOMAIN_CPU) {
> 		/* Asking for cpu access wait for object idle */
>-		r = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ);
>+		r = reservation_object_wait_timeout_rcu(robj->tbo.base.resv, true, true, 30 * HZ);
> 		if (!r)
> 			r = -EBUSY;
> 
>@@ -449,7 +449,7 @@
> 	}
> 	robj = gem_to_radeon_bo(gobj);
> 
>-	r = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
>+	r = reservation_object_test_signaled_rcu(robj->tbo.base.resv, true);
> 	if (r == 0)
> 		r = -EBUSY;
> 	else
>@@ -478,7 +478,7 @@
> 	}
> 	robj = gem_to_radeon_bo(gobj);
> 
>-	ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ);
>+	ret = reservation_object_wait_timeout_rcu(robj->tbo.base.resv, true, true, 30 * HZ);
> 	if (ret == 0)
> 		r = -EBUSY;
> 	else if (ret < 0)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon.h
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon.h	2019-08-31 15:01:12.053736185 -0500
>@@ -505,7 +505,6 @@
> 	struct list_head		va;
> 	/* Constant after initialization */
> 	struct radeon_device		*rdev;
>-	struct drm_gem_object		gem_base;
> 
> 	struct ttm_bo_kmap_obj		dma_buf_vmap;
> 	pid_t				pid;
>@@ -513,7 +512,7 @@
> 	struct radeon_mn		*mn;
> 	struct list_head		mn_list;
> };
>-#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
>+#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base)
> 
> int radeon_gem_debugfs_init(struct radeon_device *rdev);
> 
>@@ -2387,7 +2386,6 @@
> 	struct radeon_wb		wb;
> 	struct radeon_dummy_page	dummy_page;
> 	bool				shutdown;
>-	bool				need_dma32;
> 	bool				need_swiotlb;
> 	bool				accel_working;
> 	bool				fastfb_working; /* IGP feature*/
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_mn.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_mn.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_mn.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_mn.c	2019-08-31 15:01:12.055736186 -0500
>@@ -163,7 +163,7 @@
> 				continue;
> 			}
> 
>-			r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
>+			r = reservation_object_wait_timeout_rcu(bo->tbo.base.resv,
> 				true, false, MAX_SCHEDULE_TIMEOUT);
> 			if (r <= 0)
> 				DRM_ERROR("(%ld) failed to wait for user bo\n", r);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_object.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_object.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_object.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_object.c	2019-08-31 15:01:12.055736186 -0500
>@@ -85,9 +85,9 @@
> 	mutex_unlock(&bo->rdev->gem.mutex);
> 	radeon_bo_clear_surface_reg(bo);
> 	WARN_ON_ONCE(!list_empty(&bo->va));
>-	if (bo->gem_base.import_attach)
>-		drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
>-	drm_gem_object_release(&bo->gem_base);
>+	if (bo->tbo.base.import_attach)
>+		drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
>+	drm_gem_object_release(&bo->tbo.base);
> 	kfree(bo);
> }
> 
>@@ -209,7 +209,7 @@
> 	bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
> 	if (bo == NULL)
> 		return -ENOMEM;
>-	drm_gem_private_object_init(rdev->ddev, &bo->gem_base, size);
>+	drm_gem_private_object_init(rdev->ddev, &bo->tbo.base, size);
> 	bo->rdev = rdev;
> 	bo->surface_reg = -1;
> 	INIT_LIST_HEAD(&bo->list);
>@@ -442,13 +442,13 @@
> 	dev_err(rdev->dev, "Userspace still has active objects !\n");
> 	list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
> 		dev_err(rdev->dev, "%p %p %lu %lu force free\n",
>-			&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
>-			*((unsigned long *)&bo->gem_base.refcount));
>+			&bo->tbo.base, bo, (unsigned long)bo->tbo.base.size,
>+			*((unsigned long *)&bo->tbo.base.refcount));
> 		mutex_lock(&bo->rdev->gem.mutex);
> 		list_del_init(&bo->list);
> 		mutex_unlock(&bo->rdev->gem.mutex);
> 		/* this should unref the ttm bo */
>-		drm_gem_object_put_unlocked(&bo->gem_base);
>+		drm_gem_object_put_unlocked(&bo->tbo.base);
> 	}
> }
> 
>@@ -610,7 +610,7 @@
> 	int steal;
> 	int i;
> 
>-	lockdep_assert_held(&bo->tbo.resv->lock.base);
>+	reservation_object_assert_held(bo->tbo.base.resv);
> 
> 	if (!bo->tiling_flags)
> 		return 0;
>@@ -736,7 +736,7 @@
> 				uint32_t *tiling_flags,
> 				uint32_t *pitch)
> {
>-	lockdep_assert_held(&bo->tbo.resv->lock.base);
>+	reservation_object_assert_held(bo->tbo.base.resv);
> 
> 	if (tiling_flags)
> 		*tiling_flags = bo->tiling_flags;
>@@ -748,7 +748,7 @@
> 				bool force_drop)
> {
> 	if (!force_drop)
>-		lockdep_assert_held(&bo->tbo.resv->lock.base);
>+		reservation_object_assert_held(bo->tbo.base.resv);
> 
> 	if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
> 		return 0;
>@@ -870,7 +870,7 @@
> void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
> 		     bool shared)
> {
>-	struct reservation_object *resv = bo->tbo.resv;
>+	struct reservation_object *resv = bo->tbo.base.resv;
> 
> 	if (shared)
> 		reservation_object_add_shared_fence(resv, &fence->base);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_object.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_object.h
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_object.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_object.h	2019-08-31 15:01:12.055736186 -0500
>@@ -116,7 +116,7 @@
>  */
> static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo)
> {
>-	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
>+	return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
> }
> 
> extern int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_prime.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_prime.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_prime.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_prime.c	2019-08-31 15:01:12.055736186 -0500
>@@ -68,10 +68,10 @@
> 	struct radeon_bo *bo;
> 	int ret;
> 
>-	ww_mutex_lock(&resv->lock, NULL);
>+	reservation_object_lock(resv, NULL);
> 	ret = radeon_bo_create(rdev, attach->dmabuf->size, PAGE_SIZE, false,
> 			       RADEON_GEM_DOMAIN_GTT, 0, sg, resv, &bo);
>-	ww_mutex_unlock(&resv->lock);
>+	reservation_object_unlock(resv);
> 	if (ret)
> 		return ERR_PTR(ret);
> 
>@@ -80,7 +80,7 @@
> 	mutex_unlock(&rdev->gem.mutex);
> 
> 	bo->prime_shared_count = 1;
>-	return &bo->gem_base;
>+	return &bo->tbo.base;
> }
> 
> int radeon_gem_prime_pin(struct drm_gem_object *obj)
>@@ -117,19 +117,11 @@
> }
> 
> 
>-struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *obj)
>-{
>-	struct radeon_bo *bo = gem_to_radeon_bo(obj);
>-
>-	return bo->tbo.resv;
>-}
>-
>-struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
>-					struct drm_gem_object *gobj,
>+struct dma_buf *radeon_gem_prime_export(struct drm_gem_object *gobj,
> 					int flags)
> {
> 	struct radeon_bo *bo = gem_to_radeon_bo(gobj);
> 	if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
> 		return ERR_PTR(-EPERM);
>-	return drm_gem_prime_export(dev, gobj, flags);
>+	return drm_gem_prime_export(gobj, flags);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_test.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_test.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_test.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_test.c	2019-08-31 15:01:12.055736186 -0500
>@@ -120,11 +120,11 @@
> 		if (ring == R600_RING_TYPE_DMA_INDEX)
> 			fence = radeon_copy_dma(rdev, gtt_addr, vram_addr,
> 						size / RADEON_GPU_PAGE_SIZE,
>-						vram_obj->tbo.resv);
>+						vram_obj->tbo.base.resv);
> 		else
> 			fence = radeon_copy_blit(rdev, gtt_addr, vram_addr,
> 						 size / RADEON_GPU_PAGE_SIZE,
>-						 vram_obj->tbo.resv);
>+						 vram_obj->tbo.base.resv);
> 		if (IS_ERR(fence)) {
> 			DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
> 			r = PTR_ERR(fence);
>@@ -171,11 +171,11 @@
> 		if (ring == R600_RING_TYPE_DMA_INDEX)
> 			fence = radeon_copy_dma(rdev, vram_addr, gtt_addr,
> 						size / RADEON_GPU_PAGE_SIZE,
>-						vram_obj->tbo.resv);
>+						vram_obj->tbo.base.resv);
> 		else
> 			fence = radeon_copy_blit(rdev, vram_addr, gtt_addr,
> 						 size / RADEON_GPU_PAGE_SIZE,
>-						 vram_obj->tbo.resv);
>+						 vram_obj->tbo.base.resv);
> 		if (IS_ERR(fence)) {
> 			DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
> 			r = PTR_ERR(fence);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_ttm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_ttm.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_ttm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_ttm.c	2019-08-31 15:01:12.055736186 -0500
>@@ -184,7 +184,7 @@
> 
> 	if (radeon_ttm_tt_has_userptr(bo->ttm))
> 		return -EPERM;
>-	return drm_vma_node_verify_access(&rbo->gem_base.vma_node,
>+	return drm_vma_node_verify_access(&rbo->tbo.base.vma_node,
> 					  filp->private_data);
> }
> 
>@@ -244,7 +244,7 @@
> 	BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
> 
> 	num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
>-	fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
>+	fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv);
> 	if (IS_ERR(fence))
> 		return PTR_ERR(fence);
> 
>@@ -794,7 +794,7 @@
> 	r = ttm_bo_device_init(&rdev->mman.bdev,
> 			       &radeon_bo_driver,
> 			       rdev->ddev->anon_inode->i_mapping,
>-			       rdev->need_dma32);
>+			       dma_addressing_limited(&rdev->pdev->dev));
> 	if (r) {
> 		DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
> 		return r;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_uvd.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_uvd.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_uvd.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_uvd.c	2019-08-31 15:01:12.055736186 -0500
>@@ -477,7 +477,7 @@
> 		return -EINVAL;
> 	}
> 
>-	f = reservation_object_get_excl(bo->tbo.resv);
>+	f = reservation_object_get_excl(bo->tbo.base.resv);
> 	if (f) {
> 		r = radeon_fence_wait((struct radeon_fence *)f, false);
> 		if (r) {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_vm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_vm.c
>--- linux-5.3-rc6/drivers/gpu/drm/radeon/radeon_vm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/radeon/radeon_vm.c	2019-08-31 15:01:12.056736186 -0500
>@@ -702,7 +702,7 @@
> 	if (ib.length_dw != 0) {
> 		radeon_asic_vm_pad_ib(rdev, &ib);
> 
>-		radeon_sync_resv(rdev, &ib.sync, pd->tbo.resv, true);
>+		radeon_sync_resv(rdev, &ib.sync, pd->tbo.base.resv, true);
> 		WARN_ON(ib.length_dw > ndw);
> 		r = radeon_ib_schedule(rdev, &ib, NULL, false);
> 		if (r) {
>@@ -830,8 +830,8 @@
> 		uint64_t pte;
> 		int r;
> 
>-		radeon_sync_resv(rdev, &ib->sync, pt->tbo.resv, true);
>-		r = reservation_object_reserve_shared(pt->tbo.resv, 1);
>+		radeon_sync_resv(rdev, &ib->sync, pt->tbo.base.resv, true);
>+		r = reservation_object_reserve_shared(pt->tbo.base.resv, 1);
> 		if (r)
> 			return r;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rcar-du/rcar_du_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rcar-du/rcar_du_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/rcar-du/rcar_du_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rcar-du/rcar_du_drv.c	2019-08-31 15:01:12.056736186 -0500
>@@ -441,14 +441,11 @@
> DEFINE_DRM_GEM_CMA_FOPS(rcar_du_fops);
> 
> static struct drm_driver rcar_du_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME
>-				| DRIVER_ATOMIC,
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.gem_free_object_unlocked = drm_gem_cma_free_object,
> 	.gem_vm_ops		= &drm_gem_cma_vm_ops,
> 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
>-	.gem_prime_import	= drm_gem_prime_import,
>-	.gem_prime_export	= drm_gem_prime_export,
> 	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c	2019-08-31 15:01:12.235736202 -0500
>@@ -16,19 +16,18 @@
> #include <linux/reset.h>
> #include <linux/clk.h>
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_dp_helper.h>
>-#include <drm/drm_of.h>
>-#include <drm/drm_panel.h>
>-#include <drm/drm_probe_helper.h>
>-
> #include <video/of_videomode.h>
> #include <video/videomode.h>
> 
>+#include <drm/drm_atomic.h>
>+#include <drm/drm_atomic_helper.h>
> #include <drm/bridge/analogix_dp.h>
>+#include <drm/drm_dp_helper.h>
>+#include <drm/drm_of.h>
>+#include <drm/drm_panel.h>
>+#include <drm/drm_probe_helper.h>
> 
> #include "rockchip_drm_drv.h"
>-#include "rockchip_drm_psr.h"
> #include "rockchip_drm_vop.h"
> 
> #define RK3288_GRF_SOC_CON6		0x25c
>@@ -73,29 +72,6 @@
> 	struct analogix_dp_plat_data plat_data;
> };
> 
>-static int analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
>-{
>-	struct rockchip_dp_device *dp = to_dp(encoder);
>-	int ret;
>-
>-	if (!analogix_dp_psr_enabled(dp->adp))
>-		return 0;
>-
>-	DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
>-
>-	ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
>-					 PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
>-	if (ret) {
>-		DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");
>-		return -ETIMEDOUT;
>-	}
>-
>-	if (enabled)
>-		return analogix_dp_enable_psr(dp->adp);
>-	else
>-		return analogix_dp_disable_psr(dp->adp);
>-}
>-
> static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
> {
> 	reset_control_assert(dp->rst);
>@@ -126,21 +102,9 @@
> 	return ret;
> }
> 
>-static int rockchip_dp_poweron_end(struct analogix_dp_plat_data *plat_data)
>-{
>-	struct rockchip_dp_device *dp = to_dp(plat_data);
>-
>-	return rockchip_drm_psr_inhibit_put(&dp->encoder);
>-}
>-
> static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
> {
> 	struct rockchip_dp_device *dp = to_dp(plat_data);
>-	int ret;
>-
>-	ret = rockchip_drm_psr_inhibit_get(&dp->encoder);
>-	if (ret != 0)
>-		return ret;
> 
> 	clk_disable_unprepare(dp->pclk);
> 
>@@ -180,12 +144,42 @@
> 	/* do nothing */
> }
> 
>-static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
>+static
>+struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder,
>+					      struct drm_atomic_state *state)
>+{
>+	struct drm_connector *connector;
>+	struct drm_connector_state *conn_state;
>+
>+	connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
>+	if (!connector)
>+		return NULL;
>+
>+	conn_state = drm_atomic_get_new_connector_state(state, connector);
>+	if (!conn_state)
>+		return NULL;
>+
>+	return conn_state->crtc;
>+}
>+
>+static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
>+					   struct drm_atomic_state *state)
> {
> 	struct rockchip_dp_device *dp = to_dp(encoder);
>+	struct drm_crtc *crtc;
>+	struct drm_crtc_state *old_crtc_state;
> 	int ret;
> 	u32 val;
> 
>+	crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
>+	if (!crtc)
>+		return;
>+
>+	old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
>+	/* Coming back from self refresh, nothing to do */
>+	if (old_crtc_state && old_crtc_state->self_refresh_active)
>+		return;
>+
> 	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
> 	if (ret < 0)
> 		return;
>@@ -210,9 +204,27 @@
> 	clk_disable_unprepare(dp->grfclk);
> }
> 
>-static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
>+static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
>+					    struct drm_atomic_state *state)
> {
>-	/* do nothing */
>+	struct rockchip_dp_device *dp = to_dp(encoder);
>+	struct drm_crtc *crtc;
>+	struct drm_crtc_state *new_crtc_state = NULL;
>+	int ret;
>+
>+	crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
>+	/* No crtc means we're doing a full shutdown */
>+	if (!crtc)
>+		return;
>+
>+	new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
>+	/* If we're not entering self-refresh, no need to wait for vact */
>+	if (!new_crtc_state || !new_crtc_state->self_refresh_active)
>+		return;
>+
>+	ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
>+	if (ret)
>+		DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n");
> }
> 
> static int
>@@ -241,8 +253,8 @@
> static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
> 	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
> 	.mode_set = rockchip_dp_drm_encoder_mode_set,
>-	.enable = rockchip_dp_drm_encoder_enable,
>-	.disable = rockchip_dp_drm_encoder_nop,
>+	.atomic_enable = rockchip_dp_drm_encoder_enable,
>+	.atomic_disable = rockchip_dp_drm_encoder_disable,
> 	.atomic_check = rockchip_dp_drm_encoder_atomic_check,
> };
> 
>@@ -334,23 +346,16 @@
> 
> 	dp->plat_data.dev_type = dp->data->chip_type;
> 	dp->plat_data.power_on_start = rockchip_dp_poweron_start;
>-	dp->plat_data.power_on_end = rockchip_dp_poweron_end;
> 	dp->plat_data.power_off = rockchip_dp_powerdown;
> 	dp->plat_data.get_modes = rockchip_dp_get_modes;
> 
>-	ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
>-	if (ret < 0)
>-		goto err_cleanup_encoder;
>-
> 	dp->adp = analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
> 	if (IS_ERR(dp->adp)) {
> 		ret = PTR_ERR(dp->adp);
>-		goto err_unreg_psr;
>+		goto err_cleanup_encoder;
> 	}
> 
> 	return 0;
>-err_unreg_psr:
>-	rockchip_drm_psr_unregister(&dp->encoder);
> err_cleanup_encoder:
> 	dp->encoder.funcs->destroy(&dp->encoder);
> 	return ret;
>@@ -362,7 +367,6 @@
> 	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
> 
> 	analogix_dp_unbind(dp->adp);
>-	rockchip_drm_psr_unregister(&dp->encoder);
> 	dp->encoder.funcs->destroy(&dp->encoder);
> 
> 	dp->adp = ERR_PTR(-ENODEV);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/cdn-dp-core.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/cdn-dp-core.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/cdn-dp-core.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/cdn-dp-core.c	2019-08-31 15:01:12.056736186 -0500
>@@ -4,24 +4,23 @@
>  * Author: Chris Zhong <zyw@rock-chips.com>
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_dp_helper.h>
>-#include <drm/drm_edid.h>
>-#include <drm/drm_of.h>
>-#include <drm/drm_probe_helper.h>
>-
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/extcon.h>
> #include <linux/firmware.h>
>-#include <linux/regmap.h>
>-#include <linux/reset.h>
> #include <linux/mfd/syscon.h>
> #include <linux/phy/phy.h>
>+#include <linux/regmap.h>
>+#include <linux/reset.h>
> 
> #include <sound/hdmi-codec.h>
> 
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_dp_helper.h>
>+#include <drm/drm_edid.h>
>+#include <drm/drm_of.h>
>+#include <drm/drm_probe_helper.h>
>+
> #include "cdn-dp-core.h"
> #include "cdn-dp-reg.h"
> #include "rockchip_drm_vop.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/cdn-dp-core.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/cdn-dp-core.h
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/cdn-dp-core.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/cdn-dp-core.h	2019-08-31 15:01:12.056736186 -0500
>@@ -7,10 +7,10 @@
> #ifndef _CDN_DP_CORE_H
> #define _CDN_DP_CORE_H
> 
>-#include <drm/drmP.h>
> #include <drm/drm_dp_helper.h>
> #include <drm/drm_panel.h>
> #include <drm/drm_probe_helper.h>
>+
> #include "rockchip_drm_drv.h"
> 
> #define MAX_PHY		2
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c	2019-08-31 15:01:12.056736186 -0500
>@@ -10,11 +10,10 @@
> #include <linux/phy/phy.h>
> #include <linux/regmap.h>
> 
>-#include <drm/drm_of.h>
>-#include <drm/drmP.h>
>+#include <drm/bridge/dw_hdmi.h>
> #include <drm/drm_edid.h>
>+#include <drm/drm_of.h>
> #include <drm/drm_probe_helper.h>
>-#include <drm/bridge/dw_hdmi.h>
> 
> #include "rockchip_drm_drv.h"
> #include "rockchip_drm_vop.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c	2019-08-31 15:01:12.056736186 -0500
>@@ -6,10 +6,6 @@
>  *      Nickey Yang <nickey.yang@rock-chips.com>
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_mipi_dsi.h>
>-#include <drm/bridge/dw_mipi_dsi.h>
>-#include <drm/drm_of.h>
> #include <linux/clk.h>
> #include <linux/iopoll.h>
> #include <linux/math64.h>
>@@ -18,8 +14,13 @@
> #include <linux/of_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
>+
> #include <video/mipi_display.h>
> 
>+#include <drm/bridge/dw_mipi_dsi.h>
>+#include <drm/drm_mipi_dsi.h>
>+#include <drm/drm_of.h>
>+
> #include "rockchip_drm_drv.h"
> #include "rockchip_drm_vop.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/inno_hdmi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/inno_hdmi.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/inno_hdmi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/inno_hdmi.c	2019-08-31 15:01:12.056736186 -0500
>@@ -15,10 +15,9 @@
> #include <linux/mutex.h>
> #include <linux/of_device.h>
> 
>-#include <drm/drm_of.h>
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_edid.h>
>+#include <drm/drm_of.h>
> #include <drm/drm_probe_helper.h>
> 
> #include "rockchip_drm_drv.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/Makefile	2019-08-31 15:01:12.056736186 -0500
>@@ -4,8 +4,7 @@
> # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
> 
> rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
>-		rockchip_drm_gem.o rockchip_drm_psr.o \
>-		rockchip_drm_vop.o rockchip_vop_reg.o
>+		rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o
> rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
> 
> rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_drv.c	2019-08-31 15:01:12.056736186 -0500
>@@ -6,11 +6,6 @@
>  * based on exynos_drm_drv.c
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_gem_cma_helper.h>
>-#include <drm/drm_of.h>
>-#include <drm/drm_probe_helper.h>
> #include <linux/dma-mapping.h>
> #include <linux/dma-iommu.h>
> #include <linux/pm_runtime.h>
>@@ -21,6 +16,13 @@
> #include <linux/console.h>
> #include <linux/iommu.h>
> 
>+#include <drm/drm_drv.h>
>+#include <drm/drm_fb_helper.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_of.h>
>+#include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
>+
> #include "rockchip_drm_drv.h"
> #include "rockchip_drm_fb.h"
> #include "rockchip_drm_fbdev.h"
>@@ -212,16 +214,13 @@
> };
> 
> static struct drm_driver rockchip_drm_driver = {
>-	.driver_features	= DRIVER_MODESET | DRIVER_GEM |
>-				  DRIVER_PRIME | DRIVER_ATOMIC,
>+	.driver_features	= DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> 	.lastclose		= drm_fb_helper_lastclose,
> 	.gem_vm_ops		= &drm_gem_cma_vm_ops,
> 	.gem_free_object_unlocked = rockchip_gem_free_object,
> 	.dumb_create		= rockchip_gem_dumb_create,
> 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
>-	.gem_prime_import	= drm_gem_prime_import,
>-	.gem_prime_export	= drm_gem_prime_export,
> 	.gem_prime_get_sg_table	= rockchip_gem_prime_get_sg_table,
> 	.gem_prime_import_sg_table	= rockchip_gem_prime_import_sg_table,
> 	.gem_prime_vmap		= rockchip_gem_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_fb.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_fb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_fb.c	2019-08-31 15:01:12.056736186 -0500
>@@ -5,18 +5,18 @@
>  */
> 
> #include <linux/kernel.h>
>+
> #include <drm/drm.h>
>-#include <drm/drmP.h>
> #include <drm/drm_atomic.h>
> #include <drm/drm_damage_helper.h>
> #include <drm/drm_fb_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_probe_helper.h>
> 
> #include "rockchip_drm_drv.h"
> #include "rockchip_drm_fb.h"
> #include "rockchip_drm_gem.h"
>-#include "rockchip_drm_psr.h"
> 
> static const struct drm_framebuffer_funcs rockchip_drm_fb_funcs = {
> 	.destroy       = drm_gem_fb_destroy,
>@@ -105,31 +105,8 @@
> 	return ERR_PTR(ret);
> }
> 
>-static void
>-rockchip_atomic_helper_commit_tail_rpm(struct drm_atomic_state *old_state)
>-{
>-	struct drm_device *dev = old_state->dev;
>-
>-	rockchip_drm_psr_inhibit_get_state(old_state);
>-
>-	drm_atomic_helper_commit_modeset_disables(dev, old_state);
>-
>-	drm_atomic_helper_commit_modeset_enables(dev, old_state);
>-
>-	drm_atomic_helper_commit_planes(dev, old_state,
>-					DRM_PLANE_COMMIT_ACTIVE_ONLY);
>-
>-	rockchip_drm_psr_inhibit_put_state(old_state);
>-
>-	drm_atomic_helper_commit_hw_done(old_state);
>-
>-	drm_atomic_helper_wait_for_vblanks(dev, old_state);
>-
>-	drm_atomic_helper_cleanup_planes(dev, old_state);
>-}
>-
> static const struct drm_mode_config_helper_funcs rockchip_mode_config_helpers = {
>-	.atomic_commit_tail = rockchip_atomic_helper_commit_tail_rpm,
>+	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
> };
> 
> static const struct drm_mode_config_funcs rockchip_drm_mode_config_funcs = {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c	2019-08-31 15:01:12.056736186 -0500
>@@ -5,8 +5,8 @@
>  */
> 
> #include <drm/drm.h>
>-#include <drm/drmP.h>
> #include <drm/drm_fb_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_probe_helper.h>
> 
> #include "rockchip_drm_drv.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_gem.c	2019-08-31 15:01:12.057736186 -0500
>@@ -4,14 +4,14 @@
>  * Author:Mark Yao <mark.yao@rock-chips.com>
>  */
> 
>+#include <linux/dma-buf.h>
>+#include <linux/iommu.h>
>+
> #include <drm/drm.h>
>-#include <drm/drmP.h>
> #include <drm/drm_gem.h>
>+#include <drm/drm_prime.h>
> #include <drm/drm_vma_manager.h>
> 
>-#include <linux/dma-buf.h>
>-#include <linux/iommu.h>
>-
> #include "rockchip_drm_drv.h"
> #include "rockchip_drm_gem.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_psr.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_psr.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_psr.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,282 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0-only
>-/*
>- * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
>- * Author: Yakir Yang <ykk@rock-chips.com>
>- */
>-
>-#include <drm/drmP.h>
>-#include <drm/drm_atomic.h>
>-#include <drm/drm_probe_helper.h>
>-
>-#include "rockchip_drm_drv.h"
>-#include "rockchip_drm_psr.h"
>-
>-#define PSR_FLUSH_TIMEOUT_MS	100
>-
>-struct psr_drv {
>-	struct list_head	list;
>-	struct drm_encoder	*encoder;
>-
>-	struct mutex		lock;
>-	int			inhibit_count;
>-	bool			enabled;
>-
>-	struct delayed_work	flush_work;
>-
>-	int (*set)(struct drm_encoder *encoder, bool enable);
>-};
>-
>-static struct psr_drv *find_psr_by_encoder(struct drm_encoder *encoder)
>-{
>-	struct rockchip_drm_private *drm_drv = encoder->dev->dev_private;
>-	struct psr_drv *psr;
>-
>-	mutex_lock(&drm_drv->psr_list_lock);
>-	list_for_each_entry(psr, &drm_drv->psr_list, list) {
>-		if (psr->encoder == encoder)
>-			goto out;
>-	}
>-	psr = ERR_PTR(-ENODEV);
>-
>-out:
>-	mutex_unlock(&drm_drv->psr_list_lock);
>-	return psr;
>-}
>-
>-static int psr_set_state_locked(struct psr_drv *psr, bool enable)
>-{
>-	int ret;
>-
>-	if (psr->inhibit_count > 0)
>-		return -EINVAL;
>-
>-	if (enable == psr->enabled)
>-		return 0;
>-
>-	ret = psr->set(psr->encoder, enable);
>-	if (ret)
>-		return ret;
>-
>-	psr->enabled = enable;
>-	return 0;
>-}
>-
>-static void psr_flush_handler(struct work_struct *work)
>-{
>-	struct psr_drv *psr = container_of(to_delayed_work(work),
>-					   struct psr_drv, flush_work);
>-
>-	mutex_lock(&psr->lock);
>-	psr_set_state_locked(psr, true);
>-	mutex_unlock(&psr->lock);
>-}
>-
>-/**
>- * rockchip_drm_psr_inhibit_put - release PSR inhibit on given encoder
>- * @encoder: encoder to obtain the PSR encoder
>- *
>- * Decrements PSR inhibit count on given encoder. Should be called only
>- * for a PSR inhibit count increment done before. If PSR inhibit counter
>- * reaches zero, PSR flush work is scheduled to make the hardware enter
>- * PSR mode in PSR_FLUSH_TIMEOUT_MS.
>- *
>- * Returns:
>- * Zero on success, negative errno on failure.
>- */
>-int rockchip_drm_psr_inhibit_put(struct drm_encoder *encoder)
>-{
>-	struct psr_drv *psr = find_psr_by_encoder(encoder);
>-
>-	if (IS_ERR(psr))
>-		return PTR_ERR(psr);
>-
>-	mutex_lock(&psr->lock);
>-	--psr->inhibit_count;
>-	WARN_ON(psr->inhibit_count < 0);
>-	if (!psr->inhibit_count)
>-		mod_delayed_work(system_wq, &psr->flush_work,
>-				 PSR_FLUSH_TIMEOUT_MS);
>-	mutex_unlock(&psr->lock);
>-
>-	return 0;
>-}
>-EXPORT_SYMBOL(rockchip_drm_psr_inhibit_put);
>-
>-void rockchip_drm_psr_inhibit_get_state(struct drm_atomic_state *state)
>-{
>-	struct drm_crtc *crtc;
>-	struct drm_crtc_state *crtc_state;
>-	struct drm_encoder *encoder;
>-	u32 encoder_mask = 0;
>-	int i;
>-
>-	for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
>-		encoder_mask |= crtc_state->encoder_mask;
>-		encoder_mask |= crtc->state->encoder_mask;
>-	}
>-
>-	drm_for_each_encoder_mask(encoder, state->dev, encoder_mask)
>-		rockchip_drm_psr_inhibit_get(encoder);
>-}
>-EXPORT_SYMBOL(rockchip_drm_psr_inhibit_get_state);
>-
>-void rockchip_drm_psr_inhibit_put_state(struct drm_atomic_state *state)
>-{
>-	struct drm_crtc *crtc;
>-	struct drm_crtc_state *crtc_state;
>-	struct drm_encoder *encoder;
>-	u32 encoder_mask = 0;
>-	int i;
>-
>-	for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
>-		encoder_mask |= crtc_state->encoder_mask;
>-		encoder_mask |= crtc->state->encoder_mask;
>-	}
>-
>-	drm_for_each_encoder_mask(encoder, state->dev, encoder_mask)
>-		rockchip_drm_psr_inhibit_put(encoder);
>-}
>-EXPORT_SYMBOL(rockchip_drm_psr_inhibit_put_state);
>-
>-/**
>- * rockchip_drm_psr_inhibit_get - acquire PSR inhibit on given encoder
>- * @encoder: encoder to obtain the PSR encoder
>- *
>- * Increments PSR inhibit count on given encoder. This function guarantees
>- * that after it returns PSR is turned off on given encoder and no PSR-related
>- * hardware state change occurs at least until a matching call to
>- * rockchip_drm_psr_inhibit_put() is done.
>- *
>- * Returns:
>- * Zero on success, negative errno on failure.
>- */
>-int rockchip_drm_psr_inhibit_get(struct drm_encoder *encoder)
>-{
>-	struct psr_drv *psr = find_psr_by_encoder(encoder);
>-
>-	if (IS_ERR(psr))
>-		return PTR_ERR(psr);
>-
>-	mutex_lock(&psr->lock);
>-	psr_set_state_locked(psr, false);
>-	++psr->inhibit_count;
>-	mutex_unlock(&psr->lock);
>-	cancel_delayed_work_sync(&psr->flush_work);
>-
>-	return 0;
>-}
>-EXPORT_SYMBOL(rockchip_drm_psr_inhibit_get);
>-
>-static void rockchip_drm_do_flush(struct psr_drv *psr)
>-{
>-	cancel_delayed_work_sync(&psr->flush_work);
>-
>-	mutex_lock(&psr->lock);
>-	if (!psr_set_state_locked(psr, false))
>-		mod_delayed_work(system_wq, &psr->flush_work,
>-				 PSR_FLUSH_TIMEOUT_MS);
>-	mutex_unlock(&psr->lock);
>-}
>-
>-/**
>- * rockchip_drm_psr_flush_all - force to flush all registered PSR encoders
>- * @dev: drm device
>- *
>- * Disable the PSR function for all registered encoders, and then enable the
>- * PSR function back after PSR_FLUSH_TIMEOUT. If encoder PSR state have been
>- * changed during flush time, then keep the state no change after flush
>- * timeout.
>- *
>- * Returns:
>- * Zero on success, negative errno on failure.
>- */
>-void rockchip_drm_psr_flush_all(struct drm_device *dev)
>-{
>-	struct rockchip_drm_private *drm_drv = dev->dev_private;
>-	struct psr_drv *psr;
>-
>-	mutex_lock(&drm_drv->psr_list_lock);
>-	list_for_each_entry(psr, &drm_drv->psr_list, list)
>-		rockchip_drm_do_flush(psr);
>-	mutex_unlock(&drm_drv->psr_list_lock);
>-}
>-EXPORT_SYMBOL(rockchip_drm_psr_flush_all);
>-
>-/**
>- * rockchip_drm_psr_register - register encoder to psr driver
>- * @encoder: encoder that obtain the PSR function
>- * @psr_set: call back to set PSR state
>- *
>- * The function returns with PSR inhibit counter initialized with one
>- * and the caller (typically encoder driver) needs to call
>- * rockchip_drm_psr_inhibit_put() when it becomes ready to accept PSR
>- * enable request.
>- *
>- * Returns:
>- * Zero on success, negative errno on failure.
>- */
>-int rockchip_drm_psr_register(struct drm_encoder *encoder,
>-			int (*psr_set)(struct drm_encoder *, bool enable))
>-{
>-	struct rockchip_drm_private *drm_drv;
>-	struct psr_drv *psr;
>-
>-	if (!encoder || !psr_set)
>-		return -EINVAL;
>-
>-	drm_drv = encoder->dev->dev_private;
>-
>-	psr = kzalloc(sizeof(struct psr_drv), GFP_KERNEL);
>-	if (!psr)
>-		return -ENOMEM;
>-
>-	INIT_DELAYED_WORK(&psr->flush_work, psr_flush_handler);
>-	mutex_init(&psr->lock);
>-
>-	psr->inhibit_count = 1;
>-	psr->enabled = false;
>-	psr->encoder = encoder;
>-	psr->set = psr_set;
>-
>-	mutex_lock(&drm_drv->psr_list_lock);
>-	list_add_tail(&psr->list, &drm_drv->psr_list);
>-	mutex_unlock(&drm_drv->psr_list_lock);
>-
>-	return 0;
>-}
>-EXPORT_SYMBOL(rockchip_drm_psr_register);
>-
>-/**
>- * rockchip_drm_psr_unregister - unregister encoder to psr driver
>- * @encoder: encoder that obtain the PSR function
>- * @psr_set: call back to set PSR state
>- *
>- * It is expected that the PSR inhibit counter is 1 when this function is
>- * called, which corresponds to a state when related encoder has been
>- * disconnected from any CRTCs and its driver called
>- * rockchip_drm_psr_inhibit_get() to stop the PSR logic.
>- *
>- * Returns:
>- * Zero on success, negative errno on failure.
>- */
>-void rockchip_drm_psr_unregister(struct drm_encoder *encoder)
>-{
>-	struct rockchip_drm_private *drm_drv = encoder->dev->dev_private;
>-	struct psr_drv *psr, *n;
>-
>-	mutex_lock(&drm_drv->psr_list_lock);
>-	list_for_each_entry_safe(psr, n, &drm_drv->psr_list, list) {
>-		if (psr->encoder == encoder) {
>-			/*
>-			 * Any other value would mean that the encoder
>-			 * is still in use.
>-			 */
>-			WARN_ON(psr->inhibit_count != 1);
>-
>-			list_del(&psr->list);
>-			kfree(psr);
>-		}
>-	}
>-	mutex_unlock(&drm_drv->psr_list_lock);
>-}
>-EXPORT_SYMBOL(rockchip_drm_psr_unregister);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_psr.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_psr.h
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_psr.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_psr.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,22 +0,0 @@
>-/* SPDX-License-Identifier: GPL-2.0-only */
>-/*
>- * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
>- * Author: Yakir Yang <ykk@rock-chips.com>
>- */
>-
>-#ifndef __ROCKCHIP_DRM_PSR___
>-#define __ROCKCHIP_DRM_PSR___
>-
>-void rockchip_drm_psr_flush_all(struct drm_device *dev);
>-
>-int rockchip_drm_psr_inhibit_put(struct drm_encoder *encoder);
>-int rockchip_drm_psr_inhibit_get(struct drm_encoder *encoder);
>-
>-void rockchip_drm_psr_inhibit_get_state(struct drm_atomic_state *state);
>-void rockchip_drm_psr_inhibit_put_state(struct drm_atomic_state *state);
>-
>-int rockchip_drm_psr_register(struct drm_encoder *encoder,
>-			int (*psr_set)(struct drm_encoder *, bool enable));
>-void rockchip_drm_psr_unregister(struct drm_encoder *encoder);
>-
>-#endif /* __ROCKCHIP_DRM_PSR__ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_vop.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_drm_vop.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_drm_vop.c	2019-08-31 15:01:12.057736186 -0500
>@@ -4,40 +4,43 @@
>  * Author:Mark Yao <mark.yao@rock-chips.com>
>  */
> 
>+#include <linux/clk.h>
>+#include <linux/component.h>
>+#include <linux/delay.h>
>+#include <linux/iopoll.h>
>+#include <linux/kernel.h>
>+#include <linux/module.h>
>+#include <linux/of.h>
>+#include <linux/of_device.h>
>+#include <linux/overflow.h>
>+#include <linux/platform_device.h>
>+#include <linux/pm_runtime.h>
>+#include <linux/reset.h>
>+
> #include <drm/drm.h>
>-#include <drm/drmP.h>
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_uapi.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_flip_work.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_self_refresh_helper.h>
>+#include <drm/drm_vblank.h>
>+
> #ifdef CONFIG_DRM_ANALOGIX_DP
> #include <drm/bridge/analogix_dp.h>
> #endif
> 
>-#include <linux/kernel.h>
>-#include <linux/module.h>
>-#include <linux/platform_device.h>
>-#include <linux/clk.h>
>-#include <linux/iopoll.h>
>-#include <linux/of.h>
>-#include <linux/of_device.h>
>-#include <linux/pm_runtime.h>
>-#include <linux/component.h>
>-#include <linux/overflow.h>
>-
>-#include <linux/reset.h>
>-#include <linux/delay.h>
>-
> #include "rockchip_drm_drv.h"
> #include "rockchip_drm_gem.h"
> #include "rockchip_drm_fb.h"
>-#include "rockchip_drm_psr.h"
> #include "rockchip_drm_vop.h"
> #include "rockchip_rgb.h"
> 
>+#define VOP_SELF_REFRESH_ENTRY_DELAY_MS 100
>+
> #define VOP_WIN_SET(vop, win, name, v) \
> 		vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
> #define VOP_SCL_SET(vop, win, name, v) \
>@@ -79,7 +82,7 @@
> 		vop_get_intr_type(vop, &vop->data->intr->name, type)
> 
> #define VOP_WIN_GET(vop, win, name) \
>-		vop_read_reg(vop, win->offset, win->phy->name)
>+		vop_read_reg(vop, win->base, &win->phy->name)
> 
> #define VOP_WIN_HAS_REG(win, name) \
> 	(!!(win->phy->name.mask))
>@@ -124,6 +127,7 @@
> 	bool is_enabled;
> 
> 	struct completion dsp_hold_completion;
>+	unsigned int win_enabled;
> 
> 	/* protected by dev->event_lock */
> 	struct drm_pending_vblank_event *event;
>@@ -528,8 +532,10 @@
> 	clk_disable(vop->hclk);
> }
> 
>-static void vop_win_disable(struct vop *vop, const struct vop_win_data *win)
>+static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win)
> {
>+	const struct vop_win_data *win = vop_win->data;
>+
> 	if (win->phy->scl && win->phy->scl->ext) {
> 		VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
> 		VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
>@@ -538,9 +544,10 @@
> 	}
> 
> 	VOP_WIN_SET(vop, win, enable, 0);
>+	vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win));
> }
> 
>-static int vop_enable(struct drm_crtc *crtc)
>+static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
> {
> 	struct vop *vop = to_vop(crtc);
> 	int ret, i;
>@@ -580,12 +587,17 @@
> 	 * We need to make sure that all windows are disabled before we
> 	 * enable the crtc. Otherwise we might try to scan from a destroyed
> 	 * buffer later.
>+	 *
>+	 * In the case of enable-after-PSR, we don't need to worry about this
>+	 * case since the buffer is guaranteed to be valid and disabling the
>+	 * window will result in screen glitches on PSR exit.
> 	 */
>-	for (i = 0; i < vop->data->win_size; i++) {
>-		struct vop_win *vop_win = &vop->win[i];
>-		const struct vop_win_data *win = vop_win->data;
>+	if (!old_state || !old_state->self_refresh_active) {
>+		for (i = 0; i < vop->data->win_size; i++) {
>+			struct vop_win *vop_win = &vop->win[i];
> 
>-		vop_win_disable(vop, win);
>+			vop_win_disable(vop, vop_win);
>+		}
> 	}
> 	spin_unlock(&vop->reg_lock);
> 
>@@ -615,6 +627,25 @@
> 	return ret;
> }
> 
>+static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled)
>+{
>+        struct vop *vop = to_vop(crtc);
>+        int i;
>+
>+        spin_lock(&vop->reg_lock);
>+
>+        for (i = 0; i < vop->data->win_size; i++) {
>+                struct vop_win *vop_win = &vop->win[i];
>+                const struct vop_win_data *win = vop_win->data;
>+
>+                VOP_WIN_SET(vop, win, enable,
>+                            enabled && (vop->win_enabled & BIT(i)));
>+        }
>+        vop_cfg_done(vop);
>+
>+        spin_unlock(&vop->reg_lock);
>+}
>+
> static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
> 				    struct drm_crtc_state *old_state)
> {
>@@ -622,9 +653,16 @@
> 
> 	WARN_ON(vop->event);
> 
>+	if (crtc->state->self_refresh_active)
>+		rockchip_drm_set_win_enabled(crtc, false);
>+
> 	mutex_lock(&vop->vop_lock);
>+
> 	drm_crtc_vblank_off(crtc);
> 
>+	if (crtc->state->self_refresh_active)
>+		goto out;
>+
> 	/*
> 	 * Vop standby will take effect at end of current frame,
> 	 * if dsp hold valid irq happen, it means standby complete.
>@@ -655,6 +693,8 @@
> 	clk_disable(vop->dclk);
> 	vop_core_clks_disable(vop);
> 	pm_runtime_put(vop->dev);
>+
>+out:
> 	mutex_unlock(&vop->vop_lock);
> 
> 	if (crtc->state->event && !crtc->state->active) {
>@@ -726,7 +766,6 @@
> 				     struct drm_plane_state *old_state)
> {
> 	struct vop_win *vop_win = to_vop_win(plane);
>-	const struct vop_win_data *win = vop_win->data;
> 	struct vop *vop = to_vop(old_state->crtc);
> 
> 	if (!old_state->crtc)
>@@ -734,7 +773,7 @@
> 
> 	spin_lock(&vop->reg_lock);
> 
>-	vop_win_disable(vop, win);
>+	vop_win_disable(vop, vop_win);
> 
> 	spin_unlock(&vop->reg_lock);
> }
>@@ -873,6 +912,7 @@
> 	}
> 
> 	VOP_WIN_SET(vop, win, enable, 1);
>+	vop->win_enabled |= BIT(win_index);
> 	spin_unlock(&vop->reg_lock);
> }
> 
>@@ -924,12 +964,10 @@
> 	swap(plane->state->fb, new_state->fb);
> 
> 	if (vop->is_enabled) {
>-		rockchip_drm_psr_inhibit_get_state(new_state->state);
> 		vop_plane_atomic_update(plane, plane->state);
> 		spin_lock(&vop->reg_lock);
> 		vop_cfg_done(vop);
> 		spin_unlock(&vop->reg_lock);
>-		rockchip_drm_psr_inhibit_put_state(new_state->state);
> 
> 		/*
> 		 * A scanout can still be occurring, so we can't drop the
>@@ -1033,11 +1071,17 @@
> 	int dither_bpc = s->output_bpc ? s->output_bpc : 10;
> 	int ret;
> 
>+	if (old_state && old_state->self_refresh_active) {
>+		drm_crtc_vblank_on(crtc);
>+		rockchip_drm_set_win_enabled(crtc, true);
>+		return;
>+	}
>+
> 	mutex_lock(&vop->vop_lock);
> 
> 	WARN_ON(vop->event);
> 
>-	ret = vop_enable(crtc);
>+	ret = vop_enable(crtc, old_state);
> 	if (ret) {
> 		mutex_unlock(&vop->vop_lock);
> 		DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
>@@ -1519,6 +1563,13 @@
> 	init_completion(&vop->line_flag_completion);
> 	crtc->port = port;
> 
>+	ret = drm_self_refresh_helper_init(crtc,
>+					   VOP_SELF_REFRESH_ENTRY_DELAY_MS);
>+	if (ret)
>+		DRM_DEV_DEBUG_KMS(vop->dev,
>+			"Failed to init %s with SR helpers %d, ignoring\n",
>+			crtc->name, ret);
>+
> 	return 0;
> 
> err_cleanup_crtc:
>@@ -1536,6 +1587,8 @@
> 	struct drm_device *drm_dev = vop->drm_dev;
> 	struct drm_plane *plane, *tmp;
> 
>+	drm_self_refresh_helper_cleanup(crtc);
>+
> 	of_node_put(crtc->port);
> 
> 	/*
>@@ -1560,7 +1613,6 @@
> 
> static int vop_initial(struct vop *vop)
> {
>-	const struct vop_data *vop_data = vop->data;
> 	struct reset_control *ahb_rst;
> 	int i, ret;
> 
>@@ -1627,12 +1679,13 @@
> 	VOP_REG_SET(vop, misc, global_regdone_en, 1);
> 	VOP_REG_SET(vop, common, dsp_blank, 0);
> 
>-	for (i = 0; i < vop_data->win_size; i++) {
>-		const struct vop_win_data *win = &vop_data->win[i];
>+	for (i = 0; i < vop->data->win_size; i++) {
>+		struct vop_win *vop_win = &vop->win[i];
>+		const struct vop_win_data *win = vop_win->data;
> 		int channel = i * 2 + 1;
> 
> 		VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
>-		vop_win_disable(vop, win);
>+		vop_win_disable(vop, vop_win);
> 		VOP_WIN_SET(vop, win, gate, 1);
> 	}
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_lvds.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_lvds.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_lvds.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_lvds.c	2019-08-31 15:01:12.057736186 -0500
>@@ -6,21 +6,21 @@
>  *      Sandy Huang <hjc@rock-chips.com>
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_dp_helper.h>
>-#include <drm/drm_panel.h>
>-#include <drm/drm_of.h>
>-#include <drm/drm_probe_helper.h>
>-
>-#include <linux/component.h>
> #include <linux/clk.h>
>+#include <linux/component.h>
> #include <linux/mfd/syscon.h>
> #include <linux/of_graph.h>
> #include <linux/pinctrl/devinfo.h>
>+#include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> #include <linux/reset.h>
>+#include <drm/drm_atomic_helper.h>
>+
>+#include <drm/drm_dp_helper.h>
>+#include <drm/drm_of.h>
>+#include <drm/drm_panel.h>
>+#include <drm/drm_probe_helper.h>
> 
> #include "rockchip_drm_drv.h"
> #include "rockchip_drm_vop.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_rgb.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_rgb.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_rgb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_rgb.c	2019-08-31 15:01:12.057736186 -0500
>@@ -5,16 +5,15 @@
>  *      Sandy Huang <hjc@rock-chips.com>
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/component.h>
>+#include <linux/of_graph.h>
>+
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_dp_helper.h>
>-#include <drm/drm_panel.h>
> #include <drm/drm_of.h>
>+#include <drm/drm_panel.h>
> #include <drm/drm_probe_helper.h>
> 
>-#include <linux/component.h>
>-#include <linux/of_graph.h>
>-
> #include "rockchip_drm_drv.h"
> #include "rockchip_drm_vop.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_vop_reg.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
>--- linux-5.3-rc6/drivers/gpu/drm/rockchip/rockchip_vop_reg.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/rockchip/rockchip_vop_reg.c	2019-08-31 15:01:12.057736186 -0500
>@@ -4,10 +4,15 @@
>  * Author:Mark Yao <mark.yao@rock-chips.com>
>  */
> 
>-#include <drm/drmP.h>
>-
>-#include <linux/kernel.h>
> #include <linux/component.h>
>+#include <linux/mod_devicetable.h>
>+#include <linux/module.h>
>+#include <linux/of.h>
>+#include <linux/platform_device.h>
>+
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_plane.h>
>+#include <drm/drm_print.h>
> 
> #include "rockchip_drm_vop.h"
> #include "rockchip_vop_reg.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h
>--- linux-5.3-rc6/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h	2019-08-31 15:01:12.057736186 -0500
>@@ -28,8 +28,6 @@
> #include <linux/types.h>
> #include <linux/tracepoint.h>
> 
>-#include <drm/drmP.h>
>-
> #undef TRACE_SYSTEM
> #define TRACE_SYSTEM gpu_scheduler
> #define TRACE_INCLUDE_FILE gpu_scheduler_trace
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/scheduler/sched_entity.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/scheduler/sched_entity.c
>--- linux-5.3-rc6/drivers/gpu/drm/scheduler/sched_entity.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/scheduler/sched_entity.c	2019-08-31 15:01:12.235736202 -0500
>@@ -22,6 +22,9 @@
>  */
> 
> #include <linux/kthread.h>
>+#include <linux/slab.h>
>+
>+#include <drm/drm_print.h>
> #include <drm/gpu_scheduler.h>
> 
> #include "gpu_scheduler_trace.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/scheduler/sched_fence.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/scheduler/sched_fence.c
>--- linux-5.3-rc6/drivers/gpu/drm/scheduler/sched_fence.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/scheduler/sched_fence.c	2019-08-31 15:01:12.057736186 -0500
>@@ -22,9 +22,11 @@
>  */
> 
> #include <linux/kthread.h>
>-#include <linux/wait.h>
>+#include <linux/module.h>
> #include <linux/sched.h>
>-#include <drm/drmP.h>
>+#include <linux/slab.h>
>+#include <linux/wait.h>
>+
> #include <drm/gpu_scheduler.h>
> 
> static struct kmem_cache *sched_fence_slab;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/scheduler/sched_main.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/scheduler/sched_main.c
>--- linux-5.3-rc6/drivers/gpu/drm/scheduler/sched_main.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/scheduler/sched_main.c	2019-08-31 15:01:12.057736186 -0500
>@@ -48,7 +48,8 @@
> #include <linux/wait.h>
> #include <linux/sched.h>
> #include <uapi/linux/sched/types.h>
>-#include <drm/drmP.h>
>+
>+#include <drm/drm_print.h>
> #include <drm/gpu_scheduler.h>
> #include <drm/spsc_queue.h>
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/selftests/test-drm_framebuffer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/selftests/test-drm_framebuffer.c
>--- linux-5.3-rc6/drivers/gpu/drm/selftests/test-drm_framebuffer.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/selftests/test-drm_framebuffer.c	2019-08-31 15:01:12.057736186 -0500
>@@ -3,7 +3,12 @@
>  * Test cases for the drm_framebuffer functions
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/kernel.h>
>+
>+#include <drm/drm_device.h>
>+#include <drm/drm_mode.h>
>+#include <drm/drm_fourcc.h>
>+
> #include "../drm_crtc_internal.h"
> 
> #include "test-drm_modeset_common.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_crtc.c	2019-08-31 15:01:12.057736186 -0500
>@@ -10,13 +10,14 @@
> #include <linux/backlight.h>
> #include <linux/clk.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_crtc_helper.h>
> #include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "shmob_drm_backlight.h"
> #include "shmob_drm_crtc.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_crtc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_crtc.h
>--- linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_crtc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_crtc.h	2019-08-31 15:01:12.057736186 -0500
>@@ -10,12 +10,14 @@
> #ifndef __SHMOB_DRM_CRTC_H__
> #define __SHMOB_DRM_CRTC_H__
> 
>-#include <drm/drmP.h>
> #include <drm/drm_crtc.h>
>+#include <drm/drm_connector.h>
> #include <drm/drm_encoder.h>
> 
> struct backlight_device;
>+struct drm_pending_vblank_event;
> struct shmob_drm_device;
>+struct shmob_drm_format_info;
> 
> struct shmob_drm_crtc {
> 	struct drm_crtc crtc;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_drv.c	2019-08-31 15:01:12.058736186 -0500
>@@ -15,10 +15,12 @@
> #include <linux/pm.h>
> #include <linux/slab.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_crtc_helper.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_irq.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "shmob_drm_drv.h"
> #include "shmob_drm_kms.h"
>@@ -127,15 +129,12 @@
> DEFINE_DRM_GEM_CMA_FOPS(shmob_drm_fops);
> 
> static struct drm_driver shmob_drm_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET
>-				| DRIVER_PRIME,
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET,
> 	.irq_handler		= shmob_drm_irq,
> 	.gem_free_object_unlocked = drm_gem_cma_free_object,
> 	.gem_vm_ops		= &drm_gem_cma_vm_ops,
> 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
>-	.gem_prime_import	= drm_gem_prime_import,
>-	.gem_prime_export	= drm_gem_prime_export,
> 	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_kms.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_kms.c
>--- linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_kms.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_kms.c	2019-08-31 15:01:12.058736186 -0500
>@@ -7,7 +7,6 @@
>  * Laurent Pinchart (laurent.pinchart@ideasonboard.com)
>  */
> 
>-#include <drm/drmP.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_crtc_helper.h>
> #include <drm/drm_fb_cma_helper.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_plane.c	2019-08-31 15:01:12.079736188 -0500
>@@ -7,10 +7,10 @@
>  * Laurent Pinchart (laurent.pinchart@ideasonboard.com)
>  */
> 
>-#include <drm/drmP.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_crtc_helper.h>
> #include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_cma_helper.h>
> 
> #include "shmob_drm_drv.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_plane.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_plane.h
>--- linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_plane.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_plane.h	2019-08-31 15:01:12.084736188 -0500
>@@ -10,6 +10,7 @@
> #ifndef __SHMOB_DRM_PLANE_H__
> #define __SHMOB_DRM_PLANE_H__
> 
>+struct drm_plane;
> struct shmob_drm_device;
> 
> int shmob_drm_plane_create(struct shmob_drm_device *sdev, unsigned int index);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_regs.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_regs.h
>--- linux-5.3-rc6/drivers/gpu/drm/shmobile/shmob_drm_regs.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/shmobile/shmob_drm_regs.h	2019-08-31 15:01:12.084736188 -0500
>@@ -11,6 +11,9 @@
> #define __SHMOB_DRM_REGS_H__
> 
> #include <linux/io.h>
>+#include <linux/jiffies.h>
>+
>+#include "shmob_drm_drv.h"
> 
> /* Register definitions */
> #define LDDCKPAT1R		0x400
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sti/sti_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sti/sti_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/sti/sti_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sti/sti_drv.c	2019-08-31 15:01:12.084736188 -0500
>@@ -23,7 +23,6 @@
> 
> #include "sti_crtc.h"
> #include "sti_drv.h"
>-#include "sti_drv.h"
> #include "sti_plane.h"
> 
> #define DRIVER_NAME	"sti"
>@@ -141,8 +140,7 @@
> DEFINE_DRM_GEM_CMA_FOPS(sti_driver_fops);
> 
> static struct drm_driver sti_driver = {
>-	.driver_features = DRIVER_MODESET |
>-	    DRIVER_GEM | DRIVER_PRIME | DRIVER_ATOMIC,
>+	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> 	.gem_free_object_unlocked = drm_gem_cma_free_object,
> 	.gem_vm_ops = &drm_gem_cma_vm_ops,
> 	.dumb_create = drm_gem_cma_dumb_create,
>@@ -153,8 +151,6 @@
> 
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_export = drm_gem_prime_export,
>-	.gem_prime_import = drm_gem_prime_import,
> 	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap = drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sti/sti_dvo.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sti/sti_dvo.c
>--- linux-5.3-rc6/drivers/gpu/drm/sti/sti_dvo.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sti/sti_dvo.c	2019-08-31 15:01:12.084736188 -0500
>@@ -221,8 +221,7 @@
> 
> 	writel(0x00000000, dvo->regs + DVO_DOF_CFG);
> 
>-	if (dvo->panel)
>-		dvo->panel->funcs->disable(dvo->panel);
>+	drm_panel_disable(dvo->panel);
> 
> 	/* Disable/unprepare dvo clock */
> 	clk_disable_unprepare(dvo->clk_pix);
>@@ -262,8 +261,7 @@
> 	if (clk_prepare_enable(dvo->clk))
> 		DRM_ERROR("Failed to prepare/enable dvo clk\n");
> 
>-	if (dvo->panel)
>-		dvo->panel->funcs->enable(dvo->panel);
>+	drm_panel_enable(dvo->panel);
> 
> 	/* Set LUT */
> 	writel(config->lowbyte,  dvo->regs + DVO_LUT_PROG_LOW);
>@@ -340,7 +338,7 @@
> 	struct sti_dvo *dvo = dvo_connector->dvo;
> 
> 	if (dvo->panel)
>-		return dvo->panel->funcs->get_modes(dvo->panel);
>+		return drm_panel_get_modes(dvo->panel);
> 
> 	return 0;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sti/sti_hdmi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sti/sti_hdmi.c
>--- linux-5.3-rc6/drivers/gpu/drm/sti/sti_hdmi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sti/sti_hdmi.c	2019-08-31 15:01:12.084736188 -0500
>@@ -849,10 +849,13 @@
> 	switch (info->channels) {
> 	case 8:
> 		audio_cfg |= HDMI_AUD_CFG_CH78_VALID;
>+		/* fall through */
> 	case 6:
> 		audio_cfg |= HDMI_AUD_CFG_CH56_VALID;
>+		/* fall through */
> 	case 4:
> 		audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH;
>+		/* fall through */
> 	case 2:
> 		audio_cfg |= HDMI_AUD_CFG_CH12_VALID;
> 		break;
>@@ -1284,8 +1287,10 @@
> 
> 	drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
> 
>-	drm_connector_init(drm_dev, drm_connector,
>-			&sti_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
>+	drm_connector_init_with_ddc(drm_dev, drm_connector,
>+				    &sti_hdmi_connector_funcs,
>+				    DRM_MODE_CONNECTOR_HDMIA,
>+				    hdmi->ddc_adapt);
> 	drm_connector_helper_add(drm_connector,
> 			&sti_hdmi_connector_helper_funcs);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sti/sti_tvout.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sti/sti_tvout.c
>--- linux-5.3-rc6/drivers/gpu/drm/sti/sti_tvout.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sti/sti_tvout.c	2019-08-31 15:01:12.084736188 -0500
>@@ -669,10 +669,9 @@
> 
> 	encoder->tvout = tvout;
> 
>-	drm_encoder = (struct drm_encoder *)encoder;
>+	drm_encoder = &encoder->encoder;
> 
> 	drm_encoder->possible_crtcs = ENCODER_CRTC_MASK;
>-	drm_encoder->possible_clones = 1 << 0;
> 
> 	drm_encoder_init(dev, drm_encoder,
> 			 &sti_tvout_encoder_funcs, DRM_MODE_ENCODER_LVDS,
>@@ -722,10 +721,9 @@
> 
> 	encoder->tvout = tvout;
> 
>-	drm_encoder = (struct drm_encoder *) encoder;
>+	drm_encoder = &encoder->encoder;
> 
> 	drm_encoder->possible_crtcs = ENCODER_CRTC_MASK;
>-	drm_encoder->possible_clones = 1 << 0;
> 
> 	drm_encoder_init(dev, drm_encoder,
> 			&sti_tvout_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL);
>@@ -771,10 +769,9 @@
> 
> 	encoder->tvout = tvout;
> 
>-	drm_encoder = (struct drm_encoder *) encoder;
>+	drm_encoder = &encoder->encoder;
> 
> 	drm_encoder->possible_crtcs = ENCODER_CRTC_MASK;
>-	drm_encoder->possible_clones = 1 << 1;
> 
> 	drm_encoder_init(dev, drm_encoder,
> 			&sti_tvout_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL);
>@@ -790,6 +787,13 @@
> 	tvout->hdmi = sti_tvout_create_hdmi_encoder(dev, tvout);
> 	tvout->hda = sti_tvout_create_hda_encoder(dev, tvout);
> 	tvout->dvo = sti_tvout_create_dvo_encoder(dev, tvout);
>+
>+	tvout->hdmi->possible_clones = drm_encoder_mask(tvout->hdmi) |
>+		drm_encoder_mask(tvout->hda) | drm_encoder_mask(tvout->dvo);
>+	tvout->hda->possible_clones = drm_encoder_mask(tvout->hdmi) |
>+		drm_encoder_mask(tvout->hda) | drm_encoder_mask(tvout->dvo);
>+	tvout->dvo->possible_clones = drm_encoder_mask(tvout->hdmi) |
>+		drm_encoder_mask(tvout->hda) | drm_encoder_mask(tvout->dvo);
> }
> 
> static void sti_tvout_destroy_encoders(struct sti_tvout *tvout)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/stm/drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/stm/drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/stm/drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/stm/drv.c	2019-08-31 15:01:12.084736188 -0500
>@@ -54,8 +54,7 @@
> DEFINE_DRM_GEM_CMA_FOPS(drv_driver_fops);
> 
> static struct drm_driver drv_driver = {
>-	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
>-			   DRIVER_ATOMIC,
>+	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> 	.name = "stm",
> 	.desc = "STMicroelectronics SoC DRM",
> 	.date = "20170330",
>@@ -68,8 +67,6 @@
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> 	.gem_free_object_unlocked = drm_gem_cma_free_object,
> 	.gem_vm_ops = &drm_gem_cma_vm_ops,
>-	.gem_prime_export = drm_gem_prime_export,
>-	.gem_prime_import = drm_gem_prime_import,
> 	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap = drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
>--- linux-5.3-rc6/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c	2019-08-31 15:01:12.084736188 -0500
>@@ -8,13 +8,17 @@
> 
> #include <linux/clk.h>
> #include <linux/iopoll.h>
>+#include <linux/mod_devicetable.h>
> #include <linux/module.h>
>+#include <linux/platform_device.h>
> #include <linux/regulator/consumer.h>
>-#include <drm/drmP.h>
>-#include <drm/drm_mipi_dsi.h>
>-#include <drm/bridge/dw_mipi_dsi.h>
>+
> #include <video/mipi_display.h>
> 
>+#include <drm/bridge/dw_mipi_dsi.h>
>+#include <drm/drm_mipi_dsi.h>
>+#include <drm/drm_print.h>
>+
> #define HWVER_130			0x31333000	/* IP version 1.30 */
> #define HWVER_131			0x31333100	/* IP version 1.31 */
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/stm/ltdc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/stm/ltdc.c
>--- linux-5.3-rc6/drivers/gpu/drm/stm/ltdc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/stm/ltdc.c	2019-08-31 15:01:12.084736188 -0500
>@@ -26,6 +26,7 @@
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_fourcc.h>
> #include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_of.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>@@ -922,6 +923,7 @@
> };
> 
> static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
>+	.prepare_fb = drm_gem_fb_prepare_fb,
> 	.atomic_check = ltdc_plane_atomic_check,
> 	.atomic_update = ltdc_plane_atomic_update,
> 	.atomic_disable = ltdc_plane_atomic_disable,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_backend.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_backend.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_backend.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_backend.c	2019-08-31 15:01:12.085736188 -0500
>@@ -6,21 +6,23 @@
>  * Maxime Ripard <maxime.ripard@free-electrons.com>
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/component.h>
>+#include <linux/list.h>
>+#include <linux/module.h>
>+#include <linux/of_device.h>
>+#include <linux/of_graph.h>
>+#include <linux/platform_device.h>
>+#include <linux/reset.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> 
>-#include <linux/component.h>
>-#include <linux/list.h>
>-#include <linux/of_device.h>
>-#include <linux/of_graph.h>
>-#include <linux/reset.h>
>-
> #include "sun4i_backend.h"
> #include "sun4i_drv.h"
> #include "sun4i_frontend.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_crtc.c	2019-08-31 15:01:12.085736188 -0500
>@@ -6,12 +6,6 @@
>  * Maxime Ripard <maxime.ripard@free-electrons.com>
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_crtc.h>
>-#include <drm/drm_modes.h>
>-#include <drm/drm_probe_helper.h>
>-
> #include <linux/clk-provider.h>
> #include <linux/ioport.h>
> #include <linux/of_address.h>
>@@ -21,6 +15,13 @@
> 
> #include <video/videomode.h>
> 
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_crtc.h>
>+#include <drm/drm_modes.h>
>+#include <drm/drm_print.h>
>+#include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
>+
> #include "sun4i_backend.h"
> #include "sun4i_crtc.h"
> #include "sun4i_drv.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_drv.c	2019-08-31 15:01:12.085736188 -0500
>@@ -8,16 +8,19 @@
> 
> #include <linux/component.h>
> #include <linux/kfifo.h>
>+#include <linux/module.h>
> #include <linux/of_graph.h>
> #include <linux/of_reserved_mem.h>
>+#include <linux/platform_device.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_fb_helper.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_of.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "sun4i_drv.h"
> #include "sun4i_frontend.h"
>@@ -38,7 +41,7 @@
> DEFINE_DRM_GEM_CMA_FOPS(sun4i_drv_fops);
> 
> static struct drm_driver sun4i_drv_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_ATOMIC,
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 
> 	/* Generic Operations */
> 	.fops			= &sun4i_drv_fops,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_framebuffer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_framebuffer.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_framebuffer.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_framebuffer.c	2019-08-31 15:01:12.085736188 -0500
>@@ -9,7 +9,6 @@
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drmP.h>
> 
> #include "sun4i_drv.h"
> #include "sun4i_framebuffer.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_frontend.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_frontend.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_frontend.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_frontend.c	2019-08-31 15:01:12.085736188 -0500
>@@ -3,9 +3,6 @@
>  * Copyright (C) 2017 Free Electrons
>  * Maxime Ripard <maxime.ripard@free-electrons.com>
>  */
>-#include <drm/drmP.h>
>-#include <drm/drm_gem_cma_helper.h>
>-#include <drm/drm_fb_cma_helper.h>
> 
> #include <linux/clk.h>
> #include <linux/component.h>
>@@ -16,6 +13,13 @@
> #include <linux/regmap.h>
> #include <linux/reset.h>
> 
>+#include <drm/drm_device.h>
>+#include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_framebuffer.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_plane.h>
>+
> #include "sun4i_drv.h"
> #include "sun4i_frontend.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c	2019-08-31 15:01:12.085736188 -0500
>@@ -5,23 +5,24 @@
>  * Maxime Ripard <maxime.ripard@free-electrons.com>
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_probe_helper.h>
>-#include <drm/drm_edid.h>
>-#include <drm/drm_encoder.h>
>-#include <drm/drm_of.h>
>-#include <drm/drm_panel.h>
>-
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/iopoll.h>
>+#include <linux/module.h>
> #include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> #include <linux/reset.h>
> 
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_edid.h>
>+#include <drm/drm_encoder.h>
>+#include <drm/drm_of.h>
>+#include <drm/drm_panel.h>
>+#include <drm/drm_print.h>
>+#include <drm/drm_probe_helper.h>
>+
> #include "sun4i_backend.h"
> #include "sun4i_crtc.h"
> #include "sun4i_drv.h"
>@@ -639,9 +640,10 @@
> 
> 	drm_connector_helper_add(&hdmi->connector,
> 				 &sun4i_hdmi_connector_helper_funcs);
>-	ret = drm_connector_init(drm, &hdmi->connector,
>-				 &sun4i_hdmi_connector_funcs,
>-				 DRM_MODE_CONNECTOR_HDMIA);
>+	ret = drm_connector_init_with_ddc(drm, &hdmi->connector,
>+					  &sun4i_hdmi_connector_funcs,
>+					  DRM_MODE_CONNECTOR_HDMIA,
>+					  hdmi->ddc_i2c);
> 	if (ret) {
> 		dev_err(dev,
> 			"Couldn't initialise the HDMI connector\n");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_layer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_layer.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_layer.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_layer.c	2019-08-31 15:01:12.085736188 -0500
>@@ -7,9 +7,8 @@
>  */
> 
> #include <drm/drm_atomic_helper.h>
>-#include <drm/drm_plane_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drmP.h>
>+#include <drm/drm_plane_helper.h>
> 
> #include "sun4i_backend.h"
> #include "sun4i_frontend.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_lvds.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_lvds.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_lvds.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_lvds.c	2019-08-31 15:01:12.085736188 -0500
>@@ -6,10 +6,10 @@
> 
> #include <linux/clk.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_of.h>
> #include <drm/drm_panel.h>
>+#include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
> 
> #include "sun4i_crtc.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_rgb.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_rgb.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_rgb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_rgb.c	2019-08-31 15:01:12.085736188 -0500
>@@ -8,10 +8,10 @@
> 
> #include <linux/clk.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_of.h>
> #include <drm/drm_panel.h>
>+#include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
> 
> #include "sun4i_crtc.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_tcon.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_tcon.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_tcon.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_tcon.c	2019-08-31 15:01:12.234736201 -0500
>@@ -6,7 +6,15 @@
>  * Maxime Ripard <maxime.ripard@free-electrons.com>
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/component.h>
>+#include <linux/ioport.h>
>+#include <linux/module.h>
>+#include <linux/of_address.h>
>+#include <linux/of_device.h>
>+#include <linux/of_irq.h>
>+#include <linux/regmap.h>
>+#include <linux/reset.h>
>+
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_connector.h>
> #include <drm/drm_crtc.h>
>@@ -14,18 +22,12 @@
> #include <drm/drm_modes.h>
> #include <drm/drm_of.h>
> #include <drm/drm_panel.h>
>+#include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include <uapi/drm/drm_mode.h>
> 
>-#include <linux/component.h>
>-#include <linux/ioport.h>
>-#include <linux/of_address.h>
>-#include <linux/of_device.h>
>-#include <linux/of_irq.h>
>-#include <linux/regmap.h>
>-#include <linux/reset.h>
>-
> #include "sun4i_crtc.h"
> #include "sun4i_dotclock.h"
> #include "sun4i_drv.h"
>@@ -479,7 +481,7 @@
> 				     const struct drm_display_mode *mode)
> {
> 	struct drm_connector *connector = sun4i_tcon_get_connector(encoder);
>-	struct drm_display_info display_info = connector->display_info;
>+	const struct drm_display_info *info = &connector->display_info;
> 	unsigned int bp, hsync, vsync;
> 	u8 clk_delay;
> 	u32 val = 0;
>@@ -540,7 +542,7 @@
> 	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
> 		val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
> 
>-	if (display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
>+	if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
> 		val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
> 
> 	/*
>@@ -558,10 +560,10 @@
> 	 * Following code is a way to avoid quirks all around TCON
> 	 * and DOTCLOCK drivers.
> 	 */
>-	if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
>+	if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
> 		clk_set_phase(tcon->dclk, 240);
> 
>-	if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
>+	if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
> 		clk_set_phase(tcon->dclk, 0);
> 
> 	regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_tv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_tv.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun4i_tv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun4i_tv.c	2019-08-31 15:01:12.085736188 -0500
>@@ -8,14 +8,16 @@
> 
> #include <linux/clk.h>
> #include <linux/component.h>
>+#include <linux/module.h>
> #include <linux/of_address.h>
>+#include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/reset.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_of.h>
> #include <drm/drm_panel.h>
>+#include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
> 
> #include "sun4i_crtc.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c	2019-08-31 15:01:12.234736201 -0500
>@@ -9,19 +9,20 @@
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/crc-ccitt.h>
>+#include <linux/module.h>
> #include <linux/of_address.h>
>+#include <linux/phy/phy-mipi-dphy.h>
>+#include <linux/phy/phy.h>
>+#include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> #include <linux/reset.h>
> #include <linux/slab.h>
> 
>-#include <linux/phy/phy.h>
>-#include <linux/phy/phy-mipi-dphy.h>
>-
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_mipi_dsi.h>
> #include <drm/drm_panel.h>
>+#include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
> 
> #include "sun4i_crtc.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_csc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_csc.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_csc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_csc.c	2019-08-31 15:01:12.085736188 -0500
>@@ -3,7 +3,7 @@
>  * Copyright (C) Jernej Skrabec <jernej.skrabec@siol.net>
>  */
> 
>-#include <drm/drmP.h>
>+#include <drm/drm_print.h>
> 
> #include "sun8i_csc.h"
> #include "sun8i_mixer.h"
>@@ -18,16 +18,59 @@
>  * First tree values in each line are multiplication factor and last
>  * value is constant, which is added at the end.
>  */
>-static const u32 yuv2rgb[] = {
>-	0x000004A8, 0x00000000, 0x00000662, 0xFFFC845A,
>-	0x000004A8, 0xFFFFFE6F, 0xFFFFFCBF, 0x00021DF4,
>-	0x000004A8, 0x00000813, 0x00000000, 0xFFFBAC4A,
>+
>+static const u32 yuv2rgb[2][2][12] = {
>+	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
>+		[DRM_COLOR_YCBCR_BT601] = {
>+			0x000004A8, 0x00000000, 0x00000662, 0xFFFC8451,
>+			0x000004A8, 0xFFFFFE6F, 0xFFFFFCC0, 0x00021E4D,
>+			0x000004A8, 0x00000811, 0x00000000, 0xFFFBACA9,
>+		},
>+		[DRM_COLOR_YCBCR_BT709] = {
>+			0x000004A8, 0x00000000, 0x0000072B, 0xFFFC1F99,
>+			0x000004A8, 0xFFFFFF26, 0xFFFFFDDF, 0x00013383,
>+			0x000004A8, 0x00000873, 0x00000000, 0xFFFB7BEF,
>+		}
>+	},
>+	[DRM_COLOR_YCBCR_FULL_RANGE] = {
>+		[DRM_COLOR_YCBCR_BT601] = {
>+			0x00000400, 0x00000000, 0x0000059B, 0xFFFD322E,
>+			0x00000400, 0xFFFFFEA0, 0xFFFFFD25, 0x00021DD5,
>+			0x00000400, 0x00000716, 0x00000000, 0xFFFC74BD,
>+		},
>+		[DRM_COLOR_YCBCR_BT709] = {
>+			0x00000400, 0x00000000, 0x0000064C, 0xFFFCD9B4,
>+			0x00000400, 0xFFFFFF41, 0xFFFFFE21, 0x00014F96,
>+			0x00000400, 0x0000076C, 0x00000000, 0xFFFC49EF,
>+		}
>+	},
> };
> 
>-static const u32 yvu2rgb[] = {
>-	0x000004A8, 0x00000662, 0x00000000, 0xFFFC845A,
>-	0x000004A8, 0xFFFFFCBF, 0xFFFFFE6F, 0x00021DF4,
>-	0x000004A8, 0x00000000, 0x00000813, 0xFFFBAC4A,
>+static const u32 yvu2rgb[2][2][12] = {
>+	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
>+		[DRM_COLOR_YCBCR_BT601] = {
>+			0x000004A8, 0x00000662, 0x00000000, 0xFFFC8451,
>+			0x000004A8, 0xFFFFFCC0, 0xFFFFFE6F, 0x00021E4D,
>+			0x000004A8, 0x00000000, 0x00000811, 0xFFFBACA9,
>+		},
>+		[DRM_COLOR_YCBCR_BT709] = {
>+			0x000004A8, 0x0000072B, 0x00000000, 0xFFFC1F99,
>+			0x000004A8, 0xFFFFFDDF, 0xFFFFFF26, 0x00013383,
>+			0x000004A8, 0x00000000, 0x00000873, 0xFFFB7BEF,
>+		}
>+	},
>+	[DRM_COLOR_YCBCR_FULL_RANGE] = {
>+		[DRM_COLOR_YCBCR_BT601] = {
>+			0x00000400, 0x0000059B, 0x00000000, 0xFFFD322E,
>+			0x00000400, 0xFFFFFD25, 0xFFFFFEA0, 0x00021DD5,
>+			0x00000400, 0x00000000, 0x00000716, 0xFFFC74BD,
>+		},
>+		[DRM_COLOR_YCBCR_BT709] = {
>+			0x00000400, 0x0000064C, 0x00000000, 0xFFFCD9B4,
>+			0x00000400, 0xFFFFFE21, 0xFFFFFF41, 0x00014F96,
>+			0x00000400, 0x00000000, 0x0000076C, 0xFFFC49EF,
>+		}
>+	},
> };
> 
> /*
>@@ -53,57 +96,98 @@
>  * c20 c21 c22 [d2 const2]
>  */
> 
>-static const u32 yuv2rgb_de3[] = {
>-	0x0002542a, 0x00000000, 0x0003312a, 0xffc00000,
>-	0x0002542a, 0xffff376b, 0xfffe5fc3, 0xfe000000,
>-	0x0002542a, 0x000408d3, 0x00000000, 0xfe000000,
>+static const u32 yuv2rgb_de3[2][2][12] = {
>+	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
>+		[DRM_COLOR_YCBCR_BT601] = {
>+			0x0002542A, 0x00000000, 0x0003312A, 0xFFC00000,
>+			0x0002542A, 0xFFFF376B, 0xFFFE5FC3, 0xFE000000,
>+			0x0002542A, 0x000408D2, 0x00000000, 0xFE000000,
>+		},
>+		[DRM_COLOR_YCBCR_BT709] = {
>+			0x0002542A, 0x00000000, 0x000395E2, 0xFFC00000,
>+			0x0002542A, 0xFFFF92D2, 0xFFFEEF27, 0xFE000000,
>+			0x0002542A, 0x0004398C, 0x00000000, 0xFE000000,
>+		}
>+	},
>+	[DRM_COLOR_YCBCR_FULL_RANGE] = {
>+		[DRM_COLOR_YCBCR_BT601] = {
>+			0x00020000, 0x00000000, 0x0002CDD2, 0x00000000,
>+			0x00020000, 0xFFFF4FCE, 0xFFFE925D, 0xFE000000,
>+			0x00020000, 0x00038B43, 0x00000000, 0xFE000000,
>+		},
>+		[DRM_COLOR_YCBCR_BT709] = {
>+			0x00020000, 0x00000000, 0x0003264C, 0x00000000,
>+			0x00020000, 0xFFFFA018, 0xFFFF1053, 0xFE000000,
>+			0x00020000, 0x0003B611, 0x00000000, 0xFE000000,
>+		}
>+	},
> };
> 
>-static const u32 yvu2rgb_de3[] = {
>-	0x0002542a, 0x0003312a, 0x00000000, 0xffc00000,
>-	0x0002542a, 0xfffe5fc3, 0xffff376b, 0xfe000000,
>-	0x0002542a, 0x00000000, 0x000408d3, 0xfe000000,
>+static const u32 yvu2rgb_de3[2][2][12] = {
>+	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
>+		[DRM_COLOR_YCBCR_BT601] = {
>+			0x0002542A, 0x0003312A, 0x00000000, 0xFFC00000,
>+			0x0002542A, 0xFFFE5FC3, 0xFFFF376B, 0xFE000000,
>+			0x0002542A, 0x00000000, 0x000408D2, 0xFE000000,
>+		},
>+		[DRM_COLOR_YCBCR_BT709] = {
>+			0x0002542A, 0x000395E2, 0x00000000, 0xFFC00000,
>+			0x0002542A, 0xFFFEEF27, 0xFFFF92D2, 0xFE000000,
>+			0x0002542A, 0x00000000, 0x0004398C, 0xFE000000,
>+		}
>+	},
>+	[DRM_COLOR_YCBCR_FULL_RANGE] = {
>+		[DRM_COLOR_YCBCR_BT601] = {
>+			0x00020000, 0x0002CDD2, 0x00000000, 0x00000000,
>+			0x00020000, 0xFFFE925D, 0xFFFF4FCE, 0xFE000000,
>+			0x00020000, 0x00000000, 0x00038B43, 0xFE000000,
>+		},
>+		[DRM_COLOR_YCBCR_BT709] = {
>+			0x00020000, 0x0003264C, 0x00000000, 0x00000000,
>+			0x00020000, 0xFFFF1053, 0xFFFFA018, 0xFE000000,
>+			0x00020000, 0x00000000, 0x0003B611, 0xFE000000,
>+		}
>+	},
> };
> 
> static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
>-				       enum sun8i_csc_mode mode)
>+				       enum sun8i_csc_mode mode,
>+				       enum drm_color_encoding encoding,
>+				       enum drm_color_range range)
> {
> 	const u32 *table;
>-	int i, data;
>+	u32 base_reg;
> 
> 	switch (mode) {
> 	case SUN8I_CSC_MODE_YUV2RGB:
>-		table = yuv2rgb;
>+		table = yuv2rgb[range][encoding];
> 		break;
> 	case SUN8I_CSC_MODE_YVU2RGB:
>-		table = yvu2rgb;
>+		table = yvu2rgb[range][encoding];
> 		break;
> 	default:
> 		DRM_WARN("Wrong CSC mode specified.\n");
> 		return;
> 	}
> 
>-	for (i = 0; i < 12; i++) {
>-		data = table[i];
>-		/* For some reason, 0x200 must be added to constant parts */
>-		if (((i + 1) & 3) == 0)
>-			data += 0x200;
>-		regmap_write(map, SUN8I_CSC_COEFF(base, i), data);
>-	}
>+	base_reg = SUN8I_CSC_COEFF(base, 0);
>+	regmap_bulk_write(map, base_reg, table, 12);
> }
> 
> static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
>-					    enum sun8i_csc_mode mode)
>+					    enum sun8i_csc_mode mode,
>+					    enum drm_color_encoding encoding,
>+					    enum drm_color_range range)
> {
> 	const u32 *table;
> 	u32 base_reg;
> 
> 	switch (mode) {
> 	case SUN8I_CSC_MODE_YUV2RGB:
>-		table = yuv2rgb_de3;
>+		table = yuv2rgb_de3[range][encoding];
> 		break;
> 	case SUN8I_CSC_MODE_YVU2RGB:
>-		table = yvu2rgb_de3;
>+		table = yvu2rgb_de3[range][encoding];
> 		break;
> 	default:
> 		DRM_WARN("Wrong CSC mode specified.\n");
>@@ -142,19 +226,22 @@
> }
> 
> void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
>-				     enum sun8i_csc_mode mode)
>+				     enum sun8i_csc_mode mode,
>+				     enum drm_color_encoding encoding,
>+				     enum drm_color_range range)
> {
> 	u32 base;
> 
> 	if (mixer->cfg->is_de3) {
>-		sun8i_de3_ccsc_set_coefficients(mixer->engine.regs,
>-						layer, mode);
>+		sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer,
>+						mode, encoding, range);
> 		return;
> 	}
> 
> 	base = ccsc_base[mixer->cfg->ccsc][layer];
> 
>-	sun8i_csc_set_coefficients(mixer->engine.regs, base, mode);
>+	sun8i_csc_set_coefficients(mixer->engine.regs, base,
>+				   mode, encoding, range);
> }
> 
> void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_csc.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_csc.h
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_csc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_csc.h	2019-08-31 15:01:12.085736188 -0500
>@@ -6,6 +6,8 @@
> #ifndef _SUN8I_CSC_H_
> #define _SUN8I_CSC_H_
> 
>+#include <drm/drm_color_mgmt.h>
>+
> struct sun8i_mixer;
> 
> /* VI channel CSC units offsets */
>@@ -26,7 +28,9 @@
> };
> 
> void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
>-				     enum sun8i_csc_mode mode);
>+				     enum sun8i_csc_mode mode,
>+				     enum drm_color_encoding encoding,
>+				     enum drm_color_range range);
> void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable);
> 
> #endif
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c	2019-08-31 15:01:12.085736188 -0500
>@@ -8,9 +8,8 @@
> #include <linux/of_device.h>
> #include <linux/platform_device.h>
> 
>-#include <drm/drm_of.h>
>-#include <drm/drmP.h>
> #include <drm/drm_crtc_helper.h>
>+#include <drm/drm_of.h>
> 
> #include "sun8i_dw_hdmi.h"
> #include "sun8i_tcon_top.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_mixer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_mixer.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_mixer.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_mixer.c	2019-08-31 15:01:12.085736188 -0500
>@@ -7,7 +7,13 @@
>  *   Copyright (C) 2015 NextThing Co
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/component.h>
>+#include <linux/dma-mapping.h>
>+#include <linux/module.h>
>+#include <linux/of_device.h>
>+#include <linux/of_graph.h>
>+#include <linux/reset.h>
>+
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_fb_cma_helper.h>
>@@ -15,12 +21,6 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> 
>-#include <linux/component.h>
>-#include <linux/dma-mapping.h>
>-#include <linux/of_device.h>
>-#include <linux/of_graph.h>
>-#include <linux/reset.h>
>-
> #include "sun4i_drv.h"
> #include "sun8i_mixer.h"
> #include "sun8i_ui_layer.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_tcon_top.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_tcon_top.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_tcon_top.c	2019-08-31 15:01:12.086736188 -0500
>@@ -1,18 +1,18 @@
> // SPDX-License-Identifier: GPL-2.0+
> /* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
> 
>-#include <drm/drmP.h>
>-
>-#include <dt-bindings/clock/sun8i-tcon-top.h>
> 
> #include <linux/bitfield.h>
> #include <linux/component.h>
> #include <linux/device.h>
>+#include <linux/io.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> #include <linux/of_graph.h>
> #include <linux/platform_device.h>
> 
>+#include <dt-bindings/clock/sun8i-tcon-top.h>
>+
> #include "sun8i_tcon_top.h"
> 
> struct sun8i_tcon_top_quirks {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_ui_layer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_ui_layer.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_ui_layer.c	2019-08-31 15:01:12.086736188 -0500
>@@ -13,11 +13,11 @@
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
> #include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>-#include <drm/drmP.h>
> 
> #include "sun8i_ui_layer.h"
> #include "sun8i_mixer.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_vi_layer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
>--- linux-5.3-rc6/drivers/gpu/drm/sun4i/sun8i_vi_layer.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/sun4i/sun8i_vi_layer.c	2019-08-31 15:01:12.086736188 -0500
>@@ -11,7 +11,6 @@
> #include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>-#include <drm/drmP.h>
> 
> #include "sun8i_vi_layer.h"
> #include "sun8i_mixer.h"
>@@ -232,7 +231,9 @@
> 			   SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
> 
> 	if (fmt_info->csc != SUN8I_CSC_MODE_OFF) {
>-		sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc);
>+		sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc,
>+						state->color_encoding,
>+						state->color_range);
> 		sun8i_csc_enable_ccsc(mixer, channel, true);
> 	} else {
> 		sun8i_csc_enable_ccsc(mixer, channel, false);
>@@ -441,6 +442,7 @@
> 					       struct sun8i_mixer *mixer,
> 					       int index)
> {
>+	u32 supported_encodings, supported_ranges;
> 	struct sun8i_vi_layer *layer;
> 	unsigned int plane_cnt;
> 	int ret;
>@@ -469,6 +471,22 @@
> 		return ERR_PTR(ret);
> 	}
> 
>+	supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) |
>+			      BIT(DRM_COLOR_YCBCR_BT709);
>+
>+	supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
>+			   BIT(DRM_COLOR_YCBCR_FULL_RANGE);
>+
>+	ret = drm_plane_create_color_properties(&layer->plane,
>+						supported_encodings,
>+						supported_ranges,
>+						DRM_COLOR_YCBCR_BT709,
>+						DRM_COLOR_YCBCR_LIMITED_RANGE);
>+	if (ret) {
>+		dev_err(drm->dev, "Couldn't add encoding and range properties!\n");
>+		return ERR_PTR(ret);
>+	}
>+
> 	drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs);
> 	layer->mixer = mixer;
> 	layer->channel = index;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tdfx/tdfx_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tdfx/tdfx_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/tdfx/tdfx_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tdfx/tdfx_drv.c	2019-08-31 15:01:12.086736188 -0500
>@@ -32,11 +32,14 @@
> 
> #include <linux/module.h>
> 
>-#include <drm/drmP.h>
>-#include "tdfx_drv.h"
>-
>-#include <drm/drm_pciids.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_ioctl.h>
> #include <drm/drm_legacy.h>
>+#include <drm/drm_pci.h>
>+#include <drm/drm_pciids.h>
>+
>+#include "tdfx_drv.h"
> 
> static struct pci_device_id pciidlist[] = {
> 	tdfx_PCI_IDS
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tegra/drm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tegra/drm.c
>--- linux-5.3-rc6/drivers/gpu/drm/tegra/drm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tegra/drm.c	2019-08-31 15:01:12.086736188 -0500
>@@ -888,33 +888,33 @@
> static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
> #ifdef CONFIG_DRM_TEGRA_STAGING
> 	DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
>-			  DRM_UNLOCKED | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> #endif
> };
> 
>@@ -1004,7 +1004,7 @@
> #endif
> 
> static struct drm_driver tegra_drm_driver = {
>-	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
>+	.driver_features = DRIVER_MODESET | DRIVER_GEM |
> 			   DRIVER_ATOMIC | DRIVER_RENDER,
> 	.load = tegra_drm_load,
> 	.unload = tegra_drm_unload,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tegra/gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tegra/gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/tegra/gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tegra/gem.c	2019-08-31 15:01:12.086736188 -0500
>@@ -626,20 +626,19 @@
> 	.vunmap = tegra_gem_prime_vunmap,
> };
> 
>-struct dma_buf *tegra_gem_prime_export(struct drm_device *drm,
>-				       struct drm_gem_object *gem,
>+struct dma_buf *tegra_gem_prime_export(struct drm_gem_object *gem,
> 				       int flags)
> {
> 	DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
> 
> 	exp_info.exp_name = KBUILD_MODNAME;
>-	exp_info.owner = drm->driver->fops->owner;
>+	exp_info.owner = gem->dev->driver->fops->owner;
> 	exp_info.ops = &tegra_gem_prime_dmabuf_ops;
> 	exp_info.size = gem->size;
> 	exp_info.flags = flags;
> 	exp_info.priv = gem;
> 
>-	return drm_gem_dmabuf_export(drm, &exp_info);
>+	return drm_gem_dmabuf_export(gem->dev, &exp_info);
> }
> 
> struct drm_gem_object *tegra_gem_prime_import(struct drm_device *drm,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tegra/gem.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/tegra/gem.h
>--- linux-5.3-rc6/drivers/gpu/drm/tegra/gem.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tegra/gem.h	2019-08-31 15:01:12.086736188 -0500
>@@ -70,8 +70,7 @@
> int __tegra_gem_mmap(struct drm_gem_object *gem, struct vm_area_struct *vma);
> int tegra_drm_mmap(struct file *file, struct vm_area_struct *vma);
> 
>-struct dma_buf *tegra_gem_prime_export(struct drm_device *drm,
>-				       struct drm_gem_object *gem,
>+struct dma_buf *tegra_gem_prime_export(struct drm_gem_object *gem,
> 				       int flags);
> struct drm_gem_object *tegra_gem_prime_import(struct drm_device *drm,
> 					      struct dma_buf *buf);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_crtc.c	2019-08-31 15:01:12.096736189 -0500
>@@ -4,16 +4,20 @@
>  * Author: Rob Clark <robdclark@gmail.com>
>  */
> 
>+#include <linux/delay.h>
>+#include <linux/dma-mapping.h>
>+#include <linux/of_graph.h>
>+#include <linux/pm_runtime.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
>-#include <drm/drm_flip_work.h>
>-#include <drm/drm_plane_helper.h>
>-#include <linux/workqueue.h>
>-#include <linux/completion.h>
>-#include <linux/dma-mapping.h>
>-#include <linux/of_graph.h>
>-#include <linux/math64.h>
>+#include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_modeset_helper_vtables.h>
>+#include <drm/drm_print.h>
>+#include <drm/drm_vblank.h>
> 
> #include "tilcdc_drv.h"
> #include "tilcdc_regs.h"
>@@ -646,9 +650,6 @@
> static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
> 				    struct drm_crtc_state *state)
> {
>-	struct drm_display_mode *mode = &state->mode;
>-	int ret;
>-
> 	/* If we are not active we don't care */
> 	if (!state->active)
> 		return 0;
>@@ -660,12 +661,6 @@
> 		return -EINVAL;
> 	}
> 
>-	ret = tilcdc_crtc_mode_valid(crtc, mode);
>-	if (ret) {
>-		dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name);
>-		return -EINVAL;
>-	}
>-
> 	return 0;
> }
> 
>@@ -717,13 +712,6 @@
> 	.disable_vblank	= tilcdc_crtc_disable_vblank,
> };
> 
>-static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
>-		.mode_fixup     = tilcdc_crtc_mode_fixup,
>-		.atomic_check	= tilcdc_crtc_atomic_check,
>-		.atomic_enable	= tilcdc_crtc_atomic_enable,
>-		.atomic_disable	= tilcdc_crtc_atomic_disable,
>-};
>-
> int tilcdc_crtc_max_width(struct drm_crtc *crtc)
> {
> 	struct drm_device *dev = crtc->dev;
>@@ -738,7 +726,9 @@
> 	return max_width;
> }
> 
>-int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
>+static enum drm_mode_status
>+tilcdc_crtc_mode_valid(struct drm_crtc *crtc,
>+		       const struct drm_display_mode *mode)
> {
> 	struct tilcdc_drm_private *priv = crtc->dev->dev_private;
> 	unsigned int bandwidth;
>@@ -826,6 +816,14 @@
> 	return MODE_OK;
> }
> 
>+static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
>+	.mode_valid	= tilcdc_crtc_mode_valid,
>+	.mode_fixup	= tilcdc_crtc_mode_fixup,
>+	.atomic_check	= tilcdc_crtc_atomic_check,
>+	.atomic_enable	= tilcdc_crtc_atomic_enable,
>+	.atomic_disable	= tilcdc_crtc_atomic_disable,
>+};
>+
> void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
> 		const struct tilcdc_panel_info *info)
> {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_drv.c	2019-08-31 15:01:12.103736190 -0500
>@@ -7,19 +7,30 @@
> /* LCDC DRM driver, based on da8xx-fb */
> 
> #include <linux/component.h>
>+#include <linux/mod_devicetable.h>
>+#include <linux/module.h>
> #include <linux/pinctrl/consumer.h>
>-#include <linux/suspend.h>
>-#include <drm/drm_atomic.h>
>+#include <linux/platform_device.h>
>+#include <linux/pm_runtime.h>
>+
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_debugfs.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_irq.h>
>+#include <drm/drm_mm.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
>+
> 
> #include "tilcdc_drv.h"
>+#include "tilcdc_external.h"
>+#include "tilcdc_panel.h"
> #include "tilcdc_regs.h"
> #include "tilcdc_tfp410.h"
>-#include "tilcdc_panel.h"
>-#include "tilcdc_external.h"
> 
> static LIST_HEAD(module_list);
> 
>@@ -188,7 +199,6 @@
> 	drm_kms_helper_poll_fini(dev);
> 	drm_irq_uninstall(dev);
> 	drm_mode_config_cleanup(dev);
>-	tilcdc_remove_external_device(dev);
> 
> 	if (priv->clk)
> 		clk_put(priv->clk);
>@@ -501,8 +511,7 @@
> DEFINE_DRM_GEM_CMA_FOPS(fops);
> 
> static struct drm_driver tilcdc_driver = {
>-	.driver_features    = (DRIVER_GEM | DRIVER_MODESET |
>-			       DRIVER_PRIME | DRIVER_ATOMIC),
>+	.driver_features    = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.irq_handler        = tilcdc_irq,
> 	.gem_free_object_unlocked = drm_gem_cma_free_object,
> 	.gem_print_info     = drm_gem_cma_print_info,
>@@ -511,8 +520,6 @@
> 
> 	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
>-	.gem_prime_import	= drm_gem_prime_import,
>-	.gem_prime_export	= drm_gem_prime_export,
> 	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap		= drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_drv.h	2019-08-31 15:01:12.108736190 -0500
>@@ -7,21 +7,24 @@
> #ifndef __TILCDC_DRV_H__
> #define __TILCDC_DRV_H__
> 
>-#include <linux/clk.h>
> #include <linux/cpufreq.h>
>-#include <linux/module.h>
>-#include <linux/platform_device.h>
>-#include <linux/pm.h>
>-#include <linux/pm_runtime.h>
>-#include <linux/slab.h>
>-#include <linux/of.h>
>-#include <linux/of_device.h>
>-#include <linux/list.h>
>-
>-#include <drm/drmP.h>
>-#include <drm/drm_bridge.h>
>-#include <drm/drm_fb_cma_helper.h>
>-#include <drm/drm_gem_cma_helper.h>
>+#include <linux/irqreturn.h>
>+
>+#include <drm/drm_print.h>
>+
>+struct clk;
>+struct workqueue_struct;
>+
>+struct drm_connector;
>+struct drm_connector_helper_funcs;
>+struct drm_crtc;
>+struct drm_device;
>+struct drm_display_mode;
>+struct drm_encoder;
>+struct drm_framebuffer;
>+struct drm_minor;
>+struct drm_pending_vblank_event;
>+struct drm_plane;
> 
> /* Defaulting to pixel clock defined on AM335x */
> #define TILCDC_DEFAULT_MAX_PIXELCLOCK  126000
>@@ -74,7 +77,6 @@
> 
> 	struct drm_encoder *external_encoder;
> 	struct drm_connector *external_connector;
>-	const struct drm_connector_helper_funcs *connector_funcs;
> 
> 	bool is_registered;
> 	bool is_componentized;
>@@ -156,7 +158,6 @@
> 		const struct tilcdc_panel_info *info);
> void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
> 					bool simulate_vesa_sync);
>-int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode);
> int tilcdc_crtc_max_width(struct drm_crtc *crtc);
> void tilcdc_crtc_shutdown(struct drm_crtc *crtc);
> int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_external.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_external.c
>--- linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_external.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_external.c	2019-08-31 15:01:12.113736191 -0500
>@@ -6,6 +6,7 @@
> 
> #include <linux/component.h>
> #include <linux/of_graph.h>
>+
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_of.h>
> 
>@@ -37,64 +38,6 @@
> 		.raster_order           = 0,
> };
> 
>-static int tilcdc_external_mode_valid(struct drm_connector *connector,
>-				      struct drm_display_mode *mode)
>-{
>-	struct tilcdc_drm_private *priv = connector->dev->dev_private;
>-	int ret;
>-
>-	ret = tilcdc_crtc_mode_valid(priv->crtc, mode);
>-	if (ret != MODE_OK)
>-		return ret;
>-
>-	BUG_ON(priv->external_connector != connector);
>-	BUG_ON(!priv->connector_funcs);
>-
>-	/* If the connector has its own mode_valid call it. */
>-	if (!IS_ERR(priv->connector_funcs) &&
>-	    priv->connector_funcs->mode_valid)
>-		return priv->connector_funcs->mode_valid(connector, mode);
>-
>-	return MODE_OK;
>-}
>-
>-static int tilcdc_add_external_connector(struct drm_device *dev,
>-					 struct drm_connector *connector)
>-{
>-	struct tilcdc_drm_private *priv = dev->dev_private;
>-	struct drm_connector_helper_funcs *connector_funcs;
>-
>-	/* There should never be more than one connector */
>-	if (WARN_ON(priv->external_connector))
>-		return -EINVAL;
>-
>-	priv->external_connector = connector;
>-	connector_funcs = devm_kzalloc(dev->dev, sizeof(*connector_funcs),
>-				       GFP_KERNEL);
>-	if (!connector_funcs)
>-		return -ENOMEM;
>-
>-	/* connector->helper_private contains always struct
>-	 * connector_helper_funcs pointer. For tilcdc crtc to have a
>-	 * say if a specific mode is Ok, we need to install our own
>-	 * helper functions. In our helper functions we copy
>-	 * everything else but use our own mode_valid() (above).
>-	 */
>-	if (connector->helper_private) {
>-		priv->connector_funcs =	connector->helper_private;
>-		*connector_funcs = *priv->connector_funcs;
>-	} else {
>-		priv->connector_funcs = ERR_PTR(-ENOENT);
>-	}
>-	connector_funcs->mode_valid = tilcdc_external_mode_valid;
>-	drm_connector_helper_add(connector, connector_funcs);
>-
>-	dev_dbg(dev->dev, "External connector '%s' connected\n",
>-		connector->name);
>-
>-	return 0;
>-}
>-
> static
> struct drm_connector *tilcdc_encoder_find_connector(struct drm_device *ddev,
> 						    struct drm_encoder *encoder)
>@@ -115,7 +58,6 @@
> int tilcdc_add_component_encoder(struct drm_device *ddev)
> {
> 	struct tilcdc_drm_private *priv = ddev->dev_private;
>-	struct drm_connector *connector;
> 	struct drm_encoder *encoder;
> 
> 	list_for_each_entry(encoder, &ddev->mode_config.encoder_list, head)
>@@ -127,28 +69,17 @@
> 		return -ENODEV;
> 	}
> 
>-	connector = tilcdc_encoder_find_connector(ddev, encoder);
>+	priv->external_connector =
>+		tilcdc_encoder_find_connector(ddev, encoder);
> 
>-	if (!connector)
>+	if (!priv->external_connector)
> 		return -ENODEV;
> 
> 	/* Only tda998x is supported at the moment. */
> 	tilcdc_crtc_set_simulate_vesa_sync(priv->crtc, true);
> 	tilcdc_crtc_set_panel_info(priv->crtc, &panel_info_tda998x);
> 
>-	return tilcdc_add_external_connector(ddev, connector);
>-}
>-
>-void tilcdc_remove_external_device(struct drm_device *dev)
>-{
>-	struct tilcdc_drm_private *priv = dev->dev_private;
>-
>-	/* Restore the original helper functions, if any. */
>-	if (IS_ERR(priv->connector_funcs))
>-		drm_connector_helper_add(priv->external_connector, NULL);
>-	else if (priv->connector_funcs)
>-		drm_connector_helper_add(priv->external_connector,
>-					 priv->connector_funcs);
>+	return 0;
> }
> 
> static const struct drm_encoder_funcs tilcdc_external_encoder_funcs = {
>@@ -159,7 +90,6 @@
> int tilcdc_attach_bridge(struct drm_device *ddev, struct drm_bridge *bridge)
> {
> 	struct tilcdc_drm_private *priv = ddev->dev_private;
>-	struct drm_connector *connector;
> 	int ret;
> 
> 	priv->external_encoder->possible_crtcs = BIT(0);
>@@ -172,13 +102,12 @@
> 
> 	tilcdc_crtc_set_panel_info(priv->crtc, &panel_info_default);
> 
>-	connector = tilcdc_encoder_find_connector(ddev, priv->external_encoder);
>-	if (!connector)
>+	priv->external_connector =
>+		tilcdc_encoder_find_connector(ddev, priv->external_encoder);
>+	if (!priv->external_connector)
> 		return -ENODEV;
> 
>-	ret = tilcdc_add_external_connector(ddev, connector);
>-
>-	return ret;
>+	return 0;
> }
> 
> int tilcdc_attach_external_device(struct drm_device *ddev)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_external.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_external.h
>--- linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_external.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_external.h	2019-08-31 15:01:12.117736191 -0500
>@@ -8,7 +8,6 @@
> #define __TILCDC_EXTERNAL_H__
> 
> int tilcdc_add_component_encoder(struct drm_device *dev);
>-void tilcdc_remove_external_device(struct drm_device *dev);
> int tilcdc_get_external_components(struct device *dev,
> 				   struct component_match **match);
> int tilcdc_attach_external_device(struct drm_device *ddev);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_panel.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_panel.c
>--- linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_panel.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_panel.c	2019-08-31 15:01:12.122736192 -0500
>@@ -4,14 +4,17 @@
>  * Author: Rob Clark <robdclark@gmail.com>
>  */
> 
>-#include <linux/pinctrl/pinmux.h>
>-#include <linux/pinctrl/consumer.h>
>-#include <linux/backlight.h>
> #include <linux/gpio/consumer.h>
>+#include <linux/pinctrl/consumer.h>
>+#include <linux/platform_device.h>
>+
> #include <video/display_timing.h>
> #include <video/of_display_timing.h>
> #include <video/videomode.h>
>-#include <drm/drm_atomic_helper.h>
>+
>+#include <drm/drm_atomic_state_helper.h>
>+#include <drm/drm_connector.h>
>+#include <drm/drm_modeset_helper_vtables.h>
> #include <drm/drm_probe_helper.h>
> 
> #include "tilcdc_drv.h"
>@@ -160,14 +163,6 @@
> 	return i;
> }
> 
>-static int panel_connector_mode_valid(struct drm_connector *connector,
>-		  struct drm_display_mode *mode)
>-{
>-	struct tilcdc_drm_private *priv = connector->dev->dev_private;
>-	/* our only constraints are what the crtc can generate: */
>-	return tilcdc_crtc_mode_valid(priv->crtc, mode);
>-}
>-
> static struct drm_encoder *panel_connector_best_encoder(
> 		struct drm_connector *connector)
> {
>@@ -185,7 +180,6 @@
> 
> static const struct drm_connector_helper_funcs panel_connector_helper_funcs = {
> 	.get_modes          = panel_connector_get_modes,
>-	.mode_valid         = panel_connector_mode_valid,
> 	.best_encoder       = panel_connector_best_encoder,
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_plane.c	2019-08-31 15:01:12.129736192 -0500
>@@ -4,12 +4,10 @@
>  * Author: Jyri Sarha <jsarha@ti.com>
>  */
> 
>-#include <drm/drmP.h>
>-
> #include <drm/drm_atomic.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_atomic_helper.h>
>-#include <uapi/drm/drm_fourcc.h>
>+#include <drm/drm_fourcc.h>
> 
> #include "tilcdc_drv.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
>--- linux-5.3-rc6/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c	2019-08-31 15:01:12.134736193 -0500
>@@ -4,12 +4,14 @@
>  * Author: Rob Clark <robdclark@gmail.com>
>  */
> 
>-#include <linux/i2c.h>
> #include <linux/gpio.h>
>+#include <linux/mod_devicetable.h>
> #include <linux/of_gpio.h>
>-#include <linux/pinctrl/pinmux.h>
>-#include <linux/pinctrl/consumer.h>
>+#include <linux/platform_device.h>
>+
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_encoder.h>
>+#include <drm/drm_modeset_helper_vtables.h>
> #include <drm/drm_probe_helper.h>
> 
> #include "tilcdc_drv.h"
>@@ -173,14 +175,6 @@
> 	return ret;
> }
> 
>-static int tfp410_connector_mode_valid(struct drm_connector *connector,
>-		  struct drm_display_mode *mode)
>-{
>-	struct tilcdc_drm_private *priv = connector->dev->dev_private;
>-	/* our only constraints are what the crtc can generate: */
>-	return tilcdc_crtc_mode_valid(priv->crtc, mode);
>-}
>-
> static struct drm_encoder *tfp410_connector_best_encoder(
> 		struct drm_connector *connector)
> {
>@@ -199,7 +193,6 @@
> 
> static const struct drm_connector_helper_funcs tfp410_connector_helper_funcs = {
> 	.get_modes          = tfp410_connector_get_modes,
>-	.mode_valid         = tfp410_connector_mode_valid,
> 	.best_encoder       = tfp410_connector_best_encoder,
> };
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tiny/gm12u320.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/gm12u320.c
>--- linux-5.3-rc6/drivers/gpu/drm/tiny/gm12u320.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/gm12u320.c	2019-08-31 15:01:12.134736193 -0500
>@@ -0,0 +1,814 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * Copyright 2019 Hans de Goede <hdegoede@redhat.com>
>+ */
>+
>+#include <linux/dma-buf.h>
>+#include <linux/module.h>
>+#include <linux/usb.h>
>+
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_atomic_state_helper.h>
>+#include <drm/drm_connector.h>
>+#include <drm/drm_damage_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_fb_helper.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_format_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_gem_shmem_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_ioctl.h>
>+#include <drm/drm_modeset_helper_vtables.h>
>+#include <drm/drm_probe_helper.h>
>+#include <drm/drm_simple_kms_helper.h>
>+#include <drm/drm_vblank.h>
>+
>+static bool eco_mode;
>+module_param(eco_mode, bool, 0644);
>+MODULE_PARM_DESC(eco_mode, "Turn on Eco mode (less bright, more silent)");
>+
>+#define DRIVER_NAME		"gm12u320"
>+#define DRIVER_DESC		"Grain Media GM12U320 USB projector display"
>+#define DRIVER_DATE		"2019"
>+#define DRIVER_MAJOR		1
>+#define DRIVER_MINOR		0
>+#define DRIVER_PATCHLEVEL	1
>+
>+/*
>+ * The DLP has an actual width of 854 pixels, but that is not a multiple
>+ * of 8, breaking things left and right, so we export a width of 848.
>+ */
>+#define GM12U320_USER_WIDTH		848
>+#define GM12U320_REAL_WIDTH		854
>+#define GM12U320_HEIGHT			480
>+
>+#define GM12U320_BLOCK_COUNT		20
>+
>+#define MISC_RCV_EPT			1
>+#define DATA_RCV_EPT			2
>+#define DATA_SND_EPT			3
>+#define MISC_SND_EPT			4
>+
>+#define DATA_BLOCK_HEADER_SIZE		84
>+#define DATA_BLOCK_CONTENT_SIZE		64512
>+#define DATA_BLOCK_FOOTER_SIZE		20
>+#define DATA_BLOCK_SIZE			(DATA_BLOCK_HEADER_SIZE + \
>+					 DATA_BLOCK_CONTENT_SIZE + \
>+					 DATA_BLOCK_FOOTER_SIZE)
>+#define DATA_LAST_BLOCK_CONTENT_SIZE	4032
>+#define DATA_LAST_BLOCK_SIZE		(DATA_BLOCK_HEADER_SIZE + \
>+					 DATA_LAST_BLOCK_CONTENT_SIZE + \
>+					 DATA_BLOCK_FOOTER_SIZE)
>+
>+#define CMD_SIZE			31
>+#define READ_STATUS_SIZE		13
>+#define MISC_VALUE_SIZE			4
>+
>+#define CMD_TIMEOUT			msecs_to_jiffies(200)
>+#define DATA_TIMEOUT			msecs_to_jiffies(1000)
>+#define IDLE_TIMEOUT			msecs_to_jiffies(2000)
>+#define FIRST_FRAME_TIMEOUT		msecs_to_jiffies(2000)
>+
>+#define MISC_REQ_GET_SET_ECO_A		0xff
>+#define MISC_REQ_GET_SET_ECO_B		0x35
>+/* Windows driver does once every second, with arg d = 1, other args 0 */
>+#define MISC_REQ_UNKNOWN1_A		0xff
>+#define MISC_REQ_UNKNOWN1_B		0x38
>+/* Windows driver does this on init, with arg a, b = 0, c = 0xa0, d = 4 */
>+#define MISC_REQ_UNKNOWN2_A		0xa5
>+#define MISC_REQ_UNKNOWN2_B		0x00
>+
>+struct gm12u320_device {
>+	struct drm_device	         dev;
>+	struct drm_simple_display_pipe   pipe;
>+	struct drm_connector	         conn;
>+	struct usb_device               *udev;
>+	unsigned char                   *cmd_buf;
>+	unsigned char                   *data_buf[GM12U320_BLOCK_COUNT];
>+	bool                             pipe_enabled;
>+	struct {
>+		bool                     run;
>+		struct workqueue_struct *workq;
>+		struct work_struct       work;
>+		wait_queue_head_t        waitq;
>+		struct mutex             lock;
>+		struct drm_framebuffer  *fb;
>+		struct drm_rect          rect;
>+	} fb_update;
>+};
>+
>+static const char cmd_data[CMD_SIZE] = {
>+	0x55, 0x53, 0x42, 0x43, 0x00, 0x00, 0x00, 0x00,
>+	0x68, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x10, 0xff,
>+	0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x80, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
>+};
>+
>+static const char cmd_draw[CMD_SIZE] = {
>+	0x55, 0x53, 0x42, 0x43, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0xfe,
>+	0x00, 0x00, 0x00, 0xc0, 0xd1, 0x05, 0x00, 0x40,
>+	0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00
>+};
>+
>+static const char cmd_misc[CMD_SIZE] = {
>+	0x55, 0x53, 0x42, 0x43, 0x00, 0x00, 0x00, 0x00,
>+	0x04, 0x00, 0x00, 0x00, 0x80, 0x01, 0x10, 0xfd,
>+	0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
>+};
>+
>+static const char data_block_header[DATA_BLOCK_HEADER_SIZE] = {
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0xfb, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x04, 0x15, 0x00, 0x00, 0xfc, 0x00, 0x00,
>+	0x01, 0x00, 0x00, 0xdb
>+};
>+
>+static const char data_last_block_header[DATA_BLOCK_HEADER_SIZE] = {
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0xfb, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x2a, 0x00, 0x20, 0x00, 0xc0, 0x0f, 0x00, 0x00,
>+	0x01, 0x00, 0x00, 0xd7
>+};
>+
>+static const char data_block_footer[DATA_BLOCK_FOOTER_SIZE] = {
>+	0xfb, 0x14, 0x02, 0x20, 0x00, 0x00, 0x00, 0x00,
>+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+	0x80, 0x00, 0x00, 0x4f
>+};
>+
>+static int gm12u320_usb_alloc(struct gm12u320_device *gm12u320)
>+{
>+	int i, block_size;
>+	const char *hdr;
>+
>+	gm12u320->cmd_buf = kmalloc(CMD_SIZE, GFP_KERNEL);
>+	if (!gm12u320->cmd_buf)
>+		return -ENOMEM;
>+
>+	for (i = 0; i < GM12U320_BLOCK_COUNT; i++) {
>+		if (i == GM12U320_BLOCK_COUNT - 1) {
>+			block_size = DATA_LAST_BLOCK_SIZE;
>+			hdr = data_last_block_header;
>+		} else {
>+			block_size = DATA_BLOCK_SIZE;
>+			hdr = data_block_header;
>+		}
>+
>+		gm12u320->data_buf[i] = kzalloc(block_size, GFP_KERNEL);
>+		if (!gm12u320->data_buf[i])
>+			return -ENOMEM;
>+
>+		memcpy(gm12u320->data_buf[i], hdr, DATA_BLOCK_HEADER_SIZE);
>+		memcpy(gm12u320->data_buf[i] +
>+				(block_size - DATA_BLOCK_FOOTER_SIZE),
>+		       data_block_footer, DATA_BLOCK_FOOTER_SIZE);
>+	}
>+
>+	gm12u320->fb_update.workq = create_singlethread_workqueue(DRIVER_NAME);
>+	if (!gm12u320->fb_update.workq)
>+		return -ENOMEM;
>+
>+	return 0;
>+}
>+
>+static void gm12u320_usb_free(struct gm12u320_device *gm12u320)
>+{
>+	int i;
>+
>+	if (gm12u320->fb_update.workq)
>+		destroy_workqueue(gm12u320->fb_update.workq);
>+
>+	for (i = 0; i < GM12U320_BLOCK_COUNT; i++)
>+		kfree(gm12u320->data_buf[i]);
>+
>+	kfree(gm12u320->cmd_buf);
>+}
>+
>+static int gm12u320_misc_request(struct gm12u320_device *gm12u320,
>+				 u8 req_a, u8 req_b,
>+				 u8 arg_a, u8 arg_b, u8 arg_c, u8 arg_d)
>+{
>+	int ret, len;
>+
>+	memcpy(gm12u320->cmd_buf, &cmd_misc, CMD_SIZE);
>+	gm12u320->cmd_buf[20] = req_a;
>+	gm12u320->cmd_buf[21] = req_b;
>+	gm12u320->cmd_buf[22] = arg_a;
>+	gm12u320->cmd_buf[23] = arg_b;
>+	gm12u320->cmd_buf[24] = arg_c;
>+	gm12u320->cmd_buf[25] = arg_d;
>+
>+	/* Send request */
>+	ret = usb_bulk_msg(gm12u320->udev,
>+			   usb_sndbulkpipe(gm12u320->udev, MISC_SND_EPT),
>+			   gm12u320->cmd_buf, CMD_SIZE, &len, CMD_TIMEOUT);
>+	if (ret || len != CMD_SIZE) {
>+		dev_err(&gm12u320->udev->dev, "Misc. req. error %d\n", ret);
>+		return -EIO;
>+	}
>+
>+	/* Read value */
>+	ret = usb_bulk_msg(gm12u320->udev,
>+			   usb_rcvbulkpipe(gm12u320->udev, MISC_RCV_EPT),
>+			   gm12u320->cmd_buf, MISC_VALUE_SIZE, &len,
>+			   DATA_TIMEOUT);
>+	if (ret || len != MISC_VALUE_SIZE) {
>+		dev_err(&gm12u320->udev->dev, "Misc. value error %d\n", ret);
>+		return -EIO;
>+	}
>+	/* cmd_buf[0] now contains the read value, which we don't use */
>+
>+	/* Read status */
>+	ret = usb_bulk_msg(gm12u320->udev,
>+			   usb_rcvbulkpipe(gm12u320->udev, MISC_RCV_EPT),
>+			   gm12u320->cmd_buf, READ_STATUS_SIZE, &len,
>+			   CMD_TIMEOUT);
>+	if (ret || len != READ_STATUS_SIZE) {
>+		dev_err(&gm12u320->udev->dev, "Misc. status error %d\n", ret);
>+		return -EIO;
>+	}
>+
>+	return 0;
>+}
>+
>+static void gm12u320_32bpp_to_24bpp_packed(u8 *dst, u8 *src, int len)
>+{
>+	while (len--) {
>+		*dst++ = *src++;
>+		*dst++ = *src++;
>+		*dst++ = *src++;
>+		src++;
>+	}
>+}
>+
>+static void gm12u320_copy_fb_to_blocks(struct gm12u320_device *gm12u320)
>+{
>+	int block, dst_offset, len, remain, ret, x1, x2, y1, y2;
>+	struct drm_framebuffer *fb;
>+	void *vaddr;
>+	u8 *src;
>+
>+	mutex_lock(&gm12u320->fb_update.lock);
>+
>+	if (!gm12u320->fb_update.fb)
>+		goto unlock;
>+
>+	fb = gm12u320->fb_update.fb;
>+	x1 = gm12u320->fb_update.rect.x1;
>+	x2 = gm12u320->fb_update.rect.x2;
>+	y1 = gm12u320->fb_update.rect.y1;
>+	y2 = gm12u320->fb_update.rect.y2;
>+
>+	vaddr = drm_gem_shmem_vmap(fb->obj[0]);
>+	if (IS_ERR(vaddr)) {
>+		DRM_ERROR("failed to vmap fb: %ld\n", PTR_ERR(vaddr));
>+		goto put_fb;
>+	}
>+
>+	if (fb->obj[0]->import_attach) {
>+		ret = dma_buf_begin_cpu_access(
>+			fb->obj[0]->import_attach->dmabuf, DMA_FROM_DEVICE);
>+		if (ret) {
>+			DRM_ERROR("dma_buf_begin_cpu_access err: %d\n", ret);
>+			goto vunmap;
>+		}
>+	}
>+
>+	src = vaddr + y1 * fb->pitches[0] + x1 * 4;
>+
>+	x1 += (GM12U320_REAL_WIDTH - GM12U320_USER_WIDTH) / 2;
>+	x2 += (GM12U320_REAL_WIDTH - GM12U320_USER_WIDTH) / 2;
>+
>+	for (; y1 < y2; y1++) {
>+		remain = 0;
>+		len = (x2 - x1) * 3;
>+		dst_offset = (y1 * GM12U320_REAL_WIDTH + x1) * 3;
>+		block = dst_offset / DATA_BLOCK_CONTENT_SIZE;
>+		dst_offset %= DATA_BLOCK_CONTENT_SIZE;
>+
>+		if ((dst_offset + len) > DATA_BLOCK_CONTENT_SIZE) {
>+			remain = dst_offset + len - DATA_BLOCK_CONTENT_SIZE;
>+			len = DATA_BLOCK_CONTENT_SIZE - dst_offset;
>+		}
>+
>+		dst_offset += DATA_BLOCK_HEADER_SIZE;
>+		len /= 3;
>+
>+		gm12u320_32bpp_to_24bpp_packed(
>+			gm12u320->data_buf[block] + dst_offset,
>+			src, len);
>+
>+		if (remain) {
>+			block++;
>+			dst_offset = DATA_BLOCK_HEADER_SIZE;
>+			gm12u320_32bpp_to_24bpp_packed(
>+				gm12u320->data_buf[block] + dst_offset,
>+				src + len * 4, remain / 3);
>+		}
>+		src += fb->pitches[0];
>+	}
>+
>+	if (fb->obj[0]->import_attach) {
>+		ret = dma_buf_end_cpu_access(fb->obj[0]->import_attach->dmabuf,
>+					     DMA_FROM_DEVICE);
>+		if (ret)
>+			DRM_ERROR("dma_buf_end_cpu_access err: %d\n", ret);
>+	}
>+vunmap:
>+	drm_gem_shmem_vunmap(fb->obj[0], vaddr);
>+put_fb:
>+	drm_framebuffer_put(fb);
>+	gm12u320->fb_update.fb = NULL;
>+unlock:
>+	mutex_unlock(&gm12u320->fb_update.lock);
>+}
>+
>+static int gm12u320_fb_update_ready(struct gm12u320_device *gm12u320)
>+{
>+	int ret;
>+
>+	mutex_lock(&gm12u320->fb_update.lock);
>+	ret = !gm12u320->fb_update.run || gm12u320->fb_update.fb != NULL;
>+	mutex_unlock(&gm12u320->fb_update.lock);
>+
>+	return ret;
>+}
>+
>+static void gm12u320_fb_update_work(struct work_struct *work)
>+{
>+	struct gm12u320_device *gm12u320 =
>+		container_of(work, struct gm12u320_device, fb_update.work);
>+	int draw_status_timeout = FIRST_FRAME_TIMEOUT;
>+	int block, block_size, len;
>+	int frame = 0;
>+	int ret = 0;
>+
>+	while (gm12u320->fb_update.run) {
>+		gm12u320_copy_fb_to_blocks(gm12u320);
>+
>+		for (block = 0; block < GM12U320_BLOCK_COUNT; block++) {
>+			if (block == GM12U320_BLOCK_COUNT - 1)
>+				block_size = DATA_LAST_BLOCK_SIZE;
>+			else
>+				block_size = DATA_BLOCK_SIZE;
>+
>+			/* Send data command to device */
>+			memcpy(gm12u320->cmd_buf, cmd_data, CMD_SIZE);
>+			gm12u320->cmd_buf[8] = block_size & 0xff;
>+			gm12u320->cmd_buf[9] = block_size >> 8;
>+			gm12u320->cmd_buf[20] = 0xfc - block * 4;
>+			gm12u320->cmd_buf[21] = block | (frame << 7);
>+
>+			ret = usb_bulk_msg(gm12u320->udev,
>+				usb_sndbulkpipe(gm12u320->udev, DATA_SND_EPT),
>+				gm12u320->cmd_buf, CMD_SIZE, &len,
>+				CMD_TIMEOUT);
>+			if (ret || len != CMD_SIZE)
>+				goto err;
>+
>+			/* Send data block to device */
>+			ret = usb_bulk_msg(gm12u320->udev,
>+				usb_sndbulkpipe(gm12u320->udev, DATA_SND_EPT),
>+				gm12u320->data_buf[block], block_size,
>+				&len, DATA_TIMEOUT);
>+			if (ret || len != block_size)
>+				goto err;
>+
>+			/* Read status */
>+			ret = usb_bulk_msg(gm12u320->udev,
>+				usb_rcvbulkpipe(gm12u320->udev, DATA_RCV_EPT),
>+				gm12u320->cmd_buf, READ_STATUS_SIZE, &len,
>+				CMD_TIMEOUT);
>+			if (ret || len != READ_STATUS_SIZE)
>+				goto err;
>+		}
>+
>+		/* Send draw command to device */
>+		memcpy(gm12u320->cmd_buf, cmd_draw, CMD_SIZE);
>+		ret = usb_bulk_msg(gm12u320->udev,
>+			usb_sndbulkpipe(gm12u320->udev, DATA_SND_EPT),
>+			gm12u320->cmd_buf, CMD_SIZE, &len, CMD_TIMEOUT);
>+		if (ret || len != CMD_SIZE)
>+			goto err;
>+
>+		/* Read status */
>+		ret = usb_bulk_msg(gm12u320->udev,
>+			usb_rcvbulkpipe(gm12u320->udev, DATA_RCV_EPT),
>+			gm12u320->cmd_buf, READ_STATUS_SIZE, &len,
>+			draw_status_timeout);
>+		if (ret || len != READ_STATUS_SIZE)
>+			goto err;
>+
>+		draw_status_timeout = CMD_TIMEOUT;
>+		frame = !frame;
>+
>+		/*
>+		 * We must draw a frame every 2s otherwise the projector
>+		 * switches back to showing its logo.
>+		 */
>+		wait_event_timeout(gm12u320->fb_update.waitq,
>+				   gm12u320_fb_update_ready(gm12u320),
>+				   IDLE_TIMEOUT);
>+	}
>+	return;
>+err:
>+	/* Do not log errors caused by module unload or device unplug */
>+	if (ret != -ECONNRESET && ret != -ESHUTDOWN)
>+		dev_err(&gm12u320->udev->dev, "Frame update error: %d\n", ret);
>+}
>+
>+static void gm12u320_fb_mark_dirty(struct drm_framebuffer *fb,
>+				   struct drm_rect *dirty)
>+{
>+	struct gm12u320_device *gm12u320 = fb->dev->dev_private;
>+	struct drm_framebuffer *old_fb = NULL;
>+	bool wakeup = false;
>+
>+	mutex_lock(&gm12u320->fb_update.lock);
>+
>+	if (gm12u320->fb_update.fb != fb) {
>+		old_fb = gm12u320->fb_update.fb;
>+		drm_framebuffer_get(fb);
>+		gm12u320->fb_update.fb = fb;
>+		gm12u320->fb_update.rect = *dirty;
>+		wakeup = true;
>+	} else {
>+		struct drm_rect *rect = &gm12u320->fb_update.rect;
>+
>+		rect->x1 = min(rect->x1, dirty->x1);
>+		rect->y1 = min(rect->y1, dirty->y1);
>+		rect->x2 = max(rect->x2, dirty->x2);
>+		rect->y2 = max(rect->y2, dirty->y2);
>+	}
>+
>+	mutex_unlock(&gm12u320->fb_update.lock);
>+
>+	if (wakeup)
>+		wake_up(&gm12u320->fb_update.waitq);
>+
>+	if (old_fb)
>+		drm_framebuffer_put(old_fb);
>+}
>+
>+static void gm12u320_start_fb_update(struct gm12u320_device *gm12u320)
>+{
>+	mutex_lock(&gm12u320->fb_update.lock);
>+	gm12u320->fb_update.run = true;
>+	mutex_unlock(&gm12u320->fb_update.lock);
>+
>+	queue_work(gm12u320->fb_update.workq, &gm12u320->fb_update.work);
>+}
>+
>+static void gm12u320_stop_fb_update(struct gm12u320_device *gm12u320)
>+{
>+	mutex_lock(&gm12u320->fb_update.lock);
>+	gm12u320->fb_update.run = false;
>+	mutex_unlock(&gm12u320->fb_update.lock);
>+
>+	wake_up(&gm12u320->fb_update.waitq);
>+	cancel_work_sync(&gm12u320->fb_update.work);
>+
>+	mutex_lock(&gm12u320->fb_update.lock);
>+	if (gm12u320->fb_update.fb) {
>+		drm_framebuffer_put(gm12u320->fb_update.fb);
>+		gm12u320->fb_update.fb = NULL;
>+	}
>+	mutex_unlock(&gm12u320->fb_update.lock);
>+}
>+
>+static int gm12u320_set_ecomode(struct gm12u320_device *gm12u320)
>+{
>+	return gm12u320_misc_request(gm12u320, MISC_REQ_GET_SET_ECO_A,
>+				     MISC_REQ_GET_SET_ECO_B, 0x01 /* set */,
>+				     eco_mode ? 0x01 : 0x00, 0x00, 0x01);
>+}
>+
>+/* ------------------------------------------------------------------ */
>+/* gm12u320 connector						      */
>+
>+/*
>+ *Â We use fake EDID info so that userspace know that it is dealing with
>+ * an Acer projector, rather then listing this as an "unknown" monitor.
>+ * Note this assumes this driver is only ever used with the Acer C120, if we
>+ * add support for other devices the vendor and model should be parameterized.
>+ */
>+static struct edid gm12u320_edid = {
>+	.header		= { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 },
>+	.mfg_id		= { 0x04, 0x72 },	/* "ACR" */
>+	.prod_code	= { 0x20, 0xc1 },	/* C120h */
>+	.serial		= 0xaa55aa55,
>+	.mfg_week	= 1,
>+	.mfg_year	= 16,
>+	.version	= 1,			/* EDID 1.3 */
>+	.revision	= 3,			/* EDID 1.3 */
>+	.input		= 0x08,			/* Analog input */
>+	.features	= 0x0a,			/* Pref timing in DTD 1 */
>+	.standard_timings = { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 },
>+			      { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } },
>+	.detailed_timings = { {
>+		.pixel_clock = 3383,
>+		/* hactive = 848, hblank = 256 */
>+		.data.pixel_data.hactive_lo = 0x50,
>+		.data.pixel_data.hblank_lo = 0x00,
>+		.data.pixel_data.hactive_hblank_hi = 0x31,
>+		/* vactive = 480, vblank = 28 */
>+		.data.pixel_data.vactive_lo = 0xe0,
>+		.data.pixel_data.vblank_lo = 0x1c,
>+		.data.pixel_data.vactive_vblank_hi = 0x10,
>+		/* hsync offset 40 pw 128, vsync offset 1 pw 4 */
>+		.data.pixel_data.hsync_offset_lo = 0x28,
>+		.data.pixel_data.hsync_pulse_width_lo = 0x80,
>+		.data.pixel_data.vsync_offset_pulse_width_lo = 0x14,
>+		.data.pixel_data.hsync_vsync_offset_pulse_width_hi = 0x00,
>+		/* Digital separate syncs, hsync+, vsync+ */
>+		.data.pixel_data.misc = 0x1e,
>+	}, {
>+		.pixel_clock = 0,
>+		.data.other_data.type = 0xfd, /* Monitor ranges */
>+		.data.other_data.data.range.min_vfreq = 59,
>+		.data.other_data.data.range.max_vfreq = 61,
>+		.data.other_data.data.range.min_hfreq_khz = 29,
>+		.data.other_data.data.range.max_hfreq_khz = 32,
>+		.data.other_data.data.range.pixel_clock_mhz = 4, /* 40 MHz */
>+		.data.other_data.data.range.flags = 0,
>+		.data.other_data.data.range.formula.cvt = {
>+			0xa0, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 },
>+	}, {
>+		.pixel_clock = 0,
>+		.data.other_data.type = 0xfc, /* Model string */
>+		.data.other_data.data.str.str = {
>+			'P', 'r', 'o', 'j', 'e', 'c', 't', 'o', 'r', '\n',
>+			' ', ' ',  ' ' },
>+	}, {
>+		.pixel_clock = 0,
>+		.data.other_data.type = 0xfe, /* Unspecified text / padding */
>+		.data.other_data.data.str.str = {
>+			'\n', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
>+			' ', ' ',  ' ' },
>+	} },
>+	.checksum = 0x13,
>+};
>+
>+static int gm12u320_conn_get_modes(struct drm_connector *connector)
>+{
>+	drm_connector_update_edid_property(connector, &gm12u320_edid);
>+	return drm_add_edid_modes(connector, &gm12u320_edid);
>+}
>+
>+static const struct drm_connector_helper_funcs gm12u320_conn_helper_funcs = {
>+	.get_modes = gm12u320_conn_get_modes,
>+};
>+
>+static const struct drm_connector_funcs gm12u320_conn_funcs = {
>+	.fill_modes = drm_helper_probe_single_connector_modes,
>+	.destroy = drm_connector_cleanup,
>+	.reset = drm_atomic_helper_connector_reset,
>+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
>+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>+};
>+
>+static int gm12u320_conn_init(struct gm12u320_device *gm12u320)
>+{
>+	drm_connector_helper_add(&gm12u320->conn, &gm12u320_conn_helper_funcs);
>+	return drm_connector_init(&gm12u320->dev, &gm12u320->conn,
>+				  &gm12u320_conn_funcs, DRM_MODE_CONNECTOR_VGA);
>+}
>+
>+/* ------------------------------------------------------------------ */
>+/* gm12u320 (simple) display pipe				      */
>+
>+static void gm12u320_pipe_enable(struct drm_simple_display_pipe *pipe,
>+				 struct drm_crtc_state *crtc_state,
>+				 struct drm_plane_state *plane_state)
>+{
>+	struct gm12u320_device *gm12u320 = pipe->crtc.dev->dev_private;
>+	struct drm_rect rect = { 0, 0, GM12U320_USER_WIDTH, GM12U320_HEIGHT };
>+
>+	gm12u320_fb_mark_dirty(plane_state->fb, &rect);
>+	gm12u320_start_fb_update(gm12u320);
>+	gm12u320->pipe_enabled = true;
>+}
>+
>+static void gm12u320_pipe_disable(struct drm_simple_display_pipe *pipe)
>+{
>+	struct gm12u320_device *gm12u320 = pipe->crtc.dev->dev_private;
>+
>+	gm12u320_stop_fb_update(gm12u320);
>+	gm12u320->pipe_enabled = false;
>+}
>+
>+static void gm12u320_pipe_update(struct drm_simple_display_pipe *pipe,
>+				 struct drm_plane_state *old_state)
>+{
>+	struct drm_plane_state *state = pipe->plane.state;
>+	struct drm_crtc *crtc = &pipe->crtc;
>+	struct drm_rect rect;
>+
>+	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
>+		gm12u320_fb_mark_dirty(pipe->plane.state->fb, &rect);
>+
>+	if (crtc->state->event) {
>+		spin_lock_irq(&crtc->dev->event_lock);
>+		drm_crtc_send_vblank_event(crtc, crtc->state->event);
>+		crtc->state->event = NULL;
>+		spin_unlock_irq(&crtc->dev->event_lock);
>+	}
>+}
>+
>+static const struct drm_simple_display_pipe_funcs gm12u320_pipe_funcs = {
>+	.enable	    = gm12u320_pipe_enable,
>+	.disable    = gm12u320_pipe_disable,
>+	.update	    = gm12u320_pipe_update,
>+};
>+
>+static const uint32_t gm12u320_pipe_formats[] = {
>+	DRM_FORMAT_XRGB8888,
>+};
>+
>+static const uint64_t gm12u320_pipe_modifiers[] = {
>+	DRM_FORMAT_MOD_LINEAR,
>+	DRM_FORMAT_MOD_INVALID
>+};
>+
>+static void gm12u320_driver_release(struct drm_device *dev)
>+{
>+	struct gm12u320_device *gm12u320 = dev->dev_private;
>+
>+	gm12u320_usb_free(gm12u320);
>+	drm_mode_config_cleanup(dev);
>+	drm_dev_fini(dev);
>+	kfree(gm12u320);
>+}
>+
>+DEFINE_DRM_GEM_SHMEM_FOPS(gm12u320_fops);
>+
>+static struct drm_driver gm12u320_drm_driver = {
>+	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
>+
>+	.name		 = DRIVER_NAME,
>+	.desc		 = DRIVER_DESC,
>+	.date		 = DRIVER_DATE,
>+	.major		 = DRIVER_MAJOR,
>+	.minor		 = DRIVER_MINOR,
>+
>+	.release	 = gm12u320_driver_release,
>+	.fops		 = &gm12u320_fops,
>+	DRM_GEM_SHMEM_DRIVER_OPS,
>+};
>+
>+static const struct drm_mode_config_funcs gm12u320_mode_config_funcs = {
>+	.fb_create = drm_gem_fb_create_with_dirty,
>+	.atomic_check = drm_atomic_helper_check,
>+	.atomic_commit = drm_atomic_helper_commit,
>+};
>+
>+static int gm12u320_usb_probe(struct usb_interface *interface,
>+			      const struct usb_device_id *id)
>+{
>+	struct gm12u320_device *gm12u320;
>+	struct drm_device *dev;
>+	int ret;
>+
>+	/*
>+	 * The gm12u320 presents itself to the system as 2 usb mass-storage
>+	 * interfaces, we only care about / need the first one.
>+	 */
>+	if (interface->cur_altsetting->desc.bInterfaceNumber != 0)
>+		return -ENODEV;
>+
>+	gm12u320 = kzalloc(sizeof(*gm12u320), GFP_KERNEL);
>+	if (gm12u320 == NULL)
>+		return -ENOMEM;
>+
>+	gm12u320->udev = interface_to_usbdev(interface);
>+	INIT_WORK(&gm12u320->fb_update.work, gm12u320_fb_update_work);
>+	mutex_init(&gm12u320->fb_update.lock);
>+	init_waitqueue_head(&gm12u320->fb_update.waitq);
>+
>+	dev = &gm12u320->dev;
>+	ret = drm_dev_init(dev, &gm12u320_drm_driver, &interface->dev);
>+	if (ret) {
>+		kfree(gm12u320);
>+		return ret;
>+	}
>+	dev->dev_private = gm12u320;
>+
>+	drm_mode_config_init(dev);
>+	dev->mode_config.min_width = GM12U320_USER_WIDTH;
>+	dev->mode_config.max_width = GM12U320_USER_WIDTH;
>+	dev->mode_config.min_height = GM12U320_HEIGHT;
>+	dev->mode_config.max_height = GM12U320_HEIGHT;
>+	dev->mode_config.funcs = &gm12u320_mode_config_funcs;
>+
>+	ret = gm12u320_usb_alloc(gm12u320);
>+	if (ret)
>+		goto err_put;
>+
>+	ret = gm12u320_set_ecomode(gm12u320);
>+	if (ret)
>+		goto err_put;
>+
>+	ret = gm12u320_conn_init(gm12u320);
>+	if (ret)
>+		goto err_put;
>+
>+	ret = drm_simple_display_pipe_init(&gm12u320->dev,
>+					   &gm12u320->pipe,
>+					   &gm12u320_pipe_funcs,
>+					   gm12u320_pipe_formats,
>+					   ARRAY_SIZE(gm12u320_pipe_formats),
>+					   gm12u320_pipe_modifiers,
>+					   &gm12u320->conn);
>+	if (ret)
>+		goto err_put;
>+
>+	drm_mode_config_reset(dev);
>+
>+	usb_set_intfdata(interface, dev);
>+	ret = drm_dev_register(dev, 0);
>+	if (ret)
>+		goto err_put;
>+
>+	drm_fbdev_generic_setup(dev, dev->mode_config.preferred_depth);
>+
>+	return 0;
>+
>+err_put:
>+	drm_dev_put(dev);
>+	return ret;
>+}
>+
>+static void gm12u320_usb_disconnect(struct usb_interface *interface)
>+{
>+	struct drm_device *dev = usb_get_intfdata(interface);
>+	struct gm12u320_device *gm12u320 = dev->dev_private;
>+
>+	gm12u320_stop_fb_update(gm12u320);
>+	drm_dev_unplug(dev);
>+	drm_dev_put(dev);
>+}
>+
>+#ifdef CONFIG_PM
>+static int gm12u320_suspend(struct usb_interface *interface,
>+			    pm_message_t message)
>+{
>+	struct drm_device *dev = usb_get_intfdata(interface);
>+	struct gm12u320_device *gm12u320 = dev->dev_private;
>+
>+	if (gm12u320->pipe_enabled)
>+		gm12u320_stop_fb_update(gm12u320);
>+
>+	return 0;
>+}
>+
>+static int gm12u320_resume(struct usb_interface *interface)
>+{
>+	struct drm_device *dev = usb_get_intfdata(interface);
>+	struct gm12u320_device *gm12u320 = dev->dev_private;
>+
>+	gm12u320_set_ecomode(gm12u320);
>+	if (gm12u320->pipe_enabled)
>+		gm12u320_start_fb_update(gm12u320);
>+
>+	return 0;
>+}
>+#endif
>+
>+static const struct usb_device_id id_table[] = {
>+	{ USB_DEVICE(0x1de1, 0xc102) },
>+	{},
>+};
>+MODULE_DEVICE_TABLE(usb, id_table);
>+
>+static struct usb_driver gm12u320_usb_driver = {
>+	.name = "gm12u320",
>+	.probe = gm12u320_usb_probe,
>+	.disconnect = gm12u320_usb_disconnect,
>+	.id_table = id_table,
>+#ifdef CONFIG_PM
>+	.suspend = gm12u320_suspend,
>+	.resume = gm12u320_resume,
>+	.reset_resume = gm12u320_resume,
>+#endif
>+};
>+
>+module_usb_driver(gm12u320_usb_driver);
>+MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
>+MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tiny/hx8357d.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/hx8357d.c
>--- linux-5.3-rc6/drivers/gpu/drm/tiny/hx8357d.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/hx8357d.c	2019-08-31 15:01:12.233736201 -0500
>@@ -0,0 +1,304 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * DRM driver for the HX8357D LCD controller
>+ *
>+ * Copyright 2018 Broadcom
>+ * Copyright 2018 David Lechner <david@lechnology.com>
>+ * Copyright 2016 Noralf TrÃ¸nnes
>+ * Copyright (C) 2015 Adafruit Industries
>+ * Copyright (C) 2013 Christian Vogelgsang
>+ */
>+
>+#include <linux/backlight.h>
>+#include <linux/delay.h>
>+#include <linux/gpio/consumer.h>
>+#include <linux/module.h>
>+#include <linux/property.h>
>+#include <linux/spi/spi.h>
>+
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_fb_helper.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_mipi_dbi.h>
>+#include <drm/drm_modeset_helper.h>
>+#include <video/mipi_display.h>
>+
>+#define HX8357D_SETOSC 0xb0
>+#define HX8357D_SETPOWER 0xb1
>+#define HX8357D_SETRGB 0xb3
>+#define HX8357D_SETCYC 0xb3
>+#define HX8357D_SETCOM 0xb6
>+#define HX8357D_SETEXTC 0xb9
>+#define HX8357D_SETSTBA 0xc0
>+#define HX8357D_SETPANEL 0xcc
>+#define HX8357D_SETGAMMA 0xe0
>+
>+#define HX8357D_MADCTL_MY  0x80
>+#define HX8357D_MADCTL_MX  0x40
>+#define HX8357D_MADCTL_MV  0x20
>+#define HX8357D_MADCTL_ML  0x10
>+#define HX8357D_MADCTL_RGB 0x00
>+#define HX8357D_MADCTL_BGR 0x08
>+#define HX8357D_MADCTL_MH  0x04
>+
>+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
>+			     struct drm_crtc_state *crtc_state,
>+			     struct drm_plane_state *plane_state)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+	u8 addr_mode;
>+	int ret, idx;
>+
>+	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>+		return;
>+
>+	DRM_DEBUG_KMS("\n");
>+
>+	ret = mipi_dbi_poweron_conditional_reset(dbidev);
>+	if (ret < 0)
>+		goto out_exit;
>+	if (ret == 1)
>+		goto out_enable;
>+
>+	/* setextc */
>+	mipi_dbi_command(dbi, HX8357D_SETEXTC, 0xFF, 0x83, 0x57);
>+	msleep(150);
>+
>+	/* setRGB which also enables SDO */
>+	mipi_dbi_command(dbi, HX8357D_SETRGB, 0x00, 0x00, 0x06, 0x06);
>+
>+	/* -1.52V */
>+	mipi_dbi_command(dbi, HX8357D_SETCOM, 0x25);
>+
>+	/* Normal mode 70Hz, Idle mode 55 Hz */
>+	mipi_dbi_command(dbi, HX8357D_SETOSC, 0x68);
>+
>+	/* Set Panel - BGR, Gate direction swapped */
>+	mipi_dbi_command(dbi, HX8357D_SETPANEL, 0x05);
>+
>+	mipi_dbi_command(dbi, HX8357D_SETPOWER,
>+			 0x00,  /* Not deep standby */
>+			 0x15,  /* BT */
>+			 0x1C,  /* VSPR */
>+			 0x1C,  /* VSNR */
>+			 0x83,  /* AP */
>+			 0xAA);  /* FS */
>+
>+	mipi_dbi_command(dbi, HX8357D_SETSTBA,
>+			 0x50,  /* OPON normal */
>+			 0x50,  /* OPON idle */
>+			 0x01,  /* STBA */
>+			 0x3C,  /* STBA */
>+			 0x1E,  /* STBA */
>+			 0x08);  /* GEN */
>+
>+	mipi_dbi_command(dbi, HX8357D_SETCYC,
>+			 0x02,  /* NW 0x02 */
>+			 0x40,  /* RTN */
>+			 0x00,  /* DIV */
>+			 0x2A,  /* DUM */
>+			 0x2A,  /* DUM */
>+			 0x0D,  /* GDON */
>+			 0x78);  /* GDOFF */
>+
>+	mipi_dbi_command(dbi, HX8357D_SETGAMMA,
>+			 0x02,
>+			 0x0A,
>+			 0x11,
>+			 0x1d,
>+			 0x23,
>+			 0x35,
>+			 0x41,
>+			 0x4b,
>+			 0x4b,
>+			 0x42,
>+			 0x3A,
>+			 0x27,
>+			 0x1B,
>+			 0x08,
>+			 0x09,
>+			 0x03,
>+			 0x02,
>+			 0x0A,
>+			 0x11,
>+			 0x1d,
>+			 0x23,
>+			 0x35,
>+			 0x41,
>+			 0x4b,
>+			 0x4b,
>+			 0x42,
>+			 0x3A,
>+			 0x27,
>+			 0x1B,
>+			 0x08,
>+			 0x09,
>+			 0x03,
>+			 0x00,
>+			 0x01);
>+
>+	/* 16 bit */
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT,
>+			 MIPI_DCS_PIXEL_FMT_16BIT);
>+
>+	/* TE off */
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_TEAR_ON, 0x00);
>+
>+	/* tear line */
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_TEAR_SCANLINE, 0x00, 0x02);
>+
>+	/* Exit Sleep */
>+	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
>+	msleep(150);
>+
>+	/* display on */
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
>+	usleep_range(5000, 7000);
>+
>+out_enable:
>+	switch (dbidev->rotation) {
>+	default:
>+		addr_mode = HX8357D_MADCTL_MX | HX8357D_MADCTL_MY;
>+		break;
>+	case 90:
>+		addr_mode = HX8357D_MADCTL_MV | HX8357D_MADCTL_MY;
>+		break;
>+	case 180:
>+		addr_mode = 0;
>+		break;
>+	case 270:
>+		addr_mode = HX8357D_MADCTL_MV | HX8357D_MADCTL_MX;
>+		break;
>+	}
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
>+	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
>+out_exit:
>+	drm_dev_exit(idx);
>+}
>+
>+static const struct drm_simple_display_pipe_funcs hx8357d_pipe_funcs = {
>+	.enable = yx240qv29_enable,
>+	.disable = mipi_dbi_pipe_disable,
>+	.update = mipi_dbi_pipe_update,
>+	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
>+};
>+
>+static const struct drm_display_mode yx350hv15_mode = {
>+	DRM_SIMPLE_MODE(320, 480, 60, 75),
>+};
>+
>+DEFINE_DRM_GEM_CMA_FOPS(hx8357d_fops);
>+
>+static struct drm_driver hx8357d_driver = {
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
>+	.fops			= &hx8357d_fops,
>+	.release		= mipi_dbi_release,
>+	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>+	.debugfs_init		= mipi_dbi_debugfs_init,
>+	.name			= "hx8357d",
>+	.desc			= "HX8357D",
>+	.date			= "20181023",
>+	.major			= 1,
>+	.minor			= 0,
>+};
>+
>+static const struct of_device_id hx8357d_of_match[] = {
>+	{ .compatible = "adafruit,yx350hv15" },
>+	{ }
>+};
>+MODULE_DEVICE_TABLE(of, hx8357d_of_match);
>+
>+static const struct spi_device_id hx8357d_id[] = {
>+	{ "yx350hv15", 0 },
>+	{ }
>+};
>+MODULE_DEVICE_TABLE(spi, hx8357d_id);
>+
>+static int hx8357d_probe(struct spi_device *spi)
>+{
>+	struct device *dev = &spi->dev;
>+	struct mipi_dbi_dev *dbidev;
>+	struct drm_device *drm;
>+	struct gpio_desc *dc;
>+	u32 rotation = 0;
>+	int ret;
>+
>+	dbidev = kzalloc(sizeof(*dbidev), GFP_KERNEL);
>+	if (!dbidev)
>+		return -ENOMEM;
>+
>+	drm = &dbidev->drm;
>+	ret = devm_drm_dev_init(dev, drm, &hx8357d_driver);
>+	if (ret) {
>+		kfree(dbidev);
>+		return ret;
>+	}
>+
>+	drm_mode_config_init(drm);
>+
>+	dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
>+	if (IS_ERR(dc)) {
>+		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
>+		return PTR_ERR(dc);
>+	}
>+
>+	dbidev->backlight = devm_of_find_backlight(dev);
>+	if (IS_ERR(dbidev->backlight))
>+		return PTR_ERR(dbidev->backlight);
>+
>+	device_property_read_u32(dev, "rotation", &rotation);
>+
>+	ret = mipi_dbi_spi_init(spi, &dbidev->dbi, dc);
>+	if (ret)
>+		return ret;
>+
>+	ret = mipi_dbi_dev_init(dbidev, &hx8357d_pipe_funcs, &yx350hv15_mode, rotation);
>+	if (ret)
>+		return ret;
>+
>+	drm_mode_config_reset(drm);
>+
>+	ret = drm_dev_register(drm, 0);
>+	if (ret)
>+		return ret;
>+
>+	spi_set_drvdata(spi, drm);
>+
>+	drm_fbdev_generic_setup(drm, 0);
>+
>+	return 0;
>+}
>+
>+static int hx8357d_remove(struct spi_device *spi)
>+{
>+	struct drm_device *drm = spi_get_drvdata(spi);
>+
>+	drm_dev_unplug(drm);
>+	drm_atomic_helper_shutdown(drm);
>+
>+	return 0;
>+}
>+
>+static void hx8357d_shutdown(struct spi_device *spi)
>+{
>+	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>+}
>+
>+static struct spi_driver hx8357d_spi_driver = {
>+	.driver = {
>+		.name = "hx8357d",
>+		.of_match_table = hx8357d_of_match,
>+	},
>+	.id_table = hx8357d_id,
>+	.probe = hx8357d_probe,
>+	.remove = hx8357d_remove,
>+	.shutdown = hx8357d_shutdown,
>+};
>+module_spi_driver(hx8357d_spi_driver);
>+
>+MODULE_DESCRIPTION("HX8357D DRM driver");
>+MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
>+MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tiny/ili9225.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/ili9225.c
>--- linux-5.3-rc6/drivers/gpu/drm/tiny/ili9225.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/ili9225.c	2019-08-31 15:01:12.233736201 -0500
>@@ -0,0 +1,470 @@
>+// SPDX-License-Identifier: GPL-2.0-or-later
>+/*
>+ * DRM driver for Ilitek ILI9225 panels
>+ *
>+ * Copyright 2017 David Lechner <david@lechnology.com>
>+ *
>+ * Some code copied from mipi-dbi.c
>+ * Copyright 2016 Noralf TrÃ¸nnes
>+ */
>+
>+#include <linux/delay.h>
>+#include <linux/dma-buf.h>
>+#include <linux/gpio/consumer.h>
>+#include <linux/module.h>
>+#include <linux/property.h>
>+#include <linux/spi/spi.h>
>+#include <video/mipi_display.h>
>+
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_damage_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fb_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_mipi_dbi.h>
>+#include <drm/drm_rect.h>
>+#include <drm/drm_vblank.h>
>+
>+#define ILI9225_DRIVER_READ_CODE	0x00
>+#define ILI9225_DRIVER_OUTPUT_CONTROL	0x01
>+#define ILI9225_LCD_AC_DRIVING_CONTROL	0x02
>+#define ILI9225_ENTRY_MODE		0x03
>+#define ILI9225_DISPLAY_CONTROL_1	0x07
>+#define ILI9225_BLANK_PERIOD_CONTROL_1	0x08
>+#define ILI9225_FRAME_CYCLE_CONTROL	0x0b
>+#define ILI9225_INTERFACE_CONTROL	0x0c
>+#define ILI9225_OSCILLATION_CONTROL	0x0f
>+#define ILI9225_POWER_CONTROL_1		0x10
>+#define ILI9225_POWER_CONTROL_2		0x11
>+#define ILI9225_POWER_CONTROL_3		0x12
>+#define ILI9225_POWER_CONTROL_4		0x13
>+#define ILI9225_POWER_CONTROL_5		0x14
>+#define ILI9225_VCI_RECYCLING		0x15
>+#define ILI9225_RAM_ADDRESS_SET_1	0x20
>+#define ILI9225_RAM_ADDRESS_SET_2	0x21
>+#define ILI9225_WRITE_DATA_TO_GRAM	0x22
>+#define ILI9225_SOFTWARE_RESET		0x28
>+#define ILI9225_GATE_SCAN_CONTROL	0x30
>+#define ILI9225_VERTICAL_SCROLL_1	0x31
>+#define ILI9225_VERTICAL_SCROLL_2	0x32
>+#define ILI9225_VERTICAL_SCROLL_3	0x33
>+#define ILI9225_PARTIAL_DRIVING_POS_1	0x34
>+#define ILI9225_PARTIAL_DRIVING_POS_2	0x35
>+#define ILI9225_HORIZ_WINDOW_ADDR_1	0x36
>+#define ILI9225_HORIZ_WINDOW_ADDR_2	0x37
>+#define ILI9225_VERT_WINDOW_ADDR_1	0x38
>+#define ILI9225_VERT_WINDOW_ADDR_2	0x39
>+#define ILI9225_GAMMA_CONTROL_1		0x50
>+#define ILI9225_GAMMA_CONTROL_2		0x51
>+#define ILI9225_GAMMA_CONTROL_3		0x52
>+#define ILI9225_GAMMA_CONTROL_4		0x53
>+#define ILI9225_GAMMA_CONTROL_5		0x54
>+#define ILI9225_GAMMA_CONTROL_6		0x55
>+#define ILI9225_GAMMA_CONTROL_7		0x56
>+#define ILI9225_GAMMA_CONTROL_8		0x57
>+#define ILI9225_GAMMA_CONTROL_9		0x58
>+#define ILI9225_GAMMA_CONTROL_10	0x59
>+
>+static inline int ili9225_command(struct mipi_dbi *dbi, u8 cmd, u16 data)
>+{
>+	u8 par[2] = { data >> 8, data & 0xff };
>+
>+	return mipi_dbi_command_buf(dbi, cmd, par, 2);
>+}
>+
>+static void ili9225_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
>+{
>+	struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
>+	unsigned int height = rect->y2 - rect->y1;
>+	unsigned int width = rect->x2 - rect->x1;
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+	bool swap = dbi->swap_bytes;
>+	u16 x_start, y_start;
>+	u16 x1, x2, y1, y2;
>+	int idx, ret = 0;
>+	bool full;
>+	void *tr;
>+
>+	if (!dbidev->enabled)
>+		return;
>+
>+	if (!drm_dev_enter(fb->dev, &idx))
>+		return;
>+
>+	full = width == fb->width && height == fb->height;
>+
>+	DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
>+
>+	if (!dbi->dc || !full || swap ||
>+	    fb->format->format == DRM_FORMAT_XRGB8888) {
>+		tr = dbidev->tx_buf;
>+		ret = mipi_dbi_buf_copy(dbidev->tx_buf, fb, rect, swap);
>+		if (ret)
>+			goto err_msg;
>+	} else {
>+		tr = cma_obj->vaddr;
>+	}
>+
>+	switch (dbidev->rotation) {
>+	default:
>+		x1 = rect->x1;
>+		x2 = rect->x2 - 1;
>+		y1 = rect->y1;
>+		y2 = rect->y2 - 1;
>+		x_start = x1;
>+		y_start = y1;
>+		break;
>+	case 90:
>+		x1 = rect->y1;
>+		x2 = rect->y2 - 1;
>+		y1 = fb->width - rect->x2;
>+		y2 = fb->width - rect->x1 - 1;
>+		x_start = x1;
>+		y_start = y2;
>+		break;
>+	case 180:
>+		x1 = fb->width - rect->x2;
>+		x2 = fb->width - rect->x1 - 1;
>+		y1 = fb->height - rect->y2;
>+		y2 = fb->height - rect->y1 - 1;
>+		x_start = x2;
>+		y_start = y2;
>+		break;
>+	case 270:
>+		x1 = fb->height - rect->y2;
>+		x2 = fb->height - rect->y1 - 1;
>+		y1 = rect->x1;
>+		y2 = rect->x2 - 1;
>+		x_start = x2;
>+		y_start = y1;
>+		break;
>+	}
>+
>+	ili9225_command(dbi, ILI9225_HORIZ_WINDOW_ADDR_1, x2);
>+	ili9225_command(dbi, ILI9225_HORIZ_WINDOW_ADDR_2, x1);
>+	ili9225_command(dbi, ILI9225_VERT_WINDOW_ADDR_1, y2);
>+	ili9225_command(dbi, ILI9225_VERT_WINDOW_ADDR_2, y1);
>+
>+	ili9225_command(dbi, ILI9225_RAM_ADDRESS_SET_1, x_start);
>+	ili9225_command(dbi, ILI9225_RAM_ADDRESS_SET_2, y_start);
>+
>+	ret = mipi_dbi_command_buf(dbi, ILI9225_WRITE_DATA_TO_GRAM, tr,
>+				   width * height * 2);
>+err_msg:
>+	if (ret)
>+		dev_err_once(fb->dev->dev, "Failed to update display %d\n", ret);
>+
>+	drm_dev_exit(idx);
>+}
>+
>+static void ili9225_pipe_update(struct drm_simple_display_pipe *pipe,
>+				struct drm_plane_state *old_state)
>+{
>+	struct drm_plane_state *state = pipe->plane.state;
>+	struct drm_crtc *crtc = &pipe->crtc;
>+	struct drm_rect rect;
>+
>+	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
>+		ili9225_fb_dirty(state->fb, &rect);
>+
>+	if (crtc->state->event) {
>+		spin_lock_irq(&crtc->dev->event_lock);
>+		drm_crtc_send_vblank_event(crtc, crtc->state->event);
>+		spin_unlock_irq(&crtc->dev->event_lock);
>+		crtc->state->event = NULL;
>+	}
>+}
>+
>+static void ili9225_pipe_enable(struct drm_simple_display_pipe *pipe,
>+				struct drm_crtc_state *crtc_state,
>+				struct drm_plane_state *plane_state)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
>+	struct drm_framebuffer *fb = plane_state->fb;
>+	struct device *dev = pipe->crtc.dev->dev;
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+	struct drm_rect rect = {
>+		.x1 = 0,
>+		.x2 = fb->width,
>+		.y1 = 0,
>+		.y2 = fb->height,
>+	};
>+	int ret, idx;
>+	u8 am_id;
>+
>+	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>+		return;
>+
>+	DRM_DEBUG_KMS("\n");
>+
>+	mipi_dbi_hw_reset(dbi);
>+
>+	/*
>+	 * There don't seem to be two example init sequences that match, so
>+	 * using the one from the popular Arduino library for this display.
>+	 * https://github.com/Nkawu/TFT_22_ILI9225/blob/master/src/TFT_22_ILI9225.cpp
>+	 */
>+
>+	ret = ili9225_command(dbi, ILI9225_POWER_CONTROL_1, 0x0000);
>+	if (ret) {
>+		DRM_DEV_ERROR(dev, "Error sending command %d\n", ret);
>+		goto out_exit;
>+	}
>+	ili9225_command(dbi, ILI9225_POWER_CONTROL_2, 0x0000);
>+	ili9225_command(dbi, ILI9225_POWER_CONTROL_3, 0x0000);
>+	ili9225_command(dbi, ILI9225_POWER_CONTROL_4, 0x0000);
>+	ili9225_command(dbi, ILI9225_POWER_CONTROL_5, 0x0000);
>+
>+	msleep(40);
>+
>+	ili9225_command(dbi, ILI9225_POWER_CONTROL_2, 0x0018);
>+	ili9225_command(dbi, ILI9225_POWER_CONTROL_3, 0x6121);
>+	ili9225_command(dbi, ILI9225_POWER_CONTROL_4, 0x006f);
>+	ili9225_command(dbi, ILI9225_POWER_CONTROL_5, 0x495f);
>+	ili9225_command(dbi, ILI9225_POWER_CONTROL_1, 0x0800);
>+
>+	msleep(10);
>+
>+	ili9225_command(dbi, ILI9225_POWER_CONTROL_2, 0x103b);
>+
>+	msleep(50);
>+
>+	switch (dbidev->rotation) {
>+	default:
>+		am_id = 0x30;
>+		break;
>+	case 90:
>+		am_id = 0x18;
>+		break;
>+	case 180:
>+		am_id = 0x00;
>+		break;
>+	case 270:
>+		am_id = 0x28;
>+		break;
>+	}
>+	ili9225_command(dbi, ILI9225_DRIVER_OUTPUT_CONTROL, 0x011c);
>+	ili9225_command(dbi, ILI9225_LCD_AC_DRIVING_CONTROL, 0x0100);
>+	ili9225_command(dbi, ILI9225_ENTRY_MODE, 0x1000 | am_id);
>+	ili9225_command(dbi, ILI9225_DISPLAY_CONTROL_1, 0x0000);
>+	ili9225_command(dbi, ILI9225_BLANK_PERIOD_CONTROL_1, 0x0808);
>+	ili9225_command(dbi, ILI9225_FRAME_CYCLE_CONTROL, 0x1100);
>+	ili9225_command(dbi, ILI9225_INTERFACE_CONTROL, 0x0000);
>+	ili9225_command(dbi, ILI9225_OSCILLATION_CONTROL, 0x0d01);
>+	ili9225_command(dbi, ILI9225_VCI_RECYCLING, 0x0020);
>+	ili9225_command(dbi, ILI9225_RAM_ADDRESS_SET_1, 0x0000);
>+	ili9225_command(dbi, ILI9225_RAM_ADDRESS_SET_2, 0x0000);
>+
>+	ili9225_command(dbi, ILI9225_GATE_SCAN_CONTROL, 0x0000);
>+	ili9225_command(dbi, ILI9225_VERTICAL_SCROLL_1, 0x00db);
>+	ili9225_command(dbi, ILI9225_VERTICAL_SCROLL_2, 0x0000);
>+	ili9225_command(dbi, ILI9225_VERTICAL_SCROLL_3, 0x0000);
>+	ili9225_command(dbi, ILI9225_PARTIAL_DRIVING_POS_1, 0x00db);
>+	ili9225_command(dbi, ILI9225_PARTIAL_DRIVING_POS_2, 0x0000);
>+
>+	ili9225_command(dbi, ILI9225_GAMMA_CONTROL_1, 0x0000);
>+	ili9225_command(dbi, ILI9225_GAMMA_CONTROL_2, 0x0808);
>+	ili9225_command(dbi, ILI9225_GAMMA_CONTROL_3, 0x080a);
>+	ili9225_command(dbi, ILI9225_GAMMA_CONTROL_4, 0x000a);
>+	ili9225_command(dbi, ILI9225_GAMMA_CONTROL_5, 0x0a08);
>+	ili9225_command(dbi, ILI9225_GAMMA_CONTROL_6, 0x0808);
>+	ili9225_command(dbi, ILI9225_GAMMA_CONTROL_7, 0x0000);
>+	ili9225_command(dbi, ILI9225_GAMMA_CONTROL_8, 0x0a00);
>+	ili9225_command(dbi, ILI9225_GAMMA_CONTROL_9, 0x0710);
>+	ili9225_command(dbi, ILI9225_GAMMA_CONTROL_10, 0x0710);
>+
>+	ili9225_command(dbi, ILI9225_DISPLAY_CONTROL_1, 0x0012);
>+
>+	msleep(50);
>+
>+	ili9225_command(dbi, ILI9225_DISPLAY_CONTROL_1, 0x1017);
>+
>+	dbidev->enabled = true;
>+	ili9225_fb_dirty(fb, &rect);
>+out_exit:
>+	drm_dev_exit(idx);
>+}
>+
>+static void ili9225_pipe_disable(struct drm_simple_display_pipe *pipe)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+
>+	DRM_DEBUG_KMS("\n");
>+
>+	/*
>+	 * This callback is not protected by drm_dev_enter/exit since we want to
>+	 * turn off the display on regular driver unload. It's highly unlikely
>+	 * that the underlying SPI controller is gone should this be called after
>+	 * unplug.
>+	 */
>+
>+	if (!dbidev->enabled)
>+		return;
>+
>+	ili9225_command(dbi, ILI9225_DISPLAY_CONTROL_1, 0x0000);
>+	msleep(50);
>+	ili9225_command(dbi, ILI9225_POWER_CONTROL_2, 0x0007);
>+	msleep(50);
>+	ili9225_command(dbi, ILI9225_POWER_CONTROL_1, 0x0a02);
>+
>+	dbidev->enabled = false;
>+}
>+
>+static int ili9225_dbi_command(struct mipi_dbi *dbi, u8 *cmd, u8 *par,
>+			       size_t num)
>+{
>+	struct spi_device *spi = dbi->spi;
>+	unsigned int bpw = 8;
>+	u32 speed_hz;
>+	int ret;
>+
>+	gpiod_set_value_cansleep(dbi->dc, 0);
>+	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
>+	ret = mipi_dbi_spi_transfer(spi, speed_hz, 8, cmd, 1);
>+	if (ret || !num)
>+		return ret;
>+
>+	if (*cmd == ILI9225_WRITE_DATA_TO_GRAM && !dbi->swap_bytes)
>+		bpw = 16;
>+
>+	gpiod_set_value_cansleep(dbi->dc, 1);
>+	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
>+
>+	return mipi_dbi_spi_transfer(spi, speed_hz, bpw, par, num);
>+}
>+
>+static const struct drm_simple_display_pipe_funcs ili9225_pipe_funcs = {
>+	.enable		= ili9225_pipe_enable,
>+	.disable	= ili9225_pipe_disable,
>+	.update		= ili9225_pipe_update,
>+	.prepare_fb	= drm_gem_fb_simple_display_pipe_prepare_fb,
>+};
>+
>+static const struct drm_display_mode ili9225_mode = {
>+	DRM_SIMPLE_MODE(176, 220, 35, 44),
>+};
>+
>+DEFINE_DRM_GEM_CMA_FOPS(ili9225_fops);
>+
>+static struct drm_driver ili9225_driver = {
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
>+	.fops			= &ili9225_fops,
>+	.release		= mipi_dbi_release,
>+	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>+	.name			= "ili9225",
>+	.desc			= "Ilitek ILI9225",
>+	.date			= "20171106",
>+	.major			= 1,
>+	.minor			= 0,
>+};
>+
>+static const struct of_device_id ili9225_of_match[] = {
>+	{ .compatible = "vot,v220hf01a-t" },
>+	{},
>+};
>+MODULE_DEVICE_TABLE(of, ili9225_of_match);
>+
>+static const struct spi_device_id ili9225_id[] = {
>+	{ "v220hf01a-t", 0 },
>+	{ },
>+};
>+MODULE_DEVICE_TABLE(spi, ili9225_id);
>+
>+static int ili9225_probe(struct spi_device *spi)
>+{
>+	struct device *dev = &spi->dev;
>+	struct mipi_dbi_dev *dbidev;
>+	struct drm_device *drm;
>+	struct mipi_dbi *dbi;
>+	struct gpio_desc *rs;
>+	u32 rotation = 0;
>+	int ret;
>+
>+	dbidev = kzalloc(sizeof(*dbidev), GFP_KERNEL);
>+	if (!dbidev)
>+		return -ENOMEM;
>+
>+	dbi = &dbidev->dbi;
>+	drm = &dbidev->drm;
>+	ret = devm_drm_dev_init(dev, drm, &ili9225_driver);
>+	if (ret) {
>+		kfree(dbidev);
>+		return ret;
>+	}
>+
>+	drm_mode_config_init(drm);
>+
>+	dbi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
>+	if (IS_ERR(dbi->reset)) {
>+		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
>+		return PTR_ERR(dbi->reset);
>+	}
>+
>+	rs = devm_gpiod_get(dev, "rs", GPIOD_OUT_LOW);
>+	if (IS_ERR(rs)) {
>+		DRM_DEV_ERROR(dev, "Failed to get gpio 'rs'\n");
>+		return PTR_ERR(rs);
>+	}
>+
>+	device_property_read_u32(dev, "rotation", &rotation);
>+
>+	ret = mipi_dbi_spi_init(spi, dbi, rs);
>+	if (ret)
>+		return ret;
>+
>+	/* override the command function set in  mipi_dbi_spi_init() */
>+	dbi->command = ili9225_dbi_command;
>+
>+	ret = mipi_dbi_dev_init(dbidev, &ili9225_pipe_funcs, &ili9225_mode, rotation);
>+	if (ret)
>+		return ret;
>+
>+	drm_mode_config_reset(drm);
>+
>+	ret = drm_dev_register(drm, 0);
>+	if (ret)
>+		return ret;
>+
>+	spi_set_drvdata(spi, drm);
>+
>+	drm_fbdev_generic_setup(drm, 0);
>+
>+	return 0;
>+}
>+
>+static int ili9225_remove(struct spi_device *spi)
>+{
>+	struct drm_device *drm = spi_get_drvdata(spi);
>+
>+	drm_dev_unplug(drm);
>+	drm_atomic_helper_shutdown(drm);
>+
>+	return 0;
>+}
>+
>+static void ili9225_shutdown(struct spi_device *spi)
>+{
>+	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>+}
>+
>+static struct spi_driver ili9225_spi_driver = {
>+	.driver = {
>+		.name = "ili9225",
>+		.owner = THIS_MODULE,
>+		.of_match_table = ili9225_of_match,
>+	},
>+	.id_table = ili9225_id,
>+	.probe = ili9225_probe,
>+	.remove = ili9225_remove,
>+	.shutdown = ili9225_shutdown,
>+};
>+module_spi_driver(ili9225_spi_driver);
>+
>+MODULE_DESCRIPTION("Ilitek ILI9225 DRM driver");
>+MODULE_AUTHOR("David Lechner <david@lechnology.com>");
>+MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tiny/ili9341.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/ili9341.c
>--- linux-5.3-rc6/drivers/gpu/drm/tiny/ili9341.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/ili9341.c	2019-08-31 15:01:12.233736201 -0500
>@@ -0,0 +1,268 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * DRM driver for Ilitek ILI9341 panels
>+ *
>+ * Copyright 2018 David Lechner <david@lechnology.com>
>+ *
>+ * Based on mi0283qt.c:
>+ * Copyright 2016 Noralf TrÃ¸nnes
>+ */
>+
>+#include <linux/backlight.h>
>+#include <linux/delay.h>
>+#include <linux/gpio/consumer.h>
>+#include <linux/module.h>
>+#include <linux/property.h>
>+#include <linux/spi/spi.h>
>+
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_fb_helper.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_mipi_dbi.h>
>+#include <drm/drm_modeset_helper.h>
>+#include <video/mipi_display.h>
>+
>+#define ILI9341_FRMCTR1		0xb1
>+#define ILI9341_DISCTRL		0xb6
>+#define ILI9341_ETMOD		0xb7
>+
>+#define ILI9341_PWCTRL1		0xc0
>+#define ILI9341_PWCTRL2		0xc1
>+#define ILI9341_VMCTRL1		0xc5
>+#define ILI9341_VMCTRL2		0xc7
>+#define ILI9341_PWCTRLA		0xcb
>+#define ILI9341_PWCTRLB		0xcf
>+
>+#define ILI9341_PGAMCTRL	0xe0
>+#define ILI9341_NGAMCTRL	0xe1
>+#define ILI9341_DTCTRLA		0xe8
>+#define ILI9341_DTCTRLB		0xea
>+#define ILI9341_PWRSEQ		0xed
>+
>+#define ILI9341_EN3GAM		0xf2
>+#define ILI9341_PUMPCTRL	0xf7
>+
>+#define ILI9341_MADCTL_BGR	BIT(3)
>+#define ILI9341_MADCTL_MV	BIT(5)
>+#define ILI9341_MADCTL_MX	BIT(6)
>+#define ILI9341_MADCTL_MY	BIT(7)
>+
>+static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
>+			     struct drm_crtc_state *crtc_state,
>+			     struct drm_plane_state *plane_state)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+	u8 addr_mode;
>+	int ret, idx;
>+
>+	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>+		return;
>+
>+	DRM_DEBUG_KMS("\n");
>+
>+	ret = mipi_dbi_poweron_conditional_reset(dbidev);
>+	if (ret < 0)
>+		goto out_exit;
>+	if (ret == 1)
>+		goto out_enable;
>+
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF);
>+
>+	mipi_dbi_command(dbi, ILI9341_PWCTRLB, 0x00, 0xc1, 0x30);
>+	mipi_dbi_command(dbi, ILI9341_PWRSEQ, 0x64, 0x03, 0x12, 0x81);
>+	mipi_dbi_command(dbi, ILI9341_DTCTRLA, 0x85, 0x00, 0x78);
>+	mipi_dbi_command(dbi, ILI9341_PWCTRLA, 0x39, 0x2c, 0x00, 0x34, 0x02);
>+	mipi_dbi_command(dbi, ILI9341_PUMPCTRL, 0x20);
>+	mipi_dbi_command(dbi, ILI9341_DTCTRLB, 0x00, 0x00);
>+
>+	/* Power Control */
>+	mipi_dbi_command(dbi, ILI9341_PWCTRL1, 0x23);
>+	mipi_dbi_command(dbi, ILI9341_PWCTRL2, 0x10);
>+	/* VCOM */
>+	mipi_dbi_command(dbi, ILI9341_VMCTRL1, 0x3e, 0x28);
>+	mipi_dbi_command(dbi, ILI9341_VMCTRL2, 0x86);
>+
>+	/* Memory Access Control */
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
>+
>+	/* Frame Rate */
>+	mipi_dbi_command(dbi, ILI9341_FRMCTR1, 0x00, 0x1b);
>+
>+	/* Gamma */
>+	mipi_dbi_command(dbi, ILI9341_EN3GAM, 0x00);
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x01);
>+	mipi_dbi_command(dbi, ILI9341_PGAMCTRL,
>+			 0x0f, 0x31, 0x2b, 0x0c, 0x0e, 0x08, 0x4e, 0xf1,
>+			 0x37, 0x07, 0x10, 0x03, 0x0e, 0x09, 0x00);
>+	mipi_dbi_command(dbi, ILI9341_NGAMCTRL,
>+			 0x00, 0x0e, 0x14, 0x03, 0x11, 0x07, 0x31, 0xc1,
>+			 0x48, 0x08, 0x0f, 0x0c, 0x31, 0x36, 0x0f);
>+
>+	/* DDRAM */
>+	mipi_dbi_command(dbi, ILI9341_ETMOD, 0x07);
>+
>+	/* Display */
>+	mipi_dbi_command(dbi, ILI9341_DISCTRL, 0x08, 0x82, 0x27, 0x00);
>+	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
>+	msleep(100);
>+
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
>+	msleep(100);
>+
>+out_enable:
>+	switch (dbidev->rotation) {
>+	default:
>+		addr_mode = ILI9341_MADCTL_MX;
>+		break;
>+	case 90:
>+		addr_mode = ILI9341_MADCTL_MV;
>+		break;
>+	case 180:
>+		addr_mode = ILI9341_MADCTL_MY;
>+		break;
>+	case 270:
>+		addr_mode = ILI9341_MADCTL_MV | ILI9341_MADCTL_MY |
>+			    ILI9341_MADCTL_MX;
>+		break;
>+	}
>+	addr_mode |= ILI9341_MADCTL_BGR;
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
>+	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
>+out_exit:
>+	drm_dev_exit(idx);
>+}
>+
>+static const struct drm_simple_display_pipe_funcs ili9341_pipe_funcs = {
>+	.enable = yx240qv29_enable,
>+	.disable = mipi_dbi_pipe_disable,
>+	.update = mipi_dbi_pipe_update,
>+	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
>+};
>+
>+static const struct drm_display_mode yx240qv29_mode = {
>+	DRM_SIMPLE_MODE(240, 320, 37, 49),
>+};
>+
>+DEFINE_DRM_GEM_CMA_FOPS(ili9341_fops);
>+
>+static struct drm_driver ili9341_driver = {
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
>+	.fops			= &ili9341_fops,
>+	.release		= mipi_dbi_release,
>+	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>+	.debugfs_init		= mipi_dbi_debugfs_init,
>+	.name			= "ili9341",
>+	.desc			= "Ilitek ILI9341",
>+	.date			= "20180514",
>+	.major			= 1,
>+	.minor			= 0,
>+};
>+
>+static const struct of_device_id ili9341_of_match[] = {
>+	{ .compatible = "adafruit,yx240qv29" },
>+	{ }
>+};
>+MODULE_DEVICE_TABLE(of, ili9341_of_match);
>+
>+static const struct spi_device_id ili9341_id[] = {
>+	{ "yx240qv29", 0 },
>+	{ }
>+};
>+MODULE_DEVICE_TABLE(spi, ili9341_id);
>+
>+static int ili9341_probe(struct spi_device *spi)
>+{
>+	struct device *dev = &spi->dev;
>+	struct mipi_dbi_dev *dbidev;
>+	struct drm_device *drm;
>+	struct mipi_dbi *dbi;
>+	struct gpio_desc *dc;
>+	u32 rotation = 0;
>+	int ret;
>+
>+	dbidev = kzalloc(sizeof(*dbidev), GFP_KERNEL);
>+	if (!dbidev)
>+		return -ENOMEM;
>+
>+	dbi = &dbidev->dbi;
>+	drm = &dbidev->drm;
>+	ret = devm_drm_dev_init(dev, drm, &ili9341_driver);
>+	if (ret) {
>+		kfree(dbidev);
>+		return ret;
>+	}
>+
>+	drm_mode_config_init(drm);
>+
>+	dbi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
>+	if (IS_ERR(dbi->reset)) {
>+		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
>+		return PTR_ERR(dbi->reset);
>+	}
>+
>+	dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
>+	if (IS_ERR(dc)) {
>+		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
>+		return PTR_ERR(dc);
>+	}
>+
>+	dbidev->backlight = devm_of_find_backlight(dev);
>+	if (IS_ERR(dbidev->backlight))
>+		return PTR_ERR(dbidev->backlight);
>+
>+	device_property_read_u32(dev, "rotation", &rotation);
>+
>+	ret = mipi_dbi_spi_init(spi, dbi, dc);
>+	if (ret)
>+		return ret;
>+
>+	ret = mipi_dbi_dev_init(dbidev, &ili9341_pipe_funcs, &yx240qv29_mode, rotation);
>+	if (ret)
>+		return ret;
>+
>+	drm_mode_config_reset(drm);
>+
>+	ret = drm_dev_register(drm, 0);
>+	if (ret)
>+		return ret;
>+
>+	spi_set_drvdata(spi, drm);
>+
>+	drm_fbdev_generic_setup(drm, 0);
>+
>+	return 0;
>+}
>+
>+static int ili9341_remove(struct spi_device *spi)
>+{
>+	struct drm_device *drm = spi_get_drvdata(spi);
>+
>+	drm_dev_unplug(drm);
>+	drm_atomic_helper_shutdown(drm);
>+
>+	return 0;
>+}
>+
>+static void ili9341_shutdown(struct spi_device *spi)
>+{
>+	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>+}
>+
>+static struct spi_driver ili9341_spi_driver = {
>+	.driver = {
>+		.name = "ili9341",
>+		.of_match_table = ili9341_of_match,
>+	},
>+	.id_table = ili9341_id,
>+	.probe = ili9341_probe,
>+	.remove = ili9341_remove,
>+	.shutdown = ili9341_shutdown,
>+};
>+module_spi_driver(ili9341_spi_driver);
>+
>+MODULE_DESCRIPTION("Ilitek ILI9341 DRM driver");
>+MODULE_AUTHOR("David Lechner <david@lechnology.com>");
>+MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tiny/Kconfig linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/Kconfig
>--- linux-5.3-rc6/drivers/gpu/drm/tiny/Kconfig	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/Kconfig	2019-08-31 15:01:12.233736201 -0500
>@@ -0,0 +1,99 @@
>+# SPDX-License-Identifier: GPL-2.0-only
>+
>+config DRM_GM12U320
>+	tristate "GM12U320 driver for USB projectors"
>+	depends on DRM && USB
>+	select DRM_KMS_HELPER
>+	select DRM_GEM_SHMEM_HELPER
>+	help
>+	 This is a KMS driver for projectors which use the GM12U320 chipset
>+	 for video transfer over USB2/3, such as the Acer C120 mini projector.
>+
>+config TINYDRM_HX8357D
>+	tristate "DRM support for HX8357D display panels"
>+	depends on DRM && SPI
>+	select DRM_KMS_HELPER
>+	select DRM_KMS_CMA_HELPER
>+	select DRM_MIPI_DBI
>+	select BACKLIGHT_CLASS_DEVICE
>+	help
>+	  DRM driver for the following HX8357D panels:
>+	  * YX350HV15-T 3.5" 340x350 TFT (Adafruit 3.5")
>+
>+	  If M is selected the module will be called hx8357d.
>+
>+config TINYDRM_ILI9225
>+	tristate "DRM support for ILI9225 display panels"
>+	depends on DRM && SPI
>+	select DRM_KMS_HELPER
>+	select DRM_KMS_CMA_HELPER
>+	select DRM_MIPI_DBI
>+	help
>+	  DRM driver for the following Ilitek ILI9225 panels:
>+	  * No-name 2.2" color screen module
>+
>+	  If M is selected the module will be called ili9225.
>+
>+config TINYDRM_ILI9341
>+	tristate "DRM support for ILI9341 display panels"
>+	depends on DRM && SPI
>+	select DRM_KMS_HELPER
>+	select DRM_KMS_CMA_HELPER
>+	select DRM_MIPI_DBI
>+	select BACKLIGHT_CLASS_DEVICE
>+	help
>+	  DRM driver for the following Ilitek ILI9341 panels:
>+	  * YX240QV29-T 2.4" 240x320 TFT (Adafruit 2.4")
>+
>+	  If M is selected the module will be called ili9341.
>+
>+config TINYDRM_MI0283QT
>+	tristate "DRM support for MI0283QT"
>+	depends on DRM && SPI
>+	select DRM_KMS_HELPER
>+	select DRM_KMS_CMA_HELPER
>+	select DRM_MIPI_DBI
>+	select BACKLIGHT_CLASS_DEVICE
>+	help
>+	  DRM driver for the Multi-Inno MI0283QT display panel
>+	  If M is selected the module will be called mi0283qt.
>+
>+config TINYDRM_REPAPER
>+	tristate "DRM support for Pervasive Displays RePaper panels (V231)"
>+	depends on DRM && SPI
>+	select DRM_KMS_HELPER
>+	select DRM_KMS_CMA_HELPER
>+	depends on THERMAL || !THERMAL
>+	help
>+	  DRM driver for the following Pervasive Displays panels:
>+	  1.44" TFT EPD Panel (E1144CS021)
>+	  1.90" TFT EPD Panel (E1190CS021)
>+	  2.00" TFT EPD Panel (E2200CS021)
>+	  2.71" TFT EPD Panel (E2271CS021)
>+
>+	  If M is selected the module will be called repaper.
>+
>+config TINYDRM_ST7586
>+	tristate "DRM support for Sitronix ST7586 display panels"
>+	depends on DRM && SPI
>+	select DRM_KMS_HELPER
>+	select DRM_KMS_CMA_HELPER
>+	select DRM_MIPI_DBI
>+	help
>+	  DRM driver for the following Sitronix ST7586 panels:
>+	  * LEGO MINDSTORMS EV3
>+
>+	  If M is selected the module will be called st7586.
>+
>+config TINYDRM_ST7735R
>+	tristate "DRM support for Sitronix ST7735R display panels"
>+	depends on DRM && SPI
>+	select DRM_KMS_HELPER
>+	select DRM_KMS_CMA_HELPER
>+	select DRM_MIPI_DBI
>+	select BACKLIGHT_CLASS_DEVICE
>+	help
>+	  DRM driver Sitronix ST7735R with one of the following LCDs:
>+	  * JD-T18003-T01 1.8" 128x160 TFT
>+
>+	  If M is selected the module will be called st7735r.
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tiny/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/tiny/Makefile	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/Makefile	2019-08-31 15:01:12.233736201 -0500
>@@ -0,0 +1,10 @@
>+# SPDX-License-Identifier: GPL-2.0-only
>+
>+obj-$(CONFIG_DRM_GM12U320)		+= gm12u320.o
>+obj-$(CONFIG_TINYDRM_HX8357D)		+= hx8357d.o
>+obj-$(CONFIG_TINYDRM_ILI9225)		+= ili9225.o
>+obj-$(CONFIG_TINYDRM_ILI9341)		+= ili9341.o
>+obj-$(CONFIG_TINYDRM_MI0283QT)		+= mi0283qt.o
>+obj-$(CONFIG_TINYDRM_REPAPER)		+= repaper.o
>+obj-$(CONFIG_TINYDRM_ST7586)		+= st7586.o
>+obj-$(CONFIG_TINYDRM_ST7735R)		+= st7735r.o
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tiny/mi0283qt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/mi0283qt.c
>--- linux-5.3-rc6/drivers/gpu/drm/tiny/mi0283qt.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/mi0283qt.c	2019-08-31 15:01:12.233736201 -0500
>@@ -0,0 +1,294 @@
>+// SPDX-License-Identifier: GPL-2.0-or-later
>+/*
>+ * DRM driver for Multi-Inno MI0283QT panels
>+ *
>+ * Copyright 2016 Noralf TrÃ¸nnes
>+ */
>+
>+#include <linux/backlight.h>
>+#include <linux/delay.h>
>+#include <linux/gpio/consumer.h>
>+#include <linux/module.h>
>+#include <linux/property.h>
>+#include <linux/regulator/consumer.h>
>+#include <linux/spi/spi.h>
>+
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_fb_helper.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_mipi_dbi.h>
>+#include <drm/drm_modeset_helper.h>
>+#include <video/mipi_display.h>
>+
>+#define ILI9341_FRMCTR1		0xb1
>+#define ILI9341_DISCTRL		0xb6
>+#define ILI9341_ETMOD		0xb7
>+
>+#define ILI9341_PWCTRL1		0xc0
>+#define ILI9341_PWCTRL2		0xc1
>+#define ILI9341_VMCTRL1		0xc5
>+#define ILI9341_VMCTRL2		0xc7
>+#define ILI9341_PWCTRLA		0xcb
>+#define ILI9341_PWCTRLB		0xcf
>+
>+#define ILI9341_PGAMCTRL	0xe0
>+#define ILI9341_NGAMCTRL	0xe1
>+#define ILI9341_DTCTRLA		0xe8
>+#define ILI9341_DTCTRLB		0xea
>+#define ILI9341_PWRSEQ		0xed
>+
>+#define ILI9341_EN3GAM		0xf2
>+#define ILI9341_PUMPCTRL	0xf7
>+
>+#define ILI9341_MADCTL_BGR	BIT(3)
>+#define ILI9341_MADCTL_MV	BIT(5)
>+#define ILI9341_MADCTL_MX	BIT(6)
>+#define ILI9341_MADCTL_MY	BIT(7)
>+
>+static void mi0283qt_enable(struct drm_simple_display_pipe *pipe,
>+			    struct drm_crtc_state *crtc_state,
>+			    struct drm_plane_state *plane_state)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+	u8 addr_mode;
>+	int ret, idx;
>+
>+	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>+		return;
>+
>+	DRM_DEBUG_KMS("\n");
>+
>+	ret = mipi_dbi_poweron_conditional_reset(dbidev);
>+	if (ret < 0)
>+		goto out_exit;
>+	if (ret == 1)
>+		goto out_enable;
>+
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF);
>+
>+	mipi_dbi_command(dbi, ILI9341_PWCTRLB, 0x00, 0x83, 0x30);
>+	mipi_dbi_command(dbi, ILI9341_PWRSEQ, 0x64, 0x03, 0x12, 0x81);
>+	mipi_dbi_command(dbi, ILI9341_DTCTRLA, 0x85, 0x01, 0x79);
>+	mipi_dbi_command(dbi, ILI9341_PWCTRLA, 0x39, 0x2c, 0x00, 0x34, 0x02);
>+	mipi_dbi_command(dbi, ILI9341_PUMPCTRL, 0x20);
>+	mipi_dbi_command(dbi, ILI9341_DTCTRLB, 0x00, 0x00);
>+
>+	/* Power Control */
>+	mipi_dbi_command(dbi, ILI9341_PWCTRL1, 0x26);
>+	mipi_dbi_command(dbi, ILI9341_PWCTRL2, 0x11);
>+	/* VCOM */
>+	mipi_dbi_command(dbi, ILI9341_VMCTRL1, 0x35, 0x3e);
>+	mipi_dbi_command(dbi, ILI9341_VMCTRL2, 0xbe);
>+
>+	/* Memory Access Control */
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
>+
>+	/* Frame Rate */
>+	mipi_dbi_command(dbi, ILI9341_FRMCTR1, 0x00, 0x1b);
>+
>+	/* Gamma */
>+	mipi_dbi_command(dbi, ILI9341_EN3GAM, 0x08);
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x01);
>+	mipi_dbi_command(dbi, ILI9341_PGAMCTRL,
>+		       0x1f, 0x1a, 0x18, 0x0a, 0x0f, 0x06, 0x45, 0x87,
>+		       0x32, 0x0a, 0x07, 0x02, 0x07, 0x05, 0x00);
>+	mipi_dbi_command(dbi, ILI9341_NGAMCTRL,
>+		       0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3a, 0x78,
>+		       0x4d, 0x05, 0x18, 0x0d, 0x38, 0x3a, 0x1f);
>+
>+	/* DDRAM */
>+	mipi_dbi_command(dbi, ILI9341_ETMOD, 0x07);
>+
>+	/* Display */
>+	mipi_dbi_command(dbi, ILI9341_DISCTRL, 0x0a, 0x82, 0x27, 0x00);
>+	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
>+	msleep(100);
>+
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
>+	msleep(100);
>+
>+out_enable:
>+	/* The PiTFT (ili9340) has a hardware reset circuit that
>+	 * resets only on power-on and not on each reboot through
>+	 * a gpio like the rpi-display does.
>+	 * As a result, we need to always apply the rotation value
>+	 * regardless of the display "on/off" state.
>+	 */
>+	switch (dbidev->rotation) {
>+	default:
>+		addr_mode = ILI9341_MADCTL_MV | ILI9341_MADCTL_MY |
>+			    ILI9341_MADCTL_MX;
>+		break;
>+	case 90:
>+		addr_mode = ILI9341_MADCTL_MY;
>+		break;
>+	case 180:
>+		addr_mode = ILI9341_MADCTL_MV;
>+		break;
>+	case 270:
>+		addr_mode = ILI9341_MADCTL_MX;
>+		break;
>+	}
>+	addr_mode |= ILI9341_MADCTL_BGR;
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
>+	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
>+out_exit:
>+	drm_dev_exit(idx);
>+}
>+
>+static const struct drm_simple_display_pipe_funcs mi0283qt_pipe_funcs = {
>+	.enable = mi0283qt_enable,
>+	.disable = mipi_dbi_pipe_disable,
>+	.update = mipi_dbi_pipe_update,
>+	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
>+};
>+
>+static const struct drm_display_mode mi0283qt_mode = {
>+	DRM_SIMPLE_MODE(320, 240, 58, 43),
>+};
>+
>+DEFINE_DRM_GEM_CMA_FOPS(mi0283qt_fops);
>+
>+static struct drm_driver mi0283qt_driver = {
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
>+	.fops			= &mi0283qt_fops,
>+	.release		= mipi_dbi_release,
>+	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>+	.debugfs_init		= mipi_dbi_debugfs_init,
>+	.name			= "mi0283qt",
>+	.desc			= "Multi-Inno MI0283QT",
>+	.date			= "20160614",
>+	.major			= 1,
>+	.minor			= 0,
>+};
>+
>+static const struct of_device_id mi0283qt_of_match[] = {
>+	{ .compatible = "multi-inno,mi0283qt" },
>+	{},
>+};
>+MODULE_DEVICE_TABLE(of, mi0283qt_of_match);
>+
>+static const struct spi_device_id mi0283qt_id[] = {
>+	{ "mi0283qt", 0 },
>+	{ },
>+};
>+MODULE_DEVICE_TABLE(spi, mi0283qt_id);
>+
>+static int mi0283qt_probe(struct spi_device *spi)
>+{
>+	struct device *dev = &spi->dev;
>+	struct mipi_dbi_dev *dbidev;
>+	struct drm_device *drm;
>+	struct mipi_dbi *dbi;
>+	struct gpio_desc *dc;
>+	u32 rotation = 0;
>+	int ret;
>+
>+	dbidev = kzalloc(sizeof(*dbidev), GFP_KERNEL);
>+	if (!dbidev)
>+		return -ENOMEM;
>+
>+	dbi = &dbidev->dbi;
>+	drm = &dbidev->drm;
>+	ret = devm_drm_dev_init(dev, drm, &mi0283qt_driver);
>+	if (ret) {
>+		kfree(dbidev);
>+		return ret;
>+	}
>+
>+	drm_mode_config_init(drm);
>+
>+	dbi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
>+	if (IS_ERR(dbi->reset)) {
>+		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
>+		return PTR_ERR(dbi->reset);
>+	}
>+
>+	dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
>+	if (IS_ERR(dc)) {
>+		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
>+		return PTR_ERR(dc);
>+	}
>+
>+	dbidev->regulator = devm_regulator_get(dev, "power");
>+	if (IS_ERR(dbidev->regulator))
>+		return PTR_ERR(dbidev->regulator);
>+
>+	dbidev->backlight = devm_of_find_backlight(dev);
>+	if (IS_ERR(dbidev->backlight))
>+		return PTR_ERR(dbidev->backlight);
>+
>+	device_property_read_u32(dev, "rotation", &rotation);
>+
>+	ret = mipi_dbi_spi_init(spi, dbi, dc);
>+	if (ret)
>+		return ret;
>+
>+	ret = mipi_dbi_dev_init(dbidev, &mi0283qt_pipe_funcs, &mi0283qt_mode, rotation);
>+	if (ret)
>+		return ret;
>+
>+	drm_mode_config_reset(drm);
>+
>+	ret = drm_dev_register(drm, 0);
>+	if (ret)
>+		return ret;
>+
>+	spi_set_drvdata(spi, drm);
>+
>+	drm_fbdev_generic_setup(drm, 0);
>+
>+	return 0;
>+}
>+
>+static int mi0283qt_remove(struct spi_device *spi)
>+{
>+	struct drm_device *drm = spi_get_drvdata(spi);
>+
>+	drm_dev_unplug(drm);
>+	drm_atomic_helper_shutdown(drm);
>+
>+	return 0;
>+}
>+
>+static void mi0283qt_shutdown(struct spi_device *spi)
>+{
>+	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>+}
>+
>+static int __maybe_unused mi0283qt_pm_suspend(struct device *dev)
>+{
>+	return drm_mode_config_helper_suspend(dev_get_drvdata(dev));
>+}
>+
>+static int __maybe_unused mi0283qt_pm_resume(struct device *dev)
>+{
>+	drm_mode_config_helper_resume(dev_get_drvdata(dev));
>+
>+	return 0;
>+}
>+
>+static const struct dev_pm_ops mi0283qt_pm_ops = {
>+	SET_SYSTEM_SLEEP_PM_OPS(mi0283qt_pm_suspend, mi0283qt_pm_resume)
>+};
>+
>+static struct spi_driver mi0283qt_spi_driver = {
>+	.driver = {
>+		.name = "mi0283qt",
>+		.owner = THIS_MODULE,
>+		.of_match_table = mi0283qt_of_match,
>+		.pm = &mi0283qt_pm_ops,
>+	},
>+	.id_table = mi0283qt_id,
>+	.probe = mi0283qt_probe,
>+	.remove = mi0283qt_remove,
>+	.shutdown = mi0283qt_shutdown,
>+};
>+module_spi_driver(mi0283qt_spi_driver);
>+
>+MODULE_DESCRIPTION("Multi-Inno MI0283QT DRM driver");
>+MODULE_AUTHOR("Noralf TrÃ¸nnes");
>+MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tiny/repaper.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/repaper.c
>--- linux-5.3-rc6/drivers/gpu/drm/tiny/repaper.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/repaper.c	2019-08-31 15:01:12.233736201 -0500
>@@ -0,0 +1,1212 @@
>+// SPDX-License-Identifier: GPL-2.0-or-later
>+/*
>+ * DRM driver for Pervasive Displays RePaper branded e-ink panels
>+ *
>+ * Copyright 2013-2017 Pervasive Displays, Inc.
>+ * Copyright 2017 Noralf TrÃ¸nnes
>+ *
>+ * The driver supports:
>+ * Material Film: Aurora Mb (V231)
>+ * Driver IC: G2 (eTC)
>+ *
>+ * The controller code was taken from the userspace driver:
>+ * https://github.com/repaper/gratis
>+ */
>+
>+#include <linux/delay.h>
>+#include <linux/dma-buf.h>
>+#include <linux/gpio/consumer.h>
>+#include <linux/module.h>
>+#include <linux/of_device.h>
>+#include <linux/sched/clock.h>
>+#include <linux/spi/spi.h>
>+#include <linux/thermal.h>
>+
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_connector.h>
>+#include <drm/drm_damage_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fb_helper.h>
>+#include <drm/drm_format_helper.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_modes.h>
>+#include <drm/drm_rect.h>
>+#include <drm/drm_vblank.h>
>+#include <drm/drm_probe_helper.h>
>+#include <drm/drm_simple_kms_helper.h>
>+
>+#define REPAPER_RID_G2_COG_ID	0x12
>+
>+enum repaper_model {
>+	E1144CS021 = 1,
>+	E1190CS021,
>+	E2200CS021,
>+	E2271CS021,
>+};
>+
>+enum repaper_stage {         /* Image pixel -> Display pixel */
>+	REPAPER_COMPENSATE,  /* B -> W, W -> B (Current Image) */
>+	REPAPER_WHITE,       /* B -> N, W -> W (Current Image) */
>+	REPAPER_INVERSE,     /* B -> N, W -> B (New Image) */
>+	REPAPER_NORMAL       /* B -> B, W -> W (New Image) */
>+};
>+
>+enum repaper_epd_border_byte {
>+	REPAPER_BORDER_BYTE_NONE,
>+	REPAPER_BORDER_BYTE_ZERO,
>+	REPAPER_BORDER_BYTE_SET,
>+};
>+
>+struct repaper_epd {
>+	struct drm_device drm;
>+	struct drm_simple_display_pipe pipe;
>+	const struct drm_display_mode *mode;
>+	struct drm_connector connector;
>+	struct spi_device *spi;
>+
>+	struct gpio_desc *panel_on;
>+	struct gpio_desc *border;
>+	struct gpio_desc *discharge;
>+	struct gpio_desc *reset;
>+	struct gpio_desc *busy;
>+
>+	struct thermal_zone_device *thermal;
>+
>+	unsigned int height;
>+	unsigned int width;
>+	unsigned int bytes_per_scan;
>+	const u8 *channel_select;
>+	unsigned int stage_time;
>+	unsigned int factored_stage_time;
>+	bool middle_scan;
>+	bool pre_border_byte;
>+	enum repaper_epd_border_byte border_byte;
>+
>+	u8 *line_buffer;
>+	void *current_frame;
>+
>+	bool enabled;
>+	bool cleared;
>+	bool partial;
>+};
>+
>+static inline struct repaper_epd *drm_to_epd(struct drm_device *drm)
>+{
>+	return container_of(drm, struct repaper_epd, drm);
>+}
>+
>+static int repaper_spi_transfer(struct spi_device *spi, u8 header,
>+				const void *tx, void *rx, size_t len)
>+{
>+	void *txbuf = NULL, *rxbuf = NULL;
>+	struct spi_transfer tr[2] = {};
>+	u8 *headerbuf;
>+	int ret;
>+
>+	headerbuf = kmalloc(1, GFP_KERNEL);
>+	if (!headerbuf)
>+		return -ENOMEM;
>+
>+	headerbuf[0] = header;
>+	tr[0].tx_buf = headerbuf;
>+	tr[0].len = 1;
>+
>+	/* Stack allocated tx? */
>+	if (tx && len <= 32) {
>+		txbuf = kmemdup(tx, len, GFP_KERNEL);
>+		if (!txbuf) {
>+			ret = -ENOMEM;
>+			goto out_free;
>+		}
>+	}
>+
>+	if (rx) {
>+		rxbuf = kmalloc(len, GFP_KERNEL);
>+		if (!rxbuf) {
>+			ret = -ENOMEM;
>+			goto out_free;
>+		}
>+	}
>+
>+	tr[1].tx_buf = txbuf ? txbuf : tx;
>+	tr[1].rx_buf = rxbuf;
>+	tr[1].len = len;
>+
>+	ndelay(80);
>+	ret = spi_sync_transfer(spi, tr, 2);
>+	if (rx && !ret)
>+		memcpy(rx, rxbuf, len);
>+
>+out_free:
>+	kfree(headerbuf);
>+	kfree(txbuf);
>+	kfree(rxbuf);
>+
>+	return ret;
>+}
>+
>+static int repaper_write_buf(struct spi_device *spi, u8 reg,
>+			     const u8 *buf, size_t len)
>+{
>+	int ret;
>+
>+	ret = repaper_spi_transfer(spi, 0x70, &reg, NULL, 1);
>+	if (ret)
>+		return ret;
>+
>+	return repaper_spi_transfer(spi, 0x72, buf, NULL, len);
>+}
>+
>+static int repaper_write_val(struct spi_device *spi, u8 reg, u8 val)
>+{
>+	return repaper_write_buf(spi, reg, &val, 1);
>+}
>+
>+static int repaper_read_val(struct spi_device *spi, u8 reg)
>+{
>+	int ret;
>+	u8 val;
>+
>+	ret = repaper_spi_transfer(spi, 0x70, &reg, NULL, 1);
>+	if (ret)
>+		return ret;
>+
>+	ret = repaper_spi_transfer(spi, 0x73, NULL, &val, 1);
>+
>+	return ret ? ret : val;
>+}
>+
>+static int repaper_read_id(struct spi_device *spi)
>+{
>+	int ret;
>+	u8 id;
>+
>+	ret = repaper_spi_transfer(spi, 0x71, NULL, &id, 1);
>+
>+	return ret ? ret : id;
>+}
>+
>+static void repaper_spi_mosi_low(struct spi_device *spi)
>+{
>+	const u8 buf[1] = { 0 };
>+
>+	spi_write(spi, buf, 1);
>+}
>+
>+/* pixels on display are numbered from 1 so even is actually bits 1,3,5,... */
>+static void repaper_even_pixels(struct repaper_epd *epd, u8 **pp,
>+				const u8 *data, u8 fixed_value, const u8 *mask,
>+				enum repaper_stage stage)
>+{
>+	unsigned int b;
>+
>+	for (b = 0; b < (epd->width / 8); b++) {
>+		if (data) {
>+			u8 pixels = data[b] & 0xaa;
>+			u8 pixel_mask = 0xff;
>+			u8 p1, p2, p3, p4;
>+
>+			if (mask) {
>+				pixel_mask = (mask[b] ^ pixels) & 0xaa;
>+				pixel_mask |= pixel_mask >> 1;
>+			}
>+
>+			switch (stage) {
>+			case REPAPER_COMPENSATE: /* B -> W, W -> B (Current) */
>+				pixels = 0xaa | ((pixels ^ 0xaa) >> 1);
>+				break;
>+			case REPAPER_WHITE:      /* B -> N, W -> W (Current) */
>+				pixels = 0x55 + ((pixels ^ 0xaa) >> 1);
>+				break;
>+			case REPAPER_INVERSE:    /* B -> N, W -> B (New) */
>+				pixels = 0x55 | (pixels ^ 0xaa);
>+				break;
>+			case REPAPER_NORMAL:     /* B -> B, W -> W (New) */
>+				pixels = 0xaa | (pixels >> 1);
>+				break;
>+			}
>+
>+			pixels = (pixels & pixel_mask) | (~pixel_mask & 0x55);
>+			p1 = (pixels >> 6) & 0x03;
>+			p2 = (pixels >> 4) & 0x03;
>+			p3 = (pixels >> 2) & 0x03;
>+			p4 = (pixels >> 0) & 0x03;
>+			pixels = (p1 << 0) | (p2 << 2) | (p3 << 4) | (p4 << 6);
>+			*(*pp)++ = pixels;
>+		} else {
>+			*(*pp)++ = fixed_value;
>+		}
>+	}
>+}
>+
>+/* pixels on display are numbered from 1 so odd is actually bits 0,2,4,... */
>+static void repaper_odd_pixels(struct repaper_epd *epd, u8 **pp,
>+			       const u8 *data, u8 fixed_value, const u8 *mask,
>+			       enum repaper_stage stage)
>+{
>+	unsigned int b;
>+
>+	for (b = epd->width / 8; b > 0; b--) {
>+		if (data) {
>+			u8 pixels = data[b - 1] & 0x55;
>+			u8 pixel_mask = 0xff;
>+
>+			if (mask) {
>+				pixel_mask = (mask[b - 1] ^ pixels) & 0x55;
>+				pixel_mask |= pixel_mask << 1;
>+			}
>+
>+			switch (stage) {
>+			case REPAPER_COMPENSATE: /* B -> W, W -> B (Current) */
>+				pixels = 0xaa | (pixels ^ 0x55);
>+				break;
>+			case REPAPER_WHITE:      /* B -> N, W -> W (Current) */
>+				pixels = 0x55 + (pixels ^ 0x55);
>+				break;
>+			case REPAPER_INVERSE:    /* B -> N, W -> B (New) */
>+				pixels = 0x55 | ((pixels ^ 0x55) << 1);
>+				break;
>+			case REPAPER_NORMAL:     /* B -> B, W -> W (New) */
>+				pixels = 0xaa | pixels;
>+				break;
>+			}
>+
>+			pixels = (pixels & pixel_mask) | (~pixel_mask & 0x55);
>+			*(*pp)++ = pixels;
>+		} else {
>+			*(*pp)++ = fixed_value;
>+		}
>+	}
>+}
>+
>+/* interleave bits: (byte)76543210 -> (16 bit).7.6.5.4.3.2.1 */
>+static inline u16 repaper_interleave_bits(u16 value)
>+{
>+	value = (value | (value << 4)) & 0x0f0f;
>+	value = (value | (value << 2)) & 0x3333;
>+	value = (value | (value << 1)) & 0x5555;
>+
>+	return value;
>+}
>+
>+/* pixels on display are numbered from 1 */
>+static void repaper_all_pixels(struct repaper_epd *epd, u8 **pp,
>+			       const u8 *data, u8 fixed_value, const u8 *mask,
>+			       enum repaper_stage stage)
>+{
>+	unsigned int b;
>+
>+	for (b = epd->width / 8; b > 0; b--) {
>+		if (data) {
>+			u16 pixels = repaper_interleave_bits(data[b - 1]);
>+			u16 pixel_mask = 0xffff;
>+
>+			if (mask) {
>+				pixel_mask = repaper_interleave_bits(mask[b - 1]);
>+
>+				pixel_mask = (pixel_mask ^ pixels) & 0x5555;
>+				pixel_mask |= pixel_mask << 1;
>+			}
>+
>+			switch (stage) {
>+			case REPAPER_COMPENSATE: /* B -> W, W -> B (Current) */
>+				pixels = 0xaaaa | (pixels ^ 0x5555);
>+				break;
>+			case REPAPER_WHITE:      /* B -> N, W -> W (Current) */
>+				pixels = 0x5555 + (pixels ^ 0x5555);
>+				break;
>+			case REPAPER_INVERSE:    /* B -> N, W -> B (New) */
>+				pixels = 0x5555 | ((pixels ^ 0x5555) << 1);
>+				break;
>+			case REPAPER_NORMAL:     /* B -> B, W -> W (New) */
>+				pixels = 0xaaaa | pixels;
>+				break;
>+			}
>+
>+			pixels = (pixels & pixel_mask) | (~pixel_mask & 0x5555);
>+			*(*pp)++ = pixels >> 8;
>+			*(*pp)++ = pixels;
>+		} else {
>+			*(*pp)++ = fixed_value;
>+			*(*pp)++ = fixed_value;
>+		}
>+	}
>+}
>+
>+/* output one line of scan and data bytes to the display */
>+static void repaper_one_line(struct repaper_epd *epd, unsigned int line,
>+			     const u8 *data, u8 fixed_value, const u8 *mask,
>+			     enum repaper_stage stage)
>+{
>+	u8 *p = epd->line_buffer;
>+	unsigned int b;
>+
>+	repaper_spi_mosi_low(epd->spi);
>+
>+	if (epd->pre_border_byte)
>+		*p++ = 0x00;
>+
>+	if (epd->middle_scan) {
>+		/* data bytes */
>+		repaper_odd_pixels(epd, &p, data, fixed_value, mask, stage);
>+
>+		/* scan line */
>+		for (b = epd->bytes_per_scan; b > 0; b--) {
>+			if (line / 4 == b - 1)
>+				*p++ = 0x03 << (2 * (line & 0x03));
>+			else
>+				*p++ = 0x00;
>+		}
>+
>+		/* data bytes */
>+		repaper_even_pixels(epd, &p, data, fixed_value, mask, stage);
>+	} else {
>+		/*
>+		 * even scan line, but as lines on display are numbered from 1,
>+		 * line: 1,3,5,...
>+		 */
>+		for (b = 0; b < epd->bytes_per_scan; b++) {
>+			if (0 != (line & 0x01) && line / 8 == b)
>+				*p++ = 0xc0 >> (line & 0x06);
>+			else
>+				*p++ = 0x00;
>+		}
>+
>+		/* data bytes */
>+		repaper_all_pixels(epd, &p, data, fixed_value, mask, stage);
>+
>+		/*
>+		 * odd scan line, but as lines on display are numbered from 1,
>+		 * line: 0,2,4,6,...
>+		 */
>+		for (b = epd->bytes_per_scan; b > 0; b--) {
>+			if (0 == (line & 0x01) && line / 8 == b - 1)
>+				*p++ = 0x03 << (line & 0x06);
>+			else
>+				*p++ = 0x00;
>+		}
>+	}
>+
>+	switch (epd->border_byte) {
>+	case REPAPER_BORDER_BYTE_NONE:
>+		break;
>+
>+	case REPAPER_BORDER_BYTE_ZERO:
>+		*p++ = 0x00;
>+		break;
>+
>+	case REPAPER_BORDER_BYTE_SET:
>+		switch (stage) {
>+		case REPAPER_COMPENSATE:
>+		case REPAPER_WHITE:
>+		case REPAPER_INVERSE:
>+			*p++ = 0x00;
>+			break;
>+		case REPAPER_NORMAL:
>+			*p++ = 0xaa;
>+			break;
>+		}
>+		break;
>+	}
>+
>+	repaper_write_buf(epd->spi, 0x0a, epd->line_buffer,
>+			  p - epd->line_buffer);
>+
>+	/* Output data to panel */
>+	repaper_write_val(epd->spi, 0x02, 0x07);
>+
>+	repaper_spi_mosi_low(epd->spi);
>+}
>+
>+static void repaper_frame_fixed(struct repaper_epd *epd, u8 fixed_value,
>+				enum repaper_stage stage)
>+{
>+	unsigned int line;
>+
>+	for (line = 0; line < epd->height; line++)
>+		repaper_one_line(epd, line, NULL, fixed_value, NULL, stage);
>+}
>+
>+static void repaper_frame_data(struct repaper_epd *epd, const u8 *image,
>+			       const u8 *mask, enum repaper_stage stage)
>+{
>+	unsigned int line;
>+
>+	if (!mask) {
>+		for (line = 0; line < epd->height; line++) {
>+			repaper_one_line(epd, line,
>+					 &image[line * (epd->width / 8)],
>+					 0, NULL, stage);
>+		}
>+	} else {
>+		for (line = 0; line < epd->height; line++) {
>+			size_t n = line * epd->width / 8;
>+
>+			repaper_one_line(epd, line, &image[n], 0, &mask[n],
>+					 stage);
>+		}
>+	}
>+}
>+
>+static void repaper_frame_fixed_repeat(struct repaper_epd *epd, u8 fixed_value,
>+				       enum repaper_stage stage)
>+{
>+	u64 start = local_clock();
>+	u64 end = start + (epd->factored_stage_time * 1000 * 1000);
>+
>+	do {
>+		repaper_frame_fixed(epd, fixed_value, stage);
>+	} while (local_clock() < end);
>+}
>+
>+static void repaper_frame_data_repeat(struct repaper_epd *epd, const u8 *image,
>+				      const u8 *mask, enum repaper_stage stage)
>+{
>+	u64 start = local_clock();
>+	u64 end = start + (epd->factored_stage_time * 1000 * 1000);
>+
>+	do {
>+		repaper_frame_data(epd, image, mask, stage);
>+	} while (local_clock() < end);
>+}
>+
>+static void repaper_get_temperature(struct repaper_epd *epd)
>+{
>+	int ret, temperature = 0;
>+	unsigned int factor10x;
>+
>+	if (!epd->thermal)
>+		return;
>+
>+	ret = thermal_zone_get_temp(epd->thermal, &temperature);
>+	if (ret) {
>+		DRM_DEV_ERROR(&epd->spi->dev, "Failed to get temperature (%d)\n", ret);
>+		return;
>+	}
>+
>+	temperature /= 1000;
>+
>+	if (temperature <= -10)
>+		factor10x = 170;
>+	else if (temperature <= -5)
>+		factor10x = 120;
>+	else if (temperature <= 5)
>+		factor10x = 80;
>+	else if (temperature <= 10)
>+		factor10x = 40;
>+	else if (temperature <= 15)
>+		factor10x = 30;
>+	else if (temperature <= 20)
>+		factor10x = 20;
>+	else if (temperature <= 40)
>+		factor10x = 10;
>+	else
>+		factor10x = 7;
>+
>+	epd->factored_stage_time = epd->stage_time * factor10x / 10;
>+}
>+
>+static void repaper_gray8_to_mono_reversed(u8 *buf, u32 width, u32 height)
>+{
>+	u8 *gray8 = buf, *mono = buf;
>+	int y, xb, i;
>+
>+	for (y = 0; y < height; y++)
>+		for (xb = 0; xb < width / 8; xb++) {
>+			u8 byte = 0x00;
>+
>+			for (i = 0; i < 8; i++) {
>+				int x = xb * 8 + i;
>+
>+				byte >>= 1;
>+				if (gray8[y * width + x] >> 7)
>+					byte |= BIT(7);
>+			}
>+			*mono++ = byte;
>+		}
>+}
>+
>+static int repaper_fb_dirty(struct drm_framebuffer *fb)
>+{
>+	struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
>+	struct dma_buf_attachment *import_attach = cma_obj->base.import_attach;
>+	struct repaper_epd *epd = drm_to_epd(fb->dev);
>+	struct drm_rect clip;
>+	int idx, ret = 0;
>+	u8 *buf = NULL;
>+
>+	if (!epd->enabled)
>+		return 0;
>+
>+	if (!drm_dev_enter(fb->dev, &idx))
>+		return -ENODEV;
>+
>+	/* repaper can't do partial updates */
>+	clip.x1 = 0;
>+	clip.x2 = fb->width;
>+	clip.y1 = 0;
>+	clip.y2 = fb->height;
>+
>+	repaper_get_temperature(epd);
>+
>+	DRM_DEBUG("Flushing [FB:%d] st=%ums\n", fb->base.id,
>+		  epd->factored_stage_time);
>+
>+	buf = kmalloc_array(fb->width, fb->height, GFP_KERNEL);
>+	if (!buf) {
>+		ret = -ENOMEM;
>+		goto out_exit;
>+	}
>+
>+	if (import_attach) {
>+		ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
>+					       DMA_FROM_DEVICE);
>+		if (ret)
>+			goto out_free;
>+	}
>+
>+	drm_fb_xrgb8888_to_gray8(buf, cma_obj->vaddr, fb, &clip);
>+
>+	if (import_attach) {
>+		ret = dma_buf_end_cpu_access(import_attach->dmabuf,
>+					     DMA_FROM_DEVICE);
>+		if (ret)
>+			goto out_free;
>+	}
>+
>+	repaper_gray8_to_mono_reversed(buf, fb->width, fb->height);
>+
>+	if (epd->partial) {
>+		repaper_frame_data_repeat(epd, buf, epd->current_frame,
>+					  REPAPER_NORMAL);
>+	} else if (epd->cleared) {
>+		repaper_frame_data_repeat(epd, epd->current_frame, NULL,
>+					  REPAPER_COMPENSATE);
>+		repaper_frame_data_repeat(epd, epd->current_frame, NULL,
>+					  REPAPER_WHITE);
>+		repaper_frame_data_repeat(epd, buf, NULL, REPAPER_INVERSE);
>+		repaper_frame_data_repeat(epd, buf, NULL, REPAPER_NORMAL);
>+
>+		epd->partial = true;
>+	} else {
>+		/* Clear display (anything -> white) */
>+		repaper_frame_fixed_repeat(epd, 0xff, REPAPER_COMPENSATE);
>+		repaper_frame_fixed_repeat(epd, 0xff, REPAPER_WHITE);
>+		repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_INVERSE);
>+		repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_NORMAL);
>+
>+		/* Assuming a clear (white) screen output an image */
>+		repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_COMPENSATE);
>+		repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_WHITE);
>+		repaper_frame_data_repeat(epd, buf, NULL, REPAPER_INVERSE);
>+		repaper_frame_data_repeat(epd, buf, NULL, REPAPER_NORMAL);
>+
>+		epd->cleared = true;
>+		epd->partial = true;
>+	}
>+
>+	memcpy(epd->current_frame, buf, fb->width * fb->height / 8);
>+
>+	/*
>+	 * An extra frame write is needed if pixels are set in the bottom line,
>+	 * or else grey lines rises up from the pixels
>+	 */
>+	if (epd->pre_border_byte) {
>+		unsigned int x;
>+
>+		for (x = 0; x < (fb->width / 8); x++)
>+			if (buf[x + (fb->width * (fb->height - 1) / 8)]) {
>+				repaper_frame_data_repeat(epd, buf,
>+							  epd->current_frame,
>+							  REPAPER_NORMAL);
>+				break;
>+			}
>+	}
>+
>+out_free:
>+	kfree(buf);
>+out_exit:
>+	drm_dev_exit(idx);
>+
>+	return ret;
>+}
>+
>+static void power_off(struct repaper_epd *epd)
>+{
>+	/* Turn off power and all signals */
>+	gpiod_set_value_cansleep(epd->reset, 0);
>+	gpiod_set_value_cansleep(epd->panel_on, 0);
>+	if (epd->border)
>+		gpiod_set_value_cansleep(epd->border, 0);
>+
>+	/* Ensure SPI MOSI and CLOCK are Low before CS Low */
>+	repaper_spi_mosi_low(epd->spi);
>+
>+	/* Discharge pulse */
>+	gpiod_set_value_cansleep(epd->discharge, 1);
>+	msleep(150);
>+	gpiod_set_value_cansleep(epd->discharge, 0);
>+}
>+
>+static void repaper_pipe_enable(struct drm_simple_display_pipe *pipe,
>+				struct drm_crtc_state *crtc_state,
>+				struct drm_plane_state *plane_state)
>+{
>+	struct repaper_epd *epd = drm_to_epd(pipe->crtc.dev);
>+	struct spi_device *spi = epd->spi;
>+	struct device *dev = &spi->dev;
>+	bool dc_ok = false;
>+	int i, ret, idx;
>+
>+	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>+		return;
>+
>+	DRM_DEBUG_DRIVER("\n");
>+
>+	/* Power up sequence */
>+	gpiod_set_value_cansleep(epd->reset, 0);
>+	gpiod_set_value_cansleep(epd->panel_on, 0);
>+	gpiod_set_value_cansleep(epd->discharge, 0);
>+	if (epd->border)
>+		gpiod_set_value_cansleep(epd->border, 0);
>+	repaper_spi_mosi_low(spi);
>+	usleep_range(5000, 10000);
>+
>+	gpiod_set_value_cansleep(epd->panel_on, 1);
>+	/*
>+	 * This delay comes from the repaper.org userspace driver, it's not
>+	 * mentioned in the datasheet.
>+	 */
>+	usleep_range(10000, 15000);
>+	gpiod_set_value_cansleep(epd->reset, 1);
>+	if (epd->border)
>+		gpiod_set_value_cansleep(epd->border, 1);
>+	usleep_range(5000, 10000);
>+	gpiod_set_value_cansleep(epd->reset, 0);
>+	usleep_range(5000, 10000);
>+	gpiod_set_value_cansleep(epd->reset, 1);
>+	usleep_range(5000, 10000);
>+
>+	/* Wait for COG to become ready */
>+	for (i = 100; i > 0; i--) {
>+		if (!gpiod_get_value_cansleep(epd->busy))
>+			break;
>+
>+		usleep_range(10, 100);
>+	}
>+
>+	if (!i) {
>+		DRM_DEV_ERROR(dev, "timeout waiting for panel to become ready.\n");
>+		power_off(epd);
>+		goto out_exit;
>+	}
>+
>+	repaper_read_id(spi);
>+	ret = repaper_read_id(spi);
>+	if (ret != REPAPER_RID_G2_COG_ID) {
>+		if (ret < 0)
>+			dev_err(dev, "failed to read chip (%d)\n", ret);
>+		else
>+			dev_err(dev, "wrong COG ID 0x%02x\n", ret);
>+		power_off(epd);
>+		goto out_exit;
>+	}
>+
>+	/* Disable OE */
>+	repaper_write_val(spi, 0x02, 0x40);
>+
>+	ret = repaper_read_val(spi, 0x0f);
>+	if (ret < 0 || !(ret & 0x80)) {
>+		if (ret < 0)
>+			DRM_DEV_ERROR(dev, "failed to read chip (%d)\n", ret);
>+		else
>+			DRM_DEV_ERROR(dev, "panel is reported broken\n");
>+		power_off(epd);
>+		goto out_exit;
>+	}
>+
>+	/* Power saving mode */
>+	repaper_write_val(spi, 0x0b, 0x02);
>+	/* Channel select */
>+	repaper_write_buf(spi, 0x01, epd->channel_select, 8);
>+	/* High power mode osc */
>+	repaper_write_val(spi, 0x07, 0xd1);
>+	/* Power setting */
>+	repaper_write_val(spi, 0x08, 0x02);
>+	/* Vcom level */
>+	repaper_write_val(spi, 0x09, 0xc2);
>+	/* Power setting */
>+	repaper_write_val(spi, 0x04, 0x03);
>+	/* Driver latch on */
>+	repaper_write_val(spi, 0x03, 0x01);
>+	/* Driver latch off */
>+	repaper_write_val(spi, 0x03, 0x00);
>+	usleep_range(5000, 10000);
>+
>+	/* Start chargepump */
>+	for (i = 0; i < 4; ++i) {
>+		/* Charge pump positive voltage on - VGH/VDL on */
>+		repaper_write_val(spi, 0x05, 0x01);
>+		msleep(240);
>+
>+		/* Charge pump negative voltage on - VGL/VDL on */
>+		repaper_write_val(spi, 0x05, 0x03);
>+		msleep(40);
>+
>+		/* Charge pump Vcom on - Vcom driver on */
>+		repaper_write_val(spi, 0x05, 0x0f);
>+		msleep(40);
>+
>+		/* check DC/DC */
>+		ret = repaper_read_val(spi, 0x0f);
>+		if (ret < 0) {
>+			DRM_DEV_ERROR(dev, "failed to read chip (%d)\n", ret);
>+			power_off(epd);
>+			goto out_exit;
>+		}
>+
>+		if (ret & 0x40) {
>+			dc_ok = true;
>+			break;
>+		}
>+	}
>+
>+	if (!dc_ok) {
>+		DRM_DEV_ERROR(dev, "dc/dc failed\n");
>+		power_off(epd);
>+		goto out_exit;
>+	}
>+
>+	/*
>+	 * Output enable to disable
>+	 * The userspace driver sets this to 0x04, but the datasheet says 0x06
>+	 */
>+	repaper_write_val(spi, 0x02, 0x04);
>+
>+	epd->enabled = true;
>+	epd->partial = false;
>+out_exit:
>+	drm_dev_exit(idx);
>+}
>+
>+static void repaper_pipe_disable(struct drm_simple_display_pipe *pipe)
>+{
>+	struct repaper_epd *epd = drm_to_epd(pipe->crtc.dev);
>+	struct spi_device *spi = epd->spi;
>+	unsigned int line;
>+
>+	/*
>+	 * This callback is not protected by drm_dev_enter/exit since we want to
>+	 * turn off the display on regular driver unload. It's highly unlikely
>+	 * that the underlying SPI controller is gone should this be called after
>+	 * unplug.
>+	 */
>+
>+	if (!epd->enabled)
>+		return;
>+
>+	DRM_DEBUG_DRIVER("\n");
>+
>+	epd->enabled = false;
>+
>+	/* Nothing frame */
>+	for (line = 0; line < epd->height; line++)
>+		repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL,
>+				 REPAPER_COMPENSATE);
>+
>+	/* 2.7" */
>+	if (epd->border) {
>+		/* Dummy line */
>+		repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL,
>+				 REPAPER_COMPENSATE);
>+		msleep(25);
>+		gpiod_set_value_cansleep(epd->border, 0);
>+		msleep(200);
>+		gpiod_set_value_cansleep(epd->border, 1);
>+	} else {
>+		/* Border dummy line */
>+		repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL,
>+				 REPAPER_NORMAL);
>+		msleep(200);
>+	}
>+
>+	/* not described in datasheet */
>+	repaper_write_val(spi, 0x0b, 0x00);
>+	/* Latch reset turn on */
>+	repaper_write_val(spi, 0x03, 0x01);
>+	/* Power off charge pump Vcom */
>+	repaper_write_val(spi, 0x05, 0x03);
>+	/* Power off charge pump neg voltage */
>+	repaper_write_val(spi, 0x05, 0x01);
>+	msleep(120);
>+	/* Discharge internal */
>+	repaper_write_val(spi, 0x04, 0x80);
>+	/* turn off all charge pumps */
>+	repaper_write_val(spi, 0x05, 0x00);
>+	/* Turn off osc */
>+	repaper_write_val(spi, 0x07, 0x01);
>+	msleep(50);
>+
>+	power_off(epd);
>+}
>+
>+static void repaper_pipe_update(struct drm_simple_display_pipe *pipe,
>+				struct drm_plane_state *old_state)
>+{
>+	struct drm_plane_state *state = pipe->plane.state;
>+	struct drm_crtc *crtc = &pipe->crtc;
>+	struct drm_rect rect;
>+
>+	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
>+		repaper_fb_dirty(state->fb);
>+
>+	if (crtc->state->event) {
>+		spin_lock_irq(&crtc->dev->event_lock);
>+		drm_crtc_send_vblank_event(crtc, crtc->state->event);
>+		spin_unlock_irq(&crtc->dev->event_lock);
>+		crtc->state->event = NULL;
>+	}
>+}
>+
>+static const struct drm_simple_display_pipe_funcs repaper_pipe_funcs = {
>+	.enable = repaper_pipe_enable,
>+	.disable = repaper_pipe_disable,
>+	.update = repaper_pipe_update,
>+	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
>+};
>+
>+static int repaper_connector_get_modes(struct drm_connector *connector)
>+{
>+	struct repaper_epd *epd = drm_to_epd(connector->dev);
>+	struct drm_display_mode *mode;
>+
>+	mode = drm_mode_duplicate(connector->dev, epd->mode);
>+	if (!mode) {
>+		DRM_ERROR("Failed to duplicate mode\n");
>+		return 0;
>+	}
>+
>+	drm_mode_set_name(mode);
>+	mode->type |= DRM_MODE_TYPE_PREFERRED;
>+	drm_mode_probed_add(connector, mode);
>+
>+	connector->display_info.width_mm = mode->width_mm;
>+	connector->display_info.height_mm = mode->height_mm;
>+
>+	return 1;
>+}
>+
>+static const struct drm_connector_helper_funcs repaper_connector_hfuncs = {
>+	.get_modes = repaper_connector_get_modes,
>+};
>+
>+static const struct drm_connector_funcs repaper_connector_funcs = {
>+	.reset = drm_atomic_helper_connector_reset,
>+	.fill_modes = drm_helper_probe_single_connector_modes,
>+	.destroy = drm_connector_cleanup,
>+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
>+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>+};
>+
>+static const struct drm_mode_config_funcs repaper_mode_config_funcs = {
>+	.fb_create = drm_gem_fb_create_with_dirty,
>+	.atomic_check = drm_atomic_helper_check,
>+	.atomic_commit = drm_atomic_helper_commit,
>+};
>+
>+static void repaper_release(struct drm_device *drm)
>+{
>+	struct repaper_epd *epd = drm_to_epd(drm);
>+
>+	DRM_DEBUG_DRIVER("\n");
>+
>+	drm_mode_config_cleanup(drm);
>+	drm_dev_fini(drm);
>+	kfree(epd);
>+}
>+
>+static const uint32_t repaper_formats[] = {
>+	DRM_FORMAT_XRGB8888,
>+};
>+
>+static const struct drm_display_mode repaper_e1144cs021_mode = {
>+	DRM_SIMPLE_MODE(128, 96, 29, 22),
>+};
>+
>+static const u8 repaper_e1144cs021_cs[] = { 0x00, 0x00, 0x00, 0x00,
>+					    0x00, 0x0f, 0xff, 0x00 };
>+
>+static const struct drm_display_mode repaper_e1190cs021_mode = {
>+	DRM_SIMPLE_MODE(144, 128, 36, 32),
>+};
>+
>+static const u8 repaper_e1190cs021_cs[] = { 0x00, 0x00, 0x00, 0x03,
>+					    0xfc, 0x00, 0x00, 0xff };
>+
>+static const struct drm_display_mode repaper_e2200cs021_mode = {
>+	DRM_SIMPLE_MODE(200, 96, 46, 22),
>+};
>+
>+static const u8 repaper_e2200cs021_cs[] = { 0x00, 0x00, 0x00, 0x00,
>+					    0x01, 0xff, 0xe0, 0x00 };
>+
>+static const struct drm_display_mode repaper_e2271cs021_mode = {
>+	DRM_SIMPLE_MODE(264, 176, 57, 38),
>+};
>+
>+static const u8 repaper_e2271cs021_cs[] = { 0x00, 0x00, 0x00, 0x7f,
>+					    0xff, 0xfe, 0x00, 0x00 };
>+
>+DEFINE_DRM_GEM_CMA_FOPS(repaper_fops);
>+
>+static struct drm_driver repaper_driver = {
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
>+	.fops			= &repaper_fops,
>+	.release		= repaper_release,
>+	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>+	.name			= "repaper",
>+	.desc			= "Pervasive Displays RePaper e-ink panels",
>+	.date			= "20170405",
>+	.major			= 1,
>+	.minor			= 0,
>+};
>+
>+static const struct of_device_id repaper_of_match[] = {
>+	{ .compatible = "pervasive,e1144cs021", .data = (void *)E1144CS021 },
>+	{ .compatible = "pervasive,e1190cs021", .data = (void *)E1190CS021 },
>+	{ .compatible = "pervasive,e2200cs021", .data = (void *)E2200CS021 },
>+	{ .compatible = "pervasive,e2271cs021", .data = (void *)E2271CS021 },
>+	{},
>+};
>+MODULE_DEVICE_TABLE(of, repaper_of_match);
>+
>+static const struct spi_device_id repaper_id[] = {
>+	{ "e1144cs021", E1144CS021 },
>+	{ "e1190cs021", E1190CS021 },
>+	{ "e2200cs021", E2200CS021 },
>+	{ "e2271cs021", E2271CS021 },
>+	{ },
>+};
>+MODULE_DEVICE_TABLE(spi, repaper_id);
>+
>+static int repaper_probe(struct spi_device *spi)
>+{
>+	const struct drm_display_mode *mode;
>+	const struct spi_device_id *spi_id;
>+	const struct of_device_id *match;
>+	struct device *dev = &spi->dev;
>+	enum repaper_model model;
>+	const char *thermal_zone;
>+	struct repaper_epd *epd;
>+	size_t line_buffer_size;
>+	struct drm_device *drm;
>+	int ret;
>+
>+	match = of_match_device(repaper_of_match, dev);
>+	if (match) {
>+		model = (enum repaper_model)match->data;
>+	} else {
>+		spi_id = spi_get_device_id(spi);
>+		model = spi_id->driver_data;
>+	}
>+
>+	/* The SPI device is used to allocate dma memory */
>+	if (!dev->coherent_dma_mask) {
>+		ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
>+		if (ret) {
>+			dev_warn(dev, "Failed to set dma mask %d\n", ret);
>+			return ret;
>+		}
>+	}
>+
>+	epd = kzalloc(sizeof(*epd), GFP_KERNEL);
>+	if (!epd)
>+		return -ENOMEM;
>+
>+	drm = &epd->drm;
>+
>+	ret = devm_drm_dev_init(dev, drm, &repaper_driver);
>+	if (ret) {
>+		kfree(epd);
>+		return ret;
>+	}
>+
>+	drm_mode_config_init(drm);
>+	drm->mode_config.funcs = &repaper_mode_config_funcs;
>+
>+	epd->spi = spi;
>+
>+	epd->panel_on = devm_gpiod_get(dev, "panel-on", GPIOD_OUT_LOW);
>+	if (IS_ERR(epd->panel_on)) {
>+		ret = PTR_ERR(epd->panel_on);
>+		if (ret != -EPROBE_DEFER)
>+			DRM_DEV_ERROR(dev, "Failed to get gpio 'panel-on'\n");
>+		return ret;
>+	}
>+
>+	epd->discharge = devm_gpiod_get(dev, "discharge", GPIOD_OUT_LOW);
>+	if (IS_ERR(epd->discharge)) {
>+		ret = PTR_ERR(epd->discharge);
>+		if (ret != -EPROBE_DEFER)
>+			DRM_DEV_ERROR(dev, "Failed to get gpio 'discharge'\n");
>+		return ret;
>+	}
>+
>+	epd->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
>+	if (IS_ERR(epd->reset)) {
>+		ret = PTR_ERR(epd->reset);
>+		if (ret != -EPROBE_DEFER)
>+			DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
>+		return ret;
>+	}
>+
>+	epd->busy = devm_gpiod_get(dev, "busy", GPIOD_IN);
>+	if (IS_ERR(epd->busy)) {
>+		ret = PTR_ERR(epd->busy);
>+		if (ret != -EPROBE_DEFER)
>+			DRM_DEV_ERROR(dev, "Failed to get gpio 'busy'\n");
>+		return ret;
>+	}
>+
>+	if (!device_property_read_string(dev, "pervasive,thermal-zone",
>+					 &thermal_zone)) {
>+		epd->thermal = thermal_zone_get_zone_by_name(thermal_zone);
>+		if (IS_ERR(epd->thermal)) {
>+			DRM_DEV_ERROR(dev, "Failed to get thermal zone: %s\n", thermal_zone);
>+			return PTR_ERR(epd->thermal);
>+		}
>+	}
>+
>+	switch (model) {
>+	case E1144CS021:
>+		mode = &repaper_e1144cs021_mode;
>+		epd->channel_select = repaper_e1144cs021_cs;
>+		epd->stage_time = 480;
>+		epd->bytes_per_scan = 96 / 4;
>+		epd->middle_scan = true; /* data-scan-data */
>+		epd->pre_border_byte = false;
>+		epd->border_byte = REPAPER_BORDER_BYTE_ZERO;
>+		break;
>+
>+	case E1190CS021:
>+		mode = &repaper_e1190cs021_mode;
>+		epd->channel_select = repaper_e1190cs021_cs;
>+		epd->stage_time = 480;
>+		epd->bytes_per_scan = 128 / 4 / 2;
>+		epd->middle_scan = false; /* scan-data-scan */
>+		epd->pre_border_byte = false;
>+		epd->border_byte = REPAPER_BORDER_BYTE_SET;
>+		break;
>+
>+	case E2200CS021:
>+		mode = &repaper_e2200cs021_mode;
>+		epd->channel_select = repaper_e2200cs021_cs;
>+		epd->stage_time = 480;
>+		epd->bytes_per_scan = 96 / 4;
>+		epd->middle_scan = true; /* data-scan-data */
>+		epd->pre_border_byte = true;
>+		epd->border_byte = REPAPER_BORDER_BYTE_NONE;
>+		break;
>+
>+	case E2271CS021:
>+		epd->border = devm_gpiod_get(dev, "border", GPIOD_OUT_LOW);
>+		if (IS_ERR(epd->border)) {
>+			ret = PTR_ERR(epd->border);
>+			if (ret != -EPROBE_DEFER)
>+				DRM_DEV_ERROR(dev, "Failed to get gpio 'border'\n");
>+			return ret;
>+		}
>+
>+		mode = &repaper_e2271cs021_mode;
>+		epd->channel_select = repaper_e2271cs021_cs;
>+		epd->stage_time = 630;
>+		epd->bytes_per_scan = 176 / 4;
>+		epd->middle_scan = true; /* data-scan-data */
>+		epd->pre_border_byte = true;
>+		epd->border_byte = REPAPER_BORDER_BYTE_NONE;
>+		break;
>+
>+	default:
>+		return -ENODEV;
>+	}
>+
>+	epd->mode = mode;
>+	epd->width = mode->hdisplay;
>+	epd->height = mode->vdisplay;
>+	epd->factored_stage_time = epd->stage_time;
>+
>+	line_buffer_size = 2 * epd->width / 8 + epd->bytes_per_scan + 2;
>+	epd->line_buffer = devm_kzalloc(dev, line_buffer_size, GFP_KERNEL);
>+	if (!epd->line_buffer)
>+		return -ENOMEM;
>+
>+	epd->current_frame = devm_kzalloc(dev, epd->width * epd->height / 8,
>+					  GFP_KERNEL);
>+	if (!epd->current_frame)
>+		return -ENOMEM;
>+
>+	drm->mode_config.min_width = mode->hdisplay;
>+	drm->mode_config.max_width = mode->hdisplay;
>+	drm->mode_config.min_height = mode->vdisplay;
>+	drm->mode_config.max_height = mode->vdisplay;
>+
>+	drm_connector_helper_add(&epd->connector, &repaper_connector_hfuncs);
>+	ret = drm_connector_init(drm, &epd->connector, &repaper_connector_funcs,
>+				 DRM_MODE_CONNECTOR_SPI);
>+	if (ret)
>+		return ret;
>+
>+	ret = drm_simple_display_pipe_init(drm, &epd->pipe, &repaper_pipe_funcs,
>+					   repaper_formats, ARRAY_SIZE(repaper_formats),
>+					   NULL, &epd->connector);
>+	if (ret)
>+		return ret;
>+
>+	drm_mode_config_reset(drm);
>+
>+	ret = drm_dev_register(drm, 0);
>+	if (ret)
>+		return ret;
>+
>+	spi_set_drvdata(spi, drm);
>+
>+	DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
>+
>+	drm_fbdev_generic_setup(drm, 0);
>+
>+	return 0;
>+}
>+
>+static int repaper_remove(struct spi_device *spi)
>+{
>+	struct drm_device *drm = spi_get_drvdata(spi);
>+
>+	drm_dev_unplug(drm);
>+	drm_atomic_helper_shutdown(drm);
>+
>+	return 0;
>+}
>+
>+static void repaper_shutdown(struct spi_device *spi)
>+{
>+	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>+}
>+
>+static struct spi_driver repaper_spi_driver = {
>+	.driver = {
>+		.name = "repaper",
>+		.owner = THIS_MODULE,
>+		.of_match_table = repaper_of_match,
>+	},
>+	.id_table = repaper_id,
>+	.probe = repaper_probe,
>+	.remove = repaper_remove,
>+	.shutdown = repaper_shutdown,
>+};
>+module_spi_driver(repaper_spi_driver);
>+
>+MODULE_DESCRIPTION("Pervasive Displays RePaper DRM driver");
>+MODULE_AUTHOR("Noralf TrÃ¸nnes");
>+MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tiny/st7586.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/st7586.c
>--- linux-5.3-rc6/drivers/gpu/drm/tiny/st7586.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/st7586.c	2019-08-31 15:01:12.233736201 -0500
>@@ -0,0 +1,424 @@
>+// SPDX-License-Identifier: GPL-2.0-or-later
>+/*
>+ * DRM driver for Sitronix ST7586 panels
>+ *
>+ * Copyright 2017 David Lechner <david@lechnology.com>
>+ */
>+
>+#include <linux/delay.h>
>+#include <linux/dma-buf.h>
>+#include <linux/gpio/consumer.h>
>+#include <linux/module.h>
>+#include <linux/property.h>
>+#include <linux/spi/spi.h>
>+#include <video/mipi_display.h>
>+
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_damage_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fb_helper.h>
>+#include <drm/drm_format_helper.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_mipi_dbi.h>
>+#include <drm/drm_rect.h>
>+#include <drm/drm_vblank.h>
>+
>+/* controller-specific commands */
>+#define ST7586_DISP_MODE_GRAY	0x38
>+#define ST7586_DISP_MODE_MONO	0x39
>+#define ST7586_ENABLE_DDRAM	0x3a
>+#define ST7586_SET_DISP_DUTY	0xb0
>+#define ST7586_SET_PART_DISP	0xb4
>+#define ST7586_SET_NLINE_INV	0xb5
>+#define ST7586_SET_VOP		0xc0
>+#define ST7586_SET_BIAS_SYSTEM	0xc3
>+#define ST7586_SET_BOOST_LEVEL	0xc4
>+#define ST7586_SET_VOP_OFFSET	0xc7
>+#define ST7586_ENABLE_ANALOG	0xd0
>+#define ST7586_AUTO_READ_CTRL	0xd7
>+#define ST7586_OTP_RW_CTRL	0xe0
>+#define ST7586_OTP_CTRL_OUT	0xe1
>+#define ST7586_OTP_READ		0xe3
>+
>+#define ST7586_DISP_CTRL_MX	BIT(6)
>+#define ST7586_DISP_CTRL_MY	BIT(7)
>+
>+/*
>+ * The ST7586 controller has an unusual pixel format where 2bpp grayscale is
>+ * packed 3 pixels per byte with the first two pixels using 3 bits and the 3rd
>+ * pixel using only 2 bits.
>+ *
>+ * |  D7  |  D6  |  D5  ||      |      || 2bpp |
>+ * | (D4) | (D3) | (D2) ||  D1  |  D0  || GRAY |
>+ * +------+------+------++------+------++------+
>+ * |  1   |  1   |  1   ||  1   |  1   || 0  0 | black
>+ * |  1   |  0   |  0   ||  1   |  0   || 0  1 | dark gray
>+ * |  0   |  1   |  0   ||  0   |  1   || 1  0 | light gray
>+ * |  0   |  0   |  0   ||  0   |  0   || 1  1 | white
>+ */
>+
>+static const u8 st7586_lookup[] = { 0x7, 0x4, 0x2, 0x0 };
>+
>+static void st7586_xrgb8888_to_gray332(u8 *dst, void *vaddr,
>+				       struct drm_framebuffer *fb,
>+				       struct drm_rect *clip)
>+{
>+	size_t len = (clip->x2 - clip->x1) * (clip->y2 - clip->y1);
>+	unsigned int x, y;
>+	u8 *src, *buf, val;
>+
>+	buf = kmalloc(len, GFP_KERNEL);
>+	if (!buf)
>+		return;
>+
>+	drm_fb_xrgb8888_to_gray8(buf, vaddr, fb, clip);
>+	src = buf;
>+
>+	for (y = clip->y1; y < clip->y2; y++) {
>+		for (x = clip->x1; x < clip->x2; x += 3) {
>+			val = st7586_lookup[*src++ >> 6] << 5;
>+			val |= st7586_lookup[*src++ >> 6] << 2;
>+			val |= st7586_lookup[*src++ >> 6] >> 1;
>+			*dst++ = val;
>+		}
>+	}
>+
>+	kfree(buf);
>+}
>+
>+static int st7586_buf_copy(void *dst, struct drm_framebuffer *fb,
>+			   struct drm_rect *clip)
>+{
>+	struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
>+	struct dma_buf_attachment *import_attach = cma_obj->base.import_attach;
>+	void *src = cma_obj->vaddr;
>+	int ret = 0;
>+
>+	if (import_attach) {
>+		ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
>+					       DMA_FROM_DEVICE);
>+		if (ret)
>+			return ret;
>+	}
>+
>+	st7586_xrgb8888_to_gray332(dst, src, fb, clip);
>+
>+	if (import_attach)
>+		ret = dma_buf_end_cpu_access(import_attach->dmabuf,
>+					     DMA_FROM_DEVICE);
>+
>+	return ret;
>+}
>+
>+static void st7586_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(fb->dev);
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+	int start, end, idx, ret = 0;
>+
>+	if (!dbidev->enabled)
>+		return;
>+
>+	if (!drm_dev_enter(fb->dev, &idx))
>+		return;
>+
>+	/* 3 pixels per byte, so grow clip to nearest multiple of 3 */
>+	rect->x1 = rounddown(rect->x1, 3);
>+	rect->x2 = roundup(rect->x2, 3);
>+
>+	DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
>+
>+	ret = st7586_buf_copy(dbidev->tx_buf, fb, rect);
>+	if (ret)
>+		goto err_msg;
>+
>+	/* Pixels are packed 3 per byte */
>+	start = rect->x1 / 3;
>+	end = rect->x2 / 3;
>+
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS,
>+			 (start >> 8) & 0xFF, start & 0xFF,
>+			 (end >> 8) & 0xFF, (end - 1) & 0xFF);
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS,
>+			 (rect->y1 >> 8) & 0xFF, rect->y1 & 0xFF,
>+			 (rect->y2 >> 8) & 0xFF, (rect->y2 - 1) & 0xFF);
>+
>+	ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
>+				   (u8 *)dbidev->tx_buf,
>+				   (end - start) * (rect->y2 - rect->y1));
>+err_msg:
>+	if (ret)
>+		dev_err_once(fb->dev->dev, "Failed to update display %d\n", ret);
>+
>+	drm_dev_exit(idx);
>+}
>+
>+static void st7586_pipe_update(struct drm_simple_display_pipe *pipe,
>+			       struct drm_plane_state *old_state)
>+{
>+	struct drm_plane_state *state = pipe->plane.state;
>+	struct drm_crtc *crtc = &pipe->crtc;
>+	struct drm_rect rect;
>+
>+	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
>+		st7586_fb_dirty(state->fb, &rect);
>+
>+	if (crtc->state->event) {
>+		spin_lock_irq(&crtc->dev->event_lock);
>+		drm_crtc_send_vblank_event(crtc, crtc->state->event);
>+		spin_unlock_irq(&crtc->dev->event_lock);
>+		crtc->state->event = NULL;
>+	}
>+}
>+
>+static void st7586_pipe_enable(struct drm_simple_display_pipe *pipe,
>+			       struct drm_crtc_state *crtc_state,
>+			       struct drm_plane_state *plane_state)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
>+	struct drm_framebuffer *fb = plane_state->fb;
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+	struct drm_rect rect = {
>+		.x1 = 0,
>+		.x2 = fb->width,
>+		.y1 = 0,
>+		.y2 = fb->height,
>+	};
>+	int idx, ret;
>+	u8 addr_mode;
>+
>+	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>+		return;
>+
>+	DRM_DEBUG_KMS("\n");
>+
>+	ret = mipi_dbi_poweron_reset(dbidev);
>+	if (ret)
>+		goto out_exit;
>+
>+	mipi_dbi_command(dbi, ST7586_AUTO_READ_CTRL, 0x9f);
>+	mipi_dbi_command(dbi, ST7586_OTP_RW_CTRL, 0x00);
>+
>+	msleep(10);
>+
>+	mipi_dbi_command(dbi, ST7586_OTP_READ);
>+
>+	msleep(20);
>+
>+	mipi_dbi_command(dbi, ST7586_OTP_CTRL_OUT);
>+	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF);
>+
>+	msleep(50);
>+
>+	mipi_dbi_command(dbi, ST7586_SET_VOP_OFFSET, 0x00);
>+	mipi_dbi_command(dbi, ST7586_SET_VOP, 0xe3, 0x00);
>+	mipi_dbi_command(dbi, ST7586_SET_BIAS_SYSTEM, 0x02);
>+	mipi_dbi_command(dbi, ST7586_SET_BOOST_LEVEL, 0x04);
>+	mipi_dbi_command(dbi, ST7586_ENABLE_ANALOG, 0x1d);
>+	mipi_dbi_command(dbi, ST7586_SET_NLINE_INV, 0x00);
>+	mipi_dbi_command(dbi, ST7586_DISP_MODE_GRAY);
>+	mipi_dbi_command(dbi, ST7586_ENABLE_DDRAM, 0x02);
>+
>+	switch (dbidev->rotation) {
>+	default:
>+		addr_mode = 0x00;
>+		break;
>+	case 90:
>+		addr_mode = ST7586_DISP_CTRL_MY;
>+		break;
>+	case 180:
>+		addr_mode = ST7586_DISP_CTRL_MX | ST7586_DISP_CTRL_MY;
>+		break;
>+	case 270:
>+		addr_mode = ST7586_DISP_CTRL_MX;
>+		break;
>+	}
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
>+
>+	mipi_dbi_command(dbi, ST7586_SET_DISP_DUTY, 0x7f);
>+	mipi_dbi_command(dbi, ST7586_SET_PART_DISP, 0xa0);
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_PARTIAL_AREA, 0x00, 0x00, 0x00, 0x77);
>+	mipi_dbi_command(dbi, MIPI_DCS_EXIT_INVERT_MODE);
>+
>+	msleep(100);
>+
>+	dbidev->enabled = true;
>+	st7586_fb_dirty(fb, &rect);
>+
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
>+out_exit:
>+	drm_dev_exit(idx);
>+}
>+
>+static void st7586_pipe_disable(struct drm_simple_display_pipe *pipe)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
>+
>+	/*
>+	 * This callback is not protected by drm_dev_enter/exit since we want to
>+	 * turn off the display on regular driver unload. It's highly unlikely
>+	 * that the underlying SPI controller is gone should this be called after
>+	 * unplug.
>+	 */
>+
>+	DRM_DEBUG_KMS("\n");
>+
>+	if (!dbidev->enabled)
>+		return;
>+
>+	mipi_dbi_command(&dbidev->dbi, MIPI_DCS_SET_DISPLAY_OFF);
>+	dbidev->enabled = false;
>+}
>+
>+static const u32 st7586_formats[] = {
>+	DRM_FORMAT_XRGB8888,
>+};
>+
>+static const struct drm_simple_display_pipe_funcs st7586_pipe_funcs = {
>+	.enable		= st7586_pipe_enable,
>+	.disable	= st7586_pipe_disable,
>+	.update		= st7586_pipe_update,
>+	.prepare_fb	= drm_gem_fb_simple_display_pipe_prepare_fb,
>+};
>+
>+static const struct drm_display_mode st7586_mode = {
>+	DRM_SIMPLE_MODE(178, 128, 37, 27),
>+};
>+
>+DEFINE_DRM_GEM_CMA_FOPS(st7586_fops);
>+
>+static struct drm_driver st7586_driver = {
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
>+	.fops			= &st7586_fops,
>+	.release		= mipi_dbi_release,
>+	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>+	.debugfs_init		= mipi_dbi_debugfs_init,
>+	.name			= "st7586",
>+	.desc			= "Sitronix ST7586",
>+	.date			= "20170801",
>+	.major			= 1,
>+	.minor			= 0,
>+};
>+
>+static const struct of_device_id st7586_of_match[] = {
>+	{ .compatible = "lego,ev3-lcd" },
>+	{},
>+};
>+MODULE_DEVICE_TABLE(of, st7586_of_match);
>+
>+static const struct spi_device_id st7586_id[] = {
>+	{ "ev3-lcd", 0 },
>+	{ },
>+};
>+MODULE_DEVICE_TABLE(spi, st7586_id);
>+
>+static int st7586_probe(struct spi_device *spi)
>+{
>+	struct device *dev = &spi->dev;
>+	struct mipi_dbi_dev *dbidev;
>+	struct drm_device *drm;
>+	struct mipi_dbi *dbi;
>+	struct gpio_desc *a0;
>+	u32 rotation = 0;
>+	size_t bufsize;
>+	int ret;
>+
>+	dbidev = kzalloc(sizeof(*dbidev), GFP_KERNEL);
>+	if (!dbidev)
>+		return -ENOMEM;
>+
>+	dbi = &dbidev->dbi;
>+	drm = &dbidev->drm;
>+	ret = devm_drm_dev_init(dev, drm, &st7586_driver);
>+	if (ret) {
>+		kfree(dbidev);
>+		return ret;
>+	}
>+
>+	drm_mode_config_init(drm);
>+
>+	bufsize = (st7586_mode.vdisplay + 2) / 3 * st7586_mode.hdisplay;
>+
>+	dbi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
>+	if (IS_ERR(dbi->reset)) {
>+		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
>+		return PTR_ERR(dbi->reset);
>+	}
>+
>+	a0 = devm_gpiod_get(dev, "a0", GPIOD_OUT_LOW);
>+	if (IS_ERR(a0)) {
>+		DRM_DEV_ERROR(dev, "Failed to get gpio 'a0'\n");
>+		return PTR_ERR(a0);
>+	}
>+
>+	device_property_read_u32(dev, "rotation", &rotation);
>+
>+	ret = mipi_dbi_spi_init(spi, dbi, a0);
>+	if (ret)
>+		return ret;
>+
>+	/* Cannot read from this controller via SPI */
>+	dbi->read_commands = NULL;
>+
>+	ret = mipi_dbi_dev_init_with_formats(dbidev, &st7586_pipe_funcs,
>+					     st7586_formats, ARRAY_SIZE(st7586_formats),
>+					     &st7586_mode, rotation, bufsize);
>+	if (ret)
>+		return ret;
>+
>+	/*
>+	 * we are using 8-bit data, so we are not actually swapping anything,
>+	 * but setting mipi->swap_bytes makes mipi_dbi_typec3_command() do the
>+	 * right thing and not use 16-bit transfers (which results in swapped
>+	 * bytes on little-endian systems and causes out of order data to be
>+	 * sent to the display).
>+	 */
>+	dbi->swap_bytes = true;
>+
>+	drm_mode_config_reset(drm);
>+
>+	ret = drm_dev_register(drm, 0);
>+	if (ret)
>+		return ret;
>+
>+	spi_set_drvdata(spi, drm);
>+
>+	drm_fbdev_generic_setup(drm, 0);
>+
>+	return 0;
>+}
>+
>+static int st7586_remove(struct spi_device *spi)
>+{
>+	struct drm_device *drm = spi_get_drvdata(spi);
>+
>+	drm_dev_unplug(drm);
>+	drm_atomic_helper_shutdown(drm);
>+
>+	return 0;
>+}
>+
>+static void st7586_shutdown(struct spi_device *spi)
>+{
>+	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>+}
>+
>+static struct spi_driver st7586_spi_driver = {
>+	.driver = {
>+		.name = "st7586",
>+		.owner = THIS_MODULE,
>+		.of_match_table = st7586_of_match,
>+	},
>+	.id_table = st7586_id,
>+	.probe = st7586_probe,
>+	.remove = st7586_remove,
>+	.shutdown = st7586_shutdown,
>+};
>+module_spi_driver(st7586_spi_driver);
>+
>+MODULE_DESCRIPTION("Sitronix ST7586 DRM driver");
>+MODULE_AUTHOR("David Lechner <david@lechnology.com>");
>+MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tiny/st7735r.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/st7735r.c
>--- linux-5.3-rc6/drivers/gpu/drm/tiny/st7735r.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tiny/st7735r.c	2019-08-31 15:01:12.233736201 -0500
>@@ -0,0 +1,246 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+/*
>+ * DRM driver for Sitronix ST7735R panels
>+ *
>+ * Copyright 2017 David Lechner <david@lechnology.com>
>+ */
>+
>+#include <linux/backlight.h>
>+#include <linux/delay.h>
>+#include <linux/dma-buf.h>
>+#include <linux/gpio/consumer.h>
>+#include <linux/module.h>
>+#include <linux/property.h>
>+#include <linux/spi/spi.h>
>+#include <video/mipi_display.h>
>+
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_fb_helper.h>
>+#include <drm/drm_gem_cma_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_mipi_dbi.h>
>+
>+#define ST7735R_FRMCTR1		0xb1
>+#define ST7735R_FRMCTR2		0xb2
>+#define ST7735R_FRMCTR3		0xb3
>+#define ST7735R_INVCTR		0xb4
>+#define ST7735R_PWCTR1		0xc0
>+#define ST7735R_PWCTR2		0xc1
>+#define ST7735R_PWCTR3		0xc2
>+#define ST7735R_PWCTR4		0xc3
>+#define ST7735R_PWCTR5		0xc4
>+#define ST7735R_VMCTR1		0xc5
>+#define ST7735R_GAMCTRP1	0xe0
>+#define ST7735R_GAMCTRN1	0xe1
>+
>+#define ST7735R_MY	BIT(7)
>+#define ST7735R_MX	BIT(6)
>+#define ST7735R_MV	BIT(5)
>+
>+static void jd_t18003_t01_pipe_enable(struct drm_simple_display_pipe *pipe,
>+				      struct drm_crtc_state *crtc_state,
>+				      struct drm_plane_state *plane_state)
>+{
>+	struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
>+	struct mipi_dbi *dbi = &dbidev->dbi;
>+	int ret, idx;
>+	u8 addr_mode;
>+
>+	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>+		return;
>+
>+	DRM_DEBUG_KMS("\n");
>+
>+	ret = mipi_dbi_poweron_reset(dbidev);
>+	if (ret)
>+		goto out_exit;
>+
>+	msleep(150);
>+
>+	mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
>+	msleep(500);
>+
>+	mipi_dbi_command(dbi, ST7735R_FRMCTR1, 0x01, 0x2c, 0x2d);
>+	mipi_dbi_command(dbi, ST7735R_FRMCTR2, 0x01, 0x2c, 0x2d);
>+	mipi_dbi_command(dbi, ST7735R_FRMCTR3, 0x01, 0x2c, 0x2d, 0x01, 0x2c,
>+			 0x2d);
>+	mipi_dbi_command(dbi, ST7735R_INVCTR, 0x07);
>+	mipi_dbi_command(dbi, ST7735R_PWCTR1, 0xa2, 0x02, 0x84);
>+	mipi_dbi_command(dbi, ST7735R_PWCTR2, 0xc5);
>+	mipi_dbi_command(dbi, ST7735R_PWCTR3, 0x0a, 0x00);
>+	mipi_dbi_command(dbi, ST7735R_PWCTR4, 0x8a, 0x2a);
>+	mipi_dbi_command(dbi, ST7735R_PWCTR5, 0x8a, 0xee);
>+	mipi_dbi_command(dbi, ST7735R_VMCTR1, 0x0e);
>+	mipi_dbi_command(dbi, MIPI_DCS_EXIT_INVERT_MODE);
>+	switch (dbidev->rotation) {
>+	default:
>+		addr_mode = ST7735R_MX | ST7735R_MY;
>+		break;
>+	case 90:
>+		addr_mode = ST7735R_MX | ST7735R_MV;
>+		break;
>+	case 180:
>+		addr_mode = 0;
>+		break;
>+	case 270:
>+		addr_mode = ST7735R_MY | ST7735R_MV;
>+		break;
>+	}
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT,
>+			 MIPI_DCS_PIXEL_FMT_16BIT);
>+	mipi_dbi_command(dbi, ST7735R_GAMCTRP1, 0x02, 0x1c, 0x07, 0x12, 0x37,
>+			 0x32, 0x29, 0x2d, 0x29, 0x25, 0x2b, 0x39, 0x00, 0x01,
>+			 0x03, 0x10);
>+	mipi_dbi_command(dbi, ST7735R_GAMCTRN1, 0x03, 0x1d, 0x07, 0x06, 0x2e,
>+			 0x2c, 0x29, 0x2d, 0x2e, 0x2e, 0x37, 0x3f, 0x00, 0x00,
>+			 0x02, 0x10);
>+	mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
>+
>+	msleep(100);
>+
>+	mipi_dbi_command(dbi, MIPI_DCS_ENTER_NORMAL_MODE);
>+
>+	msleep(20);
>+
>+	mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
>+out_exit:
>+	drm_dev_exit(idx);
>+}
>+
>+static const struct drm_simple_display_pipe_funcs jd_t18003_t01_pipe_funcs = {
>+	.enable		= jd_t18003_t01_pipe_enable,
>+	.disable	= mipi_dbi_pipe_disable,
>+	.update		= mipi_dbi_pipe_update,
>+	.prepare_fb	= drm_gem_fb_simple_display_pipe_prepare_fb,
>+};
>+
>+static const struct drm_display_mode jd_t18003_t01_mode = {
>+	DRM_SIMPLE_MODE(128, 160, 28, 35),
>+};
>+
>+DEFINE_DRM_GEM_CMA_FOPS(st7735r_fops);
>+
>+static struct drm_driver st7735r_driver = {
>+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
>+	.fops			= &st7735r_fops,
>+	.release		= mipi_dbi_release,
>+	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>+	.debugfs_init		= mipi_dbi_debugfs_init,
>+	.name			= "st7735r",
>+	.desc			= "Sitronix ST7735R",
>+	.date			= "20171128",
>+	.major			= 1,
>+	.minor			= 0,
>+};
>+
>+static const struct of_device_id st7735r_of_match[] = {
>+	{ .compatible = "jianda,jd-t18003-t01" },
>+	{ },
>+};
>+MODULE_DEVICE_TABLE(of, st7735r_of_match);
>+
>+static const struct spi_device_id st7735r_id[] = {
>+	{ "jd-t18003-t01", 0 },
>+	{ },
>+};
>+MODULE_DEVICE_TABLE(spi, st7735r_id);
>+
>+static int st7735r_probe(struct spi_device *spi)
>+{
>+	struct device *dev = &spi->dev;
>+	struct mipi_dbi_dev *dbidev;
>+	struct drm_device *drm;
>+	struct mipi_dbi *dbi;
>+	struct gpio_desc *dc;
>+	u32 rotation = 0;
>+	int ret;
>+
>+	dbidev = kzalloc(sizeof(*dbidev), GFP_KERNEL);
>+	if (!dbidev)
>+		return -ENOMEM;
>+
>+	dbi = &dbidev->dbi;
>+	drm = &dbidev->drm;
>+	ret = devm_drm_dev_init(dev, drm, &st7735r_driver);
>+	if (ret) {
>+		kfree(dbidev);
>+		return ret;
>+	}
>+
>+	drm_mode_config_init(drm);
>+
>+	dbi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
>+	if (IS_ERR(dbi->reset)) {
>+		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
>+		return PTR_ERR(dbi->reset);
>+	}
>+
>+	dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
>+	if (IS_ERR(dc)) {
>+		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
>+		return PTR_ERR(dc);
>+	}
>+
>+	dbidev->backlight = devm_of_find_backlight(dev);
>+	if (IS_ERR(dbidev->backlight))
>+		return PTR_ERR(dbidev->backlight);
>+
>+	device_property_read_u32(dev, "rotation", &rotation);
>+
>+	ret = mipi_dbi_spi_init(spi, dbi, dc);
>+	if (ret)
>+		return ret;
>+
>+	/* Cannot read from Adafruit 1.8" display via SPI */
>+	dbi->read_commands = NULL;
>+
>+	ret = mipi_dbi_dev_init(dbidev, &jd_t18003_t01_pipe_funcs, &jd_t18003_t01_mode, rotation);
>+	if (ret)
>+		return ret;
>+
>+	drm_mode_config_reset(drm);
>+
>+	ret = drm_dev_register(drm, 0);
>+	if (ret)
>+		return ret;
>+
>+	spi_set_drvdata(spi, drm);
>+
>+	drm_fbdev_generic_setup(drm, 0);
>+
>+	return 0;
>+}
>+
>+static int st7735r_remove(struct spi_device *spi)
>+{
>+	struct drm_device *drm = spi_get_drvdata(spi);
>+
>+	drm_dev_unplug(drm);
>+	drm_atomic_helper_shutdown(drm);
>+
>+	return 0;
>+}
>+
>+static void st7735r_shutdown(struct spi_device *spi)
>+{
>+	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>+}
>+
>+static struct spi_driver st7735r_spi_driver = {
>+	.driver = {
>+		.name = "st7735r",
>+		.owner = THIS_MODULE,
>+		.of_match_table = st7735r_of_match,
>+	},
>+	.id_table = st7735r_id,
>+	.probe = st7735r_probe,
>+	.remove = st7735r_remove,
>+	.shutdown = st7735r_shutdown,
>+};
>+module_spi_driver(st7735r_spi_driver);
>+
>+MODULE_DESCRIPTION("Sitronix ST7735R DRM driver");
>+MODULE_AUTHOR("David Lechner <david@lechnology.com>");
>+MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/core/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/core/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/core/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/core/Makefile	1969-12-31 18:00:00.000000000 -0600
>@@ -1,4 +0,0 @@
>-# SPDX-License-Identifier: GPL-2.0-only
>-tinydrm-y := tinydrm-pipe.o tinydrm-helpers.o
>-
>-obj-$(CONFIG_DRM_TINYDRM) += tinydrm.o
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/core/tinydrm-helpers.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,207 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0-or-later
>-/*
>- * Copyright (C) 2016 Noralf TrÃ¸nnes
>- */
>-
>-#include <linux/backlight.h>
>-#include <linux/dma-buf.h>
>-#include <linux/module.h>
>-#include <linux/pm.h>
>-#include <linux/spi/spi.h>
>-#include <linux/swab.h>
>-
>-#include <drm/drm_device.h>
>-#include <drm/drm_drv.h>
>-#include <drm/drm_fourcc.h>
>-#include <drm/drm_framebuffer.h>
>-#include <drm/drm_print.h>
>-#include <drm/drm_rect.h>
>-#include <drm/tinydrm/tinydrm-helpers.h>
>-
>-static unsigned int spi_max;
>-module_param(spi_max, uint, 0400);
>-MODULE_PARM_DESC(spi_max, "Set a lower SPI max transfer size");
>-
>-#if IS_ENABLED(CONFIG_SPI)
>-
>-/**
>- * tinydrm_spi_max_transfer_size - Determine max SPI transfer size
>- * @spi: SPI device
>- * @max_len: Maximum buffer size needed (optional)
>- *
>- * This function returns the maximum size to use for SPI transfers. It checks
>- * the SPI master, the optional @max_len and the module parameter spi_max and
>- * returns the smallest.
>- *
>- * Returns:
>- * Maximum size for SPI transfers
>- */
>-size_t tinydrm_spi_max_transfer_size(struct spi_device *spi, size_t max_len)
>-{
>-	size_t ret;
>-
>-	ret = min(spi_max_transfer_size(spi), spi->master->max_dma_len);
>-	if (max_len)
>-		ret = min(ret, max_len);
>-	if (spi_max)
>-		ret = min_t(size_t, ret, spi_max);
>-	ret &= ~0x3;
>-	if (ret < 4)
>-		ret = 4;
>-
>-	return ret;
>-}
>-EXPORT_SYMBOL(tinydrm_spi_max_transfer_size);
>-
>-/**
>- * tinydrm_spi_bpw_supported - Check if bits per word is supported
>- * @spi: SPI device
>- * @bpw: Bits per word
>- *
>- * This function checks to see if the SPI master driver supports @bpw.
>- *
>- * Returns:
>- * True if @bpw is supported, false otherwise.
>- */
>-bool tinydrm_spi_bpw_supported(struct spi_device *spi, u8 bpw)
>-{
>-	u32 bpw_mask = spi->master->bits_per_word_mask;
>-
>-	if (bpw == 8)
>-		return true;
>-
>-	if (!bpw_mask) {
>-		dev_warn_once(&spi->dev,
>-			      "bits_per_word_mask not set, assume 8-bit only\n");
>-		return false;
>-	}
>-
>-	if (bpw_mask & SPI_BPW_MASK(bpw))
>-		return true;
>-
>-	return false;
>-}
>-EXPORT_SYMBOL(tinydrm_spi_bpw_supported);
>-
>-static void
>-tinydrm_dbg_spi_print(struct spi_device *spi, struct spi_transfer *tr,
>-		      const void *buf, int idx, bool tx)
>-{
>-	u32 speed_hz = tr->speed_hz ? tr->speed_hz : spi->max_speed_hz;
>-	char linebuf[3 * 32];
>-
>-	hex_dump_to_buffer(buf, tr->len, 16,
>-			   DIV_ROUND_UP(tr->bits_per_word, 8),
>-			   linebuf, sizeof(linebuf), false);
>-
>-	printk(KERN_DEBUG
>-	       "    tr(%i): speed=%u%s, bpw=%i, len=%u, %s_buf=[%s%s]\n", idx,
>-	       speed_hz > 1000000 ? speed_hz / 1000000 : speed_hz / 1000,
>-	       speed_hz > 1000000 ? "MHz" : "kHz", tr->bits_per_word, tr->len,
>-	       tx ? "tx" : "rx", linebuf, tr->len > 16 ? " ..." : "");
>-}
>-
>-/* called through tinydrm_dbg_spi_message() */
>-void _tinydrm_dbg_spi_message(struct spi_device *spi, struct spi_message *m)
>-{
>-	struct spi_transfer *tmp;
>-	int i = 0;
>-
>-	list_for_each_entry(tmp, &m->transfers, transfer_list) {
>-
>-		if (tmp->tx_buf)
>-			tinydrm_dbg_spi_print(spi, tmp, tmp->tx_buf, i, true);
>-		if (tmp->rx_buf)
>-			tinydrm_dbg_spi_print(spi, tmp, tmp->rx_buf, i, false);
>-		i++;
>-	}
>-}
>-EXPORT_SYMBOL(_tinydrm_dbg_spi_message);
>-
>-/**
>- * tinydrm_spi_transfer - SPI transfer helper
>- * @spi: SPI device
>- * @speed_hz: Override speed (optional)
>- * @header: Optional header transfer
>- * @bpw: Bits per word
>- * @buf: Buffer to transfer
>- * @len: Buffer length
>- *
>- * This SPI transfer helper breaks up the transfer of @buf into chunks which
>- * the SPI master driver can handle. If the machine is Little Endian and the
>- * SPI master driver doesn't support 16 bits per word, it swaps the bytes and
>- * does a 8-bit transfer.
>- * If @header is set, it is prepended to each SPI message.
>- *
>- * Returns:
>- * Zero on success, negative error code on failure.
>- */
>-int tinydrm_spi_transfer(struct spi_device *spi, u32 speed_hz,
>-			 struct spi_transfer *header, u8 bpw, const void *buf,
>-			 size_t len)
>-{
>-	struct spi_transfer tr = {
>-		.bits_per_word = bpw,
>-		.speed_hz = speed_hz,
>-	};
>-	struct spi_message m;
>-	u16 *swap_buf = NULL;
>-	size_t max_chunk;
>-	size_t chunk;
>-	int ret = 0;
>-
>-	if (WARN_ON_ONCE(bpw != 8 && bpw != 16))
>-		return -EINVAL;
>-
>-	max_chunk = tinydrm_spi_max_transfer_size(spi, 0);
>-
>-	if (drm_debug & DRM_UT_DRIVER)
>-		pr_debug("[drm:%s] bpw=%u, max_chunk=%zu, transfers:\n",
>-			 __func__, bpw, max_chunk);
>-
>-	if (bpw == 16 && !tinydrm_spi_bpw_supported(spi, 16)) {
>-		tr.bits_per_word = 8;
>-		if (tinydrm_machine_little_endian()) {
>-			swap_buf = kmalloc(min(len, max_chunk), GFP_KERNEL);
>-			if (!swap_buf)
>-				return -ENOMEM;
>-		}
>-	}
>-
>-	spi_message_init(&m);
>-	if (header)
>-		spi_message_add_tail(header, &m);
>-	spi_message_add_tail(&tr, &m);
>-
>-	while (len) {
>-		chunk = min(len, max_chunk);
>-
>-		tr.tx_buf = buf;
>-		tr.len = chunk;
>-
>-		if (swap_buf) {
>-			const u16 *buf16 = buf;
>-			unsigned int i;
>-
>-			for (i = 0; i < chunk / 2; i++)
>-				swap_buf[i] = swab16(buf16[i]);
>-
>-			tr.tx_buf = swap_buf;
>-		}
>-
>-		buf += chunk;
>-		len -= chunk;
>-
>-		tinydrm_dbg_spi_message(spi, &m);
>-		ret = spi_sync(spi, &m);
>-		if (ret)
>-			return ret;
>-	}
>-
>-	return 0;
>-}
>-EXPORT_SYMBOL(tinydrm_spi_transfer);
>-
>-#endif /* CONFIG_SPI */
>-
>-MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/core/tinydrm-pipe.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,179 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0-or-later
>-/*
>- * Copyright (C) 2016 Noralf TrÃ¸nnes
>- */
>-
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_drv.h>
>-#include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_modes.h>
>-#include <drm/drm_probe_helper.h>
>-#include <drm/drm_print.h>
>-#include <drm/drm_simple_kms_helper.h>
>-
>-struct tinydrm_connector {
>-	struct drm_connector base;
>-	struct drm_display_mode mode;
>-};
>-
>-static inline struct tinydrm_connector *
>-to_tinydrm_connector(struct drm_connector *connector)
>-{
>-	return container_of(connector, struct tinydrm_connector, base);
>-}
>-
>-static int tinydrm_connector_get_modes(struct drm_connector *connector)
>-{
>-	struct tinydrm_connector *tconn = to_tinydrm_connector(connector);
>-	struct drm_display_mode *mode;
>-
>-	mode = drm_mode_duplicate(connector->dev, &tconn->mode);
>-	if (!mode) {
>-		DRM_ERROR("Failed to duplicate mode\n");
>-		return 0;
>-	}
>-
>-	if (mode->name[0] == '\0')
>-		drm_mode_set_name(mode);
>-
>-	mode->type |= DRM_MODE_TYPE_PREFERRED;
>-	drm_mode_probed_add(connector, mode);
>-
>-	if (mode->width_mm) {
>-		connector->display_info.width_mm = mode->width_mm;
>-		connector->display_info.height_mm = mode->height_mm;
>-	}
>-
>-	return 1;
>-}
>-
>-static const struct drm_connector_helper_funcs tinydrm_connector_hfuncs = {
>-	.get_modes = tinydrm_connector_get_modes,
>-};
>-
>-static enum drm_connector_status
>-tinydrm_connector_detect(struct drm_connector *connector, bool force)
>-{
>-	if (drm_dev_is_unplugged(connector->dev))
>-		return connector_status_disconnected;
>-
>-	return connector->status;
>-}
>-
>-static void tinydrm_connector_destroy(struct drm_connector *connector)
>-{
>-	struct tinydrm_connector *tconn = to_tinydrm_connector(connector);
>-
>-	drm_connector_cleanup(connector);
>-	kfree(tconn);
>-}
>-
>-static const struct drm_connector_funcs tinydrm_connector_funcs = {
>-	.reset = drm_atomic_helper_connector_reset,
>-	.detect = tinydrm_connector_detect,
>-	.fill_modes = drm_helper_probe_single_connector_modes,
>-	.destroy = tinydrm_connector_destroy,
>-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
>-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
>-};
>-
>-struct drm_connector *
>-tinydrm_connector_create(struct drm_device *drm,
>-			 const struct drm_display_mode *mode,
>-			 int connector_type)
>-{
>-	struct tinydrm_connector *tconn;
>-	struct drm_connector *connector;
>-	int ret;
>-
>-	tconn = kzalloc(sizeof(*tconn), GFP_KERNEL);
>-	if (!tconn)
>-		return ERR_PTR(-ENOMEM);
>-
>-	drm_mode_copy(&tconn->mode, mode);
>-	connector = &tconn->base;
>-
>-	drm_connector_helper_add(connector, &tinydrm_connector_hfuncs);
>-	ret = drm_connector_init(drm, connector, &tinydrm_connector_funcs,
>-				 connector_type);
>-	if (ret) {
>-		kfree(tconn);
>-		return ERR_PTR(ret);
>-	}
>-
>-	connector->status = connector_status_connected;
>-
>-	return connector;
>-}
>-
>-static int tinydrm_rotate_mode(struct drm_display_mode *mode,
>-			       unsigned int rotation)
>-{
>-	if (rotation == 0 || rotation == 180) {
>-		return 0;
>-	} else if (rotation == 90 || rotation == 270) {
>-		swap(mode->hdisplay, mode->vdisplay);
>-		swap(mode->hsync_start, mode->vsync_start);
>-		swap(mode->hsync_end, mode->vsync_end);
>-		swap(mode->htotal, mode->vtotal);
>-		swap(mode->width_mm, mode->height_mm);
>-		return 0;
>-	} else {
>-		return -EINVAL;
>-	}
>-}
>-
>-/**
>- * tinydrm_display_pipe_init - Initialize display pipe
>- * @drm: DRM device
>- * @pipe: Display pipe
>- * @funcs: Display pipe functions
>- * @connector_type: Connector type
>- * @formats: Array of supported formats (DRM_FORMAT\_\*)
>- * @format_count: Number of elements in @formats
>- * @mode: Supported mode
>- * @rotation: Initial @mode rotation in degrees Counter Clock Wise
>- *
>- * This function sets up a &drm_simple_display_pipe with a &drm_connector that
>- * has one fixed &drm_display_mode which is rotated according to @rotation.
>- *
>- * Returns:
>- * Zero on success, negative error code on failure.
>- */
>-int tinydrm_display_pipe_init(struct drm_device *drm,
>-			      struct drm_simple_display_pipe *pipe,
>-			      const struct drm_simple_display_pipe_funcs *funcs,
>-			      int connector_type,
>-			      const uint32_t *formats,
>-			      unsigned int format_count,
>-			      const struct drm_display_mode *mode,
>-			      unsigned int rotation)
>-{
>-	struct drm_display_mode mode_copy;
>-	struct drm_connector *connector;
>-	int ret;
>-	static const uint64_t modifiers[] = {
>-		DRM_FORMAT_MOD_LINEAR,
>-		DRM_FORMAT_MOD_INVALID
>-	};
>-
>-	drm_mode_copy(&mode_copy, mode);
>-	ret = tinydrm_rotate_mode(&mode_copy, rotation);
>-	if (ret) {
>-		DRM_ERROR("Illegal rotation value %u\n", rotation);
>-		return -EINVAL;
>-	}
>-
>-	drm->mode_config.min_width = mode_copy.hdisplay;
>-	drm->mode_config.max_width = mode_copy.hdisplay;
>-	drm->mode_config.min_height = mode_copy.vdisplay;
>-	drm->mode_config.max_height = mode_copy.vdisplay;
>-
>-	connector = tinydrm_connector_create(drm, &mode_copy, connector_type);
>-	if (IS_ERR(connector))
>-		return PTR_ERR(connector);
>-
>-	return drm_simple_display_pipe_init(drm, pipe, funcs, formats,
>-					    format_count, modifiers, connector);
>-}
>-EXPORT_SYMBOL(tinydrm_display_pipe_init);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/hx8357d.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/hx8357d.c
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/hx8357d.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/hx8357d.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,304 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0+
>-/*
>- * DRM driver for the HX8357D LCD controller
>- *
>- * Copyright 2018 Broadcom
>- * Copyright 2018 David Lechner <david@lechnology.com>
>- * Copyright 2016 Noralf TrÃ¸nnes
>- * Copyright (C) 2015 Adafruit Industries
>- * Copyright (C) 2013 Christian Vogelgsang
>- */
>-
>-#include <linux/backlight.h>
>-#include <linux/delay.h>
>-#include <linux/gpio/consumer.h>
>-#include <linux/module.h>
>-#include <linux/property.h>
>-#include <linux/spi/spi.h>
>-
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_drv.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_gem_cma_helper.h>
>-#include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_modeset_helper.h>
>-#include <drm/tinydrm/mipi-dbi.h>
>-#include <drm/tinydrm/tinydrm-helpers.h>
>-#include <video/mipi_display.h>
>-
>-#define HX8357D_SETOSC 0xb0
>-#define HX8357D_SETPOWER 0xb1
>-#define HX8357D_SETRGB 0xb3
>-#define HX8357D_SETCYC 0xb3
>-#define HX8357D_SETCOM 0xb6
>-#define HX8357D_SETEXTC 0xb9
>-#define HX8357D_SETSTBA 0xc0
>-#define HX8357D_SETPANEL 0xcc
>-#define HX8357D_SETGAMMA 0xe0
>-
>-#define HX8357D_MADCTL_MY  0x80
>-#define HX8357D_MADCTL_MX  0x40
>-#define HX8357D_MADCTL_MV  0x20
>-#define HX8357D_MADCTL_ML  0x10
>-#define HX8357D_MADCTL_RGB 0x00
>-#define HX8357D_MADCTL_BGR 0x08
>-#define HX8357D_MADCTL_MH  0x04
>-
>-static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
>-			     struct drm_crtc_state *crtc_state,
>-			     struct drm_plane_state *plane_state)
>-{
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(pipe->crtc.dev);
>-	u8 addr_mode;
>-	int ret, idx;
>-
>-	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>-		return;
>-
>-	DRM_DEBUG_KMS("\n");
>-
>-	ret = mipi_dbi_poweron_conditional_reset(mipi);
>-	if (ret < 0)
>-		goto out_exit;
>-	if (ret == 1)
>-		goto out_enable;
>-
>-	/* setextc */
>-	mipi_dbi_command(mipi, HX8357D_SETEXTC, 0xFF, 0x83, 0x57);
>-	msleep(150);
>-
>-	/* setRGB which also enables SDO */
>-	mipi_dbi_command(mipi, HX8357D_SETRGB, 0x00, 0x00, 0x06, 0x06);
>-
>-	/* -1.52V */
>-	mipi_dbi_command(mipi, HX8357D_SETCOM, 0x25);
>-
>-	/* Normal mode 70Hz, Idle mode 55 Hz */
>-	mipi_dbi_command(mipi, HX8357D_SETOSC, 0x68);
>-
>-	/* Set Panel - BGR, Gate direction swapped */
>-	mipi_dbi_command(mipi, HX8357D_SETPANEL, 0x05);
>-
>-	mipi_dbi_command(mipi, HX8357D_SETPOWER,
>-			 0x00,  /* Not deep standby */
>-			 0x15,  /* BT */
>-			 0x1C,  /* VSPR */
>-			 0x1C,  /* VSNR */
>-			 0x83,  /* AP */
>-			 0xAA);  /* FS */
>-
>-	mipi_dbi_command(mipi, HX8357D_SETSTBA,
>-			 0x50,  /* OPON normal */
>-			 0x50,  /* OPON idle */
>-			 0x01,  /* STBA */
>-			 0x3C,  /* STBA */
>-			 0x1E,  /* STBA */
>-			 0x08);  /* GEN */
>-
>-	mipi_dbi_command(mipi, HX8357D_SETCYC,
>-			 0x02,  /* NW 0x02 */
>-			 0x40,  /* RTN */
>-			 0x00,  /* DIV */
>-			 0x2A,  /* DUM */
>-			 0x2A,  /* DUM */
>-			 0x0D,  /* GDON */
>-			 0x78);  /* GDOFF */
>-
>-	mipi_dbi_command(mipi, HX8357D_SETGAMMA,
>-			 0x02,
>-			 0x0A,
>-			 0x11,
>-			 0x1d,
>-			 0x23,
>-			 0x35,
>-			 0x41,
>-			 0x4b,
>-			 0x4b,
>-			 0x42,
>-			 0x3A,
>-			 0x27,
>-			 0x1B,
>-			 0x08,
>-			 0x09,
>-			 0x03,
>-			 0x02,
>-			 0x0A,
>-			 0x11,
>-			 0x1d,
>-			 0x23,
>-			 0x35,
>-			 0x41,
>-			 0x4b,
>-			 0x4b,
>-			 0x42,
>-			 0x3A,
>-			 0x27,
>-			 0x1B,
>-			 0x08,
>-			 0x09,
>-			 0x03,
>-			 0x00,
>-			 0x01);
>-
>-	/* 16 bit */
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_PIXEL_FORMAT,
>-			 MIPI_DCS_PIXEL_FMT_16BIT);
>-
>-	/* TE off */
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_TEAR_ON, 0x00);
>-
>-	/* tear line */
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_TEAR_SCANLINE, 0x00, 0x02);
>-
>-	/* Exit Sleep */
>-	mipi_dbi_command(mipi, MIPI_DCS_EXIT_SLEEP_MODE);
>-	msleep(150);
>-
>-	/* display on */
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_ON);
>-	usleep_range(5000, 7000);
>-
>-out_enable:
>-	switch (mipi->rotation) {
>-	default:
>-		addr_mode = HX8357D_MADCTL_MX | HX8357D_MADCTL_MY;
>-		break;
>-	case 90:
>-		addr_mode = HX8357D_MADCTL_MV | HX8357D_MADCTL_MY;
>-		break;
>-	case 180:
>-		addr_mode = 0;
>-		break;
>-	case 270:
>-		addr_mode = HX8357D_MADCTL_MV | HX8357D_MADCTL_MX;
>-		break;
>-	}
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
>-	mipi_dbi_enable_flush(mipi, crtc_state, plane_state);
>-out_exit:
>-	drm_dev_exit(idx);
>-}
>-
>-static const struct drm_simple_display_pipe_funcs hx8357d_pipe_funcs = {
>-	.enable = yx240qv29_enable,
>-	.disable = mipi_dbi_pipe_disable,
>-	.update = mipi_dbi_pipe_update,
>-	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
>-};
>-
>-static const struct drm_display_mode yx350hv15_mode = {
>-	DRM_SIMPLE_MODE(320, 480, 60, 75),
>-};
>-
>-DEFINE_DRM_GEM_CMA_FOPS(hx8357d_fops);
>-
>-static struct drm_driver hx8357d_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_ATOMIC,
>-	.fops			= &hx8357d_fops,
>-	.release		= mipi_dbi_release,
>-	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>-	.debugfs_init		= mipi_dbi_debugfs_init,
>-	.name			= "hx8357d",
>-	.desc			= "HX8357D",
>-	.date			= "20181023",
>-	.major			= 1,
>-	.minor			= 0,
>-};
>-
>-static const struct of_device_id hx8357d_of_match[] = {
>-	{ .compatible = "adafruit,yx350hv15" },
>-	{ }
>-};
>-MODULE_DEVICE_TABLE(of, hx8357d_of_match);
>-
>-static const struct spi_device_id hx8357d_id[] = {
>-	{ "yx350hv15", 0 },
>-	{ }
>-};
>-MODULE_DEVICE_TABLE(spi, hx8357d_id);
>-
>-static int hx8357d_probe(struct spi_device *spi)
>-{
>-	struct device *dev = &spi->dev;
>-	struct drm_device *drm;
>-	struct mipi_dbi *mipi;
>-	struct gpio_desc *dc;
>-	u32 rotation = 0;
>-	int ret;
>-
>-	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
>-	if (!mipi)
>-		return -ENOMEM;
>-
>-	drm = &mipi->drm;
>-	ret = devm_drm_dev_init(dev, drm, &hx8357d_driver);
>-	if (ret) {
>-		kfree(mipi);
>-		return ret;
>-	}
>-
>-	drm_mode_config_init(drm);
>-
>-	dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
>-	if (IS_ERR(dc)) {
>-		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
>-		return PTR_ERR(dc);
>-	}
>-
>-	mipi->backlight = devm_of_find_backlight(dev);
>-	if (IS_ERR(mipi->backlight))
>-		return PTR_ERR(mipi->backlight);
>-
>-	device_property_read_u32(dev, "rotation", &rotation);
>-
>-	ret = mipi_dbi_spi_init(spi, mipi, dc);
>-	if (ret)
>-		return ret;
>-
>-	ret = mipi_dbi_init(mipi, &hx8357d_pipe_funcs, &yx350hv15_mode, rotation);
>-	if (ret)
>-		return ret;
>-
>-	drm_mode_config_reset(drm);
>-
>-	ret = drm_dev_register(drm, 0);
>-	if (ret)
>-		return ret;
>-
>-	spi_set_drvdata(spi, drm);
>-
>-	drm_fbdev_generic_setup(drm, 0);
>-
>-	return 0;
>-}
>-
>-static int hx8357d_remove(struct spi_device *spi)
>-{
>-	struct drm_device *drm = spi_get_drvdata(spi);
>-
>-	drm_dev_unplug(drm);
>-	drm_atomic_helper_shutdown(drm);
>-
>-	return 0;
>-}
>-
>-static void hx8357d_shutdown(struct spi_device *spi)
>-{
>-	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>-}
>-
>-static struct spi_driver hx8357d_spi_driver = {
>-	.driver = {
>-		.name = "hx8357d",
>-		.of_match_table = hx8357d_of_match,
>-	},
>-	.id_table = hx8357d_id,
>-	.probe = hx8357d_probe,
>-	.remove = hx8357d_remove,
>-	.shutdown = hx8357d_shutdown,
>-};
>-module_spi_driver(hx8357d_spi_driver);
>-
>-MODULE_DESCRIPTION("HX8357D DRM driver");
>-MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
>-MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/ili9225.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/ili9225.c
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/ili9225.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/ili9225.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,467 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0-or-later
>-/*
>- * DRM driver for Ilitek ILI9225 panels
>- *
>- * Copyright 2017 David Lechner <david@lechnology.com>
>- *
>- * Some code copied from mipi-dbi.c
>- * Copyright 2016 Noralf TrÃ¸nnes
>- */
>-
>-#include <linux/delay.h>
>-#include <linux/dma-buf.h>
>-#include <linux/gpio/consumer.h>
>-#include <linux/module.h>
>-#include <linux/property.h>
>-#include <linux/spi/spi.h>
>-#include <video/mipi_display.h>
>-
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_damage_helper.h>
>-#include <drm/drm_drv.h>
>-#include <drm/drm_fb_cma_helper.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_fourcc.h>
>-#include <drm/drm_gem_cma_helper.h>
>-#include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_rect.h>
>-#include <drm/drm_vblank.h>
>-#include <drm/tinydrm/mipi-dbi.h>
>-#include <drm/tinydrm/tinydrm-helpers.h>
>-
>-#define ILI9225_DRIVER_READ_CODE	0x00
>-#define ILI9225_DRIVER_OUTPUT_CONTROL	0x01
>-#define ILI9225_LCD_AC_DRIVING_CONTROL	0x02
>-#define ILI9225_ENTRY_MODE		0x03
>-#define ILI9225_DISPLAY_CONTROL_1	0x07
>-#define ILI9225_BLANK_PERIOD_CONTROL_1	0x08
>-#define ILI9225_FRAME_CYCLE_CONTROL	0x0b
>-#define ILI9225_INTERFACE_CONTROL	0x0c
>-#define ILI9225_OSCILLATION_CONTROL	0x0f
>-#define ILI9225_POWER_CONTROL_1		0x10
>-#define ILI9225_POWER_CONTROL_2		0x11
>-#define ILI9225_POWER_CONTROL_3		0x12
>-#define ILI9225_POWER_CONTROL_4		0x13
>-#define ILI9225_POWER_CONTROL_5		0x14
>-#define ILI9225_VCI_RECYCLING		0x15
>-#define ILI9225_RAM_ADDRESS_SET_1	0x20
>-#define ILI9225_RAM_ADDRESS_SET_2	0x21
>-#define ILI9225_WRITE_DATA_TO_GRAM	0x22
>-#define ILI9225_SOFTWARE_RESET		0x28
>-#define ILI9225_GATE_SCAN_CONTROL	0x30
>-#define ILI9225_VERTICAL_SCROLL_1	0x31
>-#define ILI9225_VERTICAL_SCROLL_2	0x32
>-#define ILI9225_VERTICAL_SCROLL_3	0x33
>-#define ILI9225_PARTIAL_DRIVING_POS_1	0x34
>-#define ILI9225_PARTIAL_DRIVING_POS_2	0x35
>-#define ILI9225_HORIZ_WINDOW_ADDR_1	0x36
>-#define ILI9225_HORIZ_WINDOW_ADDR_2	0x37
>-#define ILI9225_VERT_WINDOW_ADDR_1	0x38
>-#define ILI9225_VERT_WINDOW_ADDR_2	0x39
>-#define ILI9225_GAMMA_CONTROL_1		0x50
>-#define ILI9225_GAMMA_CONTROL_2		0x51
>-#define ILI9225_GAMMA_CONTROL_3		0x52
>-#define ILI9225_GAMMA_CONTROL_4		0x53
>-#define ILI9225_GAMMA_CONTROL_5		0x54
>-#define ILI9225_GAMMA_CONTROL_6		0x55
>-#define ILI9225_GAMMA_CONTROL_7		0x56
>-#define ILI9225_GAMMA_CONTROL_8		0x57
>-#define ILI9225_GAMMA_CONTROL_9		0x58
>-#define ILI9225_GAMMA_CONTROL_10	0x59
>-
>-static inline int ili9225_command(struct mipi_dbi *mipi, u8 cmd, u16 data)
>-{
>-	u8 par[2] = { data >> 8, data & 0xff };
>-
>-	return mipi_dbi_command_buf(mipi, cmd, par, 2);
>-}
>-
>-static void ili9225_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
>-{
>-	struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(fb->dev);
>-	unsigned int height = rect->y2 - rect->y1;
>-	unsigned int width = rect->x2 - rect->x1;
>-	bool swap = mipi->swap_bytes;
>-	u16 x_start, y_start;
>-	u16 x1, x2, y1, y2;
>-	int idx, ret = 0;
>-	bool full;
>-	void *tr;
>-
>-	if (!mipi->enabled)
>-		return;
>-
>-	if (!drm_dev_enter(fb->dev, &idx))
>-		return;
>-
>-	full = width == fb->width && height == fb->height;
>-
>-	DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
>-
>-	if (!mipi->dc || !full || swap ||
>-	    fb->format->format == DRM_FORMAT_XRGB8888) {
>-		tr = mipi->tx_buf;
>-		ret = mipi_dbi_buf_copy(mipi->tx_buf, fb, rect, swap);
>-		if (ret)
>-			goto err_msg;
>-	} else {
>-		tr = cma_obj->vaddr;
>-	}
>-
>-	switch (mipi->rotation) {
>-	default:
>-		x1 = rect->x1;
>-		x2 = rect->x2 - 1;
>-		y1 = rect->y1;
>-		y2 = rect->y2 - 1;
>-		x_start = x1;
>-		y_start = y1;
>-		break;
>-	case 90:
>-		x1 = rect->y1;
>-		x2 = rect->y2 - 1;
>-		y1 = fb->width - rect->x2;
>-		y2 = fb->width - rect->x1 - 1;
>-		x_start = x1;
>-		y_start = y2;
>-		break;
>-	case 180:
>-		x1 = fb->width - rect->x2;
>-		x2 = fb->width - rect->x1 - 1;
>-		y1 = fb->height - rect->y2;
>-		y2 = fb->height - rect->y1 - 1;
>-		x_start = x2;
>-		y_start = y2;
>-		break;
>-	case 270:
>-		x1 = fb->height - rect->y2;
>-		x2 = fb->height - rect->y1 - 1;
>-		y1 = rect->x1;
>-		y2 = rect->x2 - 1;
>-		x_start = x2;
>-		y_start = y1;
>-		break;
>-	}
>-
>-	ili9225_command(mipi, ILI9225_HORIZ_WINDOW_ADDR_1, x2);
>-	ili9225_command(mipi, ILI9225_HORIZ_WINDOW_ADDR_2, x1);
>-	ili9225_command(mipi, ILI9225_VERT_WINDOW_ADDR_1, y2);
>-	ili9225_command(mipi, ILI9225_VERT_WINDOW_ADDR_2, y1);
>-
>-	ili9225_command(mipi, ILI9225_RAM_ADDRESS_SET_1, x_start);
>-	ili9225_command(mipi, ILI9225_RAM_ADDRESS_SET_2, y_start);
>-
>-	ret = mipi_dbi_command_buf(mipi, ILI9225_WRITE_DATA_TO_GRAM, tr,
>-				   width * height * 2);
>-err_msg:
>-	if (ret)
>-		dev_err_once(fb->dev->dev, "Failed to update display %d\n", ret);
>-
>-	drm_dev_exit(idx);
>-}
>-
>-static void ili9225_pipe_update(struct drm_simple_display_pipe *pipe,
>-				struct drm_plane_state *old_state)
>-{
>-	struct drm_plane_state *state = pipe->plane.state;
>-	struct drm_crtc *crtc = &pipe->crtc;
>-	struct drm_rect rect;
>-
>-	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
>-		ili9225_fb_dirty(state->fb, &rect);
>-
>-	if (crtc->state->event) {
>-		spin_lock_irq(&crtc->dev->event_lock);
>-		drm_crtc_send_vblank_event(crtc, crtc->state->event);
>-		spin_unlock_irq(&crtc->dev->event_lock);
>-		crtc->state->event = NULL;
>-	}
>-}
>-
>-static void ili9225_pipe_enable(struct drm_simple_display_pipe *pipe,
>-				struct drm_crtc_state *crtc_state,
>-				struct drm_plane_state *plane_state)
>-{
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(pipe->crtc.dev);
>-	struct drm_framebuffer *fb = plane_state->fb;
>-	struct device *dev = pipe->crtc.dev->dev;
>-	struct drm_rect rect = {
>-		.x1 = 0,
>-		.x2 = fb->width,
>-		.y1 = 0,
>-		.y2 = fb->height,
>-	};
>-	int ret, idx;
>-	u8 am_id;
>-
>-	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>-		return;
>-
>-	DRM_DEBUG_KMS("\n");
>-
>-	mipi_dbi_hw_reset(mipi);
>-
>-	/*
>-	 * There don't seem to be two example init sequences that match, so
>-	 * using the one from the popular Arduino library for this display.
>-	 * https://github.com/Nkawu/TFT_22_ILI9225/blob/master/src/TFT_22_ILI9225.cpp
>-	 */
>-
>-	ret = ili9225_command(mipi, ILI9225_POWER_CONTROL_1, 0x0000);
>-	if (ret) {
>-		DRM_DEV_ERROR(dev, "Error sending command %d\n", ret);
>-		goto out_exit;
>-	}
>-	ili9225_command(mipi, ILI9225_POWER_CONTROL_2, 0x0000);
>-	ili9225_command(mipi, ILI9225_POWER_CONTROL_3, 0x0000);
>-	ili9225_command(mipi, ILI9225_POWER_CONTROL_4, 0x0000);
>-	ili9225_command(mipi, ILI9225_POWER_CONTROL_5, 0x0000);
>-
>-	msleep(40);
>-
>-	ili9225_command(mipi, ILI9225_POWER_CONTROL_2, 0x0018);
>-	ili9225_command(mipi, ILI9225_POWER_CONTROL_3, 0x6121);
>-	ili9225_command(mipi, ILI9225_POWER_CONTROL_4, 0x006f);
>-	ili9225_command(mipi, ILI9225_POWER_CONTROL_5, 0x495f);
>-	ili9225_command(mipi, ILI9225_POWER_CONTROL_1, 0x0800);
>-
>-	msleep(10);
>-
>-	ili9225_command(mipi, ILI9225_POWER_CONTROL_2, 0x103b);
>-
>-	msleep(50);
>-
>-	switch (mipi->rotation) {
>-	default:
>-		am_id = 0x30;
>-		break;
>-	case 90:
>-		am_id = 0x18;
>-		break;
>-	case 180:
>-		am_id = 0x00;
>-		break;
>-	case 270:
>-		am_id = 0x28;
>-		break;
>-	}
>-	ili9225_command(mipi, ILI9225_DRIVER_OUTPUT_CONTROL, 0x011c);
>-	ili9225_command(mipi, ILI9225_LCD_AC_DRIVING_CONTROL, 0x0100);
>-	ili9225_command(mipi, ILI9225_ENTRY_MODE, 0x1000 | am_id);
>-	ili9225_command(mipi, ILI9225_DISPLAY_CONTROL_1, 0x0000);
>-	ili9225_command(mipi, ILI9225_BLANK_PERIOD_CONTROL_1, 0x0808);
>-	ili9225_command(mipi, ILI9225_FRAME_CYCLE_CONTROL, 0x1100);
>-	ili9225_command(mipi, ILI9225_INTERFACE_CONTROL, 0x0000);
>-	ili9225_command(mipi, ILI9225_OSCILLATION_CONTROL, 0x0d01);
>-	ili9225_command(mipi, ILI9225_VCI_RECYCLING, 0x0020);
>-	ili9225_command(mipi, ILI9225_RAM_ADDRESS_SET_1, 0x0000);
>-	ili9225_command(mipi, ILI9225_RAM_ADDRESS_SET_2, 0x0000);
>-
>-	ili9225_command(mipi, ILI9225_GATE_SCAN_CONTROL, 0x0000);
>-	ili9225_command(mipi, ILI9225_VERTICAL_SCROLL_1, 0x00db);
>-	ili9225_command(mipi, ILI9225_VERTICAL_SCROLL_2, 0x0000);
>-	ili9225_command(mipi, ILI9225_VERTICAL_SCROLL_3, 0x0000);
>-	ili9225_command(mipi, ILI9225_PARTIAL_DRIVING_POS_1, 0x00db);
>-	ili9225_command(mipi, ILI9225_PARTIAL_DRIVING_POS_2, 0x0000);
>-
>-	ili9225_command(mipi, ILI9225_GAMMA_CONTROL_1, 0x0000);
>-	ili9225_command(mipi, ILI9225_GAMMA_CONTROL_2, 0x0808);
>-	ili9225_command(mipi, ILI9225_GAMMA_CONTROL_3, 0x080a);
>-	ili9225_command(mipi, ILI9225_GAMMA_CONTROL_4, 0x000a);
>-	ili9225_command(mipi, ILI9225_GAMMA_CONTROL_5, 0x0a08);
>-	ili9225_command(mipi, ILI9225_GAMMA_CONTROL_6, 0x0808);
>-	ili9225_command(mipi, ILI9225_GAMMA_CONTROL_7, 0x0000);
>-	ili9225_command(mipi, ILI9225_GAMMA_CONTROL_8, 0x0a00);
>-	ili9225_command(mipi, ILI9225_GAMMA_CONTROL_9, 0x0710);
>-	ili9225_command(mipi, ILI9225_GAMMA_CONTROL_10, 0x0710);
>-
>-	ili9225_command(mipi, ILI9225_DISPLAY_CONTROL_1, 0x0012);
>-
>-	msleep(50);
>-
>-	ili9225_command(mipi, ILI9225_DISPLAY_CONTROL_1, 0x1017);
>-
>-	mipi->enabled = true;
>-	ili9225_fb_dirty(fb, &rect);
>-out_exit:
>-	drm_dev_exit(idx);
>-}
>-
>-static void ili9225_pipe_disable(struct drm_simple_display_pipe *pipe)
>-{
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(pipe->crtc.dev);
>-
>-	DRM_DEBUG_KMS("\n");
>-
>-	/*
>-	 * This callback is not protected by drm_dev_enter/exit since we want to
>-	 * turn off the display on regular driver unload. It's highly unlikely
>-	 * that the underlying SPI controller is gone should this be called after
>-	 * unplug.
>-	 */
>-
>-	if (!mipi->enabled)
>-		return;
>-
>-	ili9225_command(mipi, ILI9225_DISPLAY_CONTROL_1, 0x0000);
>-	msleep(50);
>-	ili9225_command(mipi, ILI9225_POWER_CONTROL_2, 0x0007);
>-	msleep(50);
>-	ili9225_command(mipi, ILI9225_POWER_CONTROL_1, 0x0a02);
>-
>-	mipi->enabled = false;
>-}
>-
>-static int ili9225_dbi_command(struct mipi_dbi *mipi, u8 *cmd, u8 *par,
>-			       size_t num)
>-{
>-	struct spi_device *spi = mipi->spi;
>-	unsigned int bpw = 8;
>-	u32 speed_hz;
>-	int ret;
>-
>-	gpiod_set_value_cansleep(mipi->dc, 0);
>-	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
>-	ret = tinydrm_spi_transfer(spi, speed_hz, NULL, 8, cmd, 1);
>-	if (ret || !num)
>-		return ret;
>-
>-	if (*cmd == ILI9225_WRITE_DATA_TO_GRAM && !mipi->swap_bytes)
>-		bpw = 16;
>-
>-	gpiod_set_value_cansleep(mipi->dc, 1);
>-	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
>-
>-	return tinydrm_spi_transfer(spi, speed_hz, NULL, bpw, par, num);
>-}
>-
>-static const struct drm_simple_display_pipe_funcs ili9225_pipe_funcs = {
>-	.enable		= ili9225_pipe_enable,
>-	.disable	= ili9225_pipe_disable,
>-	.update		= ili9225_pipe_update,
>-	.prepare_fb	= drm_gem_fb_simple_display_pipe_prepare_fb,
>-};
>-
>-static const struct drm_display_mode ili9225_mode = {
>-	DRM_SIMPLE_MODE(176, 220, 35, 44),
>-};
>-
>-DEFINE_DRM_GEM_CMA_FOPS(ili9225_fops);
>-
>-static struct drm_driver ili9225_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
>-				  DRIVER_ATOMIC,
>-	.fops			= &ili9225_fops,
>-	.release		= mipi_dbi_release,
>-	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>-	.name			= "ili9225",
>-	.desc			= "Ilitek ILI9225",
>-	.date			= "20171106",
>-	.major			= 1,
>-	.minor			= 0,
>-};
>-
>-static const struct of_device_id ili9225_of_match[] = {
>-	{ .compatible = "vot,v220hf01a-t" },
>-	{},
>-};
>-MODULE_DEVICE_TABLE(of, ili9225_of_match);
>-
>-static const struct spi_device_id ili9225_id[] = {
>-	{ "v220hf01a-t", 0 },
>-	{ },
>-};
>-MODULE_DEVICE_TABLE(spi, ili9225_id);
>-
>-static int ili9225_probe(struct spi_device *spi)
>-{
>-	struct device *dev = &spi->dev;
>-	struct drm_device *drm;
>-	struct mipi_dbi *mipi;
>-	struct gpio_desc *rs;
>-	u32 rotation = 0;
>-	int ret;
>-
>-	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
>-	if (!mipi)
>-		return -ENOMEM;
>-
>-	drm = &mipi->drm;
>-	ret = devm_drm_dev_init(dev, drm, &ili9225_driver);
>-	if (ret) {
>-		kfree(mipi);
>-		return ret;
>-	}
>-
>-	drm_mode_config_init(drm);
>-
>-	mipi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
>-	if (IS_ERR(mipi->reset)) {
>-		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
>-		return PTR_ERR(mipi->reset);
>-	}
>-
>-	rs = devm_gpiod_get(dev, "rs", GPIOD_OUT_LOW);
>-	if (IS_ERR(rs)) {
>-		DRM_DEV_ERROR(dev, "Failed to get gpio 'rs'\n");
>-		return PTR_ERR(rs);
>-	}
>-
>-	device_property_read_u32(dev, "rotation", &rotation);
>-
>-	ret = mipi_dbi_spi_init(spi, mipi, rs);
>-	if (ret)
>-		return ret;
>-
>-	/* override the command function set in  mipi_dbi_spi_init() */
>-	mipi->command = ili9225_dbi_command;
>-
>-	ret = mipi_dbi_init(mipi, &ili9225_pipe_funcs, &ili9225_mode, rotation);
>-	if (ret)
>-		return ret;
>-
>-	drm_mode_config_reset(drm);
>-
>-	ret = drm_dev_register(drm, 0);
>-	if (ret)
>-		return ret;
>-
>-	spi_set_drvdata(spi, drm);
>-
>-	drm_fbdev_generic_setup(drm, 0);
>-
>-	return 0;
>-}
>-
>-static int ili9225_remove(struct spi_device *spi)
>-{
>-	struct drm_device *drm = spi_get_drvdata(spi);
>-
>-	drm_dev_unplug(drm);
>-	drm_atomic_helper_shutdown(drm);
>-
>-	return 0;
>-}
>-
>-static void ili9225_shutdown(struct spi_device *spi)
>-{
>-	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>-}
>-
>-static struct spi_driver ili9225_spi_driver = {
>-	.driver = {
>-		.name = "ili9225",
>-		.owner = THIS_MODULE,
>-		.of_match_table = ili9225_of_match,
>-	},
>-	.id_table = ili9225_id,
>-	.probe = ili9225_probe,
>-	.remove = ili9225_remove,
>-	.shutdown = ili9225_shutdown,
>-};
>-module_spi_driver(ili9225_spi_driver);
>-
>-MODULE_DESCRIPTION("Ilitek ILI9225 DRM driver");
>-MODULE_AUTHOR("David Lechner <david@lechnology.com>");
>-MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/ili9341.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/ili9341.c
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/ili9341.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/ili9341.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,266 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0+
>-/*
>- * DRM driver for Ilitek ILI9341 panels
>- *
>- * Copyright 2018 David Lechner <david@lechnology.com>
>- *
>- * Based on mi0283qt.c:
>- * Copyright 2016 Noralf TrÃ¸nnes
>- */
>-
>-#include <linux/backlight.h>
>-#include <linux/delay.h>
>-#include <linux/gpio/consumer.h>
>-#include <linux/module.h>
>-#include <linux/property.h>
>-#include <linux/spi/spi.h>
>-
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_drv.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_gem_cma_helper.h>
>-#include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_modeset_helper.h>
>-#include <drm/tinydrm/mipi-dbi.h>
>-#include <drm/tinydrm/tinydrm-helpers.h>
>-#include <video/mipi_display.h>
>-
>-#define ILI9341_FRMCTR1		0xb1
>-#define ILI9341_DISCTRL		0xb6
>-#define ILI9341_ETMOD		0xb7
>-
>-#define ILI9341_PWCTRL1		0xc0
>-#define ILI9341_PWCTRL2		0xc1
>-#define ILI9341_VMCTRL1		0xc5
>-#define ILI9341_VMCTRL2		0xc7
>-#define ILI9341_PWCTRLA		0xcb
>-#define ILI9341_PWCTRLB		0xcf
>-
>-#define ILI9341_PGAMCTRL	0xe0
>-#define ILI9341_NGAMCTRL	0xe1
>-#define ILI9341_DTCTRLA		0xe8
>-#define ILI9341_DTCTRLB		0xea
>-#define ILI9341_PWRSEQ		0xed
>-
>-#define ILI9341_EN3GAM		0xf2
>-#define ILI9341_PUMPCTRL	0xf7
>-
>-#define ILI9341_MADCTL_BGR	BIT(3)
>-#define ILI9341_MADCTL_MV	BIT(5)
>-#define ILI9341_MADCTL_MX	BIT(6)
>-#define ILI9341_MADCTL_MY	BIT(7)
>-
>-static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
>-			     struct drm_crtc_state *crtc_state,
>-			     struct drm_plane_state *plane_state)
>-{
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(pipe->crtc.dev);
>-	u8 addr_mode;
>-	int ret, idx;
>-
>-	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>-		return;
>-
>-	DRM_DEBUG_KMS("\n");
>-
>-	ret = mipi_dbi_poweron_conditional_reset(mipi);
>-	if (ret < 0)
>-		goto out_exit;
>-	if (ret == 1)
>-		goto out_enable;
>-
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_OFF);
>-
>-	mipi_dbi_command(mipi, ILI9341_PWCTRLB, 0x00, 0xc1, 0x30);
>-	mipi_dbi_command(mipi, ILI9341_PWRSEQ, 0x64, 0x03, 0x12, 0x81);
>-	mipi_dbi_command(mipi, ILI9341_DTCTRLA, 0x85, 0x00, 0x78);
>-	mipi_dbi_command(mipi, ILI9341_PWCTRLA, 0x39, 0x2c, 0x00, 0x34, 0x02);
>-	mipi_dbi_command(mipi, ILI9341_PUMPCTRL, 0x20);
>-	mipi_dbi_command(mipi, ILI9341_DTCTRLB, 0x00, 0x00);
>-
>-	/* Power Control */
>-	mipi_dbi_command(mipi, ILI9341_PWCTRL1, 0x23);
>-	mipi_dbi_command(mipi, ILI9341_PWCTRL2, 0x10);
>-	/* VCOM */
>-	mipi_dbi_command(mipi, ILI9341_VMCTRL1, 0x3e, 0x28);
>-	mipi_dbi_command(mipi, ILI9341_VMCTRL2, 0x86);
>-
>-	/* Memory Access Control */
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
>-
>-	/* Frame Rate */
>-	mipi_dbi_command(mipi, ILI9341_FRMCTR1, 0x00, 0x1b);
>-
>-	/* Gamma */
>-	mipi_dbi_command(mipi, ILI9341_EN3GAM, 0x00);
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_GAMMA_CURVE, 0x01);
>-	mipi_dbi_command(mipi, ILI9341_PGAMCTRL,
>-			 0x0f, 0x31, 0x2b, 0x0c, 0x0e, 0x08, 0x4e, 0xf1,
>-			 0x37, 0x07, 0x10, 0x03, 0x0e, 0x09, 0x00);
>-	mipi_dbi_command(mipi, ILI9341_NGAMCTRL,
>-			 0x00, 0x0e, 0x14, 0x03, 0x11, 0x07, 0x31, 0xc1,
>-			 0x48, 0x08, 0x0f, 0x0c, 0x31, 0x36, 0x0f);
>-
>-	/* DDRAM */
>-	mipi_dbi_command(mipi, ILI9341_ETMOD, 0x07);
>-
>-	/* Display */
>-	mipi_dbi_command(mipi, ILI9341_DISCTRL, 0x08, 0x82, 0x27, 0x00);
>-	mipi_dbi_command(mipi, MIPI_DCS_EXIT_SLEEP_MODE);
>-	msleep(100);
>-
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_ON);
>-	msleep(100);
>-
>-out_enable:
>-	switch (mipi->rotation) {
>-	default:
>-		addr_mode = ILI9341_MADCTL_MX;
>-		break;
>-	case 90:
>-		addr_mode = ILI9341_MADCTL_MV;
>-		break;
>-	case 180:
>-		addr_mode = ILI9341_MADCTL_MY;
>-		break;
>-	case 270:
>-		addr_mode = ILI9341_MADCTL_MV | ILI9341_MADCTL_MY |
>-			    ILI9341_MADCTL_MX;
>-		break;
>-	}
>-	addr_mode |= ILI9341_MADCTL_BGR;
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
>-	mipi_dbi_enable_flush(mipi, crtc_state, plane_state);
>-out_exit:
>-	drm_dev_exit(idx);
>-}
>-
>-static const struct drm_simple_display_pipe_funcs ili9341_pipe_funcs = {
>-	.enable = yx240qv29_enable,
>-	.disable = mipi_dbi_pipe_disable,
>-	.update = mipi_dbi_pipe_update,
>-	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
>-};
>-
>-static const struct drm_display_mode yx240qv29_mode = {
>-	DRM_SIMPLE_MODE(240, 320, 37, 49),
>-};
>-
>-DEFINE_DRM_GEM_CMA_FOPS(ili9341_fops);
>-
>-static struct drm_driver ili9341_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_ATOMIC,
>-	.fops			= &ili9341_fops,
>-	.release		= mipi_dbi_release,
>-	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>-	.debugfs_init		= mipi_dbi_debugfs_init,
>-	.name			= "ili9341",
>-	.desc			= "Ilitek ILI9341",
>-	.date			= "20180514",
>-	.major			= 1,
>-	.minor			= 0,
>-};
>-
>-static const struct of_device_id ili9341_of_match[] = {
>-	{ .compatible = "adafruit,yx240qv29" },
>-	{ }
>-};
>-MODULE_DEVICE_TABLE(of, ili9341_of_match);
>-
>-static const struct spi_device_id ili9341_id[] = {
>-	{ "yx240qv29", 0 },
>-	{ }
>-};
>-MODULE_DEVICE_TABLE(spi, ili9341_id);
>-
>-static int ili9341_probe(struct spi_device *spi)
>-{
>-	struct device *dev = &spi->dev;
>-	struct drm_device *drm;
>-	struct mipi_dbi *mipi;
>-	struct gpio_desc *dc;
>-	u32 rotation = 0;
>-	int ret;
>-
>-	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
>-	if (!mipi)
>-		return -ENOMEM;
>-
>-	drm = &mipi->drm;
>-	ret = devm_drm_dev_init(dev, drm, &ili9341_driver);
>-	if (ret) {
>-		kfree(mipi);
>-		return ret;
>-	}
>-
>-	drm_mode_config_init(drm);
>-
>-	mipi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
>-	if (IS_ERR(mipi->reset)) {
>-		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
>-		return PTR_ERR(mipi->reset);
>-	}
>-
>-	dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
>-	if (IS_ERR(dc)) {
>-		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
>-		return PTR_ERR(dc);
>-	}
>-
>-	mipi->backlight = devm_of_find_backlight(dev);
>-	if (IS_ERR(mipi->backlight))
>-		return PTR_ERR(mipi->backlight);
>-
>-	device_property_read_u32(dev, "rotation", &rotation);
>-
>-	ret = mipi_dbi_spi_init(spi, mipi, dc);
>-	if (ret)
>-		return ret;
>-
>-	ret = mipi_dbi_init(mipi, &ili9341_pipe_funcs, &yx240qv29_mode, rotation);
>-	if (ret)
>-		return ret;
>-
>-	drm_mode_config_reset(drm);
>-
>-	ret = drm_dev_register(drm, 0);
>-	if (ret)
>-		return ret;
>-
>-	spi_set_drvdata(spi, drm);
>-
>-	drm_fbdev_generic_setup(drm, 0);
>-
>-	return 0;
>-}
>-
>-static int ili9341_remove(struct spi_device *spi)
>-{
>-	struct drm_device *drm = spi_get_drvdata(spi);
>-
>-	drm_dev_unplug(drm);
>-	drm_atomic_helper_shutdown(drm);
>-
>-	return 0;
>-}
>-
>-static void ili9341_shutdown(struct spi_device *spi)
>-{
>-	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>-}
>-
>-static struct spi_driver ili9341_spi_driver = {
>-	.driver = {
>-		.name = "ili9341",
>-		.of_match_table = ili9341_of_match,
>-	},
>-	.id_table = ili9341_id,
>-	.probe = ili9341_probe,
>-	.remove = ili9341_remove,
>-	.shutdown = ili9341_shutdown,
>-};
>-module_spi_driver(ili9341_spi_driver);
>-
>-MODULE_DESCRIPTION("Ilitek ILI9341 DRM driver");
>-MODULE_AUTHOR("David Lechner <david@lechnology.com>");
>-MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/Kconfig linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/Kconfig
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/Kconfig	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/Kconfig	1969-12-31 18:00:00.000000000 -0600
>@@ -1,87 +0,0 @@
>-# SPDX-License-Identifier: GPL-2.0-only
>-menuconfig DRM_TINYDRM
>-	tristate "Support for simple displays"
>-	depends on DRM
>-	select DRM_KMS_HELPER
>-	select DRM_KMS_CMA_HELPER
>-	help
>-	  Choose this option if you have a tinydrm supported display.
>-	  If M is selected the module will be called tinydrm.
>-
>-config TINYDRM_MIPI_DBI
>-	tristate
>-
>-config TINYDRM_HX8357D
>-	tristate "DRM support for HX8357D display panels"
>-	depends on DRM_TINYDRM && SPI
>-	depends on BACKLIGHT_CLASS_DEVICE
>-	select TINYDRM_MIPI_DBI
>-	help
>-	  DRM driver for the following HX8357D panels:
>-	  * YX350HV15-T 3.5" 340x350 TFT (Adafruit 3.5")
>-
>-	  If M is selected the module will be called hx8357d.
>-
>-config TINYDRM_ILI9225
>-	tristate "DRM support for ILI9225 display panels"
>-	depends on DRM_TINYDRM && SPI
>-	select TINYDRM_MIPI_DBI
>-	help
>-	  DRM driver for the following Ilitek ILI9225 panels:
>-	  * No-name 2.2" color screen module
>-
>-	  If M is selected the module will be called ili9225.
>-
>-config TINYDRM_ILI9341
>-	tristate "DRM support for ILI9341 display panels"
>-	depends on DRM_TINYDRM && SPI
>-	depends on BACKLIGHT_CLASS_DEVICE
>-	select TINYDRM_MIPI_DBI
>-	help
>-	  DRM driver for the following Ilitek ILI9341 panels:
>-	  * YX240QV29-T 2.4" 240x320 TFT (Adafruit 2.4")
>-
>-	  If M is selected the module will be called ili9341.
>-
>-config TINYDRM_MI0283QT
>-	tristate "DRM support for MI0283QT"
>-	depends on DRM_TINYDRM && SPI
>-	depends on BACKLIGHT_CLASS_DEVICE
>-	select TINYDRM_MIPI_DBI
>-	help
>-	  DRM driver for the Multi-Inno MI0283QT display panel
>-	  If M is selected the module will be called mi0283qt.
>-
>-config TINYDRM_REPAPER
>-	tristate "DRM support for Pervasive Displays RePaper panels (V231)"
>-	depends on DRM_TINYDRM && SPI
>-	depends on THERMAL || !THERMAL
>-	help
>-	  DRM driver for the following Pervasive Displays panels:
>-	  1.44" TFT EPD Panel (E1144CS021)
>-	  1.90" TFT EPD Panel (E1190CS021)
>-	  2.00" TFT EPD Panel (E2200CS021)
>-	  2.71" TFT EPD Panel (E2271CS021)
>-
>-	  If M is selected the module will be called repaper.
>-
>-config TINYDRM_ST7586
>-	tristate "DRM support for Sitronix ST7586 display panels"
>-	depends on DRM_TINYDRM && SPI
>-	select TINYDRM_MIPI_DBI
>-	help
>-	  DRM driver for the following Sitronix ST7586 panels:
>-	  * LEGO MINDSTORMS EV3
>-
>-	  If M is selected the module will be called st7586.
>-
>-config TINYDRM_ST7735R
>-	tristate "DRM support for Sitronix ST7735R display panels"
>-	depends on DRM_TINYDRM && SPI
>-	depends on BACKLIGHT_CLASS_DEVICE
>-	select TINYDRM_MIPI_DBI
>-	help
>-	  DRM driver Sitronix ST7735R with one of the following LCDs:
>-	  * JD-T18003-T01 1.8" 128x160 TFT
>-
>-	  If M is selected the module will be called st7735r.
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/Makefile	1969-12-31 18:00:00.000000000 -0600
>@@ -1,14 +0,0 @@
>-# SPDX-License-Identifier: GPL-2.0-only
>-obj-$(CONFIG_DRM_TINYDRM)		+= core/
>-
>-# Controllers
>-obj-$(CONFIG_TINYDRM_MIPI_DBI)		+= mipi-dbi.o
>-
>-# Displays
>-obj-$(CONFIG_TINYDRM_HX8357D)		+= hx8357d.o
>-obj-$(CONFIG_TINYDRM_ILI9225)		+= ili9225.o
>-obj-$(CONFIG_TINYDRM_ILI9341)		+= ili9341.o
>-obj-$(CONFIG_TINYDRM_MI0283QT)		+= mi0283qt.o
>-obj-$(CONFIG_TINYDRM_REPAPER)		+= repaper.o
>-obj-$(CONFIG_TINYDRM_ST7586)		+= st7586.o
>-obj-$(CONFIG_TINYDRM_ST7735R)		+= st7735r.o
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/mi0283qt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/mi0283qt.c
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/mi0283qt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/mi0283qt.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,293 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0-or-later
>-/*
>- * DRM driver for Multi-Inno MI0283QT panels
>- *
>- * Copyright 2016 Noralf TrÃ¸nnes
>- */
>-
>-#include <linux/backlight.h>
>-#include <linux/delay.h>
>-#include <linux/gpio/consumer.h>
>-#include <linux/module.h>
>-#include <linux/property.h>
>-#include <linux/regulator/consumer.h>
>-#include <linux/spi/spi.h>
>-
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_drv.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_gem_cma_helper.h>
>-#include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_modeset_helper.h>
>-#include <drm/tinydrm/mipi-dbi.h>
>-#include <drm/tinydrm/tinydrm-helpers.h>
>-#include <video/mipi_display.h>
>-
>-#define ILI9341_FRMCTR1		0xb1
>-#define ILI9341_DISCTRL		0xb6
>-#define ILI9341_ETMOD		0xb7
>-
>-#define ILI9341_PWCTRL1		0xc0
>-#define ILI9341_PWCTRL2		0xc1
>-#define ILI9341_VMCTRL1		0xc5
>-#define ILI9341_VMCTRL2		0xc7
>-#define ILI9341_PWCTRLA		0xcb
>-#define ILI9341_PWCTRLB		0xcf
>-
>-#define ILI9341_PGAMCTRL	0xe0
>-#define ILI9341_NGAMCTRL	0xe1
>-#define ILI9341_DTCTRLA		0xe8
>-#define ILI9341_DTCTRLB		0xea
>-#define ILI9341_PWRSEQ		0xed
>-
>-#define ILI9341_EN3GAM		0xf2
>-#define ILI9341_PUMPCTRL	0xf7
>-
>-#define ILI9341_MADCTL_BGR	BIT(3)
>-#define ILI9341_MADCTL_MV	BIT(5)
>-#define ILI9341_MADCTL_MX	BIT(6)
>-#define ILI9341_MADCTL_MY	BIT(7)
>-
>-static void mi0283qt_enable(struct drm_simple_display_pipe *pipe,
>-			    struct drm_crtc_state *crtc_state,
>-			    struct drm_plane_state *plane_state)
>-{
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(pipe->crtc.dev);
>-	u8 addr_mode;
>-	int ret, idx;
>-
>-	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>-		return;
>-
>-	DRM_DEBUG_KMS("\n");
>-
>-	ret = mipi_dbi_poweron_conditional_reset(mipi);
>-	if (ret < 0)
>-		goto out_exit;
>-	if (ret == 1)
>-		goto out_enable;
>-
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_OFF);
>-
>-	mipi_dbi_command(mipi, ILI9341_PWCTRLB, 0x00, 0x83, 0x30);
>-	mipi_dbi_command(mipi, ILI9341_PWRSEQ, 0x64, 0x03, 0x12, 0x81);
>-	mipi_dbi_command(mipi, ILI9341_DTCTRLA, 0x85, 0x01, 0x79);
>-	mipi_dbi_command(mipi, ILI9341_PWCTRLA, 0x39, 0x2c, 0x00, 0x34, 0x02);
>-	mipi_dbi_command(mipi, ILI9341_PUMPCTRL, 0x20);
>-	mipi_dbi_command(mipi, ILI9341_DTCTRLB, 0x00, 0x00);
>-
>-	/* Power Control */
>-	mipi_dbi_command(mipi, ILI9341_PWCTRL1, 0x26);
>-	mipi_dbi_command(mipi, ILI9341_PWCTRL2, 0x11);
>-	/* VCOM */
>-	mipi_dbi_command(mipi, ILI9341_VMCTRL1, 0x35, 0x3e);
>-	mipi_dbi_command(mipi, ILI9341_VMCTRL2, 0xbe);
>-
>-	/* Memory Access Control */
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT);
>-
>-	/* Frame Rate */
>-	mipi_dbi_command(mipi, ILI9341_FRMCTR1, 0x00, 0x1b);
>-
>-	/* Gamma */
>-	mipi_dbi_command(mipi, ILI9341_EN3GAM, 0x08);
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_GAMMA_CURVE, 0x01);
>-	mipi_dbi_command(mipi, ILI9341_PGAMCTRL,
>-		       0x1f, 0x1a, 0x18, 0x0a, 0x0f, 0x06, 0x45, 0x87,
>-		       0x32, 0x0a, 0x07, 0x02, 0x07, 0x05, 0x00);
>-	mipi_dbi_command(mipi, ILI9341_NGAMCTRL,
>-		       0x00, 0x25, 0x27, 0x05, 0x10, 0x09, 0x3a, 0x78,
>-		       0x4d, 0x05, 0x18, 0x0d, 0x38, 0x3a, 0x1f);
>-
>-	/* DDRAM */
>-	mipi_dbi_command(mipi, ILI9341_ETMOD, 0x07);
>-
>-	/* Display */
>-	mipi_dbi_command(mipi, ILI9341_DISCTRL, 0x0a, 0x82, 0x27, 0x00);
>-	mipi_dbi_command(mipi, MIPI_DCS_EXIT_SLEEP_MODE);
>-	msleep(100);
>-
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_ON);
>-	msleep(100);
>-
>-out_enable:
>-	/* The PiTFT (ili9340) has a hardware reset circuit that
>-	 * resets only on power-on and not on each reboot through
>-	 * a gpio like the rpi-display does.
>-	 * As a result, we need to always apply the rotation value
>-	 * regardless of the display "on/off" state.
>-	 */
>-	switch (mipi->rotation) {
>-	default:
>-		addr_mode = ILI9341_MADCTL_MV | ILI9341_MADCTL_MY |
>-			    ILI9341_MADCTL_MX;
>-		break;
>-	case 90:
>-		addr_mode = ILI9341_MADCTL_MY;
>-		break;
>-	case 180:
>-		addr_mode = ILI9341_MADCTL_MV;
>-		break;
>-	case 270:
>-		addr_mode = ILI9341_MADCTL_MX;
>-		break;
>-	}
>-	addr_mode |= ILI9341_MADCTL_BGR;
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
>-	mipi_dbi_enable_flush(mipi, crtc_state, plane_state);
>-out_exit:
>-	drm_dev_exit(idx);
>-}
>-
>-static const struct drm_simple_display_pipe_funcs mi0283qt_pipe_funcs = {
>-	.enable = mi0283qt_enable,
>-	.disable = mipi_dbi_pipe_disable,
>-	.update = mipi_dbi_pipe_update,
>-	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
>-};
>-
>-static const struct drm_display_mode mi0283qt_mode = {
>-	DRM_SIMPLE_MODE(320, 240, 58, 43),
>-};
>-
>-DEFINE_DRM_GEM_CMA_FOPS(mi0283qt_fops);
>-
>-static struct drm_driver mi0283qt_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
>-				  DRIVER_ATOMIC,
>-	.fops			= &mi0283qt_fops,
>-	.release		= mipi_dbi_release,
>-	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>-	.debugfs_init		= mipi_dbi_debugfs_init,
>-	.name			= "mi0283qt",
>-	.desc			= "Multi-Inno MI0283QT",
>-	.date			= "20160614",
>-	.major			= 1,
>-	.minor			= 0,
>-};
>-
>-static const struct of_device_id mi0283qt_of_match[] = {
>-	{ .compatible = "multi-inno,mi0283qt" },
>-	{},
>-};
>-MODULE_DEVICE_TABLE(of, mi0283qt_of_match);
>-
>-static const struct spi_device_id mi0283qt_id[] = {
>-	{ "mi0283qt", 0 },
>-	{ },
>-};
>-MODULE_DEVICE_TABLE(spi, mi0283qt_id);
>-
>-static int mi0283qt_probe(struct spi_device *spi)
>-{
>-	struct device *dev = &spi->dev;
>-	struct drm_device *drm;
>-	struct mipi_dbi *mipi;
>-	struct gpio_desc *dc;
>-	u32 rotation = 0;
>-	int ret;
>-
>-	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
>-	if (!mipi)
>-		return -ENOMEM;
>-
>-	drm = &mipi->drm;
>-	ret = devm_drm_dev_init(dev, drm, &mi0283qt_driver);
>-	if (ret) {
>-		kfree(mipi);
>-		return ret;
>-	}
>-
>-	drm_mode_config_init(drm);
>-
>-	mipi->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
>-	if (IS_ERR(mipi->reset)) {
>-		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
>-		return PTR_ERR(mipi->reset);
>-	}
>-
>-	dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
>-	if (IS_ERR(dc)) {
>-		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
>-		return PTR_ERR(dc);
>-	}
>-
>-	mipi->regulator = devm_regulator_get(dev, "power");
>-	if (IS_ERR(mipi->regulator))
>-		return PTR_ERR(mipi->regulator);
>-
>-	mipi->backlight = devm_of_find_backlight(dev);
>-	if (IS_ERR(mipi->backlight))
>-		return PTR_ERR(mipi->backlight);
>-
>-	device_property_read_u32(dev, "rotation", &rotation);
>-
>-	ret = mipi_dbi_spi_init(spi, mipi, dc);
>-	if (ret)
>-		return ret;
>-
>-	ret = mipi_dbi_init(mipi, &mi0283qt_pipe_funcs, &mi0283qt_mode, rotation);
>-	if (ret)
>-		return ret;
>-
>-	drm_mode_config_reset(drm);
>-
>-	ret = drm_dev_register(drm, 0);
>-	if (ret)
>-		return ret;
>-
>-	spi_set_drvdata(spi, drm);
>-
>-	drm_fbdev_generic_setup(drm, 0);
>-
>-	return 0;
>-}
>-
>-static int mi0283qt_remove(struct spi_device *spi)
>-{
>-	struct drm_device *drm = spi_get_drvdata(spi);
>-
>-	drm_dev_unplug(drm);
>-	drm_atomic_helper_shutdown(drm);
>-
>-	return 0;
>-}
>-
>-static void mi0283qt_shutdown(struct spi_device *spi)
>-{
>-	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>-}
>-
>-static int __maybe_unused mi0283qt_pm_suspend(struct device *dev)
>-{
>-	return drm_mode_config_helper_suspend(dev_get_drvdata(dev));
>-}
>-
>-static int __maybe_unused mi0283qt_pm_resume(struct device *dev)
>-{
>-	drm_mode_config_helper_resume(dev_get_drvdata(dev));
>-
>-	return 0;
>-}
>-
>-static const struct dev_pm_ops mi0283qt_pm_ops = {
>-	SET_SYSTEM_SLEEP_PM_OPS(mi0283qt_pm_suspend, mi0283qt_pm_resume)
>-};
>-
>-static struct spi_driver mi0283qt_spi_driver = {
>-	.driver = {
>-		.name = "mi0283qt",
>-		.owner = THIS_MODULE,
>-		.of_match_table = mi0283qt_of_match,
>-		.pm = &mi0283qt_pm_ops,
>-	},
>-	.id_table = mi0283qt_id,
>-	.probe = mi0283qt_probe,
>-	.remove = mi0283qt_remove,
>-	.shutdown = mi0283qt_shutdown,
>-};
>-module_spi_driver(mi0283qt_spi_driver);
>-
>-MODULE_DESCRIPTION("Multi-Inno MI0283QT DRM driver");
>-MODULE_AUTHOR("Noralf TrÃ¸nnes");
>-MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/mipi-dbi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/mipi-dbi.c
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/mipi-dbi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/mipi-dbi.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,1175 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0-or-later
>-/*
>- * MIPI Display Bus Interface (DBI) LCD controller support
>- *
>- * Copyright 2016 Noralf TrÃ¸nnes
>- */
>-
>-#include <linux/debugfs.h>
>-#include <linux/delay.h>
>-#include <linux/dma-buf.h>
>-#include <linux/gpio/consumer.h>
>-#include <linux/module.h>
>-#include <linux/regulator/consumer.h>
>-#include <linux/spi/spi.h>
>-
>-#include <drm/drm_damage_helper.h>
>-#include <drm/drm_drv.h>
>-#include <drm/drm_fb_cma_helper.h>
>-#include <drm/drm_gem_cma_helper.h>
>-#include <drm/drm_format_helper.h>
>-#include <drm/drm_fourcc.h>
>-#include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_vblank.h>
>-#include <drm/drm_rect.h>
>-#include <drm/tinydrm/mipi-dbi.h>
>-#include <drm/tinydrm/tinydrm-helpers.h>
>-#include <video/mipi_display.h>
>-
>-#define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
>-
>-#define DCS_POWER_MODE_DISPLAY			BIT(2)
>-#define DCS_POWER_MODE_DISPLAY_NORMAL_MODE	BIT(3)
>-#define DCS_POWER_MODE_SLEEP_MODE		BIT(4)
>-#define DCS_POWER_MODE_PARTIAL_MODE		BIT(5)
>-#define DCS_POWER_MODE_IDLE_MODE		BIT(6)
>-#define DCS_POWER_MODE_RESERVED_MASK		(BIT(0) | BIT(1) | BIT(7))
>-
>-/**
>- * DOC: overview
>- *
>- * This library provides helpers for MIPI Display Bus Interface (DBI)
>- * compatible display controllers.
>- *
>- * Many controllers for tiny lcd displays are MIPI compliant and can use this
>- * library. If a controller uses registers 0x2A and 0x2B to set the area to
>- * update and uses register 0x2C to write to frame memory, it is most likely
>- * MIPI compliant.
>- *
>- * Only MIPI Type 1 displays are supported since a full frame memory is needed.
>- *
>- * There are 3 MIPI DBI implementation types:
>- *
>- * A. Motorola 6800 type parallel bus
>- *
>- * B. Intel 8080 type parallel bus
>- *
>- * C. SPI type with 3 options:
>- *
>- *    1. 9-bit with the Data/Command signal as the ninth bit
>- *    2. Same as above except it's sent as 16 bits
>- *    3. 8-bit with the Data/Command signal as a separate D/CX pin
>- *
>- * Currently mipi_dbi only supports Type C options 1 and 3 with
>- * mipi_dbi_spi_init().
>- */
>-
>-#define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
>-({ \
>-	if (!len) \
>-		DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
>-	else if (len <= 32) \
>-		DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
>-	else \
>-		DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
>-})
>-
>-static const u8 mipi_dbi_dcs_read_commands[] = {
>-	MIPI_DCS_GET_DISPLAY_ID,
>-	MIPI_DCS_GET_RED_CHANNEL,
>-	MIPI_DCS_GET_GREEN_CHANNEL,
>-	MIPI_DCS_GET_BLUE_CHANNEL,
>-	MIPI_DCS_GET_DISPLAY_STATUS,
>-	MIPI_DCS_GET_POWER_MODE,
>-	MIPI_DCS_GET_ADDRESS_MODE,
>-	MIPI_DCS_GET_PIXEL_FORMAT,
>-	MIPI_DCS_GET_DISPLAY_MODE,
>-	MIPI_DCS_GET_SIGNAL_MODE,
>-	MIPI_DCS_GET_DIAGNOSTIC_RESULT,
>-	MIPI_DCS_READ_MEMORY_START,
>-	MIPI_DCS_READ_MEMORY_CONTINUE,
>-	MIPI_DCS_GET_SCANLINE,
>-	MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
>-	MIPI_DCS_GET_CONTROL_DISPLAY,
>-	MIPI_DCS_GET_POWER_SAVE,
>-	MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
>-	MIPI_DCS_READ_DDB_START,
>-	MIPI_DCS_READ_DDB_CONTINUE,
>-	0, /* sentinel */
>-};
>-
>-static bool mipi_dbi_command_is_read(struct mipi_dbi *mipi, u8 cmd)
>-{
>-	unsigned int i;
>-
>-	if (!mipi->read_commands)
>-		return false;
>-
>-	for (i = 0; i < 0xff; i++) {
>-		if (!mipi->read_commands[i])
>-			return false;
>-		if (cmd == mipi->read_commands[i])
>-			return true;
>-	}
>-
>-	return false;
>-}
>-
>-/**
>- * mipi_dbi_command_read - MIPI DCS read command
>- * @mipi: MIPI structure
>- * @cmd: Command
>- * @val: Value read
>- *
>- * Send MIPI DCS read command to the controller.
>- *
>- * Returns:
>- * Zero on success, negative error code on failure.
>- */
>-int mipi_dbi_command_read(struct mipi_dbi *mipi, u8 cmd, u8 *val)
>-{
>-	if (!mipi->read_commands)
>-		return -EACCES;
>-
>-	if (!mipi_dbi_command_is_read(mipi, cmd))
>-		return -EINVAL;
>-
>-	return mipi_dbi_command_buf(mipi, cmd, val, 1);
>-}
>-EXPORT_SYMBOL(mipi_dbi_command_read);
>-
>-/**
>- * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
>- * @mipi: MIPI structure
>- * @cmd: Command
>- * @data: Parameter buffer
>- * @len: Buffer length
>- *
>- * Returns:
>- * Zero on success, negative error code on failure.
>- */
>-int mipi_dbi_command_buf(struct mipi_dbi *mipi, u8 cmd, u8 *data, size_t len)
>-{
>-	u8 *cmdbuf;
>-	int ret;
>-
>-	/* SPI requires dma-safe buffers */
>-	cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
>-	if (!cmdbuf)
>-		return -ENOMEM;
>-
>-	mutex_lock(&mipi->cmdlock);
>-	ret = mipi->command(mipi, cmdbuf, data, len);
>-	mutex_unlock(&mipi->cmdlock);
>-
>-	kfree(cmdbuf);
>-
>-	return ret;
>-}
>-EXPORT_SYMBOL(mipi_dbi_command_buf);
>-
>-/* This should only be used by mipi_dbi_command() */
>-int mipi_dbi_command_stackbuf(struct mipi_dbi *mipi, u8 cmd, u8 *data, size_t len)
>-{
>-	u8 *buf;
>-	int ret;
>-
>-	buf = kmemdup(data, len, GFP_KERNEL);
>-	if (!buf)
>-		return -ENOMEM;
>-
>-	ret = mipi_dbi_command_buf(mipi, cmd, buf, len);
>-
>-	kfree(buf);
>-
>-	return ret;
>-}
>-EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
>-
>-/**
>- * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
>- * @dst: The destination buffer
>- * @fb: The source framebuffer
>- * @clip: Clipping rectangle of the area to be copied
>- * @swap: When true, swap MSB/LSB of 16-bit values
>- *
>- * Returns:
>- * Zero on success, negative error code on failure.
>- */
>-int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
>-		      struct drm_rect *clip, bool swap)
>-{
>-	struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
>-	struct dma_buf_attachment *import_attach = cma_obj->base.import_attach;
>-	struct drm_format_name_buf format_name;
>-	void *src = cma_obj->vaddr;
>-	int ret = 0;
>-
>-	if (import_attach) {
>-		ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
>-					       DMA_FROM_DEVICE);
>-		if (ret)
>-			return ret;
>-	}
>-
>-	switch (fb->format->format) {
>-	case DRM_FORMAT_RGB565:
>-		if (swap)
>-			drm_fb_swab16(dst, src, fb, clip);
>-		else
>-			drm_fb_memcpy(dst, src, fb, clip);
>-		break;
>-	case DRM_FORMAT_XRGB8888:
>-		drm_fb_xrgb8888_to_rgb565(dst, src, fb, clip, swap);
>-		break;
>-	default:
>-		dev_err_once(fb->dev->dev, "Format is not supported: %s\n",
>-			     drm_get_format_name(fb->format->format,
>-						 &format_name));
>-		return -EINVAL;
>-	}
>-
>-	if (import_attach)
>-		ret = dma_buf_end_cpu_access(import_attach->dmabuf,
>-					     DMA_FROM_DEVICE);
>-	return ret;
>-}
>-EXPORT_SYMBOL(mipi_dbi_buf_copy);
>-
>-static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
>-{
>-	struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(fb->dev);
>-	unsigned int height = rect->y2 - rect->y1;
>-	unsigned int width = rect->x2 - rect->x1;
>-	bool swap = mipi->swap_bytes;
>-	int idx, ret = 0;
>-	bool full;
>-	void *tr;
>-
>-	if (!mipi->enabled)
>-		return;
>-
>-	if (!drm_dev_enter(fb->dev, &idx))
>-		return;
>-
>-	full = width == fb->width && height == fb->height;
>-
>-	DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
>-
>-	if (!mipi->dc || !full || swap ||
>-	    fb->format->format == DRM_FORMAT_XRGB8888) {
>-		tr = mipi->tx_buf;
>-		ret = mipi_dbi_buf_copy(mipi->tx_buf, fb, rect, swap);
>-		if (ret)
>-			goto err_msg;
>-	} else {
>-		tr = cma_obj->vaddr;
>-	}
>-
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_COLUMN_ADDRESS,
>-			 (rect->x1 >> 8) & 0xff, rect->x1 & 0xff,
>-			 ((rect->x2 - 1) >> 8) & 0xff, (rect->x2 - 1) & 0xff);
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_PAGE_ADDRESS,
>-			 (rect->y1 >> 8) & 0xff, rect->y1 & 0xff,
>-			 ((rect->y2 - 1) >> 8) & 0xff, (rect->y2 - 1) & 0xff);
>-
>-	ret = mipi_dbi_command_buf(mipi, MIPI_DCS_WRITE_MEMORY_START, tr,
>-				   width * height * 2);
>-err_msg:
>-	if (ret)
>-		dev_err_once(fb->dev->dev, "Failed to update display %d\n", ret);
>-
>-	drm_dev_exit(idx);
>-}
>-
>-/**
>- * mipi_dbi_pipe_update - Display pipe update helper
>- * @pipe: Simple display pipe
>- * @old_state: Old plane state
>- *
>- * This function handles framebuffer flushing and vblank events. Drivers can use
>- * this as their &drm_simple_display_pipe_funcs->update callback.
>- */
>-void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
>-			  struct drm_plane_state *old_state)
>-{
>-	struct drm_plane_state *state = pipe->plane.state;
>-	struct drm_crtc *crtc = &pipe->crtc;
>-	struct drm_rect rect;
>-
>-	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
>-		mipi_dbi_fb_dirty(state->fb, &rect);
>-
>-	if (crtc->state->event) {
>-		spin_lock_irq(&crtc->dev->event_lock);
>-		drm_crtc_send_vblank_event(crtc, crtc->state->event);
>-		spin_unlock_irq(&crtc->dev->event_lock);
>-		crtc->state->event = NULL;
>-	}
>-}
>-EXPORT_SYMBOL(mipi_dbi_pipe_update);
>-
>-/**
>- * mipi_dbi_enable_flush - MIPI DBI enable helper
>- * @mipi: MIPI DBI structure
>- * @crtc_state: CRTC state
>- * @plane_state: Plane state
>- *
>- * This function sets &mipi_dbi->enabled, flushes the whole framebuffer and
>- * enables the backlight. Drivers can use this in their
>- * &drm_simple_display_pipe_funcs->enable callback.
>- *
>- * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom
>- * framebuffer flushing, can't use this function since they both use the same
>- * flushing code.
>- */
>-void mipi_dbi_enable_flush(struct mipi_dbi *mipi,
>-			   struct drm_crtc_state *crtc_state,
>-			   struct drm_plane_state *plane_state)
>-{
>-	struct drm_framebuffer *fb = plane_state->fb;
>-	struct drm_rect rect = {
>-		.x1 = 0,
>-		.x2 = fb->width,
>-		.y1 = 0,
>-		.y2 = fb->height,
>-	};
>-	int idx;
>-
>-	if (!drm_dev_enter(&mipi->drm, &idx))
>-		return;
>-
>-	mipi->enabled = true;
>-	mipi_dbi_fb_dirty(fb, &rect);
>-	backlight_enable(mipi->backlight);
>-
>-	drm_dev_exit(idx);
>-}
>-EXPORT_SYMBOL(mipi_dbi_enable_flush);
>-
>-static void mipi_dbi_blank(struct mipi_dbi *mipi)
>-{
>-	struct drm_device *drm = &mipi->drm;
>-	u16 height = drm->mode_config.min_height;
>-	u16 width = drm->mode_config.min_width;
>-	size_t len = width * height * 2;
>-	int idx;
>-
>-	if (!drm_dev_enter(drm, &idx))
>-		return;
>-
>-	memset(mipi->tx_buf, 0, len);
>-
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_COLUMN_ADDRESS, 0, 0,
>-			 (width >> 8) & 0xFF, (width - 1) & 0xFF);
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_PAGE_ADDRESS, 0, 0,
>-			 (height >> 8) & 0xFF, (height - 1) & 0xFF);
>-	mipi_dbi_command_buf(mipi, MIPI_DCS_WRITE_MEMORY_START,
>-			     (u8 *)mipi->tx_buf, len);
>-
>-	drm_dev_exit(idx);
>-}
>-
>-/**
>- * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
>- * @pipe: Display pipe
>- *
>- * This function disables backlight if present, if not the display memory is
>- * blanked. The regulator is disabled if in use. Drivers can use this as their
>- * &drm_simple_display_pipe_funcs->disable callback.
>- */
>-void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
>-{
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(pipe->crtc.dev);
>-
>-	if (!mipi->enabled)
>-		return;
>-
>-	DRM_DEBUG_KMS("\n");
>-
>-	mipi->enabled = false;
>-
>-	if (mipi->backlight)
>-		backlight_disable(mipi->backlight);
>-	else
>-		mipi_dbi_blank(mipi);
>-
>-	if (mipi->regulator)
>-		regulator_disable(mipi->regulator);
>-}
>-EXPORT_SYMBOL(mipi_dbi_pipe_disable);
>-
>-static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
>-	.fb_create = drm_gem_fb_create_with_dirty,
>-	.atomic_check = drm_atomic_helper_check,
>-	.atomic_commit = drm_atomic_helper_commit,
>-};
>-
>-static const uint32_t mipi_dbi_formats[] = {
>-	DRM_FORMAT_RGB565,
>-	DRM_FORMAT_XRGB8888,
>-};
>-
>-/**
>- * mipi_dbi_init - MIPI DBI initialization
>- * @mipi: &mipi_dbi structure to initialize
>- * @funcs: Display pipe functions
>- * @mode: Display mode
>- * @rotation: Initial rotation in degrees Counter Clock Wise
>- *
>- * This function sets up a &drm_simple_display_pipe with a &drm_connector that
>- * has one fixed &drm_display_mode which is rotated according to @rotation.
>- * This mode is used to set the mode config min/max width/height properties.
>- * Additionally &mipi_dbi.tx_buf is allocated.
>- *
>- * Supported formats: Native RGB565 and emulated XRGB8888.
>- *
>- * Returns:
>- * Zero on success, negative error code on failure.
>- */
>-int mipi_dbi_init(struct mipi_dbi *mipi,
>-		  const struct drm_simple_display_pipe_funcs *funcs,
>-		  const struct drm_display_mode *mode, unsigned int rotation)
>-{
>-	size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
>-	struct drm_device *drm = &mipi->drm;
>-	int ret;
>-
>-	if (!mipi->command)
>-		return -EINVAL;
>-
>-	mutex_init(&mipi->cmdlock);
>-
>-	mipi->tx_buf = devm_kmalloc(drm->dev, bufsize, GFP_KERNEL);
>-	if (!mipi->tx_buf)
>-		return -ENOMEM;
>-
>-	/* TODO: Maybe add DRM_MODE_CONNECTOR_SPI */
>-	ret = tinydrm_display_pipe_init(drm, &mipi->pipe, funcs,
>-					DRM_MODE_CONNECTOR_VIRTUAL,
>-					mipi_dbi_formats,
>-					ARRAY_SIZE(mipi_dbi_formats), mode,
>-					rotation);
>-	if (ret)
>-		return ret;
>-
>-	drm_plane_enable_fb_damage_clips(&mipi->pipe.plane);
>-
>-	drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
>-	drm->mode_config.preferred_depth = 16;
>-	mipi->rotation = rotation;
>-
>-	DRM_DEBUG_KMS("preferred_depth=%u, rotation = %u\n",
>-		      drm->mode_config.preferred_depth, rotation);
>-
>-	return 0;
>-}
>-EXPORT_SYMBOL(mipi_dbi_init);
>-
>-/**
>- * mipi_dbi_release - DRM driver release helper
>- * @drm: DRM device
>- *
>- * This function finalizes and frees &mipi_dbi.
>- *
>- * Drivers can use this as their &drm_driver->release callback.
>- */
>-void mipi_dbi_release(struct drm_device *drm)
>-{
>-	struct mipi_dbi *dbi = drm_to_mipi_dbi(drm);
>-
>-	DRM_DEBUG_DRIVER("\n");
>-
>-	drm_mode_config_cleanup(drm);
>-	drm_dev_fini(drm);
>-	kfree(dbi);
>-}
>-EXPORT_SYMBOL(mipi_dbi_release);
>-
>-/**
>- * mipi_dbi_hw_reset - Hardware reset of controller
>- * @mipi: MIPI DBI structure
>- *
>- * Reset controller if the &mipi_dbi->reset gpio is set.
>- */
>-void mipi_dbi_hw_reset(struct mipi_dbi *mipi)
>-{
>-	if (!mipi->reset)
>-		return;
>-
>-	gpiod_set_value_cansleep(mipi->reset, 0);
>-	usleep_range(20, 1000);
>-	gpiod_set_value_cansleep(mipi->reset, 1);
>-	msleep(120);
>-}
>-EXPORT_SYMBOL(mipi_dbi_hw_reset);
>-
>-/**
>- * mipi_dbi_display_is_on - Check if display is on
>- * @mipi: MIPI DBI structure
>- *
>- * This function checks the Power Mode register (if readable) to see if
>- * display output is turned on. This can be used to see if the bootloader
>- * has already turned on the display avoiding flicker when the pipeline is
>- * enabled.
>- *
>- * Returns:
>- * true if the display can be verified to be on, false otherwise.
>- */
>-bool mipi_dbi_display_is_on(struct mipi_dbi *mipi)
>-{
>-	u8 val;
>-
>-	if (mipi_dbi_command_read(mipi, MIPI_DCS_GET_POWER_MODE, &val))
>-		return false;
>-
>-	val &= ~DCS_POWER_MODE_RESERVED_MASK;
>-
>-	/* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */
>-	if (val != (DCS_POWER_MODE_DISPLAY |
>-	    DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
>-		return false;
>-
>-	DRM_DEBUG_DRIVER("Display is ON\n");
>-
>-	return true;
>-}
>-EXPORT_SYMBOL(mipi_dbi_display_is_on);
>-
>-static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi *mipi, bool cond)
>-{
>-	struct device *dev = mipi->drm.dev;
>-	int ret;
>-
>-	if (mipi->regulator) {
>-		ret = regulator_enable(mipi->regulator);
>-		if (ret) {
>-			DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
>-			return ret;
>-		}
>-	}
>-
>-	if (cond && mipi_dbi_display_is_on(mipi))
>-		return 1;
>-
>-	mipi_dbi_hw_reset(mipi);
>-	ret = mipi_dbi_command(mipi, MIPI_DCS_SOFT_RESET);
>-	if (ret) {
>-		DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
>-		if (mipi->regulator)
>-			regulator_disable(mipi->regulator);
>-		return ret;
>-	}
>-
>-	/*
>-	 * If we did a hw reset, we know the controller is in Sleep mode and
>-	 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't,
>-	 * we assume worst case and wait 120ms.
>-	 */
>-	if (mipi->reset)
>-		usleep_range(5000, 20000);
>-	else
>-		msleep(120);
>-
>-	return 0;
>-}
>-
>-/**
>- * mipi_dbi_poweron_reset - MIPI DBI poweron and reset
>- * @mipi: MIPI DBI structure
>- *
>- * This function enables the regulator if used and does a hardware and software
>- * reset.
>- *
>- * Returns:
>- * Zero on success, or a negative error code.
>- */
>-int mipi_dbi_poweron_reset(struct mipi_dbi *mipi)
>-{
>-	return mipi_dbi_poweron_reset_conditional(mipi, false);
>-}
>-EXPORT_SYMBOL(mipi_dbi_poweron_reset);
>-
>-/**
>- * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset
>- * @mipi: MIPI DBI structure
>- *
>- * This function enables the regulator if used and if the display is off, it
>- * does a hardware and software reset. If mipi_dbi_display_is_on() determines
>- * that the display is on, no reset is performed.
>- *
>- * Returns:
>- * Zero if the controller was reset, 1 if the display was already on, or a
>- * negative error code.
>- */
>-int mipi_dbi_poweron_conditional_reset(struct mipi_dbi *mipi)
>-{
>-	return mipi_dbi_poweron_reset_conditional(mipi, true);
>-}
>-EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
>-
>-#if IS_ENABLED(CONFIG_SPI)
>-
>-/**
>- * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
>- * @spi: SPI device
>- * @len: The transfer buffer length.
>- *
>- * Many controllers have a max speed of 10MHz, but can be pushed way beyond
>- * that. Increase reliability by running pixel data at max speed and the rest
>- * at 10MHz, preventing transfer glitches from messing up the init settings.
>- */
>-u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
>-{
>-	if (len > 64)
>-		return 0; /* use default */
>-
>-	return min_t(u32, 10000000, spi->max_speed_hz);
>-}
>-EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
>-
>-/*
>- * MIPI DBI Type C Option 1
>- *
>- * If the SPI controller doesn't have 9 bits per word support,
>- * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
>- * Pad partial blocks with MIPI_DCS_NOP (zero).
>- * This is how the D/C bit (x) is added:
>- *     x7654321
>- *     0x765432
>- *     10x76543
>- *     210x7654
>- *     3210x765
>- *     43210x76
>- *     543210x7
>- *     6543210x
>- *     76543210
>- */
>-
>-static int mipi_dbi_spi1e_transfer(struct mipi_dbi *mipi, int dc,
>-				   const void *buf, size_t len,
>-				   unsigned int bpw)
>-{
>-	bool swap_bytes = (bpw == 16 && tinydrm_machine_little_endian());
>-	size_t chunk, max_chunk = mipi->tx_buf9_len;
>-	struct spi_device *spi = mipi->spi;
>-	struct spi_transfer tr = {
>-		.tx_buf = mipi->tx_buf9,
>-		.bits_per_word = 8,
>-	};
>-	struct spi_message m;
>-	const u8 *src = buf;
>-	int i, ret;
>-	u8 *dst;
>-
>-	if (drm_debug & DRM_UT_DRIVER)
>-		pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
>-			 __func__, dc, max_chunk);
>-
>-	tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
>-	spi_message_init_with_transfers(&m, &tr, 1);
>-
>-	if (!dc) {
>-		if (WARN_ON_ONCE(len != 1))
>-			return -EINVAL;
>-
>-		/* Command: pad no-op's (zeroes) at beginning of block */
>-		dst = mipi->tx_buf9;
>-		memset(dst, 0, 9);
>-		dst[8] = *src;
>-		tr.len = 9;
>-
>-		tinydrm_dbg_spi_message(spi, &m);
>-
>-		return spi_sync(spi, &m);
>-	}
>-
>-	/* max with room for adding one bit per byte */
>-	max_chunk = max_chunk / 9 * 8;
>-	/* but no bigger than len */
>-	max_chunk = min(max_chunk, len);
>-	/* 8 byte blocks */
>-	max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
>-
>-	while (len) {
>-		size_t added = 0;
>-
>-		chunk = min(len, max_chunk);
>-		len -= chunk;
>-		dst = mipi->tx_buf9;
>-
>-		if (chunk < 8) {
>-			u8 val, carry = 0;
>-
>-			/* Data: pad no-op's (zeroes) at end of block */
>-			memset(dst, 0, 9);
>-
>-			if (swap_bytes) {
>-				for (i = 1; i < (chunk + 1); i++) {
>-					val = src[1];
>-					*dst++ = carry | BIT(8 - i) | (val >> i);
>-					carry = val << (8 - i);
>-					i++;
>-					val = src[0];
>-					*dst++ = carry | BIT(8 - i) | (val >> i);
>-					carry = val << (8 - i);
>-					src += 2;
>-				}
>-				*dst++ = carry;
>-			} else {
>-				for (i = 1; i < (chunk + 1); i++) {
>-					val = *src++;
>-					*dst++ = carry | BIT(8 - i) | (val >> i);
>-					carry = val << (8 - i);
>-				}
>-				*dst++ = carry;
>-			}
>-
>-			chunk = 8;
>-			added = 1;
>-		} else {
>-			for (i = 0; i < chunk; i += 8) {
>-				if (swap_bytes) {
>-					*dst++ =                 BIT(7) | (src[1] >> 1);
>-					*dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
>-					*dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
>-					*dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
>-					*dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
>-					*dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
>-					*dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
>-					*dst++ = (src[7] << 1) | BIT(0);
>-					*dst++ = src[6];
>-				} else {
>-					*dst++ =                 BIT(7) | (src[0] >> 1);
>-					*dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
>-					*dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
>-					*dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
>-					*dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
>-					*dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
>-					*dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
>-					*dst++ = (src[6] << 1) | BIT(0);
>-					*dst++ = src[7];
>-				}
>-
>-				src += 8;
>-				added++;
>-			}
>-		}
>-
>-		tr.len = chunk + added;
>-
>-		tinydrm_dbg_spi_message(spi, &m);
>-		ret = spi_sync(spi, &m);
>-		if (ret)
>-			return ret;
>-	}
>-
>-	return 0;
>-}
>-
>-static int mipi_dbi_spi1_transfer(struct mipi_dbi *mipi, int dc,
>-				  const void *buf, size_t len,
>-				  unsigned int bpw)
>-{
>-	struct spi_device *spi = mipi->spi;
>-	struct spi_transfer tr = {
>-		.bits_per_word = 9,
>-	};
>-	const u16 *src16 = buf;
>-	const u8 *src8 = buf;
>-	struct spi_message m;
>-	size_t max_chunk;
>-	u16 *dst16;
>-	int ret;
>-
>-	if (!tinydrm_spi_bpw_supported(spi, 9))
>-		return mipi_dbi_spi1e_transfer(mipi, dc, buf, len, bpw);
>-
>-	tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
>-	max_chunk = mipi->tx_buf9_len;
>-	dst16 = mipi->tx_buf9;
>-
>-	if (drm_debug & DRM_UT_DRIVER)
>-		pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
>-			 __func__, dc, max_chunk);
>-
>-	max_chunk = min(max_chunk / 2, len);
>-
>-	spi_message_init_with_transfers(&m, &tr, 1);
>-	tr.tx_buf = dst16;
>-
>-	while (len) {
>-		size_t chunk = min(len, max_chunk);
>-		unsigned int i;
>-
>-		if (bpw == 16 && tinydrm_machine_little_endian()) {
>-			for (i = 0; i < (chunk * 2); i += 2) {
>-				dst16[i]     = *src16 >> 8;
>-				dst16[i + 1] = *src16++ & 0xFF;
>-				if (dc) {
>-					dst16[i]     |= 0x0100;
>-					dst16[i + 1] |= 0x0100;
>-				}
>-			}
>-		} else {
>-			for (i = 0; i < chunk; i++) {
>-				dst16[i] = *src8++;
>-				if (dc)
>-					dst16[i] |= 0x0100;
>-			}
>-		}
>-
>-		tr.len = chunk;
>-		len -= chunk;
>-
>-		tinydrm_dbg_spi_message(spi, &m);
>-		ret = spi_sync(spi, &m);
>-		if (ret)
>-			return ret;
>-	}
>-
>-	return 0;
>-}
>-
>-static int mipi_dbi_typec1_command(struct mipi_dbi *mipi, u8 *cmd,
>-				   u8 *parameters, size_t num)
>-{
>-	unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;
>-	int ret;
>-
>-	if (mipi_dbi_command_is_read(mipi, *cmd))
>-		return -ENOTSUPP;
>-
>-	MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
>-
>-	ret = mipi_dbi_spi1_transfer(mipi, 0, cmd, 1, 8);
>-	if (ret || !num)
>-		return ret;
>-
>-	return mipi_dbi_spi1_transfer(mipi, 1, parameters, num, bpw);
>-}
>-
>-/* MIPI DBI Type C Option 3 */
>-
>-static int mipi_dbi_typec3_command_read(struct mipi_dbi *mipi, u8 *cmd,
>-					u8 *data, size_t len)
>-{
>-	struct spi_device *spi = mipi->spi;
>-	u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
>-			     spi->max_speed_hz / 2);
>-	struct spi_transfer tr[2] = {
>-		{
>-			.speed_hz = speed_hz,
>-			.tx_buf = cmd,
>-			.len = 1,
>-		}, {
>-			.speed_hz = speed_hz,
>-			.len = len,
>-		},
>-	};
>-	struct spi_message m;
>-	u8 *buf;
>-	int ret;
>-
>-	if (!len)
>-		return -EINVAL;
>-
>-	/*
>-	 * Support non-standard 24-bit and 32-bit Nokia read commands which
>-	 * start with a dummy clock, so we need to read an extra byte.
>-	 */
>-	if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
>-	    *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
>-		if (!(len == 3 || len == 4))
>-			return -EINVAL;
>-
>-		tr[1].len = len + 1;
>-	}
>-
>-	buf = kmalloc(tr[1].len, GFP_KERNEL);
>-	if (!buf)
>-		return -ENOMEM;
>-
>-	tr[1].rx_buf = buf;
>-	gpiod_set_value_cansleep(mipi->dc, 0);
>-
>-	spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
>-	ret = spi_sync(spi, &m);
>-	if (ret)
>-		goto err_free;
>-
>-	tinydrm_dbg_spi_message(spi, &m);
>-
>-	if (tr[1].len == len) {
>-		memcpy(data, buf, len);
>-	} else {
>-		unsigned int i;
>-
>-		for (i = 0; i < len; i++)
>-			data[i] = (buf[i] << 1) | !!(buf[i + 1] & BIT(7));
>-	}
>-
>-	MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
>-
>-err_free:
>-	kfree(buf);
>-
>-	return ret;
>-}
>-
>-static int mipi_dbi_typec3_command(struct mipi_dbi *mipi, u8 *cmd,
>-				   u8 *par, size_t num)
>-{
>-	struct spi_device *spi = mipi->spi;
>-	unsigned int bpw = 8;
>-	u32 speed_hz;
>-	int ret;
>-
>-	if (mipi_dbi_command_is_read(mipi, *cmd))
>-		return mipi_dbi_typec3_command_read(mipi, cmd, par, num);
>-
>-	MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
>-
>-	gpiod_set_value_cansleep(mipi->dc, 0);
>-	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
>-	ret = tinydrm_spi_transfer(spi, speed_hz, NULL, 8, cmd, 1);
>-	if (ret || !num)
>-		return ret;
>-
>-	if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !mipi->swap_bytes)
>-		bpw = 16;
>-
>-	gpiod_set_value_cansleep(mipi->dc, 1);
>-	speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
>-
>-	return tinydrm_spi_transfer(spi, speed_hz, NULL, bpw, par, num);
>-}
>-
>-/**
>- * mipi_dbi_spi_init - Initialize MIPI DBI SPI interfaced controller
>- * @spi: SPI device
>- * @mipi: &mipi_dbi structure to initialize
>- * @dc: D/C gpio (optional)
>- *
>- * This function sets &mipi_dbi->command, enables &mipi->read_commands for the
>- * usual read commands. It should be followed by a call to mipi_dbi_init() or
>- * a driver-specific init.
>- *
>- * If @dc is set, a Type C Option 3 interface is assumed, if not
>- * Type C Option 1.
>- *
>- * If the SPI master driver doesn't support the necessary bits per word,
>- * the following transformation is used:
>- *
>- * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command.
>- * - 16-bit: if big endian send as 8-bit, if little endian swap bytes
>- *
>- * Returns:
>- * Zero on success, negative error code on failure.
>- */
>-int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *mipi,
>-		      struct gpio_desc *dc)
>-{
>-	size_t tx_size = tinydrm_spi_max_transfer_size(spi, 0);
>-	struct device *dev = &spi->dev;
>-	int ret;
>-
>-	if (tx_size < 16) {
>-		DRM_ERROR("SPI transmit buffer too small: %zu\n", tx_size);
>-		return -EINVAL;
>-	}
>-
>-	/*
>-	 * Even though it's not the SPI device that does DMA (the master does),
>-	 * the dma mask is necessary for the dma_alloc_wc() in
>-	 * drm_gem_cma_create(). The dma_addr returned will be a physical
>-	 * address which might be different from the bus address, but this is
>-	 * not a problem since the address will not be used.
>-	 * The virtual address is used in the transfer and the SPI core
>-	 * re-maps it on the SPI master device using the DMA streaming API
>-	 * (spi_map_buf()).
>-	 */
>-	if (!dev->coherent_dma_mask) {
>-		ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
>-		if (ret) {
>-			dev_warn(dev, "Failed to set dma mask %d\n", ret);
>-			return ret;
>-		}
>-	}
>-
>-	mipi->spi = spi;
>-	mipi->read_commands = mipi_dbi_dcs_read_commands;
>-
>-	if (dc) {
>-		mipi->command = mipi_dbi_typec3_command;
>-		mipi->dc = dc;
>-		if (tinydrm_machine_little_endian() &&
>-		    !tinydrm_spi_bpw_supported(spi, 16))
>-			mipi->swap_bytes = true;
>-	} else {
>-		mipi->command = mipi_dbi_typec1_command;
>-		mipi->tx_buf9_len = tx_size;
>-		mipi->tx_buf9 = devm_kmalloc(dev, tx_size, GFP_KERNEL);
>-		if (!mipi->tx_buf9)
>-			return -ENOMEM;
>-	}
>-
>-	DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
>-
>-	return 0;
>-}
>-EXPORT_SYMBOL(mipi_dbi_spi_init);
>-
>-#endif /* CONFIG_SPI */
>-
>-#ifdef CONFIG_DEBUG_FS
>-
>-static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
>-					      const char __user *ubuf,
>-					      size_t count, loff_t *ppos)
>-{
>-	struct seq_file *m = file->private_data;
>-	struct mipi_dbi *mipi = m->private;
>-	u8 val, cmd = 0, parameters[64];
>-	char *buf, *pos, *token;
>-	unsigned int i;
>-	int ret, idx;
>-
>-	if (!drm_dev_enter(&mipi->drm, &idx))
>-		return -ENODEV;
>-
>-	buf = memdup_user_nul(ubuf, count);
>-	if (IS_ERR(buf)) {
>-		ret = PTR_ERR(buf);
>-		goto err_exit;
>-	}
>-
>-	/* strip trailing whitespace */
>-	for (i = count - 1; i > 0; i--)
>-		if (isspace(buf[i]))
>-			buf[i] = '\0';
>-		else
>-			break;
>-	i = 0;
>-	pos = buf;
>-	while (pos) {
>-		token = strsep(&pos, " ");
>-		if (!token) {
>-			ret = -EINVAL;
>-			goto err_free;
>-		}
>-
>-		ret = kstrtou8(token, 16, &val);
>-		if (ret < 0)
>-			goto err_free;
>-
>-		if (token == buf)
>-			cmd = val;
>-		else
>-			parameters[i++] = val;
>-
>-		if (i == 64) {
>-			ret = -E2BIG;
>-			goto err_free;
>-		}
>-	}
>-
>-	ret = mipi_dbi_command_buf(mipi, cmd, parameters, i);
>-
>-err_free:
>-	kfree(buf);
>-err_exit:
>-	drm_dev_exit(idx);
>-
>-	return ret < 0 ? ret : count;
>-}
>-
>-static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
>-{
>-	struct mipi_dbi *mipi = m->private;
>-	u8 cmd, val[4];
>-	int ret, idx;
>-	size_t len;
>-
>-	if (!drm_dev_enter(&mipi->drm, &idx))
>-		return -ENODEV;
>-
>-	for (cmd = 0; cmd < 255; cmd++) {
>-		if (!mipi_dbi_command_is_read(mipi, cmd))
>-			continue;
>-
>-		switch (cmd) {
>-		case MIPI_DCS_READ_MEMORY_START:
>-		case MIPI_DCS_READ_MEMORY_CONTINUE:
>-			len = 2;
>-			break;
>-		case MIPI_DCS_GET_DISPLAY_ID:
>-			len = 3;
>-			break;
>-		case MIPI_DCS_GET_DISPLAY_STATUS:
>-			len = 4;
>-			break;
>-		default:
>-			len = 1;
>-			break;
>-		}
>-
>-		seq_printf(m, "%02x: ", cmd);
>-		ret = mipi_dbi_command_buf(mipi, cmd, val, len);
>-		if (ret) {
>-			seq_puts(m, "XX\n");
>-			continue;
>-		}
>-		seq_printf(m, "%*phN\n", (int)len, val);
>-	}
>-
>-	drm_dev_exit(idx);
>-
>-	return 0;
>-}
>-
>-static int mipi_dbi_debugfs_command_open(struct inode *inode,
>-					 struct file *file)
>-{
>-	return single_open(file, mipi_dbi_debugfs_command_show,
>-			   inode->i_private);
>-}
>-
>-static const struct file_operations mipi_dbi_debugfs_command_fops = {
>-	.owner = THIS_MODULE,
>-	.open = mipi_dbi_debugfs_command_open,
>-	.read = seq_read,
>-	.llseek = seq_lseek,
>-	.release = single_release,
>-	.write = mipi_dbi_debugfs_command_write,
>-};
>-
>-/**
>- * mipi_dbi_debugfs_init - Create debugfs entries
>- * @minor: DRM minor
>- *
>- * This function creates a 'command' debugfs file for sending commands to the
>- * controller or getting the read command values.
>- * Drivers can use this as their &drm_driver->debugfs_init callback.
>- *
>- * Returns:
>- * Zero on success, negative error code on failure.
>- */
>-int mipi_dbi_debugfs_init(struct drm_minor *minor)
>-{
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(minor->dev);
>-	umode_t mode = S_IFREG | S_IWUSR;
>-
>-	if (mipi->read_commands)
>-		mode |= S_IRUGO;
>-	debugfs_create_file("command", mode, minor->debugfs_root, mipi,
>-			    &mipi_dbi_debugfs_command_fops);
>-
>-	return 0;
>-}
>-EXPORT_SYMBOL(mipi_dbi_debugfs_init);
>-
>-#endif
>-
>-MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/repaper.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/repaper.c
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/repaper.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/repaper.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,1165 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0-or-later
>-/*
>- * DRM driver for Pervasive Displays RePaper branded e-ink panels
>- *
>- * Copyright 2013-2017 Pervasive Displays, Inc.
>- * Copyright 2017 Noralf TrÃ¸nnes
>- *
>- * The driver supports:
>- * Material Film: Aurora Mb (V231)
>- * Driver IC: G2 (eTC)
>- *
>- * The controller code was taken from the userspace driver:
>- * https://github.com/repaper/gratis
>- */
>-
>-#include <linux/delay.h>
>-#include <linux/dma-buf.h>
>-#include <linux/gpio/consumer.h>
>-#include <linux/module.h>
>-#include <linux/of_device.h>
>-#include <linux/sched/clock.h>
>-#include <linux/spi/spi.h>
>-#include <linux/thermal.h>
>-
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_damage_helper.h>
>-#include <drm/drm_drv.h>
>-#include <drm/drm_fb_cma_helper.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_format_helper.h>
>-#include <drm/drm_gem_cma_helper.h>
>-#include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_rect.h>
>-#include <drm/drm_vblank.h>
>-#include <drm/drm_simple_kms_helper.h>
>-#include <drm/tinydrm/tinydrm-helpers.h>
>-
>-#define REPAPER_RID_G2_COG_ID	0x12
>-
>-enum repaper_model {
>-	E1144CS021 = 1,
>-	E1190CS021,
>-	E2200CS021,
>-	E2271CS021,
>-};
>-
>-enum repaper_stage {         /* Image pixel -> Display pixel */
>-	REPAPER_COMPENSATE,  /* B -> W, W -> B (Current Image) */
>-	REPAPER_WHITE,       /* B -> N, W -> W (Current Image) */
>-	REPAPER_INVERSE,     /* B -> N, W -> B (New Image) */
>-	REPAPER_NORMAL       /* B -> B, W -> W (New Image) */
>-};
>-
>-enum repaper_epd_border_byte {
>-	REPAPER_BORDER_BYTE_NONE,
>-	REPAPER_BORDER_BYTE_ZERO,
>-	REPAPER_BORDER_BYTE_SET,
>-};
>-
>-struct repaper_epd {
>-	struct drm_device drm;
>-	struct drm_simple_display_pipe pipe;
>-	struct spi_device *spi;
>-
>-	struct gpio_desc *panel_on;
>-	struct gpio_desc *border;
>-	struct gpio_desc *discharge;
>-	struct gpio_desc *reset;
>-	struct gpio_desc *busy;
>-
>-	struct thermal_zone_device *thermal;
>-
>-	unsigned int height;
>-	unsigned int width;
>-	unsigned int bytes_per_scan;
>-	const u8 *channel_select;
>-	unsigned int stage_time;
>-	unsigned int factored_stage_time;
>-	bool middle_scan;
>-	bool pre_border_byte;
>-	enum repaper_epd_border_byte border_byte;
>-
>-	u8 *line_buffer;
>-	void *current_frame;
>-
>-	bool enabled;
>-	bool cleared;
>-	bool partial;
>-};
>-
>-static inline struct repaper_epd *drm_to_epd(struct drm_device *drm)
>-{
>-	return container_of(drm, struct repaper_epd, drm);
>-}
>-
>-static int repaper_spi_transfer(struct spi_device *spi, u8 header,
>-				const void *tx, void *rx, size_t len)
>-{
>-	void *txbuf = NULL, *rxbuf = NULL;
>-	struct spi_transfer tr[2] = {};
>-	u8 *headerbuf;
>-	int ret;
>-
>-	headerbuf = kmalloc(1, GFP_KERNEL);
>-	if (!headerbuf)
>-		return -ENOMEM;
>-
>-	headerbuf[0] = header;
>-	tr[0].tx_buf = headerbuf;
>-	tr[0].len = 1;
>-
>-	/* Stack allocated tx? */
>-	if (tx && len <= 32) {
>-		txbuf = kmemdup(tx, len, GFP_KERNEL);
>-		if (!txbuf) {
>-			ret = -ENOMEM;
>-			goto out_free;
>-		}
>-	}
>-
>-	if (rx) {
>-		rxbuf = kmalloc(len, GFP_KERNEL);
>-		if (!rxbuf) {
>-			ret = -ENOMEM;
>-			goto out_free;
>-		}
>-	}
>-
>-	tr[1].tx_buf = txbuf ? txbuf : tx;
>-	tr[1].rx_buf = rxbuf;
>-	tr[1].len = len;
>-
>-	ndelay(80);
>-	ret = spi_sync_transfer(spi, tr, 2);
>-	if (rx && !ret)
>-		memcpy(rx, rxbuf, len);
>-
>-out_free:
>-	kfree(headerbuf);
>-	kfree(txbuf);
>-	kfree(rxbuf);
>-
>-	return ret;
>-}
>-
>-static int repaper_write_buf(struct spi_device *spi, u8 reg,
>-			     const u8 *buf, size_t len)
>-{
>-	int ret;
>-
>-	ret = repaper_spi_transfer(spi, 0x70, &reg, NULL, 1);
>-	if (ret)
>-		return ret;
>-
>-	return repaper_spi_transfer(spi, 0x72, buf, NULL, len);
>-}
>-
>-static int repaper_write_val(struct spi_device *spi, u8 reg, u8 val)
>-{
>-	return repaper_write_buf(spi, reg, &val, 1);
>-}
>-
>-static int repaper_read_val(struct spi_device *spi, u8 reg)
>-{
>-	int ret;
>-	u8 val;
>-
>-	ret = repaper_spi_transfer(spi, 0x70, &reg, NULL, 1);
>-	if (ret)
>-		return ret;
>-
>-	ret = repaper_spi_transfer(spi, 0x73, NULL, &val, 1);
>-
>-	return ret ? ret : val;
>-}
>-
>-static int repaper_read_id(struct spi_device *spi)
>-{
>-	int ret;
>-	u8 id;
>-
>-	ret = repaper_spi_transfer(spi, 0x71, NULL, &id, 1);
>-
>-	return ret ? ret : id;
>-}
>-
>-static void repaper_spi_mosi_low(struct spi_device *spi)
>-{
>-	const u8 buf[1] = { 0 };
>-
>-	spi_write(spi, buf, 1);
>-}
>-
>-/* pixels on display are numbered from 1 so even is actually bits 1,3,5,... */
>-static void repaper_even_pixels(struct repaper_epd *epd, u8 **pp,
>-				const u8 *data, u8 fixed_value, const u8 *mask,
>-				enum repaper_stage stage)
>-{
>-	unsigned int b;
>-
>-	for (b = 0; b < (epd->width / 8); b++) {
>-		if (data) {
>-			u8 pixels = data[b] & 0xaa;
>-			u8 pixel_mask = 0xff;
>-			u8 p1, p2, p3, p4;
>-
>-			if (mask) {
>-				pixel_mask = (mask[b] ^ pixels) & 0xaa;
>-				pixel_mask |= pixel_mask >> 1;
>-			}
>-
>-			switch (stage) {
>-			case REPAPER_COMPENSATE: /* B -> W, W -> B (Current) */
>-				pixels = 0xaa | ((pixels ^ 0xaa) >> 1);
>-				break;
>-			case REPAPER_WHITE:      /* B -> N, W -> W (Current) */
>-				pixels = 0x55 + ((pixels ^ 0xaa) >> 1);
>-				break;
>-			case REPAPER_INVERSE:    /* B -> N, W -> B (New) */
>-				pixels = 0x55 | (pixels ^ 0xaa);
>-				break;
>-			case REPAPER_NORMAL:     /* B -> B, W -> W (New) */
>-				pixels = 0xaa | (pixels >> 1);
>-				break;
>-			}
>-
>-			pixels = (pixels & pixel_mask) | (~pixel_mask & 0x55);
>-			p1 = (pixels >> 6) & 0x03;
>-			p2 = (pixels >> 4) & 0x03;
>-			p3 = (pixels >> 2) & 0x03;
>-			p4 = (pixels >> 0) & 0x03;
>-			pixels = (p1 << 0) | (p2 << 2) | (p3 << 4) | (p4 << 6);
>-			*(*pp)++ = pixels;
>-		} else {
>-			*(*pp)++ = fixed_value;
>-		}
>-	}
>-}
>-
>-/* pixels on display are numbered from 1 so odd is actually bits 0,2,4,... */
>-static void repaper_odd_pixels(struct repaper_epd *epd, u8 **pp,
>-			       const u8 *data, u8 fixed_value, const u8 *mask,
>-			       enum repaper_stage stage)
>-{
>-	unsigned int b;
>-
>-	for (b = epd->width / 8; b > 0; b--) {
>-		if (data) {
>-			u8 pixels = data[b - 1] & 0x55;
>-			u8 pixel_mask = 0xff;
>-
>-			if (mask) {
>-				pixel_mask = (mask[b - 1] ^ pixels) & 0x55;
>-				pixel_mask |= pixel_mask << 1;
>-			}
>-
>-			switch (stage) {
>-			case REPAPER_COMPENSATE: /* B -> W, W -> B (Current) */
>-				pixels = 0xaa | (pixels ^ 0x55);
>-				break;
>-			case REPAPER_WHITE:      /* B -> N, W -> W (Current) */
>-				pixels = 0x55 + (pixels ^ 0x55);
>-				break;
>-			case REPAPER_INVERSE:    /* B -> N, W -> B (New) */
>-				pixels = 0x55 | ((pixels ^ 0x55) << 1);
>-				break;
>-			case REPAPER_NORMAL:     /* B -> B, W -> W (New) */
>-				pixels = 0xaa | pixels;
>-				break;
>-			}
>-
>-			pixels = (pixels & pixel_mask) | (~pixel_mask & 0x55);
>-			*(*pp)++ = pixels;
>-		} else {
>-			*(*pp)++ = fixed_value;
>-		}
>-	}
>-}
>-
>-/* interleave bits: (byte)76543210 -> (16 bit).7.6.5.4.3.2.1 */
>-static inline u16 repaper_interleave_bits(u16 value)
>-{
>-	value = (value | (value << 4)) & 0x0f0f;
>-	value = (value | (value << 2)) & 0x3333;
>-	value = (value | (value << 1)) & 0x5555;
>-
>-	return value;
>-}
>-
>-/* pixels on display are numbered from 1 */
>-static void repaper_all_pixels(struct repaper_epd *epd, u8 **pp,
>-			       const u8 *data, u8 fixed_value, const u8 *mask,
>-			       enum repaper_stage stage)
>-{
>-	unsigned int b;
>-
>-	for (b = epd->width / 8; b > 0; b--) {
>-		if (data) {
>-			u16 pixels = repaper_interleave_bits(data[b - 1]);
>-			u16 pixel_mask = 0xffff;
>-
>-			if (mask) {
>-				pixel_mask = repaper_interleave_bits(mask[b - 1]);
>-
>-				pixel_mask = (pixel_mask ^ pixels) & 0x5555;
>-				pixel_mask |= pixel_mask << 1;
>-			}
>-
>-			switch (stage) {
>-			case REPAPER_COMPENSATE: /* B -> W, W -> B (Current) */
>-				pixels = 0xaaaa | (pixels ^ 0x5555);
>-				break;
>-			case REPAPER_WHITE:      /* B -> N, W -> W (Current) */
>-				pixels = 0x5555 + (pixels ^ 0x5555);
>-				break;
>-			case REPAPER_INVERSE:    /* B -> N, W -> B (New) */
>-				pixels = 0x5555 | ((pixels ^ 0x5555) << 1);
>-				break;
>-			case REPAPER_NORMAL:     /* B -> B, W -> W (New) */
>-				pixels = 0xaaaa | pixels;
>-				break;
>-			}
>-
>-			pixels = (pixels & pixel_mask) | (~pixel_mask & 0x5555);
>-			*(*pp)++ = pixels >> 8;
>-			*(*pp)++ = pixels;
>-		} else {
>-			*(*pp)++ = fixed_value;
>-			*(*pp)++ = fixed_value;
>-		}
>-	}
>-}
>-
>-/* output one line of scan and data bytes to the display */
>-static void repaper_one_line(struct repaper_epd *epd, unsigned int line,
>-			     const u8 *data, u8 fixed_value, const u8 *mask,
>-			     enum repaper_stage stage)
>-{
>-	u8 *p = epd->line_buffer;
>-	unsigned int b;
>-
>-	repaper_spi_mosi_low(epd->spi);
>-
>-	if (epd->pre_border_byte)
>-		*p++ = 0x00;
>-
>-	if (epd->middle_scan) {
>-		/* data bytes */
>-		repaper_odd_pixels(epd, &p, data, fixed_value, mask, stage);
>-
>-		/* scan line */
>-		for (b = epd->bytes_per_scan; b > 0; b--) {
>-			if (line / 4 == b - 1)
>-				*p++ = 0x03 << (2 * (line & 0x03));
>-			else
>-				*p++ = 0x00;
>-		}
>-
>-		/* data bytes */
>-		repaper_even_pixels(epd, &p, data, fixed_value, mask, stage);
>-	} else {
>-		/*
>-		 * even scan line, but as lines on display are numbered from 1,
>-		 * line: 1,3,5,...
>-		 */
>-		for (b = 0; b < epd->bytes_per_scan; b++) {
>-			if (0 != (line & 0x01) && line / 8 == b)
>-				*p++ = 0xc0 >> (line & 0x06);
>-			else
>-				*p++ = 0x00;
>-		}
>-
>-		/* data bytes */
>-		repaper_all_pixels(epd, &p, data, fixed_value, mask, stage);
>-
>-		/*
>-		 * odd scan line, but as lines on display are numbered from 1,
>-		 * line: 0,2,4,6,...
>-		 */
>-		for (b = epd->bytes_per_scan; b > 0; b--) {
>-			if (0 == (line & 0x01) && line / 8 == b - 1)
>-				*p++ = 0x03 << (line & 0x06);
>-			else
>-				*p++ = 0x00;
>-		}
>-	}
>-
>-	switch (epd->border_byte) {
>-	case REPAPER_BORDER_BYTE_NONE:
>-		break;
>-
>-	case REPAPER_BORDER_BYTE_ZERO:
>-		*p++ = 0x00;
>-		break;
>-
>-	case REPAPER_BORDER_BYTE_SET:
>-		switch (stage) {
>-		case REPAPER_COMPENSATE:
>-		case REPAPER_WHITE:
>-		case REPAPER_INVERSE:
>-			*p++ = 0x00;
>-			break;
>-		case REPAPER_NORMAL:
>-			*p++ = 0xaa;
>-			break;
>-		}
>-		break;
>-	}
>-
>-	repaper_write_buf(epd->spi, 0x0a, epd->line_buffer,
>-			  p - epd->line_buffer);
>-
>-	/* Output data to panel */
>-	repaper_write_val(epd->spi, 0x02, 0x07);
>-
>-	repaper_spi_mosi_low(epd->spi);
>-}
>-
>-static void repaper_frame_fixed(struct repaper_epd *epd, u8 fixed_value,
>-				enum repaper_stage stage)
>-{
>-	unsigned int line;
>-
>-	for (line = 0; line < epd->height; line++)
>-		repaper_one_line(epd, line, NULL, fixed_value, NULL, stage);
>-}
>-
>-static void repaper_frame_data(struct repaper_epd *epd, const u8 *image,
>-			       const u8 *mask, enum repaper_stage stage)
>-{
>-	unsigned int line;
>-
>-	if (!mask) {
>-		for (line = 0; line < epd->height; line++) {
>-			repaper_one_line(epd, line,
>-					 &image[line * (epd->width / 8)],
>-					 0, NULL, stage);
>-		}
>-	} else {
>-		for (line = 0; line < epd->height; line++) {
>-			size_t n = line * epd->width / 8;
>-
>-			repaper_one_line(epd, line, &image[n], 0, &mask[n],
>-					 stage);
>-		}
>-	}
>-}
>-
>-static void repaper_frame_fixed_repeat(struct repaper_epd *epd, u8 fixed_value,
>-				       enum repaper_stage stage)
>-{
>-	u64 start = local_clock();
>-	u64 end = start + (epd->factored_stage_time * 1000 * 1000);
>-
>-	do {
>-		repaper_frame_fixed(epd, fixed_value, stage);
>-	} while (local_clock() < end);
>-}
>-
>-static void repaper_frame_data_repeat(struct repaper_epd *epd, const u8 *image,
>-				      const u8 *mask, enum repaper_stage stage)
>-{
>-	u64 start = local_clock();
>-	u64 end = start + (epd->factored_stage_time * 1000 * 1000);
>-
>-	do {
>-		repaper_frame_data(epd, image, mask, stage);
>-	} while (local_clock() < end);
>-}
>-
>-static void repaper_get_temperature(struct repaper_epd *epd)
>-{
>-	int ret, temperature = 0;
>-	unsigned int factor10x;
>-
>-	if (!epd->thermal)
>-		return;
>-
>-	ret = thermal_zone_get_temp(epd->thermal, &temperature);
>-	if (ret) {
>-		DRM_DEV_ERROR(&epd->spi->dev, "Failed to get temperature (%d)\n", ret);
>-		return;
>-	}
>-
>-	temperature /= 1000;
>-
>-	if (temperature <= -10)
>-		factor10x = 170;
>-	else if (temperature <= -5)
>-		factor10x = 120;
>-	else if (temperature <= 5)
>-		factor10x = 80;
>-	else if (temperature <= 10)
>-		factor10x = 40;
>-	else if (temperature <= 15)
>-		factor10x = 30;
>-	else if (temperature <= 20)
>-		factor10x = 20;
>-	else if (temperature <= 40)
>-		factor10x = 10;
>-	else
>-		factor10x = 7;
>-
>-	epd->factored_stage_time = epd->stage_time * factor10x / 10;
>-}
>-
>-static void repaper_gray8_to_mono_reversed(u8 *buf, u32 width, u32 height)
>-{
>-	u8 *gray8 = buf, *mono = buf;
>-	int y, xb, i;
>-
>-	for (y = 0; y < height; y++)
>-		for (xb = 0; xb < width / 8; xb++) {
>-			u8 byte = 0x00;
>-
>-			for (i = 0; i < 8; i++) {
>-				int x = xb * 8 + i;
>-
>-				byte >>= 1;
>-				if (gray8[y * width + x] >> 7)
>-					byte |= BIT(7);
>-			}
>-			*mono++ = byte;
>-		}
>-}
>-
>-static int repaper_fb_dirty(struct drm_framebuffer *fb)
>-{
>-	struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
>-	struct dma_buf_attachment *import_attach = cma_obj->base.import_attach;
>-	struct repaper_epd *epd = drm_to_epd(fb->dev);
>-	struct drm_rect clip;
>-	int idx, ret = 0;
>-	u8 *buf = NULL;
>-
>-	if (!epd->enabled)
>-		return 0;
>-
>-	if (!drm_dev_enter(fb->dev, &idx))
>-		return -ENODEV;
>-
>-	/* repaper can't do partial updates */
>-	clip.x1 = 0;
>-	clip.x2 = fb->width;
>-	clip.y1 = 0;
>-	clip.y2 = fb->height;
>-
>-	repaper_get_temperature(epd);
>-
>-	DRM_DEBUG("Flushing [FB:%d] st=%ums\n", fb->base.id,
>-		  epd->factored_stage_time);
>-
>-	buf = kmalloc_array(fb->width, fb->height, GFP_KERNEL);
>-	if (!buf) {
>-		ret = -ENOMEM;
>-		goto out_exit;
>-	}
>-
>-	if (import_attach) {
>-		ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
>-					       DMA_FROM_DEVICE);
>-		if (ret)
>-			goto out_free;
>-	}
>-
>-	drm_fb_xrgb8888_to_gray8(buf, cma_obj->vaddr, fb, &clip);
>-
>-	if (import_attach) {
>-		ret = dma_buf_end_cpu_access(import_attach->dmabuf,
>-					     DMA_FROM_DEVICE);
>-		if (ret)
>-			goto out_free;
>-	}
>-
>-	repaper_gray8_to_mono_reversed(buf, fb->width, fb->height);
>-
>-	if (epd->partial) {
>-		repaper_frame_data_repeat(epd, buf, epd->current_frame,
>-					  REPAPER_NORMAL);
>-	} else if (epd->cleared) {
>-		repaper_frame_data_repeat(epd, epd->current_frame, NULL,
>-					  REPAPER_COMPENSATE);
>-		repaper_frame_data_repeat(epd, epd->current_frame, NULL,
>-					  REPAPER_WHITE);
>-		repaper_frame_data_repeat(epd, buf, NULL, REPAPER_INVERSE);
>-		repaper_frame_data_repeat(epd, buf, NULL, REPAPER_NORMAL);
>-
>-		epd->partial = true;
>-	} else {
>-		/* Clear display (anything -> white) */
>-		repaper_frame_fixed_repeat(epd, 0xff, REPAPER_COMPENSATE);
>-		repaper_frame_fixed_repeat(epd, 0xff, REPAPER_WHITE);
>-		repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_INVERSE);
>-		repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_NORMAL);
>-
>-		/* Assuming a clear (white) screen output an image */
>-		repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_COMPENSATE);
>-		repaper_frame_fixed_repeat(epd, 0xaa, REPAPER_WHITE);
>-		repaper_frame_data_repeat(epd, buf, NULL, REPAPER_INVERSE);
>-		repaper_frame_data_repeat(epd, buf, NULL, REPAPER_NORMAL);
>-
>-		epd->cleared = true;
>-		epd->partial = true;
>-	}
>-
>-	memcpy(epd->current_frame, buf, fb->width * fb->height / 8);
>-
>-	/*
>-	 * An extra frame write is needed if pixels are set in the bottom line,
>-	 * or else grey lines rises up from the pixels
>-	 */
>-	if (epd->pre_border_byte) {
>-		unsigned int x;
>-
>-		for (x = 0; x < (fb->width / 8); x++)
>-			if (buf[x + (fb->width * (fb->height - 1) / 8)]) {
>-				repaper_frame_data_repeat(epd, buf,
>-							  epd->current_frame,
>-							  REPAPER_NORMAL);
>-				break;
>-			}
>-	}
>-
>-out_free:
>-	kfree(buf);
>-out_exit:
>-	drm_dev_exit(idx);
>-
>-	return ret;
>-}
>-
>-static void power_off(struct repaper_epd *epd)
>-{
>-	/* Turn off power and all signals */
>-	gpiod_set_value_cansleep(epd->reset, 0);
>-	gpiod_set_value_cansleep(epd->panel_on, 0);
>-	if (epd->border)
>-		gpiod_set_value_cansleep(epd->border, 0);
>-
>-	/* Ensure SPI MOSI and CLOCK are Low before CS Low */
>-	repaper_spi_mosi_low(epd->spi);
>-
>-	/* Discharge pulse */
>-	gpiod_set_value_cansleep(epd->discharge, 1);
>-	msleep(150);
>-	gpiod_set_value_cansleep(epd->discharge, 0);
>-}
>-
>-static void repaper_pipe_enable(struct drm_simple_display_pipe *pipe,
>-				struct drm_crtc_state *crtc_state,
>-				struct drm_plane_state *plane_state)
>-{
>-	struct repaper_epd *epd = drm_to_epd(pipe->crtc.dev);
>-	struct spi_device *spi = epd->spi;
>-	struct device *dev = &spi->dev;
>-	bool dc_ok = false;
>-	int i, ret, idx;
>-
>-	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>-		return;
>-
>-	DRM_DEBUG_DRIVER("\n");
>-
>-	/* Power up sequence */
>-	gpiod_set_value_cansleep(epd->reset, 0);
>-	gpiod_set_value_cansleep(epd->panel_on, 0);
>-	gpiod_set_value_cansleep(epd->discharge, 0);
>-	if (epd->border)
>-		gpiod_set_value_cansleep(epd->border, 0);
>-	repaper_spi_mosi_low(spi);
>-	usleep_range(5000, 10000);
>-
>-	gpiod_set_value_cansleep(epd->panel_on, 1);
>-	/*
>-	 * This delay comes from the repaper.org userspace driver, it's not
>-	 * mentioned in the datasheet.
>-	 */
>-	usleep_range(10000, 15000);
>-	gpiod_set_value_cansleep(epd->reset, 1);
>-	if (epd->border)
>-		gpiod_set_value_cansleep(epd->border, 1);
>-	usleep_range(5000, 10000);
>-	gpiod_set_value_cansleep(epd->reset, 0);
>-	usleep_range(5000, 10000);
>-	gpiod_set_value_cansleep(epd->reset, 1);
>-	usleep_range(5000, 10000);
>-
>-	/* Wait for COG to become ready */
>-	for (i = 100; i > 0; i--) {
>-		if (!gpiod_get_value_cansleep(epd->busy))
>-			break;
>-
>-		usleep_range(10, 100);
>-	}
>-
>-	if (!i) {
>-		DRM_DEV_ERROR(dev, "timeout waiting for panel to become ready.\n");
>-		power_off(epd);
>-		goto out_exit;
>-	}
>-
>-	repaper_read_id(spi);
>-	ret = repaper_read_id(spi);
>-	if (ret != REPAPER_RID_G2_COG_ID) {
>-		if (ret < 0)
>-			dev_err(dev, "failed to read chip (%d)\n", ret);
>-		else
>-			dev_err(dev, "wrong COG ID 0x%02x\n", ret);
>-		power_off(epd);
>-		goto out_exit;
>-	}
>-
>-	/* Disable OE */
>-	repaper_write_val(spi, 0x02, 0x40);
>-
>-	ret = repaper_read_val(spi, 0x0f);
>-	if (ret < 0 || !(ret & 0x80)) {
>-		if (ret < 0)
>-			DRM_DEV_ERROR(dev, "failed to read chip (%d)\n", ret);
>-		else
>-			DRM_DEV_ERROR(dev, "panel is reported broken\n");
>-		power_off(epd);
>-		goto out_exit;
>-	}
>-
>-	/* Power saving mode */
>-	repaper_write_val(spi, 0x0b, 0x02);
>-	/* Channel select */
>-	repaper_write_buf(spi, 0x01, epd->channel_select, 8);
>-	/* High power mode osc */
>-	repaper_write_val(spi, 0x07, 0xd1);
>-	/* Power setting */
>-	repaper_write_val(spi, 0x08, 0x02);
>-	/* Vcom level */
>-	repaper_write_val(spi, 0x09, 0xc2);
>-	/* Power setting */
>-	repaper_write_val(spi, 0x04, 0x03);
>-	/* Driver latch on */
>-	repaper_write_val(spi, 0x03, 0x01);
>-	/* Driver latch off */
>-	repaper_write_val(spi, 0x03, 0x00);
>-	usleep_range(5000, 10000);
>-
>-	/* Start chargepump */
>-	for (i = 0; i < 4; ++i) {
>-		/* Charge pump positive voltage on - VGH/VDL on */
>-		repaper_write_val(spi, 0x05, 0x01);
>-		msleep(240);
>-
>-		/* Charge pump negative voltage on - VGL/VDL on */
>-		repaper_write_val(spi, 0x05, 0x03);
>-		msleep(40);
>-
>-		/* Charge pump Vcom on - Vcom driver on */
>-		repaper_write_val(spi, 0x05, 0x0f);
>-		msleep(40);
>-
>-		/* check DC/DC */
>-		ret = repaper_read_val(spi, 0x0f);
>-		if (ret < 0) {
>-			DRM_DEV_ERROR(dev, "failed to read chip (%d)\n", ret);
>-			power_off(epd);
>-			goto out_exit;
>-		}
>-
>-		if (ret & 0x40) {
>-			dc_ok = true;
>-			break;
>-		}
>-	}
>-
>-	if (!dc_ok) {
>-		DRM_DEV_ERROR(dev, "dc/dc failed\n");
>-		power_off(epd);
>-		goto out_exit;
>-	}
>-
>-	/*
>-	 * Output enable to disable
>-	 * The userspace driver sets this to 0x04, but the datasheet says 0x06
>-	 */
>-	repaper_write_val(spi, 0x02, 0x04);
>-
>-	epd->enabled = true;
>-	epd->partial = false;
>-out_exit:
>-	drm_dev_exit(idx);
>-}
>-
>-static void repaper_pipe_disable(struct drm_simple_display_pipe *pipe)
>-{
>-	struct repaper_epd *epd = drm_to_epd(pipe->crtc.dev);
>-	struct spi_device *spi = epd->spi;
>-	unsigned int line;
>-
>-	/*
>-	 * This callback is not protected by drm_dev_enter/exit since we want to
>-	 * turn off the display on regular driver unload. It's highly unlikely
>-	 * that the underlying SPI controller is gone should this be called after
>-	 * unplug.
>-	 */
>-
>-	if (!epd->enabled)
>-		return;
>-
>-	DRM_DEBUG_DRIVER("\n");
>-
>-	epd->enabled = false;
>-
>-	/* Nothing frame */
>-	for (line = 0; line < epd->height; line++)
>-		repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL,
>-				 REPAPER_COMPENSATE);
>-
>-	/* 2.7" */
>-	if (epd->border) {
>-		/* Dummy line */
>-		repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL,
>-				 REPAPER_COMPENSATE);
>-		msleep(25);
>-		gpiod_set_value_cansleep(epd->border, 0);
>-		msleep(200);
>-		gpiod_set_value_cansleep(epd->border, 1);
>-	} else {
>-		/* Border dummy line */
>-		repaper_one_line(epd, 0x7fffu, NULL, 0x00, NULL,
>-				 REPAPER_NORMAL);
>-		msleep(200);
>-	}
>-
>-	/* not described in datasheet */
>-	repaper_write_val(spi, 0x0b, 0x00);
>-	/* Latch reset turn on */
>-	repaper_write_val(spi, 0x03, 0x01);
>-	/* Power off charge pump Vcom */
>-	repaper_write_val(spi, 0x05, 0x03);
>-	/* Power off charge pump neg voltage */
>-	repaper_write_val(spi, 0x05, 0x01);
>-	msleep(120);
>-	/* Discharge internal */
>-	repaper_write_val(spi, 0x04, 0x80);
>-	/* turn off all charge pumps */
>-	repaper_write_val(spi, 0x05, 0x00);
>-	/* Turn off osc */
>-	repaper_write_val(spi, 0x07, 0x01);
>-	msleep(50);
>-
>-	power_off(epd);
>-}
>-
>-static void repaper_pipe_update(struct drm_simple_display_pipe *pipe,
>-				struct drm_plane_state *old_state)
>-{
>-	struct drm_plane_state *state = pipe->plane.state;
>-	struct drm_crtc *crtc = &pipe->crtc;
>-	struct drm_rect rect;
>-
>-	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
>-		repaper_fb_dirty(state->fb);
>-
>-	if (crtc->state->event) {
>-		spin_lock_irq(&crtc->dev->event_lock);
>-		drm_crtc_send_vblank_event(crtc, crtc->state->event);
>-		spin_unlock_irq(&crtc->dev->event_lock);
>-		crtc->state->event = NULL;
>-	}
>-}
>-
>-static const struct drm_simple_display_pipe_funcs repaper_pipe_funcs = {
>-	.enable = repaper_pipe_enable,
>-	.disable = repaper_pipe_disable,
>-	.update = repaper_pipe_update,
>-	.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
>-};
>-
>-static const struct drm_mode_config_funcs repaper_mode_config_funcs = {
>-	.fb_create = drm_gem_fb_create_with_dirty,
>-	.atomic_check = drm_atomic_helper_check,
>-	.atomic_commit = drm_atomic_helper_commit,
>-};
>-
>-static void repaper_release(struct drm_device *drm)
>-{
>-	struct repaper_epd *epd = drm_to_epd(drm);
>-
>-	DRM_DEBUG_DRIVER("\n");
>-
>-	drm_mode_config_cleanup(drm);
>-	drm_dev_fini(drm);
>-	kfree(epd);
>-}
>-
>-static const uint32_t repaper_formats[] = {
>-	DRM_FORMAT_XRGB8888,
>-};
>-
>-static const struct drm_display_mode repaper_e1144cs021_mode = {
>-	DRM_SIMPLE_MODE(128, 96, 29, 22),
>-};
>-
>-static const u8 repaper_e1144cs021_cs[] = { 0x00, 0x00, 0x00, 0x00,
>-					    0x00, 0x0f, 0xff, 0x00 };
>-
>-static const struct drm_display_mode repaper_e1190cs021_mode = {
>-	DRM_SIMPLE_MODE(144, 128, 36, 32),
>-};
>-
>-static const u8 repaper_e1190cs021_cs[] = { 0x00, 0x00, 0x00, 0x03,
>-					    0xfc, 0x00, 0x00, 0xff };
>-
>-static const struct drm_display_mode repaper_e2200cs021_mode = {
>-	DRM_SIMPLE_MODE(200, 96, 46, 22),
>-};
>-
>-static const u8 repaper_e2200cs021_cs[] = { 0x00, 0x00, 0x00, 0x00,
>-					    0x01, 0xff, 0xe0, 0x00 };
>-
>-static const struct drm_display_mode repaper_e2271cs021_mode = {
>-	DRM_SIMPLE_MODE(264, 176, 57, 38),
>-};
>-
>-static const u8 repaper_e2271cs021_cs[] = { 0x00, 0x00, 0x00, 0x7f,
>-					    0xff, 0xfe, 0x00, 0x00 };
>-
>-DEFINE_DRM_GEM_CMA_FOPS(repaper_fops);
>-
>-static struct drm_driver repaper_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
>-				  DRIVER_ATOMIC,
>-	.fops			= &repaper_fops,
>-	.release		= repaper_release,
>-	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>-	.name			= "repaper",
>-	.desc			= "Pervasive Displays RePaper e-ink panels",
>-	.date			= "20170405",
>-	.major			= 1,
>-	.minor			= 0,
>-};
>-
>-static const struct of_device_id repaper_of_match[] = {
>-	{ .compatible = "pervasive,e1144cs021", .data = (void *)E1144CS021 },
>-	{ .compatible = "pervasive,e1190cs021", .data = (void *)E1190CS021 },
>-	{ .compatible = "pervasive,e2200cs021", .data = (void *)E2200CS021 },
>-	{ .compatible = "pervasive,e2271cs021", .data = (void *)E2271CS021 },
>-	{},
>-};
>-MODULE_DEVICE_TABLE(of, repaper_of_match);
>-
>-static const struct spi_device_id repaper_id[] = {
>-	{ "e1144cs021", E1144CS021 },
>-	{ "e1190cs021", E1190CS021 },
>-	{ "e2200cs021", E2200CS021 },
>-	{ "e2271cs021", E2271CS021 },
>-	{ },
>-};
>-MODULE_DEVICE_TABLE(spi, repaper_id);
>-
>-static int repaper_probe(struct spi_device *spi)
>-{
>-	const struct drm_display_mode *mode;
>-	const struct spi_device_id *spi_id;
>-	const struct of_device_id *match;
>-	struct device *dev = &spi->dev;
>-	enum repaper_model model;
>-	const char *thermal_zone;
>-	struct repaper_epd *epd;
>-	size_t line_buffer_size;
>-	struct drm_device *drm;
>-	int ret;
>-
>-	match = of_match_device(repaper_of_match, dev);
>-	if (match) {
>-		model = (enum repaper_model)match->data;
>-	} else {
>-		spi_id = spi_get_device_id(spi);
>-		model = spi_id->driver_data;
>-	}
>-
>-	/* The SPI device is used to allocate dma memory */
>-	if (!dev->coherent_dma_mask) {
>-		ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
>-		if (ret) {
>-			dev_warn(dev, "Failed to set dma mask %d\n", ret);
>-			return ret;
>-		}
>-	}
>-
>-	epd = kzalloc(sizeof(*epd), GFP_KERNEL);
>-	if (!epd)
>-		return -ENOMEM;
>-
>-	drm = &epd->drm;
>-
>-	ret = devm_drm_dev_init(dev, drm, &repaper_driver);
>-	if (ret) {
>-		kfree(epd);
>-		return ret;
>-	}
>-
>-	drm_mode_config_init(drm);
>-	drm->mode_config.funcs = &repaper_mode_config_funcs;
>-
>-	epd->spi = spi;
>-
>-	epd->panel_on = devm_gpiod_get(dev, "panel-on", GPIOD_OUT_LOW);
>-	if (IS_ERR(epd->panel_on)) {
>-		ret = PTR_ERR(epd->panel_on);
>-		if (ret != -EPROBE_DEFER)
>-			DRM_DEV_ERROR(dev, "Failed to get gpio 'panel-on'\n");
>-		return ret;
>-	}
>-
>-	epd->discharge = devm_gpiod_get(dev, "discharge", GPIOD_OUT_LOW);
>-	if (IS_ERR(epd->discharge)) {
>-		ret = PTR_ERR(epd->discharge);
>-		if (ret != -EPROBE_DEFER)
>-			DRM_DEV_ERROR(dev, "Failed to get gpio 'discharge'\n");
>-		return ret;
>-	}
>-
>-	epd->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
>-	if (IS_ERR(epd->reset)) {
>-		ret = PTR_ERR(epd->reset);
>-		if (ret != -EPROBE_DEFER)
>-			DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
>-		return ret;
>-	}
>-
>-	epd->busy = devm_gpiod_get(dev, "busy", GPIOD_IN);
>-	if (IS_ERR(epd->busy)) {
>-		ret = PTR_ERR(epd->busy);
>-		if (ret != -EPROBE_DEFER)
>-			DRM_DEV_ERROR(dev, "Failed to get gpio 'busy'\n");
>-		return ret;
>-	}
>-
>-	if (!device_property_read_string(dev, "pervasive,thermal-zone",
>-					 &thermal_zone)) {
>-		epd->thermal = thermal_zone_get_zone_by_name(thermal_zone);
>-		if (IS_ERR(epd->thermal)) {
>-			DRM_DEV_ERROR(dev, "Failed to get thermal zone: %s\n", thermal_zone);
>-			return PTR_ERR(epd->thermal);
>-		}
>-	}
>-
>-	switch (model) {
>-	case E1144CS021:
>-		mode = &repaper_e1144cs021_mode;
>-		epd->channel_select = repaper_e1144cs021_cs;
>-		epd->stage_time = 480;
>-		epd->bytes_per_scan = 96 / 4;
>-		epd->middle_scan = true; /* data-scan-data */
>-		epd->pre_border_byte = false;
>-		epd->border_byte = REPAPER_BORDER_BYTE_ZERO;
>-		break;
>-
>-	case E1190CS021:
>-		mode = &repaper_e1190cs021_mode;
>-		epd->channel_select = repaper_e1190cs021_cs;
>-		epd->stage_time = 480;
>-		epd->bytes_per_scan = 128 / 4 / 2;
>-		epd->middle_scan = false; /* scan-data-scan */
>-		epd->pre_border_byte = false;
>-		epd->border_byte = REPAPER_BORDER_BYTE_SET;
>-		break;
>-
>-	case E2200CS021:
>-		mode = &repaper_e2200cs021_mode;
>-		epd->channel_select = repaper_e2200cs021_cs;
>-		epd->stage_time = 480;
>-		epd->bytes_per_scan = 96 / 4;
>-		epd->middle_scan = true; /* data-scan-data */
>-		epd->pre_border_byte = true;
>-		epd->border_byte = REPAPER_BORDER_BYTE_NONE;
>-		break;
>-
>-	case E2271CS021:
>-		epd->border = devm_gpiod_get(dev, "border", GPIOD_OUT_LOW);
>-		if (IS_ERR(epd->border)) {
>-			ret = PTR_ERR(epd->border);
>-			if (ret != -EPROBE_DEFER)
>-				DRM_DEV_ERROR(dev, "Failed to get gpio 'border'\n");
>-			return ret;
>-		}
>-
>-		mode = &repaper_e2271cs021_mode;
>-		epd->channel_select = repaper_e2271cs021_cs;
>-		epd->stage_time = 630;
>-		epd->bytes_per_scan = 176 / 4;
>-		epd->middle_scan = true; /* data-scan-data */
>-		epd->pre_border_byte = true;
>-		epd->border_byte = REPAPER_BORDER_BYTE_NONE;
>-		break;
>-
>-	default:
>-		return -ENODEV;
>-	}
>-
>-	epd->width = mode->hdisplay;
>-	epd->height = mode->vdisplay;
>-	epd->factored_stage_time = epd->stage_time;
>-
>-	line_buffer_size = 2 * epd->width / 8 + epd->bytes_per_scan + 2;
>-	epd->line_buffer = devm_kzalloc(dev, line_buffer_size, GFP_KERNEL);
>-	if (!epd->line_buffer)
>-		return -ENOMEM;
>-
>-	epd->current_frame = devm_kzalloc(dev, epd->width * epd->height / 8,
>-					  GFP_KERNEL);
>-	if (!epd->current_frame)
>-		return -ENOMEM;
>-
>-	ret = tinydrm_display_pipe_init(drm, &epd->pipe, &repaper_pipe_funcs,
>-					DRM_MODE_CONNECTOR_VIRTUAL,
>-					repaper_formats,
>-					ARRAY_SIZE(repaper_formats), mode, 0);
>-	if (ret)
>-		return ret;
>-
>-	drm_mode_config_reset(drm);
>-
>-	ret = drm_dev_register(drm, 0);
>-	if (ret)
>-		return ret;
>-
>-	spi_set_drvdata(spi, drm);
>-
>-	DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
>-
>-	drm_fbdev_generic_setup(drm, 0);
>-
>-	return 0;
>-}
>-
>-static int repaper_remove(struct spi_device *spi)
>-{
>-	struct drm_device *drm = spi_get_drvdata(spi);
>-
>-	drm_dev_unplug(drm);
>-	drm_atomic_helper_shutdown(drm);
>-
>-	return 0;
>-}
>-
>-static void repaper_shutdown(struct spi_device *spi)
>-{
>-	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>-}
>-
>-static struct spi_driver repaper_spi_driver = {
>-	.driver = {
>-		.name = "repaper",
>-		.owner = THIS_MODULE,
>-		.of_match_table = repaper_of_match,
>-	},
>-	.id_table = repaper_id,
>-	.probe = repaper_probe,
>-	.remove = repaper_remove,
>-	.shutdown = repaper_shutdown,
>-};
>-module_spi_driver(repaper_spi_driver);
>-
>-MODULE_DESCRIPTION("Pervasive Displays RePaper DRM driver");
>-MODULE_AUTHOR("Noralf TrÃ¸nnes");
>-MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/st7586.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/st7586.c
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/st7586.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/st7586.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,442 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0-or-later
>-/*
>- * DRM driver for Sitronix ST7586 panels
>- *
>- * Copyright 2017 David Lechner <david@lechnology.com>
>- */
>-
>-#include <linux/delay.h>
>-#include <linux/dma-buf.h>
>-#include <linux/gpio/consumer.h>
>-#include <linux/module.h>
>-#include <linux/property.h>
>-#include <linux/spi/spi.h>
>-#include <video/mipi_display.h>
>-
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_damage_helper.h>
>-#include <drm/drm_drv.h>
>-#include <drm/drm_fb_cma_helper.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_format_helper.h>
>-#include <drm/drm_gem_cma_helper.h>
>-#include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_rect.h>
>-#include <drm/drm_vblank.h>
>-#include <drm/tinydrm/mipi-dbi.h>
>-#include <drm/tinydrm/tinydrm-helpers.h>
>-
>-/* controller-specific commands */
>-#define ST7586_DISP_MODE_GRAY	0x38
>-#define ST7586_DISP_MODE_MONO	0x39
>-#define ST7586_ENABLE_DDRAM	0x3a
>-#define ST7586_SET_DISP_DUTY	0xb0
>-#define ST7586_SET_PART_DISP	0xb4
>-#define ST7586_SET_NLINE_INV	0xb5
>-#define ST7586_SET_VOP		0xc0
>-#define ST7586_SET_BIAS_SYSTEM	0xc3
>-#define ST7586_SET_BOOST_LEVEL	0xc4
>-#define ST7586_SET_VOP_OFFSET	0xc7
>-#define ST7586_ENABLE_ANALOG	0xd0
>-#define ST7586_AUTO_READ_CTRL	0xd7
>-#define ST7586_OTP_RW_CTRL	0xe0
>-#define ST7586_OTP_CTRL_OUT	0xe1
>-#define ST7586_OTP_READ		0xe3
>-
>-#define ST7586_DISP_CTRL_MX	BIT(6)
>-#define ST7586_DISP_CTRL_MY	BIT(7)
>-
>-/*
>- * The ST7586 controller has an unusual pixel format where 2bpp grayscale is
>- * packed 3 pixels per byte with the first two pixels using 3 bits and the 3rd
>- * pixel using only 2 bits.
>- *
>- * |  D7  |  D6  |  D5  ||      |      || 2bpp |
>- * | (D4) | (D3) | (D2) ||  D1  |  D0  || GRAY |
>- * +------+------+------++------+------++------+
>- * |  1   |  1   |  1   ||  1   |  1   || 0  0 | black
>- * |  1   |  0   |  0   ||  1   |  0   || 0  1 | dark gray
>- * |  0   |  1   |  0   ||  0   |  1   || 1  0 | light gray
>- * |  0   |  0   |  0   ||  0   |  0   || 1  1 | white
>- */
>-
>-static const u8 st7586_lookup[] = { 0x7, 0x4, 0x2, 0x0 };
>-
>-static void st7586_xrgb8888_to_gray332(u8 *dst, void *vaddr,
>-				       struct drm_framebuffer *fb,
>-				       struct drm_rect *clip)
>-{
>-	size_t len = (clip->x2 - clip->x1) * (clip->y2 - clip->y1);
>-	unsigned int x, y;
>-	u8 *src, *buf, val;
>-
>-	buf = kmalloc(len, GFP_KERNEL);
>-	if (!buf)
>-		return;
>-
>-	drm_fb_xrgb8888_to_gray8(buf, vaddr, fb, clip);
>-	src = buf;
>-
>-	for (y = clip->y1; y < clip->y2; y++) {
>-		for (x = clip->x1; x < clip->x2; x += 3) {
>-			val = st7586_lookup[*src++ >> 6] << 5;
>-			val |= st7586_lookup[*src++ >> 6] << 2;
>-			val |= st7586_lookup[*src++ >> 6] >> 1;
>-			*dst++ = val;
>-		}
>-	}
>-
>-	kfree(buf);
>-}
>-
>-static int st7586_buf_copy(void *dst, struct drm_framebuffer *fb,
>-			   struct drm_rect *clip)
>-{
>-	struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
>-	struct dma_buf_attachment *import_attach = cma_obj->base.import_attach;
>-	void *src = cma_obj->vaddr;
>-	int ret = 0;
>-
>-	if (import_attach) {
>-		ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
>-					       DMA_FROM_DEVICE);
>-		if (ret)
>-			return ret;
>-	}
>-
>-	st7586_xrgb8888_to_gray332(dst, src, fb, clip);
>-
>-	if (import_attach)
>-		ret = dma_buf_end_cpu_access(import_attach->dmabuf,
>-					     DMA_FROM_DEVICE);
>-
>-	return ret;
>-}
>-
>-static void st7586_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
>-{
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(fb->dev);
>-	int start, end, idx, ret = 0;
>-
>-	if (!mipi->enabled)
>-		return;
>-
>-	if (!drm_dev_enter(fb->dev, &idx))
>-		return;
>-
>-	/* 3 pixels per byte, so grow clip to nearest multiple of 3 */
>-	rect->x1 = rounddown(rect->x1, 3);
>-	rect->x2 = roundup(rect->x2, 3);
>-
>-	DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
>-
>-	ret = st7586_buf_copy(mipi->tx_buf, fb, rect);
>-	if (ret)
>-		goto err_msg;
>-
>-	/* Pixels are packed 3 per byte */
>-	start = rect->x1 / 3;
>-	end = rect->x2 / 3;
>-
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_COLUMN_ADDRESS,
>-			 (start >> 8) & 0xFF, start & 0xFF,
>-			 (end >> 8) & 0xFF, (end - 1) & 0xFF);
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_PAGE_ADDRESS,
>-			 (rect->y1 >> 8) & 0xFF, rect->y1 & 0xFF,
>-			 (rect->y2 >> 8) & 0xFF, (rect->y2 - 1) & 0xFF);
>-
>-	ret = mipi_dbi_command_buf(mipi, MIPI_DCS_WRITE_MEMORY_START,
>-				   (u8 *)mipi->tx_buf,
>-				   (end - start) * (rect->y2 - rect->y1));
>-err_msg:
>-	if (ret)
>-		dev_err_once(fb->dev->dev, "Failed to update display %d\n", ret);
>-
>-	drm_dev_exit(idx);
>-}
>-
>-static void st7586_pipe_update(struct drm_simple_display_pipe *pipe,
>-			       struct drm_plane_state *old_state)
>-{
>-	struct drm_plane_state *state = pipe->plane.state;
>-	struct drm_crtc *crtc = &pipe->crtc;
>-	struct drm_rect rect;
>-
>-	if (drm_atomic_helper_damage_merged(old_state, state, &rect))
>-		st7586_fb_dirty(state->fb, &rect);
>-
>-	if (crtc->state->event) {
>-		spin_lock_irq(&crtc->dev->event_lock);
>-		drm_crtc_send_vblank_event(crtc, crtc->state->event);
>-		spin_unlock_irq(&crtc->dev->event_lock);
>-		crtc->state->event = NULL;
>-	}
>-}
>-
>-static void st7586_pipe_enable(struct drm_simple_display_pipe *pipe,
>-			       struct drm_crtc_state *crtc_state,
>-			       struct drm_plane_state *plane_state)
>-{
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(pipe->crtc.dev);
>-	struct drm_framebuffer *fb = plane_state->fb;
>-	struct drm_rect rect = {
>-		.x1 = 0,
>-		.x2 = fb->width,
>-		.y1 = 0,
>-		.y2 = fb->height,
>-	};
>-	int idx, ret;
>-	u8 addr_mode;
>-
>-	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>-		return;
>-
>-	DRM_DEBUG_KMS("\n");
>-
>-	ret = mipi_dbi_poweron_reset(mipi);
>-	if (ret)
>-		goto out_exit;
>-
>-	mipi_dbi_command(mipi, ST7586_AUTO_READ_CTRL, 0x9f);
>-	mipi_dbi_command(mipi, ST7586_OTP_RW_CTRL, 0x00);
>-
>-	msleep(10);
>-
>-	mipi_dbi_command(mipi, ST7586_OTP_READ);
>-
>-	msleep(20);
>-
>-	mipi_dbi_command(mipi, ST7586_OTP_CTRL_OUT);
>-	mipi_dbi_command(mipi, MIPI_DCS_EXIT_SLEEP_MODE);
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_OFF);
>-
>-	msleep(50);
>-
>-	mipi_dbi_command(mipi, ST7586_SET_VOP_OFFSET, 0x00);
>-	mipi_dbi_command(mipi, ST7586_SET_VOP, 0xe3, 0x00);
>-	mipi_dbi_command(mipi, ST7586_SET_BIAS_SYSTEM, 0x02);
>-	mipi_dbi_command(mipi, ST7586_SET_BOOST_LEVEL, 0x04);
>-	mipi_dbi_command(mipi, ST7586_ENABLE_ANALOG, 0x1d);
>-	mipi_dbi_command(mipi, ST7586_SET_NLINE_INV, 0x00);
>-	mipi_dbi_command(mipi, ST7586_DISP_MODE_GRAY);
>-	mipi_dbi_command(mipi, ST7586_ENABLE_DDRAM, 0x02);
>-
>-	switch (mipi->rotation) {
>-	default:
>-		addr_mode = 0x00;
>-		break;
>-	case 90:
>-		addr_mode = ST7586_DISP_CTRL_MY;
>-		break;
>-	case 180:
>-		addr_mode = ST7586_DISP_CTRL_MX | ST7586_DISP_CTRL_MY;
>-		break;
>-	case 270:
>-		addr_mode = ST7586_DISP_CTRL_MX;
>-		break;
>-	}
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
>-
>-	mipi_dbi_command(mipi, ST7586_SET_DISP_DUTY, 0x7f);
>-	mipi_dbi_command(mipi, ST7586_SET_PART_DISP, 0xa0);
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_PARTIAL_AREA, 0x00, 0x00, 0x00, 0x77);
>-	mipi_dbi_command(mipi, MIPI_DCS_EXIT_INVERT_MODE);
>-
>-	msleep(100);
>-
>-	mipi->enabled = true;
>-	st7586_fb_dirty(fb, &rect);
>-
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_ON);
>-out_exit:
>-	drm_dev_exit(idx);
>-}
>-
>-static void st7586_pipe_disable(struct drm_simple_display_pipe *pipe)
>-{
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(pipe->crtc.dev);
>-
>-	/*
>-	 * This callback is not protected by drm_dev_enter/exit since we want to
>-	 * turn off the display on regular driver unload. It's highly unlikely
>-	 * that the underlying SPI controller is gone should this be called after
>-	 * unplug.
>-	 */
>-
>-	DRM_DEBUG_KMS("\n");
>-
>-	if (!mipi->enabled)
>-		return;
>-
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_OFF);
>-	mipi->enabled = false;
>-}
>-
>-static const u32 st7586_formats[] = {
>-	DRM_FORMAT_XRGB8888,
>-};
>-
>-static const struct drm_simple_display_pipe_funcs st7586_pipe_funcs = {
>-	.enable		= st7586_pipe_enable,
>-	.disable	= st7586_pipe_disable,
>-	.update		= st7586_pipe_update,
>-	.prepare_fb	= drm_gem_fb_simple_display_pipe_prepare_fb,
>-};
>-
>-static const struct drm_mode_config_funcs st7586_mode_config_funcs = {
>-	.fb_create = drm_gem_fb_create_with_dirty,
>-	.atomic_check = drm_atomic_helper_check,
>-	.atomic_commit = drm_atomic_helper_commit,
>-};
>-
>-static const struct drm_display_mode st7586_mode = {
>-	DRM_SIMPLE_MODE(178, 128, 37, 27),
>-};
>-
>-DEFINE_DRM_GEM_CMA_FOPS(st7586_fops);
>-
>-static struct drm_driver st7586_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
>-				  DRIVER_ATOMIC,
>-	.fops			= &st7586_fops,
>-	.release		= mipi_dbi_release,
>-	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>-	.debugfs_init		= mipi_dbi_debugfs_init,
>-	.name			= "st7586",
>-	.desc			= "Sitronix ST7586",
>-	.date			= "20170801",
>-	.major			= 1,
>-	.minor			= 0,
>-};
>-
>-static const struct of_device_id st7586_of_match[] = {
>-	{ .compatible = "lego,ev3-lcd" },
>-	{},
>-};
>-MODULE_DEVICE_TABLE(of, st7586_of_match);
>-
>-static const struct spi_device_id st7586_id[] = {
>-	{ "ev3-lcd", 0 },
>-	{ },
>-};
>-MODULE_DEVICE_TABLE(spi, st7586_id);
>-
>-static int st7586_probe(struct spi_device *spi)
>-{
>-	struct device *dev = &spi->dev;
>-	struct drm_device *drm;
>-	struct mipi_dbi *mipi;
>-	struct gpio_desc *a0;
>-	u32 rotation = 0;
>-	size_t bufsize;
>-	int ret;
>-
>-	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
>-	if (!mipi)
>-		return -ENOMEM;
>-
>-	drm = &mipi->drm;
>-	ret = devm_drm_dev_init(dev, drm, &st7586_driver);
>-	if (ret) {
>-		kfree(mipi);
>-		return ret;
>-	}
>-
>-	drm_mode_config_init(drm);
>-	drm->mode_config.preferred_depth = 32;
>-	drm->mode_config.funcs = &st7586_mode_config_funcs;
>-
>-	mutex_init(&mipi->cmdlock);
>-
>-	bufsize = (st7586_mode.vdisplay + 2) / 3 * st7586_mode.hdisplay;
>-	mipi->tx_buf = devm_kmalloc(dev, bufsize, GFP_KERNEL);
>-	if (!mipi->tx_buf)
>-		return -ENOMEM;
>-
>-	mipi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
>-	if (IS_ERR(mipi->reset)) {
>-		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
>-		return PTR_ERR(mipi->reset);
>-	}
>-
>-	a0 = devm_gpiod_get(dev, "a0", GPIOD_OUT_LOW);
>-	if (IS_ERR(a0)) {
>-		DRM_DEV_ERROR(dev, "Failed to get gpio 'a0'\n");
>-		return PTR_ERR(a0);
>-	}
>-
>-	device_property_read_u32(dev, "rotation", &rotation);
>-	mipi->rotation = rotation;
>-
>-	ret = mipi_dbi_spi_init(spi, mipi, a0);
>-	if (ret)
>-		return ret;
>-
>-	/* Cannot read from this controller via SPI */
>-	mipi->read_commands = NULL;
>-
>-	/*
>-	 * we are using 8-bit data, so we are not actually swapping anything,
>-	 * but setting mipi->swap_bytes makes mipi_dbi_typec3_command() do the
>-	 * right thing and not use 16-bit transfers (which results in swapped
>-	 * bytes on little-endian systems and causes out of order data to be
>-	 * sent to the display).
>-	 */
>-	mipi->swap_bytes = true;
>-
>-	ret = tinydrm_display_pipe_init(drm, &mipi->pipe, &st7586_pipe_funcs,
>-					DRM_MODE_CONNECTOR_VIRTUAL,
>-					st7586_formats, ARRAY_SIZE(st7586_formats),
>-					&st7586_mode, rotation);
>-	if (ret)
>-		return ret;
>-
>-	drm_plane_enable_fb_damage_clips(&mipi->pipe.plane);
>-
>-	drm_mode_config_reset(drm);
>-
>-	ret = drm_dev_register(drm, 0);
>-	if (ret)
>-		return ret;
>-
>-	spi_set_drvdata(spi, drm);
>-
>-	DRM_DEBUG_KMS("preferred_depth=%u, rotation = %u\n",
>-		      drm->mode_config.preferred_depth, rotation);
>-
>-	drm_fbdev_generic_setup(drm, 0);
>-
>-	return 0;
>-}
>-
>-static int st7586_remove(struct spi_device *spi)
>-{
>-	struct drm_device *drm = spi_get_drvdata(spi);
>-
>-	drm_dev_unplug(drm);
>-	drm_atomic_helper_shutdown(drm);
>-
>-	return 0;
>-}
>-
>-static void st7586_shutdown(struct spi_device *spi)
>-{
>-	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>-}
>-
>-static struct spi_driver st7586_spi_driver = {
>-	.driver = {
>-		.name = "st7586",
>-		.owner = THIS_MODULE,
>-		.of_match_table = st7586_of_match,
>-	},
>-	.id_table = st7586_id,
>-	.probe = st7586_probe,
>-	.remove = st7586_remove,
>-	.shutdown = st7586_shutdown,
>-};
>-module_spi_driver(st7586_spi_driver);
>-
>-MODULE_DESCRIPTION("Sitronix ST7586 DRM driver");
>-MODULE_AUTHOR("David Lechner <david@lechnology.com>");
>-MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tinydrm/st7735r.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/st7735r.c
>--- linux-5.3-rc6/drivers/gpu/drm/tinydrm/st7735r.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tinydrm/st7735r.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,245 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0+
>-/*
>- * DRM driver for Sitronix ST7735R panels
>- *
>- * Copyright 2017 David Lechner <david@lechnology.com>
>- */
>-
>-#include <linux/backlight.h>
>-#include <linux/delay.h>
>-#include <linux/dma-buf.h>
>-#include <linux/gpio/consumer.h>
>-#include <linux/module.h>
>-#include <linux/property.h>
>-#include <linux/spi/spi.h>
>-#include <video/mipi_display.h>
>-
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_drv.h>
>-#include <drm/drm_fb_helper.h>
>-#include <drm/drm_gem_cma_helper.h>
>-#include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/tinydrm/mipi-dbi.h>
>-#include <drm/tinydrm/tinydrm-helpers.h>
>-
>-#define ST7735R_FRMCTR1		0xb1
>-#define ST7735R_FRMCTR2		0xb2
>-#define ST7735R_FRMCTR3		0xb3
>-#define ST7735R_INVCTR		0xb4
>-#define ST7735R_PWCTR1		0xc0
>-#define ST7735R_PWCTR2		0xc1
>-#define ST7735R_PWCTR3		0xc2
>-#define ST7735R_PWCTR4		0xc3
>-#define ST7735R_PWCTR5		0xc4
>-#define ST7735R_VMCTR1		0xc5
>-#define ST7735R_GAMCTRP1	0xe0
>-#define ST7735R_GAMCTRN1	0xe1
>-
>-#define ST7735R_MY	BIT(7)
>-#define ST7735R_MX	BIT(6)
>-#define ST7735R_MV	BIT(5)
>-
>-static void jd_t18003_t01_pipe_enable(struct drm_simple_display_pipe *pipe,
>-				      struct drm_crtc_state *crtc_state,
>-				      struct drm_plane_state *plane_state)
>-{
>-	struct mipi_dbi *mipi = drm_to_mipi_dbi(pipe->crtc.dev);
>-	int ret, idx;
>-	u8 addr_mode;
>-
>-	if (!drm_dev_enter(pipe->crtc.dev, &idx))
>-		return;
>-
>-	DRM_DEBUG_KMS("\n");
>-
>-	ret = mipi_dbi_poweron_reset(mipi);
>-	if (ret)
>-		goto out_exit;
>-
>-	msleep(150);
>-
>-	mipi_dbi_command(mipi, MIPI_DCS_EXIT_SLEEP_MODE);
>-	msleep(500);
>-
>-	mipi_dbi_command(mipi, ST7735R_FRMCTR1, 0x01, 0x2c, 0x2d);
>-	mipi_dbi_command(mipi, ST7735R_FRMCTR2, 0x01, 0x2c, 0x2d);
>-	mipi_dbi_command(mipi, ST7735R_FRMCTR3, 0x01, 0x2c, 0x2d, 0x01, 0x2c,
>-			 0x2d);
>-	mipi_dbi_command(mipi, ST7735R_INVCTR, 0x07);
>-	mipi_dbi_command(mipi, ST7735R_PWCTR1, 0xa2, 0x02, 0x84);
>-	mipi_dbi_command(mipi, ST7735R_PWCTR2, 0xc5);
>-	mipi_dbi_command(mipi, ST7735R_PWCTR3, 0x0a, 0x00);
>-	mipi_dbi_command(mipi, ST7735R_PWCTR4, 0x8a, 0x2a);
>-	mipi_dbi_command(mipi, ST7735R_PWCTR5, 0x8a, 0xee);
>-	mipi_dbi_command(mipi, ST7735R_VMCTR1, 0x0e);
>-	mipi_dbi_command(mipi, MIPI_DCS_EXIT_INVERT_MODE);
>-	switch (mipi->rotation) {
>-	default:
>-		addr_mode = ST7735R_MX | ST7735R_MY;
>-		break;
>-	case 90:
>-		addr_mode = ST7735R_MX | ST7735R_MV;
>-		break;
>-	case 180:
>-		addr_mode = 0;
>-		break;
>-	case 270:
>-		addr_mode = ST7735R_MY | ST7735R_MV;
>-		break;
>-	}
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_PIXEL_FORMAT,
>-			 MIPI_DCS_PIXEL_FMT_16BIT);
>-	mipi_dbi_command(mipi, ST7735R_GAMCTRP1, 0x02, 0x1c, 0x07, 0x12, 0x37,
>-			 0x32, 0x29, 0x2d, 0x29, 0x25, 0x2b, 0x39, 0x00, 0x01,
>-			 0x03, 0x10);
>-	mipi_dbi_command(mipi, ST7735R_GAMCTRN1, 0x03, 0x1d, 0x07, 0x06, 0x2e,
>-			 0x2c, 0x29, 0x2d, 0x2e, 0x2e, 0x37, 0x3f, 0x00, 0x00,
>-			 0x02, 0x10);
>-	mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_ON);
>-
>-	msleep(100);
>-
>-	mipi_dbi_command(mipi, MIPI_DCS_ENTER_NORMAL_MODE);
>-
>-	msleep(20);
>-
>-	mipi_dbi_enable_flush(mipi, crtc_state, plane_state);
>-out_exit:
>-	drm_dev_exit(idx);
>-}
>-
>-static const struct drm_simple_display_pipe_funcs jd_t18003_t01_pipe_funcs = {
>-	.enable		= jd_t18003_t01_pipe_enable,
>-	.disable	= mipi_dbi_pipe_disable,
>-	.update		= mipi_dbi_pipe_update,
>-	.prepare_fb	= drm_gem_fb_simple_display_pipe_prepare_fb,
>-};
>-
>-static const struct drm_display_mode jd_t18003_t01_mode = {
>-	DRM_SIMPLE_MODE(128, 160, 28, 35),
>-};
>-
>-DEFINE_DRM_GEM_CMA_FOPS(st7735r_fops);
>-
>-static struct drm_driver st7735r_driver = {
>-	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
>-				  DRIVER_ATOMIC,
>-	.fops			= &st7735r_fops,
>-	.release		= mipi_dbi_release,
>-	DRM_GEM_CMA_VMAP_DRIVER_OPS,
>-	.debugfs_init		= mipi_dbi_debugfs_init,
>-	.name			= "st7735r",
>-	.desc			= "Sitronix ST7735R",
>-	.date			= "20171128",
>-	.major			= 1,
>-	.minor			= 0,
>-};
>-
>-static const struct of_device_id st7735r_of_match[] = {
>-	{ .compatible = "jianda,jd-t18003-t01" },
>-	{ },
>-};
>-MODULE_DEVICE_TABLE(of, st7735r_of_match);
>-
>-static const struct spi_device_id st7735r_id[] = {
>-	{ "jd-t18003-t01", 0 },
>-	{ },
>-};
>-MODULE_DEVICE_TABLE(spi, st7735r_id);
>-
>-static int st7735r_probe(struct spi_device *spi)
>-{
>-	struct device *dev = &spi->dev;
>-	struct drm_device *drm;
>-	struct mipi_dbi *mipi;
>-	struct gpio_desc *dc;
>-	u32 rotation = 0;
>-	int ret;
>-
>-	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
>-	if (!mipi)
>-		return -ENOMEM;
>-
>-	drm = &mipi->drm;
>-	ret = devm_drm_dev_init(dev, drm, &st7735r_driver);
>-	if (ret) {
>-		kfree(mipi);
>-		return ret;
>-	}
>-
>-	drm_mode_config_init(drm);
>-
>-	mipi->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
>-	if (IS_ERR(mipi->reset)) {
>-		DRM_DEV_ERROR(dev, "Failed to get gpio 'reset'\n");
>-		return PTR_ERR(mipi->reset);
>-	}
>-
>-	dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
>-	if (IS_ERR(dc)) {
>-		DRM_DEV_ERROR(dev, "Failed to get gpio 'dc'\n");
>-		return PTR_ERR(dc);
>-	}
>-
>-	mipi->backlight = devm_of_find_backlight(dev);
>-	if (IS_ERR(mipi->backlight))
>-		return PTR_ERR(mipi->backlight);
>-
>-	device_property_read_u32(dev, "rotation", &rotation);
>-
>-	ret = mipi_dbi_spi_init(spi, mipi, dc);
>-	if (ret)
>-		return ret;
>-
>-	/* Cannot read from Adafruit 1.8" display via SPI */
>-	mipi->read_commands = NULL;
>-
>-	ret = mipi_dbi_init(mipi, &jd_t18003_t01_pipe_funcs, &jd_t18003_t01_mode, rotation);
>-	if (ret)
>-		return ret;
>-
>-	drm_mode_config_reset(drm);
>-
>-	ret = drm_dev_register(drm, 0);
>-	if (ret)
>-		return ret;
>-
>-	spi_set_drvdata(spi, drm);
>-
>-	drm_fbdev_generic_setup(drm, 0);
>-
>-	return 0;
>-}
>-
>-static int st7735r_remove(struct spi_device *spi)
>-{
>-	struct drm_device *drm = spi_get_drvdata(spi);
>-
>-	drm_dev_unplug(drm);
>-	drm_atomic_helper_shutdown(drm);
>-
>-	return 0;
>-}
>-
>-static void st7735r_shutdown(struct spi_device *spi)
>-{
>-	drm_atomic_helper_shutdown(spi_get_drvdata(spi));
>-}
>-
>-static struct spi_driver st7735r_spi_driver = {
>-	.driver = {
>-		.name = "st7735r",
>-		.owner = THIS_MODULE,
>-		.of_match_table = st7735r_of_match,
>-	},
>-	.id_table = st7735r_id,
>-	.probe = st7735r_probe,
>-	.remove = st7735r_remove,
>-	.shutdown = st7735r_shutdown,
>-};
>-module_spi_driver(st7735r_spi_driver);
>-
>-MODULE_DESCRIPTION("Sitronix ST7735R DRM driver");
>-MODULE_AUTHOR("David Lechner <david@lechnology.com>");
>-MODULE_LICENSE("GPL");
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ttm/ttm_bo.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ttm/ttm_bo.c
>--- linux-5.3-rc6/drivers/gpu/drm/ttm/ttm_bo.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ttm/ttm_bo.c	2019-08-31 15:01:12.135736193 -0500
>@@ -160,7 +160,8 @@
> 	ttm_tt_destroy(bo->ttm);
> 	atomic_dec(&bo->bdev->glob->bo_count);
> 	dma_fence_put(bo->moving);
>-	reservation_object_fini(&bo->ttm_resv);
>+	if (!ttm_bo_uses_embedded_gem_object(bo))
>+		reservation_object_fini(&bo->base._resv);
> 	mutex_destroy(&bo->wu_mutex);
> 	bo->destroy(bo);
> 	ttm_mem_global_free(bdev->glob->mem_glob, acc_size);
>@@ -172,7 +173,7 @@
> 	struct ttm_bo_device *bdev = bo->bdev;
> 	struct ttm_mem_type_manager *man;
> 
>-	reservation_object_assert_held(bo->resv);
>+	reservation_object_assert_held(bo->base.resv);
> 
> 	if (!list_empty(&bo->lru))
> 		return;
>@@ -243,7 +244,7 @@
> void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo,
> 			     struct ttm_lru_bulk_move *bulk)
> {
>-	reservation_object_assert_held(bo->resv);
>+	reservation_object_assert_held(bo->base.resv);
> 
> 	ttm_bo_del_from_lru(bo);
> 	ttm_bo_add_to_lru(bo);
>@@ -276,8 +277,8 @@
> 		if (!pos->first)
> 			continue;
> 
>-		reservation_object_assert_held(pos->first->resv);
>-		reservation_object_assert_held(pos->last->resv);
>+		reservation_object_assert_held(pos->first->base.resv);
>+		reservation_object_assert_held(pos->last->base.resv);
> 
> 		man = &pos->first->bdev->man[TTM_PL_TT];
> 		list_bulk_move_tail(&man->lru[i], &pos->first->lru,
>@@ -291,8 +292,8 @@
> 		if (!pos->first)
> 			continue;
> 
>-		reservation_object_assert_held(pos->first->resv);
>-		reservation_object_assert_held(pos->last->resv);
>+		reservation_object_assert_held(pos->first->base.resv);
>+		reservation_object_assert_held(pos->last->base.resv);
> 
> 		man = &pos->first->bdev->man[TTM_PL_VRAM];
> 		list_bulk_move_tail(&man->lru[i], &pos->first->lru,
>@@ -306,8 +307,8 @@
> 		if (!pos->first)
> 			continue;
> 
>-		reservation_object_assert_held(pos->first->resv);
>-		reservation_object_assert_held(pos->last->resv);
>+		reservation_object_assert_held(pos->first->base.resv);
>+		reservation_object_assert_held(pos->last->base.resv);
> 
> 		lru = &pos->first->bdev->glob->swap_lru[i];
> 		list_bulk_move_tail(lru, &pos->first->swap, &pos->last->swap);
>@@ -438,14 +439,14 @@
> {
> 	int r;
> 
>-	if (bo->resv == &bo->ttm_resv)
>+	if (bo->base.resv == &bo->base._resv)
> 		return 0;
> 
>-	BUG_ON(!reservation_object_trylock(&bo->ttm_resv));
>+	BUG_ON(!reservation_object_trylock(&bo->base._resv));
> 
>-	r = reservation_object_copy_fences(&bo->ttm_resv, bo->resv);
>+	r = reservation_object_copy_fences(&bo->base._resv, bo->base.resv);
> 	if (r)
>-		reservation_object_unlock(&bo->ttm_resv);
>+		reservation_object_unlock(&bo->base._resv);
> 
> 	return r;
> }
>@@ -456,14 +457,14 @@
> 	struct dma_fence *fence;
> 	int i;
> 
>-	fobj = reservation_object_get_list(&bo->ttm_resv);
>-	fence = reservation_object_get_excl(&bo->ttm_resv);
>+	fobj = reservation_object_get_list(&bo->base._resv);
>+	fence = reservation_object_get_excl(&bo->base._resv);
> 	if (fence && !fence->ops->signaled)
> 		dma_fence_enable_sw_signaling(fence);
> 
> 	for (i = 0; fobj && i < fobj->shared_count; ++i) {
> 		fence = rcu_dereference_protected(fobj->shared[i],
>-					reservation_object_held(bo->resv));
>+					reservation_object_held(bo->base.resv));
> 
> 		if (!fence->ops->signaled)
> 			dma_fence_enable_sw_signaling(fence);
>@@ -481,23 +482,23 @@
> 		/* Last resort, if we fail to allocate memory for the
> 		 * fences block for the BO to become idle
> 		 */
>-		reservation_object_wait_timeout_rcu(bo->resv, true, false,
>+		reservation_object_wait_timeout_rcu(bo->base.resv, true, false,
> 						    30 * HZ);
> 		spin_lock(&glob->lru_lock);
> 		goto error;
> 	}
> 
> 	spin_lock(&glob->lru_lock);
>-	ret = reservation_object_trylock(bo->resv) ? 0 : -EBUSY;
>+	ret = reservation_object_trylock(bo->base.resv) ? 0 : -EBUSY;
> 	if (!ret) {
>-		if (reservation_object_test_signaled_rcu(&bo->ttm_resv, true)) {
>+		if (reservation_object_test_signaled_rcu(&bo->base._resv, true)) {
> 			ttm_bo_del_from_lru(bo);
> 			spin_unlock(&glob->lru_lock);
>-			if (bo->resv != &bo->ttm_resv)
>-				reservation_object_unlock(&bo->ttm_resv);
>+			if (bo->base.resv != &bo->base._resv)
>+				reservation_object_unlock(&bo->base._resv);
> 
> 			ttm_bo_cleanup_memtype_use(bo);
>-			reservation_object_unlock(bo->resv);
>+			reservation_object_unlock(bo->base.resv);
> 			return;
> 		}
> 
>@@ -513,10 +514,10 @@
> 			ttm_bo_add_to_lru(bo);
> 		}
> 
>-		reservation_object_unlock(bo->resv);
>+		reservation_object_unlock(bo->base.resv);
> 	}
>-	if (bo->resv != &bo->ttm_resv)
>-		reservation_object_unlock(&bo->ttm_resv);
>+	if (bo->base.resv != &bo->base._resv)
>+		reservation_object_unlock(&bo->base._resv);
> 
> error:
> 	kref_get(&bo->list_kref);
>@@ -549,9 +550,9 @@
> 	int ret;
> 
> 	if (unlikely(list_empty(&bo->ddestroy)))
>-		resv = bo->resv;
>+		resv = bo->base.resv;
> 	else
>-		resv = &bo->ttm_resv;
>+		resv = &bo->base._resv;
> 
> 	if (reservation_object_test_signaled_rcu(resv, true))
> 		ret = 0;
>@@ -562,7 +563,7 @@
> 		long lret;
> 
> 		if (unlock_resv)
>-			reservation_object_unlock(bo->resv);
>+			reservation_object_unlock(bo->base.resv);
> 		spin_unlock(&glob->lru_lock);
> 
> 		lret = reservation_object_wait_timeout_rcu(resv, true,
>@@ -575,7 +576,7 @@
> 			return -EBUSY;
> 
> 		spin_lock(&glob->lru_lock);
>-		if (unlock_resv && !reservation_object_trylock(bo->resv)) {
>+		if (unlock_resv && !reservation_object_trylock(bo->base.resv)) {
> 			/*
> 			 * We raced, and lost, someone else holds the reservation now,
> 			 * and is probably busy in ttm_bo_cleanup_memtype_use.
>@@ -592,7 +593,7 @@
> 
> 	if (ret || unlikely(list_empty(&bo->ddestroy))) {
> 		if (unlock_resv)
>-			reservation_object_unlock(bo->resv);
>+			reservation_object_unlock(bo->base.resv);
> 		spin_unlock(&glob->lru_lock);
> 		return ret;
> 	}
>@@ -605,7 +606,7 @@
> 	ttm_bo_cleanup_memtype_use(bo);
> 
> 	if (unlock_resv)
>-		reservation_object_unlock(bo->resv);
>+		reservation_object_unlock(bo->base.resv);
> 
> 	return 0;
> }
>@@ -631,14 +632,14 @@
> 		kref_get(&bo->list_kref);
> 		list_move_tail(&bo->ddestroy, &removed);
> 
>-		if (remove_all || bo->resv != &bo->ttm_resv) {
>+		if (remove_all || bo->base.resv != &bo->base._resv) {
> 			spin_unlock(&glob->lru_lock);
>-			reservation_object_lock(bo->resv, NULL);
>+			reservation_object_lock(bo->base.resv, NULL);
> 
> 			spin_lock(&glob->lru_lock);
> 			ttm_bo_cleanup_refs(bo, false, !remove_all, true);
> 
>-		} else if (reservation_object_trylock(bo->resv)) {
>+		} else if (reservation_object_trylock(bo->base.resv)) {
> 			ttm_bo_cleanup_refs(bo, false, !remove_all, true);
> 		} else {
> 			spin_unlock(&glob->lru_lock);
>@@ -671,7 +672,10 @@
> 	struct ttm_bo_device *bdev = bo->bdev;
> 	struct ttm_mem_type_manager *man = &bdev->man[bo->mem.mem_type];
> 
>-	drm_vma_offset_remove(&bdev->vma_manager, &bo->vma_node);
>+	if (bo->bdev->driver->release_notify)
>+		bo->bdev->driver->release_notify(bo);
>+
>+	drm_vma_offset_remove(&bdev->vma_manager, &bo->base.vma_node);
> 	ttm_mem_io_lock(man, false);
> 	ttm_mem_io_free_vm(bo);
> 	ttm_mem_io_unlock(man);
>@@ -707,7 +711,7 @@
> 	struct ttm_placement placement;
> 	int ret = 0;
> 
>-	reservation_object_assert_held(bo->resv);
>+	reservation_object_assert_held(bo->base.resv);
> 
> 	placement.num_placement = 0;
> 	placement.num_busy_placement = 0;
>@@ -777,8 +781,8 @@
> {
> 	bool ret = false;
> 
>-	if (bo->resv == ctx->resv) {
>-		reservation_object_assert_held(bo->resv);
>+	if (bo->base.resv == ctx->resv) {
>+		reservation_object_assert_held(bo->base.resv);
> 		if (ctx->flags & TTM_OPT_FLAG_ALLOW_RES_EVICT
> 		    || !list_empty(&bo->ddestroy))
> 			ret = true;
>@@ -786,7 +790,7 @@
> 		if (busy)
> 			*busy = false;
> 	} else {
>-		ret = reservation_object_trylock(bo->resv);
>+		ret = reservation_object_trylock(bo->base.resv);
> 		*locked = ret;
> 		if (busy)
> 			*busy = !ret;
>@@ -814,10 +818,10 @@
> 		return -EBUSY;
> 
> 	if (ctx->interruptible)
>-		r = reservation_object_lock_interruptible(busy_bo->resv,
>+		r = reservation_object_lock_interruptible(busy_bo->base.resv,
> 							  ticket);
> 	else
>-		r = reservation_object_lock(busy_bo->resv, ticket);
>+		r = reservation_object_lock(busy_bo->base.resv, ticket);
> 
> 	/*
> 	 * TODO: It would be better to keep the BO locked until allocation is at
>@@ -825,7 +829,7 @@
> 	 * of TTM.
> 	 */
> 	if (!r)
>-		reservation_object_unlock(busy_bo->resv);
>+		reservation_object_unlock(busy_bo->base.resv);
> 
> 	return r == -EDEADLK ? -EBUSY : r;
> }
>@@ -850,8 +854,8 @@
> 
> 			if (!ttm_bo_evict_swapout_allowable(bo, ctx, &locked,
> 							    &busy)) {
>-				if (busy && !busy_bo &&
>-				    bo->resv->lock.ctx != ticket)
>+				if (busy && !busy_bo && ticket !=
>+				    reservation_object_locking_ctx(bo->base.resv))
> 					busy_bo = bo;
> 				continue;
> 			}
>@@ -859,7 +863,7 @@
> 			if (place && !bdev->driver->eviction_valuable(bo,
> 								      place)) {
> 				if (locked)
>-					reservation_object_unlock(bo->resv);
>+					reservation_object_unlock(bo->base.resv);
> 				continue;
> 			}
> 			break;
>@@ -931,9 +935,9 @@
> 	spin_unlock(&man->move_lock);
> 
> 	if (fence) {
>-		reservation_object_add_shared_fence(bo->resv, fence);
>+		reservation_object_add_shared_fence(bo->base.resv, fence);
> 
>-		ret = reservation_object_reserve_shared(bo->resv, 1);
>+		ret = reservation_object_reserve_shared(bo->base.resv, 1);
> 		if (unlikely(ret)) {
> 			dma_fence_put(fence);
> 			return ret;
>@@ -957,8 +961,10 @@
> {
> 	struct ttm_bo_device *bdev = bo->bdev;
> 	struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
>+	struct ww_acquire_ctx *ticket;
> 	int ret;
> 
>+	ticket = reservation_object_locking_ctx(bo->base.resv);
> 	do {
> 		ret = (*man->func->get_node)(man, bo, place, mem);
> 		if (unlikely(ret != 0))
>@@ -966,7 +972,7 @@
> 		if (mem->mm_node)
> 			break;
> 		ret = ttm_mem_evict_first(bdev, mem->mem_type, place, ctx,
>-					  bo->resv->lock.ctx);
>+					  ticket);
> 		if (unlikely(ret != 0))
> 			return ret;
> 	} while (1);
>@@ -1088,7 +1094,7 @@
> 	bool type_found = false;
> 	int i, ret;
> 
>-	ret = reservation_object_reserve_shared(bo->resv, 1);
>+	ret = reservation_object_reserve_shared(bo->base.resv, 1);
> 	if (unlikely(ret))
> 		return ret;
> 
>@@ -1169,7 +1175,7 @@
> 	int ret = 0;
> 	struct ttm_mem_reg mem;
> 
>-	reservation_object_assert_held(bo->resv);
>+	reservation_object_assert_held(bo->base.resv);
> 
> 	mem.num_pages = bo->num_pages;
> 	mem.size = mem.num_pages << PAGE_SHIFT;
>@@ -1239,7 +1245,7 @@
> 	int ret;
> 	uint32_t new_flags;
> 
>-	reservation_object_assert_held(bo->resv);
>+	reservation_object_assert_held(bo->base.resv);
> 	/*
> 	 * Check whether we need to move buffer.
> 	 */
>@@ -1329,14 +1335,20 @@
> 	bo->acc_size = acc_size;
> 	bo->sg = sg;
> 	if (resv) {
>-		bo->resv = resv;
>-		reservation_object_assert_held(bo->resv);
>+		bo->base.resv = resv;
>+		reservation_object_assert_held(bo->base.resv);
> 	} else {
>-		bo->resv = &bo->ttm_resv;
>+		bo->base.resv = &bo->base._resv;
>+	}
>+	if (!ttm_bo_uses_embedded_gem_object(bo)) {
>+		/*
>+		 * bo.gem is not initialized, so we have to setup the
>+		 * struct elements we want use regardless.
>+		 */
>+		reservation_object_init(&bo->base._resv);
>+		drm_vma_node_reset(&bo->base.vma_node);
> 	}
>-	reservation_object_init(&bo->ttm_resv);
> 	atomic_inc(&bo->bdev->glob->bo_count);
>-	drm_vma_node_reset(&bo->vma_node);
> 
> 	/*
> 	 * For ttm_bo_type_device buffers, allocate
>@@ -1344,14 +1356,14 @@
> 	 */
> 	if (bo->type == ttm_bo_type_device ||
> 	    bo->type == ttm_bo_type_sg)
>-		ret = drm_vma_offset_add(&bdev->vma_manager, &bo->vma_node,
>+		ret = drm_vma_offset_add(&bdev->vma_manager, &bo->base.vma_node,
> 					 bo->mem.num_pages);
> 
> 	/* passed reservation objects should already be locked,
> 	 * since otherwise lockdep will be angered in radeon.
> 	 */
> 	if (!resv) {
>-		locked = reservation_object_trylock(bo->resv);
>+		locked = reservation_object_trylock(bo->base.resv);
> 		WARN_ON(!locked);
> 	}
> 
>@@ -1772,7 +1784,7 @@
> {
> 	struct ttm_bo_device *bdev = bo->bdev;
> 
>-	drm_vma_node_unmap(&bo->vma_node, bdev->dev_mapping);
>+	drm_vma_node_unmap(&bo->base.vma_node, bdev->dev_mapping);
> 	ttm_mem_io_free_vm(bo);
> }
> 
>@@ -1795,13 +1807,13 @@
> 	long timeout = 15 * HZ;
> 
> 	if (no_wait) {
>-		if (reservation_object_test_signaled_rcu(bo->resv, true))
>+		if (reservation_object_test_signaled_rcu(bo->base.resv, true))
> 			return 0;
> 		else
> 			return -EBUSY;
> 	}
> 
>-	timeout = reservation_object_wait_timeout_rcu(bo->resv, true,
>+	timeout = reservation_object_wait_timeout_rcu(bo->base.resv, true,
> 						      interruptible, timeout);
> 	if (timeout < 0)
> 		return timeout;
>@@ -1809,7 +1821,7 @@
> 	if (timeout == 0)
> 		return -EBUSY;
> 
>-	reservation_object_add_excl_fence(bo->resv, NULL);
>+	reservation_object_add_excl_fence(bo->base.resv, NULL);
> 	return 0;
> }
> EXPORT_SYMBOL(ttm_bo_wait);
>@@ -1925,7 +1937,7 @@
> 	 * already swapped buffer.
> 	 */
> 	if (locked)
>-		reservation_object_unlock(bo->resv);
>+		reservation_object_unlock(bo->base.resv);
> 	kref_put(&bo->list_kref, ttm_bo_release_list);
> 	return ret;
> }
>@@ -1963,14 +1975,14 @@
> 	ret = mutex_lock_interruptible(&bo->wu_mutex);
> 	if (unlikely(ret != 0))
> 		return -ERESTARTSYS;
>-	if (!ww_mutex_is_locked(&bo->resv->lock))
>+	if (!reservation_object_is_locked(bo->base.resv))
> 		goto out_unlock;
>-	ret = reservation_object_lock_interruptible(bo->resv, NULL);
>+	ret = reservation_object_lock_interruptible(bo->base.resv, NULL);
> 	if (ret == -EINTR)
> 		ret = -ERESTARTSYS;
> 	if (unlikely(ret != 0))
> 		goto out_unlock;
>-	reservation_object_unlock(bo->resv);
>+	reservation_object_unlock(bo->base.resv);
> 
> out_unlock:
> 	mutex_unlock(&bo->wu_mutex);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ttm/ttm_bo_util.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ttm/ttm_bo_util.c
>--- linux-5.3-rc6/drivers/gpu/drm/ttm/ttm_bo_util.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ttm/ttm_bo_util.c	2019-08-31 15:01:12.135736193 -0500
>@@ -510,16 +510,16 @@
> 	INIT_LIST_HEAD(&fbo->base.io_reserve_lru);
> 	mutex_init(&fbo->base.wu_mutex);
> 	fbo->base.moving = NULL;
>-	drm_vma_node_reset(&fbo->base.vma_node);
>+	drm_vma_node_reset(&fbo->base.base.vma_node);
> 	atomic_set(&fbo->base.cpu_writers, 0);
> 
> 	kref_init(&fbo->base.list_kref);
> 	kref_init(&fbo->base.kref);
> 	fbo->base.destroy = &ttm_transfered_destroy;
> 	fbo->base.acc_size = 0;
>-	fbo->base.resv = &fbo->base.ttm_resv;
>-	reservation_object_init(fbo->base.resv);
>-	ret = reservation_object_trylock(fbo->base.resv);
>+	fbo->base.base.resv = &fbo->base.base._resv;
>+	reservation_object_init(fbo->base.base.resv);
>+	ret = reservation_object_trylock(fbo->base.base.resv);
> 	WARN_ON(!ret);
> 
> 	*new_obj = &fbo->base;
>@@ -689,7 +689,7 @@
> 	int ret;
> 	struct ttm_buffer_object *ghost_obj;
> 
>-	reservation_object_add_excl_fence(bo->resv, fence);
>+	reservation_object_add_excl_fence(bo->base.resv, fence);
> 	if (evict) {
> 		ret = ttm_bo_wait(bo, false, false);
> 		if (ret)
>@@ -716,7 +716,7 @@
> 		if (ret)
> 			return ret;
> 
>-		reservation_object_add_excl_fence(ghost_obj->resv, fence);
>+		reservation_object_add_excl_fence(ghost_obj->base.resv, fence);
> 
> 		/**
> 		 * If we're not moving to fixed memory, the TTM object
>@@ -752,7 +752,7 @@
> 
> 	int ret;
> 
>-	reservation_object_add_excl_fence(bo->resv, fence);
>+	reservation_object_add_excl_fence(bo->base.resv, fence);
> 
> 	if (!evict) {
> 		struct ttm_buffer_object *ghost_obj;
>@@ -772,7 +772,7 @@
> 		if (ret)
> 			return ret;
> 
>-		reservation_object_add_excl_fence(ghost_obj->resv, fence);
>+		reservation_object_add_excl_fence(ghost_obj->base.resv, fence);
> 
> 		/**
> 		 * If we're not moving to fixed memory, the TTM object
>@@ -841,7 +841,7 @@
> 	if (ret)
> 		return ret;
> 
>-	ret = reservation_object_copy_fences(ghost->resv, bo->resv);
>+	ret = reservation_object_copy_fences(ghost->base.resv, bo->base.resv);
> 	/* Last resort, wait for the BO to be idle when we are OOM */
> 	if (ret)
> 		ttm_bo_wait(bo, false, false);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ttm/ttm_bo_vm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ttm/ttm_bo_vm.c
>--- linux-5.3-rc6/drivers/gpu/drm/ttm/ttm_bo_vm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ttm/ttm_bo_vm.c	2019-08-31 15:01:12.135736193 -0500
>@@ -71,7 +71,7 @@
> 		ttm_bo_get(bo);
> 		up_read(&vmf->vma->vm_mm->mmap_sem);
> 		(void) dma_fence_wait(bo->moving, true);
>-		reservation_object_unlock(bo->resv);
>+		reservation_object_unlock(bo->base.resv);
> 		ttm_bo_put(bo);
> 		goto out_unlock;
> 	}
>@@ -131,7 +131,7 @@
> 	 * for reserve, and if it fails, retry the fault after waiting
> 	 * for the buffer to become unreserved.
> 	 */
>-	if (unlikely(!reservation_object_trylock(bo->resv))) {
>+	if (unlikely(!reservation_object_trylock(bo->base.resv))) {
> 		if (vmf->flags & FAULT_FLAG_ALLOW_RETRY) {
> 			if (!(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) {
> 				ttm_bo_get(bo);
>@@ -211,9 +211,9 @@
> 	}
> 
> 	page_offset = ((address - vma->vm_start) >> PAGE_SHIFT) +
>-		vma->vm_pgoff - drm_vma_node_start(&bo->vma_node);
>+		vma->vm_pgoff - drm_vma_node_start(&bo->base.vma_node);
> 	page_last = vma_pages(vma) + vma->vm_pgoff -
>-		drm_vma_node_start(&bo->vma_node);
>+		drm_vma_node_start(&bo->base.vma_node);
> 
> 	if (unlikely(page_offset >= bo->num_pages)) {
> 		ret = VM_FAULT_SIGBUS;
>@@ -267,7 +267,7 @@
> 			} else if (unlikely(!page)) {
> 				break;
> 			}
>-			page->index = drm_vma_node_start(&bo->vma_node) +
>+			page->index = drm_vma_node_start(&bo->base.vma_node) +
> 				page_offset;
> 			pfn = page_to_pfn(page);
> 		}
>@@ -296,7 +296,7 @@
> out_io_unlock:
> 	ttm_mem_io_unlock(man);
> out_unlock:
>-	reservation_object_unlock(bo->resv);
>+	reservation_object_unlock(bo->base.resv);
> 	return ret;
> }
> 
>@@ -413,7 +413,8 @@
> 
> 	node = drm_vma_offset_lookup_locked(&bdev->vma_manager, offset, pages);
> 	if (likely(node)) {
>-		bo = container_of(node, struct ttm_buffer_object, vma_node);
>+		bo = container_of(node, struct ttm_buffer_object,
>+				  base.vma_node);
> 		bo = ttm_bo_get_unless_zero(bo);
> 	}
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ttm/ttm_execbuf_util.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ttm/ttm_execbuf_util.c
>--- linux-5.3-rc6/drivers/gpu/drm/ttm/ttm_execbuf_util.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ttm/ttm_execbuf_util.c	2019-08-31 15:01:12.135736193 -0500
>@@ -39,7 +39,7 @@
> 	list_for_each_entry_continue_reverse(entry, list, head) {
> 		struct ttm_buffer_object *bo = entry->bo;
> 
>-		reservation_object_unlock(bo->resv);
>+		reservation_object_unlock(bo->base.resv);
> 	}
> }
> 
>@@ -71,7 +71,7 @@
> 
> 		if (list_empty(&bo->lru))
> 			ttm_bo_add_to_lru(bo);
>-		reservation_object_unlock(bo->resv);
>+		reservation_object_unlock(bo->base.resv);
> 	}
> 	spin_unlock(&glob->lru_lock);
> 
>@@ -114,7 +114,7 @@
> 
> 		ret = __ttm_bo_reserve(bo, intr, (ticket == NULL), ticket);
> 		if (!ret && unlikely(atomic_read(&bo->cpu_writers) > 0)) {
>-			reservation_object_unlock(bo->resv);
>+			reservation_object_unlock(bo->base.resv);
> 
> 			ret = -EBUSY;
> 
>@@ -130,7 +130,7 @@
> 			if (!entry->num_shared)
> 				continue;
> 
>-			ret = reservation_object_reserve_shared(bo->resv,
>+			ret = reservation_object_reserve_shared(bo->base.resv,
> 								entry->num_shared);
> 			if (!ret)
> 				continue;
>@@ -144,16 +144,16 @@
> 
> 		if (ret == -EDEADLK) {
> 			if (intr) {
>-				ret = ww_mutex_lock_slow_interruptible(&bo->resv->lock,
>-								       ticket);
>+				ret = reservation_object_lock_slow_interruptible(bo->base.resv,
>+										 ticket);
> 			} else {
>-				ww_mutex_lock_slow(&bo->resv->lock, ticket);
>+				reservation_object_lock_slow(bo->base.resv, ticket);
> 				ret = 0;
> 			}
> 		}
> 
> 		if (!ret && entry->num_shared)
>-			ret = reservation_object_reserve_shared(bo->resv,
>+			ret = reservation_object_reserve_shared(bo->base.resv,
> 								entry->num_shared);
> 
> 		if (unlikely(ret != 0)) {
>@@ -201,14 +201,14 @@
> 	list_for_each_entry(entry, list, head) {
> 		bo = entry->bo;
> 		if (entry->num_shared)
>-			reservation_object_add_shared_fence(bo->resv, fence);
>+			reservation_object_add_shared_fence(bo->base.resv, fence);
> 		else
>-			reservation_object_add_excl_fence(bo->resv, fence);
>+			reservation_object_add_excl_fence(bo->base.resv, fence);
> 		if (list_empty(&bo->lru))
> 			ttm_bo_add_to_lru(bo);
> 		else
> 			ttm_bo_move_to_lru_tail(bo, NULL);
>-		reservation_object_unlock(bo->resv);
>+		reservation_object_unlock(bo->base.resv);
> 	}
> 	spin_unlock(&glob->lru_lock);
> 	if (ticket)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/ttm/ttm_tt.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/ttm/ttm_tt.c
>--- linux-5.3-rc6/drivers/gpu/drm/ttm/ttm_tt.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/ttm/ttm_tt.c	2019-08-31 15:01:12.135736193 -0500
>@@ -48,7 +48,7 @@
> 	struct ttm_bo_device *bdev = bo->bdev;
> 	uint32_t page_flags = 0;
> 
>-	reservation_object_assert_held(bo->resv);
>+	reservation_object_assert_held(bo->base.resv);
> 
> 	if (bdev->need_dma32)
> 		page_flags |= TTM_PAGE_FLAG_DMA32;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tve200/tve200_display.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tve200/tve200_display.c
>--- linux-5.3-rc6/drivers/gpu/drm/tve200/tve200_display.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tve200/tve200_display.c	2019-08-31 15:01:12.135736193 -0500
>@@ -9,16 +9,18 @@
>  * Copyright (C) 2011 Texas Instruments
>  * Copyright (C) 2017 Eric Anholt
>  */
>+
> #include <linux/clk.h>
> #include <linux/version.h>
> #include <linux/dma-buf.h>
> #include <linux/of_graph.h>
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_panel.h>
>+#include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
>-#include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_panel.h>
>+#include <drm/drm_vblank.h>
> 
> #include "tve200_drm.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tve200/tve200_drm.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/tve200/tve200_drm.h
>--- linux-5.3-rc6/drivers/gpu/drm/tve200/tve200_drm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tve200/tve200_drm.h	2019-08-31 15:01:12.135736193 -0500
>@@ -13,6 +13,18 @@
> #ifndef _TVE200_DRM_H_
> #define _TVE200_DRM_H_
> 
>+#include <linux/irqreturn.h>
>+
>+#include <drm/drm_simple_kms_helper.h>
>+
>+struct clk;
>+struct drm_bridge;
>+struct drm_connector;
>+struct drm_device;
>+struct drm_file;
>+struct drm_mode_create_dumb;
>+struct drm_panel;
>+
> /* Bits 2-31 are valid physical base addresses */
> #define TVE200_Y_FRAME_BASE_ADDR	0x00
> #define TVE200_U_FRAME_BASE_ADDR	0x04
>@@ -89,9 +101,6 @@
> #define TVE200_CTRL_4			0x24
> #define TVE200_CTRL_4_RESET		BIT(0) /* triggers reset of TVE200 */
> 
>-#include <drm/drm_gem.h>
>-#include <drm/drm_simple_kms_helper.h>
>-
> struct tve200_drm_dev_private {
> 	struct drm_device *drm;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/tve200/tve200_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/tve200/tve200_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/tve200/tve200_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/tve200/tve200_drv.c	2019-08-31 15:01:12.135736193 -0500
>@@ -37,9 +37,9 @@
> #include <linux/slab.h>
> #include <linux/version.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_bridge.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_fb_helper.h>
> #include <drm/drm_gem_cma_helper.h>
>@@ -47,6 +47,7 @@
> #include <drm/drm_of.h>
> #include <drm/drm_panel.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "tve200_drm.h"
> 
>@@ -137,8 +138,7 @@
> DEFINE_DRM_GEM_CMA_FOPS(drm_fops);
> 
> static struct drm_driver tve200_drm_driver = {
>-	.driver_features =
>-		DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | DRIVER_ATOMIC,
>+	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> 	.ioctls = NULL,
> 	.fops = &drm_fops,
> 	.name = "tve200",
>@@ -153,8 +153,6 @@
> 
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_import = drm_gem_prime_import,
>-	.gem_prime_export = drm_gem_prime_export,
> 	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap = drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/udl/udl_connector.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_connector.c
>--- linux-5.3-rc6/drivers/gpu/drm/udl/udl_connector.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_connector.c	2019-08-31 15:01:12.135736193 -0500
>@@ -7,11 +7,9 @@
>  * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_crtc.h>
>-#include <drm/drm_edid.h>
> #include <drm/drm_crtc_helper.h>
> #include <drm/drm_probe_helper.h>
>+
> #include "udl_connector.h"
> #include "udl_drv.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/udl/udl_connector.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_connector.h
>--- linux-5.3-rc6/drivers/gpu/drm/udl/udl_connector.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_connector.h	2019-08-31 15:01:12.135736193 -0500
>@@ -3,6 +3,8 @@
> 
> #include <drm/drm_crtc.h>
> 
>+struct edid;
>+
> struct udl_drm_connector {
> 	struct drm_connector connector;
> 	/* last udl_detect edid */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/udl/udl_dmabuf.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_dmabuf.c
>--- linux-5.3-rc6/drivers/gpu/drm/udl/udl_dmabuf.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_dmabuf.c	2019-08-31 15:01:12.135736193 -0500
>@@ -5,11 +5,13 @@
>  * Copyright (c) 2014 The Chromium OS Authors
>  */
> 
>-#include <drm/drmP.h>
>-#include "udl_drv.h"
> #include <linux/shmem_fs.h>
> #include <linux/dma-buf.h>
> 
>+#include <drm/drm_prime.h>
>+
>+#include "udl_drv.h"
>+
> struct udl_drm_dmabuf_attachment {
> 	struct sg_table sgt;
> 	enum dma_data_direction dir;
>@@ -170,8 +172,7 @@
> 	.release		= drm_gem_dmabuf_release,
> };
> 
>-struct dma_buf *udl_gem_prime_export(struct drm_device *dev,
>-				     struct drm_gem_object *obj, int flags)
>+struct dma_buf *udl_gem_prime_export(struct drm_gem_object *obj, int flags)
> {
> 	DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
> 
>@@ -180,7 +181,7 @@
> 	exp_info.flags = flags;
> 	exp_info.priv = obj;
> 
>-	return drm_gem_dmabuf_export(dev, &exp_info);
>+	return drm_gem_dmabuf_export(obj->dev, &exp_info);
> }
> 
> static int udl_prime_create(struct drm_device *dev,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/udl/udl_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/udl/udl_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_drv.c	2019-08-31 15:01:12.135736193 -0500
>@@ -4,9 +4,14 @@
>  */
> 
> #include <linux/module.h>
>-#include <drm/drmP.h>
>+
> #include <drm/drm_crtc_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_ioctl.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_print.h>
>+
> #include "udl_drv.h"
> 
> static int udl_usb_suspend(struct usb_interface *interface,
>@@ -54,7 +59,7 @@
> }
> 
> static struct drm_driver driver = {
>-	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME,
>+	.driver_features = DRIVER_MODESET | DRIVER_GEM,
> 	.release = udl_driver_release,
> 
> 	/* gem hooks */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/udl/udl_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/udl/udl_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_drv.h	2019-08-31 15:01:12.135736193 -0500
>@@ -11,9 +11,15 @@
> #ifndef UDL_DRV_H
> #define UDL_DRV_H
> 
>+#include <linux/mm_types.h>
> #include <linux/usb.h>
>+
>+#include <drm/drm_device.h>
>+#include <drm/drm_framebuffer.h>
> #include <drm/drm_gem.h>
>-#include <linux/mm_types.h>
>+
>+struct drm_encoder;
>+struct drm_mode_create_dumb;
> 
> #define DRIVER_NAME		"udl"
> #define DRIVER_DESC		"DisplayLink"
>@@ -126,8 +132,7 @@
> void udl_gem_free_object(struct drm_gem_object *gem_obj);
> struct udl_gem_object *udl_gem_alloc_object(struct drm_device *dev,
> 					    size_t size);
>-struct dma_buf *udl_gem_prime_export(struct drm_device *dev,
>-				     struct drm_gem_object *obj, int flags);
>+struct dma_buf *udl_gem_prime_export(struct drm_gem_object *obj, int flags);
> struct drm_gem_object *udl_gem_prime_import(struct drm_device *dev,
> 				struct dma_buf *dma_buf);
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/udl/udl_encoder.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_encoder.c
>--- linux-5.3-rc6/drivers/gpu/drm/udl/udl_encoder.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_encoder.c	2019-08-31 15:01:12.135736193 -0500
>@@ -7,9 +7,9 @@
>  * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_crtc.h>
>-#include <drm/drm_crtc_helper.h>
>+#include <drm/drm_encoder.h>
>+#include <drm/drm_modeset_helper_vtables.h>
>+
> #include "udl_drv.h"
> 
> /* dummy encoder */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/udl/udl_fb.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_fb.c
>--- linux-5.3-rc6/drivers/gpu/drm/udl/udl_fb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_fb.c	2019-08-31 15:01:12.135736193 -0500
>@@ -7,18 +7,17 @@
>  * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
>  * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
>  */
>-#include <linux/module.h>
>-#include <linux/slab.h>
>-#include <linux/fb.h>
>+
>+#include <linux/moduleparam.h>
> #include <linux/dma-buf.h>
>-#include <linux/mem_encrypt.h>
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_crtc.h>
> #include <drm/drm_crtc_helper.h>
>-#include "udl_drv.h"
>-
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_modeset_helper.h>
>+
>+#include "udl_drv.h"
> 
> #define DL_DEFIO_WRITE_DELAY    (HZ/20) /* fb_deferred_io.delay in jiffies */
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/udl/udl_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/udl/udl_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_gem.c	2019-08-31 15:01:12.135736193 -0500
>@@ -3,10 +3,13 @@
>  * Copyright (C) 2012 Red Hat
>  */
> 
>-#include <drm/drmP.h>
>-#include "udl_drv.h"
>-#include <linux/shmem_fs.h>
> #include <linux/dma-buf.h>
>+#include <linux/vmalloc.h>
>+
>+#include <drm/drm_mode.h>
>+#include <drm/drm_prime.h>
>+
>+#include "udl_drv.h"
> 
> struct udl_gem_object *udl_gem_alloc_object(struct drm_device *dev,
> 					    size_t size)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/udl/udl_main.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_main.c
>--- linux-5.3-rc6/drivers/gpu/drm/udl/udl_main.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_main.c	2019-08-31 15:01:12.136736193 -0500
>@@ -7,9 +7,11 @@
>  * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com>
>  * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
>  */
>-#include <drm/drmP.h>
>-#include <drm/drm_crtc_helper.h>
>+
>+#include <drm/drm.h>
>+#include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
>+
> #include "udl_drv.h"
> 
> /* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/udl/udl_modeset.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_modeset.c
>--- linux-5.3-rc6/drivers/gpu/drm/udl/udl_modeset.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_modeset.c	2019-08-31 15:01:12.136736193 -0500
>@@ -9,10 +9,10 @@
> 
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_crtc.h>
> #include <drm/drm_crtc_helper.h>
>-#include <drm/drm_plane_helper.h>
>+#include <drm/drm_modeset_helper_vtables.h>
>+#include <drm/drm_vblank.h>
>+
> #include "udl_drv.h"
> 
> /*
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/udl/udl_transfer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_transfer.c
>--- linux-5.3-rc6/drivers/gpu/drm/udl/udl_transfer.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/udl/udl_transfer.c	2019-08-31 15:01:12.136736193 -0500
>@@ -7,12 +7,8 @@
>  * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com>
>  */
> 
>-#include <linux/module.h>
>-#include <linux/slab.h>
>-#include <linux/fb.h>
> #include <asm/unaligned.h>
> 
>-#include <drm/drmP.h>
> #include "udl_drv.h"
> 
> #define MAX_CMD_PIXELS		255
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/v3d/v3d_debugfs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/v3d/v3d_debugfs.c
>--- linux-5.3-rc6/drivers/gpu/drm/v3d/v3d_debugfs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/v3d/v3d_debugfs.c	2019-08-31 15:01:12.136736193 -0500
>@@ -6,7 +6,8 @@
> #include <linux/debugfs.h>
> #include <linux/pm_runtime.h>
> #include <linux/seq_file.h>
>-#include <drm/drmP.h>
>+
>+#include <drm/drm_debugfs.h>
> 
> #include "v3d_drv.h"
> #include "v3d_regs.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/v3d/v3d_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/v3d/v3d_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/v3d/v3d_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/v3d/v3d_drv.c	2019-08-31 15:01:12.136736193 -0500
>@@ -14,16 +14,19 @@
> 
> #include <linux/clk.h>
> #include <linux/device.h>
>+#include <linux/dma-mapping.h>
> #include <linux/io.h>
> #include <linux/module.h>
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/reset.h>
>+
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_fb_helper.h>
>+#include <uapi/drm/v3d_drm.h>
> 
>-#include "uapi/drm/v3d_drm.h"
> #include "v3d_drv.h"
> #include "v3d_regs.h"
> 
>@@ -188,7 +191,6 @@
> static struct drm_driver v3d_drm_driver = {
> 	.driver_features = (DRIVER_GEM |
> 			    DRIVER_RENDER |
>-			    DRIVER_PRIME |
> 			    DRIVER_SYNCOBJ),
> 
> 	.open = v3d_open,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/v3d/v3d_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/v3d/v3d_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/v3d/v3d_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/v3d/v3d_drv.h	2019-08-31 15:01:12.136736193 -0500
>@@ -1,14 +1,23 @@
> // SPDX-License-Identifier: GPL-2.0+
> /* Copyright (C) 2015-2018 Broadcom */
> 
>-#include <linux/mm_types.h>
>-#include <drm/drmP.h>
>+#include <linux/delay.h>
>+#include <linux/mutex.h>
>+#include <linux/spinlock_types.h>
>+#include <linux/workqueue.h>
>+
> #include <drm/drm_encoder.h>
> #include <drm/drm_gem.h>
> #include <drm/drm_gem_shmem_helper.h>
> #include <drm/gpu_scheduler.h>
>+
> #include "uapi/drm/v3d_drm.h"
> 
>+struct clk;
>+struct device;
>+struct platform_device;
>+struct reset_control;
>+
> #define GMP_GRANULARITY (128 * 1024)
> 
> /* Enum for each of the V3D queues. */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/v3d/v3d_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/v3d/v3d_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/v3d/v3d_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/v3d/v3d_gem.c	2019-08-31 15:01:12.136736193 -0500
>@@ -1,17 +1,19 @@
> // SPDX-License-Identifier: GPL-2.0+
> /* Copyright (C) 2014-2018 Broadcom */
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_syncobj.h>
>+#include <linux/device.h>
>+#include <linux/dma-mapping.h>
>+#include <linux/io.h>
> #include <linux/module.h>
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/reset.h>
>-#include <linux/device.h>
>-#include <linux/io.h>
> #include <linux/sched/signal.h>
>+#include <linux/uaccess.h>
>+
>+#include <drm/drm_syncobj.h>
>+#include <uapi/drm/v3d_drm.h>
> 
>-#include "uapi/drm/v3d_drm.h"
> #include "v3d_drv.h"
> #include "v3d_regs.h"
> #include "v3d_trace.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/v3d/v3d_irq.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/v3d/v3d_irq.c
>--- linux-5.3-rc6/drivers/gpu/drm/v3d/v3d_irq.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/v3d/v3d_irq.c	2019-08-31 15:01:12.136736193 -0500
>@@ -13,6 +13,8 @@
>  * current job can make progress.
>  */
> 
>+#include <linux/platform_device.h>
>+
> #include "v3d_drv.h"
> #include "v3d_regs.h"
> #include "v3d_trace.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vboxvideo/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/vboxvideo/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/vboxvideo/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vboxvideo/Makefile	2019-08-31 15:01:12.136736193 -0500
>@@ -1,6 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> vboxvideo-y :=  hgsmi_base.o modesetting.o vbva_base.o \
> 		vbox_drv.o vbox_fb.o vbox_hgsmi.o vbox_irq.o vbox_main.o \
>-		vbox_mode.o vbox_prime.o vbox_ttm.o
>+		vbox_mode.o vbox_ttm.o
> 
> obj-$(CONFIG_DRM_VBOXVIDEO) += vboxvideo.o
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vboxvideo/vbox_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vboxvideo/vbox_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/vboxvideo/vbox_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vboxvideo/vbox_drv.c	2019-08-31 15:01:12.136736193 -0500
>@@ -196,7 +196,7 @@
> 
> static struct drm_driver driver = {
> 	.driver_features =
>-	    DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | DRIVER_ATOMIC,
>+	    DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> 
> 	.lastclose = drm_fb_helper_lastclose,
> 
>@@ -210,17 +210,6 @@
> 	.patchlevel = DRIVER_PATCHLEVEL,
> 
> 	DRM_GEM_VRAM_DRIVER,
>-	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
>-	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_export = drm_gem_prime_export,
>-	.gem_prime_import = drm_gem_prime_import,
>-	.gem_prime_pin = vbox_gem_prime_pin,
>-	.gem_prime_unpin = vbox_gem_prime_unpin,
>-	.gem_prime_get_sg_table = vbox_gem_prime_get_sg_table,
>-	.gem_prime_import_sg_table = vbox_gem_prime_import_sg_table,
>-	.gem_prime_vmap = vbox_gem_prime_vmap,
>-	.gem_prime_vunmap = vbox_gem_prime_vunmap,
>-	.gem_prime_mmap = vbox_gem_prime_mmap,
> };
> 
> static int __init vbox_init(void)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vboxvideo/vbox_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/vboxvideo/vbox_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/vboxvideo/vbox_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vboxvideo/vbox_drv.h	2019-08-31 15:01:12.136736193 -0500
>@@ -167,18 +167,6 @@
> int vbox_gem_create(struct vbox_private *vbox,
> 		    u32 size, bool iskernel, struct drm_gem_object **obj);
> 
>-/* vbox_prime.c */
>-int vbox_gem_prime_pin(struct drm_gem_object *obj);
>-void vbox_gem_prime_unpin(struct drm_gem_object *obj);
>-struct sg_table *vbox_gem_prime_get_sg_table(struct drm_gem_object *obj);
>-struct drm_gem_object *vbox_gem_prime_import_sg_table(
>-	struct drm_device *dev, struct dma_buf_attachment *attach,
>-	struct sg_table *table);
>-void *vbox_gem_prime_vmap(struct drm_gem_object *obj);
>-void vbox_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
>-int vbox_gem_prime_mmap(struct drm_gem_object *obj,
>-			struct vm_area_struct *area);
>-
> /* vbox_irq.c */
> int vbox_irq_init(struct vbox_private *vbox);
> void vbox_irq_fini(struct vbox_private *vbox);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vboxvideo/vbox_main.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vboxvideo/vbox_main.c
>--- linux-5.3-rc6/drivers/gpu/drm/vboxvideo/vbox_main.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vboxvideo/vbox_main.c	2019-08-31 15:01:12.136736193 -0500
>@@ -292,7 +292,7 @@
> 		return ret;
> 	}
> 
>-	*obj = &gbo->gem;
>+	*obj = &gbo->bo.base;
> 
> 	return 0;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vboxvideo/vbox_prime.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vboxvideo/vbox_prime.c
>--- linux-5.3-rc6/drivers/gpu/drm/vboxvideo/vbox_prime.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vboxvideo/vbox_prime.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,56 +0,0 @@
>-// SPDX-License-Identifier: MIT
>-/*
>- * Copyright (C) 2017 Oracle Corporation
>- * Copyright 2017 Canonical
>- * Authors: Andreas Pokorny
>- */
>-
>-#include "vbox_drv.h"
>-
>-/*
>- * Based on qxl_prime.c:
>- * Empty Implementations as there should not be any other driver for a virtual
>- * device that might share buffers with vboxvideo
>- */
>-
>-int vbox_gem_prime_pin(struct drm_gem_object *obj)
>-{
>-	WARN_ONCE(1, "not implemented");
>-	return -ENODEV;
>-}
>-
>-void vbox_gem_prime_unpin(struct drm_gem_object *obj)
>-{
>-	WARN_ONCE(1, "not implemented");
>-}
>-
>-struct sg_table *vbox_gem_prime_get_sg_table(struct drm_gem_object *obj)
>-{
>-	WARN_ONCE(1, "not implemented");
>-	return ERR_PTR(-ENODEV);
>-}
>-
>-struct drm_gem_object *vbox_gem_prime_import_sg_table(
>-	struct drm_device *dev, struct dma_buf_attachment *attach,
>-	struct sg_table *table)
>-{
>-	WARN_ONCE(1, "not implemented");
>-	return ERR_PTR(-ENODEV);
>-}
>-
>-void *vbox_gem_prime_vmap(struct drm_gem_object *obj)
>-{
>-	WARN_ONCE(1, "not implemented");
>-	return ERR_PTR(-ENODEV);
>-}
>-
>-void vbox_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
>-{
>-	WARN_ONCE(1, "not implemented");
>-}
>-
>-int vbox_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *area)
>-{
>-	WARN_ONCE(1, "not implemented");
>-	return -ENODEV;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_bo.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_bo.c
>--- linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_bo.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_bo.c	2019-08-31 15:01:12.136736193 -0500
>@@ -655,8 +655,7 @@
> 	schedule_work(&vc4->bo_cache.time_work);
> }
> 
>-struct dma_buf *
>-vc4_prime_export(struct drm_device *dev, struct drm_gem_object *obj, int flags)
>+struct dma_buf * vc4_prime_export(struct drm_gem_object *obj, int flags)
> {
> 	struct vc4_bo *bo = to_vc4_bo(obj);
> 	struct dma_buf *dmabuf;
>@@ -678,7 +677,7 @@
> 		return ERR_PTR(ret);
> 	}
> 
>-	dmabuf = drm_gem_prime_export(dev, obj, flags);
>+	dmabuf = drm_gem_prime_export(obj, flags);
> 	if (IS_ERR(dmabuf))
> 		vc4_bo_dec_usecnt(bo);
> 
>@@ -791,8 +790,6 @@
> 	if (IS_ERR(obj))
> 		return obj;
> 
>-	obj->resv = attach->dmabuf->resv;
>-
> 	return obj;
> }
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_crtc.c	2019-08-31 15:01:12.137736193 -0500
>@@ -29,15 +29,18 @@
>  * ones that set the clock.
>  */
> 
>+#include <linux/clk.h>
>+#include <linux/component.h>
>+#include <linux/of_device.h>
>+
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_atomic_uapi.h>
>+#include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
>-#include <linux/clk.h>
>-#include <drm/drm_fb_cma_helper.h>
>-#include <linux/component.h>
>-#include <linux/of_device.h>
>+#include <drm/drm_vblank.h>
>+
> #include "vc4_drv.h"
> #include "vc4_regs.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_debugfs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_debugfs.c
>--- linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_debugfs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_debugfs.c	2019-08-31 15:01:12.137736193 -0500
>@@ -7,7 +7,6 @@
> #include <linux/circ_buf.h>
> #include <linux/ctype.h>
> #include <linux/debugfs.h>
>-#include <drm/drmP.h>
> 
> #include "vc4_drv.h"
> #include "vc4_regs.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_drv.c	2019-08-31 15:01:12.137736193 -0500
>@@ -23,16 +23,21 @@
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/device.h>
>+#include <linux/dma-mapping.h>
> #include <linux/io.h>
> #include <linux/module.h>
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
>+
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_fb_helper.h>
>-#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "uapi/drm/vc4_drm.h"
>+
> #include "vc4_drv.h"
> #include "vc4_regs.h"
> 
>@@ -177,7 +182,6 @@
> 			    DRIVER_ATOMIC |
> 			    DRIVER_GEM |
> 			    DRIVER_RENDER |
>-			    DRIVER_PRIME |
> 			    DRIVER_SYNCOBJ),
> 	.open = vc4_open,
> 	.postclose = vc4_close,
>@@ -199,7 +203,6 @@
> 
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_import = drm_gem_prime_import,
> 	.gem_prime_export = vc4_prime_export,
> 	.gem_prime_get_sg_table	= drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = vc4_prime_import_sg_table,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_drv.h	2019-08-31 15:01:12.137736193 -0500
>@@ -3,16 +3,23 @@
>  * Copyright (C) 2015 Broadcom
>  */
> 
>-#include <linux/mm_types.h>
>-#include <drm/drmP.h>
>-#include <drm/drm_util.h>
>+#include <linux/delay.h>
>+#include <linux/refcount.h>
>+#include <linux/uaccess.h>
>+
>+#include <drm/drm_atomic.h>
>+#include <drm/drm_debugfs.h>
>+#include <drm/drm_device.h>
> #include <drm/drm_encoder.h>
> #include <drm/drm_gem_cma_helper.h>
>-#include <drm/drm_atomic.h>
>-#include <drm/drm_syncobj.h>
>+#include <drm/drm_mm.h>
>+#include <drm/drm_modeset_lock.h>
> 
> #include "uapi/drm/vc4_drm.h"
> 
>+struct drm_device;
>+struct drm_gem_object;
>+
> /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
>  * this.
>  */
>@@ -705,8 +712,7 @@
> int vc4_dumb_create(struct drm_file *file_priv,
> 		    struct drm_device *dev,
> 		    struct drm_mode_create_dumb *args);
>-struct dma_buf *vc4_prime_export(struct drm_device *dev,
>-				 struct drm_gem_object *obj, int flags);
>+struct dma_buf *vc4_prime_export(struct drm_gem_object *obj, int flags);
> int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
> 			struct drm_file *file_priv);
> int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_dsi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_dsi.c
>--- linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_dsi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_dsi.c	2019-08-31 15:01:12.137736193 -0500
>@@ -18,22 +18,25 @@
>  * hopefully present.
>  */
> 
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_edid.h>
>-#include <drm/drm_mipi_dsi.h>
>-#include <drm/drm_of.h>
>-#include <drm/drm_panel.h>
>-#include <drm/drm_probe_helper.h>
>-#include <linux/clk.h>
> #include <linux/clk-provider.h>
>+#include <linux/clk.h>
> #include <linux/completion.h>
> #include <linux/component.h>
>+#include <linux/dma-mapping.h>
> #include <linux/dmaengine.h>
> #include <linux/i2c.h>
> #include <linux/io.h>
> #include <linux/of_address.h>
> #include <linux/of_platform.h>
> #include <linux/pm_runtime.h>
>+
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_edid.h>
>+#include <drm/drm_mipi_dsi.h>
>+#include <drm/drm_of.h>
>+#include <drm/drm_panel.h>
>+#include <drm/drm_probe_helper.h>
>+
> #include "vc4_drv.h"
> #include "vc4_regs.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_gem.c	2019-08-31 15:01:12.137736193 -0500
>@@ -29,6 +29,8 @@
> #include <linux/sched/signal.h>
> #include <linux/dma-fence-array.h>
> 
>+#include <drm/drm_syncobj.h>
>+
> #include "uapi/drm/vc4_drm.h"
> #include "vc4_drv.h"
> #include "vc4_regs.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_hvs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_hvs.c
>--- linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_hvs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_hvs.c	2019-08-31 15:01:12.137736193 -0500
>@@ -19,8 +19,11 @@
>  * each CRTC.
>  */
> 
>-#include <drm/drm_atomic_helper.h>
> #include <linux/component.h>
>+#include <linux/platform_device.h>
>+
>+#include <drm/drm_atomic_helper.h>
>+
> #include "vc4_drv.h"
> #include "vc4_regs.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_kms.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_kms.c
>--- linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_kms.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_kms.c	2019-08-31 15:01:12.137736193 -0500
>@@ -11,12 +11,14 @@
>  * crtc, HDMI encoder).
>  */
> 
>-#include <drm/drm_crtc.h>
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_crtc.h>
> #include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
>+
> #include "vc4_drv.h"
> #include "vc4_regs.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_plane.c	2019-08-31 15:01:12.138736193 -0500
>@@ -17,11 +17,14 @@
> 
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_atomic_uapi.h>
> #include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_plane_helper.h>
>-#include <drm/drm_atomic_uapi.h>
> 
> #include "uapi/drm/vc4_drm.h"
>+
> #include "vc4_drv.h"
> #include "vc4_regs.h"
> 
>@@ -1123,7 +1126,6 @@
> 			  struct drm_plane_state *state)
> {
> 	struct vc4_bo *bo;
>-	struct dma_fence *fence;
> 	int ret;
> 
> 	if (!state->fb)
>@@ -1131,8 +1133,7 @@
> 
> 	bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
> 
>-	fence = reservation_object_get_excl_rcu(bo->base.base.resv);
>-	drm_atomic_set_fence_for_plane(state, fence);
>+	drm_gem_fb_prepare_fb(plane, state);
> 
> 	if (plane->state->fb == state->fb)
> 		return 0;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_txp.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_txp.c
>--- linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_txp.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_txp.c	2019-08-31 15:01:12.138736193 -0500
>@@ -7,18 +7,20 @@
>  *	Boris Brezillon <boris.brezillon@bootlin.com>
>  */
> 
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_fb_cma_helper.h>
>-#include <drm/drm_edid.h>
>-#include <drm/drm_panel.h>
>-#include <drm/drm_probe_helper.h>
>-#include <drm/drm_writeback.h>
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/of_graph.h>
> #include <linux/of_platform.h>
> #include <linux/pm_runtime.h>
> 
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_edid.h>
>+#include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_panel.h>
>+#include <drm/drm_probe_helper.h>
>+#include <drm/drm_writeback.h>
>+
> #include "vc4_drv.h"
> #include "vc4_regs.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_v3d.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_v3d.c
>--- linux-5.3-rc6/drivers/gpu/drm/vc4/vc4_v3d.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vc4/vc4_v3d.c	2019-08-31 15:01:12.138736193 -0500
>@@ -7,7 +7,11 @@
> 
> #include <linux/clk.h>
> #include <linux/component.h>
>+#include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
>+
>+#include <drm/drm_irq.h>
>+
> #include "vc4_drv.h"
> #include "vc4_regs.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vgem/vgem_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vgem/vgem_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/vgem/vgem_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vgem/vgem_drv.c	2019-08-31 15:01:12.138736193 -0500
>@@ -30,10 +30,17 @@
>  * software renderer and the X server for efficient buffer sharing.
>  */
> 
>+#include <linux/dma-buf.h>
> #include <linux/module.h>
>-#include <linux/ramfs.h>
>+#include <linux/platform_device.h>
> #include <linux/shmem_fs.h>
>-#include <linux/dma-buf.h>
>+#include <linux/vmalloc.h>
>+
>+#include <drm/drm_drv.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_ioctl.h>
>+#include <drm/drm_prime.h>
>+
> #include "vgem_drv.h"
> 
> #define DRIVER_NAME	"vgem"
>@@ -214,7 +221,7 @@
> 	args->size = gem_object->size;
> 	args->pitch = pitch;
> 
>-	DRM_DEBUG_DRIVER("Created object of size %lld\n", size);
>+	DRM_DEBUG("Created object of size %lld\n", size);
> 
> 	return 0;
> }
>@@ -246,8 +253,8 @@
> }
> 
> static struct drm_ioctl_desc vgem_ioctls[] = {
>-	DRM_IOCTL_DEF_DRV(VGEM_FENCE_ATTACH, vgem_fence_attach_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>-	DRM_IOCTL_DEF_DRV(VGEM_FENCE_SIGNAL, vgem_fence_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(VGEM_FENCE_ATTACH, vgem_fence_attach_ioctl, DRM_RENDER_ALLOW),
>+	DRM_IOCTL_DEF_DRV(VGEM_FENCE_SIGNAL, vgem_fence_signal_ioctl, DRM_RENDER_ALLOW),
> };
> 
> static int vgem_mmap(struct file *filp, struct vm_area_struct *vma)
>@@ -427,8 +434,7 @@
> }
> 
> static struct drm_driver vgem_driver = {
>-	.driver_features		= DRIVER_GEM | DRIVER_PRIME |
>-					  DRIVER_RENDER,
>+	.driver_features		= DRIVER_GEM | DRIVER_RENDER,
> 	.release			= vgem_release,
> 	.open				= vgem_open,
> 	.postclose			= vgem_postclose,
>@@ -446,7 +452,6 @@
> 	.gem_prime_pin = vgem_prime_pin,
> 	.gem_prime_unpin = vgem_prime_unpin,
> 	.gem_prime_import = vgem_prime_import,
>-	.gem_prime_export = drm_gem_prime_export,
> 	.gem_prime_import_sg_table = vgem_prime_import_sg_table,
> 	.gem_prime_get_sg_table = vgem_prime_get_sg_table,
> 	.gem_prime_vmap = vgem_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vgem/vgem_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/vgem/vgem_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/vgem/vgem_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vgem/vgem_drv.h	2019-08-31 15:01:12.138736193 -0500
>@@ -29,7 +29,6 @@
> #ifndef _VGEM_DRV_H_
> #define _VGEM_DRV_H_
> 
>-#include <drm/drmP.h>
> #include <drm/drm_gem.h>
> #include <drm/drm_cache.h>
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vgem/vgem_fence.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vgem/vgem_fence.c
>--- linux-5.3-rc6/drivers/gpu/drm/vgem/vgem_fence.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vgem/vgem_fence.c	2019-08-31 15:01:12.138736193 -0500
>@@ -23,6 +23,8 @@
> #include <linux/dma-buf.h>
> #include <linux/reservation.h>
> 
>+#include <drm/drm_file.h>
>+
> #include "vgem_drv.h"
> 
> #define VGEM_FENCE_TIMEOUT (10*HZ)
>@@ -100,22 +102,6 @@
> 	return &fence->base;
> }
> 
>-static int attach_dmabuf(struct drm_device *dev,
>-			 struct drm_gem_object *obj)
>-{
>-	struct dma_buf *dmabuf;
>-
>-	if (obj->dma_buf)
>-		return 0;
>-
>-	dmabuf = dev->driver->gem_prime_export(dev, obj, 0);
>-	if (IS_ERR(dmabuf))
>-		return PTR_ERR(dmabuf);
>-
>-	obj->dma_buf = dmabuf;
>-	return 0;
>-}
>-
> /*
>  * vgem_fence_attach_ioctl (DRM_IOCTL_VGEM_FENCE_ATTACH):
>  *
>@@ -157,10 +143,6 @@
> 	if (!obj)
> 		return -ENOENT;
> 
>-	ret = attach_dmabuf(dev, obj);
>-	if (ret)
>-		goto err;
>-
> 	fence = vgem_fence_create(vfile, arg->flags);
> 	if (!fence) {
> 		ret = -ENOMEM;
>@@ -168,7 +150,7 @@
> 	}
> 
> 	/* Check for a conflicting fence */
>-	resv = obj->dma_buf->resv;
>+	resv = obj->resv;
> 	if (!reservation_object_test_signaled_rcu(resv,
> 						  arg->flags & VGEM_FENCE_WRITE)) {
> 		ret = -EBUSY;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/via/via_dmablit.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_dmablit.c
>--- linux-5.3-rc6/drivers/gpu/drm/via/via_dmablit.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_dmablit.c	2019-08-31 15:01:12.139736193 -0500
>@@ -34,13 +34,16 @@
>  * the same DMA mappings?
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/via_drm.h>
>-#include "via_drv.h"
>-#include "via_dmablit.h"
>-
> #include <linux/pagemap.h>
> #include <linux/slab.h>
>+#include <linux/vmalloc.h>
>+
>+#include <drm/drm_device.h>
>+#include <drm/drm_pci.h>
>+#include <drm/via_drm.h>
>+
>+#include "via_dmablit.h"
>+#include "via_drv.h"
> 
> #define VIA_PGDN(x)	     (((unsigned long)(x)) & PAGE_MASK)
> #define VIA_PGOFF(x)	    (((unsigned long)(x)) & ~PAGE_MASK)
>@@ -214,16 +217,16 @@
> {
> 	drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
> 
>-	VIA_WRITE(VIA_PCI_DMA_MAR0 + engine*0x10, 0);
>-	VIA_WRITE(VIA_PCI_DMA_DAR0 + engine*0x10, 0);
>-	VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD |
>+	via_write(dev_priv, VIA_PCI_DMA_MAR0 + engine*0x10, 0);
>+	via_write(dev_priv, VIA_PCI_DMA_DAR0 + engine*0x10, 0);
>+	via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD |
> 		  VIA_DMA_CSR_DE);
>-	VIA_WRITE(VIA_PCI_DMA_MR0  + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE);
>-	VIA_WRITE(VIA_PCI_DMA_BCR0 + engine*0x10, 0);
>-	VIA_WRITE(VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start);
>+	via_write(dev_priv, VIA_PCI_DMA_MR0  + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE);
>+	via_write(dev_priv, VIA_PCI_DMA_BCR0 + engine*0x10, 0);
>+	via_write(dev_priv, VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start);
> 	wmb();
>-	VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS);
>-	VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04);
>+	via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS);
>+	via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04);
> }
> 
> /*
>@@ -291,7 +294,7 @@
> {
> 	drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
> 
>-	VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA);
>+	via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA);
> }
> 
> static void
>@@ -299,7 +302,7 @@
> {
> 	drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
> 
>-	VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD);
>+	via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD);
> }
> 
> 
>@@ -330,7 +333,7 @@
> 		spin_lock_irqsave(&blitq->blit_lock, irqsave);
> 
> 	done_transfer = blitq->is_active &&
>-	  ((status = VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD);
>+	  ((status = via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD);
> 	done_transfer = done_transfer || (blitq->aborting && !(status & VIA_DMA_CSR_DE));
> 
> 	cur = blitq->cur;
>@@ -349,7 +352,7 @@
> 		 * Clear transfer done flag.
> 		 */
> 
>-		VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04,  VIA_DMA_CSR_TD);
>+		via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04,  VIA_DMA_CSR_TD);
> 
> 		blitq->is_active = 0;
> 		blitq->aborting = 0;
>@@ -436,7 +439,7 @@
> 	int ret = 0;
> 
> 	if (via_dmablit_active(blitq, engine, handle, &queue)) {
>-		DRM_WAIT_ON(ret, *queue, 3 * HZ,
>+		VIA_WAIT_ON(ret, *queue, 3 * HZ,
> 			    !via_dmablit_active(blitq, engine, handle, NULL));
> 	}
> 	DRM_DEBUG("DMA blit sync handle 0x%x engine %d returned %d\n",
>@@ -687,7 +690,7 @@
> 	while (blitq->num_free == 0) {
> 		spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
> 
>-		DRM_WAIT_ON(ret, blitq->busy_queue, HZ, blitq->num_free > 0);
>+		VIA_WAIT_ON(ret, blitq->busy_queue, HZ, blitq->num_free > 0);
> 		if (ret)
> 			return (-EINTR == ret) ? -EAGAIN : ret;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/via/via_dma.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_dma.c
>--- linux-5.3-rc6/drivers/gpu/drm/via/via_dma.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_dma.c	2019-08-31 15:01:12.138736193 -0500
>@@ -34,8 +34,15 @@
>  *    Thomas Hellstrom.
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/delay.h>
>+#include <linux/uaccess.h>
>+
>+#include <drm/drm.h>
>+#include <drm/drm_agpsupport.h>
>+#include <drm/drm_device.h>
>+#include <drm/drm_file.h>
> #include <drm/via_drm.h>
>+
> #include "via_drv.h"
> #include "via_3d_reg.h"
> 
>@@ -430,14 +437,14 @@
> 	diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
> 	count = 10000000;
> 	while (diff == 0 && count--) {
>-		paused = (VIA_READ(0x41c) & 0x80000000);
>+		paused = (via_read(dev_priv, 0x41c) & 0x80000000);
> 		if (paused)
> 			break;
> 		reader = *(dev_priv->hw_addr_ptr);
> 		diff = (uint32_t) (ptr - reader) - dev_priv->dma_diff;
> 	}
> 
>-	paused = VIA_READ(0x41c) & 0x80000000;
>+	paused = via_read(dev_priv, 0x41c) & 0x80000000;
> 
> 	if (paused && !no_pci_fire) {
> 		reader = *(dev_priv->hw_addr_ptr);
>@@ -454,10 +461,10 @@
> 			 * doesn't make a difference.
> 			 */
> 
>-			VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
>-			VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
>-			VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
>-			VIA_READ(VIA_REG_TRANSPACE);
>+			via_write(dev_priv, VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
>+			via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_hi);
>+			via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_lo);
>+			via_read(dev_priv, VIA_REG_TRANSPACE);
> 		}
> 	}
> 	return paused;
>@@ -467,10 +474,10 @@
> {
> 	int count = 10000000;
> 
>-	while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && --count)
>+	while (!(via_read(dev_priv, VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && --count)
> 		;
> 
>-	while (count && (VIA_READ(VIA_REG_STATUS) &
>+	while (count && (via_read(dev_priv, VIA_REG_STATUS) &
> 			   (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
> 			    VIA_3D_ENG_BUSY)))
> 		--count;
>@@ -536,21 +543,21 @@
> 	via_flush_write_combine();
> 	(void) *(volatile uint32_t *)dev_priv->last_pause_ptr;
> 
>-	VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
>-	VIA_WRITE(VIA_REG_TRANSPACE, command);
>-	VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
>-	VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
>+	via_write(dev_priv, VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
>+	via_write(dev_priv, VIA_REG_TRANSPACE, command);
>+	via_write(dev_priv, VIA_REG_TRANSPACE, start_addr_lo);
>+	via_write(dev_priv, VIA_REG_TRANSPACE, end_addr_lo);
> 
>-	VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
>-	VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
>+	via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_hi);
>+	via_write(dev_priv, VIA_REG_TRANSPACE, pause_addr_lo);
> 	wmb();
>-	VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
>-	VIA_READ(VIA_REG_TRANSPACE);
>+	via_write(dev_priv, VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
>+	via_read(dev_priv, VIA_REG_TRANSPACE);
> 
> 	dev_priv->dma_diff = 0;
> 
> 	count = 10000000;
>-	while (!(VIA_READ(0x41c) & 0x80000000) && count--);
>+	while (!(via_read(dev_priv, 0x41c) & 0x80000000) && count--);
> 
> 	reader = *(dev_priv->hw_addr_ptr);
> 	ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/via/via_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/via/via_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_drv.c	2019-08-31 15:01:12.139736193 -0500
>@@ -24,11 +24,14 @@
> 
> #include <linux/module.h>
> 
>-#include <drm/drmP.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_pci.h>
>+#include <drm/drm_pciids.h>
> #include <drm/via_drm.h>
>+
> #include "via_drv.h"
> 
>-#include <drm/drm_pciids.h>
> 
> static int via_driver_open(struct drm_device *dev, struct drm_file *file)
> {
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/via/via_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/via/via_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_drv.h	2019-08-31 15:01:12.139736193 -0500
>@@ -24,8 +24,16 @@
> #ifndef _VIA_DRV_H_
> #define _VIA_DRV_H_
> 
>-#include <drm/drm_mm.h>
>+#include <linux/irqreturn.h>
>+#include <linux/jiffies.h>
>+#include <linux/sched.h>
>+#include <linux/sched/signal.h>
>+#include <linux/wait.h>
>+
>+#include <drm/drm_ioctl.h>
> #include <drm/drm_legacy.h>
>+#include <drm/drm_mm.h>
>+#include <drm/via_drm.h>
> 
> #define DRIVER_AUTHOR	"Various"
> 
>@@ -113,12 +121,67 @@
> };
> 
> /* VIA MMIO register access */
>-#define VIA_BASE ((dev_priv->mmio))
>-
>-#define VIA_READ(reg)		DRM_READ32(VIA_BASE, reg)
>-#define VIA_WRITE(reg, val)	DRM_WRITE32(VIA_BASE, reg, val)
>-#define VIA_READ8(reg)		DRM_READ8(VIA_BASE, reg)
>-#define VIA_WRITE8(reg, val)	DRM_WRITE8(VIA_BASE, reg, val)
>+static inline u32 via_read(struct drm_via_private *dev_priv, u32 reg)
>+{
>+	return readl((void __iomem *)(dev_priv->mmio->handle + reg));
>+}
>+
>+static inline void via_write(struct drm_via_private *dev_priv, u32 reg,
>+			     u32 val)
>+{
>+	writel(val, (void __iomem *)(dev_priv->mmio->handle + reg));
>+}
>+
>+static inline void via_write8(struct drm_via_private *dev_priv, u32 reg,
>+			      u32 val)
>+{
>+	writeb(val, (void __iomem *)(dev_priv->mmio->handle + reg));
>+}
>+
>+static inline void via_write8_mask(struct drm_via_private *dev_priv,
>+				   u32 reg, u32 mask, u32 val)
>+{
>+	u32 tmp;
>+
>+	tmp = readb((void __iomem *)(dev_priv->mmio->handle + reg));
>+	tmp = (tmp & ~mask) | (val & mask);
>+	writeb(tmp, (void __iomem *)(dev_priv->mmio->handle + reg));
>+}
>+
>+/*
>+ * Poll in a loop waiting for 'contidition' to be true.
>+ * Note: A direct replacement with wait_event_interruptible_timeout()
>+ *       will not work unless driver is updated to emit wake_up()
>+ *       in relevant places that can impact the 'condition'
>+ *
>+ * Returns:
>+ *   ret keeps current value if 'condition' becomes true
>+ *   ret = -BUSY if timeout happens
>+ *   ret = -EINTR if a signal interrupted the waiting period
>+ */
>+#define VIA_WAIT_ON( ret, queue, timeout, condition )		\
>+do {								\
>+	DECLARE_WAITQUEUE(entry, current);			\
>+	unsigned long end = jiffies + (timeout);		\
>+	add_wait_queue(&(queue), &entry);			\
>+								\
>+	for (;;) {						\
>+		__set_current_state(TASK_INTERRUPTIBLE);	\
>+		if (condition)					\
>+			break;					\
>+		if (time_after_eq(jiffies, end)) {		\
>+			ret = -EBUSY;				\
>+			break;					\
>+		}						\
>+		schedule_timeout((HZ/100 > 1) ? HZ/100 : 1);	\
>+		if (signal_pending(current)) {			\
>+			ret = -EINTR;				\
>+			break;					\
>+		}						\
>+	}							\
>+	__set_current_state(TASK_RUNNING);			\
>+	remove_wait_queue(&(queue), &entry);			\
>+} while (0)
> 
> extern const struct drm_ioctl_desc via_ioctls[];
> extern int via_max_ioctl;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/via/via_irq.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_irq.c
>--- linux-5.3-rc6/drivers/gpu/drm/via/via_irq.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_irq.c	2019-08-31 15:01:12.139736193 -0500
>@@ -35,8 +35,10 @@
>  * The refresh rate is also calculated for video playback sync purposes.
>  */
> 
>-#include <drm/drmP.h>
>+#include <drm/drm_device.h>
>+#include <drm/drm_vblank.h>
> #include <drm/via_drm.h>
>+
> #include "via_drv.h"
> 
> #define VIA_REG_INTERRUPT       0x200
>@@ -108,7 +110,7 @@
> 	drm_via_irq_t *cur_irq = dev_priv->via_irqs;
> 	int i;
> 
>-	status = VIA_READ(VIA_REG_INTERRUPT);
>+	status = via_read(dev_priv, VIA_REG_INTERRUPT);
> 	if (status & VIA_IRQ_VBLANK_PENDING) {
> 		atomic_inc(&dev_priv->vbl_received);
> 		if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) {
>@@ -143,7 +145,7 @@
> 	}
> 
> 	/* Acknowledge interrupts */
>-	VIA_WRITE(VIA_REG_INTERRUPT, status);
>+	via_write(dev_priv, VIA_REG_INTERRUPT, status);
> 
> 
> 	if (handled)
>@@ -158,8 +160,8 @@
> 
> 	if (dev_priv) {
> 		/* Acknowledge interrupts */
>-		status = VIA_READ(VIA_REG_INTERRUPT);
>-		VIA_WRITE(VIA_REG_INTERRUPT, status |
>+		status = via_read(dev_priv, VIA_REG_INTERRUPT);
>+		via_write(dev_priv, VIA_REG_INTERRUPT, status |
> 			  dev_priv->irq_pending_mask);
> 	}
> }
>@@ -174,11 +176,11 @@
> 		return -EINVAL;
> 	}
> 
>-	status = VIA_READ(VIA_REG_INTERRUPT);
>-	VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE);
>+	status = via_read(dev_priv, VIA_REG_INTERRUPT);
>+	via_write(dev_priv, VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE);
> 
>-	VIA_WRITE8(0x83d4, 0x11);
>-	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
>+	via_write8(dev_priv, 0x83d4, 0x11);
>+	via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30);
> 
> 	return 0;
> }
>@@ -188,11 +190,11 @@
> 	drm_via_private_t *dev_priv = dev->dev_private;
> 	u32 status;
> 
>-	status = VIA_READ(VIA_REG_INTERRUPT);
>-	VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE);
>+	status = via_read(dev_priv, VIA_REG_INTERRUPT);
>+	via_write(dev_priv, VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE);
> 
>-	VIA_WRITE8(0x83d4, 0x11);
>-	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
>+	via_write8(dev_priv, 0x83d4, 0x11);
>+	via_write8_mask(dev_priv, 0x83d5, 0x30, 0);
> 
> 	if (pipe != 0)
> 		DRM_ERROR("%s:  bad crtc %u\n", __func__, pipe);
>@@ -233,12 +235,12 @@
> 	cur_irq = dev_priv->via_irqs + real_irq;
> 
> 	if (masks[real_irq][2] && !force_sequence) {
>-		DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
>-			    ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
>+		VIA_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
>+			    ((via_read(dev_priv, masks[irq][2]) & masks[irq][3]) ==
> 			     masks[irq][4]));
> 		cur_irq_sequence = atomic_read(&cur_irq->irq_received);
> 	} else {
>-		DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
>+		VIA_WAIT_ON(ret, cur_irq->irq_queue, 3 * HZ,
> 			    (((cur_irq_sequence =
> 			       atomic_read(&cur_irq->irq_received)) -
> 			      *sequence) <= (1 << 23)));
>@@ -292,8 +294,8 @@
> 		dev_priv->last_vblank_valid = 0;
> 
> 		/* Clear VSync interrupt regs */
>-		status = VIA_READ(VIA_REG_INTERRUPT);
>-		VIA_WRITE(VIA_REG_INTERRUPT, status &
>+		status = via_read(dev_priv, VIA_REG_INTERRUPT);
>+		via_write(dev_priv, VIA_REG_INTERRUPT, status &
> 			  ~(dev_priv->irq_enable_mask));
> 
> 		/* Clear bits if they're already high */
>@@ -310,13 +312,13 @@
> 	if (!dev_priv)
> 		return -EINVAL;
> 
>-	status = VIA_READ(VIA_REG_INTERRUPT);
>-	VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
>+	status = via_read(dev_priv, VIA_REG_INTERRUPT);
>+	via_write(dev_priv, VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL
> 		  | dev_priv->irq_enable_mask);
> 
> 	/* Some magic, oh for some data sheets ! */
>-	VIA_WRITE8(0x83d4, 0x11);
>-	VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
>+	via_write8(dev_priv, 0x83d4, 0x11);
>+	via_write8_mask(dev_priv, 0x83d5, 0x30, 0x30);
> 
> 	return 0;
> }
>@@ -331,11 +333,11 @@
> 
> 		/* Some more magic, oh for some data sheets ! */
> 
>-		VIA_WRITE8(0x83d4, 0x11);
>-		VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
>+		via_write8(dev_priv, 0x83d4, 0x11);
>+		via_write8_mask(dev_priv, 0x83d5, 0x30, 0);
> 
>-		status = VIA_READ(VIA_REG_INTERRUPT);
>-		VIA_WRITE(VIA_REG_INTERRUPT, status &
>+		status = via_read(dev_priv, VIA_REG_INTERRUPT);
>+		via_write(dev_priv, VIA_REG_INTERRUPT, status &
> 			  ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
> 	}
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/via/via_map.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_map.c
>--- linux-5.3-rc6/drivers/gpu/drm/via/via_map.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_map.c	2019-08-31 15:01:12.139736193 -0500
>@@ -21,8 +21,12 @@
>  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>  * DEALINGS IN THE SOFTWARE.
>  */
>-#include <drm/drmP.h>
>+
>+#include <drm/drm_device.h>
>+#include <drm/drm_pci.h>
>+#include <drm/drm_vblank.h>
> #include <drm/via_drm.h>
>+
> #include "via_drv.h"
> 
> static int via_do_init_map(struct drm_device *dev, drm_via_init_t *init)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/via/via_mm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_mm.c
>--- linux-5.3-rc6/drivers/gpu/drm/via/via_mm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_mm.c	2019-08-31 15:01:12.139736193 -0500
>@@ -25,8 +25,13 @@
>  * Authors: Thomas HellstrÃ¶m <thomas-at-tungstengraphics-dot-com>
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/slab.h>
>+
>+#include <drm/drm_device.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_irq.h>
> #include <drm/via_drm.h>
>+
> #include "via_drv.h"
> 
> #define VIA_MM_ALIGN_SHIFT 4
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/via/via_verifier.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_verifier.c
>--- linux-5.3-rc6/drivers/gpu/drm/via/via_verifier.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_verifier.c	2019-08-31 15:01:12.139736193 -0500
>@@ -28,13 +28,13 @@
>  * be very slow.
>  */
> 
>-#include "via_3d_reg.h"
>-#include <drm/drmP.h>
>-#include <drm/via_drm.h>
>+#include <drm/drm_device.h>
> #include <drm/drm_legacy.h>
>-#include "via_verifier.h"
>+#include <drm/via_drm.h>
>+
>+#include "via_3d_reg.h"
> #include "via_drv.h"
>-#include <linux/kernel.h>
>+#include "via_verifier.h"
> 
> typedef enum {
> 	state_command,
>@@ -725,14 +725,14 @@
> 	next_fire = dev_priv->fire_offsets[*fire_count];
> 	buf++;
> 	cmd = (*buf & 0xFFFF0000) >> 16;
>-	VIA_WRITE(HC_REG_TRANS_SET + HC_REG_BASE, *buf++);
>+	via_write(dev_priv, HC_REG_TRANS_SET + HC_REG_BASE, *buf++);
> 	switch (cmd) {
> 	case HC_ParaType_CmdVdata:
> 		while ((buf < buf_end) &&
> 		       (*fire_count < dev_priv->num_fire_offsets) &&
> 		       (*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB) {
> 			while (buf <= next_fire) {
>-				VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
>+				via_write(dev_priv, HC_REG_TRANS_SPACE + HC_REG_BASE +
> 					  (burst & 63), *buf++);
> 				burst += 4;
> 			}
>@@ -753,7 +753,7 @@
> 			    (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6)
> 				break;
> 
>-			VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE +
>+			via_write(dev_priv, HC_REG_TRANS_SPACE + HC_REG_BASE +
> 				  (burst & 63), *buf++);
> 			burst += 4;
> 		}
>@@ -843,7 +843,7 @@
> 		cmd = *buf;
> 		if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
> 			break;
>-		VIA_WRITE((cmd & ~HALCYON_HEADER1MASK) << 2, *++buf);
>+		via_write(dev_priv, (cmd & ~HALCYON_HEADER1MASK) << 2, *++buf);
> 		buf++;
> 	}
> 	*buffer = buf;
>@@ -894,7 +894,7 @@
> 	i = count = *buf;
> 	buf += 3;
> 	while (i--)
>-		VIA_WRITE(addr, *buf++);
>+		via_write(dev_priv, addr, *buf++);
> 	if (count & 3)
> 		buf += 4 - (count & 3);
> 	*buffer = buf;
>@@ -950,7 +950,7 @@
> 	buf += 3;
> 	while (i--) {
> 		addr = *buf++;
>-		VIA_WRITE(addr, *buf++);
>+		via_write(dev_priv, addr, *buf++);
> 	}
> 	count <<= 1;
> 	if (count & 3)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/via/via_video.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_video.c
>--- linux-5.3-rc6/drivers/gpu/drm/via/via_video.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/via/via_video.c	2019-08-31 15:01:12.139736193 -0500
>@@ -25,8 +25,9 @@
>  * Video and XvMC related functions.
>  */
> 
>-#include <drm/drmP.h>
>+#include <drm/drm_device.h>
> #include <drm/via_drm.h>
>+
> #include "via_drv.h"
> 
> void via_init_futex(drm_via_private_t *dev_priv)
>@@ -82,7 +83,7 @@
> 
> 	switch (fx->func) {
> 	case VIA_FUTEX_WAIT:
>-		DRM_WAIT_ON(ret, dev_priv->decoder_queue[fx->lock],
>+		VIA_WAIT_ON(ret, dev_priv->decoder_queue[fx->lock],
> 			    (fx->ms / 10) * (HZ / 100), *lock != fx->val);
> 		return ret;
> 	case VIA_FUTEX_WAKE:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_debugfs.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_debugfs.c
>--- linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_debugfs.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_debugfs.c	2019-08-31 15:01:12.139736193 -0500
>@@ -23,8 +23,8 @@
>  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  */
> 
>-#include <linux/debugfs.h>
>-#include <drm/drmP.h>
>+#include <drm/drm_debugfs.h>
>+#include <drm/drm_file.h>
> 
> #include "virtgpu_drv.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_display.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_display.c
>--- linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_display.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_display.c	2019-08-31 15:01:12.139736193 -0500
>@@ -25,11 +25,14 @@
>  * OTHER DEALINGS IN THE SOFTWARE.
>  */
> 
>-#include "virtgpu_drv.h"
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_damage_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_probe_helper.h>
>-#include <drm/drm_damage_helper.h>
>+#include <drm/drm_vblank.h>
>+
>+#include "virtgpu_drv.h"
> 
> #define XRES_MIN    32
> #define YRES_MIN    32
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_drv.c	2019-08-31 15:01:12.139736193 -0500
>@@ -29,10 +29,13 @@
> #include <linux/module.h>
> #include <linux/console.h>
> #include <linux/pci.h>
>-#include <drm/drmP.h>
>+
> #include <drm/drm.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_file.h>
> 
> #include "virtgpu_drv.h"
>+
> static struct drm_driver driver;
> 
> static int virtio_gpu_modeset = -1;
>@@ -195,7 +198,7 @@
> };
> 
> static struct drm_driver driver = {
>-	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC,
>+	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_RENDER | DRIVER_ATOMIC,
> 	.open = virtio_gpu_driver_open,
> 	.postclose = virtio_gpu_driver_postclose,
> 
>@@ -207,8 +210,6 @@
> #endif
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_export = drm_gem_prime_export,
>-	.gem_prime_import = drm_gem_prime_import,
> 	.gem_prime_get_sg_table = virtgpu_gem_prime_get_sg_table,
> 	.gem_prime_import_sg_table = virtgpu_gem_prime_import_sg_table,
> 	.gem_prime_vmap = virtgpu_gem_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_drv.h	2019-08-31 15:01:12.139736193 -0500
>@@ -31,16 +31,16 @@
> #include <linux/virtio_config.h>
> #include <linux/virtio_gpu.h>
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_gem.h>
> #include <drm/drm_atomic.h>
> #include <drm/drm_encoder.h>
> #include <drm/drm_fb_helper.h>
>+#include <drm/drm_gem.h>
>+#include <drm/drm_ioctl.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/ttm/ttm_bo_api.h>
> #include <drm/ttm/ttm_bo_driver.h>
>-#include <drm/ttm/ttm_placement.h>
> #include <drm/ttm/ttm_module.h>
>+#include <drm/ttm/ttm_placement.h>
> 
> #define DRIVER_NAME "virtio_gpu"
> #define DRIVER_DESC "virtio GPU"
>@@ -396,7 +396,7 @@
> 
> static inline u64 virtio_gpu_object_mmap_offset(struct virtio_gpu_object *bo)
> {
>-	return drm_vma_node_offset_addr(&bo->tbo.vma_node);
>+	return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
> }
> 
> static inline int virtio_gpu_object_reserve(struct virtio_gpu_object *bo,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_fence.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_fence.c
>--- linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_fence.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_fence.c	2019-08-31 15:01:12.139736193 -0500
>@@ -23,8 +23,8 @@
>  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  */
> 
>-#include <drm/drmP.h>
> #include <trace/events/dma_fence.h>
>+
> #include "virtgpu_drv.h"
> 
> static const char *virtio_get_driver_name(struct dma_fence *f)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_gem.c	2019-08-31 15:01:12.139736193 -0500
>@@ -23,7 +23,9 @@
>  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  */
> 
>-#include <drm/drmP.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_fourcc.h>
>+
> #include "virtgpu_drv.h"
> 
> void virtio_gpu_gem_free_object(struct drm_gem_object *gem_obj)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_ioctl.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_ioctl.c
>--- linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_ioctl.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_ioctl.c	2019-08-31 15:01:12.139736193 -0500
>@@ -25,11 +25,13 @@
>  * OTHER DEALINGS IN THE SOFTWARE.
>  */
> 
>-#include <drm/drmP.h>
>-#include <drm/virtgpu_drm.h>
>-#include <drm/ttm/ttm_execbuf_util.h>
>+#include <linux/file.h>
> #include <linux/sync_file.h>
> 
>+#include <drm/drm_file.h>
>+#include <drm/ttm/ttm_execbuf_util.h>
>+#include <drm/virtgpu_drm.h>
>+
> #include "virtgpu_drv.h"
> 
> static void convert_to_hw_box(struct virtio_gpu_box *dst,
>@@ -394,7 +396,7 @@
> 		(vgdev, qobj->hw_res_handle,
> 		 vfpriv->ctx_id, offset, args->level,
> 		 &box, fence);
>-	reservation_object_add_excl_fence(qobj->tbo.resv,
>+	reservation_object_add_excl_fence(qobj->tbo.base.resv,
> 					  &fence->f);
> 
> 	dma_fence_put(&fence->f);
>@@ -448,7 +450,7 @@
> 			(vgdev, qobj,
> 			 vfpriv ? vfpriv->ctx_id : 0, offset,
> 			 args->level, &box, fence);
>-		reservation_object_add_excl_fence(qobj->tbo.resv,
>+		reservation_object_add_excl_fence(qobj->tbo.base.resv,
> 						  &fence->f);
> 		dma_fence_put(&fence->f);
> 	}
>@@ -553,34 +555,34 @@
> 
> struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
> 	DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 
> 	DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 
> 	DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 
> 	DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
> 			  virtio_gpu_resource_create_ioctl,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 
> 	DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 
> 	/* make transfer async to the main ring? - no sure, can we
> 	 * thread these in the underlying GL
> 	 */
> 	DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
> 			  virtio_gpu_transfer_from_host_ioctl,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 	DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
> 			  virtio_gpu_transfer_to_host_ioctl,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 
> 	DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> 
> 	DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
>-			  DRM_AUTH | DRM_RENDER_ALLOW),
>+			  DRM_RENDER_ALLOW),
> };
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_kms.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_kms.c
>--- linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_kms.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_kms.c	2019-08-31 15:01:12.140736193 -0500
>@@ -25,7 +25,9 @@
> 
> #include <linux/virtio.h>
> #include <linux/virtio_config.h>
>-#include <drm/drmP.h>
>+
>+#include <drm/drm_file.h>
>+
> #include "virtgpu_drv.h"
> 
> static void virtio_gpu_config_changed_work_func(struct work_struct *work)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_plane.c	2019-08-31 15:01:12.140736193 -0500
>@@ -23,9 +23,11 @@
>  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>  */
> 
>-#include "virtgpu_drv.h"
>-#include <drm/drm_plane_helper.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_fourcc.h>
>+#include <drm/drm_plane_helper.h>
>+
>+#include "virtgpu_drv.h"
> 
> static const uint32_t virtio_gpu_formats[] = {
> 	DRM_FORMAT_HOST_XRGB8888,
>@@ -210,7 +212,7 @@
> 			 0, 0, vgfb->fence);
> 		ret = virtio_gpu_object_reserve(bo, false);
> 		if (!ret) {
>-			reservation_object_add_excl_fence(bo->tbo.resv,
>+			reservation_object_add_excl_fence(bo->tbo.base.resv,
> 							  &vgfb->fence->f);
> 			dma_fence_put(&vgfb->fence->f);
> 			vgfb->fence = NULL;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_prime.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_prime.c
>--- linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_prime.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_prime.c	2019-08-31 15:01:12.140736193 -0500
>@@ -22,6 +22,8 @@
>  * Authors: Andreas Pokorny
>  */
> 
>+#include <drm/drm_prime.h>
>+
> #include "virtgpu_drv.h"
> 
> /* Empty Implementations as there should not be any other driver for a virtual
>@@ -66,8 +68,5 @@
> int virtgpu_gem_prime_mmap(struct drm_gem_object *obj,
> 			   struct vm_area_struct *vma)
> {
>-	struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(obj);
>-
>-	bo->gem_base.vma_node.vm_node.start = bo->tbo.vma_node.vm_node.start;
> 	return drm_gem_prime_mmap(obj, vma);
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_ttm.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_ttm.c
>--- linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_ttm.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_ttm.c	2019-08-31 15:01:12.140736193 -0500
>@@ -25,17 +25,18 @@
>  * OTHER DEALINGS IN THE SOFTWARE.
>  */
> 
>+#include <linux/delay.h>
>+
>+#include <drm/drm.h>
>+#include <drm/drm_file.h>
> #include <drm/ttm/ttm_bo_api.h>
> #include <drm/ttm/ttm_bo_driver.h>
>-#include <drm/ttm/ttm_placement.h>
>-#include <drm/ttm/ttm_page_alloc.h>
> #include <drm/ttm/ttm_module.h>
>-#include <drm/drmP.h>
>-#include <drm/drm.h>
>+#include <drm/ttm/ttm_page_alloc.h>
>+#include <drm/ttm/ttm_placement.h>
> #include <drm/virtgpu_drm.h>
>-#include "virtgpu_drv.h"
> 
>-#include <linux/delay.h>
>+#include "virtgpu_drv.h"
> 
> static struct
> virtio_gpu_device *virtio_gpu_get_vgdev(struct ttm_bo_device *bdev)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_vq.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_vq.c
>--- linux-5.3-rc6/drivers/gpu/drm/virtio/virtgpu_vq.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/virtio/virtgpu_vq.c	2019-08-31 15:01:12.140736193 -0500
>@@ -26,13 +26,14 @@
>  * OTHER DEALINGS IN THE SOFTWARE.
>  */
> 
>-#include <drm/drmP.h>
>-#include "virtgpu_drv.h"
>-#include "virtgpu_trace.h"
>+#include <linux/dma-mapping.h>
> #include <linux/virtio.h>
> #include <linux/virtio_config.h>
> #include <linux/virtio_ring.h>
> 
>+#include "virtgpu_drv.h"
>+#include "virtgpu_trace.h"
>+
> #define MAX_INLINE_CMD_SIZE   96
> #define MAX_INLINE_RESP_SIZE  24
> #define VBUFFER_SIZE          (sizeof(struct virtio_gpu_vbuffer) \
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vkms/Makefile linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/Makefile
>--- linux-5.3-rc6/drivers/gpu/drm/vkms/Makefile	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/Makefile	2019-08-31 15:01:12.140736193 -0500
>@@ -1,4 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0-only
>-vkms-y := vkms_drv.o vkms_plane.o vkms_output.o vkms_crtc.o vkms_gem.o vkms_crc.o
>+vkms-y := vkms_drv.o vkms_plane.o vkms_output.o vkms_crtc.o vkms_gem.o vkms_composer.o
> 
> obj-$(CONFIG_DRM_VKMS) += vkms.o
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_composer.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_composer.c
>--- linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_composer.c	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_composer.c	2019-08-31 15:01:12.232736201 -0500
>@@ -0,0 +1,249 @@
>+// SPDX-License-Identifier: GPL-2.0+
>+
>+#include <linux/crc32.h>
>+
>+#include <drm/drm_atomic.h>
>+#include <drm/drm_atomic_helper.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_vblank.h>
>+
>+#include "vkms_drv.h"
>+
>+/**
>+ * compute_crc - Compute CRC value on output frame
>+ *
>+ * @vaddr_out: address to final framebuffer
>+ * @composer: framebuffer's metadata
>+ *
>+ * returns CRC value computed using crc32 on the visible portion of
>+ * the final framebuffer at vaddr_out
>+ */
>+static uint32_t compute_crc(void *vaddr_out, struct vkms_composer *composer)
>+{
>+	int i, j, src_offset;
>+	int x_src = composer->src.x1 >> 16;
>+	int y_src = composer->src.y1 >> 16;
>+	int h_src = drm_rect_height(&composer->src) >> 16;
>+	int w_src = drm_rect_width(&composer->src) >> 16;
>+	u32 crc = 0;
>+
>+	for (i = y_src; i < y_src + h_src; ++i) {
>+		for (j = x_src; j < x_src + w_src; ++j) {
>+			src_offset = composer->offset
>+				     + (i * composer->pitch)
>+				     + (j * composer->cpp);
>+			/* XRGB format ignores Alpha channel */
>+			memset(vaddr_out + src_offset + 24, 0,  8);
>+			crc = crc32_le(crc, vaddr_out + src_offset,
>+				       sizeof(u32));
>+		}
>+	}
>+
>+	return crc;
>+}
>+
>+/**
>+ * blend - belnd value at vaddr_src with value at vaddr_dst
>+ * @vaddr_dst: destination address
>+ * @vaddr_src: source address
>+ * @dest_composer: destination framebuffer's metadata
>+ * @src_composer: source framebuffer's metadata
>+ *
>+ * Blend value at vaddr_src with value at vaddr_dst.
>+ * Currently, this function write value at vaddr_src on value
>+ * at vaddr_dst using buffer's metadata to locate the new values
>+ * from vaddr_src and their distenation at vaddr_dst.
>+ *
>+ * Todo: Use the alpha value to blend vaddr_src with vaddr_dst
>+ *	 instead of overwriting it.
>+ */
>+static void blend(void *vaddr_dst, void *vaddr_src,
>+		  struct vkms_composer *dest_composer,
>+		  struct vkms_composer *src_composer)
>+{
>+	int i, j, j_dst, i_dst;
>+	int offset_src, offset_dst;
>+
>+	int x_src = src_composer->src.x1 >> 16;
>+	int y_src = src_composer->src.y1 >> 16;
>+
>+	int x_dst = src_composer->dst.x1;
>+	int y_dst = src_composer->dst.y1;
>+	int h_dst = drm_rect_height(&src_composer->dst);
>+	int w_dst = drm_rect_width(&src_composer->dst);
>+
>+	int y_limit = y_src + h_dst;
>+	int x_limit = x_src + w_dst;
>+
>+	for (i = y_src, i_dst = y_dst; i < y_limit; ++i) {
>+		for (j = x_src, j_dst = x_dst; j < x_limit; ++j) {
>+			offset_dst = dest_composer->offset
>+				     + (i_dst * dest_composer->pitch)
>+				     + (j_dst++ * dest_composer->cpp);
>+			offset_src = src_composer->offset
>+				     + (i * src_composer->pitch)
>+				     + (j * src_composer->cpp);
>+
>+			memcpy(vaddr_dst + offset_dst,
>+			       vaddr_src + offset_src, sizeof(u32));
>+		}
>+		i_dst++;
>+	}
>+}
>+
>+static void compose_cursor(struct vkms_composer *cursor_composer,
>+			   struct vkms_composer *primary_composer,
>+			   void *vaddr_out)
>+{
>+	struct drm_gem_object *cursor_obj;
>+	struct vkms_gem_object *cursor_vkms_obj;
>+
>+	cursor_obj = drm_gem_fb_get_obj(&cursor_composer->fb, 0);
>+	cursor_vkms_obj = drm_gem_to_vkms_gem(cursor_obj);
>+
>+	if (WARN_ON(!cursor_vkms_obj->vaddr))
>+		return;
>+
>+	blend(vaddr_out, cursor_vkms_obj->vaddr,
>+	      primary_composer, cursor_composer);
>+}
>+
>+static uint32_t _vkms_get_crc(struct vkms_composer *primary_composer,
>+			      struct vkms_composer *cursor_composer)
>+{
>+	struct drm_framebuffer *fb = &primary_composer->fb;
>+	struct drm_gem_object *gem_obj = drm_gem_fb_get_obj(fb, 0);
>+	struct vkms_gem_object *vkms_obj = drm_gem_to_vkms_gem(gem_obj);
>+	void *vaddr_out = kzalloc(vkms_obj->gem.size, GFP_KERNEL);
>+	u32 crc = 0;
>+
>+	if (!vaddr_out) {
>+		DRM_ERROR("Failed to allocate memory for output frame.");
>+		return 0;
>+	}
>+
>+	if (WARN_ON(!vkms_obj->vaddr)) {
>+		kfree(vaddr_out);
>+		return crc;
>+	}
>+
>+	memcpy(vaddr_out, vkms_obj->vaddr, vkms_obj->gem.size);
>+
>+	if (cursor_composer)
>+		compose_cursor(cursor_composer, primary_composer, vaddr_out);
>+
>+	crc = compute_crc(vaddr_out, primary_composer);
>+
>+	kfree(vaddr_out);
>+
>+	return crc;
>+}
>+
>+/**
>+ * vkms_composer_worker - ordered work_struct to compute CRC
>+ *
>+ * @work: work_struct
>+ *
>+ * Work handler for composing and computing CRCs. work_struct scheduled in
>+ * an ordered workqueue that's periodically scheduled to run by
>+ * _vblank_handle() and flushed at vkms_atomic_crtc_destroy_state().
>+ */
>+void vkms_composer_worker(struct work_struct *work)
>+{
>+	struct vkms_crtc_state *crtc_state = container_of(work,
>+						struct vkms_crtc_state,
>+						composer_work);
>+	struct drm_crtc *crtc = crtc_state->base.crtc;
>+	struct vkms_output *out = drm_crtc_to_vkms_output(crtc);
>+	struct vkms_composer *primary_composer = NULL;
>+	struct vkms_composer *cursor_composer = NULL;
>+	u32 crc32 = 0;
>+	u64 frame_start, frame_end;
>+	bool crc_pending;
>+
>+	spin_lock_irq(&out->composer_lock);
>+	frame_start = crtc_state->frame_start;
>+	frame_end = crtc_state->frame_end;
>+	crc_pending = crtc_state->crc_pending;
>+	crtc_state->frame_start = 0;
>+	crtc_state->frame_end = 0;
>+	crtc_state->crc_pending = false;
>+	spin_unlock_irq(&out->composer_lock);
>+
>+	/*
>+	 * We raced with the vblank hrtimer and previous work already computed
>+	 * the crc, nothing to do.
>+	 */
>+	if (!crc_pending)
>+		return;
>+
>+	if (crtc_state->num_active_planes >= 1)
>+		primary_composer = crtc_state->active_planes[0]->composer;
>+
>+	if (crtc_state->num_active_planes == 2)
>+		cursor_composer = crtc_state->active_planes[1]->composer;
>+
>+	if (primary_composer)
>+		crc32 = _vkms_get_crc(primary_composer, cursor_composer);
>+
>+	/*
>+	 * The worker can fall behind the vblank hrtimer, make sure we catch up.
>+	 */
>+	while (frame_start <= frame_end)
>+		drm_crtc_add_crc_entry(crtc, true, frame_start++, &crc32);
>+}
>+
>+static const char * const pipe_crc_sources[] = {"auto"};
>+
>+const char *const *vkms_get_crc_sources(struct drm_crtc *crtc,
>+					size_t *count)
>+{
>+	*count = ARRAY_SIZE(pipe_crc_sources);
>+	return pipe_crc_sources;
>+}
>+
>+static int vkms_crc_parse_source(const char *src_name, bool *enabled)
>+{
>+	int ret = 0;
>+
>+	if (!src_name) {
>+		*enabled = false;
>+	} else if (strcmp(src_name, "auto") == 0) {
>+		*enabled = true;
>+	} else {
>+		*enabled = false;
>+		ret = -EINVAL;
>+	}
>+
>+	return ret;
>+}
>+
>+int vkms_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
>+			   size_t *values_cnt)
>+{
>+	bool enabled;
>+
>+	if (vkms_crc_parse_source(src_name, &enabled) < 0) {
>+		DRM_DEBUG_DRIVER("unknown source %s\n", src_name);
>+		return -EINVAL;
>+	}
>+
>+	*values_cnt = 1;
>+
>+	return 0;
>+}
>+
>+int vkms_set_crc_source(struct drm_crtc *crtc, const char *src_name)
>+{
>+	struct vkms_output *out = drm_crtc_to_vkms_output(crtc);
>+	bool enabled = false;
>+	int ret = 0;
>+
>+	ret = vkms_crc_parse_source(src_name, &enabled);
>+
>+	spin_lock_irq(&out->lock);
>+	out->composer_enabled = enabled;
>+	spin_unlock_irq(&out->lock);
>+
>+	return ret;
>+}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_crc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_crc.c
>--- linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_crc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_crc.c	1969-12-31 18:00:00.000000000 -0600
>@@ -1,272 +0,0 @@
>-// SPDX-License-Identifier: GPL-2.0+
>-
>-#include "vkms_drv.h"
>-#include <linux/crc32.h>
>-#include <drm/drm_atomic.h>
>-#include <drm/drm_atomic_helper.h>
>-#include <drm/drm_gem_framebuffer_helper.h>
>-
>-/**
>- * compute_crc - Compute CRC value on output frame
>- *
>- * @vaddr_out: address to final framebuffer
>- * @crc_out: framebuffer's metadata
>- *
>- * returns CRC value computed using crc32 on the visible portion of
>- * the final framebuffer at vaddr_out
>- */
>-static uint32_t compute_crc(void *vaddr_out, struct vkms_crc_data *crc_out)
>-{
>-	int i, j, src_offset;
>-	int x_src = crc_out->src.x1 >> 16;
>-	int y_src = crc_out->src.y1 >> 16;
>-	int h_src = drm_rect_height(&crc_out->src) >> 16;
>-	int w_src = drm_rect_width(&crc_out->src) >> 16;
>-	u32 crc = 0;
>-
>-	for (i = y_src; i < y_src + h_src; ++i) {
>-		for (j = x_src; j < x_src + w_src; ++j) {
>-			src_offset = crc_out->offset
>-				     + (i * crc_out->pitch)
>-				     + (j * crc_out->cpp);
>-			/* XRGB format ignores Alpha channel */
>-			memset(vaddr_out + src_offset + 24, 0,  8);
>-			crc = crc32_le(crc, vaddr_out + src_offset,
>-				       sizeof(u32));
>-		}
>-	}
>-
>-	return crc;
>-}
>-
>-/**
>- * blend - belnd value at vaddr_src with value at vaddr_dst
>- * @vaddr_dst: destination address
>- * @vaddr_src: source address
>- * @crc_dst: destination framebuffer's metadata
>- * @crc_src: source framebuffer's metadata
>- *
>- * Blend value at vaddr_src with value at vaddr_dst.
>- * Currently, this function write value at vaddr_src on value
>- * at vaddr_dst using buffer's metadata to locate the new values
>- * from vaddr_src and their distenation at vaddr_dst.
>- *
>- * Todo: Use the alpha value to blend vaddr_src with vaddr_dst
>- *	 instead of overwriting it.
>- */
>-static void blend(void *vaddr_dst, void *vaddr_src,
>-		  struct vkms_crc_data *crc_dst,
>-		  struct vkms_crc_data *crc_src)
>-{
>-	int i, j, j_dst, i_dst;
>-	int offset_src, offset_dst;
>-
>-	int x_src = crc_src->src.x1 >> 16;
>-	int y_src = crc_src->src.y1 >> 16;
>-
>-	int x_dst = crc_src->dst.x1;
>-	int y_dst = crc_src->dst.y1;
>-	int h_dst = drm_rect_height(&crc_src->dst);
>-	int w_dst = drm_rect_width(&crc_src->dst);
>-
>-	int y_limit = y_src + h_dst;
>-	int x_limit = x_src + w_dst;
>-
>-	for (i = y_src, i_dst = y_dst; i < y_limit; ++i) {
>-		for (j = x_src, j_dst = x_dst; j < x_limit; ++j) {
>-			offset_dst = crc_dst->offset
>-				     + (i_dst * crc_dst->pitch)
>-				     + (j_dst++ * crc_dst->cpp);
>-			offset_src = crc_src->offset
>-				     + (i * crc_src->pitch)
>-				     + (j * crc_src->cpp);
>-
>-			memcpy(vaddr_dst + offset_dst,
>-			       vaddr_src + offset_src, sizeof(u32));
>-		}
>-		i_dst++;
>-	}
>-}
>-
>-static void compose_cursor(struct vkms_crc_data *cursor_crc,
>-			   struct vkms_crc_data *primary_crc, void *vaddr_out)
>-{
>-	struct drm_gem_object *cursor_obj;
>-	struct vkms_gem_object *cursor_vkms_obj;
>-
>-	cursor_obj = drm_gem_fb_get_obj(&cursor_crc->fb, 0);
>-	cursor_vkms_obj = drm_gem_to_vkms_gem(cursor_obj);
>-
>-	mutex_lock(&cursor_vkms_obj->pages_lock);
>-	if (!cursor_vkms_obj->vaddr) {
>-		DRM_WARN("cursor plane vaddr is NULL");
>-		goto out;
>-	}
>-
>-	blend(vaddr_out, cursor_vkms_obj->vaddr, primary_crc, cursor_crc);
>-
>-out:
>-	mutex_unlock(&cursor_vkms_obj->pages_lock);
>-}
>-
>-static uint32_t _vkms_get_crc(struct vkms_crc_data *primary_crc,
>-			      struct vkms_crc_data *cursor_crc)
>-{
>-	struct drm_framebuffer *fb = &primary_crc->fb;
>-	struct drm_gem_object *gem_obj = drm_gem_fb_get_obj(fb, 0);
>-	struct vkms_gem_object *vkms_obj = drm_gem_to_vkms_gem(gem_obj);
>-	void *vaddr_out = kzalloc(vkms_obj->gem.size, GFP_KERNEL);
>-	u32 crc = 0;
>-
>-	if (!vaddr_out) {
>-		DRM_ERROR("Failed to allocate memory for output frame.");
>-		return 0;
>-	}
>-
>-	mutex_lock(&vkms_obj->pages_lock);
>-	if (WARN_ON(!vkms_obj->vaddr)) {
>-		mutex_unlock(&vkms_obj->pages_lock);
>-		kfree(vaddr_out);
>-		return crc;
>-	}
>-
>-	memcpy(vaddr_out, vkms_obj->vaddr, vkms_obj->gem.size);
>-	mutex_unlock(&vkms_obj->pages_lock);
>-
>-	if (cursor_crc)
>-		compose_cursor(cursor_crc, primary_crc, vaddr_out);
>-
>-	crc = compute_crc(vaddr_out, primary_crc);
>-
>-	kfree(vaddr_out);
>-
>-	return crc;
>-}
>-
>-/**
>- * vkms_crc_work_handle - ordered work_struct to compute CRC
>- *
>- * @work: work_struct
>- *
>- * Work handler for computing CRCs. work_struct scheduled in
>- * an ordered workqueue that's periodically scheduled to run by
>- * _vblank_handle() and flushed at vkms_atomic_crtc_destroy_state().
>- */
>-void vkms_crc_work_handle(struct work_struct *work)
>-{
>-	struct vkms_crtc_state *crtc_state = container_of(work,
>-						struct vkms_crtc_state,
>-						crc_work);
>-	struct drm_crtc *crtc = crtc_state->base.crtc;
>-	struct vkms_output *out = drm_crtc_to_vkms_output(crtc);
>-	struct vkms_device *vdev = container_of(out, struct vkms_device,
>-						output);
>-	struct vkms_crc_data *primary_crc = NULL;
>-	struct vkms_crc_data *cursor_crc = NULL;
>-	struct drm_plane *plane;
>-	u32 crc32 = 0;
>-	u64 frame_start, frame_end;
>-	unsigned long flags;
>-
>-	spin_lock_irqsave(&out->state_lock, flags);
>-	frame_start = crtc_state->frame_start;
>-	frame_end = crtc_state->frame_end;
>-	spin_unlock_irqrestore(&out->state_lock, flags);
>-
>-	/* _vblank_handle() hasn't updated frame_start yet */
>-	if (!frame_start || frame_start == frame_end)
>-		goto out;
>-
>-	drm_for_each_plane(plane, &vdev->drm) {
>-		struct vkms_plane_state *vplane_state;
>-		struct vkms_crc_data *crc_data;
>-
>-		vplane_state = to_vkms_plane_state(plane->state);
>-		crc_data = vplane_state->crc_data;
>-
>-		if (drm_framebuffer_read_refcount(&crc_data->fb) == 0)
>-			continue;
>-
>-		if (plane->type == DRM_PLANE_TYPE_PRIMARY)
>-			primary_crc = crc_data;
>-		else
>-			cursor_crc = crc_data;
>-	}
>-
>-	if (primary_crc)
>-		crc32 = _vkms_get_crc(primary_crc, cursor_crc);
>-
>-	frame_end = drm_crtc_accurate_vblank_count(crtc);
>-
>-	/* queue_work can fail to schedule crc_work; add crc for
>-	 * missing frames
>-	 */
>-	while (frame_start <= frame_end)
>-		drm_crtc_add_crc_entry(crtc, true, frame_start++, &crc32);
>-
>-out:
>-	/* to avoid using the same value for frame number again */
>-	spin_lock_irqsave(&out->state_lock, flags);
>-	crtc_state->frame_end = frame_end;
>-	crtc_state->frame_start = 0;
>-	spin_unlock_irqrestore(&out->state_lock, flags);
>-}
>-
>-static const char * const pipe_crc_sources[] = {"auto"};
>-
>-const char *const *vkms_get_crc_sources(struct drm_crtc *crtc,
>-					size_t *count)
>-{
>-	*count = ARRAY_SIZE(pipe_crc_sources);
>-	return pipe_crc_sources;
>-}
>-
>-static int vkms_crc_parse_source(const char *src_name, bool *enabled)
>-{
>-	int ret = 0;
>-
>-	if (!src_name) {
>-		*enabled = false;
>-	} else if (strcmp(src_name, "auto") == 0) {
>-		*enabled = true;
>-	} else {
>-		*enabled = false;
>-		ret = -EINVAL;
>-	}
>-
>-	return ret;
>-}
>-
>-int vkms_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
>-			   size_t *values_cnt)
>-{
>-	bool enabled;
>-
>-	if (vkms_crc_parse_source(src_name, &enabled) < 0) {
>-		DRM_DEBUG_DRIVER("unknown source %s\n", src_name);
>-		return -EINVAL;
>-	}
>-
>-	*values_cnt = 1;
>-
>-	return 0;
>-}
>-
>-int vkms_set_crc_source(struct drm_crtc *crtc, const char *src_name)
>-{
>-	struct vkms_output *out = drm_crtc_to_vkms_output(crtc);
>-	bool enabled = false;
>-	unsigned long flags;
>-	int ret = 0;
>-
>-	ret = vkms_crc_parse_source(src_name, &enabled);
>-
>-	/* make sure nothing is scheduled on crtc workq */
>-	flush_workqueue(out->crc_workq);
>-
>-	spin_lock_irqsave(&out->lock, flags);
>-	out->crc_enabled = enabled;
>-	spin_unlock_irqrestore(&out->lock, flags);
>-
>-	return ret;
>-}
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_crtc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_crtc.c
>--- linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_crtc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_crtc.c	2019-08-31 15:01:12.140736193 -0500
>@@ -1,15 +1,18 @@
> // SPDX-License-Identifier: GPL-2.0+
> 
>-#include "vkms_drv.h"
>+#include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
>+
>+#include "vkms_drv.h"
> 
> static enum hrtimer_restart vkms_vblank_simulate(struct hrtimer *timer)
> {
> 	struct vkms_output *output = container_of(timer, struct vkms_output,
> 						  vblank_hrtimer);
> 	struct drm_crtc *crtc = &output->crtc;
>-	struct vkms_crtc_state *state = to_vkms_crtc_state(crtc->state);
>+	struct vkms_crtc_state *state;
> 	u64 ret_overrun;
> 	bool ret;
> 
>@@ -23,20 +26,26 @@
> 	if (!ret)
> 		DRM_ERROR("vkms failure on handling vblank");
> 
>-	if (state && output->crc_enabled) {
>+	state = output->composer_state;
>+	if (state && output->composer_enabled) {
> 		u64 frame = drm_crtc_accurate_vblank_count(crtc);
> 
>-		/* update frame_start only if a queued vkms_crc_work_handle()
>+		/* update frame_start only if a queued vkms_composer_worker()
> 		 * has read the data
> 		 */
>-		spin_lock(&output->state_lock);
>-		if (!state->frame_start)
>+		spin_lock(&output->composer_lock);
>+		if (!state->crc_pending)
> 			state->frame_start = frame;
>-		spin_unlock(&output->state_lock);
>+		else
>+			DRM_DEBUG_DRIVER("crc worker falling behind, frame_start: %llu, frame_end: %llu\n",
>+					 state->frame_start, frame);
>+		state->frame_end = frame;
>+		state->crc_pending = true;
>+		spin_unlock(&output->composer_lock);
> 
>-		ret = queue_work(output->crc_workq, &state->crc_work);
>+		ret = queue_work(output->composer_workq, &state->composer_work);
> 		if (!ret)
>-			DRM_WARN("failed to queue vkms_crc_work_handle");
>+			DRM_DEBUG_DRIVER("Composer worker already queued\n");
> 	}
> 
> 	spin_unlock(&output->lock);
>@@ -107,7 +116,7 @@
> 
> 	__drm_atomic_helper_crtc_duplicate_state(crtc, &vkms_state->base);
> 
>-	INIT_WORK(&vkms_state->crc_work, vkms_crc_work_handle);
>+	INIT_WORK(&vkms_state->composer_work, vkms_composer_worker);
> 
> 	return &vkms_state->base;
> }
>@@ -119,10 +128,9 @@
> 
> 	__drm_atomic_helper_crtc_destroy_state(state);
> 
>-	if (vkms_state) {
>-		flush_work(&vkms_state->crc_work);
>-		kfree(vkms_state);
>-	}
>+	WARN_ON(work_pending(&vkms_state->composer_work));
>+	kfree(vkms_state->active_planes);
>+	kfree(vkms_state);
> }
> 
> static void vkms_atomic_crtc_reset(struct drm_crtc *crtc)
>@@ -135,7 +143,7 @@
> 
> 	__drm_atomic_helper_crtc_reset(crtc, &vkms_state->base);
> 	if (vkms_state)
>-		INIT_WORK(&vkms_state->crc_work, vkms_crc_work_handle);
>+		INIT_WORK(&vkms_state->composer_work, vkms_composer_worker);
> }
> 
> static const struct drm_crtc_funcs vkms_crtc_funcs = {
>@@ -152,6 +160,52 @@
> 	.verify_crc_source	= vkms_verify_crc_source,
> };
> 
>+static int vkms_crtc_atomic_check(struct drm_crtc *crtc,
>+				  struct drm_crtc_state *state)
>+{
>+	struct vkms_crtc_state *vkms_state = to_vkms_crtc_state(state);
>+	struct drm_plane *plane;
>+	struct drm_plane_state *plane_state;
>+	int i = 0, ret;
>+
>+	if (vkms_state->active_planes)
>+		return 0;
>+
>+	ret = drm_atomic_add_affected_planes(state->state, crtc);
>+	if (ret < 0)
>+		return ret;
>+
>+	drm_for_each_plane_mask(plane, crtc->dev, state->plane_mask) {
>+		plane_state = drm_atomic_get_existing_plane_state(state->state,
>+								  plane);
>+		WARN_ON(!plane_state);
>+
>+		if (!plane_state->visible)
>+			continue;
>+
>+		i++;
>+	}
>+
>+	vkms_state->active_planes = kcalloc(i, sizeof(plane), GFP_KERNEL);
>+	if (!vkms_state->active_planes)
>+		return -ENOMEM;
>+	vkms_state->num_active_planes = i;
>+
>+	i = 0;
>+	drm_for_each_plane_mask(plane, crtc->dev, state->plane_mask) {
>+		plane_state = drm_atomic_get_existing_plane_state(state->state,
>+								  plane);
>+
>+		if (!plane_state->visible)
>+			continue;
>+
>+		vkms_state->active_planes[i++] =
>+			to_vkms_plane_state(plane_state);
>+	}
>+
>+	return 0;
>+}
>+
> static void vkms_crtc_atomic_enable(struct drm_crtc *crtc,
> 				    struct drm_crtc_state *old_state)
> {
>@@ -170,7 +224,7 @@
> 	struct vkms_output *vkms_output = drm_crtc_to_vkms_output(crtc);
> 
> 	/* This lock is held across the atomic commit to block vblank timer
>-	 * from scheduling vkms_crc_work_handle until the crc_data is updated
>+	 * from scheduling vkms_composer_worker until the composer is updated
> 	 */
> 	spin_lock_irq(&vkms_output->lock);
> }
>@@ -179,25 +233,27 @@
> 				   struct drm_crtc_state *old_crtc_state)
> {
> 	struct vkms_output *vkms_output = drm_crtc_to_vkms_output(crtc);
>-	unsigned long flags;
> 
> 	if (crtc->state->event) {
>-		spin_lock_irqsave(&crtc->dev->event_lock, flags);
>+		spin_lock(&crtc->dev->event_lock);
> 
> 		if (drm_crtc_vblank_get(crtc) != 0)
> 			drm_crtc_send_vblank_event(crtc, crtc->state->event);
> 		else
> 			drm_crtc_arm_vblank_event(crtc, crtc->state->event);
> 
>-		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
>+		spin_unlock(&crtc->dev->event_lock);
> 
> 		crtc->state->event = NULL;
> 	}
> 
>+	vkms_output->composer_state = to_vkms_crtc_state(crtc->state);
>+
> 	spin_unlock_irq(&vkms_output->lock);
> }
> 
> static const struct drm_crtc_helper_funcs vkms_crtc_helper_funcs = {
>+	.atomic_check	= vkms_crtc_atomic_check,
> 	.atomic_begin	= vkms_crtc_atomic_begin,
> 	.atomic_flush	= vkms_crtc_atomic_flush,
> 	.atomic_enable	= vkms_crtc_atomic_enable,
>@@ -220,10 +276,10 @@
> 	drm_crtc_helper_add(crtc, &vkms_crtc_helper_funcs);
> 
> 	spin_lock_init(&vkms_out->lock);
>-	spin_lock_init(&vkms_out->state_lock);
>+	spin_lock_init(&vkms_out->composer_lock);
> 
>-	vkms_out->crc_workq = alloc_ordered_workqueue("vkms_crc_workq", 0);
>-	if (!vkms_out->crc_workq)
>+	vkms_out->composer_workq = alloc_ordered_workqueue("vkms_composer", 0);
>+	if (!vkms_out->composer_workq)
> 		return -ENOMEM;
> 
> 	return ret;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_drv.c	2019-08-31 15:01:12.140736193 -0500
>@@ -10,11 +10,19 @@
>  */
> 
> #include <linux/module.h>
>-#include <drm/drm_gem.h>
>+#include <linux/platform_device.h>
>+
>+#include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>-#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_helper.h>
>+#include <drm/drm_file.h>
>+#include <drm/drm_gem.h>
>+#include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_ioctl.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
>+
> #include "vkms_drv.h"
> 
> #define DRIVER_NAME	"vkms"
>@@ -55,7 +63,36 @@
> 	drm_atomic_helper_shutdown(&vkms->drm);
> 	drm_mode_config_cleanup(&vkms->drm);
> 	drm_dev_fini(&vkms->drm);
>-	destroy_workqueue(vkms->output.crc_workq);
>+	destroy_workqueue(vkms->output.composer_workq);
>+}
>+
>+static void vkms_atomic_commit_tail(struct drm_atomic_state *old_state)
>+{
>+	struct drm_device *dev = old_state->dev;
>+	struct drm_crtc *crtc;
>+	struct drm_crtc_state *old_crtc_state;
>+	int i;
>+
>+	drm_atomic_helper_commit_modeset_disables(dev, old_state);
>+
>+	drm_atomic_helper_commit_planes(dev, old_state, 0);
>+
>+	drm_atomic_helper_commit_modeset_enables(dev, old_state);
>+
>+	drm_atomic_helper_fake_vblank(old_state);
>+
>+	drm_atomic_helper_commit_hw_done(old_state);
>+
>+	drm_atomic_helper_wait_for_vblanks(dev, old_state);
>+
>+	for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
>+		struct vkms_crtc_state *vkms_state =
>+			to_vkms_crtc_state(old_crtc_state);
>+
>+		flush_work(&vkms_state->composer_work);
>+	}
>+
>+	drm_atomic_helper_cleanup_planes(dev, old_state);
> }
> 
> static struct drm_driver vkms_driver = {
>@@ -80,6 +117,10 @@
> 	.atomic_commit = drm_atomic_helper_commit,
> };
> 
>+static const struct drm_mode_config_helper_funcs vkms_mode_config_helpers = {
>+	.atomic_commit_tail = vkms_atomic_commit_tail,
>+};
>+
> static int vkms_modeset_init(struct vkms_device *vkmsdev)
> {
> 	struct drm_device *dev = &vkmsdev->drm;
>@@ -91,8 +132,9 @@
> 	dev->mode_config.max_width = XRES_MAX;
> 	dev->mode_config.max_height = YRES_MAX;
> 	dev->mode_config.preferred_depth = 24;
>+	dev->mode_config.helper_private = &vkms_mode_config_helpers;
> 
>-	return vkms_output_init(vkmsdev);
>+	return vkms_output_init(vkmsdev, 0);
> }
> 
> static int __init vkms_init(void)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_drv.h	2019-08-31 15:01:12.140736193 -0500
>@@ -3,11 +3,11 @@
> #ifndef _VKMS_DRV_H_
> #define _VKMS_DRV_H_
> 
>-#include <drm/drmP.h>
>+#include <linux/hrtimer.h>
>+
> #include <drm/drm.h>
> #include <drm/drm_gem.h>
> #include <drm/drm_encoder.h>
>-#include <linux/hrtimer.h>
> 
> #define XRES_MIN    20
> #define YRES_MIN    20
>@@ -20,7 +20,7 @@
> 
> extern bool enable_cursor;
> 
>-struct vkms_crc_data {
>+struct vkms_composer {
> 	struct drm_framebuffer fb;
> 	struct drm_rect src, dst;
> 	unsigned int offset;
>@@ -31,23 +31,30 @@
> /**
>  * vkms_plane_state - Driver specific plane state
>  * @base: base plane state
>- * @crc_data: data required for CRC computation
>+ * @composer: data required for composing computation
>  */
> struct vkms_plane_state {
> 	struct drm_plane_state base;
>-	struct vkms_crc_data *crc_data;
>+	struct vkms_composer *composer;
> };
> 
> /**
>  * vkms_crtc_state - Driver specific CRTC state
>  * @base: base CRTC state
>- * @crc_work: work struct to compute and add CRC entries
>+ * @composer_work: work struct to compose and add CRC entries
>  * @n_frame_start: start frame number for computed CRC
>  * @n_frame_end: end frame number for computed CRC
>  */
> struct vkms_crtc_state {
> 	struct drm_crtc_state base;
>-	struct work_struct crc_work;
>+	struct work_struct composer_work;
>+
>+	int num_active_planes;
>+	/* stack of active planes for crc computation, should be in z order */
>+	struct vkms_plane_state **active_planes;
>+
>+	/* below three are protected by vkms_output.composer_lock */
>+	bool crc_pending;
> 	u64 frame_start;
> 	u64 frame_end;
> };
>@@ -59,13 +66,16 @@
> 	struct hrtimer vblank_hrtimer;
> 	ktime_t period_ns;
> 	struct drm_pending_vblank_event *event;
>-	bool crc_enabled;
>-	/* ordered wq for crc_work */
>-	struct workqueue_struct *crc_workq;
>-	/* protects concurrent access to crc_data */
>+	/* ordered wq for composer_work */
>+	struct workqueue_struct *composer_workq;
>+	/* protects concurrent access to composer */
> 	spinlock_t lock;
>-	/* protects concurrent access to crtc_state */
>-	spinlock_t state_lock;
>+
>+	/* protected by @lock */
>+	bool composer_enabled;
>+	struct vkms_crtc_state *composer_state;
>+
>+	spinlock_t composer_lock;
> };
> 
> struct vkms_device {
>@@ -105,10 +115,10 @@
> 			       int *max_error, ktime_t *vblank_time,
> 			       bool in_vblank_irq);
> 
>-int vkms_output_init(struct vkms_device *vkmsdev);
>+int vkms_output_init(struct vkms_device *vkmsdev, int index);
> 
> struct drm_plane *vkms_plane_init(struct vkms_device *vkmsdev,
>-				  enum drm_plane_type type);
>+				  enum drm_plane_type type, int index);
> 
> /* Gem stuff */
> struct drm_gem_object *vkms_gem_create(struct drm_device *dev,
>@@ -133,6 +143,8 @@
> int vkms_set_crc_source(struct drm_crtc *crtc, const char *src_name);
> int vkms_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
> 			   size_t *values_cnt);
>-void vkms_crc_work_handle(struct work_struct *work);
>+
>+/* Composer Support */
>+void vkms_composer_worker(struct work_struct *work);
> 
> #endif /* _VKMS_DRV_H_ */
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_gem.c	2019-08-31 15:01:12.140736193 -0500
>@@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0+
> 
> #include <linux/shmem_fs.h>
>+#include <linux/vmalloc.h>
> 
> #include "vkms_drv.h"
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_output.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_output.c
>--- linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_output.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_output.c	2019-08-31 15:01:12.140736193 -0500
>@@ -35,7 +35,7 @@
> 	.get_modes    = vkms_conn_get_modes,
> };
> 
>-int vkms_output_init(struct vkms_device *vkmsdev)
>+int vkms_output_init(struct vkms_device *vkmsdev, int index)
> {
> 	struct vkms_output *output = &vkmsdev->output;
> 	struct drm_device *dev = &vkmsdev->drm;
>@@ -45,12 +45,12 @@
> 	struct drm_plane *primary, *cursor = NULL;
> 	int ret;
> 
>-	primary = vkms_plane_init(vkmsdev, DRM_PLANE_TYPE_PRIMARY);
>+	primary = vkms_plane_init(vkmsdev, DRM_PLANE_TYPE_PRIMARY, index);
> 	if (IS_ERR(primary))
> 		return PTR_ERR(primary);
> 
> 	if (enable_cursor) {
>-		cursor = vkms_plane_init(vkmsdev, DRM_PLANE_TYPE_CURSOR);
>+		cursor = vkms_plane_init(vkmsdev, DRM_PLANE_TYPE_CURSOR, index);
> 		if (IS_ERR(cursor)) {
> 			ret = PTR_ERR(cursor);
> 			goto err_cursor;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/vkms/vkms_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vkms/vkms_plane.c	2019-08-31 15:01:12.140736193 -0500
>@@ -1,10 +1,12 @@
> // SPDX-License-Identifier: GPL-2.0+
> 
>-#include "vkms_drv.h"
>-#include <drm/drm_plane_helper.h>
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_framebuffer_helper.h>
>+#include <drm/drm_plane_helper.h>
>+
>+#include "vkms_drv.h"
> 
> static const u32 vkms_formats[] = {
> 	DRM_FORMAT_XRGB8888,
>@@ -18,20 +20,20 @@
> vkms_plane_duplicate_state(struct drm_plane *plane)
> {
> 	struct vkms_plane_state *vkms_state;
>-	struct vkms_crc_data *crc_data;
>+	struct vkms_composer *composer;
> 
> 	vkms_state = kzalloc(sizeof(*vkms_state), GFP_KERNEL);
> 	if (!vkms_state)
> 		return NULL;
> 
>-	crc_data = kzalloc(sizeof(*crc_data), GFP_KERNEL);
>-	if (!crc_data) {
>-		DRM_DEBUG_KMS("Couldn't allocate crc_data\n");
>+	composer = kzalloc(sizeof(*composer), GFP_KERNEL);
>+	if (!composer) {
>+		DRM_DEBUG_KMS("Couldn't allocate composer\n");
> 		kfree(vkms_state);
> 		return NULL;
> 	}
> 
>-	vkms_state->crc_data = crc_data;
>+	vkms_state->composer = composer;
> 
> 	__drm_atomic_helper_plane_duplicate_state(plane,
> 						  &vkms_state->base);
>@@ -49,12 +51,12 @@
> 		/* dropping the reference we acquired in
> 		 * vkms_primary_plane_update()
> 		 */
>-		if (drm_framebuffer_read_refcount(&vkms_state->crc_data->fb))
>-			drm_framebuffer_put(&vkms_state->crc_data->fb);
>+		if (drm_framebuffer_read_refcount(&vkms_state->composer->fb))
>+			drm_framebuffer_put(&vkms_state->composer->fb);
> 	}
> 
>-	kfree(vkms_state->crc_data);
>-	vkms_state->crc_data = NULL;
>+	kfree(vkms_state->composer);
>+	vkms_state->composer = NULL;
> 
> 	__drm_atomic_helper_plane_destroy_state(old_state);
> 	kfree(vkms_state);
>@@ -91,21 +93,21 @@
> {
> 	struct vkms_plane_state *vkms_plane_state;
> 	struct drm_framebuffer *fb = plane->state->fb;
>-	struct vkms_crc_data *crc_data;
>+	struct vkms_composer *composer;
> 
> 	if (!plane->state->crtc || !fb)
> 		return;
> 
> 	vkms_plane_state = to_vkms_plane_state(plane->state);
> 
>-	crc_data = vkms_plane_state->crc_data;
>-	memcpy(&crc_data->src, &plane->state->src, sizeof(struct drm_rect));
>-	memcpy(&crc_data->dst, &plane->state->dst, sizeof(struct drm_rect));
>-	memcpy(&crc_data->fb, fb, sizeof(struct drm_framebuffer));
>-	drm_framebuffer_get(&crc_data->fb);
>-	crc_data->offset = fb->offsets[0];
>-	crc_data->pitch = fb->pitches[0];
>-	crc_data->cpp = fb->format->cpp[0];
>+	composer = vkms_plane_state->composer;
>+	memcpy(&composer->src, &plane->state->src, sizeof(struct drm_rect));
>+	memcpy(&composer->dst, &plane->state->dst, sizeof(struct drm_rect));
>+	memcpy(&composer->fb, fb, sizeof(struct drm_framebuffer));
>+	drm_framebuffer_get(&composer->fb);
>+	composer->offset = fb->offsets[0];
>+	composer->pitch = fb->pitches[0];
>+	composer->cpp = fb->format->cpp[0];
> }
> 
> static int vkms_plane_atomic_check(struct drm_plane *plane,
>@@ -176,7 +178,7 @@
> };
> 
> struct drm_plane *vkms_plane_init(struct vkms_device *vkmsdev,
>-				  enum drm_plane_type type)
>+				  enum drm_plane_type type, int index)
> {
> 	struct drm_device *dev = &vkmsdev->drm;
> 	const struct drm_plane_helper_funcs *funcs;
>@@ -198,7 +200,7 @@
> 		funcs = &vkms_primary_helper_funcs;
> 	}
> 
>-	ret = drm_universal_plane_init(dev, plane, 0,
>+	ret = drm_universal_plane_init(dev, plane, 1 << index,
> 				       &vkms_plane_funcs,
> 				       formats, nformats,
> 				       NULL, type, NULL);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_blit.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_blit.c
>--- linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_blit.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_blit.c	2019-08-31 15:01:12.141736193 -0500
>@@ -459,9 +459,9 @@
> 
> 	/* Buffer objects need to be either pinned or reserved: */
> 	if (!(dst->mem.placement & TTM_PL_FLAG_NO_EVICT))
>-		lockdep_assert_held(&dst->resv->lock.base);
>+		reservation_object_assert_held(dst->base.resv);
> 	if (!(src->mem.placement & TTM_PL_FLAG_NO_EVICT))
>-		lockdep_assert_held(&src->resv->lock.base);
>+		reservation_object_assert_held(src->base.resv);
> 
> 	if (dst->ttm->state == tt_unpopulated) {
> 		ret = dst->ttm->bdev->driver->ttm_tt_populate(dst->ttm, &ctx);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
>--- linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_bo.c	2019-08-31 15:01:12.141736193 -0500
>@@ -342,7 +342,7 @@
> 	uint32_t old_mem_type = bo->mem.mem_type;
> 	int ret;
> 
>-	lockdep_assert_held(&bo->resv->lock.base);
>+	reservation_object_assert_held(bo->base.resv);
> 
> 	if (pin) {
> 		if (vbo->pin_count++ > 0)
>@@ -690,7 +690,7 @@
> 		long lret;
> 
> 		lret = reservation_object_wait_timeout_rcu
>-			(bo->resv, true, true,
>+			(bo->base.resv, true, true,
> 			 nonblock ? 0 : MAX_SCHEDULE_TIMEOUT);
> 		if (!lret)
> 			return -EBUSY;
>@@ -835,7 +835,7 @@
> 		goto out_no_bo;
> 
> 	rep->handle = handle;
>-	rep->map_handle = drm_vma_node_offset_addr(&vbo->base.vma_node);
>+	rep->map_handle = drm_vma_node_offset_addr(&vbo->base.base.vma_node);
> 	rep->cur_gmr_id = handle;
> 	rep->cur_gmr_offset = 0;
> 
>@@ -1007,10 +1007,10 @@
> 
> 	if (fence == NULL) {
> 		vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);
>-		reservation_object_add_excl_fence(bo->resv, &fence->base);
>+		reservation_object_add_excl_fence(bo->base.resv, &fence->base);
> 		dma_fence_put(&fence->base);
> 	} else
>-		reservation_object_add_excl_fence(bo->resv, &fence->base);
>+		reservation_object_add_excl_fence(bo->base.resv, &fence->base);
> }
> 
> 
>@@ -1077,7 +1077,7 @@
> 	if (ret != 0)
> 		return -EINVAL;
> 
>-	*offset = drm_vma_node_offset_addr(&out_buf->base.vma_node);
>+	*offset = drm_vma_node_offset_addr(&out_buf->base.base.vma_node);
> 	vmw_bo_unreference(&out_buf);
> 	return 0;
> }
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c
>--- linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c	2019-08-31 15:01:12.141736193 -0500
>@@ -169,7 +169,7 @@
> 	} *cmd;
> 
> 	WARN_ON_ONCE(bo->mem.mem_type != VMW_PL_MOB);
>-	lockdep_assert_held(&bo->resv->lock.base);
>+	reservation_object_assert_held(bo->base.resv);
> 
> 	cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
> 	if (!cmd)
>@@ -311,7 +311,7 @@
> 		return 0;
> 
> 	WARN_ON_ONCE(bo->mem.mem_type != VMW_PL_MOB);
>-	lockdep_assert_held(&bo->resv->lock.base);
>+	reservation_object_assert_held(bo->base.resv);
> 
> 	mutex_lock(&dev_priv->binding_mutex);
> 	if (!vcotbl->scrubbed)
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c	2019-08-31 15:01:12.141736193 -0500
>@@ -186,7 +186,7 @@
> 		      DRM_RENDER_ALLOW),
> 	VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
> 		      DRM_AUTH | DRM_RENDER_ALLOW),
>-	VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH |
>+	VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, DRM_AUTH |
> 		      DRM_RENDER_ALLOW),
> 	VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
> 		      DRM_RENDER_ALLOW),
>@@ -641,7 +641,6 @@
> 		INIT_LIST_HEAD(&dev_priv->res_lru[i]);
> 	}
> 
>-	mutex_init(&dev_priv->init_mutex);
> 	init_waitqueue_head(&dev_priv->fence_queue);
> 	init_waitqueue_head(&dev_priv->fifo_queue);
> 	dev_priv->fence_queue_waiters = 0;
>@@ -1121,15 +1120,7 @@
> 			&vmw_ioctls[nr - DRM_COMMAND_BASE];
> 
> 		if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
>-			ret = (long) drm_ioctl_permit(ioctl->flags, file_priv);
>-			if (unlikely(ret != 0))
>-				return ret;
>-
>-			if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN))
>-				goto out_io_encoding;
>-
>-			return (long) vmw_execbuf_ioctl(dev, arg, file_priv,
>-							_IOC_SIZE(cmd));
>+			return ioctl_func(filp, cmd, arg);
> 		} else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
> 			if (!drm_is_current_master(file_priv) &&
> 			    !capable(CAP_SYS_ADMIN))
>@@ -1180,10 +1171,6 @@
> }
> #endif
> 
>-static void vmw_lastclose(struct drm_device *dev)
>-{
>-}
>-
> static void vmw_master_init(struct vmw_master *vmaster)
> {
> 	ttm_lock_init(&vmaster->lock);
>@@ -1551,10 +1538,9 @@
> 
> static struct drm_driver driver = {
> 	.driver_features =
>-	DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC,
>+	DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC,
> 	.load = vmw_driver_load,
> 	.unload = vmw_driver_unload,
>-	.lastclose = vmw_lastclose,
> 	.get_vblank_counter = vmw_get_vblank_counter,
> 	.enable_vblank = vmw_enable_vblank,
> 	.disable_vblank = vmw_disable_vblank,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
>--- linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h	2019-08-31 15:01:12.141736193 -0500
>@@ -484,11 +484,6 @@
> 
> 	spinlock_t resource_lock;
> 	struct idr res_idr[vmw_res_max];
>-	/*
>-	 * Block lastclose from racing with firstopen.
>-	 */
>-
>-	struct mutex init_mutex;
> 
> 	/*
> 	 * A resource manager for kernel-only surfaces and
>@@ -915,8 +910,8 @@
>  * Command submission - vmwgfx_execbuf.c
>  */
> 
>-extern int vmw_execbuf_ioctl(struct drm_device *dev, unsigned long data,
>-			     struct drm_file *file_priv, size_t size);
>+extern int vmw_execbuf_ioctl(struct drm_device *dev, void *data,
>+			     struct drm_file *file_priv);
> extern int vmw_execbuf_process(struct drm_file *file_priv,
> 			       struct vmw_private *dev_priv,
> 			       void __user *user_commands,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
>--- linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c	2019-08-31 15:01:12.141736193 -0500
>@@ -3995,54 +3995,40 @@
> 	mutex_unlock(&dev_priv->cmdbuf_mutex);
> }
> 
>-int vmw_execbuf_ioctl(struct drm_device *dev, unsigned long data,
>-		      struct drm_file *file_priv, size_t size)
>+int vmw_execbuf_ioctl(struct drm_device *dev, void *data,
>+		      struct drm_file *file_priv)
> {
> 	struct vmw_private *dev_priv = vmw_priv(dev);
>-	struct drm_vmw_execbuf_arg arg;
>+	struct drm_vmw_execbuf_arg *arg = data;
> 	int ret;
>-	static const size_t copy_offset[] = {
>-		offsetof(struct drm_vmw_execbuf_arg, context_handle),
>-		sizeof(struct drm_vmw_execbuf_arg)};
> 	struct dma_fence *in_fence = NULL;
> 
>-	if (unlikely(size < copy_offset[0])) {
>-		VMW_DEBUG_USER("Invalid command size, ioctl %d\n",
>-			       DRM_VMW_EXECBUF);
>-		return -EINVAL;
>-	}
>-
>-	if (copy_from_user(&arg, (void __user *) data, copy_offset[0]) != 0)
>-		return -EFAULT;
>-
> 	/*
> 	 * Extend the ioctl argument while maintaining backwards compatibility:
>-	 * We take different code paths depending on the value of arg.version.
>+	 * We take different code paths depending on the value of arg->version.
>+	 *
>+	 * Note: The ioctl argument is extended and zeropadded by core DRM.
> 	 */
>-	if (unlikely(arg.version > DRM_VMW_EXECBUF_VERSION ||
>-		     arg.version == 0)) {
>+	if (unlikely(arg->version > DRM_VMW_EXECBUF_VERSION ||
>+		     arg->version == 0)) {
> 		VMW_DEBUG_USER("Incorrect execbuf version.\n");
> 		return -EINVAL;
> 	}
> 
>-	if (arg.version > 1 &&
>-	    copy_from_user(&arg.context_handle,
>-			   (void __user *) (data + copy_offset[0]),
>-			   copy_offset[arg.version - 1] - copy_offset[0]) != 0)
>-		return -EFAULT;
>-
>-	switch (arg.version) {
>+	switch (arg->version) {
> 	case 1:
>-		arg.context_handle = (uint32_t) -1;
>+		/* For v1 core DRM have extended + zeropadded the data */
>+		arg->context_handle = (uint32_t) -1;
> 		break;
> 	case 2:
> 	default:
>+		/* For v2 and later core DRM would have correctly copied it */
> 		break;
> 	}
> 
> 	/* If imported a fence FD from elsewhere, then wait on it */
>-	if (arg.flags & DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD) {
>-		in_fence = sync_file_get_fence(arg.imported_fence_fd);
>+	if (arg->flags & DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD) {
>+		in_fence = sync_file_get_fence(arg->imported_fence_fd);
> 
> 		if (!in_fence) {
> 			VMW_DEBUG_USER("Cannot get imported fence\n");
>@@ -4059,11 +4045,11 @@
> 		return ret;
> 
> 	ret = vmw_execbuf_process(file_priv, dev_priv,
>-				  (void __user *)(unsigned long)arg.commands,
>-				  NULL, arg.command_size, arg.throttle_us,
>-				  arg.context_handle,
>-				  (void __user *)(unsigned long)arg.fence_rep,
>-				  NULL, arg.flags);
>+				  (void __user *)(unsigned long)arg->commands,
>+				  NULL, arg->command_size, arg->throttle_us,
>+				  arg->context_handle,
>+				  (void __user *)(unsigned long)arg->fence_rep,
>+				  NULL, arg->flags);
> 
> 	ttm_read_unlock(&dev_priv->reservation_sem);
> 	if (unlikely(ret != 0))
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
>--- linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c	2019-08-31 15:01:12.142736193 -0500
>@@ -1704,14 +1704,6 @@
> 	if (ret)
> 		return ret;
> 
>-	if (!state->allow_modeset)
>-		return ret;
>-
>-	/*
>-	 * Legacy path do not set allow_modeset properly like
>-	 * @drm_atomic_helper_update_plane, This will result in unnecessary call
>-	 * to vmw_kms_check_topology. So extra set of check.
>-	 */
> 	for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
> 		if (drm_atomic_crtc_needs_modeset(crtc_state))
> 			need_modeset = true;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
>--- linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c	2019-08-31 15:01:12.142736193 -0500
>@@ -402,14 +402,14 @@
> 
> 	if (switch_backup && new_backup != res->backup) {
> 		if (res->backup) {
>-			lockdep_assert_held(&res->backup->base.resv->lock.base);
>+			reservation_object_assert_held(res->backup->base.base.resv);
> 			list_del_init(&res->mob_head);
> 			vmw_bo_unreference(&res->backup);
> 		}
> 
> 		if (new_backup) {
> 			res->backup = vmw_bo_reference(new_backup);
>-			lockdep_assert_held(&new_backup->base.resv->lock.base);
>+			reservation_object_assert_held(new_backup->base.base.resv);
> 			list_add_tail(&res->mob_head, &new_backup->res_list);
> 		} else {
> 			res->backup = NULL;
>@@ -691,7 +691,7 @@
> 		.num_shared = 0
> 	};
> 
>-	lockdep_assert_held(&vbo->base.resv->lock.base);
>+	reservation_object_assert_held(vbo->base.base.resv);
> 	list_for_each_entry_safe(res, next, &vbo->res_list, mob_head) {
> 		if (!res->func->unbind)
> 			continue;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
>--- linux-5.3-rc6/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c	2019-08-31 15:01:12.142736193 -0500
>@@ -1669,7 +1669,7 @@
> 	rep->backup_size = res->backup_size;
> 	if (res->backup) {
> 		rep->buffer_map_handle =
>-			drm_vma_node_offset_addr(&res->backup->base.vma_node);
>+			drm_vma_node_offset_addr(&res->backup->base.base.vma_node);
> 		rep->buffer_size = res->backup->base.num_pages * PAGE_SIZE;
> 		rep->buffer_handle = backup_handle;
> 	} else {
>@@ -1745,7 +1745,7 @@
> 	rep->crep.backup_size = srf->res.backup_size;
> 	rep->crep.buffer_handle = backup_handle;
> 	rep->crep.buffer_map_handle =
>-		drm_vma_node_offset_addr(&srf->res.backup->base.vma_node);
>+		drm_vma_node_offset_addr(&srf->res.backup->base.base.vma_node);
> 	rep->crep.buffer_size = srf->res.backup->base.num_pages * PAGE_SIZE;
> 
> 	rep->creq.version = drm_vmw_gb_surface_v1;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front.c
>--- linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front.c	2019-08-31 15:01:12.142736193 -0500
>@@ -8,13 +8,18 @@
>  * Author: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
>  */
> 
>-#include <drm/drmP.h>
>+#include <linux/delay.h>
>+#include <linux/dma-mapping.h>
>+#include <linux/module.h>
>+#include <linux/of_device.h>
>+
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_ioctl.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_file.h>
> #include <drm/drm_gem.h>
> 
>-#include <linux/of_device.h>
>-
> #include <xen/platform_pci.h>
> #include <xen/xen.h>
> #include <xen/xenbus.h>
>@@ -485,15 +490,12 @@
> };
> 
> static struct drm_driver xen_drm_driver = {
>-	.driver_features           = DRIVER_GEM | DRIVER_MODESET |
>-				     DRIVER_PRIME | DRIVER_ATOMIC,
>+	.driver_features           = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.release                   = xen_drm_drv_release,
> 	.gem_vm_ops                = &xen_drm_drv_vm_ops,
> 	.gem_free_object_unlocked  = xen_drm_drv_free_object_unlocked,
> 	.prime_handle_to_fd        = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle        = drm_gem_prime_fd_to_handle,
>-	.gem_prime_import          = drm_gem_prime_import,
>-	.gem_prime_export          = drm_gem_prime_export,
> 	.gem_prime_import_sg_table = xen_drm_front_gem_import_sg_table,
> 	.gem_prime_get_sg_table    = xen_drm_front_gem_get_sg_table,
> 	.gem_prime_vmap            = xen_drm_front_gem_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_cfg.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_cfg.c
>--- linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_cfg.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_cfg.c	2019-08-31 15:01:12.142736193 -0500
>@@ -8,10 +8,10 @@
>  * Author: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
>  */
> 
>-#include <drm/drmP.h>
>-
> #include <linux/device.h>
> 
>+#include <drm/drm_print.h>
>+
> #include <xen/interface/io/displif.h>
> #include <xen/xenbus.h>
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_conn.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_conn.c
>--- linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_conn.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_conn.c	2019-08-31 15:01:12.142736193 -0500
>@@ -9,6 +9,7 @@
>  */
> 
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_probe_helper.h>
> 
> #include <video/videomode.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_conn.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_conn.h
>--- linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_conn.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_conn.h	2019-08-31 15:01:12.142736193 -0500
>@@ -11,11 +11,10 @@
> #ifndef __XEN_DRM_FRONT_CONN_H_
> #define __XEN_DRM_FRONT_CONN_H_
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_crtc.h>
>-#include <drm/drm_encoder.h>
>+#include <linux/types.h>
> 
>-#include <linux/wait.h>
>+struct drm_connector;
>+struct xen_drm_front_drm_info;
> 
> struct xen_drm_front_drm_info;
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_evtchnl.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_evtchnl.c
>--- linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_evtchnl.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_evtchnl.c	2019-08-31 15:01:12.142736193 -0500
>@@ -8,11 +8,11 @@
>  * Author: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
>  */
> 
>-#include <drm/drmP.h>
>-
> #include <linux/errno.h>
> #include <linux/irq.h>
> 
>+#include <drm/drm_print.h>
>+
> #include <xen/xenbus.h>
> #include <xen/events.h>
> #include <xen/grant_table.h>
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_gem.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_gem.c
>--- linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_gem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_gem.c	2019-08-31 15:01:12.142736193 -0500
>@@ -8,20 +8,19 @@
>  * Author: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
>  */
> 
>-#include "xen_drm_front_gem.h"
>+#include <linux/dma-buf.h>
>+#include <linux/scatterlist.h>
>+#include <linux/shmem_fs.h>
> 
>-#include <drm/drmP.h>
> #include <drm/drm_fb_helper.h>
> #include <drm/drm_gem.h>
>+#include <drm/drm_prime.h>
> #include <drm/drm_probe_helper.h>
> 
>-#include <linux/dma-buf.h>
>-#include <linux/scatterlist.h>
>-#include <linux/shmem_fs.h>
>-
> #include <xen/balloon.h>
> 
> #include "xen_drm_front.h"
>+#include "xen_drm_front_gem.h"
> 
> struct xen_gem_object {
> 	struct drm_gem_object base;
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_gem.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_gem.h
>--- linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_gem.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_gem.h	2019-08-31 15:01:12.142736193 -0500
>@@ -11,7 +11,12 @@
> #ifndef __XEN_DRM_FRONT_GEM_H
> #define __XEN_DRM_FRONT_GEM_H
> 
>-#include <drm/drmP.h>
>+struct dma_buf_attachment;
>+struct drm_device;
>+struct drm_gem_object;
>+struct file;
>+struct sg_table;
>+struct vm_area_struct;
> 
> struct drm_gem_object *xen_drm_front_gem_create(struct drm_device *dev,
> 						size_t size);
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front.h linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front.h
>--- linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front.h	2019-08-31 15:01:12.142736193 -0500
>@@ -11,13 +11,18 @@
> #ifndef __XEN_DRM_FRONT_H_
> #define __XEN_DRM_FRONT_H_
> 
>-#include <drm/drmP.h>
>-#include <drm/drm_simple_kms_helper.h>
>-
> #include <linux/scatterlist.h>
> 
>+#include <drm/drm_connector.h>
>+#include <drm/drm_simple_kms_helper.h>
>+
> #include "xen_drm_front_cfg.h"
> 
>+struct drm_device;
>+struct drm_framebuffer;
>+struct drm_gem_object;
>+struct drm_pending_vblank_event;
>+
> /**
>  * DOC: Driver modes of operation in terms of display buffers used
>  *
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_kms.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_kms.c
>--- linux-5.3-rc6/drivers/gpu/drm/xen/xen_drm_front_kms.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/xen/xen_drm_front_kms.c	2019-08-31 15:01:12.142736193 -0500
>@@ -8,17 +8,18 @@
>  * Author: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
>  */
> 
>-#include "xen_drm_front_kms.h"
>-
>-#include <drm/drmP.h>
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_drv.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem.h>
> #include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_probe_helper.h>
>+#include <drm/drm_vblank.h>
> 
> #include "xen_drm_front.h"
> #include "xen_drm_front_conn.h"
>+#include "xen_drm_front_kms.h"
> 
> /*
>  * Timeout in ms to wait for frame done event from the backend:
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/zte/zx_drm_drv.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/zte/zx_drm_drv.c
>--- linux-5.3-rc6/drivers/gpu/drm/zte/zx_drm_drv.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/zte/zx_drm_drv.c	2019-08-31 15:01:12.143736193 -0500
>@@ -14,13 +14,14 @@
> 
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_crtc.h>
>+#include <drm/drm_drv.h>
> #include <drm/drm_fb_cma_helper.h>
> #include <drm/drm_fb_helper.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_gem_framebuffer_helper.h>
> #include <drm/drm_of.h>
> #include <drm/drm_probe_helper.h>
>-#include <drm/drmP.h>
>+#include <drm/drm_vblank.h>
> 
> #include "zx_drm_drv.h"
> #include "zx_vou.h"
>@@ -34,15 +35,12 @@
> DEFINE_DRM_GEM_CMA_FOPS(zx_drm_fops);
> 
> static struct drm_driver zx_drm_driver = {
>-	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
>-			   DRIVER_ATOMIC,
>+	.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> 	.gem_free_object_unlocked = drm_gem_cma_free_object,
> 	.gem_vm_ops = &drm_gem_cma_vm_ops,
> 	.dumb_create = drm_gem_cma_dumb_create,
> 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>-	.gem_prime_export = drm_gem_prime_export,
>-	.gem_prime_import = drm_gem_prime_import,
> 	.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> 	.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> 	.gem_prime_vmap = drm_gem_cma_prime_vmap,
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/zte/zx_hdmi.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/zte/zx_hdmi.c
>--- linux-5.3-rc6/drivers/gpu/drm/zte/zx_hdmi.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/zte/zx_hdmi.c	2019-08-31 15:01:12.143736193 -0500
>@@ -19,7 +19,7 @@
> #include <drm/drm_edid.h>
> #include <drm/drm_of.h>
> #include <drm/drm_probe_helper.h>
>-#include <drm/drmP.h>
>+#include <drm/drm_print.h>
> 
> #include <sound/hdmi-codec.h>
> 
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/zte/zx_plane.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/zte/zx_plane.c
>--- linux-5.3-rc6/drivers/gpu/drm/zte/zx_plane.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/zte/zx_plane.c	2019-08-31 15:01:12.143736193 -0500
>@@ -7,10 +7,10 @@
> #include <drm/drm_atomic.h>
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_fb_cma_helper.h>
>+#include <drm/drm_fourcc.h>
> #include <drm/drm_gem_cma_helper.h>
> #include <drm/drm_modeset_helper_vtables.h>
> #include <drm/drm_plane_helper.h>
>-#include <drm/drmP.h>
> 
> #include "zx_common_regs.h"
> #include "zx_drm_drv.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/zte/zx_tvenc.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/zte/zx_tvenc.c
>--- linux-5.3-rc6/drivers/gpu/drm/zte/zx_tvenc.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/zte/zx_tvenc.c	2019-08-31 15:01:12.143736193 -0500
>@@ -7,11 +7,13 @@
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/mfd/syscon.h>
>+#include <linux/module.h>
>+#include <linux/platform_device.h>
> #include <linux/regmap.h>
> 
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
>-#include <drm/drmP.h>
> 
> #include "zx_drm_drv.h"
> #include "zx_tvenc_regs.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/zte/zx_vga.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/zte/zx_vga.c
>--- linux-5.3-rc6/drivers/gpu/drm/zte/zx_vga.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/zte/zx_vga.c	2019-08-31 15:01:12.143736193 -0500
>@@ -7,11 +7,13 @@
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/mfd/syscon.h>
>+#include <linux/module.h>
>+#include <linux/platform_device.h>
> #include <linux/regmap.h>
> 
> #include <drm/drm_atomic_helper.h>
>+#include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
>-#include <drm/drmP.h>
> 
> #include "zx_drm_drv.h"
> #include "zx_vga_regs.h"
>diff -Naur linux-5.3-rc6/drivers/gpu/drm/zte/zx_vou.c linux-5.3-rc6-agd5fed/drivers/gpu/drm/zte/zx_vou.c
>--- linux-5.3-rc6/drivers/gpu/drm/zte/zx_vou.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/gpu/drm/zte/zx_vou.c	2019-08-31 15:01:12.143736193 -0500
>@@ -6,7 +6,10 @@
> 
> #include <linux/clk.h>
> #include <linux/component.h>
>+#include <linux/module.h>
> #include <linux/of_address.h>
>+#include <linux/platform_device.h>
>+
> #include <video/videomode.h>
> 
> #include <drm/drm_atomic_helper.h>
>@@ -17,7 +20,7 @@
> #include <drm/drm_of.h>
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
>-#include <drm/drmP.h>
>+#include <drm/drm_vblank.h>
> 
> #include "zx_common_regs.h"
> #include "zx_drm_drv.h"
>diff -Naur linux-5.3-rc6/drivers/video/backlight/lcd.c linux-5.3-rc6-agd5fed/drivers/video/backlight/lcd.c
>--- linux-5.3-rc6/drivers/video/backlight/lcd.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/video/backlight/lcd.c	2019-08-31 15:01:12.143736193 -0500
>@@ -39,14 +39,6 @@
> 		if (event == FB_EVENT_BLANK) {
> 			if (ld->ops->set_power)
> 				ld->ops->set_power(ld, *(int *)evdata->data);
>-		} else if (event == FB_EARLY_EVENT_BLANK) {
>-			if (ld->ops->early_set_power)
>-				ld->ops->early_set_power(ld,
>-						*(int *)evdata->data);
>-		} else if (event == FB_R_EARLY_EVENT_BLANK) {
>-			if (ld->ops->r_early_set_power)
>-				ld->ops->r_early_set_power(ld,
>-						*(int *)evdata->data);
> 		} else {
> 			if (ld->ops->set_mode)
> 				ld->ops->set_mode(ld, evdata->data);
>diff -Naur linux-5.3-rc6/drivers/video/fbdev/amba-clcd.c linux-5.3-rc6-agd5fed/drivers/video/fbdev/amba-clcd.c
>--- linux-5.3-rc6/drivers/video/fbdev/amba-clcd.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/video/fbdev/amba-clcd.c	2019-08-31 15:01:12.143736193 -0500
>@@ -561,8 +561,10 @@
> 	struct videomode video;
> 
> 	err = of_get_display_timing(node, "panel-timing", &timing);
>-	if (err)
>+	if (err) {
>+		pr_err("%pOF: problems parsing panel-timing (%d)\n", node, err);
> 		return err;
>+	}
> 
> 	videomode_from_timing(&timing, &video);
> 
>diff -Naur linux-5.3-rc6/drivers/video/fbdev/au1200fb.c linux-5.3-rc6-agd5fed/drivers/video/fbdev/au1200fb.c
>--- linux-5.3-rc6/drivers/video/fbdev/au1200fb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/video/fbdev/au1200fb.c	2019-08-31 15:01:12.143736193 -0500
>@@ -1234,7 +1234,7 @@
> 	struct au1200fb_device *fbdev = info->par;
> 
> 	return dma_mmap_attrs(fbdev->dev, vma, fbdev->fb_mem, fbdev->fb_phys,
>-			fbdev->fb_len, DMA_ATTR_NON_CONSISTENT);
>+			fbdev->fb_len, 0);
> }
> 
> static void set_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata)
>@@ -1692,8 +1692,7 @@
> 
> 		fbdev->fb_mem = dmam_alloc_attrs(&dev->dev,
> 				PAGE_ALIGN(fbdev->fb_len),
>-				&fbdev->fb_phys, GFP_KERNEL,
>-				DMA_ATTR_NON_CONSISTENT);
>+				&fbdev->fb_phys, GFP_KERNEL, 0);
> 		if (!fbdev->fb_mem) {
> 			print_err("fail to allocate framebuffer (size: %dK))",
> 				  fbdev->fb_len / 1024);
>diff -Naur linux-5.3-rc6/drivers/video/fbdev/core/fbmem.c linux-5.3-rc6-agd5fed/drivers/video/fbdev/core/fbmem.c
>--- linux-5.3-rc6/drivers/video/fbdev/core/fbmem.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/video/fbdev/core/fbmem.c	2019-08-31 15:01:12.144736193 -0500
>@@ -1058,7 +1058,7 @@
> fb_blank(struct fb_info *info, int blank)
> {	
> 	struct fb_event event;
>-	int ret = -EINVAL, early_ret;
>+	int ret = -EINVAL;
> 
>  	if (blank > FB_BLANK_POWERDOWN)
>  		blank = FB_BLANK_POWERDOWN;
>@@ -1066,21 +1066,11 @@
> 	event.info = info;
> 	event.data = &blank;
> 
>-	early_ret = fb_notifier_call_chain(FB_EARLY_EVENT_BLANK, &event);
>-
> 	if (info->fbops->fb_blank)
>  		ret = info->fbops->fb_blank(blank, info);
> 
> 	if (!ret)
> 		fb_notifier_call_chain(FB_EVENT_BLANK, &event);
>-	else {
>-		/*
>-		 * if fb_blank is failed then revert effects of
>-		 * the early blank event.
>-		 */
>-		if (!early_ret)
>-			fb_notifier_call_chain(FB_R_EARLY_EVENT_BLANK, &event);
>-	}
> 
>  	return ret;
> }
>@@ -1957,7 +1947,7 @@
> 	struct list_head *pos, *n;
> 	struct fb_modelist *modelist;
> 	struct fb_videomode *m, mode;
>-	int err = 1;
>+	int err;
> 
> 	list_for_each_safe(pos, n, &info->modelist) {
> 		modelist = list_entry(pos, struct fb_modelist, list);
>diff -Naur linux-5.3-rc6/drivers/video/fbdev/core/fbmon.c linux-5.3-rc6-agd5fed/drivers/video/fbdev/core/fbmon.c
>--- linux-5.3-rc6/drivers/video/fbdev/core/fbmon.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/video/fbdev/core/fbmon.c	2019-08-31 15:01:12.144736193 -0500
>@@ -999,98 +999,6 @@
> 	DPRINTK("========================================\n");
> }
> 
>-/**
>- * fb_edid_add_monspecs() - add monitor video modes from E-EDID data
>- * @edid:	128 byte array with an E-EDID block
>- * @spacs:	monitor specs to be extended
>- */
>-void fb_edid_add_monspecs(unsigned char *edid, struct fb_monspecs *specs)
>-{
>-	unsigned char *block;
>-	struct fb_videomode *m;
>-	int num = 0, i;
>-	u8 svd[64], edt[(128 - 4) / DETAILED_TIMING_DESCRIPTION_SIZE];
>-	u8 pos = 4, svd_n = 0;
>-
>-	if (!edid)
>-		return;
>-
>-	if (!edid_checksum(edid))
>-		return;
>-
>-	if (edid[0] != 0x2 ||
>-	    edid[2] < 4 || edid[2] > 128 - DETAILED_TIMING_DESCRIPTION_SIZE)
>-		return;
>-
>-	DPRINTK("  Short Video Descriptors\n");
>-
>-	while (pos < edid[2]) {
>-		u8 len = edid[pos] & 0x1f, type = (edid[pos] >> 5) & 7;
>-		pr_debug("Data block %u of %u bytes\n", type, len);
>-		if (type == 2) {
>-			for (i = pos; i < pos + len; i++) {
>-				u8 idx = edid[pos + i] & 0x7f;
>-				svd[svd_n++] = idx;
>-				pr_debug("N%sative mode #%d\n",
>-					 edid[pos + i] & 0x80 ? "" : "on-n", idx);
>-			}
>-		} else if (type == 3 && len >= 3) {
>-			/* Check Vendor Specific Data Block.  For HDMI,
>-			   it is always 00-0C-03 for HDMI Licensing, LLC. */
>-			if (edid[pos + 1] == 3 && edid[pos + 2] == 0xc &&
>-			    edid[pos + 3] == 0)
>-				specs->misc |= FB_MISC_HDMI;
>-		}
>-		pos += len + 1;
>-	}
>-
>-	block = edid + edid[2];
>-
>-	DPRINTK("  Extended Detailed Timings\n");
>-
>-	for (i = 0; i < (128 - edid[2]) / DETAILED_TIMING_DESCRIPTION_SIZE;
>-	     i++, block += DETAILED_TIMING_DESCRIPTION_SIZE)
>-		if (PIXEL_CLOCK != 0)
>-			edt[num++] = block - edid;
>-
>-	/* Yikes, EDID data is totally useless */
>-	if (!(num + svd_n))
>-		return;
>-
>-	m = kcalloc(specs->modedb_len + num + svd_n,
>-		    sizeof(struct fb_videomode),
>-		    GFP_KERNEL);
>-
>-	if (!m)
>-		return;
>-
>-	memcpy(m, specs->modedb, specs->modedb_len * sizeof(struct fb_videomode));
>-
>-	for (i = specs->modedb_len; i < specs->modedb_len + num; i++) {
>-		get_detailed_timing(edid + edt[i - specs->modedb_len], &m[i]);
>-		if (i == specs->modedb_len)
>-			m[i].flag |= FB_MODE_IS_FIRST;
>-		pr_debug("Adding %ux%u@%u\n", m[i].xres, m[i].yres, m[i].refresh);
>-	}
>-
>-	for (i = specs->modedb_len + num; i < specs->modedb_len + num + svd_n; i++) {
>-		int idx = svd[i - specs->modedb_len - num];
>-		if (!idx || idx >= ARRAY_SIZE(cea_modes)) {
>-			pr_warn("Reserved SVD code %d\n", idx);
>-		} else if (!cea_modes[idx].xres) {
>-			pr_warn("Unimplemented SVD code %d\n", idx);
>-		} else {
>-			memcpy(&m[i], cea_modes + idx, sizeof(m[i]));
>-			pr_debug("Adding SVD #%d: %ux%u@%u\n", idx,
>-				 m[i].xres, m[i].yres, m[i].refresh);
>-		}
>-	}
>-
>-	kfree(specs->modedb);
>-	specs->modedb = m;
>-	specs->modedb_len = specs->modedb_len + num + svd_n;
>-}
>-
> /*
>  * VESA Generalized Timing Formula (GTF)
>  */
>@@ -1500,9 +1408,6 @@
> void fb_edid_to_monspecs(unsigned char *edid, struct fb_monspecs *specs)
> {
> }
>-void fb_edid_add_monspecs(unsigned char *edid, struct fb_monspecs *specs)
>-{
>-}
> void fb_destroy_modedb(struct fb_videomode *modedb)
> {
> }
>@@ -1610,7 +1515,6 @@
> 
> EXPORT_SYMBOL(fb_parse_edid);
> EXPORT_SYMBOL(fb_edid_to_monspecs);
>-EXPORT_SYMBOL(fb_edid_add_monspecs);
> EXPORT_SYMBOL(fb_get_mode);
> EXPORT_SYMBOL(fb_validate_mode);
> EXPORT_SYMBOL(fb_destroy_modedb);
>diff -Naur linux-5.3-rc6/drivers/video/fbdev/core/modedb.c linux-5.3-rc6-agd5fed/drivers/video/fbdev/core/modedb.c
>--- linux-5.3-rc6/drivers/video/fbdev/core/modedb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/video/fbdev/core/modedb.c	2019-08-31 15:01:12.144736193 -0500
>@@ -289,63 +289,6 @@
> };
> 
> #ifdef CONFIG_FB_MODE_HELPERS
>-const struct fb_videomode cea_modes[65] = {
>-	/* #1: 640x480p@59.94/60Hz */
>-	[1] = {
>-		NULL, 60, 640, 480, 39722, 48, 16, 33, 10, 96, 2, 0,
>-		FB_VMODE_NONINTERLACED, 0,
>-	},
>-	/* #3: 720x480p@59.94/60Hz */
>-	[3] = {
>-		NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0,
>-		FB_VMODE_NONINTERLACED, 0,
>-	},
>-	/* #5: 1920x1080i@59.94/60Hz */
>-	[5] = {
>-		NULL, 60, 1920, 1080, 13763, 148, 88, 15, 2, 44, 5,
>-		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
>-		FB_VMODE_INTERLACED, 0,
>-	},
>-	/* #7: 720(1440)x480iH@59.94/60Hz */
>-	[7] = {
>-		NULL, 60, 1440, 480, 18554/*37108*/, 114, 38, 15, 4, 124, 3, 0,
>-		FB_VMODE_INTERLACED, 0,
>-	},
>-	/* #9: 720(1440)x240pH@59.94/60Hz */
>-	[9] = {
>-		NULL, 60, 1440, 240, 18554, 114, 38, 16, 4, 124, 3, 0,
>-		FB_VMODE_NONINTERLACED, 0,
>-	},
>-	/* #18: 720x576pH@50Hz */
>-	[18] = {
>-		NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0,
>-		FB_VMODE_NONINTERLACED, 0,
>-	},
>-	/* #19: 1280x720p@50Hz */
>-	[19] = {
>-		NULL, 50, 1280, 720, 13468, 220, 440, 20, 5, 40, 5,
>-		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
>-		FB_VMODE_NONINTERLACED, 0,
>-	},
>-	/* #20: 1920x1080i@50Hz */
>-	[20] = {
>-		NULL, 50, 1920, 1080, 13480, 148, 528, 15, 5, 528, 5,
>-		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
>-		FB_VMODE_INTERLACED, 0,
>-	},
>-	/* #32: 1920x1080p@23.98/24Hz */
>-	[32] = {
>-		NULL, 24, 1920, 1080, 13468, 148, 638, 36, 4, 44, 5,
>-		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
>-		FB_VMODE_NONINTERLACED, 0,
>-	},
>-	/* #35: (2880)x480p4x@59.94/60Hz */
>-	[35] = {
>-		NULL, 60, 2880, 480, 9250, 240, 64, 30, 9, 248, 6, 0,
>-		FB_VMODE_NONINTERLACED, 0,
>-	},
>-};
>-
> const struct fb_videomode vesa_modes[] = {
> 	/* 0 640x350-85 VESA */
> 	{ NULL, 85, 640, 350, 31746,  96, 32, 60, 32, 64, 3,
>diff -Naur linux-5.3-rc6/drivers/video/fbdev/mmp/fb/mmpfb.c linux-5.3-rc6-agd5fed/drivers/video/fbdev/mmp/fb/mmpfb.c
>--- linux-5.3-rc6/drivers/video/fbdev/mmp/fb/mmpfb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/video/fbdev/mmp/fb/mmpfb.c	2019-08-31 15:01:12.144736193 -0500
>@@ -612,7 +612,6 @@
> 		ret = -ENOMEM;
> 		goto failed_destroy_mutex;
> 	}
>-	memset(fbi->fb_start, 0, fbi->fb_size);
> 	dev_info(fbi->dev, "fb %dk allocated\n", fbi->fb_size/1024);
> 
> 	/* fb power on */
>diff -Naur linux-5.3-rc6/drivers/video/fbdev/nvidia/nv_backlight.c linux-5.3-rc6-agd5fed/drivers/video/fbdev/nvidia/nv_backlight.c
>--- linux-5.3-rc6/drivers/video/fbdev/nvidia/nv_backlight.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/video/fbdev/nvidia/nv_backlight.c	2019-08-31 15:01:12.144736193 -0500
>@@ -123,8 +123,6 @@
> 
> 	printk("nvidia: Backlight initialized (%s)\n", name);
> 
>-	return;
>-
> error:
> 	return;
> }
>diff -Naur linux-5.3-rc6/drivers/video/fbdev/nvidia/nv_setup.c linux-5.3-rc6-agd5fed/drivers/video/fbdev/nvidia/nv_setup.c
>--- linux-5.3-rc6/drivers/video/fbdev/nvidia/nv_setup.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/video/fbdev/nvidia/nv_setup.c	2019-08-31 15:01:12.144736193 -0500
>@@ -119,34 +119,10 @@
> {
> 	return (VGA_RD08(par->PVIO, VGA_MIS_R));
> }
>-#if 0
>-void NVEnablePalette(struct nvidia_par *par)
>-{
>-	volatile u8 tmp;
>-
>-	tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
>-	VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
>-	par->paletteEnabled = 1;
>-}
>-void NVDisablePalette(struct nvidia_par *par)
>-{
>-	volatile u8 tmp;
>-
>-	tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
>-	VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
>-	par->paletteEnabled = 0;
>-}
>-#endif  /*  0  */
> void NVWriteDacMask(struct nvidia_par *par, u8 value)
> {
> 	VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
> }
>-#if 0
>-u8 NVReadDacMask(struct nvidia_par *par)
>-{
>-	return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
>-}
>-#endif  /*  0  */
> void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
> {
> 	VGA_WR08(par->PDIO, VGA_PEL_IR, value);
>diff -Naur linux-5.3-rc6/drivers/video/fbdev/ssd1307fb.c linux-5.3-rc6-agd5fed/drivers/video/fbdev/ssd1307fb.c
>--- linux-5.3-rc6/drivers/video/fbdev/ssd1307fb.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/video/fbdev/ssd1307fb.c	2019-08-31 15:01:12.144736193 -0500
>@@ -28,6 +28,7 @@
> #define SSD1307FB_SET_COL_RANGE		0x21
> #define SSD1307FB_SET_PAGE_RANGE	0x22
> #define SSD1307FB_CONTRAST		0x81
>+#define SSD1307FB_SET_LOOKUP_TABLE	0x91
> #define	SSD1307FB_CHARGE_PUMP		0x8d
> #define SSD1307FB_SEG_REMAP_ON		0xa1
> #define SSD1307FB_DISPLAY_OFF		0xae
>@@ -36,6 +37,7 @@
> #define SSD1307FB_START_PAGE_ADDRESS	0xb0
> #define SSD1307FB_SET_DISPLAY_OFFSET	0xd3
> #define	SSD1307FB_SET_CLOCK_FREQ	0xd5
>+#define	SSD1307FB_SET_AREA_COLOR_MODE	0xd8
> #define	SSD1307FB_SET_PRECHARGE_PERIOD	0xd9
> #define	SSD1307FB_SET_COM_PINS_CONFIG	0xda
> #define	SSD1307FB_SET_VCOMH		0xdb
>@@ -58,10 +60,14 @@
> };
> 
> struct ssd1307fb_par {
>-	u32 com_invdir;
>-	u32 com_lrremap;
>+	unsigned area_color_enable : 1;
>+	unsigned com_invdir : 1;
>+	unsigned com_lrremap : 1;
>+	unsigned com_seq : 1;
>+	unsigned lookup_table_set : 1;
>+	unsigned low_power : 1;
>+	unsigned seg_remap : 1;
> 	u32 com_offset;
>-	u32 com_seq;
> 	u32 contrast;
> 	u32 dclk_div;
> 	u32 dclk_frq;
>@@ -69,6 +75,7 @@
> 	struct i2c_client *client;
> 	u32 height;
> 	struct fb_info *info;
>+	u8 lookup_table[4];
> 	u32 page_offset;
> 	u32 prechargep1;
> 	u32 prechargep2;
>@@ -76,7 +83,6 @@
> 	u32 pwm_period;
> 	struct gpio_desc *reset;
> 	struct regulator *vbat_reg;
>-	u32 seg_remap;
> 	u32 vcomh;
> 	u32 width;
> };
>@@ -98,6 +104,9 @@
> 
> static const struct fb_var_screeninfo ssd1307fb_var = {
> 	.bits_per_pixel	= 1,
>+	.red = { .length = 1 },
>+	.green = { .length = 1 },
>+	.blue = { .length = 1 },
> };
> 
> static struct ssd1307fb_array *ssd1307fb_alloc_array(u32 len, u8 type)
>@@ -149,11 +158,12 @@
> static void ssd1307fb_update_display(struct ssd1307fb_par *par)
> {
> 	struct ssd1307fb_array *array;
>-	u8 *vmem = par->info->screen_base;
>+	u8 *vmem = par->info->screen_buffer;
>+	unsigned int line_length = par->info->fix.line_length;
>+	unsigned int pages = DIV_ROUND_UP(par->height, 8);
> 	int i, j, k;
> 
>-	array = ssd1307fb_alloc_array(par->width * par->height / 8,
>-				      SSD1307FB_DATA);
>+	array = ssd1307fb_alloc_array(par->width * pages, SSD1307FB_DATA);
> 	if (!array)
> 		return;
> 
>@@ -186,22 +196,24 @@
> 	 *  (5) A4 B4 C4 D4 E4 F4 G4 H4
> 	 */
> 
>-	for (i = 0; i < (par->height / 8); i++) {
>+	for (i = 0; i < pages; i++) {
> 		for (j = 0; j < par->width; j++) {
>+			int m = 8;
> 			u32 array_idx = i * par->width + j;
> 			array->data[array_idx] = 0;
>-			for (k = 0; k < 8; k++) {
>-				u32 page_length = par->width * i;
>-				u32 index = page_length + (par->width * k + j) / 8;
>-				u8 byte = *(vmem + index);
>-				u8 bit = byte & (1 << (j % 8));
>-				bit = bit >> (j % 8);
>+			/* Last page may be partial */
>+			if (i + 1 == pages && par->height % 8)
>+				m = par->height % 8;
>+			for (k = 0; k < m; k++) {
>+				u8 byte = vmem[(8 * i + k) * line_length +
>+					       j / 8];
>+				u8 bit = (byte >> (j % 8)) & 1;
> 				array->data[array_idx] |= bit << k;
> 			}
> 		}
> 	}
> 
>-	ssd1307fb_write_array(par->client, array, par->width * par->height / 8);
>+	ssd1307fb_write_array(par->client, array, par->width * pages);
> 	kfree(array);
> }
> 
>@@ -212,7 +224,7 @@
> 	struct ssd1307fb_par *par = info->par;
> 	unsigned long total_size;
> 	unsigned long p = *ppos;
>-	u8 __iomem *dst;
>+	void *dst;
> 
> 	total_size = info->fix.smem_len;
> 
>@@ -225,7 +237,7 @@
> 	if (!count)
> 		return -EINVAL;
> 
>-	dst = (void __force *) (info->screen_base + p);
>+	dst = info->screen_buffer + p;
> 
> 	if (copy_from_user(dst, buf, count))
> 		return -EFAULT;
>@@ -312,7 +324,7 @@
> 
> 		dev_dbg(&par->client->dev, "Using PWM%d with a %dns period.\n",
> 			par->pwm->pwm, par->pwm_period);
>-	};
>+	}
> 
> 	/* Set initial contrast */
> 	ret = ssd1307fb_write_cmd(par->client, SSD1307FB_CONTRAST);
>@@ -328,10 +340,10 @@
> 		ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SEG_REMAP_ON);
> 		if (ret < 0)
> 			return ret;
>-	};
>+	}
> 
> 	/* Set COM direction */
>-	com_invdir = 0xc0 | (par->com_invdir & 0x1) << 3;
>+	com_invdir = 0xc0 | par->com_invdir << 3;
> 	ret = ssd1307fb_write_cmd(par->client,  com_invdir);
> 	if (ret < 0)
> 		return ret;
>@@ -364,6 +376,22 @@
> 	if (ret < 0)
> 		return ret;
> 
>+	/* Set Set Area Color Mode ON/OFF & Low Power Display Mode */
>+	if (par->area_color_enable || par->low_power) {
>+		u32 mode;
>+
>+		ret = ssd1307fb_write_cmd(par->client,
>+					  SSD1307FB_SET_AREA_COLOR_MODE);
>+		if (ret < 0)
>+			return ret;
>+
>+		mode = (par->area_color_enable ? 0x30 : 0) |
>+			(par->low_power ? 5 : 0);
>+		ret = ssd1307fb_write_cmd(par->client, mode);
>+		if (ret < 0)
>+			return ret;
>+	}
>+
> 	/* Set precharge period in number of ticks from the internal clock */
> 	ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_PRECHARGE_PERIOD);
> 	if (ret < 0)
>@@ -379,8 +407,7 @@
> 	if (ret < 0)
> 		return ret;
> 
>-	compins = 0x02 | !(par->com_seq & 0x1) << 4
>-				   | (par->com_lrremap & 0x1) << 5;
>+	compins = 0x02 | !par->com_seq << 4 | par->com_lrremap << 5;
> 	ret = ssd1307fb_write_cmd(par->client, compins);
> 	if (ret < 0)
> 		return ret;
>@@ -404,6 +431,28 @@
> 	if (ret < 0)
> 		return ret;
> 
>+	/* Set lookup table */
>+	if (par->lookup_table_set) {
>+		int i;
>+
>+		ret = ssd1307fb_write_cmd(par->client,
>+					  SSD1307FB_SET_LOOKUP_TABLE);
>+		if (ret < 0)
>+			return ret;
>+
>+		for (i = 0; i < ARRAY_SIZE(par->lookup_table); ++i) {
>+			u8 val = par->lookup_table[i];
>+
>+			if (val < 31 || val > 63)
>+				dev_warn(&par->client->dev,
>+					 "lookup table index %d value out of range 31 <= %d <= 63\n",
>+					 i, val);
>+			ret = ssd1307fb_write_cmd(par->client, val);
>+			if (ret < 0)
>+				return ret;
>+		}
>+	}
>+
> 	/* Switch to horizontal addressing mode */
> 	ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_ADDRESS_MODE);
> 	if (ret < 0)
>@@ -432,12 +481,13 @@
> 	if (ret < 0)
> 		return ret;
> 
>-	ret = ssd1307fb_write_cmd(par->client, 0x0);
>+	ret = ssd1307fb_write_cmd(par->client, par->page_offset);
> 	if (ret < 0)
> 		return ret;
> 
> 	ret = ssd1307fb_write_cmd(par->client,
>-				  par->page_offset + (par->height / 8) - 1);
>+				  par->page_offset +
>+				  DIV_ROUND_UP(par->height, 8) - 1);
> 	if (ret < 0)
> 		return ret;
> 
>@@ -546,7 +596,7 @@
> 	struct fb_deferred_io *ssd1307fb_defio;
> 	u32 vmem_size;
> 	struct ssd1307fb_par *par;
>-	u8 *vmem;
>+	void *vmem;
> 	int ret;
> 
> 	if (!node) {
>@@ -603,19 +653,29 @@
> 	if (of_property_read_u32(node, "solomon,prechargep2", &par->prechargep2))
> 		par->prechargep2 = 2;
> 
>+	if (!of_property_read_u8_array(node, "solomon,lookup-table",
>+				       par->lookup_table,
>+				       ARRAY_SIZE(par->lookup_table)))
>+		par->lookup_table_set = 1;
>+
> 	par->seg_remap = !of_property_read_bool(node, "solomon,segment-no-remap");
> 	par->com_seq = of_property_read_bool(node, "solomon,com-seq");
> 	par->com_lrremap = of_property_read_bool(node, "solomon,com-lrremap");
> 	par->com_invdir = of_property_read_bool(node, "solomon,com-invdir");
>+	par->area_color_enable =
>+		of_property_read_bool(node, "solomon,area-color-enable");
>+	par->low_power = of_property_read_bool(node, "solomon,low-power");
> 
> 	par->contrast = 127;
> 	par->vcomh = par->device_info->default_vcomh;
> 
> 	/* Setup display timing */
>-	par->dclk_div = par->device_info->default_dclk_div;
>-	par->dclk_frq = par->device_info->default_dclk_frq;
>+	if (of_property_read_u32(node, "solomon,dclk-div", &par->dclk_div))
>+		par->dclk_div = par->device_info->default_dclk_div;
>+	if (of_property_read_u32(node, "solomon,dclk-frq", &par->dclk_frq))
>+		par->dclk_frq = par->device_info->default_dclk_frq;
> 
>-	vmem_size = par->width * par->height / 8;
>+	vmem_size = DIV_ROUND_UP(par->width, 8) * par->height;
> 
> 	vmem = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
> 					get_order(vmem_size));
>@@ -638,7 +698,7 @@
> 
> 	info->fbops = &ssd1307fb_ops;
> 	info->fix = ssd1307fb_fix;
>-	info->fix.line_length = par->width / 8;
>+	info->fix.line_length = DIV_ROUND_UP(par->width, 8);
> 	info->fbdefio = ssd1307fb_defio;
> 
> 	info->var = ssd1307fb_var;
>@@ -647,14 +707,7 @@
> 	info->var.yres = par->height;
> 	info->var.yres_virtual = par->height;
> 
>-	info->var.red.length = 1;
>-	info->var.red.offset = 0;
>-	info->var.green.length = 1;
>-	info->var.green.offset = 0;
>-	info->var.blue.length = 1;
>-	info->var.blue.offset = 0;
>-
>-	info->screen_base = (u8 __force __iomem *)vmem;
>+	info->screen_buffer = vmem;
> 	info->fix.smem_start = __pa(vmem);
> 	info->fix.smem_len = vmem_size;
> 
>@@ -713,7 +766,7 @@
> 	if (par->device_info->need_pwm) {
> 		pwm_disable(par->pwm);
> 		pwm_put(par->pwm);
>-	};
>+	}
> regulator_enable_error:
> 	if (par->vbat_reg)
> 		regulator_disable(par->vbat_reg);
>@@ -737,7 +790,7 @@
> 	if (par->device_info->need_pwm) {
> 		pwm_disable(par->pwm);
> 		pwm_put(par->pwm);
>-	};
>+	}
> 	fb_deferred_io_cleanup(info);
> 	__free_pages(__va(info->fix.smem_start), get_order(info->fix.smem_len));
> 	framebuffer_release(info);
>diff -Naur linux-5.3-rc6/drivers/video/of_display_timing.c linux-5.3-rc6-agd5fed/drivers/video/of_display_timing.c
>--- linux-5.3-rc6/drivers/video/of_display_timing.c	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/drivers/video/of_display_timing.c	2019-08-31 15:01:12.144736193 -0500
>@@ -119,17 +119,20 @@
> 		struct display_timing *dt)
> {
> 	struct device_node *timing_np;
>+	int ret;
> 
> 	if (!np)
> 		return -EINVAL;
> 
> 	timing_np = of_get_child_by_name(np, name);
>-	if (!timing_np) {
>-		pr_err("%pOF: could not find node '%s'\n", np, name);
>+	if (!timing_np)
> 		return -ENOENT;
>-	}
> 
>-	return of_parse_display_timing(timing_np, dt);
>+	ret = of_parse_display_timing(timing_np, dt);
>+
>+	of_node_put(timing_np);
>+
>+	return ret;
> }
> EXPORT_SYMBOL_GPL(of_get_display_timing);
> 
>diff -Naur linux-5.3-rc6/.get_maintainer.ignore linux-5.3-rc6-agd5fed/.get_maintainer.ignore
>--- linux-5.3-rc6/.get_maintainer.ignore	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/.get_maintainer.ignore	1969-12-31 18:00:00.000000000 -0600
>@@ -1,2 +0,0 @@
>-Christoph Hellwig <hch@lst.de>
>-Marc Gonzalez <marc.w.gonzalez@free.fr>
>diff -Naur linux-5.3-rc6/.gitattributes linux-5.3-rc6-agd5fed/.gitattributes
>--- linux-5.3-rc6/.gitattributes	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/.gitattributes	1969-12-31 18:00:00.000000000 -0600
>@@ -1,2 +0,0 @@
>-*.c   diff=cpp
>-*.h   diff=cpp
>diff -Naur linux-5.3-rc6/.gitignore linux-5.3-rc6-agd5fed/.gitignore
>--- linux-5.3-rc6/.gitignore	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/.gitignore	1969-12-31 18:00:00.000000000 -0600
>@@ -1,147 +0,0 @@
>-#
>-# NOTE! Don't add files that are generated in specific
>-# subdirectories here. Add them in the ".gitignore" file
>-# in that subdirectory instead.
>-#
>-# NOTE! Please use 'git ls-files -i --exclude-standard'
>-# command after changing this file, to see if there are
>-# any tracked files which get ignored after the change.
>-#
>-# Normal rules (sorted alphabetically)
>-#
>-.*
>-*.a
>-*.asn1.[ch]
>-*.bin
>-*.bz2
>-*.c.[012]*.*
>-*.dt.yaml
>-*.dtb
>-*.dtb.S
>-*.dwo
>-*.elf
>-*.gcno
>-*.gz
>-*.i
>-*.ko
>-*.lex.c
>-*.ll
>-*.lst
>-*.lz4
>-*.lzma
>-*.lzo
>-*.mod
>-*.mod.c
>-*.o
>-*.o.*
>-*.order
>-*.patch
>-*.s
>-*.so
>-*.so.dbg
>-*.su
>-*.symtypes
>-*.tab.[ch]
>-*.tar
>-*.xz
>-Module.symvers
>-modules.builtin
>-
>-#
>-# Top-level generic files
>-#
>-/tags
>-/TAGS
>-/linux
>-/vmlinux
>-/vmlinux.32
>-/vmlinux-gdb.py
>-/vmlinuz
>-/System.map
>-/Module.markers
>-/modules.builtin.modinfo
>-
>-#
>-# RPM spec file (make rpm-pkg)
>-#
>-/*.spec
>-
>-#
>-# Debian directory (make deb-pkg)
>-#
>-/debian/
>-
>-#
>-# Snap directory (make snap-pkg)
>-#
>-/snap/
>-
>-#
>-# tar directory (make tar*-pkg)
>-#
>-/tar-install/
>-
>-#
>-# We don't want to ignore the following even if they are dot-files
>-#
>-!.clang-format
>-!.cocciconfig
>-!.get_maintainer.ignore
>-!.gitattributes
>-!.gitignore
>-!.mailmap
>-
>-#
>-# Generated include files
>-#
>-/include/config/
>-/include/generated/
>-/include/ksym/
>-/arch/*/include/generated/
>-
>-# stgit generated dirs
>-patches-*
>-
>-# quilt's files
>-patches
>-series
>-
>-# cscope files
>-cscope.*
>-ncscope.*
>-
>-# gnu global files
>-GPATH
>-GRTAGS
>-GSYMS
>-GTAGS
>-
>-# id-utils files
>-ID
>-
>-*.orig
>-*~
>-\#*#
>-
>-#
>-# Leavings from module signing
>-#
>-extra_certificates
>-signing_key.pem
>-signing_key.priv
>-signing_key.x509
>-x509.genkey
>-
>-# Kconfig presets
>-/all.config
>-/alldef.config
>-/allmod.config
>-/allno.config
>-/allrandom.config
>-/allyes.config
>-
>-# Kdevelop4
>-*.kdev4
>-
>-# Clang's compilation database file
>-/compile_commands.json
>diff -Naur linux-5.3-rc6/include/drm/amd_asic_type.h linux-5.3-rc6-agd5fed/include/drm/amd_asic_type.h
>--- linux-5.3-rc6/include/drm/amd_asic_type.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/amd_asic_type.h	2019-08-31 15:01:12.144736193 -0500
>@@ -49,7 +49,11 @@
> 	CHIP_VEGA12,
> 	CHIP_VEGA20,
> 	CHIP_RAVEN,
>+	CHIP_ARCTURUS,
>+	CHIP_RENOIR,
> 	CHIP_NAVI10,
>+	CHIP_NAVI14,
>+	CHIP_NAVI12,
> 	CHIP_LAST,
> };
> 
>diff -Naur linux-5.3-rc6/include/drm/bridge/analogix_dp.h linux-5.3-rc6-agd5fed/include/drm/bridge/analogix_dp.h
>--- linux-5.3-rc6/include/drm/bridge/analogix_dp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/bridge/analogix_dp.h	2019-08-31 15:01:12.144736193 -0500
>@@ -38,10 +38,6 @@
> 			 struct drm_connector *);
> };
> 
>-int analogix_dp_psr_enabled(struct analogix_dp_device *dp);
>-int analogix_dp_enable_psr(struct analogix_dp_device *dp);
>-int analogix_dp_disable_psr(struct analogix_dp_device *dp);
>-
> int analogix_dp_resume(struct analogix_dp_device *dp);
> int analogix_dp_suspend(struct analogix_dp_device *dp);
> 
>diff -Naur linux-5.3-rc6/include/drm/drm_agpsupport.h linux-5.3-rc6-agd5fed/include/drm/drm_agpsupport.h
>--- linux-5.3-rc6/include/drm/drm_agpsupport.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_agpsupport.h	2019-08-31 15:01:12.145736194 -0500
>@@ -31,11 +31,6 @@
> void drm_free_agp(struct agp_memory * handle, int pages);
> int drm_bind_agp(struct agp_memory * handle, unsigned int start);
> int drm_unbind_agp(struct agp_memory * handle);
>-struct agp_memory *drm_agp_bind_pages(struct drm_device *dev,
>-				struct page **pages,
>-				unsigned long num_pages,
>-				uint32_t gtt_offset,
>-				uint32_t type);
> 
> struct drm_agp_head *drm_agp_init(struct drm_device *dev);
> void drm_legacy_agp_clear(struct drm_device *dev);
>@@ -80,15 +75,6 @@
> 	return -ENODEV;
> }
> 
>-static inline struct agp_memory *drm_agp_bind_pages(struct drm_device *dev,
>-					      struct page **pages,
>-					      unsigned long num_pages,
>-					      uint32_t gtt_offset,
>-					      uint32_t type)
>-{
>-	return NULL;
>-}
>-
> static inline struct drm_agp_head *drm_agp_init(struct drm_device *dev)
> {
> 	return NULL;
>diff -Naur linux-5.3-rc6/include/drm/drm_connector.h linux-5.3-rc6-agd5fed/include/drm/drm_connector.h
>--- linux-5.3-rc6/include/drm/drm_connector.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_connector.h	2019-08-31 15:01:12.145736194 -0500
>@@ -41,6 +41,7 @@
> struct drm_property_blob;
> struct drm_printer;
> struct edid;
>+struct i2c_adapter;
> 
> enum drm_connector_force {
> 	DRM_FORCE_UNSPECIFIED,
>@@ -323,6 +324,8 @@
>  *					edge of the pixel clock
>  * @DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE:	Sync signals are sampled on the falling
>  *					edge of the pixel clock
>+ * @DRM_BUS_FLAG_SHARP_SIGNALS:		Set if the Sharp-specific signals
>+ *					(SPL, CLS, PS, REV) must be used
>  */
> enum drm_bus_flags {
> 	DRM_BUS_FLAG_DE_LOW = BIT(0),
>@@ -341,6 +344,7 @@
> 	DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE = DRM_BUS_FLAG_SYNC_NEGEDGE,
> 	DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE = DRM_BUS_FLAG_SYNC_NEGEDGE,
> 	DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE = DRM_BUS_FLAG_SYNC_POSEDGE,
>+	DRM_BUS_FLAG_SHARP_SIGNALS = BIT(8),
> };
> 
> /**
>@@ -599,6 +603,12 @@
> 	unsigned int content_type;
> 
> 	/**
>+	 * @hdcp_content_type: Connector property to pass the type of
>+	 * protected content. This is most commonly used for HDCP.
>+	 */
>+	unsigned int hdcp_content_type;
>+
>+	/**
> 	 * @scaling_mode: Connector property to control the
> 	 * upscaling, mostly used for built-in panels.
> 	 */
>@@ -1308,6 +1318,18 @@
> 	 * [0]: progressive, [1]: interlaced
> 	 */
> 	int audio_latency[2];
>+
>+	/**
>+	 * @ddc: associated ddc adapter.
>+	 * A connector usually has its associated ddc adapter. If a driver uses
>+	 * this field, then an appropriate symbolic link is created in connector
>+	 * sysfs directory to make it easy for the user to tell which i2c
>+	 * adapter is for a particular display.
>+	 *
>+	 * The field should be set by calling drm_connector_init_with_ddc().
>+	 */
>+	struct i2c_adapter *ddc;
>+
> 	/**
> 	 * @null_edid_counter: track sinks that give us all zeros for the EDID.
> 	 * Needed to workaround some HW bugs where we get all 0s
>@@ -1396,6 +1418,11 @@
> 		       struct drm_connector *connector,
> 		       const struct drm_connector_funcs *funcs,
> 		       int connector_type);
>+int drm_connector_init_with_ddc(struct drm_device *dev,
>+				struct drm_connector *connector,
>+				const struct drm_connector_funcs *funcs,
>+				int connector_type,
>+				struct i2c_adapter *ddc);
> void drm_connector_attach_edid_property(struct drm_connector *connector);
> int drm_connector_register(struct drm_connector *connector);
> void drm_connector_unregister(struct drm_connector *connector);
>@@ -1481,6 +1508,7 @@
> const char *drm_get_tv_subconnector_name(int val);
> const char *drm_get_tv_select_name(int val);
> const char *drm_get_content_protection_name(int val);
>+const char *drm_get_hdcp_content_type_name(int val);
> 
> int drm_mode_create_dvi_i_properties(struct drm_device *dev);
> int drm_mode_create_tv_margin_properties(struct drm_device *dev);
>diff -Naur linux-5.3-rc6/include/drm/drm_crtc.h linux-5.3-rc6-agd5fed/include/drm/drm_crtc.h
>--- linux-5.3-rc6/include/drm/drm_crtc.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_crtc.h	2019-08-31 15:01:12.145736194 -0500
>@@ -756,6 +756,9 @@
> 	 * provided from the configured source. Drivers must accept an "auto"
> 	 * source name that will select a default source for this CRTC.
> 	 *
>+	 * This may trigger an atomic modeset commit if necessary, to enable CRC
>+	 * generation.
>+	 *
> 	 * Note that "auto" can depend upon the current modeset configuration,
> 	 * e.g. it could pick an encoder or output specific CRC sampling point.
> 	 *
>@@ -767,6 +770,7 @@
> 	 * 0 on success or a negative error code on failure.
> 	 */
> 	int (*set_crc_source)(struct drm_crtc *crtc, const char *source);
>+
> 	/**
> 	 * @verify_crc_source:
> 	 *
>diff -Naur linux-5.3-rc6/include/drm/drm_dp_helper.h linux-5.3-rc6-agd5fed/include/drm/drm_dp_helper.h
>--- linux-5.3-rc6/include/drm/drm_dp_helper.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_dp_helper.h	2019-08-31 15:01:12.145736194 -0500
>@@ -1309,6 +1309,10 @@
> 	 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
> 	 */
> 	struct drm_dp_aux_cec cec;
>+	/**
>+	 * @is_remote: Is this AUX CH actually using sideband messaging.
>+	 */
>+	bool is_remote;
> };
> 
> ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
>diff -Naur linux-5.3-rc6/include/drm/drm_dp_mst_helper.h linux-5.3-rc6-agd5fed/include/drm/drm_dp_mst_helper.h
>--- linux-5.3-rc6/include/drm/drm_dp_mst_helper.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_dp_mst_helper.h	2019-08-31 15:01:12.145736194 -0500
>@@ -643,6 +643,17 @@
> void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr);
> int __must_check
> drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr);
>+
>+ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
>+			     unsigned int offset, void *buffer, size_t size);
>+ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
>+			      unsigned int offset, void *buffer, size_t size);
>+
>+int drm_dp_mst_connector_late_register(struct drm_connector *connector,
>+				       struct drm_dp_mst_port *port);
>+void drm_dp_mst_connector_early_unregister(struct drm_connector *connector,
>+					   struct drm_dp_mst_port *port);
>+
> struct drm_dp_mst_topology_state *drm_atomic_get_mst_topology_state(struct drm_atomic_state *state,
> 								    struct drm_dp_mst_topology_mgr *mgr);
> int __must_check
>diff -Naur linux-5.3-rc6/include/drm/drm_drv.h linux-5.3-rc6-agd5fed/include/drm/drm_drv.h
>--- linux-5.3-rc6/include/drm/drm_drv.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_drv.h	2019-08-31 15:01:12.145736194 -0500
>@@ -62,12 +62,6 @@
> 	 */
> 	DRIVER_MODESET			= BIT(1),
> 	/**
>-	 * @DRIVER_PRIME:
>-	 *
>-	 * Driver implements DRM PRIME buffer sharing.
>-	 */
>-	DRIVER_PRIME			= BIT(2),
>-	/**
> 	 * @DRIVER_RENDER:
> 	 *
> 	 * Driver supports dedicated render nodes. See also the :ref:`section on
>@@ -502,21 +496,25 @@
> 	 * @gem_free_object: deconstructor for drm_gem_objects
> 	 *
> 	 * This is deprecated and should not be used by new drivers. Use
>-	 * @gem_free_object_unlocked instead.
>+	 * &drm_gem_object_funcs.free instead.
> 	 */
> 	void (*gem_free_object) (struct drm_gem_object *obj);
> 
> 	/**
> 	 * @gem_free_object_unlocked: deconstructor for drm_gem_objects
> 	 *
>-	 * This is for drivers which are not encumbered with &drm_device.struct_mutex
>-	 * legacy locking schemes. Use this hook instead of @gem_free_object.
>+	 * This is deprecated and should not be used by new drivers. Use
>+	 * &drm_gem_object_funcs.free instead.
>+	 * Compared to @gem_free_object this is not encumbered with
>+	 * &drm_device.struct_mutex legacy locking schemes.
> 	 */
> 	void (*gem_free_object_unlocked) (struct drm_gem_object *obj);
> 
> 	/**
> 	 * @gem_open_object:
> 	 *
>+	 * This callback is deprecated in favour of &drm_gem_object_funcs.open.
>+	 *
> 	 * Driver hook called upon gem handle creation
> 	 */
> 	int (*gem_open_object) (struct drm_gem_object *, struct drm_file *);
>@@ -524,6 +522,8 @@
> 	/**
> 	 * @gem_close_object:
> 	 *
>+	 * This callback is deprecated in favour of &drm_gem_object_funcs.close.
>+	 *
> 	 * Driver hook called upon gem handle release
> 	 */
> 	void (*gem_close_object) (struct drm_gem_object *, struct drm_file *);
>@@ -531,6 +531,9 @@
> 	/**
> 	 * @gem_print_info:
> 	 *
>+	 * This callback is deprecated in favour of
>+	 * &drm_gem_object_funcs.print_info.
>+	 *
> 	 * If driver subclasses struct &drm_gem_object, it can implement this
> 	 * optional hook for printing additional driver specific info.
> 	 *
>@@ -545,56 +548,108 @@
> 	/**
> 	 * @gem_create_object: constructor for gem objects
> 	 *
>-	 * Hook for allocating the GEM object struct, for use by core
>-	 * helpers.
>+	 * Hook for allocating the GEM object struct, for use by the CMA and
>+	 * SHMEM GEM helpers.
> 	 */
> 	struct drm_gem_object *(*gem_create_object)(struct drm_device *dev,
> 						    size_t size);
>-
>-	/* prime: */
> 	/**
> 	 * @prime_handle_to_fd:
> 	 *
>-	 * export handle -> fd (see drm_gem_prime_handle_to_fd() helper)
>+	 * Main PRIME export function. Should be implemented with
>+	 * drm_gem_prime_handle_to_fd() for GEM based drivers.
>+	 *
>+	 * For an in-depth discussion see :ref:`PRIME buffer sharing
>+	 * documentation <prime_buffer_sharing>`.
> 	 */
> 	int (*prime_handle_to_fd)(struct drm_device *dev, struct drm_file *file_priv,
> 				uint32_t handle, uint32_t flags, int *prime_fd);
> 	/**
> 	 * @prime_fd_to_handle:
> 	 *
>-	 * import fd -> handle (see drm_gem_prime_fd_to_handle() helper)
>+	 * Main PRIME import function. Should be implemented with
>+	 * drm_gem_prime_fd_to_handle() for GEM based drivers.
>+	 *
>+	 * For an in-depth discussion see :ref:`PRIME buffer sharing
>+	 * documentation <prime_buffer_sharing>`.
> 	 */
> 	int (*prime_fd_to_handle)(struct drm_device *dev, struct drm_file *file_priv,
> 				int prime_fd, uint32_t *handle);
> 	/**
> 	 * @gem_prime_export:
> 	 *
>-	 * export GEM -> dmabuf
>-	 *
>-	 * This defaults to drm_gem_prime_export() if not set.
>+	 * Export hook for GEM drivers. Deprecated in favour of
>+	 * &drm_gem_object_funcs.export.
> 	 */
>-	struct dma_buf * (*gem_prime_export)(struct drm_device *dev,
>-				struct drm_gem_object *obj, int flags);
>+	struct dma_buf * (*gem_prime_export)(struct drm_gem_object *obj,
>+					     int flags);
> 	/**
> 	 * @gem_prime_import:
> 	 *
>-	 * import dmabuf -> GEM
>+	 * Import hook for GEM drivers.
> 	 *
> 	 * This defaults to drm_gem_prime_import() if not set.
> 	 */
> 	struct drm_gem_object * (*gem_prime_import)(struct drm_device *dev,
> 				struct dma_buf *dma_buf);
>+
>+	/**
>+	 * @gem_prime_pin:
>+	 *
>+	 * Deprecated hook in favour of &drm_gem_object_funcs.pin.
>+	 */
> 	int (*gem_prime_pin)(struct drm_gem_object *obj);
>+
>+	/**
>+	 * @gem_prime_unpin:
>+	 *
>+	 * Deprecated hook in favour of &drm_gem_object_funcs.unpin.
>+	 */
> 	void (*gem_prime_unpin)(struct drm_gem_object *obj);
>-	struct reservation_object * (*gem_prime_res_obj)(
>-				struct drm_gem_object *obj);
>+
>+
>+	/**
>+	 * @gem_prime_get_sg_table:
>+	 *
>+	 * Deprecated hook in favour of &drm_gem_object_funcs.get_sg_table.
>+	 */
> 	struct sg_table *(*gem_prime_get_sg_table)(struct drm_gem_object *obj);
>+
>+	/**
>+	 * @gem_prime_import_sg_table:
>+	 *
>+	 * Optional hook used by the PRIME helper functions
>+	 * drm_gem_prime_import() respectively drm_gem_prime_import_dev().
>+	 */
> 	struct drm_gem_object *(*gem_prime_import_sg_table)(
> 				struct drm_device *dev,
> 				struct dma_buf_attachment *attach,
> 				struct sg_table *sgt);
>+	/**
>+	 * @gem_prime_vmap:
>+	 *
>+	 * Deprecated vmap hook for GEM drivers. Please use
>+	 * &drm_gem_object_funcs.vmap instead.
>+	 */
> 	void *(*gem_prime_vmap)(struct drm_gem_object *obj);
>+
>+	/**
>+	 * @gem_prime_vunmap:
>+	 *
>+	 * Deprecated vunmap hook for GEM drivers. Please use
>+	 * &drm_gem_object_funcs.vunmap instead.
>+	 */
> 	void (*gem_prime_vunmap)(struct drm_gem_object *obj, void *vaddr);
>+
>+	/**
>+	 * @gem_prime_mmap:
>+	 *
>+	 * mmap hook for GEM drivers, used to implement dma-buf mmap in the
>+	 * PRIME helpers.
>+	 *
>+	 * FIXME: There's way too much duplication going on here, and also moved
>+	 * to &drm_gem_object_funcs.
>+	 */
> 	int (*gem_prime_mmap)(struct drm_gem_object *obj,
> 				struct vm_area_struct *vma);
> 
>@@ -662,6 +717,9 @@
> 
> 	/**
> 	 * @gem_vm_ops: Driver private ops for this object
>+	 *
>+	 * For GEM drivers this is deprecated in favour of
>+	 * &drm_gem_object_funcs.vm_ops.
> 	 */
> 	const struct vm_operations_struct *gem_vm_ops;
> 
>diff -Naur linux-5.3-rc6/include/drm/drm_gem_framebuffer_helper.h linux-5.3-rc6-agd5fed/include/drm/drm_gem_framebuffer_helper.h
>--- linux-5.3-rc6/include/drm/drm_gem_framebuffer_helper.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_gem_framebuffer_helper.h	2019-08-31 15:01:12.145736194 -0500
>@@ -33,11 +33,4 @@
> 			  struct drm_plane_state *state);
> int drm_gem_fb_simple_display_pipe_prepare_fb(struct drm_simple_display_pipe *pipe,
> 					      struct drm_plane_state *plane_state);
>-
>-struct drm_framebuffer *
>-drm_gem_fbdev_fb_create(struct drm_device *dev,
>-			struct drm_fb_helper_surface_size *sizes,
>-			unsigned int pitch_align, struct drm_gem_object *obj,
>-			const struct drm_framebuffer_funcs *funcs);
>-
> #endif
>diff -Naur linux-5.3-rc6/include/drm/drm_gem.h linux-5.3-rc6-agd5fed/include/drm/drm_gem.h
>--- linux-5.3-rc6/include/drm/drm_gem.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_gem.h	2019-08-31 15:01:12.145736194 -0500
>@@ -101,7 +101,7 @@
> 	/**
> 	 * @pin:
> 	 *
>-	 * Pin backing buffer in memory.
>+	 * Pin backing buffer in memory. Used by the drm_gem_map_attach() helper.
> 	 *
> 	 * This callback is optional.
> 	 */
>@@ -110,7 +110,7 @@
> 	/**
> 	 * @unpin:
> 	 *
>-	 * Unpin backing buffer.
>+	 * Unpin backing buffer. Used by the drm_gem_map_detach() helper.
> 	 *
> 	 * This callback is optional.
> 	 */
>@@ -120,16 +120,21 @@
> 	 * @get_sg_table:
> 	 *
> 	 * Returns a Scatter-Gather table representation of the buffer.
>-	 * Used when exporting a buffer.
>+	 * Used when exporting a buffer by the drm_gem_map_dma_buf() helper.
>+	 * Releasing is done by calling dma_unmap_sg_attrs() and sg_free_table()
>+	 * in drm_gem_unmap_buf(), therefore these helpers and this callback
>+	 * here cannot be used for sg tables pointing at driver private memory
>+	 * ranges.
> 	 *
>-	 * This callback is mandatory if buffer export is supported.
>+	 * See also drm_prime_pages_to_sg().
> 	 */
> 	struct sg_table *(*get_sg_table)(struct drm_gem_object *obj);
> 
> 	/**
> 	 * @vmap:
> 	 *
>-	 * Returns a virtual address for the buffer.
>+	 * Returns a virtual address for the buffer. Used by the
>+	 * drm_gem_dmabuf_vmap() helper.
> 	 *
> 	 * This callback is optional.
> 	 */
>@@ -138,7 +143,8 @@
> 	/**
> 	 * @vunmap:
> 	 *
>-	 * Releases the the address previously returned by @vmap.
>+	 * Releases the the address previously returned by @vmap. Used by the
>+	 * drm_gem_dmabuf_vunmap() helper.
> 	 *
> 	 * This callback is optional.
> 	 */
>diff -Naur linux-5.3-rc6/include/drm/drm_gem_vram_helper.h linux-5.3-rc6-agd5fed/include/drm/drm_gem_vram_helper.h
>--- linux-5.3-rc6/include/drm/drm_gem_vram_helper.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_gem_vram_helper.h	2019-08-31 15:01:12.145736194 -0500
>@@ -36,7 +36,6 @@
>  * video memory becomes scarce.
>  */
> struct drm_gem_vram_object {
>-	struct drm_gem_object gem;
> 	struct ttm_buffer_object bo;
> 	struct ttm_bo_kmap_obj kmap;
> 
>@@ -68,7 +67,7 @@
> static inline struct drm_gem_vram_object *drm_gem_vram_of_gem(
> 	struct drm_gem_object *gem)
> {
>-	return container_of(gem, struct drm_gem_vram_object, gem);
>+	return container_of(gem, struct drm_gem_vram_object, bo.base);
> }
> 
> struct drm_gem_vram_object *drm_gem_vram_create(struct drm_device *dev,
>@@ -108,7 +107,6 @@
>  * Helpers for struct drm_driver
>  */
> 
>-void drm_gem_vram_driver_gem_free_object_unlocked(struct drm_gem_object *gem);
> int drm_gem_vram_driver_dumb_create(struct drm_file *file,
> 				    struct drm_device *dev,
> 				    struct drm_mode_create_dumb *args);
>@@ -124,30 +122,8 @@
>  * &struct drm_driver with default functions.
>  */
> #define DRM_GEM_VRAM_DRIVER \
>-	.gem_free_object_unlocked = \
>-		drm_gem_vram_driver_gem_free_object_unlocked, \
> 	.dumb_create		  = drm_gem_vram_driver_dumb_create, \
>-	.dumb_map_offset	  = drm_gem_vram_driver_dumb_mmap_offset
>-
>-/*
>- * PRIME helpers for struct drm_driver
>- */
>-
>-int drm_gem_vram_driver_gem_prime_pin(struct drm_gem_object *obj);
>-void drm_gem_vram_driver_gem_prime_unpin(struct drm_gem_object *obj);
>-void *drm_gem_vram_driver_gem_prime_vmap(struct drm_gem_object *obj);
>-void drm_gem_vram_driver_gem_prime_vunmap(struct drm_gem_object *obj,
>-					  void *vaddr);
>-int drm_gem_vram_driver_gem_prime_mmap(struct drm_gem_object *obj,
>-				       struct vm_area_struct *vma);
>-
>-#define DRM_GEM_VRAM_DRIVER_PRIME \
>-	.gem_prime_export = drm_gem_prime_export, \
>-	.gem_prime_import = drm_gem_prime_import, \
>-	.gem_prime_pin	  = drm_gem_vram_driver_gem_prime_pin, \
>-	.gem_prime_unpin  = drm_gem_vram_driver_gem_prime_unpin, \
>-	.gem_prime_vmap	  = drm_gem_vram_driver_gem_prime_vmap, \
>-	.gem_prime_vunmap = drm_gem_vram_driver_gem_prime_vunmap, \
>-	.gem_prime_mmap	  = drm_gem_vram_driver_gem_prime_mmap
>+	.dumb_map_offset	  = drm_gem_vram_driver_dumb_mmap_offset, \
>+	.gem_prime_mmap		  = drm_gem_prime_mmap
> 
> #endif
>diff -Naur linux-5.3-rc6/include/drm/drm_hdcp.h linux-5.3-rc6-agd5fed/include/drm/drm_hdcp.h
>--- linux-5.3-rc6/include/drm/drm_hdcp.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_hdcp.h	2019-08-31 15:01:12.146736194 -0500
>@@ -291,5 +291,12 @@
> bool drm_hdcp_check_ksvs_revoked(struct drm_device *dev,
> 				 u8 *ksvs, u32 ksv_count);
> int drm_connector_attach_content_protection_property(
>-		struct drm_connector *connector);
>+		struct drm_connector *connector, bool hdcp_content_type);
>+void drm_hdcp_update_content_protection(struct drm_connector *connector,
>+					u64 val);
>+
>+/* Content Type classification for HDCP2.2 vs others */
>+#define DRM_MODE_HDCP_CONTENT_TYPE0		0
>+#define DRM_MODE_HDCP_CONTENT_TYPE1		1
>+
> #endif
>diff -Naur linux-5.3-rc6/include/drm/drm_ioctl.h linux-5.3-rc6-agd5fed/include/drm/drm_ioctl.h
>--- linux-5.3-rc6/include/drm/drm_ioctl.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_ioctl.h	2019-08-31 15:01:12.146736194 -0500
>@@ -114,6 +114,9 @@
> 	 * Whether &drm_ioctl_desc.func should be called with the DRM BKL held
> 	 * or not. Enforced as the default for all modern drivers, hence there
> 	 * should never be a need to set this flag.
>+	 *
>+	 * Do not use anywhere else than for the VBLANK_WAIT IOCTL, which is the
>+	 * only legacy IOCTL which needs this.
> 	 */
> 	DRM_UNLOCKED		= BIT(4),
> 	/**
>diff -Naur linux-5.3-rc6/include/drm/drm_mipi_dbi.h linux-5.3-rc6-agd5fed/include/drm/drm_mipi_dbi.h
>--- linux-5.3-rc6/include/drm/drm_mipi_dbi.h	1969-12-31 18:00:00.000000000 -0600
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_mipi_dbi.h	2019-08-31 15:01:12.146736194 -0500
>@@ -0,0 +1,188 @@
>+/* SPDX-License-Identifier: GPL-2.0-or-later */
>+/*
>+ * MIPI Display Bus Interface (DBI) LCD controller support
>+ *
>+ * Copyright 2016 Noralf TrÃ¸nnes
>+ */
>+
>+#ifndef __LINUX_MIPI_DBI_H
>+#define __LINUX_MIPI_DBI_H
>+
>+#include <linux/mutex.h>
>+#include <drm/drm_device.h>
>+#include <drm/drm_simple_kms_helper.h>
>+
>+struct drm_rect;
>+struct spi_device;
>+struct gpio_desc;
>+struct regulator;
>+
>+/**
>+ * struct mipi_dbi - MIPI DBI interface
>+ */
>+struct mipi_dbi {
>+	/**
>+	 * @cmdlock: Command lock
>+	 */
>+	struct mutex cmdlock;
>+
>+	/**
>+	 * @command: Bus specific callback executing commands.
>+	 */
>+	int (*command)(struct mipi_dbi *dbi, u8 *cmd, u8 *param, size_t num);
>+
>+	/**
>+	 * @read_commands: Array of read commands terminated by a zero entry.
>+	 *                 Reading is disabled if this is NULL.
>+	 */
>+	const u8 *read_commands;
>+
>+	/**
>+	 * @swap_bytes: Swap bytes in buffer before transfer
>+	 */
>+	bool swap_bytes;
>+
>+	/**
>+	 * @reset: Optional reset gpio
>+	 */
>+	struct gpio_desc *reset;
>+
>+	/* Type C specific */
>+
>+	/**
>+	 * @spi: SPI device
>+	 */
>+	struct spi_device *spi;
>+
>+	/**
>+	 * @dc: Optional D/C gpio.
>+	 */
>+	struct gpio_desc *dc;
>+
>+	/**
>+	 * @tx_buf9: Buffer used for Option 1 9-bit conversion
>+	 */
>+	void *tx_buf9;
>+
>+	/**
>+	 * @tx_buf9_len: Size of tx_buf9.
>+	 */
>+	size_t tx_buf9_len;
>+};
>+
>+/**
>+ * struct mipi_dbi_dev - MIPI DBI device
>+ */
>+struct mipi_dbi_dev {
>+	/**
>+	 * @drm: DRM device
>+	 */
>+	struct drm_device drm;
>+
>+	/**
>+	 * @pipe: Display pipe structure
>+	 */
>+	struct drm_simple_display_pipe pipe;
>+
>+	/**
>+	 * @connector: Connector
>+	 */
>+	struct drm_connector connector;
>+
>+	/**
>+	 * @mode: Fixed display mode
>+	 */
>+	struct drm_display_mode mode;
>+
>+	/**
>+	 * @enabled: Pipeline is enabled
>+	 */
>+	bool enabled;
>+
>+	/**
>+	 * @tx_buf: Buffer used for transfer (copy clip rect area)
>+	 */
>+	u16 *tx_buf;
>+
>+	/**
>+	 * @rotation: initial rotation in degrees Counter Clock Wise
>+	 */
>+	unsigned int rotation;
>+
>+	/**
>+	 * @backlight: backlight device (optional)
>+	 */
>+	struct backlight_device *backlight;
>+
>+	/**
>+	 * @regulator: power regulator (optional)
>+	 */
>+	struct regulator *regulator;
>+
>+	/**
>+	 * @dbi: MIPI DBI interface
>+	 */
>+	struct mipi_dbi dbi;
>+};
>+
>+static inline struct mipi_dbi_dev *drm_to_mipi_dbi_dev(struct drm_device *drm)
>+{
>+	return container_of(drm, struct mipi_dbi_dev, drm);
>+}
>+
>+int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *dbi,
>+		      struct gpio_desc *dc);
>+int mipi_dbi_dev_init_with_formats(struct mipi_dbi_dev *dbidev,
>+				   const struct drm_simple_display_pipe_funcs *funcs,
>+				   const uint32_t *formats, unsigned int format_count,
>+				   const struct drm_display_mode *mode,
>+				   unsigned int rotation, size_t tx_buf_size);
>+int mipi_dbi_dev_init(struct mipi_dbi_dev *dbidev,
>+		      const struct drm_simple_display_pipe_funcs *funcs,
>+		      const struct drm_display_mode *mode, unsigned int rotation);
>+void mipi_dbi_release(struct drm_device *drm);
>+void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
>+			  struct drm_plane_state *old_state);
>+void mipi_dbi_enable_flush(struct mipi_dbi_dev *dbidev,
>+			   struct drm_crtc_state *crtc_state,
>+			   struct drm_plane_state *plan_state);
>+void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe);
>+void mipi_dbi_hw_reset(struct mipi_dbi *dbi);
>+bool mipi_dbi_display_is_on(struct mipi_dbi *dbi);
>+int mipi_dbi_poweron_reset(struct mipi_dbi_dev *dbidev);
>+int mipi_dbi_poweron_conditional_reset(struct mipi_dbi_dev *dbidev);
>+
>+u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len);
>+int mipi_dbi_spi_transfer(struct spi_device *spi, u32 speed_hz,
>+			  u8 bpw, const void *buf, size_t len);
>+
>+int mipi_dbi_command_read(struct mipi_dbi *dbi, u8 cmd, u8 *val);
>+int mipi_dbi_command_buf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len);
>+int mipi_dbi_command_stackbuf(struct mipi_dbi *dbi, u8 cmd, u8 *data, size_t len);
>+int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
>+		      struct drm_rect *clip, bool swap);
>+/**
>+ * mipi_dbi_command - MIPI DCS command with optional parameter(s)
>+ * @dbi: MIPI DBI structure
>+ * @cmd: Command
>+ * @seq...: Optional parameter(s)
>+ *
>+ * Send MIPI DCS command to the controller. Use mipi_dbi_command_read() for
>+ * get/read.
>+ *
>+ * Returns:
>+ * Zero on success, negative error code on failure.
>+ */
>+#define mipi_dbi_command(dbi, cmd, seq...) \
>+({ \
>+	u8 d[] = { seq }; \
>+	mipi_dbi_command_stackbuf(dbi, cmd, d, ARRAY_SIZE(d)); \
>+})
>+
>+#ifdef CONFIG_DEBUG_FS
>+int mipi_dbi_debugfs_init(struct drm_minor *minor);
>+#else
>+#define mipi_dbi_debugfs_init		NULL
>+#endif
>+
>+#endif /* __LINUX_MIPI_DBI_H */
>diff -Naur linux-5.3-rc6/include/drm/drm_mode_config.h linux-5.3-rc6-agd5fed/include/drm/drm_mode_config.h
>--- linux-5.3-rc6/include/drm/drm_mode_config.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_mode_config.h	2019-08-31 15:01:12.146736194 -0500
>@@ -849,6 +849,12 @@
> 	 */
> 	struct drm_property *content_protection_property;
> 
>+	/**
>+	 * @hdcp_content_type_property: DRM ENUM property for type of
>+	 * Protected Content.
>+	 */
>+	struct drm_property *hdcp_content_type_property;
>+
> 	/* dumb ioctl parameters */
> 	uint32_t preferred_depth, prefer_shadow;
> 
>diff -Naur linux-5.3-rc6/include/drm/drm_panel.h linux-5.3-rc6-agd5fed/include/drm/drm_panel.h
>--- linux-5.3-rc6/include/drm/drm_panel.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_panel.h	2019-08-31 15:01:12.146736194 -0500
>@@ -24,6 +24,7 @@
> #ifndef __DRM_PANEL_H__
> #define __DRM_PANEL_H__
> 
>+#include <linux/err.h>
> #include <linux/errno.h>
> #include <linux/list.h>
> 
>diff -Naur linux-5.3-rc6/include/drm/drm_prime.h linux-5.3-rc6-agd5fed/include/drm/drm_prime.h
>--- linux-5.3-rc6/include/drm/drm_prime.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_prime.h	2019-08-31 15:01:12.146736194 -0500
>@@ -42,7 +42,6 @@
>  * This just contains the internal &struct dma_buf and handle caches for each
>  * &struct drm_file used by the PRIME core code.
>  */
>-
> struct drm_prime_file_private {
> /* private: */
> 	struct mutex lock;
>@@ -64,25 +63,18 @@
> 
> struct device;
> 
>-struct dma_buf *drm_gem_prime_export(struct drm_device *dev,
>-				     struct drm_gem_object *obj,
>-				     int flags);
>+/* core prime functions */
>+struct dma_buf *drm_gem_dmabuf_export(struct drm_device *dev,
>+				      struct dma_buf_export_info *exp_info);
>+void drm_gem_dmabuf_release(struct dma_buf *dma_buf);
>+
>+int drm_gem_prime_fd_to_handle(struct drm_device *dev,
>+			       struct drm_file *file_priv, int prime_fd, uint32_t *handle);
> int drm_gem_prime_handle_to_fd(struct drm_device *dev,
> 			       struct drm_file *file_priv, uint32_t handle, uint32_t flags,
> 			       int *prime_fd);
>-int drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
>-struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev,
>-					    struct dma_buf *dma_buf);
> 
>-struct drm_gem_object *drm_gem_prime_import_dev(struct drm_device *dev,
>-						struct dma_buf *dma_buf,
>-						struct device *attach_dev);
>-
>-int drm_gem_prime_fd_to_handle(struct drm_device *dev,
>-			       struct drm_file *file_priv, int prime_fd, uint32_t *handle);
>-struct dma_buf *drm_gem_dmabuf_export(struct drm_device *dev,
>-				      struct dma_buf_export_info *exp_info);
>-void drm_gem_dmabuf_release(struct dma_buf *dma_buf);
>+/* helper functions for exporting */
> int drm_gem_map_attach(struct dma_buf *dma_buf,
> 		       struct dma_buf_attachment *attach);
> void drm_gem_map_detach(struct dma_buf *dma_buf,
>@@ -94,12 +86,25 @@
> 			   enum dma_data_direction dir);
> void *drm_gem_dmabuf_vmap(struct dma_buf *dma_buf);
> void drm_gem_dmabuf_vunmap(struct dma_buf *dma_buf, void *vaddr);
>+
>+int drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
> int drm_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma);
> 
>-int drm_prime_sg_to_page_addr_arrays(struct sg_table *sgt, struct page **pages,
>-				     dma_addr_t *addrs, int max_pages);
> struct sg_table *drm_prime_pages_to_sg(struct page **pages, unsigned int nr_pages);
>+struct dma_buf *drm_gem_prime_export(struct drm_gem_object *obj,
>+				     int flags);
>+
>+/* helper functions for importing */
>+struct drm_gem_object *drm_gem_prime_import_dev(struct drm_device *dev,
>+						struct dma_buf *dma_buf,
>+						struct device *attach_dev);
>+struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev,
>+					    struct dma_buf *dma_buf);
>+
> void drm_prime_gem_destroy(struct drm_gem_object *obj, struct sg_table *sg);
> 
>+int drm_prime_sg_to_page_addr_arrays(struct sg_table *sgt, struct page **pages,
>+				     dma_addr_t *addrs, int max_pages);
>+
> 
> #endif /* __DRM_PRIME_H__ */
>diff -Naur linux-5.3-rc6/include/drm/drm_sysfs.h linux-5.3-rc6-agd5fed/include/drm/drm_sysfs.h
>--- linux-5.3-rc6/include/drm/drm_sysfs.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_sysfs.h	2019-08-31 15:01:12.146736194 -0500
>@@ -4,10 +4,13 @@
> 
> struct drm_device;
> struct device;
>+struct drm_connector;
>+struct drm_property;
> 
> int drm_class_device_register(struct device *dev);
> void drm_class_device_unregister(struct device *dev);
> 
> void drm_sysfs_hotplug_event(struct drm_device *dev);
>-
>+void drm_sysfs_connector_status_event(struct drm_connector *connector,
>+				      struct drm_property *property);
> #endif
>diff -Naur linux-5.3-rc6/include/drm/drm_vblank.h linux-5.3-rc6-agd5fed/include/drm/drm_vblank.h
>--- linux-5.3-rc6/include/drm/drm_vblank.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_vblank.h	2019-08-31 15:01:12.146736194 -0500
>@@ -30,7 +30,6 @@
> 
> #include <drm/drm_file.h>
> #include <drm/drm_modes.h>
>-#include <uapi/drm/drm.h>
> 
> struct drm_device;
> struct drm_crtc;
>diff -Naur linux-5.3-rc6/include/drm/drm_vram_mm_helper.h linux-5.3-rc6-agd5fed/include/drm/drm_vram_mm_helper.h
>--- linux-5.3-rc6/include/drm/drm_vram_mm_helper.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/drm_vram_mm_helper.h	2019-08-31 15:01:12.146736194 -0500
>@@ -3,6 +3,8 @@
> #ifndef DRM_VRAM_MM_HELPER_H
> #define DRM_VRAM_MM_HELPER_H
> 
>+#include <drm/drm_file.h>
>+#include <drm/drm_ioctl.h>
> #include <drm/ttm/ttm_bo_driver.h>
> 
> struct drm_device;
>diff -Naur linux-5.3-rc6/include/drm/i915_component.h linux-5.3-rc6-agd5fed/include/drm/i915_component.h
>--- linux-5.3-rc6/include/drm/i915_component.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/i915_component.h	2019-08-31 15:01:12.146736194 -0500
>@@ -34,7 +34,7 @@
> /* MAX_PORT is the number of port
>  * It must be sync with I915_MAX_PORTS defined i915_drv.h
>  */
>-#define MAX_PORTS 6
>+#define MAX_PORTS 9
> 
> /**
>  * struct i915_audio_component - Used for direct communication between i915 and hda drivers
>diff -Naur linux-5.3-rc6/include/drm/i915_drm.h linux-5.3-rc6-agd5fed/include/drm/i915_drm.h
>--- linux-5.3-rc6/include/drm/i915_drm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/i915_drm.h	2019-08-31 15:01:12.146736194 -0500
>@@ -30,11 +30,11 @@
> #include <uapi/drm/i915_drm.h>
> 
> /* For use by IPS driver */
>-extern unsigned long i915_read_mch_val(void);
>-extern bool i915_gpu_raise(void);
>-extern bool i915_gpu_lower(void);
>-extern bool i915_gpu_busy(void);
>-extern bool i915_gpu_turbo_disable(void);
>+unsigned long i915_read_mch_val(void);
>+bool i915_gpu_raise(void);
>+bool i915_gpu_lower(void);
>+bool i915_gpu_busy(void);
>+bool i915_gpu_turbo_disable(void);
> 
> /* Exported from arch/x86/kernel/early-quirks.c */
> extern struct resource intel_graphics_stolen_res;
>@@ -109,6 +109,9 @@
> 	PORT_D,
> 	PORT_E,
> 	PORT_F,
>+	PORT_G,
>+	PORT_H,
>+	PORT_I,
> 
> 	I915_MAX_PORTS
> };
>diff -Naur linux-5.3-rc6/include/drm/i915_pciids.h linux-5.3-rc6-agd5fed/include/drm/i915_pciids.h
>--- linux-5.3-rc6/include/drm/i915_pciids.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/i915_pciids.h	2019-08-31 15:01:12.146736194 -0500
>@@ -568,7 +568,8 @@
> 	INTEL_VGA_DEVICE(0x8A56, info), \
> 	INTEL_VGA_DEVICE(0x8A71, info), \
> 	INTEL_VGA_DEVICE(0x8A70, info), \
>-	INTEL_VGA_DEVICE(0x8A53, info)
>+	INTEL_VGA_DEVICE(0x8A53, info), \
>+	INTEL_VGA_DEVICE(0x8A54, info)
> 
> #define INTEL_ICL_11_IDS(info) \
> 	INTEL_ICL_PORT_F_IDS(info), \
>@@ -582,4 +583,14 @@
> 	INTEL_VGA_DEVICE(0x4551, info), \
> 	INTEL_VGA_DEVICE(0x4541, info)
> 
>+/* TGL */
>+#define INTEL_TGL_12_IDS(info) \
>+	INTEL_VGA_DEVICE(0x9A49, info), \
>+	INTEL_VGA_DEVICE(0x9A40, info), \
>+	INTEL_VGA_DEVICE(0x9A59, info), \
>+	INTEL_VGA_DEVICE(0x9A60, info), \
>+	INTEL_VGA_DEVICE(0x9A68, info), \
>+	INTEL_VGA_DEVICE(0x9A70, info), \
>+	INTEL_VGA_DEVICE(0x9A78, info)
>+
> #endif /* _I915_PCIIDS_H */
>diff -Naur linux-5.3-rc6/include/drm/tinydrm/mipi-dbi.h linux-5.3-rc6-agd5fed/include/drm/tinydrm/mipi-dbi.h
>--- linux-5.3-rc6/include/drm/tinydrm/mipi-dbi.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/tinydrm/mipi-dbi.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,117 +0,0 @@
>-/* SPDX-License-Identifier: GPL-2.0-or-later */
>-/*
>- * MIPI Display Bus Interface (DBI) LCD controller support
>- *
>- * Copyright 2016 Noralf TrÃ¸nnes
>- */
>-
>-#ifndef __LINUX_MIPI_DBI_H
>-#define __LINUX_MIPI_DBI_H
>-
>-#include <linux/mutex.h>
>-#include <drm/drm_device.h>
>-#include <drm/drm_simple_kms_helper.h>
>-
>-struct drm_rect;
>-struct spi_device;
>-struct gpio_desc;
>-struct regulator;
>-
>-/**
>- * struct mipi_dbi - MIPI DBI controller
>- * @spi: SPI device
>- * @enabled: Pipeline is enabled
>- * @cmdlock: Command lock
>- * @command: Bus specific callback executing commands.
>- * @read_commands: Array of read commands terminated by a zero entry.
>- *                 Reading is disabled if this is NULL.
>- * @dc: Optional D/C gpio.
>- * @tx_buf: Buffer used for transfer (copy clip rect area)
>- * @tx_buf9: Buffer used for Option 1 9-bit conversion
>- * @tx_buf9_len: Size of tx_buf9.
>- * @swap_bytes: Swap bytes in buffer before transfer
>- * @reset: Optional reset gpio
>- * @rotation: initial rotation in degrees Counter Clock Wise
>- * @backlight: backlight device (optional)
>- * @regulator: power regulator (optional)
>- */
>-struct mipi_dbi {
>-	/**
>-	 * @drm: DRM device
>-	 */
>-	struct drm_device drm;
>-
>-	/**
>-	 * @pipe: Display pipe structure
>-	 */
>-	struct drm_simple_display_pipe pipe;
>-
>-	struct spi_device *spi;
>-	bool enabled;
>-	struct mutex cmdlock;
>-	int (*command)(struct mipi_dbi *mipi, u8 *cmd, u8 *param, size_t num);
>-	const u8 *read_commands;
>-	struct gpio_desc *dc;
>-	u16 *tx_buf;
>-	void *tx_buf9;
>-	size_t tx_buf9_len;
>-	bool swap_bytes;
>-	struct gpio_desc *reset;
>-	unsigned int rotation;
>-	struct backlight_device *backlight;
>-	struct regulator *regulator;
>-};
>-
>-static inline struct mipi_dbi *drm_to_mipi_dbi(struct drm_device *drm)
>-{
>-	return container_of(drm, struct mipi_dbi, drm);
>-}
>-
>-int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *mipi,
>-		      struct gpio_desc *dc);
>-int mipi_dbi_init(struct mipi_dbi *mipi,
>-		  const struct drm_simple_display_pipe_funcs *funcs,
>-		  const struct drm_display_mode *mode, unsigned int rotation);
>-void mipi_dbi_release(struct drm_device *drm);
>-void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
>-			  struct drm_plane_state *old_state);
>-void mipi_dbi_enable_flush(struct mipi_dbi *mipi,
>-			   struct drm_crtc_state *crtc_state,
>-			   struct drm_plane_state *plan_state);
>-void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe);
>-void mipi_dbi_hw_reset(struct mipi_dbi *mipi);
>-bool mipi_dbi_display_is_on(struct mipi_dbi *mipi);
>-int mipi_dbi_poweron_reset(struct mipi_dbi *mipi);
>-int mipi_dbi_poweron_conditional_reset(struct mipi_dbi *mipi);
>-u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len);
>-
>-int mipi_dbi_command_read(struct mipi_dbi *mipi, u8 cmd, u8 *val);
>-int mipi_dbi_command_buf(struct mipi_dbi *mipi, u8 cmd, u8 *data, size_t len);
>-int mipi_dbi_command_stackbuf(struct mipi_dbi *mipi, u8 cmd, u8 *data, size_t len);
>-int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
>-		      struct drm_rect *clip, bool swap);
>-/**
>- * mipi_dbi_command - MIPI DCS command with optional parameter(s)
>- * @mipi: MIPI structure
>- * @cmd: Command
>- * @seq...: Optional parameter(s)
>- *
>- * Send MIPI DCS command to the controller. Use mipi_dbi_command_read() for
>- * get/read.
>- *
>- * Returns:
>- * Zero on success, negative error code on failure.
>- */
>-#define mipi_dbi_command(mipi, cmd, seq...) \
>-({ \
>-	u8 d[] = { seq }; \
>-	mipi_dbi_command_stackbuf(mipi, cmd, d, ARRAY_SIZE(d)); \
>-})
>-
>-#ifdef CONFIG_DEBUG_FS
>-int mipi_dbi_debugfs_init(struct drm_minor *minor);
>-#else
>-#define mipi_dbi_debugfs_init		NULL
>-#endif
>-
>-#endif /* __LINUX_MIPI_DBI_H */
>diff -Naur linux-5.3-rc6/include/drm/tinydrm/tinydrm-helpers.h linux-5.3-rc6-agd5fed/include/drm/tinydrm/tinydrm-helpers.h
>--- linux-5.3-rc6/include/drm/tinydrm/tinydrm-helpers.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/tinydrm/tinydrm-helpers.h	1969-12-31 18:00:00.000000000 -0600
>@@ -1,75 +0,0 @@
>-/* SPDX-License-Identifier: GPL-2.0-or-later */
>-/*
>- * Copyright (C) 2016 Noralf TrÃ¸nnes
>- */
>-
>-#ifndef __LINUX_TINYDRM_HELPERS_H
>-#define __LINUX_TINYDRM_HELPERS_H
>-
>-struct backlight_device;
>-struct drm_device;
>-struct drm_display_mode;
>-struct drm_framebuffer;
>-struct drm_rect;
>-struct drm_simple_display_pipe;
>-struct drm_simple_display_pipe_funcs;
>-struct spi_transfer;
>-struct spi_message;
>-struct spi_device;
>-struct device;
>-
>-/**
>- * tinydrm_machine_little_endian - Machine is little endian
>- *
>- * Returns:
>- * true if *defined(__LITTLE_ENDIAN)*, false otherwise
>- */
>-static inline bool tinydrm_machine_little_endian(void)
>-{
>-#if defined(__LITTLE_ENDIAN)
>-	return true;
>-#else
>-	return false;
>-#endif
>-}
>-
>-int tinydrm_display_pipe_init(struct drm_device *drm,
>-			      struct drm_simple_display_pipe *pipe,
>-			      const struct drm_simple_display_pipe_funcs *funcs,
>-			      int connector_type,
>-			      const uint32_t *formats,
>-			      unsigned int format_count,
>-			      const struct drm_display_mode *mode,
>-			      unsigned int rotation);
>-
>-size_t tinydrm_spi_max_transfer_size(struct spi_device *spi, size_t max_len);
>-bool tinydrm_spi_bpw_supported(struct spi_device *spi, u8 bpw);
>-int tinydrm_spi_transfer(struct spi_device *spi, u32 speed_hz,
>-			 struct spi_transfer *header, u8 bpw, const void *buf,
>-			 size_t len);
>-void _tinydrm_dbg_spi_message(struct spi_device *spi, struct spi_message *m);
>-
>-#ifdef DEBUG
>-/**
>- * tinydrm_dbg_spi_message - Dump SPI message
>- * @spi: SPI device
>- * @m: SPI message
>- *
>- * Dumps info about the transfers in a SPI message including buffer content.
>- * DEBUG has to be defined for this function to be enabled alongside setting
>- * the DRM_UT_DRIVER bit of &drm_debug.
>- */
>-static inline void tinydrm_dbg_spi_message(struct spi_device *spi,
>-					   struct spi_message *m)
>-{
>-	if (drm_debug & DRM_UT_DRIVER)
>-		_tinydrm_dbg_spi_message(spi, m);
>-}
>-#else
>-static inline void tinydrm_dbg_spi_message(struct spi_device *spi,
>-					   struct spi_message *m)
>-{
>-}
>-#endif /* DEBUG */
>-
>-#endif /* __LINUX_TINYDRM_HELPERS_H */
>diff -Naur linux-5.3-rc6/include/drm/ttm/ttm_bo_api.h linux-5.3-rc6-agd5fed/include/drm/ttm/ttm_bo_api.h
>--- linux-5.3-rc6/include/drm/ttm/ttm_bo_api.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/ttm/ttm_bo_api.h	2019-08-31 15:01:12.146736194 -0500
>@@ -31,6 +31,7 @@
> #ifndef _TTM_BO_API_H_
> #define _TTM_BO_API_H_
> 
>+#include <drm/drm_gem.h>
> #include <drm/drm_hashtab.h>
> #include <drm/drm_vma_manager.h>
> #include <linux/kref.h>
>@@ -127,6 +128,7 @@
> /**
>  * struct ttm_buffer_object
>  *
>+ * @base: drm_gem_object superclass data.
>  * @bdev: Pointer to the buffer object device structure.
>  * @type: The bo type.
>  * @destroy: Destruction function. If NULL, kfree is used.
>@@ -150,7 +152,6 @@
>  * @ddestroy: List head for the delayed destroy list.
>  * @swap: List head for swap LRU list.
>  * @moving: Fence set when BO is moving
>- * @vma_node: Address space manager node.
>  * @offset: The current GPU offset, which can have different meanings
>  * depending on the memory type. For SYSTEM type memory, it should be 0.
>  * @cur_placement: Hint of current placement.
>@@ -169,6 +170,8 @@
>  */
> 
> struct ttm_buffer_object {
>+	struct drm_gem_object base;
>+
> 	/**
> 	 * Members constant at init.
> 	 */
>@@ -215,9 +218,6 @@
> 	 */
> 
> 	struct dma_fence *moving;
>-
>-	struct drm_vma_offset_node vma_node;
>-
> 	unsigned priority;
> 
> 	/**
>@@ -230,8 +230,6 @@
> 
> 	struct sg_table *sg;
> 
>-	struct reservation_object *resv;
>-	struct reservation_object ttm_resv;
> 	struct mutex wu_mutex;
> };
> 
>@@ -768,4 +766,23 @@
> 			struct ttm_operation_ctx *ctx);
> void ttm_bo_swapout_all(struct ttm_bo_device *bdev);
> int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo);
>+
>+/**
>+ * ttm_bo_uses_embedded_gem_object - check if the given bo uses the
>+ * embedded drm_gem_object.
>+ *
>+ * Most ttm drivers are using gem too, so the embedded
>+ * ttm_buffer_object.base will be initialized by the driver (before
>+ * calling ttm_bo_init).  It is also possible to use ttm without gem
>+ * though (vmwgfx does that).
>+ *
>+ * This helper will figure whenever a given ttm bo is a gem object too
>+ * or not.
>+ *
>+ * @bo: The bo to check.
>+ */
>+static inline bool ttm_bo_uses_embedded_gem_object(struct ttm_buffer_object *bo)
>+{
>+	return bo->base.dev != NULL;
>+}
> #endif
>diff -Naur linux-5.3-rc6/include/drm/ttm/ttm_bo_driver.h linux-5.3-rc6-agd5fed/include/drm/ttm/ttm_bo_driver.h
>--- linux-5.3-rc6/include/drm/ttm/ttm_bo_driver.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/drm/ttm/ttm_bo_driver.h	2019-08-31 15:01:12.147736194 -0500
>@@ -390,6 +390,16 @@
> 	 * notify driver that a BO was deleted from LRU.
> 	 */
> 	void (*del_from_lru_notify)(struct ttm_buffer_object *bo);
>+
>+	/**
>+	 * Notify the driver that we're about to release a BO
>+	 *
>+	 * @bo: BO that is about to be released
>+	 *
>+	 * Gives the driver a chance to do any cleanup, including
>+	 * adding fences that may force a delayed delete
>+	 */
>+	void (*release_notify)(struct ttm_buffer_object *bo);
> };
> 
> /**
>@@ -654,14 +664,14 @@
> 		if (WARN_ON(ticket))
> 			return -EBUSY;
> 
>-		success = reservation_object_trylock(bo->resv);
>+		success = reservation_object_trylock(bo->base.resv);
> 		return success ? 0 : -EBUSY;
> 	}
> 
> 	if (interruptible)
>-		ret = reservation_object_lock_interruptible(bo->resv, ticket);
>+		ret = reservation_object_lock_interruptible(bo->base.resv, ticket);
> 	else
>-		ret = reservation_object_lock(bo->resv, ticket);
>+		ret = reservation_object_lock(bo->base.resv, ticket);
> 	if (ret == -EINTR)
> 		return -ERESTARTSYS;
> 	return ret;
>@@ -745,10 +755,10 @@
> 	WARN_ON(!kref_read(&bo->kref));
> 
> 	if (interruptible)
>-		ret = ww_mutex_lock_slow_interruptible(&bo->resv->lock,
>-						       ticket);
>+		ret = reservation_object_lock_slow_interruptible(bo->base.resv,
>+								 ticket);
> 	else
>-		ww_mutex_lock_slow(&bo->resv->lock, ticket);
>+		reservation_object_lock_slow(bo->base.resv, ticket);
> 
> 	if (likely(ret == 0))
> 		ttm_bo_del_sub_from_lru(bo);
>@@ -773,7 +783,7 @@
> 	else
> 		ttm_bo_move_to_lru_tail(bo, NULL);
> 	spin_unlock(&bo->bdev->glob->lru_lock);
>-	reservation_object_unlock(bo->resv);
>+	reservation_object_unlock(bo->base.resv);
> }
> 
> /*
>diff -Naur linux-5.3-rc6/include/linux/fb.h linux-5.3-rc6-agd5fed/include/linux/fb.h
>--- linux-5.3-rc6/include/linux/fb.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/linux/fb.h	2019-08-31 15:01:12.147736194 -0500
>@@ -135,10 +135,6 @@
> 
> /*      A display blank is requested       */
> #define FB_EVENT_BLANK                  0x09
>-/*      A hardware display blank early change occurred */
>-#define FB_EARLY_EVENT_BLANK		0x10
>-/*      A hardware display blank revert early change occurred */
>-#define FB_R_EARLY_EVENT_BLANK		0x11
> 
> struct fb_event {
> 	struct fb_info *info;
>@@ -721,8 +717,6 @@
> extern const unsigned char *fb_firmware_edid(struct device *device);
> extern void fb_edid_to_monspecs(unsigned char *edid,
> 				struct fb_monspecs *specs);
>-extern void fb_edid_add_monspecs(unsigned char *edid,
>-				 struct fb_monspecs *specs);
> extern void fb_destroy_modedb(struct fb_videomode *modedb);
> extern int fb_find_mode_cvt(struct fb_videomode *mode, int margins, int rb);
> extern unsigned char *fb_ddc_read(struct i2c_adapter *adapter);
>@@ -796,7 +790,6 @@
> 
> extern const char *fb_mode_option;
> extern const struct fb_videomode vesa_modes[];
>-extern const struct fb_videomode cea_modes[65];
> extern const struct dmt_videomode dmt_modes[];
> 
> struct fb_modelist {
>diff -Naur linux-5.3-rc6/include/linux/lcd.h linux-5.3-rc6-agd5fed/include/linux/lcd.h
>--- linux-5.3-rc6/include/linux/lcd.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/linux/lcd.h	2019-08-31 15:01:12.147736194 -0500
>@@ -41,16 +41,6 @@
> 	/* Get the LCD panel power status (0: full on, 1..3: controller
> 	   power on, flat panel power off, 4: full off), see FB_BLANK_XXX */
> 	int (*get_power)(struct lcd_device *);
>-	/*
>-	 * Enable or disable power to the LCD(0: on; 4: off, see FB_BLANK_XXX)
>-	 * and this callback would be called proir to fb driver's callback.
>-	 *
>-	 * P.S. note that if early_set_power is not NULL then early fb notifier
>-	 *	would be registered.
>-	 */
>-	int (*early_set_power)(struct lcd_device *, int power);
>-	/* revert the effects of the early blank event. */
>-	int (*r_early_set_power)(struct lcd_device *, int power);
> 	/* Enable or disable power to the LCD (0: on; 4: off, see FB_BLANK_XXX) */
> 	int (*set_power)(struct lcd_device *, int power);
> 	/* Get the current contrast setting (0-max_contrast) */
>diff -Naur linux-5.3-rc6/include/linux/reservation.h linux-5.3-rc6-agd5fed/include/linux/reservation.h
>--- linux-5.3-rc6/include/linux/reservation.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/linux/reservation.h	2019-08-31 15:01:12.147736194 -0500
>@@ -82,50 +82,6 @@
> 	lockdep_assert_held(&(obj)->lock.base)
> 
> /**
>- * reservation_object_init - initialize a reservation object
>- * @obj: the reservation object
>- */
>-static inline void
>-reservation_object_init(struct reservation_object *obj)
>-{
>-	ww_mutex_init(&obj->lock, &reservation_ww_class);
>-
>-	__seqcount_init(&obj->seq, reservation_seqcount_string, &reservation_seqcount_class);
>-	RCU_INIT_POINTER(obj->fence, NULL);
>-	RCU_INIT_POINTER(obj->fence_excl, NULL);
>-}
>-
>-/**
>- * reservation_object_fini - destroys a reservation object
>- * @obj: the reservation object
>- */
>-static inline void
>-reservation_object_fini(struct reservation_object *obj)
>-{
>-	int i;
>-	struct reservation_object_list *fobj;
>-	struct dma_fence *excl;
>-
>-	/*
>-	 * This object should be dead and all references must have
>-	 * been released to it, so no need to be protected with rcu.
>-	 */
>-	excl = rcu_dereference_protected(obj->fence_excl, 1);
>-	if (excl)
>-		dma_fence_put(excl);
>-
>-	fobj = rcu_dereference_protected(obj->fence, 1);
>-	if (fobj) {
>-		for (i = 0; i < fobj->shared_count; ++i)
>-			dma_fence_put(rcu_dereference_protected(fobj->shared[i], 1));
>-
>-		kfree(fobj);
>-	}
>-
>-	ww_mutex_destroy(&obj->lock);
>-}
>-
>-/**
>  * reservation_object_get_list - get the reservation object's
>  * shared fence list, with update-side lock held
>  * @obj: the reservation object
>@@ -184,6 +140,38 @@
> 	return ww_mutex_lock_interruptible(&obj->lock, ctx);
> }
> 
>+/**
>+ * reservation_object_lock_slow - slowpath lock the reservation object
>+ * @obj: the reservation object
>+ * @ctx: the locking context
>+ *
>+ * Acquires the reservation object after a die case. This function
>+ * will sleep until the lock becomes available. See reservation_object_lock() as
>+ * well.
>+ */
>+static inline void
>+reservation_object_lock_slow(struct reservation_object *obj,
>+			     struct ww_acquire_ctx *ctx)
>+{
>+	ww_mutex_lock_slow(&obj->lock, ctx);
>+}
>+
>+/**
>+ * reservation_object_lock_slow_interruptible - slowpath lock the reservation
>+ * object, interruptible
>+ * @obj: the reservation object
>+ * @ctx: the locking context
>+ *
>+ * Acquires the reservation object interruptible after a die case. This function
>+ * will sleep until the lock becomes available. See
>+ * reservation_object_lock_interruptible() as well.
>+ */
>+static inline int
>+reservation_object_lock_slow_interruptible(struct reservation_object *obj,
>+					   struct ww_acquire_ctx *ctx)
>+{
>+	return ww_mutex_lock_slow_interruptible(&obj->lock, ctx);
>+}
> 
> /**
>  * reservation_object_trylock - trylock the reservation object
>@@ -206,6 +194,31 @@
> }
> 
> /**
>+ * reservation_object_is_locked - is the reservation object locked
>+ * @obj: the reservation object
>+ *
>+ * Returns true if the mutex is locked, false if unlocked.
>+ */
>+static inline bool
>+reservation_object_is_locked(struct reservation_object *obj)
>+{
>+	return ww_mutex_is_locked(&obj->lock);
>+}
>+
>+/**
>+ * reservation_object_locking_ctx - returns the context used to lock the object
>+ * @obj: the reservation object
>+ *
>+ * Returns the context used to lock a reservation object or NULL if no context
>+ * was used or the object is not locked at all.
>+ */
>+static inline struct ww_acquire_ctx *
>+reservation_object_locking_ctx(struct reservation_object *obj)
>+{
>+	return READ_ONCE(obj->lock.ctx);
>+}
>+
>+/**
>  * reservation_object_unlock - unlock the reservation object
>  * @obj: the reservation object
>  *
>@@ -271,6 +284,8 @@
> 	return fence;
> }
> 
>+void reservation_object_init(struct reservation_object *obj);
>+void reservation_object_fini(struct reservation_object *obj);
> int reservation_object_reserve_shared(struct reservation_object *obj,
> 				      unsigned int num_fences);
> void reservation_object_add_shared_fence(struct reservation_object *obj,
>diff -Naur linux-5.3-rc6/include/linux/soc/amlogic/meson-canvas.h linux-5.3-rc6-agd5fed/include/linux/soc/amlogic/meson-canvas.h
>--- linux-5.3-rc6/include/linux/soc/amlogic/meson-canvas.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/linux/soc/amlogic/meson-canvas.h	2019-08-31 15:01:12.147736194 -0500
>@@ -20,6 +20,7 @@
> #define MESON_CANVAS_ENDIAN_SWAP64	0x7
> #define MESON_CANVAS_ENDIAN_SWAP128	0xf
> 
>+struct device;
> struct meson_canvas;
> 
> /**
>diff -Naur linux-5.3-rc6/include/uapi/drm/amdgpu_drm.h linux-5.3-rc6-agd5fed/include/uapi/drm/amdgpu_drm.h
>--- linux-5.3-rc6/include/uapi/drm/amdgpu_drm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/uapi/drm/amdgpu_drm.h	2019-08-31 15:01:12.147736194 -0500
>@@ -128,6 +128,10 @@
>  * for the second page onward should be set to NC.
>  */
> #define AMDGPU_GEM_CREATE_MQD_GFX9		(1 << 8)
>+/* Flag that BO may contain sensitive data that must be wiped before
>+ * releasing the memory
>+ */
>+#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE	(1 << 9)
> 
> struct drm_amdgpu_gem_create_in  {
> 	/** the requested memory size */
>diff -Naur linux-5.3-rc6/include/uapi/drm/drm_mode.h linux-5.3-rc6-agd5fed/include/uapi/drm/drm_mode.h
>--- linux-5.3-rc6/include/uapi/drm/drm_mode.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/uapi/drm/drm_mode.h	2019-08-31 15:01:12.147736194 -0500
>@@ -361,6 +361,7 @@
> #define DRM_MODE_CONNECTOR_DSI		16
> #define DRM_MODE_CONNECTOR_DPI		17
> #define DRM_MODE_CONNECTOR_WRITEBACK	18
>+#define DRM_MODE_CONNECTOR_SPI		19
> 
> struct drm_mode_get_connector {
> 
>diff -Naur linux-5.3-rc6/include/uapi/drm/i915_drm.h linux-5.3-rc6-agd5fed/include/uapi/drm/i915_drm.h
>--- linux-5.3-rc6/include/uapi/drm/i915_drm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/uapi/drm/i915_drm.h	2019-08-31 15:01:12.148736194 -0500
>@@ -521,6 +521,7 @@
> #define   I915_SCHEDULER_CAP_PRIORITY	(1ul << 1)
> #define   I915_SCHEDULER_CAP_PREEMPTION	(1ul << 2)
> #define   I915_SCHEDULER_CAP_SEMAPHORES	(1ul << 3)
>+#define   I915_SCHEDULER_CAP_ENGINE_BUSY_STATS	(1ul << 4)
> 
> #define I915_PARAM_HUC_STATUS		 42
> 
>diff -Naur linux-5.3-rc6/include/uapi/drm/panfrost_drm.h linux-5.3-rc6-agd5fed/include/uapi/drm/panfrost_drm.h
>--- linux-5.3-rc6/include/uapi/drm/panfrost_drm.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/uapi/drm/panfrost_drm.h	2019-08-31 15:01:12.148736194 -0500
>@@ -127,6 +127,45 @@
> 
> enum drm_panfrost_param {
> 	DRM_PANFROST_PARAM_GPU_PROD_ID,
>+	DRM_PANFROST_PARAM_GPU_REVISION,
>+	DRM_PANFROST_PARAM_SHADER_PRESENT,
>+	DRM_PANFROST_PARAM_TILER_PRESENT,
>+	DRM_PANFROST_PARAM_L2_PRESENT,
>+	DRM_PANFROST_PARAM_STACK_PRESENT,
>+	DRM_PANFROST_PARAM_AS_PRESENT,
>+	DRM_PANFROST_PARAM_JS_PRESENT,
>+	DRM_PANFROST_PARAM_L2_FEATURES,
>+	DRM_PANFROST_PARAM_CORE_FEATURES,
>+	DRM_PANFROST_PARAM_TILER_FEATURES,
>+	DRM_PANFROST_PARAM_MEM_FEATURES,
>+	DRM_PANFROST_PARAM_MMU_FEATURES,
>+	DRM_PANFROST_PARAM_THREAD_FEATURES,
>+	DRM_PANFROST_PARAM_MAX_THREADS,
>+	DRM_PANFROST_PARAM_THREAD_MAX_WORKGROUP_SZ,
>+	DRM_PANFROST_PARAM_THREAD_MAX_BARRIER_SZ,
>+	DRM_PANFROST_PARAM_COHERENCY_FEATURES,
>+	DRM_PANFROST_PARAM_TEXTURE_FEATURES0,
>+	DRM_PANFROST_PARAM_TEXTURE_FEATURES1,
>+	DRM_PANFROST_PARAM_TEXTURE_FEATURES2,
>+	DRM_PANFROST_PARAM_TEXTURE_FEATURES3,
>+	DRM_PANFROST_PARAM_JS_FEATURES0,
>+	DRM_PANFROST_PARAM_JS_FEATURES1,
>+	DRM_PANFROST_PARAM_JS_FEATURES2,
>+	DRM_PANFROST_PARAM_JS_FEATURES3,
>+	DRM_PANFROST_PARAM_JS_FEATURES4,
>+	DRM_PANFROST_PARAM_JS_FEATURES5,
>+	DRM_PANFROST_PARAM_JS_FEATURES6,
>+	DRM_PANFROST_PARAM_JS_FEATURES7,
>+	DRM_PANFROST_PARAM_JS_FEATURES8,
>+	DRM_PANFROST_PARAM_JS_FEATURES9,
>+	DRM_PANFROST_PARAM_JS_FEATURES10,
>+	DRM_PANFROST_PARAM_JS_FEATURES11,
>+	DRM_PANFROST_PARAM_JS_FEATURES12,
>+	DRM_PANFROST_PARAM_JS_FEATURES13,
>+	DRM_PANFROST_PARAM_JS_FEATURES14,
>+	DRM_PANFROST_PARAM_JS_FEATURES15,
>+	DRM_PANFROST_PARAM_NR_CORE_GROUPS,
>+	DRM_PANFROST_PARAM_THREAD_TLS_ALLOC,
> };
> 
> struct drm_panfrost_get_param {
>diff -Naur linux-5.3-rc6/include/uapi/linux/media-bus-format.h linux-5.3-rc6-agd5fed/include/uapi/linux/media-bus-format.h
>--- linux-5.3-rc6/include/uapi/linux/media-bus-format.h	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/include/uapi/linux/media-bus-format.h	2019-08-31 15:01:12.148736194 -0500
>@@ -34,7 +34,7 @@
> 
> #define MEDIA_BUS_FMT_FIXED			0x0001
> 
>-/* RGB - next is	0x101c */
>+/* RGB - next is	0x101d */
> #define MEDIA_BUS_FMT_RGB444_1X12		0x1016
> #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE	0x1001
> #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE	0x1002
>@@ -55,6 +55,7 @@
> #define MEDIA_BUS_FMT_RGB888_1X24		0x100a
> #define MEDIA_BUS_FMT_RGB888_2X12_BE		0x100b
> #define MEDIA_BUS_FMT_RGB888_2X12_LE		0x100c
>+#define MEDIA_BUS_FMT_RGB888_3X8		0x101c
> #define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG		0x1011
> #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA	0x1012
> #define MEDIA_BUS_FMT_ARGB8888_1X32		0x100d
>diff -Naur linux-5.3-rc6/.mailmap linux-5.3-rc6-agd5fed/.mailmap
>--- linux-5.3-rc6/.mailmap	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/.mailmap	1969-12-31 18:00:00.000000000 -0600
>@@ -1,251 +0,0 @@
>-#
>-# This list is used by git-shortlog to fix a few botched name translations
>-# in the git archive, either because the author's full name was messed up
>-# and/or not always written the same way, making contributions from the
>-# same person appearing not to be so or badly displayed.
>-#
>-# repo-abbrev: /pub/scm/linux/kernel/git/
>-#
>-
>-Aaron Durbin <adurbin@google.com>
>-Adam Oldham <oldhamca@gmail.com>
>-Adam Radford <aradford@gmail.com>
>-Adrian Bunk <bunk@stusta.de>
>-Adriana Reus <adi.reus@gmail.com> <adriana.reus@intel.com>
>-Alan Cox <alan@lxorguk.ukuu.org.uk>
>-Alan Cox <root@hraefn.swansea.linux.org.uk>
>-Aleksey Gorelov <aleksey_gorelov@phoenix.com>
>-Aleksandar Markovic <aleksandar.markovic@mips.com> <aleksandar.markovic@imgtec.com>
>-Alex Shi <alex.shi@linux.alibaba.com> <alex.shi@intel.com>
>-Alex Shi <alex.shi@linux.alibaba.com> <alex.shi@linaro.org>
>-Alexei Starovoitov <ast@kernel.org> <ast@plumgrid.com>
>-Alexei Starovoitov <ast@kernel.org> <alexei.starovoitov@gmail.com>
>-Alexei Starovoitov <ast@kernel.org> <ast@fb.com>
>-Al Viro <viro@ftp.linux.org.uk>
>-Al Viro <viro@zenIV.linux.org.uk>
>-Andi Shyti <andi@etezian.org> <andi.shyti@samsung.com>
>-Andreas Herrmann <aherrman@de.ibm.com>
>-Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>
>-Andrew Morton <akpm@linux-foundation.org>
>-Andrew Vasquez <andrew.vasquez@qlogic.com>
>-Andy Adamson <andros@citi.umich.edu>
>-Antoine Tenart <antoine.tenart@free-electrons.com>
>-Antonio Ospite <ao2@ao2.it> <ao2@amarulasolutions.com>
>-Archit Taneja <archit@ti.com>
>-Arnaud Patard <arnaud.patard@rtp-net.org>
>-Arnd Bergmann <arnd@arndb.de>
>-Axel Dyks <xl@xlsigned.net>
>-Axel Lin <axel.lin@gmail.com>
>-Bart Van Assche <bvanassche@acm.org> <bart.vanassche@wdc.com>
>-Bart Van Assche <bvanassche@acm.org> <bart.vanassche@sandisk.com>
>-Ben Gardner <bgardner@wabtec.com>
>-Ben M Cahill <ben.m.cahill@intel.com>
>-BjÃ¶rn Steinbrink <B.Steinbrink@gmx.de>
>-Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
>-Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
>-Boris Brezillon <bbrezillon@kernel.org> <b.brezillon.dev@gmail.com>
>-Boris Brezillon <bbrezillon@kernel.org> <b.brezillon@overkiz.com>
>-Brian Avery <b.avery@hp.com>
>-Brian King <brking@us.ibm.com>
>-Christoph Hellwig <hch@lst.de>
>-Christophe Ricard <christophe.ricard@gmail.com>
>-Corey Minyard <minyard@acm.org>
>-Damian Hobson-Garcia <dhobsong@igel.co.jp>
>-Daniel Borkmann <daniel@iogearbox.net> <dborkman@redhat.com>
>-Daniel Borkmann <daniel@iogearbox.net> <dborkmann@redhat.com>
>-Daniel Borkmann <daniel@iogearbox.net> <danborkmann@iogearbox.net>
>-Daniel Borkmann <daniel@iogearbox.net> <daniel.borkmann@tik.ee.ethz.ch>
>-Daniel Borkmann <daniel@iogearbox.net> <danborkmann@googlemail.com>
>-Daniel Borkmann <daniel@iogearbox.net> <dxchgb@gmail.com>
>-David Brownell <david-b@pacbell.net>
>-David Woodhouse <dwmw2@shinybook.infradead.org>
>-Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@mips.com>
>-Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@imgtec.com>
>-Dengcheng Zhu <dzhu@wavecomp.com> <dczhu@mips.com>
>-Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@gmail.com>
>-Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
>-Domen Puncer <domen@coderock.org>
>-Douglas Gilbert <dougg@torque.net>
>-Ed L. Cashin <ecashin@coraid.com>
>-Evgeniy Polyakov <johnpol@2ka.mipt.ru>
>-Felipe W Damasio <felipewd@terra.com.br>
>-Felix Kuhling <fxkuehl@gmx.de>
>-Felix Moeller <felix@derklecks.de>
>-Filipe Lautert <filipe@icewall.org>
>-Franck Bui-Huu <vagabon.xyz@gmail.com>
>-Frank Rowand <frowand.list@gmail.com> <frowand@mvista.com>
>-Frank Rowand <frowand.list@gmail.com> <frank.rowand@am.sony.com>
>-Frank Rowand <frowand.list@gmail.com> <frank.rowand@sonymobile.com>
>-Frank Zago <fzago@systemfabricworks.com>
>-Greg Kroah-Hartman <greg@echidna.(none)>
>-Greg Kroah-Hartman <gregkh@suse.de>
>-Greg Kroah-Hartman <greg@kroah.com>
>-Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com>
>-Hanjun Guo <guohanjun@huawei.com> <hanjun.guo@linaro.org>
>-Henk Vergonet <Henk.Vergonet@gmail.com>
>-Henrik Kretzschmar <henne@nachtwindheim.de>
>-Henrik Rydberg <rydberg@bitmath.org>
>-Herbert Xu <herbert@gondor.apana.org.au>
>-Jacob Shin <Jacob.Shin@amd.com>
>-James Bottomley <jejb@mulgrave.(none)>
>-James Bottomley <jejb@titanic.il.steeleye.com>
>-James E Wilson <wilson@specifix.com>
>-James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
>-James Hogan <jhogan@kernel.org> <james@albanarts.com>
>-James Ketrenos <jketreno@io.(none)>
>-Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com>
>-Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>
>-Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
>-<javier@osg.samsung.com> <javier.martinez@collabora.co.uk>
>-Jean Tourrilhes <jt@hpl.hp.com>
>-<jean-philippe@linaro.org> <jean-philippe.brucker@arm.com>
>-Jeff Garzik <jgarzik@pretzel.yyz.us>
>-Jeff Layton <jlayton@kernel.org> <jlayton@redhat.com>
>-Jeff Layton <jlayton@kernel.org> <jlayton@poochiereds.net>
>-Jeff Layton <jlayton@kernel.org> <jlayton@primarydata.com>
>-Jens Axboe <axboe@suse.de>
>-Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
>-Johan Hovold <johan@kernel.org> <jhovold@gmail.com>
>-Johan Hovold <johan@kernel.org> <johan@hovoldconsulting.com>
>-John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
>-John Stultz <johnstul@us.ibm.com>
>-<josh@joshtriplett.org> <josh@freedesktop.org>
>-<josh@joshtriplett.org> <josh@kernel.org>
>-<josh@joshtriplett.org> <josht@linux.vnet.ibm.com>
>-<josh@joshtriplett.org> <josht@us.ibm.com>
>-<josh@joshtriplett.org> <josht@vnet.ibm.com>
>-Juha Yrjola <at solidboot.com>
>-Juha Yrjola <juha.yrjola@nokia.com>
>-Juha Yrjola <juha.yrjola@solidboot.com>
>-Julien Thierry <julien.thierry.kdev@gmail.com> <julien.thierry@arm.com>
>-Kay Sievers <kay.sievers@vrfy.org>
>-Kenneth W Chen <kenneth.w.chen@intel.com>
>-Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
>-Koushik <raghavendra.koushik@neterion.com>
>-Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski@samsung.com>
>-Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
>-Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>-Leon Romanovsky <leon@kernel.org> <leon@leon.nu>
>-Leon Romanovsky <leon@kernel.org> <leonro@mellanox.com>
>-Leonid I Ananiev <leonid.i.ananiev@intel.com>
>-Linas Vepstas <linas@austin.ibm.com>
>-Linus LÃ¼ssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
>-Linus LÃ¼ssing <linus.luessing@c0d3.blue> <linus.luessing@ascom.ch>
>-Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org>
>-Li Yang <leoyang.li@nxp.com> <leoli@freescale.com>
>-Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com>
>-Marc Zyngier <maz@kernel.org> <marc.zyngier@arm.com>
>-Marcin Nowakowski <marcin.nowakowski@mips.com> <marcin.nowakowski@imgtec.com>
>-Mark Brown <broonie@sirena.org.uk>
>-Mark Yao <markyao0591@gmail.com> <mark.yao@rock-chips.com>
>-Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>
>-Martin Kepplinger <martink@posteo.de> <martin.kepplinger@ginzinger.com>
>-Mathieu Othacehe <m.othacehe@gmail.com>
>-Matthew Wilcox <willy@infradead.org> <matthew.r.wilcox@intel.com>
>-Matthew Wilcox <willy@infradead.org> <matthew@wil.cx>
>-Matthew Wilcox <willy@infradead.org> <mawilcox@linuxonhyperv.com>
>-Matthew Wilcox <willy@infradead.org> <mawilcox@microsoft.com>
>-Matthew Wilcox <willy@infradead.org> <willy@debian.org>
>-Matthew Wilcox <willy@infradead.org> <willy@linux.intel.com>
>-Matthew Wilcox <willy@infradead.org> <willy@parisc-linux.org>
>-Matthieu CASTET <castet.matthieu@free.fr>
>-Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@brturbo.com.br>
>-Mauro Carvalho Chehab <mchehab@kernel.org> <maurochehab@gmail.com>
>-Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@infradead.org>
>-Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@redhat.com>
>-Mauro Carvalho Chehab <mchehab@kernel.org> <m.chehab@samsung.com>
>-Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@osg.samsung.com>
>-Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@s-opensource.com>
>-Matt Ranostay <mranostay@gmail.com> Matthew Ranostay <mranostay@embeddedalley.com>
>-Matt Ranostay <mranostay@gmail.com> <matt.ranostay@intel.com>
>-Matt Ranostay <matt.ranostay@konsulko.com> <matt@ranostay.consulting>
>-Matt Redfearn <matt.redfearn@mips.com> <matt.redfearn@imgtec.com>
>-Mayuresh Janorkar <mayur@ti.com>
>-Michael Buesch <m@bues.ch>
>-Michel DÃ¤nzer <michel@tungstengraphics.com>
>-Miodrag Dinic <miodrag.dinic@mips.com> <miodrag.dinic@imgtec.com>
>-Miquel Raynal <miquel.raynal@bootlin.com> <miquel.raynal@free-electrons.com>
>-Mitesh shah <mshah@teja.com>
>-Mohit Kumar <mohit.kumar@st.com> <mohit.kumar.dhaka@gmail.com>
>-Morten Welinder <terra@gnome.org>
>-Morten Welinder <welinder@anemone.rentec.com>
>-Morten Welinder <welinder@darter.rentec.com>
>-Morten Welinder <welinder@troll.com>
>-Mythri P K <mythripk@ti.com>
>-Nguyen Anh Quynh <aquynh@gmail.com>
>-Nicolas Pitre <nico@fluxnic.net> <nicolas.pitre@linaro.org>
>-Nicolas Pitre <nico@fluxnic.net> <nico@linaro.org>
>-Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
>-Patrick Mochel <mochel@digitalimplant.org>
>-Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
>-Peter A Jonsson <pj@ludd.ltu.se>
>-Peter Oruba <peter@oruba.de>
>-Peter Oruba <peter.oruba@amd.com>
>-Pratyush Anand <pratyush.anand@gmail.com> <pratyush.anand@st.com>
>-Praveen BP <praveenbp@ti.com>
>-Punit Agrawal <punitagrawal@gmail.com> <punit.agrawal@arm.com>
>-Qais Yousef <qsyousef@gmail.com> <qais.yousef@imgtec.com>
>-Oleksij Rempel <linux@rempel-privat.de> <bug-track@fisher-privat.net>
>-Oleksij Rempel <linux@rempel-privat.de> <external.Oleksij.Rempel@de.bosch.com>
>-Oleksij Rempel <linux@rempel-privat.de> <fixed-term.Oleksij.Rempel@de.bosch.com>
>-Oleksij Rempel <linux@rempel-privat.de> <o.rempel@pengutronix.de>
>-Oleksij Rempel <linux@rempel-privat.de> <ore@pengutronix.de>
>-Rajesh Shah <rajesh.shah@intel.com>
>-Ralf Baechle <ralf@linux-mips.org>
>-Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
>-Randy Dunlap <rdunlap@infradead.org> <rdunlap@xenotime.net>
>-RÃ©mi Denis-Courmont <rdenis@simphalempin.com>
>-Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
>-Ross Zwisler <zwisler@kernel.org> <ross.zwisler@linux.intel.com>
>-Rudolf Marek <R.Marek@sh.cvut.cz>
>-Rui Saraiva <rmps@joel.ist.utl.pt>
>-Sachin P Sant <ssant@in.ibm.com>
>-Sarangdhar Joshi <spjoshi@codeaurora.org>
>-Sam Ravnborg <sam@mars.ravnborg.org>
>-Santosh Shilimkar <ssantosh@kernel.org>
>-Santosh Shilimkar <santosh.shilimkar@oracle.org>
>-Sascha Hauer <s.hauer@pengutronix.de>
>-S.ÃaÄlar Onur <caglar@pardus.org.tr>
>-Sean Nyekjaer <sean@geanix.com> <sean.nyekjaer@prevas.dk>
>-Sebastian Reichel <sre@kernel.org> <sre@debian.org>
>-Sebastian Reichel <sre@kernel.org> <sebastian.reichel@collabora.co.uk>
>-Shiraz Hashim <shiraz.linux.kernel@gmail.com> <shiraz.hashim@st.com>
>-Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com>
>-Shuah Khan <shuah@kernel.org> <shuah.khan@hp.com>
>-Shuah Khan <shuah@kernel.org> <shuahkh@osg.samsung.com>
>-Shuah Khan <shuah@kernel.org> <shuah.kh@samsung.com>
>-Simon Kelley <simon@thekelleys.org.uk>
>-StÃ©phane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
>-Stephen Hemminger <shemminger@osdl.org>
>-Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
>-Subhash Jadavani <subhashj@codeaurora.org>
>-Sudeep Holla <sudeep.holla@arm.com> Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
>-Sumit Semwal <sumit.semwal@ti.com>
>-Tejun Heo <htejun@gmail.com>
>-Thomas Graf <tgraf@suug.ch>
>-Thomas Pedersen <twp@codeaurora.org>
>-Tony Luck <tony.luck@intel.com>
>-TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn>
>-TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org>
>-Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com>
>-Uwe Kleine-KÃ¶nig <ukleinek@informatik.uni-freiburg.de>
>-Uwe Kleine-KÃ¶nig <ukl@pengutronix.de>
>-Uwe Kleine-KÃ¶nig <Uwe.Kleine-Koenig@digi.com>
>-Valdis Kletnieks <Valdis.Kletnieks@vt.edu>
>-Vinod Koul <vkoul@kernel.org> <vinod.koul@intel.com>
>-Vinod Koul <vkoul@kernel.org> <vinod.koul@linux.intel.com>
>-Vinod Koul <vkoul@kernel.org> <vkoul@infradead.org>
>-Viresh Kumar <vireshk@kernel.org> <viresh.kumar@st.com>
>-Viresh Kumar <vireshk@kernel.org> <viresh.linux@gmail.com>
>-Viresh Kumar <vireshk@kernel.org> <viresh.kumar2@arm.com>
>-Vlad Dogaru <ddvlad@gmail.com> <vlad.dogaru@intel.com>
>-Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@virtuozzo.com>
>-Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@parallels.com>
>-Takashi YOSHII <takashi.yoshii.zj@renesas.com>
>-Will Deacon <will@kernel.org> <will.deacon@arm.com>
>-Yakir Yang <kuankuan.y@gmail.com> <ykk@rock-chips.com>
>-Yusuke Goda <goda.yusuke@renesas.com>
>-Gustavo Padovan <gustavo@las.ic.unicamp.br>
>-Gustavo Padovan <padovan@profusion.mobi>
>-Changbin Du <changbin.du@intel.com> <changbin.du@intel.com>
>-Changbin Du <changbin.du@intel.com> <changbin.du@gmail.com>
>diff -Naur linux-5.3-rc6/MAINTAINERS linux-5.3-rc6-agd5fed/MAINTAINERS
>--- linux-5.3-rc6/MAINTAINERS	2019-08-25 14:01:23.000000000 -0500
>+++ linux-5.3-rc6-agd5fed/MAINTAINERS	2019-08-31 15:01:12.298736207 -0500
>@@ -829,17 +829,11 @@
> F:	include/linux/amd-iommu.h
> 
> AMD KFD
>-M:	Oded Gabbay <oded.gabbay@gmail.com>
>-L:	dri-devel@lists.freedesktop.org
>-T:	git git://people.freedesktop.org/~gabbayo/linux.git
>+M:	Felix Kuehling <Felix.Kuehling@amd.com>
>+L:	amd-gfx@lists.freedesktop.org
>+T:	git git://people.freedesktop.org/~agd5f/linux
> S:	Supported
>-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
>-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
>-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
>-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
>-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c
>-F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>+F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd*.[ch]
> F:	drivers/gpu/drm/amd/amdkfd/
> F:	drivers/gpu/drm/amd/include/cik_structs.h
> F:	drivers/gpu/drm/amd/include/kgd_kfd_interface.h
>@@ -5099,17 +5093,24 @@
> F:	drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
> F:	Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.txt
> 
>+DRM DRIVER FOR GRAIN MEDIA GM12U320 PROJECTORS
>+M:	Hans de Goede <hdegoede@redhat.com>
>+T:	git git://anongit.freedesktop.org/drm/drm-misc
>+S:	Maintained
>+F:	drivers/gpu/drm/tiny/gm12u320.c
>+
> DRM DRIVER FOR ILITEK ILI9225 PANELS
> M:	David Lechner <david@lechnology.com>
>+T:	git git://anongit.freedesktop.org/drm/drm-misc
> S:	Maintained
>-F:	drivers/gpu/drm/tinydrm/ili9225.c
>+F:	drivers/gpu/drm/tiny/ili9225.c
> F:	Documentation/devicetree/bindings/display/ilitek,ili9225.txt
> 
> DRM DRIVER FOR HX8357D PANELS
> M:	Eric Anholt <eric@anholt.net>
> T:	git git://anongit.freedesktop.org/drm/drm-misc
> S:	Maintained
>-F:	drivers/gpu/drm/tinydrm/hx8357d.c
>+F:	drivers/gpu/drm/tiny/hx8357d.c
> F:	Documentation/devicetree/bindings/display/himax,hx8357d.txt
> 
> DRM DRIVER FOR INTEL I810 VIDEO CARDS
>@@ -5129,8 +5130,9 @@
> 
> DRM DRIVER FOR MI0283QT
> M:	Noralf TrÃ¸nnes <noralf@tronnes.org>
>+T:	git git://anongit.freedesktop.org/drm/drm-misc
> S:	Maintained
>-F:	drivers/gpu/drm/tinydrm/mi0283qt.c
>+F:	drivers/gpu/drm/tiny/mi0283qt.c
> F:	Documentation/devicetree/bindings/display/multi-inno,mi0283qt.txt
> 
> DRM DRIVER FOR MSM ADRENO GPU
>@@ -5162,8 +5164,9 @@
> 
> DRM DRIVER FOR PERVASIVE DISPLAYS REPAPER PANELS
> M:	Noralf TrÃ¸nnes <noralf@tronnes.org>
>+T:	git git://anongit.freedesktop.org/drm/drm-misc
> S:	Maintained
>-F:	drivers/gpu/drm/tinydrm/repaper.c
>+F:	drivers/gpu/drm/tiny/repaper.c
> F:	Documentation/devicetree/bindings/display/repaper.txt
> 
> DRM DRIVER FOR QEMU'S CIRRUS DEVICE
>@@ -5185,6 +5188,12 @@
> F:	drivers/gpu/drm/qxl/
> F:	include/uapi/drm/qxl_drm.h
> 
>+DRM DRIVER FOR RAYDIUM RM67191 PANELS
>+M:	Robert Chiras <robert.chiras@nxp.com>
>+S:	Maintained
>+F:	drivers/gpu/drm/panel/panel-raydium-rm67191.c
>+F:	Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt
>+
> DRM DRIVER FOR RAGE 128 VIDEO CARDS
> S:	Orphan / Obsolete
> F:	drivers/gpu/drm/r128/
>@@ -5192,6 +5201,7 @@
> 
> DRM DRIVER FOR ROCKTECH JH057N00900 PANELS
> M:	Guido GÃ¼nther <agx@sigxcpu.org>
>+R:	Purism Kernel Team <kernel@puri.sm>
> S:	Maintained
> F:	drivers/gpu/drm/panel/panel-rocktech-jh057n00900.c
> F:	Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.txt
>@@ -5214,14 +5224,16 @@
> 
> DRM DRIVER FOR SITRONIX ST7586 PANELS
> M:	David Lechner <david@lechnology.com>
>+T:	git git://anongit.freedesktop.org/drm/drm-misc
> S:	Maintained
>-F:	drivers/gpu/drm/tinydrm/st7586.c
>+F:	drivers/gpu/drm/tiny/st7586.c
> F:	Documentation/devicetree/bindings/display/sitronix,st7586.txt
> 
> DRM DRIVER FOR SITRONIX ST7735R PANELS
> M:	David Lechner <david@lechnology.com>
>+T:	git git://anongit.freedesktop.org/drm/drm-misc
> S:	Maintained
>-F:	drivers/gpu/drm/tinydrm/st7735r.c
>+F:	drivers/gpu/drm/tiny/st7735r.c
> F:	Documentation/devicetree/bindings/display/sitronix,st7735r.txt
> 
> DRM DRIVER FOR ST-ERICSSON MCDE
>@@ -5240,7 +5252,7 @@
> T:	git git://anongit.freedesktop.org/drm/drm-misc
> S:	Maintained
> F:	drivers/gpu/drm/panel/panel-tpo-tpg110.c
>-F:	Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt
>+F:	Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml
> 
> DRM DRIVER FOR USB DISPLAYLINK VIDEO ADAPTERS
> M:	Dave Airlie <airlied@redhat.com>
>@@ -5328,6 +5340,7 @@
> T:	git git://anongit.freedesktop.org/drm/drm-misc
> 
> DRM DRIVERS FOR ATMEL HLCDC
>+M:	Sam Ravnborg <sam@ravnborg.org>
> M:	Boris Brezillon <bbrezillon@kernel.org>
> L:	dri-devel@lists.freedesktop.org
> S:	Supported
>@@ -5337,7 +5350,10 @@
> 
> DRM DRIVERS FOR BRIDGE CHIPS
> M:	Andrzej Hajda <a.hajda@samsung.com>
>+M:	Neil Armstrong <narmstrong@baylibre.com>
> R:	Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
>+R:	Jonas Karlman <jonas@kwiboo.se>
>+R:	Jernej Skrabec <jernej.skrabec@siol.net>
> S:	Maintained
> T:	git git://anongit.freedesktop.org/drm/drm-misc
> F:	drivers/gpu/drm/bridge/
>@@ -5525,14 +5541,6 @@
> F:	include/drm/drm_panel.h
> F:	Documentation/devicetree/bindings/display/panel/
> 
>-DRM TINYDRM DRIVERS
>-M:	Noralf TrÃ¸nnes <noralf@tronnes.org>
>-W:	https://github.com/notro/tinydrm/wiki/Development
>-T:	git git://anongit.freedesktop.org/drm/drm-misc
>-S:	Maintained
>-F:	drivers/gpu/drm/tinydrm/
>-F:	include/drm/tinydrm/
>-
> DRM DRIVERS FOR XEN
> M:	Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
> T:	git git://anongit.freedesktop.org/drm/drm-misc

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